diff --git a/.cproject b/.cproject
index da7e7b8..f2af946 100644
--- a/.cproject
+++ b/.cproject
@@ -1,8 +1,8 @@
 <?xml version="1.0" encoding="UTF-8" standalone="no"?>
 <?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
 	<storageModule moduleId="org.eclipse.cdt.core.settings">
-		<cconfiguration id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug.898215809">
-			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug.898215809" moduleId="org.eclipse.cdt.core.settings" name="Debug">
+		<cconfiguration id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug.200712874">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug.200712874" moduleId="org.eclipse.cdt.core.settings" name="Debug">
 				<externalSettings/>
 				<extensions>
 					<extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>
@@ -14,50 +14,55 @@
 				</extensions>
 			</storageModule>
 			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
-				<configuration artifactExtension="elf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug" cleanCommand="rm -rf" description="" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug.898215809" name="Debug" parent="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug">
-					<folderInfo id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug.898215809." name="/" resourcePath="">
-						<toolChain id="com.st.stm32cube.ide.mcu.gnu.managedbuild.toolchain.exe.debug.1359763672" name="MCU ARM GCC" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.toolchain.exe.debug">
-							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_mcu.1808020710" name="MCU" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_mcu" useByScannerDiscovery="true" value="STM32H723VGHx" valueType="string"/>
-							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_cpuid.2058343744" name="CPU" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_cpuid" useByScannerDiscovery="false" value="0" valueType="string"/>
-							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_coreid.218019030" name="Core" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_coreid" useByScannerDiscovery="false" value="0" valueType="string"/>
-							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.fpu.504326181" name="Floating-point unit" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.fpu" useByScannerDiscovery="true" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.fpu.value.fpv5-d16" valueType="enumerated"/>
-							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.floatabi.511460718" name="Floating-point ABI" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.floatabi" useByScannerDiscovery="true" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.floatabi.value.hard" valueType="enumerated"/>
-							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_board.2144228528" name="Board" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_board" useByScannerDiscovery="false" value="genericBoard" valueType="string"/>
-							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults.1547339321" name="Defaults" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults" useByScannerDiscovery="false" value="com.st.stm32cube.ide.common.services.build.inputs.revA.1.0.6 || Debug || true || Executable || com.st.stm32cube.ide.mcu.gnu.managedbuild.option.toolchain.value.workspace || STM32H723VGHx || 0 || 0 || arm-none-eabi- || ${gnu_tools_for_stm32_compiler_path} || ../Core/Inc | ../Drivers/STM32H7xx_HAL_Driver/Inc | ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy | ../Drivers/CMSIS/Device/ST/STM32H7xx/Include | ../Drivers/CMSIS/Include | ../LWIP/App | ../LWIP/Target | ../Middlewares/Third_Party/LwIP/src/include | ../Middlewares/Third_Party/LwIP/system | ../Drivers/BSP/Components/lan8742 | ../Middlewares/Third_Party/LwIP/src/include/netif/ppp | ../Middlewares/Third_Party/LwIP/src/include/lwip | ../Middlewares/Third_Party/LwIP/src/include/lwip/apps | ../Middlewares/Third_Party/LwIP/src/include/lwip/priv | ../Middlewares/Third_Party/LwIP/src/include/lwip/prot | ../Middlewares/Third_Party/LwIP/src/include/netif | ../Middlewares/Third_Party/LwIP/src/include/compat/posix | ../Middlewares/Third_Party/LwIP/src/include/compat/posix/arpa | ../Middlewares/Third_Party/LwIP/src/include/compat/posix/net | ../Middlewares/Third_Party/LwIP/src/include/compat/posix/sys | ../Middlewares/Third_Party/LwIP/src/include/compat/stdc | ../Middlewares/Third_Party/LwIP/system/arch ||  ||  || USE_HAL_DRIVER | STM32H723xx ||  || LWIP | Drivers | Core/Startup | Middlewares | Core ||  ||  || ${workspace_loc:/${ProjName}/STM32H723VGHX_FLASH.ld} || true || NonSecure ||  || secure_nsclib.o ||  || None ||  ||  || " valueType="string"/>
-							<option id="com.st.stm32cube.ide.mcu.debug.option.cpuclock.1502178389" name="Cpu clock frequence" superClass="com.st.stm32cube.ide.mcu.debug.option.cpuclock" useByScannerDiscovery="false" value="240" valueType="string"/>
-							<targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.ELF" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.targetplatform.1496296201" isAbstract="false" osList="all" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.targetplatform"/>
-							<builder buildPath="${workspace_loc:/lwip_test}/Debug" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.builder.792578881" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" parallelBuildOn="true" parallelizationNumber="optimal" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.builder"/>
-							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.1994748349" name="MCU GCC Assembler" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler">
-								<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.debuglevel.299436917" name="Debug level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.debuglevel" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.debuglevel.value.g3" valueType="enumerated"/>
-								<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.definedsymbols.293849353" name="Define symbols (-D)" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.definedsymbols" valueType="definedSymbols">
+				<configuration artifactExtension="elf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug" cleanCommand="rm -rf" description="" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug.200712874" name="Debug" parent="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug">
+					<folderInfo id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug.200712874." name="/" resourcePath="">
+						<toolChain id="com.st.stm32cube.ide.mcu.gnu.managedbuild.toolchain.exe.debug.179803774" name="MCU ARM GCC" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.toolchain.exe.debug">
+							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_mcu.425245277" name="MCU" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_mcu" useByScannerDiscovery="true" value="STM32H723VGHx" valueType="string"/>
+							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_cpuid.1271054036" name="CPU" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_cpuid" useByScannerDiscovery="false" value="0" valueType="string"/>
+							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_coreid.853196324" name="Core" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_coreid" useByScannerDiscovery="false" value="0" valueType="string"/>
+							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.fpu.2128225543" name="Floating-point unit" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.fpu" useByScannerDiscovery="true" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.fpu.value.fpv5-d16" valueType="enumerated"/>
+							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.floatabi.91021570" name="Floating-point ABI" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.floatabi" useByScannerDiscovery="true" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.floatabi.value.hard" valueType="enumerated"/>
+							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_board.295169551" name="Board" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_board" useByScannerDiscovery="false" value="genericBoard" valueType="string"/>
+							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults.1917551943" name="Defaults" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults" useByScannerDiscovery="false" value="com.st.stm32cube.ide.common.services.build.inputs.revA.1.0.6 || Debug || true || Executable || com.st.stm32cube.ide.mcu.gnu.managedbuild.option.toolchain.value.workspace || STM32H723VGHx || 0 || 0 || arm-none-eabi- || ${gnu_tools_for_stm32_compiler_path} || ../Core/Inc | ../FATFS/Target | ../FATFS/App | ../LWIP/App | ../LWIP/Target | ../Middlewares/Third_Party/LwIP/src/include | ../Middlewares/Third_Party/LwIP/system | ../Drivers/STM32H7xx_HAL_Driver/Inc | ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy | ../Middlewares/Third_Party/FreeRTOS/Source/include | ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS | ../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F | ../Middlewares/Third_Party/FatFs/src | ../Drivers/BSP/Components/lan8742 | ../Middlewares/Third_Party/LwIP/src/include/netif/ppp | ../Drivers/CMSIS/Device/ST/STM32H7xx/Include | ../Middlewares/Third_Party/LwIP/src/include/lwip | ../Middlewares/Third_Party/LwIP/src/include/lwip/apps | ../Middlewares/Third_Party/LwIP/src/include/lwip/priv | ../Middlewares/Third_Party/LwIP/src/include/lwip/prot | ../Middlewares/Third_Party/LwIP/src/include/netif | ../Middlewares/Third_Party/LwIP/src/include/compat/posix | ../Middlewares/Third_Party/LwIP/src/include/compat/posix/arpa | ../Middlewares/Third_Party/LwIP/src/include/compat/posix/net | ../Middlewares/Third_Party/LwIP/src/include/compat/posix/sys | ../Middlewares/Third_Party/LwIP/src/include/compat/stdc | ../Middlewares/Third_Party/LwIP/system/arch | ../Drivers/CMSIS/Include ||  ||  || USE_HAL_DRIVER | STM32H723xx ||  || LWIP | Drivers | Core/Startup | Middlewares | Core | FATFS ||  ||  || ${workspace_loc:/${ProjName}/STM32H723VGHX_FLASH.ld} || true || NonSecure ||  || secure_nsclib.o ||  || None ||  ||  || " valueType="string"/>
+							<option id="com.st.stm32cube.ide.mcu.debug.option.cpuclock.719972608" name="Cpu clock frequence" superClass="com.st.stm32cube.ide.mcu.debug.option.cpuclock" useByScannerDiscovery="false" value="240" valueType="string"/>
+							<targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.ELF" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.targetplatform.221020393" isAbstract="false" osList="all" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.targetplatform"/>
+							<builder buildPath="${workspace_loc:/TBD_TaxiBoard}/Debug" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.builder.1641417480" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" parallelBuildOn="true" parallelizationNumber="optimal" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.builder"/>
+							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.2074665735" name="MCU GCC Assembler" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler">
+								<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.debuglevel.928451887" name="Debug level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.debuglevel" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.debuglevel.value.g3" valueType="enumerated"/>
+								<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.definedsymbols.1230072980" name="Define symbols (-D)" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.definedsymbols" valueType="definedSymbols">
 									<listOptionValue builtIn="false" value="DEBUG"/>
 								</option>
-								<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.includepaths.35156878" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.includepaths" valueType="includePath">
-									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/LWFTP}&quot;"/>
+								<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.includepaths.1794399386" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.includepaths" valueType="includePath">
+									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/LWFTPC}&quot;"/>
 								</option>
-								<inputType id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.input.1330080033" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.input"/>
+								<inputType id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.input.424465721" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.input"/>
 							</tool>
-							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.711876895" name="MCU GCC Compiler" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler">
-								<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.debuglevel.1324897233" name="Debug level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.debuglevel" useByScannerDiscovery="false" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.debuglevel.value.g3" valueType="enumerated"/>
-								<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.optimization.level.1567493263" name="Optimization level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.optimization.level" useByScannerDiscovery="false"/>
-								<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.definedsymbols.683577075" name="Define symbols (-D)" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.definedsymbols" useByScannerDiscovery="false" valueType="definedSymbols">
+							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.237799837" name="MCU GCC Compiler" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler">
+								<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.debuglevel.131594960" name="Debug level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.debuglevel" useByScannerDiscovery="false" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.debuglevel.value.g3" valueType="enumerated"/>
+								<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.optimization.level.675835907" name="Optimization level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.optimization.level" useByScannerDiscovery="false"/>
+								<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.definedsymbols.1946395127" name="Define symbols (-D)" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.definedsymbols" useByScannerDiscovery="false" valueType="definedSymbols">
 									<listOptionValue builtIn="false" value="DEBUG"/>
 									<listOptionValue builtIn="false" value="DATA_IN_D2_SRAM"/>
 									<listOptionValue builtIn="false" value="USE_HAL_DRIVER"/>
 									<listOptionValue builtIn="false" value="STM32H723xx"/>
 								</option>
-								<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.includepaths.1738667551" name="Include paths (-I)" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.includepaths" useByScannerDiscovery="false" valueType="includePath">
+								<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.includepaths.1741302430" name="Include paths (-I)" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.includepaths" useByScannerDiscovery="false" valueType="includePath">
 									<listOptionValue builtIn="false" value="../Core/Inc"/>
-									<listOptionValue builtIn="false" value="../Drivers/STM32H7xx_HAL_Driver/Inc"/>
-									<listOptionValue builtIn="false" value="../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy"/>
-									<listOptionValue builtIn="false" value="../Drivers/CMSIS/Device/ST/STM32H7xx/Include"/>
-									<listOptionValue builtIn="false" value="../Drivers/CMSIS/Include"/>
+									<listOptionValue builtIn="false" value="../FATFS/Target"/>
+									<listOptionValue builtIn="false" value="../FATFS/App"/>
 									<listOptionValue builtIn="false" value="../LWIP/App"/>
 									<listOptionValue builtIn="false" value="../LWIP/Target"/>
 									<listOptionValue builtIn="false" value="../Middlewares/Third_Party/LwIP/src/include"/>
 									<listOptionValue builtIn="false" value="../Middlewares/Third_Party/LwIP/system"/>
+									<listOptionValue builtIn="false" value="../Drivers/STM32H7xx_HAL_Driver/Inc"/>
+									<listOptionValue builtIn="false" value="../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy"/>
+									<listOptionValue builtIn="false" value="../Middlewares/Third_Party/FreeRTOS/Source/include"/>
+									<listOptionValue builtIn="false" value="../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS"/>
+									<listOptionValue builtIn="false" value="../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F"/>
+									<listOptionValue builtIn="false" value="../Middlewares/Third_Party/FatFs/src"/>
 									<listOptionValue builtIn="false" value="../Drivers/BSP/Components/lan8742"/>
 									<listOptionValue builtIn="false" value="../Middlewares/Third_Party/LwIP/src/include/netif/ppp"/>
+									<listOptionValue builtIn="false" value="../Drivers/CMSIS/Device/ST/STM32H7xx/Include"/>
 									<listOptionValue builtIn="false" value="../Middlewares/Third_Party/LwIP/src/include/lwip"/>
 									<listOptionValue builtIn="false" value="../Middlewares/Third_Party/LwIP/src/include/lwip/apps"/>
 									<listOptionValue builtIn="false" value="../Middlewares/Third_Party/LwIP/src/include/lwip/priv"/>
@@ -69,45 +74,47 @@
 									<listOptionValue builtIn="false" value="../Middlewares/Third_Party/LwIP/src/include/compat/posix/sys"/>
 									<listOptionValue builtIn="false" value="../Middlewares/Third_Party/LwIP/src/include/compat/stdc"/>
 									<listOptionValue builtIn="false" value="../Middlewares/Third_Party/LwIP/system/arch"/>
-									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/LWFTP}&quot;"/>
+									<listOptionValue builtIn="false" value="../Drivers/CMSIS/Include"/>
+									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/LWFTPC}&quot;"/>
 								</option>
-								<inputType id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.input.c.1418551688" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.input.c"/>
+								<inputType id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.input.c.1730559324" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.input.c"/>
 							</tool>
-							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.213932277" name="MCU G++ Compiler" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler">
-								<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.debuglevel.472991539" name="Debug level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.debuglevel" useByScannerDiscovery="false" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.debuglevel.value.g3" valueType="enumerated"/>
-								<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.optimization.level.1248930872" name="Optimization level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.optimization.level" useByScannerDiscovery="false"/>
+							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.1012117950" name="MCU G++ Compiler" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler">
+								<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.debuglevel.879458417" name="Debug level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.debuglevel" useByScannerDiscovery="false" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.debuglevel.value.g3" valueType="enumerated"/>
+								<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.optimization.level.197701888" name="Optimization level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.optimization.level" useByScannerDiscovery="false"/>
 							</tool>
-							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.1471597049" name="MCU GCC Linker" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker">
-								<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.option.script.1661177702" name="Linker Script (-T)" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.option.script" value="${workspace_loc:/${ProjName}/STM32H723VGHX_FLASH.ld}" valueType="string"/>
-								<inputType id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.input.1647407186" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.input">
+							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.1268662126" name="MCU GCC Linker" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker">
+								<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.option.script.2029888219" name="Linker Script (-T)" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.option.script" value="${workspace_loc:/${ProjName}/STM32H723VGHX_FLASH.ld}" valueType="string"/>
+								<inputType id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.input.1542948044" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.input">
 									<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
 									<additionalInput kind="additionalinput" paths="$(LIBS)"/>
 								</inputType>
 							</tool>
-							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.linker.1190952825" name="MCU G++ Linker" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.linker"/>
-							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.archiver.287363462" name="MCU GCC Archiver" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.archiver"/>
-							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.size.863304282" name="MCU Size" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.size"/>
-							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objdump.listfile.788957648" name="MCU Output Converter list file" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objdump.listfile"/>
-							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.hex.369001341" name="MCU Output Converter Hex" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.hex"/>
-							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.binary.2101989112" name="MCU Output Converter Binary" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.binary"/>
-							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.verilog.1194821342" name="MCU Output Converter Verilog" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.verilog"/>
-							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.srec.1633374972" name="MCU Output Converter Motorola S-rec" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.srec"/>
-							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.symbolsrec.786517133" name="MCU Output Converter Motorola S-rec with symbols" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.symbolsrec"/>
+							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.linker.1917636107" name="MCU G++ Linker" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.linker"/>
+							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.archiver.1258646509" name="MCU GCC Archiver" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.archiver"/>
+							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.size.681520180" name="MCU Size" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.size"/>
+							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objdump.listfile.165356093" name="MCU Output Converter list file" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objdump.listfile"/>
+							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.hex.964634046" name="MCU Output Converter Hex" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.hex"/>
+							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.binary.1432578511" name="MCU Output Converter Binary" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.binary"/>
+							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.verilog.984812446" name="MCU Output Converter Verilog" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.verilog"/>
+							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.srec.1772136941" name="MCU Output Converter Motorola S-rec" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.srec"/>
+							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.symbolsrec.1725739372" name="MCU Output Converter Motorola S-rec with symbols" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.symbolsrec"/>
 						</toolChain>
 					</folderInfo>
 					<sourceEntries>
 						<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Core"/>
-						<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Drivers"/>
-						<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="LWFTP"/>
+						<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="FATFS"/>
+						<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="LWFTPC"/>
 						<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="LWIP"/>
 						<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Middlewares"/>
+						<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Drivers"/>
 					</sourceEntries>
 				</configuration>
 			</storageModule>
 			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
 		</cconfiguration>
-		<cconfiguration id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.release.239570574">
-			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.release.239570574" moduleId="org.eclipse.cdt.core.settings" name="Release">
+		<cconfiguration id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.release.317158393">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.release.317158393" moduleId="org.eclipse.cdt.core.settings" name="Release">
 				<externalSettings/>
 				<extensions>
 					<extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>
@@ -119,45 +126,50 @@
 				</extensions>
 			</storageModule>
 			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
-				<configuration artifactExtension="elf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.release" cleanCommand="rm -rf" description="" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.release.239570574" name="Release" parent="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.release">
-					<folderInfo id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.release.239570574." name="/" resourcePath="">
-						<toolChain id="com.st.stm32cube.ide.mcu.gnu.managedbuild.toolchain.exe.release.222865020" name="MCU ARM GCC" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.toolchain.exe.release">
-							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_mcu.1813745990" name="MCU" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_mcu" useByScannerDiscovery="true" value="STM32H723VGHx" valueType="string"/>
-							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_cpuid.2145124287" name="CPU" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_cpuid" useByScannerDiscovery="false" value="0" valueType="string"/>
-							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_coreid.1855625784" name="Core" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_coreid" useByScannerDiscovery="false" value="0" valueType="string"/>
-							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.fpu.487312692" name="Floating-point unit" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.fpu" useByScannerDiscovery="true" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.fpu.value.fpv5-d16" valueType="enumerated"/>
-							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.floatabi.59108539" name="Floating-point ABI" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.floatabi" useByScannerDiscovery="true" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.floatabi.value.hard" valueType="enumerated"/>
-							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_board.1094597058" name="Board" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_board" useByScannerDiscovery="false" value="genericBoard" valueType="string"/>
-							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults.2066006424" name="Defaults" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults" useByScannerDiscovery="false" value="com.st.stm32cube.ide.common.services.build.inputs.revA.1.0.6 || Release || false || Executable || com.st.stm32cube.ide.mcu.gnu.managedbuild.option.toolchain.value.workspace || STM32H723VGHx || 0 || 0 || arm-none-eabi- || ${gnu_tools_for_stm32_compiler_path} || ../Core/Inc | ../Drivers/STM32H7xx_HAL_Driver/Inc | ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy | ../Drivers/CMSIS/Device/ST/STM32H7xx/Include | ../Drivers/CMSIS/Include | ../LWIP/App | ../LWIP/Target | ../Middlewares/Third_Party/LwIP/src/include | ../Middlewares/Third_Party/LwIP/system | ../Drivers/BSP/Components/lan8742 | ../Middlewares/Third_Party/LwIP/src/include/netif/ppp | ../Middlewares/Third_Party/LwIP/src/include/lwip | ../Middlewares/Third_Party/LwIP/src/include/lwip/apps | ../Middlewares/Third_Party/LwIP/src/include/lwip/priv | ../Middlewares/Third_Party/LwIP/src/include/lwip/prot | ../Middlewares/Third_Party/LwIP/src/include/netif | ../Middlewares/Third_Party/LwIP/src/include/compat/posix | ../Middlewares/Third_Party/LwIP/src/include/compat/posix/arpa | ../Middlewares/Third_Party/LwIP/src/include/compat/posix/net | ../Middlewares/Third_Party/LwIP/src/include/compat/posix/sys | ../Middlewares/Third_Party/LwIP/src/include/compat/stdc | ../Middlewares/Third_Party/LwIP/system/arch ||  ||  || USE_HAL_DRIVER | STM32H723xx ||  || LWIP | Drivers | Core/Startup | Middlewares | Core ||  ||  || ${workspace_loc:/${ProjName}/STM32H723VGHX_FLASH.ld} || true || NonSecure ||  || secure_nsclib.o ||  || None ||  ||  || " valueType="string"/>
-							<option id="com.st.stm32cube.ide.mcu.debug.option.cpuclock.775505162" name="Cpu clock frequence" superClass="com.st.stm32cube.ide.mcu.debug.option.cpuclock" useByScannerDiscovery="false" value="240" valueType="string"/>
-							<targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.ELF" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.targetplatform.1900970290" isAbstract="false" osList="all" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.targetplatform"/>
-							<builder buildPath="${workspace_loc:/lwip_test}/Release" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.builder.684602021" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" parallelBuildOn="true" parallelizationNumber="optimal" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.builder"/>
-							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.670064919" name="MCU GCC Assembler" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler">
-								<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.debuglevel.1009497809" name="Debug level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.debuglevel" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.debuglevel.value.g0" valueType="enumerated"/>
-								<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.includepaths.1582624697" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.includepaths" valueType="includePath">
-									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/LWFTP}&quot;"/>
+				<configuration artifactExtension="elf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.release" cleanCommand="rm -rf" description="" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.release.317158393" name="Release" parent="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.release">
+					<folderInfo id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.release.317158393." name="/" resourcePath="">
+						<toolChain id="com.st.stm32cube.ide.mcu.gnu.managedbuild.toolchain.exe.release.518342827" name="MCU ARM GCC" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.toolchain.exe.release">
+							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_mcu.1063038313" name="MCU" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_mcu" useByScannerDiscovery="true" value="STM32H723VGHx" valueType="string"/>
+							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_cpuid.1847054803" name="CPU" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_cpuid" useByScannerDiscovery="false" value="0" valueType="string"/>
+							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_coreid.296878444" name="Core" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_coreid" useByScannerDiscovery="false" value="0" valueType="string"/>
+							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.fpu.1238929446" name="Floating-point unit" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.fpu" useByScannerDiscovery="true" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.fpu.value.fpv5-d16" valueType="enumerated"/>
+							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.floatabi.1890639815" name="Floating-point ABI" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.floatabi" useByScannerDiscovery="true" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.floatabi.value.hard" valueType="enumerated"/>
+							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_board.28022207" name="Board" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_board" useByScannerDiscovery="false" value="genericBoard" valueType="string"/>
+							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults.1219144911" name="Defaults" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults" useByScannerDiscovery="false" value="com.st.stm32cube.ide.common.services.build.inputs.revA.1.0.6 || Release || false || Executable || com.st.stm32cube.ide.mcu.gnu.managedbuild.option.toolchain.value.workspace || STM32H723VGHx || 0 || 0 || arm-none-eabi- || ${gnu_tools_for_stm32_compiler_path} || ../Core/Inc | ../FATFS/Target | ../FATFS/App | ../LWIP/App | ../LWIP/Target | ../Middlewares/Third_Party/LwIP/src/include | ../Middlewares/Third_Party/LwIP/system | ../Drivers/STM32H7xx_HAL_Driver/Inc | ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy | ../Middlewares/Third_Party/FreeRTOS/Source/include | ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS | ../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F | ../Middlewares/Third_Party/FatFs/src | ../Drivers/BSP/Components/lan8742 | ../Middlewares/Third_Party/LwIP/src/include/netif/ppp | ../Drivers/CMSIS/Device/ST/STM32H7xx/Include | ../Middlewares/Third_Party/LwIP/src/include/lwip | ../Middlewares/Third_Party/LwIP/src/include/lwip/apps | ../Middlewares/Third_Party/LwIP/src/include/lwip/priv | ../Middlewares/Third_Party/LwIP/src/include/lwip/prot | ../Middlewares/Third_Party/LwIP/src/include/netif | ../Middlewares/Third_Party/LwIP/src/include/compat/posix | ../Middlewares/Third_Party/LwIP/src/include/compat/posix/arpa | ../Middlewares/Third_Party/LwIP/src/include/compat/posix/net | ../Middlewares/Third_Party/LwIP/src/include/compat/posix/sys | ../Middlewares/Third_Party/LwIP/src/include/compat/stdc | ../Middlewares/Third_Party/LwIP/system/arch | ../Drivers/CMSIS/Include ||  ||  || USE_HAL_DRIVER | STM32H723xx ||  || LWIP | Drivers | Core/Startup | Middlewares | Core | FATFS ||  ||  || ${workspace_loc:/${ProjName}/STM32H723VGHX_FLASH.ld} || true || NonSecure ||  || secure_nsclib.o ||  || None ||  ||  || " valueType="string"/>
+							<option id="com.st.stm32cube.ide.mcu.debug.option.cpuclock.2077132147" name="Cpu clock frequence" superClass="com.st.stm32cube.ide.mcu.debug.option.cpuclock" useByScannerDiscovery="false" value="240" valueType="string"/>
+							<targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.ELF" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.targetplatform.480984217" isAbstract="false" osList="all" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.targetplatform"/>
+							<builder buildPath="${workspace_loc:/TBD_TaxiBoard}/Release" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.builder.1603900554" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" parallelBuildOn="true" parallelizationNumber="optimal" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.builder"/>
+							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.806151474" name="MCU GCC Assembler" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler">
+								<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.debuglevel.897709490" name="Debug level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.debuglevel" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.debuglevel.value.g0" valueType="enumerated"/>
+								<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.includepaths.1257872596" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.includepaths" valueType="includePath">
+									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/LWFTPC}&quot;"/>
 								</option>
-								<inputType id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.input.570425922" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.input"/>
+								<inputType id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.input.1812707677" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.input"/>
 							</tool>
-							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.904964404" name="MCU GCC Compiler" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler">
-								<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.debuglevel.1802375991" name="Debug level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.debuglevel" useByScannerDiscovery="false" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.debuglevel.value.g0" valueType="enumerated"/>
-								<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.optimization.level.1148488985" name="Optimization level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.optimization.level" useByScannerDiscovery="false" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.optimization.level.value.os" valueType="enumerated"/>
-								<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.definedsymbols.1361588527" name="Define symbols (-D)" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.definedsymbols" useByScannerDiscovery="false" valueType="definedSymbols">
+							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.1120406180" name="MCU GCC Compiler" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler">
+								<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.debuglevel.364024979" name="Debug level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.debuglevel" useByScannerDiscovery="false" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.debuglevel.value.g0" valueType="enumerated"/>
+								<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.optimization.level.295437681" name="Optimization level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.optimization.level" useByScannerDiscovery="false" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.optimization.level.value.os" valueType="enumerated"/>
+								<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.definedsymbols.2131195825" name="Define symbols (-D)" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.definedsymbols" useByScannerDiscovery="false" valueType="definedSymbols">
 									<listOptionValue builtIn="false" value="USE_HAL_DRIVER"/>
 									<listOptionValue builtIn="false" value="STM32H723xx"/>
 								</option>
-								<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.includepaths.282609781" name="Include paths (-I)" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.includepaths" useByScannerDiscovery="false" valueType="includePath">
+								<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.includepaths.1363705572" name="Include paths (-I)" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.includepaths" useByScannerDiscovery="false" valueType="includePath">
 									<listOptionValue builtIn="false" value="../Core/Inc"/>
-									<listOptionValue builtIn="false" value="../Drivers/STM32H7xx_HAL_Driver/Inc"/>
-									<listOptionValue builtIn="false" value="../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy"/>
-									<listOptionValue builtIn="false" value="../Drivers/CMSIS/Device/ST/STM32H7xx/Include"/>
-									<listOptionValue builtIn="false" value="../Drivers/CMSIS/Include"/>
+									<listOptionValue builtIn="false" value="../FATFS/Target"/>
+									<listOptionValue builtIn="false" value="../FATFS/App"/>
 									<listOptionValue builtIn="false" value="../LWIP/App"/>
 									<listOptionValue builtIn="false" value="../LWIP/Target"/>
 									<listOptionValue builtIn="false" value="../Middlewares/Third_Party/LwIP/src/include"/>
 									<listOptionValue builtIn="false" value="../Middlewares/Third_Party/LwIP/system"/>
+									<listOptionValue builtIn="false" value="../Drivers/STM32H7xx_HAL_Driver/Inc"/>
+									<listOptionValue builtIn="false" value="../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy"/>
+									<listOptionValue builtIn="false" value="../Middlewares/Third_Party/FreeRTOS/Source/include"/>
+									<listOptionValue builtIn="false" value="../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS"/>
+									<listOptionValue builtIn="false" value="../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F"/>
+									<listOptionValue builtIn="false" value="../Middlewares/Third_Party/FatFs/src"/>
 									<listOptionValue builtIn="false" value="../Drivers/BSP/Components/lan8742"/>
 									<listOptionValue builtIn="false" value="../Middlewares/Third_Party/LwIP/src/include/netif/ppp"/>
+									<listOptionValue builtIn="false" value="../Drivers/CMSIS/Device/ST/STM32H7xx/Include"/>
 									<listOptionValue builtIn="false" value="../Middlewares/Third_Party/LwIP/src/include/lwip"/>
 									<listOptionValue builtIn="false" value="../Middlewares/Third_Party/LwIP/src/include/lwip/apps"/>
 									<listOptionValue builtIn="false" value="../Middlewares/Third_Party/LwIP/src/include/lwip/priv"/>
@@ -169,38 +181,40 @@
 									<listOptionValue builtIn="false" value="../Middlewares/Third_Party/LwIP/src/include/compat/posix/sys"/>
 									<listOptionValue builtIn="false" value="../Middlewares/Third_Party/LwIP/src/include/compat/stdc"/>
 									<listOptionValue builtIn="false" value="../Middlewares/Third_Party/LwIP/system/arch"/>
-									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/LWFTP}&quot;"/>
+									<listOptionValue builtIn="false" value="../Drivers/CMSIS/Include"/>
+									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/LWFTPC}&quot;"/>
 								</option>
-								<inputType id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.input.c.187259766" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.input.c"/>
+								<inputType id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.input.c.298630775" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.input.c"/>
 							</tool>
-							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.977271107" name="MCU G++ Compiler" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler">
-								<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.debuglevel.1246329318" name="Debug level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.debuglevel" useByScannerDiscovery="false" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.debuglevel.value.g0" valueType="enumerated"/>
-								<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.optimization.level.184728820" name="Optimization level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.optimization.level" useByScannerDiscovery="false" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.optimization.level.value.os" valueType="enumerated"/>
+							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.7463343" name="MCU G++ Compiler" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler">
+								<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.debuglevel.988891726" name="Debug level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.debuglevel" useByScannerDiscovery="false" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.debuglevel.value.g0" valueType="enumerated"/>
+								<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.optimization.level.361401006" name="Optimization level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.optimization.level" useByScannerDiscovery="false" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.optimization.level.value.os" valueType="enumerated"/>
 							</tool>
-							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.1121264579" name="MCU GCC Linker" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker">
-								<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.option.script.128143365" name="Linker Script (-T)" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.option.script" value="${workspace_loc:/${ProjName}/STM32H723VGHX_FLASH.ld}" valueType="string"/>
-								<inputType id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.input.2112765906" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.input">
+							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.1327319518" name="MCU GCC Linker" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker">
+								<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.option.script.1193604718" name="Linker Script (-T)" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.option.script" value="${workspace_loc:/${ProjName}/STM32H723VGHX_FLASH.ld}" valueType="string"/>
+								<inputType id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.input.993880947" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.input">
 									<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
 									<additionalInput kind="additionalinput" paths="$(LIBS)"/>
 								</inputType>
 							</tool>
-							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.linker.20115037" name="MCU G++ Linker" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.linker"/>
-							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.archiver.2060517745" name="MCU GCC Archiver" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.archiver"/>
-							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.size.583850711" name="MCU Size" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.size"/>
-							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objdump.listfile.1215021180" name="MCU Output Converter list file" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objdump.listfile"/>
-							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.hex.1152309887" name="MCU Output Converter Hex" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.hex"/>
-							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.binary.733343606" name="MCU Output Converter Binary" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.binary"/>
-							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.verilog.407882950" name="MCU Output Converter Verilog" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.verilog"/>
-							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.srec.1437787529" name="MCU Output Converter Motorola S-rec" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.srec"/>
-							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.symbolsrec.700016927" name="MCU Output Converter Motorola S-rec with symbols" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.symbolsrec"/>
+							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.linker.627880677" name="MCU G++ Linker" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.linker"/>
+							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.archiver.865806349" name="MCU GCC Archiver" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.archiver"/>
+							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.size.1619843907" name="MCU Size" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.size"/>
+							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objdump.listfile.516020754" name="MCU Output Converter list file" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objdump.listfile"/>
+							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.hex.789717513" name="MCU Output Converter Hex" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.hex"/>
+							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.binary.1153428400" name="MCU Output Converter Binary" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.binary"/>
+							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.verilog.1457016313" name="MCU Output Converter Verilog" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.verilog"/>
+							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.srec.853053440" name="MCU Output Converter Motorola S-rec" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.srec"/>
+							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.symbolsrec.1430474332" name="MCU Output Converter Motorola S-rec with symbols" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.symbolsrec"/>
 						</toolChain>
 					</folderInfo>
 					<sourceEntries>
 						<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Core"/>
-						<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Drivers"/>
-						<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="LWFTP"/>
+						<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="FATFS"/>
+						<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="LWFTPC"/>
 						<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="LWIP"/>
 						<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Middlewares"/>
+						<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Drivers"/>
 					</sourceEntries>
 				</configuration>
 			</storageModule>
@@ -209,25 +223,18 @@
 	</storageModule>
 	<storageModule moduleId="org.eclipse.cdt.core.pathentry"/>
 	<storageModule moduleId="cdtBuildSystem" version="4.0.0">
-		<project id="lwip_test.null.1676740300" name="lwip_test"/>
+		<project id="TBD_TaxiBoard.null.2032358461" name="TBD_TaxiBoard"/>
 	</storageModule>
 	<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
 	<storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/>
 	<storageModule moduleId="scannerConfiguration">
 		<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
-		<scannerConfigBuildInfo instanceId="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.release.239570574;com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.release.239570574.;com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.904964404;com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.input.c.187259766">
+		<scannerConfigBuildInfo instanceId="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.release.317158393;com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.release.317158393.;com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.1120406180;com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.input.c.298630775">
 			<autodiscovery enabled="false" problemReportingEnabled="true" selectedProfileId=""/>
 		</scannerConfigBuildInfo>
-		<scannerConfigBuildInfo instanceId="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug.898215809;com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug.898215809.;com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.711876895;com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.input.c.1418551688">
+		<scannerConfigBuildInfo instanceId="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug.200712874;com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug.200712874.;com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.237799837;com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.input.c.1730559324">
 			<autodiscovery enabled="false" problemReportingEnabled="true" selectedProfileId=""/>
 		</scannerConfigBuildInfo>
 	</storageModule>
-	<storageModule moduleId="refreshScope" versionNumber="2">
-		<configuration configurationName="Debug">
-			<resource resourceType="PROJECT" workspacePath="/lwip_test"/>
-		</configuration>
-		<configuration configurationName="Release">
-			<resource resourceType="PROJECT" workspacePath="/lwip_test"/>
-		</configuration>
-	</storageModule>
+	<storageModule moduleId="refreshScope"/>
 </cproject>
\ No newline at end of file
diff --git a/.mxproject b/.mxproject
index 9965b9f..db77c3a 100644
--- a/.mxproject
+++ b/.mxproject
@@ -1,34 +1,50 @@
 [PreviousLibFiles]
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netif\ppp\utils.c;Middlewares\Third_Party\LwIP\src\netif\ppp\vj.c;Middlewares\Third_Party\LwIP\src\netif\bridgeif.c;Middlewares\Third_Party\LwIP\src\netif\bridgeif_fdb.c;Middlewares\Third_Party\LwIP\src\netif\ethernet.c;Middlewares\Third_Party\LwIP\src\netif\lowpan6.c;Middlewares\Third_Party\LwIP\src\netif\lowpan6_ble.c;Middlewares\Third_Party\LwIP\src\netif\lowpan6_common.c;Middlewares\Third_Party\LwIP\src\netif\slipif.c;Middlewares\Third_Party\LwIP\src\netif\zepif.c;Middlewares\Third_Party\LwIP\src\netif\ppp\ecp.c;Middlewares\Third_Party\LwIP\src\api\api_lib.c;Middlewares\Third_Party\LwIP\src\api\api_msg.c;Middlewares\Third_Party\LwIP\src\api\err.c;Middlewares\Third_Party\LwIP\src\api\if_api.c;Middlewares\Third_Party\LwIP\src\api\netbuf.c;Middlewares\Third_Party\LwIP\src\api\netdb.c;Middlewares\Third_Party\LwIP\src\api\netifapi.c;Middlewares\Third_Party\LwIP\src\api\sockets.c;Middlewares\Third_Party\LwIP\src\api\tcpip.c;Middlewares\Third_Party\LwIP\src\core\altcp.c;Middlewares\Third_Party\LwIP\src\core\altcp_alloc.c;Middlewares\Third_Party\LwIP\src\core\altcp_tcp.c;Middlewares\Third_Party\LwIP\src\core\def.c;Middlewares\Third_Party\LwIP\src\core\dns.c;Middlewares\Third_Party\LwIP\src\core\inet_chksum.c;Middlewares\Third_Party\LwIP\src\core\init.c;Middlewares\Third_Party\LwIP\src\core\ip.c;Middlewares\Third_Party\LwIP\src\core\mem.c;Middlewares\Third_Party\LwIP\src\core\memp.c;Middlewares\Third_Party\LwIP\src\core\netif.c;Middlewares\Third_Party\LwIP\src\core\pbuf.c;Middlewares\Third_Party\LwIP\src\core\raw.c;Middlewares\Third_Party\LwIP\src\core\stats.c;Middlewares\Third_Party\LwIP\src\core\sys.c;Middlewares\Third_Party\LwIP\src\core\tcp.c;Middlewares\Third_Party\LwIP\src\core\tcp_in.c;Middlewares\Third_Party\LwIP\src\core\tcp_out.c;Middlewares\Third_Party\LwIP\src\core\timeouts.c;Middlewares\Third_Party\LwIP\src\core\udp.c;Middlewares\Third_Party\LwIP\src\core\ipv4\autoip.c;Middlewares\Third_Party\LwIP\src\core\ipv4\dhcp.c;Middlewares\Third_Party\LwIP\src\core\ipv4\etharp.c;Middlewares\Third_Party\LwIP\src\core\ipv4\icmp.c;Middlewares\Third_Party\LwIP\src\core\ipv4\igmp.c;Middlewares\Third_Party\LwIP\src\core\ipv4\ip4.c;Middlewares\Third_Party\LwIP\src\core\ipv4\ip4_addr.c;Middlewares\Third_Party\LwIP\src\core\ipv4\ip4_frag.c;Middlewares\Third_Party\LwIP\src\core\ipv6\dhcp6.c;Middlewares\Third_Party\LwIP\src\core\ipv6\ethip6.c;Middlewares\Third_Party\LwIP\src\core\ipv6\icmp6.c;Middlewares\Third_Party\LwIP\src\core\ipv6\inet6.c;Middlewares\Third_Party\LwIP\src\core\ipv6\ip6.c;Middlewares\Third_Party\LwIP\src\core\ipv6\ip6_addr.c;Middlewares\Third_Party\LwIP\src\core\ipv6\ip6_frag.c;Middlewares\Third_Party\LwIP\src\core\ipv6\mld6.c;Middlewares\Third_Party\LwIP\src\core\ipv6\nd6.c;Middlewares\Third_Party\LwIP\system\OS\sys_arch.c;Middlewares\Third_Party\LwIP\src\apps\mqtt\mqtt.c;
+HeaderPath=Middlewares\Third_Party\LwIP\src\include;Middlewares\Third_Party\LwIP\system;Middlewares\Third_Party\LwIP\src\include;Middlewares\Third_Party\LwIP\system;Drivers\STM32H7xx_HAL_Driver\Inc;Drivers\STM32H7xx_HAL_Driver\Inc\Legacy;Middlewares\Third_Party\FreeRTOS\Source\include;Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS;Middlewares\Third_Party\FreeRTOS\Source\portable\GCC\ARM_CM4F;Middlewares\Third_Party\FatFs\src;Drivers\BSP\Components\lan8742;Middlewares\Third_Party\LwIP\src\include\netif\ppp;Drivers\CMSIS\Device\ST\STM32H7xx\Include;Middlewares\Third_Party\LwIP\src\include\lwip;Middlewares\Third_Party\LwIP\src\include\lwip\apps;Middlewares\Third_Party\LwIP\src\include\lwip\priv;Middlewares\Third_Party\LwIP\src\include\lwip\prot;Middlewares\Third_Party\LwIP\src\include\netif;Middlewares\Third_Party\LwIP\src\include\compat\posix;Middlewares\Third_Party\LwIP\src\include\compat\posix\arpa;Middlewares\Third_Party\LwIP\src\include\compat\posix\net;Middlewares\Third_Party\LwIP\src\include\compat\posix\sys;Middlewares\Third_Party\LwIP\src\include\compat\stdc;Middlewares\Third_Party\LwIP\system\arch;Drivers\CMSIS\Include;Core\Inc;FATFS\Target;FATFS\App;LWIP\App;LWIP\Target;
 CDefines=USE_HAL_DRIVER;STM32H723xx;USE_HAL_DRIVER;USE_HAL_DRIVER;
 
 [PreviousGenFiles]
 AdvancedFolderStructure=true
-HeaderFileListSize=6
-HeaderFiles#0=..\LWIP\App\lwip.h
-HeaderFiles#1=..\LWIP\Target\lwipopts.h
-HeaderFiles#2=..\LWIP\Target\ethernetif.h
-HeaderFiles#3=..\Core\Inc\stm32h7xx_it.h
-HeaderFiles#4=..\Core\Inc\stm32h7xx_hal_conf.h
-HeaderFiles#5=..\Core\Inc\main.h
-HeaderFolderListSize=3
-HeaderPath#0=..\LWIP\App
-HeaderPath#1=..\LWIP\Target
-HeaderPath#2=..\Core\Inc
+HeaderFileListSize=12
+HeaderFiles#0=..\Core\Inc\FreeRTOSConfig.h
+HeaderFiles#1=..\FATFS\Target\ffconf.h
+HeaderFiles#2=..\FATFS\Target\bsp_driver_sd.h
+HeaderFiles#3=..\FATFS\Target\sd_diskio.h
+HeaderFiles#4=..\FATFS\App\fatfs.h
+HeaderFiles#5=..\FATFS\Target\fatfs_platform.h
+HeaderFiles#6=..\LWIP\App\lwip.h
+HeaderFiles#7=..\LWIP\Target\lwipopts.h
+HeaderFiles#8=..\LWIP\Target\ethernetif.h
+HeaderFiles#9=..\Core\Inc\stm32h7xx_it.h
+HeaderFiles#10=..\Core\Inc\stm32h7xx_hal_conf.h
+HeaderFiles#11=..\Core\Inc\main.h
+HeaderFolderListSize=5
+HeaderPath#0=..\Core\Inc
+HeaderPath#1=..\FATFS\Target
+HeaderPath#2=..\FATFS\App
+HeaderPath#3=..\LWIP\App
+HeaderPath#4=..\LWIP\Target
 HeaderFiles=;
-SourceFileListSize=5
-SourceFiles#0=..\LWIP\App\lwip.c
-SourceFiles#1=..\LWIP\Target\ethernetif.c
-SourceFiles#2=..\Core\Src\stm32h7xx_it.c
-SourceFiles#3=..\Core\Src\stm32h7xx_hal_msp.c
-SourceFiles#4=..\Core\Src\main.c
-SourceFolderListSize=3
-SourcePath#0=..\LWIP\App
-SourcePath#1=..\LWIP\Target
-SourcePath#2=..\Core\Src
+SourceFileListSize=11
+SourceFiles#0=..\Core\Src\freertos.c
+SourceFiles#1=..\FATFS\Target\bsp_driver_sd.c
+SourceFiles#2=..\FATFS\Target\sd_diskio.c
+SourceFiles#3=..\FATFS\App\fatfs.c
+SourceFiles#4=..\FATFS\Target\fatfs_platform.c
+SourceFiles#5=..\LWIP\App\lwip.c
+SourceFiles#6=..\LWIP\Target\ethernetif.c
+SourceFiles#7=..\Core\Src\stm32h7xx_it.c
+SourceFiles#8=..\Core\Src\stm32h7xx_hal_msp.c
+SourceFiles#9=..\Core\Src\stm32h7xx_hal_timebase_tim.c
+SourceFiles#10=..\Core\Src\main.c
+SourceFolderListSize=5
+SourcePath#0=..\Core\Src
+SourcePath#1=..\FATFS\Target
+SourcePath#2=..\FATFS\App
+SourcePath#3=..\LWIP\App
+SourcePath#4=..\LWIP\Target
 SourceFiles=;
 
diff --git a/.project b/.project
index ec118c4..4d66f3c 100644
--- a/.project
+++ b/.project
@@ -1,6 +1,6 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <projectDescription>
-	<name>lwip_test</name>
+	<name>TBD_TaxiBoard</name>
 	<comment></comment>
 	<projects>
 	</projects>
diff --git a/.settings/language.settings.xml b/.settings/language.settings.xml
index 68d9653..adaa474 100644
--- a/.settings/language.settings.xml
+++ b/.settings/language.settings.xml
@@ -1,6 +1,6 @@
 <?xml version="1.0" encoding="UTF-8" standalone="no"?>
 <project>
-	<configuration id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug.898215809" name="Debug">
+	<configuration id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug.200712874" name="Debug">
 		<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
 			<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
 			<provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
@@ -11,7 +11,7 @@
 			</provider>
 		</extension>
 	</configuration>
-	<configuration id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.release.239570574" name="Release">
+	<configuration id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.release.317158393" name="Release">
 		<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
 			<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
 			<provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
diff --git a/.settings/org.eclipse.cdt.codan.core.prefs b/.settings/org.eclipse.cdt.codan.core.prefs
new file mode 100644
index 0000000..3e86936
--- /dev/null
+++ b/.settings/org.eclipse.cdt.codan.core.prefs
@@ -0,0 +1,76 @@
+com.st.stm32cube.ide.mcu.ide.oss.source.checker.libnano.problem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Float formatting support\\")"}
+eclipse.preferences.version=1
+org.eclipse.cdt.codan.checkers.errnoreturn.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"No return\\")",implicit\=>false}
+org.eclipse.cdt.codan.checkers.errreturnvalue.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Unused return value\\")"}
+org.eclipse.cdt.codan.checkers.localvarreturn=-Warning
+org.eclipse.cdt.codan.checkers.localvarreturn.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Returning the address of a local variable\\")"}
+org.eclipse.cdt.codan.checkers.nocommentinside.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Nesting comments\\")"}
+org.eclipse.cdt.codan.checkers.nolinecomment.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Line comments\\")"}
+org.eclipse.cdt.codan.checkers.noreturn.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"No return value\\")",implicit\=>false}
+org.eclipse.cdt.codan.internal.checkers.AbstractClassCreation.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Abstract class cannot be instantiated\\")"}
+org.eclipse.cdt.codan.internal.checkers.AmbiguousProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Ambiguous problem\\")"}
+org.eclipse.cdt.codan.internal.checkers.AssignmentInConditionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Assignment in condition\\")"}
+org.eclipse.cdt.codan.internal.checkers.AssignmentToItselfProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Assignment to itself\\")"}
+org.eclipse.cdt.codan.internal.checkers.BlacklistProblem=-Warning
+org.eclipse.cdt.codan.internal.checkers.BlacklistProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Function or method is blacklisted\\")",blacklist\=>()}
+org.eclipse.cdt.codan.internal.checkers.CStyleCastProblem=-Warning
+org.eclipse.cdt.codan.internal.checkers.CStyleCastProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"C-Style cast instead of C++ cast\\")",checkMacro\=>true}
+org.eclipse.cdt.codan.internal.checkers.CaseBreakProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"No break at end of case\\")",no_break_comment\=>"no break",last_case_param\=>false,empty_case_param\=>false,enable_fallthrough_quickfix_param\=>false}
+org.eclipse.cdt.codan.internal.checkers.CatchByReference.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Catching by reference is recommended\\")",unknown\=>false,exceptions\=>()}
+org.eclipse.cdt.codan.internal.checkers.CircularReferenceProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Circular inheritance\\")"}
+org.eclipse.cdt.codan.internal.checkers.ClassMembersInitialization.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Class members should be properly initialized\\")",skip\=>true}
+org.eclipse.cdt.codan.internal.checkers.CopyrightProblem=-Warning
+org.eclipse.cdt.codan.internal.checkers.CopyrightProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Lack of copyright information\\")",regex\=>".*Copyright.*"}
+org.eclipse.cdt.codan.internal.checkers.DecltypeAutoProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Invalid 'decltype(auto)' specifier\\")"}
+org.eclipse.cdt.codan.internal.checkers.FieldResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Field cannot be resolved\\")"}
+org.eclipse.cdt.codan.internal.checkers.FloatCompareProblem=-Warning
+org.eclipse.cdt.codan.internal.checkers.FloatCompareProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Direct float comparison\\")"}
+org.eclipse.cdt.codan.internal.checkers.FunctionResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Function cannot be resolved\\")"}
+org.eclipse.cdt.codan.internal.checkers.GotoStatementProblem=-Warning
+org.eclipse.cdt.codan.internal.checkers.GotoStatementProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Goto statement used\\")"}
+org.eclipse.cdt.codan.internal.checkers.InvalidArguments.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Invalid arguments\\")"}
+org.eclipse.cdt.codan.internal.checkers.InvalidTemplateArgumentsProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Invalid template argument\\")"}
+org.eclipse.cdt.codan.internal.checkers.LabelStatementNotFoundProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Label statement not found\\")"}
+org.eclipse.cdt.codan.internal.checkers.MagicNumberProblem=-Warning
+org.eclipse.cdt.codan.internal.checkers.MagicNumberProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Avoid magic numbers\\")",checkArray\=>true,checkOperatorParen\=>true,exceptions\=>(1,0,-1,2,1.0,0.0,-1.0)}
+org.eclipse.cdt.codan.internal.checkers.MemberDeclarationNotFoundProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Member declaration not found\\")"}
+org.eclipse.cdt.codan.internal.checkers.MethodResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Method cannot be resolved\\")"}
+org.eclipse.cdt.codan.internal.checkers.MissCaseProblem=-Warning
+org.eclipse.cdt.codan.internal.checkers.MissCaseProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Missing cases in switch\\")"}
+org.eclipse.cdt.codan.internal.checkers.MissDefaultProblem=-Warning
+org.eclipse.cdt.codan.internal.checkers.MissDefaultProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Missing default in switch\\")",defaultWithAllEnums\=>false}
+org.eclipse.cdt.codan.internal.checkers.MissReferenceProblem=-Warning
+org.eclipse.cdt.codan.internal.checkers.MissReferenceProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Missing reference return value in assignment operator\\")"}
+org.eclipse.cdt.codan.internal.checkers.MissSelfCheckProblem=-Warning
+org.eclipse.cdt.codan.internal.checkers.MissSelfCheckProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Missing self check in assignment operator\\")"}
+org.eclipse.cdt.codan.internal.checkers.MultipleDeclarationsProblem=-Warning
+org.eclipse.cdt.codan.internal.checkers.MultipleDeclarationsProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Multiple variable declaration\\")"}
+org.eclipse.cdt.codan.internal.checkers.NamingConventionFunctionChecker.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Name convention for function\\")",pattern\=>"^[a-z]",macro\=>true,exceptions\=>()}
+org.eclipse.cdt.codan.internal.checkers.NoDiscardProblem=Warning
+org.eclipse.cdt.codan.internal.checkers.NoDiscardProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Return value not evaluated\\")",macro\=>true}
+org.eclipse.cdt.codan.internal.checkers.NonVirtualDestructorProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Class has a virtual method and non-virtual destructor\\")"}
+org.eclipse.cdt.codan.internal.checkers.OverloadProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Invalid overload\\")"}
+org.eclipse.cdt.codan.internal.checkers.RedeclarationProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Invalid redeclaration\\")"}
+org.eclipse.cdt.codan.internal.checkers.RedefinitionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Invalid redefinition\\")"}
+org.eclipse.cdt.codan.internal.checkers.ReturnStyleProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Return with parenthesis\\")"}
+org.eclipse.cdt.codan.internal.checkers.ScanfFormatStringSecurityProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Format String Vulnerability\\")"}
+org.eclipse.cdt.codan.internal.checkers.ShallowCopyProblem=-Warning
+org.eclipse.cdt.codan.internal.checkers.ShallowCopyProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Miss copy constructor or assignment operator\\")",onlynew\=>false}
+org.eclipse.cdt.codan.internal.checkers.StatementHasNoEffectProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Statement has no effect\\")",macro\=>true,exceptions\=>()}
+org.eclipse.cdt.codan.internal.checkers.StaticVariableInHeaderProblem=-Warning
+org.eclipse.cdt.codan.internal.checkers.StaticVariableInHeaderProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Static variable in header file\\")"}
+org.eclipse.cdt.codan.internal.checkers.StructuredBindingDeclarationProblem=Error
+org.eclipse.cdt.codan.internal.checkers.StructuredBindingDeclarationProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Invalid structured binding declaration\\")"}
+org.eclipse.cdt.codan.internal.checkers.SuggestedParenthesisProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Suggested parenthesis around expression\\")",paramNot\=>false}
+org.eclipse.cdt.codan.internal.checkers.SuspiciousSemicolonProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Suspicious semicolon\\")",else\=>false,afterelse\=>false}
+org.eclipse.cdt.codan.internal.checkers.SymbolShadowingProblem=-Warning
+org.eclipse.cdt.codan.internal.checkers.SymbolShadowingProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Symbol shadowing\\")",paramFuncParameters\=>true}
+org.eclipse.cdt.codan.internal.checkers.TypeResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Type cannot be resolved\\")"}
+org.eclipse.cdt.codan.internal.checkers.UnusedFunctionDeclarationProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Unused function declaration\\")",macro\=>true}
+org.eclipse.cdt.codan.internal.checkers.UnusedStaticFunctionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Unused static function\\")",macro\=>true}
+org.eclipse.cdt.codan.internal.checkers.UnusedVariableDeclarationProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Unused variable declaration in file scope\\")",macro\=>true,exceptions\=>("@(\#)","$Id")}
+org.eclipse.cdt.codan.internal.checkers.UsingInHeaderProblem=-Warning
+org.eclipse.cdt.codan.internal.checkers.UsingInHeaderProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Using directive in header\\")"}
+org.eclipse.cdt.codan.internal.checkers.VariableResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Symbol is not resolved\\")"}
+org.eclipse.cdt.codan.internal.checkers.VirtualMethodCallProblem=-Error
+org.eclipse.cdt.codan.internal.checkers.VirtualMethodCallProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Virtual method call in constructor/destructor\\")"}
diff --git a/.settings/org.eclipse.cdt.core.prefs b/.settings/org.eclipse.cdt.core.prefs
new file mode 100644
index 0000000..c8ec5df
--- /dev/null
+++ b/.settings/org.eclipse.cdt.core.prefs
@@ -0,0 +1,6 @@
+doxygen/doxygen_new_line_after_brief=true
+doxygen/doxygen_use_brief_tag=false
+doxygen/doxygen_use_javadoc_tags=true
+doxygen/doxygen_use_pre_tag=false
+doxygen/doxygen_use_structural_commands=false
+eclipse.preferences.version=1
diff --git a/.settings/stm32cubeide.project.prefs b/.settings/stm32cubeide.project.prefs
index 50c300f..4b9a8ab 100644
--- a/.settings/stm32cubeide.project.prefs
+++ b/.settings/stm32cubeide.project.prefs
@@ -1,6 +1,6 @@
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-635E684B79701B039C64EA45C3F84D30=591ABC0D4CC77D36A04CE6FE702D2AB0
+2F62501ED4689FB349E356AB974DBE57=142717C5F4082A60DD9609231D0F077D
+635E684B79701B039C64EA45C3F84D30=BB961CC53A0667278ACD89DFF06E1D9F
 66BE74F758C12D739921AEA421D593D3=4
-8DF89ED150041C4CBC7CB9A9CAA90856=0F380600D8D2B0DDEC8E00D7C844FF4C
+8DF89ED150041C4CBC7CB9A9CAA90856=142717C5F4082A60DD9609231D0F077D
 DC22A860405A8BF2F2C095E5B6529F12=3689951419DD9ED3A6AC68932BCB3771
 eclipse.preferences.version=1
diff --git a/Core/Inc/FreeRTOSConfig.h b/Core/Inc/FreeRTOSConfig.h
new file mode 100644
index 0000000..9927e0f
--- /dev/null
+++ b/Core/Inc/FreeRTOSConfig.h
@@ -0,0 +1,147 @@
+/* USER CODE BEGIN Header */
+/*
+ * FreeRTOS Kernel V10.3.1
+ * Portion Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Portion Copyright (C) 2019 StMicroelectronics, Inc.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+/* USER CODE END Header */
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * These parameters and more are described within the 'configuration' section of the
+ * FreeRTOS API documentation available on the FreeRTOS.org web site.
+ *
+ * See http://www.freertos.org/a00110.html
+ *----------------------------------------------------------*/
+
+/* USER CODE BEGIN Includes */
+/* Section where include file can be added */
+/* USER CODE END Includes */
+
+/* Ensure definitions are only used by the compiler, and not by the assembler. */
+#if defined(__ICCARM__) || defined(__CC_ARM) || defined(__GNUC__)
+  #include <stdint.h>
+  extern uint32_t SystemCoreClock;
+#endif
+#define configENABLE_FPU                         0
+#define configENABLE_MPU                         0
+
+#define configUSE_PREEMPTION                     1
+#define configSUPPORT_STATIC_ALLOCATION          1
+#define configSUPPORT_DYNAMIC_ALLOCATION         1
+#define configUSE_IDLE_HOOK                      0
+#define configUSE_TICK_HOOK                      0
+#define configCPU_CLOCK_HZ                       ( SystemCoreClock )
+#define configTICK_RATE_HZ                       ((TickType_t)1000)
+#define configMAX_PRIORITIES                     ( 7 )
+#define configMINIMAL_STACK_SIZE                 ((uint16_t)256)
+#define configTOTAL_HEAP_SIZE                    ((size_t)30720)
+#define configMAX_TASK_NAME_LEN                  ( 16 )
+#define configUSE_16_BIT_TICKS                   0
+#define configUSE_MUTEXES                        1
+#define configQUEUE_REGISTRY_SIZE                8
+#define configCHECK_FOR_STACK_OVERFLOW           1
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION  1
+/* USER CODE BEGIN MESSAGE_BUFFER_LENGTH_TYPE */
+/* Defaults to size_t for backward compatibility, but can be changed
+   if lengths will always be less than the number of bytes in a size_t. */
+#define configMESSAGE_BUFFER_LENGTH_TYPE         size_t
+/* USER CODE END MESSAGE_BUFFER_LENGTH_TYPE */
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES                    0
+#define configMAX_CO_ROUTINE_PRIORITIES          ( 2 )
+
+/* Software timer definitions. */
+#define configUSE_TIMERS                         1
+#define configTIMER_TASK_PRIORITY                ( 2 )
+#define configTIMER_QUEUE_LENGTH                 10
+#define configTIMER_TASK_STACK_DEPTH             512
+
+/* Set the following definitions to 1 to include the API function, or zero
+to exclude the API function. */
+#define INCLUDE_vTaskPrioritySet             1
+#define INCLUDE_uxTaskPriorityGet            1
+#define INCLUDE_vTaskDelete                  1
+#define INCLUDE_vTaskCleanUpResources        0
+#define INCLUDE_vTaskSuspend                 1
+#define INCLUDE_vTaskDelayUntil              1
+#define INCLUDE_vTaskDelay                   1
+#define INCLUDE_xTaskGetSchedulerState       1
+
+/* Cortex-M specific definitions. */
+#ifdef __NVIC_PRIO_BITS
+ /* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */
+ #define configPRIO_BITS         __NVIC_PRIO_BITS
+#else
+ #define configPRIO_BITS         4
+#endif
+
+/* The lowest interrupt priority that can be used in a call to a "set priority"
+function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY   15
+
+/* The highest interrupt priority that can be used by any interrupt service
+routine that makes calls to interrupt safe FreeRTOS API functions.  DO NOT CALL
+INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
+PRIORITY THAN THIS! (higher priorities are lower numeric values. */
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 5
+
+/* Interrupt priorities used by the kernel port layer itself.  These are generic
+to all Cortex-M ports, and do not rely on any particular library functions. */
+#define configKERNEL_INTERRUPT_PRIORITY 		( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
+See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY 	( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+/* Normal assert() semantics without relying on the provision of an assert.h
+header file. */
+/* USER CODE BEGIN 1 */
+#define configASSERT( x ) if ((x) == 0) {taskDISABLE_INTERRUPTS(); for( ;; );}
+#define INCLUDE_uxTaskGetStackHighWaterMark 1 // To check stack usage of task
+/* USER CODE END 1 */
+
+/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS
+standard names. */
+#define vPortSVCHandler    SVC_Handler
+#define xPortPendSVHandler PendSV_Handler
+
+/* IMPORTANT: This define is commented when used with STM32Cube firmware, when the timebase source is SysTick,
+              to prevent overwriting SysTick_Handler defined within STM32Cube HAL */
+
+#define xPortSysTickHandler SysTick_Handler
+
+/* USER CODE BEGIN Defines */
+/* Section where parameter definitions can be added (for instance, to override default ones in FreeRTOS.h) */
+/* USER CODE END Defines */
+
+#endif /* FREERTOS_CONFIG_H */
diff --git a/Core/Inc/main.h b/Core/Inc/main.h
index 4345c9f..6444909 100644
--- a/Core/Inc/main.h
+++ b/Core/Inc/main.h
@@ -57,6 +57,20 @@ void Error_Handler(void);
 /* USER CODE END EFP */
 
 /* Private defines -----------------------------------------------------------*/
+#define mLED_Pin GPIO_PIN_15
+#define mLED_GPIO_Port GPIOA
+#define SD_LED_Pin GPIO_PIN_10
+#define SD_LED_GPIO_Port GPIOE
+#define sdDetect_Pin GPIO_PIN_15
+#define sdDetect_GPIO_Port GPIOB
+#define VIN_IG_Pin GPIO_PIN_11
+#define VIN_IG_GPIO_Port GPIOE
+#define VIN_ON_Pin GPIO_PIN_12
+#define VIN_ON_GPIO_Port GPIOE
+#define PICO_EN_Pin GPIO_PIN_9
+#define PICO_EN_GPIO_Port GPIOE
+#define VIN_1_4_Pin GPIO_PIN_13
+#define VIN_1_4_GPIO_Port GPIOE
 
 /* USER CODE BEGIN Private defines */
 
diff --git a/Core/Inc/stm32h7xx_hal_conf.h b/Core/Inc/stm32h7xx_hal_conf.h
index 0b964f5..52236ed 100644
--- a/Core/Inc/stm32h7xx_hal_conf.h
+++ b/Core/Inc/stm32h7xx_hal_conf.h
@@ -35,7 +35,7 @@
 #define HAL_MODULE_ENABLED
 
   /* #define HAL_ADC_MODULE_ENABLED   */
-/* #define HAL_FDCAN_MODULE_ENABLED   */
+#define HAL_FDCAN_MODULE_ENABLED
 /* #define HAL_FMAC_MODULE_ENABLED   */
 /* #define HAL_CEC_MODULE_ENABLED   */
 /* #define HAL_COMP_MODULE_ENABLED   */
@@ -70,13 +70,13 @@
 /* #define HAL_RNG_MODULE_ENABLED   */
 /* #define HAL_RTC_MODULE_ENABLED   */
 /* #define HAL_SAI_MODULE_ENABLED   */
-/* #define HAL_SD_MODULE_ENABLED   */
+#define HAL_SD_MODULE_ENABLED
 /* #define HAL_MMC_MODULE_ENABLED   */
 /* #define HAL_SPDIFRX_MODULE_ENABLED   */
 /* #define HAL_SPI_MODULE_ENABLED   */
 /* #define HAL_SWPMI_MODULE_ENABLED   */
-/* #define HAL_TIM_MODULE_ENABLED   */
-/* #define HAL_UART_MODULE_ENABLED   */
+#define HAL_TIM_MODULE_ENABLED
+#define HAL_UART_MODULE_ENABLED
 /* #define HAL_USART_MODULE_ENABLED   */
 /* #define HAL_IRDA_MODULE_ENABLED   */
 /* #define HAL_SMARTCARD_MODULE_ENABLED   */
diff --git a/Core/Inc/stm32h7xx_it.h b/Core/Inc/stm32h7xx_it.h
index d0a29c7..eeb2401 100644
--- a/Core/Inc/stm32h7xx_it.h
+++ b/Core/Inc/stm32h7xx_it.h
@@ -51,11 +51,15 @@ void HardFault_Handler(void);
 void MemManage_Handler(void);
 void BusFault_Handler(void);
 void UsageFault_Handler(void);
-void SVC_Handler(void);
 void DebugMon_Handler(void);
-void PendSV_Handler(void);
-void SysTick_Handler(void);
+void DMA1_Stream0_IRQHandler(void);
+void FDCAN1_IT0_IRQHandler(void);
+void FDCAN2_IT0_IRQHandler(void);
+void SDMMC1_IRQHandler(void);
+void TIM6_DAC_IRQHandler(void);
 void ETH_IRQHandler(void);
+void MDMA_IRQHandler(void);
+void FDCAN3_IT0_IRQHandler(void);
 /* USER CODE BEGIN EFP */
 
 /* USER CODE END EFP */
diff --git a/Core/Src/freertos.c b/Core/Src/freertos.c
new file mode 100644
index 0000000..bfab709
--- /dev/null
+++ b/Core/Src/freertos.c
@@ -0,0 +1,102 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * File Name          : freertos.c
+  * Description        : Code for freertos applications
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2024 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "FreeRTOS.h"
+#include "task.h"
+#include "main.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN Variables */
+
+/* USER CODE END Variables */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN FunctionPrototypes */
+
+/* USER CODE END FunctionPrototypes */
+
+/* GetIdleTaskMemory prototype (linked to static allocation support) */
+void vApplicationGetIdleTaskMemory( StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize );
+
+/* GetTimerTaskMemory prototype (linked to static allocation support) */
+void vApplicationGetTimerTaskMemory( StaticTask_t **ppxTimerTaskTCBBuffer, StackType_t **ppxTimerTaskStackBuffer, uint32_t *pulTimerTaskStackSize );
+
+/* Hook prototypes */
+void vApplicationStackOverflowHook(xTaskHandle xTask, signed char *pcTaskName);
+
+/* USER CODE BEGIN 4 */
+__weak void vApplicationStackOverflowHook(xTaskHandle xTask, signed char *pcTaskName)
+{
+   /* Run time stack overflow checking is performed if
+   configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook function is
+   called if a stack overflow is detected. */
+}
+/* USER CODE END 4 */
+
+/* USER CODE BEGIN GET_IDLE_TASK_MEMORY */
+static StaticTask_t xIdleTaskTCBBuffer;
+static StackType_t xIdleStack[configMINIMAL_STACK_SIZE];
+
+void vApplicationGetIdleTaskMemory( StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize )
+{
+  *ppxIdleTaskTCBBuffer = &xIdleTaskTCBBuffer;
+  *ppxIdleTaskStackBuffer = &xIdleStack[0];
+  *pulIdleTaskStackSize = configMINIMAL_STACK_SIZE;
+  /* place for user code */
+}
+/* USER CODE END GET_IDLE_TASK_MEMORY */
+
+/* USER CODE BEGIN GET_TIMER_TASK_MEMORY */
+static StaticTask_t xTimerTaskTCBBuffer;
+static StackType_t xTimerStack[configTIMER_TASK_STACK_DEPTH];
+
+void vApplicationGetTimerTaskMemory( StaticTask_t **ppxTimerTaskTCBBuffer, StackType_t **ppxTimerTaskStackBuffer, uint32_t *pulTimerTaskStackSize )
+{
+  *ppxTimerTaskTCBBuffer = &xTimerTaskTCBBuffer;
+  *ppxTimerTaskStackBuffer = &xTimerStack[0];
+  *pulTimerTaskStackSize = configTIMER_TASK_STACK_DEPTH;
+  /* place for user code */
+}
+/* USER CODE END GET_TIMER_TASK_MEMORY */
+
+/* Private application code --------------------------------------------------*/
+/* USER CODE BEGIN Application */
+
+/* USER CODE END Application */
diff --git a/Core/Src/main.c b/Core/Src/main.c
index c750c3b..c8f82ee 100644
--- a/Core/Src/main.c
+++ b/Core/Src/main.c
@@ -17,14 +17,17 @@
  */
 /* USER CODE END Header */
 /* Includes ------------------------------------------------------------------*/
-#include <_lwftp.h>
 #include "main.h"
+#include "cmsis_os.h"
+#include "fatfs.h"
 #include "lwip.h"
 
 /* Private includes ----------------------------------------------------------*/
 /* USER CODE BEGIN Includes */
 #include <stdio.h>
-#include <stdarg.h>
+#include <string.h>
+#include "lwip/api.h"
+#include "lwftpc.h"
 /* USER CODE END Includes */
 
 /* Private typedef -----------------------------------------------------------*/
@@ -44,7 +47,35 @@
 
 /* Private variables ---------------------------------------------------------*/
 
+FDCAN_HandleTypeDef hfdcan1;
+FDCAN_HandleTypeDef hfdcan2;
+FDCAN_HandleTypeDef hfdcan3;
+
+SD_HandleTypeDef hsd1;
+
+TIM_HandleTypeDef htim3;
+
+UART_HandleTypeDef huart4;
+UART_HandleTypeDef huart7;
+UART_HandleTypeDef huart8;
+DMA_HandleTypeDef hdma_uart8_rx;
+
+MDMA_HandleTypeDef hmdma_mdma_channel0_sdmmc1_end_data_0;
+osThreadId defaultTaskHandle;
+uint32_t defaultTaskBuffer[ 4096 ];
+osStaticThreadDef_t defaultTaskControlBlock;
+osThreadId debugTaskHandle;
+uint32_t debugTaskBuffer[ 2048 ];
+osStaticThreadDef_t debugTaskControlBlock;
 /* USER CODE BEGIN PV */
+#define FTPSemaphore 0
+static lwftp_session_t s;
+sys_sem_t ftpsem;
+uint8_t CLI_IP[4] = { 192, 168, 0, 120 };	// client addr
+uint8_t SVR_IP[4] = { 192, 168, 0, 100 };	// server addr
+u16_t SVR_PORT = 21;
+char *USER = "anonymous";
+char *PASS = "email@example.com";
 
 /* USER CODE END PV */
 
@@ -52,338 +83,861 @@
 void SystemClock_Config(void);
 static void MPU_Config(void);
 static void MX_GPIO_Init(void);
+static void MX_DMA_Init(void);
+static void MX_MDMA_Init(void);
+static void MX_FDCAN3_Init(void);
+static void MX_SDMMC1_SD_Init(void);
+static void MX_TIM3_Init(void);
+static void MX_UART4_Init(void);
+static void MX_UART7_Init(void);
+static void MX_FDCAN1_Init(void);
+static void MX_FDCAN2_Init(void);
+static void MX_UART8_Init(void);
+void StartDefaultTask(void const * argument);
+void StartDebugTask(void const * argument);
+
 /* USER CODE BEGIN PFP */
+// Function to send the data to the server
+void lwftp_init(void);
 
 /* USER CODE END PFP */
 
 /* Private user code ---------------------------------------------------------*/
 /* USER CODE BEGIN 0 */
-#define min(x, y) (x) < (y) ? (x) : (y)
-#define max(x, y) (x) > (y) ? (x) : (y)
-
 int _write(int32_t file, uint8_t *ptr, int32_t len) {
 	for (int32_t i = 0; i < len; ++i)
 		ITM_SendChar(*ptr++);
 	return len;
 }
-
-extern void LOG_TRACE(const char *message) {
-	printf("TRACE: %s \r\n", message);
-}
-
-/* ============ LWFTP Code ============*/
-static void ftp_retr_callback(void *arg, int result) {
-	lwftp_session_t *s = (lwftp_session_t*) arg;
-
-	if (result != LWFTP_RESULT_OK) {
-		LOG_ERROR("retr failed (%d)", result);
-		return lwftp_close(s);
-	}
-	// Test is done
-	lwftp_close(s);
-}
-
-static uint data_sink(void *arg, const char *ptr, uint len) {
-	static const uint mylen = 12345;
-	static char *const myconfig = (char*) 0x20000000;
-	static uint offset = 0;
-
-	if (ptr) {
-		len = min(len, mylen - offset);
-		memcpy(myconfig + offset, ptr, len);
-		offset += len;
-	}
-	return len;
-}
-
-static void ftp_stor_callback(void *arg, int result) {
-	lwftp_session_t *s = (lwftp_session_t*) arg;
-	err_t error;
-
-	if (result != LWFTP_RESULT_OK) {
-		LOG_ERROR("stor failed (%d)", result);
-		return lwftp_close(s);
-	}
-	// Continue with RETR request
-	s->data_sink = data_sink;
-	s->done_fn = ftp_retr_callback;
-	s->remote_path = "configfile";
-	error = lwftp_retrieve(s);
-	if (error != LWFTP_RESULT_INPROGRESS) {
-		LOG_ERROR("lwftp_retrieve failed (%d)", error);
-	}
-	// FTP session will continue with RETR and sink callbacks
-}
-
-static uint data_source(void *arg, const char **pptr, uint maxlen) {
-	static const uint mylen = 12345;
-	static const char *const mydata = (char*) 0x20000000;
-	static uint offset = 0;
-	uint len = 0;
-
-	// Check for data request or data sent notice
-	if (pptr) {
-		len = mylen - offset;
-		if (len > maxlen)
-			len = maxlen;
-		*pptr = mydata + offset;
-	} else {
-		offset += maxlen;
-		if (offset > mylen)
-			offset = mylen;
-	}
-	return len;
-}
-
-static void ftp_connect_callback(void *arg, int result) {
-	lwftp_session_t *s = (lwftp_session_t*) arg;
-	err_t error;
-	if (result == LWFTP_RESULT_LOGGED) {
-		LOG_TRACE("login success !!!!! \r\n");
-	} else {
-		LOG_TRACE("login failed !!!!! \r\n");
-	}
-//	LOG_TRACE("> lwftp connect callback \r\n");
-//	if (result != LWFTP_RESULT_LOGGED) {
-//		LOG_ERROR("login failed (%d)", result);
-//		return lwftp_close(s);
-//	}
-
-	return
-	// Continue with STOR request
-	s->data_source = data_source;
-	s->done_fn = ftp_stor_callback;
-	s->remote_path = "logfile";
-	error = lwftp_store(s);
-	if (error != LWFTP_RESULT_INPROGRESS) {
-		LOG_ERROR("lwftp_store failed (%d)", error);
-	}
-	// FTP session will continue with STOR and source callbacks
-}
-
-static void ftp_test(void) {
-	static lwftp_session_t s;   // static content for the whole FTP session
-	err_t error;
-
-	// Initialize session data
-	memset(&s, 0, sizeof(s));
-
-	IP4_ADDR(&s.server_ip, 192, 168, 0, 100);
-	s.server_port = 21;
-	s.done_fn = ftp_connect_callback;
-	s.user = "anonymous";	// Anonymous client
-	s.pass = "space2lim@naver.com";
-	// We have no extra user data, simply use the session structure
-	s.handle = &s;
-
-	// Start the connection state machine
-	error = lwftp_connect(&s);
-	if (error != LWFTP_RESULT_INPROGRESS) {
-		LOG_ERROR("lwftp_connect failed (%d)", error);
-	}
-	// FTP session will continue with the connection callback
-}
-
 /* USER CODE END 0 */
 
 /**
- * @brief  The application entry point.
- * @retval int
- */
-int main(void) {
-	/* USER CODE BEGIN 1 */
+  * @brief  The application entry point.
+  * @retval int
+  */
+int main(void)
+{
+  /* USER CODE BEGIN 1 */
 
-	/* USER CODE END 1 */
+  /* USER CODE END 1 */
 
-	/* MPU Configuration--------------------------------------------------------*/
-	MPU_Config();
-	/* Enable the CPU Cache */
+  /* MPU Configuration--------------------------------------------------------*/
+  MPU_Config();
+/* Enable the CPU Cache */
 
-	/* Enable I-Cache---------------------------------------------------------*/
-	SCB_EnableICache();
+  /* Enable I-Cache---------------------------------------------------------*/
+  SCB_EnableICache();
 
-	/* Enable D-Cache---------------------------------------------------------*/
-	SCB_EnableDCache();
+  /* Enable D-Cache---------------------------------------------------------*/
+  SCB_EnableDCache();
 
-	/* MCU Configuration--------------------------------------------------------*/
+  /* MCU Configuration--------------------------------------------------------*/
 
-	/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
-	HAL_Init();
+  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+  HAL_Init();
 
-	/* USER CODE BEGIN Init */
+  /* USER CODE BEGIN Init */
 
-	/* USER CODE END Init */
+  /* USER CODE END Init */
 
-	/* Configure the system clock */
-	SystemClock_Config();
+  /* Configure the system clock */
+  SystemClock_Config();
 
-	/* USER CODE BEGIN SysInit */
+  /* USER CODE BEGIN SysInit */
 
-	/* USER CODE END SysInit */
+  /* USER CODE END SysInit */
+
+  /* Initialize all configured peripherals */
+  MX_GPIO_Init();
+  MX_DMA_Init();
+  MX_MDMA_Init();
+  MX_FDCAN3_Init();
+  MX_SDMMC1_SD_Init();
+  MX_TIM3_Init();
+  MX_UART4_Init();
+  MX_UART7_Init();
+  MX_FDCAN1_Init();
+  MX_FDCAN2_Init();
+  MX_FATFS_Init();
+  MX_UART8_Init();
+  /* USER CODE BEGIN 2 */
+#define RTOS_MODE 1
+#if RTOS_MODE
+  /* USER CODE END 2 */
+
+  /* USER CODE BEGIN RTOS_MUTEX */
+	/* add mutexes, ... */
+  /* USER CODE END RTOS_MUTEX */
+
+  /* USER CODE BEGIN RTOS_SEMAPHORES */
+	/* add semaphores, ... */
+  /* USER CODE END RTOS_SEMAPHORES */
+
+  /* USER CODE BEGIN RTOS_TIMERS */
+	/* start timers, add new ones, ... */
+  /* USER CODE END RTOS_TIMERS */
+
+  /* USER CODE BEGIN RTOS_QUEUES */
+	/* add queues, ... */
+  /* USER CODE END RTOS_QUEUES */
+
+  /* Create the thread(s) */
+  /* definition and creation of defaultTask */
+  osThreadStaticDef(defaultTask, StartDefaultTask, osPriorityNormal, 0, 4096, defaultTaskBuffer, &defaultTaskControlBlock);
+  defaultTaskHandle = osThreadCreate(osThread(defaultTask), NULL);
+
+  /* definition and creation of debugTask */
+  osThreadStaticDef(debugTask, StartDebugTask, osPriorityNormal, 0, 2048, debugTaskBuffer, &debugTaskControlBlock);
+  debugTaskHandle = osThreadCreate(osThread(debugTask), NULL);
+
+  /* USER CODE BEGIN RTOS_THREADS */
+	/* add threads, ... */
+  /* USER CODE END RTOS_THREADS */
+
+  /* Start scheduler */
+  osKernelStart();
+
+  /* We should never get here as control is now taken by the scheduler */
+  /* Infinite loop */
+  /* USER CODE BEGIN WHILE */
+#else
 
-	/* Initialize all configured peripherals */
-	MX_GPIO_Init();
 	MX_LWIP_Init();
-	/* USER CODE BEGIN 2 */
-
-	/* USER CODE END 2 */
-
-	/* Infinite loop */
-	/* USER CODE BEGIN WHILE */
-
-	/* ============ LWFTP Code ============*/
-	ftp_test();
-//	ftp_connect();
-
 	while (1) {
 		MX_LWIP_Process();
-		/* USER CODE END WHILE */
 
-		/* USER CODE BEGIN 3 */
+    /* USER CODE END WHILE */
+
+    /* USER CODE BEGIN 3 */
 	}
-	/* USER CODE END 3 */
+#endif
+  /* USER CODE END 3 */
 }
 
 /**
- * @brief System Clock Configuration
- * @retval None
- */
-void SystemClock_Config(void) {
-	RCC_OscInitTypeDef RCC_OscInitStruct = { 0 };
-	RCC_ClkInitTypeDef RCC_ClkInitStruct = { 0 };
+  * @brief System Clock Configuration
+  * @retval None
+  */
+void SystemClock_Config(void)
+{
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
 
-	/** Supply configuration update enable
-	 */
-	HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY);
+  /** Supply configuration update enable
+  */
+  HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY);
 
-	/** Configure the main internal regulator output voltage
-	 */
-	__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE0);
+  /** Configure the main internal regulator output voltage
+  */
+  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE0);
 
-	while (!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {
-	}
+  while(!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {}
 
-	/** Initializes the RCC Oscillators according to the specified parameters
-	 * in the RCC_OscInitTypeDef structure.
-	 */
-	RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
-	RCC_OscInitStruct.HSEState = RCC_HSE_ON;
-	RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
-	RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
-	RCC_OscInitStruct.PLL.PLLM = 5;
-	RCC_OscInitStruct.PLL.PLLN = 96;
-	RCC_OscInitStruct.PLL.PLLP = 1;
-	RCC_OscInitStruct.PLL.PLLQ = 2;
-	RCC_OscInitStruct.PLL.PLLR = 2;
-	RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_2;
-	RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE;
-	RCC_OscInitStruct.PLL.PLLFRACN = 0;
-	if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
-		Error_Handler();
-	}
+  /** Initializes the RCC Oscillators according to the specified parameters
+  * in the RCC_OscInitTypeDef structure.
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
+  RCC_OscInitStruct.HSEState = RCC_HSE_ON;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
+  RCC_OscInitStruct.PLL.PLLM = 5;
+  RCC_OscInitStruct.PLL.PLLN = 96;
+  RCC_OscInitStruct.PLL.PLLP = 1;
+  RCC_OscInitStruct.PLL.PLLQ = 4;
+  RCC_OscInitStruct.PLL.PLLR = 2;
+  RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_2;
+  RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE;
+  RCC_OscInitStruct.PLL.PLLFRACN = 0;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+  {
+    Error_Handler();
+  }
 
-	/** Initializes the CPU, AHB and APB buses clocks
-	 */
-	RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
-			| RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_D3PCLK1
-			| RCC_CLOCKTYPE_D1PCLK1;
-	RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
-	RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1;
-	RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2;
-	RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2;
-	RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2;
-	RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2;
-	RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2;
+  /** Initializes the CPU, AHB and APB buses clocks
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2
+                              |RCC_CLOCKTYPE_D3PCLK1|RCC_CLOCKTYPE_D1PCLK1;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2;
+  RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2;
+  RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2;
 
-	if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK) {
-		Error_Handler();
-	}
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK)
+  {
+    Error_Handler();
+  }
 }
 
 /**
- * @brief GPIO Initialization Function
- * @param None
- * @retval None
- */
-static void MX_GPIO_Init(void) {
-	/* USER CODE BEGIN MX_GPIO_Init_1 */
-	/* USER CODE END MX_GPIO_Init_1 */
+  * @brief FDCAN1 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_FDCAN1_Init(void)
+{
 
-	/* GPIO Ports Clock Enable */
-	__HAL_RCC_GPIOB_CLK_ENABLE();
-	__HAL_RCC_GPIOA_CLK_ENABLE();
-	__HAL_RCC_GPIOH_CLK_ENABLE();
-	__HAL_RCC_GPIOC_CLK_ENABLE();
+  /* USER CODE BEGIN FDCAN1_Init 0 */
 
-	/* USER CODE BEGIN MX_GPIO_Init_2 */
-	/* USER CODE END MX_GPIO_Init_2 */
+  /* USER CODE END FDCAN1_Init 0 */
+
+  /* USER CODE BEGIN FDCAN1_Init 1 */
+
+  /* USER CODE END FDCAN1_Init 1 */
+  hfdcan1.Instance = FDCAN1;
+  hfdcan1.Init.FrameFormat = FDCAN_FRAME_FD_BRS;
+  hfdcan1.Init.Mode = FDCAN_MODE_NORMAL;
+  hfdcan1.Init.AutoRetransmission = DISABLE;
+  hfdcan1.Init.TransmitPause = DISABLE;
+  hfdcan1.Init.ProtocolException = DISABLE;
+  hfdcan1.Init.NominalPrescaler = 6;
+  hfdcan1.Init.NominalSyncJumpWidth = 4;
+  hfdcan1.Init.NominalTimeSeg1 = 29;
+  hfdcan1.Init.NominalTimeSeg2 = 10;
+  hfdcan1.Init.DataPrescaler = 4;
+  hfdcan1.Init.DataSyncJumpWidth = 4;
+  hfdcan1.Init.DataTimeSeg1 = 11;
+  hfdcan1.Init.DataTimeSeg2 = 3;
+  hfdcan1.Init.MessageRAMOffset = 0;
+  hfdcan1.Init.StdFiltersNbr = 0;
+  hfdcan1.Init.ExtFiltersNbr = 0;
+  hfdcan1.Init.RxFifo0ElmtsNbr = 8;
+  hfdcan1.Init.RxFifo0ElmtSize = FDCAN_DATA_BYTES_64;
+  hfdcan1.Init.RxFifo1ElmtsNbr = 0;
+  hfdcan1.Init.RxFifo1ElmtSize = FDCAN_DATA_BYTES_64;
+  hfdcan1.Init.RxBuffersNbr = 0;
+  hfdcan1.Init.RxBufferSize = FDCAN_DATA_BYTES_64;
+  hfdcan1.Init.TxEventsNbr = 8;
+  hfdcan1.Init.TxBuffersNbr = 0;
+  hfdcan1.Init.TxFifoQueueElmtsNbr = 8;
+  hfdcan1.Init.TxFifoQueueMode = FDCAN_TX_FIFO_OPERATION;
+  hfdcan1.Init.TxElmtSize = FDCAN_DATA_BYTES_64;
+  if (HAL_FDCAN_Init(&hfdcan1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN FDCAN1_Init 2 */
+
+  /* USER CODE END FDCAN1_Init 2 */
+
+}
+
+/**
+  * @brief FDCAN2 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_FDCAN2_Init(void)
+{
+
+  /* USER CODE BEGIN FDCAN2_Init 0 */
+
+  /* USER CODE END FDCAN2_Init 0 */
+
+  /* USER CODE BEGIN FDCAN2_Init 1 */
+
+  /* USER CODE END FDCAN2_Init 1 */
+  hfdcan2.Instance = FDCAN2;
+  hfdcan2.Init.FrameFormat = FDCAN_FRAME_FD_BRS;
+  hfdcan2.Init.Mode = FDCAN_MODE_NORMAL;
+  hfdcan2.Init.AutoRetransmission = DISABLE;
+  hfdcan2.Init.TransmitPause = DISABLE;
+  hfdcan2.Init.ProtocolException = DISABLE;
+  hfdcan2.Init.NominalPrescaler = 6;
+  hfdcan2.Init.NominalSyncJumpWidth = 4;
+  hfdcan2.Init.NominalTimeSeg1 = 29;
+  hfdcan2.Init.NominalTimeSeg2 = 10;
+  hfdcan2.Init.DataPrescaler = 4;
+  hfdcan2.Init.DataSyncJumpWidth = 4;
+  hfdcan2.Init.DataTimeSeg1 = 11;
+  hfdcan2.Init.DataTimeSeg2 = 3;
+  hfdcan2.Init.MessageRAMOffset = 512;
+  hfdcan2.Init.StdFiltersNbr = 0;
+  hfdcan2.Init.ExtFiltersNbr = 0;
+  hfdcan2.Init.RxFifo0ElmtsNbr = 8;
+  hfdcan2.Init.RxFifo0ElmtSize = FDCAN_DATA_BYTES_64;
+  hfdcan2.Init.RxFifo1ElmtsNbr = 0;
+  hfdcan2.Init.RxFifo1ElmtSize = FDCAN_DATA_BYTES_64;
+  hfdcan2.Init.RxBuffersNbr = 0;
+  hfdcan2.Init.RxBufferSize = FDCAN_DATA_BYTES_64;
+  hfdcan2.Init.TxEventsNbr = 8;
+  hfdcan2.Init.TxBuffersNbr = 0;
+  hfdcan2.Init.TxFifoQueueElmtsNbr = 8;
+  hfdcan2.Init.TxFifoQueueMode = FDCAN_TX_FIFO_OPERATION;
+  hfdcan2.Init.TxElmtSize = FDCAN_DATA_BYTES_64;
+  if (HAL_FDCAN_Init(&hfdcan2) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN FDCAN2_Init 2 */
+
+  /* USER CODE END FDCAN2_Init 2 */
+
+}
+
+/**
+  * @brief FDCAN3 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_FDCAN3_Init(void)
+{
+
+  /* USER CODE BEGIN FDCAN3_Init 0 */
+
+  /* USER CODE END FDCAN3_Init 0 */
+
+  /* USER CODE BEGIN FDCAN3_Init 1 */
+
+  /* USER CODE END FDCAN3_Init 1 */
+  hfdcan3.Instance = FDCAN3;
+  hfdcan3.Init.FrameFormat = FDCAN_FRAME_FD_BRS;
+  hfdcan3.Init.Mode = FDCAN_MODE_NORMAL;
+  hfdcan3.Init.AutoRetransmission = DISABLE;
+  hfdcan3.Init.TransmitPause = DISABLE;
+  hfdcan3.Init.ProtocolException = DISABLE;
+  hfdcan3.Init.NominalPrescaler = 6;
+  hfdcan3.Init.NominalSyncJumpWidth = 4;
+  hfdcan3.Init.NominalTimeSeg1 = 29;
+  hfdcan3.Init.NominalTimeSeg2 = 10;
+  hfdcan3.Init.DataPrescaler = 4;
+  hfdcan3.Init.DataSyncJumpWidth = 4;
+  hfdcan3.Init.DataTimeSeg1 = 11;
+  hfdcan3.Init.DataTimeSeg2 = 3;
+  hfdcan3.Init.MessageRAMOffset = 1024;
+  hfdcan3.Init.StdFiltersNbr = 0;
+  hfdcan3.Init.ExtFiltersNbr = 0;
+  hfdcan3.Init.RxFifo0ElmtsNbr = 8;
+  hfdcan3.Init.RxFifo0ElmtSize = FDCAN_DATA_BYTES_64;
+  hfdcan3.Init.RxFifo1ElmtsNbr = 0;
+  hfdcan3.Init.RxFifo1ElmtSize = FDCAN_DATA_BYTES_64;
+  hfdcan3.Init.RxBuffersNbr = 0;
+  hfdcan3.Init.RxBufferSize = FDCAN_DATA_BYTES_64;
+  hfdcan3.Init.TxEventsNbr = 8;
+  hfdcan3.Init.TxBuffersNbr = 0;
+  hfdcan3.Init.TxFifoQueueElmtsNbr = 8;
+  hfdcan3.Init.TxFifoQueueMode = FDCAN_TX_FIFO_OPERATION;
+  hfdcan3.Init.TxElmtSize = FDCAN_DATA_BYTES_64;
+  if (HAL_FDCAN_Init(&hfdcan3) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN FDCAN3_Init 2 */
+
+  /* USER CODE END FDCAN3_Init 2 */
+
+}
+
+/**
+  * @brief SDMMC1 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_SDMMC1_SD_Init(void)
+{
+
+  /* USER CODE BEGIN SDMMC1_Init 0 */
+
+  /* USER CODE END SDMMC1_Init 0 */
+
+  /* USER CODE BEGIN SDMMC1_Init 1 */
+
+  /* USER CODE END SDMMC1_Init 1 */
+  hsd1.Instance = SDMMC1;
+  hsd1.Init.ClockEdge = SDMMC_CLOCK_EDGE_RISING;
+  hsd1.Init.ClockPowerSave = SDMMC_CLOCK_POWER_SAVE_DISABLE;
+  hsd1.Init.BusWide = SDMMC_BUS_WIDE_4B;
+  hsd1.Init.HardwareFlowControl = SDMMC_HARDWARE_FLOW_CONTROL_ENABLE;
+  hsd1.Init.ClockDiv = 1;
+  /* USER CODE BEGIN SDMMC1_Init 2 */
+
+  /* USER CODE END SDMMC1_Init 2 */
+
+}
+
+/**
+  * @brief TIM3 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_TIM3_Init(void)
+{
+
+  /* USER CODE BEGIN TIM3_Init 0 */
+
+  /* USER CODE END TIM3_Init 0 */
+
+  TIM_ClockConfigTypeDef sClockSourceConfig = {0};
+  TIM_MasterConfigTypeDef sMasterConfig = {0};
+
+  /* USER CODE BEGIN TIM3_Init 1 */
+
+  /* USER CODE END TIM3_Init 1 */
+  htim3.Instance = TIM3;
+  htim3.Init.Prescaler = 119;
+  htim3.Init.CounterMode = TIM_COUNTERMODE_UP;
+  htim3.Init.Period = 65535;
+  htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
+  htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
+  if (HAL_TIM_Base_Init(&htim3) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
+  if (HAL_TIM_ConfigClockSource(&htim3, &sClockSourceConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
+  sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
+  if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN TIM3_Init 2 */
+
+  /* USER CODE END TIM3_Init 2 */
+
+}
+
+/**
+  * @brief UART4 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_UART4_Init(void)
+{
+
+  /* USER CODE BEGIN UART4_Init 0 */
+
+  /* USER CODE END UART4_Init 0 */
+
+  /* USER CODE BEGIN UART4_Init 1 */
+
+  /* USER CODE END UART4_Init 1 */
+  huart4.Instance = UART4;
+  huart4.Init.BaudRate = 9600;
+  huart4.Init.WordLength = UART_WORDLENGTH_8B;
+  huart4.Init.StopBits = UART_STOPBITS_1;
+  huart4.Init.Parity = UART_PARITY_NONE;
+  huart4.Init.Mode = UART_MODE_TX_RX;
+  huart4.Init.HwFlowCtl = UART_HWCONTROL_NONE;
+  huart4.Init.OverSampling = UART_OVERSAMPLING_16;
+  huart4.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
+  huart4.Init.ClockPrescaler = UART_PRESCALER_DIV1;
+  huart4.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
+  if (HAL_UART_Init(&huart4) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_UARTEx_SetTxFifoThreshold(&huart4, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_UARTEx_SetRxFifoThreshold(&huart4, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_UARTEx_DisableFifoMode(&huart4) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN UART4_Init 2 */
+
+  /* USER CODE END UART4_Init 2 */
+
+}
+
+/**
+  * @brief UART7 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_UART7_Init(void)
+{
+
+  /* USER CODE BEGIN UART7_Init 0 */
+
+  /* USER CODE END UART7_Init 0 */
+
+  /* USER CODE BEGIN UART7_Init 1 */
+
+  /* USER CODE END UART7_Init 1 */
+  huart7.Instance = UART7;
+  huart7.Init.BaudRate = 115200;
+  huart7.Init.WordLength = UART_WORDLENGTH_8B;
+  huart7.Init.StopBits = UART_STOPBITS_1;
+  huart7.Init.Parity = UART_PARITY_NONE;
+  huart7.Init.Mode = UART_MODE_TX_RX;
+  huart7.Init.HwFlowCtl = UART_HWCONTROL_NONE;
+  huart7.Init.OverSampling = UART_OVERSAMPLING_16;
+  huart7.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
+  huart7.Init.ClockPrescaler = UART_PRESCALER_DIV1;
+  huart7.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
+  if (HAL_UART_Init(&huart7) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_UARTEx_SetTxFifoThreshold(&huart7, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_UARTEx_SetRxFifoThreshold(&huart7, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_UARTEx_DisableFifoMode(&huart7) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN UART7_Init 2 */
+
+  /* USER CODE END UART7_Init 2 */
+
+}
+
+/**
+  * @brief UART8 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_UART8_Init(void)
+{
+
+  /* USER CODE BEGIN UART8_Init 0 */
+
+  /* USER CODE END UART8_Init 0 */
+
+  /* USER CODE BEGIN UART8_Init 1 */
+
+  /* USER CODE END UART8_Init 1 */
+  huart8.Instance = UART8;
+  huart8.Init.BaudRate = 115200;
+  huart8.Init.WordLength = UART_WORDLENGTH_8B;
+  huart8.Init.StopBits = UART_STOPBITS_1;
+  huart8.Init.Parity = UART_PARITY_NONE;
+  huart8.Init.Mode = UART_MODE_TX_RX;
+  huart8.Init.HwFlowCtl = UART_HWCONTROL_NONE;
+  huart8.Init.OverSampling = UART_OVERSAMPLING_16;
+  huart8.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
+  huart8.Init.ClockPrescaler = UART_PRESCALER_DIV1;
+  huart8.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
+  if (HAL_UART_Init(&huart8) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_UARTEx_SetTxFifoThreshold(&huart8, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_UARTEx_SetRxFifoThreshold(&huart8, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_UARTEx_DisableFifoMode(&huart8) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN UART8_Init 2 */
+
+  /* USER CODE END UART8_Init 2 */
+
+}
+
+/**
+  * Enable DMA controller clock
+  */
+static void MX_DMA_Init(void)
+{
+
+  /* DMA controller clock enable */
+  __HAL_RCC_DMA1_CLK_ENABLE();
+
+  /* DMA interrupt init */
+  /* DMA1_Stream0_IRQn interrupt configuration */
+  HAL_NVIC_SetPriority(DMA1_Stream0_IRQn, 5, 0);
+  HAL_NVIC_EnableIRQ(DMA1_Stream0_IRQn);
+
+}
+
+/**
+  * Enable MDMA controller clock
+  * Configure MDMA for global transfers
+  *   hmdma_mdma_channel0_sdmmc1_end_data_0
+  */
+static void MX_MDMA_Init(void)
+{
+
+  /* MDMA controller clock enable */
+  __HAL_RCC_MDMA_CLK_ENABLE();
+  /* Local variables */
+
+  /* Configure MDMA channel MDMA_Channel0 */
+  /* Configure MDMA request hmdma_mdma_channel0_sdmmc1_end_data_0 on MDMA_Channel0 */
+  hmdma_mdma_channel0_sdmmc1_end_data_0.Instance = MDMA_Channel0;
+  hmdma_mdma_channel0_sdmmc1_end_data_0.Init.Request = MDMA_REQUEST_SDMMC1_END_DATA;
+  hmdma_mdma_channel0_sdmmc1_end_data_0.Init.TransferTriggerMode = MDMA_BUFFER_TRANSFER;
+  hmdma_mdma_channel0_sdmmc1_end_data_0.Init.Priority = MDMA_PRIORITY_LOW;
+  hmdma_mdma_channel0_sdmmc1_end_data_0.Init.Endianness = MDMA_LITTLE_ENDIANNESS_PRESERVE;
+  hmdma_mdma_channel0_sdmmc1_end_data_0.Init.SourceInc = MDMA_SRC_INC_BYTE;
+  hmdma_mdma_channel0_sdmmc1_end_data_0.Init.DestinationInc = MDMA_DEST_INC_BYTE;
+  hmdma_mdma_channel0_sdmmc1_end_data_0.Init.SourceDataSize = MDMA_SRC_DATASIZE_BYTE;
+  hmdma_mdma_channel0_sdmmc1_end_data_0.Init.DestDataSize = MDMA_DEST_DATASIZE_BYTE;
+  hmdma_mdma_channel0_sdmmc1_end_data_0.Init.DataAlignment = MDMA_DATAALIGN_PACKENABLE;
+  hmdma_mdma_channel0_sdmmc1_end_data_0.Init.BufferTransferLength = 1;
+  hmdma_mdma_channel0_sdmmc1_end_data_0.Init.SourceBurst = MDMA_SOURCE_BURST_SINGLE;
+  hmdma_mdma_channel0_sdmmc1_end_data_0.Init.DestBurst = MDMA_DEST_BURST_SINGLE;
+  hmdma_mdma_channel0_sdmmc1_end_data_0.Init.SourceBlockAddressOffset = 0;
+  hmdma_mdma_channel0_sdmmc1_end_data_0.Init.DestBlockAddressOffset = 0;
+  if (HAL_MDMA_Init(&hmdma_mdma_channel0_sdmmc1_end_data_0) != HAL_OK)
+  {
+    Error_Handler();
+  }
+
+  /* Configure post request address and data masks */
+  if (HAL_MDMA_ConfigPostRequestMask(&hmdma_mdma_channel0_sdmmc1_end_data_0, 0, 0) != HAL_OK)
+  {
+    Error_Handler();
+  }
+
+  /* MDMA interrupt initialization */
+  /* MDMA_IRQn interrupt configuration */
+  HAL_NVIC_SetPriority(MDMA_IRQn, 5, 0);
+  HAL_NVIC_EnableIRQ(MDMA_IRQn);
+
+}
+
+/**
+  * @brief GPIO Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_GPIO_Init(void)
+{
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+/* USER CODE BEGIN MX_GPIO_Init_1 */
+/* USER CODE END MX_GPIO_Init_1 */
+
+  /* GPIO Ports Clock Enable */
+  __HAL_RCC_GPIOB_CLK_ENABLE();
+  __HAL_RCC_GPIOA_CLK_ENABLE();
+  __HAL_RCC_GPIOD_CLK_ENABLE();
+  __HAL_RCC_GPIOC_CLK_ENABLE();
+  __HAL_RCC_GPIOH_CLK_ENABLE();
+  __HAL_RCC_GPIOE_CLK_ENABLE();
+
+  /*Configure GPIO pin Output Level */
+  HAL_GPIO_WritePin(mLED_GPIO_Port, mLED_Pin, GPIO_PIN_RESET);
+
+  /*Configure GPIO pin Output Level */
+  HAL_GPIO_WritePin(GPIOE, SD_LED_Pin|VIN_ON_Pin|PICO_EN_Pin, GPIO_PIN_RESET);
+
+  /*Configure GPIO pin : mLED_Pin */
+  GPIO_InitStruct.Pin = mLED_Pin;
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+  HAL_GPIO_Init(mLED_GPIO_Port, &GPIO_InitStruct);
+
+  /*Configure GPIO pins : SD_LED_Pin VIN_ON_Pin PICO_EN_Pin */
+  GPIO_InitStruct.Pin = SD_LED_Pin|VIN_ON_Pin|PICO_EN_Pin;
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+  HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
+
+  /*Configure GPIO pin : sdDetect_Pin */
+  GPIO_InitStruct.Pin = sdDetect_Pin;
+  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  HAL_GPIO_Init(sdDetect_GPIO_Port, &GPIO_InitStruct);
+
+  /*Configure GPIO pins : VIN_IG_Pin VIN_1_4_Pin */
+  GPIO_InitStruct.Pin = VIN_IG_Pin|VIN_1_4_Pin;
+  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
+
+/* USER CODE BEGIN MX_GPIO_Init_2 */
+/* USER CODE END MX_GPIO_Init_2 */
 }
 
 /* USER CODE BEGIN 4 */
+void lwftp_init(void) {
+	IP4_ADDR(&s.cli_ip, CLI_IP[0], CLI_IP[1], CLI_IP[2], CLI_IP[3]);
+	IP4_ADDR(&s.svr_ip, SVR_IP[0], SVR_IP[1], SVR_IP[2], SVR_IP[3]);
+	s.svr_port = SVR_PORT;
+	s.user = USER;
+	s.pass = PASS;
+
+	printf("\n>> lwftp: cli ip: %d.%d.%d.%d\r\n", CLI_IP[0], CLI_IP[1], CLI_IP[2], CLI_IP[3]);
+	printf(">> lwftp: svr ip: %d.%d.%d.%d\r\n", SVR_IP[0], SVR_IP[1], SVR_IP[2], SVR_IP[3]);
+	printf(">> lwftp: svr port: %d\r\n", s.svr_port);
+	printf(">> lwftp: username: %s\r\n", s.user);
+	printf(">> lwftp: password: %s\r\n\n", s.pass);
+
+#if FTPSemaphore
+	sys_sem_new(&ftpsem, 0); // the semaphore would prevent simultaneous access to lwftp_send
+#endif
+
+	/* Thread for Control connection*/
+	sys_thread_new("lwftp_ctrl_thread", lwftp_ctrl_thread, (void*) &s,
+	DEFAULT_THREAD_STACKSIZE, osPriorityNormal);
+
+	/* Thread for Data connection*/
+	sys_thread_new("lwftp_data_thread", lwftp_data_thread, (void*) &s,
+	DEFAULT_THREAD_STACKSIZE, osPriorityNormal);
+}
 
 /* USER CODE END 4 */
 
+/* USER CODE BEGIN Header_StartDefaultTask */
+/**
+ * @brief  Function implementing the defaultTask thread.
+ * @param  argument: Not used
+ * @retval None
+ */
+/* USER CODE END Header_StartDefaultTask */
+void StartDefaultTask(void const * argument)
+{
+  /* init code for LWIP */
+  MX_LWIP_Init();
+  /* USER CODE BEGIN 5 */
+	printf("[INFO] Remaining stack size of task: %ld\r\n",
+			uxTaskGetStackHighWaterMark(NULL));
+	lwftp_init();
+
+	osDelay(5000); // run code aft 5s
+	err_t err;
+//	err = lwftp_list(&s);
+//	err = lwftp_store(&s, "foobar.txt", "TESTTESTTESTTESTTESTTESTTEST\r\n");
+	err = lwftp_retrieve(&s, "ftp_test_1.txt");
+
+	printf("%d\r\n",err);
+
+	/* Infinite loop */
+	for (;;) {
+		osDelay(1);
+	}
+  /* USER CODE END 5 */
+}
+
+/* USER CODE BEGIN Header_StartDebugTask */
+/**
+* @brief Function implementing the debugTask thread.
+* @param argument: Not used
+* @retval None
+*/
+/* USER CODE END Header_StartDebugTask */
+void StartDebugTask(void const * argument)
+{
+  /* USER CODE BEGIN StartDebugTask */
+  /* Infinite loop */
+  for(;;)
+  {
+    osDelay(1);
+  }
+  /* USER CODE END StartDebugTask */
+}
+
 /* MPU Configuration */
 
-void MPU_Config(void) {
-	MPU_Region_InitTypeDef MPU_InitStruct = { 0 };
+void MPU_Config(void)
+{
+  MPU_Region_InitTypeDef MPU_InitStruct = {0};
 
-	/* Disables the MPU */
-	HAL_MPU_Disable();
+  /* Disables the MPU */
+  HAL_MPU_Disable();
 
-	/** Initializes and configures the Region and the memory to be protected
-	 */
-	MPU_InitStruct.Enable = MPU_REGION_ENABLE;
-	MPU_InitStruct.Number = MPU_REGION_NUMBER0;
-	MPU_InitStruct.BaseAddress = 0x0;
-	MPU_InitStruct.Size = MPU_REGION_SIZE_4GB;
-	MPU_InitStruct.SubRegionDisable = 0x87;
-	MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0;
-	MPU_InitStruct.AccessPermission = MPU_REGION_NO_ACCESS;
-	MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_DISABLE;
-	MPU_InitStruct.IsShareable = MPU_ACCESS_SHAREABLE;
-	MPU_InitStruct.IsCacheable = MPU_ACCESS_NOT_CACHEABLE;
-	MPU_InitStruct.IsBufferable = MPU_ACCESS_NOT_BUFFERABLE;
+  /** Initializes and configures the Region and the memory to be protected
+  */
+  MPU_InitStruct.Enable = MPU_REGION_ENABLE;
+  MPU_InitStruct.Number = MPU_REGION_NUMBER0;
+  MPU_InitStruct.BaseAddress = 0x0;
+  MPU_InitStruct.Size = MPU_REGION_SIZE_4GB;
+  MPU_InitStruct.SubRegionDisable = 0x87;
+  MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0;
+  MPU_InitStruct.AccessPermission = MPU_REGION_NO_ACCESS;
+  MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_DISABLE;
+  MPU_InitStruct.IsShareable = MPU_ACCESS_SHAREABLE;
+  MPU_InitStruct.IsCacheable = MPU_ACCESS_NOT_CACHEABLE;
+  MPU_InitStruct.IsBufferable = MPU_ACCESS_NOT_BUFFERABLE;
 
-	HAL_MPU_ConfigRegion(&MPU_InitStruct);
+  HAL_MPU_ConfigRegion(&MPU_InitStruct);
 
-	/** Initializes and configures the Region and the memory to be protected
-	 */
-	MPU_InitStruct.Number = MPU_REGION_NUMBER1;
-	MPU_InitStruct.BaseAddress = 0x30000000;
-	MPU_InitStruct.Size = MPU_REGION_SIZE_32KB;
-	MPU_InitStruct.SubRegionDisable = 0x0;
-	MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL1;
-	MPU_InitStruct.AccessPermission = MPU_REGION_FULL_ACCESS;
-	MPU_InitStruct.IsShareable = MPU_ACCESS_NOT_SHAREABLE;
+  /** Initializes and configures the Region and the memory to be protected
+  */
+  MPU_InitStruct.Number = MPU_REGION_NUMBER1;
+  MPU_InitStruct.BaseAddress = 0x30000000;
+  MPU_InitStruct.Size = MPU_REGION_SIZE_32KB;
+  MPU_InitStruct.SubRegionDisable = 0x0;
+  MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL1;
+  MPU_InitStruct.AccessPermission = MPU_REGION_FULL_ACCESS;
+  MPU_InitStruct.IsShareable = MPU_ACCESS_NOT_SHAREABLE;
 
-	HAL_MPU_ConfigRegion(&MPU_InitStruct);
+  HAL_MPU_ConfigRegion(&MPU_InitStruct);
 
-	/** Initializes and configures the Region and the memory to be protected
-	 */
-	MPU_InitStruct.Number = MPU_REGION_NUMBER2;
-	MPU_InitStruct.Size = MPU_REGION_SIZE_512B;
-	MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0;
-	MPU_InitStruct.IsShareable = MPU_ACCESS_SHAREABLE;
-	MPU_InitStruct.IsBufferable = MPU_ACCESS_BUFFERABLE;
+  /** Initializes and configures the Region and the memory to be protected
+  */
+  MPU_InitStruct.Number = MPU_REGION_NUMBER2;
+  MPU_InitStruct.Size = MPU_REGION_SIZE_512B;
+  MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0;
+  MPU_InitStruct.IsShareable = MPU_ACCESS_SHAREABLE;
+  MPU_InitStruct.IsBufferable = MPU_ACCESS_BUFFERABLE;
 
-	HAL_MPU_ConfigRegion(&MPU_InitStruct);
-	/* Enables the MPU */
-	HAL_MPU_Enable(MPU_PRIVILEGED_DEFAULT);
+  HAL_MPU_ConfigRegion(&MPU_InitStruct);
+
+  /** Initializes and configures the Region and the memory to be protected
+  */
+  MPU_InitStruct.Number = MPU_REGION_NUMBER3;
+  MPU_InitStruct.BaseAddress = 0x24000000;
+  MPU_InitStruct.Size = MPU_REGION_SIZE_128KB;
+  MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL1;
+  MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_ENABLE;
+  MPU_InitStruct.IsBufferable = MPU_ACCESS_NOT_BUFFERABLE;
+
+  HAL_MPU_ConfigRegion(&MPU_InitStruct);
+  /* Enables the MPU */
+  HAL_MPU_Enable(MPU_PRIVILEGED_DEFAULT);
 
 }
 
 /**
- * @brief  This function is executed in case of error occurrence.
- * @retval None
- */
-void Error_Handler(void) {
-	/* USER CODE BEGIN Error_Handler_Debug */
+  * @brief  Period elapsed callback in non blocking mode
+  * @note   This function is called  when TIM6 interrupt took place, inside
+  * HAL_TIM_IRQHandler(). It makes a direct call to HAL_IncTick() to increment
+  * a global variable "uwTick" used as application time base.
+  * @param  htim : TIM handle
+  * @retval None
+  */
+void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
+{
+  /* USER CODE BEGIN Callback 0 */
+
+  /* USER CODE END Callback 0 */
+  if (htim->Instance == TIM6) {
+    HAL_IncTick();
+  }
+  /* USER CODE BEGIN Callback 1 */
+
+  /* USER CODE END Callback 1 */
+}
+
+/**
+  * @brief  This function is executed in case of error occurrence.
+  * @retval None
+  */
+void Error_Handler(void)
+{
+  /* USER CODE BEGIN Error_Handler_Debug */
 	/* User can add his own implementation to report the HAL error return state */
 	__disable_irq();
 	while (1) {
 	}
-	/* USER CODE END Error_Handler_Debug */
+  /* USER CODE END Error_Handler_Debug */
 }
 
 #ifdef  USE_FULL_ASSERT
diff --git a/Core/Src/stm32h7xx_hal_msp.c b/Core/Src/stm32h7xx_hal_msp.c
index d0a0d91..19f82d0 100644
--- a/Core/Src/stm32h7xx_hal_msp.c
+++ b/Core/Src/stm32h7xx_hal_msp.c
@@ -24,6 +24,7 @@
 /* USER CODE BEGIN Includes */
 
 /* USER CODE END Includes */
+extern DMA_HandleTypeDef hdma_uart8_rx;
 
 /* Private typedef -----------------------------------------------------------*/
 /* USER CODE BEGIN TD */
@@ -70,12 +71,575 @@ void HAL_MspInit(void)
   __HAL_RCC_SYSCFG_CLK_ENABLE();
 
   /* System interrupt init*/
+  /* PendSV_IRQn interrupt configuration */
+  HAL_NVIC_SetPriority(PendSV_IRQn, 15, 0);
 
   /* USER CODE BEGIN MspInit 1 */
 
   /* USER CODE END MspInit 1 */
 }
 
+static uint32_t HAL_RCC_FDCAN_CLK_ENABLED=0;
+
+/**
+* @brief FDCAN MSP Initialization
+* This function configures the hardware resources used in this example
+* @param hfdcan: FDCAN handle pointer
+* @retval None
+*/
+void HAL_FDCAN_MspInit(FDCAN_HandleTypeDef* hfdcan)
+{
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+  RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
+  if(hfdcan->Instance==FDCAN1)
+  {
+  /* USER CODE BEGIN FDCAN1_MspInit 0 */
+
+  /* USER CODE END FDCAN1_MspInit 0 */
+
+  /** Initializes the peripherals clock
+  */
+    PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_FDCAN;
+    PeriphClkInitStruct.FdcanClockSelection = RCC_FDCANCLKSOURCE_PLL;
+    if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
+    {
+      Error_Handler();
+    }
+
+    /* Peripheral clock enable */
+    HAL_RCC_FDCAN_CLK_ENABLED++;
+    if(HAL_RCC_FDCAN_CLK_ENABLED==1){
+      __HAL_RCC_FDCAN_CLK_ENABLE();
+    }
+
+    __HAL_RCC_GPIOB_CLK_ENABLE();
+    /**FDCAN1 GPIO Configuration
+    PB9     ------> FDCAN1_TX
+    PB8     ------> FDCAN1_RX
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_8;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+    GPIO_InitStruct.Alternate = GPIO_AF9_FDCAN1;
+    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+
+    /* FDCAN1 interrupt Init */
+    HAL_NVIC_SetPriority(FDCAN1_IT0_IRQn, 5, 0);
+    HAL_NVIC_EnableIRQ(FDCAN1_IT0_IRQn);
+  /* USER CODE BEGIN FDCAN1_MspInit 1 */
+
+  /* USER CODE END FDCAN1_MspInit 1 */
+  }
+  else if(hfdcan->Instance==FDCAN2)
+  {
+  /* USER CODE BEGIN FDCAN2_MspInit 0 */
+
+  /* USER CODE END FDCAN2_MspInit 0 */
+
+  /** Initializes the peripherals clock
+  */
+    PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_FDCAN;
+    PeriphClkInitStruct.FdcanClockSelection = RCC_FDCANCLKSOURCE_PLL;
+    if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
+    {
+      Error_Handler();
+    }
+
+    /* Peripheral clock enable */
+    HAL_RCC_FDCAN_CLK_ENABLED++;
+    if(HAL_RCC_FDCAN_CLK_ENABLED==1){
+      __HAL_RCC_FDCAN_CLK_ENABLE();
+    }
+
+    __HAL_RCC_GPIOB_CLK_ENABLE();
+    /**FDCAN2 GPIO Configuration
+    PB6     ------> FDCAN2_TX
+    PB5     ------> FDCAN2_RX
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_5;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+    GPIO_InitStruct.Alternate = GPIO_AF9_FDCAN2;
+    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+
+    /* FDCAN2 interrupt Init */
+    HAL_NVIC_SetPriority(FDCAN2_IT0_IRQn, 5, 0);
+    HAL_NVIC_EnableIRQ(FDCAN2_IT0_IRQn);
+  /* USER CODE BEGIN FDCAN2_MspInit 1 */
+
+  /* USER CODE END FDCAN2_MspInit 1 */
+  }
+  else if(hfdcan->Instance==FDCAN3)
+  {
+  /* USER CODE BEGIN FDCAN3_MspInit 0 */
+
+  /* USER CODE END FDCAN3_MspInit 0 */
+
+  /** Initializes the peripherals clock
+  */
+    PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_FDCAN;
+    PeriphClkInitStruct.FdcanClockSelection = RCC_FDCANCLKSOURCE_PLL;
+    if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
+    {
+      Error_Handler();
+    }
+
+    /* Peripheral clock enable */
+    HAL_RCC_FDCAN_CLK_ENABLED++;
+    if(HAL_RCC_FDCAN_CLK_ENABLED==1){
+      __HAL_RCC_FDCAN_CLK_ENABLE();
+    }
+
+    __HAL_RCC_GPIOD_CLK_ENABLE();
+    /**FDCAN3 GPIO Configuration
+    PD13     ------> FDCAN3_TX
+    PD12     ------> FDCAN3_RX
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_13|GPIO_PIN_12;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+    GPIO_InitStruct.Alternate = GPIO_AF5_FDCAN3;
+    HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
+
+    /* FDCAN3 interrupt Init */
+    HAL_NVIC_SetPriority(FDCAN3_IT0_IRQn, 5, 0);
+    HAL_NVIC_EnableIRQ(FDCAN3_IT0_IRQn);
+  /* USER CODE BEGIN FDCAN3_MspInit 1 */
+
+  /* USER CODE END FDCAN3_MspInit 1 */
+  }
+
+}
+
+/**
+* @brief FDCAN MSP De-Initialization
+* This function freeze the hardware resources used in this example
+* @param hfdcan: FDCAN handle pointer
+* @retval None
+*/
+void HAL_FDCAN_MspDeInit(FDCAN_HandleTypeDef* hfdcan)
+{
+  if(hfdcan->Instance==FDCAN1)
+  {
+  /* USER CODE BEGIN FDCAN1_MspDeInit 0 */
+
+  /* USER CODE END FDCAN1_MspDeInit 0 */
+    /* Peripheral clock disable */
+    HAL_RCC_FDCAN_CLK_ENABLED--;
+    if(HAL_RCC_FDCAN_CLK_ENABLED==0){
+      __HAL_RCC_FDCAN_CLK_DISABLE();
+    }
+
+    /**FDCAN1 GPIO Configuration
+    PB9     ------> FDCAN1_TX
+    PB8     ------> FDCAN1_RX
+    */
+    HAL_GPIO_DeInit(GPIOB, GPIO_PIN_9|GPIO_PIN_8);
+
+    /* FDCAN1 interrupt DeInit */
+    HAL_NVIC_DisableIRQ(FDCAN1_IT0_IRQn);
+  /* USER CODE BEGIN FDCAN1_MspDeInit 1 */
+
+  /* USER CODE END FDCAN1_MspDeInit 1 */
+  }
+  else if(hfdcan->Instance==FDCAN2)
+  {
+  /* USER CODE BEGIN FDCAN2_MspDeInit 0 */
+
+  /* USER CODE END FDCAN2_MspDeInit 0 */
+    /* Peripheral clock disable */
+    HAL_RCC_FDCAN_CLK_ENABLED--;
+    if(HAL_RCC_FDCAN_CLK_ENABLED==0){
+      __HAL_RCC_FDCAN_CLK_DISABLE();
+    }
+
+    /**FDCAN2 GPIO Configuration
+    PB6     ------> FDCAN2_TX
+    PB5     ------> FDCAN2_RX
+    */
+    HAL_GPIO_DeInit(GPIOB, GPIO_PIN_6|GPIO_PIN_5);
+
+    /* FDCAN2 interrupt DeInit */
+    HAL_NVIC_DisableIRQ(FDCAN2_IT0_IRQn);
+  /* USER CODE BEGIN FDCAN2_MspDeInit 1 */
+
+  /* USER CODE END FDCAN2_MspDeInit 1 */
+  }
+  else if(hfdcan->Instance==FDCAN3)
+  {
+  /* USER CODE BEGIN FDCAN3_MspDeInit 0 */
+
+  /* USER CODE END FDCAN3_MspDeInit 0 */
+    /* Peripheral clock disable */
+    HAL_RCC_FDCAN_CLK_ENABLED--;
+    if(HAL_RCC_FDCAN_CLK_ENABLED==0){
+      __HAL_RCC_FDCAN_CLK_DISABLE();
+    }
+
+    /**FDCAN3 GPIO Configuration
+    PD13     ------> FDCAN3_TX
+    PD12     ------> FDCAN3_RX
+    */
+    HAL_GPIO_DeInit(GPIOD, GPIO_PIN_13|GPIO_PIN_12);
+
+    /* FDCAN3 interrupt DeInit */
+    HAL_NVIC_DisableIRQ(FDCAN3_IT0_IRQn);
+  /* USER CODE BEGIN FDCAN3_MspDeInit 1 */
+
+  /* USER CODE END FDCAN3_MspDeInit 1 */
+  }
+
+}
+
+/**
+* @brief SD MSP Initialization
+* This function configures the hardware resources used in this example
+* @param hsd: SD handle pointer
+* @retval None
+*/
+void HAL_SD_MspInit(SD_HandleTypeDef* hsd)
+{
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+  RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
+  if(hsd->Instance==SDMMC1)
+  {
+  /* USER CODE BEGIN SDMMC1_MspInit 0 */
+
+  /* USER CODE END SDMMC1_MspInit 0 */
+
+  /** Initializes the peripherals clock
+  */
+    PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_SDMMC;
+    PeriphClkInitStruct.SdmmcClockSelection = RCC_SDMMCCLKSOURCE_PLL;
+    if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
+    {
+      Error_Handler();
+    }
+
+    /* Peripheral clock enable */
+    __HAL_RCC_SDMMC1_CLK_ENABLE();
+
+    __HAL_RCC_GPIOD_CLK_ENABLE();
+    __HAL_RCC_GPIOC_CLK_ENABLE();
+    /**SDMMC1 GPIO Configuration
+    PD2     ------> SDMMC1_CMD
+    PC11     ------> SDMMC1_D3
+    PC10     ------> SDMMC1_D2
+    PC12     ------> SDMMC1_CK
+    PC9     ------> SDMMC1_D1
+    PC8     ------> SDMMC1_D0
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_2;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+    GPIO_InitStruct.Alternate = GPIO_AF12_SDMMC1;
+    HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
+
+    GPIO_InitStruct.Pin = GPIO_PIN_11|GPIO_PIN_10|GPIO_PIN_12|GPIO_PIN_9
+                          |GPIO_PIN_8;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+    GPIO_InitStruct.Alternate = GPIO_AF12_SDMMC1;
+    HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
+
+    /* SDMMC1 interrupt Init */
+    HAL_NVIC_SetPriority(SDMMC1_IRQn, 5, 0);
+    HAL_NVIC_EnableIRQ(SDMMC1_IRQn);
+  /* USER CODE BEGIN SDMMC1_MspInit 1 */
+
+  /* USER CODE END SDMMC1_MspInit 1 */
+  }
+
+}
+
+/**
+* @brief SD MSP De-Initialization
+* This function freeze the hardware resources used in this example
+* @param hsd: SD handle pointer
+* @retval None
+*/
+void HAL_SD_MspDeInit(SD_HandleTypeDef* hsd)
+{
+  if(hsd->Instance==SDMMC1)
+  {
+  /* USER CODE BEGIN SDMMC1_MspDeInit 0 */
+
+  /* USER CODE END SDMMC1_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_SDMMC1_CLK_DISABLE();
+
+    /**SDMMC1 GPIO Configuration
+    PD2     ------> SDMMC1_CMD
+    PC11     ------> SDMMC1_D3
+    PC10     ------> SDMMC1_D2
+    PC12     ------> SDMMC1_CK
+    PC9     ------> SDMMC1_D1
+    PC8     ------> SDMMC1_D0
+    */
+    HAL_GPIO_DeInit(GPIOD, GPIO_PIN_2);
+
+    HAL_GPIO_DeInit(GPIOC, GPIO_PIN_11|GPIO_PIN_10|GPIO_PIN_12|GPIO_PIN_9
+                          |GPIO_PIN_8);
+
+    /* SDMMC1 interrupt DeInit */
+    HAL_NVIC_DisableIRQ(SDMMC1_IRQn);
+  /* USER CODE BEGIN SDMMC1_MspDeInit 1 */
+
+  /* USER CODE END SDMMC1_MspDeInit 1 */
+  }
+
+}
+
+/**
+* @brief TIM_Base MSP Initialization
+* This function configures the hardware resources used in this example
+* @param htim_base: TIM_Base handle pointer
+* @retval None
+*/
+void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base)
+{
+  if(htim_base->Instance==TIM3)
+  {
+  /* USER CODE BEGIN TIM3_MspInit 0 */
+
+  /* USER CODE END TIM3_MspInit 0 */
+    /* Peripheral clock enable */
+    __HAL_RCC_TIM3_CLK_ENABLE();
+  /* USER CODE BEGIN TIM3_MspInit 1 */
+
+  /* USER CODE END TIM3_MspInit 1 */
+  }
+
+}
+
+/**
+* @brief TIM_Base MSP De-Initialization
+* This function freeze the hardware resources used in this example
+* @param htim_base: TIM_Base handle pointer
+* @retval None
+*/
+void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef* htim_base)
+{
+  if(htim_base->Instance==TIM3)
+  {
+  /* USER CODE BEGIN TIM3_MspDeInit 0 */
+
+  /* USER CODE END TIM3_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_TIM3_CLK_DISABLE();
+  /* USER CODE BEGIN TIM3_MspDeInit 1 */
+
+  /* USER CODE END TIM3_MspDeInit 1 */
+  }
+
+}
+
+/**
+* @brief UART MSP Initialization
+* This function configures the hardware resources used in this example
+* @param huart: UART handle pointer
+* @retval None
+*/
+void HAL_UART_MspInit(UART_HandleTypeDef* huart)
+{
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+  RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
+  if(huart->Instance==UART4)
+  {
+  /* USER CODE BEGIN UART4_MspInit 0 */
+
+  /* USER CODE END UART4_MspInit 0 */
+
+  /** Initializes the peripherals clock
+  */
+    PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_UART4;
+    PeriphClkInitStruct.Usart234578ClockSelection = RCC_USART234578CLKSOURCE_D2PCLK1;
+    if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
+    {
+      Error_Handler();
+    }
+
+    /* Peripheral clock enable */
+    __HAL_RCC_UART4_CLK_ENABLE();
+
+    __HAL_RCC_GPIOD_CLK_ENABLE();
+    /**UART4 GPIO Configuration
+    PD0     ------> UART4_RX
+    PD1     ------> UART4_TX
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+    GPIO_InitStruct.Alternate = GPIO_AF8_UART4;
+    HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
+
+  /* USER CODE BEGIN UART4_MspInit 1 */
+
+  /* USER CODE END UART4_MspInit 1 */
+  }
+  else if(huart->Instance==UART7)
+  {
+  /* USER CODE BEGIN UART7_MspInit 0 */
+
+  /* USER CODE END UART7_MspInit 0 */
+
+  /** Initializes the peripherals clock
+  */
+    PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_UART7;
+    PeriphClkInitStruct.Usart234578ClockSelection = RCC_USART234578CLKSOURCE_D2PCLK1;
+    if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
+    {
+      Error_Handler();
+    }
+
+    /* Peripheral clock enable */
+    __HAL_RCC_UART7_CLK_ENABLE();
+
+    __HAL_RCC_GPIOE_CLK_ENABLE();
+    /**UART7 GPIO Configuration
+    PE7     ------> UART7_RX
+    PE8     ------> UART7_TX
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_7|GPIO_PIN_8;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+    GPIO_InitStruct.Alternate = GPIO_AF7_UART7;
+    HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
+
+  /* USER CODE BEGIN UART7_MspInit 1 */
+
+  /* USER CODE END UART7_MspInit 1 */
+  }
+  else if(huart->Instance==UART8)
+  {
+  /* USER CODE BEGIN UART8_MspInit 0 */
+
+  /* USER CODE END UART8_MspInit 0 */
+
+  /** Initializes the peripherals clock
+  */
+    PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_UART8;
+    PeriphClkInitStruct.Usart234578ClockSelection = RCC_USART234578CLKSOURCE_D2PCLK1;
+    if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
+    {
+      Error_Handler();
+    }
+
+    /* Peripheral clock enable */
+    __HAL_RCC_UART8_CLK_ENABLE();
+
+    __HAL_RCC_GPIOE_CLK_ENABLE();
+    /**UART8 GPIO Configuration
+    PE1     ------> UART8_TX
+    PE0     ------> UART8_RX
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_0;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+    GPIO_InitStruct.Alternate = GPIO_AF8_UART8;
+    HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
+
+    /* UART8 DMA Init */
+    /* UART8_RX Init */
+    hdma_uart8_rx.Instance = DMA1_Stream0;
+    hdma_uart8_rx.Init.Request = DMA_REQUEST_UART8_RX;
+    hdma_uart8_rx.Init.Direction = DMA_PERIPH_TO_MEMORY;
+    hdma_uart8_rx.Init.PeriphInc = DMA_PINC_DISABLE;
+    hdma_uart8_rx.Init.MemInc = DMA_MINC_ENABLE;
+    hdma_uart8_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
+    hdma_uart8_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
+    hdma_uart8_rx.Init.Mode = DMA_CIRCULAR;
+    hdma_uart8_rx.Init.Priority = DMA_PRIORITY_LOW;
+    hdma_uart8_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
+    if (HAL_DMA_Init(&hdma_uart8_rx) != HAL_OK)
+    {
+      Error_Handler();
+    }
+
+    __HAL_LINKDMA(huart,hdmarx,hdma_uart8_rx);
+
+  /* USER CODE BEGIN UART8_MspInit 1 */
+
+  /* USER CODE END UART8_MspInit 1 */
+  }
+
+}
+
+/**
+* @brief UART MSP De-Initialization
+* This function freeze the hardware resources used in this example
+* @param huart: UART handle pointer
+* @retval None
+*/
+void HAL_UART_MspDeInit(UART_HandleTypeDef* huart)
+{
+  if(huart->Instance==UART4)
+  {
+  /* USER CODE BEGIN UART4_MspDeInit 0 */
+
+  /* USER CODE END UART4_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_UART4_CLK_DISABLE();
+
+    /**UART4 GPIO Configuration
+    PD0     ------> UART4_RX
+    PD1     ------> UART4_TX
+    */
+    HAL_GPIO_DeInit(GPIOD, GPIO_PIN_0|GPIO_PIN_1);
+
+  /* USER CODE BEGIN UART4_MspDeInit 1 */
+
+  /* USER CODE END UART4_MspDeInit 1 */
+  }
+  else if(huart->Instance==UART7)
+  {
+  /* USER CODE BEGIN UART7_MspDeInit 0 */
+
+  /* USER CODE END UART7_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_UART7_CLK_DISABLE();
+
+    /**UART7 GPIO Configuration
+    PE7     ------> UART7_RX
+    PE8     ------> UART7_TX
+    */
+    HAL_GPIO_DeInit(GPIOE, GPIO_PIN_7|GPIO_PIN_8);
+
+  /* USER CODE BEGIN UART7_MspDeInit 1 */
+
+  /* USER CODE END UART7_MspDeInit 1 */
+  }
+  else if(huart->Instance==UART8)
+  {
+  /* USER CODE BEGIN UART8_MspDeInit 0 */
+
+  /* USER CODE END UART8_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_UART8_CLK_DISABLE();
+
+    /**UART8 GPIO Configuration
+    PE1     ------> UART8_TX
+    PE0     ------> UART8_RX
+    */
+    HAL_GPIO_DeInit(GPIOE, GPIO_PIN_1|GPIO_PIN_0);
+
+    /* UART8 DMA DeInit */
+    HAL_DMA_DeInit(huart->hdmarx);
+  /* USER CODE BEGIN UART8_MspDeInit 1 */
+
+  /* USER CODE END UART8_MspDeInit 1 */
+  }
+
+}
+
 /* USER CODE BEGIN 1 */
 
 /* USER CODE END 1 */
diff --git a/Core/Src/stm32h7xx_hal_timebase_tim.c b/Core/Src/stm32h7xx_hal_timebase_tim.c
new file mode 100644
index 0000000..8810acf
--- /dev/null
+++ b/Core/Src/stm32h7xx_hal_timebase_tim.c
@@ -0,0 +1,131 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_timebase_tim.c
+  * @brief   HAL time base based on the hardware TIM.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2024 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal.h"
+#include "stm32h7xx_hal_tim.h"
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+TIM_HandleTypeDef        htim6;
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/**
+  * @brief  This function configures the TIM6 as a time base source.
+  *         The time source is configured  to have 1ms time base with a dedicated
+  *         Tick interrupt priority.
+  * @note   This function is called  automatically at the beginning of program after
+  *         reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig().
+  * @param  TickPriority: Tick interrupt priority.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
+{
+  RCC_ClkInitTypeDef    clkconfig;
+  uint32_t              uwTimclock, uwAPB1Prescaler;
+
+  uint32_t              uwPrescalerValue;
+  uint32_t              pFLatency;
+/*Configure the TIM6 IRQ priority */
+  if (TickPriority < (1UL << __NVIC_PRIO_BITS))
+  {
+  HAL_NVIC_SetPriority(TIM6_DAC_IRQn, TickPriority ,0U);
+
+  /* Enable the TIM6 global Interrupt */
+  HAL_NVIC_EnableIRQ(TIM6_DAC_IRQn);
+    uwTickPrio = TickPriority;
+    }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  /* Enable TIM6 clock */
+  __HAL_RCC_TIM6_CLK_ENABLE();
+
+  /* Get clock configuration */
+  HAL_RCC_GetClockConfig(&clkconfig, &pFLatency);
+
+  /* Get APB1 prescaler */
+  uwAPB1Prescaler = clkconfig.APB1CLKDivider;
+  /* Compute TIM6 clock */
+  if (uwAPB1Prescaler == RCC_HCLK_DIV1)
+  {
+    uwTimclock = HAL_RCC_GetPCLK1Freq();
+  }
+  else
+  {
+    uwTimclock = 2UL * HAL_RCC_GetPCLK1Freq();
+  }
+
+  /* Compute the prescaler value to have TIM6 counter clock equal to 1MHz */
+  uwPrescalerValue = (uint32_t) ((uwTimclock / 1000000U) - 1U);
+
+  /* Initialize TIM6 */
+  htim6.Instance = TIM6;
+
+  /* Initialize TIMx peripheral as follow:
+
+  + Period = [(TIM6CLK/1000) - 1]. to have a (1/1000) s time base.
+  + Prescaler = (uwTimclock/1000000 - 1) to have a 1MHz counter clock.
+  + ClockDivision = 0
+  + Counter direction = Up
+  */
+  htim6.Init.Period = (1000000U / 1000U) - 1U;
+  htim6.Init.Prescaler = uwPrescalerValue;
+  htim6.Init.ClockDivision = 0;
+  htim6.Init.CounterMode = TIM_COUNTERMODE_UP;
+
+  if(HAL_TIM_Base_Init(&htim6) == HAL_OK)
+  {
+    /* Start the TIM time Base generation in interrupt mode */
+    return HAL_TIM_Base_Start_IT(&htim6);
+  }
+
+  /* Return function status */
+  return HAL_ERROR;
+}
+
+/**
+  * @brief  Suspend Tick increment.
+  * @note   Disable the tick increment by disabling TIM6 update interrupt.
+  * @param  None
+  * @retval None
+  */
+void HAL_SuspendTick(void)
+{
+  /* Disable TIM6 update Interrupt */
+  __HAL_TIM_DISABLE_IT(&htim6, TIM_IT_UPDATE);
+}
+
+/**
+  * @brief  Resume Tick increment.
+  * @note   Enable the tick increment by Enabling TIM6 update interrupt.
+  * @param  None
+  * @retval None
+  */
+void HAL_ResumeTick(void)
+{
+  /* Enable TIM6 Update interrupt */
+  __HAL_TIM_ENABLE_IT(&htim6, TIM_IT_UPDATE);
+}
+
diff --git a/Core/Src/stm32h7xx_it.c b/Core/Src/stm32h7xx_it.c
index 8cd685b..fb68af1 100644
--- a/Core/Src/stm32h7xx_it.c
+++ b/Core/Src/stm32h7xx_it.c
@@ -56,6 +56,14 @@
 
 /* External variables --------------------------------------------------------*/
 extern ETH_HandleTypeDef heth;
+extern FDCAN_HandleTypeDef hfdcan1;
+extern FDCAN_HandleTypeDef hfdcan2;
+extern FDCAN_HandleTypeDef hfdcan3;
+extern MDMA_HandleTypeDef hmdma_mdma_channel0_sdmmc1_end_data_0;
+extern SD_HandleTypeDef hsd1;
+extern DMA_HandleTypeDef hdma_uart8_rx;
+extern TIM_HandleTypeDef htim6;
+
 /* USER CODE BEGIN EV */
 
 /* USER CODE END EV */
@@ -138,19 +146,6 @@ void UsageFault_Handler(void)
   }
 }
 
-/**
-  * @brief This function handles System service call via SWI instruction.
-  */
-void SVC_Handler(void)
-{
-  /* USER CODE BEGIN SVCall_IRQn 0 */
-
-  /* USER CODE END SVCall_IRQn 0 */
-  /* USER CODE BEGIN SVCall_IRQn 1 */
-
-  /* USER CODE END SVCall_IRQn 1 */
-}
-
 /**
   * @brief This function handles Debug monitor.
   */
@@ -164,33 +159,6 @@ void DebugMon_Handler(void)
   /* USER CODE END DebugMonitor_IRQn 1 */
 }
 
-/**
-  * @brief This function handles Pendable request for system service.
-  */
-void PendSV_Handler(void)
-{
-  /* USER CODE BEGIN PendSV_IRQn 0 */
-
-  /* USER CODE END PendSV_IRQn 0 */
-  /* USER CODE BEGIN PendSV_IRQn 1 */
-
-  /* USER CODE END PendSV_IRQn 1 */
-}
-
-/**
-  * @brief This function handles System tick timer.
-  */
-void SysTick_Handler(void)
-{
-  /* USER CODE BEGIN SysTick_IRQn 0 */
-
-  /* USER CODE END SysTick_IRQn 0 */
-  HAL_IncTick();
-  /* USER CODE BEGIN SysTick_IRQn 1 */
-
-  /* USER CODE END SysTick_IRQn 1 */
-}
-
 /******************************************************************************/
 /* STM32H7xx Peripheral Interrupt Handlers                                    */
 /* Add here the Interrupt Handlers for the used peripherals.                  */
@@ -198,6 +166,76 @@ void SysTick_Handler(void)
 /* please refer to the startup file (startup_stm32h7xx.s).                    */
 /******************************************************************************/
 
+/**
+  * @brief This function handles DMA1 stream0 global interrupt.
+  */
+void DMA1_Stream0_IRQHandler(void)
+{
+  /* USER CODE BEGIN DMA1_Stream0_IRQn 0 */
+
+  /* USER CODE END DMA1_Stream0_IRQn 0 */
+  HAL_DMA_IRQHandler(&hdma_uart8_rx);
+  /* USER CODE BEGIN DMA1_Stream0_IRQn 1 */
+
+  /* USER CODE END DMA1_Stream0_IRQn 1 */
+}
+
+/**
+  * @brief This function handles FDCAN1 interrupt 0.
+  */
+void FDCAN1_IT0_IRQHandler(void)
+{
+  /* USER CODE BEGIN FDCAN1_IT0_IRQn 0 */
+
+  /* USER CODE END FDCAN1_IT0_IRQn 0 */
+  HAL_FDCAN_IRQHandler(&hfdcan1);
+  /* USER CODE BEGIN FDCAN1_IT0_IRQn 1 */
+
+  /* USER CODE END FDCAN1_IT0_IRQn 1 */
+}
+
+/**
+  * @brief This function handles FDCAN2 interrupt 0.
+  */
+void FDCAN2_IT0_IRQHandler(void)
+{
+  /* USER CODE BEGIN FDCAN2_IT0_IRQn 0 */
+
+  /* USER CODE END FDCAN2_IT0_IRQn 0 */
+  HAL_FDCAN_IRQHandler(&hfdcan2);
+  /* USER CODE BEGIN FDCAN2_IT0_IRQn 1 */
+
+  /* USER CODE END FDCAN2_IT0_IRQn 1 */
+}
+
+/**
+  * @brief This function handles SDMMC1 global interrupt.
+  */
+void SDMMC1_IRQHandler(void)
+{
+  /* USER CODE BEGIN SDMMC1_IRQn 0 */
+
+  /* USER CODE END SDMMC1_IRQn 0 */
+  HAL_SD_IRQHandler(&hsd1);
+  /* USER CODE BEGIN SDMMC1_IRQn 1 */
+
+  /* USER CODE END SDMMC1_IRQn 1 */
+}
+
+/**
+  * @brief This function handles TIM6 global interrupt, DAC1_CH1 and DAC1_CH2 underrun error interrupts.
+  */
+void TIM6_DAC_IRQHandler(void)
+{
+  /* USER CODE BEGIN TIM6_DAC_IRQn 0 */
+
+  /* USER CODE END TIM6_DAC_IRQn 0 */
+  HAL_TIM_IRQHandler(&htim6);
+  /* USER CODE BEGIN TIM6_DAC_IRQn 1 */
+
+  /* USER CODE END TIM6_DAC_IRQn 1 */
+}
+
 /**
   * @brief This function handles Ethernet global interrupt.
   */
@@ -212,6 +250,34 @@ void ETH_IRQHandler(void)
   /* USER CODE END ETH_IRQn 1 */
 }
 
+/**
+  * @brief This function handles MDMA global interrupt.
+  */
+void MDMA_IRQHandler(void)
+{
+  /* USER CODE BEGIN MDMA_IRQn 0 */
+
+  /* USER CODE END MDMA_IRQn 0 */
+  HAL_MDMA_IRQHandler(&hmdma_mdma_channel0_sdmmc1_end_data_0);
+  /* USER CODE BEGIN MDMA_IRQn 1 */
+
+  /* USER CODE END MDMA_IRQn 1 */
+}
+
+/**
+  * @brief This function handles FDCAN3 interrupt 0.
+  */
+void FDCAN3_IT0_IRQHandler(void)
+{
+  /* USER CODE BEGIN FDCAN3_IT0_IRQn 0 */
+
+  /* USER CODE END FDCAN3_IT0_IRQn 0 */
+  HAL_FDCAN_IRQHandler(&hfdcan3);
+  /* USER CODE BEGIN FDCAN3_IT0_IRQn 1 */
+
+  /* USER CODE END FDCAN3_IT0_IRQn 1 */
+}
+
 /* USER CODE BEGIN 1 */
 
 /* USER CODE END 1 */
diff --git a/Debug/Core/Src/freertos.cyclo b/Debug/Core/Src/freertos.cyclo
new file mode 100644
index 0000000..1fcc95a
--- /dev/null
+++ b/Debug/Core/Src/freertos.cyclo
@@ -0,0 +1,3 @@
+../Core/Src/freertos.c:65:13:vApplicationStackOverflowHook	1
+../Core/Src/freertos.c:77:6:vApplicationGetIdleTaskMemory	1
+../Core/Src/freertos.c:90:6:vApplicationGetTimerTaskMemory	1
diff --git a/Debug/Core/Src/freertos.d b/Debug/Core/Src/freertos.d
new file mode 100644
index 0000000..2eaa058
--- /dev/null
+++ b/Debug/Core/Src/freertos.d
@@ -0,0 +1,98 @@
+Core/Src/freertos.o: ../Core/Src/freertos.c \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h \
+ ../Core/Inc/FreeRTOSConfig.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/list.h \
+ ../Core/Inc/main.h ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \
+ ../Core/Inc/stm32h7xx_hal_conf.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h \
+ ../Drivers/CMSIS/Include/core_cm7.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h
+../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h:
+../Core/Inc/FreeRTOSConfig.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h:
+../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/task.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/list.h:
+../Core/Inc/main.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h:
+../Core/Inc/stm32h7xx_hal_conf.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h:
+../Drivers/CMSIS/Include/core_cm7.h:
+../Drivers/CMSIS/Include/cmsis_version.h:
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+../Drivers/CMSIS/Include/mpu_armv7.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
diff --git a/Debug/Core/Src/freertos.o b/Debug/Core/Src/freertos.o
new file mode 100644
index 0000000..c8c50c0
Binary files /dev/null and b/Debug/Core/Src/freertos.o differ
diff --git a/Debug/Core/Src/freertos.su b/Debug/Core/Src/freertos.su
new file mode 100644
index 0000000..4771319
--- /dev/null
+++ b/Debug/Core/Src/freertos.su
@@ -0,0 +1,3 @@
+../Core/Src/freertos.c:65:13:vApplicationStackOverflowHook	16	static
+../Core/Src/freertos.c:77:6:vApplicationGetIdleTaskMemory	24	static
+../Core/Src/freertos.c:90:6:vApplicationGetTimerTaskMemory	24	static
diff --git a/Debug/Core/Src/main.cyclo b/Debug/Core/Src/main.cyclo
index 738202f..6f599e8 100644
--- a/Debug/Core/Src/main.cyclo
+++ b/Debug/Core/Src/main.cyclo
@@ -1,14 +1,21 @@
 ../Drivers/CMSIS/Include/core_cm7.h:2660:26:ITM_SendChar	4
-../Core/Src/main.c:64:5:_write	2
-../Core/Src/main.c:78:13:LOG_TRACE	1
-../Core/Src/main.c:83:13:ftp_retr_callback	2
-../Core/Src/main.c:94:13:data_sink	2
-../Core/Src/main.c:107:13:ftp_stor_callback	3
-../Core/Src/main.c:126:13:data_source	4
-../Core/Src/main.c:146:13:ftp_connect_callback	2
-../Core/Src/main.c:172:13:ftp_test	2
-../Core/Src/main.c:201:5:main	5
-../Core/Src/main.c:259:6:SystemClock_Config	4
-../Core/Src/main.c:316:13:MX_GPIO_Init	1
-../Core/Src/main.c:336:6:MPU_Config	1
-../Core/Src/main.c:388:6:Error_Handler	1
+../Core/Src/main.c:107:5:_write	2
+../Core/Src/main.c:118:5:main	5
+../Core/Src/main.c:221:6:SystemClock_Config	4
+../Core/Src/main.c:280:13:MX_FDCAN1_Init	2
+../Core/Src/main.c:333:13:MX_FDCAN2_Init	2
+../Core/Src/main.c:386:13:MX_FDCAN3_Init	2
+../Core/Src/main.c:439:13:MX_SDMMC1_SD_Init	1
+../Core/Src/main.c:466:13:MX_TIM3_Init	4
+../Core/Src/main.c:511:13:MX_UART4_Init	5
+../Core/Src/main.c:559:13:MX_UART7_Init	5
+../Core/Src/main.c:607:13:MX_UART8_Init	5
+../Core/Src/main.c:653:13:MX_DMA_Init	1
+../Core/Src/main.c:671:13:MX_MDMA_Init	3
+../Core/Src/main.c:718:13:MX_GPIO_Init	1
+../Core/Src/main.c:769:6:lwftp_init	1
+../Core/Src/main.c:804:6:StartDefaultTask	1
+../Core/Src/main.c:835:6:StartDebugTask	1
+../Core/Src/main.c:848:6:MPU_Config	1
+../Core/Src/main.c:916:6:HAL_TIM_PeriodElapsedCallback	2
+../Core/Src/main.c:933:6:Error_Handler	1
diff --git a/Debug/Core/Src/main.d b/Debug/Core/Src/main.d
index 71a8c41..c1f1087 100644
--- a/Debug/Core/Src/main.d
+++ b/Debug/Core/Src/main.d
@@ -22,6 +22,7 @@ Core/Src/main.o: ../Core/Src/main.c ../Core/Inc/main.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
@@ -29,6 +30,37 @@ Core/Src/main.o: ../Core/Src/main.c ../Core/Inc/main.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h \
+ ../Core/Inc/FreeRTOSConfig.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/list.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h \
+ ../FATFS/App/fatfs.h ../Middlewares/Third_Party/FatFs/src/ff.h \
+ ../Middlewares/Third_Party/FatFs/src/integer.h ../FATFS/Target/ffconf.h \
+ ../FATFS/Target/bsp_driver_sd.h ../FATFS/Target/fatfs_platform.h \
+ ../Middlewares/Third_Party/FatFs/src/ff_gen_drv.h \
+ ../Middlewares/Third_Party/FatFs/src/diskio.h \
+ ../Middlewares/Third_Party/FatFs/src/ff.h ../FATFS/Target/sd_diskio.h \
  ../LWIP/App/lwip.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \
  ../LWIP/Target/lwipopts.h \
@@ -60,10 +92,13 @@ Core/Src/main.o: ../Core/Src/main.c ../Core/Inc/main.h \
  ../Middlewares/Third_Party/LwIP/src/include/netif/ethernet.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/dhcp.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/timeouts.h \
- ../LWIP/Target/ethernetif.h C:/_NoSleep/STM32/lwip_test/LWFTP/lwftp.h \
- ../Middlewares/Third_Party/LwIP/src/include/lwip/ip.h \
- ../Middlewares/Third_Party/LwIP/src/include/lwip/ip6.h \
- ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip.h
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/sys.h \
+ ../Middlewares/Third_Party/LwIP/system/arch/sys_arch.h \
+ ../LWIP/Target/ethernetif.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/tcpip.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/api.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/netbuf.h \
+ C:/_NoSleep/STM32/TBD_TaxiBoard/LWFTPC/lwftpc.h
 ../Core/Inc/main.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h:
 ../Core/Inc/stm32h7xx_hal_conf.h:
@@ -88,6 +123,7 @@ Core/Src/main.o: ../Core/Src/main.c ../Core/Inc/main.h \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
@@ -95,6 +131,41 @@ Core/Src/main.o: ../Core/Src/main.c ../Core/Inc/main.h \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h:
+../Core/Inc/FreeRTOSConfig.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h:
+../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/task.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/list.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/task.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h:
+../FATFS/App/fatfs.h:
+../Middlewares/Third_Party/FatFs/src/ff.h:
+../Middlewares/Third_Party/FatFs/src/integer.h:
+../FATFS/Target/ffconf.h:
+../FATFS/Target/bsp_driver_sd.h:
+../FATFS/Target/fatfs_platform.h:
+../Middlewares/Third_Party/FatFs/src/ff_gen_drv.h:
+../Middlewares/Third_Party/FatFs/src/diskio.h:
+../Middlewares/Third_Party/FatFs/src/ff.h:
+../FATFS/Target/sd_diskio.h:
 ../LWIP/App/lwip.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h:
 ../LWIP/Target/lwipopts.h:
@@ -126,8 +197,10 @@ Core/Src/main.o: ../Core/Src/main.c ../Core/Inc/main.h \
 ../Middlewares/Third_Party/LwIP/src/include/netif/ethernet.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/dhcp.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/timeouts.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/sys.h:
+../Middlewares/Third_Party/LwIP/system/arch/sys_arch.h:
 ../LWIP/Target/ethernetif.h:
-C:/_NoSleep/STM32/lwip_test/LWFTP/lwftp.h:
-../Middlewares/Third_Party/LwIP/src/include/lwip/ip.h:
-../Middlewares/Third_Party/LwIP/src/include/lwip/ip6.h:
-../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/tcpip.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/api.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/netbuf.h:
+C:/_NoSleep/STM32/TBD_TaxiBoard/LWFTPC/lwftpc.h:
diff --git a/Debug/Core/Src/main.o b/Debug/Core/Src/main.o
index 72c67e2..3f64a42 100644
Binary files a/Debug/Core/Src/main.o and b/Debug/Core/Src/main.o differ
diff --git a/Debug/Core/Src/main.su b/Debug/Core/Src/main.su
index 4774449..4daca66 100644
--- a/Debug/Core/Src/main.su
+++ b/Debug/Core/Src/main.su
@@ -1,14 +1,21 @@
 ../Drivers/CMSIS/Include/core_cm7.h:2660:26:ITM_SendChar	16	static,ignoring_inline_asm
-../Core/Src/main.c:64:5:_write	32	static
-../Core/Src/main.c:78:13:LOG_TRACE	16	static
-../Core/Src/main.c:83:13:ftp_retr_callback	24	static
-../Core/Src/main.c:94:13:data_sink	24	static
-../Core/Src/main.c:107:13:ftp_stor_callback	24	static
-../Core/Src/main.c:126:13:data_source	32	static
-../Core/Src/main.c:146:13:ftp_connect_callback	24	static
-../Core/Src/main.c:172:13:ftp_test	16	static
-../Core/Src/main.c:201:5:main	24	static,ignoring_inline_asm
-../Core/Src/main.c:259:6:SystemClock_Config	120	static
-../Core/Src/main.c:316:13:MX_GPIO_Init	24	static
-../Core/Src/main.c:336:6:MPU_Config	24	static
-../Core/Src/main.c:388:6:Error_Handler	4	static,ignoring_inline_asm
+../Core/Src/main.c:107:5:_write	32	static
+../Core/Src/main.c:118:5:main	88	static,ignoring_inline_asm
+../Core/Src/main.c:221:6:SystemClock_Config	120	static
+../Core/Src/main.c:280:13:MX_FDCAN1_Init	8	static
+../Core/Src/main.c:333:13:MX_FDCAN2_Init	8	static
+../Core/Src/main.c:386:13:MX_FDCAN3_Init	8	static
+../Core/Src/main.c:439:13:MX_SDMMC1_SD_Init	4	static
+../Core/Src/main.c:466:13:MX_TIM3_Init	40	static
+../Core/Src/main.c:511:13:MX_UART4_Init	8	static
+../Core/Src/main.c:559:13:MX_UART7_Init	8	static
+../Core/Src/main.c:607:13:MX_UART8_Init	8	static
+../Core/Src/main.c:653:13:MX_DMA_Init	16	static
+../Core/Src/main.c:671:13:MX_MDMA_Init	16	static
+../Core/Src/main.c:718:13:MX_GPIO_Init	56	static
+../Core/Src/main.c:769:6:lwftp_init	16	static
+../Core/Src/main.c:804:6:StartDefaultTask	24	static
+../Core/Src/main.c:835:6:StartDebugTask	16	static
+../Core/Src/main.c:848:6:MPU_Config	24	static
+../Core/Src/main.c:916:6:HAL_TIM_PeriodElapsedCallback	16	static
+../Core/Src/main.c:933:6:Error_Handler	4	static,ignoring_inline_asm
diff --git a/Debug/Core/Src/stm32h7xx_hal_msp.cyclo b/Debug/Core/Src/stm32h7xx_hal_msp.cyclo
index 5590235..f232532 100644
--- a/Debug/Core/Src/stm32h7xx_hal_msp.cyclo
+++ b/Debug/Core/Src/stm32h7xx_hal_msp.cyclo
@@ -1 +1,9 @@
-../Core/Src/stm32h7xx_hal_msp.c:64:6:HAL_MspInit	1
+../Core/Src/stm32h7xx_hal_msp.c:65:6:HAL_MspInit	1
+../Core/Src/stm32h7xx_hal_msp.c:90:6:HAL_FDCAN_MspInit	10
+../Core/Src/stm32h7xx_hal_msp.c:223:6:HAL_FDCAN_MspDeInit	7
+../Core/Src/stm32h7xx_hal_msp.c:303:6:HAL_SD_MspInit	3
+../Core/Src/stm32h7xx_hal_msp.c:366:6:HAL_SD_MspDeInit	2
+../Core/Src/stm32h7xx_hal_msp.c:404:6:HAL_TIM_Base_MspInit	2
+../Core/Src/stm32h7xx_hal_msp.c:426:6:HAL_TIM_Base_MspDeInit	2
+../Core/Src/stm32h7xx_hal_msp.c:448:6:HAL_UART_MspInit	8
+../Core/Src/stm32h7xx_hal_msp.c:582:6:HAL_UART_MspDeInit	4
diff --git a/Debug/Core/Src/stm32h7xx_hal_msp.d b/Debug/Core/Src/stm32h7xx_hal_msp.d
index 1f1339d..418e428 100644
--- a/Debug/Core/Src/stm32h7xx_hal_msp.d
+++ b/Debug/Core/Src/stm32h7xx_hal_msp.d
@@ -22,13 +22,22 @@ Core/Src/stm32h7xx_hal_msp.o: ../Core/Src/stm32h7xx_hal_msp.c \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
- ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h
 ../Core/Inc/main.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h:
 ../Core/Inc/stm32h7xx_hal_conf.h:
@@ -53,6 +62,7 @@ Core/Src/stm32h7xx_hal_msp.o: ../Core/Src/stm32h7xx_hal_msp.c \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
@@ -60,3 +70,11 @@ Core/Src/stm32h7xx_hal_msp.o: ../Core/Src/stm32h7xx_hal_msp.c \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
diff --git a/Debug/Core/Src/stm32h7xx_hal_msp.o b/Debug/Core/Src/stm32h7xx_hal_msp.o
index 2282ea6..daf160a 100644
Binary files a/Debug/Core/Src/stm32h7xx_hal_msp.o and b/Debug/Core/Src/stm32h7xx_hal_msp.o differ
diff --git a/Debug/Core/Src/stm32h7xx_hal_msp.su b/Debug/Core/Src/stm32h7xx_hal_msp.su
index 8061c9c..563e3a0 100644
--- a/Debug/Core/Src/stm32h7xx_hal_msp.su
+++ b/Debug/Core/Src/stm32h7xx_hal_msp.su
@@ -1 +1,9 @@
-../Core/Src/stm32h7xx_hal_msp.c:64:6:HAL_MspInit	16	static
+../Core/Src/stm32h7xx_hal_msp.c:65:6:HAL_MspInit	16	static
+../Core/Src/stm32h7xx_hal_msp.c:90:6:HAL_FDCAN_MspInit	248	static
+../Core/Src/stm32h7xx_hal_msp.c:223:6:HAL_FDCAN_MspDeInit	16	static
+../Core/Src/stm32h7xx_hal_msp.c:303:6:HAL_SD_MspInit	240	static
+../Core/Src/stm32h7xx_hal_msp.c:366:6:HAL_SD_MspDeInit	16	static
+../Core/Src/stm32h7xx_hal_msp.c:404:6:HAL_TIM_Base_MspInit	24	static
+../Core/Src/stm32h7xx_hal_msp.c:426:6:HAL_TIM_Base_MspDeInit	16	static
+../Core/Src/stm32h7xx_hal_msp.c:448:6:HAL_UART_MspInit	248	static
+../Core/Src/stm32h7xx_hal_msp.c:582:6:HAL_UART_MspDeInit	16	static
diff --git a/Debug/Core/Src/stm32h7xx_hal_timebase_tim.cyclo b/Debug/Core/Src/stm32h7xx_hal_timebase_tim.cyclo
new file mode 100644
index 0000000..dd0e910
--- /dev/null
+++ b/Debug/Core/Src/stm32h7xx_hal_timebase_tim.cyclo
@@ -0,0 +1,3 @@
+../Core/Src/stm32h7xx_hal_timebase_tim.c:41:19:HAL_InitTick	4
+../Core/Src/stm32h7xx_hal_timebase_tim.c:114:6:HAL_SuspendTick	1
+../Core/Src/stm32h7xx_hal_timebase_tim.c:126:6:HAL_ResumeTick	1
diff --git a/Debug/Core/Src/stm32h7xx_hal_timebase_tim.d b/Debug/Core/Src/stm32h7xx_hal_timebase_tim.d
new file mode 100644
index 0000000..abbafec
--- /dev/null
+++ b/Debug/Core/Src/stm32h7xx_hal_timebase_tim.d
@@ -0,0 +1,80 @@
+Core/Src/stm32h7xx_hal_timebase_tim.o: \
+ ../Core/Src/stm32h7xx_hal_timebase_tim.c \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \
+ ../Core/Inc/stm32h7xx_hal_conf.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h \
+ ../Drivers/CMSIS/Include/core_cm7.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h:
+../Core/Inc/stm32h7xx_hal_conf.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h:
+../Drivers/CMSIS/Include/core_cm7.h:
+../Drivers/CMSIS/Include/cmsis_version.h:
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+../Drivers/CMSIS/Include/mpu_armv7.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
diff --git a/Debug/Core/Src/stm32h7xx_hal_timebase_tim.o b/Debug/Core/Src/stm32h7xx_hal_timebase_tim.o
new file mode 100644
index 0000000..30750bf
Binary files /dev/null and b/Debug/Core/Src/stm32h7xx_hal_timebase_tim.o differ
diff --git a/Debug/Core/Src/stm32h7xx_hal_timebase_tim.su b/Debug/Core/Src/stm32h7xx_hal_timebase_tim.su
new file mode 100644
index 0000000..65815f1
--- /dev/null
+++ b/Debug/Core/Src/stm32h7xx_hal_timebase_tim.su
@@ -0,0 +1,3 @@
+../Core/Src/stm32h7xx_hal_timebase_tim.c:41:19:HAL_InitTick	72	static
+../Core/Src/stm32h7xx_hal_timebase_tim.c:114:6:HAL_SuspendTick	4	static
+../Core/Src/stm32h7xx_hal_timebase_tim.c:126:6:HAL_ResumeTick	4	static
diff --git a/Debug/Core/Src/stm32h7xx_it.cyclo b/Debug/Core/Src/stm32h7xx_it.cyclo
index 9b41ae6..7982d4f 100644
--- a/Debug/Core/Src/stm32h7xx_it.cyclo
+++ b/Debug/Core/Src/stm32h7xx_it.cyclo
@@ -1,10 +1,14 @@
-../Core/Src/stm32h7xx_it.c:69:6:NMI_Handler	1
-../Core/Src/stm32h7xx_it.c:84:6:HardFault_Handler	1
-../Core/Src/stm32h7xx_it.c:99:6:MemManage_Handler	1
-../Core/Src/stm32h7xx_it.c:114:6:BusFault_Handler	1
-../Core/Src/stm32h7xx_it.c:129:6:UsageFault_Handler	1
-../Core/Src/stm32h7xx_it.c:144:6:SVC_Handler	1
-../Core/Src/stm32h7xx_it.c:157:6:DebugMon_Handler	1
-../Core/Src/stm32h7xx_it.c:170:6:PendSV_Handler	1
-../Core/Src/stm32h7xx_it.c:183:6:SysTick_Handler	1
-../Core/Src/stm32h7xx_it.c:204:6:ETH_IRQHandler	1
+../Core/Src/stm32h7xx_it.c:77:6:NMI_Handler	1
+../Core/Src/stm32h7xx_it.c:92:6:HardFault_Handler	1
+../Core/Src/stm32h7xx_it.c:107:6:MemManage_Handler	1
+../Core/Src/stm32h7xx_it.c:122:6:BusFault_Handler	1
+../Core/Src/stm32h7xx_it.c:137:6:UsageFault_Handler	1
+../Core/Src/stm32h7xx_it.c:152:6:DebugMon_Handler	1
+../Core/Src/stm32h7xx_it.c:172:6:DMA1_Stream0_IRQHandler	1
+../Core/Src/stm32h7xx_it.c:186:6:FDCAN1_IT0_IRQHandler	1
+../Core/Src/stm32h7xx_it.c:200:6:FDCAN2_IT0_IRQHandler	1
+../Core/Src/stm32h7xx_it.c:214:6:SDMMC1_IRQHandler	1
+../Core/Src/stm32h7xx_it.c:228:6:TIM6_DAC_IRQHandler	1
+../Core/Src/stm32h7xx_it.c:242:6:ETH_IRQHandler	1
+../Core/Src/stm32h7xx_it.c:256:6:MDMA_IRQHandler	1
+../Core/Src/stm32h7xx_it.c:270:6:FDCAN3_IT0_IRQHandler	1
diff --git a/Debug/Core/Src/stm32h7xx_it.d b/Debug/Core/Src/stm32h7xx_it.d
index 14d76bd..6970edd 100644
--- a/Debug/Core/Src/stm32h7xx_it.d
+++ b/Debug/Core/Src/stm32h7xx_it.d
@@ -22,6 +22,7 @@ Core/Src/stm32h7xx_it.o: ../Core/Src/stm32h7xx_it.c ../Core/Inc/main.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
@@ -29,6 +30,14 @@ Core/Src/stm32h7xx_it.o: ../Core/Src/stm32h7xx_it.c ../Core/Inc/main.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \
  ../Core/Inc/stm32h7xx_it.h
 ../Core/Inc/main.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h:
@@ -54,6 +63,7 @@ Core/Src/stm32h7xx_it.o: ../Core/Src/stm32h7xx_it.c ../Core/Inc/main.h \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
@@ -61,4 +71,12 @@ Core/Src/stm32h7xx_it.o: ../Core/Src/stm32h7xx_it.c ../Core/Inc/main.h \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
 ../Core/Inc/stm32h7xx_it.h:
diff --git a/Debug/Core/Src/stm32h7xx_it.o b/Debug/Core/Src/stm32h7xx_it.o
index ca8405d..3f3dd35 100644
Binary files a/Debug/Core/Src/stm32h7xx_it.o and b/Debug/Core/Src/stm32h7xx_it.o differ
diff --git a/Debug/Core/Src/stm32h7xx_it.su b/Debug/Core/Src/stm32h7xx_it.su
index bda5435..959cae1 100644
--- a/Debug/Core/Src/stm32h7xx_it.su
+++ b/Debug/Core/Src/stm32h7xx_it.su
@@ -1,10 +1,14 @@
-../Core/Src/stm32h7xx_it.c:69:6:NMI_Handler	4	static
-../Core/Src/stm32h7xx_it.c:84:6:HardFault_Handler	4	static
-../Core/Src/stm32h7xx_it.c:99:6:MemManage_Handler	4	static
-../Core/Src/stm32h7xx_it.c:114:6:BusFault_Handler	4	static
-../Core/Src/stm32h7xx_it.c:129:6:UsageFault_Handler	4	static
-../Core/Src/stm32h7xx_it.c:144:6:SVC_Handler	4	static
-../Core/Src/stm32h7xx_it.c:157:6:DebugMon_Handler	4	static
-../Core/Src/stm32h7xx_it.c:170:6:PendSV_Handler	4	static
-../Core/Src/stm32h7xx_it.c:183:6:SysTick_Handler	8	static
-../Core/Src/stm32h7xx_it.c:204:6:ETH_IRQHandler	8	static
+../Core/Src/stm32h7xx_it.c:77:6:NMI_Handler	4	static
+../Core/Src/stm32h7xx_it.c:92:6:HardFault_Handler	4	static
+../Core/Src/stm32h7xx_it.c:107:6:MemManage_Handler	4	static
+../Core/Src/stm32h7xx_it.c:122:6:BusFault_Handler	4	static
+../Core/Src/stm32h7xx_it.c:137:6:UsageFault_Handler	4	static
+../Core/Src/stm32h7xx_it.c:152:6:DebugMon_Handler	4	static
+../Core/Src/stm32h7xx_it.c:172:6:DMA1_Stream0_IRQHandler	8	static
+../Core/Src/stm32h7xx_it.c:186:6:FDCAN1_IT0_IRQHandler	8	static
+../Core/Src/stm32h7xx_it.c:200:6:FDCAN2_IT0_IRQHandler	8	static
+../Core/Src/stm32h7xx_it.c:214:6:SDMMC1_IRQHandler	8	static
+../Core/Src/stm32h7xx_it.c:228:6:TIM6_DAC_IRQHandler	8	static
+../Core/Src/stm32h7xx_it.c:242:6:ETH_IRQHandler	8	static
+../Core/Src/stm32h7xx_it.c:256:6:MDMA_IRQHandler	8	static
+../Core/Src/stm32h7xx_it.c:270:6:FDCAN3_IT0_IRQHandler	8	static
diff --git a/Debug/Core/Src/subdir.mk b/Debug/Core/Src/subdir.mk
index 342b87a..52d127c 100644
--- a/Debug/Core/Src/subdir.mk
+++ b/Debug/Core/Src/subdir.mk
@@ -5,24 +5,30 @@
 
 # Add inputs and outputs from these tool invocations to the build variables 
 C_SRCS += \
+../Core/Src/freertos.c \
 ../Core/Src/main.c \
 ../Core/Src/stm32h7xx_hal_msp.c \
+../Core/Src/stm32h7xx_hal_timebase_tim.c \
 ../Core/Src/stm32h7xx_it.c \
 ../Core/Src/syscalls.c \
 ../Core/Src/sysmem.c \
 ../Core/Src/system_stm32h7xx.c 
 
 OBJS += \
+./Core/Src/freertos.o \
 ./Core/Src/main.o \
 ./Core/Src/stm32h7xx_hal_msp.o \
+./Core/Src/stm32h7xx_hal_timebase_tim.o \
 ./Core/Src/stm32h7xx_it.o \
 ./Core/Src/syscalls.o \
 ./Core/Src/sysmem.o \
 ./Core/Src/system_stm32h7xx.o 
 
 C_DEPS += \
+./Core/Src/freertos.d \
 ./Core/Src/main.d \
 ./Core/Src/stm32h7xx_hal_msp.d \
+./Core/Src/stm32h7xx_hal_timebase_tim.d \
 ./Core/Src/stm32h7xx_it.d \
 ./Core/Src/syscalls.d \
 ./Core/Src/sysmem.d \
@@ -31,12 +37,12 @@ C_DEPS += \
 
 # Each subdirectory must supply rules for building sources it contributes
 Core/Src/%.o Core/Src/%.su Core/Src/%.cyclo: ../Core/Src/%.c Core/Src/subdir.mk
-	arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DDEBUG -DDATA_IN_D2_SRAM -DUSE_HAL_DRIVER -DSTM32H723xx -c -I../Core/Inc -I../Drivers/STM32H7xx_HAL_Driver/Inc -I../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32H7xx/Include -I../Drivers/CMSIS/Include -I../LWIP/App -I../LWIP/Target -I../Middlewares/Third_Party/LwIP/src/include -I../Middlewares/Third_Party/LwIP/system -I../Drivers/BSP/Components/lan8742 -I../Middlewares/Third_Party/LwIP/src/include/netif/ppp -I../Middlewares/Third_Party/LwIP/src/include/lwip -I../Middlewares/Third_Party/LwIP/src/include/lwip/apps -I../Middlewares/Third_Party/LwIP/src/include/lwip/priv -I../Middlewares/Third_Party/LwIP/src/include/lwip/prot -I../Middlewares/Third_Party/LwIP/src/include/netif -I../Middlewares/Third_Party/LwIP/src/include/compat/posix -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/arpa -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/net -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/sys -I../Middlewares/Third_Party/LwIP/src/include/compat/stdc -I../Middlewares/Third_Party/LwIP/system/arch -I"C:/_NoSleep/STM32/lwip_test/LWFTP" -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
+	arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DDEBUG -DDATA_IN_D2_SRAM -DUSE_HAL_DRIVER -DSTM32H723xx -c -I../Core/Inc -I../FATFS/Target -I../FATFS/App -I../LWIP/App -I../LWIP/Target -I../Middlewares/Third_Party/LwIP/src/include -I../Middlewares/Third_Party/LwIP/system -I../Drivers/STM32H7xx_HAL_Driver/Inc -I../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F -I../Middlewares/Third_Party/FatFs/src -I../Drivers/BSP/Components/lan8742 -I../Middlewares/Third_Party/LwIP/src/include/netif/ppp -I../Drivers/CMSIS/Device/ST/STM32H7xx/Include -I../Middlewares/Third_Party/LwIP/src/include/lwip -I../Middlewares/Third_Party/LwIP/src/include/lwip/apps -I../Middlewares/Third_Party/LwIP/src/include/lwip/priv -I../Middlewares/Third_Party/LwIP/src/include/lwip/prot -I../Middlewares/Third_Party/LwIP/src/include/netif -I../Middlewares/Third_Party/LwIP/src/include/compat/posix -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/arpa -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/net -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/sys -I../Middlewares/Third_Party/LwIP/src/include/compat/stdc -I../Middlewares/Third_Party/LwIP/system/arch -I../Drivers/CMSIS/Include -I"C:/_NoSleep/STM32/TBD_TaxiBoard/LWFTPC" -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
 
 clean: clean-Core-2f-Src
 
 clean-Core-2f-Src:
-	-$(RM) ./Core/Src/main.cyclo ./Core/Src/main.d ./Core/Src/main.o ./Core/Src/main.su ./Core/Src/stm32h7xx_hal_msp.cyclo ./Core/Src/stm32h7xx_hal_msp.d ./Core/Src/stm32h7xx_hal_msp.o ./Core/Src/stm32h7xx_hal_msp.su ./Core/Src/stm32h7xx_it.cyclo ./Core/Src/stm32h7xx_it.d ./Core/Src/stm32h7xx_it.o ./Core/Src/stm32h7xx_it.su ./Core/Src/syscalls.cyclo ./Core/Src/syscalls.d ./Core/Src/syscalls.o ./Core/Src/syscalls.su ./Core/Src/sysmem.cyclo ./Core/Src/sysmem.d ./Core/Src/sysmem.o ./Core/Src/sysmem.su ./Core/Src/system_stm32h7xx.cyclo ./Core/Src/system_stm32h7xx.d ./Core/Src/system_stm32h7xx.o ./Core/Src/system_stm32h7xx.su
+	-$(RM) ./Core/Src/freertos.cyclo ./Core/Src/freertos.d ./Core/Src/freertos.o ./Core/Src/freertos.su ./Core/Src/main.cyclo ./Core/Src/main.d ./Core/Src/main.o ./Core/Src/main.su ./Core/Src/stm32h7xx_hal_msp.cyclo ./Core/Src/stm32h7xx_hal_msp.d ./Core/Src/stm32h7xx_hal_msp.o ./Core/Src/stm32h7xx_hal_msp.su ./Core/Src/stm32h7xx_hal_timebase_tim.cyclo ./Core/Src/stm32h7xx_hal_timebase_tim.d ./Core/Src/stm32h7xx_hal_timebase_tim.o ./Core/Src/stm32h7xx_hal_timebase_tim.su ./Core/Src/stm32h7xx_it.cyclo ./Core/Src/stm32h7xx_it.d ./Core/Src/stm32h7xx_it.o ./Core/Src/stm32h7xx_it.su ./Core/Src/syscalls.cyclo ./Core/Src/syscalls.d ./Core/Src/syscalls.o ./Core/Src/syscalls.su ./Core/Src/sysmem.cyclo ./Core/Src/sysmem.d ./Core/Src/sysmem.o ./Core/Src/sysmem.su ./Core/Src/system_stm32h7xx.cyclo ./Core/Src/system_stm32h7xx.d ./Core/Src/system_stm32h7xx.o ./Core/Src/system_stm32h7xx.su
 
 .PHONY: clean-Core-2f-Src
 
diff --git a/Debug/Core/Src/syscalls.d b/Debug/Core/Src/syscalls.d
index 01862e2..c8e2259 100644
--- a/Debug/Core/Src/syscalls.d
+++ b/Debug/Core/Src/syscalls.d
@@ -25,6 +25,7 @@ Core/Src/syscalls.o: ../Core/Src/syscalls.c \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
@@ -32,6 +33,14 @@ Core/Src/syscalls.o: ../Core/Src/syscalls.c \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \
  ../Middlewares/Third_Party/LwIP/system/arch/cc.h \
@@ -63,6 +72,7 @@ Core/Src/syscalls.o: ../Core/Src/syscalls.c \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
@@ -70,6 +80,14 @@ Core/Src/syscalls.o: ../Core/Src/syscalls.c \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h:
 ../Middlewares/Third_Party/LwIP/system/arch/cc.h:
diff --git a/Debug/Core/Src/syscalls.o b/Debug/Core/Src/syscalls.o
index caa4ce2..6f4b2a5 100644
Binary files a/Debug/Core/Src/syscalls.o and b/Debug/Core/Src/syscalls.o differ
diff --git a/Debug/Core/Src/sysmem.d b/Debug/Core/Src/sysmem.d
index b7ac370..322dee5 100644
--- a/Debug/Core/Src/sysmem.d
+++ b/Debug/Core/Src/sysmem.d
@@ -25,6 +25,7 @@ Core/Src/sysmem.o: ../Core/Src/sysmem.c \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
@@ -32,6 +33,14 @@ Core/Src/sysmem.o: ../Core/Src/sysmem.c \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \
  ../Middlewares/Third_Party/LwIP/system/arch/cc.h \
@@ -63,6 +72,7 @@ Core/Src/sysmem.o: ../Core/Src/sysmem.c \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
@@ -70,6 +80,14 @@ Core/Src/sysmem.o: ../Core/Src/sysmem.c \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h:
 ../Middlewares/Third_Party/LwIP/system/arch/cc.h:
diff --git a/Debug/Core/Src/sysmem.o b/Debug/Core/Src/sysmem.o
index 6371db9..8693971 100644
Binary files a/Debug/Core/Src/sysmem.o and b/Debug/Core/Src/sysmem.o differ
diff --git a/Debug/Core/Src/system_stm32h7xx.d b/Debug/Core/Src/system_stm32h7xx.d
index 72b7c75..a063a93 100644
--- a/Debug/Core/Src/system_stm32h7xx.d
+++ b/Debug/Core/Src/system_stm32h7xx.d
@@ -22,13 +22,22 @@ Core/Src/system_stm32h7xx.o: ../Core/Src/system_stm32h7xx.c \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
- ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h
 ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h:
 ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h:
 ../Drivers/CMSIS/Include/core_cm7.h:
@@ -52,6 +61,7 @@ Core/Src/system_stm32h7xx.o: ../Core/Src/system_stm32h7xx.c \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
@@ -59,3 +69,11 @@ Core/Src/system_stm32h7xx.o: ../Core/Src/system_stm32h7xx.c \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
diff --git a/Debug/Core/Src/system_stm32h7xx.o b/Debug/Core/Src/system_stm32h7xx.o
index 33d8a56..b3e6fc6 100644
Binary files a/Debug/Core/Src/system_stm32h7xx.o and b/Debug/Core/Src/system_stm32h7xx.o differ
diff --git a/Debug/Core/Startup/startup_stm32h723vghx.o b/Debug/Core/Startup/startup_stm32h723vghx.o
index 54f55d8..d414b80 100644
Binary files a/Debug/Core/Startup/startup_stm32h723vghx.o and b/Debug/Core/Startup/startup_stm32h723vghx.o differ
diff --git a/Debug/Core/Startup/subdir.mk b/Debug/Core/Startup/subdir.mk
index bc68ae8..1bf9eaf 100644
--- a/Debug/Core/Startup/subdir.mk
+++ b/Debug/Core/Startup/subdir.mk
@@ -16,7 +16,7 @@ S_DEPS += \
 
 # Each subdirectory must supply rules for building sources it contributes
 Core/Startup/%.o: ../Core/Startup/%.s Core/Startup/subdir.mk
-	arm-none-eabi-gcc -mcpu=cortex-m7 -g3 -DDEBUG -c -I"C:/_NoSleep/STM32/lwip_test/LWFTP" -x assembler-with-cpp -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@" "$<"
+	arm-none-eabi-gcc -mcpu=cortex-m7 -g3 -DDEBUG -c -I"C:/_NoSleep/STM32/TBD_TaxiBoard/LWFTPC" -x assembler-with-cpp -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@" "$<"
 
 clean: clean-Core-2f-Startup
 
diff --git a/Debug/Drivers/BSP/Components/lan8742/lan8742.o b/Debug/Drivers/BSP/Components/lan8742/lan8742.o
index cbaa2dc..e07f11b 100644
Binary files a/Debug/Drivers/BSP/Components/lan8742/lan8742.o and b/Debug/Drivers/BSP/Components/lan8742/lan8742.o differ
diff --git a/Debug/Drivers/BSP/Components/lan8742/subdir.mk b/Debug/Drivers/BSP/Components/lan8742/subdir.mk
index ab4a471..6dee59e 100644
--- a/Debug/Drivers/BSP/Components/lan8742/subdir.mk
+++ b/Debug/Drivers/BSP/Components/lan8742/subdir.mk
@@ -16,7 +16,7 @@ C_DEPS += \
 
 # Each subdirectory must supply rules for building sources it contributes
 Drivers/BSP/Components/lan8742/%.o Drivers/BSP/Components/lan8742/%.su Drivers/BSP/Components/lan8742/%.cyclo: ../Drivers/BSP/Components/lan8742/%.c Drivers/BSP/Components/lan8742/subdir.mk
-	arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DDEBUG -DDATA_IN_D2_SRAM -DUSE_HAL_DRIVER -DSTM32H723xx -c -I../Core/Inc -I../Drivers/STM32H7xx_HAL_Driver/Inc -I../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32H7xx/Include -I../Drivers/CMSIS/Include -I../LWIP/App -I../LWIP/Target -I../Middlewares/Third_Party/LwIP/src/include -I../Middlewares/Third_Party/LwIP/system -I../Drivers/BSP/Components/lan8742 -I../Middlewares/Third_Party/LwIP/src/include/netif/ppp -I../Middlewares/Third_Party/LwIP/src/include/lwip -I../Middlewares/Third_Party/LwIP/src/include/lwip/apps -I../Middlewares/Third_Party/LwIP/src/include/lwip/priv -I../Middlewares/Third_Party/LwIP/src/include/lwip/prot -I../Middlewares/Third_Party/LwIP/src/include/netif -I../Middlewares/Third_Party/LwIP/src/include/compat/posix -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/arpa -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/net -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/sys -I../Middlewares/Third_Party/LwIP/src/include/compat/stdc -I../Middlewares/Third_Party/LwIP/system/arch -I"C:/_NoSleep/STM32/lwip_test/LWFTP" -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
+	arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DDEBUG -DDATA_IN_D2_SRAM -DUSE_HAL_DRIVER -DSTM32H723xx -c -I../Core/Inc -I../FATFS/Target -I../FATFS/App -I../LWIP/App -I../LWIP/Target -I../Middlewares/Third_Party/LwIP/src/include -I../Middlewares/Third_Party/LwIP/system -I../Drivers/STM32H7xx_HAL_Driver/Inc -I../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F -I../Middlewares/Third_Party/FatFs/src -I../Drivers/BSP/Components/lan8742 -I../Middlewares/Third_Party/LwIP/src/include/netif/ppp -I../Drivers/CMSIS/Device/ST/STM32H7xx/Include -I../Middlewares/Third_Party/LwIP/src/include/lwip -I../Middlewares/Third_Party/LwIP/src/include/lwip/apps -I../Middlewares/Third_Party/LwIP/src/include/lwip/priv -I../Middlewares/Third_Party/LwIP/src/include/lwip/prot -I../Middlewares/Third_Party/LwIP/src/include/netif -I../Middlewares/Third_Party/LwIP/src/include/compat/posix -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/arpa -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/net -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/sys -I../Middlewares/Third_Party/LwIP/src/include/compat/stdc -I../Middlewares/Third_Party/LwIP/system/arch -I../Drivers/CMSIS/Include -I"C:/_NoSleep/STM32/TBD_TaxiBoard/LWFTPC" -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
 
 clean: clean-Drivers-2f-BSP-2f-Components-2f-lan8742
 
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.d b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.d
index f14b3b3..e428be2 100644
--- a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.d
+++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.d
@@ -23,13 +23,22 @@ Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
- ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h:
 ../Core/Inc/stm32h7xx_hal_conf.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h:
@@ -53,6 +62,7 @@ Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
@@ -60,3 +70,11 @@ Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.o b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.o
index 794ff8b..1c0b05b 100644
Binary files a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.o and b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.o differ
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.d b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.d
index e15a315..db481be 100644
--- a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.d
+++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.d
@@ -23,13 +23,22 @@ Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
- ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h:
 ../Core/Inc/stm32h7xx_hal_conf.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h:
@@ -53,6 +62,7 @@ Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
@@ -60,3 +70,11 @@ Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.o b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.o
index 36540cf..102b926 100644
Binary files a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.o and b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.o differ
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.d b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.d
index 331cd08..f49bd5b 100644
--- a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.d
+++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.d
@@ -23,13 +23,22 @@ Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
- ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h:
 ../Core/Inc/stm32h7xx_hal_conf.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h:
@@ -53,6 +62,7 @@ Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
@@ -60,3 +70,11 @@ Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.o b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.o
index 13a12eb..4df4929 100644
Binary files a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.o and b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.o differ
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.d b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.d
index f170cbd..7be382b 100644
--- a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.d
+++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.d
@@ -23,13 +23,22 @@ Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
- ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h:
 ../Core/Inc/stm32h7xx_hal_conf.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h:
@@ -53,6 +62,7 @@ Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
@@ -60,3 +70,11 @@ Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.o b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.o
index 7ded811..3443786 100644
Binary files a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.o and b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.o differ
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.d b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.d
index c4c3f78..861f55d 100644
--- a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.d
+++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.d
@@ -23,13 +23,22 @@ Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
- ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h:
 ../Core/Inc/stm32h7xx_hal_conf.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h:
@@ -53,6 +62,7 @@ Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
@@ -60,3 +70,11 @@ Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o
index b5bf092..17f7c83 100644
Binary files a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o and b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o differ
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.d b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.d
index 4afa1c7..b5afaca 100644
--- a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.d
+++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.d
@@ -23,13 +23,22 @@ Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
- ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h:
 ../Core/Inc/stm32h7xx_hal_conf.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h:
@@ -53,6 +62,7 @@ Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
@@ -60,3 +70,11 @@ Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.o b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.o
index 2ebd769..a4575c2 100644
Binary files a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.o and b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.o differ
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.d b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.d
index cecfc6d..0843b74 100644
--- a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.d
+++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.d
@@ -23,13 +23,22 @@ Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
- ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h:
 ../Core/Inc/stm32h7xx_hal_conf.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h:
@@ -53,6 +62,7 @@ Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
@@ -60,3 +70,11 @@ Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.o b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.o
index b0926fa..7645eae 100644
Binary files a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.o and b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.o differ
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.cyclo b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.cyclo
new file mode 100644
index 0000000..255d4a9
--- /dev/null
+++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.cyclo
@@ -0,0 +1,100 @@
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:287:19:HAL_FDCAN_Init	22
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:592:19:HAL_FDCAN_DeInit	2
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:638:13:HAL_FDCAN_MspInit	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:653:13:HAL_FDCAN_MspDeInit	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:668:19:HAL_FDCAN_EnterPowerDownMode	3
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:703:19:HAL_FDCAN_ExitPowerDownMode	3
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:1658:19:HAL_FDCAN_ConfigClockCalibration	4
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:1726:10:HAL_FDCAN_GetClockCalibrationState	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:1740:19:HAL_FDCAN_ResetClockCalibrationState	3
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:1776:10:HAL_FDCAN_GetClockCalibrationCounter	3
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:1807:19:HAL_FDCAN_ConfigFilter	6
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:1919:19:HAL_FDCAN_ConfigGlobalFilter	2
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:1959:19:HAL_FDCAN_ConfigExtendedIdMask	2
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:1993:19:HAL_FDCAN_ConfigRxFifoOverwrite	3
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:2036:19:HAL_FDCAN_ConfigFifoWatermark	4
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:2086:19:HAL_FDCAN_ConfigRamWatchdog	2
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:2116:19:HAL_FDCAN_ConfigTimestampCounter	2
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:2146:19:HAL_FDCAN_EnableTimestampCounter	2
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:2174:19:HAL_FDCAN_DisableTimestampCounter	2
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:2199:10:HAL_FDCAN_GetTimestampCounter	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:2210:19:HAL_FDCAN_ResetTimestampCounter	2
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:2241:19:HAL_FDCAN_ConfigTimeoutCounter	2
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:2270:19:HAL_FDCAN_EnableTimeoutCounter	2
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:2295:19:HAL_FDCAN_DisableTimeoutCounter	2
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:2320:10:HAL_FDCAN_GetTimeoutCounter	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:2331:19:HAL_FDCAN_ResetTimeoutCounter	2
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:2361:19:HAL_FDCAN_ConfigTxDelayCompensation	2
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:2390:19:HAL_FDCAN_EnableTxDelayCompensation	2
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:2415:19:HAL_FDCAN_DisableTxDelayCompensation	2
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:2441:19:HAL_FDCAN_EnableISOMode	2
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:2467:19:HAL_FDCAN_DisableISOMode	2
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:2493:19:HAL_FDCAN_EnableEdgeFiltering	2
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:2519:19:HAL_FDCAN_DisableEdgeFiltering	2
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:2579:19:HAL_FDCAN_Start	2
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:2610:19:HAL_FDCAN_Stop	6
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:2692:19:HAL_FDCAN_AddMessageToTxFifoQ	4
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:2770:19:HAL_FDCAN_AddMessageToTxBuffer	7
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:2838:19:HAL_FDCAN_EnableTxBufferRequest	2
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:2865:10:HAL_FDCAN_GetLatestTxFifoQRequestBuffer	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:2879:19:HAL_FDCAN_AbortTxRequest	2
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:2908:19:HAL_FDCAN_GetRxMessage	18
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:3103:19:HAL_FDCAN_GetTxEvent	5
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:3198:19:HAL_FDCAN_GetHighPriorityMessageStatus	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:3216:19:HAL_FDCAN_GetProtocolStatus	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:3247:19:HAL_FDCAN_GetErrorCounters	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:3274:10:HAL_FDCAN_IsRxBufferMessageAvailable	6
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:3311:10:HAL_FDCAN_IsTxBufferMessagePending	2
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:3331:10:HAL_FDCAN_GetRxFifoFillLevel	2
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:3358:10:HAL_FDCAN_GetTxFifoFreeLevel	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:3376:10:HAL_FDCAN_IsRestrictedOperationMode	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:3392:19:HAL_FDCAN_ExitRestrictedOperationMode	3
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:3458:19:HAL_FDCAN_TT_ConfigOperation	10
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:3636:19:HAL_FDCAN_TT_ConfigReferenceMessage	3
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:3684:19:HAL_FDCAN_TT_ConfigTrigger	11
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:3794:19:HAL_FDCAN_TT_SetGlobalTime	7
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:3868:19:HAL_FDCAN_TT_SetClockSynchronization	7
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:3944:19:HAL_FDCAN_TT_ConfigStopWatch	5
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:4005:19:HAL_FDCAN_TT_ConfigRegisterTimeMark	11
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:4126:19:HAL_FDCAN_TT_EnableRegisterTimeMarkPulse	5
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:4176:19:HAL_FDCAN_TT_DisableRegisterTimeMarkPulse	5
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:4226:19:HAL_FDCAN_TT_EnableTriggerTimeMarkPulse	6
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:4287:19:HAL_FDCAN_TT_DisableTriggerTimeMarkPulse	6
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:4348:19:HAL_FDCAN_TT_EnableHardwareGapControl	6
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:4409:19:HAL_FDCAN_TT_DisableHardwareGapControl	6
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:4472:19:HAL_FDCAN_TT_EnableTimeMarkGapControl	6
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:4533:19:HAL_FDCAN_TT_DisableTimeMarkGapControl	6
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:4594:19:HAL_FDCAN_TT_SetNextIsGap	7
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:4664:19:HAL_FDCAN_TT_SetEndOfGap	7
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:4738:19:HAL_FDCAN_TT_ConfigExternalSyncPhase	4
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:4779:19:HAL_FDCAN_TT_EnableExternalSynchronization	5
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:4829:19:HAL_FDCAN_TT_DisableExternalSynchronization	5
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:4880:19:HAL_FDCAN_TT_GetOperationStatus	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:4944:19:HAL_FDCAN_ConfigInterruptLines	4
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:4986:19:HAL_FDCAN_TT_ConfigInterruptLines	4
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:5032:19:HAL_FDCAN_ActivateNotification	7
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:5095:19:HAL_FDCAN_DeactivateNotification	7
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:5154:19:HAL_FDCAN_TT_ActivateNotification	5
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:5204:19:HAL_FDCAN_TT_DeactivateNotification	5
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:5250:6:HAL_FDCAN_IRQHandler	33
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:5680:13:HAL_FDCAN_ClockCalibrationCallback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:5699:13:HAL_FDCAN_TxEventFifoCallback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:5718:13:HAL_FDCAN_RxFifo0Callback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:5737:13:HAL_FDCAN_RxFifo1Callback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:5754:13:HAL_FDCAN_TxFifoEmptyCallback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:5772:13:HAL_FDCAN_TxBufferCompleteCallback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:5791:13:HAL_FDCAN_TxBufferAbortCallback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:5808:13:HAL_FDCAN_RxBufferNewMessageCallback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:5824:13:HAL_FDCAN_TimestampWraparoundCallback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:5840:13:HAL_FDCAN_TimeoutOccurredCallback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:5856:13:HAL_FDCAN_HighPriorityMessageCallback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:5872:13:HAL_FDCAN_ErrorCallback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:5890:13:HAL_FDCAN_ErrorStatusCallback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:5909:13:HAL_FDCAN_TT_ScheduleSyncCallback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:5928:13:HAL_FDCAN_TT_TimeMarkCallback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:5950:13:HAL_FDCAN_TT_StopWatchCallback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:5970:13:HAL_FDCAN_TT_GlobalTimeCallback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:6006:24:HAL_FDCAN_GetState	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:6018:10:HAL_FDCAN_GetError	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:6042:26:FDCAN_CalcultateRamBlockAddresses	3
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:6141:13:FDCAN_CopyMessageToRAM	3
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.d b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.d
new file mode 100644
index 0000000..26c626f
--- /dev/null
+++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.d
@@ -0,0 +1,80 @@
+Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o: \
+ ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \
+ ../Core/Inc/stm32h7xx_hal_conf.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h \
+ ../Drivers/CMSIS/Include/core_cm7.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h:
+../Core/Inc/stm32h7xx_hal_conf.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h:
+../Drivers/CMSIS/Include/core_cm7.h:
+../Drivers/CMSIS/Include/cmsis_version.h:
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+../Drivers/CMSIS/Include/mpu_armv7.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
new file mode 100644
index 0000000..eb62a08
Binary files /dev/null and b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o differ
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.su b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.su
new file mode 100644
index 0000000..a983a37
--- /dev/null
+++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.su
@@ -0,0 +1,100 @@
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:287:19:HAL_FDCAN_Init	104	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:592:19:HAL_FDCAN_DeInit	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:638:13:HAL_FDCAN_MspInit	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:653:13:HAL_FDCAN_MspDeInit	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:668:19:HAL_FDCAN_EnterPowerDownMode	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:703:19:HAL_FDCAN_ExitPowerDownMode	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:1658:19:HAL_FDCAN_ConfigClockCalibration	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:1726:10:HAL_FDCAN_GetClockCalibrationState	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:1740:19:HAL_FDCAN_ResetClockCalibrationState	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:1776:10:HAL_FDCAN_GetClockCalibrationCounter	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:1807:19:HAL_FDCAN_ConfigFilter	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:1919:19:HAL_FDCAN_ConfigGlobalFilter	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:1959:19:HAL_FDCAN_ConfigExtendedIdMask	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:1993:19:HAL_FDCAN_ConfigRxFifoOverwrite	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:2036:19:HAL_FDCAN_ConfigFifoWatermark	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:2086:19:HAL_FDCAN_ConfigRamWatchdog	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:2116:19:HAL_FDCAN_ConfigTimestampCounter	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:2146:19:HAL_FDCAN_EnableTimestampCounter	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:2174:19:HAL_FDCAN_DisableTimestampCounter	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:2199:10:HAL_FDCAN_GetTimestampCounter	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:2210:19:HAL_FDCAN_ResetTimestampCounter	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:2241:19:HAL_FDCAN_ConfigTimeoutCounter	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:2270:19:HAL_FDCAN_EnableTimeoutCounter	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:2295:19:HAL_FDCAN_DisableTimeoutCounter	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:2320:10:HAL_FDCAN_GetTimeoutCounter	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:2331:19:HAL_FDCAN_ResetTimeoutCounter	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:2361:19:HAL_FDCAN_ConfigTxDelayCompensation	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:2390:19:HAL_FDCAN_EnableTxDelayCompensation	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:2415:19:HAL_FDCAN_DisableTxDelayCompensation	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:2441:19:HAL_FDCAN_EnableISOMode	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:2467:19:HAL_FDCAN_DisableISOMode	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:2493:19:HAL_FDCAN_EnableEdgeFiltering	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:2519:19:HAL_FDCAN_DisableEdgeFiltering	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:2579:19:HAL_FDCAN_Start	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:2610:19:HAL_FDCAN_Stop	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:2692:19:HAL_FDCAN_AddMessageToTxFifoQ	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:2770:19:HAL_FDCAN_AddMessageToTxBuffer	56	static,ignoring_inline_asm
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:2838:19:HAL_FDCAN_EnableTxBufferRequest	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:2865:10:HAL_FDCAN_GetLatestTxFifoQRequestBuffer	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:2879:19:HAL_FDCAN_AbortTxRequest	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:2908:19:HAL_FDCAN_GetRxMessage	48	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:3103:19:HAL_FDCAN_GetTxEvent	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:3198:19:HAL_FDCAN_GetHighPriorityMessageStatus	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:3216:19:HAL_FDCAN_GetProtocolStatus	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:3247:19:HAL_FDCAN_GetErrorCounters	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:3274:10:HAL_FDCAN_IsRxBufferMessageAvailable	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:3311:10:HAL_FDCAN_IsTxBufferMessagePending	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:3331:10:HAL_FDCAN_GetRxFifoFillLevel	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:3358:10:HAL_FDCAN_GetTxFifoFreeLevel	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:3376:10:HAL_FDCAN_IsRestrictedOperationMode	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:3392:19:HAL_FDCAN_ExitRestrictedOperationMode	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:3458:19:HAL_FDCAN_TT_ConfigOperation	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:3636:19:HAL_FDCAN_TT_ConfigReferenceMessage	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:3684:19:HAL_FDCAN_TT_ConfigTrigger	48	static,ignoring_inline_asm
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:3794:19:HAL_FDCAN_TT_SetGlobalTime	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:3868:19:HAL_FDCAN_TT_SetClockSynchronization	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:3944:19:HAL_FDCAN_TT_ConfigStopWatch	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:4005:19:HAL_FDCAN_TT_ConfigRegisterTimeMark	40	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:4126:19:HAL_FDCAN_TT_EnableRegisterTimeMarkPulse	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:4176:19:HAL_FDCAN_TT_DisableRegisterTimeMarkPulse	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:4226:19:HAL_FDCAN_TT_EnableTriggerTimeMarkPulse	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:4287:19:HAL_FDCAN_TT_DisableTriggerTimeMarkPulse	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:4348:19:HAL_FDCAN_TT_EnableHardwareGapControl	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:4409:19:HAL_FDCAN_TT_DisableHardwareGapControl	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:4472:19:HAL_FDCAN_TT_EnableTimeMarkGapControl	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:4533:19:HAL_FDCAN_TT_DisableTimeMarkGapControl	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:4594:19:HAL_FDCAN_TT_SetNextIsGap	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:4664:19:HAL_FDCAN_TT_SetEndOfGap	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:4738:19:HAL_FDCAN_TT_ConfigExternalSyncPhase	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:4779:19:HAL_FDCAN_TT_EnableExternalSynchronization	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:4829:19:HAL_FDCAN_TT_DisableExternalSynchronization	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:4880:19:HAL_FDCAN_TT_GetOperationStatus	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:4944:19:HAL_FDCAN_ConfigInterruptLines	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:4986:19:HAL_FDCAN_TT_ConfigInterruptLines	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:5032:19:HAL_FDCAN_ActivateNotification	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:5095:19:HAL_FDCAN_DeactivateNotification	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:5154:19:HAL_FDCAN_TT_ActivateNotification	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:5204:19:HAL_FDCAN_TT_DeactivateNotification	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:5250:6:HAL_FDCAN_IRQHandler	96	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:5680:13:HAL_FDCAN_ClockCalibrationCallback	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:5699:13:HAL_FDCAN_TxEventFifoCallback	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:5718:13:HAL_FDCAN_RxFifo0Callback	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:5737:13:HAL_FDCAN_RxFifo1Callback	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:5754:13:HAL_FDCAN_TxFifoEmptyCallback	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:5772:13:HAL_FDCAN_TxBufferCompleteCallback	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:5791:13:HAL_FDCAN_TxBufferAbortCallback	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:5808:13:HAL_FDCAN_RxBufferNewMessageCallback	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:5824:13:HAL_FDCAN_TimestampWraparoundCallback	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:5840:13:HAL_FDCAN_TimeoutOccurredCallback	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:5856:13:HAL_FDCAN_HighPriorityMessageCallback	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:5872:13:HAL_FDCAN_ErrorCallback	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:5890:13:HAL_FDCAN_ErrorStatusCallback	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:5909:13:HAL_FDCAN_TT_ScheduleSyncCallback	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:5928:13:HAL_FDCAN_TT_TimeMarkCallback	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:5950:13:HAL_FDCAN_TT_StopWatchCallback	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:5970:13:HAL_FDCAN_TT_GlobalTimeCallback	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:6006:24:HAL_FDCAN_GetState	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:6018:10:HAL_FDCAN_GetError	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:6042:26:FDCAN_CalcultateRamBlockAddresses	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:6141:13:FDCAN_CopyMessageToRAM	40	static
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.d b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.d
index 423eb1e..514ca90 100644
--- a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.d
+++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.d
@@ -23,13 +23,22 @@ Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
- ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h:
 ../Core/Inc/stm32h7xx_hal_conf.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h:
@@ -53,6 +62,7 @@ Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
@@ -60,3 +70,11 @@ Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.o b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.o
index e3b5ccc..63aaad2 100644
Binary files a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.o and b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.o differ
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.d b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.d
index 111791a..f49746f 100644
--- a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.d
+++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.d
@@ -23,13 +23,22 @@ Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
- ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h:
 ../Core/Inc/stm32h7xx_hal_conf.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h:
@@ -53,6 +62,7 @@ Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
@@ -60,3 +70,11 @@ Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.o b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.o
index 9faf5a5..67fa8f3 100644
Binary files a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.o and b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.o differ
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.d b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.d
index 01b516e..f712f37 100644
--- a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.d
+++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.d
@@ -23,13 +23,22 @@ Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
- ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h:
 ../Core/Inc/stm32h7xx_hal_conf.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h:
@@ -53,6 +62,7 @@ Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
@@ -60,3 +70,11 @@ Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.o b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.o
index 373152e..87875a3 100644
Binary files a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.o and b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.o differ
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.d b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.d
index b83bf39..0c0c8e0 100644
--- a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.d
+++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.d
@@ -23,13 +23,22 @@ Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
- ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h:
 ../Core/Inc/stm32h7xx_hal_conf.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h:
@@ -53,6 +62,7 @@ Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
@@ -60,3 +70,11 @@ Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.o b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.o
index 25dae27..0451969 100644
Binary files a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.o and b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.o differ
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.d b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.d
index 58e8fe3..10fe760 100644
--- a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.d
+++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.d
@@ -23,13 +23,22 @@ Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
- ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h:
 ../Core/Inc/stm32h7xx_hal_conf.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h:
@@ -53,6 +62,7 @@ Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
@@ -60,3 +70,11 @@ Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.o b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.o
index cc04e29..a266c19 100644
Binary files a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.o and b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.o differ
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.d b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.d
index ed8c368..8bd88b4 100644
--- a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.d
+++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.d
@@ -23,13 +23,22 @@ Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
- ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h:
 ../Core/Inc/stm32h7xx_hal_conf.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h:
@@ -53,6 +62,7 @@ Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
@@ -60,3 +70,11 @@ Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.o b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.o
index cce033a..40e8b8d 100644
Binary files a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.o and b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.o differ
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.d b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.d
index 011d337..25edddb 100644
--- a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.d
+++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.d
@@ -23,13 +23,22 @@ Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
- ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h:
 ../Core/Inc/stm32h7xx_hal_conf.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h:
@@ -53,6 +62,7 @@ Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
@@ -60,3 +70,11 @@ Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.o b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.o
index 7832633..eb4d9e2 100644
Binary files a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.o and b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.o differ
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.d b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.d
index 8596620..32ca4a3 100644
--- a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.d
+++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.d
@@ -23,13 +23,22 @@ Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
- ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h:
 ../Core/Inc/stm32h7xx_hal_conf.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h:
@@ -53,6 +62,7 @@ Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
@@ -60,3 +70,11 @@ Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.o b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.o
index 2abeb77..3444697 100644
Binary files a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.o and b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.o differ
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.d b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.d
index fc4af42..f80bde7 100644
--- a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.d
+++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.d
@@ -23,13 +23,22 @@ Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
- ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h:
 ../Core/Inc/stm32h7xx_hal_conf.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h:
@@ -53,6 +62,7 @@ Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
@@ -60,3 +70,11 @@ Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.o b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.o
index 2ae5146..4884bc2 100644
Binary files a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.o and b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.o differ
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.d b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.d
index bba4b19..87f298c 100644
--- a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.d
+++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.d
@@ -23,13 +23,22 @@ Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
- ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h:
 ../Core/Inc/stm32h7xx_hal_conf.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h:
@@ -53,6 +62,7 @@ Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
@@ -60,3 +70,11 @@ Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.o b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.o
index f4ac506..bcb6d2f 100644
Binary files a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.o and b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.o differ
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.d b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.d
index 962adae..ae495ab 100644
--- a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.d
+++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.d
@@ -23,13 +23,22 @@ Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
- ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h:
 ../Core/Inc/stm32h7xx_hal_conf.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h:
@@ -53,6 +62,7 @@ Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
@@ -60,3 +70,11 @@ Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.o b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.o
index 7fc1c12..c4b85dc 100644
Binary files a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.o and b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.o differ
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.cyclo b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.cyclo
new file mode 100644
index 0000000..7310c94
--- /dev/null
+++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.cyclo
@@ -0,0 +1,43 @@
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.c:338:19:HAL_SD_Init	12
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.c:469:19:HAL_SD_InitCard	7
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.c:559:19:HAL_SD_DeInit	2
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.c:616:13:HAL_SD_MspInit	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.c:631:13:HAL_SD_MspDeInit	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.c:672:19:HAL_SD_ReadBlocks	20
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.c:857:19:HAL_SD_WriteBlocks	20
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.c:1044:19:HAL_SD_ReadBlocks_IT	7
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.c:1139:19:HAL_SD_WriteBlocks_IT	7
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.c:1236:19:HAL_SD_ReadBlocks_DMA	7
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.c:1335:19:HAL_SD_WriteBlocks_DMA	7
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.c:1431:19:HAL_SD_Erase	11
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.c:1533:6:HAL_SD_IRQHandler	32
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.c:1768:21:HAL_SD_GetState	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.c:1779:10:HAL_SD_GetError	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.c:1789:13:HAL_SD_TxCpltCallback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.c:1804:13:HAL_SD_RxCpltCallback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.c:1819:13:HAL_SD_ErrorCallback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.c:1834:13:HAL_SD_AbortCallback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.c:2160:19:HAL_SD_GetCardCID	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.c:2193:19:HAL_SD_GetCardCSD	3
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.c:2307:19:HAL_SD_GetCardStatus	4
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.c:2377:19:HAL_SD_GetCardInfo	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.c:2402:19:HAL_SD_ConfigWideBusOperation	17
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.c:2566:19:HAL_SD_ConfigSpeedBusOperation	17
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.c:2864:25:HAL_SD_GetCardState	2
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.c:2887:19:HAL_SD_Abort	14
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.c:2983:19:HAL_SD_Abort_IT	4
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.c:3040:17:SD_InitCard	12
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.c:3137:17:SD_PowerON	13
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.c:3306:13:SD_PowerOFF	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.c:3319:17:SD_SendSDStatus	14
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.c:3425:17:SD_SendStatus	3
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.c:3452:17:SD_WideBus_Enable	6
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.c:3499:17:SD_WideBus_Disable	6
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.c:3548:17:SD_FindSCR	11
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.c:3644:13:SD_Read_IT	3
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.c:3679:13:SD_Write_IT	3
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.c:3717:10:SD_SwitchSpeed	13
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.c:4090:13:HAL_SDEx_Read_DMADoubleBuf0CpltCallback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.c:4105:13:HAL_SDEx_Read_DMADoubleBuf1CpltCallback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.c:4120:13:HAL_SDEx_Write_DMADoubleBuf0CpltCallback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.c:4135:13:HAL_SDEx_Write_DMADoubleBuf1CpltCallback	1
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.d b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.d
new file mode 100644
index 0000000..1e22a53
--- /dev/null
+++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.d
@@ -0,0 +1,80 @@
+Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.o: \
+ ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.c \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \
+ ../Core/Inc/stm32h7xx_hal_conf.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h \
+ ../Drivers/CMSIS/Include/core_cm7.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h:
+../Core/Inc/stm32h7xx_hal_conf.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h:
+../Drivers/CMSIS/Include/core_cm7.h:
+../Drivers/CMSIS/Include/cmsis_version.h:
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+../Drivers/CMSIS/Include/mpu_armv7.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.o b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.o
new file mode 100644
index 0000000..7b4cf07
Binary files /dev/null and b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.o differ
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.su b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.su
new file mode 100644
index 0000000..2a31d08
--- /dev/null
+++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.su
@@ -0,0 +1,43 @@
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.c:338:19:HAL_SD_Init	48	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.c:469:19:HAL_SD_InitCard	64	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.c:559:19:HAL_SD_DeInit	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.c:616:13:HAL_SD_MspInit	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.c:631:13:HAL_SD_MspDeInit	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.c:672:19:HAL_SD_ReadBlocks	80	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.c:857:19:HAL_SD_WriteBlocks	80	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.c:1044:19:HAL_SD_ReadBlocks_IT	56	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.c:1139:19:HAL_SD_WriteBlocks_IT	56	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.c:1236:19:HAL_SD_ReadBlocks_DMA	56	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.c:1335:19:HAL_SD_WriteBlocks_DMA	56	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.c:1431:19:HAL_SD_Erase	40	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.c:1533:6:HAL_SD_IRQHandler	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.c:1768:21:HAL_SD_GetState	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.c:1779:10:HAL_SD_GetError	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.c:1789:13:HAL_SD_TxCpltCallback	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.c:1804:13:HAL_SD_RxCpltCallback	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.c:1819:13:HAL_SD_ErrorCallback	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.c:1834:13:HAL_SD_AbortCallback	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.c:2160:19:HAL_SD_GetCardCID	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.c:2193:19:HAL_SD_GetCardCSD	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.c:2307:19:HAL_SD_GetCardStatus	88	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.c:2377:19:HAL_SD_GetCardInfo	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.c:2402:19:HAL_SD_ConfigWideBusOperation	64	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.c:2566:19:HAL_SD_ConfigSpeedBusOperation	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.c:2864:25:HAL_SD_GetCardState	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.c:2887:19:HAL_SD_Abort	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.c:2983:19:HAL_SD_Abort_IT	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.c:3040:17:SD_InitCard	72	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.c:3137:17:SD_PowerON	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.c:3306:13:SD_PowerOFF	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.c:3319:17:SD_SendSDStatus	56	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.c:3425:17:SD_SendStatus	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.c:3452:17:SD_WideBus_Enable	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.c:3499:17:SD_WideBus_Disable	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.c:3548:17:SD_FindSCR	64	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.c:3644:13:SD_Read_IT	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.c:3679:13:SD_Write_IT	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.c:3717:10:SD_SwitchSpeed	128	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.c:4090:13:HAL_SDEx_Read_DMADoubleBuf0CpltCallback	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.c:4105:13:HAL_SDEx_Read_DMADoubleBuf1CpltCallback	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.c:4120:13:HAL_SDEx_Write_DMADoubleBuf0CpltCallback	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.c:4135:13:HAL_SDEx_Write_DMADoubleBuf1CpltCallback	16	static
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd_ex.cyclo b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd_ex.cyclo
new file mode 100644
index 0000000..4010063
--- /dev/null
+++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd_ex.cyclo
@@ -0,0 +1,4 @@
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd_ex.c:83:19:HAL_SDEx_ConfigDMAMultiBuffer	2
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd_ex.c:109:19:HAL_SDEx_ReadBlocksDMAMultiBuffer	8
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd_ex.c:195:19:HAL_SDEx_WriteBlocksDMAMultiBuffer	8
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd_ex.c:279:19:HAL_SDEx_ChangeDMABuffer	2
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd_ex.d b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd_ex.d
new file mode 100644
index 0000000..204d84d
--- /dev/null
+++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd_ex.d
@@ -0,0 +1,80 @@
+Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd_ex.o: \
+ ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd_ex.c \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \
+ ../Core/Inc/stm32h7xx_hal_conf.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h \
+ ../Drivers/CMSIS/Include/core_cm7.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h:
+../Core/Inc/stm32h7xx_hal_conf.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h:
+../Drivers/CMSIS/Include/core_cm7.h:
+../Drivers/CMSIS/Include/cmsis_version.h:
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+../Drivers/CMSIS/Include/mpu_armv7.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd_ex.o b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd_ex.o
new file mode 100644
index 0000000..2391c5a
Binary files /dev/null and b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd_ex.o differ
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd_ex.su b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd_ex.su
new file mode 100644
index 0000000..b6a4c19
--- /dev/null
+++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd_ex.su
@@ -0,0 +1,4 @@
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd_ex.c:83:19:HAL_SDEx_ConfigDMAMultiBuffer	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd_ex.c:109:19:HAL_SDEx_ReadBlocksDMAMultiBuffer	64	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd_ex.c:195:19:HAL_SDEx_WriteBlocksDMAMultiBuffer	64	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd_ex.c:279:19:HAL_SDEx_ChangeDMABuffer	24	static
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.cyclo b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.cyclo
index e69de29..a78d2e2 100644
--- a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.cyclo
+++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.cyclo
@@ -0,0 +1,121 @@
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:269:19:HAL_TIM_Base_Init	3
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:329:19:HAL_TIM_Base_DeInit	3
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:372:13:HAL_TIM_Base_MspInit	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:387:13:HAL_TIM_Base_MspDeInit	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:403:19:HAL_TIM_Base_Start	14
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:442:19:HAL_TIM_Base_Stop	3
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:462:19:HAL_TIM_Base_Start_IT	14
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:504:19:HAL_TIM_Base_Stop_IT	3
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:529:19:HAL_TIM_Base_Start_DMA	18
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:598:19:HAL_TIM_Base_Stop_DMA	3
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:653:19:HAL_TIM_OC_Init	3
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:713:19:HAL_TIM_OC_DeInit	3
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:756:13:HAL_TIM_OC_MspInit	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:771:13:HAL_TIM_OC_MspDeInit	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:794:19:HAL_TIM_OC_Start	30
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:850:19:HAL_TIM_OC_Stop	16
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:885:19:HAL_TIM_OC_Start_IT	35
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:978:19:HAL_TIM_OC_Stop_IT	21
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:1055:19:HAL_TIM_OC_Start_DMA	47
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:1219:19:HAL_TIM_OC_Stop_DMA	21
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:1322:19:HAL_TIM_PWM_Init	3
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:1382:19:HAL_TIM_PWM_DeInit	3
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:1425:13:HAL_TIM_PWM_MspInit	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:1440:13:HAL_TIM_PWM_MspDeInit	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:1463:19:HAL_TIM_PWM_Start	30
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:1519:19:HAL_TIM_PWM_Stop	16
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:1554:19:HAL_TIM_PWM_Start_IT	35
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:1647:19:HAL_TIM_PWM_Stop_IT	21
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:1724:19:HAL_TIM_PWM_Start_DMA	47
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:1887:19:HAL_TIM_PWM_Stop_DMA	21
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:1990:19:HAL_TIM_IC_Init	3
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:2050:19:HAL_TIM_IC_DeInit	3
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:2093:13:HAL_TIM_IC_MspInit	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:2108:13:HAL_TIM_IC_MspDeInit	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:2129:19:HAL_TIM_IC_Start	31
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:2181:19:HAL_TIM_IC_Stop	11
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:2211:19:HAL_TIM_IC_Start_IT	36
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:2303:19:HAL_TIM_IC_Stop_IT	16
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:2375:19:HAL_TIM_IC_Start_DMA	43
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:2534:19:HAL_TIM_IC_Stop_DMA	16
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:2639:19:HAL_TIM_OnePulse_Init	3
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:2708:19:HAL_TIM_OnePulse_DeInit	3
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:2753:13:HAL_TIM_OnePulse_MspInit	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:2768:13:HAL_TIM_OnePulse_MspDeInit	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:2788:19:HAL_TIM_OnePulse_Start	11
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:2845:19:HAL_TIM_OnePulse_Stop	11
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:2888:19:HAL_TIM_OnePulse_Start_IT	11
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:2951:19:HAL_TIM_OnePulse_Stop_IT	11
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:3030:19:HAL_TIM_Encoder_Init	3
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:3145:19:HAL_TIM_Encoder_DeInit	3
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:3190:13:HAL_TIM_Encoder_MspInit	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:3205:13:HAL_TIM_Encoder_MspDeInit	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:3225:19:HAL_TIM_Encoder_Start	13
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:3319:19:HAL_TIM_Encoder_Stop	15
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:3379:19:HAL_TIM_Encoder_Start_IT	13
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:3479:19:HAL_TIM_Encoder_Stop_IT	15
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:3544:19:HAL_TIM_Encoder_Start_DMA	32
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:3757:19:HAL_TIM_Encoder_Stop_DMA	15
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:3834:6:HAL_TIM_IRQHandler	23
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:4064:19:HAL_TIM_OC_ConfigChannel	8
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:4163:19:HAL_TIM_IC_ConfigChannel	6
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:4264:19:HAL_TIM_PWM_ConfigChannel	8
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:4412:19:HAL_TIM_OnePulse_ConfigChannel	8
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:4567:19:HAL_TIM_DMABurst_WriteStart	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:4626:19:HAL_TIM_DMABurst_MultiWriteStart	25
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:4810:19:HAL_TIM_DMABurst_WriteStop	14
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:4918:19:HAL_TIM_DMABurst_ReadStart	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:4976:19:HAL_TIM_DMABurst_MultiReadStart	25
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:5160:19:HAL_TIM_DMABurst_ReadStop	14
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:5244:19:HAL_TIM_GenerateEvent	2
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:5283:19:HAL_TIM_ConfigOCrefClear	18
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:5441:19:HAL_TIM_ConfigClockSource	30
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:5600:19:HAL_TIM_ConfigTI1Input	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:5632:19:HAL_TIM_SlaveConfigSynchro	3
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:5672:19:HAL_TIM_SlaveConfigSynchro_IT	3
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:5715:10:HAL_TIM_ReadCapturedValue	5
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:5799:13:HAL_TIM_PeriodElapsedCallback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:5814:13:HAL_TIM_PeriodElapsedHalfCpltCallback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:5829:13:HAL_TIM_OC_DelayElapsedCallback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:5844:13:HAL_TIM_IC_CaptureCallback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:5859:13:HAL_TIM_IC_CaptureHalfCpltCallback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:5874:13:HAL_TIM_PWM_PulseFinishedCallback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:5889:13:HAL_TIM_PWM_PulseFinishedHalfCpltCallback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:5904:13:HAL_TIM_TriggerCallback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:5919:13:HAL_TIM_TriggerHalfCpltCallback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:5934:13:HAL_TIM_ErrorCallback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:6492:22:HAL_TIM_Base_GetState	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:6502:22:HAL_TIM_OC_GetState	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:6512:22:HAL_TIM_PWM_GetState	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:6522:22:HAL_TIM_IC_GetState	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:6532:22:HAL_TIM_OnePulse_GetState	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:6542:22:HAL_TIM_Encoder_GetState	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:6552:23:HAL_TIM_GetActiveChannel	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:6570:29:HAL_TIM_GetChannelState	6
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:6587:30:HAL_TIM_DMABurstState	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:6612:6:TIM_DMAError	5
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:6655:13:TIM_DMADelayPulseCplt	9
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:6714:6:TIM_DMADelayPulseHalfCplt	5
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:6753:6:TIM_DMACaptureCplt	9
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:6816:6:TIM_DMACaptureHalfCplt	5
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:6855:13:TIM_DMAPeriodElapsedCplt	2
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:6876:13:TIM_DMAPeriodElapsedHalfCplt	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:6892:13:TIM_DMATriggerCplt	2
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:6913:13:TIM_DMATriggerHalfCplt	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:6930:6:TIM_Base_SetConfig	23
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:6978:13:TIM_OC1_SetConfig	11
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:7053:6:TIM_OC2_SetConfig	8
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:7129:13:TIM_OC3_SetConfig	8
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:7203:13:TIM_OC4_SetConfig	6
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:7263:13:TIM_OC5_SetConfig	6
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:7316:13:TIM_OC6_SetConfig	6
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:7370:26:TIM_SlaveTimer_SetConfig	36
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:7514:6:TIM_TI1_SetConfig	12
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:7561:13:TIM_TI1_ConfigInputStage	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:7604:13:TIM_TI2_SetConfig	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:7644:13:TIM_TI2_ConfigInputStage	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:7687:13:TIM_TI3_SetConfig	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:7735:13:TIM_TI4_SetConfig	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:7791:13:TIM_ITRx_SetConfig	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:7821:6:TIM_ETR_SetConfig	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:7853:6:TIM_CCxChannelCmd	1
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.d b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.d
index 353ea59..ddba55b 100644
--- a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.d
+++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.d
@@ -23,13 +23,22 @@ Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
- ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h:
 ../Core/Inc/stm32h7xx_hal_conf.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h:
@@ -53,6 +62,7 @@ Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
@@ -60,3 +70,11 @@ Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.o b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.o
index b93754c..3bd6ecd 100644
Binary files a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.o and b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.o differ
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.su b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.su
index e69de29..d1887a0 100644
--- a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.su
+++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.su
@@ -0,0 +1,121 @@
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:269:19:HAL_TIM_Base_Init	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:329:19:HAL_TIM_Base_DeInit	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:372:13:HAL_TIM_Base_MspInit	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:387:13:HAL_TIM_Base_MspDeInit	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:403:19:HAL_TIM_Base_Start	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:442:19:HAL_TIM_Base_Stop	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:462:19:HAL_TIM_Base_Start_IT	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:504:19:HAL_TIM_Base_Stop_IT	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:529:19:HAL_TIM_Base_Start_DMA	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:598:19:HAL_TIM_Base_Stop_DMA	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:653:19:HAL_TIM_OC_Init	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:713:19:HAL_TIM_OC_DeInit	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:756:13:HAL_TIM_OC_MspInit	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:771:13:HAL_TIM_OC_MspDeInit	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:794:19:HAL_TIM_OC_Start	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:850:19:HAL_TIM_OC_Stop	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:885:19:HAL_TIM_OC_Start_IT	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:978:19:HAL_TIM_OC_Stop_IT	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:1055:19:HAL_TIM_OC_Start_DMA	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:1219:19:HAL_TIM_OC_Stop_DMA	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:1322:19:HAL_TIM_PWM_Init	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:1382:19:HAL_TIM_PWM_DeInit	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:1425:13:HAL_TIM_PWM_MspInit	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:1440:13:HAL_TIM_PWM_MspDeInit	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:1463:19:HAL_TIM_PWM_Start	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:1519:19:HAL_TIM_PWM_Stop	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:1554:19:HAL_TIM_PWM_Start_IT	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:1647:19:HAL_TIM_PWM_Stop_IT	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:1724:19:HAL_TIM_PWM_Start_DMA	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:1887:19:HAL_TIM_PWM_Stop_DMA	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:1990:19:HAL_TIM_IC_Init	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:2050:19:HAL_TIM_IC_DeInit	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:2093:13:HAL_TIM_IC_MspInit	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:2108:13:HAL_TIM_IC_MspDeInit	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:2129:19:HAL_TIM_IC_Start	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:2181:19:HAL_TIM_IC_Stop	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:2211:19:HAL_TIM_IC_Start_IT	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:2303:19:HAL_TIM_IC_Stop_IT	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:2375:19:HAL_TIM_IC_Start_DMA	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:2534:19:HAL_TIM_IC_Stop_DMA	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:2639:19:HAL_TIM_OnePulse_Init	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:2708:19:HAL_TIM_OnePulse_DeInit	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:2753:13:HAL_TIM_OnePulse_MspInit	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:2768:13:HAL_TIM_OnePulse_MspDeInit	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:2788:19:HAL_TIM_OnePulse_Start	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:2845:19:HAL_TIM_OnePulse_Stop	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:2888:19:HAL_TIM_OnePulse_Start_IT	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:2951:19:HAL_TIM_OnePulse_Stop_IT	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:3030:19:HAL_TIM_Encoder_Init	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:3145:19:HAL_TIM_Encoder_DeInit	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:3190:13:HAL_TIM_Encoder_MspInit	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:3205:13:HAL_TIM_Encoder_MspDeInit	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:3225:19:HAL_TIM_Encoder_Start	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:3319:19:HAL_TIM_Encoder_Stop	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:3379:19:HAL_TIM_Encoder_Start_IT	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:3479:19:HAL_TIM_Encoder_Stop_IT	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:3544:19:HAL_TIM_Encoder_Start_DMA	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:3757:19:HAL_TIM_Encoder_Stop_DMA	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:3834:6:HAL_TIM_IRQHandler	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:4064:19:HAL_TIM_OC_ConfigChannel	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:4163:19:HAL_TIM_IC_ConfigChannel	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:4264:19:HAL_TIM_PWM_ConfigChannel	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:4412:19:HAL_TIM_OnePulse_ConfigChannel	56	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:4567:19:HAL_TIM_DMABurst_WriteStart	40	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:4626:19:HAL_TIM_DMABurst_MultiWriteStart	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:4810:19:HAL_TIM_DMABurst_WriteStop	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:4918:19:HAL_TIM_DMABurst_ReadStart	40	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:4976:19:HAL_TIM_DMABurst_MultiReadStart	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:5160:19:HAL_TIM_DMABurst_ReadStop	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:5244:19:HAL_TIM_GenerateEvent	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:5283:19:HAL_TIM_ConfigOCrefClear	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:5441:19:HAL_TIM_ConfigClockSource	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:5600:19:HAL_TIM_ConfigTI1Input	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:5632:19:HAL_TIM_SlaveConfigSynchro	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:5672:19:HAL_TIM_SlaveConfigSynchro_IT	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:5715:10:HAL_TIM_ReadCapturedValue	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:5799:13:HAL_TIM_PeriodElapsedCallback	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:5814:13:HAL_TIM_PeriodElapsedHalfCpltCallback	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:5829:13:HAL_TIM_OC_DelayElapsedCallback	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:5844:13:HAL_TIM_IC_CaptureCallback	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:5859:13:HAL_TIM_IC_CaptureHalfCpltCallback	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:5874:13:HAL_TIM_PWM_PulseFinishedCallback	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:5889:13:HAL_TIM_PWM_PulseFinishedHalfCpltCallback	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:5904:13:HAL_TIM_TriggerCallback	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:5919:13:HAL_TIM_TriggerHalfCpltCallback	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:5934:13:HAL_TIM_ErrorCallback	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:6492:22:HAL_TIM_Base_GetState	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:6502:22:HAL_TIM_OC_GetState	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:6512:22:HAL_TIM_PWM_GetState	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:6522:22:HAL_TIM_IC_GetState	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:6532:22:HAL_TIM_OnePulse_GetState	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:6542:22:HAL_TIM_Encoder_GetState	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:6552:23:HAL_TIM_GetActiveChannel	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:6570:29:HAL_TIM_GetChannelState	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:6587:30:HAL_TIM_DMABurstState	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:6612:6:TIM_DMAError	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:6655:13:TIM_DMADelayPulseCplt	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:6714:6:TIM_DMADelayPulseHalfCplt	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:6753:6:TIM_DMACaptureCplt	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:6816:6:TIM_DMACaptureHalfCplt	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:6855:13:TIM_DMAPeriodElapsedCplt	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:6876:13:TIM_DMAPeriodElapsedHalfCplt	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:6892:13:TIM_DMATriggerCplt	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:6913:13:TIM_DMATriggerHalfCplt	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:6930:6:TIM_Base_SetConfig	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:6978:13:TIM_OC1_SetConfig	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:7053:6:TIM_OC2_SetConfig	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:7129:13:TIM_OC3_SetConfig	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:7203:13:TIM_OC4_SetConfig	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:7263:13:TIM_OC5_SetConfig	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:7316:13:TIM_OC6_SetConfig	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:7370:26:TIM_SlaveTimer_SetConfig	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:7514:6:TIM_TI1_SetConfig	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:7561:13:TIM_TI1_ConfigInputStage	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:7604:13:TIM_TI2_SetConfig	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:7644:13:TIM_TI2_ConfigInputStage	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:7687:13:TIM_TI3_SetConfig	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:7735:13:TIM_TI4_SetConfig	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:7791:13:TIM_ITRx_SetConfig	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:7821:6:TIM_ETR_SetConfig	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:7853:6:TIM_CCxChannelCmd	32	static
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.cyclo b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.cyclo
index e69de29..8d7f11c 100644
--- a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.cyclo
+++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.cyclo
@@ -0,0 +1,48 @@
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:152:19:HAL_TIMEx_HallSensor_Init	3
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:254:19:HAL_TIMEx_HallSensor_DeInit	3
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:299:13:HAL_TIMEx_HallSensor_MspInit	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:314:13:HAL_TIMEx_HallSensor_MspDeInit	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:329:19:HAL_TIMEx_HallSensor_Start	17
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:383:19:HAL_TIMEx_HallSensor_Stop	3
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:411:19:HAL_TIMEx_HallSensor_Start_IT	17
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:468:19:HAL_TIMEx_HallSensor_Stop_IT	3
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:501:19:HAL_TIMEx_HallSensor_Start_DMA	20
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:577:19:HAL_TIMEx_HallSensor_Stop_DMA	3
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:639:19:HAL_TIMEx_OCN_Start	20
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:690:19:HAL_TIMEx_OCN_Stop	8
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:722:19:HAL_TIMEx_OCN_Start_IT	25
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:809:19:HAL_TIMEx_OCN_Stop_IT	14
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:884:19:HAL_TIMEx_OCN_Start_DMA	34
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:1022:19:HAL_TIMEx_OCN_Stop_DMA	13
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:1123:19:HAL_TIMEx_PWMN_Start	20
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:1173:19:HAL_TIMEx_PWMN_Stop	8
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:1205:19:HAL_TIMEx_PWMN_Start_IT	25
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:1291:19:HAL_TIMEx_PWMN_Stop_IT	14
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:1366:19:HAL_TIMEx_PWMN_Start_DMA	34
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:1504:19:HAL_TIMEx_PWMN_Stop_DMA	13
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:1595:19:HAL_TIMEx_OnePulseN_Start	6
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:1644:19:HAL_TIMEx_OnePulseN_Stop	6
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:1683:19:HAL_TIMEx_OnePulseN_Start_IT	6
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:1738:19:HAL_TIMEx_OnePulseN_Stop_IT	6
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:1821:19:HAL_TIMEx_ConfigCommutEvent	8
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:1880:19:HAL_TIMEx_ConfigCommutEvent_IT	8
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:1943:19:HAL_TIMEx_ConfigCommutEvent_DMA	8
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:1993:19:HAL_TIMEx_MasterConfigSynchronization	14
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:2066:19:HAL_TIMEx_ConfigBreakDeadTime	8
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:2153:19:HAL_TIMEx_ConfigBreakInput	10
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:2337:19:HAL_TIMEx_RemapConfig	2
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:2431:20:HAL_TIMEx_TISelection	6
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:2476:19:HAL_TIMEx_GroupChannel5	2
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:2515:19:HAL_TIMEx_DisarmBreakInput	7
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:2570:19:HAL_TIMEx_ReArmBreakInput	11
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:2660:13:HAL_TIMEx_CommutCallback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:2674:13:HAL_TIMEx_CommutHalfCpltCallback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:2689:13:HAL_TIMEx_BreakCallback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:2704:13:HAL_TIMEx_Break2Callback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:2737:22:HAL_TIMEx_HallSensor_GetState	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:2752:29:HAL_TIMEx_GetChannelNState	4
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:2781:6:TIMEx_DMACommutationCplt	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:2800:6:TIMEx_DMACommutationHalfCplt	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:2820:13:TIM_DMADelayPulseNCplt	9
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:2879:13:TIM_DMAErrorCCxN	4
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:2924:13:TIM_CCxNChannelCmd	1
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.d b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.d
index 6521462..bde049f 100644
--- a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.d
+++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.d
@@ -23,13 +23,22 @@ Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
- ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h:
 ../Core/Inc/stm32h7xx_hal_conf.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h:
@@ -53,6 +62,7 @@ Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
@@ -60,3 +70,11 @@ Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.o b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.o
index e17b3d1..ac3b99e 100644
Binary files a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.o and b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.o differ
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.su b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.su
index e69de29..99072ca 100644
--- a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.su
+++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.su
@@ -0,0 +1,48 @@
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:152:19:HAL_TIMEx_HallSensor_Init	48	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:254:19:HAL_TIMEx_HallSensor_DeInit	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:299:13:HAL_TIMEx_HallSensor_MspInit	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:314:13:HAL_TIMEx_HallSensor_MspDeInit	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:329:19:HAL_TIMEx_HallSensor_Start	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:383:19:HAL_TIMEx_HallSensor_Stop	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:411:19:HAL_TIMEx_HallSensor_Start_IT	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:468:19:HAL_TIMEx_HallSensor_Stop_IT	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:501:19:HAL_TIMEx_HallSensor_Start_DMA	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:577:19:HAL_TIMEx_HallSensor_Stop_DMA	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:639:19:HAL_TIMEx_OCN_Start	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:690:19:HAL_TIMEx_OCN_Stop	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:722:19:HAL_TIMEx_OCN_Start_IT	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:809:19:HAL_TIMEx_OCN_Stop_IT	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:884:19:HAL_TIMEx_OCN_Start_DMA	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:1022:19:HAL_TIMEx_OCN_Stop_DMA	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:1123:19:HAL_TIMEx_PWMN_Start	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:1173:19:HAL_TIMEx_PWMN_Stop	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:1205:19:HAL_TIMEx_PWMN_Start_IT	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:1291:19:HAL_TIMEx_PWMN_Stop_IT	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:1366:19:HAL_TIMEx_PWMN_Start_DMA	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:1504:19:HAL_TIMEx_PWMN_Stop_DMA	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:1595:19:HAL_TIMEx_OnePulseN_Start	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:1644:19:HAL_TIMEx_OnePulseN_Stop	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:1683:19:HAL_TIMEx_OnePulseN_Start_IT	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:1738:19:HAL_TIMEx_OnePulseN_Stop_IT	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:1821:19:HAL_TIMEx_ConfigCommutEvent	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:1880:19:HAL_TIMEx_ConfigCommutEvent_IT	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:1943:19:HAL_TIMEx_ConfigCommutEvent_DMA	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:1993:19:HAL_TIMEx_MasterConfigSynchronization	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:2066:19:HAL_TIMEx_ConfigBreakDeadTime	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:2153:19:HAL_TIMEx_ConfigBreakInput	48	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:2337:19:HAL_TIMEx_RemapConfig	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:2431:20:HAL_TIMEx_TISelection	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:2476:19:HAL_TIMEx_GroupChannel5	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:2515:19:HAL_TIMEx_DisarmBreakInput	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:2570:19:HAL_TIMEx_ReArmBreakInput	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:2660:13:HAL_TIMEx_CommutCallback	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:2674:13:HAL_TIMEx_CommutHalfCpltCallback	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:2689:13:HAL_TIMEx_BreakCallback	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:2704:13:HAL_TIMEx_Break2Callback	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:2737:22:HAL_TIMEx_HallSensor_GetState	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:2752:29:HAL_TIMEx_GetChannelNState	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:2781:6:TIMEx_DMACommutationCplt	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:2800:6:TIMEx_DMACommutationHalfCplt	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:2820:13:TIM_DMADelayPulseNCplt	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:2879:13:TIM_DMAErrorCCxN	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:2924:13:TIM_CCxNChannelCmd	32	static
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.cyclo b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.cyclo
new file mode 100644
index 0000000..0648c5c
--- /dev/null
+++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.cyclo
@@ -0,0 +1,70 @@
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:307:19:HAL_UART_Init	5
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:380:19:HAL_HalfDuplex_Init	5
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:453:19:HAL_LIN_Init	7
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:550:19:HAL_MultiProcessor_Init	6
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:624:19:HAL_UART_DeInit	2
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:671:13:HAL_UART_MspInit	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:686:13:HAL_UART_MspDeInit	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:1120:19:HAL_UART_Transmit	10
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:1210:19:HAL_UART_Receive	15
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:1294:19:HAL_UART_Transmit_IT	11
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:1362:19:HAL_UART_Receive_IT	7
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:1403:19:HAL_UART_Transmit_DMA	7
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:1473:19:HAL_UART_Receive_DMA	7
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:1509:19:HAL_UART_DMAPause	9
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:1539:19:HAL_UART_DMAResume	8
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:1570:19:HAL_UART_DMAStop	13
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:1645:19:HAL_UART_Abort	16
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:1748:19:HAL_UART_AbortTransmit	9
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:1807:19:HAL_UART_AbortReceive	10
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:1875:19:HAL_UART_Abort_IT	19
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:2028:19:HAL_UART_AbortTransmit_IT	8
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:2119:19:HAL_UART_AbortReceive_IT	9
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:2212:6:HAL_UART_IRQHandler	75
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:2542:13:HAL_UART_TxCpltCallback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:2557:13:HAL_UART_TxHalfCpltCallback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:2572:13:HAL_UART_RxCpltCallback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:2587:13:HAL_UART_RxHalfCpltCallback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:2602:13:HAL_UART_ErrorCallback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:2617:13:HAL_UART_AbortCpltCallback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:2632:13:HAL_UART_AbortTransmitCpltCallback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:2647:13:HAL_UART_AbortReceiveCpltCallback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:2664:13:HAL_UARTEx_RxEventCallback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:2712:6:HAL_UART_ReceiverTimeout_Config	2
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:2727:19:HAL_UART_EnableReceiverTimeout	4
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:2765:19:HAL_UART_DisableReceiverTimeout	4
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:2803:19:HAL_MultiProcessor_EnableMuteMode	3
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:2823:19:HAL_MultiProcessor_DisableMuteMode	3
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:2843:6:HAL_MultiProcessor_EnterMuteMode	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:2853:19:HAL_HalfDuplex_EnableTransmitter	4
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:2876:19:HAL_HalfDuplex_EnableReceiver	4
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:2900:19:HAL_LIN_SendBreak	2
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:2945:23:HAL_UART_GetState	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:2961:10:HAL_UART_GetError	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:3007:19:UART_SetConfig	121
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:3271:6:UART_AdvFeatureConfig	10
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:3345:19:UART_CheckIdleState	8
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:3414:19:UART_WaitOnFlagUntilTimeout	8
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:3482:19:UART_Start_Receive_IT	20
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:3554:19:UART_Start_Receive_DMA	7
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:3611:13:UART_EndTxTransfer	3
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:3627:13:UART_EndRxTransfer	5
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:3653:13:UART_DMATransmitCplt	4
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:3687:13:UART_DMATxHalfCplt	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:3705:13:UART_DMAReceiveCplt	8
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:3766:13:UART_DMARxHalfCplt	2
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:3804:13:UART_DMAError	5
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:3844:13:UART_DMAAbortOnError	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:3867:13:UART_DMATxAbortCallback	4
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:3922:13:UART_DMARxAbortCallback	3
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:3974:13:UART_DMATxOnlyAbortCallback	2
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:4007:13:UART_DMARxOnlyAbortCallback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:4040:13:UART_TxISR_8BIT	5
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:4069:13:UART_TxISR_16BIT	5
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:4101:13:UART_TxISR_8BIT_FIFOEN	7
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:4141:13:UART_TxISR_16BIT_FIFOEN	7
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:4182:13:UART_EndTransmit_IT	2
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:4207:13:UART_RxISR_8BIT	11
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:4298:13:UART_RxISR_16BIT	11
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:4391:13:UART_RxISR_8BIT_FIFOEN	25
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:4553:13:UART_RxISR_16BIT_FIFOEN	25
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.d b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.d
new file mode 100644
index 0000000..0622b7a
--- /dev/null
+++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.d
@@ -0,0 +1,80 @@
+Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.o: \
+ ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \
+ ../Core/Inc/stm32h7xx_hal_conf.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h \
+ ../Drivers/CMSIS/Include/core_cm7.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h:
+../Core/Inc/stm32h7xx_hal_conf.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h:
+../Drivers/CMSIS/Include/core_cm7.h:
+../Drivers/CMSIS/Include/cmsis_version.h:
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+../Drivers/CMSIS/Include/mpu_armv7.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.o b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.o
new file mode 100644
index 0000000..a91da8e
Binary files /dev/null and b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.o differ
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.su b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.su
new file mode 100644
index 0000000..3e7b582
--- /dev/null
+++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.su
@@ -0,0 +1,70 @@
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:307:19:HAL_UART_Init	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:380:19:HAL_HalfDuplex_Init	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:453:19:HAL_LIN_Init	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:550:19:HAL_MultiProcessor_Init	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:624:19:HAL_UART_DeInit	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:671:13:HAL_UART_MspInit	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:686:13:HAL_UART_MspDeInit	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:1120:19:HAL_UART_Transmit	48	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:1210:19:HAL_UART_Receive	48	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:1294:19:HAL_UART_Transmit_IT	72	static,ignoring_inline_asm
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:1362:19:HAL_UART_Receive_IT	48	static,ignoring_inline_asm
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:1403:19:HAL_UART_Transmit_DMA	48	static,ignoring_inline_asm
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:1473:19:HAL_UART_Receive_DMA	48	static,ignoring_inline_asm
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:1509:19:HAL_UART_DMAPause	120	static,ignoring_inline_asm
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:1539:19:HAL_UART_DMAResume	112	static,ignoring_inline_asm
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:1570:19:HAL_UART_DMAStop	72	static,ignoring_inline_asm
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:1645:19:HAL_UART_Abort	136	static,ignoring_inline_asm
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:1748:19:HAL_UART_AbortTransmit	88	static,ignoring_inline_asm
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:1807:19:HAL_UART_AbortReceive	112	static,ignoring_inline_asm
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:1875:19:HAL_UART_Abort_IT	144	static,ignoring_inline_asm
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:2028:19:HAL_UART_AbortTransmit_IT	88	static,ignoring_inline_asm
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:2119:19:HAL_UART_AbortReceive_IT	112	static,ignoring_inline_asm
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:2212:6:HAL_UART_IRQHandler	240	static,ignoring_inline_asm
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:2542:13:HAL_UART_TxCpltCallback	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:2557:13:HAL_UART_TxHalfCpltCallback	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:2572:13:HAL_UART_RxCpltCallback	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:2587:13:HAL_UART_RxHalfCpltCallback	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:2602:13:HAL_UART_ErrorCallback	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:2617:13:HAL_UART_AbortCpltCallback	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:2632:13:HAL_UART_AbortTransmitCpltCallback	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:2647:13:HAL_UART_AbortReceiveCpltCallback	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:2664:13:HAL_UARTEx_RxEventCallback	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:2712:6:HAL_UART_ReceiverTimeout_Config	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:2727:19:HAL_UART_EnableReceiverTimeout	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:2765:19:HAL_UART_DisableReceiverTimeout	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:2803:19:HAL_MultiProcessor_EnableMuteMode	40	static,ignoring_inline_asm
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:2823:19:HAL_MultiProcessor_DisableMuteMode	40	static,ignoring_inline_asm
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:2843:6:HAL_MultiProcessor_EnterMuteMode	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:2853:19:HAL_HalfDuplex_EnableTransmitter	64	static,ignoring_inline_asm
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:2876:19:HAL_HalfDuplex_EnableReceiver	64	static,ignoring_inline_asm
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:2900:19:HAL_LIN_SendBreak	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:2945:23:HAL_UART_GetState	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:2961:10:HAL_UART_GetError	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:3007:19:UART_SetConfig	104	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:3271:6:UART_AdvFeatureConfig	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:3345:19:UART_CheckIdleState	104	static,ignoring_inline_asm
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:3414:19:UART_WaitOnFlagUntilTimeout	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:3482:19:UART_Start_Receive_IT	144	static,ignoring_inline_asm
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:3554:19:UART_Start_Receive_DMA	96	static,ignoring_inline_asm
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:3611:13:UART_EndTxTransfer	64	static,ignoring_inline_asm
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:3627:13:UART_EndRxTransfer	88	static,ignoring_inline_asm
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:3653:13:UART_DMATransmitCplt	72	static,ignoring_inline_asm
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:3687:13:UART_DMATxHalfCplt	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:3705:13:UART_DMAReceiveCplt	120	static,ignoring_inline_asm
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:3766:13:UART_DMARxHalfCplt	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:3804:13:UART_DMAError	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:3844:13:UART_DMAAbortOnError	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:3867:13:UART_DMATxAbortCallback	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:3922:13:UART_DMARxAbortCallback	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:3974:13:UART_DMATxOnlyAbortCallback	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:4007:13:UART_DMARxOnlyAbortCallback	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:4040:13:UART_TxISR_8BIT	64	static,ignoring_inline_asm
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:4069:13:UART_TxISR_16BIT	72	static,ignoring_inline_asm
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:4101:13:UART_TxISR_8BIT_FIFOEN	72	static,ignoring_inline_asm
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:4141:13:UART_TxISR_16BIT_FIFOEN	72	static,ignoring_inline_asm
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:4182:13:UART_EndTransmit_IT	40	static,ignoring_inline_asm
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:4207:13:UART_RxISR_8BIT	120	static,ignoring_inline_asm
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:4298:13:UART_RxISR_16BIT	120	static,ignoring_inline_asm
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:4391:13:UART_RxISR_8BIT_FIFOEN	184	static,ignoring_inline_asm
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:4553:13:UART_RxISR_16BIT_FIFOEN	192	static,ignoring_inline_asm
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.cyclo b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.cyclo
new file mode 100644
index 0000000..4a5ac70
--- /dev/null
+++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.cyclo
@@ -0,0 +1,18 @@
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c:166:19:HAL_RS485Ex_Init	5
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c:272:13:HAL_UARTEx_WakeupCallback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c:287:13:HAL_UARTEx_RxFifoFullCallback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c:302:13:HAL_UARTEx_TxFifoEmptyCallback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c:387:19:HAL_MultiProcessorEx_AddressLength_Set	2
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c:425:19:HAL_UARTEx_StopModeWakeUpSourceConfig	4
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c:480:19:HAL_UARTEx_EnableStopMode	3
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c:499:19:HAL_UARTEx_DisableStopMode	3
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c:518:19:HAL_UARTEx_EnableFifoMode	2
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c:559:19:HAL_UARTEx_DisableFifoMode	2
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c:605:19:HAL_UARTEx_SetTxFifoThreshold	2
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c:654:19:HAL_UARTEx_SetRxFifoThreshold	2
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c:711:19:HAL_UARTEx_ReceiveToIdle	20
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c:834:19:HAL_UARTEx_ReceiveToIdle_IT	7
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c:895:19:HAL_UARTEx_ReceiveToIdle_DMA	7
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c:963:29:HAL_UARTEx_GetRxEventType	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c:987:13:UARTEx_Wakeup_AddressConfig	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c:1005:13:UARTEx_SetNbDataToProcess	2
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.d b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.d
new file mode 100644
index 0000000..d525292
--- /dev/null
+++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.d
@@ -0,0 +1,80 @@
+Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.o: \
+ ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \
+ ../Core/Inc/stm32h7xx_hal_conf.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h \
+ ../Drivers/CMSIS/Include/core_cm7.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h:
+../Core/Inc/stm32h7xx_hal_conf.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h:
+../Drivers/CMSIS/Include/core_cm7.h:
+../Drivers/CMSIS/Include/cmsis_version.h:
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+../Drivers/CMSIS/Include/mpu_armv7.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.o b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.o
new file mode 100644
index 0000000..f4897d4
Binary files /dev/null and b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.o differ
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.su b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.su
new file mode 100644
index 0000000..5ab233f
--- /dev/null
+++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.su
@@ -0,0 +1,18 @@
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c:166:19:HAL_RS485Ex_Init	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c:272:13:HAL_UARTEx_WakeupCallback	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c:287:13:HAL_UARTEx_RxFifoFullCallback	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c:302:13:HAL_UARTEx_TxFifoEmptyCallback	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c:387:19:HAL_MultiProcessorEx_AddressLength_Set	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c:425:19:HAL_UARTEx_StopModeWakeUpSourceConfig	40	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c:480:19:HAL_UARTEx_EnableStopMode	40	static,ignoring_inline_asm
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c:499:19:HAL_UARTEx_DisableStopMode	40	static,ignoring_inline_asm
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c:518:19:HAL_UARTEx_EnableFifoMode	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c:559:19:HAL_UARTEx_DisableFifoMode	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c:605:19:HAL_UARTEx_SetTxFifoThreshold	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c:654:19:HAL_UARTEx_SetRxFifoThreshold	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c:711:19:HAL_UARTEx_ReceiveToIdle	40	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c:834:19:HAL_UARTEx_ReceiveToIdle_IT	56	static,ignoring_inline_asm
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c:895:19:HAL_UARTEx_ReceiveToIdle_DMA	56	static,ignoring_inline_asm
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c:963:29:HAL_UARTEx_GetRxEventType	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c:987:13:UARTEx_Wakeup_AddressConfig	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c:1005:13:UARTEx_SetNbDataToProcess	24	static
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_delayblock.cyclo b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_delayblock.cyclo
new file mode 100644
index 0000000..ae23ebd
--- /dev/null
+++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_delayblock.cyclo
@@ -0,0 +1,3 @@
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_delayblock.c:101:19:DelayBlock_Enable	9
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_delayblock.c:171:19:DelayBlock_Disable	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_delayblock.c:185:19:DelayBlock_Configure	1
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_delayblock.d b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_delayblock.d
new file mode 100644
index 0000000..1ffd401
--- /dev/null
+++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_delayblock.d
@@ -0,0 +1,80 @@
+Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_delayblock.o: \
+ ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_delayblock.c \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \
+ ../Core/Inc/stm32h7xx_hal_conf.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h \
+ ../Drivers/CMSIS/Include/core_cm7.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h:
+../Core/Inc/stm32h7xx_hal_conf.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h:
+../Drivers/CMSIS/Include/core_cm7.h:
+../Drivers/CMSIS/Include/cmsis_version.h:
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+../Drivers/CMSIS/Include/mpu_armv7.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_delayblock.o b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_delayblock.o
new file mode 100644
index 0000000..0604d1f
Binary files /dev/null and b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_delayblock.o differ
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_delayblock.su b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_delayblock.su
new file mode 100644
index 0000000..354ccc4
--- /dev/null
+++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_delayblock.su
@@ -0,0 +1,3 @@
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_delayblock.c:101:19:DelayBlock_Enable	48	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_delayblock.c:171:19:DelayBlock_Disable	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_delayblock.c:185:19:DelayBlock_Configure	24	static
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.cyclo b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.cyclo
new file mode 100644
index 0000000..9f00e95
--- /dev/null
+++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.cyclo
@@ -0,0 +1,49 @@
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.c:200:19:SDMMC_Init	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.c:251:10:SDMMC_ReadFIFO	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.c:263:19:SDMMC_WriteFIFO	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.c:295:19:SDMMC_PowerState_ON	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.c:308:19:SDMMC_PowerState_Cycle	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.c:321:19:SDMMC_PowerState_OFF	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.c:338:10:SDMMC_GetPowerState	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.c:351:19:SDMMC_SendCommand	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.c:381:9:SDMMC_GetCommandResponse	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.c:398:10:SDMMC_GetResponse	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.c:419:19:SDMMC_ConfigData	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.c:454:10:SDMMC_GetDataCounter	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.c:464:10:SDMMC_GetFIFOCount	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.c:478:19:SDMMC_SetSDMMCReadWaitMode	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.c:513:10:SDMMC_CmdBlockLength	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.c:537:10:SDMMC_CmdReadSingleBlock	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.c:561:10:SDMMC_CmdReadMultiBlock	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.c:585:10:SDMMC_CmdWriteSingleBlock	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.c:609:10:SDMMC_CmdWriteMultiBlock	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.c:633:10:SDMMC_CmdSDEraseStartAdd	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.c:657:10:SDMMC_CmdSDEraseEndAdd	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.c:681:10:SDMMC_CmdEraseStartAdd	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.c:705:10:SDMMC_CmdEraseEndAdd	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.c:730:10:SDMMC_CmdErase	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.c:754:10:SDMMC_CmdStopTransfer	2
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.c:791:10:SDMMC_CmdSelDesel	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.c:815:10:SDMMC_CmdGoIdleState	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.c:838:10:SDMMC_CmdOperCond	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.c:869:10:SDMMC_CmdAppCommand	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.c:897:10:SDMMC_CmdAppOperCommand	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.c:921:10:SDMMC_CmdBusWidth	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.c:944:10:SDMMC_CmdSendSCR	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.c:968:10:SDMMC_CmdSendCID	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.c:993:10:SDMMC_CmdSendCSD	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.c:1018:10:SDMMC_CmdSetRelAdd	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.c:1043:10:SDMMC_CmdSetRelAddMmc	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.c:1068:10:SDMMC_CmdSleepMmc	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.c:1093:10:SDMMC_CmdSendStatus	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.c:1116:10:SDMMC_CmdStatusRegister	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.c:1141:10:SDMMC_CmdOpCondition	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.c:1165:10:SDMMC_CmdSwitch	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.c:1191:10:SDMMC_CmdVoltageSwitch	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.c:1215:10:SDMMC_CmdSendEXTCSD	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.c:1258:10:SDMMC_GetCmdResp1	26
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.c:1393:10:SDMMC_GetCmdResp2	6
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.c:1437:10:SDMMC_GetCmdResp3	5
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.c:1477:10:SDMMC_GetCmdResp6	10
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.c:1551:10:SDMMC_GetCmdResp7	7
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.c:1612:17:SDMMC_GetCmdError	3
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.d b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.d
new file mode 100644
index 0000000..fd447e2
--- /dev/null
+++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.d
@@ -0,0 +1,80 @@
+Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.o: \
+ ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.c \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \
+ ../Core/Inc/stm32h7xx_hal_conf.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h \
+ ../Drivers/CMSIS/Include/core_cm7.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h:
+../Core/Inc/stm32h7xx_hal_conf.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h:
+../Drivers/CMSIS/Include/core_cm7.h:
+../Drivers/CMSIS/Include/cmsis_version.h:
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+../Drivers/CMSIS/Include/mpu_armv7.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.o b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.o
new file mode 100644
index 0000000..fe7b092
Binary files /dev/null and b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.o differ
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.su b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.su
new file mode 100644
index 0000000..ea361f3
--- /dev/null
+++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.su
@@ -0,0 +1,49 @@
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.c:200:19:SDMMC_Init	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.c:251:10:SDMMC_ReadFIFO	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.c:263:19:SDMMC_WriteFIFO	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.c:295:19:SDMMC_PowerState_ON	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.c:308:19:SDMMC_PowerState_Cycle	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.c:321:19:SDMMC_PowerState_OFF	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.c:338:10:SDMMC_GetPowerState	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.c:351:19:SDMMC_SendCommand	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.c:381:9:SDMMC_GetCommandResponse	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.c:398:10:SDMMC_GetResponse	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.c:419:19:SDMMC_ConfigData	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.c:454:10:SDMMC_GetDataCounter	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.c:464:10:SDMMC_GetFIFOCount	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.c:478:19:SDMMC_SetSDMMCReadWaitMode	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.c:513:10:SDMMC_CmdBlockLength	40	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.c:537:10:SDMMC_CmdReadSingleBlock	40	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.c:561:10:SDMMC_CmdReadMultiBlock	40	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.c:585:10:SDMMC_CmdWriteSingleBlock	40	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.c:609:10:SDMMC_CmdWriteMultiBlock	40	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.c:633:10:SDMMC_CmdSDEraseStartAdd	40	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.c:657:10:SDMMC_CmdSDEraseEndAdd	40	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.c:681:10:SDMMC_CmdEraseStartAdd	40	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.c:705:10:SDMMC_CmdEraseEndAdd	40	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.c:730:10:SDMMC_CmdErase	40	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.c:754:10:SDMMC_CmdStopTransfer	40	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.c:791:10:SDMMC_CmdSelDesel	40	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.c:815:10:SDMMC_CmdGoIdleState	40	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.c:838:10:SDMMC_CmdOperCond	40	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.c:869:10:SDMMC_CmdAppCommand	40	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.c:897:10:SDMMC_CmdAppOperCommand	40	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.c:921:10:SDMMC_CmdBusWidth	40	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.c:944:10:SDMMC_CmdSendSCR	40	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.c:968:10:SDMMC_CmdSendCID	40	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.c:993:10:SDMMC_CmdSendCSD	40	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.c:1018:10:SDMMC_CmdSetRelAdd	40	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.c:1043:10:SDMMC_CmdSetRelAddMmc	40	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.c:1068:10:SDMMC_CmdSleepMmc	40	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.c:1093:10:SDMMC_CmdSendStatus	40	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.c:1116:10:SDMMC_CmdStatusRegister	40	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.c:1141:10:SDMMC_CmdOpCondition	40	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.c:1165:10:SDMMC_CmdSwitch	40	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.c:1191:10:SDMMC_CmdVoltageSwitch	40	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.c:1215:10:SDMMC_CmdSendEXTCSD	40	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.c:1258:10:SDMMC_GetCmdResp1	40	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.c:1393:10:SDMMC_GetCmdResp2	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.c:1437:10:SDMMC_GetCmdResp3	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.c:1477:10:SDMMC_GetCmdResp6	40	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.c:1551:10:SDMMC_GetCmdResp7	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.c:1612:17:SDMMC_GetCmdError	24	static
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/subdir.mk b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/subdir.mk
index 2e7edff..54a053b 100644
--- a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/subdir.mk
+++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/subdir.mk
@@ -12,6 +12,7 @@ C_SRCS += \
 ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c \
 ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.c \
 ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c \
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c \
 ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c \
 ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c \
 ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c \
@@ -23,8 +24,14 @@ C_SRCS += \
 ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c \
 ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c \
 ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c \
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.c \
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd_ex.c \
 ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c \
-../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c 
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c \
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c \
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c \
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_delayblock.c \
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.c 
 
 OBJS += \
 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.o \
@@ -34,6 +41,7 @@ OBJS += \
 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o \
 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.o \
 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.o \
+./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o \
 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.o \
 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.o \
 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.o \
@@ -45,8 +53,14 @@ OBJS += \
 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.o \
 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.o \
 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.o \
+./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.o \
+./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd_ex.o \
 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.o \
-./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.o 
+./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.o \
+./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.o \
+./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.o \
+./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_delayblock.o \
+./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.o 
 
 C_DEPS += \
 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.d \
@@ -56,6 +70,7 @@ C_DEPS += \
 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.d \
 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.d \
 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.d \
+./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.d \
 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.d \
 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.d \
 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.d \
@@ -67,18 +82,25 @@ C_DEPS += \
 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.d \
 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.d \
 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.d \
+./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.d \
+./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd_ex.d \
 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.d \
-./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.d 
+./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.d \
+./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.d \
+./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.d \
+./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_delayblock.d \
+./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.d 
 
 
 # Each subdirectory must supply rules for building sources it contributes
 Drivers/STM32H7xx_HAL_Driver/Src/%.o Drivers/STM32H7xx_HAL_Driver/Src/%.su Drivers/STM32H7xx_HAL_Driver/Src/%.cyclo: ../Drivers/STM32H7xx_HAL_Driver/Src/%.c Drivers/STM32H7xx_HAL_Driver/Src/subdir.mk
-	arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DDEBUG -DDATA_IN_D2_SRAM -DUSE_HAL_DRIVER -DSTM32H723xx -c -I../Core/Inc -I../Drivers/STM32H7xx_HAL_Driver/Inc -I../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32H7xx/Include -I../Drivers/CMSIS/Include -I../LWIP/App -I../LWIP/Target -I../Middlewares/Third_Party/LwIP/src/include -I../Middlewares/Third_Party/LwIP/system -I../Drivers/BSP/Components/lan8742 -I../Middlewares/Third_Party/LwIP/src/include/netif/ppp -I../Middlewares/Third_Party/LwIP/src/include/lwip -I../Middlewares/Third_Party/LwIP/src/include/lwip/apps -I../Middlewares/Third_Party/LwIP/src/include/lwip/priv -I../Middlewares/Third_Party/LwIP/src/include/lwip/prot -I../Middlewares/Third_Party/LwIP/src/include/netif -I../Middlewares/Third_Party/LwIP/src/include/compat/posix -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/arpa -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/net -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/sys -I../Middlewares/Third_Party/LwIP/src/include/compat/stdc -I../Middlewares/Third_Party/LwIP/system/arch -I"C:/_NoSleep/STM32/lwip_test/LWFTP" -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
+	arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DDEBUG -DDATA_IN_D2_SRAM -DUSE_HAL_DRIVER -DSTM32H723xx -c -I../Core/Inc -I../FATFS/Target -I../FATFS/App -I../LWIP/App -I../LWIP/Target -I../Middlewares/Third_Party/LwIP/src/include -I../Middlewares/Third_Party/LwIP/system -I../Drivers/STM32H7xx_HAL_Driver/Inc -I../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F -I../Middlewares/Third_Party/FatFs/src -I../Drivers/BSP/Components/lan8742 -I../Middlewares/Third_Party/LwIP/src/include/netif/ppp -I../Drivers/CMSIS/Device/ST/STM32H7xx/Include -I../Middlewares/Third_Party/LwIP/src/include/lwip -I../Middlewares/Third_Party/LwIP/src/include/lwip/apps -I../Middlewares/Third_Party/LwIP/src/include/lwip/priv -I../Middlewares/Third_Party/LwIP/src/include/lwip/prot -I../Middlewares/Third_Party/LwIP/src/include/netif -I../Middlewares/Third_Party/LwIP/src/include/compat/posix -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/arpa -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/net -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/sys -I../Middlewares/Third_Party/LwIP/src/include/compat/stdc -I../Middlewares/Third_Party/LwIP/system/arch -I../Drivers/CMSIS/Include -I"C:/_NoSleep/STM32/TBD_TaxiBoard/LWFTPC" -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
 
 clean: clean-Drivers-2f-STM32H7xx_HAL_Driver-2f-Src
 
 clean-Drivers-2f-STM32H7xx_HAL_Driver-2f-Src:
-	-$(RM) ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.cyclo ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.d ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.o ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.su ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.cyclo ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.d ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.o ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.su ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.cyclo ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.d ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.o ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.su ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.cyclo ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.d ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.o ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.su ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.cyclo ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.d ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.su ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.cyclo ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.d ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.o ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.su ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.cyclo ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.d ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.o ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.su ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.cyclo ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.d ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.o ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.su ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.cyclo ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.d ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.o ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.su ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.cyclo ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.d ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.o ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.su ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.cyclo ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.d ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.o ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.su ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.cyclo ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.d ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.o ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.su ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.cyclo ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.d ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.o ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.su ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.cyclo ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.d ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.o ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.su ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.cyclo ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.d ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.o ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.su ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.cyclo ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.d ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.o ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.su ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.cyclo ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.d ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.o ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.su ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.cyclo ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.d ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.o ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.su ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.cyclo ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.d ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.o ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.su ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.cyclo ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.d ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.o ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.su
+	-$(RM) ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.cyclo ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.d ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.o ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.su ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.cyclo ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.d ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.o ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.su ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.cyclo ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.d ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.o ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.su ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.cyclo ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.d ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.o ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.su ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.cyclo ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.d ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.su ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.cyclo ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.d ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.o ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.su ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.cyclo ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.d ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.o ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.su ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.cyclo ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.d ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.su ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.cyclo ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.d ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.o ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.su ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.cyclo ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.d ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.o ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.su ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.cyclo ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.d ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.o ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.su ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.cyclo ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.d ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.o ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.su ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.cyclo ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.d ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.o ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.su ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.cyclo ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.d ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.o ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.su ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.cyclo ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.d ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.o ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.su ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.cyclo ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.d ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.o ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.su ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.cyclo ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.d ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.o ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.su ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.cyclo ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.d ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.o ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.su ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.cyclo ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.d ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.o ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.su ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.cyclo ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.d ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.o ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.su ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd_ex.cyclo ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd_ex.d ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd_ex.o ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd_ex.su ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.cyclo ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.d ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.o ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.su ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.cyclo ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.d ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.o ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.su ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.cyclo ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.d ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.o ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.su ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.cyclo ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.d ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.o ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.su ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_delayblock.cyclo ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_delayblock.d ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_delayblock.o
+	-$(RM) ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_delayblock.su ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.cyclo ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.d ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.o ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.su
 
 .PHONY: clean-Drivers-2f-STM32H7xx_HAL_Driver-2f-Src
 
diff --git a/Debug/FATFS/App/fatfs.cyclo b/Debug/FATFS/App/fatfs.cyclo
new file mode 100644
index 0000000..fd3a79a
--- /dev/null
+++ b/Debug/FATFS/App/fatfs.cyclo
@@ -0,0 +1,2 @@
+../FATFS/App/fatfs.c:30:6:MX_FATFS_Init	1
+../FATFS/App/fatfs.c:45:7:get_fattime	1
diff --git a/Debug/FATFS/App/fatfs.d b/Debug/FATFS/App/fatfs.d
new file mode 100644
index 0000000..9316492
--- /dev/null
+++ b/Debug/FATFS/App/fatfs.d
@@ -0,0 +1,130 @@
+FATFS/App/fatfs.o: ../FATFS/App/fatfs.c ../FATFS/App/fatfs.h \
+ ../Middlewares/Third_Party/FatFs/src/ff.h \
+ ../Middlewares/Third_Party/FatFs/src/integer.h ../FATFS/Target/ffconf.h \
+ ../Core/Inc/main.h ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \
+ ../Core/Inc/stm32h7xx_hal_conf.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h \
+ ../Drivers/CMSIS/Include/core_cm7.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \
+ ../FATFS/Target/bsp_driver_sd.h ../FATFS/Target/fatfs_platform.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h \
+ ../Core/Inc/FreeRTOSConfig.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/list.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h \
+ ../Middlewares/Third_Party/FatFs/src/ff_gen_drv.h \
+ ../Middlewares/Third_Party/FatFs/src/diskio.h \
+ ../Middlewares/Third_Party/FatFs/src/ff.h ../FATFS/Target/sd_diskio.h
+../FATFS/App/fatfs.h:
+../Middlewares/Third_Party/FatFs/src/ff.h:
+../Middlewares/Third_Party/FatFs/src/integer.h:
+../FATFS/Target/ffconf.h:
+../Core/Inc/main.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h:
+../Core/Inc/stm32h7xx_hal_conf.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h:
+../Drivers/CMSIS/Include/core_cm7.h:
+../Drivers/CMSIS/Include/cmsis_version.h:
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+../Drivers/CMSIS/Include/mpu_armv7.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
+../FATFS/Target/bsp_driver_sd.h:
+../FATFS/Target/fatfs_platform.h:
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h:
+../Core/Inc/FreeRTOSConfig.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h:
+../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/task.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/list.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/task.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h:
+../Middlewares/Third_Party/FatFs/src/ff_gen_drv.h:
+../Middlewares/Third_Party/FatFs/src/diskio.h:
+../Middlewares/Third_Party/FatFs/src/ff.h:
+../FATFS/Target/sd_diskio.h:
diff --git a/Debug/FATFS/App/fatfs.o b/Debug/FATFS/App/fatfs.o
new file mode 100644
index 0000000..e7da2b2
Binary files /dev/null and b/Debug/FATFS/App/fatfs.o differ
diff --git a/Debug/FATFS/App/fatfs.su b/Debug/FATFS/App/fatfs.su
new file mode 100644
index 0000000..fe846d1
--- /dev/null
+++ b/Debug/FATFS/App/fatfs.su
@@ -0,0 +1,2 @@
+../FATFS/App/fatfs.c:30:6:MX_FATFS_Init	8	static
+../FATFS/App/fatfs.c:45:7:get_fattime	4	static
diff --git a/Debug/FATFS/App/subdir.mk b/Debug/FATFS/App/subdir.mk
new file mode 100644
index 0000000..34f3e55
--- /dev/null
+++ b/Debug/FATFS/App/subdir.mk
@@ -0,0 +1,27 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+# Toolchain: GNU Tools for STM32 (11.3.rel1)
+################################################################################
+
+# Add inputs and outputs from these tool invocations to the build variables 
+C_SRCS += \
+../FATFS/App/fatfs.c 
+
+OBJS += \
+./FATFS/App/fatfs.o 
+
+C_DEPS += \
+./FATFS/App/fatfs.d 
+
+
+# Each subdirectory must supply rules for building sources it contributes
+FATFS/App/%.o FATFS/App/%.su FATFS/App/%.cyclo: ../FATFS/App/%.c FATFS/App/subdir.mk
+	arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DDEBUG -DDATA_IN_D2_SRAM -DUSE_HAL_DRIVER -DSTM32H723xx -c -I../Core/Inc -I../FATFS/Target -I../FATFS/App -I../LWIP/App -I../LWIP/Target -I../Middlewares/Third_Party/LwIP/src/include -I../Middlewares/Third_Party/LwIP/system -I../Drivers/STM32H7xx_HAL_Driver/Inc -I../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F -I../Middlewares/Third_Party/FatFs/src -I../Drivers/BSP/Components/lan8742 -I../Middlewares/Third_Party/LwIP/src/include/netif/ppp -I../Drivers/CMSIS/Device/ST/STM32H7xx/Include -I../Middlewares/Third_Party/LwIP/src/include/lwip -I../Middlewares/Third_Party/LwIP/src/include/lwip/apps -I../Middlewares/Third_Party/LwIP/src/include/lwip/priv -I../Middlewares/Third_Party/LwIP/src/include/lwip/prot -I../Middlewares/Third_Party/LwIP/src/include/netif -I../Middlewares/Third_Party/LwIP/src/include/compat/posix -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/arpa -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/net -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/sys -I../Middlewares/Third_Party/LwIP/src/include/compat/stdc -I../Middlewares/Third_Party/LwIP/system/arch -I../Drivers/CMSIS/Include -I"C:/_NoSleep/STM32/TBD_TaxiBoard/LWFTPC" -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
+
+clean: clean-FATFS-2f-App
+
+clean-FATFS-2f-App:
+	-$(RM) ./FATFS/App/fatfs.cyclo ./FATFS/App/fatfs.d ./FATFS/App/fatfs.o ./FATFS/App/fatfs.su
+
+.PHONY: clean-FATFS-2f-App
+
diff --git a/Debug/FATFS/Target/bsp_driver_sd.cyclo b/Debug/FATFS/Target/bsp_driver_sd.cyclo
new file mode 100644
index 0000000..3f3e2f6
--- /dev/null
+++ b/Debug/FATFS/Target/bsp_driver_sd.cyclo
@@ -0,0 +1,16 @@
+../FATFS/Target/bsp_driver_sd.c:42:16:BSP_SD_Init	4
+../FATFS/Target/bsp_driver_sd.c:73:16:BSP_SD_ITConfig	1
+../FATFS/Target/bsp_driver_sd.c:93:16:BSP_SD_ReadBlocks	2
+../FATFS/Target/bsp_driver_sd.c:116:16:BSP_SD_WriteBlocks	2
+../FATFS/Target/bsp_driver_sd.c:138:16:BSP_SD_ReadBlocks_DMA	2
+../FATFS/Target/bsp_driver_sd.c:161:16:BSP_SD_WriteBlocks_DMA	2
+../FATFS/Target/bsp_driver_sd.c:183:16:BSP_SD_Erase	2
+../FATFS/Target/bsp_driver_sd.c:207:16:BSP_SD_GetCardState	1
+../FATFS/Target/bsp_driver_sd.c:217:13:BSP_SD_GetCardInfo	1
+../FATFS/Target/bsp_driver_sd.c:231:6:HAL_SD_AbortCallback	1
+../FATFS/Target/bsp_driver_sd.c:241:6:HAL_SD_TxCpltCallback	1
+../FATFS/Target/bsp_driver_sd.c:251:6:HAL_SD_RxCpltCallback	1
+../FATFS/Target/bsp_driver_sd.c:262:13:BSP_SD_AbortCallback	1
+../FATFS/Target/bsp_driver_sd.c:272:13:BSP_SD_WriteCpltCallback	1
+../FATFS/Target/bsp_driver_sd.c:282:13:BSP_SD_ReadCpltCallback	1
+../FATFS/Target/bsp_driver_sd.c:293:16:BSP_SD_IsDetected	2
diff --git a/Debug/FATFS/Target/bsp_driver_sd.d b/Debug/FATFS/Target/bsp_driver_sd.d
new file mode 100644
index 0000000..d948f1d
--- /dev/null
+++ b/Debug/FATFS/Target/bsp_driver_sd.d
@@ -0,0 +1,83 @@
+FATFS/Target/bsp_driver_sd.o: ../FATFS/Target/bsp_driver_sd.c \
+ ../FATFS/Target/bsp_driver_sd.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \
+ ../Core/Inc/stm32h7xx_hal_conf.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h \
+ ../Drivers/CMSIS/Include/core_cm7.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \
+ ../FATFS/Target/fatfs_platform.h
+../FATFS/Target/bsp_driver_sd.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h:
+../Core/Inc/stm32h7xx_hal_conf.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h:
+../Drivers/CMSIS/Include/core_cm7.h:
+../Drivers/CMSIS/Include/cmsis_version.h:
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+../Drivers/CMSIS/Include/mpu_armv7.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
+../FATFS/Target/fatfs_platform.h:
diff --git a/Debug/FATFS/Target/bsp_driver_sd.o b/Debug/FATFS/Target/bsp_driver_sd.o
new file mode 100644
index 0000000..c4eaca6
Binary files /dev/null and b/Debug/FATFS/Target/bsp_driver_sd.o differ
diff --git a/Debug/FATFS/Target/bsp_driver_sd.su b/Debug/FATFS/Target/bsp_driver_sd.su
new file mode 100644
index 0000000..7786cd6
--- /dev/null
+++ b/Debug/FATFS/Target/bsp_driver_sd.su
@@ -0,0 +1,16 @@
+../FATFS/Target/bsp_driver_sd.c:42:16:BSP_SD_Init	16	static
+../FATFS/Target/bsp_driver_sd.c:73:16:BSP_SD_ITConfig	4	static
+../FATFS/Target/bsp_driver_sd.c:93:16:BSP_SD_ReadBlocks	40	static
+../FATFS/Target/bsp_driver_sd.c:116:16:BSP_SD_WriteBlocks	40	static
+../FATFS/Target/bsp_driver_sd.c:138:16:BSP_SD_ReadBlocks_DMA	32	static
+../FATFS/Target/bsp_driver_sd.c:161:16:BSP_SD_WriteBlocks_DMA	32	static
+../FATFS/Target/bsp_driver_sd.c:183:16:BSP_SD_Erase	24	static
+../FATFS/Target/bsp_driver_sd.c:207:16:BSP_SD_GetCardState	8	static
+../FATFS/Target/bsp_driver_sd.c:217:13:BSP_SD_GetCardInfo	16	static
+../FATFS/Target/bsp_driver_sd.c:231:6:HAL_SD_AbortCallback	16	static
+../FATFS/Target/bsp_driver_sd.c:241:6:HAL_SD_TxCpltCallback	16	static
+../FATFS/Target/bsp_driver_sd.c:251:6:HAL_SD_RxCpltCallback	16	static
+../FATFS/Target/bsp_driver_sd.c:262:13:BSP_SD_AbortCallback	4	static
+../FATFS/Target/bsp_driver_sd.c:272:13:BSP_SD_WriteCpltCallback	4	static
+../FATFS/Target/bsp_driver_sd.c:282:13:BSP_SD_ReadCpltCallback	4	static
+../FATFS/Target/bsp_driver_sd.c:293:16:BSP_SD_IsDetected	16	static
diff --git a/Debug/FATFS/Target/fatfs_platform.cyclo b/Debug/FATFS/Target/fatfs_platform.cyclo
new file mode 100644
index 0000000..7822056
--- /dev/null
+++ b/Debug/FATFS/Target/fatfs_platform.cyclo
@@ -0,0 +1 @@
+../FATFS/Target/fatfs_platform.c:21:9:BSP_PlatformIsDetected	2
diff --git a/Debug/FATFS/Target/fatfs_platform.d b/Debug/FATFS/Target/fatfs_platform.d
new file mode 100644
index 0000000..d5aff44
--- /dev/null
+++ b/Debug/FATFS/Target/fatfs_platform.d
@@ -0,0 +1,81 @@
+FATFS/Target/fatfs_platform.o: ../FATFS/Target/fatfs_platform.c \
+ ../FATFS/Target/fatfs_platform.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \
+ ../Core/Inc/stm32h7xx_hal_conf.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h \
+ ../Drivers/CMSIS/Include/core_cm7.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h
+../FATFS/Target/fatfs_platform.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h:
+../Core/Inc/stm32h7xx_hal_conf.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h:
+../Drivers/CMSIS/Include/core_cm7.h:
+../Drivers/CMSIS/Include/cmsis_version.h:
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+../Drivers/CMSIS/Include/mpu_armv7.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
diff --git a/Debug/FATFS/Target/fatfs_platform.o b/Debug/FATFS/Target/fatfs_platform.o
new file mode 100644
index 0000000..1ac1ada
Binary files /dev/null and b/Debug/FATFS/Target/fatfs_platform.o differ
diff --git a/Debug/FATFS/Target/fatfs_platform.su b/Debug/FATFS/Target/fatfs_platform.su
new file mode 100644
index 0000000..c157f48
--- /dev/null
+++ b/Debug/FATFS/Target/fatfs_platform.su
@@ -0,0 +1 @@
+../FATFS/Target/fatfs_platform.c:21:9:BSP_PlatformIsDetected	16	static
diff --git a/Debug/FATFS/Target/sd_diskio.cyclo b/Debug/FATFS/Target/sd_diskio.cyclo
new file mode 100644
index 0000000..6dc4f5c
--- /dev/null
+++ b/Debug/FATFS/Target/sd_diskio.cyclo
@@ -0,0 +1,9 @@
+../FATFS/Target/sd_diskio.c:138:12:SD_CheckStatusWithTimeout	3
+../FATFS/Target/sd_diskio.c:159:16:SD_CheckStatus	2
+../FATFS/Target/sd_diskio.c:176:9:SD_initialize	6
+../FATFS/Target/sd_diskio.c:233:9:SD_status	1
+../FATFS/Target/sd_diskio.c:250:9:SD_read	7
+../FATFS/Target/sd_diskio.c:411:9:SD_write	7
+../FATFS/Target/sd_diskio.c:578:9:SD_ioctl	6
+../FATFS/Target/sd_diskio.c:633:6:BSP_SD_WriteCpltCallback	1
+../FATFS/Target/sd_diskio.c:653:6:BSP_SD_ReadCpltCallback	1
diff --git a/Debug/FATFS/Target/sd_diskio.d b/Debug/FATFS/Target/sd_diskio.d
new file mode 100644
index 0000000..d0d200e
--- /dev/null
+++ b/Debug/FATFS/Target/sd_diskio.d
@@ -0,0 +1,128 @@
+FATFS/Target/sd_diskio.o: ../FATFS/Target/sd_diskio.c \
+ ../Middlewares/Third_Party/FatFs/src/ff_gen_drv.h \
+ ../Middlewares/Third_Party/FatFs/src/diskio.h \
+ ../Middlewares/Third_Party/FatFs/src/integer.h \
+ ../Middlewares/Third_Party/FatFs/src/ff.h ../FATFS/Target/ffconf.h \
+ ../Core/Inc/main.h ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \
+ ../Core/Inc/stm32h7xx_hal_conf.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h \
+ ../Drivers/CMSIS/Include/core_cm7.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \
+ ../FATFS/Target/bsp_driver_sd.h ../FATFS/Target/fatfs_platform.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h \
+ ../Core/Inc/FreeRTOSConfig.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/list.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h \
+ ../FATFS/Target/sd_diskio.h
+../Middlewares/Third_Party/FatFs/src/ff_gen_drv.h:
+../Middlewares/Third_Party/FatFs/src/diskio.h:
+../Middlewares/Third_Party/FatFs/src/integer.h:
+../Middlewares/Third_Party/FatFs/src/ff.h:
+../FATFS/Target/ffconf.h:
+../Core/Inc/main.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h:
+../Core/Inc/stm32h7xx_hal_conf.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h:
+../Drivers/CMSIS/Include/core_cm7.h:
+../Drivers/CMSIS/Include/cmsis_version.h:
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+../Drivers/CMSIS/Include/mpu_armv7.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
+../FATFS/Target/bsp_driver_sd.h:
+../FATFS/Target/fatfs_platform.h:
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h:
+../Core/Inc/FreeRTOSConfig.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h:
+../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/task.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/list.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/task.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h:
+../FATFS/Target/sd_diskio.h:
diff --git a/Debug/FATFS/Target/sd_diskio.o b/Debug/FATFS/Target/sd_diskio.o
new file mode 100644
index 0000000..4c1566a
Binary files /dev/null and b/Debug/FATFS/Target/sd_diskio.o differ
diff --git a/Debug/FATFS/Target/sd_diskio.su b/Debug/FATFS/Target/sd_diskio.su
new file mode 100644
index 0000000..8fd255c
--- /dev/null
+++ b/Debug/FATFS/Target/sd_diskio.su
@@ -0,0 +1,9 @@
+../FATFS/Target/sd_diskio.c:138:12:SD_CheckStatusWithTimeout	24	static
+../FATFS/Target/sd_diskio.c:159:16:SD_CheckStatus	16	static
+../FATFS/Target/sd_diskio.c:176:9:SD_initialize	40	static
+../FATFS/Target/sd_diskio.c:233:9:SD_status	16	static
+../FATFS/Target/sd_diskio.c:250:9:SD_read	48	static
+../FATFS/Target/sd_diskio.c:411:9:SD_write	48	static
+../FATFS/Target/sd_diskio.c:578:9:SD_ioctl	56	static
+../FATFS/Target/sd_diskio.c:633:6:BSP_SD_WriteCpltCallback	8	static
+../FATFS/Target/sd_diskio.c:653:6:BSP_SD_ReadCpltCallback	8	static
diff --git a/Debug/FATFS/Target/subdir.mk b/Debug/FATFS/Target/subdir.mk
new file mode 100644
index 0000000..235c089
--- /dev/null
+++ b/Debug/FATFS/Target/subdir.mk
@@ -0,0 +1,33 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+# Toolchain: GNU Tools for STM32 (11.3.rel1)
+################################################################################
+
+# Add inputs and outputs from these tool invocations to the build variables 
+C_SRCS += \
+../FATFS/Target/bsp_driver_sd.c \
+../FATFS/Target/fatfs_platform.c \
+../FATFS/Target/sd_diskio.c 
+
+OBJS += \
+./FATFS/Target/bsp_driver_sd.o \
+./FATFS/Target/fatfs_platform.o \
+./FATFS/Target/sd_diskio.o 
+
+C_DEPS += \
+./FATFS/Target/bsp_driver_sd.d \
+./FATFS/Target/fatfs_platform.d \
+./FATFS/Target/sd_diskio.d 
+
+
+# Each subdirectory must supply rules for building sources it contributes
+FATFS/Target/%.o FATFS/Target/%.su FATFS/Target/%.cyclo: ../FATFS/Target/%.c FATFS/Target/subdir.mk
+	arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DDEBUG -DDATA_IN_D2_SRAM -DUSE_HAL_DRIVER -DSTM32H723xx -c -I../Core/Inc -I../FATFS/Target -I../FATFS/App -I../LWIP/App -I../LWIP/Target -I../Middlewares/Third_Party/LwIP/src/include -I../Middlewares/Third_Party/LwIP/system -I../Drivers/STM32H7xx_HAL_Driver/Inc -I../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F -I../Middlewares/Third_Party/FatFs/src -I../Drivers/BSP/Components/lan8742 -I../Middlewares/Third_Party/LwIP/src/include/netif/ppp -I../Drivers/CMSIS/Device/ST/STM32H7xx/Include -I../Middlewares/Third_Party/LwIP/src/include/lwip -I../Middlewares/Third_Party/LwIP/src/include/lwip/apps -I../Middlewares/Third_Party/LwIP/src/include/lwip/priv -I../Middlewares/Third_Party/LwIP/src/include/lwip/prot -I../Middlewares/Third_Party/LwIP/src/include/netif -I../Middlewares/Third_Party/LwIP/src/include/compat/posix -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/arpa -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/net -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/sys -I../Middlewares/Third_Party/LwIP/src/include/compat/stdc -I../Middlewares/Third_Party/LwIP/system/arch -I../Drivers/CMSIS/Include -I"C:/_NoSleep/STM32/TBD_TaxiBoard/LWFTPC" -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
+
+clean: clean-FATFS-2f-Target
+
+clean-FATFS-2f-Target:
+	-$(RM) ./FATFS/Target/bsp_driver_sd.cyclo ./FATFS/Target/bsp_driver_sd.d ./FATFS/Target/bsp_driver_sd.o ./FATFS/Target/bsp_driver_sd.su ./FATFS/Target/fatfs_platform.cyclo ./FATFS/Target/fatfs_platform.d ./FATFS/Target/fatfs_platform.o ./FATFS/Target/fatfs_platform.su ./FATFS/Target/sd_diskio.cyclo ./FATFS/Target/sd_diskio.d ./FATFS/Target/sd_diskio.o ./FATFS/Target/sd_diskio.su
+
+.PHONY: clean-FATFS-2f-Target
+
diff --git a/Debug/LWFTP/lwftp.cyclo b/Debug/LWFTP/lwftp.cyclo
deleted file mode 100644
index 39e66f6..0000000
--- a/Debug/LWFTP/lwftp.cyclo
+++ /dev/null
@@ -1,22 +0,0 @@
-../LWFTP/lwftp.c:57:14:lwftp_pcb_close	2
-../LWFTP/lwftp.c:75:14:lwftp_send_next_data	5
-../LWFTP/lwftp.c:103:14:lwftp_data_recv	5
-../LWFTP/lwftp.c:133:14:lwftp_data_sent	2
-../LWFTP/lwftp.c:146:13:lwftp_data_err	3
-../LWFTP/lwftp.c:164:14:lwftp_data_connected	2
-../LWFTP/lwftp.c:180:14:lwftp_data_open	3
-../LWFTP/lwftp.c:216:14:lwftp_send_msg	2
-../LWFTP/lwftp.c:231:13:lwftp_data_close	3
-../LWFTP/lwftp.c:245:13:lwftp_control_close	5
-../LWFTP/lwftp.c:265:13:lwftp_control_process	39
-../LWFTP/lwftp.c:429:13:lwftp_start_RETR	3
-../LWFTP/lwftp.c:446:13:lwftp_start_STOR	3
-../LWFTP/lwftp.c:463:13:lwftp_send_QUIT	2
-../LWFTP/lwftp.c:479:14:lwftp_control_recv	3
-../LWFTP/lwftp.c:503:14:lwftp_control_sent	1
-../LWFTP/lwftp.c:512:13:lwftp_control_err	3
-../LWFTP/lwftp.c:534:14:lwftp_control_connected	3
-../LWFTP/lwftp.c:551:7:lwftp_connect	9
-../LWFTP/lwftp.c:593:7:lwftp_retrieve	7
-../LWFTP/lwftp.c:627:7:lwftp_store	7
-../LWFTP/lwftp.c:677:6:lwftp_close	4
diff --git a/Debug/LWFTP/lwftp.o b/Debug/LWFTP/lwftp.o
deleted file mode 100644
index acdab9b..0000000
Binary files a/Debug/LWFTP/lwftp.o and /dev/null differ
diff --git a/Debug/LWFTP/lwftp.su b/Debug/LWFTP/lwftp.su
deleted file mode 100644
index c1c0f2d..0000000
--- a/Debug/LWFTP/lwftp.su
+++ /dev/null
@@ -1,22 +0,0 @@
-../LWFTP/lwftp.c:57:14:lwftp_pcb_close	24	static
-../LWFTP/lwftp.c:75:14:lwftp_send_next_data	32	static
-../LWFTP/lwftp.c:103:14:lwftp_data_recv	32	static
-../LWFTP/lwftp.c:133:14:lwftp_data_sent	32	static
-../LWFTP/lwftp.c:146:13:lwftp_data_err	24	static
-../LWFTP/lwftp.c:164:14:lwftp_data_connected	32	static
-../LWFTP/lwftp.c:180:14:lwftp_data_open	48	static
-../LWFTP/lwftp.c:216:14:lwftp_send_msg	32	static
-../LWFTP/lwftp.c:231:13:lwftp_data_close	16	static
-../LWFTP/lwftp.c:245:13:lwftp_control_close	16	static
-../LWFTP/lwftp.c:265:13:lwftp_control_process	40	static
-../LWFTP/lwftp.c:429:13:lwftp_start_RETR	24	static
-../LWFTP/lwftp.c:446:13:lwftp_start_STOR	24	static
-../LWFTP/lwftp.c:463:13:lwftp_send_QUIT	24	static
-../LWFTP/lwftp.c:479:14:lwftp_control_recv	32	static
-../LWFTP/lwftp.c:503:14:lwftp_control_sent	24	static
-../LWFTP/lwftp.c:512:13:lwftp_control_err	24	static
-../LWFTP/lwftp.c:534:14:lwftp_control_connected	32	static
-../LWFTP/lwftp.c:551:7:lwftp_connect	24	static
-../LWFTP/lwftp.c:593:7:lwftp_retrieve	24	static
-../LWFTP/lwftp.c:627:7:lwftp_store	24	static
-../LWFTP/lwftp.c:677:6:lwftp_close	16	static
diff --git a/Debug/LWFTP/lwftp_mod.d b/Debug/LWFTP/lwftp_mod.d
deleted file mode 100644
index 64751d2..0000000
--- a/Debug/LWFTP/lwftp_mod.d
+++ /dev/null
@@ -1 +0,0 @@
-LWFTP/lwftp_mod.o: ../LWFTP/lwftp_mod.c
diff --git a/Debug/LWFTP/lwftp_mod.o b/Debug/LWFTP/lwftp_mod.o
deleted file mode 100644
index 8b80a07..0000000
Binary files a/Debug/LWFTP/lwftp_mod.o and /dev/null differ
diff --git a/Debug/LWFTP/subdir.mk b/Debug/LWFTP/subdir.mk
deleted file mode 100644
index b18219d..0000000
--- a/Debug/LWFTP/subdir.mk
+++ /dev/null
@@ -1,30 +0,0 @@
-################################################################################
-# Automatically-generated file. Do not edit!
-# Toolchain: GNU Tools for STM32 (11.3.rel1)
-################################################################################
-
-# Add inputs and outputs from these tool invocations to the build variables 
-C_SRCS += \
-../LWFTP/lwftp.c \
-../LWFTP/lwftp_mod.c 
-
-OBJS += \
-./LWFTP/lwftp.o \
-./LWFTP/lwftp_mod.o 
-
-C_DEPS += \
-./LWFTP/lwftp.d \
-./LWFTP/lwftp_mod.d 
-
-
-# Each subdirectory must supply rules for building sources it contributes
-LWFTP/%.o LWFTP/%.su LWFTP/%.cyclo: ../LWFTP/%.c LWFTP/subdir.mk
-	arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DDEBUG -DDATA_IN_D2_SRAM -DUSE_HAL_DRIVER -DSTM32H723xx -c -I../Core/Inc -I../Drivers/STM32H7xx_HAL_Driver/Inc -I../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32H7xx/Include -I../Drivers/CMSIS/Include -I../LWIP/App -I../LWIP/Target -I../Middlewares/Third_Party/LwIP/src/include -I../Middlewares/Third_Party/LwIP/system -I../Drivers/BSP/Components/lan8742 -I../Middlewares/Third_Party/LwIP/src/include/netif/ppp -I../Middlewares/Third_Party/LwIP/src/include/lwip -I../Middlewares/Third_Party/LwIP/src/include/lwip/apps -I../Middlewares/Third_Party/LwIP/src/include/lwip/priv -I../Middlewares/Third_Party/LwIP/src/include/lwip/prot -I../Middlewares/Third_Party/LwIP/src/include/netif -I../Middlewares/Third_Party/LwIP/src/include/compat/posix -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/arpa -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/net -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/sys -I../Middlewares/Third_Party/LwIP/src/include/compat/stdc -I../Middlewares/Third_Party/LwIP/system/arch -I"C:/_NoSleep/STM32/lwip_test/LWFTP" -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
-
-clean: clean-LWFTP
-
-clean-LWFTP:
-	-$(RM) ./LWFTP/lwftp.cyclo ./LWFTP/lwftp.d ./LWFTP/lwftp.o ./LWFTP/lwftp.su ./LWFTP/lwftp_mod.cyclo ./LWFTP/lwftp_mod.d ./LWFTP/lwftp_mod.o ./LWFTP/lwftp_mod.su
-
-.PHONY: clean-LWFTP
-
diff --git a/Debug/LWFTPC/lwftpc.cyclo b/Debug/LWFTPC/lwftpc.cyclo
new file mode 100644
index 0000000..22b5942
--- /dev/null
+++ b/Debug/LWFTPC/lwftpc.cyclo
@@ -0,0 +1,8 @@
+../LWFTPC/lwftpc.c:12:7:lwftp_send	2
+../LWFTPC/lwftpc.c:27:7:lwftp_data_open	4
+../LWFTPC/lwftpc.c:65:7:lwftp_store	3
+../LWFTPC/lwftpc.c:88:7:lwftp_retrieve	2
+../LWFTPC/lwftpc.c:103:7:lwftp_list	2
+../LWFTPC/lwftpc.c:117:6:onDataReceived	1
+../LWFTPC/lwftpc.c:144:6:lwftp_data_thread	6
+../LWFTPC/lwftpc.c:167:6:lwftp_ctrl_thread	20
diff --git a/Debug/LWFTPC/lwftpc.d b/Debug/LWFTPC/lwftpc.d
new file mode 100644
index 0000000..9aa3fe3
--- /dev/null
+++ b/Debug/LWFTPC/lwftpc.d
@@ -0,0 +1,149 @@
+LWFTPC/lwftpc.o: ../LWFTPC/lwftpc.c ../LWFTPC/lwftpc.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/api.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \
+ ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \
+ ../Core/Inc/stm32h7xx_hal_conf.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h \
+ ../Drivers/CMSIS/Include/core_cm7.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \
+ ../Middlewares/Third_Party/LwIP/system/arch/cc.h \
+ ../Middlewares/Third_Party/LwIP/system/arch/cpu.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/netbuf.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/err.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/sys.h \
+ ../Middlewares/Third_Party/LwIP/system/arch/sys_arch.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h \
+ ../Core/Inc/FreeRTOSConfig.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/list.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h
+../LWFTPC/lwftpc.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/api.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h:
+../LWIP/Target/lwipopts.h:
+../Core/Inc/main.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h:
+../Core/Inc/stm32h7xx_hal_conf.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h:
+../Drivers/CMSIS/Include/core_cm7.h:
+../Drivers/CMSIS/Include/cmsis_version.h:
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+../Drivers/CMSIS/Include/mpu_armv7.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h:
+../Middlewares/Third_Party/LwIP/system/arch/cc.h:
+../Middlewares/Third_Party/LwIP/system/arch/cpu.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/netbuf.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/err.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/def.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/def.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/sys.h:
+../Middlewares/Third_Party/LwIP/system/arch/sys_arch.h:
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h:
+../Core/Inc/FreeRTOSConfig.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h:
+../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/task.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/list.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/task.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h:
diff --git a/Debug/LWFTPC/lwftpc.o b/Debug/LWFTPC/lwftpc.o
new file mode 100644
index 0000000..adad9e3
Binary files /dev/null and b/Debug/LWFTPC/lwftpc.o differ
diff --git a/Debug/LWFTPC/lwftpc.su b/Debug/LWFTPC/lwftpc.su
new file mode 100644
index 0000000..8cd0584
--- /dev/null
+++ b/Debug/LWFTPC/lwftpc.su
@@ -0,0 +1,8 @@
+../LWFTPC/lwftpc.c:12:7:lwftp_send	32	static
+../LWFTPC/lwftpc.c:27:7:lwftp_data_open	48	static
+../LWFTPC/lwftpc.c:65:7:lwftp_store	296	static
+../LWFTPC/lwftpc.c:88:7:lwftp_retrieve	280	static
+../LWFTPC/lwftpc.c:103:7:lwftp_list	24	static
+../LWFTPC/lwftpc.c:117:6:onDataReceived	16	static
+../LWFTPC/lwftpc.c:144:6:lwftp_data_thread	32	static
+../LWFTPC/lwftpc.c:167:6:lwftp_ctrl_thread	288	static
diff --git a/Debug/LWFTPC/subdir.mk b/Debug/LWFTPC/subdir.mk
new file mode 100644
index 0000000..2d25f4a
--- /dev/null
+++ b/Debug/LWFTPC/subdir.mk
@@ -0,0 +1,27 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+# Toolchain: GNU Tools for STM32 (11.3.rel1)
+################################################################################
+
+# Add inputs and outputs from these tool invocations to the build variables 
+C_SRCS += \
+../LWFTPC/lwftpc.c 
+
+OBJS += \
+./LWFTPC/lwftpc.o 
+
+C_DEPS += \
+./LWFTPC/lwftpc.d 
+
+
+# Each subdirectory must supply rules for building sources it contributes
+LWFTPC/%.o LWFTPC/%.su LWFTPC/%.cyclo: ../LWFTPC/%.c LWFTPC/subdir.mk
+	arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DDEBUG -DDATA_IN_D2_SRAM -DUSE_HAL_DRIVER -DSTM32H723xx -c -I../Core/Inc -I../FATFS/Target -I../FATFS/App -I../LWIP/App -I../LWIP/Target -I../Middlewares/Third_Party/LwIP/src/include -I../Middlewares/Third_Party/LwIP/system -I../Drivers/STM32H7xx_HAL_Driver/Inc -I../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F -I../Middlewares/Third_Party/FatFs/src -I../Drivers/BSP/Components/lan8742 -I../Middlewares/Third_Party/LwIP/src/include/netif/ppp -I../Drivers/CMSIS/Device/ST/STM32H7xx/Include -I../Middlewares/Third_Party/LwIP/src/include/lwip -I../Middlewares/Third_Party/LwIP/src/include/lwip/apps -I../Middlewares/Third_Party/LwIP/src/include/lwip/priv -I../Middlewares/Third_Party/LwIP/src/include/lwip/prot -I../Middlewares/Third_Party/LwIP/src/include/netif -I../Middlewares/Third_Party/LwIP/src/include/compat/posix -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/arpa -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/net -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/sys -I../Middlewares/Third_Party/LwIP/src/include/compat/stdc -I../Middlewares/Third_Party/LwIP/system/arch -I../Drivers/CMSIS/Include -I"C:/_NoSleep/STM32/TBD_TaxiBoard/LWFTPC" -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
+
+clean: clean-LWFTPC
+
+clean-LWFTPC:
+	-$(RM) ./LWFTPC/lwftpc.cyclo ./LWFTPC/lwftpc.d ./LWFTPC/lwftpc.o ./LWFTPC/lwftpc.su
+
+.PHONY: clean-LWFTPC
+
diff --git a/Debug/LWIP/App/lwip.cyclo b/Debug/LWIP/App/lwip.cyclo
index dada6f4..3cb44f7 100644
--- a/Debug/LWIP/App/lwip.cyclo
+++ b/Debug/LWIP/App/lwip.cyclo
@@ -1,4 +1,2 @@
-../LWIP/App/lwip.c:60:6:MX_LWIP_Init	1
-../LWIP/App/lwip.c:118:13:Ethernet_Link_Periodic_Handle	2
-../LWIP/App/lwip.c:144:6:MX_LWIP_Process	1
-../LWIP/App/lwip.c:166:13:ethernet_link_status_updated	1
+../LWIP/App/lwip.c:58:6:MX_LWIP_Init	1
+../LWIP/App/lwip.c:121:13:ethernet_link_status_updated	1
diff --git a/Debug/LWIP/App/lwip.d b/Debug/LWIP/App/lwip.d
index aec034a..24aaf8a 100644
--- a/Debug/LWIP/App/lwip.d
+++ b/Debug/LWIP/App/lwip.d
@@ -24,6 +24,7 @@ LWIP/App/lwip.o: ../LWIP/App/lwip.c ../LWIP/App/lwip.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
@@ -31,6 +32,14 @@ LWIP/App/lwip.o: ../LWIP/App/lwip.c ../LWIP/App/lwip.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \
  ../Middlewares/Third_Party/LwIP/system/arch/cc.h \
@@ -59,7 +68,27 @@ LWIP/App/lwip.o: ../LWIP/App/lwip.c ../LWIP/App/lwip.h \
  ../Middlewares/Third_Party/LwIP/src/include/netif/ethernet.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/dhcp.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/timeouts.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/sys.h \
+ ../Middlewares/Third_Party/LwIP/system/arch/sys_arch.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h \
+ ../Core/Inc/FreeRTOSConfig.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/list.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h \
  ../LWIP/Target/ethernetif.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/tcpip.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/init.h
 ../LWIP/App/lwip.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h:
@@ -88,6 +117,7 @@ LWIP/App/lwip.o: ../LWIP/App/lwip.c ../LWIP/App/lwip.h \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
@@ -95,6 +125,14 @@ LWIP/App/lwip.o: ../LWIP/App/lwip.c ../LWIP/App/lwip.h \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h:
 ../Middlewares/Third_Party/LwIP/system/arch/cc.h:
@@ -123,5 +161,25 @@ LWIP/App/lwip.o: ../LWIP/App/lwip.c ../LWIP/App/lwip.h \
 ../Middlewares/Third_Party/LwIP/src/include/netif/ethernet.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/dhcp.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/timeouts.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/sys.h:
+../Middlewares/Third_Party/LwIP/system/arch/sys_arch.h:
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h:
+../Core/Inc/FreeRTOSConfig.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h:
+../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/task.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/list.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/task.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h:
 ../LWIP/Target/ethernetif.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/tcpip.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/init.h:
diff --git a/Debug/LWIP/App/lwip.o b/Debug/LWIP/App/lwip.o
index 37c07e4..944edc0 100644
Binary files a/Debug/LWIP/App/lwip.o and b/Debug/LWIP/App/lwip.o differ
diff --git a/Debug/LWIP/App/lwip.su b/Debug/LWIP/App/lwip.su
index 5f55939..e90d9fb 100644
--- a/Debug/LWIP/App/lwip.su
+++ b/Debug/LWIP/App/lwip.su
@@ -1,4 +1,2 @@
-../LWIP/App/lwip.c:60:6:MX_LWIP_Init	24	static
-../LWIP/App/lwip.c:118:13:Ethernet_Link_Periodic_Handle	16	static
-../LWIP/App/lwip.c:144:6:MX_LWIP_Process	8	static
-../LWIP/App/lwip.c:166:13:ethernet_link_status_updated	16	static
+../LWIP/App/lwip.c:58:6:MX_LWIP_Init	64	static
+../LWIP/App/lwip.c:121:13:ethernet_link_status_updated	16	static
diff --git a/Debug/LWIP/App/subdir.mk b/Debug/LWIP/App/subdir.mk
index 6df08e7..1aa87a3 100644
--- a/Debug/LWIP/App/subdir.mk
+++ b/Debug/LWIP/App/subdir.mk
@@ -16,7 +16,7 @@ C_DEPS += \
 
 # Each subdirectory must supply rules for building sources it contributes
 LWIP/App/%.o LWIP/App/%.su LWIP/App/%.cyclo: ../LWIP/App/%.c LWIP/App/subdir.mk
-	arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DDEBUG -DDATA_IN_D2_SRAM -DUSE_HAL_DRIVER -DSTM32H723xx -c -I../Core/Inc -I../Drivers/STM32H7xx_HAL_Driver/Inc -I../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32H7xx/Include -I../Drivers/CMSIS/Include -I../LWIP/App -I../LWIP/Target -I../Middlewares/Third_Party/LwIP/src/include -I../Middlewares/Third_Party/LwIP/system -I../Drivers/BSP/Components/lan8742 -I../Middlewares/Third_Party/LwIP/src/include/netif/ppp -I../Middlewares/Third_Party/LwIP/src/include/lwip -I../Middlewares/Third_Party/LwIP/src/include/lwip/apps -I../Middlewares/Third_Party/LwIP/src/include/lwip/priv -I../Middlewares/Third_Party/LwIP/src/include/lwip/prot -I../Middlewares/Third_Party/LwIP/src/include/netif -I../Middlewares/Third_Party/LwIP/src/include/compat/posix -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/arpa -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/net -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/sys -I../Middlewares/Third_Party/LwIP/src/include/compat/stdc -I../Middlewares/Third_Party/LwIP/system/arch -I"C:/_NoSleep/STM32/lwip_test/LWFTP" -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
+	arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DDEBUG -DDATA_IN_D2_SRAM -DUSE_HAL_DRIVER -DSTM32H723xx -c -I../Core/Inc -I../FATFS/Target -I../FATFS/App -I../LWIP/App -I../LWIP/Target -I../Middlewares/Third_Party/LwIP/src/include -I../Middlewares/Third_Party/LwIP/system -I../Drivers/STM32H7xx_HAL_Driver/Inc -I../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F -I../Middlewares/Third_Party/FatFs/src -I../Drivers/BSP/Components/lan8742 -I../Middlewares/Third_Party/LwIP/src/include/netif/ppp -I../Drivers/CMSIS/Device/ST/STM32H7xx/Include -I../Middlewares/Third_Party/LwIP/src/include/lwip -I../Middlewares/Third_Party/LwIP/src/include/lwip/apps -I../Middlewares/Third_Party/LwIP/src/include/lwip/priv -I../Middlewares/Third_Party/LwIP/src/include/lwip/prot -I../Middlewares/Third_Party/LwIP/src/include/netif -I../Middlewares/Third_Party/LwIP/src/include/compat/posix -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/arpa -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/net -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/sys -I../Middlewares/Third_Party/LwIP/src/include/compat/stdc -I../Middlewares/Third_Party/LwIP/system/arch -I../Drivers/CMSIS/Include -I"C:/_NoSleep/STM32/TBD_TaxiBoard/LWFTPC" -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
 
 clean: clean-LWIP-2f-App
 
diff --git a/Debug/LWIP/Target/ethernetif.cyclo b/Debug/LWIP/Target/ethernetif.cyclo
index ff08edf..fcc55fd 100644
--- a/Debug/LWIP/Target/ethernetif.cyclo
+++ b/Debug/LWIP/Target/ethernetif.cyclo
@@ -1,18 +1,21 @@
-../LWIP/Target/ethernetif.c:159:13:low_level_init	2
-../LWIP/Target/ethernetif.c:259:14:low_level_output	5
-../LWIP/Target/ethernetif.c:306:22:low_level_input	2
-../LWIP/Target/ethernetif.c:327:6:ethernetif_input	4
-../LWIP/Target/ethernetif.c:377:7:ethernetif_init	2
-../LWIP/Target/ethernetif.c:428:6:pbuf_free_custom	2
-../LWIP/Target/ethernetif.c:450:7:sys_now	1
-../LWIP/Target/ethernetif.c:463:6:HAL_ETH_MspInit	2
-../LWIP/Target/ethernetif.c:520:6:HAL_ETH_MspDeInit	2
-../LWIP/Target/ethernetif.c:566:9:ETH_PHY_IO_Init	1
-../LWIP/Target/ethernetif.c:583:9:ETH_PHY_IO_DeInit	1
-../LWIP/Target/ethernetif.c:595:9:ETH_PHY_IO_ReadReg	2
-../LWIP/Target/ethernetif.c:612:9:ETH_PHY_IO_WriteReg	2
-../LWIP/Target/ethernetif.c:626:9:ETH_PHY_IO_GetTick	1
-../LWIP/Target/ethernetif.c:635:6:ethernet_link_check_state	10
-../LWIP/Target/ethernetif.c:692:6:HAL_ETH_RxAllocateCallback	2
-../LWIP/Target/ethernetif.c:714:6:HAL_ETH_RxLinkCallback	5
-../LWIP/Target/ethernetif.c:754:6:HAL_ETH_TxFreeCallback	1
+../LWIP/Target/ethernetif.c:159:6:HAL_ETH_RxCpltCallback	1
+../LWIP/Target/ethernetif.c:168:6:HAL_ETH_TxCpltCallback	1
+../LWIP/Target/ethernetif.c:177:6:HAL_ETH_ErrorCallback	2
+../LWIP/Target/ethernetif.c:199:13:low_level_init	7
+../LWIP/Target/ethernetif.c:367:14:low_level_output	7
+../LWIP/Target/ethernetif.c:425:22:low_level_input	2
+../LWIP/Target/ethernetif.c:446:13:ethernetif_input	5
+../LWIP/Target/ethernetif.c:503:7:ethernetif_init	2
+../LWIP/Target/ethernetif.c:554:6:pbuf_free_custom	2
+../LWIP/Target/ethernetif.c:577:7:sys_now	1
+../LWIP/Target/ethernetif.c:590:6:HAL_ETH_MspInit	2
+../LWIP/Target/ethernetif.c:647:6:HAL_ETH_MspDeInit	2
+../LWIP/Target/ethernetif.c:693:9:ETH_PHY_IO_Init	1
+../LWIP/Target/ethernetif.c:710:9:ETH_PHY_IO_DeInit	1
+../LWIP/Target/ethernetif.c:722:9:ETH_PHY_IO_ReadReg	2
+../LWIP/Target/ethernetif.c:739:9:ETH_PHY_IO_WriteReg	2
+../LWIP/Target/ethernetif.c:753:9:ETH_PHY_IO_GetTick	1
+../LWIP/Target/ethernetif.c:763:6:ethernet_link_thread	10
+../LWIP/Target/ethernetif.c:833:6:HAL_ETH_RxAllocateCallback	2
+../LWIP/Target/ethernetif.c:855:6:HAL_ETH_RxLinkCallback	5
+../LWIP/Target/ethernetif.c:895:6:HAL_ETH_TxFreeCallback	1
diff --git a/Debug/LWIP/Target/ethernetif.d b/Debug/LWIP/Target/ethernetif.d
index 113b115..d4d057e 100644
--- a/Debug/LWIP/Target/ethernetif.d
+++ b/Debug/LWIP/Target/ethernetif.d
@@ -22,6 +22,7 @@ LWIP/Target/ethernetif.o: ../LWIP/Target/ethernetif.c ../Core/Inc/main.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
@@ -29,20 +30,41 @@ LWIP/Target/ethernetif.o: ../LWIP/Target/ethernetif.c ../Core/Inc/main.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \
  ../LWIP/Target/lwipopts.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \
  ../Middlewares/Third_Party/LwIP/system/arch/cc.h \
  ../Middlewares/Third_Party/LwIP/system/arch/cpu.h \
- ../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h \
- ../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h \
- ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h \
- ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h \
- ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h \
- ../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/timeouts.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/err.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/sys.h \
+ ../Middlewares/Third_Party/LwIP/system/arch/sys_arch.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h \
+ ../Core/Inc/FreeRTOSConfig.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/list.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h \
  ../Middlewares/Third_Party/LwIP/src/include/netif/ethernet.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/netif.h \
@@ -51,6 +73,12 @@ LWIP/Target/ethernetif.o: ../LWIP/Target/ethernetif.c ../Core/Inc/main.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ethernet.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ieee.h \
  ../Middlewares/Third_Party/LwIP/src/include/netif/etharp.h \
@@ -59,7 +87,8 @@ LWIP/Target/ethernetif.o: ../LWIP/Target/ethernetif.c ../Core/Inc/main.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip4.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/etharp.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/ethip6.h \
- ../LWIP/Target/ethernetif.h ../Drivers/BSP/Components/lan8742/lan8742.h
+ ../LWIP/Target/ethernetif.h ../Drivers/BSP/Components/lan8742/lan8742.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/tcpip.h
 ../Core/Inc/main.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h:
 ../Core/Inc/stm32h7xx_hal_conf.h:
@@ -84,6 +113,7 @@ LWIP/Target/ethernetif.o: ../LWIP/Target/ethernetif.c ../Core/Inc/main.h \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
@@ -91,20 +121,41 @@ LWIP/Target/ethernetif.o: ../LWIP/Target/ethernetif.c ../Core/Inc/main.h \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h:
 ../LWIP/Target/lwipopts.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h:
 ../Middlewares/Third_Party/LwIP/system/arch/cc.h:
 ../Middlewares/Third_Party/LwIP/system/arch/cpu.h:
-../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h:
-../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h:
-../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h:
-../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h:
-../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h:
-../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/timeouts.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/err.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/sys.h:
+../Middlewares/Third_Party/LwIP/system/arch/sys_arch.h:
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h:
+../Core/Inc/FreeRTOSConfig.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h:
+../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/task.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/list.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/task.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h:
 ../Middlewares/Third_Party/LwIP/src/include/netif/ethernet.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/netif.h:
@@ -113,6 +164,12 @@ LWIP/Target/ethernetif.o: ../LWIP/Target/ethernetif.c ../Core/Inc/main.h \
 ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ethernet.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ieee.h:
 ../Middlewares/Third_Party/LwIP/src/include/netif/etharp.h:
@@ -123,3 +180,4 @@ LWIP/Target/ethernetif.o: ../LWIP/Target/ethernetif.c ../Core/Inc/main.h \
 ../Middlewares/Third_Party/LwIP/src/include/lwip/ethip6.h:
 ../LWIP/Target/ethernetif.h:
 ../Drivers/BSP/Components/lan8742/lan8742.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/tcpip.h:
diff --git a/Debug/LWIP/Target/ethernetif.o b/Debug/LWIP/Target/ethernetif.o
index 1e91acf..8b9776f 100644
Binary files a/Debug/LWIP/Target/ethernetif.o and b/Debug/LWIP/Target/ethernetif.o differ
diff --git a/Debug/LWIP/Target/ethernetif.su b/Debug/LWIP/Target/ethernetif.su
index 9df8f41..468e3a3 100644
--- a/Debug/LWIP/Target/ethernetif.su
+++ b/Debug/LWIP/Target/ethernetif.su
@@ -1,18 +1,21 @@
-../LWIP/Target/ethernetif.c:159:13:low_level_init	24	static
-../LWIP/Target/ethernetif.c:259:14:low_level_output	80	static
-../LWIP/Target/ethernetif.c:306:22:low_level_input	24	static
-../LWIP/Target/ethernetif.c:327:6:ethernetif_input	24	static
-../LWIP/Target/ethernetif.c:377:7:ethernetif_init	16	static
-../LWIP/Target/ethernetif.c:428:6:pbuf_free_custom	24	static
-../LWIP/Target/ethernetif.c:450:7:sys_now	8	static
-../LWIP/Target/ethernetif.c:463:6:HAL_ETH_MspInit	64	static
-../LWIP/Target/ethernetif.c:520:6:HAL_ETH_MspDeInit	16	static
-../LWIP/Target/ethernetif.c:566:9:ETH_PHY_IO_Init	8	static
-../LWIP/Target/ethernetif.c:583:9:ETH_PHY_IO_DeInit	4	static
-../LWIP/Target/ethernetif.c:595:9:ETH_PHY_IO_ReadReg	24	static
-../LWIP/Target/ethernetif.c:612:9:ETH_PHY_IO_WriteReg	24	static
-../LWIP/Target/ethernetif.c:626:9:ETH_PHY_IO_GetTick	8	static
-../LWIP/Target/ethernetif.c:635:6:ethernet_link_check_state	136	static
-../LWIP/Target/ethernetif.c:692:6:HAL_ETH_RxAllocateCallback	32	static
-../LWIP/Target/ethernetif.c:714:6:HAL_ETH_RxLinkCallback	56	static,ignoring_inline_asm
-../LWIP/Target/ethernetif.c:754:6:HAL_ETH_TxFreeCallback	16	static
+../LWIP/Target/ethernetif.c:159:6:HAL_ETH_RxCpltCallback	16	static
+../LWIP/Target/ethernetif.c:168:6:HAL_ETH_TxCpltCallback	16	static
+../LWIP/Target/ethernetif.c:177:6:HAL_ETH_ErrorCallback	16	static
+../LWIP/Target/ethernetif.c:199:13:low_level_init	192	static
+../LWIP/Target/ethernetif.c:367:14:low_level_output	80	static
+../LWIP/Target/ethernetif.c:425:22:low_level_input	24	static
+../LWIP/Target/ethernetif.c:446:13:ethernetif_input	24	static
+../LWIP/Target/ethernetif.c:503:7:ethernetif_init	16	static
+../LWIP/Target/ethernetif.c:554:6:pbuf_free_custom	24	static
+../LWIP/Target/ethernetif.c:577:7:sys_now	8	static
+../LWIP/Target/ethernetif.c:590:6:HAL_ETH_MspInit	64	static
+../LWIP/Target/ethernetif.c:647:6:HAL_ETH_MspDeInit	16	static
+../LWIP/Target/ethernetif.c:693:9:ETH_PHY_IO_Init	8	static
+../LWIP/Target/ethernetif.c:710:9:ETH_PHY_IO_DeInit	4	static
+../LWIP/Target/ethernetif.c:722:9:ETH_PHY_IO_ReadReg	24	static
+../LWIP/Target/ethernetif.c:739:9:ETH_PHY_IO_WriteReg	24	static
+../LWIP/Target/ethernetif.c:753:9:ETH_PHY_IO_GetTick	8	static
+../LWIP/Target/ethernetif.c:763:6:ethernet_link_thread	136	static
+../LWIP/Target/ethernetif.c:833:6:HAL_ETH_RxAllocateCallback	32	static
+../LWIP/Target/ethernetif.c:855:6:HAL_ETH_RxLinkCallback	56	static,ignoring_inline_asm
+../LWIP/Target/ethernetif.c:895:6:HAL_ETH_TxFreeCallback	16	static
diff --git a/Debug/LWIP/Target/subdir.mk b/Debug/LWIP/Target/subdir.mk
index 778e9f6..580a048 100644
--- a/Debug/LWIP/Target/subdir.mk
+++ b/Debug/LWIP/Target/subdir.mk
@@ -16,7 +16,7 @@ C_DEPS += \
 
 # Each subdirectory must supply rules for building sources it contributes
 LWIP/Target/%.o LWIP/Target/%.su LWIP/Target/%.cyclo: ../LWIP/Target/%.c LWIP/Target/subdir.mk
-	arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DDEBUG -DDATA_IN_D2_SRAM -DUSE_HAL_DRIVER -DSTM32H723xx -c -I../Core/Inc -I../Drivers/STM32H7xx_HAL_Driver/Inc -I../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32H7xx/Include -I../Drivers/CMSIS/Include -I../LWIP/App -I../LWIP/Target -I../Middlewares/Third_Party/LwIP/src/include -I../Middlewares/Third_Party/LwIP/system -I../Drivers/BSP/Components/lan8742 -I../Middlewares/Third_Party/LwIP/src/include/netif/ppp -I../Middlewares/Third_Party/LwIP/src/include/lwip -I../Middlewares/Third_Party/LwIP/src/include/lwip/apps -I../Middlewares/Third_Party/LwIP/src/include/lwip/priv -I../Middlewares/Third_Party/LwIP/src/include/lwip/prot -I../Middlewares/Third_Party/LwIP/src/include/netif -I../Middlewares/Third_Party/LwIP/src/include/compat/posix -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/arpa -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/net -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/sys -I../Middlewares/Third_Party/LwIP/src/include/compat/stdc -I../Middlewares/Third_Party/LwIP/system/arch -I"C:/_NoSleep/STM32/lwip_test/LWFTP" -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
+	arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DDEBUG -DDATA_IN_D2_SRAM -DUSE_HAL_DRIVER -DSTM32H723xx -c -I../Core/Inc -I../FATFS/Target -I../FATFS/App -I../LWIP/App -I../LWIP/Target -I../Middlewares/Third_Party/LwIP/src/include -I../Middlewares/Third_Party/LwIP/system -I../Drivers/STM32H7xx_HAL_Driver/Inc -I../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F -I../Middlewares/Third_Party/FatFs/src -I../Drivers/BSP/Components/lan8742 -I../Middlewares/Third_Party/LwIP/src/include/netif/ppp -I../Drivers/CMSIS/Device/ST/STM32H7xx/Include -I../Middlewares/Third_Party/LwIP/src/include/lwip -I../Middlewares/Third_Party/LwIP/src/include/lwip/apps -I../Middlewares/Third_Party/LwIP/src/include/lwip/priv -I../Middlewares/Third_Party/LwIP/src/include/lwip/prot -I../Middlewares/Third_Party/LwIP/src/include/netif -I../Middlewares/Third_Party/LwIP/src/include/compat/posix -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/arpa -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/net -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/sys -I../Middlewares/Third_Party/LwIP/src/include/compat/stdc -I../Middlewares/Third_Party/LwIP/system/arch -I../Drivers/CMSIS/Include -I"C:/_NoSleep/STM32/TBD_TaxiBoard/LWFTPC" -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
 
 clean: clean-LWIP-2f-Target
 
diff --git a/Debug/Middlewares/Third_Party/FatFs/src/diskio.cyclo b/Debug/Middlewares/Third_Party/FatFs/src/diskio.cyclo
new file mode 100644
index 0000000..3f72106
--- /dev/null
+++ b/Debug/Middlewares/Third_Party/FatFs/src/diskio.cyclo
@@ -0,0 +1,6 @@
+../Middlewares/Third_Party/FatFs/src/diskio.c:36:9:disk_status	1
+../Middlewares/Third_Party/FatFs/src/diskio.c:51:9:disk_initialize	2
+../Middlewares/Third_Party/FatFs/src/diskio.c:73:9:disk_read	1
+../Middlewares/Third_Party/FatFs/src/diskio.c:95:9:disk_write	1
+../Middlewares/Third_Party/FatFs/src/diskio.c:117:9:disk_ioctl	1
+../Middlewares/Third_Party/FatFs/src/diskio.c:135:14:get_fattime	1
diff --git a/Debug/Middlewares/Third_Party/FatFs/src/diskio.d b/Debug/Middlewares/Third_Party/FatFs/src/diskio.d
new file mode 100644
index 0000000..9ce71d3
--- /dev/null
+++ b/Debug/Middlewares/Third_Party/FatFs/src/diskio.d
@@ -0,0 +1,127 @@
+Middlewares/Third_Party/FatFs/src/diskio.o: \
+ ../Middlewares/Third_Party/FatFs/src/diskio.c \
+ ../Middlewares/Third_Party/FatFs/src/diskio.h \
+ ../Middlewares/Third_Party/FatFs/src/integer.h \
+ ../Middlewares/Third_Party/FatFs/src/ff_gen_drv.h \
+ ../Middlewares/Third_Party/FatFs/src/ff.h ../FATFS/Target/ffconf.h \
+ ../Core/Inc/main.h ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \
+ ../Core/Inc/stm32h7xx_hal_conf.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h \
+ ../Drivers/CMSIS/Include/core_cm7.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \
+ ../FATFS/Target/bsp_driver_sd.h ../FATFS/Target/fatfs_platform.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h \
+ ../Core/Inc/FreeRTOSConfig.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/list.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h
+../Middlewares/Third_Party/FatFs/src/diskio.h:
+../Middlewares/Third_Party/FatFs/src/integer.h:
+../Middlewares/Third_Party/FatFs/src/ff_gen_drv.h:
+../Middlewares/Third_Party/FatFs/src/ff.h:
+../FATFS/Target/ffconf.h:
+../Core/Inc/main.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h:
+../Core/Inc/stm32h7xx_hal_conf.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h:
+../Drivers/CMSIS/Include/core_cm7.h:
+../Drivers/CMSIS/Include/cmsis_version.h:
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+../Drivers/CMSIS/Include/mpu_armv7.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
+../FATFS/Target/bsp_driver_sd.h:
+../FATFS/Target/fatfs_platform.h:
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h:
+../Core/Inc/FreeRTOSConfig.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h:
+../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/task.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/list.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/task.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h:
diff --git a/Debug/Middlewares/Third_Party/FatFs/src/diskio.o b/Debug/Middlewares/Third_Party/FatFs/src/diskio.o
new file mode 100644
index 0000000..abe04e9
Binary files /dev/null and b/Debug/Middlewares/Third_Party/FatFs/src/diskio.o differ
diff --git a/Debug/Middlewares/Third_Party/FatFs/src/diskio.su b/Debug/Middlewares/Third_Party/FatFs/src/diskio.su
new file mode 100644
index 0000000..25fd2db
--- /dev/null
+++ b/Debug/Middlewares/Third_Party/FatFs/src/diskio.su
@@ -0,0 +1,6 @@
+../Middlewares/Third_Party/FatFs/src/diskio.c:36:9:disk_status	24	static
+../Middlewares/Third_Party/FatFs/src/diskio.c:51:9:disk_initialize	24	static
+../Middlewares/Third_Party/FatFs/src/diskio.c:73:9:disk_read	40	static
+../Middlewares/Third_Party/FatFs/src/diskio.c:95:9:disk_write	40	static
+../Middlewares/Third_Party/FatFs/src/diskio.c:117:9:disk_ioctl	24	static
+../Middlewares/Third_Party/FatFs/src/diskio.c:135:14:get_fattime	4	static
diff --git a/Debug/Middlewares/Third_Party/FatFs/src/ff.cyclo b/Debug/Middlewares/Third_Party/FatFs/src/ff.cyclo
new file mode 100644
index 0000000..ce991a7
--- /dev/null
+++ b/Debug/Middlewares/Third_Party/FatFs/src/ff.cyclo
@@ -0,0 +1,83 @@
+../Middlewares/Third_Party/FatFs/src/ff.c:613:6:ld_word	1
+../Middlewares/Third_Party/FatFs/src/ff.c:623:7:ld_dword	1
+../Middlewares/Third_Party/FatFs/src/ff.c:636:7:ld_qword	1
+../Middlewares/Third_Party/FatFs/src/ff.c:654:6:st_word	1
+../Middlewares/Third_Party/FatFs/src/ff.c:661:6:st_dword	1
+../Middlewares/Third_Party/FatFs/src/ff.c:671:6:st_qword	1
+../Middlewares/Third_Party/FatFs/src/ff.c:693:6:mem_cpy	3
+../Middlewares/Third_Party/FatFs/src/ff.c:706:6:mem_set	2
+../Middlewares/Third_Party/FatFs/src/ff.c:716:5:mem_cmp	3
+../Middlewares/Third_Party/FatFs/src/ff.c:729:5:chk_chr	3
+../Middlewares/Third_Party/FatFs/src/ff.c:742:5:lock_fs	3
+../Middlewares/Third_Party/FatFs/src/ff.c:751:6:unlock_fs	5
+../Middlewares/Third_Party/FatFs/src/ff.c:771:9:chk_lock	11
+../Middlewares/Third_Party/FatFs/src/ff.c:798:5:enq_lock	3
+../Middlewares/Third_Party/FatFs/src/ff.c:808:6:inc_lock	12
+../Middlewares/Third_Party/FatFs/src/ff.c:840:9:dec_lock	5
+../Middlewares/Third_Party/FatFs/src/ff.c:863:6:clear_lock	3
+../Middlewares/Third_Party/FatFs/src/ff.c:883:9:sync_window	5
+../Middlewares/Third_Party/FatFs/src/ff.c:912:9:move_window	4
+../Middlewares/Third_Party/FatFs/src/ff.c:944:9:sync_fs	5
+../Middlewares/Third_Party/FatFs/src/ff.c:983:7:clust2sect	2
+../Middlewares/Third_Party/FatFs/src/ff.c:1001:7:get_fat	21
+../Middlewares/Third_Party/FatFs/src/ff.c:1081:9:put_fat	14
+../Middlewares/Third_Party/FatFs/src/ff.c:1146:7:find_bitmap	9
+../Middlewares/Third_Party/FatFs/src/ff.c:1187:9:change_bitmap	6
+../Middlewares/Third_Party/FatFs/src/ff.c:1223:9:fill_first_frag	4
+../Middlewares/Third_Party/FatFs/src/ff.c:1246:9:fill_last_frag	4
+../Middlewares/Third_Party/FatFs/src/ff.c:1271:9:remove_chain	22
+../Middlewares/Third_Party/FatFs/src/ff.c:1351:7:create_chain	31
+../Middlewares/Third_Party/FatFs/src/ff.c:1440:7:clmt_clust	3
+../Middlewares/Third_Party/FatFs/src/ff.c:1470:9:dir_sdi	13
+../Middlewares/Third_Party/FatFs/src/ff.c:1519:9:dir_next	18
+../Middlewares/Third_Party/FatFs/src/ff.c:1589:9:dir_alloc	10
+../Middlewares/Third_Party/FatFs/src/ff.c:1632:7:ld_clust	2
+../Middlewares/Third_Party/FatFs/src/ff.c:1650:6:st_clust	2
+../Middlewares/Third_Party/FatFs/src/ff.c:1677:5:cmp_lfn	10
+../Middlewares/Third_Party/FatFs/src/ff.c:1713:5:pick_lfn	8
+../Middlewares/Third_Party/FatFs/src/ff.c:1751:6:put_lfn	6
+../Middlewares/Third_Party/FatFs/src/ff.c:1789:6:gen_numname	11
+../Middlewares/Third_Party/FatFs/src/ff.c:1848:6:sum_sfn	2
+../Middlewares/Third_Party/FatFs/src/ff.c:1871:6:xdir_sum	3
+../Middlewares/Third_Party/FatFs/src/ff.c:1893:6:xname_sum	2
+../Middlewares/Third_Party/FatFs/src/ff.c:1912:7:xsum32	1
+../Middlewares/Third_Party/FatFs/src/ff.c:1929:6:get_xdir_info	7
+../Middlewares/Third_Party/FatFs/src/ff.c:1978:9:load_xdir	16
+../Middlewares/Third_Party/FatFs/src/ff.c:2028:9:load_obj_dir	2
+../Middlewares/Third_Party/FatFs/src/ff.c:2056:9:store_xdir	6
+../Middlewares/Third_Party/FatFs/src/ff.c:2089:6:create_xdir	5
+../Middlewares/Third_Party/FatFs/src/ff.c:2131:9:dir_read	19
+../Middlewares/Third_Party/FatFs/src/ff.c:2210:9:dir_find	26
+../Middlewares/Third_Party/FatFs/src/ff.c:2292:9:dir_register	25
+../Middlewares/Third_Party/FatFs/src/ff.c:2396:9:dir_remove	8
+../Middlewares/Third_Party/FatFs/src/ff.c:2444:6:get_fileinfo	19
+../Middlewares/Third_Party/FatFs/src/ff.c:2618:9:create_name	44
+../Middlewares/Third_Party/FatFs/src/ff.c:2813:9:follow_path	11
+../Middlewares/Third_Party/FatFs/src/ff.c:2904:5:get_ldnumber	8
+../Middlewares/Third_Party/FatFs/src/ff.c:2965:6:check_fs	9
+../Middlewares/Third_Party/FatFs/src/ff.c:2993:9:find_volume	65
+../Middlewares/Third_Party/FatFs/src/ff.c:3216:9:validate	8
+../Middlewares/Third_Party/FatFs/src/ff.c:3260:9:f_mount	8
+../Middlewares/Third_Party/FatFs/src/ff.c:3308:9:f_open	38
+../Middlewares/Third_Party/FatFs/src/ff.c:3511:9:f_read	23
+../Middlewares/Third_Party/FatFs/src/ff.c:3611:9:f_write	28
+../Middlewares/Third_Party/FatFs/src/ff.c:3732:9:f_sync	11
+../Middlewares/Third_Party/FatFs/src/ff.c:3813:9:f_close	4
+../Middlewares/Third_Party/FatFs/src/ff.c:4001:9:f_lseek	48
+../Middlewares/Third_Party/FatFs/src/ff.c:4162:9:f_opendir	13
+../Middlewares/Third_Party/FatFs/src/ff.c:4232:9:f_closedir	4
+../Middlewares/Third_Party/FatFs/src/ff.c:4265:9:f_readdir	6
+../Middlewares/Third_Party/FatFs/src/ff.c:4353:9:f_stat	5
+../Middlewares/Third_Party/FatFs/src/ff.c:4388:9:f_getfree	21
+../Middlewares/Third_Party/FatFs/src/ff.c:4475:9:f_truncate	14
+../Middlewares/Third_Party/FatFs/src/ff.c:4525:9:f_unlink	17
+../Middlewares/Third_Party/FatFs/src/ff.c:4620:9:f_mkdir	18
+../Middlewares/Third_Party/FatFs/src/ff.c:4717:9:f_rename	24
+../Middlewares/Third_Party/FatFs/src/ff.c:5301:9:f_mkfs	132
+../Middlewares/Third_Party/FatFs/src/ff.c:5830:8:f_gets	6
+../Middlewares/Third_Party/FatFs/src/ff.c:5917:6:putc_bfd	5
+../Middlewares/Third_Party/FatFs/src/ff.c:5973:5:putc_flush	4
+../Middlewares/Third_Party/FatFs/src/ff.c:5987:6:putc_init	1
+../Middlewares/Third_Party/FatFs/src/ff.c:5998:5:f_putc	1
+../Middlewares/Third_Party/FatFs/src/ff.c:6018:5:f_puts	2
+../Middlewares/Third_Party/FatFs/src/ff.c:6038:5:f_printf	37
diff --git a/Debug/Middlewares/Third_Party/FatFs/src/ff.d b/Debug/Middlewares/Third_Party/FatFs/src/ff.d
new file mode 100644
index 0000000..dd3ded9
--- /dev/null
+++ b/Debug/Middlewares/Third_Party/FatFs/src/ff.d
@@ -0,0 +1,125 @@
+Middlewares/Third_Party/FatFs/src/ff.o: \
+ ../Middlewares/Third_Party/FatFs/src/ff.c \
+ ../Middlewares/Third_Party/FatFs/src/ff.h \
+ ../Middlewares/Third_Party/FatFs/src/integer.h ../FATFS/Target/ffconf.h \
+ ../Core/Inc/main.h ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \
+ ../Core/Inc/stm32h7xx_hal_conf.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h \
+ ../Drivers/CMSIS/Include/core_cm7.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \
+ ../FATFS/Target/bsp_driver_sd.h ../FATFS/Target/fatfs_platform.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h \
+ ../Core/Inc/FreeRTOSConfig.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/list.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h \
+ ../Middlewares/Third_Party/FatFs/src/diskio.h
+../Middlewares/Third_Party/FatFs/src/ff.h:
+../Middlewares/Third_Party/FatFs/src/integer.h:
+../FATFS/Target/ffconf.h:
+../Core/Inc/main.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h:
+../Core/Inc/stm32h7xx_hal_conf.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h:
+../Drivers/CMSIS/Include/core_cm7.h:
+../Drivers/CMSIS/Include/cmsis_version.h:
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+../Drivers/CMSIS/Include/mpu_armv7.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
+../FATFS/Target/bsp_driver_sd.h:
+../FATFS/Target/fatfs_platform.h:
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h:
+../Core/Inc/FreeRTOSConfig.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h:
+../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/task.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/list.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/task.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h:
+../Middlewares/Third_Party/FatFs/src/diskio.h:
diff --git a/Debug/Middlewares/Third_Party/FatFs/src/ff.o b/Debug/Middlewares/Third_Party/FatFs/src/ff.o
new file mode 100644
index 0000000..f7fa02f
Binary files /dev/null and b/Debug/Middlewares/Third_Party/FatFs/src/ff.o differ
diff --git a/Debug/Middlewares/Third_Party/FatFs/src/ff.su b/Debug/Middlewares/Third_Party/FatFs/src/ff.su
new file mode 100644
index 0000000..ac4850e
--- /dev/null
+++ b/Debug/Middlewares/Third_Party/FatFs/src/ff.su
@@ -0,0 +1,83 @@
+../Middlewares/Third_Party/FatFs/src/ff.c:613:6:ld_word	24	static
+../Middlewares/Third_Party/FatFs/src/ff.c:623:7:ld_dword	24	static
+../Middlewares/Third_Party/FatFs/src/ff.c:636:7:ld_qword	144	static
+../Middlewares/Third_Party/FatFs/src/ff.c:654:6:st_word	16	static
+../Middlewares/Third_Party/FatFs/src/ff.c:661:6:st_dword	16	static
+../Middlewares/Third_Party/FatFs/src/ff.c:671:6:st_qword	24	static
+../Middlewares/Third_Party/FatFs/src/ff.c:693:6:mem_cpy	32	static
+../Middlewares/Third_Party/FatFs/src/ff.c:706:6:mem_set	32	static
+../Middlewares/Third_Party/FatFs/src/ff.c:716:5:mem_cmp	40	static
+../Middlewares/Third_Party/FatFs/src/ff.c:729:5:chk_chr	16	static
+../Middlewares/Third_Party/FatFs/src/ff.c:742:5:lock_fs	16	static
+../Middlewares/Third_Party/FatFs/src/ff.c:751:6:unlock_fs	16	static
+../Middlewares/Third_Party/FatFs/src/ff.c:771:9:chk_lock	24	static
+../Middlewares/Third_Party/FatFs/src/ff.c:798:5:enq_lock	16	static
+../Middlewares/Third_Party/FatFs/src/ff.c:808:6:inc_lock	24	static
+../Middlewares/Third_Party/FatFs/src/ff.c:840:9:dec_lock	24	static
+../Middlewares/Third_Party/FatFs/src/ff.c:863:6:clear_lock	24	static
+../Middlewares/Third_Party/FatFs/src/ff.c:883:9:sync_window	32	static
+../Middlewares/Third_Party/FatFs/src/ff.c:912:9:move_window	24	static
+../Middlewares/Third_Party/FatFs/src/ff.c:944:9:sync_fs	24	static
+../Middlewares/Third_Party/FatFs/src/ff.c:983:7:clust2sect	16	static
+../Middlewares/Third_Party/FatFs/src/ff.c:1001:7:get_fat	56	static
+../Middlewares/Third_Party/FatFs/src/ff.c:1081:9:put_fat	48	static
+../Middlewares/Third_Party/FatFs/src/ff.c:1146:7:find_bitmap	48	static
+../Middlewares/Third_Party/FatFs/src/ff.c:1187:9:change_bitmap	40	static
+../Middlewares/Third_Party/FatFs/src/ff.c:1223:9:fill_first_frag	32	static
+../Middlewares/Third_Party/FatFs/src/ff.c:1246:9:fill_last_frag	32	static
+../Middlewares/Third_Party/FatFs/src/ff.c:1271:9:remove_chain	48	static
+../Middlewares/Third_Party/FatFs/src/ff.c:1351:7:create_chain	40	static
+../Middlewares/Third_Party/FatFs/src/ff.c:1440:7:clmt_clust	56	static
+../Middlewares/Third_Party/FatFs/src/ff.c:1470:9:dir_sdi	32	static
+../Middlewares/Third_Party/FatFs/src/ff.c:1519:9:dir_next	32	static
+../Middlewares/Third_Party/FatFs/src/ff.c:1589:9:dir_alloc	32	static
+../Middlewares/Third_Party/FatFs/src/ff.c:1632:7:ld_clust	24	static
+../Middlewares/Third_Party/FatFs/src/ff.c:1650:6:st_clust	24	static
+../Middlewares/Third_Party/FatFs/src/ff.c:1677:5:cmp_lfn	40	static
+../Middlewares/Third_Party/FatFs/src/ff.c:1713:5:pick_lfn	32	static
+../Middlewares/Third_Party/FatFs/src/ff.c:1751:6:put_lfn	40	static
+../Middlewares/Third_Party/FatFs/src/ff.c:1789:6:gen_numname	56	static
+../Middlewares/Third_Party/FatFs/src/ff.c:1848:6:sum_sfn	24	static
+../Middlewares/Third_Party/FatFs/src/ff.c:1871:6:xdir_sum	32	static
+../Middlewares/Third_Party/FatFs/src/ff.c:1893:6:xname_sum	24	static
+../Middlewares/Third_Party/FatFs/src/ff.c:1912:7:xsum32	16	static
+../Middlewares/Third_Party/FatFs/src/ff.c:1929:6:get_xdir_info	32	static
+../Middlewares/Third_Party/FatFs/src/ff.c:1978:9:load_xdir	40	static
+../Middlewares/Third_Party/FatFs/src/ff.c:2028:9:load_obj_dir	32	static
+../Middlewares/Third_Party/FatFs/src/ff.c:2056:9:store_xdir	40	static
+../Middlewares/Third_Party/FatFs/src/ff.c:2089:6:create_xdir	32	static
+../Middlewares/Third_Party/FatFs/src/ff.c:2131:9:dir_read	32	static
+../Middlewares/Third_Party/FatFs/src/ff.c:2210:9:dir_find	48	static
+../Middlewares/Third_Party/FatFs/src/ff.c:2292:9:dir_register	152	static
+../Middlewares/Third_Party/FatFs/src/ff.c:2396:9:dir_remove	32	static
+../Middlewares/Third_Party/FatFs/src/ff.c:2444:6:get_fileinfo	48	static
+../Middlewares/Third_Party/FatFs/src/ff.c:2618:9:create_name	48	static
+../Middlewares/Third_Party/FatFs/src/ff.c:2813:9:follow_path	32	static
+../Middlewares/Third_Party/FatFs/src/ff.c:2904:5:get_ldnumber	32	static
+../Middlewares/Third_Party/FatFs/src/ff.c:2965:6:check_fs	16	static
+../Middlewares/Third_Party/FatFs/src/ff.c:2993:9:find_volume	144	static
+../Middlewares/Third_Party/FatFs/src/ff.c:3216:9:validate	24	static
+../Middlewares/Third_Party/FatFs/src/ff.c:3260:9:f_mount	40	static
+../Middlewares/Third_Party/FatFs/src/ff.c:3308:9:f_open	1312	static
+../Middlewares/Third_Party/FatFs/src/ff.c:3511:9:f_read	128	static
+../Middlewares/Third_Party/FatFs/src/ff.c:3611:9:f_write	104	static
+../Middlewares/Third_Party/FatFs/src/ff.c:3732:9:f_sync	1232	static
+../Middlewares/Third_Party/FatFs/src/ff.c:3813:9:f_close	24	static
+../Middlewares/Third_Party/FatFs/src/ff.c:4001:9:f_lseek	264	static
+../Middlewares/Third_Party/FatFs/src/ff.c:4162:9:f_opendir	1152	static
+../Middlewares/Third_Party/FatFs/src/ff.c:4232:9:f_closedir	24	static
+../Middlewares/Third_Party/FatFs/src/ff.c:4265:9:f_readdir	1144	static
+../Middlewares/Third_Party/FatFs/src/ff.c:4353:9:f_stat	1224	static
+../Middlewares/Third_Party/FatFs/src/ff.c:4388:9:f_getfree	112	static
+../Middlewares/Third_Party/FatFs/src/ff.c:4475:9:f_truncate	32	static
+../Middlewares/Third_Party/FatFs/src/ff.c:4525:9:f_unlink	1360	static
+../Middlewares/Third_Party/FatFs/src/ff.c:4620:9:f_mkdir	1264	static
+../Middlewares/Third_Party/FatFs/src/ff.c:4717:9:f_rename	1392	static
+../Middlewares/Third_Party/FatFs/src/ff.c:5301:9:f_mkfs	176	static
+../Middlewares/Third_Party/FatFs/src/ff.c:5830:8:f_gets	40	static
+../Middlewares/Third_Party/FatFs/src/ff.c:5917:6:putc_bfd	24	static
+../Middlewares/Third_Party/FatFs/src/ff.c:5973:5:putc_flush	24	static
+../Middlewares/Third_Party/FatFs/src/ff.c:5987:6:putc_init	16	static
+../Middlewares/Third_Party/FatFs/src/ff.c:5998:5:f_putc	96	static
+../Middlewares/Third_Party/FatFs/src/ff.c:6018:5:f_puts	96	static
+../Middlewares/Third_Party/FatFs/src/ff.c:6038:5:f_printf	164	static
diff --git a/Debug/Middlewares/Third_Party/FatFs/src/ff_gen_drv.cyclo b/Debug/Middlewares/Third_Party/FatFs/src/ff_gen_drv.cyclo
new file mode 100644
index 0000000..6eb9535
--- /dev/null
+++ b/Debug/Middlewares/Third_Party/FatFs/src/ff_gen_drv.cyclo
@@ -0,0 +1,5 @@
+../Middlewares/Third_Party/FatFs/src/ff_gen_drv.c:39:9:FATFS_LinkDriverEx	2
+../Middlewares/Third_Party/FatFs/src/ff_gen_drv.c:68:9:FATFS_LinkDriver	1
+../Middlewares/Third_Party/FatFs/src/ff_gen_drv.c:80:9:FATFS_UnLinkDriverEx	3
+../Middlewares/Third_Party/FatFs/src/ff_gen_drv.c:106:9:FATFS_UnLinkDriver	1
+../Middlewares/Third_Party/FatFs/src/ff_gen_drv.c:116:9:FATFS_GetAttachedDriversNbr	1
diff --git a/Debug/Middlewares/Third_Party/FatFs/src/ff_gen_drv.d b/Debug/Middlewares/Third_Party/FatFs/src/ff_gen_drv.d
new file mode 100644
index 0000000..222182a
--- /dev/null
+++ b/Debug/Middlewares/Third_Party/FatFs/src/ff_gen_drv.d
@@ -0,0 +1,127 @@
+Middlewares/Third_Party/FatFs/src/ff_gen_drv.o: \
+ ../Middlewares/Third_Party/FatFs/src/ff_gen_drv.c \
+ ../Middlewares/Third_Party/FatFs/src/ff_gen_drv.h \
+ ../Middlewares/Third_Party/FatFs/src/diskio.h \
+ ../Middlewares/Third_Party/FatFs/src/integer.h \
+ ../Middlewares/Third_Party/FatFs/src/ff.h ../FATFS/Target/ffconf.h \
+ ../Core/Inc/main.h ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \
+ ../Core/Inc/stm32h7xx_hal_conf.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h \
+ ../Drivers/CMSIS/Include/core_cm7.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \
+ ../FATFS/Target/bsp_driver_sd.h ../FATFS/Target/fatfs_platform.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h \
+ ../Core/Inc/FreeRTOSConfig.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/list.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h
+../Middlewares/Third_Party/FatFs/src/ff_gen_drv.h:
+../Middlewares/Third_Party/FatFs/src/diskio.h:
+../Middlewares/Third_Party/FatFs/src/integer.h:
+../Middlewares/Third_Party/FatFs/src/ff.h:
+../FATFS/Target/ffconf.h:
+../Core/Inc/main.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h:
+../Core/Inc/stm32h7xx_hal_conf.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h:
+../Drivers/CMSIS/Include/core_cm7.h:
+../Drivers/CMSIS/Include/cmsis_version.h:
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+../Drivers/CMSIS/Include/mpu_armv7.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
+../FATFS/Target/bsp_driver_sd.h:
+../FATFS/Target/fatfs_platform.h:
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h:
+../Core/Inc/FreeRTOSConfig.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h:
+../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/task.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/list.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/task.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h:
diff --git a/Debug/Middlewares/Third_Party/FatFs/src/ff_gen_drv.o b/Debug/Middlewares/Third_Party/FatFs/src/ff_gen_drv.o
new file mode 100644
index 0000000..5faf696
Binary files /dev/null and b/Debug/Middlewares/Third_Party/FatFs/src/ff_gen_drv.o differ
diff --git a/Debug/Middlewares/Third_Party/FatFs/src/ff_gen_drv.su b/Debug/Middlewares/Third_Party/FatFs/src/ff_gen_drv.su
new file mode 100644
index 0000000..e610e3d
--- /dev/null
+++ b/Debug/Middlewares/Third_Party/FatFs/src/ff_gen_drv.su
@@ -0,0 +1,5 @@
+../Middlewares/Third_Party/FatFs/src/ff_gen_drv.c:39:9:FATFS_LinkDriverEx	32	static
+../Middlewares/Third_Party/FatFs/src/ff_gen_drv.c:68:9:FATFS_LinkDriver	16	static
+../Middlewares/Third_Party/FatFs/src/ff_gen_drv.c:80:9:FATFS_UnLinkDriverEx	24	static
+../Middlewares/Third_Party/FatFs/src/ff_gen_drv.c:106:9:FATFS_UnLinkDriver	16	static
+../Middlewares/Third_Party/FatFs/src/ff_gen_drv.c:116:9:FATFS_GetAttachedDriversNbr	4	static
diff --git a/Debug/Middlewares/Third_Party/FatFs/src/option/ccsbcs.cyclo b/Debug/Middlewares/Third_Party/FatFs/src/option/ccsbcs.cyclo
new file mode 100644
index 0000000..57f6a42
--- /dev/null
+++ b/Debug/Middlewares/Third_Party/FatFs/src/option/ccsbcs.cyclo
@@ -0,0 +1,2 @@
+../Middlewares/Third_Party/FatFs/src/option/ccsbcs.c:275:7:ff_convert	6
+../Middlewares/Third_Party/FatFs/src/option/ccsbcs.c:303:7:ff_wtoupper	15
diff --git a/Debug/Middlewares/Third_Party/FatFs/src/option/ccsbcs.d b/Debug/Middlewares/Third_Party/FatFs/src/option/ccsbcs.d
new file mode 100644
index 0000000..979fbda
--- /dev/null
+++ b/Debug/Middlewares/Third_Party/FatFs/src/option/ccsbcs.d
@@ -0,0 +1,124 @@
+Middlewares/Third_Party/FatFs/src/option/ccsbcs.o: \
+ ../Middlewares/Third_Party/FatFs/src/option/ccsbcs.c \
+ ../Middlewares/Third_Party/FatFs/src/option/../ff.h \
+ ../Middlewares/Third_Party/FatFs/src/option/../integer.h \
+ ../FATFS/Target/ffconf.h ../Core/Inc/main.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \
+ ../Core/Inc/stm32h7xx_hal_conf.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h \
+ ../Drivers/CMSIS/Include/core_cm7.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \
+ ../FATFS/Target/bsp_driver_sd.h ../FATFS/Target/fatfs_platform.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h \
+ ../Core/Inc/FreeRTOSConfig.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/list.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h
+../Middlewares/Third_Party/FatFs/src/option/../ff.h:
+../Middlewares/Third_Party/FatFs/src/option/../integer.h:
+../FATFS/Target/ffconf.h:
+../Core/Inc/main.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h:
+../Core/Inc/stm32h7xx_hal_conf.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h:
+../Drivers/CMSIS/Include/core_cm7.h:
+../Drivers/CMSIS/Include/cmsis_version.h:
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+../Drivers/CMSIS/Include/mpu_armv7.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
+../FATFS/Target/bsp_driver_sd.h:
+../FATFS/Target/fatfs_platform.h:
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h:
+../Core/Inc/FreeRTOSConfig.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h:
+../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/task.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/list.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/task.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h:
diff --git a/Debug/Middlewares/Third_Party/FatFs/src/option/ccsbcs.o b/Debug/Middlewares/Third_Party/FatFs/src/option/ccsbcs.o
new file mode 100644
index 0000000..9e23bd9
Binary files /dev/null and b/Debug/Middlewares/Third_Party/FatFs/src/option/ccsbcs.o differ
diff --git a/Debug/Middlewares/Third_Party/FatFs/src/option/ccsbcs.su b/Debug/Middlewares/Third_Party/FatFs/src/option/ccsbcs.su
new file mode 100644
index 0000000..3d35439
--- /dev/null
+++ b/Debug/Middlewares/Third_Party/FatFs/src/option/ccsbcs.su
@@ -0,0 +1,2 @@
+../Middlewares/Third_Party/FatFs/src/option/ccsbcs.c:275:7:ff_convert	24	static
+../Middlewares/Third_Party/FatFs/src/option/ccsbcs.c:303:7:ff_wtoupper	32	static
diff --git a/Debug/Middlewares/Third_Party/FatFs/src/option/subdir.mk b/Debug/Middlewares/Third_Party/FatFs/src/option/subdir.mk
new file mode 100644
index 0000000..19f8fe6
--- /dev/null
+++ b/Debug/Middlewares/Third_Party/FatFs/src/option/subdir.mk
@@ -0,0 +1,30 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+# Toolchain: GNU Tools for STM32 (11.3.rel1)
+################################################################################
+
+# Add inputs and outputs from these tool invocations to the build variables 
+C_SRCS += \
+../Middlewares/Third_Party/FatFs/src/option/ccsbcs.c \
+../Middlewares/Third_Party/FatFs/src/option/syscall.c 
+
+OBJS += \
+./Middlewares/Third_Party/FatFs/src/option/ccsbcs.o \
+./Middlewares/Third_Party/FatFs/src/option/syscall.o 
+
+C_DEPS += \
+./Middlewares/Third_Party/FatFs/src/option/ccsbcs.d \
+./Middlewares/Third_Party/FatFs/src/option/syscall.d 
+
+
+# Each subdirectory must supply rules for building sources it contributes
+Middlewares/Third_Party/FatFs/src/option/%.o Middlewares/Third_Party/FatFs/src/option/%.su Middlewares/Third_Party/FatFs/src/option/%.cyclo: ../Middlewares/Third_Party/FatFs/src/option/%.c Middlewares/Third_Party/FatFs/src/option/subdir.mk
+	arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DDEBUG -DDATA_IN_D2_SRAM -DUSE_HAL_DRIVER -DSTM32H723xx -c -I../Core/Inc -I../FATFS/Target -I../FATFS/App -I../LWIP/App -I../LWIP/Target -I../Middlewares/Third_Party/LwIP/src/include -I../Middlewares/Third_Party/LwIP/system -I../Drivers/STM32H7xx_HAL_Driver/Inc -I../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F -I../Middlewares/Third_Party/FatFs/src -I../Drivers/BSP/Components/lan8742 -I../Middlewares/Third_Party/LwIP/src/include/netif/ppp -I../Drivers/CMSIS/Device/ST/STM32H7xx/Include -I../Middlewares/Third_Party/LwIP/src/include/lwip -I../Middlewares/Third_Party/LwIP/src/include/lwip/apps -I../Middlewares/Third_Party/LwIP/src/include/lwip/priv -I../Middlewares/Third_Party/LwIP/src/include/lwip/prot -I../Middlewares/Third_Party/LwIP/src/include/netif -I../Middlewares/Third_Party/LwIP/src/include/compat/posix -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/arpa -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/net -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/sys -I../Middlewares/Third_Party/LwIP/src/include/compat/stdc -I../Middlewares/Third_Party/LwIP/system/arch -I../Drivers/CMSIS/Include -I"C:/_NoSleep/STM32/TBD_TaxiBoard/LWFTPC" -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
+
+clean: clean-Middlewares-2f-Third_Party-2f-FatFs-2f-src-2f-option
+
+clean-Middlewares-2f-Third_Party-2f-FatFs-2f-src-2f-option:
+	-$(RM) ./Middlewares/Third_Party/FatFs/src/option/ccsbcs.cyclo ./Middlewares/Third_Party/FatFs/src/option/ccsbcs.d ./Middlewares/Third_Party/FatFs/src/option/ccsbcs.o ./Middlewares/Third_Party/FatFs/src/option/ccsbcs.su ./Middlewares/Third_Party/FatFs/src/option/syscall.cyclo ./Middlewares/Third_Party/FatFs/src/option/syscall.d ./Middlewares/Third_Party/FatFs/src/option/syscall.o ./Middlewares/Third_Party/FatFs/src/option/syscall.su
+
+.PHONY: clean-Middlewares-2f-Third_Party-2f-FatFs-2f-src-2f-option
+
diff --git a/Debug/Middlewares/Third_Party/FatFs/src/option/syscall.cyclo b/Debug/Middlewares/Third_Party/FatFs/src/option/syscall.cyclo
new file mode 100644
index 0000000..b2312a0
--- /dev/null
+++ b/Debug/Middlewares/Third_Party/FatFs/src/option/syscall.cyclo
@@ -0,0 +1,4 @@
+../Middlewares/Third_Party/FatFs/src/option/syscall.c:36:5:ff_cre_syncobj	1
+../Middlewares/Third_Party/FatFs/src/option/syscall.c:77:5:ff_del_syncobj	1
+../Middlewares/Third_Party/FatFs/src/option/syscall.c:98:5:ff_req_grant	2
+../Middlewares/Third_Party/FatFs/src/option/syscall.c:135:6:ff_rel_grant	1
diff --git a/Debug/Middlewares/Third_Party/FatFs/src/option/syscall.d b/Debug/Middlewares/Third_Party/FatFs/src/option/syscall.d
new file mode 100644
index 0000000..3ed7a4c
--- /dev/null
+++ b/Debug/Middlewares/Third_Party/FatFs/src/option/syscall.d
@@ -0,0 +1,124 @@
+Middlewares/Third_Party/FatFs/src/option/syscall.o: \
+ ../Middlewares/Third_Party/FatFs/src/option/syscall.c \
+ ../Middlewares/Third_Party/FatFs/src/option/../ff.h \
+ ../Middlewares/Third_Party/FatFs/src/option/../integer.h \
+ ../FATFS/Target/ffconf.h ../Core/Inc/main.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \
+ ../Core/Inc/stm32h7xx_hal_conf.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h \
+ ../Drivers/CMSIS/Include/core_cm7.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \
+ ../FATFS/Target/bsp_driver_sd.h ../FATFS/Target/fatfs_platform.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h \
+ ../Core/Inc/FreeRTOSConfig.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/list.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h
+../Middlewares/Third_Party/FatFs/src/option/../ff.h:
+../Middlewares/Third_Party/FatFs/src/option/../integer.h:
+../FATFS/Target/ffconf.h:
+../Core/Inc/main.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h:
+../Core/Inc/stm32h7xx_hal_conf.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h:
+../Drivers/CMSIS/Include/core_cm7.h:
+../Drivers/CMSIS/Include/cmsis_version.h:
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+../Drivers/CMSIS/Include/mpu_armv7.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
+../FATFS/Target/bsp_driver_sd.h:
+../FATFS/Target/fatfs_platform.h:
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h:
+../Core/Inc/FreeRTOSConfig.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h:
+../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/task.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/list.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/task.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h:
diff --git a/Debug/Middlewares/Third_Party/FatFs/src/option/syscall.o b/Debug/Middlewares/Third_Party/FatFs/src/option/syscall.o
new file mode 100644
index 0000000..4c0c3a7
Binary files /dev/null and b/Debug/Middlewares/Third_Party/FatFs/src/option/syscall.o differ
diff --git a/Debug/Middlewares/Third_Party/FatFs/src/option/syscall.su b/Debug/Middlewares/Third_Party/FatFs/src/option/syscall.su
new file mode 100644
index 0000000..60f8be2
--- /dev/null
+++ b/Debug/Middlewares/Third_Party/FatFs/src/option/syscall.su
@@ -0,0 +1,4 @@
+../Middlewares/Third_Party/FatFs/src/option/syscall.c:36:5:ff_cre_syncobj	32	static
+../Middlewares/Third_Party/FatFs/src/option/syscall.c:77:5:ff_del_syncobj	16	static
+../Middlewares/Third_Party/FatFs/src/option/syscall.c:98:5:ff_req_grant	24	static
+../Middlewares/Third_Party/FatFs/src/option/syscall.c:135:6:ff_rel_grant	16	static
diff --git a/Debug/Middlewares/Third_Party/FatFs/src/subdir.mk b/Debug/Middlewares/Third_Party/FatFs/src/subdir.mk
new file mode 100644
index 0000000..6d1fb94
--- /dev/null
+++ b/Debug/Middlewares/Third_Party/FatFs/src/subdir.mk
@@ -0,0 +1,33 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+# Toolchain: GNU Tools for STM32 (11.3.rel1)
+################################################################################
+
+# Add inputs and outputs from these tool invocations to the build variables 
+C_SRCS += \
+../Middlewares/Third_Party/FatFs/src/diskio.c \
+../Middlewares/Third_Party/FatFs/src/ff.c \
+../Middlewares/Third_Party/FatFs/src/ff_gen_drv.c 
+
+OBJS += \
+./Middlewares/Third_Party/FatFs/src/diskio.o \
+./Middlewares/Third_Party/FatFs/src/ff.o \
+./Middlewares/Third_Party/FatFs/src/ff_gen_drv.o 
+
+C_DEPS += \
+./Middlewares/Third_Party/FatFs/src/diskio.d \
+./Middlewares/Third_Party/FatFs/src/ff.d \
+./Middlewares/Third_Party/FatFs/src/ff_gen_drv.d 
+
+
+# Each subdirectory must supply rules for building sources it contributes
+Middlewares/Third_Party/FatFs/src/%.o Middlewares/Third_Party/FatFs/src/%.su Middlewares/Third_Party/FatFs/src/%.cyclo: ../Middlewares/Third_Party/FatFs/src/%.c Middlewares/Third_Party/FatFs/src/subdir.mk
+	arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DDEBUG -DDATA_IN_D2_SRAM -DUSE_HAL_DRIVER -DSTM32H723xx -c -I../Core/Inc -I../FATFS/Target -I../FATFS/App -I../LWIP/App -I../LWIP/Target -I../Middlewares/Third_Party/LwIP/src/include -I../Middlewares/Third_Party/LwIP/system -I../Drivers/STM32H7xx_HAL_Driver/Inc -I../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F -I../Middlewares/Third_Party/FatFs/src -I../Drivers/BSP/Components/lan8742 -I../Middlewares/Third_Party/LwIP/src/include/netif/ppp -I../Drivers/CMSIS/Device/ST/STM32H7xx/Include -I../Middlewares/Third_Party/LwIP/src/include/lwip -I../Middlewares/Third_Party/LwIP/src/include/lwip/apps -I../Middlewares/Third_Party/LwIP/src/include/lwip/priv -I../Middlewares/Third_Party/LwIP/src/include/lwip/prot -I../Middlewares/Third_Party/LwIP/src/include/netif -I../Middlewares/Third_Party/LwIP/src/include/compat/posix -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/arpa -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/net -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/sys -I../Middlewares/Third_Party/LwIP/src/include/compat/stdc -I../Middlewares/Third_Party/LwIP/system/arch -I../Drivers/CMSIS/Include -I"C:/_NoSleep/STM32/TBD_TaxiBoard/LWFTPC" -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
+
+clean: clean-Middlewares-2f-Third_Party-2f-FatFs-2f-src
+
+clean-Middlewares-2f-Third_Party-2f-FatFs-2f-src:
+	-$(RM) ./Middlewares/Third_Party/FatFs/src/diskio.cyclo ./Middlewares/Third_Party/FatFs/src/diskio.d ./Middlewares/Third_Party/FatFs/src/diskio.o ./Middlewares/Third_Party/FatFs/src/diskio.su ./Middlewares/Third_Party/FatFs/src/ff.cyclo ./Middlewares/Third_Party/FatFs/src/ff.d ./Middlewares/Third_Party/FatFs/src/ff.o ./Middlewares/Third_Party/FatFs/src/ff.su ./Middlewares/Third_Party/FatFs/src/ff_gen_drv.cyclo ./Middlewares/Third_Party/FatFs/src/ff_gen_drv.d ./Middlewares/Third_Party/FatFs/src/ff_gen_drv.o ./Middlewares/Third_Party/FatFs/src/ff_gen_drv.su
+
+.PHONY: clean-Middlewares-2f-Third_Party-2f-FatFs-2f-src
+
diff --git a/Debug/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.cyclo b/Debug/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.cyclo
new file mode 100644
index 0000000..ce38697
--- /dev/null
+++ b/Debug/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.cyclo
@@ -0,0 +1,56 @@
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:103:31:makeFreeRtosPriority	2
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:116:19:makeCmsisPriority	2
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:130:12:inHandlerMode	1
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:150:10:osKernelStart	1
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:165:9:osKernelRunning	2
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:184:10:osKernelSysTick	2
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:202:12:osThreadCreate	4
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:240:12:osThreadGetId	1
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:255:10:osThreadTerminate	1
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:270:10:osThreadYield	1
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:284:10:osThreadSetPriority	1
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:300:12:osThreadGetPriority	2
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:322:10:osDelay	2
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:357:11:osTimerCreate	4
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:404:10:osTimerStart	6
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:443:10:osTimerStop	5
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:472:10:osTimerDelete	3
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:502:9:osSignalSet	5
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:543:9:osSignalWait	8
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:597:11:osMutexCreate	2
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:626:10:osMutexWait	9
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:666:10:osMutexRelease	5
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:690:10:osMutexDelete	2
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:712:15:osSemaphoreCreate	5
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:779:9:osSemaphoreWait	9
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:819:10:osSemaphoreRelease	5
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:846:10:osSemaphoreDelete	2
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:883:10:osPoolCreate	5
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:936:7:osPoolAlloc	5
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:977:7:osPoolCAlloc	2
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:996:10:osPoolFree	6
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:1040:14:osMessageCreate	3
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:1067:10:osMessagePut	6
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:1099:9:osMessageGet	10
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:1168:11:osMailCreate	4
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:1214:7:osMailAlloc	2
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:1236:7:osMailCAlloc	3
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:1257:10:osMailPut	6
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:1290:9:osMailGet	10
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:1346:10:osMailFree	2
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:1362:6:osSystickHandler	2
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:1432:10:osThreadSuspend	1
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:1448:10:osThreadResume	3
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:1472:10:osThreadSuspendAll	1
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:1483:10:osThreadResumeAll	2
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:1500:10:osDelayUntil	2
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:1520:10:osAbortDelay	1
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:1541:10:osThreadList	1
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:1555:9:osMessagePeek	7
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:1596:10:osMessageWaiting	2
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:1612:10:osMessageAvailableSpace	1
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:1622:10:osMessageDelete	2
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:1638:11:osRecursiveMutexCreate	1
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:1664:10:osRecursiveMutexRelease	1
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:1685:10:osRecursiveMutexWait	1
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:1724:10:osSemaphoreGetCount	1
diff --git a/Debug/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.d b/Debug/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.d
new file mode 100644
index 0000000..6f93a0c
--- /dev/null
+++ b/Debug/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.d
@@ -0,0 +1,38 @@
+Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o: \
+ ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c \
+ ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h \
+ ../Core/Inc/FreeRTOSConfig.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/list.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h:
+../Core/Inc/FreeRTOSConfig.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h:
+../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/task.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/list.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/task.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h:
+../Drivers/CMSIS/Include/cmsis_gcc.h:
diff --git a/Debug/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o b/Debug/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o
new file mode 100644
index 0000000..3b7c5ee
Binary files /dev/null and b/Debug/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o differ
diff --git a/Debug/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.su b/Debug/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.su
new file mode 100644
index 0000000..c930655
--- /dev/null
+++ b/Debug/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.su
@@ -0,0 +1,56 @@
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:103:31:makeFreeRtosPriority	24	static
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:116:19:makeCmsisPriority	24	static
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:130:12:inHandlerMode	16	static,ignoring_inline_asm
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:150:10:osKernelStart	8	static
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:165:9:osKernelRunning	8	static
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:184:10:osKernelSysTick	8	static
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:202:12:osThreadCreate	56	static
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:240:12:osThreadGetId	8	static
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:255:10:osThreadTerminate	16	static
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:270:10:osThreadYield	4	static,ignoring_inline_asm
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:284:10:osThreadSetPriority	16	static
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:300:12:osThreadGetPriority	16	static
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:322:10:osDelay	24	static
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:357:11:osTimerCreate	32	static
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:404:10:osTimerStart	40	static,ignoring_inline_asm
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:443:10:osTimerStop	32	static,ignoring_inline_asm
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:472:10:osTimerDelete	32	static
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:502:9:osSignalSet	32	static,ignoring_inline_asm
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:543:9:osSignalWait	48	static
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:597:11:osMutexCreate	16	static
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:626:10:osMutexWait	24	static,ignoring_inline_asm
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:666:10:osMutexRelease	24	static,ignoring_inline_asm
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:690:10:osMutexDelete	16	static
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:712:15:osSemaphoreCreate	32	static
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:779:9:osSemaphoreWait	24	static,ignoring_inline_asm
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:819:10:osSemaphoreRelease	24	static,ignoring_inline_asm
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:846:10:osSemaphoreDelete	16	static
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:883:10:osPoolCreate	32	static
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:936:7:osPoolAlloc	48	static,ignoring_inline_asm
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:977:7:osPoolCAlloc	24	static
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:996:10:osPoolFree	24	static
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:1040:14:osMessageCreate	32	static
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:1067:10:osMessagePut	32	static,ignoring_inline_asm
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:1099:9:osMessageGet	56	static,ignoring_inline_asm
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:1168:11:osMailCreate	40	static
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:1214:7:osMailAlloc	24	static
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:1236:7:osMailCAlloc	24	static
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:1257:10:osMailPut	24	static,ignoring_inline_asm
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:1290:9:osMailGet	56	static,ignoring_inline_asm
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:1346:10:osMailFree	16	static
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:1362:6:osSystickHandler	8	static
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:1432:10:osThreadSuspend	16	static
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:1448:10:osThreadResume	16	static,ignoring_inline_asm
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:1472:10:osThreadSuspendAll	8	static
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:1483:10:osThreadResumeAll	8	static
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:1500:10:osDelayUntil	24	static
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:1520:10:osAbortDelay	16	static
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:1541:10:osThreadList	16	static
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:1555:9:osMessagePeek	48	static
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:1596:10:osMessageWaiting	16	static
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:1612:10:osMessageAvailableSpace	16	static
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:1622:10:osMessageDelete	16	static
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:1638:11:osRecursiveMutexCreate	16	static
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:1664:10:osRecursiveMutexRelease	16	static
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:1685:10:osRecursiveMutexWait	16	static
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:1724:10:osSemaphoreGetCount	16	static
diff --git a/Debug/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/subdir.mk b/Debug/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/subdir.mk
new file mode 100644
index 0000000..2219b77
--- /dev/null
+++ b/Debug/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/subdir.mk
@@ -0,0 +1,27 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+# Toolchain: GNU Tools for STM32 (11.3.rel1)
+################################################################################
+
+# Add inputs and outputs from these tool invocations to the build variables 
+C_SRCS += \
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c 
+
+OBJS += \
+./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o 
+
+C_DEPS += \
+./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.d 
+
+
+# Each subdirectory must supply rules for building sources it contributes
+Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/%.o Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/%.su Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/%.cyclo: ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/%.c Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/subdir.mk
+	arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DDEBUG -DDATA_IN_D2_SRAM -DUSE_HAL_DRIVER -DSTM32H723xx -c -I../Core/Inc -I../FATFS/Target -I../FATFS/App -I../LWIP/App -I../LWIP/Target -I../Middlewares/Third_Party/LwIP/src/include -I../Middlewares/Third_Party/LwIP/system -I../Drivers/STM32H7xx_HAL_Driver/Inc -I../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F -I../Middlewares/Third_Party/FatFs/src -I../Drivers/BSP/Components/lan8742 -I../Middlewares/Third_Party/LwIP/src/include/netif/ppp -I../Drivers/CMSIS/Device/ST/STM32H7xx/Include -I../Middlewares/Third_Party/LwIP/src/include/lwip -I../Middlewares/Third_Party/LwIP/src/include/lwip/apps -I../Middlewares/Third_Party/LwIP/src/include/lwip/priv -I../Middlewares/Third_Party/LwIP/src/include/lwip/prot -I../Middlewares/Third_Party/LwIP/src/include/netif -I../Middlewares/Third_Party/LwIP/src/include/compat/posix -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/arpa -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/net -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/sys -I../Middlewares/Third_Party/LwIP/src/include/compat/stdc -I../Middlewares/Third_Party/LwIP/system/arch -I../Drivers/CMSIS/Include -I"C:/_NoSleep/STM32/TBD_TaxiBoard/LWFTPC" -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
+
+clean: clean-Middlewares-2f-Third_Party-2f-FreeRTOS-2f-Source-2f-CMSIS_RTOS
+
+clean-Middlewares-2f-Third_Party-2f-FreeRTOS-2f-Source-2f-CMSIS_RTOS:
+	-$(RM) ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.cyclo ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.d ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.su
+
+.PHONY: clean-Middlewares-2f-Third_Party-2f-FreeRTOS-2f-Source-2f-CMSIS_RTOS
+
diff --git a/Debug/LWFTP/lwftp_mod.cyclo b/Debug/Middlewares/Third_Party/FreeRTOS/Source/croutine.cyclo
similarity index 100%
rename from Debug/LWFTP/lwftp_mod.cyclo
rename to Debug/Middlewares/Third_Party/FreeRTOS/Source/croutine.cyclo
diff --git a/Debug/Middlewares/Third_Party/FreeRTOS/Source/croutine.d b/Debug/Middlewares/Third_Party/FreeRTOS/Source/croutine.d
new file mode 100644
index 0000000..917ef11
--- /dev/null
+++ b/Debug/Middlewares/Third_Party/FreeRTOS/Source/croutine.d
@@ -0,0 +1,22 @@
+Middlewares/Third_Party/FreeRTOS/Source/croutine.o: \
+ ../Middlewares/Third_Party/FreeRTOS/Source/croutine.c \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h \
+ ../Core/Inc/FreeRTOSConfig.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/list.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/croutine.h
+../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h:
+../Core/Inc/FreeRTOSConfig.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h:
+../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/task.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/list.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/croutine.h:
diff --git a/Debug/Middlewares/Third_Party/FreeRTOS/Source/croutine.o b/Debug/Middlewares/Third_Party/FreeRTOS/Source/croutine.o
new file mode 100644
index 0000000..d1097b5
Binary files /dev/null and b/Debug/Middlewares/Third_Party/FreeRTOS/Source/croutine.o differ
diff --git a/Debug/LWFTP/lwftp_mod.su b/Debug/Middlewares/Third_Party/FreeRTOS/Source/croutine.su
similarity index 100%
rename from Debug/LWFTP/lwftp_mod.su
rename to Debug/Middlewares/Third_Party/FreeRTOS/Source/croutine.su
diff --git a/Debug/Middlewares/Third_Party/FreeRTOS/Source/event_groups.cyclo b/Debug/Middlewares/Third_Party/FreeRTOS/Source/event_groups.cyclo
new file mode 100644
index 0000000..56c4d2b
--- /dev/null
+++ b/Debug/Middlewares/Third_Party/FreeRTOS/Source/event_groups.cyclo
@@ -0,0 +1,11 @@
+../Middlewares/Third_Party/FreeRTOS/Source/event_groups.c:93:21:xEventGroupCreateStatic	4
+../Middlewares/Third_Party/FreeRTOS/Source/event_groups.c:145:21:xEventGroupCreate	2
+../Middlewares/Third_Party/FreeRTOS/Source/event_groups.c:191:13:xEventGroupSync	12
+../Middlewares/Third_Party/FreeRTOS/Source/event_groups.c:311:13:xEventGroupWaitBits	17
+../Middlewares/Third_Party/FreeRTOS/Source/event_groups.c:461:13:xEventGroupClearBits	3
+../Middlewares/Third_Party/FreeRTOS/Source/event_groups.c:503:13:xEventGroupGetBitsFromISR	1
+../Middlewares/Third_Party/FreeRTOS/Source/event_groups.c:519:13:xEventGroupSetBits	9
+../Middlewares/Third_Party/FreeRTOS/Source/event_groups.c:613:6:vEventGroupDelete	4
+../Middlewares/Third_Party/FreeRTOS/Source/event_groups.c:657:6:vEventGroupSetBitsCallback	1
+../Middlewares/Third_Party/FreeRTOS/Source/event_groups.c:665:6:vEventGroupClearBitsCallback	1
+../Middlewares/Third_Party/FreeRTOS/Source/event_groups.c:671:19:prvTestWaitCondition	4
diff --git a/Debug/Middlewares/Third_Party/FreeRTOS/Source/event_groups.d b/Debug/Middlewares/Third_Party/FreeRTOS/Source/event_groups.d
new file mode 100644
index 0000000..a2c9c62
--- /dev/null
+++ b/Debug/Middlewares/Third_Party/FreeRTOS/Source/event_groups.d
@@ -0,0 +1,28 @@
+Middlewares/Third_Party/FreeRTOS/Source/event_groups.o: \
+ ../Middlewares/Third_Party/FreeRTOS/Source/event_groups.c \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h \
+ ../Core/Inc/FreeRTOSConfig.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/list.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h
+../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h:
+../Core/Inc/FreeRTOSConfig.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h:
+../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/task.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/list.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/task.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h:
diff --git a/Debug/Middlewares/Third_Party/FreeRTOS/Source/event_groups.o b/Debug/Middlewares/Third_Party/FreeRTOS/Source/event_groups.o
new file mode 100644
index 0000000..d9745f9
Binary files /dev/null and b/Debug/Middlewares/Third_Party/FreeRTOS/Source/event_groups.o differ
diff --git a/Debug/Middlewares/Third_Party/FreeRTOS/Source/event_groups.su b/Debug/Middlewares/Third_Party/FreeRTOS/Source/event_groups.su
new file mode 100644
index 0000000..b97429e
--- /dev/null
+++ b/Debug/Middlewares/Third_Party/FreeRTOS/Source/event_groups.su
@@ -0,0 +1,11 @@
+../Middlewares/Third_Party/FreeRTOS/Source/event_groups.c:93:21:xEventGroupCreateStatic	32	static,ignoring_inline_asm
+../Middlewares/Third_Party/FreeRTOS/Source/event_groups.c:145:21:xEventGroupCreate	16	static
+../Middlewares/Third_Party/FreeRTOS/Source/event_groups.c:191:13:xEventGroupSync	56	static,ignoring_inline_asm
+../Middlewares/Third_Party/FreeRTOS/Source/event_groups.c:311:13:xEventGroupWaitBits	72	static,ignoring_inline_asm
+../Middlewares/Third_Party/FreeRTOS/Source/event_groups.c:461:13:xEventGroupClearBits	32	static,ignoring_inline_asm
+../Middlewares/Third_Party/FreeRTOS/Source/event_groups.c:503:13:xEventGroupGetBitsFromISR	40	static,ignoring_inline_asm
+../Middlewares/Third_Party/FreeRTOS/Source/event_groups.c:519:13:xEventGroupSetBits	64	static,ignoring_inline_asm
+../Middlewares/Third_Party/FreeRTOS/Source/event_groups.c:613:6:vEventGroupDelete	32	static,ignoring_inline_asm
+../Middlewares/Third_Party/FreeRTOS/Source/event_groups.c:657:6:vEventGroupSetBitsCallback	16	static
+../Middlewares/Third_Party/FreeRTOS/Source/event_groups.c:665:6:vEventGroupClearBitsCallback	16	static
+../Middlewares/Third_Party/FreeRTOS/Source/event_groups.c:671:19:prvTestWaitCondition	32	static
diff --git a/Debug/Middlewares/Third_Party/FreeRTOS/Source/list.cyclo b/Debug/Middlewares/Third_Party/FreeRTOS/Source/list.cyclo
new file mode 100644
index 0000000..8d6cdb0
--- /dev/null
+++ b/Debug/Middlewares/Third_Party/FreeRTOS/Source/list.cyclo
@@ -0,0 +1,5 @@
+../Middlewares/Third_Party/FreeRTOS/Source/list.c:37:6:vListInitialise	1
+../Middlewares/Third_Party/FreeRTOS/Source/list.c:62:6:vListInitialiseItem	1
+../Middlewares/Third_Party/FreeRTOS/Source/list.c:74:6:vListInsertEnd	1
+../Middlewares/Third_Party/FreeRTOS/Source/list.c:103:6:vListInsert	3
+../Middlewares/Third_Party/FreeRTOS/Source/list.c:170:13:uxListRemove	2
diff --git a/Debug/Middlewares/Third_Party/FreeRTOS/Source/list.d b/Debug/Middlewares/Third_Party/FreeRTOS/Source/list.d
new file mode 100644
index 0000000..a46554b
--- /dev/null
+++ b/Debug/Middlewares/Third_Party/FreeRTOS/Source/list.d
@@ -0,0 +1,18 @@
+Middlewares/Third_Party/FreeRTOS/Source/list.o: \
+ ../Middlewares/Third_Party/FreeRTOS/Source/list.c \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h \
+ ../Core/Inc/FreeRTOSConfig.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/list.h
+../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h:
+../Core/Inc/FreeRTOSConfig.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h:
+../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/list.h:
diff --git a/Debug/Middlewares/Third_Party/FreeRTOS/Source/list.o b/Debug/Middlewares/Third_Party/FreeRTOS/Source/list.o
new file mode 100644
index 0000000..6432af1
Binary files /dev/null and b/Debug/Middlewares/Third_Party/FreeRTOS/Source/list.o differ
diff --git a/Debug/Middlewares/Third_Party/FreeRTOS/Source/list.su b/Debug/Middlewares/Third_Party/FreeRTOS/Source/list.su
new file mode 100644
index 0000000..85c9323
--- /dev/null
+++ b/Debug/Middlewares/Third_Party/FreeRTOS/Source/list.su
@@ -0,0 +1,5 @@
+../Middlewares/Third_Party/FreeRTOS/Source/list.c:37:6:vListInitialise	16	static
+../Middlewares/Third_Party/FreeRTOS/Source/list.c:62:6:vListInitialiseItem	16	static
+../Middlewares/Third_Party/FreeRTOS/Source/list.c:74:6:vListInsertEnd	24	static
+../Middlewares/Third_Party/FreeRTOS/Source/list.c:103:6:vListInsert	24	static
+../Middlewares/Third_Party/FreeRTOS/Source/list.c:170:13:uxListRemove	24	static
diff --git a/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.cyclo b/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.cyclo
new file mode 100644
index 0000000..6e44697
--- /dev/null
+++ b/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.cyclo
@@ -0,0 +1,13 @@
+../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c:187:14:pxPortInitialiseStack	1
+../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c:217:13:prvTaskExitError	3
+../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c:242:6:SVC_Handler	1
+../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c:261:13:prvPortStartFirstTask	1
+../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c:287:12:xPortStartScheduler	5
+../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c:395:6:vPortEndScheduler	2
+../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c:403:6:vPortEnterCritical	3
+../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c:420:6:vPortExitCritical	3
+../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c:431:6:PendSV_Handler	1
+../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c:488:6:SysTick_Handler	2
+../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c:679:30:vPortSetupTimerInterrupt	1
+../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c:701:13:vPortEnableVFP	1
+../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c:717:7:vPortValidateInterruptPriority	4
diff --git a/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.d b/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.d
new file mode 100644
index 0000000..24dc560
--- /dev/null
+++ b/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.d
@@ -0,0 +1,20 @@
+Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.o: \
+ ../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h \
+ ../Core/Inc/FreeRTOSConfig.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/list.h
+../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h:
+../Core/Inc/FreeRTOSConfig.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h:
+../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/task.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/list.h:
diff --git a/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.o b/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.o
new file mode 100644
index 0000000..4c36497
Binary files /dev/null and b/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.o differ
diff --git a/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.su b/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.su
new file mode 100644
index 0000000..5a725d2
--- /dev/null
+++ b/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.su
@@ -0,0 +1,13 @@
+../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c:187:14:pxPortInitialiseStack	24	static
+../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c:217:13:prvTaskExitError	24	static,ignoring_inline_asm
+../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c:242:6:SVC_Handler	0	static,ignoring_inline_asm
+../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c:261:13:prvPortStartFirstTask	0	static,ignoring_inline_asm
+../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c:287:12:xPortStartScheduler	32	static,ignoring_inline_asm
+../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c:395:6:vPortEndScheduler	16	static,ignoring_inline_asm
+../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c:403:6:vPortEnterCritical	16	static,ignoring_inline_asm
+../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c:420:6:vPortExitCritical	16	static,ignoring_inline_asm
+../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c:431:6:PendSV_Handler	0	static,ignoring_inline_asm
+../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c:488:6:SysTick_Handler	16	static,ignoring_inline_asm
+../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c:679:30:vPortSetupTimerInterrupt	4	static
+../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c:701:13:vPortEnableVFP	0	static,ignoring_inline_asm
+../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c:717:7:vPortValidateInterruptPriority	24	static,ignoring_inline_asm
diff --git a/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/subdir.mk b/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/subdir.mk
new file mode 100644
index 0000000..c7380ce
--- /dev/null
+++ b/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/subdir.mk
@@ -0,0 +1,27 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+# Toolchain: GNU Tools for STM32 (11.3.rel1)
+################################################################################
+
+# Add inputs and outputs from these tool invocations to the build variables 
+C_SRCS += \
+../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c 
+
+OBJS += \
+./Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.o 
+
+C_DEPS += \
+./Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.d 
+
+
+# Each subdirectory must supply rules for building sources it contributes
+Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/%.o Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/%.su Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/%.cyclo: ../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/%.c Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/subdir.mk
+	arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DDEBUG -DDATA_IN_D2_SRAM -DUSE_HAL_DRIVER -DSTM32H723xx -c -I../Core/Inc -I../FATFS/Target -I../FATFS/App -I../LWIP/App -I../LWIP/Target -I../Middlewares/Third_Party/LwIP/src/include -I../Middlewares/Third_Party/LwIP/system -I../Drivers/STM32H7xx_HAL_Driver/Inc -I../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F -I../Middlewares/Third_Party/FatFs/src -I../Drivers/BSP/Components/lan8742 -I../Middlewares/Third_Party/LwIP/src/include/netif/ppp -I../Drivers/CMSIS/Device/ST/STM32H7xx/Include -I../Middlewares/Third_Party/LwIP/src/include/lwip -I../Middlewares/Third_Party/LwIP/src/include/lwip/apps -I../Middlewares/Third_Party/LwIP/src/include/lwip/priv -I../Middlewares/Third_Party/LwIP/src/include/lwip/prot -I../Middlewares/Third_Party/LwIP/src/include/netif -I../Middlewares/Third_Party/LwIP/src/include/compat/posix -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/arpa -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/net -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/sys -I../Middlewares/Third_Party/LwIP/src/include/compat/stdc -I../Middlewares/Third_Party/LwIP/system/arch -I../Drivers/CMSIS/Include -I"C:/_NoSleep/STM32/TBD_TaxiBoard/LWFTPC" -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
+
+clean: clean-Middlewares-2f-Third_Party-2f-FreeRTOS-2f-Source-2f-portable-2f-GCC-2f-ARM_CM4F
+
+clean-Middlewares-2f-Third_Party-2f-FreeRTOS-2f-Source-2f-portable-2f-GCC-2f-ARM_CM4F:
+	-$(RM) ./Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.cyclo ./Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.d ./Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.o ./Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.su
+
+.PHONY: clean-Middlewares-2f-Third_Party-2f-FreeRTOS-2f-Source-2f-portable-2f-GCC-2f-ARM_CM4F
+
diff --git a/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.cyclo b/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.cyclo
new file mode 100644
index 0000000..0fae04d
--- /dev/null
+++ b/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.cyclo
@@ -0,0 +1,8 @@
+../Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c:115:7:pvPortMalloc	15
+../Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c:266:6:vPortFree	6
+../Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c:315:8:xPortGetFreeHeapSize	1
+../Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c:321:8:xPortGetMinimumEverFreeHeapSize	1
+../Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c:327:6:vPortInitialiseBlocks	1
+../Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c:333:13:prvHeapInit	2
+../Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c:381:13:prvInsertBlockIntoFreeList	6
+../Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c:442:6:vPortGetHeapStats	5
diff --git a/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.d b/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.d
new file mode 100644
index 0000000..3239dc9
--- /dev/null
+++ b/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.d
@@ -0,0 +1,20 @@
+Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o: \
+ ../Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h \
+ ../Core/Inc/FreeRTOSConfig.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/list.h
+../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h:
+../Core/Inc/FreeRTOSConfig.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h:
+../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/task.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/list.h:
diff --git a/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o b/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o
new file mode 100644
index 0000000..a87569b
Binary files /dev/null and b/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o differ
diff --git a/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.su b/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.su
new file mode 100644
index 0000000..03dea47
--- /dev/null
+++ b/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.su
@@ -0,0 +1,8 @@
+../Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c:115:7:pvPortMalloc	48	static,ignoring_inline_asm
+../Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c:266:6:vPortFree	32	static,ignoring_inline_asm
+../Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c:315:8:xPortGetFreeHeapSize	4	static
+../Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c:321:8:xPortGetMinimumEverFreeHeapSize	4	static
+../Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c:327:6:vPortInitialiseBlocks	4	static
+../Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c:333:13:prvHeapInit	24	static
+../Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c:381:13:prvInsertBlockIntoFreeList	24	static
+../Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c:442:6:vPortGetHeapStats	32	static
diff --git a/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/subdir.mk b/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/subdir.mk
new file mode 100644
index 0000000..2162488
--- /dev/null
+++ b/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/subdir.mk
@@ -0,0 +1,27 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+# Toolchain: GNU Tools for STM32 (11.3.rel1)
+################################################################################
+
+# Add inputs and outputs from these tool invocations to the build variables 
+C_SRCS += \
+../Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c 
+
+OBJS += \
+./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o 
+
+C_DEPS += \
+./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.d 
+
+
+# Each subdirectory must supply rules for building sources it contributes
+Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/%.o Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/%.su Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/%.cyclo: ../Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/%.c Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/subdir.mk
+	arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DDEBUG -DDATA_IN_D2_SRAM -DUSE_HAL_DRIVER -DSTM32H723xx -c -I../Core/Inc -I../FATFS/Target -I../FATFS/App -I../LWIP/App -I../LWIP/Target -I../Middlewares/Third_Party/LwIP/src/include -I../Middlewares/Third_Party/LwIP/system -I../Drivers/STM32H7xx_HAL_Driver/Inc -I../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F -I../Middlewares/Third_Party/FatFs/src -I../Drivers/BSP/Components/lan8742 -I../Middlewares/Third_Party/LwIP/src/include/netif/ppp -I../Drivers/CMSIS/Device/ST/STM32H7xx/Include -I../Middlewares/Third_Party/LwIP/src/include/lwip -I../Middlewares/Third_Party/LwIP/src/include/lwip/apps -I../Middlewares/Third_Party/LwIP/src/include/lwip/priv -I../Middlewares/Third_Party/LwIP/src/include/lwip/prot -I../Middlewares/Third_Party/LwIP/src/include/netif -I../Middlewares/Third_Party/LwIP/src/include/compat/posix -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/arpa -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/net -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/sys -I../Middlewares/Third_Party/LwIP/src/include/compat/stdc -I../Middlewares/Third_Party/LwIP/system/arch -I../Drivers/CMSIS/Include -I"C:/_NoSleep/STM32/TBD_TaxiBoard/LWFTPC" -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
+
+clean: clean-Middlewares-2f-Third_Party-2f-FreeRTOS-2f-Source-2f-portable-2f-MemMang
+
+clean-Middlewares-2f-Third_Party-2f-FreeRTOS-2f-Source-2f-portable-2f-MemMang:
+	-$(RM) ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.cyclo ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.d ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.su
+
+.PHONY: clean-Middlewares-2f-Third_Party-2f-FreeRTOS-2f-Source-2f-portable-2f-MemMang
+
diff --git a/Debug/Middlewares/Third_Party/FreeRTOS/Source/queue.cyclo b/Debug/Middlewares/Third_Party/FreeRTOS/Source/queue.cyclo
new file mode 100644
index 0000000..5e0f982
--- /dev/null
+++ b/Debug/Middlewares/Third_Party/FreeRTOS/Source/queue.cyclo
@@ -0,0 +1,31 @@
+../Middlewares/Third_Party/FreeRTOS/Source/queue.c:255:12:xQueueGenericReset	5
+../Middlewares/Third_Party/FreeRTOS/Source/queue.c:310:16:xQueueGenericCreateStatic	11
+../Middlewares/Third_Party/FreeRTOS/Source/queue.c:368:16:xQueueGenericCreate	3
+../Middlewares/Third_Party/FreeRTOS/Source/queue.c:422:13:prvInitialiseNewQueue	2
+../Middlewares/Third_Party/FreeRTOS/Source/queue.c:466:14:prvInitialiseMutex	2
+../Middlewares/Third_Party/FreeRTOS/Source/queue.c:496:16:xQueueCreateMutex	1
+../Middlewares/Third_Party/FreeRTOS/Source/queue.c:512:16:xQueueCreateMutexStatic	1
+../Middlewares/Third_Party/FreeRTOS/Source/queue.c:740:12:xQueueGenericSend	23
+../Middlewares/Third_Party/FreeRTOS/Source/queue.c:950:12:xQueueGenericSendFromISR	14
+../Middlewares/Third_Party/FreeRTOS/Source/queue.c:1112:12:xQueueGiveFromISR	11
+../Middlewares/Third_Party/FreeRTOS/Source/queue.c:1277:12:xQueueReceive	19
+../Middlewares/Third_Party/FreeRTOS/Source/queue.c:1418:12:xQueueSemaphoreTake	21
+../Middlewares/Third_Party/FreeRTOS/Source/queue.c:1636:12:xQueuePeek	19
+../Middlewares/Third_Party/FreeRTOS/Source/queue.c:1785:12:xQueueReceiveFromISR	10
+../Middlewares/Third_Party/FreeRTOS/Source/queue.c:1876:12:xQueuePeekFromISR	7
+../Middlewares/Third_Party/FreeRTOS/Source/queue.c:1930:13:uxQueueMessagesWaiting	2
+../Middlewares/Third_Party/FreeRTOS/Source/queue.c:1946:13:uxQueueSpacesAvailable	2
+../Middlewares/Third_Party/FreeRTOS/Source/queue.c:1963:13:uxQueueMessagesWaitingFromISR	2
+../Middlewares/Third_Party/FreeRTOS/Source/queue.c:1975:6:vQueueDelete	3
+../Middlewares/Third_Party/FreeRTOS/Source/queue.c:2049:21:prvGetDisinheritPriorityAfterTimeout	2
+../Middlewares/Third_Party/FreeRTOS/Source/queue.c:2074:19:prvCopyDataToQueue	8
+../Middlewares/Third_Party/FreeRTOS/Source/queue.c:2153:13:prvCopyDataFromQueue	3
+../Middlewares/Third_Party/FreeRTOS/Source/queue.c:2171:13:prvUnlockQueue	7
+../Middlewares/Third_Party/FreeRTOS/Source/queue.c:2291:19:prvIsQueueEmpty	2
+../Middlewares/Third_Party/FreeRTOS/Source/queue.c:2312:12:xQueueIsQueueEmptyFromISR	3
+../Middlewares/Third_Party/FreeRTOS/Source/queue.c:2331:19:prvIsQueueFull	2
+../Middlewares/Third_Party/FreeRTOS/Source/queue.c:2352:12:xQueueIsQueueFullFromISR	3
+../Middlewares/Third_Party/FreeRTOS/Source/queue.c:2648:7:vQueueAddToRegistry	3
+../Middlewares/Third_Party/FreeRTOS/Source/queue.c:2677:14:pcQueueGetName	3
+../Middlewares/Third_Party/FreeRTOS/Source/queue.c:2705:7:vQueueUnregisterQueue	3
+../Middlewares/Third_Party/FreeRTOS/Source/queue.c:2737:7:vQueueWaitForMessageRestricted	4
diff --git a/Debug/Middlewares/Third_Party/FreeRTOS/Source/queue.d b/Debug/Middlewares/Third_Party/FreeRTOS/Source/queue.d
new file mode 100644
index 0000000..23ff8db
--- /dev/null
+++ b/Debug/Middlewares/Third_Party/FreeRTOS/Source/queue.d
@@ -0,0 +1,24 @@
+Middlewares/Third_Party/FreeRTOS/Source/queue.o: \
+ ../Middlewares/Third_Party/FreeRTOS/Source/queue.c \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h \
+ ../Core/Inc/FreeRTOSConfig.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/list.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h
+../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h:
+../Core/Inc/FreeRTOSConfig.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h:
+../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/task.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/list.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/task.h:
diff --git a/Debug/Middlewares/Third_Party/FreeRTOS/Source/queue.o b/Debug/Middlewares/Third_Party/FreeRTOS/Source/queue.o
new file mode 100644
index 0000000..f413f7f
Binary files /dev/null and b/Debug/Middlewares/Third_Party/FreeRTOS/Source/queue.o differ
diff --git a/Debug/Middlewares/Third_Party/FreeRTOS/Source/queue.su b/Debug/Middlewares/Third_Party/FreeRTOS/Source/queue.su
new file mode 100644
index 0000000..6c3322c
--- /dev/null
+++ b/Debug/Middlewares/Third_Party/FreeRTOS/Source/queue.su
@@ -0,0 +1,31 @@
+../Middlewares/Third_Party/FreeRTOS/Source/queue.c:255:12:xQueueGenericReset	24	static,ignoring_inline_asm
+../Middlewares/Third_Party/FreeRTOS/Source/queue.c:310:16:xQueueGenericCreateStatic	64	static,ignoring_inline_asm
+../Middlewares/Third_Party/FreeRTOS/Source/queue.c:368:16:xQueueGenericCreate	48	static,ignoring_inline_asm
+../Middlewares/Third_Party/FreeRTOS/Source/queue.c:422:13:prvInitialiseNewQueue	24	static
+../Middlewares/Third_Party/FreeRTOS/Source/queue.c:466:14:prvInitialiseMutex	16	static
+../Middlewares/Third_Party/FreeRTOS/Source/queue.c:496:16:xQueueCreateMutex	32	static
+../Middlewares/Third_Party/FreeRTOS/Source/queue.c:512:16:xQueueCreateMutexStatic	40	static
+../Middlewares/Third_Party/FreeRTOS/Source/queue.c:740:12:xQueueGenericSend	64	static,ignoring_inline_asm
+../Middlewares/Third_Party/FreeRTOS/Source/queue.c:950:12:xQueueGenericSendFromISR	72	static,ignoring_inline_asm
+../Middlewares/Third_Party/FreeRTOS/Source/queue.c:1112:12:xQueueGiveFromISR	64	static,ignoring_inline_asm
+../Middlewares/Third_Party/FreeRTOS/Source/queue.c:1277:12:xQueueReceive	56	static,ignoring_inline_asm
+../Middlewares/Third_Party/FreeRTOS/Source/queue.c:1418:12:xQueueSemaphoreTake	64	static,ignoring_inline_asm
+../Middlewares/Third_Party/FreeRTOS/Source/queue.c:1636:12:xQueuePeek	64	static,ignoring_inline_asm
+../Middlewares/Third_Party/FreeRTOS/Source/queue.c:1785:12:xQueueReceiveFromISR	64	static,ignoring_inline_asm
+../Middlewares/Third_Party/FreeRTOS/Source/queue.c:1876:12:xQueuePeekFromISR	56	static,ignoring_inline_asm
+../Middlewares/Third_Party/FreeRTOS/Source/queue.c:1930:13:uxQueueMessagesWaiting	24	static,ignoring_inline_asm
+../Middlewares/Third_Party/FreeRTOS/Source/queue.c:1946:13:uxQueueSpacesAvailable	32	static,ignoring_inline_asm
+../Middlewares/Third_Party/FreeRTOS/Source/queue.c:1963:13:uxQueueMessagesWaitingFromISR	32	static,ignoring_inline_asm
+../Middlewares/Third_Party/FreeRTOS/Source/queue.c:1975:6:vQueueDelete	24	static,ignoring_inline_asm
+../Middlewares/Third_Party/FreeRTOS/Source/queue.c:2049:21:prvGetDisinheritPriorityAfterTimeout	24	static
+../Middlewares/Third_Party/FreeRTOS/Source/queue.c:2074:19:prvCopyDataToQueue	32	static
+../Middlewares/Third_Party/FreeRTOS/Source/queue.c:2153:13:prvCopyDataFromQueue	16	static
+../Middlewares/Third_Party/FreeRTOS/Source/queue.c:2171:13:prvUnlockQueue	24	static
+../Middlewares/Third_Party/FreeRTOS/Source/queue.c:2291:19:prvIsQueueEmpty	24	static
+../Middlewares/Third_Party/FreeRTOS/Source/queue.c:2312:12:xQueueIsQueueEmptyFromISR	32	static,ignoring_inline_asm
+../Middlewares/Third_Party/FreeRTOS/Source/queue.c:2331:19:prvIsQueueFull	24	static
+../Middlewares/Third_Party/FreeRTOS/Source/queue.c:2352:12:xQueueIsQueueFullFromISR	32	static,ignoring_inline_asm
+../Middlewares/Third_Party/FreeRTOS/Source/queue.c:2648:7:vQueueAddToRegistry	24	static
+../Middlewares/Third_Party/FreeRTOS/Source/queue.c:2677:14:pcQueueGetName	24	static
+../Middlewares/Third_Party/FreeRTOS/Source/queue.c:2705:7:vQueueUnregisterQueue	24	static
+../Middlewares/Third_Party/FreeRTOS/Source/queue.c:2737:7:vQueueWaitForMessageRestricted	32	static
diff --git a/Debug/Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.cyclo b/Debug/Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.cyclo
new file mode 100644
index 0000000..3c2da12
--- /dev/null
+++ b/Debug/Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.cyclo
@@ -0,0 +1,22 @@
+../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c:219:23:xStreamBufferGenericCreate	7
+../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c:283:23:xStreamBufferGenericCreateStatic	10
+../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c:359:6:vStreamBufferDelete	3
+../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c:392:12:xStreamBufferReset	4
+../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c:441:12:xStreamBufferSetTriggerLevel	4
+../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c:470:8:xStreamBufferSpacesAvailable	3
+../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c:494:8:xStreamBufferBytesAvailable	2
+../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c:506:8:xStreamBufferSend	13
+../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c:610:8:xStreamBufferSendFromISR	7
+../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c:661:15:prvWriteMessageToBuffer	5
+../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c:713:8:xStreamBufferReceive	11
+../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c:817:8:xStreamBufferNextMessageLengthBytes	5
+../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c:861:8:xStreamBufferReceiveFromISR	7
+../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c:918:15:prvReadMessageFromBuffer	3
+../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c:970:12:xStreamBufferIsEmpty	3
+../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c:993:12:xStreamBufferIsFull	4
+../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c:1028:12:xStreamBufferSendCompletedFromISR	3
+../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c:1058:12:xStreamBufferReceiveCompletedFromISR	3
+../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c:1088:15:prvWriteBytesToBuffer	6
+../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c:1134:15:prvReadBytesFromBuffer	7
+../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c:1189:15:prvBytesInBuffer	2
+../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c:1209:13:prvInitialiseNewStreamBuffer	2
diff --git a/Debug/Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.d b/Debug/Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.d
new file mode 100644
index 0000000..c5439ea
--- /dev/null
+++ b/Debug/Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.d
@@ -0,0 +1,22 @@
+Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o: \
+ ../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h \
+ ../Core/Inc/FreeRTOSConfig.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/list.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/stream_buffer.h
+../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h:
+../Core/Inc/FreeRTOSConfig.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h:
+../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/task.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/list.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/stream_buffer.h:
diff --git a/Debug/Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o b/Debug/Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o
new file mode 100644
index 0000000..e627f7c
Binary files /dev/null and b/Debug/Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o differ
diff --git a/Debug/Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.su b/Debug/Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.su
new file mode 100644
index 0000000..ea54a6c
--- /dev/null
+++ b/Debug/Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.su
@@ -0,0 +1,22 @@
+../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c:219:23:xStreamBufferGenericCreate	56	static,ignoring_inline_asm
+../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c:283:23:xStreamBufferGenericCreateStatic	72	static,ignoring_inline_asm
+../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c:359:6:vStreamBufferDelete	24	static,ignoring_inline_asm
+../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c:392:12:xStreamBufferReset	40	static,ignoring_inline_asm
+../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c:441:12:xStreamBufferSetTriggerLevel	32	static,ignoring_inline_asm
+../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c:470:8:xStreamBufferSpacesAvailable	32	static,ignoring_inline_asm
+../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c:494:8:xStreamBufferBytesAvailable	32	static,ignoring_inline_asm
+../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c:506:8:xStreamBufferSend	72	static,ignoring_inline_asm
+../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c:610:8:xStreamBufferSendFromISR	72	static,ignoring_inline_asm
+../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c:661:15:prvWriteMessageToBuffer	32	static
+../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c:713:8:xStreamBufferReceive	64	static,ignoring_inline_asm
+../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c:817:8:xStreamBufferNextMessageLengthBytes	48	static,ignoring_inline_asm
+../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c:861:8:xStreamBufferReceiveFromISR	72	static,ignoring_inline_asm
+../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c:918:15:prvReadMessageFromBuffer	40	static
+../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c:970:12:xStreamBufferIsEmpty	32	static,ignoring_inline_asm
+../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c:993:12:xStreamBufferIsFull	32	static,ignoring_inline_asm
+../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c:1028:12:xStreamBufferSendCompletedFromISR	56	static,ignoring_inline_asm
+../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c:1058:12:xStreamBufferReceiveCompletedFromISR	56	static,ignoring_inline_asm
+../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c:1088:15:prvWriteBytesToBuffer	48	static,ignoring_inline_asm
+../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c:1134:15:prvReadBytesFromBuffer	48	static,ignoring_inline_asm
+../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c:1189:15:prvBytesInBuffer	24	static
+../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c:1209:13:prvInitialiseNewStreamBuffer	32	static,ignoring_inline_asm
diff --git a/Debug/Middlewares/Third_Party/FreeRTOS/Source/subdir.mk b/Debug/Middlewares/Third_Party/FreeRTOS/Source/subdir.mk
new file mode 100644
index 0000000..a12bb56
--- /dev/null
+++ b/Debug/Middlewares/Third_Party/FreeRTOS/Source/subdir.mk
@@ -0,0 +1,45 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+# Toolchain: GNU Tools for STM32 (11.3.rel1)
+################################################################################
+
+# Add inputs and outputs from these tool invocations to the build variables 
+C_SRCS += \
+../Middlewares/Third_Party/FreeRTOS/Source/croutine.c \
+../Middlewares/Third_Party/FreeRTOS/Source/event_groups.c \
+../Middlewares/Third_Party/FreeRTOS/Source/list.c \
+../Middlewares/Third_Party/FreeRTOS/Source/queue.c \
+../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c \
+../Middlewares/Third_Party/FreeRTOS/Source/tasks.c \
+../Middlewares/Third_Party/FreeRTOS/Source/timers.c 
+
+OBJS += \
+./Middlewares/Third_Party/FreeRTOS/Source/croutine.o \
+./Middlewares/Third_Party/FreeRTOS/Source/event_groups.o \
+./Middlewares/Third_Party/FreeRTOS/Source/list.o \
+./Middlewares/Third_Party/FreeRTOS/Source/queue.o \
+./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o \
+./Middlewares/Third_Party/FreeRTOS/Source/tasks.o \
+./Middlewares/Third_Party/FreeRTOS/Source/timers.o 
+
+C_DEPS += \
+./Middlewares/Third_Party/FreeRTOS/Source/croutine.d \
+./Middlewares/Third_Party/FreeRTOS/Source/event_groups.d \
+./Middlewares/Third_Party/FreeRTOS/Source/list.d \
+./Middlewares/Third_Party/FreeRTOS/Source/queue.d \
+./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.d \
+./Middlewares/Third_Party/FreeRTOS/Source/tasks.d \
+./Middlewares/Third_Party/FreeRTOS/Source/timers.d 
+
+
+# Each subdirectory must supply rules for building sources it contributes
+Middlewares/Third_Party/FreeRTOS/Source/%.o Middlewares/Third_Party/FreeRTOS/Source/%.su Middlewares/Third_Party/FreeRTOS/Source/%.cyclo: ../Middlewares/Third_Party/FreeRTOS/Source/%.c Middlewares/Third_Party/FreeRTOS/Source/subdir.mk
+	arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DDEBUG -DDATA_IN_D2_SRAM -DUSE_HAL_DRIVER -DSTM32H723xx -c -I../Core/Inc -I../FATFS/Target -I../FATFS/App -I../LWIP/App -I../LWIP/Target -I../Middlewares/Third_Party/LwIP/src/include -I../Middlewares/Third_Party/LwIP/system -I../Drivers/STM32H7xx_HAL_Driver/Inc -I../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F -I../Middlewares/Third_Party/FatFs/src -I../Drivers/BSP/Components/lan8742 -I../Middlewares/Third_Party/LwIP/src/include/netif/ppp -I../Drivers/CMSIS/Device/ST/STM32H7xx/Include -I../Middlewares/Third_Party/LwIP/src/include/lwip -I../Middlewares/Third_Party/LwIP/src/include/lwip/apps -I../Middlewares/Third_Party/LwIP/src/include/lwip/priv -I../Middlewares/Third_Party/LwIP/src/include/lwip/prot -I../Middlewares/Third_Party/LwIP/src/include/netif -I../Middlewares/Third_Party/LwIP/src/include/compat/posix -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/arpa -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/net -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/sys -I../Middlewares/Third_Party/LwIP/src/include/compat/stdc -I../Middlewares/Third_Party/LwIP/system/arch -I../Drivers/CMSIS/Include -I"C:/_NoSleep/STM32/TBD_TaxiBoard/LWFTPC" -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
+
+clean: clean-Middlewares-2f-Third_Party-2f-FreeRTOS-2f-Source
+
+clean-Middlewares-2f-Third_Party-2f-FreeRTOS-2f-Source:
+	-$(RM) ./Middlewares/Third_Party/FreeRTOS/Source/croutine.cyclo ./Middlewares/Third_Party/FreeRTOS/Source/croutine.d ./Middlewares/Third_Party/FreeRTOS/Source/croutine.o ./Middlewares/Third_Party/FreeRTOS/Source/croutine.su ./Middlewares/Third_Party/FreeRTOS/Source/event_groups.cyclo ./Middlewares/Third_Party/FreeRTOS/Source/event_groups.d ./Middlewares/Third_Party/FreeRTOS/Source/event_groups.o ./Middlewares/Third_Party/FreeRTOS/Source/event_groups.su ./Middlewares/Third_Party/FreeRTOS/Source/list.cyclo ./Middlewares/Third_Party/FreeRTOS/Source/list.d ./Middlewares/Third_Party/FreeRTOS/Source/list.o ./Middlewares/Third_Party/FreeRTOS/Source/list.su ./Middlewares/Third_Party/FreeRTOS/Source/queue.cyclo ./Middlewares/Third_Party/FreeRTOS/Source/queue.d ./Middlewares/Third_Party/FreeRTOS/Source/queue.o ./Middlewares/Third_Party/FreeRTOS/Source/queue.su ./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.cyclo ./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.d ./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o ./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.su ./Middlewares/Third_Party/FreeRTOS/Source/tasks.cyclo ./Middlewares/Third_Party/FreeRTOS/Source/tasks.d ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o ./Middlewares/Third_Party/FreeRTOS/Source/tasks.su ./Middlewares/Third_Party/FreeRTOS/Source/timers.cyclo ./Middlewares/Third_Party/FreeRTOS/Source/timers.d ./Middlewares/Third_Party/FreeRTOS/Source/timers.o ./Middlewares/Third_Party/FreeRTOS/Source/timers.su
+
+.PHONY: clean-Middlewares-2f-Third_Party-2f-FreeRTOS-2f-Source
+
diff --git a/Debug/Middlewares/Third_Party/FreeRTOS/Source/tasks.cyclo b/Debug/Middlewares/Third_Party/FreeRTOS/Source/tasks.cyclo
new file mode 100644
index 0000000..931ce56
--- /dev/null
+++ b/Debug/Middlewares/Third_Party/FreeRTOS/Source/tasks.cyclo
@@ -0,0 +1,56 @@
+../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:581:15:xTaskCreateStatic	6
+../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:733:13:xTaskCreate	4
+../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:824:13:prvInitialiseNewTask	7
+../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:1077:13:prvAddNewTaskToReadyList	7
+../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:1162:7:vTaskDelete	9
+../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:1257:7:vTaskDelayUntil	11
+../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:1341:7:vTaskDelay	4
+../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:1478:14:uxTaskPriorityGet	2
+../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:1500:14:uxTaskPriorityGetFromISR	2
+../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:1540:7:vTaskPrioritySet	14
+../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:1704:7:vTaskSuspend	11
+../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:1805:20:prvTaskIsTaskSuspended	5
+../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:1851:7:vTaskResume	6
+../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:1905:13:xTaskResumeFromISR	5
+../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:1975:6:vTaskStartScheduler	5
+../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:2099:6:vTaskEndScheduler	1
+../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:2110:6:vTaskSuspendAll	1
+../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:2194:12:xTaskResumeAll	11
+../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:2304:12:xTaskGetTickCount	1
+../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:2319:12:xTaskGetTickCountFromISR	1
+../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:2350:13:uxTaskGetNumberOfTasks	1
+../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:2358:7:pcTaskGetName	3
+../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:2609:12:xTaskCatchUpTicks	2
+../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:2707:12:xTaskIncrementTick	11
+../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:2989:6:vTaskSwitchContext	5
+../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:3064:6:vTaskPlaceOnEventList	2
+../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:3081:6:vTaskPlaceOnUnorderedEventList	3
+../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:3107:7:vTaskPlaceOnEventListRestricted	3
+../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:3138:12:xTaskRemoveFromEventList	4
+../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:3206:6:vTaskRemoveFromUnorderedEventList	4
+../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:3254:6:vTaskSetTimeOutState	2
+../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:3266:6:vTaskInternalSetTimeOutState	1
+../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:3274:12:xTaskCheckForTimeOut	7
+../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:3337:6:vTaskMissedYield	1
+../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:3392:8:prvIdleTask	2
+../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:3607:13:prvInitialiseTaskLists	2
+../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:3639:13:prvCheckTasksWaitingTermination	2
+../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:3799:32:prvTaskCheckFreeStackSpace	2
+../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:3859:14:uxTaskGetStackHighWaterMark	2
+../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:3887:14:prvDeleteTCB	4
+../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:3943:13:prvResetNextTaskUnblockTime	2
+../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:3969:15:xTaskGetCurrentTaskHandle	1
+../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:3986:13:xTaskGetSchedulerState	3
+../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:4014:13:xTaskPriorityInherit	7
+../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:4104:13:xTaskPriorityDisinherit	8
+../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:4184:7:vTaskPriorityDisinheritAfterTimeout	10
+../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:4602:12:uxTaskResetEventItemValue	1
+../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:4618:15:pvTaskIncrementMutexHeldCount	2
+../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:4635:11:ulTaskNotifyTake	5
+../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:4703:13:xTaskNotifyWait	5
+../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:4783:13:xTaskGenericNotify	13
+../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:4897:13:xTaskGenericNotifyFromISR	15
+../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:5026:7:vTaskNotifyGiveFromISR	7
+../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:5112:13:xTaskNotifyStateClear	3
+../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:5143:11:ulTaskNotifyValueClear	2
+../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:5177:13:prvAddCurrentTaskToDelayedList	6
diff --git a/Debug/Middlewares/Third_Party/FreeRTOS/Source/tasks.d b/Debug/Middlewares/Third_Party/FreeRTOS/Source/tasks.d
new file mode 100644
index 0000000..953067b
--- /dev/null
+++ b/Debug/Middlewares/Third_Party/FreeRTOS/Source/tasks.d
@@ -0,0 +1,26 @@
+Middlewares/Third_Party/FreeRTOS/Source/tasks.o: \
+ ../Middlewares/Third_Party/FreeRTOS/Source/tasks.c \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h \
+ ../Core/Inc/FreeRTOSConfig.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/list.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/stack_macros.h
+../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h:
+../Core/Inc/FreeRTOSConfig.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h:
+../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/task.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/list.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/task.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/stack_macros.h:
diff --git a/Debug/Middlewares/Third_Party/FreeRTOS/Source/tasks.o b/Debug/Middlewares/Third_Party/FreeRTOS/Source/tasks.o
new file mode 100644
index 0000000..6b9d868
Binary files /dev/null and b/Debug/Middlewares/Third_Party/FreeRTOS/Source/tasks.o differ
diff --git a/Debug/Middlewares/Third_Party/FreeRTOS/Source/tasks.su b/Debug/Middlewares/Third_Party/FreeRTOS/Source/tasks.su
new file mode 100644
index 0000000..570bd94
--- /dev/null
+++ b/Debug/Middlewares/Third_Party/FreeRTOS/Source/tasks.su
@@ -0,0 +1,56 @@
+../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:581:15:xTaskCreateStatic	64	static,ignoring_inline_asm
+../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:733:13:xTaskCreate	56	static
+../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:824:13:prvInitialiseNewTask	40	static,ignoring_inline_asm
+../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:1077:13:prvAddNewTaskToReadyList	16	static,ignoring_inline_asm
+../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:1162:7:vTaskDelete	24	static,ignoring_inline_asm
+../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:1257:7:vTaskDelayUntil	48	static,ignoring_inline_asm
+../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:1341:7:vTaskDelay	24	static,ignoring_inline_asm
+../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:1478:14:uxTaskPriorityGet	24	static
+../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:1500:14:uxTaskPriorityGetFromISR	40	static,ignoring_inline_asm
+../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:1540:7:vTaskPrioritySet	40	static,ignoring_inline_asm
+../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:1704:7:vTaskSuspend	24	static,ignoring_inline_asm
+../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:1805:20:prvTaskIsTaskSuspended	32	static,ignoring_inline_asm
+../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:1851:7:vTaskResume	24	static,ignoring_inline_asm
+../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:1905:13:xTaskResumeFromISR	48	static,ignoring_inline_asm
+../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:1975:6:vTaskStartScheduler	48	static,ignoring_inline_asm
+../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:2099:6:vTaskEndScheduler	16	static,ignoring_inline_asm
+../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:2110:6:vTaskSuspendAll	4	static,ignoring_inline_asm
+../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:2194:12:xTaskResumeAll	24	static,ignoring_inline_asm
+../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:2304:12:xTaskGetTickCount	16	static
+../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:2319:12:xTaskGetTickCountFromISR	16	static
+../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:2350:13:uxTaskGetNumberOfTasks	4	static
+../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:2358:7:pcTaskGetName	24	static,ignoring_inline_asm
+../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:2609:12:xTaskCatchUpTicks	24	static,ignoring_inline_asm
+../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:2707:12:xTaskIncrementTick	32	static,ignoring_inline_asm
+../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:2989:6:vTaskSwitchContext	32	static,ignoring_inline_asm
+../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:3064:6:vTaskPlaceOnEventList	24	static,ignoring_inline_asm
+../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:3081:6:vTaskPlaceOnUnorderedEventList	32	static,ignoring_inline_asm
+../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:3107:7:vTaskPlaceOnEventListRestricted	32	static,ignoring_inline_asm
+../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:3138:12:xTaskRemoveFromEventList	32	static,ignoring_inline_asm
+../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:3206:6:vTaskRemoveFromUnorderedEventList	32	static,ignoring_inline_asm
+../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:3254:6:vTaskSetTimeOutState	24	static,ignoring_inline_asm
+../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:3266:6:vTaskInternalSetTimeOutState	16	static
+../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:3274:12:xTaskCheckForTimeOut	40	static,ignoring_inline_asm
+../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:3337:6:vTaskMissedYield	4	static
+../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:3392:8:prvIdleTask	16	static,ignoring_inline_asm
+../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:3607:13:prvInitialiseTaskLists	16	static
+../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:3639:13:prvCheckTasksWaitingTermination	16	static
+../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:3799:32:prvTaskCheckFreeStackSpace	24	static
+../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:3859:14:uxTaskGetStackHighWaterMark	32	static
+../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:3887:14:prvDeleteTCB	24	static,ignoring_inline_asm
+../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:3943:13:prvResetNextTaskUnblockTime	16	static
+../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:3969:15:xTaskGetCurrentTaskHandle	16	static
+../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:3986:13:xTaskGetSchedulerState	16	static
+../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:4014:13:xTaskPriorityInherit	24	static
+../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:4104:13:xTaskPriorityDisinherit	32	static,ignoring_inline_asm
+../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:4184:7:vTaskPriorityDisinheritAfterTimeout	40	static,ignoring_inline_asm
+../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:4602:12:uxTaskResetEventItemValue	16	static
+../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:4618:15:pvTaskIncrementMutexHeldCount	4	static
+../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:4635:11:ulTaskNotifyTake	24	static,ignoring_inline_asm
+../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:4703:13:xTaskNotifyWait	32	static,ignoring_inline_asm
+../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:4783:13:xTaskGenericNotify	48	static,ignoring_inline_asm
+../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:4897:13:xTaskGenericNotifyFromISR	64	static,ignoring_inline_asm
+../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:5026:7:vTaskNotifyGiveFromISR	48	static,ignoring_inline_asm
+../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:5112:13:xTaskNotifyStateClear	24	static
+../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:5143:11:ulTaskNotifyValueClear	24	static
+../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:5177:13:prvAddCurrentTaskToDelayedList	24	static
diff --git a/Debug/Middlewares/Third_Party/FreeRTOS/Source/timers.cyclo b/Debug/Middlewares/Third_Party/FreeRTOS/Source/timers.cyclo
new file mode 100644
index 0000000..c399a08
--- /dev/null
+++ b/Debug/Middlewares/Third_Party/FreeRTOS/Source/timers.cyclo
@@ -0,0 +1,23 @@
+../Middlewares/Third_Party/FreeRTOS/Source/timers.c:227:12:xTimerCreateTimerTask	4
+../Middlewares/Third_Party/FreeRTOS/Source/timers.c:282:16:xTimerCreate	2
+../Middlewares/Third_Party/FreeRTOS/Source/timers.c:309:16:xTimerCreateStatic	4
+../Middlewares/Third_Party/FreeRTOS/Source/timers.c:349:13:prvInitialiseNewTimer	4
+../Middlewares/Third_Party/FreeRTOS/Source/timers.c:381:12:xTimerGenericCommand	5
+../Middlewares/Third_Party/FreeRTOS/Source/timers.c:424:14:xTimerGetTimerDaemonTaskHandle	2
+../Middlewares/Third_Party/FreeRTOS/Source/timers.c:433:12:xTimerGetPeriod	2
+../Middlewares/Third_Party/FreeRTOS/Source/timers.c:442:6:vTimerSetReloadMode	3
+../Middlewares/Third_Party/FreeRTOS/Source/timers.c:462:13:uxTimerGetReloadMode	3
+../Middlewares/Third_Party/FreeRTOS/Source/timers.c:487:12:xTimerGetExpiryTime	2
+../Middlewares/Third_Party/FreeRTOS/Source/timers.c:498:14:pcTimerGetName	2
+../Middlewares/Third_Party/FreeRTOS/Source/timers.c:507:13:prvProcessExpiredTimer	4
+../Middlewares/Third_Party/FreeRTOS/Source/timers.c:548:8:prvTimerTask	1
+../Middlewares/Third_Party/FreeRTOS/Source/timers.c:584:13:prvProcessTimerOrBlockTask	7
+../Middlewares/Third_Party/FreeRTOS/Source/timers.c:644:19:prvGetNextExpireTime	3
+../Middlewares/Third_Party/FreeRTOS/Source/timers.c:670:19:prvSampleTimeNow	2
+../Middlewares/Third_Party/FreeRTOS/Source/timers.c:693:19:prvInsertTimerInActiveList	5
+../Middlewares/Third_Party/FreeRTOS/Source/timers.c:734:13:prvProcessReceivedCommands	13
+../Middlewares/Third_Party/FreeRTOS/Source/timers.c:882:13:prvSwitchTimerLists	5
+../Middlewares/Third_Party/FreeRTOS/Source/timers.c:941:13:prvCheckForValidListAndQueue	3
+../Middlewares/Third_Party/FreeRTOS/Source/timers.c:992:12:xTimerIsTimerActive	3
+../Middlewares/Third_Party/FreeRTOS/Source/timers.c:1017:7:pvTimerGetTimerID	2
+../Middlewares/Third_Party/FreeRTOS/Source/timers.c:1034:6:vTimerSetTimerID	2
diff --git a/Debug/Middlewares/Third_Party/FreeRTOS/Source/timers.d b/Debug/Middlewares/Third_Party/FreeRTOS/Source/timers.d
new file mode 100644
index 0000000..221036f
--- /dev/null
+++ b/Debug/Middlewares/Third_Party/FreeRTOS/Source/timers.d
@@ -0,0 +1,26 @@
+Middlewares/Third_Party/FreeRTOS/Source/timers.o: \
+ ../Middlewares/Third_Party/FreeRTOS/Source/timers.c \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h \
+ ../Core/Inc/FreeRTOSConfig.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/list.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h
+../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h:
+../Core/Inc/FreeRTOSConfig.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h:
+../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/task.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/list.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/task.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h:
diff --git a/Debug/Middlewares/Third_Party/FreeRTOS/Source/timers.o b/Debug/Middlewares/Third_Party/FreeRTOS/Source/timers.o
new file mode 100644
index 0000000..128f07a
Binary files /dev/null and b/Debug/Middlewares/Third_Party/FreeRTOS/Source/timers.o differ
diff --git a/Debug/Middlewares/Third_Party/FreeRTOS/Source/timers.su b/Debug/Middlewares/Third_Party/FreeRTOS/Source/timers.su
new file mode 100644
index 0000000..aef1688
--- /dev/null
+++ b/Debug/Middlewares/Third_Party/FreeRTOS/Source/timers.su
@@ -0,0 +1,23 @@
+../Middlewares/Third_Party/FreeRTOS/Source/timers.c:227:12:xTimerCreateTimerTask	48	static,ignoring_inline_asm
+../Middlewares/Third_Party/FreeRTOS/Source/timers.c:282:16:xTimerCreate	40	static
+../Middlewares/Third_Party/FreeRTOS/Source/timers.c:309:16:xTimerCreateStatic	48	static,ignoring_inline_asm
+../Middlewares/Third_Party/FreeRTOS/Source/timers.c:349:13:prvInitialiseNewTimer	32	static,ignoring_inline_asm
+../Middlewares/Third_Party/FreeRTOS/Source/timers.c:381:12:xTimerGenericCommand	48	static,ignoring_inline_asm
+../Middlewares/Third_Party/FreeRTOS/Source/timers.c:424:14:xTimerGetTimerDaemonTaskHandle	16	static,ignoring_inline_asm
+../Middlewares/Third_Party/FreeRTOS/Source/timers.c:433:12:xTimerGetPeriod	24	static,ignoring_inline_asm
+../Middlewares/Third_Party/FreeRTOS/Source/timers.c:442:6:vTimerSetReloadMode	24	static,ignoring_inline_asm
+../Middlewares/Third_Party/FreeRTOS/Source/timers.c:462:13:uxTimerGetReloadMode	32	static,ignoring_inline_asm
+../Middlewares/Third_Party/FreeRTOS/Source/timers.c:487:12:xTimerGetExpiryTime	32	static,ignoring_inline_asm
+../Middlewares/Third_Party/FreeRTOS/Source/timers.c:498:14:pcTimerGetName	24	static,ignoring_inline_asm
+../Middlewares/Third_Party/FreeRTOS/Source/timers.c:507:13:prvProcessExpiredTimer	40	static,ignoring_inline_asm
+../Middlewares/Third_Party/FreeRTOS/Source/timers.c:548:8:prvTimerTask	24	static
+../Middlewares/Third_Party/FreeRTOS/Source/timers.c:584:13:prvProcessTimerOrBlockTask	24	static,ignoring_inline_asm
+../Middlewares/Third_Party/FreeRTOS/Source/timers.c:644:19:prvGetNextExpireTime	24	static
+../Middlewares/Third_Party/FreeRTOS/Source/timers.c:670:19:prvSampleTimeNow	24	static
+../Middlewares/Third_Party/FreeRTOS/Source/timers.c:693:19:prvInsertTimerInActiveList	32	static
+../Middlewares/Third_Party/FreeRTOS/Source/timers.c:734:13:prvProcessReceivedCommands	56	static,ignoring_inline_asm
+../Middlewares/Third_Party/FreeRTOS/Source/timers.c:882:13:prvSwitchTimerLists	40	static,ignoring_inline_asm
+../Middlewares/Third_Party/FreeRTOS/Source/timers.c:941:13:prvCheckForValidListAndQueue	16	static
+../Middlewares/Third_Party/FreeRTOS/Source/timers.c:992:12:xTimerIsTimerActive	32	static,ignoring_inline_asm
+../Middlewares/Third_Party/FreeRTOS/Source/timers.c:1017:7:pvTimerGetTimerID	32	static,ignoring_inline_asm
+../Middlewares/Third_Party/FreeRTOS/Source/timers.c:1034:6:vTimerSetTimerID	24	static,ignoring_inline_asm
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/api/api_lib.cyclo b/Debug/Middlewares/Third_Party/LwIP/src/api/api_lib.cyclo
index e69de29..0fb9b59 100644
--- a/Debug/Middlewares/Third_Party/LwIP/src/api/api_lib.cyclo
+++ b/Debug/Middlewares/Third_Party/LwIP/src/api/api_lib.cyclo
@@ -0,0 +1,28 @@
+../Middlewares/Third_Party/LwIP/src/api/api_lib.c:118:1:netconn_apimsg	2
+../Middlewares/Third_Party/LwIP/src/api/api_lib.c:149:1:netconn_new_with_proto_and_callback	7
+../Middlewares/Third_Party/LwIP/src/api/api_lib.c:192:1:netconn_prepare_delete	3
+../Middlewares/Third_Party/LwIP/src/api/api_lib.c:233:1:netconn_delete	3
+../Middlewares/Third_Party/LwIP/src/api/api_lib.c:269:1:netconn_getaddr	4
+../Middlewares/Third_Party/LwIP/src/api/api_lib.c:307:1:netconn_bind	3
+../Middlewares/Third_Party/LwIP/src/api/api_lib.c:351:1:netconn_bind_if	2
+../Middlewares/Third_Party/LwIP/src/api/api_lib.c:377:1:netconn_connect	3
+../Middlewares/Third_Party/LwIP/src/api/api_lib.c:409:1:netconn_disconnect	2
+../Middlewares/Third_Party/LwIP/src/api/api_lib.c:434:1:netconn_listen_with_backlog	2
+../Middlewares/Third_Party/LwIP/src/api/api_lib.c:471:1:netconn_accept	11
+../Middlewares/Third_Party/LwIP/src/api/api_lib.c:579:1:netconn_recv_data	17
+../Middlewares/Third_Party/LwIP/src/api/api_lib.c:677:1:netconn_tcp_recvd_msg	3
+../Middlewares/Third_Party/LwIP/src/api/api_lib.c:689:1:netconn_tcp_recvd	3
+../Middlewares/Third_Party/LwIP/src/api/api_lib.c:703:1:netconn_recv_data_tcp	11
+../Middlewares/Third_Party/LwIP/src/api/api_lib.c:782:1:netconn_recv_tcp_pbuf	3
+../Middlewares/Third_Party/LwIP/src/api/api_lib.c:803:1:netconn_recv_tcp_pbuf_flags	3
+../Middlewares/Third_Party/LwIP/src/api/api_lib.c:822:1:netconn_recv_udp_raw_netbuf	3
+../Middlewares/Third_Party/LwIP/src/api/api_lib.c:842:1:netconn_recv_udp_raw_netbuf_flags	3
+../Middlewares/Third_Party/LwIP/src/api/api_lib.c:860:1:netconn_recv	7
+../Middlewares/Third_Party/LwIP/src/api/api_lib.c:922:1:netconn_sendto	3
+../Middlewares/Third_Party/LwIP/src/api/api_lib.c:941:1:netconn_send	2
+../Middlewares/Third_Party/LwIP/src/api/api_lib.c:974:1:netconn_write_partly	1
+../Middlewares/Third_Party/LwIP/src/api/api_lib.c:997:1:netconn_write_vectors_partly	16
+../Middlewares/Third_Party/LwIP/src/api/api_lib.c:1089:1:netconn_close_shutdown	2
+../Middlewares/Third_Party/LwIP/src/api/api_lib.c:1125:1:netconn_close	1
+../Middlewares/Third_Party/LwIP/src/api/api_lib.c:1139:1:netconn_err	2
+../Middlewares/Third_Party/LwIP/src/api/api_lib.c:1163:1:netconn_shutdown	3
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/api/api_lib.d b/Debug/Middlewares/Third_Party/LwIP/src/api/api_lib.d
index 2cd56d6..509d35a 100644
--- a/Debug/Middlewares/Third_Party/LwIP/src/api/api_lib.d
+++ b/Debug/Middlewares/Third_Party/LwIP/src/api/api_lib.d
@@ -25,6 +25,7 @@ Middlewares/Third_Party/LwIP/src/api/api_lib.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
@@ -32,10 +33,72 @@ Middlewares/Third_Party/LwIP/src/api/api_lib.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \
  ../Middlewares/Third_Party/LwIP/system/arch/cc.h \
- ../Middlewares/Third_Party/LwIP/system/arch/cpu.h
+ ../Middlewares/Third_Party/LwIP/system/arch/cpu.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/api.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/netbuf.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/err.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/sys.h \
+ ../Middlewares/Third_Party/LwIP/system/arch/sys_arch.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h \
+ ../Core/Inc/FreeRTOSConfig.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/list.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/ip.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/netif.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip4.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/ip6.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/raw.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/udp.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/udp.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/api_msg.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/igmp.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/tcpip_priv.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/tcpip.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/timeouts.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/tcp_priv.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/tcp.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/tcpbase.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/icmp.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/icmp.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/tcp.h
 ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h:
 ../LWIP/Target/lwipopts.h:
 ../Core/Inc/main.h:
@@ -62,6 +125,7 @@ Middlewares/Third_Party/LwIP/src/api/api_lib.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
@@ -69,7 +133,69 @@ Middlewares/Third_Party/LwIP/src/api/api_lib.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h:
 ../Middlewares/Third_Party/LwIP/system/arch/cc.h:
 ../Middlewares/Third_Party/LwIP/system/arch/cpu.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/api.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/netbuf.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/err.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/def.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/def.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/sys.h:
+../Middlewares/Third_Party/LwIP/system/arch/sys_arch.h:
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h:
+../Core/Inc/FreeRTOSConfig.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h:
+../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/task.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/list.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/task.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/ip.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/netif.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/ip4.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip4.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/ip6.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/raw.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/udp.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/prot/udp.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/priv/api_msg.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/igmp.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/priv/tcpip_priv.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/tcpip.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/timeouts.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/priv/tcp_priv.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/tcp.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/tcpbase.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/icmp.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/prot/icmp.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/prot/tcp.h:
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/api/api_lib.o b/Debug/Middlewares/Third_Party/LwIP/src/api/api_lib.o
index bee5e94..8327e83 100644
Binary files a/Debug/Middlewares/Third_Party/LwIP/src/api/api_lib.o and b/Debug/Middlewares/Third_Party/LwIP/src/api/api_lib.o differ
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/api/api_lib.su b/Debug/Middlewares/Third_Party/LwIP/src/api/api_lib.su
index e69de29..49ce174 100644
--- a/Debug/Middlewares/Third_Party/LwIP/src/api/api_lib.su
+++ b/Debug/Middlewares/Third_Party/LwIP/src/api/api_lib.su
@@ -0,0 +1,28 @@
+../Middlewares/Third_Party/LwIP/src/api/api_lib.c:118:1:netconn_apimsg	24	static
+../Middlewares/Third_Party/LwIP/src/api/api_lib.c:149:1:netconn_new_with_proto_and_callback	56	static
+../Middlewares/Third_Party/LwIP/src/api/api_lib.c:192:1:netconn_prepare_delete	56	static
+../Middlewares/Third_Party/LwIP/src/api/api_lib.c:233:1:netconn_delete	24	static
+../Middlewares/Third_Party/LwIP/src/api/api_lib.c:269:1:netconn_getaddr	64	static
+../Middlewares/Third_Party/LwIP/src/api/api_lib.c:307:1:netconn_bind	64	static
+../Middlewares/Third_Party/LwIP/src/api/api_lib.c:351:1:netconn_bind_if	56	static
+../Middlewares/Third_Party/LwIP/src/api/api_lib.c:377:1:netconn_connect	64	static
+../Middlewares/Third_Party/LwIP/src/api/api_lib.c:409:1:netconn_disconnect	56	static
+../Middlewares/Third_Party/LwIP/src/api/api_lib.c:434:1:netconn_listen_with_backlog	56	static
+../Middlewares/Third_Party/LwIP/src/api/api_lib.c:471:1:netconn_accept	32	static
+../Middlewares/Third_Party/LwIP/src/api/api_lib.c:579:1:netconn_recv_data	40	static
+../Middlewares/Third_Party/LwIP/src/api/api_lib.c:677:1:netconn_tcp_recvd_msg	24	static
+../Middlewares/Third_Party/LwIP/src/api/api_lib.c:689:1:netconn_tcp_recvd	56	static
+../Middlewares/Third_Party/LwIP/src/api/api_lib.c:703:1:netconn_recv_data_tcp	72	static
+../Middlewares/Third_Party/LwIP/src/api/api_lib.c:782:1:netconn_recv_tcp_pbuf	16	static
+../Middlewares/Third_Party/LwIP/src/api/api_lib.c:803:1:netconn_recv_tcp_pbuf_flags	24	static
+../Middlewares/Third_Party/LwIP/src/api/api_lib.c:822:1:netconn_recv_udp_raw_netbuf	16	static
+../Middlewares/Third_Party/LwIP/src/api/api_lib.c:842:1:netconn_recv_udp_raw_netbuf_flags	24	static
+../Middlewares/Third_Party/LwIP/src/api/api_lib.c:860:1:netconn_recv	32	static
+../Middlewares/Third_Party/LwIP/src/api/api_lib.c:922:1:netconn_sendto	24	static
+../Middlewares/Third_Party/LwIP/src/api/api_lib.c:941:1:netconn_send	56	static
+../Middlewares/Third_Party/LwIP/src/api/api_lib.c:974:1:netconn_write_partly	40	static
+../Middlewares/Third_Party/LwIP/src/api/api_lib.c:997:1:netconn_write_vectors_partly	80	static
+../Middlewares/Third_Party/LwIP/src/api/api_lib.c:1089:1:netconn_close_shutdown	56	static
+../Middlewares/Third_Party/LwIP/src/api/api_lib.c:1125:1:netconn_close	16	static
+../Middlewares/Third_Party/LwIP/src/api/api_lib.c:1139:1:netconn_err	24	static
+../Middlewares/Third_Party/LwIP/src/api/api_lib.c:1163:1:netconn_shutdown	16	static
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/api/api_msg.cyclo b/Debug/Middlewares/Third_Party/LwIP/src/api/api_msg.cyclo
index e69de29..63862a1 100644
--- a/Debug/Middlewares/Third_Party/LwIP/src/api/api_msg.cyclo
+++ b/Debug/Middlewares/Third_Party/LwIP/src/api/api_msg.cyclo
@@ -0,0 +1,28 @@
+../Middlewares/Third_Party/LwIP/src/api/api_msg.c:115:1:lwip_netconn_err_to_msg	6
+../Middlewares/Third_Party/LwIP/src/api/api_msg.c:131:1:lwip_netconn_is_err_msg	5
+../Middlewares/Third_Party/LwIP/src/api/api_msg.c:218:1:recv_udp	10
+../Middlewares/Third_Party/LwIP/src/api/api_msg.c:293:1:recv_tcp	11
+../Middlewares/Third_Party/LwIP/src/api/api_msg.c:357:1:poll_tcp	11
+../Middlewares/Third_Party/LwIP/src/api/api_msg.c:398:1:sent_tcp	9
+../Middlewares/Third_Party/LwIP/src/api/api_msg.c:432:1:err_tcp	15
+../Middlewares/Third_Party/LwIP/src/api/api_msg.c:514:1:setup_tcp	1
+../Middlewares/Third_Party/LwIP/src/api/api_msg.c:533:1:accept_function	12
+../Middlewares/Third_Party/LwIP/src/api/api_msg.c:609:1:pcb_new	8
+../Middlewares/Third_Party/LwIP/src/api/api_msg.c:680:1:lwip_netconn_do_newconn	2
+../Middlewares/Third_Party/LwIP/src/api/api_msg.c:705:1:netconn_alloc	6
+../Middlewares/Third_Party/LwIP/src/api/api_msg.c:794:1:netconn_free	4
+../Middlewares/Third_Party/LwIP/src/api/api_msg.c:827:1:netconn_drain	9
+../Middlewares/Third_Party/LwIP/src/api/api_msg.c:920:1:lwip_netconn_do_close_internal	36
+../Middlewares/Third_Party/LwIP/src/api/api_msg.c:1113:1:lwip_netconn_do_delconn	19
+../Middlewares/Third_Party/LwIP/src/api/api_msg.c:1216:1:lwip_netconn_do_bind	4
+../Middlewares/Third_Party/LwIP/src/api/api_msg.c:1256:1:lwip_netconn_do_bind_if	5
+../Middlewares/Third_Party/LwIP/src/api/api_msg.c:1301:1:lwip_netconn_do_connected	14
+../Middlewares/Third_Party/LwIP/src/api/api_msg.c:1350:1:lwip_netconn_do_connect	11
+../Middlewares/Third_Party/LwIP/src/api/api_msg.c:1425:1:lwip_netconn_do_disconnect	2
+../Middlewares/Third_Party/LwIP/src/api/api_msg.c:1449:1:lwip_netconn_do_listen	10
+../Middlewares/Third_Party/LwIP/src/api/api_msg.c:1532:1:lwip_netconn_do_send	5
+../Middlewares/Third_Party/LwIP/src/api/api_msg.c:1589:1:lwip_netconn_do_recv	5
+../Middlewares/Third_Party/LwIP/src/api/api_msg.c:1640:1:lwip_netconn_do_writemore	42
+../Middlewares/Third_Party/LwIP/src/api/api_msg.c:1813:1:lwip_netconn_do_write	10
+../Middlewares/Third_Party/LwIP/src/api/api_msg.c:1867:1:lwip_netconn_do_getaddr	11
+../Middlewares/Third_Party/LwIP/src/api/api_msg.c:1934:1:lwip_netconn_do_close	12
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/api/api_msg.d b/Debug/Middlewares/Third_Party/LwIP/src/api/api_msg.d
index decb0a2..ed06c05 100644
--- a/Debug/Middlewares/Third_Party/LwIP/src/api/api_msg.d
+++ b/Debug/Middlewares/Third_Party/LwIP/src/api/api_msg.d
@@ -25,6 +25,7 @@ Middlewares/Third_Party/LwIP/src/api/api_msg.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
@@ -32,10 +33,72 @@ Middlewares/Third_Party/LwIP/src/api/api_msg.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \
  ../Middlewares/Third_Party/LwIP/system/arch/cc.h \
- ../Middlewares/Third_Party/LwIP/system/arch/cpu.h
+ ../Middlewares/Third_Party/LwIP/system/arch/cpu.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/api_msg.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/err.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/sys.h \
+ ../Middlewares/Third_Party/LwIP/system/arch/sys_arch.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h \
+ ../Core/Inc/FreeRTOSConfig.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/list.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/igmp.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/netif.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/api.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/netbuf.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/tcpip_priv.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/tcpip.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/timeouts.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/ip.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip4.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/ip6.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/udp.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/udp.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/tcp.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/tcpbase.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/icmp.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/icmp.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/raw.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/dns.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/mld6.h
 ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h:
 ../LWIP/Target/lwipopts.h:
 ../Core/Inc/main.h:
@@ -62,6 +125,7 @@ Middlewares/Third_Party/LwIP/src/api/api_msg.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
@@ -69,7 +133,69 @@ Middlewares/Third_Party/LwIP/src/api/api_msg.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h:
 ../Middlewares/Third_Party/LwIP/system/arch/cc.h:
 ../Middlewares/Third_Party/LwIP/system/arch/cpu.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/priv/api_msg.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/def.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/def.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/err.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/sys.h:
+../Middlewares/Third_Party/LwIP/system/arch/sys_arch.h:
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h:
+../Core/Inc/FreeRTOSConfig.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h:
+../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/task.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/list.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/task.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/igmp.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/netif.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/api.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/netbuf.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/priv/tcpip_priv.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/tcpip.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/timeouts.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/ip.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/ip4.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip4.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/ip6.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/udp.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/prot/udp.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/tcp.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/tcpbase.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/icmp.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/prot/icmp.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/raw.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/dns.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/mld6.h:
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/api/api_msg.o b/Debug/Middlewares/Third_Party/LwIP/src/api/api_msg.o
index 6e28aec..905f88c 100644
Binary files a/Debug/Middlewares/Third_Party/LwIP/src/api/api_msg.o and b/Debug/Middlewares/Third_Party/LwIP/src/api/api_msg.o differ
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/api/api_msg.su b/Debug/Middlewares/Third_Party/LwIP/src/api/api_msg.su
index e69de29..bd92c74 100644
--- a/Debug/Middlewares/Third_Party/LwIP/src/api/api_msg.su
+++ b/Debug/Middlewares/Third_Party/LwIP/src/api/api_msg.su
@@ -0,0 +1,28 @@
+../Middlewares/Third_Party/LwIP/src/api/api_msg.c:115:1:lwip_netconn_err_to_msg	16	static
+../Middlewares/Third_Party/LwIP/src/api/api_msg.c:131:1:lwip_netconn_is_err_msg	16	static
+../Middlewares/Third_Party/LwIP/src/api/api_msg.c:218:1:recv_udp	40	static
+../Middlewares/Third_Party/LwIP/src/api/api_msg.c:293:1:recv_tcp	40	static
+../Middlewares/Third_Party/LwIP/src/api/api_msg.c:357:1:poll_tcp	24	static
+../Middlewares/Third_Party/LwIP/src/api/api_msg.c:398:1:sent_tcp	32	static
+../Middlewares/Third_Party/LwIP/src/api/api_msg.c:432:1:err_tcp	40	static
+../Middlewares/Third_Party/LwIP/src/api/api_msg.c:514:1:setup_tcp	24	static
+../Middlewares/Third_Party/LwIP/src/api/api_msg.c:533:1:accept_function	48	static
+../Middlewares/Third_Party/LwIP/src/api/api_msg.c:609:1:pcb_new	32	static
+../Middlewares/Third_Party/LwIP/src/api/api_msg.c:680:1:lwip_netconn_do_newconn	24	static
+../Middlewares/Third_Party/LwIP/src/api/api_msg.c:705:1:netconn_alloc	32	static
+../Middlewares/Third_Party/LwIP/src/api/api_msg.c:794:1:netconn_free	16	static
+../Middlewares/Third_Party/LwIP/src/api/api_msg.c:827:1:netconn_drain	32	static
+../Middlewares/Third_Party/LwIP/src/api/api_msg.c:920:1:lwip_netconn_do_close_internal	32	static
+../Middlewares/Third_Party/LwIP/src/api/api_msg.c:1113:1:lwip_netconn_do_delconn	24	static
+../Middlewares/Third_Party/LwIP/src/api/api_msg.c:1216:1:lwip_netconn_do_bind	24	static
+../Middlewares/Third_Party/LwIP/src/api/api_msg.c:1256:1:lwip_netconn_do_bind_if	32	static
+../Middlewares/Third_Party/LwIP/src/api/api_msg.c:1301:1:lwip_netconn_do_connected	40	static
+../Middlewares/Third_Party/LwIP/src/api/api_msg.c:1350:1:lwip_netconn_do_connect	32	static
+../Middlewares/Third_Party/LwIP/src/api/api_msg.c:1425:1:lwip_netconn_do_disconnect	24	static
+../Middlewares/Third_Party/LwIP/src/api/api_msg.c:1449:1:lwip_netconn_do_listen	32	static
+../Middlewares/Third_Party/LwIP/src/api/api_msg.c:1532:1:lwip_netconn_do_send	24	static
+../Middlewares/Third_Party/LwIP/src/api/api_msg.c:1589:1:lwip_netconn_do_recv	32	static
+../Middlewares/Third_Party/LwIP/src/api/api_msg.c:1640:1:lwip_netconn_do_writemore	40	static
+../Middlewares/Third_Party/LwIP/src/api/api_msg.c:1813:1:lwip_netconn_do_write	24	static
+../Middlewares/Third_Party/LwIP/src/api/api_msg.c:1867:1:lwip_netconn_do_getaddr	24	static
+../Middlewares/Third_Party/LwIP/src/api/api_msg.c:1934:1:lwip_netconn_do_close	24	static
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/api/err.cyclo b/Debug/Middlewares/Third_Party/LwIP/src/api/err.cyclo
index 101b8a9..197ab2c 100644
--- a/Debug/Middlewares/Third_Party/LwIP/src/api/err.cyclo
+++ b/Debug/Middlewares/Third_Party/LwIP/src/api/err.cyclo
@@ -1 +1,2 @@
+../Middlewares/Third_Party/LwIP/src/api/err.c:69:1:err_to_errno	3
 ../Middlewares/Third_Party/LwIP/src/api/err.c:107:1:lwip_strerr	3
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/api/err.d b/Debug/Middlewares/Third_Party/LwIP/src/api/err.d
index e0db62c..f524fca 100644
--- a/Debug/Middlewares/Third_Party/LwIP/src/api/err.d
+++ b/Debug/Middlewares/Third_Party/LwIP/src/api/err.d
@@ -26,6 +26,7 @@ Middlewares/Third_Party/LwIP/src/api/err.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
@@ -33,12 +34,38 @@ Middlewares/Third_Party/LwIP/src/api/err.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \
  ../Middlewares/Third_Party/LwIP/system/arch/cc.h \
  ../Middlewares/Third_Party/LwIP/system/arch/cpu.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/sys.h \
+ ../Middlewares/Third_Party/LwIP/system/arch/sys_arch.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h \
+ ../Core/Inc/FreeRTOSConfig.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/list.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/errno.h
 ../Middlewares/Third_Party/LwIP/src/include/lwip/err.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h:
@@ -67,6 +94,7 @@ Middlewares/Third_Party/LwIP/src/api/err.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
@@ -74,10 +102,36 @@ Middlewares/Third_Party/LwIP/src/api/err.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h:
 ../Middlewares/Third_Party/LwIP/system/arch/cc.h:
 ../Middlewares/Third_Party/LwIP/system/arch/cpu.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/sys.h:
+../Middlewares/Third_Party/LwIP/system/arch/sys_arch.h:
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h:
+../Core/Inc/FreeRTOSConfig.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h:
+../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/task.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/list.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/task.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/errno.h:
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/api/err.o b/Debug/Middlewares/Third_Party/LwIP/src/api/err.o
index bd9999e..ce912f5 100644
Binary files a/Debug/Middlewares/Third_Party/LwIP/src/api/err.o and b/Debug/Middlewares/Third_Party/LwIP/src/api/err.o differ
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/api/err.su b/Debug/Middlewares/Third_Party/LwIP/src/api/err.su
index 2da5ed9..f127e4f 100644
--- a/Debug/Middlewares/Third_Party/LwIP/src/api/err.su
+++ b/Debug/Middlewares/Third_Party/LwIP/src/api/err.su
@@ -1 +1,2 @@
+../Middlewares/Third_Party/LwIP/src/api/err.c:69:1:err_to_errno	16	static
 ../Middlewares/Third_Party/LwIP/src/api/err.c:107:1:lwip_strerr	16	static
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/api/if_api.cyclo b/Debug/Middlewares/Third_Party/LwIP/src/api/if_api.cyclo
index e69de29..6aee94c 100644
--- a/Debug/Middlewares/Third_Party/LwIP/src/api/if_api.cyclo
+++ b/Debug/Middlewares/Third_Party/LwIP/src/api/if_api.cyclo
@@ -0,0 +1,2 @@
+../Middlewares/Third_Party/LwIP/src/api/if_api.c:61:1:lwip_if_indextoname	1
+../Middlewares/Third_Party/LwIP/src/api/if_api.c:86:1:lwip_if_nametoindex	1
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/api/if_api.d b/Debug/Middlewares/Third_Party/LwIP/src/api/if_api.d
index 19f70c5..065ed83 100644
--- a/Debug/Middlewares/Third_Party/LwIP/src/api/if_api.d
+++ b/Debug/Middlewares/Third_Party/LwIP/src/api/if_api.d
@@ -25,6 +25,7 @@ Middlewares/Third_Party/LwIP/src/api/if_api.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
@@ -32,10 +33,57 @@ Middlewares/Third_Party/LwIP/src/api/if_api.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \
  ../Middlewares/Third_Party/LwIP/system/arch/cc.h \
- ../Middlewares/Third_Party/LwIP/system/arch/cpu.h
+ ../Middlewares/Third_Party/LwIP/system/arch/cpu.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/errno.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/if_api.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/netif.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/err.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/netifapi.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/sockets_priv.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/sockets.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/inet.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/sys.h \
+ ../Middlewares/Third_Party/LwIP/system/arch/sys_arch.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h \
+ ../Core/Inc/FreeRTOSConfig.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/list.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h
 ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h:
 ../LWIP/Target/lwipopts.h:
 ../Core/Inc/main.h:
@@ -62,6 +110,7 @@ Middlewares/Third_Party/LwIP/src/api/if_api.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
@@ -69,7 +118,54 @@ Middlewares/Third_Party/LwIP/src/api/if_api.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h:
 ../Middlewares/Third_Party/LwIP/system/arch/cc.h:
 ../Middlewares/Third_Party/LwIP/system/arch/cpu.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/errno.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/if_api.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/netif.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/err.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/def.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/def.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/netifapi.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/priv/sockets_priv.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/sockets.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/inet.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/sys.h:
+../Middlewares/Third_Party/LwIP/system/arch/sys_arch.h:
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h:
+../Core/Inc/FreeRTOSConfig.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h:
+../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/task.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/list.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/task.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h:
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/api/if_api.o b/Debug/Middlewares/Third_Party/LwIP/src/api/if_api.o
index ef2530e..955c147 100644
Binary files a/Debug/Middlewares/Third_Party/LwIP/src/api/if_api.o and b/Debug/Middlewares/Third_Party/LwIP/src/api/if_api.o differ
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/api/if_api.su b/Debug/Middlewares/Third_Party/LwIP/src/api/if_api.su
index e69de29..72be15e 100644
--- a/Debug/Middlewares/Third_Party/LwIP/src/api/if_api.su
+++ b/Debug/Middlewares/Third_Party/LwIP/src/api/if_api.su
@@ -0,0 +1,2 @@
+../Middlewares/Third_Party/LwIP/src/api/if_api.c:61:1:lwip_if_indextoname	16	static
+../Middlewares/Third_Party/LwIP/src/api/if_api.c:86:1:lwip_if_nametoindex	16	static
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/api/netbuf.cyclo b/Debug/Middlewares/Third_Party/LwIP/src/api/netbuf.cyclo
index e69de29..8a651b9 100644
--- a/Debug/Middlewares/Third_Party/LwIP/src/api/netbuf.cyclo
+++ b/Debug/Middlewares/Third_Party/LwIP/src/api/netbuf.cyclo
@@ -0,0 +1,9 @@
+../Middlewares/Third_Party/LwIP/src/api/netbuf.c:63:9:netbuf_new	2
+../Middlewares/Third_Party/LwIP/src/api/netbuf.c:81:1:netbuf_delete	3
+../Middlewares/Third_Party/LwIP/src/api/netbuf.c:102:1:netbuf_alloc	5
+../Middlewares/Third_Party/LwIP/src/api/netbuf.c:127:1:netbuf_free	3
+../Middlewares/Third_Party/LwIP/src/api/netbuf.c:151:1:netbuf_ref	4
+../Middlewares/Third_Party/LwIP/src/api/netbuf.c:176:1:netbuf_chain	3
+../Middlewares/Third_Party/LwIP/src/api/netbuf.c:196:1:netbuf_data	5
+../Middlewares/Third_Party/LwIP/src/api/netbuf.c:222:1:netbuf_next	4
+../Middlewares/Third_Party/LwIP/src/api/netbuf.c:244:1:netbuf_first	2
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/api/netbuf.d b/Debug/Middlewares/Third_Party/LwIP/src/api/netbuf.d
index 5befdb1..d2ac743 100644
--- a/Debug/Middlewares/Third_Party/LwIP/src/api/netbuf.d
+++ b/Debug/Middlewares/Third_Party/LwIP/src/api/netbuf.d
@@ -25,6 +25,7 @@ Middlewares/Third_Party/LwIP/src/api/netbuf.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
@@ -32,10 +33,32 @@ Middlewares/Third_Party/LwIP/src/api/netbuf.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \
  ../Middlewares/Third_Party/LwIP/system/arch/cc.h \
- ../Middlewares/Third_Party/LwIP/system/arch/cpu.h
+ ../Middlewares/Third_Party/LwIP/system/arch/cpu.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/netbuf.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/err.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h
 ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h:
 ../LWIP/Target/lwipopts.h:
 ../Core/Inc/main.h:
@@ -62,6 +85,7 @@ Middlewares/Third_Party/LwIP/src/api/netbuf.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
@@ -69,7 +93,29 @@ Middlewares/Third_Party/LwIP/src/api/netbuf.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h:
 ../Middlewares/Third_Party/LwIP/system/arch/cc.h:
 ../Middlewares/Third_Party/LwIP/system/arch/cpu.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/netbuf.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/err.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/def.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/def.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h:
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/api/netbuf.o b/Debug/Middlewares/Third_Party/LwIP/src/api/netbuf.o
index a0fd983..094241f 100644
Binary files a/Debug/Middlewares/Third_Party/LwIP/src/api/netbuf.o and b/Debug/Middlewares/Third_Party/LwIP/src/api/netbuf.o differ
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/api/netbuf.su b/Debug/Middlewares/Third_Party/LwIP/src/api/netbuf.su
index e69de29..0a5bba8 100644
--- a/Debug/Middlewares/Third_Party/LwIP/src/api/netbuf.su
+++ b/Debug/Middlewares/Third_Party/LwIP/src/api/netbuf.su
@@ -0,0 +1,9 @@
+../Middlewares/Third_Party/LwIP/src/api/netbuf.c:63:9:netbuf_new	16	static
+../Middlewares/Third_Party/LwIP/src/api/netbuf.c:81:1:netbuf_delete	16	static
+../Middlewares/Third_Party/LwIP/src/api/netbuf.c:102:1:netbuf_alloc	16	static
+../Middlewares/Third_Party/LwIP/src/api/netbuf.c:127:1:netbuf_free	16	static
+../Middlewares/Third_Party/LwIP/src/api/netbuf.c:151:1:netbuf_ref	24	static
+../Middlewares/Third_Party/LwIP/src/api/netbuf.c:176:1:netbuf_chain	16	static
+../Middlewares/Third_Party/LwIP/src/api/netbuf.c:196:1:netbuf_data	24	static
+../Middlewares/Third_Party/LwIP/src/api/netbuf.c:222:1:netbuf_next	16	static
+../Middlewares/Third_Party/LwIP/src/api/netbuf.c:244:1:netbuf_first	16	static
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/api/netdb.d b/Debug/Middlewares/Third_Party/LwIP/src/api/netdb.d
index e5f5695..6d739e2 100644
--- a/Debug/Middlewares/Third_Party/LwIP/src/api/netdb.d
+++ b/Debug/Middlewares/Third_Party/LwIP/src/api/netdb.d
@@ -26,6 +26,7 @@ Middlewares/Third_Party/LwIP/src/api/netdb.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
@@ -33,6 +34,14 @@ Middlewares/Third_Party/LwIP/src/api/netdb.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \
  ../Middlewares/Third_Party/LwIP/system/arch/cc.h \
@@ -64,6 +73,7 @@ Middlewares/Third_Party/LwIP/src/api/netdb.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
@@ -71,6 +81,14 @@ Middlewares/Third_Party/LwIP/src/api/netdb.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h:
 ../Middlewares/Third_Party/LwIP/system/arch/cc.h:
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/api/netdb.o b/Debug/Middlewares/Third_Party/LwIP/src/api/netdb.o
index 66609f9..e1de9fa 100644
Binary files a/Debug/Middlewares/Third_Party/LwIP/src/api/netdb.o and b/Debug/Middlewares/Third_Party/LwIP/src/api/netdb.o differ
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/api/netifapi.d b/Debug/Middlewares/Third_Party/LwIP/src/api/netifapi.d
index 0d5dba5..d226aaa 100644
--- a/Debug/Middlewares/Third_Party/LwIP/src/api/netifapi.d
+++ b/Debug/Middlewares/Third_Party/LwIP/src/api/netifapi.d
@@ -25,6 +25,7 @@ Middlewares/Third_Party/LwIP/src/api/netifapi.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
@@ -32,6 +33,14 @@ Middlewares/Third_Party/LwIP/src/api/netifapi.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \
  ../Middlewares/Third_Party/LwIP/system/arch/cc.h \
@@ -62,6 +71,7 @@ Middlewares/Third_Party/LwIP/src/api/netifapi.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
@@ -69,6 +79,14 @@ Middlewares/Third_Party/LwIP/src/api/netifapi.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h:
 ../Middlewares/Third_Party/LwIP/system/arch/cc.h:
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/api/netifapi.o b/Debug/Middlewares/Third_Party/LwIP/src/api/netifapi.o
index bab5811..8f9b56e 100644
Binary files a/Debug/Middlewares/Third_Party/LwIP/src/api/netifapi.o and b/Debug/Middlewares/Third_Party/LwIP/src/api/netifapi.o differ
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/api/sockets.cyclo b/Debug/Middlewares/Third_Party/LwIP/src/api/sockets.cyclo
index e69de29..dcc74c8 100644
--- a/Debug/Middlewares/Third_Party/LwIP/src/api/sockets.cyclo
+++ b/Debug/Middlewares/Third_Party/LwIP/src/api/sockets.cyclo
@@ -0,0 +1,54 @@
+../Middlewares/Third_Party/LwIP/src/api/sockets.c:320:1:lwip_socket_thread_init	1
+../Middlewares/Third_Party/LwIP/src/api/sockets.c:327:1:lwip_socket_thread_cleanup	1
+../Middlewares/Third_Party/LwIP/src/api/sockets.c:411:1:tryget_socket_unconn_nouse	3
+../Middlewares/Third_Party/LwIP/src/api/sockets.c:422:1:lwip_socket_dbg_get_socket	1
+../Middlewares/Third_Party/LwIP/src/api/sockets.c:429:1:tryget_socket_unconn	1
+../Middlewares/Third_Party/LwIP/src/api/sockets.c:442:1:tryget_socket_unconn_locked	1
+../Middlewares/Third_Party/LwIP/src/api/sockets.c:460:1:tryget_socket	3
+../Middlewares/Third_Party/LwIP/src/api/sockets.c:479:1:get_socket	2
+../Middlewares/Third_Party/LwIP/src/api/sockets.c:501:1:alloc_socket	6
+../Middlewares/Third_Party/LwIP/src/api/sockets.c:548:1:free_socket_locked	1
+../Middlewares/Third_Party/LwIP/src/api/sockets.c:572:1:free_socket_free_elements	4
+../Middlewares/Third_Party/LwIP/src/api/sockets.c:594:1:free_socket	2
+../Middlewares/Third_Party/LwIP/src/api/sockets.c:620:1:lwip_accept	21
+../Middlewares/Third_Party/LwIP/src/api/sockets.c:718:1:lwip_bind	9
+../Middlewares/Third_Party/LwIP/src/api/sockets.c:772:1:lwip_close	6
+../Middlewares/Third_Party/LwIP/src/api/sockets.c:813:1:lwip_connect	11
+../Middlewares/Third_Party/LwIP/src/api/sockets.c:881:1:lwip_listen	8
+../Middlewares/Third_Party/LwIP/src/api/sockets.c:920:1:lwip_recv_tcp	22
+../Middlewares/Third_Party/LwIP/src/api/sockets.c:1023:1:lwip_sock_make_addr	6
+../Middlewares/Third_Party/LwIP/src/api/sockets.c:1056:1:lwip_recv_tcp_from	6
+../Middlewares/Third_Party/LwIP/src/api/sockets.c:1088:1:lwip_recvfrom_udp_raw	18
+../Middlewares/Third_Party/LwIP/src/api/sockets.c:1199:1:lwip_recvfrom	9
+../Middlewares/Third_Party/LwIP/src/api/sockets.c:1252:1:lwip_read	1
+../Middlewares/Third_Party/LwIP/src/api/sockets.c:1258:1:lwip_readv	1
+../Middlewares/Third_Party/LwIP/src/api/sockets.c:1275:1:lwip_recv	1
+../Middlewares/Third_Party/LwIP/src/api/sockets.c:1281:1:lwip_recvmsg	24
+../Middlewares/Third_Party/LwIP/src/api/sockets.c:1382:1:lwip_send	6
+../Middlewares/Third_Party/LwIP/src/api/sockets.c:1422:1:lwip_sendmsg	30
+../Middlewares/Third_Party/LwIP/src/api/sockets.c:1585:1:lwip_sendto	16
+../Middlewares/Third_Party/LwIP/src/api/sockets.c:1685:1:lwip_socket	8
+../Middlewares/Third_Party/LwIP/src/api/sockets.c:1746:1:lwip_write	1
+../Middlewares/Third_Party/LwIP/src/api/sockets.c:1752:1:lwip_writev	1
+../Middlewares/Third_Party/LwIP/src/api/sockets.c:1771:1:lwip_link_select_cb	2
+../Middlewares/Third_Party/LwIP/src/api/sockets.c:1795:1:lwip_unlink_select_cb	5
+../Middlewares/Third_Party/LwIP/src/api/sockets.c:1835:1:lwip_selscan	32
+../Middlewares/Third_Party/LwIP/src/api/sockets.c:1964:1:lwip_select	43
+../Middlewares/Third_Party/LwIP/src/api/sockets.c:2193:1:lwip_pollscan	19
+../Middlewares/Third_Party/LwIP/src/api/sockets.c:2319:1:lwip_poll	13
+../Middlewares/Third_Party/LwIP/src/api/sockets.c:2438:1:lwip_poll_should_wake	8
+../Middlewares/Third_Party/LwIP/src/api/sockets.c:2477:1:event_callback	15
+../Middlewares/Third_Party/LwIP/src/api/sockets.c:2576:13:select_check_waiters	19
+../Middlewares/Third_Party/LwIP/src/api/sockets.c:2655:1:lwip_shutdown	12
+../Middlewares/Third_Party/LwIP/src/api/sockets.c:2700:1:lwip_getaddrname	6
+../Middlewares/Third_Party/LwIP/src/api/sockets.c:2747:1:lwip_getpeername	1
+../Middlewares/Third_Party/LwIP/src/api/sockets.c:2753:1:lwip_getsockname	1
+../Middlewares/Third_Party/LwIP/src/api/sockets.c:2759:1:lwip_getsockopt	7
+../Middlewares/Third_Party/LwIP/src/api/sockets.c:2859:1:lwip_sockopt_to_ipopt	5
+../Middlewares/Third_Party/LwIP/src/api/sockets.c:2882:1:lwip_getsockopt_impl	55
+../Middlewares/Third_Party/LwIP/src/api/sockets.c:3205:1:lwip_setsockopt	6
+../Middlewares/Third_Party/LwIP/src/api/sockets.c:3303:1:lwip_setsockopt_impl	47
+../Middlewares/Third_Party/LwIP/src/api/sockets.c:3743:1:lwip_ioctl	8
+../Middlewares/Third_Party/LwIP/src/api/sockets.c:3836:1:lwip_fcntl	14
+../Middlewares/Third_Party/LwIP/src/api/sockets.c:3919:1:lwip_inet_ntop	4
+../Middlewares/Third_Party/LwIP/src/api/sockets.c:3952:1:lwip_inet_pton	2
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/api/sockets.d b/Debug/Middlewares/Third_Party/LwIP/src/api/sockets.d
index a7bcb90..09a8d26 100644
--- a/Debug/Middlewares/Third_Party/LwIP/src/api/sockets.d
+++ b/Debug/Middlewares/Third_Party/LwIP/src/api/sockets.d
@@ -25,6 +25,7 @@ Middlewares/Third_Party/LwIP/src/api/sockets.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
@@ -32,10 +33,74 @@ Middlewares/Third_Party/LwIP/src/api/sockets.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \
  ../Middlewares/Third_Party/LwIP/system/arch/cc.h \
- ../Middlewares/Third_Party/LwIP/system/arch/cpu.h
+ ../Middlewares/Third_Party/LwIP/system/arch/cpu.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/sockets.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/netif.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/err.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/inet.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/errno.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/sockets_priv.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/sys.h \
+ ../Middlewares/Third_Party/LwIP/system/arch/sys_arch.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h \
+ ../Core/Inc/FreeRTOSConfig.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/list.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/api.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/netbuf.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/igmp.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/tcp.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/tcpbase.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/ip.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip4.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/ip6.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/icmp.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/icmp.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/raw.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/udp.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/udp.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/tcpip_priv.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/tcpip.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/timeouts.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/mld6.h
 ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h:
 ../LWIP/Target/lwipopts.h:
 ../Core/Inc/main.h:
@@ -62,6 +127,7 @@ Middlewares/Third_Party/LwIP/src/api/sockets.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
@@ -69,7 +135,71 @@ Middlewares/Third_Party/LwIP/src/api/sockets.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h:
 ../Middlewares/Third_Party/LwIP/system/arch/cc.h:
 ../Middlewares/Third_Party/LwIP/system/arch/cpu.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/sockets.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/def.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/def.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/netif.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/err.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/inet.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/errno.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/priv/sockets_priv.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/sys.h:
+../Middlewares/Third_Party/LwIP/system/arch/sys_arch.h:
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h:
+../Core/Inc/FreeRTOSConfig.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h:
+../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/task.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/list.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/task.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/api.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/netbuf.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/igmp.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/tcp.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/tcpbase.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/ip.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/ip4.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip4.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/ip6.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/icmp.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/prot/icmp.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/raw.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/udp.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/prot/udp.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/priv/tcpip_priv.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/tcpip.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/timeouts.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/mld6.h:
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/api/sockets.o b/Debug/Middlewares/Third_Party/LwIP/src/api/sockets.o
index 8d6e872..c9d80ee 100644
Binary files a/Debug/Middlewares/Third_Party/LwIP/src/api/sockets.o and b/Debug/Middlewares/Third_Party/LwIP/src/api/sockets.o differ
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/api/sockets.su b/Debug/Middlewares/Third_Party/LwIP/src/api/sockets.su
index e69de29..2ab408a 100644
--- a/Debug/Middlewares/Third_Party/LwIP/src/api/sockets.su
+++ b/Debug/Middlewares/Third_Party/LwIP/src/api/sockets.su
@@ -0,0 +1,54 @@
+../Middlewares/Third_Party/LwIP/src/api/sockets.c:320:1:lwip_socket_thread_init	4	static
+../Middlewares/Third_Party/LwIP/src/api/sockets.c:327:1:lwip_socket_thread_cleanup	4	static
+../Middlewares/Third_Party/LwIP/src/api/sockets.c:411:1:tryget_socket_unconn_nouse	24	static
+../Middlewares/Third_Party/LwIP/src/api/sockets.c:422:1:lwip_socket_dbg_get_socket	16	static
+../Middlewares/Third_Party/LwIP/src/api/sockets.c:429:1:tryget_socket_unconn	24	static
+../Middlewares/Third_Party/LwIP/src/api/sockets.c:442:1:tryget_socket_unconn_locked	24	static
+../Middlewares/Third_Party/LwIP/src/api/sockets.c:460:1:tryget_socket	24	static
+../Middlewares/Third_Party/LwIP/src/api/sockets.c:479:1:get_socket	24	static
+../Middlewares/Third_Party/LwIP/src/api/sockets.c:501:1:alloc_socket	24	static
+../Middlewares/Third_Party/LwIP/src/api/sockets.c:548:1:free_socket_locked	24	static
+../Middlewares/Third_Party/LwIP/src/api/sockets.c:572:1:free_socket_free_elements	24	static
+../Middlewares/Third_Party/LwIP/src/api/sockets.c:594:1:free_socket	32	static
+../Middlewares/Third_Party/LwIP/src/api/sockets.c:620:1:lwip_accept	112	static
+../Middlewares/Third_Party/LwIP/src/api/sockets.c:718:1:lwip_bind	48	static
+../Middlewares/Third_Party/LwIP/src/api/sockets.c:772:1:lwip_close	32	static
+../Middlewares/Third_Party/LwIP/src/api/sockets.c:813:1:lwip_connect	48	static
+../Middlewares/Third_Party/LwIP/src/api/sockets.c:881:1:lwip_listen	40	static
+../Middlewares/Third_Party/LwIP/src/api/sockets.c:920:1:lwip_recv_tcp	56	static
+../Middlewares/Third_Party/LwIP/src/api/sockets.c:1023:1:lwip_sock_make_addr	56	static
+../Middlewares/Third_Party/LwIP/src/api/sockets.c:1056:1:lwip_recv_tcp_from	40	static
+../Middlewares/Third_Party/LwIP/src/api/sockets.c:1088:1:lwip_recvfrom_udp_raw	64	static
+../Middlewares/Third_Party/LwIP/src/api/sockets.c:1199:1:lwip_recvfrom	96	static
+../Middlewares/Third_Party/LwIP/src/api/sockets.c:1252:1:lwip_read	32	static
+../Middlewares/Third_Party/LwIP/src/api/sockets.c:1258:1:lwip_readv	56	static
+../Middlewares/Third_Party/LwIP/src/api/sockets.c:1275:1:lwip_recv	32	static
+../Middlewares/Third_Party/LwIP/src/api/sockets.c:1281:1:lwip_recvmsg	80	static
+../Middlewares/Third_Party/LwIP/src/api/sockets.c:1382:1:lwip_send	48	static
+../Middlewares/Third_Party/LwIP/src/api/sockets.c:1422:1:lwip_sendmsg	120	static
+../Middlewares/Third_Party/LwIP/src/api/sockets.c:1585:1:lwip_sendto	64	static
+../Middlewares/Third_Party/LwIP/src/api/sockets.c:1685:1:lwip_socket	32	static
+../Middlewares/Third_Party/LwIP/src/api/sockets.c:1746:1:lwip_write	24	static
+../Middlewares/Third_Party/LwIP/src/api/sockets.c:1752:1:lwip_writev	56	static
+../Middlewares/Third_Party/LwIP/src/api/sockets.c:1771:1:lwip_link_select_cb	16	static
+../Middlewares/Third_Party/LwIP/src/api/sockets.c:1795:1:lwip_unlink_select_cb	16	static
+../Middlewares/Third_Party/LwIP/src/api/sockets.c:1835:1:lwip_selscan	104	static
+../Middlewares/Third_Party/LwIP/src/api/sockets.c:1964:1:lwip_select	136	static
+../Middlewares/Third_Party/LwIP/src/api/sockets.c:2193:1:lwip_pollscan	56	static
+../Middlewares/Third_Party/LwIP/src/api/sockets.c:2319:1:lwip_poll	72	static
+../Middlewares/Third_Party/LwIP/src/api/sockets.c:2438:1:lwip_poll_should_wake	32	static
+../Middlewares/Third_Party/LwIP/src/api/sockets.c:2477:1:event_callback	48	static
+../Middlewares/Third_Party/LwIP/src/api/sockets.c:2576:13:select_check_waiters	40	static
+../Middlewares/Third_Party/LwIP/src/api/sockets.c:2655:1:lwip_shutdown	48	static
+../Middlewares/Third_Party/LwIP/src/api/sockets.c:2700:1:lwip_getaddrname	72	static
+../Middlewares/Third_Party/LwIP/src/api/sockets.c:2747:1:lwip_getpeername	24	static
+../Middlewares/Third_Party/LwIP/src/api/sockets.c:2753:1:lwip_getsockname	24	static
+../Middlewares/Third_Party/LwIP/src/api/sockets.c:2759:1:lwip_getsockopt	48	static
+../Middlewares/Third_Party/LwIP/src/api/sockets.c:2859:1:lwip_sockopt_to_ipopt	16	static
+../Middlewares/Third_Party/LwIP/src/api/sockets.c:2882:1:lwip_getsockopt_impl	32	static
+../Middlewares/Third_Party/LwIP/src/api/sockets.c:3205:1:lwip_setsockopt	48	static
+../Middlewares/Third_Party/LwIP/src/api/sockets.c:3303:1:lwip_setsockopt_impl	40	static
+../Middlewares/Third_Party/LwIP/src/api/sockets.c:3743:1:lwip_ioctl	40	static
+../Middlewares/Third_Party/LwIP/src/api/sockets.c:3836:1:lwip_fcntl	56	static
+../Middlewares/Third_Party/LwIP/src/api/sockets.c:3919:1:lwip_inet_ntop	32	static
+../Middlewares/Third_Party/LwIP/src/api/sockets.c:3952:1:lwip_inet_pton	32	static
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/api/subdir.mk b/Debug/Middlewares/Third_Party/LwIP/src/api/subdir.mk
index 2035083..0f411a6 100644
--- a/Debug/Middlewares/Third_Party/LwIP/src/api/subdir.mk
+++ b/Debug/Middlewares/Third_Party/LwIP/src/api/subdir.mk
@@ -40,7 +40,7 @@ C_DEPS += \
 
 # Each subdirectory must supply rules for building sources it contributes
 Middlewares/Third_Party/LwIP/src/api/%.o Middlewares/Third_Party/LwIP/src/api/%.su Middlewares/Third_Party/LwIP/src/api/%.cyclo: ../Middlewares/Third_Party/LwIP/src/api/%.c Middlewares/Third_Party/LwIP/src/api/subdir.mk
-	arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DDEBUG -DDATA_IN_D2_SRAM -DUSE_HAL_DRIVER -DSTM32H723xx -c -I../Core/Inc -I../Drivers/STM32H7xx_HAL_Driver/Inc -I../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32H7xx/Include -I../Drivers/CMSIS/Include -I../LWIP/App -I../LWIP/Target -I../Middlewares/Third_Party/LwIP/src/include -I../Middlewares/Third_Party/LwIP/system -I../Drivers/BSP/Components/lan8742 -I../Middlewares/Third_Party/LwIP/src/include/netif/ppp -I../Middlewares/Third_Party/LwIP/src/include/lwip -I../Middlewares/Third_Party/LwIP/src/include/lwip/apps -I../Middlewares/Third_Party/LwIP/src/include/lwip/priv -I../Middlewares/Third_Party/LwIP/src/include/lwip/prot -I../Middlewares/Third_Party/LwIP/src/include/netif -I../Middlewares/Third_Party/LwIP/src/include/compat/posix -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/arpa -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/net -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/sys -I../Middlewares/Third_Party/LwIP/src/include/compat/stdc -I../Middlewares/Third_Party/LwIP/system/arch -I"C:/_NoSleep/STM32/lwip_test/LWFTP" -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
+	arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DDEBUG -DDATA_IN_D2_SRAM -DUSE_HAL_DRIVER -DSTM32H723xx -c -I../Core/Inc -I../FATFS/Target -I../FATFS/App -I../LWIP/App -I../LWIP/Target -I../Middlewares/Third_Party/LwIP/src/include -I../Middlewares/Third_Party/LwIP/system -I../Drivers/STM32H7xx_HAL_Driver/Inc -I../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F -I../Middlewares/Third_Party/FatFs/src -I../Drivers/BSP/Components/lan8742 -I../Middlewares/Third_Party/LwIP/src/include/netif/ppp -I../Drivers/CMSIS/Device/ST/STM32H7xx/Include -I../Middlewares/Third_Party/LwIP/src/include/lwip -I../Middlewares/Third_Party/LwIP/src/include/lwip/apps -I../Middlewares/Third_Party/LwIP/src/include/lwip/priv -I../Middlewares/Third_Party/LwIP/src/include/lwip/prot -I../Middlewares/Third_Party/LwIP/src/include/netif -I../Middlewares/Third_Party/LwIP/src/include/compat/posix -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/arpa -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/net -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/sys -I../Middlewares/Third_Party/LwIP/src/include/compat/stdc -I../Middlewares/Third_Party/LwIP/system/arch -I../Drivers/CMSIS/Include -I"C:/_NoSleep/STM32/TBD_TaxiBoard/LWFTPC" -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
 
 clean: clean-Middlewares-2f-Third_Party-2f-LwIP-2f-src-2f-api
 
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/api/tcpip.cyclo b/Debug/Middlewares/Third_Party/LwIP/src/api/tcpip.cyclo
index e69de29..9501b81 100644
--- a/Debug/Middlewares/Third_Party/LwIP/src/api/tcpip.cyclo
+++ b/Debug/Middlewares/Third_Party/LwIP/src/api/tcpip.cyclo
@@ -0,0 +1,17 @@
+../Middlewares/Third_Party/LwIP/src/api/tcpip.c:84:1:tcpip_timeouts_mbox_fetch	4
+../Middlewares/Third_Party/LwIP/src/api/tcpip.c:127:1:tcpip_thread	3
+../Middlewares/Third_Party/LwIP/src/api/tcpip.c:156:1:tcpip_thread_handle_msg	6
+../Middlewares/Third_Party/LwIP/src/api/tcpip.c:240:1:tcpip_inpkt	4
+../Middlewares/Third_Party/LwIP/src/api/tcpip.c:283:1:tcpip_input	2
+../Middlewares/Third_Party/LwIP/src/api/tcpip.c:309:1:tcpip_callback	3
+../Middlewares/Third_Party/LwIP/src/api/tcpip.c:345:1:tcpip_try_callback	4
+../Middlewares/Third_Party/LwIP/src/api/tcpip.c:437:1:tcpip_send_msg_wait_sem	1
+../Middlewares/Third_Party/LwIP/src/api/tcpip.c:473:1:tcpip_api_call	1
+../Middlewares/Third_Party/LwIP/src/api/tcpip.c:531:1:tcpip_callbackmsg_new	2
+../Middlewares/Third_Party/LwIP/src/api/tcpip.c:552:1:tcpip_callbackmsg_delete	1
+../Middlewares/Third_Party/LwIP/src/api/tcpip.c:567:1:tcpip_callbackmsg_trycallback	2
+../Middlewares/Third_Party/LwIP/src/api/tcpip.c:586:1:tcpip_callbackmsg_trycallback_fromisr	2
+../Middlewares/Third_Party/LwIP/src/api/tcpip.c:602:1:tcpip_init	3
+../Middlewares/Third_Party/LwIP/src/api/tcpip.c:627:1:pbuf_free_int	1
+../Middlewares/Third_Party/LwIP/src/api/tcpip.c:640:1:pbuf_free_callback	1
+../Middlewares/Third_Party/LwIP/src/api/tcpip.c:653:1:mem_free_callback	1
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/api/tcpip.d b/Debug/Middlewares/Third_Party/LwIP/src/api/tcpip.d
index 39fd54e..22eab0d 100644
--- a/Debug/Middlewares/Third_Party/LwIP/src/api/tcpip.d
+++ b/Debug/Middlewares/Third_Party/LwIP/src/api/tcpip.d
@@ -25,6 +25,7 @@ Middlewares/Third_Party/LwIP/src/api/tcpip.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
@@ -32,10 +33,65 @@ Middlewares/Third_Party/LwIP/src/api/tcpip.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \
  ../Middlewares/Third_Party/LwIP/system/arch/cc.h \
- ../Middlewares/Third_Party/LwIP/system/arch/cpu.h
+ ../Middlewares/Third_Party/LwIP/system/arch/cpu.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/tcpip_priv.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/tcpip.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/err.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/timeouts.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/sys.h \
+ ../Middlewares/Third_Party/LwIP/system/arch/sys_arch.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h \
+ ../Core/Inc/FreeRTOSConfig.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/list.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/netif.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/init.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/ip.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip4.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/ip6.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/etharp.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ethernet.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ieee.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/etharp.h \
+ ../Middlewares/Third_Party/LwIP/src/include/netif/ethernet.h
 ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h:
 ../LWIP/Target/lwipopts.h:
 ../Core/Inc/main.h:
@@ -62,6 +118,7 @@ Middlewares/Third_Party/LwIP/src/api/tcpip.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
@@ -69,7 +126,62 @@ Middlewares/Third_Party/LwIP/src/api/tcpip.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h:
 ../Middlewares/Third_Party/LwIP/system/arch/cc.h:
 ../Middlewares/Third_Party/LwIP/system/arch/cpu.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/priv/tcpip_priv.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/tcpip.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/err.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/timeouts.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/sys.h:
+../Middlewares/Third_Party/LwIP/system/arch/sys_arch.h:
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h:
+../Core/Inc/FreeRTOSConfig.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h:
+../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/task.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/list.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/task.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/netif.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/def.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/def.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/init.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/ip.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/ip4.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip4.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/ip6.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/etharp.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ethernet.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ieee.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/prot/etharp.h:
+../Middlewares/Third_Party/LwIP/src/include/netif/ethernet.h:
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/api/tcpip.o b/Debug/Middlewares/Third_Party/LwIP/src/api/tcpip.o
index fb6f89b..cb68a47 100644
Binary files a/Debug/Middlewares/Third_Party/LwIP/src/api/tcpip.o and b/Debug/Middlewares/Third_Party/LwIP/src/api/tcpip.o differ
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/api/tcpip.su b/Debug/Middlewares/Third_Party/LwIP/src/api/tcpip.su
index e69de29..01701b0 100644
--- a/Debug/Middlewares/Third_Party/LwIP/src/api/tcpip.su
+++ b/Debug/Middlewares/Third_Party/LwIP/src/api/tcpip.su
@@ -0,0 +1,17 @@
+../Middlewares/Third_Party/LwIP/src/api/tcpip.c:84:1:tcpip_timeouts_mbox_fetch	24	static
+../Middlewares/Third_Party/LwIP/src/api/tcpip.c:127:1:tcpip_thread	24	static
+../Middlewares/Third_Party/LwIP/src/api/tcpip.c:156:1:tcpip_thread_handle_msg	16	static
+../Middlewares/Third_Party/LwIP/src/api/tcpip.c:240:1:tcpip_inpkt	32	static
+../Middlewares/Third_Party/LwIP/src/api/tcpip.c:283:1:tcpip_input	16	static
+../Middlewares/Third_Party/LwIP/src/api/tcpip.c:309:1:tcpip_callback	24	static
+../Middlewares/Third_Party/LwIP/src/api/tcpip.c:345:1:tcpip_try_callback	24	static
+../Middlewares/Third_Party/LwIP/src/api/tcpip.c:437:1:tcpip_send_msg_wait_sem	24	static
+../Middlewares/Third_Party/LwIP/src/api/tcpip.c:473:1:tcpip_api_call	24	static
+../Middlewares/Third_Party/LwIP/src/api/tcpip.c:531:1:tcpip_callbackmsg_new	24	static
+../Middlewares/Third_Party/LwIP/src/api/tcpip.c:552:1:tcpip_callbackmsg_delete	16	static
+../Middlewares/Third_Party/LwIP/src/api/tcpip.c:567:1:tcpip_callbackmsg_trycallback	16	static
+../Middlewares/Third_Party/LwIP/src/api/tcpip.c:586:1:tcpip_callbackmsg_trycallback_fromisr	16	static
+../Middlewares/Third_Party/LwIP/src/api/tcpip.c:602:1:tcpip_init	24	static
+../Middlewares/Third_Party/LwIP/src/api/tcpip.c:627:1:pbuf_free_int	24	static
+../Middlewares/Third_Party/LwIP/src/api/tcpip.c:640:1:pbuf_free_callback	16	static
+../Middlewares/Third_Party/LwIP/src/api/tcpip.c:653:1:mem_free_callback	16	static
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.d b/Debug/Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.d
index 3fc744a..f032221 100644
--- a/Debug/Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.d
+++ b/Debug/Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.d
@@ -27,6 +27,7 @@ Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
@@ -34,6 +35,14 @@ Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \
  ../Middlewares/Third_Party/LwIP/system/arch/cc.h \
@@ -65,6 +74,25 @@ Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.o: \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/icmp.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/icmp.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/timeouts.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/sys.h \
+ ../Middlewares/Third_Party/LwIP/system/arch/sys_arch.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h \
+ ../Core/Inc/FreeRTOSConfig.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/list.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/altcp_tcp.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/altcp_tls.h
 ../Middlewares/Third_Party/LwIP/src/include/lwip/apps/mqtt.h:
@@ -95,6 +123,7 @@ Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
@@ -102,6 +131,14 @@ Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h:
 ../Middlewares/Third_Party/LwIP/system/arch/cc.h:
@@ -133,5 +170,24 @@ Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.o: \
 ../Middlewares/Third_Party/LwIP/src/include/lwip/icmp.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/icmp.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/timeouts.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/sys.h:
+../Middlewares/Third_Party/LwIP/system/arch/sys_arch.h:
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h:
+../Core/Inc/FreeRTOSConfig.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h:
+../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/task.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/list.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/task.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/altcp_tcp.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/altcp_tls.h:
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.o b/Debug/Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.o
index 1f0dd59..d2ace03 100644
Binary files a/Debug/Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.o and b/Debug/Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.o differ
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/apps/mqtt/subdir.mk b/Debug/Middlewares/Third_Party/LwIP/src/apps/mqtt/subdir.mk
index 1fef600..b2c62ce 100644
--- a/Debug/Middlewares/Third_Party/LwIP/src/apps/mqtt/subdir.mk
+++ b/Debug/Middlewares/Third_Party/LwIP/src/apps/mqtt/subdir.mk
@@ -16,7 +16,7 @@ C_DEPS += \
 
 # Each subdirectory must supply rules for building sources it contributes
 Middlewares/Third_Party/LwIP/src/apps/mqtt/%.o Middlewares/Third_Party/LwIP/src/apps/mqtt/%.su Middlewares/Third_Party/LwIP/src/apps/mqtt/%.cyclo: ../Middlewares/Third_Party/LwIP/src/apps/mqtt/%.c Middlewares/Third_Party/LwIP/src/apps/mqtt/subdir.mk
-	arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DDEBUG -DDATA_IN_D2_SRAM -DUSE_HAL_DRIVER -DSTM32H723xx -c -I../Core/Inc -I../Drivers/STM32H7xx_HAL_Driver/Inc -I../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32H7xx/Include -I../Drivers/CMSIS/Include -I../LWIP/App -I../LWIP/Target -I../Middlewares/Third_Party/LwIP/src/include -I../Middlewares/Third_Party/LwIP/system -I../Drivers/BSP/Components/lan8742 -I../Middlewares/Third_Party/LwIP/src/include/netif/ppp -I../Middlewares/Third_Party/LwIP/src/include/lwip -I../Middlewares/Third_Party/LwIP/src/include/lwip/apps -I../Middlewares/Third_Party/LwIP/src/include/lwip/priv -I../Middlewares/Third_Party/LwIP/src/include/lwip/prot -I../Middlewares/Third_Party/LwIP/src/include/netif -I../Middlewares/Third_Party/LwIP/src/include/compat/posix -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/arpa -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/net -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/sys -I../Middlewares/Third_Party/LwIP/src/include/compat/stdc -I../Middlewares/Third_Party/LwIP/system/arch -I"C:/_NoSleep/STM32/lwip_test/LWFTP" -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
+	arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DDEBUG -DDATA_IN_D2_SRAM -DUSE_HAL_DRIVER -DSTM32H723xx -c -I../Core/Inc -I../FATFS/Target -I../FATFS/App -I../LWIP/App -I../LWIP/Target -I../Middlewares/Third_Party/LwIP/src/include -I../Middlewares/Third_Party/LwIP/system -I../Drivers/STM32H7xx_HAL_Driver/Inc -I../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F -I../Middlewares/Third_Party/FatFs/src -I../Drivers/BSP/Components/lan8742 -I../Middlewares/Third_Party/LwIP/src/include/netif/ppp -I../Drivers/CMSIS/Device/ST/STM32H7xx/Include -I../Middlewares/Third_Party/LwIP/src/include/lwip -I../Middlewares/Third_Party/LwIP/src/include/lwip/apps -I../Middlewares/Third_Party/LwIP/src/include/lwip/priv -I../Middlewares/Third_Party/LwIP/src/include/lwip/prot -I../Middlewares/Third_Party/LwIP/src/include/netif -I../Middlewares/Third_Party/LwIP/src/include/compat/posix -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/arpa -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/net -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/sys -I../Middlewares/Third_Party/LwIP/src/include/compat/stdc -I../Middlewares/Third_Party/LwIP/system/arch -I../Drivers/CMSIS/Include -I"C:/_NoSleep/STM32/TBD_TaxiBoard/LWFTPC" -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
 
 clean: clean-Middlewares-2f-Third_Party-2f-LwIP-2f-src-2f-apps-2f-mqtt
 
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/altcp.d b/Debug/Middlewares/Third_Party/LwIP/src/core/altcp.d
index a7f8a88..6eca718 100644
--- a/Debug/Middlewares/Third_Party/LwIP/src/core/altcp.d
+++ b/Debug/Middlewares/Third_Party/LwIP/src/core/altcp.d
@@ -25,6 +25,7 @@ Middlewares/Third_Party/LwIP/src/core/altcp.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
@@ -32,6 +33,14 @@ Middlewares/Third_Party/LwIP/src/core/altcp.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \
  ../Middlewares/Third_Party/LwIP/system/arch/cc.h \
@@ -62,6 +71,7 @@ Middlewares/Third_Party/LwIP/src/core/altcp.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
@@ -69,6 +79,14 @@ Middlewares/Third_Party/LwIP/src/core/altcp.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h:
 ../Middlewares/Third_Party/LwIP/system/arch/cc.h:
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/altcp.o b/Debug/Middlewares/Third_Party/LwIP/src/core/altcp.o
index d0e77ef..aa043d3 100644
Binary files a/Debug/Middlewares/Third_Party/LwIP/src/core/altcp.o and b/Debug/Middlewares/Third_Party/LwIP/src/core/altcp.o differ
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/altcp_alloc.d b/Debug/Middlewares/Third_Party/LwIP/src/core/altcp_alloc.d
index 976d0a7..97cca27 100644
--- a/Debug/Middlewares/Third_Party/LwIP/src/core/altcp_alloc.d
+++ b/Debug/Middlewares/Third_Party/LwIP/src/core/altcp_alloc.d
@@ -25,6 +25,7 @@ Middlewares/Third_Party/LwIP/src/core/altcp_alloc.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
@@ -32,6 +33,14 @@ Middlewares/Third_Party/LwIP/src/core/altcp_alloc.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \
  ../Middlewares/Third_Party/LwIP/system/arch/cc.h \
@@ -62,6 +71,7 @@ Middlewares/Third_Party/LwIP/src/core/altcp_alloc.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
@@ -69,6 +79,14 @@ Middlewares/Third_Party/LwIP/src/core/altcp_alloc.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h:
 ../Middlewares/Third_Party/LwIP/system/arch/cc.h:
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/altcp_alloc.o b/Debug/Middlewares/Third_Party/LwIP/src/core/altcp_alloc.o
index f97882e..9518712 100644
Binary files a/Debug/Middlewares/Third_Party/LwIP/src/core/altcp_alloc.o and b/Debug/Middlewares/Third_Party/LwIP/src/core/altcp_alloc.o differ
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/altcp_tcp.d b/Debug/Middlewares/Third_Party/LwIP/src/core/altcp_tcp.d
index 86bddf2..05f92ac 100644
--- a/Debug/Middlewares/Third_Party/LwIP/src/core/altcp_tcp.d
+++ b/Debug/Middlewares/Third_Party/LwIP/src/core/altcp_tcp.d
@@ -25,6 +25,7 @@ Middlewares/Third_Party/LwIP/src/core/altcp_tcp.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
@@ -32,6 +33,14 @@ Middlewares/Third_Party/LwIP/src/core/altcp_tcp.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \
  ../Middlewares/Third_Party/LwIP/system/arch/cc.h \
@@ -62,6 +71,7 @@ Middlewares/Third_Party/LwIP/src/core/altcp_tcp.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
@@ -69,6 +79,14 @@ Middlewares/Third_Party/LwIP/src/core/altcp_tcp.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h:
 ../Middlewares/Third_Party/LwIP/system/arch/cc.h:
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/altcp_tcp.o b/Debug/Middlewares/Third_Party/LwIP/src/core/altcp_tcp.o
index af2ba03..310de09 100644
Binary files a/Debug/Middlewares/Third_Party/LwIP/src/core/altcp_tcp.o and b/Debug/Middlewares/Third_Party/LwIP/src/core/altcp_tcp.o differ
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/def.d b/Debug/Middlewares/Third_Party/LwIP/src/core/def.d
index 781810e..5ffd1b0 100644
--- a/Debug/Middlewares/Third_Party/LwIP/src/core/def.d
+++ b/Debug/Middlewares/Third_Party/LwIP/src/core/def.d
@@ -25,6 +25,7 @@ Middlewares/Third_Party/LwIP/src/core/def.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
@@ -32,6 +33,14 @@ Middlewares/Third_Party/LwIP/src/core/def.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \
  ../Middlewares/Third_Party/LwIP/system/arch/cc.h \
@@ -63,6 +72,7 @@ Middlewares/Third_Party/LwIP/src/core/def.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
@@ -70,6 +80,14 @@ Middlewares/Third_Party/LwIP/src/core/def.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h:
 ../Middlewares/Third_Party/LwIP/system/arch/cc.h:
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/def.o b/Debug/Middlewares/Third_Party/LwIP/src/core/def.o
index 495996c..4129c2f 100644
Binary files a/Debug/Middlewares/Third_Party/LwIP/src/core/def.o and b/Debug/Middlewares/Third_Party/LwIP/src/core/def.o differ
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/dns.d b/Debug/Middlewares/Third_Party/LwIP/src/core/dns.d
index 59461ca..9b0f27f 100644
--- a/Debug/Middlewares/Third_Party/LwIP/src/core/dns.d
+++ b/Debug/Middlewares/Third_Party/LwIP/src/core/dns.d
@@ -25,6 +25,7 @@ Middlewares/Third_Party/LwIP/src/core/dns.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
@@ -32,6 +33,14 @@ Middlewares/Third_Party/LwIP/src/core/dns.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \
  ../Middlewares/Third_Party/LwIP/system/arch/cc.h \
@@ -62,6 +71,7 @@ Middlewares/Third_Party/LwIP/src/core/dns.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
@@ -69,6 +79,14 @@ Middlewares/Third_Party/LwIP/src/core/dns.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h:
 ../Middlewares/Third_Party/LwIP/system/arch/cc.h:
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/dns.o b/Debug/Middlewares/Third_Party/LwIP/src/core/dns.o
index c5e0368..6057fff 100644
Binary files a/Debug/Middlewares/Third_Party/LwIP/src/core/dns.o and b/Debug/Middlewares/Third_Party/LwIP/src/core/dns.o differ
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/inet_chksum.d b/Debug/Middlewares/Third_Party/LwIP/src/core/inet_chksum.d
index 9f4b81c..5926c43 100644
--- a/Debug/Middlewares/Third_Party/LwIP/src/core/inet_chksum.d
+++ b/Debug/Middlewares/Third_Party/LwIP/src/core/inet_chksum.d
@@ -25,6 +25,7 @@ Middlewares/Third_Party/LwIP/src/core/inet_chksum.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
@@ -32,6 +33,14 @@ Middlewares/Third_Party/LwIP/src/core/inet_chksum.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \
  ../Middlewares/Third_Party/LwIP/system/arch/cc.h \
@@ -70,6 +79,7 @@ Middlewares/Third_Party/LwIP/src/core/inet_chksum.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
@@ -77,6 +87,14 @@ Middlewares/Third_Party/LwIP/src/core/inet_chksum.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h:
 ../Middlewares/Third_Party/LwIP/system/arch/cc.h:
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/inet_chksum.o b/Debug/Middlewares/Third_Party/LwIP/src/core/inet_chksum.o
index 2d6b31a..5304413 100644
Binary files a/Debug/Middlewares/Third_Party/LwIP/src/core/inet_chksum.o and b/Debug/Middlewares/Third_Party/LwIP/src/core/inet_chksum.o differ
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/init.d b/Debug/Middlewares/Third_Party/LwIP/src/core/init.d
index 52876f1..53532ca 100644
--- a/Debug/Middlewares/Third_Party/LwIP/src/core/init.d
+++ b/Debug/Middlewares/Third_Party/LwIP/src/core/init.d
@@ -25,6 +25,7 @@ Middlewares/Third_Party/LwIP/src/core/init.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
@@ -32,6 +33,14 @@ Middlewares/Third_Party/LwIP/src/core/init.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \
  ../Middlewares/Third_Party/LwIP/system/arch/cc.h \
@@ -44,8 +53,26 @@ Middlewares/Third_Party/LwIP/src/core/init.o: \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/sys.h \
- ../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/err.h \
+ ../Middlewares/Third_Party/LwIP/system/arch/sys_arch.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h \
+ ../Core/Inc/FreeRTOSConfig.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/list.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/netif.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \
@@ -53,6 +80,8 @@ Middlewares/Third_Party/LwIP/src/core/init.o: \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/sockets.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/inet.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/errno.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/ip.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip4.h \
@@ -77,6 +106,7 @@ Middlewares/Third_Party/LwIP/src/core/init.o: \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/nd6.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/mld6.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/api.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/netbuf.h \
  ../Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_opts.h \
  ../Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_impl.h
 ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h:
@@ -105,6 +135,7 @@ Middlewares/Third_Party/LwIP/src/core/init.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
@@ -112,6 +143,14 @@ Middlewares/Third_Party/LwIP/src/core/init.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h:
 ../Middlewares/Third_Party/LwIP/system/arch/cc.h:
@@ -124,8 +163,26 @@ Middlewares/Third_Party/LwIP/src/core/init.o: \
 ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/sys.h:
-../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/err.h:
+../Middlewares/Third_Party/LwIP/system/arch/sys_arch.h:
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h:
+../Core/Inc/FreeRTOSConfig.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h:
+../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/task.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/list.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/task.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/netif.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h:
@@ -133,6 +190,8 @@ Middlewares/Third_Party/LwIP/src/core/init.o: \
 ../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/sockets.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/inet.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/errno.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/ip.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip4.h:
@@ -157,5 +216,6 @@ Middlewares/Third_Party/LwIP/src/core/init.o: \
 ../Middlewares/Third_Party/LwIP/src/include/lwip/nd6.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/mld6.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/api.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/netbuf.h:
 ../Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_opts.h:
 ../Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_impl.h:
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/init.o b/Debug/Middlewares/Third_Party/LwIP/src/core/init.o
index 539d3c4..18b3377 100644
Binary files a/Debug/Middlewares/Third_Party/LwIP/src/core/init.o and b/Debug/Middlewares/Third_Party/LwIP/src/core/init.o differ
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/ip.d b/Debug/Middlewares/Third_Party/LwIP/src/core/ip.d
index c716f08..9bcb661 100644
--- a/Debug/Middlewares/Third_Party/LwIP/src/core/ip.d
+++ b/Debug/Middlewares/Third_Party/LwIP/src/core/ip.d
@@ -25,6 +25,7 @@ Middlewares/Third_Party/LwIP/src/core/ip.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
@@ -32,6 +33,14 @@ Middlewares/Third_Party/LwIP/src/core/ip.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \
  ../Middlewares/Third_Party/LwIP/system/arch/cc.h \
@@ -81,6 +90,7 @@ Middlewares/Third_Party/LwIP/src/core/ip.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
@@ -88,6 +98,14 @@ Middlewares/Third_Party/LwIP/src/core/ip.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h:
 ../Middlewares/Third_Party/LwIP/system/arch/cc.h:
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/ip.o b/Debug/Middlewares/Third_Party/LwIP/src/core/ip.o
index e74c7ba..ecce88b 100644
Binary files a/Debug/Middlewares/Third_Party/LwIP/src/core/ip.o and b/Debug/Middlewares/Third_Party/LwIP/src/core/ip.o differ
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/autoip.d b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/autoip.d
index 5b1256f..6e48ff1 100644
--- a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/autoip.d
+++ b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/autoip.d
@@ -25,6 +25,7 @@ Middlewares/Third_Party/LwIP/src/core/ipv4/autoip.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
@@ -32,6 +33,14 @@ Middlewares/Third_Party/LwIP/src/core/ipv4/autoip.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \
  ../Middlewares/Third_Party/LwIP/system/arch/cc.h \
@@ -62,6 +71,7 @@ Middlewares/Third_Party/LwIP/src/core/ipv4/autoip.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
@@ -69,6 +79,14 @@ Middlewares/Third_Party/LwIP/src/core/ipv4/autoip.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h:
 ../Middlewares/Third_Party/LwIP/system/arch/cc.h:
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/autoip.o b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/autoip.o
index b789018..8a8a190 100644
Binary files a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/autoip.o and b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/autoip.o differ
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.d b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.d
index 045290c..8eb0266 100644
--- a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.d
+++ b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.d
@@ -25,6 +25,7 @@ Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
@@ -32,6 +33,14 @@ Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \
  ../Middlewares/Third_Party/LwIP/system/arch/cc.h \
@@ -62,6 +71,7 @@ Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
@@ -69,6 +79,14 @@ Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h:
 ../Middlewares/Third_Party/LwIP/system/arch/cc.h:
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.o b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.o
index 0d7a151..f38dd04 100644
Binary files a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.o and b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.o differ
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.d b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.d
index 97047f2..9f00bdb 100644
--- a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.d
+++ b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.d
@@ -25,6 +25,7 @@ Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
@@ -32,6 +33,14 @@ Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \
  ../Middlewares/Third_Party/LwIP/system/arch/cc.h \
@@ -87,6 +96,7 @@ Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
@@ -94,6 +104,14 @@ Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h:
 ../Middlewares/Third_Party/LwIP/system/arch/cc.h:
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.o b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.o
index e7dd609..8a23fe0 100644
Binary files a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.o and b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.o differ
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.cyclo b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.cyclo
index 4b9308c..509fac0 100644
--- a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.cyclo
+++ b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.cyclo
@@ -1,4 +1,4 @@
-../Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.c:80:1:icmp_input	19
+../Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.c:80:1:icmp_input	18
 ../Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.c:308:1:icmp_dest_unreach	1
 ../Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.c:323:1:icmp_time_exceeded	1
 ../Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.c:340:1:icmp_send_response	4
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.d b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.d
index c4579a9..ccfdc38 100644
--- a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.d
+++ b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.d
@@ -25,6 +25,7 @@ Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
@@ -32,6 +33,14 @@ Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \
  ../Middlewares/Third_Party/LwIP/system/arch/cc.h \
@@ -84,6 +93,7 @@ Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
@@ -91,6 +101,14 @@ Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h:
 ../Middlewares/Third_Party/LwIP/system/arch/cc.h:
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.o b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.o
index c846bb4..294e660 100644
Binary files a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.o and b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.o differ
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/igmp.d b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/igmp.d
index 2711320..1e92176 100644
--- a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/igmp.d
+++ b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/igmp.d
@@ -25,6 +25,7 @@ Middlewares/Third_Party/LwIP/src/core/ipv4/igmp.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
@@ -32,6 +33,14 @@ Middlewares/Third_Party/LwIP/src/core/ipv4/igmp.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \
  ../Middlewares/Third_Party/LwIP/system/arch/cc.h \
@@ -62,6 +71,7 @@ Middlewares/Third_Party/LwIP/src/core/ipv4/igmp.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
@@ -69,6 +79,14 @@ Middlewares/Third_Party/LwIP/src/core/ipv4/igmp.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h:
 ../Middlewares/Third_Party/LwIP/system/arch/cc.h:
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/igmp.o b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/igmp.o
index 4ee6e6a..35945a1 100644
Binary files a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/igmp.o and b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/igmp.o differ
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.d b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.d
index 6cd3580..dc6d855 100644
--- a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.d
+++ b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.d
@@ -25,6 +25,7 @@ Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
@@ -32,6 +33,14 @@ Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \
  ../Middlewares/Third_Party/LwIP/system/arch/cc.h \
@@ -95,6 +104,7 @@ Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
@@ -102,6 +112,14 @@ Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h:
 ../Middlewares/Third_Party/LwIP/system/arch/cc.h:
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.o b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.o
index 79a8149..370f5a0 100644
Binary files a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.o and b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.o differ
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.d b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.d
index ebf7acd..fb5be65 100644
--- a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.d
+++ b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.d
@@ -25,6 +25,7 @@ Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
@@ -32,6 +33,14 @@ Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \
  ../Middlewares/Third_Party/LwIP/system/arch/cc.h \
@@ -76,6 +85,7 @@ Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
@@ -83,6 +93,14 @@ Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h:
 ../Middlewares/Third_Party/LwIP/system/arch/cc.h:
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.o b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.o
index ea7e853..f235164 100644
Binary files a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.o and b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.o differ
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.d b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.d
index 1b5ee90..06b2d04 100644
--- a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.d
+++ b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.d
@@ -25,6 +25,7 @@ Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
@@ -32,6 +33,14 @@ Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \
  ../Middlewares/Third_Party/LwIP/system/arch/cc.h \
@@ -85,6 +94,7 @@ Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
@@ -92,6 +102,14 @@ Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h:
 ../Middlewares/Third_Party/LwIP/system/arch/cc.h:
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.o b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.o
index 77e1af3..fa9a39f 100644
Binary files a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.o and b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.o differ
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/subdir.mk b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/subdir.mk
index 89cd3dc..34d97f2 100644
--- a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/subdir.mk
+++ b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/subdir.mk
@@ -37,7 +37,7 @@ C_DEPS += \
 
 # Each subdirectory must supply rules for building sources it contributes
 Middlewares/Third_Party/LwIP/src/core/ipv4/%.o Middlewares/Third_Party/LwIP/src/core/ipv4/%.su Middlewares/Third_Party/LwIP/src/core/ipv4/%.cyclo: ../Middlewares/Third_Party/LwIP/src/core/ipv4/%.c Middlewares/Third_Party/LwIP/src/core/ipv4/subdir.mk
-	arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DDEBUG -DDATA_IN_D2_SRAM -DUSE_HAL_DRIVER -DSTM32H723xx -c -I../Core/Inc -I../Drivers/STM32H7xx_HAL_Driver/Inc -I../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32H7xx/Include -I../Drivers/CMSIS/Include -I../LWIP/App -I../LWIP/Target -I../Middlewares/Third_Party/LwIP/src/include -I../Middlewares/Third_Party/LwIP/system -I../Drivers/BSP/Components/lan8742 -I../Middlewares/Third_Party/LwIP/src/include/netif/ppp -I../Middlewares/Third_Party/LwIP/src/include/lwip -I../Middlewares/Third_Party/LwIP/src/include/lwip/apps -I../Middlewares/Third_Party/LwIP/src/include/lwip/priv -I../Middlewares/Third_Party/LwIP/src/include/lwip/prot -I../Middlewares/Third_Party/LwIP/src/include/netif -I../Middlewares/Third_Party/LwIP/src/include/compat/posix -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/arpa -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/net -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/sys -I../Middlewares/Third_Party/LwIP/src/include/compat/stdc -I../Middlewares/Third_Party/LwIP/system/arch -I"C:/_NoSleep/STM32/lwip_test/LWFTP" -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
+	arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DDEBUG -DDATA_IN_D2_SRAM -DUSE_HAL_DRIVER -DSTM32H723xx -c -I../Core/Inc -I../FATFS/Target -I../FATFS/App -I../LWIP/App -I../LWIP/Target -I../Middlewares/Third_Party/LwIP/src/include -I../Middlewares/Third_Party/LwIP/system -I../Drivers/STM32H7xx_HAL_Driver/Inc -I../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F -I../Middlewares/Third_Party/FatFs/src -I../Drivers/BSP/Components/lan8742 -I../Middlewares/Third_Party/LwIP/src/include/netif/ppp -I../Drivers/CMSIS/Device/ST/STM32H7xx/Include -I../Middlewares/Third_Party/LwIP/src/include/lwip -I../Middlewares/Third_Party/LwIP/src/include/lwip/apps -I../Middlewares/Third_Party/LwIP/src/include/lwip/priv -I../Middlewares/Third_Party/LwIP/src/include/lwip/prot -I../Middlewares/Third_Party/LwIP/src/include/netif -I../Middlewares/Third_Party/LwIP/src/include/compat/posix -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/arpa -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/net -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/sys -I../Middlewares/Third_Party/LwIP/src/include/compat/stdc -I../Middlewares/Third_Party/LwIP/system/arch -I../Drivers/CMSIS/Include -I"C:/_NoSleep/STM32/TBD_TaxiBoard/LWFTPC" -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
 
 clean: clean-Middlewares-2f-Third_Party-2f-LwIP-2f-src-2f-core-2f-ipv4
 
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/dhcp6.d b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/dhcp6.d
index 1df6c13..10aa96e 100644
--- a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/dhcp6.d
+++ b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/dhcp6.d
@@ -25,6 +25,7 @@ Middlewares/Third_Party/LwIP/src/core/ipv6/dhcp6.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
@@ -32,6 +33,14 @@ Middlewares/Third_Party/LwIP/src/core/ipv6/dhcp6.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \
  ../Middlewares/Third_Party/LwIP/system/arch/cc.h \
@@ -62,6 +71,7 @@ Middlewares/Third_Party/LwIP/src/core/ipv6/dhcp6.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
@@ -69,6 +79,14 @@ Middlewares/Third_Party/LwIP/src/core/ipv6/dhcp6.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h:
 ../Middlewares/Third_Party/LwIP/system/arch/cc.h:
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/dhcp6.o b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/dhcp6.o
index a31bb80..114d10a 100644
Binary files a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/dhcp6.o and b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/dhcp6.o differ
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/ethip6.d b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/ethip6.d
index 1795d63..382f439 100644
--- a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/ethip6.d
+++ b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/ethip6.d
@@ -25,6 +25,7 @@ Middlewares/Third_Party/LwIP/src/core/ipv6/ethip6.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
@@ -32,6 +33,14 @@ Middlewares/Third_Party/LwIP/src/core/ipv6/ethip6.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \
  ../Middlewares/Third_Party/LwIP/system/arch/cc.h \
@@ -62,6 +71,7 @@ Middlewares/Third_Party/LwIP/src/core/ipv6/ethip6.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
@@ -69,6 +79,14 @@ Middlewares/Third_Party/LwIP/src/core/ipv6/ethip6.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h:
 ../Middlewares/Third_Party/LwIP/system/arch/cc.h:
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/ethip6.o b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/ethip6.o
index ab0e3c1..b260a58 100644
Binary files a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/ethip6.o and b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/ethip6.o differ
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/icmp6.d b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/icmp6.d
index cc3d9e6..e4fd0e8 100644
--- a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/icmp6.d
+++ b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/icmp6.d
@@ -25,6 +25,7 @@ Middlewares/Third_Party/LwIP/src/core/ipv6/icmp6.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
@@ -32,6 +33,14 @@ Middlewares/Third_Party/LwIP/src/core/ipv6/icmp6.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \
  ../Middlewares/Third_Party/LwIP/system/arch/cc.h \
@@ -62,6 +71,7 @@ Middlewares/Third_Party/LwIP/src/core/ipv6/icmp6.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
@@ -69,6 +79,14 @@ Middlewares/Third_Party/LwIP/src/core/ipv6/icmp6.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h:
 ../Middlewares/Third_Party/LwIP/system/arch/cc.h:
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/icmp6.o b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/icmp6.o
index e648dd0..418b8c4 100644
Binary files a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/icmp6.o and b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/icmp6.o differ
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/inet6.d b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/inet6.d
index b3446db..2624524 100644
--- a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/inet6.d
+++ b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/inet6.d
@@ -25,6 +25,7 @@ Middlewares/Third_Party/LwIP/src/core/ipv6/inet6.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
@@ -32,6 +33,14 @@ Middlewares/Third_Party/LwIP/src/core/ipv6/inet6.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \
  ../Middlewares/Third_Party/LwIP/system/arch/cc.h \
@@ -62,6 +71,7 @@ Middlewares/Third_Party/LwIP/src/core/ipv6/inet6.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
@@ -69,6 +79,14 @@ Middlewares/Third_Party/LwIP/src/core/ipv6/inet6.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h:
 ../Middlewares/Third_Party/LwIP/system/arch/cc.h:
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/inet6.o b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/inet6.o
index 0279f10..993517b 100644
Binary files a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/inet6.o and b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/inet6.o differ
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/ip6.d b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/ip6.d
index 8bf53c7..078a105 100644
--- a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/ip6.d
+++ b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/ip6.d
@@ -25,6 +25,7 @@ Middlewares/Third_Party/LwIP/src/core/ipv6/ip6.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
@@ -32,6 +33,14 @@ Middlewares/Third_Party/LwIP/src/core/ipv6/ip6.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \
  ../Middlewares/Third_Party/LwIP/system/arch/cc.h \
@@ -62,6 +71,7 @@ Middlewares/Third_Party/LwIP/src/core/ipv6/ip6.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
@@ -69,6 +79,14 @@ Middlewares/Third_Party/LwIP/src/core/ipv6/ip6.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h:
 ../Middlewares/Third_Party/LwIP/system/arch/cc.h:
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/ip6.o b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/ip6.o
index 89b3c1a..d45b66c 100644
Binary files a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/ip6.o and b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/ip6.o differ
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_addr.d b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_addr.d
index 8347601..720248a 100644
--- a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_addr.d
+++ b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_addr.d
@@ -25,6 +25,7 @@ Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_addr.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
@@ -32,6 +33,14 @@ Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_addr.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \
  ../Middlewares/Third_Party/LwIP/system/arch/cc.h \
@@ -62,6 +71,7 @@ Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_addr.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
@@ -69,6 +79,14 @@ Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_addr.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h:
 ../Middlewares/Third_Party/LwIP/system/arch/cc.h:
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_addr.o b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_addr.o
index f316741..4f7782e 100644
Binary files a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_addr.o and b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_addr.o differ
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_frag.d b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_frag.d
index 2c1e0c6..1419437 100644
--- a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_frag.d
+++ b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_frag.d
@@ -25,6 +25,7 @@ Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_frag.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
@@ -32,6 +33,14 @@ Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_frag.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \
  ../Middlewares/Third_Party/LwIP/system/arch/cc.h \
@@ -85,6 +94,7 @@ Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_frag.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
@@ -92,6 +102,14 @@ Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_frag.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h:
 ../Middlewares/Third_Party/LwIP/system/arch/cc.h:
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_frag.o b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_frag.o
index 2881bcc..916c246 100644
Binary files a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_frag.o and b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_frag.o differ
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/mld6.d b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/mld6.d
index 90ecb24..77959eb 100644
--- a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/mld6.d
+++ b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/mld6.d
@@ -25,6 +25,7 @@ Middlewares/Third_Party/LwIP/src/core/ipv6/mld6.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
@@ -32,6 +33,14 @@ Middlewares/Third_Party/LwIP/src/core/ipv6/mld6.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \
  ../Middlewares/Third_Party/LwIP/system/arch/cc.h \
@@ -62,6 +71,7 @@ Middlewares/Third_Party/LwIP/src/core/ipv6/mld6.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
@@ -69,6 +79,14 @@ Middlewares/Third_Party/LwIP/src/core/ipv6/mld6.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h:
 ../Middlewares/Third_Party/LwIP/system/arch/cc.h:
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/mld6.o b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/mld6.o
index 4938a51..9e01678 100644
Binary files a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/mld6.o and b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/mld6.o differ
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/nd6.d b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/nd6.d
index 54e2af6..07c5e9f 100644
--- a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/nd6.d
+++ b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/nd6.d
@@ -25,6 +25,7 @@ Middlewares/Third_Party/LwIP/src/core/ipv6/nd6.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
@@ -32,6 +33,14 @@ Middlewares/Third_Party/LwIP/src/core/ipv6/nd6.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \
  ../Middlewares/Third_Party/LwIP/system/arch/cc.h \
@@ -62,6 +71,7 @@ Middlewares/Third_Party/LwIP/src/core/ipv6/nd6.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
@@ -69,6 +79,14 @@ Middlewares/Third_Party/LwIP/src/core/ipv6/nd6.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h:
 ../Middlewares/Third_Party/LwIP/system/arch/cc.h:
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/nd6.o b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/nd6.o
index 054ddb2..ebc625b 100644
Binary files a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/nd6.o and b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/nd6.o differ
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/subdir.mk b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/subdir.mk
index 60ec069..c9d6e3f 100644
--- a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/subdir.mk
+++ b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/subdir.mk
@@ -40,7 +40,7 @@ C_DEPS += \
 
 # Each subdirectory must supply rules for building sources it contributes
 Middlewares/Third_Party/LwIP/src/core/ipv6/%.o Middlewares/Third_Party/LwIP/src/core/ipv6/%.su Middlewares/Third_Party/LwIP/src/core/ipv6/%.cyclo: ../Middlewares/Third_Party/LwIP/src/core/ipv6/%.c Middlewares/Third_Party/LwIP/src/core/ipv6/subdir.mk
-	arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DDEBUG -DDATA_IN_D2_SRAM -DUSE_HAL_DRIVER -DSTM32H723xx -c -I../Core/Inc -I../Drivers/STM32H7xx_HAL_Driver/Inc -I../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32H7xx/Include -I../Drivers/CMSIS/Include -I../LWIP/App -I../LWIP/Target -I../Middlewares/Third_Party/LwIP/src/include -I../Middlewares/Third_Party/LwIP/system -I../Drivers/BSP/Components/lan8742 -I../Middlewares/Third_Party/LwIP/src/include/netif/ppp -I../Middlewares/Third_Party/LwIP/src/include/lwip -I../Middlewares/Third_Party/LwIP/src/include/lwip/apps -I../Middlewares/Third_Party/LwIP/src/include/lwip/priv -I../Middlewares/Third_Party/LwIP/src/include/lwip/prot -I../Middlewares/Third_Party/LwIP/src/include/netif -I../Middlewares/Third_Party/LwIP/src/include/compat/posix -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/arpa -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/net -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/sys -I../Middlewares/Third_Party/LwIP/src/include/compat/stdc -I../Middlewares/Third_Party/LwIP/system/arch -I"C:/_NoSleep/STM32/lwip_test/LWFTP" -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
+	arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DDEBUG -DDATA_IN_D2_SRAM -DUSE_HAL_DRIVER -DSTM32H723xx -c -I../Core/Inc -I../FATFS/Target -I../FATFS/App -I../LWIP/App -I../LWIP/Target -I../Middlewares/Third_Party/LwIP/src/include -I../Middlewares/Third_Party/LwIP/system -I../Drivers/STM32H7xx_HAL_Driver/Inc -I../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F -I../Middlewares/Third_Party/FatFs/src -I../Drivers/BSP/Components/lan8742 -I../Middlewares/Third_Party/LwIP/src/include/netif/ppp -I../Drivers/CMSIS/Device/ST/STM32H7xx/Include -I../Middlewares/Third_Party/LwIP/src/include/lwip -I../Middlewares/Third_Party/LwIP/src/include/lwip/apps -I../Middlewares/Third_Party/LwIP/src/include/lwip/priv -I../Middlewares/Third_Party/LwIP/src/include/lwip/prot -I../Middlewares/Third_Party/LwIP/src/include/netif -I../Middlewares/Third_Party/LwIP/src/include/compat/posix -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/arpa -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/net -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/sys -I../Middlewares/Third_Party/LwIP/src/include/compat/stdc -I../Middlewares/Third_Party/LwIP/system/arch -I../Drivers/CMSIS/Include -I"C:/_NoSleep/STM32/TBD_TaxiBoard/LWFTPC" -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
 
 clean: clean-Middlewares-2f-Third_Party-2f-LwIP-2f-src-2f-core-2f-ipv6
 
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/mem.cyclo b/Debug/Middlewares/Third_Party/LwIP/src/core/mem.cyclo
index 63b0381..0f55d90 100644
--- a/Debug/Middlewares/Third_Party/LwIP/src/core/mem.cyclo
+++ b/Debug/Middlewares/Third_Party/LwIP/src/core/mem.cyclo
@@ -1,7 +1,7 @@
 ../Middlewares/Third_Party/LwIP/src/core/mem.c:451:1:ptr_to_mem	1
 ../Middlewares/Third_Party/LwIP/src/core/mem.c:457:1:mem_to_ptr	1
 ../Middlewares/Third_Party/LwIP/src/core/mem.c:474:1:plug_holes	14
-../Middlewares/Third_Party/LwIP/src/core/mem.c:516:1:mem_init	1
+../Middlewares/Third_Party/LwIP/src/core/mem.c:516:1:mem_init	2
 ../Middlewares/Third_Party/LwIP/src/core/mem.c:551:1:mem_link_valid	7
 ../Middlewares/Third_Party/LwIP/src/core/mem.c:617:1:mem_free	8
 ../Middlewares/Third_Party/LwIP/src/core/mem.c:699:1:mem_trim	19
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/mem.d b/Debug/Middlewares/Third_Party/LwIP/src/core/mem.d
index 8a23b73..6e63024 100644
--- a/Debug/Middlewares/Third_Party/LwIP/src/core/mem.d
+++ b/Debug/Middlewares/Third_Party/LwIP/src/core/mem.d
@@ -25,6 +25,7 @@ Middlewares/Third_Party/LwIP/src/core/mem.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
@@ -32,6 +33,14 @@ Middlewares/Third_Party/LwIP/src/core/mem.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \
  ../Middlewares/Third_Party/LwIP/system/arch/cc.h \
@@ -39,12 +48,30 @@ Middlewares/Third_Party/LwIP/src/core/mem.o: \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/sys.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/err.h \
+ ../Middlewares/Third_Party/LwIP/system/arch/sys_arch.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h \
+ ../Core/Inc/FreeRTOSConfig.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/list.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h \
- ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h \
- ../Middlewares/Third_Party/LwIP/src/include/lwip/err.h
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h
 ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h:
 ../LWIP/Target/lwipopts.h:
 ../Core/Inc/main.h:
@@ -71,6 +98,7 @@ Middlewares/Third_Party/LwIP/src/core/mem.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
@@ -78,6 +106,14 @@ Middlewares/Third_Party/LwIP/src/core/mem.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h:
 ../Middlewares/Third_Party/LwIP/system/arch/cc.h:
@@ -85,9 +121,27 @@ Middlewares/Third_Party/LwIP/src/core/mem.o: \
 ../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/sys.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/err.h:
+../Middlewares/Third_Party/LwIP/system/arch/sys_arch.h:
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h:
+../Core/Inc/FreeRTOSConfig.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h:
+../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/task.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/list.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/task.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h:
-../Middlewares/Third_Party/LwIP/src/include/lwip/err.h:
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/mem.o b/Debug/Middlewares/Third_Party/LwIP/src/core/mem.o
index 7eb6767..8e33236 100644
Binary files a/Debug/Middlewares/Third_Party/LwIP/src/core/mem.o and b/Debug/Middlewares/Third_Party/LwIP/src/core/mem.o differ
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/mem.su b/Debug/Middlewares/Third_Party/LwIP/src/core/mem.su
index 67591ad..cf61ec5 100644
--- a/Debug/Middlewares/Third_Party/LwIP/src/core/mem.su
+++ b/Debug/Middlewares/Third_Party/LwIP/src/core/mem.su
@@ -3,7 +3,7 @@
 ../Middlewares/Third_Party/LwIP/src/core/mem.c:474:1:plug_holes	32	static
 ../Middlewares/Third_Party/LwIP/src/core/mem.c:516:1:mem_init	16	static
 ../Middlewares/Third_Party/LwIP/src/core/mem.c:551:1:mem_link_valid	32	static
-../Middlewares/Third_Party/LwIP/src/core/mem.c:617:1:mem_free	24	static
+../Middlewares/Third_Party/LwIP/src/core/mem.c:617:1:mem_free	40	static
 ../Middlewares/Third_Party/LwIP/src/core/mem.c:699:1:mem_trim	40	static
 ../Middlewares/Third_Party/LwIP/src/core/mem.c:831:1:mem_malloc	40	static
 ../Middlewares/Third_Party/LwIP/src/core/mem.c:999:1:mem_calloc	24	static
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/memp.d b/Debug/Middlewares/Third_Party/LwIP/src/core/memp.d
index 331fecd..c5ff0cc 100644
--- a/Debug/Middlewares/Third_Party/LwIP/src/core/memp.d
+++ b/Debug/Middlewares/Third_Party/LwIP/src/core/memp.d
@@ -25,6 +25,7 @@ Middlewares/Third_Party/LwIP/src/core/memp.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
@@ -32,6 +33,14 @@ Middlewares/Third_Party/LwIP/src/core/memp.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \
  ../Middlewares/Third_Party/LwIP/system/arch/cc.h \
@@ -43,8 +52,26 @@ Middlewares/Third_Party/LwIP/src/core/memp.o: \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/sys.h \
- ../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/err.h \
+ ../Middlewares/Third_Party/LwIP/system/arch/sys_arch.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h \
+ ../Core/Inc/FreeRTOSConfig.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/list.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/raw.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/udp.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/netif.h \
@@ -70,14 +97,18 @@ Middlewares/Third_Party/LwIP/src/core/memp.o: \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/netbuf.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/api.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/tcpip_priv.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/tcpip.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/timeouts.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/api_msg.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/igmp.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/sockets_priv.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/sockets.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/inet.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/errno.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/etharp.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ethernet.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ieee.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/etharp.h \
- ../Middlewares/Third_Party/LwIP/src/include/lwip/timeouts.h \
  ../Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_opts.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/netdb.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/dns.h \
@@ -110,6 +141,7 @@ Middlewares/Third_Party/LwIP/src/core/memp.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
@@ -117,6 +149,14 @@ Middlewares/Third_Party/LwIP/src/core/memp.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h:
 ../Middlewares/Third_Party/LwIP/system/arch/cc.h:
@@ -128,8 +168,26 @@ Middlewares/Third_Party/LwIP/src/core/memp.o: \
 ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/sys.h:
-../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/err.h:
+../Middlewares/Third_Party/LwIP/system/arch/sys_arch.h:
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h:
+../Core/Inc/FreeRTOSConfig.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h:
+../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/task.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/list.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/task.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/raw.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/udp.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/netif.h:
@@ -155,14 +213,18 @@ Middlewares/Third_Party/LwIP/src/core/memp.o: \
 ../Middlewares/Third_Party/LwIP/src/include/lwip/netbuf.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/api.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/tcpip_priv.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/tcpip.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/timeouts.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/api_msg.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/igmp.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/sockets_priv.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/sockets.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/inet.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/errno.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/etharp.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ethernet.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ieee.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/etharp.h:
-../Middlewares/Third_Party/LwIP/src/include/lwip/timeouts.h:
 ../Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_opts.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/netdb.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/dns.h:
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/memp.o b/Debug/Middlewares/Third_Party/LwIP/src/core/memp.o
index 4d887b6..b572111 100644
Binary files a/Debug/Middlewares/Third_Party/LwIP/src/core/memp.o and b/Debug/Middlewares/Third_Party/LwIP/src/core/memp.o differ
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/netif.d b/Debug/Middlewares/Third_Party/LwIP/src/core/netif.d
index 782f977..e53f0b4 100644
--- a/Debug/Middlewares/Third_Party/LwIP/src/core/netif.d
+++ b/Debug/Middlewares/Third_Party/LwIP/src/core/netif.d
@@ -25,6 +25,7 @@ Middlewares/Third_Party/LwIP/src/core/netif.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
@@ -32,6 +33,14 @@ Middlewares/Third_Party/LwIP/src/core/netif.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \
  ../Middlewares/Third_Party/LwIP/system/arch/cc.h \
@@ -71,6 +80,24 @@ Middlewares/Third_Party/LwIP/src/core/netif.o: \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ieee.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/etharp.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/sys.h \
+ ../Middlewares/Third_Party/LwIP/system/arch/sys_arch.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h \
+ ../Core/Inc/FreeRTOSConfig.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/list.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h \
  ../Middlewares/Third_Party/LwIP/src/include/netif/ethernet.h
 ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h:
 ../LWIP/Target/lwipopts.h:
@@ -98,6 +125,7 @@ Middlewares/Third_Party/LwIP/src/core/netif.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
@@ -105,6 +133,14 @@ Middlewares/Third_Party/LwIP/src/core/netif.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h:
 ../Middlewares/Third_Party/LwIP/system/arch/cc.h:
@@ -144,4 +180,22 @@ Middlewares/Third_Party/LwIP/src/core/netif.o: \
 ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ieee.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/etharp.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/sys.h:
+../Middlewares/Third_Party/LwIP/system/arch/sys_arch.h:
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h:
+../Core/Inc/FreeRTOSConfig.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h:
+../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/task.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/list.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/task.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h:
 ../Middlewares/Third_Party/LwIP/src/include/netif/ethernet.h:
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/netif.o b/Debug/Middlewares/Third_Party/LwIP/src/core/netif.o
index 751692a..ffc0f2b 100644
Binary files a/Debug/Middlewares/Third_Party/LwIP/src/core/netif.o and b/Debug/Middlewares/Third_Party/LwIP/src/core/netif.o differ
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/pbuf.cyclo b/Debug/Middlewares/Third_Party/LwIP/src/core/pbuf.cyclo
index f358553..d368360 100644
--- a/Debug/Middlewares/Third_Party/LwIP/src/core/pbuf.cyclo
+++ b/Debug/Middlewares/Third_Party/LwIP/src/core/pbuf.cyclo
@@ -1,5 +1,6 @@
 ../Middlewares/Third_Party/LwIP/src/core/pbuf.c:128:1:pbuf_free_ooseq	3
-../Middlewares/Third_Party/LwIP/src/core/pbuf.c:157:1:pbuf_pool_is_empty	1
+../Middlewares/Third_Party/LwIP/src/core/pbuf.c:148:1:pbuf_free_ooseq_callback	1
+../Middlewares/Third_Party/LwIP/src/core/pbuf.c:157:1:pbuf_pool_is_empty	3
 ../Middlewares/Third_Party/LwIP/src/core/pbuf.c:179:1:pbuf_init_alloced_pbuf	1
 ../Middlewares/Third_Party/LwIP/src/core/pbuf.c:224:1:pbuf_alloc	17
 ../Middlewares/Third_Party/LwIP/src/core/pbuf.c:327:1:pbuf_alloc_reference	4
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/pbuf.d b/Debug/Middlewares/Third_Party/LwIP/src/core/pbuf.d
index 0d817c8..9bcc062 100644
--- a/Debug/Middlewares/Third_Party/LwIP/src/core/pbuf.d
+++ b/Debug/Middlewares/Third_Party/LwIP/src/core/pbuf.d
@@ -25,6 +25,7 @@ Middlewares/Third_Party/LwIP/src/core/pbuf.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
@@ -32,6 +33,14 @@ Middlewares/Third_Party/LwIP/src/core/pbuf.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \
  ../Middlewares/Third_Party/LwIP/system/arch/cc.h \
@@ -46,6 +55,24 @@ Middlewares/Third_Party/LwIP/src/core/pbuf.o: \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/sys.h \
+ ../Middlewares/Third_Party/LwIP/system/arch/sys_arch.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h \
+ ../Core/Inc/FreeRTOSConfig.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/list.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/netif.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h \
@@ -61,7 +88,9 @@ Middlewares/Third_Party/LwIP/src/core/pbuf.o: \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/icmp.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/icmp.h \
- ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/tcp.h
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/tcp.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/tcpip.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/timeouts.h
 ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h:
 ../LWIP/Target/lwipopts.h:
 ../Core/Inc/main.h:
@@ -88,6 +117,7 @@ Middlewares/Third_Party/LwIP/src/core/pbuf.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
@@ -95,6 +125,14 @@ Middlewares/Third_Party/LwIP/src/core/pbuf.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h:
 ../Middlewares/Third_Party/LwIP/system/arch/cc.h:
@@ -109,6 +147,24 @@ Middlewares/Third_Party/LwIP/src/core/pbuf.o: \
 ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/sys.h:
+../Middlewares/Third_Party/LwIP/system/arch/sys_arch.h:
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h:
+../Core/Inc/FreeRTOSConfig.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h:
+../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/task.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/list.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/task.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/netif.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h:
@@ -125,3 +181,5 @@ Middlewares/Third_Party/LwIP/src/core/pbuf.o: \
 ../Middlewares/Third_Party/LwIP/src/include/lwip/icmp.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/icmp.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/tcp.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/tcpip.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/timeouts.h:
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/pbuf.o b/Debug/Middlewares/Third_Party/LwIP/src/core/pbuf.o
index 4419ef6..637c0f5 100644
Binary files a/Debug/Middlewares/Third_Party/LwIP/src/core/pbuf.o and b/Debug/Middlewares/Third_Party/LwIP/src/core/pbuf.o differ
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/pbuf.su b/Debug/Middlewares/Third_Party/LwIP/src/core/pbuf.su
index 7ff14ea..c1cc3a5 100644
--- a/Debug/Middlewares/Third_Party/LwIP/src/core/pbuf.su
+++ b/Debug/Middlewares/Third_Party/LwIP/src/core/pbuf.su
@@ -1,5 +1,6 @@
 ../Middlewares/Third_Party/LwIP/src/core/pbuf.c:128:1:pbuf_free_ooseq	16	static
-../Middlewares/Third_Party/LwIP/src/core/pbuf.c:157:1:pbuf_pool_is_empty	4	static
+../Middlewares/Third_Party/LwIP/src/core/pbuf.c:148:1:pbuf_free_ooseq_callback	16	static
+../Middlewares/Third_Party/LwIP/src/core/pbuf.c:157:1:pbuf_pool_is_empty	16	static
 ../Middlewares/Third_Party/LwIP/src/core/pbuf.c:179:1:pbuf_init_alloced_pbuf	24	static
 ../Middlewares/Third_Party/LwIP/src/core/pbuf.c:224:1:pbuf_alloc	56	static
 ../Middlewares/Third_Party/LwIP/src/core/pbuf.c:327:1:pbuf_alloc_reference	32	static
@@ -13,9 +14,9 @@
 ../Middlewares/Third_Party/LwIP/src/core/pbuf.c:646:1:pbuf_header	16	static
 ../Middlewares/Third_Party/LwIP/src/core/pbuf.c:656:1:pbuf_header_force	16	static
 ../Middlewares/Third_Party/LwIP/src/core/pbuf.c:671:1:pbuf_free_header	32	static
-../Middlewares/Third_Party/LwIP/src/core/pbuf.c:725:1:pbuf_free	32	static
+../Middlewares/Third_Party/LwIP/src/core/pbuf.c:725:1:pbuf_free	40	static
 ../Middlewares/Third_Party/LwIP/src/core/pbuf.c:809:1:pbuf_clen	24	static
-../Middlewares/Third_Party/LwIP/src/core/pbuf.c:829:1:pbuf_ref	16	static
+../Middlewares/Third_Party/LwIP/src/core/pbuf.c:829:1:pbuf_ref	24	static
 ../Middlewares/Third_Party/LwIP/src/core/pbuf.c:853:1:pbuf_cat	24	static
 ../Middlewares/Third_Party/LwIP/src/core/pbuf.c:895:1:pbuf_chain	16	static
 ../Middlewares/Third_Party/LwIP/src/core/pbuf.c:912:1:pbuf_dechain	24	static
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/raw.d b/Debug/Middlewares/Third_Party/LwIP/src/core/raw.d
index bf86a33..1c76d04 100644
--- a/Debug/Middlewares/Third_Party/LwIP/src/core/raw.d
+++ b/Debug/Middlewares/Third_Party/LwIP/src/core/raw.d
@@ -25,6 +25,7 @@ Middlewares/Third_Party/LwIP/src/core/raw.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
@@ -32,6 +33,14 @@ Middlewares/Third_Party/LwIP/src/core/raw.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \
  ../Middlewares/Third_Party/LwIP/system/arch/cc.h \
@@ -62,6 +71,7 @@ Middlewares/Third_Party/LwIP/src/core/raw.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
@@ -69,6 +79,14 @@ Middlewares/Third_Party/LwIP/src/core/raw.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h:
 ../Middlewares/Third_Party/LwIP/system/arch/cc.h:
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/raw.o b/Debug/Middlewares/Third_Party/LwIP/src/core/raw.o
index f9db435..4b51d06 100644
Binary files a/Debug/Middlewares/Third_Party/LwIP/src/core/raw.o and b/Debug/Middlewares/Third_Party/LwIP/src/core/raw.o differ
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/stats.d b/Debug/Middlewares/Third_Party/LwIP/src/core/stats.d
index 3326bef..964667b 100644
--- a/Debug/Middlewares/Third_Party/LwIP/src/core/stats.d
+++ b/Debug/Middlewares/Third_Party/LwIP/src/core/stats.d
@@ -25,6 +25,7 @@ Middlewares/Third_Party/LwIP/src/core/stats.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
@@ -32,6 +33,14 @@ Middlewares/Third_Party/LwIP/src/core/stats.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \
  ../Middlewares/Third_Party/LwIP/system/arch/cc.h \
@@ -62,6 +71,7 @@ Middlewares/Third_Party/LwIP/src/core/stats.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
@@ -69,6 +79,14 @@ Middlewares/Third_Party/LwIP/src/core/stats.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h:
 ../Middlewares/Third_Party/LwIP/system/arch/cc.h:
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/stats.o b/Debug/Middlewares/Third_Party/LwIP/src/core/stats.o
index 8d53158..ae42d0b 100644
Binary files a/Debug/Middlewares/Third_Party/LwIP/src/core/stats.o and b/Debug/Middlewares/Third_Party/LwIP/src/core/stats.o differ
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/subdir.mk b/Debug/Middlewares/Third_Party/LwIP/src/core/subdir.mk
index 3d642f1..bb2c224 100644
--- a/Debug/Middlewares/Third_Party/LwIP/src/core/subdir.mk
+++ b/Debug/Middlewares/Third_Party/LwIP/src/core/subdir.mk
@@ -73,7 +73,7 @@ C_DEPS += \
 
 # Each subdirectory must supply rules for building sources it contributes
 Middlewares/Third_Party/LwIP/src/core/%.o Middlewares/Third_Party/LwIP/src/core/%.su Middlewares/Third_Party/LwIP/src/core/%.cyclo: ../Middlewares/Third_Party/LwIP/src/core/%.c Middlewares/Third_Party/LwIP/src/core/subdir.mk
-	arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DDEBUG -DDATA_IN_D2_SRAM -DUSE_HAL_DRIVER -DSTM32H723xx -c -I../Core/Inc -I../Drivers/STM32H7xx_HAL_Driver/Inc -I../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32H7xx/Include -I../Drivers/CMSIS/Include -I../LWIP/App -I../LWIP/Target -I../Middlewares/Third_Party/LwIP/src/include -I../Middlewares/Third_Party/LwIP/system -I../Drivers/BSP/Components/lan8742 -I../Middlewares/Third_Party/LwIP/src/include/netif/ppp -I../Middlewares/Third_Party/LwIP/src/include/lwip -I../Middlewares/Third_Party/LwIP/src/include/lwip/apps -I../Middlewares/Third_Party/LwIP/src/include/lwip/priv -I../Middlewares/Third_Party/LwIP/src/include/lwip/prot -I../Middlewares/Third_Party/LwIP/src/include/netif -I../Middlewares/Third_Party/LwIP/src/include/compat/posix -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/arpa -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/net -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/sys -I../Middlewares/Third_Party/LwIP/src/include/compat/stdc -I../Middlewares/Third_Party/LwIP/system/arch -I"C:/_NoSleep/STM32/lwip_test/LWFTP" -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
+	arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DDEBUG -DDATA_IN_D2_SRAM -DUSE_HAL_DRIVER -DSTM32H723xx -c -I../Core/Inc -I../FATFS/Target -I../FATFS/App -I../LWIP/App -I../LWIP/Target -I../Middlewares/Third_Party/LwIP/src/include -I../Middlewares/Third_Party/LwIP/system -I../Drivers/STM32H7xx_HAL_Driver/Inc -I../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F -I../Middlewares/Third_Party/FatFs/src -I../Drivers/BSP/Components/lan8742 -I../Middlewares/Third_Party/LwIP/src/include/netif/ppp -I../Drivers/CMSIS/Device/ST/STM32H7xx/Include -I../Middlewares/Third_Party/LwIP/src/include/lwip -I../Middlewares/Third_Party/LwIP/src/include/lwip/apps -I../Middlewares/Third_Party/LwIP/src/include/lwip/priv -I../Middlewares/Third_Party/LwIP/src/include/lwip/prot -I../Middlewares/Third_Party/LwIP/src/include/netif -I../Middlewares/Third_Party/LwIP/src/include/compat/posix -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/arpa -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/net -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/sys -I../Middlewares/Third_Party/LwIP/src/include/compat/stdc -I../Middlewares/Third_Party/LwIP/system/arch -I../Drivers/CMSIS/Include -I"C:/_NoSleep/STM32/TBD_TaxiBoard/LWFTPC" -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
 
 clean: clean-Middlewares-2f-Third_Party-2f-LwIP-2f-src-2f-core
 
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/sys.cyclo b/Debug/Middlewares/Third_Party/LwIP/src/core/sys.cyclo
index e69de29..89b26d7 100644
--- a/Debug/Middlewares/Third_Party/LwIP/src/core/sys.cyclo
+++ b/Debug/Middlewares/Third_Party/LwIP/src/core/sys.cyclo
@@ -0,0 +1 @@
+../Middlewares/Third_Party/LwIP/src/core/sys.c:135:1:sys_msleep	3
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/sys.d b/Debug/Middlewares/Third_Party/LwIP/src/core/sys.d
index a69a8b2..11c6eac 100644
--- a/Debug/Middlewares/Third_Party/LwIP/src/core/sys.d
+++ b/Debug/Middlewares/Third_Party/LwIP/src/core/sys.d
@@ -25,6 +25,7 @@ Middlewares/Third_Party/LwIP/src/core/sys.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
@@ -32,11 +33,38 @@ Middlewares/Third_Party/LwIP/src/core/sys.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \
  ../Middlewares/Third_Party/LwIP/system/arch/cc.h \
  ../Middlewares/Third_Party/LwIP/system/arch/cpu.h \
- ../Middlewares/Third_Party/LwIP/src/include/lwip/sys.h
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/sys.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/err.h \
+ ../Middlewares/Third_Party/LwIP/system/arch/sys_arch.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h \
+ ../Core/Inc/FreeRTOSConfig.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/list.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h
 ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h:
 ../LWIP/Target/lwipopts.h:
 ../Core/Inc/main.h:
@@ -63,6 +91,7 @@ Middlewares/Third_Party/LwIP/src/core/sys.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
@@ -70,8 +99,35 @@ Middlewares/Third_Party/LwIP/src/core/sys.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h:
 ../Middlewares/Third_Party/LwIP/system/arch/cc.h:
 ../Middlewares/Third_Party/LwIP/system/arch/cpu.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/sys.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/err.h:
+../Middlewares/Third_Party/LwIP/system/arch/sys_arch.h:
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h:
+../Core/Inc/FreeRTOSConfig.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h:
+../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/task.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/list.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/task.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h:
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/sys.o b/Debug/Middlewares/Third_Party/LwIP/src/core/sys.o
index 3931e9c..3fda8db 100644
Binary files a/Debug/Middlewares/Third_Party/LwIP/src/core/sys.o and b/Debug/Middlewares/Third_Party/LwIP/src/core/sys.o differ
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/sys.su b/Debug/Middlewares/Third_Party/LwIP/src/core/sys.su
index e69de29..d5daec3 100644
--- a/Debug/Middlewares/Third_Party/LwIP/src/core/sys.su
+++ b/Debug/Middlewares/Third_Party/LwIP/src/core/sys.su
@@ -0,0 +1 @@
+../Middlewares/Third_Party/LwIP/src/core/sys.c:135:1:sys_msleep	24	static
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/tcp.d b/Debug/Middlewares/Third_Party/LwIP/src/core/tcp.d
index 08e16b4..a32b77b 100644
--- a/Debug/Middlewares/Third_Party/LwIP/src/core/tcp.d
+++ b/Debug/Middlewares/Third_Party/LwIP/src/core/tcp.d
@@ -25,6 +25,7 @@ Middlewares/Third_Party/LwIP/src/core/tcp.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
@@ -32,6 +33,14 @@ Middlewares/Third_Party/LwIP/src/core/tcp.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \
  ../Middlewares/Third_Party/LwIP/system/arch/cc.h \
@@ -88,6 +97,7 @@ Middlewares/Third_Party/LwIP/src/core/tcp.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
@@ -95,6 +105,14 @@ Middlewares/Third_Party/LwIP/src/core/tcp.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h:
 ../Middlewares/Third_Party/LwIP/system/arch/cc.h:
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/tcp.o b/Debug/Middlewares/Third_Party/LwIP/src/core/tcp.o
index a4aeb91..431a0c1 100644
Binary files a/Debug/Middlewares/Third_Party/LwIP/src/core/tcp.o and b/Debug/Middlewares/Third_Party/LwIP/src/core/tcp.o differ
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/tcp_in.d b/Debug/Middlewares/Third_Party/LwIP/src/core/tcp_in.d
index eff388a..19c242c 100644
--- a/Debug/Middlewares/Third_Party/LwIP/src/core/tcp_in.d
+++ b/Debug/Middlewares/Third_Party/LwIP/src/core/tcp_in.d
@@ -25,6 +25,7 @@ Middlewares/Third_Party/LwIP/src/core/tcp_in.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
@@ -32,6 +33,14 @@ Middlewares/Third_Party/LwIP/src/core/tcp_in.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \
  ../Middlewares/Third_Party/LwIP/system/arch/cc.h \
@@ -89,6 +98,7 @@ Middlewares/Third_Party/LwIP/src/core/tcp_in.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
@@ -96,6 +106,14 @@ Middlewares/Third_Party/LwIP/src/core/tcp_in.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h:
 ../Middlewares/Third_Party/LwIP/system/arch/cc.h:
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/tcp_in.o b/Debug/Middlewares/Third_Party/LwIP/src/core/tcp_in.o
index 2ce9238..2e5a17d 100644
Binary files a/Debug/Middlewares/Third_Party/LwIP/src/core/tcp_in.o and b/Debug/Middlewares/Third_Party/LwIP/src/core/tcp_in.o differ
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/tcp_out.d b/Debug/Middlewares/Third_Party/LwIP/src/core/tcp_out.d
index 12fe08a..c147897 100644
--- a/Debug/Middlewares/Third_Party/LwIP/src/core/tcp_out.d
+++ b/Debug/Middlewares/Third_Party/LwIP/src/core/tcp_out.d
@@ -25,6 +25,7 @@ Middlewares/Third_Party/LwIP/src/core/tcp_out.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
@@ -32,6 +33,14 @@ Middlewares/Third_Party/LwIP/src/core/tcp_out.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \
  ../Middlewares/Third_Party/LwIP/system/arch/cc.h \
@@ -88,6 +97,7 @@ Middlewares/Third_Party/LwIP/src/core/tcp_out.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
@@ -95,6 +105,14 @@ Middlewares/Third_Party/LwIP/src/core/tcp_out.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h:
 ../Middlewares/Third_Party/LwIP/system/arch/cc.h:
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/tcp_out.o b/Debug/Middlewares/Third_Party/LwIP/src/core/tcp_out.o
index 7bfd9fa..c902585 100644
Binary files a/Debug/Middlewares/Third_Party/LwIP/src/core/tcp_out.o and b/Debug/Middlewares/Third_Party/LwIP/src/core/tcp_out.o differ
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/timeouts.cyclo b/Debug/Middlewares/Third_Party/LwIP/src/core/timeouts.cyclo
index cd2c8f1..77cf02a 100644
--- a/Debug/Middlewares/Third_Party/LwIP/src/core/timeouts.cyclo
+++ b/Debug/Middlewares/Third_Party/LwIP/src/core/timeouts.cyclo
@@ -5,6 +5,6 @@
 ../Middlewares/Third_Party/LwIP/src/core/timeouts.c:264:6:sys_timeouts_init	2
 ../Middlewares/Third_Party/LwIP/src/core/timeouts.c:290:1:sys_timeout	2
 ../Middlewares/Third_Party/LwIP/src/core/timeouts.c:317:1:sys_untimeout	6
-../Middlewares/Third_Party/LwIP/src/core/timeouts.c:352:1:sys_check_timeouts	5
+../Middlewares/Third_Party/LwIP/src/core/timeouts.c:352:1:sys_check_timeouts	4
 ../Middlewares/Third_Party/LwIP/src/core/timeouts.c:404:1:sys_restart_timeouts	3
 ../Middlewares/Third_Party/LwIP/src/core/timeouts.c:426:1:sys_timeouts_sleeptime	4
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/timeouts.d b/Debug/Middlewares/Third_Party/LwIP/src/core/timeouts.d
index a07b561..996438b 100644
--- a/Debug/Middlewares/Third_Party/LwIP/src/core/timeouts.d
+++ b/Debug/Middlewares/Third_Party/LwIP/src/core/timeouts.d
@@ -25,6 +25,7 @@ Middlewares/Third_Party/LwIP/src/core/timeouts.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
@@ -32,12 +33,39 @@ Middlewares/Third_Party/LwIP/src/core/timeouts.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \
  ../Middlewares/Third_Party/LwIP/system/arch/cc.h \
  ../Middlewares/Third_Party/LwIP/system/arch/cpu.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/timeouts.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/err.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/sys.h \
+ ../Middlewares/Third_Party/LwIP/system/arch/sys_arch.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h \
+ ../Core/Inc/FreeRTOSConfig.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/list.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/tcp_priv.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/tcp.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/tcpbase.h \
@@ -63,6 +91,7 @@ Middlewares/Third_Party/LwIP/src/core/timeouts.o: \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/icmp.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/tcp.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/tcpip_priv.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/tcpip.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_frag.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/etharp.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ethernet.h \
@@ -75,8 +104,7 @@ Middlewares/Third_Party/LwIP/src/core/timeouts.o: \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/nd6.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_frag.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/mld6.h \
- ../Middlewares/Third_Party/LwIP/src/include/lwip/dhcp6.h \
- ../Middlewares/Third_Party/LwIP/src/include/lwip/sys.h
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/dhcp6.h
 ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h:
 ../LWIP/Target/lwipopts.h:
 ../Core/Inc/main.h:
@@ -103,6 +131,7 @@ Middlewares/Third_Party/LwIP/src/core/timeouts.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
@@ -110,12 +139,39 @@ Middlewares/Third_Party/LwIP/src/core/timeouts.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h:
 ../Middlewares/Third_Party/LwIP/system/arch/cc.h:
 ../Middlewares/Third_Party/LwIP/system/arch/cpu.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/timeouts.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/err.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/sys.h:
+../Middlewares/Third_Party/LwIP/system/arch/sys_arch.h:
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h:
+../Core/Inc/FreeRTOSConfig.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h:
+../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/task.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/list.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/task.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/tcp_priv.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/tcp.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/tcpbase.h:
@@ -141,6 +197,7 @@ Middlewares/Third_Party/LwIP/src/core/timeouts.o: \
 ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/icmp.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/tcp.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/tcpip_priv.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/tcpip.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_frag.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/etharp.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ethernet.h:
@@ -154,4 +211,3 @@ Middlewares/Third_Party/LwIP/src/core/timeouts.o: \
 ../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_frag.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/mld6.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/dhcp6.h:
-../Middlewares/Third_Party/LwIP/src/include/lwip/sys.h:
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/timeouts.o b/Debug/Middlewares/Third_Party/LwIP/src/core/timeouts.o
index 6d23557..4433cc3 100644
Binary files a/Debug/Middlewares/Third_Party/LwIP/src/core/timeouts.o and b/Debug/Middlewares/Third_Party/LwIP/src/core/timeouts.o differ
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/udp.d b/Debug/Middlewares/Third_Party/LwIP/src/core/udp.d
index 2635cf9..91e6984 100644
--- a/Debug/Middlewares/Third_Party/LwIP/src/core/udp.d
+++ b/Debug/Middlewares/Third_Party/LwIP/src/core/udp.d
@@ -25,6 +25,7 @@ Middlewares/Third_Party/LwIP/src/core/udp.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
@@ -32,6 +33,14 @@ Middlewares/Third_Party/LwIP/src/core/udp.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \
  ../Middlewares/Third_Party/LwIP/system/arch/cc.h \
@@ -90,6 +99,7 @@ Middlewares/Third_Party/LwIP/src/core/udp.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
@@ -97,6 +107,14 @@ Middlewares/Third_Party/LwIP/src/core/udp.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h:
 ../Middlewares/Third_Party/LwIP/system/arch/cc.h:
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/udp.o b/Debug/Middlewares/Third_Party/LwIP/src/core/udp.o
index cf0b9a5..c9fbc2b 100644
Binary files a/Debug/Middlewares/Third_Party/LwIP/src/core/udp.o and b/Debug/Middlewares/Third_Party/LwIP/src/core/udp.o differ
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/bridgeif.d b/Debug/Middlewares/Third_Party/LwIP/src/netif/bridgeif.d
index e7dfb50..155ffad 100644
--- a/Debug/Middlewares/Third_Party/LwIP/src/netif/bridgeif.d
+++ b/Debug/Middlewares/Third_Party/LwIP/src/netif/bridgeif.d
@@ -27,6 +27,7 @@ Middlewares/Third_Party/LwIP/src/netif/bridgeif.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
@@ -34,6 +35,14 @@ Middlewares/Third_Party/LwIP/src/netif/bridgeif.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \
  ../Middlewares/Third_Party/LwIP/system/arch/cc.h \
@@ -41,7 +50,27 @@ Middlewares/Third_Party/LwIP/src/netif/bridgeif.o: \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/err.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ethernet.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ieee.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/tcpip.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/timeouts.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/sys.h \
+ ../Middlewares/Third_Party/LwIP/system/arch/sys_arch.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h \
+ ../Core/Inc/FreeRTOSConfig.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/list.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/netif.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \
@@ -60,8 +89,7 @@ Middlewares/Third_Party/LwIP/src/netif/bridgeif.o: \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip4.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/etharp.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/ethip6.h \
- ../Middlewares/Third_Party/LwIP/src/include/lwip/snmp.h \
- ../Middlewares/Third_Party/LwIP/src/include/lwip/timeouts.h
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/snmp.h
 ../Middlewares/Third_Party/LwIP/src/include/netif/bridgeif.h:
 ../Middlewares/Third_Party/LwIP/src/include/netif/bridgeif_opts.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h:
@@ -90,6 +118,7 @@ Middlewares/Third_Party/LwIP/src/netif/bridgeif.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
@@ -97,6 +126,14 @@ Middlewares/Third_Party/LwIP/src/netif/bridgeif.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h:
 ../Middlewares/Third_Party/LwIP/system/arch/cc.h:
@@ -104,7 +141,27 @@ Middlewares/Third_Party/LwIP/src/netif/bridgeif.o: \
 ../Middlewares/Third_Party/LwIP/src/include/lwip/err.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ethernet.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ieee.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/tcpip.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/timeouts.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/sys.h:
+../Middlewares/Third_Party/LwIP/system/arch/sys_arch.h:
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h:
+../Core/Inc/FreeRTOSConfig.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h:
+../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/task.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/list.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/task.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/netif.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h:
@@ -124,4 +181,3 @@ Middlewares/Third_Party/LwIP/src/netif/bridgeif.o: \
 ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/etharp.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/ethip6.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/snmp.h:
-../Middlewares/Third_Party/LwIP/src/include/lwip/timeouts.h:
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/bridgeif.o b/Debug/Middlewares/Third_Party/LwIP/src/netif/bridgeif.o
index b85f789..825f117 100644
Binary files a/Debug/Middlewares/Third_Party/LwIP/src/netif/bridgeif.o and b/Debug/Middlewares/Third_Party/LwIP/src/netif/bridgeif.o differ
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.d b/Debug/Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.d
index 6ce57d6..7186d7d 100644
--- a/Debug/Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.d
+++ b/Debug/Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.d
@@ -27,6 +27,7 @@ Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
@@ -34,6 +35,14 @@ Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \
  ../Middlewares/Third_Party/LwIP/system/arch/cc.h \
@@ -41,9 +50,40 @@ Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o: \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/err.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ethernet.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ieee.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/tcpip.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/timeouts.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/sys.h \
+ ../Middlewares/Third_Party/LwIP/system/arch/sys_arch.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h \
+ ../Core/Inc/FreeRTOSConfig.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/list.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/netif.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h \
- ../Middlewares/Third_Party/LwIP/src/include/lwip/timeouts.h
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h
 ../Middlewares/Third_Party/LwIP/src/include/netif/bridgeif.h:
 ../Middlewares/Third_Party/LwIP/src/include/netif/bridgeif_opts.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h:
@@ -72,6 +112,7 @@ Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
@@ -79,6 +120,14 @@ Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h:
 ../Middlewares/Third_Party/LwIP/system/arch/cc.h:
@@ -86,6 +135,37 @@ Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o: \
 ../Middlewares/Third_Party/LwIP/src/include/lwip/err.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ethernet.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ieee.h:
-../Middlewares/Third_Party/LwIP/src/include/lwip/sys.h:
-../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/tcpip.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/timeouts.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/sys.h:
+../Middlewares/Third_Party/LwIP/system/arch/sys_arch.h:
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h:
+../Core/Inc/FreeRTOSConfig.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h:
+../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/task.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/list.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/task.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/netif.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/def.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/def.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h:
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o b/Debug/Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o
index ea703e2..47b8314 100644
Binary files a/Debug/Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o and b/Debug/Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o differ
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ethernet.d b/Debug/Middlewares/Third_Party/LwIP/src/netif/ethernet.d
index f61ea79..9ca4598 100644
--- a/Debug/Middlewares/Third_Party/LwIP/src/netif/ethernet.d
+++ b/Debug/Middlewares/Third_Party/LwIP/src/netif/ethernet.d
@@ -25,6 +25,7 @@ Middlewares/Third_Party/LwIP/src/netif/ethernet.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
@@ -32,6 +33,14 @@ Middlewares/Third_Party/LwIP/src/netif/ethernet.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \
  ../Middlewares/Third_Party/LwIP/system/arch/cc.h \
@@ -88,6 +97,7 @@ Middlewares/Third_Party/LwIP/src/netif/ethernet.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
@@ -95,6 +105,14 @@ Middlewares/Third_Party/LwIP/src/netif/ethernet.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h:
 ../Middlewares/Third_Party/LwIP/system/arch/cc.h:
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ethernet.o b/Debug/Middlewares/Third_Party/LwIP/src/netif/ethernet.o
index 299cba6..012357e 100644
Binary files a/Debug/Middlewares/Third_Party/LwIP/src/netif/ethernet.o and b/Debug/Middlewares/Third_Party/LwIP/src/netif/ethernet.o differ
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/lowpan6.d b/Debug/Middlewares/Third_Party/LwIP/src/netif/lowpan6.d
index 472467d..a478b92 100644
--- a/Debug/Middlewares/Third_Party/LwIP/src/netif/lowpan6.d
+++ b/Debug/Middlewares/Third_Party/LwIP/src/netif/lowpan6.d
@@ -27,6 +27,7 @@ Middlewares/Third_Party/LwIP/src/netif/lowpan6.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
@@ -34,6 +35,14 @@ Middlewares/Third_Party/LwIP/src/netif/lowpan6.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \
  ../Middlewares/Third_Party/LwIP/system/arch/cc.h \
@@ -66,6 +75,7 @@ Middlewares/Third_Party/LwIP/src/netif/lowpan6.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
@@ -73,6 +83,14 @@ Middlewares/Third_Party/LwIP/src/netif/lowpan6.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h:
 ../Middlewares/Third_Party/LwIP/system/arch/cc.h:
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/lowpan6.o b/Debug/Middlewares/Third_Party/LwIP/src/netif/lowpan6.o
index f1311e3..cbce0f1 100644
Binary files a/Debug/Middlewares/Third_Party/LwIP/src/netif/lowpan6.o and b/Debug/Middlewares/Third_Party/LwIP/src/netif/lowpan6.o differ
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/lowpan6_ble.d b/Debug/Middlewares/Third_Party/LwIP/src/netif/lowpan6_ble.d
index 0f478bb..f051309 100644
--- a/Debug/Middlewares/Third_Party/LwIP/src/netif/lowpan6_ble.d
+++ b/Debug/Middlewares/Third_Party/LwIP/src/netif/lowpan6_ble.d
@@ -27,6 +27,7 @@ Middlewares/Third_Party/LwIP/src/netif/lowpan6_ble.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
@@ -34,6 +35,14 @@ Middlewares/Third_Party/LwIP/src/netif/lowpan6_ble.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \
  ../Middlewares/Third_Party/LwIP/system/arch/cc.h \
@@ -66,6 +75,7 @@ Middlewares/Third_Party/LwIP/src/netif/lowpan6_ble.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
@@ -73,6 +83,14 @@ Middlewares/Third_Party/LwIP/src/netif/lowpan6_ble.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h:
 ../Middlewares/Third_Party/LwIP/system/arch/cc.h:
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/lowpan6_ble.o b/Debug/Middlewares/Third_Party/LwIP/src/netif/lowpan6_ble.o
index e4bdfa5..9273e9e 100644
Binary files a/Debug/Middlewares/Third_Party/LwIP/src/netif/lowpan6_ble.o and b/Debug/Middlewares/Third_Party/LwIP/src/netif/lowpan6_ble.o differ
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/lowpan6_common.d b/Debug/Middlewares/Third_Party/LwIP/src/netif/lowpan6_common.d
index e12778d..718be56 100644
--- a/Debug/Middlewares/Third_Party/LwIP/src/netif/lowpan6_common.d
+++ b/Debug/Middlewares/Third_Party/LwIP/src/netif/lowpan6_common.d
@@ -27,6 +27,7 @@ Middlewares/Third_Party/LwIP/src/netif/lowpan6_common.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
@@ -34,6 +35,14 @@ Middlewares/Third_Party/LwIP/src/netif/lowpan6_common.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \
  ../Middlewares/Third_Party/LwIP/system/arch/cc.h \
@@ -66,6 +75,7 @@ Middlewares/Third_Party/LwIP/src/netif/lowpan6_common.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
@@ -73,6 +83,14 @@ Middlewares/Third_Party/LwIP/src/netif/lowpan6_common.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h:
 ../Middlewares/Third_Party/LwIP/system/arch/cc.h:
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/lowpan6_common.o b/Debug/Middlewares/Third_Party/LwIP/src/netif/lowpan6_common.o
index c94e4e4..4d680d3 100644
Binary files a/Debug/Middlewares/Third_Party/LwIP/src/netif/lowpan6_common.o and b/Debug/Middlewares/Third_Party/LwIP/src/netif/lowpan6_common.o differ
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/auth.d b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/auth.d
index e32fad4..17b7bc8 100644
--- a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/auth.d
+++ b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/auth.d
@@ -26,6 +26,7 @@ Middlewares/Third_Party/LwIP/src/netif/ppp/auth.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
@@ -33,6 +34,14 @@ Middlewares/Third_Party/LwIP/src/netif/ppp/auth.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \
  ../Middlewares/Third_Party/LwIP/system/arch/cc.h \
@@ -64,6 +73,7 @@ Middlewares/Third_Party/LwIP/src/netif/ppp/auth.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
@@ -71,6 +81,14 @@ Middlewares/Third_Party/LwIP/src/netif/ppp/auth.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h:
 ../Middlewares/Third_Party/LwIP/system/arch/cc.h:
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/auth.o b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/auth.o
index 06e76e4..861fa0a 100644
Binary files a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/auth.o and b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/auth.o differ
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ccp.d b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ccp.d
index 02960f9..cbb0924 100644
--- a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ccp.d
+++ b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ccp.d
@@ -26,6 +26,7 @@ Middlewares/Third_Party/LwIP/src/netif/ppp/ccp.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
@@ -33,6 +34,14 @@ Middlewares/Third_Party/LwIP/src/netif/ppp/ccp.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \
  ../Middlewares/Third_Party/LwIP/system/arch/cc.h \
@@ -64,6 +73,7 @@ Middlewares/Third_Party/LwIP/src/netif/ppp/ccp.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
@@ -71,6 +81,14 @@ Middlewares/Third_Party/LwIP/src/netif/ppp/ccp.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h:
 ../Middlewares/Third_Party/LwIP/system/arch/cc.h:
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ccp.o b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ccp.o
index c11c54c..73554e4 100644
Binary files a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ccp.o and b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ccp.o differ
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/chap-md5.d b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/chap-md5.d
index a81da72..e60ef97 100644
--- a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/chap-md5.d
+++ b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/chap-md5.d
@@ -26,6 +26,7 @@ Middlewares/Third_Party/LwIP/src/netif/ppp/chap-md5.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
@@ -33,6 +34,14 @@ Middlewares/Third_Party/LwIP/src/netif/ppp/chap-md5.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \
  ../Middlewares/Third_Party/LwIP/system/arch/cc.h \
@@ -64,6 +73,7 @@ Middlewares/Third_Party/LwIP/src/netif/ppp/chap-md5.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
@@ -71,6 +81,14 @@ Middlewares/Third_Party/LwIP/src/netif/ppp/chap-md5.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h:
 ../Middlewares/Third_Party/LwIP/system/arch/cc.h:
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/chap-md5.o b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/chap-md5.o
index 99879c9..fa21c56 100644
Binary files a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/chap-md5.o and b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/chap-md5.o differ
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/chap-new.d b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/chap-new.d
index 95a4d20..584b81f 100644
--- a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/chap-new.d
+++ b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/chap-new.d
@@ -26,6 +26,7 @@ Middlewares/Third_Party/LwIP/src/netif/ppp/chap-new.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
@@ -33,6 +34,14 @@ Middlewares/Third_Party/LwIP/src/netif/ppp/chap-new.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \
  ../Middlewares/Third_Party/LwIP/system/arch/cc.h \
@@ -64,6 +73,7 @@ Middlewares/Third_Party/LwIP/src/netif/ppp/chap-new.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
@@ -71,6 +81,14 @@ Middlewares/Third_Party/LwIP/src/netif/ppp/chap-new.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h:
 ../Middlewares/Third_Party/LwIP/system/arch/cc.h:
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/chap-new.o b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/chap-new.o
index 120aa1b..cada44a 100644
Binary files a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/chap-new.o and b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/chap-new.o differ
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/chap_ms.d b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/chap_ms.d
index 0d3d45c..71db3e2 100644
--- a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/chap_ms.d
+++ b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/chap_ms.d
@@ -26,6 +26,7 @@ Middlewares/Third_Party/LwIP/src/netif/ppp/chap_ms.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
@@ -33,6 +34,14 @@ Middlewares/Third_Party/LwIP/src/netif/ppp/chap_ms.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \
  ../Middlewares/Third_Party/LwIP/system/arch/cc.h \
@@ -64,6 +73,7 @@ Middlewares/Third_Party/LwIP/src/netif/ppp/chap_ms.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
@@ -71,6 +81,14 @@ Middlewares/Third_Party/LwIP/src/netif/ppp/chap_ms.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h:
 ../Middlewares/Third_Party/LwIP/system/arch/cc.h:
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/chap_ms.o b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/chap_ms.o
index edd3ec6..8eb53ad 100644
Binary files a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/chap_ms.o and b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/chap_ms.o differ
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/demand.d b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/demand.d
index 7ee83f2..26e4954 100644
--- a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/demand.d
+++ b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/demand.d
@@ -26,6 +26,7 @@ Middlewares/Third_Party/LwIP/src/netif/ppp/demand.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
@@ -33,6 +34,14 @@ Middlewares/Third_Party/LwIP/src/netif/ppp/demand.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \
  ../Middlewares/Third_Party/LwIP/system/arch/cc.h \
@@ -64,6 +73,7 @@ Middlewares/Third_Party/LwIP/src/netif/ppp/demand.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
@@ -71,6 +81,14 @@ Middlewares/Third_Party/LwIP/src/netif/ppp/demand.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h:
 ../Middlewares/Third_Party/LwIP/system/arch/cc.h:
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/demand.o b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/demand.o
index 5336d77..f62fdb2 100644
Binary files a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/demand.o and b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/demand.o differ
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/eap.d b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/eap.d
index 8d6d5ef..9bb5111 100644
--- a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/eap.d
+++ b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/eap.d
@@ -26,6 +26,7 @@ Middlewares/Third_Party/LwIP/src/netif/ppp/eap.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
@@ -33,6 +34,14 @@ Middlewares/Third_Party/LwIP/src/netif/ppp/eap.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \
  ../Middlewares/Third_Party/LwIP/system/arch/cc.h \
@@ -64,6 +73,7 @@ Middlewares/Third_Party/LwIP/src/netif/ppp/eap.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
@@ -71,6 +81,14 @@ Middlewares/Third_Party/LwIP/src/netif/ppp/eap.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h:
 ../Middlewares/Third_Party/LwIP/system/arch/cc.h:
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/eap.o b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/eap.o
index 85193ff..0215fe0 100644
Binary files a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/eap.o and b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/eap.o differ
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ecp.d b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ecp.d
index c253bb7..ed07264 100644
--- a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ecp.d
+++ b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ecp.d
@@ -26,6 +26,7 @@ Middlewares/Third_Party/LwIP/src/netif/ppp/ecp.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
@@ -33,6 +34,14 @@ Middlewares/Third_Party/LwIP/src/netif/ppp/ecp.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \
  ../Middlewares/Third_Party/LwIP/system/arch/cc.h \
@@ -64,6 +73,7 @@ Middlewares/Third_Party/LwIP/src/netif/ppp/ecp.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
@@ -71,6 +81,14 @@ Middlewares/Third_Party/LwIP/src/netif/ppp/ecp.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h:
 ../Middlewares/Third_Party/LwIP/system/arch/cc.h:
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ecp.o b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ecp.o
index df84ae2..a6449c2 100644
Binary files a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ecp.o and b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ecp.o differ
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/eui64.d b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/eui64.d
index 488046f..12c7b66 100644
--- a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/eui64.d
+++ b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/eui64.d
@@ -26,6 +26,7 @@ Middlewares/Third_Party/LwIP/src/netif/ppp/eui64.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
@@ -33,6 +34,14 @@ Middlewares/Third_Party/LwIP/src/netif/ppp/eui64.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \
  ../Middlewares/Third_Party/LwIP/system/arch/cc.h \
@@ -64,6 +73,7 @@ Middlewares/Third_Party/LwIP/src/netif/ppp/eui64.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
@@ -71,6 +81,14 @@ Middlewares/Third_Party/LwIP/src/netif/ppp/eui64.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h:
 ../Middlewares/Third_Party/LwIP/system/arch/cc.h:
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/eui64.o b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/eui64.o
index e09b4ad..aaf0477 100644
Binary files a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/eui64.o and b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/eui64.o differ
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/fsm.d b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/fsm.d
index bb29f84..0428859 100644
--- a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/fsm.d
+++ b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/fsm.d
@@ -26,6 +26,7 @@ Middlewares/Third_Party/LwIP/src/netif/ppp/fsm.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
@@ -33,6 +34,14 @@ Middlewares/Third_Party/LwIP/src/netif/ppp/fsm.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \
  ../Middlewares/Third_Party/LwIP/system/arch/cc.h \
@@ -64,6 +73,7 @@ Middlewares/Third_Party/LwIP/src/netif/ppp/fsm.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
@@ -71,6 +81,14 @@ Middlewares/Third_Party/LwIP/src/netif/ppp/fsm.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h:
 ../Middlewares/Third_Party/LwIP/system/arch/cc.h:
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/fsm.o b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/fsm.o
index ee43ca4..9dbe0f7 100644
Binary files a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/fsm.o and b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/fsm.o differ
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ipcp.d b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ipcp.d
index d0b8724..c0ff03d 100644
--- a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ipcp.d
+++ b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ipcp.d
@@ -26,6 +26,7 @@ Middlewares/Third_Party/LwIP/src/netif/ppp/ipcp.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
@@ -33,6 +34,14 @@ Middlewares/Third_Party/LwIP/src/netif/ppp/ipcp.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \
  ../Middlewares/Third_Party/LwIP/system/arch/cc.h \
@@ -64,6 +73,7 @@ Middlewares/Third_Party/LwIP/src/netif/ppp/ipcp.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
@@ -71,6 +81,14 @@ Middlewares/Third_Party/LwIP/src/netif/ppp/ipcp.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h:
 ../Middlewares/Third_Party/LwIP/system/arch/cc.h:
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ipcp.o b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ipcp.o
index 9304039..1345ea4 100644
Binary files a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ipcp.o and b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ipcp.o differ
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ipv6cp.d b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ipv6cp.d
index db2fb9a..1d483d7 100644
--- a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ipv6cp.d
+++ b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ipv6cp.d
@@ -26,6 +26,7 @@ Middlewares/Third_Party/LwIP/src/netif/ppp/ipv6cp.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
@@ -33,6 +34,14 @@ Middlewares/Third_Party/LwIP/src/netif/ppp/ipv6cp.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \
  ../Middlewares/Third_Party/LwIP/system/arch/cc.h \
@@ -64,6 +73,7 @@ Middlewares/Third_Party/LwIP/src/netif/ppp/ipv6cp.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
@@ -71,6 +81,14 @@ Middlewares/Third_Party/LwIP/src/netif/ppp/ipv6cp.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h:
 ../Middlewares/Third_Party/LwIP/system/arch/cc.h:
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ipv6cp.o b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ipv6cp.o
index 28df5b3..3399b91 100644
Binary files a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ipv6cp.o and b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ipv6cp.o differ
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/lcp.d b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/lcp.d
index 0017715..edfb631 100644
--- a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/lcp.d
+++ b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/lcp.d
@@ -26,6 +26,7 @@ Middlewares/Third_Party/LwIP/src/netif/ppp/lcp.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
@@ -33,6 +34,14 @@ Middlewares/Third_Party/LwIP/src/netif/ppp/lcp.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \
  ../Middlewares/Third_Party/LwIP/system/arch/cc.h \
@@ -64,6 +73,7 @@ Middlewares/Third_Party/LwIP/src/netif/ppp/lcp.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
@@ -71,6 +81,14 @@ Middlewares/Third_Party/LwIP/src/netif/ppp/lcp.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h:
 ../Middlewares/Third_Party/LwIP/system/arch/cc.h:
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/lcp.o b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/lcp.o
index 03f053b..09714a6 100644
Binary files a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/lcp.o and b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/lcp.o differ
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/magic.d b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/magic.d
index 978007a..9cd92e5 100644
--- a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/magic.d
+++ b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/magic.d
@@ -26,6 +26,7 @@ Middlewares/Third_Party/LwIP/src/netif/ppp/magic.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
@@ -33,6 +34,14 @@ Middlewares/Third_Party/LwIP/src/netif/ppp/magic.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \
  ../Middlewares/Third_Party/LwIP/system/arch/cc.h \
@@ -64,6 +73,7 @@ Middlewares/Third_Party/LwIP/src/netif/ppp/magic.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
@@ -71,6 +81,14 @@ Middlewares/Third_Party/LwIP/src/netif/ppp/magic.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h:
 ../Middlewares/Third_Party/LwIP/system/arch/cc.h:
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/magic.o b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/magic.o
index 62b06ce..7121603 100644
Binary files a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/magic.o and b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/magic.o differ
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/mppe.d b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/mppe.d
index b0bf737..2fe78f6 100644
--- a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/mppe.d
+++ b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/mppe.d
@@ -26,6 +26,7 @@ Middlewares/Third_Party/LwIP/src/netif/ppp/mppe.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
@@ -33,6 +34,14 @@ Middlewares/Third_Party/LwIP/src/netif/ppp/mppe.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \
  ../Middlewares/Third_Party/LwIP/system/arch/cc.h \
@@ -64,6 +73,7 @@ Middlewares/Third_Party/LwIP/src/netif/ppp/mppe.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
@@ -71,6 +81,14 @@ Middlewares/Third_Party/LwIP/src/netif/ppp/mppe.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h:
 ../Middlewares/Third_Party/LwIP/system/arch/cc.h:
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/mppe.o b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/mppe.o
index 4586a34..ccd3dfa 100644
Binary files a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/mppe.o and b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/mppe.o differ
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/multilink.d b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/multilink.d
index 3fb48bd..c5f8c92 100644
--- a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/multilink.d
+++ b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/multilink.d
@@ -26,6 +26,7 @@ Middlewares/Third_Party/LwIP/src/netif/ppp/multilink.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
@@ -33,6 +34,14 @@ Middlewares/Third_Party/LwIP/src/netif/ppp/multilink.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \
  ../Middlewares/Third_Party/LwIP/system/arch/cc.h \
@@ -64,6 +73,7 @@ Middlewares/Third_Party/LwIP/src/netif/ppp/multilink.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
@@ -71,6 +81,14 @@ Middlewares/Third_Party/LwIP/src/netif/ppp/multilink.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h:
 ../Middlewares/Third_Party/LwIP/system/arch/cc.h:
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/multilink.o b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/multilink.o
index 90cc50c..c189295 100644
Binary files a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/multilink.o and b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/multilink.o differ
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ppp.d b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ppp.d
index 84bea15..6d9d51e 100644
--- a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ppp.d
+++ b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ppp.d
@@ -26,6 +26,7 @@ Middlewares/Third_Party/LwIP/src/netif/ppp/ppp.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
@@ -33,6 +34,14 @@ Middlewares/Third_Party/LwIP/src/netif/ppp/ppp.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \
  ../Middlewares/Third_Party/LwIP/system/arch/cc.h \
@@ -64,6 +73,7 @@ Middlewares/Third_Party/LwIP/src/netif/ppp/ppp.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
@@ -71,6 +81,14 @@ Middlewares/Third_Party/LwIP/src/netif/ppp/ppp.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h:
 ../Middlewares/Third_Party/LwIP/system/arch/cc.h:
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ppp.o b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ppp.o
index a35af86..658081e 100644
Binary files a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ppp.o and b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ppp.o differ
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppapi.d b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppapi.d
index 5fccfff..82689f7 100644
--- a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppapi.d
+++ b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppapi.d
@@ -26,6 +26,7 @@ Middlewares/Third_Party/LwIP/src/netif/ppp/pppapi.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
@@ -33,6 +34,14 @@ Middlewares/Third_Party/LwIP/src/netif/ppp/pppapi.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \
  ../Middlewares/Third_Party/LwIP/system/arch/cc.h \
@@ -64,6 +73,7 @@ Middlewares/Third_Party/LwIP/src/netif/ppp/pppapi.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
@@ -71,6 +81,14 @@ Middlewares/Third_Party/LwIP/src/netif/ppp/pppapi.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h:
 ../Middlewares/Third_Party/LwIP/system/arch/cc.h:
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppapi.o b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppapi.o
index cdc3035..5346538 100644
Binary files a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppapi.o and b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppapi.o differ
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppcrypt.d b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppcrypt.d
index a414880..4158a84 100644
--- a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppcrypt.d
+++ b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppcrypt.d
@@ -26,6 +26,7 @@ Middlewares/Third_Party/LwIP/src/netif/ppp/pppcrypt.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
@@ -33,6 +34,14 @@ Middlewares/Third_Party/LwIP/src/netif/ppp/pppcrypt.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \
  ../Middlewares/Third_Party/LwIP/system/arch/cc.h \
@@ -64,6 +73,7 @@ Middlewares/Third_Party/LwIP/src/netif/ppp/pppcrypt.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
@@ -71,6 +81,14 @@ Middlewares/Third_Party/LwIP/src/netif/ppp/pppcrypt.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h:
 ../Middlewares/Third_Party/LwIP/system/arch/cc.h:
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppcrypt.o b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppcrypt.o
index 7d36e9d..57bb9a1 100644
Binary files a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppcrypt.o and b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppcrypt.o differ
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppoe.d b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppoe.d
index 81054f0..11922b8 100644
--- a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppoe.d
+++ b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppoe.d
@@ -26,6 +26,7 @@ Middlewares/Third_Party/LwIP/src/netif/ppp/pppoe.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
@@ -33,6 +34,14 @@ Middlewares/Third_Party/LwIP/src/netif/ppp/pppoe.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \
  ../Middlewares/Third_Party/LwIP/system/arch/cc.h \
@@ -64,6 +73,7 @@ Middlewares/Third_Party/LwIP/src/netif/ppp/pppoe.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
@@ -71,6 +81,14 @@ Middlewares/Third_Party/LwIP/src/netif/ppp/pppoe.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h:
 ../Middlewares/Third_Party/LwIP/system/arch/cc.h:
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppoe.o b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppoe.o
index 989b13e..5c3f5a3 100644
Binary files a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppoe.o and b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppoe.o differ
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppol2tp.d b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppol2tp.d
index 36cb85c..86db1a2 100644
--- a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppol2tp.d
+++ b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppol2tp.d
@@ -26,6 +26,7 @@ Middlewares/Third_Party/LwIP/src/netif/ppp/pppol2tp.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
@@ -33,6 +34,14 @@ Middlewares/Third_Party/LwIP/src/netif/ppp/pppol2tp.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \
  ../Middlewares/Third_Party/LwIP/system/arch/cc.h \
@@ -64,6 +73,7 @@ Middlewares/Third_Party/LwIP/src/netif/ppp/pppol2tp.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
@@ -71,6 +81,14 @@ Middlewares/Third_Party/LwIP/src/netif/ppp/pppol2tp.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h:
 ../Middlewares/Third_Party/LwIP/system/arch/cc.h:
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppol2tp.o b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppol2tp.o
index 031937c..9ac1fe7 100644
Binary files a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppol2tp.o and b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppol2tp.o differ
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppos.d b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppos.d
index 8d43086..4672313 100644
--- a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppos.d
+++ b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppos.d
@@ -26,6 +26,7 @@ Middlewares/Third_Party/LwIP/src/netif/ppp/pppos.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
@@ -33,6 +34,14 @@ Middlewares/Third_Party/LwIP/src/netif/ppp/pppos.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \
  ../Middlewares/Third_Party/LwIP/system/arch/cc.h \
@@ -64,6 +73,7 @@ Middlewares/Third_Party/LwIP/src/netif/ppp/pppos.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
@@ -71,6 +81,14 @@ Middlewares/Third_Party/LwIP/src/netif/ppp/pppos.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h:
 ../Middlewares/Third_Party/LwIP/system/arch/cc.h:
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppos.o b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppos.o
index 49a4ef2..48872a1 100644
Binary files a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppos.o and b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppos.o differ
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/subdir.mk b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/subdir.mk
index 656f895..f509d33 100644
--- a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/subdir.mk
+++ b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/subdir.mk
@@ -88,7 +88,7 @@ C_DEPS += \
 
 # Each subdirectory must supply rules for building sources it contributes
 Middlewares/Third_Party/LwIP/src/netif/ppp/%.o Middlewares/Third_Party/LwIP/src/netif/ppp/%.su Middlewares/Third_Party/LwIP/src/netif/ppp/%.cyclo: ../Middlewares/Third_Party/LwIP/src/netif/ppp/%.c Middlewares/Third_Party/LwIP/src/netif/ppp/subdir.mk
-	arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DDEBUG -DDATA_IN_D2_SRAM -DUSE_HAL_DRIVER -DSTM32H723xx -c -I../Core/Inc -I../Drivers/STM32H7xx_HAL_Driver/Inc -I../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32H7xx/Include -I../Drivers/CMSIS/Include -I../LWIP/App -I../LWIP/Target -I../Middlewares/Third_Party/LwIP/src/include -I../Middlewares/Third_Party/LwIP/system -I../Drivers/BSP/Components/lan8742 -I../Middlewares/Third_Party/LwIP/src/include/netif/ppp -I../Middlewares/Third_Party/LwIP/src/include/lwip -I../Middlewares/Third_Party/LwIP/src/include/lwip/apps -I../Middlewares/Third_Party/LwIP/src/include/lwip/priv -I../Middlewares/Third_Party/LwIP/src/include/lwip/prot -I../Middlewares/Third_Party/LwIP/src/include/netif -I../Middlewares/Third_Party/LwIP/src/include/compat/posix -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/arpa -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/net -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/sys -I../Middlewares/Third_Party/LwIP/src/include/compat/stdc -I../Middlewares/Third_Party/LwIP/system/arch -I"C:/_NoSleep/STM32/lwip_test/LWFTP" -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
+	arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DDEBUG -DDATA_IN_D2_SRAM -DUSE_HAL_DRIVER -DSTM32H723xx -c -I../Core/Inc -I../FATFS/Target -I../FATFS/App -I../LWIP/App -I../LWIP/Target -I../Middlewares/Third_Party/LwIP/src/include -I../Middlewares/Third_Party/LwIP/system -I../Drivers/STM32H7xx_HAL_Driver/Inc -I../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F -I../Middlewares/Third_Party/FatFs/src -I../Drivers/BSP/Components/lan8742 -I../Middlewares/Third_Party/LwIP/src/include/netif/ppp -I../Drivers/CMSIS/Device/ST/STM32H7xx/Include -I../Middlewares/Third_Party/LwIP/src/include/lwip -I../Middlewares/Third_Party/LwIP/src/include/lwip/apps -I../Middlewares/Third_Party/LwIP/src/include/lwip/priv -I../Middlewares/Third_Party/LwIP/src/include/lwip/prot -I../Middlewares/Third_Party/LwIP/src/include/netif -I../Middlewares/Third_Party/LwIP/src/include/compat/posix -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/arpa -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/net -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/sys -I../Middlewares/Third_Party/LwIP/src/include/compat/stdc -I../Middlewares/Third_Party/LwIP/system/arch -I../Drivers/CMSIS/Include -I"C:/_NoSleep/STM32/TBD_TaxiBoard/LWFTPC" -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
 
 clean: clean-Middlewares-2f-Third_Party-2f-LwIP-2f-src-2f-netif-2f-ppp
 
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/upap.d b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/upap.d
index 36be8e5..430e307 100644
--- a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/upap.d
+++ b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/upap.d
@@ -26,6 +26,7 @@ Middlewares/Third_Party/LwIP/src/netif/ppp/upap.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
@@ -33,6 +34,14 @@ Middlewares/Third_Party/LwIP/src/netif/ppp/upap.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \
  ../Middlewares/Third_Party/LwIP/system/arch/cc.h \
@@ -64,6 +73,7 @@ Middlewares/Third_Party/LwIP/src/netif/ppp/upap.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
@@ -71,6 +81,14 @@ Middlewares/Third_Party/LwIP/src/netif/ppp/upap.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h:
 ../Middlewares/Third_Party/LwIP/system/arch/cc.h:
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/upap.o b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/upap.o
index 8f1d944..47c67c7 100644
Binary files a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/upap.o and b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/upap.o differ
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/utils.d b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/utils.d
index 7bebc10..8d5417b 100644
--- a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/utils.d
+++ b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/utils.d
@@ -26,6 +26,7 @@ Middlewares/Third_Party/LwIP/src/netif/ppp/utils.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
@@ -33,6 +34,14 @@ Middlewares/Third_Party/LwIP/src/netif/ppp/utils.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \
  ../Middlewares/Third_Party/LwIP/system/arch/cc.h \
@@ -64,6 +73,7 @@ Middlewares/Third_Party/LwIP/src/netif/ppp/utils.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
@@ -71,6 +81,14 @@ Middlewares/Third_Party/LwIP/src/netif/ppp/utils.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h:
 ../Middlewares/Third_Party/LwIP/system/arch/cc.h:
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/utils.o b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/utils.o
index 51d4c25..313af24 100644
Binary files a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/utils.o and b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/utils.o differ
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/vj.d b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/vj.d
index b2073cb..fec82a3 100644
--- a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/vj.d
+++ b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/vj.d
@@ -26,6 +26,7 @@ Middlewares/Third_Party/LwIP/src/netif/ppp/vj.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
@@ -33,6 +34,14 @@ Middlewares/Third_Party/LwIP/src/netif/ppp/vj.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \
  ../Middlewares/Third_Party/LwIP/system/arch/cc.h \
@@ -64,6 +73,7 @@ Middlewares/Third_Party/LwIP/src/netif/ppp/vj.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
@@ -71,6 +81,14 @@ Middlewares/Third_Party/LwIP/src/netif/ppp/vj.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h:
 ../Middlewares/Third_Party/LwIP/system/arch/cc.h:
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/vj.o b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/vj.o
index 26c9604..14ef045 100644
Binary files a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/vj.o and b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/vj.o differ
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/slipif.cyclo b/Debug/Middlewares/Third_Party/LwIP/src/netif/slipif.cyclo
index 15bb618..8b8f886 100644
--- a/Debug/Middlewares/Third_Party/LwIP/src/netif/slipif.cyclo
+++ b/Debug/Middlewares/Third_Party/LwIP/src/netif/slipif.cyclo
@@ -2,5 +2,6 @@
 ../Middlewares/Third_Party/LwIP/src/netif/slipif.c:172:1:slipif_output_v4	1
 ../Middlewares/Third_Party/LwIP/src/netif/slipif.c:207:1:slipif_rxbyte	18
 ../Middlewares/Third_Party/LwIP/src/netif/slipif.c:310:1:slipif_rxbyte_input	3
+../Middlewares/Third_Party/LwIP/src/netif/slipif.c:330:1:slipif_loop_thread	2
 ../Middlewares/Third_Party/LwIP/src/netif/slipif.c:360:1:slipif_init	4
 ../Middlewares/Third_Party/LwIP/src/netif/slipif.c:426:1:slipif_poll	4
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/slipif.d b/Debug/Middlewares/Third_Party/LwIP/src/netif/slipif.d
index fe32d0b..033c6b1 100644
--- a/Debug/Middlewares/Third_Party/LwIP/src/netif/slipif.d
+++ b/Debug/Middlewares/Third_Party/LwIP/src/netif/slipif.d
@@ -26,6 +26,7 @@ Middlewares/Third_Party/LwIP/src/netif/slipif.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
@@ -33,6 +34,14 @@ Middlewares/Third_Party/LwIP/src/netif/slipif.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \
  ../Middlewares/Third_Party/LwIP/system/arch/cc.h \
@@ -53,6 +62,24 @@ Middlewares/Third_Party/LwIP/src/netif/slipif.o: \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/snmp.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/sys.h \
+ ../Middlewares/Third_Party/LwIP/system/arch/sys_arch.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h \
+ ../Core/Inc/FreeRTOSConfig.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/list.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/sio.h
 ../Middlewares/Third_Party/LwIP/src/include/netif/slipif.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h:
@@ -81,6 +108,7 @@ Middlewares/Third_Party/LwIP/src/netif/slipif.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
@@ -88,6 +116,14 @@ Middlewares/Third_Party/LwIP/src/netif/slipif.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h:
 ../Middlewares/Third_Party/LwIP/system/arch/cc.h:
@@ -108,4 +144,22 @@ Middlewares/Third_Party/LwIP/src/netif/slipif.o: \
 ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/snmp.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/sys.h:
+../Middlewares/Third_Party/LwIP/system/arch/sys_arch.h:
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h:
+../Core/Inc/FreeRTOSConfig.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h:
+../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/task.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/list.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/task.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/sio.h:
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/slipif.o b/Debug/Middlewares/Third_Party/LwIP/src/netif/slipif.o
index 500bfd5..9df5e8d 100644
Binary files a/Debug/Middlewares/Third_Party/LwIP/src/netif/slipif.o and b/Debug/Middlewares/Third_Party/LwIP/src/netif/slipif.o differ
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/slipif.su b/Debug/Middlewares/Third_Party/LwIP/src/netif/slipif.su
index 0915971..962aea3 100644
--- a/Debug/Middlewares/Third_Party/LwIP/src/netif/slipif.su
+++ b/Debug/Middlewares/Third_Party/LwIP/src/netif/slipif.su
@@ -2,5 +2,6 @@
 ../Middlewares/Third_Party/LwIP/src/netif/slipif.c:172:1:slipif_output_v4	24	static
 ../Middlewares/Third_Party/LwIP/src/netif/slipif.c:207:1:slipif_rxbyte	24	static
 ../Middlewares/Third_Party/LwIP/src/netif/slipif.c:310:1:slipif_rxbyte_input	24	static
-../Middlewares/Third_Party/LwIP/src/netif/slipif.c:360:1:slipif_init	24	static
+../Middlewares/Third_Party/LwIP/src/netif/slipif.c:330:1:slipif_loop_thread	32	static
+../Middlewares/Third_Party/LwIP/src/netif/slipif.c:360:1:slipif_init	32	static
 ../Middlewares/Third_Party/LwIP/src/netif/slipif.c:426:1:slipif_poll	24	static
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/subdir.mk b/Debug/Middlewares/Third_Party/LwIP/src/netif/subdir.mk
index 0e1999c..23786be 100644
--- a/Debug/Middlewares/Third_Party/LwIP/src/netif/subdir.mk
+++ b/Debug/Middlewares/Third_Party/LwIP/src/netif/subdir.mk
@@ -37,7 +37,7 @@ C_DEPS += \
 
 # Each subdirectory must supply rules for building sources it contributes
 Middlewares/Third_Party/LwIP/src/netif/%.o Middlewares/Third_Party/LwIP/src/netif/%.su Middlewares/Third_Party/LwIP/src/netif/%.cyclo: ../Middlewares/Third_Party/LwIP/src/netif/%.c Middlewares/Third_Party/LwIP/src/netif/subdir.mk
-	arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DDEBUG -DDATA_IN_D2_SRAM -DUSE_HAL_DRIVER -DSTM32H723xx -c -I../Core/Inc -I../Drivers/STM32H7xx_HAL_Driver/Inc -I../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32H7xx/Include -I../Drivers/CMSIS/Include -I../LWIP/App -I../LWIP/Target -I../Middlewares/Third_Party/LwIP/src/include -I../Middlewares/Third_Party/LwIP/system -I../Drivers/BSP/Components/lan8742 -I../Middlewares/Third_Party/LwIP/src/include/netif/ppp -I../Middlewares/Third_Party/LwIP/src/include/lwip -I../Middlewares/Third_Party/LwIP/src/include/lwip/apps -I../Middlewares/Third_Party/LwIP/src/include/lwip/priv -I../Middlewares/Third_Party/LwIP/src/include/lwip/prot -I../Middlewares/Third_Party/LwIP/src/include/netif -I../Middlewares/Third_Party/LwIP/src/include/compat/posix -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/arpa -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/net -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/sys -I../Middlewares/Third_Party/LwIP/src/include/compat/stdc -I../Middlewares/Third_Party/LwIP/system/arch -I"C:/_NoSleep/STM32/lwip_test/LWFTP" -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
+	arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DDEBUG -DDATA_IN_D2_SRAM -DUSE_HAL_DRIVER -DSTM32H723xx -c -I../Core/Inc -I../FATFS/Target -I../FATFS/App -I../LWIP/App -I../LWIP/Target -I../Middlewares/Third_Party/LwIP/src/include -I../Middlewares/Third_Party/LwIP/system -I../Drivers/STM32H7xx_HAL_Driver/Inc -I../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F -I../Middlewares/Third_Party/FatFs/src -I../Drivers/BSP/Components/lan8742 -I../Middlewares/Third_Party/LwIP/src/include/netif/ppp -I../Drivers/CMSIS/Device/ST/STM32H7xx/Include -I../Middlewares/Third_Party/LwIP/src/include/lwip -I../Middlewares/Third_Party/LwIP/src/include/lwip/apps -I../Middlewares/Third_Party/LwIP/src/include/lwip/priv -I../Middlewares/Third_Party/LwIP/src/include/lwip/prot -I../Middlewares/Third_Party/LwIP/src/include/netif -I../Middlewares/Third_Party/LwIP/src/include/compat/posix -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/arpa -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/net -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/sys -I../Middlewares/Third_Party/LwIP/src/include/compat/stdc -I../Middlewares/Third_Party/LwIP/system/arch -I../Drivers/CMSIS/Include -I"C:/_NoSleep/STM32/TBD_TaxiBoard/LWFTPC" -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
 
 clean: clean-Middlewares-2f-Third_Party-2f-LwIP-2f-src-2f-netif
 
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/zepif.d b/Debug/Middlewares/Third_Party/LwIP/src/netif/zepif.d
index 21779fc..32c79d7 100644
--- a/Debug/Middlewares/Third_Party/LwIP/src/netif/zepif.d
+++ b/Debug/Middlewares/Third_Party/LwIP/src/netif/zepif.d
@@ -26,6 +26,7 @@ Middlewares/Third_Party/LwIP/src/netif/zepif.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
@@ -33,6 +34,14 @@ Middlewares/Third_Party/LwIP/src/netif/zepif.o: \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \
  ../Middlewares/Third_Party/LwIP/system/arch/cc.h \
@@ -66,6 +75,7 @@ Middlewares/Third_Party/LwIP/src/netif/zepif.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
@@ -73,6 +83,14 @@ Middlewares/Third_Party/LwIP/src/netif/zepif.o: \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h:
 ../Middlewares/Third_Party/LwIP/system/arch/cc.h:
diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/zepif.o b/Debug/Middlewares/Third_Party/LwIP/src/netif/zepif.o
index 88597c6..93b7ae5 100644
Binary files a/Debug/Middlewares/Third_Party/LwIP/src/netif/zepif.o and b/Debug/Middlewares/Third_Party/LwIP/src/netif/zepif.o differ
diff --git a/Debug/Middlewares/Third_Party/LwIP/system/OS/subdir.mk b/Debug/Middlewares/Third_Party/LwIP/system/OS/subdir.mk
new file mode 100644
index 0000000..9326a49
--- /dev/null
+++ b/Debug/Middlewares/Third_Party/LwIP/system/OS/subdir.mk
@@ -0,0 +1,27 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+# Toolchain: GNU Tools for STM32 (11.3.rel1)
+################################################################################
+
+# Add inputs and outputs from these tool invocations to the build variables 
+C_SRCS += \
+../Middlewares/Third_Party/LwIP/system/OS/sys_arch.c 
+
+OBJS += \
+./Middlewares/Third_Party/LwIP/system/OS/sys_arch.o 
+
+C_DEPS += \
+./Middlewares/Third_Party/LwIP/system/OS/sys_arch.d 
+
+
+# Each subdirectory must supply rules for building sources it contributes
+Middlewares/Third_Party/LwIP/system/OS/%.o Middlewares/Third_Party/LwIP/system/OS/%.su Middlewares/Third_Party/LwIP/system/OS/%.cyclo: ../Middlewares/Third_Party/LwIP/system/OS/%.c Middlewares/Third_Party/LwIP/system/OS/subdir.mk
+	arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DDEBUG -DDATA_IN_D2_SRAM -DUSE_HAL_DRIVER -DSTM32H723xx -c -I../Core/Inc -I../FATFS/Target -I../FATFS/App -I../LWIP/App -I../LWIP/Target -I../Middlewares/Third_Party/LwIP/src/include -I../Middlewares/Third_Party/LwIP/system -I../Drivers/STM32H7xx_HAL_Driver/Inc -I../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F -I../Middlewares/Third_Party/FatFs/src -I../Drivers/BSP/Components/lan8742 -I../Middlewares/Third_Party/LwIP/src/include/netif/ppp -I../Drivers/CMSIS/Device/ST/STM32H7xx/Include -I../Middlewares/Third_Party/LwIP/src/include/lwip -I../Middlewares/Third_Party/LwIP/src/include/lwip/apps -I../Middlewares/Third_Party/LwIP/src/include/lwip/priv -I../Middlewares/Third_Party/LwIP/src/include/lwip/prot -I../Middlewares/Third_Party/LwIP/src/include/netif -I../Middlewares/Third_Party/LwIP/src/include/compat/posix -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/arpa -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/net -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/sys -I../Middlewares/Third_Party/LwIP/src/include/compat/stdc -I../Middlewares/Third_Party/LwIP/system/arch -I../Drivers/CMSIS/Include -I"C:/_NoSleep/STM32/TBD_TaxiBoard/LWFTPC" -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
+
+clean: clean-Middlewares-2f-Third_Party-2f-LwIP-2f-system-2f-OS
+
+clean-Middlewares-2f-Third_Party-2f-LwIP-2f-system-2f-OS:
+	-$(RM) ./Middlewares/Third_Party/LwIP/system/OS/sys_arch.cyclo ./Middlewares/Third_Party/LwIP/system/OS/sys_arch.d ./Middlewares/Third_Party/LwIP/system/OS/sys_arch.o ./Middlewares/Third_Party/LwIP/system/OS/sys_arch.su
+
+.PHONY: clean-Middlewares-2f-Third_Party-2f-LwIP-2f-system-2f-OS
+
diff --git a/Debug/Middlewares/Third_Party/LwIP/system/OS/sys_arch.cyclo b/Debug/Middlewares/Third_Party/LwIP/system/OS/sys_arch.cyclo
new file mode 100644
index 0000000..937e921
--- /dev/null
+++ b/Debug/Middlewares/Third_Party/LwIP/system/OS/sys_arch.cyclo
@@ -0,0 +1,23 @@
+../Middlewares/Third_Party/LwIP/system/OS/sys_arch.c:50:7:sys_mbox_new	2
+../Middlewares/Third_Party/LwIP/system/OS/sys_arch.c:77:6:sys_mbox_free	1
+../Middlewares/Third_Party/LwIP/system/OS/sys_arch.c:104:6:sys_mbox_post	2
+../Middlewares/Third_Party/LwIP/system/OS/sys_arch.c:116:7:sys_mbox_trypost	2
+../Middlewares/Third_Party/LwIP/system/OS/sys_arch.c:143:7:sys_mbox_trypost_fromisr	1
+../Middlewares/Third_Party/LwIP/system/OS/sys_arch.c:164:7:sys_arch_mbox_fetch	3
+../Middlewares/Third_Party/LwIP/system/OS/sys_arch.c:213:7:sys_arch_mbox_tryfetch	2
+../Middlewares/Third_Party/LwIP/system/OS/sys_arch.c:235:5:sys_mbox_valid	2
+../Middlewares/Third_Party/LwIP/system/OS/sys_arch.c:243:6:sys_mbox_set_invalid	1
+../Middlewares/Third_Party/LwIP/system/OS/sys_arch.c:251:7:sys_sem_new	3
+../Middlewares/Third_Party/LwIP/system/OS/sys_arch.c:303:7:sys_arch_sem_wait	4
+../Middlewares/Third_Party/LwIP/system/OS/sys_arch.c:341:6:sys_sem_signal	1
+../Middlewares/Third_Party/LwIP/system/OS/sys_arch.c:348:6:sys_sem_free	1
+../Middlewares/Third_Party/LwIP/system/OS/sys_arch.c:357:5:sys_sem_valid	2
+../Middlewares/Third_Party/LwIP/system/OS/sys_arch.c:366:6:sys_sem_set_invalid	1
+../Middlewares/Third_Party/LwIP/system/OS/sys_arch.c:379:6:sys_init	1
+../Middlewares/Third_Party/LwIP/system/OS/sys_arch.c:393:7:sys_mutex_new	2
+../Middlewares/Third_Party/LwIP/system/OS/sys_arch.c:420:6:sys_mutex_free	1
+../Middlewares/Third_Party/LwIP/system/OS/sys_arch.c:430:6:sys_mutex_lock	1
+../Middlewares/Third_Party/LwIP/system/OS/sys_arch.c:441:6:sys_mutex_unlock	1
+../Middlewares/Third_Party/LwIP/system/OS/sys_arch.c:455:14:sys_thread_new	1
+../Middlewares/Third_Party/LwIP/system/OS/sys_arch.c:486:12:sys_arch_protect	1
+../Middlewares/Third_Party/LwIP/system/OS/sys_arch.c:506:6:sys_arch_unprotect	1
diff --git a/Debug/LWFTP/lwftp.d b/Debug/Middlewares/Third_Party/LwIP/system/OS/sys_arch.d
similarity index 58%
rename from Debug/LWFTP/lwftp.d
rename to Debug/Middlewares/Third_Party/LwIP/system/OS/sys_arch.d
index 8e91576..4c96c49 100644
--- a/Debug/LWFTP/lwftp.d
+++ b/Debug/Middlewares/Third_Party/LwIP/system/OS/sys_arch.d
@@ -1,4 +1,9 @@
-LWFTP/lwftp.o: ../LWFTP/lwftp.c ../LWFTP/lwftp.h \
+Middlewares/Third_Party/LwIP/system/OS/sys_arch.o: \
+ ../Middlewares/Third_Party/LwIP/system/OS/sys_arch.c \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \
+ ../Middlewares/Third_Party/LwIP/system/arch/cc.h \
+ ../Middlewares/Third_Party/LwIP/system/arch/cpu.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \
  ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \
@@ -24,6 +29,7 @@ LWFTP/lwftp.o: ../LWFTP/lwftp.c ../LWFTP/lwftp.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
@@ -31,35 +37,45 @@ LWFTP/lwftp.o: ../LWFTP/lwftp.c ../LWFTP/lwftp.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
  ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
- ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \
- ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \
- ../Middlewares/Third_Party/LwIP/system/arch/cc.h \
- ../Middlewares/Third_Party/LwIP/system/arch/cpu.h \
- ../Middlewares/Third_Party/LwIP/src/include/lwip/ip.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \
- ../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/sys.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/err.h \
- ../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h \
- ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h \
- ../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h \
- ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \
- ../Middlewares/Third_Party/LwIP/src/include/lwip/netif.h \
- ../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h \
+ ../Middlewares/Third_Party/LwIP/system/arch/sys_arch.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h \
+ ../Core/Inc/FreeRTOSConfig.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/list.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h \
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h \
  ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h \
- ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h \
- ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4.h \
- ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip4.h \
- ../Middlewares/Third_Party/LwIP/src/include/lwip/ip6.h \
- ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip.h \
- ../Middlewares/Third_Party/LwIP/src/include/lwip/tcp.h \
- ../Middlewares/Third_Party/LwIP/src/include/lwip/tcpbase.h \
- ../Middlewares/Third_Party/LwIP/src/include/lwip/icmp.h \
- ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/icmp.h \
- ../Middlewares/Third_Party/LwIP/src/include/lwip/tcpip.h
-../LWFTP/lwftp.h:
+ ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h
+../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h:
+../Middlewares/Third_Party/LwIP/system/arch/cc.h:
+../Middlewares/Third_Party/LwIP/system/arch/cpu.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h:
 ../LWIP/Target/lwipopts.h:
 ../Core/Inc/main.h:
@@ -86,6 +102,7 @@ LWFTP/lwftp.o: ../LWFTP/lwftp.c ../LWFTP/lwftp.h \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
@@ -93,31 +110,38 @@ LWFTP/lwftp.o: ../LWFTP/lwftp.c ../LWFTP/lwftp.h \
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
 ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
-../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h:
-../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h:
-../Middlewares/Third_Party/LwIP/system/arch/cc.h:
-../Middlewares/Third_Party/LwIP/system/arch/cpu.h:
-../Middlewares/Third_Party/LwIP/src/include/lwip/ip.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h:
-../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/sys.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/err.h:
-../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h:
-../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h:
-../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h:
-../Middlewares/Third_Party/LwIP/src/include/lwip/def.h:
-../Middlewares/Third_Party/LwIP/src/include/lwip/netif.h:
-../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h:
+../Middlewares/Third_Party/LwIP/system/arch/sys_arch.h:
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h:
+../Core/Inc/FreeRTOSConfig.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h:
+../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/task.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/list.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/task.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h:
+../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h:
 ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h:
-../Middlewares/Third_Party/LwIP/src/include/lwip/ip4.h:
-../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip4.h:
-../Middlewares/Third_Party/LwIP/src/include/lwip/ip6.h:
-../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip.h:
-../Middlewares/Third_Party/LwIP/src/include/lwip/tcp.h:
-../Middlewares/Third_Party/LwIP/src/include/lwip/tcpbase.h:
-../Middlewares/Third_Party/LwIP/src/include/lwip/icmp.h:
-../Middlewares/Third_Party/LwIP/src/include/lwip/prot/icmp.h:
-../Middlewares/Third_Party/LwIP/src/include/lwip/tcpip.h:
diff --git a/Debug/Middlewares/Third_Party/LwIP/system/OS/sys_arch.o b/Debug/Middlewares/Third_Party/LwIP/system/OS/sys_arch.o
new file mode 100644
index 0000000..cff5a31
Binary files /dev/null and b/Debug/Middlewares/Third_Party/LwIP/system/OS/sys_arch.o differ
diff --git a/Debug/Middlewares/Third_Party/LwIP/system/OS/sys_arch.su b/Debug/Middlewares/Third_Party/LwIP/system/OS/sys_arch.su
new file mode 100644
index 0000000..6366b9f
--- /dev/null
+++ b/Debug/Middlewares/Third_Party/LwIP/system/OS/sys_arch.su
@@ -0,0 +1,23 @@
+../Middlewares/Third_Party/LwIP/system/OS/sys_arch.c:50:7:sys_mbox_new	32	static
+../Middlewares/Third_Party/LwIP/system/OS/sys_arch.c:77:6:sys_mbox_free	16	static
+../Middlewares/Third_Party/LwIP/system/OS/sys_arch.c:104:6:sys_mbox_post	16	static
+../Middlewares/Third_Party/LwIP/system/OS/sys_arch.c:116:7:sys_mbox_trypost	24	static
+../Middlewares/Third_Party/LwIP/system/OS/sys_arch.c:143:7:sys_mbox_trypost_fromisr	16	static
+../Middlewares/Third_Party/LwIP/system/OS/sys_arch.c:164:7:sys_arch_mbox_fetch	56	static
+../Middlewares/Third_Party/LwIP/system/OS/sys_arch.c:213:7:sys_arch_mbox_tryfetch	32	static
+../Middlewares/Third_Party/LwIP/system/OS/sys_arch.c:235:5:sys_mbox_valid	16	static
+../Middlewares/Third_Party/LwIP/system/OS/sys_arch.c:243:6:sys_mbox_set_invalid	16	static
+../Middlewares/Third_Party/LwIP/system/OS/sys_arch.c:251:7:sys_sem_new	24	static
+../Middlewares/Third_Party/LwIP/system/OS/sys_arch.c:303:7:sys_arch_sem_wait	24	static
+../Middlewares/Third_Party/LwIP/system/OS/sys_arch.c:341:6:sys_sem_signal	16	static
+../Middlewares/Third_Party/LwIP/system/OS/sys_arch.c:348:6:sys_sem_free	16	static
+../Middlewares/Third_Party/LwIP/system/OS/sys_arch.c:357:5:sys_sem_valid	16	static
+../Middlewares/Third_Party/LwIP/system/OS/sys_arch.c:366:6:sys_sem_set_invalid	16	static
+../Middlewares/Third_Party/LwIP/system/OS/sys_arch.c:379:6:sys_init	8	static
+../Middlewares/Third_Party/LwIP/system/OS/sys_arch.c:393:7:sys_mutex_new	24	static
+../Middlewares/Third_Party/LwIP/system/OS/sys_arch.c:420:6:sys_mutex_free	16	static
+../Middlewares/Third_Party/LwIP/system/OS/sys_arch.c:430:6:sys_mutex_lock	16	static
+../Middlewares/Third_Party/LwIP/system/OS/sys_arch.c:441:6:sys_mutex_unlock	16	static
+../Middlewares/Third_Party/LwIP/system/OS/sys_arch.c:455:14:sys_thread_new	56	static
+../Middlewares/Third_Party/LwIP/system/OS/sys_arch.c:486:12:sys_arch_protect	8	static
+../Middlewares/Third_Party/LwIP/system/OS/sys_arch.c:506:6:sys_arch_unprotect	16	static
diff --git a/Debug/TBD_TaxiBoard.elf b/Debug/TBD_TaxiBoard.elf
new file mode 100644
index 0000000..1c2f752
Binary files /dev/null and b/Debug/TBD_TaxiBoard.elf differ
diff --git a/Debug/TBD_TaxiBoard.list b/Debug/TBD_TaxiBoard.list
new file mode 100644
index 0000000..5e2b281
--- /dev/null
+++ b/Debug/TBD_TaxiBoard.list
@@ -0,0 +1,91105 @@
+
+TBD_TaxiBoard.elf:     file format elf32-littlearm
+
+Sections:
+Idx Name          Size      VMA       LMA       File off  Algn
+  0 .isr_vector   000002cc  08000000  08000000  00010000  2**0
+                  CONTENTS, ALLOC, LOAD, READONLY, DATA
+  1 .text         000229f4  080002d0  080002d0  000102d0  2**4
+                  CONTENTS, ALLOC, LOAD, READONLY, CODE
+  2 .rodata       00004224  08022cc4  08022cc4  00032cc4  2**2
+                  CONTENTS, ALLOC, LOAD, READONLY, DATA
+  3 .ARM          00000008  08026ee8  08026ee8  00036ee8  2**2
+                  CONTENTS, ALLOC, LOAD, READONLY, DATA
+  4 .init_array   00000004  08026ef0  08026ef0  00036ef0  2**2
+                  CONTENTS, ALLOC, LOAD, DATA
+  5 .fini_array   00000004  08026ef4  08026ef4  00036ef4  2**2
+                  CONTENTS, ALLOC, LOAD, DATA
+  6 .data         000000a4  24000000  08026ef8  00040000  2**2
+                  CONTENTS, ALLOC, LOAD, DATA
+  7 .bss          0001a68c  240000a4  08026f9c  000400a4  2**2
+                  ALLOC
+  8 ._user_heap_stack 00006000  2401a730  08026f9c  0004a730  2**0
+                  ALLOC
+  9 .lwip_sec     00000160  30000000  30000000  00050000  2**2
+                  ALLOC
+ 10 .ARM.attributes 0000002e  00000000  00000000  000400a4  2**0
+                  CONTENTS, READONLY
+ 11 .comment      00000043  00000000  00000000  000400d2  2**0
+                  CONTENTS, READONLY
+ 12 .debug_info   00046c14  00000000  00000000  00040115  2**0
+                  CONTENTS, READONLY, DEBUGGING, OCTETS
+ 13 .debug_abbrev 00009da5  00000000  00000000  00086d29  2**0
+                  CONTENTS, READONLY, DEBUGGING, OCTETS
+ 14 .debug_aranges 00003268  00000000  00000000  00090ad0  2**3
+                  CONTENTS, READONLY, DEBUGGING, OCTETS
+ 15 .debug_rnglists 000027cc  00000000  00000000  00093d38  2**0
+                  CONTENTS, READONLY, DEBUGGING, OCTETS
+ 16 .debug_macro  0004a444  00000000  00000000  00096504  2**0
+                  CONTENTS, READONLY, DEBUGGING, OCTETS
+ 17 .debug_line   000516b3  00000000  00000000  000e0948  2**0
+                  CONTENTS, READONLY, DEBUGGING, OCTETS
+ 18 .debug_str    00183e93  00000000  00000000  00131ffb  2**0
+                  CONTENTS, READONLY, DEBUGGING, OCTETS
+ 19 .debug_frame  0000de4c  00000000  00000000  002b5e90  2**2
+                  CONTENTS, READONLY, DEBUGGING, OCTETS
+ 20 .debug_line_str 0000004e  00000000  00000000  002c3cdc  2**0
+                  CONTENTS, READONLY, DEBUGGING, OCTETS
+
+Disassembly of section .text:
+
+080002d0 <__do_global_dtors_aux>:
+ 80002d0:	b510      	push	{r4, lr}
+ 80002d2:	4c05      	ldr	r4, [pc, #20]	; (80002e8 <__do_global_dtors_aux+0x18>)
+ 80002d4:	7823      	ldrb	r3, [r4, #0]
+ 80002d6:	b933      	cbnz	r3, 80002e6 <__do_global_dtors_aux+0x16>
+ 80002d8:	4b04      	ldr	r3, [pc, #16]	; (80002ec <__do_global_dtors_aux+0x1c>)
+ 80002da:	b113      	cbz	r3, 80002e2 <__do_global_dtors_aux+0x12>
+ 80002dc:	4804      	ldr	r0, [pc, #16]	; (80002f0 <__do_global_dtors_aux+0x20>)
+ 80002de:	f3af 8000 	nop.w
+ 80002e2:	2301      	movs	r3, #1
+ 80002e4:	7023      	strb	r3, [r4, #0]
+ 80002e6:	bd10      	pop	{r4, pc}
+ 80002e8:	240000a4 	.word	0x240000a4
+ 80002ec:	00000000 	.word	0x00000000
+ 80002f0:	08022cac 	.word	0x08022cac
+
+080002f4 <frame_dummy>:
+ 80002f4:	b508      	push	{r3, lr}
+ 80002f6:	4b03      	ldr	r3, [pc, #12]	; (8000304 <frame_dummy+0x10>)
+ 80002f8:	b11b      	cbz	r3, 8000302 <frame_dummy+0xe>
+ 80002fa:	4903      	ldr	r1, [pc, #12]	; (8000308 <frame_dummy+0x14>)
+ 80002fc:	4803      	ldr	r0, [pc, #12]	; (800030c <frame_dummy+0x18>)
+ 80002fe:	f3af 8000 	nop.w
+ 8000302:	bd08      	pop	{r3, pc}
+ 8000304:	00000000 	.word	0x00000000
+ 8000308:	240000a8 	.word	0x240000a8
+ 800030c:	08022cac 	.word	0x08022cac
+
+08000310 <strcmp>:
+ 8000310:	f810 2b01 	ldrb.w	r2, [r0], #1
+ 8000314:	f811 3b01 	ldrb.w	r3, [r1], #1
+ 8000318:	2a01      	cmp	r2, #1
+ 800031a:	bf28      	it	cs
+ 800031c:	429a      	cmpcs	r2, r3
+ 800031e:	d0f7      	beq.n	8000310 <strcmp>
+ 8000320:	1ad0      	subs	r0, r2, r3
+ 8000322:	4770      	bx	lr
+
+08000324 <strlen>:
+ 8000324:	4603      	mov	r3, r0
+ 8000326:	f813 2b01 	ldrb.w	r2, [r3], #1
+ 800032a:	2a00      	cmp	r2, #0
+ 800032c:	d1fb      	bne.n	8000326 <strlen+0x2>
+ 800032e:	1a18      	subs	r0, r3, r0
+ 8000330:	3801      	subs	r0, #1
+ 8000332:	4770      	bx	lr
+	...
+
+08000340 <memchr>:
+ 8000340:	f001 01ff 	and.w	r1, r1, #255	; 0xff
+ 8000344:	2a10      	cmp	r2, #16
+ 8000346:	db2b      	blt.n	80003a0 <memchr+0x60>
+ 8000348:	f010 0f07 	tst.w	r0, #7
+ 800034c:	d008      	beq.n	8000360 <memchr+0x20>
+ 800034e:	f810 3b01 	ldrb.w	r3, [r0], #1
+ 8000352:	3a01      	subs	r2, #1
+ 8000354:	428b      	cmp	r3, r1
+ 8000356:	d02d      	beq.n	80003b4 <memchr+0x74>
+ 8000358:	f010 0f07 	tst.w	r0, #7
+ 800035c:	b342      	cbz	r2, 80003b0 <memchr+0x70>
+ 800035e:	d1f6      	bne.n	800034e <memchr+0xe>
+ 8000360:	b4f0      	push	{r4, r5, r6, r7}
+ 8000362:	ea41 2101 	orr.w	r1, r1, r1, lsl #8
+ 8000366:	ea41 4101 	orr.w	r1, r1, r1, lsl #16
+ 800036a:	f022 0407 	bic.w	r4, r2, #7
+ 800036e:	f07f 0700 	mvns.w	r7, #0
+ 8000372:	2300      	movs	r3, #0
+ 8000374:	e8f0 5602 	ldrd	r5, r6, [r0], #8
+ 8000378:	3c08      	subs	r4, #8
+ 800037a:	ea85 0501 	eor.w	r5, r5, r1
+ 800037e:	ea86 0601 	eor.w	r6, r6, r1
+ 8000382:	fa85 f547 	uadd8	r5, r5, r7
+ 8000386:	faa3 f587 	sel	r5, r3, r7
+ 800038a:	fa86 f647 	uadd8	r6, r6, r7
+ 800038e:	faa5 f687 	sel	r6, r5, r7
+ 8000392:	b98e      	cbnz	r6, 80003b8 <memchr+0x78>
+ 8000394:	d1ee      	bne.n	8000374 <memchr+0x34>
+ 8000396:	bcf0      	pop	{r4, r5, r6, r7}
+ 8000398:	f001 01ff 	and.w	r1, r1, #255	; 0xff
+ 800039c:	f002 0207 	and.w	r2, r2, #7
+ 80003a0:	b132      	cbz	r2, 80003b0 <memchr+0x70>
+ 80003a2:	f810 3b01 	ldrb.w	r3, [r0], #1
+ 80003a6:	3a01      	subs	r2, #1
+ 80003a8:	ea83 0301 	eor.w	r3, r3, r1
+ 80003ac:	b113      	cbz	r3, 80003b4 <memchr+0x74>
+ 80003ae:	d1f8      	bne.n	80003a2 <memchr+0x62>
+ 80003b0:	2000      	movs	r0, #0
+ 80003b2:	4770      	bx	lr
+ 80003b4:	3801      	subs	r0, #1
+ 80003b6:	4770      	bx	lr
+ 80003b8:	2d00      	cmp	r5, #0
+ 80003ba:	bf06      	itte	eq
+ 80003bc:	4635      	moveq	r5, r6
+ 80003be:	3803      	subeq	r0, #3
+ 80003c0:	3807      	subne	r0, #7
+ 80003c2:	f015 0f01 	tst.w	r5, #1
+ 80003c6:	d107      	bne.n	80003d8 <memchr+0x98>
+ 80003c8:	3001      	adds	r0, #1
+ 80003ca:	f415 7f80 	tst.w	r5, #256	; 0x100
+ 80003ce:	bf02      	ittt	eq
+ 80003d0:	3001      	addeq	r0, #1
+ 80003d2:	f415 3fc0 	tsteq.w	r5, #98304	; 0x18000
+ 80003d6:	3001      	addeq	r0, #1
+ 80003d8:	bcf0      	pop	{r4, r5, r6, r7}
+ 80003da:	3801      	subs	r0, #1
+ 80003dc:	4770      	bx	lr
+ 80003de:	bf00      	nop
+
+080003e0 <__aeabi_uldivmod>:
+ 80003e0:	b953      	cbnz	r3, 80003f8 <__aeabi_uldivmod+0x18>
+ 80003e2:	b94a      	cbnz	r2, 80003f8 <__aeabi_uldivmod+0x18>
+ 80003e4:	2900      	cmp	r1, #0
+ 80003e6:	bf08      	it	eq
+ 80003e8:	2800      	cmpeq	r0, #0
+ 80003ea:	bf1c      	itt	ne
+ 80003ec:	f04f 31ff 	movne.w	r1, #4294967295
+ 80003f0:	f04f 30ff 	movne.w	r0, #4294967295
+ 80003f4:	f000 b970 	b.w	80006d8 <__aeabi_idiv0>
+ 80003f8:	f1ad 0c08 	sub.w	ip, sp, #8
+ 80003fc:	e96d ce04 	strd	ip, lr, [sp, #-16]!
+ 8000400:	f000 f806 	bl	8000410 <__udivmoddi4>
+ 8000404:	f8dd e004 	ldr.w	lr, [sp, #4]
+ 8000408:	e9dd 2302 	ldrd	r2, r3, [sp, #8]
+ 800040c:	b004      	add	sp, #16
+ 800040e:	4770      	bx	lr
+
+08000410 <__udivmoddi4>:
+ 8000410:	e92d 47f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
+ 8000414:	9e08      	ldr	r6, [sp, #32]
+ 8000416:	460d      	mov	r5, r1
+ 8000418:	4604      	mov	r4, r0
+ 800041a:	460f      	mov	r7, r1
+ 800041c:	2b00      	cmp	r3, #0
+ 800041e:	d14a      	bne.n	80004b6 <__udivmoddi4+0xa6>
+ 8000420:	428a      	cmp	r2, r1
+ 8000422:	4694      	mov	ip, r2
+ 8000424:	d965      	bls.n	80004f2 <__udivmoddi4+0xe2>
+ 8000426:	fab2 f382 	clz	r3, r2
+ 800042a:	b143      	cbz	r3, 800043e <__udivmoddi4+0x2e>
+ 800042c:	fa02 fc03 	lsl.w	ip, r2, r3
+ 8000430:	f1c3 0220 	rsb	r2, r3, #32
+ 8000434:	409f      	lsls	r7, r3
+ 8000436:	fa20 f202 	lsr.w	r2, r0, r2
+ 800043a:	4317      	orrs	r7, r2
+ 800043c:	409c      	lsls	r4, r3
+ 800043e:	ea4f 4e1c 	mov.w	lr, ip, lsr #16
+ 8000442:	fa1f f58c 	uxth.w	r5, ip
+ 8000446:	fbb7 f1fe 	udiv	r1, r7, lr
+ 800044a:	0c22      	lsrs	r2, r4, #16
+ 800044c:	fb0e 7711 	mls	r7, lr, r1, r7
+ 8000450:	ea42 4207 	orr.w	r2, r2, r7, lsl #16
+ 8000454:	fb01 f005 	mul.w	r0, r1, r5
+ 8000458:	4290      	cmp	r0, r2
+ 800045a:	d90a      	bls.n	8000472 <__udivmoddi4+0x62>
+ 800045c:	eb1c 0202 	adds.w	r2, ip, r2
+ 8000460:	f101 37ff 	add.w	r7, r1, #4294967295
+ 8000464:	f080 811c 	bcs.w	80006a0 <__udivmoddi4+0x290>
+ 8000468:	4290      	cmp	r0, r2
+ 800046a:	f240 8119 	bls.w	80006a0 <__udivmoddi4+0x290>
+ 800046e:	3902      	subs	r1, #2
+ 8000470:	4462      	add	r2, ip
+ 8000472:	1a12      	subs	r2, r2, r0
+ 8000474:	b2a4      	uxth	r4, r4
+ 8000476:	fbb2 f0fe 	udiv	r0, r2, lr
+ 800047a:	fb0e 2210 	mls	r2, lr, r0, r2
+ 800047e:	ea44 4402 	orr.w	r4, r4, r2, lsl #16
+ 8000482:	fb00 f505 	mul.w	r5, r0, r5
+ 8000486:	42a5      	cmp	r5, r4
+ 8000488:	d90a      	bls.n	80004a0 <__udivmoddi4+0x90>
+ 800048a:	eb1c 0404 	adds.w	r4, ip, r4
+ 800048e:	f100 32ff 	add.w	r2, r0, #4294967295
+ 8000492:	f080 8107 	bcs.w	80006a4 <__udivmoddi4+0x294>
+ 8000496:	42a5      	cmp	r5, r4
+ 8000498:	f240 8104 	bls.w	80006a4 <__udivmoddi4+0x294>
+ 800049c:	4464      	add	r4, ip
+ 800049e:	3802      	subs	r0, #2
+ 80004a0:	ea40 4001 	orr.w	r0, r0, r1, lsl #16
+ 80004a4:	1b64      	subs	r4, r4, r5
+ 80004a6:	2100      	movs	r1, #0
+ 80004a8:	b11e      	cbz	r6, 80004b2 <__udivmoddi4+0xa2>
+ 80004aa:	40dc      	lsrs	r4, r3
+ 80004ac:	2300      	movs	r3, #0
+ 80004ae:	e9c6 4300 	strd	r4, r3, [r6]
+ 80004b2:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
+ 80004b6:	428b      	cmp	r3, r1
+ 80004b8:	d908      	bls.n	80004cc <__udivmoddi4+0xbc>
+ 80004ba:	2e00      	cmp	r6, #0
+ 80004bc:	f000 80ed 	beq.w	800069a <__udivmoddi4+0x28a>
+ 80004c0:	2100      	movs	r1, #0
+ 80004c2:	e9c6 0500 	strd	r0, r5, [r6]
+ 80004c6:	4608      	mov	r0, r1
+ 80004c8:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
+ 80004cc:	fab3 f183 	clz	r1, r3
+ 80004d0:	2900      	cmp	r1, #0
+ 80004d2:	d149      	bne.n	8000568 <__udivmoddi4+0x158>
+ 80004d4:	42ab      	cmp	r3, r5
+ 80004d6:	d302      	bcc.n	80004de <__udivmoddi4+0xce>
+ 80004d8:	4282      	cmp	r2, r0
+ 80004da:	f200 80f8 	bhi.w	80006ce <__udivmoddi4+0x2be>
+ 80004de:	1a84      	subs	r4, r0, r2
+ 80004e0:	eb65 0203 	sbc.w	r2, r5, r3
+ 80004e4:	2001      	movs	r0, #1
+ 80004e6:	4617      	mov	r7, r2
+ 80004e8:	2e00      	cmp	r6, #0
+ 80004ea:	d0e2      	beq.n	80004b2 <__udivmoddi4+0xa2>
+ 80004ec:	e9c6 4700 	strd	r4, r7, [r6]
+ 80004f0:	e7df      	b.n	80004b2 <__udivmoddi4+0xa2>
+ 80004f2:	b902      	cbnz	r2, 80004f6 <__udivmoddi4+0xe6>
+ 80004f4:	deff      	udf	#255	; 0xff
+ 80004f6:	fab2 f382 	clz	r3, r2
+ 80004fa:	2b00      	cmp	r3, #0
+ 80004fc:	f040 8090 	bne.w	8000620 <__udivmoddi4+0x210>
+ 8000500:	1a8a      	subs	r2, r1, r2
+ 8000502:	ea4f 471c 	mov.w	r7, ip, lsr #16
+ 8000506:	fa1f fe8c 	uxth.w	lr, ip
+ 800050a:	2101      	movs	r1, #1
+ 800050c:	fbb2 f5f7 	udiv	r5, r2, r7
+ 8000510:	fb07 2015 	mls	r0, r7, r5, r2
+ 8000514:	0c22      	lsrs	r2, r4, #16
+ 8000516:	ea42 4200 	orr.w	r2, r2, r0, lsl #16
+ 800051a:	fb0e f005 	mul.w	r0, lr, r5
+ 800051e:	4290      	cmp	r0, r2
+ 8000520:	d908      	bls.n	8000534 <__udivmoddi4+0x124>
+ 8000522:	eb1c 0202 	adds.w	r2, ip, r2
+ 8000526:	f105 38ff 	add.w	r8, r5, #4294967295
+ 800052a:	d202      	bcs.n	8000532 <__udivmoddi4+0x122>
+ 800052c:	4290      	cmp	r0, r2
+ 800052e:	f200 80cb 	bhi.w	80006c8 <__udivmoddi4+0x2b8>
+ 8000532:	4645      	mov	r5, r8
+ 8000534:	1a12      	subs	r2, r2, r0
+ 8000536:	b2a4      	uxth	r4, r4
+ 8000538:	fbb2 f0f7 	udiv	r0, r2, r7
+ 800053c:	fb07 2210 	mls	r2, r7, r0, r2
+ 8000540:	ea44 4402 	orr.w	r4, r4, r2, lsl #16
+ 8000544:	fb0e fe00 	mul.w	lr, lr, r0
+ 8000548:	45a6      	cmp	lr, r4
+ 800054a:	d908      	bls.n	800055e <__udivmoddi4+0x14e>
+ 800054c:	eb1c 0404 	adds.w	r4, ip, r4
+ 8000550:	f100 32ff 	add.w	r2, r0, #4294967295
+ 8000554:	d202      	bcs.n	800055c <__udivmoddi4+0x14c>
+ 8000556:	45a6      	cmp	lr, r4
+ 8000558:	f200 80bb 	bhi.w	80006d2 <__udivmoddi4+0x2c2>
+ 800055c:	4610      	mov	r0, r2
+ 800055e:	eba4 040e 	sub.w	r4, r4, lr
+ 8000562:	ea40 4005 	orr.w	r0, r0, r5, lsl #16
+ 8000566:	e79f      	b.n	80004a8 <__udivmoddi4+0x98>
+ 8000568:	f1c1 0720 	rsb	r7, r1, #32
+ 800056c:	408b      	lsls	r3, r1
+ 800056e:	fa22 fc07 	lsr.w	ip, r2, r7
+ 8000572:	ea4c 0c03 	orr.w	ip, ip, r3
+ 8000576:	fa05 f401 	lsl.w	r4, r5, r1
+ 800057a:	fa20 f307 	lsr.w	r3, r0, r7
+ 800057e:	40fd      	lsrs	r5, r7
+ 8000580:	ea4f 491c 	mov.w	r9, ip, lsr #16
+ 8000584:	4323      	orrs	r3, r4
+ 8000586:	fbb5 f8f9 	udiv	r8, r5, r9
+ 800058a:	fa1f fe8c 	uxth.w	lr, ip
+ 800058e:	fb09 5518 	mls	r5, r9, r8, r5
+ 8000592:	0c1c      	lsrs	r4, r3, #16
+ 8000594:	ea44 4405 	orr.w	r4, r4, r5, lsl #16
+ 8000598:	fb08 f50e 	mul.w	r5, r8, lr
+ 800059c:	42a5      	cmp	r5, r4
+ 800059e:	fa02 f201 	lsl.w	r2, r2, r1
+ 80005a2:	fa00 f001 	lsl.w	r0, r0, r1
+ 80005a6:	d90b      	bls.n	80005c0 <__udivmoddi4+0x1b0>
+ 80005a8:	eb1c 0404 	adds.w	r4, ip, r4
+ 80005ac:	f108 3aff 	add.w	sl, r8, #4294967295
+ 80005b0:	f080 8088 	bcs.w	80006c4 <__udivmoddi4+0x2b4>
+ 80005b4:	42a5      	cmp	r5, r4
+ 80005b6:	f240 8085 	bls.w	80006c4 <__udivmoddi4+0x2b4>
+ 80005ba:	f1a8 0802 	sub.w	r8, r8, #2
+ 80005be:	4464      	add	r4, ip
+ 80005c0:	1b64      	subs	r4, r4, r5
+ 80005c2:	b29d      	uxth	r5, r3
+ 80005c4:	fbb4 f3f9 	udiv	r3, r4, r9
+ 80005c8:	fb09 4413 	mls	r4, r9, r3, r4
+ 80005cc:	ea45 4404 	orr.w	r4, r5, r4, lsl #16
+ 80005d0:	fb03 fe0e 	mul.w	lr, r3, lr
+ 80005d4:	45a6      	cmp	lr, r4
+ 80005d6:	d908      	bls.n	80005ea <__udivmoddi4+0x1da>
+ 80005d8:	eb1c 0404 	adds.w	r4, ip, r4
+ 80005dc:	f103 35ff 	add.w	r5, r3, #4294967295
+ 80005e0:	d26c      	bcs.n	80006bc <__udivmoddi4+0x2ac>
+ 80005e2:	45a6      	cmp	lr, r4
+ 80005e4:	d96a      	bls.n	80006bc <__udivmoddi4+0x2ac>
+ 80005e6:	3b02      	subs	r3, #2
+ 80005e8:	4464      	add	r4, ip
+ 80005ea:	ea43 4308 	orr.w	r3, r3, r8, lsl #16
+ 80005ee:	fba3 9502 	umull	r9, r5, r3, r2
+ 80005f2:	eba4 040e 	sub.w	r4, r4, lr
+ 80005f6:	42ac      	cmp	r4, r5
+ 80005f8:	46c8      	mov	r8, r9
+ 80005fa:	46ae      	mov	lr, r5
+ 80005fc:	d356      	bcc.n	80006ac <__udivmoddi4+0x29c>
+ 80005fe:	d053      	beq.n	80006a8 <__udivmoddi4+0x298>
+ 8000600:	b156      	cbz	r6, 8000618 <__udivmoddi4+0x208>
+ 8000602:	ebb0 0208 	subs.w	r2, r0, r8
+ 8000606:	eb64 040e 	sbc.w	r4, r4, lr
+ 800060a:	fa04 f707 	lsl.w	r7, r4, r7
+ 800060e:	40ca      	lsrs	r2, r1
+ 8000610:	40cc      	lsrs	r4, r1
+ 8000612:	4317      	orrs	r7, r2
+ 8000614:	e9c6 7400 	strd	r7, r4, [r6]
+ 8000618:	4618      	mov	r0, r3
+ 800061a:	2100      	movs	r1, #0
+ 800061c:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
+ 8000620:	f1c3 0120 	rsb	r1, r3, #32
+ 8000624:	fa02 fc03 	lsl.w	ip, r2, r3
+ 8000628:	fa20 f201 	lsr.w	r2, r0, r1
+ 800062c:	fa25 f101 	lsr.w	r1, r5, r1
+ 8000630:	409d      	lsls	r5, r3
+ 8000632:	432a      	orrs	r2, r5
+ 8000634:	ea4f 471c 	mov.w	r7, ip, lsr #16
+ 8000638:	fa1f fe8c 	uxth.w	lr, ip
+ 800063c:	fbb1 f0f7 	udiv	r0, r1, r7
+ 8000640:	fb07 1510 	mls	r5, r7, r0, r1
+ 8000644:	0c11      	lsrs	r1, r2, #16
+ 8000646:	ea41 4105 	orr.w	r1, r1, r5, lsl #16
+ 800064a:	fb00 f50e 	mul.w	r5, r0, lr
+ 800064e:	428d      	cmp	r5, r1
+ 8000650:	fa04 f403 	lsl.w	r4, r4, r3
+ 8000654:	d908      	bls.n	8000668 <__udivmoddi4+0x258>
+ 8000656:	eb1c 0101 	adds.w	r1, ip, r1
+ 800065a:	f100 38ff 	add.w	r8, r0, #4294967295
+ 800065e:	d22f      	bcs.n	80006c0 <__udivmoddi4+0x2b0>
+ 8000660:	428d      	cmp	r5, r1
+ 8000662:	d92d      	bls.n	80006c0 <__udivmoddi4+0x2b0>
+ 8000664:	3802      	subs	r0, #2
+ 8000666:	4461      	add	r1, ip
+ 8000668:	1b49      	subs	r1, r1, r5
+ 800066a:	b292      	uxth	r2, r2
+ 800066c:	fbb1 f5f7 	udiv	r5, r1, r7
+ 8000670:	fb07 1115 	mls	r1, r7, r5, r1
+ 8000674:	ea42 4201 	orr.w	r2, r2, r1, lsl #16
+ 8000678:	fb05 f10e 	mul.w	r1, r5, lr
+ 800067c:	4291      	cmp	r1, r2
+ 800067e:	d908      	bls.n	8000692 <__udivmoddi4+0x282>
+ 8000680:	eb1c 0202 	adds.w	r2, ip, r2
+ 8000684:	f105 38ff 	add.w	r8, r5, #4294967295
+ 8000688:	d216      	bcs.n	80006b8 <__udivmoddi4+0x2a8>
+ 800068a:	4291      	cmp	r1, r2
+ 800068c:	d914      	bls.n	80006b8 <__udivmoddi4+0x2a8>
+ 800068e:	3d02      	subs	r5, #2
+ 8000690:	4462      	add	r2, ip
+ 8000692:	1a52      	subs	r2, r2, r1
+ 8000694:	ea45 4100 	orr.w	r1, r5, r0, lsl #16
+ 8000698:	e738      	b.n	800050c <__udivmoddi4+0xfc>
+ 800069a:	4631      	mov	r1, r6
+ 800069c:	4630      	mov	r0, r6
+ 800069e:	e708      	b.n	80004b2 <__udivmoddi4+0xa2>
+ 80006a0:	4639      	mov	r1, r7
+ 80006a2:	e6e6      	b.n	8000472 <__udivmoddi4+0x62>
+ 80006a4:	4610      	mov	r0, r2
+ 80006a6:	e6fb      	b.n	80004a0 <__udivmoddi4+0x90>
+ 80006a8:	4548      	cmp	r0, r9
+ 80006aa:	d2a9      	bcs.n	8000600 <__udivmoddi4+0x1f0>
+ 80006ac:	ebb9 0802 	subs.w	r8, r9, r2
+ 80006b0:	eb65 0e0c 	sbc.w	lr, r5, ip
+ 80006b4:	3b01      	subs	r3, #1
+ 80006b6:	e7a3      	b.n	8000600 <__udivmoddi4+0x1f0>
+ 80006b8:	4645      	mov	r5, r8
+ 80006ba:	e7ea      	b.n	8000692 <__udivmoddi4+0x282>
+ 80006bc:	462b      	mov	r3, r5
+ 80006be:	e794      	b.n	80005ea <__udivmoddi4+0x1da>
+ 80006c0:	4640      	mov	r0, r8
+ 80006c2:	e7d1      	b.n	8000668 <__udivmoddi4+0x258>
+ 80006c4:	46d0      	mov	r8, sl
+ 80006c6:	e77b      	b.n	80005c0 <__udivmoddi4+0x1b0>
+ 80006c8:	3d02      	subs	r5, #2
+ 80006ca:	4462      	add	r2, ip
+ 80006cc:	e732      	b.n	8000534 <__udivmoddi4+0x124>
+ 80006ce:	4608      	mov	r0, r1
+ 80006d0:	e70a      	b.n	80004e8 <__udivmoddi4+0xd8>
+ 80006d2:	4464      	add	r4, ip
+ 80006d4:	3802      	subs	r0, #2
+ 80006d6:	e742      	b.n	800055e <__udivmoddi4+0x14e>
+
+080006d8 <__aeabi_idiv0>:
+ 80006d8:	4770      	bx	lr
+ 80006da:	bf00      	nop
+
+080006dc <vApplicationStackOverflowHook>:
+/* Hook prototypes */
+void vApplicationStackOverflowHook(xTaskHandle xTask, signed char *pcTaskName);
+
+/* USER CODE BEGIN 4 */
+__weak void vApplicationStackOverflowHook(xTaskHandle xTask, signed char *pcTaskName)
+{
+ 80006dc:	b480      	push	{r7}
+ 80006de:	b083      	sub	sp, #12
+ 80006e0:	af00      	add	r7, sp, #0
+ 80006e2:	6078      	str	r0, [r7, #4]
+ 80006e4:	6039      	str	r1, [r7, #0]
+   /* Run time stack overflow checking is performed if
+   configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook function is
+   called if a stack overflow is detected. */
+}
+ 80006e6:	bf00      	nop
+ 80006e8:	370c      	adds	r7, #12
+ 80006ea:	46bd      	mov	sp, r7
+ 80006ec:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 80006f0:	4770      	bx	lr
+	...
+
+080006f4 <vApplicationGetIdleTaskMemory>:
+/* USER CODE BEGIN GET_IDLE_TASK_MEMORY */
+static StaticTask_t xIdleTaskTCBBuffer;
+static StackType_t xIdleStack[configMINIMAL_STACK_SIZE];
+
+void vApplicationGetIdleTaskMemory( StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize )
+{
+ 80006f4:	b480      	push	{r7}
+ 80006f6:	b085      	sub	sp, #20
+ 80006f8:	af00      	add	r7, sp, #0
+ 80006fa:	60f8      	str	r0, [r7, #12]
+ 80006fc:	60b9      	str	r1, [r7, #8]
+ 80006fe:	607a      	str	r2, [r7, #4]
+  *ppxIdleTaskTCBBuffer = &xIdleTaskTCBBuffer;
+ 8000700:	68fb      	ldr	r3, [r7, #12]
+ 8000702:	4a07      	ldr	r2, [pc, #28]	; (8000720 <vApplicationGetIdleTaskMemory+0x2c>)
+ 8000704:	601a      	str	r2, [r3, #0]
+  *ppxIdleTaskStackBuffer = &xIdleStack[0];
+ 8000706:	68bb      	ldr	r3, [r7, #8]
+ 8000708:	4a06      	ldr	r2, [pc, #24]	; (8000724 <vApplicationGetIdleTaskMemory+0x30>)
+ 800070a:	601a      	str	r2, [r3, #0]
+  *pulIdleTaskStackSize = configMINIMAL_STACK_SIZE;
+ 800070c:	687b      	ldr	r3, [r7, #4]
+ 800070e:	f44f 7280 	mov.w	r2, #256	; 0x100
+ 8000712:	601a      	str	r2, [r3, #0]
+  /* place for user code */
+}
+ 8000714:	bf00      	nop
+ 8000716:	3714      	adds	r7, #20
+ 8000718:	46bd      	mov	sp, r7
+ 800071a:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 800071e:	4770      	bx	lr
+ 8000720:	240000c0 	.word	0x240000c0
+ 8000724:	24000114 	.word	0x24000114
+
+08000728 <vApplicationGetTimerTaskMemory>:
+/* USER CODE BEGIN GET_TIMER_TASK_MEMORY */
+static StaticTask_t xTimerTaskTCBBuffer;
+static StackType_t xTimerStack[configTIMER_TASK_STACK_DEPTH];
+
+void vApplicationGetTimerTaskMemory( StaticTask_t **ppxTimerTaskTCBBuffer, StackType_t **ppxTimerTaskStackBuffer, uint32_t *pulTimerTaskStackSize )
+{
+ 8000728:	b480      	push	{r7}
+ 800072a:	b085      	sub	sp, #20
+ 800072c:	af00      	add	r7, sp, #0
+ 800072e:	60f8      	str	r0, [r7, #12]
+ 8000730:	60b9      	str	r1, [r7, #8]
+ 8000732:	607a      	str	r2, [r7, #4]
+  *ppxTimerTaskTCBBuffer = &xTimerTaskTCBBuffer;
+ 8000734:	68fb      	ldr	r3, [r7, #12]
+ 8000736:	4a07      	ldr	r2, [pc, #28]	; (8000754 <vApplicationGetTimerTaskMemory+0x2c>)
+ 8000738:	601a      	str	r2, [r3, #0]
+  *ppxTimerTaskStackBuffer = &xTimerStack[0];
+ 800073a:	68bb      	ldr	r3, [r7, #8]
+ 800073c:	4a06      	ldr	r2, [pc, #24]	; (8000758 <vApplicationGetTimerTaskMemory+0x30>)
+ 800073e:	601a      	str	r2, [r3, #0]
+  *pulTimerTaskStackSize = configTIMER_TASK_STACK_DEPTH;
+ 8000740:	687b      	ldr	r3, [r7, #4]
+ 8000742:	f44f 7200 	mov.w	r2, #512	; 0x200
+ 8000746:	601a      	str	r2, [r3, #0]
+  /* place for user code */
+}
+ 8000748:	bf00      	nop
+ 800074a:	3714      	adds	r7, #20
+ 800074c:	46bd      	mov	sp, r7
+ 800074e:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8000752:	4770      	bx	lr
+ 8000754:	24000514 	.word	0x24000514
+ 8000758:	24000568 	.word	0x24000568
+
+0800075c <ITM_SendChar>:
+           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+  \param [in]     ch  Character to transmit.
+  \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ 800075c:	b480      	push	{r7}
+ 800075e:	b083      	sub	sp, #12
+ 8000760:	af00      	add	r7, sp, #0
+ 8000762:	6078      	str	r0, [r7, #4]
+  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
+ 8000764:	f04f 4360 	mov.w	r3, #3758096384	; 0xe0000000
+ 8000768:	f8d3 3e80 	ldr.w	r3, [r3, #3712]	; 0xe80
+ 800076c:	f003 0301 	and.w	r3, r3, #1
+ 8000770:	2b00      	cmp	r3, #0
+ 8000772:	d013      	beq.n	800079c <ITM_SendChar+0x40>
+      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
+ 8000774:	f04f 4360 	mov.w	r3, #3758096384	; 0xe0000000
+ 8000778:	f8d3 3e00 	ldr.w	r3, [r3, #3584]	; 0xe00
+ 800077c:	f003 0301 	and.w	r3, r3, #1
+  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
+ 8000780:	2b00      	cmp	r3, #0
+ 8000782:	d00b      	beq.n	800079c <ITM_SendChar+0x40>
+  {
+    while (ITM->PORT[0U].u32 == 0UL)
+ 8000784:	e000      	b.n	8000788 <ITM_SendChar+0x2c>
+    {
+      __NOP();
+ 8000786:	bf00      	nop
+    while (ITM->PORT[0U].u32 == 0UL)
+ 8000788:	f04f 4360 	mov.w	r3, #3758096384	; 0xe0000000
+ 800078c:	681b      	ldr	r3, [r3, #0]
+ 800078e:	2b00      	cmp	r3, #0
+ 8000790:	d0f9      	beq.n	8000786 <ITM_SendChar+0x2a>
+    }
+    ITM->PORT[0U].u8 = (uint8_t)ch;
+ 8000792:	f04f 4360 	mov.w	r3, #3758096384	; 0xe0000000
+ 8000796:	687a      	ldr	r2, [r7, #4]
+ 8000798:	b2d2      	uxtb	r2, r2
+ 800079a:	701a      	strb	r2, [r3, #0]
+  }
+  return (ch);
+ 800079c:	687b      	ldr	r3, [r7, #4]
+}
+ 800079e:	4618      	mov	r0, r3
+ 80007a0:	370c      	adds	r7, #12
+ 80007a2:	46bd      	mov	sp, r7
+ 80007a4:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 80007a8:	4770      	bx	lr
+
+080007aa <_write>:
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+int _write(int32_t file, uint8_t *ptr, int32_t len) {
+ 80007aa:	b580      	push	{r7, lr}
+ 80007ac:	b086      	sub	sp, #24
+ 80007ae:	af00      	add	r7, sp, #0
+ 80007b0:	60f8      	str	r0, [r7, #12]
+ 80007b2:	60b9      	str	r1, [r7, #8]
+ 80007b4:	607a      	str	r2, [r7, #4]
+	for (int32_t i = 0; i < len; ++i)
+ 80007b6:	2300      	movs	r3, #0
+ 80007b8:	617b      	str	r3, [r7, #20]
+ 80007ba:	e009      	b.n	80007d0 <_write+0x26>
+		ITM_SendChar(*ptr++);
+ 80007bc:	68bb      	ldr	r3, [r7, #8]
+ 80007be:	1c5a      	adds	r2, r3, #1
+ 80007c0:	60ba      	str	r2, [r7, #8]
+ 80007c2:	781b      	ldrb	r3, [r3, #0]
+ 80007c4:	4618      	mov	r0, r3
+ 80007c6:	f7ff ffc9 	bl	800075c <ITM_SendChar>
+	for (int32_t i = 0; i < len; ++i)
+ 80007ca:	697b      	ldr	r3, [r7, #20]
+ 80007cc:	3301      	adds	r3, #1
+ 80007ce:	617b      	str	r3, [r7, #20]
+ 80007d0:	697a      	ldr	r2, [r7, #20]
+ 80007d2:	687b      	ldr	r3, [r7, #4]
+ 80007d4:	429a      	cmp	r2, r3
+ 80007d6:	dbf1      	blt.n	80007bc <_write+0x12>
+	return len;
+ 80007d8:	687b      	ldr	r3, [r7, #4]
+}
+ 80007da:	4618      	mov	r0, r3
+ 80007dc:	3718      	adds	r7, #24
+ 80007de:	46bd      	mov	sp, r7
+ 80007e0:	bd80      	pop	{r7, pc}
+	...
+
+080007e4 <main>:
+/**
+  * @brief  The application entry point.
+  * @retval int
+  */
+int main(void)
+{
+ 80007e4:	b5b0      	push	{r4, r5, r7, lr}
+ 80007e6:	b092      	sub	sp, #72	; 0x48
+ 80007e8:	af00      	add	r7, sp, #0
+  /* USER CODE BEGIN 1 */
+
+  /* USER CODE END 1 */
+
+  /* MPU Configuration--------------------------------------------------------*/
+  MPU_Config();
+ 80007ea:	f000 fe13 	bl	8001414 <MPU_Config>
+    if (SCB->CCR & SCB_CCR_IC_Msk) return;  /* return if ICache is already enabled */
+ 80007ee:	4b55      	ldr	r3, [pc, #340]	; (8000944 <main+0x160>)
+ 80007f0:	695b      	ldr	r3, [r3, #20]
+ 80007f2:	f403 3300 	and.w	r3, r3, #131072	; 0x20000
+ 80007f6:	2b00      	cmp	r3, #0
+ 80007f8:	d11b      	bne.n	8000832 <main+0x4e>
+  \details Acts as a special kind of Data Memory Barrier.
+           It completes when all explicit memory accesses before this instruction complete.
+ */
+__STATIC_FORCEINLINE void __DSB(void)
+{
+  __ASM volatile ("dsb 0xF":::"memory");
+ 80007fa:	f3bf 8f4f 	dsb	sy
+}
+ 80007fe:	bf00      	nop
+  __ASM volatile ("isb 0xF":::"memory");
+ 8000800:	f3bf 8f6f 	isb	sy
+}
+ 8000804:	bf00      	nop
+    SCB->ICIALLU = 0UL;                     /* invalidate I-Cache */
+ 8000806:	4b4f      	ldr	r3, [pc, #316]	; (8000944 <main+0x160>)
+ 8000808:	2200      	movs	r2, #0
+ 800080a:	f8c3 2250 	str.w	r2, [r3, #592]	; 0x250
+  __ASM volatile ("dsb 0xF":::"memory");
+ 800080e:	f3bf 8f4f 	dsb	sy
+}
+ 8000812:	bf00      	nop
+  __ASM volatile ("isb 0xF":::"memory");
+ 8000814:	f3bf 8f6f 	isb	sy
+}
+ 8000818:	bf00      	nop
+    SCB->CCR |=  (uint32_t)SCB_CCR_IC_Msk;  /* enable I-Cache */
+ 800081a:	4b4a      	ldr	r3, [pc, #296]	; (8000944 <main+0x160>)
+ 800081c:	695b      	ldr	r3, [r3, #20]
+ 800081e:	4a49      	ldr	r2, [pc, #292]	; (8000944 <main+0x160>)
+ 8000820:	f443 3300 	orr.w	r3, r3, #131072	; 0x20000
+ 8000824:	6153      	str	r3, [r2, #20]
+  __ASM volatile ("dsb 0xF":::"memory");
+ 8000826:	f3bf 8f4f 	dsb	sy
+}
+ 800082a:	bf00      	nop
+  __ASM volatile ("isb 0xF":::"memory");
+ 800082c:	f3bf 8f6f 	isb	sy
+}
+ 8000830:	e000      	b.n	8000834 <main+0x50>
+    if (SCB->CCR & SCB_CCR_IC_Msk) return;  /* return if ICache is already enabled */
+ 8000832:	bf00      	nop
+    if (SCB->CCR & SCB_CCR_DC_Msk) return;  /* return if DCache is already enabled */
+ 8000834:	4b43      	ldr	r3, [pc, #268]	; (8000944 <main+0x160>)
+ 8000836:	695b      	ldr	r3, [r3, #20]
+ 8000838:	f403 3380 	and.w	r3, r3, #65536	; 0x10000
+ 800083c:	2b00      	cmp	r3, #0
+ 800083e:	d138      	bne.n	80008b2 <main+0xce>
+    SCB->CSSELR = 0U;                       /* select Level 1 data cache */
+ 8000840:	4b40      	ldr	r3, [pc, #256]	; (8000944 <main+0x160>)
+ 8000842:	2200      	movs	r2, #0
+ 8000844:	f8c3 2084 	str.w	r2, [r3, #132]	; 0x84
+  __ASM volatile ("dsb 0xF":::"memory");
+ 8000848:	f3bf 8f4f 	dsb	sy
+}
+ 800084c:	bf00      	nop
+    ccsidr = SCB->CCSIDR;
+ 800084e:	4b3d      	ldr	r3, [pc, #244]	; (8000944 <main+0x160>)
+ 8000850:	f8d3 3080 	ldr.w	r3, [r3, #128]	; 0x80
+ 8000854:	647b      	str	r3, [r7, #68]	; 0x44
+    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+ 8000856:	6c7b      	ldr	r3, [r7, #68]	; 0x44
+ 8000858:	0b5b      	lsrs	r3, r3, #13
+ 800085a:	f3c3 030e 	ubfx	r3, r3, #0, #15
+ 800085e:	643b      	str	r3, [r7, #64]	; 0x40
+      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+ 8000860:	6c7b      	ldr	r3, [r7, #68]	; 0x44
+ 8000862:	08db      	lsrs	r3, r3, #3
+ 8000864:	f3c3 0309 	ubfx	r3, r3, #0, #10
+ 8000868:	63fb      	str	r3, [r7, #60]	; 0x3c
+        SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
+ 800086a:	6c3b      	ldr	r3, [r7, #64]	; 0x40
+ 800086c:	015a      	lsls	r2, r3, #5
+ 800086e:	f643 73e0 	movw	r3, #16352	; 0x3fe0
+ 8000872:	4013      	ands	r3, r2
+                      ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk)  );
+ 8000874:	6bfa      	ldr	r2, [r7, #60]	; 0x3c
+ 8000876:	0792      	lsls	r2, r2, #30
+        SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
+ 8000878:	4932      	ldr	r1, [pc, #200]	; (8000944 <main+0x160>)
+ 800087a:	4313      	orrs	r3, r2
+ 800087c:	f8c1 3260 	str.w	r3, [r1, #608]	; 0x260
+      } while (ways-- != 0U);
+ 8000880:	6bfb      	ldr	r3, [r7, #60]	; 0x3c
+ 8000882:	1e5a      	subs	r2, r3, #1
+ 8000884:	63fa      	str	r2, [r7, #60]	; 0x3c
+ 8000886:	2b00      	cmp	r3, #0
+ 8000888:	d1ef      	bne.n	800086a <main+0x86>
+    } while(sets-- != 0U);
+ 800088a:	6c3b      	ldr	r3, [r7, #64]	; 0x40
+ 800088c:	1e5a      	subs	r2, r3, #1
+ 800088e:	643a      	str	r2, [r7, #64]	; 0x40
+ 8000890:	2b00      	cmp	r3, #0
+ 8000892:	d1e5      	bne.n	8000860 <main+0x7c>
+  __ASM volatile ("dsb 0xF":::"memory");
+ 8000894:	f3bf 8f4f 	dsb	sy
+}
+ 8000898:	bf00      	nop
+    SCB->CCR |=  (uint32_t)SCB_CCR_DC_Msk;  /* enable D-Cache */
+ 800089a:	4b2a      	ldr	r3, [pc, #168]	; (8000944 <main+0x160>)
+ 800089c:	695b      	ldr	r3, [r3, #20]
+ 800089e:	4a29      	ldr	r2, [pc, #164]	; (8000944 <main+0x160>)
+ 80008a0:	f443 3380 	orr.w	r3, r3, #65536	; 0x10000
+ 80008a4:	6153      	str	r3, [r2, #20]
+  __ASM volatile ("dsb 0xF":::"memory");
+ 80008a6:	f3bf 8f4f 	dsb	sy
+}
+ 80008aa:	bf00      	nop
+  __ASM volatile ("isb 0xF":::"memory");
+ 80008ac:	f3bf 8f6f 	isb	sy
+}
+ 80008b0:	e000      	b.n	80008b4 <main+0xd0>
+    if (SCB->CCR & SCB_CCR_DC_Msk) return;  /* return if DCache is already enabled */
+ 80008b2:	bf00      	nop
+  SCB_EnableDCache();
+
+  /* MCU Configuration--------------------------------------------------------*/
+
+  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+  HAL_Init();
+ 80008b4:	f001 fd06 	bl	80022c4 <HAL_Init>
+  /* USER CODE BEGIN Init */
+
+  /* USER CODE END Init */
+
+  /* Configure the system clock */
+  SystemClock_Config();
+ 80008b8:	f000 f84e 	bl	8000958 <SystemClock_Config>
+  /* USER CODE BEGIN SysInit */
+
+  /* USER CODE END SysInit */
+
+  /* Initialize all configured peripherals */
+  MX_GPIO_Init();
+ 80008bc:	f000 fbc2 	bl	8001044 <MX_GPIO_Init>
+  MX_DMA_Init();
+ 80008c0:	f000 fb3c 	bl	8000f3c <MX_DMA_Init>
+  MX_MDMA_Init();
+ 80008c4:	f000 fb5a 	bl	8000f7c <MX_MDMA_Init>
+  MX_FDCAN3_Init();
+ 80008c8:	f000 f980 	bl	8000bcc <MX_FDCAN3_Init>
+  MX_SDMMC1_SD_Init();
+ 80008cc:	f000 f9e4 	bl	8000c98 <MX_SDMMC1_SD_Init>
+  MX_TIM3_Init();
+ 80008d0:	f000 fa02 	bl	8000cd8 <MX_TIM3_Init>
+  MX_UART4_Init();
+ 80008d4:	f000 fa4e 	bl	8000d74 <MX_UART4_Init>
+  MX_UART7_Init();
+ 80008d8:	f000 fa98 	bl	8000e0c <MX_UART7_Init>
+  MX_FDCAN1_Init();
+ 80008dc:	f000 f8aa 	bl	8000a34 <MX_FDCAN1_Init>
+  MX_FDCAN2_Init();
+ 80008e0:	f000 f90e 	bl	8000b00 <MX_FDCAN2_Init>
+  MX_FATFS_Init();
+ 80008e4:	f00e f8b4 	bl	800ea50 <MX_FATFS_Init>
+  MX_UART8_Init();
+ 80008e8:	f000 fadc 	bl	8000ea4 <MX_UART8_Init>
+	/* add queues, ... */
+  /* USER CODE END RTOS_QUEUES */
+
+  /* Create the thread(s) */
+  /* definition and creation of defaultTask */
+  osThreadStaticDef(defaultTask, StartDefaultTask, osPriorityNormal, 0, 4096, defaultTaskBuffer, &defaultTaskControlBlock);
+ 80008ec:	4b16      	ldr	r3, [pc, #88]	; (8000948 <main+0x164>)
+ 80008ee:	f107 0420 	add.w	r4, r7, #32
+ 80008f2:	461d      	mov	r5, r3
+ 80008f4:	cd0f      	ldmia	r5!, {r0, r1, r2, r3}
+ 80008f6:	c40f      	stmia	r4!, {r0, r1, r2, r3}
+ 80008f8:	e895 0007 	ldmia.w	r5, {r0, r1, r2}
+ 80008fc:	e884 0007 	stmia.w	r4, {r0, r1, r2}
+  defaultTaskHandle = osThreadCreate(osThread(defaultTask), NULL);
+ 8000900:	f107 0320 	add.w	r3, r7, #32
+ 8000904:	2100      	movs	r1, #0
+ 8000906:	4618      	mov	r0, r3
+ 8000908:	f00f fcee 	bl	80102e8 <osThreadCreate>
+ 800090c:	4603      	mov	r3, r0
+ 800090e:	4a0f      	ldr	r2, [pc, #60]	; (800094c <main+0x168>)
+ 8000910:	6013      	str	r3, [r2, #0]
+
+  /* definition and creation of debugTask */
+  osThreadStaticDef(debugTask, StartDebugTask, osPriorityNormal, 0, 2048, debugTaskBuffer, &debugTaskControlBlock);
+ 8000912:	4b0f      	ldr	r3, [pc, #60]	; (8000950 <main+0x16c>)
+ 8000914:	1d3c      	adds	r4, r7, #4
+ 8000916:	461d      	mov	r5, r3
+ 8000918:	cd0f      	ldmia	r5!, {r0, r1, r2, r3}
+ 800091a:	c40f      	stmia	r4!, {r0, r1, r2, r3}
+ 800091c:	e895 0007 	ldmia.w	r5, {r0, r1, r2}
+ 8000920:	e884 0007 	stmia.w	r4, {r0, r1, r2}
+  debugTaskHandle = osThreadCreate(osThread(debugTask), NULL);
+ 8000924:	1d3b      	adds	r3, r7, #4
+ 8000926:	2100      	movs	r1, #0
+ 8000928:	4618      	mov	r0, r3
+ 800092a:	f00f fcdd 	bl	80102e8 <osThreadCreate>
+ 800092e:	4603      	mov	r3, r0
+ 8000930:	4a08      	ldr	r2, [pc, #32]	; (8000954 <main+0x170>)
+ 8000932:	6013      	str	r3, [r2, #0]
+  /* USER CODE BEGIN RTOS_THREADS */
+	/* add threads, ... */
+  /* USER CODE END RTOS_THREADS */
+
+  /* Start scheduler */
+  osKernelStart();
+ 8000934:	f00f fcb5 	bl	80102a2 <osKernelStart>
+ 8000938:	2300      	movs	r3, #0
+
+    /* USER CODE BEGIN 3 */
+	}
+#endif
+  /* USER CODE END 3 */
+}
+ 800093a:	4618      	mov	r0, r3
+ 800093c:	3748      	adds	r7, #72	; 0x48
+ 800093e:	46bd      	mov	sp, r7
+ 8000940:	bdb0      	pop	{r4, r5, r7, pc}
+ 8000942:	bf00      	nop
+ 8000944:	e000ed00 	.word	0xe000ed00
+ 8000948:	08022cf0 	.word	0x08022cf0
+ 800094c:	240012b0 	.word	0x240012b0
+ 8000950:	08022d18 	.word	0x08022d18
+ 8000954:	24005308 	.word	0x24005308
+
+08000958 <SystemClock_Config>:
+/**
+  * @brief System Clock Configuration
+  * @retval None
+  */
+void SystemClock_Config(void)
+{
+ 8000958:	b580      	push	{r7, lr}
+ 800095a:	b09c      	sub	sp, #112	; 0x70
+ 800095c:	af00      	add	r7, sp, #0
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+ 800095e:	f107 0324 	add.w	r3, r7, #36	; 0x24
+ 8000962:	224c      	movs	r2, #76	; 0x4c
+ 8000964:	2100      	movs	r1, #0
+ 8000966:	4618      	mov	r0, r3
+ 8000968:	f021 f9ba 	bl	8021ce0 <memset>
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+ 800096c:	1d3b      	adds	r3, r7, #4
+ 800096e:	2220      	movs	r2, #32
+ 8000970:	2100      	movs	r1, #0
+ 8000972:	4618      	mov	r0, r3
+ 8000974:	f021 f9b4 	bl	8021ce0 <memset>
+
+  /** Supply configuration update enable
+  */
+  HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY);
+ 8000978:	2002      	movs	r0, #2
+ 800097a:	f006 fb7d 	bl	8007078 <HAL_PWREx_ConfigSupply>
+
+  /** Configure the main internal regulator output voltage
+  */
+  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE0);
+ 800097e:	2300      	movs	r3, #0
+ 8000980:	603b      	str	r3, [r7, #0]
+ 8000982:	4b2b      	ldr	r3, [pc, #172]	; (8000a30 <SystemClock_Config+0xd8>)
+ 8000984:	699b      	ldr	r3, [r3, #24]
+ 8000986:	4a2a      	ldr	r2, [pc, #168]	; (8000a30 <SystemClock_Config+0xd8>)
+ 8000988:	f423 4340 	bic.w	r3, r3, #49152	; 0xc000
+ 800098c:	6193      	str	r3, [r2, #24]
+ 800098e:	4b28      	ldr	r3, [pc, #160]	; (8000a30 <SystemClock_Config+0xd8>)
+ 8000990:	699b      	ldr	r3, [r3, #24]
+ 8000992:	f403 4340 	and.w	r3, r3, #49152	; 0xc000
+ 8000996:	603b      	str	r3, [r7, #0]
+ 8000998:	683b      	ldr	r3, [r7, #0]
+
+  while(!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {}
+ 800099a:	bf00      	nop
+ 800099c:	4b24      	ldr	r3, [pc, #144]	; (8000a30 <SystemClock_Config+0xd8>)
+ 800099e:	699b      	ldr	r3, [r3, #24]
+ 80009a0:	f403 5300 	and.w	r3, r3, #8192	; 0x2000
+ 80009a4:	f5b3 5f00 	cmp.w	r3, #8192	; 0x2000
+ 80009a8:	d1f8      	bne.n	800099c <SystemClock_Config+0x44>
+
+  /** Initializes the RCC Oscillators according to the specified parameters
+  * in the RCC_OscInitTypeDef structure.
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
+ 80009aa:	2301      	movs	r3, #1
+ 80009ac:	627b      	str	r3, [r7, #36]	; 0x24
+  RCC_OscInitStruct.HSEState = RCC_HSE_ON;
+ 80009ae:	f44f 3380 	mov.w	r3, #65536	; 0x10000
+ 80009b2:	62bb      	str	r3, [r7, #40]	; 0x28
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ 80009b4:	2302      	movs	r3, #2
+ 80009b6:	64bb      	str	r3, [r7, #72]	; 0x48
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
+ 80009b8:	2302      	movs	r3, #2
+ 80009ba:	64fb      	str	r3, [r7, #76]	; 0x4c
+  RCC_OscInitStruct.PLL.PLLM = 5;
+ 80009bc:	2305      	movs	r3, #5
+ 80009be:	653b      	str	r3, [r7, #80]	; 0x50
+  RCC_OscInitStruct.PLL.PLLN = 96;
+ 80009c0:	2360      	movs	r3, #96	; 0x60
+ 80009c2:	657b      	str	r3, [r7, #84]	; 0x54
+  RCC_OscInitStruct.PLL.PLLP = 1;
+ 80009c4:	2301      	movs	r3, #1
+ 80009c6:	65bb      	str	r3, [r7, #88]	; 0x58
+  RCC_OscInitStruct.PLL.PLLQ = 4;
+ 80009c8:	2304      	movs	r3, #4
+ 80009ca:	65fb      	str	r3, [r7, #92]	; 0x5c
+  RCC_OscInitStruct.PLL.PLLR = 2;
+ 80009cc:	2302      	movs	r3, #2
+ 80009ce:	663b      	str	r3, [r7, #96]	; 0x60
+  RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_2;
+ 80009d0:	2308      	movs	r3, #8
+ 80009d2:	667b      	str	r3, [r7, #100]	; 0x64
+  RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE;
+ 80009d4:	2300      	movs	r3, #0
+ 80009d6:	66bb      	str	r3, [r7, #104]	; 0x68
+  RCC_OscInitStruct.PLL.PLLFRACN = 0;
+ 80009d8:	2300      	movs	r3, #0
+ 80009da:	66fb      	str	r3, [r7, #108]	; 0x6c
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+ 80009dc:	f107 0324 	add.w	r3, r7, #36	; 0x24
+ 80009e0:	4618      	mov	r0, r3
+ 80009e2:	f006 fb83 	bl	80070ec <HAL_RCC_OscConfig>
+ 80009e6:	4603      	mov	r3, r0
+ 80009e8:	2b00      	cmp	r3, #0
+ 80009ea:	d001      	beq.n	80009f0 <SystemClock_Config+0x98>
+  {
+    Error_Handler();
+ 80009ec:	f000 fd82 	bl	80014f4 <Error_Handler>
+  }
+
+  /** Initializes the CPU, AHB and APB buses clocks
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+ 80009f0:	233f      	movs	r3, #63	; 0x3f
+ 80009f2:	607b      	str	r3, [r7, #4]
+                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2
+                              |RCC_CLOCKTYPE_D3PCLK1|RCC_CLOCKTYPE_D1PCLK1;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+ 80009f4:	2303      	movs	r3, #3
+ 80009f6:	60bb      	str	r3, [r7, #8]
+  RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1;
+ 80009f8:	2300      	movs	r3, #0
+ 80009fa:	60fb      	str	r3, [r7, #12]
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2;
+ 80009fc:	2308      	movs	r3, #8
+ 80009fe:	613b      	str	r3, [r7, #16]
+  RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2;
+ 8000a00:	2340      	movs	r3, #64	; 0x40
+ 8000a02:	617b      	str	r3, [r7, #20]
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2;
+ 8000a04:	2340      	movs	r3, #64	; 0x40
+ 8000a06:	61bb      	str	r3, [r7, #24]
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2;
+ 8000a08:	f44f 6380 	mov.w	r3, #1024	; 0x400
+ 8000a0c:	61fb      	str	r3, [r7, #28]
+  RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2;
+ 8000a0e:	2340      	movs	r3, #64	; 0x40
+ 8000a10:	623b      	str	r3, [r7, #32]
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK)
+ 8000a12:	1d3b      	adds	r3, r7, #4
+ 8000a14:	2103      	movs	r1, #3
+ 8000a16:	4618      	mov	r0, r3
+ 8000a18:	f006 ff42 	bl	80078a0 <HAL_RCC_ClockConfig>
+ 8000a1c:	4603      	mov	r3, r0
+ 8000a1e:	2b00      	cmp	r3, #0
+ 8000a20:	d001      	beq.n	8000a26 <SystemClock_Config+0xce>
+  {
+    Error_Handler();
+ 8000a22:	f000 fd67 	bl	80014f4 <Error_Handler>
+  }
+}
+ 8000a26:	bf00      	nop
+ 8000a28:	3770      	adds	r7, #112	; 0x70
+ 8000a2a:	46bd      	mov	sp, r7
+ 8000a2c:	bd80      	pop	{r7, pc}
+ 8000a2e:	bf00      	nop
+ 8000a30:	58024800 	.word	0x58024800
+
+08000a34 <MX_FDCAN1_Init>:
+  * @brief FDCAN1 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_FDCAN1_Init(void)
+{
+ 8000a34:	b580      	push	{r7, lr}
+ 8000a36:	af00      	add	r7, sp, #0
+  /* USER CODE END FDCAN1_Init 0 */
+
+  /* USER CODE BEGIN FDCAN1_Init 1 */
+
+  /* USER CODE END FDCAN1_Init 1 */
+  hfdcan1.Instance = FDCAN1;
+ 8000a38:	4b2f      	ldr	r3, [pc, #188]	; (8000af8 <MX_FDCAN1_Init+0xc4>)
+ 8000a3a:	4a30      	ldr	r2, [pc, #192]	; (8000afc <MX_FDCAN1_Init+0xc8>)
+ 8000a3c:	601a      	str	r2, [r3, #0]
+  hfdcan1.Init.FrameFormat = FDCAN_FRAME_FD_BRS;
+ 8000a3e:	4b2e      	ldr	r3, [pc, #184]	; (8000af8 <MX_FDCAN1_Init+0xc4>)
+ 8000a40:	f44f 7240 	mov.w	r2, #768	; 0x300
+ 8000a44:	609a      	str	r2, [r3, #8]
+  hfdcan1.Init.Mode = FDCAN_MODE_NORMAL;
+ 8000a46:	4b2c      	ldr	r3, [pc, #176]	; (8000af8 <MX_FDCAN1_Init+0xc4>)
+ 8000a48:	2200      	movs	r2, #0
+ 8000a4a:	60da      	str	r2, [r3, #12]
+  hfdcan1.Init.AutoRetransmission = DISABLE;
+ 8000a4c:	4b2a      	ldr	r3, [pc, #168]	; (8000af8 <MX_FDCAN1_Init+0xc4>)
+ 8000a4e:	2200      	movs	r2, #0
+ 8000a50:	741a      	strb	r2, [r3, #16]
+  hfdcan1.Init.TransmitPause = DISABLE;
+ 8000a52:	4b29      	ldr	r3, [pc, #164]	; (8000af8 <MX_FDCAN1_Init+0xc4>)
+ 8000a54:	2200      	movs	r2, #0
+ 8000a56:	745a      	strb	r2, [r3, #17]
+  hfdcan1.Init.ProtocolException = DISABLE;
+ 8000a58:	4b27      	ldr	r3, [pc, #156]	; (8000af8 <MX_FDCAN1_Init+0xc4>)
+ 8000a5a:	2200      	movs	r2, #0
+ 8000a5c:	749a      	strb	r2, [r3, #18]
+  hfdcan1.Init.NominalPrescaler = 6;
+ 8000a5e:	4b26      	ldr	r3, [pc, #152]	; (8000af8 <MX_FDCAN1_Init+0xc4>)
+ 8000a60:	2206      	movs	r2, #6
+ 8000a62:	615a      	str	r2, [r3, #20]
+  hfdcan1.Init.NominalSyncJumpWidth = 4;
+ 8000a64:	4b24      	ldr	r3, [pc, #144]	; (8000af8 <MX_FDCAN1_Init+0xc4>)
+ 8000a66:	2204      	movs	r2, #4
+ 8000a68:	619a      	str	r2, [r3, #24]
+  hfdcan1.Init.NominalTimeSeg1 = 29;
+ 8000a6a:	4b23      	ldr	r3, [pc, #140]	; (8000af8 <MX_FDCAN1_Init+0xc4>)
+ 8000a6c:	221d      	movs	r2, #29
+ 8000a6e:	61da      	str	r2, [r3, #28]
+  hfdcan1.Init.NominalTimeSeg2 = 10;
+ 8000a70:	4b21      	ldr	r3, [pc, #132]	; (8000af8 <MX_FDCAN1_Init+0xc4>)
+ 8000a72:	220a      	movs	r2, #10
+ 8000a74:	621a      	str	r2, [r3, #32]
+  hfdcan1.Init.DataPrescaler = 4;
+ 8000a76:	4b20      	ldr	r3, [pc, #128]	; (8000af8 <MX_FDCAN1_Init+0xc4>)
+ 8000a78:	2204      	movs	r2, #4
+ 8000a7a:	625a      	str	r2, [r3, #36]	; 0x24
+  hfdcan1.Init.DataSyncJumpWidth = 4;
+ 8000a7c:	4b1e      	ldr	r3, [pc, #120]	; (8000af8 <MX_FDCAN1_Init+0xc4>)
+ 8000a7e:	2204      	movs	r2, #4
+ 8000a80:	629a      	str	r2, [r3, #40]	; 0x28
+  hfdcan1.Init.DataTimeSeg1 = 11;
+ 8000a82:	4b1d      	ldr	r3, [pc, #116]	; (8000af8 <MX_FDCAN1_Init+0xc4>)
+ 8000a84:	220b      	movs	r2, #11
+ 8000a86:	62da      	str	r2, [r3, #44]	; 0x2c
+  hfdcan1.Init.DataTimeSeg2 = 3;
+ 8000a88:	4b1b      	ldr	r3, [pc, #108]	; (8000af8 <MX_FDCAN1_Init+0xc4>)
+ 8000a8a:	2203      	movs	r2, #3
+ 8000a8c:	631a      	str	r2, [r3, #48]	; 0x30
+  hfdcan1.Init.MessageRAMOffset = 0;
+ 8000a8e:	4b1a      	ldr	r3, [pc, #104]	; (8000af8 <MX_FDCAN1_Init+0xc4>)
+ 8000a90:	2200      	movs	r2, #0
+ 8000a92:	635a      	str	r2, [r3, #52]	; 0x34
+  hfdcan1.Init.StdFiltersNbr = 0;
+ 8000a94:	4b18      	ldr	r3, [pc, #96]	; (8000af8 <MX_FDCAN1_Init+0xc4>)
+ 8000a96:	2200      	movs	r2, #0
+ 8000a98:	639a      	str	r2, [r3, #56]	; 0x38
+  hfdcan1.Init.ExtFiltersNbr = 0;
+ 8000a9a:	4b17      	ldr	r3, [pc, #92]	; (8000af8 <MX_FDCAN1_Init+0xc4>)
+ 8000a9c:	2200      	movs	r2, #0
+ 8000a9e:	63da      	str	r2, [r3, #60]	; 0x3c
+  hfdcan1.Init.RxFifo0ElmtsNbr = 8;
+ 8000aa0:	4b15      	ldr	r3, [pc, #84]	; (8000af8 <MX_FDCAN1_Init+0xc4>)
+ 8000aa2:	2208      	movs	r2, #8
+ 8000aa4:	641a      	str	r2, [r3, #64]	; 0x40
+  hfdcan1.Init.RxFifo0ElmtSize = FDCAN_DATA_BYTES_64;
+ 8000aa6:	4b14      	ldr	r3, [pc, #80]	; (8000af8 <MX_FDCAN1_Init+0xc4>)
+ 8000aa8:	2212      	movs	r2, #18
+ 8000aaa:	645a      	str	r2, [r3, #68]	; 0x44
+  hfdcan1.Init.RxFifo1ElmtsNbr = 0;
+ 8000aac:	4b12      	ldr	r3, [pc, #72]	; (8000af8 <MX_FDCAN1_Init+0xc4>)
+ 8000aae:	2200      	movs	r2, #0
+ 8000ab0:	649a      	str	r2, [r3, #72]	; 0x48
+  hfdcan1.Init.RxFifo1ElmtSize = FDCAN_DATA_BYTES_64;
+ 8000ab2:	4b11      	ldr	r3, [pc, #68]	; (8000af8 <MX_FDCAN1_Init+0xc4>)
+ 8000ab4:	2212      	movs	r2, #18
+ 8000ab6:	64da      	str	r2, [r3, #76]	; 0x4c
+  hfdcan1.Init.RxBuffersNbr = 0;
+ 8000ab8:	4b0f      	ldr	r3, [pc, #60]	; (8000af8 <MX_FDCAN1_Init+0xc4>)
+ 8000aba:	2200      	movs	r2, #0
+ 8000abc:	651a      	str	r2, [r3, #80]	; 0x50
+  hfdcan1.Init.RxBufferSize = FDCAN_DATA_BYTES_64;
+ 8000abe:	4b0e      	ldr	r3, [pc, #56]	; (8000af8 <MX_FDCAN1_Init+0xc4>)
+ 8000ac0:	2212      	movs	r2, #18
+ 8000ac2:	655a      	str	r2, [r3, #84]	; 0x54
+  hfdcan1.Init.TxEventsNbr = 8;
+ 8000ac4:	4b0c      	ldr	r3, [pc, #48]	; (8000af8 <MX_FDCAN1_Init+0xc4>)
+ 8000ac6:	2208      	movs	r2, #8
+ 8000ac8:	659a      	str	r2, [r3, #88]	; 0x58
+  hfdcan1.Init.TxBuffersNbr = 0;
+ 8000aca:	4b0b      	ldr	r3, [pc, #44]	; (8000af8 <MX_FDCAN1_Init+0xc4>)
+ 8000acc:	2200      	movs	r2, #0
+ 8000ace:	65da      	str	r2, [r3, #92]	; 0x5c
+  hfdcan1.Init.TxFifoQueueElmtsNbr = 8;
+ 8000ad0:	4b09      	ldr	r3, [pc, #36]	; (8000af8 <MX_FDCAN1_Init+0xc4>)
+ 8000ad2:	2208      	movs	r2, #8
+ 8000ad4:	661a      	str	r2, [r3, #96]	; 0x60
+  hfdcan1.Init.TxFifoQueueMode = FDCAN_TX_FIFO_OPERATION;
+ 8000ad6:	4b08      	ldr	r3, [pc, #32]	; (8000af8 <MX_FDCAN1_Init+0xc4>)
+ 8000ad8:	2200      	movs	r2, #0
+ 8000ada:	665a      	str	r2, [r3, #100]	; 0x64
+  hfdcan1.Init.TxElmtSize = FDCAN_DATA_BYTES_64;
+ 8000adc:	4b06      	ldr	r3, [pc, #24]	; (8000af8 <MX_FDCAN1_Init+0xc4>)
+ 8000ade:	2212      	movs	r2, #18
+ 8000ae0:	669a      	str	r2, [r3, #104]	; 0x68
+  if (HAL_FDCAN_Init(&hfdcan1) != HAL_OK)
+ 8000ae2:	4805      	ldr	r0, [pc, #20]	; (8000af8 <MX_FDCAN1_Init+0xc4>)
+ 8000ae4:	f004 fffe 	bl	8005ae4 <HAL_FDCAN_Init>
+ 8000ae8:	4603      	mov	r3, r0
+ 8000aea:	2b00      	cmp	r3, #0
+ 8000aec:	d001      	beq.n	8000af2 <MX_FDCAN1_Init+0xbe>
+  {
+    Error_Handler();
+ 8000aee:	f000 fd01 	bl	80014f4 <Error_Handler>
+  }
+  /* USER CODE BEGIN FDCAN1_Init 2 */
+
+  /* USER CODE END FDCAN1_Init 2 */
+
+}
+ 8000af2:	bf00      	nop
+ 8000af4:	bd80      	pop	{r7, pc}
+ 8000af6:	bf00      	nop
+ 8000af8:	24000d68 	.word	0x24000d68
+ 8000afc:	4000a000 	.word	0x4000a000
+
+08000b00 <MX_FDCAN2_Init>:
+  * @brief FDCAN2 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_FDCAN2_Init(void)
+{
+ 8000b00:	b580      	push	{r7, lr}
+ 8000b02:	af00      	add	r7, sp, #0
+  /* USER CODE END FDCAN2_Init 0 */
+
+  /* USER CODE BEGIN FDCAN2_Init 1 */
+
+  /* USER CODE END FDCAN2_Init 1 */
+  hfdcan2.Instance = FDCAN2;
+ 8000b04:	4b2f      	ldr	r3, [pc, #188]	; (8000bc4 <MX_FDCAN2_Init+0xc4>)
+ 8000b06:	4a30      	ldr	r2, [pc, #192]	; (8000bc8 <MX_FDCAN2_Init+0xc8>)
+ 8000b08:	601a      	str	r2, [r3, #0]
+  hfdcan2.Init.FrameFormat = FDCAN_FRAME_FD_BRS;
+ 8000b0a:	4b2e      	ldr	r3, [pc, #184]	; (8000bc4 <MX_FDCAN2_Init+0xc4>)
+ 8000b0c:	f44f 7240 	mov.w	r2, #768	; 0x300
+ 8000b10:	609a      	str	r2, [r3, #8]
+  hfdcan2.Init.Mode = FDCAN_MODE_NORMAL;
+ 8000b12:	4b2c      	ldr	r3, [pc, #176]	; (8000bc4 <MX_FDCAN2_Init+0xc4>)
+ 8000b14:	2200      	movs	r2, #0
+ 8000b16:	60da      	str	r2, [r3, #12]
+  hfdcan2.Init.AutoRetransmission = DISABLE;
+ 8000b18:	4b2a      	ldr	r3, [pc, #168]	; (8000bc4 <MX_FDCAN2_Init+0xc4>)
+ 8000b1a:	2200      	movs	r2, #0
+ 8000b1c:	741a      	strb	r2, [r3, #16]
+  hfdcan2.Init.TransmitPause = DISABLE;
+ 8000b1e:	4b29      	ldr	r3, [pc, #164]	; (8000bc4 <MX_FDCAN2_Init+0xc4>)
+ 8000b20:	2200      	movs	r2, #0
+ 8000b22:	745a      	strb	r2, [r3, #17]
+  hfdcan2.Init.ProtocolException = DISABLE;
+ 8000b24:	4b27      	ldr	r3, [pc, #156]	; (8000bc4 <MX_FDCAN2_Init+0xc4>)
+ 8000b26:	2200      	movs	r2, #0
+ 8000b28:	749a      	strb	r2, [r3, #18]
+  hfdcan2.Init.NominalPrescaler = 6;
+ 8000b2a:	4b26      	ldr	r3, [pc, #152]	; (8000bc4 <MX_FDCAN2_Init+0xc4>)
+ 8000b2c:	2206      	movs	r2, #6
+ 8000b2e:	615a      	str	r2, [r3, #20]
+  hfdcan2.Init.NominalSyncJumpWidth = 4;
+ 8000b30:	4b24      	ldr	r3, [pc, #144]	; (8000bc4 <MX_FDCAN2_Init+0xc4>)
+ 8000b32:	2204      	movs	r2, #4
+ 8000b34:	619a      	str	r2, [r3, #24]
+  hfdcan2.Init.NominalTimeSeg1 = 29;
+ 8000b36:	4b23      	ldr	r3, [pc, #140]	; (8000bc4 <MX_FDCAN2_Init+0xc4>)
+ 8000b38:	221d      	movs	r2, #29
+ 8000b3a:	61da      	str	r2, [r3, #28]
+  hfdcan2.Init.NominalTimeSeg2 = 10;
+ 8000b3c:	4b21      	ldr	r3, [pc, #132]	; (8000bc4 <MX_FDCAN2_Init+0xc4>)
+ 8000b3e:	220a      	movs	r2, #10
+ 8000b40:	621a      	str	r2, [r3, #32]
+  hfdcan2.Init.DataPrescaler = 4;
+ 8000b42:	4b20      	ldr	r3, [pc, #128]	; (8000bc4 <MX_FDCAN2_Init+0xc4>)
+ 8000b44:	2204      	movs	r2, #4
+ 8000b46:	625a      	str	r2, [r3, #36]	; 0x24
+  hfdcan2.Init.DataSyncJumpWidth = 4;
+ 8000b48:	4b1e      	ldr	r3, [pc, #120]	; (8000bc4 <MX_FDCAN2_Init+0xc4>)
+ 8000b4a:	2204      	movs	r2, #4
+ 8000b4c:	629a      	str	r2, [r3, #40]	; 0x28
+  hfdcan2.Init.DataTimeSeg1 = 11;
+ 8000b4e:	4b1d      	ldr	r3, [pc, #116]	; (8000bc4 <MX_FDCAN2_Init+0xc4>)
+ 8000b50:	220b      	movs	r2, #11
+ 8000b52:	62da      	str	r2, [r3, #44]	; 0x2c
+  hfdcan2.Init.DataTimeSeg2 = 3;
+ 8000b54:	4b1b      	ldr	r3, [pc, #108]	; (8000bc4 <MX_FDCAN2_Init+0xc4>)
+ 8000b56:	2203      	movs	r2, #3
+ 8000b58:	631a      	str	r2, [r3, #48]	; 0x30
+  hfdcan2.Init.MessageRAMOffset = 512;
+ 8000b5a:	4b1a      	ldr	r3, [pc, #104]	; (8000bc4 <MX_FDCAN2_Init+0xc4>)
+ 8000b5c:	f44f 7200 	mov.w	r2, #512	; 0x200
+ 8000b60:	635a      	str	r2, [r3, #52]	; 0x34
+  hfdcan2.Init.StdFiltersNbr = 0;
+ 8000b62:	4b18      	ldr	r3, [pc, #96]	; (8000bc4 <MX_FDCAN2_Init+0xc4>)
+ 8000b64:	2200      	movs	r2, #0
+ 8000b66:	639a      	str	r2, [r3, #56]	; 0x38
+  hfdcan2.Init.ExtFiltersNbr = 0;
+ 8000b68:	4b16      	ldr	r3, [pc, #88]	; (8000bc4 <MX_FDCAN2_Init+0xc4>)
+ 8000b6a:	2200      	movs	r2, #0
+ 8000b6c:	63da      	str	r2, [r3, #60]	; 0x3c
+  hfdcan2.Init.RxFifo0ElmtsNbr = 8;
+ 8000b6e:	4b15      	ldr	r3, [pc, #84]	; (8000bc4 <MX_FDCAN2_Init+0xc4>)
+ 8000b70:	2208      	movs	r2, #8
+ 8000b72:	641a      	str	r2, [r3, #64]	; 0x40
+  hfdcan2.Init.RxFifo0ElmtSize = FDCAN_DATA_BYTES_64;
+ 8000b74:	4b13      	ldr	r3, [pc, #76]	; (8000bc4 <MX_FDCAN2_Init+0xc4>)
+ 8000b76:	2212      	movs	r2, #18
+ 8000b78:	645a      	str	r2, [r3, #68]	; 0x44
+  hfdcan2.Init.RxFifo1ElmtsNbr = 0;
+ 8000b7a:	4b12      	ldr	r3, [pc, #72]	; (8000bc4 <MX_FDCAN2_Init+0xc4>)
+ 8000b7c:	2200      	movs	r2, #0
+ 8000b7e:	649a      	str	r2, [r3, #72]	; 0x48
+  hfdcan2.Init.RxFifo1ElmtSize = FDCAN_DATA_BYTES_64;
+ 8000b80:	4b10      	ldr	r3, [pc, #64]	; (8000bc4 <MX_FDCAN2_Init+0xc4>)
+ 8000b82:	2212      	movs	r2, #18
+ 8000b84:	64da      	str	r2, [r3, #76]	; 0x4c
+  hfdcan2.Init.RxBuffersNbr = 0;
+ 8000b86:	4b0f      	ldr	r3, [pc, #60]	; (8000bc4 <MX_FDCAN2_Init+0xc4>)
+ 8000b88:	2200      	movs	r2, #0
+ 8000b8a:	651a      	str	r2, [r3, #80]	; 0x50
+  hfdcan2.Init.RxBufferSize = FDCAN_DATA_BYTES_64;
+ 8000b8c:	4b0d      	ldr	r3, [pc, #52]	; (8000bc4 <MX_FDCAN2_Init+0xc4>)
+ 8000b8e:	2212      	movs	r2, #18
+ 8000b90:	655a      	str	r2, [r3, #84]	; 0x54
+  hfdcan2.Init.TxEventsNbr = 8;
+ 8000b92:	4b0c      	ldr	r3, [pc, #48]	; (8000bc4 <MX_FDCAN2_Init+0xc4>)
+ 8000b94:	2208      	movs	r2, #8
+ 8000b96:	659a      	str	r2, [r3, #88]	; 0x58
+  hfdcan2.Init.TxBuffersNbr = 0;
+ 8000b98:	4b0a      	ldr	r3, [pc, #40]	; (8000bc4 <MX_FDCAN2_Init+0xc4>)
+ 8000b9a:	2200      	movs	r2, #0
+ 8000b9c:	65da      	str	r2, [r3, #92]	; 0x5c
+  hfdcan2.Init.TxFifoQueueElmtsNbr = 8;
+ 8000b9e:	4b09      	ldr	r3, [pc, #36]	; (8000bc4 <MX_FDCAN2_Init+0xc4>)
+ 8000ba0:	2208      	movs	r2, #8
+ 8000ba2:	661a      	str	r2, [r3, #96]	; 0x60
+  hfdcan2.Init.TxFifoQueueMode = FDCAN_TX_FIFO_OPERATION;
+ 8000ba4:	4b07      	ldr	r3, [pc, #28]	; (8000bc4 <MX_FDCAN2_Init+0xc4>)
+ 8000ba6:	2200      	movs	r2, #0
+ 8000ba8:	665a      	str	r2, [r3, #100]	; 0x64
+  hfdcan2.Init.TxElmtSize = FDCAN_DATA_BYTES_64;
+ 8000baa:	4b06      	ldr	r3, [pc, #24]	; (8000bc4 <MX_FDCAN2_Init+0xc4>)
+ 8000bac:	2212      	movs	r2, #18
+ 8000bae:	669a      	str	r2, [r3, #104]	; 0x68
+  if (HAL_FDCAN_Init(&hfdcan2) != HAL_OK)
+ 8000bb0:	4804      	ldr	r0, [pc, #16]	; (8000bc4 <MX_FDCAN2_Init+0xc4>)
+ 8000bb2:	f004 ff97 	bl	8005ae4 <HAL_FDCAN_Init>
+ 8000bb6:	4603      	mov	r3, r0
+ 8000bb8:	2b00      	cmp	r3, #0
+ 8000bba:	d001      	beq.n	8000bc0 <MX_FDCAN2_Init+0xc0>
+  {
+    Error_Handler();
+ 8000bbc:	f000 fc9a 	bl	80014f4 <Error_Handler>
+  }
+  /* USER CODE BEGIN FDCAN2_Init 2 */
+
+  /* USER CODE END FDCAN2_Init 2 */
+
+}
+ 8000bc0:	bf00      	nop
+ 8000bc2:	bd80      	pop	{r7, pc}
+ 8000bc4:	24000e08 	.word	0x24000e08
+ 8000bc8:	4000a400 	.word	0x4000a400
+
+08000bcc <MX_FDCAN3_Init>:
+  * @brief FDCAN3 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_FDCAN3_Init(void)
+{
+ 8000bcc:	b580      	push	{r7, lr}
+ 8000bce:	af00      	add	r7, sp, #0
+  /* USER CODE END FDCAN3_Init 0 */
+
+  /* USER CODE BEGIN FDCAN3_Init 1 */
+
+  /* USER CODE END FDCAN3_Init 1 */
+  hfdcan3.Instance = FDCAN3;
+ 8000bd0:	4b2f      	ldr	r3, [pc, #188]	; (8000c90 <MX_FDCAN3_Init+0xc4>)
+ 8000bd2:	4a30      	ldr	r2, [pc, #192]	; (8000c94 <MX_FDCAN3_Init+0xc8>)
+ 8000bd4:	601a      	str	r2, [r3, #0]
+  hfdcan3.Init.FrameFormat = FDCAN_FRAME_FD_BRS;
+ 8000bd6:	4b2e      	ldr	r3, [pc, #184]	; (8000c90 <MX_FDCAN3_Init+0xc4>)
+ 8000bd8:	f44f 7240 	mov.w	r2, #768	; 0x300
+ 8000bdc:	609a      	str	r2, [r3, #8]
+  hfdcan3.Init.Mode = FDCAN_MODE_NORMAL;
+ 8000bde:	4b2c      	ldr	r3, [pc, #176]	; (8000c90 <MX_FDCAN3_Init+0xc4>)
+ 8000be0:	2200      	movs	r2, #0
+ 8000be2:	60da      	str	r2, [r3, #12]
+  hfdcan3.Init.AutoRetransmission = DISABLE;
+ 8000be4:	4b2a      	ldr	r3, [pc, #168]	; (8000c90 <MX_FDCAN3_Init+0xc4>)
+ 8000be6:	2200      	movs	r2, #0
+ 8000be8:	741a      	strb	r2, [r3, #16]
+  hfdcan3.Init.TransmitPause = DISABLE;
+ 8000bea:	4b29      	ldr	r3, [pc, #164]	; (8000c90 <MX_FDCAN3_Init+0xc4>)
+ 8000bec:	2200      	movs	r2, #0
+ 8000bee:	745a      	strb	r2, [r3, #17]
+  hfdcan3.Init.ProtocolException = DISABLE;
+ 8000bf0:	4b27      	ldr	r3, [pc, #156]	; (8000c90 <MX_FDCAN3_Init+0xc4>)
+ 8000bf2:	2200      	movs	r2, #0
+ 8000bf4:	749a      	strb	r2, [r3, #18]
+  hfdcan3.Init.NominalPrescaler = 6;
+ 8000bf6:	4b26      	ldr	r3, [pc, #152]	; (8000c90 <MX_FDCAN3_Init+0xc4>)
+ 8000bf8:	2206      	movs	r2, #6
+ 8000bfa:	615a      	str	r2, [r3, #20]
+  hfdcan3.Init.NominalSyncJumpWidth = 4;
+ 8000bfc:	4b24      	ldr	r3, [pc, #144]	; (8000c90 <MX_FDCAN3_Init+0xc4>)
+ 8000bfe:	2204      	movs	r2, #4
+ 8000c00:	619a      	str	r2, [r3, #24]
+  hfdcan3.Init.NominalTimeSeg1 = 29;
+ 8000c02:	4b23      	ldr	r3, [pc, #140]	; (8000c90 <MX_FDCAN3_Init+0xc4>)
+ 8000c04:	221d      	movs	r2, #29
+ 8000c06:	61da      	str	r2, [r3, #28]
+  hfdcan3.Init.NominalTimeSeg2 = 10;
+ 8000c08:	4b21      	ldr	r3, [pc, #132]	; (8000c90 <MX_FDCAN3_Init+0xc4>)
+ 8000c0a:	220a      	movs	r2, #10
+ 8000c0c:	621a      	str	r2, [r3, #32]
+  hfdcan3.Init.DataPrescaler = 4;
+ 8000c0e:	4b20      	ldr	r3, [pc, #128]	; (8000c90 <MX_FDCAN3_Init+0xc4>)
+ 8000c10:	2204      	movs	r2, #4
+ 8000c12:	625a      	str	r2, [r3, #36]	; 0x24
+  hfdcan3.Init.DataSyncJumpWidth = 4;
+ 8000c14:	4b1e      	ldr	r3, [pc, #120]	; (8000c90 <MX_FDCAN3_Init+0xc4>)
+ 8000c16:	2204      	movs	r2, #4
+ 8000c18:	629a      	str	r2, [r3, #40]	; 0x28
+  hfdcan3.Init.DataTimeSeg1 = 11;
+ 8000c1a:	4b1d      	ldr	r3, [pc, #116]	; (8000c90 <MX_FDCAN3_Init+0xc4>)
+ 8000c1c:	220b      	movs	r2, #11
+ 8000c1e:	62da      	str	r2, [r3, #44]	; 0x2c
+  hfdcan3.Init.DataTimeSeg2 = 3;
+ 8000c20:	4b1b      	ldr	r3, [pc, #108]	; (8000c90 <MX_FDCAN3_Init+0xc4>)
+ 8000c22:	2203      	movs	r2, #3
+ 8000c24:	631a      	str	r2, [r3, #48]	; 0x30
+  hfdcan3.Init.MessageRAMOffset = 1024;
+ 8000c26:	4b1a      	ldr	r3, [pc, #104]	; (8000c90 <MX_FDCAN3_Init+0xc4>)
+ 8000c28:	f44f 6280 	mov.w	r2, #1024	; 0x400
+ 8000c2c:	635a      	str	r2, [r3, #52]	; 0x34
+  hfdcan3.Init.StdFiltersNbr = 0;
+ 8000c2e:	4b18      	ldr	r3, [pc, #96]	; (8000c90 <MX_FDCAN3_Init+0xc4>)
+ 8000c30:	2200      	movs	r2, #0
+ 8000c32:	639a      	str	r2, [r3, #56]	; 0x38
+  hfdcan3.Init.ExtFiltersNbr = 0;
+ 8000c34:	4b16      	ldr	r3, [pc, #88]	; (8000c90 <MX_FDCAN3_Init+0xc4>)
+ 8000c36:	2200      	movs	r2, #0
+ 8000c38:	63da      	str	r2, [r3, #60]	; 0x3c
+  hfdcan3.Init.RxFifo0ElmtsNbr = 8;
+ 8000c3a:	4b15      	ldr	r3, [pc, #84]	; (8000c90 <MX_FDCAN3_Init+0xc4>)
+ 8000c3c:	2208      	movs	r2, #8
+ 8000c3e:	641a      	str	r2, [r3, #64]	; 0x40
+  hfdcan3.Init.RxFifo0ElmtSize = FDCAN_DATA_BYTES_64;
+ 8000c40:	4b13      	ldr	r3, [pc, #76]	; (8000c90 <MX_FDCAN3_Init+0xc4>)
+ 8000c42:	2212      	movs	r2, #18
+ 8000c44:	645a      	str	r2, [r3, #68]	; 0x44
+  hfdcan3.Init.RxFifo1ElmtsNbr = 0;
+ 8000c46:	4b12      	ldr	r3, [pc, #72]	; (8000c90 <MX_FDCAN3_Init+0xc4>)
+ 8000c48:	2200      	movs	r2, #0
+ 8000c4a:	649a      	str	r2, [r3, #72]	; 0x48
+  hfdcan3.Init.RxFifo1ElmtSize = FDCAN_DATA_BYTES_64;
+ 8000c4c:	4b10      	ldr	r3, [pc, #64]	; (8000c90 <MX_FDCAN3_Init+0xc4>)
+ 8000c4e:	2212      	movs	r2, #18
+ 8000c50:	64da      	str	r2, [r3, #76]	; 0x4c
+  hfdcan3.Init.RxBuffersNbr = 0;
+ 8000c52:	4b0f      	ldr	r3, [pc, #60]	; (8000c90 <MX_FDCAN3_Init+0xc4>)
+ 8000c54:	2200      	movs	r2, #0
+ 8000c56:	651a      	str	r2, [r3, #80]	; 0x50
+  hfdcan3.Init.RxBufferSize = FDCAN_DATA_BYTES_64;
+ 8000c58:	4b0d      	ldr	r3, [pc, #52]	; (8000c90 <MX_FDCAN3_Init+0xc4>)
+ 8000c5a:	2212      	movs	r2, #18
+ 8000c5c:	655a      	str	r2, [r3, #84]	; 0x54
+  hfdcan3.Init.TxEventsNbr = 8;
+ 8000c5e:	4b0c      	ldr	r3, [pc, #48]	; (8000c90 <MX_FDCAN3_Init+0xc4>)
+ 8000c60:	2208      	movs	r2, #8
+ 8000c62:	659a      	str	r2, [r3, #88]	; 0x58
+  hfdcan3.Init.TxBuffersNbr = 0;
+ 8000c64:	4b0a      	ldr	r3, [pc, #40]	; (8000c90 <MX_FDCAN3_Init+0xc4>)
+ 8000c66:	2200      	movs	r2, #0
+ 8000c68:	65da      	str	r2, [r3, #92]	; 0x5c
+  hfdcan3.Init.TxFifoQueueElmtsNbr = 8;
+ 8000c6a:	4b09      	ldr	r3, [pc, #36]	; (8000c90 <MX_FDCAN3_Init+0xc4>)
+ 8000c6c:	2208      	movs	r2, #8
+ 8000c6e:	661a      	str	r2, [r3, #96]	; 0x60
+  hfdcan3.Init.TxFifoQueueMode = FDCAN_TX_FIFO_OPERATION;
+ 8000c70:	4b07      	ldr	r3, [pc, #28]	; (8000c90 <MX_FDCAN3_Init+0xc4>)
+ 8000c72:	2200      	movs	r2, #0
+ 8000c74:	665a      	str	r2, [r3, #100]	; 0x64
+  hfdcan3.Init.TxElmtSize = FDCAN_DATA_BYTES_64;
+ 8000c76:	4b06      	ldr	r3, [pc, #24]	; (8000c90 <MX_FDCAN3_Init+0xc4>)
+ 8000c78:	2212      	movs	r2, #18
+ 8000c7a:	669a      	str	r2, [r3, #104]	; 0x68
+  if (HAL_FDCAN_Init(&hfdcan3) != HAL_OK)
+ 8000c7c:	4804      	ldr	r0, [pc, #16]	; (8000c90 <MX_FDCAN3_Init+0xc4>)
+ 8000c7e:	f004 ff31 	bl	8005ae4 <HAL_FDCAN_Init>
+ 8000c82:	4603      	mov	r3, r0
+ 8000c84:	2b00      	cmp	r3, #0
+ 8000c86:	d001      	beq.n	8000c8c <MX_FDCAN3_Init+0xc0>
+  {
+    Error_Handler();
+ 8000c88:	f000 fc34 	bl	80014f4 <Error_Handler>
+  }
+  /* USER CODE BEGIN FDCAN3_Init 2 */
+
+  /* USER CODE END FDCAN3_Init 2 */
+
+}
+ 8000c8c:	bf00      	nop
+ 8000c8e:	bd80      	pop	{r7, pc}
+ 8000c90:	24000ea8 	.word	0x24000ea8
+ 8000c94:	4000d400 	.word	0x4000d400
+
+08000c98 <MX_SDMMC1_SD_Init>:
+  * @brief SDMMC1 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_SDMMC1_SD_Init(void)
+{
+ 8000c98:	b480      	push	{r7}
+ 8000c9a:	af00      	add	r7, sp, #0
+  /* USER CODE END SDMMC1_Init 0 */
+
+  /* USER CODE BEGIN SDMMC1_Init 1 */
+
+  /* USER CODE END SDMMC1_Init 1 */
+  hsd1.Instance = SDMMC1;
+ 8000c9c:	4b0c      	ldr	r3, [pc, #48]	; (8000cd0 <MX_SDMMC1_SD_Init+0x38>)
+ 8000c9e:	4a0d      	ldr	r2, [pc, #52]	; (8000cd4 <MX_SDMMC1_SD_Init+0x3c>)
+ 8000ca0:	601a      	str	r2, [r3, #0]
+  hsd1.Init.ClockEdge = SDMMC_CLOCK_EDGE_RISING;
+ 8000ca2:	4b0b      	ldr	r3, [pc, #44]	; (8000cd0 <MX_SDMMC1_SD_Init+0x38>)
+ 8000ca4:	2200      	movs	r2, #0
+ 8000ca6:	605a      	str	r2, [r3, #4]
+  hsd1.Init.ClockPowerSave = SDMMC_CLOCK_POWER_SAVE_DISABLE;
+ 8000ca8:	4b09      	ldr	r3, [pc, #36]	; (8000cd0 <MX_SDMMC1_SD_Init+0x38>)
+ 8000caa:	2200      	movs	r2, #0
+ 8000cac:	609a      	str	r2, [r3, #8]
+  hsd1.Init.BusWide = SDMMC_BUS_WIDE_4B;
+ 8000cae:	4b08      	ldr	r3, [pc, #32]	; (8000cd0 <MX_SDMMC1_SD_Init+0x38>)
+ 8000cb0:	f44f 4280 	mov.w	r2, #16384	; 0x4000
+ 8000cb4:	60da      	str	r2, [r3, #12]
+  hsd1.Init.HardwareFlowControl = SDMMC_HARDWARE_FLOW_CONTROL_ENABLE;
+ 8000cb6:	4b06      	ldr	r3, [pc, #24]	; (8000cd0 <MX_SDMMC1_SD_Init+0x38>)
+ 8000cb8:	f44f 3200 	mov.w	r2, #131072	; 0x20000
+ 8000cbc:	611a      	str	r2, [r3, #16]
+  hsd1.Init.ClockDiv = 1;
+ 8000cbe:	4b04      	ldr	r3, [pc, #16]	; (8000cd0 <MX_SDMMC1_SD_Init+0x38>)
+ 8000cc0:	2201      	movs	r2, #1
+ 8000cc2:	615a      	str	r2, [r3, #20]
+  /* USER CODE BEGIN SDMMC1_Init 2 */
+
+  /* USER CODE END SDMMC1_Init 2 */
+
+}
+ 8000cc4:	bf00      	nop
+ 8000cc6:	46bd      	mov	sp, r7
+ 8000cc8:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8000ccc:	4770      	bx	lr
+ 8000cce:	bf00      	nop
+ 8000cd0:	24000f48 	.word	0x24000f48
+ 8000cd4:	52007000 	.word	0x52007000
+
+08000cd8 <MX_TIM3_Init>:
+  * @brief TIM3 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_TIM3_Init(void)
+{
+ 8000cd8:	b580      	push	{r7, lr}
+ 8000cda:	b088      	sub	sp, #32
+ 8000cdc:	af00      	add	r7, sp, #0
+
+  /* USER CODE BEGIN TIM3_Init 0 */
+
+  /* USER CODE END TIM3_Init 0 */
+
+  TIM_ClockConfigTypeDef sClockSourceConfig = {0};
+ 8000cde:	f107 0310 	add.w	r3, r7, #16
+ 8000ce2:	2200      	movs	r2, #0
+ 8000ce4:	601a      	str	r2, [r3, #0]
+ 8000ce6:	605a      	str	r2, [r3, #4]
+ 8000ce8:	609a      	str	r2, [r3, #8]
+ 8000cea:	60da      	str	r2, [r3, #12]
+  TIM_MasterConfigTypeDef sMasterConfig = {0};
+ 8000cec:	1d3b      	adds	r3, r7, #4
+ 8000cee:	2200      	movs	r2, #0
+ 8000cf0:	601a      	str	r2, [r3, #0]
+ 8000cf2:	605a      	str	r2, [r3, #4]
+ 8000cf4:	609a      	str	r2, [r3, #8]
+
+  /* USER CODE BEGIN TIM3_Init 1 */
+
+  /* USER CODE END TIM3_Init 1 */
+  htim3.Instance = TIM3;
+ 8000cf6:	4b1d      	ldr	r3, [pc, #116]	; (8000d6c <MX_TIM3_Init+0x94>)
+ 8000cf8:	4a1d      	ldr	r2, [pc, #116]	; (8000d70 <MX_TIM3_Init+0x98>)
+ 8000cfa:	601a      	str	r2, [r3, #0]
+  htim3.Init.Prescaler = 119;
+ 8000cfc:	4b1b      	ldr	r3, [pc, #108]	; (8000d6c <MX_TIM3_Init+0x94>)
+ 8000cfe:	2277      	movs	r2, #119	; 0x77
+ 8000d00:	605a      	str	r2, [r3, #4]
+  htim3.Init.CounterMode = TIM_COUNTERMODE_UP;
+ 8000d02:	4b1a      	ldr	r3, [pc, #104]	; (8000d6c <MX_TIM3_Init+0x94>)
+ 8000d04:	2200      	movs	r2, #0
+ 8000d06:	609a      	str	r2, [r3, #8]
+  htim3.Init.Period = 65535;
+ 8000d08:	4b18      	ldr	r3, [pc, #96]	; (8000d6c <MX_TIM3_Init+0x94>)
+ 8000d0a:	f64f 72ff 	movw	r2, #65535	; 0xffff
+ 8000d0e:	60da      	str	r2, [r3, #12]
+  htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
+ 8000d10:	4b16      	ldr	r3, [pc, #88]	; (8000d6c <MX_TIM3_Init+0x94>)
+ 8000d12:	2200      	movs	r2, #0
+ 8000d14:	611a      	str	r2, [r3, #16]
+  htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
+ 8000d16:	4b15      	ldr	r3, [pc, #84]	; (8000d6c <MX_TIM3_Init+0x94>)
+ 8000d18:	2200      	movs	r2, #0
+ 8000d1a:	619a      	str	r2, [r3, #24]
+  if (HAL_TIM_Base_Init(&htim3) != HAL_OK)
+ 8000d1c:	4813      	ldr	r0, [pc, #76]	; (8000d6c <MX_TIM3_Init+0x94>)
+ 8000d1e:	f00b f9d7 	bl	800c0d0 <HAL_TIM_Base_Init>
+ 8000d22:	4603      	mov	r3, r0
+ 8000d24:	2b00      	cmp	r3, #0
+ 8000d26:	d001      	beq.n	8000d2c <MX_TIM3_Init+0x54>
+  {
+    Error_Handler();
+ 8000d28:	f000 fbe4 	bl	80014f4 <Error_Handler>
+  }
+  sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
+ 8000d2c:	f44f 5380 	mov.w	r3, #4096	; 0x1000
+ 8000d30:	613b      	str	r3, [r7, #16]
+  if (HAL_TIM_ConfigClockSource(&htim3, &sClockSourceConfig) != HAL_OK)
+ 8000d32:	f107 0310 	add.w	r3, r7, #16
+ 8000d36:	4619      	mov	r1, r3
+ 8000d38:	480c      	ldr	r0, [pc, #48]	; (8000d6c <MX_TIM3_Init+0x94>)
+ 8000d3a:	f00b fbc7 	bl	800c4cc <HAL_TIM_ConfigClockSource>
+ 8000d3e:	4603      	mov	r3, r0
+ 8000d40:	2b00      	cmp	r3, #0
+ 8000d42:	d001      	beq.n	8000d48 <MX_TIM3_Init+0x70>
+  {
+    Error_Handler();
+ 8000d44:	f000 fbd6 	bl	80014f4 <Error_Handler>
+  }
+  sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
+ 8000d48:	2300      	movs	r3, #0
+ 8000d4a:	607b      	str	r3, [r7, #4]
+  sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
+ 8000d4c:	2300      	movs	r3, #0
+ 8000d4e:	60fb      	str	r3, [r7, #12]
+  if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK)
+ 8000d50:	1d3b      	adds	r3, r7, #4
+ 8000d52:	4619      	mov	r1, r3
+ 8000d54:	4805      	ldr	r0, [pc, #20]	; (8000d6c <MX_TIM3_Init+0x94>)
+ 8000d56:	f00b fe1d 	bl	800c994 <HAL_TIMEx_MasterConfigSynchronization>
+ 8000d5a:	4603      	mov	r3, r0
+ 8000d5c:	2b00      	cmp	r3, #0
+ 8000d5e:	d001      	beq.n	8000d64 <MX_TIM3_Init+0x8c>
+  {
+    Error_Handler();
+ 8000d60:	f000 fbc8 	bl	80014f4 <Error_Handler>
+  }
+  /* USER CODE BEGIN TIM3_Init 2 */
+
+  /* USER CODE END TIM3_Init 2 */
+
+}
+ 8000d64:	bf00      	nop
+ 8000d66:	3720      	adds	r7, #32
+ 8000d68:	46bd      	mov	sp, r7
+ 8000d6a:	bd80      	pop	{r7, pc}
+ 8000d6c:	24000fc4 	.word	0x24000fc4
+ 8000d70:	40000400 	.word	0x40000400
+
+08000d74 <MX_UART4_Init>:
+  * @brief UART4 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_UART4_Init(void)
+{
+ 8000d74:	b580      	push	{r7, lr}
+ 8000d76:	af00      	add	r7, sp, #0
+  /* USER CODE END UART4_Init 0 */
+
+  /* USER CODE BEGIN UART4_Init 1 */
+
+  /* USER CODE END UART4_Init 1 */
+  huart4.Instance = UART4;
+ 8000d78:	4b22      	ldr	r3, [pc, #136]	; (8000e04 <MX_UART4_Init+0x90>)
+ 8000d7a:	4a23      	ldr	r2, [pc, #140]	; (8000e08 <MX_UART4_Init+0x94>)
+ 8000d7c:	601a      	str	r2, [r3, #0]
+  huart4.Init.BaudRate = 9600;
+ 8000d7e:	4b21      	ldr	r3, [pc, #132]	; (8000e04 <MX_UART4_Init+0x90>)
+ 8000d80:	f44f 5216 	mov.w	r2, #9600	; 0x2580
+ 8000d84:	605a      	str	r2, [r3, #4]
+  huart4.Init.WordLength = UART_WORDLENGTH_8B;
+ 8000d86:	4b1f      	ldr	r3, [pc, #124]	; (8000e04 <MX_UART4_Init+0x90>)
+ 8000d88:	2200      	movs	r2, #0
+ 8000d8a:	609a      	str	r2, [r3, #8]
+  huart4.Init.StopBits = UART_STOPBITS_1;
+ 8000d8c:	4b1d      	ldr	r3, [pc, #116]	; (8000e04 <MX_UART4_Init+0x90>)
+ 8000d8e:	2200      	movs	r2, #0
+ 8000d90:	60da      	str	r2, [r3, #12]
+  huart4.Init.Parity = UART_PARITY_NONE;
+ 8000d92:	4b1c      	ldr	r3, [pc, #112]	; (8000e04 <MX_UART4_Init+0x90>)
+ 8000d94:	2200      	movs	r2, #0
+ 8000d96:	611a      	str	r2, [r3, #16]
+  huart4.Init.Mode = UART_MODE_TX_RX;
+ 8000d98:	4b1a      	ldr	r3, [pc, #104]	; (8000e04 <MX_UART4_Init+0x90>)
+ 8000d9a:	220c      	movs	r2, #12
+ 8000d9c:	615a      	str	r2, [r3, #20]
+  huart4.Init.HwFlowCtl = UART_HWCONTROL_NONE;
+ 8000d9e:	4b19      	ldr	r3, [pc, #100]	; (8000e04 <MX_UART4_Init+0x90>)
+ 8000da0:	2200      	movs	r2, #0
+ 8000da2:	619a      	str	r2, [r3, #24]
+  huart4.Init.OverSampling = UART_OVERSAMPLING_16;
+ 8000da4:	4b17      	ldr	r3, [pc, #92]	; (8000e04 <MX_UART4_Init+0x90>)
+ 8000da6:	2200      	movs	r2, #0
+ 8000da8:	61da      	str	r2, [r3, #28]
+  huart4.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
+ 8000daa:	4b16      	ldr	r3, [pc, #88]	; (8000e04 <MX_UART4_Init+0x90>)
+ 8000dac:	2200      	movs	r2, #0
+ 8000dae:	621a      	str	r2, [r3, #32]
+  huart4.Init.ClockPrescaler = UART_PRESCALER_DIV1;
+ 8000db0:	4b14      	ldr	r3, [pc, #80]	; (8000e04 <MX_UART4_Init+0x90>)
+ 8000db2:	2200      	movs	r2, #0
+ 8000db4:	625a      	str	r2, [r3, #36]	; 0x24
+  huart4.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
+ 8000db6:	4b13      	ldr	r3, [pc, #76]	; (8000e04 <MX_UART4_Init+0x90>)
+ 8000db8:	2200      	movs	r2, #0
+ 8000dba:	629a      	str	r2, [r3, #40]	; 0x28
+  if (HAL_UART_Init(&huart4) != HAL_OK)
+ 8000dbc:	4811      	ldr	r0, [pc, #68]	; (8000e04 <MX_UART4_Init+0x90>)
+ 8000dbe:	f00b fea3 	bl	800cb08 <HAL_UART_Init>
+ 8000dc2:	4603      	mov	r3, r0
+ 8000dc4:	2b00      	cmp	r3, #0
+ 8000dc6:	d001      	beq.n	8000dcc <MX_UART4_Init+0x58>
+  {
+    Error_Handler();
+ 8000dc8:	f000 fb94 	bl	80014f4 <Error_Handler>
+  }
+  if (HAL_UARTEx_SetTxFifoThreshold(&huart4, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK)
+ 8000dcc:	2100      	movs	r1, #0
+ 8000dce:	480d      	ldr	r0, [pc, #52]	; (8000e04 <MX_UART4_Init+0x90>)
+ 8000dd0:	f00c ffa9 	bl	800dd26 <HAL_UARTEx_SetTxFifoThreshold>
+ 8000dd4:	4603      	mov	r3, r0
+ 8000dd6:	2b00      	cmp	r3, #0
+ 8000dd8:	d001      	beq.n	8000dde <MX_UART4_Init+0x6a>
+  {
+    Error_Handler();
+ 8000dda:	f000 fb8b 	bl	80014f4 <Error_Handler>
+  }
+  if (HAL_UARTEx_SetRxFifoThreshold(&huart4, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK)
+ 8000dde:	2100      	movs	r1, #0
+ 8000de0:	4808      	ldr	r0, [pc, #32]	; (8000e04 <MX_UART4_Init+0x90>)
+ 8000de2:	f00c ffde 	bl	800dda2 <HAL_UARTEx_SetRxFifoThreshold>
+ 8000de6:	4603      	mov	r3, r0
+ 8000de8:	2b00      	cmp	r3, #0
+ 8000dea:	d001      	beq.n	8000df0 <MX_UART4_Init+0x7c>
+  {
+    Error_Handler();
+ 8000dec:	f000 fb82 	bl	80014f4 <Error_Handler>
+  }
+  if (HAL_UARTEx_DisableFifoMode(&huart4) != HAL_OK)
+ 8000df0:	4804      	ldr	r0, [pc, #16]	; (8000e04 <MX_UART4_Init+0x90>)
+ 8000df2:	f00c ff5f 	bl	800dcb4 <HAL_UARTEx_DisableFifoMode>
+ 8000df6:	4603      	mov	r3, r0
+ 8000df8:	2b00      	cmp	r3, #0
+ 8000dfa:	d001      	beq.n	8000e00 <MX_UART4_Init+0x8c>
+  {
+    Error_Handler();
+ 8000dfc:	f000 fb7a 	bl	80014f4 <Error_Handler>
+  }
+  /* USER CODE BEGIN UART4_Init 2 */
+
+  /* USER CODE END UART4_Init 2 */
+
+}
+ 8000e00:	bf00      	nop
+ 8000e02:	bd80      	pop	{r7, pc}
+ 8000e04:	24001010 	.word	0x24001010
+ 8000e08:	40004c00 	.word	0x40004c00
+
+08000e0c <MX_UART7_Init>:
+  * @brief UART7 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_UART7_Init(void)
+{
+ 8000e0c:	b580      	push	{r7, lr}
+ 8000e0e:	af00      	add	r7, sp, #0
+  /* USER CODE END UART7_Init 0 */
+
+  /* USER CODE BEGIN UART7_Init 1 */
+
+  /* USER CODE END UART7_Init 1 */
+  huart7.Instance = UART7;
+ 8000e10:	4b22      	ldr	r3, [pc, #136]	; (8000e9c <MX_UART7_Init+0x90>)
+ 8000e12:	4a23      	ldr	r2, [pc, #140]	; (8000ea0 <MX_UART7_Init+0x94>)
+ 8000e14:	601a      	str	r2, [r3, #0]
+  huart7.Init.BaudRate = 115200;
+ 8000e16:	4b21      	ldr	r3, [pc, #132]	; (8000e9c <MX_UART7_Init+0x90>)
+ 8000e18:	f44f 32e1 	mov.w	r2, #115200	; 0x1c200
+ 8000e1c:	605a      	str	r2, [r3, #4]
+  huart7.Init.WordLength = UART_WORDLENGTH_8B;
+ 8000e1e:	4b1f      	ldr	r3, [pc, #124]	; (8000e9c <MX_UART7_Init+0x90>)
+ 8000e20:	2200      	movs	r2, #0
+ 8000e22:	609a      	str	r2, [r3, #8]
+  huart7.Init.StopBits = UART_STOPBITS_1;
+ 8000e24:	4b1d      	ldr	r3, [pc, #116]	; (8000e9c <MX_UART7_Init+0x90>)
+ 8000e26:	2200      	movs	r2, #0
+ 8000e28:	60da      	str	r2, [r3, #12]
+  huart7.Init.Parity = UART_PARITY_NONE;
+ 8000e2a:	4b1c      	ldr	r3, [pc, #112]	; (8000e9c <MX_UART7_Init+0x90>)
+ 8000e2c:	2200      	movs	r2, #0
+ 8000e2e:	611a      	str	r2, [r3, #16]
+  huart7.Init.Mode = UART_MODE_TX_RX;
+ 8000e30:	4b1a      	ldr	r3, [pc, #104]	; (8000e9c <MX_UART7_Init+0x90>)
+ 8000e32:	220c      	movs	r2, #12
+ 8000e34:	615a      	str	r2, [r3, #20]
+  huart7.Init.HwFlowCtl = UART_HWCONTROL_NONE;
+ 8000e36:	4b19      	ldr	r3, [pc, #100]	; (8000e9c <MX_UART7_Init+0x90>)
+ 8000e38:	2200      	movs	r2, #0
+ 8000e3a:	619a      	str	r2, [r3, #24]
+  huart7.Init.OverSampling = UART_OVERSAMPLING_16;
+ 8000e3c:	4b17      	ldr	r3, [pc, #92]	; (8000e9c <MX_UART7_Init+0x90>)
+ 8000e3e:	2200      	movs	r2, #0
+ 8000e40:	61da      	str	r2, [r3, #28]
+  huart7.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
+ 8000e42:	4b16      	ldr	r3, [pc, #88]	; (8000e9c <MX_UART7_Init+0x90>)
+ 8000e44:	2200      	movs	r2, #0
+ 8000e46:	621a      	str	r2, [r3, #32]
+  huart7.Init.ClockPrescaler = UART_PRESCALER_DIV1;
+ 8000e48:	4b14      	ldr	r3, [pc, #80]	; (8000e9c <MX_UART7_Init+0x90>)
+ 8000e4a:	2200      	movs	r2, #0
+ 8000e4c:	625a      	str	r2, [r3, #36]	; 0x24
+  huart7.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
+ 8000e4e:	4b13      	ldr	r3, [pc, #76]	; (8000e9c <MX_UART7_Init+0x90>)
+ 8000e50:	2200      	movs	r2, #0
+ 8000e52:	629a      	str	r2, [r3, #40]	; 0x28
+  if (HAL_UART_Init(&huart7) != HAL_OK)
+ 8000e54:	4811      	ldr	r0, [pc, #68]	; (8000e9c <MX_UART7_Init+0x90>)
+ 8000e56:	f00b fe57 	bl	800cb08 <HAL_UART_Init>
+ 8000e5a:	4603      	mov	r3, r0
+ 8000e5c:	2b00      	cmp	r3, #0
+ 8000e5e:	d001      	beq.n	8000e64 <MX_UART7_Init+0x58>
+  {
+    Error_Handler();
+ 8000e60:	f000 fb48 	bl	80014f4 <Error_Handler>
+  }
+  if (HAL_UARTEx_SetTxFifoThreshold(&huart7, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK)
+ 8000e64:	2100      	movs	r1, #0
+ 8000e66:	480d      	ldr	r0, [pc, #52]	; (8000e9c <MX_UART7_Init+0x90>)
+ 8000e68:	f00c ff5d 	bl	800dd26 <HAL_UARTEx_SetTxFifoThreshold>
+ 8000e6c:	4603      	mov	r3, r0
+ 8000e6e:	2b00      	cmp	r3, #0
+ 8000e70:	d001      	beq.n	8000e76 <MX_UART7_Init+0x6a>
+  {
+    Error_Handler();
+ 8000e72:	f000 fb3f 	bl	80014f4 <Error_Handler>
+  }
+  if (HAL_UARTEx_SetRxFifoThreshold(&huart7, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK)
+ 8000e76:	2100      	movs	r1, #0
+ 8000e78:	4808      	ldr	r0, [pc, #32]	; (8000e9c <MX_UART7_Init+0x90>)
+ 8000e7a:	f00c ff92 	bl	800dda2 <HAL_UARTEx_SetRxFifoThreshold>
+ 8000e7e:	4603      	mov	r3, r0
+ 8000e80:	2b00      	cmp	r3, #0
+ 8000e82:	d001      	beq.n	8000e88 <MX_UART7_Init+0x7c>
+  {
+    Error_Handler();
+ 8000e84:	f000 fb36 	bl	80014f4 <Error_Handler>
+  }
+  if (HAL_UARTEx_DisableFifoMode(&huart7) != HAL_OK)
+ 8000e88:	4804      	ldr	r0, [pc, #16]	; (8000e9c <MX_UART7_Init+0x90>)
+ 8000e8a:	f00c ff13 	bl	800dcb4 <HAL_UARTEx_DisableFifoMode>
+ 8000e8e:	4603      	mov	r3, r0
+ 8000e90:	2b00      	cmp	r3, #0
+ 8000e92:	d001      	beq.n	8000e98 <MX_UART7_Init+0x8c>
+  {
+    Error_Handler();
+ 8000e94:	f000 fb2e 	bl	80014f4 <Error_Handler>
+  }
+  /* USER CODE BEGIN UART7_Init 2 */
+
+  /* USER CODE END UART7_Init 2 */
+
+}
+ 8000e98:	bf00      	nop
+ 8000e9a:	bd80      	pop	{r7, pc}
+ 8000e9c:	240010a4 	.word	0x240010a4
+ 8000ea0:	40007800 	.word	0x40007800
+
+08000ea4 <MX_UART8_Init>:
+  * @brief UART8 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_UART8_Init(void)
+{
+ 8000ea4:	b580      	push	{r7, lr}
+ 8000ea6:	af00      	add	r7, sp, #0
+  /* USER CODE END UART8_Init 0 */
+
+  /* USER CODE BEGIN UART8_Init 1 */
+
+  /* USER CODE END UART8_Init 1 */
+  huart8.Instance = UART8;
+ 8000ea8:	4b22      	ldr	r3, [pc, #136]	; (8000f34 <MX_UART8_Init+0x90>)
+ 8000eaa:	4a23      	ldr	r2, [pc, #140]	; (8000f38 <MX_UART8_Init+0x94>)
+ 8000eac:	601a      	str	r2, [r3, #0]
+  huart8.Init.BaudRate = 115200;
+ 8000eae:	4b21      	ldr	r3, [pc, #132]	; (8000f34 <MX_UART8_Init+0x90>)
+ 8000eb0:	f44f 32e1 	mov.w	r2, #115200	; 0x1c200
+ 8000eb4:	605a      	str	r2, [r3, #4]
+  huart8.Init.WordLength = UART_WORDLENGTH_8B;
+ 8000eb6:	4b1f      	ldr	r3, [pc, #124]	; (8000f34 <MX_UART8_Init+0x90>)
+ 8000eb8:	2200      	movs	r2, #0
+ 8000eba:	609a      	str	r2, [r3, #8]
+  huart8.Init.StopBits = UART_STOPBITS_1;
+ 8000ebc:	4b1d      	ldr	r3, [pc, #116]	; (8000f34 <MX_UART8_Init+0x90>)
+ 8000ebe:	2200      	movs	r2, #0
+ 8000ec0:	60da      	str	r2, [r3, #12]
+  huart8.Init.Parity = UART_PARITY_NONE;
+ 8000ec2:	4b1c      	ldr	r3, [pc, #112]	; (8000f34 <MX_UART8_Init+0x90>)
+ 8000ec4:	2200      	movs	r2, #0
+ 8000ec6:	611a      	str	r2, [r3, #16]
+  huart8.Init.Mode = UART_MODE_TX_RX;
+ 8000ec8:	4b1a      	ldr	r3, [pc, #104]	; (8000f34 <MX_UART8_Init+0x90>)
+ 8000eca:	220c      	movs	r2, #12
+ 8000ecc:	615a      	str	r2, [r3, #20]
+  huart8.Init.HwFlowCtl = UART_HWCONTROL_NONE;
+ 8000ece:	4b19      	ldr	r3, [pc, #100]	; (8000f34 <MX_UART8_Init+0x90>)
+ 8000ed0:	2200      	movs	r2, #0
+ 8000ed2:	619a      	str	r2, [r3, #24]
+  huart8.Init.OverSampling = UART_OVERSAMPLING_16;
+ 8000ed4:	4b17      	ldr	r3, [pc, #92]	; (8000f34 <MX_UART8_Init+0x90>)
+ 8000ed6:	2200      	movs	r2, #0
+ 8000ed8:	61da      	str	r2, [r3, #28]
+  huart8.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
+ 8000eda:	4b16      	ldr	r3, [pc, #88]	; (8000f34 <MX_UART8_Init+0x90>)
+ 8000edc:	2200      	movs	r2, #0
+ 8000ede:	621a      	str	r2, [r3, #32]
+  huart8.Init.ClockPrescaler = UART_PRESCALER_DIV1;
+ 8000ee0:	4b14      	ldr	r3, [pc, #80]	; (8000f34 <MX_UART8_Init+0x90>)
+ 8000ee2:	2200      	movs	r2, #0
+ 8000ee4:	625a      	str	r2, [r3, #36]	; 0x24
+  huart8.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
+ 8000ee6:	4b13      	ldr	r3, [pc, #76]	; (8000f34 <MX_UART8_Init+0x90>)
+ 8000ee8:	2200      	movs	r2, #0
+ 8000eea:	629a      	str	r2, [r3, #40]	; 0x28
+  if (HAL_UART_Init(&huart8) != HAL_OK)
+ 8000eec:	4811      	ldr	r0, [pc, #68]	; (8000f34 <MX_UART8_Init+0x90>)
+ 8000eee:	f00b fe0b 	bl	800cb08 <HAL_UART_Init>
+ 8000ef2:	4603      	mov	r3, r0
+ 8000ef4:	2b00      	cmp	r3, #0
+ 8000ef6:	d001      	beq.n	8000efc <MX_UART8_Init+0x58>
+  {
+    Error_Handler();
+ 8000ef8:	f000 fafc 	bl	80014f4 <Error_Handler>
+  }
+  if (HAL_UARTEx_SetTxFifoThreshold(&huart8, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK)
+ 8000efc:	2100      	movs	r1, #0
+ 8000efe:	480d      	ldr	r0, [pc, #52]	; (8000f34 <MX_UART8_Init+0x90>)
+ 8000f00:	f00c ff11 	bl	800dd26 <HAL_UARTEx_SetTxFifoThreshold>
+ 8000f04:	4603      	mov	r3, r0
+ 8000f06:	2b00      	cmp	r3, #0
+ 8000f08:	d001      	beq.n	8000f0e <MX_UART8_Init+0x6a>
+  {
+    Error_Handler();
+ 8000f0a:	f000 faf3 	bl	80014f4 <Error_Handler>
+  }
+  if (HAL_UARTEx_SetRxFifoThreshold(&huart8, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK)
+ 8000f0e:	2100      	movs	r1, #0
+ 8000f10:	4808      	ldr	r0, [pc, #32]	; (8000f34 <MX_UART8_Init+0x90>)
+ 8000f12:	f00c ff46 	bl	800dda2 <HAL_UARTEx_SetRxFifoThreshold>
+ 8000f16:	4603      	mov	r3, r0
+ 8000f18:	2b00      	cmp	r3, #0
+ 8000f1a:	d001      	beq.n	8000f20 <MX_UART8_Init+0x7c>
+  {
+    Error_Handler();
+ 8000f1c:	f000 faea 	bl	80014f4 <Error_Handler>
+  }
+  if (HAL_UARTEx_DisableFifoMode(&huart8) != HAL_OK)
+ 8000f20:	4804      	ldr	r0, [pc, #16]	; (8000f34 <MX_UART8_Init+0x90>)
+ 8000f22:	f00c fec7 	bl	800dcb4 <HAL_UARTEx_DisableFifoMode>
+ 8000f26:	4603      	mov	r3, r0
+ 8000f28:	2b00      	cmp	r3, #0
+ 8000f2a:	d001      	beq.n	8000f30 <MX_UART8_Init+0x8c>
+  {
+    Error_Handler();
+ 8000f2c:	f000 fae2 	bl	80014f4 <Error_Handler>
+  }
+  /* USER CODE BEGIN UART8_Init 2 */
+
+  /* USER CODE END UART8_Init 2 */
+
+}
+ 8000f30:	bf00      	nop
+ 8000f32:	bd80      	pop	{r7, pc}
+ 8000f34:	24001138 	.word	0x24001138
+ 8000f38:	40007c00 	.word	0x40007c00
+
+08000f3c <MX_DMA_Init>:
+
+/**
+  * Enable DMA controller clock
+  */
+static void MX_DMA_Init(void)
+{
+ 8000f3c:	b580      	push	{r7, lr}
+ 8000f3e:	b082      	sub	sp, #8
+ 8000f40:	af00      	add	r7, sp, #0
+
+  /* DMA controller clock enable */
+  __HAL_RCC_DMA1_CLK_ENABLE();
+ 8000f42:	4b0d      	ldr	r3, [pc, #52]	; (8000f78 <MX_DMA_Init+0x3c>)
+ 8000f44:	f8d3 30d8 	ldr.w	r3, [r3, #216]	; 0xd8
+ 8000f48:	4a0b      	ldr	r2, [pc, #44]	; (8000f78 <MX_DMA_Init+0x3c>)
+ 8000f4a:	f043 0301 	orr.w	r3, r3, #1
+ 8000f4e:	f8c2 30d8 	str.w	r3, [r2, #216]	; 0xd8
+ 8000f52:	4b09      	ldr	r3, [pc, #36]	; (8000f78 <MX_DMA_Init+0x3c>)
+ 8000f54:	f8d3 30d8 	ldr.w	r3, [r3, #216]	; 0xd8
+ 8000f58:	f003 0301 	and.w	r3, r3, #1
+ 8000f5c:	607b      	str	r3, [r7, #4]
+ 8000f5e:	687b      	ldr	r3, [r7, #4]
+
+  /* DMA interrupt init */
+  /* DMA1_Stream0_IRQn interrupt configuration */
+  HAL_NVIC_SetPriority(DMA1_Stream0_IRQn, 5, 0);
+ 8000f60:	2200      	movs	r2, #0
+ 8000f62:	2105      	movs	r1, #5
+ 8000f64:	200b      	movs	r0, #11
+ 8000f66:	f001 faf9 	bl	800255c <HAL_NVIC_SetPriority>
+  HAL_NVIC_EnableIRQ(DMA1_Stream0_IRQn);
+ 8000f6a:	200b      	movs	r0, #11
+ 8000f6c:	f001 fb10 	bl	8002590 <HAL_NVIC_EnableIRQ>
+
+}
+ 8000f70:	bf00      	nop
+ 8000f72:	3708      	adds	r7, #8
+ 8000f74:	46bd      	mov	sp, r7
+ 8000f76:	bd80      	pop	{r7, pc}
+ 8000f78:	58024400 	.word	0x58024400
+
+08000f7c <MX_MDMA_Init>:
+  * Enable MDMA controller clock
+  * Configure MDMA for global transfers
+  *   hmdma_mdma_channel0_sdmmc1_end_data_0
+  */
+static void MX_MDMA_Init(void)
+{
+ 8000f7c:	b580      	push	{r7, lr}
+ 8000f7e:	b082      	sub	sp, #8
+ 8000f80:	af00      	add	r7, sp, #0
+
+  /* MDMA controller clock enable */
+  __HAL_RCC_MDMA_CLK_ENABLE();
+ 8000f82:	4b2d      	ldr	r3, [pc, #180]	; (8001038 <MX_MDMA_Init+0xbc>)
+ 8000f84:	f8d3 30d4 	ldr.w	r3, [r3, #212]	; 0xd4
+ 8000f88:	4a2b      	ldr	r2, [pc, #172]	; (8001038 <MX_MDMA_Init+0xbc>)
+ 8000f8a:	f043 0301 	orr.w	r3, r3, #1
+ 8000f8e:	f8c2 30d4 	str.w	r3, [r2, #212]	; 0xd4
+ 8000f92:	4b29      	ldr	r3, [pc, #164]	; (8001038 <MX_MDMA_Init+0xbc>)
+ 8000f94:	f8d3 30d4 	ldr.w	r3, [r3, #212]	; 0xd4
+ 8000f98:	f003 0301 	and.w	r3, r3, #1
+ 8000f9c:	607b      	str	r3, [r7, #4]
+ 8000f9e:	687b      	ldr	r3, [r7, #4]
+  /* Local variables */
+
+  /* Configure MDMA channel MDMA_Channel0 */
+  /* Configure MDMA request hmdma_mdma_channel0_sdmmc1_end_data_0 on MDMA_Channel0 */
+  hmdma_mdma_channel0_sdmmc1_end_data_0.Instance = MDMA_Channel0;
+ 8000fa0:	4b26      	ldr	r3, [pc, #152]	; (800103c <MX_MDMA_Init+0xc0>)
+ 8000fa2:	4a27      	ldr	r2, [pc, #156]	; (8001040 <MX_MDMA_Init+0xc4>)
+ 8000fa4:	601a      	str	r2, [r3, #0]
+  hmdma_mdma_channel0_sdmmc1_end_data_0.Init.Request = MDMA_REQUEST_SDMMC1_END_DATA;
+ 8000fa6:	4b25      	ldr	r3, [pc, #148]	; (800103c <MX_MDMA_Init+0xc0>)
+ 8000fa8:	221d      	movs	r2, #29
+ 8000faa:	605a      	str	r2, [r3, #4]
+  hmdma_mdma_channel0_sdmmc1_end_data_0.Init.TransferTriggerMode = MDMA_BUFFER_TRANSFER;
+ 8000fac:	4b23      	ldr	r3, [pc, #140]	; (800103c <MX_MDMA_Init+0xc0>)
+ 8000fae:	2200      	movs	r2, #0
+ 8000fb0:	609a      	str	r2, [r3, #8]
+  hmdma_mdma_channel0_sdmmc1_end_data_0.Init.Priority = MDMA_PRIORITY_LOW;
+ 8000fb2:	4b22      	ldr	r3, [pc, #136]	; (800103c <MX_MDMA_Init+0xc0>)
+ 8000fb4:	2200      	movs	r2, #0
+ 8000fb6:	60da      	str	r2, [r3, #12]
+  hmdma_mdma_channel0_sdmmc1_end_data_0.Init.Endianness = MDMA_LITTLE_ENDIANNESS_PRESERVE;
+ 8000fb8:	4b20      	ldr	r3, [pc, #128]	; (800103c <MX_MDMA_Init+0xc0>)
+ 8000fba:	2200      	movs	r2, #0
+ 8000fbc:	611a      	str	r2, [r3, #16]
+  hmdma_mdma_channel0_sdmmc1_end_data_0.Init.SourceInc = MDMA_SRC_INC_BYTE;
+ 8000fbe:	4b1f      	ldr	r3, [pc, #124]	; (800103c <MX_MDMA_Init+0xc0>)
+ 8000fc0:	2202      	movs	r2, #2
+ 8000fc2:	615a      	str	r2, [r3, #20]
+  hmdma_mdma_channel0_sdmmc1_end_data_0.Init.DestinationInc = MDMA_DEST_INC_BYTE;
+ 8000fc4:	4b1d      	ldr	r3, [pc, #116]	; (800103c <MX_MDMA_Init+0xc0>)
+ 8000fc6:	2208      	movs	r2, #8
+ 8000fc8:	619a      	str	r2, [r3, #24]
+  hmdma_mdma_channel0_sdmmc1_end_data_0.Init.SourceDataSize = MDMA_SRC_DATASIZE_BYTE;
+ 8000fca:	4b1c      	ldr	r3, [pc, #112]	; (800103c <MX_MDMA_Init+0xc0>)
+ 8000fcc:	2200      	movs	r2, #0
+ 8000fce:	61da      	str	r2, [r3, #28]
+  hmdma_mdma_channel0_sdmmc1_end_data_0.Init.DestDataSize = MDMA_DEST_DATASIZE_BYTE;
+ 8000fd0:	4b1a      	ldr	r3, [pc, #104]	; (800103c <MX_MDMA_Init+0xc0>)
+ 8000fd2:	2200      	movs	r2, #0
+ 8000fd4:	621a      	str	r2, [r3, #32]
+  hmdma_mdma_channel0_sdmmc1_end_data_0.Init.DataAlignment = MDMA_DATAALIGN_PACKENABLE;
+ 8000fd6:	4b19      	ldr	r3, [pc, #100]	; (800103c <MX_MDMA_Init+0xc0>)
+ 8000fd8:	f04f 7200 	mov.w	r2, #33554432	; 0x2000000
+ 8000fdc:	625a      	str	r2, [r3, #36]	; 0x24
+  hmdma_mdma_channel0_sdmmc1_end_data_0.Init.BufferTransferLength = 1;
+ 8000fde:	4b17      	ldr	r3, [pc, #92]	; (800103c <MX_MDMA_Init+0xc0>)
+ 8000fe0:	2201      	movs	r2, #1
+ 8000fe2:	629a      	str	r2, [r3, #40]	; 0x28
+  hmdma_mdma_channel0_sdmmc1_end_data_0.Init.SourceBurst = MDMA_SOURCE_BURST_SINGLE;
+ 8000fe4:	4b15      	ldr	r3, [pc, #84]	; (800103c <MX_MDMA_Init+0xc0>)
+ 8000fe6:	2200      	movs	r2, #0
+ 8000fe8:	62da      	str	r2, [r3, #44]	; 0x2c
+  hmdma_mdma_channel0_sdmmc1_end_data_0.Init.DestBurst = MDMA_DEST_BURST_SINGLE;
+ 8000fea:	4b14      	ldr	r3, [pc, #80]	; (800103c <MX_MDMA_Init+0xc0>)
+ 8000fec:	2200      	movs	r2, #0
+ 8000fee:	631a      	str	r2, [r3, #48]	; 0x30
+  hmdma_mdma_channel0_sdmmc1_end_data_0.Init.SourceBlockAddressOffset = 0;
+ 8000ff0:	4b12      	ldr	r3, [pc, #72]	; (800103c <MX_MDMA_Init+0xc0>)
+ 8000ff2:	2200      	movs	r2, #0
+ 8000ff4:	635a      	str	r2, [r3, #52]	; 0x34
+  hmdma_mdma_channel0_sdmmc1_end_data_0.Init.DestBlockAddressOffset = 0;
+ 8000ff6:	4b11      	ldr	r3, [pc, #68]	; (800103c <MX_MDMA_Init+0xc0>)
+ 8000ff8:	2200      	movs	r2, #0
+ 8000ffa:	639a      	str	r2, [r3, #56]	; 0x38
+  if (HAL_MDMA_Init(&hmdma_mdma_channel0_sdmmc1_end_data_0) != HAL_OK)
+ 8000ffc:	480f      	ldr	r0, [pc, #60]	; (800103c <MX_MDMA_Init+0xc0>)
+ 8000ffe:	f005 fdb0 	bl	8006b62 <HAL_MDMA_Init>
+ 8001002:	4603      	mov	r3, r0
+ 8001004:	2b00      	cmp	r3, #0
+ 8001006:	d001      	beq.n	800100c <MX_MDMA_Init+0x90>
+  {
+    Error_Handler();
+ 8001008:	f000 fa74 	bl	80014f4 <Error_Handler>
+  }
+
+  /* Configure post request address and data masks */
+  if (HAL_MDMA_ConfigPostRequestMask(&hmdma_mdma_channel0_sdmmc1_end_data_0, 0, 0) != HAL_OK)
+ 800100c:	2200      	movs	r2, #0
+ 800100e:	2100      	movs	r1, #0
+ 8001010:	480a      	ldr	r0, [pc, #40]	; (800103c <MX_MDMA_Init+0xc0>)
+ 8001012:	f005 fdf2 	bl	8006bfa <HAL_MDMA_ConfigPostRequestMask>
+ 8001016:	4603      	mov	r3, r0
+ 8001018:	2b00      	cmp	r3, #0
+ 800101a:	d001      	beq.n	8001020 <MX_MDMA_Init+0xa4>
+  {
+    Error_Handler();
+ 800101c:	f000 fa6a 	bl	80014f4 <Error_Handler>
+  }
+
+  /* MDMA interrupt initialization */
+  /* MDMA_IRQn interrupt configuration */
+  HAL_NVIC_SetPriority(MDMA_IRQn, 5, 0);
+ 8001020:	2200      	movs	r2, #0
+ 8001022:	2105      	movs	r1, #5
+ 8001024:	207a      	movs	r0, #122	; 0x7a
+ 8001026:	f001 fa99 	bl	800255c <HAL_NVIC_SetPriority>
+  HAL_NVIC_EnableIRQ(MDMA_IRQn);
+ 800102a:	207a      	movs	r0, #122	; 0x7a
+ 800102c:	f001 fab0 	bl	8002590 <HAL_NVIC_EnableIRQ>
+
+}
+ 8001030:	bf00      	nop
+ 8001032:	3708      	adds	r7, #8
+ 8001034:	46bd      	mov	sp, r7
+ 8001036:	bd80      	pop	{r7, pc}
+ 8001038:	58024400 	.word	0x58024400
+ 800103c:	24001244 	.word	0x24001244
+ 8001040:	52000040 	.word	0x52000040
+
+08001044 <MX_GPIO_Init>:
+  * @brief GPIO Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_GPIO_Init(void)
+{
+ 8001044:	b580      	push	{r7, lr}
+ 8001046:	b08c      	sub	sp, #48	; 0x30
+ 8001048:	af00      	add	r7, sp, #0
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+ 800104a:	f107 031c 	add.w	r3, r7, #28
+ 800104e:	2200      	movs	r2, #0
+ 8001050:	601a      	str	r2, [r3, #0]
+ 8001052:	605a      	str	r2, [r3, #4]
+ 8001054:	609a      	str	r2, [r3, #8]
+ 8001056:	60da      	str	r2, [r3, #12]
+ 8001058:	611a      	str	r2, [r3, #16]
+/* USER CODE BEGIN MX_GPIO_Init_1 */
+/* USER CODE END MX_GPIO_Init_1 */
+
+  /* GPIO Ports Clock Enable */
+  __HAL_RCC_GPIOB_CLK_ENABLE();
+ 800105a:	4b51      	ldr	r3, [pc, #324]	; (80011a0 <MX_GPIO_Init+0x15c>)
+ 800105c:	f8d3 30e0 	ldr.w	r3, [r3, #224]	; 0xe0
+ 8001060:	4a4f      	ldr	r2, [pc, #316]	; (80011a0 <MX_GPIO_Init+0x15c>)
+ 8001062:	f043 0302 	orr.w	r3, r3, #2
+ 8001066:	f8c2 30e0 	str.w	r3, [r2, #224]	; 0xe0
+ 800106a:	4b4d      	ldr	r3, [pc, #308]	; (80011a0 <MX_GPIO_Init+0x15c>)
+ 800106c:	f8d3 30e0 	ldr.w	r3, [r3, #224]	; 0xe0
+ 8001070:	f003 0302 	and.w	r3, r3, #2
+ 8001074:	61bb      	str	r3, [r7, #24]
+ 8001076:	69bb      	ldr	r3, [r7, #24]
+  __HAL_RCC_GPIOA_CLK_ENABLE();
+ 8001078:	4b49      	ldr	r3, [pc, #292]	; (80011a0 <MX_GPIO_Init+0x15c>)
+ 800107a:	f8d3 30e0 	ldr.w	r3, [r3, #224]	; 0xe0
+ 800107e:	4a48      	ldr	r2, [pc, #288]	; (80011a0 <MX_GPIO_Init+0x15c>)
+ 8001080:	f043 0301 	orr.w	r3, r3, #1
+ 8001084:	f8c2 30e0 	str.w	r3, [r2, #224]	; 0xe0
+ 8001088:	4b45      	ldr	r3, [pc, #276]	; (80011a0 <MX_GPIO_Init+0x15c>)
+ 800108a:	f8d3 30e0 	ldr.w	r3, [r3, #224]	; 0xe0
+ 800108e:	f003 0301 	and.w	r3, r3, #1
+ 8001092:	617b      	str	r3, [r7, #20]
+ 8001094:	697b      	ldr	r3, [r7, #20]
+  __HAL_RCC_GPIOD_CLK_ENABLE();
+ 8001096:	4b42      	ldr	r3, [pc, #264]	; (80011a0 <MX_GPIO_Init+0x15c>)
+ 8001098:	f8d3 30e0 	ldr.w	r3, [r3, #224]	; 0xe0
+ 800109c:	4a40      	ldr	r2, [pc, #256]	; (80011a0 <MX_GPIO_Init+0x15c>)
+ 800109e:	f043 0308 	orr.w	r3, r3, #8
+ 80010a2:	f8c2 30e0 	str.w	r3, [r2, #224]	; 0xe0
+ 80010a6:	4b3e      	ldr	r3, [pc, #248]	; (80011a0 <MX_GPIO_Init+0x15c>)
+ 80010a8:	f8d3 30e0 	ldr.w	r3, [r3, #224]	; 0xe0
+ 80010ac:	f003 0308 	and.w	r3, r3, #8
+ 80010b0:	613b      	str	r3, [r7, #16]
+ 80010b2:	693b      	ldr	r3, [r7, #16]
+  __HAL_RCC_GPIOC_CLK_ENABLE();
+ 80010b4:	4b3a      	ldr	r3, [pc, #232]	; (80011a0 <MX_GPIO_Init+0x15c>)
+ 80010b6:	f8d3 30e0 	ldr.w	r3, [r3, #224]	; 0xe0
+ 80010ba:	4a39      	ldr	r2, [pc, #228]	; (80011a0 <MX_GPIO_Init+0x15c>)
+ 80010bc:	f043 0304 	orr.w	r3, r3, #4
+ 80010c0:	f8c2 30e0 	str.w	r3, [r2, #224]	; 0xe0
+ 80010c4:	4b36      	ldr	r3, [pc, #216]	; (80011a0 <MX_GPIO_Init+0x15c>)
+ 80010c6:	f8d3 30e0 	ldr.w	r3, [r3, #224]	; 0xe0
+ 80010ca:	f003 0304 	and.w	r3, r3, #4
+ 80010ce:	60fb      	str	r3, [r7, #12]
+ 80010d0:	68fb      	ldr	r3, [r7, #12]
+  __HAL_RCC_GPIOH_CLK_ENABLE();
+ 80010d2:	4b33      	ldr	r3, [pc, #204]	; (80011a0 <MX_GPIO_Init+0x15c>)
+ 80010d4:	f8d3 30e0 	ldr.w	r3, [r3, #224]	; 0xe0
+ 80010d8:	4a31      	ldr	r2, [pc, #196]	; (80011a0 <MX_GPIO_Init+0x15c>)
+ 80010da:	f043 0380 	orr.w	r3, r3, #128	; 0x80
+ 80010de:	f8c2 30e0 	str.w	r3, [r2, #224]	; 0xe0
+ 80010e2:	4b2f      	ldr	r3, [pc, #188]	; (80011a0 <MX_GPIO_Init+0x15c>)
+ 80010e4:	f8d3 30e0 	ldr.w	r3, [r3, #224]	; 0xe0
+ 80010e8:	f003 0380 	and.w	r3, r3, #128	; 0x80
+ 80010ec:	60bb      	str	r3, [r7, #8]
+ 80010ee:	68bb      	ldr	r3, [r7, #8]
+  __HAL_RCC_GPIOE_CLK_ENABLE();
+ 80010f0:	4b2b      	ldr	r3, [pc, #172]	; (80011a0 <MX_GPIO_Init+0x15c>)
+ 80010f2:	f8d3 30e0 	ldr.w	r3, [r3, #224]	; 0xe0
+ 80010f6:	4a2a      	ldr	r2, [pc, #168]	; (80011a0 <MX_GPIO_Init+0x15c>)
+ 80010f8:	f043 0310 	orr.w	r3, r3, #16
+ 80010fc:	f8c2 30e0 	str.w	r3, [r2, #224]	; 0xe0
+ 8001100:	4b27      	ldr	r3, [pc, #156]	; (80011a0 <MX_GPIO_Init+0x15c>)
+ 8001102:	f8d3 30e0 	ldr.w	r3, [r3, #224]	; 0xe0
+ 8001106:	f003 0310 	and.w	r3, r3, #16
+ 800110a:	607b      	str	r3, [r7, #4]
+ 800110c:	687b      	ldr	r3, [r7, #4]
+
+  /*Configure GPIO pin Output Level */
+  HAL_GPIO_WritePin(mLED_GPIO_Port, mLED_Pin, GPIO_PIN_RESET);
+ 800110e:	2200      	movs	r2, #0
+ 8001110:	f44f 4100 	mov.w	r1, #32768	; 0x8000
+ 8001114:	4823      	ldr	r0, [pc, #140]	; (80011a4 <MX_GPIO_Init+0x160>)
+ 8001116:	f005 fd0b 	bl	8006b30 <HAL_GPIO_WritePin>
+
+  /*Configure GPIO pin Output Level */
+  HAL_GPIO_WritePin(GPIOE, SD_LED_Pin|VIN_ON_Pin|PICO_EN_Pin, GPIO_PIN_RESET);
+ 800111a:	2200      	movs	r2, #0
+ 800111c:	f44f 51b0 	mov.w	r1, #5632	; 0x1600
+ 8001120:	4821      	ldr	r0, [pc, #132]	; (80011a8 <MX_GPIO_Init+0x164>)
+ 8001122:	f005 fd05 	bl	8006b30 <HAL_GPIO_WritePin>
+
+  /*Configure GPIO pin : mLED_Pin */
+  GPIO_InitStruct.Pin = mLED_Pin;
+ 8001126:	f44f 4300 	mov.w	r3, #32768	; 0x8000
+ 800112a:	61fb      	str	r3, [r7, #28]
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+ 800112c:	2301      	movs	r3, #1
+ 800112e:	623b      	str	r3, [r7, #32]
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 8001130:	2300      	movs	r3, #0
+ 8001132:	627b      	str	r3, [r7, #36]	; 0x24
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+ 8001134:	2300      	movs	r3, #0
+ 8001136:	62bb      	str	r3, [r7, #40]	; 0x28
+  HAL_GPIO_Init(mLED_GPIO_Port, &GPIO_InitStruct);
+ 8001138:	f107 031c 	add.w	r3, r7, #28
+ 800113c:	4619      	mov	r1, r3
+ 800113e:	4819      	ldr	r0, [pc, #100]	; (80011a4 <MX_GPIO_Init+0x160>)
+ 8001140:	f005 fb36 	bl	80067b0 <HAL_GPIO_Init>
+
+  /*Configure GPIO pins : SD_LED_Pin VIN_ON_Pin PICO_EN_Pin */
+  GPIO_InitStruct.Pin = SD_LED_Pin|VIN_ON_Pin|PICO_EN_Pin;
+ 8001144:	f44f 53b0 	mov.w	r3, #5632	; 0x1600
+ 8001148:	61fb      	str	r3, [r7, #28]
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+ 800114a:	2301      	movs	r3, #1
+ 800114c:	623b      	str	r3, [r7, #32]
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 800114e:	2300      	movs	r3, #0
+ 8001150:	627b      	str	r3, [r7, #36]	; 0x24
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+ 8001152:	2300      	movs	r3, #0
+ 8001154:	62bb      	str	r3, [r7, #40]	; 0x28
+  HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
+ 8001156:	f107 031c 	add.w	r3, r7, #28
+ 800115a:	4619      	mov	r1, r3
+ 800115c:	4812      	ldr	r0, [pc, #72]	; (80011a8 <MX_GPIO_Init+0x164>)
+ 800115e:	f005 fb27 	bl	80067b0 <HAL_GPIO_Init>
+
+  /*Configure GPIO pin : sdDetect_Pin */
+  GPIO_InitStruct.Pin = sdDetect_Pin;
+ 8001162:	f44f 4300 	mov.w	r3, #32768	; 0x8000
+ 8001166:	61fb      	str	r3, [r7, #28]
+  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+ 8001168:	2300      	movs	r3, #0
+ 800116a:	623b      	str	r3, [r7, #32]
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 800116c:	2300      	movs	r3, #0
+ 800116e:	627b      	str	r3, [r7, #36]	; 0x24
+  HAL_GPIO_Init(sdDetect_GPIO_Port, &GPIO_InitStruct);
+ 8001170:	f107 031c 	add.w	r3, r7, #28
+ 8001174:	4619      	mov	r1, r3
+ 8001176:	480d      	ldr	r0, [pc, #52]	; (80011ac <MX_GPIO_Init+0x168>)
+ 8001178:	f005 fb1a 	bl	80067b0 <HAL_GPIO_Init>
+
+  /*Configure GPIO pins : VIN_IG_Pin VIN_1_4_Pin */
+  GPIO_InitStruct.Pin = VIN_IG_Pin|VIN_1_4_Pin;
+ 800117c:	f44f 5320 	mov.w	r3, #10240	; 0x2800
+ 8001180:	61fb      	str	r3, [r7, #28]
+  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+ 8001182:	2300      	movs	r3, #0
+ 8001184:	623b      	str	r3, [r7, #32]
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 8001186:	2300      	movs	r3, #0
+ 8001188:	627b      	str	r3, [r7, #36]	; 0x24
+  HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
+ 800118a:	f107 031c 	add.w	r3, r7, #28
+ 800118e:	4619      	mov	r1, r3
+ 8001190:	4805      	ldr	r0, [pc, #20]	; (80011a8 <MX_GPIO_Init+0x164>)
+ 8001192:	f005 fb0d 	bl	80067b0 <HAL_GPIO_Init>
+
+/* USER CODE BEGIN MX_GPIO_Init_2 */
+/* USER CODE END MX_GPIO_Init_2 */
+}
+ 8001196:	bf00      	nop
+ 8001198:	3730      	adds	r7, #48	; 0x30
+ 800119a:	46bd      	mov	sp, r7
+ 800119c:	bd80      	pop	{r7, pc}
+ 800119e:	bf00      	nop
+ 80011a0:	58024400 	.word	0x58024400
+ 80011a4:	58020000 	.word	0x58020000
+ 80011a8:	58021000 	.word	0x58021000
+ 80011ac:	58020400 	.word	0x58020400
+
+080011b0 <lwftp_init>:
+
+/* USER CODE BEGIN 4 */
+void lwftp_init(void) {
+ 80011b0:	b580      	push	{r7, lr}
+ 80011b2:	b082      	sub	sp, #8
+ 80011b4:	af02      	add	r7, sp, #8
+	IP4_ADDR(&s.cli_ip, CLI_IP[0], CLI_IP[1], CLI_IP[2], CLI_IP[3]);
+ 80011b6:	4b6e      	ldr	r3, [pc, #440]	; (8001370 <lwftp_init+0x1c0>)
+ 80011b8:	781b      	ldrb	r3, [r3, #0]
+ 80011ba:	061a      	lsls	r2, r3, #24
+ 80011bc:	4b6c      	ldr	r3, [pc, #432]	; (8001370 <lwftp_init+0x1c0>)
+ 80011be:	785b      	ldrb	r3, [r3, #1]
+ 80011c0:	041b      	lsls	r3, r3, #16
+ 80011c2:	431a      	orrs	r2, r3
+ 80011c4:	4b6a      	ldr	r3, [pc, #424]	; (8001370 <lwftp_init+0x1c0>)
+ 80011c6:	789b      	ldrb	r3, [r3, #2]
+ 80011c8:	021b      	lsls	r3, r3, #8
+ 80011ca:	4313      	orrs	r3, r2
+ 80011cc:	4a68      	ldr	r2, [pc, #416]	; (8001370 <lwftp_init+0x1c0>)
+ 80011ce:	78d2      	ldrb	r2, [r2, #3]
+ 80011d0:	4313      	orrs	r3, r2
+ 80011d2:	061a      	lsls	r2, r3, #24
+ 80011d4:	4b66      	ldr	r3, [pc, #408]	; (8001370 <lwftp_init+0x1c0>)
+ 80011d6:	781b      	ldrb	r3, [r3, #0]
+ 80011d8:	0619      	lsls	r1, r3, #24
+ 80011da:	4b65      	ldr	r3, [pc, #404]	; (8001370 <lwftp_init+0x1c0>)
+ 80011dc:	785b      	ldrb	r3, [r3, #1]
+ 80011de:	041b      	lsls	r3, r3, #16
+ 80011e0:	4319      	orrs	r1, r3
+ 80011e2:	4b63      	ldr	r3, [pc, #396]	; (8001370 <lwftp_init+0x1c0>)
+ 80011e4:	789b      	ldrb	r3, [r3, #2]
+ 80011e6:	021b      	lsls	r3, r3, #8
+ 80011e8:	430b      	orrs	r3, r1
+ 80011ea:	4961      	ldr	r1, [pc, #388]	; (8001370 <lwftp_init+0x1c0>)
+ 80011ec:	78c9      	ldrb	r1, [r1, #3]
+ 80011ee:	430b      	orrs	r3, r1
+ 80011f0:	021b      	lsls	r3, r3, #8
+ 80011f2:	f403 037f 	and.w	r3, r3, #16711680	; 0xff0000
+ 80011f6:	431a      	orrs	r2, r3
+ 80011f8:	4b5d      	ldr	r3, [pc, #372]	; (8001370 <lwftp_init+0x1c0>)
+ 80011fa:	781b      	ldrb	r3, [r3, #0]
+ 80011fc:	0619      	lsls	r1, r3, #24
+ 80011fe:	4b5c      	ldr	r3, [pc, #368]	; (8001370 <lwftp_init+0x1c0>)
+ 8001200:	785b      	ldrb	r3, [r3, #1]
+ 8001202:	041b      	lsls	r3, r3, #16
+ 8001204:	4319      	orrs	r1, r3
+ 8001206:	4b5a      	ldr	r3, [pc, #360]	; (8001370 <lwftp_init+0x1c0>)
+ 8001208:	789b      	ldrb	r3, [r3, #2]
+ 800120a:	021b      	lsls	r3, r3, #8
+ 800120c:	430b      	orrs	r3, r1
+ 800120e:	4958      	ldr	r1, [pc, #352]	; (8001370 <lwftp_init+0x1c0>)
+ 8001210:	78c9      	ldrb	r1, [r1, #3]
+ 8001212:	430b      	orrs	r3, r1
+ 8001214:	0a1b      	lsrs	r3, r3, #8
+ 8001216:	f403 437f 	and.w	r3, r3, #65280	; 0xff00
+ 800121a:	431a      	orrs	r2, r3
+ 800121c:	4b54      	ldr	r3, [pc, #336]	; (8001370 <lwftp_init+0x1c0>)
+ 800121e:	781b      	ldrb	r3, [r3, #0]
+ 8001220:	0619      	lsls	r1, r3, #24
+ 8001222:	4b53      	ldr	r3, [pc, #332]	; (8001370 <lwftp_init+0x1c0>)
+ 8001224:	785b      	ldrb	r3, [r3, #1]
+ 8001226:	041b      	lsls	r3, r3, #16
+ 8001228:	4319      	orrs	r1, r3
+ 800122a:	4b51      	ldr	r3, [pc, #324]	; (8001370 <lwftp_init+0x1c0>)
+ 800122c:	789b      	ldrb	r3, [r3, #2]
+ 800122e:	021b      	lsls	r3, r3, #8
+ 8001230:	430b      	orrs	r3, r1
+ 8001232:	494f      	ldr	r1, [pc, #316]	; (8001370 <lwftp_init+0x1c0>)
+ 8001234:	78c9      	ldrb	r1, [r1, #3]
+ 8001236:	430b      	orrs	r3, r1
+ 8001238:	0e1b      	lsrs	r3, r3, #24
+ 800123a:	4313      	orrs	r3, r2
+ 800123c:	4a4d      	ldr	r2, [pc, #308]	; (8001374 <lwftp_init+0x1c4>)
+ 800123e:	6013      	str	r3, [r2, #0]
+	IP4_ADDR(&s.svr_ip, SVR_IP[0], SVR_IP[1], SVR_IP[2], SVR_IP[3]);
+ 8001240:	4b4d      	ldr	r3, [pc, #308]	; (8001378 <lwftp_init+0x1c8>)
+ 8001242:	781b      	ldrb	r3, [r3, #0]
+ 8001244:	061a      	lsls	r2, r3, #24
+ 8001246:	4b4c      	ldr	r3, [pc, #304]	; (8001378 <lwftp_init+0x1c8>)
+ 8001248:	785b      	ldrb	r3, [r3, #1]
+ 800124a:	041b      	lsls	r3, r3, #16
+ 800124c:	431a      	orrs	r2, r3
+ 800124e:	4b4a      	ldr	r3, [pc, #296]	; (8001378 <lwftp_init+0x1c8>)
+ 8001250:	789b      	ldrb	r3, [r3, #2]
+ 8001252:	021b      	lsls	r3, r3, #8
+ 8001254:	4313      	orrs	r3, r2
+ 8001256:	4a48      	ldr	r2, [pc, #288]	; (8001378 <lwftp_init+0x1c8>)
+ 8001258:	78d2      	ldrb	r2, [r2, #3]
+ 800125a:	4313      	orrs	r3, r2
+ 800125c:	061a      	lsls	r2, r3, #24
+ 800125e:	4b46      	ldr	r3, [pc, #280]	; (8001378 <lwftp_init+0x1c8>)
+ 8001260:	781b      	ldrb	r3, [r3, #0]
+ 8001262:	0619      	lsls	r1, r3, #24
+ 8001264:	4b44      	ldr	r3, [pc, #272]	; (8001378 <lwftp_init+0x1c8>)
+ 8001266:	785b      	ldrb	r3, [r3, #1]
+ 8001268:	041b      	lsls	r3, r3, #16
+ 800126a:	4319      	orrs	r1, r3
+ 800126c:	4b42      	ldr	r3, [pc, #264]	; (8001378 <lwftp_init+0x1c8>)
+ 800126e:	789b      	ldrb	r3, [r3, #2]
+ 8001270:	021b      	lsls	r3, r3, #8
+ 8001272:	430b      	orrs	r3, r1
+ 8001274:	4940      	ldr	r1, [pc, #256]	; (8001378 <lwftp_init+0x1c8>)
+ 8001276:	78c9      	ldrb	r1, [r1, #3]
+ 8001278:	430b      	orrs	r3, r1
+ 800127a:	021b      	lsls	r3, r3, #8
+ 800127c:	f403 037f 	and.w	r3, r3, #16711680	; 0xff0000
+ 8001280:	431a      	orrs	r2, r3
+ 8001282:	4b3d      	ldr	r3, [pc, #244]	; (8001378 <lwftp_init+0x1c8>)
+ 8001284:	781b      	ldrb	r3, [r3, #0]
+ 8001286:	0619      	lsls	r1, r3, #24
+ 8001288:	4b3b      	ldr	r3, [pc, #236]	; (8001378 <lwftp_init+0x1c8>)
+ 800128a:	785b      	ldrb	r3, [r3, #1]
+ 800128c:	041b      	lsls	r3, r3, #16
+ 800128e:	4319      	orrs	r1, r3
+ 8001290:	4b39      	ldr	r3, [pc, #228]	; (8001378 <lwftp_init+0x1c8>)
+ 8001292:	789b      	ldrb	r3, [r3, #2]
+ 8001294:	021b      	lsls	r3, r3, #8
+ 8001296:	430b      	orrs	r3, r1
+ 8001298:	4937      	ldr	r1, [pc, #220]	; (8001378 <lwftp_init+0x1c8>)
+ 800129a:	78c9      	ldrb	r1, [r1, #3]
+ 800129c:	430b      	orrs	r3, r1
+ 800129e:	0a1b      	lsrs	r3, r3, #8
+ 80012a0:	f403 437f 	and.w	r3, r3, #65280	; 0xff00
+ 80012a4:	431a      	orrs	r2, r3
+ 80012a6:	4b34      	ldr	r3, [pc, #208]	; (8001378 <lwftp_init+0x1c8>)
+ 80012a8:	781b      	ldrb	r3, [r3, #0]
+ 80012aa:	0619      	lsls	r1, r3, #24
+ 80012ac:	4b32      	ldr	r3, [pc, #200]	; (8001378 <lwftp_init+0x1c8>)
+ 80012ae:	785b      	ldrb	r3, [r3, #1]
+ 80012b0:	041b      	lsls	r3, r3, #16
+ 80012b2:	4319      	orrs	r1, r3
+ 80012b4:	4b30      	ldr	r3, [pc, #192]	; (8001378 <lwftp_init+0x1c8>)
+ 80012b6:	789b      	ldrb	r3, [r3, #2]
+ 80012b8:	021b      	lsls	r3, r3, #8
+ 80012ba:	430b      	orrs	r3, r1
+ 80012bc:	492e      	ldr	r1, [pc, #184]	; (8001378 <lwftp_init+0x1c8>)
+ 80012be:	78c9      	ldrb	r1, [r1, #3]
+ 80012c0:	430b      	orrs	r3, r1
+ 80012c2:	0e1b      	lsrs	r3, r3, #24
+ 80012c4:	4313      	orrs	r3, r2
+ 80012c6:	4a2b      	ldr	r2, [pc, #172]	; (8001374 <lwftp_init+0x1c4>)
+ 80012c8:	6053      	str	r3, [r2, #4]
+	s.svr_port = SVR_PORT;
+ 80012ca:	4b2c      	ldr	r3, [pc, #176]	; (800137c <lwftp_init+0x1cc>)
+ 80012cc:	881a      	ldrh	r2, [r3, #0]
+ 80012ce:	4b29      	ldr	r3, [pc, #164]	; (8001374 <lwftp_init+0x1c4>)
+ 80012d0:	811a      	strh	r2, [r3, #8]
+	s.user = USER;
+ 80012d2:	4b2b      	ldr	r3, [pc, #172]	; (8001380 <lwftp_init+0x1d0>)
+ 80012d4:	681b      	ldr	r3, [r3, #0]
+ 80012d6:	4a27      	ldr	r2, [pc, #156]	; (8001374 <lwftp_init+0x1c4>)
+ 80012d8:	60d3      	str	r3, [r2, #12]
+	s.pass = PASS;
+ 80012da:	4b2a      	ldr	r3, [pc, #168]	; (8001384 <lwftp_init+0x1d4>)
+ 80012dc:	681b      	ldr	r3, [r3, #0]
+ 80012de:	4a25      	ldr	r2, [pc, #148]	; (8001374 <lwftp_init+0x1c4>)
+ 80012e0:	6113      	str	r3, [r2, #16]
+
+	printf("\n>> lwftp: cli ip: %d.%d.%d.%d\r\n", CLI_IP[0], CLI_IP[1], CLI_IP[2], CLI_IP[3]);
+ 80012e2:	4b23      	ldr	r3, [pc, #140]	; (8001370 <lwftp_init+0x1c0>)
+ 80012e4:	781b      	ldrb	r3, [r3, #0]
+ 80012e6:	4619      	mov	r1, r3
+ 80012e8:	4b21      	ldr	r3, [pc, #132]	; (8001370 <lwftp_init+0x1c0>)
+ 80012ea:	785b      	ldrb	r3, [r3, #1]
+ 80012ec:	461a      	mov	r2, r3
+ 80012ee:	4b20      	ldr	r3, [pc, #128]	; (8001370 <lwftp_init+0x1c0>)
+ 80012f0:	789b      	ldrb	r3, [r3, #2]
+ 80012f2:	4618      	mov	r0, r3
+ 80012f4:	4b1e      	ldr	r3, [pc, #120]	; (8001370 <lwftp_init+0x1c0>)
+ 80012f6:	78db      	ldrb	r3, [r3, #3]
+ 80012f8:	9300      	str	r3, [sp, #0]
+ 80012fa:	4603      	mov	r3, r0
+ 80012fc:	4822      	ldr	r0, [pc, #136]	; (8001388 <lwftp_init+0x1d8>)
+ 80012fe:	f020 fb43 	bl	8021988 <iprintf>
+	printf(">> lwftp: svr ip: %d.%d.%d.%d\r\n", SVR_IP[0], SVR_IP[1], SVR_IP[2], SVR_IP[3]);
+ 8001302:	4b1d      	ldr	r3, [pc, #116]	; (8001378 <lwftp_init+0x1c8>)
+ 8001304:	781b      	ldrb	r3, [r3, #0]
+ 8001306:	4619      	mov	r1, r3
+ 8001308:	4b1b      	ldr	r3, [pc, #108]	; (8001378 <lwftp_init+0x1c8>)
+ 800130a:	785b      	ldrb	r3, [r3, #1]
+ 800130c:	461a      	mov	r2, r3
+ 800130e:	4b1a      	ldr	r3, [pc, #104]	; (8001378 <lwftp_init+0x1c8>)
+ 8001310:	789b      	ldrb	r3, [r3, #2]
+ 8001312:	4618      	mov	r0, r3
+ 8001314:	4b18      	ldr	r3, [pc, #96]	; (8001378 <lwftp_init+0x1c8>)
+ 8001316:	78db      	ldrb	r3, [r3, #3]
+ 8001318:	9300      	str	r3, [sp, #0]
+ 800131a:	4603      	mov	r3, r0
+ 800131c:	481b      	ldr	r0, [pc, #108]	; (800138c <lwftp_init+0x1dc>)
+ 800131e:	f020 fb33 	bl	8021988 <iprintf>
+	printf(">> lwftp: svr port: %d\r\n", s.svr_port);
+ 8001322:	4b14      	ldr	r3, [pc, #80]	; (8001374 <lwftp_init+0x1c4>)
+ 8001324:	891b      	ldrh	r3, [r3, #8]
+ 8001326:	4619      	mov	r1, r3
+ 8001328:	4819      	ldr	r0, [pc, #100]	; (8001390 <lwftp_init+0x1e0>)
+ 800132a:	f020 fb2d 	bl	8021988 <iprintf>
+	printf(">> lwftp: username: %s\r\n", s.user);
+ 800132e:	4b11      	ldr	r3, [pc, #68]	; (8001374 <lwftp_init+0x1c4>)
+ 8001330:	68db      	ldr	r3, [r3, #12]
+ 8001332:	4619      	mov	r1, r3
+ 8001334:	4817      	ldr	r0, [pc, #92]	; (8001394 <lwftp_init+0x1e4>)
+ 8001336:	f020 fb27 	bl	8021988 <iprintf>
+	printf(">> lwftp: password: %s\r\n\n", s.pass);
+ 800133a:	4b0e      	ldr	r3, [pc, #56]	; (8001374 <lwftp_init+0x1c4>)
+ 800133c:	691b      	ldr	r3, [r3, #16]
+ 800133e:	4619      	mov	r1, r3
+ 8001340:	4815      	ldr	r0, [pc, #84]	; (8001398 <lwftp_init+0x1e8>)
+ 8001342:	f020 fb21 	bl	8021988 <iprintf>
+#if FTPSemaphore
+	sys_sem_new(&ftpsem, 0); // the semaphore would prevent simultaneous access to lwftp_send
+#endif
+
+	/* Thread for Control connection*/
+	sys_thread_new("lwftp_ctrl_thread", lwftp_ctrl_thread, (void*) &s,
+ 8001346:	2300      	movs	r3, #0
+ 8001348:	9300      	str	r3, [sp, #0]
+ 800134a:	f44f 6300 	mov.w	r3, #2048	; 0x800
+ 800134e:	4a09      	ldr	r2, [pc, #36]	; (8001374 <lwftp_init+0x1c4>)
+ 8001350:	4912      	ldr	r1, [pc, #72]	; (800139c <lwftp_init+0x1ec>)
+ 8001352:	4813      	ldr	r0, [pc, #76]	; (80013a0 <lwftp_init+0x1f0>)
+ 8001354:	f020 f958 	bl	8021608 <sys_thread_new>
+	DEFAULT_THREAD_STACKSIZE, osPriorityNormal);
+
+	/* Thread for Data connection*/
+	sys_thread_new("lwftp_data_thread", lwftp_data_thread, (void*) &s,
+ 8001358:	2300      	movs	r3, #0
+ 800135a:	9300      	str	r3, [sp, #0]
+ 800135c:	f44f 6300 	mov.w	r3, #2048	; 0x800
+ 8001360:	4a04      	ldr	r2, [pc, #16]	; (8001374 <lwftp_init+0x1c4>)
+ 8001362:	4910      	ldr	r1, [pc, #64]	; (80013a4 <lwftp_init+0x1f4>)
+ 8001364:	4810      	ldr	r0, [pc, #64]	; (80013a8 <lwftp_init+0x1f8>)
+ 8001366:	f020 f94f 	bl	8021608 <sys_thread_new>
+	DEFAULT_THREAD_STACKSIZE, osPriorityNormal);
+}
+ 800136a:	bf00      	nop
+ 800136c:	46bd      	mov	sp, r7
+ 800136e:	bd80      	pop	{r7, pc}
+ 8001370:	24000000 	.word	0x24000000
+ 8001374:	24007360 	.word	0x24007360
+ 8001378:	24000004 	.word	0x24000004
+ 800137c:	24000008 	.word	0x24000008
+ 8001380:	2400000c 	.word	0x2400000c
+ 8001384:	24000010 	.word	0x24000010
+ 8001388:	08022d34 	.word	0x08022d34
+ 800138c:	08022d58 	.word	0x08022d58
+ 8001390:	08022d78 	.word	0x08022d78
+ 8001394:	08022d94 	.word	0x08022d94
+ 8001398:	08022db0 	.word	0x08022db0
+ 800139c:	0800f251 	.word	0x0800f251
+ 80013a0:	08022dcc 	.word	0x08022dcc
+ 80013a4:	0800f1c9 	.word	0x0800f1c9
+ 80013a8:	08022de0 	.word	0x08022de0
+
+080013ac <StartDefaultTask>:
+ * @param  argument: Not used
+ * @retval None
+ */
+/* USER CODE END Header_StartDefaultTask */
+void StartDefaultTask(void const * argument)
+{
+ 80013ac:	b580      	push	{r7, lr}
+ 80013ae:	b084      	sub	sp, #16
+ 80013b0:	af00      	add	r7, sp, #0
+ 80013b2:	6078      	str	r0, [r7, #4]
+  /* init code for LWIP */
+  MX_LWIP_Init();
+ 80013b4:	f00e f8c4 	bl	800f540 <MX_LWIP_Init>
+  /* USER CODE BEGIN 5 */
+	printf("[INFO] Remaining stack size of task: %ld\r\n",
+ 80013b8:	2000      	movs	r0, #0
+ 80013ba:	f011 f939 	bl	8012630 <uxTaskGetStackHighWaterMark>
+ 80013be:	4603      	mov	r3, r0
+ 80013c0:	4619      	mov	r1, r3
+ 80013c2:	480c      	ldr	r0, [pc, #48]	; (80013f4 <StartDefaultTask+0x48>)
+ 80013c4:	f020 fae0 	bl	8021988 <iprintf>
+			uxTaskGetStackHighWaterMark(NULL));
+	lwftp_init();
+ 80013c8:	f7ff fef2 	bl	80011b0 <lwftp_init>
+
+	osDelay(5000); // run code aft 5s
+ 80013cc:	f241 3088 	movw	r0, #5000	; 0x1388
+ 80013d0:	f00e ffd6 	bl	8010380 <osDelay>
+	err_t err;
+//	err = lwftp_list(&s);
+//	err = lwftp_store(&s, "foobar.txt", "TESTTESTTESTTESTTESTTESTTEST\r\n");
+	err = lwftp_retrieve(&s, "ftp_test_1.txt");
+ 80013d4:	4908      	ldr	r1, [pc, #32]	; (80013f8 <StartDefaultTask+0x4c>)
+ 80013d6:	4809      	ldr	r0, [pc, #36]	; (80013fc <StartDefaultTask+0x50>)
+ 80013d8:	f00d fe9e 	bl	800f118 <lwftp_retrieve>
+ 80013dc:	4603      	mov	r3, r0
+ 80013de:	73fb      	strb	r3, [r7, #15]
+
+	printf("%d\r\n",err);
+ 80013e0:	f997 300f 	ldrsb.w	r3, [r7, #15]
+ 80013e4:	4619      	mov	r1, r3
+ 80013e6:	4806      	ldr	r0, [pc, #24]	; (8001400 <StartDefaultTask+0x54>)
+ 80013e8:	f020 face 	bl	8021988 <iprintf>
+
+	/* Infinite loop */
+	for (;;) {
+		osDelay(1);
+ 80013ec:	2001      	movs	r0, #1
+ 80013ee:	f00e ffc7 	bl	8010380 <osDelay>
+ 80013f2:	e7fb      	b.n	80013ec <StartDefaultTask+0x40>
+ 80013f4:	08022df4 	.word	0x08022df4
+ 80013f8:	08022e20 	.word	0x08022e20
+ 80013fc:	24007360 	.word	0x24007360
+ 8001400:	08022e30 	.word	0x08022e30
+
+08001404 <StartDebugTask>:
+* @param argument: Not used
+* @retval None
+*/
+/* USER CODE END Header_StartDebugTask */
+void StartDebugTask(void const * argument)
+{
+ 8001404:	b580      	push	{r7, lr}
+ 8001406:	b082      	sub	sp, #8
+ 8001408:	af00      	add	r7, sp, #0
+ 800140a:	6078      	str	r0, [r7, #4]
+  /* USER CODE BEGIN StartDebugTask */
+  /* Infinite loop */
+  for(;;)
+  {
+    osDelay(1);
+ 800140c:	2001      	movs	r0, #1
+ 800140e:	f00e ffb7 	bl	8010380 <osDelay>
+ 8001412:	e7fb      	b.n	800140c <StartDebugTask+0x8>
+
+08001414 <MPU_Config>:
+}
+
+/* MPU Configuration */
+
+void MPU_Config(void)
+{
+ 8001414:	b580      	push	{r7, lr}
+ 8001416:	b084      	sub	sp, #16
+ 8001418:	af00      	add	r7, sp, #0
+  MPU_Region_InitTypeDef MPU_InitStruct = {0};
+ 800141a:	463b      	mov	r3, r7
+ 800141c:	2200      	movs	r2, #0
+ 800141e:	601a      	str	r2, [r3, #0]
+ 8001420:	605a      	str	r2, [r3, #4]
+ 8001422:	609a      	str	r2, [r3, #8]
+ 8001424:	60da      	str	r2, [r3, #12]
+
+  /* Disables the MPU */
+  HAL_MPU_Disable();
+ 8001426:	f001 f8c1 	bl	80025ac <HAL_MPU_Disable>
+
+  /** Initializes and configures the Region and the memory to be protected
+  */
+  MPU_InitStruct.Enable = MPU_REGION_ENABLE;
+ 800142a:	2301      	movs	r3, #1
+ 800142c:	703b      	strb	r3, [r7, #0]
+  MPU_InitStruct.Number = MPU_REGION_NUMBER0;
+ 800142e:	2300      	movs	r3, #0
+ 8001430:	707b      	strb	r3, [r7, #1]
+  MPU_InitStruct.BaseAddress = 0x0;
+ 8001432:	2300      	movs	r3, #0
+ 8001434:	607b      	str	r3, [r7, #4]
+  MPU_InitStruct.Size = MPU_REGION_SIZE_4GB;
+ 8001436:	231f      	movs	r3, #31
+ 8001438:	723b      	strb	r3, [r7, #8]
+  MPU_InitStruct.SubRegionDisable = 0x87;
+ 800143a:	2387      	movs	r3, #135	; 0x87
+ 800143c:	727b      	strb	r3, [r7, #9]
+  MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0;
+ 800143e:	2300      	movs	r3, #0
+ 8001440:	72bb      	strb	r3, [r7, #10]
+  MPU_InitStruct.AccessPermission = MPU_REGION_NO_ACCESS;
+ 8001442:	2300      	movs	r3, #0
+ 8001444:	72fb      	strb	r3, [r7, #11]
+  MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_DISABLE;
+ 8001446:	2301      	movs	r3, #1
+ 8001448:	733b      	strb	r3, [r7, #12]
+  MPU_InitStruct.IsShareable = MPU_ACCESS_SHAREABLE;
+ 800144a:	2301      	movs	r3, #1
+ 800144c:	737b      	strb	r3, [r7, #13]
+  MPU_InitStruct.IsCacheable = MPU_ACCESS_NOT_CACHEABLE;
+ 800144e:	2300      	movs	r3, #0
+ 8001450:	73bb      	strb	r3, [r7, #14]
+  MPU_InitStruct.IsBufferable = MPU_ACCESS_NOT_BUFFERABLE;
+ 8001452:	2300      	movs	r3, #0
+ 8001454:	73fb      	strb	r3, [r7, #15]
+
+  HAL_MPU_ConfigRegion(&MPU_InitStruct);
+ 8001456:	463b      	mov	r3, r7
+ 8001458:	4618      	mov	r0, r3
+ 800145a:	f001 f8df 	bl	800261c <HAL_MPU_ConfigRegion>
+
+  /** Initializes and configures the Region and the memory to be protected
+  */
+  MPU_InitStruct.Number = MPU_REGION_NUMBER1;
+ 800145e:	2301      	movs	r3, #1
+ 8001460:	707b      	strb	r3, [r7, #1]
+  MPU_InitStruct.BaseAddress = 0x30000000;
+ 8001462:	f04f 5340 	mov.w	r3, #805306368	; 0x30000000
+ 8001466:	607b      	str	r3, [r7, #4]
+  MPU_InitStruct.Size = MPU_REGION_SIZE_32KB;
+ 8001468:	230e      	movs	r3, #14
+ 800146a:	723b      	strb	r3, [r7, #8]
+  MPU_InitStruct.SubRegionDisable = 0x0;
+ 800146c:	2300      	movs	r3, #0
+ 800146e:	727b      	strb	r3, [r7, #9]
+  MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL1;
+ 8001470:	2301      	movs	r3, #1
+ 8001472:	72bb      	strb	r3, [r7, #10]
+  MPU_InitStruct.AccessPermission = MPU_REGION_FULL_ACCESS;
+ 8001474:	2303      	movs	r3, #3
+ 8001476:	72fb      	strb	r3, [r7, #11]
+  MPU_InitStruct.IsShareable = MPU_ACCESS_NOT_SHAREABLE;
+ 8001478:	2300      	movs	r3, #0
+ 800147a:	737b      	strb	r3, [r7, #13]
+
+  HAL_MPU_ConfigRegion(&MPU_InitStruct);
+ 800147c:	463b      	mov	r3, r7
+ 800147e:	4618      	mov	r0, r3
+ 8001480:	f001 f8cc 	bl	800261c <HAL_MPU_ConfigRegion>
+
+  /** Initializes and configures the Region and the memory to be protected
+  */
+  MPU_InitStruct.Number = MPU_REGION_NUMBER2;
+ 8001484:	2302      	movs	r3, #2
+ 8001486:	707b      	strb	r3, [r7, #1]
+  MPU_InitStruct.Size = MPU_REGION_SIZE_512B;
+ 8001488:	2308      	movs	r3, #8
+ 800148a:	723b      	strb	r3, [r7, #8]
+  MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0;
+ 800148c:	2300      	movs	r3, #0
+ 800148e:	72bb      	strb	r3, [r7, #10]
+  MPU_InitStruct.IsShareable = MPU_ACCESS_SHAREABLE;
+ 8001490:	2301      	movs	r3, #1
+ 8001492:	737b      	strb	r3, [r7, #13]
+  MPU_InitStruct.IsBufferable = MPU_ACCESS_BUFFERABLE;
+ 8001494:	2301      	movs	r3, #1
+ 8001496:	73fb      	strb	r3, [r7, #15]
+
+  HAL_MPU_ConfigRegion(&MPU_InitStruct);
+ 8001498:	463b      	mov	r3, r7
+ 800149a:	4618      	mov	r0, r3
+ 800149c:	f001 f8be 	bl	800261c <HAL_MPU_ConfigRegion>
+
+  /** Initializes and configures the Region and the memory to be protected
+  */
+  MPU_InitStruct.Number = MPU_REGION_NUMBER3;
+ 80014a0:	2303      	movs	r3, #3
+ 80014a2:	707b      	strb	r3, [r7, #1]
+  MPU_InitStruct.BaseAddress = 0x24000000;
+ 80014a4:	f04f 5310 	mov.w	r3, #603979776	; 0x24000000
+ 80014a8:	607b      	str	r3, [r7, #4]
+  MPU_InitStruct.Size = MPU_REGION_SIZE_128KB;
+ 80014aa:	2310      	movs	r3, #16
+ 80014ac:	723b      	strb	r3, [r7, #8]
+  MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL1;
+ 80014ae:	2301      	movs	r3, #1
+ 80014b0:	72bb      	strb	r3, [r7, #10]
+  MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_ENABLE;
+ 80014b2:	2300      	movs	r3, #0
+ 80014b4:	733b      	strb	r3, [r7, #12]
+  MPU_InitStruct.IsBufferable = MPU_ACCESS_NOT_BUFFERABLE;
+ 80014b6:	2300      	movs	r3, #0
+ 80014b8:	73fb      	strb	r3, [r7, #15]
+
+  HAL_MPU_ConfigRegion(&MPU_InitStruct);
+ 80014ba:	463b      	mov	r3, r7
+ 80014bc:	4618      	mov	r0, r3
+ 80014be:	f001 f8ad 	bl	800261c <HAL_MPU_ConfigRegion>
+  /* Enables the MPU */
+  HAL_MPU_Enable(MPU_PRIVILEGED_DEFAULT);
+ 80014c2:	2004      	movs	r0, #4
+ 80014c4:	f001 f88a 	bl	80025dc <HAL_MPU_Enable>
+
+}
+ 80014c8:	bf00      	nop
+ 80014ca:	3710      	adds	r7, #16
+ 80014cc:	46bd      	mov	sp, r7
+ 80014ce:	bd80      	pop	{r7, pc}
+
+080014d0 <HAL_TIM_PeriodElapsedCallback>:
+  * a global variable "uwTick" used as application time base.
+  * @param  htim : TIM handle
+  * @retval None
+  */
+void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
+{
+ 80014d0:	b580      	push	{r7, lr}
+ 80014d2:	b082      	sub	sp, #8
+ 80014d4:	af00      	add	r7, sp, #0
+ 80014d6:	6078      	str	r0, [r7, #4]
+  /* USER CODE BEGIN Callback 0 */
+
+  /* USER CODE END Callback 0 */
+  if (htim->Instance == TIM6) {
+ 80014d8:	687b      	ldr	r3, [r7, #4]
+ 80014da:	681b      	ldr	r3, [r3, #0]
+ 80014dc:	4a04      	ldr	r2, [pc, #16]	; (80014f0 <HAL_TIM_PeriodElapsedCallback+0x20>)
+ 80014de:	4293      	cmp	r3, r2
+ 80014e0:	d101      	bne.n	80014e6 <HAL_TIM_PeriodElapsedCallback+0x16>
+    HAL_IncTick();
+ 80014e2:	f000 ff2b 	bl	800233c <HAL_IncTick>
+  }
+  /* USER CODE BEGIN Callback 1 */
+
+  /* USER CODE END Callback 1 */
+}
+ 80014e6:	bf00      	nop
+ 80014e8:	3708      	adds	r7, #8
+ 80014ea:	46bd      	mov	sp, r7
+ 80014ec:	bd80      	pop	{r7, pc}
+ 80014ee:	bf00      	nop
+ 80014f0:	40001000 	.word	0x40001000
+
+080014f4 <Error_Handler>:
+/**
+  * @brief  This function is executed in case of error occurrence.
+  * @retval None
+  */
+void Error_Handler(void)
+{
+ 80014f4:	b480      	push	{r7}
+ 80014f6:	af00      	add	r7, sp, #0
+  __ASM volatile ("cpsid i" : : : "memory");
+ 80014f8:	b672      	cpsid	i
+}
+ 80014fa:	bf00      	nop
+  /* USER CODE BEGIN Error_Handler_Debug */
+	/* User can add his own implementation to report the HAL error return state */
+	__disable_irq();
+	while (1) {
+ 80014fc:	e7fe      	b.n	80014fc <Error_Handler+0x8>
+	...
+
+08001500 <HAL_MspInit>:
+/* USER CODE END 0 */
+/**
+  * Initializes the Global MSP.
+  */
+void HAL_MspInit(void)
+{
+ 8001500:	b580      	push	{r7, lr}
+ 8001502:	b082      	sub	sp, #8
+ 8001504:	af00      	add	r7, sp, #0
+  /* USER CODE BEGIN MspInit 0 */
+
+  /* USER CODE END MspInit 0 */
+
+  __HAL_RCC_SYSCFG_CLK_ENABLE();
+ 8001506:	4b0c      	ldr	r3, [pc, #48]	; (8001538 <HAL_MspInit+0x38>)
+ 8001508:	f8d3 30f4 	ldr.w	r3, [r3, #244]	; 0xf4
+ 800150c:	4a0a      	ldr	r2, [pc, #40]	; (8001538 <HAL_MspInit+0x38>)
+ 800150e:	f043 0302 	orr.w	r3, r3, #2
+ 8001512:	f8c2 30f4 	str.w	r3, [r2, #244]	; 0xf4
+ 8001516:	4b08      	ldr	r3, [pc, #32]	; (8001538 <HAL_MspInit+0x38>)
+ 8001518:	f8d3 30f4 	ldr.w	r3, [r3, #244]	; 0xf4
+ 800151c:	f003 0302 	and.w	r3, r3, #2
+ 8001520:	607b      	str	r3, [r7, #4]
+ 8001522:	687b      	ldr	r3, [r7, #4]
+
+  /* System interrupt init*/
+  /* PendSV_IRQn interrupt configuration */
+  HAL_NVIC_SetPriority(PendSV_IRQn, 15, 0);
+ 8001524:	2200      	movs	r2, #0
+ 8001526:	210f      	movs	r1, #15
+ 8001528:	f06f 0001 	mvn.w	r0, #1
+ 800152c:	f001 f816 	bl	800255c <HAL_NVIC_SetPriority>
+
+  /* USER CODE BEGIN MspInit 1 */
+
+  /* USER CODE END MspInit 1 */
+}
+ 8001530:	bf00      	nop
+ 8001532:	3708      	adds	r7, #8
+ 8001534:	46bd      	mov	sp, r7
+ 8001536:	bd80      	pop	{r7, pc}
+ 8001538:	58024400 	.word	0x58024400
+
+0800153c <HAL_FDCAN_MspInit>:
+* This function configures the hardware resources used in this example
+* @param hfdcan: FDCAN handle pointer
+* @retval None
+*/
+void HAL_FDCAN_MspInit(FDCAN_HandleTypeDef* hfdcan)
+{
+ 800153c:	b580      	push	{r7, lr}
+ 800153e:	b0bc      	sub	sp, #240	; 0xf0
+ 8001540:	af00      	add	r7, sp, #0
+ 8001542:	6078      	str	r0, [r7, #4]
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+ 8001544:	f107 03dc 	add.w	r3, r7, #220	; 0xdc
+ 8001548:	2200      	movs	r2, #0
+ 800154a:	601a      	str	r2, [r3, #0]
+ 800154c:	605a      	str	r2, [r3, #4]
+ 800154e:	609a      	str	r2, [r3, #8]
+ 8001550:	60da      	str	r2, [r3, #12]
+ 8001552:	611a      	str	r2, [r3, #16]
+  RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
+ 8001554:	f107 0320 	add.w	r3, r7, #32
+ 8001558:	22b8      	movs	r2, #184	; 0xb8
+ 800155a:	2100      	movs	r1, #0
+ 800155c:	4618      	mov	r0, r3
+ 800155e:	f020 fbbf 	bl	8021ce0 <memset>
+  if(hfdcan->Instance==FDCAN1)
+ 8001562:	687b      	ldr	r3, [r7, #4]
+ 8001564:	681b      	ldr	r3, [r3, #0]
+ 8001566:	4a8e      	ldr	r2, [pc, #568]	; (80017a0 <HAL_FDCAN_MspInit+0x264>)
+ 8001568:	4293      	cmp	r3, r2
+ 800156a:	d159      	bne.n	8001620 <HAL_FDCAN_MspInit+0xe4>
+
+  /* USER CODE END FDCAN1_MspInit 0 */
+
+  /** Initializes the peripherals clock
+  */
+    PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_FDCAN;
+ 800156c:	f44f 4200 	mov.w	r2, #32768	; 0x8000
+ 8001570:	f04f 0300 	mov.w	r3, #0
+ 8001574:	e9c7 2308 	strd	r2, r3, [r7, #32]
+    PeriphClkInitStruct.FdcanClockSelection = RCC_FDCANCLKSOURCE_PLL;
+ 8001578:	f04f 5380 	mov.w	r3, #268435456	; 0x10000000
+ 800157c:	f8c7 308c 	str.w	r3, [r7, #140]	; 0x8c
+    if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
+ 8001580:	f107 0320 	add.w	r3, r7, #32
+ 8001584:	4618      	mov	r0, r3
+ 8001586:	f006 fd59 	bl	800803c <HAL_RCCEx_PeriphCLKConfig>
+ 800158a:	4603      	mov	r3, r0
+ 800158c:	2b00      	cmp	r3, #0
+ 800158e:	d001      	beq.n	8001594 <HAL_FDCAN_MspInit+0x58>
+    {
+      Error_Handler();
+ 8001590:	f7ff ffb0 	bl	80014f4 <Error_Handler>
+    }
+
+    /* Peripheral clock enable */
+    HAL_RCC_FDCAN_CLK_ENABLED++;
+ 8001594:	4b83      	ldr	r3, [pc, #524]	; (80017a4 <HAL_FDCAN_MspInit+0x268>)
+ 8001596:	681b      	ldr	r3, [r3, #0]
+ 8001598:	3301      	adds	r3, #1
+ 800159a:	4a82      	ldr	r2, [pc, #520]	; (80017a4 <HAL_FDCAN_MspInit+0x268>)
+ 800159c:	6013      	str	r3, [r2, #0]
+    if(HAL_RCC_FDCAN_CLK_ENABLED==1){
+ 800159e:	4b81      	ldr	r3, [pc, #516]	; (80017a4 <HAL_FDCAN_MspInit+0x268>)
+ 80015a0:	681b      	ldr	r3, [r3, #0]
+ 80015a2:	2b01      	cmp	r3, #1
+ 80015a4:	d10e      	bne.n	80015c4 <HAL_FDCAN_MspInit+0x88>
+      __HAL_RCC_FDCAN_CLK_ENABLE();
+ 80015a6:	4b80      	ldr	r3, [pc, #512]	; (80017a8 <HAL_FDCAN_MspInit+0x26c>)
+ 80015a8:	f8d3 30ec 	ldr.w	r3, [r3, #236]	; 0xec
+ 80015ac:	4a7e      	ldr	r2, [pc, #504]	; (80017a8 <HAL_FDCAN_MspInit+0x26c>)
+ 80015ae:	f443 7380 	orr.w	r3, r3, #256	; 0x100
+ 80015b2:	f8c2 30ec 	str.w	r3, [r2, #236]	; 0xec
+ 80015b6:	4b7c      	ldr	r3, [pc, #496]	; (80017a8 <HAL_FDCAN_MspInit+0x26c>)
+ 80015b8:	f8d3 30ec 	ldr.w	r3, [r3, #236]	; 0xec
+ 80015bc:	f403 7380 	and.w	r3, r3, #256	; 0x100
+ 80015c0:	61fb      	str	r3, [r7, #28]
+ 80015c2:	69fb      	ldr	r3, [r7, #28]
+    }
+
+    __HAL_RCC_GPIOB_CLK_ENABLE();
+ 80015c4:	4b78      	ldr	r3, [pc, #480]	; (80017a8 <HAL_FDCAN_MspInit+0x26c>)
+ 80015c6:	f8d3 30e0 	ldr.w	r3, [r3, #224]	; 0xe0
+ 80015ca:	4a77      	ldr	r2, [pc, #476]	; (80017a8 <HAL_FDCAN_MspInit+0x26c>)
+ 80015cc:	f043 0302 	orr.w	r3, r3, #2
+ 80015d0:	f8c2 30e0 	str.w	r3, [r2, #224]	; 0xe0
+ 80015d4:	4b74      	ldr	r3, [pc, #464]	; (80017a8 <HAL_FDCAN_MspInit+0x26c>)
+ 80015d6:	f8d3 30e0 	ldr.w	r3, [r3, #224]	; 0xe0
+ 80015da:	f003 0302 	and.w	r3, r3, #2
+ 80015de:	61bb      	str	r3, [r7, #24]
+ 80015e0:	69bb      	ldr	r3, [r7, #24]
+    /**FDCAN1 GPIO Configuration
+    PB9     ------> FDCAN1_TX
+    PB8     ------> FDCAN1_RX
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_8;
+ 80015e2:	f44f 7340 	mov.w	r3, #768	; 0x300
+ 80015e6:	f8c7 30dc 	str.w	r3, [r7, #220]	; 0xdc
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ 80015ea:	2302      	movs	r3, #2
+ 80015ec:	f8c7 30e0 	str.w	r3, [r7, #224]	; 0xe0
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 80015f0:	2300      	movs	r3, #0
+ 80015f2:	f8c7 30e4 	str.w	r3, [r7, #228]	; 0xe4
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+ 80015f6:	2300      	movs	r3, #0
+ 80015f8:	f8c7 30e8 	str.w	r3, [r7, #232]	; 0xe8
+    GPIO_InitStruct.Alternate = GPIO_AF9_FDCAN1;
+ 80015fc:	2309      	movs	r3, #9
+ 80015fe:	f8c7 30ec 	str.w	r3, [r7, #236]	; 0xec
+    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+ 8001602:	f107 03dc 	add.w	r3, r7, #220	; 0xdc
+ 8001606:	4619      	mov	r1, r3
+ 8001608:	4868      	ldr	r0, [pc, #416]	; (80017ac <HAL_FDCAN_MspInit+0x270>)
+ 800160a:	f005 f8d1 	bl	80067b0 <HAL_GPIO_Init>
+
+    /* FDCAN1 interrupt Init */
+    HAL_NVIC_SetPriority(FDCAN1_IT0_IRQn, 5, 0);
+ 800160e:	2200      	movs	r2, #0
+ 8001610:	2105      	movs	r1, #5
+ 8001612:	2013      	movs	r0, #19
+ 8001614:	f000 ffa2 	bl	800255c <HAL_NVIC_SetPriority>
+    HAL_NVIC_EnableIRQ(FDCAN1_IT0_IRQn);
+ 8001618:	2013      	movs	r0, #19
+ 800161a:	f000 ffb9 	bl	8002590 <HAL_NVIC_EnableIRQ>
+  /* USER CODE BEGIN FDCAN3_MspInit 1 */
+
+  /* USER CODE END FDCAN3_MspInit 1 */
+  }
+
+}
+ 800161e:	e0bb      	b.n	8001798 <HAL_FDCAN_MspInit+0x25c>
+  else if(hfdcan->Instance==FDCAN2)
+ 8001620:	687b      	ldr	r3, [r7, #4]
+ 8001622:	681b      	ldr	r3, [r3, #0]
+ 8001624:	4a62      	ldr	r2, [pc, #392]	; (80017b0 <HAL_FDCAN_MspInit+0x274>)
+ 8001626:	4293      	cmp	r3, r2
+ 8001628:	d158      	bne.n	80016dc <HAL_FDCAN_MspInit+0x1a0>
+    PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_FDCAN;
+ 800162a:	f44f 4200 	mov.w	r2, #32768	; 0x8000
+ 800162e:	f04f 0300 	mov.w	r3, #0
+ 8001632:	e9c7 2308 	strd	r2, r3, [r7, #32]
+    PeriphClkInitStruct.FdcanClockSelection = RCC_FDCANCLKSOURCE_PLL;
+ 8001636:	f04f 5380 	mov.w	r3, #268435456	; 0x10000000
+ 800163a:	f8c7 308c 	str.w	r3, [r7, #140]	; 0x8c
+    if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
+ 800163e:	f107 0320 	add.w	r3, r7, #32
+ 8001642:	4618      	mov	r0, r3
+ 8001644:	f006 fcfa 	bl	800803c <HAL_RCCEx_PeriphCLKConfig>
+ 8001648:	4603      	mov	r3, r0
+ 800164a:	2b00      	cmp	r3, #0
+ 800164c:	d001      	beq.n	8001652 <HAL_FDCAN_MspInit+0x116>
+      Error_Handler();
+ 800164e:	f7ff ff51 	bl	80014f4 <Error_Handler>
+    HAL_RCC_FDCAN_CLK_ENABLED++;
+ 8001652:	4b54      	ldr	r3, [pc, #336]	; (80017a4 <HAL_FDCAN_MspInit+0x268>)
+ 8001654:	681b      	ldr	r3, [r3, #0]
+ 8001656:	3301      	adds	r3, #1
+ 8001658:	4a52      	ldr	r2, [pc, #328]	; (80017a4 <HAL_FDCAN_MspInit+0x268>)
+ 800165a:	6013      	str	r3, [r2, #0]
+    if(HAL_RCC_FDCAN_CLK_ENABLED==1){
+ 800165c:	4b51      	ldr	r3, [pc, #324]	; (80017a4 <HAL_FDCAN_MspInit+0x268>)
+ 800165e:	681b      	ldr	r3, [r3, #0]
+ 8001660:	2b01      	cmp	r3, #1
+ 8001662:	d10e      	bne.n	8001682 <HAL_FDCAN_MspInit+0x146>
+      __HAL_RCC_FDCAN_CLK_ENABLE();
+ 8001664:	4b50      	ldr	r3, [pc, #320]	; (80017a8 <HAL_FDCAN_MspInit+0x26c>)
+ 8001666:	f8d3 30ec 	ldr.w	r3, [r3, #236]	; 0xec
+ 800166a:	4a4f      	ldr	r2, [pc, #316]	; (80017a8 <HAL_FDCAN_MspInit+0x26c>)
+ 800166c:	f443 7380 	orr.w	r3, r3, #256	; 0x100
+ 8001670:	f8c2 30ec 	str.w	r3, [r2, #236]	; 0xec
+ 8001674:	4b4c      	ldr	r3, [pc, #304]	; (80017a8 <HAL_FDCAN_MspInit+0x26c>)
+ 8001676:	f8d3 30ec 	ldr.w	r3, [r3, #236]	; 0xec
+ 800167a:	f403 7380 	and.w	r3, r3, #256	; 0x100
+ 800167e:	617b      	str	r3, [r7, #20]
+ 8001680:	697b      	ldr	r3, [r7, #20]
+    __HAL_RCC_GPIOB_CLK_ENABLE();
+ 8001682:	4b49      	ldr	r3, [pc, #292]	; (80017a8 <HAL_FDCAN_MspInit+0x26c>)
+ 8001684:	f8d3 30e0 	ldr.w	r3, [r3, #224]	; 0xe0
+ 8001688:	4a47      	ldr	r2, [pc, #284]	; (80017a8 <HAL_FDCAN_MspInit+0x26c>)
+ 800168a:	f043 0302 	orr.w	r3, r3, #2
+ 800168e:	f8c2 30e0 	str.w	r3, [r2, #224]	; 0xe0
+ 8001692:	4b45      	ldr	r3, [pc, #276]	; (80017a8 <HAL_FDCAN_MspInit+0x26c>)
+ 8001694:	f8d3 30e0 	ldr.w	r3, [r3, #224]	; 0xe0
+ 8001698:	f003 0302 	and.w	r3, r3, #2
+ 800169c:	613b      	str	r3, [r7, #16]
+ 800169e:	693b      	ldr	r3, [r7, #16]
+    GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_5;
+ 80016a0:	2360      	movs	r3, #96	; 0x60
+ 80016a2:	f8c7 30dc 	str.w	r3, [r7, #220]	; 0xdc
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ 80016a6:	2302      	movs	r3, #2
+ 80016a8:	f8c7 30e0 	str.w	r3, [r7, #224]	; 0xe0
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 80016ac:	2300      	movs	r3, #0
+ 80016ae:	f8c7 30e4 	str.w	r3, [r7, #228]	; 0xe4
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+ 80016b2:	2300      	movs	r3, #0
+ 80016b4:	f8c7 30e8 	str.w	r3, [r7, #232]	; 0xe8
+    GPIO_InitStruct.Alternate = GPIO_AF9_FDCAN2;
+ 80016b8:	2309      	movs	r3, #9
+ 80016ba:	f8c7 30ec 	str.w	r3, [r7, #236]	; 0xec
+    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+ 80016be:	f107 03dc 	add.w	r3, r7, #220	; 0xdc
+ 80016c2:	4619      	mov	r1, r3
+ 80016c4:	4839      	ldr	r0, [pc, #228]	; (80017ac <HAL_FDCAN_MspInit+0x270>)
+ 80016c6:	f005 f873 	bl	80067b0 <HAL_GPIO_Init>
+    HAL_NVIC_SetPriority(FDCAN2_IT0_IRQn, 5, 0);
+ 80016ca:	2200      	movs	r2, #0
+ 80016cc:	2105      	movs	r1, #5
+ 80016ce:	2014      	movs	r0, #20
+ 80016d0:	f000 ff44 	bl	800255c <HAL_NVIC_SetPriority>
+    HAL_NVIC_EnableIRQ(FDCAN2_IT0_IRQn);
+ 80016d4:	2014      	movs	r0, #20
+ 80016d6:	f000 ff5b 	bl	8002590 <HAL_NVIC_EnableIRQ>
+}
+ 80016da:	e05d      	b.n	8001798 <HAL_FDCAN_MspInit+0x25c>
+  else if(hfdcan->Instance==FDCAN3)
+ 80016dc:	687b      	ldr	r3, [r7, #4]
+ 80016de:	681b      	ldr	r3, [r3, #0]
+ 80016e0:	4a34      	ldr	r2, [pc, #208]	; (80017b4 <HAL_FDCAN_MspInit+0x278>)
+ 80016e2:	4293      	cmp	r3, r2
+ 80016e4:	d158      	bne.n	8001798 <HAL_FDCAN_MspInit+0x25c>
+    PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_FDCAN;
+ 80016e6:	f44f 4200 	mov.w	r2, #32768	; 0x8000
+ 80016ea:	f04f 0300 	mov.w	r3, #0
+ 80016ee:	e9c7 2308 	strd	r2, r3, [r7, #32]
+    PeriphClkInitStruct.FdcanClockSelection = RCC_FDCANCLKSOURCE_PLL;
+ 80016f2:	f04f 5380 	mov.w	r3, #268435456	; 0x10000000
+ 80016f6:	f8c7 308c 	str.w	r3, [r7, #140]	; 0x8c
+    if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
+ 80016fa:	f107 0320 	add.w	r3, r7, #32
+ 80016fe:	4618      	mov	r0, r3
+ 8001700:	f006 fc9c 	bl	800803c <HAL_RCCEx_PeriphCLKConfig>
+ 8001704:	4603      	mov	r3, r0
+ 8001706:	2b00      	cmp	r3, #0
+ 8001708:	d001      	beq.n	800170e <HAL_FDCAN_MspInit+0x1d2>
+      Error_Handler();
+ 800170a:	f7ff fef3 	bl	80014f4 <Error_Handler>
+    HAL_RCC_FDCAN_CLK_ENABLED++;
+ 800170e:	4b25      	ldr	r3, [pc, #148]	; (80017a4 <HAL_FDCAN_MspInit+0x268>)
+ 8001710:	681b      	ldr	r3, [r3, #0]
+ 8001712:	3301      	adds	r3, #1
+ 8001714:	4a23      	ldr	r2, [pc, #140]	; (80017a4 <HAL_FDCAN_MspInit+0x268>)
+ 8001716:	6013      	str	r3, [r2, #0]
+    if(HAL_RCC_FDCAN_CLK_ENABLED==1){
+ 8001718:	4b22      	ldr	r3, [pc, #136]	; (80017a4 <HAL_FDCAN_MspInit+0x268>)
+ 800171a:	681b      	ldr	r3, [r3, #0]
+ 800171c:	2b01      	cmp	r3, #1
+ 800171e:	d10e      	bne.n	800173e <HAL_FDCAN_MspInit+0x202>
+      __HAL_RCC_FDCAN_CLK_ENABLE();
+ 8001720:	4b21      	ldr	r3, [pc, #132]	; (80017a8 <HAL_FDCAN_MspInit+0x26c>)
+ 8001722:	f8d3 30ec 	ldr.w	r3, [r3, #236]	; 0xec
+ 8001726:	4a20      	ldr	r2, [pc, #128]	; (80017a8 <HAL_FDCAN_MspInit+0x26c>)
+ 8001728:	f443 7380 	orr.w	r3, r3, #256	; 0x100
+ 800172c:	f8c2 30ec 	str.w	r3, [r2, #236]	; 0xec
+ 8001730:	4b1d      	ldr	r3, [pc, #116]	; (80017a8 <HAL_FDCAN_MspInit+0x26c>)
+ 8001732:	f8d3 30ec 	ldr.w	r3, [r3, #236]	; 0xec
+ 8001736:	f403 7380 	and.w	r3, r3, #256	; 0x100
+ 800173a:	60fb      	str	r3, [r7, #12]
+ 800173c:	68fb      	ldr	r3, [r7, #12]
+    __HAL_RCC_GPIOD_CLK_ENABLE();
+ 800173e:	4b1a      	ldr	r3, [pc, #104]	; (80017a8 <HAL_FDCAN_MspInit+0x26c>)
+ 8001740:	f8d3 30e0 	ldr.w	r3, [r3, #224]	; 0xe0
+ 8001744:	4a18      	ldr	r2, [pc, #96]	; (80017a8 <HAL_FDCAN_MspInit+0x26c>)
+ 8001746:	f043 0308 	orr.w	r3, r3, #8
+ 800174a:	f8c2 30e0 	str.w	r3, [r2, #224]	; 0xe0
+ 800174e:	4b16      	ldr	r3, [pc, #88]	; (80017a8 <HAL_FDCAN_MspInit+0x26c>)
+ 8001750:	f8d3 30e0 	ldr.w	r3, [r3, #224]	; 0xe0
+ 8001754:	f003 0308 	and.w	r3, r3, #8
+ 8001758:	60bb      	str	r3, [r7, #8]
+ 800175a:	68bb      	ldr	r3, [r7, #8]
+    GPIO_InitStruct.Pin = GPIO_PIN_13|GPIO_PIN_12;
+ 800175c:	f44f 5340 	mov.w	r3, #12288	; 0x3000
+ 8001760:	f8c7 30dc 	str.w	r3, [r7, #220]	; 0xdc
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ 8001764:	2302      	movs	r3, #2
+ 8001766:	f8c7 30e0 	str.w	r3, [r7, #224]	; 0xe0
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 800176a:	2300      	movs	r3, #0
+ 800176c:	f8c7 30e4 	str.w	r3, [r7, #228]	; 0xe4
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+ 8001770:	2300      	movs	r3, #0
+ 8001772:	f8c7 30e8 	str.w	r3, [r7, #232]	; 0xe8
+    GPIO_InitStruct.Alternate = GPIO_AF5_FDCAN3;
+ 8001776:	2305      	movs	r3, #5
+ 8001778:	f8c7 30ec 	str.w	r3, [r7, #236]	; 0xec
+    HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
+ 800177c:	f107 03dc 	add.w	r3, r7, #220	; 0xdc
+ 8001780:	4619      	mov	r1, r3
+ 8001782:	480d      	ldr	r0, [pc, #52]	; (80017b8 <HAL_FDCAN_MspInit+0x27c>)
+ 8001784:	f005 f814 	bl	80067b0 <HAL_GPIO_Init>
+    HAL_NVIC_SetPriority(FDCAN3_IT0_IRQn, 5, 0);
+ 8001788:	2200      	movs	r2, #0
+ 800178a:	2105      	movs	r1, #5
+ 800178c:	209f      	movs	r0, #159	; 0x9f
+ 800178e:	f000 fee5 	bl	800255c <HAL_NVIC_SetPriority>
+    HAL_NVIC_EnableIRQ(FDCAN3_IT0_IRQn);
+ 8001792:	209f      	movs	r0, #159	; 0x9f
+ 8001794:	f000 fefc 	bl	8002590 <HAL_NVIC_EnableIRQ>
+}
+ 8001798:	bf00      	nop
+ 800179a:	37f0      	adds	r7, #240	; 0xf0
+ 800179c:	46bd      	mov	sp, r7
+ 800179e:	bd80      	pop	{r7, pc}
+ 80017a0:	4000a000 	.word	0x4000a000
+ 80017a4:	24007380 	.word	0x24007380
+ 80017a8:	58024400 	.word	0x58024400
+ 80017ac:	58020400 	.word	0x58020400
+ 80017b0:	4000a400 	.word	0x4000a400
+ 80017b4:	4000d400 	.word	0x4000d400
+ 80017b8:	58020c00 	.word	0x58020c00
+
+080017bc <HAL_SD_MspInit>:
+* This function configures the hardware resources used in this example
+* @param hsd: SD handle pointer
+* @retval None
+*/
+void HAL_SD_MspInit(SD_HandleTypeDef* hsd)
+{
+ 80017bc:	b580      	push	{r7, lr}
+ 80017be:	b0ba      	sub	sp, #232	; 0xe8
+ 80017c0:	af00      	add	r7, sp, #0
+ 80017c2:	6078      	str	r0, [r7, #4]
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+ 80017c4:	f107 03d4 	add.w	r3, r7, #212	; 0xd4
+ 80017c8:	2200      	movs	r2, #0
+ 80017ca:	601a      	str	r2, [r3, #0]
+ 80017cc:	605a      	str	r2, [r3, #4]
+ 80017ce:	609a      	str	r2, [r3, #8]
+ 80017d0:	60da      	str	r2, [r3, #12]
+ 80017d2:	611a      	str	r2, [r3, #16]
+  RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
+ 80017d4:	f107 0318 	add.w	r3, r7, #24
+ 80017d8:	22b8      	movs	r2, #184	; 0xb8
+ 80017da:	2100      	movs	r1, #0
+ 80017dc:	4618      	mov	r0, r3
+ 80017de:	f020 fa7f 	bl	8021ce0 <memset>
+  if(hsd->Instance==SDMMC1)
+ 80017e2:	687b      	ldr	r3, [r7, #4]
+ 80017e4:	681b      	ldr	r3, [r3, #0]
+ 80017e6:	4a3c      	ldr	r2, [pc, #240]	; (80018d8 <HAL_SD_MspInit+0x11c>)
+ 80017e8:	4293      	cmp	r3, r2
+ 80017ea:	d171      	bne.n	80018d0 <HAL_SD_MspInit+0x114>
+
+  /* USER CODE END SDMMC1_MspInit 0 */
+
+  /** Initializes the peripherals clock
+  */
+    PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_SDMMC;
+ 80017ec:	f44f 3280 	mov.w	r2, #65536	; 0x10000
+ 80017f0:	f04f 0300 	mov.w	r3, #0
+ 80017f4:	e9c7 2306 	strd	r2, r3, [r7, #24]
+    PeriphClkInitStruct.SdmmcClockSelection = RCC_SDMMCCLKSOURCE_PLL;
+ 80017f8:	2300      	movs	r3, #0
+ 80017fa:	66bb      	str	r3, [r7, #104]	; 0x68
+    if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
+ 80017fc:	f107 0318 	add.w	r3, r7, #24
+ 8001800:	4618      	mov	r0, r3
+ 8001802:	f006 fc1b 	bl	800803c <HAL_RCCEx_PeriphCLKConfig>
+ 8001806:	4603      	mov	r3, r0
+ 8001808:	2b00      	cmp	r3, #0
+ 800180a:	d001      	beq.n	8001810 <HAL_SD_MspInit+0x54>
+    {
+      Error_Handler();
+ 800180c:	f7ff fe72 	bl	80014f4 <Error_Handler>
+    }
+
+    /* Peripheral clock enable */
+    __HAL_RCC_SDMMC1_CLK_ENABLE();
+ 8001810:	4b32      	ldr	r3, [pc, #200]	; (80018dc <HAL_SD_MspInit+0x120>)
+ 8001812:	f8d3 30d4 	ldr.w	r3, [r3, #212]	; 0xd4
+ 8001816:	4a31      	ldr	r2, [pc, #196]	; (80018dc <HAL_SD_MspInit+0x120>)
+ 8001818:	f443 3380 	orr.w	r3, r3, #65536	; 0x10000
+ 800181c:	f8c2 30d4 	str.w	r3, [r2, #212]	; 0xd4
+ 8001820:	4b2e      	ldr	r3, [pc, #184]	; (80018dc <HAL_SD_MspInit+0x120>)
+ 8001822:	f8d3 30d4 	ldr.w	r3, [r3, #212]	; 0xd4
+ 8001826:	f403 3380 	and.w	r3, r3, #65536	; 0x10000
+ 800182a:	617b      	str	r3, [r7, #20]
+ 800182c:	697b      	ldr	r3, [r7, #20]
+
+    __HAL_RCC_GPIOD_CLK_ENABLE();
+ 800182e:	4b2b      	ldr	r3, [pc, #172]	; (80018dc <HAL_SD_MspInit+0x120>)
+ 8001830:	f8d3 30e0 	ldr.w	r3, [r3, #224]	; 0xe0
+ 8001834:	4a29      	ldr	r2, [pc, #164]	; (80018dc <HAL_SD_MspInit+0x120>)
+ 8001836:	f043 0308 	orr.w	r3, r3, #8
+ 800183a:	f8c2 30e0 	str.w	r3, [r2, #224]	; 0xe0
+ 800183e:	4b27      	ldr	r3, [pc, #156]	; (80018dc <HAL_SD_MspInit+0x120>)
+ 8001840:	f8d3 30e0 	ldr.w	r3, [r3, #224]	; 0xe0
+ 8001844:	f003 0308 	and.w	r3, r3, #8
+ 8001848:	613b      	str	r3, [r7, #16]
+ 800184a:	693b      	ldr	r3, [r7, #16]
+    __HAL_RCC_GPIOC_CLK_ENABLE();
+ 800184c:	4b23      	ldr	r3, [pc, #140]	; (80018dc <HAL_SD_MspInit+0x120>)
+ 800184e:	f8d3 30e0 	ldr.w	r3, [r3, #224]	; 0xe0
+ 8001852:	4a22      	ldr	r2, [pc, #136]	; (80018dc <HAL_SD_MspInit+0x120>)
+ 8001854:	f043 0304 	orr.w	r3, r3, #4
+ 8001858:	f8c2 30e0 	str.w	r3, [r2, #224]	; 0xe0
+ 800185c:	4b1f      	ldr	r3, [pc, #124]	; (80018dc <HAL_SD_MspInit+0x120>)
+ 800185e:	f8d3 30e0 	ldr.w	r3, [r3, #224]	; 0xe0
+ 8001862:	f003 0304 	and.w	r3, r3, #4
+ 8001866:	60fb      	str	r3, [r7, #12]
+ 8001868:	68fb      	ldr	r3, [r7, #12]
+    PC10     ------> SDMMC1_D2
+    PC12     ------> SDMMC1_CK
+    PC9     ------> SDMMC1_D1
+    PC8     ------> SDMMC1_D0
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_2;
+ 800186a:	2304      	movs	r3, #4
+ 800186c:	f8c7 30d4 	str.w	r3, [r7, #212]	; 0xd4
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ 8001870:	2302      	movs	r3, #2
+ 8001872:	f8c7 30d8 	str.w	r3, [r7, #216]	; 0xd8
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 8001876:	2300      	movs	r3, #0
+ 8001878:	f8c7 30dc 	str.w	r3, [r7, #220]	; 0xdc
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+ 800187c:	2303      	movs	r3, #3
+ 800187e:	f8c7 30e0 	str.w	r3, [r7, #224]	; 0xe0
+    GPIO_InitStruct.Alternate = GPIO_AF12_SDMMC1;
+ 8001882:	230c      	movs	r3, #12
+ 8001884:	f8c7 30e4 	str.w	r3, [r7, #228]	; 0xe4
+    HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
+ 8001888:	f107 03d4 	add.w	r3, r7, #212	; 0xd4
+ 800188c:	4619      	mov	r1, r3
+ 800188e:	4814      	ldr	r0, [pc, #80]	; (80018e0 <HAL_SD_MspInit+0x124>)
+ 8001890:	f004 ff8e 	bl	80067b0 <HAL_GPIO_Init>
+
+    GPIO_InitStruct.Pin = GPIO_PIN_11|GPIO_PIN_10|GPIO_PIN_12|GPIO_PIN_9
+ 8001894:	f44f 53f8 	mov.w	r3, #7936	; 0x1f00
+ 8001898:	f8c7 30d4 	str.w	r3, [r7, #212]	; 0xd4
+                          |GPIO_PIN_8;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ 800189c:	2302      	movs	r3, #2
+ 800189e:	f8c7 30d8 	str.w	r3, [r7, #216]	; 0xd8
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 80018a2:	2300      	movs	r3, #0
+ 80018a4:	f8c7 30dc 	str.w	r3, [r7, #220]	; 0xdc
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+ 80018a8:	2303      	movs	r3, #3
+ 80018aa:	f8c7 30e0 	str.w	r3, [r7, #224]	; 0xe0
+    GPIO_InitStruct.Alternate = GPIO_AF12_SDMMC1;
+ 80018ae:	230c      	movs	r3, #12
+ 80018b0:	f8c7 30e4 	str.w	r3, [r7, #228]	; 0xe4
+    HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
+ 80018b4:	f107 03d4 	add.w	r3, r7, #212	; 0xd4
+ 80018b8:	4619      	mov	r1, r3
+ 80018ba:	480a      	ldr	r0, [pc, #40]	; (80018e4 <HAL_SD_MspInit+0x128>)
+ 80018bc:	f004 ff78 	bl	80067b0 <HAL_GPIO_Init>
+
+    /* SDMMC1 interrupt Init */
+    HAL_NVIC_SetPriority(SDMMC1_IRQn, 5, 0);
+ 80018c0:	2200      	movs	r2, #0
+ 80018c2:	2105      	movs	r1, #5
+ 80018c4:	2031      	movs	r0, #49	; 0x31
+ 80018c6:	f000 fe49 	bl	800255c <HAL_NVIC_SetPriority>
+    HAL_NVIC_EnableIRQ(SDMMC1_IRQn);
+ 80018ca:	2031      	movs	r0, #49	; 0x31
+ 80018cc:	f000 fe60 	bl	8002590 <HAL_NVIC_EnableIRQ>
+  /* USER CODE BEGIN SDMMC1_MspInit 1 */
+
+  /* USER CODE END SDMMC1_MspInit 1 */
+  }
+
+}
+ 80018d0:	bf00      	nop
+ 80018d2:	37e8      	adds	r7, #232	; 0xe8
+ 80018d4:	46bd      	mov	sp, r7
+ 80018d6:	bd80      	pop	{r7, pc}
+ 80018d8:	52007000 	.word	0x52007000
+ 80018dc:	58024400 	.word	0x58024400
+ 80018e0:	58020c00 	.word	0x58020c00
+ 80018e4:	58020800 	.word	0x58020800
+
+080018e8 <HAL_TIM_Base_MspInit>:
+* This function configures the hardware resources used in this example
+* @param htim_base: TIM_Base handle pointer
+* @retval None
+*/
+void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base)
+{
+ 80018e8:	b480      	push	{r7}
+ 80018ea:	b085      	sub	sp, #20
+ 80018ec:	af00      	add	r7, sp, #0
+ 80018ee:	6078      	str	r0, [r7, #4]
+  if(htim_base->Instance==TIM3)
+ 80018f0:	687b      	ldr	r3, [r7, #4]
+ 80018f2:	681b      	ldr	r3, [r3, #0]
+ 80018f4:	4a0b      	ldr	r2, [pc, #44]	; (8001924 <HAL_TIM_Base_MspInit+0x3c>)
+ 80018f6:	4293      	cmp	r3, r2
+ 80018f8:	d10e      	bne.n	8001918 <HAL_TIM_Base_MspInit+0x30>
+  {
+  /* USER CODE BEGIN TIM3_MspInit 0 */
+
+  /* USER CODE END TIM3_MspInit 0 */
+    /* Peripheral clock enable */
+    __HAL_RCC_TIM3_CLK_ENABLE();
+ 80018fa:	4b0b      	ldr	r3, [pc, #44]	; (8001928 <HAL_TIM_Base_MspInit+0x40>)
+ 80018fc:	f8d3 30e8 	ldr.w	r3, [r3, #232]	; 0xe8
+ 8001900:	4a09      	ldr	r2, [pc, #36]	; (8001928 <HAL_TIM_Base_MspInit+0x40>)
+ 8001902:	f043 0302 	orr.w	r3, r3, #2
+ 8001906:	f8c2 30e8 	str.w	r3, [r2, #232]	; 0xe8
+ 800190a:	4b07      	ldr	r3, [pc, #28]	; (8001928 <HAL_TIM_Base_MspInit+0x40>)
+ 800190c:	f8d3 30e8 	ldr.w	r3, [r3, #232]	; 0xe8
+ 8001910:	f003 0302 	and.w	r3, r3, #2
+ 8001914:	60fb      	str	r3, [r7, #12]
+ 8001916:	68fb      	ldr	r3, [r7, #12]
+  /* USER CODE BEGIN TIM3_MspInit 1 */
+
+  /* USER CODE END TIM3_MspInit 1 */
+  }
+
+}
+ 8001918:	bf00      	nop
+ 800191a:	3714      	adds	r7, #20
+ 800191c:	46bd      	mov	sp, r7
+ 800191e:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8001922:	4770      	bx	lr
+ 8001924:	40000400 	.word	0x40000400
+ 8001928:	58024400 	.word	0x58024400
+
+0800192c <HAL_UART_MspInit>:
+* This function configures the hardware resources used in this example
+* @param huart: UART handle pointer
+* @retval None
+*/
+void HAL_UART_MspInit(UART_HandleTypeDef* huart)
+{
+ 800192c:	b580      	push	{r7, lr}
+ 800192e:	b0bc      	sub	sp, #240	; 0xf0
+ 8001930:	af00      	add	r7, sp, #0
+ 8001932:	6078      	str	r0, [r7, #4]
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+ 8001934:	f107 03dc 	add.w	r3, r7, #220	; 0xdc
+ 8001938:	2200      	movs	r2, #0
+ 800193a:	601a      	str	r2, [r3, #0]
+ 800193c:	605a      	str	r2, [r3, #4]
+ 800193e:	609a      	str	r2, [r3, #8]
+ 8001940:	60da      	str	r2, [r3, #12]
+ 8001942:	611a      	str	r2, [r3, #16]
+  RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
+ 8001944:	f107 0320 	add.w	r3, r7, #32
+ 8001948:	22b8      	movs	r2, #184	; 0xb8
+ 800194a:	2100      	movs	r1, #0
+ 800194c:	4618      	mov	r0, r3
+ 800194e:	f020 f9c7 	bl	8021ce0 <memset>
+  if(huart->Instance==UART4)
+ 8001952:	687b      	ldr	r3, [r7, #4]
+ 8001954:	681b      	ldr	r3, [r3, #0]
+ 8001956:	4a8a      	ldr	r2, [pc, #552]	; (8001b80 <HAL_UART_MspInit+0x254>)
+ 8001958:	4293      	cmp	r3, r2
+ 800195a:	d146      	bne.n	80019ea <HAL_UART_MspInit+0xbe>
+
+  /* USER CODE END UART4_MspInit 0 */
+
+  /** Initializes the peripherals clock
+  */
+    PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_UART4;
+ 800195c:	f04f 0202 	mov.w	r2, #2
+ 8001960:	f04f 0300 	mov.w	r3, #0
+ 8001964:	e9c7 2308 	strd	r2, r3, [r7, #32]
+    PeriphClkInitStruct.Usart234578ClockSelection = RCC_USART234578CLKSOURCE_D2PCLK1;
+ 8001968:	2300      	movs	r3, #0
+ 800196a:	f8c7 3094 	str.w	r3, [r7, #148]	; 0x94
+    if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
+ 800196e:	f107 0320 	add.w	r3, r7, #32
+ 8001972:	4618      	mov	r0, r3
+ 8001974:	f006 fb62 	bl	800803c <HAL_RCCEx_PeriphCLKConfig>
+ 8001978:	4603      	mov	r3, r0
+ 800197a:	2b00      	cmp	r3, #0
+ 800197c:	d001      	beq.n	8001982 <HAL_UART_MspInit+0x56>
+    {
+      Error_Handler();
+ 800197e:	f7ff fdb9 	bl	80014f4 <Error_Handler>
+    }
+
+    /* Peripheral clock enable */
+    __HAL_RCC_UART4_CLK_ENABLE();
+ 8001982:	4b80      	ldr	r3, [pc, #512]	; (8001b84 <HAL_UART_MspInit+0x258>)
+ 8001984:	f8d3 30e8 	ldr.w	r3, [r3, #232]	; 0xe8
+ 8001988:	4a7e      	ldr	r2, [pc, #504]	; (8001b84 <HAL_UART_MspInit+0x258>)
+ 800198a:	f443 2300 	orr.w	r3, r3, #524288	; 0x80000
+ 800198e:	f8c2 30e8 	str.w	r3, [r2, #232]	; 0xe8
+ 8001992:	4b7c      	ldr	r3, [pc, #496]	; (8001b84 <HAL_UART_MspInit+0x258>)
+ 8001994:	f8d3 30e8 	ldr.w	r3, [r3, #232]	; 0xe8
+ 8001998:	f403 2300 	and.w	r3, r3, #524288	; 0x80000
+ 800199c:	61fb      	str	r3, [r7, #28]
+ 800199e:	69fb      	ldr	r3, [r7, #28]
+
+    __HAL_RCC_GPIOD_CLK_ENABLE();
+ 80019a0:	4b78      	ldr	r3, [pc, #480]	; (8001b84 <HAL_UART_MspInit+0x258>)
+ 80019a2:	f8d3 30e0 	ldr.w	r3, [r3, #224]	; 0xe0
+ 80019a6:	4a77      	ldr	r2, [pc, #476]	; (8001b84 <HAL_UART_MspInit+0x258>)
+ 80019a8:	f043 0308 	orr.w	r3, r3, #8
+ 80019ac:	f8c2 30e0 	str.w	r3, [r2, #224]	; 0xe0
+ 80019b0:	4b74      	ldr	r3, [pc, #464]	; (8001b84 <HAL_UART_MspInit+0x258>)
+ 80019b2:	f8d3 30e0 	ldr.w	r3, [r3, #224]	; 0xe0
+ 80019b6:	f003 0308 	and.w	r3, r3, #8
+ 80019ba:	61bb      	str	r3, [r7, #24]
+ 80019bc:	69bb      	ldr	r3, [r7, #24]
+    /**UART4 GPIO Configuration
+    PD0     ------> UART4_RX
+    PD1     ------> UART4_TX
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1;
+ 80019be:	2303      	movs	r3, #3
+ 80019c0:	f8c7 30dc 	str.w	r3, [r7, #220]	; 0xdc
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ 80019c4:	2302      	movs	r3, #2
+ 80019c6:	f8c7 30e0 	str.w	r3, [r7, #224]	; 0xe0
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 80019ca:	2300      	movs	r3, #0
+ 80019cc:	f8c7 30e4 	str.w	r3, [r7, #228]	; 0xe4
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+ 80019d0:	2300      	movs	r3, #0
+ 80019d2:	f8c7 30e8 	str.w	r3, [r7, #232]	; 0xe8
+    GPIO_InitStruct.Alternate = GPIO_AF8_UART4;
+ 80019d6:	2308      	movs	r3, #8
+ 80019d8:	f8c7 30ec 	str.w	r3, [r7, #236]	; 0xec
+    HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
+ 80019dc:	f107 03dc 	add.w	r3, r7, #220	; 0xdc
+ 80019e0:	4619      	mov	r1, r3
+ 80019e2:	4869      	ldr	r0, [pc, #420]	; (8001b88 <HAL_UART_MspInit+0x25c>)
+ 80019e4:	f004 fee4 	bl	80067b0 <HAL_GPIO_Init>
+  /* USER CODE BEGIN UART8_MspInit 1 */
+
+  /* USER CODE END UART8_MspInit 1 */
+  }
+
+}
+ 80019e8:	e0c6      	b.n	8001b78 <HAL_UART_MspInit+0x24c>
+  else if(huart->Instance==UART7)
+ 80019ea:	687b      	ldr	r3, [r7, #4]
+ 80019ec:	681b      	ldr	r3, [r3, #0]
+ 80019ee:	4a67      	ldr	r2, [pc, #412]	; (8001b8c <HAL_UART_MspInit+0x260>)
+ 80019f0:	4293      	cmp	r3, r2
+ 80019f2:	d147      	bne.n	8001a84 <HAL_UART_MspInit+0x158>
+    PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_UART7;
+ 80019f4:	f04f 0202 	mov.w	r2, #2
+ 80019f8:	f04f 0300 	mov.w	r3, #0
+ 80019fc:	e9c7 2308 	strd	r2, r3, [r7, #32]
+    PeriphClkInitStruct.Usart234578ClockSelection = RCC_USART234578CLKSOURCE_D2PCLK1;
+ 8001a00:	2300      	movs	r3, #0
+ 8001a02:	f8c7 3094 	str.w	r3, [r7, #148]	; 0x94
+    if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
+ 8001a06:	f107 0320 	add.w	r3, r7, #32
+ 8001a0a:	4618      	mov	r0, r3
+ 8001a0c:	f006 fb16 	bl	800803c <HAL_RCCEx_PeriphCLKConfig>
+ 8001a10:	4603      	mov	r3, r0
+ 8001a12:	2b00      	cmp	r3, #0
+ 8001a14:	d001      	beq.n	8001a1a <HAL_UART_MspInit+0xee>
+      Error_Handler();
+ 8001a16:	f7ff fd6d 	bl	80014f4 <Error_Handler>
+    __HAL_RCC_UART7_CLK_ENABLE();
+ 8001a1a:	4b5a      	ldr	r3, [pc, #360]	; (8001b84 <HAL_UART_MspInit+0x258>)
+ 8001a1c:	f8d3 30e8 	ldr.w	r3, [r3, #232]	; 0xe8
+ 8001a20:	4a58      	ldr	r2, [pc, #352]	; (8001b84 <HAL_UART_MspInit+0x258>)
+ 8001a22:	f043 4380 	orr.w	r3, r3, #1073741824	; 0x40000000
+ 8001a26:	f8c2 30e8 	str.w	r3, [r2, #232]	; 0xe8
+ 8001a2a:	4b56      	ldr	r3, [pc, #344]	; (8001b84 <HAL_UART_MspInit+0x258>)
+ 8001a2c:	f8d3 30e8 	ldr.w	r3, [r3, #232]	; 0xe8
+ 8001a30:	f003 4380 	and.w	r3, r3, #1073741824	; 0x40000000
+ 8001a34:	617b      	str	r3, [r7, #20]
+ 8001a36:	697b      	ldr	r3, [r7, #20]
+    __HAL_RCC_GPIOE_CLK_ENABLE();
+ 8001a38:	4b52      	ldr	r3, [pc, #328]	; (8001b84 <HAL_UART_MspInit+0x258>)
+ 8001a3a:	f8d3 30e0 	ldr.w	r3, [r3, #224]	; 0xe0
+ 8001a3e:	4a51      	ldr	r2, [pc, #324]	; (8001b84 <HAL_UART_MspInit+0x258>)
+ 8001a40:	f043 0310 	orr.w	r3, r3, #16
+ 8001a44:	f8c2 30e0 	str.w	r3, [r2, #224]	; 0xe0
+ 8001a48:	4b4e      	ldr	r3, [pc, #312]	; (8001b84 <HAL_UART_MspInit+0x258>)
+ 8001a4a:	f8d3 30e0 	ldr.w	r3, [r3, #224]	; 0xe0
+ 8001a4e:	f003 0310 	and.w	r3, r3, #16
+ 8001a52:	613b      	str	r3, [r7, #16]
+ 8001a54:	693b      	ldr	r3, [r7, #16]
+    GPIO_InitStruct.Pin = GPIO_PIN_7|GPIO_PIN_8;
+ 8001a56:	f44f 73c0 	mov.w	r3, #384	; 0x180
+ 8001a5a:	f8c7 30dc 	str.w	r3, [r7, #220]	; 0xdc
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ 8001a5e:	2302      	movs	r3, #2
+ 8001a60:	f8c7 30e0 	str.w	r3, [r7, #224]	; 0xe0
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 8001a64:	2300      	movs	r3, #0
+ 8001a66:	f8c7 30e4 	str.w	r3, [r7, #228]	; 0xe4
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+ 8001a6a:	2300      	movs	r3, #0
+ 8001a6c:	f8c7 30e8 	str.w	r3, [r7, #232]	; 0xe8
+    GPIO_InitStruct.Alternate = GPIO_AF7_UART7;
+ 8001a70:	2307      	movs	r3, #7
+ 8001a72:	f8c7 30ec 	str.w	r3, [r7, #236]	; 0xec
+    HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
+ 8001a76:	f107 03dc 	add.w	r3, r7, #220	; 0xdc
+ 8001a7a:	4619      	mov	r1, r3
+ 8001a7c:	4844      	ldr	r0, [pc, #272]	; (8001b90 <HAL_UART_MspInit+0x264>)
+ 8001a7e:	f004 fe97 	bl	80067b0 <HAL_GPIO_Init>
+}
+ 8001a82:	e079      	b.n	8001b78 <HAL_UART_MspInit+0x24c>
+  else if(huart->Instance==UART8)
+ 8001a84:	687b      	ldr	r3, [r7, #4]
+ 8001a86:	681b      	ldr	r3, [r3, #0]
+ 8001a88:	4a42      	ldr	r2, [pc, #264]	; (8001b94 <HAL_UART_MspInit+0x268>)
+ 8001a8a:	4293      	cmp	r3, r2
+ 8001a8c:	d174      	bne.n	8001b78 <HAL_UART_MspInit+0x24c>
+    PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_UART8;
+ 8001a8e:	f04f 0202 	mov.w	r2, #2
+ 8001a92:	f04f 0300 	mov.w	r3, #0
+ 8001a96:	e9c7 2308 	strd	r2, r3, [r7, #32]
+    PeriphClkInitStruct.Usart234578ClockSelection = RCC_USART234578CLKSOURCE_D2PCLK1;
+ 8001a9a:	2300      	movs	r3, #0
+ 8001a9c:	f8c7 3094 	str.w	r3, [r7, #148]	; 0x94
+    if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
+ 8001aa0:	f107 0320 	add.w	r3, r7, #32
+ 8001aa4:	4618      	mov	r0, r3
+ 8001aa6:	f006 fac9 	bl	800803c <HAL_RCCEx_PeriphCLKConfig>
+ 8001aaa:	4603      	mov	r3, r0
+ 8001aac:	2b00      	cmp	r3, #0
+ 8001aae:	d001      	beq.n	8001ab4 <HAL_UART_MspInit+0x188>
+      Error_Handler();
+ 8001ab0:	f7ff fd20 	bl	80014f4 <Error_Handler>
+    __HAL_RCC_UART8_CLK_ENABLE();
+ 8001ab4:	4b33      	ldr	r3, [pc, #204]	; (8001b84 <HAL_UART_MspInit+0x258>)
+ 8001ab6:	f8d3 30e8 	ldr.w	r3, [r3, #232]	; 0xe8
+ 8001aba:	4a32      	ldr	r2, [pc, #200]	; (8001b84 <HAL_UART_MspInit+0x258>)
+ 8001abc:	f043 4300 	orr.w	r3, r3, #2147483648	; 0x80000000
+ 8001ac0:	f8c2 30e8 	str.w	r3, [r2, #232]	; 0xe8
+ 8001ac4:	4b2f      	ldr	r3, [pc, #188]	; (8001b84 <HAL_UART_MspInit+0x258>)
+ 8001ac6:	f8d3 30e8 	ldr.w	r3, [r3, #232]	; 0xe8
+ 8001aca:	f003 4300 	and.w	r3, r3, #2147483648	; 0x80000000
+ 8001ace:	60fb      	str	r3, [r7, #12]
+ 8001ad0:	68fb      	ldr	r3, [r7, #12]
+    __HAL_RCC_GPIOE_CLK_ENABLE();
+ 8001ad2:	4b2c      	ldr	r3, [pc, #176]	; (8001b84 <HAL_UART_MspInit+0x258>)
+ 8001ad4:	f8d3 30e0 	ldr.w	r3, [r3, #224]	; 0xe0
+ 8001ad8:	4a2a      	ldr	r2, [pc, #168]	; (8001b84 <HAL_UART_MspInit+0x258>)
+ 8001ada:	f043 0310 	orr.w	r3, r3, #16
+ 8001ade:	f8c2 30e0 	str.w	r3, [r2, #224]	; 0xe0
+ 8001ae2:	4b28      	ldr	r3, [pc, #160]	; (8001b84 <HAL_UART_MspInit+0x258>)
+ 8001ae4:	f8d3 30e0 	ldr.w	r3, [r3, #224]	; 0xe0
+ 8001ae8:	f003 0310 	and.w	r3, r3, #16
+ 8001aec:	60bb      	str	r3, [r7, #8]
+ 8001aee:	68bb      	ldr	r3, [r7, #8]
+    GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_0;
+ 8001af0:	2303      	movs	r3, #3
+ 8001af2:	f8c7 30dc 	str.w	r3, [r7, #220]	; 0xdc
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ 8001af6:	2302      	movs	r3, #2
+ 8001af8:	f8c7 30e0 	str.w	r3, [r7, #224]	; 0xe0
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 8001afc:	2300      	movs	r3, #0
+ 8001afe:	f8c7 30e4 	str.w	r3, [r7, #228]	; 0xe4
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+ 8001b02:	2300      	movs	r3, #0
+ 8001b04:	f8c7 30e8 	str.w	r3, [r7, #232]	; 0xe8
+    GPIO_InitStruct.Alternate = GPIO_AF8_UART8;
+ 8001b08:	2308      	movs	r3, #8
+ 8001b0a:	f8c7 30ec 	str.w	r3, [r7, #236]	; 0xec
+    HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
+ 8001b0e:	f107 03dc 	add.w	r3, r7, #220	; 0xdc
+ 8001b12:	4619      	mov	r1, r3
+ 8001b14:	481e      	ldr	r0, [pc, #120]	; (8001b90 <HAL_UART_MspInit+0x264>)
+ 8001b16:	f004 fe4b 	bl	80067b0 <HAL_GPIO_Init>
+    hdma_uart8_rx.Instance = DMA1_Stream0;
+ 8001b1a:	4b1f      	ldr	r3, [pc, #124]	; (8001b98 <HAL_UART_MspInit+0x26c>)
+ 8001b1c:	4a1f      	ldr	r2, [pc, #124]	; (8001b9c <HAL_UART_MspInit+0x270>)
+ 8001b1e:	601a      	str	r2, [r3, #0]
+    hdma_uart8_rx.Init.Request = DMA_REQUEST_UART8_RX;
+ 8001b20:	4b1d      	ldr	r3, [pc, #116]	; (8001b98 <HAL_UART_MspInit+0x26c>)
+ 8001b22:	2251      	movs	r2, #81	; 0x51
+ 8001b24:	605a      	str	r2, [r3, #4]
+    hdma_uart8_rx.Init.Direction = DMA_PERIPH_TO_MEMORY;
+ 8001b26:	4b1c      	ldr	r3, [pc, #112]	; (8001b98 <HAL_UART_MspInit+0x26c>)
+ 8001b28:	2200      	movs	r2, #0
+ 8001b2a:	609a      	str	r2, [r3, #8]
+    hdma_uart8_rx.Init.PeriphInc = DMA_PINC_DISABLE;
+ 8001b2c:	4b1a      	ldr	r3, [pc, #104]	; (8001b98 <HAL_UART_MspInit+0x26c>)
+ 8001b2e:	2200      	movs	r2, #0
+ 8001b30:	60da      	str	r2, [r3, #12]
+    hdma_uart8_rx.Init.MemInc = DMA_MINC_ENABLE;
+ 8001b32:	4b19      	ldr	r3, [pc, #100]	; (8001b98 <HAL_UART_MspInit+0x26c>)
+ 8001b34:	f44f 6280 	mov.w	r2, #1024	; 0x400
+ 8001b38:	611a      	str	r2, [r3, #16]
+    hdma_uart8_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
+ 8001b3a:	4b17      	ldr	r3, [pc, #92]	; (8001b98 <HAL_UART_MspInit+0x26c>)
+ 8001b3c:	2200      	movs	r2, #0
+ 8001b3e:	615a      	str	r2, [r3, #20]
+    hdma_uart8_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
+ 8001b40:	4b15      	ldr	r3, [pc, #84]	; (8001b98 <HAL_UART_MspInit+0x26c>)
+ 8001b42:	2200      	movs	r2, #0
+ 8001b44:	619a      	str	r2, [r3, #24]
+    hdma_uart8_rx.Init.Mode = DMA_CIRCULAR;
+ 8001b46:	4b14      	ldr	r3, [pc, #80]	; (8001b98 <HAL_UART_MspInit+0x26c>)
+ 8001b48:	f44f 7280 	mov.w	r2, #256	; 0x100
+ 8001b4c:	61da      	str	r2, [r3, #28]
+    hdma_uart8_rx.Init.Priority = DMA_PRIORITY_LOW;
+ 8001b4e:	4b12      	ldr	r3, [pc, #72]	; (8001b98 <HAL_UART_MspInit+0x26c>)
+ 8001b50:	2200      	movs	r2, #0
+ 8001b52:	621a      	str	r2, [r3, #32]
+    hdma_uart8_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
+ 8001b54:	4b10      	ldr	r3, [pc, #64]	; (8001b98 <HAL_UART_MspInit+0x26c>)
+ 8001b56:	2200      	movs	r2, #0
+ 8001b58:	625a      	str	r2, [r3, #36]	; 0x24
+    if (HAL_DMA_Init(&hdma_uart8_rx) != HAL_OK)
+ 8001b5a:	480f      	ldr	r0, [pc, #60]	; (8001b98 <HAL_UART_MspInit+0x26c>)
+ 8001b5c:	f000 fda2 	bl	80026a4 <HAL_DMA_Init>
+ 8001b60:	4603      	mov	r3, r0
+ 8001b62:	2b00      	cmp	r3, #0
+ 8001b64:	d001      	beq.n	8001b6a <HAL_UART_MspInit+0x23e>
+      Error_Handler();
+ 8001b66:	f7ff fcc5 	bl	80014f4 <Error_Handler>
+    __HAL_LINKDMA(huart,hdmarx,hdma_uart8_rx);
+ 8001b6a:	687b      	ldr	r3, [r7, #4]
+ 8001b6c:	4a0a      	ldr	r2, [pc, #40]	; (8001b98 <HAL_UART_MspInit+0x26c>)
+ 8001b6e:	f8c3 2080 	str.w	r2, [r3, #128]	; 0x80
+ 8001b72:	4a09      	ldr	r2, [pc, #36]	; (8001b98 <HAL_UART_MspInit+0x26c>)
+ 8001b74:	687b      	ldr	r3, [r7, #4]
+ 8001b76:	6393      	str	r3, [r2, #56]	; 0x38
+}
+ 8001b78:	bf00      	nop
+ 8001b7a:	37f0      	adds	r7, #240	; 0xf0
+ 8001b7c:	46bd      	mov	sp, r7
+ 8001b7e:	bd80      	pop	{r7, pc}
+ 8001b80:	40004c00 	.word	0x40004c00
+ 8001b84:	58024400 	.word	0x58024400
+ 8001b88:	58020c00 	.word	0x58020c00
+ 8001b8c:	40007800 	.word	0x40007800
+ 8001b90:	58021000 	.word	0x58021000
+ 8001b94:	40007c00 	.word	0x40007c00
+ 8001b98:	240011cc 	.word	0x240011cc
+ 8001b9c:	40020010 	.word	0x40020010
+
+08001ba0 <HAL_InitTick>:
+  *         reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig().
+  * @param  TickPriority: Tick interrupt priority.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
+{
+ 8001ba0:	b580      	push	{r7, lr}
+ 8001ba2:	b090      	sub	sp, #64	; 0x40
+ 8001ba4:	af00      	add	r7, sp, #0
+ 8001ba6:	6078      	str	r0, [r7, #4]
+  uint32_t              uwTimclock, uwAPB1Prescaler;
+
+  uint32_t              uwPrescalerValue;
+  uint32_t              pFLatency;
+/*Configure the TIM6 IRQ priority */
+  if (TickPriority < (1UL << __NVIC_PRIO_BITS))
+ 8001ba8:	687b      	ldr	r3, [r7, #4]
+ 8001baa:	2b0f      	cmp	r3, #15
+ 8001bac:	d827      	bhi.n	8001bfe <HAL_InitTick+0x5e>
+  {
+  HAL_NVIC_SetPriority(TIM6_DAC_IRQn, TickPriority ,0U);
+ 8001bae:	2200      	movs	r2, #0
+ 8001bb0:	6879      	ldr	r1, [r7, #4]
+ 8001bb2:	2036      	movs	r0, #54	; 0x36
+ 8001bb4:	f000 fcd2 	bl	800255c <HAL_NVIC_SetPriority>
+
+  /* Enable the TIM6 global Interrupt */
+  HAL_NVIC_EnableIRQ(TIM6_DAC_IRQn);
+ 8001bb8:	2036      	movs	r0, #54	; 0x36
+ 8001bba:	f000 fce9 	bl	8002590 <HAL_NVIC_EnableIRQ>
+    uwTickPrio = TickPriority;
+ 8001bbe:	4a29      	ldr	r2, [pc, #164]	; (8001c64 <HAL_InitTick+0xc4>)
+ 8001bc0:	687b      	ldr	r3, [r7, #4]
+ 8001bc2:	6013      	str	r3, [r2, #0]
+  {
+    return HAL_ERROR;
+  }
+
+  /* Enable TIM6 clock */
+  __HAL_RCC_TIM6_CLK_ENABLE();
+ 8001bc4:	4b28      	ldr	r3, [pc, #160]	; (8001c68 <HAL_InitTick+0xc8>)
+ 8001bc6:	f8d3 30e8 	ldr.w	r3, [r3, #232]	; 0xe8
+ 8001bca:	4a27      	ldr	r2, [pc, #156]	; (8001c68 <HAL_InitTick+0xc8>)
+ 8001bcc:	f043 0310 	orr.w	r3, r3, #16
+ 8001bd0:	f8c2 30e8 	str.w	r3, [r2, #232]	; 0xe8
+ 8001bd4:	4b24      	ldr	r3, [pc, #144]	; (8001c68 <HAL_InitTick+0xc8>)
+ 8001bd6:	f8d3 30e8 	ldr.w	r3, [r3, #232]	; 0xe8
+ 8001bda:	f003 0310 	and.w	r3, r3, #16
+ 8001bde:	60fb      	str	r3, [r7, #12]
+ 8001be0:	68fb      	ldr	r3, [r7, #12]
+
+  /* Get clock configuration */
+  HAL_RCC_GetClockConfig(&clkconfig, &pFLatency);
+ 8001be2:	f107 0210 	add.w	r2, r7, #16
+ 8001be6:	f107 0314 	add.w	r3, r7, #20
+ 8001bea:	4611      	mov	r1, r2
+ 8001bec:	4618      	mov	r0, r3
+ 8001bee:	f006 f9e3 	bl	8007fb8 <HAL_RCC_GetClockConfig>
+
+  /* Get APB1 prescaler */
+  uwAPB1Prescaler = clkconfig.APB1CLKDivider;
+ 8001bf2:	6abb      	ldr	r3, [r7, #40]	; 0x28
+ 8001bf4:	63bb      	str	r3, [r7, #56]	; 0x38
+  /* Compute TIM6 clock */
+  if (uwAPB1Prescaler == RCC_HCLK_DIV1)
+ 8001bf6:	6bbb      	ldr	r3, [r7, #56]	; 0x38
+ 8001bf8:	2b00      	cmp	r3, #0
+ 8001bfa:	d106      	bne.n	8001c0a <HAL_InitTick+0x6a>
+ 8001bfc:	e001      	b.n	8001c02 <HAL_InitTick+0x62>
+    return HAL_ERROR;
+ 8001bfe:	2301      	movs	r3, #1
+ 8001c00:	e02b      	b.n	8001c5a <HAL_InitTick+0xba>
+  {
+    uwTimclock = HAL_RCC_GetPCLK1Freq();
+ 8001c02:	f006 f9ad 	bl	8007f60 <HAL_RCC_GetPCLK1Freq>
+ 8001c06:	63f8      	str	r0, [r7, #60]	; 0x3c
+ 8001c08:	e004      	b.n	8001c14 <HAL_InitTick+0x74>
+  }
+  else
+  {
+    uwTimclock = 2UL * HAL_RCC_GetPCLK1Freq();
+ 8001c0a:	f006 f9a9 	bl	8007f60 <HAL_RCC_GetPCLK1Freq>
+ 8001c0e:	4603      	mov	r3, r0
+ 8001c10:	005b      	lsls	r3, r3, #1
+ 8001c12:	63fb      	str	r3, [r7, #60]	; 0x3c
+  }
+
+  /* Compute the prescaler value to have TIM6 counter clock equal to 1MHz */
+  uwPrescalerValue = (uint32_t) ((uwTimclock / 1000000U) - 1U);
+ 8001c14:	6bfb      	ldr	r3, [r7, #60]	; 0x3c
+ 8001c16:	4a15      	ldr	r2, [pc, #84]	; (8001c6c <HAL_InitTick+0xcc>)
+ 8001c18:	fba2 2303 	umull	r2, r3, r2, r3
+ 8001c1c:	0c9b      	lsrs	r3, r3, #18
+ 8001c1e:	3b01      	subs	r3, #1
+ 8001c20:	637b      	str	r3, [r7, #52]	; 0x34
+
+  /* Initialize TIM6 */
+  htim6.Instance = TIM6;
+ 8001c22:	4b13      	ldr	r3, [pc, #76]	; (8001c70 <HAL_InitTick+0xd0>)
+ 8001c24:	4a13      	ldr	r2, [pc, #76]	; (8001c74 <HAL_InitTick+0xd4>)
+ 8001c26:	601a      	str	r2, [r3, #0]
+  + Period = [(TIM6CLK/1000) - 1]. to have a (1/1000) s time base.
+  + Prescaler = (uwTimclock/1000000 - 1) to have a 1MHz counter clock.
+  + ClockDivision = 0
+  + Counter direction = Up
+  */
+  htim6.Init.Period = (1000000U / 1000U) - 1U;
+ 8001c28:	4b11      	ldr	r3, [pc, #68]	; (8001c70 <HAL_InitTick+0xd0>)
+ 8001c2a:	f240 32e7 	movw	r2, #999	; 0x3e7
+ 8001c2e:	60da      	str	r2, [r3, #12]
+  htim6.Init.Prescaler = uwPrescalerValue;
+ 8001c30:	4a0f      	ldr	r2, [pc, #60]	; (8001c70 <HAL_InitTick+0xd0>)
+ 8001c32:	6b7b      	ldr	r3, [r7, #52]	; 0x34
+ 8001c34:	6053      	str	r3, [r2, #4]
+  htim6.Init.ClockDivision = 0;
+ 8001c36:	4b0e      	ldr	r3, [pc, #56]	; (8001c70 <HAL_InitTick+0xd0>)
+ 8001c38:	2200      	movs	r2, #0
+ 8001c3a:	611a      	str	r2, [r3, #16]
+  htim6.Init.CounterMode = TIM_COUNTERMODE_UP;
+ 8001c3c:	4b0c      	ldr	r3, [pc, #48]	; (8001c70 <HAL_InitTick+0xd0>)
+ 8001c3e:	2200      	movs	r2, #0
+ 8001c40:	609a      	str	r2, [r3, #8]
+
+  if(HAL_TIM_Base_Init(&htim6) == HAL_OK)
+ 8001c42:	480b      	ldr	r0, [pc, #44]	; (8001c70 <HAL_InitTick+0xd0>)
+ 8001c44:	f00a fa44 	bl	800c0d0 <HAL_TIM_Base_Init>
+ 8001c48:	4603      	mov	r3, r0
+ 8001c4a:	2b00      	cmp	r3, #0
+ 8001c4c:	d104      	bne.n	8001c58 <HAL_InitTick+0xb8>
+  {
+    /* Start the TIM time Base generation in interrupt mode */
+    return HAL_TIM_Base_Start_IT(&htim6);
+ 8001c4e:	4808      	ldr	r0, [pc, #32]	; (8001c70 <HAL_InitTick+0xd0>)
+ 8001c50:	f00a fa96 	bl	800c180 <HAL_TIM_Base_Start_IT>
+ 8001c54:	4603      	mov	r3, r0
+ 8001c56:	e000      	b.n	8001c5a <HAL_InitTick+0xba>
+  }
+
+  /* Return function status */
+  return HAL_ERROR;
+ 8001c58:	2301      	movs	r3, #1
+}
+ 8001c5a:	4618      	mov	r0, r3
+ 8001c5c:	3740      	adds	r7, #64	; 0x40
+ 8001c5e:	46bd      	mov	sp, r7
+ 8001c60:	bd80      	pop	{r7, pc}
+ 8001c62:	bf00      	nop
+ 8001c64:	2400001c 	.word	0x2400001c
+ 8001c68:	58024400 	.word	0x58024400
+ 8001c6c:	431bde83 	.word	0x431bde83
+ 8001c70:	24007384 	.word	0x24007384
+ 8001c74:	40001000 	.word	0x40001000
+
+08001c78 <NMI_Handler>:
+/******************************************************************************/
+/**
+  * @brief This function handles Non maskable interrupt.
+  */
+void NMI_Handler(void)
+{
+ 8001c78:	b480      	push	{r7}
+ 8001c7a:	af00      	add	r7, sp, #0
+  /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
+
+  /* USER CODE END NonMaskableInt_IRQn 0 */
+  /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
+   while (1)
+ 8001c7c:	e7fe      	b.n	8001c7c <NMI_Handler+0x4>
+
+08001c7e <HardFault_Handler>:
+
+/**
+  * @brief This function handles Hard fault interrupt.
+  */
+void HardFault_Handler(void)
+{
+ 8001c7e:	b480      	push	{r7}
+ 8001c80:	af00      	add	r7, sp, #0
+  /* USER CODE BEGIN HardFault_IRQn 0 */
+
+  /* USER CODE END HardFault_IRQn 0 */
+  while (1)
+ 8001c82:	e7fe      	b.n	8001c82 <HardFault_Handler+0x4>
+
+08001c84 <MemManage_Handler>:
+
+/**
+  * @brief This function handles Memory management fault.
+  */
+void MemManage_Handler(void)
+{
+ 8001c84:	b480      	push	{r7}
+ 8001c86:	af00      	add	r7, sp, #0
+  /* USER CODE BEGIN MemoryManagement_IRQn 0 */
+
+  /* USER CODE END MemoryManagement_IRQn 0 */
+  while (1)
+ 8001c88:	e7fe      	b.n	8001c88 <MemManage_Handler+0x4>
+
+08001c8a <BusFault_Handler>:
+
+/**
+  * @brief This function handles Pre-fetch fault, memory access fault.
+  */
+void BusFault_Handler(void)
+{
+ 8001c8a:	b480      	push	{r7}
+ 8001c8c:	af00      	add	r7, sp, #0
+  /* USER CODE BEGIN BusFault_IRQn 0 */
+
+  /* USER CODE END BusFault_IRQn 0 */
+  while (1)
+ 8001c8e:	e7fe      	b.n	8001c8e <BusFault_Handler+0x4>
+
+08001c90 <UsageFault_Handler>:
+
+/**
+  * @brief This function handles Undefined instruction or illegal state.
+  */
+void UsageFault_Handler(void)
+{
+ 8001c90:	b480      	push	{r7}
+ 8001c92:	af00      	add	r7, sp, #0
+  /* USER CODE BEGIN UsageFault_IRQn 0 */
+
+  /* USER CODE END UsageFault_IRQn 0 */
+  while (1)
+ 8001c94:	e7fe      	b.n	8001c94 <UsageFault_Handler+0x4>
+
+08001c96 <DebugMon_Handler>:
+
+/**
+  * @brief This function handles Debug monitor.
+  */
+void DebugMon_Handler(void)
+{
+ 8001c96:	b480      	push	{r7}
+ 8001c98:	af00      	add	r7, sp, #0
+
+  /* USER CODE END DebugMonitor_IRQn 0 */
+  /* USER CODE BEGIN DebugMonitor_IRQn 1 */
+
+  /* USER CODE END DebugMonitor_IRQn 1 */
+}
+ 8001c9a:	bf00      	nop
+ 8001c9c:	46bd      	mov	sp, r7
+ 8001c9e:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8001ca2:	4770      	bx	lr
+
+08001ca4 <DMA1_Stream0_IRQHandler>:
+
+/**
+  * @brief This function handles DMA1 stream0 global interrupt.
+  */
+void DMA1_Stream0_IRQHandler(void)
+{
+ 8001ca4:	b580      	push	{r7, lr}
+ 8001ca6:	af00      	add	r7, sp, #0
+  /* USER CODE BEGIN DMA1_Stream0_IRQn 0 */
+
+  /* USER CODE END DMA1_Stream0_IRQn 0 */
+  HAL_DMA_IRQHandler(&hdma_uart8_rx);
+ 8001ca8:	4802      	ldr	r0, [pc, #8]	; (8001cb4 <DMA1_Stream0_IRQHandler+0x10>)
+ 8001caa:	f001 f853 	bl	8002d54 <HAL_DMA_IRQHandler>
+  /* USER CODE BEGIN DMA1_Stream0_IRQn 1 */
+
+  /* USER CODE END DMA1_Stream0_IRQn 1 */
+}
+ 8001cae:	bf00      	nop
+ 8001cb0:	bd80      	pop	{r7, pc}
+ 8001cb2:	bf00      	nop
+ 8001cb4:	240011cc 	.word	0x240011cc
+
+08001cb8 <FDCAN1_IT0_IRQHandler>:
+
+/**
+  * @brief This function handles FDCAN1 interrupt 0.
+  */
+void FDCAN1_IT0_IRQHandler(void)
+{
+ 8001cb8:	b580      	push	{r7, lr}
+ 8001cba:	af00      	add	r7, sp, #0
+  /* USER CODE BEGIN FDCAN1_IT0_IRQn 0 */
+
+  /* USER CODE END FDCAN1_IT0_IRQn 0 */
+  HAL_FDCAN_IRQHandler(&hfdcan1);
+ 8001cbc:	4802      	ldr	r0, [pc, #8]	; (8001cc8 <FDCAN1_IT0_IRQHandler+0x10>)
+ 8001cbe:	f004 f8ef 	bl	8005ea0 <HAL_FDCAN_IRQHandler>
+  /* USER CODE BEGIN FDCAN1_IT0_IRQn 1 */
+
+  /* USER CODE END FDCAN1_IT0_IRQn 1 */
+}
+ 8001cc2:	bf00      	nop
+ 8001cc4:	bd80      	pop	{r7, pc}
+ 8001cc6:	bf00      	nop
+ 8001cc8:	24000d68 	.word	0x24000d68
+
+08001ccc <FDCAN2_IT0_IRQHandler>:
+
+/**
+  * @brief This function handles FDCAN2 interrupt 0.
+  */
+void FDCAN2_IT0_IRQHandler(void)
+{
+ 8001ccc:	b580      	push	{r7, lr}
+ 8001cce:	af00      	add	r7, sp, #0
+  /* USER CODE BEGIN FDCAN2_IT0_IRQn 0 */
+
+  /* USER CODE END FDCAN2_IT0_IRQn 0 */
+  HAL_FDCAN_IRQHandler(&hfdcan2);
+ 8001cd0:	4802      	ldr	r0, [pc, #8]	; (8001cdc <FDCAN2_IT0_IRQHandler+0x10>)
+ 8001cd2:	f004 f8e5 	bl	8005ea0 <HAL_FDCAN_IRQHandler>
+  /* USER CODE BEGIN FDCAN2_IT0_IRQn 1 */
+
+  /* USER CODE END FDCAN2_IT0_IRQn 1 */
+}
+ 8001cd6:	bf00      	nop
+ 8001cd8:	bd80      	pop	{r7, pc}
+ 8001cda:	bf00      	nop
+ 8001cdc:	24000e08 	.word	0x24000e08
+
+08001ce0 <SDMMC1_IRQHandler>:
+
+/**
+  * @brief This function handles SDMMC1 global interrupt.
+  */
+void SDMMC1_IRQHandler(void)
+{
+ 8001ce0:	b580      	push	{r7, lr}
+ 8001ce2:	af00      	add	r7, sp, #0
+  /* USER CODE BEGIN SDMMC1_IRQn 0 */
+
+  /* USER CODE END SDMMC1_IRQn 0 */
+  HAL_SD_IRQHandler(&hsd1);
+ 8001ce4:	4802      	ldr	r0, [pc, #8]	; (8001cf0 <SDMMC1_IRQHandler+0x10>)
+ 8001ce6:	f008 ffff 	bl	800ace8 <HAL_SD_IRQHandler>
+  /* USER CODE BEGIN SDMMC1_IRQn 1 */
+
+  /* USER CODE END SDMMC1_IRQn 1 */
+}
+ 8001cea:	bf00      	nop
+ 8001cec:	bd80      	pop	{r7, pc}
+ 8001cee:	bf00      	nop
+ 8001cf0:	24000f48 	.word	0x24000f48
+
+08001cf4 <TIM6_DAC_IRQHandler>:
+
+/**
+  * @brief This function handles TIM6 global interrupt, DAC1_CH1 and DAC1_CH2 underrun error interrupts.
+  */
+void TIM6_DAC_IRQHandler(void)
+{
+ 8001cf4:	b580      	push	{r7, lr}
+ 8001cf6:	af00      	add	r7, sp, #0
+  /* USER CODE BEGIN TIM6_DAC_IRQn 0 */
+
+  /* USER CODE END TIM6_DAC_IRQn 0 */
+  HAL_TIM_IRQHandler(&htim6);
+ 8001cf8:	4802      	ldr	r0, [pc, #8]	; (8001d04 <TIM6_DAC_IRQHandler+0x10>)
+ 8001cfa:	f00a fac7 	bl	800c28c <HAL_TIM_IRQHandler>
+  /* USER CODE BEGIN TIM6_DAC_IRQn 1 */
+
+  /* USER CODE END TIM6_DAC_IRQn 1 */
+}
+ 8001cfe:	bf00      	nop
+ 8001d00:	bd80      	pop	{r7, pc}
+ 8001d02:	bf00      	nop
+ 8001d04:	24007384 	.word	0x24007384
+
+08001d08 <ETH_IRQHandler>:
+
+/**
+  * @brief This function handles Ethernet global interrupt.
+  */
+void ETH_IRQHandler(void)
+{
+ 8001d08:	b580      	push	{r7, lr}
+ 8001d0a:	af00      	add	r7, sp, #0
+  /* USER CODE BEGIN ETH_IRQn 0 */
+
+  /* USER CODE END ETH_IRQn 0 */
+  HAL_ETH_IRQHandler(&heth);
+ 8001d0c:	4802      	ldr	r0, [pc, #8]	; (8001d18 <ETH_IRQHandler+0x10>)
+ 8001d0e:	f002 fd4b 	bl	80047a8 <HAL_ETH_IRQHandler>
+  /* USER CODE BEGIN ETH_IRQn 1 */
+
+  /* USER CODE END ETH_IRQn 1 */
+}
+ 8001d12:	bf00      	nop
+ 8001d14:	bd80      	pop	{r7, pc}
+ 8001d16:	bf00      	nop
+ 8001d18:	2400bdcc 	.word	0x2400bdcc
+
+08001d1c <MDMA_IRQHandler>:
+
+/**
+  * @brief This function handles MDMA global interrupt.
+  */
+void MDMA_IRQHandler(void)
+{
+ 8001d1c:	b580      	push	{r7, lr}
+ 8001d1e:	af00      	add	r7, sp, #0
+  /* USER CODE BEGIN MDMA_IRQn 0 */
+
+  /* USER CODE END MDMA_IRQn 0 */
+  HAL_MDMA_IRQHandler(&hmdma_mdma_channel0_sdmmc1_end_data_0);
+ 8001d20:	4802      	ldr	r0, [pc, #8]	; (8001d2c <MDMA_IRQHandler+0x10>)
+ 8001d22:	f004 ffbd 	bl	8006ca0 <HAL_MDMA_IRQHandler>
+  /* USER CODE BEGIN MDMA_IRQn 1 */
+
+  /* USER CODE END MDMA_IRQn 1 */
+}
+ 8001d26:	bf00      	nop
+ 8001d28:	bd80      	pop	{r7, pc}
+ 8001d2a:	bf00      	nop
+ 8001d2c:	24001244 	.word	0x24001244
+
+08001d30 <FDCAN3_IT0_IRQHandler>:
+
+/**
+  * @brief This function handles FDCAN3 interrupt 0.
+  */
+void FDCAN3_IT0_IRQHandler(void)
+{
+ 8001d30:	b580      	push	{r7, lr}
+ 8001d32:	af00      	add	r7, sp, #0
+  /* USER CODE BEGIN FDCAN3_IT0_IRQn 0 */
+
+  /* USER CODE END FDCAN3_IT0_IRQn 0 */
+  HAL_FDCAN_IRQHandler(&hfdcan3);
+ 8001d34:	4802      	ldr	r0, [pc, #8]	; (8001d40 <FDCAN3_IT0_IRQHandler+0x10>)
+ 8001d36:	f004 f8b3 	bl	8005ea0 <HAL_FDCAN_IRQHandler>
+  /* USER CODE BEGIN FDCAN3_IT0_IRQn 1 */
+
+  /* USER CODE END FDCAN3_IT0_IRQn 1 */
+}
+ 8001d3a:	bf00      	nop
+ 8001d3c:	bd80      	pop	{r7, pc}
+ 8001d3e:	bf00      	nop
+ 8001d40:	24000ea8 	.word	0x24000ea8
+
+08001d44 <_getpid>:
+void initialise_monitor_handles()
+{
+}
+
+int _getpid(void)
+{
+ 8001d44:	b480      	push	{r7}
+ 8001d46:	af00      	add	r7, sp, #0
+  return 1;
+ 8001d48:	2301      	movs	r3, #1
+}
+ 8001d4a:	4618      	mov	r0, r3
+ 8001d4c:	46bd      	mov	sp, r7
+ 8001d4e:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8001d52:	4770      	bx	lr
+
+08001d54 <_kill>:
+
+int _kill(int pid, int sig)
+{
+ 8001d54:	b480      	push	{r7}
+ 8001d56:	b083      	sub	sp, #12
+ 8001d58:	af00      	add	r7, sp, #0
+ 8001d5a:	6078      	str	r0, [r7, #4]
+ 8001d5c:	6039      	str	r1, [r7, #0]
+  (void)pid;
+  (void)sig;
+  errno = EINVAL;
+ 8001d5e:	4b05      	ldr	r3, [pc, #20]	; (8001d74 <_kill+0x20>)
+ 8001d60:	2216      	movs	r2, #22
+ 8001d62:	601a      	str	r2, [r3, #0]
+  return -1;
+ 8001d64:	f04f 33ff 	mov.w	r3, #4294967295
+}
+ 8001d68:	4618      	mov	r0, r3
+ 8001d6a:	370c      	adds	r7, #12
+ 8001d6c:	46bd      	mov	sp, r7
+ 8001d6e:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8001d72:	4770      	bx	lr
+ 8001d74:	2401a5e0 	.word	0x2401a5e0
+
+08001d78 <_exit>:
+
+void _exit (int status)
+{
+ 8001d78:	b580      	push	{r7, lr}
+ 8001d7a:	b082      	sub	sp, #8
+ 8001d7c:	af00      	add	r7, sp, #0
+ 8001d7e:	6078      	str	r0, [r7, #4]
+  _kill(status, -1);
+ 8001d80:	f04f 31ff 	mov.w	r1, #4294967295
+ 8001d84:	6878      	ldr	r0, [r7, #4]
+ 8001d86:	f7ff ffe5 	bl	8001d54 <_kill>
+  while (1) {}    /* Make sure we hang here */
+ 8001d8a:	e7fe      	b.n	8001d8a <_exit+0x12>
+
+08001d8c <_read>:
+}
+
+__attribute__((weak)) int _read(int file, char *ptr, int len)
+{
+ 8001d8c:	b580      	push	{r7, lr}
+ 8001d8e:	b086      	sub	sp, #24
+ 8001d90:	af00      	add	r7, sp, #0
+ 8001d92:	60f8      	str	r0, [r7, #12]
+ 8001d94:	60b9      	str	r1, [r7, #8]
+ 8001d96:	607a      	str	r2, [r7, #4]
+  (void)file;
+  int DataIdx;
+
+  for (DataIdx = 0; DataIdx < len; DataIdx++)
+ 8001d98:	2300      	movs	r3, #0
+ 8001d9a:	617b      	str	r3, [r7, #20]
+ 8001d9c:	e00a      	b.n	8001db4 <_read+0x28>
+  {
+    *ptr++ = __io_getchar();
+ 8001d9e:	f3af 8000 	nop.w
+ 8001da2:	4601      	mov	r1, r0
+ 8001da4:	68bb      	ldr	r3, [r7, #8]
+ 8001da6:	1c5a      	adds	r2, r3, #1
+ 8001da8:	60ba      	str	r2, [r7, #8]
+ 8001daa:	b2ca      	uxtb	r2, r1
+ 8001dac:	701a      	strb	r2, [r3, #0]
+  for (DataIdx = 0; DataIdx < len; DataIdx++)
+ 8001dae:	697b      	ldr	r3, [r7, #20]
+ 8001db0:	3301      	adds	r3, #1
+ 8001db2:	617b      	str	r3, [r7, #20]
+ 8001db4:	697a      	ldr	r2, [r7, #20]
+ 8001db6:	687b      	ldr	r3, [r7, #4]
+ 8001db8:	429a      	cmp	r2, r3
+ 8001dba:	dbf0      	blt.n	8001d9e <_read+0x12>
+  }
+
+  return len;
+ 8001dbc:	687b      	ldr	r3, [r7, #4]
+}
+ 8001dbe:	4618      	mov	r0, r3
+ 8001dc0:	3718      	adds	r7, #24
+ 8001dc2:	46bd      	mov	sp, r7
+ 8001dc4:	bd80      	pop	{r7, pc}
+
+08001dc6 <_close>:
+  }
+  return len;
+}
+
+int _close(int file)
+{
+ 8001dc6:	b480      	push	{r7}
+ 8001dc8:	b083      	sub	sp, #12
+ 8001dca:	af00      	add	r7, sp, #0
+ 8001dcc:	6078      	str	r0, [r7, #4]
+  (void)file;
+  return -1;
+ 8001dce:	f04f 33ff 	mov.w	r3, #4294967295
+}
+ 8001dd2:	4618      	mov	r0, r3
+ 8001dd4:	370c      	adds	r7, #12
+ 8001dd6:	46bd      	mov	sp, r7
+ 8001dd8:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8001ddc:	4770      	bx	lr
+
+08001dde <_fstat>:
+
+
+int _fstat(int file, struct stat *st)
+{
+ 8001dde:	b480      	push	{r7}
+ 8001de0:	b083      	sub	sp, #12
+ 8001de2:	af00      	add	r7, sp, #0
+ 8001de4:	6078      	str	r0, [r7, #4]
+ 8001de6:	6039      	str	r1, [r7, #0]
+  (void)file;
+  st->st_mode = S_IFCHR;
+ 8001de8:	683b      	ldr	r3, [r7, #0]
+ 8001dea:	f44f 5200 	mov.w	r2, #8192	; 0x2000
+ 8001dee:	605a      	str	r2, [r3, #4]
+  return 0;
+ 8001df0:	2300      	movs	r3, #0
+}
+ 8001df2:	4618      	mov	r0, r3
+ 8001df4:	370c      	adds	r7, #12
+ 8001df6:	46bd      	mov	sp, r7
+ 8001df8:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8001dfc:	4770      	bx	lr
+
+08001dfe <_isatty>:
+
+int _isatty(int file)
+{
+ 8001dfe:	b480      	push	{r7}
+ 8001e00:	b083      	sub	sp, #12
+ 8001e02:	af00      	add	r7, sp, #0
+ 8001e04:	6078      	str	r0, [r7, #4]
+  (void)file;
+  return 1;
+ 8001e06:	2301      	movs	r3, #1
+}
+ 8001e08:	4618      	mov	r0, r3
+ 8001e0a:	370c      	adds	r7, #12
+ 8001e0c:	46bd      	mov	sp, r7
+ 8001e0e:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8001e12:	4770      	bx	lr
+
+08001e14 <_lseek>:
+
+int _lseek(int file, int ptr, int dir)
+{
+ 8001e14:	b480      	push	{r7}
+ 8001e16:	b085      	sub	sp, #20
+ 8001e18:	af00      	add	r7, sp, #0
+ 8001e1a:	60f8      	str	r0, [r7, #12]
+ 8001e1c:	60b9      	str	r1, [r7, #8]
+ 8001e1e:	607a      	str	r2, [r7, #4]
+  (void)file;
+  (void)ptr;
+  (void)dir;
+  return 0;
+ 8001e20:	2300      	movs	r3, #0
+}
+ 8001e22:	4618      	mov	r0, r3
+ 8001e24:	3714      	adds	r7, #20
+ 8001e26:	46bd      	mov	sp, r7
+ 8001e28:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8001e2c:	4770      	bx	lr
+	...
+
+08001e30 <_sbrk>:
+ *
+ * @param incr Memory size
+ * @return Pointer to allocated memory
+ */
+void *_sbrk(ptrdiff_t incr)
+{
+ 8001e30:	b480      	push	{r7}
+ 8001e32:	b087      	sub	sp, #28
+ 8001e34:	af00      	add	r7, sp, #0
+ 8001e36:	6078      	str	r0, [r7, #4]
+  extern uint8_t _end; /* Symbol defined in the linker script */
+  extern uint8_t _estack; /* Symbol defined in the linker script */
+  extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */
+  const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size;
+ 8001e38:	4a14      	ldr	r2, [pc, #80]	; (8001e8c <_sbrk+0x5c>)
+ 8001e3a:	4b15      	ldr	r3, [pc, #84]	; (8001e90 <_sbrk+0x60>)
+ 8001e3c:	1ad3      	subs	r3, r2, r3
+ 8001e3e:	617b      	str	r3, [r7, #20]
+  const uint8_t *max_heap = (uint8_t *)stack_limit;
+ 8001e40:	697b      	ldr	r3, [r7, #20]
+ 8001e42:	613b      	str	r3, [r7, #16]
+  uint8_t *prev_heap_end;
+
+  /* Initialize heap end at first call */
+  if (NULL == __sbrk_heap_end)
+ 8001e44:	4b13      	ldr	r3, [pc, #76]	; (8001e94 <_sbrk+0x64>)
+ 8001e46:	681b      	ldr	r3, [r3, #0]
+ 8001e48:	2b00      	cmp	r3, #0
+ 8001e4a:	d102      	bne.n	8001e52 <_sbrk+0x22>
+  {
+    __sbrk_heap_end = &_end;
+ 8001e4c:	4b11      	ldr	r3, [pc, #68]	; (8001e94 <_sbrk+0x64>)
+ 8001e4e:	4a12      	ldr	r2, [pc, #72]	; (8001e98 <_sbrk+0x68>)
+ 8001e50:	601a      	str	r2, [r3, #0]
+  }
+
+  /* Protect heap from growing into the reserved MSP stack */
+  if (__sbrk_heap_end + incr > max_heap)
+ 8001e52:	4b10      	ldr	r3, [pc, #64]	; (8001e94 <_sbrk+0x64>)
+ 8001e54:	681a      	ldr	r2, [r3, #0]
+ 8001e56:	687b      	ldr	r3, [r7, #4]
+ 8001e58:	4413      	add	r3, r2
+ 8001e5a:	693a      	ldr	r2, [r7, #16]
+ 8001e5c:	429a      	cmp	r2, r3
+ 8001e5e:	d205      	bcs.n	8001e6c <_sbrk+0x3c>
+  {
+    errno = ENOMEM;
+ 8001e60:	4b0e      	ldr	r3, [pc, #56]	; (8001e9c <_sbrk+0x6c>)
+ 8001e62:	220c      	movs	r2, #12
+ 8001e64:	601a      	str	r2, [r3, #0]
+    return (void *)-1;
+ 8001e66:	f04f 33ff 	mov.w	r3, #4294967295
+ 8001e6a:	e009      	b.n	8001e80 <_sbrk+0x50>
+  }
+
+  prev_heap_end = __sbrk_heap_end;
+ 8001e6c:	4b09      	ldr	r3, [pc, #36]	; (8001e94 <_sbrk+0x64>)
+ 8001e6e:	681b      	ldr	r3, [r3, #0]
+ 8001e70:	60fb      	str	r3, [r7, #12]
+  __sbrk_heap_end += incr;
+ 8001e72:	4b08      	ldr	r3, [pc, #32]	; (8001e94 <_sbrk+0x64>)
+ 8001e74:	681a      	ldr	r2, [r3, #0]
+ 8001e76:	687b      	ldr	r3, [r7, #4]
+ 8001e78:	4413      	add	r3, r2
+ 8001e7a:	4a06      	ldr	r2, [pc, #24]	; (8001e94 <_sbrk+0x64>)
+ 8001e7c:	6013      	str	r3, [r2, #0]
+
+  return (void *)prev_heap_end;
+ 8001e7e:	68fb      	ldr	r3, [r7, #12]
+}
+ 8001e80:	4618      	mov	r0, r3
+ 8001e82:	371c      	adds	r7, #28
+ 8001e84:	46bd      	mov	sp, r7
+ 8001e86:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8001e8a:	4770      	bx	lr
+ 8001e8c:	24050000 	.word	0x24050000
+ 8001e90:	00004000 	.word	0x00004000
+ 8001e94:	240073d0 	.word	0x240073d0
+ 8001e98:	2401a730 	.word	0x2401a730
+ 8001e9c:	2401a5e0 	.word	0x2401a5e0
+
+08001ea0 <SystemInit>:
+  *         configuration.
+  * @param  None
+  * @retval None
+  */
+void SystemInit (void)
+{
+ 8001ea0:	b480      	push	{r7}
+ 8001ea2:	b083      	sub	sp, #12
+ 8001ea4:	af00      	add	r7, sp, #0
+ __IO uint32_t tmpreg;
+#endif /* DATA_IN_D2_SRAM */
+
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << (10*2))|(3UL << (11*2)));  /* set CP10 and CP11 Full Access */
+ 8001ea6:	4b3a      	ldr	r3, [pc, #232]	; (8001f90 <SystemInit+0xf0>)
+ 8001ea8:	f8d3 3088 	ldr.w	r3, [r3, #136]	; 0x88
+ 8001eac:	4a38      	ldr	r2, [pc, #224]	; (8001f90 <SystemInit+0xf0>)
+ 8001eae:	f443 0370 	orr.w	r3, r3, #15728640	; 0xf00000
+ 8001eb2:	f8c2 3088 	str.w	r3, [r2, #136]	; 0x88
+  #endif
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+
+   /* Increasing the CPU frequency */
+  if(FLASH_LATENCY_DEFAULT  > (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)))
+ 8001eb6:	4b37      	ldr	r3, [pc, #220]	; (8001f94 <SystemInit+0xf4>)
+ 8001eb8:	681b      	ldr	r3, [r3, #0]
+ 8001eba:	f003 030f 	and.w	r3, r3, #15
+ 8001ebe:	2b06      	cmp	r3, #6
+ 8001ec0:	d807      	bhi.n	8001ed2 <SystemInit+0x32>
+  {
+    /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
+    MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT));
+ 8001ec2:	4b34      	ldr	r3, [pc, #208]	; (8001f94 <SystemInit+0xf4>)
+ 8001ec4:	681b      	ldr	r3, [r3, #0]
+ 8001ec6:	f023 030f 	bic.w	r3, r3, #15
+ 8001eca:	4a32      	ldr	r2, [pc, #200]	; (8001f94 <SystemInit+0xf4>)
+ 8001ecc:	f043 0307 	orr.w	r3, r3, #7
+ 8001ed0:	6013      	str	r3, [r2, #0]
+  }
+
+  /* Set HSION bit */
+  RCC->CR |= RCC_CR_HSION;
+ 8001ed2:	4b31      	ldr	r3, [pc, #196]	; (8001f98 <SystemInit+0xf8>)
+ 8001ed4:	681b      	ldr	r3, [r3, #0]
+ 8001ed6:	4a30      	ldr	r2, [pc, #192]	; (8001f98 <SystemInit+0xf8>)
+ 8001ed8:	f043 0301 	orr.w	r3, r3, #1
+ 8001edc:	6013      	str	r3, [r2, #0]
+
+  /* Reset CFGR register */
+  RCC->CFGR = 0x00000000;
+ 8001ede:	4b2e      	ldr	r3, [pc, #184]	; (8001f98 <SystemInit+0xf8>)
+ 8001ee0:	2200      	movs	r2, #0
+ 8001ee2:	611a      	str	r2, [r3, #16]
+
+  /* Reset HSEON, HSECSSON, CSION, HSI48ON, CSIKERON, PLL1ON, PLL2ON and PLL3ON bits */
+  RCC->CR &= 0xEAF6ED7FU;
+ 8001ee4:	4b2c      	ldr	r3, [pc, #176]	; (8001f98 <SystemInit+0xf8>)
+ 8001ee6:	681a      	ldr	r2, [r3, #0]
+ 8001ee8:	492b      	ldr	r1, [pc, #172]	; (8001f98 <SystemInit+0xf8>)
+ 8001eea:	4b2c      	ldr	r3, [pc, #176]	; (8001f9c <SystemInit+0xfc>)
+ 8001eec:	4013      	ands	r3, r2
+ 8001eee:	600b      	str	r3, [r1, #0]
+
+   /* Decreasing the number of wait states because of lower CPU frequency */
+  if(FLASH_LATENCY_DEFAULT  < (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)))
+ 8001ef0:	4b28      	ldr	r3, [pc, #160]	; (8001f94 <SystemInit+0xf4>)
+ 8001ef2:	681b      	ldr	r3, [r3, #0]
+ 8001ef4:	f003 0308 	and.w	r3, r3, #8
+ 8001ef8:	2b00      	cmp	r3, #0
+ 8001efa:	d007      	beq.n	8001f0c <SystemInit+0x6c>
+  {
+    /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
+    MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT));
+ 8001efc:	4b25      	ldr	r3, [pc, #148]	; (8001f94 <SystemInit+0xf4>)
+ 8001efe:	681b      	ldr	r3, [r3, #0]
+ 8001f00:	f023 030f 	bic.w	r3, r3, #15
+ 8001f04:	4a23      	ldr	r2, [pc, #140]	; (8001f94 <SystemInit+0xf4>)
+ 8001f06:	f043 0307 	orr.w	r3, r3, #7
+ 8001f0a:	6013      	str	r3, [r2, #0]
+  }
+
+#if defined(D3_SRAM_BASE)
+  /* Reset D1CFGR register */
+  RCC->D1CFGR = 0x00000000;
+ 8001f0c:	4b22      	ldr	r3, [pc, #136]	; (8001f98 <SystemInit+0xf8>)
+ 8001f0e:	2200      	movs	r2, #0
+ 8001f10:	619a      	str	r2, [r3, #24]
+
+  /* Reset D2CFGR register */
+  RCC->D2CFGR = 0x00000000;
+ 8001f12:	4b21      	ldr	r3, [pc, #132]	; (8001f98 <SystemInit+0xf8>)
+ 8001f14:	2200      	movs	r2, #0
+ 8001f16:	61da      	str	r2, [r3, #28]
+
+  /* Reset D3CFGR register */
+  RCC->D3CFGR = 0x00000000;
+ 8001f18:	4b1f      	ldr	r3, [pc, #124]	; (8001f98 <SystemInit+0xf8>)
+ 8001f1a:	2200      	movs	r2, #0
+ 8001f1c:	621a      	str	r2, [r3, #32]
+
+  /* Reset SRDCFGR register */
+  RCC->SRDCFGR = 0x00000000;
+#endif
+  /* Reset PLLCKSELR register */
+  RCC->PLLCKSELR = 0x02020200;
+ 8001f1e:	4b1e      	ldr	r3, [pc, #120]	; (8001f98 <SystemInit+0xf8>)
+ 8001f20:	4a1f      	ldr	r2, [pc, #124]	; (8001fa0 <SystemInit+0x100>)
+ 8001f22:	629a      	str	r2, [r3, #40]	; 0x28
+
+  /* Reset PLLCFGR register */
+  RCC->PLLCFGR = 0x01FF0000;
+ 8001f24:	4b1c      	ldr	r3, [pc, #112]	; (8001f98 <SystemInit+0xf8>)
+ 8001f26:	4a1f      	ldr	r2, [pc, #124]	; (8001fa4 <SystemInit+0x104>)
+ 8001f28:	62da      	str	r2, [r3, #44]	; 0x2c
+  /* Reset PLL1DIVR register */
+  RCC->PLL1DIVR = 0x01010280;
+ 8001f2a:	4b1b      	ldr	r3, [pc, #108]	; (8001f98 <SystemInit+0xf8>)
+ 8001f2c:	4a1e      	ldr	r2, [pc, #120]	; (8001fa8 <SystemInit+0x108>)
+ 8001f2e:	631a      	str	r2, [r3, #48]	; 0x30
+  /* Reset PLL1FRACR register */
+  RCC->PLL1FRACR = 0x00000000;
+ 8001f30:	4b19      	ldr	r3, [pc, #100]	; (8001f98 <SystemInit+0xf8>)
+ 8001f32:	2200      	movs	r2, #0
+ 8001f34:	635a      	str	r2, [r3, #52]	; 0x34
+
+  /* Reset PLL2DIVR register */
+  RCC->PLL2DIVR = 0x01010280;
+ 8001f36:	4b18      	ldr	r3, [pc, #96]	; (8001f98 <SystemInit+0xf8>)
+ 8001f38:	4a1b      	ldr	r2, [pc, #108]	; (8001fa8 <SystemInit+0x108>)
+ 8001f3a:	639a      	str	r2, [r3, #56]	; 0x38
+
+  /* Reset PLL2FRACR register */
+
+  RCC->PLL2FRACR = 0x00000000;
+ 8001f3c:	4b16      	ldr	r3, [pc, #88]	; (8001f98 <SystemInit+0xf8>)
+ 8001f3e:	2200      	movs	r2, #0
+ 8001f40:	63da      	str	r2, [r3, #60]	; 0x3c
+  /* Reset PLL3DIVR register */
+  RCC->PLL3DIVR = 0x01010280;
+ 8001f42:	4b15      	ldr	r3, [pc, #84]	; (8001f98 <SystemInit+0xf8>)
+ 8001f44:	4a18      	ldr	r2, [pc, #96]	; (8001fa8 <SystemInit+0x108>)
+ 8001f46:	641a      	str	r2, [r3, #64]	; 0x40
+
+  /* Reset PLL3FRACR register */
+  RCC->PLL3FRACR = 0x00000000;
+ 8001f48:	4b13      	ldr	r3, [pc, #76]	; (8001f98 <SystemInit+0xf8>)
+ 8001f4a:	2200      	movs	r2, #0
+ 8001f4c:	645a      	str	r2, [r3, #68]	; 0x44
+
+  /* Reset HSEBYP bit */
+  RCC->CR &= 0xFFFBFFFFU;
+ 8001f4e:	4b12      	ldr	r3, [pc, #72]	; (8001f98 <SystemInit+0xf8>)
+ 8001f50:	681b      	ldr	r3, [r3, #0]
+ 8001f52:	4a11      	ldr	r2, [pc, #68]	; (8001f98 <SystemInit+0xf8>)
+ 8001f54:	f423 2380 	bic.w	r3, r3, #262144	; 0x40000
+ 8001f58:	6013      	str	r3, [r2, #0]
+
+  /* Disable all interrupts */
+  RCC->CIER = 0x00000000;
+ 8001f5a:	4b0f      	ldr	r3, [pc, #60]	; (8001f98 <SystemInit+0xf8>)
+ 8001f5c:	2200      	movs	r2, #0
+ 8001f5e:	661a      	str	r2, [r3, #96]	; 0x60
+#if defined(DATA_IN_D2_SRAM)
+  /* in case of initialized data in D2 SRAM (AHB SRAM), enable the D2 SRAM clock (AHB SRAM clock) */
+#if defined(RCC_AHB2ENR_D2SRAM3EN)
+  RCC->AHB2ENR |= (RCC_AHB2ENR_D2SRAM1EN | RCC_AHB2ENR_D2SRAM2EN | RCC_AHB2ENR_D2SRAM3EN);
+#elif defined(RCC_AHB2ENR_D2SRAM2EN)
+  RCC->AHB2ENR |= (RCC_AHB2ENR_D2SRAM1EN | RCC_AHB2ENR_D2SRAM2EN);
+ 8001f60:	4b0d      	ldr	r3, [pc, #52]	; (8001f98 <SystemInit+0xf8>)
+ 8001f62:	f8d3 30dc 	ldr.w	r3, [r3, #220]	; 0xdc
+ 8001f66:	4a0c      	ldr	r2, [pc, #48]	; (8001f98 <SystemInit+0xf8>)
+ 8001f68:	f043 43c0 	orr.w	r3, r3, #1610612736	; 0x60000000
+ 8001f6c:	f8c2 30dc 	str.w	r3, [r2, #220]	; 0xdc
+#else
+  RCC->AHB2ENR |= (RCC_AHB2ENR_AHBSRAM1EN | RCC_AHB2ENR_AHBSRAM2EN);
+#endif /* RCC_AHB2ENR_D2SRAM3EN */
+
+  tmpreg = RCC->AHB2ENR;
+ 8001f70:	4b09      	ldr	r3, [pc, #36]	; (8001f98 <SystemInit+0xf8>)
+ 8001f72:	f8d3 30dc 	ldr.w	r3, [r3, #220]	; 0xdc
+ 8001f76:	607b      	str	r3, [r7, #4]
+  (void) tmpreg;
+ 8001f78:	687b      	ldr	r3, [r7, #4]
+  /*
+   * Disable the FMC bank1 (enabled after reset).
+   * This, prevents CPU speculation access on this bank which blocks the use of FMC during
+   * 24us. During this time the others FMC master (such as LTDC) cannot use it!
+   */
+  FMC_Bank1_R->BTCR[0] = 0x000030D2;
+ 8001f7a:	4b0c      	ldr	r3, [pc, #48]	; (8001fac <SystemInit+0x10c>)
+ 8001f7c:	f243 02d2 	movw	r2, #12498	; 0x30d2
+ 8001f80:	601a      	str	r2, [r3, #0]
+#if defined(USER_VECT_TAB_ADDRESS)
+  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal D1 AXI-RAM or in Internal FLASH */
+#endif /* USER_VECT_TAB_ADDRESS */
+
+#endif /*DUAL_CORE && CORE_CM4*/
+}
+ 8001f82:	bf00      	nop
+ 8001f84:	370c      	adds	r7, #12
+ 8001f86:	46bd      	mov	sp, r7
+ 8001f88:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8001f8c:	4770      	bx	lr
+ 8001f8e:	bf00      	nop
+ 8001f90:	e000ed00 	.word	0xe000ed00
+ 8001f94:	52002000 	.word	0x52002000
+ 8001f98:	58024400 	.word	0x58024400
+ 8001f9c:	eaf6ed7f 	.word	0xeaf6ed7f
+ 8001fa0:	02020200 	.word	0x02020200
+ 8001fa4:	01ff0000 	.word	0x01ff0000
+ 8001fa8:	01010280 	.word	0x01010280
+ 8001fac:	52004000 	.word	0x52004000
+
+08001fb0 <Reset_Handler>:
+
+    .section  .text.Reset_Handler
+  .weak  Reset_Handler
+  .type  Reset_Handler, %function
+Reset_Handler:
+  ldr   sp, =_estack      /* set stack pointer */
+ 8001fb0:	f8df d034 	ldr.w	sp, [pc, #52]	; 8001fe8 <LoopFillZerobss+0xe>
+
+/* Call the clock system initialization function.*/
+  bl  SystemInit
+ 8001fb4:	f7ff ff74 	bl	8001ea0 <SystemInit>
+
+/* Copy the data segment initializers from flash to SRAM */
+  ldr r0, =_sdata
+ 8001fb8:	480c      	ldr	r0, [pc, #48]	; (8001fec <LoopFillZerobss+0x12>)
+  ldr r1, =_edata
+ 8001fba:	490d      	ldr	r1, [pc, #52]	; (8001ff0 <LoopFillZerobss+0x16>)
+  ldr r2, =_sidata
+ 8001fbc:	4a0d      	ldr	r2, [pc, #52]	; (8001ff4 <LoopFillZerobss+0x1a>)
+  movs r3, #0
+ 8001fbe:	2300      	movs	r3, #0
+  b LoopCopyDataInit
+ 8001fc0:	e002      	b.n	8001fc8 <LoopCopyDataInit>
+
+08001fc2 <CopyDataInit>:
+
+CopyDataInit:
+  ldr r4, [r2, r3]
+ 8001fc2:	58d4      	ldr	r4, [r2, r3]
+  str r4, [r0, r3]
+ 8001fc4:	50c4      	str	r4, [r0, r3]
+  adds r3, r3, #4
+ 8001fc6:	3304      	adds	r3, #4
+
+08001fc8 <LoopCopyDataInit>:
+
+LoopCopyDataInit:
+  adds r4, r0, r3
+ 8001fc8:	18c4      	adds	r4, r0, r3
+  cmp r4, r1
+ 8001fca:	428c      	cmp	r4, r1
+  bcc CopyDataInit
+ 8001fcc:	d3f9      	bcc.n	8001fc2 <CopyDataInit>
+/* Zero fill the bss segment. */
+  ldr r2, =_sbss
+ 8001fce:	4a0a      	ldr	r2, [pc, #40]	; (8001ff8 <LoopFillZerobss+0x1e>)
+  ldr r4, =_ebss
+ 8001fd0:	4c0a      	ldr	r4, [pc, #40]	; (8001ffc <LoopFillZerobss+0x22>)
+  movs r3, #0
+ 8001fd2:	2300      	movs	r3, #0
+  b LoopFillZerobss
+ 8001fd4:	e001      	b.n	8001fda <LoopFillZerobss>
+
+08001fd6 <FillZerobss>:
+
+FillZerobss:
+  str  r3, [r2]
+ 8001fd6:	6013      	str	r3, [r2, #0]
+  adds r2, r2, #4
+ 8001fd8:	3204      	adds	r2, #4
+
+08001fda <LoopFillZerobss>:
+
+LoopFillZerobss:
+  cmp r2, r4
+ 8001fda:	42a2      	cmp	r2, r4
+  bcc FillZerobss
+ 8001fdc:	d3fb      	bcc.n	8001fd6 <FillZerobss>
+
+/* Call static constructors */
+    bl __libc_init_array
+ 8001fde:	f01f fedb 	bl	8021d98 <__libc_init_array>
+/* Call the application's entry point.*/
+  bl  main
+ 8001fe2:	f7fe fbff 	bl	80007e4 <main>
+  bx  lr
+ 8001fe6:	4770      	bx	lr
+  ldr   sp, =_estack      /* set stack pointer */
+ 8001fe8:	24050000 	.word	0x24050000
+  ldr r0, =_sdata
+ 8001fec:	24000000 	.word	0x24000000
+  ldr r1, =_edata
+ 8001ff0:	240000a4 	.word	0x240000a4
+  ldr r2, =_sidata
+ 8001ff4:	08026ef8 	.word	0x08026ef8
+  ldr r2, =_sbss
+ 8001ff8:	240000a4 	.word	0x240000a4
+  ldr r4, =_ebss
+ 8001ffc:	2401a730 	.word	0x2401a730
+
+08002000 <ADC3_IRQHandler>:
+ * @retval None
+*/
+    .section  .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+  b  Infinite_Loop
+ 8002000:	e7fe      	b.n	8002000 <ADC3_IRQHandler>
+
+08002002 <LAN8742_RegisterBusIO>:
+  * @param  ioctx: holds device IO functions.  
+  * @retval LAN8742_STATUS_OK  if OK
+  *         LAN8742_STATUS_ERROR if missing mandatory function
+  */
+int32_t  LAN8742_RegisterBusIO(lan8742_Object_t *pObj, lan8742_IOCtx_t *ioctx)
+{
+ 8002002:	b480      	push	{r7}
+ 8002004:	b083      	sub	sp, #12
+ 8002006:	af00      	add	r7, sp, #0
+ 8002008:	6078      	str	r0, [r7, #4]
+ 800200a:	6039      	str	r1, [r7, #0]
+  if(!pObj || !ioctx->ReadReg || !ioctx->WriteReg || !ioctx->GetTick)
+ 800200c:	687b      	ldr	r3, [r7, #4]
+ 800200e:	2b00      	cmp	r3, #0
+ 8002010:	d00b      	beq.n	800202a <LAN8742_RegisterBusIO+0x28>
+ 8002012:	683b      	ldr	r3, [r7, #0]
+ 8002014:	68db      	ldr	r3, [r3, #12]
+ 8002016:	2b00      	cmp	r3, #0
+ 8002018:	d007      	beq.n	800202a <LAN8742_RegisterBusIO+0x28>
+ 800201a:	683b      	ldr	r3, [r7, #0]
+ 800201c:	689b      	ldr	r3, [r3, #8]
+ 800201e:	2b00      	cmp	r3, #0
+ 8002020:	d003      	beq.n	800202a <LAN8742_RegisterBusIO+0x28>
+ 8002022:	683b      	ldr	r3, [r7, #0]
+ 8002024:	691b      	ldr	r3, [r3, #16]
+ 8002026:	2b00      	cmp	r3, #0
+ 8002028:	d102      	bne.n	8002030 <LAN8742_RegisterBusIO+0x2e>
+  {
+    return LAN8742_STATUS_ERROR;
+ 800202a:	f04f 33ff 	mov.w	r3, #4294967295
+ 800202e:	e014      	b.n	800205a <LAN8742_RegisterBusIO+0x58>
+  }
+  
+  pObj->IO.Init = ioctx->Init;
+ 8002030:	683b      	ldr	r3, [r7, #0]
+ 8002032:	681a      	ldr	r2, [r3, #0]
+ 8002034:	687b      	ldr	r3, [r7, #4]
+ 8002036:	609a      	str	r2, [r3, #8]
+  pObj->IO.DeInit = ioctx->DeInit;
+ 8002038:	683b      	ldr	r3, [r7, #0]
+ 800203a:	685a      	ldr	r2, [r3, #4]
+ 800203c:	687b      	ldr	r3, [r7, #4]
+ 800203e:	60da      	str	r2, [r3, #12]
+  pObj->IO.ReadReg = ioctx->ReadReg;
+ 8002040:	683b      	ldr	r3, [r7, #0]
+ 8002042:	68da      	ldr	r2, [r3, #12]
+ 8002044:	687b      	ldr	r3, [r7, #4]
+ 8002046:	615a      	str	r2, [r3, #20]
+  pObj->IO.WriteReg = ioctx->WriteReg;
+ 8002048:	683b      	ldr	r3, [r7, #0]
+ 800204a:	689a      	ldr	r2, [r3, #8]
+ 800204c:	687b      	ldr	r3, [r7, #4]
+ 800204e:	611a      	str	r2, [r3, #16]
+  pObj->IO.GetTick = ioctx->GetTick;
+ 8002050:	683b      	ldr	r3, [r7, #0]
+ 8002052:	691a      	ldr	r2, [r3, #16]
+ 8002054:	687b      	ldr	r3, [r7, #4]
+ 8002056:	619a      	str	r2, [r3, #24]
+  
+  return LAN8742_STATUS_OK;
+ 8002058:	2300      	movs	r3, #0
+}
+ 800205a:	4618      	mov	r0, r3
+ 800205c:	370c      	adds	r7, #12
+ 800205e:	46bd      	mov	sp, r7
+ 8002060:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8002064:	4770      	bx	lr
+
+08002066 <LAN8742_Init>:
+  *         LAN8742_STATUS_READ_ERROR if connot read register
+  *         LAN8742_STATUS_WRITE_ERROR if connot write to register
+  *         LAN8742_STATUS_RESET_TIMEOUT if cannot perform a software reset
+  */
+ int32_t LAN8742_Init(lan8742_Object_t *pObj)
+ {
+ 8002066:	b580      	push	{r7, lr}
+ 8002068:	b086      	sub	sp, #24
+ 800206a:	af00      	add	r7, sp, #0
+ 800206c:	6078      	str	r0, [r7, #4]
+   uint32_t tickstart = 0, regvalue = 0, addr = 0;
+ 800206e:	2300      	movs	r3, #0
+ 8002070:	60fb      	str	r3, [r7, #12]
+ 8002072:	2300      	movs	r3, #0
+ 8002074:	60bb      	str	r3, [r7, #8]
+ 8002076:	2300      	movs	r3, #0
+ 8002078:	617b      	str	r3, [r7, #20]
+   int32_t status = LAN8742_STATUS_OK;
+ 800207a:	2300      	movs	r3, #0
+ 800207c:	613b      	str	r3, [r7, #16]
+   
+   if(pObj->Is_Initialized == 0)
+ 800207e:	687b      	ldr	r3, [r7, #4]
+ 8002080:	685b      	ldr	r3, [r3, #4]
+ 8002082:	2b00      	cmp	r3, #0
+ 8002084:	d17c      	bne.n	8002180 <LAN8742_Init+0x11a>
+   {
+     if(pObj->IO.Init != 0)
+ 8002086:	687b      	ldr	r3, [r7, #4]
+ 8002088:	689b      	ldr	r3, [r3, #8]
+ 800208a:	2b00      	cmp	r3, #0
+ 800208c:	d002      	beq.n	8002094 <LAN8742_Init+0x2e>
+     {
+       /* GPIO and Clocks initialization */
+       pObj->IO.Init();
+ 800208e:	687b      	ldr	r3, [r7, #4]
+ 8002090:	689b      	ldr	r3, [r3, #8]
+ 8002092:	4798      	blx	r3
+     }
+   
+     /* for later check */
+     pObj->DevAddr = LAN8742_MAX_DEV_ADDR + 1;
+ 8002094:	687b      	ldr	r3, [r7, #4]
+ 8002096:	2220      	movs	r2, #32
+ 8002098:	601a      	str	r2, [r3, #0]
+   
+     /* Get the device address from special mode register */  
+     for(addr = 0; addr <= LAN8742_MAX_DEV_ADDR; addr ++)
+ 800209a:	2300      	movs	r3, #0
+ 800209c:	617b      	str	r3, [r7, #20]
+ 800209e:	e01c      	b.n	80020da <LAN8742_Init+0x74>
+     {
+       if(pObj->IO.ReadReg(addr, LAN8742_SMR, &regvalue) < 0)
+ 80020a0:	687b      	ldr	r3, [r7, #4]
+ 80020a2:	695b      	ldr	r3, [r3, #20]
+ 80020a4:	f107 0208 	add.w	r2, r7, #8
+ 80020a8:	2112      	movs	r1, #18
+ 80020aa:	6978      	ldr	r0, [r7, #20]
+ 80020ac:	4798      	blx	r3
+ 80020ae:	4603      	mov	r3, r0
+ 80020b0:	2b00      	cmp	r3, #0
+ 80020b2:	da03      	bge.n	80020bc <LAN8742_Init+0x56>
+       { 
+         status = LAN8742_STATUS_READ_ERROR;
+ 80020b4:	f06f 0304 	mvn.w	r3, #4
+ 80020b8:	613b      	str	r3, [r7, #16]
+         /* Can't read from this device address 
+            continue with next address */
+         continue;
+ 80020ba:	e00b      	b.n	80020d4 <LAN8742_Init+0x6e>
+       }
+     
+       if((regvalue & LAN8742_SMR_PHY_ADDR) == addr)
+ 80020bc:	68bb      	ldr	r3, [r7, #8]
+ 80020be:	f003 031f 	and.w	r3, r3, #31
+ 80020c2:	697a      	ldr	r2, [r7, #20]
+ 80020c4:	429a      	cmp	r2, r3
+ 80020c6:	d105      	bne.n	80020d4 <LAN8742_Init+0x6e>
+       {
+         pObj->DevAddr = addr;
+ 80020c8:	687b      	ldr	r3, [r7, #4]
+ 80020ca:	697a      	ldr	r2, [r7, #20]
+ 80020cc:	601a      	str	r2, [r3, #0]
+         status = LAN8742_STATUS_OK;
+ 80020ce:	2300      	movs	r3, #0
+ 80020d0:	613b      	str	r3, [r7, #16]
+         break;
+ 80020d2:	e005      	b.n	80020e0 <LAN8742_Init+0x7a>
+     for(addr = 0; addr <= LAN8742_MAX_DEV_ADDR; addr ++)
+ 80020d4:	697b      	ldr	r3, [r7, #20]
+ 80020d6:	3301      	adds	r3, #1
+ 80020d8:	617b      	str	r3, [r7, #20]
+ 80020da:	697b      	ldr	r3, [r7, #20]
+ 80020dc:	2b1f      	cmp	r3, #31
+ 80020de:	d9df      	bls.n	80020a0 <LAN8742_Init+0x3a>
+       }
+     }
+   
+     if(pObj->DevAddr > LAN8742_MAX_DEV_ADDR)
+ 80020e0:	687b      	ldr	r3, [r7, #4]
+ 80020e2:	681b      	ldr	r3, [r3, #0]
+ 80020e4:	2b1f      	cmp	r3, #31
+ 80020e6:	d902      	bls.n	80020ee <LAN8742_Init+0x88>
+     {
+       status = LAN8742_STATUS_ADDRESS_ERROR;
+ 80020e8:	f06f 0302 	mvn.w	r3, #2
+ 80020ec:	613b      	str	r3, [r7, #16]
+     }
+     
+     /* if device address is matched */
+     if(status == LAN8742_STATUS_OK)
+ 80020ee:	693b      	ldr	r3, [r7, #16]
+ 80020f0:	2b00      	cmp	r3, #0
+ 80020f2:	d145      	bne.n	8002180 <LAN8742_Init+0x11a>
+     {
+       /* set a software reset  */
+       if(pObj->IO.WriteReg(pObj->DevAddr, LAN8742_BCR, LAN8742_BCR_SOFT_RESET) >= 0)
+ 80020f4:	687b      	ldr	r3, [r7, #4]
+ 80020f6:	691b      	ldr	r3, [r3, #16]
+ 80020f8:	687a      	ldr	r2, [r7, #4]
+ 80020fa:	6810      	ldr	r0, [r2, #0]
+ 80020fc:	f44f 4200 	mov.w	r2, #32768	; 0x8000
+ 8002100:	2100      	movs	r1, #0
+ 8002102:	4798      	blx	r3
+ 8002104:	4603      	mov	r3, r0
+ 8002106:	2b00      	cmp	r3, #0
+ 8002108:	db37      	blt.n	800217a <LAN8742_Init+0x114>
+       { 
+         /* get software reset status */
+         if(pObj->IO.ReadReg(pObj->DevAddr, LAN8742_BCR, &regvalue) >= 0)
+ 800210a:	687b      	ldr	r3, [r7, #4]
+ 800210c:	695b      	ldr	r3, [r3, #20]
+ 800210e:	687a      	ldr	r2, [r7, #4]
+ 8002110:	6810      	ldr	r0, [r2, #0]
+ 8002112:	f107 0208 	add.w	r2, r7, #8
+ 8002116:	2100      	movs	r1, #0
+ 8002118:	4798      	blx	r3
+ 800211a:	4603      	mov	r3, r0
+ 800211c:	2b00      	cmp	r3, #0
+ 800211e:	db28      	blt.n	8002172 <LAN8742_Init+0x10c>
+         { 
+           tickstart = pObj->IO.GetTick();
+ 8002120:	687b      	ldr	r3, [r7, #4]
+ 8002122:	699b      	ldr	r3, [r3, #24]
+ 8002124:	4798      	blx	r3
+ 8002126:	4603      	mov	r3, r0
+ 8002128:	60fb      	str	r3, [r7, #12]
+           
+           /* wait until software reset is done or timeout occured  */
+           while(regvalue & LAN8742_BCR_SOFT_RESET)
+ 800212a:	e01c      	b.n	8002166 <LAN8742_Init+0x100>
+           {
+             if((pObj->IO.GetTick() - tickstart) <= LAN8742_SW_RESET_TO)
+ 800212c:	687b      	ldr	r3, [r7, #4]
+ 800212e:	699b      	ldr	r3, [r3, #24]
+ 8002130:	4798      	blx	r3
+ 8002132:	4603      	mov	r3, r0
+ 8002134:	461a      	mov	r2, r3
+ 8002136:	68fb      	ldr	r3, [r7, #12]
+ 8002138:	1ad3      	subs	r3, r2, r3
+ 800213a:	f5b3 7ffa 	cmp.w	r3, #500	; 0x1f4
+ 800213e:	d80e      	bhi.n	800215e <LAN8742_Init+0xf8>
+             {
+               if(pObj->IO.ReadReg(pObj->DevAddr, LAN8742_BCR, &regvalue) < 0)
+ 8002140:	687b      	ldr	r3, [r7, #4]
+ 8002142:	695b      	ldr	r3, [r3, #20]
+ 8002144:	687a      	ldr	r2, [r7, #4]
+ 8002146:	6810      	ldr	r0, [r2, #0]
+ 8002148:	f107 0208 	add.w	r2, r7, #8
+ 800214c:	2100      	movs	r1, #0
+ 800214e:	4798      	blx	r3
+ 8002150:	4603      	mov	r3, r0
+ 8002152:	2b00      	cmp	r3, #0
+ 8002154:	da07      	bge.n	8002166 <LAN8742_Init+0x100>
+               { 
+                 status = LAN8742_STATUS_READ_ERROR;
+ 8002156:	f06f 0304 	mvn.w	r3, #4
+ 800215a:	613b      	str	r3, [r7, #16]
+                 break;
+ 800215c:	e010      	b.n	8002180 <LAN8742_Init+0x11a>
+               }
+             }
+             else
+             {
+               status = LAN8742_STATUS_RESET_TIMEOUT;
+ 800215e:	f06f 0301 	mvn.w	r3, #1
+ 8002162:	613b      	str	r3, [r7, #16]
+               break;
+ 8002164:	e00c      	b.n	8002180 <LAN8742_Init+0x11a>
+           while(regvalue & LAN8742_BCR_SOFT_RESET)
+ 8002166:	68bb      	ldr	r3, [r7, #8]
+ 8002168:	f403 4300 	and.w	r3, r3, #32768	; 0x8000
+ 800216c:	2b00      	cmp	r3, #0
+ 800216e:	d1dd      	bne.n	800212c <LAN8742_Init+0xc6>
+ 8002170:	e006      	b.n	8002180 <LAN8742_Init+0x11a>
+             }
+           } 
+         }
+         else
+         {
+           status = LAN8742_STATUS_READ_ERROR;
+ 8002172:	f06f 0304 	mvn.w	r3, #4
+ 8002176:	613b      	str	r3, [r7, #16]
+ 8002178:	e002      	b.n	8002180 <LAN8742_Init+0x11a>
+         }
+       }
+       else
+       {
+         status = LAN8742_STATUS_WRITE_ERROR;
+ 800217a:	f06f 0303 	mvn.w	r3, #3
+ 800217e:	613b      	str	r3, [r7, #16]
+       }
+     }
+   }
+      
+   if(status == LAN8742_STATUS_OK)
+ 8002180:	693b      	ldr	r3, [r7, #16]
+ 8002182:	2b00      	cmp	r3, #0
+ 8002184:	d112      	bne.n	80021ac <LAN8742_Init+0x146>
+   {
+     tickstart =  pObj->IO.GetTick();
+ 8002186:	687b      	ldr	r3, [r7, #4]
+ 8002188:	699b      	ldr	r3, [r3, #24]
+ 800218a:	4798      	blx	r3
+ 800218c:	4603      	mov	r3, r0
+ 800218e:	60fb      	str	r3, [r7, #12]
+     
+     /* Wait for 2s to perform initialization */
+     while((pObj->IO.GetTick() - tickstart) <= LAN8742_INIT_TO)
+ 8002190:	bf00      	nop
+ 8002192:	687b      	ldr	r3, [r7, #4]
+ 8002194:	699b      	ldr	r3, [r3, #24]
+ 8002196:	4798      	blx	r3
+ 8002198:	4603      	mov	r3, r0
+ 800219a:	461a      	mov	r2, r3
+ 800219c:	68fb      	ldr	r3, [r7, #12]
+ 800219e:	1ad3      	subs	r3, r2, r3
+ 80021a0:	f5b3 6ffa 	cmp.w	r3, #2000	; 0x7d0
+ 80021a4:	d9f5      	bls.n	8002192 <LAN8742_Init+0x12c>
+     {
+     }
+     pObj->Is_Initialized = 1;
+ 80021a6:	687b      	ldr	r3, [r7, #4]
+ 80021a8:	2201      	movs	r2, #1
+ 80021aa:	605a      	str	r2, [r3, #4]
+   }
+   
+   return status;
+ 80021ac:	693b      	ldr	r3, [r7, #16]
+ }
+ 80021ae:	4618      	mov	r0, r3
+ 80021b0:	3718      	adds	r7, #24
+ 80021b2:	46bd      	mov	sp, r7
+ 80021b4:	bd80      	pop	{r7, pc}
+
+080021b6 <LAN8742_GetLinkState>:
+  *         LAN8742_STATUS_10MBITS_HALFDUPLEX  if 10Mb/s HD       
+  *         LAN8742_STATUS_READ_ERROR if connot read register
+  *         LAN8742_STATUS_WRITE_ERROR if connot write to register
+  */
+int32_t LAN8742_GetLinkState(lan8742_Object_t *pObj)
+{
+ 80021b6:	b580      	push	{r7, lr}
+ 80021b8:	b084      	sub	sp, #16
+ 80021ba:	af00      	add	r7, sp, #0
+ 80021bc:	6078      	str	r0, [r7, #4]
+  uint32_t readval = 0;
+ 80021be:	2300      	movs	r3, #0
+ 80021c0:	60fb      	str	r3, [r7, #12]
+  
+  /* Read Status register  */
+  if(pObj->IO.ReadReg(pObj->DevAddr, LAN8742_BSR, &readval) < 0)
+ 80021c2:	687b      	ldr	r3, [r7, #4]
+ 80021c4:	695b      	ldr	r3, [r3, #20]
+ 80021c6:	687a      	ldr	r2, [r7, #4]
+ 80021c8:	6810      	ldr	r0, [r2, #0]
+ 80021ca:	f107 020c 	add.w	r2, r7, #12
+ 80021ce:	2101      	movs	r1, #1
+ 80021d0:	4798      	blx	r3
+ 80021d2:	4603      	mov	r3, r0
+ 80021d4:	2b00      	cmp	r3, #0
+ 80021d6:	da02      	bge.n	80021de <LAN8742_GetLinkState+0x28>
+  {
+    return LAN8742_STATUS_READ_ERROR;
+ 80021d8:	f06f 0304 	mvn.w	r3, #4
+ 80021dc:	e06e      	b.n	80022bc <LAN8742_GetLinkState+0x106>
+  }
+  
+  /* Read Status register again */
+  if(pObj->IO.ReadReg(pObj->DevAddr, LAN8742_BSR, &readval) < 0)
+ 80021de:	687b      	ldr	r3, [r7, #4]
+ 80021e0:	695b      	ldr	r3, [r3, #20]
+ 80021e2:	687a      	ldr	r2, [r7, #4]
+ 80021e4:	6810      	ldr	r0, [r2, #0]
+ 80021e6:	f107 020c 	add.w	r2, r7, #12
+ 80021ea:	2101      	movs	r1, #1
+ 80021ec:	4798      	blx	r3
+ 80021ee:	4603      	mov	r3, r0
+ 80021f0:	2b00      	cmp	r3, #0
+ 80021f2:	da02      	bge.n	80021fa <LAN8742_GetLinkState+0x44>
+  {
+    return LAN8742_STATUS_READ_ERROR;
+ 80021f4:	f06f 0304 	mvn.w	r3, #4
+ 80021f8:	e060      	b.n	80022bc <LAN8742_GetLinkState+0x106>
+  }
+  
+  if((readval & LAN8742_BSR_LINK_STATUS) == 0)
+ 80021fa:	68fb      	ldr	r3, [r7, #12]
+ 80021fc:	f003 0304 	and.w	r3, r3, #4
+ 8002200:	2b00      	cmp	r3, #0
+ 8002202:	d101      	bne.n	8002208 <LAN8742_GetLinkState+0x52>
+  {
+    /* Return Link Down status */
+    return LAN8742_STATUS_LINK_DOWN;    
+ 8002204:	2301      	movs	r3, #1
+ 8002206:	e059      	b.n	80022bc <LAN8742_GetLinkState+0x106>
+  }
+  
+  /* Check Auto negotiaition */
+  if(pObj->IO.ReadReg(pObj->DevAddr, LAN8742_BCR, &readval) < 0)
+ 8002208:	687b      	ldr	r3, [r7, #4]
+ 800220a:	695b      	ldr	r3, [r3, #20]
+ 800220c:	687a      	ldr	r2, [r7, #4]
+ 800220e:	6810      	ldr	r0, [r2, #0]
+ 8002210:	f107 020c 	add.w	r2, r7, #12
+ 8002214:	2100      	movs	r1, #0
+ 8002216:	4798      	blx	r3
+ 8002218:	4603      	mov	r3, r0
+ 800221a:	2b00      	cmp	r3, #0
+ 800221c:	da02      	bge.n	8002224 <LAN8742_GetLinkState+0x6e>
+  {
+    return LAN8742_STATUS_READ_ERROR;
+ 800221e:	f06f 0304 	mvn.w	r3, #4
+ 8002222:	e04b      	b.n	80022bc <LAN8742_GetLinkState+0x106>
+  }
+  
+  if((readval & LAN8742_BCR_AUTONEGO_EN) != LAN8742_BCR_AUTONEGO_EN)
+ 8002224:	68fb      	ldr	r3, [r7, #12]
+ 8002226:	f403 5380 	and.w	r3, r3, #4096	; 0x1000
+ 800222a:	2b00      	cmp	r3, #0
+ 800222c:	d11b      	bne.n	8002266 <LAN8742_GetLinkState+0xb0>
+  {
+    if(((readval & LAN8742_BCR_SPEED_SELECT) == LAN8742_BCR_SPEED_SELECT) && ((readval & LAN8742_BCR_DUPLEX_MODE) == LAN8742_BCR_DUPLEX_MODE)) 
+ 800222e:	68fb      	ldr	r3, [r7, #12]
+ 8002230:	f403 5300 	and.w	r3, r3, #8192	; 0x2000
+ 8002234:	2b00      	cmp	r3, #0
+ 8002236:	d006      	beq.n	8002246 <LAN8742_GetLinkState+0x90>
+ 8002238:	68fb      	ldr	r3, [r7, #12]
+ 800223a:	f403 7380 	and.w	r3, r3, #256	; 0x100
+ 800223e:	2b00      	cmp	r3, #0
+ 8002240:	d001      	beq.n	8002246 <LAN8742_GetLinkState+0x90>
+    {
+      return LAN8742_STATUS_100MBITS_FULLDUPLEX;
+ 8002242:	2302      	movs	r3, #2
+ 8002244:	e03a      	b.n	80022bc <LAN8742_GetLinkState+0x106>
+    }
+    else if ((readval & LAN8742_BCR_SPEED_SELECT) == LAN8742_BCR_SPEED_SELECT)
+ 8002246:	68fb      	ldr	r3, [r7, #12]
+ 8002248:	f403 5300 	and.w	r3, r3, #8192	; 0x2000
+ 800224c:	2b00      	cmp	r3, #0
+ 800224e:	d001      	beq.n	8002254 <LAN8742_GetLinkState+0x9e>
+    {
+      return LAN8742_STATUS_100MBITS_HALFDUPLEX;
+ 8002250:	2303      	movs	r3, #3
+ 8002252:	e033      	b.n	80022bc <LAN8742_GetLinkState+0x106>
+    }        
+    else if ((readval & LAN8742_BCR_DUPLEX_MODE) == LAN8742_BCR_DUPLEX_MODE)
+ 8002254:	68fb      	ldr	r3, [r7, #12]
+ 8002256:	f403 7380 	and.w	r3, r3, #256	; 0x100
+ 800225a:	2b00      	cmp	r3, #0
+ 800225c:	d001      	beq.n	8002262 <LAN8742_GetLinkState+0xac>
+    {
+      return LAN8742_STATUS_10MBITS_FULLDUPLEX;
+ 800225e:	2304      	movs	r3, #4
+ 8002260:	e02c      	b.n	80022bc <LAN8742_GetLinkState+0x106>
+    }
+    else
+    {
+      return LAN8742_STATUS_10MBITS_HALFDUPLEX;
+ 8002262:	2305      	movs	r3, #5
+ 8002264:	e02a      	b.n	80022bc <LAN8742_GetLinkState+0x106>
+    }  		
+  }
+  else /* Auto Nego enabled */
+  {
+    if(pObj->IO.ReadReg(pObj->DevAddr, LAN8742_PHYSCSR, &readval) < 0)
+ 8002266:	687b      	ldr	r3, [r7, #4]
+ 8002268:	695b      	ldr	r3, [r3, #20]
+ 800226a:	687a      	ldr	r2, [r7, #4]
+ 800226c:	6810      	ldr	r0, [r2, #0]
+ 800226e:	f107 020c 	add.w	r2, r7, #12
+ 8002272:	211f      	movs	r1, #31
+ 8002274:	4798      	blx	r3
+ 8002276:	4603      	mov	r3, r0
+ 8002278:	2b00      	cmp	r3, #0
+ 800227a:	da02      	bge.n	8002282 <LAN8742_GetLinkState+0xcc>
+    {
+      return LAN8742_STATUS_READ_ERROR;
+ 800227c:	f06f 0304 	mvn.w	r3, #4
+ 8002280:	e01c      	b.n	80022bc <LAN8742_GetLinkState+0x106>
+    }
+    
+    /* Check if auto nego not done */
+    if((readval & LAN8742_PHYSCSR_AUTONEGO_DONE) == 0)
+ 8002282:	68fb      	ldr	r3, [r7, #12]
+ 8002284:	f403 5380 	and.w	r3, r3, #4096	; 0x1000
+ 8002288:	2b00      	cmp	r3, #0
+ 800228a:	d101      	bne.n	8002290 <LAN8742_GetLinkState+0xda>
+    {
+      return LAN8742_STATUS_AUTONEGO_NOTDONE;
+ 800228c:	2306      	movs	r3, #6
+ 800228e:	e015      	b.n	80022bc <LAN8742_GetLinkState+0x106>
+    }
+    
+    if((readval & LAN8742_PHYSCSR_HCDSPEEDMASK) == LAN8742_PHYSCSR_100BTX_FD)
+ 8002290:	68fb      	ldr	r3, [r7, #12]
+ 8002292:	f003 031c 	and.w	r3, r3, #28
+ 8002296:	2b18      	cmp	r3, #24
+ 8002298:	d101      	bne.n	800229e <LAN8742_GetLinkState+0xe8>
+    {
+      return LAN8742_STATUS_100MBITS_FULLDUPLEX;
+ 800229a:	2302      	movs	r3, #2
+ 800229c:	e00e      	b.n	80022bc <LAN8742_GetLinkState+0x106>
+    }
+    else if ((readval & LAN8742_PHYSCSR_HCDSPEEDMASK) == LAN8742_PHYSCSR_100BTX_HD)
+ 800229e:	68fb      	ldr	r3, [r7, #12]
+ 80022a0:	f003 031c 	and.w	r3, r3, #28
+ 80022a4:	2b08      	cmp	r3, #8
+ 80022a6:	d101      	bne.n	80022ac <LAN8742_GetLinkState+0xf6>
+    {
+      return LAN8742_STATUS_100MBITS_HALFDUPLEX;
+ 80022a8:	2303      	movs	r3, #3
+ 80022aa:	e007      	b.n	80022bc <LAN8742_GetLinkState+0x106>
+    }
+    else if ((readval & LAN8742_PHYSCSR_HCDSPEEDMASK) == LAN8742_PHYSCSR_10BT_FD)
+ 80022ac:	68fb      	ldr	r3, [r7, #12]
+ 80022ae:	f003 031c 	and.w	r3, r3, #28
+ 80022b2:	2b14      	cmp	r3, #20
+ 80022b4:	d101      	bne.n	80022ba <LAN8742_GetLinkState+0x104>
+    {
+      return LAN8742_STATUS_10MBITS_FULLDUPLEX;
+ 80022b6:	2304      	movs	r3, #4
+ 80022b8:	e000      	b.n	80022bc <LAN8742_GetLinkState+0x106>
+    }
+    else
+    {
+      return LAN8742_STATUS_10MBITS_HALFDUPLEX;
+ 80022ba:	2305      	movs	r3, #5
+    }				
+  }
+}
+ 80022bc:	4618      	mov	r0, r3
+ 80022be:	3710      	adds	r7, #16
+ 80022c0:	46bd      	mov	sp, r7
+ 80022c2:	bd80      	pop	{r7, pc}
+
+080022c4 <HAL_Init>:
+  *         need to ensure that the SysTick time base is always set to 1 millisecond
+  *         to have correct HAL operation.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_Init(void)
+{
+ 80022c4:	b580      	push	{r7, lr}
+ 80022c6:	b082      	sub	sp, #8
+ 80022c8:	af00      	add	r7, sp, #0
+   __HAL_ART_CONFIG_BASE_ADDRESS(0x08100000UL);  /* Configure the Cortex-M4 ART Base address to the Flash Bank 2 : */
+   __HAL_ART_ENABLE();                           /* Enable the Cortex-M4 ART */
+#endif /* DUAL_CORE &&  CORE_CM4 */
+
+  /* Set Interrupt Group Priority */
+  HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
+ 80022ca:	2003      	movs	r0, #3
+ 80022cc:	f000 f93b 	bl	8002546 <HAL_NVIC_SetPriorityGrouping>
+
+  /* Update the SystemCoreClock global variable */
+#if defined(RCC_D1CFGR_D1CPRE)
+  common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU);
+ 80022d0:	f005 fc9c 	bl	8007c0c <HAL_RCC_GetSysClockFreq>
+ 80022d4:	4602      	mov	r2, r0
+ 80022d6:	4b15      	ldr	r3, [pc, #84]	; (800232c <HAL_Init+0x68>)
+ 80022d8:	699b      	ldr	r3, [r3, #24]
+ 80022da:	0a1b      	lsrs	r3, r3, #8
+ 80022dc:	f003 030f 	and.w	r3, r3, #15
+ 80022e0:	4913      	ldr	r1, [pc, #76]	; (8002330 <HAL_Init+0x6c>)
+ 80022e2:	5ccb      	ldrb	r3, [r1, r3]
+ 80022e4:	f003 031f 	and.w	r3, r3, #31
+ 80022e8:	fa22 f303 	lsr.w	r3, r2, r3
+ 80022ec:	607b      	str	r3, [r7, #4]
+  common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos]) & 0x1FU);
+#endif
+
+  /* Update the SystemD2Clock global variable */
+#if defined(RCC_D1CFGR_HPRE)
+  SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
+ 80022ee:	4b0f      	ldr	r3, [pc, #60]	; (800232c <HAL_Init+0x68>)
+ 80022f0:	699b      	ldr	r3, [r3, #24]
+ 80022f2:	f003 030f 	and.w	r3, r3, #15
+ 80022f6:	4a0e      	ldr	r2, [pc, #56]	; (8002330 <HAL_Init+0x6c>)
+ 80022f8:	5cd3      	ldrb	r3, [r2, r3]
+ 80022fa:	f003 031f 	and.w	r3, r3, #31
+ 80022fe:	687a      	ldr	r2, [r7, #4]
+ 8002300:	fa22 f303 	lsr.w	r3, r2, r3
+ 8002304:	4a0b      	ldr	r2, [pc, #44]	; (8002334 <HAL_Init+0x70>)
+ 8002306:	6013      	str	r3, [r2, #0]
+#endif
+
+#if defined(DUAL_CORE) && defined(CORE_CM4)
+  SystemCoreClock = SystemD2Clock;
+#else
+  SystemCoreClock = common_system_clock;
+ 8002308:	4a0b      	ldr	r2, [pc, #44]	; (8002338 <HAL_Init+0x74>)
+ 800230a:	687b      	ldr	r3, [r7, #4]
+ 800230c:	6013      	str	r3, [r2, #0]
+#endif /* DUAL_CORE && CORE_CM4 */
+
+  /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
+  if(HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)
+ 800230e:	200f      	movs	r0, #15
+ 8002310:	f7ff fc46 	bl	8001ba0 <HAL_InitTick>
+ 8002314:	4603      	mov	r3, r0
+ 8002316:	2b00      	cmp	r3, #0
+ 8002318:	d001      	beq.n	800231e <HAL_Init+0x5a>
+  {
+    return HAL_ERROR;
+ 800231a:	2301      	movs	r3, #1
+ 800231c:	e002      	b.n	8002324 <HAL_Init+0x60>
+  }
+
+  /* Init the low level hardware */
+  HAL_MspInit();
+ 800231e:	f7ff f8ef 	bl	8001500 <HAL_MspInit>
+
+  /* Return function status */
+  return HAL_OK;
+ 8002322:	2300      	movs	r3, #0
+}
+ 8002324:	4618      	mov	r0, r3
+ 8002326:	3708      	adds	r7, #8
+ 8002328:	46bd      	mov	sp, r7
+ 800232a:	bd80      	pop	{r7, pc}
+ 800232c:	58024400 	.word	0x58024400
+ 8002330:	08026b40 	.word	0x08026b40
+ 8002334:	24000018 	.word	0x24000018
+ 8002338:	24000014 	.word	0x24000014
+
+0800233c <HAL_IncTick>:
+ * @note This function is declared as __weak to be overwritten in case of other
+  *      implementations in user file.
+  * @retval None
+  */
+__weak void HAL_IncTick(void)
+{
+ 800233c:	b480      	push	{r7}
+ 800233e:	af00      	add	r7, sp, #0
+  uwTick += (uint32_t)uwTickFreq;
+ 8002340:	4b06      	ldr	r3, [pc, #24]	; (800235c <HAL_IncTick+0x20>)
+ 8002342:	781b      	ldrb	r3, [r3, #0]
+ 8002344:	461a      	mov	r2, r3
+ 8002346:	4b06      	ldr	r3, [pc, #24]	; (8002360 <HAL_IncTick+0x24>)
+ 8002348:	681b      	ldr	r3, [r3, #0]
+ 800234a:	4413      	add	r3, r2
+ 800234c:	4a04      	ldr	r2, [pc, #16]	; (8002360 <HAL_IncTick+0x24>)
+ 800234e:	6013      	str	r3, [r2, #0]
+}
+ 8002350:	bf00      	nop
+ 8002352:	46bd      	mov	sp, r7
+ 8002354:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8002358:	4770      	bx	lr
+ 800235a:	bf00      	nop
+ 800235c:	24000020 	.word	0x24000020
+ 8002360:	240073d4 	.word	0x240073d4
+
+08002364 <HAL_GetTick>:
+  * @note This function is declared as __weak to be overwritten in case of other
+  *       implementations in user file.
+  * @retval tick value
+  */
+__weak uint32_t HAL_GetTick(void)
+{
+ 8002364:	b480      	push	{r7}
+ 8002366:	af00      	add	r7, sp, #0
+  return uwTick;
+ 8002368:	4b03      	ldr	r3, [pc, #12]	; (8002378 <HAL_GetTick+0x14>)
+ 800236a:	681b      	ldr	r3, [r3, #0]
+}
+ 800236c:	4618      	mov	r0, r3
+ 800236e:	46bd      	mov	sp, r7
+ 8002370:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8002374:	4770      	bx	lr
+ 8002376:	bf00      	nop
+ 8002378:	240073d4 	.word	0x240073d4
+
+0800237c <HAL_Delay>:
+  *       implementations in user file.
+  * @param Delay  specifies the delay time length, in milliseconds.
+  * @retval None
+  */
+__weak void HAL_Delay(uint32_t Delay)
+{
+ 800237c:	b580      	push	{r7, lr}
+ 800237e:	b084      	sub	sp, #16
+ 8002380:	af00      	add	r7, sp, #0
+ 8002382:	6078      	str	r0, [r7, #4]
+  uint32_t tickstart = HAL_GetTick();
+ 8002384:	f7ff ffee 	bl	8002364 <HAL_GetTick>
+ 8002388:	60b8      	str	r0, [r7, #8]
+  uint32_t wait = Delay;
+ 800238a:	687b      	ldr	r3, [r7, #4]
+ 800238c:	60fb      	str	r3, [r7, #12]
+
+  /* Add a freq to guarantee minimum wait */
+  if (wait < HAL_MAX_DELAY)
+ 800238e:	68fb      	ldr	r3, [r7, #12]
+ 8002390:	f1b3 3fff 	cmp.w	r3, #4294967295
+ 8002394:	d005      	beq.n	80023a2 <HAL_Delay+0x26>
+  {
+    wait += (uint32_t)(uwTickFreq);
+ 8002396:	4b0a      	ldr	r3, [pc, #40]	; (80023c0 <HAL_Delay+0x44>)
+ 8002398:	781b      	ldrb	r3, [r3, #0]
+ 800239a:	461a      	mov	r2, r3
+ 800239c:	68fb      	ldr	r3, [r7, #12]
+ 800239e:	4413      	add	r3, r2
+ 80023a0:	60fb      	str	r3, [r7, #12]
+  }
+
+  while ((HAL_GetTick() - tickstart) < wait)
+ 80023a2:	bf00      	nop
+ 80023a4:	f7ff ffde 	bl	8002364 <HAL_GetTick>
+ 80023a8:	4602      	mov	r2, r0
+ 80023aa:	68bb      	ldr	r3, [r7, #8]
+ 80023ac:	1ad3      	subs	r3, r2, r3
+ 80023ae:	68fa      	ldr	r2, [r7, #12]
+ 80023b0:	429a      	cmp	r2, r3
+ 80023b2:	d8f7      	bhi.n	80023a4 <HAL_Delay+0x28>
+  {
+  }
+}
+ 80023b4:	bf00      	nop
+ 80023b6:	bf00      	nop
+ 80023b8:	3710      	adds	r7, #16
+ 80023ba:	46bd      	mov	sp, r7
+ 80023bc:	bd80      	pop	{r7, pc}
+ 80023be:	bf00      	nop
+ 80023c0:	24000020 	.word	0x24000020
+
+080023c4 <HAL_SYSCFG_ETHInterfaceSelect>:
+  *   @arg SYSCFG_ETH_MII : Select the Media Independent Interface
+  *   @arg SYSCFG_ETH_RMII: Select the Reduced Media Independent Interface
+  * @retval None
+  */
+void HAL_SYSCFG_ETHInterfaceSelect(uint32_t SYSCFG_ETHInterface)
+{
+ 80023c4:	b480      	push	{r7}
+ 80023c6:	b083      	sub	sp, #12
+ 80023c8:	af00      	add	r7, sp, #0
+ 80023ca:	6078      	str	r0, [r7, #4]
+  /* Check the parameter */
+  assert_param(IS_SYSCFG_ETHERNET_CONFIG(SYSCFG_ETHInterface));
+
+  MODIFY_REG(SYSCFG->PMCR, SYSCFG_PMCR_EPIS_SEL, (uint32_t)(SYSCFG_ETHInterface));
+ 80023cc:	4b06      	ldr	r3, [pc, #24]	; (80023e8 <HAL_SYSCFG_ETHInterfaceSelect+0x24>)
+ 80023ce:	685b      	ldr	r3, [r3, #4]
+ 80023d0:	f423 0260 	bic.w	r2, r3, #14680064	; 0xe00000
+ 80023d4:	4904      	ldr	r1, [pc, #16]	; (80023e8 <HAL_SYSCFG_ETHInterfaceSelect+0x24>)
+ 80023d6:	687b      	ldr	r3, [r7, #4]
+ 80023d8:	4313      	orrs	r3, r2
+ 80023da:	604b      	str	r3, [r1, #4]
+}
+ 80023dc:	bf00      	nop
+ 80023de:	370c      	adds	r7, #12
+ 80023e0:	46bd      	mov	sp, r7
+ 80023e2:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 80023e6:	4770      	bx	lr
+ 80023e8:	58000400 	.word	0x58000400
+
+080023ec <__NVIC_SetPriorityGrouping>:
+{
+ 80023ec:	b480      	push	{r7}
+ 80023ee:	b085      	sub	sp, #20
+ 80023f0:	af00      	add	r7, sp, #0
+ 80023f2:	6078      	str	r0, [r7, #4]
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+ 80023f4:	687b      	ldr	r3, [r7, #4]
+ 80023f6:	f003 0307 	and.w	r3, r3, #7
+ 80023fa:	60fb      	str	r3, [r7, #12]
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+ 80023fc:	4b0b      	ldr	r3, [pc, #44]	; (800242c <__NVIC_SetPriorityGrouping+0x40>)
+ 80023fe:	68db      	ldr	r3, [r3, #12]
+ 8002400:	60bb      	str	r3, [r7, #8]
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
+ 8002402:	68ba      	ldr	r2, [r7, #8]
+ 8002404:	f64f 03ff 	movw	r3, #63743	; 0xf8ff
+ 8002408:	4013      	ands	r3, r2
+ 800240a:	60bb      	str	r3, [r7, #8]
+                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos)  );              /* Insert write key and priority group */
+ 800240c:	68fb      	ldr	r3, [r7, #12]
+ 800240e:	021a      	lsls	r2, r3, #8
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ 8002410:	68bb      	ldr	r3, [r7, #8]
+ 8002412:	431a      	orrs	r2, r3
+  reg_value  =  (reg_value                                   |
+ 8002414:	4b06      	ldr	r3, [pc, #24]	; (8002430 <__NVIC_SetPriorityGrouping+0x44>)
+ 8002416:	4313      	orrs	r3, r2
+ 8002418:	60bb      	str	r3, [r7, #8]
+  SCB->AIRCR =  reg_value;
+ 800241a:	4a04      	ldr	r2, [pc, #16]	; (800242c <__NVIC_SetPriorityGrouping+0x40>)
+ 800241c:	68bb      	ldr	r3, [r7, #8]
+ 800241e:	60d3      	str	r3, [r2, #12]
+}
+ 8002420:	bf00      	nop
+ 8002422:	3714      	adds	r7, #20
+ 8002424:	46bd      	mov	sp, r7
+ 8002426:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 800242a:	4770      	bx	lr
+ 800242c:	e000ed00 	.word	0xe000ed00
+ 8002430:	05fa0000 	.word	0x05fa0000
+
+08002434 <__NVIC_GetPriorityGrouping>:
+{
+ 8002434:	b480      	push	{r7}
+ 8002436:	af00      	add	r7, sp, #0
+  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+ 8002438:	4b04      	ldr	r3, [pc, #16]	; (800244c <__NVIC_GetPriorityGrouping+0x18>)
+ 800243a:	68db      	ldr	r3, [r3, #12]
+ 800243c:	0a1b      	lsrs	r3, r3, #8
+ 800243e:	f003 0307 	and.w	r3, r3, #7
+}
+ 8002442:	4618      	mov	r0, r3
+ 8002444:	46bd      	mov	sp, r7
+ 8002446:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 800244a:	4770      	bx	lr
+ 800244c:	e000ed00 	.word	0xe000ed00
+
+08002450 <__NVIC_EnableIRQ>:
+{
+ 8002450:	b480      	push	{r7}
+ 8002452:	b083      	sub	sp, #12
+ 8002454:	af00      	add	r7, sp, #0
+ 8002456:	4603      	mov	r3, r0
+ 8002458:	80fb      	strh	r3, [r7, #6]
+  if ((int32_t)(IRQn) >= 0)
+ 800245a:	f9b7 3006 	ldrsh.w	r3, [r7, #6]
+ 800245e:	2b00      	cmp	r3, #0
+ 8002460:	db0b      	blt.n	800247a <__NVIC_EnableIRQ+0x2a>
+    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ 8002462:	88fb      	ldrh	r3, [r7, #6]
+ 8002464:	f003 021f 	and.w	r2, r3, #31
+ 8002468:	4907      	ldr	r1, [pc, #28]	; (8002488 <__NVIC_EnableIRQ+0x38>)
+ 800246a:	f9b7 3006 	ldrsh.w	r3, [r7, #6]
+ 800246e:	095b      	lsrs	r3, r3, #5
+ 8002470:	2001      	movs	r0, #1
+ 8002472:	fa00 f202 	lsl.w	r2, r0, r2
+ 8002476:	f841 2023 	str.w	r2, [r1, r3, lsl #2]
+}
+ 800247a:	bf00      	nop
+ 800247c:	370c      	adds	r7, #12
+ 800247e:	46bd      	mov	sp, r7
+ 8002480:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8002484:	4770      	bx	lr
+ 8002486:	bf00      	nop
+ 8002488:	e000e100 	.word	0xe000e100
+
+0800248c <__NVIC_SetPriority>:
+{
+ 800248c:	b480      	push	{r7}
+ 800248e:	b083      	sub	sp, #12
+ 8002490:	af00      	add	r7, sp, #0
+ 8002492:	4603      	mov	r3, r0
+ 8002494:	6039      	str	r1, [r7, #0]
+ 8002496:	80fb      	strh	r3, [r7, #6]
+  if ((int32_t)(IRQn) >= 0)
+ 8002498:	f9b7 3006 	ldrsh.w	r3, [r7, #6]
+ 800249c:	2b00      	cmp	r3, #0
+ 800249e:	db0a      	blt.n	80024b6 <__NVIC_SetPriority+0x2a>
+    NVIC->IP[((uint32_t)IRQn)]                = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ 80024a0:	683b      	ldr	r3, [r7, #0]
+ 80024a2:	b2da      	uxtb	r2, r3
+ 80024a4:	490c      	ldr	r1, [pc, #48]	; (80024d8 <__NVIC_SetPriority+0x4c>)
+ 80024a6:	f9b7 3006 	ldrsh.w	r3, [r7, #6]
+ 80024aa:	0112      	lsls	r2, r2, #4
+ 80024ac:	b2d2      	uxtb	r2, r2
+ 80024ae:	440b      	add	r3, r1
+ 80024b0:	f883 2300 	strb.w	r2, [r3, #768]	; 0x300
+}
+ 80024b4:	e00a      	b.n	80024cc <__NVIC_SetPriority+0x40>
+    SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ 80024b6:	683b      	ldr	r3, [r7, #0]
+ 80024b8:	b2da      	uxtb	r2, r3
+ 80024ba:	4908      	ldr	r1, [pc, #32]	; (80024dc <__NVIC_SetPriority+0x50>)
+ 80024bc:	88fb      	ldrh	r3, [r7, #6]
+ 80024be:	f003 030f 	and.w	r3, r3, #15
+ 80024c2:	3b04      	subs	r3, #4
+ 80024c4:	0112      	lsls	r2, r2, #4
+ 80024c6:	b2d2      	uxtb	r2, r2
+ 80024c8:	440b      	add	r3, r1
+ 80024ca:	761a      	strb	r2, [r3, #24]
+}
+ 80024cc:	bf00      	nop
+ 80024ce:	370c      	adds	r7, #12
+ 80024d0:	46bd      	mov	sp, r7
+ 80024d2:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 80024d6:	4770      	bx	lr
+ 80024d8:	e000e100 	.word	0xe000e100
+ 80024dc:	e000ed00 	.word	0xe000ed00
+
+080024e0 <NVIC_EncodePriority>:
+{
+ 80024e0:	b480      	push	{r7}
+ 80024e2:	b089      	sub	sp, #36	; 0x24
+ 80024e4:	af00      	add	r7, sp, #0
+ 80024e6:	60f8      	str	r0, [r7, #12]
+ 80024e8:	60b9      	str	r1, [r7, #8]
+ 80024ea:	607a      	str	r2, [r7, #4]
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+ 80024ec:	68fb      	ldr	r3, [r7, #12]
+ 80024ee:	f003 0307 	and.w	r3, r3, #7
+ 80024f2:	61fb      	str	r3, [r7, #28]
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ 80024f4:	69fb      	ldr	r3, [r7, #28]
+ 80024f6:	f1c3 0307 	rsb	r3, r3, #7
+ 80024fa:	2b04      	cmp	r3, #4
+ 80024fc:	bf28      	it	cs
+ 80024fe:	2304      	movcs	r3, #4
+ 8002500:	61bb      	str	r3, [r7, #24]
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+ 8002502:	69fb      	ldr	r3, [r7, #28]
+ 8002504:	3304      	adds	r3, #4
+ 8002506:	2b06      	cmp	r3, #6
+ 8002508:	d902      	bls.n	8002510 <NVIC_EncodePriority+0x30>
+ 800250a:	69fb      	ldr	r3, [r7, #28]
+ 800250c:	3b03      	subs	r3, #3
+ 800250e:	e000      	b.n	8002512 <NVIC_EncodePriority+0x32>
+ 8002510:	2300      	movs	r3, #0
+ 8002512:	617b      	str	r3, [r7, #20]
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ 8002514:	f04f 32ff 	mov.w	r2, #4294967295
+ 8002518:	69bb      	ldr	r3, [r7, #24]
+ 800251a:	fa02 f303 	lsl.w	r3, r2, r3
+ 800251e:	43da      	mvns	r2, r3
+ 8002520:	68bb      	ldr	r3, [r7, #8]
+ 8002522:	401a      	ands	r2, r3
+ 8002524:	697b      	ldr	r3, [r7, #20]
+ 8002526:	409a      	lsls	r2, r3
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+ 8002528:	f04f 31ff 	mov.w	r1, #4294967295
+ 800252c:	697b      	ldr	r3, [r7, #20]
+ 800252e:	fa01 f303 	lsl.w	r3, r1, r3
+ 8002532:	43d9      	mvns	r1, r3
+ 8002534:	687b      	ldr	r3, [r7, #4]
+ 8002536:	400b      	ands	r3, r1
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ 8002538:	4313      	orrs	r3, r2
+}
+ 800253a:	4618      	mov	r0, r3
+ 800253c:	3724      	adds	r7, #36	; 0x24
+ 800253e:	46bd      	mov	sp, r7
+ 8002540:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8002544:	4770      	bx	lr
+
+08002546 <HAL_NVIC_SetPriorityGrouping>:
+  * @note   When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible.
+  *         The pending IRQ priority will be managed only by the subpriority.
+  * @retval None
+  */
+void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ 8002546:	b580      	push	{r7, lr}
+ 8002548:	b082      	sub	sp, #8
+ 800254a:	af00      	add	r7, sp, #0
+ 800254c:	6078      	str	r0, [r7, #4]
+  /* Check the parameters */
+  assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
+
+  /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
+  NVIC_SetPriorityGrouping(PriorityGroup);
+ 800254e:	6878      	ldr	r0, [r7, #4]
+ 8002550:	f7ff ff4c 	bl	80023ec <__NVIC_SetPriorityGrouping>
+}
+ 8002554:	bf00      	nop
+ 8002556:	3708      	adds	r7, #8
+ 8002558:	46bd      	mov	sp, r7
+ 800255a:	bd80      	pop	{r7, pc}
+
+0800255c <HAL_NVIC_SetPriority>:
+  *         This parameter can be a value between 0 and 15
+  *         A lower priority value indicates a higher priority.
+  * @retval None
+  */
+void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ 800255c:	b580      	push	{r7, lr}
+ 800255e:	b086      	sub	sp, #24
+ 8002560:	af00      	add	r7, sp, #0
+ 8002562:	4603      	mov	r3, r0
+ 8002564:	60b9      	str	r1, [r7, #8]
+ 8002566:	607a      	str	r2, [r7, #4]
+ 8002568:	81fb      	strh	r3, [r7, #14]
+
+  /* Check the parameters */
+  assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
+  assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
+
+  prioritygroup = NVIC_GetPriorityGrouping();
+ 800256a:	f7ff ff63 	bl	8002434 <__NVIC_GetPriorityGrouping>
+ 800256e:	6178      	str	r0, [r7, #20]
+
+  NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
+ 8002570:	687a      	ldr	r2, [r7, #4]
+ 8002572:	68b9      	ldr	r1, [r7, #8]
+ 8002574:	6978      	ldr	r0, [r7, #20]
+ 8002576:	f7ff ffb3 	bl	80024e0 <NVIC_EncodePriority>
+ 800257a:	4602      	mov	r2, r0
+ 800257c:	f9b7 300e 	ldrsh.w	r3, [r7, #14]
+ 8002580:	4611      	mov	r1, r2
+ 8002582:	4618      	mov	r0, r3
+ 8002584:	f7ff ff82 	bl	800248c <__NVIC_SetPriority>
+}
+ 8002588:	bf00      	nop
+ 800258a:	3718      	adds	r7, #24
+ 800258c:	46bd      	mov	sp, r7
+ 800258e:	bd80      	pop	{r7, pc}
+
+08002590 <HAL_NVIC_EnableIRQ>:
+  *         This parameter can be an enumerator of IRQn_Type enumeration
+  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h))
+  * @retval None
+  */
+void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ 8002590:	b580      	push	{r7, lr}
+ 8002592:	b082      	sub	sp, #8
+ 8002594:	af00      	add	r7, sp, #0
+ 8002596:	4603      	mov	r3, r0
+ 8002598:	80fb      	strh	r3, [r7, #6]
+  /* Check the parameters */
+  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+
+  /* Enable interrupt */
+  NVIC_EnableIRQ(IRQn);
+ 800259a:	f9b7 3006 	ldrsh.w	r3, [r7, #6]
+ 800259e:	4618      	mov	r0, r3
+ 80025a0:	f7ff ff56 	bl	8002450 <__NVIC_EnableIRQ>
+}
+ 80025a4:	bf00      	nop
+ 80025a6:	3708      	adds	r7, #8
+ 80025a8:	46bd      	mov	sp, r7
+ 80025aa:	bd80      	pop	{r7, pc}
+
+080025ac <HAL_MPU_Disable>:
+/**
+  * @brief  Disables the MPU
+  * @retval None
+  */
+void HAL_MPU_Disable(void)
+{
+ 80025ac:	b480      	push	{r7}
+ 80025ae:	af00      	add	r7, sp, #0
+  \details Ensures the apparent order of the explicit memory operations before
+           and after the instruction, without ensuring their completion.
+ */
+__STATIC_FORCEINLINE void __DMB(void)
+{
+  __ASM volatile ("dmb 0xF":::"memory");
+ 80025b0:	f3bf 8f5f 	dmb	sy
+}
+ 80025b4:	bf00      	nop
+  /* Make sure outstanding transfers are done */
+  __DMB();
+
+  /* Disable fault exceptions */
+  SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+ 80025b6:	4b07      	ldr	r3, [pc, #28]	; (80025d4 <HAL_MPU_Disable+0x28>)
+ 80025b8:	6a5b      	ldr	r3, [r3, #36]	; 0x24
+ 80025ba:	4a06      	ldr	r2, [pc, #24]	; (80025d4 <HAL_MPU_Disable+0x28>)
+ 80025bc:	f423 3380 	bic.w	r3, r3, #65536	; 0x10000
+ 80025c0:	6253      	str	r3, [r2, #36]	; 0x24
+
+  /* Disable the MPU and clear the control register*/
+  MPU->CTRL = 0;
+ 80025c2:	4b05      	ldr	r3, [pc, #20]	; (80025d8 <HAL_MPU_Disable+0x2c>)
+ 80025c4:	2200      	movs	r2, #0
+ 80025c6:	605a      	str	r2, [r3, #4]
+}
+ 80025c8:	bf00      	nop
+ 80025ca:	46bd      	mov	sp, r7
+ 80025cc:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 80025d0:	4770      	bx	lr
+ 80025d2:	bf00      	nop
+ 80025d4:	e000ed00 	.word	0xe000ed00
+ 80025d8:	e000ed90 	.word	0xe000ed90
+
+080025dc <HAL_MPU_Enable>:
+  *            @arg MPU_PRIVILEGED_DEFAULT
+  *            @arg MPU_HFNMI_PRIVDEF
+  * @retval None
+  */
+void HAL_MPU_Enable(uint32_t MPU_Control)
+{
+ 80025dc:	b480      	push	{r7}
+ 80025de:	b083      	sub	sp, #12
+ 80025e0:	af00      	add	r7, sp, #0
+ 80025e2:	6078      	str	r0, [r7, #4]
+  /* Enable the MPU */
+  MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+ 80025e4:	4a0b      	ldr	r2, [pc, #44]	; (8002614 <HAL_MPU_Enable+0x38>)
+ 80025e6:	687b      	ldr	r3, [r7, #4]
+ 80025e8:	f043 0301 	orr.w	r3, r3, #1
+ 80025ec:	6053      	str	r3, [r2, #4]
+
+  /* Enable fault exceptions */
+  SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+ 80025ee:	4b0a      	ldr	r3, [pc, #40]	; (8002618 <HAL_MPU_Enable+0x3c>)
+ 80025f0:	6a5b      	ldr	r3, [r3, #36]	; 0x24
+ 80025f2:	4a09      	ldr	r2, [pc, #36]	; (8002618 <HAL_MPU_Enable+0x3c>)
+ 80025f4:	f443 3380 	orr.w	r3, r3, #65536	; 0x10000
+ 80025f8:	6253      	str	r3, [r2, #36]	; 0x24
+  __ASM volatile ("dsb 0xF":::"memory");
+ 80025fa:	f3bf 8f4f 	dsb	sy
+}
+ 80025fe:	bf00      	nop
+  __ASM volatile ("isb 0xF":::"memory");
+ 8002600:	f3bf 8f6f 	isb	sy
+}
+ 8002604:	bf00      	nop
+
+  /* Ensure MPU setting take effects */
+  __DSB();
+  __ISB();
+}
+ 8002606:	bf00      	nop
+ 8002608:	370c      	adds	r7, #12
+ 800260a:	46bd      	mov	sp, r7
+ 800260c:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8002610:	4770      	bx	lr
+ 8002612:	bf00      	nop
+ 8002614:	e000ed90 	.word	0xe000ed90
+ 8002618:	e000ed00 	.word	0xe000ed00
+
+0800261c <HAL_MPU_ConfigRegion>:
+  * @param  MPU_Init Pointer to a MPU_Region_InitTypeDef structure that contains
+  *                  the initialization and configuration information.
+  * @retval None
+  */
+void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)
+{
+ 800261c:	b480      	push	{r7}
+ 800261e:	b083      	sub	sp, #12
+ 8002620:	af00      	add	r7, sp, #0
+ 8002622:	6078      	str	r0, [r7, #4]
+  /* Check the parameters */
+  assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number));
+  assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable));
+
+  /* Set the Region number */
+  MPU->RNR = MPU_Init->Number;
+ 8002624:	687b      	ldr	r3, [r7, #4]
+ 8002626:	785a      	ldrb	r2, [r3, #1]
+ 8002628:	4b1d      	ldr	r3, [pc, #116]	; (80026a0 <HAL_MPU_ConfigRegion+0x84>)
+ 800262a:	609a      	str	r2, [r3, #8]
+
+  if ((MPU_Init->Enable) != 0UL)
+ 800262c:	687b      	ldr	r3, [r7, #4]
+ 800262e:	781b      	ldrb	r3, [r3, #0]
+ 8002630:	2b00      	cmp	r3, #0
+ 8002632:	d029      	beq.n	8002688 <HAL_MPU_ConfigRegion+0x6c>
+    assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));
+    assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));
+    assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));
+    assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));
+
+    MPU->RBAR = MPU_Init->BaseAddress;
+ 8002634:	4a1a      	ldr	r2, [pc, #104]	; (80026a0 <HAL_MPU_ConfigRegion+0x84>)
+ 8002636:	687b      	ldr	r3, [r7, #4]
+ 8002638:	685b      	ldr	r3, [r3, #4]
+ 800263a:	60d3      	str	r3, [r2, #12]
+    MPU->RASR = ((uint32_t)MPU_Init->DisableExec             << MPU_RASR_XN_Pos)   |
+ 800263c:	687b      	ldr	r3, [r7, #4]
+ 800263e:	7b1b      	ldrb	r3, [r3, #12]
+ 8002640:	071a      	lsls	r2, r3, #28
+                ((uint32_t)MPU_Init->AccessPermission        << MPU_RASR_AP_Pos)   |
+ 8002642:	687b      	ldr	r3, [r7, #4]
+ 8002644:	7adb      	ldrb	r3, [r3, #11]
+ 8002646:	061b      	lsls	r3, r3, #24
+    MPU->RASR = ((uint32_t)MPU_Init->DisableExec             << MPU_RASR_XN_Pos)   |
+ 8002648:	431a      	orrs	r2, r3
+                ((uint32_t)MPU_Init->TypeExtField            << MPU_RASR_TEX_Pos)  |
+ 800264a:	687b      	ldr	r3, [r7, #4]
+ 800264c:	7a9b      	ldrb	r3, [r3, #10]
+ 800264e:	04db      	lsls	r3, r3, #19
+                ((uint32_t)MPU_Init->AccessPermission        << MPU_RASR_AP_Pos)   |
+ 8002650:	431a      	orrs	r2, r3
+                ((uint32_t)MPU_Init->IsShareable             << MPU_RASR_S_Pos)    |
+ 8002652:	687b      	ldr	r3, [r7, #4]
+ 8002654:	7b5b      	ldrb	r3, [r3, #13]
+ 8002656:	049b      	lsls	r3, r3, #18
+                ((uint32_t)MPU_Init->TypeExtField            << MPU_RASR_TEX_Pos)  |
+ 8002658:	431a      	orrs	r2, r3
+                ((uint32_t)MPU_Init->IsCacheable             << MPU_RASR_C_Pos)    |
+ 800265a:	687b      	ldr	r3, [r7, #4]
+ 800265c:	7b9b      	ldrb	r3, [r3, #14]
+ 800265e:	045b      	lsls	r3, r3, #17
+                ((uint32_t)MPU_Init->IsShareable             << MPU_RASR_S_Pos)    |
+ 8002660:	431a      	orrs	r2, r3
+                ((uint32_t)MPU_Init->IsBufferable            << MPU_RASR_B_Pos)    |
+ 8002662:	687b      	ldr	r3, [r7, #4]
+ 8002664:	7bdb      	ldrb	r3, [r3, #15]
+ 8002666:	041b      	lsls	r3, r3, #16
+                ((uint32_t)MPU_Init->IsCacheable             << MPU_RASR_C_Pos)    |
+ 8002668:	431a      	orrs	r2, r3
+                ((uint32_t)MPU_Init->SubRegionDisable        << MPU_RASR_SRD_Pos)  |
+ 800266a:	687b      	ldr	r3, [r7, #4]
+ 800266c:	7a5b      	ldrb	r3, [r3, #9]
+ 800266e:	021b      	lsls	r3, r3, #8
+                ((uint32_t)MPU_Init->IsBufferable            << MPU_RASR_B_Pos)    |
+ 8002670:	431a      	orrs	r2, r3
+                ((uint32_t)MPU_Init->Size                    << MPU_RASR_SIZE_Pos) |
+ 8002672:	687b      	ldr	r3, [r7, #4]
+ 8002674:	7a1b      	ldrb	r3, [r3, #8]
+ 8002676:	005b      	lsls	r3, r3, #1
+                ((uint32_t)MPU_Init->SubRegionDisable        << MPU_RASR_SRD_Pos)  |
+ 8002678:	4313      	orrs	r3, r2
+                ((uint32_t)MPU_Init->Enable                  << MPU_RASR_ENABLE_Pos);
+ 800267a:	687a      	ldr	r2, [r7, #4]
+ 800267c:	7812      	ldrb	r2, [r2, #0]
+ 800267e:	4611      	mov	r1, r2
+    MPU->RASR = ((uint32_t)MPU_Init->DisableExec             << MPU_RASR_XN_Pos)   |
+ 8002680:	4a07      	ldr	r2, [pc, #28]	; (80026a0 <HAL_MPU_ConfigRegion+0x84>)
+                ((uint32_t)MPU_Init->Size                    << MPU_RASR_SIZE_Pos) |
+ 8002682:	430b      	orrs	r3, r1
+    MPU->RASR = ((uint32_t)MPU_Init->DisableExec             << MPU_RASR_XN_Pos)   |
+ 8002684:	6113      	str	r3, [r2, #16]
+  else
+  {
+    MPU->RBAR = 0x00;
+    MPU->RASR = 0x00;
+  }
+}
+ 8002686:	e005      	b.n	8002694 <HAL_MPU_ConfigRegion+0x78>
+    MPU->RBAR = 0x00;
+ 8002688:	4b05      	ldr	r3, [pc, #20]	; (80026a0 <HAL_MPU_ConfigRegion+0x84>)
+ 800268a:	2200      	movs	r2, #0
+ 800268c:	60da      	str	r2, [r3, #12]
+    MPU->RASR = 0x00;
+ 800268e:	4b04      	ldr	r3, [pc, #16]	; (80026a0 <HAL_MPU_ConfigRegion+0x84>)
+ 8002690:	2200      	movs	r2, #0
+ 8002692:	611a      	str	r2, [r3, #16]
+}
+ 8002694:	bf00      	nop
+ 8002696:	370c      	adds	r7, #12
+ 8002698:	46bd      	mov	sp, r7
+ 800269a:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 800269e:	4770      	bx	lr
+ 80026a0:	e000ed90 	.word	0xe000ed90
+
+080026a4 <HAL_DMA_Init>:
+  * @param  hdma: Pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA Stream.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
+{
+ 80026a4:	b580      	push	{r7, lr}
+ 80026a6:	b086      	sub	sp, #24
+ 80026a8:	af00      	add	r7, sp, #0
+ 80026aa:	6078      	str	r0, [r7, #4]
+  uint32_t registerValue;
+  uint32_t tickstart = HAL_GetTick();
+ 80026ac:	f7ff fe5a 	bl	8002364 <HAL_GetTick>
+ 80026b0:	6138      	str	r0, [r7, #16]
+  DMA_Base_Registers *regs_dma;
+  BDMA_Base_Registers *regs_bdma;
+
+  /* Check the DMA peripheral handle */
+  if(hdma == NULL)
+ 80026b2:	687b      	ldr	r3, [r7, #4]
+ 80026b4:	2b00      	cmp	r3, #0
+ 80026b6:	d101      	bne.n	80026bc <HAL_DMA_Init+0x18>
+  {
+    return HAL_ERROR;
+ 80026b8:	2301      	movs	r3, #1
+ 80026ba:	e312      	b.n	8002ce2 <HAL_DMA_Init+0x63e>
+  assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment));
+  assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment));
+  assert_param(IS_DMA_MODE(hdma->Init.Mode));
+  assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));
+
+  if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
+ 80026bc:	687b      	ldr	r3, [r7, #4]
+ 80026be:	681b      	ldr	r3, [r3, #0]
+ 80026c0:	4a66      	ldr	r2, [pc, #408]	; (800285c <HAL_DMA_Init+0x1b8>)
+ 80026c2:	4293      	cmp	r3, r2
+ 80026c4:	d04a      	beq.n	800275c <HAL_DMA_Init+0xb8>
+ 80026c6:	687b      	ldr	r3, [r7, #4]
+ 80026c8:	681b      	ldr	r3, [r3, #0]
+ 80026ca:	4a65      	ldr	r2, [pc, #404]	; (8002860 <HAL_DMA_Init+0x1bc>)
+ 80026cc:	4293      	cmp	r3, r2
+ 80026ce:	d045      	beq.n	800275c <HAL_DMA_Init+0xb8>
+ 80026d0:	687b      	ldr	r3, [r7, #4]
+ 80026d2:	681b      	ldr	r3, [r3, #0]
+ 80026d4:	4a63      	ldr	r2, [pc, #396]	; (8002864 <HAL_DMA_Init+0x1c0>)
+ 80026d6:	4293      	cmp	r3, r2
+ 80026d8:	d040      	beq.n	800275c <HAL_DMA_Init+0xb8>
+ 80026da:	687b      	ldr	r3, [r7, #4]
+ 80026dc:	681b      	ldr	r3, [r3, #0]
+ 80026de:	4a62      	ldr	r2, [pc, #392]	; (8002868 <HAL_DMA_Init+0x1c4>)
+ 80026e0:	4293      	cmp	r3, r2
+ 80026e2:	d03b      	beq.n	800275c <HAL_DMA_Init+0xb8>
+ 80026e4:	687b      	ldr	r3, [r7, #4]
+ 80026e6:	681b      	ldr	r3, [r3, #0]
+ 80026e8:	4a60      	ldr	r2, [pc, #384]	; (800286c <HAL_DMA_Init+0x1c8>)
+ 80026ea:	4293      	cmp	r3, r2
+ 80026ec:	d036      	beq.n	800275c <HAL_DMA_Init+0xb8>
+ 80026ee:	687b      	ldr	r3, [r7, #4]
+ 80026f0:	681b      	ldr	r3, [r3, #0]
+ 80026f2:	4a5f      	ldr	r2, [pc, #380]	; (8002870 <HAL_DMA_Init+0x1cc>)
+ 80026f4:	4293      	cmp	r3, r2
+ 80026f6:	d031      	beq.n	800275c <HAL_DMA_Init+0xb8>
+ 80026f8:	687b      	ldr	r3, [r7, #4]
+ 80026fa:	681b      	ldr	r3, [r3, #0]
+ 80026fc:	4a5d      	ldr	r2, [pc, #372]	; (8002874 <HAL_DMA_Init+0x1d0>)
+ 80026fe:	4293      	cmp	r3, r2
+ 8002700:	d02c      	beq.n	800275c <HAL_DMA_Init+0xb8>
+ 8002702:	687b      	ldr	r3, [r7, #4]
+ 8002704:	681b      	ldr	r3, [r3, #0]
+ 8002706:	4a5c      	ldr	r2, [pc, #368]	; (8002878 <HAL_DMA_Init+0x1d4>)
+ 8002708:	4293      	cmp	r3, r2
+ 800270a:	d027      	beq.n	800275c <HAL_DMA_Init+0xb8>
+ 800270c:	687b      	ldr	r3, [r7, #4]
+ 800270e:	681b      	ldr	r3, [r3, #0]
+ 8002710:	4a5a      	ldr	r2, [pc, #360]	; (800287c <HAL_DMA_Init+0x1d8>)
+ 8002712:	4293      	cmp	r3, r2
+ 8002714:	d022      	beq.n	800275c <HAL_DMA_Init+0xb8>
+ 8002716:	687b      	ldr	r3, [r7, #4]
+ 8002718:	681b      	ldr	r3, [r3, #0]
+ 800271a:	4a59      	ldr	r2, [pc, #356]	; (8002880 <HAL_DMA_Init+0x1dc>)
+ 800271c:	4293      	cmp	r3, r2
+ 800271e:	d01d      	beq.n	800275c <HAL_DMA_Init+0xb8>
+ 8002720:	687b      	ldr	r3, [r7, #4]
+ 8002722:	681b      	ldr	r3, [r3, #0]
+ 8002724:	4a57      	ldr	r2, [pc, #348]	; (8002884 <HAL_DMA_Init+0x1e0>)
+ 8002726:	4293      	cmp	r3, r2
+ 8002728:	d018      	beq.n	800275c <HAL_DMA_Init+0xb8>
+ 800272a:	687b      	ldr	r3, [r7, #4]
+ 800272c:	681b      	ldr	r3, [r3, #0]
+ 800272e:	4a56      	ldr	r2, [pc, #344]	; (8002888 <HAL_DMA_Init+0x1e4>)
+ 8002730:	4293      	cmp	r3, r2
+ 8002732:	d013      	beq.n	800275c <HAL_DMA_Init+0xb8>
+ 8002734:	687b      	ldr	r3, [r7, #4]
+ 8002736:	681b      	ldr	r3, [r3, #0]
+ 8002738:	4a54      	ldr	r2, [pc, #336]	; (800288c <HAL_DMA_Init+0x1e8>)
+ 800273a:	4293      	cmp	r3, r2
+ 800273c:	d00e      	beq.n	800275c <HAL_DMA_Init+0xb8>
+ 800273e:	687b      	ldr	r3, [r7, #4]
+ 8002740:	681b      	ldr	r3, [r3, #0]
+ 8002742:	4a53      	ldr	r2, [pc, #332]	; (8002890 <HAL_DMA_Init+0x1ec>)
+ 8002744:	4293      	cmp	r3, r2
+ 8002746:	d009      	beq.n	800275c <HAL_DMA_Init+0xb8>
+ 8002748:	687b      	ldr	r3, [r7, #4]
+ 800274a:	681b      	ldr	r3, [r3, #0]
+ 800274c:	4a51      	ldr	r2, [pc, #324]	; (8002894 <HAL_DMA_Init+0x1f0>)
+ 800274e:	4293      	cmp	r3, r2
+ 8002750:	d004      	beq.n	800275c <HAL_DMA_Init+0xb8>
+ 8002752:	687b      	ldr	r3, [r7, #4]
+ 8002754:	681b      	ldr	r3, [r3, #0]
+ 8002756:	4a50      	ldr	r2, [pc, #320]	; (8002898 <HAL_DMA_Init+0x1f4>)
+ 8002758:	4293      	cmp	r3, r2
+ 800275a:	d101      	bne.n	8002760 <HAL_DMA_Init+0xbc>
+ 800275c:	2301      	movs	r3, #1
+ 800275e:	e000      	b.n	8002762 <HAL_DMA_Init+0xbe>
+ 8002760:	2300      	movs	r3, #0
+ 8002762:	2b00      	cmp	r3, #0
+ 8002764:	f000 813c 	beq.w	80029e0 <HAL_DMA_Init+0x33c>
+      assert_param(IS_DMA_MEMORY_BURST(hdma->Init.MemBurst));
+      assert_param(IS_DMA_PERIPHERAL_BURST(hdma->Init.PeriphBurst));
+    }
+
+    /* Change DMA peripheral state */
+    hdma->State = HAL_DMA_STATE_BUSY;
+ 8002768:	687b      	ldr	r3, [r7, #4]
+ 800276a:	2202      	movs	r2, #2
+ 800276c:	f883 2035 	strb.w	r2, [r3, #53]	; 0x35
+
+    /* Allocate lock resource */
+    __HAL_UNLOCK(hdma);
+ 8002770:	687b      	ldr	r3, [r7, #4]
+ 8002772:	2200      	movs	r2, #0
+ 8002774:	f883 2034 	strb.w	r2, [r3, #52]	; 0x34
+
+    /* Disable the peripheral */
+    __HAL_DMA_DISABLE(hdma);
+ 8002778:	687b      	ldr	r3, [r7, #4]
+ 800277a:	681b      	ldr	r3, [r3, #0]
+ 800277c:	4a37      	ldr	r2, [pc, #220]	; (800285c <HAL_DMA_Init+0x1b8>)
+ 800277e:	4293      	cmp	r3, r2
+ 8002780:	d04a      	beq.n	8002818 <HAL_DMA_Init+0x174>
+ 8002782:	687b      	ldr	r3, [r7, #4]
+ 8002784:	681b      	ldr	r3, [r3, #0]
+ 8002786:	4a36      	ldr	r2, [pc, #216]	; (8002860 <HAL_DMA_Init+0x1bc>)
+ 8002788:	4293      	cmp	r3, r2
+ 800278a:	d045      	beq.n	8002818 <HAL_DMA_Init+0x174>
+ 800278c:	687b      	ldr	r3, [r7, #4]
+ 800278e:	681b      	ldr	r3, [r3, #0]
+ 8002790:	4a34      	ldr	r2, [pc, #208]	; (8002864 <HAL_DMA_Init+0x1c0>)
+ 8002792:	4293      	cmp	r3, r2
+ 8002794:	d040      	beq.n	8002818 <HAL_DMA_Init+0x174>
+ 8002796:	687b      	ldr	r3, [r7, #4]
+ 8002798:	681b      	ldr	r3, [r3, #0]
+ 800279a:	4a33      	ldr	r2, [pc, #204]	; (8002868 <HAL_DMA_Init+0x1c4>)
+ 800279c:	4293      	cmp	r3, r2
+ 800279e:	d03b      	beq.n	8002818 <HAL_DMA_Init+0x174>
+ 80027a0:	687b      	ldr	r3, [r7, #4]
+ 80027a2:	681b      	ldr	r3, [r3, #0]
+ 80027a4:	4a31      	ldr	r2, [pc, #196]	; (800286c <HAL_DMA_Init+0x1c8>)
+ 80027a6:	4293      	cmp	r3, r2
+ 80027a8:	d036      	beq.n	8002818 <HAL_DMA_Init+0x174>
+ 80027aa:	687b      	ldr	r3, [r7, #4]
+ 80027ac:	681b      	ldr	r3, [r3, #0]
+ 80027ae:	4a30      	ldr	r2, [pc, #192]	; (8002870 <HAL_DMA_Init+0x1cc>)
+ 80027b0:	4293      	cmp	r3, r2
+ 80027b2:	d031      	beq.n	8002818 <HAL_DMA_Init+0x174>
+ 80027b4:	687b      	ldr	r3, [r7, #4]
+ 80027b6:	681b      	ldr	r3, [r3, #0]
+ 80027b8:	4a2e      	ldr	r2, [pc, #184]	; (8002874 <HAL_DMA_Init+0x1d0>)
+ 80027ba:	4293      	cmp	r3, r2
+ 80027bc:	d02c      	beq.n	8002818 <HAL_DMA_Init+0x174>
+ 80027be:	687b      	ldr	r3, [r7, #4]
+ 80027c0:	681b      	ldr	r3, [r3, #0]
+ 80027c2:	4a2d      	ldr	r2, [pc, #180]	; (8002878 <HAL_DMA_Init+0x1d4>)
+ 80027c4:	4293      	cmp	r3, r2
+ 80027c6:	d027      	beq.n	8002818 <HAL_DMA_Init+0x174>
+ 80027c8:	687b      	ldr	r3, [r7, #4]
+ 80027ca:	681b      	ldr	r3, [r3, #0]
+ 80027cc:	4a2b      	ldr	r2, [pc, #172]	; (800287c <HAL_DMA_Init+0x1d8>)
+ 80027ce:	4293      	cmp	r3, r2
+ 80027d0:	d022      	beq.n	8002818 <HAL_DMA_Init+0x174>
+ 80027d2:	687b      	ldr	r3, [r7, #4]
+ 80027d4:	681b      	ldr	r3, [r3, #0]
+ 80027d6:	4a2a      	ldr	r2, [pc, #168]	; (8002880 <HAL_DMA_Init+0x1dc>)
+ 80027d8:	4293      	cmp	r3, r2
+ 80027da:	d01d      	beq.n	8002818 <HAL_DMA_Init+0x174>
+ 80027dc:	687b      	ldr	r3, [r7, #4]
+ 80027de:	681b      	ldr	r3, [r3, #0]
+ 80027e0:	4a28      	ldr	r2, [pc, #160]	; (8002884 <HAL_DMA_Init+0x1e0>)
+ 80027e2:	4293      	cmp	r3, r2
+ 80027e4:	d018      	beq.n	8002818 <HAL_DMA_Init+0x174>
+ 80027e6:	687b      	ldr	r3, [r7, #4]
+ 80027e8:	681b      	ldr	r3, [r3, #0]
+ 80027ea:	4a27      	ldr	r2, [pc, #156]	; (8002888 <HAL_DMA_Init+0x1e4>)
+ 80027ec:	4293      	cmp	r3, r2
+ 80027ee:	d013      	beq.n	8002818 <HAL_DMA_Init+0x174>
+ 80027f0:	687b      	ldr	r3, [r7, #4]
+ 80027f2:	681b      	ldr	r3, [r3, #0]
+ 80027f4:	4a25      	ldr	r2, [pc, #148]	; (800288c <HAL_DMA_Init+0x1e8>)
+ 80027f6:	4293      	cmp	r3, r2
+ 80027f8:	d00e      	beq.n	8002818 <HAL_DMA_Init+0x174>
+ 80027fa:	687b      	ldr	r3, [r7, #4]
+ 80027fc:	681b      	ldr	r3, [r3, #0]
+ 80027fe:	4a24      	ldr	r2, [pc, #144]	; (8002890 <HAL_DMA_Init+0x1ec>)
+ 8002800:	4293      	cmp	r3, r2
+ 8002802:	d009      	beq.n	8002818 <HAL_DMA_Init+0x174>
+ 8002804:	687b      	ldr	r3, [r7, #4]
+ 8002806:	681b      	ldr	r3, [r3, #0]
+ 8002808:	4a22      	ldr	r2, [pc, #136]	; (8002894 <HAL_DMA_Init+0x1f0>)
+ 800280a:	4293      	cmp	r3, r2
+ 800280c:	d004      	beq.n	8002818 <HAL_DMA_Init+0x174>
+ 800280e:	687b      	ldr	r3, [r7, #4]
+ 8002810:	681b      	ldr	r3, [r3, #0]
+ 8002812:	4a21      	ldr	r2, [pc, #132]	; (8002898 <HAL_DMA_Init+0x1f4>)
+ 8002814:	4293      	cmp	r3, r2
+ 8002816:	d108      	bne.n	800282a <HAL_DMA_Init+0x186>
+ 8002818:	687b      	ldr	r3, [r7, #4]
+ 800281a:	681b      	ldr	r3, [r3, #0]
+ 800281c:	681a      	ldr	r2, [r3, #0]
+ 800281e:	687b      	ldr	r3, [r7, #4]
+ 8002820:	681b      	ldr	r3, [r3, #0]
+ 8002822:	f022 0201 	bic.w	r2, r2, #1
+ 8002826:	601a      	str	r2, [r3, #0]
+ 8002828:	e007      	b.n	800283a <HAL_DMA_Init+0x196>
+ 800282a:	687b      	ldr	r3, [r7, #4]
+ 800282c:	681b      	ldr	r3, [r3, #0]
+ 800282e:	681a      	ldr	r2, [r3, #0]
+ 8002830:	687b      	ldr	r3, [r7, #4]
+ 8002832:	681b      	ldr	r3, [r3, #0]
+ 8002834:	f022 0201 	bic.w	r2, r2, #1
+ 8002838:	601a      	str	r2, [r3, #0]
+
+    /* Check if the DMA Stream is effectively disabled */
+    while((((DMA_Stream_TypeDef   *)hdma->Instance)->CR & DMA_SxCR_EN) != 0U)
+ 800283a:	e02f      	b.n	800289c <HAL_DMA_Init+0x1f8>
+    {
+      /* Check for the Timeout */
+      if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT)
+ 800283c:	f7ff fd92 	bl	8002364 <HAL_GetTick>
+ 8002840:	4602      	mov	r2, r0
+ 8002842:	693b      	ldr	r3, [r7, #16]
+ 8002844:	1ad3      	subs	r3, r2, r3
+ 8002846:	2b05      	cmp	r3, #5
+ 8002848:	d928      	bls.n	800289c <HAL_DMA_Init+0x1f8>
+      {
+        /* Update error code */
+        hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
+ 800284a:	687b      	ldr	r3, [r7, #4]
+ 800284c:	2220      	movs	r2, #32
+ 800284e:	655a      	str	r2, [r3, #84]	; 0x54
+
+        /* Change the DMA state */
+        hdma->State = HAL_DMA_STATE_ERROR;
+ 8002850:	687b      	ldr	r3, [r7, #4]
+ 8002852:	2203      	movs	r2, #3
+ 8002854:	f883 2035 	strb.w	r2, [r3, #53]	; 0x35
+
+        return HAL_ERROR;
+ 8002858:	2301      	movs	r3, #1
+ 800285a:	e242      	b.n	8002ce2 <HAL_DMA_Init+0x63e>
+ 800285c:	40020010 	.word	0x40020010
+ 8002860:	40020028 	.word	0x40020028
+ 8002864:	40020040 	.word	0x40020040
+ 8002868:	40020058 	.word	0x40020058
+ 800286c:	40020070 	.word	0x40020070
+ 8002870:	40020088 	.word	0x40020088
+ 8002874:	400200a0 	.word	0x400200a0
+ 8002878:	400200b8 	.word	0x400200b8
+ 800287c:	40020410 	.word	0x40020410
+ 8002880:	40020428 	.word	0x40020428
+ 8002884:	40020440 	.word	0x40020440
+ 8002888:	40020458 	.word	0x40020458
+ 800288c:	40020470 	.word	0x40020470
+ 8002890:	40020488 	.word	0x40020488
+ 8002894:	400204a0 	.word	0x400204a0
+ 8002898:	400204b8 	.word	0x400204b8
+    while((((DMA_Stream_TypeDef   *)hdma->Instance)->CR & DMA_SxCR_EN) != 0U)
+ 800289c:	687b      	ldr	r3, [r7, #4]
+ 800289e:	681b      	ldr	r3, [r3, #0]
+ 80028a0:	681b      	ldr	r3, [r3, #0]
+ 80028a2:	f003 0301 	and.w	r3, r3, #1
+ 80028a6:	2b00      	cmp	r3, #0
+ 80028a8:	d1c8      	bne.n	800283c <HAL_DMA_Init+0x198>
+      }
+    }
+
+    /* Get the CR register value */
+    registerValue = ((DMA_Stream_TypeDef   *)hdma->Instance)->CR;
+ 80028aa:	687b      	ldr	r3, [r7, #4]
+ 80028ac:	681b      	ldr	r3, [r3, #0]
+ 80028ae:	681b      	ldr	r3, [r3, #0]
+ 80028b0:	617b      	str	r3, [r7, #20]
+
+    /* Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, CT and DBM bits */
+    registerValue &= ((uint32_t)~(DMA_SxCR_MBURST | DMA_SxCR_PBURST | \
+ 80028b2:	697a      	ldr	r2, [r7, #20]
+ 80028b4:	4b83      	ldr	r3, [pc, #524]	; (8002ac4 <HAL_DMA_Init+0x420>)
+ 80028b6:	4013      	ands	r3, r2
+ 80028b8:	617b      	str	r3, [r7, #20]
+                        DMA_SxCR_PL    | DMA_SxCR_MSIZE  | DMA_SxCR_PSIZE  | \
+                        DMA_SxCR_MINC  | DMA_SxCR_PINC   | DMA_SxCR_CIRC   | \
+                        DMA_SxCR_DIR   | DMA_SxCR_CT     | DMA_SxCR_DBM));
+
+    /* Prepare the DMA Stream configuration */
+    registerValue |=  hdma->Init.Direction           |
+ 80028ba:	687b      	ldr	r3, [r7, #4]
+ 80028bc:	689a      	ldr	r2, [r3, #8]
+            hdma->Init.PeriphInc           | hdma->Init.MemInc           |
+ 80028be:	687b      	ldr	r3, [r7, #4]
+ 80028c0:	68db      	ldr	r3, [r3, #12]
+    registerValue |=  hdma->Init.Direction           |
+ 80028c2:	431a      	orrs	r2, r3
+            hdma->Init.PeriphInc           | hdma->Init.MemInc           |
+ 80028c4:	687b      	ldr	r3, [r7, #4]
+ 80028c6:	691b      	ldr	r3, [r3, #16]
+ 80028c8:	431a      	orrs	r2, r3
+            hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
+ 80028ca:	687b      	ldr	r3, [r7, #4]
+ 80028cc:	695b      	ldr	r3, [r3, #20]
+            hdma->Init.PeriphInc           | hdma->Init.MemInc           |
+ 80028ce:	431a      	orrs	r2, r3
+            hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
+ 80028d0:	687b      	ldr	r3, [r7, #4]
+ 80028d2:	699b      	ldr	r3, [r3, #24]
+ 80028d4:	431a      	orrs	r2, r3
+            hdma->Init.Mode                | hdma->Init.Priority;
+ 80028d6:	687b      	ldr	r3, [r7, #4]
+ 80028d8:	69db      	ldr	r3, [r3, #28]
+            hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
+ 80028da:	431a      	orrs	r2, r3
+            hdma->Init.Mode                | hdma->Init.Priority;
+ 80028dc:	687b      	ldr	r3, [r7, #4]
+ 80028de:	6a1b      	ldr	r3, [r3, #32]
+ 80028e0:	4313      	orrs	r3, r2
+    registerValue |=  hdma->Init.Direction           |
+ 80028e2:	697a      	ldr	r2, [r7, #20]
+ 80028e4:	4313      	orrs	r3, r2
+ 80028e6:	617b      	str	r3, [r7, #20]
+
+    /* the Memory burst and peripheral burst are not used when the FIFO is disabled */
+    if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE)
+ 80028e8:	687b      	ldr	r3, [r7, #4]
+ 80028ea:	6a5b      	ldr	r3, [r3, #36]	; 0x24
+ 80028ec:	2b04      	cmp	r3, #4
+ 80028ee:	d107      	bne.n	8002900 <HAL_DMA_Init+0x25c>
+    {
+      /* Get memory burst and peripheral burst */
+      registerValue |=  hdma->Init.MemBurst | hdma->Init.PeriphBurst;
+ 80028f0:	687b      	ldr	r3, [r7, #4]
+ 80028f2:	6ada      	ldr	r2, [r3, #44]	; 0x2c
+ 80028f4:	687b      	ldr	r3, [r7, #4]
+ 80028f6:	6b1b      	ldr	r3, [r3, #48]	; 0x30
+ 80028f8:	4313      	orrs	r3, r2
+ 80028fa:	697a      	ldr	r2, [r7, #20]
+ 80028fc:	4313      	orrs	r3, r2
+ 80028fe:	617b      	str	r3, [r7, #20]
+                                    lock when transferring data to/from USART/UART */
+#if (STM32H7_DEV_ID == 0x450UL)
+    if((DBGMCU->IDCODE & 0xFFFF0000U) >= 0x20000000U)
+    {
+#endif /* STM32H7_DEV_ID == 0x450UL */
+      if(IS_DMA_UART_USART_REQUEST(hdma->Init.Request) != 0U)
+ 8002900:	687b      	ldr	r3, [r7, #4]
+ 8002902:	685b      	ldr	r3, [r3, #4]
+ 8002904:	2b28      	cmp	r3, #40	; 0x28
+ 8002906:	d903      	bls.n	8002910 <HAL_DMA_Init+0x26c>
+ 8002908:	687b      	ldr	r3, [r7, #4]
+ 800290a:	685b      	ldr	r3, [r3, #4]
+ 800290c:	2b2e      	cmp	r3, #46	; 0x2e
+ 800290e:	d91f      	bls.n	8002950 <HAL_DMA_Init+0x2ac>
+ 8002910:	687b      	ldr	r3, [r7, #4]
+ 8002912:	685b      	ldr	r3, [r3, #4]
+ 8002914:	2b3e      	cmp	r3, #62	; 0x3e
+ 8002916:	d903      	bls.n	8002920 <HAL_DMA_Init+0x27c>
+ 8002918:	687b      	ldr	r3, [r7, #4]
+ 800291a:	685b      	ldr	r3, [r3, #4]
+ 800291c:	2b42      	cmp	r3, #66	; 0x42
+ 800291e:	d917      	bls.n	8002950 <HAL_DMA_Init+0x2ac>
+ 8002920:	687b      	ldr	r3, [r7, #4]
+ 8002922:	685b      	ldr	r3, [r3, #4]
+ 8002924:	2b46      	cmp	r3, #70	; 0x46
+ 8002926:	d903      	bls.n	8002930 <HAL_DMA_Init+0x28c>
+ 8002928:	687b      	ldr	r3, [r7, #4]
+ 800292a:	685b      	ldr	r3, [r3, #4]
+ 800292c:	2b48      	cmp	r3, #72	; 0x48
+ 800292e:	d90f      	bls.n	8002950 <HAL_DMA_Init+0x2ac>
+ 8002930:	687b      	ldr	r3, [r7, #4]
+ 8002932:	685b      	ldr	r3, [r3, #4]
+ 8002934:	2b4e      	cmp	r3, #78	; 0x4e
+ 8002936:	d903      	bls.n	8002940 <HAL_DMA_Init+0x29c>
+ 8002938:	687b      	ldr	r3, [r7, #4]
+ 800293a:	685b      	ldr	r3, [r3, #4]
+ 800293c:	2b52      	cmp	r3, #82	; 0x52
+ 800293e:	d907      	bls.n	8002950 <HAL_DMA_Init+0x2ac>
+ 8002940:	687b      	ldr	r3, [r7, #4]
+ 8002942:	685b      	ldr	r3, [r3, #4]
+ 8002944:	2b73      	cmp	r3, #115	; 0x73
+ 8002946:	d905      	bls.n	8002954 <HAL_DMA_Init+0x2b0>
+ 8002948:	687b      	ldr	r3, [r7, #4]
+ 800294a:	685b      	ldr	r3, [r3, #4]
+ 800294c:	2b77      	cmp	r3, #119	; 0x77
+ 800294e:	d801      	bhi.n	8002954 <HAL_DMA_Init+0x2b0>
+ 8002950:	2301      	movs	r3, #1
+ 8002952:	e000      	b.n	8002956 <HAL_DMA_Init+0x2b2>
+ 8002954:	2300      	movs	r3, #0
+ 8002956:	2b00      	cmp	r3, #0
+ 8002958:	d003      	beq.n	8002962 <HAL_DMA_Init+0x2be>
+      {
+        registerValue |= DMA_SxCR_TRBUFF;
+ 800295a:	697b      	ldr	r3, [r7, #20]
+ 800295c:	f443 1380 	orr.w	r3, r3, #1048576	; 0x100000
+ 8002960:	617b      	str	r3, [r7, #20]
+#if (STM32H7_DEV_ID == 0x450UL)
+    }
+#endif /* STM32H7_DEV_ID == 0x450UL */
+
+    /* Write to DMA Stream CR register */
+    ((DMA_Stream_TypeDef   *)hdma->Instance)->CR = registerValue;
+ 8002962:	687b      	ldr	r3, [r7, #4]
+ 8002964:	681b      	ldr	r3, [r3, #0]
+ 8002966:	697a      	ldr	r2, [r7, #20]
+ 8002968:	601a      	str	r2, [r3, #0]
+
+    /* Get the FCR register value */
+    registerValue = ((DMA_Stream_TypeDef   *)hdma->Instance)->FCR;
+ 800296a:	687b      	ldr	r3, [r7, #4]
+ 800296c:	681b      	ldr	r3, [r3, #0]
+ 800296e:	695b      	ldr	r3, [r3, #20]
+ 8002970:	617b      	str	r3, [r7, #20]
+
+    /* Clear Direct mode and FIFO threshold bits */
+    registerValue &= (uint32_t)~(DMA_SxFCR_DMDIS | DMA_SxFCR_FTH);
+ 8002972:	697b      	ldr	r3, [r7, #20]
+ 8002974:	f023 0307 	bic.w	r3, r3, #7
+ 8002978:	617b      	str	r3, [r7, #20]
+
+    /* Prepare the DMA Stream FIFO configuration */
+    registerValue |= hdma->Init.FIFOMode;
+ 800297a:	687b      	ldr	r3, [r7, #4]
+ 800297c:	6a5b      	ldr	r3, [r3, #36]	; 0x24
+ 800297e:	697a      	ldr	r2, [r7, #20]
+ 8002980:	4313      	orrs	r3, r2
+ 8002982:	617b      	str	r3, [r7, #20]
+
+    /* the FIFO threshold is not used when the FIFO mode is disabled */
+    if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE)
+ 8002984:	687b      	ldr	r3, [r7, #4]
+ 8002986:	6a5b      	ldr	r3, [r3, #36]	; 0x24
+ 8002988:	2b04      	cmp	r3, #4
+ 800298a:	d117      	bne.n	80029bc <HAL_DMA_Init+0x318>
+    {
+      /* Get the FIFO threshold */
+      registerValue |= hdma->Init.FIFOThreshold;
+ 800298c:	687b      	ldr	r3, [r7, #4]
+ 800298e:	6a9b      	ldr	r3, [r3, #40]	; 0x28
+ 8002990:	697a      	ldr	r2, [r7, #20]
+ 8002992:	4313      	orrs	r3, r2
+ 8002994:	617b      	str	r3, [r7, #20]
+
+      /* Check compatibility between FIFO threshold level and size of the memory burst */
+      /* for INCR4, INCR8, INCR16 */
+      if(hdma->Init.MemBurst != DMA_MBURST_SINGLE)
+ 8002996:	687b      	ldr	r3, [r7, #4]
+ 8002998:	6adb      	ldr	r3, [r3, #44]	; 0x2c
+ 800299a:	2b00      	cmp	r3, #0
+ 800299c:	d00e      	beq.n	80029bc <HAL_DMA_Init+0x318>
+      {
+        if (DMA_CheckFifoParam(hdma) != HAL_OK)
+ 800299e:	6878      	ldr	r0, [r7, #4]
+ 80029a0:	f001 f9b4 	bl	8003d0c <DMA_CheckFifoParam>
+ 80029a4:	4603      	mov	r3, r0
+ 80029a6:	2b00      	cmp	r3, #0
+ 80029a8:	d008      	beq.n	80029bc <HAL_DMA_Init+0x318>
+        {
+          /* Update error code */
+          hdma->ErrorCode = HAL_DMA_ERROR_PARAM;
+ 80029aa:	687b      	ldr	r3, [r7, #4]
+ 80029ac:	2240      	movs	r2, #64	; 0x40
+ 80029ae:	655a      	str	r2, [r3, #84]	; 0x54
+
+          /* Change the DMA state */
+          hdma->State = HAL_DMA_STATE_READY;
+ 80029b0:	687b      	ldr	r3, [r7, #4]
+ 80029b2:	2201      	movs	r2, #1
+ 80029b4:	f883 2035 	strb.w	r2, [r3, #53]	; 0x35
+
+          return HAL_ERROR;
+ 80029b8:	2301      	movs	r3, #1
+ 80029ba:	e192      	b.n	8002ce2 <HAL_DMA_Init+0x63e>
+        }
+      }
+    }
+
+    /* Write to DMA Stream FCR */
+    ((DMA_Stream_TypeDef   *)hdma->Instance)->FCR = registerValue;
+ 80029bc:	687b      	ldr	r3, [r7, #4]
+ 80029be:	681b      	ldr	r3, [r3, #0]
+ 80029c0:	697a      	ldr	r2, [r7, #20]
+ 80029c2:	615a      	str	r2, [r3, #20]
+
+    /* Initialize StreamBaseAddress and StreamIndex parameters to be used to calculate
+       DMA steam Base Address needed by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */
+    regs_dma = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma);
+ 80029c4:	6878      	ldr	r0, [r7, #4]
+ 80029c6:	f001 f8ef 	bl	8003ba8 <DMA_CalcBaseAndBitshift>
+ 80029ca:	4603      	mov	r3, r0
+ 80029cc:	60bb      	str	r3, [r7, #8]
+
+    /* Clear all interrupt flags */
+    regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU);
+ 80029ce:	687b      	ldr	r3, [r7, #4]
+ 80029d0:	6ddb      	ldr	r3, [r3, #92]	; 0x5c
+ 80029d2:	f003 031f 	and.w	r3, r3, #31
+ 80029d6:	223f      	movs	r2, #63	; 0x3f
+ 80029d8:	409a      	lsls	r2, r3
+ 80029da:	68bb      	ldr	r3, [r7, #8]
+ 80029dc:	609a      	str	r2, [r3, #8]
+ 80029de:	e0c8      	b.n	8002b72 <HAL_DMA_Init+0x4ce>
+  }
+  else if(IS_BDMA_CHANNEL_INSTANCE(hdma->Instance) != 0U) /* BDMA instance(s) */
+ 80029e0:	687b      	ldr	r3, [r7, #4]
+ 80029e2:	681b      	ldr	r3, [r3, #0]
+ 80029e4:	4a38      	ldr	r2, [pc, #224]	; (8002ac8 <HAL_DMA_Init+0x424>)
+ 80029e6:	4293      	cmp	r3, r2
+ 80029e8:	d022      	beq.n	8002a30 <HAL_DMA_Init+0x38c>
+ 80029ea:	687b      	ldr	r3, [r7, #4]
+ 80029ec:	681b      	ldr	r3, [r3, #0]
+ 80029ee:	4a37      	ldr	r2, [pc, #220]	; (8002acc <HAL_DMA_Init+0x428>)
+ 80029f0:	4293      	cmp	r3, r2
+ 80029f2:	d01d      	beq.n	8002a30 <HAL_DMA_Init+0x38c>
+ 80029f4:	687b      	ldr	r3, [r7, #4]
+ 80029f6:	681b      	ldr	r3, [r3, #0]
+ 80029f8:	4a35      	ldr	r2, [pc, #212]	; (8002ad0 <HAL_DMA_Init+0x42c>)
+ 80029fa:	4293      	cmp	r3, r2
+ 80029fc:	d018      	beq.n	8002a30 <HAL_DMA_Init+0x38c>
+ 80029fe:	687b      	ldr	r3, [r7, #4]
+ 8002a00:	681b      	ldr	r3, [r3, #0]
+ 8002a02:	4a34      	ldr	r2, [pc, #208]	; (8002ad4 <HAL_DMA_Init+0x430>)
+ 8002a04:	4293      	cmp	r3, r2
+ 8002a06:	d013      	beq.n	8002a30 <HAL_DMA_Init+0x38c>
+ 8002a08:	687b      	ldr	r3, [r7, #4]
+ 8002a0a:	681b      	ldr	r3, [r3, #0]
+ 8002a0c:	4a32      	ldr	r2, [pc, #200]	; (8002ad8 <HAL_DMA_Init+0x434>)
+ 8002a0e:	4293      	cmp	r3, r2
+ 8002a10:	d00e      	beq.n	8002a30 <HAL_DMA_Init+0x38c>
+ 8002a12:	687b      	ldr	r3, [r7, #4]
+ 8002a14:	681b      	ldr	r3, [r3, #0]
+ 8002a16:	4a31      	ldr	r2, [pc, #196]	; (8002adc <HAL_DMA_Init+0x438>)
+ 8002a18:	4293      	cmp	r3, r2
+ 8002a1a:	d009      	beq.n	8002a30 <HAL_DMA_Init+0x38c>
+ 8002a1c:	687b      	ldr	r3, [r7, #4]
+ 8002a1e:	681b      	ldr	r3, [r3, #0]
+ 8002a20:	4a2f      	ldr	r2, [pc, #188]	; (8002ae0 <HAL_DMA_Init+0x43c>)
+ 8002a22:	4293      	cmp	r3, r2
+ 8002a24:	d004      	beq.n	8002a30 <HAL_DMA_Init+0x38c>
+ 8002a26:	687b      	ldr	r3, [r7, #4]
+ 8002a28:	681b      	ldr	r3, [r3, #0]
+ 8002a2a:	4a2e      	ldr	r2, [pc, #184]	; (8002ae4 <HAL_DMA_Init+0x440>)
+ 8002a2c:	4293      	cmp	r3, r2
+ 8002a2e:	d101      	bne.n	8002a34 <HAL_DMA_Init+0x390>
+ 8002a30:	2301      	movs	r3, #1
+ 8002a32:	e000      	b.n	8002a36 <HAL_DMA_Init+0x392>
+ 8002a34:	2300      	movs	r3, #0
+ 8002a36:	2b00      	cmp	r3, #0
+ 8002a38:	f000 8092 	beq.w	8002b60 <HAL_DMA_Init+0x4bc>
+  {
+    if(IS_BDMA_CHANNEL_DMAMUX_INSTANCE(hdma->Instance) != 0U)
+ 8002a3c:	687b      	ldr	r3, [r7, #4]
+ 8002a3e:	681b      	ldr	r3, [r3, #0]
+ 8002a40:	4a21      	ldr	r2, [pc, #132]	; (8002ac8 <HAL_DMA_Init+0x424>)
+ 8002a42:	4293      	cmp	r3, r2
+ 8002a44:	d021      	beq.n	8002a8a <HAL_DMA_Init+0x3e6>
+ 8002a46:	687b      	ldr	r3, [r7, #4]
+ 8002a48:	681b      	ldr	r3, [r3, #0]
+ 8002a4a:	4a20      	ldr	r2, [pc, #128]	; (8002acc <HAL_DMA_Init+0x428>)
+ 8002a4c:	4293      	cmp	r3, r2
+ 8002a4e:	d01c      	beq.n	8002a8a <HAL_DMA_Init+0x3e6>
+ 8002a50:	687b      	ldr	r3, [r7, #4]
+ 8002a52:	681b      	ldr	r3, [r3, #0]
+ 8002a54:	4a1e      	ldr	r2, [pc, #120]	; (8002ad0 <HAL_DMA_Init+0x42c>)
+ 8002a56:	4293      	cmp	r3, r2
+ 8002a58:	d017      	beq.n	8002a8a <HAL_DMA_Init+0x3e6>
+ 8002a5a:	687b      	ldr	r3, [r7, #4]
+ 8002a5c:	681b      	ldr	r3, [r3, #0]
+ 8002a5e:	4a1d      	ldr	r2, [pc, #116]	; (8002ad4 <HAL_DMA_Init+0x430>)
+ 8002a60:	4293      	cmp	r3, r2
+ 8002a62:	d012      	beq.n	8002a8a <HAL_DMA_Init+0x3e6>
+ 8002a64:	687b      	ldr	r3, [r7, #4]
+ 8002a66:	681b      	ldr	r3, [r3, #0]
+ 8002a68:	4a1b      	ldr	r2, [pc, #108]	; (8002ad8 <HAL_DMA_Init+0x434>)
+ 8002a6a:	4293      	cmp	r3, r2
+ 8002a6c:	d00d      	beq.n	8002a8a <HAL_DMA_Init+0x3e6>
+ 8002a6e:	687b      	ldr	r3, [r7, #4]
+ 8002a70:	681b      	ldr	r3, [r3, #0]
+ 8002a72:	4a1a      	ldr	r2, [pc, #104]	; (8002adc <HAL_DMA_Init+0x438>)
+ 8002a74:	4293      	cmp	r3, r2
+ 8002a76:	d008      	beq.n	8002a8a <HAL_DMA_Init+0x3e6>
+ 8002a78:	687b      	ldr	r3, [r7, #4]
+ 8002a7a:	681b      	ldr	r3, [r3, #0]
+ 8002a7c:	4a18      	ldr	r2, [pc, #96]	; (8002ae0 <HAL_DMA_Init+0x43c>)
+ 8002a7e:	4293      	cmp	r3, r2
+ 8002a80:	d003      	beq.n	8002a8a <HAL_DMA_Init+0x3e6>
+ 8002a82:	687b      	ldr	r3, [r7, #4]
+ 8002a84:	681b      	ldr	r3, [r3, #0]
+ 8002a86:	4a17      	ldr	r2, [pc, #92]	; (8002ae4 <HAL_DMA_Init+0x440>)
+ 8002a88:	4293      	cmp	r3, r2
+      /* Check the request parameter */
+      assert_param(IS_BDMA_REQUEST(hdma->Init.Request));
+    }
+
+    /* Change DMA peripheral state */
+    hdma->State = HAL_DMA_STATE_BUSY;
+ 8002a8a:	687b      	ldr	r3, [r7, #4]
+ 8002a8c:	2202      	movs	r2, #2
+ 8002a8e:	f883 2035 	strb.w	r2, [r3, #53]	; 0x35
+
+    /* Allocate lock resource */
+    __HAL_UNLOCK(hdma);
+ 8002a92:	687b      	ldr	r3, [r7, #4]
+ 8002a94:	2200      	movs	r2, #0
+ 8002a96:	f883 2034 	strb.w	r2, [r3, #52]	; 0x34
+
+    /* Get the CR register value */
+    registerValue = ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR;
+ 8002a9a:	687b      	ldr	r3, [r7, #4]
+ 8002a9c:	681b      	ldr	r3, [r3, #0]
+ 8002a9e:	681b      	ldr	r3, [r3, #0]
+ 8002aa0:	617b      	str	r3, [r7, #20]
+
+    /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, MEM2MEM, DBM and CT bits */
+    registerValue &= ((uint32_t)~(BDMA_CCR_PL    | BDMA_CCR_MSIZE   | BDMA_CCR_PSIZE  | \
+ 8002aa2:	697a      	ldr	r2, [r7, #20]
+ 8002aa4:	4b10      	ldr	r3, [pc, #64]	; (8002ae8 <HAL_DMA_Init+0x444>)
+ 8002aa6:	4013      	ands	r3, r2
+ 8002aa8:	617b      	str	r3, [r7, #20]
+                                  BDMA_CCR_MINC  | BDMA_CCR_PINC    | BDMA_CCR_CIRC   | \
+                                  BDMA_CCR_DIR   | BDMA_CCR_MEM2MEM | BDMA_CCR_DBM    | \
+                                  BDMA_CCR_CT));
+
+    /* Prepare the DMA Channel configuration */
+    registerValue |=  DMA_TO_BDMA_DIRECTION(hdma->Init.Direction)            |
+ 8002aaa:	687b      	ldr	r3, [r7, #4]
+ 8002aac:	689b      	ldr	r3, [r3, #8]
+ 8002aae:	2b40      	cmp	r3, #64	; 0x40
+ 8002ab0:	d01c      	beq.n	8002aec <HAL_DMA_Init+0x448>
+ 8002ab2:	687b      	ldr	r3, [r7, #4]
+ 8002ab4:	689b      	ldr	r3, [r3, #8]
+ 8002ab6:	2b80      	cmp	r3, #128	; 0x80
+ 8002ab8:	d102      	bne.n	8002ac0 <HAL_DMA_Init+0x41c>
+ 8002aba:	f44f 4380 	mov.w	r3, #16384	; 0x4000
+ 8002abe:	e016      	b.n	8002aee <HAL_DMA_Init+0x44a>
+ 8002ac0:	2300      	movs	r3, #0
+ 8002ac2:	e014      	b.n	8002aee <HAL_DMA_Init+0x44a>
+ 8002ac4:	fe10803f 	.word	0xfe10803f
+ 8002ac8:	58025408 	.word	0x58025408
+ 8002acc:	5802541c 	.word	0x5802541c
+ 8002ad0:	58025430 	.word	0x58025430
+ 8002ad4:	58025444 	.word	0x58025444
+ 8002ad8:	58025458 	.word	0x58025458
+ 8002adc:	5802546c 	.word	0x5802546c
+ 8002ae0:	58025480 	.word	0x58025480
+ 8002ae4:	58025494 	.word	0x58025494
+ 8002ae8:	fffe000f 	.word	0xfffe000f
+ 8002aec:	2310      	movs	r3, #16
+                      DMA_TO_BDMA_PERIPHERAL_INC(hdma->Init.PeriphInc)       |
+ 8002aee:	687a      	ldr	r2, [r7, #4]
+ 8002af0:	68d2      	ldr	r2, [r2, #12]
+ 8002af2:	08d2      	lsrs	r2, r2, #3
+    registerValue |=  DMA_TO_BDMA_DIRECTION(hdma->Init.Direction)            |
+ 8002af4:	431a      	orrs	r2, r3
+                      DMA_TO_BDMA_MEMORY_INC(hdma->Init.MemInc)              |
+ 8002af6:	687b      	ldr	r3, [r7, #4]
+ 8002af8:	691b      	ldr	r3, [r3, #16]
+ 8002afa:	08db      	lsrs	r3, r3, #3
+                      DMA_TO_BDMA_PERIPHERAL_INC(hdma->Init.PeriphInc)       |
+ 8002afc:	431a      	orrs	r2, r3
+                      DMA_TO_BDMA_PDATA_SIZE(hdma->Init.PeriphDataAlignment) |
+ 8002afe:	687b      	ldr	r3, [r7, #4]
+ 8002b00:	695b      	ldr	r3, [r3, #20]
+ 8002b02:	08db      	lsrs	r3, r3, #3
+                      DMA_TO_BDMA_MEMORY_INC(hdma->Init.MemInc)              |
+ 8002b04:	431a      	orrs	r2, r3
+                      DMA_TO_BDMA_MDATA_SIZE(hdma->Init.MemDataAlignment)    |
+ 8002b06:	687b      	ldr	r3, [r7, #4]
+ 8002b08:	699b      	ldr	r3, [r3, #24]
+ 8002b0a:	08db      	lsrs	r3, r3, #3
+                      DMA_TO_BDMA_PDATA_SIZE(hdma->Init.PeriphDataAlignment) |
+ 8002b0c:	431a      	orrs	r2, r3
+                      DMA_TO_BDMA_MODE(hdma->Init.Mode)                      |
+ 8002b0e:	687b      	ldr	r3, [r7, #4]
+ 8002b10:	69db      	ldr	r3, [r3, #28]
+ 8002b12:	08db      	lsrs	r3, r3, #3
+                      DMA_TO_BDMA_MDATA_SIZE(hdma->Init.MemDataAlignment)    |
+ 8002b14:	431a      	orrs	r2, r3
+                      DMA_TO_BDMA_PRIORITY(hdma->Init.Priority);
+ 8002b16:	687b      	ldr	r3, [r7, #4]
+ 8002b18:	6a1b      	ldr	r3, [r3, #32]
+ 8002b1a:	091b      	lsrs	r3, r3, #4
+                      DMA_TO_BDMA_MODE(hdma->Init.Mode)                      |
+ 8002b1c:	4313      	orrs	r3, r2
+    registerValue |=  DMA_TO_BDMA_DIRECTION(hdma->Init.Direction)            |
+ 8002b1e:	697a      	ldr	r2, [r7, #20]
+ 8002b20:	4313      	orrs	r3, r2
+ 8002b22:	617b      	str	r3, [r7, #20]
+
+    /* Write to DMA Channel CR register */
+    ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR = registerValue;
+ 8002b24:	687b      	ldr	r3, [r7, #4]
+ 8002b26:	681b      	ldr	r3, [r3, #0]
+ 8002b28:	697a      	ldr	r2, [r7, #20]
+ 8002b2a:	601a      	str	r2, [r3, #0]
+
+    /* calculation of the channel index */
+    hdma->StreamIndex = (((uint32_t)((uint32_t*)hdma->Instance) - (uint32_t)BDMA_Channel0) / ((uint32_t)BDMA_Channel1 - (uint32_t)BDMA_Channel0)) << 2U;
+ 8002b2c:	687b      	ldr	r3, [r7, #4]
+ 8002b2e:	681b      	ldr	r3, [r3, #0]
+ 8002b30:	461a      	mov	r2, r3
+ 8002b32:	4b6e      	ldr	r3, [pc, #440]	; (8002cec <HAL_DMA_Init+0x648>)
+ 8002b34:	4413      	add	r3, r2
+ 8002b36:	4a6e      	ldr	r2, [pc, #440]	; (8002cf0 <HAL_DMA_Init+0x64c>)
+ 8002b38:	fba2 2303 	umull	r2, r3, r2, r3
+ 8002b3c:	091b      	lsrs	r3, r3, #4
+ 8002b3e:	009a      	lsls	r2, r3, #2
+ 8002b40:	687b      	ldr	r3, [r7, #4]
+ 8002b42:	65da      	str	r2, [r3, #92]	; 0x5c
+
+    /* Initialize StreamBaseAddress and StreamIndex parameters to be used to calculate
+    DMA steam Base Address needed by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */
+    regs_bdma = (BDMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma);
+ 8002b44:	6878      	ldr	r0, [r7, #4]
+ 8002b46:	f001 f82f 	bl	8003ba8 <DMA_CalcBaseAndBitshift>
+ 8002b4a:	4603      	mov	r3, r0
+ 8002b4c:	60fb      	str	r3, [r7, #12]
+
+    /* Clear all interrupt flags */
+    regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU));
+ 8002b4e:	687b      	ldr	r3, [r7, #4]
+ 8002b50:	6ddb      	ldr	r3, [r3, #92]	; 0x5c
+ 8002b52:	f003 031f 	and.w	r3, r3, #31
+ 8002b56:	2201      	movs	r2, #1
+ 8002b58:	409a      	lsls	r2, r3
+ 8002b5a:	68fb      	ldr	r3, [r7, #12]
+ 8002b5c:	605a      	str	r2, [r3, #4]
+ 8002b5e:	e008      	b.n	8002b72 <HAL_DMA_Init+0x4ce>
+  }
+  else
+  {
+    hdma->ErrorCode = HAL_DMA_ERROR_PARAM;
+ 8002b60:	687b      	ldr	r3, [r7, #4]
+ 8002b62:	2240      	movs	r2, #64	; 0x40
+ 8002b64:	655a      	str	r2, [r3, #84]	; 0x54
+    hdma->State     = HAL_DMA_STATE_ERROR;
+ 8002b66:	687b      	ldr	r3, [r7, #4]
+ 8002b68:	2203      	movs	r2, #3
+ 8002b6a:	f883 2035 	strb.w	r2, [r3, #53]	; 0x35
+
+    return HAL_ERROR;
+ 8002b6e:	2301      	movs	r3, #1
+ 8002b70:	e0b7      	b.n	8002ce2 <HAL_DMA_Init+0x63e>
+  }
+
+  if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
+ 8002b72:	687b      	ldr	r3, [r7, #4]
+ 8002b74:	681b      	ldr	r3, [r3, #0]
+ 8002b76:	4a5f      	ldr	r2, [pc, #380]	; (8002cf4 <HAL_DMA_Init+0x650>)
+ 8002b78:	4293      	cmp	r3, r2
+ 8002b7a:	d072      	beq.n	8002c62 <HAL_DMA_Init+0x5be>
+ 8002b7c:	687b      	ldr	r3, [r7, #4]
+ 8002b7e:	681b      	ldr	r3, [r3, #0]
+ 8002b80:	4a5d      	ldr	r2, [pc, #372]	; (8002cf8 <HAL_DMA_Init+0x654>)
+ 8002b82:	4293      	cmp	r3, r2
+ 8002b84:	d06d      	beq.n	8002c62 <HAL_DMA_Init+0x5be>
+ 8002b86:	687b      	ldr	r3, [r7, #4]
+ 8002b88:	681b      	ldr	r3, [r3, #0]
+ 8002b8a:	4a5c      	ldr	r2, [pc, #368]	; (8002cfc <HAL_DMA_Init+0x658>)
+ 8002b8c:	4293      	cmp	r3, r2
+ 8002b8e:	d068      	beq.n	8002c62 <HAL_DMA_Init+0x5be>
+ 8002b90:	687b      	ldr	r3, [r7, #4]
+ 8002b92:	681b      	ldr	r3, [r3, #0]
+ 8002b94:	4a5a      	ldr	r2, [pc, #360]	; (8002d00 <HAL_DMA_Init+0x65c>)
+ 8002b96:	4293      	cmp	r3, r2
+ 8002b98:	d063      	beq.n	8002c62 <HAL_DMA_Init+0x5be>
+ 8002b9a:	687b      	ldr	r3, [r7, #4]
+ 8002b9c:	681b      	ldr	r3, [r3, #0]
+ 8002b9e:	4a59      	ldr	r2, [pc, #356]	; (8002d04 <HAL_DMA_Init+0x660>)
+ 8002ba0:	4293      	cmp	r3, r2
+ 8002ba2:	d05e      	beq.n	8002c62 <HAL_DMA_Init+0x5be>
+ 8002ba4:	687b      	ldr	r3, [r7, #4]
+ 8002ba6:	681b      	ldr	r3, [r3, #0]
+ 8002ba8:	4a57      	ldr	r2, [pc, #348]	; (8002d08 <HAL_DMA_Init+0x664>)
+ 8002baa:	4293      	cmp	r3, r2
+ 8002bac:	d059      	beq.n	8002c62 <HAL_DMA_Init+0x5be>
+ 8002bae:	687b      	ldr	r3, [r7, #4]
+ 8002bb0:	681b      	ldr	r3, [r3, #0]
+ 8002bb2:	4a56      	ldr	r2, [pc, #344]	; (8002d0c <HAL_DMA_Init+0x668>)
+ 8002bb4:	4293      	cmp	r3, r2
+ 8002bb6:	d054      	beq.n	8002c62 <HAL_DMA_Init+0x5be>
+ 8002bb8:	687b      	ldr	r3, [r7, #4]
+ 8002bba:	681b      	ldr	r3, [r3, #0]
+ 8002bbc:	4a54      	ldr	r2, [pc, #336]	; (8002d10 <HAL_DMA_Init+0x66c>)
+ 8002bbe:	4293      	cmp	r3, r2
+ 8002bc0:	d04f      	beq.n	8002c62 <HAL_DMA_Init+0x5be>
+ 8002bc2:	687b      	ldr	r3, [r7, #4]
+ 8002bc4:	681b      	ldr	r3, [r3, #0]
+ 8002bc6:	4a53      	ldr	r2, [pc, #332]	; (8002d14 <HAL_DMA_Init+0x670>)
+ 8002bc8:	4293      	cmp	r3, r2
+ 8002bca:	d04a      	beq.n	8002c62 <HAL_DMA_Init+0x5be>
+ 8002bcc:	687b      	ldr	r3, [r7, #4]
+ 8002bce:	681b      	ldr	r3, [r3, #0]
+ 8002bd0:	4a51      	ldr	r2, [pc, #324]	; (8002d18 <HAL_DMA_Init+0x674>)
+ 8002bd2:	4293      	cmp	r3, r2
+ 8002bd4:	d045      	beq.n	8002c62 <HAL_DMA_Init+0x5be>
+ 8002bd6:	687b      	ldr	r3, [r7, #4]
+ 8002bd8:	681b      	ldr	r3, [r3, #0]
+ 8002bda:	4a50      	ldr	r2, [pc, #320]	; (8002d1c <HAL_DMA_Init+0x678>)
+ 8002bdc:	4293      	cmp	r3, r2
+ 8002bde:	d040      	beq.n	8002c62 <HAL_DMA_Init+0x5be>
+ 8002be0:	687b      	ldr	r3, [r7, #4]
+ 8002be2:	681b      	ldr	r3, [r3, #0]
+ 8002be4:	4a4e      	ldr	r2, [pc, #312]	; (8002d20 <HAL_DMA_Init+0x67c>)
+ 8002be6:	4293      	cmp	r3, r2
+ 8002be8:	d03b      	beq.n	8002c62 <HAL_DMA_Init+0x5be>
+ 8002bea:	687b      	ldr	r3, [r7, #4]
+ 8002bec:	681b      	ldr	r3, [r3, #0]
+ 8002bee:	4a4d      	ldr	r2, [pc, #308]	; (8002d24 <HAL_DMA_Init+0x680>)
+ 8002bf0:	4293      	cmp	r3, r2
+ 8002bf2:	d036      	beq.n	8002c62 <HAL_DMA_Init+0x5be>
+ 8002bf4:	687b      	ldr	r3, [r7, #4]
+ 8002bf6:	681b      	ldr	r3, [r3, #0]
+ 8002bf8:	4a4b      	ldr	r2, [pc, #300]	; (8002d28 <HAL_DMA_Init+0x684>)
+ 8002bfa:	4293      	cmp	r3, r2
+ 8002bfc:	d031      	beq.n	8002c62 <HAL_DMA_Init+0x5be>
+ 8002bfe:	687b      	ldr	r3, [r7, #4]
+ 8002c00:	681b      	ldr	r3, [r3, #0]
+ 8002c02:	4a4a      	ldr	r2, [pc, #296]	; (8002d2c <HAL_DMA_Init+0x688>)
+ 8002c04:	4293      	cmp	r3, r2
+ 8002c06:	d02c      	beq.n	8002c62 <HAL_DMA_Init+0x5be>
+ 8002c08:	687b      	ldr	r3, [r7, #4]
+ 8002c0a:	681b      	ldr	r3, [r3, #0]
+ 8002c0c:	4a48      	ldr	r2, [pc, #288]	; (8002d30 <HAL_DMA_Init+0x68c>)
+ 8002c0e:	4293      	cmp	r3, r2
+ 8002c10:	d027      	beq.n	8002c62 <HAL_DMA_Init+0x5be>
+ 8002c12:	687b      	ldr	r3, [r7, #4]
+ 8002c14:	681b      	ldr	r3, [r3, #0]
+ 8002c16:	4a47      	ldr	r2, [pc, #284]	; (8002d34 <HAL_DMA_Init+0x690>)
+ 8002c18:	4293      	cmp	r3, r2
+ 8002c1a:	d022      	beq.n	8002c62 <HAL_DMA_Init+0x5be>
+ 8002c1c:	687b      	ldr	r3, [r7, #4]
+ 8002c1e:	681b      	ldr	r3, [r3, #0]
+ 8002c20:	4a45      	ldr	r2, [pc, #276]	; (8002d38 <HAL_DMA_Init+0x694>)
+ 8002c22:	4293      	cmp	r3, r2
+ 8002c24:	d01d      	beq.n	8002c62 <HAL_DMA_Init+0x5be>
+ 8002c26:	687b      	ldr	r3, [r7, #4]
+ 8002c28:	681b      	ldr	r3, [r3, #0]
+ 8002c2a:	4a44      	ldr	r2, [pc, #272]	; (8002d3c <HAL_DMA_Init+0x698>)
+ 8002c2c:	4293      	cmp	r3, r2
+ 8002c2e:	d018      	beq.n	8002c62 <HAL_DMA_Init+0x5be>
+ 8002c30:	687b      	ldr	r3, [r7, #4]
+ 8002c32:	681b      	ldr	r3, [r3, #0]
+ 8002c34:	4a42      	ldr	r2, [pc, #264]	; (8002d40 <HAL_DMA_Init+0x69c>)
+ 8002c36:	4293      	cmp	r3, r2
+ 8002c38:	d013      	beq.n	8002c62 <HAL_DMA_Init+0x5be>
+ 8002c3a:	687b      	ldr	r3, [r7, #4]
+ 8002c3c:	681b      	ldr	r3, [r3, #0]
+ 8002c3e:	4a41      	ldr	r2, [pc, #260]	; (8002d44 <HAL_DMA_Init+0x6a0>)
+ 8002c40:	4293      	cmp	r3, r2
+ 8002c42:	d00e      	beq.n	8002c62 <HAL_DMA_Init+0x5be>
+ 8002c44:	687b      	ldr	r3, [r7, #4]
+ 8002c46:	681b      	ldr	r3, [r3, #0]
+ 8002c48:	4a3f      	ldr	r2, [pc, #252]	; (8002d48 <HAL_DMA_Init+0x6a4>)
+ 8002c4a:	4293      	cmp	r3, r2
+ 8002c4c:	d009      	beq.n	8002c62 <HAL_DMA_Init+0x5be>
+ 8002c4e:	687b      	ldr	r3, [r7, #4]
+ 8002c50:	681b      	ldr	r3, [r3, #0]
+ 8002c52:	4a3e      	ldr	r2, [pc, #248]	; (8002d4c <HAL_DMA_Init+0x6a8>)
+ 8002c54:	4293      	cmp	r3, r2
+ 8002c56:	d004      	beq.n	8002c62 <HAL_DMA_Init+0x5be>
+ 8002c58:	687b      	ldr	r3, [r7, #4]
+ 8002c5a:	681b      	ldr	r3, [r3, #0]
+ 8002c5c:	4a3c      	ldr	r2, [pc, #240]	; (8002d50 <HAL_DMA_Init+0x6ac>)
+ 8002c5e:	4293      	cmp	r3, r2
+ 8002c60:	d101      	bne.n	8002c66 <HAL_DMA_Init+0x5c2>
+ 8002c62:	2301      	movs	r3, #1
+ 8002c64:	e000      	b.n	8002c68 <HAL_DMA_Init+0x5c4>
+ 8002c66:	2300      	movs	r3, #0
+ 8002c68:	2b00      	cmp	r3, #0
+ 8002c6a:	d032      	beq.n	8002cd2 <HAL_DMA_Init+0x62e>
+  {
+    /* Initialize parameters for DMAMUX channel :
+    DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask
+    */
+    DMA_CalcDMAMUXChannelBaseAndMask(hdma);
+ 8002c6c:	6878      	ldr	r0, [r7, #4]
+ 8002c6e:	f001 f8c9 	bl	8003e04 <DMA_CalcDMAMUXChannelBaseAndMask>
+
+    if(hdma->Init.Direction == DMA_MEMORY_TO_MEMORY)
+ 8002c72:	687b      	ldr	r3, [r7, #4]
+ 8002c74:	689b      	ldr	r3, [r3, #8]
+ 8002c76:	2b80      	cmp	r3, #128	; 0x80
+ 8002c78:	d102      	bne.n	8002c80 <HAL_DMA_Init+0x5dc>
+    {
+      /* if memory to memory force the request to 0*/
+      hdma->Init.Request = DMA_REQUEST_MEM2MEM;
+ 8002c7a:	687b      	ldr	r3, [r7, #4]
+ 8002c7c:	2200      	movs	r2, #0
+ 8002c7e:	605a      	str	r2, [r3, #4]
+    }
+
+    /* Set peripheral request  to DMAMUX channel */
+    hdma->DMAmuxChannel->CCR = (hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID);
+ 8002c80:	687b      	ldr	r3, [r7, #4]
+ 8002c82:	685a      	ldr	r2, [r3, #4]
+ 8002c84:	687b      	ldr	r3, [r7, #4]
+ 8002c86:	6e1b      	ldr	r3, [r3, #96]	; 0x60
+ 8002c88:	b2d2      	uxtb	r2, r2
+ 8002c8a:	601a      	str	r2, [r3, #0]
+
+    /* Clear the DMAMUX synchro overrun flag */
+    hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
+ 8002c8c:	687b      	ldr	r3, [r7, #4]
+ 8002c8e:	6e5b      	ldr	r3, [r3, #100]	; 0x64
+ 8002c90:	687a      	ldr	r2, [r7, #4]
+ 8002c92:	6e92      	ldr	r2, [r2, #104]	; 0x68
+ 8002c94:	605a      	str	r2, [r3, #4]
+
+    /* Initialize parameters for DMAMUX request generator :
+    if the DMA request is DMA_REQUEST_GENERATOR0 to DMA_REQUEST_GENERATOR7
+    */
+    if((hdma->Init.Request >= DMA_REQUEST_GENERATOR0) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR7))
+ 8002c96:	687b      	ldr	r3, [r7, #4]
+ 8002c98:	685b      	ldr	r3, [r3, #4]
+ 8002c9a:	2b00      	cmp	r3, #0
+ 8002c9c:	d010      	beq.n	8002cc0 <HAL_DMA_Init+0x61c>
+ 8002c9e:	687b      	ldr	r3, [r7, #4]
+ 8002ca0:	685b      	ldr	r3, [r3, #4]
+ 8002ca2:	2b08      	cmp	r3, #8
+ 8002ca4:	d80c      	bhi.n	8002cc0 <HAL_DMA_Init+0x61c>
+    {
+      /* Initialize parameters for DMAMUX request generator :
+      DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask */
+      DMA_CalcDMAMUXRequestGenBaseAndMask(hdma);
+ 8002ca6:	6878      	ldr	r0, [r7, #4]
+ 8002ca8:	f001 f946 	bl	8003f38 <DMA_CalcDMAMUXRequestGenBaseAndMask>
+
+      /* Reset the DMAMUX request generator register */
+      hdma->DMAmuxRequestGen->RGCR = 0U;
+ 8002cac:	687b      	ldr	r3, [r7, #4]
+ 8002cae:	6edb      	ldr	r3, [r3, #108]	; 0x6c
+ 8002cb0:	2200      	movs	r2, #0
+ 8002cb2:	601a      	str	r2, [r3, #0]
+
+      /* Clear the DMAMUX request generator overrun flag */
+      hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
+ 8002cb4:	687b      	ldr	r3, [r7, #4]
+ 8002cb6:	6f1b      	ldr	r3, [r3, #112]	; 0x70
+ 8002cb8:	687a      	ldr	r2, [r7, #4]
+ 8002cba:	6f52      	ldr	r2, [r2, #116]	; 0x74
+ 8002cbc:	605a      	str	r2, [r3, #4]
+ 8002cbe:	e008      	b.n	8002cd2 <HAL_DMA_Init+0x62e>
+    }
+    else
+    {
+      hdma->DMAmuxRequestGen = 0U;
+ 8002cc0:	687b      	ldr	r3, [r7, #4]
+ 8002cc2:	2200      	movs	r2, #0
+ 8002cc4:	66da      	str	r2, [r3, #108]	; 0x6c
+      hdma->DMAmuxRequestGenStatus = 0U;
+ 8002cc6:	687b      	ldr	r3, [r7, #4]
+ 8002cc8:	2200      	movs	r2, #0
+ 8002cca:	671a      	str	r2, [r3, #112]	; 0x70
+      hdma->DMAmuxRequestGenStatusMask = 0U;
+ 8002ccc:	687b      	ldr	r3, [r7, #4]
+ 8002cce:	2200      	movs	r2, #0
+ 8002cd0:	675a      	str	r2, [r3, #116]	; 0x74
+    }
+  }
+
+  /* Initialize the error code */
+  hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+ 8002cd2:	687b      	ldr	r3, [r7, #4]
+ 8002cd4:	2200      	movs	r2, #0
+ 8002cd6:	655a      	str	r2, [r3, #84]	; 0x54
+
+  /* Initialize the DMA state */
+  hdma->State = HAL_DMA_STATE_READY;
+ 8002cd8:	687b      	ldr	r3, [r7, #4]
+ 8002cda:	2201      	movs	r2, #1
+ 8002cdc:	f883 2035 	strb.w	r2, [r3, #53]	; 0x35
+
+  return HAL_OK;
+ 8002ce0:	2300      	movs	r3, #0
+}
+ 8002ce2:	4618      	mov	r0, r3
+ 8002ce4:	3718      	adds	r7, #24
+ 8002ce6:	46bd      	mov	sp, r7
+ 8002ce8:	bd80      	pop	{r7, pc}
+ 8002cea:	bf00      	nop
+ 8002cec:	a7fdabf8 	.word	0xa7fdabf8
+ 8002cf0:	cccccccd 	.word	0xcccccccd
+ 8002cf4:	40020010 	.word	0x40020010
+ 8002cf8:	40020028 	.word	0x40020028
+ 8002cfc:	40020040 	.word	0x40020040
+ 8002d00:	40020058 	.word	0x40020058
+ 8002d04:	40020070 	.word	0x40020070
+ 8002d08:	40020088 	.word	0x40020088
+ 8002d0c:	400200a0 	.word	0x400200a0
+ 8002d10:	400200b8 	.word	0x400200b8
+ 8002d14:	40020410 	.word	0x40020410
+ 8002d18:	40020428 	.word	0x40020428
+ 8002d1c:	40020440 	.word	0x40020440
+ 8002d20:	40020458 	.word	0x40020458
+ 8002d24:	40020470 	.word	0x40020470
+ 8002d28:	40020488 	.word	0x40020488
+ 8002d2c:	400204a0 	.word	0x400204a0
+ 8002d30:	400204b8 	.word	0x400204b8
+ 8002d34:	58025408 	.word	0x58025408
+ 8002d38:	5802541c 	.word	0x5802541c
+ 8002d3c:	58025430 	.word	0x58025430
+ 8002d40:	58025444 	.word	0x58025444
+ 8002d44:	58025458 	.word	0x58025458
+ 8002d48:	5802546c 	.word	0x5802546c
+ 8002d4c:	58025480 	.word	0x58025480
+ 8002d50:	58025494 	.word	0x58025494
+
+08002d54 <HAL_DMA_IRQHandler>:
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA Stream.
+  * @retval None
+  */
+void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
+{
+ 8002d54:	b580      	push	{r7, lr}
+ 8002d56:	b08a      	sub	sp, #40	; 0x28
+ 8002d58:	af00      	add	r7, sp, #0
+ 8002d5a:	6078      	str	r0, [r7, #4]
+  uint32_t tmpisr_dma, tmpisr_bdma;
+  uint32_t ccr_reg;
+  __IO uint32_t count = 0U;
+ 8002d5c:	2300      	movs	r3, #0
+ 8002d5e:	60fb      	str	r3, [r7, #12]
+  uint32_t timeout = SystemCoreClock / 9600U;
+ 8002d60:	4b67      	ldr	r3, [pc, #412]	; (8002f00 <HAL_DMA_IRQHandler+0x1ac>)
+ 8002d62:	681b      	ldr	r3, [r3, #0]
+ 8002d64:	4a67      	ldr	r2, [pc, #412]	; (8002f04 <HAL_DMA_IRQHandler+0x1b0>)
+ 8002d66:	fba2 2303 	umull	r2, r3, r2, r3
+ 8002d6a:	0a9b      	lsrs	r3, r3, #10
+ 8002d6c:	627b      	str	r3, [r7, #36]	; 0x24
+
+  /* calculate DMA base and stream number */
+  DMA_Base_Registers  *regs_dma  = (DMA_Base_Registers *)hdma->StreamBaseAddress;
+ 8002d6e:	687b      	ldr	r3, [r7, #4]
+ 8002d70:	6d9b      	ldr	r3, [r3, #88]	; 0x58
+ 8002d72:	623b      	str	r3, [r7, #32]
+  BDMA_Base_Registers *regs_bdma = (BDMA_Base_Registers *)hdma->StreamBaseAddress;
+ 8002d74:	687b      	ldr	r3, [r7, #4]
+ 8002d76:	6d9b      	ldr	r3, [r3, #88]	; 0x58
+ 8002d78:	61fb      	str	r3, [r7, #28]
+
+  tmpisr_dma  = regs_dma->ISR;
+ 8002d7a:	6a3b      	ldr	r3, [r7, #32]
+ 8002d7c:	681b      	ldr	r3, [r3, #0]
+ 8002d7e:	61bb      	str	r3, [r7, #24]
+  tmpisr_bdma = regs_bdma->ISR;
+ 8002d80:	69fb      	ldr	r3, [r7, #28]
+ 8002d82:	681b      	ldr	r3, [r3, #0]
+ 8002d84:	617b      	str	r3, [r7, #20]
+
+  if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U)  /* DMA1 or DMA2 instance */
+ 8002d86:	687b      	ldr	r3, [r7, #4]
+ 8002d88:	681b      	ldr	r3, [r3, #0]
+ 8002d8a:	4a5f      	ldr	r2, [pc, #380]	; (8002f08 <HAL_DMA_IRQHandler+0x1b4>)
+ 8002d8c:	4293      	cmp	r3, r2
+ 8002d8e:	d04a      	beq.n	8002e26 <HAL_DMA_IRQHandler+0xd2>
+ 8002d90:	687b      	ldr	r3, [r7, #4]
+ 8002d92:	681b      	ldr	r3, [r3, #0]
+ 8002d94:	4a5d      	ldr	r2, [pc, #372]	; (8002f0c <HAL_DMA_IRQHandler+0x1b8>)
+ 8002d96:	4293      	cmp	r3, r2
+ 8002d98:	d045      	beq.n	8002e26 <HAL_DMA_IRQHandler+0xd2>
+ 8002d9a:	687b      	ldr	r3, [r7, #4]
+ 8002d9c:	681b      	ldr	r3, [r3, #0]
+ 8002d9e:	4a5c      	ldr	r2, [pc, #368]	; (8002f10 <HAL_DMA_IRQHandler+0x1bc>)
+ 8002da0:	4293      	cmp	r3, r2
+ 8002da2:	d040      	beq.n	8002e26 <HAL_DMA_IRQHandler+0xd2>
+ 8002da4:	687b      	ldr	r3, [r7, #4]
+ 8002da6:	681b      	ldr	r3, [r3, #0]
+ 8002da8:	4a5a      	ldr	r2, [pc, #360]	; (8002f14 <HAL_DMA_IRQHandler+0x1c0>)
+ 8002daa:	4293      	cmp	r3, r2
+ 8002dac:	d03b      	beq.n	8002e26 <HAL_DMA_IRQHandler+0xd2>
+ 8002dae:	687b      	ldr	r3, [r7, #4]
+ 8002db0:	681b      	ldr	r3, [r3, #0]
+ 8002db2:	4a59      	ldr	r2, [pc, #356]	; (8002f18 <HAL_DMA_IRQHandler+0x1c4>)
+ 8002db4:	4293      	cmp	r3, r2
+ 8002db6:	d036      	beq.n	8002e26 <HAL_DMA_IRQHandler+0xd2>
+ 8002db8:	687b      	ldr	r3, [r7, #4]
+ 8002dba:	681b      	ldr	r3, [r3, #0]
+ 8002dbc:	4a57      	ldr	r2, [pc, #348]	; (8002f1c <HAL_DMA_IRQHandler+0x1c8>)
+ 8002dbe:	4293      	cmp	r3, r2
+ 8002dc0:	d031      	beq.n	8002e26 <HAL_DMA_IRQHandler+0xd2>
+ 8002dc2:	687b      	ldr	r3, [r7, #4]
+ 8002dc4:	681b      	ldr	r3, [r3, #0]
+ 8002dc6:	4a56      	ldr	r2, [pc, #344]	; (8002f20 <HAL_DMA_IRQHandler+0x1cc>)
+ 8002dc8:	4293      	cmp	r3, r2
+ 8002dca:	d02c      	beq.n	8002e26 <HAL_DMA_IRQHandler+0xd2>
+ 8002dcc:	687b      	ldr	r3, [r7, #4]
+ 8002dce:	681b      	ldr	r3, [r3, #0]
+ 8002dd0:	4a54      	ldr	r2, [pc, #336]	; (8002f24 <HAL_DMA_IRQHandler+0x1d0>)
+ 8002dd2:	4293      	cmp	r3, r2
+ 8002dd4:	d027      	beq.n	8002e26 <HAL_DMA_IRQHandler+0xd2>
+ 8002dd6:	687b      	ldr	r3, [r7, #4]
+ 8002dd8:	681b      	ldr	r3, [r3, #0]
+ 8002dda:	4a53      	ldr	r2, [pc, #332]	; (8002f28 <HAL_DMA_IRQHandler+0x1d4>)
+ 8002ddc:	4293      	cmp	r3, r2
+ 8002dde:	d022      	beq.n	8002e26 <HAL_DMA_IRQHandler+0xd2>
+ 8002de0:	687b      	ldr	r3, [r7, #4]
+ 8002de2:	681b      	ldr	r3, [r3, #0]
+ 8002de4:	4a51      	ldr	r2, [pc, #324]	; (8002f2c <HAL_DMA_IRQHandler+0x1d8>)
+ 8002de6:	4293      	cmp	r3, r2
+ 8002de8:	d01d      	beq.n	8002e26 <HAL_DMA_IRQHandler+0xd2>
+ 8002dea:	687b      	ldr	r3, [r7, #4]
+ 8002dec:	681b      	ldr	r3, [r3, #0]
+ 8002dee:	4a50      	ldr	r2, [pc, #320]	; (8002f30 <HAL_DMA_IRQHandler+0x1dc>)
+ 8002df0:	4293      	cmp	r3, r2
+ 8002df2:	d018      	beq.n	8002e26 <HAL_DMA_IRQHandler+0xd2>
+ 8002df4:	687b      	ldr	r3, [r7, #4]
+ 8002df6:	681b      	ldr	r3, [r3, #0]
+ 8002df8:	4a4e      	ldr	r2, [pc, #312]	; (8002f34 <HAL_DMA_IRQHandler+0x1e0>)
+ 8002dfa:	4293      	cmp	r3, r2
+ 8002dfc:	d013      	beq.n	8002e26 <HAL_DMA_IRQHandler+0xd2>
+ 8002dfe:	687b      	ldr	r3, [r7, #4]
+ 8002e00:	681b      	ldr	r3, [r3, #0]
+ 8002e02:	4a4d      	ldr	r2, [pc, #308]	; (8002f38 <HAL_DMA_IRQHandler+0x1e4>)
+ 8002e04:	4293      	cmp	r3, r2
+ 8002e06:	d00e      	beq.n	8002e26 <HAL_DMA_IRQHandler+0xd2>
+ 8002e08:	687b      	ldr	r3, [r7, #4]
+ 8002e0a:	681b      	ldr	r3, [r3, #0]
+ 8002e0c:	4a4b      	ldr	r2, [pc, #300]	; (8002f3c <HAL_DMA_IRQHandler+0x1e8>)
+ 8002e0e:	4293      	cmp	r3, r2
+ 8002e10:	d009      	beq.n	8002e26 <HAL_DMA_IRQHandler+0xd2>
+ 8002e12:	687b      	ldr	r3, [r7, #4]
+ 8002e14:	681b      	ldr	r3, [r3, #0]
+ 8002e16:	4a4a      	ldr	r2, [pc, #296]	; (8002f40 <HAL_DMA_IRQHandler+0x1ec>)
+ 8002e18:	4293      	cmp	r3, r2
+ 8002e1a:	d004      	beq.n	8002e26 <HAL_DMA_IRQHandler+0xd2>
+ 8002e1c:	687b      	ldr	r3, [r7, #4]
+ 8002e1e:	681b      	ldr	r3, [r3, #0]
+ 8002e20:	4a48      	ldr	r2, [pc, #288]	; (8002f44 <HAL_DMA_IRQHandler+0x1f0>)
+ 8002e22:	4293      	cmp	r3, r2
+ 8002e24:	d101      	bne.n	8002e2a <HAL_DMA_IRQHandler+0xd6>
+ 8002e26:	2301      	movs	r3, #1
+ 8002e28:	e000      	b.n	8002e2c <HAL_DMA_IRQHandler+0xd8>
+ 8002e2a:	2300      	movs	r3, #0
+ 8002e2c:	2b00      	cmp	r3, #0
+ 8002e2e:	f000 842b 	beq.w	8003688 <HAL_DMA_IRQHandler+0x934>
+  {
+    /* Transfer Error Interrupt management ***************************************/
+    if ((tmpisr_dma & (DMA_FLAG_TEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U)
+ 8002e32:	687b      	ldr	r3, [r7, #4]
+ 8002e34:	6ddb      	ldr	r3, [r3, #92]	; 0x5c
+ 8002e36:	f003 031f 	and.w	r3, r3, #31
+ 8002e3a:	2208      	movs	r2, #8
+ 8002e3c:	409a      	lsls	r2, r3
+ 8002e3e:	69bb      	ldr	r3, [r7, #24]
+ 8002e40:	4013      	ands	r3, r2
+ 8002e42:	2b00      	cmp	r3, #0
+ 8002e44:	f000 80a2 	beq.w	8002f8c <HAL_DMA_IRQHandler+0x238>
+    {
+      if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != 0U)
+ 8002e48:	687b      	ldr	r3, [r7, #4]
+ 8002e4a:	681b      	ldr	r3, [r3, #0]
+ 8002e4c:	4a2e      	ldr	r2, [pc, #184]	; (8002f08 <HAL_DMA_IRQHandler+0x1b4>)
+ 8002e4e:	4293      	cmp	r3, r2
+ 8002e50:	d04a      	beq.n	8002ee8 <HAL_DMA_IRQHandler+0x194>
+ 8002e52:	687b      	ldr	r3, [r7, #4]
+ 8002e54:	681b      	ldr	r3, [r3, #0]
+ 8002e56:	4a2d      	ldr	r2, [pc, #180]	; (8002f0c <HAL_DMA_IRQHandler+0x1b8>)
+ 8002e58:	4293      	cmp	r3, r2
+ 8002e5a:	d045      	beq.n	8002ee8 <HAL_DMA_IRQHandler+0x194>
+ 8002e5c:	687b      	ldr	r3, [r7, #4]
+ 8002e5e:	681b      	ldr	r3, [r3, #0]
+ 8002e60:	4a2b      	ldr	r2, [pc, #172]	; (8002f10 <HAL_DMA_IRQHandler+0x1bc>)
+ 8002e62:	4293      	cmp	r3, r2
+ 8002e64:	d040      	beq.n	8002ee8 <HAL_DMA_IRQHandler+0x194>
+ 8002e66:	687b      	ldr	r3, [r7, #4]
+ 8002e68:	681b      	ldr	r3, [r3, #0]
+ 8002e6a:	4a2a      	ldr	r2, [pc, #168]	; (8002f14 <HAL_DMA_IRQHandler+0x1c0>)
+ 8002e6c:	4293      	cmp	r3, r2
+ 8002e6e:	d03b      	beq.n	8002ee8 <HAL_DMA_IRQHandler+0x194>
+ 8002e70:	687b      	ldr	r3, [r7, #4]
+ 8002e72:	681b      	ldr	r3, [r3, #0]
+ 8002e74:	4a28      	ldr	r2, [pc, #160]	; (8002f18 <HAL_DMA_IRQHandler+0x1c4>)
+ 8002e76:	4293      	cmp	r3, r2
+ 8002e78:	d036      	beq.n	8002ee8 <HAL_DMA_IRQHandler+0x194>
+ 8002e7a:	687b      	ldr	r3, [r7, #4]
+ 8002e7c:	681b      	ldr	r3, [r3, #0]
+ 8002e7e:	4a27      	ldr	r2, [pc, #156]	; (8002f1c <HAL_DMA_IRQHandler+0x1c8>)
+ 8002e80:	4293      	cmp	r3, r2
+ 8002e82:	d031      	beq.n	8002ee8 <HAL_DMA_IRQHandler+0x194>
+ 8002e84:	687b      	ldr	r3, [r7, #4]
+ 8002e86:	681b      	ldr	r3, [r3, #0]
+ 8002e88:	4a25      	ldr	r2, [pc, #148]	; (8002f20 <HAL_DMA_IRQHandler+0x1cc>)
+ 8002e8a:	4293      	cmp	r3, r2
+ 8002e8c:	d02c      	beq.n	8002ee8 <HAL_DMA_IRQHandler+0x194>
+ 8002e8e:	687b      	ldr	r3, [r7, #4]
+ 8002e90:	681b      	ldr	r3, [r3, #0]
+ 8002e92:	4a24      	ldr	r2, [pc, #144]	; (8002f24 <HAL_DMA_IRQHandler+0x1d0>)
+ 8002e94:	4293      	cmp	r3, r2
+ 8002e96:	d027      	beq.n	8002ee8 <HAL_DMA_IRQHandler+0x194>
+ 8002e98:	687b      	ldr	r3, [r7, #4]
+ 8002e9a:	681b      	ldr	r3, [r3, #0]
+ 8002e9c:	4a22      	ldr	r2, [pc, #136]	; (8002f28 <HAL_DMA_IRQHandler+0x1d4>)
+ 8002e9e:	4293      	cmp	r3, r2
+ 8002ea0:	d022      	beq.n	8002ee8 <HAL_DMA_IRQHandler+0x194>
+ 8002ea2:	687b      	ldr	r3, [r7, #4]
+ 8002ea4:	681b      	ldr	r3, [r3, #0]
+ 8002ea6:	4a21      	ldr	r2, [pc, #132]	; (8002f2c <HAL_DMA_IRQHandler+0x1d8>)
+ 8002ea8:	4293      	cmp	r3, r2
+ 8002eaa:	d01d      	beq.n	8002ee8 <HAL_DMA_IRQHandler+0x194>
+ 8002eac:	687b      	ldr	r3, [r7, #4]
+ 8002eae:	681b      	ldr	r3, [r3, #0]
+ 8002eb0:	4a1f      	ldr	r2, [pc, #124]	; (8002f30 <HAL_DMA_IRQHandler+0x1dc>)
+ 8002eb2:	4293      	cmp	r3, r2
+ 8002eb4:	d018      	beq.n	8002ee8 <HAL_DMA_IRQHandler+0x194>
+ 8002eb6:	687b      	ldr	r3, [r7, #4]
+ 8002eb8:	681b      	ldr	r3, [r3, #0]
+ 8002eba:	4a1e      	ldr	r2, [pc, #120]	; (8002f34 <HAL_DMA_IRQHandler+0x1e0>)
+ 8002ebc:	4293      	cmp	r3, r2
+ 8002ebe:	d013      	beq.n	8002ee8 <HAL_DMA_IRQHandler+0x194>
+ 8002ec0:	687b      	ldr	r3, [r7, #4]
+ 8002ec2:	681b      	ldr	r3, [r3, #0]
+ 8002ec4:	4a1c      	ldr	r2, [pc, #112]	; (8002f38 <HAL_DMA_IRQHandler+0x1e4>)
+ 8002ec6:	4293      	cmp	r3, r2
+ 8002ec8:	d00e      	beq.n	8002ee8 <HAL_DMA_IRQHandler+0x194>
+ 8002eca:	687b      	ldr	r3, [r7, #4]
+ 8002ecc:	681b      	ldr	r3, [r3, #0]
+ 8002ece:	4a1b      	ldr	r2, [pc, #108]	; (8002f3c <HAL_DMA_IRQHandler+0x1e8>)
+ 8002ed0:	4293      	cmp	r3, r2
+ 8002ed2:	d009      	beq.n	8002ee8 <HAL_DMA_IRQHandler+0x194>
+ 8002ed4:	687b      	ldr	r3, [r7, #4]
+ 8002ed6:	681b      	ldr	r3, [r3, #0]
+ 8002ed8:	4a19      	ldr	r2, [pc, #100]	; (8002f40 <HAL_DMA_IRQHandler+0x1ec>)
+ 8002eda:	4293      	cmp	r3, r2
+ 8002edc:	d004      	beq.n	8002ee8 <HAL_DMA_IRQHandler+0x194>
+ 8002ede:	687b      	ldr	r3, [r7, #4]
+ 8002ee0:	681b      	ldr	r3, [r3, #0]
+ 8002ee2:	4a18      	ldr	r2, [pc, #96]	; (8002f44 <HAL_DMA_IRQHandler+0x1f0>)
+ 8002ee4:	4293      	cmp	r3, r2
+ 8002ee6:	d12f      	bne.n	8002f48 <HAL_DMA_IRQHandler+0x1f4>
+ 8002ee8:	687b      	ldr	r3, [r7, #4]
+ 8002eea:	681b      	ldr	r3, [r3, #0]
+ 8002eec:	681b      	ldr	r3, [r3, #0]
+ 8002eee:	f003 0304 	and.w	r3, r3, #4
+ 8002ef2:	2b00      	cmp	r3, #0
+ 8002ef4:	bf14      	ite	ne
+ 8002ef6:	2301      	movne	r3, #1
+ 8002ef8:	2300      	moveq	r3, #0
+ 8002efa:	b2db      	uxtb	r3, r3
+ 8002efc:	e02e      	b.n	8002f5c <HAL_DMA_IRQHandler+0x208>
+ 8002efe:	bf00      	nop
+ 8002f00:	24000014 	.word	0x24000014
+ 8002f04:	1b4e81b5 	.word	0x1b4e81b5
+ 8002f08:	40020010 	.word	0x40020010
+ 8002f0c:	40020028 	.word	0x40020028
+ 8002f10:	40020040 	.word	0x40020040
+ 8002f14:	40020058 	.word	0x40020058
+ 8002f18:	40020070 	.word	0x40020070
+ 8002f1c:	40020088 	.word	0x40020088
+ 8002f20:	400200a0 	.word	0x400200a0
+ 8002f24:	400200b8 	.word	0x400200b8
+ 8002f28:	40020410 	.word	0x40020410
+ 8002f2c:	40020428 	.word	0x40020428
+ 8002f30:	40020440 	.word	0x40020440
+ 8002f34:	40020458 	.word	0x40020458
+ 8002f38:	40020470 	.word	0x40020470
+ 8002f3c:	40020488 	.word	0x40020488
+ 8002f40:	400204a0 	.word	0x400204a0
+ 8002f44:	400204b8 	.word	0x400204b8
+ 8002f48:	687b      	ldr	r3, [r7, #4]
+ 8002f4a:	681b      	ldr	r3, [r3, #0]
+ 8002f4c:	681b      	ldr	r3, [r3, #0]
+ 8002f4e:	f003 0308 	and.w	r3, r3, #8
+ 8002f52:	2b00      	cmp	r3, #0
+ 8002f54:	bf14      	ite	ne
+ 8002f56:	2301      	movne	r3, #1
+ 8002f58:	2300      	moveq	r3, #0
+ 8002f5a:	b2db      	uxtb	r3, r3
+ 8002f5c:	2b00      	cmp	r3, #0
+ 8002f5e:	d015      	beq.n	8002f8c <HAL_DMA_IRQHandler+0x238>
+      {
+        /* Disable the transfer error interrupt */
+        ((DMA_Stream_TypeDef   *)hdma->Instance)->CR  &= ~(DMA_IT_TE);
+ 8002f60:	687b      	ldr	r3, [r7, #4]
+ 8002f62:	681b      	ldr	r3, [r3, #0]
+ 8002f64:	681a      	ldr	r2, [r3, #0]
+ 8002f66:	687b      	ldr	r3, [r7, #4]
+ 8002f68:	681b      	ldr	r3, [r3, #0]
+ 8002f6a:	f022 0204 	bic.w	r2, r2, #4
+ 8002f6e:	601a      	str	r2, [r3, #0]
+
+        /* Clear the transfer error flag */
+        regs_dma->IFCR = DMA_FLAG_TEIF0_4 << (hdma->StreamIndex & 0x1FU);
+ 8002f70:	687b      	ldr	r3, [r7, #4]
+ 8002f72:	6ddb      	ldr	r3, [r3, #92]	; 0x5c
+ 8002f74:	f003 031f 	and.w	r3, r3, #31
+ 8002f78:	2208      	movs	r2, #8
+ 8002f7a:	409a      	lsls	r2, r3
+ 8002f7c:	6a3b      	ldr	r3, [r7, #32]
+ 8002f7e:	609a      	str	r2, [r3, #8]
+
+        /* Update error code */
+        hdma->ErrorCode |= HAL_DMA_ERROR_TE;
+ 8002f80:	687b      	ldr	r3, [r7, #4]
+ 8002f82:	6d5b      	ldr	r3, [r3, #84]	; 0x54
+ 8002f84:	f043 0201 	orr.w	r2, r3, #1
+ 8002f88:	687b      	ldr	r3, [r7, #4]
+ 8002f8a:	655a      	str	r2, [r3, #84]	; 0x54
+      }
+    }
+    /* FIFO Error Interrupt management ******************************************/
+    if ((tmpisr_dma & (DMA_FLAG_FEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U)
+ 8002f8c:	687b      	ldr	r3, [r7, #4]
+ 8002f8e:	6ddb      	ldr	r3, [r3, #92]	; 0x5c
+ 8002f90:	f003 031f 	and.w	r3, r3, #31
+ 8002f94:	69ba      	ldr	r2, [r7, #24]
+ 8002f96:	fa22 f303 	lsr.w	r3, r2, r3
+ 8002f9a:	f003 0301 	and.w	r3, r3, #1
+ 8002f9e:	2b00      	cmp	r3, #0
+ 8002fa0:	d06e      	beq.n	8003080 <HAL_DMA_IRQHandler+0x32c>
+    {
+      if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_FE) != 0U)
+ 8002fa2:	687b      	ldr	r3, [r7, #4]
+ 8002fa4:	681b      	ldr	r3, [r3, #0]
+ 8002fa6:	4a69      	ldr	r2, [pc, #420]	; (800314c <HAL_DMA_IRQHandler+0x3f8>)
+ 8002fa8:	4293      	cmp	r3, r2
+ 8002faa:	d04a      	beq.n	8003042 <HAL_DMA_IRQHandler+0x2ee>
+ 8002fac:	687b      	ldr	r3, [r7, #4]
+ 8002fae:	681b      	ldr	r3, [r3, #0]
+ 8002fb0:	4a67      	ldr	r2, [pc, #412]	; (8003150 <HAL_DMA_IRQHandler+0x3fc>)
+ 8002fb2:	4293      	cmp	r3, r2
+ 8002fb4:	d045      	beq.n	8003042 <HAL_DMA_IRQHandler+0x2ee>
+ 8002fb6:	687b      	ldr	r3, [r7, #4]
+ 8002fb8:	681b      	ldr	r3, [r3, #0]
+ 8002fba:	4a66      	ldr	r2, [pc, #408]	; (8003154 <HAL_DMA_IRQHandler+0x400>)
+ 8002fbc:	4293      	cmp	r3, r2
+ 8002fbe:	d040      	beq.n	8003042 <HAL_DMA_IRQHandler+0x2ee>
+ 8002fc0:	687b      	ldr	r3, [r7, #4]
+ 8002fc2:	681b      	ldr	r3, [r3, #0]
+ 8002fc4:	4a64      	ldr	r2, [pc, #400]	; (8003158 <HAL_DMA_IRQHandler+0x404>)
+ 8002fc6:	4293      	cmp	r3, r2
+ 8002fc8:	d03b      	beq.n	8003042 <HAL_DMA_IRQHandler+0x2ee>
+ 8002fca:	687b      	ldr	r3, [r7, #4]
+ 8002fcc:	681b      	ldr	r3, [r3, #0]
+ 8002fce:	4a63      	ldr	r2, [pc, #396]	; (800315c <HAL_DMA_IRQHandler+0x408>)
+ 8002fd0:	4293      	cmp	r3, r2
+ 8002fd2:	d036      	beq.n	8003042 <HAL_DMA_IRQHandler+0x2ee>
+ 8002fd4:	687b      	ldr	r3, [r7, #4]
+ 8002fd6:	681b      	ldr	r3, [r3, #0]
+ 8002fd8:	4a61      	ldr	r2, [pc, #388]	; (8003160 <HAL_DMA_IRQHandler+0x40c>)
+ 8002fda:	4293      	cmp	r3, r2
+ 8002fdc:	d031      	beq.n	8003042 <HAL_DMA_IRQHandler+0x2ee>
+ 8002fde:	687b      	ldr	r3, [r7, #4]
+ 8002fe0:	681b      	ldr	r3, [r3, #0]
+ 8002fe2:	4a60      	ldr	r2, [pc, #384]	; (8003164 <HAL_DMA_IRQHandler+0x410>)
+ 8002fe4:	4293      	cmp	r3, r2
+ 8002fe6:	d02c      	beq.n	8003042 <HAL_DMA_IRQHandler+0x2ee>
+ 8002fe8:	687b      	ldr	r3, [r7, #4]
+ 8002fea:	681b      	ldr	r3, [r3, #0]
+ 8002fec:	4a5e      	ldr	r2, [pc, #376]	; (8003168 <HAL_DMA_IRQHandler+0x414>)
+ 8002fee:	4293      	cmp	r3, r2
+ 8002ff0:	d027      	beq.n	8003042 <HAL_DMA_IRQHandler+0x2ee>
+ 8002ff2:	687b      	ldr	r3, [r7, #4]
+ 8002ff4:	681b      	ldr	r3, [r3, #0]
+ 8002ff6:	4a5d      	ldr	r2, [pc, #372]	; (800316c <HAL_DMA_IRQHandler+0x418>)
+ 8002ff8:	4293      	cmp	r3, r2
+ 8002ffa:	d022      	beq.n	8003042 <HAL_DMA_IRQHandler+0x2ee>
+ 8002ffc:	687b      	ldr	r3, [r7, #4]
+ 8002ffe:	681b      	ldr	r3, [r3, #0]
+ 8003000:	4a5b      	ldr	r2, [pc, #364]	; (8003170 <HAL_DMA_IRQHandler+0x41c>)
+ 8003002:	4293      	cmp	r3, r2
+ 8003004:	d01d      	beq.n	8003042 <HAL_DMA_IRQHandler+0x2ee>
+ 8003006:	687b      	ldr	r3, [r7, #4]
+ 8003008:	681b      	ldr	r3, [r3, #0]
+ 800300a:	4a5a      	ldr	r2, [pc, #360]	; (8003174 <HAL_DMA_IRQHandler+0x420>)
+ 800300c:	4293      	cmp	r3, r2
+ 800300e:	d018      	beq.n	8003042 <HAL_DMA_IRQHandler+0x2ee>
+ 8003010:	687b      	ldr	r3, [r7, #4]
+ 8003012:	681b      	ldr	r3, [r3, #0]
+ 8003014:	4a58      	ldr	r2, [pc, #352]	; (8003178 <HAL_DMA_IRQHandler+0x424>)
+ 8003016:	4293      	cmp	r3, r2
+ 8003018:	d013      	beq.n	8003042 <HAL_DMA_IRQHandler+0x2ee>
+ 800301a:	687b      	ldr	r3, [r7, #4]
+ 800301c:	681b      	ldr	r3, [r3, #0]
+ 800301e:	4a57      	ldr	r2, [pc, #348]	; (800317c <HAL_DMA_IRQHandler+0x428>)
+ 8003020:	4293      	cmp	r3, r2
+ 8003022:	d00e      	beq.n	8003042 <HAL_DMA_IRQHandler+0x2ee>
+ 8003024:	687b      	ldr	r3, [r7, #4]
+ 8003026:	681b      	ldr	r3, [r3, #0]
+ 8003028:	4a55      	ldr	r2, [pc, #340]	; (8003180 <HAL_DMA_IRQHandler+0x42c>)
+ 800302a:	4293      	cmp	r3, r2
+ 800302c:	d009      	beq.n	8003042 <HAL_DMA_IRQHandler+0x2ee>
+ 800302e:	687b      	ldr	r3, [r7, #4]
+ 8003030:	681b      	ldr	r3, [r3, #0]
+ 8003032:	4a54      	ldr	r2, [pc, #336]	; (8003184 <HAL_DMA_IRQHandler+0x430>)
+ 8003034:	4293      	cmp	r3, r2
+ 8003036:	d004      	beq.n	8003042 <HAL_DMA_IRQHandler+0x2ee>
+ 8003038:	687b      	ldr	r3, [r7, #4]
+ 800303a:	681b      	ldr	r3, [r3, #0]
+ 800303c:	4a52      	ldr	r2, [pc, #328]	; (8003188 <HAL_DMA_IRQHandler+0x434>)
+ 800303e:	4293      	cmp	r3, r2
+ 8003040:	d10a      	bne.n	8003058 <HAL_DMA_IRQHandler+0x304>
+ 8003042:	687b      	ldr	r3, [r7, #4]
+ 8003044:	681b      	ldr	r3, [r3, #0]
+ 8003046:	695b      	ldr	r3, [r3, #20]
+ 8003048:	f003 0380 	and.w	r3, r3, #128	; 0x80
+ 800304c:	2b00      	cmp	r3, #0
+ 800304e:	bf14      	ite	ne
+ 8003050:	2301      	movne	r3, #1
+ 8003052:	2300      	moveq	r3, #0
+ 8003054:	b2db      	uxtb	r3, r3
+ 8003056:	e003      	b.n	8003060 <HAL_DMA_IRQHandler+0x30c>
+ 8003058:	687b      	ldr	r3, [r7, #4]
+ 800305a:	681b      	ldr	r3, [r3, #0]
+ 800305c:	681b      	ldr	r3, [r3, #0]
+ 800305e:	2300      	movs	r3, #0
+ 8003060:	2b00      	cmp	r3, #0
+ 8003062:	d00d      	beq.n	8003080 <HAL_DMA_IRQHandler+0x32c>
+      {
+        /* Clear the FIFO error flag */
+        regs_dma->IFCR = DMA_FLAG_FEIF0_4 << (hdma->StreamIndex & 0x1FU);
+ 8003064:	687b      	ldr	r3, [r7, #4]
+ 8003066:	6ddb      	ldr	r3, [r3, #92]	; 0x5c
+ 8003068:	f003 031f 	and.w	r3, r3, #31
+ 800306c:	2201      	movs	r2, #1
+ 800306e:	409a      	lsls	r2, r3
+ 8003070:	6a3b      	ldr	r3, [r7, #32]
+ 8003072:	609a      	str	r2, [r3, #8]
+
+        /* Update error code */
+        hdma->ErrorCode |= HAL_DMA_ERROR_FE;
+ 8003074:	687b      	ldr	r3, [r7, #4]
+ 8003076:	6d5b      	ldr	r3, [r3, #84]	; 0x54
+ 8003078:	f043 0202 	orr.w	r2, r3, #2
+ 800307c:	687b      	ldr	r3, [r7, #4]
+ 800307e:	655a      	str	r2, [r3, #84]	; 0x54
+      }
+    }
+    /* Direct Mode Error Interrupt management ***********************************/
+    if ((tmpisr_dma & (DMA_FLAG_DMEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U)
+ 8003080:	687b      	ldr	r3, [r7, #4]
+ 8003082:	6ddb      	ldr	r3, [r3, #92]	; 0x5c
+ 8003084:	f003 031f 	and.w	r3, r3, #31
+ 8003088:	2204      	movs	r2, #4
+ 800308a:	409a      	lsls	r2, r3
+ 800308c:	69bb      	ldr	r3, [r7, #24]
+ 800308e:	4013      	ands	r3, r2
+ 8003090:	2b00      	cmp	r3, #0
+ 8003092:	f000 808f 	beq.w	80031b4 <HAL_DMA_IRQHandler+0x460>
+    {
+      if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_DME) != 0U)
+ 8003096:	687b      	ldr	r3, [r7, #4]
+ 8003098:	681b      	ldr	r3, [r3, #0]
+ 800309a:	4a2c      	ldr	r2, [pc, #176]	; (800314c <HAL_DMA_IRQHandler+0x3f8>)
+ 800309c:	4293      	cmp	r3, r2
+ 800309e:	d04a      	beq.n	8003136 <HAL_DMA_IRQHandler+0x3e2>
+ 80030a0:	687b      	ldr	r3, [r7, #4]
+ 80030a2:	681b      	ldr	r3, [r3, #0]
+ 80030a4:	4a2a      	ldr	r2, [pc, #168]	; (8003150 <HAL_DMA_IRQHandler+0x3fc>)
+ 80030a6:	4293      	cmp	r3, r2
+ 80030a8:	d045      	beq.n	8003136 <HAL_DMA_IRQHandler+0x3e2>
+ 80030aa:	687b      	ldr	r3, [r7, #4]
+ 80030ac:	681b      	ldr	r3, [r3, #0]
+ 80030ae:	4a29      	ldr	r2, [pc, #164]	; (8003154 <HAL_DMA_IRQHandler+0x400>)
+ 80030b0:	4293      	cmp	r3, r2
+ 80030b2:	d040      	beq.n	8003136 <HAL_DMA_IRQHandler+0x3e2>
+ 80030b4:	687b      	ldr	r3, [r7, #4]
+ 80030b6:	681b      	ldr	r3, [r3, #0]
+ 80030b8:	4a27      	ldr	r2, [pc, #156]	; (8003158 <HAL_DMA_IRQHandler+0x404>)
+ 80030ba:	4293      	cmp	r3, r2
+ 80030bc:	d03b      	beq.n	8003136 <HAL_DMA_IRQHandler+0x3e2>
+ 80030be:	687b      	ldr	r3, [r7, #4]
+ 80030c0:	681b      	ldr	r3, [r3, #0]
+ 80030c2:	4a26      	ldr	r2, [pc, #152]	; (800315c <HAL_DMA_IRQHandler+0x408>)
+ 80030c4:	4293      	cmp	r3, r2
+ 80030c6:	d036      	beq.n	8003136 <HAL_DMA_IRQHandler+0x3e2>
+ 80030c8:	687b      	ldr	r3, [r7, #4]
+ 80030ca:	681b      	ldr	r3, [r3, #0]
+ 80030cc:	4a24      	ldr	r2, [pc, #144]	; (8003160 <HAL_DMA_IRQHandler+0x40c>)
+ 80030ce:	4293      	cmp	r3, r2
+ 80030d0:	d031      	beq.n	8003136 <HAL_DMA_IRQHandler+0x3e2>
+ 80030d2:	687b      	ldr	r3, [r7, #4]
+ 80030d4:	681b      	ldr	r3, [r3, #0]
+ 80030d6:	4a23      	ldr	r2, [pc, #140]	; (8003164 <HAL_DMA_IRQHandler+0x410>)
+ 80030d8:	4293      	cmp	r3, r2
+ 80030da:	d02c      	beq.n	8003136 <HAL_DMA_IRQHandler+0x3e2>
+ 80030dc:	687b      	ldr	r3, [r7, #4]
+ 80030de:	681b      	ldr	r3, [r3, #0]
+ 80030e0:	4a21      	ldr	r2, [pc, #132]	; (8003168 <HAL_DMA_IRQHandler+0x414>)
+ 80030e2:	4293      	cmp	r3, r2
+ 80030e4:	d027      	beq.n	8003136 <HAL_DMA_IRQHandler+0x3e2>
+ 80030e6:	687b      	ldr	r3, [r7, #4]
+ 80030e8:	681b      	ldr	r3, [r3, #0]
+ 80030ea:	4a20      	ldr	r2, [pc, #128]	; (800316c <HAL_DMA_IRQHandler+0x418>)
+ 80030ec:	4293      	cmp	r3, r2
+ 80030ee:	d022      	beq.n	8003136 <HAL_DMA_IRQHandler+0x3e2>
+ 80030f0:	687b      	ldr	r3, [r7, #4]
+ 80030f2:	681b      	ldr	r3, [r3, #0]
+ 80030f4:	4a1e      	ldr	r2, [pc, #120]	; (8003170 <HAL_DMA_IRQHandler+0x41c>)
+ 80030f6:	4293      	cmp	r3, r2
+ 80030f8:	d01d      	beq.n	8003136 <HAL_DMA_IRQHandler+0x3e2>
+ 80030fa:	687b      	ldr	r3, [r7, #4]
+ 80030fc:	681b      	ldr	r3, [r3, #0]
+ 80030fe:	4a1d      	ldr	r2, [pc, #116]	; (8003174 <HAL_DMA_IRQHandler+0x420>)
+ 8003100:	4293      	cmp	r3, r2
+ 8003102:	d018      	beq.n	8003136 <HAL_DMA_IRQHandler+0x3e2>
+ 8003104:	687b      	ldr	r3, [r7, #4]
+ 8003106:	681b      	ldr	r3, [r3, #0]
+ 8003108:	4a1b      	ldr	r2, [pc, #108]	; (8003178 <HAL_DMA_IRQHandler+0x424>)
+ 800310a:	4293      	cmp	r3, r2
+ 800310c:	d013      	beq.n	8003136 <HAL_DMA_IRQHandler+0x3e2>
+ 800310e:	687b      	ldr	r3, [r7, #4]
+ 8003110:	681b      	ldr	r3, [r3, #0]
+ 8003112:	4a1a      	ldr	r2, [pc, #104]	; (800317c <HAL_DMA_IRQHandler+0x428>)
+ 8003114:	4293      	cmp	r3, r2
+ 8003116:	d00e      	beq.n	8003136 <HAL_DMA_IRQHandler+0x3e2>
+ 8003118:	687b      	ldr	r3, [r7, #4]
+ 800311a:	681b      	ldr	r3, [r3, #0]
+ 800311c:	4a18      	ldr	r2, [pc, #96]	; (8003180 <HAL_DMA_IRQHandler+0x42c>)
+ 800311e:	4293      	cmp	r3, r2
+ 8003120:	d009      	beq.n	8003136 <HAL_DMA_IRQHandler+0x3e2>
+ 8003122:	687b      	ldr	r3, [r7, #4]
+ 8003124:	681b      	ldr	r3, [r3, #0]
+ 8003126:	4a17      	ldr	r2, [pc, #92]	; (8003184 <HAL_DMA_IRQHandler+0x430>)
+ 8003128:	4293      	cmp	r3, r2
+ 800312a:	d004      	beq.n	8003136 <HAL_DMA_IRQHandler+0x3e2>
+ 800312c:	687b      	ldr	r3, [r7, #4]
+ 800312e:	681b      	ldr	r3, [r3, #0]
+ 8003130:	4a15      	ldr	r2, [pc, #84]	; (8003188 <HAL_DMA_IRQHandler+0x434>)
+ 8003132:	4293      	cmp	r3, r2
+ 8003134:	d12a      	bne.n	800318c <HAL_DMA_IRQHandler+0x438>
+ 8003136:	687b      	ldr	r3, [r7, #4]
+ 8003138:	681b      	ldr	r3, [r3, #0]
+ 800313a:	681b      	ldr	r3, [r3, #0]
+ 800313c:	f003 0302 	and.w	r3, r3, #2
+ 8003140:	2b00      	cmp	r3, #0
+ 8003142:	bf14      	ite	ne
+ 8003144:	2301      	movne	r3, #1
+ 8003146:	2300      	moveq	r3, #0
+ 8003148:	b2db      	uxtb	r3, r3
+ 800314a:	e023      	b.n	8003194 <HAL_DMA_IRQHandler+0x440>
+ 800314c:	40020010 	.word	0x40020010
+ 8003150:	40020028 	.word	0x40020028
+ 8003154:	40020040 	.word	0x40020040
+ 8003158:	40020058 	.word	0x40020058
+ 800315c:	40020070 	.word	0x40020070
+ 8003160:	40020088 	.word	0x40020088
+ 8003164:	400200a0 	.word	0x400200a0
+ 8003168:	400200b8 	.word	0x400200b8
+ 800316c:	40020410 	.word	0x40020410
+ 8003170:	40020428 	.word	0x40020428
+ 8003174:	40020440 	.word	0x40020440
+ 8003178:	40020458 	.word	0x40020458
+ 800317c:	40020470 	.word	0x40020470
+ 8003180:	40020488 	.word	0x40020488
+ 8003184:	400204a0 	.word	0x400204a0
+ 8003188:	400204b8 	.word	0x400204b8
+ 800318c:	687b      	ldr	r3, [r7, #4]
+ 800318e:	681b      	ldr	r3, [r3, #0]
+ 8003190:	681b      	ldr	r3, [r3, #0]
+ 8003192:	2300      	movs	r3, #0
+ 8003194:	2b00      	cmp	r3, #0
+ 8003196:	d00d      	beq.n	80031b4 <HAL_DMA_IRQHandler+0x460>
+      {
+        /* Clear the direct mode error flag */
+        regs_dma->IFCR = DMA_FLAG_DMEIF0_4 << (hdma->StreamIndex & 0x1FU);
+ 8003198:	687b      	ldr	r3, [r7, #4]
+ 800319a:	6ddb      	ldr	r3, [r3, #92]	; 0x5c
+ 800319c:	f003 031f 	and.w	r3, r3, #31
+ 80031a0:	2204      	movs	r2, #4
+ 80031a2:	409a      	lsls	r2, r3
+ 80031a4:	6a3b      	ldr	r3, [r7, #32]
+ 80031a6:	609a      	str	r2, [r3, #8]
+
+        /* Update error code */
+        hdma->ErrorCode |= HAL_DMA_ERROR_DME;
+ 80031a8:	687b      	ldr	r3, [r7, #4]
+ 80031aa:	6d5b      	ldr	r3, [r3, #84]	; 0x54
+ 80031ac:	f043 0204 	orr.w	r2, r3, #4
+ 80031b0:	687b      	ldr	r3, [r7, #4]
+ 80031b2:	655a      	str	r2, [r3, #84]	; 0x54
+      }
+    }
+    /* Half Transfer Complete Interrupt management ******************************/
+    if ((tmpisr_dma & (DMA_FLAG_HTIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U)
+ 80031b4:	687b      	ldr	r3, [r7, #4]
+ 80031b6:	6ddb      	ldr	r3, [r3, #92]	; 0x5c
+ 80031b8:	f003 031f 	and.w	r3, r3, #31
+ 80031bc:	2210      	movs	r2, #16
+ 80031be:	409a      	lsls	r2, r3
+ 80031c0:	69bb      	ldr	r3, [r7, #24]
+ 80031c2:	4013      	ands	r3, r2
+ 80031c4:	2b00      	cmp	r3, #0
+ 80031c6:	f000 80a6 	beq.w	8003316 <HAL_DMA_IRQHandler+0x5c2>
+    {
+      if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != 0U)
+ 80031ca:	687b      	ldr	r3, [r7, #4]
+ 80031cc:	681b      	ldr	r3, [r3, #0]
+ 80031ce:	4a85      	ldr	r2, [pc, #532]	; (80033e4 <HAL_DMA_IRQHandler+0x690>)
+ 80031d0:	4293      	cmp	r3, r2
+ 80031d2:	d04a      	beq.n	800326a <HAL_DMA_IRQHandler+0x516>
+ 80031d4:	687b      	ldr	r3, [r7, #4]
+ 80031d6:	681b      	ldr	r3, [r3, #0]
+ 80031d8:	4a83      	ldr	r2, [pc, #524]	; (80033e8 <HAL_DMA_IRQHandler+0x694>)
+ 80031da:	4293      	cmp	r3, r2
+ 80031dc:	d045      	beq.n	800326a <HAL_DMA_IRQHandler+0x516>
+ 80031de:	687b      	ldr	r3, [r7, #4]
+ 80031e0:	681b      	ldr	r3, [r3, #0]
+ 80031e2:	4a82      	ldr	r2, [pc, #520]	; (80033ec <HAL_DMA_IRQHandler+0x698>)
+ 80031e4:	4293      	cmp	r3, r2
+ 80031e6:	d040      	beq.n	800326a <HAL_DMA_IRQHandler+0x516>
+ 80031e8:	687b      	ldr	r3, [r7, #4]
+ 80031ea:	681b      	ldr	r3, [r3, #0]
+ 80031ec:	4a80      	ldr	r2, [pc, #512]	; (80033f0 <HAL_DMA_IRQHandler+0x69c>)
+ 80031ee:	4293      	cmp	r3, r2
+ 80031f0:	d03b      	beq.n	800326a <HAL_DMA_IRQHandler+0x516>
+ 80031f2:	687b      	ldr	r3, [r7, #4]
+ 80031f4:	681b      	ldr	r3, [r3, #0]
+ 80031f6:	4a7f      	ldr	r2, [pc, #508]	; (80033f4 <HAL_DMA_IRQHandler+0x6a0>)
+ 80031f8:	4293      	cmp	r3, r2
+ 80031fa:	d036      	beq.n	800326a <HAL_DMA_IRQHandler+0x516>
+ 80031fc:	687b      	ldr	r3, [r7, #4]
+ 80031fe:	681b      	ldr	r3, [r3, #0]
+ 8003200:	4a7d      	ldr	r2, [pc, #500]	; (80033f8 <HAL_DMA_IRQHandler+0x6a4>)
+ 8003202:	4293      	cmp	r3, r2
+ 8003204:	d031      	beq.n	800326a <HAL_DMA_IRQHandler+0x516>
+ 8003206:	687b      	ldr	r3, [r7, #4]
+ 8003208:	681b      	ldr	r3, [r3, #0]
+ 800320a:	4a7c      	ldr	r2, [pc, #496]	; (80033fc <HAL_DMA_IRQHandler+0x6a8>)
+ 800320c:	4293      	cmp	r3, r2
+ 800320e:	d02c      	beq.n	800326a <HAL_DMA_IRQHandler+0x516>
+ 8003210:	687b      	ldr	r3, [r7, #4]
+ 8003212:	681b      	ldr	r3, [r3, #0]
+ 8003214:	4a7a      	ldr	r2, [pc, #488]	; (8003400 <HAL_DMA_IRQHandler+0x6ac>)
+ 8003216:	4293      	cmp	r3, r2
+ 8003218:	d027      	beq.n	800326a <HAL_DMA_IRQHandler+0x516>
+ 800321a:	687b      	ldr	r3, [r7, #4]
+ 800321c:	681b      	ldr	r3, [r3, #0]
+ 800321e:	4a79      	ldr	r2, [pc, #484]	; (8003404 <HAL_DMA_IRQHandler+0x6b0>)
+ 8003220:	4293      	cmp	r3, r2
+ 8003222:	d022      	beq.n	800326a <HAL_DMA_IRQHandler+0x516>
+ 8003224:	687b      	ldr	r3, [r7, #4]
+ 8003226:	681b      	ldr	r3, [r3, #0]
+ 8003228:	4a77      	ldr	r2, [pc, #476]	; (8003408 <HAL_DMA_IRQHandler+0x6b4>)
+ 800322a:	4293      	cmp	r3, r2
+ 800322c:	d01d      	beq.n	800326a <HAL_DMA_IRQHandler+0x516>
+ 800322e:	687b      	ldr	r3, [r7, #4]
+ 8003230:	681b      	ldr	r3, [r3, #0]
+ 8003232:	4a76      	ldr	r2, [pc, #472]	; (800340c <HAL_DMA_IRQHandler+0x6b8>)
+ 8003234:	4293      	cmp	r3, r2
+ 8003236:	d018      	beq.n	800326a <HAL_DMA_IRQHandler+0x516>
+ 8003238:	687b      	ldr	r3, [r7, #4]
+ 800323a:	681b      	ldr	r3, [r3, #0]
+ 800323c:	4a74      	ldr	r2, [pc, #464]	; (8003410 <HAL_DMA_IRQHandler+0x6bc>)
+ 800323e:	4293      	cmp	r3, r2
+ 8003240:	d013      	beq.n	800326a <HAL_DMA_IRQHandler+0x516>
+ 8003242:	687b      	ldr	r3, [r7, #4]
+ 8003244:	681b      	ldr	r3, [r3, #0]
+ 8003246:	4a73      	ldr	r2, [pc, #460]	; (8003414 <HAL_DMA_IRQHandler+0x6c0>)
+ 8003248:	4293      	cmp	r3, r2
+ 800324a:	d00e      	beq.n	800326a <HAL_DMA_IRQHandler+0x516>
+ 800324c:	687b      	ldr	r3, [r7, #4]
+ 800324e:	681b      	ldr	r3, [r3, #0]
+ 8003250:	4a71      	ldr	r2, [pc, #452]	; (8003418 <HAL_DMA_IRQHandler+0x6c4>)
+ 8003252:	4293      	cmp	r3, r2
+ 8003254:	d009      	beq.n	800326a <HAL_DMA_IRQHandler+0x516>
+ 8003256:	687b      	ldr	r3, [r7, #4]
+ 8003258:	681b      	ldr	r3, [r3, #0]
+ 800325a:	4a70      	ldr	r2, [pc, #448]	; (800341c <HAL_DMA_IRQHandler+0x6c8>)
+ 800325c:	4293      	cmp	r3, r2
+ 800325e:	d004      	beq.n	800326a <HAL_DMA_IRQHandler+0x516>
+ 8003260:	687b      	ldr	r3, [r7, #4]
+ 8003262:	681b      	ldr	r3, [r3, #0]
+ 8003264:	4a6e      	ldr	r2, [pc, #440]	; (8003420 <HAL_DMA_IRQHandler+0x6cc>)
+ 8003266:	4293      	cmp	r3, r2
+ 8003268:	d10a      	bne.n	8003280 <HAL_DMA_IRQHandler+0x52c>
+ 800326a:	687b      	ldr	r3, [r7, #4]
+ 800326c:	681b      	ldr	r3, [r3, #0]
+ 800326e:	681b      	ldr	r3, [r3, #0]
+ 8003270:	f003 0308 	and.w	r3, r3, #8
+ 8003274:	2b00      	cmp	r3, #0
+ 8003276:	bf14      	ite	ne
+ 8003278:	2301      	movne	r3, #1
+ 800327a:	2300      	moveq	r3, #0
+ 800327c:	b2db      	uxtb	r3, r3
+ 800327e:	e009      	b.n	8003294 <HAL_DMA_IRQHandler+0x540>
+ 8003280:	687b      	ldr	r3, [r7, #4]
+ 8003282:	681b      	ldr	r3, [r3, #0]
+ 8003284:	681b      	ldr	r3, [r3, #0]
+ 8003286:	f003 0304 	and.w	r3, r3, #4
+ 800328a:	2b00      	cmp	r3, #0
+ 800328c:	bf14      	ite	ne
+ 800328e:	2301      	movne	r3, #1
+ 8003290:	2300      	moveq	r3, #0
+ 8003292:	b2db      	uxtb	r3, r3
+ 8003294:	2b00      	cmp	r3, #0
+ 8003296:	d03e      	beq.n	8003316 <HAL_DMA_IRQHandler+0x5c2>
+      {
+        /* Clear the half transfer complete flag */
+        regs_dma->IFCR = DMA_FLAG_HTIF0_4 << (hdma->StreamIndex & 0x1FU);
+ 8003298:	687b      	ldr	r3, [r7, #4]
+ 800329a:	6ddb      	ldr	r3, [r3, #92]	; 0x5c
+ 800329c:	f003 031f 	and.w	r3, r3, #31
+ 80032a0:	2210      	movs	r2, #16
+ 80032a2:	409a      	lsls	r2, r3
+ 80032a4:	6a3b      	ldr	r3, [r7, #32]
+ 80032a6:	609a      	str	r2, [r3, #8]
+
+        /* Multi_Buffering mode enabled */
+        if(((((DMA_Stream_TypeDef   *)hdma->Instance)->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0U)
+ 80032a8:	687b      	ldr	r3, [r7, #4]
+ 80032aa:	681b      	ldr	r3, [r3, #0]
+ 80032ac:	681b      	ldr	r3, [r3, #0]
+ 80032ae:	f403 2380 	and.w	r3, r3, #262144	; 0x40000
+ 80032b2:	2b00      	cmp	r3, #0
+ 80032b4:	d018      	beq.n	80032e8 <HAL_DMA_IRQHandler+0x594>
+        {
+          /* Current memory buffer used is Memory 0 */
+          if((((DMA_Stream_TypeDef   *)hdma->Instance)->CR & DMA_SxCR_CT) == 0U)
+ 80032b6:	687b      	ldr	r3, [r7, #4]
+ 80032b8:	681b      	ldr	r3, [r3, #0]
+ 80032ba:	681b      	ldr	r3, [r3, #0]
+ 80032bc:	f403 2300 	and.w	r3, r3, #524288	; 0x80000
+ 80032c0:	2b00      	cmp	r3, #0
+ 80032c2:	d108      	bne.n	80032d6 <HAL_DMA_IRQHandler+0x582>
+          {
+            if(hdma->XferHalfCpltCallback != NULL)
+ 80032c4:	687b      	ldr	r3, [r7, #4]
+ 80032c6:	6c1b      	ldr	r3, [r3, #64]	; 0x40
+ 80032c8:	2b00      	cmp	r3, #0
+ 80032ca:	d024      	beq.n	8003316 <HAL_DMA_IRQHandler+0x5c2>
+            {
+              /* Half transfer callback */
+              hdma->XferHalfCpltCallback(hdma);
+ 80032cc:	687b      	ldr	r3, [r7, #4]
+ 80032ce:	6c1b      	ldr	r3, [r3, #64]	; 0x40
+ 80032d0:	6878      	ldr	r0, [r7, #4]
+ 80032d2:	4798      	blx	r3
+ 80032d4:	e01f      	b.n	8003316 <HAL_DMA_IRQHandler+0x5c2>
+            }
+          }
+          /* Current memory buffer used is Memory 1 */
+          else
+          {
+            if(hdma->XferM1HalfCpltCallback != NULL)
+ 80032d6:	687b      	ldr	r3, [r7, #4]
+ 80032d8:	6c9b      	ldr	r3, [r3, #72]	; 0x48
+ 80032da:	2b00      	cmp	r3, #0
+ 80032dc:	d01b      	beq.n	8003316 <HAL_DMA_IRQHandler+0x5c2>
+            {
+              /* Half transfer callback */
+              hdma->XferM1HalfCpltCallback(hdma);
+ 80032de:	687b      	ldr	r3, [r7, #4]
+ 80032e0:	6c9b      	ldr	r3, [r3, #72]	; 0x48
+ 80032e2:	6878      	ldr	r0, [r7, #4]
+ 80032e4:	4798      	blx	r3
+ 80032e6:	e016      	b.n	8003316 <HAL_DMA_IRQHandler+0x5c2>
+          }
+        }
+        else
+        {
+          /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
+          if((((DMA_Stream_TypeDef   *)hdma->Instance)->CR & DMA_SxCR_CIRC) == 0U)
+ 80032e8:	687b      	ldr	r3, [r7, #4]
+ 80032ea:	681b      	ldr	r3, [r3, #0]
+ 80032ec:	681b      	ldr	r3, [r3, #0]
+ 80032ee:	f403 7380 	and.w	r3, r3, #256	; 0x100
+ 80032f2:	2b00      	cmp	r3, #0
+ 80032f4:	d107      	bne.n	8003306 <HAL_DMA_IRQHandler+0x5b2>
+          {
+            /* Disable the half transfer interrupt */
+            ((DMA_Stream_TypeDef   *)hdma->Instance)->CR  &= ~(DMA_IT_HT);
+ 80032f6:	687b      	ldr	r3, [r7, #4]
+ 80032f8:	681b      	ldr	r3, [r3, #0]
+ 80032fa:	681a      	ldr	r2, [r3, #0]
+ 80032fc:	687b      	ldr	r3, [r7, #4]
+ 80032fe:	681b      	ldr	r3, [r3, #0]
+ 8003300:	f022 0208 	bic.w	r2, r2, #8
+ 8003304:	601a      	str	r2, [r3, #0]
+          }
+
+          if(hdma->XferHalfCpltCallback != NULL)
+ 8003306:	687b      	ldr	r3, [r7, #4]
+ 8003308:	6c1b      	ldr	r3, [r3, #64]	; 0x40
+ 800330a:	2b00      	cmp	r3, #0
+ 800330c:	d003      	beq.n	8003316 <HAL_DMA_IRQHandler+0x5c2>
+          {
+            /* Half transfer callback */
+            hdma->XferHalfCpltCallback(hdma);
+ 800330e:	687b      	ldr	r3, [r7, #4]
+ 8003310:	6c1b      	ldr	r3, [r3, #64]	; 0x40
+ 8003312:	6878      	ldr	r0, [r7, #4]
+ 8003314:	4798      	blx	r3
+          }
+        }
+      }
+    }
+    /* Transfer Complete Interrupt management ***********************************/
+    if ((tmpisr_dma & (DMA_FLAG_TCIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U)
+ 8003316:	687b      	ldr	r3, [r7, #4]
+ 8003318:	6ddb      	ldr	r3, [r3, #92]	; 0x5c
+ 800331a:	f003 031f 	and.w	r3, r3, #31
+ 800331e:	2220      	movs	r2, #32
+ 8003320:	409a      	lsls	r2, r3
+ 8003322:	69bb      	ldr	r3, [r7, #24]
+ 8003324:	4013      	ands	r3, r2
+ 8003326:	2b00      	cmp	r3, #0
+ 8003328:	f000 8110 	beq.w	800354c <HAL_DMA_IRQHandler+0x7f8>
+    {
+      if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != 0U)
+ 800332c:	687b      	ldr	r3, [r7, #4]
+ 800332e:	681b      	ldr	r3, [r3, #0]
+ 8003330:	4a2c      	ldr	r2, [pc, #176]	; (80033e4 <HAL_DMA_IRQHandler+0x690>)
+ 8003332:	4293      	cmp	r3, r2
+ 8003334:	d04a      	beq.n	80033cc <HAL_DMA_IRQHandler+0x678>
+ 8003336:	687b      	ldr	r3, [r7, #4]
+ 8003338:	681b      	ldr	r3, [r3, #0]
+ 800333a:	4a2b      	ldr	r2, [pc, #172]	; (80033e8 <HAL_DMA_IRQHandler+0x694>)
+ 800333c:	4293      	cmp	r3, r2
+ 800333e:	d045      	beq.n	80033cc <HAL_DMA_IRQHandler+0x678>
+ 8003340:	687b      	ldr	r3, [r7, #4]
+ 8003342:	681b      	ldr	r3, [r3, #0]
+ 8003344:	4a29      	ldr	r2, [pc, #164]	; (80033ec <HAL_DMA_IRQHandler+0x698>)
+ 8003346:	4293      	cmp	r3, r2
+ 8003348:	d040      	beq.n	80033cc <HAL_DMA_IRQHandler+0x678>
+ 800334a:	687b      	ldr	r3, [r7, #4]
+ 800334c:	681b      	ldr	r3, [r3, #0]
+ 800334e:	4a28      	ldr	r2, [pc, #160]	; (80033f0 <HAL_DMA_IRQHandler+0x69c>)
+ 8003350:	4293      	cmp	r3, r2
+ 8003352:	d03b      	beq.n	80033cc <HAL_DMA_IRQHandler+0x678>
+ 8003354:	687b      	ldr	r3, [r7, #4]
+ 8003356:	681b      	ldr	r3, [r3, #0]
+ 8003358:	4a26      	ldr	r2, [pc, #152]	; (80033f4 <HAL_DMA_IRQHandler+0x6a0>)
+ 800335a:	4293      	cmp	r3, r2
+ 800335c:	d036      	beq.n	80033cc <HAL_DMA_IRQHandler+0x678>
+ 800335e:	687b      	ldr	r3, [r7, #4]
+ 8003360:	681b      	ldr	r3, [r3, #0]
+ 8003362:	4a25      	ldr	r2, [pc, #148]	; (80033f8 <HAL_DMA_IRQHandler+0x6a4>)
+ 8003364:	4293      	cmp	r3, r2
+ 8003366:	d031      	beq.n	80033cc <HAL_DMA_IRQHandler+0x678>
+ 8003368:	687b      	ldr	r3, [r7, #4]
+ 800336a:	681b      	ldr	r3, [r3, #0]
+ 800336c:	4a23      	ldr	r2, [pc, #140]	; (80033fc <HAL_DMA_IRQHandler+0x6a8>)
+ 800336e:	4293      	cmp	r3, r2
+ 8003370:	d02c      	beq.n	80033cc <HAL_DMA_IRQHandler+0x678>
+ 8003372:	687b      	ldr	r3, [r7, #4]
+ 8003374:	681b      	ldr	r3, [r3, #0]
+ 8003376:	4a22      	ldr	r2, [pc, #136]	; (8003400 <HAL_DMA_IRQHandler+0x6ac>)
+ 8003378:	4293      	cmp	r3, r2
+ 800337a:	d027      	beq.n	80033cc <HAL_DMA_IRQHandler+0x678>
+ 800337c:	687b      	ldr	r3, [r7, #4]
+ 800337e:	681b      	ldr	r3, [r3, #0]
+ 8003380:	4a20      	ldr	r2, [pc, #128]	; (8003404 <HAL_DMA_IRQHandler+0x6b0>)
+ 8003382:	4293      	cmp	r3, r2
+ 8003384:	d022      	beq.n	80033cc <HAL_DMA_IRQHandler+0x678>
+ 8003386:	687b      	ldr	r3, [r7, #4]
+ 8003388:	681b      	ldr	r3, [r3, #0]
+ 800338a:	4a1f      	ldr	r2, [pc, #124]	; (8003408 <HAL_DMA_IRQHandler+0x6b4>)
+ 800338c:	4293      	cmp	r3, r2
+ 800338e:	d01d      	beq.n	80033cc <HAL_DMA_IRQHandler+0x678>
+ 8003390:	687b      	ldr	r3, [r7, #4]
+ 8003392:	681b      	ldr	r3, [r3, #0]
+ 8003394:	4a1d      	ldr	r2, [pc, #116]	; (800340c <HAL_DMA_IRQHandler+0x6b8>)
+ 8003396:	4293      	cmp	r3, r2
+ 8003398:	d018      	beq.n	80033cc <HAL_DMA_IRQHandler+0x678>
+ 800339a:	687b      	ldr	r3, [r7, #4]
+ 800339c:	681b      	ldr	r3, [r3, #0]
+ 800339e:	4a1c      	ldr	r2, [pc, #112]	; (8003410 <HAL_DMA_IRQHandler+0x6bc>)
+ 80033a0:	4293      	cmp	r3, r2
+ 80033a2:	d013      	beq.n	80033cc <HAL_DMA_IRQHandler+0x678>
+ 80033a4:	687b      	ldr	r3, [r7, #4]
+ 80033a6:	681b      	ldr	r3, [r3, #0]
+ 80033a8:	4a1a      	ldr	r2, [pc, #104]	; (8003414 <HAL_DMA_IRQHandler+0x6c0>)
+ 80033aa:	4293      	cmp	r3, r2
+ 80033ac:	d00e      	beq.n	80033cc <HAL_DMA_IRQHandler+0x678>
+ 80033ae:	687b      	ldr	r3, [r7, #4]
+ 80033b0:	681b      	ldr	r3, [r3, #0]
+ 80033b2:	4a19      	ldr	r2, [pc, #100]	; (8003418 <HAL_DMA_IRQHandler+0x6c4>)
+ 80033b4:	4293      	cmp	r3, r2
+ 80033b6:	d009      	beq.n	80033cc <HAL_DMA_IRQHandler+0x678>
+ 80033b8:	687b      	ldr	r3, [r7, #4]
+ 80033ba:	681b      	ldr	r3, [r3, #0]
+ 80033bc:	4a17      	ldr	r2, [pc, #92]	; (800341c <HAL_DMA_IRQHandler+0x6c8>)
+ 80033be:	4293      	cmp	r3, r2
+ 80033c0:	d004      	beq.n	80033cc <HAL_DMA_IRQHandler+0x678>
+ 80033c2:	687b      	ldr	r3, [r7, #4]
+ 80033c4:	681b      	ldr	r3, [r3, #0]
+ 80033c6:	4a16      	ldr	r2, [pc, #88]	; (8003420 <HAL_DMA_IRQHandler+0x6cc>)
+ 80033c8:	4293      	cmp	r3, r2
+ 80033ca:	d12b      	bne.n	8003424 <HAL_DMA_IRQHandler+0x6d0>
+ 80033cc:	687b      	ldr	r3, [r7, #4]
+ 80033ce:	681b      	ldr	r3, [r3, #0]
+ 80033d0:	681b      	ldr	r3, [r3, #0]
+ 80033d2:	f003 0310 	and.w	r3, r3, #16
+ 80033d6:	2b00      	cmp	r3, #0
+ 80033d8:	bf14      	ite	ne
+ 80033da:	2301      	movne	r3, #1
+ 80033dc:	2300      	moveq	r3, #0
+ 80033de:	b2db      	uxtb	r3, r3
+ 80033e0:	e02a      	b.n	8003438 <HAL_DMA_IRQHandler+0x6e4>
+ 80033e2:	bf00      	nop
+ 80033e4:	40020010 	.word	0x40020010
+ 80033e8:	40020028 	.word	0x40020028
+ 80033ec:	40020040 	.word	0x40020040
+ 80033f0:	40020058 	.word	0x40020058
+ 80033f4:	40020070 	.word	0x40020070
+ 80033f8:	40020088 	.word	0x40020088
+ 80033fc:	400200a0 	.word	0x400200a0
+ 8003400:	400200b8 	.word	0x400200b8
+ 8003404:	40020410 	.word	0x40020410
+ 8003408:	40020428 	.word	0x40020428
+ 800340c:	40020440 	.word	0x40020440
+ 8003410:	40020458 	.word	0x40020458
+ 8003414:	40020470 	.word	0x40020470
+ 8003418:	40020488 	.word	0x40020488
+ 800341c:	400204a0 	.word	0x400204a0
+ 8003420:	400204b8 	.word	0x400204b8
+ 8003424:	687b      	ldr	r3, [r7, #4]
+ 8003426:	681b      	ldr	r3, [r3, #0]
+ 8003428:	681b      	ldr	r3, [r3, #0]
+ 800342a:	f003 0302 	and.w	r3, r3, #2
+ 800342e:	2b00      	cmp	r3, #0
+ 8003430:	bf14      	ite	ne
+ 8003432:	2301      	movne	r3, #1
+ 8003434:	2300      	moveq	r3, #0
+ 8003436:	b2db      	uxtb	r3, r3
+ 8003438:	2b00      	cmp	r3, #0
+ 800343a:	f000 8087 	beq.w	800354c <HAL_DMA_IRQHandler+0x7f8>
+      {
+        /* Clear the transfer complete flag */
+        regs_dma->IFCR = DMA_FLAG_TCIF0_4 << (hdma->StreamIndex & 0x1FU);
+ 800343e:	687b      	ldr	r3, [r7, #4]
+ 8003440:	6ddb      	ldr	r3, [r3, #92]	; 0x5c
+ 8003442:	f003 031f 	and.w	r3, r3, #31
+ 8003446:	2220      	movs	r2, #32
+ 8003448:	409a      	lsls	r2, r3
+ 800344a:	6a3b      	ldr	r3, [r7, #32]
+ 800344c:	609a      	str	r2, [r3, #8]
+
+        if(HAL_DMA_STATE_ABORT == hdma->State)
+ 800344e:	687b      	ldr	r3, [r7, #4]
+ 8003450:	f893 3035 	ldrb.w	r3, [r3, #53]	; 0x35
+ 8003454:	b2db      	uxtb	r3, r3
+ 8003456:	2b04      	cmp	r3, #4
+ 8003458:	d139      	bne.n	80034ce <HAL_DMA_IRQHandler+0x77a>
+        {
+          /* Disable all the transfer interrupts */
+          ((DMA_Stream_TypeDef   *)hdma->Instance)->CR  &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME);
+ 800345a:	687b      	ldr	r3, [r7, #4]
+ 800345c:	681b      	ldr	r3, [r3, #0]
+ 800345e:	681a      	ldr	r2, [r3, #0]
+ 8003460:	687b      	ldr	r3, [r7, #4]
+ 8003462:	681b      	ldr	r3, [r3, #0]
+ 8003464:	f022 0216 	bic.w	r2, r2, #22
+ 8003468:	601a      	str	r2, [r3, #0]
+          ((DMA_Stream_TypeDef   *)hdma->Instance)->FCR &= ~(DMA_IT_FE);
+ 800346a:	687b      	ldr	r3, [r7, #4]
+ 800346c:	681b      	ldr	r3, [r3, #0]
+ 800346e:	695a      	ldr	r2, [r3, #20]
+ 8003470:	687b      	ldr	r3, [r7, #4]
+ 8003472:	681b      	ldr	r3, [r3, #0]
+ 8003474:	f022 0280 	bic.w	r2, r2, #128	; 0x80
+ 8003478:	615a      	str	r2, [r3, #20]
+
+          if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL))
+ 800347a:	687b      	ldr	r3, [r7, #4]
+ 800347c:	6c1b      	ldr	r3, [r3, #64]	; 0x40
+ 800347e:	2b00      	cmp	r3, #0
+ 8003480:	d103      	bne.n	800348a <HAL_DMA_IRQHandler+0x736>
+ 8003482:	687b      	ldr	r3, [r7, #4]
+ 8003484:	6c9b      	ldr	r3, [r3, #72]	; 0x48
+ 8003486:	2b00      	cmp	r3, #0
+ 8003488:	d007      	beq.n	800349a <HAL_DMA_IRQHandler+0x746>
+          {
+            ((DMA_Stream_TypeDef   *)hdma->Instance)->CR  &= ~(DMA_IT_HT);
+ 800348a:	687b      	ldr	r3, [r7, #4]
+ 800348c:	681b      	ldr	r3, [r3, #0]
+ 800348e:	681a      	ldr	r2, [r3, #0]
+ 8003490:	687b      	ldr	r3, [r7, #4]
+ 8003492:	681b      	ldr	r3, [r3, #0]
+ 8003494:	f022 0208 	bic.w	r2, r2, #8
+ 8003498:	601a      	str	r2, [r3, #0]
+          }
+
+          /* Clear all interrupt flags at correct offset within the register */
+          regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU);
+ 800349a:	687b      	ldr	r3, [r7, #4]
+ 800349c:	6ddb      	ldr	r3, [r3, #92]	; 0x5c
+ 800349e:	f003 031f 	and.w	r3, r3, #31
+ 80034a2:	223f      	movs	r2, #63	; 0x3f
+ 80034a4:	409a      	lsls	r2, r3
+ 80034a6:	6a3b      	ldr	r3, [r7, #32]
+ 80034a8:	609a      	str	r2, [r3, #8]
+
+          /* Change the DMA state */
+          hdma->State = HAL_DMA_STATE_READY;
+ 80034aa:	687b      	ldr	r3, [r7, #4]
+ 80034ac:	2201      	movs	r2, #1
+ 80034ae:	f883 2035 	strb.w	r2, [r3, #53]	; 0x35
+
+          /* Process Unlocked */
+          __HAL_UNLOCK(hdma);
+ 80034b2:	687b      	ldr	r3, [r7, #4]
+ 80034b4:	2200      	movs	r2, #0
+ 80034b6:	f883 2034 	strb.w	r2, [r3, #52]	; 0x34
+
+          if(hdma->XferAbortCallback != NULL)
+ 80034ba:	687b      	ldr	r3, [r7, #4]
+ 80034bc:	6d1b      	ldr	r3, [r3, #80]	; 0x50
+ 80034be:	2b00      	cmp	r3, #0
+ 80034c0:	f000 834a 	beq.w	8003b58 <HAL_DMA_IRQHandler+0xe04>
+          {
+            hdma->XferAbortCallback(hdma);
+ 80034c4:	687b      	ldr	r3, [r7, #4]
+ 80034c6:	6d1b      	ldr	r3, [r3, #80]	; 0x50
+ 80034c8:	6878      	ldr	r0, [r7, #4]
+ 80034ca:	4798      	blx	r3
+          }
+          return;
+ 80034cc:	e344      	b.n	8003b58 <HAL_DMA_IRQHandler+0xe04>
+        }
+
+        if(((((DMA_Stream_TypeDef   *)hdma->Instance)->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0U)
+ 80034ce:	687b      	ldr	r3, [r7, #4]
+ 80034d0:	681b      	ldr	r3, [r3, #0]
+ 80034d2:	681b      	ldr	r3, [r3, #0]
+ 80034d4:	f403 2380 	and.w	r3, r3, #262144	; 0x40000
+ 80034d8:	2b00      	cmp	r3, #0
+ 80034da:	d018      	beq.n	800350e <HAL_DMA_IRQHandler+0x7ba>
+        {
+          /* Current memory buffer used is Memory 0 */
+          if((((DMA_Stream_TypeDef   *)hdma->Instance)->CR & DMA_SxCR_CT) == 0U)
+ 80034dc:	687b      	ldr	r3, [r7, #4]
+ 80034de:	681b      	ldr	r3, [r3, #0]
+ 80034e0:	681b      	ldr	r3, [r3, #0]
+ 80034e2:	f403 2300 	and.w	r3, r3, #524288	; 0x80000
+ 80034e6:	2b00      	cmp	r3, #0
+ 80034e8:	d108      	bne.n	80034fc <HAL_DMA_IRQHandler+0x7a8>
+          {
+            if(hdma->XferM1CpltCallback != NULL)
+ 80034ea:	687b      	ldr	r3, [r7, #4]
+ 80034ec:	6c5b      	ldr	r3, [r3, #68]	; 0x44
+ 80034ee:	2b00      	cmp	r3, #0
+ 80034f0:	d02c      	beq.n	800354c <HAL_DMA_IRQHandler+0x7f8>
+            {
+              /* Transfer complete Callback for memory1 */
+              hdma->XferM1CpltCallback(hdma);
+ 80034f2:	687b      	ldr	r3, [r7, #4]
+ 80034f4:	6c5b      	ldr	r3, [r3, #68]	; 0x44
+ 80034f6:	6878      	ldr	r0, [r7, #4]
+ 80034f8:	4798      	blx	r3
+ 80034fa:	e027      	b.n	800354c <HAL_DMA_IRQHandler+0x7f8>
+            }
+          }
+          /* Current memory buffer used is Memory 1 */
+          else
+          {
+            if(hdma->XferCpltCallback != NULL)
+ 80034fc:	687b      	ldr	r3, [r7, #4]
+ 80034fe:	6bdb      	ldr	r3, [r3, #60]	; 0x3c
+ 8003500:	2b00      	cmp	r3, #0
+ 8003502:	d023      	beq.n	800354c <HAL_DMA_IRQHandler+0x7f8>
+            {
+              /* Transfer complete Callback for memory0 */
+              hdma->XferCpltCallback(hdma);
+ 8003504:	687b      	ldr	r3, [r7, #4]
+ 8003506:	6bdb      	ldr	r3, [r3, #60]	; 0x3c
+ 8003508:	6878      	ldr	r0, [r7, #4]
+ 800350a:	4798      	blx	r3
+ 800350c:	e01e      	b.n	800354c <HAL_DMA_IRQHandler+0x7f8>
+          }
+        }
+        /* Disable the transfer complete interrupt if the DMA mode is not CIRCULAR */
+        else
+        {
+          if((((DMA_Stream_TypeDef   *)hdma->Instance)->CR & DMA_SxCR_CIRC) == 0U)
+ 800350e:	687b      	ldr	r3, [r7, #4]
+ 8003510:	681b      	ldr	r3, [r3, #0]
+ 8003512:	681b      	ldr	r3, [r3, #0]
+ 8003514:	f403 7380 	and.w	r3, r3, #256	; 0x100
+ 8003518:	2b00      	cmp	r3, #0
+ 800351a:	d10f      	bne.n	800353c <HAL_DMA_IRQHandler+0x7e8>
+          {
+            /* Disable the transfer complete interrupt */
+            ((DMA_Stream_TypeDef   *)hdma->Instance)->CR  &= ~(DMA_IT_TC);
+ 800351c:	687b      	ldr	r3, [r7, #4]
+ 800351e:	681b      	ldr	r3, [r3, #0]
+ 8003520:	681a      	ldr	r2, [r3, #0]
+ 8003522:	687b      	ldr	r3, [r7, #4]
+ 8003524:	681b      	ldr	r3, [r3, #0]
+ 8003526:	f022 0210 	bic.w	r2, r2, #16
+ 800352a:	601a      	str	r2, [r3, #0]
+
+            /* Change the DMA state */
+            hdma->State = HAL_DMA_STATE_READY;
+ 800352c:	687b      	ldr	r3, [r7, #4]
+ 800352e:	2201      	movs	r2, #1
+ 8003530:	f883 2035 	strb.w	r2, [r3, #53]	; 0x35
+
+            /* Process Unlocked */
+            __HAL_UNLOCK(hdma);
+ 8003534:	687b      	ldr	r3, [r7, #4]
+ 8003536:	2200      	movs	r2, #0
+ 8003538:	f883 2034 	strb.w	r2, [r3, #52]	; 0x34
+          }
+
+          if(hdma->XferCpltCallback != NULL)
+ 800353c:	687b      	ldr	r3, [r7, #4]
+ 800353e:	6bdb      	ldr	r3, [r3, #60]	; 0x3c
+ 8003540:	2b00      	cmp	r3, #0
+ 8003542:	d003      	beq.n	800354c <HAL_DMA_IRQHandler+0x7f8>
+          {
+            /* Transfer complete callback */
+            hdma->XferCpltCallback(hdma);
+ 8003544:	687b      	ldr	r3, [r7, #4]
+ 8003546:	6bdb      	ldr	r3, [r3, #60]	; 0x3c
+ 8003548:	6878      	ldr	r0, [r7, #4]
+ 800354a:	4798      	blx	r3
+        }
+      }
+    }
+
+    /* manage error case */
+    if(hdma->ErrorCode != HAL_DMA_ERROR_NONE)
+ 800354c:	687b      	ldr	r3, [r7, #4]
+ 800354e:	6d5b      	ldr	r3, [r3, #84]	; 0x54
+ 8003550:	2b00      	cmp	r3, #0
+ 8003552:	f000 8306 	beq.w	8003b62 <HAL_DMA_IRQHandler+0xe0e>
+    {
+      if((hdma->ErrorCode & HAL_DMA_ERROR_TE) != 0U)
+ 8003556:	687b      	ldr	r3, [r7, #4]
+ 8003558:	6d5b      	ldr	r3, [r3, #84]	; 0x54
+ 800355a:	f003 0301 	and.w	r3, r3, #1
+ 800355e:	2b00      	cmp	r3, #0
+ 8003560:	f000 8088 	beq.w	8003674 <HAL_DMA_IRQHandler+0x920>
+      {
+        hdma->State = HAL_DMA_STATE_ABORT;
+ 8003564:	687b      	ldr	r3, [r7, #4]
+ 8003566:	2204      	movs	r2, #4
+ 8003568:	f883 2035 	strb.w	r2, [r3, #53]	; 0x35
+
+        /* Disable the stream */
+        __HAL_DMA_DISABLE(hdma);
+ 800356c:	687b      	ldr	r3, [r7, #4]
+ 800356e:	681b      	ldr	r3, [r3, #0]
+ 8003570:	4a7a      	ldr	r2, [pc, #488]	; (800375c <HAL_DMA_IRQHandler+0xa08>)
+ 8003572:	4293      	cmp	r3, r2
+ 8003574:	d04a      	beq.n	800360c <HAL_DMA_IRQHandler+0x8b8>
+ 8003576:	687b      	ldr	r3, [r7, #4]
+ 8003578:	681b      	ldr	r3, [r3, #0]
+ 800357a:	4a79      	ldr	r2, [pc, #484]	; (8003760 <HAL_DMA_IRQHandler+0xa0c>)
+ 800357c:	4293      	cmp	r3, r2
+ 800357e:	d045      	beq.n	800360c <HAL_DMA_IRQHandler+0x8b8>
+ 8003580:	687b      	ldr	r3, [r7, #4]
+ 8003582:	681b      	ldr	r3, [r3, #0]
+ 8003584:	4a77      	ldr	r2, [pc, #476]	; (8003764 <HAL_DMA_IRQHandler+0xa10>)
+ 8003586:	4293      	cmp	r3, r2
+ 8003588:	d040      	beq.n	800360c <HAL_DMA_IRQHandler+0x8b8>
+ 800358a:	687b      	ldr	r3, [r7, #4]
+ 800358c:	681b      	ldr	r3, [r3, #0]
+ 800358e:	4a76      	ldr	r2, [pc, #472]	; (8003768 <HAL_DMA_IRQHandler+0xa14>)
+ 8003590:	4293      	cmp	r3, r2
+ 8003592:	d03b      	beq.n	800360c <HAL_DMA_IRQHandler+0x8b8>
+ 8003594:	687b      	ldr	r3, [r7, #4]
+ 8003596:	681b      	ldr	r3, [r3, #0]
+ 8003598:	4a74      	ldr	r2, [pc, #464]	; (800376c <HAL_DMA_IRQHandler+0xa18>)
+ 800359a:	4293      	cmp	r3, r2
+ 800359c:	d036      	beq.n	800360c <HAL_DMA_IRQHandler+0x8b8>
+ 800359e:	687b      	ldr	r3, [r7, #4]
+ 80035a0:	681b      	ldr	r3, [r3, #0]
+ 80035a2:	4a73      	ldr	r2, [pc, #460]	; (8003770 <HAL_DMA_IRQHandler+0xa1c>)
+ 80035a4:	4293      	cmp	r3, r2
+ 80035a6:	d031      	beq.n	800360c <HAL_DMA_IRQHandler+0x8b8>
+ 80035a8:	687b      	ldr	r3, [r7, #4]
+ 80035aa:	681b      	ldr	r3, [r3, #0]
+ 80035ac:	4a71      	ldr	r2, [pc, #452]	; (8003774 <HAL_DMA_IRQHandler+0xa20>)
+ 80035ae:	4293      	cmp	r3, r2
+ 80035b0:	d02c      	beq.n	800360c <HAL_DMA_IRQHandler+0x8b8>
+ 80035b2:	687b      	ldr	r3, [r7, #4]
+ 80035b4:	681b      	ldr	r3, [r3, #0]
+ 80035b6:	4a70      	ldr	r2, [pc, #448]	; (8003778 <HAL_DMA_IRQHandler+0xa24>)
+ 80035b8:	4293      	cmp	r3, r2
+ 80035ba:	d027      	beq.n	800360c <HAL_DMA_IRQHandler+0x8b8>
+ 80035bc:	687b      	ldr	r3, [r7, #4]
+ 80035be:	681b      	ldr	r3, [r3, #0]
+ 80035c0:	4a6e      	ldr	r2, [pc, #440]	; (800377c <HAL_DMA_IRQHandler+0xa28>)
+ 80035c2:	4293      	cmp	r3, r2
+ 80035c4:	d022      	beq.n	800360c <HAL_DMA_IRQHandler+0x8b8>
+ 80035c6:	687b      	ldr	r3, [r7, #4]
+ 80035c8:	681b      	ldr	r3, [r3, #0]
+ 80035ca:	4a6d      	ldr	r2, [pc, #436]	; (8003780 <HAL_DMA_IRQHandler+0xa2c>)
+ 80035cc:	4293      	cmp	r3, r2
+ 80035ce:	d01d      	beq.n	800360c <HAL_DMA_IRQHandler+0x8b8>
+ 80035d0:	687b      	ldr	r3, [r7, #4]
+ 80035d2:	681b      	ldr	r3, [r3, #0]
+ 80035d4:	4a6b      	ldr	r2, [pc, #428]	; (8003784 <HAL_DMA_IRQHandler+0xa30>)
+ 80035d6:	4293      	cmp	r3, r2
+ 80035d8:	d018      	beq.n	800360c <HAL_DMA_IRQHandler+0x8b8>
+ 80035da:	687b      	ldr	r3, [r7, #4]
+ 80035dc:	681b      	ldr	r3, [r3, #0]
+ 80035de:	4a6a      	ldr	r2, [pc, #424]	; (8003788 <HAL_DMA_IRQHandler+0xa34>)
+ 80035e0:	4293      	cmp	r3, r2
+ 80035e2:	d013      	beq.n	800360c <HAL_DMA_IRQHandler+0x8b8>
+ 80035e4:	687b      	ldr	r3, [r7, #4]
+ 80035e6:	681b      	ldr	r3, [r3, #0]
+ 80035e8:	4a68      	ldr	r2, [pc, #416]	; (800378c <HAL_DMA_IRQHandler+0xa38>)
+ 80035ea:	4293      	cmp	r3, r2
+ 80035ec:	d00e      	beq.n	800360c <HAL_DMA_IRQHandler+0x8b8>
+ 80035ee:	687b      	ldr	r3, [r7, #4]
+ 80035f0:	681b      	ldr	r3, [r3, #0]
+ 80035f2:	4a67      	ldr	r2, [pc, #412]	; (8003790 <HAL_DMA_IRQHandler+0xa3c>)
+ 80035f4:	4293      	cmp	r3, r2
+ 80035f6:	d009      	beq.n	800360c <HAL_DMA_IRQHandler+0x8b8>
+ 80035f8:	687b      	ldr	r3, [r7, #4]
+ 80035fa:	681b      	ldr	r3, [r3, #0]
+ 80035fc:	4a65      	ldr	r2, [pc, #404]	; (8003794 <HAL_DMA_IRQHandler+0xa40>)
+ 80035fe:	4293      	cmp	r3, r2
+ 8003600:	d004      	beq.n	800360c <HAL_DMA_IRQHandler+0x8b8>
+ 8003602:	687b      	ldr	r3, [r7, #4]
+ 8003604:	681b      	ldr	r3, [r3, #0]
+ 8003606:	4a64      	ldr	r2, [pc, #400]	; (8003798 <HAL_DMA_IRQHandler+0xa44>)
+ 8003608:	4293      	cmp	r3, r2
+ 800360a:	d108      	bne.n	800361e <HAL_DMA_IRQHandler+0x8ca>
+ 800360c:	687b      	ldr	r3, [r7, #4]
+ 800360e:	681b      	ldr	r3, [r3, #0]
+ 8003610:	681a      	ldr	r2, [r3, #0]
+ 8003612:	687b      	ldr	r3, [r7, #4]
+ 8003614:	681b      	ldr	r3, [r3, #0]
+ 8003616:	f022 0201 	bic.w	r2, r2, #1
+ 800361a:	601a      	str	r2, [r3, #0]
+ 800361c:	e007      	b.n	800362e <HAL_DMA_IRQHandler+0x8da>
+ 800361e:	687b      	ldr	r3, [r7, #4]
+ 8003620:	681b      	ldr	r3, [r3, #0]
+ 8003622:	681a      	ldr	r2, [r3, #0]
+ 8003624:	687b      	ldr	r3, [r7, #4]
+ 8003626:	681b      	ldr	r3, [r3, #0]
+ 8003628:	f022 0201 	bic.w	r2, r2, #1
+ 800362c:	601a      	str	r2, [r3, #0]
+
+        do
+        {
+          if (++count > timeout)
+ 800362e:	68fb      	ldr	r3, [r7, #12]
+ 8003630:	3301      	adds	r3, #1
+ 8003632:	60fb      	str	r3, [r7, #12]
+ 8003634:	6a7a      	ldr	r2, [r7, #36]	; 0x24
+ 8003636:	429a      	cmp	r2, r3
+ 8003638:	d307      	bcc.n	800364a <HAL_DMA_IRQHandler+0x8f6>
+          {
+            break;
+          }
+        }
+        while((((DMA_Stream_TypeDef   *)hdma->Instance)->CR & DMA_SxCR_EN) != 0U);
+ 800363a:	687b      	ldr	r3, [r7, #4]
+ 800363c:	681b      	ldr	r3, [r3, #0]
+ 800363e:	681b      	ldr	r3, [r3, #0]
+ 8003640:	f003 0301 	and.w	r3, r3, #1
+ 8003644:	2b00      	cmp	r3, #0
+ 8003646:	d1f2      	bne.n	800362e <HAL_DMA_IRQHandler+0x8da>
+ 8003648:	e000      	b.n	800364c <HAL_DMA_IRQHandler+0x8f8>
+            break;
+ 800364a:	bf00      	nop
+
+        if((((DMA_Stream_TypeDef   *)hdma->Instance)->CR & DMA_SxCR_EN) != 0U)
+ 800364c:	687b      	ldr	r3, [r7, #4]
+ 800364e:	681b      	ldr	r3, [r3, #0]
+ 8003650:	681b      	ldr	r3, [r3, #0]
+ 8003652:	f003 0301 	and.w	r3, r3, #1
+ 8003656:	2b00      	cmp	r3, #0
+ 8003658:	d004      	beq.n	8003664 <HAL_DMA_IRQHandler+0x910>
+        {
+          /* Change the DMA state to error if DMA disable fails */
+          hdma->State = HAL_DMA_STATE_ERROR;
+ 800365a:	687b      	ldr	r3, [r7, #4]
+ 800365c:	2203      	movs	r2, #3
+ 800365e:	f883 2035 	strb.w	r2, [r3, #53]	; 0x35
+ 8003662:	e003      	b.n	800366c <HAL_DMA_IRQHandler+0x918>
+        }
+        else
+        {
+          /* Change the DMA state to Ready if DMA disable success */
+          hdma->State = HAL_DMA_STATE_READY;
+ 8003664:	687b      	ldr	r3, [r7, #4]
+ 8003666:	2201      	movs	r2, #1
+ 8003668:	f883 2035 	strb.w	r2, [r3, #53]	; 0x35
+        }
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hdma);
+ 800366c:	687b      	ldr	r3, [r7, #4]
+ 800366e:	2200      	movs	r2, #0
+ 8003670:	f883 2034 	strb.w	r2, [r3, #52]	; 0x34
+      }
+
+      if(hdma->XferErrorCallback != NULL)
+ 8003674:	687b      	ldr	r3, [r7, #4]
+ 8003676:	6cdb      	ldr	r3, [r3, #76]	; 0x4c
+ 8003678:	2b00      	cmp	r3, #0
+ 800367a:	f000 8272 	beq.w	8003b62 <HAL_DMA_IRQHandler+0xe0e>
+      {
+        /* Transfer error callback */
+        hdma->XferErrorCallback(hdma);
+ 800367e:	687b      	ldr	r3, [r7, #4]
+ 8003680:	6cdb      	ldr	r3, [r3, #76]	; 0x4c
+ 8003682:	6878      	ldr	r0, [r7, #4]
+ 8003684:	4798      	blx	r3
+ 8003686:	e26c      	b.n	8003b62 <HAL_DMA_IRQHandler+0xe0e>
+      }
+    }
+  }
+  else if(IS_BDMA_CHANNEL_INSTANCE(hdma->Instance) != 0U)  /* BDMA instance(s) */
+ 8003688:	687b      	ldr	r3, [r7, #4]
+ 800368a:	681b      	ldr	r3, [r3, #0]
+ 800368c:	4a43      	ldr	r2, [pc, #268]	; (800379c <HAL_DMA_IRQHandler+0xa48>)
+ 800368e:	4293      	cmp	r3, r2
+ 8003690:	d022      	beq.n	80036d8 <HAL_DMA_IRQHandler+0x984>
+ 8003692:	687b      	ldr	r3, [r7, #4]
+ 8003694:	681b      	ldr	r3, [r3, #0]
+ 8003696:	4a42      	ldr	r2, [pc, #264]	; (80037a0 <HAL_DMA_IRQHandler+0xa4c>)
+ 8003698:	4293      	cmp	r3, r2
+ 800369a:	d01d      	beq.n	80036d8 <HAL_DMA_IRQHandler+0x984>
+ 800369c:	687b      	ldr	r3, [r7, #4]
+ 800369e:	681b      	ldr	r3, [r3, #0]
+ 80036a0:	4a40      	ldr	r2, [pc, #256]	; (80037a4 <HAL_DMA_IRQHandler+0xa50>)
+ 80036a2:	4293      	cmp	r3, r2
+ 80036a4:	d018      	beq.n	80036d8 <HAL_DMA_IRQHandler+0x984>
+ 80036a6:	687b      	ldr	r3, [r7, #4]
+ 80036a8:	681b      	ldr	r3, [r3, #0]
+ 80036aa:	4a3f      	ldr	r2, [pc, #252]	; (80037a8 <HAL_DMA_IRQHandler+0xa54>)
+ 80036ac:	4293      	cmp	r3, r2
+ 80036ae:	d013      	beq.n	80036d8 <HAL_DMA_IRQHandler+0x984>
+ 80036b0:	687b      	ldr	r3, [r7, #4]
+ 80036b2:	681b      	ldr	r3, [r3, #0]
+ 80036b4:	4a3d      	ldr	r2, [pc, #244]	; (80037ac <HAL_DMA_IRQHandler+0xa58>)
+ 80036b6:	4293      	cmp	r3, r2
+ 80036b8:	d00e      	beq.n	80036d8 <HAL_DMA_IRQHandler+0x984>
+ 80036ba:	687b      	ldr	r3, [r7, #4]
+ 80036bc:	681b      	ldr	r3, [r3, #0]
+ 80036be:	4a3c      	ldr	r2, [pc, #240]	; (80037b0 <HAL_DMA_IRQHandler+0xa5c>)
+ 80036c0:	4293      	cmp	r3, r2
+ 80036c2:	d009      	beq.n	80036d8 <HAL_DMA_IRQHandler+0x984>
+ 80036c4:	687b      	ldr	r3, [r7, #4]
+ 80036c6:	681b      	ldr	r3, [r3, #0]
+ 80036c8:	4a3a      	ldr	r2, [pc, #232]	; (80037b4 <HAL_DMA_IRQHandler+0xa60>)
+ 80036ca:	4293      	cmp	r3, r2
+ 80036cc:	d004      	beq.n	80036d8 <HAL_DMA_IRQHandler+0x984>
+ 80036ce:	687b      	ldr	r3, [r7, #4]
+ 80036d0:	681b      	ldr	r3, [r3, #0]
+ 80036d2:	4a39      	ldr	r2, [pc, #228]	; (80037b8 <HAL_DMA_IRQHandler+0xa64>)
+ 80036d4:	4293      	cmp	r3, r2
+ 80036d6:	d101      	bne.n	80036dc <HAL_DMA_IRQHandler+0x988>
+ 80036d8:	2301      	movs	r3, #1
+ 80036da:	e000      	b.n	80036de <HAL_DMA_IRQHandler+0x98a>
+ 80036dc:	2300      	movs	r3, #0
+ 80036de:	2b00      	cmp	r3, #0
+ 80036e0:	f000 823f 	beq.w	8003b62 <HAL_DMA_IRQHandler+0xe0e>
+  {
+    ccr_reg = (((BDMA_Channel_TypeDef   *)hdma->Instance)->CCR);
+ 80036e4:	687b      	ldr	r3, [r7, #4]
+ 80036e6:	681b      	ldr	r3, [r3, #0]
+ 80036e8:	681b      	ldr	r3, [r3, #0]
+ 80036ea:	613b      	str	r3, [r7, #16]
+
+    /* Half Transfer Complete Interrupt management ******************************/
+    if (((tmpisr_bdma & (BDMA_FLAG_HT0 << (hdma->StreamIndex & 0x1FU))) != 0U) && ((ccr_reg & BDMA_CCR_HTIE) != 0U))
+ 80036ec:	687b      	ldr	r3, [r7, #4]
+ 80036ee:	6ddb      	ldr	r3, [r3, #92]	; 0x5c
+ 80036f0:	f003 031f 	and.w	r3, r3, #31
+ 80036f4:	2204      	movs	r2, #4
+ 80036f6:	409a      	lsls	r2, r3
+ 80036f8:	697b      	ldr	r3, [r7, #20]
+ 80036fa:	4013      	ands	r3, r2
+ 80036fc:	2b00      	cmp	r3, #0
+ 80036fe:	f000 80cd 	beq.w	800389c <HAL_DMA_IRQHandler+0xb48>
+ 8003702:	693b      	ldr	r3, [r7, #16]
+ 8003704:	f003 0304 	and.w	r3, r3, #4
+ 8003708:	2b00      	cmp	r3, #0
+ 800370a:	f000 80c7 	beq.w	800389c <HAL_DMA_IRQHandler+0xb48>
+    {
+      /* Clear the half transfer complete flag */
+      regs_bdma->IFCR = (BDMA_ISR_HTIF0 << (hdma->StreamIndex & 0x1FU));
+ 800370e:	687b      	ldr	r3, [r7, #4]
+ 8003710:	6ddb      	ldr	r3, [r3, #92]	; 0x5c
+ 8003712:	f003 031f 	and.w	r3, r3, #31
+ 8003716:	2204      	movs	r2, #4
+ 8003718:	409a      	lsls	r2, r3
+ 800371a:	69fb      	ldr	r3, [r7, #28]
+ 800371c:	605a      	str	r2, [r3, #4]
+
+      /* Disable the transfer complete interrupt if the DMA mode is Double Buffering */
+      if((ccr_reg & BDMA_CCR_DBM) != 0U)
+ 800371e:	693b      	ldr	r3, [r7, #16]
+ 8003720:	f403 4300 	and.w	r3, r3, #32768	; 0x8000
+ 8003724:	2b00      	cmp	r3, #0
+ 8003726:	d049      	beq.n	80037bc <HAL_DMA_IRQHandler+0xa68>
+      {
+        /* Current memory buffer used is Memory 0 */
+        if((ccr_reg & BDMA_CCR_CT) == 0U)
+ 8003728:	693b      	ldr	r3, [r7, #16]
+ 800372a:	f403 3380 	and.w	r3, r3, #65536	; 0x10000
+ 800372e:	2b00      	cmp	r3, #0
+ 8003730:	d109      	bne.n	8003746 <HAL_DMA_IRQHandler+0x9f2>
+        {
+          if(hdma->XferM1HalfCpltCallback != NULL)
+ 8003732:	687b      	ldr	r3, [r7, #4]
+ 8003734:	6c9b      	ldr	r3, [r3, #72]	; 0x48
+ 8003736:	2b00      	cmp	r3, #0
+ 8003738:	f000 8210 	beq.w	8003b5c <HAL_DMA_IRQHandler+0xe08>
+          {
+            /* Half transfer Callback for Memory 1 */
+            hdma->XferM1HalfCpltCallback(hdma);
+ 800373c:	687b      	ldr	r3, [r7, #4]
+ 800373e:	6c9b      	ldr	r3, [r3, #72]	; 0x48
+ 8003740:	6878      	ldr	r0, [r7, #4]
+ 8003742:	4798      	blx	r3
+      if((ccr_reg & BDMA_CCR_DBM) != 0U)
+ 8003744:	e20a      	b.n	8003b5c <HAL_DMA_IRQHandler+0xe08>
+          }
+        }
+        /* Current memory buffer used is Memory 1 */
+        else
+        {
+          if(hdma->XferHalfCpltCallback != NULL)
+ 8003746:	687b      	ldr	r3, [r7, #4]
+ 8003748:	6c1b      	ldr	r3, [r3, #64]	; 0x40
+ 800374a:	2b00      	cmp	r3, #0
+ 800374c:	f000 8206 	beq.w	8003b5c <HAL_DMA_IRQHandler+0xe08>
+          {
+            /* Half transfer Callback for Memory 0 */
+            hdma->XferHalfCpltCallback(hdma);
+ 8003750:	687b      	ldr	r3, [r7, #4]
+ 8003752:	6c1b      	ldr	r3, [r3, #64]	; 0x40
+ 8003754:	6878      	ldr	r0, [r7, #4]
+ 8003756:	4798      	blx	r3
+      if((ccr_reg & BDMA_CCR_DBM) != 0U)
+ 8003758:	e200      	b.n	8003b5c <HAL_DMA_IRQHandler+0xe08>
+ 800375a:	bf00      	nop
+ 800375c:	40020010 	.word	0x40020010
+ 8003760:	40020028 	.word	0x40020028
+ 8003764:	40020040 	.word	0x40020040
+ 8003768:	40020058 	.word	0x40020058
+ 800376c:	40020070 	.word	0x40020070
+ 8003770:	40020088 	.word	0x40020088
+ 8003774:	400200a0 	.word	0x400200a0
+ 8003778:	400200b8 	.word	0x400200b8
+ 800377c:	40020410 	.word	0x40020410
+ 8003780:	40020428 	.word	0x40020428
+ 8003784:	40020440 	.word	0x40020440
+ 8003788:	40020458 	.word	0x40020458
+ 800378c:	40020470 	.word	0x40020470
+ 8003790:	40020488 	.word	0x40020488
+ 8003794:	400204a0 	.word	0x400204a0
+ 8003798:	400204b8 	.word	0x400204b8
+ 800379c:	58025408 	.word	0x58025408
+ 80037a0:	5802541c 	.word	0x5802541c
+ 80037a4:	58025430 	.word	0x58025430
+ 80037a8:	58025444 	.word	0x58025444
+ 80037ac:	58025458 	.word	0x58025458
+ 80037b0:	5802546c 	.word	0x5802546c
+ 80037b4:	58025480 	.word	0x58025480
+ 80037b8:	58025494 	.word	0x58025494
+          }
+        }
+      }
+      else
+      {
+        if((ccr_reg & BDMA_CCR_CIRC) == 0U)
+ 80037bc:	693b      	ldr	r3, [r7, #16]
+ 80037be:	f003 0320 	and.w	r3, r3, #32
+ 80037c2:	2b00      	cmp	r3, #0
+ 80037c4:	d160      	bne.n	8003888 <HAL_DMA_IRQHandler+0xb34>
+        {
+          /* Disable the half transfer interrupt */
+          __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
+ 80037c6:	687b      	ldr	r3, [r7, #4]
+ 80037c8:	681b      	ldr	r3, [r3, #0]
+ 80037ca:	4a7f      	ldr	r2, [pc, #508]	; (80039c8 <HAL_DMA_IRQHandler+0xc74>)
+ 80037cc:	4293      	cmp	r3, r2
+ 80037ce:	d04a      	beq.n	8003866 <HAL_DMA_IRQHandler+0xb12>
+ 80037d0:	687b      	ldr	r3, [r7, #4]
+ 80037d2:	681b      	ldr	r3, [r3, #0]
+ 80037d4:	4a7d      	ldr	r2, [pc, #500]	; (80039cc <HAL_DMA_IRQHandler+0xc78>)
+ 80037d6:	4293      	cmp	r3, r2
+ 80037d8:	d045      	beq.n	8003866 <HAL_DMA_IRQHandler+0xb12>
+ 80037da:	687b      	ldr	r3, [r7, #4]
+ 80037dc:	681b      	ldr	r3, [r3, #0]
+ 80037de:	4a7c      	ldr	r2, [pc, #496]	; (80039d0 <HAL_DMA_IRQHandler+0xc7c>)
+ 80037e0:	4293      	cmp	r3, r2
+ 80037e2:	d040      	beq.n	8003866 <HAL_DMA_IRQHandler+0xb12>
+ 80037e4:	687b      	ldr	r3, [r7, #4]
+ 80037e6:	681b      	ldr	r3, [r3, #0]
+ 80037e8:	4a7a      	ldr	r2, [pc, #488]	; (80039d4 <HAL_DMA_IRQHandler+0xc80>)
+ 80037ea:	4293      	cmp	r3, r2
+ 80037ec:	d03b      	beq.n	8003866 <HAL_DMA_IRQHandler+0xb12>
+ 80037ee:	687b      	ldr	r3, [r7, #4]
+ 80037f0:	681b      	ldr	r3, [r3, #0]
+ 80037f2:	4a79      	ldr	r2, [pc, #484]	; (80039d8 <HAL_DMA_IRQHandler+0xc84>)
+ 80037f4:	4293      	cmp	r3, r2
+ 80037f6:	d036      	beq.n	8003866 <HAL_DMA_IRQHandler+0xb12>
+ 80037f8:	687b      	ldr	r3, [r7, #4]
+ 80037fa:	681b      	ldr	r3, [r3, #0]
+ 80037fc:	4a77      	ldr	r2, [pc, #476]	; (80039dc <HAL_DMA_IRQHandler+0xc88>)
+ 80037fe:	4293      	cmp	r3, r2
+ 8003800:	d031      	beq.n	8003866 <HAL_DMA_IRQHandler+0xb12>
+ 8003802:	687b      	ldr	r3, [r7, #4]
+ 8003804:	681b      	ldr	r3, [r3, #0]
+ 8003806:	4a76      	ldr	r2, [pc, #472]	; (80039e0 <HAL_DMA_IRQHandler+0xc8c>)
+ 8003808:	4293      	cmp	r3, r2
+ 800380a:	d02c      	beq.n	8003866 <HAL_DMA_IRQHandler+0xb12>
+ 800380c:	687b      	ldr	r3, [r7, #4]
+ 800380e:	681b      	ldr	r3, [r3, #0]
+ 8003810:	4a74      	ldr	r2, [pc, #464]	; (80039e4 <HAL_DMA_IRQHandler+0xc90>)
+ 8003812:	4293      	cmp	r3, r2
+ 8003814:	d027      	beq.n	8003866 <HAL_DMA_IRQHandler+0xb12>
+ 8003816:	687b      	ldr	r3, [r7, #4]
+ 8003818:	681b      	ldr	r3, [r3, #0]
+ 800381a:	4a73      	ldr	r2, [pc, #460]	; (80039e8 <HAL_DMA_IRQHandler+0xc94>)
+ 800381c:	4293      	cmp	r3, r2
+ 800381e:	d022      	beq.n	8003866 <HAL_DMA_IRQHandler+0xb12>
+ 8003820:	687b      	ldr	r3, [r7, #4]
+ 8003822:	681b      	ldr	r3, [r3, #0]
+ 8003824:	4a71      	ldr	r2, [pc, #452]	; (80039ec <HAL_DMA_IRQHandler+0xc98>)
+ 8003826:	4293      	cmp	r3, r2
+ 8003828:	d01d      	beq.n	8003866 <HAL_DMA_IRQHandler+0xb12>
+ 800382a:	687b      	ldr	r3, [r7, #4]
+ 800382c:	681b      	ldr	r3, [r3, #0]
+ 800382e:	4a70      	ldr	r2, [pc, #448]	; (80039f0 <HAL_DMA_IRQHandler+0xc9c>)
+ 8003830:	4293      	cmp	r3, r2
+ 8003832:	d018      	beq.n	8003866 <HAL_DMA_IRQHandler+0xb12>
+ 8003834:	687b      	ldr	r3, [r7, #4]
+ 8003836:	681b      	ldr	r3, [r3, #0]
+ 8003838:	4a6e      	ldr	r2, [pc, #440]	; (80039f4 <HAL_DMA_IRQHandler+0xca0>)
+ 800383a:	4293      	cmp	r3, r2
+ 800383c:	d013      	beq.n	8003866 <HAL_DMA_IRQHandler+0xb12>
+ 800383e:	687b      	ldr	r3, [r7, #4]
+ 8003840:	681b      	ldr	r3, [r3, #0]
+ 8003842:	4a6d      	ldr	r2, [pc, #436]	; (80039f8 <HAL_DMA_IRQHandler+0xca4>)
+ 8003844:	4293      	cmp	r3, r2
+ 8003846:	d00e      	beq.n	8003866 <HAL_DMA_IRQHandler+0xb12>
+ 8003848:	687b      	ldr	r3, [r7, #4]
+ 800384a:	681b      	ldr	r3, [r3, #0]
+ 800384c:	4a6b      	ldr	r2, [pc, #428]	; (80039fc <HAL_DMA_IRQHandler+0xca8>)
+ 800384e:	4293      	cmp	r3, r2
+ 8003850:	d009      	beq.n	8003866 <HAL_DMA_IRQHandler+0xb12>
+ 8003852:	687b      	ldr	r3, [r7, #4]
+ 8003854:	681b      	ldr	r3, [r3, #0]
+ 8003856:	4a6a      	ldr	r2, [pc, #424]	; (8003a00 <HAL_DMA_IRQHandler+0xcac>)
+ 8003858:	4293      	cmp	r3, r2
+ 800385a:	d004      	beq.n	8003866 <HAL_DMA_IRQHandler+0xb12>
+ 800385c:	687b      	ldr	r3, [r7, #4]
+ 800385e:	681b      	ldr	r3, [r3, #0]
+ 8003860:	4a68      	ldr	r2, [pc, #416]	; (8003a04 <HAL_DMA_IRQHandler+0xcb0>)
+ 8003862:	4293      	cmp	r3, r2
+ 8003864:	d108      	bne.n	8003878 <HAL_DMA_IRQHandler+0xb24>
+ 8003866:	687b      	ldr	r3, [r7, #4]
+ 8003868:	681b      	ldr	r3, [r3, #0]
+ 800386a:	681a      	ldr	r2, [r3, #0]
+ 800386c:	687b      	ldr	r3, [r7, #4]
+ 800386e:	681b      	ldr	r3, [r3, #0]
+ 8003870:	f022 0208 	bic.w	r2, r2, #8
+ 8003874:	601a      	str	r2, [r3, #0]
+ 8003876:	e007      	b.n	8003888 <HAL_DMA_IRQHandler+0xb34>
+ 8003878:	687b      	ldr	r3, [r7, #4]
+ 800387a:	681b      	ldr	r3, [r3, #0]
+ 800387c:	681a      	ldr	r2, [r3, #0]
+ 800387e:	687b      	ldr	r3, [r7, #4]
+ 8003880:	681b      	ldr	r3, [r3, #0]
+ 8003882:	f022 0204 	bic.w	r2, r2, #4
+ 8003886:	601a      	str	r2, [r3, #0]
+        }
+
+        /* DMA peripheral state is not updated in Half Transfer */
+        /* but in Transfer Complete case */
+
+       if(hdma->XferHalfCpltCallback != NULL)
+ 8003888:	687b      	ldr	r3, [r7, #4]
+ 800388a:	6c1b      	ldr	r3, [r3, #64]	; 0x40
+ 800388c:	2b00      	cmp	r3, #0
+ 800388e:	f000 8165 	beq.w	8003b5c <HAL_DMA_IRQHandler+0xe08>
+        {
+          /* Half transfer callback */
+          hdma->XferHalfCpltCallback(hdma);
+ 8003892:	687b      	ldr	r3, [r7, #4]
+ 8003894:	6c1b      	ldr	r3, [r3, #64]	; 0x40
+ 8003896:	6878      	ldr	r0, [r7, #4]
+ 8003898:	4798      	blx	r3
+      if((ccr_reg & BDMA_CCR_DBM) != 0U)
+ 800389a:	e15f      	b.n	8003b5c <HAL_DMA_IRQHandler+0xe08>
+        }
+      }
+    }
+
+    /* Transfer Complete Interrupt management ***********************************/
+    else if (((tmpisr_bdma & (BDMA_FLAG_TC0 << (hdma->StreamIndex & 0x1FU))) != 0U) && ((ccr_reg & BDMA_CCR_TCIE) != 0U))
+ 800389c:	687b      	ldr	r3, [r7, #4]
+ 800389e:	6ddb      	ldr	r3, [r3, #92]	; 0x5c
+ 80038a0:	f003 031f 	and.w	r3, r3, #31
+ 80038a4:	2202      	movs	r2, #2
+ 80038a6:	409a      	lsls	r2, r3
+ 80038a8:	697b      	ldr	r3, [r7, #20]
+ 80038aa:	4013      	ands	r3, r2
+ 80038ac:	2b00      	cmp	r3, #0
+ 80038ae:	f000 80c5 	beq.w	8003a3c <HAL_DMA_IRQHandler+0xce8>
+ 80038b2:	693b      	ldr	r3, [r7, #16]
+ 80038b4:	f003 0302 	and.w	r3, r3, #2
+ 80038b8:	2b00      	cmp	r3, #0
+ 80038ba:	f000 80bf 	beq.w	8003a3c <HAL_DMA_IRQHandler+0xce8>
+    {
+      /* Clear the transfer complete flag */
+      regs_bdma->IFCR = (BDMA_ISR_TCIF0) << (hdma->StreamIndex & 0x1FU);
+ 80038be:	687b      	ldr	r3, [r7, #4]
+ 80038c0:	6ddb      	ldr	r3, [r3, #92]	; 0x5c
+ 80038c2:	f003 031f 	and.w	r3, r3, #31
+ 80038c6:	2202      	movs	r2, #2
+ 80038c8:	409a      	lsls	r2, r3
+ 80038ca:	69fb      	ldr	r3, [r7, #28]
+ 80038cc:	605a      	str	r2, [r3, #4]
+
+      /* Disable the transfer complete interrupt if the DMA mode is Double Buffering */
+      if((ccr_reg & BDMA_CCR_DBM) != 0U)
+ 80038ce:	693b      	ldr	r3, [r7, #16]
+ 80038d0:	f403 4300 	and.w	r3, r3, #32768	; 0x8000
+ 80038d4:	2b00      	cmp	r3, #0
+ 80038d6:	d018      	beq.n	800390a <HAL_DMA_IRQHandler+0xbb6>
+      {
+        /* Current memory buffer used is Memory 0 */
+        if((ccr_reg & BDMA_CCR_CT) == 0U)
+ 80038d8:	693b      	ldr	r3, [r7, #16]
+ 80038da:	f403 3380 	and.w	r3, r3, #65536	; 0x10000
+ 80038de:	2b00      	cmp	r3, #0
+ 80038e0:	d109      	bne.n	80038f6 <HAL_DMA_IRQHandler+0xba2>
+        {
+          if(hdma->XferM1CpltCallback != NULL)
+ 80038e2:	687b      	ldr	r3, [r7, #4]
+ 80038e4:	6c5b      	ldr	r3, [r3, #68]	; 0x44
+ 80038e6:	2b00      	cmp	r3, #0
+ 80038e8:	f000 813a 	beq.w	8003b60 <HAL_DMA_IRQHandler+0xe0c>
+          {
+            /* Transfer complete Callback for Memory 1 */
+            hdma->XferM1CpltCallback(hdma);
+ 80038ec:	687b      	ldr	r3, [r7, #4]
+ 80038ee:	6c5b      	ldr	r3, [r3, #68]	; 0x44
+ 80038f0:	6878      	ldr	r0, [r7, #4]
+ 80038f2:	4798      	blx	r3
+      if((ccr_reg & BDMA_CCR_DBM) != 0U)
+ 80038f4:	e134      	b.n	8003b60 <HAL_DMA_IRQHandler+0xe0c>
+          }
+        }
+        /* Current memory buffer used is Memory 1 */
+        else
+        {
+          if(hdma->XferCpltCallback != NULL)
+ 80038f6:	687b      	ldr	r3, [r7, #4]
+ 80038f8:	6bdb      	ldr	r3, [r3, #60]	; 0x3c
+ 80038fa:	2b00      	cmp	r3, #0
+ 80038fc:	f000 8130 	beq.w	8003b60 <HAL_DMA_IRQHandler+0xe0c>
+          {
+            /* Transfer complete Callback for Memory 0 */
+            hdma->XferCpltCallback(hdma);
+ 8003900:	687b      	ldr	r3, [r7, #4]
+ 8003902:	6bdb      	ldr	r3, [r3, #60]	; 0x3c
+ 8003904:	6878      	ldr	r0, [r7, #4]
+ 8003906:	4798      	blx	r3
+      if((ccr_reg & BDMA_CCR_DBM) != 0U)
+ 8003908:	e12a      	b.n	8003b60 <HAL_DMA_IRQHandler+0xe0c>
+          }
+        }
+      }
+      else
+      {
+        if((ccr_reg & BDMA_CCR_CIRC) == 0U)
+ 800390a:	693b      	ldr	r3, [r7, #16]
+ 800390c:	f003 0320 	and.w	r3, r3, #32
+ 8003910:	2b00      	cmp	r3, #0
+ 8003912:	f040 8089 	bne.w	8003a28 <HAL_DMA_IRQHandler+0xcd4>
+        {
+          /* Disable the transfer complete and error interrupt, if the DMA mode is not CIRCULAR */
+          __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC);
+ 8003916:	687b      	ldr	r3, [r7, #4]
+ 8003918:	681b      	ldr	r3, [r3, #0]
+ 800391a:	4a2b      	ldr	r2, [pc, #172]	; (80039c8 <HAL_DMA_IRQHandler+0xc74>)
+ 800391c:	4293      	cmp	r3, r2
+ 800391e:	d04a      	beq.n	80039b6 <HAL_DMA_IRQHandler+0xc62>
+ 8003920:	687b      	ldr	r3, [r7, #4]
+ 8003922:	681b      	ldr	r3, [r3, #0]
+ 8003924:	4a29      	ldr	r2, [pc, #164]	; (80039cc <HAL_DMA_IRQHandler+0xc78>)
+ 8003926:	4293      	cmp	r3, r2
+ 8003928:	d045      	beq.n	80039b6 <HAL_DMA_IRQHandler+0xc62>
+ 800392a:	687b      	ldr	r3, [r7, #4]
+ 800392c:	681b      	ldr	r3, [r3, #0]
+ 800392e:	4a28      	ldr	r2, [pc, #160]	; (80039d0 <HAL_DMA_IRQHandler+0xc7c>)
+ 8003930:	4293      	cmp	r3, r2
+ 8003932:	d040      	beq.n	80039b6 <HAL_DMA_IRQHandler+0xc62>
+ 8003934:	687b      	ldr	r3, [r7, #4]
+ 8003936:	681b      	ldr	r3, [r3, #0]
+ 8003938:	4a26      	ldr	r2, [pc, #152]	; (80039d4 <HAL_DMA_IRQHandler+0xc80>)
+ 800393a:	4293      	cmp	r3, r2
+ 800393c:	d03b      	beq.n	80039b6 <HAL_DMA_IRQHandler+0xc62>
+ 800393e:	687b      	ldr	r3, [r7, #4]
+ 8003940:	681b      	ldr	r3, [r3, #0]
+ 8003942:	4a25      	ldr	r2, [pc, #148]	; (80039d8 <HAL_DMA_IRQHandler+0xc84>)
+ 8003944:	4293      	cmp	r3, r2
+ 8003946:	d036      	beq.n	80039b6 <HAL_DMA_IRQHandler+0xc62>
+ 8003948:	687b      	ldr	r3, [r7, #4]
+ 800394a:	681b      	ldr	r3, [r3, #0]
+ 800394c:	4a23      	ldr	r2, [pc, #140]	; (80039dc <HAL_DMA_IRQHandler+0xc88>)
+ 800394e:	4293      	cmp	r3, r2
+ 8003950:	d031      	beq.n	80039b6 <HAL_DMA_IRQHandler+0xc62>
+ 8003952:	687b      	ldr	r3, [r7, #4]
+ 8003954:	681b      	ldr	r3, [r3, #0]
+ 8003956:	4a22      	ldr	r2, [pc, #136]	; (80039e0 <HAL_DMA_IRQHandler+0xc8c>)
+ 8003958:	4293      	cmp	r3, r2
+ 800395a:	d02c      	beq.n	80039b6 <HAL_DMA_IRQHandler+0xc62>
+ 800395c:	687b      	ldr	r3, [r7, #4]
+ 800395e:	681b      	ldr	r3, [r3, #0]
+ 8003960:	4a20      	ldr	r2, [pc, #128]	; (80039e4 <HAL_DMA_IRQHandler+0xc90>)
+ 8003962:	4293      	cmp	r3, r2
+ 8003964:	d027      	beq.n	80039b6 <HAL_DMA_IRQHandler+0xc62>
+ 8003966:	687b      	ldr	r3, [r7, #4]
+ 8003968:	681b      	ldr	r3, [r3, #0]
+ 800396a:	4a1f      	ldr	r2, [pc, #124]	; (80039e8 <HAL_DMA_IRQHandler+0xc94>)
+ 800396c:	4293      	cmp	r3, r2
+ 800396e:	d022      	beq.n	80039b6 <HAL_DMA_IRQHandler+0xc62>
+ 8003970:	687b      	ldr	r3, [r7, #4]
+ 8003972:	681b      	ldr	r3, [r3, #0]
+ 8003974:	4a1d      	ldr	r2, [pc, #116]	; (80039ec <HAL_DMA_IRQHandler+0xc98>)
+ 8003976:	4293      	cmp	r3, r2
+ 8003978:	d01d      	beq.n	80039b6 <HAL_DMA_IRQHandler+0xc62>
+ 800397a:	687b      	ldr	r3, [r7, #4]
+ 800397c:	681b      	ldr	r3, [r3, #0]
+ 800397e:	4a1c      	ldr	r2, [pc, #112]	; (80039f0 <HAL_DMA_IRQHandler+0xc9c>)
+ 8003980:	4293      	cmp	r3, r2
+ 8003982:	d018      	beq.n	80039b6 <HAL_DMA_IRQHandler+0xc62>
+ 8003984:	687b      	ldr	r3, [r7, #4]
+ 8003986:	681b      	ldr	r3, [r3, #0]
+ 8003988:	4a1a      	ldr	r2, [pc, #104]	; (80039f4 <HAL_DMA_IRQHandler+0xca0>)
+ 800398a:	4293      	cmp	r3, r2
+ 800398c:	d013      	beq.n	80039b6 <HAL_DMA_IRQHandler+0xc62>
+ 800398e:	687b      	ldr	r3, [r7, #4]
+ 8003990:	681b      	ldr	r3, [r3, #0]
+ 8003992:	4a19      	ldr	r2, [pc, #100]	; (80039f8 <HAL_DMA_IRQHandler+0xca4>)
+ 8003994:	4293      	cmp	r3, r2
+ 8003996:	d00e      	beq.n	80039b6 <HAL_DMA_IRQHandler+0xc62>
+ 8003998:	687b      	ldr	r3, [r7, #4]
+ 800399a:	681b      	ldr	r3, [r3, #0]
+ 800399c:	4a17      	ldr	r2, [pc, #92]	; (80039fc <HAL_DMA_IRQHandler+0xca8>)
+ 800399e:	4293      	cmp	r3, r2
+ 80039a0:	d009      	beq.n	80039b6 <HAL_DMA_IRQHandler+0xc62>
+ 80039a2:	687b      	ldr	r3, [r7, #4]
+ 80039a4:	681b      	ldr	r3, [r3, #0]
+ 80039a6:	4a16      	ldr	r2, [pc, #88]	; (8003a00 <HAL_DMA_IRQHandler+0xcac>)
+ 80039a8:	4293      	cmp	r3, r2
+ 80039aa:	d004      	beq.n	80039b6 <HAL_DMA_IRQHandler+0xc62>
+ 80039ac:	687b      	ldr	r3, [r7, #4]
+ 80039ae:	681b      	ldr	r3, [r3, #0]
+ 80039b0:	4a14      	ldr	r2, [pc, #80]	; (8003a04 <HAL_DMA_IRQHandler+0xcb0>)
+ 80039b2:	4293      	cmp	r3, r2
+ 80039b4:	d128      	bne.n	8003a08 <HAL_DMA_IRQHandler+0xcb4>
+ 80039b6:	687b      	ldr	r3, [r7, #4]
+ 80039b8:	681b      	ldr	r3, [r3, #0]
+ 80039ba:	681a      	ldr	r2, [r3, #0]
+ 80039bc:	687b      	ldr	r3, [r7, #4]
+ 80039be:	681b      	ldr	r3, [r3, #0]
+ 80039c0:	f022 0214 	bic.w	r2, r2, #20
+ 80039c4:	601a      	str	r2, [r3, #0]
+ 80039c6:	e027      	b.n	8003a18 <HAL_DMA_IRQHandler+0xcc4>
+ 80039c8:	40020010 	.word	0x40020010
+ 80039cc:	40020028 	.word	0x40020028
+ 80039d0:	40020040 	.word	0x40020040
+ 80039d4:	40020058 	.word	0x40020058
+ 80039d8:	40020070 	.word	0x40020070
+ 80039dc:	40020088 	.word	0x40020088
+ 80039e0:	400200a0 	.word	0x400200a0
+ 80039e4:	400200b8 	.word	0x400200b8
+ 80039e8:	40020410 	.word	0x40020410
+ 80039ec:	40020428 	.word	0x40020428
+ 80039f0:	40020440 	.word	0x40020440
+ 80039f4:	40020458 	.word	0x40020458
+ 80039f8:	40020470 	.word	0x40020470
+ 80039fc:	40020488 	.word	0x40020488
+ 8003a00:	400204a0 	.word	0x400204a0
+ 8003a04:	400204b8 	.word	0x400204b8
+ 8003a08:	687b      	ldr	r3, [r7, #4]
+ 8003a0a:	681b      	ldr	r3, [r3, #0]
+ 8003a0c:	681a      	ldr	r2, [r3, #0]
+ 8003a0e:	687b      	ldr	r3, [r7, #4]
+ 8003a10:	681b      	ldr	r3, [r3, #0]
+ 8003a12:	f022 020a 	bic.w	r2, r2, #10
+ 8003a16:	601a      	str	r2, [r3, #0]
+
+          /* Change the DMA state */
+          hdma->State = HAL_DMA_STATE_READY;
+ 8003a18:	687b      	ldr	r3, [r7, #4]
+ 8003a1a:	2201      	movs	r2, #1
+ 8003a1c:	f883 2035 	strb.w	r2, [r3, #53]	; 0x35
+
+          /* Process Unlocked */
+          __HAL_UNLOCK(hdma);
+ 8003a20:	687b      	ldr	r3, [r7, #4]
+ 8003a22:	2200      	movs	r2, #0
+ 8003a24:	f883 2034 	strb.w	r2, [r3, #52]	; 0x34
+        }
+
+        if(hdma->XferCpltCallback != NULL)
+ 8003a28:	687b      	ldr	r3, [r7, #4]
+ 8003a2a:	6bdb      	ldr	r3, [r3, #60]	; 0x3c
+ 8003a2c:	2b00      	cmp	r3, #0
+ 8003a2e:	f000 8097 	beq.w	8003b60 <HAL_DMA_IRQHandler+0xe0c>
+        {
+          /* Transfer complete callback */
+          hdma->XferCpltCallback(hdma);
+ 8003a32:	687b      	ldr	r3, [r7, #4]
+ 8003a34:	6bdb      	ldr	r3, [r3, #60]	; 0x3c
+ 8003a36:	6878      	ldr	r0, [r7, #4]
+ 8003a38:	4798      	blx	r3
+      if((ccr_reg & BDMA_CCR_DBM) != 0U)
+ 8003a3a:	e091      	b.n	8003b60 <HAL_DMA_IRQHandler+0xe0c>
+        }
+      }
+    }
+    /* Transfer Error Interrupt management **************************************/
+    else if (((tmpisr_bdma & (BDMA_FLAG_TE0 << (hdma->StreamIndex & 0x1FU))) != 0U) && ((ccr_reg & BDMA_CCR_TEIE) != 0U))
+ 8003a3c:	687b      	ldr	r3, [r7, #4]
+ 8003a3e:	6ddb      	ldr	r3, [r3, #92]	; 0x5c
+ 8003a40:	f003 031f 	and.w	r3, r3, #31
+ 8003a44:	2208      	movs	r2, #8
+ 8003a46:	409a      	lsls	r2, r3
+ 8003a48:	697b      	ldr	r3, [r7, #20]
+ 8003a4a:	4013      	ands	r3, r2
+ 8003a4c:	2b00      	cmp	r3, #0
+ 8003a4e:	f000 8088 	beq.w	8003b62 <HAL_DMA_IRQHandler+0xe0e>
+ 8003a52:	693b      	ldr	r3, [r7, #16]
+ 8003a54:	f003 0308 	and.w	r3, r3, #8
+ 8003a58:	2b00      	cmp	r3, #0
+ 8003a5a:	f000 8082 	beq.w	8003b62 <HAL_DMA_IRQHandler+0xe0e>
+    {
+      /* When a DMA transfer error occurs */
+      /* A hardware clear of its EN bits is performed */
+      /* Disable ALL DMA IT */
+      __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
+ 8003a5e:	687b      	ldr	r3, [r7, #4]
+ 8003a60:	681b      	ldr	r3, [r3, #0]
+ 8003a62:	4a41      	ldr	r2, [pc, #260]	; (8003b68 <HAL_DMA_IRQHandler+0xe14>)
+ 8003a64:	4293      	cmp	r3, r2
+ 8003a66:	d04a      	beq.n	8003afe <HAL_DMA_IRQHandler+0xdaa>
+ 8003a68:	687b      	ldr	r3, [r7, #4]
+ 8003a6a:	681b      	ldr	r3, [r3, #0]
+ 8003a6c:	4a3f      	ldr	r2, [pc, #252]	; (8003b6c <HAL_DMA_IRQHandler+0xe18>)
+ 8003a6e:	4293      	cmp	r3, r2
+ 8003a70:	d045      	beq.n	8003afe <HAL_DMA_IRQHandler+0xdaa>
+ 8003a72:	687b      	ldr	r3, [r7, #4]
+ 8003a74:	681b      	ldr	r3, [r3, #0]
+ 8003a76:	4a3e      	ldr	r2, [pc, #248]	; (8003b70 <HAL_DMA_IRQHandler+0xe1c>)
+ 8003a78:	4293      	cmp	r3, r2
+ 8003a7a:	d040      	beq.n	8003afe <HAL_DMA_IRQHandler+0xdaa>
+ 8003a7c:	687b      	ldr	r3, [r7, #4]
+ 8003a7e:	681b      	ldr	r3, [r3, #0]
+ 8003a80:	4a3c      	ldr	r2, [pc, #240]	; (8003b74 <HAL_DMA_IRQHandler+0xe20>)
+ 8003a82:	4293      	cmp	r3, r2
+ 8003a84:	d03b      	beq.n	8003afe <HAL_DMA_IRQHandler+0xdaa>
+ 8003a86:	687b      	ldr	r3, [r7, #4]
+ 8003a88:	681b      	ldr	r3, [r3, #0]
+ 8003a8a:	4a3b      	ldr	r2, [pc, #236]	; (8003b78 <HAL_DMA_IRQHandler+0xe24>)
+ 8003a8c:	4293      	cmp	r3, r2
+ 8003a8e:	d036      	beq.n	8003afe <HAL_DMA_IRQHandler+0xdaa>
+ 8003a90:	687b      	ldr	r3, [r7, #4]
+ 8003a92:	681b      	ldr	r3, [r3, #0]
+ 8003a94:	4a39      	ldr	r2, [pc, #228]	; (8003b7c <HAL_DMA_IRQHandler+0xe28>)
+ 8003a96:	4293      	cmp	r3, r2
+ 8003a98:	d031      	beq.n	8003afe <HAL_DMA_IRQHandler+0xdaa>
+ 8003a9a:	687b      	ldr	r3, [r7, #4]
+ 8003a9c:	681b      	ldr	r3, [r3, #0]
+ 8003a9e:	4a38      	ldr	r2, [pc, #224]	; (8003b80 <HAL_DMA_IRQHandler+0xe2c>)
+ 8003aa0:	4293      	cmp	r3, r2
+ 8003aa2:	d02c      	beq.n	8003afe <HAL_DMA_IRQHandler+0xdaa>
+ 8003aa4:	687b      	ldr	r3, [r7, #4]
+ 8003aa6:	681b      	ldr	r3, [r3, #0]
+ 8003aa8:	4a36      	ldr	r2, [pc, #216]	; (8003b84 <HAL_DMA_IRQHandler+0xe30>)
+ 8003aaa:	4293      	cmp	r3, r2
+ 8003aac:	d027      	beq.n	8003afe <HAL_DMA_IRQHandler+0xdaa>
+ 8003aae:	687b      	ldr	r3, [r7, #4]
+ 8003ab0:	681b      	ldr	r3, [r3, #0]
+ 8003ab2:	4a35      	ldr	r2, [pc, #212]	; (8003b88 <HAL_DMA_IRQHandler+0xe34>)
+ 8003ab4:	4293      	cmp	r3, r2
+ 8003ab6:	d022      	beq.n	8003afe <HAL_DMA_IRQHandler+0xdaa>
+ 8003ab8:	687b      	ldr	r3, [r7, #4]
+ 8003aba:	681b      	ldr	r3, [r3, #0]
+ 8003abc:	4a33      	ldr	r2, [pc, #204]	; (8003b8c <HAL_DMA_IRQHandler+0xe38>)
+ 8003abe:	4293      	cmp	r3, r2
+ 8003ac0:	d01d      	beq.n	8003afe <HAL_DMA_IRQHandler+0xdaa>
+ 8003ac2:	687b      	ldr	r3, [r7, #4]
+ 8003ac4:	681b      	ldr	r3, [r3, #0]
+ 8003ac6:	4a32      	ldr	r2, [pc, #200]	; (8003b90 <HAL_DMA_IRQHandler+0xe3c>)
+ 8003ac8:	4293      	cmp	r3, r2
+ 8003aca:	d018      	beq.n	8003afe <HAL_DMA_IRQHandler+0xdaa>
+ 8003acc:	687b      	ldr	r3, [r7, #4]
+ 8003ace:	681b      	ldr	r3, [r3, #0]
+ 8003ad0:	4a30      	ldr	r2, [pc, #192]	; (8003b94 <HAL_DMA_IRQHandler+0xe40>)
+ 8003ad2:	4293      	cmp	r3, r2
+ 8003ad4:	d013      	beq.n	8003afe <HAL_DMA_IRQHandler+0xdaa>
+ 8003ad6:	687b      	ldr	r3, [r7, #4]
+ 8003ad8:	681b      	ldr	r3, [r3, #0]
+ 8003ada:	4a2f      	ldr	r2, [pc, #188]	; (8003b98 <HAL_DMA_IRQHandler+0xe44>)
+ 8003adc:	4293      	cmp	r3, r2
+ 8003ade:	d00e      	beq.n	8003afe <HAL_DMA_IRQHandler+0xdaa>
+ 8003ae0:	687b      	ldr	r3, [r7, #4]
+ 8003ae2:	681b      	ldr	r3, [r3, #0]
+ 8003ae4:	4a2d      	ldr	r2, [pc, #180]	; (8003b9c <HAL_DMA_IRQHandler+0xe48>)
+ 8003ae6:	4293      	cmp	r3, r2
+ 8003ae8:	d009      	beq.n	8003afe <HAL_DMA_IRQHandler+0xdaa>
+ 8003aea:	687b      	ldr	r3, [r7, #4]
+ 8003aec:	681b      	ldr	r3, [r3, #0]
+ 8003aee:	4a2c      	ldr	r2, [pc, #176]	; (8003ba0 <HAL_DMA_IRQHandler+0xe4c>)
+ 8003af0:	4293      	cmp	r3, r2
+ 8003af2:	d004      	beq.n	8003afe <HAL_DMA_IRQHandler+0xdaa>
+ 8003af4:	687b      	ldr	r3, [r7, #4]
+ 8003af6:	681b      	ldr	r3, [r3, #0]
+ 8003af8:	4a2a      	ldr	r2, [pc, #168]	; (8003ba4 <HAL_DMA_IRQHandler+0xe50>)
+ 8003afa:	4293      	cmp	r3, r2
+ 8003afc:	d108      	bne.n	8003b10 <HAL_DMA_IRQHandler+0xdbc>
+ 8003afe:	687b      	ldr	r3, [r7, #4]
+ 8003b00:	681b      	ldr	r3, [r3, #0]
+ 8003b02:	681a      	ldr	r2, [r3, #0]
+ 8003b04:	687b      	ldr	r3, [r7, #4]
+ 8003b06:	681b      	ldr	r3, [r3, #0]
+ 8003b08:	f022 021c 	bic.w	r2, r2, #28
+ 8003b0c:	601a      	str	r2, [r3, #0]
+ 8003b0e:	e007      	b.n	8003b20 <HAL_DMA_IRQHandler+0xdcc>
+ 8003b10:	687b      	ldr	r3, [r7, #4]
+ 8003b12:	681b      	ldr	r3, [r3, #0]
+ 8003b14:	681a      	ldr	r2, [r3, #0]
+ 8003b16:	687b      	ldr	r3, [r7, #4]
+ 8003b18:	681b      	ldr	r3, [r3, #0]
+ 8003b1a:	f022 020e 	bic.w	r2, r2, #14
+ 8003b1e:	601a      	str	r2, [r3, #0]
+
+      /* Clear all flags */
+      regs_bdma->IFCR = (BDMA_ISR_GIF0) << (hdma->StreamIndex & 0x1FU);
+ 8003b20:	687b      	ldr	r3, [r7, #4]
+ 8003b22:	6ddb      	ldr	r3, [r3, #92]	; 0x5c
+ 8003b24:	f003 031f 	and.w	r3, r3, #31
+ 8003b28:	2201      	movs	r2, #1
+ 8003b2a:	409a      	lsls	r2, r3
+ 8003b2c:	69fb      	ldr	r3, [r7, #28]
+ 8003b2e:	605a      	str	r2, [r3, #4]
+
+      /* Update error code */
+      hdma->ErrorCode = HAL_DMA_ERROR_TE;
+ 8003b30:	687b      	ldr	r3, [r7, #4]
+ 8003b32:	2201      	movs	r2, #1
+ 8003b34:	655a      	str	r2, [r3, #84]	; 0x54
+
+      /* Change the DMA state */
+      hdma->State = HAL_DMA_STATE_READY;
+ 8003b36:	687b      	ldr	r3, [r7, #4]
+ 8003b38:	2201      	movs	r2, #1
+ 8003b3a:	f883 2035 	strb.w	r2, [r3, #53]	; 0x35
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hdma);
+ 8003b3e:	687b      	ldr	r3, [r7, #4]
+ 8003b40:	2200      	movs	r2, #0
+ 8003b42:	f883 2034 	strb.w	r2, [r3, #52]	; 0x34
+
+      if (hdma->XferErrorCallback != NULL)
+ 8003b46:	687b      	ldr	r3, [r7, #4]
+ 8003b48:	6cdb      	ldr	r3, [r3, #76]	; 0x4c
+ 8003b4a:	2b00      	cmp	r3, #0
+ 8003b4c:	d009      	beq.n	8003b62 <HAL_DMA_IRQHandler+0xe0e>
+      {
+        /* Transfer error callback */
+        hdma->XferErrorCallback(hdma);
+ 8003b4e:	687b      	ldr	r3, [r7, #4]
+ 8003b50:	6cdb      	ldr	r3, [r3, #76]	; 0x4c
+ 8003b52:	6878      	ldr	r0, [r7, #4]
+ 8003b54:	4798      	blx	r3
+ 8003b56:	e004      	b.n	8003b62 <HAL_DMA_IRQHandler+0xe0e>
+          return;
+ 8003b58:	bf00      	nop
+ 8003b5a:	e002      	b.n	8003b62 <HAL_DMA_IRQHandler+0xe0e>
+      if((ccr_reg & BDMA_CCR_DBM) != 0U)
+ 8003b5c:	bf00      	nop
+ 8003b5e:	e000      	b.n	8003b62 <HAL_DMA_IRQHandler+0xe0e>
+      if((ccr_reg & BDMA_CCR_DBM) != 0U)
+ 8003b60:	bf00      	nop
+  }
+  else
+  {
+    /* Nothing To Do */
+  }
+}
+ 8003b62:	3728      	adds	r7, #40	; 0x28
+ 8003b64:	46bd      	mov	sp, r7
+ 8003b66:	bd80      	pop	{r7, pc}
+ 8003b68:	40020010 	.word	0x40020010
+ 8003b6c:	40020028 	.word	0x40020028
+ 8003b70:	40020040 	.word	0x40020040
+ 8003b74:	40020058 	.word	0x40020058
+ 8003b78:	40020070 	.word	0x40020070
+ 8003b7c:	40020088 	.word	0x40020088
+ 8003b80:	400200a0 	.word	0x400200a0
+ 8003b84:	400200b8 	.word	0x400200b8
+ 8003b88:	40020410 	.word	0x40020410
+ 8003b8c:	40020428 	.word	0x40020428
+ 8003b90:	40020440 	.word	0x40020440
+ 8003b94:	40020458 	.word	0x40020458
+ 8003b98:	40020470 	.word	0x40020470
+ 8003b9c:	40020488 	.word	0x40020488
+ 8003ba0:	400204a0 	.word	0x400204a0
+ 8003ba4:	400204b8 	.word	0x400204b8
+
+08003ba8 <DMA_CalcBaseAndBitshift>:
+  * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
+  *                     the configuration information for the specified DMA Stream.
+  * @retval Stream base address
+  */
+static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma)
+{
+ 8003ba8:	b480      	push	{r7}
+ 8003baa:	b085      	sub	sp, #20
+ 8003bac:	af00      	add	r7, sp, #0
+ 8003bae:	6078      	str	r0, [r7, #4]
+  if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
+ 8003bb0:	687b      	ldr	r3, [r7, #4]
+ 8003bb2:	681b      	ldr	r3, [r3, #0]
+ 8003bb4:	4a42      	ldr	r2, [pc, #264]	; (8003cc0 <DMA_CalcBaseAndBitshift+0x118>)
+ 8003bb6:	4293      	cmp	r3, r2
+ 8003bb8:	d04a      	beq.n	8003c50 <DMA_CalcBaseAndBitshift+0xa8>
+ 8003bba:	687b      	ldr	r3, [r7, #4]
+ 8003bbc:	681b      	ldr	r3, [r3, #0]
+ 8003bbe:	4a41      	ldr	r2, [pc, #260]	; (8003cc4 <DMA_CalcBaseAndBitshift+0x11c>)
+ 8003bc0:	4293      	cmp	r3, r2
+ 8003bc2:	d045      	beq.n	8003c50 <DMA_CalcBaseAndBitshift+0xa8>
+ 8003bc4:	687b      	ldr	r3, [r7, #4]
+ 8003bc6:	681b      	ldr	r3, [r3, #0]
+ 8003bc8:	4a3f      	ldr	r2, [pc, #252]	; (8003cc8 <DMA_CalcBaseAndBitshift+0x120>)
+ 8003bca:	4293      	cmp	r3, r2
+ 8003bcc:	d040      	beq.n	8003c50 <DMA_CalcBaseAndBitshift+0xa8>
+ 8003bce:	687b      	ldr	r3, [r7, #4]
+ 8003bd0:	681b      	ldr	r3, [r3, #0]
+ 8003bd2:	4a3e      	ldr	r2, [pc, #248]	; (8003ccc <DMA_CalcBaseAndBitshift+0x124>)
+ 8003bd4:	4293      	cmp	r3, r2
+ 8003bd6:	d03b      	beq.n	8003c50 <DMA_CalcBaseAndBitshift+0xa8>
+ 8003bd8:	687b      	ldr	r3, [r7, #4]
+ 8003bda:	681b      	ldr	r3, [r3, #0]
+ 8003bdc:	4a3c      	ldr	r2, [pc, #240]	; (8003cd0 <DMA_CalcBaseAndBitshift+0x128>)
+ 8003bde:	4293      	cmp	r3, r2
+ 8003be0:	d036      	beq.n	8003c50 <DMA_CalcBaseAndBitshift+0xa8>
+ 8003be2:	687b      	ldr	r3, [r7, #4]
+ 8003be4:	681b      	ldr	r3, [r3, #0]
+ 8003be6:	4a3b      	ldr	r2, [pc, #236]	; (8003cd4 <DMA_CalcBaseAndBitshift+0x12c>)
+ 8003be8:	4293      	cmp	r3, r2
+ 8003bea:	d031      	beq.n	8003c50 <DMA_CalcBaseAndBitshift+0xa8>
+ 8003bec:	687b      	ldr	r3, [r7, #4]
+ 8003bee:	681b      	ldr	r3, [r3, #0]
+ 8003bf0:	4a39      	ldr	r2, [pc, #228]	; (8003cd8 <DMA_CalcBaseAndBitshift+0x130>)
+ 8003bf2:	4293      	cmp	r3, r2
+ 8003bf4:	d02c      	beq.n	8003c50 <DMA_CalcBaseAndBitshift+0xa8>
+ 8003bf6:	687b      	ldr	r3, [r7, #4]
+ 8003bf8:	681b      	ldr	r3, [r3, #0]
+ 8003bfa:	4a38      	ldr	r2, [pc, #224]	; (8003cdc <DMA_CalcBaseAndBitshift+0x134>)
+ 8003bfc:	4293      	cmp	r3, r2
+ 8003bfe:	d027      	beq.n	8003c50 <DMA_CalcBaseAndBitshift+0xa8>
+ 8003c00:	687b      	ldr	r3, [r7, #4]
+ 8003c02:	681b      	ldr	r3, [r3, #0]
+ 8003c04:	4a36      	ldr	r2, [pc, #216]	; (8003ce0 <DMA_CalcBaseAndBitshift+0x138>)
+ 8003c06:	4293      	cmp	r3, r2
+ 8003c08:	d022      	beq.n	8003c50 <DMA_CalcBaseAndBitshift+0xa8>
+ 8003c0a:	687b      	ldr	r3, [r7, #4]
+ 8003c0c:	681b      	ldr	r3, [r3, #0]
+ 8003c0e:	4a35      	ldr	r2, [pc, #212]	; (8003ce4 <DMA_CalcBaseAndBitshift+0x13c>)
+ 8003c10:	4293      	cmp	r3, r2
+ 8003c12:	d01d      	beq.n	8003c50 <DMA_CalcBaseAndBitshift+0xa8>
+ 8003c14:	687b      	ldr	r3, [r7, #4]
+ 8003c16:	681b      	ldr	r3, [r3, #0]
+ 8003c18:	4a33      	ldr	r2, [pc, #204]	; (8003ce8 <DMA_CalcBaseAndBitshift+0x140>)
+ 8003c1a:	4293      	cmp	r3, r2
+ 8003c1c:	d018      	beq.n	8003c50 <DMA_CalcBaseAndBitshift+0xa8>
+ 8003c1e:	687b      	ldr	r3, [r7, #4]
+ 8003c20:	681b      	ldr	r3, [r3, #0]
+ 8003c22:	4a32      	ldr	r2, [pc, #200]	; (8003cec <DMA_CalcBaseAndBitshift+0x144>)
+ 8003c24:	4293      	cmp	r3, r2
+ 8003c26:	d013      	beq.n	8003c50 <DMA_CalcBaseAndBitshift+0xa8>
+ 8003c28:	687b      	ldr	r3, [r7, #4]
+ 8003c2a:	681b      	ldr	r3, [r3, #0]
+ 8003c2c:	4a30      	ldr	r2, [pc, #192]	; (8003cf0 <DMA_CalcBaseAndBitshift+0x148>)
+ 8003c2e:	4293      	cmp	r3, r2
+ 8003c30:	d00e      	beq.n	8003c50 <DMA_CalcBaseAndBitshift+0xa8>
+ 8003c32:	687b      	ldr	r3, [r7, #4]
+ 8003c34:	681b      	ldr	r3, [r3, #0]
+ 8003c36:	4a2f      	ldr	r2, [pc, #188]	; (8003cf4 <DMA_CalcBaseAndBitshift+0x14c>)
+ 8003c38:	4293      	cmp	r3, r2
+ 8003c3a:	d009      	beq.n	8003c50 <DMA_CalcBaseAndBitshift+0xa8>
+ 8003c3c:	687b      	ldr	r3, [r7, #4]
+ 8003c3e:	681b      	ldr	r3, [r3, #0]
+ 8003c40:	4a2d      	ldr	r2, [pc, #180]	; (8003cf8 <DMA_CalcBaseAndBitshift+0x150>)
+ 8003c42:	4293      	cmp	r3, r2
+ 8003c44:	d004      	beq.n	8003c50 <DMA_CalcBaseAndBitshift+0xa8>
+ 8003c46:	687b      	ldr	r3, [r7, #4]
+ 8003c48:	681b      	ldr	r3, [r3, #0]
+ 8003c4a:	4a2c      	ldr	r2, [pc, #176]	; (8003cfc <DMA_CalcBaseAndBitshift+0x154>)
+ 8003c4c:	4293      	cmp	r3, r2
+ 8003c4e:	d101      	bne.n	8003c54 <DMA_CalcBaseAndBitshift+0xac>
+ 8003c50:	2301      	movs	r3, #1
+ 8003c52:	e000      	b.n	8003c56 <DMA_CalcBaseAndBitshift+0xae>
+ 8003c54:	2300      	movs	r3, #0
+ 8003c56:	2b00      	cmp	r3, #0
+ 8003c58:	d024      	beq.n	8003ca4 <DMA_CalcBaseAndBitshift+0xfc>
+  {
+    uint32_t stream_number = (((uint32_t)((uint32_t*)hdma->Instance) & 0xFFU) - 16U) / 24U;
+ 8003c5a:	687b      	ldr	r3, [r7, #4]
+ 8003c5c:	681b      	ldr	r3, [r3, #0]
+ 8003c5e:	b2db      	uxtb	r3, r3
+ 8003c60:	3b10      	subs	r3, #16
+ 8003c62:	4a27      	ldr	r2, [pc, #156]	; (8003d00 <DMA_CalcBaseAndBitshift+0x158>)
+ 8003c64:	fba2 2303 	umull	r2, r3, r2, r3
+ 8003c68:	091b      	lsrs	r3, r3, #4
+ 8003c6a:	60fb      	str	r3, [r7, #12]
+
+    /* lookup table for necessary bitshift of flags within status registers */
+    static const uint8_t flagBitshiftOffset[8U] = {0U, 6U, 16U, 22U, 0U, 6U, 16U, 22U};
+    hdma->StreamIndex = flagBitshiftOffset[stream_number & 0x7U];
+ 8003c6c:	68fb      	ldr	r3, [r7, #12]
+ 8003c6e:	f003 0307 	and.w	r3, r3, #7
+ 8003c72:	4a24      	ldr	r2, [pc, #144]	; (8003d04 <DMA_CalcBaseAndBitshift+0x15c>)
+ 8003c74:	5cd3      	ldrb	r3, [r2, r3]
+ 8003c76:	461a      	mov	r2, r3
+ 8003c78:	687b      	ldr	r3, [r7, #4]
+ 8003c7a:	65da      	str	r2, [r3, #92]	; 0x5c
+
+    if (stream_number > 3U)
+ 8003c7c:	68fb      	ldr	r3, [r7, #12]
+ 8003c7e:	2b03      	cmp	r3, #3
+ 8003c80:	d908      	bls.n	8003c94 <DMA_CalcBaseAndBitshift+0xec>
+    {
+      /* return pointer to HISR and HIFCR */
+      hdma->StreamBaseAddress = (((uint32_t)((uint32_t*)hdma->Instance) & (uint32_t)(~0x3FFU)) + 4U);
+ 8003c82:	687b      	ldr	r3, [r7, #4]
+ 8003c84:	681b      	ldr	r3, [r3, #0]
+ 8003c86:	461a      	mov	r2, r3
+ 8003c88:	4b1f      	ldr	r3, [pc, #124]	; (8003d08 <DMA_CalcBaseAndBitshift+0x160>)
+ 8003c8a:	4013      	ands	r3, r2
+ 8003c8c:	1d1a      	adds	r2, r3, #4
+ 8003c8e:	687b      	ldr	r3, [r7, #4]
+ 8003c90:	659a      	str	r2, [r3, #88]	; 0x58
+ 8003c92:	e00d      	b.n	8003cb0 <DMA_CalcBaseAndBitshift+0x108>
+    }
+    else
+    {
+      /* return pointer to LISR and LIFCR */
+      hdma->StreamBaseAddress = ((uint32_t)((uint32_t*)hdma->Instance) & (uint32_t)(~0x3FFU));
+ 8003c94:	687b      	ldr	r3, [r7, #4]
+ 8003c96:	681b      	ldr	r3, [r3, #0]
+ 8003c98:	461a      	mov	r2, r3
+ 8003c9a:	4b1b      	ldr	r3, [pc, #108]	; (8003d08 <DMA_CalcBaseAndBitshift+0x160>)
+ 8003c9c:	4013      	ands	r3, r2
+ 8003c9e:	687a      	ldr	r2, [r7, #4]
+ 8003ca0:	6593      	str	r3, [r2, #88]	; 0x58
+ 8003ca2:	e005      	b.n	8003cb0 <DMA_CalcBaseAndBitshift+0x108>
+    }
+  }
+  else /* BDMA instance(s) */
+  {
+    /* return pointer to ISR and IFCR */
+    hdma->StreamBaseAddress = ((uint32_t)((uint32_t*)hdma->Instance) & (uint32_t)(~0xFFU));
+ 8003ca4:	687b      	ldr	r3, [r7, #4]
+ 8003ca6:	681b      	ldr	r3, [r3, #0]
+ 8003ca8:	f023 02ff 	bic.w	r2, r3, #255	; 0xff
+ 8003cac:	687b      	ldr	r3, [r7, #4]
+ 8003cae:	659a      	str	r2, [r3, #88]	; 0x58
+  }
+
+  return hdma->StreamBaseAddress;
+ 8003cb0:	687b      	ldr	r3, [r7, #4]
+ 8003cb2:	6d9b      	ldr	r3, [r3, #88]	; 0x58
+}
+ 8003cb4:	4618      	mov	r0, r3
+ 8003cb6:	3714      	adds	r7, #20
+ 8003cb8:	46bd      	mov	sp, r7
+ 8003cba:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8003cbe:	4770      	bx	lr
+ 8003cc0:	40020010 	.word	0x40020010
+ 8003cc4:	40020028 	.word	0x40020028
+ 8003cc8:	40020040 	.word	0x40020040
+ 8003ccc:	40020058 	.word	0x40020058
+ 8003cd0:	40020070 	.word	0x40020070
+ 8003cd4:	40020088 	.word	0x40020088
+ 8003cd8:	400200a0 	.word	0x400200a0
+ 8003cdc:	400200b8 	.word	0x400200b8
+ 8003ce0:	40020410 	.word	0x40020410
+ 8003ce4:	40020428 	.word	0x40020428
+ 8003ce8:	40020440 	.word	0x40020440
+ 8003cec:	40020458 	.word	0x40020458
+ 8003cf0:	40020470 	.word	0x40020470
+ 8003cf4:	40020488 	.word	0x40020488
+ 8003cf8:	400204a0 	.word	0x400204a0
+ 8003cfc:	400204b8 	.word	0x400204b8
+ 8003d00:	aaaaaaab 	.word	0xaaaaaaab
+ 8003d04:	08026b50 	.word	0x08026b50
+ 8003d08:	fffffc00 	.word	0xfffffc00
+
+08003d0c <DMA_CheckFifoParam>:
+  * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
+  *                     the configuration information for the specified DMA Stream.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma)
+{
+ 8003d0c:	b480      	push	{r7}
+ 8003d0e:	b085      	sub	sp, #20
+ 8003d10:	af00      	add	r7, sp, #0
+ 8003d12:	6078      	str	r0, [r7, #4]
+  HAL_StatusTypeDef status = HAL_OK;
+ 8003d14:	2300      	movs	r3, #0
+ 8003d16:	73fb      	strb	r3, [r7, #15]
+
+  /* Memory Data size equal to Byte */
+  if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_BYTE)
+ 8003d18:	687b      	ldr	r3, [r7, #4]
+ 8003d1a:	699b      	ldr	r3, [r3, #24]
+ 8003d1c:	2b00      	cmp	r3, #0
+ 8003d1e:	d120      	bne.n	8003d62 <DMA_CheckFifoParam+0x56>
+  {
+    switch (hdma->Init.FIFOThreshold)
+ 8003d20:	687b      	ldr	r3, [r7, #4]
+ 8003d22:	6a9b      	ldr	r3, [r3, #40]	; 0x28
+ 8003d24:	2b03      	cmp	r3, #3
+ 8003d26:	d858      	bhi.n	8003dda <DMA_CheckFifoParam+0xce>
+ 8003d28:	a201      	add	r2, pc, #4	; (adr r2, 8003d30 <DMA_CheckFifoParam+0x24>)
+ 8003d2a:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
+ 8003d2e:	bf00      	nop
+ 8003d30:	08003d41 	.word	0x08003d41
+ 8003d34:	08003d53 	.word	0x08003d53
+ 8003d38:	08003d41 	.word	0x08003d41
+ 8003d3c:	08003ddb 	.word	0x08003ddb
+    {
+      case DMA_FIFO_THRESHOLD_1QUARTERFULL:
+      case DMA_FIFO_THRESHOLD_3QUARTERSFULL:
+
+        if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
+ 8003d40:	687b      	ldr	r3, [r7, #4]
+ 8003d42:	6adb      	ldr	r3, [r3, #44]	; 0x2c
+ 8003d44:	f003 7380 	and.w	r3, r3, #16777216	; 0x1000000
+ 8003d48:	2b00      	cmp	r3, #0
+ 8003d4a:	d048      	beq.n	8003dde <DMA_CheckFifoParam+0xd2>
+        {
+          status = HAL_ERROR;
+ 8003d4c:	2301      	movs	r3, #1
+ 8003d4e:	73fb      	strb	r3, [r7, #15]
+        }
+        break;
+ 8003d50:	e045      	b.n	8003dde <DMA_CheckFifoParam+0xd2>
+
+      case DMA_FIFO_THRESHOLD_HALFFULL:
+        if (hdma->Init.MemBurst == DMA_MBURST_INC16)
+ 8003d52:	687b      	ldr	r3, [r7, #4]
+ 8003d54:	6adb      	ldr	r3, [r3, #44]	; 0x2c
+ 8003d56:	f1b3 7fc0 	cmp.w	r3, #25165824	; 0x1800000
+ 8003d5a:	d142      	bne.n	8003de2 <DMA_CheckFifoParam+0xd6>
+        {
+          status = HAL_ERROR;
+ 8003d5c:	2301      	movs	r3, #1
+ 8003d5e:	73fb      	strb	r3, [r7, #15]
+        }
+        break;
+ 8003d60:	e03f      	b.n	8003de2 <DMA_CheckFifoParam+0xd6>
+        break;
+    }
+  }
+
+  /* Memory Data size equal to Half-Word */
+  else if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
+ 8003d62:	687b      	ldr	r3, [r7, #4]
+ 8003d64:	699b      	ldr	r3, [r3, #24]
+ 8003d66:	f5b3 5f00 	cmp.w	r3, #8192	; 0x2000
+ 8003d6a:	d123      	bne.n	8003db4 <DMA_CheckFifoParam+0xa8>
+  {
+    switch (hdma->Init.FIFOThreshold)
+ 8003d6c:	687b      	ldr	r3, [r7, #4]
+ 8003d6e:	6a9b      	ldr	r3, [r3, #40]	; 0x28
+ 8003d70:	2b03      	cmp	r3, #3
+ 8003d72:	d838      	bhi.n	8003de6 <DMA_CheckFifoParam+0xda>
+ 8003d74:	a201      	add	r2, pc, #4	; (adr r2, 8003d7c <DMA_CheckFifoParam+0x70>)
+ 8003d76:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
+ 8003d7a:	bf00      	nop
+ 8003d7c:	08003d8d 	.word	0x08003d8d
+ 8003d80:	08003d93 	.word	0x08003d93
+ 8003d84:	08003d8d 	.word	0x08003d8d
+ 8003d88:	08003da5 	.word	0x08003da5
+    {
+      case DMA_FIFO_THRESHOLD_1QUARTERFULL:
+      case DMA_FIFO_THRESHOLD_3QUARTERSFULL:
+        status = HAL_ERROR;
+ 8003d8c:	2301      	movs	r3, #1
+ 8003d8e:	73fb      	strb	r3, [r7, #15]
+        break;
+ 8003d90:	e030      	b.n	8003df4 <DMA_CheckFifoParam+0xe8>
+
+      case DMA_FIFO_THRESHOLD_HALFFULL:
+        if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
+ 8003d92:	687b      	ldr	r3, [r7, #4]
+ 8003d94:	6adb      	ldr	r3, [r3, #44]	; 0x2c
+ 8003d96:	f003 7380 	and.w	r3, r3, #16777216	; 0x1000000
+ 8003d9a:	2b00      	cmp	r3, #0
+ 8003d9c:	d025      	beq.n	8003dea <DMA_CheckFifoParam+0xde>
+        {
+          status = HAL_ERROR;
+ 8003d9e:	2301      	movs	r3, #1
+ 8003da0:	73fb      	strb	r3, [r7, #15]
+        }
+        break;
+ 8003da2:	e022      	b.n	8003dea <DMA_CheckFifoParam+0xde>
+
+      case DMA_FIFO_THRESHOLD_FULL:
+        if (hdma->Init.MemBurst == DMA_MBURST_INC16)
+ 8003da4:	687b      	ldr	r3, [r7, #4]
+ 8003da6:	6adb      	ldr	r3, [r3, #44]	; 0x2c
+ 8003da8:	f1b3 7fc0 	cmp.w	r3, #25165824	; 0x1800000
+ 8003dac:	d11f      	bne.n	8003dee <DMA_CheckFifoParam+0xe2>
+        {
+          status = HAL_ERROR;
+ 8003dae:	2301      	movs	r3, #1
+ 8003db0:	73fb      	strb	r3, [r7, #15]
+        }
+        break;
+ 8003db2:	e01c      	b.n	8003dee <DMA_CheckFifoParam+0xe2>
+  }
+
+  /* Memory Data size equal to Word */
+  else
+  {
+    switch (hdma->Init.FIFOThreshold)
+ 8003db4:	687b      	ldr	r3, [r7, #4]
+ 8003db6:	6a9b      	ldr	r3, [r3, #40]	; 0x28
+ 8003db8:	2b02      	cmp	r3, #2
+ 8003dba:	d902      	bls.n	8003dc2 <DMA_CheckFifoParam+0xb6>
+ 8003dbc:	2b03      	cmp	r3, #3
+ 8003dbe:	d003      	beq.n	8003dc8 <DMA_CheckFifoParam+0xbc>
+          status = HAL_ERROR;
+        }
+    break;
+
+      default:
+        break;
+ 8003dc0:	e018      	b.n	8003df4 <DMA_CheckFifoParam+0xe8>
+        status = HAL_ERROR;
+ 8003dc2:	2301      	movs	r3, #1
+ 8003dc4:	73fb      	strb	r3, [r7, #15]
+        break;
+ 8003dc6:	e015      	b.n	8003df4 <DMA_CheckFifoParam+0xe8>
+        if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
+ 8003dc8:	687b      	ldr	r3, [r7, #4]
+ 8003dca:	6adb      	ldr	r3, [r3, #44]	; 0x2c
+ 8003dcc:	f003 7380 	and.w	r3, r3, #16777216	; 0x1000000
+ 8003dd0:	2b00      	cmp	r3, #0
+ 8003dd2:	d00e      	beq.n	8003df2 <DMA_CheckFifoParam+0xe6>
+          status = HAL_ERROR;
+ 8003dd4:	2301      	movs	r3, #1
+ 8003dd6:	73fb      	strb	r3, [r7, #15]
+    break;
+ 8003dd8:	e00b      	b.n	8003df2 <DMA_CheckFifoParam+0xe6>
+        break;
+ 8003dda:	bf00      	nop
+ 8003ddc:	e00a      	b.n	8003df4 <DMA_CheckFifoParam+0xe8>
+        break;
+ 8003dde:	bf00      	nop
+ 8003de0:	e008      	b.n	8003df4 <DMA_CheckFifoParam+0xe8>
+        break;
+ 8003de2:	bf00      	nop
+ 8003de4:	e006      	b.n	8003df4 <DMA_CheckFifoParam+0xe8>
+        break;
+ 8003de6:	bf00      	nop
+ 8003de8:	e004      	b.n	8003df4 <DMA_CheckFifoParam+0xe8>
+        break;
+ 8003dea:	bf00      	nop
+ 8003dec:	e002      	b.n	8003df4 <DMA_CheckFifoParam+0xe8>
+        break;
+ 8003dee:	bf00      	nop
+ 8003df0:	e000      	b.n	8003df4 <DMA_CheckFifoParam+0xe8>
+    break;
+ 8003df2:	bf00      	nop
+    }
+  }
+
+  return status;
+ 8003df4:	7bfb      	ldrb	r3, [r7, #15]
+}
+ 8003df6:	4618      	mov	r0, r3
+ 8003df8:	3714      	adds	r7, #20
+ 8003dfa:	46bd      	mov	sp, r7
+ 8003dfc:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8003e00:	4770      	bx	lr
+ 8003e02:	bf00      	nop
+
+08003e04 <DMA_CalcDMAMUXChannelBaseAndMask>:
+  * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
+  *                     the configuration information for the specified DMA Stream.
+  * @retval HAL status
+  */
+static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma)
+{
+ 8003e04:	b480      	push	{r7}
+ 8003e06:	b085      	sub	sp, #20
+ 8003e08:	af00      	add	r7, sp, #0
+ 8003e0a:	6078      	str	r0, [r7, #4]
+  uint32_t stream_number;
+  uint32_t stream_baseaddress = (uint32_t)((uint32_t*)hdma->Instance);
+ 8003e0c:	687b      	ldr	r3, [r7, #4]
+ 8003e0e:	681b      	ldr	r3, [r3, #0]
+ 8003e10:	60bb      	str	r3, [r7, #8]
+
+  if(IS_BDMA_CHANNEL_DMAMUX_INSTANCE(hdma->Instance) != 0U)
+ 8003e12:	687b      	ldr	r3, [r7, #4]
+ 8003e14:	681b      	ldr	r3, [r3, #0]
+ 8003e16:	4a38      	ldr	r2, [pc, #224]	; (8003ef8 <DMA_CalcDMAMUXChannelBaseAndMask+0xf4>)
+ 8003e18:	4293      	cmp	r3, r2
+ 8003e1a:	d022      	beq.n	8003e62 <DMA_CalcDMAMUXChannelBaseAndMask+0x5e>
+ 8003e1c:	687b      	ldr	r3, [r7, #4]
+ 8003e1e:	681b      	ldr	r3, [r3, #0]
+ 8003e20:	4a36      	ldr	r2, [pc, #216]	; (8003efc <DMA_CalcDMAMUXChannelBaseAndMask+0xf8>)
+ 8003e22:	4293      	cmp	r3, r2
+ 8003e24:	d01d      	beq.n	8003e62 <DMA_CalcDMAMUXChannelBaseAndMask+0x5e>
+ 8003e26:	687b      	ldr	r3, [r7, #4]
+ 8003e28:	681b      	ldr	r3, [r3, #0]
+ 8003e2a:	4a35      	ldr	r2, [pc, #212]	; (8003f00 <DMA_CalcDMAMUXChannelBaseAndMask+0xfc>)
+ 8003e2c:	4293      	cmp	r3, r2
+ 8003e2e:	d018      	beq.n	8003e62 <DMA_CalcDMAMUXChannelBaseAndMask+0x5e>
+ 8003e30:	687b      	ldr	r3, [r7, #4]
+ 8003e32:	681b      	ldr	r3, [r3, #0]
+ 8003e34:	4a33      	ldr	r2, [pc, #204]	; (8003f04 <DMA_CalcDMAMUXChannelBaseAndMask+0x100>)
+ 8003e36:	4293      	cmp	r3, r2
+ 8003e38:	d013      	beq.n	8003e62 <DMA_CalcDMAMUXChannelBaseAndMask+0x5e>
+ 8003e3a:	687b      	ldr	r3, [r7, #4]
+ 8003e3c:	681b      	ldr	r3, [r3, #0]
+ 8003e3e:	4a32      	ldr	r2, [pc, #200]	; (8003f08 <DMA_CalcDMAMUXChannelBaseAndMask+0x104>)
+ 8003e40:	4293      	cmp	r3, r2
+ 8003e42:	d00e      	beq.n	8003e62 <DMA_CalcDMAMUXChannelBaseAndMask+0x5e>
+ 8003e44:	687b      	ldr	r3, [r7, #4]
+ 8003e46:	681b      	ldr	r3, [r3, #0]
+ 8003e48:	4a30      	ldr	r2, [pc, #192]	; (8003f0c <DMA_CalcDMAMUXChannelBaseAndMask+0x108>)
+ 8003e4a:	4293      	cmp	r3, r2
+ 8003e4c:	d009      	beq.n	8003e62 <DMA_CalcDMAMUXChannelBaseAndMask+0x5e>
+ 8003e4e:	687b      	ldr	r3, [r7, #4]
+ 8003e50:	681b      	ldr	r3, [r3, #0]
+ 8003e52:	4a2f      	ldr	r2, [pc, #188]	; (8003f10 <DMA_CalcDMAMUXChannelBaseAndMask+0x10c>)
+ 8003e54:	4293      	cmp	r3, r2
+ 8003e56:	d004      	beq.n	8003e62 <DMA_CalcDMAMUXChannelBaseAndMask+0x5e>
+ 8003e58:	687b      	ldr	r3, [r7, #4]
+ 8003e5a:	681b      	ldr	r3, [r3, #0]
+ 8003e5c:	4a2d      	ldr	r2, [pc, #180]	; (8003f14 <DMA_CalcDMAMUXChannelBaseAndMask+0x110>)
+ 8003e5e:	4293      	cmp	r3, r2
+ 8003e60:	d101      	bne.n	8003e66 <DMA_CalcDMAMUXChannelBaseAndMask+0x62>
+ 8003e62:	2301      	movs	r3, #1
+ 8003e64:	e000      	b.n	8003e68 <DMA_CalcDMAMUXChannelBaseAndMask+0x64>
+ 8003e66:	2300      	movs	r3, #0
+ 8003e68:	2b00      	cmp	r3, #0
+ 8003e6a:	d01a      	beq.n	8003ea2 <DMA_CalcDMAMUXChannelBaseAndMask+0x9e>
+  {
+    /* BDMA Channels are connected to DMAMUX2 channels */
+    stream_number = (((uint32_t)((uint32_t*)hdma->Instance) & 0xFFU) - 8U) / 20U;
+ 8003e6c:	687b      	ldr	r3, [r7, #4]
+ 8003e6e:	681b      	ldr	r3, [r3, #0]
+ 8003e70:	b2db      	uxtb	r3, r3
+ 8003e72:	3b08      	subs	r3, #8
+ 8003e74:	4a28      	ldr	r2, [pc, #160]	; (8003f18 <DMA_CalcDMAMUXChannelBaseAndMask+0x114>)
+ 8003e76:	fba2 2303 	umull	r2, r3, r2, r3
+ 8003e7a:	091b      	lsrs	r3, r3, #4
+ 8003e7c:	60fb      	str	r3, [r7, #12]
+    hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)((uint32_t)(((uint32_t)DMAMUX2_Channel0) + (stream_number * 4U)));
+ 8003e7e:	68fa      	ldr	r2, [r7, #12]
+ 8003e80:	4b26      	ldr	r3, [pc, #152]	; (8003f1c <DMA_CalcDMAMUXChannelBaseAndMask+0x118>)
+ 8003e82:	4413      	add	r3, r2
+ 8003e84:	009b      	lsls	r3, r3, #2
+ 8003e86:	461a      	mov	r2, r3
+ 8003e88:	687b      	ldr	r3, [r7, #4]
+ 8003e8a:	661a      	str	r2, [r3, #96]	; 0x60
+    hdma->DMAmuxChannelStatus = DMAMUX2_ChannelStatus;
+ 8003e8c:	687b      	ldr	r3, [r7, #4]
+ 8003e8e:	4a24      	ldr	r2, [pc, #144]	; (8003f20 <DMA_CalcDMAMUXChannelBaseAndMask+0x11c>)
+ 8003e90:	665a      	str	r2, [r3, #100]	; 0x64
+    hdma->DMAmuxChannelStatusMask = 1UL << (stream_number & 0x1FU);
+ 8003e92:	68fb      	ldr	r3, [r7, #12]
+ 8003e94:	f003 031f 	and.w	r3, r3, #31
+ 8003e98:	2201      	movs	r2, #1
+ 8003e9a:	409a      	lsls	r2, r3
+ 8003e9c:	687b      	ldr	r3, [r7, #4]
+ 8003e9e:	669a      	str	r2, [r3, #104]	; 0x68
+    }
+    hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_Channel0) + (stream_number * 4U)));
+    hdma->DMAmuxChannelStatus = DMAMUX1_ChannelStatus;
+    hdma->DMAmuxChannelStatusMask = 1UL << (stream_number & 0x1FU);
+  }
+}
+ 8003ea0:	e024      	b.n	8003eec <DMA_CalcDMAMUXChannelBaseAndMask+0xe8>
+    stream_number = (((uint32_t)((uint32_t*)hdma->Instance) & 0xFFU) - 16U) / 24U;
+ 8003ea2:	687b      	ldr	r3, [r7, #4]
+ 8003ea4:	681b      	ldr	r3, [r3, #0]
+ 8003ea6:	b2db      	uxtb	r3, r3
+ 8003ea8:	3b10      	subs	r3, #16
+ 8003eaa:	4a1e      	ldr	r2, [pc, #120]	; (8003f24 <DMA_CalcDMAMUXChannelBaseAndMask+0x120>)
+ 8003eac:	fba2 2303 	umull	r2, r3, r2, r3
+ 8003eb0:	091b      	lsrs	r3, r3, #4
+ 8003eb2:	60fb      	str	r3, [r7, #12]
+    if((stream_baseaddress <= ((uint32_t)DMA2_Stream7) ) && \
+ 8003eb4:	68bb      	ldr	r3, [r7, #8]
+ 8003eb6:	4a1c      	ldr	r2, [pc, #112]	; (8003f28 <DMA_CalcDMAMUXChannelBaseAndMask+0x124>)
+ 8003eb8:	4293      	cmp	r3, r2
+ 8003eba:	d806      	bhi.n	8003eca <DMA_CalcDMAMUXChannelBaseAndMask+0xc6>
+ 8003ebc:	68bb      	ldr	r3, [r7, #8]
+ 8003ebe:	4a1b      	ldr	r2, [pc, #108]	; (8003f2c <DMA_CalcDMAMUXChannelBaseAndMask+0x128>)
+ 8003ec0:	4293      	cmp	r3, r2
+ 8003ec2:	d902      	bls.n	8003eca <DMA_CalcDMAMUXChannelBaseAndMask+0xc6>
+      stream_number += 8U;
+ 8003ec4:	68fb      	ldr	r3, [r7, #12]
+ 8003ec6:	3308      	adds	r3, #8
+ 8003ec8:	60fb      	str	r3, [r7, #12]
+    hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_Channel0) + (stream_number * 4U)));
+ 8003eca:	68fa      	ldr	r2, [r7, #12]
+ 8003ecc:	4b18      	ldr	r3, [pc, #96]	; (8003f30 <DMA_CalcDMAMUXChannelBaseAndMask+0x12c>)
+ 8003ece:	4413      	add	r3, r2
+ 8003ed0:	009b      	lsls	r3, r3, #2
+ 8003ed2:	461a      	mov	r2, r3
+ 8003ed4:	687b      	ldr	r3, [r7, #4]
+ 8003ed6:	661a      	str	r2, [r3, #96]	; 0x60
+    hdma->DMAmuxChannelStatus = DMAMUX1_ChannelStatus;
+ 8003ed8:	687b      	ldr	r3, [r7, #4]
+ 8003eda:	4a16      	ldr	r2, [pc, #88]	; (8003f34 <DMA_CalcDMAMUXChannelBaseAndMask+0x130>)
+ 8003edc:	665a      	str	r2, [r3, #100]	; 0x64
+    hdma->DMAmuxChannelStatusMask = 1UL << (stream_number & 0x1FU);
+ 8003ede:	68fb      	ldr	r3, [r7, #12]
+ 8003ee0:	f003 031f 	and.w	r3, r3, #31
+ 8003ee4:	2201      	movs	r2, #1
+ 8003ee6:	409a      	lsls	r2, r3
+ 8003ee8:	687b      	ldr	r3, [r7, #4]
+ 8003eea:	669a      	str	r2, [r3, #104]	; 0x68
+}
+ 8003eec:	bf00      	nop
+ 8003eee:	3714      	adds	r7, #20
+ 8003ef0:	46bd      	mov	sp, r7
+ 8003ef2:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8003ef6:	4770      	bx	lr
+ 8003ef8:	58025408 	.word	0x58025408
+ 8003efc:	5802541c 	.word	0x5802541c
+ 8003f00:	58025430 	.word	0x58025430
+ 8003f04:	58025444 	.word	0x58025444
+ 8003f08:	58025458 	.word	0x58025458
+ 8003f0c:	5802546c 	.word	0x5802546c
+ 8003f10:	58025480 	.word	0x58025480
+ 8003f14:	58025494 	.word	0x58025494
+ 8003f18:	cccccccd 	.word	0xcccccccd
+ 8003f1c:	16009600 	.word	0x16009600
+ 8003f20:	58025880 	.word	0x58025880
+ 8003f24:	aaaaaaab 	.word	0xaaaaaaab
+ 8003f28:	400204b8 	.word	0x400204b8
+ 8003f2c:	4002040f 	.word	0x4002040f
+ 8003f30:	10008200 	.word	0x10008200
+ 8003f34:	40020880 	.word	0x40020880
+
+08003f38 <DMA_CalcDMAMUXRequestGenBaseAndMask>:
+  * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
+  *                     the configuration information for the specified DMA Stream.
+  * @retval HAL status
+  */
+static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma)
+{
+ 8003f38:	b480      	push	{r7}
+ 8003f3a:	b085      	sub	sp, #20
+ 8003f3c:	af00      	add	r7, sp, #0
+ 8003f3e:	6078      	str	r0, [r7, #4]
+  uint32_t request =  hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID;
+ 8003f40:	687b      	ldr	r3, [r7, #4]
+ 8003f42:	685b      	ldr	r3, [r3, #4]
+ 8003f44:	b2db      	uxtb	r3, r3
+ 8003f46:	60fb      	str	r3, [r7, #12]
+
+  if((request >= DMA_REQUEST_GENERATOR0) && (request <= DMA_REQUEST_GENERATOR7))
+ 8003f48:	68fb      	ldr	r3, [r7, #12]
+ 8003f4a:	2b00      	cmp	r3, #0
+ 8003f4c:	d04a      	beq.n	8003fe4 <DMA_CalcDMAMUXRequestGenBaseAndMask+0xac>
+ 8003f4e:	68fb      	ldr	r3, [r7, #12]
+ 8003f50:	2b08      	cmp	r3, #8
+ 8003f52:	d847      	bhi.n	8003fe4 <DMA_CalcDMAMUXRequestGenBaseAndMask+0xac>
+  {
+    if(IS_BDMA_CHANNEL_DMAMUX_INSTANCE(hdma->Instance) != 0U)
+ 8003f54:	687b      	ldr	r3, [r7, #4]
+ 8003f56:	681b      	ldr	r3, [r3, #0]
+ 8003f58:	4a25      	ldr	r2, [pc, #148]	; (8003ff0 <DMA_CalcDMAMUXRequestGenBaseAndMask+0xb8>)
+ 8003f5a:	4293      	cmp	r3, r2
+ 8003f5c:	d022      	beq.n	8003fa4 <DMA_CalcDMAMUXRequestGenBaseAndMask+0x6c>
+ 8003f5e:	687b      	ldr	r3, [r7, #4]
+ 8003f60:	681b      	ldr	r3, [r3, #0]
+ 8003f62:	4a24      	ldr	r2, [pc, #144]	; (8003ff4 <DMA_CalcDMAMUXRequestGenBaseAndMask+0xbc>)
+ 8003f64:	4293      	cmp	r3, r2
+ 8003f66:	d01d      	beq.n	8003fa4 <DMA_CalcDMAMUXRequestGenBaseAndMask+0x6c>
+ 8003f68:	687b      	ldr	r3, [r7, #4]
+ 8003f6a:	681b      	ldr	r3, [r3, #0]
+ 8003f6c:	4a22      	ldr	r2, [pc, #136]	; (8003ff8 <DMA_CalcDMAMUXRequestGenBaseAndMask+0xc0>)
+ 8003f6e:	4293      	cmp	r3, r2
+ 8003f70:	d018      	beq.n	8003fa4 <DMA_CalcDMAMUXRequestGenBaseAndMask+0x6c>
+ 8003f72:	687b      	ldr	r3, [r7, #4]
+ 8003f74:	681b      	ldr	r3, [r3, #0]
+ 8003f76:	4a21      	ldr	r2, [pc, #132]	; (8003ffc <DMA_CalcDMAMUXRequestGenBaseAndMask+0xc4>)
+ 8003f78:	4293      	cmp	r3, r2
+ 8003f7a:	d013      	beq.n	8003fa4 <DMA_CalcDMAMUXRequestGenBaseAndMask+0x6c>
+ 8003f7c:	687b      	ldr	r3, [r7, #4]
+ 8003f7e:	681b      	ldr	r3, [r3, #0]
+ 8003f80:	4a1f      	ldr	r2, [pc, #124]	; (8004000 <DMA_CalcDMAMUXRequestGenBaseAndMask+0xc8>)
+ 8003f82:	4293      	cmp	r3, r2
+ 8003f84:	d00e      	beq.n	8003fa4 <DMA_CalcDMAMUXRequestGenBaseAndMask+0x6c>
+ 8003f86:	687b      	ldr	r3, [r7, #4]
+ 8003f88:	681b      	ldr	r3, [r3, #0]
+ 8003f8a:	4a1e      	ldr	r2, [pc, #120]	; (8004004 <DMA_CalcDMAMUXRequestGenBaseAndMask+0xcc>)
+ 8003f8c:	4293      	cmp	r3, r2
+ 8003f8e:	d009      	beq.n	8003fa4 <DMA_CalcDMAMUXRequestGenBaseAndMask+0x6c>
+ 8003f90:	687b      	ldr	r3, [r7, #4]
+ 8003f92:	681b      	ldr	r3, [r3, #0]
+ 8003f94:	4a1c      	ldr	r2, [pc, #112]	; (8004008 <DMA_CalcDMAMUXRequestGenBaseAndMask+0xd0>)
+ 8003f96:	4293      	cmp	r3, r2
+ 8003f98:	d004      	beq.n	8003fa4 <DMA_CalcDMAMUXRequestGenBaseAndMask+0x6c>
+ 8003f9a:	687b      	ldr	r3, [r7, #4]
+ 8003f9c:	681b      	ldr	r3, [r3, #0]
+ 8003f9e:	4a1b      	ldr	r2, [pc, #108]	; (800400c <DMA_CalcDMAMUXRequestGenBaseAndMask+0xd4>)
+ 8003fa0:	4293      	cmp	r3, r2
+ 8003fa2:	d101      	bne.n	8003fa8 <DMA_CalcDMAMUXRequestGenBaseAndMask+0x70>
+ 8003fa4:	2301      	movs	r3, #1
+ 8003fa6:	e000      	b.n	8003faa <DMA_CalcDMAMUXRequestGenBaseAndMask+0x72>
+ 8003fa8:	2300      	movs	r3, #0
+ 8003faa:	2b00      	cmp	r3, #0
+ 8003fac:	d00a      	beq.n	8003fc4 <DMA_CalcDMAMUXRequestGenBaseAndMask+0x8c>
+    {
+      /* BDMA Channels are connected to DMAMUX2 request generator blocks */
+      hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((uint32_t)(((uint32_t)DMAMUX2_RequestGenerator0) + ((request - 1U) * 4U)));
+ 8003fae:	68fa      	ldr	r2, [r7, #12]
+ 8003fb0:	4b17      	ldr	r3, [pc, #92]	; (8004010 <DMA_CalcDMAMUXRequestGenBaseAndMask+0xd8>)
+ 8003fb2:	4413      	add	r3, r2
+ 8003fb4:	009b      	lsls	r3, r3, #2
+ 8003fb6:	461a      	mov	r2, r3
+ 8003fb8:	687b      	ldr	r3, [r7, #4]
+ 8003fba:	66da      	str	r2, [r3, #108]	; 0x6c
+
+      hdma->DMAmuxRequestGenStatus = DMAMUX2_RequestGenStatus;
+ 8003fbc:	687b      	ldr	r3, [r7, #4]
+ 8003fbe:	4a15      	ldr	r2, [pc, #84]	; (8004014 <DMA_CalcDMAMUXRequestGenBaseAndMask+0xdc>)
+ 8003fc0:	671a      	str	r2, [r3, #112]	; 0x70
+ 8003fc2:	e009      	b.n	8003fd8 <DMA_CalcDMAMUXRequestGenBaseAndMask+0xa0>
+    }
+    else
+    {
+      /* DMA1 and DMA2 Streams use DMAMUX1 request generator blocks */
+      hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_RequestGenerator0) + ((request - 1U) * 4U)));
+ 8003fc4:	68fa      	ldr	r2, [r7, #12]
+ 8003fc6:	4b14      	ldr	r3, [pc, #80]	; (8004018 <DMA_CalcDMAMUXRequestGenBaseAndMask+0xe0>)
+ 8003fc8:	4413      	add	r3, r2
+ 8003fca:	009b      	lsls	r3, r3, #2
+ 8003fcc:	461a      	mov	r2, r3
+ 8003fce:	687b      	ldr	r3, [r7, #4]
+ 8003fd0:	66da      	str	r2, [r3, #108]	; 0x6c
+
+      hdma->DMAmuxRequestGenStatus = DMAMUX1_RequestGenStatus;
+ 8003fd2:	687b      	ldr	r3, [r7, #4]
+ 8003fd4:	4a11      	ldr	r2, [pc, #68]	; (800401c <DMA_CalcDMAMUXRequestGenBaseAndMask+0xe4>)
+ 8003fd6:	671a      	str	r2, [r3, #112]	; 0x70
+    }
+
+    hdma->DMAmuxRequestGenStatusMask = 1UL << (request - 1U);
+ 8003fd8:	68fb      	ldr	r3, [r7, #12]
+ 8003fda:	3b01      	subs	r3, #1
+ 8003fdc:	2201      	movs	r2, #1
+ 8003fde:	409a      	lsls	r2, r3
+ 8003fe0:	687b      	ldr	r3, [r7, #4]
+ 8003fe2:	675a      	str	r2, [r3, #116]	; 0x74
+  }
+}
+ 8003fe4:	bf00      	nop
+ 8003fe6:	3714      	adds	r7, #20
+ 8003fe8:	46bd      	mov	sp, r7
+ 8003fea:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8003fee:	4770      	bx	lr
+ 8003ff0:	58025408 	.word	0x58025408
+ 8003ff4:	5802541c 	.word	0x5802541c
+ 8003ff8:	58025430 	.word	0x58025430
+ 8003ffc:	58025444 	.word	0x58025444
+ 8004000:	58025458 	.word	0x58025458
+ 8004004:	5802546c 	.word	0x5802546c
+ 8004008:	58025480 	.word	0x58025480
+ 800400c:	58025494 	.word	0x58025494
+ 8004010:	1600963f 	.word	0x1600963f
+ 8004014:	58025940 	.word	0x58025940
+ 8004018:	1000823f 	.word	0x1000823f
+ 800401c:	40020940 	.word	0x40020940
+
+08004020 <HAL_ETH_Init>:
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)
+{
+ 8004020:	b580      	push	{r7, lr}
+ 8004022:	b084      	sub	sp, #16
+ 8004024:	af00      	add	r7, sp, #0
+ 8004026:	6078      	str	r0, [r7, #4]
+  uint32_t tickstart;
+
+  if (heth == NULL)
+ 8004028:	687b      	ldr	r3, [r7, #4]
+ 800402a:	2b00      	cmp	r3, #0
+ 800402c:	d101      	bne.n	8004032 <HAL_ETH_Init+0x12>
+  {
+    return HAL_ERROR;
+ 800402e:	2301      	movs	r3, #1
+ 8004030:	e0cf      	b.n	80041d2 <HAL_ETH_Init+0x1b2>
+  }
+  if (heth->gState == HAL_ETH_STATE_RESET)
+ 8004032:	687b      	ldr	r3, [r7, #4]
+ 8004034:	f8d3 3084 	ldr.w	r3, [r3, #132]	; 0x84
+ 8004038:	2b00      	cmp	r3, #0
+ 800403a:	d106      	bne.n	800404a <HAL_ETH_Init+0x2a>
+  {
+    heth->gState = HAL_ETH_STATE_BUSY;
+ 800403c:	687b      	ldr	r3, [r7, #4]
+ 800403e:	2223      	movs	r2, #35	; 0x23
+ 8004040:	f8c3 2084 	str.w	r2, [r3, #132]	; 0x84
+
+    /* Init the low level hardware */
+    heth->MspInitCallback(heth);
+#else
+    /* Init the low level hardware : GPIO, CLOCK, NVIC. */
+    HAL_ETH_MspInit(heth);
+ 8004044:	6878      	ldr	r0, [r7, #4]
+ 8004046:	f00b fe73 	bl	800fd30 <HAL_ETH_MspInit>
+
+#endif /* (USE_HAL_ETH_REGISTER_CALLBACKS) */
+  }
+
+  __HAL_RCC_SYSCFG_CLK_ENABLE();
+ 800404a:	4b64      	ldr	r3, [pc, #400]	; (80041dc <HAL_ETH_Init+0x1bc>)
+ 800404c:	f8d3 30f4 	ldr.w	r3, [r3, #244]	; 0xf4
+ 8004050:	4a62      	ldr	r2, [pc, #392]	; (80041dc <HAL_ETH_Init+0x1bc>)
+ 8004052:	f043 0302 	orr.w	r3, r3, #2
+ 8004056:	f8c2 30f4 	str.w	r3, [r2, #244]	; 0xf4
+ 800405a:	4b60      	ldr	r3, [pc, #384]	; (80041dc <HAL_ETH_Init+0x1bc>)
+ 800405c:	f8d3 30f4 	ldr.w	r3, [r3, #244]	; 0xf4
+ 8004060:	f003 0302 	and.w	r3, r3, #2
+ 8004064:	60bb      	str	r3, [r7, #8]
+ 8004066:	68bb      	ldr	r3, [r7, #8]
+
+  if (heth->Init.MediaInterface == HAL_ETH_MII_MODE)
+ 8004068:	687b      	ldr	r3, [r7, #4]
+ 800406a:	7a1b      	ldrb	r3, [r3, #8]
+ 800406c:	2b00      	cmp	r3, #0
+ 800406e:	d103      	bne.n	8004078 <HAL_ETH_Init+0x58>
+  {
+    HAL_SYSCFG_ETHInterfaceSelect(SYSCFG_ETH_MII);
+ 8004070:	2000      	movs	r0, #0
+ 8004072:	f7fe f9a7 	bl	80023c4 <HAL_SYSCFG_ETHInterfaceSelect>
+ 8004076:	e003      	b.n	8004080 <HAL_ETH_Init+0x60>
+  }
+  else
+  {
+    HAL_SYSCFG_ETHInterfaceSelect(SYSCFG_ETH_RMII);
+ 8004078:	f44f 0000 	mov.w	r0, #8388608	; 0x800000
+ 800407c:	f7fe f9a2 	bl	80023c4 <HAL_SYSCFG_ETHInterfaceSelect>
+  }
+
+  /* Dummy read to sync with ETH */
+  (void)SYSCFG->PMCR;
+ 8004080:	4b57      	ldr	r3, [pc, #348]	; (80041e0 <HAL_ETH_Init+0x1c0>)
+ 8004082:	685b      	ldr	r3, [r3, #4]
+
+  /* Ethernet Software reset */
+  /* Set the SWR bit: resets all MAC subsystem internal registers and logic */
+  /* After reset all the registers holds their respective reset values */
+  SET_BIT(heth->Instance->DMAMR, ETH_DMAMR_SWR);
+ 8004084:	687b      	ldr	r3, [r7, #4]
+ 8004086:	681b      	ldr	r3, [r3, #0]
+ 8004088:	f503 5380 	add.w	r3, r3, #4096	; 0x1000
+ 800408c:	681b      	ldr	r3, [r3, #0]
+ 800408e:	687a      	ldr	r2, [r7, #4]
+ 8004090:	6812      	ldr	r2, [r2, #0]
+ 8004092:	f043 0301 	orr.w	r3, r3, #1
+ 8004096:	f502 5280 	add.w	r2, r2, #4096	; 0x1000
+ 800409a:	6013      	str	r3, [r2, #0]
+
+  /* Get tick */
+  tickstart = HAL_GetTick();
+ 800409c:	f7fe f962 	bl	8002364 <HAL_GetTick>
+ 80040a0:	60f8      	str	r0, [r7, #12]
+
+  /* Wait for software reset */
+  while (READ_BIT(heth->Instance->DMAMR, ETH_DMAMR_SWR) > 0U)
+ 80040a2:	e011      	b.n	80040c8 <HAL_ETH_Init+0xa8>
+  {
+    if (((HAL_GetTick() - tickstart) > ETH_SWRESET_TIMEOUT))
+ 80040a4:	f7fe f95e 	bl	8002364 <HAL_GetTick>
+ 80040a8:	4602      	mov	r2, r0
+ 80040aa:	68fb      	ldr	r3, [r7, #12]
+ 80040ac:	1ad3      	subs	r3, r2, r3
+ 80040ae:	f5b3 7ffa 	cmp.w	r3, #500	; 0x1f4
+ 80040b2:	d909      	bls.n	80040c8 <HAL_ETH_Init+0xa8>
+    {
+      /* Set Error Code */
+      heth->ErrorCode = HAL_ETH_ERROR_TIMEOUT;
+ 80040b4:	687b      	ldr	r3, [r7, #4]
+ 80040b6:	2204      	movs	r2, #4
+ 80040b8:	f8c3 2088 	str.w	r2, [r3, #136]	; 0x88
+      /* Set State as Error */
+      heth->gState = HAL_ETH_STATE_ERROR;
+ 80040bc:	687b      	ldr	r3, [r7, #4]
+ 80040be:	22e0      	movs	r2, #224	; 0xe0
+ 80040c0:	f8c3 2084 	str.w	r2, [r3, #132]	; 0x84
+      /* Return Error */
+      return HAL_ERROR;
+ 80040c4:	2301      	movs	r3, #1
+ 80040c6:	e084      	b.n	80041d2 <HAL_ETH_Init+0x1b2>
+  while (READ_BIT(heth->Instance->DMAMR, ETH_DMAMR_SWR) > 0U)
+ 80040c8:	687b      	ldr	r3, [r7, #4]
+ 80040ca:	681b      	ldr	r3, [r3, #0]
+ 80040cc:	f503 5380 	add.w	r3, r3, #4096	; 0x1000
+ 80040d0:	681b      	ldr	r3, [r3, #0]
+ 80040d2:	f003 0301 	and.w	r3, r3, #1
+ 80040d6:	2b00      	cmp	r3, #0
+ 80040d8:	d1e4      	bne.n	80040a4 <HAL_ETH_Init+0x84>
+    }
+  }
+
+  /*------------------ MDIO CSR Clock Range Configuration --------------------*/
+  HAL_ETH_SetMDIOClockRange(heth);
+ 80040da:	6878      	ldr	r0, [r7, #4]
+ 80040dc:	f000 ff28 	bl	8004f30 <HAL_ETH_SetMDIOClockRange>
+
+  /*------------------ MAC LPI 1US Tic Counter Configuration --------------------*/
+  WRITE_REG(heth->Instance->MAC1USTCR, (((uint32_t)HAL_RCC_GetHCLKFreq() / ETH_MAC_US_TICK) - 1U));
+ 80040e0:	f003 ff0e 	bl	8007f00 <HAL_RCC_GetHCLKFreq>
+ 80040e4:	4603      	mov	r3, r0
+ 80040e6:	4a3f      	ldr	r2, [pc, #252]	; (80041e4 <HAL_ETH_Init+0x1c4>)
+ 80040e8:	fba2 2303 	umull	r2, r3, r2, r3
+ 80040ec:	0c9a      	lsrs	r2, r3, #18
+ 80040ee:	687b      	ldr	r3, [r7, #4]
+ 80040f0:	681b      	ldr	r3, [r3, #0]
+ 80040f2:	3a01      	subs	r2, #1
+ 80040f4:	f8c3 20dc 	str.w	r2, [r3, #220]	; 0xdc
+
+  /*------------------ MAC, MTL and DMA default Configuration ----------------*/
+  ETH_MACDMAConfig(heth);
+ 80040f8:	6878      	ldr	r0, [r7, #4]
+ 80040fa:	f001 f921 	bl	8005340 <ETH_MACDMAConfig>
+
+  /* SET DSL to 64 bit */
+  MODIFY_REG(heth->Instance->DMACCR, ETH_DMACCR_DSL, ETH_DMACCR_DSL_64BIT);
+ 80040fe:	687b      	ldr	r3, [r7, #4]
+ 8004100:	681b      	ldr	r3, [r3, #0]
+ 8004102:	f503 5380 	add.w	r3, r3, #4096	; 0x1000
+ 8004106:	f8d3 3100 	ldr.w	r3, [r3, #256]	; 0x100
+ 800410a:	f423 13e0 	bic.w	r3, r3, #1835008	; 0x1c0000
+ 800410e:	687a      	ldr	r2, [r7, #4]
+ 8004110:	6812      	ldr	r2, [r2, #0]
+ 8004112:	f443 2300 	orr.w	r3, r3, #524288	; 0x80000
+ 8004116:	f502 5280 	add.w	r2, r2, #4096	; 0x1000
+ 800411a:	f8c2 3100 	str.w	r3, [r2, #256]	; 0x100
+
+  /* Set Receive Buffers Length (must be a multiple of 4) */
+  if ((heth->Init.RxBuffLen % 0x4U) != 0x0U)
+ 800411e:	687b      	ldr	r3, [r7, #4]
+ 8004120:	695b      	ldr	r3, [r3, #20]
+ 8004122:	f003 0303 	and.w	r3, r3, #3
+ 8004126:	2b00      	cmp	r3, #0
+ 8004128:	d009      	beq.n	800413e <HAL_ETH_Init+0x11e>
+  {
+    /* Set Error Code */
+    heth->ErrorCode = HAL_ETH_ERROR_PARAM;
+ 800412a:	687b      	ldr	r3, [r7, #4]
+ 800412c:	2201      	movs	r2, #1
+ 800412e:	f8c3 2088 	str.w	r2, [r3, #136]	; 0x88
+    /* Set State as Error */
+    heth->gState = HAL_ETH_STATE_ERROR;
+ 8004132:	687b      	ldr	r3, [r7, #4]
+ 8004134:	22e0      	movs	r2, #224	; 0xe0
+ 8004136:	f8c3 2084 	str.w	r2, [r3, #132]	; 0x84
+    /* Return Error */
+    return HAL_ERROR;
+ 800413a:	2301      	movs	r3, #1
+ 800413c:	e049      	b.n	80041d2 <HAL_ETH_Init+0x1b2>
+  }
+  else
+  {
+    MODIFY_REG(heth->Instance->DMACRCR, ETH_DMACRCR_RBSZ, ((heth->Init.RxBuffLen) << 1));
+ 800413e:	687b      	ldr	r3, [r7, #4]
+ 8004140:	681b      	ldr	r3, [r3, #0]
+ 8004142:	f503 5380 	add.w	r3, r3, #4096	; 0x1000
+ 8004146:	f8d3 2108 	ldr.w	r2, [r3, #264]	; 0x108
+ 800414a:	4b27      	ldr	r3, [pc, #156]	; (80041e8 <HAL_ETH_Init+0x1c8>)
+ 800414c:	4013      	ands	r3, r2
+ 800414e:	687a      	ldr	r2, [r7, #4]
+ 8004150:	6952      	ldr	r2, [r2, #20]
+ 8004152:	0051      	lsls	r1, r2, #1
+ 8004154:	687a      	ldr	r2, [r7, #4]
+ 8004156:	6812      	ldr	r2, [r2, #0]
+ 8004158:	430b      	orrs	r3, r1
+ 800415a:	f502 5280 	add.w	r2, r2, #4096	; 0x1000
+ 800415e:	f8c2 3108 	str.w	r3, [r2, #264]	; 0x108
+  }
+
+  /*------------------ DMA Tx Descriptors Configuration ----------------------*/
+  ETH_DMATxDescListInit(heth);
+ 8004162:	6878      	ldr	r0, [r7, #4]
+ 8004164:	f001 f989 	bl	800547a <ETH_DMATxDescListInit>
+
+  /*------------------ DMA Rx Descriptors Configuration ----------------------*/
+  ETH_DMARxDescListInit(heth);
+ 8004168:	6878      	ldr	r0, [r7, #4]
+ 800416a:	f001 f9cf 	bl	800550c <ETH_DMARxDescListInit>
+
+  /*--------------------- ETHERNET MAC Address Configuration ------------------*/
+  /* Set MAC addr bits 32 to 47 */
+  heth->Instance->MACA0HR = (((uint32_t)(heth->Init.MACAddr[5]) << 8) | (uint32_t)heth->Init.MACAddr[4]);
+ 800416e:	687b      	ldr	r3, [r7, #4]
+ 8004170:	685b      	ldr	r3, [r3, #4]
+ 8004172:	3305      	adds	r3, #5
+ 8004174:	781b      	ldrb	r3, [r3, #0]
+ 8004176:	021a      	lsls	r2, r3, #8
+ 8004178:	687b      	ldr	r3, [r7, #4]
+ 800417a:	685b      	ldr	r3, [r3, #4]
+ 800417c:	3304      	adds	r3, #4
+ 800417e:	781b      	ldrb	r3, [r3, #0]
+ 8004180:	4619      	mov	r1, r3
+ 8004182:	687b      	ldr	r3, [r7, #4]
+ 8004184:	681b      	ldr	r3, [r3, #0]
+ 8004186:	430a      	orrs	r2, r1
+ 8004188:	f8c3 2300 	str.w	r2, [r3, #768]	; 0x300
+  /* Set MAC addr bits 0 to 31 */
+  heth->Instance->MACA0LR = (((uint32_t)(heth->Init.MACAddr[3]) << 24) | ((uint32_t)(heth->Init.MACAddr[2]) << 16) |
+ 800418c:	687b      	ldr	r3, [r7, #4]
+ 800418e:	685b      	ldr	r3, [r3, #4]
+ 8004190:	3303      	adds	r3, #3
+ 8004192:	781b      	ldrb	r3, [r3, #0]
+ 8004194:	061a      	lsls	r2, r3, #24
+ 8004196:	687b      	ldr	r3, [r7, #4]
+ 8004198:	685b      	ldr	r3, [r3, #4]
+ 800419a:	3302      	adds	r3, #2
+ 800419c:	781b      	ldrb	r3, [r3, #0]
+ 800419e:	041b      	lsls	r3, r3, #16
+ 80041a0:	431a      	orrs	r2, r3
+                             ((uint32_t)(heth->Init.MACAddr[1]) << 8) | (uint32_t)heth->Init.MACAddr[0]);
+ 80041a2:	687b      	ldr	r3, [r7, #4]
+ 80041a4:	685b      	ldr	r3, [r3, #4]
+ 80041a6:	3301      	adds	r3, #1
+ 80041a8:	781b      	ldrb	r3, [r3, #0]
+ 80041aa:	021b      	lsls	r3, r3, #8
+  heth->Instance->MACA0LR = (((uint32_t)(heth->Init.MACAddr[3]) << 24) | ((uint32_t)(heth->Init.MACAddr[2]) << 16) |
+ 80041ac:	431a      	orrs	r2, r3
+                             ((uint32_t)(heth->Init.MACAddr[1]) << 8) | (uint32_t)heth->Init.MACAddr[0]);
+ 80041ae:	687b      	ldr	r3, [r7, #4]
+ 80041b0:	685b      	ldr	r3, [r3, #4]
+ 80041b2:	781b      	ldrb	r3, [r3, #0]
+ 80041b4:	4619      	mov	r1, r3
+  heth->Instance->MACA0LR = (((uint32_t)(heth->Init.MACAddr[3]) << 24) | ((uint32_t)(heth->Init.MACAddr[2]) << 16) |
+ 80041b6:	687b      	ldr	r3, [r7, #4]
+ 80041b8:	681b      	ldr	r3, [r3, #0]
+                             ((uint32_t)(heth->Init.MACAddr[1]) << 8) | (uint32_t)heth->Init.MACAddr[0]);
+ 80041ba:	430a      	orrs	r2, r1
+  heth->Instance->MACA0LR = (((uint32_t)(heth->Init.MACAddr[3]) << 24) | ((uint32_t)(heth->Init.MACAddr[2]) << 16) |
+ 80041bc:	f8c3 2304 	str.w	r2, [r3, #772]	; 0x304
+
+  heth->ErrorCode = HAL_ETH_ERROR_NONE;
+ 80041c0:	687b      	ldr	r3, [r7, #4]
+ 80041c2:	2200      	movs	r2, #0
+ 80041c4:	f8c3 2088 	str.w	r2, [r3, #136]	; 0x88
+  heth->gState = HAL_ETH_STATE_READY;
+ 80041c8:	687b      	ldr	r3, [r7, #4]
+ 80041ca:	2210      	movs	r2, #16
+ 80041cc:	f8c3 2084 	str.w	r2, [r3, #132]	; 0x84
+
+  return HAL_OK;
+ 80041d0:	2300      	movs	r3, #0
+}
+ 80041d2:	4618      	mov	r0, r3
+ 80041d4:	3710      	adds	r7, #16
+ 80041d6:	46bd      	mov	sp, r7
+ 80041d8:	bd80      	pop	{r7, pc}
+ 80041da:	bf00      	nop
+ 80041dc:	58024400 	.word	0x58024400
+ 80041e0:	58000400 	.word	0x58000400
+ 80041e4:	431bde83 	.word	0x431bde83
+ 80041e8:	ffff8001 	.word	0xffff8001
+
+080041ec <HAL_ETH_Start_IT>:
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ETH_Start_IT(ETH_HandleTypeDef *heth)
+{
+ 80041ec:	b580      	push	{r7, lr}
+ 80041ee:	b082      	sub	sp, #8
+ 80041f0:	af00      	add	r7, sp, #0
+ 80041f2:	6078      	str	r0, [r7, #4]
+  if (heth->gState == HAL_ETH_STATE_READY)
+ 80041f4:	687b      	ldr	r3, [r7, #4]
+ 80041f6:	f8d3 3084 	ldr.w	r3, [r3, #132]	; 0x84
+ 80041fa:	2b10      	cmp	r3, #16
+ 80041fc:	d179      	bne.n	80042f2 <HAL_ETH_Start_IT+0x106>
+  {
+    heth->gState = HAL_ETH_STATE_BUSY;
+ 80041fe:	687b      	ldr	r3, [r7, #4]
+ 8004200:	2223      	movs	r2, #35	; 0x23
+ 8004202:	f8c3 2084 	str.w	r2, [r3, #132]	; 0x84
+
+    /* save IT mode to ETH Handle */
+    heth->RxDescList.ItMode = 1U;
+ 8004206:	687b      	ldr	r3, [r7, #4]
+ 8004208:	2201      	movs	r2, #1
+ 800420a:	659a      	str	r2, [r3, #88]	; 0x58
+    /* Disable Rx MMC Interrupts */
+    SET_BIT(heth->Instance->MMCRIMR, ETH_MMCRIMR_RXLPITRCIM | ETH_MMCRIMR_RXLPIUSCIM | \
+ 800420c:	687b      	ldr	r3, [r7, #4]
+ 800420e:	681b      	ldr	r3, [r3, #0]
+ 8004210:	f8d3 170c 	ldr.w	r1, [r3, #1804]	; 0x70c
+ 8004214:	687b      	ldr	r3, [r7, #4]
+ 8004216:	681a      	ldr	r2, [r3, #0]
+ 8004218:	4b38      	ldr	r3, [pc, #224]	; (80042fc <HAL_ETH_Start_IT+0x110>)
+ 800421a:	430b      	orrs	r3, r1
+ 800421c:	f8c2 370c 	str.w	r3, [r2, #1804]	; 0x70c
+            ETH_MMCRIMR_RXUCGPIM | ETH_MMCRIMR_RXALGNERPIM | ETH_MMCRIMR_RXCRCERPIM);
+
+    /* Disable Tx MMC Interrupts */
+    SET_BIT(heth->Instance->MMCTIMR, ETH_MMCTIMR_TXLPITRCIM | ETH_MMCTIMR_TXLPIUSCIM | \
+ 8004220:	687b      	ldr	r3, [r7, #4]
+ 8004222:	681b      	ldr	r3, [r3, #0]
+ 8004224:	f8d3 1710 	ldr.w	r1, [r3, #1808]	; 0x710
+ 8004228:	687b      	ldr	r3, [r7, #4]
+ 800422a:	681a      	ldr	r2, [r3, #0]
+ 800422c:	4b34      	ldr	r3, [pc, #208]	; (8004300 <HAL_ETH_Start_IT+0x114>)
+ 800422e:	430b      	orrs	r3, r1
+ 8004230:	f8c2 3710 	str.w	r3, [r2, #1808]	; 0x710
+            ETH_MMCTIMR_TXGPKTIM | ETH_MMCTIMR_TXMCOLGPIM | ETH_MMCTIMR_TXSCOLGPIM);
+
+    /* Set nombre of descriptors to build */
+    heth->RxDescList.RxBuildDescCnt = ETH_RX_DESC_CNT;
+ 8004234:	687b      	ldr	r3, [r7, #4]
+ 8004236:	2204      	movs	r2, #4
+ 8004238:	66da      	str	r2, [r3, #108]	; 0x6c
+
+    /* Build all descriptors */
+    ETH_UpdateDescriptor(heth);
+ 800423a:	6878      	ldr	r0, [r7, #4]
+ 800423c:	f000 f9eb 	bl	8004616 <ETH_UpdateDescriptor>
+
+    /* Enable the MAC transmission */
+    SET_BIT(heth->Instance->MACCR, ETH_MACCR_TE);
+ 8004240:	687b      	ldr	r3, [r7, #4]
+ 8004242:	681b      	ldr	r3, [r3, #0]
+ 8004244:	681a      	ldr	r2, [r3, #0]
+ 8004246:	687b      	ldr	r3, [r7, #4]
+ 8004248:	681b      	ldr	r3, [r3, #0]
+ 800424a:	f042 0202 	orr.w	r2, r2, #2
+ 800424e:	601a      	str	r2, [r3, #0]
+
+    /* Enable the MAC reception */
+    SET_BIT(heth->Instance->MACCR, ETH_MACCR_RE);
+ 8004250:	687b      	ldr	r3, [r7, #4]
+ 8004252:	681b      	ldr	r3, [r3, #0]
+ 8004254:	681a      	ldr	r2, [r3, #0]
+ 8004256:	687b      	ldr	r3, [r7, #4]
+ 8004258:	681b      	ldr	r3, [r3, #0]
+ 800425a:	f042 0201 	orr.w	r2, r2, #1
+ 800425e:	601a      	str	r2, [r3, #0]
+
+    /* Set the Flush Transmit FIFO bit */
+    SET_BIT(heth->Instance->MTLTQOMR, ETH_MTLTQOMR_FTQ);
+ 8004260:	687b      	ldr	r3, [r7, #4]
+ 8004262:	681b      	ldr	r3, [r3, #0]
+ 8004264:	f8d3 2d00 	ldr.w	r2, [r3, #3328]	; 0xd00
+ 8004268:	687b      	ldr	r3, [r7, #4]
+ 800426a:	681b      	ldr	r3, [r3, #0]
+ 800426c:	f042 0201 	orr.w	r2, r2, #1
+ 8004270:	f8c3 2d00 	str.w	r2, [r3, #3328]	; 0xd00
+
+    /* Enable the DMA transmission */
+    SET_BIT(heth->Instance->DMACTCR, ETH_DMACTCR_ST);
+ 8004274:	687b      	ldr	r3, [r7, #4]
+ 8004276:	681b      	ldr	r3, [r3, #0]
+ 8004278:	f503 5380 	add.w	r3, r3, #4096	; 0x1000
+ 800427c:	f8d3 3104 	ldr.w	r3, [r3, #260]	; 0x104
+ 8004280:	687a      	ldr	r2, [r7, #4]
+ 8004282:	6812      	ldr	r2, [r2, #0]
+ 8004284:	f043 0301 	orr.w	r3, r3, #1
+ 8004288:	f502 5280 	add.w	r2, r2, #4096	; 0x1000
+ 800428c:	f8c2 3104 	str.w	r3, [r2, #260]	; 0x104
+
+    /* Enable the DMA reception */
+    SET_BIT(heth->Instance->DMACRCR, ETH_DMACRCR_SR);
+ 8004290:	687b      	ldr	r3, [r7, #4]
+ 8004292:	681b      	ldr	r3, [r3, #0]
+ 8004294:	f503 5380 	add.w	r3, r3, #4096	; 0x1000
+ 8004298:	f8d3 3108 	ldr.w	r3, [r3, #264]	; 0x108
+ 800429c:	687a      	ldr	r2, [r7, #4]
+ 800429e:	6812      	ldr	r2, [r2, #0]
+ 80042a0:	f043 0301 	orr.w	r3, r3, #1
+ 80042a4:	f502 5280 	add.w	r2, r2, #4096	; 0x1000
+ 80042a8:	f8c2 3108 	str.w	r3, [r2, #264]	; 0x108
+
+    /* Clear Tx and Rx process stopped flags */
+    heth->Instance->DMACSR |= (ETH_DMACSR_TPS | ETH_DMACSR_RPS);
+ 80042ac:	687b      	ldr	r3, [r7, #4]
+ 80042ae:	681b      	ldr	r3, [r3, #0]
+ 80042b0:	f503 5380 	add.w	r3, r3, #4096	; 0x1000
+ 80042b4:	f8d3 3160 	ldr.w	r3, [r3, #352]	; 0x160
+ 80042b8:	687a      	ldr	r2, [r7, #4]
+ 80042ba:	6812      	ldr	r2, [r2, #0]
+ 80042bc:	f443 7381 	orr.w	r3, r3, #258	; 0x102
+ 80042c0:	f502 5280 	add.w	r2, r2, #4096	; 0x1000
+ 80042c4:	f8c2 3160 	str.w	r3, [r2, #352]	; 0x160
+    /* Enable ETH DMA interrupts:
+    - Tx complete interrupt
+    - Rx complete interrupt
+    - Fatal bus interrupt
+    */
+    __HAL_ETH_DMA_ENABLE_IT(heth, (ETH_DMACIER_NIE | ETH_DMACIER_RIE | ETH_DMACIER_TIE  |
+ 80042c8:	687b      	ldr	r3, [r7, #4]
+ 80042ca:	681b      	ldr	r3, [r3, #0]
+ 80042cc:	f503 5380 	add.w	r3, r3, #4096	; 0x1000
+ 80042d0:	f8d3 1134 	ldr.w	r1, [r3, #308]	; 0x134
+ 80042d4:	687b      	ldr	r3, [r7, #4]
+ 80042d6:	681a      	ldr	r2, [r3, #0]
+ 80042d8:	f24d 03c1 	movw	r3, #53441	; 0xd0c1
+ 80042dc:	430b      	orrs	r3, r1
+ 80042de:	f502 5280 	add.w	r2, r2, #4096	; 0x1000
+ 80042e2:	f8c2 3134 	str.w	r3, [r2, #308]	; 0x134
+                                   ETH_DMACIER_FBEE | ETH_DMACIER_AIE | ETH_DMACIER_RBUE));
+
+    heth->gState = HAL_ETH_STATE_STARTED;
+ 80042e6:	687b      	ldr	r3, [r7, #4]
+ 80042e8:	2223      	movs	r2, #35	; 0x23
+ 80042ea:	f8c3 2084 	str.w	r2, [r3, #132]	; 0x84
+    return HAL_OK;
+ 80042ee:	2300      	movs	r3, #0
+ 80042f0:	e000      	b.n	80042f4 <HAL_ETH_Start_IT+0x108>
+  }
+  else
+  {
+    return HAL_ERROR;
+ 80042f2:	2301      	movs	r3, #1
+  }
+}
+ 80042f4:	4618      	mov	r0, r3
+ 80042f6:	3708      	adds	r7, #8
+ 80042f8:	46bd      	mov	sp, r7
+ 80042fa:	bd80      	pop	{r7, pc}
+ 80042fc:	0c020060 	.word	0x0c020060
+ 8004300:	0c20c000 	.word	0x0c20c000
+
+08004304 <HAL_ETH_Stop_IT>:
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ETH_Stop_IT(ETH_HandleTypeDef *heth)
+{
+ 8004304:	b480      	push	{r7}
+ 8004306:	b085      	sub	sp, #20
+ 8004308:	af00      	add	r7, sp, #0
+ 800430a:	6078      	str	r0, [r7, #4]
+  ETH_DMADescTypeDef *dmarxdesc;
+  uint32_t descindex;
+
+  if (heth->gState == HAL_ETH_STATE_STARTED)
+ 800430c:	687b      	ldr	r3, [r7, #4]
+ 800430e:	f8d3 3084 	ldr.w	r3, [r3, #132]	; 0x84
+ 8004312:	2b23      	cmp	r3, #35	; 0x23
+ 8004314:	d165      	bne.n	80043e2 <HAL_ETH_Stop_IT+0xde>
+  {
+    /* Set the ETH peripheral state to BUSY */
+    heth->gState = HAL_ETH_STATE_BUSY;
+ 8004316:	687b      	ldr	r3, [r7, #4]
+ 8004318:	2223      	movs	r2, #35	; 0x23
+ 800431a:	f8c3 2084 	str.w	r2, [r3, #132]	; 0x84
+    /* Disable interrupts:
+    - Tx complete interrupt
+    - Rx complete interrupt
+    - Fatal bus interrupt
+    */
+    __HAL_ETH_DMA_DISABLE_IT(heth, (ETH_DMACIER_NIE | ETH_DMACIER_RIE | ETH_DMACIER_TIE  |
+ 800431e:	687b      	ldr	r3, [r7, #4]
+ 8004320:	681b      	ldr	r3, [r3, #0]
+ 8004322:	f503 5380 	add.w	r3, r3, #4096	; 0x1000
+ 8004326:	f8d3 1134 	ldr.w	r1, [r3, #308]	; 0x134
+ 800432a:	687b      	ldr	r3, [r7, #4]
+ 800432c:	681a      	ldr	r2, [r3, #0]
+ 800432e:	4b30      	ldr	r3, [pc, #192]	; (80043f0 <HAL_ETH_Stop_IT+0xec>)
+ 8004330:	400b      	ands	r3, r1
+ 8004332:	f502 5280 	add.w	r2, r2, #4096	; 0x1000
+ 8004336:	f8c2 3134 	str.w	r3, [r2, #308]	; 0x134
+                                    ETH_DMACIER_FBEE | ETH_DMACIER_AIE | ETH_DMACIER_RBUE));
+
+    /* Disable the DMA transmission */
+    CLEAR_BIT(heth->Instance->DMACTCR, ETH_DMACTCR_ST);
+ 800433a:	687b      	ldr	r3, [r7, #4]
+ 800433c:	681b      	ldr	r3, [r3, #0]
+ 800433e:	f503 5380 	add.w	r3, r3, #4096	; 0x1000
+ 8004342:	f8d3 3104 	ldr.w	r3, [r3, #260]	; 0x104
+ 8004346:	687a      	ldr	r2, [r7, #4]
+ 8004348:	6812      	ldr	r2, [r2, #0]
+ 800434a:	f023 0301 	bic.w	r3, r3, #1
+ 800434e:	f502 5280 	add.w	r2, r2, #4096	; 0x1000
+ 8004352:	f8c2 3104 	str.w	r3, [r2, #260]	; 0x104
+
+    /* Disable the DMA reception */
+    CLEAR_BIT(heth->Instance->DMACRCR, ETH_DMACRCR_SR);
+ 8004356:	687b      	ldr	r3, [r7, #4]
+ 8004358:	681b      	ldr	r3, [r3, #0]
+ 800435a:	f503 5380 	add.w	r3, r3, #4096	; 0x1000
+ 800435e:	f8d3 3108 	ldr.w	r3, [r3, #264]	; 0x108
+ 8004362:	687a      	ldr	r2, [r7, #4]
+ 8004364:	6812      	ldr	r2, [r2, #0]
+ 8004366:	f023 0301 	bic.w	r3, r3, #1
+ 800436a:	f502 5280 	add.w	r2, r2, #4096	; 0x1000
+ 800436e:	f8c2 3108 	str.w	r3, [r2, #264]	; 0x108
+
+    /* Disable the MAC reception */
+    CLEAR_BIT(heth->Instance->MACCR, ETH_MACCR_RE);
+ 8004372:	687b      	ldr	r3, [r7, #4]
+ 8004374:	681b      	ldr	r3, [r3, #0]
+ 8004376:	681a      	ldr	r2, [r3, #0]
+ 8004378:	687b      	ldr	r3, [r7, #4]
+ 800437a:	681b      	ldr	r3, [r3, #0]
+ 800437c:	f022 0201 	bic.w	r2, r2, #1
+ 8004380:	601a      	str	r2, [r3, #0]
+    /* Set the Flush Transmit FIFO bit */
+    SET_BIT(heth->Instance->MTLTQOMR, ETH_MTLTQOMR_FTQ);
+ 8004382:	687b      	ldr	r3, [r7, #4]
+ 8004384:	681b      	ldr	r3, [r3, #0]
+ 8004386:	f8d3 2d00 	ldr.w	r2, [r3, #3328]	; 0xd00
+ 800438a:	687b      	ldr	r3, [r7, #4]
+ 800438c:	681b      	ldr	r3, [r3, #0]
+ 800438e:	f042 0201 	orr.w	r2, r2, #1
+ 8004392:	f8c3 2d00 	str.w	r2, [r3, #3328]	; 0xd00
+
+    /* Disable the MAC transmission */
+    CLEAR_BIT(heth->Instance->MACCR, ETH_MACCR_TE);
+ 8004396:	687b      	ldr	r3, [r7, #4]
+ 8004398:	681b      	ldr	r3, [r3, #0]
+ 800439a:	681a      	ldr	r2, [r3, #0]
+ 800439c:	687b      	ldr	r3, [r7, #4]
+ 800439e:	681b      	ldr	r3, [r3, #0]
+ 80043a0:	f022 0202 	bic.w	r2, r2, #2
+ 80043a4:	601a      	str	r2, [r3, #0]
+
+    /* Clear IOC bit to all Rx descriptors */
+    for (descindex = 0; descindex < (uint32_t)ETH_RX_DESC_CNT; descindex++)
+ 80043a6:	2300      	movs	r3, #0
+ 80043a8:	60fb      	str	r3, [r7, #12]
+ 80043aa:	e00e      	b.n	80043ca <HAL_ETH_Stop_IT+0xc6>
+    {
+      dmarxdesc = (ETH_DMADescTypeDef *)heth->RxDescList.RxDesc[descindex];
+ 80043ac:	687b      	ldr	r3, [r7, #4]
+ 80043ae:	68fa      	ldr	r2, [r7, #12]
+ 80043b0:	3212      	adds	r2, #18
+ 80043b2:	f853 3022 	ldr.w	r3, [r3, r2, lsl #2]
+ 80043b6:	60bb      	str	r3, [r7, #8]
+      CLEAR_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCRF_IOC);
+ 80043b8:	68bb      	ldr	r3, [r7, #8]
+ 80043ba:	68db      	ldr	r3, [r3, #12]
+ 80043bc:	f023 4280 	bic.w	r2, r3, #1073741824	; 0x40000000
+ 80043c0:	68bb      	ldr	r3, [r7, #8]
+ 80043c2:	60da      	str	r2, [r3, #12]
+    for (descindex = 0; descindex < (uint32_t)ETH_RX_DESC_CNT; descindex++)
+ 80043c4:	68fb      	ldr	r3, [r7, #12]
+ 80043c6:	3301      	adds	r3, #1
+ 80043c8:	60fb      	str	r3, [r7, #12]
+ 80043ca:	68fb      	ldr	r3, [r7, #12]
+ 80043cc:	2b03      	cmp	r3, #3
+ 80043ce:	d9ed      	bls.n	80043ac <HAL_ETH_Stop_IT+0xa8>
+    }
+
+    heth->RxDescList.ItMode = 0U;
+ 80043d0:	687b      	ldr	r3, [r7, #4]
+ 80043d2:	2200      	movs	r2, #0
+ 80043d4:	659a      	str	r2, [r3, #88]	; 0x58
+
+    heth->gState = HAL_ETH_STATE_READY;
+ 80043d6:	687b      	ldr	r3, [r7, #4]
+ 80043d8:	2210      	movs	r2, #16
+ 80043da:	f8c3 2084 	str.w	r2, [r3, #132]	; 0x84
+
+    /* Return function status */
+    return HAL_OK;
+ 80043de:	2300      	movs	r3, #0
+ 80043e0:	e000      	b.n	80043e4 <HAL_ETH_Stop_IT+0xe0>
+  }
+  else
+  {
+    return HAL_ERROR;
+ 80043e2:	2301      	movs	r3, #1
+  }
+}
+ 80043e4:	4618      	mov	r0, r3
+ 80043e6:	3714      	adds	r7, #20
+ 80043e8:	46bd      	mov	sp, r7
+ 80043ea:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 80043ee:	4770      	bx	lr
+ 80043f0:	ffff2f3e 	.word	0xffff2f3e
+
+080043f4 <HAL_ETH_Transmit_IT>:
+  *         the configuration information for ETHERNET module
+  * @param  pTxConfig: Hold the configuration of packet to be transmitted
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ETH_Transmit_IT(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig)
+{
+ 80043f4:	b580      	push	{r7, lr}
+ 80043f6:	b082      	sub	sp, #8
+ 80043f8:	af00      	add	r7, sp, #0
+ 80043fa:	6078      	str	r0, [r7, #4]
+ 80043fc:	6039      	str	r1, [r7, #0]
+  if (pTxConfig == NULL)
+ 80043fe:	683b      	ldr	r3, [r7, #0]
+ 8004400:	2b00      	cmp	r3, #0
+ 8004402:	d109      	bne.n	8004418 <HAL_ETH_Transmit_IT+0x24>
+  {
+    heth->ErrorCode |= HAL_ETH_ERROR_PARAM;
+ 8004404:	687b      	ldr	r3, [r7, #4]
+ 8004406:	f8d3 3088 	ldr.w	r3, [r3, #136]	; 0x88
+ 800440a:	f043 0201 	orr.w	r2, r3, #1
+ 800440e:	687b      	ldr	r3, [r7, #4]
+ 8004410:	f8c3 2088 	str.w	r2, [r3, #136]	; 0x88
+    return HAL_ERROR;
+ 8004414:	2301      	movs	r3, #1
+ 8004416:	e03a      	b.n	800448e <HAL_ETH_Transmit_IT+0x9a>
+  }
+
+  if (heth->gState == HAL_ETH_STATE_STARTED)
+ 8004418:	687b      	ldr	r3, [r7, #4]
+ 800441a:	f8d3 3084 	ldr.w	r3, [r3, #132]	; 0x84
+ 800441e:	2b23      	cmp	r3, #35	; 0x23
+ 8004420:	d134      	bne.n	800448c <HAL_ETH_Transmit_IT+0x98>
+  {
+    /* Save the packet pointer to release.  */
+    heth->TxDescList.CurrentPacketAddress = (uint32_t *)pTxConfig->pData;
+ 8004422:	683b      	ldr	r3, [r7, #0]
+ 8004424:	6b5a      	ldr	r2, [r3, #52]	; 0x34
+ 8004426:	687b      	ldr	r3, [r7, #4]
+ 8004428:	63da      	str	r2, [r3, #60]	; 0x3c
+
+    /* Config DMA Tx descriptor by Tx Packet info */
+    if (ETH_Prepare_Tx_Descriptors(heth, pTxConfig, 1) != HAL_ETH_ERROR_NONE)
+ 800442a:	2201      	movs	r2, #1
+ 800442c:	6839      	ldr	r1, [r7, #0]
+ 800442e:	6878      	ldr	r0, [r7, #4]
+ 8004430:	f001 f8ca 	bl	80055c8 <ETH_Prepare_Tx_Descriptors>
+ 8004434:	4603      	mov	r3, r0
+ 8004436:	2b00      	cmp	r3, #0
+ 8004438:	d009      	beq.n	800444e <HAL_ETH_Transmit_IT+0x5a>
+    {
+      heth->ErrorCode |= HAL_ETH_ERROR_BUSY;
+ 800443a:	687b      	ldr	r3, [r7, #4]
+ 800443c:	f8d3 3088 	ldr.w	r3, [r3, #136]	; 0x88
+ 8004440:	f043 0202 	orr.w	r2, r3, #2
+ 8004444:	687b      	ldr	r3, [r7, #4]
+ 8004446:	f8c3 2088 	str.w	r2, [r3, #136]	; 0x88
+      return HAL_ERROR;
+ 800444a:	2301      	movs	r3, #1
+ 800444c:	e01f      	b.n	800448e <HAL_ETH_Transmit_IT+0x9a>
+  __ASM volatile ("dsb 0xF":::"memory");
+ 800444e:	f3bf 8f4f 	dsb	sy
+}
+ 8004452:	bf00      	nop
+
+    /* Ensure completion of descriptor preparation before transmission start */
+    __DSB();
+
+    /* Incr current tx desc index */
+    INCR_TX_DESC_INDEX(heth->TxDescList.CurTxDesc, 1U);
+ 8004454:	687b      	ldr	r3, [r7, #4]
+ 8004456:	6a9b      	ldr	r3, [r3, #40]	; 0x28
+ 8004458:	1c5a      	adds	r2, r3, #1
+ 800445a:	687b      	ldr	r3, [r7, #4]
+ 800445c:	629a      	str	r2, [r3, #40]	; 0x28
+ 800445e:	687b      	ldr	r3, [r7, #4]
+ 8004460:	6a9b      	ldr	r3, [r3, #40]	; 0x28
+ 8004462:	2b03      	cmp	r3, #3
+ 8004464:	d904      	bls.n	8004470 <HAL_ETH_Transmit_IT+0x7c>
+ 8004466:	687b      	ldr	r3, [r7, #4]
+ 8004468:	6a9b      	ldr	r3, [r3, #40]	; 0x28
+ 800446a:	1f1a      	subs	r2, r3, #4
+ 800446c:	687b      	ldr	r3, [r7, #4]
+ 800446e:	629a      	str	r2, [r3, #40]	; 0x28
+
+    /* Start transmission */
+    /* issue a poll command to Tx DMA by writing address of next immediate free descriptor */
+    WRITE_REG(heth->Instance->DMACTDTPR, (uint32_t)(heth->TxDescList.TxDesc[heth->TxDescList.CurTxDesc]));
+ 8004470:	687b      	ldr	r3, [r7, #4]
+ 8004472:	6a99      	ldr	r1, [r3, #40]	; 0x28
+ 8004474:	687b      	ldr	r3, [r7, #4]
+ 8004476:	681a      	ldr	r2, [r3, #0]
+ 8004478:	687b      	ldr	r3, [r7, #4]
+ 800447a:	3106      	adds	r1, #6
+ 800447c:	f853 3021 	ldr.w	r3, [r3, r1, lsl #2]
+ 8004480:	f502 5280 	add.w	r2, r2, #4096	; 0x1000
+ 8004484:	f8c2 3120 	str.w	r3, [r2, #288]	; 0x120
+
+    return HAL_OK;
+ 8004488:	2300      	movs	r3, #0
+ 800448a:	e000      	b.n	800448e <HAL_ETH_Transmit_IT+0x9a>
+
+  }
+  else
+  {
+    return HAL_ERROR;
+ 800448c:	2301      	movs	r3, #1
+  }
+}
+ 800448e:	4618      	mov	r0, r3
+ 8004490:	3708      	adds	r7, #8
+ 8004492:	46bd      	mov	sp, r7
+ 8004494:	bd80      	pop	{r7, pc}
+
+08004496 <HAL_ETH_ReadData>:
+  *         the configuration information for ETHERNET module
+  * @param  pAppBuff: Pointer to an application buffer to receive the packet.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ETH_ReadData(ETH_HandleTypeDef *heth, void **pAppBuff)
+{
+ 8004496:	b580      	push	{r7, lr}
+ 8004498:	b088      	sub	sp, #32
+ 800449a:	af00      	add	r7, sp, #0
+ 800449c:	6078      	str	r0, [r7, #4]
+ 800449e:	6039      	str	r1, [r7, #0]
+  uint32_t descidx;
+  ETH_DMADescTypeDef *dmarxdesc;
+  uint32_t desccnt = 0U;
+ 80044a0:	2300      	movs	r3, #0
+ 80044a2:	617b      	str	r3, [r7, #20]
+  uint32_t desccntmax;
+  uint32_t bufflength;
+  uint8_t rxdataready = 0U;
+ 80044a4:	2300      	movs	r3, #0
+ 80044a6:	73fb      	strb	r3, [r7, #15]
+
+
+  if (pAppBuff == NULL)
+ 80044a8:	683b      	ldr	r3, [r7, #0]
+ 80044aa:	2b00      	cmp	r3, #0
+ 80044ac:	d109      	bne.n	80044c2 <HAL_ETH_ReadData+0x2c>
+  {
+    heth->ErrorCode |= HAL_ETH_ERROR_PARAM;
+ 80044ae:	687b      	ldr	r3, [r7, #4]
+ 80044b0:	f8d3 3088 	ldr.w	r3, [r3, #136]	; 0x88
+ 80044b4:	f043 0201 	orr.w	r2, r3, #1
+ 80044b8:	687b      	ldr	r3, [r7, #4]
+ 80044ba:	f8c3 2088 	str.w	r2, [r3, #136]	; 0x88
+    return HAL_ERROR;
+ 80044be:	2301      	movs	r3, #1
+ 80044c0:	e0a5      	b.n	800460e <HAL_ETH_ReadData+0x178>
+  }
+
+  if (heth->gState != HAL_ETH_STATE_STARTED)
+ 80044c2:	687b      	ldr	r3, [r7, #4]
+ 80044c4:	f8d3 3084 	ldr.w	r3, [r3, #132]	; 0x84
+ 80044c8:	2b23      	cmp	r3, #35	; 0x23
+ 80044ca:	d001      	beq.n	80044d0 <HAL_ETH_ReadData+0x3a>
+  {
+    return HAL_ERROR;
+ 80044cc:	2301      	movs	r3, #1
+ 80044ce:	e09e      	b.n	800460e <HAL_ETH_ReadData+0x178>
+  }
+
+  descidx = heth->RxDescList.RxDescIdx;
+ 80044d0:	687b      	ldr	r3, [r7, #4]
+ 80044d2:	6ddb      	ldr	r3, [r3, #92]	; 0x5c
+ 80044d4:	61fb      	str	r3, [r7, #28]
+  dmarxdesc = (ETH_DMADescTypeDef *)heth->RxDescList.RxDesc[descidx];
+ 80044d6:	687b      	ldr	r3, [r7, #4]
+ 80044d8:	69fa      	ldr	r2, [r7, #28]
+ 80044da:	3212      	adds	r2, #18
+ 80044dc:	f853 3022 	ldr.w	r3, [r3, r2, lsl #2]
+ 80044e0:	61bb      	str	r3, [r7, #24]
+  desccntmax = ETH_RX_DESC_CNT - heth->RxDescList.RxBuildDescCnt;
+ 80044e2:	687b      	ldr	r3, [r7, #4]
+ 80044e4:	6edb      	ldr	r3, [r3, #108]	; 0x6c
+ 80044e6:	f1c3 0304 	rsb	r3, r3, #4
+ 80044ea:	60bb      	str	r3, [r7, #8]
+
+  /* Check if descriptor is not owned by DMA */
+  while ((READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_OWN) == (uint32_t)RESET) && (desccnt < desccntmax)
+ 80044ec:	e067      	b.n	80045be <HAL_ETH_ReadData+0x128>
+         && (rxdataready == 0U))
+  {
+    if (READ_BIT(dmarxdesc->DESC3,  ETH_DMARXNDESCWBF_CTXT)  != (uint32_t)RESET)
+ 80044ee:	69bb      	ldr	r3, [r7, #24]
+ 80044f0:	68db      	ldr	r3, [r3, #12]
+ 80044f2:	f003 4380 	and.w	r3, r3, #1073741824	; 0x40000000
+ 80044f6:	2b00      	cmp	r3, #0
+ 80044f8:	d007      	beq.n	800450a <HAL_ETH_ReadData+0x74>
+    {
+      /* Get timestamp high */
+      heth->RxDescList.TimeStamp.TimeStampHigh = dmarxdesc->DESC1;
+ 80044fa:	69bb      	ldr	r3, [r7, #24]
+ 80044fc:	685a      	ldr	r2, [r3, #4]
+ 80044fe:	687b      	ldr	r3, [r7, #4]
+ 8004500:	679a      	str	r2, [r3, #120]	; 0x78
+      /* Get timestamp low */
+      heth->RxDescList.TimeStamp.TimeStampLow  = dmarxdesc->DESC0;
+ 8004502:	69bb      	ldr	r3, [r7, #24]
+ 8004504:	681a      	ldr	r2, [r3, #0]
+ 8004506:	687b      	ldr	r3, [r7, #4]
+ 8004508:	675a      	str	r2, [r3, #116]	; 0x74
+    }
+    if ((READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_FD) != (uint32_t)RESET) || (heth->RxDescList.pRxStart != NULL))
+ 800450a:	69bb      	ldr	r3, [r7, #24]
+ 800450c:	68db      	ldr	r3, [r3, #12]
+ 800450e:	f003 5300 	and.w	r3, r3, #536870912	; 0x20000000
+ 8004512:	2b00      	cmp	r3, #0
+ 8004514:	d103      	bne.n	800451e <HAL_ETH_ReadData+0x88>
+ 8004516:	687b      	ldr	r3, [r7, #4]
+ 8004518:	6fdb      	ldr	r3, [r3, #124]	; 0x7c
+ 800451a:	2b00      	cmp	r3, #0
+ 800451c:	d03d      	beq.n	800459a <HAL_ETH_ReadData+0x104>
+    {
+      /* Check if first descriptor */
+      if (READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_FD) != (uint32_t)RESET)
+ 800451e:	69bb      	ldr	r3, [r7, #24]
+ 8004520:	68db      	ldr	r3, [r3, #12]
+ 8004522:	f003 5300 	and.w	r3, r3, #536870912	; 0x20000000
+ 8004526:	2b00      	cmp	r3, #0
+ 8004528:	d005      	beq.n	8004536 <HAL_ETH_ReadData+0xa0>
+      {
+        heth->RxDescList.RxDescCnt = 0;
+ 800452a:	687b      	ldr	r3, [r7, #4]
+ 800452c:	2200      	movs	r2, #0
+ 800452e:	661a      	str	r2, [r3, #96]	; 0x60
+        heth->RxDescList.RxDataLength = 0;
+ 8004530:	687b      	ldr	r3, [r7, #4]
+ 8004532:	2200      	movs	r2, #0
+ 8004534:	665a      	str	r2, [r3, #100]	; 0x64
+      }
+
+      /* Check if last descriptor */
+      bufflength = heth->Init.RxBuffLen;
+ 8004536:	687b      	ldr	r3, [r7, #4]
+ 8004538:	695b      	ldr	r3, [r3, #20]
+ 800453a:	613b      	str	r3, [r7, #16]
+      if (READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_LD) != (uint32_t)RESET)
+ 800453c:	69bb      	ldr	r3, [r7, #24]
+ 800453e:	68db      	ldr	r3, [r3, #12]
+ 8004540:	f003 5380 	and.w	r3, r3, #268435456	; 0x10000000
+ 8004544:	2b00      	cmp	r3, #0
+ 8004546:	d00d      	beq.n	8004564 <HAL_ETH_ReadData+0xce>
+      {
+        bufflength = READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_PL) - heth->RxDescList.RxDataLength;
+ 8004548:	69bb      	ldr	r3, [r7, #24]
+ 800454a:	68db      	ldr	r3, [r3, #12]
+ 800454c:	f3c3 020e 	ubfx	r2, r3, #0, #15
+ 8004550:	687b      	ldr	r3, [r7, #4]
+ 8004552:	6e5b      	ldr	r3, [r3, #100]	; 0x64
+ 8004554:	1ad3      	subs	r3, r2, r3
+ 8004556:	613b      	str	r3, [r7, #16]
+
+        /* Save Last descriptor index */
+        heth->RxDescList.pRxLastRxDesc = dmarxdesc->DESC3;
+ 8004558:	69bb      	ldr	r3, [r7, #24]
+ 800455a:	68da      	ldr	r2, [r3, #12]
+ 800455c:	687b      	ldr	r3, [r7, #4]
+ 800455e:	671a      	str	r2, [r3, #112]	; 0x70
+
+        /* Packet ready */
+        rxdataready = 1;
+ 8004560:	2301      	movs	r3, #1
+ 8004562:	73fb      	strb	r3, [r7, #15]
+      /*Call registered Link callback*/
+      heth->rxLinkCallback(&heth->RxDescList.pRxStart, &heth->RxDescList.pRxEnd,
+                           (uint8_t *)dmarxdesc->BackupAddr0, bufflength);
+#else
+      /* Link callback */
+      HAL_ETH_RxLinkCallback(&heth->RxDescList.pRxStart, &heth->RxDescList.pRxEnd,
+ 8004564:	687b      	ldr	r3, [r7, #4]
+ 8004566:	f103 007c 	add.w	r0, r3, #124	; 0x7c
+ 800456a:	687b      	ldr	r3, [r7, #4]
+ 800456c:	f103 0180 	add.w	r1, r3, #128	; 0x80
+                             (uint8_t *)dmarxdesc->BackupAddr0, (uint16_t) bufflength);
+ 8004570:	69bb      	ldr	r3, [r7, #24]
+ 8004572:	691b      	ldr	r3, [r3, #16]
+      HAL_ETH_RxLinkCallback(&heth->RxDescList.pRxStart, &heth->RxDescList.pRxEnd,
+ 8004574:	461a      	mov	r2, r3
+ 8004576:	693b      	ldr	r3, [r7, #16]
+ 8004578:	b29b      	uxth	r3, r3
+ 800457a:	f00b fd99 	bl	80100b0 <HAL_ETH_RxLinkCallback>
+#endif  /* USE_HAL_ETH_REGISTER_CALLBACKS */
+      heth->RxDescList.RxDescCnt++;
+ 800457e:	687b      	ldr	r3, [r7, #4]
+ 8004580:	6e1b      	ldr	r3, [r3, #96]	; 0x60
+ 8004582:	1c5a      	adds	r2, r3, #1
+ 8004584:	687b      	ldr	r3, [r7, #4]
+ 8004586:	661a      	str	r2, [r3, #96]	; 0x60
+      heth->RxDescList.RxDataLength += bufflength;
+ 8004588:	687b      	ldr	r3, [r7, #4]
+ 800458a:	6e5a      	ldr	r2, [r3, #100]	; 0x64
+ 800458c:	693b      	ldr	r3, [r7, #16]
+ 800458e:	441a      	add	r2, r3
+ 8004590:	687b      	ldr	r3, [r7, #4]
+ 8004592:	665a      	str	r2, [r3, #100]	; 0x64
+
+      /* Clear buffer pointer */
+      dmarxdesc->BackupAddr0 = 0;
+ 8004594:	69bb      	ldr	r3, [r7, #24]
+ 8004596:	2200      	movs	r2, #0
+ 8004598:	611a      	str	r2, [r3, #16]
+    }
+
+    /* Increment current rx descriptor index */
+    INCR_RX_DESC_INDEX(descidx, 1U);
+ 800459a:	69fb      	ldr	r3, [r7, #28]
+ 800459c:	3301      	adds	r3, #1
+ 800459e:	61fb      	str	r3, [r7, #28]
+ 80045a0:	69fb      	ldr	r3, [r7, #28]
+ 80045a2:	2b03      	cmp	r3, #3
+ 80045a4:	d902      	bls.n	80045ac <HAL_ETH_ReadData+0x116>
+ 80045a6:	69fb      	ldr	r3, [r7, #28]
+ 80045a8:	3b04      	subs	r3, #4
+ 80045aa:	61fb      	str	r3, [r7, #28]
+    /* Get current descriptor address */
+    dmarxdesc = (ETH_DMADescTypeDef *)heth->RxDescList.RxDesc[descidx];
+ 80045ac:	687b      	ldr	r3, [r7, #4]
+ 80045ae:	69fa      	ldr	r2, [r7, #28]
+ 80045b0:	3212      	adds	r2, #18
+ 80045b2:	f853 3022 	ldr.w	r3, [r3, r2, lsl #2]
+ 80045b6:	61bb      	str	r3, [r7, #24]
+    desccnt++;
+ 80045b8:	697b      	ldr	r3, [r7, #20]
+ 80045ba:	3301      	adds	r3, #1
+ 80045bc:	617b      	str	r3, [r7, #20]
+  while ((READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_OWN) == (uint32_t)RESET) && (desccnt < desccntmax)
+ 80045be:	69bb      	ldr	r3, [r7, #24]
+ 80045c0:	68db      	ldr	r3, [r3, #12]
+         && (rxdataready == 0U))
+ 80045c2:	2b00      	cmp	r3, #0
+ 80045c4:	db06      	blt.n	80045d4 <HAL_ETH_ReadData+0x13e>
+  while ((READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_OWN) == (uint32_t)RESET) && (desccnt < desccntmax)
+ 80045c6:	697a      	ldr	r2, [r7, #20]
+ 80045c8:	68bb      	ldr	r3, [r7, #8]
+ 80045ca:	429a      	cmp	r2, r3
+ 80045cc:	d202      	bcs.n	80045d4 <HAL_ETH_ReadData+0x13e>
+         && (rxdataready == 0U))
+ 80045ce:	7bfb      	ldrb	r3, [r7, #15]
+ 80045d0:	2b00      	cmp	r3, #0
+ 80045d2:	d08c      	beq.n	80044ee <HAL_ETH_ReadData+0x58>
+  }
+
+  heth->RxDescList.RxBuildDescCnt += desccnt;
+ 80045d4:	687b      	ldr	r3, [r7, #4]
+ 80045d6:	6eda      	ldr	r2, [r3, #108]	; 0x6c
+ 80045d8:	697b      	ldr	r3, [r7, #20]
+ 80045da:	441a      	add	r2, r3
+ 80045dc:	687b      	ldr	r3, [r7, #4]
+ 80045de:	66da      	str	r2, [r3, #108]	; 0x6c
+  if ((heth->RxDescList.RxBuildDescCnt) != 0U)
+ 80045e0:	687b      	ldr	r3, [r7, #4]
+ 80045e2:	6edb      	ldr	r3, [r3, #108]	; 0x6c
+ 80045e4:	2b00      	cmp	r3, #0
+ 80045e6:	d002      	beq.n	80045ee <HAL_ETH_ReadData+0x158>
+  {
+    /* Update Descriptors */
+    ETH_UpdateDescriptor(heth);
+ 80045e8:	6878      	ldr	r0, [r7, #4]
+ 80045ea:	f000 f814 	bl	8004616 <ETH_UpdateDescriptor>
+  }
+
+  heth->RxDescList.RxDescIdx = descidx;
+ 80045ee:	687b      	ldr	r3, [r7, #4]
+ 80045f0:	69fa      	ldr	r2, [r7, #28]
+ 80045f2:	65da      	str	r2, [r3, #92]	; 0x5c
+
+  if (rxdataready == 1U)
+ 80045f4:	7bfb      	ldrb	r3, [r7, #15]
+ 80045f6:	2b01      	cmp	r3, #1
+ 80045f8:	d108      	bne.n	800460c <HAL_ETH_ReadData+0x176>
+  {
+    /* Return received packet */
+    *pAppBuff = heth->RxDescList.pRxStart;
+ 80045fa:	687b      	ldr	r3, [r7, #4]
+ 80045fc:	6fda      	ldr	r2, [r3, #124]	; 0x7c
+ 80045fe:	683b      	ldr	r3, [r7, #0]
+ 8004600:	601a      	str	r2, [r3, #0]
+    /* Reset first element */
+    heth->RxDescList.pRxStart = NULL;
+ 8004602:	687b      	ldr	r3, [r7, #4]
+ 8004604:	2200      	movs	r2, #0
+ 8004606:	67da      	str	r2, [r3, #124]	; 0x7c
+
+    return HAL_OK;
+ 8004608:	2300      	movs	r3, #0
+ 800460a:	e000      	b.n	800460e <HAL_ETH_ReadData+0x178>
+  }
+
+  /* Packet not ready */
+  return HAL_ERROR;
+ 800460c:	2301      	movs	r3, #1
+}
+ 800460e:	4618      	mov	r0, r3
+ 8004610:	3720      	adds	r7, #32
+ 8004612:	46bd      	mov	sp, r7
+ 8004614:	bd80      	pop	{r7, pc}
+
+08004616 <ETH_UpdateDescriptor>:
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @retval HAL status
+  */
+static void ETH_UpdateDescriptor(ETH_HandleTypeDef *heth)
+{
+ 8004616:	b580      	push	{r7, lr}
+ 8004618:	b088      	sub	sp, #32
+ 800461a:	af00      	add	r7, sp, #0
+ 800461c:	6078      	str	r0, [r7, #4]
+  uint32_t descidx;
+  uint32_t desccount;
+  ETH_DMADescTypeDef *dmarxdesc;
+  uint8_t *buff = NULL;
+ 800461e:	2300      	movs	r3, #0
+ 8004620:	60fb      	str	r3, [r7, #12]
+  uint8_t allocStatus = 1U;
+ 8004622:	2301      	movs	r3, #1
+ 8004624:	74fb      	strb	r3, [r7, #19]
+
+  descidx = heth->RxDescList.RxBuildDescIdx;
+ 8004626:	687b      	ldr	r3, [r7, #4]
+ 8004628:	6e9b      	ldr	r3, [r3, #104]	; 0x68
+ 800462a:	61fb      	str	r3, [r7, #28]
+  dmarxdesc = (ETH_DMADescTypeDef *)heth->RxDescList.RxDesc[descidx];
+ 800462c:	687b      	ldr	r3, [r7, #4]
+ 800462e:	69fa      	ldr	r2, [r7, #28]
+ 8004630:	3212      	adds	r2, #18
+ 8004632:	f853 3022 	ldr.w	r3, [r3, r2, lsl #2]
+ 8004636:	617b      	str	r3, [r7, #20]
+  desccount = heth->RxDescList.RxBuildDescCnt;
+ 8004638:	687b      	ldr	r3, [r7, #4]
+ 800463a:	6edb      	ldr	r3, [r3, #108]	; 0x6c
+ 800463c:	61bb      	str	r3, [r7, #24]
+
+  while ((desccount > 0U) && (allocStatus != 0U))
+ 800463e:	e03b      	b.n	80046b8 <ETH_UpdateDescriptor+0xa2>
+  {
+    /* Check if a buffer's attached the descriptor */
+    if (READ_REG(dmarxdesc->BackupAddr0) == 0U)
+ 8004640:	697b      	ldr	r3, [r7, #20]
+ 8004642:	691b      	ldr	r3, [r3, #16]
+ 8004644:	2b00      	cmp	r3, #0
+ 8004646:	d112      	bne.n	800466e <ETH_UpdateDescriptor+0x58>
+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
+      /*Call registered Allocate callback*/
+      heth->rxAllocateCallback(&buff);
+#else
+      /* Allocate callback */
+      HAL_ETH_RxAllocateCallback(&buff);
+ 8004648:	f107 030c 	add.w	r3, r7, #12
+ 800464c:	4618      	mov	r0, r3
+ 800464e:	f00b fcff 	bl	8010050 <HAL_ETH_RxAllocateCallback>
+#endif  /* USE_HAL_ETH_REGISTER_CALLBACKS */
+      if (buff == NULL)
+ 8004652:	68fb      	ldr	r3, [r7, #12]
+ 8004654:	2b00      	cmp	r3, #0
+ 8004656:	d102      	bne.n	800465e <ETH_UpdateDescriptor+0x48>
+      {
+        allocStatus = 0U;
+ 8004658:	2300      	movs	r3, #0
+ 800465a:	74fb      	strb	r3, [r7, #19]
+ 800465c:	e007      	b.n	800466e <ETH_UpdateDescriptor+0x58>
+      }
+      else
+      {
+        WRITE_REG(dmarxdesc->BackupAddr0, (uint32_t)buff);
+ 800465e:	68fb      	ldr	r3, [r7, #12]
+ 8004660:	461a      	mov	r2, r3
+ 8004662:	697b      	ldr	r3, [r7, #20]
+ 8004664:	611a      	str	r2, [r3, #16]
+        WRITE_REG(dmarxdesc->DESC0, (uint32_t)buff);
+ 8004666:	68fb      	ldr	r3, [r7, #12]
+ 8004668:	461a      	mov	r2, r3
+ 800466a:	697b      	ldr	r3, [r7, #20]
+ 800466c:	601a      	str	r2, [r3, #0]
+      }
+    }
+
+    if (allocStatus != 0U)
+ 800466e:	7cfb      	ldrb	r3, [r7, #19]
+ 8004670:	2b00      	cmp	r3, #0
+ 8004672:	d021      	beq.n	80046b8 <ETH_UpdateDescriptor+0xa2>
+  __ASM volatile ("dmb 0xF":::"memory");
+ 8004674:	f3bf 8f5f 	dmb	sy
+}
+ 8004678:	bf00      	nop
+    {
+      /* Ensure rest of descriptor is written to RAM before the OWN bit */
+      __DMB();
+
+      if (heth->RxDescList.ItMode != 0U)
+ 800467a:	687b      	ldr	r3, [r7, #4]
+ 800467c:	6d9b      	ldr	r3, [r3, #88]	; 0x58
+ 800467e:	2b00      	cmp	r3, #0
+ 8004680:	d004      	beq.n	800468c <ETH_UpdateDescriptor+0x76>
+      {
+        WRITE_REG(dmarxdesc->DESC3, ETH_DMARXNDESCRF_OWN | ETH_DMARXNDESCRF_BUF1V | ETH_DMARXNDESCRF_IOC);
+ 8004682:	697b      	ldr	r3, [r7, #20]
+ 8004684:	f04f 4241 	mov.w	r2, #3238002688	; 0xc1000000
+ 8004688:	60da      	str	r2, [r3, #12]
+ 800468a:	e003      	b.n	8004694 <ETH_UpdateDescriptor+0x7e>
+      }
+      else
+      {
+        WRITE_REG(dmarxdesc->DESC3, ETH_DMARXNDESCRF_OWN | ETH_DMARXNDESCRF_BUF1V);
+ 800468c:	697b      	ldr	r3, [r7, #20]
+ 800468e:	f04f 4201 	mov.w	r2, #2164260864	; 0x81000000
+ 8004692:	60da      	str	r2, [r3, #12]
+      }
+
+      /* Increment current rx descriptor index */
+      INCR_RX_DESC_INDEX(descidx, 1U);
+ 8004694:	69fb      	ldr	r3, [r7, #28]
+ 8004696:	3301      	adds	r3, #1
+ 8004698:	61fb      	str	r3, [r7, #28]
+ 800469a:	69fb      	ldr	r3, [r7, #28]
+ 800469c:	2b03      	cmp	r3, #3
+ 800469e:	d902      	bls.n	80046a6 <ETH_UpdateDescriptor+0x90>
+ 80046a0:	69fb      	ldr	r3, [r7, #28]
+ 80046a2:	3b04      	subs	r3, #4
+ 80046a4:	61fb      	str	r3, [r7, #28]
+      /* Get current descriptor address */
+      dmarxdesc = (ETH_DMADescTypeDef *)heth->RxDescList.RxDesc[descidx];
+ 80046a6:	687b      	ldr	r3, [r7, #4]
+ 80046a8:	69fa      	ldr	r2, [r7, #28]
+ 80046aa:	3212      	adds	r2, #18
+ 80046ac:	f853 3022 	ldr.w	r3, [r3, r2, lsl #2]
+ 80046b0:	617b      	str	r3, [r7, #20]
+      desccount--;
+ 80046b2:	69bb      	ldr	r3, [r7, #24]
+ 80046b4:	3b01      	subs	r3, #1
+ 80046b6:	61bb      	str	r3, [r7, #24]
+  while ((desccount > 0U) && (allocStatus != 0U))
+ 80046b8:	69bb      	ldr	r3, [r7, #24]
+ 80046ba:	2b00      	cmp	r3, #0
+ 80046bc:	d002      	beq.n	80046c4 <ETH_UpdateDescriptor+0xae>
+ 80046be:	7cfb      	ldrb	r3, [r7, #19]
+ 80046c0:	2b00      	cmp	r3, #0
+ 80046c2:	d1bd      	bne.n	8004640 <ETH_UpdateDescriptor+0x2a>
+    }
+  }
+
+  if (heth->RxDescList.RxBuildDescCnt != desccount)
+ 80046c4:	687b      	ldr	r3, [r7, #4]
+ 80046c6:	6edb      	ldr	r3, [r3, #108]	; 0x6c
+ 80046c8:	69ba      	ldr	r2, [r7, #24]
+ 80046ca:	429a      	cmp	r2, r3
+ 80046cc:	d00d      	beq.n	80046ea <ETH_UpdateDescriptor+0xd4>
+  {
+    /* Set the Tail pointer address */
+    WRITE_REG(heth->Instance->DMACRDTPR, 0);
+ 80046ce:	687b      	ldr	r3, [r7, #4]
+ 80046d0:	681b      	ldr	r3, [r3, #0]
+ 80046d2:	f503 5380 	add.w	r3, r3, #4096	; 0x1000
+ 80046d6:	461a      	mov	r2, r3
+ 80046d8:	2300      	movs	r3, #0
+ 80046da:	f8c2 3128 	str.w	r3, [r2, #296]	; 0x128
+
+    heth->RxDescList.RxBuildDescIdx = descidx;
+ 80046de:	687b      	ldr	r3, [r7, #4]
+ 80046e0:	69fa      	ldr	r2, [r7, #28]
+ 80046e2:	669a      	str	r2, [r3, #104]	; 0x68
+    heth->RxDescList.RxBuildDescCnt = desccount;
+ 80046e4:	687b      	ldr	r3, [r7, #4]
+ 80046e6:	69ba      	ldr	r2, [r7, #24]
+ 80046e8:	66da      	str	r2, [r3, #108]	; 0x6c
+  }
+}
+ 80046ea:	bf00      	nop
+ 80046ec:	3720      	adds	r7, #32
+ 80046ee:	46bd      	mov	sp, r7
+ 80046f0:	bd80      	pop	{r7, pc}
+
+080046f2 <HAL_ETH_ReleaseTxPacket>:
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ETH_ReleaseTxPacket(ETH_HandleTypeDef *heth)
+{
+ 80046f2:	b580      	push	{r7, lr}
+ 80046f4:	b086      	sub	sp, #24
+ 80046f6:	af00      	add	r7, sp, #0
+ 80046f8:	6078      	str	r0, [r7, #4]
+  ETH_TxDescListTypeDef *dmatxdesclist = &heth->TxDescList;
+ 80046fa:	687b      	ldr	r3, [r7, #4]
+ 80046fc:	3318      	adds	r3, #24
+ 80046fe:	60bb      	str	r3, [r7, #8]
+  uint32_t numOfBuf =  dmatxdesclist->BuffersInUse;
+ 8004700:	68bb      	ldr	r3, [r7, #8]
+ 8004702:	6a9b      	ldr	r3, [r3, #40]	; 0x28
+ 8004704:	617b      	str	r3, [r7, #20]
+  uint32_t idx =       dmatxdesclist->releaseIndex;
+ 8004706:	68bb      	ldr	r3, [r7, #8]
+ 8004708:	6adb      	ldr	r3, [r3, #44]	; 0x2c
+ 800470a:	613b      	str	r3, [r7, #16]
+  uint8_t pktTxStatus = 1U;
+ 800470c:	2301      	movs	r3, #1
+ 800470e:	73fb      	strb	r3, [r7, #15]
+#ifdef HAL_ETH_USE_PTP
+  ETH_TimeStampTypeDef *timestamp = &heth->TxTimestamp;
+#endif /* HAL_ETH_USE_PTP */
+
+  /* Loop through buffers in use.  */
+  while ((numOfBuf != 0U) && (pktTxStatus != 0U))
+ 8004710:	e03f      	b.n	8004792 <HAL_ETH_ReleaseTxPacket+0xa0>
+  {
+    pktInUse = 1U;
+ 8004712:	2301      	movs	r3, #1
+ 8004714:	73bb      	strb	r3, [r7, #14]
+    numOfBuf--;
+ 8004716:	697b      	ldr	r3, [r7, #20]
+ 8004718:	3b01      	subs	r3, #1
+ 800471a:	617b      	str	r3, [r7, #20]
+    /* If no packet, just examine the next packet.  */
+    if (dmatxdesclist->PacketAddress[idx] == NULL)
+ 800471c:	68ba      	ldr	r2, [r7, #8]
+ 800471e:	693b      	ldr	r3, [r7, #16]
+ 8004720:	3304      	adds	r3, #4
+ 8004722:	009b      	lsls	r3, r3, #2
+ 8004724:	4413      	add	r3, r2
+ 8004726:	685b      	ldr	r3, [r3, #4]
+ 8004728:	2b00      	cmp	r3, #0
+ 800472a:	d106      	bne.n	800473a <HAL_ETH_ReleaseTxPacket+0x48>
+    {
+      /* No packet in use, skip to next.  */
+      idx = (idx + 1U) & (ETH_TX_DESC_CNT - 1U);
+ 800472c:	693b      	ldr	r3, [r7, #16]
+ 800472e:	3301      	adds	r3, #1
+ 8004730:	f003 0303 	and.w	r3, r3, #3
+ 8004734:	613b      	str	r3, [r7, #16]
+      pktInUse = 0U;
+ 8004736:	2300      	movs	r3, #0
+ 8004738:	73bb      	strb	r3, [r7, #14]
+    }
+
+    if (pktInUse != 0U)
+ 800473a:	7bbb      	ldrb	r3, [r7, #14]
+ 800473c:	2b00      	cmp	r3, #0
+ 800473e:	d028      	beq.n	8004792 <HAL_ETH_ReleaseTxPacket+0xa0>
+    {
+      /* Determine if the packet has been transmitted.  */
+      if ((heth->Init.TxDesc[idx].DESC3 & ETH_DMATXNDESCRF_OWN) == 0U)
+ 8004740:	687b      	ldr	r3, [r7, #4]
+ 8004742:	68d9      	ldr	r1, [r3, #12]
+ 8004744:	693a      	ldr	r2, [r7, #16]
+ 8004746:	4613      	mov	r3, r2
+ 8004748:	005b      	lsls	r3, r3, #1
+ 800474a:	4413      	add	r3, r2
+ 800474c:	00db      	lsls	r3, r3, #3
+ 800474e:	440b      	add	r3, r1
+ 8004750:	68db      	ldr	r3, [r3, #12]
+ 8004752:	2b00      	cmp	r3, #0
+ 8004754:	db1b      	blt.n	800478e <HAL_ETH_ReleaseTxPacket+0x9c>
+#ifdef HAL_ETH_USE_PTP
+        /* Handle Ptp  */
+        HAL_ETH_TxPtpCallback(dmatxdesclist->PacketAddress[idx], timestamp);
+#endif  /* HAL_ETH_USE_PTP */
+        /* Release the packet.  */
+        HAL_ETH_TxFreeCallback(dmatxdesclist->PacketAddress[idx]);
+ 8004756:	68ba      	ldr	r2, [r7, #8]
+ 8004758:	693b      	ldr	r3, [r7, #16]
+ 800475a:	3304      	adds	r3, #4
+ 800475c:	009b      	lsls	r3, r3, #2
+ 800475e:	4413      	add	r3, r2
+ 8004760:	685b      	ldr	r3, [r3, #4]
+ 8004762:	4618      	mov	r0, r3
+ 8004764:	f00b fd0c 	bl	8010180 <HAL_ETH_TxFreeCallback>
+#endif  /* USE_HAL_ETH_REGISTER_CALLBACKS */
+
+        /* Clear the entry in the in-use array.  */
+        dmatxdesclist->PacketAddress[idx] = NULL;
+ 8004768:	68ba      	ldr	r2, [r7, #8]
+ 800476a:	693b      	ldr	r3, [r7, #16]
+ 800476c:	3304      	adds	r3, #4
+ 800476e:	009b      	lsls	r3, r3, #2
+ 8004770:	4413      	add	r3, r2
+ 8004772:	2200      	movs	r2, #0
+ 8004774:	605a      	str	r2, [r3, #4]
+
+        /* Update the transmit relesae index and number of buffers in use.  */
+        idx = (idx + 1U) & (ETH_TX_DESC_CNT - 1U);
+ 8004776:	693b      	ldr	r3, [r7, #16]
+ 8004778:	3301      	adds	r3, #1
+ 800477a:	f003 0303 	and.w	r3, r3, #3
+ 800477e:	613b      	str	r3, [r7, #16]
+        dmatxdesclist->BuffersInUse = numOfBuf;
+ 8004780:	68bb      	ldr	r3, [r7, #8]
+ 8004782:	697a      	ldr	r2, [r7, #20]
+ 8004784:	629a      	str	r2, [r3, #40]	; 0x28
+        dmatxdesclist->releaseIndex = idx;
+ 8004786:	68bb      	ldr	r3, [r7, #8]
+ 8004788:	693a      	ldr	r2, [r7, #16]
+ 800478a:	62da      	str	r2, [r3, #44]	; 0x2c
+ 800478c:	e001      	b.n	8004792 <HAL_ETH_ReleaseTxPacket+0xa0>
+      }
+      else
+      {
+        /* Get out of the loop!  */
+        pktTxStatus = 0U;
+ 800478e:	2300      	movs	r3, #0
+ 8004790:	73fb      	strb	r3, [r7, #15]
+  while ((numOfBuf != 0U) && (pktTxStatus != 0U))
+ 8004792:	697b      	ldr	r3, [r7, #20]
+ 8004794:	2b00      	cmp	r3, #0
+ 8004796:	d002      	beq.n	800479e <HAL_ETH_ReleaseTxPacket+0xac>
+ 8004798:	7bfb      	ldrb	r3, [r7, #15]
+ 800479a:	2b00      	cmp	r3, #0
+ 800479c:	d1b9      	bne.n	8004712 <HAL_ETH_ReleaseTxPacket+0x20>
+      }
+    }
+  }
+  return HAL_OK;
+ 800479e:	2300      	movs	r3, #0
+}
+ 80047a0:	4618      	mov	r0, r3
+ 80047a2:	3718      	adds	r7, #24
+ 80047a4:	46bd      	mov	sp, r7
+ 80047a6:	bd80      	pop	{r7, pc}
+
+080047a8 <HAL_ETH_IRQHandler>:
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @retval HAL status
+  */
+void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth)
+{
+ 80047a8:	b580      	push	{r7, lr}
+ 80047aa:	b084      	sub	sp, #16
+ 80047ac:	af00      	add	r7, sp, #0
+ 80047ae:	6078      	str	r0, [r7, #4]
+  uint32_t macirqenable;
+  /* Packet received */
+  if (__HAL_ETH_DMA_GET_IT(heth, ETH_DMACSR_RI))
+ 80047b0:	687b      	ldr	r3, [r7, #4]
+ 80047b2:	681b      	ldr	r3, [r3, #0]
+ 80047b4:	f503 5380 	add.w	r3, r3, #4096	; 0x1000
+ 80047b8:	f8d3 3160 	ldr.w	r3, [r3, #352]	; 0x160
+ 80047bc:	f003 0340 	and.w	r3, r3, #64	; 0x40
+ 80047c0:	2b40      	cmp	r3, #64	; 0x40
+ 80047c2:	d115      	bne.n	80047f0 <HAL_ETH_IRQHandler+0x48>
+  {
+    if (__HAL_ETH_DMA_GET_IT_SOURCE(heth, ETH_DMACIER_RIE))
+ 80047c4:	687b      	ldr	r3, [r7, #4]
+ 80047c6:	681b      	ldr	r3, [r3, #0]
+ 80047c8:	f503 5380 	add.w	r3, r3, #4096	; 0x1000
+ 80047cc:	f8d3 3134 	ldr.w	r3, [r3, #308]	; 0x134
+ 80047d0:	f003 0340 	and.w	r3, r3, #64	; 0x40
+ 80047d4:	2b40      	cmp	r3, #64	; 0x40
+ 80047d6:	d10b      	bne.n	80047f0 <HAL_ETH_IRQHandler+0x48>
+    {
+      /* Clear the Eth DMA Rx IT pending bits */
+      __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMACSR_RI | ETH_DMACSR_NIS);
+ 80047d8:	687b      	ldr	r3, [r7, #4]
+ 80047da:	681b      	ldr	r3, [r3, #0]
+ 80047dc:	f503 5380 	add.w	r3, r3, #4096	; 0x1000
+ 80047e0:	461a      	mov	r2, r3
+ 80047e2:	f248 0340 	movw	r3, #32832	; 0x8040
+ 80047e6:	f8c2 3160 	str.w	r3, [r2, #352]	; 0x160
+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
+      /*Call registered Receive complete callback*/
+      heth->RxCpltCallback(heth);
+#else
+      /* Receive complete callback */
+      HAL_ETH_RxCpltCallback(heth);
+ 80047ea:	6878      	ldr	r0, [r7, #4]
+ 80047ec:	f00a ffea 	bl	800f7c4 <HAL_ETH_RxCpltCallback>
+#endif  /* USE_HAL_ETH_REGISTER_CALLBACKS */
+    }
+  }
+
+  /* Packet transmitted */
+  if (__HAL_ETH_DMA_GET_IT(heth, ETH_DMACSR_TI))
+ 80047f0:	687b      	ldr	r3, [r7, #4]
+ 80047f2:	681b      	ldr	r3, [r3, #0]
+ 80047f4:	f503 5380 	add.w	r3, r3, #4096	; 0x1000
+ 80047f8:	f8d3 3160 	ldr.w	r3, [r3, #352]	; 0x160
+ 80047fc:	f003 0301 	and.w	r3, r3, #1
+ 8004800:	2b01      	cmp	r3, #1
+ 8004802:	d115      	bne.n	8004830 <HAL_ETH_IRQHandler+0x88>
+  {
+    if (__HAL_ETH_DMA_GET_IT_SOURCE(heth, ETH_DMACIER_TIE))
+ 8004804:	687b      	ldr	r3, [r7, #4]
+ 8004806:	681b      	ldr	r3, [r3, #0]
+ 8004808:	f503 5380 	add.w	r3, r3, #4096	; 0x1000
+ 800480c:	f8d3 3134 	ldr.w	r3, [r3, #308]	; 0x134
+ 8004810:	f003 0301 	and.w	r3, r3, #1
+ 8004814:	2b01      	cmp	r3, #1
+ 8004816:	d10b      	bne.n	8004830 <HAL_ETH_IRQHandler+0x88>
+    {
+      /* Clear the Eth DMA Tx IT pending bits */
+      __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMACSR_TI | ETH_DMACSR_NIS);
+ 8004818:	687b      	ldr	r3, [r7, #4]
+ 800481a:	681b      	ldr	r3, [r3, #0]
+ 800481c:	f503 5380 	add.w	r3, r3, #4096	; 0x1000
+ 8004820:	461a      	mov	r2, r3
+ 8004822:	f248 0301 	movw	r3, #32769	; 0x8001
+ 8004826:	f8c2 3160 	str.w	r3, [r2, #352]	; 0x160
+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
+      /*Call registered Transmit complete callback*/
+      heth->TxCpltCallback(heth);
+#else
+      /* Transfer complete callback */
+      HAL_ETH_TxCpltCallback(heth);
+ 800482a:	6878      	ldr	r0, [r7, #4]
+ 800482c:	f00a ffda 	bl	800f7e4 <HAL_ETH_TxCpltCallback>
+    }
+  }
+
+
+  /* ETH DMA Error */
+  if (__HAL_ETH_DMA_GET_IT(heth, ETH_DMACSR_AIS))
+ 8004830:	687b      	ldr	r3, [r7, #4]
+ 8004832:	681b      	ldr	r3, [r3, #0]
+ 8004834:	f503 5380 	add.w	r3, r3, #4096	; 0x1000
+ 8004838:	f8d3 3160 	ldr.w	r3, [r3, #352]	; 0x160
+ 800483c:	f403 4380 	and.w	r3, r3, #16384	; 0x4000
+ 8004840:	f5b3 4f80 	cmp.w	r3, #16384	; 0x4000
+ 8004844:	d153      	bne.n	80048ee <HAL_ETH_IRQHandler+0x146>
+  {
+    if (__HAL_ETH_DMA_GET_IT_SOURCE(heth, ETH_DMACIER_AIE))
+ 8004846:	687b      	ldr	r3, [r7, #4]
+ 8004848:	681b      	ldr	r3, [r3, #0]
+ 800484a:	f503 5380 	add.w	r3, r3, #4096	; 0x1000
+ 800484e:	f8d3 3134 	ldr.w	r3, [r3, #308]	; 0x134
+ 8004852:	f403 4380 	and.w	r3, r3, #16384	; 0x4000
+ 8004856:	f5b3 4f80 	cmp.w	r3, #16384	; 0x4000
+ 800485a:	d148      	bne.n	80048ee <HAL_ETH_IRQHandler+0x146>
+    {
+      heth->ErrorCode |= HAL_ETH_ERROR_DMA;
+ 800485c:	687b      	ldr	r3, [r7, #4]
+ 800485e:	f8d3 3088 	ldr.w	r3, [r3, #136]	; 0x88
+ 8004862:	f043 0208 	orr.w	r2, r3, #8
+ 8004866:	687b      	ldr	r3, [r7, #4]
+ 8004868:	f8c3 2088 	str.w	r2, [r3, #136]	; 0x88
+
+      /* if fatal bus error occurred */
+      if (__HAL_ETH_DMA_GET_IT(heth, ETH_DMACSR_FBE))
+ 800486c:	687b      	ldr	r3, [r7, #4]
+ 800486e:	681b      	ldr	r3, [r3, #0]
+ 8004870:	f503 5380 	add.w	r3, r3, #4096	; 0x1000
+ 8004874:	f8d3 3160 	ldr.w	r3, [r3, #352]	; 0x160
+ 8004878:	f403 5380 	and.w	r3, r3, #4096	; 0x1000
+ 800487c:	f5b3 5f80 	cmp.w	r3, #4096	; 0x1000
+ 8004880:	d11e      	bne.n	80048c0 <HAL_ETH_IRQHandler+0x118>
+      {
+        /* Get DMA error code  */
+        heth->DMAErrorCode = READ_BIT(heth->Instance->DMACSR, (ETH_DMACSR_FBE | ETH_DMACSR_TPS | ETH_DMACSR_RPS));
+ 8004882:	687b      	ldr	r3, [r7, #4]
+ 8004884:	681b      	ldr	r3, [r3, #0]
+ 8004886:	f503 5380 	add.w	r3, r3, #4096	; 0x1000
+ 800488a:	f8d3 2160 	ldr.w	r2, [r3, #352]	; 0x160
+ 800488e:	f241 1302 	movw	r3, #4354	; 0x1102
+ 8004892:	4013      	ands	r3, r2
+ 8004894:	687a      	ldr	r2, [r7, #4]
+ 8004896:	f8c2 308c 	str.w	r3, [r2, #140]	; 0x8c
+
+        /* Disable all interrupts */
+        __HAL_ETH_DMA_DISABLE_IT(heth, ETH_DMACIER_NIE | ETH_DMACIER_AIE);
+ 800489a:	687b      	ldr	r3, [r7, #4]
+ 800489c:	681b      	ldr	r3, [r3, #0]
+ 800489e:	f503 5380 	add.w	r3, r3, #4096	; 0x1000
+ 80048a2:	f8d3 3134 	ldr.w	r3, [r3, #308]	; 0x134
+ 80048a6:	687a      	ldr	r2, [r7, #4]
+ 80048a8:	6812      	ldr	r2, [r2, #0]
+ 80048aa:	f423 4340 	bic.w	r3, r3, #49152	; 0xc000
+ 80048ae:	f502 5280 	add.w	r2, r2, #4096	; 0x1000
+ 80048b2:	f8c2 3134 	str.w	r3, [r2, #308]	; 0x134
+
+        /* Set HAL state to ERROR */
+        heth->gState = HAL_ETH_STATE_ERROR;
+ 80048b6:	687b      	ldr	r3, [r7, #4]
+ 80048b8:	22e0      	movs	r2, #224	; 0xe0
+ 80048ba:	f8c3 2084 	str.w	r2, [r3, #132]	; 0x84
+ 80048be:	e013      	b.n	80048e8 <HAL_ETH_IRQHandler+0x140>
+      }
+      else
+      {
+        /* Get DMA error status  */
+        heth->DMAErrorCode = READ_BIT(heth->Instance->DMACSR, (ETH_DMACSR_CDE | ETH_DMACSR_ETI | ETH_DMACSR_RWT |
+ 80048c0:	687b      	ldr	r3, [r7, #4]
+ 80048c2:	681b      	ldr	r3, [r3, #0]
+ 80048c4:	f503 5380 	add.w	r3, r3, #4096	; 0x1000
+ 80048c8:	f8d3 3160 	ldr.w	r3, [r3, #352]	; 0x160
+ 80048cc:	f403 42cd 	and.w	r2, r3, #26240	; 0x6680
+ 80048d0:	687b      	ldr	r3, [r7, #4]
+ 80048d2:	f8c3 208c 	str.w	r2, [r3, #140]	; 0x8c
+                                                               ETH_DMACSR_RBU | ETH_DMACSR_AIS));
+
+        /* Clear the interrupt summary flag */
+        __HAL_ETH_DMA_CLEAR_IT(heth, (ETH_DMACSR_CDE | ETH_DMACSR_ETI | ETH_DMACSR_RWT |
+ 80048d6:	687b      	ldr	r3, [r7, #4]
+ 80048d8:	681b      	ldr	r3, [r3, #0]
+ 80048da:	f503 5380 	add.w	r3, r3, #4096	; 0x1000
+ 80048de:	461a      	mov	r2, r3
+ 80048e0:	f44f 43cd 	mov.w	r3, #26240	; 0x6680
+ 80048e4:	f8c2 3160 	str.w	r3, [r2, #352]	; 0x160
+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
+      /* Call registered Error callback*/
+      heth->ErrorCallback(heth);
+#else
+      /* Ethernet DMA Error callback */
+      HAL_ETH_ErrorCallback(heth);
+ 80048e8:	6878      	ldr	r0, [r7, #4]
+ 80048ea:	f00a ff8b 	bl	800f804 <HAL_ETH_ErrorCallback>
+
+    }
+  }
+
+  /* ETH MAC Error IT */
+  macirqenable = heth->Instance->MACIER;
+ 80048ee:	687b      	ldr	r3, [r7, #4]
+ 80048f0:	681b      	ldr	r3, [r3, #0]
+ 80048f2:	f8d3 30b4 	ldr.w	r3, [r3, #180]	; 0xb4
+ 80048f6:	60fb      	str	r3, [r7, #12]
+  if (((macirqenable & ETH_MACIER_RXSTSIE) == ETH_MACIER_RXSTSIE) || \
+ 80048f8:	68fb      	ldr	r3, [r7, #12]
+ 80048fa:	f403 4380 	and.w	r3, r3, #16384	; 0x4000
+ 80048fe:	2b00      	cmp	r3, #0
+ 8004900:	d104      	bne.n	800490c <HAL_ETH_IRQHandler+0x164>
+      ((macirqenable & ETH_MACIER_TXSTSIE) == ETH_MACIER_TXSTSIE))
+ 8004902:	68fb      	ldr	r3, [r7, #12]
+ 8004904:	f403 5300 	and.w	r3, r3, #8192	; 0x2000
+  if (((macirqenable & ETH_MACIER_RXSTSIE) == ETH_MACIER_RXSTSIE) || \
+ 8004908:	2b00      	cmp	r3, #0
+ 800490a:	d019      	beq.n	8004940 <HAL_ETH_IRQHandler+0x198>
+  {
+    heth->ErrorCode |= HAL_ETH_ERROR_MAC;
+ 800490c:	687b      	ldr	r3, [r7, #4]
+ 800490e:	f8d3 3088 	ldr.w	r3, [r3, #136]	; 0x88
+ 8004912:	f043 0210 	orr.w	r2, r3, #16
+ 8004916:	687b      	ldr	r3, [r7, #4]
+ 8004918:	f8c3 2088 	str.w	r2, [r3, #136]	; 0x88
+
+    /* Get MAC Rx Tx status and clear Status register pending bit */
+    heth->MACErrorCode = READ_REG(heth->Instance->MACRXTXSR);
+ 800491c:	687b      	ldr	r3, [r7, #4]
+ 800491e:	681b      	ldr	r3, [r3, #0]
+ 8004920:	f8d3 20b8 	ldr.w	r2, [r3, #184]	; 0xb8
+ 8004924:	687b      	ldr	r3, [r7, #4]
+ 8004926:	f8c3 2090 	str.w	r2, [r3, #144]	; 0x90
+
+    heth->gState = HAL_ETH_STATE_ERROR;
+ 800492a:	687b      	ldr	r3, [r7, #4]
+ 800492c:	22e0      	movs	r2, #224	; 0xe0
+ 800492e:	f8c3 2084 	str.w	r2, [r3, #132]	; 0x84
+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
+    /* Call registered Error callback*/
+    heth->ErrorCallback(heth);
+#else
+    /* Ethernet Error callback */
+    HAL_ETH_ErrorCallback(heth);
+ 8004932:	6878      	ldr	r0, [r7, #4]
+ 8004934:	f00a ff66 	bl	800f804 <HAL_ETH_ErrorCallback>
+#endif  /* USE_HAL_ETH_REGISTER_CALLBACKS */
+
+    heth->MACErrorCode = (uint32_t)(0x0U);
+ 8004938:	687b      	ldr	r3, [r7, #4]
+ 800493a:	2200      	movs	r2, #0
+ 800493c:	f8c3 2090 	str.w	r2, [r3, #144]	; 0x90
+  }
+
+  /* ETH PMT IT */
+  if (__HAL_ETH_MAC_GET_IT(heth, ETH_MAC_PMT_IT))
+ 8004940:	687b      	ldr	r3, [r7, #4]
+ 8004942:	681b      	ldr	r3, [r3, #0]
+ 8004944:	f8d3 30b0 	ldr.w	r3, [r3, #176]	; 0xb0
+ 8004948:	f003 0310 	and.w	r3, r3, #16
+ 800494c:	2b10      	cmp	r3, #16
+ 800494e:	d10f      	bne.n	8004970 <HAL_ETH_IRQHandler+0x1c8>
+  {
+    /* Get MAC Wake-up source and clear the status register pending bit */
+    heth->MACWakeUpEvent = READ_BIT(heth->Instance->MACPCSR, (ETH_MACPCSR_RWKPRCVD | ETH_MACPCSR_MGKPRCVD));
+ 8004950:	687b      	ldr	r3, [r7, #4]
+ 8004952:	681b      	ldr	r3, [r3, #0]
+ 8004954:	f8d3 30c0 	ldr.w	r3, [r3, #192]	; 0xc0
+ 8004958:	f003 0260 	and.w	r2, r3, #96	; 0x60
+ 800495c:	687b      	ldr	r3, [r7, #4]
+ 800495e:	f8c3 2094 	str.w	r2, [r3, #148]	; 0x94
+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
+    /* Call registered PMT callback*/
+    heth->PMTCallback(heth);
+#else
+    /* Ethernet PMT callback */
+    HAL_ETH_PMTCallback(heth);
+ 8004962:	6878      	ldr	r0, [r7, #4]
+ 8004964:	f000 f830 	bl	80049c8 <HAL_ETH_PMTCallback>
+#endif  /* USE_HAL_ETH_REGISTER_CALLBACKS */
+
+    heth->MACWakeUpEvent = (uint32_t)(0x0U);
+ 8004968:	687b      	ldr	r3, [r7, #4]
+ 800496a:	2200      	movs	r2, #0
+ 800496c:	f8c3 2094 	str.w	r2, [r3, #148]	; 0x94
+  }
+
+  /* ETH EEE IT */
+  if (__HAL_ETH_MAC_GET_IT(heth, ETH_MAC_LPI_IT))
+ 8004970:	687b      	ldr	r3, [r7, #4]
+ 8004972:	681b      	ldr	r3, [r3, #0]
+ 8004974:	f8d3 30b0 	ldr.w	r3, [r3, #176]	; 0xb0
+ 8004978:	f003 0320 	and.w	r3, r3, #32
+ 800497c:	2b20      	cmp	r3, #32
+ 800497e:	d10f      	bne.n	80049a0 <HAL_ETH_IRQHandler+0x1f8>
+  {
+    /* Get MAC LPI interrupt source and clear the status register pending bit */
+    heth->MACLPIEvent = READ_BIT(heth->Instance->MACPCSR, 0x0000000FU);
+ 8004980:	687b      	ldr	r3, [r7, #4]
+ 8004982:	681b      	ldr	r3, [r3, #0]
+ 8004984:	f8d3 30c0 	ldr.w	r3, [r3, #192]	; 0xc0
+ 8004988:	f003 020f 	and.w	r2, r3, #15
+ 800498c:	687b      	ldr	r3, [r7, #4]
+ 800498e:	f8c3 2098 	str.w	r2, [r3, #152]	; 0x98
+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
+    /* Call registered EEE callback*/
+    heth->EEECallback(heth);
+#else
+    /* Ethernet EEE callback */
+    HAL_ETH_EEECallback(heth);
+ 8004992:	6878      	ldr	r0, [r7, #4]
+ 8004994:	f000 f822 	bl	80049dc <HAL_ETH_EEECallback>
+#endif  /* USE_HAL_ETH_REGISTER_CALLBACKS */
+
+    heth->MACLPIEvent = (uint32_t)(0x0U);
+ 8004998:	687b      	ldr	r3, [r7, #4]
+ 800499a:	2200      	movs	r2, #0
+ 800499c:	f8c3 2098 	str.w	r2, [r3, #152]	; 0x98
+#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
+    }
+  }
+#else /* USE_HAL_ETH_REGISTER_CALLBACKS */
+  /* check ETH WAKEUP exti flag */
+  if (__HAL_ETH_WAKEUP_EXTI_GET_FLAG(ETH_WAKEUP_EXTI_LINE) != (uint32_t)RESET)
+ 80049a0:	4b08      	ldr	r3, [pc, #32]	; (80049c4 <HAL_ETH_IRQHandler+0x21c>)
+ 80049a2:	6a9b      	ldr	r3, [r3, #40]	; 0x28
+ 80049a4:	f403 0380 	and.w	r3, r3, #4194304	; 0x400000
+ 80049a8:	2b00      	cmp	r3, #0
+ 80049aa:	d006      	beq.n	80049ba <HAL_ETH_IRQHandler+0x212>
+  {
+    /* Clear ETH WAKEUP Exti pending bit */
+    __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG(ETH_WAKEUP_EXTI_LINE);
+ 80049ac:	4b05      	ldr	r3, [pc, #20]	; (80049c4 <HAL_ETH_IRQHandler+0x21c>)
+ 80049ae:	f44f 0280 	mov.w	r2, #4194304	; 0x400000
+ 80049b2:	629a      	str	r2, [r3, #40]	; 0x28
+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
+    /* Call registered WakeUp callback*/
+    heth->WakeUpCallback(heth);
+#else
+    /* ETH WAKEUP callback */
+    HAL_ETH_WakeUpCallback(heth);
+ 80049b4:	6878      	ldr	r0, [r7, #4]
+ 80049b6:	f000 f81b 	bl	80049f0 <HAL_ETH_WakeUpCallback>
+#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
+  }
+#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
+}
+ 80049ba:	bf00      	nop
+ 80049bc:	3710      	adds	r7, #16
+ 80049be:	46bd      	mov	sp, r7
+ 80049c0:	bd80      	pop	{r7, pc}
+ 80049c2:	bf00      	nop
+ 80049c4:	58000080 	.word	0x58000080
+
+080049c8 <HAL_ETH_PMTCallback>:
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @retval None
+  */
+__weak void HAL_ETH_PMTCallback(ETH_HandleTypeDef *heth)
+{
+ 80049c8:	b480      	push	{r7}
+ 80049ca:	b083      	sub	sp, #12
+ 80049cc:	af00      	add	r7, sp, #0
+ 80049ce:	6078      	str	r0, [r7, #4]
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(heth);
+  /* NOTE : This function Should not be modified, when the callback is needed,
+  the HAL_ETH_PMTCallback could be implemented in the user file
+  */
+}
+ 80049d0:	bf00      	nop
+ 80049d2:	370c      	adds	r7, #12
+ 80049d4:	46bd      	mov	sp, r7
+ 80049d6:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 80049da:	4770      	bx	lr
+
+080049dc <HAL_ETH_EEECallback>:
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @retval None
+  */
+__weak void HAL_ETH_EEECallback(ETH_HandleTypeDef *heth)
+{
+ 80049dc:	b480      	push	{r7}
+ 80049de:	b083      	sub	sp, #12
+ 80049e0:	af00      	add	r7, sp, #0
+ 80049e2:	6078      	str	r0, [r7, #4]
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(heth);
+  /* NOTE : This function Should not be modified, when the callback is needed,
+  the HAL_ETH_EEECallback could be implemented in the user file
+  */
+}
+ 80049e4:	bf00      	nop
+ 80049e6:	370c      	adds	r7, #12
+ 80049e8:	46bd      	mov	sp, r7
+ 80049ea:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 80049ee:	4770      	bx	lr
+
+080049f0 <HAL_ETH_WakeUpCallback>:
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @retval None
+  */
+__weak void HAL_ETH_WakeUpCallback(ETH_HandleTypeDef *heth)
+{
+ 80049f0:	b480      	push	{r7}
+ 80049f2:	b083      	sub	sp, #12
+ 80049f4:	af00      	add	r7, sp, #0
+ 80049f6:	6078      	str	r0, [r7, #4]
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(heth);
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_ETH_WakeUpCallback could be implemented in the user file
+   */
+}
+ 80049f8:	bf00      	nop
+ 80049fa:	370c      	adds	r7, #12
+ 80049fc:	46bd      	mov	sp, r7
+ 80049fe:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8004a02:	4770      	bx	lr
+
+08004a04 <HAL_ETH_ReadPHYRegister>:
+  * @param pRegValue: parameter to hold read value
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg,
+                                          uint32_t *pRegValue)
+{
+ 8004a04:	b580      	push	{r7, lr}
+ 8004a06:	b086      	sub	sp, #24
+ 8004a08:	af00      	add	r7, sp, #0
+ 8004a0a:	60f8      	str	r0, [r7, #12]
+ 8004a0c:	60b9      	str	r1, [r7, #8]
+ 8004a0e:	607a      	str	r2, [r7, #4]
+ 8004a10:	603b      	str	r3, [r7, #0]
+  uint32_t tickstart;
+  uint32_t tmpreg;
+
+  /* Check for the Busy flag */
+  if (READ_BIT(heth->Instance->MACMDIOAR, ETH_MACMDIOAR_MB) != (uint32_t)RESET)
+ 8004a12:	68fb      	ldr	r3, [r7, #12]
+ 8004a14:	681b      	ldr	r3, [r3, #0]
+ 8004a16:	f8d3 3200 	ldr.w	r3, [r3, #512]	; 0x200
+ 8004a1a:	f003 0301 	and.w	r3, r3, #1
+ 8004a1e:	2b00      	cmp	r3, #0
+ 8004a20:	d001      	beq.n	8004a26 <HAL_ETH_ReadPHYRegister+0x22>
+  {
+    return HAL_ERROR;
+ 8004a22:	2301      	movs	r3, #1
+ 8004a24:	e03e      	b.n	8004aa4 <HAL_ETH_ReadPHYRegister+0xa0>
+  }
+
+  /* Get the  MACMDIOAR value */
+  WRITE_REG(tmpreg, heth->Instance->MACMDIOAR);
+ 8004a26:	68fb      	ldr	r3, [r7, #12]
+ 8004a28:	681b      	ldr	r3, [r3, #0]
+ 8004a2a:	f8d3 3200 	ldr.w	r3, [r3, #512]	; 0x200
+ 8004a2e:	617b      	str	r3, [r7, #20]
+     - Set the PHY device address
+     - Set the PHY register address
+     - Set the read mode
+     - Set the MII Busy bit */
+
+  MODIFY_REG(tmpreg, ETH_MACMDIOAR_PA, (PHYAddr << 21));
+ 8004a30:	697b      	ldr	r3, [r7, #20]
+ 8004a32:	f023 7278 	bic.w	r2, r3, #65011712	; 0x3e00000
+ 8004a36:	68bb      	ldr	r3, [r7, #8]
+ 8004a38:	055b      	lsls	r3, r3, #21
+ 8004a3a:	4313      	orrs	r3, r2
+ 8004a3c:	617b      	str	r3, [r7, #20]
+  MODIFY_REG(tmpreg, ETH_MACMDIOAR_RDA, (PHYReg << 16));
+ 8004a3e:	697b      	ldr	r3, [r7, #20]
+ 8004a40:	f423 12f8 	bic.w	r2, r3, #2031616	; 0x1f0000
+ 8004a44:	687b      	ldr	r3, [r7, #4]
+ 8004a46:	041b      	lsls	r3, r3, #16
+ 8004a48:	4313      	orrs	r3, r2
+ 8004a4a:	617b      	str	r3, [r7, #20]
+  MODIFY_REG(tmpreg, ETH_MACMDIOAR_MOC, ETH_MACMDIOAR_MOC_RD);
+ 8004a4c:	697b      	ldr	r3, [r7, #20]
+ 8004a4e:	f043 030c 	orr.w	r3, r3, #12
+ 8004a52:	617b      	str	r3, [r7, #20]
+  SET_BIT(tmpreg, ETH_MACMDIOAR_MB);
+ 8004a54:	697b      	ldr	r3, [r7, #20]
+ 8004a56:	f043 0301 	orr.w	r3, r3, #1
+ 8004a5a:	617b      	str	r3, [r7, #20]
+
+  /* Write the result value into the MDII Address register */
+  WRITE_REG(heth->Instance->MACMDIOAR, tmpreg);
+ 8004a5c:	68fb      	ldr	r3, [r7, #12]
+ 8004a5e:	681b      	ldr	r3, [r3, #0]
+ 8004a60:	697a      	ldr	r2, [r7, #20]
+ 8004a62:	f8c3 2200 	str.w	r2, [r3, #512]	; 0x200
+
+  tickstart = HAL_GetTick();
+ 8004a66:	f7fd fc7d 	bl	8002364 <HAL_GetTick>
+ 8004a6a:	6138      	str	r0, [r7, #16]
+
+  /* Wait for the Busy flag */
+  while (READ_BIT(heth->Instance->MACMDIOAR, ETH_MACMDIOAR_MB) > 0U)
+ 8004a6c:	e009      	b.n	8004a82 <HAL_ETH_ReadPHYRegister+0x7e>
+  {
+    if (((HAL_GetTick() - tickstart) > ETH_MDIO_BUS_TIMEOUT))
+ 8004a6e:	f7fd fc79 	bl	8002364 <HAL_GetTick>
+ 8004a72:	4602      	mov	r2, r0
+ 8004a74:	693b      	ldr	r3, [r7, #16]
+ 8004a76:	1ad3      	subs	r3, r2, r3
+ 8004a78:	f5b3 7f7a 	cmp.w	r3, #1000	; 0x3e8
+ 8004a7c:	d901      	bls.n	8004a82 <HAL_ETH_ReadPHYRegister+0x7e>
+    {
+      return HAL_ERROR;
+ 8004a7e:	2301      	movs	r3, #1
+ 8004a80:	e010      	b.n	8004aa4 <HAL_ETH_ReadPHYRegister+0xa0>
+  while (READ_BIT(heth->Instance->MACMDIOAR, ETH_MACMDIOAR_MB) > 0U)
+ 8004a82:	68fb      	ldr	r3, [r7, #12]
+ 8004a84:	681b      	ldr	r3, [r3, #0]
+ 8004a86:	f8d3 3200 	ldr.w	r3, [r3, #512]	; 0x200
+ 8004a8a:	f003 0301 	and.w	r3, r3, #1
+ 8004a8e:	2b00      	cmp	r3, #0
+ 8004a90:	d1ed      	bne.n	8004a6e <HAL_ETH_ReadPHYRegister+0x6a>
+    }
+  }
+
+  /* Get MACMIIDR value */
+  WRITE_REG(*pRegValue, (uint16_t)heth->Instance->MACMDIODR);
+ 8004a92:	68fb      	ldr	r3, [r7, #12]
+ 8004a94:	681b      	ldr	r3, [r3, #0]
+ 8004a96:	f8d3 3204 	ldr.w	r3, [r3, #516]	; 0x204
+ 8004a9a:	b29b      	uxth	r3, r3
+ 8004a9c:	461a      	mov	r2, r3
+ 8004a9e:	683b      	ldr	r3, [r7, #0]
+ 8004aa0:	601a      	str	r2, [r3, #0]
+
+  return HAL_OK;
+ 8004aa2:	2300      	movs	r3, #0
+}
+ 8004aa4:	4618      	mov	r0, r3
+ 8004aa6:	3718      	adds	r7, #24
+ 8004aa8:	46bd      	mov	sp, r7
+ 8004aaa:	bd80      	pop	{r7, pc}
+
+08004aac <HAL_ETH_WritePHYRegister>:
+  * @param  RegValue: the value to write
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg,
+                                           uint32_t RegValue)
+{
+ 8004aac:	b580      	push	{r7, lr}
+ 8004aae:	b086      	sub	sp, #24
+ 8004ab0:	af00      	add	r7, sp, #0
+ 8004ab2:	60f8      	str	r0, [r7, #12]
+ 8004ab4:	60b9      	str	r1, [r7, #8]
+ 8004ab6:	607a      	str	r2, [r7, #4]
+ 8004ab8:	603b      	str	r3, [r7, #0]
+  uint32_t tickstart;
+  uint32_t tmpreg;
+
+  /* Check for the Busy flag */
+  if (READ_BIT(heth->Instance->MACMDIOAR, ETH_MACMDIOAR_MB) != (uint32_t)RESET)
+ 8004aba:	68fb      	ldr	r3, [r7, #12]
+ 8004abc:	681b      	ldr	r3, [r3, #0]
+ 8004abe:	f8d3 3200 	ldr.w	r3, [r3, #512]	; 0x200
+ 8004ac2:	f003 0301 	and.w	r3, r3, #1
+ 8004ac6:	2b00      	cmp	r3, #0
+ 8004ac8:	d001      	beq.n	8004ace <HAL_ETH_WritePHYRegister+0x22>
+  {
+    return HAL_ERROR;
+ 8004aca:	2301      	movs	r3, #1
+ 8004acc:	e03c      	b.n	8004b48 <HAL_ETH_WritePHYRegister+0x9c>
+  }
+
+  /* Get the  MACMDIOAR value */
+  WRITE_REG(tmpreg, heth->Instance->MACMDIOAR);
+ 8004ace:	68fb      	ldr	r3, [r7, #12]
+ 8004ad0:	681b      	ldr	r3, [r3, #0]
+ 8004ad2:	f8d3 3200 	ldr.w	r3, [r3, #512]	; 0x200
+ 8004ad6:	617b      	str	r3, [r7, #20]
+     - Set the PHY device address
+     - Set the PHY register address
+     - Set the write mode
+     - Set the MII Busy bit */
+
+  MODIFY_REG(tmpreg, ETH_MACMDIOAR_PA, (PHYAddr << 21));
+ 8004ad8:	697b      	ldr	r3, [r7, #20]
+ 8004ada:	f023 7278 	bic.w	r2, r3, #65011712	; 0x3e00000
+ 8004ade:	68bb      	ldr	r3, [r7, #8]
+ 8004ae0:	055b      	lsls	r3, r3, #21
+ 8004ae2:	4313      	orrs	r3, r2
+ 8004ae4:	617b      	str	r3, [r7, #20]
+  MODIFY_REG(tmpreg, ETH_MACMDIOAR_RDA, (PHYReg << 16));
+ 8004ae6:	697b      	ldr	r3, [r7, #20]
+ 8004ae8:	f423 12f8 	bic.w	r2, r3, #2031616	; 0x1f0000
+ 8004aec:	687b      	ldr	r3, [r7, #4]
+ 8004aee:	041b      	lsls	r3, r3, #16
+ 8004af0:	4313      	orrs	r3, r2
+ 8004af2:	617b      	str	r3, [r7, #20]
+  MODIFY_REG(tmpreg, ETH_MACMDIOAR_MOC, ETH_MACMDIOAR_MOC_WR);
+ 8004af4:	697b      	ldr	r3, [r7, #20]
+ 8004af6:	f023 030c 	bic.w	r3, r3, #12
+ 8004afa:	f043 0304 	orr.w	r3, r3, #4
+ 8004afe:	617b      	str	r3, [r7, #20]
+  SET_BIT(tmpreg, ETH_MACMDIOAR_MB);
+ 8004b00:	697b      	ldr	r3, [r7, #20]
+ 8004b02:	f043 0301 	orr.w	r3, r3, #1
+ 8004b06:	617b      	str	r3, [r7, #20]
+
+
+  /* Give the value to the MII data register */
+  WRITE_REG(ETH->MACMDIODR, (uint16_t)RegValue);
+ 8004b08:	683b      	ldr	r3, [r7, #0]
+ 8004b0a:	b29a      	uxth	r2, r3
+ 8004b0c:	4b10      	ldr	r3, [pc, #64]	; (8004b50 <HAL_ETH_WritePHYRegister+0xa4>)
+ 8004b0e:	f8c3 2204 	str.w	r2, [r3, #516]	; 0x204
+
+  /* Write the result value into the MII Address register */
+  WRITE_REG(ETH->MACMDIOAR, tmpreg);
+ 8004b12:	4a0f      	ldr	r2, [pc, #60]	; (8004b50 <HAL_ETH_WritePHYRegister+0xa4>)
+ 8004b14:	697b      	ldr	r3, [r7, #20]
+ 8004b16:	f8c2 3200 	str.w	r3, [r2, #512]	; 0x200
+
+  tickstart = HAL_GetTick();
+ 8004b1a:	f7fd fc23 	bl	8002364 <HAL_GetTick>
+ 8004b1e:	6138      	str	r0, [r7, #16]
+
+  /* Wait for the Busy flag */
+  while (READ_BIT(heth->Instance->MACMDIOAR, ETH_MACMDIOAR_MB) > 0U)
+ 8004b20:	e009      	b.n	8004b36 <HAL_ETH_WritePHYRegister+0x8a>
+  {
+    if (((HAL_GetTick() - tickstart) > ETH_MDIO_BUS_TIMEOUT))
+ 8004b22:	f7fd fc1f 	bl	8002364 <HAL_GetTick>
+ 8004b26:	4602      	mov	r2, r0
+ 8004b28:	693b      	ldr	r3, [r7, #16]
+ 8004b2a:	1ad3      	subs	r3, r2, r3
+ 8004b2c:	f5b3 7f7a 	cmp.w	r3, #1000	; 0x3e8
+ 8004b30:	d901      	bls.n	8004b36 <HAL_ETH_WritePHYRegister+0x8a>
+    {
+      return HAL_ERROR;
+ 8004b32:	2301      	movs	r3, #1
+ 8004b34:	e008      	b.n	8004b48 <HAL_ETH_WritePHYRegister+0x9c>
+  while (READ_BIT(heth->Instance->MACMDIOAR, ETH_MACMDIOAR_MB) > 0U)
+ 8004b36:	68fb      	ldr	r3, [r7, #12]
+ 8004b38:	681b      	ldr	r3, [r3, #0]
+ 8004b3a:	f8d3 3200 	ldr.w	r3, [r3, #512]	; 0x200
+ 8004b3e:	f003 0301 	and.w	r3, r3, #1
+ 8004b42:	2b00      	cmp	r3, #0
+ 8004b44:	d1ed      	bne.n	8004b22 <HAL_ETH_WritePHYRegister+0x76>
+    }
+  }
+
+  return HAL_OK;
+ 8004b46:	2300      	movs	r3, #0
+}
+ 8004b48:	4618      	mov	r0, r3
+ 8004b4a:	3718      	adds	r7, #24
+ 8004b4c:	46bd      	mov	sp, r7
+ 8004b4e:	bd80      	pop	{r7, pc}
+ 8004b50:	40028000 	.word	0x40028000
+
+08004b54 <HAL_ETH_GetMACConfig>:
+  * @param  macconf: pointer to a ETH_MACConfigTypeDef structure that will hold
+  *         the configuration of the MAC.
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_ETH_GetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf)
+{
+ 8004b54:	b480      	push	{r7}
+ 8004b56:	b083      	sub	sp, #12
+ 8004b58:	af00      	add	r7, sp, #0
+ 8004b5a:	6078      	str	r0, [r7, #4]
+ 8004b5c:	6039      	str	r1, [r7, #0]
+  if (macconf == NULL)
+ 8004b5e:	683b      	ldr	r3, [r7, #0]
+ 8004b60:	2b00      	cmp	r3, #0
+ 8004b62:	d101      	bne.n	8004b68 <HAL_ETH_GetMACConfig+0x14>
+  {
+    return HAL_ERROR;
+ 8004b64:	2301      	movs	r3, #1
+ 8004b66:	e1c3      	b.n	8004ef0 <HAL_ETH_GetMACConfig+0x39c>
+  }
+
+  /* Get MAC parameters */
+  macconf->PreambleLength = READ_BIT(heth->Instance->MACCR, ETH_MACCR_PRELEN);
+ 8004b68:	687b      	ldr	r3, [r7, #4]
+ 8004b6a:	681b      	ldr	r3, [r3, #0]
+ 8004b6c:	681b      	ldr	r3, [r3, #0]
+ 8004b6e:	f003 020c 	and.w	r2, r3, #12
+ 8004b72:	683b      	ldr	r3, [r7, #0]
+ 8004b74:	62da      	str	r2, [r3, #44]	; 0x2c
+  macconf->DeferralCheck = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_DC) >> 4) > 0U) ? ENABLE : DISABLE;
+ 8004b76:	687b      	ldr	r3, [r7, #4]
+ 8004b78:	681b      	ldr	r3, [r3, #0]
+ 8004b7a:	681b      	ldr	r3, [r3, #0]
+ 8004b7c:	f003 0310 	and.w	r3, r3, #16
+ 8004b80:	2b00      	cmp	r3, #0
+ 8004b82:	bf14      	ite	ne
+ 8004b84:	2301      	movne	r3, #1
+ 8004b86:	2300      	moveq	r3, #0
+ 8004b88:	b2db      	uxtb	r3, r3
+ 8004b8a:	461a      	mov	r2, r3
+ 8004b8c:	683b      	ldr	r3, [r7, #0]
+ 8004b8e:	f883 2028 	strb.w	r2, [r3, #40]	; 0x28
+  macconf->BackOffLimit = READ_BIT(heth->Instance->MACCR, ETH_MACCR_BL);
+ 8004b92:	687b      	ldr	r3, [r7, #4]
+ 8004b94:	681b      	ldr	r3, [r3, #0]
+ 8004b96:	681b      	ldr	r3, [r3, #0]
+ 8004b98:	f003 0260 	and.w	r2, r3, #96	; 0x60
+ 8004b9c:	683b      	ldr	r3, [r7, #0]
+ 8004b9e:	625a      	str	r2, [r3, #36]	; 0x24
+  macconf->RetryTransmission = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_DR) >> 8) == 0U) ? ENABLE : DISABLE;
+ 8004ba0:	687b      	ldr	r3, [r7, #4]
+ 8004ba2:	681b      	ldr	r3, [r3, #0]
+ 8004ba4:	681b      	ldr	r3, [r3, #0]
+ 8004ba6:	f403 7380 	and.w	r3, r3, #256	; 0x100
+ 8004baa:	2b00      	cmp	r3, #0
+ 8004bac:	bf0c      	ite	eq
+ 8004bae:	2301      	moveq	r3, #1
+ 8004bb0:	2300      	movne	r3, #0
+ 8004bb2:	b2db      	uxtb	r3, r3
+ 8004bb4:	461a      	mov	r2, r3
+ 8004bb6:	683b      	ldr	r3, [r7, #0]
+ 8004bb8:	f883 2020 	strb.w	r2, [r3, #32]
+  macconf->CarrierSenseDuringTransmit = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_DCRS) >> 9) > 0U)
+ 8004bbc:	687b      	ldr	r3, [r7, #4]
+ 8004bbe:	681b      	ldr	r3, [r3, #0]
+ 8004bc0:	681b      	ldr	r3, [r3, #0]
+ 8004bc2:	f403 7300 	and.w	r3, r3, #512	; 0x200
+                                        ? ENABLE : DISABLE;
+ 8004bc6:	2b00      	cmp	r3, #0
+ 8004bc8:	bf14      	ite	ne
+ 8004bca:	2301      	movne	r3, #1
+ 8004bcc:	2300      	moveq	r3, #0
+ 8004bce:	b2db      	uxtb	r3, r3
+ 8004bd0:	461a      	mov	r2, r3
+  macconf->CarrierSenseDuringTransmit = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_DCRS) >> 9) > 0U)
+ 8004bd2:	683b      	ldr	r3, [r7, #0]
+ 8004bd4:	77da      	strb	r2, [r3, #31]
+  macconf->ReceiveOwn = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_DO) >> 10) == 0U) ? ENABLE : DISABLE;
+ 8004bd6:	687b      	ldr	r3, [r7, #4]
+ 8004bd8:	681b      	ldr	r3, [r3, #0]
+ 8004bda:	681b      	ldr	r3, [r3, #0]
+ 8004bdc:	f403 6380 	and.w	r3, r3, #1024	; 0x400
+ 8004be0:	2b00      	cmp	r3, #0
+ 8004be2:	bf0c      	ite	eq
+ 8004be4:	2301      	moveq	r3, #1
+ 8004be6:	2300      	movne	r3, #0
+ 8004be8:	b2db      	uxtb	r3, r3
+ 8004bea:	461a      	mov	r2, r3
+ 8004bec:	683b      	ldr	r3, [r7, #0]
+ 8004bee:	779a      	strb	r2, [r3, #30]
+  macconf->CarrierSenseBeforeTransmit = ((READ_BIT(heth->Instance->MACCR,
+ 8004bf0:	687b      	ldr	r3, [r7, #4]
+ 8004bf2:	681b      	ldr	r3, [r3, #0]
+ 8004bf4:	681b      	ldr	r3, [r3, #0]
+                                                   ETH_MACCR_ECRSFD) >> 11) > 0U) ? ENABLE : DISABLE;
+ 8004bf6:	f403 6300 	and.w	r3, r3, #2048	; 0x800
+ 8004bfa:	2b00      	cmp	r3, #0
+ 8004bfc:	bf14      	ite	ne
+ 8004bfe:	2301      	movne	r3, #1
+ 8004c00:	2300      	moveq	r3, #0
+ 8004c02:	b2db      	uxtb	r3, r3
+ 8004c04:	461a      	mov	r2, r3
+  macconf->CarrierSenseBeforeTransmit = ((READ_BIT(heth->Instance->MACCR,
+ 8004c06:	683b      	ldr	r3, [r7, #0]
+ 8004c08:	775a      	strb	r2, [r3, #29]
+  macconf->LoopbackMode = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_LM) >> 12) > 0U) ? ENABLE : DISABLE;
+ 8004c0a:	687b      	ldr	r3, [r7, #4]
+ 8004c0c:	681b      	ldr	r3, [r3, #0]
+ 8004c0e:	681b      	ldr	r3, [r3, #0]
+ 8004c10:	f403 5380 	and.w	r3, r3, #4096	; 0x1000
+ 8004c14:	2b00      	cmp	r3, #0
+ 8004c16:	bf14      	ite	ne
+ 8004c18:	2301      	movne	r3, #1
+ 8004c1a:	2300      	moveq	r3, #0
+ 8004c1c:	b2db      	uxtb	r3, r3
+ 8004c1e:	461a      	mov	r2, r3
+ 8004c20:	683b      	ldr	r3, [r7, #0]
+ 8004c22:	771a      	strb	r2, [r3, #28]
+  macconf->DuplexMode = READ_BIT(heth->Instance->MACCR, ETH_MACCR_DM);
+ 8004c24:	687b      	ldr	r3, [r7, #4]
+ 8004c26:	681b      	ldr	r3, [r3, #0]
+ 8004c28:	681b      	ldr	r3, [r3, #0]
+ 8004c2a:	f403 5200 	and.w	r2, r3, #8192	; 0x2000
+ 8004c2e:	683b      	ldr	r3, [r7, #0]
+ 8004c30:	619a      	str	r2, [r3, #24]
+  macconf->Speed = READ_BIT(heth->Instance->MACCR, ETH_MACCR_FES);
+ 8004c32:	687b      	ldr	r3, [r7, #4]
+ 8004c34:	681b      	ldr	r3, [r3, #0]
+ 8004c36:	681b      	ldr	r3, [r3, #0]
+ 8004c38:	f403 4280 	and.w	r2, r3, #16384	; 0x4000
+ 8004c3c:	683b      	ldr	r3, [r7, #0]
+ 8004c3e:	615a      	str	r2, [r3, #20]
+  macconf->JumboPacket = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_JE) >> 16) > 0U) ? ENABLE : DISABLE;
+ 8004c40:	687b      	ldr	r3, [r7, #4]
+ 8004c42:	681b      	ldr	r3, [r3, #0]
+ 8004c44:	681b      	ldr	r3, [r3, #0]
+ 8004c46:	f403 3380 	and.w	r3, r3, #65536	; 0x10000
+ 8004c4a:	2b00      	cmp	r3, #0
+ 8004c4c:	bf14      	ite	ne
+ 8004c4e:	2301      	movne	r3, #1
+ 8004c50:	2300      	moveq	r3, #0
+ 8004c52:	b2db      	uxtb	r3, r3
+ 8004c54:	461a      	mov	r2, r3
+ 8004c56:	683b      	ldr	r3, [r7, #0]
+ 8004c58:	749a      	strb	r2, [r3, #18]
+  macconf->Jabber = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_JD) >> 17) == 0U) ? ENABLE : DISABLE;
+ 8004c5a:	687b      	ldr	r3, [r7, #4]
+ 8004c5c:	681b      	ldr	r3, [r3, #0]
+ 8004c5e:	681b      	ldr	r3, [r3, #0]
+ 8004c60:	f403 3300 	and.w	r3, r3, #131072	; 0x20000
+ 8004c64:	2b00      	cmp	r3, #0
+ 8004c66:	bf0c      	ite	eq
+ 8004c68:	2301      	moveq	r3, #1
+ 8004c6a:	2300      	movne	r3, #0
+ 8004c6c:	b2db      	uxtb	r3, r3
+ 8004c6e:	461a      	mov	r2, r3
+ 8004c70:	683b      	ldr	r3, [r7, #0]
+ 8004c72:	745a      	strb	r2, [r3, #17]
+  macconf->Watchdog = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_WD) >> 19) == 0U) ? ENABLE : DISABLE;
+ 8004c74:	687b      	ldr	r3, [r7, #4]
+ 8004c76:	681b      	ldr	r3, [r3, #0]
+ 8004c78:	681b      	ldr	r3, [r3, #0]
+ 8004c7a:	f403 2300 	and.w	r3, r3, #524288	; 0x80000
+ 8004c7e:	2b00      	cmp	r3, #0
+ 8004c80:	bf0c      	ite	eq
+ 8004c82:	2301      	moveq	r3, #1
+ 8004c84:	2300      	movne	r3, #0
+ 8004c86:	b2db      	uxtb	r3, r3
+ 8004c88:	461a      	mov	r2, r3
+ 8004c8a:	683b      	ldr	r3, [r7, #0]
+ 8004c8c:	741a      	strb	r2, [r3, #16]
+  macconf->AutomaticPadCRCStrip = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_ACS) >> 20) > 0U) ? ENABLE : DISABLE;
+ 8004c8e:	687b      	ldr	r3, [r7, #4]
+ 8004c90:	681b      	ldr	r3, [r3, #0]
+ 8004c92:	681b      	ldr	r3, [r3, #0]
+ 8004c94:	f403 1380 	and.w	r3, r3, #1048576	; 0x100000
+ 8004c98:	2b00      	cmp	r3, #0
+ 8004c9a:	bf14      	ite	ne
+ 8004c9c:	2301      	movne	r3, #1
+ 8004c9e:	2300      	moveq	r3, #0
+ 8004ca0:	b2db      	uxtb	r3, r3
+ 8004ca2:	461a      	mov	r2, r3
+ 8004ca4:	683b      	ldr	r3, [r7, #0]
+ 8004ca6:	73da      	strb	r2, [r3, #15]
+  macconf->CRCStripTypePacket = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_CST) >> 21) > 0U) ? ENABLE : DISABLE;
+ 8004ca8:	687b      	ldr	r3, [r7, #4]
+ 8004caa:	681b      	ldr	r3, [r3, #0]
+ 8004cac:	681b      	ldr	r3, [r3, #0]
+ 8004cae:	f403 1300 	and.w	r3, r3, #2097152	; 0x200000
+ 8004cb2:	2b00      	cmp	r3, #0
+ 8004cb4:	bf14      	ite	ne
+ 8004cb6:	2301      	movne	r3, #1
+ 8004cb8:	2300      	moveq	r3, #0
+ 8004cba:	b2db      	uxtb	r3, r3
+ 8004cbc:	461a      	mov	r2, r3
+ 8004cbe:	683b      	ldr	r3, [r7, #0]
+ 8004cc0:	739a      	strb	r2, [r3, #14]
+  macconf->Support2KPacket = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_S2KP) >> 22) > 0U) ? ENABLE : DISABLE;
+ 8004cc2:	687b      	ldr	r3, [r7, #4]
+ 8004cc4:	681b      	ldr	r3, [r3, #0]
+ 8004cc6:	681b      	ldr	r3, [r3, #0]
+ 8004cc8:	f403 0380 	and.w	r3, r3, #4194304	; 0x400000
+ 8004ccc:	2b00      	cmp	r3, #0
+ 8004cce:	bf14      	ite	ne
+ 8004cd0:	2301      	movne	r3, #1
+ 8004cd2:	2300      	moveq	r3, #0
+ 8004cd4:	b2db      	uxtb	r3, r3
+ 8004cd6:	461a      	mov	r2, r3
+ 8004cd8:	683b      	ldr	r3, [r7, #0]
+ 8004cda:	735a      	strb	r2, [r3, #13]
+  macconf->GiantPacketSizeLimitControl = ((READ_BIT(heth->Instance->MACCR,
+ 8004cdc:	687b      	ldr	r3, [r7, #4]
+ 8004cde:	681b      	ldr	r3, [r3, #0]
+ 8004ce0:	681b      	ldr	r3, [r3, #0]
+                                                    ETH_MACCR_GPSLCE) >> 23) > 0U) ? ENABLE : DISABLE;
+ 8004ce2:	f403 0300 	and.w	r3, r3, #8388608	; 0x800000
+ 8004ce6:	2b00      	cmp	r3, #0
+ 8004ce8:	bf14      	ite	ne
+ 8004cea:	2301      	movne	r3, #1
+ 8004cec:	2300      	moveq	r3, #0
+ 8004cee:	b2db      	uxtb	r3, r3
+ 8004cf0:	461a      	mov	r2, r3
+  macconf->GiantPacketSizeLimitControl = ((READ_BIT(heth->Instance->MACCR,
+ 8004cf2:	683b      	ldr	r3, [r7, #0]
+ 8004cf4:	731a      	strb	r2, [r3, #12]
+  macconf->InterPacketGapVal = READ_BIT(heth->Instance->MACCR, ETH_MACCR_IPG);
+ 8004cf6:	687b      	ldr	r3, [r7, #4]
+ 8004cf8:	681b      	ldr	r3, [r3, #0]
+ 8004cfa:	681b      	ldr	r3, [r3, #0]
+ 8004cfc:	f003 62e0 	and.w	r2, r3, #117440512	; 0x7000000
+ 8004d00:	683b      	ldr	r3, [r7, #0]
+ 8004d02:	609a      	str	r2, [r3, #8]
+  macconf->ChecksumOffload = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_IPC) >> 27) > 0U) ? ENABLE : DISABLE;
+ 8004d04:	687b      	ldr	r3, [r7, #4]
+ 8004d06:	681b      	ldr	r3, [r3, #0]
+ 8004d08:	681b      	ldr	r3, [r3, #0]
+ 8004d0a:	f003 6300 	and.w	r3, r3, #134217728	; 0x8000000
+ 8004d0e:	2b00      	cmp	r3, #0
+ 8004d10:	bf14      	ite	ne
+ 8004d12:	2301      	movne	r3, #1
+ 8004d14:	2300      	moveq	r3, #0
+ 8004d16:	b2db      	uxtb	r3, r3
+ 8004d18:	461a      	mov	r2, r3
+ 8004d1a:	683b      	ldr	r3, [r7, #0]
+ 8004d1c:	711a      	strb	r2, [r3, #4]
+  macconf->SourceAddrControl = READ_BIT(heth->Instance->MACCR, ETH_MACCR_SARC);
+ 8004d1e:	687b      	ldr	r3, [r7, #4]
+ 8004d20:	681b      	ldr	r3, [r3, #0]
+ 8004d22:	681b      	ldr	r3, [r3, #0]
+ 8004d24:	f003 42e0 	and.w	r2, r3, #1879048192	; 0x70000000
+ 8004d28:	683b      	ldr	r3, [r7, #0]
+ 8004d2a:	601a      	str	r2, [r3, #0]
+
+  macconf->GiantPacketSizeLimit = READ_BIT(heth->Instance->MACECR, ETH_MACECR_GPSL);
+ 8004d2c:	687b      	ldr	r3, [r7, #4]
+ 8004d2e:	681b      	ldr	r3, [r3, #0]
+ 8004d30:	685b      	ldr	r3, [r3, #4]
+ 8004d32:	f3c3 020d 	ubfx	r2, r3, #0, #14
+ 8004d36:	683b      	ldr	r3, [r7, #0]
+ 8004d38:	635a      	str	r2, [r3, #52]	; 0x34
+  macconf->CRCCheckingRxPackets = ((READ_BIT(heth->Instance->MACECR, ETH_MACECR_DCRCC) >> 16) == 0U) ? ENABLE : DISABLE;
+ 8004d3a:	687b      	ldr	r3, [r7, #4]
+ 8004d3c:	681b      	ldr	r3, [r3, #0]
+ 8004d3e:	685b      	ldr	r3, [r3, #4]
+ 8004d40:	f403 3380 	and.w	r3, r3, #65536	; 0x10000
+ 8004d44:	2b00      	cmp	r3, #0
+ 8004d46:	bf0c      	ite	eq
+ 8004d48:	2301      	moveq	r3, #1
+ 8004d4a:	2300      	movne	r3, #0
+ 8004d4c:	b2db      	uxtb	r3, r3
+ 8004d4e:	461a      	mov	r2, r3
+ 8004d50:	683b      	ldr	r3, [r7, #0]
+ 8004d52:	f883 2032 	strb.w	r2, [r3, #50]	; 0x32
+  macconf->SlowProtocolDetect = ((READ_BIT(heth->Instance->MACECR, ETH_MACECR_SPEN) >> 17) > 0U) ? ENABLE : DISABLE;
+ 8004d56:	687b      	ldr	r3, [r7, #4]
+ 8004d58:	681b      	ldr	r3, [r3, #0]
+ 8004d5a:	685b      	ldr	r3, [r3, #4]
+ 8004d5c:	f403 3300 	and.w	r3, r3, #131072	; 0x20000
+ 8004d60:	2b00      	cmp	r3, #0
+ 8004d62:	bf14      	ite	ne
+ 8004d64:	2301      	movne	r3, #1
+ 8004d66:	2300      	moveq	r3, #0
+ 8004d68:	b2db      	uxtb	r3, r3
+ 8004d6a:	461a      	mov	r2, r3
+ 8004d6c:	683b      	ldr	r3, [r7, #0]
+ 8004d6e:	f883 2031 	strb.w	r2, [r3, #49]	; 0x31
+  macconf->UnicastSlowProtocolPacketDetect = ((READ_BIT(heth->Instance->MACECR,
+ 8004d72:	687b      	ldr	r3, [r7, #4]
+ 8004d74:	681b      	ldr	r3, [r3, #0]
+ 8004d76:	685b      	ldr	r3, [r3, #4]
+                                                        ETH_MACECR_USP) >> 18) > 0U) ? ENABLE : DISABLE;
+ 8004d78:	f403 2380 	and.w	r3, r3, #262144	; 0x40000
+ 8004d7c:	2b00      	cmp	r3, #0
+ 8004d7e:	bf14      	ite	ne
+ 8004d80:	2301      	movne	r3, #1
+ 8004d82:	2300      	moveq	r3, #0
+ 8004d84:	b2db      	uxtb	r3, r3
+ 8004d86:	461a      	mov	r2, r3
+  macconf->UnicastSlowProtocolPacketDetect = ((READ_BIT(heth->Instance->MACECR,
+ 8004d88:	683b      	ldr	r3, [r7, #0]
+ 8004d8a:	f883 2030 	strb.w	r2, [r3, #48]	; 0x30
+  macconf->ExtendedInterPacketGap = ((READ_BIT(heth->Instance->MACECR, ETH_MACECR_EIPGEN) >> 24) > 0U)
+ 8004d8e:	687b      	ldr	r3, [r7, #4]
+ 8004d90:	681b      	ldr	r3, [r3, #0]
+ 8004d92:	685b      	ldr	r3, [r3, #4]
+ 8004d94:	f003 7380 	and.w	r3, r3, #16777216	; 0x1000000
+                                    ? ENABLE : DISABLE;
+ 8004d98:	2b00      	cmp	r3, #0
+ 8004d9a:	bf14      	ite	ne
+ 8004d9c:	2301      	movne	r3, #1
+ 8004d9e:	2300      	moveq	r3, #0
+ 8004da0:	b2db      	uxtb	r3, r3
+ 8004da2:	461a      	mov	r2, r3
+  macconf->ExtendedInterPacketGap = ((READ_BIT(heth->Instance->MACECR, ETH_MACECR_EIPGEN) >> 24) > 0U)
+ 8004da4:	683b      	ldr	r3, [r7, #0]
+ 8004da6:	f883 2038 	strb.w	r2, [r3, #56]	; 0x38
+  macconf->ExtendedInterPacketGapVal = READ_BIT(heth->Instance->MACECR, ETH_MACECR_EIPG) >> 25;
+ 8004daa:	687b      	ldr	r3, [r7, #4]
+ 8004dac:	681b      	ldr	r3, [r3, #0]
+ 8004dae:	685b      	ldr	r3, [r3, #4]
+ 8004db0:	0e5b      	lsrs	r3, r3, #25
+ 8004db2:	f003 021f 	and.w	r2, r3, #31
+ 8004db6:	683b      	ldr	r3, [r7, #0]
+ 8004db8:	63da      	str	r2, [r3, #60]	; 0x3c
+
+
+  macconf->ProgrammableWatchdog = ((READ_BIT(heth->Instance->MACWTR, ETH_MACWTR_PWE) >> 8) > 0U) ? ENABLE : DISABLE;
+ 8004dba:	687b      	ldr	r3, [r7, #4]
+ 8004dbc:	681b      	ldr	r3, [r3, #0]
+ 8004dbe:	68db      	ldr	r3, [r3, #12]
+ 8004dc0:	f403 7380 	and.w	r3, r3, #256	; 0x100
+ 8004dc4:	2b00      	cmp	r3, #0
+ 8004dc6:	bf14      	ite	ne
+ 8004dc8:	2301      	movne	r3, #1
+ 8004dca:	2300      	moveq	r3, #0
+ 8004dcc:	b2db      	uxtb	r3, r3
+ 8004dce:	461a      	mov	r2, r3
+ 8004dd0:	683b      	ldr	r3, [r7, #0]
+ 8004dd2:	f883 2040 	strb.w	r2, [r3, #64]	; 0x40
+  macconf->WatchdogTimeout = READ_BIT(heth->Instance->MACWTR, ETH_MACWTR_WTO);
+ 8004dd6:	687b      	ldr	r3, [r7, #4]
+ 8004dd8:	681b      	ldr	r3, [r3, #0]
+ 8004dda:	68db      	ldr	r3, [r3, #12]
+ 8004ddc:	f003 020f 	and.w	r2, r3, #15
+ 8004de0:	683b      	ldr	r3, [r7, #0]
+ 8004de2:	645a      	str	r2, [r3, #68]	; 0x44
+
+  macconf->TransmitFlowControl = ((READ_BIT(heth->Instance->MACTFCR, ETH_MACTFCR_TFE) >> 1) > 0U) ? ENABLE : DISABLE;
+ 8004de4:	687b      	ldr	r3, [r7, #4]
+ 8004de6:	681b      	ldr	r3, [r3, #0]
+ 8004de8:	6f1b      	ldr	r3, [r3, #112]	; 0x70
+ 8004dea:	f003 0302 	and.w	r3, r3, #2
+ 8004dee:	2b00      	cmp	r3, #0
+ 8004df0:	bf14      	ite	ne
+ 8004df2:	2301      	movne	r3, #1
+ 8004df4:	2300      	moveq	r3, #0
+ 8004df6:	b2db      	uxtb	r3, r3
+ 8004df8:	461a      	mov	r2, r3
+ 8004dfa:	683b      	ldr	r3, [r7, #0]
+ 8004dfc:	f883 2054 	strb.w	r2, [r3, #84]	; 0x54
+  macconf->ZeroQuantaPause = ((READ_BIT(heth->Instance->MACTFCR, ETH_MACTFCR_DZPQ) >> 7) == 0U) ? ENABLE : DISABLE;
+ 8004e00:	687b      	ldr	r3, [r7, #4]
+ 8004e02:	681b      	ldr	r3, [r3, #0]
+ 8004e04:	6f1b      	ldr	r3, [r3, #112]	; 0x70
+ 8004e06:	f003 0380 	and.w	r3, r3, #128	; 0x80
+ 8004e0a:	2b00      	cmp	r3, #0
+ 8004e0c:	bf0c      	ite	eq
+ 8004e0e:	2301      	moveq	r3, #1
+ 8004e10:	2300      	movne	r3, #0
+ 8004e12:	b2db      	uxtb	r3, r3
+ 8004e14:	461a      	mov	r2, r3
+ 8004e16:	683b      	ldr	r3, [r7, #0]
+ 8004e18:	f883 204c 	strb.w	r2, [r3, #76]	; 0x4c
+  macconf->PauseLowThreshold = READ_BIT(heth->Instance->MACTFCR, ETH_MACTFCR_PLT);
+ 8004e1c:	687b      	ldr	r3, [r7, #4]
+ 8004e1e:	681b      	ldr	r3, [r3, #0]
+ 8004e20:	6f1b      	ldr	r3, [r3, #112]	; 0x70
+ 8004e22:	f003 0270 	and.w	r2, r3, #112	; 0x70
+ 8004e26:	683b      	ldr	r3, [r7, #0]
+ 8004e28:	651a      	str	r2, [r3, #80]	; 0x50
+  macconf->PauseTime = (READ_BIT(heth->Instance->MACTFCR, ETH_MACTFCR_PT) >> 16);
+ 8004e2a:	687b      	ldr	r3, [r7, #4]
+ 8004e2c:	681b      	ldr	r3, [r3, #0]
+ 8004e2e:	6f1b      	ldr	r3, [r3, #112]	; 0x70
+ 8004e30:	0c1b      	lsrs	r3, r3, #16
+ 8004e32:	b29a      	uxth	r2, r3
+ 8004e34:	683b      	ldr	r3, [r7, #0]
+ 8004e36:	649a      	str	r2, [r3, #72]	; 0x48
+
+
+  macconf->ReceiveFlowControl = (READ_BIT(heth->Instance->MACRFCR, ETH_MACRFCR_RFE) > 0U) ? ENABLE : DISABLE;
+ 8004e38:	687b      	ldr	r3, [r7, #4]
+ 8004e3a:	681b      	ldr	r3, [r3, #0]
+ 8004e3c:	f8d3 3090 	ldr.w	r3, [r3, #144]	; 0x90
+ 8004e40:	f003 0301 	and.w	r3, r3, #1
+ 8004e44:	2b00      	cmp	r3, #0
+ 8004e46:	bf14      	ite	ne
+ 8004e48:	2301      	movne	r3, #1
+ 8004e4a:	2300      	moveq	r3, #0
+ 8004e4c:	b2db      	uxtb	r3, r3
+ 8004e4e:	461a      	mov	r2, r3
+ 8004e50:	683b      	ldr	r3, [r7, #0]
+ 8004e52:	f883 2056 	strb.w	r2, [r3, #86]	; 0x56
+  macconf->UnicastPausePacketDetect = ((READ_BIT(heth->Instance->MACRFCR, ETH_MACRFCR_UP) >> 1) > 0U)
+ 8004e56:	687b      	ldr	r3, [r7, #4]
+ 8004e58:	681b      	ldr	r3, [r3, #0]
+ 8004e5a:	f8d3 3090 	ldr.w	r3, [r3, #144]	; 0x90
+ 8004e5e:	f003 0302 	and.w	r3, r3, #2
+                                      ? ENABLE : DISABLE;
+ 8004e62:	2b00      	cmp	r3, #0
+ 8004e64:	bf14      	ite	ne
+ 8004e66:	2301      	movne	r3, #1
+ 8004e68:	2300      	moveq	r3, #0
+ 8004e6a:	b2db      	uxtb	r3, r3
+ 8004e6c:	461a      	mov	r2, r3
+  macconf->UnicastPausePacketDetect = ((READ_BIT(heth->Instance->MACRFCR, ETH_MACRFCR_UP) >> 1) > 0U)
+ 8004e6e:	683b      	ldr	r3, [r7, #0]
+ 8004e70:	f883 2055 	strb.w	r2, [r3, #85]	; 0x55
+
+  macconf->TransmitQueueMode = READ_BIT(heth->Instance->MTLTQOMR, (ETH_MTLTQOMR_TTC | ETH_MTLTQOMR_TSF));
+ 8004e74:	687b      	ldr	r3, [r7, #4]
+ 8004e76:	681b      	ldr	r3, [r3, #0]
+ 8004e78:	f8d3 3d00 	ldr.w	r3, [r3, #3328]	; 0xd00
+ 8004e7c:	f003 0272 	and.w	r2, r3, #114	; 0x72
+ 8004e80:	683b      	ldr	r3, [r7, #0]
+ 8004e82:	659a      	str	r2, [r3, #88]	; 0x58
+
+  macconf->ReceiveQueueMode = READ_BIT(heth->Instance->MTLRQOMR, (ETH_MTLRQOMR_RTC | ETH_MTLRQOMR_RSF));
+ 8004e84:	687b      	ldr	r3, [r7, #4]
+ 8004e86:	681b      	ldr	r3, [r3, #0]
+ 8004e88:	f8d3 3d30 	ldr.w	r3, [r3, #3376]	; 0xd30
+ 8004e8c:	f003 0223 	and.w	r2, r3, #35	; 0x23
+ 8004e90:	683b      	ldr	r3, [r7, #0]
+ 8004e92:	65da      	str	r2, [r3, #92]	; 0x5c
+  macconf->ForwardRxUndersizedGoodPacket = ((READ_BIT(heth->Instance->MTLRQOMR,
+ 8004e94:	687b      	ldr	r3, [r7, #4]
+ 8004e96:	681b      	ldr	r3, [r3, #0]
+ 8004e98:	f8d3 3d30 	ldr.w	r3, [r3, #3376]	; 0xd30
+                                                      ETH_MTLRQOMR_FUP) >> 3) > 0U) ? ENABLE : DISABLE;
+ 8004e9c:	f003 0308 	and.w	r3, r3, #8
+ 8004ea0:	2b00      	cmp	r3, #0
+ 8004ea2:	bf14      	ite	ne
+ 8004ea4:	2301      	movne	r3, #1
+ 8004ea6:	2300      	moveq	r3, #0
+ 8004ea8:	b2db      	uxtb	r3, r3
+ 8004eaa:	461a      	mov	r2, r3
+  macconf->ForwardRxUndersizedGoodPacket = ((READ_BIT(heth->Instance->MTLRQOMR,
+ 8004eac:	683b      	ldr	r3, [r7, #0]
+ 8004eae:	f883 2062 	strb.w	r2, [r3, #98]	; 0x62
+  macconf->ForwardRxErrorPacket = ((READ_BIT(heth->Instance->MTLRQOMR, ETH_MTLRQOMR_FEP) >> 4) > 0U) ? ENABLE : DISABLE;
+ 8004eb2:	687b      	ldr	r3, [r7, #4]
+ 8004eb4:	681b      	ldr	r3, [r3, #0]
+ 8004eb6:	f8d3 3d30 	ldr.w	r3, [r3, #3376]	; 0xd30
+ 8004eba:	f003 0310 	and.w	r3, r3, #16
+ 8004ebe:	2b00      	cmp	r3, #0
+ 8004ec0:	bf14      	ite	ne
+ 8004ec2:	2301      	movne	r3, #1
+ 8004ec4:	2300      	moveq	r3, #0
+ 8004ec6:	b2db      	uxtb	r3, r3
+ 8004ec8:	461a      	mov	r2, r3
+ 8004eca:	683b      	ldr	r3, [r7, #0]
+ 8004ecc:	f883 2061 	strb.w	r2, [r3, #97]	; 0x61
+  macconf->DropTCPIPChecksumErrorPacket = ((READ_BIT(heth->Instance->MTLRQOMR,
+ 8004ed0:	687b      	ldr	r3, [r7, #4]
+ 8004ed2:	681b      	ldr	r3, [r3, #0]
+ 8004ed4:	f8d3 3d30 	ldr.w	r3, [r3, #3376]	; 0xd30
+                                                     ETH_MTLRQOMR_DISTCPEF) >> 6) == 0U) ? ENABLE : DISABLE;
+ 8004ed8:	f003 0340 	and.w	r3, r3, #64	; 0x40
+ 8004edc:	2b00      	cmp	r3, #0
+ 8004ede:	bf0c      	ite	eq
+ 8004ee0:	2301      	moveq	r3, #1
+ 8004ee2:	2300      	movne	r3, #0
+ 8004ee4:	b2db      	uxtb	r3, r3
+ 8004ee6:	461a      	mov	r2, r3
+  macconf->DropTCPIPChecksumErrorPacket = ((READ_BIT(heth->Instance->MTLRQOMR,
+ 8004ee8:	683b      	ldr	r3, [r7, #0]
+ 8004eea:	f883 2060 	strb.w	r2, [r3, #96]	; 0x60
+
+  return HAL_OK;
+ 8004eee:	2300      	movs	r3, #0
+}
+ 8004ef0:	4618      	mov	r0, r3
+ 8004ef2:	370c      	adds	r7, #12
+ 8004ef4:	46bd      	mov	sp, r7
+ 8004ef6:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8004efa:	4770      	bx	lr
+
+08004efc <HAL_ETH_SetMACConfig>:
+  * @param  macconf: pointer to a ETH_MACConfigTypeDef structure that contains
+  *         the configuration of the MAC.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ETH_SetMACConfig(ETH_HandleTypeDef *heth,  ETH_MACConfigTypeDef *macconf)
+{
+ 8004efc:	b580      	push	{r7, lr}
+ 8004efe:	b082      	sub	sp, #8
+ 8004f00:	af00      	add	r7, sp, #0
+ 8004f02:	6078      	str	r0, [r7, #4]
+ 8004f04:	6039      	str	r1, [r7, #0]
+  if (macconf == NULL)
+ 8004f06:	683b      	ldr	r3, [r7, #0]
+ 8004f08:	2b00      	cmp	r3, #0
+ 8004f0a:	d101      	bne.n	8004f10 <HAL_ETH_SetMACConfig+0x14>
+  {
+    return HAL_ERROR;
+ 8004f0c:	2301      	movs	r3, #1
+ 8004f0e:	e00b      	b.n	8004f28 <HAL_ETH_SetMACConfig+0x2c>
+  }
+
+  if (heth->gState == HAL_ETH_STATE_READY)
+ 8004f10:	687b      	ldr	r3, [r7, #4]
+ 8004f12:	f8d3 3084 	ldr.w	r3, [r3, #132]	; 0x84
+ 8004f16:	2b10      	cmp	r3, #16
+ 8004f18:	d105      	bne.n	8004f26 <HAL_ETH_SetMACConfig+0x2a>
+  {
+    ETH_SetMACConfig(heth, macconf);
+ 8004f1a:	6839      	ldr	r1, [r7, #0]
+ 8004f1c:	6878      	ldr	r0, [r7, #4]
+ 8004f1e:	f000 f86d 	bl	8004ffc <ETH_SetMACConfig>
+
+    return HAL_OK;
+ 8004f22:	2300      	movs	r3, #0
+ 8004f24:	e000      	b.n	8004f28 <HAL_ETH_SetMACConfig+0x2c>
+  }
+  else
+  {
+    return HAL_ERROR;
+ 8004f26:	2301      	movs	r3, #1
+  }
+}
+ 8004f28:	4618      	mov	r0, r3
+ 8004f2a:	3708      	adds	r7, #8
+ 8004f2c:	46bd      	mov	sp, r7
+ 8004f2e:	bd80      	pop	{r7, pc}
+
+08004f30 <HAL_ETH_SetMDIOClockRange>:
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @retval None
+  */
+void HAL_ETH_SetMDIOClockRange(ETH_HandleTypeDef *heth)
+{
+ 8004f30:	b580      	push	{r7, lr}
+ 8004f32:	b084      	sub	sp, #16
+ 8004f34:	af00      	add	r7, sp, #0
+ 8004f36:	6078      	str	r0, [r7, #4]
+  uint32_t hclk;
+  uint32_t tmpreg;
+
+  /* Get the ETHERNET MACMDIOAR value */
+  tmpreg = (heth->Instance)->MACMDIOAR;
+ 8004f38:	687b      	ldr	r3, [r7, #4]
+ 8004f3a:	681b      	ldr	r3, [r3, #0]
+ 8004f3c:	f8d3 3200 	ldr.w	r3, [r3, #512]	; 0x200
+ 8004f40:	60fb      	str	r3, [r7, #12]
+
+  /* Clear CSR Clock Range bits */
+  tmpreg &= ~ETH_MACMDIOAR_CR;
+ 8004f42:	68fb      	ldr	r3, [r7, #12]
+ 8004f44:	f423 6370 	bic.w	r3, r3, #3840	; 0xf00
+ 8004f48:	60fb      	str	r3, [r7, #12]
+
+  /* Get hclk frequency value */
+  hclk = HAL_RCC_GetHCLKFreq();
+ 8004f4a:	f002 ffd9 	bl	8007f00 <HAL_RCC_GetHCLKFreq>
+ 8004f4e:	60b8      	str	r0, [r7, #8]
+
+  /* Set CR bits depending on hclk value */
+  if ((hclk >= 20000000U) && (hclk < 35000000U))
+ 8004f50:	68bb      	ldr	r3, [r7, #8]
+ 8004f52:	4a1e      	ldr	r2, [pc, #120]	; (8004fcc <HAL_ETH_SetMDIOClockRange+0x9c>)
+ 8004f54:	4293      	cmp	r3, r2
+ 8004f56:	d908      	bls.n	8004f6a <HAL_ETH_SetMDIOClockRange+0x3a>
+ 8004f58:	68bb      	ldr	r3, [r7, #8]
+ 8004f5a:	4a1d      	ldr	r2, [pc, #116]	; (8004fd0 <HAL_ETH_SetMDIOClockRange+0xa0>)
+ 8004f5c:	4293      	cmp	r3, r2
+ 8004f5e:	d804      	bhi.n	8004f6a <HAL_ETH_SetMDIOClockRange+0x3a>
+  {
+    /* CSR Clock Range between 20-35 MHz */
+    tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV16;
+ 8004f60:	68fb      	ldr	r3, [r7, #12]
+ 8004f62:	f443 7300 	orr.w	r3, r3, #512	; 0x200
+ 8004f66:	60fb      	str	r3, [r7, #12]
+ 8004f68:	e027      	b.n	8004fba <HAL_ETH_SetMDIOClockRange+0x8a>
+  }
+  else if ((hclk >= 35000000U) && (hclk < 60000000U))
+ 8004f6a:	68bb      	ldr	r3, [r7, #8]
+ 8004f6c:	4a18      	ldr	r2, [pc, #96]	; (8004fd0 <HAL_ETH_SetMDIOClockRange+0xa0>)
+ 8004f6e:	4293      	cmp	r3, r2
+ 8004f70:	d908      	bls.n	8004f84 <HAL_ETH_SetMDIOClockRange+0x54>
+ 8004f72:	68bb      	ldr	r3, [r7, #8]
+ 8004f74:	4a17      	ldr	r2, [pc, #92]	; (8004fd4 <HAL_ETH_SetMDIOClockRange+0xa4>)
+ 8004f76:	4293      	cmp	r3, r2
+ 8004f78:	d204      	bcs.n	8004f84 <HAL_ETH_SetMDIOClockRange+0x54>
+  {
+    /* CSR Clock Range between 35-60 MHz */
+    tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV26;
+ 8004f7a:	68fb      	ldr	r3, [r7, #12]
+ 8004f7c:	f443 7340 	orr.w	r3, r3, #768	; 0x300
+ 8004f80:	60fb      	str	r3, [r7, #12]
+ 8004f82:	e01a      	b.n	8004fba <HAL_ETH_SetMDIOClockRange+0x8a>
+  }
+  else if ((hclk >= 60000000U) && (hclk < 100000000U))
+ 8004f84:	68bb      	ldr	r3, [r7, #8]
+ 8004f86:	4a13      	ldr	r2, [pc, #76]	; (8004fd4 <HAL_ETH_SetMDIOClockRange+0xa4>)
+ 8004f88:	4293      	cmp	r3, r2
+ 8004f8a:	d303      	bcc.n	8004f94 <HAL_ETH_SetMDIOClockRange+0x64>
+ 8004f8c:	68bb      	ldr	r3, [r7, #8]
+ 8004f8e:	4a12      	ldr	r2, [pc, #72]	; (8004fd8 <HAL_ETH_SetMDIOClockRange+0xa8>)
+ 8004f90:	4293      	cmp	r3, r2
+ 8004f92:	d911      	bls.n	8004fb8 <HAL_ETH_SetMDIOClockRange+0x88>
+  {
+    /* CSR Clock Range between 60-100 MHz */
+    tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV42;
+  }
+  else if ((hclk >= 100000000U) && (hclk < 150000000U))
+ 8004f94:	68bb      	ldr	r3, [r7, #8]
+ 8004f96:	4a10      	ldr	r2, [pc, #64]	; (8004fd8 <HAL_ETH_SetMDIOClockRange+0xa8>)
+ 8004f98:	4293      	cmp	r3, r2
+ 8004f9a:	d908      	bls.n	8004fae <HAL_ETH_SetMDIOClockRange+0x7e>
+ 8004f9c:	68bb      	ldr	r3, [r7, #8]
+ 8004f9e:	4a0f      	ldr	r2, [pc, #60]	; (8004fdc <HAL_ETH_SetMDIOClockRange+0xac>)
+ 8004fa0:	4293      	cmp	r3, r2
+ 8004fa2:	d804      	bhi.n	8004fae <HAL_ETH_SetMDIOClockRange+0x7e>
+  {
+    /* CSR Clock Range between 100-150 MHz */
+    tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV62;
+ 8004fa4:	68fb      	ldr	r3, [r7, #12]
+ 8004fa6:	f443 7380 	orr.w	r3, r3, #256	; 0x100
+ 8004faa:	60fb      	str	r3, [r7, #12]
+ 8004fac:	e005      	b.n	8004fba <HAL_ETH_SetMDIOClockRange+0x8a>
+  }
+  else /* (hclk >= 150000000)&&(hclk <= 200000000) */
+  {
+    /* CSR Clock Range between 150-200 MHz */
+    tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV102;
+ 8004fae:	68fb      	ldr	r3, [r7, #12]
+ 8004fb0:	f443 6380 	orr.w	r3, r3, #1024	; 0x400
+ 8004fb4:	60fb      	str	r3, [r7, #12]
+ 8004fb6:	e000      	b.n	8004fba <HAL_ETH_SetMDIOClockRange+0x8a>
+    tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV42;
+ 8004fb8:	bf00      	nop
+  }
+
+  /* Configure the CSR Clock Range */
+  (heth->Instance)->MACMDIOAR = (uint32_t)tmpreg;
+ 8004fba:	687b      	ldr	r3, [r7, #4]
+ 8004fbc:	681b      	ldr	r3, [r3, #0]
+ 8004fbe:	68fa      	ldr	r2, [r7, #12]
+ 8004fc0:	f8c3 2200 	str.w	r2, [r3, #512]	; 0x200
+}
+ 8004fc4:	bf00      	nop
+ 8004fc6:	3710      	adds	r7, #16
+ 8004fc8:	46bd      	mov	sp, r7
+ 8004fca:	bd80      	pop	{r7, pc}
+ 8004fcc:	01312cff 	.word	0x01312cff
+ 8004fd0:	02160ebf 	.word	0x02160ebf
+ 8004fd4:	03938700 	.word	0x03938700
+ 8004fd8:	05f5e0ff 	.word	0x05f5e0ff
+ 8004fdc:	08f0d17f 	.word	0x08f0d17f
+
+08004fe0 <HAL_ETH_GetDMAError>:
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @retval ETH DMA Error Code
+  */
+uint32_t HAL_ETH_GetDMAError(ETH_HandleTypeDef *heth)
+{
+ 8004fe0:	b480      	push	{r7}
+ 8004fe2:	b083      	sub	sp, #12
+ 8004fe4:	af00      	add	r7, sp, #0
+ 8004fe6:	6078      	str	r0, [r7, #4]
+  return heth->DMAErrorCode;
+ 8004fe8:	687b      	ldr	r3, [r7, #4]
+ 8004fea:	f8d3 308c 	ldr.w	r3, [r3, #140]	; 0x8c
+}
+ 8004fee:	4618      	mov	r0, r3
+ 8004ff0:	370c      	adds	r7, #12
+ 8004ff2:	46bd      	mov	sp, r7
+ 8004ff4:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8004ff8:	4770      	bx	lr
+	...
+
+08004ffc <ETH_SetMACConfig>:
+  * @{
+  */
+
+
+static void ETH_SetMACConfig(ETH_HandleTypeDef *heth,  ETH_MACConfigTypeDef *macconf)
+{
+ 8004ffc:	b480      	push	{r7}
+ 8004ffe:	b085      	sub	sp, #20
+ 8005000:	af00      	add	r7, sp, #0
+ 8005002:	6078      	str	r0, [r7, #4]
+ 8005004:	6039      	str	r1, [r7, #0]
+  uint32_t macregval;
+
+  /*------------------------ MACCR Configuration --------------------*/
+  macregval = (macconf->InterPacketGapVal |
+ 8005006:	683b      	ldr	r3, [r7, #0]
+ 8005008:	689a      	ldr	r2, [r3, #8]
+               macconf->SourceAddrControl |
+ 800500a:	683b      	ldr	r3, [r7, #0]
+ 800500c:	681b      	ldr	r3, [r3, #0]
+  macregval = (macconf->InterPacketGapVal |
+ 800500e:	431a      	orrs	r2, r3
+               ((uint32_t)macconf->ChecksumOffload << 27) |
+ 8005010:	683b      	ldr	r3, [r7, #0]
+ 8005012:	791b      	ldrb	r3, [r3, #4]
+ 8005014:	06db      	lsls	r3, r3, #27
+               macconf->SourceAddrControl |
+ 8005016:	431a      	orrs	r2, r3
+               ((uint32_t)macconf->GiantPacketSizeLimitControl << 23) |
+ 8005018:	683b      	ldr	r3, [r7, #0]
+ 800501a:	7b1b      	ldrb	r3, [r3, #12]
+ 800501c:	05db      	lsls	r3, r3, #23
+               ((uint32_t)macconf->ChecksumOffload << 27) |
+ 800501e:	431a      	orrs	r2, r3
+               ((uint32_t)macconf->Support2KPacket  << 22) |
+ 8005020:	683b      	ldr	r3, [r7, #0]
+ 8005022:	7b5b      	ldrb	r3, [r3, #13]
+ 8005024:	059b      	lsls	r3, r3, #22
+               ((uint32_t)macconf->GiantPacketSizeLimitControl << 23) |
+ 8005026:	431a      	orrs	r2, r3
+               ((uint32_t)macconf->CRCStripTypePacket << 21) |
+ 8005028:	683b      	ldr	r3, [r7, #0]
+ 800502a:	7b9b      	ldrb	r3, [r3, #14]
+ 800502c:	055b      	lsls	r3, r3, #21
+               ((uint32_t)macconf->Support2KPacket  << 22) |
+ 800502e:	431a      	orrs	r2, r3
+               ((uint32_t)macconf->AutomaticPadCRCStrip << 20) |
+ 8005030:	683b      	ldr	r3, [r7, #0]
+ 8005032:	7bdb      	ldrb	r3, [r3, #15]
+ 8005034:	051b      	lsls	r3, r3, #20
+               ((uint32_t)macconf->CRCStripTypePacket << 21) |
+ 8005036:	4313      	orrs	r3, r2
+               ((uint32_t)((macconf->Watchdog == DISABLE) ? 1U : 0U) << 19) |
+ 8005038:	683a      	ldr	r2, [r7, #0]
+ 800503a:	7c12      	ldrb	r2, [r2, #16]
+ 800503c:	2a00      	cmp	r2, #0
+ 800503e:	d102      	bne.n	8005046 <ETH_SetMACConfig+0x4a>
+ 8005040:	f44f 2200 	mov.w	r2, #524288	; 0x80000
+ 8005044:	e000      	b.n	8005048 <ETH_SetMACConfig+0x4c>
+ 8005046:	2200      	movs	r2, #0
+               ((uint32_t)macconf->AutomaticPadCRCStrip << 20) |
+ 8005048:	4313      	orrs	r3, r2
+               ((uint32_t)((macconf->Jabber == DISABLE) ? 1U : 0U) << 17) |
+ 800504a:	683a      	ldr	r2, [r7, #0]
+ 800504c:	7c52      	ldrb	r2, [r2, #17]
+ 800504e:	2a00      	cmp	r2, #0
+ 8005050:	d102      	bne.n	8005058 <ETH_SetMACConfig+0x5c>
+ 8005052:	f44f 3200 	mov.w	r2, #131072	; 0x20000
+ 8005056:	e000      	b.n	800505a <ETH_SetMACConfig+0x5e>
+ 8005058:	2200      	movs	r2, #0
+               ((uint32_t)((macconf->Watchdog == DISABLE) ? 1U : 0U) << 19) |
+ 800505a:	431a      	orrs	r2, r3
+               ((uint32_t)macconf->JumboPacket << 16) |
+ 800505c:	683b      	ldr	r3, [r7, #0]
+ 800505e:	7c9b      	ldrb	r3, [r3, #18]
+ 8005060:	041b      	lsls	r3, r3, #16
+               ((uint32_t)((macconf->Jabber == DISABLE) ? 1U : 0U) << 17) |
+ 8005062:	431a      	orrs	r2, r3
+               macconf->Speed |
+ 8005064:	683b      	ldr	r3, [r7, #0]
+ 8005066:	695b      	ldr	r3, [r3, #20]
+               ((uint32_t)macconf->JumboPacket << 16) |
+ 8005068:	431a      	orrs	r2, r3
+               macconf->DuplexMode |
+ 800506a:	683b      	ldr	r3, [r7, #0]
+ 800506c:	699b      	ldr	r3, [r3, #24]
+               macconf->Speed |
+ 800506e:	431a      	orrs	r2, r3
+               ((uint32_t)macconf->LoopbackMode << 12) |
+ 8005070:	683b      	ldr	r3, [r7, #0]
+ 8005072:	7f1b      	ldrb	r3, [r3, #28]
+ 8005074:	031b      	lsls	r3, r3, #12
+               macconf->DuplexMode |
+ 8005076:	431a      	orrs	r2, r3
+               ((uint32_t)macconf->CarrierSenseBeforeTransmit << 11) |
+ 8005078:	683b      	ldr	r3, [r7, #0]
+ 800507a:	7f5b      	ldrb	r3, [r3, #29]
+ 800507c:	02db      	lsls	r3, r3, #11
+               ((uint32_t)macconf->LoopbackMode << 12) |
+ 800507e:	4313      	orrs	r3, r2
+               ((uint32_t)((macconf->ReceiveOwn == DISABLE) ? 1U : 0U) << 10) |
+ 8005080:	683a      	ldr	r2, [r7, #0]
+ 8005082:	7f92      	ldrb	r2, [r2, #30]
+ 8005084:	2a00      	cmp	r2, #0
+ 8005086:	d102      	bne.n	800508e <ETH_SetMACConfig+0x92>
+ 8005088:	f44f 6280 	mov.w	r2, #1024	; 0x400
+ 800508c:	e000      	b.n	8005090 <ETH_SetMACConfig+0x94>
+ 800508e:	2200      	movs	r2, #0
+               ((uint32_t)macconf->CarrierSenseBeforeTransmit << 11) |
+ 8005090:	431a      	orrs	r2, r3
+               ((uint32_t)macconf->CarrierSenseDuringTransmit << 9) |
+ 8005092:	683b      	ldr	r3, [r7, #0]
+ 8005094:	7fdb      	ldrb	r3, [r3, #31]
+ 8005096:	025b      	lsls	r3, r3, #9
+               ((uint32_t)((macconf->ReceiveOwn == DISABLE) ? 1U : 0U) << 10) |
+ 8005098:	4313      	orrs	r3, r2
+               ((uint32_t)((macconf->RetryTransmission == DISABLE) ? 1U : 0U) << 8) |
+ 800509a:	683a      	ldr	r2, [r7, #0]
+ 800509c:	f892 2020 	ldrb.w	r2, [r2, #32]
+ 80050a0:	2a00      	cmp	r2, #0
+ 80050a2:	d102      	bne.n	80050aa <ETH_SetMACConfig+0xae>
+ 80050a4:	f44f 7280 	mov.w	r2, #256	; 0x100
+ 80050a8:	e000      	b.n	80050ac <ETH_SetMACConfig+0xb0>
+ 80050aa:	2200      	movs	r2, #0
+               ((uint32_t)macconf->CarrierSenseDuringTransmit << 9) |
+ 80050ac:	431a      	orrs	r2, r3
+               macconf->BackOffLimit |
+ 80050ae:	683b      	ldr	r3, [r7, #0]
+ 80050b0:	6a5b      	ldr	r3, [r3, #36]	; 0x24
+               ((uint32_t)((macconf->RetryTransmission == DISABLE) ? 1U : 0U) << 8) |
+ 80050b2:	431a      	orrs	r2, r3
+               ((uint32_t)macconf->DeferralCheck << 4) |
+ 80050b4:	683b      	ldr	r3, [r7, #0]
+ 80050b6:	f893 3028 	ldrb.w	r3, [r3, #40]	; 0x28
+ 80050ba:	011b      	lsls	r3, r3, #4
+               macconf->BackOffLimit |
+ 80050bc:	431a      	orrs	r2, r3
+               macconf->PreambleLength);
+ 80050be:	683b      	ldr	r3, [r7, #0]
+ 80050c0:	6adb      	ldr	r3, [r3, #44]	; 0x2c
+  macregval = (macconf->InterPacketGapVal |
+ 80050c2:	4313      	orrs	r3, r2
+ 80050c4:	60fb      	str	r3, [r7, #12]
+
+  /* Write to MACCR */
+  MODIFY_REG(heth->Instance->MACCR, ETH_MACCR_MASK, macregval);
+ 80050c6:	687b      	ldr	r3, [r7, #4]
+ 80050c8:	681b      	ldr	r3, [r3, #0]
+ 80050ca:	681a      	ldr	r2, [r3, #0]
+ 80050cc:	4b56      	ldr	r3, [pc, #344]	; (8005228 <ETH_SetMACConfig+0x22c>)
+ 80050ce:	4013      	ands	r3, r2
+ 80050d0:	687a      	ldr	r2, [r7, #4]
+ 80050d2:	6812      	ldr	r2, [r2, #0]
+ 80050d4:	68f9      	ldr	r1, [r7, #12]
+ 80050d6:	430b      	orrs	r3, r1
+ 80050d8:	6013      	str	r3, [r2, #0]
+
+  /*------------------------ MACECR Configuration --------------------*/
+  macregval = ((macconf->ExtendedInterPacketGapVal << 25) |
+ 80050da:	683b      	ldr	r3, [r7, #0]
+ 80050dc:	6bdb      	ldr	r3, [r3, #60]	; 0x3c
+ 80050de:	065a      	lsls	r2, r3, #25
+               ((uint32_t)macconf->ExtendedInterPacketGap << 24) |
+ 80050e0:	683b      	ldr	r3, [r7, #0]
+ 80050e2:	f893 3038 	ldrb.w	r3, [r3, #56]	; 0x38
+ 80050e6:	061b      	lsls	r3, r3, #24
+  macregval = ((macconf->ExtendedInterPacketGapVal << 25) |
+ 80050e8:	431a      	orrs	r2, r3
+               ((uint32_t)macconf->UnicastSlowProtocolPacketDetect << 18) |
+ 80050ea:	683b      	ldr	r3, [r7, #0]
+ 80050ec:	f893 3030 	ldrb.w	r3, [r3, #48]	; 0x30
+ 80050f0:	049b      	lsls	r3, r3, #18
+               ((uint32_t)macconf->ExtendedInterPacketGap << 24) |
+ 80050f2:	431a      	orrs	r2, r3
+               ((uint32_t)macconf->SlowProtocolDetect << 17) |
+ 80050f4:	683b      	ldr	r3, [r7, #0]
+ 80050f6:	f893 3031 	ldrb.w	r3, [r3, #49]	; 0x31
+ 80050fa:	045b      	lsls	r3, r3, #17
+               ((uint32_t)macconf->UnicastSlowProtocolPacketDetect << 18) |
+ 80050fc:	4313      	orrs	r3, r2
+               ((uint32_t)((macconf->CRCCheckingRxPackets == DISABLE) ? 1U : 0U) << 16) |
+ 80050fe:	683a      	ldr	r2, [r7, #0]
+ 8005100:	f892 2032 	ldrb.w	r2, [r2, #50]	; 0x32
+ 8005104:	2a00      	cmp	r2, #0
+ 8005106:	d102      	bne.n	800510e <ETH_SetMACConfig+0x112>
+ 8005108:	f44f 3280 	mov.w	r2, #65536	; 0x10000
+ 800510c:	e000      	b.n	8005110 <ETH_SetMACConfig+0x114>
+ 800510e:	2200      	movs	r2, #0
+               ((uint32_t)macconf->SlowProtocolDetect << 17) |
+ 8005110:	431a      	orrs	r2, r3
+               macconf->GiantPacketSizeLimit);
+ 8005112:	683b      	ldr	r3, [r7, #0]
+ 8005114:	6b5b      	ldr	r3, [r3, #52]	; 0x34
+  macregval = ((macconf->ExtendedInterPacketGapVal << 25) |
+ 8005116:	4313      	orrs	r3, r2
+ 8005118:	60fb      	str	r3, [r7, #12]
+
+  /* Write to MACECR */
+  MODIFY_REG(heth->Instance->MACECR, ETH_MACECR_MASK, macregval);
+ 800511a:	687b      	ldr	r3, [r7, #4]
+ 800511c:	681b      	ldr	r3, [r3, #0]
+ 800511e:	685a      	ldr	r2, [r3, #4]
+ 8005120:	4b42      	ldr	r3, [pc, #264]	; (800522c <ETH_SetMACConfig+0x230>)
+ 8005122:	4013      	ands	r3, r2
+ 8005124:	687a      	ldr	r2, [r7, #4]
+ 8005126:	6812      	ldr	r2, [r2, #0]
+ 8005128:	68f9      	ldr	r1, [r7, #12]
+ 800512a:	430b      	orrs	r3, r1
+ 800512c:	6053      	str	r3, [r2, #4]
+
+  /*------------------------ MACWTR Configuration --------------------*/
+  macregval = (((uint32_t)macconf->ProgrammableWatchdog << 8) |
+ 800512e:	683b      	ldr	r3, [r7, #0]
+ 8005130:	f893 3040 	ldrb.w	r3, [r3, #64]	; 0x40
+ 8005134:	021a      	lsls	r2, r3, #8
+               macconf->WatchdogTimeout);
+ 8005136:	683b      	ldr	r3, [r7, #0]
+ 8005138:	6c5b      	ldr	r3, [r3, #68]	; 0x44
+  macregval = (((uint32_t)macconf->ProgrammableWatchdog << 8) |
+ 800513a:	4313      	orrs	r3, r2
+ 800513c:	60fb      	str	r3, [r7, #12]
+
+  /* Write to MACWTR */
+  MODIFY_REG(heth->Instance->MACWTR, ETH_MACWTR_MASK, macregval);
+ 800513e:	687b      	ldr	r3, [r7, #4]
+ 8005140:	681b      	ldr	r3, [r3, #0]
+ 8005142:	68da      	ldr	r2, [r3, #12]
+ 8005144:	4b3a      	ldr	r3, [pc, #232]	; (8005230 <ETH_SetMACConfig+0x234>)
+ 8005146:	4013      	ands	r3, r2
+ 8005148:	687a      	ldr	r2, [r7, #4]
+ 800514a:	6812      	ldr	r2, [r2, #0]
+ 800514c:	68f9      	ldr	r1, [r7, #12]
+ 800514e:	430b      	orrs	r3, r1
+ 8005150:	60d3      	str	r3, [r2, #12]
+
+  /*------------------------ MACTFCR Configuration --------------------*/
+  macregval = (((uint32_t)macconf->TransmitFlowControl << 1) |
+ 8005152:	683b      	ldr	r3, [r7, #0]
+ 8005154:	f893 3054 	ldrb.w	r3, [r3, #84]	; 0x54
+ 8005158:	005a      	lsls	r2, r3, #1
+               macconf->PauseLowThreshold |
+ 800515a:	683b      	ldr	r3, [r7, #0]
+ 800515c:	6d1b      	ldr	r3, [r3, #80]	; 0x50
+  macregval = (((uint32_t)macconf->TransmitFlowControl << 1) |
+ 800515e:	4313      	orrs	r3, r2
+               ((uint32_t)((macconf->ZeroQuantaPause == DISABLE) ? 1U : 0U) << 7) |
+ 8005160:	683a      	ldr	r2, [r7, #0]
+ 8005162:	f892 204c 	ldrb.w	r2, [r2, #76]	; 0x4c
+ 8005166:	2a00      	cmp	r2, #0
+ 8005168:	d101      	bne.n	800516e <ETH_SetMACConfig+0x172>
+ 800516a:	2280      	movs	r2, #128	; 0x80
+ 800516c:	e000      	b.n	8005170 <ETH_SetMACConfig+0x174>
+ 800516e:	2200      	movs	r2, #0
+               macconf->PauseLowThreshold |
+ 8005170:	431a      	orrs	r2, r3
+               (macconf->PauseTime << 16));
+ 8005172:	683b      	ldr	r3, [r7, #0]
+ 8005174:	6c9b      	ldr	r3, [r3, #72]	; 0x48
+ 8005176:	041b      	lsls	r3, r3, #16
+  macregval = (((uint32_t)macconf->TransmitFlowControl << 1) |
+ 8005178:	4313      	orrs	r3, r2
+ 800517a:	60fb      	str	r3, [r7, #12]
+
+  /* Write to MACTFCR */
+  MODIFY_REG(heth->Instance->MACTFCR, ETH_MACTFCR_MASK, macregval);
+ 800517c:	687b      	ldr	r3, [r7, #4]
+ 800517e:	681b      	ldr	r3, [r3, #0]
+ 8005180:	6f1a      	ldr	r2, [r3, #112]	; 0x70
+ 8005182:	f64f 730d 	movw	r3, #65293	; 0xff0d
+ 8005186:	4013      	ands	r3, r2
+ 8005188:	687a      	ldr	r2, [r7, #4]
+ 800518a:	6812      	ldr	r2, [r2, #0]
+ 800518c:	68f9      	ldr	r1, [r7, #12]
+ 800518e:	430b      	orrs	r3, r1
+ 8005190:	6713      	str	r3, [r2, #112]	; 0x70
+
+  /*------------------------ MACRFCR Configuration --------------------*/
+  macregval = ((uint32_t)macconf->ReceiveFlowControl |
+ 8005192:	683b      	ldr	r3, [r7, #0]
+ 8005194:	f893 3056 	ldrb.w	r3, [r3, #86]	; 0x56
+ 8005198:	461a      	mov	r2, r3
+               ((uint32_t)macconf->UnicastPausePacketDetect << 1));
+ 800519a:	683b      	ldr	r3, [r7, #0]
+ 800519c:	f893 3055 	ldrb.w	r3, [r3, #85]	; 0x55
+ 80051a0:	005b      	lsls	r3, r3, #1
+  macregval = ((uint32_t)macconf->ReceiveFlowControl |
+ 80051a2:	4313      	orrs	r3, r2
+ 80051a4:	60fb      	str	r3, [r7, #12]
+
+  /* Write to MACRFCR */
+  MODIFY_REG(heth->Instance->MACRFCR, ETH_MACRFCR_MASK, macregval);
+ 80051a6:	687b      	ldr	r3, [r7, #4]
+ 80051a8:	681b      	ldr	r3, [r3, #0]
+ 80051aa:	f8d3 3090 	ldr.w	r3, [r3, #144]	; 0x90
+ 80051ae:	f023 0103 	bic.w	r1, r3, #3
+ 80051b2:	687b      	ldr	r3, [r7, #4]
+ 80051b4:	681b      	ldr	r3, [r3, #0]
+ 80051b6:	68fa      	ldr	r2, [r7, #12]
+ 80051b8:	430a      	orrs	r2, r1
+ 80051ba:	f8c3 2090 	str.w	r2, [r3, #144]	; 0x90
+
+  /*------------------------ MTLTQOMR Configuration --------------------*/
+  /* Write to MTLTQOMR */
+  MODIFY_REG(heth->Instance->MTLTQOMR, ETH_MTLTQOMR_MASK, macconf->TransmitQueueMode);
+ 80051be:	687b      	ldr	r3, [r7, #4]
+ 80051c0:	681b      	ldr	r3, [r3, #0]
+ 80051c2:	f8d3 3d00 	ldr.w	r3, [r3, #3328]	; 0xd00
+ 80051c6:	f023 0172 	bic.w	r1, r3, #114	; 0x72
+ 80051ca:	683b      	ldr	r3, [r7, #0]
+ 80051cc:	6d9a      	ldr	r2, [r3, #88]	; 0x58
+ 80051ce:	687b      	ldr	r3, [r7, #4]
+ 80051d0:	681b      	ldr	r3, [r3, #0]
+ 80051d2:	430a      	orrs	r2, r1
+ 80051d4:	f8c3 2d00 	str.w	r2, [r3, #3328]	; 0xd00
+
+  /*------------------------ MTLRQOMR Configuration --------------------*/
+  macregval = (macconf->ReceiveQueueMode |
+ 80051d8:	683b      	ldr	r3, [r7, #0]
+ 80051da:	6ddb      	ldr	r3, [r3, #92]	; 0x5c
+               ((uint32_t)((macconf->DropTCPIPChecksumErrorPacket == DISABLE) ? 1U : 0U) << 6) |
+ 80051dc:	683a      	ldr	r2, [r7, #0]
+ 80051de:	f892 2060 	ldrb.w	r2, [r2, #96]	; 0x60
+ 80051e2:	2a00      	cmp	r2, #0
+ 80051e4:	d101      	bne.n	80051ea <ETH_SetMACConfig+0x1ee>
+ 80051e6:	2240      	movs	r2, #64	; 0x40
+ 80051e8:	e000      	b.n	80051ec <ETH_SetMACConfig+0x1f0>
+ 80051ea:	2200      	movs	r2, #0
+  macregval = (macconf->ReceiveQueueMode |
+ 80051ec:	431a      	orrs	r2, r3
+               ((uint32_t)macconf->ForwardRxErrorPacket << 4) |
+ 80051ee:	683b      	ldr	r3, [r7, #0]
+ 80051f0:	f893 3061 	ldrb.w	r3, [r3, #97]	; 0x61
+ 80051f4:	011b      	lsls	r3, r3, #4
+               ((uint32_t)((macconf->DropTCPIPChecksumErrorPacket == DISABLE) ? 1U : 0U) << 6) |
+ 80051f6:	431a      	orrs	r2, r3
+               ((uint32_t)macconf->ForwardRxUndersizedGoodPacket << 3));
+ 80051f8:	683b      	ldr	r3, [r7, #0]
+ 80051fa:	f893 3062 	ldrb.w	r3, [r3, #98]	; 0x62
+ 80051fe:	00db      	lsls	r3, r3, #3
+  macregval = (macconf->ReceiveQueueMode |
+ 8005200:	4313      	orrs	r3, r2
+ 8005202:	60fb      	str	r3, [r7, #12]
+
+  /* Write to MTLRQOMR */
+  MODIFY_REG(heth->Instance->MTLRQOMR, ETH_MTLRQOMR_MASK, macregval);
+ 8005204:	687b      	ldr	r3, [r7, #4]
+ 8005206:	681b      	ldr	r3, [r3, #0]
+ 8005208:	f8d3 3d30 	ldr.w	r3, [r3, #3376]	; 0xd30
+ 800520c:	f023 017b 	bic.w	r1, r3, #123	; 0x7b
+ 8005210:	687b      	ldr	r3, [r7, #4]
+ 8005212:	681b      	ldr	r3, [r3, #0]
+ 8005214:	68fa      	ldr	r2, [r7, #12]
+ 8005216:	430a      	orrs	r2, r1
+ 8005218:	f8c3 2d30 	str.w	r2, [r3, #3376]	; 0xd30
+}
+ 800521c:	bf00      	nop
+ 800521e:	3714      	adds	r7, #20
+ 8005220:	46bd      	mov	sp, r7
+ 8005222:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8005226:	4770      	bx	lr
+ 8005228:	00048083 	.word	0x00048083
+ 800522c:	c0f88000 	.word	0xc0f88000
+ 8005230:	fffffef0 	.word	0xfffffef0
+
+08005234 <ETH_SetDMAConfig>:
+
+static void ETH_SetDMAConfig(ETH_HandleTypeDef *heth,  ETH_DMAConfigTypeDef *dmaconf)
+{
+ 8005234:	b480      	push	{r7}
+ 8005236:	b085      	sub	sp, #20
+ 8005238:	af00      	add	r7, sp, #0
+ 800523a:	6078      	str	r0, [r7, #4]
+ 800523c:	6039      	str	r1, [r7, #0]
+  uint32_t dmaregval;
+
+  /*------------------------ DMAMR Configuration --------------------*/
+  MODIFY_REG(heth->Instance->DMAMR, ETH_DMAMR_MASK, dmaconf->DMAArbitration);
+ 800523e:	687b      	ldr	r3, [r7, #4]
+ 8005240:	681b      	ldr	r3, [r3, #0]
+ 8005242:	f503 5380 	add.w	r3, r3, #4096	; 0x1000
+ 8005246:	681a      	ldr	r2, [r3, #0]
+ 8005248:	4b38      	ldr	r3, [pc, #224]	; (800532c <ETH_SetDMAConfig+0xf8>)
+ 800524a:	4013      	ands	r3, r2
+ 800524c:	683a      	ldr	r2, [r7, #0]
+ 800524e:	6811      	ldr	r1, [r2, #0]
+ 8005250:	687a      	ldr	r2, [r7, #4]
+ 8005252:	6812      	ldr	r2, [r2, #0]
+ 8005254:	430b      	orrs	r3, r1
+ 8005256:	f502 5280 	add.w	r2, r2, #4096	; 0x1000
+ 800525a:	6013      	str	r3, [r2, #0]
+
+  /*------------------------ DMASBMR Configuration --------------------*/
+  dmaregval = (((uint32_t)dmaconf->AddressAlignedBeats << 12) |
+ 800525c:	683b      	ldr	r3, [r7, #0]
+ 800525e:	791b      	ldrb	r3, [r3, #4]
+ 8005260:	031a      	lsls	r2, r3, #12
+               dmaconf->BurstMode |
+ 8005262:	683b      	ldr	r3, [r7, #0]
+ 8005264:	689b      	ldr	r3, [r3, #8]
+  dmaregval = (((uint32_t)dmaconf->AddressAlignedBeats << 12) |
+ 8005266:	431a      	orrs	r2, r3
+               ((uint32_t)dmaconf->RebuildINCRxBurst << 15));
+ 8005268:	683b      	ldr	r3, [r7, #0]
+ 800526a:	7b1b      	ldrb	r3, [r3, #12]
+ 800526c:	03db      	lsls	r3, r3, #15
+  dmaregval = (((uint32_t)dmaconf->AddressAlignedBeats << 12) |
+ 800526e:	4313      	orrs	r3, r2
+ 8005270:	60fb      	str	r3, [r7, #12]
+
+  MODIFY_REG(heth->Instance->DMASBMR, ETH_DMASBMR_MASK, dmaregval);
+ 8005272:	687b      	ldr	r3, [r7, #4]
+ 8005274:	681b      	ldr	r3, [r3, #0]
+ 8005276:	f503 5380 	add.w	r3, r3, #4096	; 0x1000
+ 800527a:	685a      	ldr	r2, [r3, #4]
+ 800527c:	4b2c      	ldr	r3, [pc, #176]	; (8005330 <ETH_SetDMAConfig+0xfc>)
+ 800527e:	4013      	ands	r3, r2
+ 8005280:	687a      	ldr	r2, [r7, #4]
+ 8005282:	6812      	ldr	r2, [r2, #0]
+ 8005284:	68f9      	ldr	r1, [r7, #12]
+ 8005286:	430b      	orrs	r3, r1
+ 8005288:	f502 5280 	add.w	r2, r2, #4096	; 0x1000
+ 800528c:	6053      	str	r3, [r2, #4]
+
+  /*------------------------ DMACCR Configuration --------------------*/
+  dmaregval = (((uint32_t)dmaconf->PBLx8Mode << 16) |
+ 800528e:	683b      	ldr	r3, [r7, #0]
+ 8005290:	7b5b      	ldrb	r3, [r3, #13]
+ 8005292:	041a      	lsls	r2, r3, #16
+               dmaconf->MaximumSegmentSize);
+ 8005294:	683b      	ldr	r3, [r7, #0]
+ 8005296:	6a1b      	ldr	r3, [r3, #32]
+  dmaregval = (((uint32_t)dmaconf->PBLx8Mode << 16) |
+ 8005298:	4313      	orrs	r3, r2
+ 800529a:	60fb      	str	r3, [r7, #12]
+
+  MODIFY_REG(heth->Instance->DMACCR, ETH_DMACCR_MASK, dmaregval);
+ 800529c:	687b      	ldr	r3, [r7, #4]
+ 800529e:	681b      	ldr	r3, [r3, #0]
+ 80052a0:	f503 5380 	add.w	r3, r3, #4096	; 0x1000
+ 80052a4:	f8d3 2100 	ldr.w	r2, [r3, #256]	; 0x100
+ 80052a8:	4b22      	ldr	r3, [pc, #136]	; (8005334 <ETH_SetDMAConfig+0x100>)
+ 80052aa:	4013      	ands	r3, r2
+ 80052ac:	687a      	ldr	r2, [r7, #4]
+ 80052ae:	6812      	ldr	r2, [r2, #0]
+ 80052b0:	68f9      	ldr	r1, [r7, #12]
+ 80052b2:	430b      	orrs	r3, r1
+ 80052b4:	f502 5280 	add.w	r2, r2, #4096	; 0x1000
+ 80052b8:	f8c2 3100 	str.w	r3, [r2, #256]	; 0x100
+
+  /*------------------------ DMACTCR Configuration --------------------*/
+  dmaregval = (dmaconf->TxDMABurstLength |
+ 80052bc:	683b      	ldr	r3, [r7, #0]
+ 80052be:	691a      	ldr	r2, [r3, #16]
+               ((uint32_t)dmaconf->SecondPacketOperate << 4) |
+ 80052c0:	683b      	ldr	r3, [r7, #0]
+ 80052c2:	7d1b      	ldrb	r3, [r3, #20]
+ 80052c4:	011b      	lsls	r3, r3, #4
+  dmaregval = (dmaconf->TxDMABurstLength |
+ 80052c6:	431a      	orrs	r2, r3
+               ((uint32_t)dmaconf->TCPSegmentation << 12));
+ 80052c8:	683b      	ldr	r3, [r7, #0]
+ 80052ca:	7f5b      	ldrb	r3, [r3, #29]
+ 80052cc:	031b      	lsls	r3, r3, #12
+  dmaregval = (dmaconf->TxDMABurstLength |
+ 80052ce:	4313      	orrs	r3, r2
+ 80052d0:	60fb      	str	r3, [r7, #12]
+
+  MODIFY_REG(heth->Instance->DMACTCR, ETH_DMACTCR_MASK, dmaregval);
+ 80052d2:	687b      	ldr	r3, [r7, #4]
+ 80052d4:	681b      	ldr	r3, [r3, #0]
+ 80052d6:	f503 5380 	add.w	r3, r3, #4096	; 0x1000
+ 80052da:	f8d3 2104 	ldr.w	r2, [r3, #260]	; 0x104
+ 80052de:	4b16      	ldr	r3, [pc, #88]	; (8005338 <ETH_SetDMAConfig+0x104>)
+ 80052e0:	4013      	ands	r3, r2
+ 80052e2:	687a      	ldr	r2, [r7, #4]
+ 80052e4:	6812      	ldr	r2, [r2, #0]
+ 80052e6:	68f9      	ldr	r1, [r7, #12]
+ 80052e8:	430b      	orrs	r3, r1
+ 80052ea:	f502 5280 	add.w	r2, r2, #4096	; 0x1000
+ 80052ee:	f8c2 3104 	str.w	r3, [r2, #260]	; 0x104
+
+  /*------------------------ DMACRCR Configuration --------------------*/
+  dmaregval = (((uint32_t)dmaconf->FlushRxPacket  << 31) |
+ 80052f2:	683b      	ldr	r3, [r7, #0]
+ 80052f4:	7f1b      	ldrb	r3, [r3, #28]
+ 80052f6:	07da      	lsls	r2, r3, #31
+               dmaconf->RxDMABurstLength);
+ 80052f8:	683b      	ldr	r3, [r7, #0]
+ 80052fa:	699b      	ldr	r3, [r3, #24]
+  dmaregval = (((uint32_t)dmaconf->FlushRxPacket  << 31) |
+ 80052fc:	4313      	orrs	r3, r2
+ 80052fe:	60fb      	str	r3, [r7, #12]
+
+  /* Write to DMACRCR */
+  MODIFY_REG(heth->Instance->DMACRCR, ETH_DMACRCR_MASK, dmaregval);
+ 8005300:	687b      	ldr	r3, [r7, #4]
+ 8005302:	681b      	ldr	r3, [r3, #0]
+ 8005304:	f503 5380 	add.w	r3, r3, #4096	; 0x1000
+ 8005308:	f8d3 2108 	ldr.w	r2, [r3, #264]	; 0x108
+ 800530c:	4b0b      	ldr	r3, [pc, #44]	; (800533c <ETH_SetDMAConfig+0x108>)
+ 800530e:	4013      	ands	r3, r2
+ 8005310:	687a      	ldr	r2, [r7, #4]
+ 8005312:	6812      	ldr	r2, [r2, #0]
+ 8005314:	68f9      	ldr	r1, [r7, #12]
+ 8005316:	430b      	orrs	r3, r1
+ 8005318:	f502 5280 	add.w	r2, r2, #4096	; 0x1000
+ 800531c:	f8c2 3108 	str.w	r3, [r2, #264]	; 0x108
+}
+ 8005320:	bf00      	nop
+ 8005322:	3714      	adds	r7, #20
+ 8005324:	46bd      	mov	sp, r7
+ 8005326:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 800532a:	4770      	bx	lr
+ 800532c:	ffff87fd 	.word	0xffff87fd
+ 8005330:	ffff2ffe 	.word	0xffff2ffe
+ 8005334:	fffec000 	.word	0xfffec000
+ 8005338:	ffc0efef 	.word	0xffc0efef
+ 800533c:	7fc0ffff 	.word	0x7fc0ffff
+
+08005340 <ETH_MACDMAConfig>:
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @retval HAL status
+  */
+static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth)
+{
+ 8005340:	b580      	push	{r7, lr}
+ 8005342:	b0a4      	sub	sp, #144	; 0x90
+ 8005344:	af00      	add	r7, sp, #0
+ 8005346:	6078      	str	r0, [r7, #4]
+  ETH_MACConfigTypeDef macDefaultConf;
+  ETH_DMAConfigTypeDef dmaDefaultConf;
+
+  /*--------------- ETHERNET MAC registers default Configuration --------------*/
+  macDefaultConf.AutomaticPadCRCStrip = ENABLE;
+ 8005348:	2301      	movs	r3, #1
+ 800534a:	f887 303b 	strb.w	r3, [r7, #59]	; 0x3b
+  macDefaultConf.BackOffLimit = ETH_BACKOFFLIMIT_10;
+ 800534e:	2300      	movs	r3, #0
+ 8005350:	653b      	str	r3, [r7, #80]	; 0x50
+  macDefaultConf.CarrierSenseBeforeTransmit = DISABLE;
+ 8005352:	2300      	movs	r3, #0
+ 8005354:	f887 3049 	strb.w	r3, [r7, #73]	; 0x49
+  macDefaultConf.CarrierSenseDuringTransmit = DISABLE;
+ 8005358:	2300      	movs	r3, #0
+ 800535a:	f887 304b 	strb.w	r3, [r7, #75]	; 0x4b
+  macDefaultConf.ChecksumOffload = ENABLE;
+ 800535e:	2301      	movs	r3, #1
+ 8005360:	f887 3030 	strb.w	r3, [r7, #48]	; 0x30
+  macDefaultConf.CRCCheckingRxPackets = ENABLE;
+ 8005364:	2301      	movs	r3, #1
+ 8005366:	f887 305e 	strb.w	r3, [r7, #94]	; 0x5e
+  macDefaultConf.CRCStripTypePacket = ENABLE;
+ 800536a:	2301      	movs	r3, #1
+ 800536c:	f887 303a 	strb.w	r3, [r7, #58]	; 0x3a
+  macDefaultConf.DeferralCheck = DISABLE;
+ 8005370:	2300      	movs	r3, #0
+ 8005372:	f887 3054 	strb.w	r3, [r7, #84]	; 0x54
+  macDefaultConf.DropTCPIPChecksumErrorPacket = ENABLE;
+ 8005376:	2301      	movs	r3, #1
+ 8005378:	f887 308c 	strb.w	r3, [r7, #140]	; 0x8c
+  macDefaultConf.DuplexMode = ETH_FULLDUPLEX_MODE;
+ 800537c:	f44f 5300 	mov.w	r3, #8192	; 0x2000
+ 8005380:	647b      	str	r3, [r7, #68]	; 0x44
+  macDefaultConf.ExtendedInterPacketGap = DISABLE;
+ 8005382:	2300      	movs	r3, #0
+ 8005384:	f887 3064 	strb.w	r3, [r7, #100]	; 0x64
+  macDefaultConf.ExtendedInterPacketGapVal = 0x0;
+ 8005388:	2300      	movs	r3, #0
+ 800538a:	66bb      	str	r3, [r7, #104]	; 0x68
+  macDefaultConf.ForwardRxErrorPacket = DISABLE;
+ 800538c:	2300      	movs	r3, #0
+ 800538e:	f887 308d 	strb.w	r3, [r7, #141]	; 0x8d
+  macDefaultConf.ForwardRxUndersizedGoodPacket = DISABLE;
+ 8005392:	2300      	movs	r3, #0
+ 8005394:	f887 308e 	strb.w	r3, [r7, #142]	; 0x8e
+  macDefaultConf.GiantPacketSizeLimit = 0x618;
+ 8005398:	f44f 63c3 	mov.w	r3, #1560	; 0x618
+ 800539c:	663b      	str	r3, [r7, #96]	; 0x60
+  macDefaultConf.GiantPacketSizeLimitControl = DISABLE;
+ 800539e:	2300      	movs	r3, #0
+ 80053a0:	f887 3038 	strb.w	r3, [r7, #56]	; 0x38
+  macDefaultConf.InterPacketGapVal = ETH_INTERPACKETGAP_96BIT;
+ 80053a4:	2300      	movs	r3, #0
+ 80053a6:	637b      	str	r3, [r7, #52]	; 0x34
+  macDefaultConf.Jabber = ENABLE;
+ 80053a8:	2301      	movs	r3, #1
+ 80053aa:	f887 303d 	strb.w	r3, [r7, #61]	; 0x3d
+  macDefaultConf.JumboPacket = DISABLE;
+ 80053ae:	2300      	movs	r3, #0
+ 80053b0:	f887 303e 	strb.w	r3, [r7, #62]	; 0x3e
+  macDefaultConf.LoopbackMode = DISABLE;
+ 80053b4:	2300      	movs	r3, #0
+ 80053b6:	f887 3048 	strb.w	r3, [r7, #72]	; 0x48
+  macDefaultConf.PauseLowThreshold = ETH_PAUSELOWTHRESHOLD_MINUS_4;
+ 80053ba:	2300      	movs	r3, #0
+ 80053bc:	67fb      	str	r3, [r7, #124]	; 0x7c
+  macDefaultConf.PauseTime = 0x0;
+ 80053be:	2300      	movs	r3, #0
+ 80053c0:	677b      	str	r3, [r7, #116]	; 0x74
+  macDefaultConf.PreambleLength = ETH_PREAMBLELENGTH_7;
+ 80053c2:	2300      	movs	r3, #0
+ 80053c4:	65bb      	str	r3, [r7, #88]	; 0x58
+  macDefaultConf.ProgrammableWatchdog = DISABLE;
+ 80053c6:	2300      	movs	r3, #0
+ 80053c8:	f887 306c 	strb.w	r3, [r7, #108]	; 0x6c
+  macDefaultConf.ReceiveFlowControl = DISABLE;
+ 80053cc:	2300      	movs	r3, #0
+ 80053ce:	f887 3082 	strb.w	r3, [r7, #130]	; 0x82
+  macDefaultConf.ReceiveOwn = ENABLE;
+ 80053d2:	2301      	movs	r3, #1
+ 80053d4:	f887 304a 	strb.w	r3, [r7, #74]	; 0x4a
+  macDefaultConf.ReceiveQueueMode = ETH_RECEIVESTOREFORWARD;
+ 80053d8:	2320      	movs	r3, #32
+ 80053da:	f8c7 3088 	str.w	r3, [r7, #136]	; 0x88
+  macDefaultConf.RetryTransmission = ENABLE;
+ 80053de:	2301      	movs	r3, #1
+ 80053e0:	f887 304c 	strb.w	r3, [r7, #76]	; 0x4c
+  macDefaultConf.SlowProtocolDetect = DISABLE;
+ 80053e4:	2300      	movs	r3, #0
+ 80053e6:	f887 305d 	strb.w	r3, [r7, #93]	; 0x5d
+  macDefaultConf.SourceAddrControl = ETH_SOURCEADDRESS_REPLACE_ADDR0;
+ 80053ea:	f04f 5340 	mov.w	r3, #805306368	; 0x30000000
+ 80053ee:	62fb      	str	r3, [r7, #44]	; 0x2c
+  macDefaultConf.Speed = ETH_SPEED_100M;
+ 80053f0:	f44f 4380 	mov.w	r3, #16384	; 0x4000
+ 80053f4:	643b      	str	r3, [r7, #64]	; 0x40
+  macDefaultConf.Support2KPacket = DISABLE;
+ 80053f6:	2300      	movs	r3, #0
+ 80053f8:	f887 3039 	strb.w	r3, [r7, #57]	; 0x39
+  macDefaultConf.TransmitQueueMode = ETH_TRANSMITSTOREFORWARD;
+ 80053fc:	2302      	movs	r3, #2
+ 80053fe:	f8c7 3084 	str.w	r3, [r7, #132]	; 0x84
+  macDefaultConf.TransmitFlowControl = DISABLE;
+ 8005402:	2300      	movs	r3, #0
+ 8005404:	f887 3080 	strb.w	r3, [r7, #128]	; 0x80
+  macDefaultConf.UnicastPausePacketDetect = DISABLE;
+ 8005408:	2300      	movs	r3, #0
+ 800540a:	f887 3081 	strb.w	r3, [r7, #129]	; 0x81
+  macDefaultConf.UnicastSlowProtocolPacketDetect = DISABLE;
+ 800540e:	2300      	movs	r3, #0
+ 8005410:	f887 305c 	strb.w	r3, [r7, #92]	; 0x5c
+  macDefaultConf.Watchdog = ENABLE;
+ 8005414:	2301      	movs	r3, #1
+ 8005416:	f887 303c 	strb.w	r3, [r7, #60]	; 0x3c
+  macDefaultConf.WatchdogTimeout =  ETH_MACWTR_WTO_2KB;
+ 800541a:	2300      	movs	r3, #0
+ 800541c:	673b      	str	r3, [r7, #112]	; 0x70
+  macDefaultConf.ZeroQuantaPause = ENABLE;
+ 800541e:	2301      	movs	r3, #1
+ 8005420:	f887 3078 	strb.w	r3, [r7, #120]	; 0x78
+
+  /* MAC default configuration */
+  ETH_SetMACConfig(heth, &macDefaultConf);
+ 8005424:	f107 032c 	add.w	r3, r7, #44	; 0x2c
+ 8005428:	4619      	mov	r1, r3
+ 800542a:	6878      	ldr	r0, [r7, #4]
+ 800542c:	f7ff fde6 	bl	8004ffc <ETH_SetMACConfig>
+
+  /*--------------- ETHERNET DMA registers default Configuration --------------*/
+  dmaDefaultConf.AddressAlignedBeats = ENABLE;
+ 8005430:	2301      	movs	r3, #1
+ 8005432:	733b      	strb	r3, [r7, #12]
+  dmaDefaultConf.BurstMode = ETH_BURSTLENGTH_FIXED;
+ 8005434:	2301      	movs	r3, #1
+ 8005436:	613b      	str	r3, [r7, #16]
+  dmaDefaultConf.DMAArbitration = ETH_DMAARBITRATION_RX1_TX1;
+ 8005438:	2300      	movs	r3, #0
+ 800543a:	60bb      	str	r3, [r7, #8]
+  dmaDefaultConf.FlushRxPacket = DISABLE;
+ 800543c:	2300      	movs	r3, #0
+ 800543e:	f887 3024 	strb.w	r3, [r7, #36]	; 0x24
+  dmaDefaultConf.PBLx8Mode = DISABLE;
+ 8005442:	2300      	movs	r3, #0
+ 8005444:	757b      	strb	r3, [r7, #21]
+  dmaDefaultConf.RebuildINCRxBurst = DISABLE;
+ 8005446:	2300      	movs	r3, #0
+ 8005448:	753b      	strb	r3, [r7, #20]
+  dmaDefaultConf.RxDMABurstLength = ETH_RXDMABURSTLENGTH_32BEAT;
+ 800544a:	f44f 1300 	mov.w	r3, #2097152	; 0x200000
+ 800544e:	623b      	str	r3, [r7, #32]
+  dmaDefaultConf.SecondPacketOperate = DISABLE;
+ 8005450:	2300      	movs	r3, #0
+ 8005452:	773b      	strb	r3, [r7, #28]
+  dmaDefaultConf.TxDMABurstLength = ETH_TXDMABURSTLENGTH_32BEAT;
+ 8005454:	f44f 1300 	mov.w	r3, #2097152	; 0x200000
+ 8005458:	61bb      	str	r3, [r7, #24]
+  dmaDefaultConf.TCPSegmentation = DISABLE;
+ 800545a:	2300      	movs	r3, #0
+ 800545c:	f887 3025 	strb.w	r3, [r7, #37]	; 0x25
+  dmaDefaultConf.MaximumSegmentSize = ETH_SEGMENT_SIZE_DEFAULT;
+ 8005460:	f44f 7306 	mov.w	r3, #536	; 0x218
+ 8005464:	62bb      	str	r3, [r7, #40]	; 0x28
+
+  /* DMA default configuration */
+  ETH_SetDMAConfig(heth, &dmaDefaultConf);
+ 8005466:	f107 0308 	add.w	r3, r7, #8
+ 800546a:	4619      	mov	r1, r3
+ 800546c:	6878      	ldr	r0, [r7, #4]
+ 800546e:	f7ff fee1 	bl	8005234 <ETH_SetDMAConfig>
+}
+ 8005472:	bf00      	nop
+ 8005474:	3790      	adds	r7, #144	; 0x90
+ 8005476:	46bd      	mov	sp, r7
+ 8005478:	bd80      	pop	{r7, pc}
+
+0800547a <ETH_DMATxDescListInit>:
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @retval None
+  */
+static void ETH_DMATxDescListInit(ETH_HandleTypeDef *heth)
+{
+ 800547a:	b480      	push	{r7}
+ 800547c:	b085      	sub	sp, #20
+ 800547e:	af00      	add	r7, sp, #0
+ 8005480:	6078      	str	r0, [r7, #4]
+  ETH_DMADescTypeDef *dmatxdesc;
+  uint32_t i;
+
+  /* Fill each DMATxDesc descriptor with the right values */
+  for (i = 0; i < (uint32_t)ETH_TX_DESC_CNT; i++)
+ 8005482:	2300      	movs	r3, #0
+ 8005484:	60fb      	str	r3, [r7, #12]
+ 8005486:	e01d      	b.n	80054c4 <ETH_DMATxDescListInit+0x4a>
+  {
+    dmatxdesc = heth->Init.TxDesc + i;
+ 8005488:	687b      	ldr	r3, [r7, #4]
+ 800548a:	68d9      	ldr	r1, [r3, #12]
+ 800548c:	68fa      	ldr	r2, [r7, #12]
+ 800548e:	4613      	mov	r3, r2
+ 8005490:	005b      	lsls	r3, r3, #1
+ 8005492:	4413      	add	r3, r2
+ 8005494:	00db      	lsls	r3, r3, #3
+ 8005496:	440b      	add	r3, r1
+ 8005498:	60bb      	str	r3, [r7, #8]
+
+    WRITE_REG(dmatxdesc->DESC0, 0x0);
+ 800549a:	68bb      	ldr	r3, [r7, #8]
+ 800549c:	2200      	movs	r2, #0
+ 800549e:	601a      	str	r2, [r3, #0]
+    WRITE_REG(dmatxdesc->DESC1, 0x0);
+ 80054a0:	68bb      	ldr	r3, [r7, #8]
+ 80054a2:	2200      	movs	r2, #0
+ 80054a4:	605a      	str	r2, [r3, #4]
+    WRITE_REG(dmatxdesc->DESC2, 0x0);
+ 80054a6:	68bb      	ldr	r3, [r7, #8]
+ 80054a8:	2200      	movs	r2, #0
+ 80054aa:	609a      	str	r2, [r3, #8]
+    WRITE_REG(dmatxdesc->DESC3, 0x0);
+ 80054ac:	68bb      	ldr	r3, [r7, #8]
+ 80054ae:	2200      	movs	r2, #0
+ 80054b0:	60da      	str	r2, [r3, #12]
+
+    WRITE_REG(heth->TxDescList.TxDesc[i], (uint32_t)dmatxdesc);
+ 80054b2:	68b9      	ldr	r1, [r7, #8]
+ 80054b4:	687b      	ldr	r3, [r7, #4]
+ 80054b6:	68fa      	ldr	r2, [r7, #12]
+ 80054b8:	3206      	adds	r2, #6
+ 80054ba:	f843 1022 	str.w	r1, [r3, r2, lsl #2]
+  for (i = 0; i < (uint32_t)ETH_TX_DESC_CNT; i++)
+ 80054be:	68fb      	ldr	r3, [r7, #12]
+ 80054c0:	3301      	adds	r3, #1
+ 80054c2:	60fb      	str	r3, [r7, #12]
+ 80054c4:	68fb      	ldr	r3, [r7, #12]
+ 80054c6:	2b03      	cmp	r3, #3
+ 80054c8:	d9de      	bls.n	8005488 <ETH_DMATxDescListInit+0xe>
+
+  }
+
+  heth->TxDescList.CurTxDesc = 0;
+ 80054ca:	687b      	ldr	r3, [r7, #4]
+ 80054cc:	2200      	movs	r2, #0
+ 80054ce:	629a      	str	r2, [r3, #40]	; 0x28
+
+  /* Set Transmit Descriptor Ring Length */
+  WRITE_REG(heth->Instance->DMACTDRLR, (ETH_TX_DESC_CNT - 1U));
+ 80054d0:	687b      	ldr	r3, [r7, #4]
+ 80054d2:	681b      	ldr	r3, [r3, #0]
+ 80054d4:	f503 5380 	add.w	r3, r3, #4096	; 0x1000
+ 80054d8:	461a      	mov	r2, r3
+ 80054da:	2303      	movs	r3, #3
+ 80054dc:	f8c2 312c 	str.w	r3, [r2, #300]	; 0x12c
+
+  /* Set Transmit Descriptor List Address */
+  WRITE_REG(heth->Instance->DMACTDLAR, (uint32_t) heth->Init.TxDesc);
+ 80054e0:	687b      	ldr	r3, [r7, #4]
+ 80054e2:	68da      	ldr	r2, [r3, #12]
+ 80054e4:	687b      	ldr	r3, [r7, #4]
+ 80054e6:	681b      	ldr	r3, [r3, #0]
+ 80054e8:	f503 5380 	add.w	r3, r3, #4096	; 0x1000
+ 80054ec:	f8c3 2114 	str.w	r2, [r3, #276]	; 0x114
+
+  /* Set Transmit Descriptor Tail pointer */
+  WRITE_REG(heth->Instance->DMACTDTPR, (uint32_t) heth->Init.TxDesc);
+ 80054f0:	687b      	ldr	r3, [r7, #4]
+ 80054f2:	68da      	ldr	r2, [r3, #12]
+ 80054f4:	687b      	ldr	r3, [r7, #4]
+ 80054f6:	681b      	ldr	r3, [r3, #0]
+ 80054f8:	f503 5380 	add.w	r3, r3, #4096	; 0x1000
+ 80054fc:	f8c3 2120 	str.w	r2, [r3, #288]	; 0x120
+}
+ 8005500:	bf00      	nop
+ 8005502:	3714      	adds	r7, #20
+ 8005504:	46bd      	mov	sp, r7
+ 8005506:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 800550a:	4770      	bx	lr
+
+0800550c <ETH_DMARxDescListInit>:
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @retval None
+  */
+static void ETH_DMARxDescListInit(ETH_HandleTypeDef *heth)
+{
+ 800550c:	b480      	push	{r7}
+ 800550e:	b085      	sub	sp, #20
+ 8005510:	af00      	add	r7, sp, #0
+ 8005512:	6078      	str	r0, [r7, #4]
+  ETH_DMADescTypeDef *dmarxdesc;
+  uint32_t i;
+
+  for (i = 0; i < (uint32_t)ETH_RX_DESC_CNT; i++)
+ 8005514:	2300      	movs	r3, #0
+ 8005516:	60fb      	str	r3, [r7, #12]
+ 8005518:	e023      	b.n	8005562 <ETH_DMARxDescListInit+0x56>
+  {
+    dmarxdesc =  heth->Init.RxDesc + i;
+ 800551a:	687b      	ldr	r3, [r7, #4]
+ 800551c:	6919      	ldr	r1, [r3, #16]
+ 800551e:	68fa      	ldr	r2, [r7, #12]
+ 8005520:	4613      	mov	r3, r2
+ 8005522:	005b      	lsls	r3, r3, #1
+ 8005524:	4413      	add	r3, r2
+ 8005526:	00db      	lsls	r3, r3, #3
+ 8005528:	440b      	add	r3, r1
+ 800552a:	60bb      	str	r3, [r7, #8]
+
+    WRITE_REG(dmarxdesc->DESC0, 0x0);
+ 800552c:	68bb      	ldr	r3, [r7, #8]
+ 800552e:	2200      	movs	r2, #0
+ 8005530:	601a      	str	r2, [r3, #0]
+    WRITE_REG(dmarxdesc->DESC1, 0x0);
+ 8005532:	68bb      	ldr	r3, [r7, #8]
+ 8005534:	2200      	movs	r2, #0
+ 8005536:	605a      	str	r2, [r3, #4]
+    WRITE_REG(dmarxdesc->DESC2, 0x0);
+ 8005538:	68bb      	ldr	r3, [r7, #8]
+ 800553a:	2200      	movs	r2, #0
+ 800553c:	609a      	str	r2, [r3, #8]
+    WRITE_REG(dmarxdesc->DESC3, 0x0);
+ 800553e:	68bb      	ldr	r3, [r7, #8]
+ 8005540:	2200      	movs	r2, #0
+ 8005542:	60da      	str	r2, [r3, #12]
+    WRITE_REG(dmarxdesc->BackupAddr0, 0x0);
+ 8005544:	68bb      	ldr	r3, [r7, #8]
+ 8005546:	2200      	movs	r2, #0
+ 8005548:	611a      	str	r2, [r3, #16]
+    WRITE_REG(dmarxdesc->BackupAddr1, 0x0);
+ 800554a:	68bb      	ldr	r3, [r7, #8]
+ 800554c:	2200      	movs	r2, #0
+ 800554e:	615a      	str	r2, [r3, #20]
+
+
+    /* Set Rx descritors addresses */
+    WRITE_REG(heth->RxDescList.RxDesc[i], (uint32_t)dmarxdesc);
+ 8005550:	68b9      	ldr	r1, [r7, #8]
+ 8005552:	687b      	ldr	r3, [r7, #4]
+ 8005554:	68fa      	ldr	r2, [r7, #12]
+ 8005556:	3212      	adds	r2, #18
+ 8005558:	f843 1022 	str.w	r1, [r3, r2, lsl #2]
+  for (i = 0; i < (uint32_t)ETH_RX_DESC_CNT; i++)
+ 800555c:	68fb      	ldr	r3, [r7, #12]
+ 800555e:	3301      	adds	r3, #1
+ 8005560:	60fb      	str	r3, [r7, #12]
+ 8005562:	68fb      	ldr	r3, [r7, #12]
+ 8005564:	2b03      	cmp	r3, #3
+ 8005566:	d9d8      	bls.n	800551a <ETH_DMARxDescListInit+0xe>
+
+  }
+
+  WRITE_REG(heth->RxDescList.RxDescIdx, 0);
+ 8005568:	687b      	ldr	r3, [r7, #4]
+ 800556a:	2200      	movs	r2, #0
+ 800556c:	65da      	str	r2, [r3, #92]	; 0x5c
+  WRITE_REG(heth->RxDescList.RxDescCnt, 0);
+ 800556e:	687b      	ldr	r3, [r7, #4]
+ 8005570:	2200      	movs	r2, #0
+ 8005572:	661a      	str	r2, [r3, #96]	; 0x60
+  WRITE_REG(heth->RxDescList.RxBuildDescIdx, 0);
+ 8005574:	687b      	ldr	r3, [r7, #4]
+ 8005576:	2200      	movs	r2, #0
+ 8005578:	669a      	str	r2, [r3, #104]	; 0x68
+  WRITE_REG(heth->RxDescList.RxBuildDescCnt, 0);
+ 800557a:	687b      	ldr	r3, [r7, #4]
+ 800557c:	2200      	movs	r2, #0
+ 800557e:	66da      	str	r2, [r3, #108]	; 0x6c
+  WRITE_REG(heth->RxDescList.ItMode, 0);
+ 8005580:	687b      	ldr	r3, [r7, #4]
+ 8005582:	2200      	movs	r2, #0
+ 8005584:	659a      	str	r2, [r3, #88]	; 0x58
+
+  /* Set Receive Descriptor Ring Length */
+  WRITE_REG(heth->Instance->DMACRDRLR, ((uint32_t)(ETH_RX_DESC_CNT - 1U)));
+ 8005586:	687b      	ldr	r3, [r7, #4]
+ 8005588:	681b      	ldr	r3, [r3, #0]
+ 800558a:	f503 5380 	add.w	r3, r3, #4096	; 0x1000
+ 800558e:	461a      	mov	r2, r3
+ 8005590:	2303      	movs	r3, #3
+ 8005592:	f8c2 3130 	str.w	r3, [r2, #304]	; 0x130
+
+  /* Set Receive Descriptor List Address */
+  WRITE_REG(heth->Instance->DMACRDLAR, (uint32_t) heth->Init.RxDesc);
+ 8005596:	687b      	ldr	r3, [r7, #4]
+ 8005598:	691a      	ldr	r2, [r3, #16]
+ 800559a:	687b      	ldr	r3, [r7, #4]
+ 800559c:	681b      	ldr	r3, [r3, #0]
+ 800559e:	f503 5380 	add.w	r3, r3, #4096	; 0x1000
+ 80055a2:	f8c3 211c 	str.w	r2, [r3, #284]	; 0x11c
+
+  /* Set Receive Descriptor Tail pointer Address */
+  WRITE_REG(heth->Instance->DMACRDTPR, ((uint32_t)(heth->Init.RxDesc + (uint32_t)(ETH_RX_DESC_CNT - 1U))));
+ 80055a6:	687b      	ldr	r3, [r7, #4]
+ 80055a8:	691b      	ldr	r3, [r3, #16]
+ 80055aa:	f103 0248 	add.w	r2, r3, #72	; 0x48
+ 80055ae:	687b      	ldr	r3, [r7, #4]
+ 80055b0:	681b      	ldr	r3, [r3, #0]
+ 80055b2:	f503 5380 	add.w	r3, r3, #4096	; 0x1000
+ 80055b6:	f8c3 2128 	str.w	r2, [r3, #296]	; 0x128
+}
+ 80055ba:	bf00      	nop
+ 80055bc:	3714      	adds	r7, #20
+ 80055be:	46bd      	mov	sp, r7
+ 80055c0:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 80055c4:	4770      	bx	lr
+	...
+
+080055c8 <ETH_Prepare_Tx_Descriptors>:
+  * @param  pTxConfig: Tx packet configuration
+  * @param  ItMode: Enable or disable Tx EOT interrept
+  * @retval Status
+  */
+static uint32_t ETH_Prepare_Tx_Descriptors(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig, uint32_t ItMode)
+{
+ 80055c8:	b480      	push	{r7}
+ 80055ca:	b08d      	sub	sp, #52	; 0x34
+ 80055cc:	af00      	add	r7, sp, #0
+ 80055ce:	60f8      	str	r0, [r7, #12]
+ 80055d0:	60b9      	str	r1, [r7, #8]
+ 80055d2:	607a      	str	r2, [r7, #4]
+  ETH_TxDescListTypeDef *dmatxdesclist = &heth->TxDescList;
+ 80055d4:	68fb      	ldr	r3, [r7, #12]
+ 80055d6:	3318      	adds	r3, #24
+ 80055d8:	617b      	str	r3, [r7, #20]
+  uint32_t descidx = dmatxdesclist->CurTxDesc;
+ 80055da:	697b      	ldr	r3, [r7, #20]
+ 80055dc:	691b      	ldr	r3, [r3, #16]
+ 80055de:	62fb      	str	r3, [r7, #44]	; 0x2c
+  uint32_t firstdescidx = dmatxdesclist->CurTxDesc;
+ 80055e0:	697b      	ldr	r3, [r7, #20]
+ 80055e2:	691b      	ldr	r3, [r3, #16]
+ 80055e4:	613b      	str	r3, [r7, #16]
+  uint32_t idx;
+  uint32_t descnbr = 0;
+ 80055e6:	2300      	movs	r3, #0
+ 80055e8:	627b      	str	r3, [r7, #36]	; 0x24
+  ETH_DMADescTypeDef *dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[descidx];
+ 80055ea:	697b      	ldr	r3, [r7, #20]
+ 80055ec:	6afa      	ldr	r2, [r7, #44]	; 0x2c
+ 80055ee:	f853 3022 	ldr.w	r3, [r3, r2, lsl #2]
+ 80055f2:	623b      	str	r3, [r7, #32]
+
+  ETH_BufferTypeDef  *txbuffer = pTxConfig->TxBuffer;
+ 80055f4:	68bb      	ldr	r3, [r7, #8]
+ 80055f6:	689b      	ldr	r3, [r3, #8]
+ 80055f8:	61fb      	str	r3, [r7, #28]
+  uint32_t           bd_count = 0;
+ 80055fa:	2300      	movs	r3, #0
+ 80055fc:	61bb      	str	r3, [r7, #24]
+
+  /* Current Tx Descriptor Owned by DMA: cannot be used by the application  */
+  if ((READ_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCWBF_OWN) == ETH_DMATXNDESCWBF_OWN)
+ 80055fe:	6a3b      	ldr	r3, [r7, #32]
+ 8005600:	68db      	ldr	r3, [r3, #12]
+ 8005602:	f003 4300 	and.w	r3, r3, #2147483648	; 0x80000000
+ 8005606:	f1b3 4f00 	cmp.w	r3, #2147483648	; 0x80000000
+ 800560a:	d007      	beq.n	800561c <ETH_Prepare_Tx_Descriptors+0x54>
+      || (dmatxdesclist->PacketAddress[descidx] != NULL))
+ 800560c:	697a      	ldr	r2, [r7, #20]
+ 800560e:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 8005610:	3304      	adds	r3, #4
+ 8005612:	009b      	lsls	r3, r3, #2
+ 8005614:	4413      	add	r3, r2
+ 8005616:	685b      	ldr	r3, [r3, #4]
+ 8005618:	2b00      	cmp	r3, #0
+ 800561a:	d001      	beq.n	8005620 <ETH_Prepare_Tx_Descriptors+0x58>
+  {
+    return HAL_ETH_ERROR_BUSY;
+ 800561c:	2302      	movs	r3, #2
+ 800561e:	e259      	b.n	8005ad4 <ETH_Prepare_Tx_Descriptors+0x50c>
+
+  /***************************************************************************/
+  /*****************    Context descriptor configuration (Optional) **********/
+  /***************************************************************************/
+  /* If VLAN tag is enabled for this packet */
+  if (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_VLANTAG) != (uint32_t)RESET)
+ 8005620:	68bb      	ldr	r3, [r7, #8]
+ 8005622:	681b      	ldr	r3, [r3, #0]
+ 8005624:	f003 0304 	and.w	r3, r3, #4
+ 8005628:	2b00      	cmp	r3, #0
+ 800562a:	d044      	beq.n	80056b6 <ETH_Prepare_Tx_Descriptors+0xee>
+  {
+    /* Set vlan tag value */
+    MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXCDESC_VT, pTxConfig->VlanTag);
+ 800562c:	6a3b      	ldr	r3, [r7, #32]
+ 800562e:	68da      	ldr	r2, [r3, #12]
+ 8005630:	4b75      	ldr	r3, [pc, #468]	; (8005808 <ETH_Prepare_Tx_Descriptors+0x240>)
+ 8005632:	4013      	ands	r3, r2
+ 8005634:	68ba      	ldr	r2, [r7, #8]
+ 8005636:	6a52      	ldr	r2, [r2, #36]	; 0x24
+ 8005638:	431a      	orrs	r2, r3
+ 800563a:	6a3b      	ldr	r3, [r7, #32]
+ 800563c:	60da      	str	r2, [r3, #12]
+    /* Set vlan tag valid bit */
+    SET_BIT(dmatxdesc->DESC3, ETH_DMATXCDESC_VLTV);
+ 800563e:	6a3b      	ldr	r3, [r7, #32]
+ 8005640:	68db      	ldr	r3, [r3, #12]
+ 8005642:	f443 3280 	orr.w	r2, r3, #65536	; 0x10000
+ 8005646:	6a3b      	ldr	r3, [r7, #32]
+ 8005648:	60da      	str	r2, [r3, #12]
+    /* Set the descriptor as the vlan input source */
+    SET_BIT(heth->Instance->MACVIR, ETH_MACVIR_VLTI);
+ 800564a:	68fb      	ldr	r3, [r7, #12]
+ 800564c:	681b      	ldr	r3, [r3, #0]
+ 800564e:	6e1a      	ldr	r2, [r3, #96]	; 0x60
+ 8005650:	68fb      	ldr	r3, [r7, #12]
+ 8005652:	681b      	ldr	r3, [r3, #0]
+ 8005654:	f442 1280 	orr.w	r2, r2, #1048576	; 0x100000
+ 8005658:	661a      	str	r2, [r3, #96]	; 0x60
+
+    /* if inner VLAN is enabled */
+    if (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_INNERVLANTAG) != (uint32_t)RESET)
+ 800565a:	68bb      	ldr	r3, [r7, #8]
+ 800565c:	681b      	ldr	r3, [r3, #0]
+ 800565e:	f003 0308 	and.w	r3, r3, #8
+ 8005662:	2b00      	cmp	r3, #0
+ 8005664:	d027      	beq.n	80056b6 <ETH_Prepare_Tx_Descriptors+0xee>
+    {
+      /* Set inner vlan tag value */
+      MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXCDESC_IVT, (pTxConfig->InnerVlanTag << 16));
+ 8005666:	6a3b      	ldr	r3, [r7, #32]
+ 8005668:	689b      	ldr	r3, [r3, #8]
+ 800566a:	b29a      	uxth	r2, r3
+ 800566c:	68bb      	ldr	r3, [r7, #8]
+ 800566e:	6adb      	ldr	r3, [r3, #44]	; 0x2c
+ 8005670:	041b      	lsls	r3, r3, #16
+ 8005672:	431a      	orrs	r2, r3
+ 8005674:	6a3b      	ldr	r3, [r7, #32]
+ 8005676:	609a      	str	r2, [r3, #8]
+      /* Set inner vlan tag valid bit */
+      SET_BIT(dmatxdesc->DESC3, ETH_DMATXCDESC_IVLTV);
+ 8005678:	6a3b      	ldr	r3, [r7, #32]
+ 800567a:	68db      	ldr	r3, [r3, #12]
+ 800567c:	f443 3200 	orr.w	r2, r3, #131072	; 0x20000
+ 8005680:	6a3b      	ldr	r3, [r7, #32]
+ 8005682:	60da      	str	r2, [r3, #12]
+
+      /* Set Vlan Tag control */
+      MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXCDESC_IVTIR, pTxConfig->InnerVlanCtrl);
+ 8005684:	6a3b      	ldr	r3, [r7, #32]
+ 8005686:	68db      	ldr	r3, [r3, #12]
+ 8005688:	f423 2240 	bic.w	r2, r3, #786432	; 0xc0000
+ 800568c:	68bb      	ldr	r3, [r7, #8]
+ 800568e:	6b1b      	ldr	r3, [r3, #48]	; 0x30
+ 8005690:	431a      	orrs	r2, r3
+ 8005692:	6a3b      	ldr	r3, [r7, #32]
+ 8005694:	60da      	str	r2, [r3, #12]
+
+      /* Set the descriptor as the inner vlan input source */
+      SET_BIT(heth->Instance->MACIVIR, ETH_MACIVIR_VLTI);
+ 8005696:	68fb      	ldr	r3, [r7, #12]
+ 8005698:	681b      	ldr	r3, [r3, #0]
+ 800569a:	6e5a      	ldr	r2, [r3, #100]	; 0x64
+ 800569c:	68fb      	ldr	r3, [r7, #12]
+ 800569e:	681b      	ldr	r3, [r3, #0]
+ 80056a0:	f442 1280 	orr.w	r2, r2, #1048576	; 0x100000
+ 80056a4:	665a      	str	r2, [r3, #100]	; 0x64
+      /* Enable double VLAN processing */
+      SET_BIT(heth->Instance->MACVTR, ETH_MACVTR_EDVLP);
+ 80056a6:	68fb      	ldr	r3, [r7, #12]
+ 80056a8:	681b      	ldr	r3, [r3, #0]
+ 80056aa:	6d1a      	ldr	r2, [r3, #80]	; 0x50
+ 80056ac:	68fb      	ldr	r3, [r7, #12]
+ 80056ae:	681b      	ldr	r3, [r3, #0]
+ 80056b0:	f042 6280 	orr.w	r2, r2, #67108864	; 0x4000000
+ 80056b4:	651a      	str	r2, [r3, #80]	; 0x50
+    }
+  }
+
+  /* if tcp segmentation is enabled for this packet */
+  if (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_TSO) != (uint32_t)RESET)
+ 80056b6:	68bb      	ldr	r3, [r7, #8]
+ 80056b8:	681b      	ldr	r3, [r3, #0]
+ 80056ba:	f003 0310 	and.w	r3, r3, #16
+ 80056be:	2b00      	cmp	r3, #0
+ 80056c0:	d00e      	beq.n	80056e0 <ETH_Prepare_Tx_Descriptors+0x118>
+  {
+    /* Set MSS value */
+    MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXCDESC_MSS, pTxConfig->MaxSegmentSize);
+ 80056c2:	6a3b      	ldr	r3, [r7, #32]
+ 80056c4:	689a      	ldr	r2, [r3, #8]
+ 80056c6:	4b51      	ldr	r3, [pc, #324]	; (800580c <ETH_Prepare_Tx_Descriptors+0x244>)
+ 80056c8:	4013      	ands	r3, r2
+ 80056ca:	68ba      	ldr	r2, [r7, #8]
+ 80056cc:	6992      	ldr	r2, [r2, #24]
+ 80056ce:	431a      	orrs	r2, r3
+ 80056d0:	6a3b      	ldr	r3, [r7, #32]
+ 80056d2:	609a      	str	r2, [r3, #8]
+    /* Set MSS valid bit */
+    SET_BIT(dmatxdesc->DESC3, ETH_DMATXCDESC_TCMSSV);
+ 80056d4:	6a3b      	ldr	r3, [r7, #32]
+ 80056d6:	68db      	ldr	r3, [r3, #12]
+ 80056d8:	f043 6280 	orr.w	r2, r3, #67108864	; 0x4000000
+ 80056dc:	6a3b      	ldr	r3, [r7, #32]
+ 80056de:	60da      	str	r2, [r3, #12]
+  }
+
+  if ((READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_VLANTAG) != (uint32_t)RESET)
+ 80056e0:	68bb      	ldr	r3, [r7, #8]
+ 80056e2:	681b      	ldr	r3, [r3, #0]
+ 80056e4:	f003 0304 	and.w	r3, r3, #4
+ 80056e8:	2b00      	cmp	r3, #0
+ 80056ea:	d105      	bne.n	80056f8 <ETH_Prepare_Tx_Descriptors+0x130>
+      || (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_TSO) != (uint32_t)RESET))
+ 80056ec:	68bb      	ldr	r3, [r7, #8]
+ 80056ee:	681b      	ldr	r3, [r3, #0]
+ 80056f0:	f003 0310 	and.w	r3, r3, #16
+ 80056f4:	2b00      	cmp	r3, #0
+ 80056f6:	d036      	beq.n	8005766 <ETH_Prepare_Tx_Descriptors+0x19e>
+  {
+    /* Set as context descriptor */
+    SET_BIT(dmatxdesc->DESC3, ETH_DMATXCDESC_CTXT);
+ 80056f8:	6a3b      	ldr	r3, [r7, #32]
+ 80056fa:	68db      	ldr	r3, [r3, #12]
+ 80056fc:	f043 4280 	orr.w	r2, r3, #1073741824	; 0x40000000
+ 8005700:	6a3b      	ldr	r3, [r7, #32]
+ 8005702:	60da      	str	r2, [r3, #12]
+  __ASM volatile ("dmb 0xF":::"memory");
+ 8005704:	f3bf 8f5f 	dmb	sy
+}
+ 8005708:	bf00      	nop
+    /* Ensure rest of descriptor is written to RAM before the OWN bit */
+    __DMB();
+    /* Set own bit */
+    SET_BIT(dmatxdesc->DESC3, ETH_DMATXCDESC_OWN);
+ 800570a:	6a3b      	ldr	r3, [r7, #32]
+ 800570c:	68db      	ldr	r3, [r3, #12]
+ 800570e:	f043 4200 	orr.w	r2, r3, #2147483648	; 0x80000000
+ 8005712:	6a3b      	ldr	r3, [r7, #32]
+ 8005714:	60da      	str	r2, [r3, #12]
+    /* Increment current tx descriptor index */
+    INCR_TX_DESC_INDEX(descidx, 1U);
+ 8005716:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 8005718:	3301      	adds	r3, #1
+ 800571a:	62fb      	str	r3, [r7, #44]	; 0x2c
+ 800571c:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 800571e:	2b03      	cmp	r3, #3
+ 8005720:	d902      	bls.n	8005728 <ETH_Prepare_Tx_Descriptors+0x160>
+ 8005722:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 8005724:	3b04      	subs	r3, #4
+ 8005726:	62fb      	str	r3, [r7, #44]	; 0x2c
+    /* Get current descriptor address */
+    dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[descidx];
+ 8005728:	697b      	ldr	r3, [r7, #20]
+ 800572a:	6afa      	ldr	r2, [r7, #44]	; 0x2c
+ 800572c:	f853 3022 	ldr.w	r3, [r3, r2, lsl #2]
+ 8005730:	623b      	str	r3, [r7, #32]
+
+    descnbr += 1U;
+ 8005732:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 8005734:	3301      	adds	r3, #1
+ 8005736:	627b      	str	r3, [r7, #36]	; 0x24
+
+    /* Current Tx Descriptor Owned by DMA: cannot be used by the application  */
+    if (READ_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCWBF_OWN) == ETH_DMATXNDESCWBF_OWN)
+ 8005738:	6a3b      	ldr	r3, [r7, #32]
+ 800573a:	68db      	ldr	r3, [r3, #12]
+ 800573c:	f003 4300 	and.w	r3, r3, #2147483648	; 0x80000000
+ 8005740:	f1b3 4f00 	cmp.w	r3, #2147483648	; 0x80000000
+ 8005744:	d10f      	bne.n	8005766 <ETH_Prepare_Tx_Descriptors+0x19e>
+    {
+      dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[firstdescidx];
+ 8005746:	697b      	ldr	r3, [r7, #20]
+ 8005748:	693a      	ldr	r2, [r7, #16]
+ 800574a:	f853 3022 	ldr.w	r3, [r3, r2, lsl #2]
+ 800574e:	623b      	str	r3, [r7, #32]
+  __ASM volatile ("dmb 0xF":::"memory");
+ 8005750:	f3bf 8f5f 	dmb	sy
+}
+ 8005754:	bf00      	nop
+      /* Ensure rest of descriptor is written to RAM before the OWN bit */
+      __DMB();
+      /* Clear own bit */
+      CLEAR_BIT(dmatxdesc->DESC3, ETH_DMATXCDESC_OWN);
+ 8005756:	6a3b      	ldr	r3, [r7, #32]
+ 8005758:	68db      	ldr	r3, [r3, #12]
+ 800575a:	f023 4200 	bic.w	r2, r3, #2147483648	; 0x80000000
+ 800575e:	6a3b      	ldr	r3, [r7, #32]
+ 8005760:	60da      	str	r2, [r3, #12]
+
+      return HAL_ETH_ERROR_BUSY;
+ 8005762:	2302      	movs	r3, #2
+ 8005764:	e1b6      	b.n	8005ad4 <ETH_Prepare_Tx_Descriptors+0x50c>
+
+  /***************************************************************************/
+  /*****************    Normal descriptors configuration     *****************/
+  /***************************************************************************/
+
+  descnbr += 1U;
+ 8005766:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 8005768:	3301      	adds	r3, #1
+ 800576a:	627b      	str	r3, [r7, #36]	; 0x24
+
+  /* Set header or buffer 1 address */
+  WRITE_REG(dmatxdesc->DESC0, (uint32_t)txbuffer->buffer);
+ 800576c:	69fb      	ldr	r3, [r7, #28]
+ 800576e:	681b      	ldr	r3, [r3, #0]
+ 8005770:	461a      	mov	r2, r3
+ 8005772:	6a3b      	ldr	r3, [r7, #32]
+ 8005774:	601a      	str	r2, [r3, #0]
+  /* Set header or buffer 1 Length */
+  MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_B1L, txbuffer->len);
+ 8005776:	6a3b      	ldr	r3, [r7, #32]
+ 8005778:	689a      	ldr	r2, [r3, #8]
+ 800577a:	4b24      	ldr	r3, [pc, #144]	; (800580c <ETH_Prepare_Tx_Descriptors+0x244>)
+ 800577c:	4013      	ands	r3, r2
+ 800577e:	69fa      	ldr	r2, [r7, #28]
+ 8005780:	6852      	ldr	r2, [r2, #4]
+ 8005782:	431a      	orrs	r2, r3
+ 8005784:	6a3b      	ldr	r3, [r7, #32]
+ 8005786:	609a      	str	r2, [r3, #8]
+
+  if (txbuffer->next != NULL)
+ 8005788:	69fb      	ldr	r3, [r7, #28]
+ 800578a:	689b      	ldr	r3, [r3, #8]
+ 800578c:	2b00      	cmp	r3, #0
+ 800578e:	d012      	beq.n	80057b6 <ETH_Prepare_Tx_Descriptors+0x1ee>
+  {
+    txbuffer = txbuffer->next;
+ 8005790:	69fb      	ldr	r3, [r7, #28]
+ 8005792:	689b      	ldr	r3, [r3, #8]
+ 8005794:	61fb      	str	r3, [r7, #28]
+    /* Set buffer 2 address */
+    WRITE_REG(dmatxdesc->DESC1, (uint32_t)txbuffer->buffer);
+ 8005796:	69fb      	ldr	r3, [r7, #28]
+ 8005798:	681b      	ldr	r3, [r3, #0]
+ 800579a:	461a      	mov	r2, r3
+ 800579c:	6a3b      	ldr	r3, [r7, #32]
+ 800579e:	605a      	str	r2, [r3, #4]
+    /* Set buffer 2 Length */
+    MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_B2L, (txbuffer->len << 16));
+ 80057a0:	6a3b      	ldr	r3, [r7, #32]
+ 80057a2:	689a      	ldr	r2, [r3, #8]
+ 80057a4:	4b1a      	ldr	r3, [pc, #104]	; (8005810 <ETH_Prepare_Tx_Descriptors+0x248>)
+ 80057a6:	4013      	ands	r3, r2
+ 80057a8:	69fa      	ldr	r2, [r7, #28]
+ 80057aa:	6852      	ldr	r2, [r2, #4]
+ 80057ac:	0412      	lsls	r2, r2, #16
+ 80057ae:	431a      	orrs	r2, r3
+ 80057b0:	6a3b      	ldr	r3, [r7, #32]
+ 80057b2:	609a      	str	r2, [r3, #8]
+ 80057b4:	e008      	b.n	80057c8 <ETH_Prepare_Tx_Descriptors+0x200>
+  }
+  else
+  {
+    WRITE_REG(dmatxdesc->DESC1, 0x0);
+ 80057b6:	6a3b      	ldr	r3, [r7, #32]
+ 80057b8:	2200      	movs	r2, #0
+ 80057ba:	605a      	str	r2, [r3, #4]
+    /* Set buffer 2 Length */
+    MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_B2L, 0x0U);
+ 80057bc:	6a3b      	ldr	r3, [r7, #32]
+ 80057be:	689a      	ldr	r2, [r3, #8]
+ 80057c0:	4b13      	ldr	r3, [pc, #76]	; (8005810 <ETH_Prepare_Tx_Descriptors+0x248>)
+ 80057c2:	4013      	ands	r3, r2
+ 80057c4:	6a3a      	ldr	r2, [r7, #32]
+ 80057c6:	6093      	str	r3, [r2, #8]
+  }
+
+  if (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_TSO) != (uint32_t)RESET)
+ 80057c8:	68bb      	ldr	r3, [r7, #8]
+ 80057ca:	681b      	ldr	r3, [r3, #0]
+ 80057cc:	f003 0310 	and.w	r3, r3, #16
+ 80057d0:	2b00      	cmp	r3, #0
+ 80057d2:	d021      	beq.n	8005818 <ETH_Prepare_Tx_Descriptors+0x250>
+  {
+    /* Set TCP Header length */
+    MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_THL, (pTxConfig->TCPHeaderLen << 19));
+ 80057d4:	6a3b      	ldr	r3, [r7, #32]
+ 80057d6:	68db      	ldr	r3, [r3, #12]
+ 80057d8:	f423 02f0 	bic.w	r2, r3, #7864320	; 0x780000
+ 80057dc:	68bb      	ldr	r3, [r7, #8]
+ 80057de:	6a1b      	ldr	r3, [r3, #32]
+ 80057e0:	04db      	lsls	r3, r3, #19
+ 80057e2:	431a      	orrs	r2, r3
+ 80057e4:	6a3b      	ldr	r3, [r7, #32]
+ 80057e6:	60da      	str	r2, [r3, #12]
+    /* Set TCP payload length */
+    MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_TPL, pTxConfig->PayloadLen);
+ 80057e8:	6a3b      	ldr	r3, [r7, #32]
+ 80057ea:	68da      	ldr	r2, [r3, #12]
+ 80057ec:	4b09      	ldr	r3, [pc, #36]	; (8005814 <ETH_Prepare_Tx_Descriptors+0x24c>)
+ 80057ee:	4013      	ands	r3, r2
+ 80057f0:	68ba      	ldr	r2, [r7, #8]
+ 80057f2:	69d2      	ldr	r2, [r2, #28]
+ 80057f4:	431a      	orrs	r2, r3
+ 80057f6:	6a3b      	ldr	r3, [r7, #32]
+ 80057f8:	60da      	str	r2, [r3, #12]
+    /* Set TCP Segmentation Enabled bit */
+    SET_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_TSE);
+ 80057fa:	6a3b      	ldr	r3, [r7, #32]
+ 80057fc:	68db      	ldr	r3, [r3, #12]
+ 80057fe:	f443 2280 	orr.w	r2, r3, #262144	; 0x40000
+ 8005802:	6a3b      	ldr	r3, [r7, #32]
+ 8005804:	60da      	str	r2, [r3, #12]
+ 8005806:	e02e      	b.n	8005866 <ETH_Prepare_Tx_Descriptors+0x29e>
+ 8005808:	ffff0000 	.word	0xffff0000
+ 800580c:	ffffc000 	.word	0xffffc000
+ 8005810:	c000ffff 	.word	0xc000ffff
+ 8005814:	fffc0000 	.word	0xfffc0000
+  }
+  else
+  {
+    MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_FL, pTxConfig->Length);
+ 8005818:	6a3b      	ldr	r3, [r7, #32]
+ 800581a:	68da      	ldr	r2, [r3, #12]
+ 800581c:	4b7b      	ldr	r3, [pc, #492]	; (8005a0c <ETH_Prepare_Tx_Descriptors+0x444>)
+ 800581e:	4013      	ands	r3, r2
+ 8005820:	68ba      	ldr	r2, [r7, #8]
+ 8005822:	6852      	ldr	r2, [r2, #4]
+ 8005824:	431a      	orrs	r2, r3
+ 8005826:	6a3b      	ldr	r3, [r7, #32]
+ 8005828:	60da      	str	r2, [r3, #12]
+
+    if (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_CSUM) != (uint32_t)RESET)
+ 800582a:	68bb      	ldr	r3, [r7, #8]
+ 800582c:	681b      	ldr	r3, [r3, #0]
+ 800582e:	f003 0301 	and.w	r3, r3, #1
+ 8005832:	2b00      	cmp	r3, #0
+ 8005834:	d008      	beq.n	8005848 <ETH_Prepare_Tx_Descriptors+0x280>
+    {
+      MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_CIC, pTxConfig->ChecksumCtrl);
+ 8005836:	6a3b      	ldr	r3, [r7, #32]
+ 8005838:	68db      	ldr	r3, [r3, #12]
+ 800583a:	f423 3240 	bic.w	r2, r3, #196608	; 0x30000
+ 800583e:	68bb      	ldr	r3, [r7, #8]
+ 8005840:	695b      	ldr	r3, [r3, #20]
+ 8005842:	431a      	orrs	r2, r3
+ 8005844:	6a3b      	ldr	r3, [r7, #32]
+ 8005846:	60da      	str	r2, [r3, #12]
+    }
+
+    if (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_CRCPAD) != (uint32_t)RESET)
+ 8005848:	68bb      	ldr	r3, [r7, #8]
+ 800584a:	681b      	ldr	r3, [r3, #0]
+ 800584c:	f003 0320 	and.w	r3, r3, #32
+ 8005850:	2b00      	cmp	r3, #0
+ 8005852:	d008      	beq.n	8005866 <ETH_Prepare_Tx_Descriptors+0x29e>
+    {
+      MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_CPC, pTxConfig->CRCPadCtrl);
+ 8005854:	6a3b      	ldr	r3, [r7, #32]
+ 8005856:	68db      	ldr	r3, [r3, #12]
+ 8005858:	f023 6240 	bic.w	r2, r3, #201326592	; 0xc000000
+ 800585c:	68bb      	ldr	r3, [r7, #8]
+ 800585e:	691b      	ldr	r3, [r3, #16]
+ 8005860:	431a      	orrs	r2, r3
+ 8005862:	6a3b      	ldr	r3, [r7, #32]
+ 8005864:	60da      	str	r2, [r3, #12]
+    }
+  }
+
+  if (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_VLANTAG) != (uint32_t)RESET)
+ 8005866:	68bb      	ldr	r3, [r7, #8]
+ 8005868:	681b      	ldr	r3, [r3, #0]
+ 800586a:	f003 0304 	and.w	r3, r3, #4
+ 800586e:	2b00      	cmp	r3, #0
+ 8005870:	d008      	beq.n	8005884 <ETH_Prepare_Tx_Descriptors+0x2bc>
+  {
+    /* Set Vlan Tag control */
+    MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_VTIR, pTxConfig->VlanCtrl);
+ 8005872:	6a3b      	ldr	r3, [r7, #32]
+ 8005874:	689b      	ldr	r3, [r3, #8]
+ 8005876:	f423 4240 	bic.w	r2, r3, #49152	; 0xc000
+ 800587a:	68bb      	ldr	r3, [r7, #8]
+ 800587c:	6a9b      	ldr	r3, [r3, #40]	; 0x28
+ 800587e:	431a      	orrs	r2, r3
+ 8005880:	6a3b      	ldr	r3, [r7, #32]
+ 8005882:	609a      	str	r2, [r3, #8]
+  }
+
+  /* Mark it as First Descriptor */
+  SET_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_FD);
+ 8005884:	6a3b      	ldr	r3, [r7, #32]
+ 8005886:	68db      	ldr	r3, [r3, #12]
+ 8005888:	f043 5200 	orr.w	r2, r3, #536870912	; 0x20000000
+ 800588c:	6a3b      	ldr	r3, [r7, #32]
+ 800588e:	60da      	str	r2, [r3, #12]
+  /* Mark it as NORMAL descriptor */
+  CLEAR_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_CTXT);
+ 8005890:	6a3b      	ldr	r3, [r7, #32]
+ 8005892:	68db      	ldr	r3, [r3, #12]
+ 8005894:	f023 4280 	bic.w	r2, r3, #1073741824	; 0x40000000
+ 8005898:	6a3b      	ldr	r3, [r7, #32]
+ 800589a:	60da      	str	r2, [r3, #12]
+  __ASM volatile ("dmb 0xF":::"memory");
+ 800589c:	f3bf 8f5f 	dmb	sy
+}
+ 80058a0:	bf00      	nop
+  /* Ensure rest of descriptor is written to RAM before the OWN bit */
+  __DMB();
+  /* set OWN bit of FIRST descriptor */
+  SET_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_OWN);
+ 80058a2:	6a3b      	ldr	r3, [r7, #32]
+ 80058a4:	68db      	ldr	r3, [r3, #12]
+ 80058a6:	f043 4200 	orr.w	r2, r3, #2147483648	; 0x80000000
+ 80058aa:	6a3b      	ldr	r3, [r7, #32]
+ 80058ac:	60da      	str	r2, [r3, #12]
+
+  /* If source address insertion/replacement is enabled for this packet */
+  if (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_SAIC) != (uint32_t)RESET)
+ 80058ae:	68bb      	ldr	r3, [r7, #8]
+ 80058b0:	681b      	ldr	r3, [r3, #0]
+ 80058b2:	f003 0302 	and.w	r3, r3, #2
+ 80058b6:	2b00      	cmp	r3, #0
+ 80058b8:	f000 80da 	beq.w	8005a70 <ETH_Prepare_Tx_Descriptors+0x4a8>
+  {
+    MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_SAIC, pTxConfig->SrcAddrCtrl);
+ 80058bc:	6a3b      	ldr	r3, [r7, #32]
+ 80058be:	68db      	ldr	r3, [r3, #12]
+ 80058c0:	f023 7260 	bic.w	r2, r3, #58720256	; 0x3800000
+ 80058c4:	68bb      	ldr	r3, [r7, #8]
+ 80058c6:	68db      	ldr	r3, [r3, #12]
+ 80058c8:	431a      	orrs	r2, r3
+ 80058ca:	6a3b      	ldr	r3, [r7, #32]
+ 80058cc:	60da      	str	r2, [r3, #12]
+  }
+
+  /* only if the packet is split into more than one descriptors > 1 */
+  while (txbuffer->next != NULL)
+ 80058ce:	e0cf      	b.n	8005a70 <ETH_Prepare_Tx_Descriptors+0x4a8>
+  {
+    /* Clear the LD bit of previous descriptor */
+    CLEAR_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_LD);
+ 80058d0:	6a3b      	ldr	r3, [r7, #32]
+ 80058d2:	68db      	ldr	r3, [r3, #12]
+ 80058d4:	f023 5280 	bic.w	r2, r3, #268435456	; 0x10000000
+ 80058d8:	6a3b      	ldr	r3, [r7, #32]
+ 80058da:	60da      	str	r2, [r3, #12]
+    /* Increment current tx descriptor index */
+    INCR_TX_DESC_INDEX(descidx, 1U);
+ 80058dc:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 80058de:	3301      	adds	r3, #1
+ 80058e0:	62fb      	str	r3, [r7, #44]	; 0x2c
+ 80058e2:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 80058e4:	2b03      	cmp	r3, #3
+ 80058e6:	d902      	bls.n	80058ee <ETH_Prepare_Tx_Descriptors+0x326>
+ 80058e8:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 80058ea:	3b04      	subs	r3, #4
+ 80058ec:	62fb      	str	r3, [r7, #44]	; 0x2c
+    /* Get current descriptor address */
+    dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[descidx];
+ 80058ee:	697b      	ldr	r3, [r7, #20]
+ 80058f0:	6afa      	ldr	r2, [r7, #44]	; 0x2c
+ 80058f2:	f853 3022 	ldr.w	r3, [r3, r2, lsl #2]
+ 80058f6:	623b      	str	r3, [r7, #32]
+
+    /* Clear the FD bit of new Descriptor */
+    CLEAR_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_FD);
+ 80058f8:	6a3b      	ldr	r3, [r7, #32]
+ 80058fa:	68db      	ldr	r3, [r3, #12]
+ 80058fc:	f023 5200 	bic.w	r2, r3, #536870912	; 0x20000000
+ 8005900:	6a3b      	ldr	r3, [r7, #32]
+ 8005902:	60da      	str	r2, [r3, #12]
+
+    /* Current Tx Descriptor Owned by DMA: cannot be used by the application  */
+    if ((READ_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_OWN) == ETH_DMATXNDESCRF_OWN)
+ 8005904:	6a3b      	ldr	r3, [r7, #32]
+ 8005906:	68db      	ldr	r3, [r3, #12]
+ 8005908:	f003 4300 	and.w	r3, r3, #2147483648	; 0x80000000
+ 800590c:	f1b3 4f00 	cmp.w	r3, #2147483648	; 0x80000000
+ 8005910:	d007      	beq.n	8005922 <ETH_Prepare_Tx_Descriptors+0x35a>
+        || (dmatxdesclist->PacketAddress[descidx] != NULL))
+ 8005912:	697a      	ldr	r2, [r7, #20]
+ 8005914:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 8005916:	3304      	adds	r3, #4
+ 8005918:	009b      	lsls	r3, r3, #2
+ 800591a:	4413      	add	r3, r2
+ 800591c:	685b      	ldr	r3, [r3, #4]
+ 800591e:	2b00      	cmp	r3, #0
+ 8005920:	d029      	beq.n	8005976 <ETH_Prepare_Tx_Descriptors+0x3ae>
+    {
+      descidx = firstdescidx;
+ 8005922:	693b      	ldr	r3, [r7, #16]
+ 8005924:	62fb      	str	r3, [r7, #44]	; 0x2c
+      dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[descidx];
+ 8005926:	697b      	ldr	r3, [r7, #20]
+ 8005928:	6afa      	ldr	r2, [r7, #44]	; 0x2c
+ 800592a:	f853 3022 	ldr.w	r3, [r3, r2, lsl #2]
+ 800592e:	623b      	str	r3, [r7, #32]
+
+      /* clear previous desc own bit */
+      for (idx = 0; idx < descnbr; idx ++)
+ 8005930:	2300      	movs	r3, #0
+ 8005932:	62bb      	str	r3, [r7, #40]	; 0x28
+ 8005934:	e019      	b.n	800596a <ETH_Prepare_Tx_Descriptors+0x3a2>
+  __ASM volatile ("dmb 0xF":::"memory");
+ 8005936:	f3bf 8f5f 	dmb	sy
+}
+ 800593a:	bf00      	nop
+      {
+        /* Ensure rest of descriptor is written to RAM before the OWN bit */
+        __DMB();
+
+        CLEAR_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_OWN);
+ 800593c:	6a3b      	ldr	r3, [r7, #32]
+ 800593e:	68db      	ldr	r3, [r3, #12]
+ 8005940:	f023 4200 	bic.w	r2, r3, #2147483648	; 0x80000000
+ 8005944:	6a3b      	ldr	r3, [r7, #32]
+ 8005946:	60da      	str	r2, [r3, #12]
+
+        /* Increment current tx descriptor index */
+        INCR_TX_DESC_INDEX(descidx, 1U);
+ 8005948:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 800594a:	3301      	adds	r3, #1
+ 800594c:	62fb      	str	r3, [r7, #44]	; 0x2c
+ 800594e:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 8005950:	2b03      	cmp	r3, #3
+ 8005952:	d902      	bls.n	800595a <ETH_Prepare_Tx_Descriptors+0x392>
+ 8005954:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 8005956:	3b04      	subs	r3, #4
+ 8005958:	62fb      	str	r3, [r7, #44]	; 0x2c
+        /* Get current descriptor address */
+        dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[descidx];
+ 800595a:	697b      	ldr	r3, [r7, #20]
+ 800595c:	6afa      	ldr	r2, [r7, #44]	; 0x2c
+ 800595e:	f853 3022 	ldr.w	r3, [r3, r2, lsl #2]
+ 8005962:	623b      	str	r3, [r7, #32]
+      for (idx = 0; idx < descnbr; idx ++)
+ 8005964:	6abb      	ldr	r3, [r7, #40]	; 0x28
+ 8005966:	3301      	adds	r3, #1
+ 8005968:	62bb      	str	r3, [r7, #40]	; 0x28
+ 800596a:	6aba      	ldr	r2, [r7, #40]	; 0x28
+ 800596c:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 800596e:	429a      	cmp	r2, r3
+ 8005970:	d3e1      	bcc.n	8005936 <ETH_Prepare_Tx_Descriptors+0x36e>
+      }
+
+      return HAL_ETH_ERROR_BUSY;
+ 8005972:	2302      	movs	r3, #2
+ 8005974:	e0ae      	b.n	8005ad4 <ETH_Prepare_Tx_Descriptors+0x50c>
+    }
+
+    descnbr += 1U;
+ 8005976:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 8005978:	3301      	adds	r3, #1
+ 800597a:	627b      	str	r3, [r7, #36]	; 0x24
+
+    /* Get the next Tx buffer in the list */
+    txbuffer = txbuffer->next;
+ 800597c:	69fb      	ldr	r3, [r7, #28]
+ 800597e:	689b      	ldr	r3, [r3, #8]
+ 8005980:	61fb      	str	r3, [r7, #28]
+
+    /* Set header or buffer 1 address */
+    WRITE_REG(dmatxdesc->DESC0, (uint32_t)txbuffer->buffer);
+ 8005982:	69fb      	ldr	r3, [r7, #28]
+ 8005984:	681b      	ldr	r3, [r3, #0]
+ 8005986:	461a      	mov	r2, r3
+ 8005988:	6a3b      	ldr	r3, [r7, #32]
+ 800598a:	601a      	str	r2, [r3, #0]
+    /* Set header or buffer 1 Length */
+    MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_B1L, txbuffer->len);
+ 800598c:	6a3b      	ldr	r3, [r7, #32]
+ 800598e:	689a      	ldr	r2, [r3, #8]
+ 8005990:	4b1f      	ldr	r3, [pc, #124]	; (8005a10 <ETH_Prepare_Tx_Descriptors+0x448>)
+ 8005992:	4013      	ands	r3, r2
+ 8005994:	69fa      	ldr	r2, [r7, #28]
+ 8005996:	6852      	ldr	r2, [r2, #4]
+ 8005998:	431a      	orrs	r2, r3
+ 800599a:	6a3b      	ldr	r3, [r7, #32]
+ 800599c:	609a      	str	r2, [r3, #8]
+
+    if (txbuffer->next != NULL)
+ 800599e:	69fb      	ldr	r3, [r7, #28]
+ 80059a0:	689b      	ldr	r3, [r3, #8]
+ 80059a2:	2b00      	cmp	r3, #0
+ 80059a4:	d012      	beq.n	80059cc <ETH_Prepare_Tx_Descriptors+0x404>
+    {
+      /* Get the next Tx buffer in the list */
+      txbuffer = txbuffer->next;
+ 80059a6:	69fb      	ldr	r3, [r7, #28]
+ 80059a8:	689b      	ldr	r3, [r3, #8]
+ 80059aa:	61fb      	str	r3, [r7, #28]
+      /* Set buffer 2 address */
+      WRITE_REG(dmatxdesc->DESC1, (uint32_t)txbuffer->buffer);
+ 80059ac:	69fb      	ldr	r3, [r7, #28]
+ 80059ae:	681b      	ldr	r3, [r3, #0]
+ 80059b0:	461a      	mov	r2, r3
+ 80059b2:	6a3b      	ldr	r3, [r7, #32]
+ 80059b4:	605a      	str	r2, [r3, #4]
+      /* Set buffer 2 Length */
+      MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_B2L, (txbuffer->len << 16));
+ 80059b6:	6a3b      	ldr	r3, [r7, #32]
+ 80059b8:	689a      	ldr	r2, [r3, #8]
+ 80059ba:	4b16      	ldr	r3, [pc, #88]	; (8005a14 <ETH_Prepare_Tx_Descriptors+0x44c>)
+ 80059bc:	4013      	ands	r3, r2
+ 80059be:	69fa      	ldr	r2, [r7, #28]
+ 80059c0:	6852      	ldr	r2, [r2, #4]
+ 80059c2:	0412      	lsls	r2, r2, #16
+ 80059c4:	431a      	orrs	r2, r3
+ 80059c6:	6a3b      	ldr	r3, [r7, #32]
+ 80059c8:	609a      	str	r2, [r3, #8]
+ 80059ca:	e008      	b.n	80059de <ETH_Prepare_Tx_Descriptors+0x416>
+    }
+    else
+    {
+      WRITE_REG(dmatxdesc->DESC1, 0x0);
+ 80059cc:	6a3b      	ldr	r3, [r7, #32]
+ 80059ce:	2200      	movs	r2, #0
+ 80059d0:	605a      	str	r2, [r3, #4]
+      /* Set buffer 2 Length */
+      MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_B2L, 0x0U);
+ 80059d2:	6a3b      	ldr	r3, [r7, #32]
+ 80059d4:	689a      	ldr	r2, [r3, #8]
+ 80059d6:	4b0f      	ldr	r3, [pc, #60]	; (8005a14 <ETH_Prepare_Tx_Descriptors+0x44c>)
+ 80059d8:	4013      	ands	r3, r2
+ 80059da:	6a3a      	ldr	r2, [r7, #32]
+ 80059dc:	6093      	str	r3, [r2, #8]
+    }
+
+    if (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_TSO) != (uint32_t)RESET)
+ 80059de:	68bb      	ldr	r3, [r7, #8]
+ 80059e0:	681b      	ldr	r3, [r3, #0]
+ 80059e2:	f003 0310 	and.w	r3, r3, #16
+ 80059e6:	2b00      	cmp	r3, #0
+ 80059e8:	d018      	beq.n	8005a1c <ETH_Prepare_Tx_Descriptors+0x454>
+    {
+      /* Set TCP payload length */
+      MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_TPL, pTxConfig->PayloadLen);
+ 80059ea:	6a3b      	ldr	r3, [r7, #32]
+ 80059ec:	68da      	ldr	r2, [r3, #12]
+ 80059ee:	4b0a      	ldr	r3, [pc, #40]	; (8005a18 <ETH_Prepare_Tx_Descriptors+0x450>)
+ 80059f0:	4013      	ands	r3, r2
+ 80059f2:	68ba      	ldr	r2, [r7, #8]
+ 80059f4:	69d2      	ldr	r2, [r2, #28]
+ 80059f6:	431a      	orrs	r2, r3
+ 80059f8:	6a3b      	ldr	r3, [r7, #32]
+ 80059fa:	60da      	str	r2, [r3, #12]
+      /* Set TCP Segmentation Enabled bit */
+      SET_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_TSE);
+ 80059fc:	6a3b      	ldr	r3, [r7, #32]
+ 80059fe:	68db      	ldr	r3, [r3, #12]
+ 8005a00:	f443 2280 	orr.w	r2, r3, #262144	; 0x40000
+ 8005a04:	6a3b      	ldr	r3, [r7, #32]
+ 8005a06:	60da      	str	r2, [r3, #12]
+ 8005a08:	e020      	b.n	8005a4c <ETH_Prepare_Tx_Descriptors+0x484>
+ 8005a0a:	bf00      	nop
+ 8005a0c:	ffff8000 	.word	0xffff8000
+ 8005a10:	ffffc000 	.word	0xffffc000
+ 8005a14:	c000ffff 	.word	0xc000ffff
+ 8005a18:	fffc0000 	.word	0xfffc0000
+    }
+    else
+    {
+      /* Set the packet length */
+      MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_FL, pTxConfig->Length);
+ 8005a1c:	6a3b      	ldr	r3, [r7, #32]
+ 8005a1e:	68da      	ldr	r2, [r3, #12]
+ 8005a20:	4b2f      	ldr	r3, [pc, #188]	; (8005ae0 <ETH_Prepare_Tx_Descriptors+0x518>)
+ 8005a22:	4013      	ands	r3, r2
+ 8005a24:	68ba      	ldr	r2, [r7, #8]
+ 8005a26:	6852      	ldr	r2, [r2, #4]
+ 8005a28:	431a      	orrs	r2, r3
+ 8005a2a:	6a3b      	ldr	r3, [r7, #32]
+ 8005a2c:	60da      	str	r2, [r3, #12]
+
+      if (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_CSUM) != (uint32_t)RESET)
+ 8005a2e:	68bb      	ldr	r3, [r7, #8]
+ 8005a30:	681b      	ldr	r3, [r3, #0]
+ 8005a32:	f003 0301 	and.w	r3, r3, #1
+ 8005a36:	2b00      	cmp	r3, #0
+ 8005a38:	d008      	beq.n	8005a4c <ETH_Prepare_Tx_Descriptors+0x484>
+      {
+        /* Checksum Insertion Control */
+        MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_CIC, pTxConfig->ChecksumCtrl);
+ 8005a3a:	6a3b      	ldr	r3, [r7, #32]
+ 8005a3c:	68db      	ldr	r3, [r3, #12]
+ 8005a3e:	f423 3240 	bic.w	r2, r3, #196608	; 0x30000
+ 8005a42:	68bb      	ldr	r3, [r7, #8]
+ 8005a44:	695b      	ldr	r3, [r3, #20]
+ 8005a46:	431a      	orrs	r2, r3
+ 8005a48:	6a3b      	ldr	r3, [r7, #32]
+ 8005a4a:	60da      	str	r2, [r3, #12]
+      }
+    }
+
+    bd_count += 1U;
+ 8005a4c:	69bb      	ldr	r3, [r7, #24]
+ 8005a4e:	3301      	adds	r3, #1
+ 8005a50:	61bb      	str	r3, [r7, #24]
+  __ASM volatile ("dmb 0xF":::"memory");
+ 8005a52:	f3bf 8f5f 	dmb	sy
+}
+ 8005a56:	bf00      	nop
+
+    /* Ensure rest of descriptor is written to RAM before the OWN bit */
+    __DMB();
+    /* Set Own bit */
+    SET_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_OWN);
+ 8005a58:	6a3b      	ldr	r3, [r7, #32]
+ 8005a5a:	68db      	ldr	r3, [r3, #12]
+ 8005a5c:	f043 4200 	orr.w	r2, r3, #2147483648	; 0x80000000
+ 8005a60:	6a3b      	ldr	r3, [r7, #32]
+ 8005a62:	60da      	str	r2, [r3, #12]
+    /* Mark it as NORMAL descriptor */
+    CLEAR_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_CTXT);
+ 8005a64:	6a3b      	ldr	r3, [r7, #32]
+ 8005a66:	68db      	ldr	r3, [r3, #12]
+ 8005a68:	f023 4280 	bic.w	r2, r3, #1073741824	; 0x40000000
+ 8005a6c:	6a3b      	ldr	r3, [r7, #32]
+ 8005a6e:	60da      	str	r2, [r3, #12]
+  while (txbuffer->next != NULL)
+ 8005a70:	69fb      	ldr	r3, [r7, #28]
+ 8005a72:	689b      	ldr	r3, [r3, #8]
+ 8005a74:	2b00      	cmp	r3, #0
+ 8005a76:	f47f af2b 	bne.w	80058d0 <ETH_Prepare_Tx_Descriptors+0x308>
+  }
+
+  if (ItMode != ((uint32_t)RESET))
+ 8005a7a:	687b      	ldr	r3, [r7, #4]
+ 8005a7c:	2b00      	cmp	r3, #0
+ 8005a7e:	d006      	beq.n	8005a8e <ETH_Prepare_Tx_Descriptors+0x4c6>
+  {
+    /* Set Interrupt on completion bit */
+    SET_BIT(dmatxdesc->DESC2, ETH_DMATXNDESCRF_IOC);
+ 8005a80:	6a3b      	ldr	r3, [r7, #32]
+ 8005a82:	689b      	ldr	r3, [r3, #8]
+ 8005a84:	f043 4200 	orr.w	r2, r3, #2147483648	; 0x80000000
+ 8005a88:	6a3b      	ldr	r3, [r7, #32]
+ 8005a8a:	609a      	str	r2, [r3, #8]
+ 8005a8c:	e005      	b.n	8005a9a <ETH_Prepare_Tx_Descriptors+0x4d2>
+  }
+  else
+  {
+    /* Clear Interrupt on completion bit */
+    CLEAR_BIT(dmatxdesc->DESC2, ETH_DMATXNDESCRF_IOC);
+ 8005a8e:	6a3b      	ldr	r3, [r7, #32]
+ 8005a90:	689b      	ldr	r3, [r3, #8]
+ 8005a92:	f023 4200 	bic.w	r2, r3, #2147483648	; 0x80000000
+ 8005a96:	6a3b      	ldr	r3, [r7, #32]
+ 8005a98:	609a      	str	r2, [r3, #8]
+  }
+
+  /* Mark it as LAST descriptor */
+  SET_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_LD);
+ 8005a9a:	6a3b      	ldr	r3, [r7, #32]
+ 8005a9c:	68db      	ldr	r3, [r3, #12]
+ 8005a9e:	f043 5280 	orr.w	r2, r3, #268435456	; 0x10000000
+ 8005aa2:	6a3b      	ldr	r3, [r7, #32]
+ 8005aa4:	60da      	str	r2, [r3, #12]
+  /* Save the current packet address to expose it to the application */
+  dmatxdesclist->PacketAddress[descidx] = dmatxdesclist->CurrentPacketAddress;
+ 8005aa6:	697b      	ldr	r3, [r7, #20]
+ 8005aa8:	6a5a      	ldr	r2, [r3, #36]	; 0x24
+ 8005aaa:	6979      	ldr	r1, [r7, #20]
+ 8005aac:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 8005aae:	3304      	adds	r3, #4
+ 8005ab0:	009b      	lsls	r3, r3, #2
+ 8005ab2:	440b      	add	r3, r1
+ 8005ab4:	605a      	str	r2, [r3, #4]
+
+  dmatxdesclist->CurTxDesc = descidx;
+ 8005ab6:	697b      	ldr	r3, [r7, #20]
+ 8005ab8:	6afa      	ldr	r2, [r7, #44]	; 0x2c
+ 8005aba:	611a      	str	r2, [r3, #16]
+  __ASM volatile ("cpsid i" : : : "memory");
+ 8005abc:	b672      	cpsid	i
+}
+ 8005abe:	bf00      	nop
+
+  /* disable the interrupt */
+  __disable_irq();
+
+  dmatxdesclist->BuffersInUse += bd_count + 1U;
+ 8005ac0:	697b      	ldr	r3, [r7, #20]
+ 8005ac2:	6a9a      	ldr	r2, [r3, #40]	; 0x28
+ 8005ac4:	69bb      	ldr	r3, [r7, #24]
+ 8005ac6:	4413      	add	r3, r2
+ 8005ac8:	1c5a      	adds	r2, r3, #1
+ 8005aca:	697b      	ldr	r3, [r7, #20]
+ 8005acc:	629a      	str	r2, [r3, #40]	; 0x28
+  __ASM volatile ("cpsie i" : : : "memory");
+ 8005ace:	b662      	cpsie	i
+}
+ 8005ad0:	bf00      	nop
+  /* Enable interrupts back */
+  __enable_irq();
+
+
+  /* Return function status */
+  return HAL_ETH_ERROR_NONE;
+ 8005ad2:	2300      	movs	r3, #0
+}
+ 8005ad4:	4618      	mov	r0, r3
+ 8005ad6:	3734      	adds	r7, #52	; 0x34
+ 8005ad8:	46bd      	mov	sp, r7
+ 8005ada:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8005ade:	4770      	bx	lr
+ 8005ae0:	ffff8000 	.word	0xffff8000
+
+08005ae4 <HAL_FDCAN_Init>:
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_Init(FDCAN_HandleTypeDef *hfdcan)
+{
+ 8005ae4:	b580      	push	{r7, lr}
+ 8005ae6:	b098      	sub	sp, #96	; 0x60
+ 8005ae8:	af00      	add	r7, sp, #0
+ 8005aea:	6078      	str	r0, [r7, #4]
+  uint32_t tickstart;
+  HAL_StatusTypeDef status;
+  const uint32_t CvtEltSize[] = {0, 0, 0, 0, 0, 1, 2, 3, 4, 0, 5, 0, 0, 0, 6, 0, 0, 0, 7};
+ 8005aec:	4a84      	ldr	r2, [pc, #528]	; (8005d00 <HAL_FDCAN_Init+0x21c>)
+ 8005aee:	f107 030c 	add.w	r3, r7, #12
+ 8005af2:	4611      	mov	r1, r2
+ 8005af4:	224c      	movs	r2, #76	; 0x4c
+ 8005af6:	4618      	mov	r0, r3
+ 8005af8:	f01c f975 	bl	8021de6 <memcpy>
+
+  /* Check FDCAN handle */
+  if (hfdcan == NULL)
+ 8005afc:	687b      	ldr	r3, [r7, #4]
+ 8005afe:	2b00      	cmp	r3, #0
+ 8005b00:	d101      	bne.n	8005b06 <HAL_FDCAN_Init+0x22>
+  {
+    return HAL_ERROR;
+ 8005b02:	2301      	movs	r3, #1
+ 8005b04:	e1c6      	b.n	8005e94 <HAL_FDCAN_Init+0x3b0>
+  }
+
+  /* Check FDCAN instance */
+  if (hfdcan->Instance == FDCAN1)
+ 8005b06:	687b      	ldr	r3, [r7, #4]
+ 8005b08:	681b      	ldr	r3, [r3, #0]
+ 8005b0a:	4a7e      	ldr	r2, [pc, #504]	; (8005d04 <HAL_FDCAN_Init+0x220>)
+ 8005b0c:	4293      	cmp	r3, r2
+ 8005b0e:	d106      	bne.n	8005b1e <HAL_FDCAN_Init+0x3a>
+  {
+    hfdcan->ttcan = (TTCAN_TypeDef *)((uint32_t)hfdcan->Instance + 0x100U);
+ 8005b10:	687b      	ldr	r3, [r7, #4]
+ 8005b12:	681b      	ldr	r3, [r3, #0]
+ 8005b14:	f503 7380 	add.w	r3, r3, #256	; 0x100
+ 8005b18:	461a      	mov	r2, r3
+ 8005b1a:	687b      	ldr	r3, [r7, #4]
+ 8005b1c:	605a      	str	r2, [r3, #4]
+
+    /* Init the low level hardware: CLOCK, NVIC */
+    hfdcan->MspInitCallback(hfdcan);
+  }
+#else
+  if (hfdcan->State == HAL_FDCAN_STATE_RESET)
+ 8005b1e:	687b      	ldr	r3, [r7, #4]
+ 8005b20:	f893 3098 	ldrb.w	r3, [r3, #152]	; 0x98
+ 8005b24:	b2db      	uxtb	r3, r3
+ 8005b26:	2b00      	cmp	r3, #0
+ 8005b28:	d106      	bne.n	8005b38 <HAL_FDCAN_Init+0x54>
+  {
+    /* Allocate lock resource and initialize it */
+    hfdcan->Lock = HAL_UNLOCKED;
+ 8005b2a:	687b      	ldr	r3, [r7, #4]
+ 8005b2c:	2200      	movs	r2, #0
+ 8005b2e:	f883 2099 	strb.w	r2, [r3, #153]	; 0x99
+
+    /* Init the low level hardware: CLOCK, NVIC */
+    HAL_FDCAN_MspInit(hfdcan);
+ 8005b32:	6878      	ldr	r0, [r7, #4]
+ 8005b34:	f7fb fd02 	bl	800153c <HAL_FDCAN_MspInit>
+  }
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+
+  /* Exit from Sleep mode */
+  CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_CSR);
+ 8005b38:	687b      	ldr	r3, [r7, #4]
+ 8005b3a:	681b      	ldr	r3, [r3, #0]
+ 8005b3c:	699a      	ldr	r2, [r3, #24]
+ 8005b3e:	687b      	ldr	r3, [r7, #4]
+ 8005b40:	681b      	ldr	r3, [r3, #0]
+ 8005b42:	f022 0210 	bic.w	r2, r2, #16
+ 8005b46:	619a      	str	r2, [r3, #24]
+
+  /* Get tick */
+  tickstart = HAL_GetTick();
+ 8005b48:	f7fc fc0c 	bl	8002364 <HAL_GetTick>
+ 8005b4c:	65f8      	str	r0, [r7, #92]	; 0x5c
+
+  /* Check Sleep mode acknowledge */
+  while ((hfdcan->Instance->CCCR & FDCAN_CCCR_CSA) == FDCAN_CCCR_CSA)
+ 8005b4e:	e014      	b.n	8005b7a <HAL_FDCAN_Init+0x96>
+  {
+    if ((HAL_GetTick() - tickstart) > FDCAN_TIMEOUT_VALUE)
+ 8005b50:	f7fc fc08 	bl	8002364 <HAL_GetTick>
+ 8005b54:	4602      	mov	r2, r0
+ 8005b56:	6dfb      	ldr	r3, [r7, #92]	; 0x5c
+ 8005b58:	1ad3      	subs	r3, r2, r3
+ 8005b5a:	2b0a      	cmp	r3, #10
+ 8005b5c:	d90d      	bls.n	8005b7a <HAL_FDCAN_Init+0x96>
+    {
+      /* Update error code */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+ 8005b5e:	687b      	ldr	r3, [r7, #4]
+ 8005b60:	f8d3 309c 	ldr.w	r3, [r3, #156]	; 0x9c
+ 8005b64:	f043 0201 	orr.w	r2, r3, #1
+ 8005b68:	687b      	ldr	r3, [r7, #4]
+ 8005b6a:	f8c3 209c 	str.w	r2, [r3, #156]	; 0x9c
+
+      /* Change FDCAN state */
+      hfdcan->State = HAL_FDCAN_STATE_ERROR;
+ 8005b6e:	687b      	ldr	r3, [r7, #4]
+ 8005b70:	2203      	movs	r2, #3
+ 8005b72:	f883 2098 	strb.w	r2, [r3, #152]	; 0x98
+
+      return HAL_ERROR;
+ 8005b76:	2301      	movs	r3, #1
+ 8005b78:	e18c      	b.n	8005e94 <HAL_FDCAN_Init+0x3b0>
+  while ((hfdcan->Instance->CCCR & FDCAN_CCCR_CSA) == FDCAN_CCCR_CSA)
+ 8005b7a:	687b      	ldr	r3, [r7, #4]
+ 8005b7c:	681b      	ldr	r3, [r3, #0]
+ 8005b7e:	699b      	ldr	r3, [r3, #24]
+ 8005b80:	f003 0308 	and.w	r3, r3, #8
+ 8005b84:	2b08      	cmp	r3, #8
+ 8005b86:	d0e3      	beq.n	8005b50 <HAL_FDCAN_Init+0x6c>
+    }
+  }
+
+  /* Request initialisation */
+  SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_INIT);
+ 8005b88:	687b      	ldr	r3, [r7, #4]
+ 8005b8a:	681b      	ldr	r3, [r3, #0]
+ 8005b8c:	699a      	ldr	r2, [r3, #24]
+ 8005b8e:	687b      	ldr	r3, [r7, #4]
+ 8005b90:	681b      	ldr	r3, [r3, #0]
+ 8005b92:	f042 0201 	orr.w	r2, r2, #1
+ 8005b96:	619a      	str	r2, [r3, #24]
+
+  /* Get tick */
+  tickstart = HAL_GetTick();
+ 8005b98:	f7fc fbe4 	bl	8002364 <HAL_GetTick>
+ 8005b9c:	65f8      	str	r0, [r7, #92]	; 0x5c
+
+  /* Wait until the INIT bit into CCCR register is set */
+  while ((hfdcan->Instance->CCCR & FDCAN_CCCR_INIT) == 0U)
+ 8005b9e:	e014      	b.n	8005bca <HAL_FDCAN_Init+0xe6>
+  {
+    /* Check for the Timeout */
+    if ((HAL_GetTick() - tickstart) > FDCAN_TIMEOUT_VALUE)
+ 8005ba0:	f7fc fbe0 	bl	8002364 <HAL_GetTick>
+ 8005ba4:	4602      	mov	r2, r0
+ 8005ba6:	6dfb      	ldr	r3, [r7, #92]	; 0x5c
+ 8005ba8:	1ad3      	subs	r3, r2, r3
+ 8005baa:	2b0a      	cmp	r3, #10
+ 8005bac:	d90d      	bls.n	8005bca <HAL_FDCAN_Init+0xe6>
+    {
+      /* Update error code */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+ 8005bae:	687b      	ldr	r3, [r7, #4]
+ 8005bb0:	f8d3 309c 	ldr.w	r3, [r3, #156]	; 0x9c
+ 8005bb4:	f043 0201 	orr.w	r2, r3, #1
+ 8005bb8:	687b      	ldr	r3, [r7, #4]
+ 8005bba:	f8c3 209c 	str.w	r2, [r3, #156]	; 0x9c
+
+      /* Change FDCAN state */
+      hfdcan->State = HAL_FDCAN_STATE_ERROR;
+ 8005bbe:	687b      	ldr	r3, [r7, #4]
+ 8005bc0:	2203      	movs	r2, #3
+ 8005bc2:	f883 2098 	strb.w	r2, [r3, #152]	; 0x98
+
+      return HAL_ERROR;
+ 8005bc6:	2301      	movs	r3, #1
+ 8005bc8:	e164      	b.n	8005e94 <HAL_FDCAN_Init+0x3b0>
+  while ((hfdcan->Instance->CCCR & FDCAN_CCCR_INIT) == 0U)
+ 8005bca:	687b      	ldr	r3, [r7, #4]
+ 8005bcc:	681b      	ldr	r3, [r3, #0]
+ 8005bce:	699b      	ldr	r3, [r3, #24]
+ 8005bd0:	f003 0301 	and.w	r3, r3, #1
+ 8005bd4:	2b00      	cmp	r3, #0
+ 8005bd6:	d0e3      	beq.n	8005ba0 <HAL_FDCAN_Init+0xbc>
+    }
+  }
+
+  /* Enable configuration change */
+  SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_CCE);
+ 8005bd8:	687b      	ldr	r3, [r7, #4]
+ 8005bda:	681b      	ldr	r3, [r3, #0]
+ 8005bdc:	699a      	ldr	r2, [r3, #24]
+ 8005bde:	687b      	ldr	r3, [r7, #4]
+ 8005be0:	681b      	ldr	r3, [r3, #0]
+ 8005be2:	f042 0202 	orr.w	r2, r2, #2
+ 8005be6:	619a      	str	r2, [r3, #24]
+
+  /* Set the no automatic retransmission */
+  if (hfdcan->Init.AutoRetransmission == ENABLE)
+ 8005be8:	687b      	ldr	r3, [r7, #4]
+ 8005bea:	7c1b      	ldrb	r3, [r3, #16]
+ 8005bec:	2b01      	cmp	r3, #1
+ 8005bee:	d108      	bne.n	8005c02 <HAL_FDCAN_Init+0x11e>
+  {
+    CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_DAR);
+ 8005bf0:	687b      	ldr	r3, [r7, #4]
+ 8005bf2:	681b      	ldr	r3, [r3, #0]
+ 8005bf4:	699a      	ldr	r2, [r3, #24]
+ 8005bf6:	687b      	ldr	r3, [r7, #4]
+ 8005bf8:	681b      	ldr	r3, [r3, #0]
+ 8005bfa:	f022 0240 	bic.w	r2, r2, #64	; 0x40
+ 8005bfe:	619a      	str	r2, [r3, #24]
+ 8005c00:	e007      	b.n	8005c12 <HAL_FDCAN_Init+0x12e>
+  }
+  else
+  {
+    SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_DAR);
+ 8005c02:	687b      	ldr	r3, [r7, #4]
+ 8005c04:	681b      	ldr	r3, [r3, #0]
+ 8005c06:	699a      	ldr	r2, [r3, #24]
+ 8005c08:	687b      	ldr	r3, [r7, #4]
+ 8005c0a:	681b      	ldr	r3, [r3, #0]
+ 8005c0c:	f042 0240 	orr.w	r2, r2, #64	; 0x40
+ 8005c10:	619a      	str	r2, [r3, #24]
+  }
+
+  /* Set the transmit pause feature */
+  if (hfdcan->Init.TransmitPause == ENABLE)
+ 8005c12:	687b      	ldr	r3, [r7, #4]
+ 8005c14:	7c5b      	ldrb	r3, [r3, #17]
+ 8005c16:	2b01      	cmp	r3, #1
+ 8005c18:	d108      	bne.n	8005c2c <HAL_FDCAN_Init+0x148>
+  {
+    SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_TXP);
+ 8005c1a:	687b      	ldr	r3, [r7, #4]
+ 8005c1c:	681b      	ldr	r3, [r3, #0]
+ 8005c1e:	699a      	ldr	r2, [r3, #24]
+ 8005c20:	687b      	ldr	r3, [r7, #4]
+ 8005c22:	681b      	ldr	r3, [r3, #0]
+ 8005c24:	f442 4280 	orr.w	r2, r2, #16384	; 0x4000
+ 8005c28:	619a      	str	r2, [r3, #24]
+ 8005c2a:	e007      	b.n	8005c3c <HAL_FDCAN_Init+0x158>
+  }
+  else
+  {
+    CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_TXP);
+ 8005c2c:	687b      	ldr	r3, [r7, #4]
+ 8005c2e:	681b      	ldr	r3, [r3, #0]
+ 8005c30:	699a      	ldr	r2, [r3, #24]
+ 8005c32:	687b      	ldr	r3, [r7, #4]
+ 8005c34:	681b      	ldr	r3, [r3, #0]
+ 8005c36:	f422 4280 	bic.w	r2, r2, #16384	; 0x4000
+ 8005c3a:	619a      	str	r2, [r3, #24]
+  }
+
+  /* Set the Protocol Exception Handling */
+  if (hfdcan->Init.ProtocolException == ENABLE)
+ 8005c3c:	687b      	ldr	r3, [r7, #4]
+ 8005c3e:	7c9b      	ldrb	r3, [r3, #18]
+ 8005c40:	2b01      	cmp	r3, #1
+ 8005c42:	d108      	bne.n	8005c56 <HAL_FDCAN_Init+0x172>
+  {
+    CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_PXHD);
+ 8005c44:	687b      	ldr	r3, [r7, #4]
+ 8005c46:	681b      	ldr	r3, [r3, #0]
+ 8005c48:	699a      	ldr	r2, [r3, #24]
+ 8005c4a:	687b      	ldr	r3, [r7, #4]
+ 8005c4c:	681b      	ldr	r3, [r3, #0]
+ 8005c4e:	f422 5280 	bic.w	r2, r2, #4096	; 0x1000
+ 8005c52:	619a      	str	r2, [r3, #24]
+ 8005c54:	e007      	b.n	8005c66 <HAL_FDCAN_Init+0x182>
+  }
+  else
+  {
+    SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_PXHD);
+ 8005c56:	687b      	ldr	r3, [r7, #4]
+ 8005c58:	681b      	ldr	r3, [r3, #0]
+ 8005c5a:	699a      	ldr	r2, [r3, #24]
+ 8005c5c:	687b      	ldr	r3, [r7, #4]
+ 8005c5e:	681b      	ldr	r3, [r3, #0]
+ 8005c60:	f442 5280 	orr.w	r2, r2, #4096	; 0x1000
+ 8005c64:	619a      	str	r2, [r3, #24]
+  }
+
+  /* Set FDCAN Frame Format */
+  MODIFY_REG(hfdcan->Instance->CCCR, FDCAN_FRAME_FD_BRS, hfdcan->Init.FrameFormat);
+ 8005c66:	687b      	ldr	r3, [r7, #4]
+ 8005c68:	681b      	ldr	r3, [r3, #0]
+ 8005c6a:	699b      	ldr	r3, [r3, #24]
+ 8005c6c:	f423 7140 	bic.w	r1, r3, #768	; 0x300
+ 8005c70:	687b      	ldr	r3, [r7, #4]
+ 8005c72:	689a      	ldr	r2, [r3, #8]
+ 8005c74:	687b      	ldr	r3, [r7, #4]
+ 8005c76:	681b      	ldr	r3, [r3, #0]
+ 8005c78:	430a      	orrs	r2, r1
+ 8005c7a:	619a      	str	r2, [r3, #24]
+
+  /* Reset FDCAN Operation Mode */
+  CLEAR_BIT(hfdcan->Instance->CCCR, (FDCAN_CCCR_TEST | FDCAN_CCCR_MON | FDCAN_CCCR_ASM));
+ 8005c7c:	687b      	ldr	r3, [r7, #4]
+ 8005c7e:	681b      	ldr	r3, [r3, #0]
+ 8005c80:	699a      	ldr	r2, [r3, #24]
+ 8005c82:	687b      	ldr	r3, [r7, #4]
+ 8005c84:	681b      	ldr	r3, [r3, #0]
+ 8005c86:	f022 02a4 	bic.w	r2, r2, #164	; 0xa4
+ 8005c8a:	619a      	str	r2, [r3, #24]
+  CLEAR_BIT(hfdcan->Instance->TEST, FDCAN_TEST_LBCK);
+ 8005c8c:	687b      	ldr	r3, [r7, #4]
+ 8005c8e:	681b      	ldr	r3, [r3, #0]
+ 8005c90:	691a      	ldr	r2, [r3, #16]
+ 8005c92:	687b      	ldr	r3, [r7, #4]
+ 8005c94:	681b      	ldr	r3, [r3, #0]
+ 8005c96:	f022 0210 	bic.w	r2, r2, #16
+ 8005c9a:	611a      	str	r2, [r3, #16]
+     CCCR.TEST |   0    |     0      |     0      |    1     |    1
+     CCCR.MON  |   0    |     0      |     1      |    1     |    0
+     TEST.LBCK |   0    |     0      |     0      |    1     |    1
+     CCCR.ASM  |   0    |     1      |     0      |    0     |    0
+  */
+  if (hfdcan->Init.Mode == FDCAN_MODE_RESTRICTED_OPERATION)
+ 8005c9c:	687b      	ldr	r3, [r7, #4]
+ 8005c9e:	68db      	ldr	r3, [r3, #12]
+ 8005ca0:	2b01      	cmp	r3, #1
+ 8005ca2:	d108      	bne.n	8005cb6 <HAL_FDCAN_Init+0x1d2>
+  {
+    /* Enable Restricted Operation mode */
+    SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_ASM);
+ 8005ca4:	687b      	ldr	r3, [r7, #4]
+ 8005ca6:	681b      	ldr	r3, [r3, #0]
+ 8005ca8:	699a      	ldr	r2, [r3, #24]
+ 8005caa:	687b      	ldr	r3, [r7, #4]
+ 8005cac:	681b      	ldr	r3, [r3, #0]
+ 8005cae:	f042 0204 	orr.w	r2, r2, #4
+ 8005cb2:	619a      	str	r2, [r3, #24]
+ 8005cb4:	e030      	b.n	8005d18 <HAL_FDCAN_Init+0x234>
+  }
+  else if (hfdcan->Init.Mode != FDCAN_MODE_NORMAL)
+ 8005cb6:	687b      	ldr	r3, [r7, #4]
+ 8005cb8:	68db      	ldr	r3, [r3, #12]
+ 8005cba:	2b00      	cmp	r3, #0
+ 8005cbc:	d02c      	beq.n	8005d18 <HAL_FDCAN_Init+0x234>
+  {
+    if (hfdcan->Init.Mode != FDCAN_MODE_BUS_MONITORING)
+ 8005cbe:	687b      	ldr	r3, [r7, #4]
+ 8005cc0:	68db      	ldr	r3, [r3, #12]
+ 8005cc2:	2b02      	cmp	r3, #2
+ 8005cc4:	d020      	beq.n	8005d08 <HAL_FDCAN_Init+0x224>
+    {
+      /* Enable write access to TEST register */
+      SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_TEST);
+ 8005cc6:	687b      	ldr	r3, [r7, #4]
+ 8005cc8:	681b      	ldr	r3, [r3, #0]
+ 8005cca:	699a      	ldr	r2, [r3, #24]
+ 8005ccc:	687b      	ldr	r3, [r7, #4]
+ 8005cce:	681b      	ldr	r3, [r3, #0]
+ 8005cd0:	f042 0280 	orr.w	r2, r2, #128	; 0x80
+ 8005cd4:	619a      	str	r2, [r3, #24]
+
+      /* Enable LoopBack mode */
+      SET_BIT(hfdcan->Instance->TEST, FDCAN_TEST_LBCK);
+ 8005cd6:	687b      	ldr	r3, [r7, #4]
+ 8005cd8:	681b      	ldr	r3, [r3, #0]
+ 8005cda:	691a      	ldr	r2, [r3, #16]
+ 8005cdc:	687b      	ldr	r3, [r7, #4]
+ 8005cde:	681b      	ldr	r3, [r3, #0]
+ 8005ce0:	f042 0210 	orr.w	r2, r2, #16
+ 8005ce4:	611a      	str	r2, [r3, #16]
+
+      if (hfdcan->Init.Mode == FDCAN_MODE_INTERNAL_LOOPBACK)
+ 8005ce6:	687b      	ldr	r3, [r7, #4]
+ 8005ce8:	68db      	ldr	r3, [r3, #12]
+ 8005cea:	2b03      	cmp	r3, #3
+ 8005cec:	d114      	bne.n	8005d18 <HAL_FDCAN_Init+0x234>
+      {
+        SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_MON);
+ 8005cee:	687b      	ldr	r3, [r7, #4]
+ 8005cf0:	681b      	ldr	r3, [r3, #0]
+ 8005cf2:	699a      	ldr	r2, [r3, #24]
+ 8005cf4:	687b      	ldr	r3, [r7, #4]
+ 8005cf6:	681b      	ldr	r3, [r3, #0]
+ 8005cf8:	f042 0220 	orr.w	r2, r2, #32
+ 8005cfc:	619a      	str	r2, [r3, #24]
+ 8005cfe:	e00b      	b.n	8005d18 <HAL_FDCAN_Init+0x234>
+ 8005d00:	08022e38 	.word	0x08022e38
+ 8005d04:	4000a000 	.word	0x4000a000
+      }
+    }
+    else
+    {
+      /* Enable bus monitoring mode */
+      SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_MON);
+ 8005d08:	687b      	ldr	r3, [r7, #4]
+ 8005d0a:	681b      	ldr	r3, [r3, #0]
+ 8005d0c:	699a      	ldr	r2, [r3, #24]
+ 8005d0e:	687b      	ldr	r3, [r7, #4]
+ 8005d10:	681b      	ldr	r3, [r3, #0]
+ 8005d12:	f042 0220 	orr.w	r2, r2, #32
+ 8005d16:	619a      	str	r2, [r3, #24]
+  {
+    /* Nothing to do: normal mode */
+  }
+
+  /* Set the nominal bit timing register */
+  hfdcan->Instance->NBTP = ((((uint32_t)hfdcan->Init.NominalSyncJumpWidth - 1U) << FDCAN_NBTP_NSJW_Pos) | \
+ 8005d18:	687b      	ldr	r3, [r7, #4]
+ 8005d1a:	699b      	ldr	r3, [r3, #24]
+ 8005d1c:	3b01      	subs	r3, #1
+ 8005d1e:	065a      	lsls	r2, r3, #25
+                            (((uint32_t)hfdcan->Init.NominalTimeSeg1 - 1U) << FDCAN_NBTP_NTSEG1_Pos)    | \
+ 8005d20:	687b      	ldr	r3, [r7, #4]
+ 8005d22:	69db      	ldr	r3, [r3, #28]
+ 8005d24:	3b01      	subs	r3, #1
+ 8005d26:	021b      	lsls	r3, r3, #8
+  hfdcan->Instance->NBTP = ((((uint32_t)hfdcan->Init.NominalSyncJumpWidth - 1U) << FDCAN_NBTP_NSJW_Pos) | \
+ 8005d28:	431a      	orrs	r2, r3
+                            (((uint32_t)hfdcan->Init.NominalTimeSeg2 - 1U) << FDCAN_NBTP_NTSEG2_Pos)    | \
+ 8005d2a:	687b      	ldr	r3, [r7, #4]
+ 8005d2c:	6a1b      	ldr	r3, [r3, #32]
+ 8005d2e:	3b01      	subs	r3, #1
+                            (((uint32_t)hfdcan->Init.NominalTimeSeg1 - 1U) << FDCAN_NBTP_NTSEG1_Pos)    | \
+ 8005d30:	ea42 0103 	orr.w	r1, r2, r3
+                            (((uint32_t)hfdcan->Init.NominalPrescaler - 1U) << FDCAN_NBTP_NBRP_Pos));
+ 8005d34:	687b      	ldr	r3, [r7, #4]
+ 8005d36:	695b      	ldr	r3, [r3, #20]
+ 8005d38:	3b01      	subs	r3, #1
+ 8005d3a:	041a      	lsls	r2, r3, #16
+  hfdcan->Instance->NBTP = ((((uint32_t)hfdcan->Init.NominalSyncJumpWidth - 1U) << FDCAN_NBTP_NSJW_Pos) | \
+ 8005d3c:	687b      	ldr	r3, [r7, #4]
+ 8005d3e:	681b      	ldr	r3, [r3, #0]
+                            (((uint32_t)hfdcan->Init.NominalTimeSeg2 - 1U) << FDCAN_NBTP_NTSEG2_Pos)    | \
+ 8005d40:	430a      	orrs	r2, r1
+  hfdcan->Instance->NBTP = ((((uint32_t)hfdcan->Init.NominalSyncJumpWidth - 1U) << FDCAN_NBTP_NSJW_Pos) | \
+ 8005d42:	61da      	str	r2, [r3, #28]
+
+  /* If FD operation with BRS is selected, set the data bit timing register */
+  if (hfdcan->Init.FrameFormat == FDCAN_FRAME_FD_BRS)
+ 8005d44:	687b      	ldr	r3, [r7, #4]
+ 8005d46:	689b      	ldr	r3, [r3, #8]
+ 8005d48:	f5b3 7f40 	cmp.w	r3, #768	; 0x300
+ 8005d4c:	d115      	bne.n	8005d7a <HAL_FDCAN_Init+0x296>
+  {
+    hfdcan->Instance->DBTP = ((((uint32_t)hfdcan->Init.DataSyncJumpWidth - 1U) << FDCAN_DBTP_DSJW_Pos) | \
+ 8005d4e:	687b      	ldr	r3, [r7, #4]
+ 8005d50:	6a9b      	ldr	r3, [r3, #40]	; 0x28
+ 8005d52:	1e5a      	subs	r2, r3, #1
+                              (((uint32_t)hfdcan->Init.DataTimeSeg1 - 1U) << FDCAN_DBTP_DTSEG1_Pos)    | \
+ 8005d54:	687b      	ldr	r3, [r7, #4]
+ 8005d56:	6adb      	ldr	r3, [r3, #44]	; 0x2c
+ 8005d58:	3b01      	subs	r3, #1
+ 8005d5a:	021b      	lsls	r3, r3, #8
+    hfdcan->Instance->DBTP = ((((uint32_t)hfdcan->Init.DataSyncJumpWidth - 1U) << FDCAN_DBTP_DSJW_Pos) | \
+ 8005d5c:	431a      	orrs	r2, r3
+                              (((uint32_t)hfdcan->Init.DataTimeSeg2 - 1U) << FDCAN_DBTP_DTSEG2_Pos)    | \
+ 8005d5e:	687b      	ldr	r3, [r7, #4]
+ 8005d60:	6b1b      	ldr	r3, [r3, #48]	; 0x30
+ 8005d62:	3b01      	subs	r3, #1
+ 8005d64:	011b      	lsls	r3, r3, #4
+                              (((uint32_t)hfdcan->Init.DataTimeSeg1 - 1U) << FDCAN_DBTP_DTSEG1_Pos)    | \
+ 8005d66:	ea42 0103 	orr.w	r1, r2, r3
+                              (((uint32_t)hfdcan->Init.DataPrescaler - 1U) << FDCAN_DBTP_DBRP_Pos));
+ 8005d6a:	687b      	ldr	r3, [r7, #4]
+ 8005d6c:	6a5b      	ldr	r3, [r3, #36]	; 0x24
+ 8005d6e:	3b01      	subs	r3, #1
+ 8005d70:	041a      	lsls	r2, r3, #16
+    hfdcan->Instance->DBTP = ((((uint32_t)hfdcan->Init.DataSyncJumpWidth - 1U) << FDCAN_DBTP_DSJW_Pos) | \
+ 8005d72:	687b      	ldr	r3, [r7, #4]
+ 8005d74:	681b      	ldr	r3, [r3, #0]
+                              (((uint32_t)hfdcan->Init.DataTimeSeg2 - 1U) << FDCAN_DBTP_DTSEG2_Pos)    | \
+ 8005d76:	430a      	orrs	r2, r1
+    hfdcan->Instance->DBTP = ((((uint32_t)hfdcan->Init.DataSyncJumpWidth - 1U) << FDCAN_DBTP_DSJW_Pos) | \
+ 8005d78:	60da      	str	r2, [r3, #12]
+  }
+
+  if (hfdcan->Init.TxFifoQueueElmtsNbr > 0U)
+ 8005d7a:	687b      	ldr	r3, [r7, #4]
+ 8005d7c:	6e1b      	ldr	r3, [r3, #96]	; 0x60
+ 8005d7e:	2b00      	cmp	r3, #0
+ 8005d80:	d00a      	beq.n	8005d98 <HAL_FDCAN_Init+0x2b4>
+  {
+    /* Select between Tx FIFO and Tx Queue operation modes */
+    SET_BIT(hfdcan->Instance->TXBC, hfdcan->Init.TxFifoQueueMode);
+ 8005d82:	687b      	ldr	r3, [r7, #4]
+ 8005d84:	681b      	ldr	r3, [r3, #0]
+ 8005d86:	f8d3 10c0 	ldr.w	r1, [r3, #192]	; 0xc0
+ 8005d8a:	687b      	ldr	r3, [r7, #4]
+ 8005d8c:	6e5a      	ldr	r2, [r3, #100]	; 0x64
+ 8005d8e:	687b      	ldr	r3, [r7, #4]
+ 8005d90:	681b      	ldr	r3, [r3, #0]
+ 8005d92:	430a      	orrs	r2, r1
+ 8005d94:	f8c3 20c0 	str.w	r2, [r3, #192]	; 0xc0
+  }
+
+  /* Configure Tx element size */
+  if ((hfdcan->Init.TxBuffersNbr + hfdcan->Init.TxFifoQueueElmtsNbr) > 0U)
+ 8005d98:	687b      	ldr	r3, [r7, #4]
+ 8005d9a:	6dda      	ldr	r2, [r3, #92]	; 0x5c
+ 8005d9c:	687b      	ldr	r3, [r7, #4]
+ 8005d9e:	6e1b      	ldr	r3, [r3, #96]	; 0x60
+ 8005da0:	4413      	add	r3, r2
+ 8005da2:	2b00      	cmp	r3, #0
+ 8005da4:	d011      	beq.n	8005dca <HAL_FDCAN_Init+0x2e6>
+  {
+    MODIFY_REG(hfdcan->Instance->TXESC, FDCAN_TXESC_TBDS, CvtEltSize[hfdcan->Init.TxElmtSize]);
+ 8005da6:	687b      	ldr	r3, [r7, #4]
+ 8005da8:	681b      	ldr	r3, [r3, #0]
+ 8005daa:	f8d3 30c8 	ldr.w	r3, [r3, #200]	; 0xc8
+ 8005dae:	f023 0107 	bic.w	r1, r3, #7
+ 8005db2:	687b      	ldr	r3, [r7, #4]
+ 8005db4:	6e9b      	ldr	r3, [r3, #104]	; 0x68
+ 8005db6:	009b      	lsls	r3, r3, #2
+ 8005db8:	3360      	adds	r3, #96	; 0x60
+ 8005dba:	443b      	add	r3, r7
+ 8005dbc:	f853 2c54 	ldr.w	r2, [r3, #-84]
+ 8005dc0:	687b      	ldr	r3, [r7, #4]
+ 8005dc2:	681b      	ldr	r3, [r3, #0]
+ 8005dc4:	430a      	orrs	r2, r1
+ 8005dc6:	f8c3 20c8 	str.w	r2, [r3, #200]	; 0xc8
+  }
+
+  /* Configure Rx FIFO 0 element size */
+  if (hfdcan->Init.RxFifo0ElmtsNbr > 0U)
+ 8005dca:	687b      	ldr	r3, [r7, #4]
+ 8005dcc:	6c1b      	ldr	r3, [r3, #64]	; 0x40
+ 8005dce:	2b00      	cmp	r3, #0
+ 8005dd0:	d011      	beq.n	8005df6 <HAL_FDCAN_Init+0x312>
+  {
+    MODIFY_REG(hfdcan->Instance->RXESC, FDCAN_RXESC_F0DS, (CvtEltSize[hfdcan->Init.RxFifo0ElmtSize] << FDCAN_RXESC_F0DS_Pos));
+ 8005dd2:	687b      	ldr	r3, [r7, #4]
+ 8005dd4:	681b      	ldr	r3, [r3, #0]
+ 8005dd6:	f8d3 30bc 	ldr.w	r3, [r3, #188]	; 0xbc
+ 8005dda:	f023 0107 	bic.w	r1, r3, #7
+ 8005dde:	687b      	ldr	r3, [r7, #4]
+ 8005de0:	6c5b      	ldr	r3, [r3, #68]	; 0x44
+ 8005de2:	009b      	lsls	r3, r3, #2
+ 8005de4:	3360      	adds	r3, #96	; 0x60
+ 8005de6:	443b      	add	r3, r7
+ 8005de8:	f853 2c54 	ldr.w	r2, [r3, #-84]
+ 8005dec:	687b      	ldr	r3, [r7, #4]
+ 8005dee:	681b      	ldr	r3, [r3, #0]
+ 8005df0:	430a      	orrs	r2, r1
+ 8005df2:	f8c3 20bc 	str.w	r2, [r3, #188]	; 0xbc
+  }
+
+  /* Configure Rx FIFO 1 element size */
+  if (hfdcan->Init.RxFifo1ElmtsNbr > 0U)
+ 8005df6:	687b      	ldr	r3, [r7, #4]
+ 8005df8:	6c9b      	ldr	r3, [r3, #72]	; 0x48
+ 8005dfa:	2b00      	cmp	r3, #0
+ 8005dfc:	d012      	beq.n	8005e24 <HAL_FDCAN_Init+0x340>
+  {
+    MODIFY_REG(hfdcan->Instance->RXESC, FDCAN_RXESC_F1DS, (CvtEltSize[hfdcan->Init.RxFifo1ElmtSize] << FDCAN_RXESC_F1DS_Pos));
+ 8005dfe:	687b      	ldr	r3, [r7, #4]
+ 8005e00:	681b      	ldr	r3, [r3, #0]
+ 8005e02:	f8d3 30bc 	ldr.w	r3, [r3, #188]	; 0xbc
+ 8005e06:	f023 0170 	bic.w	r1, r3, #112	; 0x70
+ 8005e0a:	687b      	ldr	r3, [r7, #4]
+ 8005e0c:	6cdb      	ldr	r3, [r3, #76]	; 0x4c
+ 8005e0e:	009b      	lsls	r3, r3, #2
+ 8005e10:	3360      	adds	r3, #96	; 0x60
+ 8005e12:	443b      	add	r3, r7
+ 8005e14:	f853 3c54 	ldr.w	r3, [r3, #-84]
+ 8005e18:	011a      	lsls	r2, r3, #4
+ 8005e1a:	687b      	ldr	r3, [r7, #4]
+ 8005e1c:	681b      	ldr	r3, [r3, #0]
+ 8005e1e:	430a      	orrs	r2, r1
+ 8005e20:	f8c3 20bc 	str.w	r2, [r3, #188]	; 0xbc
+  }
+
+  /* Configure Rx buffer element size */
+  if (hfdcan->Init.RxBuffersNbr > 0U)
+ 8005e24:	687b      	ldr	r3, [r7, #4]
+ 8005e26:	6d1b      	ldr	r3, [r3, #80]	; 0x50
+ 8005e28:	2b00      	cmp	r3, #0
+ 8005e2a:	d012      	beq.n	8005e52 <HAL_FDCAN_Init+0x36e>
+  {
+    MODIFY_REG(hfdcan->Instance->RXESC, FDCAN_RXESC_RBDS, (CvtEltSize[hfdcan->Init.RxBufferSize] << FDCAN_RXESC_RBDS_Pos));
+ 8005e2c:	687b      	ldr	r3, [r7, #4]
+ 8005e2e:	681b      	ldr	r3, [r3, #0]
+ 8005e30:	f8d3 30bc 	ldr.w	r3, [r3, #188]	; 0xbc
+ 8005e34:	f423 61e0 	bic.w	r1, r3, #1792	; 0x700
+ 8005e38:	687b      	ldr	r3, [r7, #4]
+ 8005e3a:	6d5b      	ldr	r3, [r3, #84]	; 0x54
+ 8005e3c:	009b      	lsls	r3, r3, #2
+ 8005e3e:	3360      	adds	r3, #96	; 0x60
+ 8005e40:	443b      	add	r3, r7
+ 8005e42:	f853 3c54 	ldr.w	r3, [r3, #-84]
+ 8005e46:	021a      	lsls	r2, r3, #8
+ 8005e48:	687b      	ldr	r3, [r7, #4]
+ 8005e4a:	681b      	ldr	r3, [r3, #0]
+ 8005e4c:	430a      	orrs	r2, r1
+ 8005e4e:	f8c3 20bc 	str.w	r2, [r3, #188]	; 0xbc
+  }
+
+  /* By default operation mode is set to Event-driven communication.
+     If Time-triggered communication is needed, user should call the
+     HAL_FDCAN_TT_ConfigOperation function just after the HAL_FDCAN_Init */
+  if (hfdcan->Instance == FDCAN1)
+ 8005e52:	687b      	ldr	r3, [r7, #4]
+ 8005e54:	681b      	ldr	r3, [r3, #0]
+ 8005e56:	4a11      	ldr	r2, [pc, #68]	; (8005e9c <HAL_FDCAN_Init+0x3b8>)
+ 8005e58:	4293      	cmp	r3, r2
+ 8005e5a:	d107      	bne.n	8005e6c <HAL_FDCAN_Init+0x388>
+  {
+    CLEAR_BIT(hfdcan->ttcan->TTOCF, FDCAN_TTOCF_OM);
+ 8005e5c:	687b      	ldr	r3, [r7, #4]
+ 8005e5e:	685b      	ldr	r3, [r3, #4]
+ 8005e60:	689a      	ldr	r2, [r3, #8]
+ 8005e62:	687b      	ldr	r3, [r7, #4]
+ 8005e64:	685b      	ldr	r3, [r3, #4]
+ 8005e66:	f022 0203 	bic.w	r2, r2, #3
+ 8005e6a:	609a      	str	r2, [r3, #8]
+  }
+
+  /* Initialize the Latest Tx FIFO/Queue request buffer index */
+  hfdcan->LatestTxFifoQRequest = 0U;
+ 8005e6c:	687b      	ldr	r3, [r7, #4]
+ 8005e6e:	2200      	movs	r2, #0
+ 8005e70:	f8c3 2094 	str.w	r2, [r3, #148]	; 0x94
+
+  /* Initialize the error code */
+  hfdcan->ErrorCode = HAL_FDCAN_ERROR_NONE;
+ 8005e74:	687b      	ldr	r3, [r7, #4]
+ 8005e76:	2200      	movs	r2, #0
+ 8005e78:	f8c3 209c 	str.w	r2, [r3, #156]	; 0x9c
+
+  /* Initialize the FDCAN state */
+  hfdcan->State = HAL_FDCAN_STATE_READY;
+ 8005e7c:	687b      	ldr	r3, [r7, #4]
+ 8005e7e:	2201      	movs	r2, #1
+ 8005e80:	f883 2098 	strb.w	r2, [r3, #152]	; 0x98
+
+  /* Calculate each RAM block address */
+  status = FDCAN_CalcultateRamBlockAddresses(hfdcan);
+ 8005e84:	6878      	ldr	r0, [r7, #4]
+ 8005e86:	f000 fb0d 	bl	80064a4 <FDCAN_CalcultateRamBlockAddresses>
+ 8005e8a:	4603      	mov	r3, r0
+ 8005e8c:	f887 305b 	strb.w	r3, [r7, #91]	; 0x5b
+
+  /* Return function status */
+  return status;
+ 8005e90:	f897 305b 	ldrb.w	r3, [r7, #91]	; 0x5b
+}
+ 8005e94:	4618      	mov	r0, r3
+ 8005e96:	3760      	adds	r7, #96	; 0x60
+ 8005e98:	46bd      	mov	sp, r7
+ 8005e9a:	bd80      	pop	{r7, pc}
+ 8005e9c:	4000a000 	.word	0x4000a000
+
+08005ea0 <HAL_FDCAN_IRQHandler>:
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+void HAL_FDCAN_IRQHandler(FDCAN_HandleTypeDef *hfdcan)
+{
+ 8005ea0:	b580      	push	{r7, lr}
+ 8005ea2:	b096      	sub	sp, #88	; 0x58
+ 8005ea4:	af00      	add	r7, sp, #0
+ 8005ea6:	6078      	str	r0, [r7, #4]
+  uint32_t itsourceIE;
+  uint32_t itsourceTTIE;
+  uint32_t itflagIR;
+  uint32_t itflagTTIR;
+
+  ClkCalibrationITs = (FDCAN_CCU->IR << 30);
+ 8005ea8:	4b95      	ldr	r3, [pc, #596]	; (8006100 <HAL_FDCAN_IRQHandler+0x260>)
+ 8005eaa:	691b      	ldr	r3, [r3, #16]
+ 8005eac:	079b      	lsls	r3, r3, #30
+ 8005eae:	657b      	str	r3, [r7, #84]	; 0x54
+  ClkCalibrationITs &= (FDCAN_CCU->IE << 30);
+ 8005eb0:	4b93      	ldr	r3, [pc, #588]	; (8006100 <HAL_FDCAN_IRQHandler+0x260>)
+ 8005eb2:	695b      	ldr	r3, [r3, #20]
+ 8005eb4:	079b      	lsls	r3, r3, #30
+ 8005eb6:	6d7a      	ldr	r2, [r7, #84]	; 0x54
+ 8005eb8:	4013      	ands	r3, r2
+ 8005eba:	657b      	str	r3, [r7, #84]	; 0x54
+  TxEventFifoITs = hfdcan->Instance->IR & FDCAN_TX_EVENT_FIFO_MASK;
+ 8005ebc:	687b      	ldr	r3, [r7, #4]
+ 8005ebe:	681b      	ldr	r3, [r3, #0]
+ 8005ec0:	6d1b      	ldr	r3, [r3, #80]	; 0x50
+ 8005ec2:	f403 4370 	and.w	r3, r3, #61440	; 0xf000
+ 8005ec6:	653b      	str	r3, [r7, #80]	; 0x50
+  TxEventFifoITs &= hfdcan->Instance->IE;
+ 8005ec8:	687b      	ldr	r3, [r7, #4]
+ 8005eca:	681b      	ldr	r3, [r3, #0]
+ 8005ecc:	6d5b      	ldr	r3, [r3, #84]	; 0x54
+ 8005ece:	6d3a      	ldr	r2, [r7, #80]	; 0x50
+ 8005ed0:	4013      	ands	r3, r2
+ 8005ed2:	653b      	str	r3, [r7, #80]	; 0x50
+  RxFifo0ITs = hfdcan->Instance->IR & FDCAN_RX_FIFO0_MASK;
+ 8005ed4:	687b      	ldr	r3, [r7, #4]
+ 8005ed6:	681b      	ldr	r3, [r3, #0]
+ 8005ed8:	6d1b      	ldr	r3, [r3, #80]	; 0x50
+ 8005eda:	f003 030f 	and.w	r3, r3, #15
+ 8005ede:	64fb      	str	r3, [r7, #76]	; 0x4c
+  RxFifo0ITs &= hfdcan->Instance->IE;
+ 8005ee0:	687b      	ldr	r3, [r7, #4]
+ 8005ee2:	681b      	ldr	r3, [r3, #0]
+ 8005ee4:	6d5b      	ldr	r3, [r3, #84]	; 0x54
+ 8005ee6:	6cfa      	ldr	r2, [r7, #76]	; 0x4c
+ 8005ee8:	4013      	ands	r3, r2
+ 8005eea:	64fb      	str	r3, [r7, #76]	; 0x4c
+  RxFifo1ITs = hfdcan->Instance->IR & FDCAN_RX_FIFO1_MASK;
+ 8005eec:	687b      	ldr	r3, [r7, #4]
+ 8005eee:	681b      	ldr	r3, [r3, #0]
+ 8005ef0:	6d1b      	ldr	r3, [r3, #80]	; 0x50
+ 8005ef2:	f003 03f0 	and.w	r3, r3, #240	; 0xf0
+ 8005ef6:	64bb      	str	r3, [r7, #72]	; 0x48
+  RxFifo1ITs &= hfdcan->Instance->IE;
+ 8005ef8:	687b      	ldr	r3, [r7, #4]
+ 8005efa:	681b      	ldr	r3, [r3, #0]
+ 8005efc:	6d5b      	ldr	r3, [r3, #84]	; 0x54
+ 8005efe:	6cba      	ldr	r2, [r7, #72]	; 0x48
+ 8005f00:	4013      	ands	r3, r2
+ 8005f02:	64bb      	str	r3, [r7, #72]	; 0x48
+  Errors = hfdcan->Instance->IR & FDCAN_ERROR_MASK;
+ 8005f04:	687b      	ldr	r3, [r7, #4]
+ 8005f06:	681b      	ldr	r3, [r3, #0]
+ 8005f08:	6d1b      	ldr	r3, [r3, #80]	; 0x50
+ 8005f0a:	f003 5371 	and.w	r3, r3, #1010827264	; 0x3c400000
+ 8005f0e:	647b      	str	r3, [r7, #68]	; 0x44
+  Errors &= hfdcan->Instance->IE;
+ 8005f10:	687b      	ldr	r3, [r7, #4]
+ 8005f12:	681b      	ldr	r3, [r3, #0]
+ 8005f14:	6d5b      	ldr	r3, [r3, #84]	; 0x54
+ 8005f16:	6c7a      	ldr	r2, [r7, #68]	; 0x44
+ 8005f18:	4013      	ands	r3, r2
+ 8005f1a:	647b      	str	r3, [r7, #68]	; 0x44
+  ErrorStatusITs = hfdcan->Instance->IR & FDCAN_ERROR_STATUS_MASK;
+ 8005f1c:	687b      	ldr	r3, [r7, #4]
+ 8005f1e:	681b      	ldr	r3, [r3, #0]
+ 8005f20:	6d1b      	ldr	r3, [r3, #80]	; 0x50
+ 8005f22:	f003 7360 	and.w	r3, r3, #58720256	; 0x3800000
+ 8005f26:	643b      	str	r3, [r7, #64]	; 0x40
+  ErrorStatusITs &= hfdcan->Instance->IE;
+ 8005f28:	687b      	ldr	r3, [r7, #4]
+ 8005f2a:	681b      	ldr	r3, [r3, #0]
+ 8005f2c:	6d5b      	ldr	r3, [r3, #84]	; 0x54
+ 8005f2e:	6c3a      	ldr	r2, [r7, #64]	; 0x40
+ 8005f30:	4013      	ands	r3, r2
+ 8005f32:	643b      	str	r3, [r7, #64]	; 0x40
+  itsourceIE = hfdcan->Instance->IE;
+ 8005f34:	687b      	ldr	r3, [r7, #4]
+ 8005f36:	681b      	ldr	r3, [r3, #0]
+ 8005f38:	6d5b      	ldr	r3, [r3, #84]	; 0x54
+ 8005f3a:	63fb      	str	r3, [r7, #60]	; 0x3c
+  itflagIR = hfdcan->Instance->IR;
+ 8005f3c:	687b      	ldr	r3, [r7, #4]
+ 8005f3e:	681b      	ldr	r3, [r3, #0]
+ 8005f40:	6d1b      	ldr	r3, [r3, #80]	; 0x50
+ 8005f42:	63bb      	str	r3, [r7, #56]	; 0x38
+
+  /* High Priority Message interrupt management *******************************/
+  if (FDCAN_CHECK_IT_SOURCE(itsourceIE, FDCAN_IT_RX_HIGH_PRIORITY_MSG) != RESET)
+ 8005f44:	6bfb      	ldr	r3, [r7, #60]	; 0x3c
+ 8005f46:	f403 7380 	and.w	r3, r3, #256	; 0x100
+ 8005f4a:	2b00      	cmp	r3, #0
+ 8005f4c:	d00f      	beq.n	8005f6e <HAL_FDCAN_IRQHandler+0xce>
+  {
+    if (FDCAN_CHECK_FLAG(itflagIR, FDCAN_FLAG_RX_HIGH_PRIORITY_MSG) != RESET)
+ 8005f4e:	6bbb      	ldr	r3, [r7, #56]	; 0x38
+ 8005f50:	f403 7380 	and.w	r3, r3, #256	; 0x100
+ 8005f54:	2b00      	cmp	r3, #0
+ 8005f56:	d00a      	beq.n	8005f6e <HAL_FDCAN_IRQHandler+0xce>
+    {
+      /* Clear the High Priority Message flag */
+      __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_RX_HIGH_PRIORITY_MSG);
+ 8005f58:	687b      	ldr	r3, [r7, #4]
+ 8005f5a:	681b      	ldr	r3, [r3, #0]
+ 8005f5c:	f44f 7280 	mov.w	r2, #256	; 0x100
+ 8005f60:	651a      	str	r2, [r3, #80]	; 0x50
+ 8005f62:	4b67      	ldr	r3, [pc, #412]	; (8006100 <HAL_FDCAN_IRQHandler+0x260>)
+ 8005f64:	2200      	movs	r2, #0
+ 8005f66:	611a      	str	r2, [r3, #16]
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+      /* Call registered callback*/
+      hfdcan->HighPriorityMessageCallback(hfdcan);
+#else
+      /* High Priority Message Callback */
+      HAL_FDCAN_HighPriorityMessageCallback(hfdcan);
+ 8005f68:	6878      	ldr	r0, [r7, #4]
+ 8005f6a:	f000 fa4f 	bl	800640c <HAL_FDCAN_HighPriorityMessageCallback>
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+    }
+  }
+
+  /* Transmission Abort interrupt management **********************************/
+  if (FDCAN_CHECK_IT_SOURCE(itsourceIE, FDCAN_IT_TX_ABORT_COMPLETE) != RESET)
+ 8005f6e:	6bfb      	ldr	r3, [r7, #60]	; 0x3c
+ 8005f70:	f403 6380 	and.w	r3, r3, #1024	; 0x400
+ 8005f74:	2b00      	cmp	r3, #0
+ 8005f76:	d01c      	beq.n	8005fb2 <HAL_FDCAN_IRQHandler+0x112>
+  {
+    if (FDCAN_CHECK_FLAG(itflagIR, FDCAN_FLAG_TX_ABORT_COMPLETE) != RESET)
+ 8005f78:	6bbb      	ldr	r3, [r7, #56]	; 0x38
+ 8005f7a:	f403 6380 	and.w	r3, r3, #1024	; 0x400
+ 8005f7e:	2b00      	cmp	r3, #0
+ 8005f80:	d017      	beq.n	8005fb2 <HAL_FDCAN_IRQHandler+0x112>
+    {
+      /* List of aborted monitored buffers */
+      AbortedBuffers = hfdcan->Instance->TXBCF;
+ 8005f82:	687b      	ldr	r3, [r7, #4]
+ 8005f84:	681b      	ldr	r3, [r3, #0]
+ 8005f86:	f8d3 30dc 	ldr.w	r3, [r3, #220]	; 0xdc
+ 8005f8a:	637b      	str	r3, [r7, #52]	; 0x34
+      AbortedBuffers &= hfdcan->Instance->TXBCIE;
+ 8005f8c:	687b      	ldr	r3, [r7, #4]
+ 8005f8e:	681b      	ldr	r3, [r3, #0]
+ 8005f90:	f8d3 30e4 	ldr.w	r3, [r3, #228]	; 0xe4
+ 8005f94:	6b7a      	ldr	r2, [r7, #52]	; 0x34
+ 8005f96:	4013      	ands	r3, r2
+ 8005f98:	637b      	str	r3, [r7, #52]	; 0x34
+
+      /* Clear the Transmission Cancellation flag */
+      __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TX_ABORT_COMPLETE);
+ 8005f9a:	687b      	ldr	r3, [r7, #4]
+ 8005f9c:	681b      	ldr	r3, [r3, #0]
+ 8005f9e:	f44f 6280 	mov.w	r2, #1024	; 0x400
+ 8005fa2:	651a      	str	r2, [r3, #80]	; 0x50
+ 8005fa4:	4b56      	ldr	r3, [pc, #344]	; (8006100 <HAL_FDCAN_IRQHandler+0x260>)
+ 8005fa6:	2200      	movs	r2, #0
+ 8005fa8:	611a      	str	r2, [r3, #16]
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+      /* Call registered callback*/
+      hfdcan->TxBufferAbortCallback(hfdcan, AbortedBuffers);
+#else
+      /* Transmission Cancellation Callback */
+      HAL_FDCAN_TxBufferAbortCallback(hfdcan, AbortedBuffers);
+ 8005faa:	6b79      	ldr	r1, [r7, #52]	; 0x34
+ 8005fac:	6878      	ldr	r0, [r7, #4]
+ 8005fae:	f000 fa04 	bl	80063ba <HAL_FDCAN_TxBufferAbortCallback>
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+    }
+  }
+
+  /* Clock calibration unit interrupts management *****************************/
+  if (ClkCalibrationITs != 0U)
+ 8005fb2:	6d7b      	ldr	r3, [r7, #84]	; 0x54
+ 8005fb4:	2b00      	cmp	r3, #0
+ 8005fb6:	d00d      	beq.n	8005fd4 <HAL_FDCAN_IRQHandler+0x134>
+  {
+    /* Clear the Clock Calibration flags */
+    __HAL_FDCAN_CLEAR_FLAG(hfdcan, ClkCalibrationITs);
+ 8005fb8:	687b      	ldr	r3, [r7, #4]
+ 8005fba:	681a      	ldr	r2, [r3, #0]
+ 8005fbc:	6d79      	ldr	r1, [r7, #84]	; 0x54
+ 8005fbe:	4b51      	ldr	r3, [pc, #324]	; (8006104 <HAL_FDCAN_IRQHandler+0x264>)
+ 8005fc0:	400b      	ands	r3, r1
+ 8005fc2:	6513      	str	r3, [r2, #80]	; 0x50
+ 8005fc4:	4a4e      	ldr	r2, [pc, #312]	; (8006100 <HAL_FDCAN_IRQHandler+0x260>)
+ 8005fc6:	6d7b      	ldr	r3, [r7, #84]	; 0x54
+ 8005fc8:	0f9b      	lsrs	r3, r3, #30
+ 8005fca:	6113      	str	r3, [r2, #16]
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+    /* Call registered callback*/
+    hfdcan->ClockCalibrationCallback(hfdcan, ClkCalibrationITs);
+#else
+    /* Clock Calibration Callback */
+    HAL_FDCAN_ClockCalibrationCallback(hfdcan, ClkCalibrationITs);
+ 8005fcc:	6d79      	ldr	r1, [r7, #84]	; 0x54
+ 8005fce:	6878      	ldr	r0, [r7, #4]
+ 8005fd0:	f000 f9b2 	bl	8006338 <HAL_FDCAN_ClockCalibrationCallback>
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+  }
+
+  /* Tx event FIFO interrupts management **************************************/
+  if (TxEventFifoITs != 0U)
+ 8005fd4:	6d3b      	ldr	r3, [r7, #80]	; 0x50
+ 8005fd6:	2b00      	cmp	r3, #0
+ 8005fd8:	d00d      	beq.n	8005ff6 <HAL_FDCAN_IRQHandler+0x156>
+  {
+    /* Clear the Tx Event FIFO flags */
+    __HAL_FDCAN_CLEAR_FLAG(hfdcan, TxEventFifoITs);
+ 8005fda:	687b      	ldr	r3, [r7, #4]
+ 8005fdc:	681a      	ldr	r2, [r3, #0]
+ 8005fde:	6d39      	ldr	r1, [r7, #80]	; 0x50
+ 8005fe0:	4b48      	ldr	r3, [pc, #288]	; (8006104 <HAL_FDCAN_IRQHandler+0x264>)
+ 8005fe2:	400b      	ands	r3, r1
+ 8005fe4:	6513      	str	r3, [r2, #80]	; 0x50
+ 8005fe6:	4a46      	ldr	r2, [pc, #280]	; (8006100 <HAL_FDCAN_IRQHandler+0x260>)
+ 8005fe8:	6d3b      	ldr	r3, [r7, #80]	; 0x50
+ 8005fea:	0f9b      	lsrs	r3, r3, #30
+ 8005fec:	6113      	str	r3, [r2, #16]
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+    /* Call registered callback*/
+    hfdcan->TxEventFifoCallback(hfdcan, TxEventFifoITs);
+#else
+    /* Tx Event FIFO Callback */
+    HAL_FDCAN_TxEventFifoCallback(hfdcan, TxEventFifoITs);
+ 8005fee:	6d39      	ldr	r1, [r7, #80]	; 0x50
+ 8005ff0:	6878      	ldr	r0, [r7, #4]
+ 8005ff2:	f000 f9ac 	bl	800634e <HAL_FDCAN_TxEventFifoCallback>
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+  }
+
+  /* Rx FIFO 0 interrupts management ******************************************/
+  if (RxFifo0ITs != 0U)
+ 8005ff6:	6cfb      	ldr	r3, [r7, #76]	; 0x4c
+ 8005ff8:	2b00      	cmp	r3, #0
+ 8005ffa:	d00d      	beq.n	8006018 <HAL_FDCAN_IRQHandler+0x178>
+  {
+    /* Clear the Rx FIFO 0 flags */
+    __HAL_FDCAN_CLEAR_FLAG(hfdcan, RxFifo0ITs);
+ 8005ffc:	687b      	ldr	r3, [r7, #4]
+ 8005ffe:	681a      	ldr	r2, [r3, #0]
+ 8006000:	6cf9      	ldr	r1, [r7, #76]	; 0x4c
+ 8006002:	4b40      	ldr	r3, [pc, #256]	; (8006104 <HAL_FDCAN_IRQHandler+0x264>)
+ 8006004:	400b      	ands	r3, r1
+ 8006006:	6513      	str	r3, [r2, #80]	; 0x50
+ 8006008:	4a3d      	ldr	r2, [pc, #244]	; (8006100 <HAL_FDCAN_IRQHandler+0x260>)
+ 800600a:	6cfb      	ldr	r3, [r7, #76]	; 0x4c
+ 800600c:	0f9b      	lsrs	r3, r3, #30
+ 800600e:	6113      	str	r3, [r2, #16]
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+    /* Call registered callback*/
+    hfdcan->RxFifo0Callback(hfdcan, RxFifo0ITs);
+#else
+    /* Rx FIFO 0 Callback */
+    HAL_FDCAN_RxFifo0Callback(hfdcan, RxFifo0ITs);
+ 8006010:	6cf9      	ldr	r1, [r7, #76]	; 0x4c
+ 8006012:	6878      	ldr	r0, [r7, #4]
+ 8006014:	f000 f9a6 	bl	8006364 <HAL_FDCAN_RxFifo0Callback>
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+  }
+
+  /* Rx FIFO 1 interrupts management ******************************************/
+  if (RxFifo1ITs != 0U)
+ 8006018:	6cbb      	ldr	r3, [r7, #72]	; 0x48
+ 800601a:	2b00      	cmp	r3, #0
+ 800601c:	d00d      	beq.n	800603a <HAL_FDCAN_IRQHandler+0x19a>
+  {
+    /* Clear the Rx FIFO 1 flags */
+    __HAL_FDCAN_CLEAR_FLAG(hfdcan, RxFifo1ITs);
+ 800601e:	687b      	ldr	r3, [r7, #4]
+ 8006020:	681a      	ldr	r2, [r3, #0]
+ 8006022:	6cb9      	ldr	r1, [r7, #72]	; 0x48
+ 8006024:	4b37      	ldr	r3, [pc, #220]	; (8006104 <HAL_FDCAN_IRQHandler+0x264>)
+ 8006026:	400b      	ands	r3, r1
+ 8006028:	6513      	str	r3, [r2, #80]	; 0x50
+ 800602a:	4a35      	ldr	r2, [pc, #212]	; (8006100 <HAL_FDCAN_IRQHandler+0x260>)
+ 800602c:	6cbb      	ldr	r3, [r7, #72]	; 0x48
+ 800602e:	0f9b      	lsrs	r3, r3, #30
+ 8006030:	6113      	str	r3, [r2, #16]
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+    /* Call registered callback*/
+    hfdcan->RxFifo1Callback(hfdcan, RxFifo1ITs);
+#else
+    /* Rx FIFO 1 Callback */
+    HAL_FDCAN_RxFifo1Callback(hfdcan, RxFifo1ITs);
+ 8006032:	6cb9      	ldr	r1, [r7, #72]	; 0x48
+ 8006034:	6878      	ldr	r0, [r7, #4]
+ 8006036:	f000 f9a0 	bl	800637a <HAL_FDCAN_RxFifo1Callback>
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+  }
+
+  /* Tx FIFO empty interrupt management ***************************************/
+  if (FDCAN_CHECK_IT_SOURCE(itsourceIE, FDCAN_IT_TX_FIFO_EMPTY) != RESET)
+ 800603a:	6bfb      	ldr	r3, [r7, #60]	; 0x3c
+ 800603c:	f403 6300 	and.w	r3, r3, #2048	; 0x800
+ 8006040:	2b00      	cmp	r3, #0
+ 8006042:	d00f      	beq.n	8006064 <HAL_FDCAN_IRQHandler+0x1c4>
+  {
+    if (FDCAN_CHECK_FLAG(itflagIR, FDCAN_FLAG_TX_FIFO_EMPTY) != RESET)
+ 8006044:	6bbb      	ldr	r3, [r7, #56]	; 0x38
+ 8006046:	f403 6300 	and.w	r3, r3, #2048	; 0x800
+ 800604a:	2b00      	cmp	r3, #0
+ 800604c:	d00a      	beq.n	8006064 <HAL_FDCAN_IRQHandler+0x1c4>
+    {
+      /* Clear the Tx FIFO empty flag */
+      __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TX_FIFO_EMPTY);
+ 800604e:	687b      	ldr	r3, [r7, #4]
+ 8006050:	681b      	ldr	r3, [r3, #0]
+ 8006052:	f44f 6200 	mov.w	r2, #2048	; 0x800
+ 8006056:	651a      	str	r2, [r3, #80]	; 0x50
+ 8006058:	4b29      	ldr	r3, [pc, #164]	; (8006100 <HAL_FDCAN_IRQHandler+0x260>)
+ 800605a:	2200      	movs	r2, #0
+ 800605c:	611a      	str	r2, [r3, #16]
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+      /* Call registered callback*/
+      hfdcan->TxFifoEmptyCallback(hfdcan);
+#else
+      /* Tx FIFO empty Callback */
+      HAL_FDCAN_TxFifoEmptyCallback(hfdcan);
+ 800605e:	6878      	ldr	r0, [r7, #4]
+ 8006060:	f000 f996 	bl	8006390 <HAL_FDCAN_TxFifoEmptyCallback>
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+    }
+  }
+
+  /* Transmission Complete interrupt management *******************************/
+  if (FDCAN_CHECK_IT_SOURCE(itsourceIE, FDCAN_IT_TX_COMPLETE) != RESET)
+ 8006064:	6bfb      	ldr	r3, [r7, #60]	; 0x3c
+ 8006066:	f403 7300 	and.w	r3, r3, #512	; 0x200
+ 800606a:	2b00      	cmp	r3, #0
+ 800606c:	d01c      	beq.n	80060a8 <HAL_FDCAN_IRQHandler+0x208>
+  {
+    if (FDCAN_CHECK_FLAG(itflagIR, FDCAN_FLAG_TX_COMPLETE) != RESET)
+ 800606e:	6bbb      	ldr	r3, [r7, #56]	; 0x38
+ 8006070:	f403 7300 	and.w	r3, r3, #512	; 0x200
+ 8006074:	2b00      	cmp	r3, #0
+ 8006076:	d017      	beq.n	80060a8 <HAL_FDCAN_IRQHandler+0x208>
+    {
+      /* List of transmitted monitored buffers */
+      TransmittedBuffers = hfdcan->Instance->TXBTO;
+ 8006078:	687b      	ldr	r3, [r7, #4]
+ 800607a:	681b      	ldr	r3, [r3, #0]
+ 800607c:	f8d3 30d8 	ldr.w	r3, [r3, #216]	; 0xd8
+ 8006080:	633b      	str	r3, [r7, #48]	; 0x30
+      TransmittedBuffers &= hfdcan->Instance->TXBTIE;
+ 8006082:	687b      	ldr	r3, [r7, #4]
+ 8006084:	681b      	ldr	r3, [r3, #0]
+ 8006086:	f8d3 30e0 	ldr.w	r3, [r3, #224]	; 0xe0
+ 800608a:	6b3a      	ldr	r2, [r7, #48]	; 0x30
+ 800608c:	4013      	ands	r3, r2
+ 800608e:	633b      	str	r3, [r7, #48]	; 0x30
+
+      /* Clear the Transmission Complete flag */
+      __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TX_COMPLETE);
+ 8006090:	687b      	ldr	r3, [r7, #4]
+ 8006092:	681b      	ldr	r3, [r3, #0]
+ 8006094:	f44f 7200 	mov.w	r2, #512	; 0x200
+ 8006098:	651a      	str	r2, [r3, #80]	; 0x50
+ 800609a:	4b19      	ldr	r3, [pc, #100]	; (8006100 <HAL_FDCAN_IRQHandler+0x260>)
+ 800609c:	2200      	movs	r2, #0
+ 800609e:	611a      	str	r2, [r3, #16]
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+      /* Call registered callback*/
+      hfdcan->TxBufferCompleteCallback(hfdcan, TransmittedBuffers);
+#else
+      /* Transmission Complete Callback */
+      HAL_FDCAN_TxBufferCompleteCallback(hfdcan, TransmittedBuffers);
+ 80060a0:	6b39      	ldr	r1, [r7, #48]	; 0x30
+ 80060a2:	6878      	ldr	r0, [r7, #4]
+ 80060a4:	f000 f97e 	bl	80063a4 <HAL_FDCAN_TxBufferCompleteCallback>
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+    }
+  }
+
+  /* Rx Buffer New Message interrupt management *******************************/
+  if (FDCAN_CHECK_IT_SOURCE(itsourceIE, FDCAN_IT_RX_BUFFER_NEW_MESSAGE) != RESET)
+ 80060a8:	6bfb      	ldr	r3, [r7, #60]	; 0x3c
+ 80060aa:	f403 2300 	and.w	r3, r3, #524288	; 0x80000
+ 80060ae:	2b00      	cmp	r3, #0
+ 80060b0:	d00f      	beq.n	80060d2 <HAL_FDCAN_IRQHandler+0x232>
+  {
+    if (FDCAN_CHECK_FLAG(itflagIR, FDCAN_FLAG_RX_BUFFER_NEW_MESSAGE) != RESET)
+ 80060b2:	6bbb      	ldr	r3, [r7, #56]	; 0x38
+ 80060b4:	f403 2300 	and.w	r3, r3, #524288	; 0x80000
+ 80060b8:	2b00      	cmp	r3, #0
+ 80060ba:	d00a      	beq.n	80060d2 <HAL_FDCAN_IRQHandler+0x232>
+    {
+      /* Clear the Rx Buffer New Message flag */
+      __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_RX_BUFFER_NEW_MESSAGE);
+ 80060bc:	687b      	ldr	r3, [r7, #4]
+ 80060be:	681b      	ldr	r3, [r3, #0]
+ 80060c0:	f44f 2200 	mov.w	r2, #524288	; 0x80000
+ 80060c4:	651a      	str	r2, [r3, #80]	; 0x50
+ 80060c6:	4b0e      	ldr	r3, [pc, #56]	; (8006100 <HAL_FDCAN_IRQHandler+0x260>)
+ 80060c8:	2200      	movs	r2, #0
+ 80060ca:	611a      	str	r2, [r3, #16]
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+      /* Call registered callback*/
+      hfdcan->RxBufferNewMessageCallback(hfdcan);
+#else
+      /* Rx Buffer New Message Callback */
+      HAL_FDCAN_RxBufferNewMessageCallback(hfdcan);
+ 80060cc:	6878      	ldr	r0, [r7, #4]
+ 80060ce:	f000 f97f 	bl	80063d0 <HAL_FDCAN_RxBufferNewMessageCallback>
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+    }
+  }
+
+  /* Timestamp Wraparound interrupt management ********************************/
+  if (FDCAN_CHECK_IT_SOURCE(itsourceIE, FDCAN_IT_TIMESTAMP_WRAPAROUND) != RESET)
+ 80060d2:	6bfb      	ldr	r3, [r7, #60]	; 0x3c
+ 80060d4:	f403 3380 	and.w	r3, r3, #65536	; 0x10000
+ 80060d8:	2b00      	cmp	r3, #0
+ 80060da:	d015      	beq.n	8006108 <HAL_FDCAN_IRQHandler+0x268>
+  {
+    if (FDCAN_CHECK_FLAG(itflagIR, FDCAN_FLAG_TIMESTAMP_WRAPAROUND) != RESET)
+ 80060dc:	6bbb      	ldr	r3, [r7, #56]	; 0x38
+ 80060de:	f403 3380 	and.w	r3, r3, #65536	; 0x10000
+ 80060e2:	2b00      	cmp	r3, #0
+ 80060e4:	d010      	beq.n	8006108 <HAL_FDCAN_IRQHandler+0x268>
+    {
+      /* Clear the Timestamp Wraparound flag */
+      __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TIMESTAMP_WRAPAROUND);
+ 80060e6:	687b      	ldr	r3, [r7, #4]
+ 80060e8:	681b      	ldr	r3, [r3, #0]
+ 80060ea:	f44f 3280 	mov.w	r2, #65536	; 0x10000
+ 80060ee:	651a      	str	r2, [r3, #80]	; 0x50
+ 80060f0:	4b03      	ldr	r3, [pc, #12]	; (8006100 <HAL_FDCAN_IRQHandler+0x260>)
+ 80060f2:	2200      	movs	r2, #0
+ 80060f4:	611a      	str	r2, [r3, #16]
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+      /* Call registered callback*/
+      hfdcan->TimestampWraparoundCallback(hfdcan);
+#else
+      /* Timestamp Wraparound Callback */
+      HAL_FDCAN_TimestampWraparoundCallback(hfdcan);
+ 80060f6:	6878      	ldr	r0, [r7, #4]
+ 80060f8:	f000 f974 	bl	80063e4 <HAL_FDCAN_TimestampWraparoundCallback>
+ 80060fc:	e004      	b.n	8006108 <HAL_FDCAN_IRQHandler+0x268>
+ 80060fe:	bf00      	nop
+ 8006100:	4000a800 	.word	0x4000a800
+ 8006104:	3fcfffff 	.word	0x3fcfffff
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+    }
+  }
+
+  /* Timeout Occurred interrupt management ************************************/
+  if (FDCAN_CHECK_IT_SOURCE(itsourceIE, FDCAN_IT_TIMEOUT_OCCURRED) != RESET)
+ 8006108:	6bfb      	ldr	r3, [r7, #60]	; 0x3c
+ 800610a:	f403 2380 	and.w	r3, r3, #262144	; 0x40000
+ 800610e:	2b00      	cmp	r3, #0
+ 8006110:	d00f      	beq.n	8006132 <HAL_FDCAN_IRQHandler+0x292>
+  {
+    if (FDCAN_CHECK_FLAG(itflagIR, FDCAN_FLAG_TIMEOUT_OCCURRED) != RESET)
+ 8006112:	6bbb      	ldr	r3, [r7, #56]	; 0x38
+ 8006114:	f403 2380 	and.w	r3, r3, #262144	; 0x40000
+ 8006118:	2b00      	cmp	r3, #0
+ 800611a:	d00a      	beq.n	8006132 <HAL_FDCAN_IRQHandler+0x292>
+    {
+      /* Clear the Timeout Occurred flag */
+      __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TIMEOUT_OCCURRED);
+ 800611c:	687b      	ldr	r3, [r7, #4]
+ 800611e:	681b      	ldr	r3, [r3, #0]
+ 8006120:	f44f 2280 	mov.w	r2, #262144	; 0x40000
+ 8006124:	651a      	str	r2, [r3, #80]	; 0x50
+ 8006126:	4b81      	ldr	r3, [pc, #516]	; (800632c <HAL_FDCAN_IRQHandler+0x48c>)
+ 8006128:	2200      	movs	r2, #0
+ 800612a:	611a      	str	r2, [r3, #16]
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+      /* Call registered callback*/
+      hfdcan->TimeoutOccurredCallback(hfdcan);
+#else
+      /* Timeout Occurred Callback */
+      HAL_FDCAN_TimeoutOccurredCallback(hfdcan);
+ 800612c:	6878      	ldr	r0, [r7, #4]
+ 800612e:	f000 f963 	bl	80063f8 <HAL_FDCAN_TimeoutOccurredCallback>
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+    }
+  }
+
+  /* Message RAM access failure interrupt management **************************/
+  if (FDCAN_CHECK_IT_SOURCE(itsourceIE, FDCAN_IT_RAM_ACCESS_FAILURE) != RESET)
+ 8006132:	6bfb      	ldr	r3, [r7, #60]	; 0x3c
+ 8006134:	f403 3300 	and.w	r3, r3, #131072	; 0x20000
+ 8006138:	2b00      	cmp	r3, #0
+ 800613a:	d014      	beq.n	8006166 <HAL_FDCAN_IRQHandler+0x2c6>
+  {
+    if (FDCAN_CHECK_FLAG(itflagIR, FDCAN_FLAG_RAM_ACCESS_FAILURE) != RESET)
+ 800613c:	6bbb      	ldr	r3, [r7, #56]	; 0x38
+ 800613e:	f403 3300 	and.w	r3, r3, #131072	; 0x20000
+ 8006142:	2b00      	cmp	r3, #0
+ 8006144:	d00f      	beq.n	8006166 <HAL_FDCAN_IRQHandler+0x2c6>
+    {
+      /* Clear the Message RAM access failure flag */
+      __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_RAM_ACCESS_FAILURE);
+ 8006146:	687b      	ldr	r3, [r7, #4]
+ 8006148:	681b      	ldr	r3, [r3, #0]
+ 800614a:	f44f 3200 	mov.w	r2, #131072	; 0x20000
+ 800614e:	651a      	str	r2, [r3, #80]	; 0x50
+ 8006150:	4b76      	ldr	r3, [pc, #472]	; (800632c <HAL_FDCAN_IRQHandler+0x48c>)
+ 8006152:	2200      	movs	r2, #0
+ 8006154:	611a      	str	r2, [r3, #16]
+
+      /* Update error code */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_RAM_ACCESS;
+ 8006156:	687b      	ldr	r3, [r7, #4]
+ 8006158:	f8d3 309c 	ldr.w	r3, [r3, #156]	; 0x9c
+ 800615c:	f043 0280 	orr.w	r2, r3, #128	; 0x80
+ 8006160:	687b      	ldr	r3, [r7, #4]
+ 8006162:	f8c3 209c 	str.w	r2, [r3, #156]	; 0x9c
+    }
+  }
+
+  /* Error Status interrupts management ***************************************/
+  if (ErrorStatusITs != 0U)
+ 8006166:	6c3b      	ldr	r3, [r7, #64]	; 0x40
+ 8006168:	2b00      	cmp	r3, #0
+ 800616a:	d00d      	beq.n	8006188 <HAL_FDCAN_IRQHandler+0x2e8>
+  {
+    /* Clear the Error flags */
+    __HAL_FDCAN_CLEAR_FLAG(hfdcan, ErrorStatusITs);
+ 800616c:	687b      	ldr	r3, [r7, #4]
+ 800616e:	681a      	ldr	r2, [r3, #0]
+ 8006170:	6c39      	ldr	r1, [r7, #64]	; 0x40
+ 8006172:	4b6f      	ldr	r3, [pc, #444]	; (8006330 <HAL_FDCAN_IRQHandler+0x490>)
+ 8006174:	400b      	ands	r3, r1
+ 8006176:	6513      	str	r3, [r2, #80]	; 0x50
+ 8006178:	4a6c      	ldr	r2, [pc, #432]	; (800632c <HAL_FDCAN_IRQHandler+0x48c>)
+ 800617a:	6c3b      	ldr	r3, [r7, #64]	; 0x40
+ 800617c:	0f9b      	lsrs	r3, r3, #30
+ 800617e:	6113      	str	r3, [r2, #16]
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+    /* Call registered callback*/
+    hfdcan->ErrorStatusCallback(hfdcan, ErrorStatusITs);
+#else
+    /* Error Status Callback */
+    HAL_FDCAN_ErrorStatusCallback(hfdcan, ErrorStatusITs);
+ 8006180:	6c39      	ldr	r1, [r7, #64]	; 0x40
+ 8006182:	6878      	ldr	r0, [r7, #4]
+ 8006184:	f000 f956 	bl	8006434 <HAL_FDCAN_ErrorStatusCallback>
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+  }
+
+  /* Error interrupts management **********************************************/
+  if (Errors != 0U)
+ 8006188:	6c7b      	ldr	r3, [r7, #68]	; 0x44
+ 800618a:	2b00      	cmp	r3, #0
+ 800618c:	d011      	beq.n	80061b2 <HAL_FDCAN_IRQHandler+0x312>
+  {
+    /* Clear the Error flags */
+    __HAL_FDCAN_CLEAR_FLAG(hfdcan, Errors);
+ 800618e:	687b      	ldr	r3, [r7, #4]
+ 8006190:	681a      	ldr	r2, [r3, #0]
+ 8006192:	6c79      	ldr	r1, [r7, #68]	; 0x44
+ 8006194:	4b66      	ldr	r3, [pc, #408]	; (8006330 <HAL_FDCAN_IRQHandler+0x490>)
+ 8006196:	400b      	ands	r3, r1
+ 8006198:	6513      	str	r3, [r2, #80]	; 0x50
+ 800619a:	4a64      	ldr	r2, [pc, #400]	; (800632c <HAL_FDCAN_IRQHandler+0x48c>)
+ 800619c:	6c7b      	ldr	r3, [r7, #68]	; 0x44
+ 800619e:	0f9b      	lsrs	r3, r3, #30
+ 80061a0:	6113      	str	r3, [r2, #16]
+
+    /* Update error code */
+    hfdcan->ErrorCode |= Errors;
+ 80061a2:	687b      	ldr	r3, [r7, #4]
+ 80061a4:	f8d3 209c 	ldr.w	r2, [r3, #156]	; 0x9c
+ 80061a8:	6c7b      	ldr	r3, [r7, #68]	; 0x44
+ 80061aa:	431a      	orrs	r2, r3
+ 80061ac:	687b      	ldr	r3, [r7, #4]
+ 80061ae:	f8c3 209c 	str.w	r2, [r3, #156]	; 0x9c
+  }
+
+  if (hfdcan->Instance == FDCAN1)
+ 80061b2:	687b      	ldr	r3, [r7, #4]
+ 80061b4:	681b      	ldr	r3, [r3, #0]
+ 80061b6:	4a5f      	ldr	r2, [pc, #380]	; (8006334 <HAL_FDCAN_IRQHandler+0x494>)
+ 80061b8:	4293      	cmp	r3, r2
+ 80061ba:	f040 80aa 	bne.w	8006312 <HAL_FDCAN_IRQHandler+0x472>
+  {
+    if ((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_OM) != 0U)
+ 80061be:	687b      	ldr	r3, [r7, #4]
+ 80061c0:	685b      	ldr	r3, [r3, #4]
+ 80061c2:	689b      	ldr	r3, [r3, #8]
+ 80061c4:	f003 0303 	and.w	r3, r3, #3
+ 80061c8:	2b00      	cmp	r3, #0
+ 80061ca:	f000 80a2 	beq.w	8006312 <HAL_FDCAN_IRQHandler+0x472>
+    {
+      TTSchedSyncITs = hfdcan->ttcan->TTIR & FDCAN_TT_SCHEDULE_SYNC_MASK;
+ 80061ce:	687b      	ldr	r3, [r7, #4]
+ 80061d0:	685b      	ldr	r3, [r3, #4]
+ 80061d2:	6a1b      	ldr	r3, [r3, #32]
+ 80061d4:	f003 030f 	and.w	r3, r3, #15
+ 80061d8:	62fb      	str	r3, [r7, #44]	; 0x2c
+      TTSchedSyncITs &= hfdcan->ttcan->TTIE;
+ 80061da:	687b      	ldr	r3, [r7, #4]
+ 80061dc:	685b      	ldr	r3, [r3, #4]
+ 80061de:	6a5b      	ldr	r3, [r3, #36]	; 0x24
+ 80061e0:	6afa      	ldr	r2, [r7, #44]	; 0x2c
+ 80061e2:	4013      	ands	r3, r2
+ 80061e4:	62fb      	str	r3, [r7, #44]	; 0x2c
+      TTTimeMarkITs = hfdcan->ttcan->TTIR & FDCAN_TT_TIME_MARK_MASK;
+ 80061e6:	687b      	ldr	r3, [r7, #4]
+ 80061e8:	685b      	ldr	r3, [r3, #4]
+ 80061ea:	6a1b      	ldr	r3, [r3, #32]
+ 80061ec:	f003 0330 	and.w	r3, r3, #48	; 0x30
+ 80061f0:	62bb      	str	r3, [r7, #40]	; 0x28
+      TTTimeMarkITs &= hfdcan->ttcan->TTIE;
+ 80061f2:	687b      	ldr	r3, [r7, #4]
+ 80061f4:	685b      	ldr	r3, [r3, #4]
+ 80061f6:	6a5b      	ldr	r3, [r3, #36]	; 0x24
+ 80061f8:	6aba      	ldr	r2, [r7, #40]	; 0x28
+ 80061fa:	4013      	ands	r3, r2
+ 80061fc:	62bb      	str	r3, [r7, #40]	; 0x28
+      TTGlobTimeITs = hfdcan->ttcan->TTIR & FDCAN_TT_GLOBAL_TIME_MASK;
+ 80061fe:	687b      	ldr	r3, [r7, #4]
+ 8006200:	685b      	ldr	r3, [r3, #4]
+ 8006202:	6a1b      	ldr	r3, [r3, #32]
+ 8006204:	f403 73c0 	and.w	r3, r3, #384	; 0x180
+ 8006208:	627b      	str	r3, [r7, #36]	; 0x24
+      TTGlobTimeITs &= hfdcan->ttcan->TTIE;
+ 800620a:	687b      	ldr	r3, [r7, #4]
+ 800620c:	685b      	ldr	r3, [r3, #4]
+ 800620e:	6a5b      	ldr	r3, [r3, #36]	; 0x24
+ 8006210:	6a7a      	ldr	r2, [r7, #36]	; 0x24
+ 8006212:	4013      	ands	r3, r2
+ 8006214:	627b      	str	r3, [r7, #36]	; 0x24
+      TTDistErrors = hfdcan->ttcan->TTIR & FDCAN_TT_DISTURBING_ERROR_MASK;
+ 8006216:	687b      	ldr	r3, [r7, #4]
+ 8006218:	685b      	ldr	r3, [r3, #4]
+ 800621a:	6a1b      	ldr	r3, [r3, #32]
+ 800621c:	f403 43fc 	and.w	r3, r3, #32256	; 0x7e00
+ 8006220:	623b      	str	r3, [r7, #32]
+      TTDistErrors &= hfdcan->ttcan->TTIE;
+ 8006222:	687b      	ldr	r3, [r7, #4]
+ 8006224:	685b      	ldr	r3, [r3, #4]
+ 8006226:	6a5b      	ldr	r3, [r3, #36]	; 0x24
+ 8006228:	6a3a      	ldr	r2, [r7, #32]
+ 800622a:	4013      	ands	r3, r2
+ 800622c:	623b      	str	r3, [r7, #32]
+      TTFatalErrors = hfdcan->ttcan->TTIR & FDCAN_TT_FATAL_ERROR_MASK;
+ 800622e:	687b      	ldr	r3, [r7, #4]
+ 8006230:	685b      	ldr	r3, [r3, #4]
+ 8006232:	6a1b      	ldr	r3, [r3, #32]
+ 8006234:	f403 23f0 	and.w	r3, r3, #491520	; 0x78000
+ 8006238:	61fb      	str	r3, [r7, #28]
+      TTFatalErrors &= hfdcan->ttcan->TTIE;
+ 800623a:	687b      	ldr	r3, [r7, #4]
+ 800623c:	685b      	ldr	r3, [r3, #4]
+ 800623e:	6a5b      	ldr	r3, [r3, #36]	; 0x24
+ 8006240:	69fa      	ldr	r2, [r7, #28]
+ 8006242:	4013      	ands	r3, r2
+ 8006244:	61fb      	str	r3, [r7, #28]
+      itsourceTTIE = hfdcan->ttcan->TTIE;
+ 8006246:	687b      	ldr	r3, [r7, #4]
+ 8006248:	685b      	ldr	r3, [r3, #4]
+ 800624a:	6a5b      	ldr	r3, [r3, #36]	; 0x24
+ 800624c:	61bb      	str	r3, [r7, #24]
+      itflagTTIR = hfdcan->ttcan->TTIR;
+ 800624e:	687b      	ldr	r3, [r7, #4]
+ 8006250:	685b      	ldr	r3, [r3, #4]
+ 8006252:	6a1b      	ldr	r3, [r3, #32]
+ 8006254:	617b      	str	r3, [r7, #20]
+
+      /* TT Schedule Synchronization interrupts management **********************/
+      if (TTSchedSyncITs != 0U)
+ 8006256:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 8006258:	2b00      	cmp	r3, #0
+ 800625a:	d007      	beq.n	800626c <HAL_FDCAN_IRQHandler+0x3cc>
+      {
+        /* Clear the TT Schedule Synchronization flags */
+        __HAL_FDCAN_TT_CLEAR_FLAG(hfdcan, TTSchedSyncITs);
+ 800625c:	687b      	ldr	r3, [r7, #4]
+ 800625e:	685b      	ldr	r3, [r3, #4]
+ 8006260:	6afa      	ldr	r2, [r7, #44]	; 0x2c
+ 8006262:	621a      	str	r2, [r3, #32]
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+        /* Call registered callback*/
+        hfdcan->TT_ScheduleSyncCallback(hfdcan, TTSchedSyncITs);
+#else
+        /* TT Schedule Synchronization Callback */
+        HAL_FDCAN_TT_ScheduleSyncCallback(hfdcan, TTSchedSyncITs);
+ 8006264:	6af9      	ldr	r1, [r7, #44]	; 0x2c
+ 8006266:	6878      	ldr	r0, [r7, #4]
+ 8006268:	f000 f8ef 	bl	800644a <HAL_FDCAN_TT_ScheduleSyncCallback>
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+      }
+
+      /* TT Time Mark interrupts management *************************************/
+      if (TTTimeMarkITs != 0U)
+ 800626c:	6abb      	ldr	r3, [r7, #40]	; 0x28
+ 800626e:	2b00      	cmp	r3, #0
+ 8006270:	d007      	beq.n	8006282 <HAL_FDCAN_IRQHandler+0x3e2>
+      {
+        /* Clear the TT Time Mark flags */
+        __HAL_FDCAN_TT_CLEAR_FLAG(hfdcan, TTTimeMarkITs);
+ 8006272:	687b      	ldr	r3, [r7, #4]
+ 8006274:	685b      	ldr	r3, [r3, #4]
+ 8006276:	6aba      	ldr	r2, [r7, #40]	; 0x28
+ 8006278:	621a      	str	r2, [r3, #32]
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+        /* Call registered callback*/
+        hfdcan->TT_TimeMarkCallback(hfdcan, TTTimeMarkITs);
+#else
+        /* TT Time Mark Callback */
+        HAL_FDCAN_TT_TimeMarkCallback(hfdcan, TTTimeMarkITs);
+ 800627a:	6ab9      	ldr	r1, [r7, #40]	; 0x28
+ 800627c:	6878      	ldr	r0, [r7, #4]
+ 800627e:	f000 f8ef 	bl	8006460 <HAL_FDCAN_TT_TimeMarkCallback>
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+      }
+
+      /* TT Stop Watch interrupt management *************************************/
+      if (FDCAN_CHECK_IT_SOURCE(itsourceTTIE, FDCAN_TT_IT_STOP_WATCH) != RESET)
+ 8006282:	69bb      	ldr	r3, [r7, #24]
+ 8006284:	f003 0340 	and.w	r3, r3, #64	; 0x40
+ 8006288:	2b00      	cmp	r3, #0
+ 800628a:	d019      	beq.n	80062c0 <HAL_FDCAN_IRQHandler+0x420>
+      {
+        if (FDCAN_CHECK_FLAG(itflagTTIR, FDCAN_TT_FLAG_STOP_WATCH) != RESET)
+ 800628c:	697b      	ldr	r3, [r7, #20]
+ 800628e:	f003 0340 	and.w	r3, r3, #64	; 0x40
+ 8006292:	2b00      	cmp	r3, #0
+ 8006294:	d014      	beq.n	80062c0 <HAL_FDCAN_IRQHandler+0x420>
+        {
+          /* Retrieve Stop watch Time and Cycle count */
+          SWTime = ((hfdcan->ttcan->TTCPT & FDCAN_TTCPT_SWV) >> FDCAN_TTCPT_SWV_Pos);
+ 8006296:	687b      	ldr	r3, [r7, #4]
+ 8006298:	685b      	ldr	r3, [r3, #4]
+ 800629a:	6bdb      	ldr	r3, [r3, #60]	; 0x3c
+ 800629c:	0c1b      	lsrs	r3, r3, #16
+ 800629e:	b29b      	uxth	r3, r3
+ 80062a0:	613b      	str	r3, [r7, #16]
+          SWCycleCount = ((hfdcan->ttcan->TTCPT & FDCAN_TTCPT_CCV) >> FDCAN_TTCPT_CCV_Pos);
+ 80062a2:	687b      	ldr	r3, [r7, #4]
+ 80062a4:	685b      	ldr	r3, [r3, #4]
+ 80062a6:	6bdb      	ldr	r3, [r3, #60]	; 0x3c
+ 80062a8:	f003 033f 	and.w	r3, r3, #63	; 0x3f
+ 80062ac:	60fb      	str	r3, [r7, #12]
+
+          /* Clear the TT Stop Watch flag */
+          __HAL_FDCAN_TT_CLEAR_FLAG(hfdcan, FDCAN_TT_FLAG_STOP_WATCH);
+ 80062ae:	687b      	ldr	r3, [r7, #4]
+ 80062b0:	685b      	ldr	r3, [r3, #4]
+ 80062b2:	2240      	movs	r2, #64	; 0x40
+ 80062b4:	621a      	str	r2, [r3, #32]
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+          /* Call registered callback*/
+          hfdcan->TT_StopWatchCallback(hfdcan, SWTime, SWCycleCount);
+#else
+          /* TT Stop Watch Callback */
+          HAL_FDCAN_TT_StopWatchCallback(hfdcan, SWTime, SWCycleCount);
+ 80062b6:	68fa      	ldr	r2, [r7, #12]
+ 80062b8:	6939      	ldr	r1, [r7, #16]
+ 80062ba:	6878      	ldr	r0, [r7, #4]
+ 80062bc:	f000 f8db 	bl	8006476 <HAL_FDCAN_TT_StopWatchCallback>
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+        }
+      }
+
+      /* TT Global Time interrupts management ***********************************/
+      if (TTGlobTimeITs != 0U)
+ 80062c0:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 80062c2:	2b00      	cmp	r3, #0
+ 80062c4:	d007      	beq.n	80062d6 <HAL_FDCAN_IRQHandler+0x436>
+      {
+        /* Clear the TT Global Time flags */
+        __HAL_FDCAN_TT_CLEAR_FLAG(hfdcan, TTGlobTimeITs);
+ 80062c6:	687b      	ldr	r3, [r7, #4]
+ 80062c8:	685b      	ldr	r3, [r3, #4]
+ 80062ca:	6a7a      	ldr	r2, [r7, #36]	; 0x24
+ 80062cc:	621a      	str	r2, [r3, #32]
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+        /* Call registered callback*/
+        hfdcan->TT_GlobalTimeCallback(hfdcan, TTGlobTimeITs);
+#else
+        /* TT Global Time Callback */
+        HAL_FDCAN_TT_GlobalTimeCallback(hfdcan, TTGlobTimeITs);
+ 80062ce:	6a79      	ldr	r1, [r7, #36]	; 0x24
+ 80062d0:	6878      	ldr	r0, [r7, #4]
+ 80062d2:	f000 f8dc 	bl	800648e <HAL_FDCAN_TT_GlobalTimeCallback>
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+      }
+
+      /* TT Disturbing Error interrupts management ******************************/
+      if (TTDistErrors != 0U)
+ 80062d6:	6a3b      	ldr	r3, [r7, #32]
+ 80062d8:	2b00      	cmp	r3, #0
+ 80062da:	d00b      	beq.n	80062f4 <HAL_FDCAN_IRQHandler+0x454>
+      {
+        /* Clear the TT Disturbing Error flags */
+        __HAL_FDCAN_TT_CLEAR_FLAG(hfdcan, TTDistErrors);
+ 80062dc:	687b      	ldr	r3, [r7, #4]
+ 80062de:	685b      	ldr	r3, [r3, #4]
+ 80062e0:	6a3a      	ldr	r2, [r7, #32]
+ 80062e2:	621a      	str	r2, [r3, #32]
+
+        /* Update error code */
+        hfdcan->ErrorCode |= TTDistErrors;
+ 80062e4:	687b      	ldr	r3, [r7, #4]
+ 80062e6:	f8d3 209c 	ldr.w	r2, [r3, #156]	; 0x9c
+ 80062ea:	6a3b      	ldr	r3, [r7, #32]
+ 80062ec:	431a      	orrs	r2, r3
+ 80062ee:	687b      	ldr	r3, [r7, #4]
+ 80062f0:	f8c3 209c 	str.w	r2, [r3, #156]	; 0x9c
+      }
+
+      /* TT Fatal Error interrupts management ***********************************/
+      if (TTFatalErrors != 0U)
+ 80062f4:	69fb      	ldr	r3, [r7, #28]
+ 80062f6:	2b00      	cmp	r3, #0
+ 80062f8:	d00b      	beq.n	8006312 <HAL_FDCAN_IRQHandler+0x472>
+      {
+        /* Clear the TT Fatal Error flags */
+        __HAL_FDCAN_TT_CLEAR_FLAG(hfdcan, TTFatalErrors);
+ 80062fa:	687b      	ldr	r3, [r7, #4]
+ 80062fc:	685b      	ldr	r3, [r3, #4]
+ 80062fe:	69fa      	ldr	r2, [r7, #28]
+ 8006300:	621a      	str	r2, [r3, #32]
+
+        /* Update error code */
+        hfdcan->ErrorCode |= TTFatalErrors;
+ 8006302:	687b      	ldr	r3, [r7, #4]
+ 8006304:	f8d3 209c 	ldr.w	r2, [r3, #156]	; 0x9c
+ 8006308:	69fb      	ldr	r3, [r7, #28]
+ 800630a:	431a      	orrs	r2, r3
+ 800630c:	687b      	ldr	r3, [r7, #4]
+ 800630e:	f8c3 209c 	str.w	r2, [r3, #156]	; 0x9c
+      }
+    }
+  }
+
+  if (hfdcan->ErrorCode != HAL_FDCAN_ERROR_NONE)
+ 8006312:	687b      	ldr	r3, [r7, #4]
+ 8006314:	f8d3 309c 	ldr.w	r3, [r3, #156]	; 0x9c
+ 8006318:	2b00      	cmp	r3, #0
+ 800631a:	d002      	beq.n	8006322 <HAL_FDCAN_IRQHandler+0x482>
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+    /* Call registered callback*/
+    hfdcan->ErrorCallback(hfdcan);
+#else
+    /* Error Callback */
+    HAL_FDCAN_ErrorCallback(hfdcan);
+ 800631c:	6878      	ldr	r0, [r7, #4]
+ 800631e:	f000 f87f 	bl	8006420 <HAL_FDCAN_ErrorCallback>
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+  }
+}
+ 8006322:	bf00      	nop
+ 8006324:	3758      	adds	r7, #88	; 0x58
+ 8006326:	46bd      	mov	sp, r7
+ 8006328:	bd80      	pop	{r7, pc}
+ 800632a:	bf00      	nop
+ 800632c:	4000a800 	.word	0x4000a800
+ 8006330:	3fcfffff 	.word	0x3fcfffff
+ 8006334:	4000a000 	.word	0x4000a000
+
+08006338 <HAL_FDCAN_ClockCalibrationCallback>:
+  * @param  ClkCalibrationITs indicates which Clock Calibration interrupts are signaled.
+  *         This parameter can be any combination of @arg FDCAN_Clock_Calibration_Interrupts.
+  * @retval None
+  */
+__weak void HAL_FDCAN_ClockCalibrationCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t ClkCalibrationITs)
+{
+ 8006338:	b480      	push	{r7}
+ 800633a:	b083      	sub	sp, #12
+ 800633c:	af00      	add	r7, sp, #0
+ 800633e:	6078      	str	r0, [r7, #4]
+ 8006340:	6039      	str	r1, [r7, #0]
+  UNUSED(ClkCalibrationITs);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_ClockCalibrationCallback could be implemented in the user file
+   */
+}
+ 8006342:	bf00      	nop
+ 8006344:	370c      	adds	r7, #12
+ 8006346:	46bd      	mov	sp, r7
+ 8006348:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 800634c:	4770      	bx	lr
+
+0800634e <HAL_FDCAN_TxEventFifoCallback>:
+  * @param  TxEventFifoITs indicates which Tx Event FIFO interrupts are signaled.
+  *         This parameter can be any combination of @arg FDCAN_Tx_Event_Fifo_Interrupts.
+  * @retval None
+  */
+__weak void HAL_FDCAN_TxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TxEventFifoITs)
+{
+ 800634e:	b480      	push	{r7}
+ 8006350:	b083      	sub	sp, #12
+ 8006352:	af00      	add	r7, sp, #0
+ 8006354:	6078      	str	r0, [r7, #4]
+ 8006356:	6039      	str	r1, [r7, #0]
+  UNUSED(TxEventFifoITs);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_TxEventFifoCallback could be implemented in the user file
+   */
+}
+ 8006358:	bf00      	nop
+ 800635a:	370c      	adds	r7, #12
+ 800635c:	46bd      	mov	sp, r7
+ 800635e:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8006362:	4770      	bx	lr
+
+08006364 <HAL_FDCAN_RxFifo0Callback>:
+  * @param  RxFifo0ITs indicates which Rx FIFO 0 interrupts are signaled.
+  *         This parameter can be any combination of @arg FDCAN_Rx_Fifo0_Interrupts.
+  * @retval None
+  */
+__weak void HAL_FDCAN_RxFifo0Callback(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs)
+{
+ 8006364:	b480      	push	{r7}
+ 8006366:	b083      	sub	sp, #12
+ 8006368:	af00      	add	r7, sp, #0
+ 800636a:	6078      	str	r0, [r7, #4]
+ 800636c:	6039      	str	r1, [r7, #0]
+  UNUSED(RxFifo0ITs);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_RxFifo0Callback could be implemented in the user file
+   */
+}
+ 800636e:	bf00      	nop
+ 8006370:	370c      	adds	r7, #12
+ 8006372:	46bd      	mov	sp, r7
+ 8006374:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8006378:	4770      	bx	lr
+
+0800637a <HAL_FDCAN_RxFifo1Callback>:
+  * @param  RxFifo1ITs indicates which Rx FIFO 1 interrupts are signaled.
+  *         This parameter can be any combination of @arg FDCAN_Rx_Fifo1_Interrupts.
+  * @retval None
+  */
+__weak void HAL_FDCAN_RxFifo1Callback(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo1ITs)
+{
+ 800637a:	b480      	push	{r7}
+ 800637c:	b083      	sub	sp, #12
+ 800637e:	af00      	add	r7, sp, #0
+ 8006380:	6078      	str	r0, [r7, #4]
+ 8006382:	6039      	str	r1, [r7, #0]
+  UNUSED(RxFifo1ITs);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_RxFifo1Callback could be implemented in the user file
+   */
+}
+ 8006384:	bf00      	nop
+ 8006386:	370c      	adds	r7, #12
+ 8006388:	46bd      	mov	sp, r7
+ 800638a:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 800638e:	4770      	bx	lr
+
+08006390 <HAL_FDCAN_TxFifoEmptyCallback>:
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval None
+  */
+__weak void HAL_FDCAN_TxFifoEmptyCallback(FDCAN_HandleTypeDef *hfdcan)
+{
+ 8006390:	b480      	push	{r7}
+ 8006392:	b083      	sub	sp, #12
+ 8006394:	af00      	add	r7, sp, #0
+ 8006396:	6078      	str	r0, [r7, #4]
+  UNUSED(hfdcan);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_TxFifoEmptyCallback could be implemented in the user file
+   */
+}
+ 8006398:	bf00      	nop
+ 800639a:	370c      	adds	r7, #12
+ 800639c:	46bd      	mov	sp, r7
+ 800639e:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 80063a2:	4770      	bx	lr
+
+080063a4 <HAL_FDCAN_TxBufferCompleteCallback>:
+  * @param  BufferIndexes Indexes of the transmitted buffers.
+  *         This parameter can be any combination of @arg FDCAN_Tx_location.
+  * @retval None
+  */
+__weak void HAL_FDCAN_TxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes)
+{
+ 80063a4:	b480      	push	{r7}
+ 80063a6:	b083      	sub	sp, #12
+ 80063a8:	af00      	add	r7, sp, #0
+ 80063aa:	6078      	str	r0, [r7, #4]
+ 80063ac:	6039      	str	r1, [r7, #0]
+  UNUSED(BufferIndexes);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_TxBufferCompleteCallback could be implemented in the user file
+   */
+}
+ 80063ae:	bf00      	nop
+ 80063b0:	370c      	adds	r7, #12
+ 80063b2:	46bd      	mov	sp, r7
+ 80063b4:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 80063b8:	4770      	bx	lr
+
+080063ba <HAL_FDCAN_TxBufferAbortCallback>:
+  * @param  BufferIndexes Indexes of the aborted buffers.
+  *         This parameter can be any combination of @arg FDCAN_Tx_location.
+  * @retval None
+  */
+__weak void HAL_FDCAN_TxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes)
+{
+ 80063ba:	b480      	push	{r7}
+ 80063bc:	b083      	sub	sp, #12
+ 80063be:	af00      	add	r7, sp, #0
+ 80063c0:	6078      	str	r0, [r7, #4]
+ 80063c2:	6039      	str	r1, [r7, #0]
+  UNUSED(BufferIndexes);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_TxBufferAbortCallback could be implemented in the user file
+   */
+}
+ 80063c4:	bf00      	nop
+ 80063c6:	370c      	adds	r7, #12
+ 80063c8:	46bd      	mov	sp, r7
+ 80063ca:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 80063ce:	4770      	bx	lr
+
+080063d0 <HAL_FDCAN_RxBufferNewMessageCallback>:
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval None
+  */
+__weak void HAL_FDCAN_RxBufferNewMessageCallback(FDCAN_HandleTypeDef *hfdcan)
+{
+ 80063d0:	b480      	push	{r7}
+ 80063d2:	b083      	sub	sp, #12
+ 80063d4:	af00      	add	r7, sp, #0
+ 80063d6:	6078      	str	r0, [r7, #4]
+  UNUSED(hfdcan);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_RxBufferNewMessageCallback could be implemented in the user file
+   */
+}
+ 80063d8:	bf00      	nop
+ 80063da:	370c      	adds	r7, #12
+ 80063dc:	46bd      	mov	sp, r7
+ 80063de:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 80063e2:	4770      	bx	lr
+
+080063e4 <HAL_FDCAN_TimestampWraparoundCallback>:
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval None
+  */
+__weak void HAL_FDCAN_TimestampWraparoundCallback(FDCAN_HandleTypeDef *hfdcan)
+{
+ 80063e4:	b480      	push	{r7}
+ 80063e6:	b083      	sub	sp, #12
+ 80063e8:	af00      	add	r7, sp, #0
+ 80063ea:	6078      	str	r0, [r7, #4]
+  UNUSED(hfdcan);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_TimestampWraparoundCallback could be implemented in the user file
+   */
+}
+ 80063ec:	bf00      	nop
+ 80063ee:	370c      	adds	r7, #12
+ 80063f0:	46bd      	mov	sp, r7
+ 80063f2:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 80063f6:	4770      	bx	lr
+
+080063f8 <HAL_FDCAN_TimeoutOccurredCallback>:
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval None
+  */
+__weak void HAL_FDCAN_TimeoutOccurredCallback(FDCAN_HandleTypeDef *hfdcan)
+{
+ 80063f8:	b480      	push	{r7}
+ 80063fa:	b083      	sub	sp, #12
+ 80063fc:	af00      	add	r7, sp, #0
+ 80063fe:	6078      	str	r0, [r7, #4]
+  UNUSED(hfdcan);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_TimeoutOccurredCallback could be implemented in the user file
+   */
+}
+ 8006400:	bf00      	nop
+ 8006402:	370c      	adds	r7, #12
+ 8006404:	46bd      	mov	sp, r7
+ 8006406:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 800640a:	4770      	bx	lr
+
+0800640c <HAL_FDCAN_HighPriorityMessageCallback>:
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval None
+  */
+__weak void HAL_FDCAN_HighPriorityMessageCallback(FDCAN_HandleTypeDef *hfdcan)
+{
+ 800640c:	b480      	push	{r7}
+ 800640e:	b083      	sub	sp, #12
+ 8006410:	af00      	add	r7, sp, #0
+ 8006412:	6078      	str	r0, [r7, #4]
+  UNUSED(hfdcan);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_HighPriorityMessageCallback could be implemented in the user file
+   */
+}
+ 8006414:	bf00      	nop
+ 8006416:	370c      	adds	r7, #12
+ 8006418:	46bd      	mov	sp, r7
+ 800641a:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 800641e:	4770      	bx	lr
+
+08006420 <HAL_FDCAN_ErrorCallback>:
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval None
+  */
+__weak void HAL_FDCAN_ErrorCallback(FDCAN_HandleTypeDef *hfdcan)
+{
+ 8006420:	b480      	push	{r7}
+ 8006422:	b083      	sub	sp, #12
+ 8006424:	af00      	add	r7, sp, #0
+ 8006426:	6078      	str	r0, [r7, #4]
+  UNUSED(hfdcan);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_ErrorCallback could be implemented in the user file
+   */
+}
+ 8006428:	bf00      	nop
+ 800642a:	370c      	adds	r7, #12
+ 800642c:	46bd      	mov	sp, r7
+ 800642e:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8006432:	4770      	bx	lr
+
+08006434 <HAL_FDCAN_ErrorStatusCallback>:
+  * @param  ErrorStatusITs indicates which Error Status interrupts are signaled.
+  *         This parameter can be any combination of @arg FDCAN_Error_Status_Interrupts.
+  * @retval None
+  */
+__weak void HAL_FDCAN_ErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t ErrorStatusITs)
+{
+ 8006434:	b480      	push	{r7}
+ 8006436:	b083      	sub	sp, #12
+ 8006438:	af00      	add	r7, sp, #0
+ 800643a:	6078      	str	r0, [r7, #4]
+ 800643c:	6039      	str	r1, [r7, #0]
+  UNUSED(ErrorStatusITs);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_ErrorStatusCallback could be implemented in the user file
+   */
+}
+ 800643e:	bf00      	nop
+ 8006440:	370c      	adds	r7, #12
+ 8006442:	46bd      	mov	sp, r7
+ 8006444:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8006448:	4770      	bx	lr
+
+0800644a <HAL_FDCAN_TT_ScheduleSyncCallback>:
+  * @param  TTSchedSyncITs indicates which TT Schedule Synchronization interrupts are signaled.
+  *         This parameter can be any combination of @arg FDCAN_TTScheduleSynchronization_Interrupts.
+  * @retval None
+  */
+__weak void HAL_FDCAN_TT_ScheduleSyncCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TTSchedSyncITs)
+{
+ 800644a:	b480      	push	{r7}
+ 800644c:	b083      	sub	sp, #12
+ 800644e:	af00      	add	r7, sp, #0
+ 8006450:	6078      	str	r0, [r7, #4]
+ 8006452:	6039      	str	r1, [r7, #0]
+  UNUSED(TTSchedSyncITs);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_TT_ScheduleSyncCallback could be implemented in the user file
+   */
+}
+ 8006454:	bf00      	nop
+ 8006456:	370c      	adds	r7, #12
+ 8006458:	46bd      	mov	sp, r7
+ 800645a:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 800645e:	4770      	bx	lr
+
+08006460 <HAL_FDCAN_TT_TimeMarkCallback>:
+  * @param  TTTimeMarkITs indicates which TT Schedule Synchronization interrupts are signaled.
+  *         This parameter can be any combination of @arg FDCAN_TTTimeMark_Interrupts.
+  * @retval None
+  */
+__weak void HAL_FDCAN_TT_TimeMarkCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TTTimeMarkITs)
+{
+ 8006460:	b480      	push	{r7}
+ 8006462:	b083      	sub	sp, #12
+ 8006464:	af00      	add	r7, sp, #0
+ 8006466:	6078      	str	r0, [r7, #4]
+ 8006468:	6039      	str	r1, [r7, #0]
+  UNUSED(TTTimeMarkITs);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_TT_TimeMarkCallback could be implemented in the user file
+   */
+}
+ 800646a:	bf00      	nop
+ 800646c:	370c      	adds	r7, #12
+ 800646e:	46bd      	mov	sp, r7
+ 8006470:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8006474:	4770      	bx	lr
+
+08006476 <HAL_FDCAN_TT_StopWatchCallback>:
+  * @param  SWCycleCount Cycle count value captured together with SWTime.
+  *         This parameter is a number between 0 and 0x3F.
+  * @retval None
+  */
+__weak void HAL_FDCAN_TT_StopWatchCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t SWTime, uint32_t SWCycleCount)
+{
+ 8006476:	b480      	push	{r7}
+ 8006478:	b085      	sub	sp, #20
+ 800647a:	af00      	add	r7, sp, #0
+ 800647c:	60f8      	str	r0, [r7, #12]
+ 800647e:	60b9      	str	r1, [r7, #8]
+ 8006480:	607a      	str	r2, [r7, #4]
+  UNUSED(SWCycleCount);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_TT_StopWatchCallback could be implemented in the user file
+   */
+}
+ 8006482:	bf00      	nop
+ 8006484:	3714      	adds	r7, #20
+ 8006486:	46bd      	mov	sp, r7
+ 8006488:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 800648c:	4770      	bx	lr
+
+0800648e <HAL_FDCAN_TT_GlobalTimeCallback>:
+  * @param  TTGlobTimeITs indicates which TT Global Time interrupts are signaled.
+  *         This parameter can be any combination of @arg FDCAN_TTGlobalTime_Interrupts.
+  * @retval None
+  */
+__weak void HAL_FDCAN_TT_GlobalTimeCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TTGlobTimeITs)
+{
+ 800648e:	b480      	push	{r7}
+ 8006490:	b083      	sub	sp, #12
+ 8006492:	af00      	add	r7, sp, #0
+ 8006494:	6078      	str	r0, [r7, #4]
+ 8006496:	6039      	str	r1, [r7, #0]
+  UNUSED(TTGlobTimeITs);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_TT_GlobalTimeCallback could be implemented in the user file
+   */
+}
+ 8006498:	bf00      	nop
+ 800649a:	370c      	adds	r7, #12
+ 800649c:	46bd      	mov	sp, r7
+ 800649e:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 80064a2:	4770      	bx	lr
+
+080064a4 <FDCAN_CalcultateRamBlockAddresses>:
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+ */
+static HAL_StatusTypeDef FDCAN_CalcultateRamBlockAddresses(FDCAN_HandleTypeDef *hfdcan)
+{
+ 80064a4:	b480      	push	{r7}
+ 80064a6:	b085      	sub	sp, #20
+ 80064a8:	af00      	add	r7, sp, #0
+ 80064aa:	6078      	str	r0, [r7, #4]
+  uint32_t RAMcounter;
+  uint32_t StartAddress;
+
+  StartAddress = hfdcan->Init.MessageRAMOffset;
+ 80064ac:	687b      	ldr	r3, [r7, #4]
+ 80064ae:	6b5b      	ldr	r3, [r3, #52]	; 0x34
+ 80064b0:	60bb      	str	r3, [r7, #8]
+
+  /* Standard filter list start address */
+  MODIFY_REG(hfdcan->Instance->SIDFC, FDCAN_SIDFC_FLSSA, (StartAddress << FDCAN_SIDFC_FLSSA_Pos));
+ 80064b2:	687b      	ldr	r3, [r7, #4]
+ 80064b4:	681b      	ldr	r3, [r3, #0]
+ 80064b6:	f8d3 2084 	ldr.w	r2, [r3, #132]	; 0x84
+ 80064ba:	4ba7      	ldr	r3, [pc, #668]	; (8006758 <FDCAN_CalcultateRamBlockAddresses+0x2b4>)
+ 80064bc:	4013      	ands	r3, r2
+ 80064be:	68ba      	ldr	r2, [r7, #8]
+ 80064c0:	0091      	lsls	r1, r2, #2
+ 80064c2:	687a      	ldr	r2, [r7, #4]
+ 80064c4:	6812      	ldr	r2, [r2, #0]
+ 80064c6:	430b      	orrs	r3, r1
+ 80064c8:	f8c2 3084 	str.w	r3, [r2, #132]	; 0x84
+
+  /* Standard filter elements number */
+  MODIFY_REG(hfdcan->Instance->SIDFC, FDCAN_SIDFC_LSS, (hfdcan->Init.StdFiltersNbr << FDCAN_SIDFC_LSS_Pos));
+ 80064cc:	687b      	ldr	r3, [r7, #4]
+ 80064ce:	681b      	ldr	r3, [r3, #0]
+ 80064d0:	f8d3 3084 	ldr.w	r3, [r3, #132]	; 0x84
+ 80064d4:	f423 017f 	bic.w	r1, r3, #16711680	; 0xff0000
+ 80064d8:	687b      	ldr	r3, [r7, #4]
+ 80064da:	6b9b      	ldr	r3, [r3, #56]	; 0x38
+ 80064dc:	041a      	lsls	r2, r3, #16
+ 80064de:	687b      	ldr	r3, [r7, #4]
+ 80064e0:	681b      	ldr	r3, [r3, #0]
+ 80064e2:	430a      	orrs	r2, r1
+ 80064e4:	f8c3 2084 	str.w	r2, [r3, #132]	; 0x84
+
+  /* Extended filter list start address */
+  StartAddress += hfdcan->Init.StdFiltersNbr;
+ 80064e8:	687b      	ldr	r3, [r7, #4]
+ 80064ea:	6b9b      	ldr	r3, [r3, #56]	; 0x38
+ 80064ec:	68ba      	ldr	r2, [r7, #8]
+ 80064ee:	4413      	add	r3, r2
+ 80064f0:	60bb      	str	r3, [r7, #8]
+  MODIFY_REG(hfdcan->Instance->XIDFC, FDCAN_XIDFC_FLESA, (StartAddress << FDCAN_XIDFC_FLESA_Pos));
+ 80064f2:	687b      	ldr	r3, [r7, #4]
+ 80064f4:	681b      	ldr	r3, [r3, #0]
+ 80064f6:	f8d3 2088 	ldr.w	r2, [r3, #136]	; 0x88
+ 80064fa:	4b97      	ldr	r3, [pc, #604]	; (8006758 <FDCAN_CalcultateRamBlockAddresses+0x2b4>)
+ 80064fc:	4013      	ands	r3, r2
+ 80064fe:	68ba      	ldr	r2, [r7, #8]
+ 8006500:	0091      	lsls	r1, r2, #2
+ 8006502:	687a      	ldr	r2, [r7, #4]
+ 8006504:	6812      	ldr	r2, [r2, #0]
+ 8006506:	430b      	orrs	r3, r1
+ 8006508:	f8c2 3088 	str.w	r3, [r2, #136]	; 0x88
+
+  /* Extended filter elements number */
+  MODIFY_REG(hfdcan->Instance->XIDFC, FDCAN_XIDFC_LSE, (hfdcan->Init.ExtFiltersNbr << FDCAN_XIDFC_LSE_Pos));
+ 800650c:	687b      	ldr	r3, [r7, #4]
+ 800650e:	681b      	ldr	r3, [r3, #0]
+ 8006510:	f8d3 3088 	ldr.w	r3, [r3, #136]	; 0x88
+ 8006514:	f423 01fe 	bic.w	r1, r3, #8323072	; 0x7f0000
+ 8006518:	687b      	ldr	r3, [r7, #4]
+ 800651a:	6bdb      	ldr	r3, [r3, #60]	; 0x3c
+ 800651c:	041a      	lsls	r2, r3, #16
+ 800651e:	687b      	ldr	r3, [r7, #4]
+ 8006520:	681b      	ldr	r3, [r3, #0]
+ 8006522:	430a      	orrs	r2, r1
+ 8006524:	f8c3 2088 	str.w	r2, [r3, #136]	; 0x88
+
+  /* Rx FIFO 0 start address */
+  StartAddress += (hfdcan->Init.ExtFiltersNbr * 2U);
+ 8006528:	687b      	ldr	r3, [r7, #4]
+ 800652a:	6bdb      	ldr	r3, [r3, #60]	; 0x3c
+ 800652c:	005b      	lsls	r3, r3, #1
+ 800652e:	68ba      	ldr	r2, [r7, #8]
+ 8006530:	4413      	add	r3, r2
+ 8006532:	60bb      	str	r3, [r7, #8]
+  MODIFY_REG(hfdcan->Instance->RXF0C, FDCAN_RXF0C_F0SA, (StartAddress << FDCAN_RXF0C_F0SA_Pos));
+ 8006534:	687b      	ldr	r3, [r7, #4]
+ 8006536:	681b      	ldr	r3, [r3, #0]
+ 8006538:	f8d3 20a0 	ldr.w	r2, [r3, #160]	; 0xa0
+ 800653c:	4b86      	ldr	r3, [pc, #536]	; (8006758 <FDCAN_CalcultateRamBlockAddresses+0x2b4>)
+ 800653e:	4013      	ands	r3, r2
+ 8006540:	68ba      	ldr	r2, [r7, #8]
+ 8006542:	0091      	lsls	r1, r2, #2
+ 8006544:	687a      	ldr	r2, [r7, #4]
+ 8006546:	6812      	ldr	r2, [r2, #0]
+ 8006548:	430b      	orrs	r3, r1
+ 800654a:	f8c2 30a0 	str.w	r3, [r2, #160]	; 0xa0
+
+  /* Rx FIFO 0 elements number */
+  MODIFY_REG(hfdcan->Instance->RXF0C, FDCAN_RXF0C_F0S, (hfdcan->Init.RxFifo0ElmtsNbr << FDCAN_RXF0C_F0S_Pos));
+ 800654e:	687b      	ldr	r3, [r7, #4]
+ 8006550:	681b      	ldr	r3, [r3, #0]
+ 8006552:	f8d3 30a0 	ldr.w	r3, [r3, #160]	; 0xa0
+ 8006556:	f423 01fe 	bic.w	r1, r3, #8323072	; 0x7f0000
+ 800655a:	687b      	ldr	r3, [r7, #4]
+ 800655c:	6c1b      	ldr	r3, [r3, #64]	; 0x40
+ 800655e:	041a      	lsls	r2, r3, #16
+ 8006560:	687b      	ldr	r3, [r7, #4]
+ 8006562:	681b      	ldr	r3, [r3, #0]
+ 8006564:	430a      	orrs	r2, r1
+ 8006566:	f8c3 20a0 	str.w	r2, [r3, #160]	; 0xa0
+
+  /* Rx FIFO 1 start address */
+  StartAddress += (hfdcan->Init.RxFifo0ElmtsNbr * hfdcan->Init.RxFifo0ElmtSize);
+ 800656a:	687b      	ldr	r3, [r7, #4]
+ 800656c:	6c1b      	ldr	r3, [r3, #64]	; 0x40
+ 800656e:	687a      	ldr	r2, [r7, #4]
+ 8006570:	6c52      	ldr	r2, [r2, #68]	; 0x44
+ 8006572:	fb02 f303 	mul.w	r3, r2, r3
+ 8006576:	68ba      	ldr	r2, [r7, #8]
+ 8006578:	4413      	add	r3, r2
+ 800657a:	60bb      	str	r3, [r7, #8]
+  MODIFY_REG(hfdcan->Instance->RXF1C, FDCAN_RXF1C_F1SA, (StartAddress << FDCAN_RXF1C_F1SA_Pos));
+ 800657c:	687b      	ldr	r3, [r7, #4]
+ 800657e:	681b      	ldr	r3, [r3, #0]
+ 8006580:	f8d3 20b0 	ldr.w	r2, [r3, #176]	; 0xb0
+ 8006584:	4b74      	ldr	r3, [pc, #464]	; (8006758 <FDCAN_CalcultateRamBlockAddresses+0x2b4>)
+ 8006586:	4013      	ands	r3, r2
+ 8006588:	68ba      	ldr	r2, [r7, #8]
+ 800658a:	0091      	lsls	r1, r2, #2
+ 800658c:	687a      	ldr	r2, [r7, #4]
+ 800658e:	6812      	ldr	r2, [r2, #0]
+ 8006590:	430b      	orrs	r3, r1
+ 8006592:	f8c2 30b0 	str.w	r3, [r2, #176]	; 0xb0
+
+  /* Rx FIFO 1 elements number */
+  MODIFY_REG(hfdcan->Instance->RXF1C, FDCAN_RXF1C_F1S, (hfdcan->Init.RxFifo1ElmtsNbr << FDCAN_RXF1C_F1S_Pos));
+ 8006596:	687b      	ldr	r3, [r7, #4]
+ 8006598:	681b      	ldr	r3, [r3, #0]
+ 800659a:	f8d3 30b0 	ldr.w	r3, [r3, #176]	; 0xb0
+ 800659e:	f423 01fe 	bic.w	r1, r3, #8323072	; 0x7f0000
+ 80065a2:	687b      	ldr	r3, [r7, #4]
+ 80065a4:	6c9b      	ldr	r3, [r3, #72]	; 0x48
+ 80065a6:	041a      	lsls	r2, r3, #16
+ 80065a8:	687b      	ldr	r3, [r7, #4]
+ 80065aa:	681b      	ldr	r3, [r3, #0]
+ 80065ac:	430a      	orrs	r2, r1
+ 80065ae:	f8c3 20b0 	str.w	r2, [r3, #176]	; 0xb0
+
+  /* Rx buffer list start address */
+  StartAddress += (hfdcan->Init.RxFifo1ElmtsNbr * hfdcan->Init.RxFifo1ElmtSize);
+ 80065b2:	687b      	ldr	r3, [r7, #4]
+ 80065b4:	6c9b      	ldr	r3, [r3, #72]	; 0x48
+ 80065b6:	687a      	ldr	r2, [r7, #4]
+ 80065b8:	6cd2      	ldr	r2, [r2, #76]	; 0x4c
+ 80065ba:	fb02 f303 	mul.w	r3, r2, r3
+ 80065be:	68ba      	ldr	r2, [r7, #8]
+ 80065c0:	4413      	add	r3, r2
+ 80065c2:	60bb      	str	r3, [r7, #8]
+  MODIFY_REG(hfdcan->Instance->RXBC, FDCAN_RXBC_RBSA, (StartAddress << FDCAN_RXBC_RBSA_Pos));
+ 80065c4:	687b      	ldr	r3, [r7, #4]
+ 80065c6:	681b      	ldr	r3, [r3, #0]
+ 80065c8:	f8d3 20ac 	ldr.w	r2, [r3, #172]	; 0xac
+ 80065cc:	4b62      	ldr	r3, [pc, #392]	; (8006758 <FDCAN_CalcultateRamBlockAddresses+0x2b4>)
+ 80065ce:	4013      	ands	r3, r2
+ 80065d0:	68ba      	ldr	r2, [r7, #8]
+ 80065d2:	0091      	lsls	r1, r2, #2
+ 80065d4:	687a      	ldr	r2, [r7, #4]
+ 80065d6:	6812      	ldr	r2, [r2, #0]
+ 80065d8:	430b      	orrs	r3, r1
+ 80065da:	f8c2 30ac 	str.w	r3, [r2, #172]	; 0xac
+
+  /* Tx event FIFO start address */
+  StartAddress += (hfdcan->Init.RxBuffersNbr * hfdcan->Init.RxBufferSize);
+ 80065de:	687b      	ldr	r3, [r7, #4]
+ 80065e0:	6d1b      	ldr	r3, [r3, #80]	; 0x50
+ 80065e2:	687a      	ldr	r2, [r7, #4]
+ 80065e4:	6d52      	ldr	r2, [r2, #84]	; 0x54
+ 80065e6:	fb02 f303 	mul.w	r3, r2, r3
+ 80065ea:	68ba      	ldr	r2, [r7, #8]
+ 80065ec:	4413      	add	r3, r2
+ 80065ee:	60bb      	str	r3, [r7, #8]
+  MODIFY_REG(hfdcan->Instance->TXEFC, FDCAN_TXEFC_EFSA, (StartAddress << FDCAN_TXEFC_EFSA_Pos));
+ 80065f0:	687b      	ldr	r3, [r7, #4]
+ 80065f2:	681b      	ldr	r3, [r3, #0]
+ 80065f4:	f8d3 20f0 	ldr.w	r2, [r3, #240]	; 0xf0
+ 80065f8:	4b57      	ldr	r3, [pc, #348]	; (8006758 <FDCAN_CalcultateRamBlockAddresses+0x2b4>)
+ 80065fa:	4013      	ands	r3, r2
+ 80065fc:	68ba      	ldr	r2, [r7, #8]
+ 80065fe:	0091      	lsls	r1, r2, #2
+ 8006600:	687a      	ldr	r2, [r7, #4]
+ 8006602:	6812      	ldr	r2, [r2, #0]
+ 8006604:	430b      	orrs	r3, r1
+ 8006606:	f8c2 30f0 	str.w	r3, [r2, #240]	; 0xf0
+
+  /* Tx event FIFO elements number */
+  MODIFY_REG(hfdcan->Instance->TXEFC, FDCAN_TXEFC_EFS, (hfdcan->Init.TxEventsNbr << FDCAN_TXEFC_EFS_Pos));
+ 800660a:	687b      	ldr	r3, [r7, #4]
+ 800660c:	681b      	ldr	r3, [r3, #0]
+ 800660e:	f8d3 30f0 	ldr.w	r3, [r3, #240]	; 0xf0
+ 8006612:	f423 117c 	bic.w	r1, r3, #4128768	; 0x3f0000
+ 8006616:	687b      	ldr	r3, [r7, #4]
+ 8006618:	6d9b      	ldr	r3, [r3, #88]	; 0x58
+ 800661a:	041a      	lsls	r2, r3, #16
+ 800661c:	687b      	ldr	r3, [r7, #4]
+ 800661e:	681b      	ldr	r3, [r3, #0]
+ 8006620:	430a      	orrs	r2, r1
+ 8006622:	f8c3 20f0 	str.w	r2, [r3, #240]	; 0xf0
+
+  /* Tx buffer list start address */
+  StartAddress += (hfdcan->Init.TxEventsNbr * 2U);
+ 8006626:	687b      	ldr	r3, [r7, #4]
+ 8006628:	6d9b      	ldr	r3, [r3, #88]	; 0x58
+ 800662a:	005b      	lsls	r3, r3, #1
+ 800662c:	68ba      	ldr	r2, [r7, #8]
+ 800662e:	4413      	add	r3, r2
+ 8006630:	60bb      	str	r3, [r7, #8]
+  MODIFY_REG(hfdcan->Instance->TXBC, FDCAN_TXBC_TBSA, (StartAddress << FDCAN_TXBC_TBSA_Pos));
+ 8006632:	687b      	ldr	r3, [r7, #4]
+ 8006634:	681b      	ldr	r3, [r3, #0]
+ 8006636:	f8d3 20c0 	ldr.w	r2, [r3, #192]	; 0xc0
+ 800663a:	4b47      	ldr	r3, [pc, #284]	; (8006758 <FDCAN_CalcultateRamBlockAddresses+0x2b4>)
+ 800663c:	4013      	ands	r3, r2
+ 800663e:	68ba      	ldr	r2, [r7, #8]
+ 8006640:	0091      	lsls	r1, r2, #2
+ 8006642:	687a      	ldr	r2, [r7, #4]
+ 8006644:	6812      	ldr	r2, [r2, #0]
+ 8006646:	430b      	orrs	r3, r1
+ 8006648:	f8c2 30c0 	str.w	r3, [r2, #192]	; 0xc0
+
+  /* Dedicated Tx buffers number */
+  MODIFY_REG(hfdcan->Instance->TXBC, FDCAN_TXBC_NDTB, (hfdcan->Init.TxBuffersNbr << FDCAN_TXBC_NDTB_Pos));
+ 800664c:	687b      	ldr	r3, [r7, #4]
+ 800664e:	681b      	ldr	r3, [r3, #0]
+ 8006650:	f8d3 30c0 	ldr.w	r3, [r3, #192]	; 0xc0
+ 8006654:	f423 117c 	bic.w	r1, r3, #4128768	; 0x3f0000
+ 8006658:	687b      	ldr	r3, [r7, #4]
+ 800665a:	6ddb      	ldr	r3, [r3, #92]	; 0x5c
+ 800665c:	041a      	lsls	r2, r3, #16
+ 800665e:	687b      	ldr	r3, [r7, #4]
+ 8006660:	681b      	ldr	r3, [r3, #0]
+ 8006662:	430a      	orrs	r2, r1
+ 8006664:	f8c3 20c0 	str.w	r2, [r3, #192]	; 0xc0
+
+  /* Tx FIFO/queue elements number */
+  MODIFY_REG(hfdcan->Instance->TXBC, FDCAN_TXBC_TFQS, (hfdcan->Init.TxFifoQueueElmtsNbr << FDCAN_TXBC_TFQS_Pos));
+ 8006668:	687b      	ldr	r3, [r7, #4]
+ 800666a:	681b      	ldr	r3, [r3, #0]
+ 800666c:	f8d3 30c0 	ldr.w	r3, [r3, #192]	; 0xc0
+ 8006670:	f023 517c 	bic.w	r1, r3, #1056964608	; 0x3f000000
+ 8006674:	687b      	ldr	r3, [r7, #4]
+ 8006676:	6e1b      	ldr	r3, [r3, #96]	; 0x60
+ 8006678:	061a      	lsls	r2, r3, #24
+ 800667a:	687b      	ldr	r3, [r7, #4]
+ 800667c:	681b      	ldr	r3, [r3, #0]
+ 800667e:	430a      	orrs	r2, r1
+ 8006680:	f8c3 20c0 	str.w	r2, [r3, #192]	; 0xc0
+
+  hfdcan->msgRam.StandardFilterSA = SRAMCAN_BASE + (hfdcan->Init.MessageRAMOffset * 4U);
+ 8006684:	687b      	ldr	r3, [r7, #4]
+ 8006686:	6b5a      	ldr	r2, [r3, #52]	; 0x34
+ 8006688:	4b34      	ldr	r3, [pc, #208]	; (800675c <FDCAN_CalcultateRamBlockAddresses+0x2b8>)
+ 800668a:	4413      	add	r3, r2
+ 800668c:	009a      	lsls	r2, r3, #2
+ 800668e:	687b      	ldr	r3, [r7, #4]
+ 8006690:	66da      	str	r2, [r3, #108]	; 0x6c
+  hfdcan->msgRam.ExtendedFilterSA = hfdcan->msgRam.StandardFilterSA + (hfdcan->Init.StdFiltersNbr * 4U);
+ 8006692:	687b      	ldr	r3, [r7, #4]
+ 8006694:	6eda      	ldr	r2, [r3, #108]	; 0x6c
+ 8006696:	687b      	ldr	r3, [r7, #4]
+ 8006698:	6b9b      	ldr	r3, [r3, #56]	; 0x38
+ 800669a:	009b      	lsls	r3, r3, #2
+ 800669c:	441a      	add	r2, r3
+ 800669e:	687b      	ldr	r3, [r7, #4]
+ 80066a0:	671a      	str	r2, [r3, #112]	; 0x70
+  hfdcan->msgRam.RxFIFO0SA = hfdcan->msgRam.ExtendedFilterSA + (hfdcan->Init.ExtFiltersNbr * 2U * 4U);
+ 80066a2:	687b      	ldr	r3, [r7, #4]
+ 80066a4:	6f1a      	ldr	r2, [r3, #112]	; 0x70
+ 80066a6:	687b      	ldr	r3, [r7, #4]
+ 80066a8:	6bdb      	ldr	r3, [r3, #60]	; 0x3c
+ 80066aa:	00db      	lsls	r3, r3, #3
+ 80066ac:	441a      	add	r2, r3
+ 80066ae:	687b      	ldr	r3, [r7, #4]
+ 80066b0:	675a      	str	r2, [r3, #116]	; 0x74
+  hfdcan->msgRam.RxFIFO1SA = hfdcan->msgRam.RxFIFO0SA + (hfdcan->Init.RxFifo0ElmtsNbr * hfdcan->Init.RxFifo0ElmtSize * 4U);
+ 80066b2:	687b      	ldr	r3, [r7, #4]
+ 80066b4:	6f5a      	ldr	r2, [r3, #116]	; 0x74
+ 80066b6:	687b      	ldr	r3, [r7, #4]
+ 80066b8:	6c1b      	ldr	r3, [r3, #64]	; 0x40
+ 80066ba:	6879      	ldr	r1, [r7, #4]
+ 80066bc:	6c49      	ldr	r1, [r1, #68]	; 0x44
+ 80066be:	fb01 f303 	mul.w	r3, r1, r3
+ 80066c2:	009b      	lsls	r3, r3, #2
+ 80066c4:	441a      	add	r2, r3
+ 80066c6:	687b      	ldr	r3, [r7, #4]
+ 80066c8:	679a      	str	r2, [r3, #120]	; 0x78
+  hfdcan->msgRam.RxBufferSA = hfdcan->msgRam.RxFIFO1SA + (hfdcan->Init.RxFifo1ElmtsNbr * hfdcan->Init.RxFifo1ElmtSize * 4U);
+ 80066ca:	687b      	ldr	r3, [r7, #4]
+ 80066cc:	6f9a      	ldr	r2, [r3, #120]	; 0x78
+ 80066ce:	687b      	ldr	r3, [r7, #4]
+ 80066d0:	6c9b      	ldr	r3, [r3, #72]	; 0x48
+ 80066d2:	6879      	ldr	r1, [r7, #4]
+ 80066d4:	6cc9      	ldr	r1, [r1, #76]	; 0x4c
+ 80066d6:	fb01 f303 	mul.w	r3, r1, r3
+ 80066da:	009b      	lsls	r3, r3, #2
+ 80066dc:	441a      	add	r2, r3
+ 80066de:	687b      	ldr	r3, [r7, #4]
+ 80066e0:	67da      	str	r2, [r3, #124]	; 0x7c
+  hfdcan->msgRam.TxEventFIFOSA = hfdcan->msgRam.RxBufferSA + (hfdcan->Init.RxBuffersNbr * hfdcan->Init.RxBufferSize * 4U);
+ 80066e2:	687b      	ldr	r3, [r7, #4]
+ 80066e4:	6fda      	ldr	r2, [r3, #124]	; 0x7c
+ 80066e6:	687b      	ldr	r3, [r7, #4]
+ 80066e8:	6d1b      	ldr	r3, [r3, #80]	; 0x50
+ 80066ea:	6879      	ldr	r1, [r7, #4]
+ 80066ec:	6d49      	ldr	r1, [r1, #84]	; 0x54
+ 80066ee:	fb01 f303 	mul.w	r3, r1, r3
+ 80066f2:	009b      	lsls	r3, r3, #2
+ 80066f4:	441a      	add	r2, r3
+ 80066f6:	687b      	ldr	r3, [r7, #4]
+ 80066f8:	f8c3 2080 	str.w	r2, [r3, #128]	; 0x80
+  hfdcan->msgRam.TxBufferSA = hfdcan->msgRam.TxEventFIFOSA + (hfdcan->Init.TxEventsNbr * 2U * 4U);
+ 80066fc:	687b      	ldr	r3, [r7, #4]
+ 80066fe:	f8d3 2080 	ldr.w	r2, [r3, #128]	; 0x80
+ 8006702:	687b      	ldr	r3, [r7, #4]
+ 8006704:	6d9b      	ldr	r3, [r3, #88]	; 0x58
+ 8006706:	00db      	lsls	r3, r3, #3
+ 8006708:	441a      	add	r2, r3
+ 800670a:	687b      	ldr	r3, [r7, #4]
+ 800670c:	f8c3 2084 	str.w	r2, [r3, #132]	; 0x84
+  hfdcan->msgRam.TxFIFOQSA = hfdcan->msgRam.TxBufferSA + (hfdcan->Init.TxBuffersNbr * hfdcan->Init.TxElmtSize * 4U);
+ 8006710:	687b      	ldr	r3, [r7, #4]
+ 8006712:	f8d3 2084 	ldr.w	r2, [r3, #132]	; 0x84
+ 8006716:	687b      	ldr	r3, [r7, #4]
+ 8006718:	6ddb      	ldr	r3, [r3, #92]	; 0x5c
+ 800671a:	6879      	ldr	r1, [r7, #4]
+ 800671c:	6e89      	ldr	r1, [r1, #104]	; 0x68
+ 800671e:	fb01 f303 	mul.w	r3, r1, r3
+ 8006722:	009b      	lsls	r3, r3, #2
+ 8006724:	441a      	add	r2, r3
+ 8006726:	687b      	ldr	r3, [r7, #4]
+ 8006728:	f8c3 2088 	str.w	r2, [r3, #136]	; 0x88
+
+  hfdcan->msgRam.EndAddress = hfdcan->msgRam.TxFIFOQSA + (hfdcan->Init.TxFifoQueueElmtsNbr * hfdcan->Init.TxElmtSize * 4U);
+ 800672c:	687b      	ldr	r3, [r7, #4]
+ 800672e:	f8d3 2088 	ldr.w	r2, [r3, #136]	; 0x88
+ 8006732:	687b      	ldr	r3, [r7, #4]
+ 8006734:	6e1b      	ldr	r3, [r3, #96]	; 0x60
+ 8006736:	6879      	ldr	r1, [r7, #4]
+ 8006738:	6e89      	ldr	r1, [r1, #104]	; 0x68
+ 800673a:	fb01 f303 	mul.w	r3, r1, r3
+ 800673e:	009b      	lsls	r3, r3, #2
+ 8006740:	441a      	add	r2, r3
+ 8006742:	687b      	ldr	r3, [r7, #4]
+ 8006744:	f8c3 2090 	str.w	r2, [r3, #144]	; 0x90
+
+  if (hfdcan->msgRam.EndAddress > FDCAN_MESSAGE_RAM_END_ADDRESS) /* Last address of the Message RAM */
+ 8006748:	687b      	ldr	r3, [r7, #4]
+ 800674a:	f8d3 3090 	ldr.w	r3, [r3, #144]	; 0x90
+ 800674e:	4a04      	ldr	r2, [pc, #16]	; (8006760 <FDCAN_CalcultateRamBlockAddresses+0x2bc>)
+ 8006750:	4293      	cmp	r3, r2
+ 8006752:	d915      	bls.n	8006780 <FDCAN_CalcultateRamBlockAddresses+0x2dc>
+ 8006754:	e006      	b.n	8006764 <FDCAN_CalcultateRamBlockAddresses+0x2c0>
+ 8006756:	bf00      	nop
+ 8006758:	ffff0003 	.word	0xffff0003
+ 800675c:	10002b00 	.word	0x10002b00
+ 8006760:	4000d3fc 	.word	0x4000d3fc
+  {
+    /* Update error code.
+       Message RAM overflow */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM;
+ 8006764:	687b      	ldr	r3, [r7, #4]
+ 8006766:	f8d3 309c 	ldr.w	r3, [r3, #156]	; 0x9c
+ 800676a:	f043 0220 	orr.w	r2, r3, #32
+ 800676e:	687b      	ldr	r3, [r7, #4]
+ 8006770:	f8c3 209c 	str.w	r2, [r3, #156]	; 0x9c
+
+    /* Change FDCAN state */
+    hfdcan->State = HAL_FDCAN_STATE_ERROR;
+ 8006774:	687b      	ldr	r3, [r7, #4]
+ 8006776:	2203      	movs	r2, #3
+ 8006778:	f883 2098 	strb.w	r2, [r3, #152]	; 0x98
+
+    return HAL_ERROR;
+ 800677c:	2301      	movs	r3, #1
+ 800677e:	e010      	b.n	80067a2 <FDCAN_CalcultateRamBlockAddresses+0x2fe>
+  }
+  else
+  {
+    /* Flush the allocated Message RAM area */
+    for (RAMcounter = hfdcan->msgRam.StandardFilterSA; RAMcounter < hfdcan->msgRam.EndAddress; RAMcounter += 4U)
+ 8006780:	687b      	ldr	r3, [r7, #4]
+ 8006782:	6edb      	ldr	r3, [r3, #108]	; 0x6c
+ 8006784:	60fb      	str	r3, [r7, #12]
+ 8006786:	e005      	b.n	8006794 <FDCAN_CalcultateRamBlockAddresses+0x2f0>
+    {
+      *(uint32_t *)(RAMcounter) = 0x00000000;
+ 8006788:	68fb      	ldr	r3, [r7, #12]
+ 800678a:	2200      	movs	r2, #0
+ 800678c:	601a      	str	r2, [r3, #0]
+    for (RAMcounter = hfdcan->msgRam.StandardFilterSA; RAMcounter < hfdcan->msgRam.EndAddress; RAMcounter += 4U)
+ 800678e:	68fb      	ldr	r3, [r7, #12]
+ 8006790:	3304      	adds	r3, #4
+ 8006792:	60fb      	str	r3, [r7, #12]
+ 8006794:	687b      	ldr	r3, [r7, #4]
+ 8006796:	f8d3 3090 	ldr.w	r3, [r3, #144]	; 0x90
+ 800679a:	68fa      	ldr	r2, [r7, #12]
+ 800679c:	429a      	cmp	r2, r3
+ 800679e:	d3f3      	bcc.n	8006788 <FDCAN_CalcultateRamBlockAddresses+0x2e4>
+    }
+  }
+
+  /* Return function status */
+  return HAL_OK;
+ 80067a0:	2300      	movs	r3, #0
+}
+ 80067a2:	4618      	mov	r0, r3
+ 80067a4:	3714      	adds	r7, #20
+ 80067a6:	46bd      	mov	sp, r7
+ 80067a8:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 80067ac:	4770      	bx	lr
+ 80067ae:	bf00      	nop
+
+080067b0 <HAL_GPIO_Init>:
+  * @param  GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains
+  *         the configuration information for the specified GPIO peripheral.
+  * @retval None
+  */
+void HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init)
+{
+ 80067b0:	b480      	push	{r7}
+ 80067b2:	b089      	sub	sp, #36	; 0x24
+ 80067b4:	af00      	add	r7, sp, #0
+ 80067b6:	6078      	str	r0, [r7, #4]
+ 80067b8:	6039      	str	r1, [r7, #0]
+  uint32_t position = 0x00U;
+ 80067ba:	2300      	movs	r3, #0
+ 80067bc:	61fb      	str	r3, [r7, #28]
+  EXTI_Core_TypeDef *EXTI_CurrentCPU;
+
+#if defined(DUAL_CORE) && defined(CORE_CM4)
+  EXTI_CurrentCPU = EXTI_D2; /* EXTI for CM4 CPU */
+#else
+  EXTI_CurrentCPU = EXTI_D1; /* EXTI for CM7 CPU */
+ 80067be:	4b86      	ldr	r3, [pc, #536]	; (80069d8 <HAL_GPIO_Init+0x228>)
+ 80067c0:	617b      	str	r3, [r7, #20]
+  assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
+  assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
+  assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
+
+  /* Configure the port pins */
+  while (((GPIO_Init->Pin) >> position) != 0x00U)
+ 80067c2:	e18c      	b.n	8006ade <HAL_GPIO_Init+0x32e>
+  {
+    /* Get current io position */
+    iocurrent = (GPIO_Init->Pin) & (1UL << position);
+ 80067c4:	683b      	ldr	r3, [r7, #0]
+ 80067c6:	681a      	ldr	r2, [r3, #0]
+ 80067c8:	2101      	movs	r1, #1
+ 80067ca:	69fb      	ldr	r3, [r7, #28]
+ 80067cc:	fa01 f303 	lsl.w	r3, r1, r3
+ 80067d0:	4013      	ands	r3, r2
+ 80067d2:	613b      	str	r3, [r7, #16]
+
+    if (iocurrent != 0x00U)
+ 80067d4:	693b      	ldr	r3, [r7, #16]
+ 80067d6:	2b00      	cmp	r3, #0
+ 80067d8:	f000 817e 	beq.w	8006ad8 <HAL_GPIO_Init+0x328>
+    {
+      /*--------------------- GPIO Mode Configuration ------------------------*/
+      /* In case of Output or Alternate function mode selection */
+      if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF))
+ 80067dc:	683b      	ldr	r3, [r7, #0]
+ 80067de:	685b      	ldr	r3, [r3, #4]
+ 80067e0:	f003 0303 	and.w	r3, r3, #3
+ 80067e4:	2b01      	cmp	r3, #1
+ 80067e6:	d005      	beq.n	80067f4 <HAL_GPIO_Init+0x44>
+ 80067e8:	683b      	ldr	r3, [r7, #0]
+ 80067ea:	685b      	ldr	r3, [r3, #4]
+ 80067ec:	f003 0303 	and.w	r3, r3, #3
+ 80067f0:	2b02      	cmp	r3, #2
+ 80067f2:	d130      	bne.n	8006856 <HAL_GPIO_Init+0xa6>
+      {
+        /* Check the Speed parameter */
+        assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
+
+        /* Configure the IO Speed */
+        temp = GPIOx->OSPEEDR;
+ 80067f4:	687b      	ldr	r3, [r7, #4]
+ 80067f6:	689b      	ldr	r3, [r3, #8]
+ 80067f8:	61bb      	str	r3, [r7, #24]
+        temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U));
+ 80067fa:	69fb      	ldr	r3, [r7, #28]
+ 80067fc:	005b      	lsls	r3, r3, #1
+ 80067fe:	2203      	movs	r2, #3
+ 8006800:	fa02 f303 	lsl.w	r3, r2, r3
+ 8006804:	43db      	mvns	r3, r3
+ 8006806:	69ba      	ldr	r2, [r7, #24]
+ 8006808:	4013      	ands	r3, r2
+ 800680a:	61bb      	str	r3, [r7, #24]
+        temp |= (GPIO_Init->Speed << (position * 2U));
+ 800680c:	683b      	ldr	r3, [r7, #0]
+ 800680e:	68da      	ldr	r2, [r3, #12]
+ 8006810:	69fb      	ldr	r3, [r7, #28]
+ 8006812:	005b      	lsls	r3, r3, #1
+ 8006814:	fa02 f303 	lsl.w	r3, r2, r3
+ 8006818:	69ba      	ldr	r2, [r7, #24]
+ 800681a:	4313      	orrs	r3, r2
+ 800681c:	61bb      	str	r3, [r7, #24]
+        GPIOx->OSPEEDR = temp;
+ 800681e:	687b      	ldr	r3, [r7, #4]
+ 8006820:	69ba      	ldr	r2, [r7, #24]
+ 8006822:	609a      	str	r2, [r3, #8]
+
+        /* Configure the IO Output Type */
+        temp = GPIOx->OTYPER;
+ 8006824:	687b      	ldr	r3, [r7, #4]
+ 8006826:	685b      	ldr	r3, [r3, #4]
+ 8006828:	61bb      	str	r3, [r7, #24]
+        temp &= ~(GPIO_OTYPER_OT0 << position) ;
+ 800682a:	2201      	movs	r2, #1
+ 800682c:	69fb      	ldr	r3, [r7, #28]
+ 800682e:	fa02 f303 	lsl.w	r3, r2, r3
+ 8006832:	43db      	mvns	r3, r3
+ 8006834:	69ba      	ldr	r2, [r7, #24]
+ 8006836:	4013      	ands	r3, r2
+ 8006838:	61bb      	str	r3, [r7, #24]
+        temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
+ 800683a:	683b      	ldr	r3, [r7, #0]
+ 800683c:	685b      	ldr	r3, [r3, #4]
+ 800683e:	091b      	lsrs	r3, r3, #4
+ 8006840:	f003 0201 	and.w	r2, r3, #1
+ 8006844:	69fb      	ldr	r3, [r7, #28]
+ 8006846:	fa02 f303 	lsl.w	r3, r2, r3
+ 800684a:	69ba      	ldr	r2, [r7, #24]
+ 800684c:	4313      	orrs	r3, r2
+ 800684e:	61bb      	str	r3, [r7, #24]
+        GPIOx->OTYPER = temp;
+ 8006850:	687b      	ldr	r3, [r7, #4]
+ 8006852:	69ba      	ldr	r2, [r7, #24]
+ 8006854:	605a      	str	r2, [r3, #4]
+      }
+
+      if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG)
+ 8006856:	683b      	ldr	r3, [r7, #0]
+ 8006858:	685b      	ldr	r3, [r3, #4]
+ 800685a:	f003 0303 	and.w	r3, r3, #3
+ 800685e:	2b03      	cmp	r3, #3
+ 8006860:	d017      	beq.n	8006892 <HAL_GPIO_Init+0xe2>
+      {
+       /* Check the Pull parameter */
+       assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
+
+      /* Activate the Pull-up or Pull down resistor for the current IO */
+      temp = GPIOx->PUPDR;
+ 8006862:	687b      	ldr	r3, [r7, #4]
+ 8006864:	68db      	ldr	r3, [r3, #12]
+ 8006866:	61bb      	str	r3, [r7, #24]
+      temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U));
+ 8006868:	69fb      	ldr	r3, [r7, #28]
+ 800686a:	005b      	lsls	r3, r3, #1
+ 800686c:	2203      	movs	r2, #3
+ 800686e:	fa02 f303 	lsl.w	r3, r2, r3
+ 8006872:	43db      	mvns	r3, r3
+ 8006874:	69ba      	ldr	r2, [r7, #24]
+ 8006876:	4013      	ands	r3, r2
+ 8006878:	61bb      	str	r3, [r7, #24]
+      temp |= ((GPIO_Init->Pull) << (position * 2U));
+ 800687a:	683b      	ldr	r3, [r7, #0]
+ 800687c:	689a      	ldr	r2, [r3, #8]
+ 800687e:	69fb      	ldr	r3, [r7, #28]
+ 8006880:	005b      	lsls	r3, r3, #1
+ 8006882:	fa02 f303 	lsl.w	r3, r2, r3
+ 8006886:	69ba      	ldr	r2, [r7, #24]
+ 8006888:	4313      	orrs	r3, r2
+ 800688a:	61bb      	str	r3, [r7, #24]
+      GPIOx->PUPDR = temp;
+ 800688c:	687b      	ldr	r3, [r7, #4]
+ 800688e:	69ba      	ldr	r2, [r7, #24]
+ 8006890:	60da      	str	r2, [r3, #12]
+      }
+
+      /* In case of Alternate function mode selection */
+      if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
+ 8006892:	683b      	ldr	r3, [r7, #0]
+ 8006894:	685b      	ldr	r3, [r3, #4]
+ 8006896:	f003 0303 	and.w	r3, r3, #3
+ 800689a:	2b02      	cmp	r3, #2
+ 800689c:	d123      	bne.n	80068e6 <HAL_GPIO_Init+0x136>
+        /* Check the Alternate function parameters */
+        assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
+        assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
+
+        /* Configure Alternate function mapped with the current IO */
+        temp = GPIOx->AFR[position >> 3U];
+ 800689e:	69fb      	ldr	r3, [r7, #28]
+ 80068a0:	08da      	lsrs	r2, r3, #3
+ 80068a2:	687b      	ldr	r3, [r7, #4]
+ 80068a4:	3208      	adds	r2, #8
+ 80068a6:	f853 3022 	ldr.w	r3, [r3, r2, lsl #2]
+ 80068aa:	61bb      	str	r3, [r7, #24]
+        temp &= ~(0xFU << ((position & 0x07U) * 4U));
+ 80068ac:	69fb      	ldr	r3, [r7, #28]
+ 80068ae:	f003 0307 	and.w	r3, r3, #7
+ 80068b2:	009b      	lsls	r3, r3, #2
+ 80068b4:	220f      	movs	r2, #15
+ 80068b6:	fa02 f303 	lsl.w	r3, r2, r3
+ 80068ba:	43db      	mvns	r3, r3
+ 80068bc:	69ba      	ldr	r2, [r7, #24]
+ 80068be:	4013      	ands	r3, r2
+ 80068c0:	61bb      	str	r3, [r7, #24]
+        temp |= ((GPIO_Init->Alternate) << ((position & 0x07U) * 4U));
+ 80068c2:	683b      	ldr	r3, [r7, #0]
+ 80068c4:	691a      	ldr	r2, [r3, #16]
+ 80068c6:	69fb      	ldr	r3, [r7, #28]
+ 80068c8:	f003 0307 	and.w	r3, r3, #7
+ 80068cc:	009b      	lsls	r3, r3, #2
+ 80068ce:	fa02 f303 	lsl.w	r3, r2, r3
+ 80068d2:	69ba      	ldr	r2, [r7, #24]
+ 80068d4:	4313      	orrs	r3, r2
+ 80068d6:	61bb      	str	r3, [r7, #24]
+        GPIOx->AFR[position >> 3U] = temp;
+ 80068d8:	69fb      	ldr	r3, [r7, #28]
+ 80068da:	08da      	lsrs	r2, r3, #3
+ 80068dc:	687b      	ldr	r3, [r7, #4]
+ 80068de:	3208      	adds	r2, #8
+ 80068e0:	69b9      	ldr	r1, [r7, #24]
+ 80068e2:	f843 1022 	str.w	r1, [r3, r2, lsl #2]
+      }
+
+      /* Configure IO Direction mode (Input, Output, Alternate or Analog) */
+      temp = GPIOx->MODER;
+ 80068e6:	687b      	ldr	r3, [r7, #4]
+ 80068e8:	681b      	ldr	r3, [r3, #0]
+ 80068ea:	61bb      	str	r3, [r7, #24]
+      temp &= ~(GPIO_MODER_MODE0 << (position * 2U));
+ 80068ec:	69fb      	ldr	r3, [r7, #28]
+ 80068ee:	005b      	lsls	r3, r3, #1
+ 80068f0:	2203      	movs	r2, #3
+ 80068f2:	fa02 f303 	lsl.w	r3, r2, r3
+ 80068f6:	43db      	mvns	r3, r3
+ 80068f8:	69ba      	ldr	r2, [r7, #24]
+ 80068fa:	4013      	ands	r3, r2
+ 80068fc:	61bb      	str	r3, [r7, #24]
+      temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U));
+ 80068fe:	683b      	ldr	r3, [r7, #0]
+ 8006900:	685b      	ldr	r3, [r3, #4]
+ 8006902:	f003 0203 	and.w	r2, r3, #3
+ 8006906:	69fb      	ldr	r3, [r7, #28]
+ 8006908:	005b      	lsls	r3, r3, #1
+ 800690a:	fa02 f303 	lsl.w	r3, r2, r3
+ 800690e:	69ba      	ldr	r2, [r7, #24]
+ 8006910:	4313      	orrs	r3, r2
+ 8006912:	61bb      	str	r3, [r7, #24]
+      GPIOx->MODER = temp;
+ 8006914:	687b      	ldr	r3, [r7, #4]
+ 8006916:	69ba      	ldr	r2, [r7, #24]
+ 8006918:	601a      	str	r2, [r3, #0]
+
+      /*--------------------- EXTI Mode Configuration ------------------------*/
+      /* Configure the External Interrupt or event for the current IO */
+      if ((GPIO_Init->Mode & EXTI_MODE) != 0x00U)
+ 800691a:	683b      	ldr	r3, [r7, #0]
+ 800691c:	685b      	ldr	r3, [r3, #4]
+ 800691e:	f403 3340 	and.w	r3, r3, #196608	; 0x30000
+ 8006922:	2b00      	cmp	r3, #0
+ 8006924:	f000 80d8 	beq.w	8006ad8 <HAL_GPIO_Init+0x328>
+      {
+        /* Enable SYSCFG Clock */
+        __HAL_RCC_SYSCFG_CLK_ENABLE();
+ 8006928:	4b2c      	ldr	r3, [pc, #176]	; (80069dc <HAL_GPIO_Init+0x22c>)
+ 800692a:	f8d3 30f4 	ldr.w	r3, [r3, #244]	; 0xf4
+ 800692e:	4a2b      	ldr	r2, [pc, #172]	; (80069dc <HAL_GPIO_Init+0x22c>)
+ 8006930:	f043 0302 	orr.w	r3, r3, #2
+ 8006934:	f8c2 30f4 	str.w	r3, [r2, #244]	; 0xf4
+ 8006938:	4b28      	ldr	r3, [pc, #160]	; (80069dc <HAL_GPIO_Init+0x22c>)
+ 800693a:	f8d3 30f4 	ldr.w	r3, [r3, #244]	; 0xf4
+ 800693e:	f003 0302 	and.w	r3, r3, #2
+ 8006942:	60fb      	str	r3, [r7, #12]
+ 8006944:	68fb      	ldr	r3, [r7, #12]
+
+        temp = SYSCFG->EXTICR[position >> 2U];
+ 8006946:	4a26      	ldr	r2, [pc, #152]	; (80069e0 <HAL_GPIO_Init+0x230>)
+ 8006948:	69fb      	ldr	r3, [r7, #28]
+ 800694a:	089b      	lsrs	r3, r3, #2
+ 800694c:	3302      	adds	r3, #2
+ 800694e:	f852 3023 	ldr.w	r3, [r2, r3, lsl #2]
+ 8006952:	61bb      	str	r3, [r7, #24]
+        temp &= ~(0x0FUL << (4U * (position & 0x03U)));
+ 8006954:	69fb      	ldr	r3, [r7, #28]
+ 8006956:	f003 0303 	and.w	r3, r3, #3
+ 800695a:	009b      	lsls	r3, r3, #2
+ 800695c:	220f      	movs	r2, #15
+ 800695e:	fa02 f303 	lsl.w	r3, r2, r3
+ 8006962:	43db      	mvns	r3, r3
+ 8006964:	69ba      	ldr	r2, [r7, #24]
+ 8006966:	4013      	ands	r3, r2
+ 8006968:	61bb      	str	r3, [r7, #24]
+        temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U)));
+ 800696a:	687b      	ldr	r3, [r7, #4]
+ 800696c:	4a1d      	ldr	r2, [pc, #116]	; (80069e4 <HAL_GPIO_Init+0x234>)
+ 800696e:	4293      	cmp	r3, r2
+ 8006970:	d04a      	beq.n	8006a08 <HAL_GPIO_Init+0x258>
+ 8006972:	687b      	ldr	r3, [r7, #4]
+ 8006974:	4a1c      	ldr	r2, [pc, #112]	; (80069e8 <HAL_GPIO_Init+0x238>)
+ 8006976:	4293      	cmp	r3, r2
+ 8006978:	d02b      	beq.n	80069d2 <HAL_GPIO_Init+0x222>
+ 800697a:	687b      	ldr	r3, [r7, #4]
+ 800697c:	4a1b      	ldr	r2, [pc, #108]	; (80069ec <HAL_GPIO_Init+0x23c>)
+ 800697e:	4293      	cmp	r3, r2
+ 8006980:	d025      	beq.n	80069ce <HAL_GPIO_Init+0x21e>
+ 8006982:	687b      	ldr	r3, [r7, #4]
+ 8006984:	4a1a      	ldr	r2, [pc, #104]	; (80069f0 <HAL_GPIO_Init+0x240>)
+ 8006986:	4293      	cmp	r3, r2
+ 8006988:	d01f      	beq.n	80069ca <HAL_GPIO_Init+0x21a>
+ 800698a:	687b      	ldr	r3, [r7, #4]
+ 800698c:	4a19      	ldr	r2, [pc, #100]	; (80069f4 <HAL_GPIO_Init+0x244>)
+ 800698e:	4293      	cmp	r3, r2
+ 8006990:	d019      	beq.n	80069c6 <HAL_GPIO_Init+0x216>
+ 8006992:	687b      	ldr	r3, [r7, #4]
+ 8006994:	4a18      	ldr	r2, [pc, #96]	; (80069f8 <HAL_GPIO_Init+0x248>)
+ 8006996:	4293      	cmp	r3, r2
+ 8006998:	d013      	beq.n	80069c2 <HAL_GPIO_Init+0x212>
+ 800699a:	687b      	ldr	r3, [r7, #4]
+ 800699c:	4a17      	ldr	r2, [pc, #92]	; (80069fc <HAL_GPIO_Init+0x24c>)
+ 800699e:	4293      	cmp	r3, r2
+ 80069a0:	d00d      	beq.n	80069be <HAL_GPIO_Init+0x20e>
+ 80069a2:	687b      	ldr	r3, [r7, #4]
+ 80069a4:	4a16      	ldr	r2, [pc, #88]	; (8006a00 <HAL_GPIO_Init+0x250>)
+ 80069a6:	4293      	cmp	r3, r2
+ 80069a8:	d007      	beq.n	80069ba <HAL_GPIO_Init+0x20a>
+ 80069aa:	687b      	ldr	r3, [r7, #4]
+ 80069ac:	4a15      	ldr	r2, [pc, #84]	; (8006a04 <HAL_GPIO_Init+0x254>)
+ 80069ae:	4293      	cmp	r3, r2
+ 80069b0:	d101      	bne.n	80069b6 <HAL_GPIO_Init+0x206>
+ 80069b2:	2309      	movs	r3, #9
+ 80069b4:	e029      	b.n	8006a0a <HAL_GPIO_Init+0x25a>
+ 80069b6:	230a      	movs	r3, #10
+ 80069b8:	e027      	b.n	8006a0a <HAL_GPIO_Init+0x25a>
+ 80069ba:	2307      	movs	r3, #7
+ 80069bc:	e025      	b.n	8006a0a <HAL_GPIO_Init+0x25a>
+ 80069be:	2306      	movs	r3, #6
+ 80069c0:	e023      	b.n	8006a0a <HAL_GPIO_Init+0x25a>
+ 80069c2:	2305      	movs	r3, #5
+ 80069c4:	e021      	b.n	8006a0a <HAL_GPIO_Init+0x25a>
+ 80069c6:	2304      	movs	r3, #4
+ 80069c8:	e01f      	b.n	8006a0a <HAL_GPIO_Init+0x25a>
+ 80069ca:	2303      	movs	r3, #3
+ 80069cc:	e01d      	b.n	8006a0a <HAL_GPIO_Init+0x25a>
+ 80069ce:	2302      	movs	r3, #2
+ 80069d0:	e01b      	b.n	8006a0a <HAL_GPIO_Init+0x25a>
+ 80069d2:	2301      	movs	r3, #1
+ 80069d4:	e019      	b.n	8006a0a <HAL_GPIO_Init+0x25a>
+ 80069d6:	bf00      	nop
+ 80069d8:	58000080 	.word	0x58000080
+ 80069dc:	58024400 	.word	0x58024400
+ 80069e0:	58000400 	.word	0x58000400
+ 80069e4:	58020000 	.word	0x58020000
+ 80069e8:	58020400 	.word	0x58020400
+ 80069ec:	58020800 	.word	0x58020800
+ 80069f0:	58020c00 	.word	0x58020c00
+ 80069f4:	58021000 	.word	0x58021000
+ 80069f8:	58021400 	.word	0x58021400
+ 80069fc:	58021800 	.word	0x58021800
+ 8006a00:	58021c00 	.word	0x58021c00
+ 8006a04:	58022400 	.word	0x58022400
+ 8006a08:	2300      	movs	r3, #0
+ 8006a0a:	69fa      	ldr	r2, [r7, #28]
+ 8006a0c:	f002 0203 	and.w	r2, r2, #3
+ 8006a10:	0092      	lsls	r2, r2, #2
+ 8006a12:	4093      	lsls	r3, r2
+ 8006a14:	69ba      	ldr	r2, [r7, #24]
+ 8006a16:	4313      	orrs	r3, r2
+ 8006a18:	61bb      	str	r3, [r7, #24]
+        SYSCFG->EXTICR[position >> 2U] = temp;
+ 8006a1a:	4938      	ldr	r1, [pc, #224]	; (8006afc <HAL_GPIO_Init+0x34c>)
+ 8006a1c:	69fb      	ldr	r3, [r7, #28]
+ 8006a1e:	089b      	lsrs	r3, r3, #2
+ 8006a20:	3302      	adds	r3, #2
+ 8006a22:	69ba      	ldr	r2, [r7, #24]
+ 8006a24:	f841 2023 	str.w	r2, [r1, r3, lsl #2]
+
+        /* Clear Rising Falling edge configuration */
+        temp = EXTI->RTSR1;
+ 8006a28:	f04f 43b0 	mov.w	r3, #1476395008	; 0x58000000
+ 8006a2c:	681b      	ldr	r3, [r3, #0]
+ 8006a2e:	61bb      	str	r3, [r7, #24]
+        temp &= ~(iocurrent);
+ 8006a30:	693b      	ldr	r3, [r7, #16]
+ 8006a32:	43db      	mvns	r3, r3
+ 8006a34:	69ba      	ldr	r2, [r7, #24]
+ 8006a36:	4013      	ands	r3, r2
+ 8006a38:	61bb      	str	r3, [r7, #24]
+        if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U)
+ 8006a3a:	683b      	ldr	r3, [r7, #0]
+ 8006a3c:	685b      	ldr	r3, [r3, #4]
+ 8006a3e:	f403 1380 	and.w	r3, r3, #1048576	; 0x100000
+ 8006a42:	2b00      	cmp	r3, #0
+ 8006a44:	d003      	beq.n	8006a4e <HAL_GPIO_Init+0x29e>
+        {
+          temp |= iocurrent;
+ 8006a46:	69ba      	ldr	r2, [r7, #24]
+ 8006a48:	693b      	ldr	r3, [r7, #16]
+ 8006a4a:	4313      	orrs	r3, r2
+ 8006a4c:	61bb      	str	r3, [r7, #24]
+        }
+        EXTI->RTSR1 = temp;
+ 8006a4e:	f04f 42b0 	mov.w	r2, #1476395008	; 0x58000000
+ 8006a52:	69bb      	ldr	r3, [r7, #24]
+ 8006a54:	6013      	str	r3, [r2, #0]
+
+        temp = EXTI->FTSR1;
+ 8006a56:	f04f 43b0 	mov.w	r3, #1476395008	; 0x58000000
+ 8006a5a:	685b      	ldr	r3, [r3, #4]
+ 8006a5c:	61bb      	str	r3, [r7, #24]
+        temp &= ~(iocurrent);
+ 8006a5e:	693b      	ldr	r3, [r7, #16]
+ 8006a60:	43db      	mvns	r3, r3
+ 8006a62:	69ba      	ldr	r2, [r7, #24]
+ 8006a64:	4013      	ands	r3, r2
+ 8006a66:	61bb      	str	r3, [r7, #24]
+        if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U)
+ 8006a68:	683b      	ldr	r3, [r7, #0]
+ 8006a6a:	685b      	ldr	r3, [r3, #4]
+ 8006a6c:	f403 1300 	and.w	r3, r3, #2097152	; 0x200000
+ 8006a70:	2b00      	cmp	r3, #0
+ 8006a72:	d003      	beq.n	8006a7c <HAL_GPIO_Init+0x2cc>
+        {
+          temp |= iocurrent;
+ 8006a74:	69ba      	ldr	r2, [r7, #24]
+ 8006a76:	693b      	ldr	r3, [r7, #16]
+ 8006a78:	4313      	orrs	r3, r2
+ 8006a7a:	61bb      	str	r3, [r7, #24]
+        }
+        EXTI->FTSR1 = temp;
+ 8006a7c:	f04f 42b0 	mov.w	r2, #1476395008	; 0x58000000
+ 8006a80:	69bb      	ldr	r3, [r7, #24]
+ 8006a82:	6053      	str	r3, [r2, #4]
+
+        temp = EXTI_CurrentCPU->EMR1;
+ 8006a84:	697b      	ldr	r3, [r7, #20]
+ 8006a86:	685b      	ldr	r3, [r3, #4]
+ 8006a88:	61bb      	str	r3, [r7, #24]
+        temp &= ~(iocurrent);
+ 8006a8a:	693b      	ldr	r3, [r7, #16]
+ 8006a8c:	43db      	mvns	r3, r3
+ 8006a8e:	69ba      	ldr	r2, [r7, #24]
+ 8006a90:	4013      	ands	r3, r2
+ 8006a92:	61bb      	str	r3, [r7, #24]
+        if ((GPIO_Init->Mode & EXTI_EVT) != 0x00U)
+ 8006a94:	683b      	ldr	r3, [r7, #0]
+ 8006a96:	685b      	ldr	r3, [r3, #4]
+ 8006a98:	f403 3300 	and.w	r3, r3, #131072	; 0x20000
+ 8006a9c:	2b00      	cmp	r3, #0
+ 8006a9e:	d003      	beq.n	8006aa8 <HAL_GPIO_Init+0x2f8>
+        {
+          temp |= iocurrent;
+ 8006aa0:	69ba      	ldr	r2, [r7, #24]
+ 8006aa2:	693b      	ldr	r3, [r7, #16]
+ 8006aa4:	4313      	orrs	r3, r2
+ 8006aa6:	61bb      	str	r3, [r7, #24]
+        }
+        EXTI_CurrentCPU->EMR1 = temp;
+ 8006aa8:	697b      	ldr	r3, [r7, #20]
+ 8006aaa:	69ba      	ldr	r2, [r7, #24]
+ 8006aac:	605a      	str	r2, [r3, #4]
+
+        /* Clear EXTI line configuration */
+        temp = EXTI_CurrentCPU->IMR1;
+ 8006aae:	697b      	ldr	r3, [r7, #20]
+ 8006ab0:	681b      	ldr	r3, [r3, #0]
+ 8006ab2:	61bb      	str	r3, [r7, #24]
+        temp &= ~(iocurrent);
+ 8006ab4:	693b      	ldr	r3, [r7, #16]
+ 8006ab6:	43db      	mvns	r3, r3
+ 8006ab8:	69ba      	ldr	r2, [r7, #24]
+ 8006aba:	4013      	ands	r3, r2
+ 8006abc:	61bb      	str	r3, [r7, #24]
+        if ((GPIO_Init->Mode & EXTI_IT) != 0x00U)
+ 8006abe:	683b      	ldr	r3, [r7, #0]
+ 8006ac0:	685b      	ldr	r3, [r3, #4]
+ 8006ac2:	f403 3380 	and.w	r3, r3, #65536	; 0x10000
+ 8006ac6:	2b00      	cmp	r3, #0
+ 8006ac8:	d003      	beq.n	8006ad2 <HAL_GPIO_Init+0x322>
+        {
+          temp |= iocurrent;
+ 8006aca:	69ba      	ldr	r2, [r7, #24]
+ 8006acc:	693b      	ldr	r3, [r7, #16]
+ 8006ace:	4313      	orrs	r3, r2
+ 8006ad0:	61bb      	str	r3, [r7, #24]
+        }
+        EXTI_CurrentCPU->IMR1 = temp;
+ 8006ad2:	697b      	ldr	r3, [r7, #20]
+ 8006ad4:	69ba      	ldr	r2, [r7, #24]
+ 8006ad6:	601a      	str	r2, [r3, #0]
+      }
+    }
+
+    position++;
+ 8006ad8:	69fb      	ldr	r3, [r7, #28]
+ 8006ada:	3301      	adds	r3, #1
+ 8006adc:	61fb      	str	r3, [r7, #28]
+  while (((GPIO_Init->Pin) >> position) != 0x00U)
+ 8006ade:	683b      	ldr	r3, [r7, #0]
+ 8006ae0:	681a      	ldr	r2, [r3, #0]
+ 8006ae2:	69fb      	ldr	r3, [r7, #28]
+ 8006ae4:	fa22 f303 	lsr.w	r3, r2, r3
+ 8006ae8:	2b00      	cmp	r3, #0
+ 8006aea:	f47f ae6b 	bne.w	80067c4 <HAL_GPIO_Init+0x14>
+  }
+}
+ 8006aee:	bf00      	nop
+ 8006af0:	bf00      	nop
+ 8006af2:	3724      	adds	r7, #36	; 0x24
+ 8006af4:	46bd      	mov	sp, r7
+ 8006af6:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8006afa:	4770      	bx	lr
+ 8006afc:	58000400 	.word	0x58000400
+
+08006b00 <HAL_GPIO_ReadPin>:
+  * @param  GPIO_Pin: specifies the port bit to read.
+  *         This parameter can be GPIO_PIN_x where x can be (0..15).
+  * @retval The input port pin value.
+  */
+GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
+{
+ 8006b00:	b480      	push	{r7}
+ 8006b02:	b085      	sub	sp, #20
+ 8006b04:	af00      	add	r7, sp, #0
+ 8006b06:	6078      	str	r0, [r7, #4]
+ 8006b08:	460b      	mov	r3, r1
+ 8006b0a:	807b      	strh	r3, [r7, #2]
+  GPIO_PinState bitstatus;
+
+  /* Check the parameters */
+  assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+  if ((GPIOx->IDR & GPIO_Pin) != 0x00U)
+ 8006b0c:	687b      	ldr	r3, [r7, #4]
+ 8006b0e:	691a      	ldr	r2, [r3, #16]
+ 8006b10:	887b      	ldrh	r3, [r7, #2]
+ 8006b12:	4013      	ands	r3, r2
+ 8006b14:	2b00      	cmp	r3, #0
+ 8006b16:	d002      	beq.n	8006b1e <HAL_GPIO_ReadPin+0x1e>
+  {
+    bitstatus = GPIO_PIN_SET;
+ 8006b18:	2301      	movs	r3, #1
+ 8006b1a:	73fb      	strb	r3, [r7, #15]
+ 8006b1c:	e001      	b.n	8006b22 <HAL_GPIO_ReadPin+0x22>
+  }
+  else
+  {
+    bitstatus = GPIO_PIN_RESET;
+ 8006b1e:	2300      	movs	r3, #0
+ 8006b20:	73fb      	strb	r3, [r7, #15]
+  }
+  return bitstatus;
+ 8006b22:	7bfb      	ldrb	r3, [r7, #15]
+}
+ 8006b24:	4618      	mov	r0, r3
+ 8006b26:	3714      	adds	r7, #20
+ 8006b28:	46bd      	mov	sp, r7
+ 8006b2a:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8006b2e:	4770      	bx	lr
+
+08006b30 <HAL_GPIO_WritePin>:
+  *            @arg GPIO_PIN_RESET: to clear the port pin
+  *            @arg GPIO_PIN_SET: to set the port pin
+  * @retval None
+  */
+void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
+{
+ 8006b30:	b480      	push	{r7}
+ 8006b32:	b083      	sub	sp, #12
+ 8006b34:	af00      	add	r7, sp, #0
+ 8006b36:	6078      	str	r0, [r7, #4]
+ 8006b38:	460b      	mov	r3, r1
+ 8006b3a:	807b      	strh	r3, [r7, #2]
+ 8006b3c:	4613      	mov	r3, r2
+ 8006b3e:	707b      	strb	r3, [r7, #1]
+  /* Check the parameters */
+  assert_param(IS_GPIO_PIN(GPIO_Pin));
+  assert_param(IS_GPIO_PIN_ACTION(PinState));
+
+  if (PinState != GPIO_PIN_RESET)
+ 8006b40:	787b      	ldrb	r3, [r7, #1]
+ 8006b42:	2b00      	cmp	r3, #0
+ 8006b44:	d003      	beq.n	8006b4e <HAL_GPIO_WritePin+0x1e>
+  {
+    GPIOx->BSRR = GPIO_Pin;
+ 8006b46:	887a      	ldrh	r2, [r7, #2]
+ 8006b48:	687b      	ldr	r3, [r7, #4]
+ 8006b4a:	619a      	str	r2, [r3, #24]
+  }
+  else
+  {
+    GPIOx->BSRR = (uint32_t)GPIO_Pin << GPIO_NUMBER;
+  }
+}
+ 8006b4c:	e003      	b.n	8006b56 <HAL_GPIO_WritePin+0x26>
+    GPIOx->BSRR = (uint32_t)GPIO_Pin << GPIO_NUMBER;
+ 8006b4e:	887b      	ldrh	r3, [r7, #2]
+ 8006b50:	041a      	lsls	r2, r3, #16
+ 8006b52:	687b      	ldr	r3, [r7, #4]
+ 8006b54:	619a      	str	r2, [r3, #24]
+}
+ 8006b56:	bf00      	nop
+ 8006b58:	370c      	adds	r7, #12
+ 8006b5a:	46bd      	mov	sp, r7
+ 8006b5c:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8006b60:	4770      	bx	lr
+
+08006b62 <HAL_MDMA_Init>:
+  * @param  hmdma: Pointer to a MDMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified MDMA Channel.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MDMA_Init(MDMA_HandleTypeDef *hmdma)
+{
+ 8006b62:	b580      	push	{r7, lr}
+ 8006b64:	b084      	sub	sp, #16
+ 8006b66:	af00      	add	r7, sp, #0
+ 8006b68:	6078      	str	r0, [r7, #4]
+  uint32_t tickstart = HAL_GetTick();
+ 8006b6a:	f7fb fbfb 	bl	8002364 <HAL_GetTick>
+ 8006b6e:	60f8      	str	r0, [r7, #12]
+
+  /* Check the MDMA peripheral handle */
+  if(hmdma == NULL)
+ 8006b70:	687b      	ldr	r3, [r7, #4]
+ 8006b72:	2b00      	cmp	r3, #0
+ 8006b74:	d101      	bne.n	8006b7a <HAL_MDMA_Init+0x18>
+  {
+    return HAL_ERROR;
+ 8006b76:	2301      	movs	r3, #1
+ 8006b78:	e03b      	b.n	8006bf2 <HAL_MDMA_Init+0x90>
+  assert_param(IS_MDMA_BLOCK_ADDR_OFFSET(hmdma->Init.SourceBlockAddressOffset));
+  assert_param(IS_MDMA_BLOCK_ADDR_OFFSET(hmdma->Init.DestBlockAddressOffset));
+
+
+  /* Allocate lock resource */
+  __HAL_UNLOCK(hmdma);
+ 8006b7a:	687b      	ldr	r3, [r7, #4]
+ 8006b7c:	2200      	movs	r2, #0
+ 8006b7e:	f883 203c 	strb.w	r2, [r3, #60]	; 0x3c
+
+  /* Change MDMA peripheral state */
+  hmdma->State = HAL_MDMA_STATE_BUSY;
+ 8006b82:	687b      	ldr	r3, [r7, #4]
+ 8006b84:	2202      	movs	r2, #2
+ 8006b86:	f883 203d 	strb.w	r2, [r3, #61]	; 0x3d
+
+  /* Disable the MDMA channel */
+  __HAL_MDMA_DISABLE(hmdma);
+ 8006b8a:	687b      	ldr	r3, [r7, #4]
+ 8006b8c:	681b      	ldr	r3, [r3, #0]
+ 8006b8e:	68da      	ldr	r2, [r3, #12]
+ 8006b90:	687b      	ldr	r3, [r7, #4]
+ 8006b92:	681b      	ldr	r3, [r3, #0]
+ 8006b94:	f022 0201 	bic.w	r2, r2, #1
+ 8006b98:	60da      	str	r2, [r3, #12]
+
+  /* Check if the MDMA channel is effectively disabled */
+  while((hmdma->Instance->CCR & MDMA_CCR_EN) != 0U)
+ 8006b9a:	e00f      	b.n	8006bbc <HAL_MDMA_Init+0x5a>
+  {
+    /* Check for the Timeout */
+    if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_MDMA_ABORT)
+ 8006b9c:	f7fb fbe2 	bl	8002364 <HAL_GetTick>
+ 8006ba0:	4602      	mov	r2, r0
+ 8006ba2:	68fb      	ldr	r3, [r7, #12]
+ 8006ba4:	1ad3      	subs	r3, r2, r3
+ 8006ba6:	2b05      	cmp	r3, #5
+ 8006ba8:	d908      	bls.n	8006bbc <HAL_MDMA_Init+0x5a>
+    {
+      /* Update error code */
+      hmdma->ErrorCode = HAL_MDMA_ERROR_TIMEOUT;
+ 8006baa:	687b      	ldr	r3, [r7, #4]
+ 8006bac:	2240      	movs	r2, #64	; 0x40
+ 8006bae:	669a      	str	r2, [r3, #104]	; 0x68
+
+      /* Change the MDMA state */
+      hmdma->State = HAL_MDMA_STATE_ERROR;
+ 8006bb0:	687b      	ldr	r3, [r7, #4]
+ 8006bb2:	2203      	movs	r2, #3
+ 8006bb4:	f883 203d 	strb.w	r2, [r3, #61]	; 0x3d
+
+      return HAL_ERROR;
+ 8006bb8:	2301      	movs	r3, #1
+ 8006bba:	e01a      	b.n	8006bf2 <HAL_MDMA_Init+0x90>
+  while((hmdma->Instance->CCR & MDMA_CCR_EN) != 0U)
+ 8006bbc:	687b      	ldr	r3, [r7, #4]
+ 8006bbe:	681b      	ldr	r3, [r3, #0]
+ 8006bc0:	68db      	ldr	r3, [r3, #12]
+ 8006bc2:	f003 0301 	and.w	r3, r3, #1
+ 8006bc6:	2b00      	cmp	r3, #0
+ 8006bc8:	d1e8      	bne.n	8006b9c <HAL_MDMA_Init+0x3a>
+    }
+  }
+
+  /* Initialize the MDMA channel registers */
+  MDMA_Init(hmdma);
+ 8006bca:	6878      	ldr	r0, [r7, #4]
+ 8006bcc:	f000 f9bc 	bl	8006f48 <MDMA_Init>
+
+  /* Reset the MDMA first/last linkedlist node addresses and node counter */
+  hmdma->FirstLinkedListNodeAddress  = 0;
+ 8006bd0:	687b      	ldr	r3, [r7, #4]
+ 8006bd2:	2200      	movs	r2, #0
+ 8006bd4:	65da      	str	r2, [r3, #92]	; 0x5c
+  hmdma->LastLinkedListNodeAddress   = 0;
+ 8006bd6:	687b      	ldr	r3, [r7, #4]
+ 8006bd8:	2200      	movs	r2, #0
+ 8006bda:	661a      	str	r2, [r3, #96]	; 0x60
+  hmdma->LinkedListNodeCounter  = 0;
+ 8006bdc:	687b      	ldr	r3, [r7, #4]
+ 8006bde:	2200      	movs	r2, #0
+ 8006be0:	665a      	str	r2, [r3, #100]	; 0x64
+
+  /* Initialize the error code */
+  hmdma->ErrorCode = HAL_MDMA_ERROR_NONE;
+ 8006be2:	687b      	ldr	r3, [r7, #4]
+ 8006be4:	2200      	movs	r2, #0
+ 8006be6:	669a      	str	r2, [r3, #104]	; 0x68
+
+  /* Initialize the MDMA state */
+  hmdma->State = HAL_MDMA_STATE_READY;
+ 8006be8:	687b      	ldr	r3, [r7, #4]
+ 8006bea:	2201      	movs	r2, #1
+ 8006bec:	f883 203d 	strb.w	r2, [r3, #61]	; 0x3d
+
+  return HAL_OK;
+ 8006bf0:	2300      	movs	r3, #0
+}
+ 8006bf2:	4618      	mov	r0, r3
+ 8006bf4:	3710      	adds	r7, #16
+ 8006bf6:	46bd      	mov	sp, r7
+ 8006bf8:	bd80      	pop	{r7, pc}
+
+08006bfa <HAL_MDMA_ConfigPostRequestMask>:
+  * @param  MaskData:    specifies the value to be written to MaskAddress after a request is served.
+  *                      MaskAddress and MaskData could be used to automatically clear a peripheral flag when the request is served.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MDMA_ConfigPostRequestMask(MDMA_HandleTypeDef *hmdma, uint32_t MaskAddress, uint32_t MaskData)
+{
+ 8006bfa:	b480      	push	{r7}
+ 8006bfc:	b087      	sub	sp, #28
+ 8006bfe:	af00      	add	r7, sp, #0
+ 8006c00:	60f8      	str	r0, [r7, #12]
+ 8006c02:	60b9      	str	r1, [r7, #8]
+ 8006c04:	607a      	str	r2, [r7, #4]
+  HAL_StatusTypeDef  status = HAL_OK;
+ 8006c06:	2300      	movs	r3, #0
+ 8006c08:	75fb      	strb	r3, [r7, #23]
+
+  /* Check the MDMA peripheral handle */
+  if(hmdma == NULL)
+ 8006c0a:	68fb      	ldr	r3, [r7, #12]
+ 8006c0c:	2b00      	cmp	r3, #0
+ 8006c0e:	d101      	bne.n	8006c14 <HAL_MDMA_ConfigPostRequestMask+0x1a>
+  {
+    return HAL_ERROR;
+ 8006c10:	2301      	movs	r3, #1
+ 8006c12:	e03e      	b.n	8006c92 <HAL_MDMA_ConfigPostRequestMask+0x98>
+  }
+
+  /* Process locked */
+  __HAL_LOCK(hmdma);
+ 8006c14:	68fb      	ldr	r3, [r7, #12]
+ 8006c16:	f893 303c 	ldrb.w	r3, [r3, #60]	; 0x3c
+ 8006c1a:	2b01      	cmp	r3, #1
+ 8006c1c:	d101      	bne.n	8006c22 <HAL_MDMA_ConfigPostRequestMask+0x28>
+ 8006c1e:	2302      	movs	r3, #2
+ 8006c20:	e037      	b.n	8006c92 <HAL_MDMA_ConfigPostRequestMask+0x98>
+ 8006c22:	68fb      	ldr	r3, [r7, #12]
+ 8006c24:	2201      	movs	r2, #1
+ 8006c26:	f883 203c 	strb.w	r2, [r3, #60]	; 0x3c
+
+  if(HAL_MDMA_STATE_READY == hmdma->State)
+ 8006c2a:	68fb      	ldr	r3, [r7, #12]
+ 8006c2c:	f893 303d 	ldrb.w	r3, [r3, #61]	; 0x3d
+ 8006c30:	b2db      	uxtb	r3, r3
+ 8006c32:	2b01      	cmp	r3, #1
+ 8006c34:	d126      	bne.n	8006c84 <HAL_MDMA_ConfigPostRequestMask+0x8a>
+  {
+    /* if HW request set Post Request MaskAddress and MaskData,  */
+    if((hmdma->Instance->CTCR & MDMA_CTCR_SWRM) == 0U)
+ 8006c36:	68fb      	ldr	r3, [r7, #12]
+ 8006c38:	681b      	ldr	r3, [r3, #0]
+ 8006c3a:	691b      	ldr	r3, [r3, #16]
+ 8006c3c:	f003 4380 	and.w	r3, r3, #1073741824	; 0x40000000
+ 8006c40:	2b00      	cmp	r3, #0
+ 8006c42:	d11c      	bne.n	8006c7e <HAL_MDMA_ConfigPostRequestMask+0x84>
+    {
+      /* Set the HW request clear Mask and Data */
+      hmdma->Instance->CMAR = MaskAddress;
+ 8006c44:	68fb      	ldr	r3, [r7, #12]
+ 8006c46:	681b      	ldr	r3, [r3, #0]
+ 8006c48:	68ba      	ldr	r2, [r7, #8]
+ 8006c4a:	631a      	str	r2, [r3, #48]	; 0x30
+      hmdma->Instance->CMDR = MaskData;
+ 8006c4c:	68fb      	ldr	r3, [r7, #12]
+ 8006c4e:	681b      	ldr	r3, [r3, #0]
+ 8006c50:	687a      	ldr	r2, [r7, #4]
+ 8006c52:	635a      	str	r2, [r3, #52]	; 0x34
+      -If the request is done by SW : BWM could be set to 1 or 0.
+      -If the request is done by a peripheral :
+         If mask address not set (0) => BWM must be set to 0
+         If mask address set (different than 0) => BWM could be set to 1 or 0
+      */
+      if(MaskAddress == 0U)
+ 8006c54:	68bb      	ldr	r3, [r7, #8]
+ 8006c56:	2b00      	cmp	r3, #0
+ 8006c58:	d108      	bne.n	8006c6c <HAL_MDMA_ConfigPostRequestMask+0x72>
+      {
+        hmdma->Instance->CTCR &=  ~MDMA_CTCR_BWM;
+ 8006c5a:	68fb      	ldr	r3, [r7, #12]
+ 8006c5c:	681b      	ldr	r3, [r3, #0]
+ 8006c5e:	691a      	ldr	r2, [r3, #16]
+ 8006c60:	68fb      	ldr	r3, [r7, #12]
+ 8006c62:	681b      	ldr	r3, [r3, #0]
+ 8006c64:	f022 4200 	bic.w	r2, r2, #2147483648	; 0x80000000
+ 8006c68:	611a      	str	r2, [r3, #16]
+ 8006c6a:	e00d      	b.n	8006c88 <HAL_MDMA_ConfigPostRequestMask+0x8e>
+      }
+      else
+      {
+        hmdma->Instance->CTCR |=  MDMA_CTCR_BWM;
+ 8006c6c:	68fb      	ldr	r3, [r7, #12]
+ 8006c6e:	681b      	ldr	r3, [r3, #0]
+ 8006c70:	691a      	ldr	r2, [r3, #16]
+ 8006c72:	68fb      	ldr	r3, [r7, #12]
+ 8006c74:	681b      	ldr	r3, [r3, #0]
+ 8006c76:	f042 4200 	orr.w	r2, r2, #2147483648	; 0x80000000
+ 8006c7a:	611a      	str	r2, [r3, #16]
+ 8006c7c:	e004      	b.n	8006c88 <HAL_MDMA_ConfigPostRequestMask+0x8e>
+      }
+    }
+    else
+    {
+      /* Return error status */
+      status =  HAL_ERROR;
+ 8006c7e:	2301      	movs	r3, #1
+ 8006c80:	75fb      	strb	r3, [r7, #23]
+ 8006c82:	e001      	b.n	8006c88 <HAL_MDMA_ConfigPostRequestMask+0x8e>
+    }
+  }
+  else
+  {
+    /* Return error status */
+    status =  HAL_ERROR;
+ 8006c84:	2301      	movs	r3, #1
+ 8006c86:	75fb      	strb	r3, [r7, #23]
+  }
+  /* Release Lock */
+  __HAL_UNLOCK(hmdma);
+ 8006c88:	68fb      	ldr	r3, [r7, #12]
+ 8006c8a:	2200      	movs	r2, #0
+ 8006c8c:	f883 203c 	strb.w	r2, [r3, #60]	; 0x3c
+
+  return status;
+ 8006c90:	7dfb      	ldrb	r3, [r7, #23]
+}
+ 8006c92:	4618      	mov	r0, r3
+ 8006c94:	371c      	adds	r7, #28
+ 8006c96:	46bd      	mov	sp, r7
+ 8006c98:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8006c9c:	4770      	bx	lr
+	...
+
+08006ca0 <HAL_MDMA_IRQHandler>:
+  * @param  hmdma: pointer to a MDMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified MDMA Channel.
+  * @retval None
+  */
+void HAL_MDMA_IRQHandler(MDMA_HandleTypeDef *hmdma)
+{
+ 8006ca0:	b580      	push	{r7, lr}
+ 8006ca2:	b086      	sub	sp, #24
+ 8006ca4:	af00      	add	r7, sp, #0
+ 8006ca6:	6078      	str	r0, [r7, #4]
+  __IO uint32_t count = 0;
+ 8006ca8:	2300      	movs	r3, #0
+ 8006caa:	60bb      	str	r3, [r7, #8]
+  uint32_t timeout = SystemCoreClock / 9600U;
+ 8006cac:	4b91      	ldr	r3, [pc, #580]	; (8006ef4 <HAL_MDMA_IRQHandler+0x254>)
+ 8006cae:	681b      	ldr	r3, [r3, #0]
+ 8006cb0:	4a91      	ldr	r2, [pc, #580]	; (8006ef8 <HAL_MDMA_IRQHandler+0x258>)
+ 8006cb2:	fba2 2303 	umull	r2, r3, r2, r3
+ 8006cb6:	0a9b      	lsrs	r3, r3, #10
+ 8006cb8:	617b      	str	r3, [r7, #20]
+
+  uint32_t generalIntFlag, errorFlag;
+
+  /* General Interrupt Flag management ****************************************/
+  generalIntFlag =  1UL << ((((uint32_t)hmdma->Instance - (uint32_t)(MDMA_Channel0))/HAL_MDMA_CHANNEL_SIZE) & 0x1FU);
+ 8006cba:	687b      	ldr	r3, [r7, #4]
+ 8006cbc:	681b      	ldr	r3, [r3, #0]
+ 8006cbe:	461a      	mov	r2, r3
+ 8006cc0:	4b8e      	ldr	r3, [pc, #568]	; (8006efc <HAL_MDMA_IRQHandler+0x25c>)
+ 8006cc2:	4413      	add	r3, r2
+ 8006cc4:	099b      	lsrs	r3, r3, #6
+ 8006cc6:	f003 031f 	and.w	r3, r3, #31
+ 8006cca:	2201      	movs	r2, #1
+ 8006ccc:	fa02 f303 	lsl.w	r3, r2, r3
+ 8006cd0:	613b      	str	r3, [r7, #16]
+  if((MDMA->GISR0 & generalIntFlag) == 0U)
+ 8006cd2:	f04f 43a4 	mov.w	r3, #1375731712	; 0x52000000
+ 8006cd6:	681a      	ldr	r2, [r3, #0]
+ 8006cd8:	693b      	ldr	r3, [r7, #16]
+ 8006cda:	4013      	ands	r3, r2
+ 8006cdc:	2b00      	cmp	r3, #0
+ 8006cde:	f000 812d 	beq.w	8006f3c <HAL_MDMA_IRQHandler+0x29c>
+  {
+    return; /* the  General interrupt flag for the current channel is down , nothing to do */
+  }
+
+  /* Transfer Error Interrupt management ***************************************/
+  if((__HAL_MDMA_GET_FLAG(hmdma, MDMA_FLAG_TE) != 0U))
+ 8006ce2:	687b      	ldr	r3, [r7, #4]
+ 8006ce4:	681b      	ldr	r3, [r3, #0]
+ 8006ce6:	681b      	ldr	r3, [r3, #0]
+ 8006ce8:	f003 0301 	and.w	r3, r3, #1
+ 8006cec:	2b00      	cmp	r3, #0
+ 8006cee:	d054      	beq.n	8006d9a <HAL_MDMA_IRQHandler+0xfa>
+  {
+    if(__HAL_MDMA_GET_IT_SOURCE(hmdma, MDMA_IT_TE) != 0U)
+ 8006cf0:	687b      	ldr	r3, [r7, #4]
+ 8006cf2:	681b      	ldr	r3, [r3, #0]
+ 8006cf4:	68db      	ldr	r3, [r3, #12]
+ 8006cf6:	f003 0302 	and.w	r3, r3, #2
+ 8006cfa:	2b00      	cmp	r3, #0
+ 8006cfc:	d04d      	beq.n	8006d9a <HAL_MDMA_IRQHandler+0xfa>
+    {
+      /* Disable the transfer error interrupt */
+      __HAL_MDMA_DISABLE_IT(hmdma, MDMA_IT_TE);
+ 8006cfe:	687b      	ldr	r3, [r7, #4]
+ 8006d00:	681b      	ldr	r3, [r3, #0]
+ 8006d02:	68da      	ldr	r2, [r3, #12]
+ 8006d04:	687b      	ldr	r3, [r7, #4]
+ 8006d06:	681b      	ldr	r3, [r3, #0]
+ 8006d08:	f022 0202 	bic.w	r2, r2, #2
+ 8006d0c:	60da      	str	r2, [r3, #12]
+
+      /* Get the transfer error source flag */
+      errorFlag = hmdma->Instance->CESR;
+ 8006d0e:	687b      	ldr	r3, [r7, #4]
+ 8006d10:	681b      	ldr	r3, [r3, #0]
+ 8006d12:	689b      	ldr	r3, [r3, #8]
+ 8006d14:	60fb      	str	r3, [r7, #12]
+
+      if((errorFlag & MDMA_CESR_TED) == 0U)
+ 8006d16:	68fb      	ldr	r3, [r7, #12]
+ 8006d18:	f003 0380 	and.w	r3, r3, #128	; 0x80
+ 8006d1c:	2b00      	cmp	r3, #0
+ 8006d1e:	d106      	bne.n	8006d2e <HAL_MDMA_IRQHandler+0x8e>
+      {
+        /* Update error code : Read Transfer error  */
+        hmdma->ErrorCode |= HAL_MDMA_ERROR_READ_XFER;
+ 8006d20:	687b      	ldr	r3, [r7, #4]
+ 8006d22:	6e9b      	ldr	r3, [r3, #104]	; 0x68
+ 8006d24:	f043 0201 	orr.w	r2, r3, #1
+ 8006d28:	687b      	ldr	r3, [r7, #4]
+ 8006d2a:	669a      	str	r2, [r3, #104]	; 0x68
+ 8006d2c:	e005      	b.n	8006d3a <HAL_MDMA_IRQHandler+0x9a>
+      }
+      else
+      {
+        /* Update error code : Write Transfer error */
+        hmdma->ErrorCode |= HAL_MDMA_ERROR_WRITE_XFER;
+ 8006d2e:	687b      	ldr	r3, [r7, #4]
+ 8006d30:	6e9b      	ldr	r3, [r3, #104]	; 0x68
+ 8006d32:	f043 0202 	orr.w	r2, r3, #2
+ 8006d36:	687b      	ldr	r3, [r7, #4]
+ 8006d38:	669a      	str	r2, [r3, #104]	; 0x68
+      }
+
+      if((errorFlag & MDMA_CESR_TEMD) != 0U)
+ 8006d3a:	68fb      	ldr	r3, [r7, #12]
+ 8006d3c:	f403 7300 	and.w	r3, r3, #512	; 0x200
+ 8006d40:	2b00      	cmp	r3, #0
+ 8006d42:	d005      	beq.n	8006d50 <HAL_MDMA_IRQHandler+0xb0>
+      {
+        /* Update error code : Error Mask Data */
+        hmdma->ErrorCode |= HAL_MDMA_ERROR_MASK_DATA;
+ 8006d44:	687b      	ldr	r3, [r7, #4]
+ 8006d46:	6e9b      	ldr	r3, [r3, #104]	; 0x68
+ 8006d48:	f043 0204 	orr.w	r2, r3, #4
+ 8006d4c:	687b      	ldr	r3, [r7, #4]
+ 8006d4e:	669a      	str	r2, [r3, #104]	; 0x68
+      }
+
+      if((errorFlag & MDMA_CESR_TELD) != 0U)
+ 8006d50:	68fb      	ldr	r3, [r7, #12]
+ 8006d52:	f403 7380 	and.w	r3, r3, #256	; 0x100
+ 8006d56:	2b00      	cmp	r3, #0
+ 8006d58:	d005      	beq.n	8006d66 <HAL_MDMA_IRQHandler+0xc6>
+      {
+        /* Update error code : Error Linked list */
+        hmdma->ErrorCode |= HAL_MDMA_ERROR_LINKED_LIST;
+ 8006d5a:	687b      	ldr	r3, [r7, #4]
+ 8006d5c:	6e9b      	ldr	r3, [r3, #104]	; 0x68
+ 8006d5e:	f043 0208 	orr.w	r2, r3, #8
+ 8006d62:	687b      	ldr	r3, [r7, #4]
+ 8006d64:	669a      	str	r2, [r3, #104]	; 0x68
+      }
+
+      if((errorFlag & MDMA_CESR_ASE) != 0U)
+ 8006d66:	68fb      	ldr	r3, [r7, #12]
+ 8006d68:	f403 6380 	and.w	r3, r3, #1024	; 0x400
+ 8006d6c:	2b00      	cmp	r3, #0
+ 8006d6e:	d005      	beq.n	8006d7c <HAL_MDMA_IRQHandler+0xdc>
+      {
+        /* Update error code : Address/Size alignment error */
+        hmdma->ErrorCode |= HAL_MDMA_ERROR_ALIGNMENT;
+ 8006d70:	687b      	ldr	r3, [r7, #4]
+ 8006d72:	6e9b      	ldr	r3, [r3, #104]	; 0x68
+ 8006d74:	f043 0210 	orr.w	r2, r3, #16
+ 8006d78:	687b      	ldr	r3, [r7, #4]
+ 8006d7a:	669a      	str	r2, [r3, #104]	; 0x68
+      }
+
+      if((errorFlag & MDMA_CESR_BSE) != 0U)
+ 8006d7c:	68fb      	ldr	r3, [r7, #12]
+ 8006d7e:	f403 6300 	and.w	r3, r3, #2048	; 0x800
+ 8006d82:	2b00      	cmp	r3, #0
+ 8006d84:	d005      	beq.n	8006d92 <HAL_MDMA_IRQHandler+0xf2>
+      {
+        /* Update error code : Block Size error error */
+        hmdma->ErrorCode |= HAL_MDMA_ERROR_BLOCK_SIZE;
+ 8006d86:	687b      	ldr	r3, [r7, #4]
+ 8006d88:	6e9b      	ldr	r3, [r3, #104]	; 0x68
+ 8006d8a:	f043 0220 	orr.w	r2, r3, #32
+ 8006d8e:	687b      	ldr	r3, [r7, #4]
+ 8006d90:	669a      	str	r2, [r3, #104]	; 0x68
+      }
+
+      /* Clear the transfer error flags */
+      __HAL_MDMA_CLEAR_FLAG(hmdma, MDMA_FLAG_TE);
+ 8006d92:	687b      	ldr	r3, [r7, #4]
+ 8006d94:	681b      	ldr	r3, [r3, #0]
+ 8006d96:	2201      	movs	r2, #1
+ 8006d98:	605a      	str	r2, [r3, #4]
+    }
+  }
+
+  /* Buffer Transfer Complete Interrupt management ******************************/
+  if((__HAL_MDMA_GET_FLAG(hmdma, MDMA_FLAG_BFTC) != 0U))
+ 8006d9a:	687b      	ldr	r3, [r7, #4]
+ 8006d9c:	681b      	ldr	r3, [r3, #0]
+ 8006d9e:	681b      	ldr	r3, [r3, #0]
+ 8006da0:	f003 0310 	and.w	r3, r3, #16
+ 8006da4:	2b00      	cmp	r3, #0
+ 8006da6:	d012      	beq.n	8006dce <HAL_MDMA_IRQHandler+0x12e>
+  {
+    if(__HAL_MDMA_GET_IT_SOURCE(hmdma, MDMA_IT_BFTC) != 0U)
+ 8006da8:	687b      	ldr	r3, [r7, #4]
+ 8006daa:	681b      	ldr	r3, [r3, #0]
+ 8006dac:	68db      	ldr	r3, [r3, #12]
+ 8006dae:	f003 0320 	and.w	r3, r3, #32
+ 8006db2:	2b00      	cmp	r3, #0
+ 8006db4:	d00b      	beq.n	8006dce <HAL_MDMA_IRQHandler+0x12e>
+    {
+      /* Clear the buffer transfer complete flag */
+      __HAL_MDMA_CLEAR_FLAG(hmdma, MDMA_FLAG_BFTC);
+ 8006db6:	687b      	ldr	r3, [r7, #4]
+ 8006db8:	681b      	ldr	r3, [r3, #0]
+ 8006dba:	2210      	movs	r2, #16
+ 8006dbc:	605a      	str	r2, [r3, #4]
+
+      if(hmdma->XferBufferCpltCallback != NULL)
+ 8006dbe:	687b      	ldr	r3, [r7, #4]
+ 8006dc0:	6c9b      	ldr	r3, [r3, #72]	; 0x48
+ 8006dc2:	2b00      	cmp	r3, #0
+ 8006dc4:	d003      	beq.n	8006dce <HAL_MDMA_IRQHandler+0x12e>
+      {
+        /* Buffer transfer callback */
+        hmdma->XferBufferCpltCallback(hmdma);
+ 8006dc6:	687b      	ldr	r3, [r7, #4]
+ 8006dc8:	6c9b      	ldr	r3, [r3, #72]	; 0x48
+ 8006dca:	6878      	ldr	r0, [r7, #4]
+ 8006dcc:	4798      	blx	r3
+      }
+    }
+  }
+
+  /* Block Transfer Complete Interrupt management ******************************/
+  if((__HAL_MDMA_GET_FLAG(hmdma, MDMA_FLAG_BT) != 0U))
+ 8006dce:	687b      	ldr	r3, [r7, #4]
+ 8006dd0:	681b      	ldr	r3, [r3, #0]
+ 8006dd2:	681b      	ldr	r3, [r3, #0]
+ 8006dd4:	f003 0308 	and.w	r3, r3, #8
+ 8006dd8:	2b00      	cmp	r3, #0
+ 8006dda:	d012      	beq.n	8006e02 <HAL_MDMA_IRQHandler+0x162>
+  {
+    if(__HAL_MDMA_GET_IT_SOURCE(hmdma, MDMA_IT_BT) != 0U)
+ 8006ddc:	687b      	ldr	r3, [r7, #4]
+ 8006dde:	681b      	ldr	r3, [r3, #0]
+ 8006de0:	68db      	ldr	r3, [r3, #12]
+ 8006de2:	f003 0310 	and.w	r3, r3, #16
+ 8006de6:	2b00      	cmp	r3, #0
+ 8006de8:	d00b      	beq.n	8006e02 <HAL_MDMA_IRQHandler+0x162>
+    {
+      /* Clear the block transfer complete flag */
+      __HAL_MDMA_CLEAR_FLAG(hmdma, MDMA_FLAG_BT);
+ 8006dea:	687b      	ldr	r3, [r7, #4]
+ 8006dec:	681b      	ldr	r3, [r3, #0]
+ 8006dee:	2208      	movs	r2, #8
+ 8006df0:	605a      	str	r2, [r3, #4]
+
+      if(hmdma->XferBlockCpltCallback != NULL)
+ 8006df2:	687b      	ldr	r3, [r7, #4]
+ 8006df4:	6cdb      	ldr	r3, [r3, #76]	; 0x4c
+ 8006df6:	2b00      	cmp	r3, #0
+ 8006df8:	d003      	beq.n	8006e02 <HAL_MDMA_IRQHandler+0x162>
+      {
+        /* Block transfer callback */
+        hmdma->XferBlockCpltCallback(hmdma);
+ 8006dfa:	687b      	ldr	r3, [r7, #4]
+ 8006dfc:	6cdb      	ldr	r3, [r3, #76]	; 0x4c
+ 8006dfe:	6878      	ldr	r0, [r7, #4]
+ 8006e00:	4798      	blx	r3
+      }
+    }
+  }
+
+  /* Repeated Block Transfer Complete Interrupt management ******************************/
+  if((__HAL_MDMA_GET_FLAG(hmdma, MDMA_FLAG_BRT) != 0U))
+ 8006e02:	687b      	ldr	r3, [r7, #4]
+ 8006e04:	681b      	ldr	r3, [r3, #0]
+ 8006e06:	681b      	ldr	r3, [r3, #0]
+ 8006e08:	f003 0304 	and.w	r3, r3, #4
+ 8006e0c:	2b00      	cmp	r3, #0
+ 8006e0e:	d012      	beq.n	8006e36 <HAL_MDMA_IRQHandler+0x196>
+  {
+    if(__HAL_MDMA_GET_IT_SOURCE(hmdma, MDMA_IT_BRT) != 0U)
+ 8006e10:	687b      	ldr	r3, [r7, #4]
+ 8006e12:	681b      	ldr	r3, [r3, #0]
+ 8006e14:	68db      	ldr	r3, [r3, #12]
+ 8006e16:	f003 0308 	and.w	r3, r3, #8
+ 8006e1a:	2b00      	cmp	r3, #0
+ 8006e1c:	d00b      	beq.n	8006e36 <HAL_MDMA_IRQHandler+0x196>
+    {
+      /* Clear the repeat block transfer complete flag */
+      __HAL_MDMA_CLEAR_FLAG(hmdma, MDMA_FLAG_BRT);
+ 8006e1e:	687b      	ldr	r3, [r7, #4]
+ 8006e20:	681b      	ldr	r3, [r3, #0]
+ 8006e22:	2204      	movs	r2, #4
+ 8006e24:	605a      	str	r2, [r3, #4]
+
+      if(hmdma->XferRepeatBlockCpltCallback != NULL)
+ 8006e26:	687b      	ldr	r3, [r7, #4]
+ 8006e28:	6d1b      	ldr	r3, [r3, #80]	; 0x50
+ 8006e2a:	2b00      	cmp	r3, #0
+ 8006e2c:	d003      	beq.n	8006e36 <HAL_MDMA_IRQHandler+0x196>
+      {
+        /* Repeated Block transfer callback */
+        hmdma->XferRepeatBlockCpltCallback(hmdma);
+ 8006e2e:	687b      	ldr	r3, [r7, #4]
+ 8006e30:	6d1b      	ldr	r3, [r3, #80]	; 0x50
+ 8006e32:	6878      	ldr	r0, [r7, #4]
+ 8006e34:	4798      	blx	r3
+      }
+    }
+  }
+
+  /* Channel Transfer Complete Interrupt management ***********************************/
+  if((__HAL_MDMA_GET_FLAG(hmdma, MDMA_FLAG_CTC) != 0U))
+ 8006e36:	687b      	ldr	r3, [r7, #4]
+ 8006e38:	681b      	ldr	r3, [r3, #0]
+ 8006e3a:	681b      	ldr	r3, [r3, #0]
+ 8006e3c:	f003 0302 	and.w	r3, r3, #2
+ 8006e40:	2b00      	cmp	r3, #0
+ 8006e42:	d039      	beq.n	8006eb8 <HAL_MDMA_IRQHandler+0x218>
+  {
+    if(__HAL_MDMA_GET_IT_SOURCE(hmdma, MDMA_IT_CTC) != 0U)
+ 8006e44:	687b      	ldr	r3, [r7, #4]
+ 8006e46:	681b      	ldr	r3, [r3, #0]
+ 8006e48:	68db      	ldr	r3, [r3, #12]
+ 8006e4a:	f003 0304 	and.w	r3, r3, #4
+ 8006e4e:	2b00      	cmp	r3, #0
+ 8006e50:	d032      	beq.n	8006eb8 <HAL_MDMA_IRQHandler+0x218>
+    {
+      /* Disable all the transfer interrupts */
+      __HAL_MDMA_DISABLE_IT(hmdma, (MDMA_IT_TE | MDMA_IT_CTC | MDMA_IT_BT | MDMA_IT_BRT | MDMA_IT_BFTC));
+ 8006e52:	687b      	ldr	r3, [r7, #4]
+ 8006e54:	681b      	ldr	r3, [r3, #0]
+ 8006e56:	68da      	ldr	r2, [r3, #12]
+ 8006e58:	687b      	ldr	r3, [r7, #4]
+ 8006e5a:	681b      	ldr	r3, [r3, #0]
+ 8006e5c:	f022 023e 	bic.w	r2, r2, #62	; 0x3e
+ 8006e60:	60da      	str	r2, [r3, #12]
+
+      if(HAL_MDMA_STATE_ABORT == hmdma->State)
+ 8006e62:	687b      	ldr	r3, [r7, #4]
+ 8006e64:	f893 303d 	ldrb.w	r3, [r3, #61]	; 0x3d
+ 8006e68:	b2db      	uxtb	r3, r3
+ 8006e6a:	2b04      	cmp	r3, #4
+ 8006e6c:	d110      	bne.n	8006e90 <HAL_MDMA_IRQHandler+0x1f0>
+      {
+        /* Process Unlocked */
+        __HAL_UNLOCK(hmdma);
+ 8006e6e:	687b      	ldr	r3, [r7, #4]
+ 8006e70:	2200      	movs	r2, #0
+ 8006e72:	f883 203c 	strb.w	r2, [r3, #60]	; 0x3c
+
+        /* Change the DMA state */
+        hmdma->State = HAL_MDMA_STATE_READY;
+ 8006e76:	687b      	ldr	r3, [r7, #4]
+ 8006e78:	2201      	movs	r2, #1
+ 8006e7a:	f883 203d 	strb.w	r2, [r3, #61]	; 0x3d
+
+        if(hmdma->XferAbortCallback != NULL)
+ 8006e7e:	687b      	ldr	r3, [r7, #4]
+ 8006e80:	6d9b      	ldr	r3, [r3, #88]	; 0x58
+ 8006e82:	2b00      	cmp	r3, #0
+ 8006e84:	d05c      	beq.n	8006f40 <HAL_MDMA_IRQHandler+0x2a0>
+        {
+          hmdma->XferAbortCallback(hmdma);
+ 8006e86:	687b      	ldr	r3, [r7, #4]
+ 8006e88:	6d9b      	ldr	r3, [r3, #88]	; 0x58
+ 8006e8a:	6878      	ldr	r0, [r7, #4]
+ 8006e8c:	4798      	blx	r3
+        }
+        return;
+ 8006e8e:	e057      	b.n	8006f40 <HAL_MDMA_IRQHandler+0x2a0>
+      }
+
+      /* Clear the Channel Transfer Complete flag */
+      __HAL_MDMA_CLEAR_FLAG(hmdma, MDMA_FLAG_CTC);
+ 8006e90:	687b      	ldr	r3, [r7, #4]
+ 8006e92:	681b      	ldr	r3, [r3, #0]
+ 8006e94:	2202      	movs	r2, #2
+ 8006e96:	605a      	str	r2, [r3, #4]
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hmdma);
+ 8006e98:	687b      	ldr	r3, [r7, #4]
+ 8006e9a:	2200      	movs	r2, #0
+ 8006e9c:	f883 203c 	strb.w	r2, [r3, #60]	; 0x3c
+
+      /* Change MDMA peripheral state */
+      hmdma->State = HAL_MDMA_STATE_READY;
+ 8006ea0:	687b      	ldr	r3, [r7, #4]
+ 8006ea2:	2201      	movs	r2, #1
+ 8006ea4:	f883 203d 	strb.w	r2, [r3, #61]	; 0x3d
+
+      if(hmdma->XferCpltCallback != NULL)
+ 8006ea8:	687b      	ldr	r3, [r7, #4]
+ 8006eaa:	6c5b      	ldr	r3, [r3, #68]	; 0x44
+ 8006eac:	2b00      	cmp	r3, #0
+ 8006eae:	d003      	beq.n	8006eb8 <HAL_MDMA_IRQHandler+0x218>
+      {
+        /* Channel Transfer Complete callback */
+        hmdma->XferCpltCallback(hmdma);
+ 8006eb0:	687b      	ldr	r3, [r7, #4]
+ 8006eb2:	6c5b      	ldr	r3, [r3, #68]	; 0x44
+ 8006eb4:	6878      	ldr	r0, [r7, #4]
+ 8006eb6:	4798      	blx	r3
+      }
+    }
+  }
+
+  /* manage error case */
+  if(hmdma->ErrorCode != HAL_MDMA_ERROR_NONE)
+ 8006eb8:	687b      	ldr	r3, [r7, #4]
+ 8006eba:	6e9b      	ldr	r3, [r3, #104]	; 0x68
+ 8006ebc:	2b00      	cmp	r3, #0
+ 8006ebe:	d040      	beq.n	8006f42 <HAL_MDMA_IRQHandler+0x2a2>
+  {
+    hmdma->State = HAL_MDMA_STATE_ABORT;
+ 8006ec0:	687b      	ldr	r3, [r7, #4]
+ 8006ec2:	2204      	movs	r2, #4
+ 8006ec4:	f883 203d 	strb.w	r2, [r3, #61]	; 0x3d
+
+    /* Disable the channel */
+    __HAL_MDMA_DISABLE(hmdma);
+ 8006ec8:	687b      	ldr	r3, [r7, #4]
+ 8006eca:	681b      	ldr	r3, [r3, #0]
+ 8006ecc:	68da      	ldr	r2, [r3, #12]
+ 8006ece:	687b      	ldr	r3, [r7, #4]
+ 8006ed0:	681b      	ldr	r3, [r3, #0]
+ 8006ed2:	f022 0201 	bic.w	r2, r2, #1
+ 8006ed6:	60da      	str	r2, [r3, #12]
+
+    do
+    {
+      if (++count > timeout)
+ 8006ed8:	68bb      	ldr	r3, [r7, #8]
+ 8006eda:	3301      	adds	r3, #1
+ 8006edc:	60bb      	str	r3, [r7, #8]
+ 8006ede:	697a      	ldr	r2, [r7, #20]
+ 8006ee0:	429a      	cmp	r2, r3
+ 8006ee2:	d30d      	bcc.n	8006f00 <HAL_MDMA_IRQHandler+0x260>
+      {
+        break;
+      }
+    }
+    while((hmdma->Instance->CCR & MDMA_CCR_EN) != 0U);
+ 8006ee4:	687b      	ldr	r3, [r7, #4]
+ 8006ee6:	681b      	ldr	r3, [r3, #0]
+ 8006ee8:	68db      	ldr	r3, [r3, #12]
+ 8006eea:	f003 0301 	and.w	r3, r3, #1
+ 8006eee:	2b00      	cmp	r3, #0
+ 8006ef0:	d1f2      	bne.n	8006ed8 <HAL_MDMA_IRQHandler+0x238>
+ 8006ef2:	e006      	b.n	8006f02 <HAL_MDMA_IRQHandler+0x262>
+ 8006ef4:	24000014 	.word	0x24000014
+ 8006ef8:	1b4e81b5 	.word	0x1b4e81b5
+ 8006efc:	adffffc0 	.word	0xadffffc0
+        break;
+ 8006f00:	bf00      	nop
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hmdma);
+ 8006f02:	687b      	ldr	r3, [r7, #4]
+ 8006f04:	2200      	movs	r2, #0
+ 8006f06:	f883 203c 	strb.w	r2, [r3, #60]	; 0x3c
+
+    if((hmdma->Instance->CCR & MDMA_CCR_EN) != 0U)
+ 8006f0a:	687b      	ldr	r3, [r7, #4]
+ 8006f0c:	681b      	ldr	r3, [r3, #0]
+ 8006f0e:	68db      	ldr	r3, [r3, #12]
+ 8006f10:	f003 0301 	and.w	r3, r3, #1
+ 8006f14:	2b00      	cmp	r3, #0
+ 8006f16:	d004      	beq.n	8006f22 <HAL_MDMA_IRQHandler+0x282>
+    {
+      /* Change the MDMA state to error if MDMA disable fails */
+      hmdma->State = HAL_MDMA_STATE_ERROR;
+ 8006f18:	687b      	ldr	r3, [r7, #4]
+ 8006f1a:	2203      	movs	r2, #3
+ 8006f1c:	f883 203d 	strb.w	r2, [r3, #61]	; 0x3d
+ 8006f20:	e003      	b.n	8006f2a <HAL_MDMA_IRQHandler+0x28a>
+    }
+    else
+    {
+      /* Change the MDMA state to Ready if MDMA disable success */
+      hmdma->State = HAL_MDMA_STATE_READY;
+ 8006f22:	687b      	ldr	r3, [r7, #4]
+ 8006f24:	2201      	movs	r2, #1
+ 8006f26:	f883 203d 	strb.w	r2, [r3, #61]	; 0x3d
+    }
+
+
+    if (hmdma->XferErrorCallback != NULL)
+ 8006f2a:	687b      	ldr	r3, [r7, #4]
+ 8006f2c:	6d5b      	ldr	r3, [r3, #84]	; 0x54
+ 8006f2e:	2b00      	cmp	r3, #0
+ 8006f30:	d007      	beq.n	8006f42 <HAL_MDMA_IRQHandler+0x2a2>
+    {
+      /* Transfer error callback */
+      hmdma->XferErrorCallback(hmdma);
+ 8006f32:	687b      	ldr	r3, [r7, #4]
+ 8006f34:	6d5b      	ldr	r3, [r3, #84]	; 0x54
+ 8006f36:	6878      	ldr	r0, [r7, #4]
+ 8006f38:	4798      	blx	r3
+ 8006f3a:	e002      	b.n	8006f42 <HAL_MDMA_IRQHandler+0x2a2>
+    return; /* the  General interrupt flag for the current channel is down , nothing to do */
+ 8006f3c:	bf00      	nop
+ 8006f3e:	e000      	b.n	8006f42 <HAL_MDMA_IRQHandler+0x2a2>
+        return;
+ 8006f40:	bf00      	nop
+    }
+  }
+}
+ 8006f42:	3718      	adds	r7, #24
+ 8006f44:	46bd      	mov	sp, r7
+ 8006f46:	bd80      	pop	{r7, pc}
+
+08006f48 <MDMA_Init>:
+  * @param  hmdma:       pointer to a MDMA_HandleTypeDef structure that contains
+  *                     the configuration information for the specified MDMA Channel.
+  * @retval None
+  */
+static void MDMA_Init(MDMA_HandleTypeDef *hmdma)
+{
+ 8006f48:	b480      	push	{r7}
+ 8006f4a:	b085      	sub	sp, #20
+ 8006f4c:	af00      	add	r7, sp, #0
+ 8006f4e:	6078      	str	r0, [r7, #4]
+  uint32_t blockoffset;
+
+  /* Prepare the MDMA Channel configuration */
+  hmdma->Instance->CCR = hmdma->Init.Priority  | hmdma->Init.Endianness;
+ 8006f50:	687b      	ldr	r3, [r7, #4]
+ 8006f52:	68d9      	ldr	r1, [r3, #12]
+ 8006f54:	687b      	ldr	r3, [r7, #4]
+ 8006f56:	691a      	ldr	r2, [r3, #16]
+ 8006f58:	687b      	ldr	r3, [r7, #4]
+ 8006f5a:	681b      	ldr	r3, [r3, #0]
+ 8006f5c:	430a      	orrs	r2, r1
+ 8006f5e:	60da      	str	r2, [r3, #12]
+
+  /* Write new CTCR Register value */
+  hmdma->Instance->CTCR =  hmdma->Init.SourceInc      | hmdma->Init.DestinationInc | \
+ 8006f60:	687b      	ldr	r3, [r7, #4]
+ 8006f62:	695a      	ldr	r2, [r3, #20]
+ 8006f64:	687b      	ldr	r3, [r7, #4]
+ 8006f66:	699b      	ldr	r3, [r3, #24]
+ 8006f68:	431a      	orrs	r2, r3
+                           hmdma->Init.SourceDataSize | hmdma->Init.DestDataSize   | \
+ 8006f6a:	687b      	ldr	r3, [r7, #4]
+ 8006f6c:	69db      	ldr	r3, [r3, #28]
+  hmdma->Instance->CTCR =  hmdma->Init.SourceInc      | hmdma->Init.DestinationInc | \
+ 8006f6e:	431a      	orrs	r2, r3
+                           hmdma->Init.SourceDataSize | hmdma->Init.DestDataSize   | \
+ 8006f70:	687b      	ldr	r3, [r7, #4]
+ 8006f72:	6a1b      	ldr	r3, [r3, #32]
+ 8006f74:	431a      	orrs	r2, r3
+                           hmdma->Init.DataAlignment  | hmdma->Init.SourceBurst    | \
+ 8006f76:	687b      	ldr	r3, [r7, #4]
+ 8006f78:	6a5b      	ldr	r3, [r3, #36]	; 0x24
+                           hmdma->Init.SourceDataSize | hmdma->Init.DestDataSize   | \
+ 8006f7a:	431a      	orrs	r2, r3
+                           hmdma->Init.DataAlignment  | hmdma->Init.SourceBurst    | \
+ 8006f7c:	687b      	ldr	r3, [r7, #4]
+ 8006f7e:	6adb      	ldr	r3, [r3, #44]	; 0x2c
+ 8006f80:	431a      	orrs	r2, r3
+                           hmdma->Init.DestBurst                                   | \
+ 8006f82:	687b      	ldr	r3, [r7, #4]
+ 8006f84:	6b1b      	ldr	r3, [r3, #48]	; 0x30
+                           hmdma->Init.DataAlignment  | hmdma->Init.SourceBurst    | \
+ 8006f86:	431a      	orrs	r2, r3
+                           ((hmdma->Init.BufferTransferLength - 1U) << MDMA_CTCR_TLEN_Pos) | \
+ 8006f88:	687b      	ldr	r3, [r7, #4]
+ 8006f8a:	6a9b      	ldr	r3, [r3, #40]	; 0x28
+ 8006f8c:	3b01      	subs	r3, #1
+ 8006f8e:	049b      	lsls	r3, r3, #18
+                           hmdma->Init.DestBurst                                   | \
+ 8006f90:	ea42 0103 	orr.w	r1, r2, r3
+                           hmdma->Init.TransferTriggerMode;
+ 8006f94:	687b      	ldr	r3, [r7, #4]
+ 8006f96:	689a      	ldr	r2, [r3, #8]
+  hmdma->Instance->CTCR =  hmdma->Init.SourceInc      | hmdma->Init.DestinationInc | \
+ 8006f98:	687b      	ldr	r3, [r7, #4]
+ 8006f9a:	681b      	ldr	r3, [r3, #0]
+                           ((hmdma->Init.BufferTransferLength - 1U) << MDMA_CTCR_TLEN_Pos) | \
+ 8006f9c:	430a      	orrs	r2, r1
+  hmdma->Instance->CTCR =  hmdma->Init.SourceInc      | hmdma->Init.DestinationInc | \
+ 8006f9e:	611a      	str	r2, [r3, #16]
+
+  /* If SW request set the CTCR register to SW Request Mode */
+  if(hmdma->Init.Request == MDMA_REQUEST_SW)
+ 8006fa0:	687b      	ldr	r3, [r7, #4]
+ 8006fa2:	685b      	ldr	r3, [r3, #4]
+ 8006fa4:	f1b3 4f80 	cmp.w	r3, #1073741824	; 0x40000000
+ 8006fa8:	d107      	bne.n	8006fba <MDMA_Init+0x72>
+    -If the request is done by SW : BWM could be set to 1 or 0.
+    -If the request is done by a peripheral :
+    If mask address not set (0) => BWM must be set to 0
+    If mask address set (different than 0) => BWM could be set to 1 or 0
+    */
+    hmdma->Instance->CTCR |= (MDMA_CTCR_SWRM | MDMA_CTCR_BWM);
+ 8006faa:	687b      	ldr	r3, [r7, #4]
+ 8006fac:	681b      	ldr	r3, [r3, #0]
+ 8006fae:	691a      	ldr	r2, [r3, #16]
+ 8006fb0:	687b      	ldr	r3, [r7, #4]
+ 8006fb2:	681b      	ldr	r3, [r3, #0]
+ 8006fb4:	f042 4240 	orr.w	r2, r2, #3221225472	; 0xc0000000
+ 8006fb8:	611a      	str	r2, [r3, #16]
+  }
+
+  /* Reset CBNDTR Register */
+  hmdma->Instance->CBNDTR = 0;
+ 8006fba:	687b      	ldr	r3, [r7, #4]
+ 8006fbc:	681b      	ldr	r3, [r3, #0]
+ 8006fbe:	2200      	movs	r2, #0
+ 8006fc0:	615a      	str	r2, [r3, #20]
+
+  /* if block source address offset is negative set the Block Repeat Source address Update Mode to decrement */
+  if(hmdma->Init.SourceBlockAddressOffset < 0)
+ 8006fc2:	687b      	ldr	r3, [r7, #4]
+ 8006fc4:	6b5b      	ldr	r3, [r3, #52]	; 0x34
+ 8006fc6:	2b00      	cmp	r3, #0
+ 8006fc8:	da11      	bge.n	8006fee <MDMA_Init+0xa6>
+  {
+    hmdma->Instance->CBNDTR |= MDMA_CBNDTR_BRSUM;
+ 8006fca:	687b      	ldr	r3, [r7, #4]
+ 8006fcc:	681b      	ldr	r3, [r3, #0]
+ 8006fce:	695a      	ldr	r2, [r3, #20]
+ 8006fd0:	687b      	ldr	r3, [r7, #4]
+ 8006fd2:	681b      	ldr	r3, [r3, #0]
+ 8006fd4:	f442 2280 	orr.w	r2, r2, #262144	; 0x40000
+ 8006fd8:	615a      	str	r2, [r3, #20]
+    /* Write new CBRUR Register value : source repeat block offset */
+    blockoffset = (uint32_t)(- hmdma->Init.SourceBlockAddressOffset);
+ 8006fda:	687b      	ldr	r3, [r7, #4]
+ 8006fdc:	6b5b      	ldr	r3, [r3, #52]	; 0x34
+ 8006fde:	425b      	negs	r3, r3
+ 8006fe0:	60fb      	str	r3, [r7, #12]
+    hmdma->Instance->CBRUR = (blockoffset & 0x0000FFFFU);
+ 8006fe2:	687b      	ldr	r3, [r7, #4]
+ 8006fe4:	681b      	ldr	r3, [r3, #0]
+ 8006fe6:	68fa      	ldr	r2, [r7, #12]
+ 8006fe8:	b292      	uxth	r2, r2
+ 8006fea:	621a      	str	r2, [r3, #32]
+ 8006fec:	e006      	b.n	8006ffc <MDMA_Init+0xb4>
+  }
+  else
+  {
+    /* Write new CBRUR Register value : source repeat block offset */
+    hmdma->Instance->CBRUR = (((uint32_t)hmdma->Init.SourceBlockAddressOffset) & 0x0000FFFFU);
+ 8006fee:	687b      	ldr	r3, [r7, #4]
+ 8006ff0:	6b5b      	ldr	r3, [r3, #52]	; 0x34
+ 8006ff2:	461a      	mov	r2, r3
+ 8006ff4:	687b      	ldr	r3, [r7, #4]
+ 8006ff6:	681b      	ldr	r3, [r3, #0]
+ 8006ff8:	b292      	uxth	r2, r2
+ 8006ffa:	621a      	str	r2, [r3, #32]
+  }
+
+  /* If block destination address offset is negative set the Block Repeat destination address Update Mode to decrement */
+  if(hmdma->Init.DestBlockAddressOffset < 0)
+ 8006ffc:	687b      	ldr	r3, [r7, #4]
+ 8006ffe:	6b9b      	ldr	r3, [r3, #56]	; 0x38
+ 8007000:	2b00      	cmp	r3, #0
+ 8007002:	da15      	bge.n	8007030 <MDMA_Init+0xe8>
+  {
+    hmdma->Instance->CBNDTR |= MDMA_CBNDTR_BRDUM;
+ 8007004:	687b      	ldr	r3, [r7, #4]
+ 8007006:	681b      	ldr	r3, [r3, #0]
+ 8007008:	695a      	ldr	r2, [r3, #20]
+ 800700a:	687b      	ldr	r3, [r7, #4]
+ 800700c:	681b      	ldr	r3, [r3, #0]
+ 800700e:	f442 2200 	orr.w	r2, r2, #524288	; 0x80000
+ 8007012:	615a      	str	r2, [r3, #20]
+    /* Write new CBRUR Register value : destination repeat block offset */
+    blockoffset = (uint32_t)(- hmdma->Init.DestBlockAddressOffset);
+ 8007014:	687b      	ldr	r3, [r7, #4]
+ 8007016:	6b9b      	ldr	r3, [r3, #56]	; 0x38
+ 8007018:	425b      	negs	r3, r3
+ 800701a:	60fb      	str	r3, [r7, #12]
+    hmdma->Instance->CBRUR |= ((blockoffset & 0x0000FFFFU) << MDMA_CBRUR_DUV_Pos);
+ 800701c:	687b      	ldr	r3, [r7, #4]
+ 800701e:	681b      	ldr	r3, [r3, #0]
+ 8007020:	6a19      	ldr	r1, [r3, #32]
+ 8007022:	68fb      	ldr	r3, [r7, #12]
+ 8007024:	041a      	lsls	r2, r3, #16
+ 8007026:	687b      	ldr	r3, [r7, #4]
+ 8007028:	681b      	ldr	r3, [r3, #0]
+ 800702a:	430a      	orrs	r2, r1
+ 800702c:	621a      	str	r2, [r3, #32]
+ 800702e:	e009      	b.n	8007044 <MDMA_Init+0xfc>
+  }
+  else
+  {
+    /*write new CBRUR Register value : destination repeat block offset */
+    hmdma->Instance->CBRUR |= ((((uint32_t)hmdma->Init.DestBlockAddressOffset) & 0x0000FFFFU) << MDMA_CBRUR_DUV_Pos);
+ 8007030:	687b      	ldr	r3, [r7, #4]
+ 8007032:	681b      	ldr	r3, [r3, #0]
+ 8007034:	6a19      	ldr	r1, [r3, #32]
+ 8007036:	687b      	ldr	r3, [r7, #4]
+ 8007038:	6b9b      	ldr	r3, [r3, #56]	; 0x38
+ 800703a:	041a      	lsls	r2, r3, #16
+ 800703c:	687b      	ldr	r3, [r7, #4]
+ 800703e:	681b      	ldr	r3, [r3, #0]
+ 8007040:	430a      	orrs	r2, r1
+ 8007042:	621a      	str	r2, [r3, #32]
+  }
+
+  /* if HW request set the HW request and the requet CleraMask and ClearData MaskData, */
+  if(hmdma->Init.Request != MDMA_REQUEST_SW)
+ 8007044:	687b      	ldr	r3, [r7, #4]
+ 8007046:	685b      	ldr	r3, [r3, #4]
+ 8007048:	f1b3 4f80 	cmp.w	r3, #1073741824	; 0x40000000
+ 800704c:	d006      	beq.n	800705c <MDMA_Init+0x114>
+  {
+    /* Set the HW request in CTRB register  */
+    hmdma->Instance->CTBR = hmdma->Init.Request & MDMA_CTBR_TSEL;
+ 800704e:	687b      	ldr	r3, [r7, #4]
+ 8007050:	685a      	ldr	r2, [r3, #4]
+ 8007052:	687b      	ldr	r3, [r7, #4]
+ 8007054:	681b      	ldr	r3, [r3, #0]
+ 8007056:	b2d2      	uxtb	r2, r2
+ 8007058:	629a      	str	r2, [r3, #40]	; 0x28
+ 800705a:	e003      	b.n	8007064 <MDMA_Init+0x11c>
+  }
+  else /* SW request : reset the CTBR register */
+  {
+    hmdma->Instance->CTBR = 0;
+ 800705c:	687b      	ldr	r3, [r7, #4]
+ 800705e:	681b      	ldr	r3, [r3, #0]
+ 8007060:	2200      	movs	r2, #0
+ 8007062:	629a      	str	r2, [r3, #40]	; 0x28
+  }
+
+  /* Write Link Address Register */
+  hmdma->Instance->CLAR =  0;
+ 8007064:	687b      	ldr	r3, [r7, #4]
+ 8007066:	681b      	ldr	r3, [r3, #0]
+ 8007068:	2200      	movs	r2, #0
+ 800706a:	625a      	str	r2, [r3, #36]	; 0x24
+}
+ 800706c:	bf00      	nop
+ 800706e:	3714      	adds	r7, #20
+ 8007070:	46bd      	mov	sp, r7
+ 8007072:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8007076:	4770      	bx	lr
+
+08007078 <HAL_PWREx_ConfigSupply>:
+  *         PWR_SMPS_2V5_SUPPLIES_EXT are used only for lines that supports SMPS
+  *         regulator.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_PWREx_ConfigSupply (uint32_t SupplySource)
+{
+ 8007078:	b580      	push	{r7, lr}
+ 800707a:	b084      	sub	sp, #16
+ 800707c:	af00      	add	r7, sp, #0
+ 800707e:	6078      	str	r0, [r7, #4]
+  /* Check the parameters */
+  assert_param (IS_PWR_SUPPLY (SupplySource));
+
+  /* Check if supply source was configured */
+#if defined (PWR_FLAG_SCUEN)
+  if (__HAL_PWR_GET_FLAG (PWR_FLAG_SCUEN) == 0U)
+ 8007080:	4b19      	ldr	r3, [pc, #100]	; (80070e8 <HAL_PWREx_ConfigSupply+0x70>)
+ 8007082:	68db      	ldr	r3, [r3, #12]
+ 8007084:	f003 0304 	and.w	r3, r3, #4
+ 8007088:	2b04      	cmp	r3, #4
+ 800708a:	d00a      	beq.n	80070a2 <HAL_PWREx_ConfigSupply+0x2a>
+#else
+  if ((PWR->CR3 & (PWR_CR3_SMPSEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS)) != (PWR_CR3_SMPSEN | PWR_CR3_LDOEN))
+#endif /* defined (PWR_FLAG_SCUEN) */
+  {
+    /* Check supply configuration */
+    if ((PWR->CR3 & PWR_SUPPLY_CONFIG_MASK) != SupplySource)
+ 800708c:	4b16      	ldr	r3, [pc, #88]	; (80070e8 <HAL_PWREx_ConfigSupply+0x70>)
+ 800708e:	68db      	ldr	r3, [r3, #12]
+ 8007090:	f003 0307 	and.w	r3, r3, #7
+ 8007094:	687a      	ldr	r2, [r7, #4]
+ 8007096:	429a      	cmp	r2, r3
+ 8007098:	d001      	beq.n	800709e <HAL_PWREx_ConfigSupply+0x26>
+    {
+      /* Supply configuration update locked, can't apply a new supply config */
+      return HAL_ERROR;
+ 800709a:	2301      	movs	r3, #1
+ 800709c:	e01f      	b.n	80070de <HAL_PWREx_ConfigSupply+0x66>
+    else
+    {
+      /* Supply configuration update locked, but new supply configuration
+         matches with old supply configuration : nothing to do
+      */
+      return HAL_OK;
+ 800709e:	2300      	movs	r3, #0
+ 80070a0:	e01d      	b.n	80070de <HAL_PWREx_ConfigSupply+0x66>
+    }
+  }
+
+  /* Set the power supply configuration */
+  MODIFY_REG (PWR->CR3, PWR_SUPPLY_CONFIG_MASK, SupplySource);
+ 80070a2:	4b11      	ldr	r3, [pc, #68]	; (80070e8 <HAL_PWREx_ConfigSupply+0x70>)
+ 80070a4:	68db      	ldr	r3, [r3, #12]
+ 80070a6:	f023 0207 	bic.w	r2, r3, #7
+ 80070aa:	490f      	ldr	r1, [pc, #60]	; (80070e8 <HAL_PWREx_ConfigSupply+0x70>)
+ 80070ac:	687b      	ldr	r3, [r7, #4]
+ 80070ae:	4313      	orrs	r3, r2
+ 80070b0:	60cb      	str	r3, [r1, #12]
+
+  /* Get tick */
+  tickstart = HAL_GetTick ();
+ 80070b2:	f7fb f957 	bl	8002364 <HAL_GetTick>
+ 80070b6:	60f8      	str	r0, [r7, #12]
+
+  /* Wait till voltage level flag is set */
+  while (__HAL_PWR_GET_FLAG (PWR_FLAG_ACTVOSRDY) == 0U)
+ 80070b8:	e009      	b.n	80070ce <HAL_PWREx_ConfigSupply+0x56>
+  {
+    if ((HAL_GetTick () - tickstart) > PWR_FLAG_SETTING_DELAY)
+ 80070ba:	f7fb f953 	bl	8002364 <HAL_GetTick>
+ 80070be:	4602      	mov	r2, r0
+ 80070c0:	68fb      	ldr	r3, [r7, #12]
+ 80070c2:	1ad3      	subs	r3, r2, r3
+ 80070c4:	f5b3 7f7a 	cmp.w	r3, #1000	; 0x3e8
+ 80070c8:	d901      	bls.n	80070ce <HAL_PWREx_ConfigSupply+0x56>
+    {
+      return HAL_ERROR;
+ 80070ca:	2301      	movs	r3, #1
+ 80070cc:	e007      	b.n	80070de <HAL_PWREx_ConfigSupply+0x66>
+  while (__HAL_PWR_GET_FLAG (PWR_FLAG_ACTVOSRDY) == 0U)
+ 80070ce:	4b06      	ldr	r3, [pc, #24]	; (80070e8 <HAL_PWREx_ConfigSupply+0x70>)
+ 80070d0:	685b      	ldr	r3, [r3, #4]
+ 80070d2:	f403 5300 	and.w	r3, r3, #8192	; 0x2000
+ 80070d6:	f5b3 5f00 	cmp.w	r3, #8192	; 0x2000
+ 80070da:	d1ee      	bne.n	80070ba <HAL_PWREx_ConfigSupply+0x42>
+      }
+    }
+  }
+#endif /* defined (SMPS) */
+
+  return HAL_OK;
+ 80070dc:	2300      	movs	r3, #0
+}
+ 80070de:	4618      	mov	r0, r3
+ 80070e0:	3710      	adds	r7, #16
+ 80070e2:	46bd      	mov	sp, r7
+ 80070e4:	bd80      	pop	{r7, pc}
+ 80070e6:	bf00      	nop
+ 80070e8:	58024800 	.word	0x58024800
+
+080070ec <HAL_RCC_OscConfig>:
+  *         supported by this function. User should request a transition to HSE Off
+  *         first and then HSE On or HSE Bypass.
+  * @retval HAL status
+  */
+__weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
+{
+ 80070ec:	b580      	push	{r7, lr}
+ 80070ee:	b08c      	sub	sp, #48	; 0x30
+ 80070f0:	af00      	add	r7, sp, #0
+ 80070f2:	6078      	str	r0, [r7, #4]
+  uint32_t tickstart;
+  uint32_t temp1_pllckcfg, temp2_pllckcfg;
+
+  /* Check Null pointer */
+  if (RCC_OscInitStruct == NULL)
+ 80070f4:	687b      	ldr	r3, [r7, #4]
+ 80070f6:	2b00      	cmp	r3, #0
+ 80070f8:	d101      	bne.n	80070fe <HAL_RCC_OscConfig+0x12>
+  {
+    return HAL_ERROR;
+ 80070fa:	2301      	movs	r3, #1
+ 80070fc:	e3c8      	b.n	8007890 <HAL_RCC_OscConfig+0x7a4>
+  }
+
+  /* Check the parameters */
+  assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
+  /*------------------------------- HSE Configuration ------------------------*/
+  if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
+ 80070fe:	687b      	ldr	r3, [r7, #4]
+ 8007100:	681b      	ldr	r3, [r3, #0]
+ 8007102:	f003 0301 	and.w	r3, r3, #1
+ 8007106:	2b00      	cmp	r3, #0
+ 8007108:	f000 8087 	beq.w	800721a <HAL_RCC_OscConfig+0x12e>
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
+
+    const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();
+ 800710c:	4b88      	ldr	r3, [pc, #544]	; (8007330 <HAL_RCC_OscConfig+0x244>)
+ 800710e:	691b      	ldr	r3, [r3, #16]
+ 8007110:	f003 0338 	and.w	r3, r3, #56	; 0x38
+ 8007114:	62fb      	str	r3, [r7, #44]	; 0x2c
+    const uint32_t temp_pllckselr = RCC->PLLCKSELR;
+ 8007116:	4b86      	ldr	r3, [pc, #536]	; (8007330 <HAL_RCC_OscConfig+0x244>)
+ 8007118:	6a9b      	ldr	r3, [r3, #40]	; 0x28
+ 800711a:	62bb      	str	r3, [r7, #40]	; 0x28
+    /* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */
+    if ((temp_sysclksrc == RCC_CFGR_SWS_HSE) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_HSE)))
+ 800711c:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 800711e:	2b10      	cmp	r3, #16
+ 8007120:	d007      	beq.n	8007132 <HAL_RCC_OscConfig+0x46>
+ 8007122:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 8007124:	2b18      	cmp	r3, #24
+ 8007126:	d110      	bne.n	800714a <HAL_RCC_OscConfig+0x5e>
+ 8007128:	6abb      	ldr	r3, [r7, #40]	; 0x28
+ 800712a:	f003 0303 	and.w	r3, r3, #3
+ 800712e:	2b02      	cmp	r3, #2
+ 8007130:	d10b      	bne.n	800714a <HAL_RCC_OscConfig+0x5e>
+    {
+      if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
+ 8007132:	4b7f      	ldr	r3, [pc, #508]	; (8007330 <HAL_RCC_OscConfig+0x244>)
+ 8007134:	681b      	ldr	r3, [r3, #0]
+ 8007136:	f403 3300 	and.w	r3, r3, #131072	; 0x20000
+ 800713a:	2b00      	cmp	r3, #0
+ 800713c:	d06c      	beq.n	8007218 <HAL_RCC_OscConfig+0x12c>
+ 800713e:	687b      	ldr	r3, [r7, #4]
+ 8007140:	685b      	ldr	r3, [r3, #4]
+ 8007142:	2b00      	cmp	r3, #0
+ 8007144:	d168      	bne.n	8007218 <HAL_RCC_OscConfig+0x12c>
+      {
+        return HAL_ERROR;
+ 8007146:	2301      	movs	r3, #1
+ 8007148:	e3a2      	b.n	8007890 <HAL_RCC_OscConfig+0x7a4>
+      }
+    }
+    else
+    {
+      /* Set the new HSE configuration ---------------------------------------*/
+      __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
+ 800714a:	687b      	ldr	r3, [r7, #4]
+ 800714c:	685b      	ldr	r3, [r3, #4]
+ 800714e:	f5b3 3f80 	cmp.w	r3, #65536	; 0x10000
+ 8007152:	d106      	bne.n	8007162 <HAL_RCC_OscConfig+0x76>
+ 8007154:	4b76      	ldr	r3, [pc, #472]	; (8007330 <HAL_RCC_OscConfig+0x244>)
+ 8007156:	681b      	ldr	r3, [r3, #0]
+ 8007158:	4a75      	ldr	r2, [pc, #468]	; (8007330 <HAL_RCC_OscConfig+0x244>)
+ 800715a:	f443 3380 	orr.w	r3, r3, #65536	; 0x10000
+ 800715e:	6013      	str	r3, [r2, #0]
+ 8007160:	e02e      	b.n	80071c0 <HAL_RCC_OscConfig+0xd4>
+ 8007162:	687b      	ldr	r3, [r7, #4]
+ 8007164:	685b      	ldr	r3, [r3, #4]
+ 8007166:	2b00      	cmp	r3, #0
+ 8007168:	d10c      	bne.n	8007184 <HAL_RCC_OscConfig+0x98>
+ 800716a:	4b71      	ldr	r3, [pc, #452]	; (8007330 <HAL_RCC_OscConfig+0x244>)
+ 800716c:	681b      	ldr	r3, [r3, #0]
+ 800716e:	4a70      	ldr	r2, [pc, #448]	; (8007330 <HAL_RCC_OscConfig+0x244>)
+ 8007170:	f423 3380 	bic.w	r3, r3, #65536	; 0x10000
+ 8007174:	6013      	str	r3, [r2, #0]
+ 8007176:	4b6e      	ldr	r3, [pc, #440]	; (8007330 <HAL_RCC_OscConfig+0x244>)
+ 8007178:	681b      	ldr	r3, [r3, #0]
+ 800717a:	4a6d      	ldr	r2, [pc, #436]	; (8007330 <HAL_RCC_OscConfig+0x244>)
+ 800717c:	f423 2380 	bic.w	r3, r3, #262144	; 0x40000
+ 8007180:	6013      	str	r3, [r2, #0]
+ 8007182:	e01d      	b.n	80071c0 <HAL_RCC_OscConfig+0xd4>
+ 8007184:	687b      	ldr	r3, [r7, #4]
+ 8007186:	685b      	ldr	r3, [r3, #4]
+ 8007188:	f5b3 2fa0 	cmp.w	r3, #327680	; 0x50000
+ 800718c:	d10c      	bne.n	80071a8 <HAL_RCC_OscConfig+0xbc>
+ 800718e:	4b68      	ldr	r3, [pc, #416]	; (8007330 <HAL_RCC_OscConfig+0x244>)
+ 8007190:	681b      	ldr	r3, [r3, #0]
+ 8007192:	4a67      	ldr	r2, [pc, #412]	; (8007330 <HAL_RCC_OscConfig+0x244>)
+ 8007194:	f443 2380 	orr.w	r3, r3, #262144	; 0x40000
+ 8007198:	6013      	str	r3, [r2, #0]
+ 800719a:	4b65      	ldr	r3, [pc, #404]	; (8007330 <HAL_RCC_OscConfig+0x244>)
+ 800719c:	681b      	ldr	r3, [r3, #0]
+ 800719e:	4a64      	ldr	r2, [pc, #400]	; (8007330 <HAL_RCC_OscConfig+0x244>)
+ 80071a0:	f443 3380 	orr.w	r3, r3, #65536	; 0x10000
+ 80071a4:	6013      	str	r3, [r2, #0]
+ 80071a6:	e00b      	b.n	80071c0 <HAL_RCC_OscConfig+0xd4>
+ 80071a8:	4b61      	ldr	r3, [pc, #388]	; (8007330 <HAL_RCC_OscConfig+0x244>)
+ 80071aa:	681b      	ldr	r3, [r3, #0]
+ 80071ac:	4a60      	ldr	r2, [pc, #384]	; (8007330 <HAL_RCC_OscConfig+0x244>)
+ 80071ae:	f423 3380 	bic.w	r3, r3, #65536	; 0x10000
+ 80071b2:	6013      	str	r3, [r2, #0]
+ 80071b4:	4b5e      	ldr	r3, [pc, #376]	; (8007330 <HAL_RCC_OscConfig+0x244>)
+ 80071b6:	681b      	ldr	r3, [r3, #0]
+ 80071b8:	4a5d      	ldr	r2, [pc, #372]	; (8007330 <HAL_RCC_OscConfig+0x244>)
+ 80071ba:	f423 2380 	bic.w	r3, r3, #262144	; 0x40000
+ 80071be:	6013      	str	r3, [r2, #0]
+
+      /* Check the HSE State */
+      if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
+ 80071c0:	687b      	ldr	r3, [r7, #4]
+ 80071c2:	685b      	ldr	r3, [r3, #4]
+ 80071c4:	2b00      	cmp	r3, #0
+ 80071c6:	d013      	beq.n	80071f0 <HAL_RCC_OscConfig+0x104>
+      {
+        /* Get Start Tick*/
+        tickstart = HAL_GetTick();
+ 80071c8:	f7fb f8cc 	bl	8002364 <HAL_GetTick>
+ 80071cc:	6278      	str	r0, [r7, #36]	; 0x24
+
+        /* Wait till HSE is ready */
+        while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U)
+ 80071ce:	e008      	b.n	80071e2 <HAL_RCC_OscConfig+0xf6>
+        {
+          if ((uint32_t)(HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
+ 80071d0:	f7fb f8c8 	bl	8002364 <HAL_GetTick>
+ 80071d4:	4602      	mov	r2, r0
+ 80071d6:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 80071d8:	1ad3      	subs	r3, r2, r3
+ 80071da:	2b64      	cmp	r3, #100	; 0x64
+ 80071dc:	d901      	bls.n	80071e2 <HAL_RCC_OscConfig+0xf6>
+          {
+            return HAL_TIMEOUT;
+ 80071de:	2303      	movs	r3, #3
+ 80071e0:	e356      	b.n	8007890 <HAL_RCC_OscConfig+0x7a4>
+        while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U)
+ 80071e2:	4b53      	ldr	r3, [pc, #332]	; (8007330 <HAL_RCC_OscConfig+0x244>)
+ 80071e4:	681b      	ldr	r3, [r3, #0]
+ 80071e6:	f403 3300 	and.w	r3, r3, #131072	; 0x20000
+ 80071ea:	2b00      	cmp	r3, #0
+ 80071ec:	d0f0      	beq.n	80071d0 <HAL_RCC_OscConfig+0xe4>
+ 80071ee:	e014      	b.n	800721a <HAL_RCC_OscConfig+0x12e>
+        }
+      }
+      else
+      {
+        /* Get Start Tick*/
+        tickstart = HAL_GetTick();
+ 80071f0:	f7fb f8b8 	bl	8002364 <HAL_GetTick>
+ 80071f4:	6278      	str	r0, [r7, #36]	; 0x24
+
+        /* Wait till HSE is disabled */
+        while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U)
+ 80071f6:	e008      	b.n	800720a <HAL_RCC_OscConfig+0x11e>
+        {
+          if ((uint32_t)(HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
+ 80071f8:	f7fb f8b4 	bl	8002364 <HAL_GetTick>
+ 80071fc:	4602      	mov	r2, r0
+ 80071fe:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 8007200:	1ad3      	subs	r3, r2, r3
+ 8007202:	2b64      	cmp	r3, #100	; 0x64
+ 8007204:	d901      	bls.n	800720a <HAL_RCC_OscConfig+0x11e>
+          {
+            return HAL_TIMEOUT;
+ 8007206:	2303      	movs	r3, #3
+ 8007208:	e342      	b.n	8007890 <HAL_RCC_OscConfig+0x7a4>
+        while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U)
+ 800720a:	4b49      	ldr	r3, [pc, #292]	; (8007330 <HAL_RCC_OscConfig+0x244>)
+ 800720c:	681b      	ldr	r3, [r3, #0]
+ 800720e:	f403 3300 	and.w	r3, r3, #131072	; 0x20000
+ 8007212:	2b00      	cmp	r3, #0
+ 8007214:	d1f0      	bne.n	80071f8 <HAL_RCC_OscConfig+0x10c>
+ 8007216:	e000      	b.n	800721a <HAL_RCC_OscConfig+0x12e>
+      if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
+ 8007218:	bf00      	nop
+        }
+      }
+    }
+  }
+  /*----------------------------- HSI Configuration --------------------------*/
+  if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
+ 800721a:	687b      	ldr	r3, [r7, #4]
+ 800721c:	681b      	ldr	r3, [r3, #0]
+ 800721e:	f003 0302 	and.w	r3, r3, #2
+ 8007222:	2b00      	cmp	r3, #0
+ 8007224:	f000 808c 	beq.w	8007340 <HAL_RCC_OscConfig+0x254>
+    /* Check the parameters */
+    assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
+    assert_param(IS_RCC_HSICALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
+
+    /* When the HSI is used as system clock it will not be disabled */
+    const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();
+ 8007228:	4b41      	ldr	r3, [pc, #260]	; (8007330 <HAL_RCC_OscConfig+0x244>)
+ 800722a:	691b      	ldr	r3, [r3, #16]
+ 800722c:	f003 0338 	and.w	r3, r3, #56	; 0x38
+ 8007230:	623b      	str	r3, [r7, #32]
+    const uint32_t temp_pllckselr = RCC->PLLCKSELR;
+ 8007232:	4b3f      	ldr	r3, [pc, #252]	; (8007330 <HAL_RCC_OscConfig+0x244>)
+ 8007234:	6a9b      	ldr	r3, [r3, #40]	; 0x28
+ 8007236:	61fb      	str	r3, [r7, #28]
+    if ((temp_sysclksrc == RCC_CFGR_SWS_HSI) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_HSI)))
+ 8007238:	6a3b      	ldr	r3, [r7, #32]
+ 800723a:	2b00      	cmp	r3, #0
+ 800723c:	d007      	beq.n	800724e <HAL_RCC_OscConfig+0x162>
+ 800723e:	6a3b      	ldr	r3, [r7, #32]
+ 8007240:	2b18      	cmp	r3, #24
+ 8007242:	d137      	bne.n	80072b4 <HAL_RCC_OscConfig+0x1c8>
+ 8007244:	69fb      	ldr	r3, [r7, #28]
+ 8007246:	f003 0303 	and.w	r3, r3, #3
+ 800724a:	2b00      	cmp	r3, #0
+ 800724c:	d132      	bne.n	80072b4 <HAL_RCC_OscConfig+0x1c8>
+    {
+      /* When HSI is used as system clock it will not be disabled */
+      if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF))
+ 800724e:	4b38      	ldr	r3, [pc, #224]	; (8007330 <HAL_RCC_OscConfig+0x244>)
+ 8007250:	681b      	ldr	r3, [r3, #0]
+ 8007252:	f003 0304 	and.w	r3, r3, #4
+ 8007256:	2b00      	cmp	r3, #0
+ 8007258:	d005      	beq.n	8007266 <HAL_RCC_OscConfig+0x17a>
+ 800725a:	687b      	ldr	r3, [r7, #4]
+ 800725c:	68db      	ldr	r3, [r3, #12]
+ 800725e:	2b00      	cmp	r3, #0
+ 8007260:	d101      	bne.n	8007266 <HAL_RCC_OscConfig+0x17a>
+      {
+        return HAL_ERROR;
+ 8007262:	2301      	movs	r3, #1
+ 8007264:	e314      	b.n	8007890 <HAL_RCC_OscConfig+0x7a4>
+      }
+      /* Otherwise, only HSI division and calibration are allowed */
+      else
+      {
+        /* Enable the Internal High Speed oscillator (HSI, HSIDIV2, HSIDIV4, or HSIDIV8) */
+        __HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIState);
+ 8007266:	4b32      	ldr	r3, [pc, #200]	; (8007330 <HAL_RCC_OscConfig+0x244>)
+ 8007268:	681b      	ldr	r3, [r3, #0]
+ 800726a:	f023 0219 	bic.w	r2, r3, #25
+ 800726e:	687b      	ldr	r3, [r7, #4]
+ 8007270:	68db      	ldr	r3, [r3, #12]
+ 8007272:	492f      	ldr	r1, [pc, #188]	; (8007330 <HAL_RCC_OscConfig+0x244>)
+ 8007274:	4313      	orrs	r3, r2
+ 8007276:	600b      	str	r3, [r1, #0]
+
+        /* Get Start Tick*/
+        tickstart = HAL_GetTick();
+ 8007278:	f7fb f874 	bl	8002364 <HAL_GetTick>
+ 800727c:	6278      	str	r0, [r7, #36]	; 0x24
+
+        /* Wait till HSI is ready */
+        while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U)
+ 800727e:	e008      	b.n	8007292 <HAL_RCC_OscConfig+0x1a6>
+        {
+          if ((uint32_t)(HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
+ 8007280:	f7fb f870 	bl	8002364 <HAL_GetTick>
+ 8007284:	4602      	mov	r2, r0
+ 8007286:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 8007288:	1ad3      	subs	r3, r2, r3
+ 800728a:	2b02      	cmp	r3, #2
+ 800728c:	d901      	bls.n	8007292 <HAL_RCC_OscConfig+0x1a6>
+          {
+            return HAL_TIMEOUT;
+ 800728e:	2303      	movs	r3, #3
+ 8007290:	e2fe      	b.n	8007890 <HAL_RCC_OscConfig+0x7a4>
+        while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U)
+ 8007292:	4b27      	ldr	r3, [pc, #156]	; (8007330 <HAL_RCC_OscConfig+0x244>)
+ 8007294:	681b      	ldr	r3, [r3, #0]
+ 8007296:	f003 0304 	and.w	r3, r3, #4
+ 800729a:	2b00      	cmp	r3, #0
+ 800729c:	d0f0      	beq.n	8007280 <HAL_RCC_OscConfig+0x194>
+          }
+        }
+        /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
+        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
+ 800729e:	4b24      	ldr	r3, [pc, #144]	; (8007330 <HAL_RCC_OscConfig+0x244>)
+ 80072a0:	685b      	ldr	r3, [r3, #4]
+ 80072a2:	f023 42fe 	bic.w	r2, r3, #2130706432	; 0x7f000000
+ 80072a6:	687b      	ldr	r3, [r7, #4]
+ 80072a8:	691b      	ldr	r3, [r3, #16]
+ 80072aa:	061b      	lsls	r3, r3, #24
+ 80072ac:	4920      	ldr	r1, [pc, #128]	; (8007330 <HAL_RCC_OscConfig+0x244>)
+ 80072ae:	4313      	orrs	r3, r2
+ 80072b0:	604b      	str	r3, [r1, #4]
+      if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF))
+ 80072b2:	e045      	b.n	8007340 <HAL_RCC_OscConfig+0x254>
+    }
+
+    else
+    {
+      /* Check the HSI State */
+      if ((RCC_OscInitStruct->HSIState) != RCC_HSI_OFF)
+ 80072b4:	687b      	ldr	r3, [r7, #4]
+ 80072b6:	68db      	ldr	r3, [r3, #12]
+ 80072b8:	2b00      	cmp	r3, #0
+ 80072ba:	d026      	beq.n	800730a <HAL_RCC_OscConfig+0x21e>
+      {
+        /* Enable the Internal High Speed oscillator (HSI, HSIDIV2,HSIDIV4, or HSIDIV8) */
+        __HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIState);
+ 80072bc:	4b1c      	ldr	r3, [pc, #112]	; (8007330 <HAL_RCC_OscConfig+0x244>)
+ 80072be:	681b      	ldr	r3, [r3, #0]
+ 80072c0:	f023 0219 	bic.w	r2, r3, #25
+ 80072c4:	687b      	ldr	r3, [r7, #4]
+ 80072c6:	68db      	ldr	r3, [r3, #12]
+ 80072c8:	4919      	ldr	r1, [pc, #100]	; (8007330 <HAL_RCC_OscConfig+0x244>)
+ 80072ca:	4313      	orrs	r3, r2
+ 80072cc:	600b      	str	r3, [r1, #0]
+
+        /* Get Start Tick*/
+        tickstart = HAL_GetTick();
+ 80072ce:	f7fb f849 	bl	8002364 <HAL_GetTick>
+ 80072d2:	6278      	str	r0, [r7, #36]	; 0x24
+
+        /* Wait till HSI is ready */
+        while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U)
+ 80072d4:	e008      	b.n	80072e8 <HAL_RCC_OscConfig+0x1fc>
+        {
+          if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
+ 80072d6:	f7fb f845 	bl	8002364 <HAL_GetTick>
+ 80072da:	4602      	mov	r2, r0
+ 80072dc:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 80072de:	1ad3      	subs	r3, r2, r3
+ 80072e0:	2b02      	cmp	r3, #2
+ 80072e2:	d901      	bls.n	80072e8 <HAL_RCC_OscConfig+0x1fc>
+          {
+            return HAL_TIMEOUT;
+ 80072e4:	2303      	movs	r3, #3
+ 80072e6:	e2d3      	b.n	8007890 <HAL_RCC_OscConfig+0x7a4>
+        while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U)
+ 80072e8:	4b11      	ldr	r3, [pc, #68]	; (8007330 <HAL_RCC_OscConfig+0x244>)
+ 80072ea:	681b      	ldr	r3, [r3, #0]
+ 80072ec:	f003 0304 	and.w	r3, r3, #4
+ 80072f0:	2b00      	cmp	r3, #0
+ 80072f2:	d0f0      	beq.n	80072d6 <HAL_RCC_OscConfig+0x1ea>
+          }
+        }
+
+        /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
+        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
+ 80072f4:	4b0e      	ldr	r3, [pc, #56]	; (8007330 <HAL_RCC_OscConfig+0x244>)
+ 80072f6:	685b      	ldr	r3, [r3, #4]
+ 80072f8:	f023 42fe 	bic.w	r2, r3, #2130706432	; 0x7f000000
+ 80072fc:	687b      	ldr	r3, [r7, #4]
+ 80072fe:	691b      	ldr	r3, [r3, #16]
+ 8007300:	061b      	lsls	r3, r3, #24
+ 8007302:	490b      	ldr	r1, [pc, #44]	; (8007330 <HAL_RCC_OscConfig+0x244>)
+ 8007304:	4313      	orrs	r3, r2
+ 8007306:	604b      	str	r3, [r1, #4]
+ 8007308:	e01a      	b.n	8007340 <HAL_RCC_OscConfig+0x254>
+      }
+      else
+      {
+        /* Disable the Internal High Speed oscillator (HSI). */
+        __HAL_RCC_HSI_DISABLE();
+ 800730a:	4b09      	ldr	r3, [pc, #36]	; (8007330 <HAL_RCC_OscConfig+0x244>)
+ 800730c:	681b      	ldr	r3, [r3, #0]
+ 800730e:	4a08      	ldr	r2, [pc, #32]	; (8007330 <HAL_RCC_OscConfig+0x244>)
+ 8007310:	f023 0301 	bic.w	r3, r3, #1
+ 8007314:	6013      	str	r3, [r2, #0]
+
+        /* Get Start Tick*/
+        tickstart = HAL_GetTick();
+ 8007316:	f7fb f825 	bl	8002364 <HAL_GetTick>
+ 800731a:	6278      	str	r0, [r7, #36]	; 0x24
+
+        /* Wait till HSI is disabled */
+        while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U)
+ 800731c:	e00a      	b.n	8007334 <HAL_RCC_OscConfig+0x248>
+        {
+          if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
+ 800731e:	f7fb f821 	bl	8002364 <HAL_GetTick>
+ 8007322:	4602      	mov	r2, r0
+ 8007324:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 8007326:	1ad3      	subs	r3, r2, r3
+ 8007328:	2b02      	cmp	r3, #2
+ 800732a:	d903      	bls.n	8007334 <HAL_RCC_OscConfig+0x248>
+          {
+            return HAL_TIMEOUT;
+ 800732c:	2303      	movs	r3, #3
+ 800732e:	e2af      	b.n	8007890 <HAL_RCC_OscConfig+0x7a4>
+ 8007330:	58024400 	.word	0x58024400
+        while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U)
+ 8007334:	4b96      	ldr	r3, [pc, #600]	; (8007590 <HAL_RCC_OscConfig+0x4a4>)
+ 8007336:	681b      	ldr	r3, [r3, #0]
+ 8007338:	f003 0304 	and.w	r3, r3, #4
+ 800733c:	2b00      	cmp	r3, #0
+ 800733e:	d1ee      	bne.n	800731e <HAL_RCC_OscConfig+0x232>
+        }
+      }
+    }
+  }
+  /*----------------------------- CSI Configuration --------------------------*/
+  if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_CSI) == RCC_OSCILLATORTYPE_CSI)
+ 8007340:	687b      	ldr	r3, [r7, #4]
+ 8007342:	681b      	ldr	r3, [r3, #0]
+ 8007344:	f003 0310 	and.w	r3, r3, #16
+ 8007348:	2b00      	cmp	r3, #0
+ 800734a:	d06a      	beq.n	8007422 <HAL_RCC_OscConfig+0x336>
+    /* Check the parameters */
+    assert_param(IS_RCC_CSI(RCC_OscInitStruct->CSIState));
+    assert_param(IS_RCC_CSICALIBRATION_VALUE(RCC_OscInitStruct->CSICalibrationValue));
+
+    /* When the CSI is used as system clock it will not disabled */
+    const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();
+ 800734c:	4b90      	ldr	r3, [pc, #576]	; (8007590 <HAL_RCC_OscConfig+0x4a4>)
+ 800734e:	691b      	ldr	r3, [r3, #16]
+ 8007350:	f003 0338 	and.w	r3, r3, #56	; 0x38
+ 8007354:	61bb      	str	r3, [r7, #24]
+    const uint32_t temp_pllckselr = RCC->PLLCKSELR;
+ 8007356:	4b8e      	ldr	r3, [pc, #568]	; (8007590 <HAL_RCC_OscConfig+0x4a4>)
+ 8007358:	6a9b      	ldr	r3, [r3, #40]	; 0x28
+ 800735a:	617b      	str	r3, [r7, #20]
+    if ((temp_sysclksrc == RCC_CFGR_SWS_CSI) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_CSI)))
+ 800735c:	69bb      	ldr	r3, [r7, #24]
+ 800735e:	2b08      	cmp	r3, #8
+ 8007360:	d007      	beq.n	8007372 <HAL_RCC_OscConfig+0x286>
+ 8007362:	69bb      	ldr	r3, [r7, #24]
+ 8007364:	2b18      	cmp	r3, #24
+ 8007366:	d11b      	bne.n	80073a0 <HAL_RCC_OscConfig+0x2b4>
+ 8007368:	697b      	ldr	r3, [r7, #20]
+ 800736a:	f003 0303 	and.w	r3, r3, #3
+ 800736e:	2b01      	cmp	r3, #1
+ 8007370:	d116      	bne.n	80073a0 <HAL_RCC_OscConfig+0x2b4>
+    {
+      /* When CSI is used as system clock it will not disabled */
+      if ((__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) && (RCC_OscInitStruct->CSIState != RCC_CSI_ON))
+ 8007372:	4b87      	ldr	r3, [pc, #540]	; (8007590 <HAL_RCC_OscConfig+0x4a4>)
+ 8007374:	681b      	ldr	r3, [r3, #0]
+ 8007376:	f403 7380 	and.w	r3, r3, #256	; 0x100
+ 800737a:	2b00      	cmp	r3, #0
+ 800737c:	d005      	beq.n	800738a <HAL_RCC_OscConfig+0x29e>
+ 800737e:	687b      	ldr	r3, [r7, #4]
+ 8007380:	69db      	ldr	r3, [r3, #28]
+ 8007382:	2b80      	cmp	r3, #128	; 0x80
+ 8007384:	d001      	beq.n	800738a <HAL_RCC_OscConfig+0x29e>
+      {
+        return HAL_ERROR;
+ 8007386:	2301      	movs	r3, #1
+ 8007388:	e282      	b.n	8007890 <HAL_RCC_OscConfig+0x7a4>
+      }
+      /* Otherwise, just the calibration is allowed */
+      else
+      {
+        /* Adjusts the Internal High Speed oscillator (CSI) calibration value.*/
+        __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->CSICalibrationValue);
+ 800738a:	4b81      	ldr	r3, [pc, #516]	; (8007590 <HAL_RCC_OscConfig+0x4a4>)
+ 800738c:	68db      	ldr	r3, [r3, #12]
+ 800738e:	f023 527c 	bic.w	r2, r3, #1056964608	; 0x3f000000
+ 8007392:	687b      	ldr	r3, [r7, #4]
+ 8007394:	6a1b      	ldr	r3, [r3, #32]
+ 8007396:	061b      	lsls	r3, r3, #24
+ 8007398:	497d      	ldr	r1, [pc, #500]	; (8007590 <HAL_RCC_OscConfig+0x4a4>)
+ 800739a:	4313      	orrs	r3, r2
+ 800739c:	60cb      	str	r3, [r1, #12]
+      if ((__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) && (RCC_OscInitStruct->CSIState != RCC_CSI_ON))
+ 800739e:	e040      	b.n	8007422 <HAL_RCC_OscConfig+0x336>
+      }
+    }
+    else
+    {
+      /* Check the CSI State */
+      if ((RCC_OscInitStruct->CSIState) != RCC_CSI_OFF)
+ 80073a0:	687b      	ldr	r3, [r7, #4]
+ 80073a2:	69db      	ldr	r3, [r3, #28]
+ 80073a4:	2b00      	cmp	r3, #0
+ 80073a6:	d023      	beq.n	80073f0 <HAL_RCC_OscConfig+0x304>
+      {
+        /* Enable the Internal High Speed oscillator (CSI). */
+        __HAL_RCC_CSI_ENABLE();
+ 80073a8:	4b79      	ldr	r3, [pc, #484]	; (8007590 <HAL_RCC_OscConfig+0x4a4>)
+ 80073aa:	681b      	ldr	r3, [r3, #0]
+ 80073ac:	4a78      	ldr	r2, [pc, #480]	; (8007590 <HAL_RCC_OscConfig+0x4a4>)
+ 80073ae:	f043 0380 	orr.w	r3, r3, #128	; 0x80
+ 80073b2:	6013      	str	r3, [r2, #0]
+
+        /* Get Start Tick*/
+        tickstart = HAL_GetTick();
+ 80073b4:	f7fa ffd6 	bl	8002364 <HAL_GetTick>
+ 80073b8:	6278      	str	r0, [r7, #36]	; 0x24
+
+        /* Wait till CSI is ready */
+        while (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) == 0U)
+ 80073ba:	e008      	b.n	80073ce <HAL_RCC_OscConfig+0x2e2>
+        {
+          if ((HAL_GetTick() - tickstart) > CSI_TIMEOUT_VALUE)
+ 80073bc:	f7fa ffd2 	bl	8002364 <HAL_GetTick>
+ 80073c0:	4602      	mov	r2, r0
+ 80073c2:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 80073c4:	1ad3      	subs	r3, r2, r3
+ 80073c6:	2b02      	cmp	r3, #2
+ 80073c8:	d901      	bls.n	80073ce <HAL_RCC_OscConfig+0x2e2>
+          {
+            return HAL_TIMEOUT;
+ 80073ca:	2303      	movs	r3, #3
+ 80073cc:	e260      	b.n	8007890 <HAL_RCC_OscConfig+0x7a4>
+        while (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) == 0U)
+ 80073ce:	4b70      	ldr	r3, [pc, #448]	; (8007590 <HAL_RCC_OscConfig+0x4a4>)
+ 80073d0:	681b      	ldr	r3, [r3, #0]
+ 80073d2:	f403 7380 	and.w	r3, r3, #256	; 0x100
+ 80073d6:	2b00      	cmp	r3, #0
+ 80073d8:	d0f0      	beq.n	80073bc <HAL_RCC_OscConfig+0x2d0>
+          }
+        }
+
+        /* Adjusts the Internal High Speed oscillator (CSI) calibration value.*/
+        __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->CSICalibrationValue);
+ 80073da:	4b6d      	ldr	r3, [pc, #436]	; (8007590 <HAL_RCC_OscConfig+0x4a4>)
+ 80073dc:	68db      	ldr	r3, [r3, #12]
+ 80073de:	f023 527c 	bic.w	r2, r3, #1056964608	; 0x3f000000
+ 80073e2:	687b      	ldr	r3, [r7, #4]
+ 80073e4:	6a1b      	ldr	r3, [r3, #32]
+ 80073e6:	061b      	lsls	r3, r3, #24
+ 80073e8:	4969      	ldr	r1, [pc, #420]	; (8007590 <HAL_RCC_OscConfig+0x4a4>)
+ 80073ea:	4313      	orrs	r3, r2
+ 80073ec:	60cb      	str	r3, [r1, #12]
+ 80073ee:	e018      	b.n	8007422 <HAL_RCC_OscConfig+0x336>
+      }
+      else
+      {
+        /* Disable the Internal High Speed oscillator (CSI). */
+        __HAL_RCC_CSI_DISABLE();
+ 80073f0:	4b67      	ldr	r3, [pc, #412]	; (8007590 <HAL_RCC_OscConfig+0x4a4>)
+ 80073f2:	681b      	ldr	r3, [r3, #0]
+ 80073f4:	4a66      	ldr	r2, [pc, #408]	; (8007590 <HAL_RCC_OscConfig+0x4a4>)
+ 80073f6:	f023 0380 	bic.w	r3, r3, #128	; 0x80
+ 80073fa:	6013      	str	r3, [r2, #0]
+
+        /* Get Start Tick*/
+        tickstart = HAL_GetTick();
+ 80073fc:	f7fa ffb2 	bl	8002364 <HAL_GetTick>
+ 8007400:	6278      	str	r0, [r7, #36]	; 0x24
+
+        /* Wait till CSI is disabled */
+        while (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U)
+ 8007402:	e008      	b.n	8007416 <HAL_RCC_OscConfig+0x32a>
+        {
+          if ((HAL_GetTick() - tickstart) > CSI_TIMEOUT_VALUE)
+ 8007404:	f7fa ffae 	bl	8002364 <HAL_GetTick>
+ 8007408:	4602      	mov	r2, r0
+ 800740a:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 800740c:	1ad3      	subs	r3, r2, r3
+ 800740e:	2b02      	cmp	r3, #2
+ 8007410:	d901      	bls.n	8007416 <HAL_RCC_OscConfig+0x32a>
+          {
+            return HAL_TIMEOUT;
+ 8007412:	2303      	movs	r3, #3
+ 8007414:	e23c      	b.n	8007890 <HAL_RCC_OscConfig+0x7a4>
+        while (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U)
+ 8007416:	4b5e      	ldr	r3, [pc, #376]	; (8007590 <HAL_RCC_OscConfig+0x4a4>)
+ 8007418:	681b      	ldr	r3, [r3, #0]
+ 800741a:	f403 7380 	and.w	r3, r3, #256	; 0x100
+ 800741e:	2b00      	cmp	r3, #0
+ 8007420:	d1f0      	bne.n	8007404 <HAL_RCC_OscConfig+0x318>
+        }
+      }
+    }
+  }
+  /*------------------------------ LSI Configuration -------------------------*/
+  if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
+ 8007422:	687b      	ldr	r3, [r7, #4]
+ 8007424:	681b      	ldr	r3, [r3, #0]
+ 8007426:	f003 0308 	and.w	r3, r3, #8
+ 800742a:	2b00      	cmp	r3, #0
+ 800742c:	d036      	beq.n	800749c <HAL_RCC_OscConfig+0x3b0>
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
+
+    /* Check the LSI State */
+    if ((RCC_OscInitStruct->LSIState) != RCC_LSI_OFF)
+ 800742e:	687b      	ldr	r3, [r7, #4]
+ 8007430:	695b      	ldr	r3, [r3, #20]
+ 8007432:	2b00      	cmp	r3, #0
+ 8007434:	d019      	beq.n	800746a <HAL_RCC_OscConfig+0x37e>
+    {
+      /* Enable the Internal Low Speed oscillator (LSI). */
+      __HAL_RCC_LSI_ENABLE();
+ 8007436:	4b56      	ldr	r3, [pc, #344]	; (8007590 <HAL_RCC_OscConfig+0x4a4>)
+ 8007438:	6f5b      	ldr	r3, [r3, #116]	; 0x74
+ 800743a:	4a55      	ldr	r2, [pc, #340]	; (8007590 <HAL_RCC_OscConfig+0x4a4>)
+ 800743c:	f043 0301 	orr.w	r3, r3, #1
+ 8007440:	6753      	str	r3, [r2, #116]	; 0x74
+
+      /* Get Start Tick*/
+      tickstart = HAL_GetTick();
+ 8007442:	f7fa ff8f 	bl	8002364 <HAL_GetTick>
+ 8007446:	6278      	str	r0, [r7, #36]	; 0x24
+
+      /* Wait till LSI is ready */
+      while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == 0U)
+ 8007448:	e008      	b.n	800745c <HAL_RCC_OscConfig+0x370>
+      {
+        if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
+ 800744a:	f7fa ff8b 	bl	8002364 <HAL_GetTick>
+ 800744e:	4602      	mov	r2, r0
+ 8007450:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 8007452:	1ad3      	subs	r3, r2, r3
+ 8007454:	2b02      	cmp	r3, #2
+ 8007456:	d901      	bls.n	800745c <HAL_RCC_OscConfig+0x370>
+        {
+          return HAL_TIMEOUT;
+ 8007458:	2303      	movs	r3, #3
+ 800745a:	e219      	b.n	8007890 <HAL_RCC_OscConfig+0x7a4>
+      while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == 0U)
+ 800745c:	4b4c      	ldr	r3, [pc, #304]	; (8007590 <HAL_RCC_OscConfig+0x4a4>)
+ 800745e:	6f5b      	ldr	r3, [r3, #116]	; 0x74
+ 8007460:	f003 0302 	and.w	r3, r3, #2
+ 8007464:	2b00      	cmp	r3, #0
+ 8007466:	d0f0      	beq.n	800744a <HAL_RCC_OscConfig+0x35e>
+ 8007468:	e018      	b.n	800749c <HAL_RCC_OscConfig+0x3b0>
+      }
+    }
+    else
+    {
+      /* Disable the Internal Low Speed oscillator (LSI). */
+      __HAL_RCC_LSI_DISABLE();
+ 800746a:	4b49      	ldr	r3, [pc, #292]	; (8007590 <HAL_RCC_OscConfig+0x4a4>)
+ 800746c:	6f5b      	ldr	r3, [r3, #116]	; 0x74
+ 800746e:	4a48      	ldr	r2, [pc, #288]	; (8007590 <HAL_RCC_OscConfig+0x4a4>)
+ 8007470:	f023 0301 	bic.w	r3, r3, #1
+ 8007474:	6753      	str	r3, [r2, #116]	; 0x74
+
+      /* Get Start Tick*/
+      tickstart = HAL_GetTick();
+ 8007476:	f7fa ff75 	bl	8002364 <HAL_GetTick>
+ 800747a:	6278      	str	r0, [r7, #36]	; 0x24
+
+      /* Wait till LSI is ready */
+      while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != 0U)
+ 800747c:	e008      	b.n	8007490 <HAL_RCC_OscConfig+0x3a4>
+      {
+        if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
+ 800747e:	f7fa ff71 	bl	8002364 <HAL_GetTick>
+ 8007482:	4602      	mov	r2, r0
+ 8007484:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 8007486:	1ad3      	subs	r3, r2, r3
+ 8007488:	2b02      	cmp	r3, #2
+ 800748a:	d901      	bls.n	8007490 <HAL_RCC_OscConfig+0x3a4>
+        {
+          return HAL_TIMEOUT;
+ 800748c:	2303      	movs	r3, #3
+ 800748e:	e1ff      	b.n	8007890 <HAL_RCC_OscConfig+0x7a4>
+      while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != 0U)
+ 8007490:	4b3f      	ldr	r3, [pc, #252]	; (8007590 <HAL_RCC_OscConfig+0x4a4>)
+ 8007492:	6f5b      	ldr	r3, [r3, #116]	; 0x74
+ 8007494:	f003 0302 	and.w	r3, r3, #2
+ 8007498:	2b00      	cmp	r3, #0
+ 800749a:	d1f0      	bne.n	800747e <HAL_RCC_OscConfig+0x392>
+      }
+    }
+  }
+
+  /*------------------------------ HSI48 Configuration -------------------------*/
+  if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48)
+ 800749c:	687b      	ldr	r3, [r7, #4]
+ 800749e:	681b      	ldr	r3, [r3, #0]
+ 80074a0:	f003 0320 	and.w	r3, r3, #32
+ 80074a4:	2b00      	cmp	r3, #0
+ 80074a6:	d036      	beq.n	8007516 <HAL_RCC_OscConfig+0x42a>
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_HSI48(RCC_OscInitStruct->HSI48State));
+
+    /* Check the HSI48 State */
+    if ((RCC_OscInitStruct->HSI48State) != RCC_HSI48_OFF)
+ 80074a8:	687b      	ldr	r3, [r7, #4]
+ 80074aa:	699b      	ldr	r3, [r3, #24]
+ 80074ac:	2b00      	cmp	r3, #0
+ 80074ae:	d019      	beq.n	80074e4 <HAL_RCC_OscConfig+0x3f8>
+    {
+      /* Enable the Internal Low Speed oscillator (HSI48). */
+      __HAL_RCC_HSI48_ENABLE();
+ 80074b0:	4b37      	ldr	r3, [pc, #220]	; (8007590 <HAL_RCC_OscConfig+0x4a4>)
+ 80074b2:	681b      	ldr	r3, [r3, #0]
+ 80074b4:	4a36      	ldr	r2, [pc, #216]	; (8007590 <HAL_RCC_OscConfig+0x4a4>)
+ 80074b6:	f443 5380 	orr.w	r3, r3, #4096	; 0x1000
+ 80074ba:	6013      	str	r3, [r2, #0]
+
+      /* Get time-out */
+      tickstart = HAL_GetTick();
+ 80074bc:	f7fa ff52 	bl	8002364 <HAL_GetTick>
+ 80074c0:	6278      	str	r0, [r7, #36]	; 0x24
+
+      /* Wait till HSI48 is ready */
+      while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == 0U)
+ 80074c2:	e008      	b.n	80074d6 <HAL_RCC_OscConfig+0x3ea>
+      {
+        if ((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE)
+ 80074c4:	f7fa ff4e 	bl	8002364 <HAL_GetTick>
+ 80074c8:	4602      	mov	r2, r0
+ 80074ca:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 80074cc:	1ad3      	subs	r3, r2, r3
+ 80074ce:	2b02      	cmp	r3, #2
+ 80074d0:	d901      	bls.n	80074d6 <HAL_RCC_OscConfig+0x3ea>
+        {
+          return HAL_TIMEOUT;
+ 80074d2:	2303      	movs	r3, #3
+ 80074d4:	e1dc      	b.n	8007890 <HAL_RCC_OscConfig+0x7a4>
+      while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == 0U)
+ 80074d6:	4b2e      	ldr	r3, [pc, #184]	; (8007590 <HAL_RCC_OscConfig+0x4a4>)
+ 80074d8:	681b      	ldr	r3, [r3, #0]
+ 80074da:	f403 5300 	and.w	r3, r3, #8192	; 0x2000
+ 80074de:	2b00      	cmp	r3, #0
+ 80074e0:	d0f0      	beq.n	80074c4 <HAL_RCC_OscConfig+0x3d8>
+ 80074e2:	e018      	b.n	8007516 <HAL_RCC_OscConfig+0x42a>
+      }
+    }
+    else
+    {
+      /* Disable the Internal Low Speed oscillator (HSI48). */
+      __HAL_RCC_HSI48_DISABLE();
+ 80074e4:	4b2a      	ldr	r3, [pc, #168]	; (8007590 <HAL_RCC_OscConfig+0x4a4>)
+ 80074e6:	681b      	ldr	r3, [r3, #0]
+ 80074e8:	4a29      	ldr	r2, [pc, #164]	; (8007590 <HAL_RCC_OscConfig+0x4a4>)
+ 80074ea:	f423 5380 	bic.w	r3, r3, #4096	; 0x1000
+ 80074ee:	6013      	str	r3, [r2, #0]
+
+      /* Get time-out */
+      tickstart = HAL_GetTick();
+ 80074f0:	f7fa ff38 	bl	8002364 <HAL_GetTick>
+ 80074f4:	6278      	str	r0, [r7, #36]	; 0x24
+
+      /* Wait till HSI48 is ready */
+      while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != 0U)
+ 80074f6:	e008      	b.n	800750a <HAL_RCC_OscConfig+0x41e>
+      {
+        if ((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE)
+ 80074f8:	f7fa ff34 	bl	8002364 <HAL_GetTick>
+ 80074fc:	4602      	mov	r2, r0
+ 80074fe:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 8007500:	1ad3      	subs	r3, r2, r3
+ 8007502:	2b02      	cmp	r3, #2
+ 8007504:	d901      	bls.n	800750a <HAL_RCC_OscConfig+0x41e>
+        {
+          return HAL_TIMEOUT;
+ 8007506:	2303      	movs	r3, #3
+ 8007508:	e1c2      	b.n	8007890 <HAL_RCC_OscConfig+0x7a4>
+      while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != 0U)
+ 800750a:	4b21      	ldr	r3, [pc, #132]	; (8007590 <HAL_RCC_OscConfig+0x4a4>)
+ 800750c:	681b      	ldr	r3, [r3, #0]
+ 800750e:	f403 5300 	and.w	r3, r3, #8192	; 0x2000
+ 8007512:	2b00      	cmp	r3, #0
+ 8007514:	d1f0      	bne.n	80074f8 <HAL_RCC_OscConfig+0x40c>
+        }
+      }
+    }
+  }
+  /*------------------------------ LSE Configuration -------------------------*/
+  if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
+ 8007516:	687b      	ldr	r3, [r7, #4]
+ 8007518:	681b      	ldr	r3, [r3, #0]
+ 800751a:	f003 0304 	and.w	r3, r3, #4
+ 800751e:	2b00      	cmp	r3, #0
+ 8007520:	f000 8086 	beq.w	8007630 <HAL_RCC_OscConfig+0x544>
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
+
+    /* Enable write access to Backup domain */
+    PWR->CR1 |= PWR_CR1_DBP;
+ 8007524:	4b1b      	ldr	r3, [pc, #108]	; (8007594 <HAL_RCC_OscConfig+0x4a8>)
+ 8007526:	681b      	ldr	r3, [r3, #0]
+ 8007528:	4a1a      	ldr	r2, [pc, #104]	; (8007594 <HAL_RCC_OscConfig+0x4a8>)
+ 800752a:	f443 7380 	orr.w	r3, r3, #256	; 0x100
+ 800752e:	6013      	str	r3, [r2, #0]
+
+    /* Wait for Backup domain Write protection disable */
+    tickstart = HAL_GetTick();
+ 8007530:	f7fa ff18 	bl	8002364 <HAL_GetTick>
+ 8007534:	6278      	str	r0, [r7, #36]	; 0x24
+
+    while ((PWR->CR1 & PWR_CR1_DBP) == 0U)
+ 8007536:	e008      	b.n	800754a <HAL_RCC_OscConfig+0x45e>
+    {
+      if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
+ 8007538:	f7fa ff14 	bl	8002364 <HAL_GetTick>
+ 800753c:	4602      	mov	r2, r0
+ 800753e:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 8007540:	1ad3      	subs	r3, r2, r3
+ 8007542:	2b64      	cmp	r3, #100	; 0x64
+ 8007544:	d901      	bls.n	800754a <HAL_RCC_OscConfig+0x45e>
+      {
+        return HAL_TIMEOUT;
+ 8007546:	2303      	movs	r3, #3
+ 8007548:	e1a2      	b.n	8007890 <HAL_RCC_OscConfig+0x7a4>
+    while ((PWR->CR1 & PWR_CR1_DBP) == 0U)
+ 800754a:	4b12      	ldr	r3, [pc, #72]	; (8007594 <HAL_RCC_OscConfig+0x4a8>)
+ 800754c:	681b      	ldr	r3, [r3, #0]
+ 800754e:	f403 7380 	and.w	r3, r3, #256	; 0x100
+ 8007552:	2b00      	cmp	r3, #0
+ 8007554:	d0f0      	beq.n	8007538 <HAL_RCC_OscConfig+0x44c>
+      }
+    }
+
+    /* Set the new LSE configuration -----------------------------------------*/
+    __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
+ 8007556:	687b      	ldr	r3, [r7, #4]
+ 8007558:	689b      	ldr	r3, [r3, #8]
+ 800755a:	2b01      	cmp	r3, #1
+ 800755c:	d106      	bne.n	800756c <HAL_RCC_OscConfig+0x480>
+ 800755e:	4b0c      	ldr	r3, [pc, #48]	; (8007590 <HAL_RCC_OscConfig+0x4a4>)
+ 8007560:	6f1b      	ldr	r3, [r3, #112]	; 0x70
+ 8007562:	4a0b      	ldr	r2, [pc, #44]	; (8007590 <HAL_RCC_OscConfig+0x4a4>)
+ 8007564:	f043 0301 	orr.w	r3, r3, #1
+ 8007568:	6713      	str	r3, [r2, #112]	; 0x70
+ 800756a:	e032      	b.n	80075d2 <HAL_RCC_OscConfig+0x4e6>
+ 800756c:	687b      	ldr	r3, [r7, #4]
+ 800756e:	689b      	ldr	r3, [r3, #8]
+ 8007570:	2b00      	cmp	r3, #0
+ 8007572:	d111      	bne.n	8007598 <HAL_RCC_OscConfig+0x4ac>
+ 8007574:	4b06      	ldr	r3, [pc, #24]	; (8007590 <HAL_RCC_OscConfig+0x4a4>)
+ 8007576:	6f1b      	ldr	r3, [r3, #112]	; 0x70
+ 8007578:	4a05      	ldr	r2, [pc, #20]	; (8007590 <HAL_RCC_OscConfig+0x4a4>)
+ 800757a:	f023 0301 	bic.w	r3, r3, #1
+ 800757e:	6713      	str	r3, [r2, #112]	; 0x70
+ 8007580:	4b03      	ldr	r3, [pc, #12]	; (8007590 <HAL_RCC_OscConfig+0x4a4>)
+ 8007582:	6f1b      	ldr	r3, [r3, #112]	; 0x70
+ 8007584:	4a02      	ldr	r2, [pc, #8]	; (8007590 <HAL_RCC_OscConfig+0x4a4>)
+ 8007586:	f023 0304 	bic.w	r3, r3, #4
+ 800758a:	6713      	str	r3, [r2, #112]	; 0x70
+ 800758c:	e021      	b.n	80075d2 <HAL_RCC_OscConfig+0x4e6>
+ 800758e:	bf00      	nop
+ 8007590:	58024400 	.word	0x58024400
+ 8007594:	58024800 	.word	0x58024800
+ 8007598:	687b      	ldr	r3, [r7, #4]
+ 800759a:	689b      	ldr	r3, [r3, #8]
+ 800759c:	2b05      	cmp	r3, #5
+ 800759e:	d10c      	bne.n	80075ba <HAL_RCC_OscConfig+0x4ce>
+ 80075a0:	4b83      	ldr	r3, [pc, #524]	; (80077b0 <HAL_RCC_OscConfig+0x6c4>)
+ 80075a2:	6f1b      	ldr	r3, [r3, #112]	; 0x70
+ 80075a4:	4a82      	ldr	r2, [pc, #520]	; (80077b0 <HAL_RCC_OscConfig+0x6c4>)
+ 80075a6:	f043 0304 	orr.w	r3, r3, #4
+ 80075aa:	6713      	str	r3, [r2, #112]	; 0x70
+ 80075ac:	4b80      	ldr	r3, [pc, #512]	; (80077b0 <HAL_RCC_OscConfig+0x6c4>)
+ 80075ae:	6f1b      	ldr	r3, [r3, #112]	; 0x70
+ 80075b0:	4a7f      	ldr	r2, [pc, #508]	; (80077b0 <HAL_RCC_OscConfig+0x6c4>)
+ 80075b2:	f043 0301 	orr.w	r3, r3, #1
+ 80075b6:	6713      	str	r3, [r2, #112]	; 0x70
+ 80075b8:	e00b      	b.n	80075d2 <HAL_RCC_OscConfig+0x4e6>
+ 80075ba:	4b7d      	ldr	r3, [pc, #500]	; (80077b0 <HAL_RCC_OscConfig+0x6c4>)
+ 80075bc:	6f1b      	ldr	r3, [r3, #112]	; 0x70
+ 80075be:	4a7c      	ldr	r2, [pc, #496]	; (80077b0 <HAL_RCC_OscConfig+0x6c4>)
+ 80075c0:	f023 0301 	bic.w	r3, r3, #1
+ 80075c4:	6713      	str	r3, [r2, #112]	; 0x70
+ 80075c6:	4b7a      	ldr	r3, [pc, #488]	; (80077b0 <HAL_RCC_OscConfig+0x6c4>)
+ 80075c8:	6f1b      	ldr	r3, [r3, #112]	; 0x70
+ 80075ca:	4a79      	ldr	r2, [pc, #484]	; (80077b0 <HAL_RCC_OscConfig+0x6c4>)
+ 80075cc:	f023 0304 	bic.w	r3, r3, #4
+ 80075d0:	6713      	str	r3, [r2, #112]	; 0x70
+    /* Check the LSE State */
+    if ((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)
+ 80075d2:	687b      	ldr	r3, [r7, #4]
+ 80075d4:	689b      	ldr	r3, [r3, #8]
+ 80075d6:	2b00      	cmp	r3, #0
+ 80075d8:	d015      	beq.n	8007606 <HAL_RCC_OscConfig+0x51a>
+    {
+      /* Get Start Tick*/
+      tickstart = HAL_GetTick();
+ 80075da:	f7fa fec3 	bl	8002364 <HAL_GetTick>
+ 80075de:	6278      	str	r0, [r7, #36]	; 0x24
+
+      /* Wait till LSE is ready */
+      while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U)
+ 80075e0:	e00a      	b.n	80075f8 <HAL_RCC_OscConfig+0x50c>
+      {
+        if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
+ 80075e2:	f7fa febf 	bl	8002364 <HAL_GetTick>
+ 80075e6:	4602      	mov	r2, r0
+ 80075e8:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 80075ea:	1ad3      	subs	r3, r2, r3
+ 80075ec:	f241 3288 	movw	r2, #5000	; 0x1388
+ 80075f0:	4293      	cmp	r3, r2
+ 80075f2:	d901      	bls.n	80075f8 <HAL_RCC_OscConfig+0x50c>
+        {
+          return HAL_TIMEOUT;
+ 80075f4:	2303      	movs	r3, #3
+ 80075f6:	e14b      	b.n	8007890 <HAL_RCC_OscConfig+0x7a4>
+      while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U)
+ 80075f8:	4b6d      	ldr	r3, [pc, #436]	; (80077b0 <HAL_RCC_OscConfig+0x6c4>)
+ 80075fa:	6f1b      	ldr	r3, [r3, #112]	; 0x70
+ 80075fc:	f003 0302 	and.w	r3, r3, #2
+ 8007600:	2b00      	cmp	r3, #0
+ 8007602:	d0ee      	beq.n	80075e2 <HAL_RCC_OscConfig+0x4f6>
+ 8007604:	e014      	b.n	8007630 <HAL_RCC_OscConfig+0x544>
+      }
+    }
+    else
+    {
+      /* Get Start Tick*/
+      tickstart = HAL_GetTick();
+ 8007606:	f7fa fead 	bl	8002364 <HAL_GetTick>
+ 800760a:	6278      	str	r0, [r7, #36]	; 0x24
+
+      /* Wait till LSE is disabled */
+      while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U)
+ 800760c:	e00a      	b.n	8007624 <HAL_RCC_OscConfig+0x538>
+      {
+        if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
+ 800760e:	f7fa fea9 	bl	8002364 <HAL_GetTick>
+ 8007612:	4602      	mov	r2, r0
+ 8007614:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 8007616:	1ad3      	subs	r3, r2, r3
+ 8007618:	f241 3288 	movw	r2, #5000	; 0x1388
+ 800761c:	4293      	cmp	r3, r2
+ 800761e:	d901      	bls.n	8007624 <HAL_RCC_OscConfig+0x538>
+        {
+          return HAL_TIMEOUT;
+ 8007620:	2303      	movs	r3, #3
+ 8007622:	e135      	b.n	8007890 <HAL_RCC_OscConfig+0x7a4>
+      while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U)
+ 8007624:	4b62      	ldr	r3, [pc, #392]	; (80077b0 <HAL_RCC_OscConfig+0x6c4>)
+ 8007626:	6f1b      	ldr	r3, [r3, #112]	; 0x70
+ 8007628:	f003 0302 	and.w	r3, r3, #2
+ 800762c:	2b00      	cmp	r3, #0
+ 800762e:	d1ee      	bne.n	800760e <HAL_RCC_OscConfig+0x522>
+    }
+  }
+  /*-------------------------------- PLL Configuration -----------------------*/
+  /* Check the parameters */
+  assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
+  if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
+ 8007630:	687b      	ldr	r3, [r7, #4]
+ 8007632:	6a5b      	ldr	r3, [r3, #36]	; 0x24
+ 8007634:	2b00      	cmp	r3, #0
+ 8007636:	f000 812a 	beq.w	800788e <HAL_RCC_OscConfig+0x7a2>
+  {
+    /* Check if the PLL is used as system clock or not */
+    if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL1)
+ 800763a:	4b5d      	ldr	r3, [pc, #372]	; (80077b0 <HAL_RCC_OscConfig+0x6c4>)
+ 800763c:	691b      	ldr	r3, [r3, #16]
+ 800763e:	f003 0338 	and.w	r3, r3, #56	; 0x38
+ 8007642:	2b18      	cmp	r3, #24
+ 8007644:	f000 80ba 	beq.w	80077bc <HAL_RCC_OscConfig+0x6d0>
+    {
+      if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
+ 8007648:	687b      	ldr	r3, [r7, #4]
+ 800764a:	6a5b      	ldr	r3, [r3, #36]	; 0x24
+ 800764c:	2b02      	cmp	r3, #2
+ 800764e:	f040 8095 	bne.w	800777c <HAL_RCC_OscConfig+0x690>
+        assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
+        assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR));
+        assert_param(IS_RCC_PLLFRACN_VALUE(RCC_OscInitStruct->PLL.PLLFRACN));
+
+        /* Disable the main PLL. */
+        __HAL_RCC_PLL_DISABLE();
+ 8007652:	4b57      	ldr	r3, [pc, #348]	; (80077b0 <HAL_RCC_OscConfig+0x6c4>)
+ 8007654:	681b      	ldr	r3, [r3, #0]
+ 8007656:	4a56      	ldr	r2, [pc, #344]	; (80077b0 <HAL_RCC_OscConfig+0x6c4>)
+ 8007658:	f023 7380 	bic.w	r3, r3, #16777216	; 0x1000000
+ 800765c:	6013      	str	r3, [r2, #0]
+
+        /* Get Start Tick*/
+        tickstart = HAL_GetTick();
+ 800765e:	f7fa fe81 	bl	8002364 <HAL_GetTick>
+ 8007662:	6278      	str	r0, [r7, #36]	; 0x24
+
+        /* Wait till PLL is disabled */
+        while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U)
+ 8007664:	e008      	b.n	8007678 <HAL_RCC_OscConfig+0x58c>
+        {
+          if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
+ 8007666:	f7fa fe7d 	bl	8002364 <HAL_GetTick>
+ 800766a:	4602      	mov	r2, r0
+ 800766c:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 800766e:	1ad3      	subs	r3, r2, r3
+ 8007670:	2b02      	cmp	r3, #2
+ 8007672:	d901      	bls.n	8007678 <HAL_RCC_OscConfig+0x58c>
+          {
+            return HAL_TIMEOUT;
+ 8007674:	2303      	movs	r3, #3
+ 8007676:	e10b      	b.n	8007890 <HAL_RCC_OscConfig+0x7a4>
+        while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U)
+ 8007678:	4b4d      	ldr	r3, [pc, #308]	; (80077b0 <HAL_RCC_OscConfig+0x6c4>)
+ 800767a:	681b      	ldr	r3, [r3, #0]
+ 800767c:	f003 7300 	and.w	r3, r3, #33554432	; 0x2000000
+ 8007680:	2b00      	cmp	r3, #0
+ 8007682:	d1f0      	bne.n	8007666 <HAL_RCC_OscConfig+0x57a>
+          }
+        }
+
+        /* Configure the main PLL clock source, multiplication and division factors. */
+        __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
+ 8007684:	4b4a      	ldr	r3, [pc, #296]	; (80077b0 <HAL_RCC_OscConfig+0x6c4>)
+ 8007686:	6a9a      	ldr	r2, [r3, #40]	; 0x28
+ 8007688:	4b4a      	ldr	r3, [pc, #296]	; (80077b4 <HAL_RCC_OscConfig+0x6c8>)
+ 800768a:	4013      	ands	r3, r2
+ 800768c:	687a      	ldr	r2, [r7, #4]
+ 800768e:	6a91      	ldr	r1, [r2, #40]	; 0x28
+ 8007690:	687a      	ldr	r2, [r7, #4]
+ 8007692:	6ad2      	ldr	r2, [r2, #44]	; 0x2c
+ 8007694:	0112      	lsls	r2, r2, #4
+ 8007696:	430a      	orrs	r2, r1
+ 8007698:	4945      	ldr	r1, [pc, #276]	; (80077b0 <HAL_RCC_OscConfig+0x6c4>)
+ 800769a:	4313      	orrs	r3, r2
+ 800769c:	628b      	str	r3, [r1, #40]	; 0x28
+ 800769e:	687b      	ldr	r3, [r7, #4]
+ 80076a0:	6b1b      	ldr	r3, [r3, #48]	; 0x30
+ 80076a2:	3b01      	subs	r3, #1
+ 80076a4:	f3c3 0208 	ubfx	r2, r3, #0, #9
+ 80076a8:	687b      	ldr	r3, [r7, #4]
+ 80076aa:	6b5b      	ldr	r3, [r3, #52]	; 0x34
+ 80076ac:	3b01      	subs	r3, #1
+ 80076ae:	025b      	lsls	r3, r3, #9
+ 80076b0:	b29b      	uxth	r3, r3
+ 80076b2:	431a      	orrs	r2, r3
+ 80076b4:	687b      	ldr	r3, [r7, #4]
+ 80076b6:	6b9b      	ldr	r3, [r3, #56]	; 0x38
+ 80076b8:	3b01      	subs	r3, #1
+ 80076ba:	041b      	lsls	r3, r3, #16
+ 80076bc:	f403 03fe 	and.w	r3, r3, #8323072	; 0x7f0000
+ 80076c0:	431a      	orrs	r2, r3
+ 80076c2:	687b      	ldr	r3, [r7, #4]
+ 80076c4:	6bdb      	ldr	r3, [r3, #60]	; 0x3c
+ 80076c6:	3b01      	subs	r3, #1
+ 80076c8:	061b      	lsls	r3, r3, #24
+ 80076ca:	f003 43fe 	and.w	r3, r3, #2130706432	; 0x7f000000
+ 80076ce:	4938      	ldr	r1, [pc, #224]	; (80077b0 <HAL_RCC_OscConfig+0x6c4>)
+ 80076d0:	4313      	orrs	r3, r2
+ 80076d2:	630b      	str	r3, [r1, #48]	; 0x30
+                             RCC_OscInitStruct->PLL.PLLP,
+                             RCC_OscInitStruct->PLL.PLLQ,
+                             RCC_OscInitStruct->PLL.PLLR);
+
+        /* Disable PLLFRACN . */
+        __HAL_RCC_PLLFRACN_DISABLE();
+ 80076d4:	4b36      	ldr	r3, [pc, #216]	; (80077b0 <HAL_RCC_OscConfig+0x6c4>)
+ 80076d6:	6adb      	ldr	r3, [r3, #44]	; 0x2c
+ 80076d8:	4a35      	ldr	r2, [pc, #212]	; (80077b0 <HAL_RCC_OscConfig+0x6c4>)
+ 80076da:	f023 0301 	bic.w	r3, r3, #1
+ 80076de:	62d3      	str	r3, [r2, #44]	; 0x2c
+
+        /* Configure PLL PLL1FRACN */
+        __HAL_RCC_PLLFRACN_CONFIG(RCC_OscInitStruct->PLL.PLLFRACN);
+ 80076e0:	4b33      	ldr	r3, [pc, #204]	; (80077b0 <HAL_RCC_OscConfig+0x6c4>)
+ 80076e2:	6b5a      	ldr	r2, [r3, #52]	; 0x34
+ 80076e4:	4b34      	ldr	r3, [pc, #208]	; (80077b8 <HAL_RCC_OscConfig+0x6cc>)
+ 80076e6:	4013      	ands	r3, r2
+ 80076e8:	687a      	ldr	r2, [r7, #4]
+ 80076ea:	6c92      	ldr	r2, [r2, #72]	; 0x48
+ 80076ec:	00d2      	lsls	r2, r2, #3
+ 80076ee:	4930      	ldr	r1, [pc, #192]	; (80077b0 <HAL_RCC_OscConfig+0x6c4>)
+ 80076f0:	4313      	orrs	r3, r2
+ 80076f2:	634b      	str	r3, [r1, #52]	; 0x34
+
+        /* Select PLL1 input reference frequency range: VCI */
+        __HAL_RCC_PLL_VCIRANGE(RCC_OscInitStruct->PLL.PLLRGE) ;
+ 80076f4:	4b2e      	ldr	r3, [pc, #184]	; (80077b0 <HAL_RCC_OscConfig+0x6c4>)
+ 80076f6:	6adb      	ldr	r3, [r3, #44]	; 0x2c
+ 80076f8:	f023 020c 	bic.w	r2, r3, #12
+ 80076fc:	687b      	ldr	r3, [r7, #4]
+ 80076fe:	6c1b      	ldr	r3, [r3, #64]	; 0x40
+ 8007700:	492b      	ldr	r1, [pc, #172]	; (80077b0 <HAL_RCC_OscConfig+0x6c4>)
+ 8007702:	4313      	orrs	r3, r2
+ 8007704:	62cb      	str	r3, [r1, #44]	; 0x2c
+
+        /* Select PLL1 output frequency range : VCO */
+        __HAL_RCC_PLL_VCORANGE(RCC_OscInitStruct->PLL.PLLVCOSEL) ;
+ 8007706:	4b2a      	ldr	r3, [pc, #168]	; (80077b0 <HAL_RCC_OscConfig+0x6c4>)
+ 8007708:	6adb      	ldr	r3, [r3, #44]	; 0x2c
+ 800770a:	f023 0202 	bic.w	r2, r3, #2
+ 800770e:	687b      	ldr	r3, [r7, #4]
+ 8007710:	6c5b      	ldr	r3, [r3, #68]	; 0x44
+ 8007712:	4927      	ldr	r1, [pc, #156]	; (80077b0 <HAL_RCC_OscConfig+0x6c4>)
+ 8007714:	4313      	orrs	r3, r2
+ 8007716:	62cb      	str	r3, [r1, #44]	; 0x2c
+
+        /* Enable PLL System Clock output. */
+        __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVP);
+ 8007718:	4b25      	ldr	r3, [pc, #148]	; (80077b0 <HAL_RCC_OscConfig+0x6c4>)
+ 800771a:	6adb      	ldr	r3, [r3, #44]	; 0x2c
+ 800771c:	4a24      	ldr	r2, [pc, #144]	; (80077b0 <HAL_RCC_OscConfig+0x6c4>)
+ 800771e:	f443 3380 	orr.w	r3, r3, #65536	; 0x10000
+ 8007722:	62d3      	str	r3, [r2, #44]	; 0x2c
+
+        /* Enable PLL1Q Clock output. */
+        __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
+ 8007724:	4b22      	ldr	r3, [pc, #136]	; (80077b0 <HAL_RCC_OscConfig+0x6c4>)
+ 8007726:	6adb      	ldr	r3, [r3, #44]	; 0x2c
+ 8007728:	4a21      	ldr	r2, [pc, #132]	; (80077b0 <HAL_RCC_OscConfig+0x6c4>)
+ 800772a:	f443 3300 	orr.w	r3, r3, #131072	; 0x20000
+ 800772e:	62d3      	str	r3, [r2, #44]	; 0x2c
+
+        /* Enable PLL1R  Clock output. */
+        __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVR);
+ 8007730:	4b1f      	ldr	r3, [pc, #124]	; (80077b0 <HAL_RCC_OscConfig+0x6c4>)
+ 8007732:	6adb      	ldr	r3, [r3, #44]	; 0x2c
+ 8007734:	4a1e      	ldr	r2, [pc, #120]	; (80077b0 <HAL_RCC_OscConfig+0x6c4>)
+ 8007736:	f443 2380 	orr.w	r3, r3, #262144	; 0x40000
+ 800773a:	62d3      	str	r3, [r2, #44]	; 0x2c
+
+        /* Enable PLL1FRACN . */
+        __HAL_RCC_PLLFRACN_ENABLE();
+ 800773c:	4b1c      	ldr	r3, [pc, #112]	; (80077b0 <HAL_RCC_OscConfig+0x6c4>)
+ 800773e:	6adb      	ldr	r3, [r3, #44]	; 0x2c
+ 8007740:	4a1b      	ldr	r2, [pc, #108]	; (80077b0 <HAL_RCC_OscConfig+0x6c4>)
+ 8007742:	f043 0301 	orr.w	r3, r3, #1
+ 8007746:	62d3      	str	r3, [r2, #44]	; 0x2c
+
+        /* Enable the main PLL. */
+        __HAL_RCC_PLL_ENABLE();
+ 8007748:	4b19      	ldr	r3, [pc, #100]	; (80077b0 <HAL_RCC_OscConfig+0x6c4>)
+ 800774a:	681b      	ldr	r3, [r3, #0]
+ 800774c:	4a18      	ldr	r2, [pc, #96]	; (80077b0 <HAL_RCC_OscConfig+0x6c4>)
+ 800774e:	f043 7380 	orr.w	r3, r3, #16777216	; 0x1000000
+ 8007752:	6013      	str	r3, [r2, #0]
+
+        /* Get Start Tick*/
+        tickstart = HAL_GetTick();
+ 8007754:	f7fa fe06 	bl	8002364 <HAL_GetTick>
+ 8007758:	6278      	str	r0, [r7, #36]	; 0x24
+
+        /* Wait till PLL is ready */
+        while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U)
+ 800775a:	e008      	b.n	800776e <HAL_RCC_OscConfig+0x682>
+        {
+          if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
+ 800775c:	f7fa fe02 	bl	8002364 <HAL_GetTick>
+ 8007760:	4602      	mov	r2, r0
+ 8007762:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 8007764:	1ad3      	subs	r3, r2, r3
+ 8007766:	2b02      	cmp	r3, #2
+ 8007768:	d901      	bls.n	800776e <HAL_RCC_OscConfig+0x682>
+          {
+            return HAL_TIMEOUT;
+ 800776a:	2303      	movs	r3, #3
+ 800776c:	e090      	b.n	8007890 <HAL_RCC_OscConfig+0x7a4>
+        while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U)
+ 800776e:	4b10      	ldr	r3, [pc, #64]	; (80077b0 <HAL_RCC_OscConfig+0x6c4>)
+ 8007770:	681b      	ldr	r3, [r3, #0]
+ 8007772:	f003 7300 	and.w	r3, r3, #33554432	; 0x2000000
+ 8007776:	2b00      	cmp	r3, #0
+ 8007778:	d0f0      	beq.n	800775c <HAL_RCC_OscConfig+0x670>
+ 800777a:	e088      	b.n	800788e <HAL_RCC_OscConfig+0x7a2>
+        }
+      }
+      else
+      {
+        /* Disable the main PLL. */
+        __HAL_RCC_PLL_DISABLE();
+ 800777c:	4b0c      	ldr	r3, [pc, #48]	; (80077b0 <HAL_RCC_OscConfig+0x6c4>)
+ 800777e:	681b      	ldr	r3, [r3, #0]
+ 8007780:	4a0b      	ldr	r2, [pc, #44]	; (80077b0 <HAL_RCC_OscConfig+0x6c4>)
+ 8007782:	f023 7380 	bic.w	r3, r3, #16777216	; 0x1000000
+ 8007786:	6013      	str	r3, [r2, #0]
+
+        /* Get Start Tick*/
+        tickstart = HAL_GetTick();
+ 8007788:	f7fa fdec 	bl	8002364 <HAL_GetTick>
+ 800778c:	6278      	str	r0, [r7, #36]	; 0x24
+
+        /* Wait till PLL is disabled */
+        while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U)
+ 800778e:	e008      	b.n	80077a2 <HAL_RCC_OscConfig+0x6b6>
+        {
+          if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
+ 8007790:	f7fa fde8 	bl	8002364 <HAL_GetTick>
+ 8007794:	4602      	mov	r2, r0
+ 8007796:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 8007798:	1ad3      	subs	r3, r2, r3
+ 800779a:	2b02      	cmp	r3, #2
+ 800779c:	d901      	bls.n	80077a2 <HAL_RCC_OscConfig+0x6b6>
+          {
+            return HAL_TIMEOUT;
+ 800779e:	2303      	movs	r3, #3
+ 80077a0:	e076      	b.n	8007890 <HAL_RCC_OscConfig+0x7a4>
+        while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U)
+ 80077a2:	4b03      	ldr	r3, [pc, #12]	; (80077b0 <HAL_RCC_OscConfig+0x6c4>)
+ 80077a4:	681b      	ldr	r3, [r3, #0]
+ 80077a6:	f003 7300 	and.w	r3, r3, #33554432	; 0x2000000
+ 80077aa:	2b00      	cmp	r3, #0
+ 80077ac:	d1f0      	bne.n	8007790 <HAL_RCC_OscConfig+0x6a4>
+ 80077ae:	e06e      	b.n	800788e <HAL_RCC_OscConfig+0x7a2>
+ 80077b0:	58024400 	.word	0x58024400
+ 80077b4:	fffffc0c 	.word	0xfffffc0c
+ 80077b8:	ffff0007 	.word	0xffff0007
+      }
+    }
+    else
+    {
+      /* Do not return HAL_ERROR if request repeats the current configuration */
+      temp1_pllckcfg = RCC->PLLCKSELR;
+ 80077bc:	4b36      	ldr	r3, [pc, #216]	; (8007898 <HAL_RCC_OscConfig+0x7ac>)
+ 80077be:	6a9b      	ldr	r3, [r3, #40]	; 0x28
+ 80077c0:	613b      	str	r3, [r7, #16]
+      temp2_pllckcfg = RCC->PLL1DIVR;
+ 80077c2:	4b35      	ldr	r3, [pc, #212]	; (8007898 <HAL_RCC_OscConfig+0x7ac>)
+ 80077c4:	6b1b      	ldr	r3, [r3, #48]	; 0x30
+ 80077c6:	60fb      	str	r3, [r7, #12]
+      if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
+ 80077c8:	687b      	ldr	r3, [r7, #4]
+ 80077ca:	6a5b      	ldr	r3, [r3, #36]	; 0x24
+ 80077cc:	2b01      	cmp	r3, #1
+ 80077ce:	d031      	beq.n	8007834 <HAL_RCC_OscConfig+0x748>
+          (READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
+ 80077d0:	693b      	ldr	r3, [r7, #16]
+ 80077d2:	f003 0203 	and.w	r2, r3, #3
+ 80077d6:	687b      	ldr	r3, [r7, #4]
+ 80077d8:	6a9b      	ldr	r3, [r3, #40]	; 0x28
+      if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
+ 80077da:	429a      	cmp	r2, r3
+ 80077dc:	d12a      	bne.n	8007834 <HAL_RCC_OscConfig+0x748>
+          ((READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_DIVM1) >> RCC_PLLCKSELR_DIVM1_Pos) != RCC_OscInitStruct->PLL.PLLM) ||
+ 80077de:	693b      	ldr	r3, [r7, #16]
+ 80077e0:	091b      	lsrs	r3, r3, #4
+ 80077e2:	f003 023f 	and.w	r2, r3, #63	; 0x3f
+ 80077e6:	687b      	ldr	r3, [r7, #4]
+ 80077e8:	6adb      	ldr	r3, [r3, #44]	; 0x2c
+          (READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
+ 80077ea:	429a      	cmp	r2, r3
+ 80077ec:	d122      	bne.n	8007834 <HAL_RCC_OscConfig+0x748>
+          (READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_N1) != (RCC_OscInitStruct->PLL.PLLN - 1U)) ||
+ 80077ee:	68fb      	ldr	r3, [r7, #12]
+ 80077f0:	f3c3 0208 	ubfx	r2, r3, #0, #9
+ 80077f4:	687b      	ldr	r3, [r7, #4]
+ 80077f6:	6b1b      	ldr	r3, [r3, #48]	; 0x30
+ 80077f8:	3b01      	subs	r3, #1
+          ((READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_DIVM1) >> RCC_PLLCKSELR_DIVM1_Pos) != RCC_OscInitStruct->PLL.PLLM) ||
+ 80077fa:	429a      	cmp	r2, r3
+ 80077fc:	d11a      	bne.n	8007834 <HAL_RCC_OscConfig+0x748>
+          ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_P1) >> RCC_PLL1DIVR_P1_Pos) != (RCC_OscInitStruct->PLL.PLLP - 1U)) ||
+ 80077fe:	68fb      	ldr	r3, [r7, #12]
+ 8007800:	0a5b      	lsrs	r3, r3, #9
+ 8007802:	f003 027f 	and.w	r2, r3, #127	; 0x7f
+ 8007806:	687b      	ldr	r3, [r7, #4]
+ 8007808:	6b5b      	ldr	r3, [r3, #52]	; 0x34
+ 800780a:	3b01      	subs	r3, #1
+          (READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_N1) != (RCC_OscInitStruct->PLL.PLLN - 1U)) ||
+ 800780c:	429a      	cmp	r2, r3
+ 800780e:	d111      	bne.n	8007834 <HAL_RCC_OscConfig+0x748>
+          ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_Q1) >> RCC_PLL1DIVR_Q1_Pos) != (RCC_OscInitStruct->PLL.PLLQ - 1U)) ||
+ 8007810:	68fb      	ldr	r3, [r7, #12]
+ 8007812:	0c1b      	lsrs	r3, r3, #16
+ 8007814:	f003 027f 	and.w	r2, r3, #127	; 0x7f
+ 8007818:	687b      	ldr	r3, [r7, #4]
+ 800781a:	6b9b      	ldr	r3, [r3, #56]	; 0x38
+ 800781c:	3b01      	subs	r3, #1
+          ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_P1) >> RCC_PLL1DIVR_P1_Pos) != (RCC_OscInitStruct->PLL.PLLP - 1U)) ||
+ 800781e:	429a      	cmp	r2, r3
+ 8007820:	d108      	bne.n	8007834 <HAL_RCC_OscConfig+0x748>
+          ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_R1) >> RCC_PLL1DIVR_R1_Pos) != (RCC_OscInitStruct->PLL.PLLR - 1U)))
+ 8007822:	68fb      	ldr	r3, [r7, #12]
+ 8007824:	0e1b      	lsrs	r3, r3, #24
+ 8007826:	f003 027f 	and.w	r2, r3, #127	; 0x7f
+ 800782a:	687b      	ldr	r3, [r7, #4]
+ 800782c:	6bdb      	ldr	r3, [r3, #60]	; 0x3c
+ 800782e:	3b01      	subs	r3, #1
+          ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_Q1) >> RCC_PLL1DIVR_Q1_Pos) != (RCC_OscInitStruct->PLL.PLLQ - 1U)) ||
+ 8007830:	429a      	cmp	r2, r3
+ 8007832:	d001      	beq.n	8007838 <HAL_RCC_OscConfig+0x74c>
+      {
+        return HAL_ERROR;
+ 8007834:	2301      	movs	r3, #1
+ 8007836:	e02b      	b.n	8007890 <HAL_RCC_OscConfig+0x7a4>
+      }
+      else
+      {
+        /* Check if only fractional part needs to be updated  */
+        temp1_pllckcfg = ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> RCC_PLL1FRACR_FRACN1_Pos);
+ 8007838:	4b17      	ldr	r3, [pc, #92]	; (8007898 <HAL_RCC_OscConfig+0x7ac>)
+ 800783a:	6b5b      	ldr	r3, [r3, #52]	; 0x34
+ 800783c:	08db      	lsrs	r3, r3, #3
+ 800783e:	f3c3 030c 	ubfx	r3, r3, #0, #13
+ 8007842:	613b      	str	r3, [r7, #16]
+        if (RCC_OscInitStruct->PLL.PLLFRACN != temp1_pllckcfg)
+ 8007844:	687b      	ldr	r3, [r7, #4]
+ 8007846:	6c9b      	ldr	r3, [r3, #72]	; 0x48
+ 8007848:	693a      	ldr	r2, [r7, #16]
+ 800784a:	429a      	cmp	r2, r3
+ 800784c:	d01f      	beq.n	800788e <HAL_RCC_OscConfig+0x7a2>
+        {
+          assert_param(IS_RCC_PLLFRACN_VALUE(RCC_OscInitStruct->PLL.PLLFRACN));
+          /* Disable PLL1FRACEN */
+          __HAL_RCC_PLLFRACN_DISABLE();
+ 800784e:	4b12      	ldr	r3, [pc, #72]	; (8007898 <HAL_RCC_OscConfig+0x7ac>)
+ 8007850:	6adb      	ldr	r3, [r3, #44]	; 0x2c
+ 8007852:	4a11      	ldr	r2, [pc, #68]	; (8007898 <HAL_RCC_OscConfig+0x7ac>)
+ 8007854:	f023 0301 	bic.w	r3, r3, #1
+ 8007858:	62d3      	str	r3, [r2, #44]	; 0x2c
+          /* Get Start Tick*/
+          tickstart = HAL_GetTick();
+ 800785a:	f7fa fd83 	bl	8002364 <HAL_GetTick>
+ 800785e:	6278      	str	r0, [r7, #36]	; 0x24
+          /* Wait at least 2 CK_REF (PLL input source divided by M) period to make sure next latched value will be taken into account. */
+          while ((HAL_GetTick() - tickstart) < PLL_FRAC_TIMEOUT_VALUE)
+ 8007860:	bf00      	nop
+ 8007862:	f7fa fd7f 	bl	8002364 <HAL_GetTick>
+ 8007866:	4602      	mov	r2, r0
+ 8007868:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 800786a:	4293      	cmp	r3, r2
+ 800786c:	d0f9      	beq.n	8007862 <HAL_RCC_OscConfig+0x776>
+          {
+          }
+          /* Configure PLL1 PLL1FRACN */
+          __HAL_RCC_PLLFRACN_CONFIG(RCC_OscInitStruct->PLL.PLLFRACN);
+ 800786e:	4b0a      	ldr	r3, [pc, #40]	; (8007898 <HAL_RCC_OscConfig+0x7ac>)
+ 8007870:	6b5a      	ldr	r2, [r3, #52]	; 0x34
+ 8007872:	4b0a      	ldr	r3, [pc, #40]	; (800789c <HAL_RCC_OscConfig+0x7b0>)
+ 8007874:	4013      	ands	r3, r2
+ 8007876:	687a      	ldr	r2, [r7, #4]
+ 8007878:	6c92      	ldr	r2, [r2, #72]	; 0x48
+ 800787a:	00d2      	lsls	r2, r2, #3
+ 800787c:	4906      	ldr	r1, [pc, #24]	; (8007898 <HAL_RCC_OscConfig+0x7ac>)
+ 800787e:	4313      	orrs	r3, r2
+ 8007880:	634b      	str	r3, [r1, #52]	; 0x34
+          /* Enable PLL1FRACEN to latch new value. */
+          __HAL_RCC_PLLFRACN_ENABLE();
+ 8007882:	4b05      	ldr	r3, [pc, #20]	; (8007898 <HAL_RCC_OscConfig+0x7ac>)
+ 8007884:	6adb      	ldr	r3, [r3, #44]	; 0x2c
+ 8007886:	4a04      	ldr	r2, [pc, #16]	; (8007898 <HAL_RCC_OscConfig+0x7ac>)
+ 8007888:	f043 0301 	orr.w	r3, r3, #1
+ 800788c:	62d3      	str	r3, [r2, #44]	; 0x2c
+        }
+      }
+    }
+  }
+  return HAL_OK;
+ 800788e:	2300      	movs	r3, #0
+}
+ 8007890:	4618      	mov	r0, r3
+ 8007892:	3730      	adds	r7, #48	; 0x30
+ 8007894:	46bd      	mov	sp, r7
+ 8007896:	bd80      	pop	{r7, pc}
+ 8007898:	58024400 	.word	0x58024400
+ 800789c:	ffff0007 	.word	0xffff0007
+
+080078a0 <HAL_RCC_ClockConfig>:
+  *         D1CPRE[3:0] bits to ensure that  Domain1 core clock not exceed the maximum allowed frequency
+  *         (for more details refer to section above "Initialization/de-initialization functions")
+  * @retval None
+  */
+HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t FLatency)
+{
+ 80078a0:	b580      	push	{r7, lr}
+ 80078a2:	b086      	sub	sp, #24
+ 80078a4:	af00      	add	r7, sp, #0
+ 80078a6:	6078      	str	r0, [r7, #4]
+ 80078a8:	6039      	str	r1, [r7, #0]
+  HAL_StatusTypeDef halstatus;
+  uint32_t tickstart;
+  uint32_t common_system_clock;
+
+  /* Check Null pointer */
+  if (RCC_ClkInitStruct == NULL)
+ 80078aa:	687b      	ldr	r3, [r7, #4]
+ 80078ac:	2b00      	cmp	r3, #0
+ 80078ae:	d101      	bne.n	80078b4 <HAL_RCC_ClockConfig+0x14>
+  {
+    return HAL_ERROR;
+ 80078b0:	2301      	movs	r3, #1
+ 80078b2:	e19c      	b.n	8007bee <HAL_RCC_ClockConfig+0x34e>
+  /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
+    must be correctly programmed according to the frequency of the CPU clock
+    (HCLK) and the supply voltage of the device. */
+
+  /* Increasing the CPU frequency */
+  if (FLatency > __HAL_FLASH_GET_LATENCY())
+ 80078b4:	4b8a      	ldr	r3, [pc, #552]	; (8007ae0 <HAL_RCC_ClockConfig+0x240>)
+ 80078b6:	681b      	ldr	r3, [r3, #0]
+ 80078b8:	f003 030f 	and.w	r3, r3, #15
+ 80078bc:	683a      	ldr	r2, [r7, #0]
+ 80078be:	429a      	cmp	r2, r3
+ 80078c0:	d910      	bls.n	80078e4 <HAL_RCC_ClockConfig+0x44>
+  {
+    /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
+    __HAL_FLASH_SET_LATENCY(FLatency);
+ 80078c2:	4b87      	ldr	r3, [pc, #540]	; (8007ae0 <HAL_RCC_ClockConfig+0x240>)
+ 80078c4:	681b      	ldr	r3, [r3, #0]
+ 80078c6:	f023 020f 	bic.w	r2, r3, #15
+ 80078ca:	4985      	ldr	r1, [pc, #532]	; (8007ae0 <HAL_RCC_ClockConfig+0x240>)
+ 80078cc:	683b      	ldr	r3, [r7, #0]
+ 80078ce:	4313      	orrs	r3, r2
+ 80078d0:	600b      	str	r3, [r1, #0]
+
+    /* Check that the new number of wait states is taken into account to access the Flash
+    memory by reading the FLASH_ACR register */
+    if (__HAL_FLASH_GET_LATENCY() != FLatency)
+ 80078d2:	4b83      	ldr	r3, [pc, #524]	; (8007ae0 <HAL_RCC_ClockConfig+0x240>)
+ 80078d4:	681b      	ldr	r3, [r3, #0]
+ 80078d6:	f003 030f 	and.w	r3, r3, #15
+ 80078da:	683a      	ldr	r2, [r7, #0]
+ 80078dc:	429a      	cmp	r2, r3
+ 80078de:	d001      	beq.n	80078e4 <HAL_RCC_ClockConfig+0x44>
+    {
+      return HAL_ERROR;
+ 80078e0:	2301      	movs	r3, #1
+ 80078e2:	e184      	b.n	8007bee <HAL_RCC_ClockConfig+0x34e>
+
+  }
+
+  /* Increasing the BUS frequency divider */
+  /*-------------------------- D1PCLK1/CDPCLK1 Configuration ---------------------------*/
+  if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D1PCLK1) == RCC_CLOCKTYPE_D1PCLK1)
+ 80078e4:	687b      	ldr	r3, [r7, #4]
+ 80078e6:	681b      	ldr	r3, [r3, #0]
+ 80078e8:	f003 0304 	and.w	r3, r3, #4
+ 80078ec:	2b00      	cmp	r3, #0
+ 80078ee:	d010      	beq.n	8007912 <HAL_RCC_ClockConfig+0x72>
+  {
+#if defined (RCC_D1CFGR_D1PPRE)
+    if ((RCC_ClkInitStruct->APB3CLKDivider) > (RCC->D1CFGR & RCC_D1CFGR_D1PPRE))
+ 80078f0:	687b      	ldr	r3, [r7, #4]
+ 80078f2:	691a      	ldr	r2, [r3, #16]
+ 80078f4:	4b7b      	ldr	r3, [pc, #492]	; (8007ae4 <HAL_RCC_ClockConfig+0x244>)
+ 80078f6:	699b      	ldr	r3, [r3, #24]
+ 80078f8:	f003 0370 	and.w	r3, r3, #112	; 0x70
+ 80078fc:	429a      	cmp	r2, r3
+ 80078fe:	d908      	bls.n	8007912 <HAL_RCC_ClockConfig+0x72>
+    {
+      assert_param(IS_RCC_D1PCLK1(RCC_ClkInitStruct->APB3CLKDivider));
+      MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1PPRE, RCC_ClkInitStruct->APB3CLKDivider);
+ 8007900:	4b78      	ldr	r3, [pc, #480]	; (8007ae4 <HAL_RCC_ClockConfig+0x244>)
+ 8007902:	699b      	ldr	r3, [r3, #24]
+ 8007904:	f023 0270 	bic.w	r2, r3, #112	; 0x70
+ 8007908:	687b      	ldr	r3, [r7, #4]
+ 800790a:	691b      	ldr	r3, [r3, #16]
+ 800790c:	4975      	ldr	r1, [pc, #468]	; (8007ae4 <HAL_RCC_ClockConfig+0x244>)
+ 800790e:	4313      	orrs	r3, r2
+ 8007910:	618b      	str	r3, [r1, #24]
+    }
+#endif
+  }
+
+  /*-------------------------- PCLK1 Configuration ---------------------------*/
+  if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
+ 8007912:	687b      	ldr	r3, [r7, #4]
+ 8007914:	681b      	ldr	r3, [r3, #0]
+ 8007916:	f003 0308 	and.w	r3, r3, #8
+ 800791a:	2b00      	cmp	r3, #0
+ 800791c:	d010      	beq.n	8007940 <HAL_RCC_ClockConfig+0xa0>
+  {
+#if defined (RCC_D2CFGR_D2PPRE1)
+    if ((RCC_ClkInitStruct->APB1CLKDivider) > (RCC->D2CFGR & RCC_D2CFGR_D2PPRE1))
+ 800791e:	687b      	ldr	r3, [r7, #4]
+ 8007920:	695a      	ldr	r2, [r3, #20]
+ 8007922:	4b70      	ldr	r3, [pc, #448]	; (8007ae4 <HAL_RCC_ClockConfig+0x244>)
+ 8007924:	69db      	ldr	r3, [r3, #28]
+ 8007926:	f003 0370 	and.w	r3, r3, #112	; 0x70
+ 800792a:	429a      	cmp	r2, r3
+ 800792c:	d908      	bls.n	8007940 <HAL_RCC_ClockConfig+0xa0>
+    {
+      assert_param(IS_RCC_PCLK1(RCC_ClkInitStruct->APB1CLKDivider));
+      MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE1, (RCC_ClkInitStruct->APB1CLKDivider));
+ 800792e:	4b6d      	ldr	r3, [pc, #436]	; (8007ae4 <HAL_RCC_ClockConfig+0x244>)
+ 8007930:	69db      	ldr	r3, [r3, #28]
+ 8007932:	f023 0270 	bic.w	r2, r3, #112	; 0x70
+ 8007936:	687b      	ldr	r3, [r7, #4]
+ 8007938:	695b      	ldr	r3, [r3, #20]
+ 800793a:	496a      	ldr	r1, [pc, #424]	; (8007ae4 <HAL_RCC_ClockConfig+0x244>)
+ 800793c:	4313      	orrs	r3, r2
+ 800793e:	61cb      	str	r3, [r1, #28]
+      MODIFY_REG(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE1, (RCC_ClkInitStruct->APB1CLKDivider));
+    }
+#endif
+  }
+  /*-------------------------- PCLK2 Configuration ---------------------------*/
+  if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
+ 8007940:	687b      	ldr	r3, [r7, #4]
+ 8007942:	681b      	ldr	r3, [r3, #0]
+ 8007944:	f003 0310 	and.w	r3, r3, #16
+ 8007948:	2b00      	cmp	r3, #0
+ 800794a:	d010      	beq.n	800796e <HAL_RCC_ClockConfig+0xce>
+  {
+#if defined(RCC_D2CFGR_D2PPRE2)
+    if ((RCC_ClkInitStruct->APB2CLKDivider) > (RCC->D2CFGR & RCC_D2CFGR_D2PPRE2))
+ 800794c:	687b      	ldr	r3, [r7, #4]
+ 800794e:	699a      	ldr	r2, [r3, #24]
+ 8007950:	4b64      	ldr	r3, [pc, #400]	; (8007ae4 <HAL_RCC_ClockConfig+0x244>)
+ 8007952:	69db      	ldr	r3, [r3, #28]
+ 8007954:	f403 63e0 	and.w	r3, r3, #1792	; 0x700
+ 8007958:	429a      	cmp	r2, r3
+ 800795a:	d908      	bls.n	800796e <HAL_RCC_ClockConfig+0xce>
+    {
+      assert_param(IS_RCC_PCLK2(RCC_ClkInitStruct->APB2CLKDivider));
+      MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE2, (RCC_ClkInitStruct->APB2CLKDivider));
+ 800795c:	4b61      	ldr	r3, [pc, #388]	; (8007ae4 <HAL_RCC_ClockConfig+0x244>)
+ 800795e:	69db      	ldr	r3, [r3, #28]
+ 8007960:	f423 62e0 	bic.w	r2, r3, #1792	; 0x700
+ 8007964:	687b      	ldr	r3, [r7, #4]
+ 8007966:	699b      	ldr	r3, [r3, #24]
+ 8007968:	495e      	ldr	r1, [pc, #376]	; (8007ae4 <HAL_RCC_ClockConfig+0x244>)
+ 800796a:	4313      	orrs	r3, r2
+ 800796c:	61cb      	str	r3, [r1, #28]
+    }
+#endif
+  }
+
+  /*-------------------------- D3PCLK1 Configuration ---------------------------*/
+  if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D3PCLK1) == RCC_CLOCKTYPE_D3PCLK1)
+ 800796e:	687b      	ldr	r3, [r7, #4]
+ 8007970:	681b      	ldr	r3, [r3, #0]
+ 8007972:	f003 0320 	and.w	r3, r3, #32
+ 8007976:	2b00      	cmp	r3, #0
+ 8007978:	d010      	beq.n	800799c <HAL_RCC_ClockConfig+0xfc>
+  {
+#if defined(RCC_D3CFGR_D3PPRE)
+    if ((RCC_ClkInitStruct->APB4CLKDivider) > (RCC->D3CFGR & RCC_D3CFGR_D3PPRE))
+ 800797a:	687b      	ldr	r3, [r7, #4]
+ 800797c:	69da      	ldr	r2, [r3, #28]
+ 800797e:	4b59      	ldr	r3, [pc, #356]	; (8007ae4 <HAL_RCC_ClockConfig+0x244>)
+ 8007980:	6a1b      	ldr	r3, [r3, #32]
+ 8007982:	f003 0370 	and.w	r3, r3, #112	; 0x70
+ 8007986:	429a      	cmp	r2, r3
+ 8007988:	d908      	bls.n	800799c <HAL_RCC_ClockConfig+0xfc>
+    {
+      assert_param(IS_RCC_D3PCLK1(RCC_ClkInitStruct->APB4CLKDivider));
+      MODIFY_REG(RCC->D3CFGR, RCC_D3CFGR_D3PPRE, (RCC_ClkInitStruct->APB4CLKDivider));
+ 800798a:	4b56      	ldr	r3, [pc, #344]	; (8007ae4 <HAL_RCC_ClockConfig+0x244>)
+ 800798c:	6a1b      	ldr	r3, [r3, #32]
+ 800798e:	f023 0270 	bic.w	r2, r3, #112	; 0x70
+ 8007992:	687b      	ldr	r3, [r7, #4]
+ 8007994:	69db      	ldr	r3, [r3, #28]
+ 8007996:	4953      	ldr	r1, [pc, #332]	; (8007ae4 <HAL_RCC_ClockConfig+0x244>)
+ 8007998:	4313      	orrs	r3, r2
+ 800799a:	620b      	str	r3, [r1, #32]
+    }
+#endif
+  }
+
+  /*-------------------------- HCLK Configuration --------------------------*/
+  if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
+ 800799c:	687b      	ldr	r3, [r7, #4]
+ 800799e:	681b      	ldr	r3, [r3, #0]
+ 80079a0:	f003 0302 	and.w	r3, r3, #2
+ 80079a4:	2b00      	cmp	r3, #0
+ 80079a6:	d010      	beq.n	80079ca <HAL_RCC_ClockConfig+0x12a>
+  {
+#if defined (RCC_D1CFGR_HPRE)
+    if ((RCC_ClkInitStruct->AHBCLKDivider) > (RCC->D1CFGR & RCC_D1CFGR_HPRE))
+ 80079a8:	687b      	ldr	r3, [r7, #4]
+ 80079aa:	68da      	ldr	r2, [r3, #12]
+ 80079ac:	4b4d      	ldr	r3, [pc, #308]	; (8007ae4 <HAL_RCC_ClockConfig+0x244>)
+ 80079ae:	699b      	ldr	r3, [r3, #24]
+ 80079b0:	f003 030f 	and.w	r3, r3, #15
+ 80079b4:	429a      	cmp	r2, r3
+ 80079b6:	d908      	bls.n	80079ca <HAL_RCC_ClockConfig+0x12a>
+    {
+      /* Set the new HCLK clock divider */
+      assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
+      MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
+ 80079b8:	4b4a      	ldr	r3, [pc, #296]	; (8007ae4 <HAL_RCC_ClockConfig+0x244>)
+ 80079ba:	699b      	ldr	r3, [r3, #24]
+ 80079bc:	f023 020f 	bic.w	r2, r3, #15
+ 80079c0:	687b      	ldr	r3, [r7, #4]
+ 80079c2:	68db      	ldr	r3, [r3, #12]
+ 80079c4:	4947      	ldr	r1, [pc, #284]	; (8007ae4 <HAL_RCC_ClockConfig+0x244>)
+ 80079c6:	4313      	orrs	r3, r2
+ 80079c8:	618b      	str	r3, [r1, #24]
+    }
+#endif
+  }
+
+  /*------------------------- SYSCLK Configuration -------------------------*/
+  if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
+ 80079ca:	687b      	ldr	r3, [r7, #4]
+ 80079cc:	681b      	ldr	r3, [r3, #0]
+ 80079ce:	f003 0301 	and.w	r3, r3, #1
+ 80079d2:	2b00      	cmp	r3, #0
+ 80079d4:	d055      	beq.n	8007a82 <HAL_RCC_ClockConfig+0x1e2>
+  {
+    assert_param(IS_RCC_SYSCLK(RCC_ClkInitStruct->SYSCLKDivider));
+    assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
+#if defined(RCC_D1CFGR_D1CPRE)
+    MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1CPRE, RCC_ClkInitStruct->SYSCLKDivider);
+ 80079d6:	4b43      	ldr	r3, [pc, #268]	; (8007ae4 <HAL_RCC_ClockConfig+0x244>)
+ 80079d8:	699b      	ldr	r3, [r3, #24]
+ 80079da:	f423 6270 	bic.w	r2, r3, #3840	; 0xf00
+ 80079de:	687b      	ldr	r3, [r7, #4]
+ 80079e0:	689b      	ldr	r3, [r3, #8]
+ 80079e2:	4940      	ldr	r1, [pc, #256]	; (8007ae4 <HAL_RCC_ClockConfig+0x244>)
+ 80079e4:	4313      	orrs	r3, r2
+ 80079e6:	618b      	str	r3, [r1, #24]
+#else
+    MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_CDCPRE, RCC_ClkInitStruct->SYSCLKDivider);
+#endif
+    /* HSE is selected as System Clock Source */
+    if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
+ 80079e8:	687b      	ldr	r3, [r7, #4]
+ 80079ea:	685b      	ldr	r3, [r3, #4]
+ 80079ec:	2b02      	cmp	r3, #2
+ 80079ee:	d107      	bne.n	8007a00 <HAL_RCC_ClockConfig+0x160>
+    {
+      /* Check the HSE ready flag */
+      if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U)
+ 80079f0:	4b3c      	ldr	r3, [pc, #240]	; (8007ae4 <HAL_RCC_ClockConfig+0x244>)
+ 80079f2:	681b      	ldr	r3, [r3, #0]
+ 80079f4:	f403 3300 	and.w	r3, r3, #131072	; 0x20000
+ 80079f8:	2b00      	cmp	r3, #0
+ 80079fa:	d121      	bne.n	8007a40 <HAL_RCC_ClockConfig+0x1a0>
+      {
+        return HAL_ERROR;
+ 80079fc:	2301      	movs	r3, #1
+ 80079fe:	e0f6      	b.n	8007bee <HAL_RCC_ClockConfig+0x34e>
+      }
+    }
+    /* PLL is selected as System Clock Source */
+    else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
+ 8007a00:	687b      	ldr	r3, [r7, #4]
+ 8007a02:	685b      	ldr	r3, [r3, #4]
+ 8007a04:	2b03      	cmp	r3, #3
+ 8007a06:	d107      	bne.n	8007a18 <HAL_RCC_ClockConfig+0x178>
+    {
+      /* Check the PLL ready flag */
+      if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U)
+ 8007a08:	4b36      	ldr	r3, [pc, #216]	; (8007ae4 <HAL_RCC_ClockConfig+0x244>)
+ 8007a0a:	681b      	ldr	r3, [r3, #0]
+ 8007a0c:	f003 7300 	and.w	r3, r3, #33554432	; 0x2000000
+ 8007a10:	2b00      	cmp	r3, #0
+ 8007a12:	d115      	bne.n	8007a40 <HAL_RCC_ClockConfig+0x1a0>
+      {
+        return HAL_ERROR;
+ 8007a14:	2301      	movs	r3, #1
+ 8007a16:	e0ea      	b.n	8007bee <HAL_RCC_ClockConfig+0x34e>
+      }
+    }
+    /* CSI is selected as System Clock Source */
+    else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_CSI)
+ 8007a18:	687b      	ldr	r3, [r7, #4]
+ 8007a1a:	685b      	ldr	r3, [r3, #4]
+ 8007a1c:	2b01      	cmp	r3, #1
+ 8007a1e:	d107      	bne.n	8007a30 <HAL_RCC_ClockConfig+0x190>
+    {
+      /* Check the PLL ready flag */
+      if (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) == 0U)
+ 8007a20:	4b30      	ldr	r3, [pc, #192]	; (8007ae4 <HAL_RCC_ClockConfig+0x244>)
+ 8007a22:	681b      	ldr	r3, [r3, #0]
+ 8007a24:	f403 7380 	and.w	r3, r3, #256	; 0x100
+ 8007a28:	2b00      	cmp	r3, #0
+ 8007a2a:	d109      	bne.n	8007a40 <HAL_RCC_ClockConfig+0x1a0>
+      {
+        return HAL_ERROR;
+ 8007a2c:	2301      	movs	r3, #1
+ 8007a2e:	e0de      	b.n	8007bee <HAL_RCC_ClockConfig+0x34e>
+    }
+    /* HSI is selected as System Clock Source */
+    else
+    {
+      /* Check the HSI ready flag */
+      if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U)
+ 8007a30:	4b2c      	ldr	r3, [pc, #176]	; (8007ae4 <HAL_RCC_ClockConfig+0x244>)
+ 8007a32:	681b      	ldr	r3, [r3, #0]
+ 8007a34:	f003 0304 	and.w	r3, r3, #4
+ 8007a38:	2b00      	cmp	r3, #0
+ 8007a3a:	d101      	bne.n	8007a40 <HAL_RCC_ClockConfig+0x1a0>
+      {
+        return HAL_ERROR;
+ 8007a3c:	2301      	movs	r3, #1
+ 8007a3e:	e0d6      	b.n	8007bee <HAL_RCC_ClockConfig+0x34e>
+      }
+    }
+    MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);
+ 8007a40:	4b28      	ldr	r3, [pc, #160]	; (8007ae4 <HAL_RCC_ClockConfig+0x244>)
+ 8007a42:	691b      	ldr	r3, [r3, #16]
+ 8007a44:	f023 0207 	bic.w	r2, r3, #7
+ 8007a48:	687b      	ldr	r3, [r7, #4]
+ 8007a4a:	685b      	ldr	r3, [r3, #4]
+ 8007a4c:	4925      	ldr	r1, [pc, #148]	; (8007ae4 <HAL_RCC_ClockConfig+0x244>)
+ 8007a4e:	4313      	orrs	r3, r2
+ 8007a50:	610b      	str	r3, [r1, #16]
+
+    /* Get Start Tick*/
+    tickstart = HAL_GetTick();
+ 8007a52:	f7fa fc87 	bl	8002364 <HAL_GetTick>
+ 8007a56:	6178      	str	r0, [r7, #20]
+
+    while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
+ 8007a58:	e00a      	b.n	8007a70 <HAL_RCC_ClockConfig+0x1d0>
+    {
+      if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
+ 8007a5a:	f7fa fc83 	bl	8002364 <HAL_GetTick>
+ 8007a5e:	4602      	mov	r2, r0
+ 8007a60:	697b      	ldr	r3, [r7, #20]
+ 8007a62:	1ad3      	subs	r3, r2, r3
+ 8007a64:	f241 3288 	movw	r2, #5000	; 0x1388
+ 8007a68:	4293      	cmp	r3, r2
+ 8007a6a:	d901      	bls.n	8007a70 <HAL_RCC_ClockConfig+0x1d0>
+      {
+        return HAL_TIMEOUT;
+ 8007a6c:	2303      	movs	r3, #3
+ 8007a6e:	e0be      	b.n	8007bee <HAL_RCC_ClockConfig+0x34e>
+    while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
+ 8007a70:	4b1c      	ldr	r3, [pc, #112]	; (8007ae4 <HAL_RCC_ClockConfig+0x244>)
+ 8007a72:	691b      	ldr	r3, [r3, #16]
+ 8007a74:	f003 0238 	and.w	r2, r3, #56	; 0x38
+ 8007a78:	687b      	ldr	r3, [r7, #4]
+ 8007a7a:	685b      	ldr	r3, [r3, #4]
+ 8007a7c:	00db      	lsls	r3, r3, #3
+ 8007a7e:	429a      	cmp	r2, r3
+ 8007a80:	d1eb      	bne.n	8007a5a <HAL_RCC_ClockConfig+0x1ba>
+
+  }
+
+  /* Decreasing the BUS frequency divider */
+  /*-------------------------- HCLK Configuration --------------------------*/
+  if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
+ 8007a82:	687b      	ldr	r3, [r7, #4]
+ 8007a84:	681b      	ldr	r3, [r3, #0]
+ 8007a86:	f003 0302 	and.w	r3, r3, #2
+ 8007a8a:	2b00      	cmp	r3, #0
+ 8007a8c:	d010      	beq.n	8007ab0 <HAL_RCC_ClockConfig+0x210>
+  {
+#if defined(RCC_D1CFGR_HPRE)
+    if ((RCC_ClkInitStruct->AHBCLKDivider) < (RCC->D1CFGR & RCC_D1CFGR_HPRE))
+ 8007a8e:	687b      	ldr	r3, [r7, #4]
+ 8007a90:	68da      	ldr	r2, [r3, #12]
+ 8007a92:	4b14      	ldr	r3, [pc, #80]	; (8007ae4 <HAL_RCC_ClockConfig+0x244>)
+ 8007a94:	699b      	ldr	r3, [r3, #24]
+ 8007a96:	f003 030f 	and.w	r3, r3, #15
+ 8007a9a:	429a      	cmp	r2, r3
+ 8007a9c:	d208      	bcs.n	8007ab0 <HAL_RCC_ClockConfig+0x210>
+    {
+      /* Set the new HCLK clock divider */
+      assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
+      MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
+ 8007a9e:	4b11      	ldr	r3, [pc, #68]	; (8007ae4 <HAL_RCC_ClockConfig+0x244>)
+ 8007aa0:	699b      	ldr	r3, [r3, #24]
+ 8007aa2:	f023 020f 	bic.w	r2, r3, #15
+ 8007aa6:	687b      	ldr	r3, [r7, #4]
+ 8007aa8:	68db      	ldr	r3, [r3, #12]
+ 8007aaa:	490e      	ldr	r1, [pc, #56]	; (8007ae4 <HAL_RCC_ClockConfig+0x244>)
+ 8007aac:	4313      	orrs	r3, r2
+ 8007aae:	618b      	str	r3, [r1, #24]
+    }
+#endif
+  }
+
+  /* Decreasing the number of wait states because of lower CPU frequency */
+  if (FLatency < __HAL_FLASH_GET_LATENCY())
+ 8007ab0:	4b0b      	ldr	r3, [pc, #44]	; (8007ae0 <HAL_RCC_ClockConfig+0x240>)
+ 8007ab2:	681b      	ldr	r3, [r3, #0]
+ 8007ab4:	f003 030f 	and.w	r3, r3, #15
+ 8007ab8:	683a      	ldr	r2, [r7, #0]
+ 8007aba:	429a      	cmp	r2, r3
+ 8007abc:	d214      	bcs.n	8007ae8 <HAL_RCC_ClockConfig+0x248>
+  {
+    /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
+    __HAL_FLASH_SET_LATENCY(FLatency);
+ 8007abe:	4b08      	ldr	r3, [pc, #32]	; (8007ae0 <HAL_RCC_ClockConfig+0x240>)
+ 8007ac0:	681b      	ldr	r3, [r3, #0]
+ 8007ac2:	f023 020f 	bic.w	r2, r3, #15
+ 8007ac6:	4906      	ldr	r1, [pc, #24]	; (8007ae0 <HAL_RCC_ClockConfig+0x240>)
+ 8007ac8:	683b      	ldr	r3, [r7, #0]
+ 8007aca:	4313      	orrs	r3, r2
+ 8007acc:	600b      	str	r3, [r1, #0]
+
+    /* Check that the new number of wait states is taken into account to access the Flash
+    memory by reading the FLASH_ACR register */
+    if (__HAL_FLASH_GET_LATENCY() != FLatency)
+ 8007ace:	4b04      	ldr	r3, [pc, #16]	; (8007ae0 <HAL_RCC_ClockConfig+0x240>)
+ 8007ad0:	681b      	ldr	r3, [r3, #0]
+ 8007ad2:	f003 030f 	and.w	r3, r3, #15
+ 8007ad6:	683a      	ldr	r2, [r7, #0]
+ 8007ad8:	429a      	cmp	r2, r3
+ 8007ada:	d005      	beq.n	8007ae8 <HAL_RCC_ClockConfig+0x248>
+    {
+      return HAL_ERROR;
+ 8007adc:	2301      	movs	r3, #1
+ 8007ade:	e086      	b.n	8007bee <HAL_RCC_ClockConfig+0x34e>
+ 8007ae0:	52002000 	.word	0x52002000
+ 8007ae4:	58024400 	.word	0x58024400
+    }
+  }
+
+  /*-------------------------- D1PCLK1/CDPCLK Configuration ---------------------------*/
+  if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D1PCLK1) == RCC_CLOCKTYPE_D1PCLK1)
+ 8007ae8:	687b      	ldr	r3, [r7, #4]
+ 8007aea:	681b      	ldr	r3, [r3, #0]
+ 8007aec:	f003 0304 	and.w	r3, r3, #4
+ 8007af0:	2b00      	cmp	r3, #0
+ 8007af2:	d010      	beq.n	8007b16 <HAL_RCC_ClockConfig+0x276>
+  {
+#if defined(RCC_D1CFGR_D1PPRE)
+    if ((RCC_ClkInitStruct->APB3CLKDivider) < (RCC->D1CFGR & RCC_D1CFGR_D1PPRE))
+ 8007af4:	687b      	ldr	r3, [r7, #4]
+ 8007af6:	691a      	ldr	r2, [r3, #16]
+ 8007af8:	4b3f      	ldr	r3, [pc, #252]	; (8007bf8 <HAL_RCC_ClockConfig+0x358>)
+ 8007afa:	699b      	ldr	r3, [r3, #24]
+ 8007afc:	f003 0370 	and.w	r3, r3, #112	; 0x70
+ 8007b00:	429a      	cmp	r2, r3
+ 8007b02:	d208      	bcs.n	8007b16 <HAL_RCC_ClockConfig+0x276>
+    {
+      assert_param(IS_RCC_D1PCLK1(RCC_ClkInitStruct->APB3CLKDivider));
+      MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1PPRE, RCC_ClkInitStruct->APB3CLKDivider);
+ 8007b04:	4b3c      	ldr	r3, [pc, #240]	; (8007bf8 <HAL_RCC_ClockConfig+0x358>)
+ 8007b06:	699b      	ldr	r3, [r3, #24]
+ 8007b08:	f023 0270 	bic.w	r2, r3, #112	; 0x70
+ 8007b0c:	687b      	ldr	r3, [r7, #4]
+ 8007b0e:	691b      	ldr	r3, [r3, #16]
+ 8007b10:	4939      	ldr	r1, [pc, #228]	; (8007bf8 <HAL_RCC_ClockConfig+0x358>)
+ 8007b12:	4313      	orrs	r3, r2
+ 8007b14:	618b      	str	r3, [r1, #24]
+    }
+#endif
+  }
+
+  /*-------------------------- PCLK1 Configuration ---------------------------*/
+  if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
+ 8007b16:	687b      	ldr	r3, [r7, #4]
+ 8007b18:	681b      	ldr	r3, [r3, #0]
+ 8007b1a:	f003 0308 	and.w	r3, r3, #8
+ 8007b1e:	2b00      	cmp	r3, #0
+ 8007b20:	d010      	beq.n	8007b44 <HAL_RCC_ClockConfig+0x2a4>
+  {
+#if defined(RCC_D2CFGR_D2PPRE1)
+    if ((RCC_ClkInitStruct->APB1CLKDivider) < (RCC->D2CFGR & RCC_D2CFGR_D2PPRE1))
+ 8007b22:	687b      	ldr	r3, [r7, #4]
+ 8007b24:	695a      	ldr	r2, [r3, #20]
+ 8007b26:	4b34      	ldr	r3, [pc, #208]	; (8007bf8 <HAL_RCC_ClockConfig+0x358>)
+ 8007b28:	69db      	ldr	r3, [r3, #28]
+ 8007b2a:	f003 0370 	and.w	r3, r3, #112	; 0x70
+ 8007b2e:	429a      	cmp	r2, r3
+ 8007b30:	d208      	bcs.n	8007b44 <HAL_RCC_ClockConfig+0x2a4>
+    {
+      assert_param(IS_RCC_PCLK1(RCC_ClkInitStruct->APB1CLKDivider));
+      MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE1, (RCC_ClkInitStruct->APB1CLKDivider));
+ 8007b32:	4b31      	ldr	r3, [pc, #196]	; (8007bf8 <HAL_RCC_ClockConfig+0x358>)
+ 8007b34:	69db      	ldr	r3, [r3, #28]
+ 8007b36:	f023 0270 	bic.w	r2, r3, #112	; 0x70
+ 8007b3a:	687b      	ldr	r3, [r7, #4]
+ 8007b3c:	695b      	ldr	r3, [r3, #20]
+ 8007b3e:	492e      	ldr	r1, [pc, #184]	; (8007bf8 <HAL_RCC_ClockConfig+0x358>)
+ 8007b40:	4313      	orrs	r3, r2
+ 8007b42:	61cb      	str	r3, [r1, #28]
+    }
+#endif
+  }
+
+  /*-------------------------- PCLK2 Configuration ---------------------------*/
+  if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
+ 8007b44:	687b      	ldr	r3, [r7, #4]
+ 8007b46:	681b      	ldr	r3, [r3, #0]
+ 8007b48:	f003 0310 	and.w	r3, r3, #16
+ 8007b4c:	2b00      	cmp	r3, #0
+ 8007b4e:	d010      	beq.n	8007b72 <HAL_RCC_ClockConfig+0x2d2>
+  {
+#if defined (RCC_D2CFGR_D2PPRE2)
+    if ((RCC_ClkInitStruct->APB2CLKDivider) < (RCC->D2CFGR & RCC_D2CFGR_D2PPRE2))
+ 8007b50:	687b      	ldr	r3, [r7, #4]
+ 8007b52:	699a      	ldr	r2, [r3, #24]
+ 8007b54:	4b28      	ldr	r3, [pc, #160]	; (8007bf8 <HAL_RCC_ClockConfig+0x358>)
+ 8007b56:	69db      	ldr	r3, [r3, #28]
+ 8007b58:	f403 63e0 	and.w	r3, r3, #1792	; 0x700
+ 8007b5c:	429a      	cmp	r2, r3
+ 8007b5e:	d208      	bcs.n	8007b72 <HAL_RCC_ClockConfig+0x2d2>
+    {
+      assert_param(IS_RCC_PCLK2(RCC_ClkInitStruct->APB2CLKDivider));
+      MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE2, (RCC_ClkInitStruct->APB2CLKDivider));
+ 8007b60:	4b25      	ldr	r3, [pc, #148]	; (8007bf8 <HAL_RCC_ClockConfig+0x358>)
+ 8007b62:	69db      	ldr	r3, [r3, #28]
+ 8007b64:	f423 62e0 	bic.w	r2, r3, #1792	; 0x700
+ 8007b68:	687b      	ldr	r3, [r7, #4]
+ 8007b6a:	699b      	ldr	r3, [r3, #24]
+ 8007b6c:	4922      	ldr	r1, [pc, #136]	; (8007bf8 <HAL_RCC_ClockConfig+0x358>)
+ 8007b6e:	4313      	orrs	r3, r2
+ 8007b70:	61cb      	str	r3, [r1, #28]
+    }
+#endif
+  }
+
+  /*-------------------------- D3PCLK1/SRDPCLK1 Configuration ---------------------------*/
+  if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D3PCLK1) == RCC_CLOCKTYPE_D3PCLK1)
+ 8007b72:	687b      	ldr	r3, [r7, #4]
+ 8007b74:	681b      	ldr	r3, [r3, #0]
+ 8007b76:	f003 0320 	and.w	r3, r3, #32
+ 8007b7a:	2b00      	cmp	r3, #0
+ 8007b7c:	d010      	beq.n	8007ba0 <HAL_RCC_ClockConfig+0x300>
+  {
+#if defined(RCC_D3CFGR_D3PPRE)
+    if ((RCC_ClkInitStruct->APB4CLKDivider) < (RCC->D3CFGR & RCC_D3CFGR_D3PPRE))
+ 8007b7e:	687b      	ldr	r3, [r7, #4]
+ 8007b80:	69da      	ldr	r2, [r3, #28]
+ 8007b82:	4b1d      	ldr	r3, [pc, #116]	; (8007bf8 <HAL_RCC_ClockConfig+0x358>)
+ 8007b84:	6a1b      	ldr	r3, [r3, #32]
+ 8007b86:	f003 0370 	and.w	r3, r3, #112	; 0x70
+ 8007b8a:	429a      	cmp	r2, r3
+ 8007b8c:	d208      	bcs.n	8007ba0 <HAL_RCC_ClockConfig+0x300>
+    {
+      assert_param(IS_RCC_D3PCLK1(RCC_ClkInitStruct->APB4CLKDivider));
+      MODIFY_REG(RCC->D3CFGR, RCC_D3CFGR_D3PPRE, (RCC_ClkInitStruct->APB4CLKDivider));
+ 8007b8e:	4b1a      	ldr	r3, [pc, #104]	; (8007bf8 <HAL_RCC_ClockConfig+0x358>)
+ 8007b90:	6a1b      	ldr	r3, [r3, #32]
+ 8007b92:	f023 0270 	bic.w	r2, r3, #112	; 0x70
+ 8007b96:	687b      	ldr	r3, [r7, #4]
+ 8007b98:	69db      	ldr	r3, [r3, #28]
+ 8007b9a:	4917      	ldr	r1, [pc, #92]	; (8007bf8 <HAL_RCC_ClockConfig+0x358>)
+ 8007b9c:	4313      	orrs	r3, r2
+ 8007b9e:	620b      	str	r3, [r1, #32]
+#endif
+  }
+
+  /* Update the SystemCoreClock global variable */
+#if defined(RCC_D1CFGR_D1CPRE)
+  common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE) >> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU);
+ 8007ba0:	f000 f834 	bl	8007c0c <HAL_RCC_GetSysClockFreq>
+ 8007ba4:	4602      	mov	r2, r0
+ 8007ba6:	4b14      	ldr	r3, [pc, #80]	; (8007bf8 <HAL_RCC_ClockConfig+0x358>)
+ 8007ba8:	699b      	ldr	r3, [r3, #24]
+ 8007baa:	0a1b      	lsrs	r3, r3, #8
+ 8007bac:	f003 030f 	and.w	r3, r3, #15
+ 8007bb0:	4912      	ldr	r1, [pc, #72]	; (8007bfc <HAL_RCC_ClockConfig+0x35c>)
+ 8007bb2:	5ccb      	ldrb	r3, [r1, r3]
+ 8007bb4:	f003 031f 	and.w	r3, r3, #31
+ 8007bb8:	fa22 f303 	lsr.w	r3, r2, r3
+ 8007bbc:	613b      	str	r3, [r7, #16]
+#else
+  common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE) >> RCC_CDCFGR1_CDCPRE_Pos]) & 0x1FU);
+#endif
+
+#if defined(RCC_D1CFGR_HPRE)
+  SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE) >> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
+ 8007bbe:	4b0e      	ldr	r3, [pc, #56]	; (8007bf8 <HAL_RCC_ClockConfig+0x358>)
+ 8007bc0:	699b      	ldr	r3, [r3, #24]
+ 8007bc2:	f003 030f 	and.w	r3, r3, #15
+ 8007bc6:	4a0d      	ldr	r2, [pc, #52]	; (8007bfc <HAL_RCC_ClockConfig+0x35c>)
+ 8007bc8:	5cd3      	ldrb	r3, [r2, r3]
+ 8007bca:	f003 031f 	and.w	r3, r3, #31
+ 8007bce:	693a      	ldr	r2, [r7, #16]
+ 8007bd0:	fa22 f303 	lsr.w	r3, r2, r3
+ 8007bd4:	4a0a      	ldr	r2, [pc, #40]	; (8007c00 <HAL_RCC_ClockConfig+0x360>)
+ 8007bd6:	6013      	str	r3, [r2, #0]
+#endif
+
+#if defined(DUAL_CORE) && defined(CORE_CM4)
+  SystemCoreClock = SystemD2Clock;
+#else
+  SystemCoreClock = common_system_clock;
+ 8007bd8:	4a0a      	ldr	r2, [pc, #40]	; (8007c04 <HAL_RCC_ClockConfig+0x364>)
+ 8007bda:	693b      	ldr	r3, [r7, #16]
+ 8007bdc:	6013      	str	r3, [r2, #0]
+#endif /* DUAL_CORE && CORE_CM4 */
+
+  /* Configure the source of time base considering new system clocks settings*/
+  halstatus = HAL_InitTick(uwTickPrio);
+ 8007bde:	4b0a      	ldr	r3, [pc, #40]	; (8007c08 <HAL_RCC_ClockConfig+0x368>)
+ 8007be0:	681b      	ldr	r3, [r3, #0]
+ 8007be2:	4618      	mov	r0, r3
+ 8007be4:	f7f9 ffdc 	bl	8001ba0 <HAL_InitTick>
+ 8007be8:	4603      	mov	r3, r0
+ 8007bea:	73fb      	strb	r3, [r7, #15]
+
+  return halstatus;
+ 8007bec:	7bfb      	ldrb	r3, [r7, #15]
+}
+ 8007bee:	4618      	mov	r0, r3
+ 8007bf0:	3718      	adds	r7, #24
+ 8007bf2:	46bd      	mov	sp, r7
+ 8007bf4:	bd80      	pop	{r7, pc}
+ 8007bf6:	bf00      	nop
+ 8007bf8:	58024400 	.word	0x58024400
+ 8007bfc:	08026b40 	.word	0x08026b40
+ 8007c00:	24000018 	.word	0x24000018
+ 8007c04:	24000014 	.word	0x24000014
+ 8007c08:	2400001c 	.word	0x2400001c
+
+08007c0c <HAL_RCC_GetSysClockFreq>:
+  *
+  *
+  * @retval SYSCLK frequency
+  */
+uint32_t HAL_RCC_GetSysClockFreq(void)
+{
+ 8007c0c:	b480      	push	{r7}
+ 8007c0e:	b089      	sub	sp, #36	; 0x24
+ 8007c10:	af00      	add	r7, sp, #0
+  float_t fracn1, pllvco;
+  uint32_t sysclockfreq;
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+
+  switch (RCC->CFGR & RCC_CFGR_SWS)
+ 8007c12:	4bb3      	ldr	r3, [pc, #716]	; (8007ee0 <HAL_RCC_GetSysClockFreq+0x2d4>)
+ 8007c14:	691b      	ldr	r3, [r3, #16]
+ 8007c16:	f003 0338 	and.w	r3, r3, #56	; 0x38
+ 8007c1a:	2b18      	cmp	r3, #24
+ 8007c1c:	f200 8155 	bhi.w	8007eca <HAL_RCC_GetSysClockFreq+0x2be>
+ 8007c20:	a201      	add	r2, pc, #4	; (adr r2, 8007c28 <HAL_RCC_GetSysClockFreq+0x1c>)
+ 8007c22:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
+ 8007c26:	bf00      	nop
+ 8007c28:	08007c8d 	.word	0x08007c8d
+ 8007c2c:	08007ecb 	.word	0x08007ecb
+ 8007c30:	08007ecb 	.word	0x08007ecb
+ 8007c34:	08007ecb 	.word	0x08007ecb
+ 8007c38:	08007ecb 	.word	0x08007ecb
+ 8007c3c:	08007ecb 	.word	0x08007ecb
+ 8007c40:	08007ecb 	.word	0x08007ecb
+ 8007c44:	08007ecb 	.word	0x08007ecb
+ 8007c48:	08007cb3 	.word	0x08007cb3
+ 8007c4c:	08007ecb 	.word	0x08007ecb
+ 8007c50:	08007ecb 	.word	0x08007ecb
+ 8007c54:	08007ecb 	.word	0x08007ecb
+ 8007c58:	08007ecb 	.word	0x08007ecb
+ 8007c5c:	08007ecb 	.word	0x08007ecb
+ 8007c60:	08007ecb 	.word	0x08007ecb
+ 8007c64:	08007ecb 	.word	0x08007ecb
+ 8007c68:	08007cb9 	.word	0x08007cb9
+ 8007c6c:	08007ecb 	.word	0x08007ecb
+ 8007c70:	08007ecb 	.word	0x08007ecb
+ 8007c74:	08007ecb 	.word	0x08007ecb
+ 8007c78:	08007ecb 	.word	0x08007ecb
+ 8007c7c:	08007ecb 	.word	0x08007ecb
+ 8007c80:	08007ecb 	.word	0x08007ecb
+ 8007c84:	08007ecb 	.word	0x08007ecb
+ 8007c88:	08007cbf 	.word	0x08007cbf
+  {
+    case RCC_CFGR_SWS_HSI:  /* HSI used as system clock source */
+
+      if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
+ 8007c8c:	4b94      	ldr	r3, [pc, #592]	; (8007ee0 <HAL_RCC_GetSysClockFreq+0x2d4>)
+ 8007c8e:	681b      	ldr	r3, [r3, #0]
+ 8007c90:	f003 0320 	and.w	r3, r3, #32
+ 8007c94:	2b00      	cmp	r3, #0
+ 8007c96:	d009      	beq.n	8007cac <HAL_RCC_GetSysClockFreq+0xa0>
+      {
+        sysclockfreq = (uint32_t)(HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
+ 8007c98:	4b91      	ldr	r3, [pc, #580]	; (8007ee0 <HAL_RCC_GetSysClockFreq+0x2d4>)
+ 8007c9a:	681b      	ldr	r3, [r3, #0]
+ 8007c9c:	08db      	lsrs	r3, r3, #3
+ 8007c9e:	f003 0303 	and.w	r3, r3, #3
+ 8007ca2:	4a90      	ldr	r2, [pc, #576]	; (8007ee4 <HAL_RCC_GetSysClockFreq+0x2d8>)
+ 8007ca4:	fa22 f303 	lsr.w	r3, r2, r3
+ 8007ca8:	61bb      	str	r3, [r7, #24]
+      else
+      {
+        sysclockfreq = (uint32_t) HSI_VALUE;
+      }
+
+      break;
+ 8007caa:	e111      	b.n	8007ed0 <HAL_RCC_GetSysClockFreq+0x2c4>
+        sysclockfreq = (uint32_t) HSI_VALUE;
+ 8007cac:	4b8d      	ldr	r3, [pc, #564]	; (8007ee4 <HAL_RCC_GetSysClockFreq+0x2d8>)
+ 8007cae:	61bb      	str	r3, [r7, #24]
+      break;
+ 8007cb0:	e10e      	b.n	8007ed0 <HAL_RCC_GetSysClockFreq+0x2c4>
+
+    case RCC_CFGR_SWS_CSI:  /* CSI used as system clock  source */
+      sysclockfreq = CSI_VALUE;
+ 8007cb2:	4b8d      	ldr	r3, [pc, #564]	; (8007ee8 <HAL_RCC_GetSysClockFreq+0x2dc>)
+ 8007cb4:	61bb      	str	r3, [r7, #24]
+      break;
+ 8007cb6:	e10b      	b.n	8007ed0 <HAL_RCC_GetSysClockFreq+0x2c4>
+
+    case RCC_CFGR_SWS_HSE:  /* HSE used as system clock  source */
+      sysclockfreq = HSE_VALUE;
+ 8007cb8:	4b8c      	ldr	r3, [pc, #560]	; (8007eec <HAL_RCC_GetSysClockFreq+0x2e0>)
+ 8007cba:	61bb      	str	r3, [r7, #24]
+      break;
+ 8007cbc:	e108      	b.n	8007ed0 <HAL_RCC_GetSysClockFreq+0x2c4>
+    case RCC_CFGR_SWS_PLL1:  /* PLL1 used as system clock  source */
+
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN
+      SYSCLK = PLL_VCO / PLLR
+      */
+      pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
+ 8007cbe:	4b88      	ldr	r3, [pc, #544]	; (8007ee0 <HAL_RCC_GetSysClockFreq+0x2d4>)
+ 8007cc0:	6a9b      	ldr	r3, [r3, #40]	; 0x28
+ 8007cc2:	f003 0303 	and.w	r3, r3, #3
+ 8007cc6:	617b      	str	r3, [r7, #20]
+      pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1) >> 4)  ;
+ 8007cc8:	4b85      	ldr	r3, [pc, #532]	; (8007ee0 <HAL_RCC_GetSysClockFreq+0x2d4>)
+ 8007cca:	6a9b      	ldr	r3, [r3, #40]	; 0x28
+ 8007ccc:	091b      	lsrs	r3, r3, #4
+ 8007cce:	f003 033f 	and.w	r3, r3, #63	; 0x3f
+ 8007cd2:	613b      	str	r3, [r7, #16]
+      pllfracen = ((RCC-> PLLCFGR & RCC_PLLCFGR_PLL1FRACEN) >> RCC_PLLCFGR_PLL1FRACEN_Pos);
+ 8007cd4:	4b82      	ldr	r3, [pc, #520]	; (8007ee0 <HAL_RCC_GetSysClockFreq+0x2d4>)
+ 8007cd6:	6adb      	ldr	r3, [r3, #44]	; 0x2c
+ 8007cd8:	f003 0301 	and.w	r3, r3, #1
+ 8007cdc:	60fb      	str	r3, [r7, #12]
+      fracn1 = (float_t)(uint32_t)(pllfracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> 3));
+ 8007cde:	4b80      	ldr	r3, [pc, #512]	; (8007ee0 <HAL_RCC_GetSysClockFreq+0x2d4>)
+ 8007ce0:	6b5b      	ldr	r3, [r3, #52]	; 0x34
+ 8007ce2:	08db      	lsrs	r3, r3, #3
+ 8007ce4:	f3c3 030c 	ubfx	r3, r3, #0, #13
+ 8007ce8:	68fa      	ldr	r2, [r7, #12]
+ 8007cea:	fb02 f303 	mul.w	r3, r2, r3
+ 8007cee:	ee07 3a90 	vmov	s15, r3
+ 8007cf2:	eef8 7a67 	vcvt.f32.u32	s15, s15
+ 8007cf6:	edc7 7a02 	vstr	s15, [r7, #8]
+
+      if (pllm != 0U)
+ 8007cfa:	693b      	ldr	r3, [r7, #16]
+ 8007cfc:	2b00      	cmp	r3, #0
+ 8007cfe:	f000 80e1 	beq.w	8007ec4 <HAL_RCC_GetSysClockFreq+0x2b8>
+ 8007d02:	697b      	ldr	r3, [r7, #20]
+ 8007d04:	2b02      	cmp	r3, #2
+ 8007d06:	f000 8083 	beq.w	8007e10 <HAL_RCC_GetSysClockFreq+0x204>
+ 8007d0a:	697b      	ldr	r3, [r7, #20]
+ 8007d0c:	2b02      	cmp	r3, #2
+ 8007d0e:	f200 80a1 	bhi.w	8007e54 <HAL_RCC_GetSysClockFreq+0x248>
+ 8007d12:	697b      	ldr	r3, [r7, #20]
+ 8007d14:	2b00      	cmp	r3, #0
+ 8007d16:	d003      	beq.n	8007d20 <HAL_RCC_GetSysClockFreq+0x114>
+ 8007d18:	697b      	ldr	r3, [r7, #20]
+ 8007d1a:	2b01      	cmp	r3, #1
+ 8007d1c:	d056      	beq.n	8007dcc <HAL_RCC_GetSysClockFreq+0x1c0>
+ 8007d1e:	e099      	b.n	8007e54 <HAL_RCC_GetSysClockFreq+0x248>
+      {
+        switch (pllsource)
+        {
+          case RCC_PLLSOURCE_HSI:  /* HSI used as PLL clock source */
+
+            if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
+ 8007d20:	4b6f      	ldr	r3, [pc, #444]	; (8007ee0 <HAL_RCC_GetSysClockFreq+0x2d4>)
+ 8007d22:	681b      	ldr	r3, [r3, #0]
+ 8007d24:	f003 0320 	and.w	r3, r3, #32
+ 8007d28:	2b00      	cmp	r3, #0
+ 8007d2a:	d02d      	beq.n	8007d88 <HAL_RCC_GetSysClockFreq+0x17c>
+            {
+              hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
+ 8007d2c:	4b6c      	ldr	r3, [pc, #432]	; (8007ee0 <HAL_RCC_GetSysClockFreq+0x2d4>)
+ 8007d2e:	681b      	ldr	r3, [r3, #0]
+ 8007d30:	08db      	lsrs	r3, r3, #3
+ 8007d32:	f003 0303 	and.w	r3, r3, #3
+ 8007d36:	4a6b      	ldr	r2, [pc, #428]	; (8007ee4 <HAL_RCC_GetSysClockFreq+0x2d8>)
+ 8007d38:	fa22 f303 	lsr.w	r3, r2, r3
+ 8007d3c:	607b      	str	r3, [r7, #4]
+              pllvco = ((float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
+ 8007d3e:	687b      	ldr	r3, [r7, #4]
+ 8007d40:	ee07 3a90 	vmov	s15, r3
+ 8007d44:	eef8 6a67 	vcvt.f32.u32	s13, s15
+ 8007d48:	693b      	ldr	r3, [r7, #16]
+ 8007d4a:	ee07 3a90 	vmov	s15, r3
+ 8007d4e:	eef8 7a67 	vcvt.f32.u32	s15, s15
+ 8007d52:	ee86 7aa7 	vdiv.f32	s14, s13, s15
+ 8007d56:	4b62      	ldr	r3, [pc, #392]	; (8007ee0 <HAL_RCC_GetSysClockFreq+0x2d4>)
+ 8007d58:	6b1b      	ldr	r3, [r3, #48]	; 0x30
+ 8007d5a:	f3c3 0308 	ubfx	r3, r3, #0, #9
+ 8007d5e:	ee07 3a90 	vmov	s15, r3
+ 8007d62:	eef8 6a67 	vcvt.f32.u32	s13, s15
+ 8007d66:	ed97 6a02 	vldr	s12, [r7, #8]
+ 8007d6a:	eddf 5a61 	vldr	s11, [pc, #388]	; 8007ef0 <HAL_RCC_GetSysClockFreq+0x2e4>
+ 8007d6e:	eec6 7a25 	vdiv.f32	s15, s12, s11
+ 8007d72:	ee76 7aa7 	vadd.f32	s15, s13, s15
+ 8007d76:	eef7 6a00 	vmov.f32	s13, #112	; 0x3f800000  1.0
+ 8007d7a:	ee77 7aa6 	vadd.f32	s15, s15, s13
+ 8007d7e:	ee67 7a27 	vmul.f32	s15, s14, s15
+ 8007d82:	edc7 7a07 	vstr	s15, [r7, #28]
+            }
+            else
+            {
+              pllvco = ((float_t)HSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
+            }
+            break;
+ 8007d86:	e087      	b.n	8007e98 <HAL_RCC_GetSysClockFreq+0x28c>
+              pllvco = ((float_t)HSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
+ 8007d88:	693b      	ldr	r3, [r7, #16]
+ 8007d8a:	ee07 3a90 	vmov	s15, r3
+ 8007d8e:	eef8 7a67 	vcvt.f32.u32	s15, s15
+ 8007d92:	eddf 6a58 	vldr	s13, [pc, #352]	; 8007ef4 <HAL_RCC_GetSysClockFreq+0x2e8>
+ 8007d96:	ee86 7aa7 	vdiv.f32	s14, s13, s15
+ 8007d9a:	4b51      	ldr	r3, [pc, #324]	; (8007ee0 <HAL_RCC_GetSysClockFreq+0x2d4>)
+ 8007d9c:	6b1b      	ldr	r3, [r3, #48]	; 0x30
+ 8007d9e:	f3c3 0308 	ubfx	r3, r3, #0, #9
+ 8007da2:	ee07 3a90 	vmov	s15, r3
+ 8007da6:	eef8 6a67 	vcvt.f32.u32	s13, s15
+ 8007daa:	ed97 6a02 	vldr	s12, [r7, #8]
+ 8007dae:	eddf 5a50 	vldr	s11, [pc, #320]	; 8007ef0 <HAL_RCC_GetSysClockFreq+0x2e4>
+ 8007db2:	eec6 7a25 	vdiv.f32	s15, s12, s11
+ 8007db6:	ee76 7aa7 	vadd.f32	s15, s13, s15
+ 8007dba:	eef7 6a00 	vmov.f32	s13, #112	; 0x3f800000  1.0
+ 8007dbe:	ee77 7aa6 	vadd.f32	s15, s15, s13
+ 8007dc2:	ee67 7a27 	vmul.f32	s15, s14, s15
+ 8007dc6:	edc7 7a07 	vstr	s15, [r7, #28]
+            break;
+ 8007dca:	e065      	b.n	8007e98 <HAL_RCC_GetSysClockFreq+0x28c>
+
+          case RCC_PLLSOURCE_CSI:  /* CSI used as PLL clock source */
+            pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
+ 8007dcc:	693b      	ldr	r3, [r7, #16]
+ 8007dce:	ee07 3a90 	vmov	s15, r3
+ 8007dd2:	eef8 7a67 	vcvt.f32.u32	s15, s15
+ 8007dd6:	eddf 6a48 	vldr	s13, [pc, #288]	; 8007ef8 <HAL_RCC_GetSysClockFreq+0x2ec>
+ 8007dda:	ee86 7aa7 	vdiv.f32	s14, s13, s15
+ 8007dde:	4b40      	ldr	r3, [pc, #256]	; (8007ee0 <HAL_RCC_GetSysClockFreq+0x2d4>)
+ 8007de0:	6b1b      	ldr	r3, [r3, #48]	; 0x30
+ 8007de2:	f3c3 0308 	ubfx	r3, r3, #0, #9
+ 8007de6:	ee07 3a90 	vmov	s15, r3
+ 8007dea:	eef8 6a67 	vcvt.f32.u32	s13, s15
+ 8007dee:	ed97 6a02 	vldr	s12, [r7, #8]
+ 8007df2:	eddf 5a3f 	vldr	s11, [pc, #252]	; 8007ef0 <HAL_RCC_GetSysClockFreq+0x2e4>
+ 8007df6:	eec6 7a25 	vdiv.f32	s15, s12, s11
+ 8007dfa:	ee76 7aa7 	vadd.f32	s15, s13, s15
+ 8007dfe:	eef7 6a00 	vmov.f32	s13, #112	; 0x3f800000  1.0
+ 8007e02:	ee77 7aa6 	vadd.f32	s15, s15, s13
+ 8007e06:	ee67 7a27 	vmul.f32	s15, s14, s15
+ 8007e0a:	edc7 7a07 	vstr	s15, [r7, #28]
+            break;
+ 8007e0e:	e043      	b.n	8007e98 <HAL_RCC_GetSysClockFreq+0x28c>
+
+          case RCC_PLLSOURCE_HSE:  /* HSE used as PLL clock source */
+            pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
+ 8007e10:	693b      	ldr	r3, [r7, #16]
+ 8007e12:	ee07 3a90 	vmov	s15, r3
+ 8007e16:	eef8 7a67 	vcvt.f32.u32	s15, s15
+ 8007e1a:	eddf 6a38 	vldr	s13, [pc, #224]	; 8007efc <HAL_RCC_GetSysClockFreq+0x2f0>
+ 8007e1e:	ee86 7aa7 	vdiv.f32	s14, s13, s15
+ 8007e22:	4b2f      	ldr	r3, [pc, #188]	; (8007ee0 <HAL_RCC_GetSysClockFreq+0x2d4>)
+ 8007e24:	6b1b      	ldr	r3, [r3, #48]	; 0x30
+ 8007e26:	f3c3 0308 	ubfx	r3, r3, #0, #9
+ 8007e2a:	ee07 3a90 	vmov	s15, r3
+ 8007e2e:	eef8 6a67 	vcvt.f32.u32	s13, s15
+ 8007e32:	ed97 6a02 	vldr	s12, [r7, #8]
+ 8007e36:	eddf 5a2e 	vldr	s11, [pc, #184]	; 8007ef0 <HAL_RCC_GetSysClockFreq+0x2e4>
+ 8007e3a:	eec6 7a25 	vdiv.f32	s15, s12, s11
+ 8007e3e:	ee76 7aa7 	vadd.f32	s15, s13, s15
+ 8007e42:	eef7 6a00 	vmov.f32	s13, #112	; 0x3f800000  1.0
+ 8007e46:	ee77 7aa6 	vadd.f32	s15, s15, s13
+ 8007e4a:	ee67 7a27 	vmul.f32	s15, s14, s15
+ 8007e4e:	edc7 7a07 	vstr	s15, [r7, #28]
+            break;
+ 8007e52:	e021      	b.n	8007e98 <HAL_RCC_GetSysClockFreq+0x28c>
+
+          default:
+            pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
+ 8007e54:	693b      	ldr	r3, [r7, #16]
+ 8007e56:	ee07 3a90 	vmov	s15, r3
+ 8007e5a:	eef8 7a67 	vcvt.f32.u32	s15, s15
+ 8007e5e:	eddf 6a26 	vldr	s13, [pc, #152]	; 8007ef8 <HAL_RCC_GetSysClockFreq+0x2ec>
+ 8007e62:	ee86 7aa7 	vdiv.f32	s14, s13, s15
+ 8007e66:	4b1e      	ldr	r3, [pc, #120]	; (8007ee0 <HAL_RCC_GetSysClockFreq+0x2d4>)
+ 8007e68:	6b1b      	ldr	r3, [r3, #48]	; 0x30
+ 8007e6a:	f3c3 0308 	ubfx	r3, r3, #0, #9
+ 8007e6e:	ee07 3a90 	vmov	s15, r3
+ 8007e72:	eef8 6a67 	vcvt.f32.u32	s13, s15
+ 8007e76:	ed97 6a02 	vldr	s12, [r7, #8]
+ 8007e7a:	eddf 5a1d 	vldr	s11, [pc, #116]	; 8007ef0 <HAL_RCC_GetSysClockFreq+0x2e4>
+ 8007e7e:	eec6 7a25 	vdiv.f32	s15, s12, s11
+ 8007e82:	ee76 7aa7 	vadd.f32	s15, s13, s15
+ 8007e86:	eef7 6a00 	vmov.f32	s13, #112	; 0x3f800000  1.0
+ 8007e8a:	ee77 7aa6 	vadd.f32	s15, s15, s13
+ 8007e8e:	ee67 7a27 	vmul.f32	s15, s14, s15
+ 8007e92:	edc7 7a07 	vstr	s15, [r7, #28]
+            break;
+ 8007e96:	bf00      	nop
+        }
+        pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >> 9) + 1U) ;
+ 8007e98:	4b11      	ldr	r3, [pc, #68]	; (8007ee0 <HAL_RCC_GetSysClockFreq+0x2d4>)
+ 8007e9a:	6b1b      	ldr	r3, [r3, #48]	; 0x30
+ 8007e9c:	0a5b      	lsrs	r3, r3, #9
+ 8007e9e:	f003 037f 	and.w	r3, r3, #127	; 0x7f
+ 8007ea2:	3301      	adds	r3, #1
+ 8007ea4:	603b      	str	r3, [r7, #0]
+        sysclockfreq = (uint32_t)(float_t)(pllvco / (float_t)pllp);
+ 8007ea6:	683b      	ldr	r3, [r7, #0]
+ 8007ea8:	ee07 3a90 	vmov	s15, r3
+ 8007eac:	eeb8 7a67 	vcvt.f32.u32	s14, s15
+ 8007eb0:	edd7 6a07 	vldr	s13, [r7, #28]
+ 8007eb4:	eec6 7a87 	vdiv.f32	s15, s13, s14
+ 8007eb8:	eefc 7ae7 	vcvt.u32.f32	s15, s15
+ 8007ebc:	ee17 3a90 	vmov	r3, s15
+ 8007ec0:	61bb      	str	r3, [r7, #24]
+      }
+      else
+      {
+        sysclockfreq = 0U;
+      }
+      break;
+ 8007ec2:	e005      	b.n	8007ed0 <HAL_RCC_GetSysClockFreq+0x2c4>
+        sysclockfreq = 0U;
+ 8007ec4:	2300      	movs	r3, #0
+ 8007ec6:	61bb      	str	r3, [r7, #24]
+      break;
+ 8007ec8:	e002      	b.n	8007ed0 <HAL_RCC_GetSysClockFreq+0x2c4>
+
+    default:
+      sysclockfreq = CSI_VALUE;
+ 8007eca:	4b07      	ldr	r3, [pc, #28]	; (8007ee8 <HAL_RCC_GetSysClockFreq+0x2dc>)
+ 8007ecc:	61bb      	str	r3, [r7, #24]
+      break;
+ 8007ece:	bf00      	nop
+  }
+
+  return sysclockfreq;
+ 8007ed0:	69bb      	ldr	r3, [r7, #24]
+}
+ 8007ed2:	4618      	mov	r0, r3
+ 8007ed4:	3724      	adds	r7, #36	; 0x24
+ 8007ed6:	46bd      	mov	sp, r7
+ 8007ed8:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8007edc:	4770      	bx	lr
+ 8007ede:	bf00      	nop
+ 8007ee0:	58024400 	.word	0x58024400
+ 8007ee4:	03d09000 	.word	0x03d09000
+ 8007ee8:	003d0900 	.word	0x003d0900
+ 8007eec:	017d7840 	.word	0x017d7840
+ 8007ef0:	46000000 	.word	0x46000000
+ 8007ef4:	4c742400 	.word	0x4c742400
+ 8007ef8:	4a742400 	.word	0x4a742400
+ 8007efc:	4bbebc20 	.word	0x4bbebc20
+
+08007f00 <HAL_RCC_GetHCLKFreq>:
+  * @note   The SystemD2Clock CMSIS variable is used to store System domain2 Clock Frequency
+  *         and updated within this function
+  * @retval HCLK frequency
+  */
+uint32_t HAL_RCC_GetHCLKFreq(void)
+{
+ 8007f00:	b580      	push	{r7, lr}
+ 8007f02:	b082      	sub	sp, #8
+ 8007f04:	af00      	add	r7, sp, #0
+  uint32_t common_system_clock;
+
+#if defined(RCC_D1CFGR_D1CPRE)
+  common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE) >> RCC_D1CFGR_D1CPRE_Pos] & 0x1FU);
+ 8007f06:	f7ff fe81 	bl	8007c0c <HAL_RCC_GetSysClockFreq>
+ 8007f0a:	4602      	mov	r2, r0
+ 8007f0c:	4b10      	ldr	r3, [pc, #64]	; (8007f50 <HAL_RCC_GetHCLKFreq+0x50>)
+ 8007f0e:	699b      	ldr	r3, [r3, #24]
+ 8007f10:	0a1b      	lsrs	r3, r3, #8
+ 8007f12:	f003 030f 	and.w	r3, r3, #15
+ 8007f16:	490f      	ldr	r1, [pc, #60]	; (8007f54 <HAL_RCC_GetHCLKFreq+0x54>)
+ 8007f18:	5ccb      	ldrb	r3, [r1, r3]
+ 8007f1a:	f003 031f 	and.w	r3, r3, #31
+ 8007f1e:	fa22 f303 	lsr.w	r3, r2, r3
+ 8007f22:	607b      	str	r3, [r7, #4]
+#else
+  common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE) >> RCC_CDCFGR1_CDCPRE_Pos] & 0x1FU);
+#endif
+
+#if defined(RCC_D1CFGR_HPRE)
+  SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE) >> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
+ 8007f24:	4b0a      	ldr	r3, [pc, #40]	; (8007f50 <HAL_RCC_GetHCLKFreq+0x50>)
+ 8007f26:	699b      	ldr	r3, [r3, #24]
+ 8007f28:	f003 030f 	and.w	r3, r3, #15
+ 8007f2c:	4a09      	ldr	r2, [pc, #36]	; (8007f54 <HAL_RCC_GetHCLKFreq+0x54>)
+ 8007f2e:	5cd3      	ldrb	r3, [r2, r3]
+ 8007f30:	f003 031f 	and.w	r3, r3, #31
+ 8007f34:	687a      	ldr	r2, [r7, #4]
+ 8007f36:	fa22 f303 	lsr.w	r3, r2, r3
+ 8007f3a:	4a07      	ldr	r2, [pc, #28]	; (8007f58 <HAL_RCC_GetHCLKFreq+0x58>)
+ 8007f3c:	6013      	str	r3, [r2, #0]
+#endif
+
+#if defined(DUAL_CORE) && defined(CORE_CM4)
+  SystemCoreClock = SystemD2Clock;
+#else
+  SystemCoreClock = common_system_clock;
+ 8007f3e:	4a07      	ldr	r2, [pc, #28]	; (8007f5c <HAL_RCC_GetHCLKFreq+0x5c>)
+ 8007f40:	687b      	ldr	r3, [r7, #4]
+ 8007f42:	6013      	str	r3, [r2, #0]
+#endif /* DUAL_CORE && CORE_CM4 */
+
+  return SystemD2Clock;
+ 8007f44:	4b04      	ldr	r3, [pc, #16]	; (8007f58 <HAL_RCC_GetHCLKFreq+0x58>)
+ 8007f46:	681b      	ldr	r3, [r3, #0]
+}
+ 8007f48:	4618      	mov	r0, r3
+ 8007f4a:	3708      	adds	r7, #8
+ 8007f4c:	46bd      	mov	sp, r7
+ 8007f4e:	bd80      	pop	{r7, pc}
+ 8007f50:	58024400 	.word	0x58024400
+ 8007f54:	08026b40 	.word	0x08026b40
+ 8007f58:	24000018 	.word	0x24000018
+ 8007f5c:	24000014 	.word	0x24000014
+
+08007f60 <HAL_RCC_GetPCLK1Freq>:
+  * @note   Each time PCLK1 changes, this function must be called to update the
+  *         right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
+  * @retval PCLK1 frequency
+  */
+uint32_t HAL_RCC_GetPCLK1Freq(void)
+{
+ 8007f60:	b580      	push	{r7, lr}
+ 8007f62:	af00      	add	r7, sp, #0
+#if defined (RCC_D2CFGR_D2PPRE1)
+  /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
+  return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->D2CFGR & RCC_D2CFGR_D2PPRE1) >> RCC_D2CFGR_D2PPRE1_Pos]) & 0x1FU));
+ 8007f64:	f7ff ffcc 	bl	8007f00 <HAL_RCC_GetHCLKFreq>
+ 8007f68:	4602      	mov	r2, r0
+ 8007f6a:	4b06      	ldr	r3, [pc, #24]	; (8007f84 <HAL_RCC_GetPCLK1Freq+0x24>)
+ 8007f6c:	69db      	ldr	r3, [r3, #28]
+ 8007f6e:	091b      	lsrs	r3, r3, #4
+ 8007f70:	f003 0307 	and.w	r3, r3, #7
+ 8007f74:	4904      	ldr	r1, [pc, #16]	; (8007f88 <HAL_RCC_GetPCLK1Freq+0x28>)
+ 8007f76:	5ccb      	ldrb	r3, [r1, r3]
+ 8007f78:	f003 031f 	and.w	r3, r3, #31
+ 8007f7c:	fa22 f303 	lsr.w	r3, r2, r3
+#else
+  /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
+  return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE1) >> RCC_CDCFGR2_CDPPRE1_Pos]) & 0x1FU));
+#endif
+}
+ 8007f80:	4618      	mov	r0, r3
+ 8007f82:	bd80      	pop	{r7, pc}
+ 8007f84:	58024400 	.word	0x58024400
+ 8007f88:	08026b40 	.word	0x08026b40
+
+08007f8c <HAL_RCC_GetPCLK2Freq>:
+  * @note   Each time PCLK2 changes, this function must be called to update the
+  *         right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
+  * @retval PCLK1 frequency
+  */
+uint32_t HAL_RCC_GetPCLK2Freq(void)
+{
+ 8007f8c:	b580      	push	{r7, lr}
+ 8007f8e:	af00      	add	r7, sp, #0
+  /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
+#if defined(RCC_D2CFGR_D2PPRE2)
+  return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->D2CFGR & RCC_D2CFGR_D2PPRE2) >> RCC_D2CFGR_D2PPRE2_Pos]) & 0x1FU));
+ 8007f90:	f7ff ffb6 	bl	8007f00 <HAL_RCC_GetHCLKFreq>
+ 8007f94:	4602      	mov	r2, r0
+ 8007f96:	4b06      	ldr	r3, [pc, #24]	; (8007fb0 <HAL_RCC_GetPCLK2Freq+0x24>)
+ 8007f98:	69db      	ldr	r3, [r3, #28]
+ 8007f9a:	0a1b      	lsrs	r3, r3, #8
+ 8007f9c:	f003 0307 	and.w	r3, r3, #7
+ 8007fa0:	4904      	ldr	r1, [pc, #16]	; (8007fb4 <HAL_RCC_GetPCLK2Freq+0x28>)
+ 8007fa2:	5ccb      	ldrb	r3, [r1, r3]
+ 8007fa4:	f003 031f 	and.w	r3, r3, #31
+ 8007fa8:	fa22 f303 	lsr.w	r3, r2, r3
+#else
+  return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE2) >> RCC_CDCFGR2_CDPPRE2_Pos]) & 0x1FU));
+#endif
+}
+ 8007fac:	4618      	mov	r0, r3
+ 8007fae:	bd80      	pop	{r7, pc}
+ 8007fb0:	58024400 	.word	0x58024400
+ 8007fb4:	08026b40 	.word	0x08026b40
+
+08007fb8 <HAL_RCC_GetClockConfig>:
+  * will be configured.
+  * @param  pFLatency: Pointer on the Flash Latency.
+  * @retval None
+  */
+void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t *pFLatency)
+{
+ 8007fb8:	b480      	push	{r7}
+ 8007fba:	b083      	sub	sp, #12
+ 8007fbc:	af00      	add	r7, sp, #0
+ 8007fbe:	6078      	str	r0, [r7, #4]
+ 8007fc0:	6039      	str	r1, [r7, #0]
+  /* Set all possible values for the Clock type parameter --------------------*/
+  RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_D1PCLK1 | RCC_CLOCKTYPE_PCLK1 |
+ 8007fc2:	687b      	ldr	r3, [r7, #4]
+ 8007fc4:	223f      	movs	r2, #63	; 0x3f
+ 8007fc6:	601a      	str	r2, [r3, #0]
+                                 RCC_CLOCKTYPE_PCLK2 |  RCC_CLOCKTYPE_D3PCLK1  ;
+
+  /* Get the SYSCLK configuration --------------------------------------------*/
+  RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW);
+ 8007fc8:	4b1a      	ldr	r3, [pc, #104]	; (8008034 <HAL_RCC_GetClockConfig+0x7c>)
+ 8007fca:	691b      	ldr	r3, [r3, #16]
+ 8007fcc:	f003 0207 	and.w	r2, r3, #7
+ 8007fd0:	687b      	ldr	r3, [r7, #4]
+ 8007fd2:	605a      	str	r2, [r3, #4]
+
+#if defined(RCC_D1CFGR_D1CPRE)
+  /* Get the SYSCLK configuration ----------------------------------------------*/
+  RCC_ClkInitStruct->SYSCLKDivider = (uint32_t)(RCC->D1CFGR & RCC_D1CFGR_D1CPRE);
+ 8007fd4:	4b17      	ldr	r3, [pc, #92]	; (8008034 <HAL_RCC_GetClockConfig+0x7c>)
+ 8007fd6:	699b      	ldr	r3, [r3, #24]
+ 8007fd8:	f403 6270 	and.w	r2, r3, #3840	; 0xf00
+ 8007fdc:	687b      	ldr	r3, [r7, #4]
+ 8007fde:	609a      	str	r2, [r3, #8]
+
+  /* Get the D1HCLK configuration ----------------------------------------------*/
+  RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->D1CFGR & RCC_D1CFGR_HPRE);
+ 8007fe0:	4b14      	ldr	r3, [pc, #80]	; (8008034 <HAL_RCC_GetClockConfig+0x7c>)
+ 8007fe2:	699b      	ldr	r3, [r3, #24]
+ 8007fe4:	f003 020f 	and.w	r2, r3, #15
+ 8007fe8:	687b      	ldr	r3, [r7, #4]
+ 8007fea:	60da      	str	r2, [r3, #12]
+
+  /* Get the APB3 configuration ----------------------------------------------*/
+  RCC_ClkInitStruct->APB3CLKDivider = (uint32_t)(RCC->D1CFGR & RCC_D1CFGR_D1PPRE);
+ 8007fec:	4b11      	ldr	r3, [pc, #68]	; (8008034 <HAL_RCC_GetClockConfig+0x7c>)
+ 8007fee:	699b      	ldr	r3, [r3, #24]
+ 8007ff0:	f003 0270 	and.w	r2, r3, #112	; 0x70
+ 8007ff4:	687b      	ldr	r3, [r7, #4]
+ 8007ff6:	611a      	str	r2, [r3, #16]
+
+  /* Get the APB1 configuration ----------------------------------------------*/
+  RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->D2CFGR & RCC_D2CFGR_D2PPRE1);
+ 8007ff8:	4b0e      	ldr	r3, [pc, #56]	; (8008034 <HAL_RCC_GetClockConfig+0x7c>)
+ 8007ffa:	69db      	ldr	r3, [r3, #28]
+ 8007ffc:	f003 0270 	and.w	r2, r3, #112	; 0x70
+ 8008000:	687b      	ldr	r3, [r7, #4]
+ 8008002:	615a      	str	r2, [r3, #20]
+
+  /* Get the APB2 configuration ----------------------------------------------*/
+  RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)(RCC->D2CFGR & RCC_D2CFGR_D2PPRE2);
+ 8008004:	4b0b      	ldr	r3, [pc, #44]	; (8008034 <HAL_RCC_GetClockConfig+0x7c>)
+ 8008006:	69db      	ldr	r3, [r3, #28]
+ 8008008:	f403 62e0 	and.w	r2, r3, #1792	; 0x700
+ 800800c:	687b      	ldr	r3, [r7, #4]
+ 800800e:	619a      	str	r2, [r3, #24]
+
+  /* Get the APB4 configuration ----------------------------------------------*/
+  RCC_ClkInitStruct->APB4CLKDivider = (uint32_t)(RCC->D3CFGR & RCC_D3CFGR_D3PPRE);
+ 8008010:	4b08      	ldr	r3, [pc, #32]	; (8008034 <HAL_RCC_GetClockConfig+0x7c>)
+ 8008012:	6a1b      	ldr	r3, [r3, #32]
+ 8008014:	f003 0270 	and.w	r2, r3, #112	; 0x70
+ 8008018:	687b      	ldr	r3, [r7, #4]
+ 800801a:	61da      	str	r2, [r3, #28]
+  /* Get the APB4 configuration ----------------------------------------------*/
+  RCC_ClkInitStruct->APB4CLKDivider = (uint32_t)(RCC->SRDCFGR & RCC_SRDCFGR_SRDPPRE);
+#endif
+
+  /* Get the Flash Wait State (Latency) configuration ------------------------*/
+  *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY);
+ 800801c:	4b06      	ldr	r3, [pc, #24]	; (8008038 <HAL_RCC_GetClockConfig+0x80>)
+ 800801e:	681b      	ldr	r3, [r3, #0]
+ 8008020:	f003 020f 	and.w	r2, r3, #15
+ 8008024:	683b      	ldr	r3, [r7, #0]
+ 8008026:	601a      	str	r2, [r3, #0]
+}
+ 8008028:	bf00      	nop
+ 800802a:	370c      	adds	r7, #12
+ 800802c:	46bd      	mov	sp, r7
+ 800802e:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8008032:	4770      	bx	lr
+ 8008034:	58024400 	.word	0x58024400
+ 8008038:	52002000 	.word	0x52002000
+
+0800803c <HAL_RCCEx_PeriphCLKConfig>:
+  * (*) : Available on some STM32H7 lines only.
+  *
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
+{
+ 800803c:	e92d 4fb0 	stmdb	sp!, {r4, r5, r7, r8, r9, sl, fp, lr}
+ 8008040:	b0c6      	sub	sp, #280	; 0x118
+ 8008042:	af00      	add	r7, sp, #0
+ 8008044:	f8c7 0104 	str.w	r0, [r7, #260]	; 0x104
+  uint32_t tmpreg;
+  uint32_t tickstart;
+  HAL_StatusTypeDef ret = HAL_OK;      /* Intermediate status */
+ 8008048:	2300      	movs	r3, #0
+ 800804a:	f887 3117 	strb.w	r3, [r7, #279]	; 0x117
+  HAL_StatusTypeDef status = HAL_OK;   /* Final status */
+ 800804e:	2300      	movs	r3, #0
+ 8008050:	f887 3116 	strb.w	r3, [r7, #278]	; 0x116
+
+  /*---------------------------- SPDIFRX configuration -------------------------------*/
+
+  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX)
+ 8008054:	f8d7 3104 	ldr.w	r3, [r7, #260]	; 0x104
+ 8008058:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 800805c:	f002 6400 	and.w	r4, r2, #134217728	; 0x8000000
+ 8008060:	2500      	movs	r5, #0
+ 8008062:	ea54 0305 	orrs.w	r3, r4, r5
+ 8008066:	d049      	beq.n	80080fc <HAL_RCCEx_PeriphCLKConfig+0xc0>
+  {
+
+    switch (PeriphClkInit->SpdifrxClockSelection)
+ 8008068:	f8d7 3104 	ldr.w	r3, [r7, #260]	; 0x104
+ 800806c:	6e5b      	ldr	r3, [r3, #100]	; 0x64
+ 800806e:	f5b3 1f40 	cmp.w	r3, #3145728	; 0x300000
+ 8008072:	d02f      	beq.n	80080d4 <HAL_RCCEx_PeriphCLKConfig+0x98>
+ 8008074:	f5b3 1f40 	cmp.w	r3, #3145728	; 0x300000
+ 8008078:	d828      	bhi.n	80080cc <HAL_RCCEx_PeriphCLKConfig+0x90>
+ 800807a:	f5b3 1f00 	cmp.w	r3, #2097152	; 0x200000
+ 800807e:	d01a      	beq.n	80080b6 <HAL_RCCEx_PeriphCLKConfig+0x7a>
+ 8008080:	f5b3 1f00 	cmp.w	r3, #2097152	; 0x200000
+ 8008084:	d822      	bhi.n	80080cc <HAL_RCCEx_PeriphCLKConfig+0x90>
+ 8008086:	2b00      	cmp	r3, #0
+ 8008088:	d003      	beq.n	8008092 <HAL_RCCEx_PeriphCLKConfig+0x56>
+ 800808a:	f5b3 1f80 	cmp.w	r3, #1048576	; 0x100000
+ 800808e:	d007      	beq.n	80080a0 <HAL_RCCEx_PeriphCLKConfig+0x64>
+ 8008090:	e01c      	b.n	80080cc <HAL_RCCEx_PeriphCLKConfig+0x90>
+    {
+      case RCC_SPDIFRXCLKSOURCE_PLL:      /* PLL is used as clock source for SPDIFRX*/
+        /* Enable PLL1Q Clock output generated form System PLL . */
+        __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
+ 8008092:	4bab      	ldr	r3, [pc, #684]	; (8008340 <HAL_RCCEx_PeriphCLKConfig+0x304>)
+ 8008094:	6adb      	ldr	r3, [r3, #44]	; 0x2c
+ 8008096:	4aaa      	ldr	r2, [pc, #680]	; (8008340 <HAL_RCCEx_PeriphCLKConfig+0x304>)
+ 8008098:	f443 3300 	orr.w	r3, r3, #131072	; 0x20000
+ 800809c:	62d3      	str	r3, [r2, #44]	; 0x2c
+
+        /* SPDIFRX clock source configuration done later after clock selection check */
+        break;
+ 800809e:	e01a      	b.n	80080d6 <HAL_RCCEx_PeriphCLKConfig+0x9a>
+
+      case RCC_SPDIFRXCLKSOURCE_PLL2: /* PLL2 is used as clock source for SPDIFRX*/
+
+        ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_R_UPDATE);
+ 80080a0:	f8d7 3104 	ldr.w	r3, [r7, #260]	; 0x104
+ 80080a4:	3308      	adds	r3, #8
+ 80080a6:	2102      	movs	r1, #2
+ 80080a8:	4618      	mov	r0, r3
+ 80080aa:	f002 fa49 	bl	800a540 <RCCEx_PLL2_Config>
+ 80080ae:	4603      	mov	r3, r0
+ 80080b0:	f887 3117 	strb.w	r3, [r7, #279]	; 0x117
+
+        /* SPDIFRX clock source configuration done later after clock selection check */
+        break;
+ 80080b4:	e00f      	b.n	80080d6 <HAL_RCCEx_PeriphCLKConfig+0x9a>
+
+      case RCC_SPDIFRXCLKSOURCE_PLL3:  /* PLL3 is used as clock source for SPDIFRX*/
+        ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE);
+ 80080b6:	f8d7 3104 	ldr.w	r3, [r7, #260]	; 0x104
+ 80080ba:	3328      	adds	r3, #40	; 0x28
+ 80080bc:	2102      	movs	r1, #2
+ 80080be:	4618      	mov	r0, r3
+ 80080c0:	f002 faf0 	bl	800a6a4 <RCCEx_PLL3_Config>
+ 80080c4:	4603      	mov	r3, r0
+ 80080c6:	f887 3117 	strb.w	r3, [r7, #279]	; 0x117
+
+        /* SPDIFRX clock source configuration done later after clock selection check */
+        break;
+ 80080ca:	e004      	b.n	80080d6 <HAL_RCCEx_PeriphCLKConfig+0x9a>
+        /* Internal OSC clock is used as source of SPDIFRX clock*/
+        /* SPDIFRX clock source configuration done later after clock selection check */
+        break;
+
+      default:
+        ret = HAL_ERROR;
+ 80080cc:	2301      	movs	r3, #1
+ 80080ce:	f887 3117 	strb.w	r3, [r7, #279]	; 0x117
+        break;
+ 80080d2:	e000      	b.n	80080d6 <HAL_RCCEx_PeriphCLKConfig+0x9a>
+        break;
+ 80080d4:	bf00      	nop
+    }
+
+    if (ret == HAL_OK)
+ 80080d6:	f897 3117 	ldrb.w	r3, [r7, #279]	; 0x117
+ 80080da:	2b00      	cmp	r3, #0
+ 80080dc:	d10a      	bne.n	80080f4 <HAL_RCCEx_PeriphCLKConfig+0xb8>
+    {
+      /* Set the source of SPDIFRX clock*/
+      __HAL_RCC_SPDIFRX_CONFIG(PeriphClkInit->SpdifrxClockSelection);
+ 80080de:	4b98      	ldr	r3, [pc, #608]	; (8008340 <HAL_RCCEx_PeriphCLKConfig+0x304>)
+ 80080e0:	6d1b      	ldr	r3, [r3, #80]	; 0x50
+ 80080e2:	f423 1140 	bic.w	r1, r3, #3145728	; 0x300000
+ 80080e6:	f8d7 3104 	ldr.w	r3, [r7, #260]	; 0x104
+ 80080ea:	6e5b      	ldr	r3, [r3, #100]	; 0x64
+ 80080ec:	4a94      	ldr	r2, [pc, #592]	; (8008340 <HAL_RCCEx_PeriphCLKConfig+0x304>)
+ 80080ee:	430b      	orrs	r3, r1
+ 80080f0:	6513      	str	r3, [r2, #80]	; 0x50
+ 80080f2:	e003      	b.n	80080fc <HAL_RCCEx_PeriphCLKConfig+0xc0>
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+ 80080f4:	f897 3117 	ldrb.w	r3, [r7, #279]	; 0x117
+ 80080f8:	f887 3116 	strb.w	r3, [r7, #278]	; 0x116
+    }
+  }
+
+  /*---------------------------- SAI1 configuration -------------------------------*/
+  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1)
+ 80080fc:	f8d7 3104 	ldr.w	r3, [r7, #260]	; 0x104
+ 8008100:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 8008104:	f402 7880 	and.w	r8, r2, #256	; 0x100
+ 8008108:	f04f 0900 	mov.w	r9, #0
+ 800810c:	ea58 0309 	orrs.w	r3, r8, r9
+ 8008110:	d047      	beq.n	80081a2 <HAL_RCCEx_PeriphCLKConfig+0x166>
+  {
+    switch (PeriphClkInit->Sai1ClockSelection)
+ 8008112:	f8d7 3104 	ldr.w	r3, [r7, #260]	; 0x104
+ 8008116:	6d9b      	ldr	r3, [r3, #88]	; 0x58
+ 8008118:	2b04      	cmp	r3, #4
+ 800811a:	d82a      	bhi.n	8008172 <HAL_RCCEx_PeriphCLKConfig+0x136>
+ 800811c:	a201      	add	r2, pc, #4	; (adr r2, 8008124 <HAL_RCCEx_PeriphCLKConfig+0xe8>)
+ 800811e:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
+ 8008122:	bf00      	nop
+ 8008124:	08008139 	.word	0x08008139
+ 8008128:	08008147 	.word	0x08008147
+ 800812c:	0800815d 	.word	0x0800815d
+ 8008130:	0800817b 	.word	0x0800817b
+ 8008134:	0800817b 	.word	0x0800817b
+    {
+      case RCC_SAI1CLKSOURCE_PLL:      /* PLL is used as clock source for SAI1*/
+        /* Enable SAI Clock output generated form System PLL . */
+        __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
+ 8008138:	4b81      	ldr	r3, [pc, #516]	; (8008340 <HAL_RCCEx_PeriphCLKConfig+0x304>)
+ 800813a:	6adb      	ldr	r3, [r3, #44]	; 0x2c
+ 800813c:	4a80      	ldr	r2, [pc, #512]	; (8008340 <HAL_RCCEx_PeriphCLKConfig+0x304>)
+ 800813e:	f443 3300 	orr.w	r3, r3, #131072	; 0x20000
+ 8008142:	62d3      	str	r3, [r2, #44]	; 0x2c
+
+        /* SAI1 clock source configuration done later after clock selection check */
+        break;
+ 8008144:	e01a      	b.n	800817c <HAL_RCCEx_PeriphCLKConfig+0x140>
+
+      case RCC_SAI1CLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI1*/
+
+        ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE);
+ 8008146:	f8d7 3104 	ldr.w	r3, [r7, #260]	; 0x104
+ 800814a:	3308      	adds	r3, #8
+ 800814c:	2100      	movs	r1, #0
+ 800814e:	4618      	mov	r0, r3
+ 8008150:	f002 f9f6 	bl	800a540 <RCCEx_PLL2_Config>
+ 8008154:	4603      	mov	r3, r0
+ 8008156:	f887 3117 	strb.w	r3, [r7, #279]	; 0x117
+
+        /* SAI1 clock source configuration done later after clock selection check */
+        break;
+ 800815a:	e00f      	b.n	800817c <HAL_RCCEx_PeriphCLKConfig+0x140>
+
+      case RCC_SAI1CLKSOURCE_PLL3:  /* PLL3 is used as clock source for SAI1*/
+        ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE);
+ 800815c:	f8d7 3104 	ldr.w	r3, [r7, #260]	; 0x104
+ 8008160:	3328      	adds	r3, #40	; 0x28
+ 8008162:	2100      	movs	r1, #0
+ 8008164:	4618      	mov	r0, r3
+ 8008166:	f002 fa9d 	bl	800a6a4 <RCCEx_PLL3_Config>
+ 800816a:	4603      	mov	r3, r0
+ 800816c:	f887 3117 	strb.w	r3, [r7, #279]	; 0x117
+
+        /* SAI1 clock source configuration done later after clock selection check */
+        break;
+ 8008170:	e004      	b.n	800817c <HAL_RCCEx_PeriphCLKConfig+0x140>
+        /* HSI, HSE, or CSI oscillator is used as source of SAI1 clock */
+        /* SAI1 clock source configuration done later after clock selection check */
+        break;
+
+      default:
+        ret = HAL_ERROR;
+ 8008172:	2301      	movs	r3, #1
+ 8008174:	f887 3117 	strb.w	r3, [r7, #279]	; 0x117
+        break;
+ 8008178:	e000      	b.n	800817c <HAL_RCCEx_PeriphCLKConfig+0x140>
+        break;
+ 800817a:	bf00      	nop
+    }
+
+    if (ret == HAL_OK)
+ 800817c:	f897 3117 	ldrb.w	r3, [r7, #279]	; 0x117
+ 8008180:	2b00      	cmp	r3, #0
+ 8008182:	d10a      	bne.n	800819a <HAL_RCCEx_PeriphCLKConfig+0x15e>
+    {
+      /* Set the source of SAI1 clock*/
+      __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);
+ 8008184:	4b6e      	ldr	r3, [pc, #440]	; (8008340 <HAL_RCCEx_PeriphCLKConfig+0x304>)
+ 8008186:	6d1b      	ldr	r3, [r3, #80]	; 0x50
+ 8008188:	f023 0107 	bic.w	r1, r3, #7
+ 800818c:	f8d7 3104 	ldr.w	r3, [r7, #260]	; 0x104
+ 8008190:	6d9b      	ldr	r3, [r3, #88]	; 0x58
+ 8008192:	4a6b      	ldr	r2, [pc, #428]	; (8008340 <HAL_RCCEx_PeriphCLKConfig+0x304>)
+ 8008194:	430b      	orrs	r3, r1
+ 8008196:	6513      	str	r3, [r2, #80]	; 0x50
+ 8008198:	e003      	b.n	80081a2 <HAL_RCCEx_PeriphCLKConfig+0x166>
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+ 800819a:	f897 3117 	ldrb.w	r3, [r7, #279]	; 0x117
+ 800819e:	f887 3116 	strb.w	r3, [r7, #278]	; 0x116
+  }
+#endif  /*SAI2B*/
+
+#if defined(SAI4)
+  /*---------------------------- SAI4A configuration -------------------------------*/
+  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI4A) == RCC_PERIPHCLK_SAI4A)
+ 80081a2:	f8d7 3104 	ldr.w	r3, [r7, #260]	; 0x104
+ 80081a6:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 80081aa:	f402 6a80 	and.w	sl, r2, #1024	; 0x400
+ 80081ae:	f04f 0b00 	mov.w	fp, #0
+ 80081b2:	ea5a 030b 	orrs.w	r3, sl, fp
+ 80081b6:	d05b      	beq.n	8008270 <HAL_RCCEx_PeriphCLKConfig+0x234>
+  {
+    switch (PeriphClkInit->Sai4AClockSelection)
+ 80081b8:	f8d7 3104 	ldr.w	r3, [r7, #260]	; 0x104
+ 80081bc:	f8d3 30a4 	ldr.w	r3, [r3, #164]	; 0xa4
+ 80081c0:	f5b3 0f20 	cmp.w	r3, #10485760	; 0xa00000
+ 80081c4:	d03b      	beq.n	800823e <HAL_RCCEx_PeriphCLKConfig+0x202>
+ 80081c6:	f5b3 0f20 	cmp.w	r3, #10485760	; 0xa00000
+ 80081ca:	d834      	bhi.n	8008236 <HAL_RCCEx_PeriphCLKConfig+0x1fa>
+ 80081cc:	f5b3 0f00 	cmp.w	r3, #8388608	; 0x800000
+ 80081d0:	d037      	beq.n	8008242 <HAL_RCCEx_PeriphCLKConfig+0x206>
+ 80081d2:	f5b3 0f00 	cmp.w	r3, #8388608	; 0x800000
+ 80081d6:	d82e      	bhi.n	8008236 <HAL_RCCEx_PeriphCLKConfig+0x1fa>
+ 80081d8:	f5b3 0fc0 	cmp.w	r3, #6291456	; 0x600000
+ 80081dc:	d033      	beq.n	8008246 <HAL_RCCEx_PeriphCLKConfig+0x20a>
+ 80081de:	f5b3 0fc0 	cmp.w	r3, #6291456	; 0x600000
+ 80081e2:	d828      	bhi.n	8008236 <HAL_RCCEx_PeriphCLKConfig+0x1fa>
+ 80081e4:	f5b3 0f80 	cmp.w	r3, #4194304	; 0x400000
+ 80081e8:	d01a      	beq.n	8008220 <HAL_RCCEx_PeriphCLKConfig+0x1e4>
+ 80081ea:	f5b3 0f80 	cmp.w	r3, #4194304	; 0x400000
+ 80081ee:	d822      	bhi.n	8008236 <HAL_RCCEx_PeriphCLKConfig+0x1fa>
+ 80081f0:	2b00      	cmp	r3, #0
+ 80081f2:	d003      	beq.n	80081fc <HAL_RCCEx_PeriphCLKConfig+0x1c0>
+ 80081f4:	f5b3 1f00 	cmp.w	r3, #2097152	; 0x200000
+ 80081f8:	d007      	beq.n	800820a <HAL_RCCEx_PeriphCLKConfig+0x1ce>
+ 80081fa:	e01c      	b.n	8008236 <HAL_RCCEx_PeriphCLKConfig+0x1fa>
+    {
+      case RCC_SAI4ACLKSOURCE_PLL:      /* PLL is used as clock source for SAI2*/
+        /* Enable SAI Clock output generated form System PLL . */
+        __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
+ 80081fc:	4b50      	ldr	r3, [pc, #320]	; (8008340 <HAL_RCCEx_PeriphCLKConfig+0x304>)
+ 80081fe:	6adb      	ldr	r3, [r3, #44]	; 0x2c
+ 8008200:	4a4f      	ldr	r2, [pc, #316]	; (8008340 <HAL_RCCEx_PeriphCLKConfig+0x304>)
+ 8008202:	f443 3300 	orr.w	r3, r3, #131072	; 0x20000
+ 8008206:	62d3      	str	r3, [r2, #44]	; 0x2c
+
+        /* SAI1 clock source configuration done later after clock selection check */
+        break;
+ 8008208:	e01e      	b.n	8008248 <HAL_RCCEx_PeriphCLKConfig+0x20c>
+
+      case RCC_SAI4ACLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2*/
+
+        ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE);
+ 800820a:	f8d7 3104 	ldr.w	r3, [r7, #260]	; 0x104
+ 800820e:	3308      	adds	r3, #8
+ 8008210:	2100      	movs	r1, #0
+ 8008212:	4618      	mov	r0, r3
+ 8008214:	f002 f994 	bl	800a540 <RCCEx_PLL2_Config>
+ 8008218:	4603      	mov	r3, r0
+ 800821a:	f887 3117 	strb.w	r3, [r7, #279]	; 0x117
+
+        /* SAI2 clock source configuration done later after clock selection check */
+        break;
+ 800821e:	e013      	b.n	8008248 <HAL_RCCEx_PeriphCLKConfig+0x20c>
+
+      case RCC_SAI4ACLKSOURCE_PLL3:  /* PLL3 is used as clock source for SAI2*/
+        ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE);
+ 8008220:	f8d7 3104 	ldr.w	r3, [r7, #260]	; 0x104
+ 8008224:	3328      	adds	r3, #40	; 0x28
+ 8008226:	2100      	movs	r1, #0
+ 8008228:	4618      	mov	r0, r3
+ 800822a:	f002 fa3b 	bl	800a6a4 <RCCEx_PLL3_Config>
+ 800822e:	4603      	mov	r3, r0
+ 8008230:	f887 3117 	strb.w	r3, [r7, #279]	; 0x117
+
+        /* SAI1 clock source configuration done later after clock selection check */
+        break;
+ 8008234:	e008      	b.n	8008248 <HAL_RCCEx_PeriphCLKConfig+0x20c>
+        /* SAI4A clock source configuration done later after clock selection check */
+        break;
+#endif /* RCC_VER_3_0 */
+
+      default:
+        ret = HAL_ERROR;
+ 8008236:	2301      	movs	r3, #1
+ 8008238:	f887 3117 	strb.w	r3, [r7, #279]	; 0x117
+        break;
+ 800823c:	e004      	b.n	8008248 <HAL_RCCEx_PeriphCLKConfig+0x20c>
+        break;
+ 800823e:	bf00      	nop
+ 8008240:	e002      	b.n	8008248 <HAL_RCCEx_PeriphCLKConfig+0x20c>
+        break;
+ 8008242:	bf00      	nop
+ 8008244:	e000      	b.n	8008248 <HAL_RCCEx_PeriphCLKConfig+0x20c>
+        break;
+ 8008246:	bf00      	nop
+    }
+
+    if (ret == HAL_OK)
+ 8008248:	f897 3117 	ldrb.w	r3, [r7, #279]	; 0x117
+ 800824c:	2b00      	cmp	r3, #0
+ 800824e:	d10b      	bne.n	8008268 <HAL_RCCEx_PeriphCLKConfig+0x22c>
+    {
+      /* Set the source of SAI4A clock*/
+      __HAL_RCC_SAI4A_CONFIG(PeriphClkInit->Sai4AClockSelection);
+ 8008250:	4b3b      	ldr	r3, [pc, #236]	; (8008340 <HAL_RCCEx_PeriphCLKConfig+0x304>)
+ 8008252:	6d9b      	ldr	r3, [r3, #88]	; 0x58
+ 8008254:	f423 0160 	bic.w	r1, r3, #14680064	; 0xe00000
+ 8008258:	f8d7 3104 	ldr.w	r3, [r7, #260]	; 0x104
+ 800825c:	f8d3 30a4 	ldr.w	r3, [r3, #164]	; 0xa4
+ 8008260:	4a37      	ldr	r2, [pc, #220]	; (8008340 <HAL_RCCEx_PeriphCLKConfig+0x304>)
+ 8008262:	430b      	orrs	r3, r1
+ 8008264:	6593      	str	r3, [r2, #88]	; 0x58
+ 8008266:	e003      	b.n	8008270 <HAL_RCCEx_PeriphCLKConfig+0x234>
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+ 8008268:	f897 3117 	ldrb.w	r3, [r7, #279]	; 0x117
+ 800826c:	f887 3116 	strb.w	r3, [r7, #278]	; 0x116
+    }
+  }
+  /*---------------------------- SAI4B configuration -------------------------------*/
+  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI4B) == RCC_PERIPHCLK_SAI4B)
+ 8008270:	f8d7 3104 	ldr.w	r3, [r7, #260]	; 0x104
+ 8008274:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 8008278:	f402 6300 	and.w	r3, r2, #2048	; 0x800
+ 800827c:	f8c7 30f8 	str.w	r3, [r7, #248]	; 0xf8
+ 8008280:	2300      	movs	r3, #0
+ 8008282:	f8c7 30fc 	str.w	r3, [r7, #252]	; 0xfc
+ 8008286:	e9d7 123e 	ldrd	r1, r2, [r7, #248]	; 0xf8
+ 800828a:	460b      	mov	r3, r1
+ 800828c:	4313      	orrs	r3, r2
+ 800828e:	d05d      	beq.n	800834c <HAL_RCCEx_PeriphCLKConfig+0x310>
+  {
+    switch (PeriphClkInit->Sai4BClockSelection)
+ 8008290:	f8d7 3104 	ldr.w	r3, [r7, #260]	; 0x104
+ 8008294:	f8d3 30a8 	ldr.w	r3, [r3, #168]	; 0xa8
+ 8008298:	f1b3 6fa0 	cmp.w	r3, #83886080	; 0x5000000
+ 800829c:	d03b      	beq.n	8008316 <HAL_RCCEx_PeriphCLKConfig+0x2da>
+ 800829e:	f1b3 6fa0 	cmp.w	r3, #83886080	; 0x5000000
+ 80082a2:	d834      	bhi.n	800830e <HAL_RCCEx_PeriphCLKConfig+0x2d2>
+ 80082a4:	f1b3 6f80 	cmp.w	r3, #67108864	; 0x4000000
+ 80082a8:	d037      	beq.n	800831a <HAL_RCCEx_PeriphCLKConfig+0x2de>
+ 80082aa:	f1b3 6f80 	cmp.w	r3, #67108864	; 0x4000000
+ 80082ae:	d82e      	bhi.n	800830e <HAL_RCCEx_PeriphCLKConfig+0x2d2>
+ 80082b0:	f1b3 7f40 	cmp.w	r3, #50331648	; 0x3000000
+ 80082b4:	d033      	beq.n	800831e <HAL_RCCEx_PeriphCLKConfig+0x2e2>
+ 80082b6:	f1b3 7f40 	cmp.w	r3, #50331648	; 0x3000000
+ 80082ba:	d828      	bhi.n	800830e <HAL_RCCEx_PeriphCLKConfig+0x2d2>
+ 80082bc:	f1b3 7f00 	cmp.w	r3, #33554432	; 0x2000000
+ 80082c0:	d01a      	beq.n	80082f8 <HAL_RCCEx_PeriphCLKConfig+0x2bc>
+ 80082c2:	f1b3 7f00 	cmp.w	r3, #33554432	; 0x2000000
+ 80082c6:	d822      	bhi.n	800830e <HAL_RCCEx_PeriphCLKConfig+0x2d2>
+ 80082c8:	2b00      	cmp	r3, #0
+ 80082ca:	d003      	beq.n	80082d4 <HAL_RCCEx_PeriphCLKConfig+0x298>
+ 80082cc:	f1b3 7f80 	cmp.w	r3, #16777216	; 0x1000000
+ 80082d0:	d007      	beq.n	80082e2 <HAL_RCCEx_PeriphCLKConfig+0x2a6>
+ 80082d2:	e01c      	b.n	800830e <HAL_RCCEx_PeriphCLKConfig+0x2d2>
+    {
+      case RCC_SAI4BCLKSOURCE_PLL:      /* PLL is used as clock source for SAI2*/
+        /* Enable SAI Clock output generated form System PLL . */
+        __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
+ 80082d4:	4b1a      	ldr	r3, [pc, #104]	; (8008340 <HAL_RCCEx_PeriphCLKConfig+0x304>)
+ 80082d6:	6adb      	ldr	r3, [r3, #44]	; 0x2c
+ 80082d8:	4a19      	ldr	r2, [pc, #100]	; (8008340 <HAL_RCCEx_PeriphCLKConfig+0x304>)
+ 80082da:	f443 3300 	orr.w	r3, r3, #131072	; 0x20000
+ 80082de:	62d3      	str	r3, [r2, #44]	; 0x2c
+
+        /* SAI1 clock source configuration done later after clock selection check */
+        break;
+ 80082e0:	e01e      	b.n	8008320 <HAL_RCCEx_PeriphCLKConfig+0x2e4>
+
+      case RCC_SAI4BCLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2*/
+
+        ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE);
+ 80082e2:	f8d7 3104 	ldr.w	r3, [r7, #260]	; 0x104
+ 80082e6:	3308      	adds	r3, #8
+ 80082e8:	2100      	movs	r1, #0
+ 80082ea:	4618      	mov	r0, r3
+ 80082ec:	f002 f928 	bl	800a540 <RCCEx_PLL2_Config>
+ 80082f0:	4603      	mov	r3, r0
+ 80082f2:	f887 3117 	strb.w	r3, [r7, #279]	; 0x117
+
+        /* SAI2 clock source configuration done later after clock selection check */
+        break;
+ 80082f6:	e013      	b.n	8008320 <HAL_RCCEx_PeriphCLKConfig+0x2e4>
+
+      case RCC_SAI4BCLKSOURCE_PLL3:  /* PLL3 is used as clock source for SAI2*/
+        ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE);
+ 80082f8:	f8d7 3104 	ldr.w	r3, [r7, #260]	; 0x104
+ 80082fc:	3328      	adds	r3, #40	; 0x28
+ 80082fe:	2100      	movs	r1, #0
+ 8008300:	4618      	mov	r0, r3
+ 8008302:	f002 f9cf 	bl	800a6a4 <RCCEx_PLL3_Config>
+ 8008306:	4603      	mov	r3, r0
+ 8008308:	f887 3117 	strb.w	r3, [r7, #279]	; 0x117
+
+        /* SAI1 clock source configuration done later after clock selection check */
+        break;
+ 800830c:	e008      	b.n	8008320 <HAL_RCCEx_PeriphCLKConfig+0x2e4>
+        /* SAI4B clock source configuration done later after clock selection check */
+        break;
+#endif /* RCC_VER_3_0 */
+
+      default:
+        ret = HAL_ERROR;
+ 800830e:	2301      	movs	r3, #1
+ 8008310:	f887 3117 	strb.w	r3, [r7, #279]	; 0x117
+        break;
+ 8008314:	e004      	b.n	8008320 <HAL_RCCEx_PeriphCLKConfig+0x2e4>
+        break;
+ 8008316:	bf00      	nop
+ 8008318:	e002      	b.n	8008320 <HAL_RCCEx_PeriphCLKConfig+0x2e4>
+        break;
+ 800831a:	bf00      	nop
+ 800831c:	e000      	b.n	8008320 <HAL_RCCEx_PeriphCLKConfig+0x2e4>
+        break;
+ 800831e:	bf00      	nop
+    }
+
+    if (ret == HAL_OK)
+ 8008320:	f897 3117 	ldrb.w	r3, [r7, #279]	; 0x117
+ 8008324:	2b00      	cmp	r3, #0
+ 8008326:	d10d      	bne.n	8008344 <HAL_RCCEx_PeriphCLKConfig+0x308>
+    {
+      /* Set the source of SAI4B clock*/
+      __HAL_RCC_SAI4B_CONFIG(PeriphClkInit->Sai4BClockSelection);
+ 8008328:	4b05      	ldr	r3, [pc, #20]	; (8008340 <HAL_RCCEx_PeriphCLKConfig+0x304>)
+ 800832a:	6d9b      	ldr	r3, [r3, #88]	; 0x58
+ 800832c:	f023 61e0 	bic.w	r1, r3, #117440512	; 0x7000000
+ 8008330:	f8d7 3104 	ldr.w	r3, [r7, #260]	; 0x104
+ 8008334:	f8d3 30a8 	ldr.w	r3, [r3, #168]	; 0xa8
+ 8008338:	4a01      	ldr	r2, [pc, #4]	; (8008340 <HAL_RCCEx_PeriphCLKConfig+0x304>)
+ 800833a:	430b      	orrs	r3, r1
+ 800833c:	6593      	str	r3, [r2, #88]	; 0x58
+ 800833e:	e005      	b.n	800834c <HAL_RCCEx_PeriphCLKConfig+0x310>
+ 8008340:	58024400 	.word	0x58024400
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+ 8008344:	f897 3117 	ldrb.w	r3, [r7, #279]	; 0x117
+ 8008348:	f887 3116 	strb.w	r3, [r7, #278]	; 0x116
+  }
+#endif  /*QUADSPI*/
+
+#if defined(OCTOSPI1) || defined(OCTOSPI2)
+  /*---------------------------- OCTOSPI configuration -------------------------------*/
+  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_OSPI) == RCC_PERIPHCLK_OSPI)
+ 800834c:	f8d7 3104 	ldr.w	r3, [r7, #260]	; 0x104
+ 8008350:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 8008354:	f002 7300 	and.w	r3, r2, #33554432	; 0x2000000
+ 8008358:	f8c7 30f0 	str.w	r3, [r7, #240]	; 0xf0
+ 800835c:	2300      	movs	r3, #0
+ 800835e:	f8c7 30f4 	str.w	r3, [r7, #244]	; 0xf4
+ 8008362:	e9d7 123c 	ldrd	r1, r2, [r7, #240]	; 0xf0
+ 8008366:	460b      	mov	r3, r1
+ 8008368:	4313      	orrs	r3, r2
+ 800836a:	d03a      	beq.n	80083e2 <HAL_RCCEx_PeriphCLKConfig+0x3a6>
+  {
+    switch (PeriphClkInit->OspiClockSelection)
+ 800836c:	f8d7 3104 	ldr.w	r3, [r7, #260]	; 0x104
+ 8008370:	6cdb      	ldr	r3, [r3, #76]	; 0x4c
+ 8008372:	2b30      	cmp	r3, #48	; 0x30
+ 8008374:	d01f      	beq.n	80083b6 <HAL_RCCEx_PeriphCLKConfig+0x37a>
+ 8008376:	2b30      	cmp	r3, #48	; 0x30
+ 8008378:	d819      	bhi.n	80083ae <HAL_RCCEx_PeriphCLKConfig+0x372>
+ 800837a:	2b20      	cmp	r3, #32
+ 800837c:	d00c      	beq.n	8008398 <HAL_RCCEx_PeriphCLKConfig+0x35c>
+ 800837e:	2b20      	cmp	r3, #32
+ 8008380:	d815      	bhi.n	80083ae <HAL_RCCEx_PeriphCLKConfig+0x372>
+ 8008382:	2b00      	cmp	r3, #0
+ 8008384:	d019      	beq.n	80083ba <HAL_RCCEx_PeriphCLKConfig+0x37e>
+ 8008386:	2b10      	cmp	r3, #16
+ 8008388:	d111      	bne.n	80083ae <HAL_RCCEx_PeriphCLKConfig+0x372>
+    {
+      case RCC_OSPICLKSOURCE_PLL:      /* PLL is used as clock source for OSPI*/
+        /* Enable OSPI Clock output generated form System PLL . */
+        __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
+ 800838a:	4baa      	ldr	r3, [pc, #680]	; (8008634 <HAL_RCCEx_PeriphCLKConfig+0x5f8>)
+ 800838c:	6adb      	ldr	r3, [r3, #44]	; 0x2c
+ 800838e:	4aa9      	ldr	r2, [pc, #676]	; (8008634 <HAL_RCCEx_PeriphCLKConfig+0x5f8>)
+ 8008390:	f443 3300 	orr.w	r3, r3, #131072	; 0x20000
+ 8008394:	62d3      	str	r3, [r2, #44]	; 0x2c
+
+        /* OSPI clock source configuration done later after clock selection check */
+        break;
+ 8008396:	e011      	b.n	80083bc <HAL_RCCEx_PeriphCLKConfig+0x380>
+
+      case RCC_OSPICLKSOURCE_PLL2: /* PLL2 is used as clock source for OSPI*/
+
+        ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_R_UPDATE);
+ 8008398:	f8d7 3104 	ldr.w	r3, [r7, #260]	; 0x104
+ 800839c:	3308      	adds	r3, #8
+ 800839e:	2102      	movs	r1, #2
+ 80083a0:	4618      	mov	r0, r3
+ 80083a2:	f002 f8cd 	bl	800a540 <RCCEx_PLL2_Config>
+ 80083a6:	4603      	mov	r3, r0
+ 80083a8:	f887 3117 	strb.w	r3, [r7, #279]	; 0x117
+
+        /* OSPI clock source configuration done later after clock selection check */
+        break;
+ 80083ac:	e006      	b.n	80083bc <HAL_RCCEx_PeriphCLKConfig+0x380>
+      case RCC_OSPICLKSOURCE_HCLK:
+        /* HCLK clock selected as OSPI kernel peripheral clock */
+        break;
+
+      default:
+        ret = HAL_ERROR;
+ 80083ae:	2301      	movs	r3, #1
+ 80083b0:	f887 3117 	strb.w	r3, [r7, #279]	; 0x117
+        break;
+ 80083b4:	e002      	b.n	80083bc <HAL_RCCEx_PeriphCLKConfig+0x380>
+        break;
+ 80083b6:	bf00      	nop
+ 80083b8:	e000      	b.n	80083bc <HAL_RCCEx_PeriphCLKConfig+0x380>
+        break;
+ 80083ba:	bf00      	nop
+    }
+
+    if (ret == HAL_OK)
+ 80083bc:	f897 3117 	ldrb.w	r3, [r7, #279]	; 0x117
+ 80083c0:	2b00      	cmp	r3, #0
+ 80083c2:	d10a      	bne.n	80083da <HAL_RCCEx_PeriphCLKConfig+0x39e>
+    {
+      /* Set the source of OSPI clock*/
+      __HAL_RCC_OSPI_CONFIG(PeriphClkInit->OspiClockSelection);
+ 80083c4:	4b9b      	ldr	r3, [pc, #620]	; (8008634 <HAL_RCCEx_PeriphCLKConfig+0x5f8>)
+ 80083c6:	6cdb      	ldr	r3, [r3, #76]	; 0x4c
+ 80083c8:	f023 0130 	bic.w	r1, r3, #48	; 0x30
+ 80083cc:	f8d7 3104 	ldr.w	r3, [r7, #260]	; 0x104
+ 80083d0:	6cdb      	ldr	r3, [r3, #76]	; 0x4c
+ 80083d2:	4a98      	ldr	r2, [pc, #608]	; (8008634 <HAL_RCCEx_PeriphCLKConfig+0x5f8>)
+ 80083d4:	430b      	orrs	r3, r1
+ 80083d6:	64d3      	str	r3, [r2, #76]	; 0x4c
+ 80083d8:	e003      	b.n	80083e2 <HAL_RCCEx_PeriphCLKConfig+0x3a6>
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+ 80083da:	f897 3117 	ldrb.w	r3, [r7, #279]	; 0x117
+ 80083de:	f887 3116 	strb.w	r3, [r7, #278]	; 0x116
+    }
+  }
+#endif  /*OCTOSPI*/
+
+  /*---------------------------- SPI1/2/3 configuration -------------------------------*/
+  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI123) == RCC_PERIPHCLK_SPI123)
+ 80083e2:	f8d7 3104 	ldr.w	r3, [r7, #260]	; 0x104
+ 80083e6:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 80083ea:	f402 5380 	and.w	r3, r2, #4096	; 0x1000
+ 80083ee:	f8c7 30e8 	str.w	r3, [r7, #232]	; 0xe8
+ 80083f2:	2300      	movs	r3, #0
+ 80083f4:	f8c7 30ec 	str.w	r3, [r7, #236]	; 0xec
+ 80083f8:	e9d7 123a 	ldrd	r1, r2, [r7, #232]	; 0xe8
+ 80083fc:	460b      	mov	r3, r1
+ 80083fe:	4313      	orrs	r3, r2
+ 8008400:	d051      	beq.n	80084a6 <HAL_RCCEx_PeriphCLKConfig+0x46a>
+  {
+    switch (PeriphClkInit->Spi123ClockSelection)
+ 8008402:	f8d7 3104 	ldr.w	r3, [r7, #260]	; 0x104
+ 8008406:	6ddb      	ldr	r3, [r3, #92]	; 0x5c
+ 8008408:	f5b3 4f80 	cmp.w	r3, #16384	; 0x4000
+ 800840c:	d035      	beq.n	800847a <HAL_RCCEx_PeriphCLKConfig+0x43e>
+ 800840e:	f5b3 4f80 	cmp.w	r3, #16384	; 0x4000
+ 8008412:	d82e      	bhi.n	8008472 <HAL_RCCEx_PeriphCLKConfig+0x436>
+ 8008414:	f5b3 5f40 	cmp.w	r3, #12288	; 0x3000
+ 8008418:	d031      	beq.n	800847e <HAL_RCCEx_PeriphCLKConfig+0x442>
+ 800841a:	f5b3 5f40 	cmp.w	r3, #12288	; 0x3000
+ 800841e:	d828      	bhi.n	8008472 <HAL_RCCEx_PeriphCLKConfig+0x436>
+ 8008420:	f5b3 5f00 	cmp.w	r3, #8192	; 0x2000
+ 8008424:	d01a      	beq.n	800845c <HAL_RCCEx_PeriphCLKConfig+0x420>
+ 8008426:	f5b3 5f00 	cmp.w	r3, #8192	; 0x2000
+ 800842a:	d822      	bhi.n	8008472 <HAL_RCCEx_PeriphCLKConfig+0x436>
+ 800842c:	2b00      	cmp	r3, #0
+ 800842e:	d003      	beq.n	8008438 <HAL_RCCEx_PeriphCLKConfig+0x3fc>
+ 8008430:	f5b3 5f80 	cmp.w	r3, #4096	; 0x1000
+ 8008434:	d007      	beq.n	8008446 <HAL_RCCEx_PeriphCLKConfig+0x40a>
+ 8008436:	e01c      	b.n	8008472 <HAL_RCCEx_PeriphCLKConfig+0x436>
+    {
+      case RCC_SPI123CLKSOURCE_PLL:      /* PLL is used as clock source for SPI1/2/3 */
+        /* Enable SPI Clock output generated form System PLL . */
+        __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
+ 8008438:	4b7e      	ldr	r3, [pc, #504]	; (8008634 <HAL_RCCEx_PeriphCLKConfig+0x5f8>)
+ 800843a:	6adb      	ldr	r3, [r3, #44]	; 0x2c
+ 800843c:	4a7d      	ldr	r2, [pc, #500]	; (8008634 <HAL_RCCEx_PeriphCLKConfig+0x5f8>)
+ 800843e:	f443 3300 	orr.w	r3, r3, #131072	; 0x20000
+ 8008442:	62d3      	str	r3, [r2, #44]	; 0x2c
+
+        /* SPI1/2/3 clock source configuration done later after clock selection check */
+        break;
+ 8008444:	e01c      	b.n	8008480 <HAL_RCCEx_PeriphCLKConfig+0x444>
+
+      case RCC_SPI123CLKSOURCE_PLL2: /* PLL2 is used as clock source for SPI1/2/3 */
+        ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE);
+ 8008446:	f8d7 3104 	ldr.w	r3, [r7, #260]	; 0x104
+ 800844a:	3308      	adds	r3, #8
+ 800844c:	2100      	movs	r1, #0
+ 800844e:	4618      	mov	r0, r3
+ 8008450:	f002 f876 	bl	800a540 <RCCEx_PLL2_Config>
+ 8008454:	4603      	mov	r3, r0
+ 8008456:	f887 3117 	strb.w	r3, [r7, #279]	; 0x117
+
+        /* SPI1/2/3 clock source configuration done later after clock selection check */
+        break;
+ 800845a:	e011      	b.n	8008480 <HAL_RCCEx_PeriphCLKConfig+0x444>
+
+      case RCC_SPI123CLKSOURCE_PLL3:  /* PLL3 is used as clock source for SPI1/2/3 */
+        ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE);
+ 800845c:	f8d7 3104 	ldr.w	r3, [r7, #260]	; 0x104
+ 8008460:	3328      	adds	r3, #40	; 0x28
+ 8008462:	2100      	movs	r1, #0
+ 8008464:	4618      	mov	r0, r3
+ 8008466:	f002 f91d 	bl	800a6a4 <RCCEx_PLL3_Config>
+ 800846a:	4603      	mov	r3, r0
+ 800846c:	f887 3117 	strb.w	r3, [r7, #279]	; 0x117
+
+        /* SPI1/2/3 clock source configuration done later after clock selection check */
+        break;
+ 8008470:	e006      	b.n	8008480 <HAL_RCCEx_PeriphCLKConfig+0x444>
+        /* HSI, HSE, or CSI oscillator is used as source of SPI1/2/3 clock */
+        /* SPI1/2/3 clock source configuration done later after clock selection check */
+        break;
+
+      default:
+        ret = HAL_ERROR;
+ 8008472:	2301      	movs	r3, #1
+ 8008474:	f887 3117 	strb.w	r3, [r7, #279]	; 0x117
+        break;
+ 8008478:	e002      	b.n	8008480 <HAL_RCCEx_PeriphCLKConfig+0x444>
+        break;
+ 800847a:	bf00      	nop
+ 800847c:	e000      	b.n	8008480 <HAL_RCCEx_PeriphCLKConfig+0x444>
+        break;
+ 800847e:	bf00      	nop
+    }
+
+    if (ret == HAL_OK)
+ 8008480:	f897 3117 	ldrb.w	r3, [r7, #279]	; 0x117
+ 8008484:	2b00      	cmp	r3, #0
+ 8008486:	d10a      	bne.n	800849e <HAL_RCCEx_PeriphCLKConfig+0x462>
+    {
+      /* Set the source of SPI1/2/3 clock*/
+      __HAL_RCC_SPI123_CONFIG(PeriphClkInit->Spi123ClockSelection);
+ 8008488:	4b6a      	ldr	r3, [pc, #424]	; (8008634 <HAL_RCCEx_PeriphCLKConfig+0x5f8>)
+ 800848a:	6d1b      	ldr	r3, [r3, #80]	; 0x50
+ 800848c:	f423 41e0 	bic.w	r1, r3, #28672	; 0x7000
+ 8008490:	f8d7 3104 	ldr.w	r3, [r7, #260]	; 0x104
+ 8008494:	6ddb      	ldr	r3, [r3, #92]	; 0x5c
+ 8008496:	4a67      	ldr	r2, [pc, #412]	; (8008634 <HAL_RCCEx_PeriphCLKConfig+0x5f8>)
+ 8008498:	430b      	orrs	r3, r1
+ 800849a:	6513      	str	r3, [r2, #80]	; 0x50
+ 800849c:	e003      	b.n	80084a6 <HAL_RCCEx_PeriphCLKConfig+0x46a>
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+ 800849e:	f897 3117 	ldrb.w	r3, [r7, #279]	; 0x117
+ 80084a2:	f887 3116 	strb.w	r3, [r7, #278]	; 0x116
+    }
+  }
+
+  /*---------------------------- SPI4/5 configuration -------------------------------*/
+  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI45) == RCC_PERIPHCLK_SPI45)
+ 80084a6:	f8d7 3104 	ldr.w	r3, [r7, #260]	; 0x104
+ 80084aa:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 80084ae:	f402 5300 	and.w	r3, r2, #8192	; 0x2000
+ 80084b2:	f8c7 30e0 	str.w	r3, [r7, #224]	; 0xe0
+ 80084b6:	2300      	movs	r3, #0
+ 80084b8:	f8c7 30e4 	str.w	r3, [r7, #228]	; 0xe4
+ 80084bc:	e9d7 1238 	ldrd	r1, r2, [r7, #224]	; 0xe0
+ 80084c0:	460b      	mov	r3, r1
+ 80084c2:	4313      	orrs	r3, r2
+ 80084c4:	d053      	beq.n	800856e <HAL_RCCEx_PeriphCLKConfig+0x532>
+  {
+    switch (PeriphClkInit->Spi45ClockSelection)
+ 80084c6:	f8d7 3104 	ldr.w	r3, [r7, #260]	; 0x104
+ 80084ca:	6e1b      	ldr	r3, [r3, #96]	; 0x60
+ 80084cc:	f5b3 2fa0 	cmp.w	r3, #327680	; 0x50000
+ 80084d0:	d033      	beq.n	800853a <HAL_RCCEx_PeriphCLKConfig+0x4fe>
+ 80084d2:	f5b3 2fa0 	cmp.w	r3, #327680	; 0x50000
+ 80084d6:	d82c      	bhi.n	8008532 <HAL_RCCEx_PeriphCLKConfig+0x4f6>
+ 80084d8:	f5b3 2f80 	cmp.w	r3, #262144	; 0x40000
+ 80084dc:	d02f      	beq.n	800853e <HAL_RCCEx_PeriphCLKConfig+0x502>
+ 80084de:	f5b3 2f80 	cmp.w	r3, #262144	; 0x40000
+ 80084e2:	d826      	bhi.n	8008532 <HAL_RCCEx_PeriphCLKConfig+0x4f6>
+ 80084e4:	f5b3 3f40 	cmp.w	r3, #196608	; 0x30000
+ 80084e8:	d02b      	beq.n	8008542 <HAL_RCCEx_PeriphCLKConfig+0x506>
+ 80084ea:	f5b3 3f40 	cmp.w	r3, #196608	; 0x30000
+ 80084ee:	d820      	bhi.n	8008532 <HAL_RCCEx_PeriphCLKConfig+0x4f6>
+ 80084f0:	f5b3 3f00 	cmp.w	r3, #131072	; 0x20000
+ 80084f4:	d012      	beq.n	800851c <HAL_RCCEx_PeriphCLKConfig+0x4e0>
+ 80084f6:	f5b3 3f00 	cmp.w	r3, #131072	; 0x20000
+ 80084fa:	d81a      	bhi.n	8008532 <HAL_RCCEx_PeriphCLKConfig+0x4f6>
+ 80084fc:	2b00      	cmp	r3, #0
+ 80084fe:	d022      	beq.n	8008546 <HAL_RCCEx_PeriphCLKConfig+0x50a>
+ 8008500:	f5b3 3f80 	cmp.w	r3, #65536	; 0x10000
+ 8008504:	d115      	bne.n	8008532 <HAL_RCCEx_PeriphCLKConfig+0x4f6>
+        /* SPI4/5 clock source configuration done later after clock selection check */
+        break;
+
+      case RCC_SPI45CLKSOURCE_PLL2: /* PLL2 is used as clock source for SPI4/5 */
+
+        ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE);
+ 8008506:	f8d7 3104 	ldr.w	r3, [r7, #260]	; 0x104
+ 800850a:	3308      	adds	r3, #8
+ 800850c:	2101      	movs	r1, #1
+ 800850e:	4618      	mov	r0, r3
+ 8008510:	f002 f816 	bl	800a540 <RCCEx_PLL2_Config>
+ 8008514:	4603      	mov	r3, r0
+ 8008516:	f887 3117 	strb.w	r3, [r7, #279]	; 0x117
+
+        /* SPI4/5 clock source configuration done later after clock selection check */
+        break;
+ 800851a:	e015      	b.n	8008548 <HAL_RCCEx_PeriphCLKConfig+0x50c>
+      case RCC_SPI45CLKSOURCE_PLL3:  /* PLL3 is used as clock source for SPI4/5 */
+        ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE);
+ 800851c:	f8d7 3104 	ldr.w	r3, [r7, #260]	; 0x104
+ 8008520:	3328      	adds	r3, #40	; 0x28
+ 8008522:	2101      	movs	r1, #1
+ 8008524:	4618      	mov	r0, r3
+ 8008526:	f002 f8bd 	bl	800a6a4 <RCCEx_PLL3_Config>
+ 800852a:	4603      	mov	r3, r0
+ 800852c:	f887 3117 	strb.w	r3, [r7, #279]	; 0x117
+        /* SPI4/5 clock source configuration done later after clock selection check */
+        break;
+ 8008530:	e00a      	b.n	8008548 <HAL_RCCEx_PeriphCLKConfig+0x50c>
+        /* HSE,  oscillator is used as source of SPI4/5 clock */
+        /* SPI4/5 clock source configuration done later after clock selection check */
+        break;
+
+      default:
+        ret = HAL_ERROR;
+ 8008532:	2301      	movs	r3, #1
+ 8008534:	f887 3117 	strb.w	r3, [r7, #279]	; 0x117
+        break;
+ 8008538:	e006      	b.n	8008548 <HAL_RCCEx_PeriphCLKConfig+0x50c>
+        break;
+ 800853a:	bf00      	nop
+ 800853c:	e004      	b.n	8008548 <HAL_RCCEx_PeriphCLKConfig+0x50c>
+        break;
+ 800853e:	bf00      	nop
+ 8008540:	e002      	b.n	8008548 <HAL_RCCEx_PeriphCLKConfig+0x50c>
+        break;
+ 8008542:	bf00      	nop
+ 8008544:	e000      	b.n	8008548 <HAL_RCCEx_PeriphCLKConfig+0x50c>
+        break;
+ 8008546:	bf00      	nop
+    }
+
+    if (ret == HAL_OK)
+ 8008548:	f897 3117 	ldrb.w	r3, [r7, #279]	; 0x117
+ 800854c:	2b00      	cmp	r3, #0
+ 800854e:	d10a      	bne.n	8008566 <HAL_RCCEx_PeriphCLKConfig+0x52a>
+    {
+      /* Set the source of SPI4/5 clock*/
+      __HAL_RCC_SPI45_CONFIG(PeriphClkInit->Spi45ClockSelection);
+ 8008550:	4b38      	ldr	r3, [pc, #224]	; (8008634 <HAL_RCCEx_PeriphCLKConfig+0x5f8>)
+ 8008552:	6d1b      	ldr	r3, [r3, #80]	; 0x50
+ 8008554:	f423 21e0 	bic.w	r1, r3, #458752	; 0x70000
+ 8008558:	f8d7 3104 	ldr.w	r3, [r7, #260]	; 0x104
+ 800855c:	6e1b      	ldr	r3, [r3, #96]	; 0x60
+ 800855e:	4a35      	ldr	r2, [pc, #212]	; (8008634 <HAL_RCCEx_PeriphCLKConfig+0x5f8>)
+ 8008560:	430b      	orrs	r3, r1
+ 8008562:	6513      	str	r3, [r2, #80]	; 0x50
+ 8008564:	e003      	b.n	800856e <HAL_RCCEx_PeriphCLKConfig+0x532>
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+ 8008566:	f897 3117 	ldrb.w	r3, [r7, #279]	; 0x117
+ 800856a:	f887 3116 	strb.w	r3, [r7, #278]	; 0x116
+    }
+  }
+
+  /*---------------------------- SPI6 configuration -------------------------------*/
+  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI6) == RCC_PERIPHCLK_SPI6)
+ 800856e:	f8d7 3104 	ldr.w	r3, [r7, #260]	; 0x104
+ 8008572:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 8008576:	f402 4380 	and.w	r3, r2, #16384	; 0x4000
+ 800857a:	f8c7 30d8 	str.w	r3, [r7, #216]	; 0xd8
+ 800857e:	2300      	movs	r3, #0
+ 8008580:	f8c7 30dc 	str.w	r3, [r7, #220]	; 0xdc
+ 8008584:	e9d7 1236 	ldrd	r1, r2, [r7, #216]	; 0xd8
+ 8008588:	460b      	mov	r3, r1
+ 800858a:	4313      	orrs	r3, r2
+ 800858c:	d058      	beq.n	8008640 <HAL_RCCEx_PeriphCLKConfig+0x604>
+  {
+    switch (PeriphClkInit->Spi6ClockSelection)
+ 800858e:	f8d7 3104 	ldr.w	r3, [r7, #260]	; 0x104
+ 8008592:	f8d3 30ac 	ldr.w	r3, [r3, #172]	; 0xac
+ 8008596:	f1b3 4fa0 	cmp.w	r3, #1342177280	; 0x50000000
+ 800859a:	d033      	beq.n	8008604 <HAL_RCCEx_PeriphCLKConfig+0x5c8>
+ 800859c:	f1b3 4fa0 	cmp.w	r3, #1342177280	; 0x50000000
+ 80085a0:	d82c      	bhi.n	80085fc <HAL_RCCEx_PeriphCLKConfig+0x5c0>
+ 80085a2:	f1b3 4f80 	cmp.w	r3, #1073741824	; 0x40000000
+ 80085a6:	d02f      	beq.n	8008608 <HAL_RCCEx_PeriphCLKConfig+0x5cc>
+ 80085a8:	f1b3 4f80 	cmp.w	r3, #1073741824	; 0x40000000
+ 80085ac:	d826      	bhi.n	80085fc <HAL_RCCEx_PeriphCLKConfig+0x5c0>
+ 80085ae:	f1b3 5f40 	cmp.w	r3, #805306368	; 0x30000000
+ 80085b2:	d02b      	beq.n	800860c <HAL_RCCEx_PeriphCLKConfig+0x5d0>
+ 80085b4:	f1b3 5f40 	cmp.w	r3, #805306368	; 0x30000000
+ 80085b8:	d820      	bhi.n	80085fc <HAL_RCCEx_PeriphCLKConfig+0x5c0>
+ 80085ba:	f1b3 5f00 	cmp.w	r3, #536870912	; 0x20000000
+ 80085be:	d012      	beq.n	80085e6 <HAL_RCCEx_PeriphCLKConfig+0x5aa>
+ 80085c0:	f1b3 5f00 	cmp.w	r3, #536870912	; 0x20000000
+ 80085c4:	d81a      	bhi.n	80085fc <HAL_RCCEx_PeriphCLKConfig+0x5c0>
+ 80085c6:	2b00      	cmp	r3, #0
+ 80085c8:	d022      	beq.n	8008610 <HAL_RCCEx_PeriphCLKConfig+0x5d4>
+ 80085ca:	f1b3 5f80 	cmp.w	r3, #268435456	; 0x10000000
+ 80085ce:	d115      	bne.n	80085fc <HAL_RCCEx_PeriphCLKConfig+0x5c0>
+        /* SPI6 clock source configuration done later after clock selection check */
+        break;
+
+      case RCC_SPI6CLKSOURCE_PLL2: /* PLL2 is used as clock source for SPI6*/
+
+        ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE);
+ 80085d0:	f8d7 3104 	ldr.w	r3, [r7, #260]	; 0x104
+ 80085d4:	3308      	adds	r3, #8
+ 80085d6:	2101      	movs	r1, #1
+ 80085d8:	4618      	mov	r0, r3
+ 80085da:	f001 ffb1 	bl	800a540 <RCCEx_PLL2_Config>
+ 80085de:	4603      	mov	r3, r0
+ 80085e0:	f887 3117 	strb.w	r3, [r7, #279]	; 0x117
+
+        /* SPI6 clock source configuration done later after clock selection check */
+        break;
+ 80085e4:	e015      	b.n	8008612 <HAL_RCCEx_PeriphCLKConfig+0x5d6>
+      case RCC_SPI6CLKSOURCE_PLL3:  /* PLL3 is used as clock source for SPI6*/
+        ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE);
+ 80085e6:	f8d7 3104 	ldr.w	r3, [r7, #260]	; 0x104
+ 80085ea:	3328      	adds	r3, #40	; 0x28
+ 80085ec:	2101      	movs	r1, #1
+ 80085ee:	4618      	mov	r0, r3
+ 80085f0:	f002 f858 	bl	800a6a4 <RCCEx_PLL3_Config>
+ 80085f4:	4603      	mov	r3, r0
+ 80085f6:	f887 3117 	strb.w	r3, [r7, #279]	; 0x117
+        /* SPI6 clock source configuration done later after clock selection check */
+        break;
+ 80085fa:	e00a      	b.n	8008612 <HAL_RCCEx_PeriphCLKConfig+0x5d6>
+        /* SPI6 clock source configuration done later after clock selection check */
+        break;
+#endif
+
+      default:
+        ret = HAL_ERROR;
+ 80085fc:	2301      	movs	r3, #1
+ 80085fe:	f887 3117 	strb.w	r3, [r7, #279]	; 0x117
+        break;
+ 8008602:	e006      	b.n	8008612 <HAL_RCCEx_PeriphCLKConfig+0x5d6>
+        break;
+ 8008604:	bf00      	nop
+ 8008606:	e004      	b.n	8008612 <HAL_RCCEx_PeriphCLKConfig+0x5d6>
+        break;
+ 8008608:	bf00      	nop
+ 800860a:	e002      	b.n	8008612 <HAL_RCCEx_PeriphCLKConfig+0x5d6>
+        break;
+ 800860c:	bf00      	nop
+ 800860e:	e000      	b.n	8008612 <HAL_RCCEx_PeriphCLKConfig+0x5d6>
+        break;
+ 8008610:	bf00      	nop
+    }
+
+    if (ret == HAL_OK)
+ 8008612:	f897 3117 	ldrb.w	r3, [r7, #279]	; 0x117
+ 8008616:	2b00      	cmp	r3, #0
+ 8008618:	d10e      	bne.n	8008638 <HAL_RCCEx_PeriphCLKConfig+0x5fc>
+    {
+      /* Set the source of SPI6 clock*/
+      __HAL_RCC_SPI6_CONFIG(PeriphClkInit->Spi6ClockSelection);
+ 800861a:	4b06      	ldr	r3, [pc, #24]	; (8008634 <HAL_RCCEx_PeriphCLKConfig+0x5f8>)
+ 800861c:	6d9b      	ldr	r3, [r3, #88]	; 0x58
+ 800861e:	f023 41e0 	bic.w	r1, r3, #1879048192	; 0x70000000
+ 8008622:	f8d7 3104 	ldr.w	r3, [r7, #260]	; 0x104
+ 8008626:	f8d3 30ac 	ldr.w	r3, [r3, #172]	; 0xac
+ 800862a:	4a02      	ldr	r2, [pc, #8]	; (8008634 <HAL_RCCEx_PeriphCLKConfig+0x5f8>)
+ 800862c:	430b      	orrs	r3, r1
+ 800862e:	6593      	str	r3, [r2, #88]	; 0x58
+ 8008630:	e006      	b.n	8008640 <HAL_RCCEx_PeriphCLKConfig+0x604>
+ 8008632:	bf00      	nop
+ 8008634:	58024400 	.word	0x58024400
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+ 8008638:	f897 3117 	ldrb.w	r3, [r7, #279]	; 0x117
+ 800863c:	f887 3116 	strb.w	r3, [r7, #278]	; 0x116
+  }
+#endif /*DSI*/
+
+#if defined(FDCAN1) || defined(FDCAN2)
+  /*---------------------------- FDCAN configuration -------------------------------*/
+  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN)
+ 8008640:	f8d7 3104 	ldr.w	r3, [r7, #260]	; 0x104
+ 8008644:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 8008648:	f402 4300 	and.w	r3, r2, #32768	; 0x8000
+ 800864c:	f8c7 30d0 	str.w	r3, [r7, #208]	; 0xd0
+ 8008650:	2300      	movs	r3, #0
+ 8008652:	f8c7 30d4 	str.w	r3, [r7, #212]	; 0xd4
+ 8008656:	e9d7 1234 	ldrd	r1, r2, [r7, #208]	; 0xd0
+ 800865a:	460b      	mov	r3, r1
+ 800865c:	4313      	orrs	r3, r2
+ 800865e:	d037      	beq.n	80086d0 <HAL_RCCEx_PeriphCLKConfig+0x694>
+  {
+    switch (PeriphClkInit->FdcanClockSelection)
+ 8008660:	f8d7 3104 	ldr.w	r3, [r7, #260]	; 0x104
+ 8008664:	6edb      	ldr	r3, [r3, #108]	; 0x6c
+ 8008666:	f1b3 5f00 	cmp.w	r3, #536870912	; 0x20000000
+ 800866a:	d00e      	beq.n	800868a <HAL_RCCEx_PeriphCLKConfig+0x64e>
+ 800866c:	f1b3 5f00 	cmp.w	r3, #536870912	; 0x20000000
+ 8008670:	d816      	bhi.n	80086a0 <HAL_RCCEx_PeriphCLKConfig+0x664>
+ 8008672:	2b00      	cmp	r3, #0
+ 8008674:	d018      	beq.n	80086a8 <HAL_RCCEx_PeriphCLKConfig+0x66c>
+ 8008676:	f1b3 5f80 	cmp.w	r3, #268435456	; 0x10000000
+ 800867a:	d111      	bne.n	80086a0 <HAL_RCCEx_PeriphCLKConfig+0x664>
+    {
+      case RCC_FDCANCLKSOURCE_PLL:      /* PLL is used as clock source for FDCAN*/
+        /* Enable FDCAN Clock output generated form System PLL . */
+        __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
+ 800867c:	4bc4      	ldr	r3, [pc, #784]	; (8008990 <HAL_RCCEx_PeriphCLKConfig+0x954>)
+ 800867e:	6adb      	ldr	r3, [r3, #44]	; 0x2c
+ 8008680:	4ac3      	ldr	r2, [pc, #780]	; (8008990 <HAL_RCCEx_PeriphCLKConfig+0x954>)
+ 8008682:	f443 3300 	orr.w	r3, r3, #131072	; 0x20000
+ 8008686:	62d3      	str	r3, [r2, #44]	; 0x2c
+
+        /* FDCAN clock source configuration done later after clock selection check */
+        break;
+ 8008688:	e00f      	b.n	80086aa <HAL_RCCEx_PeriphCLKConfig+0x66e>
+
+      case RCC_FDCANCLKSOURCE_PLL2: /* PLL2 is used as clock source for FDCAN*/
+
+        ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE);
+ 800868a:	f8d7 3104 	ldr.w	r3, [r7, #260]	; 0x104
+ 800868e:	3308      	adds	r3, #8
+ 8008690:	2101      	movs	r1, #1
+ 8008692:	4618      	mov	r0, r3
+ 8008694:	f001 ff54 	bl	800a540 <RCCEx_PLL2_Config>
+ 8008698:	4603      	mov	r3, r0
+ 800869a:	f887 3117 	strb.w	r3, [r7, #279]	; 0x117
+
+        /* FDCAN clock source configuration done later after clock selection check */
+        break;
+ 800869e:	e004      	b.n	80086aa <HAL_RCCEx_PeriphCLKConfig+0x66e>
+        /* HSE is used as clock source for FDCAN*/
+        /* FDCAN clock source configuration done later after clock selection check */
+        break;
+
+      default:
+        ret = HAL_ERROR;
+ 80086a0:	2301      	movs	r3, #1
+ 80086a2:	f887 3117 	strb.w	r3, [r7, #279]	; 0x117
+        break;
+ 80086a6:	e000      	b.n	80086aa <HAL_RCCEx_PeriphCLKConfig+0x66e>
+        break;
+ 80086a8:	bf00      	nop
+    }
+
+    if (ret == HAL_OK)
+ 80086aa:	f897 3117 	ldrb.w	r3, [r7, #279]	; 0x117
+ 80086ae:	2b00      	cmp	r3, #0
+ 80086b0:	d10a      	bne.n	80086c8 <HAL_RCCEx_PeriphCLKConfig+0x68c>
+    {
+      /* Set the source of FDCAN clock*/
+      __HAL_RCC_FDCAN_CONFIG(PeriphClkInit->FdcanClockSelection);
+ 80086b2:	4bb7      	ldr	r3, [pc, #732]	; (8008990 <HAL_RCCEx_PeriphCLKConfig+0x954>)
+ 80086b4:	6d1b      	ldr	r3, [r3, #80]	; 0x50
+ 80086b6:	f023 5140 	bic.w	r1, r3, #805306368	; 0x30000000
+ 80086ba:	f8d7 3104 	ldr.w	r3, [r7, #260]	; 0x104
+ 80086be:	6edb      	ldr	r3, [r3, #108]	; 0x6c
+ 80086c0:	4ab3      	ldr	r2, [pc, #716]	; (8008990 <HAL_RCCEx_PeriphCLKConfig+0x954>)
+ 80086c2:	430b      	orrs	r3, r1
+ 80086c4:	6513      	str	r3, [r2, #80]	; 0x50
+ 80086c6:	e003      	b.n	80086d0 <HAL_RCCEx_PeriphCLKConfig+0x694>
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+ 80086c8:	f897 3117 	ldrb.w	r3, [r7, #279]	; 0x117
+ 80086cc:	f887 3116 	strb.w	r3, [r7, #278]	; 0x116
+    }
+  }
+#endif /*FDCAN1 || FDCAN2*/
+
+  /*---------------------------- FMC configuration -------------------------------*/
+  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMC) == RCC_PERIPHCLK_FMC)
+ 80086d0:	f8d7 3104 	ldr.w	r3, [r7, #260]	; 0x104
+ 80086d4:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 80086d8:	f002 7380 	and.w	r3, r2, #16777216	; 0x1000000
+ 80086dc:	f8c7 30c8 	str.w	r3, [r7, #200]	; 0xc8
+ 80086e0:	2300      	movs	r3, #0
+ 80086e2:	f8c7 30cc 	str.w	r3, [r7, #204]	; 0xcc
+ 80086e6:	e9d7 1232 	ldrd	r1, r2, [r7, #200]	; 0xc8
+ 80086ea:	460b      	mov	r3, r1
+ 80086ec:	4313      	orrs	r3, r2
+ 80086ee:	d039      	beq.n	8008764 <HAL_RCCEx_PeriphCLKConfig+0x728>
+  {
+    switch (PeriphClkInit->FmcClockSelection)
+ 80086f0:	f8d7 3104 	ldr.w	r3, [r7, #260]	; 0x104
+ 80086f4:	6c9b      	ldr	r3, [r3, #72]	; 0x48
+ 80086f6:	2b03      	cmp	r3, #3
+ 80086f8:	d81c      	bhi.n	8008734 <HAL_RCCEx_PeriphCLKConfig+0x6f8>
+ 80086fa:	a201      	add	r2, pc, #4	; (adr r2, 8008700 <HAL_RCCEx_PeriphCLKConfig+0x6c4>)
+ 80086fc:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
+ 8008700:	0800873d 	.word	0x0800873d
+ 8008704:	08008711 	.word	0x08008711
+ 8008708:	0800871f 	.word	0x0800871f
+ 800870c:	0800873d 	.word	0x0800873d
+    {
+      case RCC_FMCCLKSOURCE_PLL:      /* PLL is used as clock source for FMC*/
+        /* Enable FMC Clock output generated form System PLL . */
+        __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
+ 8008710:	4b9f      	ldr	r3, [pc, #636]	; (8008990 <HAL_RCCEx_PeriphCLKConfig+0x954>)
+ 8008712:	6adb      	ldr	r3, [r3, #44]	; 0x2c
+ 8008714:	4a9e      	ldr	r2, [pc, #632]	; (8008990 <HAL_RCCEx_PeriphCLKConfig+0x954>)
+ 8008716:	f443 3300 	orr.w	r3, r3, #131072	; 0x20000
+ 800871a:	62d3      	str	r3, [r2, #44]	; 0x2c
+
+        /* FMC clock source configuration done later after clock selection check */
+        break;
+ 800871c:	e00f      	b.n	800873e <HAL_RCCEx_PeriphCLKConfig+0x702>
+
+      case RCC_FMCCLKSOURCE_PLL2: /* PLL2 is used as clock source for FMC*/
+
+        ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_R_UPDATE);
+ 800871e:	f8d7 3104 	ldr.w	r3, [r7, #260]	; 0x104
+ 8008722:	3308      	adds	r3, #8
+ 8008724:	2102      	movs	r1, #2
+ 8008726:	4618      	mov	r0, r3
+ 8008728:	f001 ff0a 	bl	800a540 <RCCEx_PLL2_Config>
+ 800872c:	4603      	mov	r3, r0
+ 800872e:	f887 3117 	strb.w	r3, [r7, #279]	; 0x117
+
+        /* FMC clock source configuration done later after clock selection check */
+        break;
+ 8008732:	e004      	b.n	800873e <HAL_RCCEx_PeriphCLKConfig+0x702>
+      case RCC_FMCCLKSOURCE_HCLK:
+        /* D1/CD HCLK  clock selected as FMC kernel peripheral clock */
+        break;
+
+      default:
+        ret = HAL_ERROR;
+ 8008734:	2301      	movs	r3, #1
+ 8008736:	f887 3117 	strb.w	r3, [r7, #279]	; 0x117
+        break;
+ 800873a:	e000      	b.n	800873e <HAL_RCCEx_PeriphCLKConfig+0x702>
+        break;
+ 800873c:	bf00      	nop
+    }
+
+    if (ret == HAL_OK)
+ 800873e:	f897 3117 	ldrb.w	r3, [r7, #279]	; 0x117
+ 8008742:	2b00      	cmp	r3, #0
+ 8008744:	d10a      	bne.n	800875c <HAL_RCCEx_PeriphCLKConfig+0x720>
+    {
+      /* Set the source of FMC clock*/
+      __HAL_RCC_FMC_CONFIG(PeriphClkInit->FmcClockSelection);
+ 8008746:	4b92      	ldr	r3, [pc, #584]	; (8008990 <HAL_RCCEx_PeriphCLKConfig+0x954>)
+ 8008748:	6cdb      	ldr	r3, [r3, #76]	; 0x4c
+ 800874a:	f023 0103 	bic.w	r1, r3, #3
+ 800874e:	f8d7 3104 	ldr.w	r3, [r7, #260]	; 0x104
+ 8008752:	6c9b      	ldr	r3, [r3, #72]	; 0x48
+ 8008754:	4a8e      	ldr	r2, [pc, #568]	; (8008990 <HAL_RCCEx_PeriphCLKConfig+0x954>)
+ 8008756:	430b      	orrs	r3, r1
+ 8008758:	64d3      	str	r3, [r2, #76]	; 0x4c
+ 800875a:	e003      	b.n	8008764 <HAL_RCCEx_PeriphCLKConfig+0x728>
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+ 800875c:	f897 3117 	ldrb.w	r3, [r7, #279]	; 0x117
+ 8008760:	f887 3116 	strb.w	r3, [r7, #278]	; 0x116
+    }
+  }
+
+  /*---------------------------- RTC configuration -------------------------------*/
+  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)
+ 8008764:	f8d7 3104 	ldr.w	r3, [r7, #260]	; 0x104
+ 8008768:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 800876c:	f402 0380 	and.w	r3, r2, #4194304	; 0x400000
+ 8008770:	f8c7 30c0 	str.w	r3, [r7, #192]	; 0xc0
+ 8008774:	2300      	movs	r3, #0
+ 8008776:	f8c7 30c4 	str.w	r3, [r7, #196]	; 0xc4
+ 800877a:	e9d7 1230 	ldrd	r1, r2, [r7, #192]	; 0xc0
+ 800877e:	460b      	mov	r3, r1
+ 8008780:	4313      	orrs	r3, r2
+ 8008782:	f000 8099 	beq.w	80088b8 <HAL_RCCEx_PeriphCLKConfig+0x87c>
+  {
+    /* check for RTC Parameters used to output RTCCLK */
+    assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
+
+    /* Enable write access to Backup domain */
+    SET_BIT(PWR->CR1, PWR_CR1_DBP);
+ 8008786:	4b83      	ldr	r3, [pc, #524]	; (8008994 <HAL_RCCEx_PeriphCLKConfig+0x958>)
+ 8008788:	681b      	ldr	r3, [r3, #0]
+ 800878a:	4a82      	ldr	r2, [pc, #520]	; (8008994 <HAL_RCCEx_PeriphCLKConfig+0x958>)
+ 800878c:	f443 7380 	orr.w	r3, r3, #256	; 0x100
+ 8008790:	6013      	str	r3, [r2, #0]
+
+    /* Wait for Backup domain Write protection disable */
+    tickstart = HAL_GetTick();
+ 8008792:	f7f9 fde7 	bl	8002364 <HAL_GetTick>
+ 8008796:	f8c7 0110 	str.w	r0, [r7, #272]	; 0x110
+
+    while ((PWR->CR1 & PWR_CR1_DBP) == 0U)
+ 800879a:	e00b      	b.n	80087b4 <HAL_RCCEx_PeriphCLKConfig+0x778>
+    {
+      if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
+ 800879c:	f7f9 fde2 	bl	8002364 <HAL_GetTick>
+ 80087a0:	4602      	mov	r2, r0
+ 80087a2:	f8d7 3110 	ldr.w	r3, [r7, #272]	; 0x110
+ 80087a6:	1ad3      	subs	r3, r2, r3
+ 80087a8:	2b64      	cmp	r3, #100	; 0x64
+ 80087aa:	d903      	bls.n	80087b4 <HAL_RCCEx_PeriphCLKConfig+0x778>
+      {
+        ret = HAL_TIMEOUT;
+ 80087ac:	2303      	movs	r3, #3
+ 80087ae:	f887 3117 	strb.w	r3, [r7, #279]	; 0x117
+        break;
+ 80087b2:	e005      	b.n	80087c0 <HAL_RCCEx_PeriphCLKConfig+0x784>
+    while ((PWR->CR1 & PWR_CR1_DBP) == 0U)
+ 80087b4:	4b77      	ldr	r3, [pc, #476]	; (8008994 <HAL_RCCEx_PeriphCLKConfig+0x958>)
+ 80087b6:	681b      	ldr	r3, [r3, #0]
+ 80087b8:	f403 7380 	and.w	r3, r3, #256	; 0x100
+ 80087bc:	2b00      	cmp	r3, #0
+ 80087be:	d0ed      	beq.n	800879c <HAL_RCCEx_PeriphCLKConfig+0x760>
+      }
+    }
+
+    if (ret == HAL_OK)
+ 80087c0:	f897 3117 	ldrb.w	r3, [r7, #279]	; 0x117
+ 80087c4:	2b00      	cmp	r3, #0
+ 80087c6:	d173      	bne.n	80088b0 <HAL_RCCEx_PeriphCLKConfig+0x874>
+    {
+      /* Reset the Backup domain only if the RTC Clock source selection is modified */
+      if ((RCC->BDCR & RCC_BDCR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))
+ 80087c8:	4b71      	ldr	r3, [pc, #452]	; (8008990 <HAL_RCCEx_PeriphCLKConfig+0x954>)
+ 80087ca:	6f1a      	ldr	r2, [r3, #112]	; 0x70
+ 80087cc:	f8d7 3104 	ldr.w	r3, [r7, #260]	; 0x104
+ 80087d0:	f8d3 30b0 	ldr.w	r3, [r3, #176]	; 0xb0
+ 80087d4:	4053      	eors	r3, r2
+ 80087d6:	f403 7340 	and.w	r3, r3, #768	; 0x300
+ 80087da:	2b00      	cmp	r3, #0
+ 80087dc:	d015      	beq.n	800880a <HAL_RCCEx_PeriphCLKConfig+0x7ce>
+      {
+        /* Store the content of BDCR register before the reset of Backup Domain */
+        tmpreg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
+ 80087de:	4b6c      	ldr	r3, [pc, #432]	; (8008990 <HAL_RCCEx_PeriphCLKConfig+0x954>)
+ 80087e0:	6f1b      	ldr	r3, [r3, #112]	; 0x70
+ 80087e2:	f423 7340 	bic.w	r3, r3, #768	; 0x300
+ 80087e6:	f8c7 310c 	str.w	r3, [r7, #268]	; 0x10c
+        /* RTC Clock selection can be changed only if the Backup Domain is reset */
+        __HAL_RCC_BACKUPRESET_FORCE();
+ 80087ea:	4b69      	ldr	r3, [pc, #420]	; (8008990 <HAL_RCCEx_PeriphCLKConfig+0x954>)
+ 80087ec:	6f1b      	ldr	r3, [r3, #112]	; 0x70
+ 80087ee:	4a68      	ldr	r2, [pc, #416]	; (8008990 <HAL_RCCEx_PeriphCLKConfig+0x954>)
+ 80087f0:	f443 3380 	orr.w	r3, r3, #65536	; 0x10000
+ 80087f4:	6713      	str	r3, [r2, #112]	; 0x70
+        __HAL_RCC_BACKUPRESET_RELEASE();
+ 80087f6:	4b66      	ldr	r3, [pc, #408]	; (8008990 <HAL_RCCEx_PeriphCLKConfig+0x954>)
+ 80087f8:	6f1b      	ldr	r3, [r3, #112]	; 0x70
+ 80087fa:	4a65      	ldr	r2, [pc, #404]	; (8008990 <HAL_RCCEx_PeriphCLKConfig+0x954>)
+ 80087fc:	f423 3380 	bic.w	r3, r3, #65536	; 0x10000
+ 8008800:	6713      	str	r3, [r2, #112]	; 0x70
+        /* Restore the Content of BDCR register */
+        RCC->BDCR = tmpreg;
+ 8008802:	4a63      	ldr	r2, [pc, #396]	; (8008990 <HAL_RCCEx_PeriphCLKConfig+0x954>)
+ 8008804:	f8d7 310c 	ldr.w	r3, [r7, #268]	; 0x10c
+ 8008808:	6713      	str	r3, [r2, #112]	; 0x70
+      }
+
+      /* If LSE is selected as RTC clock source (and enabled prior to Backup Domain reset), wait for LSE reactivation */
+      if (PeriphClkInit->RTCClockSelection == RCC_RTCCLKSOURCE_LSE)
+ 800880a:	f8d7 3104 	ldr.w	r3, [r7, #260]	; 0x104
+ 800880e:	f8d3 30b0 	ldr.w	r3, [r3, #176]	; 0xb0
+ 8008812:	f5b3 7f80 	cmp.w	r3, #256	; 0x100
+ 8008816:	d118      	bne.n	800884a <HAL_RCCEx_PeriphCLKConfig+0x80e>
+      {
+        /* Get Start Tick*/
+        tickstart = HAL_GetTick();
+ 8008818:	f7f9 fda4 	bl	8002364 <HAL_GetTick>
+ 800881c:	f8c7 0110 	str.w	r0, [r7, #272]	; 0x110
+
+        /* Wait till LSE is ready */
+        while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U)
+ 8008820:	e00d      	b.n	800883e <HAL_RCCEx_PeriphCLKConfig+0x802>
+        {
+          if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
+ 8008822:	f7f9 fd9f 	bl	8002364 <HAL_GetTick>
+ 8008826:	4602      	mov	r2, r0
+ 8008828:	f8d7 3110 	ldr.w	r3, [r7, #272]	; 0x110
+ 800882c:	1ad2      	subs	r2, r2, r3
+ 800882e:	f241 3388 	movw	r3, #5000	; 0x1388
+ 8008832:	429a      	cmp	r2, r3
+ 8008834:	d903      	bls.n	800883e <HAL_RCCEx_PeriphCLKConfig+0x802>
+          {
+            ret = HAL_TIMEOUT;
+ 8008836:	2303      	movs	r3, #3
+ 8008838:	f887 3117 	strb.w	r3, [r7, #279]	; 0x117
+            break;
+ 800883c:	e005      	b.n	800884a <HAL_RCCEx_PeriphCLKConfig+0x80e>
+        while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U)
+ 800883e:	4b54      	ldr	r3, [pc, #336]	; (8008990 <HAL_RCCEx_PeriphCLKConfig+0x954>)
+ 8008840:	6f1b      	ldr	r3, [r3, #112]	; 0x70
+ 8008842:	f003 0302 	and.w	r3, r3, #2
+ 8008846:	2b00      	cmp	r3, #0
+ 8008848:	d0eb      	beq.n	8008822 <HAL_RCCEx_PeriphCLKConfig+0x7e6>
+          }
+        }
+      }
+
+      if (ret == HAL_OK)
+ 800884a:	f897 3117 	ldrb.w	r3, [r7, #279]	; 0x117
+ 800884e:	2b00      	cmp	r3, #0
+ 8008850:	d129      	bne.n	80088a6 <HAL_RCCEx_PeriphCLKConfig+0x86a>
+      {
+        __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
+ 8008852:	f8d7 3104 	ldr.w	r3, [r7, #260]	; 0x104
+ 8008856:	f8d3 30b0 	ldr.w	r3, [r3, #176]	; 0xb0
+ 800885a:	f403 7340 	and.w	r3, r3, #768	; 0x300
+ 800885e:	f5b3 7f40 	cmp.w	r3, #768	; 0x300
+ 8008862:	d10e      	bne.n	8008882 <HAL_RCCEx_PeriphCLKConfig+0x846>
+ 8008864:	4b4a      	ldr	r3, [pc, #296]	; (8008990 <HAL_RCCEx_PeriphCLKConfig+0x954>)
+ 8008866:	691b      	ldr	r3, [r3, #16]
+ 8008868:	f423 517c 	bic.w	r1, r3, #16128	; 0x3f00
+ 800886c:	f8d7 3104 	ldr.w	r3, [r7, #260]	; 0x104
+ 8008870:	f8d3 30b0 	ldr.w	r3, [r3, #176]	; 0xb0
+ 8008874:	091a      	lsrs	r2, r3, #4
+ 8008876:	4b48      	ldr	r3, [pc, #288]	; (8008998 <HAL_RCCEx_PeriphCLKConfig+0x95c>)
+ 8008878:	4013      	ands	r3, r2
+ 800887a:	4a45      	ldr	r2, [pc, #276]	; (8008990 <HAL_RCCEx_PeriphCLKConfig+0x954>)
+ 800887c:	430b      	orrs	r3, r1
+ 800887e:	6113      	str	r3, [r2, #16]
+ 8008880:	e005      	b.n	800888e <HAL_RCCEx_PeriphCLKConfig+0x852>
+ 8008882:	4b43      	ldr	r3, [pc, #268]	; (8008990 <HAL_RCCEx_PeriphCLKConfig+0x954>)
+ 8008884:	691b      	ldr	r3, [r3, #16]
+ 8008886:	4a42      	ldr	r2, [pc, #264]	; (8008990 <HAL_RCCEx_PeriphCLKConfig+0x954>)
+ 8008888:	f423 537c 	bic.w	r3, r3, #16128	; 0x3f00
+ 800888c:	6113      	str	r3, [r2, #16]
+ 800888e:	4b40      	ldr	r3, [pc, #256]	; (8008990 <HAL_RCCEx_PeriphCLKConfig+0x954>)
+ 8008890:	6f19      	ldr	r1, [r3, #112]	; 0x70
+ 8008892:	f8d7 3104 	ldr.w	r3, [r7, #260]	; 0x104
+ 8008896:	f8d3 30b0 	ldr.w	r3, [r3, #176]	; 0xb0
+ 800889a:	f3c3 030b 	ubfx	r3, r3, #0, #12
+ 800889e:	4a3c      	ldr	r2, [pc, #240]	; (8008990 <HAL_RCCEx_PeriphCLKConfig+0x954>)
+ 80088a0:	430b      	orrs	r3, r1
+ 80088a2:	6713      	str	r3, [r2, #112]	; 0x70
+ 80088a4:	e008      	b.n	80088b8 <HAL_RCCEx_PeriphCLKConfig+0x87c>
+      }
+      else
+      {
+        /* set overall return value */
+        status = ret;
+ 80088a6:	f897 3117 	ldrb.w	r3, [r7, #279]	; 0x117
+ 80088aa:	f887 3116 	strb.w	r3, [r7, #278]	; 0x116
+ 80088ae:	e003      	b.n	80088b8 <HAL_RCCEx_PeriphCLKConfig+0x87c>
+      }
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+ 80088b0:	f897 3117 	ldrb.w	r3, [r7, #279]	; 0x117
+ 80088b4:	f887 3116 	strb.w	r3, [r7, #278]	; 0x116
+    }
+  }
+
+
+  /*-------------------------- USART1/6 configuration --------------------------*/
+  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART16) == RCC_PERIPHCLK_USART16)
+ 80088b8:	f8d7 3104 	ldr.w	r3, [r7, #260]	; 0x104
+ 80088bc:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 80088c0:	f002 0301 	and.w	r3, r2, #1
+ 80088c4:	f8c7 30b8 	str.w	r3, [r7, #184]	; 0xb8
+ 80088c8:	2300      	movs	r3, #0
+ 80088ca:	f8c7 30bc 	str.w	r3, [r7, #188]	; 0xbc
+ 80088ce:	e9d7 122e 	ldrd	r1, r2, [r7, #184]	; 0xb8
+ 80088d2:	460b      	mov	r3, r1
+ 80088d4:	4313      	orrs	r3, r2
+ 80088d6:	f000 808f 	beq.w	80089f8 <HAL_RCCEx_PeriphCLKConfig+0x9bc>
+  {
+    switch (PeriphClkInit->Usart16ClockSelection)
+ 80088da:	f8d7 3104 	ldr.w	r3, [r7, #260]	; 0x104
+ 80088de:	6f9b      	ldr	r3, [r3, #120]	; 0x78
+ 80088e0:	2b28      	cmp	r3, #40	; 0x28
+ 80088e2:	d871      	bhi.n	80089c8 <HAL_RCCEx_PeriphCLKConfig+0x98c>
+ 80088e4:	a201      	add	r2, pc, #4	; (adr r2, 80088ec <HAL_RCCEx_PeriphCLKConfig+0x8b0>)
+ 80088e6:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
+ 80088ea:	bf00      	nop
+ 80088ec:	080089d1 	.word	0x080089d1
+ 80088f0:	080089c9 	.word	0x080089c9
+ 80088f4:	080089c9 	.word	0x080089c9
+ 80088f8:	080089c9 	.word	0x080089c9
+ 80088fc:	080089c9 	.word	0x080089c9
+ 8008900:	080089c9 	.word	0x080089c9
+ 8008904:	080089c9 	.word	0x080089c9
+ 8008908:	080089c9 	.word	0x080089c9
+ 800890c:	0800899d 	.word	0x0800899d
+ 8008910:	080089c9 	.word	0x080089c9
+ 8008914:	080089c9 	.word	0x080089c9
+ 8008918:	080089c9 	.word	0x080089c9
+ 800891c:	080089c9 	.word	0x080089c9
+ 8008920:	080089c9 	.word	0x080089c9
+ 8008924:	080089c9 	.word	0x080089c9
+ 8008928:	080089c9 	.word	0x080089c9
+ 800892c:	080089b3 	.word	0x080089b3
+ 8008930:	080089c9 	.word	0x080089c9
+ 8008934:	080089c9 	.word	0x080089c9
+ 8008938:	080089c9 	.word	0x080089c9
+ 800893c:	080089c9 	.word	0x080089c9
+ 8008940:	080089c9 	.word	0x080089c9
+ 8008944:	080089c9 	.word	0x080089c9
+ 8008948:	080089c9 	.word	0x080089c9
+ 800894c:	080089d1 	.word	0x080089d1
+ 8008950:	080089c9 	.word	0x080089c9
+ 8008954:	080089c9 	.word	0x080089c9
+ 8008958:	080089c9 	.word	0x080089c9
+ 800895c:	080089c9 	.word	0x080089c9
+ 8008960:	080089c9 	.word	0x080089c9
+ 8008964:	080089c9 	.word	0x080089c9
+ 8008968:	080089c9 	.word	0x080089c9
+ 800896c:	080089d1 	.word	0x080089d1
+ 8008970:	080089c9 	.word	0x080089c9
+ 8008974:	080089c9 	.word	0x080089c9
+ 8008978:	080089c9 	.word	0x080089c9
+ 800897c:	080089c9 	.word	0x080089c9
+ 8008980:	080089c9 	.word	0x080089c9
+ 8008984:	080089c9 	.word	0x080089c9
+ 8008988:	080089c9 	.word	0x080089c9
+ 800898c:	080089d1 	.word	0x080089d1
+ 8008990:	58024400 	.word	0x58024400
+ 8008994:	58024800 	.word	0x58024800
+ 8008998:	00ffffcf 	.word	0x00ffffcf
+      case RCC_USART16CLKSOURCE_PCLK2: /* CD/D2 PCLK2 as clock source for USART1/6 */
+        /* USART1/6 clock source configuration done later after clock selection check */
+        break;
+
+      case RCC_USART16CLKSOURCE_PLL2: /* PLL2 is used as clock source for USART1/6 */
+        ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE);
+ 800899c:	f8d7 3104 	ldr.w	r3, [r7, #260]	; 0x104
+ 80089a0:	3308      	adds	r3, #8
+ 80089a2:	2101      	movs	r1, #1
+ 80089a4:	4618      	mov	r0, r3
+ 80089a6:	f001 fdcb 	bl	800a540 <RCCEx_PLL2_Config>
+ 80089aa:	4603      	mov	r3, r0
+ 80089ac:	f887 3117 	strb.w	r3, [r7, #279]	; 0x117
+        /* USART1/6 clock source configuration done later after clock selection check */
+        break;
+ 80089b0:	e00f      	b.n	80089d2 <HAL_RCCEx_PeriphCLKConfig+0x996>
+
+      case RCC_USART16CLKSOURCE_PLL3: /* PLL3 is used as clock source for USART1/6 */
+        ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE);
+ 80089b2:	f8d7 3104 	ldr.w	r3, [r7, #260]	; 0x104
+ 80089b6:	3328      	adds	r3, #40	; 0x28
+ 80089b8:	2101      	movs	r1, #1
+ 80089ba:	4618      	mov	r0, r3
+ 80089bc:	f001 fe72 	bl	800a6a4 <RCCEx_PLL3_Config>
+ 80089c0:	4603      	mov	r3, r0
+ 80089c2:	f887 3117 	strb.w	r3, [r7, #279]	; 0x117
+        /* USART1/6 clock source configuration done later after clock selection check */
+        break;
+ 80089c6:	e004      	b.n	80089d2 <HAL_RCCEx_PeriphCLKConfig+0x996>
+        /* LSE,  oscillator is used as source of USART1/6 clock */
+        /* USART1/6 clock source configuration done later after clock selection check */
+        break;
+
+      default:
+        ret = HAL_ERROR;
+ 80089c8:	2301      	movs	r3, #1
+ 80089ca:	f887 3117 	strb.w	r3, [r7, #279]	; 0x117
+        break;
+ 80089ce:	e000      	b.n	80089d2 <HAL_RCCEx_PeriphCLKConfig+0x996>
+        break;
+ 80089d0:	bf00      	nop
+    }
+
+    if (ret == HAL_OK)
+ 80089d2:	f897 3117 	ldrb.w	r3, [r7, #279]	; 0x117
+ 80089d6:	2b00      	cmp	r3, #0
+ 80089d8:	d10a      	bne.n	80089f0 <HAL_RCCEx_PeriphCLKConfig+0x9b4>
+    {
+      /* Set the source of USART1/6 clock */
+      __HAL_RCC_USART16_CONFIG(PeriphClkInit->Usart16ClockSelection);
+ 80089da:	4bbf      	ldr	r3, [pc, #764]	; (8008cd8 <HAL_RCCEx_PeriphCLKConfig+0xc9c>)
+ 80089dc:	6d5b      	ldr	r3, [r3, #84]	; 0x54
+ 80089de:	f023 0138 	bic.w	r1, r3, #56	; 0x38
+ 80089e2:	f8d7 3104 	ldr.w	r3, [r7, #260]	; 0x104
+ 80089e6:	6f9b      	ldr	r3, [r3, #120]	; 0x78
+ 80089e8:	4abb      	ldr	r2, [pc, #748]	; (8008cd8 <HAL_RCCEx_PeriphCLKConfig+0xc9c>)
+ 80089ea:	430b      	orrs	r3, r1
+ 80089ec:	6553      	str	r3, [r2, #84]	; 0x54
+ 80089ee:	e003      	b.n	80089f8 <HAL_RCCEx_PeriphCLKConfig+0x9bc>
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+ 80089f0:	f897 3117 	ldrb.w	r3, [r7, #279]	; 0x117
+ 80089f4:	f887 3116 	strb.w	r3, [r7, #278]	; 0x116
+    }
+  }
+
+  /*-------------------------- USART2/3/4/5/7/8 Configuration --------------------------*/
+  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART234578) == RCC_PERIPHCLK_USART234578)
+ 80089f8:	f8d7 3104 	ldr.w	r3, [r7, #260]	; 0x104
+ 80089fc:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 8008a00:	f002 0302 	and.w	r3, r2, #2
+ 8008a04:	f8c7 30b0 	str.w	r3, [r7, #176]	; 0xb0
+ 8008a08:	2300      	movs	r3, #0
+ 8008a0a:	f8c7 30b4 	str.w	r3, [r7, #180]	; 0xb4
+ 8008a0e:	e9d7 122c 	ldrd	r1, r2, [r7, #176]	; 0xb0
+ 8008a12:	460b      	mov	r3, r1
+ 8008a14:	4313      	orrs	r3, r2
+ 8008a16:	d041      	beq.n	8008a9c <HAL_RCCEx_PeriphCLKConfig+0xa60>
+  {
+    switch (PeriphClkInit->Usart234578ClockSelection)
+ 8008a18:	f8d7 3104 	ldr.w	r3, [r7, #260]	; 0x104
+ 8008a1c:	6f5b      	ldr	r3, [r3, #116]	; 0x74
+ 8008a1e:	2b05      	cmp	r3, #5
+ 8008a20:	d824      	bhi.n	8008a6c <HAL_RCCEx_PeriphCLKConfig+0xa30>
+ 8008a22:	a201      	add	r2, pc, #4	; (adr r2, 8008a28 <HAL_RCCEx_PeriphCLKConfig+0x9ec>)
+ 8008a24:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
+ 8008a28:	08008a75 	.word	0x08008a75
+ 8008a2c:	08008a41 	.word	0x08008a41
+ 8008a30:	08008a57 	.word	0x08008a57
+ 8008a34:	08008a75 	.word	0x08008a75
+ 8008a38:	08008a75 	.word	0x08008a75
+ 8008a3c:	08008a75 	.word	0x08008a75
+      case RCC_USART234578CLKSOURCE_PCLK1: /* CD/D2 PCLK1 as clock source for USART2/3/4/5/7/8 */
+        /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */
+        break;
+
+      case RCC_USART234578CLKSOURCE_PLL2: /* PLL2 is used as clock source for USART2/3/4/5/7/8 */
+        ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE);
+ 8008a40:	f8d7 3104 	ldr.w	r3, [r7, #260]	; 0x104
+ 8008a44:	3308      	adds	r3, #8
+ 8008a46:	2101      	movs	r1, #1
+ 8008a48:	4618      	mov	r0, r3
+ 8008a4a:	f001 fd79 	bl	800a540 <RCCEx_PLL2_Config>
+ 8008a4e:	4603      	mov	r3, r0
+ 8008a50:	f887 3117 	strb.w	r3, [r7, #279]	; 0x117
+        /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */
+        break;
+ 8008a54:	e00f      	b.n	8008a76 <HAL_RCCEx_PeriphCLKConfig+0xa3a>
+
+      case RCC_USART234578CLKSOURCE_PLL3: /* PLL3 is used as clock source for USART2/3/4/5/7/8 */
+        ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE);
+ 8008a56:	f8d7 3104 	ldr.w	r3, [r7, #260]	; 0x104
+ 8008a5a:	3328      	adds	r3, #40	; 0x28
+ 8008a5c:	2101      	movs	r1, #1
+ 8008a5e:	4618      	mov	r0, r3
+ 8008a60:	f001 fe20 	bl	800a6a4 <RCCEx_PLL3_Config>
+ 8008a64:	4603      	mov	r3, r0
+ 8008a66:	f887 3117 	strb.w	r3, [r7, #279]	; 0x117
+        /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */
+        break;
+ 8008a6a:	e004      	b.n	8008a76 <HAL_RCCEx_PeriphCLKConfig+0xa3a>
+        /* LSE,  oscillator is used as source of USART2/3/4/5/7/8 clock */
+        /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */
+        break;
+
+      default:
+        ret = HAL_ERROR;
+ 8008a6c:	2301      	movs	r3, #1
+ 8008a6e:	f887 3117 	strb.w	r3, [r7, #279]	; 0x117
+        break;
+ 8008a72:	e000      	b.n	8008a76 <HAL_RCCEx_PeriphCLKConfig+0xa3a>
+        break;
+ 8008a74:	bf00      	nop
+    }
+
+    if (ret == HAL_OK)
+ 8008a76:	f897 3117 	ldrb.w	r3, [r7, #279]	; 0x117
+ 8008a7a:	2b00      	cmp	r3, #0
+ 8008a7c:	d10a      	bne.n	8008a94 <HAL_RCCEx_PeriphCLKConfig+0xa58>
+    {
+      /* Set the source of USART2/3/4/5/7/8 clock */
+      __HAL_RCC_USART234578_CONFIG(PeriphClkInit->Usart234578ClockSelection);
+ 8008a7e:	4b96      	ldr	r3, [pc, #600]	; (8008cd8 <HAL_RCCEx_PeriphCLKConfig+0xc9c>)
+ 8008a80:	6d5b      	ldr	r3, [r3, #84]	; 0x54
+ 8008a82:	f023 0107 	bic.w	r1, r3, #7
+ 8008a86:	f8d7 3104 	ldr.w	r3, [r7, #260]	; 0x104
+ 8008a8a:	6f5b      	ldr	r3, [r3, #116]	; 0x74
+ 8008a8c:	4a92      	ldr	r2, [pc, #584]	; (8008cd8 <HAL_RCCEx_PeriphCLKConfig+0xc9c>)
+ 8008a8e:	430b      	orrs	r3, r1
+ 8008a90:	6553      	str	r3, [r2, #84]	; 0x54
+ 8008a92:	e003      	b.n	8008a9c <HAL_RCCEx_PeriphCLKConfig+0xa60>
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+ 8008a94:	f897 3117 	ldrb.w	r3, [r7, #279]	; 0x117
+ 8008a98:	f887 3116 	strb.w	r3, [r7, #278]	; 0x116
+    }
+  }
+
+  /*-------------------------- LPUART1 Configuration -------------------------*/
+  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1)
+ 8008a9c:	f8d7 3104 	ldr.w	r3, [r7, #260]	; 0x104
+ 8008aa0:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 8008aa4:	f002 0304 	and.w	r3, r2, #4
+ 8008aa8:	f8c7 30a8 	str.w	r3, [r7, #168]	; 0xa8
+ 8008aac:	2300      	movs	r3, #0
+ 8008aae:	f8c7 30ac 	str.w	r3, [r7, #172]	; 0xac
+ 8008ab2:	e9d7 122a 	ldrd	r1, r2, [r7, #168]	; 0xa8
+ 8008ab6:	460b      	mov	r3, r1
+ 8008ab8:	4313      	orrs	r3, r2
+ 8008aba:	d044      	beq.n	8008b46 <HAL_RCCEx_PeriphCLKConfig+0xb0a>
+  {
+    switch (PeriphClkInit->Lpuart1ClockSelection)
+ 8008abc:	f8d7 3104 	ldr.w	r3, [r7, #260]	; 0x104
+ 8008ac0:	f8d3 3090 	ldr.w	r3, [r3, #144]	; 0x90
+ 8008ac4:	2b05      	cmp	r3, #5
+ 8008ac6:	d825      	bhi.n	8008b14 <HAL_RCCEx_PeriphCLKConfig+0xad8>
+ 8008ac8:	a201      	add	r2, pc, #4	; (adr r2, 8008ad0 <HAL_RCCEx_PeriphCLKConfig+0xa94>)
+ 8008aca:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
+ 8008ace:	bf00      	nop
+ 8008ad0:	08008b1d 	.word	0x08008b1d
+ 8008ad4:	08008ae9 	.word	0x08008ae9
+ 8008ad8:	08008aff 	.word	0x08008aff
+ 8008adc:	08008b1d 	.word	0x08008b1d
+ 8008ae0:	08008b1d 	.word	0x08008b1d
+ 8008ae4:	08008b1d 	.word	0x08008b1d
+      case RCC_LPUART1CLKSOURCE_PCLK4: /* SRD/D3 PCLK1 (PCLK4) as clock source for LPUART1 */
+        /* LPUART1 clock source configuration done later after clock selection check */
+        break;
+
+      case RCC_LPUART1CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPUART1 */
+        ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE);
+ 8008ae8:	f8d7 3104 	ldr.w	r3, [r7, #260]	; 0x104
+ 8008aec:	3308      	adds	r3, #8
+ 8008aee:	2101      	movs	r1, #1
+ 8008af0:	4618      	mov	r0, r3
+ 8008af2:	f001 fd25 	bl	800a540 <RCCEx_PLL2_Config>
+ 8008af6:	4603      	mov	r3, r0
+ 8008af8:	f887 3117 	strb.w	r3, [r7, #279]	; 0x117
+        /* LPUART1 clock source configuration done later after clock selection check */
+        break;
+ 8008afc:	e00f      	b.n	8008b1e <HAL_RCCEx_PeriphCLKConfig+0xae2>
+
+      case RCC_LPUART1CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPUART1 */
+        ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE);
+ 8008afe:	f8d7 3104 	ldr.w	r3, [r7, #260]	; 0x104
+ 8008b02:	3328      	adds	r3, #40	; 0x28
+ 8008b04:	2101      	movs	r1, #1
+ 8008b06:	4618      	mov	r0, r3
+ 8008b08:	f001 fdcc 	bl	800a6a4 <RCCEx_PLL3_Config>
+ 8008b0c:	4603      	mov	r3, r0
+ 8008b0e:	f887 3117 	strb.w	r3, [r7, #279]	; 0x117
+        /* LPUART1 clock source configuration done later after clock selection check */
+        break;
+ 8008b12:	e004      	b.n	8008b1e <HAL_RCCEx_PeriphCLKConfig+0xae2>
+        /* LSE,  oscillator is used as source of LPUART1 clock */
+        /* LPUART1 clock source configuration done later after clock selection check */
+        break;
+
+      default:
+        ret = HAL_ERROR;
+ 8008b14:	2301      	movs	r3, #1
+ 8008b16:	f887 3117 	strb.w	r3, [r7, #279]	; 0x117
+        break;
+ 8008b1a:	e000      	b.n	8008b1e <HAL_RCCEx_PeriphCLKConfig+0xae2>
+        break;
+ 8008b1c:	bf00      	nop
+    }
+
+    if (ret == HAL_OK)
+ 8008b1e:	f897 3117 	ldrb.w	r3, [r7, #279]	; 0x117
+ 8008b22:	2b00      	cmp	r3, #0
+ 8008b24:	d10b      	bne.n	8008b3e <HAL_RCCEx_PeriphCLKConfig+0xb02>
+    {
+      /* Set the source of LPUART1 clock */
+      __HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection);
+ 8008b26:	4b6c      	ldr	r3, [pc, #432]	; (8008cd8 <HAL_RCCEx_PeriphCLKConfig+0xc9c>)
+ 8008b28:	6d9b      	ldr	r3, [r3, #88]	; 0x58
+ 8008b2a:	f023 0107 	bic.w	r1, r3, #7
+ 8008b2e:	f8d7 3104 	ldr.w	r3, [r7, #260]	; 0x104
+ 8008b32:	f8d3 3090 	ldr.w	r3, [r3, #144]	; 0x90
+ 8008b36:	4a68      	ldr	r2, [pc, #416]	; (8008cd8 <HAL_RCCEx_PeriphCLKConfig+0xc9c>)
+ 8008b38:	430b      	orrs	r3, r1
+ 8008b3a:	6593      	str	r3, [r2, #88]	; 0x58
+ 8008b3c:	e003      	b.n	8008b46 <HAL_RCCEx_PeriphCLKConfig+0xb0a>
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+ 8008b3e:	f897 3117 	ldrb.w	r3, [r7, #279]	; 0x117
+ 8008b42:	f887 3116 	strb.w	r3, [r7, #278]	; 0x116
+    }
+  }
+
+  /*---------------------------- LPTIM1 configuration -------------------------------*/
+  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1)
+ 8008b46:	f8d7 3104 	ldr.w	r3, [r7, #260]	; 0x104
+ 8008b4a:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 8008b4e:	f002 0320 	and.w	r3, r2, #32
+ 8008b52:	f8c7 30a0 	str.w	r3, [r7, #160]	; 0xa0
+ 8008b56:	2300      	movs	r3, #0
+ 8008b58:	f8c7 30a4 	str.w	r3, [r7, #164]	; 0xa4
+ 8008b5c:	e9d7 1228 	ldrd	r1, r2, [r7, #160]	; 0xa0
+ 8008b60:	460b      	mov	r3, r1
+ 8008b62:	4313      	orrs	r3, r2
+ 8008b64:	d055      	beq.n	8008c12 <HAL_RCCEx_PeriphCLKConfig+0xbd6>
+  {
+    switch (PeriphClkInit->Lptim1ClockSelection)
+ 8008b66:	f8d7 3104 	ldr.w	r3, [r7, #260]	; 0x104
+ 8008b6a:	f8d3 308c 	ldr.w	r3, [r3, #140]	; 0x8c
+ 8008b6e:	f1b3 4fa0 	cmp.w	r3, #1342177280	; 0x50000000
+ 8008b72:	d033      	beq.n	8008bdc <HAL_RCCEx_PeriphCLKConfig+0xba0>
+ 8008b74:	f1b3 4fa0 	cmp.w	r3, #1342177280	; 0x50000000
+ 8008b78:	d82c      	bhi.n	8008bd4 <HAL_RCCEx_PeriphCLKConfig+0xb98>
+ 8008b7a:	f1b3 4f80 	cmp.w	r3, #1073741824	; 0x40000000
+ 8008b7e:	d02f      	beq.n	8008be0 <HAL_RCCEx_PeriphCLKConfig+0xba4>
+ 8008b80:	f1b3 4f80 	cmp.w	r3, #1073741824	; 0x40000000
+ 8008b84:	d826      	bhi.n	8008bd4 <HAL_RCCEx_PeriphCLKConfig+0xb98>
+ 8008b86:	f1b3 5f40 	cmp.w	r3, #805306368	; 0x30000000
+ 8008b8a:	d02b      	beq.n	8008be4 <HAL_RCCEx_PeriphCLKConfig+0xba8>
+ 8008b8c:	f1b3 5f40 	cmp.w	r3, #805306368	; 0x30000000
+ 8008b90:	d820      	bhi.n	8008bd4 <HAL_RCCEx_PeriphCLKConfig+0xb98>
+ 8008b92:	f1b3 5f00 	cmp.w	r3, #536870912	; 0x20000000
+ 8008b96:	d012      	beq.n	8008bbe <HAL_RCCEx_PeriphCLKConfig+0xb82>
+ 8008b98:	f1b3 5f00 	cmp.w	r3, #536870912	; 0x20000000
+ 8008b9c:	d81a      	bhi.n	8008bd4 <HAL_RCCEx_PeriphCLKConfig+0xb98>
+ 8008b9e:	2b00      	cmp	r3, #0
+ 8008ba0:	d022      	beq.n	8008be8 <HAL_RCCEx_PeriphCLKConfig+0xbac>
+ 8008ba2:	f1b3 5f80 	cmp.w	r3, #268435456	; 0x10000000
+ 8008ba6:	d115      	bne.n	8008bd4 <HAL_RCCEx_PeriphCLKConfig+0xb98>
+        /* LPTIM1 clock source configuration done later after clock selection check */
+        break;
+
+      case RCC_LPTIM1CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPTIM1*/
+
+        ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE);
+ 8008ba8:	f8d7 3104 	ldr.w	r3, [r7, #260]	; 0x104
+ 8008bac:	3308      	adds	r3, #8
+ 8008bae:	2100      	movs	r1, #0
+ 8008bb0:	4618      	mov	r0, r3
+ 8008bb2:	f001 fcc5 	bl	800a540 <RCCEx_PLL2_Config>
+ 8008bb6:	4603      	mov	r3, r0
+ 8008bb8:	f887 3117 	strb.w	r3, [r7, #279]	; 0x117
+
+        /* LPTIM1 clock source configuration done later after clock selection check */
+        break;
+ 8008bbc:	e015      	b.n	8008bea <HAL_RCCEx_PeriphCLKConfig+0xbae>
+
+      case RCC_LPTIM1CLKSOURCE_PLL3:  /* PLL3 is used as clock source for LPTIM1*/
+        ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE);
+ 8008bbe:	f8d7 3104 	ldr.w	r3, [r7, #260]	; 0x104
+ 8008bc2:	3328      	adds	r3, #40	; 0x28
+ 8008bc4:	2102      	movs	r1, #2
+ 8008bc6:	4618      	mov	r0, r3
+ 8008bc8:	f001 fd6c 	bl	800a6a4 <RCCEx_PLL3_Config>
+ 8008bcc:	4603      	mov	r3, r0
+ 8008bce:	f887 3117 	strb.w	r3, [r7, #279]	; 0x117
+
+        /* LPTIM1 clock source configuration done later after clock selection check */
+        break;
+ 8008bd2:	e00a      	b.n	8008bea <HAL_RCCEx_PeriphCLKConfig+0xbae>
+        /* HSI, HSE, or CSI oscillator is used as source of LPTIM1 clock */
+        /* LPTIM1 clock source configuration done later after clock selection check */
+        break;
+
+      default:
+        ret = HAL_ERROR;
+ 8008bd4:	2301      	movs	r3, #1
+ 8008bd6:	f887 3117 	strb.w	r3, [r7, #279]	; 0x117
+        break;
+ 8008bda:	e006      	b.n	8008bea <HAL_RCCEx_PeriphCLKConfig+0xbae>
+        break;
+ 8008bdc:	bf00      	nop
+ 8008bde:	e004      	b.n	8008bea <HAL_RCCEx_PeriphCLKConfig+0xbae>
+        break;
+ 8008be0:	bf00      	nop
+ 8008be2:	e002      	b.n	8008bea <HAL_RCCEx_PeriphCLKConfig+0xbae>
+        break;
+ 8008be4:	bf00      	nop
+ 8008be6:	e000      	b.n	8008bea <HAL_RCCEx_PeriphCLKConfig+0xbae>
+        break;
+ 8008be8:	bf00      	nop
+    }
+
+    if (ret == HAL_OK)
+ 8008bea:	f897 3117 	ldrb.w	r3, [r7, #279]	; 0x117
+ 8008bee:	2b00      	cmp	r3, #0
+ 8008bf0:	d10b      	bne.n	8008c0a <HAL_RCCEx_PeriphCLKConfig+0xbce>
+    {
+      /* Set the source of LPTIM1 clock*/
+      __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);
+ 8008bf2:	4b39      	ldr	r3, [pc, #228]	; (8008cd8 <HAL_RCCEx_PeriphCLKConfig+0xc9c>)
+ 8008bf4:	6d5b      	ldr	r3, [r3, #84]	; 0x54
+ 8008bf6:	f023 41e0 	bic.w	r1, r3, #1879048192	; 0x70000000
+ 8008bfa:	f8d7 3104 	ldr.w	r3, [r7, #260]	; 0x104
+ 8008bfe:	f8d3 308c 	ldr.w	r3, [r3, #140]	; 0x8c
+ 8008c02:	4a35      	ldr	r2, [pc, #212]	; (8008cd8 <HAL_RCCEx_PeriphCLKConfig+0xc9c>)
+ 8008c04:	430b      	orrs	r3, r1
+ 8008c06:	6553      	str	r3, [r2, #84]	; 0x54
+ 8008c08:	e003      	b.n	8008c12 <HAL_RCCEx_PeriphCLKConfig+0xbd6>
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+ 8008c0a:	f897 3117 	ldrb.w	r3, [r7, #279]	; 0x117
+ 8008c0e:	f887 3116 	strb.w	r3, [r7, #278]	; 0x116
+    }
+  }
+
+  /*---------------------------- LPTIM2 configuration -------------------------------*/
+  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2)
+ 8008c12:	f8d7 3104 	ldr.w	r3, [r7, #260]	; 0x104
+ 8008c16:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 8008c1a:	f002 0340 	and.w	r3, r2, #64	; 0x40
+ 8008c1e:	f8c7 3098 	str.w	r3, [r7, #152]	; 0x98
+ 8008c22:	2300      	movs	r3, #0
+ 8008c24:	f8c7 309c 	str.w	r3, [r7, #156]	; 0x9c
+ 8008c28:	e9d7 1226 	ldrd	r1, r2, [r7, #152]	; 0x98
+ 8008c2c:	460b      	mov	r3, r1
+ 8008c2e:	4313      	orrs	r3, r2
+ 8008c30:	d058      	beq.n	8008ce4 <HAL_RCCEx_PeriphCLKConfig+0xca8>
+  {
+    switch (PeriphClkInit->Lptim2ClockSelection)
+ 8008c32:	f8d7 3104 	ldr.w	r3, [r7, #260]	; 0x104
+ 8008c36:	f8d3 3098 	ldr.w	r3, [r3, #152]	; 0x98
+ 8008c3a:	f5b3 5fa0 	cmp.w	r3, #5120	; 0x1400
+ 8008c3e:	d033      	beq.n	8008ca8 <HAL_RCCEx_PeriphCLKConfig+0xc6c>
+ 8008c40:	f5b3 5fa0 	cmp.w	r3, #5120	; 0x1400
+ 8008c44:	d82c      	bhi.n	8008ca0 <HAL_RCCEx_PeriphCLKConfig+0xc64>
+ 8008c46:	f5b3 5f80 	cmp.w	r3, #4096	; 0x1000
+ 8008c4a:	d02f      	beq.n	8008cac <HAL_RCCEx_PeriphCLKConfig+0xc70>
+ 8008c4c:	f5b3 5f80 	cmp.w	r3, #4096	; 0x1000
+ 8008c50:	d826      	bhi.n	8008ca0 <HAL_RCCEx_PeriphCLKConfig+0xc64>
+ 8008c52:	f5b3 6f40 	cmp.w	r3, #3072	; 0xc00
+ 8008c56:	d02b      	beq.n	8008cb0 <HAL_RCCEx_PeriphCLKConfig+0xc74>
+ 8008c58:	f5b3 6f40 	cmp.w	r3, #3072	; 0xc00
+ 8008c5c:	d820      	bhi.n	8008ca0 <HAL_RCCEx_PeriphCLKConfig+0xc64>
+ 8008c5e:	f5b3 6f00 	cmp.w	r3, #2048	; 0x800
+ 8008c62:	d012      	beq.n	8008c8a <HAL_RCCEx_PeriphCLKConfig+0xc4e>
+ 8008c64:	f5b3 6f00 	cmp.w	r3, #2048	; 0x800
+ 8008c68:	d81a      	bhi.n	8008ca0 <HAL_RCCEx_PeriphCLKConfig+0xc64>
+ 8008c6a:	2b00      	cmp	r3, #0
+ 8008c6c:	d022      	beq.n	8008cb4 <HAL_RCCEx_PeriphCLKConfig+0xc78>
+ 8008c6e:	f5b3 6f80 	cmp.w	r3, #1024	; 0x400
+ 8008c72:	d115      	bne.n	8008ca0 <HAL_RCCEx_PeriphCLKConfig+0xc64>
+        /* LPTIM2 clock source configuration done later after clock selection check */
+        break;
+
+      case RCC_LPTIM2CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPTIM2*/
+
+        ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE);
+ 8008c74:	f8d7 3104 	ldr.w	r3, [r7, #260]	; 0x104
+ 8008c78:	3308      	adds	r3, #8
+ 8008c7a:	2100      	movs	r1, #0
+ 8008c7c:	4618      	mov	r0, r3
+ 8008c7e:	f001 fc5f 	bl	800a540 <RCCEx_PLL2_Config>
+ 8008c82:	4603      	mov	r3, r0
+ 8008c84:	f887 3117 	strb.w	r3, [r7, #279]	; 0x117
+
+        /* LPTIM2 clock source configuration done later after clock selection check */
+        break;
+ 8008c88:	e015      	b.n	8008cb6 <HAL_RCCEx_PeriphCLKConfig+0xc7a>
+
+      case RCC_LPTIM2CLKSOURCE_PLL3:  /* PLL3 is used as clock source for LPTIM2*/
+        ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE);
+ 8008c8a:	f8d7 3104 	ldr.w	r3, [r7, #260]	; 0x104
+ 8008c8e:	3328      	adds	r3, #40	; 0x28
+ 8008c90:	2102      	movs	r1, #2
+ 8008c92:	4618      	mov	r0, r3
+ 8008c94:	f001 fd06 	bl	800a6a4 <RCCEx_PLL3_Config>
+ 8008c98:	4603      	mov	r3, r0
+ 8008c9a:	f887 3117 	strb.w	r3, [r7, #279]	; 0x117
+
+        /* LPTIM2 clock source configuration done later after clock selection check */
+        break;
+ 8008c9e:	e00a      	b.n	8008cb6 <HAL_RCCEx_PeriphCLKConfig+0xc7a>
+        /* HSI, HSE, or CSI oscillator is used as source of LPTIM2 clock */
+        /* LPTIM2 clock source configuration done later after clock selection check */
+        break;
+
+      default:
+        ret = HAL_ERROR;
+ 8008ca0:	2301      	movs	r3, #1
+ 8008ca2:	f887 3117 	strb.w	r3, [r7, #279]	; 0x117
+        break;
+ 8008ca6:	e006      	b.n	8008cb6 <HAL_RCCEx_PeriphCLKConfig+0xc7a>
+        break;
+ 8008ca8:	bf00      	nop
+ 8008caa:	e004      	b.n	8008cb6 <HAL_RCCEx_PeriphCLKConfig+0xc7a>
+        break;
+ 8008cac:	bf00      	nop
+ 8008cae:	e002      	b.n	8008cb6 <HAL_RCCEx_PeriphCLKConfig+0xc7a>
+        break;
+ 8008cb0:	bf00      	nop
+ 8008cb2:	e000      	b.n	8008cb6 <HAL_RCCEx_PeriphCLKConfig+0xc7a>
+        break;
+ 8008cb4:	bf00      	nop
+    }
+
+    if (ret == HAL_OK)
+ 8008cb6:	f897 3117 	ldrb.w	r3, [r7, #279]	; 0x117
+ 8008cba:	2b00      	cmp	r3, #0
+ 8008cbc:	d10e      	bne.n	8008cdc <HAL_RCCEx_PeriphCLKConfig+0xca0>
+    {
+      /* Set the source of LPTIM2 clock*/
+      __HAL_RCC_LPTIM2_CONFIG(PeriphClkInit->Lptim2ClockSelection);
+ 8008cbe:	4b06      	ldr	r3, [pc, #24]	; (8008cd8 <HAL_RCCEx_PeriphCLKConfig+0xc9c>)
+ 8008cc0:	6d9b      	ldr	r3, [r3, #88]	; 0x58
+ 8008cc2:	f423 51e0 	bic.w	r1, r3, #7168	; 0x1c00
+ 8008cc6:	f8d7 3104 	ldr.w	r3, [r7, #260]	; 0x104
+ 8008cca:	f8d3 3098 	ldr.w	r3, [r3, #152]	; 0x98
+ 8008cce:	4a02      	ldr	r2, [pc, #8]	; (8008cd8 <HAL_RCCEx_PeriphCLKConfig+0xc9c>)
+ 8008cd0:	430b      	orrs	r3, r1
+ 8008cd2:	6593      	str	r3, [r2, #88]	; 0x58
+ 8008cd4:	e006      	b.n	8008ce4 <HAL_RCCEx_PeriphCLKConfig+0xca8>
+ 8008cd6:	bf00      	nop
+ 8008cd8:	58024400 	.word	0x58024400
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+ 8008cdc:	f897 3117 	ldrb.w	r3, [r7, #279]	; 0x117
+ 8008ce0:	f887 3116 	strb.w	r3, [r7, #278]	; 0x116
+    }
+  }
+
+  /*---------------------------- LPTIM345 configuration -------------------------------*/
+  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM345) == RCC_PERIPHCLK_LPTIM345)
+ 8008ce4:	f8d7 3104 	ldr.w	r3, [r7, #260]	; 0x104
+ 8008ce8:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 8008cec:	f002 0380 	and.w	r3, r2, #128	; 0x80
+ 8008cf0:	f8c7 3090 	str.w	r3, [r7, #144]	; 0x90
+ 8008cf4:	2300      	movs	r3, #0
+ 8008cf6:	f8c7 3094 	str.w	r3, [r7, #148]	; 0x94
+ 8008cfa:	e9d7 1224 	ldrd	r1, r2, [r7, #144]	; 0x90
+ 8008cfe:	460b      	mov	r3, r1
+ 8008d00:	4313      	orrs	r3, r2
+ 8008d02:	d055      	beq.n	8008db0 <HAL_RCCEx_PeriphCLKConfig+0xd74>
+  {
+    switch (PeriphClkInit->Lptim345ClockSelection)
+ 8008d04:	f8d7 3104 	ldr.w	r3, [r7, #260]	; 0x104
+ 8008d08:	f8d3 309c 	ldr.w	r3, [r3, #156]	; 0x9c
+ 8008d0c:	f5b3 4f20 	cmp.w	r3, #40960	; 0xa000
+ 8008d10:	d033      	beq.n	8008d7a <HAL_RCCEx_PeriphCLKConfig+0xd3e>
+ 8008d12:	f5b3 4f20 	cmp.w	r3, #40960	; 0xa000
+ 8008d16:	d82c      	bhi.n	8008d72 <HAL_RCCEx_PeriphCLKConfig+0xd36>
+ 8008d18:	f5b3 4f00 	cmp.w	r3, #32768	; 0x8000
+ 8008d1c:	d02f      	beq.n	8008d7e <HAL_RCCEx_PeriphCLKConfig+0xd42>
+ 8008d1e:	f5b3 4f00 	cmp.w	r3, #32768	; 0x8000
+ 8008d22:	d826      	bhi.n	8008d72 <HAL_RCCEx_PeriphCLKConfig+0xd36>
+ 8008d24:	f5b3 4fc0 	cmp.w	r3, #24576	; 0x6000
+ 8008d28:	d02b      	beq.n	8008d82 <HAL_RCCEx_PeriphCLKConfig+0xd46>
+ 8008d2a:	f5b3 4fc0 	cmp.w	r3, #24576	; 0x6000
+ 8008d2e:	d820      	bhi.n	8008d72 <HAL_RCCEx_PeriphCLKConfig+0xd36>
+ 8008d30:	f5b3 4f80 	cmp.w	r3, #16384	; 0x4000
+ 8008d34:	d012      	beq.n	8008d5c <HAL_RCCEx_PeriphCLKConfig+0xd20>
+ 8008d36:	f5b3 4f80 	cmp.w	r3, #16384	; 0x4000
+ 8008d3a:	d81a      	bhi.n	8008d72 <HAL_RCCEx_PeriphCLKConfig+0xd36>
+ 8008d3c:	2b00      	cmp	r3, #0
+ 8008d3e:	d022      	beq.n	8008d86 <HAL_RCCEx_PeriphCLKConfig+0xd4a>
+ 8008d40:	f5b3 5f00 	cmp.w	r3, #8192	; 0x2000
+ 8008d44:	d115      	bne.n	8008d72 <HAL_RCCEx_PeriphCLKConfig+0xd36>
+      case RCC_LPTIM345CLKSOURCE_PCLK4:      /* SRD/D3 PCLK1 (PCLK4) as clock source for LPTIM3/4/5 */
+        /* LPTIM3/4/5 clock source configuration done later after clock selection check */
+        break;
+
+      case RCC_LPTIM345CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPTIM3/4/5 */
+        ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE);
+ 8008d46:	f8d7 3104 	ldr.w	r3, [r7, #260]	; 0x104
+ 8008d4a:	3308      	adds	r3, #8
+ 8008d4c:	2100      	movs	r1, #0
+ 8008d4e:	4618      	mov	r0, r3
+ 8008d50:	f001 fbf6 	bl	800a540 <RCCEx_PLL2_Config>
+ 8008d54:	4603      	mov	r3, r0
+ 8008d56:	f887 3117 	strb.w	r3, [r7, #279]	; 0x117
+
+        /* LPTIM3/4/5 clock source configuration done later after clock selection check */
+        break;
+ 8008d5a:	e015      	b.n	8008d88 <HAL_RCCEx_PeriphCLKConfig+0xd4c>
+
+      case RCC_LPTIM345CLKSOURCE_PLL3:  /* PLL3 is used as clock source for LPTIM3/4/5 */
+        ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE);
+ 8008d5c:	f8d7 3104 	ldr.w	r3, [r7, #260]	; 0x104
+ 8008d60:	3328      	adds	r3, #40	; 0x28
+ 8008d62:	2102      	movs	r1, #2
+ 8008d64:	4618      	mov	r0, r3
+ 8008d66:	f001 fc9d 	bl	800a6a4 <RCCEx_PLL3_Config>
+ 8008d6a:	4603      	mov	r3, r0
+ 8008d6c:	f887 3117 	strb.w	r3, [r7, #279]	; 0x117
+
+        /* LPTIM3/4/5 clock source configuration done later after clock selection check */
+        break;
+ 8008d70:	e00a      	b.n	8008d88 <HAL_RCCEx_PeriphCLKConfig+0xd4c>
+        /* HSI, HSE, or CSI oscillator is used as source of LPTIM3/4/5 clock */
+        /* LPTIM3/4/5 clock source configuration done later after clock selection check */
+        break;
+
+      default:
+        ret = HAL_ERROR;
+ 8008d72:	2301      	movs	r3, #1
+ 8008d74:	f887 3117 	strb.w	r3, [r7, #279]	; 0x117
+        break;
+ 8008d78:	e006      	b.n	8008d88 <HAL_RCCEx_PeriphCLKConfig+0xd4c>
+        break;
+ 8008d7a:	bf00      	nop
+ 8008d7c:	e004      	b.n	8008d88 <HAL_RCCEx_PeriphCLKConfig+0xd4c>
+        break;
+ 8008d7e:	bf00      	nop
+ 8008d80:	e002      	b.n	8008d88 <HAL_RCCEx_PeriphCLKConfig+0xd4c>
+        break;
+ 8008d82:	bf00      	nop
+ 8008d84:	e000      	b.n	8008d88 <HAL_RCCEx_PeriphCLKConfig+0xd4c>
+        break;
+ 8008d86:	bf00      	nop
+    }
+
+    if (ret == HAL_OK)
+ 8008d88:	f897 3117 	ldrb.w	r3, [r7, #279]	; 0x117
+ 8008d8c:	2b00      	cmp	r3, #0
+ 8008d8e:	d10b      	bne.n	8008da8 <HAL_RCCEx_PeriphCLKConfig+0xd6c>
+    {
+      /* Set the source of LPTIM3/4/5 clock */
+      __HAL_RCC_LPTIM345_CONFIG(PeriphClkInit->Lptim345ClockSelection);
+ 8008d90:	4ba0      	ldr	r3, [pc, #640]	; (8009014 <HAL_RCCEx_PeriphCLKConfig+0xfd8>)
+ 8008d92:	6d9b      	ldr	r3, [r3, #88]	; 0x58
+ 8008d94:	f423 4160 	bic.w	r1, r3, #57344	; 0xe000
+ 8008d98:	f8d7 3104 	ldr.w	r3, [r7, #260]	; 0x104
+ 8008d9c:	f8d3 309c 	ldr.w	r3, [r3, #156]	; 0x9c
+ 8008da0:	4a9c      	ldr	r2, [pc, #624]	; (8009014 <HAL_RCCEx_PeriphCLKConfig+0xfd8>)
+ 8008da2:	430b      	orrs	r3, r1
+ 8008da4:	6593      	str	r3, [r2, #88]	; 0x58
+ 8008da6:	e003      	b.n	8008db0 <HAL_RCCEx_PeriphCLKConfig+0xd74>
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+ 8008da8:	f897 3117 	ldrb.w	r3, [r7, #279]	; 0x117
+ 8008dac:	f887 3116 	strb.w	r3, [r7, #278]	; 0x116
+    }
+  }
+
+  /*------------------------------ I2C1/2/3/5* Configuration ------------------------*/
+#if defined(I2C5)
+  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1235) == RCC_PERIPHCLK_I2C1235)
+ 8008db0:	f8d7 3104 	ldr.w	r3, [r7, #260]	; 0x104
+ 8008db4:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 8008db8:	f002 0308 	and.w	r3, r2, #8
+ 8008dbc:	f8c7 3088 	str.w	r3, [r7, #136]	; 0x88
+ 8008dc0:	2300      	movs	r3, #0
+ 8008dc2:	f8c7 308c 	str.w	r3, [r7, #140]	; 0x8c
+ 8008dc6:	e9d7 1222 	ldrd	r1, r2, [r7, #136]	; 0x88
+ 8008dca:	460b      	mov	r3, r1
+ 8008dcc:	4313      	orrs	r3, r2
+ 8008dce:	d01e      	beq.n	8008e0e <HAL_RCCEx_PeriphCLKConfig+0xdd2>
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_I2C1235CLKSOURCE(PeriphClkInit->I2c1235ClockSelection));
+
+    if ((PeriphClkInit->I2c1235ClockSelection) == RCC_I2C1235CLKSOURCE_PLL3)
+ 8008dd0:	f8d7 3104 	ldr.w	r3, [r7, #260]	; 0x104
+ 8008dd4:	f8d3 3080 	ldr.w	r3, [r3, #128]	; 0x80
+ 8008dd8:	f5b3 5f80 	cmp.w	r3, #4096	; 0x1000
+ 8008ddc:	d10c      	bne.n	8008df8 <HAL_RCCEx_PeriphCLKConfig+0xdbc>
+    {
+      if (RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE) != HAL_OK)
+ 8008dde:	f8d7 3104 	ldr.w	r3, [r7, #260]	; 0x104
+ 8008de2:	3328      	adds	r3, #40	; 0x28
+ 8008de4:	2102      	movs	r1, #2
+ 8008de6:	4618      	mov	r0, r3
+ 8008de8:	f001 fc5c 	bl	800a6a4 <RCCEx_PLL3_Config>
+ 8008dec:	4603      	mov	r3, r0
+ 8008dee:	2b00      	cmp	r3, #0
+ 8008df0:	d002      	beq.n	8008df8 <HAL_RCCEx_PeriphCLKConfig+0xdbc>
+      {
+        status = HAL_ERROR;
+ 8008df2:	2301      	movs	r3, #1
+ 8008df4:	f887 3116 	strb.w	r3, [r7, #278]	; 0x116
+      }
+    }
+
+    __HAL_RCC_I2C1235_CONFIG(PeriphClkInit->I2c1235ClockSelection);
+ 8008df8:	4b86      	ldr	r3, [pc, #536]	; (8009014 <HAL_RCCEx_PeriphCLKConfig+0xfd8>)
+ 8008dfa:	6d5b      	ldr	r3, [r3, #84]	; 0x54
+ 8008dfc:	f423 5140 	bic.w	r1, r3, #12288	; 0x3000
+ 8008e00:	f8d7 3104 	ldr.w	r3, [r7, #260]	; 0x104
+ 8008e04:	f8d3 3080 	ldr.w	r3, [r3, #128]	; 0x80
+ 8008e08:	4a82      	ldr	r2, [pc, #520]	; (8009014 <HAL_RCCEx_PeriphCLKConfig+0xfd8>)
+ 8008e0a:	430b      	orrs	r3, r1
+ 8008e0c:	6553      	str	r3, [r2, #84]	; 0x54
+
+  }
+#endif /* I2C5 */
+
+  /*------------------------------ I2C4 Configuration ------------------------*/
+  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4)
+ 8008e0e:	f8d7 3104 	ldr.w	r3, [r7, #260]	; 0x104
+ 8008e12:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 8008e16:	f002 0310 	and.w	r3, r2, #16
+ 8008e1a:	f8c7 3080 	str.w	r3, [r7, #128]	; 0x80
+ 8008e1e:	2300      	movs	r3, #0
+ 8008e20:	f8c7 3084 	str.w	r3, [r7, #132]	; 0x84
+ 8008e24:	e9d7 1220 	ldrd	r1, r2, [r7, #128]	; 0x80
+ 8008e28:	460b      	mov	r3, r1
+ 8008e2a:	4313      	orrs	r3, r2
+ 8008e2c:	d01e      	beq.n	8008e6c <HAL_RCCEx_PeriphCLKConfig+0xe30>
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_I2C4CLKSOURCE(PeriphClkInit->I2c4ClockSelection));
+
+    if ((PeriphClkInit->I2c4ClockSelection) == RCC_I2C4CLKSOURCE_PLL3)
+ 8008e2e:	f8d7 3104 	ldr.w	r3, [r7, #260]	; 0x104
+ 8008e32:	f8d3 3094 	ldr.w	r3, [r3, #148]	; 0x94
+ 8008e36:	f5b3 7f80 	cmp.w	r3, #256	; 0x100
+ 8008e3a:	d10c      	bne.n	8008e56 <HAL_RCCEx_PeriphCLKConfig+0xe1a>
+    {
+      if (RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE) != HAL_OK)
+ 8008e3c:	f8d7 3104 	ldr.w	r3, [r7, #260]	; 0x104
+ 8008e40:	3328      	adds	r3, #40	; 0x28
+ 8008e42:	2102      	movs	r1, #2
+ 8008e44:	4618      	mov	r0, r3
+ 8008e46:	f001 fc2d 	bl	800a6a4 <RCCEx_PLL3_Config>
+ 8008e4a:	4603      	mov	r3, r0
+ 8008e4c:	2b00      	cmp	r3, #0
+ 8008e4e:	d002      	beq.n	8008e56 <HAL_RCCEx_PeriphCLKConfig+0xe1a>
+      {
+        status = HAL_ERROR;
+ 8008e50:	2301      	movs	r3, #1
+ 8008e52:	f887 3116 	strb.w	r3, [r7, #278]	; 0x116
+      }
+    }
+
+    __HAL_RCC_I2C4_CONFIG(PeriphClkInit->I2c4ClockSelection);
+ 8008e56:	4b6f      	ldr	r3, [pc, #444]	; (8009014 <HAL_RCCEx_PeriphCLKConfig+0xfd8>)
+ 8008e58:	6d9b      	ldr	r3, [r3, #88]	; 0x58
+ 8008e5a:	f423 7140 	bic.w	r1, r3, #768	; 0x300
+ 8008e5e:	f8d7 3104 	ldr.w	r3, [r7, #260]	; 0x104
+ 8008e62:	f8d3 3094 	ldr.w	r3, [r3, #148]	; 0x94
+ 8008e66:	4a6b      	ldr	r2, [pc, #428]	; (8009014 <HAL_RCCEx_PeriphCLKConfig+0xfd8>)
+ 8008e68:	430b      	orrs	r3, r1
+ 8008e6a:	6593      	str	r3, [r2, #88]	; 0x58
+
+  }
+
+  /*---------------------------- ADC configuration -------------------------------*/
+  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC)
+ 8008e6c:	f8d7 3104 	ldr.w	r3, [r7, #260]	; 0x104
+ 8008e70:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 8008e74:	f402 2300 	and.w	r3, r2, #524288	; 0x80000
+ 8008e78:	67bb      	str	r3, [r7, #120]	; 0x78
+ 8008e7a:	2300      	movs	r3, #0
+ 8008e7c:	67fb      	str	r3, [r7, #124]	; 0x7c
+ 8008e7e:	e9d7 121e 	ldrd	r1, r2, [r7, #120]	; 0x78
+ 8008e82:	460b      	mov	r3, r1
+ 8008e84:	4313      	orrs	r3, r2
+ 8008e86:	d03e      	beq.n	8008f06 <HAL_RCCEx_PeriphCLKConfig+0xeca>
+  {
+    switch (PeriphClkInit->AdcClockSelection)
+ 8008e88:	f8d7 3104 	ldr.w	r3, [r7, #260]	; 0x104
+ 8008e8c:	f8d3 30a0 	ldr.w	r3, [r3, #160]	; 0xa0
+ 8008e90:	f5b3 3f00 	cmp.w	r3, #131072	; 0x20000
+ 8008e94:	d022      	beq.n	8008edc <HAL_RCCEx_PeriphCLKConfig+0xea0>
+ 8008e96:	f5b3 3f00 	cmp.w	r3, #131072	; 0x20000
+ 8008e9a:	d81b      	bhi.n	8008ed4 <HAL_RCCEx_PeriphCLKConfig+0xe98>
+ 8008e9c:	2b00      	cmp	r3, #0
+ 8008e9e:	d003      	beq.n	8008ea8 <HAL_RCCEx_PeriphCLKConfig+0xe6c>
+ 8008ea0:	f5b3 3f80 	cmp.w	r3, #65536	; 0x10000
+ 8008ea4:	d00b      	beq.n	8008ebe <HAL_RCCEx_PeriphCLKConfig+0xe82>
+ 8008ea6:	e015      	b.n	8008ed4 <HAL_RCCEx_PeriphCLKConfig+0xe98>
+    {
+
+      case RCC_ADCCLKSOURCE_PLL2: /* PLL2 is used as clock source for ADC*/
+
+        ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE);
+ 8008ea8:	f8d7 3104 	ldr.w	r3, [r7, #260]	; 0x104
+ 8008eac:	3308      	adds	r3, #8
+ 8008eae:	2100      	movs	r1, #0
+ 8008eb0:	4618      	mov	r0, r3
+ 8008eb2:	f001 fb45 	bl	800a540 <RCCEx_PLL2_Config>
+ 8008eb6:	4603      	mov	r3, r0
+ 8008eb8:	f887 3117 	strb.w	r3, [r7, #279]	; 0x117
+
+        /* ADC clock source configuration done later after clock selection check */
+        break;
+ 8008ebc:	e00f      	b.n	8008ede <HAL_RCCEx_PeriphCLKConfig+0xea2>
+
+      case RCC_ADCCLKSOURCE_PLL3:  /* PLL3 is used as clock source for ADC*/
+        ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE);
+ 8008ebe:	f8d7 3104 	ldr.w	r3, [r7, #260]	; 0x104
+ 8008ec2:	3328      	adds	r3, #40	; 0x28
+ 8008ec4:	2102      	movs	r1, #2
+ 8008ec6:	4618      	mov	r0, r3
+ 8008ec8:	f001 fbec 	bl	800a6a4 <RCCEx_PLL3_Config>
+ 8008ecc:	4603      	mov	r3, r0
+ 8008ece:	f887 3117 	strb.w	r3, [r7, #279]	; 0x117
+
+        /* ADC clock source configuration done later after clock selection check */
+        break;
+ 8008ed2:	e004      	b.n	8008ede <HAL_RCCEx_PeriphCLKConfig+0xea2>
+        /* HSI, HSE, or CSI oscillator is used as source of ADC clock */
+        /* ADC clock source configuration done later after clock selection check */
+        break;
+
+      default:
+        ret = HAL_ERROR;
+ 8008ed4:	2301      	movs	r3, #1
+ 8008ed6:	f887 3117 	strb.w	r3, [r7, #279]	; 0x117
+        break;
+ 8008eda:	e000      	b.n	8008ede <HAL_RCCEx_PeriphCLKConfig+0xea2>
+        break;
+ 8008edc:	bf00      	nop
+    }
+
+    if (ret == HAL_OK)
+ 8008ede:	f897 3117 	ldrb.w	r3, [r7, #279]	; 0x117
+ 8008ee2:	2b00      	cmp	r3, #0
+ 8008ee4:	d10b      	bne.n	8008efe <HAL_RCCEx_PeriphCLKConfig+0xec2>
+    {
+      /* Set the source of ADC clock*/
+      __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection);
+ 8008ee6:	4b4b      	ldr	r3, [pc, #300]	; (8009014 <HAL_RCCEx_PeriphCLKConfig+0xfd8>)
+ 8008ee8:	6d9b      	ldr	r3, [r3, #88]	; 0x58
+ 8008eea:	f423 3140 	bic.w	r1, r3, #196608	; 0x30000
+ 8008eee:	f8d7 3104 	ldr.w	r3, [r7, #260]	; 0x104
+ 8008ef2:	f8d3 30a0 	ldr.w	r3, [r3, #160]	; 0xa0
+ 8008ef6:	4a47      	ldr	r2, [pc, #284]	; (8009014 <HAL_RCCEx_PeriphCLKConfig+0xfd8>)
+ 8008ef8:	430b      	orrs	r3, r1
+ 8008efa:	6593      	str	r3, [r2, #88]	; 0x58
+ 8008efc:	e003      	b.n	8008f06 <HAL_RCCEx_PeriphCLKConfig+0xeca>
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+ 8008efe:	f897 3117 	ldrb.w	r3, [r7, #279]	; 0x117
+ 8008f02:	f887 3116 	strb.w	r3, [r7, #278]	; 0x116
+    }
+  }
+
+  /*------------------------------ USB Configuration -------------------------*/
+  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB)
+ 8008f06:	f8d7 3104 	ldr.w	r3, [r7, #260]	; 0x104
+ 8008f0a:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 8008f0e:	f402 2380 	and.w	r3, r2, #262144	; 0x40000
+ 8008f12:	673b      	str	r3, [r7, #112]	; 0x70
+ 8008f14:	2300      	movs	r3, #0
+ 8008f16:	677b      	str	r3, [r7, #116]	; 0x74
+ 8008f18:	e9d7 121c 	ldrd	r1, r2, [r7, #112]	; 0x70
+ 8008f1c:	460b      	mov	r3, r1
+ 8008f1e:	4313      	orrs	r3, r2
+ 8008f20:	d03b      	beq.n	8008f9a <HAL_RCCEx_PeriphCLKConfig+0xf5e>
+  {
+
+    switch (PeriphClkInit->UsbClockSelection)
+ 8008f22:	f8d7 3104 	ldr.w	r3, [r7, #260]	; 0x104
+ 8008f26:	f8d3 3084 	ldr.w	r3, [r3, #132]	; 0x84
+ 8008f2a:	f5b3 1f40 	cmp.w	r3, #3145728	; 0x300000
+ 8008f2e:	d01f      	beq.n	8008f70 <HAL_RCCEx_PeriphCLKConfig+0xf34>
+ 8008f30:	f5b3 1f40 	cmp.w	r3, #3145728	; 0x300000
+ 8008f34:	d818      	bhi.n	8008f68 <HAL_RCCEx_PeriphCLKConfig+0xf2c>
+ 8008f36:	f5b3 1f80 	cmp.w	r3, #1048576	; 0x100000
+ 8008f3a:	d003      	beq.n	8008f44 <HAL_RCCEx_PeriphCLKConfig+0xf08>
+ 8008f3c:	f5b3 1f00 	cmp.w	r3, #2097152	; 0x200000
+ 8008f40:	d007      	beq.n	8008f52 <HAL_RCCEx_PeriphCLKConfig+0xf16>
+ 8008f42:	e011      	b.n	8008f68 <HAL_RCCEx_PeriphCLKConfig+0xf2c>
+    {
+      case RCC_USBCLKSOURCE_PLL:      /* PLL is used as clock source for USB*/
+        /* Enable USB Clock output generated form System USB . */
+        __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
+ 8008f44:	4b33      	ldr	r3, [pc, #204]	; (8009014 <HAL_RCCEx_PeriphCLKConfig+0xfd8>)
+ 8008f46:	6adb      	ldr	r3, [r3, #44]	; 0x2c
+ 8008f48:	4a32      	ldr	r2, [pc, #200]	; (8009014 <HAL_RCCEx_PeriphCLKConfig+0xfd8>)
+ 8008f4a:	f443 3300 	orr.w	r3, r3, #131072	; 0x20000
+ 8008f4e:	62d3      	str	r3, [r2, #44]	; 0x2c
+
+        /* USB clock source configuration done later after clock selection check */
+        break;
+ 8008f50:	e00f      	b.n	8008f72 <HAL_RCCEx_PeriphCLKConfig+0xf36>
+
+      case RCC_USBCLKSOURCE_PLL3: /* PLL3 is used as clock source for USB*/
+
+        ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE);
+ 8008f52:	f8d7 3104 	ldr.w	r3, [r7, #260]	; 0x104
+ 8008f56:	3328      	adds	r3, #40	; 0x28
+ 8008f58:	2101      	movs	r1, #1
+ 8008f5a:	4618      	mov	r0, r3
+ 8008f5c:	f001 fba2 	bl	800a6a4 <RCCEx_PLL3_Config>
+ 8008f60:	4603      	mov	r3, r0
+ 8008f62:	f887 3117 	strb.w	r3, [r7, #279]	; 0x117
+
+        /* USB clock source configuration done later after clock selection check */
+        break;
+ 8008f66:	e004      	b.n	8008f72 <HAL_RCCEx_PeriphCLKConfig+0xf36>
+        /* HSI48 oscillator is used as source of USB clock */
+        /* USB clock source configuration done later after clock selection check */
+        break;
+
+      default:
+        ret = HAL_ERROR;
+ 8008f68:	2301      	movs	r3, #1
+ 8008f6a:	f887 3117 	strb.w	r3, [r7, #279]	; 0x117
+        break;
+ 8008f6e:	e000      	b.n	8008f72 <HAL_RCCEx_PeriphCLKConfig+0xf36>
+        break;
+ 8008f70:	bf00      	nop
+    }
+
+    if (ret == HAL_OK)
+ 8008f72:	f897 3117 	ldrb.w	r3, [r7, #279]	; 0x117
+ 8008f76:	2b00      	cmp	r3, #0
+ 8008f78:	d10b      	bne.n	8008f92 <HAL_RCCEx_PeriphCLKConfig+0xf56>
+    {
+      /* Set the source of USB clock*/
+      __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection);
+ 8008f7a:	4b26      	ldr	r3, [pc, #152]	; (8009014 <HAL_RCCEx_PeriphCLKConfig+0xfd8>)
+ 8008f7c:	6d5b      	ldr	r3, [r3, #84]	; 0x54
+ 8008f7e:	f423 1140 	bic.w	r1, r3, #3145728	; 0x300000
+ 8008f82:	f8d7 3104 	ldr.w	r3, [r7, #260]	; 0x104
+ 8008f86:	f8d3 3084 	ldr.w	r3, [r3, #132]	; 0x84
+ 8008f8a:	4a22      	ldr	r2, [pc, #136]	; (8009014 <HAL_RCCEx_PeriphCLKConfig+0xfd8>)
+ 8008f8c:	430b      	orrs	r3, r1
+ 8008f8e:	6553      	str	r3, [r2, #84]	; 0x54
+ 8008f90:	e003      	b.n	8008f9a <HAL_RCCEx_PeriphCLKConfig+0xf5e>
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+ 8008f92:	f897 3117 	ldrb.w	r3, [r7, #279]	; 0x117
+ 8008f96:	f887 3116 	strb.w	r3, [r7, #278]	; 0x116
+    }
+
+  }
+
+  /*------------------------------------- SDMMC Configuration ------------------------------------*/
+  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC) == RCC_PERIPHCLK_SDMMC)
+ 8008f9a:	f8d7 3104 	ldr.w	r3, [r7, #260]	; 0x104
+ 8008f9e:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 8008fa2:	f402 3380 	and.w	r3, r2, #65536	; 0x10000
+ 8008fa6:	66bb      	str	r3, [r7, #104]	; 0x68
+ 8008fa8:	2300      	movs	r3, #0
+ 8008faa:	66fb      	str	r3, [r7, #108]	; 0x6c
+ 8008fac:	e9d7 121a 	ldrd	r1, r2, [r7, #104]	; 0x68
+ 8008fb0:	460b      	mov	r3, r1
+ 8008fb2:	4313      	orrs	r3, r2
+ 8008fb4:	d034      	beq.n	8009020 <HAL_RCCEx_PeriphCLKConfig+0xfe4>
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_SDMMC(PeriphClkInit->SdmmcClockSelection));
+
+    switch (PeriphClkInit->SdmmcClockSelection)
+ 8008fb6:	f8d7 3104 	ldr.w	r3, [r7, #260]	; 0x104
+ 8008fba:	6d1b      	ldr	r3, [r3, #80]	; 0x50
+ 8008fbc:	2b00      	cmp	r3, #0
+ 8008fbe:	d003      	beq.n	8008fc8 <HAL_RCCEx_PeriphCLKConfig+0xf8c>
+ 8008fc0:	f5b3 3f80 	cmp.w	r3, #65536	; 0x10000
+ 8008fc4:	d007      	beq.n	8008fd6 <HAL_RCCEx_PeriphCLKConfig+0xf9a>
+ 8008fc6:	e011      	b.n	8008fec <HAL_RCCEx_PeriphCLKConfig+0xfb0>
+    {
+      case RCC_SDMMCCLKSOURCE_PLL:      /* PLL is used as clock source for SDMMC*/
+        /* Enable SDMMC Clock output generated form System PLL . */
+        __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
+ 8008fc8:	4b12      	ldr	r3, [pc, #72]	; (8009014 <HAL_RCCEx_PeriphCLKConfig+0xfd8>)
+ 8008fca:	6adb      	ldr	r3, [r3, #44]	; 0x2c
+ 8008fcc:	4a11      	ldr	r2, [pc, #68]	; (8009014 <HAL_RCCEx_PeriphCLKConfig+0xfd8>)
+ 8008fce:	f443 3300 	orr.w	r3, r3, #131072	; 0x20000
+ 8008fd2:	62d3      	str	r3, [r2, #44]	; 0x2c
+
+        /* SDMMC clock source configuration done later after clock selection check */
+        break;
+ 8008fd4:	e00e      	b.n	8008ff4 <HAL_RCCEx_PeriphCLKConfig+0xfb8>
+
+      case RCC_SDMMCCLKSOURCE_PLL2: /* PLL2 is used as clock source for SDMMC*/
+
+        ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_R_UPDATE);
+ 8008fd6:	f8d7 3104 	ldr.w	r3, [r7, #260]	; 0x104
+ 8008fda:	3308      	adds	r3, #8
+ 8008fdc:	2102      	movs	r1, #2
+ 8008fde:	4618      	mov	r0, r3
+ 8008fe0:	f001 faae 	bl	800a540 <RCCEx_PLL2_Config>
+ 8008fe4:	4603      	mov	r3, r0
+ 8008fe6:	f887 3117 	strb.w	r3, [r7, #279]	; 0x117
+
+        /* SDMMC clock source configuration done later after clock selection check */
+        break;
+ 8008fea:	e003      	b.n	8008ff4 <HAL_RCCEx_PeriphCLKConfig+0xfb8>
+
+      default:
+        ret = HAL_ERROR;
+ 8008fec:	2301      	movs	r3, #1
+ 8008fee:	f887 3117 	strb.w	r3, [r7, #279]	; 0x117
+        break;
+ 8008ff2:	bf00      	nop
+    }
+
+    if (ret == HAL_OK)
+ 8008ff4:	f897 3117 	ldrb.w	r3, [r7, #279]	; 0x117
+ 8008ff8:	2b00      	cmp	r3, #0
+ 8008ffa:	d10d      	bne.n	8009018 <HAL_RCCEx_PeriphCLKConfig+0xfdc>
+    {
+      /* Set the source of SDMMC clock*/
+      __HAL_RCC_SDMMC_CONFIG(PeriphClkInit->SdmmcClockSelection);
+ 8008ffc:	4b05      	ldr	r3, [pc, #20]	; (8009014 <HAL_RCCEx_PeriphCLKConfig+0xfd8>)
+ 8008ffe:	6cdb      	ldr	r3, [r3, #76]	; 0x4c
+ 8009000:	f423 3180 	bic.w	r1, r3, #65536	; 0x10000
+ 8009004:	f8d7 3104 	ldr.w	r3, [r7, #260]	; 0x104
+ 8009008:	6d1b      	ldr	r3, [r3, #80]	; 0x50
+ 800900a:	4a02      	ldr	r2, [pc, #8]	; (8009014 <HAL_RCCEx_PeriphCLKConfig+0xfd8>)
+ 800900c:	430b      	orrs	r3, r1
+ 800900e:	64d3      	str	r3, [r2, #76]	; 0x4c
+ 8009010:	e006      	b.n	8009020 <HAL_RCCEx_PeriphCLKConfig+0xfe4>
+ 8009012:	bf00      	nop
+ 8009014:	58024400 	.word	0x58024400
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+ 8009018:	f897 3117 	ldrb.w	r3, [r7, #279]	; 0x117
+ 800901c:	f887 3116 	strb.w	r3, [r7, #278]	; 0x116
+    }
+  }
+
+#if defined(LTDC)
+  /*-------------------------------------- LTDC Configuration -----------------------------------*/
+  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC)
+ 8009020:	f8d7 3104 	ldr.w	r3, [r7, #260]	; 0x104
+ 8009024:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 8009028:	f002 5300 	and.w	r3, r2, #536870912	; 0x20000000
+ 800902c:	663b      	str	r3, [r7, #96]	; 0x60
+ 800902e:	2300      	movs	r3, #0
+ 8009030:	667b      	str	r3, [r7, #100]	; 0x64
+ 8009032:	e9d7 1218 	ldrd	r1, r2, [r7, #96]	; 0x60
+ 8009036:	460b      	mov	r3, r1
+ 8009038:	4313      	orrs	r3, r2
+ 800903a:	d00c      	beq.n	8009056 <HAL_RCCEx_PeriphCLKConfig+0x101a>
+  {
+    if (RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE) != HAL_OK)
+ 800903c:	f8d7 3104 	ldr.w	r3, [r7, #260]	; 0x104
+ 8009040:	3328      	adds	r3, #40	; 0x28
+ 8009042:	2102      	movs	r1, #2
+ 8009044:	4618      	mov	r0, r3
+ 8009046:	f001 fb2d 	bl	800a6a4 <RCCEx_PLL3_Config>
+ 800904a:	4603      	mov	r3, r0
+ 800904c:	2b00      	cmp	r3, #0
+ 800904e:	d002      	beq.n	8009056 <HAL_RCCEx_PeriphCLKConfig+0x101a>
+    {
+      status = HAL_ERROR;
+ 8009050:	2301      	movs	r3, #1
+ 8009052:	f887 3116 	strb.w	r3, [r7, #278]	; 0x116
+    }
+  }
+#endif /* LTDC */
+
+  /*------------------------------ RNG Configuration -------------------------*/
+  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG)
+ 8009056:	f8d7 3104 	ldr.w	r3, [r7, #260]	; 0x104
+ 800905a:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 800905e:	f402 3300 	and.w	r3, r2, #131072	; 0x20000
+ 8009062:	65bb      	str	r3, [r7, #88]	; 0x58
+ 8009064:	2300      	movs	r3, #0
+ 8009066:	65fb      	str	r3, [r7, #92]	; 0x5c
+ 8009068:	e9d7 1216 	ldrd	r1, r2, [r7, #88]	; 0x58
+ 800906c:	460b      	mov	r3, r1
+ 800906e:	4313      	orrs	r3, r2
+ 8009070:	d036      	beq.n	80090e0 <HAL_RCCEx_PeriphCLKConfig+0x10a4>
+  {
+
+    switch (PeriphClkInit->RngClockSelection)
+ 8009072:	f8d7 3104 	ldr.w	r3, [r7, #260]	; 0x104
+ 8009076:	6fdb      	ldr	r3, [r3, #124]	; 0x7c
+ 8009078:	f5b3 7f40 	cmp.w	r3, #768	; 0x300
+ 800907c:	d018      	beq.n	80090b0 <HAL_RCCEx_PeriphCLKConfig+0x1074>
+ 800907e:	f5b3 7f40 	cmp.w	r3, #768	; 0x300
+ 8009082:	d811      	bhi.n	80090a8 <HAL_RCCEx_PeriphCLKConfig+0x106c>
+ 8009084:	f5b3 7f00 	cmp.w	r3, #512	; 0x200
+ 8009088:	d014      	beq.n	80090b4 <HAL_RCCEx_PeriphCLKConfig+0x1078>
+ 800908a:	f5b3 7f00 	cmp.w	r3, #512	; 0x200
+ 800908e:	d80b      	bhi.n	80090a8 <HAL_RCCEx_PeriphCLKConfig+0x106c>
+ 8009090:	2b00      	cmp	r3, #0
+ 8009092:	d011      	beq.n	80090b8 <HAL_RCCEx_PeriphCLKConfig+0x107c>
+ 8009094:	f5b3 7f80 	cmp.w	r3, #256	; 0x100
+ 8009098:	d106      	bne.n	80090a8 <HAL_RCCEx_PeriphCLKConfig+0x106c>
+    {
+      case RCC_RNGCLKSOURCE_PLL:     /* PLL is used as clock source for RNG*/
+        /* Enable RNG Clock output generated form System RNG . */
+        __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
+ 800909a:	4bb7      	ldr	r3, [pc, #732]	; (8009378 <HAL_RCCEx_PeriphCLKConfig+0x133c>)
+ 800909c:	6adb      	ldr	r3, [r3, #44]	; 0x2c
+ 800909e:	4ab6      	ldr	r2, [pc, #728]	; (8009378 <HAL_RCCEx_PeriphCLKConfig+0x133c>)
+ 80090a0:	f443 3300 	orr.w	r3, r3, #131072	; 0x20000
+ 80090a4:	62d3      	str	r3, [r2, #44]	; 0x2c
+
+        /* RNG clock source configuration done later after clock selection check */
+        break;
+ 80090a6:	e008      	b.n	80090ba <HAL_RCCEx_PeriphCLKConfig+0x107e>
+        /* HSI48 oscillator is used as source of RNG clock */
+        /* RNG clock source configuration done later after clock selection check */
+        break;
+
+      default:
+        ret = HAL_ERROR;
+ 80090a8:	2301      	movs	r3, #1
+ 80090aa:	f887 3117 	strb.w	r3, [r7, #279]	; 0x117
+        break;
+ 80090ae:	e004      	b.n	80090ba <HAL_RCCEx_PeriphCLKConfig+0x107e>
+        break;
+ 80090b0:	bf00      	nop
+ 80090b2:	e002      	b.n	80090ba <HAL_RCCEx_PeriphCLKConfig+0x107e>
+        break;
+ 80090b4:	bf00      	nop
+ 80090b6:	e000      	b.n	80090ba <HAL_RCCEx_PeriphCLKConfig+0x107e>
+        break;
+ 80090b8:	bf00      	nop
+    }
+
+    if (ret == HAL_OK)
+ 80090ba:	f897 3117 	ldrb.w	r3, [r7, #279]	; 0x117
+ 80090be:	2b00      	cmp	r3, #0
+ 80090c0:	d10a      	bne.n	80090d8 <HAL_RCCEx_PeriphCLKConfig+0x109c>
+    {
+      /* Set the source of RNG clock*/
+      __HAL_RCC_RNG_CONFIG(PeriphClkInit->RngClockSelection);
+ 80090c2:	4bad      	ldr	r3, [pc, #692]	; (8009378 <HAL_RCCEx_PeriphCLKConfig+0x133c>)
+ 80090c4:	6d5b      	ldr	r3, [r3, #84]	; 0x54
+ 80090c6:	f423 7140 	bic.w	r1, r3, #768	; 0x300
+ 80090ca:	f8d7 3104 	ldr.w	r3, [r7, #260]	; 0x104
+ 80090ce:	6fdb      	ldr	r3, [r3, #124]	; 0x7c
+ 80090d0:	4aa9      	ldr	r2, [pc, #676]	; (8009378 <HAL_RCCEx_PeriphCLKConfig+0x133c>)
+ 80090d2:	430b      	orrs	r3, r1
+ 80090d4:	6553      	str	r3, [r2, #84]	; 0x54
+ 80090d6:	e003      	b.n	80090e0 <HAL_RCCEx_PeriphCLKConfig+0x10a4>
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+ 80090d8:	f897 3117 	ldrb.w	r3, [r7, #279]	; 0x117
+ 80090dc:	f887 3116 	strb.w	r3, [r7, #278]	; 0x116
+    }
+
+  }
+
+  /*------------------------------ SWPMI1 Configuration ------------------------*/
+  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1)
+ 80090e0:	f8d7 3104 	ldr.w	r3, [r7, #260]	; 0x104
+ 80090e4:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 80090e8:	f402 1380 	and.w	r3, r2, #1048576	; 0x100000
+ 80090ec:	653b      	str	r3, [r7, #80]	; 0x50
+ 80090ee:	2300      	movs	r3, #0
+ 80090f0:	657b      	str	r3, [r7, #84]	; 0x54
+ 80090f2:	e9d7 1214 	ldrd	r1, r2, [r7, #80]	; 0x50
+ 80090f6:	460b      	mov	r3, r1
+ 80090f8:	4313      	orrs	r3, r2
+ 80090fa:	d009      	beq.n	8009110 <HAL_RCCEx_PeriphCLKConfig+0x10d4>
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_SWPMI1CLKSOURCE(PeriphClkInit->Swpmi1ClockSelection));
+
+    /* Configure the SWPMI1 interface clock source */
+    __HAL_RCC_SWPMI1_CONFIG(PeriphClkInit->Swpmi1ClockSelection);
+ 80090fc:	4b9e      	ldr	r3, [pc, #632]	; (8009378 <HAL_RCCEx_PeriphCLKConfig+0x133c>)
+ 80090fe:	6d1b      	ldr	r3, [r3, #80]	; 0x50
+ 8009100:	f023 4100 	bic.w	r1, r3, #2147483648	; 0x80000000
+ 8009104:	f8d7 3104 	ldr.w	r3, [r7, #260]	; 0x104
+ 8009108:	6f1b      	ldr	r3, [r3, #112]	; 0x70
+ 800910a:	4a9b      	ldr	r2, [pc, #620]	; (8009378 <HAL_RCCEx_PeriphCLKConfig+0x133c>)
+ 800910c:	430b      	orrs	r3, r1
+ 800910e:	6513      	str	r3, [r2, #80]	; 0x50
+    /* Configure the HRTIM1 clock source */
+    __HAL_RCC_HRTIM1_CONFIG(PeriphClkInit->Hrtim1ClockSelection);
+  }
+#endif  /*HRTIM1*/
+  /*------------------------------ DFSDM1 Configuration ------------------------*/
+  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1)
+ 8009110:	f8d7 3104 	ldr.w	r3, [r7, #260]	; 0x104
+ 8009114:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 8009118:	f402 1300 	and.w	r3, r2, #2097152	; 0x200000
+ 800911c:	64bb      	str	r3, [r7, #72]	; 0x48
+ 800911e:	2300      	movs	r3, #0
+ 8009120:	64fb      	str	r3, [r7, #76]	; 0x4c
+ 8009122:	e9d7 1212 	ldrd	r1, r2, [r7, #72]	; 0x48
+ 8009126:	460b      	mov	r3, r1
+ 8009128:	4313      	orrs	r3, r2
+ 800912a:	d009      	beq.n	8009140 <HAL_RCCEx_PeriphCLKConfig+0x1104>
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_DFSDM1CLKSOURCE(PeriphClkInit->Dfsdm1ClockSelection));
+
+    /* Configure the DFSDM1 interface clock source */
+    __HAL_RCC_DFSDM1_CONFIG(PeriphClkInit->Dfsdm1ClockSelection);
+ 800912c:	4b92      	ldr	r3, [pc, #584]	; (8009378 <HAL_RCCEx_PeriphCLKConfig+0x133c>)
+ 800912e:	6d1b      	ldr	r3, [r3, #80]	; 0x50
+ 8009130:	f023 7180 	bic.w	r1, r3, #16777216	; 0x1000000
+ 8009134:	f8d7 3104 	ldr.w	r3, [r7, #260]	; 0x104
+ 8009138:	6e9b      	ldr	r3, [r3, #104]	; 0x68
+ 800913a:	4a8f      	ldr	r2, [pc, #572]	; (8009378 <HAL_RCCEx_PeriphCLKConfig+0x133c>)
+ 800913c:	430b      	orrs	r3, r1
+ 800913e:	6513      	str	r3, [r2, #80]	; 0x50
+    __HAL_RCC_DFSDM2_CONFIG(PeriphClkInit->Dfsdm2ClockSelection);
+  }
+#endif  /* DFSDM2 */
+
+  /*------------------------------------ TIM configuration --------------------------------------*/
+  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM)
+ 8009140:	f8d7 3104 	ldr.w	r3, [r7, #260]	; 0x104
+ 8009144:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 8009148:	f002 4380 	and.w	r3, r2, #1073741824	; 0x40000000
+ 800914c:	643b      	str	r3, [r7, #64]	; 0x40
+ 800914e:	2300      	movs	r3, #0
+ 8009150:	647b      	str	r3, [r7, #68]	; 0x44
+ 8009152:	e9d7 1210 	ldrd	r1, r2, [r7, #64]	; 0x40
+ 8009156:	460b      	mov	r3, r1
+ 8009158:	4313      	orrs	r3, r2
+ 800915a:	d00e      	beq.n	800917a <HAL_RCCEx_PeriphCLKConfig+0x113e>
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_TIMPRES(PeriphClkInit->TIMPresSelection));
+
+    /* Configure Timer Prescaler */
+    __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
+ 800915c:	4b86      	ldr	r3, [pc, #536]	; (8009378 <HAL_RCCEx_PeriphCLKConfig+0x133c>)
+ 800915e:	691b      	ldr	r3, [r3, #16]
+ 8009160:	4a85      	ldr	r2, [pc, #532]	; (8009378 <HAL_RCCEx_PeriphCLKConfig+0x133c>)
+ 8009162:	f423 4300 	bic.w	r3, r3, #32768	; 0x8000
+ 8009166:	6113      	str	r3, [r2, #16]
+ 8009168:	4b83      	ldr	r3, [pc, #524]	; (8009378 <HAL_RCCEx_PeriphCLKConfig+0x133c>)
+ 800916a:	6919      	ldr	r1, [r3, #16]
+ 800916c:	f8d7 3104 	ldr.w	r3, [r7, #260]	; 0x104
+ 8009170:	f8d3 30b4 	ldr.w	r3, [r3, #180]	; 0xb4
+ 8009174:	4a80      	ldr	r2, [pc, #512]	; (8009378 <HAL_RCCEx_PeriphCLKConfig+0x133c>)
+ 8009176:	430b      	orrs	r3, r1
+ 8009178:	6113      	str	r3, [r2, #16]
+  }
+
+  /*------------------------------------ CKPER configuration --------------------------------------*/
+  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CKPER) == RCC_PERIPHCLK_CKPER)
+ 800917a:	f8d7 3104 	ldr.w	r3, [r7, #260]	; 0x104
+ 800917e:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 8009182:	f002 4300 	and.w	r3, r2, #2147483648	; 0x80000000
+ 8009186:	63bb      	str	r3, [r7, #56]	; 0x38
+ 8009188:	2300      	movs	r3, #0
+ 800918a:	63fb      	str	r3, [r7, #60]	; 0x3c
+ 800918c:	e9d7 120e 	ldrd	r1, r2, [r7, #56]	; 0x38
+ 8009190:	460b      	mov	r3, r1
+ 8009192:	4313      	orrs	r3, r2
+ 8009194:	d009      	beq.n	80091aa <HAL_RCCEx_PeriphCLKConfig+0x116e>
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_CLKPSOURCE(PeriphClkInit->CkperClockSelection));
+
+    /* Configure the CKPER clock source */
+    __HAL_RCC_CLKP_CONFIG(PeriphClkInit->CkperClockSelection);
+ 8009196:	4b78      	ldr	r3, [pc, #480]	; (8009378 <HAL_RCCEx_PeriphCLKConfig+0x133c>)
+ 8009198:	6cdb      	ldr	r3, [r3, #76]	; 0x4c
+ 800919a:	f023 5140 	bic.w	r1, r3, #805306368	; 0x30000000
+ 800919e:	f8d7 3104 	ldr.w	r3, [r7, #260]	; 0x104
+ 80091a2:	6d5b      	ldr	r3, [r3, #84]	; 0x54
+ 80091a4:	4a74      	ldr	r2, [pc, #464]	; (8009378 <HAL_RCCEx_PeriphCLKConfig+0x133c>)
+ 80091a6:	430b      	orrs	r3, r1
+ 80091a8:	64d3      	str	r3, [r2, #76]	; 0x4c
+  }
+
+  /*------------------------------ CEC Configuration ------------------------*/
+  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC)
+ 80091aa:	f8d7 3104 	ldr.w	r3, [r7, #260]	; 0x104
+ 80091ae:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 80091b2:	f402 0300 	and.w	r3, r2, #8388608	; 0x800000
+ 80091b6:	633b      	str	r3, [r7, #48]	; 0x30
+ 80091b8:	2300      	movs	r3, #0
+ 80091ba:	637b      	str	r3, [r7, #52]	; 0x34
+ 80091bc:	e9d7 120c 	ldrd	r1, r2, [r7, #48]	; 0x30
+ 80091c0:	460b      	mov	r3, r1
+ 80091c2:	4313      	orrs	r3, r2
+ 80091c4:	d00a      	beq.n	80091dc <HAL_RCCEx_PeriphCLKConfig+0x11a0>
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection));
+
+    /* Configure the CEC interface clock source */
+    __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection);
+ 80091c6:	4b6c      	ldr	r3, [pc, #432]	; (8009378 <HAL_RCCEx_PeriphCLKConfig+0x133c>)
+ 80091c8:	6d5b      	ldr	r3, [r3, #84]	; 0x54
+ 80091ca:	f423 0140 	bic.w	r1, r3, #12582912	; 0xc00000
+ 80091ce:	f8d7 3104 	ldr.w	r3, [r7, #260]	; 0x104
+ 80091d2:	f8d3 3088 	ldr.w	r3, [r3, #136]	; 0x88
+ 80091d6:	4a68      	ldr	r2, [pc, #416]	; (8009378 <HAL_RCCEx_PeriphCLKConfig+0x133c>)
+ 80091d8:	430b      	orrs	r3, r1
+ 80091da:	6553      	str	r3, [r2, #84]	; 0x54
+  }
+
+  /*---------------------------- PLL2 configuration -------------------------------*/
+  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL2_DIVP) == RCC_PERIPHCLK_PLL2_DIVP)
+ 80091dc:	f8d7 3104 	ldr.w	r3, [r7, #260]	; 0x104
+ 80091e0:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 80091e4:	2100      	movs	r1, #0
+ 80091e6:	62b9      	str	r1, [r7, #40]	; 0x28
+ 80091e8:	f003 0301 	and.w	r3, r3, #1
+ 80091ec:	62fb      	str	r3, [r7, #44]	; 0x2c
+ 80091ee:	e9d7 120a 	ldrd	r1, r2, [r7, #40]	; 0x28
+ 80091f2:	460b      	mov	r3, r1
+ 80091f4:	4313      	orrs	r3, r2
+ 80091f6:	d011      	beq.n	800921c <HAL_RCCEx_PeriphCLKConfig+0x11e0>
+  {
+    ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE);
+ 80091f8:	f8d7 3104 	ldr.w	r3, [r7, #260]	; 0x104
+ 80091fc:	3308      	adds	r3, #8
+ 80091fe:	2100      	movs	r1, #0
+ 8009200:	4618      	mov	r0, r3
+ 8009202:	f001 f99d 	bl	800a540 <RCCEx_PLL2_Config>
+ 8009206:	4603      	mov	r3, r0
+ 8009208:	f887 3117 	strb.w	r3, [r7, #279]	; 0x117
+    
+    if (ret == HAL_OK)
+ 800920c:	f897 3117 	ldrb.w	r3, [r7, #279]	; 0x117
+ 8009210:	2b00      	cmp	r3, #0
+ 8009212:	d003      	beq.n	800921c <HAL_RCCEx_PeriphCLKConfig+0x11e0>
+      /*Nothing to do*/
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+ 8009214:	f897 3117 	ldrb.w	r3, [r7, #279]	; 0x117
+ 8009218:	f887 3116 	strb.w	r3, [r7, #278]	; 0x116
+    } 
+  }
+  
+  
+  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL2_DIVQ) == RCC_PERIPHCLK_PLL2_DIVQ)
+ 800921c:	f8d7 3104 	ldr.w	r3, [r7, #260]	; 0x104
+ 8009220:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 8009224:	2100      	movs	r1, #0
+ 8009226:	6239      	str	r1, [r7, #32]
+ 8009228:	f003 0302 	and.w	r3, r3, #2
+ 800922c:	627b      	str	r3, [r7, #36]	; 0x24
+ 800922e:	e9d7 1208 	ldrd	r1, r2, [r7, #32]
+ 8009232:	460b      	mov	r3, r1
+ 8009234:	4313      	orrs	r3, r2
+ 8009236:	d011      	beq.n	800925c <HAL_RCCEx_PeriphCLKConfig+0x1220>
+  {
+    ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE);
+ 8009238:	f8d7 3104 	ldr.w	r3, [r7, #260]	; 0x104
+ 800923c:	3308      	adds	r3, #8
+ 800923e:	2101      	movs	r1, #1
+ 8009240:	4618      	mov	r0, r3
+ 8009242:	f001 f97d 	bl	800a540 <RCCEx_PLL2_Config>
+ 8009246:	4603      	mov	r3, r0
+ 8009248:	f887 3117 	strb.w	r3, [r7, #279]	; 0x117
+    
+    if (ret == HAL_OK)
+ 800924c:	f897 3117 	ldrb.w	r3, [r7, #279]	; 0x117
+ 8009250:	2b00      	cmp	r3, #0
+ 8009252:	d003      	beq.n	800925c <HAL_RCCEx_PeriphCLKConfig+0x1220>
+      /*Nothing to do*/
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+ 8009254:	f897 3117 	ldrb.w	r3, [r7, #279]	; 0x117
+ 8009258:	f887 3116 	strb.w	r3, [r7, #278]	; 0x116
+    }
+  }
+  
+  
+  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL2_DIVR) == RCC_PERIPHCLK_PLL2_DIVR)
+ 800925c:	f8d7 3104 	ldr.w	r3, [r7, #260]	; 0x104
+ 8009260:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 8009264:	2100      	movs	r1, #0
+ 8009266:	61b9      	str	r1, [r7, #24]
+ 8009268:	f003 0304 	and.w	r3, r3, #4
+ 800926c:	61fb      	str	r3, [r7, #28]
+ 800926e:	e9d7 1206 	ldrd	r1, r2, [r7, #24]
+ 8009272:	460b      	mov	r3, r1
+ 8009274:	4313      	orrs	r3, r2
+ 8009276:	d011      	beq.n	800929c <HAL_RCCEx_PeriphCLKConfig+0x1260>
+  {
+    ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_R_UPDATE);
+ 8009278:	f8d7 3104 	ldr.w	r3, [r7, #260]	; 0x104
+ 800927c:	3308      	adds	r3, #8
+ 800927e:	2102      	movs	r1, #2
+ 8009280:	4618      	mov	r0, r3
+ 8009282:	f001 f95d 	bl	800a540 <RCCEx_PLL2_Config>
+ 8009286:	4603      	mov	r3, r0
+ 8009288:	f887 3117 	strb.w	r3, [r7, #279]	; 0x117
+    
+    if (ret == HAL_OK)
+ 800928c:	f897 3117 	ldrb.w	r3, [r7, #279]	; 0x117
+ 8009290:	2b00      	cmp	r3, #0
+ 8009292:	d003      	beq.n	800929c <HAL_RCCEx_PeriphCLKConfig+0x1260>
+      /*Nothing to do*/
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+ 8009294:	f897 3117 	ldrb.w	r3, [r7, #279]	; 0x117
+ 8009298:	f887 3116 	strb.w	r3, [r7, #278]	; 0x116
+    }
+  }
+  
+
+  /*---------------------------- PLL3 configuration -------------------------------*/
+  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL3_DIVP) == RCC_PERIPHCLK_PLL3_DIVP)
+ 800929c:	f8d7 3104 	ldr.w	r3, [r7, #260]	; 0x104
+ 80092a0:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 80092a4:	2100      	movs	r1, #0
+ 80092a6:	6139      	str	r1, [r7, #16]
+ 80092a8:	f003 0308 	and.w	r3, r3, #8
+ 80092ac:	617b      	str	r3, [r7, #20]
+ 80092ae:	e9d7 1204 	ldrd	r1, r2, [r7, #16]
+ 80092b2:	460b      	mov	r3, r1
+ 80092b4:	4313      	orrs	r3, r2
+ 80092b6:	d011      	beq.n	80092dc <HAL_RCCEx_PeriphCLKConfig+0x12a0>
+  {
+    ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE);
+ 80092b8:	f8d7 3104 	ldr.w	r3, [r7, #260]	; 0x104
+ 80092bc:	3328      	adds	r3, #40	; 0x28
+ 80092be:	2100      	movs	r1, #0
+ 80092c0:	4618      	mov	r0, r3
+ 80092c2:	f001 f9ef 	bl	800a6a4 <RCCEx_PLL3_Config>
+ 80092c6:	4603      	mov	r3, r0
+ 80092c8:	f887 3117 	strb.w	r3, [r7, #279]	; 0x117
+  
+    if (ret == HAL_OK)
+ 80092cc:	f897 3117 	ldrb.w	r3, [r7, #279]	; 0x117
+ 80092d0:	2b00      	cmp	r3, #0
+ 80092d2:	d003      	beq.n	80092dc <HAL_RCCEx_PeriphCLKConfig+0x12a0>
+      /*Nothing to do*/
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+ 80092d4:	f897 3117 	ldrb.w	r3, [r7, #279]	; 0x117
+ 80092d8:	f887 3116 	strb.w	r3, [r7, #278]	; 0x116
+    }
+  }
+  
+  
+  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL3_DIVQ) == RCC_PERIPHCLK_PLL3_DIVQ)
+ 80092dc:	f8d7 3104 	ldr.w	r3, [r7, #260]	; 0x104
+ 80092e0:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 80092e4:	2100      	movs	r1, #0
+ 80092e6:	60b9      	str	r1, [r7, #8]
+ 80092e8:	f003 0310 	and.w	r3, r3, #16
+ 80092ec:	60fb      	str	r3, [r7, #12]
+ 80092ee:	e9d7 1202 	ldrd	r1, r2, [r7, #8]
+ 80092f2:	460b      	mov	r3, r1
+ 80092f4:	4313      	orrs	r3, r2
+ 80092f6:	d011      	beq.n	800931c <HAL_RCCEx_PeriphCLKConfig+0x12e0>
+  {
+    ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE);
+ 80092f8:	f8d7 3104 	ldr.w	r3, [r7, #260]	; 0x104
+ 80092fc:	3328      	adds	r3, #40	; 0x28
+ 80092fe:	2101      	movs	r1, #1
+ 8009300:	4618      	mov	r0, r3
+ 8009302:	f001 f9cf 	bl	800a6a4 <RCCEx_PLL3_Config>
+ 8009306:	4603      	mov	r3, r0
+ 8009308:	f887 3117 	strb.w	r3, [r7, #279]	; 0x117
+    
+    if (ret == HAL_OK)
+ 800930c:	f897 3117 	ldrb.w	r3, [r7, #279]	; 0x117
+ 8009310:	2b00      	cmp	r3, #0
+ 8009312:	d003      	beq.n	800931c <HAL_RCCEx_PeriphCLKConfig+0x12e0>
+      /*Nothing to do*/
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+ 8009314:	f897 3117 	ldrb.w	r3, [r7, #279]	; 0x117
+ 8009318:	f887 3116 	strb.w	r3, [r7, #278]	; 0x116
+    }
+  }
+  
+  
+  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL3_DIVR) == RCC_PERIPHCLK_PLL3_DIVR)
+ 800931c:	f8d7 3104 	ldr.w	r3, [r7, #260]	; 0x104
+ 8009320:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 8009324:	2100      	movs	r1, #0
+ 8009326:	6039      	str	r1, [r7, #0]
+ 8009328:	f003 0320 	and.w	r3, r3, #32
+ 800932c:	607b      	str	r3, [r7, #4]
+ 800932e:	e9d7 1200 	ldrd	r1, r2, [r7]
+ 8009332:	460b      	mov	r3, r1
+ 8009334:	4313      	orrs	r3, r2
+ 8009336:	d011      	beq.n	800935c <HAL_RCCEx_PeriphCLKConfig+0x1320>
+  {
+    ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE);
+ 8009338:	f8d7 3104 	ldr.w	r3, [r7, #260]	; 0x104
+ 800933c:	3328      	adds	r3, #40	; 0x28
+ 800933e:	2102      	movs	r1, #2
+ 8009340:	4618      	mov	r0, r3
+ 8009342:	f001 f9af 	bl	800a6a4 <RCCEx_PLL3_Config>
+ 8009346:	4603      	mov	r3, r0
+ 8009348:	f887 3117 	strb.w	r3, [r7, #279]	; 0x117
+    
+    if (ret == HAL_OK)
+ 800934c:	f897 3117 	ldrb.w	r3, [r7, #279]	; 0x117
+ 8009350:	2b00      	cmp	r3, #0
+ 8009352:	d003      	beq.n	800935c <HAL_RCCEx_PeriphCLKConfig+0x1320>
+      /*Nothing to do*/
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+ 8009354:	f897 3117 	ldrb.w	r3, [r7, #279]	; 0x117
+ 8009358:	f887 3116 	strb.w	r3, [r7, #278]	; 0x116
+    } 
+  }
+
+  if (status == HAL_OK)
+ 800935c:	f897 3116 	ldrb.w	r3, [r7, #278]	; 0x116
+ 8009360:	2b00      	cmp	r3, #0
+ 8009362:	d101      	bne.n	8009368 <HAL_RCCEx_PeriphCLKConfig+0x132c>
+  {
+    return HAL_OK;
+ 8009364:	2300      	movs	r3, #0
+ 8009366:	e000      	b.n	800936a <HAL_RCCEx_PeriphCLKConfig+0x132e>
+  }
+  return HAL_ERROR;
+ 8009368:	2301      	movs	r3, #1
+}
+ 800936a:	4618      	mov	r0, r3
+ 800936c:	f507 778c 	add.w	r7, r7, #280	; 0x118
+ 8009370:	46bd      	mov	sp, r7
+ 8009372:	e8bd 8fb0 	ldmia.w	sp!, {r4, r5, r7, r8, r9, sl, fp, pc}
+ 8009376:	bf00      	nop
+ 8009378:	58024400 	.word	0x58024400
+
+0800937c <HAL_RCCEx_GetPeriphCLKFreq>:
+  * @retval Frequency in KHz
+  *
+  *  (*) : Available on some STM32H7 lines only.
+  */
+uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint64_t PeriphClk)
+{
+ 800937c:	b580      	push	{r7, lr}
+ 800937e:	b090      	sub	sp, #64	; 0x40
+ 8009380:	af00      	add	r7, sp, #0
+ 8009382:	e9c7 0100 	strd	r0, r1, [r7]
+  /* This variable is used to store the SAI and CKP clock source */
+  uint32_t saiclocksource;
+  uint32_t ckpclocksource;
+  uint32_t srcclk;
+
+  if (PeriphClk == RCC_PERIPHCLK_SAI1)
+ 8009386:	e9d7 2300 	ldrd	r2, r3, [r7]
+ 800938a:	f5a2 7180 	sub.w	r1, r2, #256	; 0x100
+ 800938e:	430b      	orrs	r3, r1
+ 8009390:	f040 8094 	bne.w	80094bc <HAL_RCCEx_GetPeriphCLKFreq+0x140>
+  {
+
+    saiclocksource = __HAL_RCC_GET_SAI1_SOURCE();
+ 8009394:	4b9b      	ldr	r3, [pc, #620]	; (8009604 <HAL_RCCEx_GetPeriphCLKFreq+0x288>)
+ 8009396:	6d1b      	ldr	r3, [r3, #80]	; 0x50
+ 8009398:	f003 0307 	and.w	r3, r3, #7
+ 800939c:	633b      	str	r3, [r7, #48]	; 0x30
+
+    switch (saiclocksource)
+ 800939e:	6b3b      	ldr	r3, [r7, #48]	; 0x30
+ 80093a0:	2b04      	cmp	r3, #4
+ 80093a2:	f200 8087 	bhi.w	80094b4 <HAL_RCCEx_GetPeriphCLKFreq+0x138>
+ 80093a6:	a201      	add	r2, pc, #4	; (adr r2, 80093ac <HAL_RCCEx_GetPeriphCLKFreq+0x30>)
+ 80093a8:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
+ 80093ac:	080093c1 	.word	0x080093c1
+ 80093b0:	080093e9 	.word	0x080093e9
+ 80093b4:	08009411 	.word	0x08009411
+ 80093b8:	080094ad 	.word	0x080094ad
+ 80093bc:	08009439 	.word	0x08009439
+    {
+      case RCC_SAI1CLKSOURCE_PLL: /* PLL1 is the clock source for SAI1 */
+      {
+        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY))
+ 80093c0:	4b90      	ldr	r3, [pc, #576]	; (8009604 <HAL_RCCEx_GetPeriphCLKFreq+0x288>)
+ 80093c2:	681b      	ldr	r3, [r3, #0]
+ 80093c4:	f003 7300 	and.w	r3, r3, #33554432	; 0x2000000
+ 80093c8:	f1b3 7f00 	cmp.w	r3, #33554432	; 0x2000000
+ 80093cc:	d108      	bne.n	80093e0 <HAL_RCCEx_GetPeriphCLKFreq+0x64>
+        {
+          HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
+ 80093ce:	f107 0324 	add.w	r3, r7, #36	; 0x24
+ 80093d2:	4618      	mov	r0, r3
+ 80093d4:	f000 ff62 	bl	800a29c <HAL_RCCEx_GetPLL1ClockFreq>
+          frequency = pll1_clocks.PLL1_Q_Frequency;
+ 80093d8:	6abb      	ldr	r3, [r7, #40]	; 0x28
+ 80093da:	63fb      	str	r3, [r7, #60]	; 0x3c
+        }
+        else
+        {
+          frequency = 0;
+        }
+        break;
+ 80093dc:	f000 bc93 	b.w	8009d06 <HAL_RCCEx_GetPeriphCLKFreq+0x98a>
+          frequency = 0;
+ 80093e0:	2300      	movs	r3, #0
+ 80093e2:	63fb      	str	r3, [r7, #60]	; 0x3c
+        break;
+ 80093e4:	f000 bc8f 	b.w	8009d06 <HAL_RCCEx_GetPeriphCLKFreq+0x98a>
+      }
+      case RCC_SAI1CLKSOURCE_PLL2: /* PLL2 is the clock source for SAI1 */
+      {
+        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY))
+ 80093e8:	4b86      	ldr	r3, [pc, #536]	; (8009604 <HAL_RCCEx_GetPeriphCLKFreq+0x288>)
+ 80093ea:	681b      	ldr	r3, [r3, #0]
+ 80093ec:	f003 6300 	and.w	r3, r3, #134217728	; 0x8000000
+ 80093f0:	f1b3 6f00 	cmp.w	r3, #134217728	; 0x8000000
+ 80093f4:	d108      	bne.n	8009408 <HAL_RCCEx_GetPeriphCLKFreq+0x8c>
+        {
+          HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
+ 80093f6:	f107 0318 	add.w	r3, r7, #24
+ 80093fa:	4618      	mov	r0, r3
+ 80093fc:	f000 fca6 	bl	8009d4c <HAL_RCCEx_GetPLL2ClockFreq>
+          frequency = pll2_clocks.PLL2_P_Frequency;
+ 8009400:	69bb      	ldr	r3, [r7, #24]
+ 8009402:	63fb      	str	r3, [r7, #60]	; 0x3c
+        }
+        else
+        {
+          frequency = 0;
+        }
+        break;
+ 8009404:	f000 bc7f 	b.w	8009d06 <HAL_RCCEx_GetPeriphCLKFreq+0x98a>
+          frequency = 0;
+ 8009408:	2300      	movs	r3, #0
+ 800940a:	63fb      	str	r3, [r7, #60]	; 0x3c
+        break;
+ 800940c:	f000 bc7b 	b.w	8009d06 <HAL_RCCEx_GetPeriphCLKFreq+0x98a>
+      }
+
+      case RCC_SAI1CLKSOURCE_PLL3: /* PLL3 is the clock source for SAI1 */
+      {
+        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY))
+ 8009410:	4b7c      	ldr	r3, [pc, #496]	; (8009604 <HAL_RCCEx_GetPeriphCLKFreq+0x288>)
+ 8009412:	681b      	ldr	r3, [r3, #0]
+ 8009414:	f003 5300 	and.w	r3, r3, #536870912	; 0x20000000
+ 8009418:	f1b3 5f00 	cmp.w	r3, #536870912	; 0x20000000
+ 800941c:	d108      	bne.n	8009430 <HAL_RCCEx_GetPeriphCLKFreq+0xb4>
+        {
+          HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
+ 800941e:	f107 030c 	add.w	r3, r7, #12
+ 8009422:	4618      	mov	r0, r3
+ 8009424:	f000 fde6 	bl	8009ff4 <HAL_RCCEx_GetPLL3ClockFreq>
+          frequency = pll3_clocks.PLL3_P_Frequency;
+ 8009428:	68fb      	ldr	r3, [r7, #12]
+ 800942a:	63fb      	str	r3, [r7, #60]	; 0x3c
+        }
+        else
+        {
+          frequency = 0;
+        }
+        break;
+ 800942c:	f000 bc6b 	b.w	8009d06 <HAL_RCCEx_GetPeriphCLKFreq+0x98a>
+          frequency = 0;
+ 8009430:	2300      	movs	r3, #0
+ 8009432:	63fb      	str	r3, [r7, #60]	; 0x3c
+        break;
+ 8009434:	f000 bc67 	b.w	8009d06 <HAL_RCCEx_GetPeriphCLKFreq+0x98a>
+      }
+
+      case RCC_SAI1CLKSOURCE_CLKP: /* CKPER is the clock source for SAI1*/
+      {
+
+        ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE();
+ 8009438:	4b72      	ldr	r3, [pc, #456]	; (8009604 <HAL_RCCEx_GetPeriphCLKFreq+0x288>)
+ 800943a:	6cdb      	ldr	r3, [r3, #76]	; 0x4c
+ 800943c:	f003 5340 	and.w	r3, r3, #805306368	; 0x30000000
+ 8009440:	637b      	str	r3, [r7, #52]	; 0x34
+
+        if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI))
+ 8009442:	4b70      	ldr	r3, [pc, #448]	; (8009604 <HAL_RCCEx_GetPeriphCLKFreq+0x288>)
+ 8009444:	681b      	ldr	r3, [r3, #0]
+ 8009446:	f003 0304 	and.w	r3, r3, #4
+ 800944a:	2b04      	cmp	r3, #4
+ 800944c:	d10c      	bne.n	8009468 <HAL_RCCEx_GetPeriphCLKFreq+0xec>
+ 800944e:	6b7b      	ldr	r3, [r7, #52]	; 0x34
+ 8009450:	2b00      	cmp	r3, #0
+ 8009452:	d109      	bne.n	8009468 <HAL_RCCEx_GetPeriphCLKFreq+0xec>
+        {
+          /* In Case the CKPER Source is HSI */
+          frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
+ 8009454:	4b6b      	ldr	r3, [pc, #428]	; (8009604 <HAL_RCCEx_GetPeriphCLKFreq+0x288>)
+ 8009456:	681b      	ldr	r3, [r3, #0]
+ 8009458:	08db      	lsrs	r3, r3, #3
+ 800945a:	f003 0303 	and.w	r3, r3, #3
+ 800945e:	4a6a      	ldr	r2, [pc, #424]	; (8009608 <HAL_RCCEx_GetPeriphCLKFreq+0x28c>)
+ 8009460:	fa22 f303 	lsr.w	r3, r2, r3
+ 8009464:	63fb      	str	r3, [r7, #60]	; 0x3c
+ 8009466:	e01f      	b.n	80094a8 <HAL_RCCEx_GetPeriphCLKFreq+0x12c>
+        }
+
+        else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI))
+ 8009468:	4b66      	ldr	r3, [pc, #408]	; (8009604 <HAL_RCCEx_GetPeriphCLKFreq+0x288>)
+ 800946a:	681b      	ldr	r3, [r3, #0]
+ 800946c:	f403 7380 	and.w	r3, r3, #256	; 0x100
+ 8009470:	f5b3 7f80 	cmp.w	r3, #256	; 0x100
+ 8009474:	d106      	bne.n	8009484 <HAL_RCCEx_GetPeriphCLKFreq+0x108>
+ 8009476:	6b7b      	ldr	r3, [r7, #52]	; 0x34
+ 8009478:	f1b3 5f80 	cmp.w	r3, #268435456	; 0x10000000
+ 800947c:	d102      	bne.n	8009484 <HAL_RCCEx_GetPeriphCLKFreq+0x108>
+        {
+          /* In Case the CKPER Source is CSI */
+          frequency = CSI_VALUE;
+ 800947e:	4b63      	ldr	r3, [pc, #396]	; (800960c <HAL_RCCEx_GetPeriphCLKFreq+0x290>)
+ 8009480:	63fb      	str	r3, [r7, #60]	; 0x3c
+ 8009482:	e011      	b.n	80094a8 <HAL_RCCEx_GetPeriphCLKFreq+0x12c>
+        }
+
+        else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE))
+ 8009484:	4b5f      	ldr	r3, [pc, #380]	; (8009604 <HAL_RCCEx_GetPeriphCLKFreq+0x288>)
+ 8009486:	681b      	ldr	r3, [r3, #0]
+ 8009488:	f403 3300 	and.w	r3, r3, #131072	; 0x20000
+ 800948c:	f5b3 3f00 	cmp.w	r3, #131072	; 0x20000
+ 8009490:	d106      	bne.n	80094a0 <HAL_RCCEx_GetPeriphCLKFreq+0x124>
+ 8009492:	6b7b      	ldr	r3, [r7, #52]	; 0x34
+ 8009494:	f1b3 5f00 	cmp.w	r3, #536870912	; 0x20000000
+ 8009498:	d102      	bne.n	80094a0 <HAL_RCCEx_GetPeriphCLKFreq+0x124>
+        {
+          /* In Case the CKPER Source is HSE */
+          frequency = HSE_VALUE;
+ 800949a:	4b5d      	ldr	r3, [pc, #372]	; (8009610 <HAL_RCCEx_GetPeriphCLKFreq+0x294>)
+ 800949c:	63fb      	str	r3, [r7, #60]	; 0x3c
+ 800949e:	e003      	b.n	80094a8 <HAL_RCCEx_GetPeriphCLKFreq+0x12c>
+        }
+
+        else
+        {
+          /* In Case the CKPER is disabled*/
+          frequency = 0;
+ 80094a0:	2300      	movs	r3, #0
+ 80094a2:	63fb      	str	r3, [r7, #60]	; 0x3c
+        }
+
+        break;
+ 80094a4:	f000 bc2f 	b.w	8009d06 <HAL_RCCEx_GetPeriphCLKFreq+0x98a>
+ 80094a8:	f000 bc2d 	b.w	8009d06 <HAL_RCCEx_GetPeriphCLKFreq+0x98a>
+      }
+
+      case (RCC_SAI1CLKSOURCE_PIN): /* External clock is the clock source for SAI1 */
+      {
+        frequency = EXTERNAL_CLOCK_VALUE;
+ 80094ac:	4b59      	ldr	r3, [pc, #356]	; (8009614 <HAL_RCCEx_GetPeriphCLKFreq+0x298>)
+ 80094ae:	63fb      	str	r3, [r7, #60]	; 0x3c
+        break;
+ 80094b0:	f000 bc29 	b.w	8009d06 <HAL_RCCEx_GetPeriphCLKFreq+0x98a>
+      }
+      default :
+      {
+        frequency = 0;
+ 80094b4:	2300      	movs	r3, #0
+ 80094b6:	63fb      	str	r3, [r7, #60]	; 0x3c
+        break;
+ 80094b8:	f000 bc25 	b.w	8009d06 <HAL_RCCEx_GetPeriphCLKFreq+0x98a>
+    }
+  }
+#endif
+
+#if defined(SAI4)
+  else if (PeriphClk == RCC_PERIPHCLK_SAI4A)
+ 80094bc:	e9d7 2300 	ldrd	r2, r3, [r7]
+ 80094c0:	f5a2 6180 	sub.w	r1, r2, #1024	; 0x400
+ 80094c4:	430b      	orrs	r3, r1
+ 80094c6:	f040 80a7 	bne.w	8009618 <HAL_RCCEx_GetPeriphCLKFreq+0x29c>
+  {
+
+    saiclocksource = __HAL_RCC_GET_SAI4A_SOURCE();
+ 80094ca:	4b4e      	ldr	r3, [pc, #312]	; (8009604 <HAL_RCCEx_GetPeriphCLKFreq+0x288>)
+ 80094cc:	6d9b      	ldr	r3, [r3, #88]	; 0x58
+ 80094ce:	f403 0360 	and.w	r3, r3, #14680064	; 0xe00000
+ 80094d2:	633b      	str	r3, [r7, #48]	; 0x30
+
+    switch (saiclocksource)
+ 80094d4:	6b3b      	ldr	r3, [r7, #48]	; 0x30
+ 80094d6:	f5b3 0f00 	cmp.w	r3, #8388608	; 0x800000
+ 80094da:	d054      	beq.n	8009586 <HAL_RCCEx_GetPeriphCLKFreq+0x20a>
+ 80094dc:	6b3b      	ldr	r3, [r7, #48]	; 0x30
+ 80094de:	f5b3 0f00 	cmp.w	r3, #8388608	; 0x800000
+ 80094e2:	f200 808b 	bhi.w	80095fc <HAL_RCCEx_GetPeriphCLKFreq+0x280>
+ 80094e6:	6b3b      	ldr	r3, [r7, #48]	; 0x30
+ 80094e8:	f5b3 0fc0 	cmp.w	r3, #6291456	; 0x600000
+ 80094ec:	f000 8083 	beq.w	80095f6 <HAL_RCCEx_GetPeriphCLKFreq+0x27a>
+ 80094f0:	6b3b      	ldr	r3, [r7, #48]	; 0x30
+ 80094f2:	f5b3 0fc0 	cmp.w	r3, #6291456	; 0x600000
+ 80094f6:	f200 8081 	bhi.w	80095fc <HAL_RCCEx_GetPeriphCLKFreq+0x280>
+ 80094fa:	6b3b      	ldr	r3, [r7, #48]	; 0x30
+ 80094fc:	f5b3 0f80 	cmp.w	r3, #4194304	; 0x400000
+ 8009500:	d02f      	beq.n	8009562 <HAL_RCCEx_GetPeriphCLKFreq+0x1e6>
+ 8009502:	6b3b      	ldr	r3, [r7, #48]	; 0x30
+ 8009504:	f5b3 0f80 	cmp.w	r3, #4194304	; 0x400000
+ 8009508:	d878      	bhi.n	80095fc <HAL_RCCEx_GetPeriphCLKFreq+0x280>
+ 800950a:	6b3b      	ldr	r3, [r7, #48]	; 0x30
+ 800950c:	2b00      	cmp	r3, #0
+ 800950e:	d004      	beq.n	800951a <HAL_RCCEx_GetPeriphCLKFreq+0x19e>
+ 8009510:	6b3b      	ldr	r3, [r7, #48]	; 0x30
+ 8009512:	f5b3 1f00 	cmp.w	r3, #2097152	; 0x200000
+ 8009516:	d012      	beq.n	800953e <HAL_RCCEx_GetPeriphCLKFreq+0x1c2>
+ 8009518:	e070      	b.n	80095fc <HAL_RCCEx_GetPeriphCLKFreq+0x280>
+    {
+      case RCC_SAI4ACLKSOURCE_PLL: /* PLL1 is the clock source for SAI4A */
+      {
+        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY))
+ 800951a:	4b3a      	ldr	r3, [pc, #232]	; (8009604 <HAL_RCCEx_GetPeriphCLKFreq+0x288>)
+ 800951c:	681b      	ldr	r3, [r3, #0]
+ 800951e:	f003 7300 	and.w	r3, r3, #33554432	; 0x2000000
+ 8009522:	f1b3 7f00 	cmp.w	r3, #33554432	; 0x2000000
+ 8009526:	d107      	bne.n	8009538 <HAL_RCCEx_GetPeriphCLKFreq+0x1bc>
+        {
+          HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
+ 8009528:	f107 0324 	add.w	r3, r7, #36	; 0x24
+ 800952c:	4618      	mov	r0, r3
+ 800952e:	f000 feb5 	bl	800a29c <HAL_RCCEx_GetPLL1ClockFreq>
+          frequency = pll1_clocks.PLL1_Q_Frequency;
+ 8009532:	6abb      	ldr	r3, [r7, #40]	; 0x28
+ 8009534:	63fb      	str	r3, [r7, #60]	; 0x3c
+        }
+        else
+        {
+          frequency = 0;
+        }
+        break;
+ 8009536:	e3e6      	b.n	8009d06 <HAL_RCCEx_GetPeriphCLKFreq+0x98a>
+          frequency = 0;
+ 8009538:	2300      	movs	r3, #0
+ 800953a:	63fb      	str	r3, [r7, #60]	; 0x3c
+        break;
+ 800953c:	e3e3      	b.n	8009d06 <HAL_RCCEx_GetPeriphCLKFreq+0x98a>
+      }
+      case RCC_SAI4ACLKSOURCE_PLL2: /* PLLI2 is the clock source for SAI4A */
+      {
+        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY))
+ 800953e:	4b31      	ldr	r3, [pc, #196]	; (8009604 <HAL_RCCEx_GetPeriphCLKFreq+0x288>)
+ 8009540:	681b      	ldr	r3, [r3, #0]
+ 8009542:	f003 6300 	and.w	r3, r3, #134217728	; 0x8000000
+ 8009546:	f1b3 6f00 	cmp.w	r3, #134217728	; 0x8000000
+ 800954a:	d107      	bne.n	800955c <HAL_RCCEx_GetPeriphCLKFreq+0x1e0>
+        {
+          HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
+ 800954c:	f107 0318 	add.w	r3, r7, #24
+ 8009550:	4618      	mov	r0, r3
+ 8009552:	f000 fbfb 	bl	8009d4c <HAL_RCCEx_GetPLL2ClockFreq>
+          frequency = pll2_clocks.PLL2_P_Frequency;
+ 8009556:	69bb      	ldr	r3, [r7, #24]
+ 8009558:	63fb      	str	r3, [r7, #60]	; 0x3c
+        }
+        else
+        {
+          frequency = 0;
+        }
+        break;
+ 800955a:	e3d4      	b.n	8009d06 <HAL_RCCEx_GetPeriphCLKFreq+0x98a>
+          frequency = 0;
+ 800955c:	2300      	movs	r3, #0
+ 800955e:	63fb      	str	r3, [r7, #60]	; 0x3c
+        break;
+ 8009560:	e3d1      	b.n	8009d06 <HAL_RCCEx_GetPeriphCLKFreq+0x98a>
+      }
+
+      case RCC_SAI4ACLKSOURCE_PLL3: /* PLLI3 is the clock source for SAI4A */
+      {
+        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY))
+ 8009562:	4b28      	ldr	r3, [pc, #160]	; (8009604 <HAL_RCCEx_GetPeriphCLKFreq+0x288>)
+ 8009564:	681b      	ldr	r3, [r3, #0]
+ 8009566:	f003 5300 	and.w	r3, r3, #536870912	; 0x20000000
+ 800956a:	f1b3 5f00 	cmp.w	r3, #536870912	; 0x20000000
+ 800956e:	d107      	bne.n	8009580 <HAL_RCCEx_GetPeriphCLKFreq+0x204>
+        {
+          HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
+ 8009570:	f107 030c 	add.w	r3, r7, #12
+ 8009574:	4618      	mov	r0, r3
+ 8009576:	f000 fd3d 	bl	8009ff4 <HAL_RCCEx_GetPLL3ClockFreq>
+          frequency = pll3_clocks.PLL3_P_Frequency;
+ 800957a:	68fb      	ldr	r3, [r7, #12]
+ 800957c:	63fb      	str	r3, [r7, #60]	; 0x3c
+        }
+        else
+        {
+          frequency = 0;
+        }
+        break;
+ 800957e:	e3c2      	b.n	8009d06 <HAL_RCCEx_GetPeriphCLKFreq+0x98a>
+          frequency = 0;
+ 8009580:	2300      	movs	r3, #0
+ 8009582:	63fb      	str	r3, [r7, #60]	; 0x3c
+        break;
+ 8009584:	e3bf      	b.n	8009d06 <HAL_RCCEx_GetPeriphCLKFreq+0x98a>
+      }
+
+      case RCC_SAI4ACLKSOURCE_CLKP: /* CKPER is the clock source for SAI4A*/
+      {
+
+        ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE();
+ 8009586:	4b1f      	ldr	r3, [pc, #124]	; (8009604 <HAL_RCCEx_GetPeriphCLKFreq+0x288>)
+ 8009588:	6cdb      	ldr	r3, [r3, #76]	; 0x4c
+ 800958a:	f003 5340 	and.w	r3, r3, #805306368	; 0x30000000
+ 800958e:	637b      	str	r3, [r7, #52]	; 0x34
+
+        if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI))
+ 8009590:	4b1c      	ldr	r3, [pc, #112]	; (8009604 <HAL_RCCEx_GetPeriphCLKFreq+0x288>)
+ 8009592:	681b      	ldr	r3, [r3, #0]
+ 8009594:	f003 0304 	and.w	r3, r3, #4
+ 8009598:	2b04      	cmp	r3, #4
+ 800959a:	d10c      	bne.n	80095b6 <HAL_RCCEx_GetPeriphCLKFreq+0x23a>
+ 800959c:	6b7b      	ldr	r3, [r7, #52]	; 0x34
+ 800959e:	2b00      	cmp	r3, #0
+ 80095a0:	d109      	bne.n	80095b6 <HAL_RCCEx_GetPeriphCLKFreq+0x23a>
+        {
+          /* In Case the CKPER Source is HSI */
+          frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
+ 80095a2:	4b18      	ldr	r3, [pc, #96]	; (8009604 <HAL_RCCEx_GetPeriphCLKFreq+0x288>)
+ 80095a4:	681b      	ldr	r3, [r3, #0]
+ 80095a6:	08db      	lsrs	r3, r3, #3
+ 80095a8:	f003 0303 	and.w	r3, r3, #3
+ 80095ac:	4a16      	ldr	r2, [pc, #88]	; (8009608 <HAL_RCCEx_GetPeriphCLKFreq+0x28c>)
+ 80095ae:	fa22 f303 	lsr.w	r3, r2, r3
+ 80095b2:	63fb      	str	r3, [r7, #60]	; 0x3c
+ 80095b4:	e01e      	b.n	80095f4 <HAL_RCCEx_GetPeriphCLKFreq+0x278>
+        }
+
+        else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI))
+ 80095b6:	4b13      	ldr	r3, [pc, #76]	; (8009604 <HAL_RCCEx_GetPeriphCLKFreq+0x288>)
+ 80095b8:	681b      	ldr	r3, [r3, #0]
+ 80095ba:	f403 7380 	and.w	r3, r3, #256	; 0x100
+ 80095be:	f5b3 7f80 	cmp.w	r3, #256	; 0x100
+ 80095c2:	d106      	bne.n	80095d2 <HAL_RCCEx_GetPeriphCLKFreq+0x256>
+ 80095c4:	6b7b      	ldr	r3, [r7, #52]	; 0x34
+ 80095c6:	f1b3 5f80 	cmp.w	r3, #268435456	; 0x10000000
+ 80095ca:	d102      	bne.n	80095d2 <HAL_RCCEx_GetPeriphCLKFreq+0x256>
+        {
+          /* In Case the CKPER Source is CSI */
+          frequency = CSI_VALUE;
+ 80095cc:	4b0f      	ldr	r3, [pc, #60]	; (800960c <HAL_RCCEx_GetPeriphCLKFreq+0x290>)
+ 80095ce:	63fb      	str	r3, [r7, #60]	; 0x3c
+ 80095d0:	e010      	b.n	80095f4 <HAL_RCCEx_GetPeriphCLKFreq+0x278>
+        }
+
+        else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE))
+ 80095d2:	4b0c      	ldr	r3, [pc, #48]	; (8009604 <HAL_RCCEx_GetPeriphCLKFreq+0x288>)
+ 80095d4:	681b      	ldr	r3, [r3, #0]
+ 80095d6:	f403 3300 	and.w	r3, r3, #131072	; 0x20000
+ 80095da:	f5b3 3f00 	cmp.w	r3, #131072	; 0x20000
+ 80095de:	d106      	bne.n	80095ee <HAL_RCCEx_GetPeriphCLKFreq+0x272>
+ 80095e0:	6b7b      	ldr	r3, [r7, #52]	; 0x34
+ 80095e2:	f1b3 5f00 	cmp.w	r3, #536870912	; 0x20000000
+ 80095e6:	d102      	bne.n	80095ee <HAL_RCCEx_GetPeriphCLKFreq+0x272>
+        {
+          /* In Case the CKPER Source is HSE */
+          frequency = HSE_VALUE;
+ 80095e8:	4b09      	ldr	r3, [pc, #36]	; (8009610 <HAL_RCCEx_GetPeriphCLKFreq+0x294>)
+ 80095ea:	63fb      	str	r3, [r7, #60]	; 0x3c
+ 80095ec:	e002      	b.n	80095f4 <HAL_RCCEx_GetPeriphCLKFreq+0x278>
+        }
+
+        else
+        {
+          /* In Case the CKPER is disabled*/
+          frequency = 0;
+ 80095ee:	2300      	movs	r3, #0
+ 80095f0:	63fb      	str	r3, [r7, #60]	; 0x3c
+        }
+
+        break;
+ 80095f2:	e388      	b.n	8009d06 <HAL_RCCEx_GetPeriphCLKFreq+0x98a>
+ 80095f4:	e387      	b.n	8009d06 <HAL_RCCEx_GetPeriphCLKFreq+0x98a>
+      }
+
+      case RCC_SAI4ACLKSOURCE_PIN: /* External clock is the clock source for SAI4A */
+      {
+        frequency = EXTERNAL_CLOCK_VALUE;
+ 80095f6:	4b07      	ldr	r3, [pc, #28]	; (8009614 <HAL_RCCEx_GetPeriphCLKFreq+0x298>)
+ 80095f8:	63fb      	str	r3, [r7, #60]	; 0x3c
+        break;
+ 80095fa:	e384      	b.n	8009d06 <HAL_RCCEx_GetPeriphCLKFreq+0x98a>
+      }
+
+      default :
+      {
+        frequency = 0;
+ 80095fc:	2300      	movs	r3, #0
+ 80095fe:	63fb      	str	r3, [r7, #60]	; 0x3c
+        break;
+ 8009600:	e381      	b.n	8009d06 <HAL_RCCEx_GetPeriphCLKFreq+0x98a>
+ 8009602:	bf00      	nop
+ 8009604:	58024400 	.word	0x58024400
+ 8009608:	03d09000 	.word	0x03d09000
+ 800960c:	003d0900 	.word	0x003d0900
+ 8009610:	017d7840 	.word	0x017d7840
+ 8009614:	00bb8000 	.word	0x00bb8000
+      }
+    }
+  }
+
+  else if (PeriphClk == RCC_PERIPHCLK_SAI4B)
+ 8009618:	e9d7 2300 	ldrd	r2, r3, [r7]
+ 800961c:	f5a2 6100 	sub.w	r1, r2, #2048	; 0x800
+ 8009620:	430b      	orrs	r3, r1
+ 8009622:	f040 809c 	bne.w	800975e <HAL_RCCEx_GetPeriphCLKFreq+0x3e2>
+  {
+
+    saiclocksource = __HAL_RCC_GET_SAI4B_SOURCE();
+ 8009626:	4b9e      	ldr	r3, [pc, #632]	; (80098a0 <HAL_RCCEx_GetPeriphCLKFreq+0x524>)
+ 8009628:	6d9b      	ldr	r3, [r3, #88]	; 0x58
+ 800962a:	f003 63e0 	and.w	r3, r3, #117440512	; 0x7000000
+ 800962e:	633b      	str	r3, [r7, #48]	; 0x30
+
+    switch (saiclocksource)
+ 8009630:	6b3b      	ldr	r3, [r7, #48]	; 0x30
+ 8009632:	f1b3 6f80 	cmp.w	r3, #67108864	; 0x4000000
+ 8009636:	d054      	beq.n	80096e2 <HAL_RCCEx_GetPeriphCLKFreq+0x366>
+ 8009638:	6b3b      	ldr	r3, [r7, #48]	; 0x30
+ 800963a:	f1b3 6f80 	cmp.w	r3, #67108864	; 0x4000000
+ 800963e:	f200 808b 	bhi.w	8009758 <HAL_RCCEx_GetPeriphCLKFreq+0x3dc>
+ 8009642:	6b3b      	ldr	r3, [r7, #48]	; 0x30
+ 8009644:	f1b3 7f40 	cmp.w	r3, #50331648	; 0x3000000
+ 8009648:	f000 8083 	beq.w	8009752 <HAL_RCCEx_GetPeriphCLKFreq+0x3d6>
+ 800964c:	6b3b      	ldr	r3, [r7, #48]	; 0x30
+ 800964e:	f1b3 7f40 	cmp.w	r3, #50331648	; 0x3000000
+ 8009652:	f200 8081 	bhi.w	8009758 <HAL_RCCEx_GetPeriphCLKFreq+0x3dc>
+ 8009656:	6b3b      	ldr	r3, [r7, #48]	; 0x30
+ 8009658:	f1b3 7f00 	cmp.w	r3, #33554432	; 0x2000000
+ 800965c:	d02f      	beq.n	80096be <HAL_RCCEx_GetPeriphCLKFreq+0x342>
+ 800965e:	6b3b      	ldr	r3, [r7, #48]	; 0x30
+ 8009660:	f1b3 7f00 	cmp.w	r3, #33554432	; 0x2000000
+ 8009664:	d878      	bhi.n	8009758 <HAL_RCCEx_GetPeriphCLKFreq+0x3dc>
+ 8009666:	6b3b      	ldr	r3, [r7, #48]	; 0x30
+ 8009668:	2b00      	cmp	r3, #0
+ 800966a:	d004      	beq.n	8009676 <HAL_RCCEx_GetPeriphCLKFreq+0x2fa>
+ 800966c:	6b3b      	ldr	r3, [r7, #48]	; 0x30
+ 800966e:	f1b3 7f80 	cmp.w	r3, #16777216	; 0x1000000
+ 8009672:	d012      	beq.n	800969a <HAL_RCCEx_GetPeriphCLKFreq+0x31e>
+ 8009674:	e070      	b.n	8009758 <HAL_RCCEx_GetPeriphCLKFreq+0x3dc>
+    {
+      case RCC_SAI4BCLKSOURCE_PLL: /* PLL1 is the clock source for SAI4B */
+      {
+        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY))
+ 8009676:	4b8a      	ldr	r3, [pc, #552]	; (80098a0 <HAL_RCCEx_GetPeriphCLKFreq+0x524>)
+ 8009678:	681b      	ldr	r3, [r3, #0]
+ 800967a:	f003 7300 	and.w	r3, r3, #33554432	; 0x2000000
+ 800967e:	f1b3 7f00 	cmp.w	r3, #33554432	; 0x2000000
+ 8009682:	d107      	bne.n	8009694 <HAL_RCCEx_GetPeriphCLKFreq+0x318>
+        {
+          HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
+ 8009684:	f107 0324 	add.w	r3, r7, #36	; 0x24
+ 8009688:	4618      	mov	r0, r3
+ 800968a:	f000 fe07 	bl	800a29c <HAL_RCCEx_GetPLL1ClockFreq>
+          frequency = pll1_clocks.PLL1_Q_Frequency;
+ 800968e:	6abb      	ldr	r3, [r7, #40]	; 0x28
+ 8009690:	63fb      	str	r3, [r7, #60]	; 0x3c
+        }
+        else
+        {
+          frequency = 0;
+        }
+        break;
+ 8009692:	e338      	b.n	8009d06 <HAL_RCCEx_GetPeriphCLKFreq+0x98a>
+          frequency = 0;
+ 8009694:	2300      	movs	r3, #0
+ 8009696:	63fb      	str	r3, [r7, #60]	; 0x3c
+        break;
+ 8009698:	e335      	b.n	8009d06 <HAL_RCCEx_GetPeriphCLKFreq+0x98a>
+      }
+      case RCC_SAI4BCLKSOURCE_PLL2: /* PLLI2 is the clock source for SAI4B */
+      {
+        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY))
+ 800969a:	4b81      	ldr	r3, [pc, #516]	; (80098a0 <HAL_RCCEx_GetPeriphCLKFreq+0x524>)
+ 800969c:	681b      	ldr	r3, [r3, #0]
+ 800969e:	f003 6300 	and.w	r3, r3, #134217728	; 0x8000000
+ 80096a2:	f1b3 6f00 	cmp.w	r3, #134217728	; 0x8000000
+ 80096a6:	d107      	bne.n	80096b8 <HAL_RCCEx_GetPeriphCLKFreq+0x33c>
+        {
+          HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
+ 80096a8:	f107 0318 	add.w	r3, r7, #24
+ 80096ac:	4618      	mov	r0, r3
+ 80096ae:	f000 fb4d 	bl	8009d4c <HAL_RCCEx_GetPLL2ClockFreq>
+          frequency = pll2_clocks.PLL2_P_Frequency;
+ 80096b2:	69bb      	ldr	r3, [r7, #24]
+ 80096b4:	63fb      	str	r3, [r7, #60]	; 0x3c
+        }
+        else
+        {
+          frequency = 0;
+        }
+        break;
+ 80096b6:	e326      	b.n	8009d06 <HAL_RCCEx_GetPeriphCLKFreq+0x98a>
+          frequency = 0;
+ 80096b8:	2300      	movs	r3, #0
+ 80096ba:	63fb      	str	r3, [r7, #60]	; 0x3c
+        break;
+ 80096bc:	e323      	b.n	8009d06 <HAL_RCCEx_GetPeriphCLKFreq+0x98a>
+      }
+
+      case RCC_SAI4BCLKSOURCE_PLL3: /* PLLI3 is the clock source for SAI4B */
+      {
+        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY))
+ 80096be:	4b78      	ldr	r3, [pc, #480]	; (80098a0 <HAL_RCCEx_GetPeriphCLKFreq+0x524>)
+ 80096c0:	681b      	ldr	r3, [r3, #0]
+ 80096c2:	f003 5300 	and.w	r3, r3, #536870912	; 0x20000000
+ 80096c6:	f1b3 5f00 	cmp.w	r3, #536870912	; 0x20000000
+ 80096ca:	d107      	bne.n	80096dc <HAL_RCCEx_GetPeriphCLKFreq+0x360>
+        {
+          HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
+ 80096cc:	f107 030c 	add.w	r3, r7, #12
+ 80096d0:	4618      	mov	r0, r3
+ 80096d2:	f000 fc8f 	bl	8009ff4 <HAL_RCCEx_GetPLL3ClockFreq>
+          frequency = pll3_clocks.PLL3_P_Frequency;
+ 80096d6:	68fb      	ldr	r3, [r7, #12]
+ 80096d8:	63fb      	str	r3, [r7, #60]	; 0x3c
+        }
+        else
+        {
+          frequency = 0;
+        }
+        break;
+ 80096da:	e314      	b.n	8009d06 <HAL_RCCEx_GetPeriphCLKFreq+0x98a>
+          frequency = 0;
+ 80096dc:	2300      	movs	r3, #0
+ 80096de:	63fb      	str	r3, [r7, #60]	; 0x3c
+        break;
+ 80096e0:	e311      	b.n	8009d06 <HAL_RCCEx_GetPeriphCLKFreq+0x98a>
+      }
+
+      case RCC_SAI4BCLKSOURCE_CLKP: /* CKPER is the clock source for SAI4B*/
+      {
+
+        ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE();
+ 80096e2:	4b6f      	ldr	r3, [pc, #444]	; (80098a0 <HAL_RCCEx_GetPeriphCLKFreq+0x524>)
+ 80096e4:	6cdb      	ldr	r3, [r3, #76]	; 0x4c
+ 80096e6:	f003 5340 	and.w	r3, r3, #805306368	; 0x30000000
+ 80096ea:	637b      	str	r3, [r7, #52]	; 0x34
+
+        if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI))
+ 80096ec:	4b6c      	ldr	r3, [pc, #432]	; (80098a0 <HAL_RCCEx_GetPeriphCLKFreq+0x524>)
+ 80096ee:	681b      	ldr	r3, [r3, #0]
+ 80096f0:	f003 0304 	and.w	r3, r3, #4
+ 80096f4:	2b04      	cmp	r3, #4
+ 80096f6:	d10c      	bne.n	8009712 <HAL_RCCEx_GetPeriphCLKFreq+0x396>
+ 80096f8:	6b7b      	ldr	r3, [r7, #52]	; 0x34
+ 80096fa:	2b00      	cmp	r3, #0
+ 80096fc:	d109      	bne.n	8009712 <HAL_RCCEx_GetPeriphCLKFreq+0x396>
+        {
+          /* In Case the CKPER Source is HSI */
+          frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
+ 80096fe:	4b68      	ldr	r3, [pc, #416]	; (80098a0 <HAL_RCCEx_GetPeriphCLKFreq+0x524>)
+ 8009700:	681b      	ldr	r3, [r3, #0]
+ 8009702:	08db      	lsrs	r3, r3, #3
+ 8009704:	f003 0303 	and.w	r3, r3, #3
+ 8009708:	4a66      	ldr	r2, [pc, #408]	; (80098a4 <HAL_RCCEx_GetPeriphCLKFreq+0x528>)
+ 800970a:	fa22 f303 	lsr.w	r3, r2, r3
+ 800970e:	63fb      	str	r3, [r7, #60]	; 0x3c
+ 8009710:	e01e      	b.n	8009750 <HAL_RCCEx_GetPeriphCLKFreq+0x3d4>
+        }
+
+        else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI))
+ 8009712:	4b63      	ldr	r3, [pc, #396]	; (80098a0 <HAL_RCCEx_GetPeriphCLKFreq+0x524>)
+ 8009714:	681b      	ldr	r3, [r3, #0]
+ 8009716:	f403 7380 	and.w	r3, r3, #256	; 0x100
+ 800971a:	f5b3 7f80 	cmp.w	r3, #256	; 0x100
+ 800971e:	d106      	bne.n	800972e <HAL_RCCEx_GetPeriphCLKFreq+0x3b2>
+ 8009720:	6b7b      	ldr	r3, [r7, #52]	; 0x34
+ 8009722:	f1b3 5f80 	cmp.w	r3, #268435456	; 0x10000000
+ 8009726:	d102      	bne.n	800972e <HAL_RCCEx_GetPeriphCLKFreq+0x3b2>
+        {
+          /* In Case the CKPER Source is CSI */
+          frequency = CSI_VALUE;
+ 8009728:	4b5f      	ldr	r3, [pc, #380]	; (80098a8 <HAL_RCCEx_GetPeriphCLKFreq+0x52c>)
+ 800972a:	63fb      	str	r3, [r7, #60]	; 0x3c
+ 800972c:	e010      	b.n	8009750 <HAL_RCCEx_GetPeriphCLKFreq+0x3d4>
+        }
+
+        else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE))
+ 800972e:	4b5c      	ldr	r3, [pc, #368]	; (80098a0 <HAL_RCCEx_GetPeriphCLKFreq+0x524>)
+ 8009730:	681b      	ldr	r3, [r3, #0]
+ 8009732:	f403 3300 	and.w	r3, r3, #131072	; 0x20000
+ 8009736:	f5b3 3f00 	cmp.w	r3, #131072	; 0x20000
+ 800973a:	d106      	bne.n	800974a <HAL_RCCEx_GetPeriphCLKFreq+0x3ce>
+ 800973c:	6b7b      	ldr	r3, [r7, #52]	; 0x34
+ 800973e:	f1b3 5f00 	cmp.w	r3, #536870912	; 0x20000000
+ 8009742:	d102      	bne.n	800974a <HAL_RCCEx_GetPeriphCLKFreq+0x3ce>
+        {
+          /* In Case the CKPER Source is HSE */
+          frequency = HSE_VALUE;
+ 8009744:	4b59      	ldr	r3, [pc, #356]	; (80098ac <HAL_RCCEx_GetPeriphCLKFreq+0x530>)
+ 8009746:	63fb      	str	r3, [r7, #60]	; 0x3c
+ 8009748:	e002      	b.n	8009750 <HAL_RCCEx_GetPeriphCLKFreq+0x3d4>
+        }
+
+        else
+        {
+          /* In Case the CKPER is disabled*/
+          frequency = 0;
+ 800974a:	2300      	movs	r3, #0
+ 800974c:	63fb      	str	r3, [r7, #60]	; 0x3c
+        }
+
+        break;
+ 800974e:	e2da      	b.n	8009d06 <HAL_RCCEx_GetPeriphCLKFreq+0x98a>
+ 8009750:	e2d9      	b.n	8009d06 <HAL_RCCEx_GetPeriphCLKFreq+0x98a>
+      }
+
+      case RCC_SAI4BCLKSOURCE_PIN: /* External clock is the clock source for SAI4B */
+      {
+        frequency = EXTERNAL_CLOCK_VALUE;
+ 8009752:	4b57      	ldr	r3, [pc, #348]	; (80098b0 <HAL_RCCEx_GetPeriphCLKFreq+0x534>)
+ 8009754:	63fb      	str	r3, [r7, #60]	; 0x3c
+        break;
+ 8009756:	e2d6      	b.n	8009d06 <HAL_RCCEx_GetPeriphCLKFreq+0x98a>
+      }
+
+      default :
+      {
+        frequency = 0;
+ 8009758:	2300      	movs	r3, #0
+ 800975a:	63fb      	str	r3, [r7, #60]	; 0x3c
+        break;
+ 800975c:	e2d3      	b.n	8009d06 <HAL_RCCEx_GetPeriphCLKFreq+0x98a>
+      }
+    }
+  }
+#endif /*SAI4*/
+  else if (PeriphClk == RCC_PERIPHCLK_SPI123)
+ 800975e:	e9d7 2300 	ldrd	r2, r3, [r7]
+ 8009762:	f5a2 5180 	sub.w	r1, r2, #4096	; 0x1000
+ 8009766:	430b      	orrs	r3, r1
+ 8009768:	f040 80a7 	bne.w	80098ba <HAL_RCCEx_GetPeriphCLKFreq+0x53e>
+  {
+    /* Get SPI1/2/3 clock source */
+    srcclk = __HAL_RCC_GET_SPI123_SOURCE();
+ 800976c:	4b4c      	ldr	r3, [pc, #304]	; (80098a0 <HAL_RCCEx_GetPeriphCLKFreq+0x524>)
+ 800976e:	6d1b      	ldr	r3, [r3, #80]	; 0x50
+ 8009770:	f403 43e0 	and.w	r3, r3, #28672	; 0x7000
+ 8009774:	63bb      	str	r3, [r7, #56]	; 0x38
+
+    switch (srcclk)
+ 8009776:	6bbb      	ldr	r3, [r7, #56]	; 0x38
+ 8009778:	f5b3 4f80 	cmp.w	r3, #16384	; 0x4000
+ 800977c:	d055      	beq.n	800982a <HAL_RCCEx_GetPeriphCLKFreq+0x4ae>
+ 800977e:	6bbb      	ldr	r3, [r7, #56]	; 0x38
+ 8009780:	f5b3 4f80 	cmp.w	r3, #16384	; 0x4000
+ 8009784:	f200 8096 	bhi.w	80098b4 <HAL_RCCEx_GetPeriphCLKFreq+0x538>
+ 8009788:	6bbb      	ldr	r3, [r7, #56]	; 0x38
+ 800978a:	f5b3 5f40 	cmp.w	r3, #12288	; 0x3000
+ 800978e:	f000 8084 	beq.w	800989a <HAL_RCCEx_GetPeriphCLKFreq+0x51e>
+ 8009792:	6bbb      	ldr	r3, [r7, #56]	; 0x38
+ 8009794:	f5b3 5f40 	cmp.w	r3, #12288	; 0x3000
+ 8009798:	f200 808c 	bhi.w	80098b4 <HAL_RCCEx_GetPeriphCLKFreq+0x538>
+ 800979c:	6bbb      	ldr	r3, [r7, #56]	; 0x38
+ 800979e:	f5b3 5f00 	cmp.w	r3, #8192	; 0x2000
+ 80097a2:	d030      	beq.n	8009806 <HAL_RCCEx_GetPeriphCLKFreq+0x48a>
+ 80097a4:	6bbb      	ldr	r3, [r7, #56]	; 0x38
+ 80097a6:	f5b3 5f00 	cmp.w	r3, #8192	; 0x2000
+ 80097aa:	f200 8083 	bhi.w	80098b4 <HAL_RCCEx_GetPeriphCLKFreq+0x538>
+ 80097ae:	6bbb      	ldr	r3, [r7, #56]	; 0x38
+ 80097b0:	2b00      	cmp	r3, #0
+ 80097b2:	d004      	beq.n	80097be <HAL_RCCEx_GetPeriphCLKFreq+0x442>
+ 80097b4:	6bbb      	ldr	r3, [r7, #56]	; 0x38
+ 80097b6:	f5b3 5f80 	cmp.w	r3, #4096	; 0x1000
+ 80097ba:	d012      	beq.n	80097e2 <HAL_RCCEx_GetPeriphCLKFreq+0x466>
+ 80097bc:	e07a      	b.n	80098b4 <HAL_RCCEx_GetPeriphCLKFreq+0x538>
+    {
+      case RCC_SPI123CLKSOURCE_PLL: /* PLL1 is the clock source for SPI123 */
+      {
+        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY))
+ 80097be:	4b38      	ldr	r3, [pc, #224]	; (80098a0 <HAL_RCCEx_GetPeriphCLKFreq+0x524>)
+ 80097c0:	681b      	ldr	r3, [r3, #0]
+ 80097c2:	f003 7300 	and.w	r3, r3, #33554432	; 0x2000000
+ 80097c6:	f1b3 7f00 	cmp.w	r3, #33554432	; 0x2000000
+ 80097ca:	d107      	bne.n	80097dc <HAL_RCCEx_GetPeriphCLKFreq+0x460>
+        {
+          HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
+ 80097cc:	f107 0324 	add.w	r3, r7, #36	; 0x24
+ 80097d0:	4618      	mov	r0, r3
+ 80097d2:	f000 fd63 	bl	800a29c <HAL_RCCEx_GetPLL1ClockFreq>
+          frequency = pll1_clocks.PLL1_Q_Frequency;
+ 80097d6:	6abb      	ldr	r3, [r7, #40]	; 0x28
+ 80097d8:	63fb      	str	r3, [r7, #60]	; 0x3c
+        }
+        else
+        {
+          frequency = 0;
+        }
+        break;
+ 80097da:	e294      	b.n	8009d06 <HAL_RCCEx_GetPeriphCLKFreq+0x98a>
+          frequency = 0;
+ 80097dc:	2300      	movs	r3, #0
+ 80097de:	63fb      	str	r3, [r7, #60]	; 0x3c
+        break;
+ 80097e0:	e291      	b.n	8009d06 <HAL_RCCEx_GetPeriphCLKFreq+0x98a>
+      }
+      case RCC_SPI123CLKSOURCE_PLL2: /* PLL2 is the clock source for SPI123 */
+      {
+        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY))
+ 80097e2:	4b2f      	ldr	r3, [pc, #188]	; (80098a0 <HAL_RCCEx_GetPeriphCLKFreq+0x524>)
+ 80097e4:	681b      	ldr	r3, [r3, #0]
+ 80097e6:	f003 6300 	and.w	r3, r3, #134217728	; 0x8000000
+ 80097ea:	f1b3 6f00 	cmp.w	r3, #134217728	; 0x8000000
+ 80097ee:	d107      	bne.n	8009800 <HAL_RCCEx_GetPeriphCLKFreq+0x484>
+        {
+          HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
+ 80097f0:	f107 0318 	add.w	r3, r7, #24
+ 80097f4:	4618      	mov	r0, r3
+ 80097f6:	f000 faa9 	bl	8009d4c <HAL_RCCEx_GetPLL2ClockFreq>
+          frequency = pll2_clocks.PLL2_P_Frequency;
+ 80097fa:	69bb      	ldr	r3, [r7, #24]
+ 80097fc:	63fb      	str	r3, [r7, #60]	; 0x3c
+        }
+        else
+        {
+          frequency = 0;
+        }
+        break;
+ 80097fe:	e282      	b.n	8009d06 <HAL_RCCEx_GetPeriphCLKFreq+0x98a>
+          frequency = 0;
+ 8009800:	2300      	movs	r3, #0
+ 8009802:	63fb      	str	r3, [r7, #60]	; 0x3c
+        break;
+ 8009804:	e27f      	b.n	8009d06 <HAL_RCCEx_GetPeriphCLKFreq+0x98a>
+      }
+
+      case RCC_SPI123CLKSOURCE_PLL3: /* PLL3 is the clock source for SPI123 */
+      {
+        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY))
+ 8009806:	4b26      	ldr	r3, [pc, #152]	; (80098a0 <HAL_RCCEx_GetPeriphCLKFreq+0x524>)
+ 8009808:	681b      	ldr	r3, [r3, #0]
+ 800980a:	f003 5300 	and.w	r3, r3, #536870912	; 0x20000000
+ 800980e:	f1b3 5f00 	cmp.w	r3, #536870912	; 0x20000000
+ 8009812:	d107      	bne.n	8009824 <HAL_RCCEx_GetPeriphCLKFreq+0x4a8>
+        {
+          HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
+ 8009814:	f107 030c 	add.w	r3, r7, #12
+ 8009818:	4618      	mov	r0, r3
+ 800981a:	f000 fbeb 	bl	8009ff4 <HAL_RCCEx_GetPLL3ClockFreq>
+          frequency = pll3_clocks.PLL3_P_Frequency;
+ 800981e:	68fb      	ldr	r3, [r7, #12]
+ 8009820:	63fb      	str	r3, [r7, #60]	; 0x3c
+        }
+        else
+        {
+          frequency = 0;
+        }
+        break;
+ 8009822:	e270      	b.n	8009d06 <HAL_RCCEx_GetPeriphCLKFreq+0x98a>
+          frequency = 0;
+ 8009824:	2300      	movs	r3, #0
+ 8009826:	63fb      	str	r3, [r7, #60]	; 0x3c
+        break;
+ 8009828:	e26d      	b.n	8009d06 <HAL_RCCEx_GetPeriphCLKFreq+0x98a>
+      }
+
+      case RCC_SPI123CLKSOURCE_CLKP: /* CKPER is the clock source for SPI123 */
+      {
+
+        ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE();
+ 800982a:	4b1d      	ldr	r3, [pc, #116]	; (80098a0 <HAL_RCCEx_GetPeriphCLKFreq+0x524>)
+ 800982c:	6cdb      	ldr	r3, [r3, #76]	; 0x4c
+ 800982e:	f003 5340 	and.w	r3, r3, #805306368	; 0x30000000
+ 8009832:	637b      	str	r3, [r7, #52]	; 0x34
+
+        if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI))
+ 8009834:	4b1a      	ldr	r3, [pc, #104]	; (80098a0 <HAL_RCCEx_GetPeriphCLKFreq+0x524>)
+ 8009836:	681b      	ldr	r3, [r3, #0]
+ 8009838:	f003 0304 	and.w	r3, r3, #4
+ 800983c:	2b04      	cmp	r3, #4
+ 800983e:	d10c      	bne.n	800985a <HAL_RCCEx_GetPeriphCLKFreq+0x4de>
+ 8009840:	6b7b      	ldr	r3, [r7, #52]	; 0x34
+ 8009842:	2b00      	cmp	r3, #0
+ 8009844:	d109      	bne.n	800985a <HAL_RCCEx_GetPeriphCLKFreq+0x4de>
+        {
+          /* In Case the CKPER Source is HSI */
+          frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
+ 8009846:	4b16      	ldr	r3, [pc, #88]	; (80098a0 <HAL_RCCEx_GetPeriphCLKFreq+0x524>)
+ 8009848:	681b      	ldr	r3, [r3, #0]
+ 800984a:	08db      	lsrs	r3, r3, #3
+ 800984c:	f003 0303 	and.w	r3, r3, #3
+ 8009850:	4a14      	ldr	r2, [pc, #80]	; (80098a4 <HAL_RCCEx_GetPeriphCLKFreq+0x528>)
+ 8009852:	fa22 f303 	lsr.w	r3, r2, r3
+ 8009856:	63fb      	str	r3, [r7, #60]	; 0x3c
+ 8009858:	e01e      	b.n	8009898 <HAL_RCCEx_GetPeriphCLKFreq+0x51c>
+        }
+
+        else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI))
+ 800985a:	4b11      	ldr	r3, [pc, #68]	; (80098a0 <HAL_RCCEx_GetPeriphCLKFreq+0x524>)
+ 800985c:	681b      	ldr	r3, [r3, #0]
+ 800985e:	f403 7380 	and.w	r3, r3, #256	; 0x100
+ 8009862:	f5b3 7f80 	cmp.w	r3, #256	; 0x100
+ 8009866:	d106      	bne.n	8009876 <HAL_RCCEx_GetPeriphCLKFreq+0x4fa>
+ 8009868:	6b7b      	ldr	r3, [r7, #52]	; 0x34
+ 800986a:	f1b3 5f80 	cmp.w	r3, #268435456	; 0x10000000
+ 800986e:	d102      	bne.n	8009876 <HAL_RCCEx_GetPeriphCLKFreq+0x4fa>
+        {
+          /* In Case the CKPER Source is CSI */
+          frequency = CSI_VALUE;
+ 8009870:	4b0d      	ldr	r3, [pc, #52]	; (80098a8 <HAL_RCCEx_GetPeriphCLKFreq+0x52c>)
+ 8009872:	63fb      	str	r3, [r7, #60]	; 0x3c
+ 8009874:	e010      	b.n	8009898 <HAL_RCCEx_GetPeriphCLKFreq+0x51c>
+        }
+
+        else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE))
+ 8009876:	4b0a      	ldr	r3, [pc, #40]	; (80098a0 <HAL_RCCEx_GetPeriphCLKFreq+0x524>)
+ 8009878:	681b      	ldr	r3, [r3, #0]
+ 800987a:	f403 3300 	and.w	r3, r3, #131072	; 0x20000
+ 800987e:	f5b3 3f00 	cmp.w	r3, #131072	; 0x20000
+ 8009882:	d106      	bne.n	8009892 <HAL_RCCEx_GetPeriphCLKFreq+0x516>
+ 8009884:	6b7b      	ldr	r3, [r7, #52]	; 0x34
+ 8009886:	f1b3 5f00 	cmp.w	r3, #536870912	; 0x20000000
+ 800988a:	d102      	bne.n	8009892 <HAL_RCCEx_GetPeriphCLKFreq+0x516>
+        {
+          /* In Case the CKPER Source is HSE */
+          frequency = HSE_VALUE;
+ 800988c:	4b07      	ldr	r3, [pc, #28]	; (80098ac <HAL_RCCEx_GetPeriphCLKFreq+0x530>)
+ 800988e:	63fb      	str	r3, [r7, #60]	; 0x3c
+ 8009890:	e002      	b.n	8009898 <HAL_RCCEx_GetPeriphCLKFreq+0x51c>
+        }
+
+        else
+        {
+          /* In Case the CKPER is disabled*/
+          frequency = 0;
+ 8009892:	2300      	movs	r3, #0
+ 8009894:	63fb      	str	r3, [r7, #60]	; 0x3c
+        }
+
+        break;
+ 8009896:	e236      	b.n	8009d06 <HAL_RCCEx_GetPeriphCLKFreq+0x98a>
+ 8009898:	e235      	b.n	8009d06 <HAL_RCCEx_GetPeriphCLKFreq+0x98a>
+      }
+
+      case (RCC_SPI123CLKSOURCE_PIN): /* External clock is the clock source for I2S */
+      {
+        frequency = EXTERNAL_CLOCK_VALUE;
+ 800989a:	4b05      	ldr	r3, [pc, #20]	; (80098b0 <HAL_RCCEx_GetPeriphCLKFreq+0x534>)
+ 800989c:	63fb      	str	r3, [r7, #60]	; 0x3c
+        break;
+ 800989e:	e232      	b.n	8009d06 <HAL_RCCEx_GetPeriphCLKFreq+0x98a>
+ 80098a0:	58024400 	.word	0x58024400
+ 80098a4:	03d09000 	.word	0x03d09000
+ 80098a8:	003d0900 	.word	0x003d0900
+ 80098ac:	017d7840 	.word	0x017d7840
+ 80098b0:	00bb8000 	.word	0x00bb8000
+      }
+      default :
+      {
+        frequency = 0;
+ 80098b4:	2300      	movs	r3, #0
+ 80098b6:	63fb      	str	r3, [r7, #60]	; 0x3c
+        break;
+ 80098b8:	e225      	b.n	8009d06 <HAL_RCCEx_GetPeriphCLKFreq+0x98a>
+      }
+    }
+  }
+  else if (PeriphClk == RCC_PERIPHCLK_SPI45)
+ 80098ba:	e9d7 2300 	ldrd	r2, r3, [r7]
+ 80098be:	f5a2 5100 	sub.w	r1, r2, #8192	; 0x2000
+ 80098c2:	430b      	orrs	r3, r1
+ 80098c4:	f040 8085 	bne.w	80099d2 <HAL_RCCEx_GetPeriphCLKFreq+0x656>
+  {
+    /* Get SPI45 clock source */
+    srcclk = __HAL_RCC_GET_SPI45_SOURCE();
+ 80098c8:	4b9c      	ldr	r3, [pc, #624]	; (8009b3c <HAL_RCCEx_GetPeriphCLKFreq+0x7c0>)
+ 80098ca:	6d1b      	ldr	r3, [r3, #80]	; 0x50
+ 80098cc:	f403 23e0 	and.w	r3, r3, #458752	; 0x70000
+ 80098d0:	63bb      	str	r3, [r7, #56]	; 0x38
+    switch (srcclk)
+ 80098d2:	6bbb      	ldr	r3, [r7, #56]	; 0x38
+ 80098d4:	f5b3 2fa0 	cmp.w	r3, #327680	; 0x50000
+ 80098d8:	d06b      	beq.n	80099b2 <HAL_RCCEx_GetPeriphCLKFreq+0x636>
+ 80098da:	6bbb      	ldr	r3, [r7, #56]	; 0x38
+ 80098dc:	f5b3 2fa0 	cmp.w	r3, #327680	; 0x50000
+ 80098e0:	d874      	bhi.n	80099cc <HAL_RCCEx_GetPeriphCLKFreq+0x650>
+ 80098e2:	6bbb      	ldr	r3, [r7, #56]	; 0x38
+ 80098e4:	f5b3 2f80 	cmp.w	r3, #262144	; 0x40000
+ 80098e8:	d056      	beq.n	8009998 <HAL_RCCEx_GetPeriphCLKFreq+0x61c>
+ 80098ea:	6bbb      	ldr	r3, [r7, #56]	; 0x38
+ 80098ec:	f5b3 2f80 	cmp.w	r3, #262144	; 0x40000
+ 80098f0:	d86c      	bhi.n	80099cc <HAL_RCCEx_GetPeriphCLKFreq+0x650>
+ 80098f2:	6bbb      	ldr	r3, [r7, #56]	; 0x38
+ 80098f4:	f5b3 3f40 	cmp.w	r3, #196608	; 0x30000
+ 80098f8:	d03b      	beq.n	8009972 <HAL_RCCEx_GetPeriphCLKFreq+0x5f6>
+ 80098fa:	6bbb      	ldr	r3, [r7, #56]	; 0x38
+ 80098fc:	f5b3 3f40 	cmp.w	r3, #196608	; 0x30000
+ 8009900:	d864      	bhi.n	80099cc <HAL_RCCEx_GetPeriphCLKFreq+0x650>
+ 8009902:	6bbb      	ldr	r3, [r7, #56]	; 0x38
+ 8009904:	f5b3 3f00 	cmp.w	r3, #131072	; 0x20000
+ 8009908:	d021      	beq.n	800994e <HAL_RCCEx_GetPeriphCLKFreq+0x5d2>
+ 800990a:	6bbb      	ldr	r3, [r7, #56]	; 0x38
+ 800990c:	f5b3 3f00 	cmp.w	r3, #131072	; 0x20000
+ 8009910:	d85c      	bhi.n	80099cc <HAL_RCCEx_GetPeriphCLKFreq+0x650>
+ 8009912:	6bbb      	ldr	r3, [r7, #56]	; 0x38
+ 8009914:	2b00      	cmp	r3, #0
+ 8009916:	d004      	beq.n	8009922 <HAL_RCCEx_GetPeriphCLKFreq+0x5a6>
+ 8009918:	6bbb      	ldr	r3, [r7, #56]	; 0x38
+ 800991a:	f5b3 3f80 	cmp.w	r3, #65536	; 0x10000
+ 800991e:	d004      	beq.n	800992a <HAL_RCCEx_GetPeriphCLKFreq+0x5ae>
+ 8009920:	e054      	b.n	80099cc <HAL_RCCEx_GetPeriphCLKFreq+0x650>
+    {
+      case RCC_SPI45CLKSOURCE_PCLK2: /* CD/D2 PCLK2 is the clock source for SPI4/5 */
+      {
+        frequency = HAL_RCC_GetPCLK1Freq();
+ 8009922:	f7fe fb1d 	bl	8007f60 <HAL_RCC_GetPCLK1Freq>
+ 8009926:	63f8      	str	r0, [r7, #60]	; 0x3c
+        break;
+ 8009928:	e1ed      	b.n	8009d06 <HAL_RCCEx_GetPeriphCLKFreq+0x98a>
+      }
+      case RCC_SPI45CLKSOURCE_PLL2: /* PLL2 is the clock source for SPI45 */
+      {
+        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY))
+ 800992a:	4b84      	ldr	r3, [pc, #528]	; (8009b3c <HAL_RCCEx_GetPeriphCLKFreq+0x7c0>)
+ 800992c:	681b      	ldr	r3, [r3, #0]
+ 800992e:	f003 6300 	and.w	r3, r3, #134217728	; 0x8000000
+ 8009932:	f1b3 6f00 	cmp.w	r3, #134217728	; 0x8000000
+ 8009936:	d107      	bne.n	8009948 <HAL_RCCEx_GetPeriphCLKFreq+0x5cc>
+        {
+          HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
+ 8009938:	f107 0318 	add.w	r3, r7, #24
+ 800993c:	4618      	mov	r0, r3
+ 800993e:	f000 fa05 	bl	8009d4c <HAL_RCCEx_GetPLL2ClockFreq>
+          frequency = pll2_clocks.PLL2_Q_Frequency;
+ 8009942:	69fb      	ldr	r3, [r7, #28]
+ 8009944:	63fb      	str	r3, [r7, #60]	; 0x3c
+        }
+        else
+        {
+          frequency = 0;
+        }
+        break;
+ 8009946:	e1de      	b.n	8009d06 <HAL_RCCEx_GetPeriphCLKFreq+0x98a>
+          frequency = 0;
+ 8009948:	2300      	movs	r3, #0
+ 800994a:	63fb      	str	r3, [r7, #60]	; 0x3c
+        break;
+ 800994c:	e1db      	b.n	8009d06 <HAL_RCCEx_GetPeriphCLKFreq+0x98a>
+      }
+      case RCC_SPI45CLKSOURCE_PLL3: /* PLL3 is the clock source for SPI45 */
+      {
+        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY))
+ 800994e:	4b7b      	ldr	r3, [pc, #492]	; (8009b3c <HAL_RCCEx_GetPeriphCLKFreq+0x7c0>)
+ 8009950:	681b      	ldr	r3, [r3, #0]
+ 8009952:	f003 5300 	and.w	r3, r3, #536870912	; 0x20000000
+ 8009956:	f1b3 5f00 	cmp.w	r3, #536870912	; 0x20000000
+ 800995a:	d107      	bne.n	800996c <HAL_RCCEx_GetPeriphCLKFreq+0x5f0>
+        {
+          HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
+ 800995c:	f107 030c 	add.w	r3, r7, #12
+ 8009960:	4618      	mov	r0, r3
+ 8009962:	f000 fb47 	bl	8009ff4 <HAL_RCCEx_GetPLL3ClockFreq>
+          frequency = pll3_clocks.PLL3_Q_Frequency;
+ 8009966:	693b      	ldr	r3, [r7, #16]
+ 8009968:	63fb      	str	r3, [r7, #60]	; 0x3c
+        }
+        else
+        {
+          frequency = 0;
+        }
+        break;
+ 800996a:	e1cc      	b.n	8009d06 <HAL_RCCEx_GetPeriphCLKFreq+0x98a>
+          frequency = 0;
+ 800996c:	2300      	movs	r3, #0
+ 800996e:	63fb      	str	r3, [r7, #60]	; 0x3c
+        break;
+ 8009970:	e1c9      	b.n	8009d06 <HAL_RCCEx_GetPeriphCLKFreq+0x98a>
+      }
+      case RCC_SPI45CLKSOURCE_HSI: /* HSI is the clock source for SPI45 */
+      {
+        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
+ 8009972:	4b72      	ldr	r3, [pc, #456]	; (8009b3c <HAL_RCCEx_GetPeriphCLKFreq+0x7c0>)
+ 8009974:	681b      	ldr	r3, [r3, #0]
+ 8009976:	f003 0304 	and.w	r3, r3, #4
+ 800997a:	2b04      	cmp	r3, #4
+ 800997c:	d109      	bne.n	8009992 <HAL_RCCEx_GetPeriphCLKFreq+0x616>
+        {
+          frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
+ 800997e:	4b6f      	ldr	r3, [pc, #444]	; (8009b3c <HAL_RCCEx_GetPeriphCLKFreq+0x7c0>)
+ 8009980:	681b      	ldr	r3, [r3, #0]
+ 8009982:	08db      	lsrs	r3, r3, #3
+ 8009984:	f003 0303 	and.w	r3, r3, #3
+ 8009988:	4a6d      	ldr	r2, [pc, #436]	; (8009b40 <HAL_RCCEx_GetPeriphCLKFreq+0x7c4>)
+ 800998a:	fa22 f303 	lsr.w	r3, r2, r3
+ 800998e:	63fb      	str	r3, [r7, #60]	; 0x3c
+        }
+        else
+        {
+          frequency = 0;
+        }
+        break;
+ 8009990:	e1b9      	b.n	8009d06 <HAL_RCCEx_GetPeriphCLKFreq+0x98a>
+          frequency = 0;
+ 8009992:	2300      	movs	r3, #0
+ 8009994:	63fb      	str	r3, [r7, #60]	; 0x3c
+        break;
+ 8009996:	e1b6      	b.n	8009d06 <HAL_RCCEx_GetPeriphCLKFreq+0x98a>
+      }
+      case RCC_SPI45CLKSOURCE_CSI: /* CSI is the clock source for SPI45 */
+      {
+        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY))
+ 8009998:	4b68      	ldr	r3, [pc, #416]	; (8009b3c <HAL_RCCEx_GetPeriphCLKFreq+0x7c0>)
+ 800999a:	681b      	ldr	r3, [r3, #0]
+ 800999c:	f403 7380 	and.w	r3, r3, #256	; 0x100
+ 80099a0:	f5b3 7f80 	cmp.w	r3, #256	; 0x100
+ 80099a4:	d102      	bne.n	80099ac <HAL_RCCEx_GetPeriphCLKFreq+0x630>
+        {
+          frequency = CSI_VALUE;
+ 80099a6:	4b67      	ldr	r3, [pc, #412]	; (8009b44 <HAL_RCCEx_GetPeriphCLKFreq+0x7c8>)
+ 80099a8:	63fb      	str	r3, [r7, #60]	; 0x3c
+        }
+        else
+        {
+          frequency = 0;
+        }
+        break;
+ 80099aa:	e1ac      	b.n	8009d06 <HAL_RCCEx_GetPeriphCLKFreq+0x98a>
+          frequency = 0;
+ 80099ac:	2300      	movs	r3, #0
+ 80099ae:	63fb      	str	r3, [r7, #60]	; 0x3c
+        break;
+ 80099b0:	e1a9      	b.n	8009d06 <HAL_RCCEx_GetPeriphCLKFreq+0x98a>
+      }
+      case RCC_SPI45CLKSOURCE_HSE: /* HSE is the clock source for SPI45 */
+      {
+        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))
+ 80099b2:	4b62      	ldr	r3, [pc, #392]	; (8009b3c <HAL_RCCEx_GetPeriphCLKFreq+0x7c0>)
+ 80099b4:	681b      	ldr	r3, [r3, #0]
+ 80099b6:	f403 3300 	and.w	r3, r3, #131072	; 0x20000
+ 80099ba:	f5b3 3f00 	cmp.w	r3, #131072	; 0x20000
+ 80099be:	d102      	bne.n	80099c6 <HAL_RCCEx_GetPeriphCLKFreq+0x64a>
+        {
+          frequency = HSE_VALUE;
+ 80099c0:	4b61      	ldr	r3, [pc, #388]	; (8009b48 <HAL_RCCEx_GetPeriphCLKFreq+0x7cc>)
+ 80099c2:	63fb      	str	r3, [r7, #60]	; 0x3c
+        }
+        else
+        {
+          frequency = 0;
+        }
+        break;
+ 80099c4:	e19f      	b.n	8009d06 <HAL_RCCEx_GetPeriphCLKFreq+0x98a>
+          frequency = 0;
+ 80099c6:	2300      	movs	r3, #0
+ 80099c8:	63fb      	str	r3, [r7, #60]	; 0x3c
+        break;
+ 80099ca:	e19c      	b.n	8009d06 <HAL_RCCEx_GetPeriphCLKFreq+0x98a>
+      }
+      default :
+      {
+        frequency = 0;
+ 80099cc:	2300      	movs	r3, #0
+ 80099ce:	63fb      	str	r3, [r7, #60]	; 0x3c
+        break;
+ 80099d0:	e199      	b.n	8009d06 <HAL_RCCEx_GetPeriphCLKFreq+0x98a>
+      }
+    }
+  }
+  else if (PeriphClk == RCC_PERIPHCLK_ADC)
+ 80099d2:	e9d7 2300 	ldrd	r2, r3, [r7]
+ 80099d6:	f5a2 2100 	sub.w	r1, r2, #524288	; 0x80000
+ 80099da:	430b      	orrs	r3, r1
+ 80099dc:	d173      	bne.n	8009ac6 <HAL_RCCEx_GetPeriphCLKFreq+0x74a>
+  {
+    /* Get ADC clock source */
+    srcclk = __HAL_RCC_GET_ADC_SOURCE();
+ 80099de:	4b57      	ldr	r3, [pc, #348]	; (8009b3c <HAL_RCCEx_GetPeriphCLKFreq+0x7c0>)
+ 80099e0:	6d9b      	ldr	r3, [r3, #88]	; 0x58
+ 80099e2:	f403 3340 	and.w	r3, r3, #196608	; 0x30000
+ 80099e6:	63bb      	str	r3, [r7, #56]	; 0x38
+
+    switch (srcclk)
+ 80099e8:	6bbb      	ldr	r3, [r7, #56]	; 0x38
+ 80099ea:	f5b3 3f00 	cmp.w	r3, #131072	; 0x20000
+ 80099ee:	d02f      	beq.n	8009a50 <HAL_RCCEx_GetPeriphCLKFreq+0x6d4>
+ 80099f0:	6bbb      	ldr	r3, [r7, #56]	; 0x38
+ 80099f2:	f5b3 3f00 	cmp.w	r3, #131072	; 0x20000
+ 80099f6:	d863      	bhi.n	8009ac0 <HAL_RCCEx_GetPeriphCLKFreq+0x744>
+ 80099f8:	6bbb      	ldr	r3, [r7, #56]	; 0x38
+ 80099fa:	2b00      	cmp	r3, #0
+ 80099fc:	d004      	beq.n	8009a08 <HAL_RCCEx_GetPeriphCLKFreq+0x68c>
+ 80099fe:	6bbb      	ldr	r3, [r7, #56]	; 0x38
+ 8009a00:	f5b3 3f80 	cmp.w	r3, #65536	; 0x10000
+ 8009a04:	d012      	beq.n	8009a2c <HAL_RCCEx_GetPeriphCLKFreq+0x6b0>
+ 8009a06:	e05b      	b.n	8009ac0 <HAL_RCCEx_GetPeriphCLKFreq+0x744>
+    {
+      case RCC_ADCCLKSOURCE_PLL2:
+      {
+        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY))
+ 8009a08:	4b4c      	ldr	r3, [pc, #304]	; (8009b3c <HAL_RCCEx_GetPeriphCLKFreq+0x7c0>)
+ 8009a0a:	681b      	ldr	r3, [r3, #0]
+ 8009a0c:	f003 6300 	and.w	r3, r3, #134217728	; 0x8000000
+ 8009a10:	f1b3 6f00 	cmp.w	r3, #134217728	; 0x8000000
+ 8009a14:	d107      	bne.n	8009a26 <HAL_RCCEx_GetPeriphCLKFreq+0x6aa>
+        {
+          HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
+ 8009a16:	f107 0318 	add.w	r3, r7, #24
+ 8009a1a:	4618      	mov	r0, r3
+ 8009a1c:	f000 f996 	bl	8009d4c <HAL_RCCEx_GetPLL2ClockFreq>
+          frequency = pll2_clocks.PLL2_P_Frequency;
+ 8009a20:	69bb      	ldr	r3, [r7, #24]
+ 8009a22:	63fb      	str	r3, [r7, #60]	; 0x3c
+        }
+        else
+        {
+          frequency = 0;
+        }
+        break;
+ 8009a24:	e16f      	b.n	8009d06 <HAL_RCCEx_GetPeriphCLKFreq+0x98a>
+          frequency = 0;
+ 8009a26:	2300      	movs	r3, #0
+ 8009a28:	63fb      	str	r3, [r7, #60]	; 0x3c
+        break;
+ 8009a2a:	e16c      	b.n	8009d06 <HAL_RCCEx_GetPeriphCLKFreq+0x98a>
+      }
+      case RCC_ADCCLKSOURCE_PLL3:
+      {
+        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY))
+ 8009a2c:	4b43      	ldr	r3, [pc, #268]	; (8009b3c <HAL_RCCEx_GetPeriphCLKFreq+0x7c0>)
+ 8009a2e:	681b      	ldr	r3, [r3, #0]
+ 8009a30:	f003 5300 	and.w	r3, r3, #536870912	; 0x20000000
+ 8009a34:	f1b3 5f00 	cmp.w	r3, #536870912	; 0x20000000
+ 8009a38:	d107      	bne.n	8009a4a <HAL_RCCEx_GetPeriphCLKFreq+0x6ce>
+        {
+          HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
+ 8009a3a:	f107 030c 	add.w	r3, r7, #12
+ 8009a3e:	4618      	mov	r0, r3
+ 8009a40:	f000 fad8 	bl	8009ff4 <HAL_RCCEx_GetPLL3ClockFreq>
+          frequency = pll3_clocks.PLL3_R_Frequency;
+ 8009a44:	697b      	ldr	r3, [r7, #20]
+ 8009a46:	63fb      	str	r3, [r7, #60]	; 0x3c
+        }
+        else
+        {
+          frequency = 0;
+        }
+        break;
+ 8009a48:	e15d      	b.n	8009d06 <HAL_RCCEx_GetPeriphCLKFreq+0x98a>
+          frequency = 0;
+ 8009a4a:	2300      	movs	r3, #0
+ 8009a4c:	63fb      	str	r3, [r7, #60]	; 0x3c
+        break;
+ 8009a4e:	e15a      	b.n	8009d06 <HAL_RCCEx_GetPeriphCLKFreq+0x98a>
+      }
+
+      case RCC_ADCCLKSOURCE_CLKP:
+      {
+
+        ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE();
+ 8009a50:	4b3a      	ldr	r3, [pc, #232]	; (8009b3c <HAL_RCCEx_GetPeriphCLKFreq+0x7c0>)
+ 8009a52:	6cdb      	ldr	r3, [r3, #76]	; 0x4c
+ 8009a54:	f003 5340 	and.w	r3, r3, #805306368	; 0x30000000
+ 8009a58:	637b      	str	r3, [r7, #52]	; 0x34
+
+        if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI))
+ 8009a5a:	4b38      	ldr	r3, [pc, #224]	; (8009b3c <HAL_RCCEx_GetPeriphCLKFreq+0x7c0>)
+ 8009a5c:	681b      	ldr	r3, [r3, #0]
+ 8009a5e:	f003 0304 	and.w	r3, r3, #4
+ 8009a62:	2b04      	cmp	r3, #4
+ 8009a64:	d10c      	bne.n	8009a80 <HAL_RCCEx_GetPeriphCLKFreq+0x704>
+ 8009a66:	6b7b      	ldr	r3, [r7, #52]	; 0x34
+ 8009a68:	2b00      	cmp	r3, #0
+ 8009a6a:	d109      	bne.n	8009a80 <HAL_RCCEx_GetPeriphCLKFreq+0x704>
+        {
+          /* In Case the CKPER Source is HSI */
+          frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
+ 8009a6c:	4b33      	ldr	r3, [pc, #204]	; (8009b3c <HAL_RCCEx_GetPeriphCLKFreq+0x7c0>)
+ 8009a6e:	681b      	ldr	r3, [r3, #0]
+ 8009a70:	08db      	lsrs	r3, r3, #3
+ 8009a72:	f003 0303 	and.w	r3, r3, #3
+ 8009a76:	4a32      	ldr	r2, [pc, #200]	; (8009b40 <HAL_RCCEx_GetPeriphCLKFreq+0x7c4>)
+ 8009a78:	fa22 f303 	lsr.w	r3, r2, r3
+ 8009a7c:	63fb      	str	r3, [r7, #60]	; 0x3c
+ 8009a7e:	e01e      	b.n	8009abe <HAL_RCCEx_GetPeriphCLKFreq+0x742>
+        }
+
+        else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI))
+ 8009a80:	4b2e      	ldr	r3, [pc, #184]	; (8009b3c <HAL_RCCEx_GetPeriphCLKFreq+0x7c0>)
+ 8009a82:	681b      	ldr	r3, [r3, #0]
+ 8009a84:	f403 7380 	and.w	r3, r3, #256	; 0x100
+ 8009a88:	f5b3 7f80 	cmp.w	r3, #256	; 0x100
+ 8009a8c:	d106      	bne.n	8009a9c <HAL_RCCEx_GetPeriphCLKFreq+0x720>
+ 8009a8e:	6b7b      	ldr	r3, [r7, #52]	; 0x34
+ 8009a90:	f1b3 5f80 	cmp.w	r3, #268435456	; 0x10000000
+ 8009a94:	d102      	bne.n	8009a9c <HAL_RCCEx_GetPeriphCLKFreq+0x720>
+        {
+          /* In Case the CKPER Source is CSI */
+          frequency = CSI_VALUE;
+ 8009a96:	4b2b      	ldr	r3, [pc, #172]	; (8009b44 <HAL_RCCEx_GetPeriphCLKFreq+0x7c8>)
+ 8009a98:	63fb      	str	r3, [r7, #60]	; 0x3c
+ 8009a9a:	e010      	b.n	8009abe <HAL_RCCEx_GetPeriphCLKFreq+0x742>
+        }
+
+        else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE))
+ 8009a9c:	4b27      	ldr	r3, [pc, #156]	; (8009b3c <HAL_RCCEx_GetPeriphCLKFreq+0x7c0>)
+ 8009a9e:	681b      	ldr	r3, [r3, #0]
+ 8009aa0:	f403 3300 	and.w	r3, r3, #131072	; 0x20000
+ 8009aa4:	f5b3 3f00 	cmp.w	r3, #131072	; 0x20000
+ 8009aa8:	d106      	bne.n	8009ab8 <HAL_RCCEx_GetPeriphCLKFreq+0x73c>
+ 8009aaa:	6b7b      	ldr	r3, [r7, #52]	; 0x34
+ 8009aac:	f1b3 5f00 	cmp.w	r3, #536870912	; 0x20000000
+ 8009ab0:	d102      	bne.n	8009ab8 <HAL_RCCEx_GetPeriphCLKFreq+0x73c>
+        {
+          /* In Case the CKPER Source is HSE */
+          frequency = HSE_VALUE;
+ 8009ab2:	4b25      	ldr	r3, [pc, #148]	; (8009b48 <HAL_RCCEx_GetPeriphCLKFreq+0x7cc>)
+ 8009ab4:	63fb      	str	r3, [r7, #60]	; 0x3c
+ 8009ab6:	e002      	b.n	8009abe <HAL_RCCEx_GetPeriphCLKFreq+0x742>
+        }
+
+        else
+        {
+          /* In Case the CKPER is disabled*/
+          frequency = 0;
+ 8009ab8:	2300      	movs	r3, #0
+ 8009aba:	63fb      	str	r3, [r7, #60]	; 0x3c
+        }
+
+        break;
+ 8009abc:	e123      	b.n	8009d06 <HAL_RCCEx_GetPeriphCLKFreq+0x98a>
+ 8009abe:	e122      	b.n	8009d06 <HAL_RCCEx_GetPeriphCLKFreq+0x98a>
+      }
+
+      default :
+      {
+        frequency = 0;
+ 8009ac0:	2300      	movs	r3, #0
+ 8009ac2:	63fb      	str	r3, [r7, #60]	; 0x3c
+        break;
+ 8009ac4:	e11f      	b.n	8009d06 <HAL_RCCEx_GetPeriphCLKFreq+0x98a>
+      }
+    }
+  }
+  else if (PeriphClk == RCC_PERIPHCLK_SDMMC)
+ 8009ac6:	e9d7 2300 	ldrd	r2, r3, [r7]
+ 8009aca:	f5a2 3180 	sub.w	r1, r2, #65536	; 0x10000
+ 8009ace:	430b      	orrs	r3, r1
+ 8009ad0:	d13c      	bne.n	8009b4c <HAL_RCCEx_GetPeriphCLKFreq+0x7d0>
+  {
+    /* Get SDMMC clock source */
+    srcclk = __HAL_RCC_GET_SDMMC_SOURCE();
+ 8009ad2:	4b1a      	ldr	r3, [pc, #104]	; (8009b3c <HAL_RCCEx_GetPeriphCLKFreq+0x7c0>)
+ 8009ad4:	6cdb      	ldr	r3, [r3, #76]	; 0x4c
+ 8009ad6:	f403 3380 	and.w	r3, r3, #65536	; 0x10000
+ 8009ada:	63bb      	str	r3, [r7, #56]	; 0x38
+
+    switch (srcclk)
+ 8009adc:	6bbb      	ldr	r3, [r7, #56]	; 0x38
+ 8009ade:	2b00      	cmp	r3, #0
+ 8009ae0:	d004      	beq.n	8009aec <HAL_RCCEx_GetPeriphCLKFreq+0x770>
+ 8009ae2:	6bbb      	ldr	r3, [r7, #56]	; 0x38
+ 8009ae4:	f5b3 3f80 	cmp.w	r3, #65536	; 0x10000
+ 8009ae8:	d012      	beq.n	8009b10 <HAL_RCCEx_GetPeriphCLKFreq+0x794>
+ 8009aea:	e023      	b.n	8009b34 <HAL_RCCEx_GetPeriphCLKFreq+0x7b8>
+    {
+      case RCC_SDMMCCLKSOURCE_PLL: /* PLL1 is the clock source for SDMMC */
+      {
+        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY))
+ 8009aec:	4b13      	ldr	r3, [pc, #76]	; (8009b3c <HAL_RCCEx_GetPeriphCLKFreq+0x7c0>)
+ 8009aee:	681b      	ldr	r3, [r3, #0]
+ 8009af0:	f003 7300 	and.w	r3, r3, #33554432	; 0x2000000
+ 8009af4:	f1b3 7f00 	cmp.w	r3, #33554432	; 0x2000000
+ 8009af8:	d107      	bne.n	8009b0a <HAL_RCCEx_GetPeriphCLKFreq+0x78e>
+        {
+          HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
+ 8009afa:	f107 0324 	add.w	r3, r7, #36	; 0x24
+ 8009afe:	4618      	mov	r0, r3
+ 8009b00:	f000 fbcc 	bl	800a29c <HAL_RCCEx_GetPLL1ClockFreq>
+          frequency = pll1_clocks.PLL1_Q_Frequency;
+ 8009b04:	6abb      	ldr	r3, [r7, #40]	; 0x28
+ 8009b06:	63fb      	str	r3, [r7, #60]	; 0x3c
+        }
+        else
+        {
+          frequency = 0;
+        }
+        break;
+ 8009b08:	e0fd      	b.n	8009d06 <HAL_RCCEx_GetPeriphCLKFreq+0x98a>
+          frequency = 0;
+ 8009b0a:	2300      	movs	r3, #0
+ 8009b0c:	63fb      	str	r3, [r7, #60]	; 0x3c
+        break;
+ 8009b0e:	e0fa      	b.n	8009d06 <HAL_RCCEx_GetPeriphCLKFreq+0x98a>
+      }
+      case RCC_SDMMCCLKSOURCE_PLL2: /* PLL2 is the clock source for SDMMC */
+      {
+        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY))
+ 8009b10:	4b0a      	ldr	r3, [pc, #40]	; (8009b3c <HAL_RCCEx_GetPeriphCLKFreq+0x7c0>)
+ 8009b12:	681b      	ldr	r3, [r3, #0]
+ 8009b14:	f003 6300 	and.w	r3, r3, #134217728	; 0x8000000
+ 8009b18:	f1b3 6f00 	cmp.w	r3, #134217728	; 0x8000000
+ 8009b1c:	d107      	bne.n	8009b2e <HAL_RCCEx_GetPeriphCLKFreq+0x7b2>
+        {
+          HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
+ 8009b1e:	f107 0318 	add.w	r3, r7, #24
+ 8009b22:	4618      	mov	r0, r3
+ 8009b24:	f000 f912 	bl	8009d4c <HAL_RCCEx_GetPLL2ClockFreq>
+          frequency = pll2_clocks.PLL2_R_Frequency;
+ 8009b28:	6a3b      	ldr	r3, [r7, #32]
+ 8009b2a:	63fb      	str	r3, [r7, #60]	; 0x3c
+        }
+        else
+        {
+          frequency = 0;
+        }
+        break;
+ 8009b2c:	e0eb      	b.n	8009d06 <HAL_RCCEx_GetPeriphCLKFreq+0x98a>
+          frequency = 0;
+ 8009b2e:	2300      	movs	r3, #0
+ 8009b30:	63fb      	str	r3, [r7, #60]	; 0x3c
+        break;
+ 8009b32:	e0e8      	b.n	8009d06 <HAL_RCCEx_GetPeriphCLKFreq+0x98a>
+      }
+
+      default :
+      {
+        frequency = 0;
+ 8009b34:	2300      	movs	r3, #0
+ 8009b36:	63fb      	str	r3, [r7, #60]	; 0x3c
+        break;
+ 8009b38:	e0e5      	b.n	8009d06 <HAL_RCCEx_GetPeriphCLKFreq+0x98a>
+ 8009b3a:	bf00      	nop
+ 8009b3c:	58024400 	.word	0x58024400
+ 8009b40:	03d09000 	.word	0x03d09000
+ 8009b44:	003d0900 	.word	0x003d0900
+ 8009b48:	017d7840 	.word	0x017d7840
+      }
+    }
+  }
+  else if (PeriphClk == RCC_PERIPHCLK_SPI6)
+ 8009b4c:	e9d7 2300 	ldrd	r2, r3, [r7]
+ 8009b50:	f5a2 4180 	sub.w	r1, r2, #16384	; 0x4000
+ 8009b54:	430b      	orrs	r3, r1
+ 8009b56:	f040 8085 	bne.w	8009c64 <HAL_RCCEx_GetPeriphCLKFreq+0x8e8>
+  {
+    /* Get SPI6 clock source */
+    srcclk = __HAL_RCC_GET_SPI6_SOURCE();
+ 8009b5a:	4b6d      	ldr	r3, [pc, #436]	; (8009d10 <HAL_RCCEx_GetPeriphCLKFreq+0x994>)
+ 8009b5c:	6d9b      	ldr	r3, [r3, #88]	; 0x58
+ 8009b5e:	f003 43e0 	and.w	r3, r3, #1879048192	; 0x70000000
+ 8009b62:	63bb      	str	r3, [r7, #56]	; 0x38
+
+    switch (srcclk)
+ 8009b64:	6bbb      	ldr	r3, [r7, #56]	; 0x38
+ 8009b66:	f1b3 4fa0 	cmp.w	r3, #1342177280	; 0x50000000
+ 8009b6a:	d06b      	beq.n	8009c44 <HAL_RCCEx_GetPeriphCLKFreq+0x8c8>
+ 8009b6c:	6bbb      	ldr	r3, [r7, #56]	; 0x38
+ 8009b6e:	f1b3 4fa0 	cmp.w	r3, #1342177280	; 0x50000000
+ 8009b72:	d874      	bhi.n	8009c5e <HAL_RCCEx_GetPeriphCLKFreq+0x8e2>
+ 8009b74:	6bbb      	ldr	r3, [r7, #56]	; 0x38
+ 8009b76:	f1b3 4f80 	cmp.w	r3, #1073741824	; 0x40000000
+ 8009b7a:	d056      	beq.n	8009c2a <HAL_RCCEx_GetPeriphCLKFreq+0x8ae>
+ 8009b7c:	6bbb      	ldr	r3, [r7, #56]	; 0x38
+ 8009b7e:	f1b3 4f80 	cmp.w	r3, #1073741824	; 0x40000000
+ 8009b82:	d86c      	bhi.n	8009c5e <HAL_RCCEx_GetPeriphCLKFreq+0x8e2>
+ 8009b84:	6bbb      	ldr	r3, [r7, #56]	; 0x38
+ 8009b86:	f1b3 5f40 	cmp.w	r3, #805306368	; 0x30000000
+ 8009b8a:	d03b      	beq.n	8009c04 <HAL_RCCEx_GetPeriphCLKFreq+0x888>
+ 8009b8c:	6bbb      	ldr	r3, [r7, #56]	; 0x38
+ 8009b8e:	f1b3 5f40 	cmp.w	r3, #805306368	; 0x30000000
+ 8009b92:	d864      	bhi.n	8009c5e <HAL_RCCEx_GetPeriphCLKFreq+0x8e2>
+ 8009b94:	6bbb      	ldr	r3, [r7, #56]	; 0x38
+ 8009b96:	f1b3 5f00 	cmp.w	r3, #536870912	; 0x20000000
+ 8009b9a:	d021      	beq.n	8009be0 <HAL_RCCEx_GetPeriphCLKFreq+0x864>
+ 8009b9c:	6bbb      	ldr	r3, [r7, #56]	; 0x38
+ 8009b9e:	f1b3 5f00 	cmp.w	r3, #536870912	; 0x20000000
+ 8009ba2:	d85c      	bhi.n	8009c5e <HAL_RCCEx_GetPeriphCLKFreq+0x8e2>
+ 8009ba4:	6bbb      	ldr	r3, [r7, #56]	; 0x38
+ 8009ba6:	2b00      	cmp	r3, #0
+ 8009ba8:	d004      	beq.n	8009bb4 <HAL_RCCEx_GetPeriphCLKFreq+0x838>
+ 8009baa:	6bbb      	ldr	r3, [r7, #56]	; 0x38
+ 8009bac:	f1b3 5f80 	cmp.w	r3, #268435456	; 0x10000000
+ 8009bb0:	d004      	beq.n	8009bbc <HAL_RCCEx_GetPeriphCLKFreq+0x840>
+ 8009bb2:	e054      	b.n	8009c5e <HAL_RCCEx_GetPeriphCLKFreq+0x8e2>
+    {
+      case RCC_SPI6CLKSOURCE_D3PCLK1: /* D3PCLK1 (PCLK4) is the clock source for SPI6 */
+      {
+        frequency = HAL_RCCEx_GetD3PCLK1Freq();
+ 8009bb4:	f000 f8b4 	bl	8009d20 <HAL_RCCEx_GetD3PCLK1Freq>
+ 8009bb8:	63f8      	str	r0, [r7, #60]	; 0x3c
+        break;
+ 8009bba:	e0a4      	b.n	8009d06 <HAL_RCCEx_GetPeriphCLKFreq+0x98a>
+      }
+      case RCC_SPI6CLKSOURCE_PLL2: /* PLL2 is the clock source for SPI6 */
+      {
+        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY))
+ 8009bbc:	4b54      	ldr	r3, [pc, #336]	; (8009d10 <HAL_RCCEx_GetPeriphCLKFreq+0x994>)
+ 8009bbe:	681b      	ldr	r3, [r3, #0]
+ 8009bc0:	f003 6300 	and.w	r3, r3, #134217728	; 0x8000000
+ 8009bc4:	f1b3 6f00 	cmp.w	r3, #134217728	; 0x8000000
+ 8009bc8:	d107      	bne.n	8009bda <HAL_RCCEx_GetPeriphCLKFreq+0x85e>
+        {
+          HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
+ 8009bca:	f107 0318 	add.w	r3, r7, #24
+ 8009bce:	4618      	mov	r0, r3
+ 8009bd0:	f000 f8bc 	bl	8009d4c <HAL_RCCEx_GetPLL2ClockFreq>
+          frequency = pll2_clocks.PLL2_Q_Frequency;
+ 8009bd4:	69fb      	ldr	r3, [r7, #28]
+ 8009bd6:	63fb      	str	r3, [r7, #60]	; 0x3c
+        }
+        else
+        {
+          frequency = 0;
+        }
+        break;
+ 8009bd8:	e095      	b.n	8009d06 <HAL_RCCEx_GetPeriphCLKFreq+0x98a>
+          frequency = 0;
+ 8009bda:	2300      	movs	r3, #0
+ 8009bdc:	63fb      	str	r3, [r7, #60]	; 0x3c
+        break;
+ 8009bde:	e092      	b.n	8009d06 <HAL_RCCEx_GetPeriphCLKFreq+0x98a>
+      }
+      case RCC_SPI6CLKSOURCE_PLL3: /* PLL3 is the clock source for SPI6 */
+      {
+        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY))
+ 8009be0:	4b4b      	ldr	r3, [pc, #300]	; (8009d10 <HAL_RCCEx_GetPeriphCLKFreq+0x994>)
+ 8009be2:	681b      	ldr	r3, [r3, #0]
+ 8009be4:	f003 5300 	and.w	r3, r3, #536870912	; 0x20000000
+ 8009be8:	f1b3 5f00 	cmp.w	r3, #536870912	; 0x20000000
+ 8009bec:	d107      	bne.n	8009bfe <HAL_RCCEx_GetPeriphCLKFreq+0x882>
+        {
+          HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
+ 8009bee:	f107 030c 	add.w	r3, r7, #12
+ 8009bf2:	4618      	mov	r0, r3
+ 8009bf4:	f000 f9fe 	bl	8009ff4 <HAL_RCCEx_GetPLL3ClockFreq>
+          frequency = pll3_clocks.PLL3_Q_Frequency;
+ 8009bf8:	693b      	ldr	r3, [r7, #16]
+ 8009bfa:	63fb      	str	r3, [r7, #60]	; 0x3c
+        }
+        else
+        {
+          frequency = 0;
+        }
+        break;
+ 8009bfc:	e083      	b.n	8009d06 <HAL_RCCEx_GetPeriphCLKFreq+0x98a>
+          frequency = 0;
+ 8009bfe:	2300      	movs	r3, #0
+ 8009c00:	63fb      	str	r3, [r7, #60]	; 0x3c
+        break;
+ 8009c02:	e080      	b.n	8009d06 <HAL_RCCEx_GetPeriphCLKFreq+0x98a>
+      }
+      case RCC_SPI6CLKSOURCE_HSI: /* HSI is the clock source for SPI6 */
+      {
+        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
+ 8009c04:	4b42      	ldr	r3, [pc, #264]	; (8009d10 <HAL_RCCEx_GetPeriphCLKFreq+0x994>)
+ 8009c06:	681b      	ldr	r3, [r3, #0]
+ 8009c08:	f003 0304 	and.w	r3, r3, #4
+ 8009c0c:	2b04      	cmp	r3, #4
+ 8009c0e:	d109      	bne.n	8009c24 <HAL_RCCEx_GetPeriphCLKFreq+0x8a8>
+        {
+          frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
+ 8009c10:	4b3f      	ldr	r3, [pc, #252]	; (8009d10 <HAL_RCCEx_GetPeriphCLKFreq+0x994>)
+ 8009c12:	681b      	ldr	r3, [r3, #0]
+ 8009c14:	08db      	lsrs	r3, r3, #3
+ 8009c16:	f003 0303 	and.w	r3, r3, #3
+ 8009c1a:	4a3e      	ldr	r2, [pc, #248]	; (8009d14 <HAL_RCCEx_GetPeriphCLKFreq+0x998>)
+ 8009c1c:	fa22 f303 	lsr.w	r3, r2, r3
+ 8009c20:	63fb      	str	r3, [r7, #60]	; 0x3c
+        }
+        else
+        {
+          frequency = 0;
+        }
+        break;
+ 8009c22:	e070      	b.n	8009d06 <HAL_RCCEx_GetPeriphCLKFreq+0x98a>
+          frequency = 0;
+ 8009c24:	2300      	movs	r3, #0
+ 8009c26:	63fb      	str	r3, [r7, #60]	; 0x3c
+        break;
+ 8009c28:	e06d      	b.n	8009d06 <HAL_RCCEx_GetPeriphCLKFreq+0x98a>
+      }
+      case RCC_SPI6CLKSOURCE_CSI: /* CSI is the clock source for SPI6 */
+      {
+        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY))
+ 8009c2a:	4b39      	ldr	r3, [pc, #228]	; (8009d10 <HAL_RCCEx_GetPeriphCLKFreq+0x994>)
+ 8009c2c:	681b      	ldr	r3, [r3, #0]
+ 8009c2e:	f403 7380 	and.w	r3, r3, #256	; 0x100
+ 8009c32:	f5b3 7f80 	cmp.w	r3, #256	; 0x100
+ 8009c36:	d102      	bne.n	8009c3e <HAL_RCCEx_GetPeriphCLKFreq+0x8c2>
+        {
+          frequency = CSI_VALUE;
+ 8009c38:	4b37      	ldr	r3, [pc, #220]	; (8009d18 <HAL_RCCEx_GetPeriphCLKFreq+0x99c>)
+ 8009c3a:	63fb      	str	r3, [r7, #60]	; 0x3c
+        }
+        else
+        {
+          frequency = 0;
+        }
+        break;
+ 8009c3c:	e063      	b.n	8009d06 <HAL_RCCEx_GetPeriphCLKFreq+0x98a>
+          frequency = 0;
+ 8009c3e:	2300      	movs	r3, #0
+ 8009c40:	63fb      	str	r3, [r7, #60]	; 0x3c
+        break;
+ 8009c42:	e060      	b.n	8009d06 <HAL_RCCEx_GetPeriphCLKFreq+0x98a>
+      }
+      case RCC_SPI6CLKSOURCE_HSE: /* HSE is the clock source for SPI6 */
+      {
+        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))
+ 8009c44:	4b32      	ldr	r3, [pc, #200]	; (8009d10 <HAL_RCCEx_GetPeriphCLKFreq+0x994>)
+ 8009c46:	681b      	ldr	r3, [r3, #0]
+ 8009c48:	f403 3300 	and.w	r3, r3, #131072	; 0x20000
+ 8009c4c:	f5b3 3f00 	cmp.w	r3, #131072	; 0x20000
+ 8009c50:	d102      	bne.n	8009c58 <HAL_RCCEx_GetPeriphCLKFreq+0x8dc>
+        {
+          frequency = HSE_VALUE;
+ 8009c52:	4b32      	ldr	r3, [pc, #200]	; (8009d1c <HAL_RCCEx_GetPeriphCLKFreq+0x9a0>)
+ 8009c54:	63fb      	str	r3, [r7, #60]	; 0x3c
+        }
+        else
+        {
+          frequency = 0;
+        }
+        break;
+ 8009c56:	e056      	b.n	8009d06 <HAL_RCCEx_GetPeriphCLKFreq+0x98a>
+          frequency = 0;
+ 8009c58:	2300      	movs	r3, #0
+ 8009c5a:	63fb      	str	r3, [r7, #60]	; 0x3c
+        break;
+ 8009c5c:	e053      	b.n	8009d06 <HAL_RCCEx_GetPeriphCLKFreq+0x98a>
+        break;
+      }
+#endif /* RCC_SPI6CLKSOURCE_PIN */
+      default :
+      {
+        frequency = 0;
+ 8009c5e:	2300      	movs	r3, #0
+ 8009c60:	63fb      	str	r3, [r7, #60]	; 0x3c
+        break;
+ 8009c62:	e050      	b.n	8009d06 <HAL_RCCEx_GetPeriphCLKFreq+0x98a>
+      }
+    }
+  }
+  else if (PeriphClk == RCC_PERIPHCLK_FDCAN)
+ 8009c64:	e9d7 2300 	ldrd	r2, r3, [r7]
+ 8009c68:	f5a2 4100 	sub.w	r1, r2, #32768	; 0x8000
+ 8009c6c:	430b      	orrs	r3, r1
+ 8009c6e:	d148      	bne.n	8009d02 <HAL_RCCEx_GetPeriphCLKFreq+0x986>
+  {
+    /* Get FDCAN clock source */
+    srcclk = __HAL_RCC_GET_FDCAN_SOURCE();
+ 8009c70:	4b27      	ldr	r3, [pc, #156]	; (8009d10 <HAL_RCCEx_GetPeriphCLKFreq+0x994>)
+ 8009c72:	6d1b      	ldr	r3, [r3, #80]	; 0x50
+ 8009c74:	f003 5340 	and.w	r3, r3, #805306368	; 0x30000000
+ 8009c78:	63bb      	str	r3, [r7, #56]	; 0x38
+
+    switch (srcclk)
+ 8009c7a:	6bbb      	ldr	r3, [r7, #56]	; 0x38
+ 8009c7c:	f1b3 5f00 	cmp.w	r3, #536870912	; 0x20000000
+ 8009c80:	d02a      	beq.n	8009cd8 <HAL_RCCEx_GetPeriphCLKFreq+0x95c>
+ 8009c82:	6bbb      	ldr	r3, [r7, #56]	; 0x38
+ 8009c84:	f1b3 5f00 	cmp.w	r3, #536870912	; 0x20000000
+ 8009c88:	d838      	bhi.n	8009cfc <HAL_RCCEx_GetPeriphCLKFreq+0x980>
+ 8009c8a:	6bbb      	ldr	r3, [r7, #56]	; 0x38
+ 8009c8c:	2b00      	cmp	r3, #0
+ 8009c8e:	d004      	beq.n	8009c9a <HAL_RCCEx_GetPeriphCLKFreq+0x91e>
+ 8009c90:	6bbb      	ldr	r3, [r7, #56]	; 0x38
+ 8009c92:	f1b3 5f80 	cmp.w	r3, #268435456	; 0x10000000
+ 8009c96:	d00d      	beq.n	8009cb4 <HAL_RCCEx_GetPeriphCLKFreq+0x938>
+ 8009c98:	e030      	b.n	8009cfc <HAL_RCCEx_GetPeriphCLKFreq+0x980>
+    {
+      case RCC_FDCANCLKSOURCE_HSE: /* HSE is the clock source for FDCAN */
+      {
+        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))
+ 8009c9a:	4b1d      	ldr	r3, [pc, #116]	; (8009d10 <HAL_RCCEx_GetPeriphCLKFreq+0x994>)
+ 8009c9c:	681b      	ldr	r3, [r3, #0]
+ 8009c9e:	f403 3300 	and.w	r3, r3, #131072	; 0x20000
+ 8009ca2:	f5b3 3f00 	cmp.w	r3, #131072	; 0x20000
+ 8009ca6:	d102      	bne.n	8009cae <HAL_RCCEx_GetPeriphCLKFreq+0x932>
+        {
+          frequency = HSE_VALUE;
+ 8009ca8:	4b1c      	ldr	r3, [pc, #112]	; (8009d1c <HAL_RCCEx_GetPeriphCLKFreq+0x9a0>)
+ 8009caa:	63fb      	str	r3, [r7, #60]	; 0x3c
+        }
+        else
+        {
+          frequency = 0;
+        }
+        break;
+ 8009cac:	e02b      	b.n	8009d06 <HAL_RCCEx_GetPeriphCLKFreq+0x98a>
+          frequency = 0;
+ 8009cae:	2300      	movs	r3, #0
+ 8009cb0:	63fb      	str	r3, [r7, #60]	; 0x3c
+        break;
+ 8009cb2:	e028      	b.n	8009d06 <HAL_RCCEx_GetPeriphCLKFreq+0x98a>
+      }
+      case RCC_FDCANCLKSOURCE_PLL: /* PLL is the clock source for FDCAN */
+      {
+        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY))
+ 8009cb4:	4b16      	ldr	r3, [pc, #88]	; (8009d10 <HAL_RCCEx_GetPeriphCLKFreq+0x994>)
+ 8009cb6:	681b      	ldr	r3, [r3, #0]
+ 8009cb8:	f003 7300 	and.w	r3, r3, #33554432	; 0x2000000
+ 8009cbc:	f1b3 7f00 	cmp.w	r3, #33554432	; 0x2000000
+ 8009cc0:	d107      	bne.n	8009cd2 <HAL_RCCEx_GetPeriphCLKFreq+0x956>
+        {
+          HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
+ 8009cc2:	f107 0324 	add.w	r3, r7, #36	; 0x24
+ 8009cc6:	4618      	mov	r0, r3
+ 8009cc8:	f000 fae8 	bl	800a29c <HAL_RCCEx_GetPLL1ClockFreq>
+          frequency = pll1_clocks.PLL1_Q_Frequency;
+ 8009ccc:	6abb      	ldr	r3, [r7, #40]	; 0x28
+ 8009cce:	63fb      	str	r3, [r7, #60]	; 0x3c
+        }
+        else
+        {
+          frequency = 0;
+        }
+        break;
+ 8009cd0:	e019      	b.n	8009d06 <HAL_RCCEx_GetPeriphCLKFreq+0x98a>
+          frequency = 0;
+ 8009cd2:	2300      	movs	r3, #0
+ 8009cd4:	63fb      	str	r3, [r7, #60]	; 0x3c
+        break;
+ 8009cd6:	e016      	b.n	8009d06 <HAL_RCCEx_GetPeriphCLKFreq+0x98a>
+      }
+      case RCC_FDCANCLKSOURCE_PLL2: /* PLL2 is the clock source for FDCAN */
+      {
+        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY))
+ 8009cd8:	4b0d      	ldr	r3, [pc, #52]	; (8009d10 <HAL_RCCEx_GetPeriphCLKFreq+0x994>)
+ 8009cda:	681b      	ldr	r3, [r3, #0]
+ 8009cdc:	f003 6300 	and.w	r3, r3, #134217728	; 0x8000000
+ 8009ce0:	f1b3 6f00 	cmp.w	r3, #134217728	; 0x8000000
+ 8009ce4:	d107      	bne.n	8009cf6 <HAL_RCCEx_GetPeriphCLKFreq+0x97a>
+        {
+          HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
+ 8009ce6:	f107 0318 	add.w	r3, r7, #24
+ 8009cea:	4618      	mov	r0, r3
+ 8009cec:	f000 f82e 	bl	8009d4c <HAL_RCCEx_GetPLL2ClockFreq>
+          frequency = pll2_clocks.PLL2_Q_Frequency;
+ 8009cf0:	69fb      	ldr	r3, [r7, #28]
+ 8009cf2:	63fb      	str	r3, [r7, #60]	; 0x3c
+        }
+        else
+        {
+          frequency = 0;
+        }
+        break;
+ 8009cf4:	e007      	b.n	8009d06 <HAL_RCCEx_GetPeriphCLKFreq+0x98a>
+          frequency = 0;
+ 8009cf6:	2300      	movs	r3, #0
+ 8009cf8:	63fb      	str	r3, [r7, #60]	; 0x3c
+        break;
+ 8009cfa:	e004      	b.n	8009d06 <HAL_RCCEx_GetPeriphCLKFreq+0x98a>
+      }
+      default :
+      {
+        frequency = 0;
+ 8009cfc:	2300      	movs	r3, #0
+ 8009cfe:	63fb      	str	r3, [r7, #60]	; 0x3c
+        break;
+ 8009d00:	e001      	b.n	8009d06 <HAL_RCCEx_GetPeriphCLKFreq+0x98a>
+      }
+    }
+  }
+  else
+  {
+    frequency = 0;
+ 8009d02:	2300      	movs	r3, #0
+ 8009d04:	63fb      	str	r3, [r7, #60]	; 0x3c
+  }
+
+  return frequency;
+ 8009d06:	6bfb      	ldr	r3, [r7, #60]	; 0x3c
+}
+ 8009d08:	4618      	mov	r0, r3
+ 8009d0a:	3740      	adds	r7, #64	; 0x40
+ 8009d0c:	46bd      	mov	sp, r7
+ 8009d0e:	bd80      	pop	{r7, pc}
+ 8009d10:	58024400 	.word	0x58024400
+ 8009d14:	03d09000 	.word	0x03d09000
+ 8009d18:	003d0900 	.word	0x003d0900
+ 8009d1c:	017d7840 	.word	0x017d7840
+
+08009d20 <HAL_RCCEx_GetD3PCLK1Freq>:
+  * @note   Each time D3PCLK1 changes, this function must be called to update the
+  *         right D3PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
+  * @retval D3PCLK1 frequency
+  */
+uint32_t HAL_RCCEx_GetD3PCLK1Freq(void)
+{
+ 8009d20:	b580      	push	{r7, lr}
+ 8009d22:	af00      	add	r7, sp, #0
+#if defined(RCC_D3CFGR_D3PPRE)
+  /* Get HCLK source and Compute D3PCLK1 frequency ---------------------------*/
+  return (HAL_RCC_GetHCLKFreq() >> (D1CorePrescTable[(RCC->D3CFGR & RCC_D3CFGR_D3PPRE) >> RCC_D3CFGR_D3PPRE_Pos] & 0x1FU));
+ 8009d24:	f7fe f8ec 	bl	8007f00 <HAL_RCC_GetHCLKFreq>
+ 8009d28:	4602      	mov	r2, r0
+ 8009d2a:	4b06      	ldr	r3, [pc, #24]	; (8009d44 <HAL_RCCEx_GetD3PCLK1Freq+0x24>)
+ 8009d2c:	6a1b      	ldr	r3, [r3, #32]
+ 8009d2e:	091b      	lsrs	r3, r3, #4
+ 8009d30:	f003 0307 	and.w	r3, r3, #7
+ 8009d34:	4904      	ldr	r1, [pc, #16]	; (8009d48 <HAL_RCCEx_GetD3PCLK1Freq+0x28>)
+ 8009d36:	5ccb      	ldrb	r3, [r1, r3]
+ 8009d38:	f003 031f 	and.w	r3, r3, #31
+ 8009d3c:	fa22 f303 	lsr.w	r3, r2, r3
+#else
+  /* Get HCLK source and Compute D3PCLK1 frequency ---------------------------*/
+  return (HAL_RCC_GetHCLKFreq() >> (D1CorePrescTable[(RCC->SRDCFGR & RCC_SRDCFGR_SRDPPRE) >> RCC_SRDCFGR_SRDPPRE_Pos] & 0x1FU));
+#endif
+}
+ 8009d40:	4618      	mov	r0, r3
+ 8009d42:	bd80      	pop	{r7, pc}
+ 8009d44:	58024400 	.word	0x58024400
+ 8009d48:	08026b40 	.word	0x08026b40
+
+08009d4c <HAL_RCCEx_GetPLL2ClockFreq>:
+  *         right PLL2CLK value. Otherwise, any configuration based on this function will be incorrect.
+  * @param  PLL2_Clocks structure.
+  * @retval None
+  */
+void HAL_RCCEx_GetPLL2ClockFreq(PLL2_ClocksTypeDef *PLL2_Clocks)
+{
+ 8009d4c:	b480      	push	{r7}
+ 8009d4e:	b089      	sub	sp, #36	; 0x24
+ 8009d50:	af00      	add	r7, sp, #0
+ 8009d52:	6078      	str	r0, [r7, #4]
+  float_t fracn2, pll2vco;
+
+  /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLL2M) * PLL2N
+     PLL2xCLK = PLL2_VCO / PLL2x
+  */
+  pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
+ 8009d54:	4ba1      	ldr	r3, [pc, #644]	; (8009fdc <HAL_RCCEx_GetPLL2ClockFreq+0x290>)
+ 8009d56:	6a9b      	ldr	r3, [r3, #40]	; 0x28
+ 8009d58:	f003 0303 	and.w	r3, r3, #3
+ 8009d5c:	61bb      	str	r3, [r7, #24]
+  pll2m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM2) >> 12);
+ 8009d5e:	4b9f      	ldr	r3, [pc, #636]	; (8009fdc <HAL_RCCEx_GetPLL2ClockFreq+0x290>)
+ 8009d60:	6a9b      	ldr	r3, [r3, #40]	; 0x28
+ 8009d62:	0b1b      	lsrs	r3, r3, #12
+ 8009d64:	f003 033f 	and.w	r3, r3, #63	; 0x3f
+ 8009d68:	617b      	str	r3, [r7, #20]
+  pll2fracen = (RCC->PLLCFGR & RCC_PLLCFGR_PLL2FRACEN) >> RCC_PLLCFGR_PLL2FRACEN_Pos;
+ 8009d6a:	4b9c      	ldr	r3, [pc, #624]	; (8009fdc <HAL_RCCEx_GetPLL2ClockFreq+0x290>)
+ 8009d6c:	6adb      	ldr	r3, [r3, #44]	; 0x2c
+ 8009d6e:	091b      	lsrs	r3, r3, #4
+ 8009d70:	f003 0301 	and.w	r3, r3, #1
+ 8009d74:	613b      	str	r3, [r7, #16]
+  fracn2 = (float_t)(uint32_t)(pll2fracen * ((RCC->PLL2FRACR & RCC_PLL2FRACR_FRACN2) >> 3));
+ 8009d76:	4b99      	ldr	r3, [pc, #612]	; (8009fdc <HAL_RCCEx_GetPLL2ClockFreq+0x290>)
+ 8009d78:	6bdb      	ldr	r3, [r3, #60]	; 0x3c
+ 8009d7a:	08db      	lsrs	r3, r3, #3
+ 8009d7c:	f3c3 030c 	ubfx	r3, r3, #0, #13
+ 8009d80:	693a      	ldr	r2, [r7, #16]
+ 8009d82:	fb02 f303 	mul.w	r3, r2, r3
+ 8009d86:	ee07 3a90 	vmov	s15, r3
+ 8009d8a:	eef8 7a67 	vcvt.f32.u32	s15, s15
+ 8009d8e:	edc7 7a03 	vstr	s15, [r7, #12]
+
+  if (pll2m != 0U)
+ 8009d92:	697b      	ldr	r3, [r7, #20]
+ 8009d94:	2b00      	cmp	r3, #0
+ 8009d96:	f000 8111 	beq.w	8009fbc <HAL_RCCEx_GetPLL2ClockFreq+0x270>
+  {
+    switch (pllsource)
+ 8009d9a:	69bb      	ldr	r3, [r7, #24]
+ 8009d9c:	2b02      	cmp	r3, #2
+ 8009d9e:	f000 8083 	beq.w	8009ea8 <HAL_RCCEx_GetPLL2ClockFreq+0x15c>
+ 8009da2:	69bb      	ldr	r3, [r7, #24]
+ 8009da4:	2b02      	cmp	r3, #2
+ 8009da6:	f200 80a1 	bhi.w	8009eec <HAL_RCCEx_GetPLL2ClockFreq+0x1a0>
+ 8009daa:	69bb      	ldr	r3, [r7, #24]
+ 8009dac:	2b00      	cmp	r3, #0
+ 8009dae:	d003      	beq.n	8009db8 <HAL_RCCEx_GetPLL2ClockFreq+0x6c>
+ 8009db0:	69bb      	ldr	r3, [r7, #24]
+ 8009db2:	2b01      	cmp	r3, #1
+ 8009db4:	d056      	beq.n	8009e64 <HAL_RCCEx_GetPLL2ClockFreq+0x118>
+ 8009db6:	e099      	b.n	8009eec <HAL_RCCEx_GetPLL2ClockFreq+0x1a0>
+    {
+
+      case RCC_PLLSOURCE_HSI:  /* HSI used as PLL clock source */
+
+        if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
+ 8009db8:	4b88      	ldr	r3, [pc, #544]	; (8009fdc <HAL_RCCEx_GetPLL2ClockFreq+0x290>)
+ 8009dba:	681b      	ldr	r3, [r3, #0]
+ 8009dbc:	f003 0320 	and.w	r3, r3, #32
+ 8009dc0:	2b00      	cmp	r3, #0
+ 8009dc2:	d02d      	beq.n	8009e20 <HAL_RCCEx_GetPLL2ClockFreq+0xd4>
+        {
+          hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
+ 8009dc4:	4b85      	ldr	r3, [pc, #532]	; (8009fdc <HAL_RCCEx_GetPLL2ClockFreq+0x290>)
+ 8009dc6:	681b      	ldr	r3, [r3, #0]
+ 8009dc8:	08db      	lsrs	r3, r3, #3
+ 8009dca:	f003 0303 	and.w	r3, r3, #3
+ 8009dce:	4a84      	ldr	r2, [pc, #528]	; (8009fe0 <HAL_RCCEx_GetPLL2ClockFreq+0x294>)
+ 8009dd0:	fa22 f303 	lsr.w	r3, r2, r3
+ 8009dd4:	60bb      	str	r3, [r7, #8]
+          pll2vco = ((float_t)hsivalue / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1);
+ 8009dd6:	68bb      	ldr	r3, [r7, #8]
+ 8009dd8:	ee07 3a90 	vmov	s15, r3
+ 8009ddc:	eef8 6a67 	vcvt.f32.u32	s13, s15
+ 8009de0:	697b      	ldr	r3, [r7, #20]
+ 8009de2:	ee07 3a90 	vmov	s15, r3
+ 8009de6:	eef8 7a67 	vcvt.f32.u32	s15, s15
+ 8009dea:	ee86 7aa7 	vdiv.f32	s14, s13, s15
+ 8009dee:	4b7b      	ldr	r3, [pc, #492]	; (8009fdc <HAL_RCCEx_GetPLL2ClockFreq+0x290>)
+ 8009df0:	6b9b      	ldr	r3, [r3, #56]	; 0x38
+ 8009df2:	f3c3 0308 	ubfx	r3, r3, #0, #9
+ 8009df6:	ee07 3a90 	vmov	s15, r3
+ 8009dfa:	eef8 6a67 	vcvt.f32.u32	s13, s15
+ 8009dfe:	ed97 6a03 	vldr	s12, [r7, #12]
+ 8009e02:	eddf 5a78 	vldr	s11, [pc, #480]	; 8009fe4 <HAL_RCCEx_GetPLL2ClockFreq+0x298>
+ 8009e06:	eec6 7a25 	vdiv.f32	s15, s12, s11
+ 8009e0a:	ee76 7aa7 	vadd.f32	s15, s13, s15
+ 8009e0e:	eef7 6a00 	vmov.f32	s13, #112	; 0x3f800000  1.0
+ 8009e12:	ee77 7aa6 	vadd.f32	s15, s15, s13
+ 8009e16:	ee67 7a27 	vmul.f32	s15, s14, s15
+ 8009e1a:	edc7 7a07 	vstr	s15, [r7, #28]
+        }
+        else
+        {
+          pll2vco = ((float_t)HSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1);
+        }
+        break;
+ 8009e1e:	e087      	b.n	8009f30 <HAL_RCCEx_GetPLL2ClockFreq+0x1e4>
+          pll2vco = ((float_t)HSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1);
+ 8009e20:	697b      	ldr	r3, [r7, #20]
+ 8009e22:	ee07 3a90 	vmov	s15, r3
+ 8009e26:	eef8 7a67 	vcvt.f32.u32	s15, s15
+ 8009e2a:	eddf 6a6f 	vldr	s13, [pc, #444]	; 8009fe8 <HAL_RCCEx_GetPLL2ClockFreq+0x29c>
+ 8009e2e:	ee86 7aa7 	vdiv.f32	s14, s13, s15
+ 8009e32:	4b6a      	ldr	r3, [pc, #424]	; (8009fdc <HAL_RCCEx_GetPLL2ClockFreq+0x290>)
+ 8009e34:	6b9b      	ldr	r3, [r3, #56]	; 0x38
+ 8009e36:	f3c3 0308 	ubfx	r3, r3, #0, #9
+ 8009e3a:	ee07 3a90 	vmov	s15, r3
+ 8009e3e:	eef8 6a67 	vcvt.f32.u32	s13, s15
+ 8009e42:	ed97 6a03 	vldr	s12, [r7, #12]
+ 8009e46:	eddf 5a67 	vldr	s11, [pc, #412]	; 8009fe4 <HAL_RCCEx_GetPLL2ClockFreq+0x298>
+ 8009e4a:	eec6 7a25 	vdiv.f32	s15, s12, s11
+ 8009e4e:	ee76 7aa7 	vadd.f32	s15, s13, s15
+ 8009e52:	eef7 6a00 	vmov.f32	s13, #112	; 0x3f800000  1.0
+ 8009e56:	ee77 7aa6 	vadd.f32	s15, s15, s13
+ 8009e5a:	ee67 7a27 	vmul.f32	s15, s14, s15
+ 8009e5e:	edc7 7a07 	vstr	s15, [r7, #28]
+        break;
+ 8009e62:	e065      	b.n	8009f30 <HAL_RCCEx_GetPLL2ClockFreq+0x1e4>
+
+      case RCC_PLLSOURCE_CSI:  /* CSI used as PLL clock source */
+        pll2vco = ((float_t)CSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1);
+ 8009e64:	697b      	ldr	r3, [r7, #20]
+ 8009e66:	ee07 3a90 	vmov	s15, r3
+ 8009e6a:	eef8 7a67 	vcvt.f32.u32	s15, s15
+ 8009e6e:	eddf 6a5f 	vldr	s13, [pc, #380]	; 8009fec <HAL_RCCEx_GetPLL2ClockFreq+0x2a0>
+ 8009e72:	ee86 7aa7 	vdiv.f32	s14, s13, s15
+ 8009e76:	4b59      	ldr	r3, [pc, #356]	; (8009fdc <HAL_RCCEx_GetPLL2ClockFreq+0x290>)
+ 8009e78:	6b9b      	ldr	r3, [r3, #56]	; 0x38
+ 8009e7a:	f3c3 0308 	ubfx	r3, r3, #0, #9
+ 8009e7e:	ee07 3a90 	vmov	s15, r3
+ 8009e82:	eef8 6a67 	vcvt.f32.u32	s13, s15
+ 8009e86:	ed97 6a03 	vldr	s12, [r7, #12]
+ 8009e8a:	eddf 5a56 	vldr	s11, [pc, #344]	; 8009fe4 <HAL_RCCEx_GetPLL2ClockFreq+0x298>
+ 8009e8e:	eec6 7a25 	vdiv.f32	s15, s12, s11
+ 8009e92:	ee76 7aa7 	vadd.f32	s15, s13, s15
+ 8009e96:	eef7 6a00 	vmov.f32	s13, #112	; 0x3f800000  1.0
+ 8009e9a:	ee77 7aa6 	vadd.f32	s15, s15, s13
+ 8009e9e:	ee67 7a27 	vmul.f32	s15, s14, s15
+ 8009ea2:	edc7 7a07 	vstr	s15, [r7, #28]
+        break;
+ 8009ea6:	e043      	b.n	8009f30 <HAL_RCCEx_GetPLL2ClockFreq+0x1e4>
+
+      case RCC_PLLSOURCE_HSE:  /* HSE used as PLL clock source */
+        pll2vco = ((float_t)HSE_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1);
+ 8009ea8:	697b      	ldr	r3, [r7, #20]
+ 8009eaa:	ee07 3a90 	vmov	s15, r3
+ 8009eae:	eef8 7a67 	vcvt.f32.u32	s15, s15
+ 8009eb2:	eddf 6a4f 	vldr	s13, [pc, #316]	; 8009ff0 <HAL_RCCEx_GetPLL2ClockFreq+0x2a4>
+ 8009eb6:	ee86 7aa7 	vdiv.f32	s14, s13, s15
+ 8009eba:	4b48      	ldr	r3, [pc, #288]	; (8009fdc <HAL_RCCEx_GetPLL2ClockFreq+0x290>)
+ 8009ebc:	6b9b      	ldr	r3, [r3, #56]	; 0x38
+ 8009ebe:	f3c3 0308 	ubfx	r3, r3, #0, #9
+ 8009ec2:	ee07 3a90 	vmov	s15, r3
+ 8009ec6:	eef8 6a67 	vcvt.f32.u32	s13, s15
+ 8009eca:	ed97 6a03 	vldr	s12, [r7, #12]
+ 8009ece:	eddf 5a45 	vldr	s11, [pc, #276]	; 8009fe4 <HAL_RCCEx_GetPLL2ClockFreq+0x298>
+ 8009ed2:	eec6 7a25 	vdiv.f32	s15, s12, s11
+ 8009ed6:	ee76 7aa7 	vadd.f32	s15, s13, s15
+ 8009eda:	eef7 6a00 	vmov.f32	s13, #112	; 0x3f800000  1.0
+ 8009ede:	ee77 7aa6 	vadd.f32	s15, s15, s13
+ 8009ee2:	ee67 7a27 	vmul.f32	s15, s14, s15
+ 8009ee6:	edc7 7a07 	vstr	s15, [r7, #28]
+        break;
+ 8009eea:	e021      	b.n	8009f30 <HAL_RCCEx_GetPLL2ClockFreq+0x1e4>
+
+      default:
+        pll2vco = ((float_t)CSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1);
+ 8009eec:	697b      	ldr	r3, [r7, #20]
+ 8009eee:	ee07 3a90 	vmov	s15, r3
+ 8009ef2:	eef8 7a67 	vcvt.f32.u32	s15, s15
+ 8009ef6:	eddf 6a3d 	vldr	s13, [pc, #244]	; 8009fec <HAL_RCCEx_GetPLL2ClockFreq+0x2a0>
+ 8009efa:	ee86 7aa7 	vdiv.f32	s14, s13, s15
+ 8009efe:	4b37      	ldr	r3, [pc, #220]	; (8009fdc <HAL_RCCEx_GetPLL2ClockFreq+0x290>)
+ 8009f00:	6b9b      	ldr	r3, [r3, #56]	; 0x38
+ 8009f02:	f3c3 0308 	ubfx	r3, r3, #0, #9
+ 8009f06:	ee07 3a90 	vmov	s15, r3
+ 8009f0a:	eef8 6a67 	vcvt.f32.u32	s13, s15
+ 8009f0e:	ed97 6a03 	vldr	s12, [r7, #12]
+ 8009f12:	eddf 5a34 	vldr	s11, [pc, #208]	; 8009fe4 <HAL_RCCEx_GetPLL2ClockFreq+0x298>
+ 8009f16:	eec6 7a25 	vdiv.f32	s15, s12, s11
+ 8009f1a:	ee76 7aa7 	vadd.f32	s15, s13, s15
+ 8009f1e:	eef7 6a00 	vmov.f32	s13, #112	; 0x3f800000  1.0
+ 8009f22:	ee77 7aa6 	vadd.f32	s15, s15, s13
+ 8009f26:	ee67 7a27 	vmul.f32	s15, s14, s15
+ 8009f2a:	edc7 7a07 	vstr	s15, [r7, #28]
+        break;
+ 8009f2e:	bf00      	nop
+    }
+    PLL2_Clocks->PLL2_P_Frequency = (uint32_t)(float_t)(pll2vco / ((float_t)(uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_P2) >> 9)  + (float_t)1)) ;
+ 8009f30:	4b2a      	ldr	r3, [pc, #168]	; (8009fdc <HAL_RCCEx_GetPLL2ClockFreq+0x290>)
+ 8009f32:	6b9b      	ldr	r3, [r3, #56]	; 0x38
+ 8009f34:	0a5b      	lsrs	r3, r3, #9
+ 8009f36:	f003 037f 	and.w	r3, r3, #127	; 0x7f
+ 8009f3a:	ee07 3a90 	vmov	s15, r3
+ 8009f3e:	eef8 7a67 	vcvt.f32.u32	s15, s15
+ 8009f42:	eeb7 7a00 	vmov.f32	s14, #112	; 0x3f800000  1.0
+ 8009f46:	ee37 7a87 	vadd.f32	s14, s15, s14
+ 8009f4a:	edd7 6a07 	vldr	s13, [r7, #28]
+ 8009f4e:	eec6 7a87 	vdiv.f32	s15, s13, s14
+ 8009f52:	eefc 7ae7 	vcvt.u32.f32	s15, s15
+ 8009f56:	ee17 2a90 	vmov	r2, s15
+ 8009f5a:	687b      	ldr	r3, [r7, #4]
+ 8009f5c:	601a      	str	r2, [r3, #0]
+    PLL2_Clocks->PLL2_Q_Frequency = (uint32_t)(float_t)(pll2vco / ((float_t)(uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_Q2) >> 16) + (float_t)1)) ;
+ 8009f5e:	4b1f      	ldr	r3, [pc, #124]	; (8009fdc <HAL_RCCEx_GetPLL2ClockFreq+0x290>)
+ 8009f60:	6b9b      	ldr	r3, [r3, #56]	; 0x38
+ 8009f62:	0c1b      	lsrs	r3, r3, #16
+ 8009f64:	f003 037f 	and.w	r3, r3, #127	; 0x7f
+ 8009f68:	ee07 3a90 	vmov	s15, r3
+ 8009f6c:	eef8 7a67 	vcvt.f32.u32	s15, s15
+ 8009f70:	eeb7 7a00 	vmov.f32	s14, #112	; 0x3f800000  1.0
+ 8009f74:	ee37 7a87 	vadd.f32	s14, s15, s14
+ 8009f78:	edd7 6a07 	vldr	s13, [r7, #28]
+ 8009f7c:	eec6 7a87 	vdiv.f32	s15, s13, s14
+ 8009f80:	eefc 7ae7 	vcvt.u32.f32	s15, s15
+ 8009f84:	ee17 2a90 	vmov	r2, s15
+ 8009f88:	687b      	ldr	r3, [r7, #4]
+ 8009f8a:	605a      	str	r2, [r3, #4]
+    PLL2_Clocks->PLL2_R_Frequency = (uint32_t)(float_t)(pll2vco / ((float_t)(uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_R2) >> 24) + (float_t)1)) ;
+ 8009f8c:	4b13      	ldr	r3, [pc, #76]	; (8009fdc <HAL_RCCEx_GetPLL2ClockFreq+0x290>)
+ 8009f8e:	6b9b      	ldr	r3, [r3, #56]	; 0x38
+ 8009f90:	0e1b      	lsrs	r3, r3, #24
+ 8009f92:	f003 037f 	and.w	r3, r3, #127	; 0x7f
+ 8009f96:	ee07 3a90 	vmov	s15, r3
+ 8009f9a:	eef8 7a67 	vcvt.f32.u32	s15, s15
+ 8009f9e:	eeb7 7a00 	vmov.f32	s14, #112	; 0x3f800000  1.0
+ 8009fa2:	ee37 7a87 	vadd.f32	s14, s15, s14
+ 8009fa6:	edd7 6a07 	vldr	s13, [r7, #28]
+ 8009faa:	eec6 7a87 	vdiv.f32	s15, s13, s14
+ 8009fae:	eefc 7ae7 	vcvt.u32.f32	s15, s15
+ 8009fb2:	ee17 2a90 	vmov	r2, s15
+ 8009fb6:	687b      	ldr	r3, [r7, #4]
+ 8009fb8:	609a      	str	r2, [r3, #8]
+  {
+    PLL2_Clocks->PLL2_P_Frequency = 0U;
+    PLL2_Clocks->PLL2_Q_Frequency = 0U;
+    PLL2_Clocks->PLL2_R_Frequency = 0U;
+  }
+}
+ 8009fba:	e008      	b.n	8009fce <HAL_RCCEx_GetPLL2ClockFreq+0x282>
+    PLL2_Clocks->PLL2_P_Frequency = 0U;
+ 8009fbc:	687b      	ldr	r3, [r7, #4]
+ 8009fbe:	2200      	movs	r2, #0
+ 8009fc0:	601a      	str	r2, [r3, #0]
+    PLL2_Clocks->PLL2_Q_Frequency = 0U;
+ 8009fc2:	687b      	ldr	r3, [r7, #4]
+ 8009fc4:	2200      	movs	r2, #0
+ 8009fc6:	605a      	str	r2, [r3, #4]
+    PLL2_Clocks->PLL2_R_Frequency = 0U;
+ 8009fc8:	687b      	ldr	r3, [r7, #4]
+ 8009fca:	2200      	movs	r2, #0
+ 8009fcc:	609a      	str	r2, [r3, #8]
+}
+ 8009fce:	bf00      	nop
+ 8009fd0:	3724      	adds	r7, #36	; 0x24
+ 8009fd2:	46bd      	mov	sp, r7
+ 8009fd4:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8009fd8:	4770      	bx	lr
+ 8009fda:	bf00      	nop
+ 8009fdc:	58024400 	.word	0x58024400
+ 8009fe0:	03d09000 	.word	0x03d09000
+ 8009fe4:	46000000 	.word	0x46000000
+ 8009fe8:	4c742400 	.word	0x4c742400
+ 8009fec:	4a742400 	.word	0x4a742400
+ 8009ff0:	4bbebc20 	.word	0x4bbebc20
+
+08009ff4 <HAL_RCCEx_GetPLL3ClockFreq>:
+  *         right PLL3CLK value. Otherwise, any configuration based on this function will be incorrect.
+  * @param  PLL3_Clocks structure.
+  * @retval None
+  */
+void HAL_RCCEx_GetPLL3ClockFreq(PLL3_ClocksTypeDef *PLL3_Clocks)
+{
+ 8009ff4:	b480      	push	{r7}
+ 8009ff6:	b089      	sub	sp, #36	; 0x24
+ 8009ff8:	af00      	add	r7, sp, #0
+ 8009ffa:	6078      	str	r0, [r7, #4]
+  float_t fracn3, pll3vco;
+
+  /* PLL3_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLL3M) * PLL3N
+     PLL3xCLK = PLL3_VCO / PLLxR
+  */
+  pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
+ 8009ffc:	4ba1      	ldr	r3, [pc, #644]	; (800a284 <HAL_RCCEx_GetPLL3ClockFreq+0x290>)
+ 8009ffe:	6a9b      	ldr	r3, [r3, #40]	; 0x28
+ 800a000:	f003 0303 	and.w	r3, r3, #3
+ 800a004:	61bb      	str	r3, [r7, #24]
+  pll3m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM3) >> 20)  ;
+ 800a006:	4b9f      	ldr	r3, [pc, #636]	; (800a284 <HAL_RCCEx_GetPLL3ClockFreq+0x290>)
+ 800a008:	6a9b      	ldr	r3, [r3, #40]	; 0x28
+ 800a00a:	0d1b      	lsrs	r3, r3, #20
+ 800a00c:	f003 033f 	and.w	r3, r3, #63	; 0x3f
+ 800a010:	617b      	str	r3, [r7, #20]
+  pll3fracen = (RCC->PLLCFGR & RCC_PLLCFGR_PLL3FRACEN) >> RCC_PLLCFGR_PLL3FRACEN_Pos;
+ 800a012:	4b9c      	ldr	r3, [pc, #624]	; (800a284 <HAL_RCCEx_GetPLL3ClockFreq+0x290>)
+ 800a014:	6adb      	ldr	r3, [r3, #44]	; 0x2c
+ 800a016:	0a1b      	lsrs	r3, r3, #8
+ 800a018:	f003 0301 	and.w	r3, r3, #1
+ 800a01c:	613b      	str	r3, [r7, #16]
+  fracn3 = (float_t)(uint32_t)(pll3fracen * ((RCC->PLL3FRACR & RCC_PLL3FRACR_FRACN3) >> 3));
+ 800a01e:	4b99      	ldr	r3, [pc, #612]	; (800a284 <HAL_RCCEx_GetPLL3ClockFreq+0x290>)
+ 800a020:	6c5b      	ldr	r3, [r3, #68]	; 0x44
+ 800a022:	08db      	lsrs	r3, r3, #3
+ 800a024:	f3c3 030c 	ubfx	r3, r3, #0, #13
+ 800a028:	693a      	ldr	r2, [r7, #16]
+ 800a02a:	fb02 f303 	mul.w	r3, r2, r3
+ 800a02e:	ee07 3a90 	vmov	s15, r3
+ 800a032:	eef8 7a67 	vcvt.f32.u32	s15, s15
+ 800a036:	edc7 7a03 	vstr	s15, [r7, #12]
+
+  if (pll3m != 0U)
+ 800a03a:	697b      	ldr	r3, [r7, #20]
+ 800a03c:	2b00      	cmp	r3, #0
+ 800a03e:	f000 8111 	beq.w	800a264 <HAL_RCCEx_GetPLL3ClockFreq+0x270>
+  {
+    switch (pllsource)
+ 800a042:	69bb      	ldr	r3, [r7, #24]
+ 800a044:	2b02      	cmp	r3, #2
+ 800a046:	f000 8083 	beq.w	800a150 <HAL_RCCEx_GetPLL3ClockFreq+0x15c>
+ 800a04a:	69bb      	ldr	r3, [r7, #24]
+ 800a04c:	2b02      	cmp	r3, #2
+ 800a04e:	f200 80a1 	bhi.w	800a194 <HAL_RCCEx_GetPLL3ClockFreq+0x1a0>
+ 800a052:	69bb      	ldr	r3, [r7, #24]
+ 800a054:	2b00      	cmp	r3, #0
+ 800a056:	d003      	beq.n	800a060 <HAL_RCCEx_GetPLL3ClockFreq+0x6c>
+ 800a058:	69bb      	ldr	r3, [r7, #24]
+ 800a05a:	2b01      	cmp	r3, #1
+ 800a05c:	d056      	beq.n	800a10c <HAL_RCCEx_GetPLL3ClockFreq+0x118>
+ 800a05e:	e099      	b.n	800a194 <HAL_RCCEx_GetPLL3ClockFreq+0x1a0>
+    {
+      case RCC_PLLSOURCE_HSI:  /* HSI used as PLL clock source */
+
+        if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
+ 800a060:	4b88      	ldr	r3, [pc, #544]	; (800a284 <HAL_RCCEx_GetPLL3ClockFreq+0x290>)
+ 800a062:	681b      	ldr	r3, [r3, #0]
+ 800a064:	f003 0320 	and.w	r3, r3, #32
+ 800a068:	2b00      	cmp	r3, #0
+ 800a06a:	d02d      	beq.n	800a0c8 <HAL_RCCEx_GetPLL3ClockFreq+0xd4>
+        {
+          hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
+ 800a06c:	4b85      	ldr	r3, [pc, #532]	; (800a284 <HAL_RCCEx_GetPLL3ClockFreq+0x290>)
+ 800a06e:	681b      	ldr	r3, [r3, #0]
+ 800a070:	08db      	lsrs	r3, r3, #3
+ 800a072:	f003 0303 	and.w	r3, r3, #3
+ 800a076:	4a84      	ldr	r2, [pc, #528]	; (800a288 <HAL_RCCEx_GetPLL3ClockFreq+0x294>)
+ 800a078:	fa22 f303 	lsr.w	r3, r2, r3
+ 800a07c:	60bb      	str	r3, [r7, #8]
+          pll3vco = ((float_t)hsivalue / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1);
+ 800a07e:	68bb      	ldr	r3, [r7, #8]
+ 800a080:	ee07 3a90 	vmov	s15, r3
+ 800a084:	eef8 6a67 	vcvt.f32.u32	s13, s15
+ 800a088:	697b      	ldr	r3, [r7, #20]
+ 800a08a:	ee07 3a90 	vmov	s15, r3
+ 800a08e:	eef8 7a67 	vcvt.f32.u32	s15, s15
+ 800a092:	ee86 7aa7 	vdiv.f32	s14, s13, s15
+ 800a096:	4b7b      	ldr	r3, [pc, #492]	; (800a284 <HAL_RCCEx_GetPLL3ClockFreq+0x290>)
+ 800a098:	6c1b      	ldr	r3, [r3, #64]	; 0x40
+ 800a09a:	f3c3 0308 	ubfx	r3, r3, #0, #9
+ 800a09e:	ee07 3a90 	vmov	s15, r3
+ 800a0a2:	eef8 6a67 	vcvt.f32.u32	s13, s15
+ 800a0a6:	ed97 6a03 	vldr	s12, [r7, #12]
+ 800a0aa:	eddf 5a78 	vldr	s11, [pc, #480]	; 800a28c <HAL_RCCEx_GetPLL3ClockFreq+0x298>
+ 800a0ae:	eec6 7a25 	vdiv.f32	s15, s12, s11
+ 800a0b2:	ee76 7aa7 	vadd.f32	s15, s13, s15
+ 800a0b6:	eef7 6a00 	vmov.f32	s13, #112	; 0x3f800000  1.0
+ 800a0ba:	ee77 7aa6 	vadd.f32	s15, s15, s13
+ 800a0be:	ee67 7a27 	vmul.f32	s15, s14, s15
+ 800a0c2:	edc7 7a07 	vstr	s15, [r7, #28]
+        }
+        else
+        {
+          pll3vco = ((float_t)HSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1);
+        }
+        break;
+ 800a0c6:	e087      	b.n	800a1d8 <HAL_RCCEx_GetPLL3ClockFreq+0x1e4>
+          pll3vco = ((float_t)HSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1);
+ 800a0c8:	697b      	ldr	r3, [r7, #20]
+ 800a0ca:	ee07 3a90 	vmov	s15, r3
+ 800a0ce:	eef8 7a67 	vcvt.f32.u32	s15, s15
+ 800a0d2:	eddf 6a6f 	vldr	s13, [pc, #444]	; 800a290 <HAL_RCCEx_GetPLL3ClockFreq+0x29c>
+ 800a0d6:	ee86 7aa7 	vdiv.f32	s14, s13, s15
+ 800a0da:	4b6a      	ldr	r3, [pc, #424]	; (800a284 <HAL_RCCEx_GetPLL3ClockFreq+0x290>)
+ 800a0dc:	6c1b      	ldr	r3, [r3, #64]	; 0x40
+ 800a0de:	f3c3 0308 	ubfx	r3, r3, #0, #9
+ 800a0e2:	ee07 3a90 	vmov	s15, r3
+ 800a0e6:	eef8 6a67 	vcvt.f32.u32	s13, s15
+ 800a0ea:	ed97 6a03 	vldr	s12, [r7, #12]
+ 800a0ee:	eddf 5a67 	vldr	s11, [pc, #412]	; 800a28c <HAL_RCCEx_GetPLL3ClockFreq+0x298>
+ 800a0f2:	eec6 7a25 	vdiv.f32	s15, s12, s11
+ 800a0f6:	ee76 7aa7 	vadd.f32	s15, s13, s15
+ 800a0fa:	eef7 6a00 	vmov.f32	s13, #112	; 0x3f800000  1.0
+ 800a0fe:	ee77 7aa6 	vadd.f32	s15, s15, s13
+ 800a102:	ee67 7a27 	vmul.f32	s15, s14, s15
+ 800a106:	edc7 7a07 	vstr	s15, [r7, #28]
+        break;
+ 800a10a:	e065      	b.n	800a1d8 <HAL_RCCEx_GetPLL3ClockFreq+0x1e4>
+      case RCC_PLLSOURCE_CSI:  /* CSI used as PLL clock source */
+        pll3vco = ((float_t)CSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1);
+ 800a10c:	697b      	ldr	r3, [r7, #20]
+ 800a10e:	ee07 3a90 	vmov	s15, r3
+ 800a112:	eef8 7a67 	vcvt.f32.u32	s15, s15
+ 800a116:	eddf 6a5f 	vldr	s13, [pc, #380]	; 800a294 <HAL_RCCEx_GetPLL3ClockFreq+0x2a0>
+ 800a11a:	ee86 7aa7 	vdiv.f32	s14, s13, s15
+ 800a11e:	4b59      	ldr	r3, [pc, #356]	; (800a284 <HAL_RCCEx_GetPLL3ClockFreq+0x290>)
+ 800a120:	6c1b      	ldr	r3, [r3, #64]	; 0x40
+ 800a122:	f3c3 0308 	ubfx	r3, r3, #0, #9
+ 800a126:	ee07 3a90 	vmov	s15, r3
+ 800a12a:	eef8 6a67 	vcvt.f32.u32	s13, s15
+ 800a12e:	ed97 6a03 	vldr	s12, [r7, #12]
+ 800a132:	eddf 5a56 	vldr	s11, [pc, #344]	; 800a28c <HAL_RCCEx_GetPLL3ClockFreq+0x298>
+ 800a136:	eec6 7a25 	vdiv.f32	s15, s12, s11
+ 800a13a:	ee76 7aa7 	vadd.f32	s15, s13, s15
+ 800a13e:	eef7 6a00 	vmov.f32	s13, #112	; 0x3f800000  1.0
+ 800a142:	ee77 7aa6 	vadd.f32	s15, s15, s13
+ 800a146:	ee67 7a27 	vmul.f32	s15, s14, s15
+ 800a14a:	edc7 7a07 	vstr	s15, [r7, #28]
+        break;
+ 800a14e:	e043      	b.n	800a1d8 <HAL_RCCEx_GetPLL3ClockFreq+0x1e4>
+
+      case RCC_PLLSOURCE_HSE:  /* HSE used as PLL clock source */
+        pll3vco = ((float_t)HSE_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1);
+ 800a150:	697b      	ldr	r3, [r7, #20]
+ 800a152:	ee07 3a90 	vmov	s15, r3
+ 800a156:	eef8 7a67 	vcvt.f32.u32	s15, s15
+ 800a15a:	eddf 6a4f 	vldr	s13, [pc, #316]	; 800a298 <HAL_RCCEx_GetPLL3ClockFreq+0x2a4>
+ 800a15e:	ee86 7aa7 	vdiv.f32	s14, s13, s15
+ 800a162:	4b48      	ldr	r3, [pc, #288]	; (800a284 <HAL_RCCEx_GetPLL3ClockFreq+0x290>)
+ 800a164:	6c1b      	ldr	r3, [r3, #64]	; 0x40
+ 800a166:	f3c3 0308 	ubfx	r3, r3, #0, #9
+ 800a16a:	ee07 3a90 	vmov	s15, r3
+ 800a16e:	eef8 6a67 	vcvt.f32.u32	s13, s15
+ 800a172:	ed97 6a03 	vldr	s12, [r7, #12]
+ 800a176:	eddf 5a45 	vldr	s11, [pc, #276]	; 800a28c <HAL_RCCEx_GetPLL3ClockFreq+0x298>
+ 800a17a:	eec6 7a25 	vdiv.f32	s15, s12, s11
+ 800a17e:	ee76 7aa7 	vadd.f32	s15, s13, s15
+ 800a182:	eef7 6a00 	vmov.f32	s13, #112	; 0x3f800000  1.0
+ 800a186:	ee77 7aa6 	vadd.f32	s15, s15, s13
+ 800a18a:	ee67 7a27 	vmul.f32	s15, s14, s15
+ 800a18e:	edc7 7a07 	vstr	s15, [r7, #28]
+        break;
+ 800a192:	e021      	b.n	800a1d8 <HAL_RCCEx_GetPLL3ClockFreq+0x1e4>
+
+      default:
+        pll3vco = ((float_t)CSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1);
+ 800a194:	697b      	ldr	r3, [r7, #20]
+ 800a196:	ee07 3a90 	vmov	s15, r3
+ 800a19a:	eef8 7a67 	vcvt.f32.u32	s15, s15
+ 800a19e:	eddf 6a3d 	vldr	s13, [pc, #244]	; 800a294 <HAL_RCCEx_GetPLL3ClockFreq+0x2a0>
+ 800a1a2:	ee86 7aa7 	vdiv.f32	s14, s13, s15
+ 800a1a6:	4b37      	ldr	r3, [pc, #220]	; (800a284 <HAL_RCCEx_GetPLL3ClockFreq+0x290>)
+ 800a1a8:	6c1b      	ldr	r3, [r3, #64]	; 0x40
+ 800a1aa:	f3c3 0308 	ubfx	r3, r3, #0, #9
+ 800a1ae:	ee07 3a90 	vmov	s15, r3
+ 800a1b2:	eef8 6a67 	vcvt.f32.u32	s13, s15
+ 800a1b6:	ed97 6a03 	vldr	s12, [r7, #12]
+ 800a1ba:	eddf 5a34 	vldr	s11, [pc, #208]	; 800a28c <HAL_RCCEx_GetPLL3ClockFreq+0x298>
+ 800a1be:	eec6 7a25 	vdiv.f32	s15, s12, s11
+ 800a1c2:	ee76 7aa7 	vadd.f32	s15, s13, s15
+ 800a1c6:	eef7 6a00 	vmov.f32	s13, #112	; 0x3f800000  1.0
+ 800a1ca:	ee77 7aa6 	vadd.f32	s15, s15, s13
+ 800a1ce:	ee67 7a27 	vmul.f32	s15, s14, s15
+ 800a1d2:	edc7 7a07 	vstr	s15, [r7, #28]
+        break;
+ 800a1d6:	bf00      	nop
+    }
+    PLL3_Clocks->PLL3_P_Frequency = (uint32_t)(float_t)(pll3vco / ((float_t)(uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_P3) >> 9)  + (float_t)1)) ;
+ 800a1d8:	4b2a      	ldr	r3, [pc, #168]	; (800a284 <HAL_RCCEx_GetPLL3ClockFreq+0x290>)
+ 800a1da:	6c1b      	ldr	r3, [r3, #64]	; 0x40
+ 800a1dc:	0a5b      	lsrs	r3, r3, #9
+ 800a1de:	f003 037f 	and.w	r3, r3, #127	; 0x7f
+ 800a1e2:	ee07 3a90 	vmov	s15, r3
+ 800a1e6:	eef8 7a67 	vcvt.f32.u32	s15, s15
+ 800a1ea:	eeb7 7a00 	vmov.f32	s14, #112	; 0x3f800000  1.0
+ 800a1ee:	ee37 7a87 	vadd.f32	s14, s15, s14
+ 800a1f2:	edd7 6a07 	vldr	s13, [r7, #28]
+ 800a1f6:	eec6 7a87 	vdiv.f32	s15, s13, s14
+ 800a1fa:	eefc 7ae7 	vcvt.u32.f32	s15, s15
+ 800a1fe:	ee17 2a90 	vmov	r2, s15
+ 800a202:	687b      	ldr	r3, [r7, #4]
+ 800a204:	601a      	str	r2, [r3, #0]
+    PLL3_Clocks->PLL3_Q_Frequency = (uint32_t)(float_t)(pll3vco / ((float_t)(uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_Q3) >> 16) + (float_t)1)) ;
+ 800a206:	4b1f      	ldr	r3, [pc, #124]	; (800a284 <HAL_RCCEx_GetPLL3ClockFreq+0x290>)
+ 800a208:	6c1b      	ldr	r3, [r3, #64]	; 0x40
+ 800a20a:	0c1b      	lsrs	r3, r3, #16
+ 800a20c:	f003 037f 	and.w	r3, r3, #127	; 0x7f
+ 800a210:	ee07 3a90 	vmov	s15, r3
+ 800a214:	eef8 7a67 	vcvt.f32.u32	s15, s15
+ 800a218:	eeb7 7a00 	vmov.f32	s14, #112	; 0x3f800000  1.0
+ 800a21c:	ee37 7a87 	vadd.f32	s14, s15, s14
+ 800a220:	edd7 6a07 	vldr	s13, [r7, #28]
+ 800a224:	eec6 7a87 	vdiv.f32	s15, s13, s14
+ 800a228:	eefc 7ae7 	vcvt.u32.f32	s15, s15
+ 800a22c:	ee17 2a90 	vmov	r2, s15
+ 800a230:	687b      	ldr	r3, [r7, #4]
+ 800a232:	605a      	str	r2, [r3, #4]
+    PLL3_Clocks->PLL3_R_Frequency = (uint32_t)(float_t)(pll3vco / ((float_t)(uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_R3) >> 24) + (float_t)1)) ;
+ 800a234:	4b13      	ldr	r3, [pc, #76]	; (800a284 <HAL_RCCEx_GetPLL3ClockFreq+0x290>)
+ 800a236:	6c1b      	ldr	r3, [r3, #64]	; 0x40
+ 800a238:	0e1b      	lsrs	r3, r3, #24
+ 800a23a:	f003 037f 	and.w	r3, r3, #127	; 0x7f
+ 800a23e:	ee07 3a90 	vmov	s15, r3
+ 800a242:	eef8 7a67 	vcvt.f32.u32	s15, s15
+ 800a246:	eeb7 7a00 	vmov.f32	s14, #112	; 0x3f800000  1.0
+ 800a24a:	ee37 7a87 	vadd.f32	s14, s15, s14
+ 800a24e:	edd7 6a07 	vldr	s13, [r7, #28]
+ 800a252:	eec6 7a87 	vdiv.f32	s15, s13, s14
+ 800a256:	eefc 7ae7 	vcvt.u32.f32	s15, s15
+ 800a25a:	ee17 2a90 	vmov	r2, s15
+ 800a25e:	687b      	ldr	r3, [r7, #4]
+ 800a260:	609a      	str	r2, [r3, #8]
+    PLL3_Clocks->PLL3_P_Frequency = 0U;
+    PLL3_Clocks->PLL3_Q_Frequency = 0U;
+    PLL3_Clocks->PLL3_R_Frequency = 0U;
+  }
+
+}
+ 800a262:	e008      	b.n	800a276 <HAL_RCCEx_GetPLL3ClockFreq+0x282>
+    PLL3_Clocks->PLL3_P_Frequency = 0U;
+ 800a264:	687b      	ldr	r3, [r7, #4]
+ 800a266:	2200      	movs	r2, #0
+ 800a268:	601a      	str	r2, [r3, #0]
+    PLL3_Clocks->PLL3_Q_Frequency = 0U;
+ 800a26a:	687b      	ldr	r3, [r7, #4]
+ 800a26c:	2200      	movs	r2, #0
+ 800a26e:	605a      	str	r2, [r3, #4]
+    PLL3_Clocks->PLL3_R_Frequency = 0U;
+ 800a270:	687b      	ldr	r3, [r7, #4]
+ 800a272:	2200      	movs	r2, #0
+ 800a274:	609a      	str	r2, [r3, #8]
+}
+ 800a276:	bf00      	nop
+ 800a278:	3724      	adds	r7, #36	; 0x24
+ 800a27a:	46bd      	mov	sp, r7
+ 800a27c:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 800a280:	4770      	bx	lr
+ 800a282:	bf00      	nop
+ 800a284:	58024400 	.word	0x58024400
+ 800a288:	03d09000 	.word	0x03d09000
+ 800a28c:	46000000 	.word	0x46000000
+ 800a290:	4c742400 	.word	0x4c742400
+ 800a294:	4a742400 	.word	0x4a742400
+ 800a298:	4bbebc20 	.word	0x4bbebc20
+
+0800a29c <HAL_RCCEx_GetPLL1ClockFreq>:
+  *         right PLL1CLK value. Otherwise, any configuration based on this function will be incorrect.
+  * @param  PLL1_Clocks structure.
+  * @retval None
+  */
+void HAL_RCCEx_GetPLL1ClockFreq(PLL1_ClocksTypeDef *PLL1_Clocks)
+{
+ 800a29c:	b480      	push	{r7}
+ 800a29e:	b089      	sub	sp, #36	; 0x24
+ 800a2a0:	af00      	add	r7, sp, #0
+ 800a2a2:	6078      	str	r0, [r7, #4]
+  uint32_t pllsource, pll1m, pll1fracen, hsivalue;
+  float_t fracn1, pll1vco;
+
+  pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
+ 800a2a4:	4ba0      	ldr	r3, [pc, #640]	; (800a528 <HAL_RCCEx_GetPLL1ClockFreq+0x28c>)
+ 800a2a6:	6a9b      	ldr	r3, [r3, #40]	; 0x28
+ 800a2a8:	f003 0303 	and.w	r3, r3, #3
+ 800a2ac:	61bb      	str	r3, [r7, #24]
+  pll1m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1) >> 4);
+ 800a2ae:	4b9e      	ldr	r3, [pc, #632]	; (800a528 <HAL_RCCEx_GetPLL1ClockFreq+0x28c>)
+ 800a2b0:	6a9b      	ldr	r3, [r3, #40]	; 0x28
+ 800a2b2:	091b      	lsrs	r3, r3, #4
+ 800a2b4:	f003 033f 	and.w	r3, r3, #63	; 0x3f
+ 800a2b8:	617b      	str	r3, [r7, #20]
+  pll1fracen = RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN;
+ 800a2ba:	4b9b      	ldr	r3, [pc, #620]	; (800a528 <HAL_RCCEx_GetPLL1ClockFreq+0x28c>)
+ 800a2bc:	6adb      	ldr	r3, [r3, #44]	; 0x2c
+ 800a2be:	f003 0301 	and.w	r3, r3, #1
+ 800a2c2:	613b      	str	r3, [r7, #16]
+  fracn1 = (float_t)(uint32_t)(pll1fracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> 3));
+ 800a2c4:	4b98      	ldr	r3, [pc, #608]	; (800a528 <HAL_RCCEx_GetPLL1ClockFreq+0x28c>)
+ 800a2c6:	6b5b      	ldr	r3, [r3, #52]	; 0x34
+ 800a2c8:	08db      	lsrs	r3, r3, #3
+ 800a2ca:	f3c3 030c 	ubfx	r3, r3, #0, #13
+ 800a2ce:	693a      	ldr	r2, [r7, #16]
+ 800a2d0:	fb02 f303 	mul.w	r3, r2, r3
+ 800a2d4:	ee07 3a90 	vmov	s15, r3
+ 800a2d8:	eef8 7a67 	vcvt.f32.u32	s15, s15
+ 800a2dc:	edc7 7a03 	vstr	s15, [r7, #12]
+
+  if (pll1m != 0U)
+ 800a2e0:	697b      	ldr	r3, [r7, #20]
+ 800a2e2:	2b00      	cmp	r3, #0
+ 800a2e4:	f000 8111 	beq.w	800a50a <HAL_RCCEx_GetPLL1ClockFreq+0x26e>
+  {
+    switch (pllsource)
+ 800a2e8:	69bb      	ldr	r3, [r7, #24]
+ 800a2ea:	2b02      	cmp	r3, #2
+ 800a2ec:	f000 8083 	beq.w	800a3f6 <HAL_RCCEx_GetPLL1ClockFreq+0x15a>
+ 800a2f0:	69bb      	ldr	r3, [r7, #24]
+ 800a2f2:	2b02      	cmp	r3, #2
+ 800a2f4:	f200 80a1 	bhi.w	800a43a <HAL_RCCEx_GetPLL1ClockFreq+0x19e>
+ 800a2f8:	69bb      	ldr	r3, [r7, #24]
+ 800a2fa:	2b00      	cmp	r3, #0
+ 800a2fc:	d003      	beq.n	800a306 <HAL_RCCEx_GetPLL1ClockFreq+0x6a>
+ 800a2fe:	69bb      	ldr	r3, [r7, #24]
+ 800a300:	2b01      	cmp	r3, #1
+ 800a302:	d056      	beq.n	800a3b2 <HAL_RCCEx_GetPLL1ClockFreq+0x116>
+ 800a304:	e099      	b.n	800a43a <HAL_RCCEx_GetPLL1ClockFreq+0x19e>
+    {
+
+      case RCC_PLLSOURCE_HSI:  /* HSI used as PLL clock source */
+
+        if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
+ 800a306:	4b88      	ldr	r3, [pc, #544]	; (800a528 <HAL_RCCEx_GetPLL1ClockFreq+0x28c>)
+ 800a308:	681b      	ldr	r3, [r3, #0]
+ 800a30a:	f003 0320 	and.w	r3, r3, #32
+ 800a30e:	2b00      	cmp	r3, #0
+ 800a310:	d02d      	beq.n	800a36e <HAL_RCCEx_GetPLL1ClockFreq+0xd2>
+        {
+          hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
+ 800a312:	4b85      	ldr	r3, [pc, #532]	; (800a528 <HAL_RCCEx_GetPLL1ClockFreq+0x28c>)
+ 800a314:	681b      	ldr	r3, [r3, #0]
+ 800a316:	08db      	lsrs	r3, r3, #3
+ 800a318:	f003 0303 	and.w	r3, r3, #3
+ 800a31c:	4a83      	ldr	r2, [pc, #524]	; (800a52c <HAL_RCCEx_GetPLL1ClockFreq+0x290>)
+ 800a31e:	fa22 f303 	lsr.w	r3, r2, r3
+ 800a322:	60bb      	str	r3, [r7, #8]
+          pll1vco = ((float_t)hsivalue / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
+ 800a324:	68bb      	ldr	r3, [r7, #8]
+ 800a326:	ee07 3a90 	vmov	s15, r3
+ 800a32a:	eef8 6a67 	vcvt.f32.u32	s13, s15
+ 800a32e:	697b      	ldr	r3, [r7, #20]
+ 800a330:	ee07 3a90 	vmov	s15, r3
+ 800a334:	eef8 7a67 	vcvt.f32.u32	s15, s15
+ 800a338:	ee86 7aa7 	vdiv.f32	s14, s13, s15
+ 800a33c:	4b7a      	ldr	r3, [pc, #488]	; (800a528 <HAL_RCCEx_GetPLL1ClockFreq+0x28c>)
+ 800a33e:	6b1b      	ldr	r3, [r3, #48]	; 0x30
+ 800a340:	f3c3 0308 	ubfx	r3, r3, #0, #9
+ 800a344:	ee07 3a90 	vmov	s15, r3
+ 800a348:	eef8 6a67 	vcvt.f32.u32	s13, s15
+ 800a34c:	ed97 6a03 	vldr	s12, [r7, #12]
+ 800a350:	eddf 5a77 	vldr	s11, [pc, #476]	; 800a530 <HAL_RCCEx_GetPLL1ClockFreq+0x294>
+ 800a354:	eec6 7a25 	vdiv.f32	s15, s12, s11
+ 800a358:	ee76 7aa7 	vadd.f32	s15, s13, s15
+ 800a35c:	eef7 6a00 	vmov.f32	s13, #112	; 0x3f800000  1.0
+ 800a360:	ee77 7aa6 	vadd.f32	s15, s15, s13
+ 800a364:	ee67 7a27 	vmul.f32	s15, s14, s15
+ 800a368:	edc7 7a07 	vstr	s15, [r7, #28]
+        }
+        else
+        {
+          pll1vco = ((float_t)HSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
+        }
+        break;
+ 800a36c:	e087      	b.n	800a47e <HAL_RCCEx_GetPLL1ClockFreq+0x1e2>
+          pll1vco = ((float_t)HSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
+ 800a36e:	697b      	ldr	r3, [r7, #20]
+ 800a370:	ee07 3a90 	vmov	s15, r3
+ 800a374:	eef8 7a67 	vcvt.f32.u32	s15, s15
+ 800a378:	eddf 6a6e 	vldr	s13, [pc, #440]	; 800a534 <HAL_RCCEx_GetPLL1ClockFreq+0x298>
+ 800a37c:	ee86 7aa7 	vdiv.f32	s14, s13, s15
+ 800a380:	4b69      	ldr	r3, [pc, #420]	; (800a528 <HAL_RCCEx_GetPLL1ClockFreq+0x28c>)
+ 800a382:	6b1b      	ldr	r3, [r3, #48]	; 0x30
+ 800a384:	f3c3 0308 	ubfx	r3, r3, #0, #9
+ 800a388:	ee07 3a90 	vmov	s15, r3
+ 800a38c:	eef8 6a67 	vcvt.f32.u32	s13, s15
+ 800a390:	ed97 6a03 	vldr	s12, [r7, #12]
+ 800a394:	eddf 5a66 	vldr	s11, [pc, #408]	; 800a530 <HAL_RCCEx_GetPLL1ClockFreq+0x294>
+ 800a398:	eec6 7a25 	vdiv.f32	s15, s12, s11
+ 800a39c:	ee76 7aa7 	vadd.f32	s15, s13, s15
+ 800a3a0:	eef7 6a00 	vmov.f32	s13, #112	; 0x3f800000  1.0
+ 800a3a4:	ee77 7aa6 	vadd.f32	s15, s15, s13
+ 800a3a8:	ee67 7a27 	vmul.f32	s15, s14, s15
+ 800a3ac:	edc7 7a07 	vstr	s15, [r7, #28]
+        break;
+ 800a3b0:	e065      	b.n	800a47e <HAL_RCCEx_GetPLL1ClockFreq+0x1e2>
+      case RCC_PLLSOURCE_CSI:  /* CSI used as PLL clock source */
+        pll1vco = ((float_t)CSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
+ 800a3b2:	697b      	ldr	r3, [r7, #20]
+ 800a3b4:	ee07 3a90 	vmov	s15, r3
+ 800a3b8:	eef8 7a67 	vcvt.f32.u32	s15, s15
+ 800a3bc:	eddf 6a5e 	vldr	s13, [pc, #376]	; 800a538 <HAL_RCCEx_GetPLL1ClockFreq+0x29c>
+ 800a3c0:	ee86 7aa7 	vdiv.f32	s14, s13, s15
+ 800a3c4:	4b58      	ldr	r3, [pc, #352]	; (800a528 <HAL_RCCEx_GetPLL1ClockFreq+0x28c>)
+ 800a3c6:	6b1b      	ldr	r3, [r3, #48]	; 0x30
+ 800a3c8:	f3c3 0308 	ubfx	r3, r3, #0, #9
+ 800a3cc:	ee07 3a90 	vmov	s15, r3
+ 800a3d0:	eef8 6a67 	vcvt.f32.u32	s13, s15
+ 800a3d4:	ed97 6a03 	vldr	s12, [r7, #12]
+ 800a3d8:	eddf 5a55 	vldr	s11, [pc, #340]	; 800a530 <HAL_RCCEx_GetPLL1ClockFreq+0x294>
+ 800a3dc:	eec6 7a25 	vdiv.f32	s15, s12, s11
+ 800a3e0:	ee76 7aa7 	vadd.f32	s15, s13, s15
+ 800a3e4:	eef7 6a00 	vmov.f32	s13, #112	; 0x3f800000  1.0
+ 800a3e8:	ee77 7aa6 	vadd.f32	s15, s15, s13
+ 800a3ec:	ee67 7a27 	vmul.f32	s15, s14, s15
+ 800a3f0:	edc7 7a07 	vstr	s15, [r7, #28]
+        break;
+ 800a3f4:	e043      	b.n	800a47e <HAL_RCCEx_GetPLL1ClockFreq+0x1e2>
+
+      case RCC_PLLSOURCE_HSE:  /* HSE used as PLL clock source */
+        pll1vco = ((float_t)HSE_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
+ 800a3f6:	697b      	ldr	r3, [r7, #20]
+ 800a3f8:	ee07 3a90 	vmov	s15, r3
+ 800a3fc:	eef8 7a67 	vcvt.f32.u32	s15, s15
+ 800a400:	eddf 6a4e 	vldr	s13, [pc, #312]	; 800a53c <HAL_RCCEx_GetPLL1ClockFreq+0x2a0>
+ 800a404:	ee86 7aa7 	vdiv.f32	s14, s13, s15
+ 800a408:	4b47      	ldr	r3, [pc, #284]	; (800a528 <HAL_RCCEx_GetPLL1ClockFreq+0x28c>)
+ 800a40a:	6b1b      	ldr	r3, [r3, #48]	; 0x30
+ 800a40c:	f3c3 0308 	ubfx	r3, r3, #0, #9
+ 800a410:	ee07 3a90 	vmov	s15, r3
+ 800a414:	eef8 6a67 	vcvt.f32.u32	s13, s15
+ 800a418:	ed97 6a03 	vldr	s12, [r7, #12]
+ 800a41c:	eddf 5a44 	vldr	s11, [pc, #272]	; 800a530 <HAL_RCCEx_GetPLL1ClockFreq+0x294>
+ 800a420:	eec6 7a25 	vdiv.f32	s15, s12, s11
+ 800a424:	ee76 7aa7 	vadd.f32	s15, s13, s15
+ 800a428:	eef7 6a00 	vmov.f32	s13, #112	; 0x3f800000  1.0
+ 800a42c:	ee77 7aa6 	vadd.f32	s15, s15, s13
+ 800a430:	ee67 7a27 	vmul.f32	s15, s14, s15
+ 800a434:	edc7 7a07 	vstr	s15, [r7, #28]
+        break;
+ 800a438:	e021      	b.n	800a47e <HAL_RCCEx_GetPLL1ClockFreq+0x1e2>
+
+      default:
+        pll1vco = ((float_t)HSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
+ 800a43a:	697b      	ldr	r3, [r7, #20]
+ 800a43c:	ee07 3a90 	vmov	s15, r3
+ 800a440:	eef8 7a67 	vcvt.f32.u32	s15, s15
+ 800a444:	eddf 6a3b 	vldr	s13, [pc, #236]	; 800a534 <HAL_RCCEx_GetPLL1ClockFreq+0x298>
+ 800a448:	ee86 7aa7 	vdiv.f32	s14, s13, s15
+ 800a44c:	4b36      	ldr	r3, [pc, #216]	; (800a528 <HAL_RCCEx_GetPLL1ClockFreq+0x28c>)
+ 800a44e:	6b1b      	ldr	r3, [r3, #48]	; 0x30
+ 800a450:	f3c3 0308 	ubfx	r3, r3, #0, #9
+ 800a454:	ee07 3a90 	vmov	s15, r3
+ 800a458:	eef8 6a67 	vcvt.f32.u32	s13, s15
+ 800a45c:	ed97 6a03 	vldr	s12, [r7, #12]
+ 800a460:	eddf 5a33 	vldr	s11, [pc, #204]	; 800a530 <HAL_RCCEx_GetPLL1ClockFreq+0x294>
+ 800a464:	eec6 7a25 	vdiv.f32	s15, s12, s11
+ 800a468:	ee76 7aa7 	vadd.f32	s15, s13, s15
+ 800a46c:	eef7 6a00 	vmov.f32	s13, #112	; 0x3f800000  1.0
+ 800a470:	ee77 7aa6 	vadd.f32	s15, s15, s13
+ 800a474:	ee67 7a27 	vmul.f32	s15, s14, s15
+ 800a478:	edc7 7a07 	vstr	s15, [r7, #28]
+        break;
+ 800a47c:	bf00      	nop
+    }
+
+    PLL1_Clocks->PLL1_P_Frequency = (uint32_t)(float_t)(pll1vco / ((float_t)(uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >> 9)  + (float_t)1)) ;
+ 800a47e:	4b2a      	ldr	r3, [pc, #168]	; (800a528 <HAL_RCCEx_GetPLL1ClockFreq+0x28c>)
+ 800a480:	6b1b      	ldr	r3, [r3, #48]	; 0x30
+ 800a482:	0a5b      	lsrs	r3, r3, #9
+ 800a484:	f003 037f 	and.w	r3, r3, #127	; 0x7f
+ 800a488:	ee07 3a90 	vmov	s15, r3
+ 800a48c:	eef8 7a67 	vcvt.f32.u32	s15, s15
+ 800a490:	eeb7 7a00 	vmov.f32	s14, #112	; 0x3f800000  1.0
+ 800a494:	ee37 7a87 	vadd.f32	s14, s15, s14
+ 800a498:	edd7 6a07 	vldr	s13, [r7, #28]
+ 800a49c:	eec6 7a87 	vdiv.f32	s15, s13, s14
+ 800a4a0:	eefc 7ae7 	vcvt.u32.f32	s15, s15
+ 800a4a4:	ee17 2a90 	vmov	r2, s15
+ 800a4a8:	687b      	ldr	r3, [r7, #4]
+ 800a4aa:	601a      	str	r2, [r3, #0]
+    PLL1_Clocks->PLL1_Q_Frequency = (uint32_t)(float_t)(pll1vco / ((float_t)(uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_Q1) >> 16) + (float_t)1)) ;
+ 800a4ac:	4b1e      	ldr	r3, [pc, #120]	; (800a528 <HAL_RCCEx_GetPLL1ClockFreq+0x28c>)
+ 800a4ae:	6b1b      	ldr	r3, [r3, #48]	; 0x30
+ 800a4b0:	0c1b      	lsrs	r3, r3, #16
+ 800a4b2:	f003 037f 	and.w	r3, r3, #127	; 0x7f
+ 800a4b6:	ee07 3a90 	vmov	s15, r3
+ 800a4ba:	eef8 7a67 	vcvt.f32.u32	s15, s15
+ 800a4be:	eeb7 7a00 	vmov.f32	s14, #112	; 0x3f800000  1.0
+ 800a4c2:	ee37 7a87 	vadd.f32	s14, s15, s14
+ 800a4c6:	edd7 6a07 	vldr	s13, [r7, #28]
+ 800a4ca:	eec6 7a87 	vdiv.f32	s15, s13, s14
+ 800a4ce:	eefc 7ae7 	vcvt.u32.f32	s15, s15
+ 800a4d2:	ee17 2a90 	vmov	r2, s15
+ 800a4d6:	687b      	ldr	r3, [r7, #4]
+ 800a4d8:	605a      	str	r2, [r3, #4]
+    PLL1_Clocks->PLL1_R_Frequency = (uint32_t)(float_t)(pll1vco / ((float_t)(uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_R1) >> 24) + (float_t)1)) ;
+ 800a4da:	4b13      	ldr	r3, [pc, #76]	; (800a528 <HAL_RCCEx_GetPLL1ClockFreq+0x28c>)
+ 800a4dc:	6b1b      	ldr	r3, [r3, #48]	; 0x30
+ 800a4de:	0e1b      	lsrs	r3, r3, #24
+ 800a4e0:	f003 037f 	and.w	r3, r3, #127	; 0x7f
+ 800a4e4:	ee07 3a90 	vmov	s15, r3
+ 800a4e8:	eef8 7a67 	vcvt.f32.u32	s15, s15
+ 800a4ec:	eeb7 7a00 	vmov.f32	s14, #112	; 0x3f800000  1.0
+ 800a4f0:	ee37 7a87 	vadd.f32	s14, s15, s14
+ 800a4f4:	edd7 6a07 	vldr	s13, [r7, #28]
+ 800a4f8:	eec6 7a87 	vdiv.f32	s15, s13, s14
+ 800a4fc:	eefc 7ae7 	vcvt.u32.f32	s15, s15
+ 800a500:	ee17 2a90 	vmov	r2, s15
+ 800a504:	687b      	ldr	r3, [r7, #4]
+ 800a506:	609a      	str	r2, [r3, #8]
+    PLL1_Clocks->PLL1_P_Frequency = 0U;
+    PLL1_Clocks->PLL1_Q_Frequency = 0U;
+    PLL1_Clocks->PLL1_R_Frequency = 0U;
+  }
+
+}
+ 800a508:	e008      	b.n	800a51c <HAL_RCCEx_GetPLL1ClockFreq+0x280>
+    PLL1_Clocks->PLL1_P_Frequency = 0U;
+ 800a50a:	687b      	ldr	r3, [r7, #4]
+ 800a50c:	2200      	movs	r2, #0
+ 800a50e:	601a      	str	r2, [r3, #0]
+    PLL1_Clocks->PLL1_Q_Frequency = 0U;
+ 800a510:	687b      	ldr	r3, [r7, #4]
+ 800a512:	2200      	movs	r2, #0
+ 800a514:	605a      	str	r2, [r3, #4]
+    PLL1_Clocks->PLL1_R_Frequency = 0U;
+ 800a516:	687b      	ldr	r3, [r7, #4]
+ 800a518:	2200      	movs	r2, #0
+ 800a51a:	609a      	str	r2, [r3, #8]
+}
+ 800a51c:	bf00      	nop
+ 800a51e:	3724      	adds	r7, #36	; 0x24
+ 800a520:	46bd      	mov	sp, r7
+ 800a522:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 800a526:	4770      	bx	lr
+ 800a528:	58024400 	.word	0x58024400
+ 800a52c:	03d09000 	.word	0x03d09000
+ 800a530:	46000000 	.word	0x46000000
+ 800a534:	4c742400 	.word	0x4c742400
+ 800a538:	4a742400 	.word	0x4a742400
+ 800a53c:	4bbebc20 	.word	0x4bbebc20
+
+0800a540 <RCCEx_PLL2_Config>:
+  * @note   PLL2 is temporary disabled to apply new parameters
+  *
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef RCCEx_PLL2_Config(RCC_PLL2InitTypeDef *pll2, uint32_t Divider)
+{
+ 800a540:	b580      	push	{r7, lr}
+ 800a542:	b084      	sub	sp, #16
+ 800a544:	af00      	add	r7, sp, #0
+ 800a546:	6078      	str	r0, [r7, #4]
+ 800a548:	6039      	str	r1, [r7, #0]
+
+  uint32_t tickstart;
+  HAL_StatusTypeDef status = HAL_OK;
+ 800a54a:	2300      	movs	r3, #0
+ 800a54c:	73fb      	strb	r3, [r7, #15]
+  assert_param(IS_RCC_PLL2RGE_VALUE(pll2->PLL2RGE));
+  assert_param(IS_RCC_PLL2VCO_VALUE(pll2->PLL2VCOSEL));
+  assert_param(IS_RCC_PLLFRACN_VALUE(pll2->PLL2FRACN));
+
+  /* Check that PLL2 OSC clock source is already set */
+  if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE)
+ 800a54e:	4b53      	ldr	r3, [pc, #332]	; (800a69c <RCCEx_PLL2_Config+0x15c>)
+ 800a550:	6a9b      	ldr	r3, [r3, #40]	; 0x28
+ 800a552:	f003 0303 	and.w	r3, r3, #3
+ 800a556:	2b03      	cmp	r3, #3
+ 800a558:	d101      	bne.n	800a55e <RCCEx_PLL2_Config+0x1e>
+  {
+    return HAL_ERROR;
+ 800a55a:	2301      	movs	r3, #1
+ 800a55c:	e099      	b.n	800a692 <RCCEx_PLL2_Config+0x152>
+
+
+  else
+  {
+    /* Disable  PLL2. */
+    __HAL_RCC_PLL2_DISABLE();
+ 800a55e:	4b4f      	ldr	r3, [pc, #316]	; (800a69c <RCCEx_PLL2_Config+0x15c>)
+ 800a560:	681b      	ldr	r3, [r3, #0]
+ 800a562:	4a4e      	ldr	r2, [pc, #312]	; (800a69c <RCCEx_PLL2_Config+0x15c>)
+ 800a564:	f023 6380 	bic.w	r3, r3, #67108864	; 0x4000000
+ 800a568:	6013      	str	r3, [r2, #0]
+
+    /* Get Start Tick*/
+    tickstart = HAL_GetTick();
+ 800a56a:	f7f7 fefb 	bl	8002364 <HAL_GetTick>
+ 800a56e:	60b8      	str	r0, [r7, #8]
+
+    /* Wait till PLL is disabled */
+    while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != 0U)
+ 800a570:	e008      	b.n	800a584 <RCCEx_PLL2_Config+0x44>
+    {
+      if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE)
+ 800a572:	f7f7 fef7 	bl	8002364 <HAL_GetTick>
+ 800a576:	4602      	mov	r2, r0
+ 800a578:	68bb      	ldr	r3, [r7, #8]
+ 800a57a:	1ad3      	subs	r3, r2, r3
+ 800a57c:	2b02      	cmp	r3, #2
+ 800a57e:	d901      	bls.n	800a584 <RCCEx_PLL2_Config+0x44>
+      {
+        return HAL_TIMEOUT;
+ 800a580:	2303      	movs	r3, #3
+ 800a582:	e086      	b.n	800a692 <RCCEx_PLL2_Config+0x152>
+    while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != 0U)
+ 800a584:	4b45      	ldr	r3, [pc, #276]	; (800a69c <RCCEx_PLL2_Config+0x15c>)
+ 800a586:	681b      	ldr	r3, [r3, #0]
+ 800a588:	f003 6300 	and.w	r3, r3, #134217728	; 0x8000000
+ 800a58c:	2b00      	cmp	r3, #0
+ 800a58e:	d1f0      	bne.n	800a572 <RCCEx_PLL2_Config+0x32>
+      }
+    }
+
+    /* Configure PLL2 multiplication and division factors. */
+    __HAL_RCC_PLL2_CONFIG(pll2->PLL2M,
+ 800a590:	4b42      	ldr	r3, [pc, #264]	; (800a69c <RCCEx_PLL2_Config+0x15c>)
+ 800a592:	6a9b      	ldr	r3, [r3, #40]	; 0x28
+ 800a594:	f423 327c 	bic.w	r2, r3, #258048	; 0x3f000
+ 800a598:	687b      	ldr	r3, [r7, #4]
+ 800a59a:	681b      	ldr	r3, [r3, #0]
+ 800a59c:	031b      	lsls	r3, r3, #12
+ 800a59e:	493f      	ldr	r1, [pc, #252]	; (800a69c <RCCEx_PLL2_Config+0x15c>)
+ 800a5a0:	4313      	orrs	r3, r2
+ 800a5a2:	628b      	str	r3, [r1, #40]	; 0x28
+ 800a5a4:	687b      	ldr	r3, [r7, #4]
+ 800a5a6:	685b      	ldr	r3, [r3, #4]
+ 800a5a8:	3b01      	subs	r3, #1
+ 800a5aa:	f3c3 0208 	ubfx	r2, r3, #0, #9
+ 800a5ae:	687b      	ldr	r3, [r7, #4]
+ 800a5b0:	689b      	ldr	r3, [r3, #8]
+ 800a5b2:	3b01      	subs	r3, #1
+ 800a5b4:	025b      	lsls	r3, r3, #9
+ 800a5b6:	b29b      	uxth	r3, r3
+ 800a5b8:	431a      	orrs	r2, r3
+ 800a5ba:	687b      	ldr	r3, [r7, #4]
+ 800a5bc:	68db      	ldr	r3, [r3, #12]
+ 800a5be:	3b01      	subs	r3, #1
+ 800a5c0:	041b      	lsls	r3, r3, #16
+ 800a5c2:	f403 03fe 	and.w	r3, r3, #8323072	; 0x7f0000
+ 800a5c6:	431a      	orrs	r2, r3
+ 800a5c8:	687b      	ldr	r3, [r7, #4]
+ 800a5ca:	691b      	ldr	r3, [r3, #16]
+ 800a5cc:	3b01      	subs	r3, #1
+ 800a5ce:	061b      	lsls	r3, r3, #24
+ 800a5d0:	f003 43fe 	and.w	r3, r3, #2130706432	; 0x7f000000
+ 800a5d4:	4931      	ldr	r1, [pc, #196]	; (800a69c <RCCEx_PLL2_Config+0x15c>)
+ 800a5d6:	4313      	orrs	r3, r2
+ 800a5d8:	638b      	str	r3, [r1, #56]	; 0x38
+                          pll2->PLL2P,
+                          pll2->PLL2Q,
+                          pll2->PLL2R);
+
+    /* Select PLL2 input reference frequency range: VCI */
+    __HAL_RCC_PLL2_VCIRANGE(pll2->PLL2RGE) ;
+ 800a5da:	4b30      	ldr	r3, [pc, #192]	; (800a69c <RCCEx_PLL2_Config+0x15c>)
+ 800a5dc:	6adb      	ldr	r3, [r3, #44]	; 0x2c
+ 800a5de:	f023 02c0 	bic.w	r2, r3, #192	; 0xc0
+ 800a5e2:	687b      	ldr	r3, [r7, #4]
+ 800a5e4:	695b      	ldr	r3, [r3, #20]
+ 800a5e6:	492d      	ldr	r1, [pc, #180]	; (800a69c <RCCEx_PLL2_Config+0x15c>)
+ 800a5e8:	4313      	orrs	r3, r2
+ 800a5ea:	62cb      	str	r3, [r1, #44]	; 0x2c
+
+    /* Select PLL2 output frequency range : VCO */
+    __HAL_RCC_PLL2_VCORANGE(pll2->PLL2VCOSEL) ;
+ 800a5ec:	4b2b      	ldr	r3, [pc, #172]	; (800a69c <RCCEx_PLL2_Config+0x15c>)
+ 800a5ee:	6adb      	ldr	r3, [r3, #44]	; 0x2c
+ 800a5f0:	f023 0220 	bic.w	r2, r3, #32
+ 800a5f4:	687b      	ldr	r3, [r7, #4]
+ 800a5f6:	699b      	ldr	r3, [r3, #24]
+ 800a5f8:	4928      	ldr	r1, [pc, #160]	; (800a69c <RCCEx_PLL2_Config+0x15c>)
+ 800a5fa:	4313      	orrs	r3, r2
+ 800a5fc:	62cb      	str	r3, [r1, #44]	; 0x2c
+
+    /* Disable PLL2FRACN . */
+    __HAL_RCC_PLL2FRACN_DISABLE();
+ 800a5fe:	4b27      	ldr	r3, [pc, #156]	; (800a69c <RCCEx_PLL2_Config+0x15c>)
+ 800a600:	6adb      	ldr	r3, [r3, #44]	; 0x2c
+ 800a602:	4a26      	ldr	r2, [pc, #152]	; (800a69c <RCCEx_PLL2_Config+0x15c>)
+ 800a604:	f023 0310 	bic.w	r3, r3, #16
+ 800a608:	62d3      	str	r3, [r2, #44]	; 0x2c
+
+    /* Configures PLL2 clock Fractional Part Of The Multiplication Factor */
+    __HAL_RCC_PLL2FRACN_CONFIG(pll2->PLL2FRACN);
+ 800a60a:	4b24      	ldr	r3, [pc, #144]	; (800a69c <RCCEx_PLL2_Config+0x15c>)
+ 800a60c:	6bda      	ldr	r2, [r3, #60]	; 0x3c
+ 800a60e:	4b24      	ldr	r3, [pc, #144]	; (800a6a0 <RCCEx_PLL2_Config+0x160>)
+ 800a610:	4013      	ands	r3, r2
+ 800a612:	687a      	ldr	r2, [r7, #4]
+ 800a614:	69d2      	ldr	r2, [r2, #28]
+ 800a616:	00d2      	lsls	r2, r2, #3
+ 800a618:	4920      	ldr	r1, [pc, #128]	; (800a69c <RCCEx_PLL2_Config+0x15c>)
+ 800a61a:	4313      	orrs	r3, r2
+ 800a61c:	63cb      	str	r3, [r1, #60]	; 0x3c
+
+    /* Enable PLL2FRACN . */
+    __HAL_RCC_PLL2FRACN_ENABLE();
+ 800a61e:	4b1f      	ldr	r3, [pc, #124]	; (800a69c <RCCEx_PLL2_Config+0x15c>)
+ 800a620:	6adb      	ldr	r3, [r3, #44]	; 0x2c
+ 800a622:	4a1e      	ldr	r2, [pc, #120]	; (800a69c <RCCEx_PLL2_Config+0x15c>)
+ 800a624:	f043 0310 	orr.w	r3, r3, #16
+ 800a628:	62d3      	str	r3, [r2, #44]	; 0x2c
+
+    /* Enable the PLL2 clock output */
+    if (Divider == DIVIDER_P_UPDATE)
+ 800a62a:	683b      	ldr	r3, [r7, #0]
+ 800a62c:	2b00      	cmp	r3, #0
+ 800a62e:	d106      	bne.n	800a63e <RCCEx_PLL2_Config+0xfe>
+    {
+      __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVP);
+ 800a630:	4b1a      	ldr	r3, [pc, #104]	; (800a69c <RCCEx_PLL2_Config+0x15c>)
+ 800a632:	6adb      	ldr	r3, [r3, #44]	; 0x2c
+ 800a634:	4a19      	ldr	r2, [pc, #100]	; (800a69c <RCCEx_PLL2_Config+0x15c>)
+ 800a636:	f443 2300 	orr.w	r3, r3, #524288	; 0x80000
+ 800a63a:	62d3      	str	r3, [r2, #44]	; 0x2c
+ 800a63c:	e00f      	b.n	800a65e <RCCEx_PLL2_Config+0x11e>
+    }
+    else if (Divider == DIVIDER_Q_UPDATE)
+ 800a63e:	683b      	ldr	r3, [r7, #0]
+ 800a640:	2b01      	cmp	r3, #1
+ 800a642:	d106      	bne.n	800a652 <RCCEx_PLL2_Config+0x112>
+    {
+      __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVQ);
+ 800a644:	4b15      	ldr	r3, [pc, #84]	; (800a69c <RCCEx_PLL2_Config+0x15c>)
+ 800a646:	6adb      	ldr	r3, [r3, #44]	; 0x2c
+ 800a648:	4a14      	ldr	r2, [pc, #80]	; (800a69c <RCCEx_PLL2_Config+0x15c>)
+ 800a64a:	f443 1380 	orr.w	r3, r3, #1048576	; 0x100000
+ 800a64e:	62d3      	str	r3, [r2, #44]	; 0x2c
+ 800a650:	e005      	b.n	800a65e <RCCEx_PLL2_Config+0x11e>
+    }
+    else
+    {
+      __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVR);
+ 800a652:	4b12      	ldr	r3, [pc, #72]	; (800a69c <RCCEx_PLL2_Config+0x15c>)
+ 800a654:	6adb      	ldr	r3, [r3, #44]	; 0x2c
+ 800a656:	4a11      	ldr	r2, [pc, #68]	; (800a69c <RCCEx_PLL2_Config+0x15c>)
+ 800a658:	f443 1300 	orr.w	r3, r3, #2097152	; 0x200000
+ 800a65c:	62d3      	str	r3, [r2, #44]	; 0x2c
+    }
+
+    /* Enable  PLL2. */
+    __HAL_RCC_PLL2_ENABLE();
+ 800a65e:	4b0f      	ldr	r3, [pc, #60]	; (800a69c <RCCEx_PLL2_Config+0x15c>)
+ 800a660:	681b      	ldr	r3, [r3, #0]
+ 800a662:	4a0e      	ldr	r2, [pc, #56]	; (800a69c <RCCEx_PLL2_Config+0x15c>)
+ 800a664:	f043 6380 	orr.w	r3, r3, #67108864	; 0x4000000
+ 800a668:	6013      	str	r3, [r2, #0]
+
+    /* Get Start Tick*/
+    tickstart = HAL_GetTick();
+ 800a66a:	f7f7 fe7b 	bl	8002364 <HAL_GetTick>
+ 800a66e:	60b8      	str	r0, [r7, #8]
+
+    /* Wait till PLL2 is ready */
+    while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == 0U)
+ 800a670:	e008      	b.n	800a684 <RCCEx_PLL2_Config+0x144>
+    {
+      if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE)
+ 800a672:	f7f7 fe77 	bl	8002364 <HAL_GetTick>
+ 800a676:	4602      	mov	r2, r0
+ 800a678:	68bb      	ldr	r3, [r7, #8]
+ 800a67a:	1ad3      	subs	r3, r2, r3
+ 800a67c:	2b02      	cmp	r3, #2
+ 800a67e:	d901      	bls.n	800a684 <RCCEx_PLL2_Config+0x144>
+      {
+        return HAL_TIMEOUT;
+ 800a680:	2303      	movs	r3, #3
+ 800a682:	e006      	b.n	800a692 <RCCEx_PLL2_Config+0x152>
+    while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == 0U)
+ 800a684:	4b05      	ldr	r3, [pc, #20]	; (800a69c <RCCEx_PLL2_Config+0x15c>)
+ 800a686:	681b      	ldr	r3, [r3, #0]
+ 800a688:	f003 6300 	and.w	r3, r3, #134217728	; 0x8000000
+ 800a68c:	2b00      	cmp	r3, #0
+ 800a68e:	d0f0      	beq.n	800a672 <RCCEx_PLL2_Config+0x132>
+    }
+
+  }
+
+
+  return status;
+ 800a690:	7bfb      	ldrb	r3, [r7, #15]
+}
+ 800a692:	4618      	mov	r0, r3
+ 800a694:	3710      	adds	r7, #16
+ 800a696:	46bd      	mov	sp, r7
+ 800a698:	bd80      	pop	{r7, pc}
+ 800a69a:	bf00      	nop
+ 800a69c:	58024400 	.word	0x58024400
+ 800a6a0:	ffff0007 	.word	0xffff0007
+
+0800a6a4 <RCCEx_PLL3_Config>:
+  * @note   PLL3 is temporary disabled to apply new parameters
+  *
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef RCCEx_PLL3_Config(RCC_PLL3InitTypeDef *pll3, uint32_t Divider)
+{
+ 800a6a4:	b580      	push	{r7, lr}
+ 800a6a6:	b084      	sub	sp, #16
+ 800a6a8:	af00      	add	r7, sp, #0
+ 800a6aa:	6078      	str	r0, [r7, #4]
+ 800a6ac:	6039      	str	r1, [r7, #0]
+  uint32_t tickstart;
+  HAL_StatusTypeDef status = HAL_OK;
+ 800a6ae:	2300      	movs	r3, #0
+ 800a6b0:	73fb      	strb	r3, [r7, #15]
+  assert_param(IS_RCC_PLL3RGE_VALUE(pll3->PLL3RGE));
+  assert_param(IS_RCC_PLL3VCO_VALUE(pll3->PLL3VCOSEL));
+  assert_param(IS_RCC_PLLFRACN_VALUE(pll3->PLL3FRACN));
+
+  /* Check that PLL3 OSC clock source is already set */
+  if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE)
+ 800a6b2:	4b53      	ldr	r3, [pc, #332]	; (800a800 <RCCEx_PLL3_Config+0x15c>)
+ 800a6b4:	6a9b      	ldr	r3, [r3, #40]	; 0x28
+ 800a6b6:	f003 0303 	and.w	r3, r3, #3
+ 800a6ba:	2b03      	cmp	r3, #3
+ 800a6bc:	d101      	bne.n	800a6c2 <RCCEx_PLL3_Config+0x1e>
+  {
+    return HAL_ERROR;
+ 800a6be:	2301      	movs	r3, #1
+ 800a6c0:	e099      	b.n	800a7f6 <RCCEx_PLL3_Config+0x152>
+
+
+  else
+  {
+    /* Disable  PLL3. */
+    __HAL_RCC_PLL3_DISABLE();
+ 800a6c2:	4b4f      	ldr	r3, [pc, #316]	; (800a800 <RCCEx_PLL3_Config+0x15c>)
+ 800a6c4:	681b      	ldr	r3, [r3, #0]
+ 800a6c6:	4a4e      	ldr	r2, [pc, #312]	; (800a800 <RCCEx_PLL3_Config+0x15c>)
+ 800a6c8:	f023 5380 	bic.w	r3, r3, #268435456	; 0x10000000
+ 800a6cc:	6013      	str	r3, [r2, #0]
+
+    /* Get Start Tick*/
+    tickstart = HAL_GetTick();
+ 800a6ce:	f7f7 fe49 	bl	8002364 <HAL_GetTick>
+ 800a6d2:	60b8      	str	r0, [r7, #8]
+    /* Wait till PLL3 is ready */
+    while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) != 0U)
+ 800a6d4:	e008      	b.n	800a6e8 <RCCEx_PLL3_Config+0x44>
+    {
+      if ((HAL_GetTick() - tickstart) > PLL3_TIMEOUT_VALUE)
+ 800a6d6:	f7f7 fe45 	bl	8002364 <HAL_GetTick>
+ 800a6da:	4602      	mov	r2, r0
+ 800a6dc:	68bb      	ldr	r3, [r7, #8]
+ 800a6de:	1ad3      	subs	r3, r2, r3
+ 800a6e0:	2b02      	cmp	r3, #2
+ 800a6e2:	d901      	bls.n	800a6e8 <RCCEx_PLL3_Config+0x44>
+      {
+        return HAL_TIMEOUT;
+ 800a6e4:	2303      	movs	r3, #3
+ 800a6e6:	e086      	b.n	800a7f6 <RCCEx_PLL3_Config+0x152>
+    while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) != 0U)
+ 800a6e8:	4b45      	ldr	r3, [pc, #276]	; (800a800 <RCCEx_PLL3_Config+0x15c>)
+ 800a6ea:	681b      	ldr	r3, [r3, #0]
+ 800a6ec:	f003 5300 	and.w	r3, r3, #536870912	; 0x20000000
+ 800a6f0:	2b00      	cmp	r3, #0
+ 800a6f2:	d1f0      	bne.n	800a6d6 <RCCEx_PLL3_Config+0x32>
+      }
+    }
+
+    /* Configure the PLL3  multiplication and division factors. */
+    __HAL_RCC_PLL3_CONFIG(pll3->PLL3M,
+ 800a6f4:	4b42      	ldr	r3, [pc, #264]	; (800a800 <RCCEx_PLL3_Config+0x15c>)
+ 800a6f6:	6a9b      	ldr	r3, [r3, #40]	; 0x28
+ 800a6f8:	f023 727c 	bic.w	r2, r3, #66060288	; 0x3f00000
+ 800a6fc:	687b      	ldr	r3, [r7, #4]
+ 800a6fe:	681b      	ldr	r3, [r3, #0]
+ 800a700:	051b      	lsls	r3, r3, #20
+ 800a702:	493f      	ldr	r1, [pc, #252]	; (800a800 <RCCEx_PLL3_Config+0x15c>)
+ 800a704:	4313      	orrs	r3, r2
+ 800a706:	628b      	str	r3, [r1, #40]	; 0x28
+ 800a708:	687b      	ldr	r3, [r7, #4]
+ 800a70a:	685b      	ldr	r3, [r3, #4]
+ 800a70c:	3b01      	subs	r3, #1
+ 800a70e:	f3c3 0208 	ubfx	r2, r3, #0, #9
+ 800a712:	687b      	ldr	r3, [r7, #4]
+ 800a714:	689b      	ldr	r3, [r3, #8]
+ 800a716:	3b01      	subs	r3, #1
+ 800a718:	025b      	lsls	r3, r3, #9
+ 800a71a:	b29b      	uxth	r3, r3
+ 800a71c:	431a      	orrs	r2, r3
+ 800a71e:	687b      	ldr	r3, [r7, #4]
+ 800a720:	68db      	ldr	r3, [r3, #12]
+ 800a722:	3b01      	subs	r3, #1
+ 800a724:	041b      	lsls	r3, r3, #16
+ 800a726:	f403 03fe 	and.w	r3, r3, #8323072	; 0x7f0000
+ 800a72a:	431a      	orrs	r2, r3
+ 800a72c:	687b      	ldr	r3, [r7, #4]
+ 800a72e:	691b      	ldr	r3, [r3, #16]
+ 800a730:	3b01      	subs	r3, #1
+ 800a732:	061b      	lsls	r3, r3, #24
+ 800a734:	f003 43fe 	and.w	r3, r3, #2130706432	; 0x7f000000
+ 800a738:	4931      	ldr	r1, [pc, #196]	; (800a800 <RCCEx_PLL3_Config+0x15c>)
+ 800a73a:	4313      	orrs	r3, r2
+ 800a73c:	640b      	str	r3, [r1, #64]	; 0x40
+                          pll3->PLL3P,
+                          pll3->PLL3Q,
+                          pll3->PLL3R);
+
+    /* Select PLL3 input reference frequency range: VCI */
+    __HAL_RCC_PLL3_VCIRANGE(pll3->PLL3RGE) ;
+ 800a73e:	4b30      	ldr	r3, [pc, #192]	; (800a800 <RCCEx_PLL3_Config+0x15c>)
+ 800a740:	6adb      	ldr	r3, [r3, #44]	; 0x2c
+ 800a742:	f423 6240 	bic.w	r2, r3, #3072	; 0xc00
+ 800a746:	687b      	ldr	r3, [r7, #4]
+ 800a748:	695b      	ldr	r3, [r3, #20]
+ 800a74a:	492d      	ldr	r1, [pc, #180]	; (800a800 <RCCEx_PLL3_Config+0x15c>)
+ 800a74c:	4313      	orrs	r3, r2
+ 800a74e:	62cb      	str	r3, [r1, #44]	; 0x2c
+
+    /* Select PLL3 output frequency range : VCO */
+    __HAL_RCC_PLL3_VCORANGE(pll3->PLL3VCOSEL) ;
+ 800a750:	4b2b      	ldr	r3, [pc, #172]	; (800a800 <RCCEx_PLL3_Config+0x15c>)
+ 800a752:	6adb      	ldr	r3, [r3, #44]	; 0x2c
+ 800a754:	f423 7200 	bic.w	r2, r3, #512	; 0x200
+ 800a758:	687b      	ldr	r3, [r7, #4]
+ 800a75a:	699b      	ldr	r3, [r3, #24]
+ 800a75c:	4928      	ldr	r1, [pc, #160]	; (800a800 <RCCEx_PLL3_Config+0x15c>)
+ 800a75e:	4313      	orrs	r3, r2
+ 800a760:	62cb      	str	r3, [r1, #44]	; 0x2c
+
+    /* Disable PLL3FRACN . */
+    __HAL_RCC_PLL3FRACN_DISABLE();
+ 800a762:	4b27      	ldr	r3, [pc, #156]	; (800a800 <RCCEx_PLL3_Config+0x15c>)
+ 800a764:	6adb      	ldr	r3, [r3, #44]	; 0x2c
+ 800a766:	4a26      	ldr	r2, [pc, #152]	; (800a800 <RCCEx_PLL3_Config+0x15c>)
+ 800a768:	f423 7380 	bic.w	r3, r3, #256	; 0x100
+ 800a76c:	62d3      	str	r3, [r2, #44]	; 0x2c
+
+    /* Configures PLL3 clock Fractional Part Of The Multiplication Factor */
+    __HAL_RCC_PLL3FRACN_CONFIG(pll3->PLL3FRACN);
+ 800a76e:	4b24      	ldr	r3, [pc, #144]	; (800a800 <RCCEx_PLL3_Config+0x15c>)
+ 800a770:	6c5a      	ldr	r2, [r3, #68]	; 0x44
+ 800a772:	4b24      	ldr	r3, [pc, #144]	; (800a804 <RCCEx_PLL3_Config+0x160>)
+ 800a774:	4013      	ands	r3, r2
+ 800a776:	687a      	ldr	r2, [r7, #4]
+ 800a778:	69d2      	ldr	r2, [r2, #28]
+ 800a77a:	00d2      	lsls	r2, r2, #3
+ 800a77c:	4920      	ldr	r1, [pc, #128]	; (800a800 <RCCEx_PLL3_Config+0x15c>)
+ 800a77e:	4313      	orrs	r3, r2
+ 800a780:	644b      	str	r3, [r1, #68]	; 0x44
+
+    /* Enable PLL3FRACN . */
+    __HAL_RCC_PLL3FRACN_ENABLE();
+ 800a782:	4b1f      	ldr	r3, [pc, #124]	; (800a800 <RCCEx_PLL3_Config+0x15c>)
+ 800a784:	6adb      	ldr	r3, [r3, #44]	; 0x2c
+ 800a786:	4a1e      	ldr	r2, [pc, #120]	; (800a800 <RCCEx_PLL3_Config+0x15c>)
+ 800a788:	f443 7380 	orr.w	r3, r3, #256	; 0x100
+ 800a78c:	62d3      	str	r3, [r2, #44]	; 0x2c
+
+    /* Enable the PLL3 clock output */
+    if (Divider == DIVIDER_P_UPDATE)
+ 800a78e:	683b      	ldr	r3, [r7, #0]
+ 800a790:	2b00      	cmp	r3, #0
+ 800a792:	d106      	bne.n	800a7a2 <RCCEx_PLL3_Config+0xfe>
+    {
+      __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVP);
+ 800a794:	4b1a      	ldr	r3, [pc, #104]	; (800a800 <RCCEx_PLL3_Config+0x15c>)
+ 800a796:	6adb      	ldr	r3, [r3, #44]	; 0x2c
+ 800a798:	4a19      	ldr	r2, [pc, #100]	; (800a800 <RCCEx_PLL3_Config+0x15c>)
+ 800a79a:	f443 0380 	orr.w	r3, r3, #4194304	; 0x400000
+ 800a79e:	62d3      	str	r3, [r2, #44]	; 0x2c
+ 800a7a0:	e00f      	b.n	800a7c2 <RCCEx_PLL3_Config+0x11e>
+    }
+    else if (Divider == DIVIDER_Q_UPDATE)
+ 800a7a2:	683b      	ldr	r3, [r7, #0]
+ 800a7a4:	2b01      	cmp	r3, #1
+ 800a7a6:	d106      	bne.n	800a7b6 <RCCEx_PLL3_Config+0x112>
+    {
+      __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVQ);
+ 800a7a8:	4b15      	ldr	r3, [pc, #84]	; (800a800 <RCCEx_PLL3_Config+0x15c>)
+ 800a7aa:	6adb      	ldr	r3, [r3, #44]	; 0x2c
+ 800a7ac:	4a14      	ldr	r2, [pc, #80]	; (800a800 <RCCEx_PLL3_Config+0x15c>)
+ 800a7ae:	f443 0300 	orr.w	r3, r3, #8388608	; 0x800000
+ 800a7b2:	62d3      	str	r3, [r2, #44]	; 0x2c
+ 800a7b4:	e005      	b.n	800a7c2 <RCCEx_PLL3_Config+0x11e>
+    }
+    else
+    {
+      __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVR);
+ 800a7b6:	4b12      	ldr	r3, [pc, #72]	; (800a800 <RCCEx_PLL3_Config+0x15c>)
+ 800a7b8:	6adb      	ldr	r3, [r3, #44]	; 0x2c
+ 800a7ba:	4a11      	ldr	r2, [pc, #68]	; (800a800 <RCCEx_PLL3_Config+0x15c>)
+ 800a7bc:	f043 7380 	orr.w	r3, r3, #16777216	; 0x1000000
+ 800a7c0:	62d3      	str	r3, [r2, #44]	; 0x2c
+    }
+
+    /* Enable  PLL3. */
+    __HAL_RCC_PLL3_ENABLE();
+ 800a7c2:	4b0f      	ldr	r3, [pc, #60]	; (800a800 <RCCEx_PLL3_Config+0x15c>)
+ 800a7c4:	681b      	ldr	r3, [r3, #0]
+ 800a7c6:	4a0e      	ldr	r2, [pc, #56]	; (800a800 <RCCEx_PLL3_Config+0x15c>)
+ 800a7c8:	f043 5380 	orr.w	r3, r3, #268435456	; 0x10000000
+ 800a7cc:	6013      	str	r3, [r2, #0]
+
+    /* Get Start Tick*/
+    tickstart = HAL_GetTick();
+ 800a7ce:	f7f7 fdc9 	bl	8002364 <HAL_GetTick>
+ 800a7d2:	60b8      	str	r0, [r7, #8]
+
+    /* Wait till PLL3 is ready */
+    while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) == 0U)
+ 800a7d4:	e008      	b.n	800a7e8 <RCCEx_PLL3_Config+0x144>
+    {
+      if ((HAL_GetTick() - tickstart) > PLL3_TIMEOUT_VALUE)
+ 800a7d6:	f7f7 fdc5 	bl	8002364 <HAL_GetTick>
+ 800a7da:	4602      	mov	r2, r0
+ 800a7dc:	68bb      	ldr	r3, [r7, #8]
+ 800a7de:	1ad3      	subs	r3, r2, r3
+ 800a7e0:	2b02      	cmp	r3, #2
+ 800a7e2:	d901      	bls.n	800a7e8 <RCCEx_PLL3_Config+0x144>
+      {
+        return HAL_TIMEOUT;
+ 800a7e4:	2303      	movs	r3, #3
+ 800a7e6:	e006      	b.n	800a7f6 <RCCEx_PLL3_Config+0x152>
+    while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) == 0U)
+ 800a7e8:	4b05      	ldr	r3, [pc, #20]	; (800a800 <RCCEx_PLL3_Config+0x15c>)
+ 800a7ea:	681b      	ldr	r3, [r3, #0]
+ 800a7ec:	f003 5300 	and.w	r3, r3, #536870912	; 0x20000000
+ 800a7f0:	2b00      	cmp	r3, #0
+ 800a7f2:	d0f0      	beq.n	800a7d6 <RCCEx_PLL3_Config+0x132>
+    }
+
+  }
+
+
+  return status;
+ 800a7f4:	7bfb      	ldrb	r3, [r7, #15]
+}
+ 800a7f6:	4618      	mov	r0, r3
+ 800a7f8:	3710      	adds	r7, #16
+ 800a7fa:	46bd      	mov	sp, r7
+ 800a7fc:	bd80      	pop	{r7, pc}
+ 800a7fe:	bf00      	nop
+ 800a800:	58024400 	.word	0x58024400
+ 800a804:	ffff0007 	.word	0xffff0007
+
+0800a808 <HAL_SD_Init>:
+            SD_HandleTypeDef and create the associated handle.
+  * @param  hsd: Pointer to the SD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SD_Init(SD_HandleTypeDef *hsd)
+{
+ 800a808:	b580      	push	{r7, lr}
+ 800a80a:	b08a      	sub	sp, #40	; 0x28
+ 800a80c:	af00      	add	r7, sp, #0
+ 800a80e:	6078      	str	r0, [r7, #4]
+  uint32_t speedgrade;
+  uint32_t unitsize;
+  uint32_t tickstart;
+
+  /* Check the SD handle allocation */
+  if (hsd == NULL)
+ 800a810:	687b      	ldr	r3, [r7, #4]
+ 800a812:	2b00      	cmp	r3, #0
+ 800a814:	d101      	bne.n	800a81a <HAL_SD_Init+0x12>
+  {
+    return HAL_ERROR;
+ 800a816:	2301      	movs	r3, #1
+ 800a818:	e075      	b.n	800a906 <HAL_SD_Init+0xfe>
+  assert_param(IS_SDMMC_CLOCK_POWER_SAVE(hsd->Init.ClockPowerSave));
+  assert_param(IS_SDMMC_BUS_WIDE(hsd->Init.BusWide));
+  assert_param(IS_SDMMC_HARDWARE_FLOW_CONTROL(hsd->Init.HardwareFlowControl));
+  assert_param(IS_SDMMC_CLKDIV(hsd->Init.ClockDiv));
+
+  if (hsd->State == HAL_SD_STATE_RESET)
+ 800a81a:	687b      	ldr	r3, [r7, #4]
+ 800a81c:	f893 3030 	ldrb.w	r3, [r3, #48]	; 0x30
+ 800a820:	b2db      	uxtb	r3, r3
+ 800a822:	2b00      	cmp	r3, #0
+ 800a824:	d105      	bne.n	800a832 <HAL_SD_Init+0x2a>
+  {
+    /* Allocate lock resource and initialize it */
+    hsd->Lock = HAL_UNLOCKED;
+ 800a826:	687b      	ldr	r3, [r7, #4]
+ 800a828:	2200      	movs	r2, #0
+ 800a82a:	761a      	strb	r2, [r3, #24]
+
+    /* Init the low level hardware */
+    hsd->MspInitCallback(hsd);
+#else
+    /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
+    HAL_SD_MspInit(hsd);
+ 800a82c:	6878      	ldr	r0, [r7, #4]
+ 800a82e:	f7f6 ffc5 	bl	80017bc <HAL_SD_MspInit>
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+  }
+
+  hsd->State = HAL_SD_STATE_PROGRAMMING;
+ 800a832:	687b      	ldr	r3, [r7, #4]
+ 800a834:	2204      	movs	r2, #4
+ 800a836:	f883 2030 	strb.w	r2, [r3, #48]	; 0x30
+
+  /* Initialize the Card parameters */
+  if (HAL_SD_InitCard(hsd) != HAL_OK)
+ 800a83a:	6878      	ldr	r0, [r7, #4]
+ 800a83c:	f000 f868 	bl	800a910 <HAL_SD_InitCard>
+ 800a840:	4603      	mov	r3, r0
+ 800a842:	2b00      	cmp	r3, #0
+ 800a844:	d001      	beq.n	800a84a <HAL_SD_Init+0x42>
+  {
+    return HAL_ERROR;
+ 800a846:	2301      	movs	r3, #1
+ 800a848:	e05d      	b.n	800a906 <HAL_SD_Init+0xfe>
+  }
+
+  if (HAL_SD_GetCardStatus(hsd, &CardStatus) != HAL_OK)
+ 800a84a:	f107 0308 	add.w	r3, r7, #8
+ 800a84e:	4619      	mov	r1, r3
+ 800a850:	6878      	ldr	r0, [r7, #4]
+ 800a852:	f000 fdaf 	bl	800b3b4 <HAL_SD_GetCardStatus>
+ 800a856:	4603      	mov	r3, r0
+ 800a858:	2b00      	cmp	r3, #0
+ 800a85a:	d001      	beq.n	800a860 <HAL_SD_Init+0x58>
+  {
+    return HAL_ERROR;
+ 800a85c:	2301      	movs	r3, #1
+ 800a85e:	e052      	b.n	800a906 <HAL_SD_Init+0xfe>
+  }
+  /* Get Initial Card Speed from Card Status*/
+  speedgrade = CardStatus.UhsSpeedGrade;
+ 800a860:	7e3b      	ldrb	r3, [r7, #24]
+ 800a862:	b2db      	uxtb	r3, r3
+ 800a864:	627b      	str	r3, [r7, #36]	; 0x24
+  unitsize = CardStatus.UhsAllocationUnitSize;
+ 800a866:	7e7b      	ldrb	r3, [r7, #25]
+ 800a868:	b2db      	uxtb	r3, r3
+ 800a86a:	623b      	str	r3, [r7, #32]
+  if ((hsd->SdCard.CardType == CARD_SDHC_SDXC) && ((speedgrade != 0U) || (unitsize != 0U)))
+ 800a86c:	687b      	ldr	r3, [r7, #4]
+ 800a86e:	6b9b      	ldr	r3, [r3, #56]	; 0x38
+ 800a870:	2b01      	cmp	r3, #1
+ 800a872:	d10a      	bne.n	800a88a <HAL_SD_Init+0x82>
+ 800a874:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 800a876:	2b00      	cmp	r3, #0
+ 800a878:	d102      	bne.n	800a880 <HAL_SD_Init+0x78>
+ 800a87a:	6a3b      	ldr	r3, [r7, #32]
+ 800a87c:	2b00      	cmp	r3, #0
+ 800a87e:	d004      	beq.n	800a88a <HAL_SD_Init+0x82>
+  {
+    hsd->SdCard.CardSpeed = CARD_ULTRA_HIGH_SPEED;
+ 800a880:	687b      	ldr	r3, [r7, #4]
+ 800a882:	f44f 7200 	mov.w	r2, #512	; 0x200
+ 800a886:	659a      	str	r2, [r3, #88]	; 0x58
+ 800a888:	e00b      	b.n	800a8a2 <HAL_SD_Init+0x9a>
+  }
+  else
+  {
+    if (hsd->SdCard.CardType == CARD_SDHC_SDXC)
+ 800a88a:	687b      	ldr	r3, [r7, #4]
+ 800a88c:	6b9b      	ldr	r3, [r3, #56]	; 0x38
+ 800a88e:	2b01      	cmp	r3, #1
+ 800a890:	d104      	bne.n	800a89c <HAL_SD_Init+0x94>
+    {
+      hsd->SdCard.CardSpeed  = CARD_HIGH_SPEED;
+ 800a892:	687b      	ldr	r3, [r7, #4]
+ 800a894:	f44f 7280 	mov.w	r2, #256	; 0x100
+ 800a898:	659a      	str	r2, [r3, #88]	; 0x58
+ 800a89a:	e002      	b.n	800a8a2 <HAL_SD_Init+0x9a>
+    }
+    else
+    {
+      hsd->SdCard.CardSpeed  = CARD_NORMAL_SPEED;
+ 800a89c:	687b      	ldr	r3, [r7, #4]
+ 800a89e:	2200      	movs	r2, #0
+ 800a8a0:	659a      	str	r2, [r3, #88]	; 0x58
+    }
+
+  }
+  /* Configure the bus wide */
+  if (HAL_SD_ConfigWideBusOperation(hsd, hsd->Init.BusWide) != HAL_OK)
+ 800a8a2:	687b      	ldr	r3, [r7, #4]
+ 800a8a4:	68db      	ldr	r3, [r3, #12]
+ 800a8a6:	4619      	mov	r1, r3
+ 800a8a8:	6878      	ldr	r0, [r7, #4]
+ 800a8aa:	f000 fe6d 	bl	800b588 <HAL_SD_ConfigWideBusOperation>
+ 800a8ae:	4603      	mov	r3, r0
+ 800a8b0:	2b00      	cmp	r3, #0
+ 800a8b2:	d001      	beq.n	800a8b8 <HAL_SD_Init+0xb0>
+  {
+    return HAL_ERROR;
+ 800a8b4:	2301      	movs	r3, #1
+ 800a8b6:	e026      	b.n	800a906 <HAL_SD_Init+0xfe>
+  }
+
+  /* Verify that SD card is ready to use after Initialization */
+  tickstart = HAL_GetTick();
+ 800a8b8:	f7f7 fd54 	bl	8002364 <HAL_GetTick>
+ 800a8bc:	61f8      	str	r0, [r7, #28]
+  while ((HAL_SD_GetCardState(hsd) != HAL_SD_CARD_TRANSFER))
+ 800a8be:	e011      	b.n	800a8e4 <HAL_SD_Init+0xdc>
+  {
+    if ((HAL_GetTick() - tickstart) >=  SDMMC_DATATIMEOUT)
+ 800a8c0:	f7f7 fd50 	bl	8002364 <HAL_GetTick>
+ 800a8c4:	4602      	mov	r2, r0
+ 800a8c6:	69fb      	ldr	r3, [r7, #28]
+ 800a8c8:	1ad3      	subs	r3, r2, r3
+ 800a8ca:	f1b3 3fff 	cmp.w	r3, #4294967295
+ 800a8ce:	d109      	bne.n	800a8e4 <HAL_SD_Init+0xdc>
+    {
+      hsd->ErrorCode = HAL_SD_ERROR_TIMEOUT;
+ 800a8d0:	687b      	ldr	r3, [r7, #4]
+ 800a8d2:	f04f 4200 	mov.w	r2, #2147483648	; 0x80000000
+ 800a8d6:	635a      	str	r2, [r3, #52]	; 0x34
+      hsd->State = HAL_SD_STATE_READY;
+ 800a8d8:	687b      	ldr	r3, [r7, #4]
+ 800a8da:	2201      	movs	r2, #1
+ 800a8dc:	f883 2030 	strb.w	r2, [r3, #48]	; 0x30
+      return HAL_TIMEOUT;
+ 800a8e0:	2303      	movs	r3, #3
+ 800a8e2:	e010      	b.n	800a906 <HAL_SD_Init+0xfe>
+  while ((HAL_SD_GetCardState(hsd) != HAL_SD_CARD_TRANSFER))
+ 800a8e4:	6878      	ldr	r0, [r7, #4]
+ 800a8e6:	f000 ff61 	bl	800b7ac <HAL_SD_GetCardState>
+ 800a8ea:	4603      	mov	r3, r0
+ 800a8ec:	2b04      	cmp	r3, #4
+ 800a8ee:	d1e7      	bne.n	800a8c0 <HAL_SD_Init+0xb8>
+    }
+  }
+
+  /* Initialize the error code */
+  hsd->ErrorCode = HAL_SD_ERROR_NONE;
+ 800a8f0:	687b      	ldr	r3, [r7, #4]
+ 800a8f2:	2200      	movs	r2, #0
+ 800a8f4:	635a      	str	r2, [r3, #52]	; 0x34
+
+  /* Initialize the SD operation */
+  hsd->Context = SD_CONTEXT_NONE;
+ 800a8f6:	687b      	ldr	r3, [r7, #4]
+ 800a8f8:	2200      	movs	r2, #0
+ 800a8fa:	62da      	str	r2, [r3, #44]	; 0x2c
+
+  /* Initialize the SD state */
+  hsd->State = HAL_SD_STATE_READY;
+ 800a8fc:	687b      	ldr	r3, [r7, #4]
+ 800a8fe:	2201      	movs	r2, #1
+ 800a900:	f883 2030 	strb.w	r2, [r3, #48]	; 0x30
+
+  return HAL_OK;
+ 800a904:	2300      	movs	r3, #0
+}
+ 800a906:	4618      	mov	r0, r3
+ 800a908:	3728      	adds	r7, #40	; 0x28
+ 800a90a:	46bd      	mov	sp, r7
+ 800a90c:	bd80      	pop	{r7, pc}
+	...
+
+0800a910 <HAL_SD_InitCard>:
+  * @note   This function initializes the SD card. It could be used when a card
+            re-initialization is needed.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd)
+{
+ 800a910:	b590      	push	{r4, r7, lr}
+ 800a912:	b08d      	sub	sp, #52	; 0x34
+ 800a914:	af02      	add	r7, sp, #8
+ 800a916:	6078      	str	r0, [r7, #4]
+  uint32_t errorstate;
+  SD_InitTypeDef Init;
+  uint32_t sdmmc_clk;
+
+  /* Default SDMMC peripheral configuration for SD card initialization */
+  Init.ClockEdge           = SDMMC_CLOCK_EDGE_RISING;
+ 800a918:	2300      	movs	r3, #0
+ 800a91a:	60fb      	str	r3, [r7, #12]
+  Init.ClockPowerSave      = SDMMC_CLOCK_POWER_SAVE_DISABLE;
+ 800a91c:	2300      	movs	r3, #0
+ 800a91e:	613b      	str	r3, [r7, #16]
+  Init.BusWide             = SDMMC_BUS_WIDE_1B;
+ 800a920:	2300      	movs	r3, #0
+ 800a922:	617b      	str	r3, [r7, #20]
+  Init.HardwareFlowControl = SDMMC_HARDWARE_FLOW_CONTROL_DISABLE;
+ 800a924:	2300      	movs	r3, #0
+ 800a926:	61bb      	str	r3, [r7, #24]
+
+  /* Init Clock should be less or equal to 400Khz*/
+  sdmmc_clk     = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SDMMC);
+ 800a928:	f44f 3080 	mov.w	r0, #65536	; 0x10000
+ 800a92c:	f04f 0100 	mov.w	r1, #0
+ 800a930:	f7fe fd24 	bl	800937c <HAL_RCCEx_GetPeriphCLKFreq>
+ 800a934:	6278      	str	r0, [r7, #36]	; 0x24
+  if (sdmmc_clk == 0U)
+ 800a936:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 800a938:	2b00      	cmp	r3, #0
+ 800a93a:	d109      	bne.n	800a950 <HAL_SD_InitCard+0x40>
+  {
+    hsd->State = HAL_SD_STATE_READY;
+ 800a93c:	687b      	ldr	r3, [r7, #4]
+ 800a93e:	2201      	movs	r2, #1
+ 800a940:	f883 2030 	strb.w	r2, [r3, #48]	; 0x30
+    hsd->ErrorCode = SDMMC_ERROR_INVALID_PARAMETER;
+ 800a944:	687b      	ldr	r3, [r7, #4]
+ 800a946:	f04f 6200 	mov.w	r2, #134217728	; 0x8000000
+ 800a94a:	635a      	str	r2, [r3, #52]	; 0x34
+    return HAL_ERROR;
+ 800a94c:	2301      	movs	r3, #1
+ 800a94e:	e070      	b.n	800aa32 <HAL_SD_InitCard+0x122>
+  }
+  Init.ClockDiv = sdmmc_clk / (2U * SD_INIT_FREQ);
+ 800a950:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 800a952:	0a1b      	lsrs	r3, r3, #8
+ 800a954:	4a39      	ldr	r2, [pc, #228]	; (800aa3c <HAL_SD_InitCard+0x12c>)
+ 800a956:	fba2 2303 	umull	r2, r3, r2, r3
+ 800a95a:	091b      	lsrs	r3, r3, #4
+ 800a95c:	61fb      	str	r3, [r7, #28]
+  /* Set Transceiver polarity */
+  hsd->Instance->POWER |= SDMMC_POWER_DIRPOL;
+#endif /* USE_SD_TRANSCEIVER  */
+
+  /* Initialize SDMMC peripheral interface with default configuration */
+  (void)SDMMC_Init(hsd->Instance, Init);
+ 800a95e:	687b      	ldr	r3, [r7, #4]
+ 800a960:	681c      	ldr	r4, [r3, #0]
+ 800a962:	466a      	mov	r2, sp
+ 800a964:	f107 0318 	add.w	r3, r7, #24
+ 800a968:	e893 0003 	ldmia.w	r3, {r0, r1}
+ 800a96c:	e882 0003 	stmia.w	r2, {r0, r1}
+ 800a970:	f107 030c 	add.w	r3, r7, #12
+ 800a974:	cb0e      	ldmia	r3, {r1, r2, r3}
+ 800a976:	4620      	mov	r0, r4
+ 800a978:	f003 faa0 	bl	800debc <SDMMC_Init>
+
+  /* Set Power State to ON */
+  (void)SDMMC_PowerState_ON(hsd->Instance);
+ 800a97c:	687b      	ldr	r3, [r7, #4]
+ 800a97e:	681b      	ldr	r3, [r3, #0]
+ 800a980:	4618      	mov	r0, r3
+ 800a982:	f003 fae3 	bl	800df4c <SDMMC_PowerState_ON>
+
+  /* wait 74 Cycles: required power up waiting time before starting
+     the SD initialization sequence */
+  if (Init.ClockDiv != 0U)
+ 800a986:	69fb      	ldr	r3, [r7, #28]
+ 800a988:	2b00      	cmp	r3, #0
+ 800a98a:	d005      	beq.n	800a998 <HAL_SD_InitCard+0x88>
+  {
+    sdmmc_clk = sdmmc_clk / (2U * Init.ClockDiv);
+ 800a98c:	69fb      	ldr	r3, [r7, #28]
+ 800a98e:	005b      	lsls	r3, r3, #1
+ 800a990:	6a7a      	ldr	r2, [r7, #36]	; 0x24
+ 800a992:	fbb2 f3f3 	udiv	r3, r2, r3
+ 800a996:	627b      	str	r3, [r7, #36]	; 0x24
+  }
+
+  if (sdmmc_clk != 0U)
+ 800a998:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 800a99a:	2b00      	cmp	r3, #0
+ 800a99c:	d007      	beq.n	800a9ae <HAL_SD_InitCard+0x9e>
+  {
+    HAL_Delay(1U + (74U * 1000U / (sdmmc_clk)));
+ 800a99e:	4a28      	ldr	r2, [pc, #160]	; (800aa40 <HAL_SD_InitCard+0x130>)
+ 800a9a0:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 800a9a2:	fbb2 f3f3 	udiv	r3, r2, r3
+ 800a9a6:	3301      	adds	r3, #1
+ 800a9a8:	4618      	mov	r0, r3
+ 800a9aa:	f7f7 fce7 	bl	800237c <HAL_Delay>
+  }
+
+  /* Identify card operating voltage */
+  errorstate = SD_PowerON(hsd);
+ 800a9ae:	6878      	ldr	r0, [r7, #4]
+ 800a9b0:	f000 ffea 	bl	800b988 <SD_PowerON>
+ 800a9b4:	6238      	str	r0, [r7, #32]
+  if (errorstate != HAL_SD_ERROR_NONE)
+ 800a9b6:	6a3b      	ldr	r3, [r7, #32]
+ 800a9b8:	2b00      	cmp	r3, #0
+ 800a9ba:	d00b      	beq.n	800a9d4 <HAL_SD_InitCard+0xc4>
+  {
+    hsd->State = HAL_SD_STATE_READY;
+ 800a9bc:	687b      	ldr	r3, [r7, #4]
+ 800a9be:	2201      	movs	r2, #1
+ 800a9c0:	f883 2030 	strb.w	r2, [r3, #48]	; 0x30
+    hsd->ErrorCode |= errorstate;
+ 800a9c4:	687b      	ldr	r3, [r7, #4]
+ 800a9c6:	6b5a      	ldr	r2, [r3, #52]	; 0x34
+ 800a9c8:	6a3b      	ldr	r3, [r7, #32]
+ 800a9ca:	431a      	orrs	r2, r3
+ 800a9cc:	687b      	ldr	r3, [r7, #4]
+ 800a9ce:	635a      	str	r2, [r3, #52]	; 0x34
+    return HAL_ERROR;
+ 800a9d0:	2301      	movs	r3, #1
+ 800a9d2:	e02e      	b.n	800aa32 <HAL_SD_InitCard+0x122>
+  }
+
+  /* Card initialization */
+  errorstate = SD_InitCard(hsd);
+ 800a9d4:	6878      	ldr	r0, [r7, #4]
+ 800a9d6:	f000 ff09 	bl	800b7ec <SD_InitCard>
+ 800a9da:	6238      	str	r0, [r7, #32]
+  if (errorstate != HAL_SD_ERROR_NONE)
+ 800a9dc:	6a3b      	ldr	r3, [r7, #32]
+ 800a9de:	2b00      	cmp	r3, #0
+ 800a9e0:	d00b      	beq.n	800a9fa <HAL_SD_InitCard+0xea>
+  {
+    hsd->State = HAL_SD_STATE_READY;
+ 800a9e2:	687b      	ldr	r3, [r7, #4]
+ 800a9e4:	2201      	movs	r2, #1
+ 800a9e6:	f883 2030 	strb.w	r2, [r3, #48]	; 0x30
+    hsd->ErrorCode |= errorstate;
+ 800a9ea:	687b      	ldr	r3, [r7, #4]
+ 800a9ec:	6b5a      	ldr	r2, [r3, #52]	; 0x34
+ 800a9ee:	6a3b      	ldr	r3, [r7, #32]
+ 800a9f0:	431a      	orrs	r2, r3
+ 800a9f2:	687b      	ldr	r3, [r7, #4]
+ 800a9f4:	635a      	str	r2, [r3, #52]	; 0x34
+    return HAL_ERROR;
+ 800a9f6:	2301      	movs	r3, #1
+ 800a9f8:	e01b      	b.n	800aa32 <HAL_SD_InitCard+0x122>
+  }
+
+  /* Set Block Size for Card */
+  errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
+ 800a9fa:	687b      	ldr	r3, [r7, #4]
+ 800a9fc:	681b      	ldr	r3, [r3, #0]
+ 800a9fe:	f44f 7100 	mov.w	r1, #512	; 0x200
+ 800aa02:	4618      	mov	r0, r3
+ 800aa04:	f003 fb38 	bl	800e078 <SDMMC_CmdBlockLength>
+ 800aa08:	6238      	str	r0, [r7, #32]
+  if (errorstate != HAL_SD_ERROR_NONE)
+ 800aa0a:	6a3b      	ldr	r3, [r7, #32]
+ 800aa0c:	2b00      	cmp	r3, #0
+ 800aa0e:	d00f      	beq.n	800aa30 <HAL_SD_InitCard+0x120>
+  {
+    /* Clear all the static flags */
+    __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+ 800aa10:	687b      	ldr	r3, [r7, #4]
+ 800aa12:	681b      	ldr	r3, [r3, #0]
+ 800aa14:	4a0b      	ldr	r2, [pc, #44]	; (800aa44 <HAL_SD_InitCard+0x134>)
+ 800aa16:	639a      	str	r2, [r3, #56]	; 0x38
+    hsd->ErrorCode |= errorstate;
+ 800aa18:	687b      	ldr	r3, [r7, #4]
+ 800aa1a:	6b5a      	ldr	r2, [r3, #52]	; 0x34
+ 800aa1c:	6a3b      	ldr	r3, [r7, #32]
+ 800aa1e:	431a      	orrs	r2, r3
+ 800aa20:	687b      	ldr	r3, [r7, #4]
+ 800aa22:	635a      	str	r2, [r3, #52]	; 0x34
+    hsd->State = HAL_SD_STATE_READY;
+ 800aa24:	687b      	ldr	r3, [r7, #4]
+ 800aa26:	2201      	movs	r2, #1
+ 800aa28:	f883 2030 	strb.w	r2, [r3, #48]	; 0x30
+    return HAL_ERROR;
+ 800aa2c:	2301      	movs	r3, #1
+ 800aa2e:	e000      	b.n	800aa32 <HAL_SD_InitCard+0x122>
+  }
+
+  return HAL_OK;
+ 800aa30:	2300      	movs	r3, #0
+}
+ 800aa32:	4618      	mov	r0, r3
+ 800aa34:	372c      	adds	r7, #44	; 0x2c
+ 800aa36:	46bd      	mov	sp, r7
+ 800aa38:	bd90      	pop	{r4, r7, pc}
+ 800aa3a:	bf00      	nop
+ 800aa3c:	014f8b59 	.word	0x014f8b59
+ 800aa40:	00012110 	.word	0x00012110
+ 800aa44:	1fe00fff 	.word	0x1fe00fff
+
+0800aa48 <HAL_SD_ReadBlocks_DMA>:
+  * @param  NumberOfBlocks: Number of blocks to read.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd,
+                                        uint32_t NumberOfBlocks)
+{
+ 800aa48:	b580      	push	{r7, lr}
+ 800aa4a:	b08c      	sub	sp, #48	; 0x30
+ 800aa4c:	af00      	add	r7, sp, #0
+ 800aa4e:	60f8      	str	r0, [r7, #12]
+ 800aa50:	60b9      	str	r1, [r7, #8]
+ 800aa52:	607a      	str	r2, [r7, #4]
+ 800aa54:	603b      	str	r3, [r7, #0]
+  SDMMC_DataInitTypeDef config;
+  uint32_t errorstate;
+  uint32_t add = BlockAdd;
+ 800aa56:	687b      	ldr	r3, [r7, #4]
+ 800aa58:	62bb      	str	r3, [r7, #40]	; 0x28
+
+  if (NULL == pData)
+ 800aa5a:	68bb      	ldr	r3, [r7, #8]
+ 800aa5c:	2b00      	cmp	r3, #0
+ 800aa5e:	d107      	bne.n	800aa70 <HAL_SD_ReadBlocks_DMA+0x28>
+  {
+    hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
+ 800aa60:	68fb      	ldr	r3, [r7, #12]
+ 800aa62:	6b5b      	ldr	r3, [r3, #52]	; 0x34
+ 800aa64:	f043 6200 	orr.w	r2, r3, #134217728	; 0x8000000
+ 800aa68:	68fb      	ldr	r3, [r7, #12]
+ 800aa6a:	635a      	str	r2, [r3, #52]	; 0x34
+    return HAL_ERROR;
+ 800aa6c:	2301      	movs	r3, #1
+ 800aa6e:	e08d      	b.n	800ab8c <HAL_SD_ReadBlocks_DMA+0x144>
+  }
+
+  if (hsd->State == HAL_SD_STATE_READY)
+ 800aa70:	68fb      	ldr	r3, [r7, #12]
+ 800aa72:	f893 3030 	ldrb.w	r3, [r3, #48]	; 0x30
+ 800aa76:	b2db      	uxtb	r3, r3
+ 800aa78:	2b01      	cmp	r3, #1
+ 800aa7a:	f040 8086 	bne.w	800ab8a <HAL_SD_ReadBlocks_DMA+0x142>
+  {
+    hsd->ErrorCode = HAL_SD_ERROR_NONE;
+ 800aa7e:	68fb      	ldr	r3, [r7, #12]
+ 800aa80:	2200      	movs	r2, #0
+ 800aa82:	635a      	str	r2, [r3, #52]	; 0x34
+
+    if ((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
+ 800aa84:	6aba      	ldr	r2, [r7, #40]	; 0x28
+ 800aa86:	683b      	ldr	r3, [r7, #0]
+ 800aa88:	441a      	add	r2, r3
+ 800aa8a:	68fb      	ldr	r3, [r7, #12]
+ 800aa8c:	6d1b      	ldr	r3, [r3, #80]	; 0x50
+ 800aa8e:	429a      	cmp	r2, r3
+ 800aa90:	d907      	bls.n	800aaa2 <HAL_SD_ReadBlocks_DMA+0x5a>
+    {
+      hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
+ 800aa92:	68fb      	ldr	r3, [r7, #12]
+ 800aa94:	6b5b      	ldr	r3, [r3, #52]	; 0x34
+ 800aa96:	f043 7200 	orr.w	r2, r3, #33554432	; 0x2000000
+ 800aa9a:	68fb      	ldr	r3, [r7, #12]
+ 800aa9c:	635a      	str	r2, [r3, #52]	; 0x34
+      return HAL_ERROR;
+ 800aa9e:	2301      	movs	r3, #1
+ 800aaa0:	e074      	b.n	800ab8c <HAL_SD_ReadBlocks_DMA+0x144>
+    }
+
+    hsd->State = HAL_SD_STATE_BUSY;
+ 800aaa2:	68fb      	ldr	r3, [r7, #12]
+ 800aaa4:	2203      	movs	r2, #3
+ 800aaa6:	f883 2030 	strb.w	r2, [r3, #48]	; 0x30
+
+    /* Initialize data control register */
+    hsd->Instance->DCTRL = 0U;
+ 800aaaa:	68fb      	ldr	r3, [r7, #12]
+ 800aaac:	681b      	ldr	r3, [r3, #0]
+ 800aaae:	2200      	movs	r2, #0
+ 800aab0:	62da      	str	r2, [r3, #44]	; 0x2c
+
+    hsd->pRxBuffPtr = pData;
+ 800aab2:	68fb      	ldr	r3, [r7, #12]
+ 800aab4:	68ba      	ldr	r2, [r7, #8]
+ 800aab6:	625a      	str	r2, [r3, #36]	; 0x24
+    hsd->RxXferSize = BLOCKSIZE * NumberOfBlocks;
+ 800aab8:	683b      	ldr	r3, [r7, #0]
+ 800aaba:	025a      	lsls	r2, r3, #9
+ 800aabc:	68fb      	ldr	r3, [r7, #12]
+ 800aabe:	629a      	str	r2, [r3, #40]	; 0x28
+
+    if (hsd->SdCard.CardType != CARD_SDHC_SDXC)
+ 800aac0:	68fb      	ldr	r3, [r7, #12]
+ 800aac2:	6b9b      	ldr	r3, [r3, #56]	; 0x38
+ 800aac4:	2b01      	cmp	r3, #1
+ 800aac6:	d002      	beq.n	800aace <HAL_SD_ReadBlocks_DMA+0x86>
+    {
+      add *= 512U;
+ 800aac8:	6abb      	ldr	r3, [r7, #40]	; 0x28
+ 800aaca:	025b      	lsls	r3, r3, #9
+ 800aacc:	62bb      	str	r3, [r7, #40]	; 0x28
+    }
+
+    /* Configure the SD DPSM (Data Path State Machine) */
+    config.DataTimeOut   = SDMMC_DATATIMEOUT;
+ 800aace:	f04f 33ff 	mov.w	r3, #4294967295
+ 800aad2:	613b      	str	r3, [r7, #16]
+    config.DataLength    = BLOCKSIZE * NumberOfBlocks;
+ 800aad4:	683b      	ldr	r3, [r7, #0]
+ 800aad6:	025b      	lsls	r3, r3, #9
+ 800aad8:	617b      	str	r3, [r7, #20]
+    config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
+ 800aada:	2390      	movs	r3, #144	; 0x90
+ 800aadc:	61bb      	str	r3, [r7, #24]
+    config.TransferDir   = SDMMC_TRANSFER_DIR_TO_SDMMC;
+ 800aade:	2302      	movs	r3, #2
+ 800aae0:	61fb      	str	r3, [r7, #28]
+    config.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
+ 800aae2:	2300      	movs	r3, #0
+ 800aae4:	623b      	str	r3, [r7, #32]
+    config.DPSM          = SDMMC_DPSM_DISABLE;
+ 800aae6:	2300      	movs	r3, #0
+ 800aae8:	627b      	str	r3, [r7, #36]	; 0x24
+    (void)SDMMC_ConfigData(hsd->Instance, &config);
+ 800aaea:	68fb      	ldr	r3, [r7, #12]
+ 800aaec:	681b      	ldr	r3, [r3, #0]
+ 800aaee:	f107 0210 	add.w	r2, r7, #16
+ 800aaf2:	4611      	mov	r1, r2
+ 800aaf4:	4618      	mov	r0, r3
+ 800aaf6:	f003 fa93 	bl	800e020 <SDMMC_ConfigData>
+
+    __SDMMC_CMDTRANS_ENABLE(hsd->Instance);
+ 800aafa:	68fb      	ldr	r3, [r7, #12]
+ 800aafc:	681b      	ldr	r3, [r3, #0]
+ 800aafe:	68da      	ldr	r2, [r3, #12]
+ 800ab00:	68fb      	ldr	r3, [r7, #12]
+ 800ab02:	681b      	ldr	r3, [r3, #0]
+ 800ab04:	f042 0240 	orr.w	r2, r2, #64	; 0x40
+ 800ab08:	60da      	str	r2, [r3, #12]
+    hsd->Instance->IDMABASE0 = (uint32_t) pData ;
+ 800ab0a:	68fb      	ldr	r3, [r7, #12]
+ 800ab0c:	681b      	ldr	r3, [r3, #0]
+ 800ab0e:	68ba      	ldr	r2, [r7, #8]
+ 800ab10:	659a      	str	r2, [r3, #88]	; 0x58
+    hsd->Instance->IDMACTRL  = SDMMC_ENABLE_IDMA_SINGLE_BUFF;
+ 800ab12:	68fb      	ldr	r3, [r7, #12]
+ 800ab14:	681b      	ldr	r3, [r3, #0]
+ 800ab16:	2201      	movs	r2, #1
+ 800ab18:	651a      	str	r2, [r3, #80]	; 0x50
+
+    /* Read Blocks in DMA mode */
+    if (NumberOfBlocks > 1U)
+ 800ab1a:	683b      	ldr	r3, [r7, #0]
+ 800ab1c:	2b01      	cmp	r3, #1
+ 800ab1e:	d90a      	bls.n	800ab36 <HAL_SD_ReadBlocks_DMA+0xee>
+    {
+      hsd->Context = (SD_CONTEXT_READ_MULTIPLE_BLOCK | SD_CONTEXT_DMA);
+ 800ab20:	68fb      	ldr	r3, [r7, #12]
+ 800ab22:	2282      	movs	r2, #130	; 0x82
+ 800ab24:	62da      	str	r2, [r3, #44]	; 0x2c
+
+      /* Read Multi Block command */
+      errorstate = SDMMC_CmdReadMultiBlock(hsd->Instance, add);
+ 800ab26:	68fb      	ldr	r3, [r7, #12]
+ 800ab28:	681b      	ldr	r3, [r3, #0]
+ 800ab2a:	6ab9      	ldr	r1, [r7, #40]	; 0x28
+ 800ab2c:	4618      	mov	r0, r3
+ 800ab2e:	f003 fae9 	bl	800e104 <SDMMC_CmdReadMultiBlock>
+ 800ab32:	62f8      	str	r0, [r7, #44]	; 0x2c
+ 800ab34:	e009      	b.n	800ab4a <HAL_SD_ReadBlocks_DMA+0x102>
+    }
+    else
+    {
+      hsd->Context = (SD_CONTEXT_READ_SINGLE_BLOCK | SD_CONTEXT_DMA);
+ 800ab36:	68fb      	ldr	r3, [r7, #12]
+ 800ab38:	2281      	movs	r2, #129	; 0x81
+ 800ab3a:	62da      	str	r2, [r3, #44]	; 0x2c
+
+      /* Read Single Block command */
+      errorstate = SDMMC_CmdReadSingleBlock(hsd->Instance, add);
+ 800ab3c:	68fb      	ldr	r3, [r7, #12]
+ 800ab3e:	681b      	ldr	r3, [r3, #0]
+ 800ab40:	6ab9      	ldr	r1, [r7, #40]	; 0x28
+ 800ab42:	4618      	mov	r0, r3
+ 800ab44:	f003 fabb 	bl	800e0be <SDMMC_CmdReadSingleBlock>
+ 800ab48:	62f8      	str	r0, [r7, #44]	; 0x2c
+    }
+    if (errorstate != HAL_SD_ERROR_NONE)
+ 800ab4a:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 800ab4c:	2b00      	cmp	r3, #0
+ 800ab4e:	d012      	beq.n	800ab76 <HAL_SD_ReadBlocks_DMA+0x12e>
+    {
+      /* Clear all the static flags */
+      __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+ 800ab50:	68fb      	ldr	r3, [r7, #12]
+ 800ab52:	681b      	ldr	r3, [r3, #0]
+ 800ab54:	4a0f      	ldr	r2, [pc, #60]	; (800ab94 <HAL_SD_ReadBlocks_DMA+0x14c>)
+ 800ab56:	639a      	str	r2, [r3, #56]	; 0x38
+      hsd->ErrorCode |= errorstate;
+ 800ab58:	68fb      	ldr	r3, [r7, #12]
+ 800ab5a:	6b5a      	ldr	r2, [r3, #52]	; 0x34
+ 800ab5c:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 800ab5e:	431a      	orrs	r2, r3
+ 800ab60:	68fb      	ldr	r3, [r7, #12]
+ 800ab62:	635a      	str	r2, [r3, #52]	; 0x34
+      hsd->State = HAL_SD_STATE_READY;
+ 800ab64:	68fb      	ldr	r3, [r7, #12]
+ 800ab66:	2201      	movs	r2, #1
+ 800ab68:	f883 2030 	strb.w	r2, [r3, #48]	; 0x30
+      hsd->Context = SD_CONTEXT_NONE;
+ 800ab6c:	68fb      	ldr	r3, [r7, #12]
+ 800ab6e:	2200      	movs	r2, #0
+ 800ab70:	62da      	str	r2, [r3, #44]	; 0x2c
+      return HAL_ERROR;
+ 800ab72:	2301      	movs	r3, #1
+ 800ab74:	e00a      	b.n	800ab8c <HAL_SD_ReadBlocks_DMA+0x144>
+    }
+
+    /* Enable transfer interrupts */
+    __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND));
+ 800ab76:	68fb      	ldr	r3, [r7, #12]
+ 800ab78:	681b      	ldr	r3, [r3, #0]
+ 800ab7a:	6bda      	ldr	r2, [r3, #60]	; 0x3c
+ 800ab7c:	68fb      	ldr	r3, [r7, #12]
+ 800ab7e:	681b      	ldr	r3, [r3, #0]
+ 800ab80:	f442 7295 	orr.w	r2, r2, #298	; 0x12a
+ 800ab84:	63da      	str	r2, [r3, #60]	; 0x3c
+
+
+    return HAL_OK;
+ 800ab86:	2300      	movs	r3, #0
+ 800ab88:	e000      	b.n	800ab8c <HAL_SD_ReadBlocks_DMA+0x144>
+  }
+  else
+  {
+    return HAL_BUSY;
+ 800ab8a:	2302      	movs	r3, #2
+  }
+}
+ 800ab8c:	4618      	mov	r0, r3
+ 800ab8e:	3730      	adds	r7, #48	; 0x30
+ 800ab90:	46bd      	mov	sp, r7
+ 800ab92:	bd80      	pop	{r7, pc}
+ 800ab94:	1fe00fff 	.word	0x1fe00fff
+
+0800ab98 <HAL_SD_WriteBlocks_DMA>:
+  * @param  NumberOfBlocks: Number of blocks to write
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, const uint8_t *pData, uint32_t BlockAdd,
+                                         uint32_t NumberOfBlocks)
+{
+ 800ab98:	b580      	push	{r7, lr}
+ 800ab9a:	b08c      	sub	sp, #48	; 0x30
+ 800ab9c:	af00      	add	r7, sp, #0
+ 800ab9e:	60f8      	str	r0, [r7, #12]
+ 800aba0:	60b9      	str	r1, [r7, #8]
+ 800aba2:	607a      	str	r2, [r7, #4]
+ 800aba4:	603b      	str	r3, [r7, #0]
+  SDMMC_DataInitTypeDef config;
+  uint32_t errorstate;
+  uint32_t add = BlockAdd;
+ 800aba6:	687b      	ldr	r3, [r7, #4]
+ 800aba8:	62bb      	str	r3, [r7, #40]	; 0x28
+
+  if (NULL == pData)
+ 800abaa:	68bb      	ldr	r3, [r7, #8]
+ 800abac:	2b00      	cmp	r3, #0
+ 800abae:	d107      	bne.n	800abc0 <HAL_SD_WriteBlocks_DMA+0x28>
+  {
+    hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
+ 800abb0:	68fb      	ldr	r3, [r7, #12]
+ 800abb2:	6b5b      	ldr	r3, [r3, #52]	; 0x34
+ 800abb4:	f043 6200 	orr.w	r2, r3, #134217728	; 0x8000000
+ 800abb8:	68fb      	ldr	r3, [r7, #12]
+ 800abba:	635a      	str	r2, [r3, #52]	; 0x34
+    return HAL_ERROR;
+ 800abbc:	2301      	movs	r3, #1
+ 800abbe:	e08d      	b.n	800acdc <HAL_SD_WriteBlocks_DMA+0x144>
+  }
+
+  if (hsd->State == HAL_SD_STATE_READY)
+ 800abc0:	68fb      	ldr	r3, [r7, #12]
+ 800abc2:	f893 3030 	ldrb.w	r3, [r3, #48]	; 0x30
+ 800abc6:	b2db      	uxtb	r3, r3
+ 800abc8:	2b01      	cmp	r3, #1
+ 800abca:	f040 8086 	bne.w	800acda <HAL_SD_WriteBlocks_DMA+0x142>
+  {
+    hsd->ErrorCode = HAL_SD_ERROR_NONE;
+ 800abce:	68fb      	ldr	r3, [r7, #12]
+ 800abd0:	2200      	movs	r2, #0
+ 800abd2:	635a      	str	r2, [r3, #52]	; 0x34
+
+    if ((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
+ 800abd4:	6aba      	ldr	r2, [r7, #40]	; 0x28
+ 800abd6:	683b      	ldr	r3, [r7, #0]
+ 800abd8:	441a      	add	r2, r3
+ 800abda:	68fb      	ldr	r3, [r7, #12]
+ 800abdc:	6d1b      	ldr	r3, [r3, #80]	; 0x50
+ 800abde:	429a      	cmp	r2, r3
+ 800abe0:	d907      	bls.n	800abf2 <HAL_SD_WriteBlocks_DMA+0x5a>
+    {
+      hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
+ 800abe2:	68fb      	ldr	r3, [r7, #12]
+ 800abe4:	6b5b      	ldr	r3, [r3, #52]	; 0x34
+ 800abe6:	f043 7200 	orr.w	r2, r3, #33554432	; 0x2000000
+ 800abea:	68fb      	ldr	r3, [r7, #12]
+ 800abec:	635a      	str	r2, [r3, #52]	; 0x34
+      return HAL_ERROR;
+ 800abee:	2301      	movs	r3, #1
+ 800abf0:	e074      	b.n	800acdc <HAL_SD_WriteBlocks_DMA+0x144>
+    }
+
+    hsd->State = HAL_SD_STATE_BUSY;
+ 800abf2:	68fb      	ldr	r3, [r7, #12]
+ 800abf4:	2203      	movs	r2, #3
+ 800abf6:	f883 2030 	strb.w	r2, [r3, #48]	; 0x30
+
+    /* Initialize data control register */
+    hsd->Instance->DCTRL = 0U;
+ 800abfa:	68fb      	ldr	r3, [r7, #12]
+ 800abfc:	681b      	ldr	r3, [r3, #0]
+ 800abfe:	2200      	movs	r2, #0
+ 800ac00:	62da      	str	r2, [r3, #44]	; 0x2c
+
+    hsd->pTxBuffPtr = pData;
+ 800ac02:	68fb      	ldr	r3, [r7, #12]
+ 800ac04:	68ba      	ldr	r2, [r7, #8]
+ 800ac06:	61da      	str	r2, [r3, #28]
+    hsd->TxXferSize = BLOCKSIZE * NumberOfBlocks;
+ 800ac08:	683b      	ldr	r3, [r7, #0]
+ 800ac0a:	025a      	lsls	r2, r3, #9
+ 800ac0c:	68fb      	ldr	r3, [r7, #12]
+ 800ac0e:	621a      	str	r2, [r3, #32]
+
+    if (hsd->SdCard.CardType != CARD_SDHC_SDXC)
+ 800ac10:	68fb      	ldr	r3, [r7, #12]
+ 800ac12:	6b9b      	ldr	r3, [r3, #56]	; 0x38
+ 800ac14:	2b01      	cmp	r3, #1
+ 800ac16:	d002      	beq.n	800ac1e <HAL_SD_WriteBlocks_DMA+0x86>
+    {
+      add *= 512U;
+ 800ac18:	6abb      	ldr	r3, [r7, #40]	; 0x28
+ 800ac1a:	025b      	lsls	r3, r3, #9
+ 800ac1c:	62bb      	str	r3, [r7, #40]	; 0x28
+    }
+
+    /* Configure the SD DPSM (Data Path State Machine) */
+    config.DataTimeOut   = SDMMC_DATATIMEOUT;
+ 800ac1e:	f04f 33ff 	mov.w	r3, #4294967295
+ 800ac22:	613b      	str	r3, [r7, #16]
+    config.DataLength    = BLOCKSIZE * NumberOfBlocks;
+ 800ac24:	683b      	ldr	r3, [r7, #0]
+ 800ac26:	025b      	lsls	r3, r3, #9
+ 800ac28:	617b      	str	r3, [r7, #20]
+    config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
+ 800ac2a:	2390      	movs	r3, #144	; 0x90
+ 800ac2c:	61bb      	str	r3, [r7, #24]
+    config.TransferDir   = SDMMC_TRANSFER_DIR_TO_CARD;
+ 800ac2e:	2300      	movs	r3, #0
+ 800ac30:	61fb      	str	r3, [r7, #28]
+    config.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
+ 800ac32:	2300      	movs	r3, #0
+ 800ac34:	623b      	str	r3, [r7, #32]
+    config.DPSM          = SDMMC_DPSM_DISABLE;
+ 800ac36:	2300      	movs	r3, #0
+ 800ac38:	627b      	str	r3, [r7, #36]	; 0x24
+    (void)SDMMC_ConfigData(hsd->Instance, &config);
+ 800ac3a:	68fb      	ldr	r3, [r7, #12]
+ 800ac3c:	681b      	ldr	r3, [r3, #0]
+ 800ac3e:	f107 0210 	add.w	r2, r7, #16
+ 800ac42:	4611      	mov	r1, r2
+ 800ac44:	4618      	mov	r0, r3
+ 800ac46:	f003 f9eb 	bl	800e020 <SDMMC_ConfigData>
+
+
+    __SDMMC_CMDTRANS_ENABLE(hsd->Instance);
+ 800ac4a:	68fb      	ldr	r3, [r7, #12]
+ 800ac4c:	681b      	ldr	r3, [r3, #0]
+ 800ac4e:	68da      	ldr	r2, [r3, #12]
+ 800ac50:	68fb      	ldr	r3, [r7, #12]
+ 800ac52:	681b      	ldr	r3, [r3, #0]
+ 800ac54:	f042 0240 	orr.w	r2, r2, #64	; 0x40
+ 800ac58:	60da      	str	r2, [r3, #12]
+
+    hsd->Instance->IDMABASE0 = (uint32_t) pData ;
+ 800ac5a:	68fb      	ldr	r3, [r7, #12]
+ 800ac5c:	681b      	ldr	r3, [r3, #0]
+ 800ac5e:	68ba      	ldr	r2, [r7, #8]
+ 800ac60:	659a      	str	r2, [r3, #88]	; 0x58
+    hsd->Instance->IDMACTRL  = SDMMC_ENABLE_IDMA_SINGLE_BUFF;
+ 800ac62:	68fb      	ldr	r3, [r7, #12]
+ 800ac64:	681b      	ldr	r3, [r3, #0]
+ 800ac66:	2201      	movs	r2, #1
+ 800ac68:	651a      	str	r2, [r3, #80]	; 0x50
+
+    /* Write Blocks in Polling mode */
+    if (NumberOfBlocks > 1U)
+ 800ac6a:	683b      	ldr	r3, [r7, #0]
+ 800ac6c:	2b01      	cmp	r3, #1
+ 800ac6e:	d90a      	bls.n	800ac86 <HAL_SD_WriteBlocks_DMA+0xee>
+    {
+      hsd->Context = (SD_CONTEXT_WRITE_MULTIPLE_BLOCK | SD_CONTEXT_DMA);
+ 800ac70:	68fb      	ldr	r3, [r7, #12]
+ 800ac72:	22a0      	movs	r2, #160	; 0xa0
+ 800ac74:	62da      	str	r2, [r3, #44]	; 0x2c
+
+      /* Write Multi Block command */
+      errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, add);
+ 800ac76:	68fb      	ldr	r3, [r7, #12]
+ 800ac78:	681b      	ldr	r3, [r3, #0]
+ 800ac7a:	6ab9      	ldr	r1, [r7, #40]	; 0x28
+ 800ac7c:	4618      	mov	r0, r3
+ 800ac7e:	f003 fa87 	bl	800e190 <SDMMC_CmdWriteMultiBlock>
+ 800ac82:	62f8      	str	r0, [r7, #44]	; 0x2c
+ 800ac84:	e009      	b.n	800ac9a <HAL_SD_WriteBlocks_DMA+0x102>
+    }
+    else
+    {
+      hsd->Context = (SD_CONTEXT_WRITE_SINGLE_BLOCK | SD_CONTEXT_DMA);
+ 800ac86:	68fb      	ldr	r3, [r7, #12]
+ 800ac88:	2290      	movs	r2, #144	; 0x90
+ 800ac8a:	62da      	str	r2, [r3, #44]	; 0x2c
+
+      /* Write Single Block command */
+      errorstate = SDMMC_CmdWriteSingleBlock(hsd->Instance, add);
+ 800ac8c:	68fb      	ldr	r3, [r7, #12]
+ 800ac8e:	681b      	ldr	r3, [r3, #0]
+ 800ac90:	6ab9      	ldr	r1, [r7, #40]	; 0x28
+ 800ac92:	4618      	mov	r0, r3
+ 800ac94:	f003 fa59 	bl	800e14a <SDMMC_CmdWriteSingleBlock>
+ 800ac98:	62f8      	str	r0, [r7, #44]	; 0x2c
+    }
+    if (errorstate != HAL_SD_ERROR_NONE)
+ 800ac9a:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 800ac9c:	2b00      	cmp	r3, #0
+ 800ac9e:	d012      	beq.n	800acc6 <HAL_SD_WriteBlocks_DMA+0x12e>
+    {
+      /* Clear all the static flags */
+      __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+ 800aca0:	68fb      	ldr	r3, [r7, #12]
+ 800aca2:	681b      	ldr	r3, [r3, #0]
+ 800aca4:	4a0f      	ldr	r2, [pc, #60]	; (800ace4 <HAL_SD_WriteBlocks_DMA+0x14c>)
+ 800aca6:	639a      	str	r2, [r3, #56]	; 0x38
+      hsd->ErrorCode |= errorstate;
+ 800aca8:	68fb      	ldr	r3, [r7, #12]
+ 800acaa:	6b5a      	ldr	r2, [r3, #52]	; 0x34
+ 800acac:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 800acae:	431a      	orrs	r2, r3
+ 800acb0:	68fb      	ldr	r3, [r7, #12]
+ 800acb2:	635a      	str	r2, [r3, #52]	; 0x34
+      hsd->State = HAL_SD_STATE_READY;
+ 800acb4:	68fb      	ldr	r3, [r7, #12]
+ 800acb6:	2201      	movs	r2, #1
+ 800acb8:	f883 2030 	strb.w	r2, [r3, #48]	; 0x30
+      hsd->Context = SD_CONTEXT_NONE;
+ 800acbc:	68fb      	ldr	r3, [r7, #12]
+ 800acbe:	2200      	movs	r2, #0
+ 800acc0:	62da      	str	r2, [r3, #44]	; 0x2c
+      return HAL_ERROR;
+ 800acc2:	2301      	movs	r3, #1
+ 800acc4:	e00a      	b.n	800acdc <HAL_SD_WriteBlocks_DMA+0x144>
+    }
+
+    /* Enable transfer interrupts */
+    __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND));
+ 800acc6:	68fb      	ldr	r3, [r7, #12]
+ 800acc8:	681b      	ldr	r3, [r3, #0]
+ 800acca:	6bda      	ldr	r2, [r3, #60]	; 0x3c
+ 800accc:	68fb      	ldr	r3, [r7, #12]
+ 800acce:	681b      	ldr	r3, [r3, #0]
+ 800acd0:	f442 728d 	orr.w	r2, r2, #282	; 0x11a
+ 800acd4:	63da      	str	r2, [r3, #60]	; 0x3c
+
+    return HAL_OK;
+ 800acd6:	2300      	movs	r3, #0
+ 800acd8:	e000      	b.n	800acdc <HAL_SD_WriteBlocks_DMA+0x144>
+  }
+  else
+  {
+    return HAL_BUSY;
+ 800acda:	2302      	movs	r3, #2
+  }
+}
+ 800acdc:	4618      	mov	r0, r3
+ 800acde:	3730      	adds	r7, #48	; 0x30
+ 800ace0:	46bd      	mov	sp, r7
+ 800ace2:	bd80      	pop	{r7, pc}
+ 800ace4:	1fe00fff 	.word	0x1fe00fff
+
+0800ace8 <HAL_SD_IRQHandler>:
+  * @brief  This function handles SD card interrupt request.
+  * @param  hsd: Pointer to SD handle
+  * @retval None
+  */
+void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd)
+{
+ 800ace8:	b580      	push	{r7, lr}
+ 800acea:	b084      	sub	sp, #16
+ 800acec:	af00      	add	r7, sp, #0
+ 800acee:	6078      	str	r0, [r7, #4]
+  uint32_t errorstate;
+  uint32_t context = hsd->Context;
+ 800acf0:	687b      	ldr	r3, [r7, #4]
+ 800acf2:	6adb      	ldr	r3, [r3, #44]	; 0x2c
+ 800acf4:	60fb      	str	r3, [r7, #12]
+
+  /* Check for SDMMC interrupt flags */
+  if ((__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF) != RESET) && ((context & SD_CONTEXT_IT) != 0U))
+ 800acf6:	687b      	ldr	r3, [r7, #4]
+ 800acf8:	681b      	ldr	r3, [r3, #0]
+ 800acfa:	6b5b      	ldr	r3, [r3, #52]	; 0x34
+ 800acfc:	f403 4300 	and.w	r3, r3, #32768	; 0x8000
+ 800ad00:	2b00      	cmp	r3, #0
+ 800ad02:	d008      	beq.n	800ad16 <HAL_SD_IRQHandler+0x2e>
+ 800ad04:	68fb      	ldr	r3, [r7, #12]
+ 800ad06:	f003 0308 	and.w	r3, r3, #8
+ 800ad0a:	2b00      	cmp	r3, #0
+ 800ad0c:	d003      	beq.n	800ad16 <HAL_SD_IRQHandler+0x2e>
+  {
+    SD_Read_IT(hsd);
+ 800ad0e:	6878      	ldr	r0, [r7, #4]
+ 800ad10:	f001 f926 	bl	800bf60 <SD_Read_IT>
+ 800ad14:	e19a      	b.n	800b04c <HAL_SD_IRQHandler+0x364>
+  }
+
+  else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DATAEND) != RESET)
+ 800ad16:	687b      	ldr	r3, [r7, #4]
+ 800ad18:	681b      	ldr	r3, [r3, #0]
+ 800ad1a:	6b5b      	ldr	r3, [r3, #52]	; 0x34
+ 800ad1c:	f403 7380 	and.w	r3, r3, #256	; 0x100
+ 800ad20:	2b00      	cmp	r3, #0
+ 800ad22:	f000 80ac 	beq.w	800ae7e <HAL_SD_IRQHandler+0x196>
+  {
+    __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DATAEND);
+ 800ad26:	687b      	ldr	r3, [r7, #4]
+ 800ad28:	681b      	ldr	r3, [r3, #0]
+ 800ad2a:	f44f 7280 	mov.w	r2, #256	; 0x100
+ 800ad2e:	639a      	str	r2, [r3, #56]	; 0x38
+
+    __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND  | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | \
+ 800ad30:	687b      	ldr	r3, [r7, #4]
+ 800ad32:	681b      	ldr	r3, [r3, #0]
+ 800ad34:	6bd9      	ldr	r1, [r3, #60]	; 0x3c
+ 800ad36:	687b      	ldr	r3, [r7, #4]
+ 800ad38:	681a      	ldr	r2, [r3, #0]
+ 800ad3a:	4b59      	ldr	r3, [pc, #356]	; (800aea0 <HAL_SD_IRQHandler+0x1b8>)
+ 800ad3c:	400b      	ands	r3, r1
+ 800ad3e:	63d3      	str	r3, [r2, #60]	; 0x3c
+                        SDMMC_IT_TXUNDERR | SDMMC_IT_RXOVERR  | SDMMC_IT_TXFIFOHE | \
+                        SDMMC_IT_RXFIFOHF);
+
+    __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_IDMABTC);
+ 800ad40:	687b      	ldr	r3, [r7, #4]
+ 800ad42:	681b      	ldr	r3, [r3, #0]
+ 800ad44:	6bda      	ldr	r2, [r3, #60]	; 0x3c
+ 800ad46:	687b      	ldr	r3, [r7, #4]
+ 800ad48:	681b      	ldr	r3, [r3, #0]
+ 800ad4a:	f022 5280 	bic.w	r2, r2, #268435456	; 0x10000000
+ 800ad4e:	63da      	str	r2, [r3, #60]	; 0x3c
+    __SDMMC_CMDTRANS_DISABLE(hsd->Instance);
+ 800ad50:	687b      	ldr	r3, [r7, #4]
+ 800ad52:	681b      	ldr	r3, [r3, #0]
+ 800ad54:	68da      	ldr	r2, [r3, #12]
+ 800ad56:	687b      	ldr	r3, [r7, #4]
+ 800ad58:	681b      	ldr	r3, [r3, #0]
+ 800ad5a:	f022 0240 	bic.w	r2, r2, #64	; 0x40
+ 800ad5e:	60da      	str	r2, [r3, #12]
+
+    if ((context & SD_CONTEXT_IT) != 0U)
+ 800ad60:	68fb      	ldr	r3, [r7, #12]
+ 800ad62:	f003 0308 	and.w	r3, r3, #8
+ 800ad66:	2b00      	cmp	r3, #0
+ 800ad68:	d038      	beq.n	800addc <HAL_SD_IRQHandler+0xf4>
+    {
+      if (((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U) || ((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U))
+ 800ad6a:	68fb      	ldr	r3, [r7, #12]
+ 800ad6c:	f003 0302 	and.w	r3, r3, #2
+ 800ad70:	2b00      	cmp	r3, #0
+ 800ad72:	d104      	bne.n	800ad7e <HAL_SD_IRQHandler+0x96>
+ 800ad74:	68fb      	ldr	r3, [r7, #12]
+ 800ad76:	f003 0320 	and.w	r3, r3, #32
+ 800ad7a:	2b00      	cmp	r3, #0
+ 800ad7c:	d011      	beq.n	800ada2 <HAL_SD_IRQHandler+0xba>
+      {
+        errorstate = SDMMC_CmdStopTransfer(hsd->Instance);
+ 800ad7e:	687b      	ldr	r3, [r7, #4]
+ 800ad80:	681b      	ldr	r3, [r3, #0]
+ 800ad82:	4618      	mov	r0, r3
+ 800ad84:	f003 fa28 	bl	800e1d8 <SDMMC_CmdStopTransfer>
+ 800ad88:	60b8      	str	r0, [r7, #8]
+        if (errorstate != HAL_SD_ERROR_NONE)
+ 800ad8a:	68bb      	ldr	r3, [r7, #8]
+ 800ad8c:	2b00      	cmp	r3, #0
+ 800ad8e:	d008      	beq.n	800ada2 <HAL_SD_IRQHandler+0xba>
+        {
+          hsd->ErrorCode |= errorstate;
+ 800ad90:	687b      	ldr	r3, [r7, #4]
+ 800ad92:	6b5a      	ldr	r2, [r3, #52]	; 0x34
+ 800ad94:	68bb      	ldr	r3, [r7, #8]
+ 800ad96:	431a      	orrs	r2, r3
+ 800ad98:	687b      	ldr	r3, [r7, #4]
+ 800ad9a:	635a      	str	r2, [r3, #52]	; 0x34
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+          hsd->ErrorCallback(hsd);
+#else
+          HAL_SD_ErrorCallback(hsd);
+ 800ad9c:	6878      	ldr	r0, [r7, #4]
+ 800ad9e:	f000 f95b 	bl	800b058 <HAL_SD_ErrorCallback>
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+        }
+      }
+
+      /* Clear all the static flags */
+      __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS);
+ 800ada2:	687b      	ldr	r3, [r7, #4]
+ 800ada4:	681b      	ldr	r3, [r3, #0]
+ 800ada6:	4a3f      	ldr	r2, [pc, #252]	; (800aea4 <HAL_SD_IRQHandler+0x1bc>)
+ 800ada8:	639a      	str	r2, [r3, #56]	; 0x38
+
+      hsd->State = HAL_SD_STATE_READY;
+ 800adaa:	687b      	ldr	r3, [r7, #4]
+ 800adac:	2201      	movs	r2, #1
+ 800adae:	f883 2030 	strb.w	r2, [r3, #48]	; 0x30
+      hsd->Context = SD_CONTEXT_NONE;
+ 800adb2:	687b      	ldr	r3, [r7, #4]
+ 800adb4:	2200      	movs	r2, #0
+ 800adb6:	62da      	str	r2, [r3, #44]	; 0x2c
+      if (((context & SD_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U))
+ 800adb8:	68fb      	ldr	r3, [r7, #12]
+ 800adba:	f003 0301 	and.w	r3, r3, #1
+ 800adbe:	2b00      	cmp	r3, #0
+ 800adc0:	d104      	bne.n	800adcc <HAL_SD_IRQHandler+0xe4>
+ 800adc2:	68fb      	ldr	r3, [r7, #12]
+ 800adc4:	f003 0302 	and.w	r3, r3, #2
+ 800adc8:	2b00      	cmp	r3, #0
+ 800adca:	d003      	beq.n	800add4 <HAL_SD_IRQHandler+0xec>
+      {
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+        hsd->RxCpltCallback(hsd);
+#else
+        HAL_SD_RxCpltCallback(hsd);
+ 800adcc:	6878      	ldr	r0, [r7, #4]
+ 800adce:	f003 fed3 	bl	800eb78 <HAL_SD_RxCpltCallback>
+ 800add2:	e13b      	b.n	800b04c <HAL_SD_IRQHandler+0x364>
+      else
+      {
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+        hsd->TxCpltCallback(hsd);
+#else
+        HAL_SD_TxCpltCallback(hsd);
+ 800add4:	6878      	ldr	r0, [r7, #4]
+ 800add6:	f003 fec5 	bl	800eb64 <HAL_SD_TxCpltCallback>
+  }
+  else
+  {
+    /* Nothing to do */
+  }
+}
+ 800adda:	e137      	b.n	800b04c <HAL_SD_IRQHandler+0x364>
+    else if ((context & SD_CONTEXT_DMA) != 0U)
+ 800addc:	68fb      	ldr	r3, [r7, #12]
+ 800adde:	f003 0380 	and.w	r3, r3, #128	; 0x80
+ 800ade2:	2b00      	cmp	r3, #0
+ 800ade4:	f000 8132 	beq.w	800b04c <HAL_SD_IRQHandler+0x364>
+      hsd->Instance->DLEN = 0;
+ 800ade8:	687b      	ldr	r3, [r7, #4]
+ 800adea:	681b      	ldr	r3, [r3, #0]
+ 800adec:	2200      	movs	r2, #0
+ 800adee:	629a      	str	r2, [r3, #40]	; 0x28
+      hsd->Instance->DCTRL = 0;
+ 800adf0:	687b      	ldr	r3, [r7, #4]
+ 800adf2:	681b      	ldr	r3, [r3, #0]
+ 800adf4:	2200      	movs	r2, #0
+ 800adf6:	62da      	str	r2, [r3, #44]	; 0x2c
+      hsd->Instance->IDMACTRL = SDMMC_DISABLE_IDMA;
+ 800adf8:	687b      	ldr	r3, [r7, #4]
+ 800adfa:	681b      	ldr	r3, [r3, #0]
+ 800adfc:	2200      	movs	r2, #0
+ 800adfe:	651a      	str	r2, [r3, #80]	; 0x50
+      if (((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U) || ((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U))
+ 800ae00:	68fb      	ldr	r3, [r7, #12]
+ 800ae02:	f003 0302 	and.w	r3, r3, #2
+ 800ae06:	2b00      	cmp	r3, #0
+ 800ae08:	d104      	bne.n	800ae14 <HAL_SD_IRQHandler+0x12c>
+ 800ae0a:	68fb      	ldr	r3, [r7, #12]
+ 800ae0c:	f003 0320 	and.w	r3, r3, #32
+ 800ae10:	2b00      	cmp	r3, #0
+ 800ae12:	d011      	beq.n	800ae38 <HAL_SD_IRQHandler+0x150>
+        errorstate = SDMMC_CmdStopTransfer(hsd->Instance);
+ 800ae14:	687b      	ldr	r3, [r7, #4]
+ 800ae16:	681b      	ldr	r3, [r3, #0]
+ 800ae18:	4618      	mov	r0, r3
+ 800ae1a:	f003 f9dd 	bl	800e1d8 <SDMMC_CmdStopTransfer>
+ 800ae1e:	60b8      	str	r0, [r7, #8]
+        if (errorstate != HAL_SD_ERROR_NONE)
+ 800ae20:	68bb      	ldr	r3, [r7, #8]
+ 800ae22:	2b00      	cmp	r3, #0
+ 800ae24:	d008      	beq.n	800ae38 <HAL_SD_IRQHandler+0x150>
+          hsd->ErrorCode |= errorstate;
+ 800ae26:	687b      	ldr	r3, [r7, #4]
+ 800ae28:	6b5a      	ldr	r2, [r3, #52]	; 0x34
+ 800ae2a:	68bb      	ldr	r3, [r7, #8]
+ 800ae2c:	431a      	orrs	r2, r3
+ 800ae2e:	687b      	ldr	r3, [r7, #4]
+ 800ae30:	635a      	str	r2, [r3, #52]	; 0x34
+          HAL_SD_ErrorCallback(hsd);
+ 800ae32:	6878      	ldr	r0, [r7, #4]
+ 800ae34:	f000 f910 	bl	800b058 <HAL_SD_ErrorCallback>
+      hsd->State = HAL_SD_STATE_READY;
+ 800ae38:	687b      	ldr	r3, [r7, #4]
+ 800ae3a:	2201      	movs	r2, #1
+ 800ae3c:	f883 2030 	strb.w	r2, [r3, #48]	; 0x30
+      hsd->Context = SD_CONTEXT_NONE;
+ 800ae40:	687b      	ldr	r3, [r7, #4]
+ 800ae42:	2200      	movs	r2, #0
+ 800ae44:	62da      	str	r2, [r3, #44]	; 0x2c
+      if (((context & SD_CONTEXT_WRITE_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U))
+ 800ae46:	68fb      	ldr	r3, [r7, #12]
+ 800ae48:	f003 0310 	and.w	r3, r3, #16
+ 800ae4c:	2b00      	cmp	r3, #0
+ 800ae4e:	d104      	bne.n	800ae5a <HAL_SD_IRQHandler+0x172>
+ 800ae50:	68fb      	ldr	r3, [r7, #12]
+ 800ae52:	f003 0320 	and.w	r3, r3, #32
+ 800ae56:	2b00      	cmp	r3, #0
+ 800ae58:	d002      	beq.n	800ae60 <HAL_SD_IRQHandler+0x178>
+        HAL_SD_TxCpltCallback(hsd);
+ 800ae5a:	6878      	ldr	r0, [r7, #4]
+ 800ae5c:	f003 fe82 	bl	800eb64 <HAL_SD_TxCpltCallback>
+      if (((context & SD_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U))
+ 800ae60:	68fb      	ldr	r3, [r7, #12]
+ 800ae62:	f003 0301 	and.w	r3, r3, #1
+ 800ae66:	2b00      	cmp	r3, #0
+ 800ae68:	d105      	bne.n	800ae76 <HAL_SD_IRQHandler+0x18e>
+ 800ae6a:	68fb      	ldr	r3, [r7, #12]
+ 800ae6c:	f003 0302 	and.w	r3, r3, #2
+ 800ae70:	2b00      	cmp	r3, #0
+ 800ae72:	f000 80eb 	beq.w	800b04c <HAL_SD_IRQHandler+0x364>
+        HAL_SD_RxCpltCallback(hsd);
+ 800ae76:	6878      	ldr	r0, [r7, #4]
+ 800ae78:	f003 fe7e 	bl	800eb78 <HAL_SD_RxCpltCallback>
+}
+ 800ae7c:	e0e6      	b.n	800b04c <HAL_SD_IRQHandler+0x364>
+  else if ((__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXFIFOHE) != RESET) && ((context & SD_CONTEXT_IT) != 0U))
+ 800ae7e:	687b      	ldr	r3, [r7, #4]
+ 800ae80:	681b      	ldr	r3, [r3, #0]
+ 800ae82:	6b5b      	ldr	r3, [r3, #52]	; 0x34
+ 800ae84:	f403 4380 	and.w	r3, r3, #16384	; 0x4000
+ 800ae88:	2b00      	cmp	r3, #0
+ 800ae8a:	d00d      	beq.n	800aea8 <HAL_SD_IRQHandler+0x1c0>
+ 800ae8c:	68fb      	ldr	r3, [r7, #12]
+ 800ae8e:	f003 0308 	and.w	r3, r3, #8
+ 800ae92:	2b00      	cmp	r3, #0
+ 800ae94:	d008      	beq.n	800aea8 <HAL_SD_IRQHandler+0x1c0>
+    SD_Write_IT(hsd);
+ 800ae96:	6878      	ldr	r0, [r7, #4]
+ 800ae98:	f001 f8a8 	bl	800bfec <SD_Write_IT>
+ 800ae9c:	e0d6      	b.n	800b04c <HAL_SD_IRQHandler+0x364>
+ 800ae9e:	bf00      	nop
+ 800aea0:	ffff3ec5 	.word	0xffff3ec5
+ 800aea4:	18000f3a 	.word	0x18000f3a
+  else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_RXOVERR |
+ 800aea8:	687b      	ldr	r3, [r7, #4]
+ 800aeaa:	681b      	ldr	r3, [r3, #0]
+ 800aeac:	6b5b      	ldr	r3, [r3, #52]	; 0x34
+ 800aeae:	f003 033a 	and.w	r3, r3, #58	; 0x3a
+ 800aeb2:	2b00      	cmp	r3, #0
+ 800aeb4:	f000 809d 	beq.w	800aff2 <HAL_SD_IRQHandler+0x30a>
+    if (__HAL_SD_GET_FLAG(hsd, SDMMC_IT_DCRCFAIL) != RESET)
+ 800aeb8:	687b      	ldr	r3, [r7, #4]
+ 800aeba:	681b      	ldr	r3, [r3, #0]
+ 800aebc:	6b5b      	ldr	r3, [r3, #52]	; 0x34
+ 800aebe:	f003 0302 	and.w	r3, r3, #2
+ 800aec2:	2b00      	cmp	r3, #0
+ 800aec4:	d005      	beq.n	800aed2 <HAL_SD_IRQHandler+0x1ea>
+      hsd->ErrorCode |= HAL_SD_ERROR_DATA_CRC_FAIL;
+ 800aec6:	687b      	ldr	r3, [r7, #4]
+ 800aec8:	6b5b      	ldr	r3, [r3, #52]	; 0x34
+ 800aeca:	f043 0202 	orr.w	r2, r3, #2
+ 800aece:	687b      	ldr	r3, [r7, #4]
+ 800aed0:	635a      	str	r2, [r3, #52]	; 0x34
+    if (__HAL_SD_GET_FLAG(hsd, SDMMC_IT_DTIMEOUT) != RESET)
+ 800aed2:	687b      	ldr	r3, [r7, #4]
+ 800aed4:	681b      	ldr	r3, [r3, #0]
+ 800aed6:	6b5b      	ldr	r3, [r3, #52]	; 0x34
+ 800aed8:	f003 0308 	and.w	r3, r3, #8
+ 800aedc:	2b00      	cmp	r3, #0
+ 800aede:	d005      	beq.n	800aeec <HAL_SD_IRQHandler+0x204>
+      hsd->ErrorCode |= HAL_SD_ERROR_DATA_TIMEOUT;
+ 800aee0:	687b      	ldr	r3, [r7, #4]
+ 800aee2:	6b5b      	ldr	r3, [r3, #52]	; 0x34
+ 800aee4:	f043 0208 	orr.w	r2, r3, #8
+ 800aee8:	687b      	ldr	r3, [r7, #4]
+ 800aeea:	635a      	str	r2, [r3, #52]	; 0x34
+    if (__HAL_SD_GET_FLAG(hsd, SDMMC_IT_RXOVERR) != RESET)
+ 800aeec:	687b      	ldr	r3, [r7, #4]
+ 800aeee:	681b      	ldr	r3, [r3, #0]
+ 800aef0:	6b5b      	ldr	r3, [r3, #52]	; 0x34
+ 800aef2:	f003 0320 	and.w	r3, r3, #32
+ 800aef6:	2b00      	cmp	r3, #0
+ 800aef8:	d005      	beq.n	800af06 <HAL_SD_IRQHandler+0x21e>
+      hsd->ErrorCode |= HAL_SD_ERROR_RX_OVERRUN;
+ 800aefa:	687b      	ldr	r3, [r7, #4]
+ 800aefc:	6b5b      	ldr	r3, [r3, #52]	; 0x34
+ 800aefe:	f043 0220 	orr.w	r2, r3, #32
+ 800af02:	687b      	ldr	r3, [r7, #4]
+ 800af04:	635a      	str	r2, [r3, #52]	; 0x34
+    if (__HAL_SD_GET_FLAG(hsd, SDMMC_IT_TXUNDERR) != RESET)
+ 800af06:	687b      	ldr	r3, [r7, #4]
+ 800af08:	681b      	ldr	r3, [r3, #0]
+ 800af0a:	6b5b      	ldr	r3, [r3, #52]	; 0x34
+ 800af0c:	f003 0310 	and.w	r3, r3, #16
+ 800af10:	2b00      	cmp	r3, #0
+ 800af12:	d005      	beq.n	800af20 <HAL_SD_IRQHandler+0x238>
+      hsd->ErrorCode |= HAL_SD_ERROR_TX_UNDERRUN;
+ 800af14:	687b      	ldr	r3, [r7, #4]
+ 800af16:	6b5b      	ldr	r3, [r3, #52]	; 0x34
+ 800af18:	f043 0210 	orr.w	r2, r3, #16
+ 800af1c:	687b      	ldr	r3, [r7, #4]
+ 800af1e:	635a      	str	r2, [r3, #52]	; 0x34
+    __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS);
+ 800af20:	687b      	ldr	r3, [r7, #4]
+ 800af22:	681b      	ldr	r3, [r3, #0]
+ 800af24:	4a4b      	ldr	r2, [pc, #300]	; (800b054 <HAL_SD_IRQHandler+0x36c>)
+ 800af26:	639a      	str	r2, [r3, #56]	; 0x38
+    __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | \
+ 800af28:	687b      	ldr	r3, [r7, #4]
+ 800af2a:	681b      	ldr	r3, [r3, #0]
+ 800af2c:	6bda      	ldr	r2, [r3, #60]	; 0x3c
+ 800af2e:	687b      	ldr	r3, [r7, #4]
+ 800af30:	681b      	ldr	r3, [r3, #0]
+ 800af32:	f422 729d 	bic.w	r2, r2, #314	; 0x13a
+ 800af36:	63da      	str	r2, [r3, #60]	; 0x3c
+    __SDMMC_CMDTRANS_DISABLE(hsd->Instance);
+ 800af38:	687b      	ldr	r3, [r7, #4]
+ 800af3a:	681b      	ldr	r3, [r3, #0]
+ 800af3c:	68da      	ldr	r2, [r3, #12]
+ 800af3e:	687b      	ldr	r3, [r7, #4]
+ 800af40:	681b      	ldr	r3, [r3, #0]
+ 800af42:	f022 0240 	bic.w	r2, r2, #64	; 0x40
+ 800af46:	60da      	str	r2, [r3, #12]
+    hsd->Instance->DCTRL |= SDMMC_DCTRL_FIFORST;
+ 800af48:	687b      	ldr	r3, [r7, #4]
+ 800af4a:	681b      	ldr	r3, [r3, #0]
+ 800af4c:	6ada      	ldr	r2, [r3, #44]	; 0x2c
+ 800af4e:	687b      	ldr	r3, [r7, #4]
+ 800af50:	681b      	ldr	r3, [r3, #0]
+ 800af52:	f442 5200 	orr.w	r2, r2, #8192	; 0x2000
+ 800af56:	62da      	str	r2, [r3, #44]	; 0x2c
+    hsd->Instance->CMD |= SDMMC_CMD_CMDSTOP;
+ 800af58:	687b      	ldr	r3, [r7, #4]
+ 800af5a:	681b      	ldr	r3, [r3, #0]
+ 800af5c:	68da      	ldr	r2, [r3, #12]
+ 800af5e:	687b      	ldr	r3, [r7, #4]
+ 800af60:	681b      	ldr	r3, [r3, #0]
+ 800af62:	f042 0280 	orr.w	r2, r2, #128	; 0x80
+ 800af66:	60da      	str	r2, [r3, #12]
+    hsd->ErrorCode |= SDMMC_CmdStopTransfer(hsd->Instance);
+ 800af68:	687b      	ldr	r3, [r7, #4]
+ 800af6a:	681b      	ldr	r3, [r3, #0]
+ 800af6c:	4618      	mov	r0, r3
+ 800af6e:	f003 f933 	bl	800e1d8 <SDMMC_CmdStopTransfer>
+ 800af72:	4602      	mov	r2, r0
+ 800af74:	687b      	ldr	r3, [r7, #4]
+ 800af76:	6b5b      	ldr	r3, [r3, #52]	; 0x34
+ 800af78:	431a      	orrs	r2, r3
+ 800af7a:	687b      	ldr	r3, [r7, #4]
+ 800af7c:	635a      	str	r2, [r3, #52]	; 0x34
+    hsd->Instance->CMD &= ~(SDMMC_CMD_CMDSTOP);
+ 800af7e:	687b      	ldr	r3, [r7, #4]
+ 800af80:	681b      	ldr	r3, [r3, #0]
+ 800af82:	68da      	ldr	r2, [r3, #12]
+ 800af84:	687b      	ldr	r3, [r7, #4]
+ 800af86:	681b      	ldr	r3, [r3, #0]
+ 800af88:	f022 0280 	bic.w	r2, r2, #128	; 0x80
+ 800af8c:	60da      	str	r2, [r3, #12]
+    __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DABORT);
+ 800af8e:	687b      	ldr	r3, [r7, #4]
+ 800af90:	681b      	ldr	r3, [r3, #0]
+ 800af92:	f44f 6200 	mov.w	r2, #2048	; 0x800
+ 800af96:	639a      	str	r2, [r3, #56]	; 0x38
+    if ((context & SD_CONTEXT_IT) != 0U)
+ 800af98:	68fb      	ldr	r3, [r7, #12]
+ 800af9a:	f003 0308 	and.w	r3, r3, #8
+ 800af9e:	2b00      	cmp	r3, #0
+ 800afa0:	d00a      	beq.n	800afb8 <HAL_SD_IRQHandler+0x2d0>
+      hsd->State = HAL_SD_STATE_READY;
+ 800afa2:	687b      	ldr	r3, [r7, #4]
+ 800afa4:	2201      	movs	r2, #1
+ 800afa6:	f883 2030 	strb.w	r2, [r3, #48]	; 0x30
+      hsd->Context = SD_CONTEXT_NONE;
+ 800afaa:	687b      	ldr	r3, [r7, #4]
+ 800afac:	2200      	movs	r2, #0
+ 800afae:	62da      	str	r2, [r3, #44]	; 0x2c
+      HAL_SD_ErrorCallback(hsd);
+ 800afb0:	6878      	ldr	r0, [r7, #4]
+ 800afb2:	f000 f851 	bl	800b058 <HAL_SD_ErrorCallback>
+}
+ 800afb6:	e049      	b.n	800b04c <HAL_SD_IRQHandler+0x364>
+    else if ((context & SD_CONTEXT_DMA) != 0U)
+ 800afb8:	68fb      	ldr	r3, [r7, #12]
+ 800afba:	f003 0380 	and.w	r3, r3, #128	; 0x80
+ 800afbe:	2b00      	cmp	r3, #0
+ 800afc0:	d044      	beq.n	800b04c <HAL_SD_IRQHandler+0x364>
+      if (hsd->ErrorCode != HAL_SD_ERROR_NONE)
+ 800afc2:	687b      	ldr	r3, [r7, #4]
+ 800afc4:	6b5b      	ldr	r3, [r3, #52]	; 0x34
+ 800afc6:	2b00      	cmp	r3, #0
+ 800afc8:	d040      	beq.n	800b04c <HAL_SD_IRQHandler+0x364>
+        __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_IDMABTC);
+ 800afca:	687b      	ldr	r3, [r7, #4]
+ 800afcc:	681b      	ldr	r3, [r3, #0]
+ 800afce:	6bda      	ldr	r2, [r3, #60]	; 0x3c
+ 800afd0:	687b      	ldr	r3, [r7, #4]
+ 800afd2:	681b      	ldr	r3, [r3, #0]
+ 800afd4:	f022 5280 	bic.w	r2, r2, #268435456	; 0x10000000
+ 800afd8:	63da      	str	r2, [r3, #60]	; 0x3c
+        hsd->Instance->IDMACTRL = SDMMC_DISABLE_IDMA;
+ 800afda:	687b      	ldr	r3, [r7, #4]
+ 800afdc:	681b      	ldr	r3, [r3, #0]
+ 800afde:	2200      	movs	r2, #0
+ 800afe0:	651a      	str	r2, [r3, #80]	; 0x50
+        hsd->State = HAL_SD_STATE_READY;
+ 800afe2:	687b      	ldr	r3, [r7, #4]
+ 800afe4:	2201      	movs	r2, #1
+ 800afe6:	f883 2030 	strb.w	r2, [r3, #48]	; 0x30
+        HAL_SD_ErrorCallback(hsd);
+ 800afea:	6878      	ldr	r0, [r7, #4]
+ 800afec:	f000 f834 	bl	800b058 <HAL_SD_ErrorCallback>
+}
+ 800aff0:	e02c      	b.n	800b04c <HAL_SD_IRQHandler+0x364>
+  else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_IDMABTC) != RESET)
+ 800aff2:	687b      	ldr	r3, [r7, #4]
+ 800aff4:	681b      	ldr	r3, [r3, #0]
+ 800aff6:	6b5b      	ldr	r3, [r3, #52]	; 0x34
+ 800aff8:	f003 5380 	and.w	r3, r3, #268435456	; 0x10000000
+ 800affc:	2b00      	cmp	r3, #0
+ 800affe:	d025      	beq.n	800b04c <HAL_SD_IRQHandler+0x364>
+    __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_IDMABTC);
+ 800b000:	687b      	ldr	r3, [r7, #4]
+ 800b002:	681b      	ldr	r3, [r3, #0]
+ 800b004:	f04f 5280 	mov.w	r2, #268435456	; 0x10000000
+ 800b008:	639a      	str	r2, [r3, #56]	; 0x38
+    if (READ_BIT(hsd->Instance->IDMACTRL, SDMMC_IDMA_IDMABACT) == 0U)
+ 800b00a:	687b      	ldr	r3, [r7, #4]
+ 800b00c:	681b      	ldr	r3, [r3, #0]
+ 800b00e:	6d1b      	ldr	r3, [r3, #80]	; 0x50
+ 800b010:	f003 0304 	and.w	r3, r3, #4
+ 800b014:	2b00      	cmp	r3, #0
+ 800b016:	d10c      	bne.n	800b032 <HAL_SD_IRQHandler+0x34a>
+      if ((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U)
+ 800b018:	68fb      	ldr	r3, [r7, #12]
+ 800b01a:	f003 0320 	and.w	r3, r3, #32
+ 800b01e:	2b00      	cmp	r3, #0
+ 800b020:	d003      	beq.n	800b02a <HAL_SD_IRQHandler+0x342>
+        HAL_SDEx_Write_DMADoubleBuf1CpltCallback(hsd);
+ 800b022:	6878      	ldr	r0, [r7, #4]
+ 800b024:	f001 f84a 	bl	800c0bc <HAL_SDEx_Write_DMADoubleBuf1CpltCallback>
+}
+ 800b028:	e010      	b.n	800b04c <HAL_SD_IRQHandler+0x364>
+        HAL_SDEx_Read_DMADoubleBuf1CpltCallback(hsd);
+ 800b02a:	6878      	ldr	r0, [r7, #4]
+ 800b02c:	f001 f832 	bl	800c094 <HAL_SDEx_Read_DMADoubleBuf1CpltCallback>
+}
+ 800b030:	e00c      	b.n	800b04c <HAL_SD_IRQHandler+0x364>
+      if ((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U)
+ 800b032:	68fb      	ldr	r3, [r7, #12]
+ 800b034:	f003 0320 	and.w	r3, r3, #32
+ 800b038:	2b00      	cmp	r3, #0
+ 800b03a:	d003      	beq.n	800b044 <HAL_SD_IRQHandler+0x35c>
+        HAL_SDEx_Write_DMADoubleBuf0CpltCallback(hsd);
+ 800b03c:	6878      	ldr	r0, [r7, #4]
+ 800b03e:	f001 f833 	bl	800c0a8 <HAL_SDEx_Write_DMADoubleBuf0CpltCallback>
+}
+ 800b042:	e003      	b.n	800b04c <HAL_SD_IRQHandler+0x364>
+        HAL_SDEx_Read_DMADoubleBuf0CpltCallback(hsd);
+ 800b044:	6878      	ldr	r0, [r7, #4]
+ 800b046:	f001 f81b 	bl	800c080 <HAL_SDEx_Read_DMADoubleBuf0CpltCallback>
+}
+ 800b04a:	e7ff      	b.n	800b04c <HAL_SD_IRQHandler+0x364>
+ 800b04c:	bf00      	nop
+ 800b04e:	3710      	adds	r7, #16
+ 800b050:	46bd      	mov	sp, r7
+ 800b052:	bd80      	pop	{r7, pc}
+ 800b054:	18000f3a 	.word	0x18000f3a
+
+0800b058 <HAL_SD_ErrorCallback>:
+  * @brief SD error callbacks
+  * @param hsd: Pointer SD handle
+  * @retval None
+  */
+__weak void HAL_SD_ErrorCallback(SD_HandleTypeDef *hsd)
+{
+ 800b058:	b480      	push	{r7}
+ 800b05a:	b083      	sub	sp, #12
+ 800b05c:	af00      	add	r7, sp, #0
+ 800b05e:	6078      	str	r0, [r7, #4]
+  UNUSED(hsd);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SD_ErrorCallback can be implemented in the user file
+   */
+}
+ 800b060:	bf00      	nop
+ 800b062:	370c      	adds	r7, #12
+ 800b064:	46bd      	mov	sp, r7
+ 800b066:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 800b06a:	4770      	bx	lr
+
+0800b06c <HAL_SD_GetCardCSD>:
+  * @param  pCSD: Pointer to a HAL_SD_CardCSDTypeDef structure that
+  *         contains all CSD register parameters
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SD_GetCardCSD(SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypeDef *pCSD)
+{
+ 800b06c:	b480      	push	{r7}
+ 800b06e:	b083      	sub	sp, #12
+ 800b070:	af00      	add	r7, sp, #0
+ 800b072:	6078      	str	r0, [r7, #4]
+ 800b074:	6039      	str	r1, [r7, #0]
+  pCSD->CSDStruct = (uint8_t)((hsd->CSD[0] & 0xC0000000U) >> 30U);
+ 800b076:	687b      	ldr	r3, [r7, #4]
+ 800b078:	6ddb      	ldr	r3, [r3, #92]	; 0x5c
+ 800b07a:	0f9b      	lsrs	r3, r3, #30
+ 800b07c:	b2da      	uxtb	r2, r3
+ 800b07e:	683b      	ldr	r3, [r7, #0]
+ 800b080:	701a      	strb	r2, [r3, #0]
+
+  pCSD->SysSpecVersion = (uint8_t)((hsd->CSD[0] & 0x3C000000U) >> 26U);
+ 800b082:	687b      	ldr	r3, [r7, #4]
+ 800b084:	6ddb      	ldr	r3, [r3, #92]	; 0x5c
+ 800b086:	0e9b      	lsrs	r3, r3, #26
+ 800b088:	b2db      	uxtb	r3, r3
+ 800b08a:	f003 030f 	and.w	r3, r3, #15
+ 800b08e:	b2da      	uxtb	r2, r3
+ 800b090:	683b      	ldr	r3, [r7, #0]
+ 800b092:	705a      	strb	r2, [r3, #1]
+
+  pCSD->Reserved1 = (uint8_t)((hsd->CSD[0] & 0x03000000U) >> 24U);
+ 800b094:	687b      	ldr	r3, [r7, #4]
+ 800b096:	6ddb      	ldr	r3, [r3, #92]	; 0x5c
+ 800b098:	0e1b      	lsrs	r3, r3, #24
+ 800b09a:	b2db      	uxtb	r3, r3
+ 800b09c:	f003 0303 	and.w	r3, r3, #3
+ 800b0a0:	b2da      	uxtb	r2, r3
+ 800b0a2:	683b      	ldr	r3, [r7, #0]
+ 800b0a4:	709a      	strb	r2, [r3, #2]
+
+  pCSD->TAAC = (uint8_t)((hsd->CSD[0] & 0x00FF0000U) >> 16U);
+ 800b0a6:	687b      	ldr	r3, [r7, #4]
+ 800b0a8:	6ddb      	ldr	r3, [r3, #92]	; 0x5c
+ 800b0aa:	0c1b      	lsrs	r3, r3, #16
+ 800b0ac:	b2da      	uxtb	r2, r3
+ 800b0ae:	683b      	ldr	r3, [r7, #0]
+ 800b0b0:	70da      	strb	r2, [r3, #3]
+
+  pCSD->NSAC = (uint8_t)((hsd->CSD[0] & 0x0000FF00U) >> 8U);
+ 800b0b2:	687b      	ldr	r3, [r7, #4]
+ 800b0b4:	6ddb      	ldr	r3, [r3, #92]	; 0x5c
+ 800b0b6:	0a1b      	lsrs	r3, r3, #8
+ 800b0b8:	b2da      	uxtb	r2, r3
+ 800b0ba:	683b      	ldr	r3, [r7, #0]
+ 800b0bc:	711a      	strb	r2, [r3, #4]
+
+  pCSD->MaxBusClkFrec = (uint8_t)(hsd->CSD[0] & 0x000000FFU);
+ 800b0be:	687b      	ldr	r3, [r7, #4]
+ 800b0c0:	6ddb      	ldr	r3, [r3, #92]	; 0x5c
+ 800b0c2:	b2da      	uxtb	r2, r3
+ 800b0c4:	683b      	ldr	r3, [r7, #0]
+ 800b0c6:	715a      	strb	r2, [r3, #5]
+
+  pCSD->CardComdClasses = (uint16_t)((hsd->CSD[1] & 0xFFF00000U) >> 20U);
+ 800b0c8:	687b      	ldr	r3, [r7, #4]
+ 800b0ca:	6e1b      	ldr	r3, [r3, #96]	; 0x60
+ 800b0cc:	0d1b      	lsrs	r3, r3, #20
+ 800b0ce:	b29a      	uxth	r2, r3
+ 800b0d0:	683b      	ldr	r3, [r7, #0]
+ 800b0d2:	80da      	strh	r2, [r3, #6]
+
+  pCSD->RdBlockLen = (uint8_t)((hsd->CSD[1] & 0x000F0000U) >> 16U);
+ 800b0d4:	687b      	ldr	r3, [r7, #4]
+ 800b0d6:	6e1b      	ldr	r3, [r3, #96]	; 0x60
+ 800b0d8:	0c1b      	lsrs	r3, r3, #16
+ 800b0da:	b2db      	uxtb	r3, r3
+ 800b0dc:	f003 030f 	and.w	r3, r3, #15
+ 800b0e0:	b2da      	uxtb	r2, r3
+ 800b0e2:	683b      	ldr	r3, [r7, #0]
+ 800b0e4:	721a      	strb	r2, [r3, #8]
+
+  pCSD->PartBlockRead   = (uint8_t)((hsd->CSD[1] & 0x00008000U) >> 15U);
+ 800b0e6:	687b      	ldr	r3, [r7, #4]
+ 800b0e8:	6e1b      	ldr	r3, [r3, #96]	; 0x60
+ 800b0ea:	0bdb      	lsrs	r3, r3, #15
+ 800b0ec:	b2db      	uxtb	r3, r3
+ 800b0ee:	f003 0301 	and.w	r3, r3, #1
+ 800b0f2:	b2da      	uxtb	r2, r3
+ 800b0f4:	683b      	ldr	r3, [r7, #0]
+ 800b0f6:	725a      	strb	r2, [r3, #9]
+
+  pCSD->WrBlockMisalign = (uint8_t)((hsd->CSD[1] & 0x00004000U) >> 14U);
+ 800b0f8:	687b      	ldr	r3, [r7, #4]
+ 800b0fa:	6e1b      	ldr	r3, [r3, #96]	; 0x60
+ 800b0fc:	0b9b      	lsrs	r3, r3, #14
+ 800b0fe:	b2db      	uxtb	r3, r3
+ 800b100:	f003 0301 	and.w	r3, r3, #1
+ 800b104:	b2da      	uxtb	r2, r3
+ 800b106:	683b      	ldr	r3, [r7, #0]
+ 800b108:	729a      	strb	r2, [r3, #10]
+
+  pCSD->RdBlockMisalign = (uint8_t)((hsd->CSD[1] & 0x00002000U) >> 13U);
+ 800b10a:	687b      	ldr	r3, [r7, #4]
+ 800b10c:	6e1b      	ldr	r3, [r3, #96]	; 0x60
+ 800b10e:	0b5b      	lsrs	r3, r3, #13
+ 800b110:	b2db      	uxtb	r3, r3
+ 800b112:	f003 0301 	and.w	r3, r3, #1
+ 800b116:	b2da      	uxtb	r2, r3
+ 800b118:	683b      	ldr	r3, [r7, #0]
+ 800b11a:	72da      	strb	r2, [r3, #11]
+
+  pCSD->DSRImpl = (uint8_t)((hsd->CSD[1] & 0x00001000U) >> 12U);
+ 800b11c:	687b      	ldr	r3, [r7, #4]
+ 800b11e:	6e1b      	ldr	r3, [r3, #96]	; 0x60
+ 800b120:	0b1b      	lsrs	r3, r3, #12
+ 800b122:	b2db      	uxtb	r3, r3
+ 800b124:	f003 0301 	and.w	r3, r3, #1
+ 800b128:	b2da      	uxtb	r2, r3
+ 800b12a:	683b      	ldr	r3, [r7, #0]
+ 800b12c:	731a      	strb	r2, [r3, #12]
+
+  pCSD->Reserved2 = 0U; /*!< Reserved */
+ 800b12e:	683b      	ldr	r3, [r7, #0]
+ 800b130:	2200      	movs	r2, #0
+ 800b132:	735a      	strb	r2, [r3, #13]
+
+  if (hsd->SdCard.CardType == CARD_SDSC)
+ 800b134:	687b      	ldr	r3, [r7, #4]
+ 800b136:	6b9b      	ldr	r3, [r3, #56]	; 0x38
+ 800b138:	2b00      	cmp	r3, #0
+ 800b13a:	d163      	bne.n	800b204 <HAL_SD_GetCardCSD+0x198>
+  {
+    pCSD->DeviceSize = (((hsd->CSD[1] & 0x000003FFU) << 2U) | ((hsd->CSD[2] & 0xC0000000U) >> 30U));
+ 800b13c:	687b      	ldr	r3, [r7, #4]
+ 800b13e:	6e1b      	ldr	r3, [r3, #96]	; 0x60
+ 800b140:	009a      	lsls	r2, r3, #2
+ 800b142:	f640 73fc 	movw	r3, #4092	; 0xffc
+ 800b146:	4013      	ands	r3, r2
+ 800b148:	687a      	ldr	r2, [r7, #4]
+ 800b14a:	6e52      	ldr	r2, [r2, #100]	; 0x64
+ 800b14c:	0f92      	lsrs	r2, r2, #30
+ 800b14e:	431a      	orrs	r2, r3
+ 800b150:	683b      	ldr	r3, [r7, #0]
+ 800b152:	611a      	str	r2, [r3, #16]
+
+    pCSD->MaxRdCurrentVDDMin = (uint8_t)((hsd->CSD[2] & 0x38000000U) >> 27U);
+ 800b154:	687b      	ldr	r3, [r7, #4]
+ 800b156:	6e5b      	ldr	r3, [r3, #100]	; 0x64
+ 800b158:	0edb      	lsrs	r3, r3, #27
+ 800b15a:	b2db      	uxtb	r3, r3
+ 800b15c:	f003 0307 	and.w	r3, r3, #7
+ 800b160:	b2da      	uxtb	r2, r3
+ 800b162:	683b      	ldr	r3, [r7, #0]
+ 800b164:	751a      	strb	r2, [r3, #20]
+
+    pCSD->MaxRdCurrentVDDMax = (uint8_t)((hsd->CSD[2] & 0x07000000U) >> 24U);
+ 800b166:	687b      	ldr	r3, [r7, #4]
+ 800b168:	6e5b      	ldr	r3, [r3, #100]	; 0x64
+ 800b16a:	0e1b      	lsrs	r3, r3, #24
+ 800b16c:	b2db      	uxtb	r3, r3
+ 800b16e:	f003 0307 	and.w	r3, r3, #7
+ 800b172:	b2da      	uxtb	r2, r3
+ 800b174:	683b      	ldr	r3, [r7, #0]
+ 800b176:	755a      	strb	r2, [r3, #21]
+
+    pCSD->MaxWrCurrentVDDMin = (uint8_t)((hsd->CSD[2] & 0x00E00000U) >> 21U);
+ 800b178:	687b      	ldr	r3, [r7, #4]
+ 800b17a:	6e5b      	ldr	r3, [r3, #100]	; 0x64
+ 800b17c:	0d5b      	lsrs	r3, r3, #21
+ 800b17e:	b2db      	uxtb	r3, r3
+ 800b180:	f003 0307 	and.w	r3, r3, #7
+ 800b184:	b2da      	uxtb	r2, r3
+ 800b186:	683b      	ldr	r3, [r7, #0]
+ 800b188:	759a      	strb	r2, [r3, #22]
+
+    pCSD->MaxWrCurrentVDDMax = (uint8_t)((hsd->CSD[2] & 0x001C0000U) >> 18U);
+ 800b18a:	687b      	ldr	r3, [r7, #4]
+ 800b18c:	6e5b      	ldr	r3, [r3, #100]	; 0x64
+ 800b18e:	0c9b      	lsrs	r3, r3, #18
+ 800b190:	b2db      	uxtb	r3, r3
+ 800b192:	f003 0307 	and.w	r3, r3, #7
+ 800b196:	b2da      	uxtb	r2, r3
+ 800b198:	683b      	ldr	r3, [r7, #0]
+ 800b19a:	75da      	strb	r2, [r3, #23]
+
+    pCSD->DeviceSizeMul = (uint8_t)((hsd->CSD[2] & 0x00038000U) >> 15U);
+ 800b19c:	687b      	ldr	r3, [r7, #4]
+ 800b19e:	6e5b      	ldr	r3, [r3, #100]	; 0x64
+ 800b1a0:	0bdb      	lsrs	r3, r3, #15
+ 800b1a2:	b2db      	uxtb	r3, r3
+ 800b1a4:	f003 0307 	and.w	r3, r3, #7
+ 800b1a8:	b2da      	uxtb	r2, r3
+ 800b1aa:	683b      	ldr	r3, [r7, #0]
+ 800b1ac:	761a      	strb	r2, [r3, #24]
+
+    hsd->SdCard.BlockNbr  = (pCSD->DeviceSize + 1U) ;
+ 800b1ae:	683b      	ldr	r3, [r7, #0]
+ 800b1b0:	691b      	ldr	r3, [r3, #16]
+ 800b1b2:	1c5a      	adds	r2, r3, #1
+ 800b1b4:	687b      	ldr	r3, [r7, #4]
+ 800b1b6:	649a      	str	r2, [r3, #72]	; 0x48
+    hsd->SdCard.BlockNbr *= (1UL << ((pCSD->DeviceSizeMul & 0x07U) + 2U));
+ 800b1b8:	683b      	ldr	r3, [r7, #0]
+ 800b1ba:	7e1b      	ldrb	r3, [r3, #24]
+ 800b1bc:	b2db      	uxtb	r3, r3
+ 800b1be:	f003 0307 	and.w	r3, r3, #7
+ 800b1c2:	3302      	adds	r3, #2
+ 800b1c4:	2201      	movs	r2, #1
+ 800b1c6:	fa02 f303 	lsl.w	r3, r2, r3
+ 800b1ca:	687a      	ldr	r2, [r7, #4]
+ 800b1cc:	6c92      	ldr	r2, [r2, #72]	; 0x48
+ 800b1ce:	fb03 f202 	mul.w	r2, r3, r2
+ 800b1d2:	687b      	ldr	r3, [r7, #4]
+ 800b1d4:	649a      	str	r2, [r3, #72]	; 0x48
+    hsd->SdCard.BlockSize = (1UL << (pCSD->RdBlockLen & 0x0FU));
+ 800b1d6:	683b      	ldr	r3, [r7, #0]
+ 800b1d8:	7a1b      	ldrb	r3, [r3, #8]
+ 800b1da:	b2db      	uxtb	r3, r3
+ 800b1dc:	f003 030f 	and.w	r3, r3, #15
+ 800b1e0:	2201      	movs	r2, #1
+ 800b1e2:	409a      	lsls	r2, r3
+ 800b1e4:	687b      	ldr	r3, [r7, #4]
+ 800b1e6:	64da      	str	r2, [r3, #76]	; 0x4c
+
+    hsd->SdCard.LogBlockNbr = (hsd->SdCard.BlockNbr) * ((hsd->SdCard.BlockSize) / 512U);
+ 800b1e8:	687b      	ldr	r3, [r7, #4]
+ 800b1ea:	6c9b      	ldr	r3, [r3, #72]	; 0x48
+ 800b1ec:	687a      	ldr	r2, [r7, #4]
+ 800b1ee:	6cd2      	ldr	r2, [r2, #76]	; 0x4c
+ 800b1f0:	0a52      	lsrs	r2, r2, #9
+ 800b1f2:	fb03 f202 	mul.w	r2, r3, r2
+ 800b1f6:	687b      	ldr	r3, [r7, #4]
+ 800b1f8:	651a      	str	r2, [r3, #80]	; 0x50
+    hsd->SdCard.LogBlockSize = 512U;
+ 800b1fa:	687b      	ldr	r3, [r7, #4]
+ 800b1fc:	f44f 7200 	mov.w	r2, #512	; 0x200
+ 800b200:	655a      	str	r2, [r3, #84]	; 0x54
+ 800b202:	e031      	b.n	800b268 <HAL_SD_GetCardCSD+0x1fc>
+  }
+  else if (hsd->SdCard.CardType == CARD_SDHC_SDXC)
+ 800b204:	687b      	ldr	r3, [r7, #4]
+ 800b206:	6b9b      	ldr	r3, [r3, #56]	; 0x38
+ 800b208:	2b01      	cmp	r3, #1
+ 800b20a:	d11d      	bne.n	800b248 <HAL_SD_GetCardCSD+0x1dc>
+  {
+    /* Byte 7 */
+    pCSD->DeviceSize = (((hsd->CSD[1] & 0x0000003FU) << 16U) | ((hsd->CSD[2] & 0xFFFF0000U) >> 16U));
+ 800b20c:	687b      	ldr	r3, [r7, #4]
+ 800b20e:	6e1b      	ldr	r3, [r3, #96]	; 0x60
+ 800b210:	041b      	lsls	r3, r3, #16
+ 800b212:	f403 127c 	and.w	r2, r3, #4128768	; 0x3f0000
+ 800b216:	687b      	ldr	r3, [r7, #4]
+ 800b218:	6e5b      	ldr	r3, [r3, #100]	; 0x64
+ 800b21a:	0c1b      	lsrs	r3, r3, #16
+ 800b21c:	431a      	orrs	r2, r3
+ 800b21e:	683b      	ldr	r3, [r7, #0]
+ 800b220:	611a      	str	r2, [r3, #16]
+
+    hsd->SdCard.BlockNbr = ((pCSD->DeviceSize + 1U) * 1024U);
+ 800b222:	683b      	ldr	r3, [r7, #0]
+ 800b224:	691b      	ldr	r3, [r3, #16]
+ 800b226:	3301      	adds	r3, #1
+ 800b228:	029a      	lsls	r2, r3, #10
+ 800b22a:	687b      	ldr	r3, [r7, #4]
+ 800b22c:	649a      	str	r2, [r3, #72]	; 0x48
+    hsd->SdCard.LogBlockNbr = hsd->SdCard.BlockNbr;
+ 800b22e:	687b      	ldr	r3, [r7, #4]
+ 800b230:	6c9a      	ldr	r2, [r3, #72]	; 0x48
+ 800b232:	687b      	ldr	r3, [r7, #4]
+ 800b234:	651a      	str	r2, [r3, #80]	; 0x50
+    hsd->SdCard.BlockSize = 512U;
+ 800b236:	687b      	ldr	r3, [r7, #4]
+ 800b238:	f44f 7200 	mov.w	r2, #512	; 0x200
+ 800b23c:	64da      	str	r2, [r3, #76]	; 0x4c
+    hsd->SdCard.LogBlockSize = hsd->SdCard.BlockSize;
+ 800b23e:	687b      	ldr	r3, [r7, #4]
+ 800b240:	6cda      	ldr	r2, [r3, #76]	; 0x4c
+ 800b242:	687b      	ldr	r3, [r7, #4]
+ 800b244:	655a      	str	r2, [r3, #84]	; 0x54
+ 800b246:	e00f      	b.n	800b268 <HAL_SD_GetCardCSD+0x1fc>
+  }
+  else
+  {
+    /* Clear all the static flags */
+    __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+ 800b248:	687b      	ldr	r3, [r7, #4]
+ 800b24a:	681b      	ldr	r3, [r3, #0]
+ 800b24c:	4a58      	ldr	r2, [pc, #352]	; (800b3b0 <HAL_SD_GetCardCSD+0x344>)
+ 800b24e:	639a      	str	r2, [r3, #56]	; 0x38
+    hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
+ 800b250:	687b      	ldr	r3, [r7, #4]
+ 800b252:	6b5b      	ldr	r3, [r3, #52]	; 0x34
+ 800b254:	f043 5280 	orr.w	r2, r3, #268435456	; 0x10000000
+ 800b258:	687b      	ldr	r3, [r7, #4]
+ 800b25a:	635a      	str	r2, [r3, #52]	; 0x34
+    hsd->State = HAL_SD_STATE_READY;
+ 800b25c:	687b      	ldr	r3, [r7, #4]
+ 800b25e:	2201      	movs	r2, #1
+ 800b260:	f883 2030 	strb.w	r2, [r3, #48]	; 0x30
+    return HAL_ERROR;
+ 800b264:	2301      	movs	r3, #1
+ 800b266:	e09d      	b.n	800b3a4 <HAL_SD_GetCardCSD+0x338>
+  }
+
+  pCSD->EraseGrSize = (uint8_t)((hsd->CSD[2] & 0x00004000U) >> 14U);
+ 800b268:	687b      	ldr	r3, [r7, #4]
+ 800b26a:	6e5b      	ldr	r3, [r3, #100]	; 0x64
+ 800b26c:	0b9b      	lsrs	r3, r3, #14
+ 800b26e:	b2db      	uxtb	r3, r3
+ 800b270:	f003 0301 	and.w	r3, r3, #1
+ 800b274:	b2da      	uxtb	r2, r3
+ 800b276:	683b      	ldr	r3, [r7, #0]
+ 800b278:	765a      	strb	r2, [r3, #25]
+
+  pCSD->EraseGrMul = (uint8_t)((hsd->CSD[2] & 0x00003F80U) >> 7U);
+ 800b27a:	687b      	ldr	r3, [r7, #4]
+ 800b27c:	6e5b      	ldr	r3, [r3, #100]	; 0x64
+ 800b27e:	09db      	lsrs	r3, r3, #7
+ 800b280:	b2db      	uxtb	r3, r3
+ 800b282:	f003 037f 	and.w	r3, r3, #127	; 0x7f
+ 800b286:	b2da      	uxtb	r2, r3
+ 800b288:	683b      	ldr	r3, [r7, #0]
+ 800b28a:	769a      	strb	r2, [r3, #26]
+
+  pCSD->WrProtectGrSize = (uint8_t)(hsd->CSD[2] & 0x0000007FU);
+ 800b28c:	687b      	ldr	r3, [r7, #4]
+ 800b28e:	6e5b      	ldr	r3, [r3, #100]	; 0x64
+ 800b290:	b2db      	uxtb	r3, r3
+ 800b292:	f003 037f 	and.w	r3, r3, #127	; 0x7f
+ 800b296:	b2da      	uxtb	r2, r3
+ 800b298:	683b      	ldr	r3, [r7, #0]
+ 800b29a:	76da      	strb	r2, [r3, #27]
+
+  pCSD->WrProtectGrEnable = (uint8_t)((hsd->CSD[3] & 0x80000000U) >> 31U);
+ 800b29c:	687b      	ldr	r3, [r7, #4]
+ 800b29e:	6e9b      	ldr	r3, [r3, #104]	; 0x68
+ 800b2a0:	0fdb      	lsrs	r3, r3, #31
+ 800b2a2:	b2da      	uxtb	r2, r3
+ 800b2a4:	683b      	ldr	r3, [r7, #0]
+ 800b2a6:	771a      	strb	r2, [r3, #28]
+
+  pCSD->ManDeflECC = (uint8_t)((hsd->CSD[3] & 0x60000000U) >> 29U);
+ 800b2a8:	687b      	ldr	r3, [r7, #4]
+ 800b2aa:	6e9b      	ldr	r3, [r3, #104]	; 0x68
+ 800b2ac:	0f5b      	lsrs	r3, r3, #29
+ 800b2ae:	b2db      	uxtb	r3, r3
+ 800b2b0:	f003 0303 	and.w	r3, r3, #3
+ 800b2b4:	b2da      	uxtb	r2, r3
+ 800b2b6:	683b      	ldr	r3, [r7, #0]
+ 800b2b8:	775a      	strb	r2, [r3, #29]
+
+  pCSD->WrSpeedFact = (uint8_t)((hsd->CSD[3] & 0x1C000000U) >> 26U);
+ 800b2ba:	687b      	ldr	r3, [r7, #4]
+ 800b2bc:	6e9b      	ldr	r3, [r3, #104]	; 0x68
+ 800b2be:	0e9b      	lsrs	r3, r3, #26
+ 800b2c0:	b2db      	uxtb	r3, r3
+ 800b2c2:	f003 0307 	and.w	r3, r3, #7
+ 800b2c6:	b2da      	uxtb	r2, r3
+ 800b2c8:	683b      	ldr	r3, [r7, #0]
+ 800b2ca:	779a      	strb	r2, [r3, #30]
+
+  pCSD->MaxWrBlockLen = (uint8_t)((hsd->CSD[3] & 0x03C00000U) >> 22U);
+ 800b2cc:	687b      	ldr	r3, [r7, #4]
+ 800b2ce:	6e9b      	ldr	r3, [r3, #104]	; 0x68
+ 800b2d0:	0d9b      	lsrs	r3, r3, #22
+ 800b2d2:	b2db      	uxtb	r3, r3
+ 800b2d4:	f003 030f 	and.w	r3, r3, #15
+ 800b2d8:	b2da      	uxtb	r2, r3
+ 800b2da:	683b      	ldr	r3, [r7, #0]
+ 800b2dc:	77da      	strb	r2, [r3, #31]
+
+  pCSD->WriteBlockPaPartial = (uint8_t)((hsd->CSD[3] & 0x00200000U) >> 21U);
+ 800b2de:	687b      	ldr	r3, [r7, #4]
+ 800b2e0:	6e9b      	ldr	r3, [r3, #104]	; 0x68
+ 800b2e2:	0d5b      	lsrs	r3, r3, #21
+ 800b2e4:	b2db      	uxtb	r3, r3
+ 800b2e6:	f003 0301 	and.w	r3, r3, #1
+ 800b2ea:	b2da      	uxtb	r2, r3
+ 800b2ec:	683b      	ldr	r3, [r7, #0]
+ 800b2ee:	f883 2020 	strb.w	r2, [r3, #32]
+
+  pCSD->Reserved3 = 0;
+ 800b2f2:	683b      	ldr	r3, [r7, #0]
+ 800b2f4:	2200      	movs	r2, #0
+ 800b2f6:	f883 2021 	strb.w	r2, [r3, #33]	; 0x21
+
+  pCSD->ContentProtectAppli = (uint8_t)((hsd->CSD[3] & 0x00010000U) >> 16U);
+ 800b2fa:	687b      	ldr	r3, [r7, #4]
+ 800b2fc:	6e9b      	ldr	r3, [r3, #104]	; 0x68
+ 800b2fe:	0c1b      	lsrs	r3, r3, #16
+ 800b300:	b2db      	uxtb	r3, r3
+ 800b302:	f003 0301 	and.w	r3, r3, #1
+ 800b306:	b2da      	uxtb	r2, r3
+ 800b308:	683b      	ldr	r3, [r7, #0]
+ 800b30a:	f883 2022 	strb.w	r2, [r3, #34]	; 0x22
+
+  pCSD->FileFormatGroup = (uint8_t)((hsd->CSD[3] & 0x00008000U) >> 15U);
+ 800b30e:	687b      	ldr	r3, [r7, #4]
+ 800b310:	6e9b      	ldr	r3, [r3, #104]	; 0x68
+ 800b312:	0bdb      	lsrs	r3, r3, #15
+ 800b314:	b2db      	uxtb	r3, r3
+ 800b316:	f003 0301 	and.w	r3, r3, #1
+ 800b31a:	b2da      	uxtb	r2, r3
+ 800b31c:	683b      	ldr	r3, [r7, #0]
+ 800b31e:	f883 2023 	strb.w	r2, [r3, #35]	; 0x23
+
+  pCSD->CopyFlag = (uint8_t)((hsd->CSD[3] & 0x00004000U) >> 14U);
+ 800b322:	687b      	ldr	r3, [r7, #4]
+ 800b324:	6e9b      	ldr	r3, [r3, #104]	; 0x68
+ 800b326:	0b9b      	lsrs	r3, r3, #14
+ 800b328:	b2db      	uxtb	r3, r3
+ 800b32a:	f003 0301 	and.w	r3, r3, #1
+ 800b32e:	b2da      	uxtb	r2, r3
+ 800b330:	683b      	ldr	r3, [r7, #0]
+ 800b332:	f883 2024 	strb.w	r2, [r3, #36]	; 0x24
+
+  pCSD->PermWrProtect = (uint8_t)((hsd->CSD[3] & 0x00002000U) >> 13U);
+ 800b336:	687b      	ldr	r3, [r7, #4]
+ 800b338:	6e9b      	ldr	r3, [r3, #104]	; 0x68
+ 800b33a:	0b5b      	lsrs	r3, r3, #13
+ 800b33c:	b2db      	uxtb	r3, r3
+ 800b33e:	f003 0301 	and.w	r3, r3, #1
+ 800b342:	b2da      	uxtb	r2, r3
+ 800b344:	683b      	ldr	r3, [r7, #0]
+ 800b346:	f883 2025 	strb.w	r2, [r3, #37]	; 0x25
+
+  pCSD->TempWrProtect = (uint8_t)((hsd->CSD[3] & 0x00001000U) >> 12U);
+ 800b34a:	687b      	ldr	r3, [r7, #4]
+ 800b34c:	6e9b      	ldr	r3, [r3, #104]	; 0x68
+ 800b34e:	0b1b      	lsrs	r3, r3, #12
+ 800b350:	b2db      	uxtb	r3, r3
+ 800b352:	f003 0301 	and.w	r3, r3, #1
+ 800b356:	b2da      	uxtb	r2, r3
+ 800b358:	683b      	ldr	r3, [r7, #0]
+ 800b35a:	f883 2026 	strb.w	r2, [r3, #38]	; 0x26
+
+  pCSD->FileFormat = (uint8_t)((hsd->CSD[3] & 0x00000C00U) >> 10U);
+ 800b35e:	687b      	ldr	r3, [r7, #4]
+ 800b360:	6e9b      	ldr	r3, [r3, #104]	; 0x68
+ 800b362:	0a9b      	lsrs	r3, r3, #10
+ 800b364:	b2db      	uxtb	r3, r3
+ 800b366:	f003 0303 	and.w	r3, r3, #3
+ 800b36a:	b2da      	uxtb	r2, r3
+ 800b36c:	683b      	ldr	r3, [r7, #0]
+ 800b36e:	f883 2027 	strb.w	r2, [r3, #39]	; 0x27
+
+  pCSD->ECC = (uint8_t)((hsd->CSD[3] & 0x00000300U) >> 8U);
+ 800b372:	687b      	ldr	r3, [r7, #4]
+ 800b374:	6e9b      	ldr	r3, [r3, #104]	; 0x68
+ 800b376:	0a1b      	lsrs	r3, r3, #8
+ 800b378:	b2db      	uxtb	r3, r3
+ 800b37a:	f003 0303 	and.w	r3, r3, #3
+ 800b37e:	b2da      	uxtb	r2, r3
+ 800b380:	683b      	ldr	r3, [r7, #0]
+ 800b382:	f883 2028 	strb.w	r2, [r3, #40]	; 0x28
+
+  pCSD->CSD_CRC = (uint8_t)((hsd->CSD[3] & 0x000000FEU) >> 1U);
+ 800b386:	687b      	ldr	r3, [r7, #4]
+ 800b388:	6e9b      	ldr	r3, [r3, #104]	; 0x68
+ 800b38a:	085b      	lsrs	r3, r3, #1
+ 800b38c:	b2db      	uxtb	r3, r3
+ 800b38e:	f003 037f 	and.w	r3, r3, #127	; 0x7f
+ 800b392:	b2da      	uxtb	r2, r3
+ 800b394:	683b      	ldr	r3, [r7, #0]
+ 800b396:	f883 2029 	strb.w	r2, [r3, #41]	; 0x29
+
+  pCSD->Reserved4 = 1;
+ 800b39a:	683b      	ldr	r3, [r7, #0]
+ 800b39c:	2201      	movs	r2, #1
+ 800b39e:	f883 202a 	strb.w	r2, [r3, #42]	; 0x2a
+
+  return HAL_OK;
+ 800b3a2:	2300      	movs	r3, #0
+}
+ 800b3a4:	4618      	mov	r0, r3
+ 800b3a6:	370c      	adds	r7, #12
+ 800b3a8:	46bd      	mov	sp, r7
+ 800b3aa:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 800b3ae:	4770      	bx	lr
+ 800b3b0:	1fe00fff 	.word	0x1fe00fff
+
+0800b3b4 <HAL_SD_GetCardStatus>:
+  * @param  pStatus: Pointer to the HAL_SD_CardStatusTypeDef structure that
+  *         will contain the SD card status information
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypeDef *pStatus)
+{
+ 800b3b4:	b580      	push	{r7, lr}
+ 800b3b6:	b094      	sub	sp, #80	; 0x50
+ 800b3b8:	af00      	add	r7, sp, #0
+ 800b3ba:	6078      	str	r0, [r7, #4]
+ 800b3bc:	6039      	str	r1, [r7, #0]
+  uint32_t sd_status[16];
+  uint32_t errorstate;
+  HAL_StatusTypeDef status = HAL_OK;
+ 800b3be:	2300      	movs	r3, #0
+ 800b3c0:	f887 304f 	strb.w	r3, [r7, #79]	; 0x4f
+
+  if (hsd->State == HAL_SD_STATE_BUSY)
+ 800b3c4:	687b      	ldr	r3, [r7, #4]
+ 800b3c6:	f893 3030 	ldrb.w	r3, [r3, #48]	; 0x30
+ 800b3ca:	b2db      	uxtb	r3, r3
+ 800b3cc:	2b03      	cmp	r3, #3
+ 800b3ce:	d101      	bne.n	800b3d4 <HAL_SD_GetCardStatus+0x20>
+  {
+    return HAL_ERROR;
+ 800b3d0:	2301      	movs	r3, #1
+ 800b3d2:	e0a7      	b.n	800b524 <HAL_SD_GetCardStatus+0x170>
+  }
+
+  errorstate = SD_SendSDStatus(hsd, sd_status);
+ 800b3d4:	f107 0308 	add.w	r3, r7, #8
+ 800b3d8:	4619      	mov	r1, r3
+ 800b3da:	6878      	ldr	r0, [r7, #4]
+ 800b3dc:	f000 fb62 	bl	800baa4 <SD_SendSDStatus>
+ 800b3e0:	64b8      	str	r0, [r7, #72]	; 0x48
+  if (errorstate != HAL_SD_ERROR_NONE)
+ 800b3e2:	6cbb      	ldr	r3, [r7, #72]	; 0x48
+ 800b3e4:	2b00      	cmp	r3, #0
+ 800b3e6:	d011      	beq.n	800b40c <HAL_SD_GetCardStatus+0x58>
+  {
+    /* Clear all the static flags */
+    __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+ 800b3e8:	687b      	ldr	r3, [r7, #4]
+ 800b3ea:	681b      	ldr	r3, [r3, #0]
+ 800b3ec:	4a4f      	ldr	r2, [pc, #316]	; (800b52c <HAL_SD_GetCardStatus+0x178>)
+ 800b3ee:	639a      	str	r2, [r3, #56]	; 0x38
+    hsd->ErrorCode |= errorstate;
+ 800b3f0:	687b      	ldr	r3, [r7, #4]
+ 800b3f2:	6b5a      	ldr	r2, [r3, #52]	; 0x34
+ 800b3f4:	6cbb      	ldr	r3, [r7, #72]	; 0x48
+ 800b3f6:	431a      	orrs	r2, r3
+ 800b3f8:	687b      	ldr	r3, [r7, #4]
+ 800b3fa:	635a      	str	r2, [r3, #52]	; 0x34
+    hsd->State = HAL_SD_STATE_READY;
+ 800b3fc:	687b      	ldr	r3, [r7, #4]
+ 800b3fe:	2201      	movs	r2, #1
+ 800b400:	f883 2030 	strb.w	r2, [r3, #48]	; 0x30
+    status = HAL_ERROR;
+ 800b404:	2301      	movs	r3, #1
+ 800b406:	f887 304f 	strb.w	r3, [r7, #79]	; 0x4f
+ 800b40a:	e070      	b.n	800b4ee <HAL_SD_GetCardStatus+0x13a>
+  }
+  else
+  {
+    pStatus->DataBusWidth = (uint8_t)((sd_status[0] & 0xC0U) >> 6U);
+ 800b40c:	68bb      	ldr	r3, [r7, #8]
+ 800b40e:	099b      	lsrs	r3, r3, #6
+ 800b410:	b2db      	uxtb	r3, r3
+ 800b412:	f003 0303 	and.w	r3, r3, #3
+ 800b416:	b2da      	uxtb	r2, r3
+ 800b418:	683b      	ldr	r3, [r7, #0]
+ 800b41a:	701a      	strb	r2, [r3, #0]
+
+    pStatus->SecuredMode = (uint8_t)((sd_status[0] & 0x20U) >> 5U);
+ 800b41c:	68bb      	ldr	r3, [r7, #8]
+ 800b41e:	095b      	lsrs	r3, r3, #5
+ 800b420:	b2db      	uxtb	r3, r3
+ 800b422:	f003 0301 	and.w	r3, r3, #1
+ 800b426:	b2da      	uxtb	r2, r3
+ 800b428:	683b      	ldr	r3, [r7, #0]
+ 800b42a:	705a      	strb	r2, [r3, #1]
+
+    pStatus->CardType = (uint16_t)(((sd_status[0] & 0x00FF0000U) >> 8U) | ((sd_status[0] & 0xFF000000U) >> 24U));
+ 800b42c:	68bb      	ldr	r3, [r7, #8]
+ 800b42e:	0a1b      	lsrs	r3, r3, #8
+ 800b430:	b29b      	uxth	r3, r3
+ 800b432:	f023 03ff 	bic.w	r3, r3, #255	; 0xff
+ 800b436:	b29a      	uxth	r2, r3
+ 800b438:	68bb      	ldr	r3, [r7, #8]
+ 800b43a:	0e1b      	lsrs	r3, r3, #24
+ 800b43c:	b29b      	uxth	r3, r3
+ 800b43e:	4313      	orrs	r3, r2
+ 800b440:	b29a      	uxth	r2, r3
+ 800b442:	683b      	ldr	r3, [r7, #0]
+ 800b444:	805a      	strh	r2, [r3, #2]
+
+    pStatus->ProtectedAreaSize = (((sd_status[1] & 0xFFU) << 24U)    | ((sd_status[1] & 0xFF00U) << 8U) |
+ 800b446:	68fb      	ldr	r3, [r7, #12]
+ 800b448:	061a      	lsls	r2, r3, #24
+ 800b44a:	68fb      	ldr	r3, [r7, #12]
+ 800b44c:	021b      	lsls	r3, r3, #8
+ 800b44e:	f403 037f 	and.w	r3, r3, #16711680	; 0xff0000
+ 800b452:	431a      	orrs	r2, r3
+                                  ((sd_status[1] & 0xFF0000U) >> 8U) | ((sd_status[1] & 0xFF000000U) >> 24U));
+ 800b454:	68fb      	ldr	r3, [r7, #12]
+ 800b456:	0a1b      	lsrs	r3, r3, #8
+ 800b458:	f403 437f 	and.w	r3, r3, #65280	; 0xff00
+    pStatus->ProtectedAreaSize = (((sd_status[1] & 0xFFU) << 24U)    | ((sd_status[1] & 0xFF00U) << 8U) |
+ 800b45c:	431a      	orrs	r2, r3
+                                  ((sd_status[1] & 0xFF0000U) >> 8U) | ((sd_status[1] & 0xFF000000U) >> 24U));
+ 800b45e:	68fb      	ldr	r3, [r7, #12]
+ 800b460:	0e1b      	lsrs	r3, r3, #24
+ 800b462:	431a      	orrs	r2, r3
+    pStatus->ProtectedAreaSize = (((sd_status[1] & 0xFFU) << 24U)    | ((sd_status[1] & 0xFF00U) << 8U) |
+ 800b464:	683b      	ldr	r3, [r7, #0]
+ 800b466:	605a      	str	r2, [r3, #4]
+
+    pStatus->SpeedClass = (uint8_t)(sd_status[2] & 0xFFU);
+ 800b468:	693b      	ldr	r3, [r7, #16]
+ 800b46a:	b2da      	uxtb	r2, r3
+ 800b46c:	683b      	ldr	r3, [r7, #0]
+ 800b46e:	721a      	strb	r2, [r3, #8]
+
+    pStatus->PerformanceMove = (uint8_t)((sd_status[2] & 0xFF00U) >> 8U);
+ 800b470:	693b      	ldr	r3, [r7, #16]
+ 800b472:	0a1b      	lsrs	r3, r3, #8
+ 800b474:	b2da      	uxtb	r2, r3
+ 800b476:	683b      	ldr	r3, [r7, #0]
+ 800b478:	725a      	strb	r2, [r3, #9]
+
+    pStatus->AllocationUnitSize = (uint8_t)((sd_status[2] & 0xF00000U) >> 20U);
+ 800b47a:	693b      	ldr	r3, [r7, #16]
+ 800b47c:	0d1b      	lsrs	r3, r3, #20
+ 800b47e:	b2db      	uxtb	r3, r3
+ 800b480:	f003 030f 	and.w	r3, r3, #15
+ 800b484:	b2da      	uxtb	r2, r3
+ 800b486:	683b      	ldr	r3, [r7, #0]
+ 800b488:	729a      	strb	r2, [r3, #10]
+
+    pStatus->EraseSize = (uint16_t)(((sd_status[2] & 0xFF000000U) >> 16U) | (sd_status[3] & 0xFFU));
+ 800b48a:	693b      	ldr	r3, [r7, #16]
+ 800b48c:	0c1b      	lsrs	r3, r3, #16
+ 800b48e:	b29b      	uxth	r3, r3
+ 800b490:	f023 03ff 	bic.w	r3, r3, #255	; 0xff
+ 800b494:	b29a      	uxth	r2, r3
+ 800b496:	697b      	ldr	r3, [r7, #20]
+ 800b498:	b29b      	uxth	r3, r3
+ 800b49a:	b2db      	uxtb	r3, r3
+ 800b49c:	b29b      	uxth	r3, r3
+ 800b49e:	4313      	orrs	r3, r2
+ 800b4a0:	b29a      	uxth	r2, r3
+ 800b4a2:	683b      	ldr	r3, [r7, #0]
+ 800b4a4:	819a      	strh	r2, [r3, #12]
+
+    pStatus->EraseTimeout = (uint8_t)((sd_status[3] & 0xFC00U) >> 10U);
+ 800b4a6:	697b      	ldr	r3, [r7, #20]
+ 800b4a8:	0a9b      	lsrs	r3, r3, #10
+ 800b4aa:	b2db      	uxtb	r3, r3
+ 800b4ac:	f003 033f 	and.w	r3, r3, #63	; 0x3f
+ 800b4b0:	b2da      	uxtb	r2, r3
+ 800b4b2:	683b      	ldr	r3, [r7, #0]
+ 800b4b4:	739a      	strb	r2, [r3, #14]
+
+    pStatus->EraseOffset = (uint8_t)((sd_status[3] & 0x0300U) >> 8U);
+ 800b4b6:	697b      	ldr	r3, [r7, #20]
+ 800b4b8:	0a1b      	lsrs	r3, r3, #8
+ 800b4ba:	b2db      	uxtb	r3, r3
+ 800b4bc:	f003 0303 	and.w	r3, r3, #3
+ 800b4c0:	b2da      	uxtb	r2, r3
+ 800b4c2:	683b      	ldr	r3, [r7, #0]
+ 800b4c4:	73da      	strb	r2, [r3, #15]
+
+    pStatus->UhsSpeedGrade = (uint8_t)((sd_status[3] & 0x00F0U) >> 4U);
+ 800b4c6:	697b      	ldr	r3, [r7, #20]
+ 800b4c8:	091b      	lsrs	r3, r3, #4
+ 800b4ca:	b2db      	uxtb	r3, r3
+ 800b4cc:	f003 030f 	and.w	r3, r3, #15
+ 800b4d0:	b2da      	uxtb	r2, r3
+ 800b4d2:	683b      	ldr	r3, [r7, #0]
+ 800b4d4:	741a      	strb	r2, [r3, #16]
+    pStatus->UhsAllocationUnitSize = (uint8_t)(sd_status[3] & 0x000FU) ;
+ 800b4d6:	697b      	ldr	r3, [r7, #20]
+ 800b4d8:	b2db      	uxtb	r3, r3
+ 800b4da:	f003 030f 	and.w	r3, r3, #15
+ 800b4de:	b2da      	uxtb	r2, r3
+ 800b4e0:	683b      	ldr	r3, [r7, #0]
+ 800b4e2:	745a      	strb	r2, [r3, #17]
+    pStatus->VideoSpeedClass = (uint8_t)((sd_status[4] & 0xFF000000U) >> 24U);
+ 800b4e4:	69bb      	ldr	r3, [r7, #24]
+ 800b4e6:	0e1b      	lsrs	r3, r3, #24
+ 800b4e8:	b2da      	uxtb	r2, r3
+ 800b4ea:	683b      	ldr	r3, [r7, #0]
+ 800b4ec:	749a      	strb	r2, [r3, #18]
+  }
+
+  /* Set Block Size for Card */
+  errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
+ 800b4ee:	687b      	ldr	r3, [r7, #4]
+ 800b4f0:	681b      	ldr	r3, [r3, #0]
+ 800b4f2:	f44f 7100 	mov.w	r1, #512	; 0x200
+ 800b4f6:	4618      	mov	r0, r3
+ 800b4f8:	f002 fdbe 	bl	800e078 <SDMMC_CmdBlockLength>
+ 800b4fc:	64b8      	str	r0, [r7, #72]	; 0x48
+  if (errorstate != HAL_SD_ERROR_NONE)
+ 800b4fe:	6cbb      	ldr	r3, [r7, #72]	; 0x48
+ 800b500:	2b00      	cmp	r3, #0
+ 800b502:	d00d      	beq.n	800b520 <HAL_SD_GetCardStatus+0x16c>
+  {
+    /* Clear all the static flags */
+    __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+ 800b504:	687b      	ldr	r3, [r7, #4]
+ 800b506:	681b      	ldr	r3, [r3, #0]
+ 800b508:	4a08      	ldr	r2, [pc, #32]	; (800b52c <HAL_SD_GetCardStatus+0x178>)
+ 800b50a:	639a      	str	r2, [r3, #56]	; 0x38
+    hsd->ErrorCode = errorstate;
+ 800b50c:	687b      	ldr	r3, [r7, #4]
+ 800b50e:	6cba      	ldr	r2, [r7, #72]	; 0x48
+ 800b510:	635a      	str	r2, [r3, #52]	; 0x34
+    hsd->State = HAL_SD_STATE_READY;
+ 800b512:	687b      	ldr	r3, [r7, #4]
+ 800b514:	2201      	movs	r2, #1
+ 800b516:	f883 2030 	strb.w	r2, [r3, #48]	; 0x30
+    status = HAL_ERROR;
+ 800b51a:	2301      	movs	r3, #1
+ 800b51c:	f887 304f 	strb.w	r3, [r7, #79]	; 0x4f
+  }
+
+
+  return status;
+ 800b520:	f897 304f 	ldrb.w	r3, [r7, #79]	; 0x4f
+}
+ 800b524:	4618      	mov	r0, r3
+ 800b526:	3750      	adds	r7, #80	; 0x50
+ 800b528:	46bd      	mov	sp, r7
+ 800b52a:	bd80      	pop	{r7, pc}
+ 800b52c:	1fe00fff 	.word	0x1fe00fff
+
+0800b530 <HAL_SD_GetCardInfo>:
+  * @param  pCardInfo: Pointer to the HAL_SD_CardInfoTypeDef structure that
+  *         will contain the SD card status information
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SD_GetCardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypeDef *pCardInfo)
+{
+ 800b530:	b480      	push	{r7}
+ 800b532:	b083      	sub	sp, #12
+ 800b534:	af00      	add	r7, sp, #0
+ 800b536:	6078      	str	r0, [r7, #4]
+ 800b538:	6039      	str	r1, [r7, #0]
+  pCardInfo->CardType     = (uint32_t)(hsd->SdCard.CardType);
+ 800b53a:	687b      	ldr	r3, [r7, #4]
+ 800b53c:	6b9a      	ldr	r2, [r3, #56]	; 0x38
+ 800b53e:	683b      	ldr	r3, [r7, #0]
+ 800b540:	601a      	str	r2, [r3, #0]
+  pCardInfo->CardVersion  = (uint32_t)(hsd->SdCard.CardVersion);
+ 800b542:	687b      	ldr	r3, [r7, #4]
+ 800b544:	6bda      	ldr	r2, [r3, #60]	; 0x3c
+ 800b546:	683b      	ldr	r3, [r7, #0]
+ 800b548:	605a      	str	r2, [r3, #4]
+  pCardInfo->Class        = (uint32_t)(hsd->SdCard.Class);
+ 800b54a:	687b      	ldr	r3, [r7, #4]
+ 800b54c:	6c1a      	ldr	r2, [r3, #64]	; 0x40
+ 800b54e:	683b      	ldr	r3, [r7, #0]
+ 800b550:	609a      	str	r2, [r3, #8]
+  pCardInfo->RelCardAdd   = (uint32_t)(hsd->SdCard.RelCardAdd);
+ 800b552:	687b      	ldr	r3, [r7, #4]
+ 800b554:	6c5a      	ldr	r2, [r3, #68]	; 0x44
+ 800b556:	683b      	ldr	r3, [r7, #0]
+ 800b558:	60da      	str	r2, [r3, #12]
+  pCardInfo->BlockNbr     = (uint32_t)(hsd->SdCard.BlockNbr);
+ 800b55a:	687b      	ldr	r3, [r7, #4]
+ 800b55c:	6c9a      	ldr	r2, [r3, #72]	; 0x48
+ 800b55e:	683b      	ldr	r3, [r7, #0]
+ 800b560:	611a      	str	r2, [r3, #16]
+  pCardInfo->BlockSize    = (uint32_t)(hsd->SdCard.BlockSize);
+ 800b562:	687b      	ldr	r3, [r7, #4]
+ 800b564:	6cda      	ldr	r2, [r3, #76]	; 0x4c
+ 800b566:	683b      	ldr	r3, [r7, #0]
+ 800b568:	615a      	str	r2, [r3, #20]
+  pCardInfo->LogBlockNbr  = (uint32_t)(hsd->SdCard.LogBlockNbr);
+ 800b56a:	687b      	ldr	r3, [r7, #4]
+ 800b56c:	6d1a      	ldr	r2, [r3, #80]	; 0x50
+ 800b56e:	683b      	ldr	r3, [r7, #0]
+ 800b570:	619a      	str	r2, [r3, #24]
+  pCardInfo->LogBlockSize = (uint32_t)(hsd->SdCard.LogBlockSize);
+ 800b572:	687b      	ldr	r3, [r7, #4]
+ 800b574:	6d5a      	ldr	r2, [r3, #84]	; 0x54
+ 800b576:	683b      	ldr	r3, [r7, #0]
+ 800b578:	61da      	str	r2, [r3, #28]
+
+  return HAL_OK;
+ 800b57a:	2300      	movs	r3, #0
+}
+ 800b57c:	4618      	mov	r0, r3
+ 800b57e:	370c      	adds	r7, #12
+ 800b580:	46bd      	mov	sp, r7
+ 800b582:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 800b586:	4770      	bx	lr
+
+0800b588 <HAL_SD_ConfigWideBusOperation>:
+  *            @arg SDMMC_BUS_WIDE_4B: 4-bit data transfer
+  *            @arg SDMMC_BUS_WIDE_1B: 1-bit data transfer
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SD_ConfigWideBusOperation(SD_HandleTypeDef *hsd, uint32_t WideMode)
+{
+ 800b588:	b590      	push	{r4, r7, lr}
+ 800b58a:	b08d      	sub	sp, #52	; 0x34
+ 800b58c:	af02      	add	r7, sp, #8
+ 800b58e:	6078      	str	r0, [r7, #4]
+ 800b590:	6039      	str	r1, [r7, #0]
+  SDMMC_InitTypeDef Init;
+  uint32_t errorstate;
+  uint32_t sdmmc_clk;
+  HAL_StatusTypeDef status = HAL_OK;
+ 800b592:	2300      	movs	r3, #0
+ 800b594:	f887 3027 	strb.w	r3, [r7, #39]	; 0x27
+
+  /* Check the parameters */
+  assert_param(IS_SDMMC_BUS_WIDE(WideMode));
+
+  /* Change State */
+  hsd->State = HAL_SD_STATE_BUSY;
+ 800b598:	687b      	ldr	r3, [r7, #4]
+ 800b59a:	2203      	movs	r2, #3
+ 800b59c:	f883 2030 	strb.w	r2, [r3, #48]	; 0x30
+
+  if (hsd->SdCard.CardType != CARD_SECURED)
+ 800b5a0:	687b      	ldr	r3, [r7, #4]
+ 800b5a2:	6b9b      	ldr	r3, [r3, #56]	; 0x38
+ 800b5a4:	2b03      	cmp	r3, #3
+ 800b5a6:	d02e      	beq.n	800b606 <HAL_SD_ConfigWideBusOperation+0x7e>
+  {
+    if (WideMode == SDMMC_BUS_WIDE_8B)
+ 800b5a8:	683b      	ldr	r3, [r7, #0]
+ 800b5aa:	f5b3 4f00 	cmp.w	r3, #32768	; 0x8000
+ 800b5ae:	d106      	bne.n	800b5be <HAL_SD_ConfigWideBusOperation+0x36>
+    {
+      hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
+ 800b5b0:	687b      	ldr	r3, [r7, #4]
+ 800b5b2:	6b5b      	ldr	r3, [r3, #52]	; 0x34
+ 800b5b4:	f043 5280 	orr.w	r2, r3, #268435456	; 0x10000000
+ 800b5b8:	687b      	ldr	r3, [r7, #4]
+ 800b5ba:	635a      	str	r2, [r3, #52]	; 0x34
+ 800b5bc:	e029      	b.n	800b612 <HAL_SD_ConfigWideBusOperation+0x8a>
+    }
+    else if (WideMode == SDMMC_BUS_WIDE_4B)
+ 800b5be:	683b      	ldr	r3, [r7, #0]
+ 800b5c0:	f5b3 4f80 	cmp.w	r3, #16384	; 0x4000
+ 800b5c4:	d10a      	bne.n	800b5dc <HAL_SD_ConfigWideBusOperation+0x54>
+    {
+      errorstate = SD_WideBus_Enable(hsd);
+ 800b5c6:	6878      	ldr	r0, [r7, #4]
+ 800b5c8:	f000 fb64 	bl	800bc94 <SD_WideBus_Enable>
+ 800b5cc:	6238      	str	r0, [r7, #32]
+
+      hsd->ErrorCode |= errorstate;
+ 800b5ce:	687b      	ldr	r3, [r7, #4]
+ 800b5d0:	6b5a      	ldr	r2, [r3, #52]	; 0x34
+ 800b5d2:	6a3b      	ldr	r3, [r7, #32]
+ 800b5d4:	431a      	orrs	r2, r3
+ 800b5d6:	687b      	ldr	r3, [r7, #4]
+ 800b5d8:	635a      	str	r2, [r3, #52]	; 0x34
+ 800b5da:	e01a      	b.n	800b612 <HAL_SD_ConfigWideBusOperation+0x8a>
+    }
+    else if (WideMode == SDMMC_BUS_WIDE_1B)
+ 800b5dc:	683b      	ldr	r3, [r7, #0]
+ 800b5de:	2b00      	cmp	r3, #0
+ 800b5e0:	d10a      	bne.n	800b5f8 <HAL_SD_ConfigWideBusOperation+0x70>
+    {
+      errorstate = SD_WideBus_Disable(hsd);
+ 800b5e2:	6878      	ldr	r0, [r7, #4]
+ 800b5e4:	f000 fba1 	bl	800bd2a <SD_WideBus_Disable>
+ 800b5e8:	6238      	str	r0, [r7, #32]
+
+      hsd->ErrorCode |= errorstate;
+ 800b5ea:	687b      	ldr	r3, [r7, #4]
+ 800b5ec:	6b5a      	ldr	r2, [r3, #52]	; 0x34
+ 800b5ee:	6a3b      	ldr	r3, [r7, #32]
+ 800b5f0:	431a      	orrs	r2, r3
+ 800b5f2:	687b      	ldr	r3, [r7, #4]
+ 800b5f4:	635a      	str	r2, [r3, #52]	; 0x34
+ 800b5f6:	e00c      	b.n	800b612 <HAL_SD_ConfigWideBusOperation+0x8a>
+    }
+    else
+    {
+      /* WideMode is not a valid argument*/
+      hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
+ 800b5f8:	687b      	ldr	r3, [r7, #4]
+ 800b5fa:	6b5b      	ldr	r3, [r3, #52]	; 0x34
+ 800b5fc:	f043 6200 	orr.w	r2, r3, #134217728	; 0x8000000
+ 800b600:	687b      	ldr	r3, [r7, #4]
+ 800b602:	635a      	str	r2, [r3, #52]	; 0x34
+ 800b604:	e005      	b.n	800b612 <HAL_SD_ConfigWideBusOperation+0x8a>
+    }
+  }
+  else
+  {
+    /* SD Card does not support this feature */
+    hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
+ 800b606:	687b      	ldr	r3, [r7, #4]
+ 800b608:	6b5b      	ldr	r3, [r3, #52]	; 0x34
+ 800b60a:	f043 5280 	orr.w	r2, r3, #268435456	; 0x10000000
+ 800b60e:	687b      	ldr	r3, [r7, #4]
+ 800b610:	635a      	str	r2, [r3, #52]	; 0x34
+  }
+
+  if (hsd->ErrorCode != HAL_SD_ERROR_NONE)
+ 800b612:	687b      	ldr	r3, [r7, #4]
+ 800b614:	6b5b      	ldr	r3, [r3, #52]	; 0x34
+ 800b616:	2b00      	cmp	r3, #0
+ 800b618:	d007      	beq.n	800b62a <HAL_SD_ConfigWideBusOperation+0xa2>
+  {
+    /* Clear all the static flags */
+    __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+ 800b61a:	687b      	ldr	r3, [r7, #4]
+ 800b61c:	681b      	ldr	r3, [r3, #0]
+ 800b61e:	4a5f      	ldr	r2, [pc, #380]	; (800b79c <HAL_SD_ConfigWideBusOperation+0x214>)
+ 800b620:	639a      	str	r2, [r3, #56]	; 0x38
+    status = HAL_ERROR;
+ 800b622:	2301      	movs	r3, #1
+ 800b624:	f887 3027 	strb.w	r3, [r7, #39]	; 0x27
+ 800b628:	e096      	b.n	800b758 <HAL_SD_ConfigWideBusOperation+0x1d0>
+  }
+  else
+  {
+    sdmmc_clk     = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SDMMC);
+ 800b62a:	f44f 3080 	mov.w	r0, #65536	; 0x10000
+ 800b62e:	f04f 0100 	mov.w	r1, #0
+ 800b632:	f7fd fea3 	bl	800937c <HAL_RCCEx_GetPeriphCLKFreq>
+ 800b636:	61f8      	str	r0, [r7, #28]
+    if (sdmmc_clk != 0U)
+ 800b638:	69fb      	ldr	r3, [r7, #28]
+ 800b63a:	2b00      	cmp	r3, #0
+ 800b63c:	f000 8083 	beq.w	800b746 <HAL_SD_ConfigWideBusOperation+0x1be>
+    {
+      /* Configure the SDMMC peripheral */
+      Init.ClockEdge           = hsd->Init.ClockEdge;
+ 800b640:	687b      	ldr	r3, [r7, #4]
+ 800b642:	685b      	ldr	r3, [r3, #4]
+ 800b644:	60bb      	str	r3, [r7, #8]
+      Init.ClockPowerSave      = hsd->Init.ClockPowerSave;
+ 800b646:	687b      	ldr	r3, [r7, #4]
+ 800b648:	689b      	ldr	r3, [r3, #8]
+ 800b64a:	60fb      	str	r3, [r7, #12]
+      Init.BusWide             = WideMode;
+ 800b64c:	683b      	ldr	r3, [r7, #0]
+ 800b64e:	613b      	str	r3, [r7, #16]
+      Init.HardwareFlowControl = hsd->Init.HardwareFlowControl;
+ 800b650:	687b      	ldr	r3, [r7, #4]
+ 800b652:	691b      	ldr	r3, [r3, #16]
+ 800b654:	617b      	str	r3, [r7, #20]
+
+      /* Check if user Clock div < Normal speed 25Mhz, no change in Clockdiv */
+      if (hsd->Init.ClockDiv >= (sdmmc_clk / (2U * SD_NORMAL_SPEED_FREQ)))
+ 800b656:	687b      	ldr	r3, [r7, #4]
+ 800b658:	695a      	ldr	r2, [r3, #20]
+ 800b65a:	69fb      	ldr	r3, [r7, #28]
+ 800b65c:	4950      	ldr	r1, [pc, #320]	; (800b7a0 <HAL_SD_ConfigWideBusOperation+0x218>)
+ 800b65e:	fba1 1303 	umull	r1, r3, r1, r3
+ 800b662:	0e1b      	lsrs	r3, r3, #24
+ 800b664:	429a      	cmp	r2, r3
+ 800b666:	d303      	bcc.n	800b670 <HAL_SD_ConfigWideBusOperation+0xe8>
+      {
+        Init.ClockDiv = hsd->Init.ClockDiv;
+ 800b668:	687b      	ldr	r3, [r7, #4]
+ 800b66a:	695b      	ldr	r3, [r3, #20]
+ 800b66c:	61bb      	str	r3, [r7, #24]
+ 800b66e:	e05a      	b.n	800b726 <HAL_SD_ConfigWideBusOperation+0x19e>
+      }
+      else if (hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED)
+ 800b670:	687b      	ldr	r3, [r7, #4]
+ 800b672:	6d9b      	ldr	r3, [r3, #88]	; 0x58
+ 800b674:	f5b3 7f00 	cmp.w	r3, #512	; 0x200
+ 800b678:	d103      	bne.n	800b682 <HAL_SD_ConfigWideBusOperation+0xfa>
+      {
+        /* UltraHigh speed SD card,user Clock div */
+        Init.ClockDiv = hsd->Init.ClockDiv;
+ 800b67a:	687b      	ldr	r3, [r7, #4]
+ 800b67c:	695b      	ldr	r3, [r3, #20]
+ 800b67e:	61bb      	str	r3, [r7, #24]
+ 800b680:	e051      	b.n	800b726 <HAL_SD_ConfigWideBusOperation+0x19e>
+      }
+      else if (hsd->SdCard.CardSpeed == CARD_HIGH_SPEED)
+ 800b682:	687b      	ldr	r3, [r7, #4]
+ 800b684:	6d9b      	ldr	r3, [r3, #88]	; 0x58
+ 800b686:	f5b3 7f80 	cmp.w	r3, #256	; 0x100
+ 800b68a:	d126      	bne.n	800b6da <HAL_SD_ConfigWideBusOperation+0x152>
+      {
+        /* High speed SD card, Max Frequency = 50Mhz */
+        if (hsd->Init.ClockDiv == 0U)
+ 800b68c:	687b      	ldr	r3, [r7, #4]
+ 800b68e:	695b      	ldr	r3, [r3, #20]
+ 800b690:	2b00      	cmp	r3, #0
+ 800b692:	d10e      	bne.n	800b6b2 <HAL_SD_ConfigWideBusOperation+0x12a>
+        {
+          if (sdmmc_clk > SD_HIGH_SPEED_FREQ)
+ 800b694:	69fb      	ldr	r3, [r7, #28]
+ 800b696:	4a43      	ldr	r2, [pc, #268]	; (800b7a4 <HAL_SD_ConfigWideBusOperation+0x21c>)
+ 800b698:	4293      	cmp	r3, r2
+ 800b69a:	d906      	bls.n	800b6aa <HAL_SD_ConfigWideBusOperation+0x122>
+          {
+            Init.ClockDiv = sdmmc_clk / (2U * SD_HIGH_SPEED_FREQ);
+ 800b69c:	69fb      	ldr	r3, [r7, #28]
+ 800b69e:	4a40      	ldr	r2, [pc, #256]	; (800b7a0 <HAL_SD_ConfigWideBusOperation+0x218>)
+ 800b6a0:	fba2 2303 	umull	r2, r3, r2, r3
+ 800b6a4:	0e5b      	lsrs	r3, r3, #25
+ 800b6a6:	61bb      	str	r3, [r7, #24]
+ 800b6a8:	e03d      	b.n	800b726 <HAL_SD_ConfigWideBusOperation+0x19e>
+          }
+          else
+          {
+            Init.ClockDiv = hsd->Init.ClockDiv;
+ 800b6aa:	687b      	ldr	r3, [r7, #4]
+ 800b6ac:	695b      	ldr	r3, [r3, #20]
+ 800b6ae:	61bb      	str	r3, [r7, #24]
+ 800b6b0:	e039      	b.n	800b726 <HAL_SD_ConfigWideBusOperation+0x19e>
+          }
+        }
+        else
+        {
+          if ((sdmmc_clk / (2U * hsd->Init.ClockDiv)) > SD_HIGH_SPEED_FREQ)
+ 800b6b2:	687b      	ldr	r3, [r7, #4]
+ 800b6b4:	695b      	ldr	r3, [r3, #20]
+ 800b6b6:	005b      	lsls	r3, r3, #1
+ 800b6b8:	69fa      	ldr	r2, [r7, #28]
+ 800b6ba:	fbb2 f3f3 	udiv	r3, r2, r3
+ 800b6be:	4a39      	ldr	r2, [pc, #228]	; (800b7a4 <HAL_SD_ConfigWideBusOperation+0x21c>)
+ 800b6c0:	4293      	cmp	r3, r2
+ 800b6c2:	d906      	bls.n	800b6d2 <HAL_SD_ConfigWideBusOperation+0x14a>
+          {
+            Init.ClockDiv = sdmmc_clk / (2U * SD_HIGH_SPEED_FREQ);
+ 800b6c4:	69fb      	ldr	r3, [r7, #28]
+ 800b6c6:	4a36      	ldr	r2, [pc, #216]	; (800b7a0 <HAL_SD_ConfigWideBusOperation+0x218>)
+ 800b6c8:	fba2 2303 	umull	r2, r3, r2, r3
+ 800b6cc:	0e5b      	lsrs	r3, r3, #25
+ 800b6ce:	61bb      	str	r3, [r7, #24]
+ 800b6d0:	e029      	b.n	800b726 <HAL_SD_ConfigWideBusOperation+0x19e>
+          }
+          else
+          {
+            Init.ClockDiv = hsd->Init.ClockDiv;
+ 800b6d2:	687b      	ldr	r3, [r7, #4]
+ 800b6d4:	695b      	ldr	r3, [r3, #20]
+ 800b6d6:	61bb      	str	r3, [r7, #24]
+ 800b6d8:	e025      	b.n	800b726 <HAL_SD_ConfigWideBusOperation+0x19e>
+        }
+      }
+      else
+      {
+        /* No High speed SD card, Max Frequency = 25Mhz */
+        if (hsd->Init.ClockDiv == 0U)
+ 800b6da:	687b      	ldr	r3, [r7, #4]
+ 800b6dc:	695b      	ldr	r3, [r3, #20]
+ 800b6de:	2b00      	cmp	r3, #0
+ 800b6e0:	d10e      	bne.n	800b700 <HAL_SD_ConfigWideBusOperation+0x178>
+        {
+          if (sdmmc_clk > SD_NORMAL_SPEED_FREQ)
+ 800b6e2:	69fb      	ldr	r3, [r7, #28]
+ 800b6e4:	4a30      	ldr	r2, [pc, #192]	; (800b7a8 <HAL_SD_ConfigWideBusOperation+0x220>)
+ 800b6e6:	4293      	cmp	r3, r2
+ 800b6e8:	d906      	bls.n	800b6f8 <HAL_SD_ConfigWideBusOperation+0x170>
+          {
+            Init.ClockDiv = sdmmc_clk / (2U * SD_NORMAL_SPEED_FREQ);
+ 800b6ea:	69fb      	ldr	r3, [r7, #28]
+ 800b6ec:	4a2c      	ldr	r2, [pc, #176]	; (800b7a0 <HAL_SD_ConfigWideBusOperation+0x218>)
+ 800b6ee:	fba2 2303 	umull	r2, r3, r2, r3
+ 800b6f2:	0e1b      	lsrs	r3, r3, #24
+ 800b6f4:	61bb      	str	r3, [r7, #24]
+ 800b6f6:	e016      	b.n	800b726 <HAL_SD_ConfigWideBusOperation+0x19e>
+          }
+          else
+          {
+            Init.ClockDiv = hsd->Init.ClockDiv;
+ 800b6f8:	687b      	ldr	r3, [r7, #4]
+ 800b6fa:	695b      	ldr	r3, [r3, #20]
+ 800b6fc:	61bb      	str	r3, [r7, #24]
+ 800b6fe:	e012      	b.n	800b726 <HAL_SD_ConfigWideBusOperation+0x19e>
+          }
+        }
+        else
+        {
+          if ((sdmmc_clk / (2U * hsd->Init.ClockDiv)) > SD_NORMAL_SPEED_FREQ)
+ 800b700:	687b      	ldr	r3, [r7, #4]
+ 800b702:	695b      	ldr	r3, [r3, #20]
+ 800b704:	005b      	lsls	r3, r3, #1
+ 800b706:	69fa      	ldr	r2, [r7, #28]
+ 800b708:	fbb2 f3f3 	udiv	r3, r2, r3
+ 800b70c:	4a26      	ldr	r2, [pc, #152]	; (800b7a8 <HAL_SD_ConfigWideBusOperation+0x220>)
+ 800b70e:	4293      	cmp	r3, r2
+ 800b710:	d906      	bls.n	800b720 <HAL_SD_ConfigWideBusOperation+0x198>
+          {
+            Init.ClockDiv = sdmmc_clk / (2U * SD_NORMAL_SPEED_FREQ);
+ 800b712:	69fb      	ldr	r3, [r7, #28]
+ 800b714:	4a22      	ldr	r2, [pc, #136]	; (800b7a0 <HAL_SD_ConfigWideBusOperation+0x218>)
+ 800b716:	fba2 2303 	umull	r2, r3, r2, r3
+ 800b71a:	0e1b      	lsrs	r3, r3, #24
+ 800b71c:	61bb      	str	r3, [r7, #24]
+ 800b71e:	e002      	b.n	800b726 <HAL_SD_ConfigWideBusOperation+0x19e>
+          }
+          else
+          {
+            Init.ClockDiv = hsd->Init.ClockDiv;
+ 800b720:	687b      	ldr	r3, [r7, #4]
+ 800b722:	695b      	ldr	r3, [r3, #20]
+ 800b724:	61bb      	str	r3, [r7, #24]
+
+#if (USE_SD_TRANSCEIVER != 0U)
+      Init.TranceiverPresent = hsd->Init.TranceiverPresent;
+#endif /* USE_SD_TRANSCEIVER */
+
+      (void)SDMMC_Init(hsd->Instance, Init);
+ 800b726:	687b      	ldr	r3, [r7, #4]
+ 800b728:	681c      	ldr	r4, [r3, #0]
+ 800b72a:	466a      	mov	r2, sp
+ 800b72c:	f107 0314 	add.w	r3, r7, #20
+ 800b730:	e893 0003 	ldmia.w	r3, {r0, r1}
+ 800b734:	e882 0003 	stmia.w	r2, {r0, r1}
+ 800b738:	f107 0308 	add.w	r3, r7, #8
+ 800b73c:	cb0e      	ldmia	r3, {r1, r2, r3}
+ 800b73e:	4620      	mov	r0, r4
+ 800b740:	f002 fbbc 	bl	800debc <SDMMC_Init>
+ 800b744:	e008      	b.n	800b758 <HAL_SD_ConfigWideBusOperation+0x1d0>
+    }
+    else
+    {
+      hsd->ErrorCode |= SDMMC_ERROR_INVALID_PARAMETER;
+ 800b746:	687b      	ldr	r3, [r7, #4]
+ 800b748:	6b5b      	ldr	r3, [r3, #52]	; 0x34
+ 800b74a:	f043 6200 	orr.w	r2, r3, #134217728	; 0x8000000
+ 800b74e:	687b      	ldr	r3, [r7, #4]
+ 800b750:	635a      	str	r2, [r3, #52]	; 0x34
+      status = HAL_ERROR;
+ 800b752:	2301      	movs	r3, #1
+ 800b754:	f887 3027 	strb.w	r3, [r7, #39]	; 0x27
+    }
+  }
+
+  /* Set Block Size for Card */
+  errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
+ 800b758:	687b      	ldr	r3, [r7, #4]
+ 800b75a:	681b      	ldr	r3, [r3, #0]
+ 800b75c:	f44f 7100 	mov.w	r1, #512	; 0x200
+ 800b760:	4618      	mov	r0, r3
+ 800b762:	f002 fc89 	bl	800e078 <SDMMC_CmdBlockLength>
+ 800b766:	6238      	str	r0, [r7, #32]
+  if (errorstate != HAL_SD_ERROR_NONE)
+ 800b768:	6a3b      	ldr	r3, [r7, #32]
+ 800b76a:	2b00      	cmp	r3, #0
+ 800b76c:	d00c      	beq.n	800b788 <HAL_SD_ConfigWideBusOperation+0x200>
+  {
+    /* Clear all the static flags */
+    __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+ 800b76e:	687b      	ldr	r3, [r7, #4]
+ 800b770:	681b      	ldr	r3, [r3, #0]
+ 800b772:	4a0a      	ldr	r2, [pc, #40]	; (800b79c <HAL_SD_ConfigWideBusOperation+0x214>)
+ 800b774:	639a      	str	r2, [r3, #56]	; 0x38
+    hsd->ErrorCode |= errorstate;
+ 800b776:	687b      	ldr	r3, [r7, #4]
+ 800b778:	6b5a      	ldr	r2, [r3, #52]	; 0x34
+ 800b77a:	6a3b      	ldr	r3, [r7, #32]
+ 800b77c:	431a      	orrs	r2, r3
+ 800b77e:	687b      	ldr	r3, [r7, #4]
+ 800b780:	635a      	str	r2, [r3, #52]	; 0x34
+    status = HAL_ERROR;
+ 800b782:	2301      	movs	r3, #1
+ 800b784:	f887 3027 	strb.w	r3, [r7, #39]	; 0x27
+  }
+
+  /* Change State */
+  hsd->State = HAL_SD_STATE_READY;
+ 800b788:	687b      	ldr	r3, [r7, #4]
+ 800b78a:	2201      	movs	r2, #1
+ 800b78c:	f883 2030 	strb.w	r2, [r3, #48]	; 0x30
+
+  return status;
+ 800b790:	f897 3027 	ldrb.w	r3, [r7, #39]	; 0x27
+}
+ 800b794:	4618      	mov	r0, r3
+ 800b796:	372c      	adds	r7, #44	; 0x2c
+ 800b798:	46bd      	mov	sp, r7
+ 800b79a:	bd90      	pop	{r4, r7, pc}
+ 800b79c:	1fe00fff 	.word	0x1fe00fff
+ 800b7a0:	55e63b89 	.word	0x55e63b89
+ 800b7a4:	02faf080 	.word	0x02faf080
+ 800b7a8:	017d7840 	.word	0x017d7840
+
+0800b7ac <HAL_SD_GetCardState>:
+  * @brief  Gets the current sd card data state.
+  * @param  hsd: pointer to SD handle
+  * @retval Card state
+  */
+HAL_SD_CardStateTypeDef HAL_SD_GetCardState(SD_HandleTypeDef *hsd)
+{
+ 800b7ac:	b580      	push	{r7, lr}
+ 800b7ae:	b086      	sub	sp, #24
+ 800b7b0:	af00      	add	r7, sp, #0
+ 800b7b2:	6078      	str	r0, [r7, #4]
+  uint32_t cardstate;
+  uint32_t errorstate;
+  uint32_t resp1 = 0;
+ 800b7b4:	2300      	movs	r3, #0
+ 800b7b6:	60fb      	str	r3, [r7, #12]
+
+  errorstate = SD_SendStatus(hsd, &resp1);
+ 800b7b8:	f107 030c 	add.w	r3, r7, #12
+ 800b7bc:	4619      	mov	r1, r3
+ 800b7be:	6878      	ldr	r0, [r7, #4]
+ 800b7c0:	f000 fa40 	bl	800bc44 <SD_SendStatus>
+ 800b7c4:	6178      	str	r0, [r7, #20]
+  if (errorstate != HAL_SD_ERROR_NONE)
+ 800b7c6:	697b      	ldr	r3, [r7, #20]
+ 800b7c8:	2b00      	cmp	r3, #0
+ 800b7ca:	d005      	beq.n	800b7d8 <HAL_SD_GetCardState+0x2c>
+  {
+    hsd->ErrorCode |= errorstate;
+ 800b7cc:	687b      	ldr	r3, [r7, #4]
+ 800b7ce:	6b5a      	ldr	r2, [r3, #52]	; 0x34
+ 800b7d0:	697b      	ldr	r3, [r7, #20]
+ 800b7d2:	431a      	orrs	r2, r3
+ 800b7d4:	687b      	ldr	r3, [r7, #4]
+ 800b7d6:	635a      	str	r2, [r3, #52]	; 0x34
+  }
+
+  cardstate = ((resp1 >> 9U) & 0x0FU);
+ 800b7d8:	68fb      	ldr	r3, [r7, #12]
+ 800b7da:	0a5b      	lsrs	r3, r3, #9
+ 800b7dc:	f003 030f 	and.w	r3, r3, #15
+ 800b7e0:	613b      	str	r3, [r7, #16]
+
+  return (HAL_SD_CardStateTypeDef)cardstate;
+ 800b7e2:	693b      	ldr	r3, [r7, #16]
+}
+ 800b7e4:	4618      	mov	r0, r3
+ 800b7e6:	3718      	adds	r7, #24
+ 800b7e8:	46bd      	mov	sp, r7
+ 800b7ea:	bd80      	pop	{r7, pc}
+
+0800b7ec <SD_InitCard>:
+  * @brief  Initializes the sd card.
+  * @param  hsd: Pointer to SD handle
+  * @retval SD Card error state
+  */
+static uint32_t SD_InitCard(SD_HandleTypeDef *hsd)
+{
+ 800b7ec:	b580      	push	{r7, lr}
+ 800b7ee:	b090      	sub	sp, #64	; 0x40
+ 800b7f0:	af00      	add	r7, sp, #0
+ 800b7f2:	6078      	str	r0, [r7, #4]
+  HAL_SD_CardCSDTypeDef CSD;
+  uint32_t errorstate;
+  uint16_t sd_rca = 0U;
+ 800b7f4:	2300      	movs	r3, #0
+ 800b7f6:	817b      	strh	r3, [r7, #10]
+  uint32_t tickstart = HAL_GetTick();
+ 800b7f8:	f7f6 fdb4 	bl	8002364 <HAL_GetTick>
+ 800b7fc:	63f8      	str	r0, [r7, #60]	; 0x3c
+
+  /* Check the power State */
+  if (SDMMC_GetPowerState(hsd->Instance) == 0U)
+ 800b7fe:	687b      	ldr	r3, [r7, #4]
+ 800b800:	681b      	ldr	r3, [r3, #0]
+ 800b802:	4618      	mov	r0, r3
+ 800b804:	f002 fbb3 	bl	800df6e <SDMMC_GetPowerState>
+ 800b808:	4603      	mov	r3, r0
+ 800b80a:	2b00      	cmp	r3, #0
+ 800b80c:	d102      	bne.n	800b814 <SD_InitCard+0x28>
+  {
+    /* Power off */
+    return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE;
+ 800b80e:	f04f 6380 	mov.w	r3, #67108864	; 0x4000000
+ 800b812:	e0b5      	b.n	800b980 <SD_InitCard+0x194>
+  }
+
+  if (hsd->SdCard.CardType != CARD_SECURED)
+ 800b814:	687b      	ldr	r3, [r7, #4]
+ 800b816:	6b9b      	ldr	r3, [r3, #56]	; 0x38
+ 800b818:	2b03      	cmp	r3, #3
+ 800b81a:	d02e      	beq.n	800b87a <SD_InitCard+0x8e>
+  {
+    /* Send CMD2 ALL_SEND_CID */
+    errorstate = SDMMC_CmdSendCID(hsd->Instance);
+ 800b81c:	687b      	ldr	r3, [r7, #4]
+ 800b81e:	681b      	ldr	r3, [r3, #0]
+ 800b820:	4618      	mov	r0, r3
+ 800b822:	f002 fdfe 	bl	800e422 <SDMMC_CmdSendCID>
+ 800b826:	63b8      	str	r0, [r7, #56]	; 0x38
+    if (errorstate != HAL_SD_ERROR_NONE)
+ 800b828:	6bbb      	ldr	r3, [r7, #56]	; 0x38
+ 800b82a:	2b00      	cmp	r3, #0
+ 800b82c:	d001      	beq.n	800b832 <SD_InitCard+0x46>
+    {
+      return errorstate;
+ 800b82e:	6bbb      	ldr	r3, [r7, #56]	; 0x38
+ 800b830:	e0a6      	b.n	800b980 <SD_InitCard+0x194>
+    }
+    else
+    {
+      /* Get Card identification number data */
+      hsd->CID[0U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1);
+ 800b832:	687b      	ldr	r3, [r7, #4]
+ 800b834:	681b      	ldr	r3, [r3, #0]
+ 800b836:	2100      	movs	r1, #0
+ 800b838:	4618      	mov	r0, r3
+ 800b83a:	f002 fbde 	bl	800dffa <SDMMC_GetResponse>
+ 800b83e:	4602      	mov	r2, r0
+ 800b840:	687b      	ldr	r3, [r7, #4]
+ 800b842:	66da      	str	r2, [r3, #108]	; 0x6c
+      hsd->CID[1U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP2);
+ 800b844:	687b      	ldr	r3, [r7, #4]
+ 800b846:	681b      	ldr	r3, [r3, #0]
+ 800b848:	2104      	movs	r1, #4
+ 800b84a:	4618      	mov	r0, r3
+ 800b84c:	f002 fbd5 	bl	800dffa <SDMMC_GetResponse>
+ 800b850:	4602      	mov	r2, r0
+ 800b852:	687b      	ldr	r3, [r7, #4]
+ 800b854:	671a      	str	r2, [r3, #112]	; 0x70
+      hsd->CID[2U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP3);
+ 800b856:	687b      	ldr	r3, [r7, #4]
+ 800b858:	681b      	ldr	r3, [r3, #0]
+ 800b85a:	2108      	movs	r1, #8
+ 800b85c:	4618      	mov	r0, r3
+ 800b85e:	f002 fbcc 	bl	800dffa <SDMMC_GetResponse>
+ 800b862:	4602      	mov	r2, r0
+ 800b864:	687b      	ldr	r3, [r7, #4]
+ 800b866:	675a      	str	r2, [r3, #116]	; 0x74
+      hsd->CID[3U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP4);
+ 800b868:	687b      	ldr	r3, [r7, #4]
+ 800b86a:	681b      	ldr	r3, [r3, #0]
+ 800b86c:	210c      	movs	r1, #12
+ 800b86e:	4618      	mov	r0, r3
+ 800b870:	f002 fbc3 	bl	800dffa <SDMMC_GetResponse>
+ 800b874:	4602      	mov	r2, r0
+ 800b876:	687b      	ldr	r3, [r7, #4]
+ 800b878:	679a      	str	r2, [r3, #120]	; 0x78
+    }
+  }
+
+  if (hsd->SdCard.CardType != CARD_SECURED)
+ 800b87a:	687b      	ldr	r3, [r7, #4]
+ 800b87c:	6b9b      	ldr	r3, [r3, #56]	; 0x38
+ 800b87e:	2b03      	cmp	r3, #3
+ 800b880:	d01d      	beq.n	800b8be <SD_InitCard+0xd2>
+  {
+    /* Send CMD3 SET_REL_ADDR with argument 0 */
+    /* SD Card publishes its RCA. */
+    while (sd_rca == 0U)
+ 800b882:	e019      	b.n	800b8b8 <SD_InitCard+0xcc>
+    {
+      errorstate = SDMMC_CmdSetRelAdd(hsd->Instance, &sd_rca);
+ 800b884:	687b      	ldr	r3, [r7, #4]
+ 800b886:	681b      	ldr	r3, [r3, #0]
+ 800b888:	f107 020a 	add.w	r2, r7, #10
+ 800b88c:	4611      	mov	r1, r2
+ 800b88e:	4618      	mov	r0, r3
+ 800b890:	f002 fe06 	bl	800e4a0 <SDMMC_CmdSetRelAdd>
+ 800b894:	63b8      	str	r0, [r7, #56]	; 0x38
+      if (errorstate != HAL_SD_ERROR_NONE)
+ 800b896:	6bbb      	ldr	r3, [r7, #56]	; 0x38
+ 800b898:	2b00      	cmp	r3, #0
+ 800b89a:	d001      	beq.n	800b8a0 <SD_InitCard+0xb4>
+      {
+        return errorstate;
+ 800b89c:	6bbb      	ldr	r3, [r7, #56]	; 0x38
+ 800b89e:	e06f      	b.n	800b980 <SD_InitCard+0x194>
+      }
+      if ((HAL_GetTick() - tickstart) >=  SDMMC_CMDTIMEOUT)
+ 800b8a0:	f7f6 fd60 	bl	8002364 <HAL_GetTick>
+ 800b8a4:	4602      	mov	r2, r0
+ 800b8a6:	6bfb      	ldr	r3, [r7, #60]	; 0x3c
+ 800b8a8:	1ad3      	subs	r3, r2, r3
+ 800b8aa:	f241 3287 	movw	r2, #4999	; 0x1387
+ 800b8ae:	4293      	cmp	r3, r2
+ 800b8b0:	d902      	bls.n	800b8b8 <SD_InitCard+0xcc>
+      {
+        return HAL_SD_ERROR_TIMEOUT;
+ 800b8b2:	f04f 4300 	mov.w	r3, #2147483648	; 0x80000000
+ 800b8b6:	e063      	b.n	800b980 <SD_InitCard+0x194>
+    while (sd_rca == 0U)
+ 800b8b8:	897b      	ldrh	r3, [r7, #10]
+ 800b8ba:	2b00      	cmp	r3, #0
+ 800b8bc:	d0e2      	beq.n	800b884 <SD_InitCard+0x98>
+      }
+    }
+  }
+  if (hsd->SdCard.CardType != CARD_SECURED)
+ 800b8be:	687b      	ldr	r3, [r7, #4]
+ 800b8c0:	6b9b      	ldr	r3, [r3, #56]	; 0x38
+ 800b8c2:	2b03      	cmp	r3, #3
+ 800b8c4:	d036      	beq.n	800b934 <SD_InitCard+0x148>
+  {
+    /* Get the SD card RCA */
+    hsd->SdCard.RelCardAdd = sd_rca;
+ 800b8c6:	897b      	ldrh	r3, [r7, #10]
+ 800b8c8:	461a      	mov	r2, r3
+ 800b8ca:	687b      	ldr	r3, [r7, #4]
+ 800b8cc:	645a      	str	r2, [r3, #68]	; 0x44
+
+    /* Send CMD9 SEND_CSD with argument as card's RCA */
+    errorstate = SDMMC_CmdSendCSD(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U));
+ 800b8ce:	687b      	ldr	r3, [r7, #4]
+ 800b8d0:	681a      	ldr	r2, [r3, #0]
+ 800b8d2:	687b      	ldr	r3, [r7, #4]
+ 800b8d4:	6c5b      	ldr	r3, [r3, #68]	; 0x44
+ 800b8d6:	041b      	lsls	r3, r3, #16
+ 800b8d8:	4619      	mov	r1, r3
+ 800b8da:	4610      	mov	r0, r2
+ 800b8dc:	f002 fdc0 	bl	800e460 <SDMMC_CmdSendCSD>
+ 800b8e0:	63b8      	str	r0, [r7, #56]	; 0x38
+    if (errorstate != HAL_SD_ERROR_NONE)
+ 800b8e2:	6bbb      	ldr	r3, [r7, #56]	; 0x38
+ 800b8e4:	2b00      	cmp	r3, #0
+ 800b8e6:	d001      	beq.n	800b8ec <SD_InitCard+0x100>
+    {
+      return errorstate;
+ 800b8e8:	6bbb      	ldr	r3, [r7, #56]	; 0x38
+ 800b8ea:	e049      	b.n	800b980 <SD_InitCard+0x194>
+    }
+    else
+    {
+      /* Get Card Specific Data */
+      hsd->CSD[0U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1);
+ 800b8ec:	687b      	ldr	r3, [r7, #4]
+ 800b8ee:	681b      	ldr	r3, [r3, #0]
+ 800b8f0:	2100      	movs	r1, #0
+ 800b8f2:	4618      	mov	r0, r3
+ 800b8f4:	f002 fb81 	bl	800dffa <SDMMC_GetResponse>
+ 800b8f8:	4602      	mov	r2, r0
+ 800b8fa:	687b      	ldr	r3, [r7, #4]
+ 800b8fc:	65da      	str	r2, [r3, #92]	; 0x5c
+      hsd->CSD[1U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP2);
+ 800b8fe:	687b      	ldr	r3, [r7, #4]
+ 800b900:	681b      	ldr	r3, [r3, #0]
+ 800b902:	2104      	movs	r1, #4
+ 800b904:	4618      	mov	r0, r3
+ 800b906:	f002 fb78 	bl	800dffa <SDMMC_GetResponse>
+ 800b90a:	4602      	mov	r2, r0
+ 800b90c:	687b      	ldr	r3, [r7, #4]
+ 800b90e:	661a      	str	r2, [r3, #96]	; 0x60
+      hsd->CSD[2U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP3);
+ 800b910:	687b      	ldr	r3, [r7, #4]
+ 800b912:	681b      	ldr	r3, [r3, #0]
+ 800b914:	2108      	movs	r1, #8
+ 800b916:	4618      	mov	r0, r3
+ 800b918:	f002 fb6f 	bl	800dffa <SDMMC_GetResponse>
+ 800b91c:	4602      	mov	r2, r0
+ 800b91e:	687b      	ldr	r3, [r7, #4]
+ 800b920:	665a      	str	r2, [r3, #100]	; 0x64
+      hsd->CSD[3U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP4);
+ 800b922:	687b      	ldr	r3, [r7, #4]
+ 800b924:	681b      	ldr	r3, [r3, #0]
+ 800b926:	210c      	movs	r1, #12
+ 800b928:	4618      	mov	r0, r3
+ 800b92a:	f002 fb66 	bl	800dffa <SDMMC_GetResponse>
+ 800b92e:	4602      	mov	r2, r0
+ 800b930:	687b      	ldr	r3, [r7, #4]
+ 800b932:	669a      	str	r2, [r3, #104]	; 0x68
+    }
+  }
+
+  /* Get the Card Class */
+  hsd->SdCard.Class = (SDMMC_GetResponse(hsd->Instance, SDMMC_RESP2) >> 20U);
+ 800b934:	687b      	ldr	r3, [r7, #4]
+ 800b936:	681b      	ldr	r3, [r3, #0]
+ 800b938:	2104      	movs	r1, #4
+ 800b93a:	4618      	mov	r0, r3
+ 800b93c:	f002 fb5d 	bl	800dffa <SDMMC_GetResponse>
+ 800b940:	4603      	mov	r3, r0
+ 800b942:	0d1a      	lsrs	r2, r3, #20
+ 800b944:	687b      	ldr	r3, [r7, #4]
+ 800b946:	641a      	str	r2, [r3, #64]	; 0x40
+
+  /* Get CSD parameters */
+  if (HAL_SD_GetCardCSD(hsd, &CSD) != HAL_OK)
+ 800b948:	f107 030c 	add.w	r3, r7, #12
+ 800b94c:	4619      	mov	r1, r3
+ 800b94e:	6878      	ldr	r0, [r7, #4]
+ 800b950:	f7ff fb8c 	bl	800b06c <HAL_SD_GetCardCSD>
+ 800b954:	4603      	mov	r3, r0
+ 800b956:	2b00      	cmp	r3, #0
+ 800b958:	d002      	beq.n	800b960 <SD_InitCard+0x174>
+  {
+    return HAL_SD_ERROR_UNSUPPORTED_FEATURE;
+ 800b95a:	f04f 5380 	mov.w	r3, #268435456	; 0x10000000
+ 800b95e:	e00f      	b.n	800b980 <SD_InitCard+0x194>
+  }
+
+  /* Select the Card */
+  errorstate = SDMMC_CmdSelDesel(hsd->Instance, (uint32_t)(((uint32_t)hsd->SdCard.RelCardAdd) << 16U));
+ 800b960:	687b      	ldr	r3, [r7, #4]
+ 800b962:	681a      	ldr	r2, [r3, #0]
+ 800b964:	687b      	ldr	r3, [r7, #4]
+ 800b966:	6c5b      	ldr	r3, [r3, #68]	; 0x44
+ 800b968:	041b      	lsls	r3, r3, #16
+ 800b96a:	4619      	mov	r1, r3
+ 800b96c:	4610      	mov	r0, r2
+ 800b96e:	f002 fc6f 	bl	800e250 <SDMMC_CmdSelDesel>
+ 800b972:	63b8      	str	r0, [r7, #56]	; 0x38
+  if (errorstate != HAL_SD_ERROR_NONE)
+ 800b974:	6bbb      	ldr	r3, [r7, #56]	; 0x38
+ 800b976:	2b00      	cmp	r3, #0
+ 800b978:	d001      	beq.n	800b97e <SD_InitCard+0x192>
+  {
+    return errorstate;
+ 800b97a:	6bbb      	ldr	r3, [r7, #56]	; 0x38
+ 800b97c:	e000      	b.n	800b980 <SD_InitCard+0x194>
+  }
+
+  /* All cards are initialized */
+  return HAL_SD_ERROR_NONE;
+ 800b97e:	2300      	movs	r3, #0
+}
+ 800b980:	4618      	mov	r0, r3
+ 800b982:	3740      	adds	r7, #64	; 0x40
+ 800b984:	46bd      	mov	sp, r7
+ 800b986:	bd80      	pop	{r7, pc}
+
+0800b988 <SD_PowerON>:
+  *         in the SD handle.
+  * @param  hsd: Pointer to SD handle
+  * @retval error state
+  */
+static uint32_t SD_PowerON(SD_HandleTypeDef *hsd)
+{
+ 800b988:	b580      	push	{r7, lr}
+ 800b98a:	b086      	sub	sp, #24
+ 800b98c:	af00      	add	r7, sp, #0
+ 800b98e:	6078      	str	r0, [r7, #4]
+  __IO uint32_t count = 0U;
+ 800b990:	2300      	movs	r3, #0
+ 800b992:	60bb      	str	r3, [r7, #8]
+  uint32_t response = 0U;
+ 800b994:	2300      	movs	r3, #0
+ 800b996:	617b      	str	r3, [r7, #20]
+  uint32_t validvoltage = 0U;
+ 800b998:	2300      	movs	r3, #0
+ 800b99a:	613b      	str	r3, [r7, #16]
+#if (USE_SD_TRANSCEIVER != 0U)
+  uint32_t tickstart = HAL_GetTick();
+#endif /* USE_SD_TRANSCEIVER  */
+
+  /* CMD0: GO_IDLE_STATE */
+  errorstate = SDMMC_CmdGoIdleState(hsd->Instance);
+ 800b99c:	687b      	ldr	r3, [r7, #4]
+ 800b99e:	681b      	ldr	r3, [r3, #0]
+ 800b9a0:	4618      	mov	r0, r3
+ 800b9a2:	f002 fc78 	bl	800e296 <SDMMC_CmdGoIdleState>
+ 800b9a6:	60f8      	str	r0, [r7, #12]
+  if (errorstate != HAL_SD_ERROR_NONE)
+ 800b9a8:	68fb      	ldr	r3, [r7, #12]
+ 800b9aa:	2b00      	cmp	r3, #0
+ 800b9ac:	d001      	beq.n	800b9b2 <SD_PowerON+0x2a>
+  {
+    return errorstate;
+ 800b9ae:	68fb      	ldr	r3, [r7, #12]
+ 800b9b0:	e072      	b.n	800ba98 <SD_PowerON+0x110>
+  }
+
+  /* CMD8: SEND_IF_COND: Command available only on V2.0 cards */
+  errorstate = SDMMC_CmdOperCond(hsd->Instance);
+ 800b9b2:	687b      	ldr	r3, [r7, #4]
+ 800b9b4:	681b      	ldr	r3, [r3, #0]
+ 800b9b6:	4618      	mov	r0, r3
+ 800b9b8:	f002 fc8b 	bl	800e2d2 <SDMMC_CmdOperCond>
+ 800b9bc:	60f8      	str	r0, [r7, #12]
+  if (errorstate == SDMMC_ERROR_TIMEOUT) /* No response to CMD8 */
+ 800b9be:	68fb      	ldr	r3, [r7, #12]
+ 800b9c0:	f1b3 4f00 	cmp.w	r3, #2147483648	; 0x80000000
+ 800b9c4:	d10d      	bne.n	800b9e2 <SD_PowerON+0x5a>
+  {
+    hsd->SdCard.CardVersion = CARD_V1_X;
+ 800b9c6:	687b      	ldr	r3, [r7, #4]
+ 800b9c8:	2200      	movs	r2, #0
+ 800b9ca:	63da      	str	r2, [r3, #60]	; 0x3c
+    /* CMD0: GO_IDLE_STATE */
+    errorstate = SDMMC_CmdGoIdleState(hsd->Instance);
+ 800b9cc:	687b      	ldr	r3, [r7, #4]
+ 800b9ce:	681b      	ldr	r3, [r3, #0]
+ 800b9d0:	4618      	mov	r0, r3
+ 800b9d2:	f002 fc60 	bl	800e296 <SDMMC_CmdGoIdleState>
+ 800b9d6:	60f8      	str	r0, [r7, #12]
+    if (errorstate != HAL_SD_ERROR_NONE)
+ 800b9d8:	68fb      	ldr	r3, [r7, #12]
+ 800b9da:	2b00      	cmp	r3, #0
+ 800b9dc:	d004      	beq.n	800b9e8 <SD_PowerON+0x60>
+    {
+      return errorstate;
+ 800b9de:	68fb      	ldr	r3, [r7, #12]
+ 800b9e0:	e05a      	b.n	800ba98 <SD_PowerON+0x110>
+    }
+
+  }
+  else
+  {
+    hsd->SdCard.CardVersion = CARD_V2_X;
+ 800b9e2:	687b      	ldr	r3, [r7, #4]
+ 800b9e4:	2201      	movs	r2, #1
+ 800b9e6:	63da      	str	r2, [r3, #60]	; 0x3c
+  }
+
+  if (hsd->SdCard.CardVersion == CARD_V2_X)
+ 800b9e8:	687b      	ldr	r3, [r7, #4]
+ 800b9ea:	6bdb      	ldr	r3, [r3, #60]	; 0x3c
+ 800b9ec:	2b01      	cmp	r3, #1
+ 800b9ee:	d137      	bne.n	800ba60 <SD_PowerON+0xd8>
+  {
+    /* SEND CMD55 APP_CMD with RCA as 0 */
+    errorstate = SDMMC_CmdAppCommand(hsd->Instance, 0);
+ 800b9f0:	687b      	ldr	r3, [r7, #4]
+ 800b9f2:	681b      	ldr	r3, [r3, #0]
+ 800b9f4:	2100      	movs	r1, #0
+ 800b9f6:	4618      	mov	r0, r3
+ 800b9f8:	f002 fc8b 	bl	800e312 <SDMMC_CmdAppCommand>
+ 800b9fc:	60f8      	str	r0, [r7, #12]
+    if (errorstate != HAL_SD_ERROR_NONE)
+ 800b9fe:	68fb      	ldr	r3, [r7, #12]
+ 800ba00:	2b00      	cmp	r3, #0
+ 800ba02:	d02d      	beq.n	800ba60 <SD_PowerON+0xd8>
+    {
+      return HAL_SD_ERROR_UNSUPPORTED_FEATURE;
+ 800ba04:	f04f 5380 	mov.w	r3, #268435456	; 0x10000000
+ 800ba08:	e046      	b.n	800ba98 <SD_PowerON+0x110>
+  /* SD CARD */
+  /* Send ACMD41 SD_APP_OP_COND with Argument 0x80100000 */
+  while ((count < SDMMC_MAX_VOLT_TRIAL) && (validvoltage == 0U))
+  {
+    /* SEND CMD55 APP_CMD with RCA as 0 */
+    errorstate = SDMMC_CmdAppCommand(hsd->Instance, 0);
+ 800ba0a:	687b      	ldr	r3, [r7, #4]
+ 800ba0c:	681b      	ldr	r3, [r3, #0]
+ 800ba0e:	2100      	movs	r1, #0
+ 800ba10:	4618      	mov	r0, r3
+ 800ba12:	f002 fc7e 	bl	800e312 <SDMMC_CmdAppCommand>
+ 800ba16:	60f8      	str	r0, [r7, #12]
+    if (errorstate != HAL_SD_ERROR_NONE)
+ 800ba18:	68fb      	ldr	r3, [r7, #12]
+ 800ba1a:	2b00      	cmp	r3, #0
+ 800ba1c:	d001      	beq.n	800ba22 <SD_PowerON+0x9a>
+    {
+      return errorstate;
+ 800ba1e:	68fb      	ldr	r3, [r7, #12]
+ 800ba20:	e03a      	b.n	800ba98 <SD_PowerON+0x110>
+    }
+
+    /* Send CMD41 */
+    errorstate = SDMMC_CmdAppOperCommand(hsd->Instance, SDMMC_VOLTAGE_WINDOW_SD | SDMMC_HIGH_CAPACITY |
+ 800ba22:	687b      	ldr	r3, [r7, #4]
+ 800ba24:	681b      	ldr	r3, [r3, #0]
+ 800ba26:	491e      	ldr	r1, [pc, #120]	; (800baa0 <SD_PowerON+0x118>)
+ 800ba28:	4618      	mov	r0, r3
+ 800ba2a:	f002 fc95 	bl	800e358 <SDMMC_CmdAppOperCommand>
+ 800ba2e:	60f8      	str	r0, [r7, #12]
+                                         SD_SWITCH_1_8V_CAPACITY);
+    if (errorstate != HAL_SD_ERROR_NONE)
+ 800ba30:	68fb      	ldr	r3, [r7, #12]
+ 800ba32:	2b00      	cmp	r3, #0
+ 800ba34:	d002      	beq.n	800ba3c <SD_PowerON+0xb4>
+    {
+      return HAL_SD_ERROR_UNSUPPORTED_FEATURE;
+ 800ba36:	f04f 5380 	mov.w	r3, #268435456	; 0x10000000
+ 800ba3a:	e02d      	b.n	800ba98 <SD_PowerON+0x110>
+    }
+
+    /* Get command response */
+    response = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1);
+ 800ba3c:	687b      	ldr	r3, [r7, #4]
+ 800ba3e:	681b      	ldr	r3, [r3, #0]
+ 800ba40:	2100      	movs	r1, #0
+ 800ba42:	4618      	mov	r0, r3
+ 800ba44:	f002 fad9 	bl	800dffa <SDMMC_GetResponse>
+ 800ba48:	6178      	str	r0, [r7, #20]
+
+    /* Get operating voltage*/
+    validvoltage = (((response >> 31U) == 1U) ? 1U : 0U);
+ 800ba4a:	697b      	ldr	r3, [r7, #20]
+ 800ba4c:	0fdb      	lsrs	r3, r3, #31
+ 800ba4e:	2b01      	cmp	r3, #1
+ 800ba50:	d101      	bne.n	800ba56 <SD_PowerON+0xce>
+ 800ba52:	2301      	movs	r3, #1
+ 800ba54:	e000      	b.n	800ba58 <SD_PowerON+0xd0>
+ 800ba56:	2300      	movs	r3, #0
+ 800ba58:	613b      	str	r3, [r7, #16]
+
+    count++;
+ 800ba5a:	68bb      	ldr	r3, [r7, #8]
+ 800ba5c:	3301      	adds	r3, #1
+ 800ba5e:	60bb      	str	r3, [r7, #8]
+  while ((count < SDMMC_MAX_VOLT_TRIAL) && (validvoltage == 0U))
+ 800ba60:	68bb      	ldr	r3, [r7, #8]
+ 800ba62:	f64f 72fe 	movw	r2, #65534	; 0xfffe
+ 800ba66:	4293      	cmp	r3, r2
+ 800ba68:	d802      	bhi.n	800ba70 <SD_PowerON+0xe8>
+ 800ba6a:	693b      	ldr	r3, [r7, #16]
+ 800ba6c:	2b00      	cmp	r3, #0
+ 800ba6e:	d0cc      	beq.n	800ba0a <SD_PowerON+0x82>
+  }
+
+  if (count >= SDMMC_MAX_VOLT_TRIAL)
+ 800ba70:	68bb      	ldr	r3, [r7, #8]
+ 800ba72:	f64f 72fe 	movw	r2, #65534	; 0xfffe
+ 800ba76:	4293      	cmp	r3, r2
+ 800ba78:	d902      	bls.n	800ba80 <SD_PowerON+0xf8>
+  {
+    return HAL_SD_ERROR_INVALID_VOLTRANGE;
+ 800ba7a:	f04f 7380 	mov.w	r3, #16777216	; 0x1000000
+ 800ba7e:	e00b      	b.n	800ba98 <SD_PowerON+0x110>
+  }
+
+  /* Set default card type */
+  hsd->SdCard.CardType = CARD_SDSC;
+ 800ba80:	687b      	ldr	r3, [r7, #4]
+ 800ba82:	2200      	movs	r2, #0
+ 800ba84:	639a      	str	r2, [r3, #56]	; 0x38
+
+  if ((response & SDMMC_HIGH_CAPACITY) == SDMMC_HIGH_CAPACITY)
+ 800ba86:	697b      	ldr	r3, [r7, #20]
+ 800ba88:	f003 4380 	and.w	r3, r3, #1073741824	; 0x40000000
+ 800ba8c:	2b00      	cmp	r3, #0
+ 800ba8e:	d002      	beq.n	800ba96 <SD_PowerON+0x10e>
+  {
+    hsd->SdCard.CardType = CARD_SDHC_SDXC;
+ 800ba90:	687b      	ldr	r3, [r7, #4]
+ 800ba92:	2201      	movs	r2, #1
+ 800ba94:	639a      	str	r2, [r3, #56]	; 0x38
+      }
+    }
+#endif /* USE_SD_TRANSCEIVER  */
+  }
+
+  return HAL_SD_ERROR_NONE;
+ 800ba96:	2300      	movs	r3, #0
+}
+ 800ba98:	4618      	mov	r0, r3
+ 800ba9a:	3718      	adds	r7, #24
+ 800ba9c:	46bd      	mov	sp, r7
+ 800ba9e:	bd80      	pop	{r7, pc}
+ 800baa0:	c1100000 	.word	0xc1100000
+
+0800baa4 <SD_SendSDStatus>:
+  * @param  pSDstatus: Pointer to the buffer that will contain the SD card status
+  *         SD Status register)
+  * @retval error state
+  */
+static uint32_t SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus)
+{
+ 800baa4:	b580      	push	{r7, lr}
+ 800baa6:	b08c      	sub	sp, #48	; 0x30
+ 800baa8:	af00      	add	r7, sp, #0
+ 800baaa:	6078      	str	r0, [r7, #4]
+ 800baac:	6039      	str	r1, [r7, #0]
+  SDMMC_DataInitTypeDef config;
+  uint32_t errorstate;
+  uint32_t tickstart = HAL_GetTick();
+ 800baae:	f7f6 fc59 	bl	8002364 <HAL_GetTick>
+ 800bab2:	6278      	str	r0, [r7, #36]	; 0x24
+  uint32_t count;
+  uint32_t *pData = pSDstatus;
+ 800bab4:	683b      	ldr	r3, [r7, #0]
+ 800bab6:	62bb      	str	r3, [r7, #40]	; 0x28
+
+  /* Check SD response */
+  if ((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)
+ 800bab8:	687b      	ldr	r3, [r7, #4]
+ 800baba:	681b      	ldr	r3, [r3, #0]
+ 800babc:	2100      	movs	r1, #0
+ 800babe:	4618      	mov	r0, r3
+ 800bac0:	f002 fa9b 	bl	800dffa <SDMMC_GetResponse>
+ 800bac4:	4603      	mov	r3, r0
+ 800bac6:	f003 7300 	and.w	r3, r3, #33554432	; 0x2000000
+ 800baca:	f1b3 7f00 	cmp.w	r3, #33554432	; 0x2000000
+ 800bace:	d102      	bne.n	800bad6 <SD_SendSDStatus+0x32>
+  {
+    return HAL_SD_ERROR_LOCK_UNLOCK_FAILED;
+ 800bad0:	f44f 6300 	mov.w	r3, #2048	; 0x800
+ 800bad4:	e0b0      	b.n	800bc38 <SD_SendSDStatus+0x194>
+  }
+
+  /* Set block size for card if it is not equal to current block size for card */
+  errorstate = SDMMC_CmdBlockLength(hsd->Instance, 64U);
+ 800bad6:	687b      	ldr	r3, [r7, #4]
+ 800bad8:	681b      	ldr	r3, [r3, #0]
+ 800bada:	2140      	movs	r1, #64	; 0x40
+ 800badc:	4618      	mov	r0, r3
+ 800bade:	f002 facb 	bl	800e078 <SDMMC_CmdBlockLength>
+ 800bae2:	6238      	str	r0, [r7, #32]
+  if (errorstate != HAL_SD_ERROR_NONE)
+ 800bae4:	6a3b      	ldr	r3, [r7, #32]
+ 800bae6:	2b00      	cmp	r3, #0
+ 800bae8:	d005      	beq.n	800baf6 <SD_SendSDStatus+0x52>
+  {
+    hsd->ErrorCode |= HAL_SD_ERROR_NONE;
+ 800baea:	687b      	ldr	r3, [r7, #4]
+ 800baec:	6b5a      	ldr	r2, [r3, #52]	; 0x34
+ 800baee:	687b      	ldr	r3, [r7, #4]
+ 800baf0:	635a      	str	r2, [r3, #52]	; 0x34
+    return errorstate;
+ 800baf2:	6a3b      	ldr	r3, [r7, #32]
+ 800baf4:	e0a0      	b.n	800bc38 <SD_SendSDStatus+0x194>
+  }
+
+  /* Send CMD55 */
+  errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U));
+ 800baf6:	687b      	ldr	r3, [r7, #4]
+ 800baf8:	681a      	ldr	r2, [r3, #0]
+ 800bafa:	687b      	ldr	r3, [r7, #4]
+ 800bafc:	6c5b      	ldr	r3, [r3, #68]	; 0x44
+ 800bafe:	041b      	lsls	r3, r3, #16
+ 800bb00:	4619      	mov	r1, r3
+ 800bb02:	4610      	mov	r0, r2
+ 800bb04:	f002 fc05 	bl	800e312 <SDMMC_CmdAppCommand>
+ 800bb08:	6238      	str	r0, [r7, #32]
+  if (errorstate != HAL_SD_ERROR_NONE)
+ 800bb0a:	6a3b      	ldr	r3, [r7, #32]
+ 800bb0c:	2b00      	cmp	r3, #0
+ 800bb0e:	d005      	beq.n	800bb1c <SD_SendSDStatus+0x78>
+  {
+    hsd->ErrorCode |= HAL_SD_ERROR_NONE;
+ 800bb10:	687b      	ldr	r3, [r7, #4]
+ 800bb12:	6b5a      	ldr	r2, [r3, #52]	; 0x34
+ 800bb14:	687b      	ldr	r3, [r7, #4]
+ 800bb16:	635a      	str	r2, [r3, #52]	; 0x34
+    return errorstate;
+ 800bb18:	6a3b      	ldr	r3, [r7, #32]
+ 800bb1a:	e08d      	b.n	800bc38 <SD_SendSDStatus+0x194>
+  }
+
+  /* Configure the SD DPSM (Data Path State Machine) */
+  config.DataTimeOut   = SDMMC_DATATIMEOUT;
+ 800bb1c:	f04f 33ff 	mov.w	r3, #4294967295
+ 800bb20:	60bb      	str	r3, [r7, #8]
+  config.DataLength    = 64U;
+ 800bb22:	2340      	movs	r3, #64	; 0x40
+ 800bb24:	60fb      	str	r3, [r7, #12]
+  config.DataBlockSize = SDMMC_DATABLOCK_SIZE_64B;
+ 800bb26:	2360      	movs	r3, #96	; 0x60
+ 800bb28:	613b      	str	r3, [r7, #16]
+  config.TransferDir   = SDMMC_TRANSFER_DIR_TO_SDMMC;
+ 800bb2a:	2302      	movs	r3, #2
+ 800bb2c:	617b      	str	r3, [r7, #20]
+  config.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
+ 800bb2e:	2300      	movs	r3, #0
+ 800bb30:	61bb      	str	r3, [r7, #24]
+  config.DPSM          = SDMMC_DPSM_ENABLE;
+ 800bb32:	2301      	movs	r3, #1
+ 800bb34:	61fb      	str	r3, [r7, #28]
+  (void)SDMMC_ConfigData(hsd->Instance, &config);
+ 800bb36:	687b      	ldr	r3, [r7, #4]
+ 800bb38:	681b      	ldr	r3, [r3, #0]
+ 800bb3a:	f107 0208 	add.w	r2, r7, #8
+ 800bb3e:	4611      	mov	r1, r2
+ 800bb40:	4618      	mov	r0, r3
+ 800bb42:	f002 fa6d 	bl	800e020 <SDMMC_ConfigData>
+
+  /* Send ACMD13 (SD_APP_STAUS)  with argument as card's RCA */
+  errorstate = SDMMC_CmdStatusRegister(hsd->Instance);
+ 800bb46:	687b      	ldr	r3, [r7, #4]
+ 800bb48:	681b      	ldr	r3, [r3, #0]
+ 800bb4a:	4618      	mov	r0, r3
+ 800bb4c:	f002 fced 	bl	800e52a <SDMMC_CmdStatusRegister>
+ 800bb50:	6238      	str	r0, [r7, #32]
+  if (errorstate != HAL_SD_ERROR_NONE)
+ 800bb52:	6a3b      	ldr	r3, [r7, #32]
+ 800bb54:	2b00      	cmp	r3, #0
+ 800bb56:	d02b      	beq.n	800bbb0 <SD_SendSDStatus+0x10c>
+  {
+    hsd->ErrorCode |= HAL_SD_ERROR_NONE;
+ 800bb58:	687b      	ldr	r3, [r7, #4]
+ 800bb5a:	6b5a      	ldr	r2, [r3, #52]	; 0x34
+ 800bb5c:	687b      	ldr	r3, [r7, #4]
+ 800bb5e:	635a      	str	r2, [r3, #52]	; 0x34
+    return errorstate;
+ 800bb60:	6a3b      	ldr	r3, [r7, #32]
+ 800bb62:	e069      	b.n	800bc38 <SD_SendSDStatus+0x194>
+  }
+
+  /* Get status data */
+  while (!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND))
+  {
+    if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF))
+ 800bb64:	687b      	ldr	r3, [r7, #4]
+ 800bb66:	681b      	ldr	r3, [r3, #0]
+ 800bb68:	6b5b      	ldr	r3, [r3, #52]	; 0x34
+ 800bb6a:	f403 4300 	and.w	r3, r3, #32768	; 0x8000
+ 800bb6e:	2b00      	cmp	r3, #0
+ 800bb70:	d013      	beq.n	800bb9a <SD_SendSDStatus+0xf6>
+    {
+      for (count = 0U; count < 8U; count++)
+ 800bb72:	2300      	movs	r3, #0
+ 800bb74:	62fb      	str	r3, [r7, #44]	; 0x2c
+ 800bb76:	e00d      	b.n	800bb94 <SD_SendSDStatus+0xf0>
+      {
+        *pData = SDMMC_ReadFIFO(hsd->Instance);
+ 800bb78:	687b      	ldr	r3, [r7, #4]
+ 800bb7a:	681b      	ldr	r3, [r3, #0]
+ 800bb7c:	4618      	mov	r0, r3
+ 800bb7e:	f002 f9c7 	bl	800df10 <SDMMC_ReadFIFO>
+ 800bb82:	4602      	mov	r2, r0
+ 800bb84:	6abb      	ldr	r3, [r7, #40]	; 0x28
+ 800bb86:	601a      	str	r2, [r3, #0]
+        pData++;
+ 800bb88:	6abb      	ldr	r3, [r7, #40]	; 0x28
+ 800bb8a:	3304      	adds	r3, #4
+ 800bb8c:	62bb      	str	r3, [r7, #40]	; 0x28
+      for (count = 0U; count < 8U; count++)
+ 800bb8e:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 800bb90:	3301      	adds	r3, #1
+ 800bb92:	62fb      	str	r3, [r7, #44]	; 0x2c
+ 800bb94:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 800bb96:	2b07      	cmp	r3, #7
+ 800bb98:	d9ee      	bls.n	800bb78 <SD_SendSDStatus+0xd4>
+      }
+    }
+
+    if ((HAL_GetTick() - tickstart) >=  SDMMC_DATATIMEOUT)
+ 800bb9a:	f7f6 fbe3 	bl	8002364 <HAL_GetTick>
+ 800bb9e:	4602      	mov	r2, r0
+ 800bba0:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 800bba2:	1ad3      	subs	r3, r2, r3
+ 800bba4:	f1b3 3fff 	cmp.w	r3, #4294967295
+ 800bba8:	d102      	bne.n	800bbb0 <SD_SendSDStatus+0x10c>
+    {
+      return HAL_SD_ERROR_TIMEOUT;
+ 800bbaa:	f04f 4300 	mov.w	r3, #2147483648	; 0x80000000
+ 800bbae:	e043      	b.n	800bc38 <SD_SendSDStatus+0x194>
+  while (!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND))
+ 800bbb0:	687b      	ldr	r3, [r7, #4]
+ 800bbb2:	681b      	ldr	r3, [r3, #0]
+ 800bbb4:	6b5b      	ldr	r3, [r3, #52]	; 0x34
+ 800bbb6:	f403 7395 	and.w	r3, r3, #298	; 0x12a
+ 800bbba:	2b00      	cmp	r3, #0
+ 800bbbc:	d0d2      	beq.n	800bb64 <SD_SendSDStatus+0xc0>
+    }
+  }
+
+  if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT))
+ 800bbbe:	687b      	ldr	r3, [r7, #4]
+ 800bbc0:	681b      	ldr	r3, [r3, #0]
+ 800bbc2:	6b5b      	ldr	r3, [r3, #52]	; 0x34
+ 800bbc4:	f003 0308 	and.w	r3, r3, #8
+ 800bbc8:	2b00      	cmp	r3, #0
+ 800bbca:	d001      	beq.n	800bbd0 <SD_SendSDStatus+0x12c>
+  {
+    return HAL_SD_ERROR_DATA_TIMEOUT;
+ 800bbcc:	2308      	movs	r3, #8
+ 800bbce:	e033      	b.n	800bc38 <SD_SendSDStatus+0x194>
+  }
+  else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL))
+ 800bbd0:	687b      	ldr	r3, [r7, #4]
+ 800bbd2:	681b      	ldr	r3, [r3, #0]
+ 800bbd4:	6b5b      	ldr	r3, [r3, #52]	; 0x34
+ 800bbd6:	f003 0302 	and.w	r3, r3, #2
+ 800bbda:	2b00      	cmp	r3, #0
+ 800bbdc:	d001      	beq.n	800bbe2 <SD_SendSDStatus+0x13e>
+  {
+    return HAL_SD_ERROR_DATA_CRC_FAIL;
+ 800bbde:	2302      	movs	r3, #2
+ 800bbe0:	e02a      	b.n	800bc38 <SD_SendSDStatus+0x194>
+  }
+  else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR))
+ 800bbe2:	687b      	ldr	r3, [r7, #4]
+ 800bbe4:	681b      	ldr	r3, [r3, #0]
+ 800bbe6:	6b5b      	ldr	r3, [r3, #52]	; 0x34
+ 800bbe8:	f003 0320 	and.w	r3, r3, #32
+ 800bbec:	2b00      	cmp	r3, #0
+ 800bbee:	d017      	beq.n	800bc20 <SD_SendSDStatus+0x17c>
+  {
+    return HAL_SD_ERROR_RX_OVERRUN;
+ 800bbf0:	2320      	movs	r3, #32
+ 800bbf2:	e021      	b.n	800bc38 <SD_SendSDStatus+0x194>
+    /* Nothing to do */
+  }
+
+  while ((__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DPSMACT)))
+  {
+    *pData = SDMMC_ReadFIFO(hsd->Instance);
+ 800bbf4:	687b      	ldr	r3, [r7, #4]
+ 800bbf6:	681b      	ldr	r3, [r3, #0]
+ 800bbf8:	4618      	mov	r0, r3
+ 800bbfa:	f002 f989 	bl	800df10 <SDMMC_ReadFIFO>
+ 800bbfe:	4602      	mov	r2, r0
+ 800bc00:	6abb      	ldr	r3, [r7, #40]	; 0x28
+ 800bc02:	601a      	str	r2, [r3, #0]
+    pData++;
+ 800bc04:	6abb      	ldr	r3, [r7, #40]	; 0x28
+ 800bc06:	3304      	adds	r3, #4
+ 800bc08:	62bb      	str	r3, [r7, #40]	; 0x28
+
+    if ((HAL_GetTick() - tickstart) >=  SDMMC_DATATIMEOUT)
+ 800bc0a:	f7f6 fbab 	bl	8002364 <HAL_GetTick>
+ 800bc0e:	4602      	mov	r2, r0
+ 800bc10:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 800bc12:	1ad3      	subs	r3, r2, r3
+ 800bc14:	f1b3 3fff 	cmp.w	r3, #4294967295
+ 800bc18:	d102      	bne.n	800bc20 <SD_SendSDStatus+0x17c>
+    {
+      return HAL_SD_ERROR_TIMEOUT;
+ 800bc1a:	f04f 4300 	mov.w	r3, #2147483648	; 0x80000000
+ 800bc1e:	e00b      	b.n	800bc38 <SD_SendSDStatus+0x194>
+  while ((__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DPSMACT)))
+ 800bc20:	687b      	ldr	r3, [r7, #4]
+ 800bc22:	681b      	ldr	r3, [r3, #0]
+ 800bc24:	6b5b      	ldr	r3, [r3, #52]	; 0x34
+ 800bc26:	f403 5380 	and.w	r3, r3, #4096	; 0x1000
+ 800bc2a:	2b00      	cmp	r3, #0
+ 800bc2c:	d1e2      	bne.n	800bbf4 <SD_SendSDStatus+0x150>
+    }
+  }
+
+  /* Clear all the static status flags*/
+  __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS);
+ 800bc2e:	687b      	ldr	r3, [r7, #4]
+ 800bc30:	681b      	ldr	r3, [r3, #0]
+ 800bc32:	4a03      	ldr	r2, [pc, #12]	; (800bc40 <SD_SendSDStatus+0x19c>)
+ 800bc34:	639a      	str	r2, [r3, #56]	; 0x38
+
+  return HAL_SD_ERROR_NONE;
+ 800bc36:	2300      	movs	r3, #0
+}
+ 800bc38:	4618      	mov	r0, r3
+ 800bc3a:	3730      	adds	r7, #48	; 0x30
+ 800bc3c:	46bd      	mov	sp, r7
+ 800bc3e:	bd80      	pop	{r7, pc}
+ 800bc40:	18000f3a 	.word	0x18000f3a
+
+0800bc44 <SD_SendStatus>:
+  * @param  pCardStatus: pointer to the buffer that will contain the SD card
+  *         status (Card Status register)
+  * @retval error state
+  */
+static uint32_t SD_SendStatus(SD_HandleTypeDef *hsd, uint32_t *pCardStatus)
+{
+ 800bc44:	b580      	push	{r7, lr}
+ 800bc46:	b084      	sub	sp, #16
+ 800bc48:	af00      	add	r7, sp, #0
+ 800bc4a:	6078      	str	r0, [r7, #4]
+ 800bc4c:	6039      	str	r1, [r7, #0]
+  uint32_t errorstate;
+
+  if (pCardStatus == NULL)
+ 800bc4e:	683b      	ldr	r3, [r7, #0]
+ 800bc50:	2b00      	cmp	r3, #0
+ 800bc52:	d102      	bne.n	800bc5a <SD_SendStatus+0x16>
+  {
+    return HAL_SD_ERROR_PARAM;
+ 800bc54:	f04f 6300 	mov.w	r3, #134217728	; 0x8000000
+ 800bc58:	e018      	b.n	800bc8c <SD_SendStatus+0x48>
+  }
+
+  /* Send Status command */
+  errorstate = SDMMC_CmdSendStatus(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U));
+ 800bc5a:	687b      	ldr	r3, [r7, #4]
+ 800bc5c:	681a      	ldr	r2, [r3, #0]
+ 800bc5e:	687b      	ldr	r3, [r7, #4]
+ 800bc60:	6c5b      	ldr	r3, [r3, #68]	; 0x44
+ 800bc62:	041b      	lsls	r3, r3, #16
+ 800bc64:	4619      	mov	r1, r3
+ 800bc66:	4610      	mov	r0, r2
+ 800bc68:	f002 fc3c 	bl	800e4e4 <SDMMC_CmdSendStatus>
+ 800bc6c:	60f8      	str	r0, [r7, #12]
+  if (errorstate != HAL_SD_ERROR_NONE)
+ 800bc6e:	68fb      	ldr	r3, [r7, #12]
+ 800bc70:	2b00      	cmp	r3, #0
+ 800bc72:	d001      	beq.n	800bc78 <SD_SendStatus+0x34>
+  {
+    return errorstate;
+ 800bc74:	68fb      	ldr	r3, [r7, #12]
+ 800bc76:	e009      	b.n	800bc8c <SD_SendStatus+0x48>
+  }
+
+  /* Get SD card status */
+  *pCardStatus = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1);
+ 800bc78:	687b      	ldr	r3, [r7, #4]
+ 800bc7a:	681b      	ldr	r3, [r3, #0]
+ 800bc7c:	2100      	movs	r1, #0
+ 800bc7e:	4618      	mov	r0, r3
+ 800bc80:	f002 f9bb 	bl	800dffa <SDMMC_GetResponse>
+ 800bc84:	4602      	mov	r2, r0
+ 800bc86:	683b      	ldr	r3, [r7, #0]
+ 800bc88:	601a      	str	r2, [r3, #0]
+
+  return HAL_SD_ERROR_NONE;
+ 800bc8a:	2300      	movs	r3, #0
+}
+ 800bc8c:	4618      	mov	r0, r3
+ 800bc8e:	3710      	adds	r7, #16
+ 800bc90:	46bd      	mov	sp, r7
+ 800bc92:	bd80      	pop	{r7, pc}
+
+0800bc94 <SD_WideBus_Enable>:
+  * @brief  Enables the SDMMC wide bus mode.
+  * @param  hsd: pointer to SD handle
+  * @retval error state
+  */
+static uint32_t SD_WideBus_Enable(SD_HandleTypeDef *hsd)
+{
+ 800bc94:	b580      	push	{r7, lr}
+ 800bc96:	b086      	sub	sp, #24
+ 800bc98:	af00      	add	r7, sp, #0
+ 800bc9a:	6078      	str	r0, [r7, #4]
+  uint32_t scr[2U] = {0UL, 0UL};
+ 800bc9c:	2300      	movs	r3, #0
+ 800bc9e:	60fb      	str	r3, [r7, #12]
+ 800bca0:	2300      	movs	r3, #0
+ 800bca2:	613b      	str	r3, [r7, #16]
+  uint32_t errorstate;
+
+  if ((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)
+ 800bca4:	687b      	ldr	r3, [r7, #4]
+ 800bca6:	681b      	ldr	r3, [r3, #0]
+ 800bca8:	2100      	movs	r1, #0
+ 800bcaa:	4618      	mov	r0, r3
+ 800bcac:	f002 f9a5 	bl	800dffa <SDMMC_GetResponse>
+ 800bcb0:	4603      	mov	r3, r0
+ 800bcb2:	f003 7300 	and.w	r3, r3, #33554432	; 0x2000000
+ 800bcb6:	f1b3 7f00 	cmp.w	r3, #33554432	; 0x2000000
+ 800bcba:	d102      	bne.n	800bcc2 <SD_WideBus_Enable+0x2e>
+  {
+    return HAL_SD_ERROR_LOCK_UNLOCK_FAILED;
+ 800bcbc:	f44f 6300 	mov.w	r3, #2048	; 0x800
+ 800bcc0:	e02f      	b.n	800bd22 <SD_WideBus_Enable+0x8e>
+  }
+
+  /* Get SCR Register */
+  errorstate = SD_FindSCR(hsd, scr);
+ 800bcc2:	f107 030c 	add.w	r3, r7, #12
+ 800bcc6:	4619      	mov	r1, r3
+ 800bcc8:	6878      	ldr	r0, [r7, #4]
+ 800bcca:	f000 f879 	bl	800bdc0 <SD_FindSCR>
+ 800bcce:	6178      	str	r0, [r7, #20]
+  if (errorstate != HAL_SD_ERROR_NONE)
+ 800bcd0:	697b      	ldr	r3, [r7, #20]
+ 800bcd2:	2b00      	cmp	r3, #0
+ 800bcd4:	d001      	beq.n	800bcda <SD_WideBus_Enable+0x46>
+  {
+    return errorstate;
+ 800bcd6:	697b      	ldr	r3, [r7, #20]
+ 800bcd8:	e023      	b.n	800bd22 <SD_WideBus_Enable+0x8e>
+  }
+
+  /* If requested card supports wide bus operation */
+  if ((scr[1U] & SDMMC_WIDE_BUS_SUPPORT) != SDMMC_ALLZERO)
+ 800bcda:	693b      	ldr	r3, [r7, #16]
+ 800bcdc:	f403 2380 	and.w	r3, r3, #262144	; 0x40000
+ 800bce0:	2b00      	cmp	r3, #0
+ 800bce2:	d01c      	beq.n	800bd1e <SD_WideBus_Enable+0x8a>
+  {
+    /* Send CMD55 APP_CMD with argument as card's RCA.*/
+    errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U));
+ 800bce4:	687b      	ldr	r3, [r7, #4]
+ 800bce6:	681a      	ldr	r2, [r3, #0]
+ 800bce8:	687b      	ldr	r3, [r7, #4]
+ 800bcea:	6c5b      	ldr	r3, [r3, #68]	; 0x44
+ 800bcec:	041b      	lsls	r3, r3, #16
+ 800bcee:	4619      	mov	r1, r3
+ 800bcf0:	4610      	mov	r0, r2
+ 800bcf2:	f002 fb0e 	bl	800e312 <SDMMC_CmdAppCommand>
+ 800bcf6:	6178      	str	r0, [r7, #20]
+    if (errorstate != HAL_SD_ERROR_NONE)
+ 800bcf8:	697b      	ldr	r3, [r7, #20]
+ 800bcfa:	2b00      	cmp	r3, #0
+ 800bcfc:	d001      	beq.n	800bd02 <SD_WideBus_Enable+0x6e>
+    {
+      return errorstate;
+ 800bcfe:	697b      	ldr	r3, [r7, #20]
+ 800bd00:	e00f      	b.n	800bd22 <SD_WideBus_Enable+0x8e>
+    }
+
+    /* Send ACMD6 APP_CMD with argument as 2 for wide bus mode */
+    errorstate = SDMMC_CmdBusWidth(hsd->Instance, 2U);
+ 800bd02:	687b      	ldr	r3, [r7, #4]
+ 800bd04:	681b      	ldr	r3, [r3, #0]
+ 800bd06:	2102      	movs	r1, #2
+ 800bd08:	4618      	mov	r0, r3
+ 800bd0a:	f002 fb45 	bl	800e398 <SDMMC_CmdBusWidth>
+ 800bd0e:	6178      	str	r0, [r7, #20]
+    if (errorstate != HAL_SD_ERROR_NONE)
+ 800bd10:	697b      	ldr	r3, [r7, #20]
+ 800bd12:	2b00      	cmp	r3, #0
+ 800bd14:	d001      	beq.n	800bd1a <SD_WideBus_Enable+0x86>
+    {
+      return errorstate;
+ 800bd16:	697b      	ldr	r3, [r7, #20]
+ 800bd18:	e003      	b.n	800bd22 <SD_WideBus_Enable+0x8e>
+    }
+
+    return HAL_SD_ERROR_NONE;
+ 800bd1a:	2300      	movs	r3, #0
+ 800bd1c:	e001      	b.n	800bd22 <SD_WideBus_Enable+0x8e>
+  }
+  else
+  {
+    return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE;
+ 800bd1e:	f04f 6380 	mov.w	r3, #67108864	; 0x4000000
+  }
+}
+ 800bd22:	4618      	mov	r0, r3
+ 800bd24:	3718      	adds	r7, #24
+ 800bd26:	46bd      	mov	sp, r7
+ 800bd28:	bd80      	pop	{r7, pc}
+
+0800bd2a <SD_WideBus_Disable>:
+  * @brief  Disables the SDMMC wide bus mode.
+  * @param  hsd: Pointer to SD handle
+  * @retval error state
+  */
+static uint32_t SD_WideBus_Disable(SD_HandleTypeDef *hsd)
+{
+ 800bd2a:	b580      	push	{r7, lr}
+ 800bd2c:	b086      	sub	sp, #24
+ 800bd2e:	af00      	add	r7, sp, #0
+ 800bd30:	6078      	str	r0, [r7, #4]
+  uint32_t scr[2U] = {0UL, 0UL};
+ 800bd32:	2300      	movs	r3, #0
+ 800bd34:	60fb      	str	r3, [r7, #12]
+ 800bd36:	2300      	movs	r3, #0
+ 800bd38:	613b      	str	r3, [r7, #16]
+  uint32_t errorstate;
+
+  if ((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)
+ 800bd3a:	687b      	ldr	r3, [r7, #4]
+ 800bd3c:	681b      	ldr	r3, [r3, #0]
+ 800bd3e:	2100      	movs	r1, #0
+ 800bd40:	4618      	mov	r0, r3
+ 800bd42:	f002 f95a 	bl	800dffa <SDMMC_GetResponse>
+ 800bd46:	4603      	mov	r3, r0
+ 800bd48:	f003 7300 	and.w	r3, r3, #33554432	; 0x2000000
+ 800bd4c:	f1b3 7f00 	cmp.w	r3, #33554432	; 0x2000000
+ 800bd50:	d102      	bne.n	800bd58 <SD_WideBus_Disable+0x2e>
+  {
+    return HAL_SD_ERROR_LOCK_UNLOCK_FAILED;
+ 800bd52:	f44f 6300 	mov.w	r3, #2048	; 0x800
+ 800bd56:	e02f      	b.n	800bdb8 <SD_WideBus_Disable+0x8e>
+  }
+
+  /* Get SCR Register */
+  errorstate = SD_FindSCR(hsd, scr);
+ 800bd58:	f107 030c 	add.w	r3, r7, #12
+ 800bd5c:	4619      	mov	r1, r3
+ 800bd5e:	6878      	ldr	r0, [r7, #4]
+ 800bd60:	f000 f82e 	bl	800bdc0 <SD_FindSCR>
+ 800bd64:	6178      	str	r0, [r7, #20]
+  if (errorstate != HAL_SD_ERROR_NONE)
+ 800bd66:	697b      	ldr	r3, [r7, #20]
+ 800bd68:	2b00      	cmp	r3, #0
+ 800bd6a:	d001      	beq.n	800bd70 <SD_WideBus_Disable+0x46>
+  {
+    return errorstate;
+ 800bd6c:	697b      	ldr	r3, [r7, #20]
+ 800bd6e:	e023      	b.n	800bdb8 <SD_WideBus_Disable+0x8e>
+  }
+
+  /* If requested card supports 1 bit mode operation */
+  if ((scr[1U] & SDMMC_SINGLE_BUS_SUPPORT) != SDMMC_ALLZERO)
+ 800bd70:	693b      	ldr	r3, [r7, #16]
+ 800bd72:	f403 3380 	and.w	r3, r3, #65536	; 0x10000
+ 800bd76:	2b00      	cmp	r3, #0
+ 800bd78:	d01c      	beq.n	800bdb4 <SD_WideBus_Disable+0x8a>
+  {
+    /* Send CMD55 APP_CMD with argument as card's RCA */
+    errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U));
+ 800bd7a:	687b      	ldr	r3, [r7, #4]
+ 800bd7c:	681a      	ldr	r2, [r3, #0]
+ 800bd7e:	687b      	ldr	r3, [r7, #4]
+ 800bd80:	6c5b      	ldr	r3, [r3, #68]	; 0x44
+ 800bd82:	041b      	lsls	r3, r3, #16
+ 800bd84:	4619      	mov	r1, r3
+ 800bd86:	4610      	mov	r0, r2
+ 800bd88:	f002 fac3 	bl	800e312 <SDMMC_CmdAppCommand>
+ 800bd8c:	6178      	str	r0, [r7, #20]
+    if (errorstate != HAL_SD_ERROR_NONE)
+ 800bd8e:	697b      	ldr	r3, [r7, #20]
+ 800bd90:	2b00      	cmp	r3, #0
+ 800bd92:	d001      	beq.n	800bd98 <SD_WideBus_Disable+0x6e>
+    {
+      return errorstate;
+ 800bd94:	697b      	ldr	r3, [r7, #20]
+ 800bd96:	e00f      	b.n	800bdb8 <SD_WideBus_Disable+0x8e>
+    }
+
+    /* Send ACMD6 APP_CMD with argument as 0 for single bus mode */
+    errorstate = SDMMC_CmdBusWidth(hsd->Instance, 0U);
+ 800bd98:	687b      	ldr	r3, [r7, #4]
+ 800bd9a:	681b      	ldr	r3, [r3, #0]
+ 800bd9c:	2100      	movs	r1, #0
+ 800bd9e:	4618      	mov	r0, r3
+ 800bda0:	f002 fafa 	bl	800e398 <SDMMC_CmdBusWidth>
+ 800bda4:	6178      	str	r0, [r7, #20]
+    if (errorstate != HAL_SD_ERROR_NONE)
+ 800bda6:	697b      	ldr	r3, [r7, #20]
+ 800bda8:	2b00      	cmp	r3, #0
+ 800bdaa:	d001      	beq.n	800bdb0 <SD_WideBus_Disable+0x86>
+    {
+      return errorstate;
+ 800bdac:	697b      	ldr	r3, [r7, #20]
+ 800bdae:	e003      	b.n	800bdb8 <SD_WideBus_Disable+0x8e>
+    }
+
+    return HAL_SD_ERROR_NONE;
+ 800bdb0:	2300      	movs	r3, #0
+ 800bdb2:	e001      	b.n	800bdb8 <SD_WideBus_Disable+0x8e>
+  }
+  else
+  {
+    return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE;
+ 800bdb4:	f04f 6380 	mov.w	r3, #67108864	; 0x4000000
+  }
+}
+ 800bdb8:	4618      	mov	r0, r3
+ 800bdba:	3718      	adds	r7, #24
+ 800bdbc:	46bd      	mov	sp, r7
+ 800bdbe:	bd80      	pop	{r7, pc}
+
+0800bdc0 <SD_FindSCR>:
+  * @param  hsd: Pointer to SD handle
+  * @param  pSCR: pointer to the buffer that will contain the SCR value
+  * @retval error state
+  */
+static uint32_t SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR)
+{
+ 800bdc0:	b580      	push	{r7, lr}
+ 800bdc2:	b08e      	sub	sp, #56	; 0x38
+ 800bdc4:	af00      	add	r7, sp, #0
+ 800bdc6:	6078      	str	r0, [r7, #4]
+ 800bdc8:	6039      	str	r1, [r7, #0]
+  SDMMC_DataInitTypeDef config;
+  uint32_t errorstate;
+  uint32_t tickstart = HAL_GetTick();
+ 800bdca:	f7f6 facb 	bl	8002364 <HAL_GetTick>
+ 800bdce:	6338      	str	r0, [r7, #48]	; 0x30
+  uint32_t index = 0U;
+ 800bdd0:	2300      	movs	r3, #0
+ 800bdd2:	637b      	str	r3, [r7, #52]	; 0x34
+  uint32_t tempscr[2U] = {0UL, 0UL};
+ 800bdd4:	2300      	movs	r3, #0
+ 800bdd6:	60bb      	str	r3, [r7, #8]
+ 800bdd8:	2300      	movs	r3, #0
+ 800bdda:	60fb      	str	r3, [r7, #12]
+  uint32_t *scr = pSCR;
+ 800bddc:	683b      	ldr	r3, [r7, #0]
+ 800bdde:	62fb      	str	r3, [r7, #44]	; 0x2c
+
+  /* Set Block Size To 8 Bytes */
+  errorstate = SDMMC_CmdBlockLength(hsd->Instance, 8U);
+ 800bde0:	687b      	ldr	r3, [r7, #4]
+ 800bde2:	681b      	ldr	r3, [r3, #0]
+ 800bde4:	2108      	movs	r1, #8
+ 800bde6:	4618      	mov	r0, r3
+ 800bde8:	f002 f946 	bl	800e078 <SDMMC_CmdBlockLength>
+ 800bdec:	62b8      	str	r0, [r7, #40]	; 0x28
+  if (errorstate != HAL_SD_ERROR_NONE)
+ 800bdee:	6abb      	ldr	r3, [r7, #40]	; 0x28
+ 800bdf0:	2b00      	cmp	r3, #0
+ 800bdf2:	d001      	beq.n	800bdf8 <SD_FindSCR+0x38>
+  {
+    return errorstate;
+ 800bdf4:	6abb      	ldr	r3, [r7, #40]	; 0x28
+ 800bdf6:	e0ad      	b.n	800bf54 <SD_FindSCR+0x194>
+  }
+
+  /* Send CMD55 APP_CMD with argument as card's RCA */
+  errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)((hsd->SdCard.RelCardAdd) << 16U));
+ 800bdf8:	687b      	ldr	r3, [r7, #4]
+ 800bdfa:	681a      	ldr	r2, [r3, #0]
+ 800bdfc:	687b      	ldr	r3, [r7, #4]
+ 800bdfe:	6c5b      	ldr	r3, [r3, #68]	; 0x44
+ 800be00:	041b      	lsls	r3, r3, #16
+ 800be02:	4619      	mov	r1, r3
+ 800be04:	4610      	mov	r0, r2
+ 800be06:	f002 fa84 	bl	800e312 <SDMMC_CmdAppCommand>
+ 800be0a:	62b8      	str	r0, [r7, #40]	; 0x28
+  if (errorstate != HAL_SD_ERROR_NONE)
+ 800be0c:	6abb      	ldr	r3, [r7, #40]	; 0x28
+ 800be0e:	2b00      	cmp	r3, #0
+ 800be10:	d001      	beq.n	800be16 <SD_FindSCR+0x56>
+  {
+    return errorstate;
+ 800be12:	6abb      	ldr	r3, [r7, #40]	; 0x28
+ 800be14:	e09e      	b.n	800bf54 <SD_FindSCR+0x194>
+  }
+
+  config.DataTimeOut   = SDMMC_DATATIMEOUT;
+ 800be16:	f04f 33ff 	mov.w	r3, #4294967295
+ 800be1a:	613b      	str	r3, [r7, #16]
+  config.DataLength    = 8U;
+ 800be1c:	2308      	movs	r3, #8
+ 800be1e:	617b      	str	r3, [r7, #20]
+  config.DataBlockSize = SDMMC_DATABLOCK_SIZE_8B;
+ 800be20:	2330      	movs	r3, #48	; 0x30
+ 800be22:	61bb      	str	r3, [r7, #24]
+  config.TransferDir   = SDMMC_TRANSFER_DIR_TO_SDMMC;
+ 800be24:	2302      	movs	r3, #2
+ 800be26:	61fb      	str	r3, [r7, #28]
+  config.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
+ 800be28:	2300      	movs	r3, #0
+ 800be2a:	623b      	str	r3, [r7, #32]
+  config.DPSM          = SDMMC_DPSM_ENABLE;
+ 800be2c:	2301      	movs	r3, #1
+ 800be2e:	627b      	str	r3, [r7, #36]	; 0x24
+  (void)SDMMC_ConfigData(hsd->Instance, &config);
+ 800be30:	687b      	ldr	r3, [r7, #4]
+ 800be32:	681b      	ldr	r3, [r3, #0]
+ 800be34:	f107 0210 	add.w	r2, r7, #16
+ 800be38:	4611      	mov	r1, r2
+ 800be3a:	4618      	mov	r0, r3
+ 800be3c:	f002 f8f0 	bl	800e020 <SDMMC_ConfigData>
+
+  /* Send ACMD51 SD_APP_SEND_SCR with argument as 0 */
+  errorstate = SDMMC_CmdSendSCR(hsd->Instance);
+ 800be40:	687b      	ldr	r3, [r7, #4]
+ 800be42:	681b      	ldr	r3, [r3, #0]
+ 800be44:	4618      	mov	r0, r3
+ 800be46:	f002 faca 	bl	800e3de <SDMMC_CmdSendSCR>
+ 800be4a:	62b8      	str	r0, [r7, #40]	; 0x28
+  if (errorstate != HAL_SD_ERROR_NONE)
+ 800be4c:	6abb      	ldr	r3, [r7, #40]	; 0x28
+ 800be4e:	2b00      	cmp	r3, #0
+ 800be50:	d027      	beq.n	800bea2 <SD_FindSCR+0xe2>
+  {
+    return errorstate;
+ 800be52:	6abb      	ldr	r3, [r7, #40]	; 0x28
+ 800be54:	e07e      	b.n	800bf54 <SD_FindSCR+0x194>
+  }
+
+  while (!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND |
+                            SDMMC_FLAG_DATAEND))
+  {
+    if ((!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOE)) && (index == 0U))
+ 800be56:	687b      	ldr	r3, [r7, #4]
+ 800be58:	681b      	ldr	r3, [r3, #0]
+ 800be5a:	6b5b      	ldr	r3, [r3, #52]	; 0x34
+ 800be5c:	f403 2300 	and.w	r3, r3, #524288	; 0x80000
+ 800be60:	2b00      	cmp	r3, #0
+ 800be62:	d113      	bne.n	800be8c <SD_FindSCR+0xcc>
+ 800be64:	6b7b      	ldr	r3, [r7, #52]	; 0x34
+ 800be66:	2b00      	cmp	r3, #0
+ 800be68:	d110      	bne.n	800be8c <SD_FindSCR+0xcc>
+    {
+      tempscr[0] = SDMMC_ReadFIFO(hsd->Instance);
+ 800be6a:	687b      	ldr	r3, [r7, #4]
+ 800be6c:	681b      	ldr	r3, [r3, #0]
+ 800be6e:	4618      	mov	r0, r3
+ 800be70:	f002 f84e 	bl	800df10 <SDMMC_ReadFIFO>
+ 800be74:	4603      	mov	r3, r0
+ 800be76:	60bb      	str	r3, [r7, #8]
+      tempscr[1] = SDMMC_ReadFIFO(hsd->Instance);
+ 800be78:	687b      	ldr	r3, [r7, #4]
+ 800be7a:	681b      	ldr	r3, [r3, #0]
+ 800be7c:	4618      	mov	r0, r3
+ 800be7e:	f002 f847 	bl	800df10 <SDMMC_ReadFIFO>
+ 800be82:	4603      	mov	r3, r0
+ 800be84:	60fb      	str	r3, [r7, #12]
+      index++;
+ 800be86:	6b7b      	ldr	r3, [r7, #52]	; 0x34
+ 800be88:	3301      	adds	r3, #1
+ 800be8a:	637b      	str	r3, [r7, #52]	; 0x34
+    }
+
+
+    if ((HAL_GetTick() - tickstart) >=  SDMMC_DATATIMEOUT)
+ 800be8c:	f7f6 fa6a 	bl	8002364 <HAL_GetTick>
+ 800be90:	4602      	mov	r2, r0
+ 800be92:	6b3b      	ldr	r3, [r7, #48]	; 0x30
+ 800be94:	1ad3      	subs	r3, r2, r3
+ 800be96:	f1b3 3fff 	cmp.w	r3, #4294967295
+ 800be9a:	d102      	bne.n	800bea2 <SD_FindSCR+0xe2>
+    {
+      return HAL_SD_ERROR_TIMEOUT;
+ 800be9c:	f04f 4300 	mov.w	r3, #2147483648	; 0x80000000
+ 800bea0:	e058      	b.n	800bf54 <SD_FindSCR+0x194>
+  while (!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND |
+ 800bea2:	687b      	ldr	r3, [r7, #4]
+ 800bea4:	681b      	ldr	r3, [r3, #0]
+ 800bea6:	6b5a      	ldr	r2, [r3, #52]	; 0x34
+ 800bea8:	f240 532a 	movw	r3, #1322	; 0x52a
+ 800beac:	4013      	ands	r3, r2
+ 800beae:	2b00      	cmp	r3, #0
+ 800beb0:	d0d1      	beq.n	800be56 <SD_FindSCR+0x96>
+    }
+  }
+
+  if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT))
+ 800beb2:	687b      	ldr	r3, [r7, #4]
+ 800beb4:	681b      	ldr	r3, [r3, #0]
+ 800beb6:	6b5b      	ldr	r3, [r3, #52]	; 0x34
+ 800beb8:	f003 0308 	and.w	r3, r3, #8
+ 800bebc:	2b00      	cmp	r3, #0
+ 800bebe:	d005      	beq.n	800becc <SD_FindSCR+0x10c>
+  {
+    __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DTIMEOUT);
+ 800bec0:	687b      	ldr	r3, [r7, #4]
+ 800bec2:	681b      	ldr	r3, [r3, #0]
+ 800bec4:	2208      	movs	r2, #8
+ 800bec6:	639a      	str	r2, [r3, #56]	; 0x38
+
+    return HAL_SD_ERROR_DATA_TIMEOUT;
+ 800bec8:	2308      	movs	r3, #8
+ 800beca:	e043      	b.n	800bf54 <SD_FindSCR+0x194>
+  }
+  else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL))
+ 800becc:	687b      	ldr	r3, [r7, #4]
+ 800bece:	681b      	ldr	r3, [r3, #0]
+ 800bed0:	6b5b      	ldr	r3, [r3, #52]	; 0x34
+ 800bed2:	f003 0302 	and.w	r3, r3, #2
+ 800bed6:	2b00      	cmp	r3, #0
+ 800bed8:	d005      	beq.n	800bee6 <SD_FindSCR+0x126>
+  {
+    __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DCRCFAIL);
+ 800beda:	687b      	ldr	r3, [r7, #4]
+ 800bedc:	681b      	ldr	r3, [r3, #0]
+ 800bede:	2202      	movs	r2, #2
+ 800bee0:	639a      	str	r2, [r3, #56]	; 0x38
+
+    return HAL_SD_ERROR_DATA_CRC_FAIL;
+ 800bee2:	2302      	movs	r3, #2
+ 800bee4:	e036      	b.n	800bf54 <SD_FindSCR+0x194>
+  }
+  else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR))
+ 800bee6:	687b      	ldr	r3, [r7, #4]
+ 800bee8:	681b      	ldr	r3, [r3, #0]
+ 800beea:	6b5b      	ldr	r3, [r3, #52]	; 0x34
+ 800beec:	f003 0320 	and.w	r3, r3, #32
+ 800bef0:	2b00      	cmp	r3, #0
+ 800bef2:	d005      	beq.n	800bf00 <SD_FindSCR+0x140>
+  {
+    __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_RXOVERR);
+ 800bef4:	687b      	ldr	r3, [r7, #4]
+ 800bef6:	681b      	ldr	r3, [r3, #0]
+ 800bef8:	2220      	movs	r2, #32
+ 800befa:	639a      	str	r2, [r3, #56]	; 0x38
+
+    return HAL_SD_ERROR_RX_OVERRUN;
+ 800befc:	2320      	movs	r3, #32
+ 800befe:	e029      	b.n	800bf54 <SD_FindSCR+0x194>
+  }
+  else
+  {
+    /* No error flag set */
+    /* Clear all the static flags */
+    __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS);
+ 800bf00:	687b      	ldr	r3, [r7, #4]
+ 800bf02:	681b      	ldr	r3, [r3, #0]
+ 800bf04:	4a15      	ldr	r2, [pc, #84]	; (800bf5c <SD_FindSCR+0x19c>)
+ 800bf06:	639a      	str	r2, [r3, #56]	; 0x38
+
+    *scr = (((tempscr[1] & SDMMC_0TO7BITS) << 24)  | ((tempscr[1] & SDMMC_8TO15BITS) << 8) | \
+ 800bf08:	68fb      	ldr	r3, [r7, #12]
+ 800bf0a:	061a      	lsls	r2, r3, #24
+ 800bf0c:	68fb      	ldr	r3, [r7, #12]
+ 800bf0e:	021b      	lsls	r3, r3, #8
+ 800bf10:	f403 037f 	and.w	r3, r3, #16711680	; 0xff0000
+ 800bf14:	431a      	orrs	r2, r3
+            ((tempscr[1] & SDMMC_16TO23BITS) >> 8) | ((tempscr[1] & SDMMC_24TO31BITS) >> 24));
+ 800bf16:	68fb      	ldr	r3, [r7, #12]
+ 800bf18:	0a1b      	lsrs	r3, r3, #8
+ 800bf1a:	f403 437f 	and.w	r3, r3, #65280	; 0xff00
+    *scr = (((tempscr[1] & SDMMC_0TO7BITS) << 24)  | ((tempscr[1] & SDMMC_8TO15BITS) << 8) | \
+ 800bf1e:	431a      	orrs	r2, r3
+            ((tempscr[1] & SDMMC_16TO23BITS) >> 8) | ((tempscr[1] & SDMMC_24TO31BITS) >> 24));
+ 800bf20:	68fb      	ldr	r3, [r7, #12]
+ 800bf22:	0e1b      	lsrs	r3, r3, #24
+ 800bf24:	431a      	orrs	r2, r3
+    *scr = (((tempscr[1] & SDMMC_0TO7BITS) << 24)  | ((tempscr[1] & SDMMC_8TO15BITS) << 8) | \
+ 800bf26:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 800bf28:	601a      	str	r2, [r3, #0]
+    scr++;
+ 800bf2a:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 800bf2c:	3304      	adds	r3, #4
+ 800bf2e:	62fb      	str	r3, [r7, #44]	; 0x2c
+    *scr = (((tempscr[0] & SDMMC_0TO7BITS) << 24)  | ((tempscr[0] & SDMMC_8TO15BITS) << 8) | \
+ 800bf30:	68bb      	ldr	r3, [r7, #8]
+ 800bf32:	061a      	lsls	r2, r3, #24
+ 800bf34:	68bb      	ldr	r3, [r7, #8]
+ 800bf36:	021b      	lsls	r3, r3, #8
+ 800bf38:	f403 037f 	and.w	r3, r3, #16711680	; 0xff0000
+ 800bf3c:	431a      	orrs	r2, r3
+            ((tempscr[0] & SDMMC_16TO23BITS) >> 8) | ((tempscr[0] & SDMMC_24TO31BITS) >> 24));
+ 800bf3e:	68bb      	ldr	r3, [r7, #8]
+ 800bf40:	0a1b      	lsrs	r3, r3, #8
+ 800bf42:	f403 437f 	and.w	r3, r3, #65280	; 0xff00
+    *scr = (((tempscr[0] & SDMMC_0TO7BITS) << 24)  | ((tempscr[0] & SDMMC_8TO15BITS) << 8) | \
+ 800bf46:	431a      	orrs	r2, r3
+            ((tempscr[0] & SDMMC_16TO23BITS) >> 8) | ((tempscr[0] & SDMMC_24TO31BITS) >> 24));
+ 800bf48:	68bb      	ldr	r3, [r7, #8]
+ 800bf4a:	0e1b      	lsrs	r3, r3, #24
+ 800bf4c:	431a      	orrs	r2, r3
+    *scr = (((tempscr[0] & SDMMC_0TO7BITS) << 24)  | ((tempscr[0] & SDMMC_8TO15BITS) << 8) | \
+ 800bf4e:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 800bf50:	601a      	str	r2, [r3, #0]
+
+  }
+
+  return HAL_SD_ERROR_NONE;
+ 800bf52:	2300      	movs	r3, #0
+}
+ 800bf54:	4618      	mov	r0, r3
+ 800bf56:	3738      	adds	r7, #56	; 0x38
+ 800bf58:	46bd      	mov	sp, r7
+ 800bf5a:	bd80      	pop	{r7, pc}
+ 800bf5c:	18000f3a 	.word	0x18000f3a
+
+0800bf60 <SD_Read_IT>:
+  * @param  hsd: pointer to a SD_HandleTypeDef structure that contains
+  *              the configuration information.
+  * @retval None
+  */
+static void SD_Read_IT(SD_HandleTypeDef *hsd)
+{
+ 800bf60:	b580      	push	{r7, lr}
+ 800bf62:	b086      	sub	sp, #24
+ 800bf64:	af00      	add	r7, sp, #0
+ 800bf66:	6078      	str	r0, [r7, #4]
+  uint32_t count;
+  uint32_t data;
+  uint8_t *tmp;
+
+  tmp = hsd->pRxBuffPtr;
+ 800bf68:	687b      	ldr	r3, [r7, #4]
+ 800bf6a:	6a5b      	ldr	r3, [r3, #36]	; 0x24
+ 800bf6c:	613b      	str	r3, [r7, #16]
+
+  if (hsd->RxXferSize >= 32U)
+ 800bf6e:	687b      	ldr	r3, [r7, #4]
+ 800bf70:	6a9b      	ldr	r3, [r3, #40]	; 0x28
+ 800bf72:	2b1f      	cmp	r3, #31
+ 800bf74:	d936      	bls.n	800bfe4 <SD_Read_IT+0x84>
+  {
+    /* Read data from SDMMC Rx FIFO */
+    for (count = 0U; count < 8U; count++)
+ 800bf76:	2300      	movs	r3, #0
+ 800bf78:	617b      	str	r3, [r7, #20]
+ 800bf7a:	e027      	b.n	800bfcc <SD_Read_IT+0x6c>
+    {
+      data = SDMMC_ReadFIFO(hsd->Instance);
+ 800bf7c:	687b      	ldr	r3, [r7, #4]
+ 800bf7e:	681b      	ldr	r3, [r3, #0]
+ 800bf80:	4618      	mov	r0, r3
+ 800bf82:	f001 ffc5 	bl	800df10 <SDMMC_ReadFIFO>
+ 800bf86:	60f8      	str	r0, [r7, #12]
+      *tmp = (uint8_t)(data & 0xFFU);
+ 800bf88:	68fb      	ldr	r3, [r7, #12]
+ 800bf8a:	b2da      	uxtb	r2, r3
+ 800bf8c:	693b      	ldr	r3, [r7, #16]
+ 800bf8e:	701a      	strb	r2, [r3, #0]
+      tmp++;
+ 800bf90:	693b      	ldr	r3, [r7, #16]
+ 800bf92:	3301      	adds	r3, #1
+ 800bf94:	613b      	str	r3, [r7, #16]
+      *tmp = (uint8_t)((data >> 8U) & 0xFFU);
+ 800bf96:	68fb      	ldr	r3, [r7, #12]
+ 800bf98:	0a1b      	lsrs	r3, r3, #8
+ 800bf9a:	b2da      	uxtb	r2, r3
+ 800bf9c:	693b      	ldr	r3, [r7, #16]
+ 800bf9e:	701a      	strb	r2, [r3, #0]
+      tmp++;
+ 800bfa0:	693b      	ldr	r3, [r7, #16]
+ 800bfa2:	3301      	adds	r3, #1
+ 800bfa4:	613b      	str	r3, [r7, #16]
+      *tmp = (uint8_t)((data >> 16U) & 0xFFU);
+ 800bfa6:	68fb      	ldr	r3, [r7, #12]
+ 800bfa8:	0c1b      	lsrs	r3, r3, #16
+ 800bfaa:	b2da      	uxtb	r2, r3
+ 800bfac:	693b      	ldr	r3, [r7, #16]
+ 800bfae:	701a      	strb	r2, [r3, #0]
+      tmp++;
+ 800bfb0:	693b      	ldr	r3, [r7, #16]
+ 800bfb2:	3301      	adds	r3, #1
+ 800bfb4:	613b      	str	r3, [r7, #16]
+      *tmp = (uint8_t)((data >> 24U) & 0xFFU);
+ 800bfb6:	68fb      	ldr	r3, [r7, #12]
+ 800bfb8:	0e1b      	lsrs	r3, r3, #24
+ 800bfba:	b2da      	uxtb	r2, r3
+ 800bfbc:	693b      	ldr	r3, [r7, #16]
+ 800bfbe:	701a      	strb	r2, [r3, #0]
+      tmp++;
+ 800bfc0:	693b      	ldr	r3, [r7, #16]
+ 800bfc2:	3301      	adds	r3, #1
+ 800bfc4:	613b      	str	r3, [r7, #16]
+    for (count = 0U; count < 8U; count++)
+ 800bfc6:	697b      	ldr	r3, [r7, #20]
+ 800bfc8:	3301      	adds	r3, #1
+ 800bfca:	617b      	str	r3, [r7, #20]
+ 800bfcc:	697b      	ldr	r3, [r7, #20]
+ 800bfce:	2b07      	cmp	r3, #7
+ 800bfd0:	d9d4      	bls.n	800bf7c <SD_Read_IT+0x1c>
+    }
+
+    hsd->pRxBuffPtr = tmp;
+ 800bfd2:	687b      	ldr	r3, [r7, #4]
+ 800bfd4:	693a      	ldr	r2, [r7, #16]
+ 800bfd6:	625a      	str	r2, [r3, #36]	; 0x24
+    hsd->RxXferSize -= 32U;
+ 800bfd8:	687b      	ldr	r3, [r7, #4]
+ 800bfda:	6a9b      	ldr	r3, [r3, #40]	; 0x28
+ 800bfdc:	f1a3 0220 	sub.w	r2, r3, #32
+ 800bfe0:	687b      	ldr	r3, [r7, #4]
+ 800bfe2:	629a      	str	r2, [r3, #40]	; 0x28
+  }
+}
+ 800bfe4:	bf00      	nop
+ 800bfe6:	3718      	adds	r7, #24
+ 800bfe8:	46bd      	mov	sp, r7
+ 800bfea:	bd80      	pop	{r7, pc}
+
+0800bfec <SD_Write_IT>:
+  * @param  hsd: pointer to a SD_HandleTypeDef structure that contains
+  *              the configuration information.
+  * @retval None
+  */
+static void SD_Write_IT(SD_HandleTypeDef *hsd)
+{
+ 800bfec:	b580      	push	{r7, lr}
+ 800bfee:	b086      	sub	sp, #24
+ 800bff0:	af00      	add	r7, sp, #0
+ 800bff2:	6078      	str	r0, [r7, #4]
+  uint32_t count;
+  uint32_t data;
+  const uint8_t *tmp;
+
+  tmp = hsd->pTxBuffPtr;
+ 800bff4:	687b      	ldr	r3, [r7, #4]
+ 800bff6:	69db      	ldr	r3, [r3, #28]
+ 800bff8:	613b      	str	r3, [r7, #16]
+
+  if (hsd->TxXferSize >= 32U)
+ 800bffa:	687b      	ldr	r3, [r7, #4]
+ 800bffc:	6a1b      	ldr	r3, [r3, #32]
+ 800bffe:	2b1f      	cmp	r3, #31
+ 800c000:	d93a      	bls.n	800c078 <SD_Write_IT+0x8c>
+  {
+    /* Write data to SDMMC Tx FIFO */
+    for (count = 0U; count < 8U; count++)
+ 800c002:	2300      	movs	r3, #0
+ 800c004:	617b      	str	r3, [r7, #20]
+ 800c006:	e02b      	b.n	800c060 <SD_Write_IT+0x74>
+    {
+      data = (uint32_t)(*tmp);
+ 800c008:	693b      	ldr	r3, [r7, #16]
+ 800c00a:	781b      	ldrb	r3, [r3, #0]
+ 800c00c:	60fb      	str	r3, [r7, #12]
+      tmp++;
+ 800c00e:	693b      	ldr	r3, [r7, #16]
+ 800c010:	3301      	adds	r3, #1
+ 800c012:	613b      	str	r3, [r7, #16]
+      data |= ((uint32_t)(*tmp) << 8U);
+ 800c014:	693b      	ldr	r3, [r7, #16]
+ 800c016:	781b      	ldrb	r3, [r3, #0]
+ 800c018:	021a      	lsls	r2, r3, #8
+ 800c01a:	68fb      	ldr	r3, [r7, #12]
+ 800c01c:	4313      	orrs	r3, r2
+ 800c01e:	60fb      	str	r3, [r7, #12]
+      tmp++;
+ 800c020:	693b      	ldr	r3, [r7, #16]
+ 800c022:	3301      	adds	r3, #1
+ 800c024:	613b      	str	r3, [r7, #16]
+      data |= ((uint32_t)(*tmp) << 16U);
+ 800c026:	693b      	ldr	r3, [r7, #16]
+ 800c028:	781b      	ldrb	r3, [r3, #0]
+ 800c02a:	041a      	lsls	r2, r3, #16
+ 800c02c:	68fb      	ldr	r3, [r7, #12]
+ 800c02e:	4313      	orrs	r3, r2
+ 800c030:	60fb      	str	r3, [r7, #12]
+      tmp++;
+ 800c032:	693b      	ldr	r3, [r7, #16]
+ 800c034:	3301      	adds	r3, #1
+ 800c036:	613b      	str	r3, [r7, #16]
+      data |= ((uint32_t)(*tmp) << 24U);
+ 800c038:	693b      	ldr	r3, [r7, #16]
+ 800c03a:	781b      	ldrb	r3, [r3, #0]
+ 800c03c:	061a      	lsls	r2, r3, #24
+ 800c03e:	68fb      	ldr	r3, [r7, #12]
+ 800c040:	4313      	orrs	r3, r2
+ 800c042:	60fb      	str	r3, [r7, #12]
+      tmp++;
+ 800c044:	693b      	ldr	r3, [r7, #16]
+ 800c046:	3301      	adds	r3, #1
+ 800c048:	613b      	str	r3, [r7, #16]
+      (void)SDMMC_WriteFIFO(hsd->Instance, &data);
+ 800c04a:	687b      	ldr	r3, [r7, #4]
+ 800c04c:	681b      	ldr	r3, [r3, #0]
+ 800c04e:	f107 020c 	add.w	r2, r7, #12
+ 800c052:	4611      	mov	r1, r2
+ 800c054:	4618      	mov	r0, r3
+ 800c056:	f001 ff68 	bl	800df2a <SDMMC_WriteFIFO>
+    for (count = 0U; count < 8U; count++)
+ 800c05a:	697b      	ldr	r3, [r7, #20]
+ 800c05c:	3301      	adds	r3, #1
+ 800c05e:	617b      	str	r3, [r7, #20]
+ 800c060:	697b      	ldr	r3, [r7, #20]
+ 800c062:	2b07      	cmp	r3, #7
+ 800c064:	d9d0      	bls.n	800c008 <SD_Write_IT+0x1c>
+    }
+
+    hsd->pTxBuffPtr = tmp;
+ 800c066:	687b      	ldr	r3, [r7, #4]
+ 800c068:	693a      	ldr	r2, [r7, #16]
+ 800c06a:	61da      	str	r2, [r3, #28]
+    hsd->TxXferSize -= 32U;
+ 800c06c:	687b      	ldr	r3, [r7, #4]
+ 800c06e:	6a1b      	ldr	r3, [r3, #32]
+ 800c070:	f1a3 0220 	sub.w	r2, r3, #32
+ 800c074:	687b      	ldr	r3, [r7, #4]
+ 800c076:	621a      	str	r2, [r3, #32]
+  }
+}
+ 800c078:	bf00      	nop
+ 800c07a:	3718      	adds	r7, #24
+ 800c07c:	46bd      	mov	sp, r7
+ 800c07e:	bd80      	pop	{r7, pc}
+
+0800c080 <HAL_SDEx_Read_DMADoubleBuf0CpltCallback>:
+  * @brief Read DMA Buffer 0 Transfer completed callbacks
+  * @param hsd: SD handle
+  * @retval None
+  */
+__weak void HAL_SDEx_Read_DMADoubleBuf0CpltCallback(SD_HandleTypeDef *hsd)
+{
+ 800c080:	b480      	push	{r7}
+ 800c082:	b083      	sub	sp, #12
+ 800c084:	af00      	add	r7, sp, #0
+ 800c086:	6078      	str	r0, [r7, #4]
+  UNUSED(hsd);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SDEx_Read_DMADoubleBuf0CpltCallback can be implemented in the user file
+   */
+}
+ 800c088:	bf00      	nop
+ 800c08a:	370c      	adds	r7, #12
+ 800c08c:	46bd      	mov	sp, r7
+ 800c08e:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 800c092:	4770      	bx	lr
+
+0800c094 <HAL_SDEx_Read_DMADoubleBuf1CpltCallback>:
+  * @brief Read DMA Buffer 1 Transfer completed callbacks
+  * @param hsd: SD handle
+  * @retval None
+  */
+__weak void HAL_SDEx_Read_DMADoubleBuf1CpltCallback(SD_HandleTypeDef *hsd)
+{
+ 800c094:	b480      	push	{r7}
+ 800c096:	b083      	sub	sp, #12
+ 800c098:	af00      	add	r7, sp, #0
+ 800c09a:	6078      	str	r0, [r7, #4]
+  UNUSED(hsd);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SDEx_Read_DMADoubleBuf1CpltCallback can be implemented in the user file
+   */
+}
+ 800c09c:	bf00      	nop
+ 800c09e:	370c      	adds	r7, #12
+ 800c0a0:	46bd      	mov	sp, r7
+ 800c0a2:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 800c0a6:	4770      	bx	lr
+
+0800c0a8 <HAL_SDEx_Write_DMADoubleBuf0CpltCallback>:
+  * @brief Write DMA Buffer 0 Transfer completed callbacks
+  * @param hsd: SD handle
+  * @retval None
+  */
+__weak void HAL_SDEx_Write_DMADoubleBuf0CpltCallback(SD_HandleTypeDef *hsd)
+{
+ 800c0a8:	b480      	push	{r7}
+ 800c0aa:	b083      	sub	sp, #12
+ 800c0ac:	af00      	add	r7, sp, #0
+ 800c0ae:	6078      	str	r0, [r7, #4]
+  UNUSED(hsd);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SDEx_Write_DMADoubleBuf0CpltCallback can be implemented in the user file
+   */
+}
+ 800c0b0:	bf00      	nop
+ 800c0b2:	370c      	adds	r7, #12
+ 800c0b4:	46bd      	mov	sp, r7
+ 800c0b6:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 800c0ba:	4770      	bx	lr
+
+0800c0bc <HAL_SDEx_Write_DMADoubleBuf1CpltCallback>:
+  * @brief Write DMA Buffer 1 Transfer completed callbacks
+  * @param hsd: SD handle
+  * @retval None
+  */
+__weak void HAL_SDEx_Write_DMADoubleBuf1CpltCallback(SD_HandleTypeDef *hsd)
+{
+ 800c0bc:	b480      	push	{r7}
+ 800c0be:	b083      	sub	sp, #12
+ 800c0c0:	af00      	add	r7, sp, #0
+ 800c0c2:	6078      	str	r0, [r7, #4]
+  UNUSED(hsd);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SDEx_Write_DMADoubleBuf1CpltCallback can be implemented in the user file
+   */
+}
+ 800c0c4:	bf00      	nop
+ 800c0c6:	370c      	adds	r7, #12
+ 800c0c8:	46bd      	mov	sp, r7
+ 800c0ca:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 800c0ce:	4770      	bx	lr
+
+0800c0d0 <HAL_TIM_Base_Init>:
+  *         Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
+  * @param  htim TIM Base handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
+{
+ 800c0d0:	b580      	push	{r7, lr}
+ 800c0d2:	b082      	sub	sp, #8
+ 800c0d4:	af00      	add	r7, sp, #0
+ 800c0d6:	6078      	str	r0, [r7, #4]
+  /* Check the TIM handle allocation */
+  if (htim == NULL)
+ 800c0d8:	687b      	ldr	r3, [r7, #4]
+ 800c0da:	2b00      	cmp	r3, #0
+ 800c0dc:	d101      	bne.n	800c0e2 <HAL_TIM_Base_Init+0x12>
+  {
+    return HAL_ERROR;
+ 800c0de:	2301      	movs	r3, #1
+ 800c0e0:	e049      	b.n	800c176 <HAL_TIM_Base_Init+0xa6>
+  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+  assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
+  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+
+  if (htim->State == HAL_TIM_STATE_RESET)
+ 800c0e2:	687b      	ldr	r3, [r7, #4]
+ 800c0e4:	f893 303d 	ldrb.w	r3, [r3, #61]	; 0x3d
+ 800c0e8:	b2db      	uxtb	r3, r3
+ 800c0ea:	2b00      	cmp	r3, #0
+ 800c0ec:	d106      	bne.n	800c0fc <HAL_TIM_Base_Init+0x2c>
+  {
+    /* Allocate lock resource and initialize it */
+    htim->Lock = HAL_UNLOCKED;
+ 800c0ee:	687b      	ldr	r3, [r7, #4]
+ 800c0f0:	2200      	movs	r2, #0
+ 800c0f2:	f883 203c 	strb.w	r2, [r3, #60]	; 0x3c
+    }
+    /* Init the low level hardware : GPIO, CLOCK, NVIC */
+    htim->Base_MspInitCallback(htim);
+#else
+    /* Init the low level hardware : GPIO, CLOCK, NVIC */
+    HAL_TIM_Base_MspInit(htim);
+ 800c0f6:	6878      	ldr	r0, [r7, #4]
+ 800c0f8:	f7f5 fbf6 	bl	80018e8 <HAL_TIM_Base_MspInit>
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+  }
+
+  /* Set the TIM state */
+  htim->State = HAL_TIM_STATE_BUSY;
+ 800c0fc:	687b      	ldr	r3, [r7, #4]
+ 800c0fe:	2202      	movs	r2, #2
+ 800c100:	f883 203d 	strb.w	r2, [r3, #61]	; 0x3d
+
+  /* Set the Time Base configuration */
+  TIM_Base_SetConfig(htim->Instance, &htim->Init);
+ 800c104:	687b      	ldr	r3, [r7, #4]
+ 800c106:	681a      	ldr	r2, [r3, #0]
+ 800c108:	687b      	ldr	r3, [r7, #4]
+ 800c10a:	3304      	adds	r3, #4
+ 800c10c:	4619      	mov	r1, r3
+ 800c10e:	4610      	mov	r0, r2
+ 800c110:	f000 fafc 	bl	800c70c <TIM_Base_SetConfig>
+
+  /* Initialize the DMA burst operation state */
+  htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+ 800c114:	687b      	ldr	r3, [r7, #4]
+ 800c116:	2201      	movs	r2, #1
+ 800c118:	f883 2048 	strb.w	r2, [r3, #72]	; 0x48
+
+  /* Initialize the TIM channels state */
+  TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+ 800c11c:	687b      	ldr	r3, [r7, #4]
+ 800c11e:	2201      	movs	r2, #1
+ 800c120:	f883 203e 	strb.w	r2, [r3, #62]	; 0x3e
+ 800c124:	687b      	ldr	r3, [r7, #4]
+ 800c126:	2201      	movs	r2, #1
+ 800c128:	f883 203f 	strb.w	r2, [r3, #63]	; 0x3f
+ 800c12c:	687b      	ldr	r3, [r7, #4]
+ 800c12e:	2201      	movs	r2, #1
+ 800c130:	f883 2040 	strb.w	r2, [r3, #64]	; 0x40
+ 800c134:	687b      	ldr	r3, [r7, #4]
+ 800c136:	2201      	movs	r2, #1
+ 800c138:	f883 2041 	strb.w	r2, [r3, #65]	; 0x41
+ 800c13c:	687b      	ldr	r3, [r7, #4]
+ 800c13e:	2201      	movs	r2, #1
+ 800c140:	f883 2042 	strb.w	r2, [r3, #66]	; 0x42
+ 800c144:	687b      	ldr	r3, [r7, #4]
+ 800c146:	2201      	movs	r2, #1
+ 800c148:	f883 2043 	strb.w	r2, [r3, #67]	; 0x43
+  TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+ 800c14c:	687b      	ldr	r3, [r7, #4]
+ 800c14e:	2201      	movs	r2, #1
+ 800c150:	f883 2044 	strb.w	r2, [r3, #68]	; 0x44
+ 800c154:	687b      	ldr	r3, [r7, #4]
+ 800c156:	2201      	movs	r2, #1
+ 800c158:	f883 2045 	strb.w	r2, [r3, #69]	; 0x45
+ 800c15c:	687b      	ldr	r3, [r7, #4]
+ 800c15e:	2201      	movs	r2, #1
+ 800c160:	f883 2046 	strb.w	r2, [r3, #70]	; 0x46
+ 800c164:	687b      	ldr	r3, [r7, #4]
+ 800c166:	2201      	movs	r2, #1
+ 800c168:	f883 2047 	strb.w	r2, [r3, #71]	; 0x47
+
+  /* Initialize the TIM state*/
+  htim->State = HAL_TIM_STATE_READY;
+ 800c16c:	687b      	ldr	r3, [r7, #4]
+ 800c16e:	2201      	movs	r2, #1
+ 800c170:	f883 203d 	strb.w	r2, [r3, #61]	; 0x3d
+
+  return HAL_OK;
+ 800c174:	2300      	movs	r3, #0
+}
+ 800c176:	4618      	mov	r0, r3
+ 800c178:	3708      	adds	r7, #8
+ 800c17a:	46bd      	mov	sp, r7
+ 800c17c:	bd80      	pop	{r7, pc}
+	...
+
+0800c180 <HAL_TIM_Base_Start_IT>:
+  * @brief  Starts the TIM Base generation in interrupt mode.
+  * @param  htim TIM Base handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
+{
+ 800c180:	b480      	push	{r7}
+ 800c182:	b085      	sub	sp, #20
+ 800c184:	af00      	add	r7, sp, #0
+ 800c186:	6078      	str	r0, [r7, #4]
+
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+  /* Check the TIM state */
+  if (htim->State != HAL_TIM_STATE_READY)
+ 800c188:	687b      	ldr	r3, [r7, #4]
+ 800c18a:	f893 303d 	ldrb.w	r3, [r3, #61]	; 0x3d
+ 800c18e:	b2db      	uxtb	r3, r3
+ 800c190:	2b01      	cmp	r3, #1
+ 800c192:	d001      	beq.n	800c198 <HAL_TIM_Base_Start_IT+0x18>
+  {
+    return HAL_ERROR;
+ 800c194:	2301      	movs	r3, #1
+ 800c196:	e05e      	b.n	800c256 <HAL_TIM_Base_Start_IT+0xd6>
+  }
+
+  /* Set the TIM state */
+  htim->State = HAL_TIM_STATE_BUSY;
+ 800c198:	687b      	ldr	r3, [r7, #4]
+ 800c19a:	2202      	movs	r2, #2
+ 800c19c:	f883 203d 	strb.w	r2, [r3, #61]	; 0x3d
+
+  /* Enable the TIM Update interrupt */
+  __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
+ 800c1a0:	687b      	ldr	r3, [r7, #4]
+ 800c1a2:	681b      	ldr	r3, [r3, #0]
+ 800c1a4:	68da      	ldr	r2, [r3, #12]
+ 800c1a6:	687b      	ldr	r3, [r7, #4]
+ 800c1a8:	681b      	ldr	r3, [r3, #0]
+ 800c1aa:	f042 0201 	orr.w	r2, r2, #1
+ 800c1ae:	60da      	str	r2, [r3, #12]
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ 800c1b0:	687b      	ldr	r3, [r7, #4]
+ 800c1b2:	681b      	ldr	r3, [r3, #0]
+ 800c1b4:	4a2b      	ldr	r2, [pc, #172]	; (800c264 <HAL_TIM_Base_Start_IT+0xe4>)
+ 800c1b6:	4293      	cmp	r3, r2
+ 800c1b8:	d02c      	beq.n	800c214 <HAL_TIM_Base_Start_IT+0x94>
+ 800c1ba:	687b      	ldr	r3, [r7, #4]
+ 800c1bc:	681b      	ldr	r3, [r3, #0]
+ 800c1be:	f1b3 4f80 	cmp.w	r3, #1073741824	; 0x40000000
+ 800c1c2:	d027      	beq.n	800c214 <HAL_TIM_Base_Start_IT+0x94>
+ 800c1c4:	687b      	ldr	r3, [r7, #4]
+ 800c1c6:	681b      	ldr	r3, [r3, #0]
+ 800c1c8:	4a27      	ldr	r2, [pc, #156]	; (800c268 <HAL_TIM_Base_Start_IT+0xe8>)
+ 800c1ca:	4293      	cmp	r3, r2
+ 800c1cc:	d022      	beq.n	800c214 <HAL_TIM_Base_Start_IT+0x94>
+ 800c1ce:	687b      	ldr	r3, [r7, #4]
+ 800c1d0:	681b      	ldr	r3, [r3, #0]
+ 800c1d2:	4a26      	ldr	r2, [pc, #152]	; (800c26c <HAL_TIM_Base_Start_IT+0xec>)
+ 800c1d4:	4293      	cmp	r3, r2
+ 800c1d6:	d01d      	beq.n	800c214 <HAL_TIM_Base_Start_IT+0x94>
+ 800c1d8:	687b      	ldr	r3, [r7, #4]
+ 800c1da:	681b      	ldr	r3, [r3, #0]
+ 800c1dc:	4a24      	ldr	r2, [pc, #144]	; (800c270 <HAL_TIM_Base_Start_IT+0xf0>)
+ 800c1de:	4293      	cmp	r3, r2
+ 800c1e0:	d018      	beq.n	800c214 <HAL_TIM_Base_Start_IT+0x94>
+ 800c1e2:	687b      	ldr	r3, [r7, #4]
+ 800c1e4:	681b      	ldr	r3, [r3, #0]
+ 800c1e6:	4a23      	ldr	r2, [pc, #140]	; (800c274 <HAL_TIM_Base_Start_IT+0xf4>)
+ 800c1e8:	4293      	cmp	r3, r2
+ 800c1ea:	d013      	beq.n	800c214 <HAL_TIM_Base_Start_IT+0x94>
+ 800c1ec:	687b      	ldr	r3, [r7, #4]
+ 800c1ee:	681b      	ldr	r3, [r3, #0]
+ 800c1f0:	4a21      	ldr	r2, [pc, #132]	; (800c278 <HAL_TIM_Base_Start_IT+0xf8>)
+ 800c1f2:	4293      	cmp	r3, r2
+ 800c1f4:	d00e      	beq.n	800c214 <HAL_TIM_Base_Start_IT+0x94>
+ 800c1f6:	687b      	ldr	r3, [r7, #4]
+ 800c1f8:	681b      	ldr	r3, [r3, #0]
+ 800c1fa:	4a20      	ldr	r2, [pc, #128]	; (800c27c <HAL_TIM_Base_Start_IT+0xfc>)
+ 800c1fc:	4293      	cmp	r3, r2
+ 800c1fe:	d009      	beq.n	800c214 <HAL_TIM_Base_Start_IT+0x94>
+ 800c200:	687b      	ldr	r3, [r7, #4]
+ 800c202:	681b      	ldr	r3, [r3, #0]
+ 800c204:	4a1e      	ldr	r2, [pc, #120]	; (800c280 <HAL_TIM_Base_Start_IT+0x100>)
+ 800c206:	4293      	cmp	r3, r2
+ 800c208:	d004      	beq.n	800c214 <HAL_TIM_Base_Start_IT+0x94>
+ 800c20a:	687b      	ldr	r3, [r7, #4]
+ 800c20c:	681b      	ldr	r3, [r3, #0]
+ 800c20e:	4a1d      	ldr	r2, [pc, #116]	; (800c284 <HAL_TIM_Base_Start_IT+0x104>)
+ 800c210:	4293      	cmp	r3, r2
+ 800c212:	d115      	bne.n	800c240 <HAL_TIM_Base_Start_IT+0xc0>
+  {
+    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ 800c214:	687b      	ldr	r3, [r7, #4]
+ 800c216:	681b      	ldr	r3, [r3, #0]
+ 800c218:	689a      	ldr	r2, [r3, #8]
+ 800c21a:	4b1b      	ldr	r3, [pc, #108]	; (800c288 <HAL_TIM_Base_Start_IT+0x108>)
+ 800c21c:	4013      	ands	r3, r2
+ 800c21e:	60fb      	str	r3, [r7, #12]
+    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 800c220:	68fb      	ldr	r3, [r7, #12]
+ 800c222:	2b06      	cmp	r3, #6
+ 800c224:	d015      	beq.n	800c252 <HAL_TIM_Base_Start_IT+0xd2>
+ 800c226:	68fb      	ldr	r3, [r7, #12]
+ 800c228:	f5b3 3f80 	cmp.w	r3, #65536	; 0x10000
+ 800c22c:	d011      	beq.n	800c252 <HAL_TIM_Base_Start_IT+0xd2>
+    {
+      __HAL_TIM_ENABLE(htim);
+ 800c22e:	687b      	ldr	r3, [r7, #4]
+ 800c230:	681b      	ldr	r3, [r3, #0]
+ 800c232:	681a      	ldr	r2, [r3, #0]
+ 800c234:	687b      	ldr	r3, [r7, #4]
+ 800c236:	681b      	ldr	r3, [r3, #0]
+ 800c238:	f042 0201 	orr.w	r2, r2, #1
+ 800c23c:	601a      	str	r2, [r3, #0]
+    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 800c23e:	e008      	b.n	800c252 <HAL_TIM_Base_Start_IT+0xd2>
+    }
+  }
+  else
+  {
+    __HAL_TIM_ENABLE(htim);
+ 800c240:	687b      	ldr	r3, [r7, #4]
+ 800c242:	681b      	ldr	r3, [r3, #0]
+ 800c244:	681a      	ldr	r2, [r3, #0]
+ 800c246:	687b      	ldr	r3, [r7, #4]
+ 800c248:	681b      	ldr	r3, [r3, #0]
+ 800c24a:	f042 0201 	orr.w	r2, r2, #1
+ 800c24e:	601a      	str	r2, [r3, #0]
+ 800c250:	e000      	b.n	800c254 <HAL_TIM_Base_Start_IT+0xd4>
+    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 800c252:	bf00      	nop
+  }
+
+  /* Return function status */
+  return HAL_OK;
+ 800c254:	2300      	movs	r3, #0
+}
+ 800c256:	4618      	mov	r0, r3
+ 800c258:	3714      	adds	r7, #20
+ 800c25a:	46bd      	mov	sp, r7
+ 800c25c:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 800c260:	4770      	bx	lr
+ 800c262:	bf00      	nop
+ 800c264:	40010000 	.word	0x40010000
+ 800c268:	40000400 	.word	0x40000400
+ 800c26c:	40000800 	.word	0x40000800
+ 800c270:	40000c00 	.word	0x40000c00
+ 800c274:	40010400 	.word	0x40010400
+ 800c278:	40001800 	.word	0x40001800
+ 800c27c:	40014000 	.word	0x40014000
+ 800c280:	4000e000 	.word	0x4000e000
+ 800c284:	4000e400 	.word	0x4000e400
+ 800c288:	00010007 	.word	0x00010007
+
+0800c28c <HAL_TIM_IRQHandler>:
+  * @brief  This function handles TIM interrupts requests.
+  * @param  htim TIM  handle
+  * @retval None
+  */
+void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
+{
+ 800c28c:	b580      	push	{r7, lr}
+ 800c28e:	b082      	sub	sp, #8
+ 800c290:	af00      	add	r7, sp, #0
+ 800c292:	6078      	str	r0, [r7, #4]
+  /* Capture compare 1 event */
+  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
+ 800c294:	687b      	ldr	r3, [r7, #4]
+ 800c296:	681b      	ldr	r3, [r3, #0]
+ 800c298:	691b      	ldr	r3, [r3, #16]
+ 800c29a:	f003 0302 	and.w	r3, r3, #2
+ 800c29e:	2b02      	cmp	r3, #2
+ 800c2a0:	d122      	bne.n	800c2e8 <HAL_TIM_IRQHandler+0x5c>
+  {
+    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET)
+ 800c2a2:	687b      	ldr	r3, [r7, #4]
+ 800c2a4:	681b      	ldr	r3, [r3, #0]
+ 800c2a6:	68db      	ldr	r3, [r3, #12]
+ 800c2a8:	f003 0302 	and.w	r3, r3, #2
+ 800c2ac:	2b02      	cmp	r3, #2
+ 800c2ae:	d11b      	bne.n	800c2e8 <HAL_TIM_IRQHandler+0x5c>
+    {
+      {
+        __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
+ 800c2b0:	687b      	ldr	r3, [r7, #4]
+ 800c2b2:	681b      	ldr	r3, [r3, #0]
+ 800c2b4:	f06f 0202 	mvn.w	r2, #2
+ 800c2b8:	611a      	str	r2, [r3, #16]
+        htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+ 800c2ba:	687b      	ldr	r3, [r7, #4]
+ 800c2bc:	2201      	movs	r2, #1
+ 800c2be:	771a      	strb	r2, [r3, #28]
+
+        /* Input capture event */
+        if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
+ 800c2c0:	687b      	ldr	r3, [r7, #4]
+ 800c2c2:	681b      	ldr	r3, [r3, #0]
+ 800c2c4:	699b      	ldr	r3, [r3, #24]
+ 800c2c6:	f003 0303 	and.w	r3, r3, #3
+ 800c2ca:	2b00      	cmp	r3, #0
+ 800c2cc:	d003      	beq.n	800c2d6 <HAL_TIM_IRQHandler+0x4a>
+        {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+          htim->IC_CaptureCallback(htim);
+#else
+          HAL_TIM_IC_CaptureCallback(htim);
+ 800c2ce:	6878      	ldr	r0, [r7, #4]
+ 800c2d0:	f000 f9fe 	bl	800c6d0 <HAL_TIM_IC_CaptureCallback>
+ 800c2d4:	e005      	b.n	800c2e2 <HAL_TIM_IRQHandler+0x56>
+        {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+          htim->OC_DelayElapsedCallback(htim);
+          htim->PWM_PulseFinishedCallback(htim);
+#else
+          HAL_TIM_OC_DelayElapsedCallback(htim);
+ 800c2d6:	6878      	ldr	r0, [r7, #4]
+ 800c2d8:	f000 f9f0 	bl	800c6bc <HAL_TIM_OC_DelayElapsedCallback>
+          HAL_TIM_PWM_PulseFinishedCallback(htim);
+ 800c2dc:	6878      	ldr	r0, [r7, #4]
+ 800c2de:	f000 fa01 	bl	800c6e4 <HAL_TIM_PWM_PulseFinishedCallback>
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+        }
+        htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+ 800c2e2:	687b      	ldr	r3, [r7, #4]
+ 800c2e4:	2200      	movs	r2, #0
+ 800c2e6:	771a      	strb	r2, [r3, #28]
+      }
+    }
+  }
+  /* Capture compare 2 event */
+  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
+ 800c2e8:	687b      	ldr	r3, [r7, #4]
+ 800c2ea:	681b      	ldr	r3, [r3, #0]
+ 800c2ec:	691b      	ldr	r3, [r3, #16]
+ 800c2ee:	f003 0304 	and.w	r3, r3, #4
+ 800c2f2:	2b04      	cmp	r3, #4
+ 800c2f4:	d122      	bne.n	800c33c <HAL_TIM_IRQHandler+0xb0>
+  {
+    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET)
+ 800c2f6:	687b      	ldr	r3, [r7, #4]
+ 800c2f8:	681b      	ldr	r3, [r3, #0]
+ 800c2fa:	68db      	ldr	r3, [r3, #12]
+ 800c2fc:	f003 0304 	and.w	r3, r3, #4
+ 800c300:	2b04      	cmp	r3, #4
+ 800c302:	d11b      	bne.n	800c33c <HAL_TIM_IRQHandler+0xb0>
+    {
+      __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
+ 800c304:	687b      	ldr	r3, [r7, #4]
+ 800c306:	681b      	ldr	r3, [r3, #0]
+ 800c308:	f06f 0204 	mvn.w	r2, #4
+ 800c30c:	611a      	str	r2, [r3, #16]
+      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+ 800c30e:	687b      	ldr	r3, [r7, #4]
+ 800c310:	2202      	movs	r2, #2
+ 800c312:	771a      	strb	r2, [r3, #28]
+      /* Input capture event */
+      if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
+ 800c314:	687b      	ldr	r3, [r7, #4]
+ 800c316:	681b      	ldr	r3, [r3, #0]
+ 800c318:	699b      	ldr	r3, [r3, #24]
+ 800c31a:	f403 7340 	and.w	r3, r3, #768	; 0x300
+ 800c31e:	2b00      	cmp	r3, #0
+ 800c320:	d003      	beq.n	800c32a <HAL_TIM_IRQHandler+0x9e>
+      {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+        htim->IC_CaptureCallback(htim);
+#else
+        HAL_TIM_IC_CaptureCallback(htim);
+ 800c322:	6878      	ldr	r0, [r7, #4]
+ 800c324:	f000 f9d4 	bl	800c6d0 <HAL_TIM_IC_CaptureCallback>
+ 800c328:	e005      	b.n	800c336 <HAL_TIM_IRQHandler+0xaa>
+      {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+        htim->OC_DelayElapsedCallback(htim);
+        htim->PWM_PulseFinishedCallback(htim);
+#else
+        HAL_TIM_OC_DelayElapsedCallback(htim);
+ 800c32a:	6878      	ldr	r0, [r7, #4]
+ 800c32c:	f000 f9c6 	bl	800c6bc <HAL_TIM_OC_DelayElapsedCallback>
+        HAL_TIM_PWM_PulseFinishedCallback(htim);
+ 800c330:	6878      	ldr	r0, [r7, #4]
+ 800c332:	f000 f9d7 	bl	800c6e4 <HAL_TIM_PWM_PulseFinishedCallback>
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+      }
+      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+ 800c336:	687b      	ldr	r3, [r7, #4]
+ 800c338:	2200      	movs	r2, #0
+ 800c33a:	771a      	strb	r2, [r3, #28]
+    }
+  }
+  /* Capture compare 3 event */
+  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
+ 800c33c:	687b      	ldr	r3, [r7, #4]
+ 800c33e:	681b      	ldr	r3, [r3, #0]
+ 800c340:	691b      	ldr	r3, [r3, #16]
+ 800c342:	f003 0308 	and.w	r3, r3, #8
+ 800c346:	2b08      	cmp	r3, #8
+ 800c348:	d122      	bne.n	800c390 <HAL_TIM_IRQHandler+0x104>
+  {
+    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET)
+ 800c34a:	687b      	ldr	r3, [r7, #4]
+ 800c34c:	681b      	ldr	r3, [r3, #0]
+ 800c34e:	68db      	ldr	r3, [r3, #12]
+ 800c350:	f003 0308 	and.w	r3, r3, #8
+ 800c354:	2b08      	cmp	r3, #8
+ 800c356:	d11b      	bne.n	800c390 <HAL_TIM_IRQHandler+0x104>
+    {
+      __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
+ 800c358:	687b      	ldr	r3, [r7, #4]
+ 800c35a:	681b      	ldr	r3, [r3, #0]
+ 800c35c:	f06f 0208 	mvn.w	r2, #8
+ 800c360:	611a      	str	r2, [r3, #16]
+      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+ 800c362:	687b      	ldr	r3, [r7, #4]
+ 800c364:	2204      	movs	r2, #4
+ 800c366:	771a      	strb	r2, [r3, #28]
+      /* Input capture event */
+      if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
+ 800c368:	687b      	ldr	r3, [r7, #4]
+ 800c36a:	681b      	ldr	r3, [r3, #0]
+ 800c36c:	69db      	ldr	r3, [r3, #28]
+ 800c36e:	f003 0303 	and.w	r3, r3, #3
+ 800c372:	2b00      	cmp	r3, #0
+ 800c374:	d003      	beq.n	800c37e <HAL_TIM_IRQHandler+0xf2>
+      {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+        htim->IC_CaptureCallback(htim);
+#else
+        HAL_TIM_IC_CaptureCallback(htim);
+ 800c376:	6878      	ldr	r0, [r7, #4]
+ 800c378:	f000 f9aa 	bl	800c6d0 <HAL_TIM_IC_CaptureCallback>
+ 800c37c:	e005      	b.n	800c38a <HAL_TIM_IRQHandler+0xfe>
+      {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+        htim->OC_DelayElapsedCallback(htim);
+        htim->PWM_PulseFinishedCallback(htim);
+#else
+        HAL_TIM_OC_DelayElapsedCallback(htim);
+ 800c37e:	6878      	ldr	r0, [r7, #4]
+ 800c380:	f000 f99c 	bl	800c6bc <HAL_TIM_OC_DelayElapsedCallback>
+        HAL_TIM_PWM_PulseFinishedCallback(htim);
+ 800c384:	6878      	ldr	r0, [r7, #4]
+ 800c386:	f000 f9ad 	bl	800c6e4 <HAL_TIM_PWM_PulseFinishedCallback>
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+      }
+      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+ 800c38a:	687b      	ldr	r3, [r7, #4]
+ 800c38c:	2200      	movs	r2, #0
+ 800c38e:	771a      	strb	r2, [r3, #28]
+    }
+  }
+  /* Capture compare 4 event */
+  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
+ 800c390:	687b      	ldr	r3, [r7, #4]
+ 800c392:	681b      	ldr	r3, [r3, #0]
+ 800c394:	691b      	ldr	r3, [r3, #16]
+ 800c396:	f003 0310 	and.w	r3, r3, #16
+ 800c39a:	2b10      	cmp	r3, #16
+ 800c39c:	d122      	bne.n	800c3e4 <HAL_TIM_IRQHandler+0x158>
+  {
+    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET)
+ 800c39e:	687b      	ldr	r3, [r7, #4]
+ 800c3a0:	681b      	ldr	r3, [r3, #0]
+ 800c3a2:	68db      	ldr	r3, [r3, #12]
+ 800c3a4:	f003 0310 	and.w	r3, r3, #16
+ 800c3a8:	2b10      	cmp	r3, #16
+ 800c3aa:	d11b      	bne.n	800c3e4 <HAL_TIM_IRQHandler+0x158>
+    {
+      __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
+ 800c3ac:	687b      	ldr	r3, [r7, #4]
+ 800c3ae:	681b      	ldr	r3, [r3, #0]
+ 800c3b0:	f06f 0210 	mvn.w	r2, #16
+ 800c3b4:	611a      	str	r2, [r3, #16]
+      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+ 800c3b6:	687b      	ldr	r3, [r7, #4]
+ 800c3b8:	2208      	movs	r2, #8
+ 800c3ba:	771a      	strb	r2, [r3, #28]
+      /* Input capture event */
+      if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
+ 800c3bc:	687b      	ldr	r3, [r7, #4]
+ 800c3be:	681b      	ldr	r3, [r3, #0]
+ 800c3c0:	69db      	ldr	r3, [r3, #28]
+ 800c3c2:	f403 7340 	and.w	r3, r3, #768	; 0x300
+ 800c3c6:	2b00      	cmp	r3, #0
+ 800c3c8:	d003      	beq.n	800c3d2 <HAL_TIM_IRQHandler+0x146>
+      {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+        htim->IC_CaptureCallback(htim);
+#else
+        HAL_TIM_IC_CaptureCallback(htim);
+ 800c3ca:	6878      	ldr	r0, [r7, #4]
+ 800c3cc:	f000 f980 	bl	800c6d0 <HAL_TIM_IC_CaptureCallback>
+ 800c3d0:	e005      	b.n	800c3de <HAL_TIM_IRQHandler+0x152>
+      {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+        htim->OC_DelayElapsedCallback(htim);
+        htim->PWM_PulseFinishedCallback(htim);
+#else
+        HAL_TIM_OC_DelayElapsedCallback(htim);
+ 800c3d2:	6878      	ldr	r0, [r7, #4]
+ 800c3d4:	f000 f972 	bl	800c6bc <HAL_TIM_OC_DelayElapsedCallback>
+        HAL_TIM_PWM_PulseFinishedCallback(htim);
+ 800c3d8:	6878      	ldr	r0, [r7, #4]
+ 800c3da:	f000 f983 	bl	800c6e4 <HAL_TIM_PWM_PulseFinishedCallback>
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+      }
+      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+ 800c3de:	687b      	ldr	r3, [r7, #4]
+ 800c3e0:	2200      	movs	r2, #0
+ 800c3e2:	771a      	strb	r2, [r3, #28]
+    }
+  }
+  /* TIM Update event */
+  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
+ 800c3e4:	687b      	ldr	r3, [r7, #4]
+ 800c3e6:	681b      	ldr	r3, [r3, #0]
+ 800c3e8:	691b      	ldr	r3, [r3, #16]
+ 800c3ea:	f003 0301 	and.w	r3, r3, #1
+ 800c3ee:	2b01      	cmp	r3, #1
+ 800c3f0:	d10e      	bne.n	800c410 <HAL_TIM_IRQHandler+0x184>
+  {
+    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET)
+ 800c3f2:	687b      	ldr	r3, [r7, #4]
+ 800c3f4:	681b      	ldr	r3, [r3, #0]
+ 800c3f6:	68db      	ldr	r3, [r3, #12]
+ 800c3f8:	f003 0301 	and.w	r3, r3, #1
+ 800c3fc:	2b01      	cmp	r3, #1
+ 800c3fe:	d107      	bne.n	800c410 <HAL_TIM_IRQHandler+0x184>
+    {
+      __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
+ 800c400:	687b      	ldr	r3, [r7, #4]
+ 800c402:	681b      	ldr	r3, [r3, #0]
+ 800c404:	f06f 0201 	mvn.w	r2, #1
+ 800c408:	611a      	str	r2, [r3, #16]
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+      htim->PeriodElapsedCallback(htim);
+#else
+      HAL_TIM_PeriodElapsedCallback(htim);
+ 800c40a:	6878      	ldr	r0, [r7, #4]
+ 800c40c:	f7f5 f860 	bl	80014d0 <HAL_TIM_PeriodElapsedCallback>
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+    }
+  }
+  /* TIM Break input event */
+  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
+ 800c410:	687b      	ldr	r3, [r7, #4]
+ 800c412:	681b      	ldr	r3, [r3, #0]
+ 800c414:	691b      	ldr	r3, [r3, #16]
+ 800c416:	f003 0380 	and.w	r3, r3, #128	; 0x80
+ 800c41a:	2b80      	cmp	r3, #128	; 0x80
+ 800c41c:	d10e      	bne.n	800c43c <HAL_TIM_IRQHandler+0x1b0>
+  {
+    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET)
+ 800c41e:	687b      	ldr	r3, [r7, #4]
+ 800c420:	681b      	ldr	r3, [r3, #0]
+ 800c422:	68db      	ldr	r3, [r3, #12]
+ 800c424:	f003 0380 	and.w	r3, r3, #128	; 0x80
+ 800c428:	2b80      	cmp	r3, #128	; 0x80
+ 800c42a:	d107      	bne.n	800c43c <HAL_TIM_IRQHandler+0x1b0>
+    {
+      __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
+ 800c42c:	687b      	ldr	r3, [r7, #4]
+ 800c42e:	681b      	ldr	r3, [r3, #0]
+ 800c430:	f06f 0280 	mvn.w	r2, #128	; 0x80
+ 800c434:	611a      	str	r2, [r3, #16]
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+      htim->BreakCallback(htim);
+#else
+      HAL_TIMEx_BreakCallback(htim);
+ 800c436:	6878      	ldr	r0, [r7, #4]
+ 800c438:	f000 fb52 	bl	800cae0 <HAL_TIMEx_BreakCallback>
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+    }
+  }
+  /* TIM Break2 input event */
+  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK2) != RESET)
+ 800c43c:	687b      	ldr	r3, [r7, #4]
+ 800c43e:	681b      	ldr	r3, [r3, #0]
+ 800c440:	691b      	ldr	r3, [r3, #16]
+ 800c442:	f403 7380 	and.w	r3, r3, #256	; 0x100
+ 800c446:	f5b3 7f80 	cmp.w	r3, #256	; 0x100
+ 800c44a:	d10e      	bne.n	800c46a <HAL_TIM_IRQHandler+0x1de>
+  {
+    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET)
+ 800c44c:	687b      	ldr	r3, [r7, #4]
+ 800c44e:	681b      	ldr	r3, [r3, #0]
+ 800c450:	68db      	ldr	r3, [r3, #12]
+ 800c452:	f003 0380 	and.w	r3, r3, #128	; 0x80
+ 800c456:	2b80      	cmp	r3, #128	; 0x80
+ 800c458:	d107      	bne.n	800c46a <HAL_TIM_IRQHandler+0x1de>
+    {
+      __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2);
+ 800c45a:	687b      	ldr	r3, [r7, #4]
+ 800c45c:	681b      	ldr	r3, [r3, #0]
+ 800c45e:	f46f 7280 	mvn.w	r2, #256	; 0x100
+ 800c462:	611a      	str	r2, [r3, #16]
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+      htim->Break2Callback(htim);
+#else
+      HAL_TIMEx_Break2Callback(htim);
+ 800c464:	6878      	ldr	r0, [r7, #4]
+ 800c466:	f000 fb45 	bl	800caf4 <HAL_TIMEx_Break2Callback>
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+    }
+  }
+  /* TIM Trigger detection event */
+  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
+ 800c46a:	687b      	ldr	r3, [r7, #4]
+ 800c46c:	681b      	ldr	r3, [r3, #0]
+ 800c46e:	691b      	ldr	r3, [r3, #16]
+ 800c470:	f003 0340 	and.w	r3, r3, #64	; 0x40
+ 800c474:	2b40      	cmp	r3, #64	; 0x40
+ 800c476:	d10e      	bne.n	800c496 <HAL_TIM_IRQHandler+0x20a>
+  {
+    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET)
+ 800c478:	687b      	ldr	r3, [r7, #4]
+ 800c47a:	681b      	ldr	r3, [r3, #0]
+ 800c47c:	68db      	ldr	r3, [r3, #12]
+ 800c47e:	f003 0340 	and.w	r3, r3, #64	; 0x40
+ 800c482:	2b40      	cmp	r3, #64	; 0x40
+ 800c484:	d107      	bne.n	800c496 <HAL_TIM_IRQHandler+0x20a>
+    {
+      __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
+ 800c486:	687b      	ldr	r3, [r7, #4]
+ 800c488:	681b      	ldr	r3, [r3, #0]
+ 800c48a:	f06f 0240 	mvn.w	r2, #64	; 0x40
+ 800c48e:	611a      	str	r2, [r3, #16]
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+      htim->TriggerCallback(htim);
+#else
+      HAL_TIM_TriggerCallback(htim);
+ 800c490:	6878      	ldr	r0, [r7, #4]
+ 800c492:	f000 f931 	bl	800c6f8 <HAL_TIM_TriggerCallback>
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+    }
+  }
+  /* TIM commutation event */
+  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
+ 800c496:	687b      	ldr	r3, [r7, #4]
+ 800c498:	681b      	ldr	r3, [r3, #0]
+ 800c49a:	691b      	ldr	r3, [r3, #16]
+ 800c49c:	f003 0320 	and.w	r3, r3, #32
+ 800c4a0:	2b20      	cmp	r3, #32
+ 800c4a2:	d10e      	bne.n	800c4c2 <HAL_TIM_IRQHandler+0x236>
+  {
+    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) != RESET)
+ 800c4a4:	687b      	ldr	r3, [r7, #4]
+ 800c4a6:	681b      	ldr	r3, [r3, #0]
+ 800c4a8:	68db      	ldr	r3, [r3, #12]
+ 800c4aa:	f003 0320 	and.w	r3, r3, #32
+ 800c4ae:	2b20      	cmp	r3, #32
+ 800c4b0:	d107      	bne.n	800c4c2 <HAL_TIM_IRQHandler+0x236>
+    {
+      __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
+ 800c4b2:	687b      	ldr	r3, [r7, #4]
+ 800c4b4:	681b      	ldr	r3, [r3, #0]
+ 800c4b6:	f06f 0220 	mvn.w	r2, #32
+ 800c4ba:	611a      	str	r2, [r3, #16]
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+      htim->CommutationCallback(htim);
+#else
+      HAL_TIMEx_CommutCallback(htim);
+ 800c4bc:	6878      	ldr	r0, [r7, #4]
+ 800c4be:	f000 fb05 	bl	800cacc <HAL_TIMEx_CommutCallback>
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+    }
+  }
+}
+ 800c4c2:	bf00      	nop
+ 800c4c4:	3708      	adds	r7, #8
+ 800c4c6:	46bd      	mov	sp, r7
+ 800c4c8:	bd80      	pop	{r7, pc}
+	...
+
+0800c4cc <HAL_TIM_ConfigClockSource>:
+  * @param  sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that
+  *         contains the clock source information for the TIM peripheral.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig)
+{
+ 800c4cc:	b580      	push	{r7, lr}
+ 800c4ce:	b084      	sub	sp, #16
+ 800c4d0:	af00      	add	r7, sp, #0
+ 800c4d2:	6078      	str	r0, [r7, #4]
+ 800c4d4:	6039      	str	r1, [r7, #0]
+  HAL_StatusTypeDef status = HAL_OK;
+ 800c4d6:	2300      	movs	r3, #0
+ 800c4d8:	73fb      	strb	r3, [r7, #15]
+  uint32_t tmpsmcr;
+
+  /* Process Locked */
+  __HAL_LOCK(htim);
+ 800c4da:	687b      	ldr	r3, [r7, #4]
+ 800c4dc:	f893 303c 	ldrb.w	r3, [r3, #60]	; 0x3c
+ 800c4e0:	2b01      	cmp	r3, #1
+ 800c4e2:	d101      	bne.n	800c4e8 <HAL_TIM_ConfigClockSource+0x1c>
+ 800c4e4:	2302      	movs	r3, #2
+ 800c4e6:	e0dc      	b.n	800c6a2 <HAL_TIM_ConfigClockSource+0x1d6>
+ 800c4e8:	687b      	ldr	r3, [r7, #4]
+ 800c4ea:	2201      	movs	r2, #1
+ 800c4ec:	f883 203c 	strb.w	r2, [r3, #60]	; 0x3c
+
+  htim->State = HAL_TIM_STATE_BUSY;
+ 800c4f0:	687b      	ldr	r3, [r7, #4]
+ 800c4f2:	2202      	movs	r2, #2
+ 800c4f4:	f883 203d 	strb.w	r2, [r3, #61]	; 0x3d
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
+
+  /* Reset the SMS, TS, ECE, ETPS and ETRF bits */
+  tmpsmcr = htim->Instance->SMCR;
+ 800c4f8:	687b      	ldr	r3, [r7, #4]
+ 800c4fa:	681b      	ldr	r3, [r3, #0]
+ 800c4fc:	689b      	ldr	r3, [r3, #8]
+ 800c4fe:	60bb      	str	r3, [r7, #8]
+  tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
+ 800c500:	68ba      	ldr	r2, [r7, #8]
+ 800c502:	4b6a      	ldr	r3, [pc, #424]	; (800c6ac <HAL_TIM_ConfigClockSource+0x1e0>)
+ 800c504:	4013      	ands	r3, r2
+ 800c506:	60bb      	str	r3, [r7, #8]
+  tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
+ 800c508:	68bb      	ldr	r3, [r7, #8]
+ 800c50a:	f423 437f 	bic.w	r3, r3, #65280	; 0xff00
+ 800c50e:	60bb      	str	r3, [r7, #8]
+  htim->Instance->SMCR = tmpsmcr;
+ 800c510:	687b      	ldr	r3, [r7, #4]
+ 800c512:	681b      	ldr	r3, [r3, #0]
+ 800c514:	68ba      	ldr	r2, [r7, #8]
+ 800c516:	609a      	str	r2, [r3, #8]
+
+  switch (sClockSourceConfig->ClockSource)
+ 800c518:	683b      	ldr	r3, [r7, #0]
+ 800c51a:	681b      	ldr	r3, [r3, #0]
+ 800c51c:	4a64      	ldr	r2, [pc, #400]	; (800c6b0 <HAL_TIM_ConfigClockSource+0x1e4>)
+ 800c51e:	4293      	cmp	r3, r2
+ 800c520:	f000 80a9 	beq.w	800c676 <HAL_TIM_ConfigClockSource+0x1aa>
+ 800c524:	4a62      	ldr	r2, [pc, #392]	; (800c6b0 <HAL_TIM_ConfigClockSource+0x1e4>)
+ 800c526:	4293      	cmp	r3, r2
+ 800c528:	f200 80ae 	bhi.w	800c688 <HAL_TIM_ConfigClockSource+0x1bc>
+ 800c52c:	4a61      	ldr	r2, [pc, #388]	; (800c6b4 <HAL_TIM_ConfigClockSource+0x1e8>)
+ 800c52e:	4293      	cmp	r3, r2
+ 800c530:	f000 80a1 	beq.w	800c676 <HAL_TIM_ConfigClockSource+0x1aa>
+ 800c534:	4a5f      	ldr	r2, [pc, #380]	; (800c6b4 <HAL_TIM_ConfigClockSource+0x1e8>)
+ 800c536:	4293      	cmp	r3, r2
+ 800c538:	f200 80a6 	bhi.w	800c688 <HAL_TIM_ConfigClockSource+0x1bc>
+ 800c53c:	4a5e      	ldr	r2, [pc, #376]	; (800c6b8 <HAL_TIM_ConfigClockSource+0x1ec>)
+ 800c53e:	4293      	cmp	r3, r2
+ 800c540:	f000 8099 	beq.w	800c676 <HAL_TIM_ConfigClockSource+0x1aa>
+ 800c544:	4a5c      	ldr	r2, [pc, #368]	; (800c6b8 <HAL_TIM_ConfigClockSource+0x1ec>)
+ 800c546:	4293      	cmp	r3, r2
+ 800c548:	f200 809e 	bhi.w	800c688 <HAL_TIM_ConfigClockSource+0x1bc>
+ 800c54c:	f1b3 1f10 	cmp.w	r3, #1048592	; 0x100010
+ 800c550:	f000 8091 	beq.w	800c676 <HAL_TIM_ConfigClockSource+0x1aa>
+ 800c554:	f1b3 1f10 	cmp.w	r3, #1048592	; 0x100010
+ 800c558:	f200 8096 	bhi.w	800c688 <HAL_TIM_ConfigClockSource+0x1bc>
+ 800c55c:	f5b3 1f80 	cmp.w	r3, #1048576	; 0x100000
+ 800c560:	f000 8089 	beq.w	800c676 <HAL_TIM_ConfigClockSource+0x1aa>
+ 800c564:	f5b3 1f80 	cmp.w	r3, #1048576	; 0x100000
+ 800c568:	f200 808e 	bhi.w	800c688 <HAL_TIM_ConfigClockSource+0x1bc>
+ 800c56c:	f5b3 5f00 	cmp.w	r3, #8192	; 0x2000
+ 800c570:	d03e      	beq.n	800c5f0 <HAL_TIM_ConfigClockSource+0x124>
+ 800c572:	f5b3 5f00 	cmp.w	r3, #8192	; 0x2000
+ 800c576:	f200 8087 	bhi.w	800c688 <HAL_TIM_ConfigClockSource+0x1bc>
+ 800c57a:	f5b3 5f80 	cmp.w	r3, #4096	; 0x1000
+ 800c57e:	f000 8086 	beq.w	800c68e <HAL_TIM_ConfigClockSource+0x1c2>
+ 800c582:	f5b3 5f80 	cmp.w	r3, #4096	; 0x1000
+ 800c586:	d87f      	bhi.n	800c688 <HAL_TIM_ConfigClockSource+0x1bc>
+ 800c588:	2b70      	cmp	r3, #112	; 0x70
+ 800c58a:	d01a      	beq.n	800c5c2 <HAL_TIM_ConfigClockSource+0xf6>
+ 800c58c:	2b70      	cmp	r3, #112	; 0x70
+ 800c58e:	d87b      	bhi.n	800c688 <HAL_TIM_ConfigClockSource+0x1bc>
+ 800c590:	2b60      	cmp	r3, #96	; 0x60
+ 800c592:	d050      	beq.n	800c636 <HAL_TIM_ConfigClockSource+0x16a>
+ 800c594:	2b60      	cmp	r3, #96	; 0x60
+ 800c596:	d877      	bhi.n	800c688 <HAL_TIM_ConfigClockSource+0x1bc>
+ 800c598:	2b50      	cmp	r3, #80	; 0x50
+ 800c59a:	d03c      	beq.n	800c616 <HAL_TIM_ConfigClockSource+0x14a>
+ 800c59c:	2b50      	cmp	r3, #80	; 0x50
+ 800c59e:	d873      	bhi.n	800c688 <HAL_TIM_ConfigClockSource+0x1bc>
+ 800c5a0:	2b40      	cmp	r3, #64	; 0x40
+ 800c5a2:	d058      	beq.n	800c656 <HAL_TIM_ConfigClockSource+0x18a>
+ 800c5a4:	2b40      	cmp	r3, #64	; 0x40
+ 800c5a6:	d86f      	bhi.n	800c688 <HAL_TIM_ConfigClockSource+0x1bc>
+ 800c5a8:	2b30      	cmp	r3, #48	; 0x30
+ 800c5aa:	d064      	beq.n	800c676 <HAL_TIM_ConfigClockSource+0x1aa>
+ 800c5ac:	2b30      	cmp	r3, #48	; 0x30
+ 800c5ae:	d86b      	bhi.n	800c688 <HAL_TIM_ConfigClockSource+0x1bc>
+ 800c5b0:	2b20      	cmp	r3, #32
+ 800c5b2:	d060      	beq.n	800c676 <HAL_TIM_ConfigClockSource+0x1aa>
+ 800c5b4:	2b20      	cmp	r3, #32
+ 800c5b6:	d867      	bhi.n	800c688 <HAL_TIM_ConfigClockSource+0x1bc>
+ 800c5b8:	2b00      	cmp	r3, #0
+ 800c5ba:	d05c      	beq.n	800c676 <HAL_TIM_ConfigClockSource+0x1aa>
+ 800c5bc:	2b10      	cmp	r3, #16
+ 800c5be:	d05a      	beq.n	800c676 <HAL_TIM_ConfigClockSource+0x1aa>
+ 800c5c0:	e062      	b.n	800c688 <HAL_TIM_ConfigClockSource+0x1bc>
+      assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
+      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+
+      /* Configure the ETR Clock source */
+      TIM_ETR_SetConfig(htim->Instance,
+ 800c5c2:	687b      	ldr	r3, [r7, #4]
+ 800c5c4:	6818      	ldr	r0, [r3, #0]
+                        sClockSourceConfig->ClockPrescaler,
+ 800c5c6:	683b      	ldr	r3, [r7, #0]
+ 800c5c8:	6899      	ldr	r1, [r3, #8]
+                        sClockSourceConfig->ClockPolarity,
+ 800c5ca:	683b      	ldr	r3, [r7, #0]
+ 800c5cc:	685a      	ldr	r2, [r3, #4]
+                        sClockSourceConfig->ClockFilter);
+ 800c5ce:	683b      	ldr	r3, [r7, #0]
+ 800c5d0:	68db      	ldr	r3, [r3, #12]
+      TIM_ETR_SetConfig(htim->Instance,
+ 800c5d2:	f000 f9bf 	bl	800c954 <TIM_ETR_SetConfig>
+
+      /* Select the External clock mode1 and the ETRF trigger */
+      tmpsmcr = htim->Instance->SMCR;
+ 800c5d6:	687b      	ldr	r3, [r7, #4]
+ 800c5d8:	681b      	ldr	r3, [r3, #0]
+ 800c5da:	689b      	ldr	r3, [r3, #8]
+ 800c5dc:	60bb      	str	r3, [r7, #8]
+      tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
+ 800c5de:	68bb      	ldr	r3, [r7, #8]
+ 800c5e0:	f043 0377 	orr.w	r3, r3, #119	; 0x77
+ 800c5e4:	60bb      	str	r3, [r7, #8]
+      /* Write to TIMx SMCR */
+      htim->Instance->SMCR = tmpsmcr;
+ 800c5e6:	687b      	ldr	r3, [r7, #4]
+ 800c5e8:	681b      	ldr	r3, [r3, #0]
+ 800c5ea:	68ba      	ldr	r2, [r7, #8]
+ 800c5ec:	609a      	str	r2, [r3, #8]
+      break;
+ 800c5ee:	e04f      	b.n	800c690 <HAL_TIM_ConfigClockSource+0x1c4>
+      assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
+      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+
+      /* Configure the ETR Clock source */
+      TIM_ETR_SetConfig(htim->Instance,
+ 800c5f0:	687b      	ldr	r3, [r7, #4]
+ 800c5f2:	6818      	ldr	r0, [r3, #0]
+                        sClockSourceConfig->ClockPrescaler,
+ 800c5f4:	683b      	ldr	r3, [r7, #0]
+ 800c5f6:	6899      	ldr	r1, [r3, #8]
+                        sClockSourceConfig->ClockPolarity,
+ 800c5f8:	683b      	ldr	r3, [r7, #0]
+ 800c5fa:	685a      	ldr	r2, [r3, #4]
+                        sClockSourceConfig->ClockFilter);
+ 800c5fc:	683b      	ldr	r3, [r7, #0]
+ 800c5fe:	68db      	ldr	r3, [r3, #12]
+      TIM_ETR_SetConfig(htim->Instance,
+ 800c600:	f000 f9a8 	bl	800c954 <TIM_ETR_SetConfig>
+      /* Enable the External clock mode2 */
+      htim->Instance->SMCR |= TIM_SMCR_ECE;
+ 800c604:	687b      	ldr	r3, [r7, #4]
+ 800c606:	681b      	ldr	r3, [r3, #0]
+ 800c608:	689a      	ldr	r2, [r3, #8]
+ 800c60a:	687b      	ldr	r3, [r7, #4]
+ 800c60c:	681b      	ldr	r3, [r3, #0]
+ 800c60e:	f442 4280 	orr.w	r2, r2, #16384	; 0x4000
+ 800c612:	609a      	str	r2, [r3, #8]
+      break;
+ 800c614:	e03c      	b.n	800c690 <HAL_TIM_ConfigClockSource+0x1c4>
+
+      /* Check TI1 input conditioning related parameters */
+      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+
+      TIM_TI1_ConfigInputStage(htim->Instance,
+ 800c616:	687b      	ldr	r3, [r7, #4]
+ 800c618:	6818      	ldr	r0, [r3, #0]
+                               sClockSourceConfig->ClockPolarity,
+ 800c61a:	683b      	ldr	r3, [r7, #0]
+ 800c61c:	6859      	ldr	r1, [r3, #4]
+                               sClockSourceConfig->ClockFilter);
+ 800c61e:	683b      	ldr	r3, [r7, #0]
+ 800c620:	68db      	ldr	r3, [r3, #12]
+      TIM_TI1_ConfigInputStage(htim->Instance,
+ 800c622:	461a      	mov	r2, r3
+ 800c624:	f000 f918 	bl	800c858 <TIM_TI1_ConfigInputStage>
+      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
+ 800c628:	687b      	ldr	r3, [r7, #4]
+ 800c62a:	681b      	ldr	r3, [r3, #0]
+ 800c62c:	2150      	movs	r1, #80	; 0x50
+ 800c62e:	4618      	mov	r0, r3
+ 800c630:	f000 f972 	bl	800c918 <TIM_ITRx_SetConfig>
+      break;
+ 800c634:	e02c      	b.n	800c690 <HAL_TIM_ConfigClockSource+0x1c4>
+
+      /* Check TI2 input conditioning related parameters */
+      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+
+      TIM_TI2_ConfigInputStage(htim->Instance,
+ 800c636:	687b      	ldr	r3, [r7, #4]
+ 800c638:	6818      	ldr	r0, [r3, #0]
+                               sClockSourceConfig->ClockPolarity,
+ 800c63a:	683b      	ldr	r3, [r7, #0]
+ 800c63c:	6859      	ldr	r1, [r3, #4]
+                               sClockSourceConfig->ClockFilter);
+ 800c63e:	683b      	ldr	r3, [r7, #0]
+ 800c640:	68db      	ldr	r3, [r3, #12]
+      TIM_TI2_ConfigInputStage(htim->Instance,
+ 800c642:	461a      	mov	r2, r3
+ 800c644:	f000 f937 	bl	800c8b6 <TIM_TI2_ConfigInputStage>
+      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
+ 800c648:	687b      	ldr	r3, [r7, #4]
+ 800c64a:	681b      	ldr	r3, [r3, #0]
+ 800c64c:	2160      	movs	r1, #96	; 0x60
+ 800c64e:	4618      	mov	r0, r3
+ 800c650:	f000 f962 	bl	800c918 <TIM_ITRx_SetConfig>
+      break;
+ 800c654:	e01c      	b.n	800c690 <HAL_TIM_ConfigClockSource+0x1c4>
+
+      /* Check TI1 input conditioning related parameters */
+      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+
+      TIM_TI1_ConfigInputStage(htim->Instance,
+ 800c656:	687b      	ldr	r3, [r7, #4]
+ 800c658:	6818      	ldr	r0, [r3, #0]
+                               sClockSourceConfig->ClockPolarity,
+ 800c65a:	683b      	ldr	r3, [r7, #0]
+ 800c65c:	6859      	ldr	r1, [r3, #4]
+                               sClockSourceConfig->ClockFilter);
+ 800c65e:	683b      	ldr	r3, [r7, #0]
+ 800c660:	68db      	ldr	r3, [r3, #12]
+      TIM_TI1_ConfigInputStage(htim->Instance,
+ 800c662:	461a      	mov	r2, r3
+ 800c664:	f000 f8f8 	bl	800c858 <TIM_TI1_ConfigInputStage>
+      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
+ 800c668:	687b      	ldr	r3, [r7, #4]
+ 800c66a:	681b      	ldr	r3, [r3, #0]
+ 800c66c:	2140      	movs	r1, #64	; 0x40
+ 800c66e:	4618      	mov	r0, r3
+ 800c670:	f000 f952 	bl	800c918 <TIM_ITRx_SetConfig>
+      break;
+ 800c674:	e00c      	b.n	800c690 <HAL_TIM_ConfigClockSource+0x1c4>
+    case TIM_CLOCKSOURCE_ITR8:
+    {
+      /* Check whether or not the timer instance supports internal trigger input */
+      assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
+
+      TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
+ 800c676:	687b      	ldr	r3, [r7, #4]
+ 800c678:	681a      	ldr	r2, [r3, #0]
+ 800c67a:	683b      	ldr	r3, [r7, #0]
+ 800c67c:	681b      	ldr	r3, [r3, #0]
+ 800c67e:	4619      	mov	r1, r3
+ 800c680:	4610      	mov	r0, r2
+ 800c682:	f000 f949 	bl	800c918 <TIM_ITRx_SetConfig>
+      break;
+ 800c686:	e003      	b.n	800c690 <HAL_TIM_ConfigClockSource+0x1c4>
+    }
+
+    default:
+      status = HAL_ERROR;
+ 800c688:	2301      	movs	r3, #1
+ 800c68a:	73fb      	strb	r3, [r7, #15]
+      break;
+ 800c68c:	e000      	b.n	800c690 <HAL_TIM_ConfigClockSource+0x1c4>
+      break;
+ 800c68e:	bf00      	nop
+  }
+  htim->State = HAL_TIM_STATE_READY;
+ 800c690:	687b      	ldr	r3, [r7, #4]
+ 800c692:	2201      	movs	r2, #1
+ 800c694:	f883 203d 	strb.w	r2, [r3, #61]	; 0x3d
+
+  __HAL_UNLOCK(htim);
+ 800c698:	687b      	ldr	r3, [r7, #4]
+ 800c69a:	2200      	movs	r2, #0
+ 800c69c:	f883 203c 	strb.w	r2, [r3, #60]	; 0x3c
+
+  return status;
+ 800c6a0:	7bfb      	ldrb	r3, [r7, #15]
+}
+ 800c6a2:	4618      	mov	r0, r3
+ 800c6a4:	3710      	adds	r7, #16
+ 800c6a6:	46bd      	mov	sp, r7
+ 800c6a8:	bd80      	pop	{r7, pc}
+ 800c6aa:	bf00      	nop
+ 800c6ac:	ffceff88 	.word	0xffceff88
+ 800c6b0:	00100040 	.word	0x00100040
+ 800c6b4:	00100030 	.word	0x00100030
+ 800c6b8:	00100020 	.word	0x00100020
+
+0800c6bc <HAL_TIM_OC_DelayElapsedCallback>:
+  * @brief  Output Compare callback in non-blocking mode
+  * @param  htim TIM OC handle
+  * @retval None
+  */
+__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
+{
+ 800c6bc:	b480      	push	{r7}
+ 800c6be:	b083      	sub	sp, #12
+ 800c6c0:	af00      	add	r7, sp, #0
+ 800c6c2:	6078      	str	r0, [r7, #4]
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
+   */
+}
+ 800c6c4:	bf00      	nop
+ 800c6c6:	370c      	adds	r7, #12
+ 800c6c8:	46bd      	mov	sp, r7
+ 800c6ca:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 800c6ce:	4770      	bx	lr
+
+0800c6d0 <HAL_TIM_IC_CaptureCallback>:
+  * @brief  Input Capture callback in non-blocking mode
+  * @param  htim TIM IC handle
+  * @retval None
+  */
+__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
+{
+ 800c6d0:	b480      	push	{r7}
+ 800c6d2:	b083      	sub	sp, #12
+ 800c6d4:	af00      	add	r7, sp, #0
+ 800c6d6:	6078      	str	r0, [r7, #4]
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_IC_CaptureCallback could be implemented in the user file
+   */
+}
+ 800c6d8:	bf00      	nop
+ 800c6da:	370c      	adds	r7, #12
+ 800c6dc:	46bd      	mov	sp, r7
+ 800c6de:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 800c6e2:	4770      	bx	lr
+
+0800c6e4 <HAL_TIM_PWM_PulseFinishedCallback>:
+  * @brief  PWM Pulse finished callback in non-blocking mode
+  * @param  htim TIM handle
+  * @retval None
+  */
+__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
+{
+ 800c6e4:	b480      	push	{r7}
+ 800c6e6:	b083      	sub	sp, #12
+ 800c6e8:	af00      	add	r7, sp, #0
+ 800c6ea:	6078      	str	r0, [r7, #4]
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
+   */
+}
+ 800c6ec:	bf00      	nop
+ 800c6ee:	370c      	adds	r7, #12
+ 800c6f0:	46bd      	mov	sp, r7
+ 800c6f2:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 800c6f6:	4770      	bx	lr
+
+0800c6f8 <HAL_TIM_TriggerCallback>:
+  * @brief  Hall Trigger detection callback in non-blocking mode
+  * @param  htim TIM handle
+  * @retval None
+  */
+__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
+{
+ 800c6f8:	b480      	push	{r7}
+ 800c6fa:	b083      	sub	sp, #12
+ 800c6fc:	af00      	add	r7, sp, #0
+ 800c6fe:	6078      	str	r0, [r7, #4]
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_TriggerCallback could be implemented in the user file
+   */
+}
+ 800c700:	bf00      	nop
+ 800c702:	370c      	adds	r7, #12
+ 800c704:	46bd      	mov	sp, r7
+ 800c706:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 800c70a:	4770      	bx	lr
+
+0800c70c <TIM_Base_SetConfig>:
+  * @param  TIMx TIM peripheral
+  * @param  Structure TIM Base configuration structure
+  * @retval None
+  */
+void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure)
+{
+ 800c70c:	b480      	push	{r7}
+ 800c70e:	b085      	sub	sp, #20
+ 800c710:	af00      	add	r7, sp, #0
+ 800c712:	6078      	str	r0, [r7, #4]
+ 800c714:	6039      	str	r1, [r7, #0]
+  uint32_t tmpcr1;
+  tmpcr1 = TIMx->CR1;
+ 800c716:	687b      	ldr	r3, [r7, #4]
+ 800c718:	681b      	ldr	r3, [r3, #0]
+ 800c71a:	60fb      	str	r3, [r7, #12]
+
+  /* Set TIM Time Base Unit parameters ---------------------------------------*/
+  if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
+ 800c71c:	687b      	ldr	r3, [r7, #4]
+ 800c71e:	4a44      	ldr	r2, [pc, #272]	; (800c830 <TIM_Base_SetConfig+0x124>)
+ 800c720:	4293      	cmp	r3, r2
+ 800c722:	d013      	beq.n	800c74c <TIM_Base_SetConfig+0x40>
+ 800c724:	687b      	ldr	r3, [r7, #4]
+ 800c726:	f1b3 4f80 	cmp.w	r3, #1073741824	; 0x40000000
+ 800c72a:	d00f      	beq.n	800c74c <TIM_Base_SetConfig+0x40>
+ 800c72c:	687b      	ldr	r3, [r7, #4]
+ 800c72e:	4a41      	ldr	r2, [pc, #260]	; (800c834 <TIM_Base_SetConfig+0x128>)
+ 800c730:	4293      	cmp	r3, r2
+ 800c732:	d00b      	beq.n	800c74c <TIM_Base_SetConfig+0x40>
+ 800c734:	687b      	ldr	r3, [r7, #4]
+ 800c736:	4a40      	ldr	r2, [pc, #256]	; (800c838 <TIM_Base_SetConfig+0x12c>)
+ 800c738:	4293      	cmp	r3, r2
+ 800c73a:	d007      	beq.n	800c74c <TIM_Base_SetConfig+0x40>
+ 800c73c:	687b      	ldr	r3, [r7, #4]
+ 800c73e:	4a3f      	ldr	r2, [pc, #252]	; (800c83c <TIM_Base_SetConfig+0x130>)
+ 800c740:	4293      	cmp	r3, r2
+ 800c742:	d003      	beq.n	800c74c <TIM_Base_SetConfig+0x40>
+ 800c744:	687b      	ldr	r3, [r7, #4]
+ 800c746:	4a3e      	ldr	r2, [pc, #248]	; (800c840 <TIM_Base_SetConfig+0x134>)
+ 800c748:	4293      	cmp	r3, r2
+ 800c74a:	d108      	bne.n	800c75e <TIM_Base_SetConfig+0x52>
+  {
+    /* Select the Counter Mode */
+    tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
+ 800c74c:	68fb      	ldr	r3, [r7, #12]
+ 800c74e:	f023 0370 	bic.w	r3, r3, #112	; 0x70
+ 800c752:	60fb      	str	r3, [r7, #12]
+    tmpcr1 |= Structure->CounterMode;
+ 800c754:	683b      	ldr	r3, [r7, #0]
+ 800c756:	685b      	ldr	r3, [r3, #4]
+ 800c758:	68fa      	ldr	r2, [r7, #12]
+ 800c75a:	4313      	orrs	r3, r2
+ 800c75c:	60fb      	str	r3, [r7, #12]
+  }
+
+  if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
+ 800c75e:	687b      	ldr	r3, [r7, #4]
+ 800c760:	4a33      	ldr	r2, [pc, #204]	; (800c830 <TIM_Base_SetConfig+0x124>)
+ 800c762:	4293      	cmp	r3, r2
+ 800c764:	d027      	beq.n	800c7b6 <TIM_Base_SetConfig+0xaa>
+ 800c766:	687b      	ldr	r3, [r7, #4]
+ 800c768:	f1b3 4f80 	cmp.w	r3, #1073741824	; 0x40000000
+ 800c76c:	d023      	beq.n	800c7b6 <TIM_Base_SetConfig+0xaa>
+ 800c76e:	687b      	ldr	r3, [r7, #4]
+ 800c770:	4a30      	ldr	r2, [pc, #192]	; (800c834 <TIM_Base_SetConfig+0x128>)
+ 800c772:	4293      	cmp	r3, r2
+ 800c774:	d01f      	beq.n	800c7b6 <TIM_Base_SetConfig+0xaa>
+ 800c776:	687b      	ldr	r3, [r7, #4]
+ 800c778:	4a2f      	ldr	r2, [pc, #188]	; (800c838 <TIM_Base_SetConfig+0x12c>)
+ 800c77a:	4293      	cmp	r3, r2
+ 800c77c:	d01b      	beq.n	800c7b6 <TIM_Base_SetConfig+0xaa>
+ 800c77e:	687b      	ldr	r3, [r7, #4]
+ 800c780:	4a2e      	ldr	r2, [pc, #184]	; (800c83c <TIM_Base_SetConfig+0x130>)
+ 800c782:	4293      	cmp	r3, r2
+ 800c784:	d017      	beq.n	800c7b6 <TIM_Base_SetConfig+0xaa>
+ 800c786:	687b      	ldr	r3, [r7, #4]
+ 800c788:	4a2d      	ldr	r2, [pc, #180]	; (800c840 <TIM_Base_SetConfig+0x134>)
+ 800c78a:	4293      	cmp	r3, r2
+ 800c78c:	d013      	beq.n	800c7b6 <TIM_Base_SetConfig+0xaa>
+ 800c78e:	687b      	ldr	r3, [r7, #4]
+ 800c790:	4a2c      	ldr	r2, [pc, #176]	; (800c844 <TIM_Base_SetConfig+0x138>)
+ 800c792:	4293      	cmp	r3, r2
+ 800c794:	d00f      	beq.n	800c7b6 <TIM_Base_SetConfig+0xaa>
+ 800c796:	687b      	ldr	r3, [r7, #4]
+ 800c798:	4a2b      	ldr	r2, [pc, #172]	; (800c848 <TIM_Base_SetConfig+0x13c>)
+ 800c79a:	4293      	cmp	r3, r2
+ 800c79c:	d00b      	beq.n	800c7b6 <TIM_Base_SetConfig+0xaa>
+ 800c79e:	687b      	ldr	r3, [r7, #4]
+ 800c7a0:	4a2a      	ldr	r2, [pc, #168]	; (800c84c <TIM_Base_SetConfig+0x140>)
+ 800c7a2:	4293      	cmp	r3, r2
+ 800c7a4:	d007      	beq.n	800c7b6 <TIM_Base_SetConfig+0xaa>
+ 800c7a6:	687b      	ldr	r3, [r7, #4]
+ 800c7a8:	4a29      	ldr	r2, [pc, #164]	; (800c850 <TIM_Base_SetConfig+0x144>)
+ 800c7aa:	4293      	cmp	r3, r2
+ 800c7ac:	d003      	beq.n	800c7b6 <TIM_Base_SetConfig+0xaa>
+ 800c7ae:	687b      	ldr	r3, [r7, #4]
+ 800c7b0:	4a28      	ldr	r2, [pc, #160]	; (800c854 <TIM_Base_SetConfig+0x148>)
+ 800c7b2:	4293      	cmp	r3, r2
+ 800c7b4:	d108      	bne.n	800c7c8 <TIM_Base_SetConfig+0xbc>
+  {
+    /* Set the clock division */
+    tmpcr1 &= ~TIM_CR1_CKD;
+ 800c7b6:	68fb      	ldr	r3, [r7, #12]
+ 800c7b8:	f423 7340 	bic.w	r3, r3, #768	; 0x300
+ 800c7bc:	60fb      	str	r3, [r7, #12]
+    tmpcr1 |= (uint32_t)Structure->ClockDivision;
+ 800c7be:	683b      	ldr	r3, [r7, #0]
+ 800c7c0:	68db      	ldr	r3, [r3, #12]
+ 800c7c2:	68fa      	ldr	r2, [r7, #12]
+ 800c7c4:	4313      	orrs	r3, r2
+ 800c7c6:	60fb      	str	r3, [r7, #12]
+  }
+
+  /* Set the auto-reload preload */
+  MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
+ 800c7c8:	68fb      	ldr	r3, [r7, #12]
+ 800c7ca:	f023 0280 	bic.w	r2, r3, #128	; 0x80
+ 800c7ce:	683b      	ldr	r3, [r7, #0]
+ 800c7d0:	695b      	ldr	r3, [r3, #20]
+ 800c7d2:	4313      	orrs	r3, r2
+ 800c7d4:	60fb      	str	r3, [r7, #12]
+
+  TIMx->CR1 = tmpcr1;
+ 800c7d6:	687b      	ldr	r3, [r7, #4]
+ 800c7d8:	68fa      	ldr	r2, [r7, #12]
+ 800c7da:	601a      	str	r2, [r3, #0]
+
+  /* Set the Autoreload value */
+  TIMx->ARR = (uint32_t)Structure->Period ;
+ 800c7dc:	683b      	ldr	r3, [r7, #0]
+ 800c7de:	689a      	ldr	r2, [r3, #8]
+ 800c7e0:	687b      	ldr	r3, [r7, #4]
+ 800c7e2:	62da      	str	r2, [r3, #44]	; 0x2c
+
+  /* Set the Prescaler value */
+  TIMx->PSC = Structure->Prescaler;
+ 800c7e4:	683b      	ldr	r3, [r7, #0]
+ 800c7e6:	681a      	ldr	r2, [r3, #0]
+ 800c7e8:	687b      	ldr	r3, [r7, #4]
+ 800c7ea:	629a      	str	r2, [r3, #40]	; 0x28
+
+  if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
+ 800c7ec:	687b      	ldr	r3, [r7, #4]
+ 800c7ee:	4a10      	ldr	r2, [pc, #64]	; (800c830 <TIM_Base_SetConfig+0x124>)
+ 800c7f0:	4293      	cmp	r3, r2
+ 800c7f2:	d00f      	beq.n	800c814 <TIM_Base_SetConfig+0x108>
+ 800c7f4:	687b      	ldr	r3, [r7, #4]
+ 800c7f6:	4a12      	ldr	r2, [pc, #72]	; (800c840 <TIM_Base_SetConfig+0x134>)
+ 800c7f8:	4293      	cmp	r3, r2
+ 800c7fa:	d00b      	beq.n	800c814 <TIM_Base_SetConfig+0x108>
+ 800c7fc:	687b      	ldr	r3, [r7, #4]
+ 800c7fe:	4a11      	ldr	r2, [pc, #68]	; (800c844 <TIM_Base_SetConfig+0x138>)
+ 800c800:	4293      	cmp	r3, r2
+ 800c802:	d007      	beq.n	800c814 <TIM_Base_SetConfig+0x108>
+ 800c804:	687b      	ldr	r3, [r7, #4]
+ 800c806:	4a10      	ldr	r2, [pc, #64]	; (800c848 <TIM_Base_SetConfig+0x13c>)
+ 800c808:	4293      	cmp	r3, r2
+ 800c80a:	d003      	beq.n	800c814 <TIM_Base_SetConfig+0x108>
+ 800c80c:	687b      	ldr	r3, [r7, #4]
+ 800c80e:	4a0f      	ldr	r2, [pc, #60]	; (800c84c <TIM_Base_SetConfig+0x140>)
+ 800c810:	4293      	cmp	r3, r2
+ 800c812:	d103      	bne.n	800c81c <TIM_Base_SetConfig+0x110>
+  {
+    /* Set the Repetition Counter value */
+    TIMx->RCR = Structure->RepetitionCounter;
+ 800c814:	683b      	ldr	r3, [r7, #0]
+ 800c816:	691a      	ldr	r2, [r3, #16]
+ 800c818:	687b      	ldr	r3, [r7, #4]
+ 800c81a:	631a      	str	r2, [r3, #48]	; 0x30
+  }
+
+  /* Generate an update event to reload the Prescaler
+     and the repetition counter (only for advanced timer) value immediately */
+  TIMx->EGR = TIM_EGR_UG;
+ 800c81c:	687b      	ldr	r3, [r7, #4]
+ 800c81e:	2201      	movs	r2, #1
+ 800c820:	615a      	str	r2, [r3, #20]
+}
+ 800c822:	bf00      	nop
+ 800c824:	3714      	adds	r7, #20
+ 800c826:	46bd      	mov	sp, r7
+ 800c828:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 800c82c:	4770      	bx	lr
+ 800c82e:	bf00      	nop
+ 800c830:	40010000 	.word	0x40010000
+ 800c834:	40000400 	.word	0x40000400
+ 800c838:	40000800 	.word	0x40000800
+ 800c83c:	40000c00 	.word	0x40000c00
+ 800c840:	40010400 	.word	0x40010400
+ 800c844:	40014000 	.word	0x40014000
+ 800c848:	40014400 	.word	0x40014400
+ 800c84c:	40014800 	.word	0x40014800
+ 800c850:	4000e000 	.word	0x4000e000
+ 800c854:	4000e400 	.word	0x4000e400
+
+0800c858 <TIM_TI1_ConfigInputStage>:
+  * @param  TIM_ICFilter Specifies the Input Capture Filter.
+  *          This parameter must be a value between 0x00 and 0x0F.
+  * @retval None
+  */
+static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
+{
+ 800c858:	b480      	push	{r7}
+ 800c85a:	b087      	sub	sp, #28
+ 800c85c:	af00      	add	r7, sp, #0
+ 800c85e:	60f8      	str	r0, [r7, #12]
+ 800c860:	60b9      	str	r1, [r7, #8]
+ 800c862:	607a      	str	r2, [r7, #4]
+  uint32_t tmpccmr1;
+  uint32_t tmpccer;
+
+  /* Disable the Channel 1: Reset the CC1E Bit */
+  tmpccer = TIMx->CCER;
+ 800c864:	68fb      	ldr	r3, [r7, #12]
+ 800c866:	6a1b      	ldr	r3, [r3, #32]
+ 800c868:	617b      	str	r3, [r7, #20]
+  TIMx->CCER &= ~TIM_CCER_CC1E;
+ 800c86a:	68fb      	ldr	r3, [r7, #12]
+ 800c86c:	6a1b      	ldr	r3, [r3, #32]
+ 800c86e:	f023 0201 	bic.w	r2, r3, #1
+ 800c872:	68fb      	ldr	r3, [r7, #12]
+ 800c874:	621a      	str	r2, [r3, #32]
+  tmpccmr1 = TIMx->CCMR1;
+ 800c876:	68fb      	ldr	r3, [r7, #12]
+ 800c878:	699b      	ldr	r3, [r3, #24]
+ 800c87a:	613b      	str	r3, [r7, #16]
+
+  /* Set the filter */
+  tmpccmr1 &= ~TIM_CCMR1_IC1F;
+ 800c87c:	693b      	ldr	r3, [r7, #16]
+ 800c87e:	f023 03f0 	bic.w	r3, r3, #240	; 0xf0
+ 800c882:	613b      	str	r3, [r7, #16]
+  tmpccmr1 |= (TIM_ICFilter << 4U);
+ 800c884:	687b      	ldr	r3, [r7, #4]
+ 800c886:	011b      	lsls	r3, r3, #4
+ 800c888:	693a      	ldr	r2, [r7, #16]
+ 800c88a:	4313      	orrs	r3, r2
+ 800c88c:	613b      	str	r3, [r7, #16]
+
+  /* Select the Polarity and set the CC1E Bit */
+  tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
+ 800c88e:	697b      	ldr	r3, [r7, #20]
+ 800c890:	f023 030a 	bic.w	r3, r3, #10
+ 800c894:	617b      	str	r3, [r7, #20]
+  tmpccer |= TIM_ICPolarity;
+ 800c896:	697a      	ldr	r2, [r7, #20]
+ 800c898:	68bb      	ldr	r3, [r7, #8]
+ 800c89a:	4313      	orrs	r3, r2
+ 800c89c:	617b      	str	r3, [r7, #20]
+
+  /* Write to TIMx CCMR1 and CCER registers */
+  TIMx->CCMR1 = tmpccmr1;
+ 800c89e:	68fb      	ldr	r3, [r7, #12]
+ 800c8a0:	693a      	ldr	r2, [r7, #16]
+ 800c8a2:	619a      	str	r2, [r3, #24]
+  TIMx->CCER = tmpccer;
+ 800c8a4:	68fb      	ldr	r3, [r7, #12]
+ 800c8a6:	697a      	ldr	r2, [r7, #20]
+ 800c8a8:	621a      	str	r2, [r3, #32]
+}
+ 800c8aa:	bf00      	nop
+ 800c8ac:	371c      	adds	r7, #28
+ 800c8ae:	46bd      	mov	sp, r7
+ 800c8b0:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 800c8b4:	4770      	bx	lr
+
+0800c8b6 <TIM_TI2_ConfigInputStage>:
+  * @param  TIM_ICFilter Specifies the Input Capture Filter.
+  *          This parameter must be a value between 0x00 and 0x0F.
+  * @retval None
+  */
+static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
+{
+ 800c8b6:	b480      	push	{r7}
+ 800c8b8:	b087      	sub	sp, #28
+ 800c8ba:	af00      	add	r7, sp, #0
+ 800c8bc:	60f8      	str	r0, [r7, #12]
+ 800c8be:	60b9      	str	r1, [r7, #8]
+ 800c8c0:	607a      	str	r2, [r7, #4]
+  uint32_t tmpccmr1;
+  uint32_t tmpccer;
+
+  /* Disable the Channel 2: Reset the CC2E Bit */
+  TIMx->CCER &= ~TIM_CCER_CC2E;
+ 800c8c2:	68fb      	ldr	r3, [r7, #12]
+ 800c8c4:	6a1b      	ldr	r3, [r3, #32]
+ 800c8c6:	f023 0210 	bic.w	r2, r3, #16
+ 800c8ca:	68fb      	ldr	r3, [r7, #12]
+ 800c8cc:	621a      	str	r2, [r3, #32]
+  tmpccmr1 = TIMx->CCMR1;
+ 800c8ce:	68fb      	ldr	r3, [r7, #12]
+ 800c8d0:	699b      	ldr	r3, [r3, #24]
+ 800c8d2:	617b      	str	r3, [r7, #20]
+  tmpccer = TIMx->CCER;
+ 800c8d4:	68fb      	ldr	r3, [r7, #12]
+ 800c8d6:	6a1b      	ldr	r3, [r3, #32]
+ 800c8d8:	613b      	str	r3, [r7, #16]
+
+  /* Set the filter */
+  tmpccmr1 &= ~TIM_CCMR1_IC2F;
+ 800c8da:	697b      	ldr	r3, [r7, #20]
+ 800c8dc:	f423 4370 	bic.w	r3, r3, #61440	; 0xf000
+ 800c8e0:	617b      	str	r3, [r7, #20]
+  tmpccmr1 |= (TIM_ICFilter << 12U);
+ 800c8e2:	687b      	ldr	r3, [r7, #4]
+ 800c8e4:	031b      	lsls	r3, r3, #12
+ 800c8e6:	697a      	ldr	r2, [r7, #20]
+ 800c8e8:	4313      	orrs	r3, r2
+ 800c8ea:	617b      	str	r3, [r7, #20]
+
+  /* Select the Polarity and set the CC2E Bit */
+  tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
+ 800c8ec:	693b      	ldr	r3, [r7, #16]
+ 800c8ee:	f023 03a0 	bic.w	r3, r3, #160	; 0xa0
+ 800c8f2:	613b      	str	r3, [r7, #16]
+  tmpccer |= (TIM_ICPolarity << 4U);
+ 800c8f4:	68bb      	ldr	r3, [r7, #8]
+ 800c8f6:	011b      	lsls	r3, r3, #4
+ 800c8f8:	693a      	ldr	r2, [r7, #16]
+ 800c8fa:	4313      	orrs	r3, r2
+ 800c8fc:	613b      	str	r3, [r7, #16]
+
+  /* Write to TIMx CCMR1 and CCER registers */
+  TIMx->CCMR1 = tmpccmr1 ;
+ 800c8fe:	68fb      	ldr	r3, [r7, #12]
+ 800c900:	697a      	ldr	r2, [r7, #20]
+ 800c902:	619a      	str	r2, [r3, #24]
+  TIMx->CCER = tmpccer;
+ 800c904:	68fb      	ldr	r3, [r7, #12]
+ 800c906:	693a      	ldr	r2, [r7, #16]
+ 800c908:	621a      	str	r2, [r3, #32]
+}
+ 800c90a:	bf00      	nop
+ 800c90c:	371c      	adds	r7, #28
+ 800c90e:	46bd      	mov	sp, r7
+ 800c910:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 800c914:	4770      	bx	lr
+	...
+
+0800c918 <TIM_ITRx_SetConfig>:
+  *       (*)  Value not defined in all devices.
+  *
+  * @retval None
+  */
+static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource)
+{
+ 800c918:	b480      	push	{r7}
+ 800c91a:	b085      	sub	sp, #20
+ 800c91c:	af00      	add	r7, sp, #0
+ 800c91e:	6078      	str	r0, [r7, #4]
+ 800c920:	6039      	str	r1, [r7, #0]
+  uint32_t tmpsmcr;
+
+  /* Get the TIMx SMCR register value */
+  tmpsmcr = TIMx->SMCR;
+ 800c922:	687b      	ldr	r3, [r7, #4]
+ 800c924:	689b      	ldr	r3, [r3, #8]
+ 800c926:	60fb      	str	r3, [r7, #12]
+  /* Reset the TS Bits */
+  tmpsmcr &= ~TIM_SMCR_TS;
+ 800c928:	68fa      	ldr	r2, [r7, #12]
+ 800c92a:	4b09      	ldr	r3, [pc, #36]	; (800c950 <TIM_ITRx_SetConfig+0x38>)
+ 800c92c:	4013      	ands	r3, r2
+ 800c92e:	60fb      	str	r3, [r7, #12]
+  /* Set the Input Trigger source and the slave mode*/
+  tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);
+ 800c930:	683a      	ldr	r2, [r7, #0]
+ 800c932:	68fb      	ldr	r3, [r7, #12]
+ 800c934:	4313      	orrs	r3, r2
+ 800c936:	f043 0307 	orr.w	r3, r3, #7
+ 800c93a:	60fb      	str	r3, [r7, #12]
+  /* Write to TIMx SMCR */
+  TIMx->SMCR = tmpsmcr;
+ 800c93c:	687b      	ldr	r3, [r7, #4]
+ 800c93e:	68fa      	ldr	r2, [r7, #12]
+ 800c940:	609a      	str	r2, [r3, #8]
+}
+ 800c942:	bf00      	nop
+ 800c944:	3714      	adds	r7, #20
+ 800c946:	46bd      	mov	sp, r7
+ 800c948:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 800c94c:	4770      	bx	lr
+ 800c94e:	bf00      	nop
+ 800c950:	ffcfff8f 	.word	0xffcfff8f
+
+0800c954 <TIM_ETR_SetConfig>:
+  *          This parameter must be a value between 0x00 and 0x0F
+  * @retval None
+  */
+void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
+                       uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
+{
+ 800c954:	b480      	push	{r7}
+ 800c956:	b087      	sub	sp, #28
+ 800c958:	af00      	add	r7, sp, #0
+ 800c95a:	60f8      	str	r0, [r7, #12]
+ 800c95c:	60b9      	str	r1, [r7, #8]
+ 800c95e:	607a      	str	r2, [r7, #4]
+ 800c960:	603b      	str	r3, [r7, #0]
+  uint32_t tmpsmcr;
+
+  tmpsmcr = TIMx->SMCR;
+ 800c962:	68fb      	ldr	r3, [r7, #12]
+ 800c964:	689b      	ldr	r3, [r3, #8]
+ 800c966:	617b      	str	r3, [r7, #20]
+
+  /* Reset the ETR Bits */
+  tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
+ 800c968:	697b      	ldr	r3, [r7, #20]
+ 800c96a:	f423 437f 	bic.w	r3, r3, #65280	; 0xff00
+ 800c96e:	617b      	str	r3, [r7, #20]
+
+  /* Set the Prescaler, the Filter value and the Polarity */
+  tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
+ 800c970:	683b      	ldr	r3, [r7, #0]
+ 800c972:	021a      	lsls	r2, r3, #8
+ 800c974:	687b      	ldr	r3, [r7, #4]
+ 800c976:	431a      	orrs	r2, r3
+ 800c978:	68bb      	ldr	r3, [r7, #8]
+ 800c97a:	4313      	orrs	r3, r2
+ 800c97c:	697a      	ldr	r2, [r7, #20]
+ 800c97e:	4313      	orrs	r3, r2
+ 800c980:	617b      	str	r3, [r7, #20]
+
+  /* Write to TIMx SMCR */
+  TIMx->SMCR = tmpsmcr;
+ 800c982:	68fb      	ldr	r3, [r7, #12]
+ 800c984:	697a      	ldr	r2, [r7, #20]
+ 800c986:	609a      	str	r2, [r3, #8]
+}
+ 800c988:	bf00      	nop
+ 800c98a:	371c      	adds	r7, #28
+ 800c98c:	46bd      	mov	sp, r7
+ 800c98e:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 800c992:	4770      	bx	lr
+
+0800c994 <HAL_TIMEx_MasterConfigSynchronization>:
+  *         mode.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
+                                                        const TIM_MasterConfigTypeDef *sMasterConfig)
+{
+ 800c994:	b480      	push	{r7}
+ 800c996:	b085      	sub	sp, #20
+ 800c998:	af00      	add	r7, sp, #0
+ 800c99a:	6078      	str	r0, [r7, #4]
+ 800c99c:	6039      	str	r1, [r7, #0]
+  assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
+  assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
+
+  /* Check input state */
+  __HAL_LOCK(htim);
+ 800c99e:	687b      	ldr	r3, [r7, #4]
+ 800c9a0:	f893 303c 	ldrb.w	r3, [r3, #60]	; 0x3c
+ 800c9a4:	2b01      	cmp	r3, #1
+ 800c9a6:	d101      	bne.n	800c9ac <HAL_TIMEx_MasterConfigSynchronization+0x18>
+ 800c9a8:	2302      	movs	r3, #2
+ 800c9aa:	e077      	b.n	800ca9c <HAL_TIMEx_MasterConfigSynchronization+0x108>
+ 800c9ac:	687b      	ldr	r3, [r7, #4]
+ 800c9ae:	2201      	movs	r2, #1
+ 800c9b0:	f883 203c 	strb.w	r2, [r3, #60]	; 0x3c
+
+  /* Change the handler state */
+  htim->State = HAL_TIM_STATE_BUSY;
+ 800c9b4:	687b      	ldr	r3, [r7, #4]
+ 800c9b6:	2202      	movs	r2, #2
+ 800c9b8:	f883 203d 	strb.w	r2, [r3, #61]	; 0x3d
+
+  /* Get the TIMx CR2 register value */
+  tmpcr2 = htim->Instance->CR2;
+ 800c9bc:	687b      	ldr	r3, [r7, #4]
+ 800c9be:	681b      	ldr	r3, [r3, #0]
+ 800c9c0:	685b      	ldr	r3, [r3, #4]
+ 800c9c2:	60fb      	str	r3, [r7, #12]
+
+  /* Get the TIMx SMCR register value */
+  tmpsmcr = htim->Instance->SMCR;
+ 800c9c4:	687b      	ldr	r3, [r7, #4]
+ 800c9c6:	681b      	ldr	r3, [r3, #0]
+ 800c9c8:	689b      	ldr	r3, [r3, #8]
+ 800c9ca:	60bb      	str	r3, [r7, #8]
+
+  /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */
+  if (IS_TIM_TRGO2_INSTANCE(htim->Instance))
+ 800c9cc:	687b      	ldr	r3, [r7, #4]
+ 800c9ce:	681b      	ldr	r3, [r3, #0]
+ 800c9d0:	4a35      	ldr	r2, [pc, #212]	; (800caa8 <HAL_TIMEx_MasterConfigSynchronization+0x114>)
+ 800c9d2:	4293      	cmp	r3, r2
+ 800c9d4:	d004      	beq.n	800c9e0 <HAL_TIMEx_MasterConfigSynchronization+0x4c>
+ 800c9d6:	687b      	ldr	r3, [r7, #4]
+ 800c9d8:	681b      	ldr	r3, [r3, #0]
+ 800c9da:	4a34      	ldr	r2, [pc, #208]	; (800caac <HAL_TIMEx_MasterConfigSynchronization+0x118>)
+ 800c9dc:	4293      	cmp	r3, r2
+ 800c9de:	d108      	bne.n	800c9f2 <HAL_TIMEx_MasterConfigSynchronization+0x5e>
+  {
+    /* Check the parameters */
+    assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2));
+
+    /* Clear the MMS2 bits */
+    tmpcr2 &= ~TIM_CR2_MMS2;
+ 800c9e0:	68fb      	ldr	r3, [r7, #12]
+ 800c9e2:	f423 0370 	bic.w	r3, r3, #15728640	; 0xf00000
+ 800c9e6:	60fb      	str	r3, [r7, #12]
+    /* Select the TRGO2 source*/
+    tmpcr2 |= sMasterConfig->MasterOutputTrigger2;
+ 800c9e8:	683b      	ldr	r3, [r7, #0]
+ 800c9ea:	685b      	ldr	r3, [r3, #4]
+ 800c9ec:	68fa      	ldr	r2, [r7, #12]
+ 800c9ee:	4313      	orrs	r3, r2
+ 800c9f0:	60fb      	str	r3, [r7, #12]
+  }
+
+  /* Reset the MMS Bits */
+  tmpcr2 &= ~TIM_CR2_MMS;
+ 800c9f2:	68fb      	ldr	r3, [r7, #12]
+ 800c9f4:	f023 0370 	bic.w	r3, r3, #112	; 0x70
+ 800c9f8:	60fb      	str	r3, [r7, #12]
+  /* Select the TRGO source */
+  tmpcr2 |=  sMasterConfig->MasterOutputTrigger;
+ 800c9fa:	683b      	ldr	r3, [r7, #0]
+ 800c9fc:	681b      	ldr	r3, [r3, #0]
+ 800c9fe:	68fa      	ldr	r2, [r7, #12]
+ 800ca00:	4313      	orrs	r3, r2
+ 800ca02:	60fb      	str	r3, [r7, #12]
+
+  /* Update TIMx CR2 */
+  htim->Instance->CR2 = tmpcr2;
+ 800ca04:	687b      	ldr	r3, [r7, #4]
+ 800ca06:	681b      	ldr	r3, [r3, #0]
+ 800ca08:	68fa      	ldr	r2, [r7, #12]
+ 800ca0a:	605a      	str	r2, [r3, #4]
+
+  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ 800ca0c:	687b      	ldr	r3, [r7, #4]
+ 800ca0e:	681b      	ldr	r3, [r3, #0]
+ 800ca10:	4a25      	ldr	r2, [pc, #148]	; (800caa8 <HAL_TIMEx_MasterConfigSynchronization+0x114>)
+ 800ca12:	4293      	cmp	r3, r2
+ 800ca14:	d02c      	beq.n	800ca70 <HAL_TIMEx_MasterConfigSynchronization+0xdc>
+ 800ca16:	687b      	ldr	r3, [r7, #4]
+ 800ca18:	681b      	ldr	r3, [r3, #0]
+ 800ca1a:	f1b3 4f80 	cmp.w	r3, #1073741824	; 0x40000000
+ 800ca1e:	d027      	beq.n	800ca70 <HAL_TIMEx_MasterConfigSynchronization+0xdc>
+ 800ca20:	687b      	ldr	r3, [r7, #4]
+ 800ca22:	681b      	ldr	r3, [r3, #0]
+ 800ca24:	4a22      	ldr	r2, [pc, #136]	; (800cab0 <HAL_TIMEx_MasterConfigSynchronization+0x11c>)
+ 800ca26:	4293      	cmp	r3, r2
+ 800ca28:	d022      	beq.n	800ca70 <HAL_TIMEx_MasterConfigSynchronization+0xdc>
+ 800ca2a:	687b      	ldr	r3, [r7, #4]
+ 800ca2c:	681b      	ldr	r3, [r3, #0]
+ 800ca2e:	4a21      	ldr	r2, [pc, #132]	; (800cab4 <HAL_TIMEx_MasterConfigSynchronization+0x120>)
+ 800ca30:	4293      	cmp	r3, r2
+ 800ca32:	d01d      	beq.n	800ca70 <HAL_TIMEx_MasterConfigSynchronization+0xdc>
+ 800ca34:	687b      	ldr	r3, [r7, #4]
+ 800ca36:	681b      	ldr	r3, [r3, #0]
+ 800ca38:	4a1f      	ldr	r2, [pc, #124]	; (800cab8 <HAL_TIMEx_MasterConfigSynchronization+0x124>)
+ 800ca3a:	4293      	cmp	r3, r2
+ 800ca3c:	d018      	beq.n	800ca70 <HAL_TIMEx_MasterConfigSynchronization+0xdc>
+ 800ca3e:	687b      	ldr	r3, [r7, #4]
+ 800ca40:	681b      	ldr	r3, [r3, #0]
+ 800ca42:	4a1a      	ldr	r2, [pc, #104]	; (800caac <HAL_TIMEx_MasterConfigSynchronization+0x118>)
+ 800ca44:	4293      	cmp	r3, r2
+ 800ca46:	d013      	beq.n	800ca70 <HAL_TIMEx_MasterConfigSynchronization+0xdc>
+ 800ca48:	687b      	ldr	r3, [r7, #4]
+ 800ca4a:	681b      	ldr	r3, [r3, #0]
+ 800ca4c:	4a1b      	ldr	r2, [pc, #108]	; (800cabc <HAL_TIMEx_MasterConfigSynchronization+0x128>)
+ 800ca4e:	4293      	cmp	r3, r2
+ 800ca50:	d00e      	beq.n	800ca70 <HAL_TIMEx_MasterConfigSynchronization+0xdc>
+ 800ca52:	687b      	ldr	r3, [r7, #4]
+ 800ca54:	681b      	ldr	r3, [r3, #0]
+ 800ca56:	4a1a      	ldr	r2, [pc, #104]	; (800cac0 <HAL_TIMEx_MasterConfigSynchronization+0x12c>)
+ 800ca58:	4293      	cmp	r3, r2
+ 800ca5a:	d009      	beq.n	800ca70 <HAL_TIMEx_MasterConfigSynchronization+0xdc>
+ 800ca5c:	687b      	ldr	r3, [r7, #4]
+ 800ca5e:	681b      	ldr	r3, [r3, #0]
+ 800ca60:	4a18      	ldr	r2, [pc, #96]	; (800cac4 <HAL_TIMEx_MasterConfigSynchronization+0x130>)
+ 800ca62:	4293      	cmp	r3, r2
+ 800ca64:	d004      	beq.n	800ca70 <HAL_TIMEx_MasterConfigSynchronization+0xdc>
+ 800ca66:	687b      	ldr	r3, [r7, #4]
+ 800ca68:	681b      	ldr	r3, [r3, #0]
+ 800ca6a:	4a17      	ldr	r2, [pc, #92]	; (800cac8 <HAL_TIMEx_MasterConfigSynchronization+0x134>)
+ 800ca6c:	4293      	cmp	r3, r2
+ 800ca6e:	d10c      	bne.n	800ca8a <HAL_TIMEx_MasterConfigSynchronization+0xf6>
+  {
+    /* Reset the MSM Bit */
+    tmpsmcr &= ~TIM_SMCR_MSM;
+ 800ca70:	68bb      	ldr	r3, [r7, #8]
+ 800ca72:	f023 0380 	bic.w	r3, r3, #128	; 0x80
+ 800ca76:	60bb      	str	r3, [r7, #8]
+    /* Set master mode */
+    tmpsmcr |= sMasterConfig->MasterSlaveMode;
+ 800ca78:	683b      	ldr	r3, [r7, #0]
+ 800ca7a:	689b      	ldr	r3, [r3, #8]
+ 800ca7c:	68ba      	ldr	r2, [r7, #8]
+ 800ca7e:	4313      	orrs	r3, r2
+ 800ca80:	60bb      	str	r3, [r7, #8]
+
+    /* Update TIMx SMCR */
+    htim->Instance->SMCR = tmpsmcr;
+ 800ca82:	687b      	ldr	r3, [r7, #4]
+ 800ca84:	681b      	ldr	r3, [r3, #0]
+ 800ca86:	68ba      	ldr	r2, [r7, #8]
+ 800ca88:	609a      	str	r2, [r3, #8]
+  }
+
+  /* Change the htim state */
+  htim->State = HAL_TIM_STATE_READY;
+ 800ca8a:	687b      	ldr	r3, [r7, #4]
+ 800ca8c:	2201      	movs	r2, #1
+ 800ca8e:	f883 203d 	strb.w	r2, [r3, #61]	; 0x3d
+
+  __HAL_UNLOCK(htim);
+ 800ca92:	687b      	ldr	r3, [r7, #4]
+ 800ca94:	2200      	movs	r2, #0
+ 800ca96:	f883 203c 	strb.w	r2, [r3, #60]	; 0x3c
+
+  return HAL_OK;
+ 800ca9a:	2300      	movs	r3, #0
+}
+ 800ca9c:	4618      	mov	r0, r3
+ 800ca9e:	3714      	adds	r7, #20
+ 800caa0:	46bd      	mov	sp, r7
+ 800caa2:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 800caa6:	4770      	bx	lr
+ 800caa8:	40010000 	.word	0x40010000
+ 800caac:	40010400 	.word	0x40010400
+ 800cab0:	40000400 	.word	0x40000400
+ 800cab4:	40000800 	.word	0x40000800
+ 800cab8:	40000c00 	.word	0x40000c00
+ 800cabc:	40001800 	.word	0x40001800
+ 800cac0:	40014000 	.word	0x40014000
+ 800cac4:	4000e000 	.word	0x4000e000
+ 800cac8:	4000e400 	.word	0x4000e400
+
+0800cacc <HAL_TIMEx_CommutCallback>:
+  * @brief  Hall commutation changed callback in non-blocking mode
+  * @param  htim TIM handle
+  * @retval None
+  */
+__weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim)
+{
+ 800cacc:	b480      	push	{r7}
+ 800cace:	b083      	sub	sp, #12
+ 800cad0:	af00      	add	r7, sp, #0
+ 800cad2:	6078      	str	r0, [r7, #4]
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIMEx_CommutCallback could be implemented in the user file
+   */
+}
+ 800cad4:	bf00      	nop
+ 800cad6:	370c      	adds	r7, #12
+ 800cad8:	46bd      	mov	sp, r7
+ 800cada:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 800cade:	4770      	bx	lr
+
+0800cae0 <HAL_TIMEx_BreakCallback>:
+  * @brief  Hall Break detection callback in non-blocking mode
+  * @param  htim TIM handle
+  * @retval None
+  */
+__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
+{
+ 800cae0:	b480      	push	{r7}
+ 800cae2:	b083      	sub	sp, #12
+ 800cae4:	af00      	add	r7, sp, #0
+ 800cae6:	6078      	str	r0, [r7, #4]
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIMEx_BreakCallback could be implemented in the user file
+   */
+}
+ 800cae8:	bf00      	nop
+ 800caea:	370c      	adds	r7, #12
+ 800caec:	46bd      	mov	sp, r7
+ 800caee:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 800caf2:	4770      	bx	lr
+
+0800caf4 <HAL_TIMEx_Break2Callback>:
+  * @brief  Hall Break2 detection callback in non blocking mode
+  * @param  htim: TIM handle
+  * @retval None
+  */
+__weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim)
+{
+ 800caf4:	b480      	push	{r7}
+ 800caf6:	b083      	sub	sp, #12
+ 800caf8:	af00      	add	r7, sp, #0
+ 800cafa:	6078      	str	r0, [r7, #4]
+  UNUSED(htim);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_TIMEx_Break2Callback could be implemented in the user file
+   */
+}
+ 800cafc:	bf00      	nop
+ 800cafe:	370c      	adds	r7, #12
+ 800cb00:	46bd      	mov	sp, r7
+ 800cb02:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 800cb06:	4770      	bx	lr
+
+0800cb08 <HAL_UART_Init>:
+  *        parameters in the UART_InitTypeDef and initialize the associated handle.
+  * @param huart UART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
+{
+ 800cb08:	b580      	push	{r7, lr}
+ 800cb0a:	b082      	sub	sp, #8
+ 800cb0c:	af00      	add	r7, sp, #0
+ 800cb0e:	6078      	str	r0, [r7, #4]
+  /* Check the UART handle allocation */
+  if (huart == NULL)
+ 800cb10:	687b      	ldr	r3, [r7, #4]
+ 800cb12:	2b00      	cmp	r3, #0
+ 800cb14:	d101      	bne.n	800cb1a <HAL_UART_Init+0x12>
+  {
+    return HAL_ERROR;
+ 800cb16:	2301      	movs	r3, #1
+ 800cb18:	e042      	b.n	800cba0 <HAL_UART_Init+0x98>
+  {
+    /* Check the parameters */
+    assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance)));
+  }
+
+  if (huart->gState == HAL_UART_STATE_RESET)
+ 800cb1a:	687b      	ldr	r3, [r7, #4]
+ 800cb1c:	f8d3 3088 	ldr.w	r3, [r3, #136]	; 0x88
+ 800cb20:	2b00      	cmp	r3, #0
+ 800cb22:	d106      	bne.n	800cb32 <HAL_UART_Init+0x2a>
+  {
+    /* Allocate lock resource and initialize it */
+    huart->Lock = HAL_UNLOCKED;
+ 800cb24:	687b      	ldr	r3, [r7, #4]
+ 800cb26:	2200      	movs	r2, #0
+ 800cb28:	f883 2084 	strb.w	r2, [r3, #132]	; 0x84
+
+    /* Init the low level hardware */
+    huart->MspInitCallback(huart);
+#else
+    /* Init the low level hardware : GPIO, CLOCK */
+    HAL_UART_MspInit(huart);
+ 800cb2c:	6878      	ldr	r0, [r7, #4]
+ 800cb2e:	f7f4 fefd 	bl	800192c <HAL_UART_MspInit>
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+  }
+
+  huart->gState = HAL_UART_STATE_BUSY;
+ 800cb32:	687b      	ldr	r3, [r7, #4]
+ 800cb34:	2224      	movs	r2, #36	; 0x24
+ 800cb36:	f8c3 2088 	str.w	r2, [r3, #136]	; 0x88
+
+  __HAL_UART_DISABLE(huart);
+ 800cb3a:	687b      	ldr	r3, [r7, #4]
+ 800cb3c:	681b      	ldr	r3, [r3, #0]
+ 800cb3e:	681a      	ldr	r2, [r3, #0]
+ 800cb40:	687b      	ldr	r3, [r7, #4]
+ 800cb42:	681b      	ldr	r3, [r3, #0]
+ 800cb44:	f022 0201 	bic.w	r2, r2, #1
+ 800cb48:	601a      	str	r2, [r3, #0]
+
+  /* Set the UART Communication parameters */
+  if (UART_SetConfig(huart) == HAL_ERROR)
+ 800cb4a:	6878      	ldr	r0, [r7, #4]
+ 800cb4c:	f000 f82c 	bl	800cba8 <UART_SetConfig>
+ 800cb50:	4603      	mov	r3, r0
+ 800cb52:	2b01      	cmp	r3, #1
+ 800cb54:	d101      	bne.n	800cb5a <HAL_UART_Init+0x52>
+  {
+    return HAL_ERROR;
+ 800cb56:	2301      	movs	r3, #1
+ 800cb58:	e022      	b.n	800cba0 <HAL_UART_Init+0x98>
+  }
+
+  if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
+ 800cb5a:	687b      	ldr	r3, [r7, #4]
+ 800cb5c:	6a9b      	ldr	r3, [r3, #40]	; 0x28
+ 800cb5e:	2b00      	cmp	r3, #0
+ 800cb60:	d002      	beq.n	800cb68 <HAL_UART_Init+0x60>
+  {
+    UART_AdvFeatureConfig(huart);
+ 800cb62:	6878      	ldr	r0, [r7, #4]
+ 800cb64:	f000 fe8c 	bl	800d880 <UART_AdvFeatureConfig>
+  }
+
+  /* In asynchronous mode, the following bits must be kept cleared:
+  - LINEN and CLKEN bits in the USART_CR2 register,
+  - SCEN, HDSEL and IREN  bits in the USART_CR3 register.*/
+  CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+ 800cb68:	687b      	ldr	r3, [r7, #4]
+ 800cb6a:	681b      	ldr	r3, [r3, #0]
+ 800cb6c:	685a      	ldr	r2, [r3, #4]
+ 800cb6e:	687b      	ldr	r3, [r7, #4]
+ 800cb70:	681b      	ldr	r3, [r3, #0]
+ 800cb72:	f422 4290 	bic.w	r2, r2, #18432	; 0x4800
+ 800cb76:	605a      	str	r2, [r3, #4]
+  CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
+ 800cb78:	687b      	ldr	r3, [r7, #4]
+ 800cb7a:	681b      	ldr	r3, [r3, #0]
+ 800cb7c:	689a      	ldr	r2, [r3, #8]
+ 800cb7e:	687b      	ldr	r3, [r7, #4]
+ 800cb80:	681b      	ldr	r3, [r3, #0]
+ 800cb82:	f022 022a 	bic.w	r2, r2, #42	; 0x2a
+ 800cb86:	609a      	str	r2, [r3, #8]
+
+  __HAL_UART_ENABLE(huart);
+ 800cb88:	687b      	ldr	r3, [r7, #4]
+ 800cb8a:	681b      	ldr	r3, [r3, #0]
+ 800cb8c:	681a      	ldr	r2, [r3, #0]
+ 800cb8e:	687b      	ldr	r3, [r7, #4]
+ 800cb90:	681b      	ldr	r3, [r3, #0]
+ 800cb92:	f042 0201 	orr.w	r2, r2, #1
+ 800cb96:	601a      	str	r2, [r3, #0]
+
+  /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
+  return (UART_CheckIdleState(huart));
+ 800cb98:	6878      	ldr	r0, [r7, #4]
+ 800cb9a:	f000 ff13 	bl	800d9c4 <UART_CheckIdleState>
+ 800cb9e:	4603      	mov	r3, r0
+}
+ 800cba0:	4618      	mov	r0, r3
+ 800cba2:	3708      	adds	r7, #8
+ 800cba4:	46bd      	mov	sp, r7
+ 800cba6:	bd80      	pop	{r7, pc}
+
+0800cba8 <UART_SetConfig>:
+  * @brief Configure the UART peripheral.
+  * @param huart UART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart)
+{
+ 800cba8:	e92d 4fb0 	stmdb	sp!, {r4, r5, r7, r8, r9, sl, fp, lr}
+ 800cbac:	b092      	sub	sp, #72	; 0x48
+ 800cbae:	af00      	add	r7, sp, #0
+ 800cbb0:	6178      	str	r0, [r7, #20]
+  uint32_t tmpreg;
+  uint16_t brrtemp;
+  UART_ClockSourceTypeDef clocksource;
+  uint32_t usartdiv;
+  HAL_StatusTypeDef ret               = HAL_OK;
+ 800cbb2:	2300      	movs	r3, #0
+ 800cbb4:	f887 3042 	strb.w	r3, [r7, #66]	; 0x42
+  *  the UART Word Length, Parity, Mode and oversampling:
+  *  set the M bits according to huart->Init.WordLength value
+  *  set PCE and PS bits according to huart->Init.Parity value
+  *  set TE and RE bits according to huart->Init.Mode value
+  *  set OVER8 bit according to huart->Init.OverSampling value */
+  tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ;
+ 800cbb8:	697b      	ldr	r3, [r7, #20]
+ 800cbba:	689a      	ldr	r2, [r3, #8]
+ 800cbbc:	697b      	ldr	r3, [r7, #20]
+ 800cbbe:	691b      	ldr	r3, [r3, #16]
+ 800cbc0:	431a      	orrs	r2, r3
+ 800cbc2:	697b      	ldr	r3, [r7, #20]
+ 800cbc4:	695b      	ldr	r3, [r3, #20]
+ 800cbc6:	431a      	orrs	r2, r3
+ 800cbc8:	697b      	ldr	r3, [r7, #20]
+ 800cbca:	69db      	ldr	r3, [r3, #28]
+ 800cbcc:	4313      	orrs	r3, r2
+ 800cbce:	647b      	str	r3, [r7, #68]	; 0x44
+  MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
+ 800cbd0:	697b      	ldr	r3, [r7, #20]
+ 800cbd2:	681b      	ldr	r3, [r3, #0]
+ 800cbd4:	681a      	ldr	r2, [r3, #0]
+ 800cbd6:	4bbe      	ldr	r3, [pc, #760]	; (800ced0 <UART_SetConfig+0x328>)
+ 800cbd8:	4013      	ands	r3, r2
+ 800cbda:	697a      	ldr	r2, [r7, #20]
+ 800cbdc:	6812      	ldr	r2, [r2, #0]
+ 800cbde:	6c79      	ldr	r1, [r7, #68]	; 0x44
+ 800cbe0:	430b      	orrs	r3, r1
+ 800cbe2:	6013      	str	r3, [r2, #0]
+
+  /*-------------------------- USART CR2 Configuration -----------------------*/
+  /* Configure the UART Stop Bits: Set STOP[13:12] bits according
+  * to huart->Init.StopBits value */
+  MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
+ 800cbe4:	697b      	ldr	r3, [r7, #20]
+ 800cbe6:	681b      	ldr	r3, [r3, #0]
+ 800cbe8:	685b      	ldr	r3, [r3, #4]
+ 800cbea:	f423 5140 	bic.w	r1, r3, #12288	; 0x3000
+ 800cbee:	697b      	ldr	r3, [r7, #20]
+ 800cbf0:	68da      	ldr	r2, [r3, #12]
+ 800cbf2:	697b      	ldr	r3, [r7, #20]
+ 800cbf4:	681b      	ldr	r3, [r3, #0]
+ 800cbf6:	430a      	orrs	r2, r1
+ 800cbf8:	605a      	str	r2, [r3, #4]
+  /* Configure
+  * - UART HardWare Flow Control: set CTSE and RTSE bits according
+  *   to huart->Init.HwFlowCtl value
+  * - one-bit sampling method versus three samples' majority rule according
+  *   to huart->Init.OneBitSampling (not applicable to LPUART) */
+  tmpreg = (uint32_t)huart->Init.HwFlowCtl;
+ 800cbfa:	697b      	ldr	r3, [r7, #20]
+ 800cbfc:	699b      	ldr	r3, [r3, #24]
+ 800cbfe:	647b      	str	r3, [r7, #68]	; 0x44
+
+  if (!(UART_INSTANCE_LOWPOWER(huart)))
+ 800cc00:	697b      	ldr	r3, [r7, #20]
+ 800cc02:	681b      	ldr	r3, [r3, #0]
+ 800cc04:	4ab3      	ldr	r2, [pc, #716]	; (800ced4 <UART_SetConfig+0x32c>)
+ 800cc06:	4293      	cmp	r3, r2
+ 800cc08:	d004      	beq.n	800cc14 <UART_SetConfig+0x6c>
+  {
+    tmpreg |= huart->Init.OneBitSampling;
+ 800cc0a:	697b      	ldr	r3, [r7, #20]
+ 800cc0c:	6a1b      	ldr	r3, [r3, #32]
+ 800cc0e:	6c7a      	ldr	r2, [r7, #68]	; 0x44
+ 800cc10:	4313      	orrs	r3, r2
+ 800cc12:	647b      	str	r3, [r7, #68]	; 0x44
+  }
+  MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg);
+ 800cc14:	697b      	ldr	r3, [r7, #20]
+ 800cc16:	681b      	ldr	r3, [r3, #0]
+ 800cc18:	689a      	ldr	r2, [r3, #8]
+ 800cc1a:	4baf      	ldr	r3, [pc, #700]	; (800ced8 <UART_SetConfig+0x330>)
+ 800cc1c:	4013      	ands	r3, r2
+ 800cc1e:	697a      	ldr	r2, [r7, #20]
+ 800cc20:	6812      	ldr	r2, [r2, #0]
+ 800cc22:	6c79      	ldr	r1, [r7, #68]	; 0x44
+ 800cc24:	430b      	orrs	r3, r1
+ 800cc26:	6093      	str	r3, [r2, #8]
+
+  /*-------------------------- USART PRESC Configuration -----------------------*/
+  /* Configure
+  * - UART Clock Prescaler : set PRESCALER according to huart->Init.ClockPrescaler value */
+  MODIFY_REG(huart->Instance->PRESC, USART_PRESC_PRESCALER, huart->Init.ClockPrescaler);
+ 800cc28:	697b      	ldr	r3, [r7, #20]
+ 800cc2a:	681b      	ldr	r3, [r3, #0]
+ 800cc2c:	6adb      	ldr	r3, [r3, #44]	; 0x2c
+ 800cc2e:	f023 010f 	bic.w	r1, r3, #15
+ 800cc32:	697b      	ldr	r3, [r7, #20]
+ 800cc34:	6a5a      	ldr	r2, [r3, #36]	; 0x24
+ 800cc36:	697b      	ldr	r3, [r7, #20]
+ 800cc38:	681b      	ldr	r3, [r3, #0]
+ 800cc3a:	430a      	orrs	r2, r1
+ 800cc3c:	62da      	str	r2, [r3, #44]	; 0x2c
+
+  /*-------------------------- USART BRR Configuration -----------------------*/
+  UART_GETCLOCKSOURCE(huart, clocksource);
+ 800cc3e:	697b      	ldr	r3, [r7, #20]
+ 800cc40:	681b      	ldr	r3, [r3, #0]
+ 800cc42:	4aa6      	ldr	r2, [pc, #664]	; (800cedc <UART_SetConfig+0x334>)
+ 800cc44:	4293      	cmp	r3, r2
+ 800cc46:	d177      	bne.n	800cd38 <UART_SetConfig+0x190>
+ 800cc48:	4ba5      	ldr	r3, [pc, #660]	; (800cee0 <UART_SetConfig+0x338>)
+ 800cc4a:	6d5b      	ldr	r3, [r3, #84]	; 0x54
+ 800cc4c:	f003 0338 	and.w	r3, r3, #56	; 0x38
+ 800cc50:	2b28      	cmp	r3, #40	; 0x28
+ 800cc52:	d86d      	bhi.n	800cd30 <UART_SetConfig+0x188>
+ 800cc54:	a201      	add	r2, pc, #4	; (adr r2, 800cc5c <UART_SetConfig+0xb4>)
+ 800cc56:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
+ 800cc5a:	bf00      	nop
+ 800cc5c:	0800cd01 	.word	0x0800cd01
+ 800cc60:	0800cd31 	.word	0x0800cd31
+ 800cc64:	0800cd31 	.word	0x0800cd31
+ 800cc68:	0800cd31 	.word	0x0800cd31
+ 800cc6c:	0800cd31 	.word	0x0800cd31
+ 800cc70:	0800cd31 	.word	0x0800cd31
+ 800cc74:	0800cd31 	.word	0x0800cd31
+ 800cc78:	0800cd31 	.word	0x0800cd31
+ 800cc7c:	0800cd09 	.word	0x0800cd09
+ 800cc80:	0800cd31 	.word	0x0800cd31
+ 800cc84:	0800cd31 	.word	0x0800cd31
+ 800cc88:	0800cd31 	.word	0x0800cd31
+ 800cc8c:	0800cd31 	.word	0x0800cd31
+ 800cc90:	0800cd31 	.word	0x0800cd31
+ 800cc94:	0800cd31 	.word	0x0800cd31
+ 800cc98:	0800cd31 	.word	0x0800cd31
+ 800cc9c:	0800cd11 	.word	0x0800cd11
+ 800cca0:	0800cd31 	.word	0x0800cd31
+ 800cca4:	0800cd31 	.word	0x0800cd31
+ 800cca8:	0800cd31 	.word	0x0800cd31
+ 800ccac:	0800cd31 	.word	0x0800cd31
+ 800ccb0:	0800cd31 	.word	0x0800cd31
+ 800ccb4:	0800cd31 	.word	0x0800cd31
+ 800ccb8:	0800cd31 	.word	0x0800cd31
+ 800ccbc:	0800cd19 	.word	0x0800cd19
+ 800ccc0:	0800cd31 	.word	0x0800cd31
+ 800ccc4:	0800cd31 	.word	0x0800cd31
+ 800ccc8:	0800cd31 	.word	0x0800cd31
+ 800cccc:	0800cd31 	.word	0x0800cd31
+ 800ccd0:	0800cd31 	.word	0x0800cd31
+ 800ccd4:	0800cd31 	.word	0x0800cd31
+ 800ccd8:	0800cd31 	.word	0x0800cd31
+ 800ccdc:	0800cd21 	.word	0x0800cd21
+ 800cce0:	0800cd31 	.word	0x0800cd31
+ 800cce4:	0800cd31 	.word	0x0800cd31
+ 800cce8:	0800cd31 	.word	0x0800cd31
+ 800ccec:	0800cd31 	.word	0x0800cd31
+ 800ccf0:	0800cd31 	.word	0x0800cd31
+ 800ccf4:	0800cd31 	.word	0x0800cd31
+ 800ccf8:	0800cd31 	.word	0x0800cd31
+ 800ccfc:	0800cd29 	.word	0x0800cd29
+ 800cd00:	2301      	movs	r3, #1
+ 800cd02:	f887 3043 	strb.w	r3, [r7, #67]	; 0x43
+ 800cd06:	e326      	b.n	800d356 <UART_SetConfig+0x7ae>
+ 800cd08:	2304      	movs	r3, #4
+ 800cd0a:	f887 3043 	strb.w	r3, [r7, #67]	; 0x43
+ 800cd0e:	e322      	b.n	800d356 <UART_SetConfig+0x7ae>
+ 800cd10:	2308      	movs	r3, #8
+ 800cd12:	f887 3043 	strb.w	r3, [r7, #67]	; 0x43
+ 800cd16:	e31e      	b.n	800d356 <UART_SetConfig+0x7ae>
+ 800cd18:	2310      	movs	r3, #16
+ 800cd1a:	f887 3043 	strb.w	r3, [r7, #67]	; 0x43
+ 800cd1e:	e31a      	b.n	800d356 <UART_SetConfig+0x7ae>
+ 800cd20:	2320      	movs	r3, #32
+ 800cd22:	f887 3043 	strb.w	r3, [r7, #67]	; 0x43
+ 800cd26:	e316      	b.n	800d356 <UART_SetConfig+0x7ae>
+ 800cd28:	2340      	movs	r3, #64	; 0x40
+ 800cd2a:	f887 3043 	strb.w	r3, [r7, #67]	; 0x43
+ 800cd2e:	e312      	b.n	800d356 <UART_SetConfig+0x7ae>
+ 800cd30:	2380      	movs	r3, #128	; 0x80
+ 800cd32:	f887 3043 	strb.w	r3, [r7, #67]	; 0x43
+ 800cd36:	e30e      	b.n	800d356 <UART_SetConfig+0x7ae>
+ 800cd38:	697b      	ldr	r3, [r7, #20]
+ 800cd3a:	681b      	ldr	r3, [r3, #0]
+ 800cd3c:	4a69      	ldr	r2, [pc, #420]	; (800cee4 <UART_SetConfig+0x33c>)
+ 800cd3e:	4293      	cmp	r3, r2
+ 800cd40:	d130      	bne.n	800cda4 <UART_SetConfig+0x1fc>
+ 800cd42:	4b67      	ldr	r3, [pc, #412]	; (800cee0 <UART_SetConfig+0x338>)
+ 800cd44:	6d5b      	ldr	r3, [r3, #84]	; 0x54
+ 800cd46:	f003 0307 	and.w	r3, r3, #7
+ 800cd4a:	2b05      	cmp	r3, #5
+ 800cd4c:	d826      	bhi.n	800cd9c <UART_SetConfig+0x1f4>
+ 800cd4e:	a201      	add	r2, pc, #4	; (adr r2, 800cd54 <UART_SetConfig+0x1ac>)
+ 800cd50:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
+ 800cd54:	0800cd6d 	.word	0x0800cd6d
+ 800cd58:	0800cd75 	.word	0x0800cd75
+ 800cd5c:	0800cd7d 	.word	0x0800cd7d
+ 800cd60:	0800cd85 	.word	0x0800cd85
+ 800cd64:	0800cd8d 	.word	0x0800cd8d
+ 800cd68:	0800cd95 	.word	0x0800cd95
+ 800cd6c:	2300      	movs	r3, #0
+ 800cd6e:	f887 3043 	strb.w	r3, [r7, #67]	; 0x43
+ 800cd72:	e2f0      	b.n	800d356 <UART_SetConfig+0x7ae>
+ 800cd74:	2304      	movs	r3, #4
+ 800cd76:	f887 3043 	strb.w	r3, [r7, #67]	; 0x43
+ 800cd7a:	e2ec      	b.n	800d356 <UART_SetConfig+0x7ae>
+ 800cd7c:	2308      	movs	r3, #8
+ 800cd7e:	f887 3043 	strb.w	r3, [r7, #67]	; 0x43
+ 800cd82:	e2e8      	b.n	800d356 <UART_SetConfig+0x7ae>
+ 800cd84:	2310      	movs	r3, #16
+ 800cd86:	f887 3043 	strb.w	r3, [r7, #67]	; 0x43
+ 800cd8a:	e2e4      	b.n	800d356 <UART_SetConfig+0x7ae>
+ 800cd8c:	2320      	movs	r3, #32
+ 800cd8e:	f887 3043 	strb.w	r3, [r7, #67]	; 0x43
+ 800cd92:	e2e0      	b.n	800d356 <UART_SetConfig+0x7ae>
+ 800cd94:	2340      	movs	r3, #64	; 0x40
+ 800cd96:	f887 3043 	strb.w	r3, [r7, #67]	; 0x43
+ 800cd9a:	e2dc      	b.n	800d356 <UART_SetConfig+0x7ae>
+ 800cd9c:	2380      	movs	r3, #128	; 0x80
+ 800cd9e:	f887 3043 	strb.w	r3, [r7, #67]	; 0x43
+ 800cda2:	e2d8      	b.n	800d356 <UART_SetConfig+0x7ae>
+ 800cda4:	697b      	ldr	r3, [r7, #20]
+ 800cda6:	681b      	ldr	r3, [r3, #0]
+ 800cda8:	4a4f      	ldr	r2, [pc, #316]	; (800cee8 <UART_SetConfig+0x340>)
+ 800cdaa:	4293      	cmp	r3, r2
+ 800cdac:	d130      	bne.n	800ce10 <UART_SetConfig+0x268>
+ 800cdae:	4b4c      	ldr	r3, [pc, #304]	; (800cee0 <UART_SetConfig+0x338>)
+ 800cdb0:	6d5b      	ldr	r3, [r3, #84]	; 0x54
+ 800cdb2:	f003 0307 	and.w	r3, r3, #7
+ 800cdb6:	2b05      	cmp	r3, #5
+ 800cdb8:	d826      	bhi.n	800ce08 <UART_SetConfig+0x260>
+ 800cdba:	a201      	add	r2, pc, #4	; (adr r2, 800cdc0 <UART_SetConfig+0x218>)
+ 800cdbc:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
+ 800cdc0:	0800cdd9 	.word	0x0800cdd9
+ 800cdc4:	0800cde1 	.word	0x0800cde1
+ 800cdc8:	0800cde9 	.word	0x0800cde9
+ 800cdcc:	0800cdf1 	.word	0x0800cdf1
+ 800cdd0:	0800cdf9 	.word	0x0800cdf9
+ 800cdd4:	0800ce01 	.word	0x0800ce01
+ 800cdd8:	2300      	movs	r3, #0
+ 800cdda:	f887 3043 	strb.w	r3, [r7, #67]	; 0x43
+ 800cdde:	e2ba      	b.n	800d356 <UART_SetConfig+0x7ae>
+ 800cde0:	2304      	movs	r3, #4
+ 800cde2:	f887 3043 	strb.w	r3, [r7, #67]	; 0x43
+ 800cde6:	e2b6      	b.n	800d356 <UART_SetConfig+0x7ae>
+ 800cde8:	2308      	movs	r3, #8
+ 800cdea:	f887 3043 	strb.w	r3, [r7, #67]	; 0x43
+ 800cdee:	e2b2      	b.n	800d356 <UART_SetConfig+0x7ae>
+ 800cdf0:	2310      	movs	r3, #16
+ 800cdf2:	f887 3043 	strb.w	r3, [r7, #67]	; 0x43
+ 800cdf6:	e2ae      	b.n	800d356 <UART_SetConfig+0x7ae>
+ 800cdf8:	2320      	movs	r3, #32
+ 800cdfa:	f887 3043 	strb.w	r3, [r7, #67]	; 0x43
+ 800cdfe:	e2aa      	b.n	800d356 <UART_SetConfig+0x7ae>
+ 800ce00:	2340      	movs	r3, #64	; 0x40
+ 800ce02:	f887 3043 	strb.w	r3, [r7, #67]	; 0x43
+ 800ce06:	e2a6      	b.n	800d356 <UART_SetConfig+0x7ae>
+ 800ce08:	2380      	movs	r3, #128	; 0x80
+ 800ce0a:	f887 3043 	strb.w	r3, [r7, #67]	; 0x43
+ 800ce0e:	e2a2      	b.n	800d356 <UART_SetConfig+0x7ae>
+ 800ce10:	697b      	ldr	r3, [r7, #20]
+ 800ce12:	681b      	ldr	r3, [r3, #0]
+ 800ce14:	4a35      	ldr	r2, [pc, #212]	; (800ceec <UART_SetConfig+0x344>)
+ 800ce16:	4293      	cmp	r3, r2
+ 800ce18:	d130      	bne.n	800ce7c <UART_SetConfig+0x2d4>
+ 800ce1a:	4b31      	ldr	r3, [pc, #196]	; (800cee0 <UART_SetConfig+0x338>)
+ 800ce1c:	6d5b      	ldr	r3, [r3, #84]	; 0x54
+ 800ce1e:	f003 0307 	and.w	r3, r3, #7
+ 800ce22:	2b05      	cmp	r3, #5
+ 800ce24:	d826      	bhi.n	800ce74 <UART_SetConfig+0x2cc>
+ 800ce26:	a201      	add	r2, pc, #4	; (adr r2, 800ce2c <UART_SetConfig+0x284>)
+ 800ce28:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
+ 800ce2c:	0800ce45 	.word	0x0800ce45
+ 800ce30:	0800ce4d 	.word	0x0800ce4d
+ 800ce34:	0800ce55 	.word	0x0800ce55
+ 800ce38:	0800ce5d 	.word	0x0800ce5d
+ 800ce3c:	0800ce65 	.word	0x0800ce65
+ 800ce40:	0800ce6d 	.word	0x0800ce6d
+ 800ce44:	2300      	movs	r3, #0
+ 800ce46:	f887 3043 	strb.w	r3, [r7, #67]	; 0x43
+ 800ce4a:	e284      	b.n	800d356 <UART_SetConfig+0x7ae>
+ 800ce4c:	2304      	movs	r3, #4
+ 800ce4e:	f887 3043 	strb.w	r3, [r7, #67]	; 0x43
+ 800ce52:	e280      	b.n	800d356 <UART_SetConfig+0x7ae>
+ 800ce54:	2308      	movs	r3, #8
+ 800ce56:	f887 3043 	strb.w	r3, [r7, #67]	; 0x43
+ 800ce5a:	e27c      	b.n	800d356 <UART_SetConfig+0x7ae>
+ 800ce5c:	2310      	movs	r3, #16
+ 800ce5e:	f887 3043 	strb.w	r3, [r7, #67]	; 0x43
+ 800ce62:	e278      	b.n	800d356 <UART_SetConfig+0x7ae>
+ 800ce64:	2320      	movs	r3, #32
+ 800ce66:	f887 3043 	strb.w	r3, [r7, #67]	; 0x43
+ 800ce6a:	e274      	b.n	800d356 <UART_SetConfig+0x7ae>
+ 800ce6c:	2340      	movs	r3, #64	; 0x40
+ 800ce6e:	f887 3043 	strb.w	r3, [r7, #67]	; 0x43
+ 800ce72:	e270      	b.n	800d356 <UART_SetConfig+0x7ae>
+ 800ce74:	2380      	movs	r3, #128	; 0x80
+ 800ce76:	f887 3043 	strb.w	r3, [r7, #67]	; 0x43
+ 800ce7a:	e26c      	b.n	800d356 <UART_SetConfig+0x7ae>
+ 800ce7c:	697b      	ldr	r3, [r7, #20]
+ 800ce7e:	681b      	ldr	r3, [r3, #0]
+ 800ce80:	4a1b      	ldr	r2, [pc, #108]	; (800cef0 <UART_SetConfig+0x348>)
+ 800ce82:	4293      	cmp	r3, r2
+ 800ce84:	d142      	bne.n	800cf0c <UART_SetConfig+0x364>
+ 800ce86:	4b16      	ldr	r3, [pc, #88]	; (800cee0 <UART_SetConfig+0x338>)
+ 800ce88:	6d5b      	ldr	r3, [r3, #84]	; 0x54
+ 800ce8a:	f003 0307 	and.w	r3, r3, #7
+ 800ce8e:	2b05      	cmp	r3, #5
+ 800ce90:	d838      	bhi.n	800cf04 <UART_SetConfig+0x35c>
+ 800ce92:	a201      	add	r2, pc, #4	; (adr r2, 800ce98 <UART_SetConfig+0x2f0>)
+ 800ce94:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
+ 800ce98:	0800ceb1 	.word	0x0800ceb1
+ 800ce9c:	0800ceb9 	.word	0x0800ceb9
+ 800cea0:	0800cec1 	.word	0x0800cec1
+ 800cea4:	0800cec9 	.word	0x0800cec9
+ 800cea8:	0800cef5 	.word	0x0800cef5
+ 800ceac:	0800cefd 	.word	0x0800cefd
+ 800ceb0:	2300      	movs	r3, #0
+ 800ceb2:	f887 3043 	strb.w	r3, [r7, #67]	; 0x43
+ 800ceb6:	e24e      	b.n	800d356 <UART_SetConfig+0x7ae>
+ 800ceb8:	2304      	movs	r3, #4
+ 800ceba:	f887 3043 	strb.w	r3, [r7, #67]	; 0x43
+ 800cebe:	e24a      	b.n	800d356 <UART_SetConfig+0x7ae>
+ 800cec0:	2308      	movs	r3, #8
+ 800cec2:	f887 3043 	strb.w	r3, [r7, #67]	; 0x43
+ 800cec6:	e246      	b.n	800d356 <UART_SetConfig+0x7ae>
+ 800cec8:	2310      	movs	r3, #16
+ 800ceca:	f887 3043 	strb.w	r3, [r7, #67]	; 0x43
+ 800cece:	e242      	b.n	800d356 <UART_SetConfig+0x7ae>
+ 800ced0:	cfff69f3 	.word	0xcfff69f3
+ 800ced4:	58000c00 	.word	0x58000c00
+ 800ced8:	11fff4ff 	.word	0x11fff4ff
+ 800cedc:	40011000 	.word	0x40011000
+ 800cee0:	58024400 	.word	0x58024400
+ 800cee4:	40004400 	.word	0x40004400
+ 800cee8:	40004800 	.word	0x40004800
+ 800ceec:	40004c00 	.word	0x40004c00
+ 800cef0:	40005000 	.word	0x40005000
+ 800cef4:	2320      	movs	r3, #32
+ 800cef6:	f887 3043 	strb.w	r3, [r7, #67]	; 0x43
+ 800cefa:	e22c      	b.n	800d356 <UART_SetConfig+0x7ae>
+ 800cefc:	2340      	movs	r3, #64	; 0x40
+ 800cefe:	f887 3043 	strb.w	r3, [r7, #67]	; 0x43
+ 800cf02:	e228      	b.n	800d356 <UART_SetConfig+0x7ae>
+ 800cf04:	2380      	movs	r3, #128	; 0x80
+ 800cf06:	f887 3043 	strb.w	r3, [r7, #67]	; 0x43
+ 800cf0a:	e224      	b.n	800d356 <UART_SetConfig+0x7ae>
+ 800cf0c:	697b      	ldr	r3, [r7, #20]
+ 800cf0e:	681b      	ldr	r3, [r3, #0]
+ 800cf10:	4ab1      	ldr	r2, [pc, #708]	; (800d1d8 <UART_SetConfig+0x630>)
+ 800cf12:	4293      	cmp	r3, r2
+ 800cf14:	d176      	bne.n	800d004 <UART_SetConfig+0x45c>
+ 800cf16:	4bb1      	ldr	r3, [pc, #708]	; (800d1dc <UART_SetConfig+0x634>)
+ 800cf18:	6d5b      	ldr	r3, [r3, #84]	; 0x54
+ 800cf1a:	f003 0338 	and.w	r3, r3, #56	; 0x38
+ 800cf1e:	2b28      	cmp	r3, #40	; 0x28
+ 800cf20:	d86c      	bhi.n	800cffc <UART_SetConfig+0x454>
+ 800cf22:	a201      	add	r2, pc, #4	; (adr r2, 800cf28 <UART_SetConfig+0x380>)
+ 800cf24:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
+ 800cf28:	0800cfcd 	.word	0x0800cfcd
+ 800cf2c:	0800cffd 	.word	0x0800cffd
+ 800cf30:	0800cffd 	.word	0x0800cffd
+ 800cf34:	0800cffd 	.word	0x0800cffd
+ 800cf38:	0800cffd 	.word	0x0800cffd
+ 800cf3c:	0800cffd 	.word	0x0800cffd
+ 800cf40:	0800cffd 	.word	0x0800cffd
+ 800cf44:	0800cffd 	.word	0x0800cffd
+ 800cf48:	0800cfd5 	.word	0x0800cfd5
+ 800cf4c:	0800cffd 	.word	0x0800cffd
+ 800cf50:	0800cffd 	.word	0x0800cffd
+ 800cf54:	0800cffd 	.word	0x0800cffd
+ 800cf58:	0800cffd 	.word	0x0800cffd
+ 800cf5c:	0800cffd 	.word	0x0800cffd
+ 800cf60:	0800cffd 	.word	0x0800cffd
+ 800cf64:	0800cffd 	.word	0x0800cffd
+ 800cf68:	0800cfdd 	.word	0x0800cfdd
+ 800cf6c:	0800cffd 	.word	0x0800cffd
+ 800cf70:	0800cffd 	.word	0x0800cffd
+ 800cf74:	0800cffd 	.word	0x0800cffd
+ 800cf78:	0800cffd 	.word	0x0800cffd
+ 800cf7c:	0800cffd 	.word	0x0800cffd
+ 800cf80:	0800cffd 	.word	0x0800cffd
+ 800cf84:	0800cffd 	.word	0x0800cffd
+ 800cf88:	0800cfe5 	.word	0x0800cfe5
+ 800cf8c:	0800cffd 	.word	0x0800cffd
+ 800cf90:	0800cffd 	.word	0x0800cffd
+ 800cf94:	0800cffd 	.word	0x0800cffd
+ 800cf98:	0800cffd 	.word	0x0800cffd
+ 800cf9c:	0800cffd 	.word	0x0800cffd
+ 800cfa0:	0800cffd 	.word	0x0800cffd
+ 800cfa4:	0800cffd 	.word	0x0800cffd
+ 800cfa8:	0800cfed 	.word	0x0800cfed
+ 800cfac:	0800cffd 	.word	0x0800cffd
+ 800cfb0:	0800cffd 	.word	0x0800cffd
+ 800cfb4:	0800cffd 	.word	0x0800cffd
+ 800cfb8:	0800cffd 	.word	0x0800cffd
+ 800cfbc:	0800cffd 	.word	0x0800cffd
+ 800cfc0:	0800cffd 	.word	0x0800cffd
+ 800cfc4:	0800cffd 	.word	0x0800cffd
+ 800cfc8:	0800cff5 	.word	0x0800cff5
+ 800cfcc:	2301      	movs	r3, #1
+ 800cfce:	f887 3043 	strb.w	r3, [r7, #67]	; 0x43
+ 800cfd2:	e1c0      	b.n	800d356 <UART_SetConfig+0x7ae>
+ 800cfd4:	2304      	movs	r3, #4
+ 800cfd6:	f887 3043 	strb.w	r3, [r7, #67]	; 0x43
+ 800cfda:	e1bc      	b.n	800d356 <UART_SetConfig+0x7ae>
+ 800cfdc:	2308      	movs	r3, #8
+ 800cfde:	f887 3043 	strb.w	r3, [r7, #67]	; 0x43
+ 800cfe2:	e1b8      	b.n	800d356 <UART_SetConfig+0x7ae>
+ 800cfe4:	2310      	movs	r3, #16
+ 800cfe6:	f887 3043 	strb.w	r3, [r7, #67]	; 0x43
+ 800cfea:	e1b4      	b.n	800d356 <UART_SetConfig+0x7ae>
+ 800cfec:	2320      	movs	r3, #32
+ 800cfee:	f887 3043 	strb.w	r3, [r7, #67]	; 0x43
+ 800cff2:	e1b0      	b.n	800d356 <UART_SetConfig+0x7ae>
+ 800cff4:	2340      	movs	r3, #64	; 0x40
+ 800cff6:	f887 3043 	strb.w	r3, [r7, #67]	; 0x43
+ 800cffa:	e1ac      	b.n	800d356 <UART_SetConfig+0x7ae>
+ 800cffc:	2380      	movs	r3, #128	; 0x80
+ 800cffe:	f887 3043 	strb.w	r3, [r7, #67]	; 0x43
+ 800d002:	e1a8      	b.n	800d356 <UART_SetConfig+0x7ae>
+ 800d004:	697b      	ldr	r3, [r7, #20]
+ 800d006:	681b      	ldr	r3, [r3, #0]
+ 800d008:	4a75      	ldr	r2, [pc, #468]	; (800d1e0 <UART_SetConfig+0x638>)
+ 800d00a:	4293      	cmp	r3, r2
+ 800d00c:	d130      	bne.n	800d070 <UART_SetConfig+0x4c8>
+ 800d00e:	4b73      	ldr	r3, [pc, #460]	; (800d1dc <UART_SetConfig+0x634>)
+ 800d010:	6d5b      	ldr	r3, [r3, #84]	; 0x54
+ 800d012:	f003 0307 	and.w	r3, r3, #7
+ 800d016:	2b05      	cmp	r3, #5
+ 800d018:	d826      	bhi.n	800d068 <UART_SetConfig+0x4c0>
+ 800d01a:	a201      	add	r2, pc, #4	; (adr r2, 800d020 <UART_SetConfig+0x478>)
+ 800d01c:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
+ 800d020:	0800d039 	.word	0x0800d039
+ 800d024:	0800d041 	.word	0x0800d041
+ 800d028:	0800d049 	.word	0x0800d049
+ 800d02c:	0800d051 	.word	0x0800d051
+ 800d030:	0800d059 	.word	0x0800d059
+ 800d034:	0800d061 	.word	0x0800d061
+ 800d038:	2300      	movs	r3, #0
+ 800d03a:	f887 3043 	strb.w	r3, [r7, #67]	; 0x43
+ 800d03e:	e18a      	b.n	800d356 <UART_SetConfig+0x7ae>
+ 800d040:	2304      	movs	r3, #4
+ 800d042:	f887 3043 	strb.w	r3, [r7, #67]	; 0x43
+ 800d046:	e186      	b.n	800d356 <UART_SetConfig+0x7ae>
+ 800d048:	2308      	movs	r3, #8
+ 800d04a:	f887 3043 	strb.w	r3, [r7, #67]	; 0x43
+ 800d04e:	e182      	b.n	800d356 <UART_SetConfig+0x7ae>
+ 800d050:	2310      	movs	r3, #16
+ 800d052:	f887 3043 	strb.w	r3, [r7, #67]	; 0x43
+ 800d056:	e17e      	b.n	800d356 <UART_SetConfig+0x7ae>
+ 800d058:	2320      	movs	r3, #32
+ 800d05a:	f887 3043 	strb.w	r3, [r7, #67]	; 0x43
+ 800d05e:	e17a      	b.n	800d356 <UART_SetConfig+0x7ae>
+ 800d060:	2340      	movs	r3, #64	; 0x40
+ 800d062:	f887 3043 	strb.w	r3, [r7, #67]	; 0x43
+ 800d066:	e176      	b.n	800d356 <UART_SetConfig+0x7ae>
+ 800d068:	2380      	movs	r3, #128	; 0x80
+ 800d06a:	f887 3043 	strb.w	r3, [r7, #67]	; 0x43
+ 800d06e:	e172      	b.n	800d356 <UART_SetConfig+0x7ae>
+ 800d070:	697b      	ldr	r3, [r7, #20]
+ 800d072:	681b      	ldr	r3, [r3, #0]
+ 800d074:	4a5b      	ldr	r2, [pc, #364]	; (800d1e4 <UART_SetConfig+0x63c>)
+ 800d076:	4293      	cmp	r3, r2
+ 800d078:	d130      	bne.n	800d0dc <UART_SetConfig+0x534>
+ 800d07a:	4b58      	ldr	r3, [pc, #352]	; (800d1dc <UART_SetConfig+0x634>)
+ 800d07c:	6d5b      	ldr	r3, [r3, #84]	; 0x54
+ 800d07e:	f003 0307 	and.w	r3, r3, #7
+ 800d082:	2b05      	cmp	r3, #5
+ 800d084:	d826      	bhi.n	800d0d4 <UART_SetConfig+0x52c>
+ 800d086:	a201      	add	r2, pc, #4	; (adr r2, 800d08c <UART_SetConfig+0x4e4>)
+ 800d088:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
+ 800d08c:	0800d0a5 	.word	0x0800d0a5
+ 800d090:	0800d0ad 	.word	0x0800d0ad
+ 800d094:	0800d0b5 	.word	0x0800d0b5
+ 800d098:	0800d0bd 	.word	0x0800d0bd
+ 800d09c:	0800d0c5 	.word	0x0800d0c5
+ 800d0a0:	0800d0cd 	.word	0x0800d0cd
+ 800d0a4:	2300      	movs	r3, #0
+ 800d0a6:	f887 3043 	strb.w	r3, [r7, #67]	; 0x43
+ 800d0aa:	e154      	b.n	800d356 <UART_SetConfig+0x7ae>
+ 800d0ac:	2304      	movs	r3, #4
+ 800d0ae:	f887 3043 	strb.w	r3, [r7, #67]	; 0x43
+ 800d0b2:	e150      	b.n	800d356 <UART_SetConfig+0x7ae>
+ 800d0b4:	2308      	movs	r3, #8
+ 800d0b6:	f887 3043 	strb.w	r3, [r7, #67]	; 0x43
+ 800d0ba:	e14c      	b.n	800d356 <UART_SetConfig+0x7ae>
+ 800d0bc:	2310      	movs	r3, #16
+ 800d0be:	f887 3043 	strb.w	r3, [r7, #67]	; 0x43
+ 800d0c2:	e148      	b.n	800d356 <UART_SetConfig+0x7ae>
+ 800d0c4:	2320      	movs	r3, #32
+ 800d0c6:	f887 3043 	strb.w	r3, [r7, #67]	; 0x43
+ 800d0ca:	e144      	b.n	800d356 <UART_SetConfig+0x7ae>
+ 800d0cc:	2340      	movs	r3, #64	; 0x40
+ 800d0ce:	f887 3043 	strb.w	r3, [r7, #67]	; 0x43
+ 800d0d2:	e140      	b.n	800d356 <UART_SetConfig+0x7ae>
+ 800d0d4:	2380      	movs	r3, #128	; 0x80
+ 800d0d6:	f887 3043 	strb.w	r3, [r7, #67]	; 0x43
+ 800d0da:	e13c      	b.n	800d356 <UART_SetConfig+0x7ae>
+ 800d0dc:	697b      	ldr	r3, [r7, #20]
+ 800d0de:	681b      	ldr	r3, [r3, #0]
+ 800d0e0:	4a41      	ldr	r2, [pc, #260]	; (800d1e8 <UART_SetConfig+0x640>)
+ 800d0e2:	4293      	cmp	r3, r2
+ 800d0e4:	f040 8082 	bne.w	800d1ec <UART_SetConfig+0x644>
+ 800d0e8:	4b3c      	ldr	r3, [pc, #240]	; (800d1dc <UART_SetConfig+0x634>)
+ 800d0ea:	6d5b      	ldr	r3, [r3, #84]	; 0x54
+ 800d0ec:	f003 0338 	and.w	r3, r3, #56	; 0x38
+ 800d0f0:	2b28      	cmp	r3, #40	; 0x28
+ 800d0f2:	d86d      	bhi.n	800d1d0 <UART_SetConfig+0x628>
+ 800d0f4:	a201      	add	r2, pc, #4	; (adr r2, 800d0fc <UART_SetConfig+0x554>)
+ 800d0f6:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
+ 800d0fa:	bf00      	nop
+ 800d0fc:	0800d1a1 	.word	0x0800d1a1
+ 800d100:	0800d1d1 	.word	0x0800d1d1
+ 800d104:	0800d1d1 	.word	0x0800d1d1
+ 800d108:	0800d1d1 	.word	0x0800d1d1
+ 800d10c:	0800d1d1 	.word	0x0800d1d1
+ 800d110:	0800d1d1 	.word	0x0800d1d1
+ 800d114:	0800d1d1 	.word	0x0800d1d1
+ 800d118:	0800d1d1 	.word	0x0800d1d1
+ 800d11c:	0800d1a9 	.word	0x0800d1a9
+ 800d120:	0800d1d1 	.word	0x0800d1d1
+ 800d124:	0800d1d1 	.word	0x0800d1d1
+ 800d128:	0800d1d1 	.word	0x0800d1d1
+ 800d12c:	0800d1d1 	.word	0x0800d1d1
+ 800d130:	0800d1d1 	.word	0x0800d1d1
+ 800d134:	0800d1d1 	.word	0x0800d1d1
+ 800d138:	0800d1d1 	.word	0x0800d1d1
+ 800d13c:	0800d1b1 	.word	0x0800d1b1
+ 800d140:	0800d1d1 	.word	0x0800d1d1
+ 800d144:	0800d1d1 	.word	0x0800d1d1
+ 800d148:	0800d1d1 	.word	0x0800d1d1
+ 800d14c:	0800d1d1 	.word	0x0800d1d1
+ 800d150:	0800d1d1 	.word	0x0800d1d1
+ 800d154:	0800d1d1 	.word	0x0800d1d1
+ 800d158:	0800d1d1 	.word	0x0800d1d1
+ 800d15c:	0800d1b9 	.word	0x0800d1b9
+ 800d160:	0800d1d1 	.word	0x0800d1d1
+ 800d164:	0800d1d1 	.word	0x0800d1d1
+ 800d168:	0800d1d1 	.word	0x0800d1d1
+ 800d16c:	0800d1d1 	.word	0x0800d1d1
+ 800d170:	0800d1d1 	.word	0x0800d1d1
+ 800d174:	0800d1d1 	.word	0x0800d1d1
+ 800d178:	0800d1d1 	.word	0x0800d1d1
+ 800d17c:	0800d1c1 	.word	0x0800d1c1
+ 800d180:	0800d1d1 	.word	0x0800d1d1
+ 800d184:	0800d1d1 	.word	0x0800d1d1
+ 800d188:	0800d1d1 	.word	0x0800d1d1
+ 800d18c:	0800d1d1 	.word	0x0800d1d1
+ 800d190:	0800d1d1 	.word	0x0800d1d1
+ 800d194:	0800d1d1 	.word	0x0800d1d1
+ 800d198:	0800d1d1 	.word	0x0800d1d1
+ 800d19c:	0800d1c9 	.word	0x0800d1c9
+ 800d1a0:	2301      	movs	r3, #1
+ 800d1a2:	f887 3043 	strb.w	r3, [r7, #67]	; 0x43
+ 800d1a6:	e0d6      	b.n	800d356 <UART_SetConfig+0x7ae>
+ 800d1a8:	2304      	movs	r3, #4
+ 800d1aa:	f887 3043 	strb.w	r3, [r7, #67]	; 0x43
+ 800d1ae:	e0d2      	b.n	800d356 <UART_SetConfig+0x7ae>
+ 800d1b0:	2308      	movs	r3, #8
+ 800d1b2:	f887 3043 	strb.w	r3, [r7, #67]	; 0x43
+ 800d1b6:	e0ce      	b.n	800d356 <UART_SetConfig+0x7ae>
+ 800d1b8:	2310      	movs	r3, #16
+ 800d1ba:	f887 3043 	strb.w	r3, [r7, #67]	; 0x43
+ 800d1be:	e0ca      	b.n	800d356 <UART_SetConfig+0x7ae>
+ 800d1c0:	2320      	movs	r3, #32
+ 800d1c2:	f887 3043 	strb.w	r3, [r7, #67]	; 0x43
+ 800d1c6:	e0c6      	b.n	800d356 <UART_SetConfig+0x7ae>
+ 800d1c8:	2340      	movs	r3, #64	; 0x40
+ 800d1ca:	f887 3043 	strb.w	r3, [r7, #67]	; 0x43
+ 800d1ce:	e0c2      	b.n	800d356 <UART_SetConfig+0x7ae>
+ 800d1d0:	2380      	movs	r3, #128	; 0x80
+ 800d1d2:	f887 3043 	strb.w	r3, [r7, #67]	; 0x43
+ 800d1d6:	e0be      	b.n	800d356 <UART_SetConfig+0x7ae>
+ 800d1d8:	40011400 	.word	0x40011400
+ 800d1dc:	58024400 	.word	0x58024400
+ 800d1e0:	40007800 	.word	0x40007800
+ 800d1e4:	40007c00 	.word	0x40007c00
+ 800d1e8:	40011800 	.word	0x40011800
+ 800d1ec:	697b      	ldr	r3, [r7, #20]
+ 800d1ee:	681b      	ldr	r3, [r3, #0]
+ 800d1f0:	4aad      	ldr	r2, [pc, #692]	; (800d4a8 <UART_SetConfig+0x900>)
+ 800d1f2:	4293      	cmp	r3, r2
+ 800d1f4:	d176      	bne.n	800d2e4 <UART_SetConfig+0x73c>
+ 800d1f6:	4bad      	ldr	r3, [pc, #692]	; (800d4ac <UART_SetConfig+0x904>)
+ 800d1f8:	6d5b      	ldr	r3, [r3, #84]	; 0x54
+ 800d1fa:	f003 0338 	and.w	r3, r3, #56	; 0x38
+ 800d1fe:	2b28      	cmp	r3, #40	; 0x28
+ 800d200:	d86c      	bhi.n	800d2dc <UART_SetConfig+0x734>
+ 800d202:	a201      	add	r2, pc, #4	; (adr r2, 800d208 <UART_SetConfig+0x660>)
+ 800d204:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
+ 800d208:	0800d2ad 	.word	0x0800d2ad
+ 800d20c:	0800d2dd 	.word	0x0800d2dd
+ 800d210:	0800d2dd 	.word	0x0800d2dd
+ 800d214:	0800d2dd 	.word	0x0800d2dd
+ 800d218:	0800d2dd 	.word	0x0800d2dd
+ 800d21c:	0800d2dd 	.word	0x0800d2dd
+ 800d220:	0800d2dd 	.word	0x0800d2dd
+ 800d224:	0800d2dd 	.word	0x0800d2dd
+ 800d228:	0800d2b5 	.word	0x0800d2b5
+ 800d22c:	0800d2dd 	.word	0x0800d2dd
+ 800d230:	0800d2dd 	.word	0x0800d2dd
+ 800d234:	0800d2dd 	.word	0x0800d2dd
+ 800d238:	0800d2dd 	.word	0x0800d2dd
+ 800d23c:	0800d2dd 	.word	0x0800d2dd
+ 800d240:	0800d2dd 	.word	0x0800d2dd
+ 800d244:	0800d2dd 	.word	0x0800d2dd
+ 800d248:	0800d2bd 	.word	0x0800d2bd
+ 800d24c:	0800d2dd 	.word	0x0800d2dd
+ 800d250:	0800d2dd 	.word	0x0800d2dd
+ 800d254:	0800d2dd 	.word	0x0800d2dd
+ 800d258:	0800d2dd 	.word	0x0800d2dd
+ 800d25c:	0800d2dd 	.word	0x0800d2dd
+ 800d260:	0800d2dd 	.word	0x0800d2dd
+ 800d264:	0800d2dd 	.word	0x0800d2dd
+ 800d268:	0800d2c5 	.word	0x0800d2c5
+ 800d26c:	0800d2dd 	.word	0x0800d2dd
+ 800d270:	0800d2dd 	.word	0x0800d2dd
+ 800d274:	0800d2dd 	.word	0x0800d2dd
+ 800d278:	0800d2dd 	.word	0x0800d2dd
+ 800d27c:	0800d2dd 	.word	0x0800d2dd
+ 800d280:	0800d2dd 	.word	0x0800d2dd
+ 800d284:	0800d2dd 	.word	0x0800d2dd
+ 800d288:	0800d2cd 	.word	0x0800d2cd
+ 800d28c:	0800d2dd 	.word	0x0800d2dd
+ 800d290:	0800d2dd 	.word	0x0800d2dd
+ 800d294:	0800d2dd 	.word	0x0800d2dd
+ 800d298:	0800d2dd 	.word	0x0800d2dd
+ 800d29c:	0800d2dd 	.word	0x0800d2dd
+ 800d2a0:	0800d2dd 	.word	0x0800d2dd
+ 800d2a4:	0800d2dd 	.word	0x0800d2dd
+ 800d2a8:	0800d2d5 	.word	0x0800d2d5
+ 800d2ac:	2301      	movs	r3, #1
+ 800d2ae:	f887 3043 	strb.w	r3, [r7, #67]	; 0x43
+ 800d2b2:	e050      	b.n	800d356 <UART_SetConfig+0x7ae>
+ 800d2b4:	2304      	movs	r3, #4
+ 800d2b6:	f887 3043 	strb.w	r3, [r7, #67]	; 0x43
+ 800d2ba:	e04c      	b.n	800d356 <UART_SetConfig+0x7ae>
+ 800d2bc:	2308      	movs	r3, #8
+ 800d2be:	f887 3043 	strb.w	r3, [r7, #67]	; 0x43
+ 800d2c2:	e048      	b.n	800d356 <UART_SetConfig+0x7ae>
+ 800d2c4:	2310      	movs	r3, #16
+ 800d2c6:	f887 3043 	strb.w	r3, [r7, #67]	; 0x43
+ 800d2ca:	e044      	b.n	800d356 <UART_SetConfig+0x7ae>
+ 800d2cc:	2320      	movs	r3, #32
+ 800d2ce:	f887 3043 	strb.w	r3, [r7, #67]	; 0x43
+ 800d2d2:	e040      	b.n	800d356 <UART_SetConfig+0x7ae>
+ 800d2d4:	2340      	movs	r3, #64	; 0x40
+ 800d2d6:	f887 3043 	strb.w	r3, [r7, #67]	; 0x43
+ 800d2da:	e03c      	b.n	800d356 <UART_SetConfig+0x7ae>
+ 800d2dc:	2380      	movs	r3, #128	; 0x80
+ 800d2de:	f887 3043 	strb.w	r3, [r7, #67]	; 0x43
+ 800d2e2:	e038      	b.n	800d356 <UART_SetConfig+0x7ae>
+ 800d2e4:	697b      	ldr	r3, [r7, #20]
+ 800d2e6:	681b      	ldr	r3, [r3, #0]
+ 800d2e8:	4a71      	ldr	r2, [pc, #452]	; (800d4b0 <UART_SetConfig+0x908>)
+ 800d2ea:	4293      	cmp	r3, r2
+ 800d2ec:	d130      	bne.n	800d350 <UART_SetConfig+0x7a8>
+ 800d2ee:	4b6f      	ldr	r3, [pc, #444]	; (800d4ac <UART_SetConfig+0x904>)
+ 800d2f0:	6d9b      	ldr	r3, [r3, #88]	; 0x58
+ 800d2f2:	f003 0307 	and.w	r3, r3, #7
+ 800d2f6:	2b05      	cmp	r3, #5
+ 800d2f8:	d826      	bhi.n	800d348 <UART_SetConfig+0x7a0>
+ 800d2fa:	a201      	add	r2, pc, #4	; (adr r2, 800d300 <UART_SetConfig+0x758>)
+ 800d2fc:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
+ 800d300:	0800d319 	.word	0x0800d319
+ 800d304:	0800d321 	.word	0x0800d321
+ 800d308:	0800d329 	.word	0x0800d329
+ 800d30c:	0800d331 	.word	0x0800d331
+ 800d310:	0800d339 	.word	0x0800d339
+ 800d314:	0800d341 	.word	0x0800d341
+ 800d318:	2302      	movs	r3, #2
+ 800d31a:	f887 3043 	strb.w	r3, [r7, #67]	; 0x43
+ 800d31e:	e01a      	b.n	800d356 <UART_SetConfig+0x7ae>
+ 800d320:	2304      	movs	r3, #4
+ 800d322:	f887 3043 	strb.w	r3, [r7, #67]	; 0x43
+ 800d326:	e016      	b.n	800d356 <UART_SetConfig+0x7ae>
+ 800d328:	2308      	movs	r3, #8
+ 800d32a:	f887 3043 	strb.w	r3, [r7, #67]	; 0x43
+ 800d32e:	e012      	b.n	800d356 <UART_SetConfig+0x7ae>
+ 800d330:	2310      	movs	r3, #16
+ 800d332:	f887 3043 	strb.w	r3, [r7, #67]	; 0x43
+ 800d336:	e00e      	b.n	800d356 <UART_SetConfig+0x7ae>
+ 800d338:	2320      	movs	r3, #32
+ 800d33a:	f887 3043 	strb.w	r3, [r7, #67]	; 0x43
+ 800d33e:	e00a      	b.n	800d356 <UART_SetConfig+0x7ae>
+ 800d340:	2340      	movs	r3, #64	; 0x40
+ 800d342:	f887 3043 	strb.w	r3, [r7, #67]	; 0x43
+ 800d346:	e006      	b.n	800d356 <UART_SetConfig+0x7ae>
+ 800d348:	2380      	movs	r3, #128	; 0x80
+ 800d34a:	f887 3043 	strb.w	r3, [r7, #67]	; 0x43
+ 800d34e:	e002      	b.n	800d356 <UART_SetConfig+0x7ae>
+ 800d350:	2380      	movs	r3, #128	; 0x80
+ 800d352:	f887 3043 	strb.w	r3, [r7, #67]	; 0x43
+
+  /* Check LPUART instance */
+  if (UART_INSTANCE_LOWPOWER(huart))
+ 800d356:	697b      	ldr	r3, [r7, #20]
+ 800d358:	681b      	ldr	r3, [r3, #0]
+ 800d35a:	4a55      	ldr	r2, [pc, #340]	; (800d4b0 <UART_SetConfig+0x908>)
+ 800d35c:	4293      	cmp	r3, r2
+ 800d35e:	f040 80f8 	bne.w	800d552 <UART_SetConfig+0x9aa>
+  {
+    /* Retrieve frequency clock */
+    switch (clocksource)
+ 800d362:	f897 3043 	ldrb.w	r3, [r7, #67]	; 0x43
+ 800d366:	2b20      	cmp	r3, #32
+ 800d368:	dc46      	bgt.n	800d3f8 <UART_SetConfig+0x850>
+ 800d36a:	2b02      	cmp	r3, #2
+ 800d36c:	db75      	blt.n	800d45a <UART_SetConfig+0x8b2>
+ 800d36e:	3b02      	subs	r3, #2
+ 800d370:	2b1e      	cmp	r3, #30
+ 800d372:	d872      	bhi.n	800d45a <UART_SetConfig+0x8b2>
+ 800d374:	a201      	add	r2, pc, #4	; (adr r2, 800d37c <UART_SetConfig+0x7d4>)
+ 800d376:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
+ 800d37a:	bf00      	nop
+ 800d37c:	0800d3ff 	.word	0x0800d3ff
+ 800d380:	0800d45b 	.word	0x0800d45b
+ 800d384:	0800d407 	.word	0x0800d407
+ 800d388:	0800d45b 	.word	0x0800d45b
+ 800d38c:	0800d45b 	.word	0x0800d45b
+ 800d390:	0800d45b 	.word	0x0800d45b
+ 800d394:	0800d417 	.word	0x0800d417
+ 800d398:	0800d45b 	.word	0x0800d45b
+ 800d39c:	0800d45b 	.word	0x0800d45b
+ 800d3a0:	0800d45b 	.word	0x0800d45b
+ 800d3a4:	0800d45b 	.word	0x0800d45b
+ 800d3a8:	0800d45b 	.word	0x0800d45b
+ 800d3ac:	0800d45b 	.word	0x0800d45b
+ 800d3b0:	0800d45b 	.word	0x0800d45b
+ 800d3b4:	0800d427 	.word	0x0800d427
+ 800d3b8:	0800d45b 	.word	0x0800d45b
+ 800d3bc:	0800d45b 	.word	0x0800d45b
+ 800d3c0:	0800d45b 	.word	0x0800d45b
+ 800d3c4:	0800d45b 	.word	0x0800d45b
+ 800d3c8:	0800d45b 	.word	0x0800d45b
+ 800d3cc:	0800d45b 	.word	0x0800d45b
+ 800d3d0:	0800d45b 	.word	0x0800d45b
+ 800d3d4:	0800d45b 	.word	0x0800d45b
+ 800d3d8:	0800d45b 	.word	0x0800d45b
+ 800d3dc:	0800d45b 	.word	0x0800d45b
+ 800d3e0:	0800d45b 	.word	0x0800d45b
+ 800d3e4:	0800d45b 	.word	0x0800d45b
+ 800d3e8:	0800d45b 	.word	0x0800d45b
+ 800d3ec:	0800d45b 	.word	0x0800d45b
+ 800d3f0:	0800d45b 	.word	0x0800d45b
+ 800d3f4:	0800d44d 	.word	0x0800d44d
+ 800d3f8:	2b40      	cmp	r3, #64	; 0x40
+ 800d3fa:	d02a      	beq.n	800d452 <UART_SetConfig+0x8aa>
+ 800d3fc:	e02d      	b.n	800d45a <UART_SetConfig+0x8b2>
+    {
+      case UART_CLOCKSOURCE_D3PCLK1:
+        pclk = HAL_RCCEx_GetD3PCLK1Freq();
+ 800d3fe:	f7fc fc8f 	bl	8009d20 <HAL_RCCEx_GetD3PCLK1Freq>
+ 800d402:	63f8      	str	r0, [r7, #60]	; 0x3c
+        break;
+ 800d404:	e02f      	b.n	800d466 <UART_SetConfig+0x8be>
+      case UART_CLOCKSOURCE_PLL2:
+        HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
+ 800d406:	f107 0324 	add.w	r3, r7, #36	; 0x24
+ 800d40a:	4618      	mov	r0, r3
+ 800d40c:	f7fc fc9e 	bl	8009d4c <HAL_RCCEx_GetPLL2ClockFreq>
+        pclk = pll2_clocks.PLL2_Q_Frequency;
+ 800d410:	6abb      	ldr	r3, [r7, #40]	; 0x28
+ 800d412:	63fb      	str	r3, [r7, #60]	; 0x3c
+        break;
+ 800d414:	e027      	b.n	800d466 <UART_SetConfig+0x8be>
+      case UART_CLOCKSOURCE_PLL3:
+        HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
+ 800d416:	f107 0318 	add.w	r3, r7, #24
+ 800d41a:	4618      	mov	r0, r3
+ 800d41c:	f7fc fdea 	bl	8009ff4 <HAL_RCCEx_GetPLL3ClockFreq>
+        pclk = pll3_clocks.PLL3_Q_Frequency;
+ 800d420:	69fb      	ldr	r3, [r7, #28]
+ 800d422:	63fb      	str	r3, [r7, #60]	; 0x3c
+        break;
+ 800d424:	e01f      	b.n	800d466 <UART_SetConfig+0x8be>
+      case UART_CLOCKSOURCE_HSI:
+        if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
+ 800d426:	4b21      	ldr	r3, [pc, #132]	; (800d4ac <UART_SetConfig+0x904>)
+ 800d428:	681b      	ldr	r3, [r3, #0]
+ 800d42a:	f003 0320 	and.w	r3, r3, #32
+ 800d42e:	2b00      	cmp	r3, #0
+ 800d430:	d009      	beq.n	800d446 <UART_SetConfig+0x89e>
+        {
+          pclk = (uint32_t)(HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3U));
+ 800d432:	4b1e      	ldr	r3, [pc, #120]	; (800d4ac <UART_SetConfig+0x904>)
+ 800d434:	681b      	ldr	r3, [r3, #0]
+ 800d436:	08db      	lsrs	r3, r3, #3
+ 800d438:	f003 0303 	and.w	r3, r3, #3
+ 800d43c:	4a1d      	ldr	r2, [pc, #116]	; (800d4b4 <UART_SetConfig+0x90c>)
+ 800d43e:	fa22 f303 	lsr.w	r3, r2, r3
+ 800d442:	63fb      	str	r3, [r7, #60]	; 0x3c
+        }
+        else
+        {
+          pclk = (uint32_t) HSI_VALUE;
+        }
+        break;
+ 800d444:	e00f      	b.n	800d466 <UART_SetConfig+0x8be>
+          pclk = (uint32_t) HSI_VALUE;
+ 800d446:	4b1b      	ldr	r3, [pc, #108]	; (800d4b4 <UART_SetConfig+0x90c>)
+ 800d448:	63fb      	str	r3, [r7, #60]	; 0x3c
+        break;
+ 800d44a:	e00c      	b.n	800d466 <UART_SetConfig+0x8be>
+      case UART_CLOCKSOURCE_CSI:
+        pclk = (uint32_t) CSI_VALUE;
+ 800d44c:	4b1a      	ldr	r3, [pc, #104]	; (800d4b8 <UART_SetConfig+0x910>)
+ 800d44e:	63fb      	str	r3, [r7, #60]	; 0x3c
+        break;
+ 800d450:	e009      	b.n	800d466 <UART_SetConfig+0x8be>
+      case UART_CLOCKSOURCE_LSE:
+        pclk = (uint32_t) LSE_VALUE;
+ 800d452:	f44f 4300 	mov.w	r3, #32768	; 0x8000
+ 800d456:	63fb      	str	r3, [r7, #60]	; 0x3c
+        break;
+ 800d458:	e005      	b.n	800d466 <UART_SetConfig+0x8be>
+      default:
+        pclk = 0U;
+ 800d45a:	2300      	movs	r3, #0
+ 800d45c:	63fb      	str	r3, [r7, #60]	; 0x3c
+        ret = HAL_ERROR;
+ 800d45e:	2301      	movs	r3, #1
+ 800d460:	f887 3042 	strb.w	r3, [r7, #66]	; 0x42
+        break;
+ 800d464:	bf00      	nop
+    }
+
+    /* If proper clock source reported */
+    if (pclk != 0U)
+ 800d466:	6bfb      	ldr	r3, [r7, #60]	; 0x3c
+ 800d468:	2b00      	cmp	r3, #0
+ 800d46a:	f000 81ee 	beq.w	800d84a <UART_SetConfig+0xca2>
+    {
+      /* Compute clock after Prescaler */
+      lpuart_ker_ck_pres = (pclk / UARTPrescTable[huart->Init.ClockPrescaler]);
+ 800d46e:	697b      	ldr	r3, [r7, #20]
+ 800d470:	6a5b      	ldr	r3, [r3, #36]	; 0x24
+ 800d472:	4a12      	ldr	r2, [pc, #72]	; (800d4bc <UART_SetConfig+0x914>)
+ 800d474:	f832 3013 	ldrh.w	r3, [r2, r3, lsl #1]
+ 800d478:	461a      	mov	r2, r3
+ 800d47a:	6bfb      	ldr	r3, [r7, #60]	; 0x3c
+ 800d47c:	fbb3 f3f2 	udiv	r3, r3, r2
+ 800d480:	633b      	str	r3, [r7, #48]	; 0x30
+
+      /* Ensure that Frequency clock is in the range [3 * baudrate, 4096 * baudrate] */
+      if ((lpuart_ker_ck_pres < (3U * huart->Init.BaudRate)) ||
+ 800d482:	697b      	ldr	r3, [r7, #20]
+ 800d484:	685a      	ldr	r2, [r3, #4]
+ 800d486:	4613      	mov	r3, r2
+ 800d488:	005b      	lsls	r3, r3, #1
+ 800d48a:	4413      	add	r3, r2
+ 800d48c:	6b3a      	ldr	r2, [r7, #48]	; 0x30
+ 800d48e:	429a      	cmp	r2, r3
+ 800d490:	d305      	bcc.n	800d49e <UART_SetConfig+0x8f6>
+          (lpuart_ker_ck_pres > (4096U * huart->Init.BaudRate)))
+ 800d492:	697b      	ldr	r3, [r7, #20]
+ 800d494:	685b      	ldr	r3, [r3, #4]
+ 800d496:	031b      	lsls	r3, r3, #12
+      if ((lpuart_ker_ck_pres < (3U * huart->Init.BaudRate)) ||
+ 800d498:	6b3a      	ldr	r2, [r7, #48]	; 0x30
+ 800d49a:	429a      	cmp	r2, r3
+ 800d49c:	d910      	bls.n	800d4c0 <UART_SetConfig+0x918>
+      {
+        ret = HAL_ERROR;
+ 800d49e:	2301      	movs	r3, #1
+ 800d4a0:	f887 3042 	strb.w	r3, [r7, #66]	; 0x42
+ 800d4a4:	e1d1      	b.n	800d84a <UART_SetConfig+0xca2>
+ 800d4a6:	bf00      	nop
+ 800d4a8:	40011c00 	.word	0x40011c00
+ 800d4ac:	58024400 	.word	0x58024400
+ 800d4b0:	58000c00 	.word	0x58000c00
+ 800d4b4:	03d09000 	.word	0x03d09000
+ 800d4b8:	003d0900 	.word	0x003d0900
+ 800d4bc:	08026b58 	.word	0x08026b58
+      }
+      else
+      {
+        /* Check computed UsartDiv value is in allocated range
+           (it is forbidden to write values lower than 0x300 in the LPUART_BRR register) */
+        usartdiv = (uint32_t)(UART_DIV_LPUART(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
+ 800d4c0:	6bfb      	ldr	r3, [r7, #60]	; 0x3c
+ 800d4c2:	2200      	movs	r2, #0
+ 800d4c4:	60bb      	str	r3, [r7, #8]
+ 800d4c6:	60fa      	str	r2, [r7, #12]
+ 800d4c8:	697b      	ldr	r3, [r7, #20]
+ 800d4ca:	6a5b      	ldr	r3, [r3, #36]	; 0x24
+ 800d4cc:	4ac0      	ldr	r2, [pc, #768]	; (800d7d0 <UART_SetConfig+0xc28>)
+ 800d4ce:	f832 3013 	ldrh.w	r3, [r2, r3, lsl #1]
+ 800d4d2:	b29b      	uxth	r3, r3
+ 800d4d4:	2200      	movs	r2, #0
+ 800d4d6:	603b      	str	r3, [r7, #0]
+ 800d4d8:	607a      	str	r2, [r7, #4]
+ 800d4da:	e9d7 2300 	ldrd	r2, r3, [r7]
+ 800d4de:	e9d7 0102 	ldrd	r0, r1, [r7, #8]
+ 800d4e2:	f7f2 ff7d 	bl	80003e0 <__aeabi_uldivmod>
+ 800d4e6:	4602      	mov	r2, r0
+ 800d4e8:	460b      	mov	r3, r1
+ 800d4ea:	4610      	mov	r0, r2
+ 800d4ec:	4619      	mov	r1, r3
+ 800d4ee:	f04f 0200 	mov.w	r2, #0
+ 800d4f2:	f04f 0300 	mov.w	r3, #0
+ 800d4f6:	020b      	lsls	r3, r1, #8
+ 800d4f8:	ea43 6310 	orr.w	r3, r3, r0, lsr #24
+ 800d4fc:	0202      	lsls	r2, r0, #8
+ 800d4fe:	6979      	ldr	r1, [r7, #20]
+ 800d500:	6849      	ldr	r1, [r1, #4]
+ 800d502:	0849      	lsrs	r1, r1, #1
+ 800d504:	2000      	movs	r0, #0
+ 800d506:	460c      	mov	r4, r1
+ 800d508:	4605      	mov	r5, r0
+ 800d50a:	eb12 0804 	adds.w	r8, r2, r4
+ 800d50e:	eb43 0905 	adc.w	r9, r3, r5
+ 800d512:	697b      	ldr	r3, [r7, #20]
+ 800d514:	685b      	ldr	r3, [r3, #4]
+ 800d516:	2200      	movs	r2, #0
+ 800d518:	469a      	mov	sl, r3
+ 800d51a:	4693      	mov	fp, r2
+ 800d51c:	4652      	mov	r2, sl
+ 800d51e:	465b      	mov	r3, fp
+ 800d520:	4640      	mov	r0, r8
+ 800d522:	4649      	mov	r1, r9
+ 800d524:	f7f2 ff5c 	bl	80003e0 <__aeabi_uldivmod>
+ 800d528:	4602      	mov	r2, r0
+ 800d52a:	460b      	mov	r3, r1
+ 800d52c:	4613      	mov	r3, r2
+ 800d52e:	63bb      	str	r3, [r7, #56]	; 0x38
+        if ((usartdiv >= LPUART_BRR_MIN) && (usartdiv <= LPUART_BRR_MAX))
+ 800d530:	6bbb      	ldr	r3, [r7, #56]	; 0x38
+ 800d532:	f5b3 7f40 	cmp.w	r3, #768	; 0x300
+ 800d536:	d308      	bcc.n	800d54a <UART_SetConfig+0x9a2>
+ 800d538:	6bbb      	ldr	r3, [r7, #56]	; 0x38
+ 800d53a:	f5b3 1f80 	cmp.w	r3, #1048576	; 0x100000
+ 800d53e:	d204      	bcs.n	800d54a <UART_SetConfig+0x9a2>
+        {
+          huart->Instance->BRR = usartdiv;
+ 800d540:	697b      	ldr	r3, [r7, #20]
+ 800d542:	681b      	ldr	r3, [r3, #0]
+ 800d544:	6bba      	ldr	r2, [r7, #56]	; 0x38
+ 800d546:	60da      	str	r2, [r3, #12]
+ 800d548:	e17f      	b.n	800d84a <UART_SetConfig+0xca2>
+        }
+        else
+        {
+          ret = HAL_ERROR;
+ 800d54a:	2301      	movs	r3, #1
+ 800d54c:	f887 3042 	strb.w	r3, [r7, #66]	; 0x42
+ 800d550:	e17b      	b.n	800d84a <UART_SetConfig+0xca2>
+      } /* if ( (lpuart_ker_ck_pres < (3 * huart->Init.BaudRate) ) ||
+                (lpuart_ker_ck_pres > (4096 * huart->Init.BaudRate) )) */
+    } /* if (pclk != 0) */
+  }
+  /* Check UART Over Sampling to set Baud Rate Register */
+  else if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
+ 800d552:	697b      	ldr	r3, [r7, #20]
+ 800d554:	69db      	ldr	r3, [r3, #28]
+ 800d556:	f5b3 4f00 	cmp.w	r3, #32768	; 0x8000
+ 800d55a:	f040 80bd 	bne.w	800d6d8 <UART_SetConfig+0xb30>
+  {
+    switch (clocksource)
+ 800d55e:	f897 3043 	ldrb.w	r3, [r7, #67]	; 0x43
+ 800d562:	2b20      	cmp	r3, #32
+ 800d564:	dc48      	bgt.n	800d5f8 <UART_SetConfig+0xa50>
+ 800d566:	2b00      	cmp	r3, #0
+ 800d568:	db7b      	blt.n	800d662 <UART_SetConfig+0xaba>
+ 800d56a:	2b20      	cmp	r3, #32
+ 800d56c:	d879      	bhi.n	800d662 <UART_SetConfig+0xaba>
+ 800d56e:	a201      	add	r2, pc, #4	; (adr r2, 800d574 <UART_SetConfig+0x9cc>)
+ 800d570:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
+ 800d574:	0800d5ff 	.word	0x0800d5ff
+ 800d578:	0800d607 	.word	0x0800d607
+ 800d57c:	0800d663 	.word	0x0800d663
+ 800d580:	0800d663 	.word	0x0800d663
+ 800d584:	0800d60f 	.word	0x0800d60f
+ 800d588:	0800d663 	.word	0x0800d663
+ 800d58c:	0800d663 	.word	0x0800d663
+ 800d590:	0800d663 	.word	0x0800d663
+ 800d594:	0800d61f 	.word	0x0800d61f
+ 800d598:	0800d663 	.word	0x0800d663
+ 800d59c:	0800d663 	.word	0x0800d663
+ 800d5a0:	0800d663 	.word	0x0800d663
+ 800d5a4:	0800d663 	.word	0x0800d663
+ 800d5a8:	0800d663 	.word	0x0800d663
+ 800d5ac:	0800d663 	.word	0x0800d663
+ 800d5b0:	0800d663 	.word	0x0800d663
+ 800d5b4:	0800d62f 	.word	0x0800d62f
+ 800d5b8:	0800d663 	.word	0x0800d663
+ 800d5bc:	0800d663 	.word	0x0800d663
+ 800d5c0:	0800d663 	.word	0x0800d663
+ 800d5c4:	0800d663 	.word	0x0800d663
+ 800d5c8:	0800d663 	.word	0x0800d663
+ 800d5cc:	0800d663 	.word	0x0800d663
+ 800d5d0:	0800d663 	.word	0x0800d663
+ 800d5d4:	0800d663 	.word	0x0800d663
+ 800d5d8:	0800d663 	.word	0x0800d663
+ 800d5dc:	0800d663 	.word	0x0800d663
+ 800d5e0:	0800d663 	.word	0x0800d663
+ 800d5e4:	0800d663 	.word	0x0800d663
+ 800d5e8:	0800d663 	.word	0x0800d663
+ 800d5ec:	0800d663 	.word	0x0800d663
+ 800d5f0:	0800d663 	.word	0x0800d663
+ 800d5f4:	0800d655 	.word	0x0800d655
+ 800d5f8:	2b40      	cmp	r3, #64	; 0x40
+ 800d5fa:	d02e      	beq.n	800d65a <UART_SetConfig+0xab2>
+ 800d5fc:	e031      	b.n	800d662 <UART_SetConfig+0xaba>
+    {
+      case UART_CLOCKSOURCE_D2PCLK1:
+        pclk = HAL_RCC_GetPCLK1Freq();
+ 800d5fe:	f7fa fcaf 	bl	8007f60 <HAL_RCC_GetPCLK1Freq>
+ 800d602:	63f8      	str	r0, [r7, #60]	; 0x3c
+        break;
+ 800d604:	e033      	b.n	800d66e <UART_SetConfig+0xac6>
+      case UART_CLOCKSOURCE_D2PCLK2:
+        pclk = HAL_RCC_GetPCLK2Freq();
+ 800d606:	f7fa fcc1 	bl	8007f8c <HAL_RCC_GetPCLK2Freq>
+ 800d60a:	63f8      	str	r0, [r7, #60]	; 0x3c
+        break;
+ 800d60c:	e02f      	b.n	800d66e <UART_SetConfig+0xac6>
+      case UART_CLOCKSOURCE_PLL2:
+        HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
+ 800d60e:	f107 0324 	add.w	r3, r7, #36	; 0x24
+ 800d612:	4618      	mov	r0, r3
+ 800d614:	f7fc fb9a 	bl	8009d4c <HAL_RCCEx_GetPLL2ClockFreq>
+        pclk = pll2_clocks.PLL2_Q_Frequency;
+ 800d618:	6abb      	ldr	r3, [r7, #40]	; 0x28
+ 800d61a:	63fb      	str	r3, [r7, #60]	; 0x3c
+        break;
+ 800d61c:	e027      	b.n	800d66e <UART_SetConfig+0xac6>
+      case UART_CLOCKSOURCE_PLL3:
+        HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
+ 800d61e:	f107 0318 	add.w	r3, r7, #24
+ 800d622:	4618      	mov	r0, r3
+ 800d624:	f7fc fce6 	bl	8009ff4 <HAL_RCCEx_GetPLL3ClockFreq>
+        pclk = pll3_clocks.PLL3_Q_Frequency;
+ 800d628:	69fb      	ldr	r3, [r7, #28]
+ 800d62a:	63fb      	str	r3, [r7, #60]	; 0x3c
+        break;
+ 800d62c:	e01f      	b.n	800d66e <UART_SetConfig+0xac6>
+      case UART_CLOCKSOURCE_HSI:
+        if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
+ 800d62e:	4b69      	ldr	r3, [pc, #420]	; (800d7d4 <UART_SetConfig+0xc2c>)
+ 800d630:	681b      	ldr	r3, [r3, #0]
+ 800d632:	f003 0320 	and.w	r3, r3, #32
+ 800d636:	2b00      	cmp	r3, #0
+ 800d638:	d009      	beq.n	800d64e <UART_SetConfig+0xaa6>
+        {
+          pclk = (uint32_t)(HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3U));
+ 800d63a:	4b66      	ldr	r3, [pc, #408]	; (800d7d4 <UART_SetConfig+0xc2c>)
+ 800d63c:	681b      	ldr	r3, [r3, #0]
+ 800d63e:	08db      	lsrs	r3, r3, #3
+ 800d640:	f003 0303 	and.w	r3, r3, #3
+ 800d644:	4a64      	ldr	r2, [pc, #400]	; (800d7d8 <UART_SetConfig+0xc30>)
+ 800d646:	fa22 f303 	lsr.w	r3, r2, r3
+ 800d64a:	63fb      	str	r3, [r7, #60]	; 0x3c
+        }
+        else
+        {
+          pclk = (uint32_t) HSI_VALUE;
+        }
+        break;
+ 800d64c:	e00f      	b.n	800d66e <UART_SetConfig+0xac6>
+          pclk = (uint32_t) HSI_VALUE;
+ 800d64e:	4b62      	ldr	r3, [pc, #392]	; (800d7d8 <UART_SetConfig+0xc30>)
+ 800d650:	63fb      	str	r3, [r7, #60]	; 0x3c
+        break;
+ 800d652:	e00c      	b.n	800d66e <UART_SetConfig+0xac6>
+      case UART_CLOCKSOURCE_CSI:
+        pclk = (uint32_t) CSI_VALUE;
+ 800d654:	4b61      	ldr	r3, [pc, #388]	; (800d7dc <UART_SetConfig+0xc34>)
+ 800d656:	63fb      	str	r3, [r7, #60]	; 0x3c
+        break;
+ 800d658:	e009      	b.n	800d66e <UART_SetConfig+0xac6>
+      case UART_CLOCKSOURCE_LSE:
+        pclk = (uint32_t) LSE_VALUE;
+ 800d65a:	f44f 4300 	mov.w	r3, #32768	; 0x8000
+ 800d65e:	63fb      	str	r3, [r7, #60]	; 0x3c
+        break;
+ 800d660:	e005      	b.n	800d66e <UART_SetConfig+0xac6>
+      default:
+        pclk = 0U;
+ 800d662:	2300      	movs	r3, #0
+ 800d664:	63fb      	str	r3, [r7, #60]	; 0x3c
+        ret = HAL_ERROR;
+ 800d666:	2301      	movs	r3, #1
+ 800d668:	f887 3042 	strb.w	r3, [r7, #66]	; 0x42
+        break;
+ 800d66c:	bf00      	nop
+    }
+
+    /* USARTDIV must be greater than or equal to 0d16 */
+    if (pclk != 0U)
+ 800d66e:	6bfb      	ldr	r3, [r7, #60]	; 0x3c
+ 800d670:	2b00      	cmp	r3, #0
+ 800d672:	f000 80ea 	beq.w	800d84a <UART_SetConfig+0xca2>
+    {
+      usartdiv = (uint32_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
+ 800d676:	697b      	ldr	r3, [r7, #20]
+ 800d678:	6a5b      	ldr	r3, [r3, #36]	; 0x24
+ 800d67a:	4a55      	ldr	r2, [pc, #340]	; (800d7d0 <UART_SetConfig+0xc28>)
+ 800d67c:	f832 3013 	ldrh.w	r3, [r2, r3, lsl #1]
+ 800d680:	461a      	mov	r2, r3
+ 800d682:	6bfb      	ldr	r3, [r7, #60]	; 0x3c
+ 800d684:	fbb3 f3f2 	udiv	r3, r3, r2
+ 800d688:	005a      	lsls	r2, r3, #1
+ 800d68a:	697b      	ldr	r3, [r7, #20]
+ 800d68c:	685b      	ldr	r3, [r3, #4]
+ 800d68e:	085b      	lsrs	r3, r3, #1
+ 800d690:	441a      	add	r2, r3
+ 800d692:	697b      	ldr	r3, [r7, #20]
+ 800d694:	685b      	ldr	r3, [r3, #4]
+ 800d696:	fbb2 f3f3 	udiv	r3, r2, r3
+ 800d69a:	63bb      	str	r3, [r7, #56]	; 0x38
+      if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
+ 800d69c:	6bbb      	ldr	r3, [r7, #56]	; 0x38
+ 800d69e:	2b0f      	cmp	r3, #15
+ 800d6a0:	d916      	bls.n	800d6d0 <UART_SetConfig+0xb28>
+ 800d6a2:	6bbb      	ldr	r3, [r7, #56]	; 0x38
+ 800d6a4:	f5b3 3f80 	cmp.w	r3, #65536	; 0x10000
+ 800d6a8:	d212      	bcs.n	800d6d0 <UART_SetConfig+0xb28>
+      {
+        brrtemp = (uint16_t)(usartdiv & 0xFFF0U);
+ 800d6aa:	6bbb      	ldr	r3, [r7, #56]	; 0x38
+ 800d6ac:	b29b      	uxth	r3, r3
+ 800d6ae:	f023 030f 	bic.w	r3, r3, #15
+ 800d6b2:	86fb      	strh	r3, [r7, #54]	; 0x36
+        brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
+ 800d6b4:	6bbb      	ldr	r3, [r7, #56]	; 0x38
+ 800d6b6:	085b      	lsrs	r3, r3, #1
+ 800d6b8:	b29b      	uxth	r3, r3
+ 800d6ba:	f003 0307 	and.w	r3, r3, #7
+ 800d6be:	b29a      	uxth	r2, r3
+ 800d6c0:	8efb      	ldrh	r3, [r7, #54]	; 0x36
+ 800d6c2:	4313      	orrs	r3, r2
+ 800d6c4:	86fb      	strh	r3, [r7, #54]	; 0x36
+        huart->Instance->BRR = brrtemp;
+ 800d6c6:	697b      	ldr	r3, [r7, #20]
+ 800d6c8:	681b      	ldr	r3, [r3, #0]
+ 800d6ca:	8efa      	ldrh	r2, [r7, #54]	; 0x36
+ 800d6cc:	60da      	str	r2, [r3, #12]
+ 800d6ce:	e0bc      	b.n	800d84a <UART_SetConfig+0xca2>
+      }
+      else
+      {
+        ret = HAL_ERROR;
+ 800d6d0:	2301      	movs	r3, #1
+ 800d6d2:	f887 3042 	strb.w	r3, [r7, #66]	; 0x42
+ 800d6d6:	e0b8      	b.n	800d84a <UART_SetConfig+0xca2>
+      }
+    }
+  }
+  else
+  {
+    switch (clocksource)
+ 800d6d8:	f897 3043 	ldrb.w	r3, [r7, #67]	; 0x43
+ 800d6dc:	2b20      	cmp	r3, #32
+ 800d6de:	dc4b      	bgt.n	800d778 <UART_SetConfig+0xbd0>
+ 800d6e0:	2b00      	cmp	r3, #0
+ 800d6e2:	f2c0 8087 	blt.w	800d7f4 <UART_SetConfig+0xc4c>
+ 800d6e6:	2b20      	cmp	r3, #32
+ 800d6e8:	f200 8084 	bhi.w	800d7f4 <UART_SetConfig+0xc4c>
+ 800d6ec:	a201      	add	r2, pc, #4	; (adr r2, 800d6f4 <UART_SetConfig+0xb4c>)
+ 800d6ee:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
+ 800d6f2:	bf00      	nop
+ 800d6f4:	0800d77f 	.word	0x0800d77f
+ 800d6f8:	0800d787 	.word	0x0800d787
+ 800d6fc:	0800d7f5 	.word	0x0800d7f5
+ 800d700:	0800d7f5 	.word	0x0800d7f5
+ 800d704:	0800d78f 	.word	0x0800d78f
+ 800d708:	0800d7f5 	.word	0x0800d7f5
+ 800d70c:	0800d7f5 	.word	0x0800d7f5
+ 800d710:	0800d7f5 	.word	0x0800d7f5
+ 800d714:	0800d79f 	.word	0x0800d79f
+ 800d718:	0800d7f5 	.word	0x0800d7f5
+ 800d71c:	0800d7f5 	.word	0x0800d7f5
+ 800d720:	0800d7f5 	.word	0x0800d7f5
+ 800d724:	0800d7f5 	.word	0x0800d7f5
+ 800d728:	0800d7f5 	.word	0x0800d7f5
+ 800d72c:	0800d7f5 	.word	0x0800d7f5
+ 800d730:	0800d7f5 	.word	0x0800d7f5
+ 800d734:	0800d7af 	.word	0x0800d7af
+ 800d738:	0800d7f5 	.word	0x0800d7f5
+ 800d73c:	0800d7f5 	.word	0x0800d7f5
+ 800d740:	0800d7f5 	.word	0x0800d7f5
+ 800d744:	0800d7f5 	.word	0x0800d7f5
+ 800d748:	0800d7f5 	.word	0x0800d7f5
+ 800d74c:	0800d7f5 	.word	0x0800d7f5
+ 800d750:	0800d7f5 	.word	0x0800d7f5
+ 800d754:	0800d7f5 	.word	0x0800d7f5
+ 800d758:	0800d7f5 	.word	0x0800d7f5
+ 800d75c:	0800d7f5 	.word	0x0800d7f5
+ 800d760:	0800d7f5 	.word	0x0800d7f5
+ 800d764:	0800d7f5 	.word	0x0800d7f5
+ 800d768:	0800d7f5 	.word	0x0800d7f5
+ 800d76c:	0800d7f5 	.word	0x0800d7f5
+ 800d770:	0800d7f5 	.word	0x0800d7f5
+ 800d774:	0800d7e7 	.word	0x0800d7e7
+ 800d778:	2b40      	cmp	r3, #64	; 0x40
+ 800d77a:	d037      	beq.n	800d7ec <UART_SetConfig+0xc44>
+ 800d77c:	e03a      	b.n	800d7f4 <UART_SetConfig+0xc4c>
+    {
+      case UART_CLOCKSOURCE_D2PCLK1:
+        pclk = HAL_RCC_GetPCLK1Freq();
+ 800d77e:	f7fa fbef 	bl	8007f60 <HAL_RCC_GetPCLK1Freq>
+ 800d782:	63f8      	str	r0, [r7, #60]	; 0x3c
+        break;
+ 800d784:	e03c      	b.n	800d800 <UART_SetConfig+0xc58>
+      case UART_CLOCKSOURCE_D2PCLK2:
+        pclk = HAL_RCC_GetPCLK2Freq();
+ 800d786:	f7fa fc01 	bl	8007f8c <HAL_RCC_GetPCLK2Freq>
+ 800d78a:	63f8      	str	r0, [r7, #60]	; 0x3c
+        break;
+ 800d78c:	e038      	b.n	800d800 <UART_SetConfig+0xc58>
+      case UART_CLOCKSOURCE_PLL2:
+        HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
+ 800d78e:	f107 0324 	add.w	r3, r7, #36	; 0x24
+ 800d792:	4618      	mov	r0, r3
+ 800d794:	f7fc fada 	bl	8009d4c <HAL_RCCEx_GetPLL2ClockFreq>
+        pclk = pll2_clocks.PLL2_Q_Frequency;
+ 800d798:	6abb      	ldr	r3, [r7, #40]	; 0x28
+ 800d79a:	63fb      	str	r3, [r7, #60]	; 0x3c
+        break;
+ 800d79c:	e030      	b.n	800d800 <UART_SetConfig+0xc58>
+      case UART_CLOCKSOURCE_PLL3:
+        HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
+ 800d79e:	f107 0318 	add.w	r3, r7, #24
+ 800d7a2:	4618      	mov	r0, r3
+ 800d7a4:	f7fc fc26 	bl	8009ff4 <HAL_RCCEx_GetPLL3ClockFreq>
+        pclk = pll3_clocks.PLL3_Q_Frequency;
+ 800d7a8:	69fb      	ldr	r3, [r7, #28]
+ 800d7aa:	63fb      	str	r3, [r7, #60]	; 0x3c
+        break;
+ 800d7ac:	e028      	b.n	800d800 <UART_SetConfig+0xc58>
+      case UART_CLOCKSOURCE_HSI:
+        if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
+ 800d7ae:	4b09      	ldr	r3, [pc, #36]	; (800d7d4 <UART_SetConfig+0xc2c>)
+ 800d7b0:	681b      	ldr	r3, [r3, #0]
+ 800d7b2:	f003 0320 	and.w	r3, r3, #32
+ 800d7b6:	2b00      	cmp	r3, #0
+ 800d7b8:	d012      	beq.n	800d7e0 <UART_SetConfig+0xc38>
+        {
+          pclk = (uint32_t)(HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3U));
+ 800d7ba:	4b06      	ldr	r3, [pc, #24]	; (800d7d4 <UART_SetConfig+0xc2c>)
+ 800d7bc:	681b      	ldr	r3, [r3, #0]
+ 800d7be:	08db      	lsrs	r3, r3, #3
+ 800d7c0:	f003 0303 	and.w	r3, r3, #3
+ 800d7c4:	4a04      	ldr	r2, [pc, #16]	; (800d7d8 <UART_SetConfig+0xc30>)
+ 800d7c6:	fa22 f303 	lsr.w	r3, r2, r3
+ 800d7ca:	63fb      	str	r3, [r7, #60]	; 0x3c
+        }
+        else
+        {
+          pclk = (uint32_t) HSI_VALUE;
+        }
+        break;
+ 800d7cc:	e018      	b.n	800d800 <UART_SetConfig+0xc58>
+ 800d7ce:	bf00      	nop
+ 800d7d0:	08026b58 	.word	0x08026b58
+ 800d7d4:	58024400 	.word	0x58024400
+ 800d7d8:	03d09000 	.word	0x03d09000
+ 800d7dc:	003d0900 	.word	0x003d0900
+          pclk = (uint32_t) HSI_VALUE;
+ 800d7e0:	4b24      	ldr	r3, [pc, #144]	; (800d874 <UART_SetConfig+0xccc>)
+ 800d7e2:	63fb      	str	r3, [r7, #60]	; 0x3c
+        break;
+ 800d7e4:	e00c      	b.n	800d800 <UART_SetConfig+0xc58>
+      case UART_CLOCKSOURCE_CSI:
+        pclk = (uint32_t) CSI_VALUE;
+ 800d7e6:	4b24      	ldr	r3, [pc, #144]	; (800d878 <UART_SetConfig+0xcd0>)
+ 800d7e8:	63fb      	str	r3, [r7, #60]	; 0x3c
+        break;
+ 800d7ea:	e009      	b.n	800d800 <UART_SetConfig+0xc58>
+      case UART_CLOCKSOURCE_LSE:
+        pclk = (uint32_t) LSE_VALUE;
+ 800d7ec:	f44f 4300 	mov.w	r3, #32768	; 0x8000
+ 800d7f0:	63fb      	str	r3, [r7, #60]	; 0x3c
+        break;
+ 800d7f2:	e005      	b.n	800d800 <UART_SetConfig+0xc58>
+      default:
+        pclk = 0U;
+ 800d7f4:	2300      	movs	r3, #0
+ 800d7f6:	63fb      	str	r3, [r7, #60]	; 0x3c
+        ret = HAL_ERROR;
+ 800d7f8:	2301      	movs	r3, #1
+ 800d7fa:	f887 3042 	strb.w	r3, [r7, #66]	; 0x42
+        break;
+ 800d7fe:	bf00      	nop
+    }
+
+    if (pclk != 0U)
+ 800d800:	6bfb      	ldr	r3, [r7, #60]	; 0x3c
+ 800d802:	2b00      	cmp	r3, #0
+ 800d804:	d021      	beq.n	800d84a <UART_SetConfig+0xca2>
+    {
+      /* USARTDIV must be greater than or equal to 0d16 */
+      usartdiv = (uint32_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
+ 800d806:	697b      	ldr	r3, [r7, #20]
+ 800d808:	6a5b      	ldr	r3, [r3, #36]	; 0x24
+ 800d80a:	4a1c      	ldr	r2, [pc, #112]	; (800d87c <UART_SetConfig+0xcd4>)
+ 800d80c:	f832 3013 	ldrh.w	r3, [r2, r3, lsl #1]
+ 800d810:	461a      	mov	r2, r3
+ 800d812:	6bfb      	ldr	r3, [r7, #60]	; 0x3c
+ 800d814:	fbb3 f2f2 	udiv	r2, r3, r2
+ 800d818:	697b      	ldr	r3, [r7, #20]
+ 800d81a:	685b      	ldr	r3, [r3, #4]
+ 800d81c:	085b      	lsrs	r3, r3, #1
+ 800d81e:	441a      	add	r2, r3
+ 800d820:	697b      	ldr	r3, [r7, #20]
+ 800d822:	685b      	ldr	r3, [r3, #4]
+ 800d824:	fbb2 f3f3 	udiv	r3, r2, r3
+ 800d828:	63bb      	str	r3, [r7, #56]	; 0x38
+      if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
+ 800d82a:	6bbb      	ldr	r3, [r7, #56]	; 0x38
+ 800d82c:	2b0f      	cmp	r3, #15
+ 800d82e:	d909      	bls.n	800d844 <UART_SetConfig+0xc9c>
+ 800d830:	6bbb      	ldr	r3, [r7, #56]	; 0x38
+ 800d832:	f5b3 3f80 	cmp.w	r3, #65536	; 0x10000
+ 800d836:	d205      	bcs.n	800d844 <UART_SetConfig+0xc9c>
+      {
+        huart->Instance->BRR = (uint16_t)usartdiv;
+ 800d838:	6bbb      	ldr	r3, [r7, #56]	; 0x38
+ 800d83a:	b29a      	uxth	r2, r3
+ 800d83c:	697b      	ldr	r3, [r7, #20]
+ 800d83e:	681b      	ldr	r3, [r3, #0]
+ 800d840:	60da      	str	r2, [r3, #12]
+ 800d842:	e002      	b.n	800d84a <UART_SetConfig+0xca2>
+      }
+      else
+      {
+        ret = HAL_ERROR;
+ 800d844:	2301      	movs	r3, #1
+ 800d846:	f887 3042 	strb.w	r3, [r7, #66]	; 0x42
+      }
+    }
+  }
+
+  /* Initialize the number of data to process during RX/TX ISR execution */
+  huart->NbTxDataToProcess = 1;
+ 800d84a:	697b      	ldr	r3, [r7, #20]
+ 800d84c:	2201      	movs	r2, #1
+ 800d84e:	f8a3 206a 	strh.w	r2, [r3, #106]	; 0x6a
+  huart->NbRxDataToProcess = 1;
+ 800d852:	697b      	ldr	r3, [r7, #20]
+ 800d854:	2201      	movs	r2, #1
+ 800d856:	f8a3 2068 	strh.w	r2, [r3, #104]	; 0x68
+
+  /* Clear ISR function pointers */
+  huart->RxISR = NULL;
+ 800d85a:	697b      	ldr	r3, [r7, #20]
+ 800d85c:	2200      	movs	r2, #0
+ 800d85e:	675a      	str	r2, [r3, #116]	; 0x74
+  huart->TxISR = NULL;
+ 800d860:	697b      	ldr	r3, [r7, #20]
+ 800d862:	2200      	movs	r2, #0
+ 800d864:	679a      	str	r2, [r3, #120]	; 0x78
+
+  return ret;
+ 800d866:	f897 3042 	ldrb.w	r3, [r7, #66]	; 0x42
+}
+ 800d86a:	4618      	mov	r0, r3
+ 800d86c:	3748      	adds	r7, #72	; 0x48
+ 800d86e:	46bd      	mov	sp, r7
+ 800d870:	e8bd 8fb0 	ldmia.w	sp!, {r4, r5, r7, r8, r9, sl, fp, pc}
+ 800d874:	03d09000 	.word	0x03d09000
+ 800d878:	003d0900 	.word	0x003d0900
+ 800d87c:	08026b58 	.word	0x08026b58
+
+0800d880 <UART_AdvFeatureConfig>:
+  * @brief Configure the UART peripheral advanced features.
+  * @param huart UART handle.
+  * @retval None
+  */
+void UART_AdvFeatureConfig(UART_HandleTypeDef *huart)
+{
+ 800d880:	b480      	push	{r7}
+ 800d882:	b083      	sub	sp, #12
+ 800d884:	af00      	add	r7, sp, #0
+ 800d886:	6078      	str	r0, [r7, #4]
+  /* Check whether the set of advanced features to configure is properly set */
+  assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit));
+
+  /* if required, configure TX pin active level inversion */
+  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT))
+ 800d888:	687b      	ldr	r3, [r7, #4]
+ 800d88a:	6a9b      	ldr	r3, [r3, #40]	; 0x28
+ 800d88c:	f003 0301 	and.w	r3, r3, #1
+ 800d890:	2b00      	cmp	r3, #0
+ 800d892:	d00a      	beq.n	800d8aa <UART_AdvFeatureConfig+0x2a>
+  {
+    assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert));
+    MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert);
+ 800d894:	687b      	ldr	r3, [r7, #4]
+ 800d896:	681b      	ldr	r3, [r3, #0]
+ 800d898:	685b      	ldr	r3, [r3, #4]
+ 800d89a:	f423 3100 	bic.w	r1, r3, #131072	; 0x20000
+ 800d89e:	687b      	ldr	r3, [r7, #4]
+ 800d8a0:	6ada      	ldr	r2, [r3, #44]	; 0x2c
+ 800d8a2:	687b      	ldr	r3, [r7, #4]
+ 800d8a4:	681b      	ldr	r3, [r3, #0]
+ 800d8a6:	430a      	orrs	r2, r1
+ 800d8a8:	605a      	str	r2, [r3, #4]
+  }
+
+  /* if required, configure RX pin active level inversion */
+  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT))
+ 800d8aa:	687b      	ldr	r3, [r7, #4]
+ 800d8ac:	6a9b      	ldr	r3, [r3, #40]	; 0x28
+ 800d8ae:	f003 0302 	and.w	r3, r3, #2
+ 800d8b2:	2b00      	cmp	r3, #0
+ 800d8b4:	d00a      	beq.n	800d8cc <UART_AdvFeatureConfig+0x4c>
+  {
+    assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert));
+    MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert);
+ 800d8b6:	687b      	ldr	r3, [r7, #4]
+ 800d8b8:	681b      	ldr	r3, [r3, #0]
+ 800d8ba:	685b      	ldr	r3, [r3, #4]
+ 800d8bc:	f423 3180 	bic.w	r1, r3, #65536	; 0x10000
+ 800d8c0:	687b      	ldr	r3, [r7, #4]
+ 800d8c2:	6b1a      	ldr	r2, [r3, #48]	; 0x30
+ 800d8c4:	687b      	ldr	r3, [r7, #4]
+ 800d8c6:	681b      	ldr	r3, [r3, #0]
+ 800d8c8:	430a      	orrs	r2, r1
+ 800d8ca:	605a      	str	r2, [r3, #4]
+  }
+
+  /* if required, configure data inversion */
+  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT))
+ 800d8cc:	687b      	ldr	r3, [r7, #4]
+ 800d8ce:	6a9b      	ldr	r3, [r3, #40]	; 0x28
+ 800d8d0:	f003 0304 	and.w	r3, r3, #4
+ 800d8d4:	2b00      	cmp	r3, #0
+ 800d8d6:	d00a      	beq.n	800d8ee <UART_AdvFeatureConfig+0x6e>
+  {
+    assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert));
+    MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert);
+ 800d8d8:	687b      	ldr	r3, [r7, #4]
+ 800d8da:	681b      	ldr	r3, [r3, #0]
+ 800d8dc:	685b      	ldr	r3, [r3, #4]
+ 800d8de:	f423 2180 	bic.w	r1, r3, #262144	; 0x40000
+ 800d8e2:	687b      	ldr	r3, [r7, #4]
+ 800d8e4:	6b5a      	ldr	r2, [r3, #52]	; 0x34
+ 800d8e6:	687b      	ldr	r3, [r7, #4]
+ 800d8e8:	681b      	ldr	r3, [r3, #0]
+ 800d8ea:	430a      	orrs	r2, r1
+ 800d8ec:	605a      	str	r2, [r3, #4]
+  }
+
+  /* if required, configure RX/TX pins swap */
+  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT))
+ 800d8ee:	687b      	ldr	r3, [r7, #4]
+ 800d8f0:	6a9b      	ldr	r3, [r3, #40]	; 0x28
+ 800d8f2:	f003 0308 	and.w	r3, r3, #8
+ 800d8f6:	2b00      	cmp	r3, #0
+ 800d8f8:	d00a      	beq.n	800d910 <UART_AdvFeatureConfig+0x90>
+  {
+    assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap));
+    MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap);
+ 800d8fa:	687b      	ldr	r3, [r7, #4]
+ 800d8fc:	681b      	ldr	r3, [r3, #0]
+ 800d8fe:	685b      	ldr	r3, [r3, #4]
+ 800d900:	f423 4100 	bic.w	r1, r3, #32768	; 0x8000
+ 800d904:	687b      	ldr	r3, [r7, #4]
+ 800d906:	6b9a      	ldr	r2, [r3, #56]	; 0x38
+ 800d908:	687b      	ldr	r3, [r7, #4]
+ 800d90a:	681b      	ldr	r3, [r3, #0]
+ 800d90c:	430a      	orrs	r2, r1
+ 800d90e:	605a      	str	r2, [r3, #4]
+  }
+
+  /* if required, configure RX overrun detection disabling */
+  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT))
+ 800d910:	687b      	ldr	r3, [r7, #4]
+ 800d912:	6a9b      	ldr	r3, [r3, #40]	; 0x28
+ 800d914:	f003 0310 	and.w	r3, r3, #16
+ 800d918:	2b00      	cmp	r3, #0
+ 800d91a:	d00a      	beq.n	800d932 <UART_AdvFeatureConfig+0xb2>
+  {
+    assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable));
+    MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable);
+ 800d91c:	687b      	ldr	r3, [r7, #4]
+ 800d91e:	681b      	ldr	r3, [r3, #0]
+ 800d920:	689b      	ldr	r3, [r3, #8]
+ 800d922:	f423 5180 	bic.w	r1, r3, #4096	; 0x1000
+ 800d926:	687b      	ldr	r3, [r7, #4]
+ 800d928:	6bda      	ldr	r2, [r3, #60]	; 0x3c
+ 800d92a:	687b      	ldr	r3, [r7, #4]
+ 800d92c:	681b      	ldr	r3, [r3, #0]
+ 800d92e:	430a      	orrs	r2, r1
+ 800d930:	609a      	str	r2, [r3, #8]
+  }
+
+  /* if required, configure DMA disabling on reception error */
+  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT))
+ 800d932:	687b      	ldr	r3, [r7, #4]
+ 800d934:	6a9b      	ldr	r3, [r3, #40]	; 0x28
+ 800d936:	f003 0320 	and.w	r3, r3, #32
+ 800d93a:	2b00      	cmp	r3, #0
+ 800d93c:	d00a      	beq.n	800d954 <UART_AdvFeatureConfig+0xd4>
+  {
+    assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError));
+    MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError);
+ 800d93e:	687b      	ldr	r3, [r7, #4]
+ 800d940:	681b      	ldr	r3, [r3, #0]
+ 800d942:	689b      	ldr	r3, [r3, #8]
+ 800d944:	f423 5100 	bic.w	r1, r3, #8192	; 0x2000
+ 800d948:	687b      	ldr	r3, [r7, #4]
+ 800d94a:	6c1a      	ldr	r2, [r3, #64]	; 0x40
+ 800d94c:	687b      	ldr	r3, [r7, #4]
+ 800d94e:	681b      	ldr	r3, [r3, #0]
+ 800d950:	430a      	orrs	r2, r1
+ 800d952:	609a      	str	r2, [r3, #8]
+  }
+
+  /* if required, configure auto Baud rate detection scheme */
+  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT))
+ 800d954:	687b      	ldr	r3, [r7, #4]
+ 800d956:	6a9b      	ldr	r3, [r3, #40]	; 0x28
+ 800d958:	f003 0340 	and.w	r3, r3, #64	; 0x40
+ 800d95c:	2b00      	cmp	r3, #0
+ 800d95e:	d01a      	beq.n	800d996 <UART_AdvFeatureConfig+0x116>
+  {
+    assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance));
+    assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable));
+    MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable);
+ 800d960:	687b      	ldr	r3, [r7, #4]
+ 800d962:	681b      	ldr	r3, [r3, #0]
+ 800d964:	685b      	ldr	r3, [r3, #4]
+ 800d966:	f423 1180 	bic.w	r1, r3, #1048576	; 0x100000
+ 800d96a:	687b      	ldr	r3, [r7, #4]
+ 800d96c:	6c5a      	ldr	r2, [r3, #68]	; 0x44
+ 800d96e:	687b      	ldr	r3, [r7, #4]
+ 800d970:	681b      	ldr	r3, [r3, #0]
+ 800d972:	430a      	orrs	r2, r1
+ 800d974:	605a      	str	r2, [r3, #4]
+    /* set auto Baudrate detection parameters if detection is enabled */
+    if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)
+ 800d976:	687b      	ldr	r3, [r7, #4]
+ 800d978:	6c5b      	ldr	r3, [r3, #68]	; 0x44
+ 800d97a:	f5b3 1f80 	cmp.w	r3, #1048576	; 0x100000
+ 800d97e:	d10a      	bne.n	800d996 <UART_AdvFeatureConfig+0x116>
+    {
+      assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode));
+      MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode);
+ 800d980:	687b      	ldr	r3, [r7, #4]
+ 800d982:	681b      	ldr	r3, [r3, #0]
+ 800d984:	685b      	ldr	r3, [r3, #4]
+ 800d986:	f423 01c0 	bic.w	r1, r3, #6291456	; 0x600000
+ 800d98a:	687b      	ldr	r3, [r7, #4]
+ 800d98c:	6c9a      	ldr	r2, [r3, #72]	; 0x48
+ 800d98e:	687b      	ldr	r3, [r7, #4]
+ 800d990:	681b      	ldr	r3, [r3, #0]
+ 800d992:	430a      	orrs	r2, r1
+ 800d994:	605a      	str	r2, [r3, #4]
+    }
+  }
+
+  /* if required, configure MSB first on communication line */
+  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT))
+ 800d996:	687b      	ldr	r3, [r7, #4]
+ 800d998:	6a9b      	ldr	r3, [r3, #40]	; 0x28
+ 800d99a:	f003 0380 	and.w	r3, r3, #128	; 0x80
+ 800d99e:	2b00      	cmp	r3, #0
+ 800d9a0:	d00a      	beq.n	800d9b8 <UART_AdvFeatureConfig+0x138>
+  {
+    assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst));
+    MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst);
+ 800d9a2:	687b      	ldr	r3, [r7, #4]
+ 800d9a4:	681b      	ldr	r3, [r3, #0]
+ 800d9a6:	685b      	ldr	r3, [r3, #4]
+ 800d9a8:	f423 2100 	bic.w	r1, r3, #524288	; 0x80000
+ 800d9ac:	687b      	ldr	r3, [r7, #4]
+ 800d9ae:	6cda      	ldr	r2, [r3, #76]	; 0x4c
+ 800d9b0:	687b      	ldr	r3, [r7, #4]
+ 800d9b2:	681b      	ldr	r3, [r3, #0]
+ 800d9b4:	430a      	orrs	r2, r1
+ 800d9b6:	605a      	str	r2, [r3, #4]
+  }
+}
+ 800d9b8:	bf00      	nop
+ 800d9ba:	370c      	adds	r7, #12
+ 800d9bc:	46bd      	mov	sp, r7
+ 800d9be:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 800d9c2:	4770      	bx	lr
+
+0800d9c4 <UART_CheckIdleState>:
+  * @brief Check the UART Idle State.
+  * @param huart UART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart)
+{
+ 800d9c4:	b580      	push	{r7, lr}
+ 800d9c6:	b098      	sub	sp, #96	; 0x60
+ 800d9c8:	af02      	add	r7, sp, #8
+ 800d9ca:	6078      	str	r0, [r7, #4]
+  uint32_t tickstart;
+
+  /* Initialize the UART ErrorCode */
+  huart->ErrorCode = HAL_UART_ERROR_NONE;
+ 800d9cc:	687b      	ldr	r3, [r7, #4]
+ 800d9ce:	2200      	movs	r2, #0
+ 800d9d0:	f8c3 2090 	str.w	r2, [r3, #144]	; 0x90
+
+  /* Init tickstart for timeout management */
+  tickstart = HAL_GetTick();
+ 800d9d4:	f7f4 fcc6 	bl	8002364 <HAL_GetTick>
+ 800d9d8:	6578      	str	r0, [r7, #84]	; 0x54
+
+  /* Check if the Transmitter is enabled */
+  if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
+ 800d9da:	687b      	ldr	r3, [r7, #4]
+ 800d9dc:	681b      	ldr	r3, [r3, #0]
+ 800d9de:	681b      	ldr	r3, [r3, #0]
+ 800d9e0:	f003 0308 	and.w	r3, r3, #8
+ 800d9e4:	2b08      	cmp	r3, #8
+ 800d9e6:	d12f      	bne.n	800da48 <UART_CheckIdleState+0x84>
+  {
+    /* Wait until TEACK flag is set */
+    if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
+ 800d9e8:	f06f 437e 	mvn.w	r3, #4261412864	; 0xfe000000
+ 800d9ec:	9300      	str	r3, [sp, #0]
+ 800d9ee:	6d7b      	ldr	r3, [r7, #84]	; 0x54
+ 800d9f0:	2200      	movs	r2, #0
+ 800d9f2:	f44f 1100 	mov.w	r1, #2097152	; 0x200000
+ 800d9f6:	6878      	ldr	r0, [r7, #4]
+ 800d9f8:	f000 f88e 	bl	800db18 <UART_WaitOnFlagUntilTimeout>
+ 800d9fc:	4603      	mov	r3, r0
+ 800d9fe:	2b00      	cmp	r3, #0
+ 800da00:	d022      	beq.n	800da48 <UART_CheckIdleState+0x84>
+    {
+      /* Disable TXE interrupt for the interrupt process */
+      ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE));
+ 800da02:	687b      	ldr	r3, [r7, #4]
+ 800da04:	681b      	ldr	r3, [r3, #0]
+ 800da06:	63bb      	str	r3, [r7, #56]	; 0x38
+ */
+__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+ 800da08:	6bbb      	ldr	r3, [r7, #56]	; 0x38
+ 800da0a:	e853 3f00 	ldrex	r3, [r3]
+ 800da0e:	637b      	str	r3, [r7, #52]	; 0x34
+   return(result);
+ 800da10:	6b7b      	ldr	r3, [r7, #52]	; 0x34
+ 800da12:	f023 0380 	bic.w	r3, r3, #128	; 0x80
+ 800da16:	653b      	str	r3, [r7, #80]	; 0x50
+ 800da18:	687b      	ldr	r3, [r7, #4]
+ 800da1a:	681b      	ldr	r3, [r3, #0]
+ 800da1c:	461a      	mov	r2, r3
+ 800da1e:	6d3b      	ldr	r3, [r7, #80]	; 0x50
+ 800da20:	647b      	str	r3, [r7, #68]	; 0x44
+ 800da22:	643a      	str	r2, [r7, #64]	; 0x40
+ */
+__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+ 800da24:	6c39      	ldr	r1, [r7, #64]	; 0x40
+ 800da26:	6c7a      	ldr	r2, [r7, #68]	; 0x44
+ 800da28:	e841 2300 	strex	r3, r2, [r1]
+ 800da2c:	63fb      	str	r3, [r7, #60]	; 0x3c
+   return(result);
+ 800da2e:	6bfb      	ldr	r3, [r7, #60]	; 0x3c
+ 800da30:	2b00      	cmp	r3, #0
+ 800da32:	d1e6      	bne.n	800da02 <UART_CheckIdleState+0x3e>
+
+      huart->gState = HAL_UART_STATE_READY;
+ 800da34:	687b      	ldr	r3, [r7, #4]
+ 800da36:	2220      	movs	r2, #32
+ 800da38:	f8c3 2088 	str.w	r2, [r3, #136]	; 0x88
+
+      __HAL_UNLOCK(huart);
+ 800da3c:	687b      	ldr	r3, [r7, #4]
+ 800da3e:	2200      	movs	r2, #0
+ 800da40:	f883 2084 	strb.w	r2, [r3, #132]	; 0x84
+
+      /* Timeout occurred */
+      return HAL_TIMEOUT;
+ 800da44:	2303      	movs	r3, #3
+ 800da46:	e063      	b.n	800db10 <UART_CheckIdleState+0x14c>
+    }
+  }
+
+  /* Check if the Receiver is enabled */
+  if ((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
+ 800da48:	687b      	ldr	r3, [r7, #4]
+ 800da4a:	681b      	ldr	r3, [r3, #0]
+ 800da4c:	681b      	ldr	r3, [r3, #0]
+ 800da4e:	f003 0304 	and.w	r3, r3, #4
+ 800da52:	2b04      	cmp	r3, #4
+ 800da54:	d149      	bne.n	800daea <UART_CheckIdleState+0x126>
+  {
+    /* Wait until REACK flag is set */
+    if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
+ 800da56:	f06f 437e 	mvn.w	r3, #4261412864	; 0xfe000000
+ 800da5a:	9300      	str	r3, [sp, #0]
+ 800da5c:	6d7b      	ldr	r3, [r7, #84]	; 0x54
+ 800da5e:	2200      	movs	r2, #0
+ 800da60:	f44f 0180 	mov.w	r1, #4194304	; 0x400000
+ 800da64:	6878      	ldr	r0, [r7, #4]
+ 800da66:	f000 f857 	bl	800db18 <UART_WaitOnFlagUntilTimeout>
+ 800da6a:	4603      	mov	r3, r0
+ 800da6c:	2b00      	cmp	r3, #0
+ 800da6e:	d03c      	beq.n	800daea <UART_CheckIdleState+0x126>
+    {
+      /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error)
+      interrupts for the interrupt process */
+      ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
+ 800da70:	687b      	ldr	r3, [r7, #4]
+ 800da72:	681b      	ldr	r3, [r3, #0]
+ 800da74:	627b      	str	r3, [r7, #36]	; 0x24
+   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+ 800da76:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 800da78:	e853 3f00 	ldrex	r3, [r3]
+ 800da7c:	623b      	str	r3, [r7, #32]
+   return(result);
+ 800da7e:	6a3b      	ldr	r3, [r7, #32]
+ 800da80:	f423 7390 	bic.w	r3, r3, #288	; 0x120
+ 800da84:	64fb      	str	r3, [r7, #76]	; 0x4c
+ 800da86:	687b      	ldr	r3, [r7, #4]
+ 800da88:	681b      	ldr	r3, [r3, #0]
+ 800da8a:	461a      	mov	r2, r3
+ 800da8c:	6cfb      	ldr	r3, [r7, #76]	; 0x4c
+ 800da8e:	633b      	str	r3, [r7, #48]	; 0x30
+ 800da90:	62fa      	str	r2, [r7, #44]	; 0x2c
+   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+ 800da92:	6af9      	ldr	r1, [r7, #44]	; 0x2c
+ 800da94:	6b3a      	ldr	r2, [r7, #48]	; 0x30
+ 800da96:	e841 2300 	strex	r3, r2, [r1]
+ 800da9a:	62bb      	str	r3, [r7, #40]	; 0x28
+   return(result);
+ 800da9c:	6abb      	ldr	r3, [r7, #40]	; 0x28
+ 800da9e:	2b00      	cmp	r3, #0
+ 800daa0:	d1e6      	bne.n	800da70 <UART_CheckIdleState+0xac>
+      ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+ 800daa2:	687b      	ldr	r3, [r7, #4]
+ 800daa4:	681b      	ldr	r3, [r3, #0]
+ 800daa6:	3308      	adds	r3, #8
+ 800daa8:	613b      	str	r3, [r7, #16]
+   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+ 800daaa:	693b      	ldr	r3, [r7, #16]
+ 800daac:	e853 3f00 	ldrex	r3, [r3]
+ 800dab0:	60fb      	str	r3, [r7, #12]
+   return(result);
+ 800dab2:	68fb      	ldr	r3, [r7, #12]
+ 800dab4:	f023 0301 	bic.w	r3, r3, #1
+ 800dab8:	64bb      	str	r3, [r7, #72]	; 0x48
+ 800daba:	687b      	ldr	r3, [r7, #4]
+ 800dabc:	681b      	ldr	r3, [r3, #0]
+ 800dabe:	3308      	adds	r3, #8
+ 800dac0:	6cba      	ldr	r2, [r7, #72]	; 0x48
+ 800dac2:	61fa      	str	r2, [r7, #28]
+ 800dac4:	61bb      	str	r3, [r7, #24]
+   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+ 800dac6:	69b9      	ldr	r1, [r7, #24]
+ 800dac8:	69fa      	ldr	r2, [r7, #28]
+ 800daca:	e841 2300 	strex	r3, r2, [r1]
+ 800dace:	617b      	str	r3, [r7, #20]
+   return(result);
+ 800dad0:	697b      	ldr	r3, [r7, #20]
+ 800dad2:	2b00      	cmp	r3, #0
+ 800dad4:	d1e5      	bne.n	800daa2 <UART_CheckIdleState+0xde>
+
+      huart->RxState = HAL_UART_STATE_READY;
+ 800dad6:	687b      	ldr	r3, [r7, #4]
+ 800dad8:	2220      	movs	r2, #32
+ 800dada:	f8c3 208c 	str.w	r2, [r3, #140]	; 0x8c
+
+      __HAL_UNLOCK(huart);
+ 800dade:	687b      	ldr	r3, [r7, #4]
+ 800dae0:	2200      	movs	r2, #0
+ 800dae2:	f883 2084 	strb.w	r2, [r3, #132]	; 0x84
+
+      /* Timeout occurred */
+      return HAL_TIMEOUT;
+ 800dae6:	2303      	movs	r3, #3
+ 800dae8:	e012      	b.n	800db10 <UART_CheckIdleState+0x14c>
+    }
+  }
+
+  /* Initialize the UART State */
+  huart->gState = HAL_UART_STATE_READY;
+ 800daea:	687b      	ldr	r3, [r7, #4]
+ 800daec:	2220      	movs	r2, #32
+ 800daee:	f8c3 2088 	str.w	r2, [r3, #136]	; 0x88
+  huart->RxState = HAL_UART_STATE_READY;
+ 800daf2:	687b      	ldr	r3, [r7, #4]
+ 800daf4:	2220      	movs	r2, #32
+ 800daf6:	f8c3 208c 	str.w	r2, [r3, #140]	; 0x8c
+  huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+ 800dafa:	687b      	ldr	r3, [r7, #4]
+ 800dafc:	2200      	movs	r2, #0
+ 800dafe:	66da      	str	r2, [r3, #108]	; 0x6c
+  huart->RxEventType = HAL_UART_RXEVENT_TC;
+ 800db00:	687b      	ldr	r3, [r7, #4]
+ 800db02:	2200      	movs	r2, #0
+ 800db04:	671a      	str	r2, [r3, #112]	; 0x70
+
+  __HAL_UNLOCK(huart);
+ 800db06:	687b      	ldr	r3, [r7, #4]
+ 800db08:	2200      	movs	r2, #0
+ 800db0a:	f883 2084 	strb.w	r2, [r3, #132]	; 0x84
+
+  return HAL_OK;
+ 800db0e:	2300      	movs	r3, #0
+}
+ 800db10:	4618      	mov	r0, r3
+ 800db12:	3758      	adds	r7, #88	; 0x58
+ 800db14:	46bd      	mov	sp, r7
+ 800db16:	bd80      	pop	{r7, pc}
+
+0800db18 <UART_WaitOnFlagUntilTimeout>:
+  * @param Timeout   Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status,
+                                              uint32_t Tickstart, uint32_t Timeout)
+{
+ 800db18:	b580      	push	{r7, lr}
+ 800db1a:	b084      	sub	sp, #16
+ 800db1c:	af00      	add	r7, sp, #0
+ 800db1e:	60f8      	str	r0, [r7, #12]
+ 800db20:	60b9      	str	r1, [r7, #8]
+ 800db22:	603b      	str	r3, [r7, #0]
+ 800db24:	4613      	mov	r3, r2
+ 800db26:	71fb      	strb	r3, [r7, #7]
+  /* Wait until flag is set */
+  while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
+ 800db28:	e049      	b.n	800dbbe <UART_WaitOnFlagUntilTimeout+0xa6>
+  {
+    /* Check for the Timeout */
+    if (Timeout != HAL_MAX_DELAY)
+ 800db2a:	69bb      	ldr	r3, [r7, #24]
+ 800db2c:	f1b3 3fff 	cmp.w	r3, #4294967295
+ 800db30:	d045      	beq.n	800dbbe <UART_WaitOnFlagUntilTimeout+0xa6>
+    {
+      if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
+ 800db32:	f7f4 fc17 	bl	8002364 <HAL_GetTick>
+ 800db36:	4602      	mov	r2, r0
+ 800db38:	683b      	ldr	r3, [r7, #0]
+ 800db3a:	1ad3      	subs	r3, r2, r3
+ 800db3c:	69ba      	ldr	r2, [r7, #24]
+ 800db3e:	429a      	cmp	r2, r3
+ 800db40:	d302      	bcc.n	800db48 <UART_WaitOnFlagUntilTimeout+0x30>
+ 800db42:	69bb      	ldr	r3, [r7, #24]
+ 800db44:	2b00      	cmp	r3, #0
+ 800db46:	d101      	bne.n	800db4c <UART_WaitOnFlagUntilTimeout+0x34>
+      {
+
+        return HAL_TIMEOUT;
+ 800db48:	2303      	movs	r3, #3
+ 800db4a:	e048      	b.n	800dbde <UART_WaitOnFlagUntilTimeout+0xc6>
+      }
+
+      if (READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U)
+ 800db4c:	68fb      	ldr	r3, [r7, #12]
+ 800db4e:	681b      	ldr	r3, [r3, #0]
+ 800db50:	681b      	ldr	r3, [r3, #0]
+ 800db52:	f003 0304 	and.w	r3, r3, #4
+ 800db56:	2b00      	cmp	r3, #0
+ 800db58:	d031      	beq.n	800dbbe <UART_WaitOnFlagUntilTimeout+0xa6>
+      {
+        if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET)
+ 800db5a:	68fb      	ldr	r3, [r7, #12]
+ 800db5c:	681b      	ldr	r3, [r3, #0]
+ 800db5e:	69db      	ldr	r3, [r3, #28]
+ 800db60:	f003 0308 	and.w	r3, r3, #8
+ 800db64:	2b08      	cmp	r3, #8
+ 800db66:	d110      	bne.n	800db8a <UART_WaitOnFlagUntilTimeout+0x72>
+        {
+           /* Clear Overrun Error flag*/
+           __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
+ 800db68:	68fb      	ldr	r3, [r7, #12]
+ 800db6a:	681b      	ldr	r3, [r3, #0]
+ 800db6c:	2208      	movs	r2, #8
+ 800db6e:	621a      	str	r2, [r3, #32]
+
+           /* Blocking error : transfer is aborted
+           Set the UART state ready to be able to start again the process,
+           Disable Rx Interrupts if ongoing */
+           UART_EndRxTransfer(huart);
+ 800db70:	68f8      	ldr	r0, [r7, #12]
+ 800db72:	f000 f839 	bl	800dbe8 <UART_EndRxTransfer>
+
+           huart->ErrorCode = HAL_UART_ERROR_ORE;
+ 800db76:	68fb      	ldr	r3, [r7, #12]
+ 800db78:	2208      	movs	r2, #8
+ 800db7a:	f8c3 2090 	str.w	r2, [r3, #144]	; 0x90
+
+           /* Process Unlocked */
+           __HAL_UNLOCK(huart);
+ 800db7e:	68fb      	ldr	r3, [r7, #12]
+ 800db80:	2200      	movs	r2, #0
+ 800db82:	f883 2084 	strb.w	r2, [r3, #132]	; 0x84
+
+           return HAL_ERROR;
+ 800db86:	2301      	movs	r3, #1
+ 800db88:	e029      	b.n	800dbde <UART_WaitOnFlagUntilTimeout+0xc6>
+        }
+        if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET)
+ 800db8a:	68fb      	ldr	r3, [r7, #12]
+ 800db8c:	681b      	ldr	r3, [r3, #0]
+ 800db8e:	69db      	ldr	r3, [r3, #28]
+ 800db90:	f403 6300 	and.w	r3, r3, #2048	; 0x800
+ 800db94:	f5b3 6f00 	cmp.w	r3, #2048	; 0x800
+ 800db98:	d111      	bne.n	800dbbe <UART_WaitOnFlagUntilTimeout+0xa6>
+        {
+          /* Clear Receiver Timeout flag*/
+          __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF);
+ 800db9a:	68fb      	ldr	r3, [r7, #12]
+ 800db9c:	681b      	ldr	r3, [r3, #0]
+ 800db9e:	f44f 6200 	mov.w	r2, #2048	; 0x800
+ 800dba2:	621a      	str	r2, [r3, #32]
+
+          /* Blocking error : transfer is aborted
+          Set the UART state ready to be able to start again the process,
+          Disable Rx Interrupts if ongoing */
+          UART_EndRxTransfer(huart);
+ 800dba4:	68f8      	ldr	r0, [r7, #12]
+ 800dba6:	f000 f81f 	bl	800dbe8 <UART_EndRxTransfer>
+
+          huart->ErrorCode = HAL_UART_ERROR_RTO;
+ 800dbaa:	68fb      	ldr	r3, [r7, #12]
+ 800dbac:	2220      	movs	r2, #32
+ 800dbae:	f8c3 2090 	str.w	r2, [r3, #144]	; 0x90
+
+          /* Process Unlocked */
+          __HAL_UNLOCK(huart);
+ 800dbb2:	68fb      	ldr	r3, [r7, #12]
+ 800dbb4:	2200      	movs	r2, #0
+ 800dbb6:	f883 2084 	strb.w	r2, [r3, #132]	; 0x84
+
+          return HAL_TIMEOUT;
+ 800dbba:	2303      	movs	r3, #3
+ 800dbbc:	e00f      	b.n	800dbde <UART_WaitOnFlagUntilTimeout+0xc6>
+  while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
+ 800dbbe:	68fb      	ldr	r3, [r7, #12]
+ 800dbc0:	681b      	ldr	r3, [r3, #0]
+ 800dbc2:	69da      	ldr	r2, [r3, #28]
+ 800dbc4:	68bb      	ldr	r3, [r7, #8]
+ 800dbc6:	4013      	ands	r3, r2
+ 800dbc8:	68ba      	ldr	r2, [r7, #8]
+ 800dbca:	429a      	cmp	r2, r3
+ 800dbcc:	bf0c      	ite	eq
+ 800dbce:	2301      	moveq	r3, #1
+ 800dbd0:	2300      	movne	r3, #0
+ 800dbd2:	b2db      	uxtb	r3, r3
+ 800dbd4:	461a      	mov	r2, r3
+ 800dbd6:	79fb      	ldrb	r3, [r7, #7]
+ 800dbd8:	429a      	cmp	r2, r3
+ 800dbda:	d0a6      	beq.n	800db2a <UART_WaitOnFlagUntilTimeout+0x12>
+        }
+      }
+    }
+  }
+  return HAL_OK;
+ 800dbdc:	2300      	movs	r3, #0
+}
+ 800dbde:	4618      	mov	r0, r3
+ 800dbe0:	3710      	adds	r7, #16
+ 800dbe2:	46bd      	mov	sp, r7
+ 800dbe4:	bd80      	pop	{r7, pc}
+	...
+
+0800dbe8 <UART_EndRxTransfer>:
+  * @brief  End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
+  * @param  huart UART handle.
+  * @retval None
+  */
+static void UART_EndRxTransfer(UART_HandleTypeDef *huart)
+{
+ 800dbe8:	b480      	push	{r7}
+ 800dbea:	b095      	sub	sp, #84	; 0x54
+ 800dbec:	af00      	add	r7, sp, #0
+ 800dbee:	6078      	str	r0, [r7, #4]
+  /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+  ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
+ 800dbf0:	687b      	ldr	r3, [r7, #4]
+ 800dbf2:	681b      	ldr	r3, [r3, #0]
+ 800dbf4:	637b      	str	r3, [r7, #52]	; 0x34
+   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+ 800dbf6:	6b7b      	ldr	r3, [r7, #52]	; 0x34
+ 800dbf8:	e853 3f00 	ldrex	r3, [r3]
+ 800dbfc:	633b      	str	r3, [r7, #48]	; 0x30
+   return(result);
+ 800dbfe:	6b3b      	ldr	r3, [r7, #48]	; 0x30
+ 800dc00:	f423 7390 	bic.w	r3, r3, #288	; 0x120
+ 800dc04:	64fb      	str	r3, [r7, #76]	; 0x4c
+ 800dc06:	687b      	ldr	r3, [r7, #4]
+ 800dc08:	681b      	ldr	r3, [r3, #0]
+ 800dc0a:	461a      	mov	r2, r3
+ 800dc0c:	6cfb      	ldr	r3, [r7, #76]	; 0x4c
+ 800dc0e:	643b      	str	r3, [r7, #64]	; 0x40
+ 800dc10:	63fa      	str	r2, [r7, #60]	; 0x3c
+   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+ 800dc12:	6bf9      	ldr	r1, [r7, #60]	; 0x3c
+ 800dc14:	6c3a      	ldr	r2, [r7, #64]	; 0x40
+ 800dc16:	e841 2300 	strex	r3, r2, [r1]
+ 800dc1a:	63bb      	str	r3, [r7, #56]	; 0x38
+   return(result);
+ 800dc1c:	6bbb      	ldr	r3, [r7, #56]	; 0x38
+ 800dc1e:	2b00      	cmp	r3, #0
+ 800dc20:	d1e6      	bne.n	800dbf0 <UART_EndRxTransfer+0x8>
+  ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
+ 800dc22:	687b      	ldr	r3, [r7, #4]
+ 800dc24:	681b      	ldr	r3, [r3, #0]
+ 800dc26:	3308      	adds	r3, #8
+ 800dc28:	623b      	str	r3, [r7, #32]
+   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+ 800dc2a:	6a3b      	ldr	r3, [r7, #32]
+ 800dc2c:	e853 3f00 	ldrex	r3, [r3]
+ 800dc30:	61fb      	str	r3, [r7, #28]
+   return(result);
+ 800dc32:	69fa      	ldr	r2, [r7, #28]
+ 800dc34:	4b1e      	ldr	r3, [pc, #120]	; (800dcb0 <UART_EndRxTransfer+0xc8>)
+ 800dc36:	4013      	ands	r3, r2
+ 800dc38:	64bb      	str	r3, [r7, #72]	; 0x48
+ 800dc3a:	687b      	ldr	r3, [r7, #4]
+ 800dc3c:	681b      	ldr	r3, [r3, #0]
+ 800dc3e:	3308      	adds	r3, #8
+ 800dc40:	6cba      	ldr	r2, [r7, #72]	; 0x48
+ 800dc42:	62fa      	str	r2, [r7, #44]	; 0x2c
+ 800dc44:	62bb      	str	r3, [r7, #40]	; 0x28
+   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+ 800dc46:	6ab9      	ldr	r1, [r7, #40]	; 0x28
+ 800dc48:	6afa      	ldr	r2, [r7, #44]	; 0x2c
+ 800dc4a:	e841 2300 	strex	r3, r2, [r1]
+ 800dc4e:	627b      	str	r3, [r7, #36]	; 0x24
+   return(result);
+ 800dc50:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 800dc52:	2b00      	cmp	r3, #0
+ 800dc54:	d1e5      	bne.n	800dc22 <UART_EndRxTransfer+0x3a>
+
+  /* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */
+  if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+ 800dc56:	687b      	ldr	r3, [r7, #4]
+ 800dc58:	6edb      	ldr	r3, [r3, #108]	; 0x6c
+ 800dc5a:	2b01      	cmp	r3, #1
+ 800dc5c:	d118      	bne.n	800dc90 <UART_EndRxTransfer+0xa8>
+  {
+    ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+ 800dc5e:	687b      	ldr	r3, [r7, #4]
+ 800dc60:	681b      	ldr	r3, [r3, #0]
+ 800dc62:	60fb      	str	r3, [r7, #12]
+   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+ 800dc64:	68fb      	ldr	r3, [r7, #12]
+ 800dc66:	e853 3f00 	ldrex	r3, [r3]
+ 800dc6a:	60bb      	str	r3, [r7, #8]
+   return(result);
+ 800dc6c:	68bb      	ldr	r3, [r7, #8]
+ 800dc6e:	f023 0310 	bic.w	r3, r3, #16
+ 800dc72:	647b      	str	r3, [r7, #68]	; 0x44
+ 800dc74:	687b      	ldr	r3, [r7, #4]
+ 800dc76:	681b      	ldr	r3, [r3, #0]
+ 800dc78:	461a      	mov	r2, r3
+ 800dc7a:	6c7b      	ldr	r3, [r7, #68]	; 0x44
+ 800dc7c:	61bb      	str	r3, [r7, #24]
+ 800dc7e:	617a      	str	r2, [r7, #20]
+   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+ 800dc80:	6979      	ldr	r1, [r7, #20]
+ 800dc82:	69ba      	ldr	r2, [r7, #24]
+ 800dc84:	e841 2300 	strex	r3, r2, [r1]
+ 800dc88:	613b      	str	r3, [r7, #16]
+   return(result);
+ 800dc8a:	693b      	ldr	r3, [r7, #16]
+ 800dc8c:	2b00      	cmp	r3, #0
+ 800dc8e:	d1e6      	bne.n	800dc5e <UART_EndRxTransfer+0x76>
+  }
+
+  /* At end of Rx process, restore huart->RxState to Ready */
+  huart->RxState = HAL_UART_STATE_READY;
+ 800dc90:	687b      	ldr	r3, [r7, #4]
+ 800dc92:	2220      	movs	r2, #32
+ 800dc94:	f8c3 208c 	str.w	r2, [r3, #140]	; 0x8c
+  huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+ 800dc98:	687b      	ldr	r3, [r7, #4]
+ 800dc9a:	2200      	movs	r2, #0
+ 800dc9c:	66da      	str	r2, [r3, #108]	; 0x6c
+
+  /* Reset RxIsr function pointer */
+  huart->RxISR = NULL;
+ 800dc9e:	687b      	ldr	r3, [r7, #4]
+ 800dca0:	2200      	movs	r2, #0
+ 800dca2:	675a      	str	r2, [r3, #116]	; 0x74
+}
+ 800dca4:	bf00      	nop
+ 800dca6:	3754      	adds	r7, #84	; 0x54
+ 800dca8:	46bd      	mov	sp, r7
+ 800dcaa:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 800dcae:	4770      	bx	lr
+ 800dcb0:	effffffe 	.word	0xeffffffe
+
+0800dcb4 <HAL_UARTEx_DisableFifoMode>:
+  * @brief  Disable the FIFO mode.
+  * @param huart      UART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart)
+{
+ 800dcb4:	b480      	push	{r7}
+ 800dcb6:	b085      	sub	sp, #20
+ 800dcb8:	af00      	add	r7, sp, #0
+ 800dcba:	6078      	str	r0, [r7, #4]
+
+  /* Check parameters */
+  assert_param(IS_UART_FIFO_INSTANCE(huart->Instance));
+
+  /* Process Locked */
+  __HAL_LOCK(huart);
+ 800dcbc:	687b      	ldr	r3, [r7, #4]
+ 800dcbe:	f893 3084 	ldrb.w	r3, [r3, #132]	; 0x84
+ 800dcc2:	2b01      	cmp	r3, #1
+ 800dcc4:	d101      	bne.n	800dcca <HAL_UARTEx_DisableFifoMode+0x16>
+ 800dcc6:	2302      	movs	r3, #2
+ 800dcc8:	e027      	b.n	800dd1a <HAL_UARTEx_DisableFifoMode+0x66>
+ 800dcca:	687b      	ldr	r3, [r7, #4]
+ 800dccc:	2201      	movs	r2, #1
+ 800dcce:	f883 2084 	strb.w	r2, [r3, #132]	; 0x84
+
+  huart->gState = HAL_UART_STATE_BUSY;
+ 800dcd2:	687b      	ldr	r3, [r7, #4]
+ 800dcd4:	2224      	movs	r2, #36	; 0x24
+ 800dcd6:	f8c3 2088 	str.w	r2, [r3, #136]	; 0x88
+
+  /* Save actual UART configuration */
+  tmpcr1 = READ_REG(huart->Instance->CR1);
+ 800dcda:	687b      	ldr	r3, [r7, #4]
+ 800dcdc:	681b      	ldr	r3, [r3, #0]
+ 800dcde:	681b      	ldr	r3, [r3, #0]
+ 800dce0:	60fb      	str	r3, [r7, #12]
+
+  /* Disable UART */
+  __HAL_UART_DISABLE(huart);
+ 800dce2:	687b      	ldr	r3, [r7, #4]
+ 800dce4:	681b      	ldr	r3, [r3, #0]
+ 800dce6:	681a      	ldr	r2, [r3, #0]
+ 800dce8:	687b      	ldr	r3, [r7, #4]
+ 800dcea:	681b      	ldr	r3, [r3, #0]
+ 800dcec:	f022 0201 	bic.w	r2, r2, #1
+ 800dcf0:	601a      	str	r2, [r3, #0]
+
+  /* Enable FIFO mode */
+  CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN);
+ 800dcf2:	68fb      	ldr	r3, [r7, #12]
+ 800dcf4:	f023 5300 	bic.w	r3, r3, #536870912	; 0x20000000
+ 800dcf8:	60fb      	str	r3, [r7, #12]
+  huart->FifoMode = UART_FIFOMODE_DISABLE;
+ 800dcfa:	687b      	ldr	r3, [r7, #4]
+ 800dcfc:	2200      	movs	r2, #0
+ 800dcfe:	665a      	str	r2, [r3, #100]	; 0x64
+
+  /* Restore UART configuration */
+  WRITE_REG(huart->Instance->CR1, tmpcr1);
+ 800dd00:	687b      	ldr	r3, [r7, #4]
+ 800dd02:	681b      	ldr	r3, [r3, #0]
+ 800dd04:	68fa      	ldr	r2, [r7, #12]
+ 800dd06:	601a      	str	r2, [r3, #0]
+
+  huart->gState = HAL_UART_STATE_READY;
+ 800dd08:	687b      	ldr	r3, [r7, #4]
+ 800dd0a:	2220      	movs	r2, #32
+ 800dd0c:	f8c3 2088 	str.w	r2, [r3, #136]	; 0x88
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(huart);
+ 800dd10:	687b      	ldr	r3, [r7, #4]
+ 800dd12:	2200      	movs	r2, #0
+ 800dd14:	f883 2084 	strb.w	r2, [r3, #132]	; 0x84
+
+  return HAL_OK;
+ 800dd18:	2300      	movs	r3, #0
+}
+ 800dd1a:	4618      	mov	r0, r3
+ 800dd1c:	3714      	adds	r7, #20
+ 800dd1e:	46bd      	mov	sp, r7
+ 800dd20:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 800dd24:	4770      	bx	lr
+
+0800dd26 <HAL_UARTEx_SetTxFifoThreshold>:
+  *            @arg @ref UART_TXFIFO_THRESHOLD_7_8
+  *            @arg @ref UART_TXFIFO_THRESHOLD_8_8
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold)
+{
+ 800dd26:	b580      	push	{r7, lr}
+ 800dd28:	b084      	sub	sp, #16
+ 800dd2a:	af00      	add	r7, sp, #0
+ 800dd2c:	6078      	str	r0, [r7, #4]
+ 800dd2e:	6039      	str	r1, [r7, #0]
+  /* Check parameters */
+  assert_param(IS_UART_FIFO_INSTANCE(huart->Instance));
+  assert_param(IS_UART_TXFIFO_THRESHOLD(Threshold));
+
+  /* Process Locked */
+  __HAL_LOCK(huart);
+ 800dd30:	687b      	ldr	r3, [r7, #4]
+ 800dd32:	f893 3084 	ldrb.w	r3, [r3, #132]	; 0x84
+ 800dd36:	2b01      	cmp	r3, #1
+ 800dd38:	d101      	bne.n	800dd3e <HAL_UARTEx_SetTxFifoThreshold+0x18>
+ 800dd3a:	2302      	movs	r3, #2
+ 800dd3c:	e02d      	b.n	800dd9a <HAL_UARTEx_SetTxFifoThreshold+0x74>
+ 800dd3e:	687b      	ldr	r3, [r7, #4]
+ 800dd40:	2201      	movs	r2, #1
+ 800dd42:	f883 2084 	strb.w	r2, [r3, #132]	; 0x84
+
+  huart->gState = HAL_UART_STATE_BUSY;
+ 800dd46:	687b      	ldr	r3, [r7, #4]
+ 800dd48:	2224      	movs	r2, #36	; 0x24
+ 800dd4a:	f8c3 2088 	str.w	r2, [r3, #136]	; 0x88
+
+  /* Save actual UART configuration */
+  tmpcr1 = READ_REG(huart->Instance->CR1);
+ 800dd4e:	687b      	ldr	r3, [r7, #4]
+ 800dd50:	681b      	ldr	r3, [r3, #0]
+ 800dd52:	681b      	ldr	r3, [r3, #0]
+ 800dd54:	60fb      	str	r3, [r7, #12]
+
+  /* Disable UART */
+  __HAL_UART_DISABLE(huart);
+ 800dd56:	687b      	ldr	r3, [r7, #4]
+ 800dd58:	681b      	ldr	r3, [r3, #0]
+ 800dd5a:	681a      	ldr	r2, [r3, #0]
+ 800dd5c:	687b      	ldr	r3, [r7, #4]
+ 800dd5e:	681b      	ldr	r3, [r3, #0]
+ 800dd60:	f022 0201 	bic.w	r2, r2, #1
+ 800dd64:	601a      	str	r2, [r3, #0]
+
+  /* Update TX threshold configuration */
+  MODIFY_REG(huart->Instance->CR3, USART_CR3_TXFTCFG, Threshold);
+ 800dd66:	687b      	ldr	r3, [r7, #4]
+ 800dd68:	681b      	ldr	r3, [r3, #0]
+ 800dd6a:	689b      	ldr	r3, [r3, #8]
+ 800dd6c:	f023 4160 	bic.w	r1, r3, #3758096384	; 0xe0000000
+ 800dd70:	687b      	ldr	r3, [r7, #4]
+ 800dd72:	681b      	ldr	r3, [r3, #0]
+ 800dd74:	683a      	ldr	r2, [r7, #0]
+ 800dd76:	430a      	orrs	r2, r1
+ 800dd78:	609a      	str	r2, [r3, #8]
+
+  /* Determine the number of data to process during RX/TX ISR execution */
+  UARTEx_SetNbDataToProcess(huart);
+ 800dd7a:	6878      	ldr	r0, [r7, #4]
+ 800dd7c:	f000 f850 	bl	800de20 <UARTEx_SetNbDataToProcess>
+
+  /* Restore UART configuration */
+  WRITE_REG(huart->Instance->CR1, tmpcr1);
+ 800dd80:	687b      	ldr	r3, [r7, #4]
+ 800dd82:	681b      	ldr	r3, [r3, #0]
+ 800dd84:	68fa      	ldr	r2, [r7, #12]
+ 800dd86:	601a      	str	r2, [r3, #0]
+
+  huart->gState = HAL_UART_STATE_READY;
+ 800dd88:	687b      	ldr	r3, [r7, #4]
+ 800dd8a:	2220      	movs	r2, #32
+ 800dd8c:	f8c3 2088 	str.w	r2, [r3, #136]	; 0x88
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(huart);
+ 800dd90:	687b      	ldr	r3, [r7, #4]
+ 800dd92:	2200      	movs	r2, #0
+ 800dd94:	f883 2084 	strb.w	r2, [r3, #132]	; 0x84
+
+  return HAL_OK;
+ 800dd98:	2300      	movs	r3, #0
+}
+ 800dd9a:	4618      	mov	r0, r3
+ 800dd9c:	3710      	adds	r7, #16
+ 800dd9e:	46bd      	mov	sp, r7
+ 800dda0:	bd80      	pop	{r7, pc}
+
+0800dda2 <HAL_UARTEx_SetRxFifoThreshold>:
+  *            @arg @ref UART_RXFIFO_THRESHOLD_7_8
+  *            @arg @ref UART_RXFIFO_THRESHOLD_8_8
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold)
+{
+ 800dda2:	b580      	push	{r7, lr}
+ 800dda4:	b084      	sub	sp, #16
+ 800dda6:	af00      	add	r7, sp, #0
+ 800dda8:	6078      	str	r0, [r7, #4]
+ 800ddaa:	6039      	str	r1, [r7, #0]
+  /* Check the parameters */
+  assert_param(IS_UART_FIFO_INSTANCE(huart->Instance));
+  assert_param(IS_UART_RXFIFO_THRESHOLD(Threshold));
+
+  /* Process Locked */
+  __HAL_LOCK(huart);
+ 800ddac:	687b      	ldr	r3, [r7, #4]
+ 800ddae:	f893 3084 	ldrb.w	r3, [r3, #132]	; 0x84
+ 800ddb2:	2b01      	cmp	r3, #1
+ 800ddb4:	d101      	bne.n	800ddba <HAL_UARTEx_SetRxFifoThreshold+0x18>
+ 800ddb6:	2302      	movs	r3, #2
+ 800ddb8:	e02d      	b.n	800de16 <HAL_UARTEx_SetRxFifoThreshold+0x74>
+ 800ddba:	687b      	ldr	r3, [r7, #4]
+ 800ddbc:	2201      	movs	r2, #1
+ 800ddbe:	f883 2084 	strb.w	r2, [r3, #132]	; 0x84
+
+  huart->gState = HAL_UART_STATE_BUSY;
+ 800ddc2:	687b      	ldr	r3, [r7, #4]
+ 800ddc4:	2224      	movs	r2, #36	; 0x24
+ 800ddc6:	f8c3 2088 	str.w	r2, [r3, #136]	; 0x88
+
+  /* Save actual UART configuration */
+  tmpcr1 = READ_REG(huart->Instance->CR1);
+ 800ddca:	687b      	ldr	r3, [r7, #4]
+ 800ddcc:	681b      	ldr	r3, [r3, #0]
+ 800ddce:	681b      	ldr	r3, [r3, #0]
+ 800ddd0:	60fb      	str	r3, [r7, #12]
+
+  /* Disable UART */
+  __HAL_UART_DISABLE(huart);
+ 800ddd2:	687b      	ldr	r3, [r7, #4]
+ 800ddd4:	681b      	ldr	r3, [r3, #0]
+ 800ddd6:	681a      	ldr	r2, [r3, #0]
+ 800ddd8:	687b      	ldr	r3, [r7, #4]
+ 800ddda:	681b      	ldr	r3, [r3, #0]
+ 800dddc:	f022 0201 	bic.w	r2, r2, #1
+ 800dde0:	601a      	str	r2, [r3, #0]
+
+  /* Update RX threshold configuration */
+  MODIFY_REG(huart->Instance->CR3, USART_CR3_RXFTCFG, Threshold);
+ 800dde2:	687b      	ldr	r3, [r7, #4]
+ 800dde4:	681b      	ldr	r3, [r3, #0]
+ 800dde6:	689b      	ldr	r3, [r3, #8]
+ 800dde8:	f023 6160 	bic.w	r1, r3, #234881024	; 0xe000000
+ 800ddec:	687b      	ldr	r3, [r7, #4]
+ 800ddee:	681b      	ldr	r3, [r3, #0]
+ 800ddf0:	683a      	ldr	r2, [r7, #0]
+ 800ddf2:	430a      	orrs	r2, r1
+ 800ddf4:	609a      	str	r2, [r3, #8]
+
+  /* Determine the number of data to process during RX/TX ISR execution */
+  UARTEx_SetNbDataToProcess(huart);
+ 800ddf6:	6878      	ldr	r0, [r7, #4]
+ 800ddf8:	f000 f812 	bl	800de20 <UARTEx_SetNbDataToProcess>
+
+  /* Restore UART configuration */
+  WRITE_REG(huart->Instance->CR1, tmpcr1);
+ 800ddfc:	687b      	ldr	r3, [r7, #4]
+ 800ddfe:	681b      	ldr	r3, [r3, #0]
+ 800de00:	68fa      	ldr	r2, [r7, #12]
+ 800de02:	601a      	str	r2, [r3, #0]
+
+  huart->gState = HAL_UART_STATE_READY;
+ 800de04:	687b      	ldr	r3, [r7, #4]
+ 800de06:	2220      	movs	r2, #32
+ 800de08:	f8c3 2088 	str.w	r2, [r3, #136]	; 0x88
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(huart);
+ 800de0c:	687b      	ldr	r3, [r7, #4]
+ 800de0e:	2200      	movs	r2, #0
+ 800de10:	f883 2084 	strb.w	r2, [r3, #132]	; 0x84
+
+  return HAL_OK;
+ 800de14:	2300      	movs	r3, #0
+}
+ 800de16:	4618      	mov	r0, r3
+ 800de18:	3710      	adds	r7, #16
+ 800de1a:	46bd      	mov	sp, r7
+ 800de1c:	bd80      	pop	{r7, pc}
+	...
+
+0800de20 <UARTEx_SetNbDataToProcess>:
+  *       the UART configuration registers.
+  * @param huart UART handle.
+  * @retval None
+  */
+static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart)
+{
+ 800de20:	b480      	push	{r7}
+ 800de22:	b085      	sub	sp, #20
+ 800de24:	af00      	add	r7, sp, #0
+ 800de26:	6078      	str	r0, [r7, #4]
+  uint8_t rx_fifo_threshold;
+  uint8_t tx_fifo_threshold;
+  static const uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U};
+  static const uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U};
+
+  if (huart->FifoMode == UART_FIFOMODE_DISABLE)
+ 800de28:	687b      	ldr	r3, [r7, #4]
+ 800de2a:	6e5b      	ldr	r3, [r3, #100]	; 0x64
+ 800de2c:	2b00      	cmp	r3, #0
+ 800de2e:	d108      	bne.n	800de42 <UARTEx_SetNbDataToProcess+0x22>
+  {
+    huart->NbTxDataToProcess = 1U;
+ 800de30:	687b      	ldr	r3, [r7, #4]
+ 800de32:	2201      	movs	r2, #1
+ 800de34:	f8a3 206a 	strh.w	r2, [r3, #106]	; 0x6a
+    huart->NbRxDataToProcess = 1U;
+ 800de38:	687b      	ldr	r3, [r7, #4]
+ 800de3a:	2201      	movs	r2, #1
+ 800de3c:	f8a3 2068 	strh.w	r2, [r3, #104]	; 0x68
+    huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) /
+                               (uint16_t)denominator[tx_fifo_threshold];
+    huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) /
+                               (uint16_t)denominator[rx_fifo_threshold];
+  }
+}
+ 800de40:	e031      	b.n	800dea6 <UARTEx_SetNbDataToProcess+0x86>
+    rx_fifo_depth = RX_FIFO_DEPTH;
+ 800de42:	2310      	movs	r3, #16
+ 800de44:	73fb      	strb	r3, [r7, #15]
+    tx_fifo_depth = TX_FIFO_DEPTH;
+ 800de46:	2310      	movs	r3, #16
+ 800de48:	73bb      	strb	r3, [r7, #14]
+    rx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos);
+ 800de4a:	687b      	ldr	r3, [r7, #4]
+ 800de4c:	681b      	ldr	r3, [r3, #0]
+ 800de4e:	689b      	ldr	r3, [r3, #8]
+ 800de50:	0e5b      	lsrs	r3, r3, #25
+ 800de52:	b2db      	uxtb	r3, r3
+ 800de54:	f003 0307 	and.w	r3, r3, #7
+ 800de58:	737b      	strb	r3, [r7, #13]
+    tx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos);
+ 800de5a:	687b      	ldr	r3, [r7, #4]
+ 800de5c:	681b      	ldr	r3, [r3, #0]
+ 800de5e:	689b      	ldr	r3, [r3, #8]
+ 800de60:	0f5b      	lsrs	r3, r3, #29
+ 800de62:	b2db      	uxtb	r3, r3
+ 800de64:	f003 0307 	and.w	r3, r3, #7
+ 800de68:	733b      	strb	r3, [r7, #12]
+    huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) /
+ 800de6a:	7bbb      	ldrb	r3, [r7, #14]
+ 800de6c:	7b3a      	ldrb	r2, [r7, #12]
+ 800de6e:	4911      	ldr	r1, [pc, #68]	; (800deb4 <UARTEx_SetNbDataToProcess+0x94>)
+ 800de70:	5c8a      	ldrb	r2, [r1, r2]
+ 800de72:	fb02 f303 	mul.w	r3, r2, r3
+                               (uint16_t)denominator[tx_fifo_threshold];
+ 800de76:	7b3a      	ldrb	r2, [r7, #12]
+ 800de78:	490f      	ldr	r1, [pc, #60]	; (800deb8 <UARTEx_SetNbDataToProcess+0x98>)
+ 800de7a:	5c8a      	ldrb	r2, [r1, r2]
+    huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) /
+ 800de7c:	fb93 f3f2 	sdiv	r3, r3, r2
+ 800de80:	b29a      	uxth	r2, r3
+ 800de82:	687b      	ldr	r3, [r7, #4]
+ 800de84:	f8a3 206a 	strh.w	r2, [r3, #106]	; 0x6a
+    huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) /
+ 800de88:	7bfb      	ldrb	r3, [r7, #15]
+ 800de8a:	7b7a      	ldrb	r2, [r7, #13]
+ 800de8c:	4909      	ldr	r1, [pc, #36]	; (800deb4 <UARTEx_SetNbDataToProcess+0x94>)
+ 800de8e:	5c8a      	ldrb	r2, [r1, r2]
+ 800de90:	fb02 f303 	mul.w	r3, r2, r3
+                               (uint16_t)denominator[rx_fifo_threshold];
+ 800de94:	7b7a      	ldrb	r2, [r7, #13]
+ 800de96:	4908      	ldr	r1, [pc, #32]	; (800deb8 <UARTEx_SetNbDataToProcess+0x98>)
+ 800de98:	5c8a      	ldrb	r2, [r1, r2]
+    huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) /
+ 800de9a:	fb93 f3f2 	sdiv	r3, r3, r2
+ 800de9e:	b29a      	uxth	r2, r3
+ 800dea0:	687b      	ldr	r3, [r7, #4]
+ 800dea2:	f8a3 2068 	strh.w	r2, [r3, #104]	; 0x68
+}
+ 800dea6:	bf00      	nop
+ 800dea8:	3714      	adds	r7, #20
+ 800deaa:	46bd      	mov	sp, r7
+ 800deac:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 800deb0:	4770      	bx	lr
+ 800deb2:	bf00      	nop
+ 800deb4:	08026b70 	.word	0x08026b70
+ 800deb8:	08026b78 	.word	0x08026b78
+
+0800debc <SDMMC_Init>:
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @param  Init: SDMMC initialization structure
+  * @retval HAL status
+  */
+HAL_StatusTypeDef SDMMC_Init(SDMMC_TypeDef *SDMMCx, SDMMC_InitTypeDef Init)
+{
+ 800debc:	b084      	sub	sp, #16
+ 800debe:	b480      	push	{r7}
+ 800dec0:	b085      	sub	sp, #20
+ 800dec2:	af00      	add	r7, sp, #0
+ 800dec4:	6078      	str	r0, [r7, #4]
+ 800dec6:	f107 001c 	add.w	r0, r7, #28
+ 800deca:	e880 000e 	stmia.w	r0, {r1, r2, r3}
+  uint32_t tmpreg = 0;
+ 800dece:	2300      	movs	r3, #0
+ 800ded0:	60fb      	str	r3, [r7, #12]
+  assert_param(IS_SDMMC_BUS_WIDE(Init.BusWide));
+  assert_param(IS_SDMMC_HARDWARE_FLOW_CONTROL(Init.HardwareFlowControl));
+  assert_param(IS_SDMMC_CLKDIV(Init.ClockDiv));
+
+  /* Set SDMMC configuration parameters */
+  tmpreg |= (Init.ClockEdge           | \
+ 800ded2:	69fa      	ldr	r2, [r7, #28]
+             Init.ClockPowerSave      | \
+ 800ded4:	6a3b      	ldr	r3, [r7, #32]
+  tmpreg |= (Init.ClockEdge           | \
+ 800ded6:	431a      	orrs	r2, r3
+             Init.BusWide             | \
+ 800ded8:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+             Init.ClockPowerSave      | \
+ 800deda:	431a      	orrs	r2, r3
+             Init.HardwareFlowControl | \
+ 800dedc:	6abb      	ldr	r3, [r7, #40]	; 0x28
+             Init.BusWide             | \
+ 800dede:	431a      	orrs	r2, r3
+             Init.ClockDiv
+ 800dee0:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+             Init.HardwareFlowControl | \
+ 800dee2:	4313      	orrs	r3, r2
+  tmpreg |= (Init.ClockEdge           | \
+ 800dee4:	68fa      	ldr	r2, [r7, #12]
+ 800dee6:	4313      	orrs	r3, r2
+ 800dee8:	60fb      	str	r3, [r7, #12]
+            );
+
+  /* Write to SDMMC CLKCR */
+  MODIFY_REG(SDMMCx->CLKCR, CLKCR_CLEAR_MASK, tmpreg);
+ 800deea:	687b      	ldr	r3, [r7, #4]
+ 800deec:	685a      	ldr	r2, [r3, #4]
+ 800deee:	4b07      	ldr	r3, [pc, #28]	; (800df0c <SDMMC_Init+0x50>)
+ 800def0:	4013      	ands	r3, r2
+ 800def2:	68fa      	ldr	r2, [r7, #12]
+ 800def4:	431a      	orrs	r2, r3
+ 800def6:	687b      	ldr	r3, [r7, #4]
+ 800def8:	605a      	str	r2, [r3, #4]
+
+  return HAL_OK;
+ 800defa:	2300      	movs	r3, #0
+}
+ 800defc:	4618      	mov	r0, r3
+ 800defe:	3714      	adds	r7, #20
+ 800df00:	46bd      	mov	sp, r7
+ 800df02:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 800df06:	b004      	add	sp, #16
+ 800df08:	4770      	bx	lr
+ 800df0a:	bf00      	nop
+ 800df0c:	ffc02c00 	.word	0xffc02c00
+
+0800df10 <SDMMC_ReadFIFO>:
+  * @brief  Read data (word) from Rx FIFO in blocking mode (polling)
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @retval HAL status
+  */
+uint32_t SDMMC_ReadFIFO(SDMMC_TypeDef *SDMMCx)
+{
+ 800df10:	b480      	push	{r7}
+ 800df12:	b083      	sub	sp, #12
+ 800df14:	af00      	add	r7, sp, #0
+ 800df16:	6078      	str	r0, [r7, #4]
+  /* Read data from Rx FIFO */
+  return (SDMMCx->FIFO);
+ 800df18:	687b      	ldr	r3, [r7, #4]
+ 800df1a:	f8d3 3080 	ldr.w	r3, [r3, #128]	; 0x80
+}
+ 800df1e:	4618      	mov	r0, r3
+ 800df20:	370c      	adds	r7, #12
+ 800df22:	46bd      	mov	sp, r7
+ 800df24:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 800df28:	4770      	bx	lr
+
+0800df2a <SDMMC_WriteFIFO>:
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @param  pWriteData: pointer to data to write
+  * @retval HAL status
+  */
+HAL_StatusTypeDef SDMMC_WriteFIFO(SDMMC_TypeDef *SDMMCx, uint32_t *pWriteData)
+{
+ 800df2a:	b480      	push	{r7}
+ 800df2c:	b083      	sub	sp, #12
+ 800df2e:	af00      	add	r7, sp, #0
+ 800df30:	6078      	str	r0, [r7, #4]
+ 800df32:	6039      	str	r1, [r7, #0]
+  /* Write data to FIFO */
+  SDMMCx->FIFO = *pWriteData;
+ 800df34:	683b      	ldr	r3, [r7, #0]
+ 800df36:	681a      	ldr	r2, [r3, #0]
+ 800df38:	687b      	ldr	r3, [r7, #4]
+ 800df3a:	f8c3 2080 	str.w	r2, [r3, #128]	; 0x80
+
+  return HAL_OK;
+ 800df3e:	2300      	movs	r3, #0
+}
+ 800df40:	4618      	mov	r0, r3
+ 800df42:	370c      	adds	r7, #12
+ 800df44:	46bd      	mov	sp, r7
+ 800df46:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 800df4a:	4770      	bx	lr
+
+0800df4c <SDMMC_PowerState_ON>:
+  * @brief  Set SDMMC Power state to ON.
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @retval HAL status
+  */
+HAL_StatusTypeDef SDMMC_PowerState_ON(SDMMC_TypeDef *SDMMCx)
+{
+ 800df4c:	b480      	push	{r7}
+ 800df4e:	b083      	sub	sp, #12
+ 800df50:	af00      	add	r7, sp, #0
+ 800df52:	6078      	str	r0, [r7, #4]
+  /* Set power state to ON */
+  SDMMCx->POWER |= SDMMC_POWER_PWRCTRL;
+ 800df54:	687b      	ldr	r3, [r7, #4]
+ 800df56:	681b      	ldr	r3, [r3, #0]
+ 800df58:	f043 0203 	orr.w	r2, r3, #3
+ 800df5c:	687b      	ldr	r3, [r7, #4]
+ 800df5e:	601a      	str	r2, [r3, #0]
+
+  return HAL_OK;
+ 800df60:	2300      	movs	r3, #0
+}
+ 800df62:	4618      	mov	r0, r3
+ 800df64:	370c      	adds	r7, #12
+ 800df66:	46bd      	mov	sp, r7
+ 800df68:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 800df6c:	4770      	bx	lr
+
+0800df6e <SDMMC_GetPowerState>:
+  *            - 0x00: Power OFF
+  *            - 0x02: Power UP
+  *            - 0x03: Power ON
+  */
+uint32_t SDMMC_GetPowerState(SDMMC_TypeDef *SDMMCx)
+{
+ 800df6e:	b480      	push	{r7}
+ 800df70:	b083      	sub	sp, #12
+ 800df72:	af00      	add	r7, sp, #0
+ 800df74:	6078      	str	r0, [r7, #4]
+  return (SDMMCx->POWER & SDMMC_POWER_PWRCTRL);
+ 800df76:	687b      	ldr	r3, [r7, #4]
+ 800df78:	681b      	ldr	r3, [r3, #0]
+ 800df7a:	f003 0303 	and.w	r3, r3, #3
+}
+ 800df7e:	4618      	mov	r0, r3
+ 800df80:	370c      	adds	r7, #12
+ 800df82:	46bd      	mov	sp, r7
+ 800df84:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 800df88:	4770      	bx	lr
+	...
+
+0800df8c <SDMMC_SendCommand>:
+  * @param  Command: pointer to a SDMMC_CmdInitTypeDef structure that contains
+  *         the configuration information for the SDMMC command
+  * @retval HAL status
+  */
+HAL_StatusTypeDef SDMMC_SendCommand(SDMMC_TypeDef *SDMMCx, SDMMC_CmdInitTypeDef *Command)
+{
+ 800df8c:	b480      	push	{r7}
+ 800df8e:	b085      	sub	sp, #20
+ 800df90:	af00      	add	r7, sp, #0
+ 800df92:	6078      	str	r0, [r7, #4]
+ 800df94:	6039      	str	r1, [r7, #0]
+  uint32_t tmpreg = 0;
+ 800df96:	2300      	movs	r3, #0
+ 800df98:	60fb      	str	r3, [r7, #12]
+  assert_param(IS_SDMMC_RESPONSE(Command->Response));
+  assert_param(IS_SDMMC_WAIT(Command->WaitForInterrupt));
+  assert_param(IS_SDMMC_CPSM(Command->CPSM));
+
+  /* Set the SDMMC Argument value */
+  SDMMCx->ARG = Command->Argument;
+ 800df9a:	683b      	ldr	r3, [r7, #0]
+ 800df9c:	681a      	ldr	r2, [r3, #0]
+ 800df9e:	687b      	ldr	r3, [r7, #4]
+ 800dfa0:	609a      	str	r2, [r3, #8]
+
+  /* Set SDMMC command parameters */
+  tmpreg |= (uint32_t)(Command->CmdIndex         | \
+ 800dfa2:	683b      	ldr	r3, [r7, #0]
+ 800dfa4:	685a      	ldr	r2, [r3, #4]
+                       Command->Response         | \
+ 800dfa6:	683b      	ldr	r3, [r7, #0]
+ 800dfa8:	689b      	ldr	r3, [r3, #8]
+  tmpreg |= (uint32_t)(Command->CmdIndex         | \
+ 800dfaa:	431a      	orrs	r2, r3
+                       Command->WaitForInterrupt | \
+ 800dfac:	683b      	ldr	r3, [r7, #0]
+ 800dfae:	68db      	ldr	r3, [r3, #12]
+                       Command->Response         | \
+ 800dfb0:	431a      	orrs	r2, r3
+                       Command->CPSM);
+ 800dfb2:	683b      	ldr	r3, [r7, #0]
+ 800dfb4:	691b      	ldr	r3, [r3, #16]
+                       Command->WaitForInterrupt | \
+ 800dfb6:	4313      	orrs	r3, r2
+  tmpreg |= (uint32_t)(Command->CmdIndex         | \
+ 800dfb8:	68fa      	ldr	r2, [r7, #12]
+ 800dfba:	4313      	orrs	r3, r2
+ 800dfbc:	60fb      	str	r3, [r7, #12]
+
+  /* Write to SDMMC CMD register */
+  MODIFY_REG(SDMMCx->CMD, CMD_CLEAR_MASK, tmpreg);
+ 800dfbe:	687b      	ldr	r3, [r7, #4]
+ 800dfc0:	68da      	ldr	r2, [r3, #12]
+ 800dfc2:	4b06      	ldr	r3, [pc, #24]	; (800dfdc <SDMMC_SendCommand+0x50>)
+ 800dfc4:	4013      	ands	r3, r2
+ 800dfc6:	68fa      	ldr	r2, [r7, #12]
+ 800dfc8:	431a      	orrs	r2, r3
+ 800dfca:	687b      	ldr	r3, [r7, #4]
+ 800dfcc:	60da      	str	r2, [r3, #12]
+
+  return HAL_OK;
+ 800dfce:	2300      	movs	r3, #0
+}
+ 800dfd0:	4618      	mov	r0, r3
+ 800dfd2:	3714      	adds	r7, #20
+ 800dfd4:	46bd      	mov	sp, r7
+ 800dfd6:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 800dfda:	4770      	bx	lr
+ 800dfdc:	fffee0c0 	.word	0xfffee0c0
+
+0800dfe0 <SDMMC_GetCommandResponse>:
+  * @brief  Return the command index of last command for which response received
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @retval Command index of the last command response received
+  */
+uint8_t SDMMC_GetCommandResponse(SDMMC_TypeDef *SDMMCx)
+{
+ 800dfe0:	b480      	push	{r7}
+ 800dfe2:	b083      	sub	sp, #12
+ 800dfe4:	af00      	add	r7, sp, #0
+ 800dfe6:	6078      	str	r0, [r7, #4]
+  return (uint8_t)(SDMMCx->RESPCMD);
+ 800dfe8:	687b      	ldr	r3, [r7, #4]
+ 800dfea:	691b      	ldr	r3, [r3, #16]
+ 800dfec:	b2db      	uxtb	r3, r3
+}
+ 800dfee:	4618      	mov	r0, r3
+ 800dff0:	370c      	adds	r7, #12
+ 800dff2:	46bd      	mov	sp, r7
+ 800dff4:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 800dff8:	4770      	bx	lr
+
+0800dffa <SDMMC_GetResponse>:
+  *            @arg SDMMC_RESP3: Response Register 3
+  *            @arg SDMMC_RESP4: Response Register 4
+  * @retval The Corresponding response register value
+  */
+uint32_t SDMMC_GetResponse(SDMMC_TypeDef *SDMMCx, uint32_t Response)
+{
+ 800dffa:	b480      	push	{r7}
+ 800dffc:	b085      	sub	sp, #20
+ 800dffe:	af00      	add	r7, sp, #0
+ 800e000:	6078      	str	r0, [r7, #4]
+ 800e002:	6039      	str	r1, [r7, #0]
+
+  /* Check the parameters */
+  assert_param(IS_SDMMC_RESP(Response));
+
+  /* Get the response */
+  tmp = (uint32_t)(&(SDMMCx->RESP1)) + Response;
+ 800e004:	687b      	ldr	r3, [r7, #4]
+ 800e006:	3314      	adds	r3, #20
+ 800e008:	461a      	mov	r2, r3
+ 800e00a:	683b      	ldr	r3, [r7, #0]
+ 800e00c:	4413      	add	r3, r2
+ 800e00e:	60fb      	str	r3, [r7, #12]
+
+  return (*(__IO uint32_t *) tmp);
+ 800e010:	68fb      	ldr	r3, [r7, #12]
+ 800e012:	681b      	ldr	r3, [r3, #0]
+}
+ 800e014:	4618      	mov	r0, r3
+ 800e016:	3714      	adds	r7, #20
+ 800e018:	46bd      	mov	sp, r7
+ 800e01a:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 800e01e:	4770      	bx	lr
+
+0800e020 <SDMMC_ConfigData>:
+  * @param  Data : pointer to a SDMMC_DataInitTypeDef structure
+  *         that contains the configuration information for the SDMMC data.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef SDMMC_ConfigData(SDMMC_TypeDef *SDMMCx, SDMMC_DataInitTypeDef *Data)
+{
+ 800e020:	b480      	push	{r7}
+ 800e022:	b085      	sub	sp, #20
+ 800e024:	af00      	add	r7, sp, #0
+ 800e026:	6078      	str	r0, [r7, #4]
+ 800e028:	6039      	str	r1, [r7, #0]
+  uint32_t tmpreg = 0;
+ 800e02a:	2300      	movs	r3, #0
+ 800e02c:	60fb      	str	r3, [r7, #12]
+  assert_param(IS_SDMMC_TRANSFER_DIR(Data->TransferDir));
+  assert_param(IS_SDMMC_TRANSFER_MODE(Data->TransferMode));
+  assert_param(IS_SDMMC_DPSM(Data->DPSM));
+
+  /* Set the SDMMC Data TimeOut value */
+  SDMMCx->DTIMER = Data->DataTimeOut;
+ 800e02e:	683b      	ldr	r3, [r7, #0]
+ 800e030:	681a      	ldr	r2, [r3, #0]
+ 800e032:	687b      	ldr	r3, [r7, #4]
+ 800e034:	625a      	str	r2, [r3, #36]	; 0x24
+
+  /* Set the SDMMC DataLength value */
+  SDMMCx->DLEN = Data->DataLength;
+ 800e036:	683b      	ldr	r3, [r7, #0]
+ 800e038:	685a      	ldr	r2, [r3, #4]
+ 800e03a:	687b      	ldr	r3, [r7, #4]
+ 800e03c:	629a      	str	r2, [r3, #40]	; 0x28
+
+  /* Set the SDMMC data configuration parameters */
+  tmpreg |= (uint32_t)(Data->DataBlockSize | \
+ 800e03e:	683b      	ldr	r3, [r7, #0]
+ 800e040:	689a      	ldr	r2, [r3, #8]
+                       Data->TransferDir   | \
+ 800e042:	683b      	ldr	r3, [r7, #0]
+ 800e044:	68db      	ldr	r3, [r3, #12]
+  tmpreg |= (uint32_t)(Data->DataBlockSize | \
+ 800e046:	431a      	orrs	r2, r3
+                       Data->TransferMode  | \
+ 800e048:	683b      	ldr	r3, [r7, #0]
+ 800e04a:	691b      	ldr	r3, [r3, #16]
+                       Data->TransferDir   | \
+ 800e04c:	431a      	orrs	r2, r3
+                       Data->DPSM);
+ 800e04e:	683b      	ldr	r3, [r7, #0]
+ 800e050:	695b      	ldr	r3, [r3, #20]
+                       Data->TransferMode  | \
+ 800e052:	4313      	orrs	r3, r2
+  tmpreg |= (uint32_t)(Data->DataBlockSize | \
+ 800e054:	68fa      	ldr	r2, [r7, #12]
+ 800e056:	4313      	orrs	r3, r2
+ 800e058:	60fb      	str	r3, [r7, #12]
+
+  /* Write to SDMMC DCTRL */
+  MODIFY_REG(SDMMCx->DCTRL, DCTRL_CLEAR_MASK, tmpreg);
+ 800e05a:	687b      	ldr	r3, [r7, #4]
+ 800e05c:	6adb      	ldr	r3, [r3, #44]	; 0x2c
+ 800e05e:	f023 02ff 	bic.w	r2, r3, #255	; 0xff
+ 800e062:	68fb      	ldr	r3, [r7, #12]
+ 800e064:	431a      	orrs	r2, r3
+ 800e066:	687b      	ldr	r3, [r7, #4]
+ 800e068:	62da      	str	r2, [r3, #44]	; 0x2c
+
+  return HAL_OK;
+ 800e06a:	2300      	movs	r3, #0
+
+}
+ 800e06c:	4618      	mov	r0, r3
+ 800e06e:	3714      	adds	r7, #20
+ 800e070:	46bd      	mov	sp, r7
+ 800e072:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 800e076:	4770      	bx	lr
+
+0800e078 <SDMMC_CmdBlockLength>:
+  * @brief  Send the Data Block Length command and check the response
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdBlockLength(SDMMC_TypeDef *SDMMCx, uint32_t BlockSize)
+{
+ 800e078:	b580      	push	{r7, lr}
+ 800e07a:	b088      	sub	sp, #32
+ 800e07c:	af00      	add	r7, sp, #0
+ 800e07e:	6078      	str	r0, [r7, #4]
+ 800e080:	6039      	str	r1, [r7, #0]
+  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+
+  /* Set Block Size for Card */
+  sdmmc_cmdinit.Argument         = (uint32_t)BlockSize;
+ 800e082:	683b      	ldr	r3, [r7, #0]
+ 800e084:	60bb      	str	r3, [r7, #8]
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SET_BLOCKLEN;
+ 800e086:	2310      	movs	r3, #16
+ 800e088:	60fb      	str	r3, [r7, #12]
+  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+ 800e08a:	f44f 7380 	mov.w	r3, #256	; 0x100
+ 800e08e:	613b      	str	r3, [r7, #16]
+  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+ 800e090:	2300      	movs	r3, #0
+ 800e092:	617b      	str	r3, [r7, #20]
+  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+ 800e094:	f44f 5380 	mov.w	r3, #4096	; 0x1000
+ 800e098:	61bb      	str	r3, [r7, #24]
+  (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+ 800e09a:	f107 0308 	add.w	r3, r7, #8
+ 800e09e:	4619      	mov	r1, r3
+ 800e0a0:	6878      	ldr	r0, [r7, #4]
+ 800e0a2:	f7ff ff73 	bl	800df8c <SDMMC_SendCommand>
+
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SET_BLOCKLEN, SDMMC_CMDTIMEOUT);
+ 800e0a6:	f241 3288 	movw	r2, #5000	; 0x1388
+ 800e0aa:	2110      	movs	r1, #16
+ 800e0ac:	6878      	ldr	r0, [r7, #4]
+ 800e0ae:	f000 fa5f 	bl	800e570 <SDMMC_GetCmdResp1>
+ 800e0b2:	61f8      	str	r0, [r7, #28]
+
+  return errorstate;
+ 800e0b4:	69fb      	ldr	r3, [r7, #28]
+}
+ 800e0b6:	4618      	mov	r0, r3
+ 800e0b8:	3720      	adds	r7, #32
+ 800e0ba:	46bd      	mov	sp, r7
+ 800e0bc:	bd80      	pop	{r7, pc}
+
+0800e0be <SDMMC_CmdReadSingleBlock>:
+  * @brief  Send the Read Single Block command and check the response
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdReadSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd)
+{
+ 800e0be:	b580      	push	{r7, lr}
+ 800e0c0:	b088      	sub	sp, #32
+ 800e0c2:	af00      	add	r7, sp, #0
+ 800e0c4:	6078      	str	r0, [r7, #4]
+ 800e0c6:	6039      	str	r1, [r7, #0]
+  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+
+  /* Set Block Size for Card */
+  sdmmc_cmdinit.Argument         = (uint32_t)ReadAdd;
+ 800e0c8:	683b      	ldr	r3, [r7, #0]
+ 800e0ca:	60bb      	str	r3, [r7, #8]
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_READ_SINGLE_BLOCK;
+ 800e0cc:	2311      	movs	r3, #17
+ 800e0ce:	60fb      	str	r3, [r7, #12]
+  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+ 800e0d0:	f44f 7380 	mov.w	r3, #256	; 0x100
+ 800e0d4:	613b      	str	r3, [r7, #16]
+  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+ 800e0d6:	2300      	movs	r3, #0
+ 800e0d8:	617b      	str	r3, [r7, #20]
+  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+ 800e0da:	f44f 5380 	mov.w	r3, #4096	; 0x1000
+ 800e0de:	61bb      	str	r3, [r7, #24]
+  (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+ 800e0e0:	f107 0308 	add.w	r3, r7, #8
+ 800e0e4:	4619      	mov	r1, r3
+ 800e0e6:	6878      	ldr	r0, [r7, #4]
+ 800e0e8:	f7ff ff50 	bl	800df8c <SDMMC_SendCommand>
+
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_READ_SINGLE_BLOCK, SDMMC_CMDTIMEOUT);
+ 800e0ec:	f241 3288 	movw	r2, #5000	; 0x1388
+ 800e0f0:	2111      	movs	r1, #17
+ 800e0f2:	6878      	ldr	r0, [r7, #4]
+ 800e0f4:	f000 fa3c 	bl	800e570 <SDMMC_GetCmdResp1>
+ 800e0f8:	61f8      	str	r0, [r7, #28]
+
+  return errorstate;
+ 800e0fa:	69fb      	ldr	r3, [r7, #28]
+}
+ 800e0fc:	4618      	mov	r0, r3
+ 800e0fe:	3720      	adds	r7, #32
+ 800e100:	46bd      	mov	sp, r7
+ 800e102:	bd80      	pop	{r7, pc}
+
+0800e104 <SDMMC_CmdReadMultiBlock>:
+  * @brief  Send the Read Multi Block command and check the response
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdReadMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd)
+{
+ 800e104:	b580      	push	{r7, lr}
+ 800e106:	b088      	sub	sp, #32
+ 800e108:	af00      	add	r7, sp, #0
+ 800e10a:	6078      	str	r0, [r7, #4]
+ 800e10c:	6039      	str	r1, [r7, #0]
+  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+
+  /* Set Block Size for Card */
+  sdmmc_cmdinit.Argument         = (uint32_t)ReadAdd;
+ 800e10e:	683b      	ldr	r3, [r7, #0]
+ 800e110:	60bb      	str	r3, [r7, #8]
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_READ_MULT_BLOCK;
+ 800e112:	2312      	movs	r3, #18
+ 800e114:	60fb      	str	r3, [r7, #12]
+  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+ 800e116:	f44f 7380 	mov.w	r3, #256	; 0x100
+ 800e11a:	613b      	str	r3, [r7, #16]
+  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+ 800e11c:	2300      	movs	r3, #0
+ 800e11e:	617b      	str	r3, [r7, #20]
+  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+ 800e120:	f44f 5380 	mov.w	r3, #4096	; 0x1000
+ 800e124:	61bb      	str	r3, [r7, #24]
+  (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+ 800e126:	f107 0308 	add.w	r3, r7, #8
+ 800e12a:	4619      	mov	r1, r3
+ 800e12c:	6878      	ldr	r0, [r7, #4]
+ 800e12e:	f7ff ff2d 	bl	800df8c <SDMMC_SendCommand>
+
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_READ_MULT_BLOCK, SDMMC_CMDTIMEOUT);
+ 800e132:	f241 3288 	movw	r2, #5000	; 0x1388
+ 800e136:	2112      	movs	r1, #18
+ 800e138:	6878      	ldr	r0, [r7, #4]
+ 800e13a:	f000 fa19 	bl	800e570 <SDMMC_GetCmdResp1>
+ 800e13e:	61f8      	str	r0, [r7, #28]
+
+  return errorstate;
+ 800e140:	69fb      	ldr	r3, [r7, #28]
+}
+ 800e142:	4618      	mov	r0, r3
+ 800e144:	3720      	adds	r7, #32
+ 800e146:	46bd      	mov	sp, r7
+ 800e148:	bd80      	pop	{r7, pc}
+
+0800e14a <SDMMC_CmdWriteSingleBlock>:
+  * @brief  Send the Write Single Block command and check the response
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdWriteSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd)
+{
+ 800e14a:	b580      	push	{r7, lr}
+ 800e14c:	b088      	sub	sp, #32
+ 800e14e:	af00      	add	r7, sp, #0
+ 800e150:	6078      	str	r0, [r7, #4]
+ 800e152:	6039      	str	r1, [r7, #0]
+  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+
+  /* Set Block Size for Card */
+  sdmmc_cmdinit.Argument         = (uint32_t)WriteAdd;
+ 800e154:	683b      	ldr	r3, [r7, #0]
+ 800e156:	60bb      	str	r3, [r7, #8]
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_WRITE_SINGLE_BLOCK;
+ 800e158:	2318      	movs	r3, #24
+ 800e15a:	60fb      	str	r3, [r7, #12]
+  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+ 800e15c:	f44f 7380 	mov.w	r3, #256	; 0x100
+ 800e160:	613b      	str	r3, [r7, #16]
+  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+ 800e162:	2300      	movs	r3, #0
+ 800e164:	617b      	str	r3, [r7, #20]
+  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+ 800e166:	f44f 5380 	mov.w	r3, #4096	; 0x1000
+ 800e16a:	61bb      	str	r3, [r7, #24]
+  (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+ 800e16c:	f107 0308 	add.w	r3, r7, #8
+ 800e170:	4619      	mov	r1, r3
+ 800e172:	6878      	ldr	r0, [r7, #4]
+ 800e174:	f7ff ff0a 	bl	800df8c <SDMMC_SendCommand>
+
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_WRITE_SINGLE_BLOCK, SDMMC_CMDTIMEOUT);
+ 800e178:	f241 3288 	movw	r2, #5000	; 0x1388
+ 800e17c:	2118      	movs	r1, #24
+ 800e17e:	6878      	ldr	r0, [r7, #4]
+ 800e180:	f000 f9f6 	bl	800e570 <SDMMC_GetCmdResp1>
+ 800e184:	61f8      	str	r0, [r7, #28]
+
+  return errorstate;
+ 800e186:	69fb      	ldr	r3, [r7, #28]
+}
+ 800e188:	4618      	mov	r0, r3
+ 800e18a:	3720      	adds	r7, #32
+ 800e18c:	46bd      	mov	sp, r7
+ 800e18e:	bd80      	pop	{r7, pc}
+
+0800e190 <SDMMC_CmdWriteMultiBlock>:
+  * @brief  Send the Write Multi Block command and check the response
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdWriteMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd)
+{
+ 800e190:	b580      	push	{r7, lr}
+ 800e192:	b088      	sub	sp, #32
+ 800e194:	af00      	add	r7, sp, #0
+ 800e196:	6078      	str	r0, [r7, #4]
+ 800e198:	6039      	str	r1, [r7, #0]
+  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+
+  /* Set Block Size for Card */
+  sdmmc_cmdinit.Argument         = (uint32_t)WriteAdd;
+ 800e19a:	683b      	ldr	r3, [r7, #0]
+ 800e19c:	60bb      	str	r3, [r7, #8]
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_WRITE_MULT_BLOCK;
+ 800e19e:	2319      	movs	r3, #25
+ 800e1a0:	60fb      	str	r3, [r7, #12]
+  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+ 800e1a2:	f44f 7380 	mov.w	r3, #256	; 0x100
+ 800e1a6:	613b      	str	r3, [r7, #16]
+  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+ 800e1a8:	2300      	movs	r3, #0
+ 800e1aa:	617b      	str	r3, [r7, #20]
+  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+ 800e1ac:	f44f 5380 	mov.w	r3, #4096	; 0x1000
+ 800e1b0:	61bb      	str	r3, [r7, #24]
+  (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+ 800e1b2:	f107 0308 	add.w	r3, r7, #8
+ 800e1b6:	4619      	mov	r1, r3
+ 800e1b8:	6878      	ldr	r0, [r7, #4]
+ 800e1ba:	f7ff fee7 	bl	800df8c <SDMMC_SendCommand>
+
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_WRITE_MULT_BLOCK, SDMMC_CMDTIMEOUT);
+ 800e1be:	f241 3288 	movw	r2, #5000	; 0x1388
+ 800e1c2:	2119      	movs	r1, #25
+ 800e1c4:	6878      	ldr	r0, [r7, #4]
+ 800e1c6:	f000 f9d3 	bl	800e570 <SDMMC_GetCmdResp1>
+ 800e1ca:	61f8      	str	r0, [r7, #28]
+
+  return errorstate;
+ 800e1cc:	69fb      	ldr	r3, [r7, #28]
+}
+ 800e1ce:	4618      	mov	r0, r3
+ 800e1d0:	3720      	adds	r7, #32
+ 800e1d2:	46bd      	mov	sp, r7
+ 800e1d4:	bd80      	pop	{r7, pc}
+	...
+
+0800e1d8 <SDMMC_CmdStopTransfer>:
+  * @brief  Send the Stop Transfer command and check the response.
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdStopTransfer(SDMMC_TypeDef *SDMMCx)
+{
+ 800e1d8:	b580      	push	{r7, lr}
+ 800e1da:	b088      	sub	sp, #32
+ 800e1dc:	af00      	add	r7, sp, #0
+ 800e1de:	6078      	str	r0, [r7, #4]
+  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+
+  /* Send CMD12 STOP_TRANSMISSION  */
+  sdmmc_cmdinit.Argument         = 0U;
+ 800e1e0:	2300      	movs	r3, #0
+ 800e1e2:	60bb      	str	r3, [r7, #8]
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_STOP_TRANSMISSION;
+ 800e1e4:	230c      	movs	r3, #12
+ 800e1e6:	60fb      	str	r3, [r7, #12]
+  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+ 800e1e8:	f44f 7380 	mov.w	r3, #256	; 0x100
+ 800e1ec:	613b      	str	r3, [r7, #16]
+  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+ 800e1ee:	2300      	movs	r3, #0
+ 800e1f0:	617b      	str	r3, [r7, #20]
+  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+ 800e1f2:	f44f 5380 	mov.w	r3, #4096	; 0x1000
+ 800e1f6:	61bb      	str	r3, [r7, #24]
+
+  __SDMMC_CMDSTOP_ENABLE(SDMMCx);
+ 800e1f8:	687b      	ldr	r3, [r7, #4]
+ 800e1fa:	68db      	ldr	r3, [r3, #12]
+ 800e1fc:	f043 0280 	orr.w	r2, r3, #128	; 0x80
+ 800e200:	687b      	ldr	r3, [r7, #4]
+ 800e202:	60da      	str	r2, [r3, #12]
+  __SDMMC_CMDTRANS_DISABLE(SDMMCx);
+ 800e204:	687b      	ldr	r3, [r7, #4]
+ 800e206:	68db      	ldr	r3, [r3, #12]
+ 800e208:	f023 0240 	bic.w	r2, r3, #64	; 0x40
+ 800e20c:	687b      	ldr	r3, [r7, #4]
+ 800e20e:	60da      	str	r2, [r3, #12]
+
+  (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+ 800e210:	f107 0308 	add.w	r3, r7, #8
+ 800e214:	4619      	mov	r1, r3
+ 800e216:	6878      	ldr	r0, [r7, #4]
+ 800e218:	f7ff feb8 	bl	800df8c <SDMMC_SendCommand>
+
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_STOP_TRANSMISSION, SDMMC_STOPTRANSFERTIMEOUT);
+ 800e21c:	4a0b      	ldr	r2, [pc, #44]	; (800e24c <SDMMC_CmdStopTransfer+0x74>)
+ 800e21e:	210c      	movs	r1, #12
+ 800e220:	6878      	ldr	r0, [r7, #4]
+ 800e222:	f000 f9a5 	bl	800e570 <SDMMC_GetCmdResp1>
+ 800e226:	61f8      	str	r0, [r7, #28]
+
+  __SDMMC_CMDSTOP_DISABLE(SDMMCx);
+ 800e228:	687b      	ldr	r3, [r7, #4]
+ 800e22a:	68db      	ldr	r3, [r3, #12]
+ 800e22c:	f023 0280 	bic.w	r2, r3, #128	; 0x80
+ 800e230:	687b      	ldr	r3, [r7, #4]
+ 800e232:	60da      	str	r2, [r3, #12]
+
+  /* Ignore Address Out Of Range Error, Not relevant at end of memory */
+  if (errorstate == SDMMC_ERROR_ADDR_OUT_OF_RANGE)
+ 800e234:	69fb      	ldr	r3, [r7, #28]
+ 800e236:	f1b3 7f00 	cmp.w	r3, #33554432	; 0x2000000
+ 800e23a:	d101      	bne.n	800e240 <SDMMC_CmdStopTransfer+0x68>
+  {
+    errorstate = SDMMC_ERROR_NONE;
+ 800e23c:	2300      	movs	r3, #0
+ 800e23e:	61fb      	str	r3, [r7, #28]
+  }
+
+  return errorstate;
+ 800e240:	69fb      	ldr	r3, [r7, #28]
+}
+ 800e242:	4618      	mov	r0, r3
+ 800e244:	3720      	adds	r7, #32
+ 800e246:	46bd      	mov	sp, r7
+ 800e248:	bd80      	pop	{r7, pc}
+ 800e24a:	bf00      	nop
+ 800e24c:	05f5e100 	.word	0x05f5e100
+
+0800e250 <SDMMC_CmdSelDesel>:
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @param  addr: Address of the card to be selected
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdSelDesel(SDMMC_TypeDef *SDMMCx, uint32_t Addr)
+{
+ 800e250:	b580      	push	{r7, lr}
+ 800e252:	b088      	sub	sp, #32
+ 800e254:	af00      	add	r7, sp, #0
+ 800e256:	6078      	str	r0, [r7, #4]
+ 800e258:	6039      	str	r1, [r7, #0]
+  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+
+  /* Send CMD7 SDMMC_SEL_DESEL_CARD */
+  sdmmc_cmdinit.Argument         = (uint32_t)Addr;
+ 800e25a:	683b      	ldr	r3, [r7, #0]
+ 800e25c:	60bb      	str	r3, [r7, #8]
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SEL_DESEL_CARD;
+ 800e25e:	2307      	movs	r3, #7
+ 800e260:	60fb      	str	r3, [r7, #12]
+  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+ 800e262:	f44f 7380 	mov.w	r3, #256	; 0x100
+ 800e266:	613b      	str	r3, [r7, #16]
+  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+ 800e268:	2300      	movs	r3, #0
+ 800e26a:	617b      	str	r3, [r7, #20]
+  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+ 800e26c:	f44f 5380 	mov.w	r3, #4096	; 0x1000
+ 800e270:	61bb      	str	r3, [r7, #24]
+  (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+ 800e272:	f107 0308 	add.w	r3, r7, #8
+ 800e276:	4619      	mov	r1, r3
+ 800e278:	6878      	ldr	r0, [r7, #4]
+ 800e27a:	f7ff fe87 	bl	800df8c <SDMMC_SendCommand>
+
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SEL_DESEL_CARD, SDMMC_CMDTIMEOUT);
+ 800e27e:	f241 3288 	movw	r2, #5000	; 0x1388
+ 800e282:	2107      	movs	r1, #7
+ 800e284:	6878      	ldr	r0, [r7, #4]
+ 800e286:	f000 f973 	bl	800e570 <SDMMC_GetCmdResp1>
+ 800e28a:	61f8      	str	r0, [r7, #28]
+
+  return errorstate;
+ 800e28c:	69fb      	ldr	r3, [r7, #28]
+}
+ 800e28e:	4618      	mov	r0, r3
+ 800e290:	3720      	adds	r7, #32
+ 800e292:	46bd      	mov	sp, r7
+ 800e294:	bd80      	pop	{r7, pc}
+
+0800e296 <SDMMC_CmdGoIdleState>:
+  * @brief  Send the Go Idle State command and check the response.
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdGoIdleState(SDMMC_TypeDef *SDMMCx)
+{
+ 800e296:	b580      	push	{r7, lr}
+ 800e298:	b088      	sub	sp, #32
+ 800e29a:	af00      	add	r7, sp, #0
+ 800e29c:	6078      	str	r0, [r7, #4]
+  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+
+  sdmmc_cmdinit.Argument         = 0U;
+ 800e29e:	2300      	movs	r3, #0
+ 800e2a0:	60bb      	str	r3, [r7, #8]
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_GO_IDLE_STATE;
+ 800e2a2:	2300      	movs	r3, #0
+ 800e2a4:	60fb      	str	r3, [r7, #12]
+  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_NO;
+ 800e2a6:	2300      	movs	r3, #0
+ 800e2a8:	613b      	str	r3, [r7, #16]
+  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+ 800e2aa:	2300      	movs	r3, #0
+ 800e2ac:	617b      	str	r3, [r7, #20]
+  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+ 800e2ae:	f44f 5380 	mov.w	r3, #4096	; 0x1000
+ 800e2b2:	61bb      	str	r3, [r7, #24]
+  (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+ 800e2b4:	f107 0308 	add.w	r3, r7, #8
+ 800e2b8:	4619      	mov	r1, r3
+ 800e2ba:	6878      	ldr	r0, [r7, #4]
+ 800e2bc:	f7ff fe66 	bl	800df8c <SDMMC_SendCommand>
+
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdError(SDMMCx);
+ 800e2c0:	6878      	ldr	r0, [r7, #4]
+ 800e2c2:	f000 fb97 	bl	800e9f4 <SDMMC_GetCmdError>
+ 800e2c6:	61f8      	str	r0, [r7, #28]
+
+  return errorstate;
+ 800e2c8:	69fb      	ldr	r3, [r7, #28]
+}
+ 800e2ca:	4618      	mov	r0, r3
+ 800e2cc:	3720      	adds	r7, #32
+ 800e2ce:	46bd      	mov	sp, r7
+ 800e2d0:	bd80      	pop	{r7, pc}
+
+0800e2d2 <SDMMC_CmdOperCond>:
+  * @brief  Send the Operating Condition command and check the response.
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdOperCond(SDMMC_TypeDef *SDMMCx)
+{
+ 800e2d2:	b580      	push	{r7, lr}
+ 800e2d4:	b088      	sub	sp, #32
+ 800e2d6:	af00      	add	r7, sp, #0
+ 800e2d8:	6078      	str	r0, [r7, #4]
+  /* Send CMD8 to verify SD card interface operating condition */
+  /* Argument: - [31:12]: Reserved (shall be set to '0')
+  - [11:8]: Supply Voltage (VHS) 0x1 (Range: 2.7-3.6 V)
+  - [7:0]: Check Pattern (recommended 0xAA) */
+  /* CMD Response: R7 */
+  sdmmc_cmdinit.Argument         = SDMMC_CHECK_PATTERN;
+ 800e2da:	f44f 73d5 	mov.w	r3, #426	; 0x1aa
+ 800e2de:	60bb      	str	r3, [r7, #8]
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_HS_SEND_EXT_CSD;
+ 800e2e0:	2308      	movs	r3, #8
+ 800e2e2:	60fb      	str	r3, [r7, #12]
+  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+ 800e2e4:	f44f 7380 	mov.w	r3, #256	; 0x100
+ 800e2e8:	613b      	str	r3, [r7, #16]
+  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+ 800e2ea:	2300      	movs	r3, #0
+ 800e2ec:	617b      	str	r3, [r7, #20]
+  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+ 800e2ee:	f44f 5380 	mov.w	r3, #4096	; 0x1000
+ 800e2f2:	61bb      	str	r3, [r7, #24]
+  (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+ 800e2f4:	f107 0308 	add.w	r3, r7, #8
+ 800e2f8:	4619      	mov	r1, r3
+ 800e2fa:	6878      	ldr	r0, [r7, #4]
+ 800e2fc:	f7ff fe46 	bl	800df8c <SDMMC_SendCommand>
+
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp7(SDMMCx);
+ 800e300:	6878      	ldr	r0, [r7, #4]
+ 800e302:	f000 fb29 	bl	800e958 <SDMMC_GetCmdResp7>
+ 800e306:	61f8      	str	r0, [r7, #28]
+
+  return errorstate;
+ 800e308:	69fb      	ldr	r3, [r7, #28]
+}
+ 800e30a:	4618      	mov	r0, r3
+ 800e30c:	3720      	adds	r7, #32
+ 800e30e:	46bd      	mov	sp, r7
+ 800e310:	bd80      	pop	{r7, pc}
+
+0800e312 <SDMMC_CmdAppCommand>:
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @param  Argument: Command Argument
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdAppCommand(SDMMC_TypeDef *SDMMCx, uint32_t Argument)
+{
+ 800e312:	b580      	push	{r7, lr}
+ 800e314:	b088      	sub	sp, #32
+ 800e316:	af00      	add	r7, sp, #0
+ 800e318:	6078      	str	r0, [r7, #4]
+ 800e31a:	6039      	str	r1, [r7, #0]
+  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+
+  sdmmc_cmdinit.Argument         = (uint32_t)Argument;
+ 800e31c:	683b      	ldr	r3, [r7, #0]
+ 800e31e:	60bb      	str	r3, [r7, #8]
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_APP_CMD;
+ 800e320:	2337      	movs	r3, #55	; 0x37
+ 800e322:	60fb      	str	r3, [r7, #12]
+  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+ 800e324:	f44f 7380 	mov.w	r3, #256	; 0x100
+ 800e328:	613b      	str	r3, [r7, #16]
+  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+ 800e32a:	2300      	movs	r3, #0
+ 800e32c:	617b      	str	r3, [r7, #20]
+  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+ 800e32e:	f44f 5380 	mov.w	r3, #4096	; 0x1000
+ 800e332:	61bb      	str	r3, [r7, #24]
+  (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+ 800e334:	f107 0308 	add.w	r3, r7, #8
+ 800e338:	4619      	mov	r1, r3
+ 800e33a:	6878      	ldr	r0, [r7, #4]
+ 800e33c:	f7ff fe26 	bl	800df8c <SDMMC_SendCommand>
+
+  /* Check for error conditions */
+  /* If there is a HAL_ERROR, it is a MMC card, else
+  it is a SD card: SD card 2.0 (voltage range mismatch)
+     or SD card 1.x */
+  errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_APP_CMD, SDMMC_CMDTIMEOUT);
+ 800e340:	f241 3288 	movw	r2, #5000	; 0x1388
+ 800e344:	2137      	movs	r1, #55	; 0x37
+ 800e346:	6878      	ldr	r0, [r7, #4]
+ 800e348:	f000 f912 	bl	800e570 <SDMMC_GetCmdResp1>
+ 800e34c:	61f8      	str	r0, [r7, #28]
+
+  return errorstate;
+ 800e34e:	69fb      	ldr	r3, [r7, #28]
+}
+ 800e350:	4618      	mov	r0, r3
+ 800e352:	3720      	adds	r7, #32
+ 800e354:	46bd      	mov	sp, r7
+ 800e356:	bd80      	pop	{r7, pc}
+
+0800e358 <SDMMC_CmdAppOperCommand>:
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @param  Argument: Command Argument
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdAppOperCommand(SDMMC_TypeDef *SDMMCx, uint32_t Argument)
+{
+ 800e358:	b580      	push	{r7, lr}
+ 800e35a:	b088      	sub	sp, #32
+ 800e35c:	af00      	add	r7, sp, #0
+ 800e35e:	6078      	str	r0, [r7, #4]
+ 800e360:	6039      	str	r1, [r7, #0]
+  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+
+  sdmmc_cmdinit.Argument         = Argument;
+ 800e362:	683b      	ldr	r3, [r7, #0]
+ 800e364:	60bb      	str	r3, [r7, #8]
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SD_APP_OP_COND;
+ 800e366:	2329      	movs	r3, #41	; 0x29
+ 800e368:	60fb      	str	r3, [r7, #12]
+  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+ 800e36a:	f44f 7380 	mov.w	r3, #256	; 0x100
+ 800e36e:	613b      	str	r3, [r7, #16]
+  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+ 800e370:	2300      	movs	r3, #0
+ 800e372:	617b      	str	r3, [r7, #20]
+  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+ 800e374:	f44f 5380 	mov.w	r3, #4096	; 0x1000
+ 800e378:	61bb      	str	r3, [r7, #24]
+  (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+ 800e37a:	f107 0308 	add.w	r3, r7, #8
+ 800e37e:	4619      	mov	r1, r3
+ 800e380:	6878      	ldr	r0, [r7, #4]
+ 800e382:	f7ff fe03 	bl	800df8c <SDMMC_SendCommand>
+
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp3(SDMMCx);
+ 800e386:	6878      	ldr	r0, [r7, #4]
+ 800e388:	f000 fa2e 	bl	800e7e8 <SDMMC_GetCmdResp3>
+ 800e38c:	61f8      	str	r0, [r7, #28]
+
+  return errorstate;
+ 800e38e:	69fb      	ldr	r3, [r7, #28]
+}
+ 800e390:	4618      	mov	r0, r3
+ 800e392:	3720      	adds	r7, #32
+ 800e394:	46bd      	mov	sp, r7
+ 800e396:	bd80      	pop	{r7, pc}
+
+0800e398 <SDMMC_CmdBusWidth>:
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @param  BusWidth: BusWidth
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdBusWidth(SDMMC_TypeDef *SDMMCx, uint32_t BusWidth)
+{
+ 800e398:	b580      	push	{r7, lr}
+ 800e39a:	b088      	sub	sp, #32
+ 800e39c:	af00      	add	r7, sp, #0
+ 800e39e:	6078      	str	r0, [r7, #4]
+ 800e3a0:	6039      	str	r1, [r7, #0]
+  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+
+  sdmmc_cmdinit.Argument         = (uint32_t)BusWidth;
+ 800e3a2:	683b      	ldr	r3, [r7, #0]
+ 800e3a4:	60bb      	str	r3, [r7, #8]
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_APP_SD_SET_BUSWIDTH;
+ 800e3a6:	2306      	movs	r3, #6
+ 800e3a8:	60fb      	str	r3, [r7, #12]
+  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+ 800e3aa:	f44f 7380 	mov.w	r3, #256	; 0x100
+ 800e3ae:	613b      	str	r3, [r7, #16]
+  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+ 800e3b0:	2300      	movs	r3, #0
+ 800e3b2:	617b      	str	r3, [r7, #20]
+  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+ 800e3b4:	f44f 5380 	mov.w	r3, #4096	; 0x1000
+ 800e3b8:	61bb      	str	r3, [r7, #24]
+  (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+ 800e3ba:	f107 0308 	add.w	r3, r7, #8
+ 800e3be:	4619      	mov	r1, r3
+ 800e3c0:	6878      	ldr	r0, [r7, #4]
+ 800e3c2:	f7ff fde3 	bl	800df8c <SDMMC_SendCommand>
+
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_APP_SD_SET_BUSWIDTH, SDMMC_CMDTIMEOUT);
+ 800e3c6:	f241 3288 	movw	r2, #5000	; 0x1388
+ 800e3ca:	2106      	movs	r1, #6
+ 800e3cc:	6878      	ldr	r0, [r7, #4]
+ 800e3ce:	f000 f8cf 	bl	800e570 <SDMMC_GetCmdResp1>
+ 800e3d2:	61f8      	str	r0, [r7, #28]
+
+  return errorstate;
+ 800e3d4:	69fb      	ldr	r3, [r7, #28]
+}
+ 800e3d6:	4618      	mov	r0, r3
+ 800e3d8:	3720      	adds	r7, #32
+ 800e3da:	46bd      	mov	sp, r7
+ 800e3dc:	bd80      	pop	{r7, pc}
+
+0800e3de <SDMMC_CmdSendSCR>:
+  * @brief  Send the Send SCR command and check the response.
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdSendSCR(SDMMC_TypeDef *SDMMCx)
+{
+ 800e3de:	b580      	push	{r7, lr}
+ 800e3e0:	b088      	sub	sp, #32
+ 800e3e2:	af00      	add	r7, sp, #0
+ 800e3e4:	6078      	str	r0, [r7, #4]
+  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+
+  /* Send CMD51 SD_APP_SEND_SCR */
+  sdmmc_cmdinit.Argument         = 0U;
+ 800e3e6:	2300      	movs	r3, #0
+ 800e3e8:	60bb      	str	r3, [r7, #8]
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SD_APP_SEND_SCR;
+ 800e3ea:	2333      	movs	r3, #51	; 0x33
+ 800e3ec:	60fb      	str	r3, [r7, #12]
+  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+ 800e3ee:	f44f 7380 	mov.w	r3, #256	; 0x100
+ 800e3f2:	613b      	str	r3, [r7, #16]
+  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+ 800e3f4:	2300      	movs	r3, #0
+ 800e3f6:	617b      	str	r3, [r7, #20]
+  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+ 800e3f8:	f44f 5380 	mov.w	r3, #4096	; 0x1000
+ 800e3fc:	61bb      	str	r3, [r7, #24]
+  (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+ 800e3fe:	f107 0308 	add.w	r3, r7, #8
+ 800e402:	4619      	mov	r1, r3
+ 800e404:	6878      	ldr	r0, [r7, #4]
+ 800e406:	f7ff fdc1 	bl	800df8c <SDMMC_SendCommand>
+
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SD_APP_SEND_SCR, SDMMC_CMDTIMEOUT);
+ 800e40a:	f241 3288 	movw	r2, #5000	; 0x1388
+ 800e40e:	2133      	movs	r1, #51	; 0x33
+ 800e410:	6878      	ldr	r0, [r7, #4]
+ 800e412:	f000 f8ad 	bl	800e570 <SDMMC_GetCmdResp1>
+ 800e416:	61f8      	str	r0, [r7, #28]
+
+  return errorstate;
+ 800e418:	69fb      	ldr	r3, [r7, #28]
+}
+ 800e41a:	4618      	mov	r0, r3
+ 800e41c:	3720      	adds	r7, #32
+ 800e41e:	46bd      	mov	sp, r7
+ 800e420:	bd80      	pop	{r7, pc}
+
+0800e422 <SDMMC_CmdSendCID>:
+  * @brief  Send the Send CID command and check the response.
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdSendCID(SDMMC_TypeDef *SDMMCx)
+{
+ 800e422:	b580      	push	{r7, lr}
+ 800e424:	b088      	sub	sp, #32
+ 800e426:	af00      	add	r7, sp, #0
+ 800e428:	6078      	str	r0, [r7, #4]
+  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+
+  /* Send CMD2 ALL_SEND_CID */
+  sdmmc_cmdinit.Argument         = 0U;
+ 800e42a:	2300      	movs	r3, #0
+ 800e42c:	60bb      	str	r3, [r7, #8]
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_ALL_SEND_CID;
+ 800e42e:	2302      	movs	r3, #2
+ 800e430:	60fb      	str	r3, [r7, #12]
+  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_LONG;
+ 800e432:	f44f 7340 	mov.w	r3, #768	; 0x300
+ 800e436:	613b      	str	r3, [r7, #16]
+  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+ 800e438:	2300      	movs	r3, #0
+ 800e43a:	617b      	str	r3, [r7, #20]
+  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+ 800e43c:	f44f 5380 	mov.w	r3, #4096	; 0x1000
+ 800e440:	61bb      	str	r3, [r7, #24]
+  (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+ 800e442:	f107 0308 	add.w	r3, r7, #8
+ 800e446:	4619      	mov	r1, r3
+ 800e448:	6878      	ldr	r0, [r7, #4]
+ 800e44a:	f7ff fd9f 	bl	800df8c <SDMMC_SendCommand>
+
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp2(SDMMCx);
+ 800e44e:	6878      	ldr	r0, [r7, #4]
+ 800e450:	f000 f980 	bl	800e754 <SDMMC_GetCmdResp2>
+ 800e454:	61f8      	str	r0, [r7, #28]
+
+  return errorstate;
+ 800e456:	69fb      	ldr	r3, [r7, #28]
+}
+ 800e458:	4618      	mov	r0, r3
+ 800e45a:	3720      	adds	r7, #32
+ 800e45c:	46bd      	mov	sp, r7
+ 800e45e:	bd80      	pop	{r7, pc}
+
+0800e460 <SDMMC_CmdSendCSD>:
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @param  Argument: Command Argument
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdSendCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument)
+{
+ 800e460:	b580      	push	{r7, lr}
+ 800e462:	b088      	sub	sp, #32
+ 800e464:	af00      	add	r7, sp, #0
+ 800e466:	6078      	str	r0, [r7, #4]
+ 800e468:	6039      	str	r1, [r7, #0]
+  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+
+  /* Send CMD9 SEND_CSD */
+  sdmmc_cmdinit.Argument         = Argument;
+ 800e46a:	683b      	ldr	r3, [r7, #0]
+ 800e46c:	60bb      	str	r3, [r7, #8]
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SEND_CSD;
+ 800e46e:	2309      	movs	r3, #9
+ 800e470:	60fb      	str	r3, [r7, #12]
+  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_LONG;
+ 800e472:	f44f 7340 	mov.w	r3, #768	; 0x300
+ 800e476:	613b      	str	r3, [r7, #16]
+  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+ 800e478:	2300      	movs	r3, #0
+ 800e47a:	617b      	str	r3, [r7, #20]
+  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+ 800e47c:	f44f 5380 	mov.w	r3, #4096	; 0x1000
+ 800e480:	61bb      	str	r3, [r7, #24]
+  (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+ 800e482:	f107 0308 	add.w	r3, r7, #8
+ 800e486:	4619      	mov	r1, r3
+ 800e488:	6878      	ldr	r0, [r7, #4]
+ 800e48a:	f7ff fd7f 	bl	800df8c <SDMMC_SendCommand>
+
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp2(SDMMCx);
+ 800e48e:	6878      	ldr	r0, [r7, #4]
+ 800e490:	f000 f960 	bl	800e754 <SDMMC_GetCmdResp2>
+ 800e494:	61f8      	str	r0, [r7, #28]
+
+  return errorstate;
+ 800e496:	69fb      	ldr	r3, [r7, #28]
+}
+ 800e498:	4618      	mov	r0, r3
+ 800e49a:	3720      	adds	r7, #32
+ 800e49c:	46bd      	mov	sp, r7
+ 800e49e:	bd80      	pop	{r7, pc}
+
+0800e4a0 <SDMMC_CmdSetRelAdd>:
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @param  pRCA: Card RCA
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdSetRelAdd(SDMMC_TypeDef *SDMMCx, uint16_t *pRCA)
+{
+ 800e4a0:	b580      	push	{r7, lr}
+ 800e4a2:	b088      	sub	sp, #32
+ 800e4a4:	af00      	add	r7, sp, #0
+ 800e4a6:	6078      	str	r0, [r7, #4]
+ 800e4a8:	6039      	str	r1, [r7, #0]
+  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+
+  /* Send CMD3 SD_CMD_SET_REL_ADDR */
+  sdmmc_cmdinit.Argument         = 0U;
+ 800e4aa:	2300      	movs	r3, #0
+ 800e4ac:	60bb      	str	r3, [r7, #8]
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SET_REL_ADDR;
+ 800e4ae:	2303      	movs	r3, #3
+ 800e4b0:	60fb      	str	r3, [r7, #12]
+  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+ 800e4b2:	f44f 7380 	mov.w	r3, #256	; 0x100
+ 800e4b6:	613b      	str	r3, [r7, #16]
+  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+ 800e4b8:	2300      	movs	r3, #0
+ 800e4ba:	617b      	str	r3, [r7, #20]
+  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+ 800e4bc:	f44f 5380 	mov.w	r3, #4096	; 0x1000
+ 800e4c0:	61bb      	str	r3, [r7, #24]
+  (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+ 800e4c2:	f107 0308 	add.w	r3, r7, #8
+ 800e4c6:	4619      	mov	r1, r3
+ 800e4c8:	6878      	ldr	r0, [r7, #4]
+ 800e4ca:	f7ff fd5f 	bl	800df8c <SDMMC_SendCommand>
+
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp6(SDMMCx, SDMMC_CMD_SET_REL_ADDR, pRCA);
+ 800e4ce:	683a      	ldr	r2, [r7, #0]
+ 800e4d0:	2103      	movs	r1, #3
+ 800e4d2:	6878      	ldr	r0, [r7, #4]
+ 800e4d4:	f000 f9c8 	bl	800e868 <SDMMC_GetCmdResp6>
+ 800e4d8:	61f8      	str	r0, [r7, #28]
+
+  return errorstate;
+ 800e4da:	69fb      	ldr	r3, [r7, #28]
+}
+ 800e4dc:	4618      	mov	r0, r3
+ 800e4de:	3720      	adds	r7, #32
+ 800e4e0:	46bd      	mov	sp, r7
+ 800e4e2:	bd80      	pop	{r7, pc}
+
+0800e4e4 <SDMMC_CmdSendStatus>:
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @param  Argument: Command Argument
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdSendStatus(SDMMC_TypeDef *SDMMCx, uint32_t Argument)
+{
+ 800e4e4:	b580      	push	{r7, lr}
+ 800e4e6:	b088      	sub	sp, #32
+ 800e4e8:	af00      	add	r7, sp, #0
+ 800e4ea:	6078      	str	r0, [r7, #4]
+ 800e4ec:	6039      	str	r1, [r7, #0]
+  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+
+  sdmmc_cmdinit.Argument         = Argument;
+ 800e4ee:	683b      	ldr	r3, [r7, #0]
+ 800e4f0:	60bb      	str	r3, [r7, #8]
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SEND_STATUS;
+ 800e4f2:	230d      	movs	r3, #13
+ 800e4f4:	60fb      	str	r3, [r7, #12]
+  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+ 800e4f6:	f44f 7380 	mov.w	r3, #256	; 0x100
+ 800e4fa:	613b      	str	r3, [r7, #16]
+  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+ 800e4fc:	2300      	movs	r3, #0
+ 800e4fe:	617b      	str	r3, [r7, #20]
+  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+ 800e500:	f44f 5380 	mov.w	r3, #4096	; 0x1000
+ 800e504:	61bb      	str	r3, [r7, #24]
+  (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+ 800e506:	f107 0308 	add.w	r3, r7, #8
+ 800e50a:	4619      	mov	r1, r3
+ 800e50c:	6878      	ldr	r0, [r7, #4]
+ 800e50e:	f7ff fd3d 	bl	800df8c <SDMMC_SendCommand>
+
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SEND_STATUS, SDMMC_CMDTIMEOUT);
+ 800e512:	f241 3288 	movw	r2, #5000	; 0x1388
+ 800e516:	210d      	movs	r1, #13
+ 800e518:	6878      	ldr	r0, [r7, #4]
+ 800e51a:	f000 f829 	bl	800e570 <SDMMC_GetCmdResp1>
+ 800e51e:	61f8      	str	r0, [r7, #28]
+
+  return errorstate;
+ 800e520:	69fb      	ldr	r3, [r7, #28]
+}
+ 800e522:	4618      	mov	r0, r3
+ 800e524:	3720      	adds	r7, #32
+ 800e526:	46bd      	mov	sp, r7
+ 800e528:	bd80      	pop	{r7, pc}
+
+0800e52a <SDMMC_CmdStatusRegister>:
+  * @brief  Send the Status register command and check the response.
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdStatusRegister(SDMMC_TypeDef *SDMMCx)
+{
+ 800e52a:	b580      	push	{r7, lr}
+ 800e52c:	b088      	sub	sp, #32
+ 800e52e:	af00      	add	r7, sp, #0
+ 800e530:	6078      	str	r0, [r7, #4]
+  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+
+  sdmmc_cmdinit.Argument         = 0U;
+ 800e532:	2300      	movs	r3, #0
+ 800e534:	60bb      	str	r3, [r7, #8]
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SD_APP_STATUS;
+ 800e536:	230d      	movs	r3, #13
+ 800e538:	60fb      	str	r3, [r7, #12]
+  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+ 800e53a:	f44f 7380 	mov.w	r3, #256	; 0x100
+ 800e53e:	613b      	str	r3, [r7, #16]
+  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+ 800e540:	2300      	movs	r3, #0
+ 800e542:	617b      	str	r3, [r7, #20]
+  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+ 800e544:	f44f 5380 	mov.w	r3, #4096	; 0x1000
+ 800e548:	61bb      	str	r3, [r7, #24]
+  (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+ 800e54a:	f107 0308 	add.w	r3, r7, #8
+ 800e54e:	4619      	mov	r1, r3
+ 800e550:	6878      	ldr	r0, [r7, #4]
+ 800e552:	f7ff fd1b 	bl	800df8c <SDMMC_SendCommand>
+
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SD_APP_STATUS, SDMMC_CMDTIMEOUT);
+ 800e556:	f241 3288 	movw	r2, #5000	; 0x1388
+ 800e55a:	210d      	movs	r1, #13
+ 800e55c:	6878      	ldr	r0, [r7, #4]
+ 800e55e:	f000 f807 	bl	800e570 <SDMMC_GetCmdResp1>
+ 800e562:	61f8      	str	r0, [r7, #28]
+
+  return errorstate;
+ 800e564:	69fb      	ldr	r3, [r7, #28]
+}
+ 800e566:	4618      	mov	r0, r3
+ 800e568:	3720      	adds	r7, #32
+ 800e56a:	46bd      	mov	sp, r7
+ 800e56c:	bd80      	pop	{r7, pc}
+	...
+
+0800e570 <SDMMC_GetCmdResp1>:
+  * @param  hsd: SD handle
+  * @param  SD_CMD: The sent command index
+  * @retval SD Card error state
+  */
+uint32_t SDMMC_GetCmdResp1(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint32_t Timeout)
+{
+ 800e570:	b580      	push	{r7, lr}
+ 800e572:	b088      	sub	sp, #32
+ 800e574:	af00      	add	r7, sp, #0
+ 800e576:	60f8      	str	r0, [r7, #12]
+ 800e578:	460b      	mov	r3, r1
+ 800e57a:	607a      	str	r2, [r7, #4]
+ 800e57c:	72fb      	strb	r3, [r7, #11]
+  uint32_t response_r1;
+  uint32_t sta_reg;
+
+  /* 8 is the number of required instructions cycles for the below loop statement.
+  The Timeout is expressed in ms */
+  uint32_t count = Timeout * (SystemCoreClock / 8U / 1000U);
+ 800e57e:	4b70      	ldr	r3, [pc, #448]	; (800e740 <SDMMC_GetCmdResp1+0x1d0>)
+ 800e580:	681b      	ldr	r3, [r3, #0]
+ 800e582:	4a70      	ldr	r2, [pc, #448]	; (800e744 <SDMMC_GetCmdResp1+0x1d4>)
+ 800e584:	fba2 2303 	umull	r2, r3, r2, r3
+ 800e588:	0a5a      	lsrs	r2, r3, #9
+ 800e58a:	687b      	ldr	r3, [r7, #4]
+ 800e58c:	fb02 f303 	mul.w	r3, r2, r3
+ 800e590:	61fb      	str	r3, [r7, #28]
+
+  do
+  {
+    if (count-- == 0U)
+ 800e592:	69fb      	ldr	r3, [r7, #28]
+ 800e594:	1e5a      	subs	r2, r3, #1
+ 800e596:	61fa      	str	r2, [r7, #28]
+ 800e598:	2b00      	cmp	r3, #0
+ 800e59a:	d102      	bne.n	800e5a2 <SDMMC_GetCmdResp1+0x32>
+    {
+      return SDMMC_ERROR_TIMEOUT;
+ 800e59c:	f04f 4300 	mov.w	r3, #2147483648	; 0x80000000
+ 800e5a0:	e0c9      	b.n	800e736 <SDMMC_GetCmdResp1+0x1c6>
+    }
+    sta_reg = SDMMCx->STA;
+ 800e5a2:	68fb      	ldr	r3, [r7, #12]
+ 800e5a4:	6b5b      	ldr	r3, [r3, #52]	; 0x34
+ 800e5a6:	61bb      	str	r3, [r7, #24]
+  } while (((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT |
+ 800e5a8:	69ba      	ldr	r2, [r7, #24]
+ 800e5aa:	4b67      	ldr	r3, [pc, #412]	; (800e748 <SDMMC_GetCmdResp1+0x1d8>)
+ 800e5ac:	4013      	ands	r3, r2
+                        SDMMC_FLAG_BUSYD0END)) == 0U) || ((sta_reg & SDMMC_FLAG_CMDACT) != 0U));
+ 800e5ae:	2b00      	cmp	r3, #0
+ 800e5b0:	d0ef      	beq.n	800e592 <SDMMC_GetCmdResp1+0x22>
+ 800e5b2:	69bb      	ldr	r3, [r7, #24]
+ 800e5b4:	f403 5300 	and.w	r3, r3, #8192	; 0x2000
+ 800e5b8:	2b00      	cmp	r3, #0
+ 800e5ba:	d1ea      	bne.n	800e592 <SDMMC_GetCmdResp1+0x22>
+
+  if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT))
+ 800e5bc:	68fb      	ldr	r3, [r7, #12]
+ 800e5be:	6b5b      	ldr	r3, [r3, #52]	; 0x34
+ 800e5c0:	f003 0304 	and.w	r3, r3, #4
+ 800e5c4:	2b00      	cmp	r3, #0
+ 800e5c6:	d004      	beq.n	800e5d2 <SDMMC_GetCmdResp1+0x62>
+  {
+    __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT);
+ 800e5c8:	68fb      	ldr	r3, [r7, #12]
+ 800e5ca:	2204      	movs	r2, #4
+ 800e5cc:	639a      	str	r2, [r3, #56]	; 0x38
+
+    return SDMMC_ERROR_CMD_RSP_TIMEOUT;
+ 800e5ce:	2304      	movs	r3, #4
+ 800e5d0:	e0b1      	b.n	800e736 <SDMMC_GetCmdResp1+0x1c6>
+  }
+  else if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL))
+ 800e5d2:	68fb      	ldr	r3, [r7, #12]
+ 800e5d4:	6b5b      	ldr	r3, [r3, #52]	; 0x34
+ 800e5d6:	f003 0301 	and.w	r3, r3, #1
+ 800e5da:	2b00      	cmp	r3, #0
+ 800e5dc:	d004      	beq.n	800e5e8 <SDMMC_GetCmdResp1+0x78>
+  {
+    __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL);
+ 800e5de:	68fb      	ldr	r3, [r7, #12]
+ 800e5e0:	2201      	movs	r2, #1
+ 800e5e2:	639a      	str	r2, [r3, #56]	; 0x38
+
+    return SDMMC_ERROR_CMD_CRC_FAIL;
+ 800e5e4:	2301      	movs	r3, #1
+ 800e5e6:	e0a6      	b.n	800e736 <SDMMC_GetCmdResp1+0x1c6>
+  {
+    /* Nothing to do */
+  }
+
+  /* Clear all the static flags */
+  __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS);
+ 800e5e8:	68fb      	ldr	r3, [r7, #12]
+ 800e5ea:	4a58      	ldr	r2, [pc, #352]	; (800e74c <SDMMC_GetCmdResp1+0x1dc>)
+ 800e5ec:	639a      	str	r2, [r3, #56]	; 0x38
+
+  /* Check response received is of desired command */
+  if (SDMMC_GetCommandResponse(SDMMCx) != SD_CMD)
+ 800e5ee:	68f8      	ldr	r0, [r7, #12]
+ 800e5f0:	f7ff fcf6 	bl	800dfe0 <SDMMC_GetCommandResponse>
+ 800e5f4:	4603      	mov	r3, r0
+ 800e5f6:	461a      	mov	r2, r3
+ 800e5f8:	7afb      	ldrb	r3, [r7, #11]
+ 800e5fa:	4293      	cmp	r3, r2
+ 800e5fc:	d001      	beq.n	800e602 <SDMMC_GetCmdResp1+0x92>
+  {
+    return SDMMC_ERROR_CMD_CRC_FAIL;
+ 800e5fe:	2301      	movs	r3, #1
+ 800e600:	e099      	b.n	800e736 <SDMMC_GetCmdResp1+0x1c6>
+  }
+
+  /* We have received response, retrieve it for analysis  */
+  response_r1 = SDMMC_GetResponse(SDMMCx, SDMMC_RESP1);
+ 800e602:	2100      	movs	r1, #0
+ 800e604:	68f8      	ldr	r0, [r7, #12]
+ 800e606:	f7ff fcf8 	bl	800dffa <SDMMC_GetResponse>
+ 800e60a:	6178      	str	r0, [r7, #20]
+
+  if ((response_r1 & SDMMC_OCR_ERRORBITS) == SDMMC_ALLZERO)
+ 800e60c:	697a      	ldr	r2, [r7, #20]
+ 800e60e:	4b50      	ldr	r3, [pc, #320]	; (800e750 <SDMMC_GetCmdResp1+0x1e0>)
+ 800e610:	4013      	ands	r3, r2
+ 800e612:	2b00      	cmp	r3, #0
+ 800e614:	d101      	bne.n	800e61a <SDMMC_GetCmdResp1+0xaa>
+  {
+    return SDMMC_ERROR_NONE;
+ 800e616:	2300      	movs	r3, #0
+ 800e618:	e08d      	b.n	800e736 <SDMMC_GetCmdResp1+0x1c6>
+  }
+  else if ((response_r1 & SDMMC_OCR_ADDR_OUT_OF_RANGE) == SDMMC_OCR_ADDR_OUT_OF_RANGE)
+ 800e61a:	697b      	ldr	r3, [r7, #20]
+ 800e61c:	2b00      	cmp	r3, #0
+ 800e61e:	da02      	bge.n	800e626 <SDMMC_GetCmdResp1+0xb6>
+  {
+    return SDMMC_ERROR_ADDR_OUT_OF_RANGE;
+ 800e620:	f04f 7300 	mov.w	r3, #33554432	; 0x2000000
+ 800e624:	e087      	b.n	800e736 <SDMMC_GetCmdResp1+0x1c6>
+  }
+  else if ((response_r1 & SDMMC_OCR_ADDR_MISALIGNED) == SDMMC_OCR_ADDR_MISALIGNED)
+ 800e626:	697b      	ldr	r3, [r7, #20]
+ 800e628:	f003 4380 	and.w	r3, r3, #1073741824	; 0x40000000
+ 800e62c:	2b00      	cmp	r3, #0
+ 800e62e:	d001      	beq.n	800e634 <SDMMC_GetCmdResp1+0xc4>
+  {
+    return SDMMC_ERROR_ADDR_MISALIGNED;
+ 800e630:	2340      	movs	r3, #64	; 0x40
+ 800e632:	e080      	b.n	800e736 <SDMMC_GetCmdResp1+0x1c6>
+  }
+  else if ((response_r1 & SDMMC_OCR_BLOCK_LEN_ERR) == SDMMC_OCR_BLOCK_LEN_ERR)
+ 800e634:	697b      	ldr	r3, [r7, #20]
+ 800e636:	f003 5300 	and.w	r3, r3, #536870912	; 0x20000000
+ 800e63a:	2b00      	cmp	r3, #0
+ 800e63c:	d001      	beq.n	800e642 <SDMMC_GetCmdResp1+0xd2>
+  {
+    return SDMMC_ERROR_BLOCK_LEN_ERR;
+ 800e63e:	2380      	movs	r3, #128	; 0x80
+ 800e640:	e079      	b.n	800e736 <SDMMC_GetCmdResp1+0x1c6>
+  }
+  else if ((response_r1 & SDMMC_OCR_ERASE_SEQ_ERR) == SDMMC_OCR_ERASE_SEQ_ERR)
+ 800e642:	697b      	ldr	r3, [r7, #20]
+ 800e644:	f003 5380 	and.w	r3, r3, #268435456	; 0x10000000
+ 800e648:	2b00      	cmp	r3, #0
+ 800e64a:	d002      	beq.n	800e652 <SDMMC_GetCmdResp1+0xe2>
+  {
+    return SDMMC_ERROR_ERASE_SEQ_ERR;
+ 800e64c:	f44f 7380 	mov.w	r3, #256	; 0x100
+ 800e650:	e071      	b.n	800e736 <SDMMC_GetCmdResp1+0x1c6>
+  }
+  else if ((response_r1 & SDMMC_OCR_BAD_ERASE_PARAM) == SDMMC_OCR_BAD_ERASE_PARAM)
+ 800e652:	697b      	ldr	r3, [r7, #20]
+ 800e654:	f003 6300 	and.w	r3, r3, #134217728	; 0x8000000
+ 800e658:	2b00      	cmp	r3, #0
+ 800e65a:	d002      	beq.n	800e662 <SDMMC_GetCmdResp1+0xf2>
+  {
+    return SDMMC_ERROR_BAD_ERASE_PARAM;
+ 800e65c:	f44f 7300 	mov.w	r3, #512	; 0x200
+ 800e660:	e069      	b.n	800e736 <SDMMC_GetCmdResp1+0x1c6>
+  }
+  else if ((response_r1 & SDMMC_OCR_WRITE_PROT_VIOLATION) == SDMMC_OCR_WRITE_PROT_VIOLATION)
+ 800e662:	697b      	ldr	r3, [r7, #20]
+ 800e664:	f003 6380 	and.w	r3, r3, #67108864	; 0x4000000
+ 800e668:	2b00      	cmp	r3, #0
+ 800e66a:	d002      	beq.n	800e672 <SDMMC_GetCmdResp1+0x102>
+  {
+    return SDMMC_ERROR_WRITE_PROT_VIOLATION;
+ 800e66c:	f44f 6380 	mov.w	r3, #1024	; 0x400
+ 800e670:	e061      	b.n	800e736 <SDMMC_GetCmdResp1+0x1c6>
+  }
+  else if ((response_r1 & SDMMC_OCR_LOCK_UNLOCK_FAILED) == SDMMC_OCR_LOCK_UNLOCK_FAILED)
+ 800e672:	697b      	ldr	r3, [r7, #20]
+ 800e674:	f003 7380 	and.w	r3, r3, #16777216	; 0x1000000
+ 800e678:	2b00      	cmp	r3, #0
+ 800e67a:	d002      	beq.n	800e682 <SDMMC_GetCmdResp1+0x112>
+  {
+    return SDMMC_ERROR_LOCK_UNLOCK_FAILED;
+ 800e67c:	f44f 6300 	mov.w	r3, #2048	; 0x800
+ 800e680:	e059      	b.n	800e736 <SDMMC_GetCmdResp1+0x1c6>
+  }
+  else if ((response_r1 & SDMMC_OCR_COM_CRC_FAILED) == SDMMC_OCR_COM_CRC_FAILED)
+ 800e682:	697b      	ldr	r3, [r7, #20]
+ 800e684:	f403 0300 	and.w	r3, r3, #8388608	; 0x800000
+ 800e688:	2b00      	cmp	r3, #0
+ 800e68a:	d002      	beq.n	800e692 <SDMMC_GetCmdResp1+0x122>
+  {
+    return SDMMC_ERROR_COM_CRC_FAILED;
+ 800e68c:	f44f 5380 	mov.w	r3, #4096	; 0x1000
+ 800e690:	e051      	b.n	800e736 <SDMMC_GetCmdResp1+0x1c6>
+  }
+  else if ((response_r1 & SDMMC_OCR_ILLEGAL_CMD) == SDMMC_OCR_ILLEGAL_CMD)
+ 800e692:	697b      	ldr	r3, [r7, #20]
+ 800e694:	f403 0380 	and.w	r3, r3, #4194304	; 0x400000
+ 800e698:	2b00      	cmp	r3, #0
+ 800e69a:	d002      	beq.n	800e6a2 <SDMMC_GetCmdResp1+0x132>
+  {
+    return SDMMC_ERROR_ILLEGAL_CMD;
+ 800e69c:	f44f 5300 	mov.w	r3, #8192	; 0x2000
+ 800e6a0:	e049      	b.n	800e736 <SDMMC_GetCmdResp1+0x1c6>
+  }
+  else if ((response_r1 & SDMMC_OCR_CARD_ECC_FAILED) == SDMMC_OCR_CARD_ECC_FAILED)
+ 800e6a2:	697b      	ldr	r3, [r7, #20]
+ 800e6a4:	f403 1300 	and.w	r3, r3, #2097152	; 0x200000
+ 800e6a8:	2b00      	cmp	r3, #0
+ 800e6aa:	d002      	beq.n	800e6b2 <SDMMC_GetCmdResp1+0x142>
+  {
+    return SDMMC_ERROR_CARD_ECC_FAILED;
+ 800e6ac:	f44f 4380 	mov.w	r3, #16384	; 0x4000
+ 800e6b0:	e041      	b.n	800e736 <SDMMC_GetCmdResp1+0x1c6>
+  }
+  else if ((response_r1 & SDMMC_OCR_CC_ERROR) == SDMMC_OCR_CC_ERROR)
+ 800e6b2:	697b      	ldr	r3, [r7, #20]
+ 800e6b4:	f403 1380 	and.w	r3, r3, #1048576	; 0x100000
+ 800e6b8:	2b00      	cmp	r3, #0
+ 800e6ba:	d002      	beq.n	800e6c2 <SDMMC_GetCmdResp1+0x152>
+  {
+    return SDMMC_ERROR_CC_ERR;
+ 800e6bc:	f44f 4300 	mov.w	r3, #32768	; 0x8000
+ 800e6c0:	e039      	b.n	800e736 <SDMMC_GetCmdResp1+0x1c6>
+  }
+  else if ((response_r1 & SDMMC_OCR_STREAM_READ_UNDERRUN) == SDMMC_OCR_STREAM_READ_UNDERRUN)
+ 800e6c2:	697b      	ldr	r3, [r7, #20]
+ 800e6c4:	f403 2380 	and.w	r3, r3, #262144	; 0x40000
+ 800e6c8:	2b00      	cmp	r3, #0
+ 800e6ca:	d002      	beq.n	800e6d2 <SDMMC_GetCmdResp1+0x162>
+  {
+    return SDMMC_ERROR_STREAM_READ_UNDERRUN;
+ 800e6cc:	f44f 3300 	mov.w	r3, #131072	; 0x20000
+ 800e6d0:	e031      	b.n	800e736 <SDMMC_GetCmdResp1+0x1c6>
+  }
+  else if ((response_r1 & SDMMC_OCR_STREAM_WRITE_OVERRUN) == SDMMC_OCR_STREAM_WRITE_OVERRUN)
+ 800e6d2:	697b      	ldr	r3, [r7, #20]
+ 800e6d4:	f403 3300 	and.w	r3, r3, #131072	; 0x20000
+ 800e6d8:	2b00      	cmp	r3, #0
+ 800e6da:	d002      	beq.n	800e6e2 <SDMMC_GetCmdResp1+0x172>
+  {
+    return SDMMC_ERROR_STREAM_WRITE_OVERRUN;
+ 800e6dc:	f44f 2380 	mov.w	r3, #262144	; 0x40000
+ 800e6e0:	e029      	b.n	800e736 <SDMMC_GetCmdResp1+0x1c6>
+  }
+  else if ((response_r1 & SDMMC_OCR_CID_CSD_OVERWRITE) == SDMMC_OCR_CID_CSD_OVERWRITE)
+ 800e6e2:	697b      	ldr	r3, [r7, #20]
+ 800e6e4:	f403 3380 	and.w	r3, r3, #65536	; 0x10000
+ 800e6e8:	2b00      	cmp	r3, #0
+ 800e6ea:	d002      	beq.n	800e6f2 <SDMMC_GetCmdResp1+0x182>
+  {
+    return SDMMC_ERROR_CID_CSD_OVERWRITE;
+ 800e6ec:	f44f 2300 	mov.w	r3, #524288	; 0x80000
+ 800e6f0:	e021      	b.n	800e736 <SDMMC_GetCmdResp1+0x1c6>
+  }
+  else if ((response_r1 & SDMMC_OCR_WP_ERASE_SKIP) == SDMMC_OCR_WP_ERASE_SKIP)
+ 800e6f2:	697b      	ldr	r3, [r7, #20]
+ 800e6f4:	f403 4300 	and.w	r3, r3, #32768	; 0x8000
+ 800e6f8:	2b00      	cmp	r3, #0
+ 800e6fa:	d002      	beq.n	800e702 <SDMMC_GetCmdResp1+0x192>
+  {
+    return SDMMC_ERROR_WP_ERASE_SKIP;
+ 800e6fc:	f44f 1380 	mov.w	r3, #1048576	; 0x100000
+ 800e700:	e019      	b.n	800e736 <SDMMC_GetCmdResp1+0x1c6>
+  }
+  else if ((response_r1 & SDMMC_OCR_CARD_ECC_DISABLED) == SDMMC_OCR_CARD_ECC_DISABLED)
+ 800e702:	697b      	ldr	r3, [r7, #20]
+ 800e704:	f403 4380 	and.w	r3, r3, #16384	; 0x4000
+ 800e708:	2b00      	cmp	r3, #0
+ 800e70a:	d002      	beq.n	800e712 <SDMMC_GetCmdResp1+0x1a2>
+  {
+    return SDMMC_ERROR_CARD_ECC_DISABLED;
+ 800e70c:	f44f 1300 	mov.w	r3, #2097152	; 0x200000
+ 800e710:	e011      	b.n	800e736 <SDMMC_GetCmdResp1+0x1c6>
+  }
+  else if ((response_r1 & SDMMC_OCR_ERASE_RESET) == SDMMC_OCR_ERASE_RESET)
+ 800e712:	697b      	ldr	r3, [r7, #20]
+ 800e714:	f403 5300 	and.w	r3, r3, #8192	; 0x2000
+ 800e718:	2b00      	cmp	r3, #0
+ 800e71a:	d002      	beq.n	800e722 <SDMMC_GetCmdResp1+0x1b2>
+  {
+    return SDMMC_ERROR_ERASE_RESET;
+ 800e71c:	f44f 0380 	mov.w	r3, #4194304	; 0x400000
+ 800e720:	e009      	b.n	800e736 <SDMMC_GetCmdResp1+0x1c6>
+  }
+  else if ((response_r1 & SDMMC_OCR_AKE_SEQ_ERROR) == SDMMC_OCR_AKE_SEQ_ERROR)
+ 800e722:	697b      	ldr	r3, [r7, #20]
+ 800e724:	f003 0308 	and.w	r3, r3, #8
+ 800e728:	2b00      	cmp	r3, #0
+ 800e72a:	d002      	beq.n	800e732 <SDMMC_GetCmdResp1+0x1c2>
+  {
+    return SDMMC_ERROR_AKE_SEQ_ERR;
+ 800e72c:	f44f 0300 	mov.w	r3, #8388608	; 0x800000
+ 800e730:	e001      	b.n	800e736 <SDMMC_GetCmdResp1+0x1c6>
+  }
+  else
+  {
+    return SDMMC_ERROR_GENERAL_UNKNOWN_ERR;
+ 800e732:	f44f 3380 	mov.w	r3, #65536	; 0x10000
+  }
+}
+ 800e736:	4618      	mov	r0, r3
+ 800e738:	3720      	adds	r7, #32
+ 800e73a:	46bd      	mov	sp, r7
+ 800e73c:	bd80      	pop	{r7, pc}
+ 800e73e:	bf00      	nop
+ 800e740:	24000014 	.word	0x24000014
+ 800e744:	10624dd3 	.word	0x10624dd3
+ 800e748:	00200045 	.word	0x00200045
+ 800e74c:	002000c5 	.word	0x002000c5
+ 800e750:	fdffe008 	.word	0xfdffe008
+
+0800e754 <SDMMC_GetCmdResp2>:
+  * @brief  Checks for error conditions for R2 (CID or CSD) response.
+  * @param  hsd: SD handle
+  * @retval SD Card error state
+  */
+uint32_t SDMMC_GetCmdResp2(SDMMC_TypeDef *SDMMCx)
+{
+ 800e754:	b480      	push	{r7}
+ 800e756:	b085      	sub	sp, #20
+ 800e758:	af00      	add	r7, sp, #0
+ 800e75a:	6078      	str	r0, [r7, #4]
+  uint32_t sta_reg;
+  /* 8 is the number of required instructions cycles for the below loop statement.
+  The SDMMC_CMDTIMEOUT is expressed in ms */
+  uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U / 1000U);
+ 800e75c:	4b1f      	ldr	r3, [pc, #124]	; (800e7dc <SDMMC_GetCmdResp2+0x88>)
+ 800e75e:	681b      	ldr	r3, [r3, #0]
+ 800e760:	4a1f      	ldr	r2, [pc, #124]	; (800e7e0 <SDMMC_GetCmdResp2+0x8c>)
+ 800e762:	fba2 2303 	umull	r2, r3, r2, r3
+ 800e766:	0a5b      	lsrs	r3, r3, #9
+ 800e768:	f241 3288 	movw	r2, #5000	; 0x1388
+ 800e76c:	fb02 f303 	mul.w	r3, r2, r3
+ 800e770:	60fb      	str	r3, [r7, #12]
+
+  do
+  {
+    if (count-- == 0U)
+ 800e772:	68fb      	ldr	r3, [r7, #12]
+ 800e774:	1e5a      	subs	r2, r3, #1
+ 800e776:	60fa      	str	r2, [r7, #12]
+ 800e778:	2b00      	cmp	r3, #0
+ 800e77a:	d102      	bne.n	800e782 <SDMMC_GetCmdResp2+0x2e>
+    {
+      return SDMMC_ERROR_TIMEOUT;
+ 800e77c:	f04f 4300 	mov.w	r3, #2147483648	; 0x80000000
+ 800e780:	e026      	b.n	800e7d0 <SDMMC_GetCmdResp2+0x7c>
+    }
+    sta_reg = SDMMCx->STA;
+ 800e782:	687b      	ldr	r3, [r7, #4]
+ 800e784:	6b5b      	ldr	r3, [r3, #52]	; 0x34
+ 800e786:	60bb      	str	r3, [r7, #8]
+  } while (((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) ||
+ 800e788:	68bb      	ldr	r3, [r7, #8]
+ 800e78a:	f003 0345 	and.w	r3, r3, #69	; 0x45
+ 800e78e:	2b00      	cmp	r3, #0
+ 800e790:	d0ef      	beq.n	800e772 <SDMMC_GetCmdResp2+0x1e>
+           ((sta_reg & SDMMC_FLAG_CMDACT) != 0U));
+ 800e792:	68bb      	ldr	r3, [r7, #8]
+ 800e794:	f403 5300 	and.w	r3, r3, #8192	; 0x2000
+  } while (((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) ||
+ 800e798:	2b00      	cmp	r3, #0
+ 800e79a:	d1ea      	bne.n	800e772 <SDMMC_GetCmdResp2+0x1e>
+
+  if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT))
+ 800e79c:	687b      	ldr	r3, [r7, #4]
+ 800e79e:	6b5b      	ldr	r3, [r3, #52]	; 0x34
+ 800e7a0:	f003 0304 	and.w	r3, r3, #4
+ 800e7a4:	2b00      	cmp	r3, #0
+ 800e7a6:	d004      	beq.n	800e7b2 <SDMMC_GetCmdResp2+0x5e>
+  {
+    __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT);
+ 800e7a8:	687b      	ldr	r3, [r7, #4]
+ 800e7aa:	2204      	movs	r2, #4
+ 800e7ac:	639a      	str	r2, [r3, #56]	; 0x38
+
+    return SDMMC_ERROR_CMD_RSP_TIMEOUT;
+ 800e7ae:	2304      	movs	r3, #4
+ 800e7b0:	e00e      	b.n	800e7d0 <SDMMC_GetCmdResp2+0x7c>
+  }
+  else if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL))
+ 800e7b2:	687b      	ldr	r3, [r7, #4]
+ 800e7b4:	6b5b      	ldr	r3, [r3, #52]	; 0x34
+ 800e7b6:	f003 0301 	and.w	r3, r3, #1
+ 800e7ba:	2b00      	cmp	r3, #0
+ 800e7bc:	d004      	beq.n	800e7c8 <SDMMC_GetCmdResp2+0x74>
+  {
+    __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL);
+ 800e7be:	687b      	ldr	r3, [r7, #4]
+ 800e7c0:	2201      	movs	r2, #1
+ 800e7c2:	639a      	str	r2, [r3, #56]	; 0x38
+
+    return SDMMC_ERROR_CMD_CRC_FAIL;
+ 800e7c4:	2301      	movs	r3, #1
+ 800e7c6:	e003      	b.n	800e7d0 <SDMMC_GetCmdResp2+0x7c>
+  }
+  else
+  {
+    /* No error flag set */
+    /* Clear all the static flags */
+    __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS);
+ 800e7c8:	687b      	ldr	r3, [r7, #4]
+ 800e7ca:	4a06      	ldr	r2, [pc, #24]	; (800e7e4 <SDMMC_GetCmdResp2+0x90>)
+ 800e7cc:	639a      	str	r2, [r3, #56]	; 0x38
+  }
+
+  return SDMMC_ERROR_NONE;
+ 800e7ce:	2300      	movs	r3, #0
+}
+ 800e7d0:	4618      	mov	r0, r3
+ 800e7d2:	3714      	adds	r7, #20
+ 800e7d4:	46bd      	mov	sp, r7
+ 800e7d6:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 800e7da:	4770      	bx	lr
+ 800e7dc:	24000014 	.word	0x24000014
+ 800e7e0:	10624dd3 	.word	0x10624dd3
+ 800e7e4:	002000c5 	.word	0x002000c5
+
+0800e7e8 <SDMMC_GetCmdResp3>:
+  * @brief  Checks for error conditions for R3 (OCR) response.
+  * @param  hsd: SD handle
+  * @retval SD Card error state
+  */
+uint32_t SDMMC_GetCmdResp3(SDMMC_TypeDef *SDMMCx)
+{
+ 800e7e8:	b480      	push	{r7}
+ 800e7ea:	b085      	sub	sp, #20
+ 800e7ec:	af00      	add	r7, sp, #0
+ 800e7ee:	6078      	str	r0, [r7, #4]
+  uint32_t sta_reg;
+  /* 8 is the number of required instructions cycles for the below loop statement.
+  The SDMMC_CMDTIMEOUT is expressed in ms */
+  uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U / 1000U);
+ 800e7f0:	4b1a      	ldr	r3, [pc, #104]	; (800e85c <SDMMC_GetCmdResp3+0x74>)
+ 800e7f2:	681b      	ldr	r3, [r3, #0]
+ 800e7f4:	4a1a      	ldr	r2, [pc, #104]	; (800e860 <SDMMC_GetCmdResp3+0x78>)
+ 800e7f6:	fba2 2303 	umull	r2, r3, r2, r3
+ 800e7fa:	0a5b      	lsrs	r3, r3, #9
+ 800e7fc:	f241 3288 	movw	r2, #5000	; 0x1388
+ 800e800:	fb02 f303 	mul.w	r3, r2, r3
+ 800e804:	60fb      	str	r3, [r7, #12]
+
+  do
+  {
+    if (count-- == 0U)
+ 800e806:	68fb      	ldr	r3, [r7, #12]
+ 800e808:	1e5a      	subs	r2, r3, #1
+ 800e80a:	60fa      	str	r2, [r7, #12]
+ 800e80c:	2b00      	cmp	r3, #0
+ 800e80e:	d102      	bne.n	800e816 <SDMMC_GetCmdResp3+0x2e>
+    {
+      return SDMMC_ERROR_TIMEOUT;
+ 800e810:	f04f 4300 	mov.w	r3, #2147483648	; 0x80000000
+ 800e814:	e01b      	b.n	800e84e <SDMMC_GetCmdResp3+0x66>
+    }
+    sta_reg = SDMMCx->STA;
+ 800e816:	687b      	ldr	r3, [r7, #4]
+ 800e818:	6b5b      	ldr	r3, [r3, #52]	; 0x34
+ 800e81a:	60bb      	str	r3, [r7, #8]
+  } while (((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) ||
+ 800e81c:	68bb      	ldr	r3, [r7, #8]
+ 800e81e:	f003 0345 	and.w	r3, r3, #69	; 0x45
+ 800e822:	2b00      	cmp	r3, #0
+ 800e824:	d0ef      	beq.n	800e806 <SDMMC_GetCmdResp3+0x1e>
+           ((sta_reg & SDMMC_FLAG_CMDACT) != 0U));
+ 800e826:	68bb      	ldr	r3, [r7, #8]
+ 800e828:	f403 5300 	and.w	r3, r3, #8192	; 0x2000
+  } while (((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) ||
+ 800e82c:	2b00      	cmp	r3, #0
+ 800e82e:	d1ea      	bne.n	800e806 <SDMMC_GetCmdResp3+0x1e>
+
+  if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT))
+ 800e830:	687b      	ldr	r3, [r7, #4]
+ 800e832:	6b5b      	ldr	r3, [r3, #52]	; 0x34
+ 800e834:	f003 0304 	and.w	r3, r3, #4
+ 800e838:	2b00      	cmp	r3, #0
+ 800e83a:	d004      	beq.n	800e846 <SDMMC_GetCmdResp3+0x5e>
+  {
+    __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT);
+ 800e83c:	687b      	ldr	r3, [r7, #4]
+ 800e83e:	2204      	movs	r2, #4
+ 800e840:	639a      	str	r2, [r3, #56]	; 0x38
+
+    return SDMMC_ERROR_CMD_RSP_TIMEOUT;
+ 800e842:	2304      	movs	r3, #4
+ 800e844:	e003      	b.n	800e84e <SDMMC_GetCmdResp3+0x66>
+  }
+  else
+  {
+    /* Clear all the static flags */
+    __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS);
+ 800e846:	687b      	ldr	r3, [r7, #4]
+ 800e848:	4a06      	ldr	r2, [pc, #24]	; (800e864 <SDMMC_GetCmdResp3+0x7c>)
+ 800e84a:	639a      	str	r2, [r3, #56]	; 0x38
+  }
+
+  return SDMMC_ERROR_NONE;
+ 800e84c:	2300      	movs	r3, #0
+}
+ 800e84e:	4618      	mov	r0, r3
+ 800e850:	3714      	adds	r7, #20
+ 800e852:	46bd      	mov	sp, r7
+ 800e854:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 800e858:	4770      	bx	lr
+ 800e85a:	bf00      	nop
+ 800e85c:	24000014 	.word	0x24000014
+ 800e860:	10624dd3 	.word	0x10624dd3
+ 800e864:	002000c5 	.word	0x002000c5
+
+0800e868 <SDMMC_GetCmdResp6>:
+  * @param  pRCA: Pointer to the variable that will contain the SD card relative
+  *         address RCA
+  * @retval SD Card error state
+  */
+uint32_t SDMMC_GetCmdResp6(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint16_t *pRCA)
+{
+ 800e868:	b580      	push	{r7, lr}
+ 800e86a:	b088      	sub	sp, #32
+ 800e86c:	af00      	add	r7, sp, #0
+ 800e86e:	60f8      	str	r0, [r7, #12]
+ 800e870:	460b      	mov	r3, r1
+ 800e872:	607a      	str	r2, [r7, #4]
+ 800e874:	72fb      	strb	r3, [r7, #11]
+  uint32_t response_r1;
+  uint32_t sta_reg;
+
+  /* 8 is the number of required instructions cycles for the below loop statement.
+  The SDMMC_CMDTIMEOUT is expressed in ms */
+  uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U / 1000U);
+ 800e876:	4b35      	ldr	r3, [pc, #212]	; (800e94c <SDMMC_GetCmdResp6+0xe4>)
+ 800e878:	681b      	ldr	r3, [r3, #0]
+ 800e87a:	4a35      	ldr	r2, [pc, #212]	; (800e950 <SDMMC_GetCmdResp6+0xe8>)
+ 800e87c:	fba2 2303 	umull	r2, r3, r2, r3
+ 800e880:	0a5b      	lsrs	r3, r3, #9
+ 800e882:	f241 3288 	movw	r2, #5000	; 0x1388
+ 800e886:	fb02 f303 	mul.w	r3, r2, r3
+ 800e88a:	61fb      	str	r3, [r7, #28]
+
+  do
+  {
+    if (count-- == 0U)
+ 800e88c:	69fb      	ldr	r3, [r7, #28]
+ 800e88e:	1e5a      	subs	r2, r3, #1
+ 800e890:	61fa      	str	r2, [r7, #28]
+ 800e892:	2b00      	cmp	r3, #0
+ 800e894:	d102      	bne.n	800e89c <SDMMC_GetCmdResp6+0x34>
+    {
+      return SDMMC_ERROR_TIMEOUT;
+ 800e896:	f04f 4300 	mov.w	r3, #2147483648	; 0x80000000
+ 800e89a:	e052      	b.n	800e942 <SDMMC_GetCmdResp6+0xda>
+    }
+    sta_reg = SDMMCx->STA;
+ 800e89c:	68fb      	ldr	r3, [r7, #12]
+ 800e89e:	6b5b      	ldr	r3, [r3, #52]	; 0x34
+ 800e8a0:	61bb      	str	r3, [r7, #24]
+  } while (((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) ||
+ 800e8a2:	69bb      	ldr	r3, [r7, #24]
+ 800e8a4:	f003 0345 	and.w	r3, r3, #69	; 0x45
+ 800e8a8:	2b00      	cmp	r3, #0
+ 800e8aa:	d0ef      	beq.n	800e88c <SDMMC_GetCmdResp6+0x24>
+           ((sta_reg & SDMMC_FLAG_CMDACT) != 0U));
+ 800e8ac:	69bb      	ldr	r3, [r7, #24]
+ 800e8ae:	f403 5300 	and.w	r3, r3, #8192	; 0x2000
+  } while (((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) ||
+ 800e8b2:	2b00      	cmp	r3, #0
+ 800e8b4:	d1ea      	bne.n	800e88c <SDMMC_GetCmdResp6+0x24>
+
+  if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT))
+ 800e8b6:	68fb      	ldr	r3, [r7, #12]
+ 800e8b8:	6b5b      	ldr	r3, [r3, #52]	; 0x34
+ 800e8ba:	f003 0304 	and.w	r3, r3, #4
+ 800e8be:	2b00      	cmp	r3, #0
+ 800e8c0:	d004      	beq.n	800e8cc <SDMMC_GetCmdResp6+0x64>
+  {
+    __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT);
+ 800e8c2:	68fb      	ldr	r3, [r7, #12]
+ 800e8c4:	2204      	movs	r2, #4
+ 800e8c6:	639a      	str	r2, [r3, #56]	; 0x38
+
+    return SDMMC_ERROR_CMD_RSP_TIMEOUT;
+ 800e8c8:	2304      	movs	r3, #4
+ 800e8ca:	e03a      	b.n	800e942 <SDMMC_GetCmdResp6+0xda>
+  }
+  else if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL))
+ 800e8cc:	68fb      	ldr	r3, [r7, #12]
+ 800e8ce:	6b5b      	ldr	r3, [r3, #52]	; 0x34
+ 800e8d0:	f003 0301 	and.w	r3, r3, #1
+ 800e8d4:	2b00      	cmp	r3, #0
+ 800e8d6:	d004      	beq.n	800e8e2 <SDMMC_GetCmdResp6+0x7a>
+  {
+    __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL);
+ 800e8d8:	68fb      	ldr	r3, [r7, #12]
+ 800e8da:	2201      	movs	r2, #1
+ 800e8dc:	639a      	str	r2, [r3, #56]	; 0x38
+
+    return SDMMC_ERROR_CMD_CRC_FAIL;
+ 800e8de:	2301      	movs	r3, #1
+ 800e8e0:	e02f      	b.n	800e942 <SDMMC_GetCmdResp6+0xda>
+  {
+    /* Nothing to do */
+  }
+
+  /* Check response received is of desired command */
+  if (SDMMC_GetCommandResponse(SDMMCx) != SD_CMD)
+ 800e8e2:	68f8      	ldr	r0, [r7, #12]
+ 800e8e4:	f7ff fb7c 	bl	800dfe0 <SDMMC_GetCommandResponse>
+ 800e8e8:	4603      	mov	r3, r0
+ 800e8ea:	461a      	mov	r2, r3
+ 800e8ec:	7afb      	ldrb	r3, [r7, #11]
+ 800e8ee:	4293      	cmp	r3, r2
+ 800e8f0:	d001      	beq.n	800e8f6 <SDMMC_GetCmdResp6+0x8e>
+  {
+    return SDMMC_ERROR_CMD_CRC_FAIL;
+ 800e8f2:	2301      	movs	r3, #1
+ 800e8f4:	e025      	b.n	800e942 <SDMMC_GetCmdResp6+0xda>
+  }
+
+  /* Clear all the static flags */
+  __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS);
+ 800e8f6:	68fb      	ldr	r3, [r7, #12]
+ 800e8f8:	4a16      	ldr	r2, [pc, #88]	; (800e954 <SDMMC_GetCmdResp6+0xec>)
+ 800e8fa:	639a      	str	r2, [r3, #56]	; 0x38
+
+  /* We have received response, retrieve it.  */
+  response_r1 = SDMMC_GetResponse(SDMMCx, SDMMC_RESP1);
+ 800e8fc:	2100      	movs	r1, #0
+ 800e8fe:	68f8      	ldr	r0, [r7, #12]
+ 800e900:	f7ff fb7b 	bl	800dffa <SDMMC_GetResponse>
+ 800e904:	6178      	str	r0, [r7, #20]
+
+  if ((response_r1 & (SDMMC_R6_GENERAL_UNKNOWN_ERROR | SDMMC_R6_ILLEGAL_CMD |
+ 800e906:	697b      	ldr	r3, [r7, #20]
+ 800e908:	f403 4360 	and.w	r3, r3, #57344	; 0xe000
+ 800e90c:	2b00      	cmp	r3, #0
+ 800e90e:	d106      	bne.n	800e91e <SDMMC_GetCmdResp6+0xb6>
+                      SDMMC_R6_COM_CRC_FAILED)) == SDMMC_ALLZERO)
+  {
+    *pRCA = (uint16_t)(response_r1 >> 16);
+ 800e910:	697b      	ldr	r3, [r7, #20]
+ 800e912:	0c1b      	lsrs	r3, r3, #16
+ 800e914:	b29a      	uxth	r2, r3
+ 800e916:	687b      	ldr	r3, [r7, #4]
+ 800e918:	801a      	strh	r2, [r3, #0]
+
+    return SDMMC_ERROR_NONE;
+ 800e91a:	2300      	movs	r3, #0
+ 800e91c:	e011      	b.n	800e942 <SDMMC_GetCmdResp6+0xda>
+  }
+  else if ((response_r1 & SDMMC_R6_ILLEGAL_CMD) == SDMMC_R6_ILLEGAL_CMD)
+ 800e91e:	697b      	ldr	r3, [r7, #20]
+ 800e920:	f403 4380 	and.w	r3, r3, #16384	; 0x4000
+ 800e924:	2b00      	cmp	r3, #0
+ 800e926:	d002      	beq.n	800e92e <SDMMC_GetCmdResp6+0xc6>
+  {
+    return SDMMC_ERROR_ILLEGAL_CMD;
+ 800e928:	f44f 5300 	mov.w	r3, #8192	; 0x2000
+ 800e92c:	e009      	b.n	800e942 <SDMMC_GetCmdResp6+0xda>
+  }
+  else if ((response_r1 & SDMMC_R6_COM_CRC_FAILED) == SDMMC_R6_COM_CRC_FAILED)
+ 800e92e:	697b      	ldr	r3, [r7, #20]
+ 800e930:	f403 4300 	and.w	r3, r3, #32768	; 0x8000
+ 800e934:	2b00      	cmp	r3, #0
+ 800e936:	d002      	beq.n	800e93e <SDMMC_GetCmdResp6+0xd6>
+  {
+    return SDMMC_ERROR_COM_CRC_FAILED;
+ 800e938:	f44f 5380 	mov.w	r3, #4096	; 0x1000
+ 800e93c:	e001      	b.n	800e942 <SDMMC_GetCmdResp6+0xda>
+  }
+  else
+  {
+    return SDMMC_ERROR_GENERAL_UNKNOWN_ERR;
+ 800e93e:	f44f 3380 	mov.w	r3, #65536	; 0x10000
+  }
+}
+ 800e942:	4618      	mov	r0, r3
+ 800e944:	3720      	adds	r7, #32
+ 800e946:	46bd      	mov	sp, r7
+ 800e948:	bd80      	pop	{r7, pc}
+ 800e94a:	bf00      	nop
+ 800e94c:	24000014 	.word	0x24000014
+ 800e950:	10624dd3 	.word	0x10624dd3
+ 800e954:	002000c5 	.word	0x002000c5
+
+0800e958 <SDMMC_GetCmdResp7>:
+  * @brief  Checks for error conditions for R7 response.
+  * @param  hsd: SD handle
+  * @retval SD Card error state
+  */
+uint32_t SDMMC_GetCmdResp7(SDMMC_TypeDef *SDMMCx)
+{
+ 800e958:	b480      	push	{r7}
+ 800e95a:	b085      	sub	sp, #20
+ 800e95c:	af00      	add	r7, sp, #0
+ 800e95e:	6078      	str	r0, [r7, #4]
+  uint32_t sta_reg;
+  /* 8 is the number of required instructions cycles for the below loop statement.
+  The SDMMC_CMDTIMEOUT is expressed in ms */
+  uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U / 1000U);
+ 800e960:	4b22      	ldr	r3, [pc, #136]	; (800e9ec <SDMMC_GetCmdResp7+0x94>)
+ 800e962:	681b      	ldr	r3, [r3, #0]
+ 800e964:	4a22      	ldr	r2, [pc, #136]	; (800e9f0 <SDMMC_GetCmdResp7+0x98>)
+ 800e966:	fba2 2303 	umull	r2, r3, r2, r3
+ 800e96a:	0a5b      	lsrs	r3, r3, #9
+ 800e96c:	f241 3288 	movw	r2, #5000	; 0x1388
+ 800e970:	fb02 f303 	mul.w	r3, r2, r3
+ 800e974:	60fb      	str	r3, [r7, #12]
+
+  do
+  {
+    if (count-- == 0U)
+ 800e976:	68fb      	ldr	r3, [r7, #12]
+ 800e978:	1e5a      	subs	r2, r3, #1
+ 800e97a:	60fa      	str	r2, [r7, #12]
+ 800e97c:	2b00      	cmp	r3, #0
+ 800e97e:	d102      	bne.n	800e986 <SDMMC_GetCmdResp7+0x2e>
+    {
+      return SDMMC_ERROR_TIMEOUT;
+ 800e980:	f04f 4300 	mov.w	r3, #2147483648	; 0x80000000
+ 800e984:	e02c      	b.n	800e9e0 <SDMMC_GetCmdResp7+0x88>
+    }
+    sta_reg = SDMMCx->STA;
+ 800e986:	687b      	ldr	r3, [r7, #4]
+ 800e988:	6b5b      	ldr	r3, [r3, #52]	; 0x34
+ 800e98a:	60bb      	str	r3, [r7, #8]
+  } while (((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) ||
+ 800e98c:	68bb      	ldr	r3, [r7, #8]
+ 800e98e:	f003 0345 	and.w	r3, r3, #69	; 0x45
+ 800e992:	2b00      	cmp	r3, #0
+ 800e994:	d0ef      	beq.n	800e976 <SDMMC_GetCmdResp7+0x1e>
+           ((sta_reg & SDMMC_FLAG_CMDACT) != 0U));
+ 800e996:	68bb      	ldr	r3, [r7, #8]
+ 800e998:	f403 5300 	and.w	r3, r3, #8192	; 0x2000
+  } while (((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) ||
+ 800e99c:	2b00      	cmp	r3, #0
+ 800e99e:	d1ea      	bne.n	800e976 <SDMMC_GetCmdResp7+0x1e>
+
+  if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT))
+ 800e9a0:	687b      	ldr	r3, [r7, #4]
+ 800e9a2:	6b5b      	ldr	r3, [r3, #52]	; 0x34
+ 800e9a4:	f003 0304 	and.w	r3, r3, #4
+ 800e9a8:	2b00      	cmp	r3, #0
+ 800e9aa:	d004      	beq.n	800e9b6 <SDMMC_GetCmdResp7+0x5e>
+  {
+    /* Card is not SD V2.0 compliant */
+    __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT);
+ 800e9ac:	687b      	ldr	r3, [r7, #4]
+ 800e9ae:	2204      	movs	r2, #4
+ 800e9b0:	639a      	str	r2, [r3, #56]	; 0x38
+
+    return SDMMC_ERROR_CMD_RSP_TIMEOUT;
+ 800e9b2:	2304      	movs	r3, #4
+ 800e9b4:	e014      	b.n	800e9e0 <SDMMC_GetCmdResp7+0x88>
+  }
+
+  else if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL))
+ 800e9b6:	687b      	ldr	r3, [r7, #4]
+ 800e9b8:	6b5b      	ldr	r3, [r3, #52]	; 0x34
+ 800e9ba:	f003 0301 	and.w	r3, r3, #1
+ 800e9be:	2b00      	cmp	r3, #0
+ 800e9c0:	d004      	beq.n	800e9cc <SDMMC_GetCmdResp7+0x74>
+  {
+    /* Card is not SD V2.0 compliant */
+    __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL);
+ 800e9c2:	687b      	ldr	r3, [r7, #4]
+ 800e9c4:	2201      	movs	r2, #1
+ 800e9c6:	639a      	str	r2, [r3, #56]	; 0x38
+
+    return SDMMC_ERROR_CMD_CRC_FAIL;
+ 800e9c8:	2301      	movs	r3, #1
+ 800e9ca:	e009      	b.n	800e9e0 <SDMMC_GetCmdResp7+0x88>
+  else
+  {
+    /* Nothing to do */
+  }
+
+  if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CMDREND))
+ 800e9cc:	687b      	ldr	r3, [r7, #4]
+ 800e9ce:	6b5b      	ldr	r3, [r3, #52]	; 0x34
+ 800e9d0:	f003 0340 	and.w	r3, r3, #64	; 0x40
+ 800e9d4:	2b00      	cmp	r3, #0
+ 800e9d6:	d002      	beq.n	800e9de <SDMMC_GetCmdResp7+0x86>
+  {
+    /* Card is SD V2.0 compliant */
+    __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CMDREND);
+ 800e9d8:	687b      	ldr	r3, [r7, #4]
+ 800e9da:	2240      	movs	r2, #64	; 0x40
+ 800e9dc:	639a      	str	r2, [r3, #56]	; 0x38
+  }
+
+  return SDMMC_ERROR_NONE;
+ 800e9de:	2300      	movs	r3, #0
+
+}
+ 800e9e0:	4618      	mov	r0, r3
+ 800e9e2:	3714      	adds	r7, #20
+ 800e9e4:	46bd      	mov	sp, r7
+ 800e9e6:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 800e9ea:	4770      	bx	lr
+ 800e9ec:	24000014 	.word	0x24000014
+ 800e9f0:	10624dd3 	.word	0x10624dd3
+
+0800e9f4 <SDMMC_GetCmdError>:
+  * @brief  Checks for error conditions for CMD0.
+  * @param  hsd: SD handle
+  * @retval SD Card error state
+  */
+static uint32_t SDMMC_GetCmdError(SDMMC_TypeDef *SDMMCx)
+{
+ 800e9f4:	b480      	push	{r7}
+ 800e9f6:	b085      	sub	sp, #20
+ 800e9f8:	af00      	add	r7, sp, #0
+ 800e9fa:	6078      	str	r0, [r7, #4]
+  /* 8 is the number of required instructions cycles for the below loop statement.
+  The SDMMC_CMDTIMEOUT is expressed in ms */
+  uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U / 1000U);
+ 800e9fc:	4b11      	ldr	r3, [pc, #68]	; (800ea44 <SDMMC_GetCmdError+0x50>)
+ 800e9fe:	681b      	ldr	r3, [r3, #0]
+ 800ea00:	4a11      	ldr	r2, [pc, #68]	; (800ea48 <SDMMC_GetCmdError+0x54>)
+ 800ea02:	fba2 2303 	umull	r2, r3, r2, r3
+ 800ea06:	0a5b      	lsrs	r3, r3, #9
+ 800ea08:	f241 3288 	movw	r2, #5000	; 0x1388
+ 800ea0c:	fb02 f303 	mul.w	r3, r2, r3
+ 800ea10:	60fb      	str	r3, [r7, #12]
+
+  do
+  {
+    if (count-- == 0U)
+ 800ea12:	68fb      	ldr	r3, [r7, #12]
+ 800ea14:	1e5a      	subs	r2, r3, #1
+ 800ea16:	60fa      	str	r2, [r7, #12]
+ 800ea18:	2b00      	cmp	r3, #0
+ 800ea1a:	d102      	bne.n	800ea22 <SDMMC_GetCmdError+0x2e>
+    {
+      return SDMMC_ERROR_TIMEOUT;
+ 800ea1c:	f04f 4300 	mov.w	r3, #2147483648	; 0x80000000
+ 800ea20:	e009      	b.n	800ea36 <SDMMC_GetCmdError+0x42>
+    }
+
+  } while (!__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CMDSENT));
+ 800ea22:	687b      	ldr	r3, [r7, #4]
+ 800ea24:	6b5b      	ldr	r3, [r3, #52]	; 0x34
+ 800ea26:	f003 0380 	and.w	r3, r3, #128	; 0x80
+ 800ea2a:	2b00      	cmp	r3, #0
+ 800ea2c:	d0f1      	beq.n	800ea12 <SDMMC_GetCmdError+0x1e>
+
+  /* Clear all the static flags */
+  __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS);
+ 800ea2e:	687b      	ldr	r3, [r7, #4]
+ 800ea30:	4a06      	ldr	r2, [pc, #24]	; (800ea4c <SDMMC_GetCmdError+0x58>)
+ 800ea32:	639a      	str	r2, [r3, #56]	; 0x38
+
+  return SDMMC_ERROR_NONE;
+ 800ea34:	2300      	movs	r3, #0
+}
+ 800ea36:	4618      	mov	r0, r3
+ 800ea38:	3714      	adds	r7, #20
+ 800ea3a:	46bd      	mov	sp, r7
+ 800ea3c:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 800ea40:	4770      	bx	lr
+ 800ea42:	bf00      	nop
+ 800ea44:	24000014 	.word	0x24000014
+ 800ea48:	10624dd3 	.word	0x10624dd3
+ 800ea4c:	002000c5 	.word	0x002000c5
+
+0800ea50 <MX_FATFS_Init>:
+/* USER CODE BEGIN Variables */
+
+/* USER CODE END Variables */
+
+void MX_FATFS_Init(void)
+{
+ 800ea50:	b580      	push	{r7, lr}
+ 800ea52:	af00      	add	r7, sp, #0
+  /*## FatFS: Link the SD driver ###########################*/
+  retSD = FATFS_LinkDriver(&SD_Driver, SDPath);
+ 800ea54:	4904      	ldr	r1, [pc, #16]	; (800ea68 <MX_FATFS_Init+0x18>)
+ 800ea56:	4805      	ldr	r0, [pc, #20]	; (800ea6c <MX_FATFS_Init+0x1c>)
+ 800ea58:	f001 fbea 	bl	8010230 <FATFS_LinkDriver>
+ 800ea5c:	4603      	mov	r3, r0
+ 800ea5e:	461a      	mov	r2, r3
+ 800ea60:	4b03      	ldr	r3, [pc, #12]	; (800ea70 <MX_FATFS_Init+0x20>)
+ 800ea62:	701a      	strb	r2, [r3, #0]
+
+  /* USER CODE BEGIN Init */
+  /* additional user code for init */
+  /* USER CODE END Init */
+}
+ 800ea64:	bf00      	nop
+ 800ea66:	bd80      	pop	{r7, pc}
+ 800ea68:	240073dc 	.word	0x240073dc
+ 800ea6c:	08026b80 	.word	0x08026b80
+ 800ea70:	240073d8 	.word	0x240073d8
+
+0800ea74 <BSP_SD_Init>:
+/**
+  * @brief  Initializes the SD card device.
+  * @retval SD status
+  */
+__weak uint8_t BSP_SD_Init(void)
+{
+ 800ea74:	b580      	push	{r7, lr}
+ 800ea76:	b082      	sub	sp, #8
+ 800ea78:	af00      	add	r7, sp, #0
+  uint8_t sd_state = MSD_OK;
+ 800ea7a:	2300      	movs	r3, #0
+ 800ea7c:	71fb      	strb	r3, [r7, #7]
+  /* Check if the SD card is plugged in the slot */
+  if (BSP_SD_IsDetected() != SD_PRESENT)
+ 800ea7e:	f000 f885 	bl	800eb8c <BSP_SD_IsDetected>
+ 800ea82:	4603      	mov	r3, r0
+ 800ea84:	2b01      	cmp	r3, #1
+ 800ea86:	d001      	beq.n	800ea8c <BSP_SD_Init+0x18>
+  {
+    return MSD_ERROR_SD_NOT_PRESENT;
+ 800ea88:	2302      	movs	r3, #2
+ 800ea8a:	e012      	b.n	800eab2 <BSP_SD_Init+0x3e>
+  }
+  /* HAL SD initialization */
+  sd_state = HAL_SD_Init(&hsd1);
+ 800ea8c:	480b      	ldr	r0, [pc, #44]	; (800eabc <BSP_SD_Init+0x48>)
+ 800ea8e:	f7fb febb 	bl	800a808 <HAL_SD_Init>
+ 800ea92:	4603      	mov	r3, r0
+ 800ea94:	71fb      	strb	r3, [r7, #7]
+  /* Configure SD Bus width (4 bits mode selected) */
+  if (sd_state == MSD_OK)
+ 800ea96:	79fb      	ldrb	r3, [r7, #7]
+ 800ea98:	2b00      	cmp	r3, #0
+ 800ea9a:	d109      	bne.n	800eab0 <BSP_SD_Init+0x3c>
+  {
+    /* Enable wide operation */
+    if (HAL_SD_ConfigWideBusOperation(&hsd1, SDMMC_BUS_WIDE_4B) != HAL_OK)
+ 800ea9c:	f44f 4180 	mov.w	r1, #16384	; 0x4000
+ 800eaa0:	4806      	ldr	r0, [pc, #24]	; (800eabc <BSP_SD_Init+0x48>)
+ 800eaa2:	f7fc fd71 	bl	800b588 <HAL_SD_ConfigWideBusOperation>
+ 800eaa6:	4603      	mov	r3, r0
+ 800eaa8:	2b00      	cmp	r3, #0
+ 800eaaa:	d001      	beq.n	800eab0 <BSP_SD_Init+0x3c>
+    {
+      sd_state = MSD_ERROR;
+ 800eaac:	2301      	movs	r3, #1
+ 800eaae:	71fb      	strb	r3, [r7, #7]
+    }
+  }
+
+  return sd_state;
+ 800eab0:	79fb      	ldrb	r3, [r7, #7]
+}
+ 800eab2:	4618      	mov	r0, r3
+ 800eab4:	3708      	adds	r7, #8
+ 800eab6:	46bd      	mov	sp, r7
+ 800eab8:	bd80      	pop	{r7, pc}
+ 800eaba:	bf00      	nop
+ 800eabc:	24000f48 	.word	0x24000f48
+
+0800eac0 <BSP_SD_ReadBlocks_DMA>:
+  * @param  ReadAddr: Address from where data is to be read
+  * @param  NumOfBlocks: Number of SD blocks to read
+  * @retval SD status
+  */
+__weak uint8_t BSP_SD_ReadBlocks_DMA(uint32_t *pData, uint32_t ReadAddr, uint32_t NumOfBlocks)
+{
+ 800eac0:	b580      	push	{r7, lr}
+ 800eac2:	b086      	sub	sp, #24
+ 800eac4:	af00      	add	r7, sp, #0
+ 800eac6:	60f8      	str	r0, [r7, #12]
+ 800eac8:	60b9      	str	r1, [r7, #8]
+ 800eaca:	607a      	str	r2, [r7, #4]
+  uint8_t sd_state = MSD_OK;
+ 800eacc:	2300      	movs	r3, #0
+ 800eace:	75fb      	strb	r3, [r7, #23]
+
+  /* Read block(s) in DMA transfer mode */
+  if (HAL_SD_ReadBlocks_DMA(&hsd1, (uint8_t *)pData, ReadAddr, NumOfBlocks) != HAL_OK)
+ 800ead0:	687b      	ldr	r3, [r7, #4]
+ 800ead2:	68ba      	ldr	r2, [r7, #8]
+ 800ead4:	68f9      	ldr	r1, [r7, #12]
+ 800ead6:	4806      	ldr	r0, [pc, #24]	; (800eaf0 <BSP_SD_ReadBlocks_DMA+0x30>)
+ 800ead8:	f7fb ffb6 	bl	800aa48 <HAL_SD_ReadBlocks_DMA>
+ 800eadc:	4603      	mov	r3, r0
+ 800eade:	2b00      	cmp	r3, #0
+ 800eae0:	d001      	beq.n	800eae6 <BSP_SD_ReadBlocks_DMA+0x26>
+  {
+    sd_state = MSD_ERROR;
+ 800eae2:	2301      	movs	r3, #1
+ 800eae4:	75fb      	strb	r3, [r7, #23]
+  }
+
+  return sd_state;
+ 800eae6:	7dfb      	ldrb	r3, [r7, #23]
+}
+ 800eae8:	4618      	mov	r0, r3
+ 800eaea:	3718      	adds	r7, #24
+ 800eaec:	46bd      	mov	sp, r7
+ 800eaee:	bd80      	pop	{r7, pc}
+ 800eaf0:	24000f48 	.word	0x24000f48
+
+0800eaf4 <BSP_SD_WriteBlocks_DMA>:
+  * @param  WriteAddr: Address from where data is to be written
+  * @param  NumOfBlocks: Number of SD blocks to write
+  * @retval SD status
+  */
+__weak uint8_t BSP_SD_WriteBlocks_DMA(uint32_t *pData, uint32_t WriteAddr, uint32_t NumOfBlocks)
+{
+ 800eaf4:	b580      	push	{r7, lr}
+ 800eaf6:	b086      	sub	sp, #24
+ 800eaf8:	af00      	add	r7, sp, #0
+ 800eafa:	60f8      	str	r0, [r7, #12]
+ 800eafc:	60b9      	str	r1, [r7, #8]
+ 800eafe:	607a      	str	r2, [r7, #4]
+  uint8_t sd_state = MSD_OK;
+ 800eb00:	2300      	movs	r3, #0
+ 800eb02:	75fb      	strb	r3, [r7, #23]
+
+  /* Write block(s) in DMA transfer mode */
+  if (HAL_SD_WriteBlocks_DMA(&hsd1, (uint8_t *)pData, WriteAddr, NumOfBlocks) != HAL_OK)
+ 800eb04:	687b      	ldr	r3, [r7, #4]
+ 800eb06:	68ba      	ldr	r2, [r7, #8]
+ 800eb08:	68f9      	ldr	r1, [r7, #12]
+ 800eb0a:	4806      	ldr	r0, [pc, #24]	; (800eb24 <BSP_SD_WriteBlocks_DMA+0x30>)
+ 800eb0c:	f7fc f844 	bl	800ab98 <HAL_SD_WriteBlocks_DMA>
+ 800eb10:	4603      	mov	r3, r0
+ 800eb12:	2b00      	cmp	r3, #0
+ 800eb14:	d001      	beq.n	800eb1a <BSP_SD_WriteBlocks_DMA+0x26>
+  {
+    sd_state = MSD_ERROR;
+ 800eb16:	2301      	movs	r3, #1
+ 800eb18:	75fb      	strb	r3, [r7, #23]
+  }
+
+  return sd_state;
+ 800eb1a:	7dfb      	ldrb	r3, [r7, #23]
+}
+ 800eb1c:	4618      	mov	r0, r3
+ 800eb1e:	3718      	adds	r7, #24
+ 800eb20:	46bd      	mov	sp, r7
+ 800eb22:	bd80      	pop	{r7, pc}
+ 800eb24:	24000f48 	.word	0x24000f48
+
+0800eb28 <BSP_SD_GetCardState>:
+  *          This value can be one of the following values:
+  *            @arg  SD_TRANSFER_OK: No data transfer is acting
+  *            @arg  SD_TRANSFER_BUSY: Data transfer is acting
+  */
+__weak uint8_t BSP_SD_GetCardState(void)
+{
+ 800eb28:	b580      	push	{r7, lr}
+ 800eb2a:	af00      	add	r7, sp, #0
+  return ((HAL_SD_GetCardState(&hsd1) == HAL_SD_CARD_TRANSFER ) ? SD_TRANSFER_OK : SD_TRANSFER_BUSY);
+ 800eb2c:	4805      	ldr	r0, [pc, #20]	; (800eb44 <BSP_SD_GetCardState+0x1c>)
+ 800eb2e:	f7fc fe3d 	bl	800b7ac <HAL_SD_GetCardState>
+ 800eb32:	4603      	mov	r3, r0
+ 800eb34:	2b04      	cmp	r3, #4
+ 800eb36:	bf14      	ite	ne
+ 800eb38:	2301      	movne	r3, #1
+ 800eb3a:	2300      	moveq	r3, #0
+ 800eb3c:	b2db      	uxtb	r3, r3
+}
+ 800eb3e:	4618      	mov	r0, r3
+ 800eb40:	bd80      	pop	{r7, pc}
+ 800eb42:	bf00      	nop
+ 800eb44:	24000f48 	.word	0x24000f48
+
+0800eb48 <BSP_SD_GetCardInfo>:
+  * @brief  Get SD information about specific SD card.
+  * @param  CardInfo: Pointer to HAL_SD_CardInfoTypedef structure
+  * @retval None
+  */
+__weak void BSP_SD_GetCardInfo(HAL_SD_CardInfoTypeDef *CardInfo)
+{
+ 800eb48:	b580      	push	{r7, lr}
+ 800eb4a:	b082      	sub	sp, #8
+ 800eb4c:	af00      	add	r7, sp, #0
+ 800eb4e:	6078      	str	r0, [r7, #4]
+  /* Get SD card Information */
+  HAL_SD_GetCardInfo(&hsd1, CardInfo);
+ 800eb50:	6879      	ldr	r1, [r7, #4]
+ 800eb52:	4803      	ldr	r0, [pc, #12]	; (800eb60 <BSP_SD_GetCardInfo+0x18>)
+ 800eb54:	f7fc fcec 	bl	800b530 <HAL_SD_GetCardInfo>
+}
+ 800eb58:	bf00      	nop
+ 800eb5a:	3708      	adds	r7, #8
+ 800eb5c:	46bd      	mov	sp, r7
+ 800eb5e:	bd80      	pop	{r7, pc}
+ 800eb60:	24000f48 	.word	0x24000f48
+
+0800eb64 <HAL_SD_TxCpltCallback>:
+  * @brief Tx Transfer completed callback
+  * @param hsd: SD handle
+  * @retval None
+  */
+void HAL_SD_TxCpltCallback(SD_HandleTypeDef *hsd)
+{
+ 800eb64:	b580      	push	{r7, lr}
+ 800eb66:	b082      	sub	sp, #8
+ 800eb68:	af00      	add	r7, sp, #0
+ 800eb6a:	6078      	str	r0, [r7, #4]
+  BSP_SD_WriteCpltCallback();
+ 800eb6c:	f000 f9bc 	bl	800eee8 <BSP_SD_WriteCpltCallback>
+}
+ 800eb70:	bf00      	nop
+ 800eb72:	3708      	adds	r7, #8
+ 800eb74:	46bd      	mov	sp, r7
+ 800eb76:	bd80      	pop	{r7, pc}
+
+0800eb78 <HAL_SD_RxCpltCallback>:
+  * @brief Rx Transfer completed callback
+  * @param hsd: SD handle
+  * @retval None
+  */
+void HAL_SD_RxCpltCallback(SD_HandleTypeDef *hsd)
+{
+ 800eb78:	b580      	push	{r7, lr}
+ 800eb7a:	b082      	sub	sp, #8
+ 800eb7c:	af00      	add	r7, sp, #0
+ 800eb7e:	6078      	str	r0, [r7, #4]
+  BSP_SD_ReadCpltCallback();
+ 800eb80:	f000 f9c0 	bl	800ef04 <BSP_SD_ReadCpltCallback>
+}
+ 800eb84:	bf00      	nop
+ 800eb86:	3708      	adds	r7, #8
+ 800eb88:	46bd      	mov	sp, r7
+ 800eb8a:	bd80      	pop	{r7, pc}
+
+0800eb8c <BSP_SD_IsDetected>:
+ * @brief  Detects if SD card is correctly plugged in the memory slot or not.
+ * @param  None
+ * @retval Returns if SD is detected or not
+ */
+__weak uint8_t BSP_SD_IsDetected(void)
+{
+ 800eb8c:	b580      	push	{r7, lr}
+ 800eb8e:	b082      	sub	sp, #8
+ 800eb90:	af00      	add	r7, sp, #0
+  __IO uint8_t status = SD_PRESENT;
+ 800eb92:	2301      	movs	r3, #1
+ 800eb94:	71fb      	strb	r3, [r7, #7]
+
+  if (BSP_PlatformIsDetected() == 0x0)
+ 800eb96:	f000 f80b 	bl	800ebb0 <BSP_PlatformIsDetected>
+ 800eb9a:	4603      	mov	r3, r0
+ 800eb9c:	2b00      	cmp	r3, #0
+ 800eb9e:	d101      	bne.n	800eba4 <BSP_SD_IsDetected+0x18>
+  {
+    status = SD_NOT_PRESENT;
+ 800eba0:	2300      	movs	r3, #0
+ 800eba2:	71fb      	strb	r3, [r7, #7]
+  }
+
+  return status;
+ 800eba4:	79fb      	ldrb	r3, [r7, #7]
+ 800eba6:	b2db      	uxtb	r3, r3
+}
+ 800eba8:	4618      	mov	r0, r3
+ 800ebaa:	3708      	adds	r7, #8
+ 800ebac:	46bd      	mov	sp, r7
+ 800ebae:	bd80      	pop	{r7, pc}
+
+0800ebb0 <BSP_PlatformIsDetected>:
+  ******************************************************************************
+*/
+/* USER CODE END Header */
+#include "fatfs_platform.h"
+
+uint8_t	BSP_PlatformIsDetected(void) {
+ 800ebb0:	b580      	push	{r7, lr}
+ 800ebb2:	b082      	sub	sp, #8
+ 800ebb4:	af00      	add	r7, sp, #0
+    uint8_t status = SD_PRESENT;
+ 800ebb6:	2301      	movs	r3, #1
+ 800ebb8:	71fb      	strb	r3, [r7, #7]
+    /* Check SD card detect pin */
+    if(HAL_GPIO_ReadPin(SD_DETECT_GPIO_PORT, SD_DETECT_PIN) != GPIO_PIN_RESET)
+ 800ebba:	f44f 4100 	mov.w	r1, #32768	; 0x8000
+ 800ebbe:	4806      	ldr	r0, [pc, #24]	; (800ebd8 <BSP_PlatformIsDetected+0x28>)
+ 800ebc0:	f7f7 ff9e 	bl	8006b00 <HAL_GPIO_ReadPin>
+ 800ebc4:	4603      	mov	r3, r0
+ 800ebc6:	2b00      	cmp	r3, #0
+ 800ebc8:	d001      	beq.n	800ebce <BSP_PlatformIsDetected+0x1e>
+    {
+        status = SD_NOT_PRESENT;
+ 800ebca:	2300      	movs	r3, #0
+ 800ebcc:	71fb      	strb	r3, [r7, #7]
+    }
+    /* USER CODE BEGIN 1 */
+    /* user code can be inserted here */
+    /* USER CODE END 1 */
+    return status;
+ 800ebce:	79fb      	ldrb	r3, [r7, #7]
+}
+ 800ebd0:	4618      	mov	r0, r3
+ 800ebd2:	3708      	adds	r7, #8
+ 800ebd4:	46bd      	mov	sp, r7
+ 800ebd6:	bd80      	pop	{r7, pc}
+ 800ebd8:	58020400 	.word	0x58020400
+
+0800ebdc <SD_CheckStatusWithTimeout>:
+/* USER CODE END beforeFunctionSection */
+
+/* Private functions ---------------------------------------------------------*/
+
+static int SD_CheckStatusWithTimeout(uint32_t timeout)
+{
+ 800ebdc:	b580      	push	{r7, lr}
+ 800ebde:	b084      	sub	sp, #16
+ 800ebe0:	af00      	add	r7, sp, #0
+ 800ebe2:	6078      	str	r0, [r7, #4]
+  uint32_t timer;
+  /* block until SDIO peripheral is ready again or a timeout occur */
+#if (osCMSIS <= 0x20000U)
+  timer = osKernelSysTick();
+ 800ebe4:	f001 fb70 	bl	80102c8 <osKernelSysTick>
+ 800ebe8:	60f8      	str	r0, [r7, #12]
+  while( osKernelSysTick() - timer < timeout)
+ 800ebea:	e006      	b.n	800ebfa <SD_CheckStatusWithTimeout+0x1e>
+#else
+  timer = osKernelGetTickCount();
+  while( osKernelGetTickCount() - timer < timeout)
+#endif
+  {
+    if (BSP_SD_GetCardState() == SD_TRANSFER_OK)
+ 800ebec:	f7ff ff9c 	bl	800eb28 <BSP_SD_GetCardState>
+ 800ebf0:	4603      	mov	r3, r0
+ 800ebf2:	2b00      	cmp	r3, #0
+ 800ebf4:	d101      	bne.n	800ebfa <SD_CheckStatusWithTimeout+0x1e>
+    {
+      return 0;
+ 800ebf6:	2300      	movs	r3, #0
+ 800ebf8:	e009      	b.n	800ec0e <SD_CheckStatusWithTimeout+0x32>
+  while( osKernelSysTick() - timer < timeout)
+ 800ebfa:	f001 fb65 	bl	80102c8 <osKernelSysTick>
+ 800ebfe:	4602      	mov	r2, r0
+ 800ec00:	68fb      	ldr	r3, [r7, #12]
+ 800ec02:	1ad3      	subs	r3, r2, r3
+ 800ec04:	687a      	ldr	r2, [r7, #4]
+ 800ec06:	429a      	cmp	r2, r3
+ 800ec08:	d8f0      	bhi.n	800ebec <SD_CheckStatusWithTimeout+0x10>
+    }
+  }
+
+  return -1;
+ 800ec0a:	f04f 33ff 	mov.w	r3, #4294967295
+}
+ 800ec0e:	4618      	mov	r0, r3
+ 800ec10:	3710      	adds	r7, #16
+ 800ec12:	46bd      	mov	sp, r7
+ 800ec14:	bd80      	pop	{r7, pc}
+	...
+
+0800ec18 <SD_CheckStatus>:
+
+static DSTATUS SD_CheckStatus(BYTE lun)
+{
+ 800ec18:	b580      	push	{r7, lr}
+ 800ec1a:	b082      	sub	sp, #8
+ 800ec1c:	af00      	add	r7, sp, #0
+ 800ec1e:	4603      	mov	r3, r0
+ 800ec20:	71fb      	strb	r3, [r7, #7]
+  Stat = STA_NOINIT;
+ 800ec22:	4b0b      	ldr	r3, [pc, #44]	; (800ec50 <SD_CheckStatus+0x38>)
+ 800ec24:	2201      	movs	r2, #1
+ 800ec26:	701a      	strb	r2, [r3, #0]
+
+  if(BSP_SD_GetCardState() == SD_TRANSFER_OK)
+ 800ec28:	f7ff ff7e 	bl	800eb28 <BSP_SD_GetCardState>
+ 800ec2c:	4603      	mov	r3, r0
+ 800ec2e:	2b00      	cmp	r3, #0
+ 800ec30:	d107      	bne.n	800ec42 <SD_CheckStatus+0x2a>
+  {
+    Stat &= ~STA_NOINIT;
+ 800ec32:	4b07      	ldr	r3, [pc, #28]	; (800ec50 <SD_CheckStatus+0x38>)
+ 800ec34:	781b      	ldrb	r3, [r3, #0]
+ 800ec36:	b2db      	uxtb	r3, r3
+ 800ec38:	f023 0301 	bic.w	r3, r3, #1
+ 800ec3c:	b2da      	uxtb	r2, r3
+ 800ec3e:	4b04      	ldr	r3, [pc, #16]	; (800ec50 <SD_CheckStatus+0x38>)
+ 800ec40:	701a      	strb	r2, [r3, #0]
+  }
+
+  return Stat;
+ 800ec42:	4b03      	ldr	r3, [pc, #12]	; (800ec50 <SD_CheckStatus+0x38>)
+ 800ec44:	781b      	ldrb	r3, [r3, #0]
+ 800ec46:	b2db      	uxtb	r3, r3
+}
+ 800ec48:	4618      	mov	r0, r3
+ 800ec4a:	3708      	adds	r7, #8
+ 800ec4c:	46bd      	mov	sp, r7
+ 800ec4e:	bd80      	pop	{r7, pc}
+ 800ec50:	24000021 	.word	0x24000021
+
+0800ec54 <SD_initialize>:
+  * @brief  Initializes a Drive
+  * @param  lun : not used
+  * @retval DSTATUS: Operation status
+  */
+DSTATUS SD_initialize(BYTE lun)
+{
+ 800ec54:	b590      	push	{r4, r7, lr}
+ 800ec56:	b087      	sub	sp, #28
+ 800ec58:	af00      	add	r7, sp, #0
+ 800ec5a:	4603      	mov	r3, r0
+ 800ec5c:	71fb      	strb	r3, [r7, #7]
+Stat = STA_NOINIT;
+ 800ec5e:	4b20      	ldr	r3, [pc, #128]	; (800ece0 <SD_initialize+0x8c>)
+ 800ec60:	2201      	movs	r2, #1
+ 800ec62:	701a      	strb	r2, [r3, #0]
+  /*
+   * check that the kernel has been started before continuing
+   * as the osMessage API will fail otherwise
+   */
+#if (osCMSIS <= 0x20000U)
+  if(osKernelRunning())
+ 800ec64:	f001 fb24 	bl	80102b0 <osKernelRunning>
+ 800ec68:	4603      	mov	r3, r0
+ 800ec6a:	2b00      	cmp	r3, #0
+ 800ec6c:	d030      	beq.n	800ecd0 <SD_initialize+0x7c>
+  if(osKernelGetState() == osKernelRunning)
+#endif
+  {
+#if !defined(DISABLE_SD_INIT)
+
+    if(BSP_SD_Init() == MSD_OK)
+ 800ec6e:	f7ff ff01 	bl	800ea74 <BSP_SD_Init>
+ 800ec72:	4603      	mov	r3, r0
+ 800ec74:	2b00      	cmp	r3, #0
+ 800ec76:	d107      	bne.n	800ec88 <SD_initialize+0x34>
+    {
+      Stat = SD_CheckStatus(lun);
+ 800ec78:	79fb      	ldrb	r3, [r7, #7]
+ 800ec7a:	4618      	mov	r0, r3
+ 800ec7c:	f7ff ffcc 	bl	800ec18 <SD_CheckStatus>
+ 800ec80:	4603      	mov	r3, r0
+ 800ec82:	461a      	mov	r2, r3
+ 800ec84:	4b16      	ldr	r3, [pc, #88]	; (800ece0 <SD_initialize+0x8c>)
+ 800ec86:	701a      	strb	r2, [r3, #0]
+    /*
+    * if the SD is correctly initialized, create the operation queue
+    * if not already created
+    */
+
+    if (Stat != STA_NOINIT)
+ 800ec88:	4b15      	ldr	r3, [pc, #84]	; (800ece0 <SD_initialize+0x8c>)
+ 800ec8a:	781b      	ldrb	r3, [r3, #0]
+ 800ec8c:	b2db      	uxtb	r3, r3
+ 800ec8e:	2b01      	cmp	r3, #1
+ 800ec90:	d01e      	beq.n	800ecd0 <SD_initialize+0x7c>
+    {
+      if (SDQueueID == NULL)
+ 800ec92:	4b14      	ldr	r3, [pc, #80]	; (800ece4 <SD_initialize+0x90>)
+ 800ec94:	681b      	ldr	r3, [r3, #0]
+ 800ec96:	2b00      	cmp	r3, #0
+ 800ec98:	d10e      	bne.n	800ecb8 <SD_initialize+0x64>
+      {
+ #if (osCMSIS <= 0x20000U)
+      osMessageQDef(SD_Queue, QUEUE_SIZE, uint16_t);
+ 800ec9a:	4b13      	ldr	r3, [pc, #76]	; (800ece8 <SD_initialize+0x94>)
+ 800ec9c:	f107 0408 	add.w	r4, r7, #8
+ 800eca0:	cb0f      	ldmia	r3, {r0, r1, r2, r3}
+ 800eca2:	e884 000f 	stmia.w	r4, {r0, r1, r2, r3}
+      SDQueueID = osMessageCreate (osMessageQ(SD_Queue), NULL);
+ 800eca6:	f107 0308 	add.w	r3, r7, #8
+ 800ecaa:	2100      	movs	r1, #0
+ 800ecac:	4618      	mov	r0, r3
+ 800ecae:	f001 fce0 	bl	8010672 <osMessageCreate>
+ 800ecb2:	4603      	mov	r3, r0
+ 800ecb4:	4a0b      	ldr	r2, [pc, #44]	; (800ece4 <SD_initialize+0x90>)
+ 800ecb6:	6013      	str	r3, [r2, #0]
+#else
+      SDQueueID = osMessageQueueNew(QUEUE_SIZE, 2, NULL);
+#endif
+      }
+
+      if (SDQueueID == NULL)
+ 800ecb8:	4b0a      	ldr	r3, [pc, #40]	; (800ece4 <SD_initialize+0x90>)
+ 800ecba:	681b      	ldr	r3, [r3, #0]
+ 800ecbc:	2b00      	cmp	r3, #0
+ 800ecbe:	d107      	bne.n	800ecd0 <SD_initialize+0x7c>
+      {
+        Stat |= STA_NOINIT;
+ 800ecc0:	4b07      	ldr	r3, [pc, #28]	; (800ece0 <SD_initialize+0x8c>)
+ 800ecc2:	781b      	ldrb	r3, [r3, #0]
+ 800ecc4:	b2db      	uxtb	r3, r3
+ 800ecc6:	f043 0301 	orr.w	r3, r3, #1
+ 800ecca:	b2da      	uxtb	r2, r3
+ 800eccc:	4b04      	ldr	r3, [pc, #16]	; (800ece0 <SD_initialize+0x8c>)
+ 800ecce:	701a      	strb	r2, [r3, #0]
+      }
+    }
+  }
+
+  return Stat;
+ 800ecd0:	4b03      	ldr	r3, [pc, #12]	; (800ece0 <SD_initialize+0x8c>)
+ 800ecd2:	781b      	ldrb	r3, [r3, #0]
+ 800ecd4:	b2db      	uxtb	r3, r3
+}
+ 800ecd6:	4618      	mov	r0, r3
+ 800ecd8:	371c      	adds	r7, #28
+ 800ecda:	46bd      	mov	sp, r7
+ 800ecdc:	bd90      	pop	{r4, r7, pc}
+ 800ecde:	bf00      	nop
+ 800ece0:	24000021 	.word	0x24000021
+ 800ece4:	240073e0 	.word	0x240073e0
+ 800ece8:	08022e84 	.word	0x08022e84
+
+0800ecec <SD_status>:
+  * @brief  Gets Disk Status
+  * @param  lun : not used
+  * @retval DSTATUS: Operation status
+  */
+DSTATUS SD_status(BYTE lun)
+{
+ 800ecec:	b580      	push	{r7, lr}
+ 800ecee:	b082      	sub	sp, #8
+ 800ecf0:	af00      	add	r7, sp, #0
+ 800ecf2:	4603      	mov	r3, r0
+ 800ecf4:	71fb      	strb	r3, [r7, #7]
+  return SD_CheckStatus(lun);
+ 800ecf6:	79fb      	ldrb	r3, [r7, #7]
+ 800ecf8:	4618      	mov	r0, r3
+ 800ecfa:	f7ff ff8d 	bl	800ec18 <SD_CheckStatus>
+ 800ecfe:	4603      	mov	r3, r0
+}
+ 800ed00:	4618      	mov	r0, r3
+ 800ed02:	3708      	adds	r7, #8
+ 800ed04:	46bd      	mov	sp, r7
+ 800ed06:	bd80      	pop	{r7, pc}
+
+0800ed08 <SD_read>:
+  * @param  count: Number of sectors to read (1..128)
+  * @retval DRESULT: Operation result
+  */
+
+DRESULT SD_read(BYTE lun, BYTE *buff, DWORD sector, UINT count)
+{
+ 800ed08:	b580      	push	{r7, lr}
+ 800ed0a:	b08a      	sub	sp, #40	; 0x28
+ 800ed0c:	af00      	add	r7, sp, #0
+ 800ed0e:	60b9      	str	r1, [r7, #8]
+ 800ed10:	607a      	str	r2, [r7, #4]
+ 800ed12:	603b      	str	r3, [r7, #0]
+ 800ed14:	4603      	mov	r3, r0
+ 800ed16:	73fb      	strb	r3, [r7, #15]
+  uint8_t ret;
+  DRESULT res = RES_ERROR;
+ 800ed18:	2301      	movs	r3, #1
+ 800ed1a:	f887 3027 	strb.w	r3, [r7, #39]	; 0x27
+#endif
+  /*
+  * ensure the SDCard is ready for a new operation
+  */
+
+  if (SD_CheckStatusWithTimeout(SD_TIMEOUT) < 0)
+ 800ed1e:	f247 5030 	movw	r0, #30000	; 0x7530
+ 800ed22:	f7ff ff5b 	bl	800ebdc <SD_CheckStatusWithTimeout>
+ 800ed26:	4603      	mov	r3, r0
+ 800ed28:	2b00      	cmp	r3, #0
+ 800ed2a:	da02      	bge.n	800ed32 <SD_read+0x2a>
+  {
+    return res;
+ 800ed2c:	f897 3027 	ldrb.w	r3, [r7, #39]	; 0x27
+ 800ed30:	e032      	b.n	800ed98 <SD_read+0x90>
+#if defined(ENABLE_SCRATCH_BUFFER)
+  if (!((uint32_t)buff & 0x3))
+  {
+#endif
+    /* Fast path cause destination buffer is correctly aligned */
+    ret = BSP_SD_ReadBlocks_DMA((uint32_t*)buff, (uint32_t)(sector), count);
+ 800ed32:	683a      	ldr	r2, [r7, #0]
+ 800ed34:	6879      	ldr	r1, [r7, #4]
+ 800ed36:	68b8      	ldr	r0, [r7, #8]
+ 800ed38:	f7ff fec2 	bl	800eac0 <BSP_SD_ReadBlocks_DMA>
+ 800ed3c:	4603      	mov	r3, r0
+ 800ed3e:	f887 3026 	strb.w	r3, [r7, #38]	; 0x26
+
+    if (ret == MSD_OK) {
+ 800ed42:	f897 3026 	ldrb.w	r3, [r7, #38]	; 0x26
+ 800ed46:	2b00      	cmp	r3, #0
+ 800ed48:	d124      	bne.n	800ed94 <SD_read+0x8c>
+#if (osCMSIS < 0x20000U)
+    /* wait for a message from the queue or a timeout */
+    event = osMessageGet(SDQueueID, SD_TIMEOUT);
+ 800ed4a:	4b15      	ldr	r3, [pc, #84]	; (800eda0 <SD_read+0x98>)
+ 800ed4c:	6819      	ldr	r1, [r3, #0]
+ 800ed4e:	f107 0314 	add.w	r3, r7, #20
+ 800ed52:	f247 5230 	movw	r2, #30000	; 0x7530
+ 800ed56:	4618      	mov	r0, r3
+ 800ed58:	f001 fcf4 	bl	8010744 <osMessageGet>
+
+    if (event.status == osEventMessage)
+ 800ed5c:	697b      	ldr	r3, [r7, #20]
+ 800ed5e:	2b10      	cmp	r3, #16
+ 800ed60:	d118      	bne.n	800ed94 <SD_read+0x8c>
+    {
+      if (event.value.v == READ_CPLT_MSG)
+ 800ed62:	69bb      	ldr	r3, [r7, #24]
+ 800ed64:	2b01      	cmp	r3, #1
+ 800ed66:	d115      	bne.n	800ed94 <SD_read+0x8c>
+      {
+        timer = osKernelSysTick();
+ 800ed68:	f001 faae 	bl	80102c8 <osKernelSysTick>
+ 800ed6c:	6238      	str	r0, [r7, #32]
+        /* block until SDIO IP is ready or a timeout occur */
+        while(osKernelSysTick() - timer <SD_TIMEOUT)
+ 800ed6e:	e008      	b.n	800ed82 <SD_read+0x7a>
+            timer = osKernelGetTickCount();
+            /* block until SDIO IP is ready or a timeout occur */
+            while(osKernelGetTickCount() - timer <SD_TIMEOUT)
+#endif
+            {
+              if (BSP_SD_GetCardState() == SD_TRANSFER_OK)
+ 800ed70:	f7ff feda 	bl	800eb28 <BSP_SD_GetCardState>
+ 800ed74:	4603      	mov	r3, r0
+ 800ed76:	2b00      	cmp	r3, #0
+ 800ed78:	d103      	bne.n	800ed82 <SD_read+0x7a>
+              {
+                res = RES_OK;
+ 800ed7a:	2300      	movs	r3, #0
+ 800ed7c:	f887 3027 	strb.w	r3, [r7, #39]	; 0x27
+                adjust the address and the D-Cache size to invalidate accordingly.
+                */
+                alignedAddr = (uint32_t)buff & ~0x1F;
+                SCB_InvalidateDCache_by_Addr((uint32_t*)alignedAddr, count*BLOCKSIZE + ((uint32_t)buff - alignedAddr));
+#endif
+                break;
+ 800ed80:	e008      	b.n	800ed94 <SD_read+0x8c>
+        while(osKernelSysTick() - timer <SD_TIMEOUT)
+ 800ed82:	f001 faa1 	bl	80102c8 <osKernelSysTick>
+ 800ed86:	4602      	mov	r2, r0
+ 800ed88:	6a3b      	ldr	r3, [r7, #32]
+ 800ed8a:	1ad3      	subs	r3, r2, r3
+ 800ed8c:	f247 522f 	movw	r2, #29999	; 0x752f
+ 800ed90:	4293      	cmp	r3, r2
+ 800ed92:	d9ed      	bls.n	800ed70 <SD_read+0x68>
+
+      if ((i == count) && (ret == MSD_OK ))
+        res = RES_OK;
+    }
+#endif
+  return res;
+ 800ed94:	f897 3027 	ldrb.w	r3, [r7, #39]	; 0x27
+}
+ 800ed98:	4618      	mov	r0, r3
+ 800ed9a:	3728      	adds	r7, #40	; 0x28
+ 800ed9c:	46bd      	mov	sp, r7
+ 800ed9e:	bd80      	pop	{r7, pc}
+ 800eda0:	240073e0 	.word	0x240073e0
+
+0800eda4 <SD_write>:
+  * @retval DRESULT: Operation result
+  */
+#if _USE_WRITE == 1
+
+DRESULT SD_write(BYTE lun, const BYTE *buff, DWORD sector, UINT count)
+{
+ 800eda4:	b580      	push	{r7, lr}
+ 800eda6:	b08a      	sub	sp, #40	; 0x28
+ 800eda8:	af00      	add	r7, sp, #0
+ 800edaa:	60b9      	str	r1, [r7, #8]
+ 800edac:	607a      	str	r2, [r7, #4]
+ 800edae:	603b      	str	r3, [r7, #0]
+ 800edb0:	4603      	mov	r3, r0
+ 800edb2:	73fb      	strb	r3, [r7, #15]
+  DRESULT res = RES_ERROR;
+ 800edb4:	2301      	movs	r3, #1
+ 800edb6:	f887 3027 	strb.w	r3, [r7, #39]	; 0x27
+
+  /*
+  * ensure the SDCard is ready for a new operation
+  */
+
+  if (SD_CheckStatusWithTimeout(SD_TIMEOUT) < 0)
+ 800edba:	f247 5030 	movw	r0, #30000	; 0x7530
+ 800edbe:	f7ff ff0d 	bl	800ebdc <SD_CheckStatusWithTimeout>
+ 800edc2:	4603      	mov	r3, r0
+ 800edc4:	2b00      	cmp	r3, #0
+ 800edc6:	da02      	bge.n	800edce <SD_write+0x2a>
+  {
+    return res;
+ 800edc8:	f897 3027 	ldrb.w	r3, [r7, #39]	; 0x27
+ 800edcc:	e02e      	b.n	800ee2c <SD_write+0x88>
+  */
+  alignedAddr = (uint32_t)buff & ~0x1F;
+  SCB_CleanDCache_by_Addr((uint32_t*)alignedAddr, count*BLOCKSIZE + ((uint32_t)buff - alignedAddr));
+#endif
+
+  if(BSP_SD_WriteBlocks_DMA((uint32_t*)buff,
+ 800edce:	683a      	ldr	r2, [r7, #0]
+ 800edd0:	6879      	ldr	r1, [r7, #4]
+ 800edd2:	68b8      	ldr	r0, [r7, #8]
+ 800edd4:	f7ff fe8e 	bl	800eaf4 <BSP_SD_WriteBlocks_DMA>
+ 800edd8:	4603      	mov	r3, r0
+ 800edda:	2b00      	cmp	r3, #0
+ 800eddc:	d124      	bne.n	800ee28 <SD_write+0x84>
+                           (uint32_t) (sector),
+                           count) == MSD_OK)
+  {
+#if (osCMSIS < 0x20000U)
+    /* Get the message from the queue */
+    event = osMessageGet(SDQueueID, SD_TIMEOUT);
+ 800edde:	4b15      	ldr	r3, [pc, #84]	; (800ee34 <SD_write+0x90>)
+ 800ede0:	6819      	ldr	r1, [r3, #0]
+ 800ede2:	f107 0314 	add.w	r3, r7, #20
+ 800ede6:	f247 5230 	movw	r2, #30000	; 0x7530
+ 800edea:	4618      	mov	r0, r3
+ 800edec:	f001 fcaa 	bl	8010744 <osMessageGet>
+
+    if (event.status == osEventMessage)
+ 800edf0:	697b      	ldr	r3, [r7, #20]
+ 800edf2:	2b10      	cmp	r3, #16
+ 800edf4:	d118      	bne.n	800ee28 <SD_write+0x84>
+    {
+      if (event.value.v == WRITE_CPLT_MSG)
+ 800edf6:	69bb      	ldr	r3, [r7, #24]
+ 800edf8:	2b02      	cmp	r3, #2
+ 800edfa:	d115      	bne.n	800ee28 <SD_write+0x84>
+    status = osMessageQueueGet(SDQueueID, (void *)&event, NULL, SD_TIMEOUT);
+    if ((status == osOK) && (event == WRITE_CPLT_MSG))
+    {
+#endif
+ #if (osCMSIS < 0x20000U)
+        timer = osKernelSysTick();
+ 800edfc:	f001 fa64 	bl	80102c8 <osKernelSysTick>
+ 800ee00:	6238      	str	r0, [r7, #32]
+        /* block until SDIO IP is ready or a timeout occur */
+        while(osKernelSysTick() - timer  < SD_TIMEOUT)
+ 800ee02:	e008      	b.n	800ee16 <SD_write+0x72>
+        timer = osKernelGetTickCount();
+        /* block until SDIO IP is ready or a timeout occur */
+        while(osKernelGetTickCount() - timer  < SD_TIMEOUT)
+#endif
+        {
+          if (BSP_SD_GetCardState() == SD_TRANSFER_OK)
+ 800ee04:	f7ff fe90 	bl	800eb28 <BSP_SD_GetCardState>
+ 800ee08:	4603      	mov	r3, r0
+ 800ee0a:	2b00      	cmp	r3, #0
+ 800ee0c:	d103      	bne.n	800ee16 <SD_write+0x72>
+          {
+            res = RES_OK;
+ 800ee0e:	2300      	movs	r3, #0
+ 800ee10:	f887 3027 	strb.w	r3, [r7, #39]	; 0x27
+            break;
+ 800ee14:	e008      	b.n	800ee28 <SD_write+0x84>
+        while(osKernelSysTick() - timer  < SD_TIMEOUT)
+ 800ee16:	f001 fa57 	bl	80102c8 <osKernelSysTick>
+ 800ee1a:	4602      	mov	r2, r0
+ 800ee1c:	6a3b      	ldr	r3, [r7, #32]
+ 800ee1e:	1ad3      	subs	r3, r2, r3
+ 800ee20:	f247 522f 	movw	r2, #29999	; 0x752f
+ 800ee24:	4293      	cmp	r3, r2
+ 800ee26:	d9ed      	bls.n	800ee04 <SD_write+0x60>
+    }
+
+  }
+#endif
+
+  return res;
+ 800ee28:	f897 3027 	ldrb.w	r3, [r7, #39]	; 0x27
+}
+ 800ee2c:	4618      	mov	r0, r3
+ 800ee2e:	3728      	adds	r7, #40	; 0x28
+ 800ee30:	46bd      	mov	sp, r7
+ 800ee32:	bd80      	pop	{r7, pc}
+ 800ee34:	240073e0 	.word	0x240073e0
+
+0800ee38 <SD_ioctl>:
+  * @param  *buff: Buffer to send/receive control data
+  * @retval DRESULT: Operation result
+  */
+#if _USE_IOCTL == 1
+DRESULT SD_ioctl(BYTE lun, BYTE cmd, void *buff)
+{
+ 800ee38:	b580      	push	{r7, lr}
+ 800ee3a:	b08c      	sub	sp, #48	; 0x30
+ 800ee3c:	af00      	add	r7, sp, #0
+ 800ee3e:	4603      	mov	r3, r0
+ 800ee40:	603a      	str	r2, [r7, #0]
+ 800ee42:	71fb      	strb	r3, [r7, #7]
+ 800ee44:	460b      	mov	r3, r1
+ 800ee46:	71bb      	strb	r3, [r7, #6]
+  DRESULT res = RES_ERROR;
+ 800ee48:	2301      	movs	r3, #1
+ 800ee4a:	f887 302f 	strb.w	r3, [r7, #47]	; 0x2f
+  BSP_SD_CardInfo CardInfo;
+
+  if (Stat & STA_NOINIT) return RES_NOTRDY;
+ 800ee4e:	4b25      	ldr	r3, [pc, #148]	; (800eee4 <SD_ioctl+0xac>)
+ 800ee50:	781b      	ldrb	r3, [r3, #0]
+ 800ee52:	b2db      	uxtb	r3, r3
+ 800ee54:	f003 0301 	and.w	r3, r3, #1
+ 800ee58:	2b00      	cmp	r3, #0
+ 800ee5a:	d001      	beq.n	800ee60 <SD_ioctl+0x28>
+ 800ee5c:	2303      	movs	r3, #3
+ 800ee5e:	e03c      	b.n	800eeda <SD_ioctl+0xa2>
+
+  switch (cmd)
+ 800ee60:	79bb      	ldrb	r3, [r7, #6]
+ 800ee62:	2b03      	cmp	r3, #3
+ 800ee64:	d834      	bhi.n	800eed0 <SD_ioctl+0x98>
+ 800ee66:	a201      	add	r2, pc, #4	; (adr r2, 800ee6c <SD_ioctl+0x34>)
+ 800ee68:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
+ 800ee6c:	0800ee7d 	.word	0x0800ee7d
+ 800ee70:	0800ee85 	.word	0x0800ee85
+ 800ee74:	0800ee9d 	.word	0x0800ee9d
+ 800ee78:	0800eeb7 	.word	0x0800eeb7
+  {
+  /* Make sure that no pending write process */
+  case CTRL_SYNC :
+    res = RES_OK;
+ 800ee7c:	2300      	movs	r3, #0
+ 800ee7e:	f887 302f 	strb.w	r3, [r7, #47]	; 0x2f
+    break;
+ 800ee82:	e028      	b.n	800eed6 <SD_ioctl+0x9e>
+
+  /* Get number of sectors on the disk (DWORD) */
+  case GET_SECTOR_COUNT :
+    BSP_SD_GetCardInfo(&CardInfo);
+ 800ee84:	f107 0308 	add.w	r3, r7, #8
+ 800ee88:	4618      	mov	r0, r3
+ 800ee8a:	f7ff fe5d 	bl	800eb48 <BSP_SD_GetCardInfo>
+    *(DWORD*)buff = CardInfo.LogBlockNbr;
+ 800ee8e:	6a3a      	ldr	r2, [r7, #32]
+ 800ee90:	683b      	ldr	r3, [r7, #0]
+ 800ee92:	601a      	str	r2, [r3, #0]
+    res = RES_OK;
+ 800ee94:	2300      	movs	r3, #0
+ 800ee96:	f887 302f 	strb.w	r3, [r7, #47]	; 0x2f
+    break;
+ 800ee9a:	e01c      	b.n	800eed6 <SD_ioctl+0x9e>
+
+  /* Get R/W sector size (WORD) */
+  case GET_SECTOR_SIZE :
+    BSP_SD_GetCardInfo(&CardInfo);
+ 800ee9c:	f107 0308 	add.w	r3, r7, #8
+ 800eea0:	4618      	mov	r0, r3
+ 800eea2:	f7ff fe51 	bl	800eb48 <BSP_SD_GetCardInfo>
+    *(WORD*)buff = CardInfo.LogBlockSize;
+ 800eea6:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 800eea8:	b29a      	uxth	r2, r3
+ 800eeaa:	683b      	ldr	r3, [r7, #0]
+ 800eeac:	801a      	strh	r2, [r3, #0]
+    res = RES_OK;
+ 800eeae:	2300      	movs	r3, #0
+ 800eeb0:	f887 302f 	strb.w	r3, [r7, #47]	; 0x2f
+    break;
+ 800eeb4:	e00f      	b.n	800eed6 <SD_ioctl+0x9e>
+
+  /* Get erase block size in unit of sector (DWORD) */
+  case GET_BLOCK_SIZE :
+    BSP_SD_GetCardInfo(&CardInfo);
+ 800eeb6:	f107 0308 	add.w	r3, r7, #8
+ 800eeba:	4618      	mov	r0, r3
+ 800eebc:	f7ff fe44 	bl	800eb48 <BSP_SD_GetCardInfo>
+    *(DWORD*)buff = CardInfo.LogBlockSize / SD_DEFAULT_BLOCK_SIZE;
+ 800eec0:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 800eec2:	0a5a      	lsrs	r2, r3, #9
+ 800eec4:	683b      	ldr	r3, [r7, #0]
+ 800eec6:	601a      	str	r2, [r3, #0]
+    res = RES_OK;
+ 800eec8:	2300      	movs	r3, #0
+ 800eeca:	f887 302f 	strb.w	r3, [r7, #47]	; 0x2f
+    break;
+ 800eece:	e002      	b.n	800eed6 <SD_ioctl+0x9e>
+
+  default:
+    res = RES_PARERR;
+ 800eed0:	2304      	movs	r3, #4
+ 800eed2:	f887 302f 	strb.w	r3, [r7, #47]	; 0x2f
+  }
+
+  return res;
+ 800eed6:	f897 302f 	ldrb.w	r3, [r7, #47]	; 0x2f
+}
+ 800eeda:	4618      	mov	r0, r3
+ 800eedc:	3730      	adds	r7, #48	; 0x30
+ 800eede:	46bd      	mov	sp, r7
+ 800eee0:	bd80      	pop	{r7, pc}
+ 800eee2:	bf00      	nop
+ 800eee4:	24000021 	.word	0x24000021
+
+0800eee8 <BSP_SD_WriteCpltCallback>:
+  * @brief Tx Transfer completed callbacks
+  * @param hsd: SD handle
+  * @retval None
+  */
+void BSP_SD_WriteCpltCallback(void)
+{
+ 800eee8:	b580      	push	{r7, lr}
+ 800eeea:	af00      	add	r7, sp, #0
+  /*
+   * No need to add an "osKernelRunning()" check here, as the SD_initialize()
+   * is always called before any SD_Read()/SD_Write() call
+   */
+#if (osCMSIS < 0x20000U)
+   osMessagePut(SDQueueID, WRITE_CPLT_MSG, 0);
+ 800eeec:	4b04      	ldr	r3, [pc, #16]	; (800ef00 <BSP_SD_WriteCpltCallback+0x18>)
+ 800eeee:	681b      	ldr	r3, [r3, #0]
+ 800eef0:	2200      	movs	r2, #0
+ 800eef2:	2102      	movs	r1, #2
+ 800eef4:	4618      	mov	r0, r3
+ 800eef6:	f001 fbe5 	bl	80106c4 <osMessagePut>
+#else
+   const uint16_t msg = WRITE_CPLT_MSG;
+   osMessageQueuePut(SDQueueID, (const void *)&msg, 0, 0);
+#endif
+}
+ 800eefa:	bf00      	nop
+ 800eefc:	bd80      	pop	{r7, pc}
+ 800eefe:	bf00      	nop
+ 800ef00:	240073e0 	.word	0x240073e0
+
+0800ef04 <BSP_SD_ReadCpltCallback>:
+  * @brief Rx Transfer completed callbacks
+  * @param hsd: SD handle
+  * @retval None
+  */
+void BSP_SD_ReadCpltCallback(void)
+{
+ 800ef04:	b580      	push	{r7, lr}
+ 800ef06:	af00      	add	r7, sp, #0
+  /*
+   * No need to add an "osKernelRunning()" check here, as the SD_initialize()
+   * is always called before any SD_Read()/SD_Write() call
+   */
+#if (osCMSIS < 0x20000U)
+   osMessagePut(SDQueueID, READ_CPLT_MSG, 0);
+ 800ef08:	4b04      	ldr	r3, [pc, #16]	; (800ef1c <BSP_SD_ReadCpltCallback+0x18>)
+ 800ef0a:	681b      	ldr	r3, [r3, #0]
+ 800ef0c:	2200      	movs	r2, #0
+ 800ef0e:	2101      	movs	r1, #1
+ 800ef10:	4618      	mov	r0, r3
+ 800ef12:	f001 fbd7 	bl	80106c4 <osMessagePut>
+#else
+   const uint16_t msg = READ_CPLT_MSG;
+   osMessageQueuePut(SDQueueID, (const void *)&msg, 0, 0);
+#endif
+}
+ 800ef16:	bf00      	nop
+ 800ef18:	bd80      	pop	{r7, pc}
+ 800ef1a:	bf00      	nop
+ 800ef1c:	240073e0 	.word	0x240073e0
+
+0800ef20 <lwftp_send>:
+
+#include "lwftpc.h"
+
+
+/** send the data to the connected connection */
+err_t lwftp_send(struct netconn *conn, const char *data) {
+ 800ef20:	b580      	push	{r7, lr}
+ 800ef22:	b086      	sub	sp, #24
+ 800ef24:	af02      	add	r7, sp, #8
+ 800ef26:	6078      	str	r0, [r7, #4]
+ 800ef28:	6039      	str	r1, [r7, #0]
+	err_t err = 0;
+ 800ef2a:	2300      	movs	r3, #0
+ 800ef2c:	73fb      	strb	r3, [r7, #15]
+	if (strcmp(data, "\r\n") == 0)
+ 800ef2e:	4911      	ldr	r1, [pc, #68]	; (800ef74 <lwftp_send+0x54>)
+ 800ef30:	6838      	ldr	r0, [r7, #0]
+ 800ef32:	f7f1 f9ed 	bl	8000310 <strcmp>
+ 800ef36:	4603      	mov	r3, r0
+ 800ef38:	2b00      	cmp	r3, #0
+ 800ef3a:	d103      	bne.n	800ef44 <lwftp_send+0x24>
+		printf(">> lwftp: ----> send <CRLF>\r\n");
+ 800ef3c:	480e      	ldr	r0, [pc, #56]	; (800ef78 <lwftp_send+0x58>)
+ 800ef3e:	f012 fd91 	bl	8021a64 <puts>
+ 800ef42:	e003      	b.n	800ef4c <lwftp_send+0x2c>
+	else
+		printf(">> lwftp: ----> send %s", data);
+ 800ef44:	6839      	ldr	r1, [r7, #0]
+ 800ef46:	480d      	ldr	r0, [pc, #52]	; (800ef7c <lwftp_send+0x5c>)
+ 800ef48:	f012 fd1e 	bl	8021988 <iprintf>
+	err = netconn_write(conn, data, strlen(data), NETCONN_COPY);
+ 800ef4c:	6838      	ldr	r0, [r7, #0]
+ 800ef4e:	f7f1 f9e9 	bl	8000324 <strlen>
+ 800ef52:	4602      	mov	r2, r0
+ 800ef54:	2300      	movs	r3, #0
+ 800ef56:	9300      	str	r3, [sp, #0]
+ 800ef58:	2301      	movs	r3, #1
+ 800ef5a:	6839      	ldr	r1, [r7, #0]
+ 800ef5c:	6878      	ldr	r0, [r7, #4]
+ 800ef5e:	f005 f89d 	bl	801409c <netconn_write_partly>
+ 800ef62:	4603      	mov	r3, r0
+ 800ef64:	73fb      	strb	r3, [r7, #15]
+#if FTPSemaphore
+	// relaese the semaphore
+	sys_sem_signal(&ftpsem);
+#endif
+	return err;
+ 800ef66:	f997 300f 	ldrsb.w	r3, [r7, #15]
+}
+ 800ef6a:	4618      	mov	r0, r3
+ 800ef6c:	3710      	adds	r7, #16
+ 800ef6e:	46bd      	mov	sp, r7
+ 800ef70:	bd80      	pop	{r7, pc}
+ 800ef72:	bf00      	nop
+ 800ef74:	08022e94 	.word	0x08022e94
+ 800ef78:	08022e98 	.word	0x08022e98
+ 800ef7c:	08022eb8 	.word	0x08022eb8
+
+0800ef80 <lwftp_data_open>:
+
+
+err_t lwftp_data_open(lwftp_session_t *s, const char *response) {
+ 800ef80:	b580      	push	{r7, lr}
+ 800ef82:	b08a      	sub	sp, #40	; 0x28
+ 800ef84:	af00      	add	r7, sp, #0
+ 800ef86:	6078      	str	r0, [r7, #4]
+ 800ef88:	6039      	str	r1, [r7, #0]
+	err_t err = ERR_VAL;
+ 800ef8a:	23fa      	movs	r3, #250	; 0xfa
+ 800ef8c:	f887 3027 	strb.w	r3, [r7, #39]	; 0x27
+	char *ptr;
+	ip_addr_t addr_d;
+
+	ptr = strchr(response, '(');
+ 800ef90:	2128      	movs	r1, #40	; 0x28
+ 800ef92:	6838      	ldr	r0, [r7, #0]
+ 800ef94:	f012 feac 	bl	8021cf0 <strchr>
+ 800ef98:	4603      	mov	r3, r0
+ 800ef9a:	613b      	str	r3, [r7, #16]
+	if (ptr) {
+ 800ef9c:	693b      	ldr	r3, [r7, #16]
+ 800ef9e:	2b00      	cmp	r3, #0
+ 800efa0:	f000 80ae 	beq.w	800f100 <lwftp_data_open+0x180>
+		unsigned int a = strtoul(ptr + 1, &ptr, 10);
+ 800efa4:	693b      	ldr	r3, [r7, #16]
+ 800efa6:	3301      	adds	r3, #1
+ 800efa8:	f107 0110 	add.w	r1, r7, #16
+ 800efac:	220a      	movs	r2, #10
+ 800efae:	4618      	mov	r0, r3
+ 800efb0:	f012 fc1e 	bl	80217f0 <strtoul>
+ 800efb4:	6238      	str	r0, [r7, #32]
+		unsigned int b = strtoul(ptr + 1, &ptr, 10);
+ 800efb6:	693b      	ldr	r3, [r7, #16]
+ 800efb8:	3301      	adds	r3, #1
+ 800efba:	f107 0110 	add.w	r1, r7, #16
+ 800efbe:	220a      	movs	r2, #10
+ 800efc0:	4618      	mov	r0, r3
+ 800efc2:	f012 fc15 	bl	80217f0 <strtoul>
+ 800efc6:	61f8      	str	r0, [r7, #28]
+		unsigned int c = strtoul(ptr + 1, &ptr, 10);
+ 800efc8:	693b      	ldr	r3, [r7, #16]
+ 800efca:	3301      	adds	r3, #1
+ 800efcc:	f107 0110 	add.w	r1, r7, #16
+ 800efd0:	220a      	movs	r2, #10
+ 800efd2:	4618      	mov	r0, r3
+ 800efd4:	f012 fc0c 	bl	80217f0 <strtoul>
+ 800efd8:	61b8      	str	r0, [r7, #24]
+		unsigned int d = strtoul(ptr + 1, &ptr, 10);
+ 800efda:	693b      	ldr	r3, [r7, #16]
+ 800efdc:	3301      	adds	r3, #1
+ 800efde:	f107 0110 	add.w	r1, r7, #16
+ 800efe2:	220a      	movs	r2, #10
+ 800efe4:	4618      	mov	r0, r3
+ 800efe6:	f012 fc03 	bl	80217f0 <strtoul>
+ 800efea:	6178      	str	r0, [r7, #20]
+		IP4_ADDR(&addr_d, a, b, c, d);
+ 800efec:	6a3b      	ldr	r3, [r7, #32]
+ 800efee:	061a      	lsls	r2, r3, #24
+ 800eff0:	69fb      	ldr	r3, [r7, #28]
+ 800eff2:	041b      	lsls	r3, r3, #16
+ 800eff4:	f403 037f 	and.w	r3, r3, #16711680	; 0xff0000
+ 800eff8:	431a      	orrs	r2, r3
+ 800effa:	69bb      	ldr	r3, [r7, #24]
+ 800effc:	021b      	lsls	r3, r3, #8
+ 800effe:	b29b      	uxth	r3, r3
+ 800f000:	431a      	orrs	r2, r3
+ 800f002:	697b      	ldr	r3, [r7, #20]
+ 800f004:	b2db      	uxtb	r3, r3
+ 800f006:	4313      	orrs	r3, r2
+ 800f008:	061a      	lsls	r2, r3, #24
+ 800f00a:	6a3b      	ldr	r3, [r7, #32]
+ 800f00c:	0619      	lsls	r1, r3, #24
+ 800f00e:	69fb      	ldr	r3, [r7, #28]
+ 800f010:	041b      	lsls	r3, r3, #16
+ 800f012:	f403 037f 	and.w	r3, r3, #16711680	; 0xff0000
+ 800f016:	4319      	orrs	r1, r3
+ 800f018:	69bb      	ldr	r3, [r7, #24]
+ 800f01a:	021b      	lsls	r3, r3, #8
+ 800f01c:	b29b      	uxth	r3, r3
+ 800f01e:	4319      	orrs	r1, r3
+ 800f020:	697b      	ldr	r3, [r7, #20]
+ 800f022:	b2db      	uxtb	r3, r3
+ 800f024:	430b      	orrs	r3, r1
+ 800f026:	021b      	lsls	r3, r3, #8
+ 800f028:	f403 037f 	and.w	r3, r3, #16711680	; 0xff0000
+ 800f02c:	431a      	orrs	r2, r3
+ 800f02e:	6a3b      	ldr	r3, [r7, #32]
+ 800f030:	0619      	lsls	r1, r3, #24
+ 800f032:	69fb      	ldr	r3, [r7, #28]
+ 800f034:	041b      	lsls	r3, r3, #16
+ 800f036:	f403 037f 	and.w	r3, r3, #16711680	; 0xff0000
+ 800f03a:	4319      	orrs	r1, r3
+ 800f03c:	69bb      	ldr	r3, [r7, #24]
+ 800f03e:	021b      	lsls	r3, r3, #8
+ 800f040:	b29b      	uxth	r3, r3
+ 800f042:	4319      	orrs	r1, r3
+ 800f044:	697b      	ldr	r3, [r7, #20]
+ 800f046:	b2db      	uxtb	r3, r3
+ 800f048:	430b      	orrs	r3, r1
+ 800f04a:	0a1b      	lsrs	r3, r3, #8
+ 800f04c:	f403 437f 	and.w	r3, r3, #65280	; 0xff00
+ 800f050:	431a      	orrs	r2, r3
+ 800f052:	6a3b      	ldr	r3, [r7, #32]
+ 800f054:	0619      	lsls	r1, r3, #24
+ 800f056:	69fb      	ldr	r3, [r7, #28]
+ 800f058:	041b      	lsls	r3, r3, #16
+ 800f05a:	f403 037f 	and.w	r3, r3, #16711680	; 0xff0000
+ 800f05e:	4319      	orrs	r1, r3
+ 800f060:	69bb      	ldr	r3, [r7, #24]
+ 800f062:	021b      	lsls	r3, r3, #8
+ 800f064:	b29b      	uxth	r3, r3
+ 800f066:	4319      	orrs	r1, r3
+ 800f068:	697b      	ldr	r3, [r7, #20]
+ 800f06a:	b2db      	uxtb	r3, r3
+ 800f06c:	430b      	orrs	r3, r1
+ 800f06e:	0e1b      	lsrs	r3, r3, #24
+ 800f070:	4313      	orrs	r3, r2
+ 800f072:	60fb      	str	r3, [r7, #12]
+
+		s->data_port = strtoul(ptr + 1, &ptr, 10) << 8;
+ 800f074:	693b      	ldr	r3, [r7, #16]
+ 800f076:	3301      	adds	r3, #1
+ 800f078:	f107 0110 	add.w	r1, r7, #16
+ 800f07c:	220a      	movs	r2, #10
+ 800f07e:	4618      	mov	r0, r3
+ 800f080:	f012 fbb6 	bl	80217f0 <strtoul>
+ 800f084:	4603      	mov	r3, r0
+ 800f086:	b29b      	uxth	r3, r3
+ 800f088:	021b      	lsls	r3, r3, #8
+ 800f08a:	b29a      	uxth	r2, r3
+ 800f08c:	687b      	ldr	r3, [r7, #4]
+ 800f08e:	815a      	strh	r2, [r3, #10]
+		s->data_port |= strtoul(ptr + 1, &ptr, 10) & 255;
+ 800f090:	693b      	ldr	r3, [r7, #16]
+ 800f092:	3301      	adds	r3, #1
+ 800f094:	f107 0110 	add.w	r1, r7, #16
+ 800f098:	220a      	movs	r2, #10
+ 800f09a:	4618      	mov	r0, r3
+ 800f09c:	f012 fba8 	bl	80217f0 <strtoul>
+ 800f0a0:	4603      	mov	r3, r0
+ 800f0a2:	b2d9      	uxtb	r1, r3
+ 800f0a4:	687b      	ldr	r3, [r7, #4]
+ 800f0a6:	895a      	ldrh	r2, [r3, #10]
+ 800f0a8:	b28b      	uxth	r3, r1
+ 800f0aa:	4313      	orrs	r3, r2
+ 800f0ac:	b29a      	uxth	r2, r3
+ 800f0ae:	687b      	ldr	r3, [r7, #4]
+ 800f0b0:	815a      	strh	r2, [r3, #10]
+		printf(">> lwftp: server data port: '%d'\r\n", s->data_port);
+ 800f0b2:	687b      	ldr	r3, [r7, #4]
+ 800f0b4:	895b      	ldrh	r3, [r3, #10]
+ 800f0b6:	4619      	mov	r1, r3
+ 800f0b8:	4816      	ldr	r0, [pc, #88]	; (800f114 <lwftp_data_open+0x194>)
+ 800f0ba:	f012 fc65 	bl	8021988 <iprintf>
+
+		if (*ptr == ')') {
+ 800f0be:	693b      	ldr	r3, [r7, #16]
+ 800f0c0:	781b      	ldrb	r3, [r3, #0]
+ 800f0c2:	2b29      	cmp	r3, #41	; 0x29
+ 800f0c4:	d11f      	bne.n	800f106 <lwftp_data_open+0x186>
+			s->data_conn = netconn_new(NETCONN_TCP);
+ 800f0c6:	2200      	movs	r2, #0
+ 800f0c8:	2100      	movs	r1, #0
+ 800f0ca:	2010      	movs	r0, #16
+ 800f0cc:	f004 fcc6 	bl	8013a5c <netconn_new_with_proto_and_callback>
+ 800f0d0:	4602      	mov	r2, r0
+ 800f0d2:	687b      	ldr	r3, [r7, #4]
+ 800f0d4:	61da      	str	r2, [r3, #28]
+			if (s->data_conn != NULL) {
+ 800f0d6:	687b      	ldr	r3, [r7, #4]
+ 800f0d8:	69db      	ldr	r3, [r3, #28]
+ 800f0da:	2b00      	cmp	r3, #0
+ 800f0dc:	d00c      	beq.n	800f0f8 <lwftp_data_open+0x178>
+				err = netconn_connect(s->data_conn, &addr_d, s->data_port);
+ 800f0de:	687b      	ldr	r3, [r7, #4]
+ 800f0e0:	69d8      	ldr	r0, [r3, #28]
+ 800f0e2:	687b      	ldr	r3, [r7, #4]
+ 800f0e4:	895a      	ldrh	r2, [r3, #10]
+ 800f0e6:	f107 030c 	add.w	r3, r7, #12
+ 800f0ea:	4619      	mov	r1, r3
+ 800f0ec:	f004 fda8 	bl	8013c40 <netconn_connect>
+ 800f0f0:	4603      	mov	r3, r0
+ 800f0f2:	f887 3027 	strb.w	r3, [r7, #39]	; 0x27
+ 800f0f6:	e006      	b.n	800f106 <lwftp_data_open+0x186>
+			} else {
+				err = ERR_MEM;
+ 800f0f8:	23ff      	movs	r3, #255	; 0xff
+ 800f0fa:	f887 3027 	strb.w	r3, [r7, #39]	; 0x27
+ 800f0fe:	e002      	b.n	800f106 <lwftp_data_open+0x186>
+			}
+		}
+	} else {
+		err = ERR_BUF;
+ 800f100:	23fe      	movs	r3, #254	; 0xfe
+ 800f102:	f887 3027 	strb.w	r3, [r7, #39]	; 0x27
+	}
+	return err;
+ 800f106:	f997 3027 	ldrsb.w	r3, [r7, #39]	; 0x27
+}
+ 800f10a:	4618      	mov	r0, r3
+ 800f10c:	3728      	adds	r7, #40	; 0x28
+ 800f10e:	46bd      	mov	sp, r7
+ 800f110:	bd80      	pop	{r7, pc}
+ 800f112:	bf00      	nop
+ 800f114:	08022ed0 	.word	0x08022ed0
+
+0800f118 <lwftp_retrieve>:
+	return err;
+}
+
+
+/* Get data from Server*/
+err_t lwftp_retrieve(lwftp_session_t *s, const char *filename) {
+ 800f118:	b580      	push	{r7, lr}
+ 800f11a:	b0c4      	sub	sp, #272	; 0x110
+ 800f11c:	af00      	add	r7, sp, #0
+ 800f11e:	f507 7388 	add.w	r3, r7, #272	; 0x110
+ 800f122:	f5a3 7386 	sub.w	r3, r3, #268	; 0x10c
+ 800f126:	6018      	str	r0, [r3, #0]
+ 800f128:	f507 7388 	add.w	r3, r7, #272	; 0x110
+ 800f12c:	f5a3 7388 	sub.w	r3, r3, #272	; 0x110
+ 800f130:	6019      	str	r1, [r3, #0]
+	char cmd[256];
+	err_t err;
+
+	snprintf(cmd, sizeof(cmd), "RETR %s\r\n", filename);
+ 800f132:	f507 7388 	add.w	r3, r7, #272	; 0x110
+ 800f136:	f5a3 7388 	sub.w	r3, r3, #272	; 0x110
+ 800f13a:	f107 000c 	add.w	r0, r7, #12
+ 800f13e:	681b      	ldr	r3, [r3, #0]
+ 800f140:	4a14      	ldr	r2, [pc, #80]	; (800f194 <lwftp_retrieve+0x7c>)
+ 800f142:	f44f 7180 	mov.w	r1, #256	; 0x100
+ 800f146:	f012 fc95 	bl	8021a74 <sniprintf>
+	err = lwftp_send(s->conn, cmd);
+ 800f14a:	f507 7388 	add.w	r3, r7, #272	; 0x110
+ 800f14e:	f5a3 7386 	sub.w	r3, r3, #268	; 0x10c
+ 800f152:	681b      	ldr	r3, [r3, #0]
+ 800f154:	699b      	ldr	r3, [r3, #24]
+ 800f156:	f107 020c 	add.w	r2, r7, #12
+ 800f15a:	4611      	mov	r1, r2
+ 800f15c:	4618      	mov	r0, r3
+ 800f15e:	f7ff fedf 	bl	800ef20 <lwftp_send>
+ 800f162:	4603      	mov	r3, r0
+ 800f164:	f887 310f 	strb.w	r3, [r7, #271]	; 0x10f
+	if (err == ERR_OK) {
+ 800f168:	f997 310f 	ldrsb.w	r3, [r7, #271]	; 0x10f
+ 800f16c:	2b00      	cmp	r3, #0
+ 800f16e:	d103      	bne.n	800f178 <lwftp_retrieve+0x60>
+		printf(">> lwftp: command sent successfully\r\n");
+ 800f170:	4809      	ldr	r0, [pc, #36]	; (800f198 <lwftp_retrieve+0x80>)
+ 800f172:	f012 fc77 	bl	8021a64 <puts>
+ 800f176:	e005      	b.n	800f184 <lwftp_retrieve+0x6c>
+	} else {
+		printf(">> lwftp: send command failed with code %d\r\n", err);
+ 800f178:	f997 310f 	ldrsb.w	r3, [r7, #271]	; 0x10f
+ 800f17c:	4619      	mov	r1, r3
+ 800f17e:	4807      	ldr	r0, [pc, #28]	; (800f19c <lwftp_retrieve+0x84>)
+ 800f180:	f012 fc02 	bl	8021988 <iprintf>
+	}
+	return err;
+ 800f184:	f997 310f 	ldrsb.w	r3, [r7, #271]	; 0x10f
+}
+ 800f188:	4618      	mov	r0, r3
+ 800f18a:	f507 7788 	add.w	r7, r7, #272	; 0x110
+ 800f18e:	46bd      	mov	sp, r7
+ 800f190:	bd80      	pop	{r7, pc}
+ 800f192:	bf00      	nop
+ 800f194:	08022f80 	.word	0x08022f80
+ 800f198:	08022f8c 	.word	0x08022f8c
+ 800f19c:	08022f50 	.word	0x08022f50
+
+0800f1a0 <onDataReceived>:
+	return err;
+}
+
+
+
+void onDataReceived(void *data, size_t size) {
+ 800f1a0:	b580      	push	{r7, lr}
+ 800f1a2:	b082      	sub	sp, #8
+ 800f1a4:	af00      	add	r7, sp, #0
+ 800f1a6:	6078      	str	r0, [r7, #4]
+ 800f1a8:	6039      	str	r1, [r7, #0]
+	osDelay(1000);
+ 800f1aa:	f44f 707a 	mov.w	r0, #1000	; 0x3e8
+ 800f1ae:	f001 f8e7 	bl	8010380 <osDelay>
+	printf("%s\r\n", (char*) data);
+ 800f1b2:	6879      	ldr	r1, [r7, #4]
+ 800f1b4:	4803      	ldr	r0, [pc, #12]	; (800f1c4 <onDataReceived+0x24>)
+ 800f1b6:	f012 fbe7 	bl	8021988 <iprintf>
+}
+ 800f1ba:	bf00      	nop
+ 800f1bc:	3708      	adds	r7, #8
+ 800f1be:	46bd      	mov	sp, r7
+ 800f1c0:	bd80      	pop	{r7, pc}
+ 800f1c2:	bf00      	nop
+ 800f1c4:	08022fbc 	.word	0x08022fbc
+
+0800f1c8 <lwftp_data_thread>:
+//			}
+//		}
+//	}
+//}
+
+void lwftp_data_thread(void *arg) {
+ 800f1c8:	b580      	push	{r7, lr}
+ 800f1ca:	b086      	sub	sp, #24
+ 800f1cc:	af00      	add	r7, sp, #0
+ 800f1ce:	6078      	str	r0, [r7, #4]
+	lwftp_session_t *s = (lwftp_session_t*) arg;
+ 800f1d0:	687b      	ldr	r3, [r7, #4]
+ 800f1d2:	617b      	str	r3, [r7, #20]
+		static struct netbuf *d_buf;
+
+	while (1) {
+		if (s->data_conn != NULL && s->data_state == LWFTP_CONNECTED) {
+ 800f1d4:	697b      	ldr	r3, [r7, #20]
+ 800f1d6:	69db      	ldr	r3, [r3, #28]
+ 800f1d8:	2b00      	cmp	r3, #0
+ 800f1da:	d030      	beq.n	800f23e <lwftp_data_thread+0x76>
+ 800f1dc:	697b      	ldr	r3, [r7, #20]
+ 800f1de:	7d5b      	ldrb	r3, [r3, #21]
+ 800f1e0:	2b01      	cmp	r3, #1
+ 800f1e2:	d12c      	bne.n	800f23e <lwftp_data_thread+0x76>
+			err_t err = netconn_recv(s->data_conn, &d_buf);
+ 800f1e4:	697b      	ldr	r3, [r7, #20]
+ 800f1e6:	69db      	ldr	r3, [r3, #28]
+ 800f1e8:	4918      	ldr	r1, [pc, #96]	; (800f24c <lwftp_data_thread+0x84>)
+ 800f1ea:	4618      	mov	r0, r3
+ 800f1ec:	f004 fedc 	bl	8013fa8 <netconn_recv>
+ 800f1f0:	4603      	mov	r3, r0
+ 800f1f2:	74fb      	strb	r3, [r7, #19]
+			if (err == ERR_OK && d_buf != NULL) {
+ 800f1f4:	f997 3013 	ldrsb.w	r3, [r7, #19]
+ 800f1f8:	2b00      	cmp	r3, #0
+ 800f1fa:	d124      	bne.n	800f246 <lwftp_data_thread+0x7e>
+ 800f1fc:	4b13      	ldr	r3, [pc, #76]	; (800f24c <lwftp_data_thread+0x84>)
+ 800f1fe:	681b      	ldr	r3, [r3, #0]
+ 800f200:	2b00      	cmp	r3, #0
+ 800f202:	d020      	beq.n	800f246 <lwftp_data_thread+0x7e>
+				void *data;
+				u16_t len;
+				do {
+					netbuf_data(d_buf, &data, &len);
+ 800f204:	4b11      	ldr	r3, [pc, #68]	; (800f24c <lwftp_data_thread+0x84>)
+ 800f206:	681b      	ldr	r3, [r3, #0]
+ 800f208:	f107 020a 	add.w	r2, r7, #10
+ 800f20c:	f107 010c 	add.w	r1, r7, #12
+ 800f210:	4618      	mov	r0, r3
+ 800f212:	f006 fc63 	bl	8015adc <netbuf_data>
+					onDataReceived(data, len);
+ 800f216:	68fb      	ldr	r3, [r7, #12]
+ 800f218:	897a      	ldrh	r2, [r7, #10]
+ 800f21a:	4611      	mov	r1, r2
+ 800f21c:	4618      	mov	r0, r3
+ 800f21e:	f7ff ffbf 	bl	800f1a0 <onDataReceived>
+				} while (netbuf_next(d_buf) >= 0);
+ 800f222:	4b0a      	ldr	r3, [pc, #40]	; (800f24c <lwftp_data_thread+0x84>)
+ 800f224:	681b      	ldr	r3, [r3, #0]
+ 800f226:	4618      	mov	r0, r3
+ 800f228:	f006 fca2 	bl	8015b70 <netbuf_next>
+ 800f22c:	4603      	mov	r3, r0
+ 800f22e:	2b00      	cmp	r3, #0
+ 800f230:	dae8      	bge.n	800f204 <lwftp_data_thread+0x3c>
+				netbuf_delete(d_buf);
+ 800f232:	4b06      	ldr	r3, [pc, #24]	; (800f24c <lwftp_data_thread+0x84>)
+ 800f234:	681b      	ldr	r3, [r3, #0]
+ 800f236:	4618      	mov	r0, r3
+ 800f238:	f006 fc30 	bl	8015a9c <netbuf_delete>
+		if (s->data_conn != NULL && s->data_state == LWFTP_CONNECTED) {
+ 800f23c:	e003      	b.n	800f246 <lwftp_data_thread+0x7e>
+			} else {
+			}
+		} else {
+			vTaskDelay(pdMS_TO_TICKS(100));
+ 800f23e:	2064      	movs	r0, #100	; 0x64
+ 800f240:	f002 fd96 	bl	8011d70 <vTaskDelay>
+ 800f244:	e7c6      	b.n	800f1d4 <lwftp_data_thread+0xc>
+		if (s->data_conn != NULL && s->data_state == LWFTP_CONNECTED) {
+ 800f246:	bf00      	nop
+ 800f248:	e7c4      	b.n	800f1d4 <lwftp_data_thread+0xc>
+ 800f24a:	bf00      	nop
+ 800f24c:	240073e4 	.word	0x240073e4
+
+0800f250 <lwftp_ctrl_thread>:
+		}
+	}
+}
+
+void lwftp_ctrl_thread(void *arg) {
+ 800f250:	b580      	push	{r7, lr}
+ 800f252:	b0c6      	sub	sp, #280	; 0x118
+ 800f254:	af00      	add	r7, sp, #0
+ 800f256:	f507 738c 	add.w	r3, r7, #280	; 0x118
+ 800f25a:	f5a3 738a 	sub.w	r3, r3, #276	; 0x114
+ 800f25e:	6018      	str	r0, [r3, #0]
+	lwftp_session_t *s = (lwftp_session_t*) arg;
+ 800f260:	f507 738c 	add.w	r3, r7, #280	; 0x118
+ 800f264:	f5a3 738a 	sub.w	r3, r3, #276	; 0x114
+ 800f268:	681b      	ldr	r3, [r3, #0]
+ 800f26a:	f8c7 3114 	str.w	r3, [r7, #276]	; 0x114
+
+	static struct netbuf *buf;
+	uint response = 0;
+ 800f26e:	2300      	movs	r3, #0
+ 800f270:	f8c7 3110 	str.w	r3, [r7, #272]	; 0x110
+	char cmd[256];
+	err_t err;
+
+	// check session data invalid
+	if ((s->control_state != LWFTP_CLOSED) || s->conn || s->data_conn || !s->user
+ 800f274:	f8d7 3114 	ldr.w	r3, [r7, #276]	; 0x114
+ 800f278:	7d1b      	ldrb	r3, [r3, #20]
+ 800f27a:	2b00      	cmp	r3, #0
+ 800f27c:	d113      	bne.n	800f2a6 <lwftp_ctrl_thread+0x56>
+ 800f27e:	f8d7 3114 	ldr.w	r3, [r7, #276]	; 0x114
+ 800f282:	699b      	ldr	r3, [r3, #24]
+ 800f284:	2b00      	cmp	r3, #0
+ 800f286:	d10e      	bne.n	800f2a6 <lwftp_ctrl_thread+0x56>
+ 800f288:	f8d7 3114 	ldr.w	r3, [r7, #276]	; 0x114
+ 800f28c:	69db      	ldr	r3, [r3, #28]
+ 800f28e:	2b00      	cmp	r3, #0
+ 800f290:	d109      	bne.n	800f2a6 <lwftp_ctrl_thread+0x56>
+ 800f292:	f8d7 3114 	ldr.w	r3, [r7, #276]	; 0x114
+ 800f296:	68db      	ldr	r3, [r3, #12]
+ 800f298:	2b00      	cmp	r3, #0
+ 800f29a:	d004      	beq.n	800f2a6 <lwftp_ctrl_thread+0x56>
+			|| !s->pass) {
+ 800f29c:	f8d7 3114 	ldr.w	r3, [r7, #276]	; 0x114
+ 800f2a0:	691b      	ldr	r3, [r3, #16]
+ 800f2a2:	2b00      	cmp	r3, #0
+ 800f2a4:	d103      	bne.n	800f2ae <lwftp_ctrl_thread+0x5e>
+		printf(">> lwftp: invalid session data\r\n");
+ 800f2a6:	4894      	ldr	r0, [pc, #592]	; (800f4f8 <lwftp_ctrl_thread+0x2a8>)
+ 800f2a8:	f012 fbdc 	bl	8021a64 <puts>
+ 800f2ac:	e120      	b.n	800f4f0 <lwftp_ctrl_thread+0x2a0>
+		return;
+	}
+
+	s->conn = netconn_new(NETCONN_TCP);
+ 800f2ae:	2200      	movs	r2, #0
+ 800f2b0:	2100      	movs	r1, #0
+ 800f2b2:	2010      	movs	r0, #16
+ 800f2b4:	f004 fbd2 	bl	8013a5c <netconn_new_with_proto_and_callback>
+ 800f2b8:	4602      	mov	r2, r0
+ 800f2ba:	f8d7 3114 	ldr.w	r3, [r7, #276]	; 0x114
+ 800f2be:	619a      	str	r2, [r3, #24]
+	s->data_conn = netconn_new(NETCONN_TCP);
+ 800f2c0:	2200      	movs	r2, #0
+ 800f2c2:	2100      	movs	r1, #0
+ 800f2c4:	2010      	movs	r0, #16
+ 800f2c6:	f004 fbc9 	bl	8013a5c <netconn_new_with_proto_and_callback>
+ 800f2ca:	4602      	mov	r2, r0
+ 800f2cc:	f8d7 3114 	ldr.w	r3, [r7, #276]	; 0x114
+ 800f2d0:	61da      	str	r2, [r3, #28]
+
+	// create a new connection identifier
+	if (s->conn != NULL) {
+ 800f2d2:	f8d7 3114 	ldr.w	r3, [r7, #276]	; 0x114
+ 800f2d6:	699b      	ldr	r3, [r3, #24]
+ 800f2d8:	2b00      	cmp	r3, #0
+ 800f2da:	f000 80e8 	beq.w	800f4ae <lwftp_ctrl_thread+0x25e>
+		err = netconn_bind(s->conn, &s->cli_ip, 0);
+ 800f2de:	f8d7 3114 	ldr.w	r3, [r7, #276]	; 0x114
+ 800f2e2:	699b      	ldr	r3, [r3, #24]
+ 800f2e4:	f8d7 1114 	ldr.w	r1, [r7, #276]	; 0x114
+ 800f2e8:	2200      	movs	r2, #0
+ 800f2ea:	4618      	mov	r0, r3
+ 800f2ec:	f004 fc70 	bl	8013bd0 <netconn_bind>
+ 800f2f0:	4603      	mov	r3, r0
+ 800f2f2:	f887 310f 	strb.w	r3, [r7, #271]	; 0x10f
+
+		if (err == ERR_OK) {
+ 800f2f6:	f997 310f 	ldrsb.w	r3, [r7, #271]	; 0x10f
+ 800f2fa:	2b00      	cmp	r3, #0
+ 800f2fc:	f040 80d0 	bne.w	800f4a0 <lwftp_ctrl_thread+0x250>
+			printf(">> lwftp: client IP bind OK\r\n");
+ 800f300:	487e      	ldr	r0, [pc, #504]	; (800f4fc <lwftp_ctrl_thread+0x2ac>)
+ 800f302:	f012 fbaf 	bl	8021a64 <puts>
+			err = netconn_connect(s->conn, &s->svr_ip, s->svr_port);
+ 800f306:	f8d7 3114 	ldr.w	r3, [r7, #276]	; 0x114
+ 800f30a:	6998      	ldr	r0, [r3, #24]
+ 800f30c:	f8d7 3114 	ldr.w	r3, [r7, #276]	; 0x114
+ 800f310:	1d19      	adds	r1, r3, #4
+ 800f312:	f8d7 3114 	ldr.w	r3, [r7, #276]	; 0x114
+ 800f316:	891b      	ldrh	r3, [r3, #8]
+ 800f318:	461a      	mov	r2, r3
+ 800f31a:	f004 fc91 	bl	8013c40 <netconn_connect>
+ 800f31e:	4603      	mov	r3, r0
+ 800f320:	f887 310f 	strb.w	r3, [r7, #271]	; 0x10f
+
+			// If the connection to the server is established, the following will continue, else delete the connection
+			if (err == ERR_OK) {
+ 800f324:	f997 310f 	ldrsb.w	r3, [r7, #271]	; 0x10f
+ 800f328:	2b00      	cmp	r3, #0
+ 800f32a:	f040 80b2 	bne.w	800f492 <lwftp_ctrl_thread+0x242>
+				printf(">> lwftp: server connect OK\r\n");
+ 800f32e:	4874      	ldr	r0, [pc, #464]	; (800f500 <lwftp_ctrl_thread+0x2b0>)
+ 800f330:	f012 fb98 	bl	8021a64 <puts>
+				 * Response processing
+				 * =====================
+				 */
+				while (1) {
+					/* wait until the data is sent by the server*/
+					if (netconn_recv(s->conn, &buf) == ERR_OK) {
+ 800f334:	f8d7 3114 	ldr.w	r3, [r7, #276]	; 0x114
+ 800f338:	699b      	ldr	r3, [r3, #24]
+ 800f33a:	4972      	ldr	r1, [pc, #456]	; (800f504 <lwftp_ctrl_thread+0x2b4>)
+ 800f33c:	4618      	mov	r0, r3
+ 800f33e:	f004 fe33 	bl	8013fa8 <netconn_recv>
+ 800f342:	4603      	mov	r3, r0
+ 800f344:	2b00      	cmp	r3, #0
+ 800f346:	f040 808e 	bne.w	800f466 <lwftp_ctrl_thread+0x216>
+						if (buf) {
+ 800f34a:	4b6e      	ldr	r3, [pc, #440]	; (800f504 <lwftp_ctrl_thread+0x2b4>)
+ 800f34c:	681b      	ldr	r3, [r3, #0]
+ 800f34e:	2b00      	cmp	r3, #0
+ 800f350:	f000 8089 	beq.w	800f466 <lwftp_ctrl_thread+0x216>
+							response = strtoul(buf->p->payload, NULL, 10);
+ 800f354:	4b6b      	ldr	r3, [pc, #428]	; (800f504 <lwftp_ctrl_thread+0x2b4>)
+ 800f356:	681b      	ldr	r3, [r3, #0]
+ 800f358:	681b      	ldr	r3, [r3, #0]
+ 800f35a:	685b      	ldr	r3, [r3, #4]
+ 800f35c:	220a      	movs	r2, #10
+ 800f35e:	2100      	movs	r1, #0
+ 800f360:	4618      	mov	r0, r3
+ 800f362:	f012 fa45 	bl	80217f0 <strtoul>
+ 800f366:	f8c7 0110 	str.w	r0, [r7, #272]	; 0x110
+							printf("\n>> lwftp: <==== resp '%d'\r\n", response);
+ 800f36a:	f8d7 1110 	ldr.w	r1, [r7, #272]	; 0x110
+ 800f36e:	4866      	ldr	r0, [pc, #408]	; (800f508 <lwftp_ctrl_thread+0x2b8>)
+ 800f370:	f012 fb0a 	bl	8021988 <iprintf>
+
+							/** [Response 220] Service ready for new user.*/
+							if (response == 220) {
+ 800f374:	f8d7 3110 	ldr.w	r3, [r7, #272]	; 0x110
+ 800f378:	2bdc      	cmp	r3, #220	; 0xdc
+ 800f37a:	d113      	bne.n	800f3a4 <lwftp_ctrl_thread+0x154>
+								snprintf(cmd, sizeof(cmd), "USER %s\r\n", s->user);
+ 800f37c:	f8d7 3114 	ldr.w	r3, [r7, #276]	; 0x114
+ 800f380:	68db      	ldr	r3, [r3, #12]
+ 800f382:	f107 000c 	add.w	r0, r7, #12
+ 800f386:	4a61      	ldr	r2, [pc, #388]	; (800f50c <lwftp_ctrl_thread+0x2bc>)
+ 800f388:	f44f 7180 	mov.w	r1, #256	; 0x100
+ 800f38c:	f012 fb72 	bl	8021a74 <sniprintf>
+								lwftp_send(s->conn, cmd);
+ 800f390:	f8d7 3114 	ldr.w	r3, [r7, #276]	; 0x114
+ 800f394:	699b      	ldr	r3, [r3, #24]
+ 800f396:	f107 020c 	add.w	r2, r7, #12
+ 800f39a:	4611      	mov	r1, r2
+ 800f39c:	4618      	mov	r0, r3
+ 800f39e:	f7ff fdbf 	bl	800ef20 <lwftp_send>
+ 800f3a2:	e060      	b.n	800f466 <lwftp_ctrl_thread+0x216>
+							}
+							/** [Response 331] User name okay, need password.*/
+							else if (response == 331) {
+ 800f3a4:	f8d7 3110 	ldr.w	r3, [r7, #272]	; 0x110
+ 800f3a8:	f240 124b 	movw	r2, #331	; 0x14b
+ 800f3ac:	4293      	cmp	r3, r2
+ 800f3ae:	d113      	bne.n	800f3d8 <lwftp_ctrl_thread+0x188>
+								snprintf(cmd, sizeof(cmd), "PASS %s\r\n", s->pass);
+ 800f3b0:	f8d7 3114 	ldr.w	r3, [r7, #276]	; 0x114
+ 800f3b4:	691b      	ldr	r3, [r3, #16]
+ 800f3b6:	f107 000c 	add.w	r0, r7, #12
+ 800f3ba:	4a55      	ldr	r2, [pc, #340]	; (800f510 <lwftp_ctrl_thread+0x2c0>)
+ 800f3bc:	f44f 7180 	mov.w	r1, #256	; 0x100
+ 800f3c0:	f012 fb58 	bl	8021a74 <sniprintf>
+								lwftp_send(s->conn, cmd);
+ 800f3c4:	f8d7 3114 	ldr.w	r3, [r7, #276]	; 0x114
+ 800f3c8:	699b      	ldr	r3, [r3, #24]
+ 800f3ca:	f107 020c 	add.w	r2, r7, #12
+ 800f3ce:	4611      	mov	r1, r2
+ 800f3d0:	4618      	mov	r0, r3
+ 800f3d2:	f7ff fda5 	bl	800ef20 <lwftp_send>
+ 800f3d6:	e046      	b.n	800f466 <lwftp_ctrl_thread+0x216>
+							}
+							/** [Response 230] User logged in, proceed.*/
+							else if (response == 230) {
+ 800f3d8:	f8d7 3110 	ldr.w	r3, [r7, #272]	; 0x110
+ 800f3dc:	2be6      	cmp	r3, #230	; 0xe6
+ 800f3de:	d10a      	bne.n	800f3f6 <lwftp_ctrl_thread+0x1a6>
+								printf(">> lwftp: now logged in\r\n");
+ 800f3e0:	484c      	ldr	r0, [pc, #304]	; (800f514 <lwftp_ctrl_thread+0x2c4>)
+ 800f3e2:	f012 fb3f 	bl	8021a64 <puts>
+								lwftp_send(s->conn, "PASV\r\n");
+ 800f3e6:	f8d7 3114 	ldr.w	r3, [r7, #276]	; 0x114
+ 800f3ea:	699b      	ldr	r3, [r3, #24]
+ 800f3ec:	494a      	ldr	r1, [pc, #296]	; (800f518 <lwftp_ctrl_thread+0x2c8>)
+ 800f3ee:	4618      	mov	r0, r3
+ 800f3f0:	f7ff fd96 	bl	800ef20 <lwftp_send>
+ 800f3f4:	e037      	b.n	800f466 <lwftp_ctrl_thread+0x216>
+							}
+
+							/** [Response 227] Entering Passive Mode (h1,h2,h3,h4,p1,p2).*/
+							else if (response == 227) {
+ 800f3f6:	f8d7 3110 	ldr.w	r3, [r7, #272]	; 0x110
+ 800f3fa:	2be3      	cmp	r3, #227	; 0xe3
+ 800f3fc:	d121      	bne.n	800f442 <lwftp_ctrl_thread+0x1f2>
+								printf(">> lwftp: entering passive Mode\r\n");
+ 800f3fe:	4847      	ldr	r0, [pc, #284]	; (800f51c <lwftp_ctrl_thread+0x2cc>)
+ 800f400:	f012 fb30 	bl	8021a64 <puts>
+								err = lwftp_data_open(s, buf->p->payload);
+ 800f404:	4b3f      	ldr	r3, [pc, #252]	; (800f504 <lwftp_ctrl_thread+0x2b4>)
+ 800f406:	681b      	ldr	r3, [r3, #0]
+ 800f408:	681b      	ldr	r3, [r3, #0]
+ 800f40a:	685b      	ldr	r3, [r3, #4]
+ 800f40c:	4619      	mov	r1, r3
+ 800f40e:	f8d7 0114 	ldr.w	r0, [r7, #276]	; 0x114
+ 800f412:	f7ff fdb5 	bl	800ef80 <lwftp_data_open>
+ 800f416:	4603      	mov	r3, r0
+ 800f418:	f887 310f 	strb.w	r3, [r7, #271]	; 0x10f
+								if (err != ERR_OK) {
+ 800f41c:	f997 310f 	ldrsb.w	r3, [r7, #271]	; 0x10f
+ 800f420:	2b00      	cmp	r3, #0
+ 800f422:	d006      	beq.n	800f432 <lwftp_ctrl_thread+0x1e2>
+									printf(">> lwftp: data port connection failed with code %d\r\n",err);
+ 800f424:	f997 310f 	ldrsb.w	r3, [r7, #271]	; 0x10f
+ 800f428:	4619      	mov	r1, r3
+ 800f42a:	483d      	ldr	r0, [pc, #244]	; (800f520 <lwftp_ctrl_thread+0x2d0>)
+ 800f42c:	f012 faac 	bl	8021988 <iprintf>
+									goto exit;
+ 800f430:	e03e      	b.n	800f4b0 <lwftp_ctrl_thread+0x260>
+								}
+								s->data_state = LWFTP_CONNECTED;
+ 800f432:	f8d7 3114 	ldr.w	r3, [r7, #276]	; 0x114
+ 800f436:	2201      	movs	r2, #1
+ 800f438:	755a      	strb	r2, [r3, #21]
+								printf(">> lwftp: data port connect OK\r\n");
+ 800f43a:	483a      	ldr	r0, [pc, #232]	; (800f524 <lwftp_ctrl_thread+0x2d4>)
+ 800f43c:	f012 fb12 	bl	8021a64 <puts>
+ 800f440:	e011      	b.n	800f466 <lwftp_ctrl_thread+0x216>
+							}
+
+							/** [Response 125] Data connection already open; transfer starting.*/
+							else if (response == 125) {
+ 800f442:	f8d7 3110 	ldr.w	r3, [r7, #272]	; 0x110
+ 800f446:	2b7d      	cmp	r3, #125	; 0x7d
+ 800f448:	d103      	bne.n	800f452 <lwftp_ctrl_thread+0x202>
+								printf(">> lwftp: transfer starting.\r\n");
+ 800f44a:	4837      	ldr	r0, [pc, #220]	; (800f528 <lwftp_ctrl_thread+0x2d8>)
+ 800f44c:	f012 fb0a 	bl	8021a64 <puts>
+ 800f450:	e009      	b.n	800f466 <lwftp_ctrl_thread+0x216>
+							}
+
+							/** [Response 226] Closing data connection. Requested file action successful*/
+							else if (response == 226) {
+ 800f452:	f8d7 3110 	ldr.w	r3, [r7, #272]	; 0x110
+ 800f456:	2be2      	cmp	r3, #226	; 0xe2
+ 800f458:	d105      	bne.n	800f466 <lwftp_ctrl_thread+0x216>
+								printf(">> lwftp: closing data connection.\r\n");
+ 800f45a:	4834      	ldr	r0, [pc, #208]	; (800f52c <lwftp_ctrl_thread+0x2dc>)
+ 800f45c:	f012 fb02 	bl	8021a64 <puts>
+								printf(">> lwftp: requested file action successful.\r\n");
+ 800f460:	4833      	ldr	r0, [pc, #204]	; (800f530 <lwftp_ctrl_thread+0x2e0>)
+ 800f462:	f012 faff 	bl	8021a64 <puts>
+							}
+						}
+					}
+					memset(cmd, 0, sizeof(cmd));
+ 800f466:	f107 030c 	add.w	r3, r7, #12
+ 800f46a:	f44f 7280 	mov.w	r2, #256	; 0x100
+ 800f46e:	2100      	movs	r1, #0
+ 800f470:	4618      	mov	r0, r3
+ 800f472:	f012 fc35 	bl	8021ce0 <memset>
+					if (buf != NULL) {
+ 800f476:	4b23      	ldr	r3, [pc, #140]	; (800f504 <lwftp_ctrl_thread+0x2b4>)
+ 800f478:	681b      	ldr	r3, [r3, #0]
+ 800f47a:	2b00      	cmp	r3, #0
+ 800f47c:	f43f af5a 	beq.w	800f334 <lwftp_ctrl_thread+0xe4>
+						netbuf_delete(buf);
+ 800f480:	4b20      	ldr	r3, [pc, #128]	; (800f504 <lwftp_ctrl_thread+0x2b4>)
+ 800f482:	681b      	ldr	r3, [r3, #0]
+ 800f484:	4618      	mov	r0, r3
+ 800f486:	f006 fb09 	bl	8015a9c <netbuf_delete>
+						buf = NULL;
+ 800f48a:	4b1e      	ldr	r3, [pc, #120]	; (800f504 <lwftp_ctrl_thread+0x2b4>)
+ 800f48c:	2200      	movs	r2, #0
+ 800f48e:	601a      	str	r2, [r3, #0]
+					if (netconn_recv(s->conn, &buf) == ERR_OK) {
+ 800f490:	e750      	b.n	800f334 <lwftp_ctrl_thread+0xe4>
+					}
+				}
+			} else {
+				printf(">> lwftp: server connection failed with code %d\r\n", err);
+ 800f492:	f997 310f 	ldrsb.w	r3, [r7, #271]	; 0x10f
+ 800f496:	4619      	mov	r1, r3
+ 800f498:	4826      	ldr	r0, [pc, #152]	; (800f534 <lwftp_ctrl_thread+0x2e4>)
+ 800f49a:	f012 fa75 	bl	8021988 <iprintf>
+				goto exit;
+ 800f49e:	e007      	b.n	800f4b0 <lwftp_ctrl_thread+0x260>
+			}
+		} else {
+			printf(">> lwftp: client IP binding failed with code %d\r\n", err);
+ 800f4a0:	f997 310f 	ldrsb.w	r3, [r7, #271]	; 0x10f
+ 800f4a4:	4619      	mov	r1, r3
+ 800f4a6:	4824      	ldr	r0, [pc, #144]	; (800f538 <lwftp_ctrl_thread+0x2e8>)
+ 800f4a8:	f012 fa6e 	bl	8021988 <iprintf>
+			goto exit;
+ 800f4ac:	e000      	b.n	800f4b0 <lwftp_ctrl_thread+0x260>
+		}
+	}
+	exit: if (s->data_conn) {
+ 800f4ae:	bf00      	nop
+ 800f4b0:	f8d7 3114 	ldr.w	r3, [r7, #276]	; 0x114
+ 800f4b4:	69db      	ldr	r3, [r3, #28]
+ 800f4b6:	2b00      	cmp	r3, #0
+ 800f4b8:	d00b      	beq.n	800f4d2 <lwftp_ctrl_thread+0x282>
+		netconn_close(s->data_conn);
+ 800f4ba:	f8d7 3114 	ldr.w	r3, [r7, #276]	; 0x114
+ 800f4be:	69db      	ldr	r3, [r3, #28]
+ 800f4c0:	4618      	mov	r0, r3
+ 800f4c2:	f004 feed 	bl	80142a0 <netconn_close>
+		netconn_delete(s->data_conn);
+ 800f4c6:	f8d7 3114 	ldr.w	r3, [r7, #276]	; 0x114
+ 800f4ca:	69db      	ldr	r3, [r3, #28]
+ 800f4cc:	4618      	mov	r0, r3
+ 800f4ce:	f004 fb63 	bl	8013b98 <netconn_delete>
+	}
+	netconn_close(s->conn);
+ 800f4d2:	f8d7 3114 	ldr.w	r3, [r7, #276]	; 0x114
+ 800f4d6:	699b      	ldr	r3, [r3, #24]
+ 800f4d8:	4618      	mov	r0, r3
+ 800f4da:	f004 fee1 	bl	80142a0 <netconn_close>
+	netconn_delete(s->conn);
+ 800f4de:	f8d7 3114 	ldr.w	r3, [r7, #276]	; 0x114
+ 800f4e2:	699b      	ldr	r3, [r3, #24]
+ 800f4e4:	4618      	mov	r0, r3
+ 800f4e6:	f004 fb57 	bl	8013b98 <netconn_delete>
+	printf(">> lwftp: all ftp connection closed\r\n");
+ 800f4ea:	4814      	ldr	r0, [pc, #80]	; (800f53c <lwftp_ctrl_thread+0x2ec>)
+ 800f4ec:	f012 faba 	bl	8021a64 <puts>
+}
+ 800f4f0:	f507 778c 	add.w	r7, r7, #280	; 0x118
+ 800f4f4:	46bd      	mov	sp, r7
+ 800f4f6:	bd80      	pop	{r7, pc}
+ 800f4f8:	08022fc4 	.word	0x08022fc4
+ 800f4fc:	08022fe4 	.word	0x08022fe4
+ 800f500:	08023004 	.word	0x08023004
+ 800f504:	240073e8 	.word	0x240073e8
+ 800f508:	08023024 	.word	0x08023024
+ 800f50c:	08023044 	.word	0x08023044
+ 800f510:	08023050 	.word	0x08023050
+ 800f514:	0802305c 	.word	0x0802305c
+ 800f518:	08023078 	.word	0x08023078
+ 800f51c:	08023080 	.word	0x08023080
+ 800f520:	080230a4 	.word	0x080230a4
+ 800f524:	080230dc 	.word	0x080230dc
+ 800f528:	080230fc 	.word	0x080230fc
+ 800f52c:	0802311c 	.word	0x0802311c
+ 800f530:	08023140 	.word	0x08023140
+ 800f534:	08023170 	.word	0x08023170
+ 800f538:	080231a4 	.word	0x080231a4
+ 800f53c:	080231d8 	.word	0x080231d8
+
+0800f540 <MX_LWIP_Init>:
+
+/**
+  * LwIP initialization function
+  */
+void MX_LWIP_Init(void)
+{
+ 800f540:	b5b0      	push	{r4, r5, r7, lr}
+ 800f542:	b08c      	sub	sp, #48	; 0x30
+ 800f544:	af04      	add	r7, sp, #16
+  /* IP addresses initialization */
+  IP_ADDRESS[0] = 192;
+ 800f546:	4b8f      	ldr	r3, [pc, #572]	; (800f784 <MX_LWIP_Init+0x244>)
+ 800f548:	22c0      	movs	r2, #192	; 0xc0
+ 800f54a:	701a      	strb	r2, [r3, #0]
+  IP_ADDRESS[1] = 168;
+ 800f54c:	4b8d      	ldr	r3, [pc, #564]	; (800f784 <MX_LWIP_Init+0x244>)
+ 800f54e:	22a8      	movs	r2, #168	; 0xa8
+ 800f550:	705a      	strb	r2, [r3, #1]
+  IP_ADDRESS[2] = 0;
+ 800f552:	4b8c      	ldr	r3, [pc, #560]	; (800f784 <MX_LWIP_Init+0x244>)
+ 800f554:	2200      	movs	r2, #0
+ 800f556:	709a      	strb	r2, [r3, #2]
+  IP_ADDRESS[3] = 120;
+ 800f558:	4b8a      	ldr	r3, [pc, #552]	; (800f784 <MX_LWIP_Init+0x244>)
+ 800f55a:	2278      	movs	r2, #120	; 0x78
+ 800f55c:	70da      	strb	r2, [r3, #3]
+  NETMASK_ADDRESS[0] = 255;
+ 800f55e:	4b8a      	ldr	r3, [pc, #552]	; (800f788 <MX_LWIP_Init+0x248>)
+ 800f560:	22ff      	movs	r2, #255	; 0xff
+ 800f562:	701a      	strb	r2, [r3, #0]
+  NETMASK_ADDRESS[1] = 255;
+ 800f564:	4b88      	ldr	r3, [pc, #544]	; (800f788 <MX_LWIP_Init+0x248>)
+ 800f566:	22ff      	movs	r2, #255	; 0xff
+ 800f568:	705a      	strb	r2, [r3, #1]
+  NETMASK_ADDRESS[2] = 255;
+ 800f56a:	4b87      	ldr	r3, [pc, #540]	; (800f788 <MX_LWIP_Init+0x248>)
+ 800f56c:	22ff      	movs	r2, #255	; 0xff
+ 800f56e:	709a      	strb	r2, [r3, #2]
+  NETMASK_ADDRESS[3] = 0;
+ 800f570:	4b85      	ldr	r3, [pc, #532]	; (800f788 <MX_LWIP_Init+0x248>)
+ 800f572:	2200      	movs	r2, #0
+ 800f574:	70da      	strb	r2, [r3, #3]
+  GATEWAY_ADDRESS[0] = 0;
+ 800f576:	4b85      	ldr	r3, [pc, #532]	; (800f78c <MX_LWIP_Init+0x24c>)
+ 800f578:	2200      	movs	r2, #0
+ 800f57a:	701a      	strb	r2, [r3, #0]
+  GATEWAY_ADDRESS[1] = 0;
+ 800f57c:	4b83      	ldr	r3, [pc, #524]	; (800f78c <MX_LWIP_Init+0x24c>)
+ 800f57e:	2200      	movs	r2, #0
+ 800f580:	705a      	strb	r2, [r3, #1]
+  GATEWAY_ADDRESS[2] = 0;
+ 800f582:	4b82      	ldr	r3, [pc, #520]	; (800f78c <MX_LWIP_Init+0x24c>)
+ 800f584:	2200      	movs	r2, #0
+ 800f586:	709a      	strb	r2, [r3, #2]
+  GATEWAY_ADDRESS[3] = 0;
+ 800f588:	4b80      	ldr	r3, [pc, #512]	; (800f78c <MX_LWIP_Init+0x24c>)
+ 800f58a:	2200      	movs	r2, #0
+ 800f58c:	70da      	strb	r2, [r3, #3]
+/* USER CODE BEGIN IP_ADDRESSES */
+
+/* USER CODE END IP_ADDRESSES */
+
+  /* Initilialize the LwIP stack with RTOS */
+  tcpip_init( NULL, NULL );
+ 800f58e:	2100      	movs	r1, #0
+ 800f590:	2000      	movs	r0, #0
+ 800f592:	f006 fc8b 	bl	8015eac <tcpip_init>
+
+  /* IP addresses initialization without DHCP (IPv4) */
+  IP4_ADDR(&ipaddr, IP_ADDRESS[0], IP_ADDRESS[1], IP_ADDRESS[2], IP_ADDRESS[3]);
+ 800f596:	4b7b      	ldr	r3, [pc, #492]	; (800f784 <MX_LWIP_Init+0x244>)
+ 800f598:	781b      	ldrb	r3, [r3, #0]
+ 800f59a:	061a      	lsls	r2, r3, #24
+ 800f59c:	4b79      	ldr	r3, [pc, #484]	; (800f784 <MX_LWIP_Init+0x244>)
+ 800f59e:	785b      	ldrb	r3, [r3, #1]
+ 800f5a0:	041b      	lsls	r3, r3, #16
+ 800f5a2:	431a      	orrs	r2, r3
+ 800f5a4:	4b77      	ldr	r3, [pc, #476]	; (800f784 <MX_LWIP_Init+0x244>)
+ 800f5a6:	789b      	ldrb	r3, [r3, #2]
+ 800f5a8:	021b      	lsls	r3, r3, #8
+ 800f5aa:	4313      	orrs	r3, r2
+ 800f5ac:	4a75      	ldr	r2, [pc, #468]	; (800f784 <MX_LWIP_Init+0x244>)
+ 800f5ae:	78d2      	ldrb	r2, [r2, #3]
+ 800f5b0:	4313      	orrs	r3, r2
+ 800f5b2:	061a      	lsls	r2, r3, #24
+ 800f5b4:	4b73      	ldr	r3, [pc, #460]	; (800f784 <MX_LWIP_Init+0x244>)
+ 800f5b6:	781b      	ldrb	r3, [r3, #0]
+ 800f5b8:	0619      	lsls	r1, r3, #24
+ 800f5ba:	4b72      	ldr	r3, [pc, #456]	; (800f784 <MX_LWIP_Init+0x244>)
+ 800f5bc:	785b      	ldrb	r3, [r3, #1]
+ 800f5be:	041b      	lsls	r3, r3, #16
+ 800f5c0:	4319      	orrs	r1, r3
+ 800f5c2:	4b70      	ldr	r3, [pc, #448]	; (800f784 <MX_LWIP_Init+0x244>)
+ 800f5c4:	789b      	ldrb	r3, [r3, #2]
+ 800f5c6:	021b      	lsls	r3, r3, #8
+ 800f5c8:	430b      	orrs	r3, r1
+ 800f5ca:	496e      	ldr	r1, [pc, #440]	; (800f784 <MX_LWIP_Init+0x244>)
+ 800f5cc:	78c9      	ldrb	r1, [r1, #3]
+ 800f5ce:	430b      	orrs	r3, r1
+ 800f5d0:	021b      	lsls	r3, r3, #8
+ 800f5d2:	f403 037f 	and.w	r3, r3, #16711680	; 0xff0000
+ 800f5d6:	431a      	orrs	r2, r3
+ 800f5d8:	4b6a      	ldr	r3, [pc, #424]	; (800f784 <MX_LWIP_Init+0x244>)
+ 800f5da:	781b      	ldrb	r3, [r3, #0]
+ 800f5dc:	0619      	lsls	r1, r3, #24
+ 800f5de:	4b69      	ldr	r3, [pc, #420]	; (800f784 <MX_LWIP_Init+0x244>)
+ 800f5e0:	785b      	ldrb	r3, [r3, #1]
+ 800f5e2:	041b      	lsls	r3, r3, #16
+ 800f5e4:	4319      	orrs	r1, r3
+ 800f5e6:	4b67      	ldr	r3, [pc, #412]	; (800f784 <MX_LWIP_Init+0x244>)
+ 800f5e8:	789b      	ldrb	r3, [r3, #2]
+ 800f5ea:	021b      	lsls	r3, r3, #8
+ 800f5ec:	430b      	orrs	r3, r1
+ 800f5ee:	4965      	ldr	r1, [pc, #404]	; (800f784 <MX_LWIP_Init+0x244>)
+ 800f5f0:	78c9      	ldrb	r1, [r1, #3]
+ 800f5f2:	430b      	orrs	r3, r1
+ 800f5f4:	0a1b      	lsrs	r3, r3, #8
+ 800f5f6:	f403 437f 	and.w	r3, r3, #65280	; 0xff00
+ 800f5fa:	431a      	orrs	r2, r3
+ 800f5fc:	4b61      	ldr	r3, [pc, #388]	; (800f784 <MX_LWIP_Init+0x244>)
+ 800f5fe:	781b      	ldrb	r3, [r3, #0]
+ 800f600:	0619      	lsls	r1, r3, #24
+ 800f602:	4b60      	ldr	r3, [pc, #384]	; (800f784 <MX_LWIP_Init+0x244>)
+ 800f604:	785b      	ldrb	r3, [r3, #1]
+ 800f606:	041b      	lsls	r3, r3, #16
+ 800f608:	4319      	orrs	r1, r3
+ 800f60a:	4b5e      	ldr	r3, [pc, #376]	; (800f784 <MX_LWIP_Init+0x244>)
+ 800f60c:	789b      	ldrb	r3, [r3, #2]
+ 800f60e:	021b      	lsls	r3, r3, #8
+ 800f610:	430b      	orrs	r3, r1
+ 800f612:	495c      	ldr	r1, [pc, #368]	; (800f784 <MX_LWIP_Init+0x244>)
+ 800f614:	78c9      	ldrb	r1, [r1, #3]
+ 800f616:	430b      	orrs	r3, r1
+ 800f618:	0e1b      	lsrs	r3, r3, #24
+ 800f61a:	4313      	orrs	r3, r2
+ 800f61c:	4a5c      	ldr	r2, [pc, #368]	; (800f790 <MX_LWIP_Init+0x250>)
+ 800f61e:	6013      	str	r3, [r2, #0]
+  IP4_ADDR(&netmask, NETMASK_ADDRESS[0], NETMASK_ADDRESS[1] , NETMASK_ADDRESS[2], NETMASK_ADDRESS[3]);
+ 800f620:	4b59      	ldr	r3, [pc, #356]	; (800f788 <MX_LWIP_Init+0x248>)
+ 800f622:	781b      	ldrb	r3, [r3, #0]
+ 800f624:	061a      	lsls	r2, r3, #24
+ 800f626:	4b58      	ldr	r3, [pc, #352]	; (800f788 <MX_LWIP_Init+0x248>)
+ 800f628:	785b      	ldrb	r3, [r3, #1]
+ 800f62a:	041b      	lsls	r3, r3, #16
+ 800f62c:	431a      	orrs	r2, r3
+ 800f62e:	4b56      	ldr	r3, [pc, #344]	; (800f788 <MX_LWIP_Init+0x248>)
+ 800f630:	789b      	ldrb	r3, [r3, #2]
+ 800f632:	021b      	lsls	r3, r3, #8
+ 800f634:	4313      	orrs	r3, r2
+ 800f636:	4a54      	ldr	r2, [pc, #336]	; (800f788 <MX_LWIP_Init+0x248>)
+ 800f638:	78d2      	ldrb	r2, [r2, #3]
+ 800f63a:	4313      	orrs	r3, r2
+ 800f63c:	061a      	lsls	r2, r3, #24
+ 800f63e:	4b52      	ldr	r3, [pc, #328]	; (800f788 <MX_LWIP_Init+0x248>)
+ 800f640:	781b      	ldrb	r3, [r3, #0]
+ 800f642:	0619      	lsls	r1, r3, #24
+ 800f644:	4b50      	ldr	r3, [pc, #320]	; (800f788 <MX_LWIP_Init+0x248>)
+ 800f646:	785b      	ldrb	r3, [r3, #1]
+ 800f648:	041b      	lsls	r3, r3, #16
+ 800f64a:	4319      	orrs	r1, r3
+ 800f64c:	4b4e      	ldr	r3, [pc, #312]	; (800f788 <MX_LWIP_Init+0x248>)
+ 800f64e:	789b      	ldrb	r3, [r3, #2]
+ 800f650:	021b      	lsls	r3, r3, #8
+ 800f652:	430b      	orrs	r3, r1
+ 800f654:	494c      	ldr	r1, [pc, #304]	; (800f788 <MX_LWIP_Init+0x248>)
+ 800f656:	78c9      	ldrb	r1, [r1, #3]
+ 800f658:	430b      	orrs	r3, r1
+ 800f65a:	021b      	lsls	r3, r3, #8
+ 800f65c:	f403 037f 	and.w	r3, r3, #16711680	; 0xff0000
+ 800f660:	431a      	orrs	r2, r3
+ 800f662:	4b49      	ldr	r3, [pc, #292]	; (800f788 <MX_LWIP_Init+0x248>)
+ 800f664:	781b      	ldrb	r3, [r3, #0]
+ 800f666:	0619      	lsls	r1, r3, #24
+ 800f668:	4b47      	ldr	r3, [pc, #284]	; (800f788 <MX_LWIP_Init+0x248>)
+ 800f66a:	785b      	ldrb	r3, [r3, #1]
+ 800f66c:	041b      	lsls	r3, r3, #16
+ 800f66e:	4319      	orrs	r1, r3
+ 800f670:	4b45      	ldr	r3, [pc, #276]	; (800f788 <MX_LWIP_Init+0x248>)
+ 800f672:	789b      	ldrb	r3, [r3, #2]
+ 800f674:	021b      	lsls	r3, r3, #8
+ 800f676:	430b      	orrs	r3, r1
+ 800f678:	4943      	ldr	r1, [pc, #268]	; (800f788 <MX_LWIP_Init+0x248>)
+ 800f67a:	78c9      	ldrb	r1, [r1, #3]
+ 800f67c:	430b      	orrs	r3, r1
+ 800f67e:	0a1b      	lsrs	r3, r3, #8
+ 800f680:	f403 437f 	and.w	r3, r3, #65280	; 0xff00
+ 800f684:	431a      	orrs	r2, r3
+ 800f686:	4b40      	ldr	r3, [pc, #256]	; (800f788 <MX_LWIP_Init+0x248>)
+ 800f688:	781b      	ldrb	r3, [r3, #0]
+ 800f68a:	0619      	lsls	r1, r3, #24
+ 800f68c:	4b3e      	ldr	r3, [pc, #248]	; (800f788 <MX_LWIP_Init+0x248>)
+ 800f68e:	785b      	ldrb	r3, [r3, #1]
+ 800f690:	041b      	lsls	r3, r3, #16
+ 800f692:	4319      	orrs	r1, r3
+ 800f694:	4b3c      	ldr	r3, [pc, #240]	; (800f788 <MX_LWIP_Init+0x248>)
+ 800f696:	789b      	ldrb	r3, [r3, #2]
+ 800f698:	021b      	lsls	r3, r3, #8
+ 800f69a:	430b      	orrs	r3, r1
+ 800f69c:	493a      	ldr	r1, [pc, #232]	; (800f788 <MX_LWIP_Init+0x248>)
+ 800f69e:	78c9      	ldrb	r1, [r1, #3]
+ 800f6a0:	430b      	orrs	r3, r1
+ 800f6a2:	0e1b      	lsrs	r3, r3, #24
+ 800f6a4:	4313      	orrs	r3, r2
+ 800f6a6:	4a3b      	ldr	r2, [pc, #236]	; (800f794 <MX_LWIP_Init+0x254>)
+ 800f6a8:	6013      	str	r3, [r2, #0]
+  IP4_ADDR(&gw, GATEWAY_ADDRESS[0], GATEWAY_ADDRESS[1], GATEWAY_ADDRESS[2], GATEWAY_ADDRESS[3]);
+ 800f6aa:	4b38      	ldr	r3, [pc, #224]	; (800f78c <MX_LWIP_Init+0x24c>)
+ 800f6ac:	781b      	ldrb	r3, [r3, #0]
+ 800f6ae:	061a      	lsls	r2, r3, #24
+ 800f6b0:	4b36      	ldr	r3, [pc, #216]	; (800f78c <MX_LWIP_Init+0x24c>)
+ 800f6b2:	785b      	ldrb	r3, [r3, #1]
+ 800f6b4:	041b      	lsls	r3, r3, #16
+ 800f6b6:	431a      	orrs	r2, r3
+ 800f6b8:	4b34      	ldr	r3, [pc, #208]	; (800f78c <MX_LWIP_Init+0x24c>)
+ 800f6ba:	789b      	ldrb	r3, [r3, #2]
+ 800f6bc:	021b      	lsls	r3, r3, #8
+ 800f6be:	4313      	orrs	r3, r2
+ 800f6c0:	4a32      	ldr	r2, [pc, #200]	; (800f78c <MX_LWIP_Init+0x24c>)
+ 800f6c2:	78d2      	ldrb	r2, [r2, #3]
+ 800f6c4:	4313      	orrs	r3, r2
+ 800f6c6:	061a      	lsls	r2, r3, #24
+ 800f6c8:	4b30      	ldr	r3, [pc, #192]	; (800f78c <MX_LWIP_Init+0x24c>)
+ 800f6ca:	781b      	ldrb	r3, [r3, #0]
+ 800f6cc:	0619      	lsls	r1, r3, #24
+ 800f6ce:	4b2f      	ldr	r3, [pc, #188]	; (800f78c <MX_LWIP_Init+0x24c>)
+ 800f6d0:	785b      	ldrb	r3, [r3, #1]
+ 800f6d2:	041b      	lsls	r3, r3, #16
+ 800f6d4:	4319      	orrs	r1, r3
+ 800f6d6:	4b2d      	ldr	r3, [pc, #180]	; (800f78c <MX_LWIP_Init+0x24c>)
+ 800f6d8:	789b      	ldrb	r3, [r3, #2]
+ 800f6da:	021b      	lsls	r3, r3, #8
+ 800f6dc:	430b      	orrs	r3, r1
+ 800f6de:	492b      	ldr	r1, [pc, #172]	; (800f78c <MX_LWIP_Init+0x24c>)
+ 800f6e0:	78c9      	ldrb	r1, [r1, #3]
+ 800f6e2:	430b      	orrs	r3, r1
+ 800f6e4:	021b      	lsls	r3, r3, #8
+ 800f6e6:	f403 037f 	and.w	r3, r3, #16711680	; 0xff0000
+ 800f6ea:	431a      	orrs	r2, r3
+ 800f6ec:	4b27      	ldr	r3, [pc, #156]	; (800f78c <MX_LWIP_Init+0x24c>)
+ 800f6ee:	781b      	ldrb	r3, [r3, #0]
+ 800f6f0:	0619      	lsls	r1, r3, #24
+ 800f6f2:	4b26      	ldr	r3, [pc, #152]	; (800f78c <MX_LWIP_Init+0x24c>)
+ 800f6f4:	785b      	ldrb	r3, [r3, #1]
+ 800f6f6:	041b      	lsls	r3, r3, #16
+ 800f6f8:	4319      	orrs	r1, r3
+ 800f6fa:	4b24      	ldr	r3, [pc, #144]	; (800f78c <MX_LWIP_Init+0x24c>)
+ 800f6fc:	789b      	ldrb	r3, [r3, #2]
+ 800f6fe:	021b      	lsls	r3, r3, #8
+ 800f700:	430b      	orrs	r3, r1
+ 800f702:	4922      	ldr	r1, [pc, #136]	; (800f78c <MX_LWIP_Init+0x24c>)
+ 800f704:	78c9      	ldrb	r1, [r1, #3]
+ 800f706:	430b      	orrs	r3, r1
+ 800f708:	0a1b      	lsrs	r3, r3, #8
+ 800f70a:	f403 437f 	and.w	r3, r3, #65280	; 0xff00
+ 800f70e:	431a      	orrs	r2, r3
+ 800f710:	4b1e      	ldr	r3, [pc, #120]	; (800f78c <MX_LWIP_Init+0x24c>)
+ 800f712:	781b      	ldrb	r3, [r3, #0]
+ 800f714:	0619      	lsls	r1, r3, #24
+ 800f716:	4b1d      	ldr	r3, [pc, #116]	; (800f78c <MX_LWIP_Init+0x24c>)
+ 800f718:	785b      	ldrb	r3, [r3, #1]
+ 800f71a:	041b      	lsls	r3, r3, #16
+ 800f71c:	4319      	orrs	r1, r3
+ 800f71e:	4b1b      	ldr	r3, [pc, #108]	; (800f78c <MX_LWIP_Init+0x24c>)
+ 800f720:	789b      	ldrb	r3, [r3, #2]
+ 800f722:	021b      	lsls	r3, r3, #8
+ 800f724:	430b      	orrs	r3, r1
+ 800f726:	4919      	ldr	r1, [pc, #100]	; (800f78c <MX_LWIP_Init+0x24c>)
+ 800f728:	78c9      	ldrb	r1, [r1, #3]
+ 800f72a:	430b      	orrs	r3, r1
+ 800f72c:	0e1b      	lsrs	r3, r3, #24
+ 800f72e:	4313      	orrs	r3, r2
+ 800f730:	4a19      	ldr	r2, [pc, #100]	; (800f798 <MX_LWIP_Init+0x258>)
+ 800f732:	6013      	str	r3, [r2, #0]
+
+  /* add the network interface (IPv4/IPv6) with RTOS */
+  netif_add(&gnetif, &ipaddr, &netmask, &gw, NULL, &ethernetif_init, &tcpip_input);
+ 800f734:	4b19      	ldr	r3, [pc, #100]	; (800f79c <MX_LWIP_Init+0x25c>)
+ 800f736:	9302      	str	r3, [sp, #8]
+ 800f738:	4b19      	ldr	r3, [pc, #100]	; (800f7a0 <MX_LWIP_Init+0x260>)
+ 800f73a:	9301      	str	r3, [sp, #4]
+ 800f73c:	2300      	movs	r3, #0
+ 800f73e:	9300      	str	r3, [sp, #0]
+ 800f740:	4b15      	ldr	r3, [pc, #84]	; (800f798 <MX_LWIP_Init+0x258>)
+ 800f742:	4a14      	ldr	r2, [pc, #80]	; (800f794 <MX_LWIP_Init+0x254>)
+ 800f744:	4912      	ldr	r1, [pc, #72]	; (800f790 <MX_LWIP_Init+0x250>)
+ 800f746:	4817      	ldr	r0, [pc, #92]	; (800f7a4 <MX_LWIP_Init+0x264>)
+ 800f748:	f007 fa6a 	bl	8016c20 <netif_add>
+
+  /* Registers the default network interface */
+  netif_set_default(&gnetif);
+ 800f74c:	4815      	ldr	r0, [pc, #84]	; (800f7a4 <MX_LWIP_Init+0x264>)
+ 800f74e:	f007 fcfb 	bl	8017148 <netif_set_default>
+
+  /* We must always bring the network interface up connection or not... */
+  netif_set_up(&gnetif);
+ 800f752:	4814      	ldr	r0, [pc, #80]	; (800f7a4 <MX_LWIP_Init+0x264>)
+ 800f754:	f007 fd1c 	bl	8017190 <netif_set_up>
+
+  /* Set the link callback function, this function is called on change of link status*/
+  netif_set_link_callback(&gnetif, ethernet_link_status_updated);
+ 800f758:	4913      	ldr	r1, [pc, #76]	; (800f7a8 <MX_LWIP_Init+0x268>)
+ 800f75a:	4812      	ldr	r0, [pc, #72]	; (800f7a4 <MX_LWIP_Init+0x264>)
+ 800f75c:	f007 fe1a 	bl	8017394 <netif_set_link_callback>
+
+  /* Create the Ethernet link handler thread */
+/* USER CODE BEGIN H7_OS_THREAD_DEF_CREATE_CMSIS_RTOS_V1 */
+  osThreadDef(EthLink, ethernet_link_thread, osPriorityBelowNormal, 0, configMINIMAL_STACK_SIZE *2);
+ 800f760:	4b12      	ldr	r3, [pc, #72]	; (800f7ac <MX_LWIP_Init+0x26c>)
+ 800f762:	1d3c      	adds	r4, r7, #4
+ 800f764:	461d      	mov	r5, r3
+ 800f766:	cd0f      	ldmia	r5!, {r0, r1, r2, r3}
+ 800f768:	c40f      	stmia	r4!, {r0, r1, r2, r3}
+ 800f76a:	e895 0007 	ldmia.w	r5, {r0, r1, r2}
+ 800f76e:	e884 0007 	stmia.w	r4, {r0, r1, r2}
+  osThreadCreate (osThread(EthLink), &gnetif);
+ 800f772:	1d3b      	adds	r3, r7, #4
+ 800f774:	490b      	ldr	r1, [pc, #44]	; (800f7a4 <MX_LWIP_Init+0x264>)
+ 800f776:	4618      	mov	r0, r3
+ 800f778:	f000 fdb6 	bl	80102e8 <osThreadCreate>
+/* USER CODE END H7_OS_THREAD_DEF_CREATE_CMSIS_RTOS_V1 */
+
+/* USER CODE BEGIN 3 */
+
+/* USER CODE END 3 */
+}
+ 800f77c:	bf00      	nop
+ 800f77e:	3720      	adds	r7, #32
+ 800f780:	46bd      	mov	sp, r7
+ 800f782:	bdb0      	pop	{r4, r5, r7, pc}
+ 800f784:	2400742c 	.word	0x2400742c
+ 800f788:	24007430 	.word	0x24007430
+ 800f78c:	24007434 	.word	0x24007434
+ 800f790:	24007420 	.word	0x24007420
+ 800f794:	24007424 	.word	0x24007424
+ 800f798:	24007428 	.word	0x24007428
+ 800f79c:	08015dbd 	.word	0x08015dbd
+ 800f7a0:	0800fc85 	.word	0x0800fc85
+ 800f7a4:	240073ec 	.word	0x240073ec
+ 800f7a8:	0800f7b1 	.word	0x0800f7b1
+ 800f7ac:	08023208 	.word	0x08023208
+
+0800f7b0 <ethernet_link_status_updated>:
+  * @brief  Notify the User about the network interface config status
+  * @param  netif: the network interface
+  * @retval None
+  */
+static void ethernet_link_status_updated(struct netif *netif)
+{
+ 800f7b0:	b480      	push	{r7}
+ 800f7b2:	b083      	sub	sp, #12
+ 800f7b4:	af00      	add	r7, sp, #0
+ 800f7b6:	6078      	str	r0, [r7, #4]
+  else /* netif is down */
+  {
+/* USER CODE BEGIN 6 */
+/* USER CODE END 6 */
+  }
+}
+ 800f7b8:	bf00      	nop
+ 800f7ba:	370c      	adds	r7, #12
+ 800f7bc:	46bd      	mov	sp, r7
+ 800f7be:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 800f7c2:	4770      	bx	lr
+
+0800f7c4 <HAL_ETH_RxCpltCallback>:
+  * @brief  Ethernet Rx Transfer completed callback
+  * @param  handlerEth: ETH handler
+  * @retval None
+  */
+void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *handlerEth)
+{
+ 800f7c4:	b580      	push	{r7, lr}
+ 800f7c6:	b082      	sub	sp, #8
+ 800f7c8:	af00      	add	r7, sp, #0
+ 800f7ca:	6078      	str	r0, [r7, #4]
+  osSemaphoreRelease(RxPktSemaphore);
+ 800f7cc:	4b04      	ldr	r3, [pc, #16]	; (800f7e0 <HAL_ETH_RxCpltCallback+0x1c>)
+ 800f7ce:	681b      	ldr	r3, [r3, #0]
+ 800f7d0:	4618      	mov	r0, r3
+ 800f7d2:	f000 ff05 	bl	80105e0 <osSemaphoreRelease>
+}
+ 800f7d6:	bf00      	nop
+ 800f7d8:	3708      	adds	r7, #8
+ 800f7da:	46bd      	mov	sp, r7
+ 800f7dc:	bd80      	pop	{r7, pc}
+ 800f7de:	bf00      	nop
+ 800f7e0:	2400bdc4 	.word	0x2400bdc4
+
+0800f7e4 <HAL_ETH_TxCpltCallback>:
+  * @brief  Ethernet Tx Transfer completed callback
+  * @param  handlerEth: ETH handler
+  * @retval None
+  */
+void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *handlerEth)
+{
+ 800f7e4:	b580      	push	{r7, lr}
+ 800f7e6:	b082      	sub	sp, #8
+ 800f7e8:	af00      	add	r7, sp, #0
+ 800f7ea:	6078      	str	r0, [r7, #4]
+  osSemaphoreRelease(TxPktSemaphore);
+ 800f7ec:	4b04      	ldr	r3, [pc, #16]	; (800f800 <HAL_ETH_TxCpltCallback+0x1c>)
+ 800f7ee:	681b      	ldr	r3, [r3, #0]
+ 800f7f0:	4618      	mov	r0, r3
+ 800f7f2:	f000 fef5 	bl	80105e0 <osSemaphoreRelease>
+}
+ 800f7f6:	bf00      	nop
+ 800f7f8:	3708      	adds	r7, #8
+ 800f7fa:	46bd      	mov	sp, r7
+ 800f7fc:	bd80      	pop	{r7, pc}
+ 800f7fe:	bf00      	nop
+ 800f800:	2400bdc8 	.word	0x2400bdc8
+
+0800f804 <HAL_ETH_ErrorCallback>:
+  * @brief  Ethernet DMA transfer error callback
+  * @param  handlerEth: ETH handler
+  * @retval None
+  */
+void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *handlerEth)
+{
+ 800f804:	b580      	push	{r7, lr}
+ 800f806:	b082      	sub	sp, #8
+ 800f808:	af00      	add	r7, sp, #0
+ 800f80a:	6078      	str	r0, [r7, #4]
+  if((HAL_ETH_GetDMAError(handlerEth) & ETH_DMACSR_RBU) == ETH_DMACSR_RBU)
+ 800f80c:	6878      	ldr	r0, [r7, #4]
+ 800f80e:	f7f5 fbe7 	bl	8004fe0 <HAL_ETH_GetDMAError>
+ 800f812:	4603      	mov	r3, r0
+ 800f814:	f003 0380 	and.w	r3, r3, #128	; 0x80
+ 800f818:	2b80      	cmp	r3, #128	; 0x80
+ 800f81a:	d104      	bne.n	800f826 <HAL_ETH_ErrorCallback+0x22>
+  {
+     osSemaphoreRelease(RxPktSemaphore);
+ 800f81c:	4b04      	ldr	r3, [pc, #16]	; (800f830 <HAL_ETH_ErrorCallback+0x2c>)
+ 800f81e:	681b      	ldr	r3, [r3, #0]
+ 800f820:	4618      	mov	r0, r3
+ 800f822:	f000 fedd 	bl	80105e0 <osSemaphoreRelease>
+  }
+}
+ 800f826:	bf00      	nop
+ 800f828:	3708      	adds	r7, #8
+ 800f82a:	46bd      	mov	sp, r7
+ 800f82c:	bd80      	pop	{r7, pc}
+ 800f82e:	bf00      	nop
+ 800f830:	2400bdc4 	.word	0x2400bdc4
+
+0800f834 <low_level_init>:
+ *
+ * @param netif the already initialized lwip network interface structure
+ *        for this ethernetif
+ */
+static void low_level_init(struct netif *netif)
+{
+ 800f834:	b5b0      	push	{r4, r5, r7, lr}
+ 800f836:	b0ac      	sub	sp, #176	; 0xb0
+ 800f838:	af00      	add	r7, sp, #0
+ 800f83a:	6078      	str	r0, [r7, #4]
+  HAL_StatusTypeDef hal_eth_init_status = HAL_OK;
+ 800f83c:	2300      	movs	r3, #0
+ 800f83e:	f887 30a7 	strb.w	r3, [r7, #167]	; 0xa7
+  uint32_t duplex, speed = 0;
+ 800f842:	2300      	movs	r3, #0
+ 800f844:	f8c7 30a8 	str.w	r3, [r7, #168]	; 0xa8
+  int32_t PHYLinkState = 0;
+ 800f848:	2300      	movs	r3, #0
+ 800f84a:	f8c7 30a0 	str.w	r3, [r7, #160]	; 0xa0
+  ETH_MACConfigTypeDef MACConf = {0};
+ 800f84e:	f107 033c 	add.w	r3, r7, #60	; 0x3c
+ 800f852:	2264      	movs	r2, #100	; 0x64
+ 800f854:	2100      	movs	r1, #0
+ 800f856:	4618      	mov	r0, r3
+ 800f858:	f012 fa42 	bl	8021ce0 <memset>
+  /* Start ETH HAL Init */
+
+   uint8_t MACAddr[6] ;
+  heth.Instance = ETH;
+ 800f85c:	4b8f      	ldr	r3, [pc, #572]	; (800fa9c <low_level_init+0x268>)
+ 800f85e:	4a90      	ldr	r2, [pc, #576]	; (800faa0 <low_level_init+0x26c>)
+ 800f860:	601a      	str	r2, [r3, #0]
+  MACAddr[0] = 0x00;
+ 800f862:	2300      	movs	r3, #0
+ 800f864:	f887 3034 	strb.w	r3, [r7, #52]	; 0x34
+  MACAddr[1] = 0x80;
+ 800f868:	2380      	movs	r3, #128	; 0x80
+ 800f86a:	f887 3035 	strb.w	r3, [r7, #53]	; 0x35
+  MACAddr[2] = 0xE1;
+ 800f86e:	23e1      	movs	r3, #225	; 0xe1
+ 800f870:	f887 3036 	strb.w	r3, [r7, #54]	; 0x36
+  MACAddr[3] = 0x00;
+ 800f874:	2300      	movs	r3, #0
+ 800f876:	f887 3037 	strb.w	r3, [r7, #55]	; 0x37
+  MACAddr[4] = 0x00;
+ 800f87a:	2300      	movs	r3, #0
+ 800f87c:	f887 3038 	strb.w	r3, [r7, #56]	; 0x38
+  MACAddr[5] = 0x00;
+ 800f880:	2300      	movs	r3, #0
+ 800f882:	f887 3039 	strb.w	r3, [r7, #57]	; 0x39
+  heth.Init.MACAddr = &MACAddr[0];
+ 800f886:	4a85      	ldr	r2, [pc, #532]	; (800fa9c <low_level_init+0x268>)
+ 800f888:	f107 0334 	add.w	r3, r7, #52	; 0x34
+ 800f88c:	6053      	str	r3, [r2, #4]
+  heth.Init.MediaInterface = HAL_ETH_RMII_MODE;
+ 800f88e:	4b83      	ldr	r3, [pc, #524]	; (800fa9c <low_level_init+0x268>)
+ 800f890:	2201      	movs	r2, #1
+ 800f892:	721a      	strb	r2, [r3, #8]
+  heth.Init.TxDesc = DMATxDscrTab;
+ 800f894:	4b81      	ldr	r3, [pc, #516]	; (800fa9c <low_level_init+0x268>)
+ 800f896:	4a83      	ldr	r2, [pc, #524]	; (800faa4 <low_level_init+0x270>)
+ 800f898:	60da      	str	r2, [r3, #12]
+  heth.Init.RxDesc = DMARxDscrTab;
+ 800f89a:	4b80      	ldr	r3, [pc, #512]	; (800fa9c <low_level_init+0x268>)
+ 800f89c:	4a82      	ldr	r2, [pc, #520]	; (800faa8 <low_level_init+0x274>)
+ 800f89e:	611a      	str	r2, [r3, #16]
+  heth.Init.RxBuffLen = 1536;
+ 800f8a0:	4b7e      	ldr	r3, [pc, #504]	; (800fa9c <low_level_init+0x268>)
+ 800f8a2:	f44f 62c0 	mov.w	r2, #1536	; 0x600
+ 800f8a6:	615a      	str	r2, [r3, #20]
+
+  /* USER CODE BEGIN MACADDRESS */
+
+  /* USER CODE END MACADDRESS */
+
+  hal_eth_init_status = HAL_ETH_Init(&heth);
+ 800f8a8:	487c      	ldr	r0, [pc, #496]	; (800fa9c <low_level_init+0x268>)
+ 800f8aa:	f7f4 fbb9 	bl	8004020 <HAL_ETH_Init>
+ 800f8ae:	4603      	mov	r3, r0
+ 800f8b0:	f887 30a7 	strb.w	r3, [r7, #167]	; 0xa7
+
+  memset(&TxConfig, 0 , sizeof(ETH_TxPacketConfig));
+ 800f8b4:	2238      	movs	r2, #56	; 0x38
+ 800f8b6:	2100      	movs	r1, #0
+ 800f8b8:	487c      	ldr	r0, [pc, #496]	; (800faac <low_level_init+0x278>)
+ 800f8ba:	f012 fa11 	bl	8021ce0 <memset>
+  TxConfig.Attributes = ETH_TX_PACKETS_FEATURES_CSUM | ETH_TX_PACKETS_FEATURES_CRCPAD;
+ 800f8be:	4b7b      	ldr	r3, [pc, #492]	; (800faac <low_level_init+0x278>)
+ 800f8c0:	2221      	movs	r2, #33	; 0x21
+ 800f8c2:	601a      	str	r2, [r3, #0]
+  TxConfig.ChecksumCtrl = ETH_CHECKSUM_IPHDR_PAYLOAD_INSERT_PHDR_CALC;
+ 800f8c4:	4b79      	ldr	r3, [pc, #484]	; (800faac <low_level_init+0x278>)
+ 800f8c6:	f44f 3240 	mov.w	r2, #196608	; 0x30000
+ 800f8ca:	615a      	str	r2, [r3, #20]
+  TxConfig.CRCPadCtrl = ETH_CRC_PAD_INSERT;
+ 800f8cc:	4b77      	ldr	r3, [pc, #476]	; (800faac <low_level_init+0x278>)
+ 800f8ce:	2200      	movs	r2, #0
+ 800f8d0:	611a      	str	r2, [r3, #16]
+
+  /* End ETH HAL Init */
+
+  /* Initialize the RX POOL */
+  LWIP_MEMPOOL_INIT(RX_POOL);
+ 800f8d2:	4877      	ldr	r0, [pc, #476]	; (800fab0 <low_level_init+0x27c>)
+ 800f8d4:	f007 f856 	bl	8016984 <memp_init_pool>
+
+#if LWIP_ARP || LWIP_ETHERNET
+
+  /* set MAC hardware address length */
+  netif->hwaddr_len = ETH_HWADDR_LEN;
+ 800f8d8:	687b      	ldr	r3, [r7, #4]
+ 800f8da:	2206      	movs	r2, #6
+ 800f8dc:	f883 202c 	strb.w	r2, [r3, #44]	; 0x2c
+
+  /* set MAC hardware address */
+  netif->hwaddr[0] =  heth.Init.MACAddr[0];
+ 800f8e0:	4b6e      	ldr	r3, [pc, #440]	; (800fa9c <low_level_init+0x268>)
+ 800f8e2:	685b      	ldr	r3, [r3, #4]
+ 800f8e4:	781a      	ldrb	r2, [r3, #0]
+ 800f8e6:	687b      	ldr	r3, [r7, #4]
+ 800f8e8:	f883 2026 	strb.w	r2, [r3, #38]	; 0x26
+  netif->hwaddr[1] =  heth.Init.MACAddr[1];
+ 800f8ec:	4b6b      	ldr	r3, [pc, #428]	; (800fa9c <low_level_init+0x268>)
+ 800f8ee:	685b      	ldr	r3, [r3, #4]
+ 800f8f0:	785a      	ldrb	r2, [r3, #1]
+ 800f8f2:	687b      	ldr	r3, [r7, #4]
+ 800f8f4:	f883 2027 	strb.w	r2, [r3, #39]	; 0x27
+  netif->hwaddr[2] =  heth.Init.MACAddr[2];
+ 800f8f8:	4b68      	ldr	r3, [pc, #416]	; (800fa9c <low_level_init+0x268>)
+ 800f8fa:	685b      	ldr	r3, [r3, #4]
+ 800f8fc:	789a      	ldrb	r2, [r3, #2]
+ 800f8fe:	687b      	ldr	r3, [r7, #4]
+ 800f900:	f883 2028 	strb.w	r2, [r3, #40]	; 0x28
+  netif->hwaddr[3] =  heth.Init.MACAddr[3];
+ 800f904:	4b65      	ldr	r3, [pc, #404]	; (800fa9c <low_level_init+0x268>)
+ 800f906:	685b      	ldr	r3, [r3, #4]
+ 800f908:	78da      	ldrb	r2, [r3, #3]
+ 800f90a:	687b      	ldr	r3, [r7, #4]
+ 800f90c:	f883 2029 	strb.w	r2, [r3, #41]	; 0x29
+  netif->hwaddr[4] =  heth.Init.MACAddr[4];
+ 800f910:	4b62      	ldr	r3, [pc, #392]	; (800fa9c <low_level_init+0x268>)
+ 800f912:	685b      	ldr	r3, [r3, #4]
+ 800f914:	791a      	ldrb	r2, [r3, #4]
+ 800f916:	687b      	ldr	r3, [r7, #4]
+ 800f918:	f883 202a 	strb.w	r2, [r3, #42]	; 0x2a
+  netif->hwaddr[5] =  heth.Init.MACAddr[5];
+ 800f91c:	4b5f      	ldr	r3, [pc, #380]	; (800fa9c <low_level_init+0x268>)
+ 800f91e:	685b      	ldr	r3, [r3, #4]
+ 800f920:	795a      	ldrb	r2, [r3, #5]
+ 800f922:	687b      	ldr	r3, [r7, #4]
+ 800f924:	f883 202b 	strb.w	r2, [r3, #43]	; 0x2b
+
+  /* maximum transfer unit */
+  netif->mtu = ETH_MAX_PAYLOAD;
+ 800f928:	687b      	ldr	r3, [r7, #4]
+ 800f92a:	f240 52dc 	movw	r2, #1500	; 0x5dc
+ 800f92e:	849a      	strh	r2, [r3, #36]	; 0x24
+
+  /* Accept broadcast address and ARP traffic */
+  /* don't set NETIF_FLAG_ETHARP if this device is not an ethernet one */
+  #if LWIP_ARP
+    netif->flags |= NETIF_FLAG_BROADCAST | NETIF_FLAG_ETHARP;
+ 800f930:	687b      	ldr	r3, [r7, #4]
+ 800f932:	f893 302d 	ldrb.w	r3, [r3, #45]	; 0x2d
+ 800f936:	f043 030a 	orr.w	r3, r3, #10
+ 800f93a:	b2da      	uxtb	r2, r3
+ 800f93c:	687b      	ldr	r3, [r7, #4]
+ 800f93e:	f883 202d 	strb.w	r2, [r3, #45]	; 0x2d
+  #else
+    netif->flags |= NETIF_FLAG_BROADCAST;
+  #endif /* LWIP_ARP */
+
+  /* create a binary semaphore used for informing ethernetif of frame reception */
+  osSemaphoreDef(RxSem);
+ 800f942:	2300      	movs	r3, #0
+ 800f944:	62fb      	str	r3, [r7, #44]	; 0x2c
+ 800f946:	2300      	movs	r3, #0
+ 800f948:	633b      	str	r3, [r7, #48]	; 0x30
+  RxPktSemaphore = osSemaphoreCreate(osSemaphore(RxSem), 1);
+ 800f94a:	f107 032c 	add.w	r3, r7, #44	; 0x2c
+ 800f94e:	2101      	movs	r1, #1
+ 800f950:	4618      	mov	r0, r3
+ 800f952:	f000 fdc5 	bl	80104e0 <osSemaphoreCreate>
+ 800f956:	4603      	mov	r3, r0
+ 800f958:	4a56      	ldr	r2, [pc, #344]	; (800fab4 <low_level_init+0x280>)
+ 800f95a:	6013      	str	r3, [r2, #0]
+
+  /* create a binary semaphore used for informing ethernetif of frame transmission */
+  osSemaphoreDef(TxSem);
+ 800f95c:	2300      	movs	r3, #0
+ 800f95e:	627b      	str	r3, [r7, #36]	; 0x24
+ 800f960:	2300      	movs	r3, #0
+ 800f962:	62bb      	str	r3, [r7, #40]	; 0x28
+  TxPktSemaphore = osSemaphoreCreate(osSemaphore(TxSem), 1);
+ 800f964:	f107 0324 	add.w	r3, r7, #36	; 0x24
+ 800f968:	2101      	movs	r1, #1
+ 800f96a:	4618      	mov	r0, r3
+ 800f96c:	f000 fdb8 	bl	80104e0 <osSemaphoreCreate>
+ 800f970:	4603      	mov	r3, r0
+ 800f972:	4a51      	ldr	r2, [pc, #324]	; (800fab8 <low_level_init+0x284>)
+ 800f974:	6013      	str	r3, [r2, #0]
+
+  /* Decrease the semaphore's initial count from 1 to 0 */
+  osSemaphoreWait(RxPktSemaphore, 0);
+ 800f976:	4b4f      	ldr	r3, [pc, #316]	; (800fab4 <low_level_init+0x280>)
+ 800f978:	681b      	ldr	r3, [r3, #0]
+ 800f97a:	2100      	movs	r1, #0
+ 800f97c:	4618      	mov	r0, r3
+ 800f97e:	f000 fde1 	bl	8010544 <osSemaphoreWait>
+  osSemaphoreWait(TxPktSemaphore, 0);
+ 800f982:	4b4d      	ldr	r3, [pc, #308]	; (800fab8 <low_level_init+0x284>)
+ 800f984:	681b      	ldr	r3, [r3, #0]
+ 800f986:	2100      	movs	r1, #0
+ 800f988:	4618      	mov	r0, r3
+ 800f98a:	f000 fddb 	bl	8010544 <osSemaphoreWait>
+
+  /* create the task that handles the ETH_MAC */
+/* USER CODE BEGIN OS_THREAD_DEF_CREATE_CMSIS_RTOS_V1 */
+  osThreadDef(EthIf, ethernetif_input, osPriorityRealtime, 0, INTERFACE_THREAD_STACK_SIZE);
+ 800f98e:	4b4b      	ldr	r3, [pc, #300]	; (800fabc <low_level_init+0x288>)
+ 800f990:	f107 0408 	add.w	r4, r7, #8
+ 800f994:	461d      	mov	r5, r3
+ 800f996:	cd0f      	ldmia	r5!, {r0, r1, r2, r3}
+ 800f998:	c40f      	stmia	r4!, {r0, r1, r2, r3}
+ 800f99a:	e895 0007 	ldmia.w	r5, {r0, r1, r2}
+ 800f99e:	e884 0007 	stmia.w	r4, {r0, r1, r2}
+  osThreadCreate (osThread(EthIf), netif);
+ 800f9a2:	f107 0308 	add.w	r3, r7, #8
+ 800f9a6:	6879      	ldr	r1, [r7, #4]
+ 800f9a8:	4618      	mov	r0, r3
+ 800f9aa:	f000 fc9d 	bl	80102e8 <osThreadCreate>
+
+/* USER CODE BEGIN PHY_PRE_CONFIG */
+
+/* USER CODE END PHY_PRE_CONFIG */
+  /* Set PHY IO functions */
+  LAN8742_RegisterBusIO(&LAN8742, &LAN8742_IOCtx);
+ 800f9ae:	4944      	ldr	r1, [pc, #272]	; (800fac0 <low_level_init+0x28c>)
+ 800f9b0:	4844      	ldr	r0, [pc, #272]	; (800fac4 <low_level_init+0x290>)
+ 800f9b2:	f7f2 fb26 	bl	8002002 <LAN8742_RegisterBusIO>
+
+  /* Initialize the LAN8742 ETH PHY */
+  LAN8742_Init(&LAN8742);
+ 800f9b6:	4843      	ldr	r0, [pc, #268]	; (800fac4 <low_level_init+0x290>)
+ 800f9b8:	f7f2 fb55 	bl	8002066 <LAN8742_Init>
+
+  if (hal_eth_init_status == HAL_OK)
+ 800f9bc:	f897 30a7 	ldrb.w	r3, [r7, #167]	; 0xa7
+ 800f9c0:	2b00      	cmp	r3, #0
+ 800f9c2:	d164      	bne.n	800fa8e <low_level_init+0x25a>
+  {
+    PHYLinkState = LAN8742_GetLinkState(&LAN8742);
+ 800f9c4:	483f      	ldr	r0, [pc, #252]	; (800fac4 <low_level_init+0x290>)
+ 800f9c6:	f7f2 fbf6 	bl	80021b6 <LAN8742_GetLinkState>
+ 800f9ca:	f8c7 00a0 	str.w	r0, [r7, #160]	; 0xa0
+
+    /* Get link state */
+    if(PHYLinkState <= LAN8742_STATUS_LINK_DOWN)
+ 800f9ce:	f8d7 30a0 	ldr.w	r3, [r7, #160]	; 0xa0
+ 800f9d2:	2b01      	cmp	r3, #1
+ 800f9d4:	dc06      	bgt.n	800f9e4 <low_level_init+0x1b0>
+    {
+      netif_set_link_down(netif);
+ 800f9d6:	6878      	ldr	r0, [r7, #4]
+ 800f9d8:	f007 fcac 	bl	8017334 <netif_set_link_down>
+      netif_set_down(netif);
+ 800f9dc:	6878      	ldr	r0, [r7, #4]
+ 800f9de:	f007 fc43 	bl	8017268 <netif_set_down>
+#endif /* LWIP_ARP || LWIP_ETHERNET */
+
+/* USER CODE BEGIN LOW_LEVEL_INIT */
+
+/* USER CODE END LOW_LEVEL_INIT */
+}
+ 800f9e2:	e056      	b.n	800fa92 <low_level_init+0x25e>
+      switch (PHYLinkState)
+ 800f9e4:	f8d7 30a0 	ldr.w	r3, [r7, #160]	; 0xa0
+ 800f9e8:	3b02      	subs	r3, #2
+ 800f9ea:	2b03      	cmp	r3, #3
+ 800f9ec:	d82a      	bhi.n	800fa44 <low_level_init+0x210>
+ 800f9ee:	a201      	add	r2, pc, #4	; (adr r2, 800f9f4 <low_level_init+0x1c0>)
+ 800f9f0:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
+ 800f9f4:	0800fa05 	.word	0x0800fa05
+ 800f9f8:	0800fa17 	.word	0x0800fa17
+ 800f9fc:	0800fa27 	.word	0x0800fa27
+ 800fa00:	0800fa37 	.word	0x0800fa37
+        duplex = ETH_FULLDUPLEX_MODE;
+ 800fa04:	f44f 5300 	mov.w	r3, #8192	; 0x2000
+ 800fa08:	f8c7 30ac 	str.w	r3, [r7, #172]	; 0xac
+        speed = ETH_SPEED_100M;
+ 800fa0c:	f44f 4380 	mov.w	r3, #16384	; 0x4000
+ 800fa10:	f8c7 30a8 	str.w	r3, [r7, #168]	; 0xa8
+        break;
+ 800fa14:	e01f      	b.n	800fa56 <low_level_init+0x222>
+        duplex = ETH_HALFDUPLEX_MODE;
+ 800fa16:	2300      	movs	r3, #0
+ 800fa18:	f8c7 30ac 	str.w	r3, [r7, #172]	; 0xac
+        speed = ETH_SPEED_100M;
+ 800fa1c:	f44f 4380 	mov.w	r3, #16384	; 0x4000
+ 800fa20:	f8c7 30a8 	str.w	r3, [r7, #168]	; 0xa8
+        break;
+ 800fa24:	e017      	b.n	800fa56 <low_level_init+0x222>
+        duplex = ETH_FULLDUPLEX_MODE;
+ 800fa26:	f44f 5300 	mov.w	r3, #8192	; 0x2000
+ 800fa2a:	f8c7 30ac 	str.w	r3, [r7, #172]	; 0xac
+        speed = ETH_SPEED_10M;
+ 800fa2e:	2300      	movs	r3, #0
+ 800fa30:	f8c7 30a8 	str.w	r3, [r7, #168]	; 0xa8
+        break;
+ 800fa34:	e00f      	b.n	800fa56 <low_level_init+0x222>
+        duplex = ETH_HALFDUPLEX_MODE;
+ 800fa36:	2300      	movs	r3, #0
+ 800fa38:	f8c7 30ac 	str.w	r3, [r7, #172]	; 0xac
+        speed = ETH_SPEED_10M;
+ 800fa3c:	2300      	movs	r3, #0
+ 800fa3e:	f8c7 30a8 	str.w	r3, [r7, #168]	; 0xa8
+        break;
+ 800fa42:	e008      	b.n	800fa56 <low_level_init+0x222>
+        duplex = ETH_FULLDUPLEX_MODE;
+ 800fa44:	f44f 5300 	mov.w	r3, #8192	; 0x2000
+ 800fa48:	f8c7 30ac 	str.w	r3, [r7, #172]	; 0xac
+        speed = ETH_SPEED_100M;
+ 800fa4c:	f44f 4380 	mov.w	r3, #16384	; 0x4000
+ 800fa50:	f8c7 30a8 	str.w	r3, [r7, #168]	; 0xa8
+        break;
+ 800fa54:	bf00      	nop
+    HAL_ETH_GetMACConfig(&heth, &MACConf);
+ 800fa56:	f107 033c 	add.w	r3, r7, #60	; 0x3c
+ 800fa5a:	4619      	mov	r1, r3
+ 800fa5c:	480f      	ldr	r0, [pc, #60]	; (800fa9c <low_level_init+0x268>)
+ 800fa5e:	f7f5 f879 	bl	8004b54 <HAL_ETH_GetMACConfig>
+    MACConf.DuplexMode = duplex;
+ 800fa62:	f8d7 30ac 	ldr.w	r3, [r7, #172]	; 0xac
+ 800fa66:	657b      	str	r3, [r7, #84]	; 0x54
+    MACConf.Speed = speed;
+ 800fa68:	f8d7 30a8 	ldr.w	r3, [r7, #168]	; 0xa8
+ 800fa6c:	653b      	str	r3, [r7, #80]	; 0x50
+    HAL_ETH_SetMACConfig(&heth, &MACConf);
+ 800fa6e:	f107 033c 	add.w	r3, r7, #60	; 0x3c
+ 800fa72:	4619      	mov	r1, r3
+ 800fa74:	4809      	ldr	r0, [pc, #36]	; (800fa9c <low_level_init+0x268>)
+ 800fa76:	f7f5 fa41 	bl	8004efc <HAL_ETH_SetMACConfig>
+    HAL_ETH_Start_IT(&heth);
+ 800fa7a:	4808      	ldr	r0, [pc, #32]	; (800fa9c <low_level_init+0x268>)
+ 800fa7c:	f7f4 fbb6 	bl	80041ec <HAL_ETH_Start_IT>
+    netif_set_up(netif);
+ 800fa80:	6878      	ldr	r0, [r7, #4]
+ 800fa82:	f007 fb85 	bl	8017190 <netif_set_up>
+    netif_set_link_up(netif);
+ 800fa86:	6878      	ldr	r0, [r7, #4]
+ 800fa88:	f007 fc20 	bl	80172cc <netif_set_link_up>
+}
+ 800fa8c:	e001      	b.n	800fa92 <low_level_init+0x25e>
+    Error_Handler();
+ 800fa8e:	f7f1 fd31 	bl	80014f4 <Error_Handler>
+}
+ 800fa92:	bf00      	nop
+ 800fa94:	37b0      	adds	r7, #176	; 0xb0
+ 800fa96:	46bd      	mov	sp, r7
+ 800fa98:	bdb0      	pop	{r4, r5, r7, pc}
+ 800fa9a:	bf00      	nop
+ 800fa9c:	2400bdcc 	.word	0x2400bdcc
+ 800faa0:	40028000 	.word	0x40028000
+ 800faa4:	30000100 	.word	0x30000100
+ 800faa8:	30000000 	.word	0x30000000
+ 800faac:	2400be7c 	.word	0x2400be7c
+ 800fab0:	08026b94 	.word	0x08026b94
+ 800fab4:	2400bdc4 	.word	0x2400bdc4
+ 800fab8:	2400bdc8 	.word	0x2400bdc8
+ 800fabc:	08023244 	.word	0x08023244
+ 800fac0:	24000024 	.word	0x24000024
+ 800fac4:	2400beb4 	.word	0x2400beb4
+
+0800fac8 <low_level_output>:
+ *       to become available since the stack doesn't retry to send a packet
+ *       dropped because of memory failure (except for the TCP timers).
+ */
+
+static err_t low_level_output(struct netif *netif, struct pbuf *p)
+{
+ 800fac8:	b580      	push	{r7, lr}
+ 800faca:	b092      	sub	sp, #72	; 0x48
+ 800facc:	af00      	add	r7, sp, #0
+ 800face:	6078      	str	r0, [r7, #4]
+ 800fad0:	6039      	str	r1, [r7, #0]
+  uint32_t i = 0U;
+ 800fad2:	2300      	movs	r3, #0
+ 800fad4:	647b      	str	r3, [r7, #68]	; 0x44
+  struct pbuf *q = NULL;
+ 800fad6:	2300      	movs	r3, #0
+ 800fad8:	643b      	str	r3, [r7, #64]	; 0x40
+  err_t errval = ERR_OK;
+ 800fada:	2300      	movs	r3, #0
+ 800fadc:	f887 303f 	strb.w	r3, [r7, #63]	; 0x3f
+  ETH_BufferTypeDef Txbuffer[ETH_TX_DESC_CNT] = {0};
+ 800fae0:	f107 030c 	add.w	r3, r7, #12
+ 800fae4:	2230      	movs	r2, #48	; 0x30
+ 800fae6:	2100      	movs	r1, #0
+ 800fae8:	4618      	mov	r0, r3
+ 800faea:	f012 f8f9 	bl	8021ce0 <memset>
+
+  memset(Txbuffer, 0 , ETH_TX_DESC_CNT*sizeof(ETH_BufferTypeDef));
+ 800faee:	f107 030c 	add.w	r3, r7, #12
+ 800faf2:	2230      	movs	r2, #48	; 0x30
+ 800faf4:	2100      	movs	r1, #0
+ 800faf6:	4618      	mov	r0, r3
+ 800faf8:	f012 f8f2 	bl	8021ce0 <memset>
+
+  for(q = p; q != NULL; q = q->next)
+ 800fafc:	683b      	ldr	r3, [r7, #0]
+ 800fafe:	643b      	str	r3, [r7, #64]	; 0x40
+ 800fb00:	e045      	b.n	800fb8e <low_level_output+0xc6>
+  {
+    if(i >= ETH_TX_DESC_CNT)
+ 800fb02:	6c7b      	ldr	r3, [r7, #68]	; 0x44
+ 800fb04:	2b03      	cmp	r3, #3
+ 800fb06:	d902      	bls.n	800fb0e <low_level_output+0x46>
+      return ERR_IF;
+ 800fb08:	f06f 030b 	mvn.w	r3, #11
+ 800fb0c:	e06c      	b.n	800fbe8 <low_level_output+0x120>
+
+    Txbuffer[i].buffer = q->payload;
+ 800fb0e:	6c3b      	ldr	r3, [r7, #64]	; 0x40
+ 800fb10:	6859      	ldr	r1, [r3, #4]
+ 800fb12:	6c7a      	ldr	r2, [r7, #68]	; 0x44
+ 800fb14:	4613      	mov	r3, r2
+ 800fb16:	005b      	lsls	r3, r3, #1
+ 800fb18:	4413      	add	r3, r2
+ 800fb1a:	009b      	lsls	r3, r3, #2
+ 800fb1c:	3348      	adds	r3, #72	; 0x48
+ 800fb1e:	443b      	add	r3, r7
+ 800fb20:	3b3c      	subs	r3, #60	; 0x3c
+ 800fb22:	6019      	str	r1, [r3, #0]
+    Txbuffer[i].len = q->len;
+ 800fb24:	6c3b      	ldr	r3, [r7, #64]	; 0x40
+ 800fb26:	895b      	ldrh	r3, [r3, #10]
+ 800fb28:	4619      	mov	r1, r3
+ 800fb2a:	6c7a      	ldr	r2, [r7, #68]	; 0x44
+ 800fb2c:	4613      	mov	r3, r2
+ 800fb2e:	005b      	lsls	r3, r3, #1
+ 800fb30:	4413      	add	r3, r2
+ 800fb32:	009b      	lsls	r3, r3, #2
+ 800fb34:	3348      	adds	r3, #72	; 0x48
+ 800fb36:	443b      	add	r3, r7
+ 800fb38:	3b38      	subs	r3, #56	; 0x38
+ 800fb3a:	6019      	str	r1, [r3, #0]
+
+    if(i>0)
+ 800fb3c:	6c7b      	ldr	r3, [r7, #68]	; 0x44
+ 800fb3e:	2b00      	cmp	r3, #0
+ 800fb40:	d011      	beq.n	800fb66 <low_level_output+0x9e>
+    {
+      Txbuffer[i-1].next = &Txbuffer[i];
+ 800fb42:	6c7b      	ldr	r3, [r7, #68]	; 0x44
+ 800fb44:	1e5a      	subs	r2, r3, #1
+ 800fb46:	f107 000c 	add.w	r0, r7, #12
+ 800fb4a:	6c79      	ldr	r1, [r7, #68]	; 0x44
+ 800fb4c:	460b      	mov	r3, r1
+ 800fb4e:	005b      	lsls	r3, r3, #1
+ 800fb50:	440b      	add	r3, r1
+ 800fb52:	009b      	lsls	r3, r3, #2
+ 800fb54:	18c1      	adds	r1, r0, r3
+ 800fb56:	4613      	mov	r3, r2
+ 800fb58:	005b      	lsls	r3, r3, #1
+ 800fb5a:	4413      	add	r3, r2
+ 800fb5c:	009b      	lsls	r3, r3, #2
+ 800fb5e:	3348      	adds	r3, #72	; 0x48
+ 800fb60:	443b      	add	r3, r7
+ 800fb62:	3b34      	subs	r3, #52	; 0x34
+ 800fb64:	6019      	str	r1, [r3, #0]
+    }
+
+    if(q->next == NULL)
+ 800fb66:	6c3b      	ldr	r3, [r7, #64]	; 0x40
+ 800fb68:	681b      	ldr	r3, [r3, #0]
+ 800fb6a:	2b00      	cmp	r3, #0
+ 800fb6c:	d109      	bne.n	800fb82 <low_level_output+0xba>
+    {
+      Txbuffer[i].next = NULL;
+ 800fb6e:	6c7a      	ldr	r2, [r7, #68]	; 0x44
+ 800fb70:	4613      	mov	r3, r2
+ 800fb72:	005b      	lsls	r3, r3, #1
+ 800fb74:	4413      	add	r3, r2
+ 800fb76:	009b      	lsls	r3, r3, #2
+ 800fb78:	3348      	adds	r3, #72	; 0x48
+ 800fb7a:	443b      	add	r3, r7
+ 800fb7c:	3b34      	subs	r3, #52	; 0x34
+ 800fb7e:	2200      	movs	r2, #0
+ 800fb80:	601a      	str	r2, [r3, #0]
+    }
+
+    i++;
+ 800fb82:	6c7b      	ldr	r3, [r7, #68]	; 0x44
+ 800fb84:	3301      	adds	r3, #1
+ 800fb86:	647b      	str	r3, [r7, #68]	; 0x44
+  for(q = p; q != NULL; q = q->next)
+ 800fb88:	6c3b      	ldr	r3, [r7, #64]	; 0x40
+ 800fb8a:	681b      	ldr	r3, [r3, #0]
+ 800fb8c:	643b      	str	r3, [r7, #64]	; 0x40
+ 800fb8e:	6c3b      	ldr	r3, [r7, #64]	; 0x40
+ 800fb90:	2b00      	cmp	r3, #0
+ 800fb92:	d1b6      	bne.n	800fb02 <low_level_output+0x3a>
+  }
+
+  TxConfig.Length = p->tot_len;
+ 800fb94:	683b      	ldr	r3, [r7, #0]
+ 800fb96:	891b      	ldrh	r3, [r3, #8]
+ 800fb98:	461a      	mov	r2, r3
+ 800fb9a:	4b15      	ldr	r3, [pc, #84]	; (800fbf0 <low_level_output+0x128>)
+ 800fb9c:	605a      	str	r2, [r3, #4]
+  TxConfig.TxBuffer = Txbuffer;
+ 800fb9e:	4a14      	ldr	r2, [pc, #80]	; (800fbf0 <low_level_output+0x128>)
+ 800fba0:	f107 030c 	add.w	r3, r7, #12
+ 800fba4:	6093      	str	r3, [r2, #8]
+  TxConfig.pData = p;
+ 800fba6:	4a12      	ldr	r2, [pc, #72]	; (800fbf0 <low_level_output+0x128>)
+ 800fba8:	683b      	ldr	r3, [r7, #0]
+ 800fbaa:	6353      	str	r3, [r2, #52]	; 0x34
+
+  pbuf_ref(p);
+ 800fbac:	6838      	ldr	r0, [r7, #0]
+ 800fbae:	f008 f849 	bl	8017c44 <pbuf_ref>
+
+  if (HAL_ETH_Transmit_IT(&heth, &TxConfig) == HAL_OK) {
+ 800fbb2:	490f      	ldr	r1, [pc, #60]	; (800fbf0 <low_level_output+0x128>)
+ 800fbb4:	480f      	ldr	r0, [pc, #60]	; (800fbf4 <low_level_output+0x12c>)
+ 800fbb6:	f7f4 fc1d 	bl	80043f4 <HAL_ETH_Transmit_IT>
+ 800fbba:	4603      	mov	r3, r0
+ 800fbbc:	2b00      	cmp	r3, #0
+ 800fbbe:	d10e      	bne.n	800fbde <low_level_output+0x116>
+    while(osSemaphoreWait(TxPktSemaphore, TIME_WAITING_FOR_INPUT)!=osOK)
+ 800fbc0:	bf00      	nop
+ 800fbc2:	4b0d      	ldr	r3, [pc, #52]	; (800fbf8 <low_level_output+0x130>)
+ 800fbc4:	681b      	ldr	r3, [r3, #0]
+ 800fbc6:	f04f 31ff 	mov.w	r1, #4294967295
+ 800fbca:	4618      	mov	r0, r3
+ 800fbcc:	f000 fcba 	bl	8010544 <osSemaphoreWait>
+ 800fbd0:	4603      	mov	r3, r0
+ 800fbd2:	2b00      	cmp	r3, #0
+ 800fbd4:	d1f5      	bne.n	800fbc2 <low_level_output+0xfa>
+
+    {
+    }
+
+    HAL_ETH_ReleaseTxPacket(&heth);
+ 800fbd6:	4807      	ldr	r0, [pc, #28]	; (800fbf4 <low_level_output+0x12c>)
+ 800fbd8:	f7f4 fd8b 	bl	80046f2 <HAL_ETH_ReleaseTxPacket>
+ 800fbdc:	e002      	b.n	800fbe4 <low_level_output+0x11c>
+  } else {
+    pbuf_free(p);
+ 800fbde:	6838      	ldr	r0, [r7, #0]
+ 800fbe0:	f007 ff8a 	bl	8017af8 <pbuf_free>
+  }
+
+  return errval;
+ 800fbe4:	f997 303f 	ldrsb.w	r3, [r7, #63]	; 0x3f
+}
+ 800fbe8:	4618      	mov	r0, r3
+ 800fbea:	3748      	adds	r7, #72	; 0x48
+ 800fbec:	46bd      	mov	sp, r7
+ 800fbee:	bd80      	pop	{r7, pc}
+ 800fbf0:	2400be7c 	.word	0x2400be7c
+ 800fbf4:	2400bdcc 	.word	0x2400bdcc
+ 800fbf8:	2400bdc8 	.word	0x2400bdc8
+
+0800fbfc <low_level_input>:
+ * @param netif the lwip network interface structure for this ethernetif
+ * @return a pbuf filled with the received packet (including MAC header)
+ *         NULL on memory error
+   */
+static struct pbuf * low_level_input(struct netif *netif)
+{
+ 800fbfc:	b580      	push	{r7, lr}
+ 800fbfe:	b084      	sub	sp, #16
+ 800fc00:	af00      	add	r7, sp, #0
+ 800fc02:	6078      	str	r0, [r7, #4]
+  struct pbuf *p = NULL;
+ 800fc04:	2300      	movs	r3, #0
+ 800fc06:	60fb      	str	r3, [r7, #12]
+
+  if(RxAllocStatus == RX_ALLOC_OK)
+ 800fc08:	4b07      	ldr	r3, [pc, #28]	; (800fc28 <low_level_input+0x2c>)
+ 800fc0a:	781b      	ldrb	r3, [r3, #0]
+ 800fc0c:	2b00      	cmp	r3, #0
+ 800fc0e:	d105      	bne.n	800fc1c <low_level_input+0x20>
+  {
+    HAL_ETH_ReadData(&heth, (void **)&p);
+ 800fc10:	f107 030c 	add.w	r3, r7, #12
+ 800fc14:	4619      	mov	r1, r3
+ 800fc16:	4805      	ldr	r0, [pc, #20]	; (800fc2c <low_level_input+0x30>)
+ 800fc18:	f7f4 fc3d 	bl	8004496 <HAL_ETH_ReadData>
+  }
+
+  return p;
+ 800fc1c:	68fb      	ldr	r3, [r7, #12]
+}
+ 800fc1e:	4618      	mov	r0, r3
+ 800fc20:	3710      	adds	r7, #16
+ 800fc22:	46bd      	mov	sp, r7
+ 800fc24:	bd80      	pop	{r7, pc}
+ 800fc26:	bf00      	nop
+ 800fc28:	2400bdc0 	.word	0x2400bdc0
+ 800fc2c:	2400bdcc 	.word	0x2400bdcc
+
+0800fc30 <ethernetif_input>:
+ * the appropriate input function is called.
+ *
+ * @param netif the lwip network interface structure for this ethernetif
+ */
+static void ethernetif_input(void const * argument)
+{
+ 800fc30:	b580      	push	{r7, lr}
+ 800fc32:	b084      	sub	sp, #16
+ 800fc34:	af00      	add	r7, sp, #0
+ 800fc36:	6078      	str	r0, [r7, #4]
+  struct pbuf *p = NULL;
+ 800fc38:	2300      	movs	r3, #0
+ 800fc3a:	60fb      	str	r3, [r7, #12]
+  struct netif *netif = (struct netif *) argument;
+ 800fc3c:	687b      	ldr	r3, [r7, #4]
+ 800fc3e:	60bb      	str	r3, [r7, #8]
+
+  for( ;; )
+  {
+    if (osSemaphoreWait(RxPktSemaphore, TIME_WAITING_FOR_INPUT) == osOK)
+ 800fc40:	4b0f      	ldr	r3, [pc, #60]	; (800fc80 <ethernetif_input+0x50>)
+ 800fc42:	681b      	ldr	r3, [r3, #0]
+ 800fc44:	f04f 31ff 	mov.w	r1, #4294967295
+ 800fc48:	4618      	mov	r0, r3
+ 800fc4a:	f000 fc7b 	bl	8010544 <osSemaphoreWait>
+ 800fc4e:	4603      	mov	r3, r0
+ 800fc50:	2b00      	cmp	r3, #0
+ 800fc52:	d1f5      	bne.n	800fc40 <ethernetif_input+0x10>
+    {
+      do
+      {
+        p = low_level_input( netif );
+ 800fc54:	68b8      	ldr	r0, [r7, #8]
+ 800fc56:	f7ff ffd1 	bl	800fbfc <low_level_input>
+ 800fc5a:	60f8      	str	r0, [r7, #12]
+        if (p != NULL)
+ 800fc5c:	68fb      	ldr	r3, [r7, #12]
+ 800fc5e:	2b00      	cmp	r3, #0
+ 800fc60:	d00a      	beq.n	800fc78 <ethernetif_input+0x48>
+        {
+          if (netif->input( p, netif) != ERR_OK )
+ 800fc62:	68bb      	ldr	r3, [r7, #8]
+ 800fc64:	691b      	ldr	r3, [r3, #16]
+ 800fc66:	68b9      	ldr	r1, [r7, #8]
+ 800fc68:	68f8      	ldr	r0, [r7, #12]
+ 800fc6a:	4798      	blx	r3
+ 800fc6c:	4603      	mov	r3, r0
+ 800fc6e:	2b00      	cmp	r3, #0
+ 800fc70:	d002      	beq.n	800fc78 <ethernetif_input+0x48>
+          {
+            pbuf_free(p);
+ 800fc72:	68f8      	ldr	r0, [r7, #12]
+ 800fc74:	f007 ff40 	bl	8017af8 <pbuf_free>
+          }
+        }
+      } while(p!=NULL);
+ 800fc78:	68fb      	ldr	r3, [r7, #12]
+ 800fc7a:	2b00      	cmp	r3, #0
+ 800fc7c:	d1ea      	bne.n	800fc54 <ethernetif_input+0x24>
+    if (osSemaphoreWait(RxPktSemaphore, TIME_WAITING_FOR_INPUT) == osOK)
+ 800fc7e:	e7df      	b.n	800fc40 <ethernetif_input+0x10>
+ 800fc80:	2400bdc4 	.word	0x2400bdc4
+
+0800fc84 <ethernetif_init>:
+ * @return ERR_OK if the loopif is initialized
+ *         ERR_MEM if private data couldn't be allocated
+ *         any other err_t on error
+ */
+err_t ethernetif_init(struct netif *netif)
+{
+ 800fc84:	b580      	push	{r7, lr}
+ 800fc86:	b082      	sub	sp, #8
+ 800fc88:	af00      	add	r7, sp, #0
+ 800fc8a:	6078      	str	r0, [r7, #4]
+  LWIP_ASSERT("netif != NULL", (netif != NULL));
+ 800fc8c:	687b      	ldr	r3, [r7, #4]
+ 800fc8e:	2b00      	cmp	r3, #0
+ 800fc90:	d106      	bne.n	800fca0 <ethernetif_init+0x1c>
+ 800fc92:	4b0e      	ldr	r3, [pc, #56]	; (800fccc <ethernetif_init+0x48>)
+ 800fc94:	f240 12f9 	movw	r2, #505	; 0x1f9
+ 800fc98:	490d      	ldr	r1, [pc, #52]	; (800fcd0 <ethernetif_init+0x4c>)
+ 800fc9a:	480e      	ldr	r0, [pc, #56]	; (800fcd4 <ethernetif_init+0x50>)
+ 800fc9c:	f011 fe74 	bl	8021988 <iprintf>
+   * The last argument should be replaced with your link speed, in units
+   * of bits per second.
+   */
+  // MIB2_INIT_NETIF(netif, snmp_ifType_ethernet_csmacd, LINK_SPEED_OF_YOUR_NETIF_IN_BPS);
+
+  netif->name[0] = IFNAME0;
+ 800fca0:	687b      	ldr	r3, [r7, #4]
+ 800fca2:	2273      	movs	r2, #115	; 0x73
+ 800fca4:	f883 202e 	strb.w	r2, [r3, #46]	; 0x2e
+  netif->name[1] = IFNAME1;
+ 800fca8:	687b      	ldr	r3, [r7, #4]
+ 800fcaa:	2274      	movs	r2, #116	; 0x74
+ 800fcac:	f883 202f 	strb.w	r2, [r3, #47]	; 0x2f
+   * is available...) */
+
+#if LWIP_IPV4
+#if LWIP_ARP || LWIP_ETHERNET
+#if LWIP_ARP
+  netif->output = etharp_output;
+ 800fcb0:	687b      	ldr	r3, [r7, #4]
+ 800fcb2:	4a09      	ldr	r2, [pc, #36]	; (800fcd8 <ethernetif_init+0x54>)
+ 800fcb4:	615a      	str	r2, [r3, #20]
+
+#if LWIP_IPV6
+  netif->output_ip6 = ethip6_output;
+#endif /* LWIP_IPV6 */
+
+  netif->linkoutput = low_level_output;
+ 800fcb6:	687b      	ldr	r3, [r7, #4]
+ 800fcb8:	4a08      	ldr	r2, [pc, #32]	; (800fcdc <ethernetif_init+0x58>)
+ 800fcba:	619a      	str	r2, [r3, #24]
+
+  /* initialize the hardware */
+  low_level_init(netif);
+ 800fcbc:	6878      	ldr	r0, [r7, #4]
+ 800fcbe:	f7ff fdb9 	bl	800f834 <low_level_init>
+
+  return ERR_OK;
+ 800fcc2:	2300      	movs	r3, #0
+}
+ 800fcc4:	4618      	mov	r0, r3
+ 800fcc6:	3708      	adds	r7, #8
+ 800fcc8:	46bd      	mov	sp, r7
+ 800fcca:	bd80      	pop	{r7, pc}
+ 800fccc:	08023260 	.word	0x08023260
+ 800fcd0:	0802327c 	.word	0x0802327c
+ 800fcd4:	0802328c 	.word	0x0802328c
+ 800fcd8:	0801f585 	.word	0x0801f585
+ 800fcdc:	0800fac9 	.word	0x0800fac9
+
+0800fce0 <pbuf_free_custom>:
+  * @brief  Custom Rx pbuf free callback
+  * @param  pbuf: pbuf to be freed
+  * @retval None
+  */
+void pbuf_free_custom(struct pbuf *p)
+{
+ 800fce0:	b580      	push	{r7, lr}
+ 800fce2:	b084      	sub	sp, #16
+ 800fce4:	af00      	add	r7, sp, #0
+ 800fce6:	6078      	str	r0, [r7, #4]
+  struct pbuf_custom* custom_pbuf = (struct pbuf_custom*)p;
+ 800fce8:	687b      	ldr	r3, [r7, #4]
+ 800fcea:	60fb      	str	r3, [r7, #12]
+  LWIP_MEMPOOL_FREE(RX_POOL, custom_pbuf);
+ 800fcec:	68f9      	ldr	r1, [r7, #12]
+ 800fcee:	4809      	ldr	r0, [pc, #36]	; (800fd14 <pbuf_free_custom+0x34>)
+ 800fcf0:	f006 ff40 	bl	8016b74 <memp_free_pool>
+
+  /* If the Rx Buffer Pool was exhausted, signal the ethernetif_input task to
+   * call HAL_ETH_GetRxDataBuffer to rebuild the Rx descriptors. */
+
+  if (RxAllocStatus == RX_ALLOC_ERROR)
+ 800fcf4:	4b08      	ldr	r3, [pc, #32]	; (800fd18 <pbuf_free_custom+0x38>)
+ 800fcf6:	781b      	ldrb	r3, [r3, #0]
+ 800fcf8:	2b01      	cmp	r3, #1
+ 800fcfa:	d107      	bne.n	800fd0c <pbuf_free_custom+0x2c>
+  {
+    RxAllocStatus = RX_ALLOC_OK;
+ 800fcfc:	4b06      	ldr	r3, [pc, #24]	; (800fd18 <pbuf_free_custom+0x38>)
+ 800fcfe:	2200      	movs	r2, #0
+ 800fd00:	701a      	strb	r2, [r3, #0]
+    osSemaphoreRelease(RxPktSemaphore);
+ 800fd02:	4b06      	ldr	r3, [pc, #24]	; (800fd1c <pbuf_free_custom+0x3c>)
+ 800fd04:	681b      	ldr	r3, [r3, #0]
+ 800fd06:	4618      	mov	r0, r3
+ 800fd08:	f000 fc6a 	bl	80105e0 <osSemaphoreRelease>
+  }
+}
+ 800fd0c:	bf00      	nop
+ 800fd0e:	3710      	adds	r7, #16
+ 800fd10:	46bd      	mov	sp, r7
+ 800fd12:	bd80      	pop	{r7, pc}
+ 800fd14:	08026b94 	.word	0x08026b94
+ 800fd18:	2400bdc0 	.word	0x2400bdc0
+ 800fd1c:	2400bdc4 	.word	0x2400bdc4
+
+0800fd20 <sys_now>:
+*         when LWIP_TIMERS == 1 and NO_SYS == 1
+* @param  None
+* @retval Current Time value
+*/
+u32_t sys_now(void)
+{
+ 800fd20:	b580      	push	{r7, lr}
+ 800fd22:	af00      	add	r7, sp, #0
+  return HAL_GetTick();
+ 800fd24:	f7f2 fb1e 	bl	8002364 <HAL_GetTick>
+ 800fd28:	4603      	mov	r3, r0
+}
+ 800fd2a:	4618      	mov	r0, r3
+ 800fd2c:	bd80      	pop	{r7, pc}
+	...
+
+0800fd30 <HAL_ETH_MspInit>:
+  * @param  ethHandle: ETH handle
+  * @retval None
+  */
+
+void HAL_ETH_MspInit(ETH_HandleTypeDef* ethHandle)
+{
+ 800fd30:	b580      	push	{r7, lr}
+ 800fd32:	b08e      	sub	sp, #56	; 0x38
+ 800fd34:	af00      	add	r7, sp, #0
+ 800fd36:	6078      	str	r0, [r7, #4]
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+ 800fd38:	f107 0324 	add.w	r3, r7, #36	; 0x24
+ 800fd3c:	2200      	movs	r2, #0
+ 800fd3e:	601a      	str	r2, [r3, #0]
+ 800fd40:	605a      	str	r2, [r3, #4]
+ 800fd42:	609a      	str	r2, [r3, #8]
+ 800fd44:	60da      	str	r2, [r3, #12]
+ 800fd46:	611a      	str	r2, [r3, #16]
+  if(ethHandle->Instance==ETH)
+ 800fd48:	687b      	ldr	r3, [r7, #4]
+ 800fd4a:	681b      	ldr	r3, [r3, #0]
+ 800fd4c:	4a4d      	ldr	r2, [pc, #308]	; (800fe84 <HAL_ETH_MspInit+0x154>)
+ 800fd4e:	4293      	cmp	r3, r2
+ 800fd50:	f040 8093 	bne.w	800fe7a <HAL_ETH_MspInit+0x14a>
+  {
+  /* USER CODE BEGIN ETH_MspInit 0 */
+
+  /* USER CODE END ETH_MspInit 0 */
+    /* Enable Peripheral clock */
+    __HAL_RCC_ETH1MAC_CLK_ENABLE();
+ 800fd54:	4b4c      	ldr	r3, [pc, #304]	; (800fe88 <HAL_ETH_MspInit+0x158>)
+ 800fd56:	f8d3 30d8 	ldr.w	r3, [r3, #216]	; 0xd8
+ 800fd5a:	4a4b      	ldr	r2, [pc, #300]	; (800fe88 <HAL_ETH_MspInit+0x158>)
+ 800fd5c:	f443 4300 	orr.w	r3, r3, #32768	; 0x8000
+ 800fd60:	f8c2 30d8 	str.w	r3, [r2, #216]	; 0xd8
+ 800fd64:	4b48      	ldr	r3, [pc, #288]	; (800fe88 <HAL_ETH_MspInit+0x158>)
+ 800fd66:	f8d3 30d8 	ldr.w	r3, [r3, #216]	; 0xd8
+ 800fd6a:	f403 4300 	and.w	r3, r3, #32768	; 0x8000
+ 800fd6e:	623b      	str	r3, [r7, #32]
+ 800fd70:	6a3b      	ldr	r3, [r7, #32]
+    __HAL_RCC_ETH1TX_CLK_ENABLE();
+ 800fd72:	4b45      	ldr	r3, [pc, #276]	; (800fe88 <HAL_ETH_MspInit+0x158>)
+ 800fd74:	f8d3 30d8 	ldr.w	r3, [r3, #216]	; 0xd8
+ 800fd78:	4a43      	ldr	r2, [pc, #268]	; (800fe88 <HAL_ETH_MspInit+0x158>)
+ 800fd7a:	f443 3380 	orr.w	r3, r3, #65536	; 0x10000
+ 800fd7e:	f8c2 30d8 	str.w	r3, [r2, #216]	; 0xd8
+ 800fd82:	4b41      	ldr	r3, [pc, #260]	; (800fe88 <HAL_ETH_MspInit+0x158>)
+ 800fd84:	f8d3 30d8 	ldr.w	r3, [r3, #216]	; 0xd8
+ 800fd88:	f403 3380 	and.w	r3, r3, #65536	; 0x10000
+ 800fd8c:	61fb      	str	r3, [r7, #28]
+ 800fd8e:	69fb      	ldr	r3, [r7, #28]
+    __HAL_RCC_ETH1RX_CLK_ENABLE();
+ 800fd90:	4b3d      	ldr	r3, [pc, #244]	; (800fe88 <HAL_ETH_MspInit+0x158>)
+ 800fd92:	f8d3 30d8 	ldr.w	r3, [r3, #216]	; 0xd8
+ 800fd96:	4a3c      	ldr	r2, [pc, #240]	; (800fe88 <HAL_ETH_MspInit+0x158>)
+ 800fd98:	f443 3300 	orr.w	r3, r3, #131072	; 0x20000
+ 800fd9c:	f8c2 30d8 	str.w	r3, [r2, #216]	; 0xd8
+ 800fda0:	4b39      	ldr	r3, [pc, #228]	; (800fe88 <HAL_ETH_MspInit+0x158>)
+ 800fda2:	f8d3 30d8 	ldr.w	r3, [r3, #216]	; 0xd8
+ 800fda6:	f403 3300 	and.w	r3, r3, #131072	; 0x20000
+ 800fdaa:	61bb      	str	r3, [r7, #24]
+ 800fdac:	69bb      	ldr	r3, [r7, #24]
+
+    __HAL_RCC_GPIOC_CLK_ENABLE();
+ 800fdae:	4b36      	ldr	r3, [pc, #216]	; (800fe88 <HAL_ETH_MspInit+0x158>)
+ 800fdb0:	f8d3 30e0 	ldr.w	r3, [r3, #224]	; 0xe0
+ 800fdb4:	4a34      	ldr	r2, [pc, #208]	; (800fe88 <HAL_ETH_MspInit+0x158>)
+ 800fdb6:	f043 0304 	orr.w	r3, r3, #4
+ 800fdba:	f8c2 30e0 	str.w	r3, [r2, #224]	; 0xe0
+ 800fdbe:	4b32      	ldr	r3, [pc, #200]	; (800fe88 <HAL_ETH_MspInit+0x158>)
+ 800fdc0:	f8d3 30e0 	ldr.w	r3, [r3, #224]	; 0xe0
+ 800fdc4:	f003 0304 	and.w	r3, r3, #4
+ 800fdc8:	617b      	str	r3, [r7, #20]
+ 800fdca:	697b      	ldr	r3, [r7, #20]
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+ 800fdcc:	4b2e      	ldr	r3, [pc, #184]	; (800fe88 <HAL_ETH_MspInit+0x158>)
+ 800fdce:	f8d3 30e0 	ldr.w	r3, [r3, #224]	; 0xe0
+ 800fdd2:	4a2d      	ldr	r2, [pc, #180]	; (800fe88 <HAL_ETH_MspInit+0x158>)
+ 800fdd4:	f043 0301 	orr.w	r3, r3, #1
+ 800fdd8:	f8c2 30e0 	str.w	r3, [r2, #224]	; 0xe0
+ 800fddc:	4b2a      	ldr	r3, [pc, #168]	; (800fe88 <HAL_ETH_MspInit+0x158>)
+ 800fdde:	f8d3 30e0 	ldr.w	r3, [r3, #224]	; 0xe0
+ 800fde2:	f003 0301 	and.w	r3, r3, #1
+ 800fde6:	613b      	str	r3, [r7, #16]
+ 800fde8:	693b      	ldr	r3, [r7, #16]
+    __HAL_RCC_GPIOB_CLK_ENABLE();
+ 800fdea:	4b27      	ldr	r3, [pc, #156]	; (800fe88 <HAL_ETH_MspInit+0x158>)
+ 800fdec:	f8d3 30e0 	ldr.w	r3, [r3, #224]	; 0xe0
+ 800fdf0:	4a25      	ldr	r2, [pc, #148]	; (800fe88 <HAL_ETH_MspInit+0x158>)
+ 800fdf2:	f043 0302 	orr.w	r3, r3, #2
+ 800fdf6:	f8c2 30e0 	str.w	r3, [r2, #224]	; 0xe0
+ 800fdfa:	4b23      	ldr	r3, [pc, #140]	; (800fe88 <HAL_ETH_MspInit+0x158>)
+ 800fdfc:	f8d3 30e0 	ldr.w	r3, [r3, #224]	; 0xe0
+ 800fe00:	f003 0302 	and.w	r3, r3, #2
+ 800fe04:	60fb      	str	r3, [r7, #12]
+ 800fe06:	68fb      	ldr	r3, [r7, #12]
+    PB13     ------> ETH_TXD1
+    PA7     ------> ETH_CRS_DV
+    PB11     ------> ETH_TX_EN
+    PB12     ------> ETH_TXD0
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_4|GPIO_PIN_5;
+ 800fe08:	2332      	movs	r3, #50	; 0x32
+ 800fe0a:	627b      	str	r3, [r7, #36]	; 0x24
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ 800fe0c:	2302      	movs	r3, #2
+ 800fe0e:	62bb      	str	r3, [r7, #40]	; 0x28
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 800fe10:	2300      	movs	r3, #0
+ 800fe12:	62fb      	str	r3, [r7, #44]	; 0x2c
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+ 800fe14:	2303      	movs	r3, #3
+ 800fe16:	633b      	str	r3, [r7, #48]	; 0x30
+    GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
+ 800fe18:	230b      	movs	r3, #11
+ 800fe1a:	637b      	str	r3, [r7, #52]	; 0x34
+    HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
+ 800fe1c:	f107 0324 	add.w	r3, r7, #36	; 0x24
+ 800fe20:	4619      	mov	r1, r3
+ 800fe22:	481a      	ldr	r0, [pc, #104]	; (800fe8c <HAL_ETH_MspInit+0x15c>)
+ 800fe24:	f7f6 fcc4 	bl	80067b0 <HAL_GPIO_Init>
+
+    GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_7;
+ 800fe28:	2386      	movs	r3, #134	; 0x86
+ 800fe2a:	627b      	str	r3, [r7, #36]	; 0x24
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ 800fe2c:	2302      	movs	r3, #2
+ 800fe2e:	62bb      	str	r3, [r7, #40]	; 0x28
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 800fe30:	2300      	movs	r3, #0
+ 800fe32:	62fb      	str	r3, [r7, #44]	; 0x2c
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+ 800fe34:	2303      	movs	r3, #3
+ 800fe36:	633b      	str	r3, [r7, #48]	; 0x30
+    GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
+ 800fe38:	230b      	movs	r3, #11
+ 800fe3a:	637b      	str	r3, [r7, #52]	; 0x34
+    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+ 800fe3c:	f107 0324 	add.w	r3, r7, #36	; 0x24
+ 800fe40:	4619      	mov	r1, r3
+ 800fe42:	4813      	ldr	r0, [pc, #76]	; (800fe90 <HAL_ETH_MspInit+0x160>)
+ 800fe44:	f7f6 fcb4 	bl	80067b0 <HAL_GPIO_Init>
+
+    GPIO_InitStruct.Pin = GPIO_PIN_13|GPIO_PIN_11|GPIO_PIN_12;
+ 800fe48:	f44f 5360 	mov.w	r3, #14336	; 0x3800
+ 800fe4c:	627b      	str	r3, [r7, #36]	; 0x24
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ 800fe4e:	2302      	movs	r3, #2
+ 800fe50:	62bb      	str	r3, [r7, #40]	; 0x28
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 800fe52:	2300      	movs	r3, #0
+ 800fe54:	62fb      	str	r3, [r7, #44]	; 0x2c
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+ 800fe56:	2303      	movs	r3, #3
+ 800fe58:	633b      	str	r3, [r7, #48]	; 0x30
+    GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
+ 800fe5a:	230b      	movs	r3, #11
+ 800fe5c:	637b      	str	r3, [r7, #52]	; 0x34
+    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+ 800fe5e:	f107 0324 	add.w	r3, r7, #36	; 0x24
+ 800fe62:	4619      	mov	r1, r3
+ 800fe64:	480b      	ldr	r0, [pc, #44]	; (800fe94 <HAL_ETH_MspInit+0x164>)
+ 800fe66:	f7f6 fca3 	bl	80067b0 <HAL_GPIO_Init>
+
+    /* Peripheral interrupt init */
+    HAL_NVIC_SetPriority(ETH_IRQn, 5, 0);
+ 800fe6a:	2200      	movs	r2, #0
+ 800fe6c:	2105      	movs	r1, #5
+ 800fe6e:	203d      	movs	r0, #61	; 0x3d
+ 800fe70:	f7f2 fb74 	bl	800255c <HAL_NVIC_SetPriority>
+    HAL_NVIC_EnableIRQ(ETH_IRQn);
+ 800fe74:	203d      	movs	r0, #61	; 0x3d
+ 800fe76:	f7f2 fb8b 	bl	8002590 <HAL_NVIC_EnableIRQ>
+  /* USER CODE BEGIN ETH_MspInit 1 */
+
+  /* USER CODE END ETH_MspInit 1 */
+  }
+}
+ 800fe7a:	bf00      	nop
+ 800fe7c:	3738      	adds	r7, #56	; 0x38
+ 800fe7e:	46bd      	mov	sp, r7
+ 800fe80:	bd80      	pop	{r7, pc}
+ 800fe82:	bf00      	nop
+ 800fe84:	40028000 	.word	0x40028000
+ 800fe88:	58024400 	.word	0x58024400
+ 800fe8c:	58020800 	.word	0x58020800
+ 800fe90:	58020000 	.word	0x58020000
+ 800fe94:	58020400 	.word	0x58020400
+
+0800fe98 <ETH_PHY_IO_Init>:
+  * @brief  Initializes the MDIO interface GPIO and clocks.
+  * @param  None
+  * @retval 0 if OK, -1 if ERROR
+  */
+int32_t ETH_PHY_IO_Init(void)
+{
+ 800fe98:	b580      	push	{r7, lr}
+ 800fe9a:	af00      	add	r7, sp, #0
+  /* We assume that MDIO GPIO configuration is already done
+     in the ETH_MspInit() else it should be done here
+  */
+
+  /* Configure the MDIO Clock */
+  HAL_ETH_SetMDIOClockRange(&heth);
+ 800fe9c:	4802      	ldr	r0, [pc, #8]	; (800fea8 <ETH_PHY_IO_Init+0x10>)
+ 800fe9e:	f7f5 f847 	bl	8004f30 <HAL_ETH_SetMDIOClockRange>
+
+  return 0;
+ 800fea2:	2300      	movs	r3, #0
+}
+ 800fea4:	4618      	mov	r0, r3
+ 800fea6:	bd80      	pop	{r7, pc}
+ 800fea8:	2400bdcc 	.word	0x2400bdcc
+
+0800feac <ETH_PHY_IO_DeInit>:
+  * @brief  De-Initializes the MDIO interface .
+  * @param  None
+  * @retval 0 if OK, -1 if ERROR
+  */
+int32_t ETH_PHY_IO_DeInit (void)
+{
+ 800feac:	b480      	push	{r7}
+ 800feae:	af00      	add	r7, sp, #0
+  return 0;
+ 800feb0:	2300      	movs	r3, #0
+}
+ 800feb2:	4618      	mov	r0, r3
+ 800feb4:	46bd      	mov	sp, r7
+ 800feb6:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 800feba:	4770      	bx	lr
+
+0800febc <ETH_PHY_IO_ReadReg>:
+  * @param  RegAddr: PHY register address
+  * @param  pRegVal: pointer to hold the register value
+  * @retval 0 if OK -1 if Error
+  */
+int32_t ETH_PHY_IO_ReadReg(uint32_t DevAddr, uint32_t RegAddr, uint32_t *pRegVal)
+{
+ 800febc:	b580      	push	{r7, lr}
+ 800febe:	b084      	sub	sp, #16
+ 800fec0:	af00      	add	r7, sp, #0
+ 800fec2:	60f8      	str	r0, [r7, #12]
+ 800fec4:	60b9      	str	r1, [r7, #8]
+ 800fec6:	607a      	str	r2, [r7, #4]
+  if(HAL_ETH_ReadPHYRegister(&heth, DevAddr, RegAddr, pRegVal) != HAL_OK)
+ 800fec8:	687b      	ldr	r3, [r7, #4]
+ 800feca:	68ba      	ldr	r2, [r7, #8]
+ 800fecc:	68f9      	ldr	r1, [r7, #12]
+ 800fece:	4807      	ldr	r0, [pc, #28]	; (800feec <ETH_PHY_IO_ReadReg+0x30>)
+ 800fed0:	f7f4 fd98 	bl	8004a04 <HAL_ETH_ReadPHYRegister>
+ 800fed4:	4603      	mov	r3, r0
+ 800fed6:	2b00      	cmp	r3, #0
+ 800fed8:	d002      	beq.n	800fee0 <ETH_PHY_IO_ReadReg+0x24>
+  {
+    return -1;
+ 800feda:	f04f 33ff 	mov.w	r3, #4294967295
+ 800fede:	e000      	b.n	800fee2 <ETH_PHY_IO_ReadReg+0x26>
+  }
+
+  return 0;
+ 800fee0:	2300      	movs	r3, #0
+}
+ 800fee2:	4618      	mov	r0, r3
+ 800fee4:	3710      	adds	r7, #16
+ 800fee6:	46bd      	mov	sp, r7
+ 800fee8:	bd80      	pop	{r7, pc}
+ 800feea:	bf00      	nop
+ 800feec:	2400bdcc 	.word	0x2400bdcc
+
+0800fef0 <ETH_PHY_IO_WriteReg>:
+  * @param  RegAddr: PHY register address
+  * @param  RegVal: Value to be written
+  * @retval 0 if OK -1 if Error
+  */
+int32_t ETH_PHY_IO_WriteReg(uint32_t DevAddr, uint32_t RegAddr, uint32_t RegVal)
+{
+ 800fef0:	b580      	push	{r7, lr}
+ 800fef2:	b084      	sub	sp, #16
+ 800fef4:	af00      	add	r7, sp, #0
+ 800fef6:	60f8      	str	r0, [r7, #12]
+ 800fef8:	60b9      	str	r1, [r7, #8]
+ 800fefa:	607a      	str	r2, [r7, #4]
+  if(HAL_ETH_WritePHYRegister(&heth, DevAddr, RegAddr, RegVal) != HAL_OK)
+ 800fefc:	687b      	ldr	r3, [r7, #4]
+ 800fefe:	68ba      	ldr	r2, [r7, #8]
+ 800ff00:	68f9      	ldr	r1, [r7, #12]
+ 800ff02:	4807      	ldr	r0, [pc, #28]	; (800ff20 <ETH_PHY_IO_WriteReg+0x30>)
+ 800ff04:	f7f4 fdd2 	bl	8004aac <HAL_ETH_WritePHYRegister>
+ 800ff08:	4603      	mov	r3, r0
+ 800ff0a:	2b00      	cmp	r3, #0
+ 800ff0c:	d002      	beq.n	800ff14 <ETH_PHY_IO_WriteReg+0x24>
+  {
+    return -1;
+ 800ff0e:	f04f 33ff 	mov.w	r3, #4294967295
+ 800ff12:	e000      	b.n	800ff16 <ETH_PHY_IO_WriteReg+0x26>
+  }
+
+  return 0;
+ 800ff14:	2300      	movs	r3, #0
+}
+ 800ff16:	4618      	mov	r0, r3
+ 800ff18:	3710      	adds	r7, #16
+ 800ff1a:	46bd      	mov	sp, r7
+ 800ff1c:	bd80      	pop	{r7, pc}
+ 800ff1e:	bf00      	nop
+ 800ff20:	2400bdcc 	.word	0x2400bdcc
+
+0800ff24 <ETH_PHY_IO_GetTick>:
+/**
+  * @brief  Get the time in millisecons used for internal PHY driver process.
+  * @retval Time value
+  */
+int32_t ETH_PHY_IO_GetTick(void)
+{
+ 800ff24:	b580      	push	{r7, lr}
+ 800ff26:	af00      	add	r7, sp, #0
+  return HAL_GetTick();
+ 800ff28:	f7f2 fa1c 	bl	8002364 <HAL_GetTick>
+ 800ff2c:	4603      	mov	r3, r0
+}
+ 800ff2e:	4618      	mov	r0, r3
+ 800ff30:	bd80      	pop	{r7, pc}
+	...
+
+0800ff34 <ethernet_link_thread>:
+  * @brief  Check the ETH link state then update ETH driver and netif link accordingly.
+  * @retval None
+  */
+
+void ethernet_link_thread(void const * argument)
+{
+ 800ff34:	b580      	push	{r7, lr}
+ 800ff36:	b0a0      	sub	sp, #128	; 0x80
+ 800ff38:	af00      	add	r7, sp, #0
+ 800ff3a:	6078      	str	r0, [r7, #4]
+  ETH_MACConfigTypeDef MACConf = {0};
+ 800ff3c:	f107 0308 	add.w	r3, r7, #8
+ 800ff40:	2264      	movs	r2, #100	; 0x64
+ 800ff42:	2100      	movs	r1, #0
+ 800ff44:	4618      	mov	r0, r3
+ 800ff46:	f011 fecb 	bl	8021ce0 <memset>
+  int32_t PHYLinkState = 0;
+ 800ff4a:	2300      	movs	r3, #0
+ 800ff4c:	673b      	str	r3, [r7, #112]	; 0x70
+  uint32_t linkchanged = 0U, speed = 0U, duplex = 0U;
+ 800ff4e:	2300      	movs	r3, #0
+ 800ff50:	67fb      	str	r3, [r7, #124]	; 0x7c
+ 800ff52:	2300      	movs	r3, #0
+ 800ff54:	67bb      	str	r3, [r7, #120]	; 0x78
+ 800ff56:	2300      	movs	r3, #0
+ 800ff58:	677b      	str	r3, [r7, #116]	; 0x74
+
+  struct netif *netif = (struct netif *) argument;
+ 800ff5a:	687b      	ldr	r3, [r7, #4]
+ 800ff5c:	66fb      	str	r3, [r7, #108]	; 0x6c
+
+/* USER CODE END ETH link init */
+
+  for(;;)
+  {
+  PHYLinkState = LAN8742_GetLinkState(&LAN8742);
+ 800ff5e:	483a      	ldr	r0, [pc, #232]	; (8010048 <ethernet_link_thread+0x114>)
+ 800ff60:	f7f2 f929 	bl	80021b6 <LAN8742_GetLinkState>
+ 800ff64:	6738      	str	r0, [r7, #112]	; 0x70
+
+  if(netif_is_link_up(netif) && (PHYLinkState <= LAN8742_STATUS_LINK_DOWN))
+ 800ff66:	6efb      	ldr	r3, [r7, #108]	; 0x6c
+ 800ff68:	f893 302d 	ldrb.w	r3, [r3, #45]	; 0x2d
+ 800ff6c:	089b      	lsrs	r3, r3, #2
+ 800ff6e:	f003 0301 	and.w	r3, r3, #1
+ 800ff72:	b2db      	uxtb	r3, r3
+ 800ff74:	2b00      	cmp	r3, #0
+ 800ff76:	d00c      	beq.n	800ff92 <ethernet_link_thread+0x5e>
+ 800ff78:	6f3b      	ldr	r3, [r7, #112]	; 0x70
+ 800ff7a:	2b01      	cmp	r3, #1
+ 800ff7c:	dc09      	bgt.n	800ff92 <ethernet_link_thread+0x5e>
+  {
+    HAL_ETH_Stop_IT(&heth);
+ 800ff7e:	4833      	ldr	r0, [pc, #204]	; (801004c <ethernet_link_thread+0x118>)
+ 800ff80:	f7f4 f9c0 	bl	8004304 <HAL_ETH_Stop_IT>
+    netif_set_down(netif);
+ 800ff84:	6ef8      	ldr	r0, [r7, #108]	; 0x6c
+ 800ff86:	f007 f96f 	bl	8017268 <netif_set_down>
+    netif_set_link_down(netif);
+ 800ff8a:	6ef8      	ldr	r0, [r7, #108]	; 0x6c
+ 800ff8c:	f007 f9d2 	bl	8017334 <netif_set_link_down>
+ 800ff90:	e055      	b.n	801003e <ethernet_link_thread+0x10a>
+  }
+  else if(!netif_is_link_up(netif) && (PHYLinkState > LAN8742_STATUS_LINK_DOWN))
+ 800ff92:	6efb      	ldr	r3, [r7, #108]	; 0x6c
+ 800ff94:	f893 302d 	ldrb.w	r3, [r3, #45]	; 0x2d
+ 800ff98:	f003 0304 	and.w	r3, r3, #4
+ 800ff9c:	2b00      	cmp	r3, #0
+ 800ff9e:	d14e      	bne.n	801003e <ethernet_link_thread+0x10a>
+ 800ffa0:	6f3b      	ldr	r3, [r7, #112]	; 0x70
+ 800ffa2:	2b01      	cmp	r3, #1
+ 800ffa4:	dd4b      	ble.n	801003e <ethernet_link_thread+0x10a>
+  {
+    switch (PHYLinkState)
+ 800ffa6:	6f3b      	ldr	r3, [r7, #112]	; 0x70
+ 800ffa8:	3b02      	subs	r3, #2
+ 800ffaa:	2b03      	cmp	r3, #3
+ 800ffac:	d82a      	bhi.n	8010004 <ethernet_link_thread+0xd0>
+ 800ffae:	a201      	add	r2, pc, #4	; (adr r2, 800ffb4 <ethernet_link_thread+0x80>)
+ 800ffb0:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
+ 800ffb4:	0800ffc5 	.word	0x0800ffc5
+ 800ffb8:	0800ffd7 	.word	0x0800ffd7
+ 800ffbc:	0800ffe7 	.word	0x0800ffe7
+ 800ffc0:	0800fff7 	.word	0x0800fff7
+    {
+    case LAN8742_STATUS_100MBITS_FULLDUPLEX:
+      duplex = ETH_FULLDUPLEX_MODE;
+ 800ffc4:	f44f 5300 	mov.w	r3, #8192	; 0x2000
+ 800ffc8:	677b      	str	r3, [r7, #116]	; 0x74
+      speed = ETH_SPEED_100M;
+ 800ffca:	f44f 4380 	mov.w	r3, #16384	; 0x4000
+ 800ffce:	67bb      	str	r3, [r7, #120]	; 0x78
+      linkchanged = 1;
+ 800ffd0:	2301      	movs	r3, #1
+ 800ffd2:	67fb      	str	r3, [r7, #124]	; 0x7c
+      break;
+ 800ffd4:	e017      	b.n	8010006 <ethernet_link_thread+0xd2>
+    case LAN8742_STATUS_100MBITS_HALFDUPLEX:
+      duplex = ETH_HALFDUPLEX_MODE;
+ 800ffd6:	2300      	movs	r3, #0
+ 800ffd8:	677b      	str	r3, [r7, #116]	; 0x74
+      speed = ETH_SPEED_100M;
+ 800ffda:	f44f 4380 	mov.w	r3, #16384	; 0x4000
+ 800ffde:	67bb      	str	r3, [r7, #120]	; 0x78
+      linkchanged = 1;
+ 800ffe0:	2301      	movs	r3, #1
+ 800ffe2:	67fb      	str	r3, [r7, #124]	; 0x7c
+      break;
+ 800ffe4:	e00f      	b.n	8010006 <ethernet_link_thread+0xd2>
+    case LAN8742_STATUS_10MBITS_FULLDUPLEX:
+      duplex = ETH_FULLDUPLEX_MODE;
+ 800ffe6:	f44f 5300 	mov.w	r3, #8192	; 0x2000
+ 800ffea:	677b      	str	r3, [r7, #116]	; 0x74
+      speed = ETH_SPEED_10M;
+ 800ffec:	2300      	movs	r3, #0
+ 800ffee:	67bb      	str	r3, [r7, #120]	; 0x78
+      linkchanged = 1;
+ 800fff0:	2301      	movs	r3, #1
+ 800fff2:	67fb      	str	r3, [r7, #124]	; 0x7c
+      break;
+ 800fff4:	e007      	b.n	8010006 <ethernet_link_thread+0xd2>
+    case LAN8742_STATUS_10MBITS_HALFDUPLEX:
+      duplex = ETH_HALFDUPLEX_MODE;
+ 800fff6:	2300      	movs	r3, #0
+ 800fff8:	677b      	str	r3, [r7, #116]	; 0x74
+      speed = ETH_SPEED_10M;
+ 800fffa:	2300      	movs	r3, #0
+ 800fffc:	67bb      	str	r3, [r7, #120]	; 0x78
+      linkchanged = 1;
+ 800fffe:	2301      	movs	r3, #1
+ 8010000:	67fb      	str	r3, [r7, #124]	; 0x7c
+      break;
+ 8010002:	e000      	b.n	8010006 <ethernet_link_thread+0xd2>
+    default:
+      break;
+ 8010004:	bf00      	nop
+    }
+
+    if(linkchanged)
+ 8010006:	6ffb      	ldr	r3, [r7, #124]	; 0x7c
+ 8010008:	2b00      	cmp	r3, #0
+ 801000a:	d018      	beq.n	801003e <ethernet_link_thread+0x10a>
+    {
+      /* Get MAC Config MAC */
+      HAL_ETH_GetMACConfig(&heth, &MACConf);
+ 801000c:	f107 0308 	add.w	r3, r7, #8
+ 8010010:	4619      	mov	r1, r3
+ 8010012:	480e      	ldr	r0, [pc, #56]	; (801004c <ethernet_link_thread+0x118>)
+ 8010014:	f7f4 fd9e 	bl	8004b54 <HAL_ETH_GetMACConfig>
+      MACConf.DuplexMode = duplex;
+ 8010018:	6f7b      	ldr	r3, [r7, #116]	; 0x74
+ 801001a:	623b      	str	r3, [r7, #32]
+      MACConf.Speed = speed;
+ 801001c:	6fbb      	ldr	r3, [r7, #120]	; 0x78
+ 801001e:	61fb      	str	r3, [r7, #28]
+      HAL_ETH_SetMACConfig(&heth, &MACConf);
+ 8010020:	f107 0308 	add.w	r3, r7, #8
+ 8010024:	4619      	mov	r1, r3
+ 8010026:	4809      	ldr	r0, [pc, #36]	; (801004c <ethernet_link_thread+0x118>)
+ 8010028:	f7f4 ff68 	bl	8004efc <HAL_ETH_SetMACConfig>
+      HAL_ETH_Start_IT(&heth);
+ 801002c:	4807      	ldr	r0, [pc, #28]	; (801004c <ethernet_link_thread+0x118>)
+ 801002e:	f7f4 f8dd 	bl	80041ec <HAL_ETH_Start_IT>
+      netif_set_up(netif);
+ 8010032:	6ef8      	ldr	r0, [r7, #108]	; 0x6c
+ 8010034:	f007 f8ac 	bl	8017190 <netif_set_up>
+      netif_set_link_up(netif);
+ 8010038:	6ef8      	ldr	r0, [r7, #108]	; 0x6c
+ 801003a:	f007 f947 	bl	80172cc <netif_set_link_up>
+
+/* USER CODE BEGIN ETH link Thread core code for User BSP */
+
+/* USER CODE END ETH link Thread core code for User BSP */
+
+    osDelay(100);
+ 801003e:	2064      	movs	r0, #100	; 0x64
+ 8010040:	f000 f99e 	bl	8010380 <osDelay>
+  PHYLinkState = LAN8742_GetLinkState(&LAN8742);
+ 8010044:	e78b      	b.n	800ff5e <ethernet_link_thread+0x2a>
+ 8010046:	bf00      	nop
+ 8010048:	2400beb4 	.word	0x2400beb4
+ 801004c:	2400bdcc 	.word	0x2400bdcc
+
+08010050 <HAL_ETH_RxAllocateCallback>:
+  }
+}
+
+void HAL_ETH_RxAllocateCallback(uint8_t **buff)
+{
+ 8010050:	b580      	push	{r7, lr}
+ 8010052:	b086      	sub	sp, #24
+ 8010054:	af02      	add	r7, sp, #8
+ 8010056:	6078      	str	r0, [r7, #4]
+/* USER CODE BEGIN HAL ETH RxAllocateCallback */
+  struct pbuf_custom *p = LWIP_MEMPOOL_ALLOC(RX_POOL);
+ 8010058:	4812      	ldr	r0, [pc, #72]	; (80100a4 <HAL_ETH_RxAllocateCallback+0x54>)
+ 801005a:	f006 fd17 	bl	8016a8c <memp_malloc_pool>
+ 801005e:	60f8      	str	r0, [r7, #12]
+  if (p)
+ 8010060:	68fb      	ldr	r3, [r7, #12]
+ 8010062:	2b00      	cmp	r3, #0
+ 8010064:	d014      	beq.n	8010090 <HAL_ETH_RxAllocateCallback+0x40>
+  {
+    /* Get the buff from the struct pbuf address. */
+    *buff = (uint8_t *)p + offsetof(RxBuff_t, buff);
+ 8010066:	68fb      	ldr	r3, [r7, #12]
+ 8010068:	f103 0220 	add.w	r2, r3, #32
+ 801006c:	687b      	ldr	r3, [r7, #4]
+ 801006e:	601a      	str	r2, [r3, #0]
+    p->custom_free_function = pbuf_free_custom;
+ 8010070:	68fb      	ldr	r3, [r7, #12]
+ 8010072:	4a0d      	ldr	r2, [pc, #52]	; (80100a8 <HAL_ETH_RxAllocateCallback+0x58>)
+ 8010074:	611a      	str	r2, [r3, #16]
+    /* Initialize the struct pbuf.
+    * This must be performed whenever a buffer's allocated because it may be
+    * changed by lwIP or the app, e.g., pbuf_free decrements ref. */
+    pbuf_alloced_custom(PBUF_RAW, 0, PBUF_REF, p, *buff, ETH_RX_BUFFER_SIZE);
+ 8010076:	687b      	ldr	r3, [r7, #4]
+ 8010078:	681b      	ldr	r3, [r3, #0]
+ 801007a:	f44f 62c0 	mov.w	r2, #1536	; 0x600
+ 801007e:	9201      	str	r2, [sp, #4]
+ 8010080:	9300      	str	r3, [sp, #0]
+ 8010082:	68fb      	ldr	r3, [r7, #12]
+ 8010084:	2241      	movs	r2, #65	; 0x41
+ 8010086:	2100      	movs	r1, #0
+ 8010088:	2000      	movs	r0, #0
+ 801008a:	f007 fb7b 	bl	8017784 <pbuf_alloced_custom>
+  {
+    RxAllocStatus = RX_ALLOC_ERROR;
+    *buff = NULL;
+  }
+/* USER CODE END HAL ETH RxAllocateCallback */
+}
+ 801008e:	e005      	b.n	801009c <HAL_ETH_RxAllocateCallback+0x4c>
+    RxAllocStatus = RX_ALLOC_ERROR;
+ 8010090:	4b06      	ldr	r3, [pc, #24]	; (80100ac <HAL_ETH_RxAllocateCallback+0x5c>)
+ 8010092:	2201      	movs	r2, #1
+ 8010094:	701a      	strb	r2, [r3, #0]
+    *buff = NULL;
+ 8010096:	687b      	ldr	r3, [r7, #4]
+ 8010098:	2200      	movs	r2, #0
+ 801009a:	601a      	str	r2, [r3, #0]
+}
+ 801009c:	bf00      	nop
+ 801009e:	3710      	adds	r7, #16
+ 80100a0:	46bd      	mov	sp, r7
+ 80100a2:	bd80      	pop	{r7, pc}
+ 80100a4:	08026b94 	.word	0x08026b94
+ 80100a8:	0800fce1 	.word	0x0800fce1
+ 80100ac:	2400bdc0 	.word	0x2400bdc0
+
+080100b0 <HAL_ETH_RxLinkCallback>:
+
+void HAL_ETH_RxLinkCallback(void **pStart, void **pEnd, uint8_t *buff, uint16_t Length)
+{
+ 80100b0:	b480      	push	{r7}
+ 80100b2:	b08d      	sub	sp, #52	; 0x34
+ 80100b4:	af00      	add	r7, sp, #0
+ 80100b6:	60f8      	str	r0, [r7, #12]
+ 80100b8:	60b9      	str	r1, [r7, #8]
+ 80100ba:	607a      	str	r2, [r7, #4]
+ 80100bc:	807b      	strh	r3, [r7, #2]
+/* USER CODE BEGIN HAL ETH RxLinkCallback */
+
+  struct pbuf **ppStart = (struct pbuf **)pStart;
+ 80100be:	68fb      	ldr	r3, [r7, #12]
+ 80100c0:	62bb      	str	r3, [r7, #40]	; 0x28
+  struct pbuf **ppEnd = (struct pbuf **)pEnd;
+ 80100c2:	68bb      	ldr	r3, [r7, #8]
+ 80100c4:	627b      	str	r3, [r7, #36]	; 0x24
+  struct pbuf *p = NULL;
+ 80100c6:	2300      	movs	r3, #0
+ 80100c8:	62fb      	str	r3, [r7, #44]	; 0x2c
+
+  /* Get the struct pbuf from the buff address. */
+  p = (struct pbuf *)(buff - offsetof(RxBuff_t, buff));
+ 80100ca:	687b      	ldr	r3, [r7, #4]
+ 80100cc:	3b20      	subs	r3, #32
+ 80100ce:	62fb      	str	r3, [r7, #44]	; 0x2c
+  p->next = NULL;
+ 80100d0:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 80100d2:	2200      	movs	r2, #0
+ 80100d4:	601a      	str	r2, [r3, #0]
+  p->tot_len = 0;
+ 80100d6:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 80100d8:	2200      	movs	r2, #0
+ 80100da:	811a      	strh	r2, [r3, #8]
+  p->len = Length;
+ 80100dc:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 80100de:	887a      	ldrh	r2, [r7, #2]
+ 80100e0:	815a      	strh	r2, [r3, #10]
+
+  /* Chain the buffer. */
+  if (!*ppStart)
+ 80100e2:	6abb      	ldr	r3, [r7, #40]	; 0x28
+ 80100e4:	681b      	ldr	r3, [r3, #0]
+ 80100e6:	2b00      	cmp	r3, #0
+ 80100e8:	d103      	bne.n	80100f2 <HAL_ETH_RxLinkCallback+0x42>
+  {
+    /* The first buffer of the packet. */
+    *ppStart = p;
+ 80100ea:	6abb      	ldr	r3, [r7, #40]	; 0x28
+ 80100ec:	6afa      	ldr	r2, [r7, #44]	; 0x2c
+ 80100ee:	601a      	str	r2, [r3, #0]
+ 80100f0:	e003      	b.n	80100fa <HAL_ETH_RxLinkCallback+0x4a>
+  }
+  else
+  {
+    /* Chain the buffer to the end of the packet. */
+    (*ppEnd)->next = p;
+ 80100f2:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 80100f4:	681b      	ldr	r3, [r3, #0]
+ 80100f6:	6afa      	ldr	r2, [r7, #44]	; 0x2c
+ 80100f8:	601a      	str	r2, [r3, #0]
+  }
+  *ppEnd  = p;
+ 80100fa:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 80100fc:	6afa      	ldr	r2, [r7, #44]	; 0x2c
+ 80100fe:	601a      	str	r2, [r3, #0]
+
+  /* Update the total length of all the buffers of the chain. Each pbuf in the chain should have its tot_len
+   * set to its own length, plus the length of all the following pbufs in the chain. */
+  for (p = *ppStart; p != NULL; p = p->next)
+ 8010100:	6abb      	ldr	r3, [r7, #40]	; 0x28
+ 8010102:	681b      	ldr	r3, [r3, #0]
+ 8010104:	62fb      	str	r3, [r7, #44]	; 0x2c
+ 8010106:	e009      	b.n	801011c <HAL_ETH_RxLinkCallback+0x6c>
+  {
+    p->tot_len += Length;
+ 8010108:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 801010a:	891a      	ldrh	r2, [r3, #8]
+ 801010c:	887b      	ldrh	r3, [r7, #2]
+ 801010e:	4413      	add	r3, r2
+ 8010110:	b29a      	uxth	r2, r3
+ 8010112:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 8010114:	811a      	strh	r2, [r3, #8]
+  for (p = *ppStart; p != NULL; p = p->next)
+ 8010116:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 8010118:	681b      	ldr	r3, [r3, #0]
+ 801011a:	62fb      	str	r3, [r7, #44]	; 0x2c
+ 801011c:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 801011e:	2b00      	cmp	r3, #0
+ 8010120:	d1f2      	bne.n	8010108 <HAL_ETH_RxLinkCallback+0x58>
+  }
+
+  /* Invalidate data cache because Rx DMA's writing to physical memory makes it stale. */
+  SCB_InvalidateDCache_by_Addr((uint32_t *)buff, Length);
+ 8010122:	887b      	ldrh	r3, [r7, #2]
+ 8010124:	687a      	ldr	r2, [r7, #4]
+ 8010126:	623a      	str	r2, [r7, #32]
+ 8010128:	61fb      	str	r3, [r7, #28]
+    if ( dsize > 0 ) { 
+ 801012a:	69fb      	ldr	r3, [r7, #28]
+ 801012c:	2b00      	cmp	r3, #0
+ 801012e:	dd1d      	ble.n	801016c <HAL_ETH_RxLinkCallback+0xbc>
+       int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
+ 8010130:	6a3b      	ldr	r3, [r7, #32]
+ 8010132:	f003 021f 	and.w	r2, r3, #31
+ 8010136:	69fb      	ldr	r3, [r7, #28]
+ 8010138:	4413      	add	r3, r2
+ 801013a:	61bb      	str	r3, [r7, #24]
+      uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
+ 801013c:	6a3b      	ldr	r3, [r7, #32]
+ 801013e:	617b      	str	r3, [r7, #20]
+  __ASM volatile ("dsb 0xF":::"memory");
+ 8010140:	f3bf 8f4f 	dsb	sy
+}
+ 8010144:	bf00      	nop
+        SCB->DCIMVAC = op_addr;             /* register accepts only 32byte aligned values, only bits 31..5 are valid */
+ 8010146:	4a0d      	ldr	r2, [pc, #52]	; (801017c <HAL_ETH_RxLinkCallback+0xcc>)
+ 8010148:	697b      	ldr	r3, [r7, #20]
+ 801014a:	f8c2 325c 	str.w	r3, [r2, #604]	; 0x25c
+        op_addr += __SCB_DCACHE_LINE_SIZE;
+ 801014e:	697b      	ldr	r3, [r7, #20]
+ 8010150:	3320      	adds	r3, #32
+ 8010152:	617b      	str	r3, [r7, #20]
+        op_size -= __SCB_DCACHE_LINE_SIZE;
+ 8010154:	69bb      	ldr	r3, [r7, #24]
+ 8010156:	3b20      	subs	r3, #32
+ 8010158:	61bb      	str	r3, [r7, #24]
+      } while ( op_size > 0 );
+ 801015a:	69bb      	ldr	r3, [r7, #24]
+ 801015c:	2b00      	cmp	r3, #0
+ 801015e:	dcf2      	bgt.n	8010146 <HAL_ETH_RxLinkCallback+0x96>
+  __ASM volatile ("dsb 0xF":::"memory");
+ 8010160:	f3bf 8f4f 	dsb	sy
+}
+ 8010164:	bf00      	nop
+  __ASM volatile ("isb 0xF":::"memory");
+ 8010166:	f3bf 8f6f 	isb	sy
+}
+ 801016a:	bf00      	nop
+}
+ 801016c:	bf00      	nop
+
+/* USER CODE END HAL ETH RxLinkCallback */
+}
+ 801016e:	bf00      	nop
+ 8010170:	3734      	adds	r7, #52	; 0x34
+ 8010172:	46bd      	mov	sp, r7
+ 8010174:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8010178:	4770      	bx	lr
+ 801017a:	bf00      	nop
+ 801017c:	e000ed00 	.word	0xe000ed00
+
+08010180 <HAL_ETH_TxFreeCallback>:
+
+void HAL_ETH_TxFreeCallback(uint32_t * buff)
+{
+ 8010180:	b580      	push	{r7, lr}
+ 8010182:	b082      	sub	sp, #8
+ 8010184:	af00      	add	r7, sp, #0
+ 8010186:	6078      	str	r0, [r7, #4]
+/* USER CODE BEGIN HAL ETH TxFreeCallback */
+
+  pbuf_free((struct pbuf *)buff);
+ 8010188:	6878      	ldr	r0, [r7, #4]
+ 801018a:	f007 fcb5 	bl	8017af8 <pbuf_free>
+
+/* USER CODE END HAL ETH TxFreeCallback */
+}
+ 801018e:	bf00      	nop
+ 8010190:	3708      	adds	r7, #8
+ 8010192:	46bd      	mov	sp, r7
+ 8010194:	bd80      	pop	{r7, pc}
+	...
+
+08010198 <FATFS_LinkDriverEx>:
+  * @param  lun : only used for USB Key Disk to add multi-lun management
+            else the parameter must be equal to 0
+  * @retval Returns 0 in case of success, otherwise 1.
+  */
+uint8_t FATFS_LinkDriverEx(const Diskio_drvTypeDef *drv, char *path, uint8_t lun)
+{
+ 8010198:	b480      	push	{r7}
+ 801019a:	b087      	sub	sp, #28
+ 801019c:	af00      	add	r7, sp, #0
+ 801019e:	60f8      	str	r0, [r7, #12]
+ 80101a0:	60b9      	str	r1, [r7, #8]
+ 80101a2:	4613      	mov	r3, r2
+ 80101a4:	71fb      	strb	r3, [r7, #7]
+  uint8_t ret = 1;
+ 80101a6:	2301      	movs	r3, #1
+ 80101a8:	75fb      	strb	r3, [r7, #23]
+  uint8_t DiskNum = 0;
+ 80101aa:	2300      	movs	r3, #0
+ 80101ac:	75bb      	strb	r3, [r7, #22]
+
+  if(disk.nbr < _VOLUMES)
+ 80101ae:	4b1f      	ldr	r3, [pc, #124]	; (801022c <FATFS_LinkDriverEx+0x94>)
+ 80101b0:	7a5b      	ldrb	r3, [r3, #9]
+ 80101b2:	b2db      	uxtb	r3, r3
+ 80101b4:	2b00      	cmp	r3, #0
+ 80101b6:	d131      	bne.n	801021c <FATFS_LinkDriverEx+0x84>
+  {
+    disk.is_initialized[disk.nbr] = 0;
+ 80101b8:	4b1c      	ldr	r3, [pc, #112]	; (801022c <FATFS_LinkDriverEx+0x94>)
+ 80101ba:	7a5b      	ldrb	r3, [r3, #9]
+ 80101bc:	b2db      	uxtb	r3, r3
+ 80101be:	461a      	mov	r2, r3
+ 80101c0:	4b1a      	ldr	r3, [pc, #104]	; (801022c <FATFS_LinkDriverEx+0x94>)
+ 80101c2:	2100      	movs	r1, #0
+ 80101c4:	5499      	strb	r1, [r3, r2]
+    disk.drv[disk.nbr] = drv;
+ 80101c6:	4b19      	ldr	r3, [pc, #100]	; (801022c <FATFS_LinkDriverEx+0x94>)
+ 80101c8:	7a5b      	ldrb	r3, [r3, #9]
+ 80101ca:	b2db      	uxtb	r3, r3
+ 80101cc:	4a17      	ldr	r2, [pc, #92]	; (801022c <FATFS_LinkDriverEx+0x94>)
+ 80101ce:	009b      	lsls	r3, r3, #2
+ 80101d0:	4413      	add	r3, r2
+ 80101d2:	68fa      	ldr	r2, [r7, #12]
+ 80101d4:	605a      	str	r2, [r3, #4]
+    disk.lun[disk.nbr] = lun;
+ 80101d6:	4b15      	ldr	r3, [pc, #84]	; (801022c <FATFS_LinkDriverEx+0x94>)
+ 80101d8:	7a5b      	ldrb	r3, [r3, #9]
+ 80101da:	b2db      	uxtb	r3, r3
+ 80101dc:	461a      	mov	r2, r3
+ 80101de:	4b13      	ldr	r3, [pc, #76]	; (801022c <FATFS_LinkDriverEx+0x94>)
+ 80101e0:	4413      	add	r3, r2
+ 80101e2:	79fa      	ldrb	r2, [r7, #7]
+ 80101e4:	721a      	strb	r2, [r3, #8]
+    DiskNum = disk.nbr++;
+ 80101e6:	4b11      	ldr	r3, [pc, #68]	; (801022c <FATFS_LinkDriverEx+0x94>)
+ 80101e8:	7a5b      	ldrb	r3, [r3, #9]
+ 80101ea:	b2db      	uxtb	r3, r3
+ 80101ec:	1c5a      	adds	r2, r3, #1
+ 80101ee:	b2d1      	uxtb	r1, r2
+ 80101f0:	4a0e      	ldr	r2, [pc, #56]	; (801022c <FATFS_LinkDriverEx+0x94>)
+ 80101f2:	7251      	strb	r1, [r2, #9]
+ 80101f4:	75bb      	strb	r3, [r7, #22]
+    path[0] = DiskNum + '0';
+ 80101f6:	7dbb      	ldrb	r3, [r7, #22]
+ 80101f8:	3330      	adds	r3, #48	; 0x30
+ 80101fa:	b2da      	uxtb	r2, r3
+ 80101fc:	68bb      	ldr	r3, [r7, #8]
+ 80101fe:	701a      	strb	r2, [r3, #0]
+    path[1] = ':';
+ 8010200:	68bb      	ldr	r3, [r7, #8]
+ 8010202:	3301      	adds	r3, #1
+ 8010204:	223a      	movs	r2, #58	; 0x3a
+ 8010206:	701a      	strb	r2, [r3, #0]
+    path[2] = '/';
+ 8010208:	68bb      	ldr	r3, [r7, #8]
+ 801020a:	3302      	adds	r3, #2
+ 801020c:	222f      	movs	r2, #47	; 0x2f
+ 801020e:	701a      	strb	r2, [r3, #0]
+    path[3] = 0;
+ 8010210:	68bb      	ldr	r3, [r7, #8]
+ 8010212:	3303      	adds	r3, #3
+ 8010214:	2200      	movs	r2, #0
+ 8010216:	701a      	strb	r2, [r3, #0]
+    ret = 0;
+ 8010218:	2300      	movs	r3, #0
+ 801021a:	75fb      	strb	r3, [r7, #23]
+  }
+
+  return ret;
+ 801021c:	7dfb      	ldrb	r3, [r7, #23]
+}
+ 801021e:	4618      	mov	r0, r3
+ 8010220:	371c      	adds	r7, #28
+ 8010222:	46bd      	mov	sp, r7
+ 8010224:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8010228:	4770      	bx	lr
+ 801022a:	bf00      	nop
+ 801022c:	2400bed4 	.word	0x2400bed4
+
+08010230 <FATFS_LinkDriver>:
+  * @param  drv: pointer to the disk IO Driver structure
+  * @param  path: pointer to the logical drive path
+  * @retval Returns 0 in case of success, otherwise 1.
+  */
+uint8_t FATFS_LinkDriver(const Diskio_drvTypeDef *drv, char *path)
+{
+ 8010230:	b580      	push	{r7, lr}
+ 8010232:	b082      	sub	sp, #8
+ 8010234:	af00      	add	r7, sp, #0
+ 8010236:	6078      	str	r0, [r7, #4]
+ 8010238:	6039      	str	r1, [r7, #0]
+  return FATFS_LinkDriverEx(drv, path, 0);
+ 801023a:	2200      	movs	r2, #0
+ 801023c:	6839      	ldr	r1, [r7, #0]
+ 801023e:	6878      	ldr	r0, [r7, #4]
+ 8010240:	f7ff ffaa 	bl	8010198 <FATFS_LinkDriverEx>
+ 8010244:	4603      	mov	r3, r0
+}
+ 8010246:	4618      	mov	r0, r3
+ 8010248:	3708      	adds	r7, #8
+ 801024a:	46bd      	mov	sp, r7
+ 801024c:	bd80      	pop	{r7, pc}
+
+0801024e <makeFreeRtosPriority>:
+
+extern void xPortSysTickHandler(void);
+
+/* Convert from CMSIS type osPriority to FreeRTOS priority number */
+static unsigned portBASE_TYPE makeFreeRtosPriority (osPriority priority)
+{
+ 801024e:	b480      	push	{r7}
+ 8010250:	b085      	sub	sp, #20
+ 8010252:	af00      	add	r7, sp, #0
+ 8010254:	4603      	mov	r3, r0
+ 8010256:	80fb      	strh	r3, [r7, #6]
+  unsigned portBASE_TYPE fpriority = tskIDLE_PRIORITY;
+ 8010258:	2300      	movs	r3, #0
+ 801025a:	60fb      	str	r3, [r7, #12]
+  
+  if (priority != osPriorityError) {
+ 801025c:	f9b7 3006 	ldrsh.w	r3, [r7, #6]
+ 8010260:	2b84      	cmp	r3, #132	; 0x84
+ 8010262:	d005      	beq.n	8010270 <makeFreeRtosPriority+0x22>
+    fpriority += (priority - osPriorityIdle);
+ 8010264:	f9b7 2006 	ldrsh.w	r2, [r7, #6]
+ 8010268:	68fb      	ldr	r3, [r7, #12]
+ 801026a:	4413      	add	r3, r2
+ 801026c:	3303      	adds	r3, #3
+ 801026e:	60fb      	str	r3, [r7, #12]
+  }
+  
+  return fpriority;
+ 8010270:	68fb      	ldr	r3, [r7, #12]
+}
+ 8010272:	4618      	mov	r0, r3
+ 8010274:	3714      	adds	r7, #20
+ 8010276:	46bd      	mov	sp, r7
+ 8010278:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 801027c:	4770      	bx	lr
+
+0801027e <inHandlerMode>:
+#endif
+
+
+/* Determine whether we are in thread mode or handler mode. */
+static int inHandlerMode (void)
+{
+ 801027e:	b480      	push	{r7}
+ 8010280:	b083      	sub	sp, #12
+ 8010282:	af00      	add	r7, sp, #0
+  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+ 8010284:	f3ef 8305 	mrs	r3, IPSR
+ 8010288:	607b      	str	r3, [r7, #4]
+  return(result);
+ 801028a:	687b      	ldr	r3, [r7, #4]
+  return __get_IPSR() != 0;
+ 801028c:	2b00      	cmp	r3, #0
+ 801028e:	bf14      	ite	ne
+ 8010290:	2301      	movne	r3, #1
+ 8010292:	2300      	moveq	r3, #0
+ 8010294:	b2db      	uxtb	r3, r3
+}
+ 8010296:	4618      	mov	r0, r3
+ 8010298:	370c      	adds	r7, #12
+ 801029a:	46bd      	mov	sp, r7
+ 801029c:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 80102a0:	4770      	bx	lr
+
+080102a2 <osKernelStart>:
+* @param  argument      pointer that is passed to the thread function as start argument.
+* @retval status code that indicates the execution status of the function
+* @note   MUST REMAIN UNCHANGED: \b osKernelStart shall be consistent in every CMSIS-RTOS.
+*/
+osStatus osKernelStart (void)
+{
+ 80102a2:	b580      	push	{r7, lr}
+ 80102a4:	af00      	add	r7, sp, #0
+  vTaskStartScheduler();
+ 80102a6:	f001 fd97 	bl	8011dd8 <vTaskStartScheduler>
+  
+  return osOK;
+ 80102aa:	2300      	movs	r3, #0
+}
+ 80102ac:	4618      	mov	r0, r3
+ 80102ae:	bd80      	pop	{r7, pc}
+
+080102b0 <osKernelRunning>:
+*         (1) RTOS is started
+*         (-1) if this feature is disabled in FreeRTOSConfig.h 
+* @note  MUST REMAIN UNCHANGED: \b osKernelRunning shall be consistent in every CMSIS-RTOS.
+*/
+int32_t osKernelRunning(void)
+{
+ 80102b0:	b580      	push	{r7, lr}
+ 80102b2:	af00      	add	r7, sp, #0
+#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
+  if (xTaskGetSchedulerState() == taskSCHEDULER_NOT_STARTED)
+ 80102b4:	f002 fa28 	bl	8012708 <xTaskGetSchedulerState>
+ 80102b8:	4603      	mov	r3, r0
+ 80102ba:	2b01      	cmp	r3, #1
+ 80102bc:	d101      	bne.n	80102c2 <osKernelRunning+0x12>
+    return 0;
+ 80102be:	2300      	movs	r3, #0
+ 80102c0:	e000      	b.n	80102c4 <osKernelRunning+0x14>
+  else
+    return 1;
+ 80102c2:	2301      	movs	r3, #1
+#else
+	return (-1);
+#endif	
+}
+ 80102c4:	4618      	mov	r0, r3
+ 80102c6:	bd80      	pop	{r7, pc}
+
+080102c8 <osKernelSysTick>:
+* @param  None
+* @retval None
+* @note   MUST REMAIN UNCHANGED: \b osKernelSysTick shall be consistent in every CMSIS-RTOS.
+*/
+uint32_t osKernelSysTick(void)
+{
+ 80102c8:	b580      	push	{r7, lr}
+ 80102ca:	af00      	add	r7, sp, #0
+  if (inHandlerMode()) {
+ 80102cc:	f7ff ffd7 	bl	801027e <inHandlerMode>
+ 80102d0:	4603      	mov	r3, r0
+ 80102d2:	2b00      	cmp	r3, #0
+ 80102d4:	d003      	beq.n	80102de <osKernelSysTick+0x16>
+    return xTaskGetTickCountFromISR();
+ 80102d6:	f001 fe9f 	bl	8012018 <xTaskGetTickCountFromISR>
+ 80102da:	4603      	mov	r3, r0
+ 80102dc:	e002      	b.n	80102e4 <osKernelSysTick+0x1c>
+  }
+  else {
+    return xTaskGetTickCount();
+ 80102de:	f001 fe8b 	bl	8011ff8 <xTaskGetTickCount>
+ 80102e2:	4603      	mov	r3, r0
+  }
+}
+ 80102e4:	4618      	mov	r0, r3
+ 80102e6:	bd80      	pop	{r7, pc}
+
+080102e8 <osThreadCreate>:
+* @param  argument      pointer that is passed to the thread function as start argument.
+* @retval thread ID for reference by other functions or NULL in case of error.
+* @note   MUST REMAIN UNCHANGED: \b osThreadCreate shall be consistent in every CMSIS-RTOS.
+*/
+osThreadId osThreadCreate (const osThreadDef_t *thread_def, void *argument)
+{
+ 80102e8:	b5f0      	push	{r4, r5, r6, r7, lr}
+ 80102ea:	b089      	sub	sp, #36	; 0x24
+ 80102ec:	af04      	add	r7, sp, #16
+ 80102ee:	6078      	str	r0, [r7, #4]
+ 80102f0:	6039      	str	r1, [r7, #0]
+  TaskHandle_t handle;
+  
+#if( configSUPPORT_STATIC_ALLOCATION == 1 ) &&  ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+  if((thread_def->buffer != NULL) && (thread_def->controlblock != NULL)) {
+ 80102f2:	687b      	ldr	r3, [r7, #4]
+ 80102f4:	695b      	ldr	r3, [r3, #20]
+ 80102f6:	2b00      	cmp	r3, #0
+ 80102f8:	d020      	beq.n	801033c <osThreadCreate+0x54>
+ 80102fa:	687b      	ldr	r3, [r7, #4]
+ 80102fc:	699b      	ldr	r3, [r3, #24]
+ 80102fe:	2b00      	cmp	r3, #0
+ 8010300:	d01c      	beq.n	801033c <osThreadCreate+0x54>
+    handle = xTaskCreateStatic((TaskFunction_t)thread_def->pthread,(const portCHAR *)thread_def->name,
+ 8010302:	687b      	ldr	r3, [r7, #4]
+ 8010304:	685c      	ldr	r4, [r3, #4]
+ 8010306:	687b      	ldr	r3, [r7, #4]
+ 8010308:	681d      	ldr	r5, [r3, #0]
+              thread_def->stacksize, argument, makeFreeRtosPriority(thread_def->tpriority),
+ 801030a:	687b      	ldr	r3, [r7, #4]
+ 801030c:	691e      	ldr	r6, [r3, #16]
+ 801030e:	687b      	ldr	r3, [r7, #4]
+ 8010310:	f9b3 3008 	ldrsh.w	r3, [r3, #8]
+    handle = xTaskCreateStatic((TaskFunction_t)thread_def->pthread,(const portCHAR *)thread_def->name,
+ 8010314:	4618      	mov	r0, r3
+ 8010316:	f7ff ff9a 	bl	801024e <makeFreeRtosPriority>
+ 801031a:	4601      	mov	r1, r0
+              thread_def->buffer, thread_def->controlblock);
+ 801031c:	687b      	ldr	r3, [r7, #4]
+ 801031e:	695b      	ldr	r3, [r3, #20]
+ 8010320:	687a      	ldr	r2, [r7, #4]
+ 8010322:	6992      	ldr	r2, [r2, #24]
+    handle = xTaskCreateStatic((TaskFunction_t)thread_def->pthread,(const portCHAR *)thread_def->name,
+ 8010324:	9202      	str	r2, [sp, #8]
+ 8010326:	9301      	str	r3, [sp, #4]
+ 8010328:	9100      	str	r1, [sp, #0]
+ 801032a:	683b      	ldr	r3, [r7, #0]
+ 801032c:	4632      	mov	r2, r6
+ 801032e:	4629      	mov	r1, r5
+ 8010330:	4620      	mov	r0, r4
+ 8010332:	f001 fb81 	bl	8011a38 <xTaskCreateStatic>
+ 8010336:	4603      	mov	r3, r0
+ 8010338:	60fb      	str	r3, [r7, #12]
+ 801033a:	e01c      	b.n	8010376 <osThreadCreate+0x8e>
+  }
+  else {
+    if (xTaskCreate((TaskFunction_t)thread_def->pthread,(const portCHAR *)thread_def->name,
+ 801033c:	687b      	ldr	r3, [r7, #4]
+ 801033e:	685c      	ldr	r4, [r3, #4]
+ 8010340:	687b      	ldr	r3, [r7, #4]
+ 8010342:	681d      	ldr	r5, [r3, #0]
+              thread_def->stacksize, argument, makeFreeRtosPriority(thread_def->tpriority),
+ 8010344:	687b      	ldr	r3, [r7, #4]
+ 8010346:	691b      	ldr	r3, [r3, #16]
+    if (xTaskCreate((TaskFunction_t)thread_def->pthread,(const portCHAR *)thread_def->name,
+ 8010348:	b29e      	uxth	r6, r3
+              thread_def->stacksize, argument, makeFreeRtosPriority(thread_def->tpriority),
+ 801034a:	687b      	ldr	r3, [r7, #4]
+ 801034c:	f9b3 3008 	ldrsh.w	r3, [r3, #8]
+    if (xTaskCreate((TaskFunction_t)thread_def->pthread,(const portCHAR *)thread_def->name,
+ 8010350:	4618      	mov	r0, r3
+ 8010352:	f7ff ff7c 	bl	801024e <makeFreeRtosPriority>
+ 8010356:	4602      	mov	r2, r0
+ 8010358:	f107 030c 	add.w	r3, r7, #12
+ 801035c:	9301      	str	r3, [sp, #4]
+ 801035e:	9200      	str	r2, [sp, #0]
+ 8010360:	683b      	ldr	r3, [r7, #0]
+ 8010362:	4632      	mov	r2, r6
+ 8010364:	4629      	mov	r1, r5
+ 8010366:	4620      	mov	r0, r4
+ 8010368:	f001 fbc3 	bl	8011af2 <xTaskCreate>
+ 801036c:	4603      	mov	r3, r0
+ 801036e:	2b01      	cmp	r3, #1
+ 8010370:	d001      	beq.n	8010376 <osThreadCreate+0x8e>
+              &handle) != pdPASS)  {
+      return NULL;
+ 8010372:	2300      	movs	r3, #0
+ 8010374:	e000      	b.n	8010378 <osThreadCreate+0x90>
+                   &handle) != pdPASS)  {
+    return NULL;
+  }     
+#endif
+  
+  return handle;
+ 8010376:	68fb      	ldr	r3, [r7, #12]
+}
+ 8010378:	4618      	mov	r0, r3
+ 801037a:	3714      	adds	r7, #20
+ 801037c:	46bd      	mov	sp, r7
+ 801037e:	bdf0      	pop	{r4, r5, r6, r7, pc}
+
+08010380 <osDelay>:
+* @brief   Wait for Timeout (Time Delay)
+* @param   millisec      time delay value
+* @retval  status code that indicates the execution status of the function.
+*/
+osStatus osDelay (uint32_t millisec)
+{
+ 8010380:	b580      	push	{r7, lr}
+ 8010382:	b084      	sub	sp, #16
+ 8010384:	af00      	add	r7, sp, #0
+ 8010386:	6078      	str	r0, [r7, #4]
+#if INCLUDE_vTaskDelay
+  TickType_t ticks = millisec / portTICK_PERIOD_MS;
+ 8010388:	687b      	ldr	r3, [r7, #4]
+ 801038a:	60fb      	str	r3, [r7, #12]
+  
+  vTaskDelay(ticks ? ticks : 1);          /* Minimum delay = 1 tick */
+ 801038c:	68fb      	ldr	r3, [r7, #12]
+ 801038e:	2b00      	cmp	r3, #0
+ 8010390:	d001      	beq.n	8010396 <osDelay+0x16>
+ 8010392:	68fb      	ldr	r3, [r7, #12]
+ 8010394:	e000      	b.n	8010398 <osDelay+0x18>
+ 8010396:	2301      	movs	r3, #1
+ 8010398:	4618      	mov	r0, r3
+ 801039a:	f001 fce9 	bl	8011d70 <vTaskDelay>
+  
+  return osOK;
+ 801039e:	2300      	movs	r3, #0
+#else
+  (void) millisec;
+  
+  return osErrorResource;
+#endif
+}
+ 80103a0:	4618      	mov	r0, r3
+ 80103a2:	3710      	adds	r7, #16
+ 80103a4:	46bd      	mov	sp, r7
+ 80103a6:	bd80      	pop	{r7, pc}
+
+080103a8 <osMutexCreate>:
+* @param  mutex_def     mutex definition referenced with \ref osMutex.
+* @retval  mutex ID for reference by other functions or NULL in case of error.
+* @note   MUST REMAIN UNCHANGED: \b osMutexCreate shall be consistent in every CMSIS-RTOS.
+*/
+osMutexId osMutexCreate (const osMutexDef_t *mutex_def)
+{
+ 80103a8:	b580      	push	{r7, lr}
+ 80103aa:	b082      	sub	sp, #8
+ 80103ac:	af00      	add	r7, sp, #0
+ 80103ae:	6078      	str	r0, [r7, #4]
+#if ( configUSE_MUTEXES == 1)
+
+#if( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+
+  if (mutex_def->controlblock != NULL) {
+ 80103b0:	687b      	ldr	r3, [r7, #4]
+ 80103b2:	685b      	ldr	r3, [r3, #4]
+ 80103b4:	2b00      	cmp	r3, #0
+ 80103b6:	d007      	beq.n	80103c8 <osMutexCreate+0x20>
+    return xSemaphoreCreateMutexStatic( mutex_def->controlblock );
+ 80103b8:	687b      	ldr	r3, [r7, #4]
+ 80103ba:	685b      	ldr	r3, [r3, #4]
+ 80103bc:	4619      	mov	r1, r3
+ 80103be:	2001      	movs	r0, #1
+ 80103c0:	f000 fc7d 	bl	8010cbe <xQueueCreateMutexStatic>
+ 80103c4:	4603      	mov	r3, r0
+ 80103c6:	e003      	b.n	80103d0 <osMutexCreate+0x28>
+     }
+  else {
+    return xSemaphoreCreateMutex(); 
+ 80103c8:	2001      	movs	r0, #1
+ 80103ca:	f000 fc60 	bl	8010c8e <xQueueCreateMutex>
+ 80103ce:	4603      	mov	r3, r0
+    return xSemaphoreCreateMutex(); 
+#endif
+#else
+  return NULL;
+#endif
+}
+ 80103d0:	4618      	mov	r0, r3
+ 80103d2:	3708      	adds	r7, #8
+ 80103d4:	46bd      	mov	sp, r7
+ 80103d6:	bd80      	pop	{r7, pc}
+
+080103d8 <osMutexWait>:
+* @param millisec      timeout value or 0 in case of no time-out.
+* @retval  status code that indicates the execution status of the function.
+* @note   MUST REMAIN UNCHANGED: \b osMutexWait shall be consistent in every CMSIS-RTOS.
+*/
+osStatus osMutexWait (osMutexId mutex_id, uint32_t millisec)
+{
+ 80103d8:	b580      	push	{r7, lr}
+ 80103da:	b084      	sub	sp, #16
+ 80103dc:	af00      	add	r7, sp, #0
+ 80103de:	6078      	str	r0, [r7, #4]
+ 80103e0:	6039      	str	r1, [r7, #0]
+  TickType_t ticks;
+  portBASE_TYPE taskWoken = pdFALSE;  
+ 80103e2:	2300      	movs	r3, #0
+ 80103e4:	60bb      	str	r3, [r7, #8]
+  
+  
+  if (mutex_id == NULL) {
+ 80103e6:	687b      	ldr	r3, [r7, #4]
+ 80103e8:	2b00      	cmp	r3, #0
+ 80103ea:	d101      	bne.n	80103f0 <osMutexWait+0x18>
+    return osErrorParameter;
+ 80103ec:	2380      	movs	r3, #128	; 0x80
+ 80103ee:	e03a      	b.n	8010466 <osMutexWait+0x8e>
+  }
+  
+  ticks = 0;
+ 80103f0:	2300      	movs	r3, #0
+ 80103f2:	60fb      	str	r3, [r7, #12]
+  if (millisec == osWaitForever) {
+ 80103f4:	683b      	ldr	r3, [r7, #0]
+ 80103f6:	f1b3 3fff 	cmp.w	r3, #4294967295
+ 80103fa:	d103      	bne.n	8010404 <osMutexWait+0x2c>
+    ticks = portMAX_DELAY;
+ 80103fc:	f04f 33ff 	mov.w	r3, #4294967295
+ 8010400:	60fb      	str	r3, [r7, #12]
+ 8010402:	e009      	b.n	8010418 <osMutexWait+0x40>
+  }
+  else if (millisec != 0) {
+ 8010404:	683b      	ldr	r3, [r7, #0]
+ 8010406:	2b00      	cmp	r3, #0
+ 8010408:	d006      	beq.n	8010418 <osMutexWait+0x40>
+    ticks = millisec / portTICK_PERIOD_MS;
+ 801040a:	683b      	ldr	r3, [r7, #0]
+ 801040c:	60fb      	str	r3, [r7, #12]
+    if (ticks == 0) {
+ 801040e:	68fb      	ldr	r3, [r7, #12]
+ 8010410:	2b00      	cmp	r3, #0
+ 8010412:	d101      	bne.n	8010418 <osMutexWait+0x40>
+      ticks = 1;
+ 8010414:	2301      	movs	r3, #1
+ 8010416:	60fb      	str	r3, [r7, #12]
+    }
+  }
+  
+  if (inHandlerMode()) {
+ 8010418:	f7ff ff31 	bl	801027e <inHandlerMode>
+ 801041c:	4603      	mov	r3, r0
+ 801041e:	2b00      	cmp	r3, #0
+ 8010420:	d017      	beq.n	8010452 <osMutexWait+0x7a>
+    if (xSemaphoreTakeFromISR(mutex_id, &taskWoken) != pdTRUE) {
+ 8010422:	f107 0308 	add.w	r3, r7, #8
+ 8010426:	461a      	mov	r2, r3
+ 8010428:	2100      	movs	r1, #0
+ 801042a:	6878      	ldr	r0, [r7, #4]
+ 801042c:	f001 f874 	bl	8011518 <xQueueReceiveFromISR>
+ 8010430:	4603      	mov	r3, r0
+ 8010432:	2b01      	cmp	r3, #1
+ 8010434:	d001      	beq.n	801043a <osMutexWait+0x62>
+      return osErrorOS;
+ 8010436:	23ff      	movs	r3, #255	; 0xff
+ 8010438:	e015      	b.n	8010466 <osMutexWait+0x8e>
+    }
+	portEND_SWITCHING_ISR(taskWoken);
+ 801043a:	68bb      	ldr	r3, [r7, #8]
+ 801043c:	2b00      	cmp	r3, #0
+ 801043e:	d011      	beq.n	8010464 <osMutexWait+0x8c>
+ 8010440:	4b0b      	ldr	r3, [pc, #44]	; (8010470 <osMutexWait+0x98>)
+ 8010442:	f04f 5280 	mov.w	r2, #268435456	; 0x10000000
+ 8010446:	601a      	str	r2, [r3, #0]
+ 8010448:	f3bf 8f4f 	dsb	sy
+ 801044c:	f3bf 8f6f 	isb	sy
+ 8010450:	e008      	b.n	8010464 <osMutexWait+0x8c>
+  } 
+  else if (xSemaphoreTake(mutex_id, ticks) != pdTRUE) {
+ 8010452:	68f9      	ldr	r1, [r7, #12]
+ 8010454:	6878      	ldr	r0, [r7, #4]
+ 8010456:	f000 ff53 	bl	8011300 <xQueueSemaphoreTake>
+ 801045a:	4603      	mov	r3, r0
+ 801045c:	2b01      	cmp	r3, #1
+ 801045e:	d001      	beq.n	8010464 <osMutexWait+0x8c>
+    return osErrorOS;
+ 8010460:	23ff      	movs	r3, #255	; 0xff
+ 8010462:	e000      	b.n	8010466 <osMutexWait+0x8e>
+  }
+  
+  return osOK;
+ 8010464:	2300      	movs	r3, #0
+}
+ 8010466:	4618      	mov	r0, r3
+ 8010468:	3710      	adds	r7, #16
+ 801046a:	46bd      	mov	sp, r7
+ 801046c:	bd80      	pop	{r7, pc}
+ 801046e:	bf00      	nop
+ 8010470:	e000ed04 	.word	0xe000ed04
+
+08010474 <osMutexRelease>:
+* @param mutex_id      mutex ID obtained by \ref osMutexCreate.
+* @retval  status code that indicates the execution status of the function.
+* @note   MUST REMAIN UNCHANGED: \b osMutexRelease shall be consistent in every CMSIS-RTOS.
+*/
+osStatus osMutexRelease (osMutexId mutex_id)
+{
+ 8010474:	b580      	push	{r7, lr}
+ 8010476:	b084      	sub	sp, #16
+ 8010478:	af00      	add	r7, sp, #0
+ 801047a:	6078      	str	r0, [r7, #4]
+  osStatus result = osOK;
+ 801047c:	2300      	movs	r3, #0
+ 801047e:	60fb      	str	r3, [r7, #12]
+  portBASE_TYPE taskWoken = pdFALSE;
+ 8010480:	2300      	movs	r3, #0
+ 8010482:	60bb      	str	r3, [r7, #8]
+  
+  if (inHandlerMode()) {
+ 8010484:	f7ff fefb 	bl	801027e <inHandlerMode>
+ 8010488:	4603      	mov	r3, r0
+ 801048a:	2b00      	cmp	r3, #0
+ 801048c:	d016      	beq.n	80104bc <osMutexRelease+0x48>
+    if (xSemaphoreGiveFromISR(mutex_id, &taskWoken) != pdTRUE) {
+ 801048e:	f107 0308 	add.w	r3, r7, #8
+ 8010492:	4619      	mov	r1, r3
+ 8010494:	6878      	ldr	r0, [r7, #4]
+ 8010496:	f000 fdc6 	bl	8011026 <xQueueGiveFromISR>
+ 801049a:	4603      	mov	r3, r0
+ 801049c:	2b01      	cmp	r3, #1
+ 801049e:	d001      	beq.n	80104a4 <osMutexRelease+0x30>
+      return osErrorOS;
+ 80104a0:	23ff      	movs	r3, #255	; 0xff
+ 80104a2:	e017      	b.n	80104d4 <osMutexRelease+0x60>
+    }
+    portEND_SWITCHING_ISR(taskWoken);
+ 80104a4:	68bb      	ldr	r3, [r7, #8]
+ 80104a6:	2b00      	cmp	r3, #0
+ 80104a8:	d013      	beq.n	80104d2 <osMutexRelease+0x5e>
+ 80104aa:	4b0c      	ldr	r3, [pc, #48]	; (80104dc <osMutexRelease+0x68>)
+ 80104ac:	f04f 5280 	mov.w	r2, #268435456	; 0x10000000
+ 80104b0:	601a      	str	r2, [r3, #0]
+ 80104b2:	f3bf 8f4f 	dsb	sy
+ 80104b6:	f3bf 8f6f 	isb	sy
+ 80104ba:	e00a      	b.n	80104d2 <osMutexRelease+0x5e>
+  }
+  else if (xSemaphoreGive(mutex_id) != pdTRUE) 
+ 80104bc:	2300      	movs	r3, #0
+ 80104be:	2200      	movs	r2, #0
+ 80104c0:	2100      	movs	r1, #0
+ 80104c2:	6878      	ldr	r0, [r7, #4]
+ 80104c4:	f000 fc16 	bl	8010cf4 <xQueueGenericSend>
+ 80104c8:	4603      	mov	r3, r0
+ 80104ca:	2b01      	cmp	r3, #1
+ 80104cc:	d001      	beq.n	80104d2 <osMutexRelease+0x5e>
+  {
+    result = osErrorOS;
+ 80104ce:	23ff      	movs	r3, #255	; 0xff
+ 80104d0:	60fb      	str	r3, [r7, #12]
+  }
+  return result;
+ 80104d2:	68fb      	ldr	r3, [r7, #12]
+}
+ 80104d4:	4618      	mov	r0, r3
+ 80104d6:	3710      	adds	r7, #16
+ 80104d8:	46bd      	mov	sp, r7
+ 80104da:	bd80      	pop	{r7, pc}
+ 80104dc:	e000ed04 	.word	0xe000ed04
+
+080104e0 <osSemaphoreCreate>:
+* @param count         number of available resources.
+* @retval  semaphore ID for reference by other functions or NULL in case of error.
+* @note   MUST REMAIN UNCHANGED: \b osSemaphoreCreate shall be consistent in every CMSIS-RTOS.
+*/
+osSemaphoreId osSemaphoreCreate (const osSemaphoreDef_t *semaphore_def, int32_t count)
+{ 
+ 80104e0:	b580      	push	{r7, lr}
+ 80104e2:	b086      	sub	sp, #24
+ 80104e4:	af02      	add	r7, sp, #8
+ 80104e6:	6078      	str	r0, [r7, #4]
+ 80104e8:	6039      	str	r1, [r7, #0]
+#if( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+
+  osSemaphoreId sema;
+  
+  if (semaphore_def->controlblock != NULL){
+ 80104ea:	687b      	ldr	r3, [r7, #4]
+ 80104ec:	685b      	ldr	r3, [r3, #4]
+ 80104ee:	2b00      	cmp	r3, #0
+ 80104f0:	d00f      	beq.n	8010512 <osSemaphoreCreate+0x32>
+    if (count == 1) {
+ 80104f2:	683b      	ldr	r3, [r7, #0]
+ 80104f4:	2b01      	cmp	r3, #1
+ 80104f6:	d10a      	bne.n	801050e <osSemaphoreCreate+0x2e>
+      return xSemaphoreCreateBinaryStatic( semaphore_def->controlblock );
+ 80104f8:	687b      	ldr	r3, [r7, #4]
+ 80104fa:	685b      	ldr	r3, [r3, #4]
+ 80104fc:	2203      	movs	r2, #3
+ 80104fe:	9200      	str	r2, [sp, #0]
+ 8010500:	2200      	movs	r2, #0
+ 8010502:	2100      	movs	r1, #0
+ 8010504:	2001      	movs	r0, #1
+ 8010506:	f000 fad7 	bl	8010ab8 <xQueueGenericCreateStatic>
+ 801050a:	4603      	mov	r3, r0
+ 801050c:	e016      	b.n	801053c <osSemaphoreCreate+0x5c>
+    }
+    else {
+#if (configUSE_COUNTING_SEMAPHORES == 1 )
+      return xSemaphoreCreateCountingStatic( count, count, semaphore_def->controlblock );
+#else
+      return NULL;
+ 801050e:	2300      	movs	r3, #0
+ 8010510:	e014      	b.n	801053c <osSemaphoreCreate+0x5c>
+#endif
+    }
+  }
+  else {
+    if (count == 1) {
+ 8010512:	683b      	ldr	r3, [r7, #0]
+ 8010514:	2b01      	cmp	r3, #1
+ 8010516:	d110      	bne.n	801053a <osSemaphoreCreate+0x5a>
+      vSemaphoreCreateBinary(sema);
+ 8010518:	2203      	movs	r2, #3
+ 801051a:	2100      	movs	r1, #0
+ 801051c:	2001      	movs	r0, #1
+ 801051e:	f000 fb43 	bl	8010ba8 <xQueueGenericCreate>
+ 8010522:	60f8      	str	r0, [r7, #12]
+ 8010524:	68fb      	ldr	r3, [r7, #12]
+ 8010526:	2b00      	cmp	r3, #0
+ 8010528:	d005      	beq.n	8010536 <osSemaphoreCreate+0x56>
+ 801052a:	2300      	movs	r3, #0
+ 801052c:	2200      	movs	r2, #0
+ 801052e:	2100      	movs	r1, #0
+ 8010530:	68f8      	ldr	r0, [r7, #12]
+ 8010532:	f000 fbdf 	bl	8010cf4 <xQueueGenericSend>
+      return sema;
+ 8010536:	68fb      	ldr	r3, [r7, #12]
+ 8010538:	e000      	b.n	801053c <osSemaphoreCreate+0x5c>
+    }
+    else {
+#if (configUSE_COUNTING_SEMAPHORES == 1 )	
+      return xSemaphoreCreateCounting(count, count);
+#else
+      return NULL;
+ 801053a:	2300      	movs	r3, #0
+#else
+    return NULL;
+#endif
+  }
+#endif
+}
+ 801053c:	4618      	mov	r0, r3
+ 801053e:	3710      	adds	r7, #16
+ 8010540:	46bd      	mov	sp, r7
+ 8010542:	bd80      	pop	{r7, pc}
+
+08010544 <osSemaphoreWait>:
+* @param  millisec      timeout value or 0 in case of no time-out.
+* @retval  number of available tokens, or -1 in case of incorrect parameters.
+* @note   MUST REMAIN UNCHANGED: \b osSemaphoreWait shall be consistent in every CMSIS-RTOS.
+*/
+int32_t osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec)
+{
+ 8010544:	b580      	push	{r7, lr}
+ 8010546:	b084      	sub	sp, #16
+ 8010548:	af00      	add	r7, sp, #0
+ 801054a:	6078      	str	r0, [r7, #4]
+ 801054c:	6039      	str	r1, [r7, #0]
+  TickType_t ticks;
+  portBASE_TYPE taskWoken = pdFALSE;  
+ 801054e:	2300      	movs	r3, #0
+ 8010550:	60bb      	str	r3, [r7, #8]
+  
+  
+  if (semaphore_id == NULL) {
+ 8010552:	687b      	ldr	r3, [r7, #4]
+ 8010554:	2b00      	cmp	r3, #0
+ 8010556:	d101      	bne.n	801055c <osSemaphoreWait+0x18>
+    return osErrorParameter;
+ 8010558:	2380      	movs	r3, #128	; 0x80
+ 801055a:	e03a      	b.n	80105d2 <osSemaphoreWait+0x8e>
+  }
+  
+  ticks = 0;
+ 801055c:	2300      	movs	r3, #0
+ 801055e:	60fb      	str	r3, [r7, #12]
+  if (millisec == osWaitForever) {
+ 8010560:	683b      	ldr	r3, [r7, #0]
+ 8010562:	f1b3 3fff 	cmp.w	r3, #4294967295
+ 8010566:	d103      	bne.n	8010570 <osSemaphoreWait+0x2c>
+    ticks = portMAX_DELAY;
+ 8010568:	f04f 33ff 	mov.w	r3, #4294967295
+ 801056c:	60fb      	str	r3, [r7, #12]
+ 801056e:	e009      	b.n	8010584 <osSemaphoreWait+0x40>
+  }
+  else if (millisec != 0) {
+ 8010570:	683b      	ldr	r3, [r7, #0]
+ 8010572:	2b00      	cmp	r3, #0
+ 8010574:	d006      	beq.n	8010584 <osSemaphoreWait+0x40>
+    ticks = millisec / portTICK_PERIOD_MS;
+ 8010576:	683b      	ldr	r3, [r7, #0]
+ 8010578:	60fb      	str	r3, [r7, #12]
+    if (ticks == 0) {
+ 801057a:	68fb      	ldr	r3, [r7, #12]
+ 801057c:	2b00      	cmp	r3, #0
+ 801057e:	d101      	bne.n	8010584 <osSemaphoreWait+0x40>
+      ticks = 1;
+ 8010580:	2301      	movs	r3, #1
+ 8010582:	60fb      	str	r3, [r7, #12]
+    }
+  }
+  
+  if (inHandlerMode()) {
+ 8010584:	f7ff fe7b 	bl	801027e <inHandlerMode>
+ 8010588:	4603      	mov	r3, r0
+ 801058a:	2b00      	cmp	r3, #0
+ 801058c:	d017      	beq.n	80105be <osSemaphoreWait+0x7a>
+    if (xSemaphoreTakeFromISR(semaphore_id, &taskWoken) != pdTRUE) {
+ 801058e:	f107 0308 	add.w	r3, r7, #8
+ 8010592:	461a      	mov	r2, r3
+ 8010594:	2100      	movs	r1, #0
+ 8010596:	6878      	ldr	r0, [r7, #4]
+ 8010598:	f000 ffbe 	bl	8011518 <xQueueReceiveFromISR>
+ 801059c:	4603      	mov	r3, r0
+ 801059e:	2b01      	cmp	r3, #1
+ 80105a0:	d001      	beq.n	80105a6 <osSemaphoreWait+0x62>
+      return osErrorOS;
+ 80105a2:	23ff      	movs	r3, #255	; 0xff
+ 80105a4:	e015      	b.n	80105d2 <osSemaphoreWait+0x8e>
+    }
+	portEND_SWITCHING_ISR(taskWoken);
+ 80105a6:	68bb      	ldr	r3, [r7, #8]
+ 80105a8:	2b00      	cmp	r3, #0
+ 80105aa:	d011      	beq.n	80105d0 <osSemaphoreWait+0x8c>
+ 80105ac:	4b0b      	ldr	r3, [pc, #44]	; (80105dc <osSemaphoreWait+0x98>)
+ 80105ae:	f04f 5280 	mov.w	r2, #268435456	; 0x10000000
+ 80105b2:	601a      	str	r2, [r3, #0]
+ 80105b4:	f3bf 8f4f 	dsb	sy
+ 80105b8:	f3bf 8f6f 	isb	sy
+ 80105bc:	e008      	b.n	80105d0 <osSemaphoreWait+0x8c>
+  }  
+  else if (xSemaphoreTake(semaphore_id, ticks) != pdTRUE) {
+ 80105be:	68f9      	ldr	r1, [r7, #12]
+ 80105c0:	6878      	ldr	r0, [r7, #4]
+ 80105c2:	f000 fe9d 	bl	8011300 <xQueueSemaphoreTake>
+ 80105c6:	4603      	mov	r3, r0
+ 80105c8:	2b01      	cmp	r3, #1
+ 80105ca:	d001      	beq.n	80105d0 <osSemaphoreWait+0x8c>
+    return osErrorOS;
+ 80105cc:	23ff      	movs	r3, #255	; 0xff
+ 80105ce:	e000      	b.n	80105d2 <osSemaphoreWait+0x8e>
+  }
+  
+  return osOK;
+ 80105d0:	2300      	movs	r3, #0
+}
+ 80105d2:	4618      	mov	r0, r3
+ 80105d4:	3710      	adds	r7, #16
+ 80105d6:	46bd      	mov	sp, r7
+ 80105d8:	bd80      	pop	{r7, pc}
+ 80105da:	bf00      	nop
+ 80105dc:	e000ed04 	.word	0xe000ed04
+
+080105e0 <osSemaphoreRelease>:
+* @param  semaphore_id  semaphore object referenced with \ref osSemaphore.
+* @retval  status code that indicates the execution status of the function.
+* @note   MUST REMAIN UNCHANGED: \b osSemaphoreRelease shall be consistent in every CMSIS-RTOS.
+*/
+osStatus osSemaphoreRelease (osSemaphoreId semaphore_id)
+{
+ 80105e0:	b580      	push	{r7, lr}
+ 80105e2:	b084      	sub	sp, #16
+ 80105e4:	af00      	add	r7, sp, #0
+ 80105e6:	6078      	str	r0, [r7, #4]
+  osStatus result = osOK;
+ 80105e8:	2300      	movs	r3, #0
+ 80105ea:	60fb      	str	r3, [r7, #12]
+  portBASE_TYPE taskWoken = pdFALSE;
+ 80105ec:	2300      	movs	r3, #0
+ 80105ee:	60bb      	str	r3, [r7, #8]
+  
+  
+  if (inHandlerMode()) {
+ 80105f0:	f7ff fe45 	bl	801027e <inHandlerMode>
+ 80105f4:	4603      	mov	r3, r0
+ 80105f6:	2b00      	cmp	r3, #0
+ 80105f8:	d016      	beq.n	8010628 <osSemaphoreRelease+0x48>
+    if (xSemaphoreGiveFromISR(semaphore_id, &taskWoken) != pdTRUE) {
+ 80105fa:	f107 0308 	add.w	r3, r7, #8
+ 80105fe:	4619      	mov	r1, r3
+ 8010600:	6878      	ldr	r0, [r7, #4]
+ 8010602:	f000 fd10 	bl	8011026 <xQueueGiveFromISR>
+ 8010606:	4603      	mov	r3, r0
+ 8010608:	2b01      	cmp	r3, #1
+ 801060a:	d001      	beq.n	8010610 <osSemaphoreRelease+0x30>
+      return osErrorOS;
+ 801060c:	23ff      	movs	r3, #255	; 0xff
+ 801060e:	e017      	b.n	8010640 <osSemaphoreRelease+0x60>
+    }
+    portEND_SWITCHING_ISR(taskWoken);
+ 8010610:	68bb      	ldr	r3, [r7, #8]
+ 8010612:	2b00      	cmp	r3, #0
+ 8010614:	d013      	beq.n	801063e <osSemaphoreRelease+0x5e>
+ 8010616:	4b0c      	ldr	r3, [pc, #48]	; (8010648 <osSemaphoreRelease+0x68>)
+ 8010618:	f04f 5280 	mov.w	r2, #268435456	; 0x10000000
+ 801061c:	601a      	str	r2, [r3, #0]
+ 801061e:	f3bf 8f4f 	dsb	sy
+ 8010622:	f3bf 8f6f 	isb	sy
+ 8010626:	e00a      	b.n	801063e <osSemaphoreRelease+0x5e>
+  }
+  else {
+    if (xSemaphoreGive(semaphore_id) != pdTRUE) {
+ 8010628:	2300      	movs	r3, #0
+ 801062a:	2200      	movs	r2, #0
+ 801062c:	2100      	movs	r1, #0
+ 801062e:	6878      	ldr	r0, [r7, #4]
+ 8010630:	f000 fb60 	bl	8010cf4 <xQueueGenericSend>
+ 8010634:	4603      	mov	r3, r0
+ 8010636:	2b01      	cmp	r3, #1
+ 8010638:	d001      	beq.n	801063e <osSemaphoreRelease+0x5e>
+      result = osErrorOS;
+ 801063a:	23ff      	movs	r3, #255	; 0xff
+ 801063c:	60fb      	str	r3, [r7, #12]
+    }
+  }
+  
+  return result;
+ 801063e:	68fb      	ldr	r3, [r7, #12]
+}
+ 8010640:	4618      	mov	r0, r3
+ 8010642:	3710      	adds	r7, #16
+ 8010644:	46bd      	mov	sp, r7
+ 8010646:	bd80      	pop	{r7, pc}
+ 8010648:	e000ed04 	.word	0xe000ed04
+
+0801064c <osSemaphoreDelete>:
+* @param  semaphore_id  semaphore object referenced with \ref osSemaphore.
+* @retval  status code that indicates the execution status of the function.
+* @note   MUST REMAIN UNCHANGED: \b osSemaphoreDelete shall be consistent in every CMSIS-RTOS.
+*/
+osStatus osSemaphoreDelete (osSemaphoreId semaphore_id)
+{
+ 801064c:	b580      	push	{r7, lr}
+ 801064e:	b082      	sub	sp, #8
+ 8010650:	af00      	add	r7, sp, #0
+ 8010652:	6078      	str	r0, [r7, #4]
+  if (inHandlerMode()) {
+ 8010654:	f7ff fe13 	bl	801027e <inHandlerMode>
+ 8010658:	4603      	mov	r3, r0
+ 801065a:	2b00      	cmp	r3, #0
+ 801065c:	d001      	beq.n	8010662 <osSemaphoreDelete+0x16>
+    return osErrorISR;
+ 801065e:	2382      	movs	r3, #130	; 0x82
+ 8010660:	e003      	b.n	801066a <osSemaphoreDelete+0x1e>
+  }
+
+  vSemaphoreDelete(semaphore_id);
+ 8010662:	6878      	ldr	r0, [r7, #4]
+ 8010664:	f001 f814 	bl	8011690 <vQueueDelete>
+
+  return osOK; 
+ 8010668:	2300      	movs	r3, #0
+}
+ 801066a:	4618      	mov	r0, r3
+ 801066c:	3708      	adds	r7, #8
+ 801066e:	46bd      	mov	sp, r7
+ 8010670:	bd80      	pop	{r7, pc}
+
+08010672 <osMessageCreate>:
+* @param  thread_id     thread ID (obtained by \ref osThreadCreate or \ref osThreadGetId) or NULL.
+* @retval  message queue ID for reference by other functions or NULL in case of error.
+* @note   MUST REMAIN UNCHANGED: \b osMessageCreate shall be consistent in every CMSIS-RTOS.
+*/
+osMessageQId osMessageCreate (const osMessageQDef_t *queue_def, osThreadId thread_id)
+{
+ 8010672:	b590      	push	{r4, r7, lr}
+ 8010674:	b085      	sub	sp, #20
+ 8010676:	af02      	add	r7, sp, #8
+ 8010678:	6078      	str	r0, [r7, #4]
+ 801067a:	6039      	str	r1, [r7, #0]
+  (void) thread_id;
+  
+#if( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+
+  if ((queue_def->buffer != NULL) && (queue_def->controlblock != NULL)) {
+ 801067c:	687b      	ldr	r3, [r7, #4]
+ 801067e:	689b      	ldr	r3, [r3, #8]
+ 8010680:	2b00      	cmp	r3, #0
+ 8010682:	d011      	beq.n	80106a8 <osMessageCreate+0x36>
+ 8010684:	687b      	ldr	r3, [r7, #4]
+ 8010686:	68db      	ldr	r3, [r3, #12]
+ 8010688:	2b00      	cmp	r3, #0
+ 801068a:	d00d      	beq.n	80106a8 <osMessageCreate+0x36>
+    return xQueueCreateStatic(queue_def->queue_sz, queue_def->item_sz, queue_def->buffer, queue_def->controlblock);
+ 801068c:	687b      	ldr	r3, [r7, #4]
+ 801068e:	6818      	ldr	r0, [r3, #0]
+ 8010690:	687b      	ldr	r3, [r7, #4]
+ 8010692:	6859      	ldr	r1, [r3, #4]
+ 8010694:	687b      	ldr	r3, [r7, #4]
+ 8010696:	689a      	ldr	r2, [r3, #8]
+ 8010698:	687b      	ldr	r3, [r7, #4]
+ 801069a:	68db      	ldr	r3, [r3, #12]
+ 801069c:	2400      	movs	r4, #0
+ 801069e:	9400      	str	r4, [sp, #0]
+ 80106a0:	f000 fa0a 	bl	8010ab8 <xQueueGenericCreateStatic>
+ 80106a4:	4603      	mov	r3, r0
+ 80106a6:	e008      	b.n	80106ba <osMessageCreate+0x48>
+  }
+  else {
+    return xQueueCreate(queue_def->queue_sz, queue_def->item_sz);
+ 80106a8:	687b      	ldr	r3, [r7, #4]
+ 80106aa:	6818      	ldr	r0, [r3, #0]
+ 80106ac:	687b      	ldr	r3, [r7, #4]
+ 80106ae:	685b      	ldr	r3, [r3, #4]
+ 80106b0:	2200      	movs	r2, #0
+ 80106b2:	4619      	mov	r1, r3
+ 80106b4:	f000 fa78 	bl	8010ba8 <xQueueGenericCreate>
+ 80106b8:	4603      	mov	r3, r0
+#elif ( configSUPPORT_STATIC_ALLOCATION == 1 )
+  return xQueueCreateStatic(queue_def->queue_sz, queue_def->item_sz, queue_def->buffer, queue_def->controlblock);
+#else  
+  return xQueueCreate(queue_def->queue_sz, queue_def->item_sz);
+#endif
+}
+ 80106ba:	4618      	mov	r0, r3
+ 80106bc:	370c      	adds	r7, #12
+ 80106be:	46bd      	mov	sp, r7
+ 80106c0:	bd90      	pop	{r4, r7, pc}
+	...
+
+080106c4 <osMessagePut>:
+* @param  millisec  timeout value or 0 in case of no time-out.
+* @retval status code that indicates the execution status of the function.
+* @note   MUST REMAIN UNCHANGED: \b osMessagePut shall be consistent in every CMSIS-RTOS.
+*/
+osStatus osMessagePut (osMessageQId queue_id, uint32_t info, uint32_t millisec)
+{
+ 80106c4:	b580      	push	{r7, lr}
+ 80106c6:	b086      	sub	sp, #24
+ 80106c8:	af00      	add	r7, sp, #0
+ 80106ca:	60f8      	str	r0, [r7, #12]
+ 80106cc:	60b9      	str	r1, [r7, #8]
+ 80106ce:	607a      	str	r2, [r7, #4]
+  portBASE_TYPE taskWoken = pdFALSE;
+ 80106d0:	2300      	movs	r3, #0
+ 80106d2:	613b      	str	r3, [r7, #16]
+  TickType_t ticks;
+  
+  ticks = millisec / portTICK_PERIOD_MS;
+ 80106d4:	687b      	ldr	r3, [r7, #4]
+ 80106d6:	617b      	str	r3, [r7, #20]
+  if (ticks == 0) {
+ 80106d8:	697b      	ldr	r3, [r7, #20]
+ 80106da:	2b00      	cmp	r3, #0
+ 80106dc:	d101      	bne.n	80106e2 <osMessagePut+0x1e>
+    ticks = 1;
+ 80106de:	2301      	movs	r3, #1
+ 80106e0:	617b      	str	r3, [r7, #20]
+  }
+  
+  if (inHandlerMode()) {
+ 80106e2:	f7ff fdcc 	bl	801027e <inHandlerMode>
+ 80106e6:	4603      	mov	r3, r0
+ 80106e8:	2b00      	cmp	r3, #0
+ 80106ea:	d018      	beq.n	801071e <osMessagePut+0x5a>
+    if (xQueueSendFromISR(queue_id, &info, &taskWoken) != pdTRUE) {
+ 80106ec:	f107 0210 	add.w	r2, r7, #16
+ 80106f0:	f107 0108 	add.w	r1, r7, #8
+ 80106f4:	2300      	movs	r3, #0
+ 80106f6:	68f8      	ldr	r0, [r7, #12]
+ 80106f8:	f000 fbfa 	bl	8010ef0 <xQueueGenericSendFromISR>
+ 80106fc:	4603      	mov	r3, r0
+ 80106fe:	2b01      	cmp	r3, #1
+ 8010700:	d001      	beq.n	8010706 <osMessagePut+0x42>
+      return osErrorOS;
+ 8010702:	23ff      	movs	r3, #255	; 0xff
+ 8010704:	e018      	b.n	8010738 <osMessagePut+0x74>
+    }
+    portEND_SWITCHING_ISR(taskWoken);
+ 8010706:	693b      	ldr	r3, [r7, #16]
+ 8010708:	2b00      	cmp	r3, #0
+ 801070a:	d014      	beq.n	8010736 <osMessagePut+0x72>
+ 801070c:	4b0c      	ldr	r3, [pc, #48]	; (8010740 <osMessagePut+0x7c>)
+ 801070e:	f04f 5280 	mov.w	r2, #268435456	; 0x10000000
+ 8010712:	601a      	str	r2, [r3, #0]
+ 8010714:	f3bf 8f4f 	dsb	sy
+ 8010718:	f3bf 8f6f 	isb	sy
+ 801071c:	e00b      	b.n	8010736 <osMessagePut+0x72>
+  }
+  else {
+    if (xQueueSend(queue_id, &info, ticks) != pdTRUE) {
+ 801071e:	f107 0108 	add.w	r1, r7, #8
+ 8010722:	2300      	movs	r3, #0
+ 8010724:	697a      	ldr	r2, [r7, #20]
+ 8010726:	68f8      	ldr	r0, [r7, #12]
+ 8010728:	f000 fae4 	bl	8010cf4 <xQueueGenericSend>
+ 801072c:	4603      	mov	r3, r0
+ 801072e:	2b01      	cmp	r3, #1
+ 8010730:	d001      	beq.n	8010736 <osMessagePut+0x72>
+      return osErrorOS;
+ 8010732:	23ff      	movs	r3, #255	; 0xff
+ 8010734:	e000      	b.n	8010738 <osMessagePut+0x74>
+    }
+  }
+  
+  return osOK;
+ 8010736:	2300      	movs	r3, #0
+}
+ 8010738:	4618      	mov	r0, r3
+ 801073a:	3718      	adds	r7, #24
+ 801073c:	46bd      	mov	sp, r7
+ 801073e:	bd80      	pop	{r7, pc}
+ 8010740:	e000ed04 	.word	0xe000ed04
+
+08010744 <osMessageGet>:
+* @param  millisec  timeout value or 0 in case of no time-out.
+* @retval event information that includes status code.
+* @note   MUST REMAIN UNCHANGED: \b osMessageGet shall be consistent in every CMSIS-RTOS.
+*/
+osEvent osMessageGet (osMessageQId queue_id, uint32_t millisec)
+{
+ 8010744:	b590      	push	{r4, r7, lr}
+ 8010746:	b08b      	sub	sp, #44	; 0x2c
+ 8010748:	af00      	add	r7, sp, #0
+ 801074a:	60f8      	str	r0, [r7, #12]
+ 801074c:	60b9      	str	r1, [r7, #8]
+ 801074e:	607a      	str	r2, [r7, #4]
+  portBASE_TYPE taskWoken;
+  TickType_t ticks;
+  osEvent event;
+  
+  event.def.message_id = queue_id;
+ 8010750:	68bb      	ldr	r3, [r7, #8]
+ 8010752:	61fb      	str	r3, [r7, #28]
+  event.value.v = 0;
+ 8010754:	2300      	movs	r3, #0
+ 8010756:	61bb      	str	r3, [r7, #24]
+  
+  if (queue_id == NULL) {
+ 8010758:	68bb      	ldr	r3, [r7, #8]
+ 801075a:	2b00      	cmp	r3, #0
+ 801075c:	d10a      	bne.n	8010774 <osMessageGet+0x30>
+    event.status = osErrorParameter;
+ 801075e:	2380      	movs	r3, #128	; 0x80
+ 8010760:	617b      	str	r3, [r7, #20]
+    return event;
+ 8010762:	68fb      	ldr	r3, [r7, #12]
+ 8010764:	461c      	mov	r4, r3
+ 8010766:	f107 0314 	add.w	r3, r7, #20
+ 801076a:	e893 0007 	ldmia.w	r3, {r0, r1, r2}
+ 801076e:	e884 0007 	stmia.w	r4, {r0, r1, r2}
+ 8010772:	e054      	b.n	801081e <osMessageGet+0xda>
+  }
+  
+  taskWoken = pdFALSE;
+ 8010774:	2300      	movs	r3, #0
+ 8010776:	623b      	str	r3, [r7, #32]
+  
+  ticks = 0;
+ 8010778:	2300      	movs	r3, #0
+ 801077a:	627b      	str	r3, [r7, #36]	; 0x24
+  if (millisec == osWaitForever) {
+ 801077c:	687b      	ldr	r3, [r7, #4]
+ 801077e:	f1b3 3fff 	cmp.w	r3, #4294967295
+ 8010782:	d103      	bne.n	801078c <osMessageGet+0x48>
+    ticks = portMAX_DELAY;
+ 8010784:	f04f 33ff 	mov.w	r3, #4294967295
+ 8010788:	627b      	str	r3, [r7, #36]	; 0x24
+ 801078a:	e009      	b.n	80107a0 <osMessageGet+0x5c>
+  }
+  else if (millisec != 0) {
+ 801078c:	687b      	ldr	r3, [r7, #4]
+ 801078e:	2b00      	cmp	r3, #0
+ 8010790:	d006      	beq.n	80107a0 <osMessageGet+0x5c>
+    ticks = millisec / portTICK_PERIOD_MS;
+ 8010792:	687b      	ldr	r3, [r7, #4]
+ 8010794:	627b      	str	r3, [r7, #36]	; 0x24
+    if (ticks == 0) {
+ 8010796:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 8010798:	2b00      	cmp	r3, #0
+ 801079a:	d101      	bne.n	80107a0 <osMessageGet+0x5c>
+      ticks = 1;
+ 801079c:	2301      	movs	r3, #1
+ 801079e:	627b      	str	r3, [r7, #36]	; 0x24
+    }
+  }
+  
+  if (inHandlerMode()) {
+ 80107a0:	f7ff fd6d 	bl	801027e <inHandlerMode>
+ 80107a4:	4603      	mov	r3, r0
+ 80107a6:	2b00      	cmp	r3, #0
+ 80107a8:	d01c      	beq.n	80107e4 <osMessageGet+0xa0>
+    if (xQueueReceiveFromISR(queue_id, &event.value.v, &taskWoken) == pdTRUE) {
+ 80107aa:	f107 0220 	add.w	r2, r7, #32
+ 80107ae:	f107 0314 	add.w	r3, r7, #20
+ 80107b2:	3304      	adds	r3, #4
+ 80107b4:	4619      	mov	r1, r3
+ 80107b6:	68b8      	ldr	r0, [r7, #8]
+ 80107b8:	f000 feae 	bl	8011518 <xQueueReceiveFromISR>
+ 80107bc:	4603      	mov	r3, r0
+ 80107be:	2b01      	cmp	r3, #1
+ 80107c0:	d102      	bne.n	80107c8 <osMessageGet+0x84>
+      /* We have mail */
+      event.status = osEventMessage;
+ 80107c2:	2310      	movs	r3, #16
+ 80107c4:	617b      	str	r3, [r7, #20]
+ 80107c6:	e001      	b.n	80107cc <osMessageGet+0x88>
+    }
+    else {
+      event.status = osOK;
+ 80107c8:	2300      	movs	r3, #0
+ 80107ca:	617b      	str	r3, [r7, #20]
+    }
+    portEND_SWITCHING_ISR(taskWoken);
+ 80107cc:	6a3b      	ldr	r3, [r7, #32]
+ 80107ce:	2b00      	cmp	r3, #0
+ 80107d0:	d01d      	beq.n	801080e <osMessageGet+0xca>
+ 80107d2:	4b15      	ldr	r3, [pc, #84]	; (8010828 <osMessageGet+0xe4>)
+ 80107d4:	f04f 5280 	mov.w	r2, #268435456	; 0x10000000
+ 80107d8:	601a      	str	r2, [r3, #0]
+ 80107da:	f3bf 8f4f 	dsb	sy
+ 80107de:	f3bf 8f6f 	isb	sy
+ 80107e2:	e014      	b.n	801080e <osMessageGet+0xca>
+  }
+  else {
+    if (xQueueReceive(queue_id, &event.value.v, ticks) == pdTRUE) {
+ 80107e4:	f107 0314 	add.w	r3, r7, #20
+ 80107e8:	3304      	adds	r3, #4
+ 80107ea:	6a7a      	ldr	r2, [r7, #36]	; 0x24
+ 80107ec:	4619      	mov	r1, r3
+ 80107ee:	68b8      	ldr	r0, [r7, #8]
+ 80107f0:	f000 fca6 	bl	8011140 <xQueueReceive>
+ 80107f4:	4603      	mov	r3, r0
+ 80107f6:	2b01      	cmp	r3, #1
+ 80107f8:	d102      	bne.n	8010800 <osMessageGet+0xbc>
+      /* We have mail */
+      event.status = osEventMessage;
+ 80107fa:	2310      	movs	r3, #16
+ 80107fc:	617b      	str	r3, [r7, #20]
+ 80107fe:	e006      	b.n	801080e <osMessageGet+0xca>
+    }
+    else {
+      event.status = (ticks == 0) ? osOK : osEventTimeout;
+ 8010800:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 8010802:	2b00      	cmp	r3, #0
+ 8010804:	d101      	bne.n	801080a <osMessageGet+0xc6>
+ 8010806:	2300      	movs	r3, #0
+ 8010808:	e000      	b.n	801080c <osMessageGet+0xc8>
+ 801080a:	2340      	movs	r3, #64	; 0x40
+ 801080c:	617b      	str	r3, [r7, #20]
+    }
+  }
+  
+  return event;
+ 801080e:	68fb      	ldr	r3, [r7, #12]
+ 8010810:	461c      	mov	r4, r3
+ 8010812:	f107 0314 	add.w	r3, r7, #20
+ 8010816:	e893 0007 	ldmia.w	r3, {r0, r1, r2}
+ 801081a:	e884 0007 	stmia.w	r4, {r0, r1, r2}
+}
+ 801081e:	68f8      	ldr	r0, [r7, #12]
+ 8010820:	372c      	adds	r7, #44	; 0x2c
+ 8010822:	46bd      	mov	sp, r7
+ 8010824:	bd90      	pop	{r4, r7, pc}
+ 8010826:	bf00      	nop
+ 8010828:	e000ed04 	.word	0xe000ed04
+
+0801082c <osMessageWaiting>:
+* @brief  Get the number of messaged stored in a queue.
+* @param  queue_id  message queue ID obtained with \ref osMessageCreate.
+* @retval number of messages stored in a queue.
+*/
+uint32_t osMessageWaiting(osMessageQId queue_id)
+{
+ 801082c:	b580      	push	{r7, lr}
+ 801082e:	b082      	sub	sp, #8
+ 8010830:	af00      	add	r7, sp, #0
+ 8010832:	6078      	str	r0, [r7, #4]
+  if (inHandlerMode()) {
+ 8010834:	f7ff fd23 	bl	801027e <inHandlerMode>
+ 8010838:	4603      	mov	r3, r0
+ 801083a:	2b00      	cmp	r3, #0
+ 801083c:	d004      	beq.n	8010848 <osMessageWaiting+0x1c>
+    return uxQueueMessagesWaitingFromISR(queue_id);
+ 801083e:	6878      	ldr	r0, [r7, #4]
+ 8010840:	f000 ff08 	bl	8011654 <uxQueueMessagesWaitingFromISR>
+ 8010844:	4603      	mov	r3, r0
+ 8010846:	e003      	b.n	8010850 <osMessageWaiting+0x24>
+  }
+  else
+  {
+    return uxQueueMessagesWaiting(queue_id);
+ 8010848:	6878      	ldr	r0, [r7, #4]
+ 801084a:	f000 fee5 	bl	8011618 <uxQueueMessagesWaiting>
+ 801084e:	4603      	mov	r3, r0
+  }
+}
+ 8010850:	4618      	mov	r0, r3
+ 8010852:	3708      	adds	r7, #8
+ 8010854:	46bd      	mov	sp, r7
+ 8010856:	bd80      	pop	{r7, pc}
+
+08010858 <osMessageDelete>:
+* @brief Delete a Message Queue
+* @param  queue_id  message queue ID obtained with \ref osMessageCreate.
+* @retval  status code that indicates the execution status of the function.
+*/
+osStatus osMessageDelete (osMessageQId queue_id)
+{
+ 8010858:	b580      	push	{r7, lr}
+ 801085a:	b082      	sub	sp, #8
+ 801085c:	af00      	add	r7, sp, #0
+ 801085e:	6078      	str	r0, [r7, #4]
+  if (inHandlerMode()) {
+ 8010860:	f7ff fd0d 	bl	801027e <inHandlerMode>
+ 8010864:	4603      	mov	r3, r0
+ 8010866:	2b00      	cmp	r3, #0
+ 8010868:	d001      	beq.n	801086e <osMessageDelete+0x16>
+    return osErrorISR;
+ 801086a:	2382      	movs	r3, #130	; 0x82
+ 801086c:	e003      	b.n	8010876 <osMessageDelete+0x1e>
+  }
+
+  vQueueDelete(queue_id);
+ 801086e:	6878      	ldr	r0, [r7, #4]
+ 8010870:	f000 ff0e 	bl	8011690 <vQueueDelete>
+
+  return osOK; 
+ 8010874:	2300      	movs	r3, #0
+}
+ 8010876:	4618      	mov	r0, r3
+ 8010878:	3708      	adds	r7, #8
+ 801087a:	46bd      	mov	sp, r7
+ 801087c:	bd80      	pop	{r7, pc}
+
+0801087e <vListInitialise>:
+/*-----------------------------------------------------------
+ * PUBLIC LIST API documented in list.h
+ *----------------------------------------------------------*/
+
+void vListInitialise( List_t * const pxList )
+{
+ 801087e:	b480      	push	{r7}
+ 8010880:	b083      	sub	sp, #12
+ 8010882:	af00      	add	r7, sp, #0
+ 8010884:	6078      	str	r0, [r7, #4]
+	/* The list structure contains a list item which is used to mark the
+	end of the list.  To initialise the list the list end is inserted
+	as the only list entry. */
+	pxList->pxIndex = ( ListItem_t * ) &( pxList->xListEnd );			/*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM.  This is checked and valid. */
+ 8010886:	687b      	ldr	r3, [r7, #4]
+ 8010888:	f103 0208 	add.w	r2, r3, #8
+ 801088c:	687b      	ldr	r3, [r7, #4]
+ 801088e:	605a      	str	r2, [r3, #4]
+
+	/* The list end value is the highest possible value in the list to
+	ensure it remains at the end of the list. */
+	pxList->xListEnd.xItemValue = portMAX_DELAY;
+ 8010890:	687b      	ldr	r3, [r7, #4]
+ 8010892:	f04f 32ff 	mov.w	r2, #4294967295
+ 8010896:	609a      	str	r2, [r3, #8]
+
+	/* The list end next and previous pointers point to itself so we know
+	when the list is empty. */
+	pxList->xListEnd.pxNext = ( ListItem_t * ) &( pxList->xListEnd );	/*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM.  This is checked and valid. */
+ 8010898:	687b      	ldr	r3, [r7, #4]
+ 801089a:	f103 0208 	add.w	r2, r3, #8
+ 801089e:	687b      	ldr	r3, [r7, #4]
+ 80108a0:	60da      	str	r2, [r3, #12]
+	pxList->xListEnd.pxPrevious = ( ListItem_t * ) &( pxList->xListEnd );/*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM.  This is checked and valid. */
+ 80108a2:	687b      	ldr	r3, [r7, #4]
+ 80108a4:	f103 0208 	add.w	r2, r3, #8
+ 80108a8:	687b      	ldr	r3, [r7, #4]
+ 80108aa:	611a      	str	r2, [r3, #16]
+
+	pxList->uxNumberOfItems = ( UBaseType_t ) 0U;
+ 80108ac:	687b      	ldr	r3, [r7, #4]
+ 80108ae:	2200      	movs	r2, #0
+ 80108b0:	601a      	str	r2, [r3, #0]
+
+	/* Write known values into the list if
+	configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
+	listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList );
+	listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList );
+}
+ 80108b2:	bf00      	nop
+ 80108b4:	370c      	adds	r7, #12
+ 80108b6:	46bd      	mov	sp, r7
+ 80108b8:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 80108bc:	4770      	bx	lr
+
+080108be <vListInitialiseItem>:
+/*-----------------------------------------------------------*/
+
+void vListInitialiseItem( ListItem_t * const pxItem )
+{
+ 80108be:	b480      	push	{r7}
+ 80108c0:	b083      	sub	sp, #12
+ 80108c2:	af00      	add	r7, sp, #0
+ 80108c4:	6078      	str	r0, [r7, #4]
+	/* Make sure the list item is not recorded as being on a list. */
+	pxItem->pxContainer = NULL;
+ 80108c6:	687b      	ldr	r3, [r7, #4]
+ 80108c8:	2200      	movs	r2, #0
+ 80108ca:	611a      	str	r2, [r3, #16]
+
+	/* Write known values into the list item if
+	configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
+	listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem );
+	listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem );
+}
+ 80108cc:	bf00      	nop
+ 80108ce:	370c      	adds	r7, #12
+ 80108d0:	46bd      	mov	sp, r7
+ 80108d2:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 80108d6:	4770      	bx	lr
+
+080108d8 <vListInsertEnd>:
+/*-----------------------------------------------------------*/
+
+void vListInsertEnd( List_t * const pxList, ListItem_t * const pxNewListItem )
+{
+ 80108d8:	b480      	push	{r7}
+ 80108da:	b085      	sub	sp, #20
+ 80108dc:	af00      	add	r7, sp, #0
+ 80108de:	6078      	str	r0, [r7, #4]
+ 80108e0:	6039      	str	r1, [r7, #0]
+ListItem_t * const pxIndex = pxList->pxIndex;
+ 80108e2:	687b      	ldr	r3, [r7, #4]
+ 80108e4:	685b      	ldr	r3, [r3, #4]
+ 80108e6:	60fb      	str	r3, [r7, #12]
+	listTEST_LIST_ITEM_INTEGRITY( pxNewListItem );
+
+	/* Insert a new list item into pxList, but rather than sort the list,
+	makes the new list item the last item to be removed by a call to
+	listGET_OWNER_OF_NEXT_ENTRY(). */
+	pxNewListItem->pxNext = pxIndex;
+ 80108e8:	683b      	ldr	r3, [r7, #0]
+ 80108ea:	68fa      	ldr	r2, [r7, #12]
+ 80108ec:	605a      	str	r2, [r3, #4]
+	pxNewListItem->pxPrevious = pxIndex->pxPrevious;
+ 80108ee:	68fb      	ldr	r3, [r7, #12]
+ 80108f0:	689a      	ldr	r2, [r3, #8]
+ 80108f2:	683b      	ldr	r3, [r7, #0]
+ 80108f4:	609a      	str	r2, [r3, #8]
+
+	/* Only used during decision coverage testing. */
+	mtCOVERAGE_TEST_DELAY();
+
+	pxIndex->pxPrevious->pxNext = pxNewListItem;
+ 80108f6:	68fb      	ldr	r3, [r7, #12]
+ 80108f8:	689b      	ldr	r3, [r3, #8]
+ 80108fa:	683a      	ldr	r2, [r7, #0]
+ 80108fc:	605a      	str	r2, [r3, #4]
+	pxIndex->pxPrevious = pxNewListItem;
+ 80108fe:	68fb      	ldr	r3, [r7, #12]
+ 8010900:	683a      	ldr	r2, [r7, #0]
+ 8010902:	609a      	str	r2, [r3, #8]
+
+	/* Remember which list the item is in. */
+	pxNewListItem->pxContainer = pxList;
+ 8010904:	683b      	ldr	r3, [r7, #0]
+ 8010906:	687a      	ldr	r2, [r7, #4]
+ 8010908:	611a      	str	r2, [r3, #16]
+
+	( pxList->uxNumberOfItems )++;
+ 801090a:	687b      	ldr	r3, [r7, #4]
+ 801090c:	681b      	ldr	r3, [r3, #0]
+ 801090e:	1c5a      	adds	r2, r3, #1
+ 8010910:	687b      	ldr	r3, [r7, #4]
+ 8010912:	601a      	str	r2, [r3, #0]
+}
+ 8010914:	bf00      	nop
+ 8010916:	3714      	adds	r7, #20
+ 8010918:	46bd      	mov	sp, r7
+ 801091a:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 801091e:	4770      	bx	lr
+
+08010920 <vListInsert>:
+/*-----------------------------------------------------------*/
+
+void vListInsert( List_t * const pxList, ListItem_t * const pxNewListItem )
+{
+ 8010920:	b480      	push	{r7}
+ 8010922:	b085      	sub	sp, #20
+ 8010924:	af00      	add	r7, sp, #0
+ 8010926:	6078      	str	r0, [r7, #4]
+ 8010928:	6039      	str	r1, [r7, #0]
+ListItem_t *pxIterator;
+const TickType_t xValueOfInsertion = pxNewListItem->xItemValue;
+ 801092a:	683b      	ldr	r3, [r7, #0]
+ 801092c:	681b      	ldr	r3, [r3, #0]
+ 801092e:	60bb      	str	r3, [r7, #8]
+	new list item should be placed after it.  This ensures that TCBs which are
+	stored in ready lists (all of which have the same xItemValue value) get a
+	share of the CPU.  However, if the xItemValue is the same as the back marker
+	the iteration loop below will not end.  Therefore the value is checked
+	first, and the algorithm slightly modified if necessary. */
+	if( xValueOfInsertion == portMAX_DELAY )
+ 8010930:	68bb      	ldr	r3, [r7, #8]
+ 8010932:	f1b3 3fff 	cmp.w	r3, #4294967295
+ 8010936:	d103      	bne.n	8010940 <vListInsert+0x20>
+	{
+		pxIterator = pxList->xListEnd.pxPrevious;
+ 8010938:	687b      	ldr	r3, [r7, #4]
+ 801093a:	691b      	ldr	r3, [r3, #16]
+ 801093c:	60fb      	str	r3, [r7, #12]
+ 801093e:	e00c      	b.n	801095a <vListInsert+0x3a>
+			4) Using a queue or semaphore before it has been initialised or
+			   before the scheduler has been started (are interrupts firing
+			   before vTaskStartScheduler() has been called?).
+		**********************************************************************/
+
+		for( pxIterator = ( ListItem_t * ) &( pxList->xListEnd ); pxIterator->pxNext->xItemValue <= xValueOfInsertion; pxIterator = pxIterator->pxNext ) /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM.  This is checked and valid. *//*lint !e440 The iterator moves to a different value, not xValueOfInsertion. */
+ 8010940:	687b      	ldr	r3, [r7, #4]
+ 8010942:	3308      	adds	r3, #8
+ 8010944:	60fb      	str	r3, [r7, #12]
+ 8010946:	e002      	b.n	801094e <vListInsert+0x2e>
+ 8010948:	68fb      	ldr	r3, [r7, #12]
+ 801094a:	685b      	ldr	r3, [r3, #4]
+ 801094c:	60fb      	str	r3, [r7, #12]
+ 801094e:	68fb      	ldr	r3, [r7, #12]
+ 8010950:	685b      	ldr	r3, [r3, #4]
+ 8010952:	681b      	ldr	r3, [r3, #0]
+ 8010954:	68ba      	ldr	r2, [r7, #8]
+ 8010956:	429a      	cmp	r2, r3
+ 8010958:	d2f6      	bcs.n	8010948 <vListInsert+0x28>
+			/* There is nothing to do here, just iterating to the wanted
+			insertion position. */
+		}
+	}
+
+	pxNewListItem->pxNext = pxIterator->pxNext;
+ 801095a:	68fb      	ldr	r3, [r7, #12]
+ 801095c:	685a      	ldr	r2, [r3, #4]
+ 801095e:	683b      	ldr	r3, [r7, #0]
+ 8010960:	605a      	str	r2, [r3, #4]
+	pxNewListItem->pxNext->pxPrevious = pxNewListItem;
+ 8010962:	683b      	ldr	r3, [r7, #0]
+ 8010964:	685b      	ldr	r3, [r3, #4]
+ 8010966:	683a      	ldr	r2, [r7, #0]
+ 8010968:	609a      	str	r2, [r3, #8]
+	pxNewListItem->pxPrevious = pxIterator;
+ 801096a:	683b      	ldr	r3, [r7, #0]
+ 801096c:	68fa      	ldr	r2, [r7, #12]
+ 801096e:	609a      	str	r2, [r3, #8]
+	pxIterator->pxNext = pxNewListItem;
+ 8010970:	68fb      	ldr	r3, [r7, #12]
+ 8010972:	683a      	ldr	r2, [r7, #0]
+ 8010974:	605a      	str	r2, [r3, #4]
+
+	/* Remember which list the item is in.  This allows fast removal of the
+	item later. */
+	pxNewListItem->pxContainer = pxList;
+ 8010976:	683b      	ldr	r3, [r7, #0]
+ 8010978:	687a      	ldr	r2, [r7, #4]
+ 801097a:	611a      	str	r2, [r3, #16]
+
+	( pxList->uxNumberOfItems )++;
+ 801097c:	687b      	ldr	r3, [r7, #4]
+ 801097e:	681b      	ldr	r3, [r3, #0]
+ 8010980:	1c5a      	adds	r2, r3, #1
+ 8010982:	687b      	ldr	r3, [r7, #4]
+ 8010984:	601a      	str	r2, [r3, #0]
+}
+ 8010986:	bf00      	nop
+ 8010988:	3714      	adds	r7, #20
+ 801098a:	46bd      	mov	sp, r7
+ 801098c:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8010990:	4770      	bx	lr
+
+08010992 <uxListRemove>:
+/*-----------------------------------------------------------*/
+
+UBaseType_t uxListRemove( ListItem_t * const pxItemToRemove )
+{
+ 8010992:	b480      	push	{r7}
+ 8010994:	b085      	sub	sp, #20
+ 8010996:	af00      	add	r7, sp, #0
+ 8010998:	6078      	str	r0, [r7, #4]
+/* The list item knows which list it is in.  Obtain the list from the list
+item. */
+List_t * const pxList = pxItemToRemove->pxContainer;
+ 801099a:	687b      	ldr	r3, [r7, #4]
+ 801099c:	691b      	ldr	r3, [r3, #16]
+ 801099e:	60fb      	str	r3, [r7, #12]
+
+	pxItemToRemove->pxNext->pxPrevious = pxItemToRemove->pxPrevious;
+ 80109a0:	687b      	ldr	r3, [r7, #4]
+ 80109a2:	685b      	ldr	r3, [r3, #4]
+ 80109a4:	687a      	ldr	r2, [r7, #4]
+ 80109a6:	6892      	ldr	r2, [r2, #8]
+ 80109a8:	609a      	str	r2, [r3, #8]
+	pxItemToRemove->pxPrevious->pxNext = pxItemToRemove->pxNext;
+ 80109aa:	687b      	ldr	r3, [r7, #4]
+ 80109ac:	689b      	ldr	r3, [r3, #8]
+ 80109ae:	687a      	ldr	r2, [r7, #4]
+ 80109b0:	6852      	ldr	r2, [r2, #4]
+ 80109b2:	605a      	str	r2, [r3, #4]
+
+	/* Only used during decision coverage testing. */
+	mtCOVERAGE_TEST_DELAY();
+
+	/* Make sure the index is left pointing to a valid item. */
+	if( pxList->pxIndex == pxItemToRemove )
+ 80109b4:	68fb      	ldr	r3, [r7, #12]
+ 80109b6:	685b      	ldr	r3, [r3, #4]
+ 80109b8:	687a      	ldr	r2, [r7, #4]
+ 80109ba:	429a      	cmp	r2, r3
+ 80109bc:	d103      	bne.n	80109c6 <uxListRemove+0x34>
+	{
+		pxList->pxIndex = pxItemToRemove->pxPrevious;
+ 80109be:	687b      	ldr	r3, [r7, #4]
+ 80109c0:	689a      	ldr	r2, [r3, #8]
+ 80109c2:	68fb      	ldr	r3, [r7, #12]
+ 80109c4:	605a      	str	r2, [r3, #4]
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	pxItemToRemove->pxContainer = NULL;
+ 80109c6:	687b      	ldr	r3, [r7, #4]
+ 80109c8:	2200      	movs	r2, #0
+ 80109ca:	611a      	str	r2, [r3, #16]
+	( pxList->uxNumberOfItems )--;
+ 80109cc:	68fb      	ldr	r3, [r7, #12]
+ 80109ce:	681b      	ldr	r3, [r3, #0]
+ 80109d0:	1e5a      	subs	r2, r3, #1
+ 80109d2:	68fb      	ldr	r3, [r7, #12]
+ 80109d4:	601a      	str	r2, [r3, #0]
+
+	return pxList->uxNumberOfItems;
+ 80109d6:	68fb      	ldr	r3, [r7, #12]
+ 80109d8:	681b      	ldr	r3, [r3, #0]
+}
+ 80109da:	4618      	mov	r0, r3
+ 80109dc:	3714      	adds	r7, #20
+ 80109de:	46bd      	mov	sp, r7
+ 80109e0:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 80109e4:	4770      	bx	lr
+	...
+
+080109e8 <xQueueGenericReset>:
+	}														\
+	taskEXIT_CRITICAL()
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueGenericReset( QueueHandle_t xQueue, BaseType_t xNewQueue )
+{
+ 80109e8:	b580      	push	{r7, lr}
+ 80109ea:	b084      	sub	sp, #16
+ 80109ec:	af00      	add	r7, sp, #0
+ 80109ee:	6078      	str	r0, [r7, #4]
+ 80109f0:	6039      	str	r1, [r7, #0]
+Queue_t * const pxQueue = xQueue;
+ 80109f2:	687b      	ldr	r3, [r7, #4]
+ 80109f4:	60fb      	str	r3, [r7, #12]
+
+	configASSERT( pxQueue );
+ 80109f6:	68fb      	ldr	r3, [r7, #12]
+ 80109f8:	2b00      	cmp	r3, #0
+ 80109fa:	d10a      	bne.n	8010a12 <xQueueGenericReset+0x2a>
+
+portFORCE_INLINE static void vPortRaiseBASEPRI( void )
+{
+uint32_t ulNewBASEPRI;
+
+	__asm volatile
+ 80109fc:	f04f 0350 	mov.w	r3, #80	; 0x50
+ 8010a00:	f383 8811 	msr	BASEPRI, r3
+ 8010a04:	f3bf 8f6f 	isb	sy
+ 8010a08:	f3bf 8f4f 	dsb	sy
+ 8010a0c:	60bb      	str	r3, [r7, #8]
+		"	msr basepri, %0											\n" \
+		"	isb														\n" \
+		"	dsb														\n" \
+		:"=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
+	);
+}
+ 8010a0e:	bf00      	nop
+ 8010a10:	e7fe      	b.n	8010a10 <xQueueGenericReset+0x28>
+
+	taskENTER_CRITICAL();
+ 8010a12:	f002 fcf7 	bl	8013404 <vPortEnterCritical>
+	{
+		pxQueue->u.xQueue.pcTail = pxQueue->pcHead + ( pxQueue->uxLength * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
+ 8010a16:	68fb      	ldr	r3, [r7, #12]
+ 8010a18:	681a      	ldr	r2, [r3, #0]
+ 8010a1a:	68fb      	ldr	r3, [r7, #12]
+ 8010a1c:	6bdb      	ldr	r3, [r3, #60]	; 0x3c
+ 8010a1e:	68f9      	ldr	r1, [r7, #12]
+ 8010a20:	6c09      	ldr	r1, [r1, #64]	; 0x40
+ 8010a22:	fb01 f303 	mul.w	r3, r1, r3
+ 8010a26:	441a      	add	r2, r3
+ 8010a28:	68fb      	ldr	r3, [r7, #12]
+ 8010a2a:	609a      	str	r2, [r3, #8]
+		pxQueue->uxMessagesWaiting = ( UBaseType_t ) 0U;
+ 8010a2c:	68fb      	ldr	r3, [r7, #12]
+ 8010a2e:	2200      	movs	r2, #0
+ 8010a30:	639a      	str	r2, [r3, #56]	; 0x38
+		pxQueue->pcWriteTo = pxQueue->pcHead;
+ 8010a32:	68fb      	ldr	r3, [r7, #12]
+ 8010a34:	681a      	ldr	r2, [r3, #0]
+ 8010a36:	68fb      	ldr	r3, [r7, #12]
+ 8010a38:	605a      	str	r2, [r3, #4]
+		pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead + ( ( pxQueue->uxLength - 1U ) * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
+ 8010a3a:	68fb      	ldr	r3, [r7, #12]
+ 8010a3c:	681a      	ldr	r2, [r3, #0]
+ 8010a3e:	68fb      	ldr	r3, [r7, #12]
+ 8010a40:	6bdb      	ldr	r3, [r3, #60]	; 0x3c
+ 8010a42:	3b01      	subs	r3, #1
+ 8010a44:	68f9      	ldr	r1, [r7, #12]
+ 8010a46:	6c09      	ldr	r1, [r1, #64]	; 0x40
+ 8010a48:	fb01 f303 	mul.w	r3, r1, r3
+ 8010a4c:	441a      	add	r2, r3
+ 8010a4e:	68fb      	ldr	r3, [r7, #12]
+ 8010a50:	60da      	str	r2, [r3, #12]
+		pxQueue->cRxLock = queueUNLOCKED;
+ 8010a52:	68fb      	ldr	r3, [r7, #12]
+ 8010a54:	22ff      	movs	r2, #255	; 0xff
+ 8010a56:	f883 2044 	strb.w	r2, [r3, #68]	; 0x44
+		pxQueue->cTxLock = queueUNLOCKED;
+ 8010a5a:	68fb      	ldr	r3, [r7, #12]
+ 8010a5c:	22ff      	movs	r2, #255	; 0xff
+ 8010a5e:	f883 2045 	strb.w	r2, [r3, #69]	; 0x45
+
+		if( xNewQueue == pdFALSE )
+ 8010a62:	683b      	ldr	r3, [r7, #0]
+ 8010a64:	2b00      	cmp	r3, #0
+ 8010a66:	d114      	bne.n	8010a92 <xQueueGenericReset+0xaa>
+			/* If there are tasks blocked waiting to read from the queue, then
+			the tasks will remain blocked as after this function exits the queue
+			will still be empty.  If there are tasks blocked waiting to write to
+			the queue, then one should be unblocked as after this function exits
+			it will be possible to write to it. */
+			if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
+ 8010a68:	68fb      	ldr	r3, [r7, #12]
+ 8010a6a:	691b      	ldr	r3, [r3, #16]
+ 8010a6c:	2b00      	cmp	r3, #0
+ 8010a6e:	d01a      	beq.n	8010aa6 <xQueueGenericReset+0xbe>
+			{
+				if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
+ 8010a70:	68fb      	ldr	r3, [r7, #12]
+ 8010a72:	3310      	adds	r3, #16
+ 8010a74:	4618      	mov	r0, r3
+ 8010a76:	f001 fc53 	bl	8012320 <xTaskRemoveFromEventList>
+ 8010a7a:	4603      	mov	r3, r0
+ 8010a7c:	2b00      	cmp	r3, #0
+ 8010a7e:	d012      	beq.n	8010aa6 <xQueueGenericReset+0xbe>
+				{
+					queueYIELD_IF_USING_PREEMPTION();
+ 8010a80:	4b0c      	ldr	r3, [pc, #48]	; (8010ab4 <xQueueGenericReset+0xcc>)
+ 8010a82:	f04f 5280 	mov.w	r2, #268435456	; 0x10000000
+ 8010a86:	601a      	str	r2, [r3, #0]
+ 8010a88:	f3bf 8f4f 	dsb	sy
+ 8010a8c:	f3bf 8f6f 	isb	sy
+ 8010a90:	e009      	b.n	8010aa6 <xQueueGenericReset+0xbe>
+			}
+		}
+		else
+		{
+			/* Ensure the event queues start in the correct state. */
+			vListInitialise( &( pxQueue->xTasksWaitingToSend ) );
+ 8010a92:	68fb      	ldr	r3, [r7, #12]
+ 8010a94:	3310      	adds	r3, #16
+ 8010a96:	4618      	mov	r0, r3
+ 8010a98:	f7ff fef1 	bl	801087e <vListInitialise>
+			vListInitialise( &( pxQueue->xTasksWaitingToReceive ) );
+ 8010a9c:	68fb      	ldr	r3, [r7, #12]
+ 8010a9e:	3324      	adds	r3, #36	; 0x24
+ 8010aa0:	4618      	mov	r0, r3
+ 8010aa2:	f7ff feec 	bl	801087e <vListInitialise>
+		}
+	}
+	taskEXIT_CRITICAL();
+ 8010aa6:	f002 fcdd 	bl	8013464 <vPortExitCritical>
+
+	/* A value is returned for calling semantic consistency with previous
+	versions. */
+	return pdPASS;
+ 8010aaa:	2301      	movs	r3, #1
+}
+ 8010aac:	4618      	mov	r0, r3
+ 8010aae:	3710      	adds	r7, #16
+ 8010ab0:	46bd      	mov	sp, r7
+ 8010ab2:	bd80      	pop	{r7, pc}
+ 8010ab4:	e000ed04 	.word	0xe000ed04
+
+08010ab8 <xQueueGenericCreateStatic>:
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+
+	QueueHandle_t xQueueGenericCreateStatic( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, StaticQueue_t *pxStaticQueue, const uint8_t ucQueueType )
+	{
+ 8010ab8:	b580      	push	{r7, lr}
+ 8010aba:	b08e      	sub	sp, #56	; 0x38
+ 8010abc:	af02      	add	r7, sp, #8
+ 8010abe:	60f8      	str	r0, [r7, #12]
+ 8010ac0:	60b9      	str	r1, [r7, #8]
+ 8010ac2:	607a      	str	r2, [r7, #4]
+ 8010ac4:	603b      	str	r3, [r7, #0]
+	Queue_t *pxNewQueue;
+
+		configASSERT( uxQueueLength > ( UBaseType_t ) 0 );
+ 8010ac6:	68fb      	ldr	r3, [r7, #12]
+ 8010ac8:	2b00      	cmp	r3, #0
+ 8010aca:	d10a      	bne.n	8010ae2 <xQueueGenericCreateStatic+0x2a>
+	__asm volatile
+ 8010acc:	f04f 0350 	mov.w	r3, #80	; 0x50
+ 8010ad0:	f383 8811 	msr	BASEPRI, r3
+ 8010ad4:	f3bf 8f6f 	isb	sy
+ 8010ad8:	f3bf 8f4f 	dsb	sy
+ 8010adc:	62bb      	str	r3, [r7, #40]	; 0x28
+}
+ 8010ade:	bf00      	nop
+ 8010ae0:	e7fe      	b.n	8010ae0 <xQueueGenericCreateStatic+0x28>
+
+		/* The StaticQueue_t structure and the queue storage area must be
+		supplied. */
+		configASSERT( pxStaticQueue != NULL );
+ 8010ae2:	683b      	ldr	r3, [r7, #0]
+ 8010ae4:	2b00      	cmp	r3, #0
+ 8010ae6:	d10a      	bne.n	8010afe <xQueueGenericCreateStatic+0x46>
+	__asm volatile
+ 8010ae8:	f04f 0350 	mov.w	r3, #80	; 0x50
+ 8010aec:	f383 8811 	msr	BASEPRI, r3
+ 8010af0:	f3bf 8f6f 	isb	sy
+ 8010af4:	f3bf 8f4f 	dsb	sy
+ 8010af8:	627b      	str	r3, [r7, #36]	; 0x24
+}
+ 8010afa:	bf00      	nop
+ 8010afc:	e7fe      	b.n	8010afc <xQueueGenericCreateStatic+0x44>
+
+		/* A queue storage area should be provided if the item size is not 0, and
+		should not be provided if the item size is 0. */
+		configASSERT( !( ( pucQueueStorage != NULL ) && ( uxItemSize == 0 ) ) );
+ 8010afe:	687b      	ldr	r3, [r7, #4]
+ 8010b00:	2b00      	cmp	r3, #0
+ 8010b02:	d002      	beq.n	8010b0a <xQueueGenericCreateStatic+0x52>
+ 8010b04:	68bb      	ldr	r3, [r7, #8]
+ 8010b06:	2b00      	cmp	r3, #0
+ 8010b08:	d001      	beq.n	8010b0e <xQueueGenericCreateStatic+0x56>
+ 8010b0a:	2301      	movs	r3, #1
+ 8010b0c:	e000      	b.n	8010b10 <xQueueGenericCreateStatic+0x58>
+ 8010b0e:	2300      	movs	r3, #0
+ 8010b10:	2b00      	cmp	r3, #0
+ 8010b12:	d10a      	bne.n	8010b2a <xQueueGenericCreateStatic+0x72>
+	__asm volatile
+ 8010b14:	f04f 0350 	mov.w	r3, #80	; 0x50
+ 8010b18:	f383 8811 	msr	BASEPRI, r3
+ 8010b1c:	f3bf 8f6f 	isb	sy
+ 8010b20:	f3bf 8f4f 	dsb	sy
+ 8010b24:	623b      	str	r3, [r7, #32]
+}
+ 8010b26:	bf00      	nop
+ 8010b28:	e7fe      	b.n	8010b28 <xQueueGenericCreateStatic+0x70>
+		configASSERT( !( ( pucQueueStorage == NULL ) && ( uxItemSize != 0 ) ) );
+ 8010b2a:	687b      	ldr	r3, [r7, #4]
+ 8010b2c:	2b00      	cmp	r3, #0
+ 8010b2e:	d102      	bne.n	8010b36 <xQueueGenericCreateStatic+0x7e>
+ 8010b30:	68bb      	ldr	r3, [r7, #8]
+ 8010b32:	2b00      	cmp	r3, #0
+ 8010b34:	d101      	bne.n	8010b3a <xQueueGenericCreateStatic+0x82>
+ 8010b36:	2301      	movs	r3, #1
+ 8010b38:	e000      	b.n	8010b3c <xQueueGenericCreateStatic+0x84>
+ 8010b3a:	2300      	movs	r3, #0
+ 8010b3c:	2b00      	cmp	r3, #0
+ 8010b3e:	d10a      	bne.n	8010b56 <xQueueGenericCreateStatic+0x9e>
+	__asm volatile
+ 8010b40:	f04f 0350 	mov.w	r3, #80	; 0x50
+ 8010b44:	f383 8811 	msr	BASEPRI, r3
+ 8010b48:	f3bf 8f6f 	isb	sy
+ 8010b4c:	f3bf 8f4f 	dsb	sy
+ 8010b50:	61fb      	str	r3, [r7, #28]
+}
+ 8010b52:	bf00      	nop
+ 8010b54:	e7fe      	b.n	8010b54 <xQueueGenericCreateStatic+0x9c>
+		#if( configASSERT_DEFINED == 1 )
+		{
+			/* Sanity check that the size of the structure used to declare a
+			variable of type StaticQueue_t or StaticSemaphore_t equals the size of
+			the real queue and semaphore structures. */
+			volatile size_t xSize = sizeof( StaticQueue_t );
+ 8010b56:	2348      	movs	r3, #72	; 0x48
+ 8010b58:	617b      	str	r3, [r7, #20]
+			configASSERT( xSize == sizeof( Queue_t ) );
+ 8010b5a:	697b      	ldr	r3, [r7, #20]
+ 8010b5c:	2b48      	cmp	r3, #72	; 0x48
+ 8010b5e:	d00a      	beq.n	8010b76 <xQueueGenericCreateStatic+0xbe>
+	__asm volatile
+ 8010b60:	f04f 0350 	mov.w	r3, #80	; 0x50
+ 8010b64:	f383 8811 	msr	BASEPRI, r3
+ 8010b68:	f3bf 8f6f 	isb	sy
+ 8010b6c:	f3bf 8f4f 	dsb	sy
+ 8010b70:	61bb      	str	r3, [r7, #24]
+}
+ 8010b72:	bf00      	nop
+ 8010b74:	e7fe      	b.n	8010b74 <xQueueGenericCreateStatic+0xbc>
+			( void ) xSize; /* Keeps lint quiet when configASSERT() is not defined. */
+ 8010b76:	697b      	ldr	r3, [r7, #20]
+		#endif /* configASSERT_DEFINED */
+
+		/* The address of a statically allocated queue was passed in, use it.
+		The address of a statically allocated storage area was also passed in
+		but is already set. */
+		pxNewQueue = ( Queue_t * ) pxStaticQueue; /*lint !e740 !e9087 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */
+ 8010b78:	683b      	ldr	r3, [r7, #0]
+ 8010b7a:	62fb      	str	r3, [r7, #44]	; 0x2c
+
+		if( pxNewQueue != NULL )
+ 8010b7c:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 8010b7e:	2b00      	cmp	r3, #0
+ 8010b80:	d00d      	beq.n	8010b9e <xQueueGenericCreateStatic+0xe6>
+			#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+			{
+				/* Queues can be allocated wither statically or dynamically, so
+				note this queue was allocated statically in case the queue is
+				later deleted. */
+				pxNewQueue->ucStaticallyAllocated = pdTRUE;
+ 8010b82:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 8010b84:	2201      	movs	r2, #1
+ 8010b86:	f883 2046 	strb.w	r2, [r3, #70]	; 0x46
+			}
+			#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+
+			prvInitialiseNewQueue( uxQueueLength, uxItemSize, pucQueueStorage, ucQueueType, pxNewQueue );
+ 8010b8a:	f897 2038 	ldrb.w	r2, [r7, #56]	; 0x38
+ 8010b8e:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 8010b90:	9300      	str	r3, [sp, #0]
+ 8010b92:	4613      	mov	r3, r2
+ 8010b94:	687a      	ldr	r2, [r7, #4]
+ 8010b96:	68b9      	ldr	r1, [r7, #8]
+ 8010b98:	68f8      	ldr	r0, [r7, #12]
+ 8010b9a:	f000 f83f 	bl	8010c1c <prvInitialiseNewQueue>
+		{
+			traceQUEUE_CREATE_FAILED( ucQueueType );
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		return pxNewQueue;
+ 8010b9e:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+	}
+ 8010ba0:	4618      	mov	r0, r3
+ 8010ba2:	3730      	adds	r7, #48	; 0x30
+ 8010ba4:	46bd      	mov	sp, r7
+ 8010ba6:	bd80      	pop	{r7, pc}
+
+08010ba8 <xQueueGenericCreate>:
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+
+	QueueHandle_t xQueueGenericCreate( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, const uint8_t ucQueueType )
+	{
+ 8010ba8:	b580      	push	{r7, lr}
+ 8010baa:	b08a      	sub	sp, #40	; 0x28
+ 8010bac:	af02      	add	r7, sp, #8
+ 8010bae:	60f8      	str	r0, [r7, #12]
+ 8010bb0:	60b9      	str	r1, [r7, #8]
+ 8010bb2:	4613      	mov	r3, r2
+ 8010bb4:	71fb      	strb	r3, [r7, #7]
+	Queue_t *pxNewQueue;
+	size_t xQueueSizeInBytes;
+	uint8_t *pucQueueStorage;
+
+		configASSERT( uxQueueLength > ( UBaseType_t ) 0 );
+ 8010bb6:	68fb      	ldr	r3, [r7, #12]
+ 8010bb8:	2b00      	cmp	r3, #0
+ 8010bba:	d10a      	bne.n	8010bd2 <xQueueGenericCreate+0x2a>
+	__asm volatile
+ 8010bbc:	f04f 0350 	mov.w	r3, #80	; 0x50
+ 8010bc0:	f383 8811 	msr	BASEPRI, r3
+ 8010bc4:	f3bf 8f6f 	isb	sy
+ 8010bc8:	f3bf 8f4f 	dsb	sy
+ 8010bcc:	613b      	str	r3, [r7, #16]
+}
+ 8010bce:	bf00      	nop
+ 8010bd0:	e7fe      	b.n	8010bd0 <xQueueGenericCreate+0x28>
+
+		/* Allocate enough space to hold the maximum number of items that
+		can be in the queue at any time.  It is valid for uxItemSize to be
+		zero in the case the queue is used as a semaphore. */
+		xQueueSizeInBytes = ( size_t ) ( uxQueueLength * uxItemSize ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+ 8010bd2:	68fb      	ldr	r3, [r7, #12]
+ 8010bd4:	68ba      	ldr	r2, [r7, #8]
+ 8010bd6:	fb02 f303 	mul.w	r3, r2, r3
+ 8010bda:	61fb      	str	r3, [r7, #28]
+		alignment requirements of the Queue_t structure - which in this case
+		is an int8_t *.  Therefore, whenever the stack alignment requirements
+		are greater than or equal to the pointer to char requirements the cast
+		is safe.  In other cases alignment requirements are not strict (one or
+		two bytes). */
+		pxNewQueue = ( Queue_t * ) pvPortMalloc( sizeof( Queue_t ) + xQueueSizeInBytes ); /*lint !e9087 !e9079 see comment above. */
+ 8010bdc:	69fb      	ldr	r3, [r7, #28]
+ 8010bde:	3348      	adds	r3, #72	; 0x48
+ 8010be0:	4618      	mov	r0, r3
+ 8010be2:	f002 fd31 	bl	8013648 <pvPortMalloc>
+ 8010be6:	61b8      	str	r0, [r7, #24]
+
+		if( pxNewQueue != NULL )
+ 8010be8:	69bb      	ldr	r3, [r7, #24]
+ 8010bea:	2b00      	cmp	r3, #0
+ 8010bec:	d011      	beq.n	8010c12 <xQueueGenericCreate+0x6a>
+		{
+			/* Jump past the queue structure to find the location of the queue
+			storage area. */
+			pucQueueStorage = ( uint8_t * ) pxNewQueue;
+ 8010bee:	69bb      	ldr	r3, [r7, #24]
+ 8010bf0:	617b      	str	r3, [r7, #20]
+			pucQueueStorage += sizeof( Queue_t ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
+ 8010bf2:	697b      	ldr	r3, [r7, #20]
+ 8010bf4:	3348      	adds	r3, #72	; 0x48
+ 8010bf6:	617b      	str	r3, [r7, #20]
+			#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+			{
+				/* Queues can be created either statically or dynamically, so
+				note this task was created dynamically in case it is later
+				deleted. */
+				pxNewQueue->ucStaticallyAllocated = pdFALSE;
+ 8010bf8:	69bb      	ldr	r3, [r7, #24]
+ 8010bfa:	2200      	movs	r2, #0
+ 8010bfc:	f883 2046 	strb.w	r2, [r3, #70]	; 0x46
+			}
+			#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+			prvInitialiseNewQueue( uxQueueLength, uxItemSize, pucQueueStorage, ucQueueType, pxNewQueue );
+ 8010c00:	79fa      	ldrb	r2, [r7, #7]
+ 8010c02:	69bb      	ldr	r3, [r7, #24]
+ 8010c04:	9300      	str	r3, [sp, #0]
+ 8010c06:	4613      	mov	r3, r2
+ 8010c08:	697a      	ldr	r2, [r7, #20]
+ 8010c0a:	68b9      	ldr	r1, [r7, #8]
+ 8010c0c:	68f8      	ldr	r0, [r7, #12]
+ 8010c0e:	f000 f805 	bl	8010c1c <prvInitialiseNewQueue>
+		{
+			traceQUEUE_CREATE_FAILED( ucQueueType );
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		return pxNewQueue;
+ 8010c12:	69bb      	ldr	r3, [r7, #24]
+	}
+ 8010c14:	4618      	mov	r0, r3
+ 8010c16:	3720      	adds	r7, #32
+ 8010c18:	46bd      	mov	sp, r7
+ 8010c1a:	bd80      	pop	{r7, pc}
+
+08010c1c <prvInitialiseNewQueue>:
+
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, const uint8_t ucQueueType, Queue_t *pxNewQueue )
+{
+ 8010c1c:	b580      	push	{r7, lr}
+ 8010c1e:	b084      	sub	sp, #16
+ 8010c20:	af00      	add	r7, sp, #0
+ 8010c22:	60f8      	str	r0, [r7, #12]
+ 8010c24:	60b9      	str	r1, [r7, #8]
+ 8010c26:	607a      	str	r2, [r7, #4]
+ 8010c28:	70fb      	strb	r3, [r7, #3]
+	/* Remove compiler warnings about unused parameters should
+	configUSE_TRACE_FACILITY not be set to 1. */
+	( void ) ucQueueType;
+
+	if( uxItemSize == ( UBaseType_t ) 0 )
+ 8010c2a:	68bb      	ldr	r3, [r7, #8]
+ 8010c2c:	2b00      	cmp	r3, #0
+ 8010c2e:	d103      	bne.n	8010c38 <prvInitialiseNewQueue+0x1c>
+	{
+		/* No RAM was allocated for the queue storage area, but PC head cannot
+		be set to NULL because NULL is used as a key to say the queue is used as
+		a mutex.  Therefore just set pcHead to point to the queue as a benign
+		value that is known to be within the memory map. */
+		pxNewQueue->pcHead = ( int8_t * ) pxNewQueue;
+ 8010c30:	69bb      	ldr	r3, [r7, #24]
+ 8010c32:	69ba      	ldr	r2, [r7, #24]
+ 8010c34:	601a      	str	r2, [r3, #0]
+ 8010c36:	e002      	b.n	8010c3e <prvInitialiseNewQueue+0x22>
+	}
+	else
+	{
+		/* Set the head to the start of the queue storage area. */
+		pxNewQueue->pcHead = ( int8_t * ) pucQueueStorage;
+ 8010c38:	69bb      	ldr	r3, [r7, #24]
+ 8010c3a:	687a      	ldr	r2, [r7, #4]
+ 8010c3c:	601a      	str	r2, [r3, #0]
+	}
+
+	/* Initialise the queue members as described where the queue type is
+	defined. */
+	pxNewQueue->uxLength = uxQueueLength;
+ 8010c3e:	69bb      	ldr	r3, [r7, #24]
+ 8010c40:	68fa      	ldr	r2, [r7, #12]
+ 8010c42:	63da      	str	r2, [r3, #60]	; 0x3c
+	pxNewQueue->uxItemSize = uxItemSize;
+ 8010c44:	69bb      	ldr	r3, [r7, #24]
+ 8010c46:	68ba      	ldr	r2, [r7, #8]
+ 8010c48:	641a      	str	r2, [r3, #64]	; 0x40
+	( void ) xQueueGenericReset( pxNewQueue, pdTRUE );
+ 8010c4a:	2101      	movs	r1, #1
+ 8010c4c:	69b8      	ldr	r0, [r7, #24]
+ 8010c4e:	f7ff fecb 	bl	80109e8 <xQueueGenericReset>
+		pxNewQueue->pxQueueSetContainer = NULL;
+	}
+	#endif /* configUSE_QUEUE_SETS */
+
+	traceQUEUE_CREATE( pxNewQueue );
+}
+ 8010c52:	bf00      	nop
+ 8010c54:	3710      	adds	r7, #16
+ 8010c56:	46bd      	mov	sp, r7
+ 8010c58:	bd80      	pop	{r7, pc}
+
+08010c5a <prvInitialiseMutex>:
+/*-----------------------------------------------------------*/
+
+#if( configUSE_MUTEXES == 1 )
+
+	static void prvInitialiseMutex( Queue_t *pxNewQueue )
+	{
+ 8010c5a:	b580      	push	{r7, lr}
+ 8010c5c:	b082      	sub	sp, #8
+ 8010c5e:	af00      	add	r7, sp, #0
+ 8010c60:	6078      	str	r0, [r7, #4]
+		if( pxNewQueue != NULL )
+ 8010c62:	687b      	ldr	r3, [r7, #4]
+ 8010c64:	2b00      	cmp	r3, #0
+ 8010c66:	d00e      	beq.n	8010c86 <prvInitialiseMutex+0x2c>
+		{
+			/* The queue create function will set all the queue structure members
+			correctly for a generic queue, but this function is creating a
+			mutex.  Overwrite those members that need to be set differently -
+			in particular the information required for priority inheritance. */
+			pxNewQueue->u.xSemaphore.xMutexHolder = NULL;
+ 8010c68:	687b      	ldr	r3, [r7, #4]
+ 8010c6a:	2200      	movs	r2, #0
+ 8010c6c:	609a      	str	r2, [r3, #8]
+			pxNewQueue->uxQueueType = queueQUEUE_IS_MUTEX;
+ 8010c6e:	687b      	ldr	r3, [r7, #4]
+ 8010c70:	2200      	movs	r2, #0
+ 8010c72:	601a      	str	r2, [r3, #0]
+
+			/* In case this is a recursive mutex. */
+			pxNewQueue->u.xSemaphore.uxRecursiveCallCount = 0;
+ 8010c74:	687b      	ldr	r3, [r7, #4]
+ 8010c76:	2200      	movs	r2, #0
+ 8010c78:	60da      	str	r2, [r3, #12]
+
+			traceCREATE_MUTEX( pxNewQueue );
+
+			/* Start with the semaphore in the expected state. */
+			( void ) xQueueGenericSend( pxNewQueue, NULL, ( TickType_t ) 0U, queueSEND_TO_BACK );
+ 8010c7a:	2300      	movs	r3, #0
+ 8010c7c:	2200      	movs	r2, #0
+ 8010c7e:	2100      	movs	r1, #0
+ 8010c80:	6878      	ldr	r0, [r7, #4]
+ 8010c82:	f000 f837 	bl	8010cf4 <xQueueGenericSend>
+		}
+		else
+		{
+			traceCREATE_MUTEX_FAILED();
+		}
+	}
+ 8010c86:	bf00      	nop
+ 8010c88:	3708      	adds	r7, #8
+ 8010c8a:	46bd      	mov	sp, r7
+ 8010c8c:	bd80      	pop	{r7, pc}
+
+08010c8e <xQueueCreateMutex>:
+/*-----------------------------------------------------------*/
+
+#if( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+
+	QueueHandle_t xQueueCreateMutex( const uint8_t ucQueueType )
+	{
+ 8010c8e:	b580      	push	{r7, lr}
+ 8010c90:	b086      	sub	sp, #24
+ 8010c92:	af00      	add	r7, sp, #0
+ 8010c94:	4603      	mov	r3, r0
+ 8010c96:	71fb      	strb	r3, [r7, #7]
+	QueueHandle_t xNewQueue;
+	const UBaseType_t uxMutexLength = ( UBaseType_t ) 1, uxMutexSize = ( UBaseType_t ) 0;
+ 8010c98:	2301      	movs	r3, #1
+ 8010c9a:	617b      	str	r3, [r7, #20]
+ 8010c9c:	2300      	movs	r3, #0
+ 8010c9e:	613b      	str	r3, [r7, #16]
+
+		xNewQueue = xQueueGenericCreate( uxMutexLength, uxMutexSize, ucQueueType );
+ 8010ca0:	79fb      	ldrb	r3, [r7, #7]
+ 8010ca2:	461a      	mov	r2, r3
+ 8010ca4:	6939      	ldr	r1, [r7, #16]
+ 8010ca6:	6978      	ldr	r0, [r7, #20]
+ 8010ca8:	f7ff ff7e 	bl	8010ba8 <xQueueGenericCreate>
+ 8010cac:	60f8      	str	r0, [r7, #12]
+		prvInitialiseMutex( ( Queue_t * ) xNewQueue );
+ 8010cae:	68f8      	ldr	r0, [r7, #12]
+ 8010cb0:	f7ff ffd3 	bl	8010c5a <prvInitialiseMutex>
+
+		return xNewQueue;
+ 8010cb4:	68fb      	ldr	r3, [r7, #12]
+	}
+ 8010cb6:	4618      	mov	r0, r3
+ 8010cb8:	3718      	adds	r7, #24
+ 8010cba:	46bd      	mov	sp, r7
+ 8010cbc:	bd80      	pop	{r7, pc}
+
+08010cbe <xQueueCreateMutexStatic>:
+/*-----------------------------------------------------------*/
+
+#if( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
+
+	QueueHandle_t xQueueCreateMutexStatic( const uint8_t ucQueueType, StaticQueue_t *pxStaticQueue )
+	{
+ 8010cbe:	b580      	push	{r7, lr}
+ 8010cc0:	b088      	sub	sp, #32
+ 8010cc2:	af02      	add	r7, sp, #8
+ 8010cc4:	4603      	mov	r3, r0
+ 8010cc6:	6039      	str	r1, [r7, #0]
+ 8010cc8:	71fb      	strb	r3, [r7, #7]
+	QueueHandle_t xNewQueue;
+	const UBaseType_t uxMutexLength = ( UBaseType_t ) 1, uxMutexSize = ( UBaseType_t ) 0;
+ 8010cca:	2301      	movs	r3, #1
+ 8010ccc:	617b      	str	r3, [r7, #20]
+ 8010cce:	2300      	movs	r3, #0
+ 8010cd0:	613b      	str	r3, [r7, #16]
+
+		/* Prevent compiler warnings about unused parameters if
+		configUSE_TRACE_FACILITY does not equal 1. */
+		( void ) ucQueueType;
+
+		xNewQueue = xQueueGenericCreateStatic( uxMutexLength, uxMutexSize, NULL, pxStaticQueue, ucQueueType );
+ 8010cd2:	79fb      	ldrb	r3, [r7, #7]
+ 8010cd4:	9300      	str	r3, [sp, #0]
+ 8010cd6:	683b      	ldr	r3, [r7, #0]
+ 8010cd8:	2200      	movs	r2, #0
+ 8010cda:	6939      	ldr	r1, [r7, #16]
+ 8010cdc:	6978      	ldr	r0, [r7, #20]
+ 8010cde:	f7ff feeb 	bl	8010ab8 <xQueueGenericCreateStatic>
+ 8010ce2:	60f8      	str	r0, [r7, #12]
+		prvInitialiseMutex( ( Queue_t * ) xNewQueue );
+ 8010ce4:	68f8      	ldr	r0, [r7, #12]
+ 8010ce6:	f7ff ffb8 	bl	8010c5a <prvInitialiseMutex>
+
+		return xNewQueue;
+ 8010cea:	68fb      	ldr	r3, [r7, #12]
+	}
+ 8010cec:	4618      	mov	r0, r3
+ 8010cee:	3718      	adds	r7, #24
+ 8010cf0:	46bd      	mov	sp, r7
+ 8010cf2:	bd80      	pop	{r7, pc}
+
+08010cf4 <xQueueGenericSend>:
+
+#endif /* ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, const BaseType_t xCopyPosition )
+{
+ 8010cf4:	b580      	push	{r7, lr}
+ 8010cf6:	b08e      	sub	sp, #56	; 0x38
+ 8010cf8:	af00      	add	r7, sp, #0
+ 8010cfa:	60f8      	str	r0, [r7, #12]
+ 8010cfc:	60b9      	str	r1, [r7, #8]
+ 8010cfe:	607a      	str	r2, [r7, #4]
+ 8010d00:	603b      	str	r3, [r7, #0]
+BaseType_t xEntryTimeSet = pdFALSE, xYieldRequired;
+ 8010d02:	2300      	movs	r3, #0
+ 8010d04:	637b      	str	r3, [r7, #52]	; 0x34
+TimeOut_t xTimeOut;
+Queue_t * const pxQueue = xQueue;
+ 8010d06:	68fb      	ldr	r3, [r7, #12]
+ 8010d08:	633b      	str	r3, [r7, #48]	; 0x30
+
+	configASSERT( pxQueue );
+ 8010d0a:	6b3b      	ldr	r3, [r7, #48]	; 0x30
+ 8010d0c:	2b00      	cmp	r3, #0
+ 8010d0e:	d10a      	bne.n	8010d26 <xQueueGenericSend+0x32>
+	__asm volatile
+ 8010d10:	f04f 0350 	mov.w	r3, #80	; 0x50
+ 8010d14:	f383 8811 	msr	BASEPRI, r3
+ 8010d18:	f3bf 8f6f 	isb	sy
+ 8010d1c:	f3bf 8f4f 	dsb	sy
+ 8010d20:	62bb      	str	r3, [r7, #40]	; 0x28
+}
+ 8010d22:	bf00      	nop
+ 8010d24:	e7fe      	b.n	8010d24 <xQueueGenericSend+0x30>
+	configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
+ 8010d26:	68bb      	ldr	r3, [r7, #8]
+ 8010d28:	2b00      	cmp	r3, #0
+ 8010d2a:	d103      	bne.n	8010d34 <xQueueGenericSend+0x40>
+ 8010d2c:	6b3b      	ldr	r3, [r7, #48]	; 0x30
+ 8010d2e:	6c1b      	ldr	r3, [r3, #64]	; 0x40
+ 8010d30:	2b00      	cmp	r3, #0
+ 8010d32:	d101      	bne.n	8010d38 <xQueueGenericSend+0x44>
+ 8010d34:	2301      	movs	r3, #1
+ 8010d36:	e000      	b.n	8010d3a <xQueueGenericSend+0x46>
+ 8010d38:	2300      	movs	r3, #0
+ 8010d3a:	2b00      	cmp	r3, #0
+ 8010d3c:	d10a      	bne.n	8010d54 <xQueueGenericSend+0x60>
+	__asm volatile
+ 8010d3e:	f04f 0350 	mov.w	r3, #80	; 0x50
+ 8010d42:	f383 8811 	msr	BASEPRI, r3
+ 8010d46:	f3bf 8f6f 	isb	sy
+ 8010d4a:	f3bf 8f4f 	dsb	sy
+ 8010d4e:	627b      	str	r3, [r7, #36]	; 0x24
+}
+ 8010d50:	bf00      	nop
+ 8010d52:	e7fe      	b.n	8010d52 <xQueueGenericSend+0x5e>
+	configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) );
+ 8010d54:	683b      	ldr	r3, [r7, #0]
+ 8010d56:	2b02      	cmp	r3, #2
+ 8010d58:	d103      	bne.n	8010d62 <xQueueGenericSend+0x6e>
+ 8010d5a:	6b3b      	ldr	r3, [r7, #48]	; 0x30
+ 8010d5c:	6bdb      	ldr	r3, [r3, #60]	; 0x3c
+ 8010d5e:	2b01      	cmp	r3, #1
+ 8010d60:	d101      	bne.n	8010d66 <xQueueGenericSend+0x72>
+ 8010d62:	2301      	movs	r3, #1
+ 8010d64:	e000      	b.n	8010d68 <xQueueGenericSend+0x74>
+ 8010d66:	2300      	movs	r3, #0
+ 8010d68:	2b00      	cmp	r3, #0
+ 8010d6a:	d10a      	bne.n	8010d82 <xQueueGenericSend+0x8e>
+	__asm volatile
+ 8010d6c:	f04f 0350 	mov.w	r3, #80	; 0x50
+ 8010d70:	f383 8811 	msr	BASEPRI, r3
+ 8010d74:	f3bf 8f6f 	isb	sy
+ 8010d78:	f3bf 8f4f 	dsb	sy
+ 8010d7c:	623b      	str	r3, [r7, #32]
+}
+ 8010d7e:	bf00      	nop
+ 8010d80:	e7fe      	b.n	8010d80 <xQueueGenericSend+0x8c>
+	#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
+	{
+		configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
+ 8010d82:	f001 fcc1 	bl	8012708 <xTaskGetSchedulerState>
+ 8010d86:	4603      	mov	r3, r0
+ 8010d88:	2b00      	cmp	r3, #0
+ 8010d8a:	d102      	bne.n	8010d92 <xQueueGenericSend+0x9e>
+ 8010d8c:	687b      	ldr	r3, [r7, #4]
+ 8010d8e:	2b00      	cmp	r3, #0
+ 8010d90:	d101      	bne.n	8010d96 <xQueueGenericSend+0xa2>
+ 8010d92:	2301      	movs	r3, #1
+ 8010d94:	e000      	b.n	8010d98 <xQueueGenericSend+0xa4>
+ 8010d96:	2300      	movs	r3, #0
+ 8010d98:	2b00      	cmp	r3, #0
+ 8010d9a:	d10a      	bne.n	8010db2 <xQueueGenericSend+0xbe>
+	__asm volatile
+ 8010d9c:	f04f 0350 	mov.w	r3, #80	; 0x50
+ 8010da0:	f383 8811 	msr	BASEPRI, r3
+ 8010da4:	f3bf 8f6f 	isb	sy
+ 8010da8:	f3bf 8f4f 	dsb	sy
+ 8010dac:	61fb      	str	r3, [r7, #28]
+}
+ 8010dae:	bf00      	nop
+ 8010db0:	e7fe      	b.n	8010db0 <xQueueGenericSend+0xbc>
+	/*lint -save -e904 This function relaxes the coding standard somewhat to
+	allow return statements within the function itself.  This is done in the
+	interest of execution time efficiency. */
+	for( ;; )
+	{
+		taskENTER_CRITICAL();
+ 8010db2:	f002 fb27 	bl	8013404 <vPortEnterCritical>
+		{
+			/* Is there room on the queue now?  The running task must be the
+			highest priority task wanting to access the queue.  If the head item
+			in the queue is to be overwritten then it does not matter if the
+			queue is full. */
+			if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) )
+ 8010db6:	6b3b      	ldr	r3, [r7, #48]	; 0x30
+ 8010db8:	6b9a      	ldr	r2, [r3, #56]	; 0x38
+ 8010dba:	6b3b      	ldr	r3, [r7, #48]	; 0x30
+ 8010dbc:	6bdb      	ldr	r3, [r3, #60]	; 0x3c
+ 8010dbe:	429a      	cmp	r2, r3
+ 8010dc0:	d302      	bcc.n	8010dc8 <xQueueGenericSend+0xd4>
+ 8010dc2:	683b      	ldr	r3, [r7, #0]
+ 8010dc4:	2b02      	cmp	r3, #2
+ 8010dc6:	d129      	bne.n	8010e1c <xQueueGenericSend+0x128>
+						}
+					}
+				}
+				#else /* configUSE_QUEUE_SETS */
+				{
+					xYieldRequired = prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );
+ 8010dc8:	683a      	ldr	r2, [r7, #0]
+ 8010dca:	68b9      	ldr	r1, [r7, #8]
+ 8010dcc:	6b38      	ldr	r0, [r7, #48]	; 0x30
+ 8010dce:	f000 fc9a 	bl	8011706 <prvCopyDataToQueue>
+ 8010dd2:	62f8      	str	r0, [r7, #44]	; 0x2c
+
+					/* If there was a task waiting for data to arrive on the
+					queue then unblock it now. */
+					if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+ 8010dd4:	6b3b      	ldr	r3, [r7, #48]	; 0x30
+ 8010dd6:	6a5b      	ldr	r3, [r3, #36]	; 0x24
+ 8010dd8:	2b00      	cmp	r3, #0
+ 8010dda:	d010      	beq.n	8010dfe <xQueueGenericSend+0x10a>
+					{
+						if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+ 8010ddc:	6b3b      	ldr	r3, [r7, #48]	; 0x30
+ 8010dde:	3324      	adds	r3, #36	; 0x24
+ 8010de0:	4618      	mov	r0, r3
+ 8010de2:	f001 fa9d 	bl	8012320 <xTaskRemoveFromEventList>
+ 8010de6:	4603      	mov	r3, r0
+ 8010de8:	2b00      	cmp	r3, #0
+ 8010dea:	d013      	beq.n	8010e14 <xQueueGenericSend+0x120>
+						{
+							/* The unblocked task has a priority higher than
+							our own so yield immediately.  Yes it is ok to do
+							this from within the critical section - the kernel
+							takes care of that. */
+							queueYIELD_IF_USING_PREEMPTION();
+ 8010dec:	4b3f      	ldr	r3, [pc, #252]	; (8010eec <xQueueGenericSend+0x1f8>)
+ 8010dee:	f04f 5280 	mov.w	r2, #268435456	; 0x10000000
+ 8010df2:	601a      	str	r2, [r3, #0]
+ 8010df4:	f3bf 8f4f 	dsb	sy
+ 8010df8:	f3bf 8f6f 	isb	sy
+ 8010dfc:	e00a      	b.n	8010e14 <xQueueGenericSend+0x120>
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+					else if( xYieldRequired != pdFALSE )
+ 8010dfe:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 8010e00:	2b00      	cmp	r3, #0
+ 8010e02:	d007      	beq.n	8010e14 <xQueueGenericSend+0x120>
+					{
+						/* This path is a special case that will only get
+						executed if the task was holding multiple mutexes and
+						the mutexes were given back in an order that is
+						different to that in which they were taken. */
+						queueYIELD_IF_USING_PREEMPTION();
+ 8010e04:	4b39      	ldr	r3, [pc, #228]	; (8010eec <xQueueGenericSend+0x1f8>)
+ 8010e06:	f04f 5280 	mov.w	r2, #268435456	; 0x10000000
+ 8010e0a:	601a      	str	r2, [r3, #0]
+ 8010e0c:	f3bf 8f4f 	dsb	sy
+ 8010e10:	f3bf 8f6f 	isb	sy
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				#endif /* configUSE_QUEUE_SETS */
+
+				taskEXIT_CRITICAL();
+ 8010e14:	f002 fb26 	bl	8013464 <vPortExitCritical>
+				return pdPASS;
+ 8010e18:	2301      	movs	r3, #1
+ 8010e1a:	e063      	b.n	8010ee4 <xQueueGenericSend+0x1f0>
+			}
+			else
+			{
+				if( xTicksToWait == ( TickType_t ) 0 )
+ 8010e1c:	687b      	ldr	r3, [r7, #4]
+ 8010e1e:	2b00      	cmp	r3, #0
+ 8010e20:	d103      	bne.n	8010e2a <xQueueGenericSend+0x136>
+				{
+					/* The queue was full and no block time is specified (or
+					the block time has expired) so leave now. */
+					taskEXIT_CRITICAL();
+ 8010e22:	f002 fb1f 	bl	8013464 <vPortExitCritical>
+
+					/* Return to the original privilege level before exiting
+					the function. */
+					traceQUEUE_SEND_FAILED( pxQueue );
+					return errQUEUE_FULL;
+ 8010e26:	2300      	movs	r3, #0
+ 8010e28:	e05c      	b.n	8010ee4 <xQueueGenericSend+0x1f0>
+				}
+				else if( xEntryTimeSet == pdFALSE )
+ 8010e2a:	6b7b      	ldr	r3, [r7, #52]	; 0x34
+ 8010e2c:	2b00      	cmp	r3, #0
+ 8010e2e:	d106      	bne.n	8010e3e <xQueueGenericSend+0x14a>
+				{
+					/* The queue was full and a block time was specified so
+					configure the timeout structure. */
+					vTaskInternalSetTimeOutState( &xTimeOut );
+ 8010e30:	f107 0314 	add.w	r3, r7, #20
+ 8010e34:	4618      	mov	r0, r3
+ 8010e36:	f001 fad5 	bl	80123e4 <vTaskInternalSetTimeOutState>
+					xEntryTimeSet = pdTRUE;
+ 8010e3a:	2301      	movs	r3, #1
+ 8010e3c:	637b      	str	r3, [r7, #52]	; 0x34
+					/* Entry time was already set. */
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+		}
+		taskEXIT_CRITICAL();
+ 8010e3e:	f002 fb11 	bl	8013464 <vPortExitCritical>
+
+		/* Interrupts and other tasks can send to and receive from the queue
+		now the critical section has been exited. */
+
+		vTaskSuspendAll();
+ 8010e42:	f001 f82f 	bl	8011ea4 <vTaskSuspendAll>
+		prvLockQueue( pxQueue );
+ 8010e46:	f002 fadd 	bl	8013404 <vPortEnterCritical>
+ 8010e4a:	6b3b      	ldr	r3, [r7, #48]	; 0x30
+ 8010e4c:	f893 3044 	ldrb.w	r3, [r3, #68]	; 0x44
+ 8010e50:	b25b      	sxtb	r3, r3
+ 8010e52:	f1b3 3fff 	cmp.w	r3, #4294967295
+ 8010e56:	d103      	bne.n	8010e60 <xQueueGenericSend+0x16c>
+ 8010e58:	6b3b      	ldr	r3, [r7, #48]	; 0x30
+ 8010e5a:	2200      	movs	r2, #0
+ 8010e5c:	f883 2044 	strb.w	r2, [r3, #68]	; 0x44
+ 8010e60:	6b3b      	ldr	r3, [r7, #48]	; 0x30
+ 8010e62:	f893 3045 	ldrb.w	r3, [r3, #69]	; 0x45
+ 8010e66:	b25b      	sxtb	r3, r3
+ 8010e68:	f1b3 3fff 	cmp.w	r3, #4294967295
+ 8010e6c:	d103      	bne.n	8010e76 <xQueueGenericSend+0x182>
+ 8010e6e:	6b3b      	ldr	r3, [r7, #48]	; 0x30
+ 8010e70:	2200      	movs	r2, #0
+ 8010e72:	f883 2045 	strb.w	r2, [r3, #69]	; 0x45
+ 8010e76:	f002 faf5 	bl	8013464 <vPortExitCritical>
+
+		/* Update the timeout state to see if it has expired yet. */
+		if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
+ 8010e7a:	1d3a      	adds	r2, r7, #4
+ 8010e7c:	f107 0314 	add.w	r3, r7, #20
+ 8010e80:	4611      	mov	r1, r2
+ 8010e82:	4618      	mov	r0, r3
+ 8010e84:	f001 fac4 	bl	8012410 <xTaskCheckForTimeOut>
+ 8010e88:	4603      	mov	r3, r0
+ 8010e8a:	2b00      	cmp	r3, #0
+ 8010e8c:	d124      	bne.n	8010ed8 <xQueueGenericSend+0x1e4>
+		{
+			if( prvIsQueueFull( pxQueue ) != pdFALSE )
+ 8010e8e:	6b38      	ldr	r0, [r7, #48]	; 0x30
+ 8010e90:	f000 fd31 	bl	80118f6 <prvIsQueueFull>
+ 8010e94:	4603      	mov	r3, r0
+ 8010e96:	2b00      	cmp	r3, #0
+ 8010e98:	d018      	beq.n	8010ecc <xQueueGenericSend+0x1d8>
+			{
+				traceBLOCKING_ON_QUEUE_SEND( pxQueue );
+				vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToSend ), xTicksToWait );
+ 8010e9a:	6b3b      	ldr	r3, [r7, #48]	; 0x30
+ 8010e9c:	3310      	adds	r3, #16
+ 8010e9e:	687a      	ldr	r2, [r7, #4]
+ 8010ea0:	4611      	mov	r1, r2
+ 8010ea2:	4618      	mov	r0, r3
+ 8010ea4:	f001 f9ec 	bl	8012280 <vTaskPlaceOnEventList>
+				/* Unlocking the queue means queue events can effect the
+				event list.  It is possible that interrupts occurring now
+				remove this task from the event list again - but as the
+				scheduler is suspended the task will go onto the pending
+				ready last instead of the actual ready list. */
+				prvUnlockQueue( pxQueue );
+ 8010ea8:	6b38      	ldr	r0, [r7, #48]	; 0x30
+ 8010eaa:	f000 fcbc 	bl	8011826 <prvUnlockQueue>
+				/* Resuming the scheduler will move tasks from the pending
+				ready list into the ready list - so it is feasible that this
+				task is already in a ready list before it yields - in which
+				case the yield will not cause a context switch unless there
+				is also a higher priority task in the pending ready list. */
+				if( xTaskResumeAll() == pdFALSE )
+ 8010eae:	f001 f807 	bl	8011ec0 <xTaskResumeAll>
+ 8010eb2:	4603      	mov	r3, r0
+ 8010eb4:	2b00      	cmp	r3, #0
+ 8010eb6:	f47f af7c 	bne.w	8010db2 <xQueueGenericSend+0xbe>
+				{
+					portYIELD_WITHIN_API();
+ 8010eba:	4b0c      	ldr	r3, [pc, #48]	; (8010eec <xQueueGenericSend+0x1f8>)
+ 8010ebc:	f04f 5280 	mov.w	r2, #268435456	; 0x10000000
+ 8010ec0:	601a      	str	r2, [r3, #0]
+ 8010ec2:	f3bf 8f4f 	dsb	sy
+ 8010ec6:	f3bf 8f6f 	isb	sy
+ 8010eca:	e772      	b.n	8010db2 <xQueueGenericSend+0xbe>
+				}
+			}
+			else
+			{
+				/* Try again. */
+				prvUnlockQueue( pxQueue );
+ 8010ecc:	6b38      	ldr	r0, [r7, #48]	; 0x30
+ 8010ece:	f000 fcaa 	bl	8011826 <prvUnlockQueue>
+				( void ) xTaskResumeAll();
+ 8010ed2:	f000 fff5 	bl	8011ec0 <xTaskResumeAll>
+ 8010ed6:	e76c      	b.n	8010db2 <xQueueGenericSend+0xbe>
+			}
+		}
+		else
+		{
+			/* The timeout has expired. */
+			prvUnlockQueue( pxQueue );
+ 8010ed8:	6b38      	ldr	r0, [r7, #48]	; 0x30
+ 8010eda:	f000 fca4 	bl	8011826 <prvUnlockQueue>
+			( void ) xTaskResumeAll();
+ 8010ede:	f000 ffef 	bl	8011ec0 <xTaskResumeAll>
+
+			traceQUEUE_SEND_FAILED( pxQueue );
+			return errQUEUE_FULL;
+ 8010ee2:	2300      	movs	r3, #0
+		}
+	} /*lint -restore */
+}
+ 8010ee4:	4618      	mov	r0, r3
+ 8010ee6:	3738      	adds	r7, #56	; 0x38
+ 8010ee8:	46bd      	mov	sp, r7
+ 8010eea:	bd80      	pop	{r7, pc}
+ 8010eec:	e000ed04 	.word	0xe000ed04
+
+08010ef0 <xQueueGenericSendFromISR>:
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueGenericSendFromISR( QueueHandle_t xQueue, const void * const pvItemToQueue, BaseType_t * const pxHigherPriorityTaskWoken, const BaseType_t xCopyPosition )
+{
+ 8010ef0:	b580      	push	{r7, lr}
+ 8010ef2:	b090      	sub	sp, #64	; 0x40
+ 8010ef4:	af00      	add	r7, sp, #0
+ 8010ef6:	60f8      	str	r0, [r7, #12]
+ 8010ef8:	60b9      	str	r1, [r7, #8]
+ 8010efa:	607a      	str	r2, [r7, #4]
+ 8010efc:	603b      	str	r3, [r7, #0]
+BaseType_t xReturn;
+UBaseType_t uxSavedInterruptStatus;
+Queue_t * const pxQueue = xQueue;
+ 8010efe:	68fb      	ldr	r3, [r7, #12]
+ 8010f00:	63bb      	str	r3, [r7, #56]	; 0x38
+
+	configASSERT( pxQueue );
+ 8010f02:	6bbb      	ldr	r3, [r7, #56]	; 0x38
+ 8010f04:	2b00      	cmp	r3, #0
+ 8010f06:	d10a      	bne.n	8010f1e <xQueueGenericSendFromISR+0x2e>
+	__asm volatile
+ 8010f08:	f04f 0350 	mov.w	r3, #80	; 0x50
+ 8010f0c:	f383 8811 	msr	BASEPRI, r3
+ 8010f10:	f3bf 8f6f 	isb	sy
+ 8010f14:	f3bf 8f4f 	dsb	sy
+ 8010f18:	62bb      	str	r3, [r7, #40]	; 0x28
+}
+ 8010f1a:	bf00      	nop
+ 8010f1c:	e7fe      	b.n	8010f1c <xQueueGenericSendFromISR+0x2c>
+	configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
+ 8010f1e:	68bb      	ldr	r3, [r7, #8]
+ 8010f20:	2b00      	cmp	r3, #0
+ 8010f22:	d103      	bne.n	8010f2c <xQueueGenericSendFromISR+0x3c>
+ 8010f24:	6bbb      	ldr	r3, [r7, #56]	; 0x38
+ 8010f26:	6c1b      	ldr	r3, [r3, #64]	; 0x40
+ 8010f28:	2b00      	cmp	r3, #0
+ 8010f2a:	d101      	bne.n	8010f30 <xQueueGenericSendFromISR+0x40>
+ 8010f2c:	2301      	movs	r3, #1
+ 8010f2e:	e000      	b.n	8010f32 <xQueueGenericSendFromISR+0x42>
+ 8010f30:	2300      	movs	r3, #0
+ 8010f32:	2b00      	cmp	r3, #0
+ 8010f34:	d10a      	bne.n	8010f4c <xQueueGenericSendFromISR+0x5c>
+	__asm volatile
+ 8010f36:	f04f 0350 	mov.w	r3, #80	; 0x50
+ 8010f3a:	f383 8811 	msr	BASEPRI, r3
+ 8010f3e:	f3bf 8f6f 	isb	sy
+ 8010f42:	f3bf 8f4f 	dsb	sy
+ 8010f46:	627b      	str	r3, [r7, #36]	; 0x24
+}
+ 8010f48:	bf00      	nop
+ 8010f4a:	e7fe      	b.n	8010f4a <xQueueGenericSendFromISR+0x5a>
+	configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) );
+ 8010f4c:	683b      	ldr	r3, [r7, #0]
+ 8010f4e:	2b02      	cmp	r3, #2
+ 8010f50:	d103      	bne.n	8010f5a <xQueueGenericSendFromISR+0x6a>
+ 8010f52:	6bbb      	ldr	r3, [r7, #56]	; 0x38
+ 8010f54:	6bdb      	ldr	r3, [r3, #60]	; 0x3c
+ 8010f56:	2b01      	cmp	r3, #1
+ 8010f58:	d101      	bne.n	8010f5e <xQueueGenericSendFromISR+0x6e>
+ 8010f5a:	2301      	movs	r3, #1
+ 8010f5c:	e000      	b.n	8010f60 <xQueueGenericSendFromISR+0x70>
+ 8010f5e:	2300      	movs	r3, #0
+ 8010f60:	2b00      	cmp	r3, #0
+ 8010f62:	d10a      	bne.n	8010f7a <xQueueGenericSendFromISR+0x8a>
+	__asm volatile
+ 8010f64:	f04f 0350 	mov.w	r3, #80	; 0x50
+ 8010f68:	f383 8811 	msr	BASEPRI, r3
+ 8010f6c:	f3bf 8f6f 	isb	sy
+ 8010f70:	f3bf 8f4f 	dsb	sy
+ 8010f74:	623b      	str	r3, [r7, #32]
+}
+ 8010f76:	bf00      	nop
+ 8010f78:	e7fe      	b.n	8010f78 <xQueueGenericSendFromISR+0x88>
+	that have been assigned a priority at or (logically) below the maximum
+	system call	interrupt priority.  FreeRTOS maintains a separate interrupt
+	safe API to ensure interrupt entry is as fast and as simple as possible.
+	More information (albeit Cortex-M specific) is provided on the following
+	link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */
+	portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+ 8010f7a:	f002 fb25 	bl	80135c8 <vPortValidateInterruptPriority>
+
+portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void )
+{
+uint32_t ulOriginalBASEPRI, ulNewBASEPRI;
+
+	__asm volatile
+ 8010f7e:	f3ef 8211 	mrs	r2, BASEPRI
+ 8010f82:	f04f 0350 	mov.w	r3, #80	; 0x50
+ 8010f86:	f383 8811 	msr	BASEPRI, r3
+ 8010f8a:	f3bf 8f6f 	isb	sy
+ 8010f8e:	f3bf 8f4f 	dsb	sy
+ 8010f92:	61fa      	str	r2, [r7, #28]
+ 8010f94:	61bb      	str	r3, [r7, #24]
+		:"=r" (ulOriginalBASEPRI), "=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
+	);
+
+	/* This return will not be reached but is necessary to prevent compiler
+	warnings. */
+	return ulOriginalBASEPRI;
+ 8010f96:	69fb      	ldr	r3, [r7, #28]
+	/* Similar to xQueueGenericSend, except without blocking if there is no room
+	in the queue.  Also don't directly wake a task that was blocked on a queue
+	read, instead return a flag to say whether a context switch is required or
+	not (i.e. has a task with a higher priority than us been woken by this
+	post). */
+	uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+ 8010f98:	637b      	str	r3, [r7, #52]	; 0x34
+	{
+		if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) )
+ 8010f9a:	6bbb      	ldr	r3, [r7, #56]	; 0x38
+ 8010f9c:	6b9a      	ldr	r2, [r3, #56]	; 0x38
+ 8010f9e:	6bbb      	ldr	r3, [r7, #56]	; 0x38
+ 8010fa0:	6bdb      	ldr	r3, [r3, #60]	; 0x3c
+ 8010fa2:	429a      	cmp	r2, r3
+ 8010fa4:	d302      	bcc.n	8010fac <xQueueGenericSendFromISR+0xbc>
+ 8010fa6:	683b      	ldr	r3, [r7, #0]
+ 8010fa8:	2b02      	cmp	r3, #2
+ 8010faa:	d12f      	bne.n	801100c <xQueueGenericSendFromISR+0x11c>
+		{
+			const int8_t cTxLock = pxQueue->cTxLock;
+ 8010fac:	6bbb      	ldr	r3, [r7, #56]	; 0x38
+ 8010fae:	f893 3045 	ldrb.w	r3, [r3, #69]	; 0x45
+ 8010fb2:	f887 3033 	strb.w	r3, [r7, #51]	; 0x33
+			const UBaseType_t uxPreviousMessagesWaiting = pxQueue->uxMessagesWaiting;
+ 8010fb6:	6bbb      	ldr	r3, [r7, #56]	; 0x38
+ 8010fb8:	6b9b      	ldr	r3, [r3, #56]	; 0x38
+ 8010fba:	62fb      	str	r3, [r7, #44]	; 0x2c
+			/* Semaphores use xQueueGiveFromISR(), so pxQueue will not be a
+			semaphore or mutex.  That means prvCopyDataToQueue() cannot result
+			in a task disinheriting a priority and prvCopyDataToQueue() can be
+			called here even though the disinherit function does not check if
+			the scheduler is suspended before accessing the ready lists. */
+			( void ) prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );
+ 8010fbc:	683a      	ldr	r2, [r7, #0]
+ 8010fbe:	68b9      	ldr	r1, [r7, #8]
+ 8010fc0:	6bb8      	ldr	r0, [r7, #56]	; 0x38
+ 8010fc2:	f000 fba0 	bl	8011706 <prvCopyDataToQueue>
+
+			/* The event list is not altered if the queue is locked.  This will
+			be done when the queue is unlocked later. */
+			if( cTxLock == queueUNLOCKED )
+ 8010fc6:	f997 3033 	ldrsb.w	r3, [r7, #51]	; 0x33
+ 8010fca:	f1b3 3fff 	cmp.w	r3, #4294967295
+ 8010fce:	d112      	bne.n	8010ff6 <xQueueGenericSendFromISR+0x106>
+						}
+					}
+				}
+				#else /* configUSE_QUEUE_SETS */
+				{
+					if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+ 8010fd0:	6bbb      	ldr	r3, [r7, #56]	; 0x38
+ 8010fd2:	6a5b      	ldr	r3, [r3, #36]	; 0x24
+ 8010fd4:	2b00      	cmp	r3, #0
+ 8010fd6:	d016      	beq.n	8011006 <xQueueGenericSendFromISR+0x116>
+					{
+						if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+ 8010fd8:	6bbb      	ldr	r3, [r7, #56]	; 0x38
+ 8010fda:	3324      	adds	r3, #36	; 0x24
+ 8010fdc:	4618      	mov	r0, r3
+ 8010fde:	f001 f99f 	bl	8012320 <xTaskRemoveFromEventList>
+ 8010fe2:	4603      	mov	r3, r0
+ 8010fe4:	2b00      	cmp	r3, #0
+ 8010fe6:	d00e      	beq.n	8011006 <xQueueGenericSendFromISR+0x116>
+						{
+							/* The task waiting has a higher priority so record that a
+							context	switch is required. */
+							if( pxHigherPriorityTaskWoken != NULL )
+ 8010fe8:	687b      	ldr	r3, [r7, #4]
+ 8010fea:	2b00      	cmp	r3, #0
+ 8010fec:	d00b      	beq.n	8011006 <xQueueGenericSendFromISR+0x116>
+							{
+								*pxHigherPriorityTaskWoken = pdTRUE;
+ 8010fee:	687b      	ldr	r3, [r7, #4]
+ 8010ff0:	2201      	movs	r2, #1
+ 8010ff2:	601a      	str	r2, [r3, #0]
+ 8010ff4:	e007      	b.n	8011006 <xQueueGenericSendFromISR+0x116>
+			}
+			else
+			{
+				/* Increment the lock count so the task that unlocks the queue
+				knows that data was posted while it was locked. */
+				pxQueue->cTxLock = ( int8_t ) ( cTxLock + 1 );
+ 8010ff6:	f897 3033 	ldrb.w	r3, [r7, #51]	; 0x33
+ 8010ffa:	3301      	adds	r3, #1
+ 8010ffc:	b2db      	uxtb	r3, r3
+ 8010ffe:	b25a      	sxtb	r2, r3
+ 8011000:	6bbb      	ldr	r3, [r7, #56]	; 0x38
+ 8011002:	f883 2045 	strb.w	r2, [r3, #69]	; 0x45
+			}
+
+			xReturn = pdPASS;
+ 8011006:	2301      	movs	r3, #1
+ 8011008:	63fb      	str	r3, [r7, #60]	; 0x3c
+		{
+ 801100a:	e001      	b.n	8011010 <xQueueGenericSendFromISR+0x120>
+		}
+		else
+		{
+			traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue );
+			xReturn = errQUEUE_FULL;
+ 801100c:	2300      	movs	r3, #0
+ 801100e:	63fb      	str	r3, [r7, #60]	; 0x3c
+ 8011010:	6b7b      	ldr	r3, [r7, #52]	; 0x34
+ 8011012:	617b      	str	r3, [r7, #20]
+}
+/*-----------------------------------------------------------*/
+
+portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue )
+{
+	__asm volatile
+ 8011014:	697b      	ldr	r3, [r7, #20]
+ 8011016:	f383 8811 	msr	BASEPRI, r3
+	(
+		"	msr basepri, %0	" :: "r" ( ulNewMaskValue ) : "memory"
+	);
+}
+ 801101a:	bf00      	nop
+		}
+	}
+	portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+	return xReturn;
+ 801101c:	6bfb      	ldr	r3, [r7, #60]	; 0x3c
+}
+ 801101e:	4618      	mov	r0, r3
+ 8011020:	3740      	adds	r7, #64	; 0x40
+ 8011022:	46bd      	mov	sp, r7
+ 8011024:	bd80      	pop	{r7, pc}
+
+08011026 <xQueueGiveFromISR>:
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueGiveFromISR( QueueHandle_t xQueue, BaseType_t * const pxHigherPriorityTaskWoken )
+{
+ 8011026:	b580      	push	{r7, lr}
+ 8011028:	b08e      	sub	sp, #56	; 0x38
+ 801102a:	af00      	add	r7, sp, #0
+ 801102c:	6078      	str	r0, [r7, #4]
+ 801102e:	6039      	str	r1, [r7, #0]
+BaseType_t xReturn;
+UBaseType_t uxSavedInterruptStatus;
+Queue_t * const pxQueue = xQueue;
+ 8011030:	687b      	ldr	r3, [r7, #4]
+ 8011032:	633b      	str	r3, [r7, #48]	; 0x30
+	item size is 0.  Don't directly wake a task that was blocked on a queue
+	read, instead return a flag to say whether a context switch is required or
+	not (i.e. has a task with a higher priority than us been woken by this
+	post). */
+
+	configASSERT( pxQueue );
+ 8011034:	6b3b      	ldr	r3, [r7, #48]	; 0x30
+ 8011036:	2b00      	cmp	r3, #0
+ 8011038:	d10a      	bne.n	8011050 <xQueueGiveFromISR+0x2a>
+	__asm volatile
+ 801103a:	f04f 0350 	mov.w	r3, #80	; 0x50
+ 801103e:	f383 8811 	msr	BASEPRI, r3
+ 8011042:	f3bf 8f6f 	isb	sy
+ 8011046:	f3bf 8f4f 	dsb	sy
+ 801104a:	623b      	str	r3, [r7, #32]
+}
+ 801104c:	bf00      	nop
+ 801104e:	e7fe      	b.n	801104e <xQueueGiveFromISR+0x28>
+
+	/* xQueueGenericSendFromISR() should be used instead of xQueueGiveFromISR()
+	if the item size is not 0. */
+	configASSERT( pxQueue->uxItemSize == 0 );
+ 8011050:	6b3b      	ldr	r3, [r7, #48]	; 0x30
+ 8011052:	6c1b      	ldr	r3, [r3, #64]	; 0x40
+ 8011054:	2b00      	cmp	r3, #0
+ 8011056:	d00a      	beq.n	801106e <xQueueGiveFromISR+0x48>
+	__asm volatile
+ 8011058:	f04f 0350 	mov.w	r3, #80	; 0x50
+ 801105c:	f383 8811 	msr	BASEPRI, r3
+ 8011060:	f3bf 8f6f 	isb	sy
+ 8011064:	f3bf 8f4f 	dsb	sy
+ 8011068:	61fb      	str	r3, [r7, #28]
+}
+ 801106a:	bf00      	nop
+ 801106c:	e7fe      	b.n	801106c <xQueueGiveFromISR+0x46>
+
+	/* Normally a mutex would not be given from an interrupt, especially if
+	there is a mutex holder, as priority inheritance makes no sense for an
+	interrupts, only tasks. */
+	configASSERT( !( ( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) && ( pxQueue->u.xSemaphore.xMutexHolder != NULL ) ) );
+ 801106e:	6b3b      	ldr	r3, [r7, #48]	; 0x30
+ 8011070:	681b      	ldr	r3, [r3, #0]
+ 8011072:	2b00      	cmp	r3, #0
+ 8011074:	d103      	bne.n	801107e <xQueueGiveFromISR+0x58>
+ 8011076:	6b3b      	ldr	r3, [r7, #48]	; 0x30
+ 8011078:	689b      	ldr	r3, [r3, #8]
+ 801107a:	2b00      	cmp	r3, #0
+ 801107c:	d101      	bne.n	8011082 <xQueueGiveFromISR+0x5c>
+ 801107e:	2301      	movs	r3, #1
+ 8011080:	e000      	b.n	8011084 <xQueueGiveFromISR+0x5e>
+ 8011082:	2300      	movs	r3, #0
+ 8011084:	2b00      	cmp	r3, #0
+ 8011086:	d10a      	bne.n	801109e <xQueueGiveFromISR+0x78>
+	__asm volatile
+ 8011088:	f04f 0350 	mov.w	r3, #80	; 0x50
+ 801108c:	f383 8811 	msr	BASEPRI, r3
+ 8011090:	f3bf 8f6f 	isb	sy
+ 8011094:	f3bf 8f4f 	dsb	sy
+ 8011098:	61bb      	str	r3, [r7, #24]
+}
+ 801109a:	bf00      	nop
+ 801109c:	e7fe      	b.n	801109c <xQueueGiveFromISR+0x76>
+	that have been assigned a priority at or (logically) below the maximum
+	system call	interrupt priority.  FreeRTOS maintains a separate interrupt
+	safe API to ensure interrupt entry is as fast and as simple as possible.
+	More information (albeit Cortex-M specific) is provided on the following
+	link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */
+	portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+ 801109e:	f002 fa93 	bl	80135c8 <vPortValidateInterruptPriority>
+	__asm volatile
+ 80110a2:	f3ef 8211 	mrs	r2, BASEPRI
+ 80110a6:	f04f 0350 	mov.w	r3, #80	; 0x50
+ 80110aa:	f383 8811 	msr	BASEPRI, r3
+ 80110ae:	f3bf 8f6f 	isb	sy
+ 80110b2:	f3bf 8f4f 	dsb	sy
+ 80110b6:	617a      	str	r2, [r7, #20]
+ 80110b8:	613b      	str	r3, [r7, #16]
+	return ulOriginalBASEPRI;
+ 80110ba:	697b      	ldr	r3, [r7, #20]
+
+	uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+ 80110bc:	62fb      	str	r3, [r7, #44]	; 0x2c
+	{
+		const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;
+ 80110be:	6b3b      	ldr	r3, [r7, #48]	; 0x30
+ 80110c0:	6b9b      	ldr	r3, [r3, #56]	; 0x38
+ 80110c2:	62bb      	str	r3, [r7, #40]	; 0x28
+
+		/* When the queue is used to implement a semaphore no data is ever
+		moved through the queue but it is still valid to see if the queue 'has
+		space'. */
+		if( uxMessagesWaiting < pxQueue->uxLength )
+ 80110c4:	6b3b      	ldr	r3, [r7, #48]	; 0x30
+ 80110c6:	6bdb      	ldr	r3, [r3, #60]	; 0x3c
+ 80110c8:	6aba      	ldr	r2, [r7, #40]	; 0x28
+ 80110ca:	429a      	cmp	r2, r3
+ 80110cc:	d22b      	bcs.n	8011126 <xQueueGiveFromISR+0x100>
+		{
+			const int8_t cTxLock = pxQueue->cTxLock;
+ 80110ce:	6b3b      	ldr	r3, [r7, #48]	; 0x30
+ 80110d0:	f893 3045 	ldrb.w	r3, [r3, #69]	; 0x45
+ 80110d4:	f887 3027 	strb.w	r3, [r7, #39]	; 0x27
+			holder - and if there is a mutex holder then the mutex cannot be
+			given from an ISR.  As this is the ISR version of the function it
+			can be assumed there is no mutex holder and no need to determine if
+			priority disinheritance is needed.  Simply increase the count of
+			messages (semaphores) available. */
+			pxQueue->uxMessagesWaiting = uxMessagesWaiting + ( UBaseType_t ) 1;
+ 80110d8:	6abb      	ldr	r3, [r7, #40]	; 0x28
+ 80110da:	1c5a      	adds	r2, r3, #1
+ 80110dc:	6b3b      	ldr	r3, [r7, #48]	; 0x30
+ 80110de:	639a      	str	r2, [r3, #56]	; 0x38
+
+			/* The event list is not altered if the queue is locked.  This will
+			be done when the queue is unlocked later. */
+			if( cTxLock == queueUNLOCKED )
+ 80110e0:	f997 3027 	ldrsb.w	r3, [r7, #39]	; 0x27
+ 80110e4:	f1b3 3fff 	cmp.w	r3, #4294967295
+ 80110e8:	d112      	bne.n	8011110 <xQueueGiveFromISR+0xea>
+						}
+					}
+				}
+				#else /* configUSE_QUEUE_SETS */
+				{
+					if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+ 80110ea:	6b3b      	ldr	r3, [r7, #48]	; 0x30
+ 80110ec:	6a5b      	ldr	r3, [r3, #36]	; 0x24
+ 80110ee:	2b00      	cmp	r3, #0
+ 80110f0:	d016      	beq.n	8011120 <xQueueGiveFromISR+0xfa>
+					{
+						if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+ 80110f2:	6b3b      	ldr	r3, [r7, #48]	; 0x30
+ 80110f4:	3324      	adds	r3, #36	; 0x24
+ 80110f6:	4618      	mov	r0, r3
+ 80110f8:	f001 f912 	bl	8012320 <xTaskRemoveFromEventList>
+ 80110fc:	4603      	mov	r3, r0
+ 80110fe:	2b00      	cmp	r3, #0
+ 8011100:	d00e      	beq.n	8011120 <xQueueGiveFromISR+0xfa>
+						{
+							/* The task waiting has a higher priority so record that a
+							context	switch is required. */
+							if( pxHigherPriorityTaskWoken != NULL )
+ 8011102:	683b      	ldr	r3, [r7, #0]
+ 8011104:	2b00      	cmp	r3, #0
+ 8011106:	d00b      	beq.n	8011120 <xQueueGiveFromISR+0xfa>
+							{
+								*pxHigherPriorityTaskWoken = pdTRUE;
+ 8011108:	683b      	ldr	r3, [r7, #0]
+ 801110a:	2201      	movs	r2, #1
+ 801110c:	601a      	str	r2, [r3, #0]
+ 801110e:	e007      	b.n	8011120 <xQueueGiveFromISR+0xfa>
+			}
+			else
+			{
+				/* Increment the lock count so the task that unlocks the queue
+				knows that data was posted while it was locked. */
+				pxQueue->cTxLock = ( int8_t ) ( cTxLock + 1 );
+ 8011110:	f897 3027 	ldrb.w	r3, [r7, #39]	; 0x27
+ 8011114:	3301      	adds	r3, #1
+ 8011116:	b2db      	uxtb	r3, r3
+ 8011118:	b25a      	sxtb	r2, r3
+ 801111a:	6b3b      	ldr	r3, [r7, #48]	; 0x30
+ 801111c:	f883 2045 	strb.w	r2, [r3, #69]	; 0x45
+			}
+
+			xReturn = pdPASS;
+ 8011120:	2301      	movs	r3, #1
+ 8011122:	637b      	str	r3, [r7, #52]	; 0x34
+ 8011124:	e001      	b.n	801112a <xQueueGiveFromISR+0x104>
+		}
+		else
+		{
+			traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue );
+			xReturn = errQUEUE_FULL;
+ 8011126:	2300      	movs	r3, #0
+ 8011128:	637b      	str	r3, [r7, #52]	; 0x34
+ 801112a:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 801112c:	60fb      	str	r3, [r7, #12]
+	__asm volatile
+ 801112e:	68fb      	ldr	r3, [r7, #12]
+ 8011130:	f383 8811 	msr	BASEPRI, r3
+}
+ 8011134:	bf00      	nop
+		}
+	}
+	portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+	return xReturn;
+ 8011136:	6b7b      	ldr	r3, [r7, #52]	; 0x34
+}
+ 8011138:	4618      	mov	r0, r3
+ 801113a:	3738      	adds	r7, #56	; 0x38
+ 801113c:	46bd      	mov	sp, r7
+ 801113e:	bd80      	pop	{r7, pc}
+
+08011140 <xQueueReceive>:
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueReceive( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait )
+{
+ 8011140:	b580      	push	{r7, lr}
+ 8011142:	b08c      	sub	sp, #48	; 0x30
+ 8011144:	af00      	add	r7, sp, #0
+ 8011146:	60f8      	str	r0, [r7, #12]
+ 8011148:	60b9      	str	r1, [r7, #8]
+ 801114a:	607a      	str	r2, [r7, #4]
+BaseType_t xEntryTimeSet = pdFALSE;
+ 801114c:	2300      	movs	r3, #0
+ 801114e:	62fb      	str	r3, [r7, #44]	; 0x2c
+TimeOut_t xTimeOut;
+Queue_t * const pxQueue = xQueue;
+ 8011150:	68fb      	ldr	r3, [r7, #12]
+ 8011152:	62bb      	str	r3, [r7, #40]	; 0x28
+
+	/* Check the pointer is not NULL. */
+	configASSERT( ( pxQueue ) );
+ 8011154:	6abb      	ldr	r3, [r7, #40]	; 0x28
+ 8011156:	2b00      	cmp	r3, #0
+ 8011158:	d10a      	bne.n	8011170 <xQueueReceive+0x30>
+	__asm volatile
+ 801115a:	f04f 0350 	mov.w	r3, #80	; 0x50
+ 801115e:	f383 8811 	msr	BASEPRI, r3
+ 8011162:	f3bf 8f6f 	isb	sy
+ 8011166:	f3bf 8f4f 	dsb	sy
+ 801116a:	623b      	str	r3, [r7, #32]
+}
+ 801116c:	bf00      	nop
+ 801116e:	e7fe      	b.n	801116e <xQueueReceive+0x2e>
+
+	/* The buffer into which data is received can only be NULL if the data size
+	is zero (so no data is copied into the buffer. */
+	configASSERT( !( ( ( pvBuffer ) == NULL ) && ( ( pxQueue )->uxItemSize != ( UBaseType_t ) 0U ) ) );
+ 8011170:	68bb      	ldr	r3, [r7, #8]
+ 8011172:	2b00      	cmp	r3, #0
+ 8011174:	d103      	bne.n	801117e <xQueueReceive+0x3e>
+ 8011176:	6abb      	ldr	r3, [r7, #40]	; 0x28
+ 8011178:	6c1b      	ldr	r3, [r3, #64]	; 0x40
+ 801117a:	2b00      	cmp	r3, #0
+ 801117c:	d101      	bne.n	8011182 <xQueueReceive+0x42>
+ 801117e:	2301      	movs	r3, #1
+ 8011180:	e000      	b.n	8011184 <xQueueReceive+0x44>
+ 8011182:	2300      	movs	r3, #0
+ 8011184:	2b00      	cmp	r3, #0
+ 8011186:	d10a      	bne.n	801119e <xQueueReceive+0x5e>
+	__asm volatile
+ 8011188:	f04f 0350 	mov.w	r3, #80	; 0x50
+ 801118c:	f383 8811 	msr	BASEPRI, r3
+ 8011190:	f3bf 8f6f 	isb	sy
+ 8011194:	f3bf 8f4f 	dsb	sy
+ 8011198:	61fb      	str	r3, [r7, #28]
+}
+ 801119a:	bf00      	nop
+ 801119c:	e7fe      	b.n	801119c <xQueueReceive+0x5c>
+
+	/* Cannot block if the scheduler is suspended. */
+	#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
+	{
+		configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
+ 801119e:	f001 fab3 	bl	8012708 <xTaskGetSchedulerState>
+ 80111a2:	4603      	mov	r3, r0
+ 80111a4:	2b00      	cmp	r3, #0
+ 80111a6:	d102      	bne.n	80111ae <xQueueReceive+0x6e>
+ 80111a8:	687b      	ldr	r3, [r7, #4]
+ 80111aa:	2b00      	cmp	r3, #0
+ 80111ac:	d101      	bne.n	80111b2 <xQueueReceive+0x72>
+ 80111ae:	2301      	movs	r3, #1
+ 80111b0:	e000      	b.n	80111b4 <xQueueReceive+0x74>
+ 80111b2:	2300      	movs	r3, #0
+ 80111b4:	2b00      	cmp	r3, #0
+ 80111b6:	d10a      	bne.n	80111ce <xQueueReceive+0x8e>
+	__asm volatile
+ 80111b8:	f04f 0350 	mov.w	r3, #80	; 0x50
+ 80111bc:	f383 8811 	msr	BASEPRI, r3
+ 80111c0:	f3bf 8f6f 	isb	sy
+ 80111c4:	f3bf 8f4f 	dsb	sy
+ 80111c8:	61bb      	str	r3, [r7, #24]
+}
+ 80111ca:	bf00      	nop
+ 80111cc:	e7fe      	b.n	80111cc <xQueueReceive+0x8c>
+	/*lint -save -e904  This function relaxes the coding standard somewhat to
+	allow return statements within the function itself.  This is done in the
+	interest of execution time efficiency. */
+	for( ;; )
+	{
+		taskENTER_CRITICAL();
+ 80111ce:	f002 f919 	bl	8013404 <vPortEnterCritical>
+		{
+			const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;
+ 80111d2:	6abb      	ldr	r3, [r7, #40]	; 0x28
+ 80111d4:	6b9b      	ldr	r3, [r3, #56]	; 0x38
+ 80111d6:	627b      	str	r3, [r7, #36]	; 0x24
+
+			/* Is there data in the queue now?  To be running the calling task
+			must be the highest priority task wanting to access the queue. */
+			if( uxMessagesWaiting > ( UBaseType_t ) 0 )
+ 80111d8:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 80111da:	2b00      	cmp	r3, #0
+ 80111dc:	d01f      	beq.n	801121e <xQueueReceive+0xde>
+			{
+				/* Data available, remove one item. */
+				prvCopyDataFromQueue( pxQueue, pvBuffer );
+ 80111de:	68b9      	ldr	r1, [r7, #8]
+ 80111e0:	6ab8      	ldr	r0, [r7, #40]	; 0x28
+ 80111e2:	f000 fafa 	bl	80117da <prvCopyDataFromQueue>
+				traceQUEUE_RECEIVE( pxQueue );
+				pxQueue->uxMessagesWaiting = uxMessagesWaiting - ( UBaseType_t ) 1;
+ 80111e6:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 80111e8:	1e5a      	subs	r2, r3, #1
+ 80111ea:	6abb      	ldr	r3, [r7, #40]	; 0x28
+ 80111ec:	639a      	str	r2, [r3, #56]	; 0x38
+
+				/* There is now space in the queue, were any tasks waiting to
+				post to the queue?  If so, unblock the highest priority waiting
+				task. */
+				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
+ 80111ee:	6abb      	ldr	r3, [r7, #40]	; 0x28
+ 80111f0:	691b      	ldr	r3, [r3, #16]
+ 80111f2:	2b00      	cmp	r3, #0
+ 80111f4:	d00f      	beq.n	8011216 <xQueueReceive+0xd6>
+				{
+					if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
+ 80111f6:	6abb      	ldr	r3, [r7, #40]	; 0x28
+ 80111f8:	3310      	adds	r3, #16
+ 80111fa:	4618      	mov	r0, r3
+ 80111fc:	f001 f890 	bl	8012320 <xTaskRemoveFromEventList>
+ 8011200:	4603      	mov	r3, r0
+ 8011202:	2b00      	cmp	r3, #0
+ 8011204:	d007      	beq.n	8011216 <xQueueReceive+0xd6>
+					{
+						queueYIELD_IF_USING_PREEMPTION();
+ 8011206:	4b3d      	ldr	r3, [pc, #244]	; (80112fc <xQueueReceive+0x1bc>)
+ 8011208:	f04f 5280 	mov.w	r2, #268435456	; 0x10000000
+ 801120c:	601a      	str	r2, [r3, #0]
+ 801120e:	f3bf 8f4f 	dsb	sy
+ 8011212:	f3bf 8f6f 	isb	sy
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+
+				taskEXIT_CRITICAL();
+ 8011216:	f002 f925 	bl	8013464 <vPortExitCritical>
+				return pdPASS;
+ 801121a:	2301      	movs	r3, #1
+ 801121c:	e069      	b.n	80112f2 <xQueueReceive+0x1b2>
+			}
+			else
+			{
+				if( xTicksToWait == ( TickType_t ) 0 )
+ 801121e:	687b      	ldr	r3, [r7, #4]
+ 8011220:	2b00      	cmp	r3, #0
+ 8011222:	d103      	bne.n	801122c <xQueueReceive+0xec>
+				{
+					/* The queue was empty and no block time is specified (or
+					the block time has expired) so leave now. */
+					taskEXIT_CRITICAL();
+ 8011224:	f002 f91e 	bl	8013464 <vPortExitCritical>
+					traceQUEUE_RECEIVE_FAILED( pxQueue );
+					return errQUEUE_EMPTY;
+ 8011228:	2300      	movs	r3, #0
+ 801122a:	e062      	b.n	80112f2 <xQueueReceive+0x1b2>
+				}
+				else if( xEntryTimeSet == pdFALSE )
+ 801122c:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 801122e:	2b00      	cmp	r3, #0
+ 8011230:	d106      	bne.n	8011240 <xQueueReceive+0x100>
+				{
+					/* The queue was empty and a block time was specified so
+					configure the timeout structure. */
+					vTaskInternalSetTimeOutState( &xTimeOut );
+ 8011232:	f107 0310 	add.w	r3, r7, #16
+ 8011236:	4618      	mov	r0, r3
+ 8011238:	f001 f8d4 	bl	80123e4 <vTaskInternalSetTimeOutState>
+					xEntryTimeSet = pdTRUE;
+ 801123c:	2301      	movs	r3, #1
+ 801123e:	62fb      	str	r3, [r7, #44]	; 0x2c
+					/* Entry time was already set. */
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+		}
+		taskEXIT_CRITICAL();
+ 8011240:	f002 f910 	bl	8013464 <vPortExitCritical>
+
+		/* Interrupts and other tasks can send to and receive from the queue
+		now the critical section has been exited. */
+
+		vTaskSuspendAll();
+ 8011244:	f000 fe2e 	bl	8011ea4 <vTaskSuspendAll>
+		prvLockQueue( pxQueue );
+ 8011248:	f002 f8dc 	bl	8013404 <vPortEnterCritical>
+ 801124c:	6abb      	ldr	r3, [r7, #40]	; 0x28
+ 801124e:	f893 3044 	ldrb.w	r3, [r3, #68]	; 0x44
+ 8011252:	b25b      	sxtb	r3, r3
+ 8011254:	f1b3 3fff 	cmp.w	r3, #4294967295
+ 8011258:	d103      	bne.n	8011262 <xQueueReceive+0x122>
+ 801125a:	6abb      	ldr	r3, [r7, #40]	; 0x28
+ 801125c:	2200      	movs	r2, #0
+ 801125e:	f883 2044 	strb.w	r2, [r3, #68]	; 0x44
+ 8011262:	6abb      	ldr	r3, [r7, #40]	; 0x28
+ 8011264:	f893 3045 	ldrb.w	r3, [r3, #69]	; 0x45
+ 8011268:	b25b      	sxtb	r3, r3
+ 801126a:	f1b3 3fff 	cmp.w	r3, #4294967295
+ 801126e:	d103      	bne.n	8011278 <xQueueReceive+0x138>
+ 8011270:	6abb      	ldr	r3, [r7, #40]	; 0x28
+ 8011272:	2200      	movs	r2, #0
+ 8011274:	f883 2045 	strb.w	r2, [r3, #69]	; 0x45
+ 8011278:	f002 f8f4 	bl	8013464 <vPortExitCritical>
+
+		/* Update the timeout state to see if it has expired yet. */
+		if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
+ 801127c:	1d3a      	adds	r2, r7, #4
+ 801127e:	f107 0310 	add.w	r3, r7, #16
+ 8011282:	4611      	mov	r1, r2
+ 8011284:	4618      	mov	r0, r3
+ 8011286:	f001 f8c3 	bl	8012410 <xTaskCheckForTimeOut>
+ 801128a:	4603      	mov	r3, r0
+ 801128c:	2b00      	cmp	r3, #0
+ 801128e:	d123      	bne.n	80112d8 <xQueueReceive+0x198>
+		{
+			/* The timeout has not expired.  If the queue is still empty place
+			the task on the list of tasks waiting to receive from the queue. */
+			if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
+ 8011290:	6ab8      	ldr	r0, [r7, #40]	; 0x28
+ 8011292:	f000 fb1a 	bl	80118ca <prvIsQueueEmpty>
+ 8011296:	4603      	mov	r3, r0
+ 8011298:	2b00      	cmp	r3, #0
+ 801129a:	d017      	beq.n	80112cc <xQueueReceive+0x18c>
+			{
+				traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue );
+				vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait );
+ 801129c:	6abb      	ldr	r3, [r7, #40]	; 0x28
+ 801129e:	3324      	adds	r3, #36	; 0x24
+ 80112a0:	687a      	ldr	r2, [r7, #4]
+ 80112a2:	4611      	mov	r1, r2
+ 80112a4:	4618      	mov	r0, r3
+ 80112a6:	f000 ffeb 	bl	8012280 <vTaskPlaceOnEventList>
+				prvUnlockQueue( pxQueue );
+ 80112aa:	6ab8      	ldr	r0, [r7, #40]	; 0x28
+ 80112ac:	f000 fabb 	bl	8011826 <prvUnlockQueue>
+				if( xTaskResumeAll() == pdFALSE )
+ 80112b0:	f000 fe06 	bl	8011ec0 <xTaskResumeAll>
+ 80112b4:	4603      	mov	r3, r0
+ 80112b6:	2b00      	cmp	r3, #0
+ 80112b8:	d189      	bne.n	80111ce <xQueueReceive+0x8e>
+				{
+					portYIELD_WITHIN_API();
+ 80112ba:	4b10      	ldr	r3, [pc, #64]	; (80112fc <xQueueReceive+0x1bc>)
+ 80112bc:	f04f 5280 	mov.w	r2, #268435456	; 0x10000000
+ 80112c0:	601a      	str	r2, [r3, #0]
+ 80112c2:	f3bf 8f4f 	dsb	sy
+ 80112c6:	f3bf 8f6f 	isb	sy
+ 80112ca:	e780      	b.n	80111ce <xQueueReceive+0x8e>
+			}
+			else
+			{
+				/* The queue contains data again.  Loop back to try and read the
+				data. */
+				prvUnlockQueue( pxQueue );
+ 80112cc:	6ab8      	ldr	r0, [r7, #40]	; 0x28
+ 80112ce:	f000 faaa 	bl	8011826 <prvUnlockQueue>
+				( void ) xTaskResumeAll();
+ 80112d2:	f000 fdf5 	bl	8011ec0 <xTaskResumeAll>
+ 80112d6:	e77a      	b.n	80111ce <xQueueReceive+0x8e>
+		}
+		else
+		{
+			/* Timed out.  If there is no data in the queue exit, otherwise loop
+			back and attempt to read the data. */
+			prvUnlockQueue( pxQueue );
+ 80112d8:	6ab8      	ldr	r0, [r7, #40]	; 0x28
+ 80112da:	f000 faa4 	bl	8011826 <prvUnlockQueue>
+			( void ) xTaskResumeAll();
+ 80112de:	f000 fdef 	bl	8011ec0 <xTaskResumeAll>
+
+			if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
+ 80112e2:	6ab8      	ldr	r0, [r7, #40]	; 0x28
+ 80112e4:	f000 faf1 	bl	80118ca <prvIsQueueEmpty>
+ 80112e8:	4603      	mov	r3, r0
+ 80112ea:	2b00      	cmp	r3, #0
+ 80112ec:	f43f af6f 	beq.w	80111ce <xQueueReceive+0x8e>
+			{
+				traceQUEUE_RECEIVE_FAILED( pxQueue );
+				return errQUEUE_EMPTY;
+ 80112f0:	2300      	movs	r3, #0
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+	} /*lint -restore */
+}
+ 80112f2:	4618      	mov	r0, r3
+ 80112f4:	3730      	adds	r7, #48	; 0x30
+ 80112f6:	46bd      	mov	sp, r7
+ 80112f8:	bd80      	pop	{r7, pc}
+ 80112fa:	bf00      	nop
+ 80112fc:	e000ed04 	.word	0xe000ed04
+
+08011300 <xQueueSemaphoreTake>:
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueSemaphoreTake( QueueHandle_t xQueue, TickType_t xTicksToWait )
+{
+ 8011300:	b580      	push	{r7, lr}
+ 8011302:	b08e      	sub	sp, #56	; 0x38
+ 8011304:	af00      	add	r7, sp, #0
+ 8011306:	6078      	str	r0, [r7, #4]
+ 8011308:	6039      	str	r1, [r7, #0]
+BaseType_t xEntryTimeSet = pdFALSE;
+ 801130a:	2300      	movs	r3, #0
+ 801130c:	637b      	str	r3, [r7, #52]	; 0x34
+TimeOut_t xTimeOut;
+Queue_t * const pxQueue = xQueue;
+ 801130e:	687b      	ldr	r3, [r7, #4]
+ 8011310:	62fb      	str	r3, [r7, #44]	; 0x2c
+
+#if( configUSE_MUTEXES == 1 )
+	BaseType_t xInheritanceOccurred = pdFALSE;
+ 8011312:	2300      	movs	r3, #0
+ 8011314:	633b      	str	r3, [r7, #48]	; 0x30
+#endif
+
+	/* Check the queue pointer is not NULL. */
+	configASSERT( ( pxQueue ) );
+ 8011316:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 8011318:	2b00      	cmp	r3, #0
+ 801131a:	d10a      	bne.n	8011332 <xQueueSemaphoreTake+0x32>
+	__asm volatile
+ 801131c:	f04f 0350 	mov.w	r3, #80	; 0x50
+ 8011320:	f383 8811 	msr	BASEPRI, r3
+ 8011324:	f3bf 8f6f 	isb	sy
+ 8011328:	f3bf 8f4f 	dsb	sy
+ 801132c:	623b      	str	r3, [r7, #32]
+}
+ 801132e:	bf00      	nop
+ 8011330:	e7fe      	b.n	8011330 <xQueueSemaphoreTake+0x30>
+
+	/* Check this really is a semaphore, in which case the item size will be
+	0. */
+	configASSERT( pxQueue->uxItemSize == 0 );
+ 8011332:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 8011334:	6c1b      	ldr	r3, [r3, #64]	; 0x40
+ 8011336:	2b00      	cmp	r3, #0
+ 8011338:	d00a      	beq.n	8011350 <xQueueSemaphoreTake+0x50>
+	__asm volatile
+ 801133a:	f04f 0350 	mov.w	r3, #80	; 0x50
+ 801133e:	f383 8811 	msr	BASEPRI, r3
+ 8011342:	f3bf 8f6f 	isb	sy
+ 8011346:	f3bf 8f4f 	dsb	sy
+ 801134a:	61fb      	str	r3, [r7, #28]
+}
+ 801134c:	bf00      	nop
+ 801134e:	e7fe      	b.n	801134e <xQueueSemaphoreTake+0x4e>
+
+	/* Cannot block if the scheduler is suspended. */
+	#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
+	{
+		configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
+ 8011350:	f001 f9da 	bl	8012708 <xTaskGetSchedulerState>
+ 8011354:	4603      	mov	r3, r0
+ 8011356:	2b00      	cmp	r3, #0
+ 8011358:	d102      	bne.n	8011360 <xQueueSemaphoreTake+0x60>
+ 801135a:	683b      	ldr	r3, [r7, #0]
+ 801135c:	2b00      	cmp	r3, #0
+ 801135e:	d101      	bne.n	8011364 <xQueueSemaphoreTake+0x64>
+ 8011360:	2301      	movs	r3, #1
+ 8011362:	e000      	b.n	8011366 <xQueueSemaphoreTake+0x66>
+ 8011364:	2300      	movs	r3, #0
+ 8011366:	2b00      	cmp	r3, #0
+ 8011368:	d10a      	bne.n	8011380 <xQueueSemaphoreTake+0x80>
+	__asm volatile
+ 801136a:	f04f 0350 	mov.w	r3, #80	; 0x50
+ 801136e:	f383 8811 	msr	BASEPRI, r3
+ 8011372:	f3bf 8f6f 	isb	sy
+ 8011376:	f3bf 8f4f 	dsb	sy
+ 801137a:	61bb      	str	r3, [r7, #24]
+}
+ 801137c:	bf00      	nop
+ 801137e:	e7fe      	b.n	801137e <xQueueSemaphoreTake+0x7e>
+	/*lint -save -e904 This function relaxes the coding standard somewhat to allow return
+	statements within the function itself.  This is done in the interest
+	of execution time efficiency. */
+	for( ;; )
+	{
+		taskENTER_CRITICAL();
+ 8011380:	f002 f840 	bl	8013404 <vPortEnterCritical>
+		{
+			/* Semaphores are queues with an item size of 0, and where the
+			number of messages in the queue is the semaphore's count value. */
+			const UBaseType_t uxSemaphoreCount = pxQueue->uxMessagesWaiting;
+ 8011384:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 8011386:	6b9b      	ldr	r3, [r3, #56]	; 0x38
+ 8011388:	62bb      	str	r3, [r7, #40]	; 0x28
+
+			/* Is there data in the queue now?  To be running the calling task
+			must be the highest priority task wanting to access the queue. */
+			if( uxSemaphoreCount > ( UBaseType_t ) 0 )
+ 801138a:	6abb      	ldr	r3, [r7, #40]	; 0x28
+ 801138c:	2b00      	cmp	r3, #0
+ 801138e:	d024      	beq.n	80113da <xQueueSemaphoreTake+0xda>
+			{
+				traceQUEUE_RECEIVE( pxQueue );
+
+				/* Semaphores are queues with a data size of zero and where the
+				messages waiting is the semaphore's count.  Reduce the count. */
+				pxQueue->uxMessagesWaiting = uxSemaphoreCount - ( UBaseType_t ) 1;
+ 8011390:	6abb      	ldr	r3, [r7, #40]	; 0x28
+ 8011392:	1e5a      	subs	r2, r3, #1
+ 8011394:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 8011396:	639a      	str	r2, [r3, #56]	; 0x38
+
+				#if ( configUSE_MUTEXES == 1 )
+				{
+					if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )
+ 8011398:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 801139a:	681b      	ldr	r3, [r3, #0]
+ 801139c:	2b00      	cmp	r3, #0
+ 801139e:	d104      	bne.n	80113aa <xQueueSemaphoreTake+0xaa>
+					{
+						/* Record the information required to implement
+						priority inheritance should it become necessary. */
+						pxQueue->u.xSemaphore.xMutexHolder = pvTaskIncrementMutexHeldCount();
+ 80113a0:	f001 fb5a 	bl	8012a58 <pvTaskIncrementMutexHeldCount>
+ 80113a4:	4602      	mov	r2, r0
+ 80113a6:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 80113a8:	609a      	str	r2, [r3, #8]
+				}
+				#endif /* configUSE_MUTEXES */
+
+				/* Check to see if other tasks are blocked waiting to give the
+				semaphore, and if so, unblock the highest priority such task. */
+				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
+ 80113aa:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 80113ac:	691b      	ldr	r3, [r3, #16]
+ 80113ae:	2b00      	cmp	r3, #0
+ 80113b0:	d00f      	beq.n	80113d2 <xQueueSemaphoreTake+0xd2>
+				{
+					if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
+ 80113b2:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 80113b4:	3310      	adds	r3, #16
+ 80113b6:	4618      	mov	r0, r3
+ 80113b8:	f000 ffb2 	bl	8012320 <xTaskRemoveFromEventList>
+ 80113bc:	4603      	mov	r3, r0
+ 80113be:	2b00      	cmp	r3, #0
+ 80113c0:	d007      	beq.n	80113d2 <xQueueSemaphoreTake+0xd2>
+					{
+						queueYIELD_IF_USING_PREEMPTION();
+ 80113c2:	4b54      	ldr	r3, [pc, #336]	; (8011514 <xQueueSemaphoreTake+0x214>)
+ 80113c4:	f04f 5280 	mov.w	r2, #268435456	; 0x10000000
+ 80113c8:	601a      	str	r2, [r3, #0]
+ 80113ca:	f3bf 8f4f 	dsb	sy
+ 80113ce:	f3bf 8f6f 	isb	sy
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+
+				taskEXIT_CRITICAL();
+ 80113d2:	f002 f847 	bl	8013464 <vPortExitCritical>
+				return pdPASS;
+ 80113d6:	2301      	movs	r3, #1
+ 80113d8:	e097      	b.n	801150a <xQueueSemaphoreTake+0x20a>
+			}
+			else
+			{
+				if( xTicksToWait == ( TickType_t ) 0 )
+ 80113da:	683b      	ldr	r3, [r7, #0]
+ 80113dc:	2b00      	cmp	r3, #0
+ 80113de:	d111      	bne.n	8011404 <xQueueSemaphoreTake+0x104>
+					/* For inheritance to have occurred there must have been an
+					initial timeout, and an adjusted timeout cannot become 0, as
+					if it were 0 the function would have exited. */
+					#if( configUSE_MUTEXES == 1 )
+					{
+						configASSERT( xInheritanceOccurred == pdFALSE );
+ 80113e0:	6b3b      	ldr	r3, [r7, #48]	; 0x30
+ 80113e2:	2b00      	cmp	r3, #0
+ 80113e4:	d00a      	beq.n	80113fc <xQueueSemaphoreTake+0xfc>
+	__asm volatile
+ 80113e6:	f04f 0350 	mov.w	r3, #80	; 0x50
+ 80113ea:	f383 8811 	msr	BASEPRI, r3
+ 80113ee:	f3bf 8f6f 	isb	sy
+ 80113f2:	f3bf 8f4f 	dsb	sy
+ 80113f6:	617b      	str	r3, [r7, #20]
+}
+ 80113f8:	bf00      	nop
+ 80113fa:	e7fe      	b.n	80113fa <xQueueSemaphoreTake+0xfa>
+					}
+					#endif /* configUSE_MUTEXES */
+
+					/* The semaphore count was 0 and no block time is specified
+					(or the block time has expired) so exit now. */
+					taskEXIT_CRITICAL();
+ 80113fc:	f002 f832 	bl	8013464 <vPortExitCritical>
+					traceQUEUE_RECEIVE_FAILED( pxQueue );
+					return errQUEUE_EMPTY;
+ 8011400:	2300      	movs	r3, #0
+ 8011402:	e082      	b.n	801150a <xQueueSemaphoreTake+0x20a>
+				}
+				else if( xEntryTimeSet == pdFALSE )
+ 8011404:	6b7b      	ldr	r3, [r7, #52]	; 0x34
+ 8011406:	2b00      	cmp	r3, #0
+ 8011408:	d106      	bne.n	8011418 <xQueueSemaphoreTake+0x118>
+				{
+					/* The semaphore count was 0 and a block time was specified
+					so configure the timeout structure ready to block. */
+					vTaskInternalSetTimeOutState( &xTimeOut );
+ 801140a:	f107 030c 	add.w	r3, r7, #12
+ 801140e:	4618      	mov	r0, r3
+ 8011410:	f000 ffe8 	bl	80123e4 <vTaskInternalSetTimeOutState>
+					xEntryTimeSet = pdTRUE;
+ 8011414:	2301      	movs	r3, #1
+ 8011416:	637b      	str	r3, [r7, #52]	; 0x34
+					/* Entry time was already set. */
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+		}
+		taskEXIT_CRITICAL();
+ 8011418:	f002 f824 	bl	8013464 <vPortExitCritical>
+
+		/* Interrupts and other tasks can give to and take from the semaphore
+		now the critical section has been exited. */
+
+		vTaskSuspendAll();
+ 801141c:	f000 fd42 	bl	8011ea4 <vTaskSuspendAll>
+		prvLockQueue( pxQueue );
+ 8011420:	f001 fff0 	bl	8013404 <vPortEnterCritical>
+ 8011424:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 8011426:	f893 3044 	ldrb.w	r3, [r3, #68]	; 0x44
+ 801142a:	b25b      	sxtb	r3, r3
+ 801142c:	f1b3 3fff 	cmp.w	r3, #4294967295
+ 8011430:	d103      	bne.n	801143a <xQueueSemaphoreTake+0x13a>
+ 8011432:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 8011434:	2200      	movs	r2, #0
+ 8011436:	f883 2044 	strb.w	r2, [r3, #68]	; 0x44
+ 801143a:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 801143c:	f893 3045 	ldrb.w	r3, [r3, #69]	; 0x45
+ 8011440:	b25b      	sxtb	r3, r3
+ 8011442:	f1b3 3fff 	cmp.w	r3, #4294967295
+ 8011446:	d103      	bne.n	8011450 <xQueueSemaphoreTake+0x150>
+ 8011448:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 801144a:	2200      	movs	r2, #0
+ 801144c:	f883 2045 	strb.w	r2, [r3, #69]	; 0x45
+ 8011450:	f002 f808 	bl	8013464 <vPortExitCritical>
+
+		/* Update the timeout state to see if it has expired yet. */
+		if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
+ 8011454:	463a      	mov	r2, r7
+ 8011456:	f107 030c 	add.w	r3, r7, #12
+ 801145a:	4611      	mov	r1, r2
+ 801145c:	4618      	mov	r0, r3
+ 801145e:	f000 ffd7 	bl	8012410 <xTaskCheckForTimeOut>
+ 8011462:	4603      	mov	r3, r0
+ 8011464:	2b00      	cmp	r3, #0
+ 8011466:	d132      	bne.n	80114ce <xQueueSemaphoreTake+0x1ce>
+		{
+			/* A block time is specified and not expired.  If the semaphore
+			count is 0 then enter the Blocked state to wait for a semaphore to
+			become available.  As semaphores are implemented with queues the
+			queue being empty is equivalent to the semaphore count being 0. */
+			if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
+ 8011468:	6af8      	ldr	r0, [r7, #44]	; 0x2c
+ 801146a:	f000 fa2e 	bl	80118ca <prvIsQueueEmpty>
+ 801146e:	4603      	mov	r3, r0
+ 8011470:	2b00      	cmp	r3, #0
+ 8011472:	d026      	beq.n	80114c2 <xQueueSemaphoreTake+0x1c2>
+			{
+				traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue );
+
+				#if ( configUSE_MUTEXES == 1 )
+				{
+					if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )
+ 8011474:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 8011476:	681b      	ldr	r3, [r3, #0]
+ 8011478:	2b00      	cmp	r3, #0
+ 801147a:	d109      	bne.n	8011490 <xQueueSemaphoreTake+0x190>
+					{
+						taskENTER_CRITICAL();
+ 801147c:	f001 ffc2 	bl	8013404 <vPortEnterCritical>
+						{
+							xInheritanceOccurred = xTaskPriorityInherit( pxQueue->u.xSemaphore.xMutexHolder );
+ 8011480:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 8011482:	689b      	ldr	r3, [r3, #8]
+ 8011484:	4618      	mov	r0, r3
+ 8011486:	f001 f95d 	bl	8012744 <xTaskPriorityInherit>
+ 801148a:	6338      	str	r0, [r7, #48]	; 0x30
+						}
+						taskEXIT_CRITICAL();
+ 801148c:	f001 ffea 	bl	8013464 <vPortExitCritical>
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				#endif
+
+				vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait );
+ 8011490:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 8011492:	3324      	adds	r3, #36	; 0x24
+ 8011494:	683a      	ldr	r2, [r7, #0]
+ 8011496:	4611      	mov	r1, r2
+ 8011498:	4618      	mov	r0, r3
+ 801149a:	f000 fef1 	bl	8012280 <vTaskPlaceOnEventList>
+				prvUnlockQueue( pxQueue );
+ 801149e:	6af8      	ldr	r0, [r7, #44]	; 0x2c
+ 80114a0:	f000 f9c1 	bl	8011826 <prvUnlockQueue>
+				if( xTaskResumeAll() == pdFALSE )
+ 80114a4:	f000 fd0c 	bl	8011ec0 <xTaskResumeAll>
+ 80114a8:	4603      	mov	r3, r0
+ 80114aa:	2b00      	cmp	r3, #0
+ 80114ac:	f47f af68 	bne.w	8011380 <xQueueSemaphoreTake+0x80>
+				{
+					portYIELD_WITHIN_API();
+ 80114b0:	4b18      	ldr	r3, [pc, #96]	; (8011514 <xQueueSemaphoreTake+0x214>)
+ 80114b2:	f04f 5280 	mov.w	r2, #268435456	; 0x10000000
+ 80114b6:	601a      	str	r2, [r3, #0]
+ 80114b8:	f3bf 8f4f 	dsb	sy
+ 80114bc:	f3bf 8f6f 	isb	sy
+ 80114c0:	e75e      	b.n	8011380 <xQueueSemaphoreTake+0x80>
+			}
+			else
+			{
+				/* There was no timeout and the semaphore count was not 0, so
+				attempt to take the semaphore again. */
+				prvUnlockQueue( pxQueue );
+ 80114c2:	6af8      	ldr	r0, [r7, #44]	; 0x2c
+ 80114c4:	f000 f9af 	bl	8011826 <prvUnlockQueue>
+				( void ) xTaskResumeAll();
+ 80114c8:	f000 fcfa 	bl	8011ec0 <xTaskResumeAll>
+ 80114cc:	e758      	b.n	8011380 <xQueueSemaphoreTake+0x80>
+			}
+		}
+		else
+		{
+			/* Timed out. */
+			prvUnlockQueue( pxQueue );
+ 80114ce:	6af8      	ldr	r0, [r7, #44]	; 0x2c
+ 80114d0:	f000 f9a9 	bl	8011826 <prvUnlockQueue>
+			( void ) xTaskResumeAll();
+ 80114d4:	f000 fcf4 	bl	8011ec0 <xTaskResumeAll>
+
+			/* If the semaphore count is 0 exit now as the timeout has
+			expired.  Otherwise return to attempt to take the semaphore that is
+			known to be available.  As semaphores are implemented by queues the
+			queue being empty is equivalent to the semaphore count being 0. */
+			if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
+ 80114d8:	6af8      	ldr	r0, [r7, #44]	; 0x2c
+ 80114da:	f000 f9f6 	bl	80118ca <prvIsQueueEmpty>
+ 80114de:	4603      	mov	r3, r0
+ 80114e0:	2b00      	cmp	r3, #0
+ 80114e2:	f43f af4d 	beq.w	8011380 <xQueueSemaphoreTake+0x80>
+				#if ( configUSE_MUTEXES == 1 )
+				{
+					/* xInheritanceOccurred could only have be set if
+					pxQueue->uxQueueType == queueQUEUE_IS_MUTEX so no need to
+					test the mutex type again to check it is actually a mutex. */
+					if( xInheritanceOccurred != pdFALSE )
+ 80114e6:	6b3b      	ldr	r3, [r7, #48]	; 0x30
+ 80114e8:	2b00      	cmp	r3, #0
+ 80114ea:	d00d      	beq.n	8011508 <xQueueSemaphoreTake+0x208>
+					{
+						taskENTER_CRITICAL();
+ 80114ec:	f001 ff8a 	bl	8013404 <vPortEnterCritical>
+							/* This task blocking on the mutex caused another
+							task to inherit this task's priority.  Now this task
+							has timed out the priority should be disinherited
+							again, but only as low as the next highest priority
+							task that is waiting for the same mutex. */
+							uxHighestWaitingPriority = prvGetDisinheritPriorityAfterTimeout( pxQueue );
+ 80114f0:	6af8      	ldr	r0, [r7, #44]	; 0x2c
+ 80114f2:	f000 f8f0 	bl	80116d6 <prvGetDisinheritPriorityAfterTimeout>
+ 80114f6:	6278      	str	r0, [r7, #36]	; 0x24
+							vTaskPriorityDisinheritAfterTimeout( pxQueue->u.xSemaphore.xMutexHolder, uxHighestWaitingPriority );
+ 80114f8:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 80114fa:	689b      	ldr	r3, [r3, #8]
+ 80114fc:	6a79      	ldr	r1, [r7, #36]	; 0x24
+ 80114fe:	4618      	mov	r0, r3
+ 8011500:	f001 fa1c 	bl	801293c <vTaskPriorityDisinheritAfterTimeout>
+						}
+						taskEXIT_CRITICAL();
+ 8011504:	f001 ffae 	bl	8013464 <vPortExitCritical>
+					}
+				}
+				#endif /* configUSE_MUTEXES */
+
+				traceQUEUE_RECEIVE_FAILED( pxQueue );
+				return errQUEUE_EMPTY;
+ 8011508:	2300      	movs	r3, #0
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+	} /*lint -restore */
+}
+ 801150a:	4618      	mov	r0, r3
+ 801150c:	3738      	adds	r7, #56	; 0x38
+ 801150e:	46bd      	mov	sp, r7
+ 8011510:	bd80      	pop	{r7, pc}
+ 8011512:	bf00      	nop
+ 8011514:	e000ed04 	.word	0xe000ed04
+
+08011518 <xQueueReceiveFromISR>:
+	} /*lint -restore */
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueReceiveFromISR( QueueHandle_t xQueue, void * const pvBuffer, BaseType_t * const pxHigherPriorityTaskWoken )
+{
+ 8011518:	b580      	push	{r7, lr}
+ 801151a:	b08e      	sub	sp, #56	; 0x38
+ 801151c:	af00      	add	r7, sp, #0
+ 801151e:	60f8      	str	r0, [r7, #12]
+ 8011520:	60b9      	str	r1, [r7, #8]
+ 8011522:	607a      	str	r2, [r7, #4]
+BaseType_t xReturn;
+UBaseType_t uxSavedInterruptStatus;
+Queue_t * const pxQueue = xQueue;
+ 8011524:	68fb      	ldr	r3, [r7, #12]
+ 8011526:	633b      	str	r3, [r7, #48]	; 0x30
+
+	configASSERT( pxQueue );
+ 8011528:	6b3b      	ldr	r3, [r7, #48]	; 0x30
+ 801152a:	2b00      	cmp	r3, #0
+ 801152c:	d10a      	bne.n	8011544 <xQueueReceiveFromISR+0x2c>
+	__asm volatile
+ 801152e:	f04f 0350 	mov.w	r3, #80	; 0x50
+ 8011532:	f383 8811 	msr	BASEPRI, r3
+ 8011536:	f3bf 8f6f 	isb	sy
+ 801153a:	f3bf 8f4f 	dsb	sy
+ 801153e:	623b      	str	r3, [r7, #32]
+}
+ 8011540:	bf00      	nop
+ 8011542:	e7fe      	b.n	8011542 <xQueueReceiveFromISR+0x2a>
+	configASSERT( !( ( pvBuffer == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
+ 8011544:	68bb      	ldr	r3, [r7, #8]
+ 8011546:	2b00      	cmp	r3, #0
+ 8011548:	d103      	bne.n	8011552 <xQueueReceiveFromISR+0x3a>
+ 801154a:	6b3b      	ldr	r3, [r7, #48]	; 0x30
+ 801154c:	6c1b      	ldr	r3, [r3, #64]	; 0x40
+ 801154e:	2b00      	cmp	r3, #0
+ 8011550:	d101      	bne.n	8011556 <xQueueReceiveFromISR+0x3e>
+ 8011552:	2301      	movs	r3, #1
+ 8011554:	e000      	b.n	8011558 <xQueueReceiveFromISR+0x40>
+ 8011556:	2300      	movs	r3, #0
+ 8011558:	2b00      	cmp	r3, #0
+ 801155a:	d10a      	bne.n	8011572 <xQueueReceiveFromISR+0x5a>
+	__asm volatile
+ 801155c:	f04f 0350 	mov.w	r3, #80	; 0x50
+ 8011560:	f383 8811 	msr	BASEPRI, r3
+ 8011564:	f3bf 8f6f 	isb	sy
+ 8011568:	f3bf 8f4f 	dsb	sy
+ 801156c:	61fb      	str	r3, [r7, #28]
+}
+ 801156e:	bf00      	nop
+ 8011570:	e7fe      	b.n	8011570 <xQueueReceiveFromISR+0x58>
+	that have been assigned a priority at or (logically) below the maximum
+	system call	interrupt priority.  FreeRTOS maintains a separate interrupt
+	safe API to ensure interrupt entry is as fast and as simple as possible.
+	More information (albeit Cortex-M specific) is provided on the following
+	link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */
+	portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+ 8011572:	f002 f829 	bl	80135c8 <vPortValidateInterruptPriority>
+	__asm volatile
+ 8011576:	f3ef 8211 	mrs	r2, BASEPRI
+ 801157a:	f04f 0350 	mov.w	r3, #80	; 0x50
+ 801157e:	f383 8811 	msr	BASEPRI, r3
+ 8011582:	f3bf 8f6f 	isb	sy
+ 8011586:	f3bf 8f4f 	dsb	sy
+ 801158a:	61ba      	str	r2, [r7, #24]
+ 801158c:	617b      	str	r3, [r7, #20]
+	return ulOriginalBASEPRI;
+ 801158e:	69bb      	ldr	r3, [r7, #24]
+
+	uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+ 8011590:	62fb      	str	r3, [r7, #44]	; 0x2c
+	{
+		const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;
+ 8011592:	6b3b      	ldr	r3, [r7, #48]	; 0x30
+ 8011594:	6b9b      	ldr	r3, [r3, #56]	; 0x38
+ 8011596:	62bb      	str	r3, [r7, #40]	; 0x28
+
+		/* Cannot block in an ISR, so check there is data available. */
+		if( uxMessagesWaiting > ( UBaseType_t ) 0 )
+ 8011598:	6abb      	ldr	r3, [r7, #40]	; 0x28
+ 801159a:	2b00      	cmp	r3, #0
+ 801159c:	d02f      	beq.n	80115fe <xQueueReceiveFromISR+0xe6>
+		{
+			const int8_t cRxLock = pxQueue->cRxLock;
+ 801159e:	6b3b      	ldr	r3, [r7, #48]	; 0x30
+ 80115a0:	f893 3044 	ldrb.w	r3, [r3, #68]	; 0x44
+ 80115a4:	f887 3027 	strb.w	r3, [r7, #39]	; 0x27
+
+			traceQUEUE_RECEIVE_FROM_ISR( pxQueue );
+
+			prvCopyDataFromQueue( pxQueue, pvBuffer );
+ 80115a8:	68b9      	ldr	r1, [r7, #8]
+ 80115aa:	6b38      	ldr	r0, [r7, #48]	; 0x30
+ 80115ac:	f000 f915 	bl	80117da <prvCopyDataFromQueue>
+			pxQueue->uxMessagesWaiting = uxMessagesWaiting - ( UBaseType_t ) 1;
+ 80115b0:	6abb      	ldr	r3, [r7, #40]	; 0x28
+ 80115b2:	1e5a      	subs	r2, r3, #1
+ 80115b4:	6b3b      	ldr	r3, [r7, #48]	; 0x30
+ 80115b6:	639a      	str	r2, [r3, #56]	; 0x38
+
+			/* If the queue is locked the event list will not be modified.
+			Instead update the lock count so the task that unlocks the queue
+			will know that an ISR has removed data while the queue was
+			locked. */
+			if( cRxLock == queueUNLOCKED )
+ 80115b8:	f997 3027 	ldrsb.w	r3, [r7, #39]	; 0x27
+ 80115bc:	f1b3 3fff 	cmp.w	r3, #4294967295
+ 80115c0:	d112      	bne.n	80115e8 <xQueueReceiveFromISR+0xd0>
+			{
+				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
+ 80115c2:	6b3b      	ldr	r3, [r7, #48]	; 0x30
+ 80115c4:	691b      	ldr	r3, [r3, #16]
+ 80115c6:	2b00      	cmp	r3, #0
+ 80115c8:	d016      	beq.n	80115f8 <xQueueReceiveFromISR+0xe0>
+				{
+					if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
+ 80115ca:	6b3b      	ldr	r3, [r7, #48]	; 0x30
+ 80115cc:	3310      	adds	r3, #16
+ 80115ce:	4618      	mov	r0, r3
+ 80115d0:	f000 fea6 	bl	8012320 <xTaskRemoveFromEventList>
+ 80115d4:	4603      	mov	r3, r0
+ 80115d6:	2b00      	cmp	r3, #0
+ 80115d8:	d00e      	beq.n	80115f8 <xQueueReceiveFromISR+0xe0>
+					{
+						/* The task waiting has a higher priority than us so
+						force a context switch. */
+						if( pxHigherPriorityTaskWoken != NULL )
+ 80115da:	687b      	ldr	r3, [r7, #4]
+ 80115dc:	2b00      	cmp	r3, #0
+ 80115de:	d00b      	beq.n	80115f8 <xQueueReceiveFromISR+0xe0>
+						{
+							*pxHigherPriorityTaskWoken = pdTRUE;
+ 80115e0:	687b      	ldr	r3, [r7, #4]
+ 80115e2:	2201      	movs	r2, #1
+ 80115e4:	601a      	str	r2, [r3, #0]
+ 80115e6:	e007      	b.n	80115f8 <xQueueReceiveFromISR+0xe0>
+			}
+			else
+			{
+				/* Increment the lock count so the task that unlocks the queue
+				knows that data was removed while it was locked. */
+				pxQueue->cRxLock = ( int8_t ) ( cRxLock + 1 );
+ 80115e8:	f897 3027 	ldrb.w	r3, [r7, #39]	; 0x27
+ 80115ec:	3301      	adds	r3, #1
+ 80115ee:	b2db      	uxtb	r3, r3
+ 80115f0:	b25a      	sxtb	r2, r3
+ 80115f2:	6b3b      	ldr	r3, [r7, #48]	; 0x30
+ 80115f4:	f883 2044 	strb.w	r2, [r3, #68]	; 0x44
+			}
+
+			xReturn = pdPASS;
+ 80115f8:	2301      	movs	r3, #1
+ 80115fa:	637b      	str	r3, [r7, #52]	; 0x34
+ 80115fc:	e001      	b.n	8011602 <xQueueReceiveFromISR+0xea>
+		}
+		else
+		{
+			xReturn = pdFAIL;
+ 80115fe:	2300      	movs	r3, #0
+ 8011600:	637b      	str	r3, [r7, #52]	; 0x34
+ 8011602:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 8011604:	613b      	str	r3, [r7, #16]
+	__asm volatile
+ 8011606:	693b      	ldr	r3, [r7, #16]
+ 8011608:	f383 8811 	msr	BASEPRI, r3
+}
+ 801160c:	bf00      	nop
+			traceQUEUE_RECEIVE_FROM_ISR_FAILED( pxQueue );
+		}
+	}
+	portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+	return xReturn;
+ 801160e:	6b7b      	ldr	r3, [r7, #52]	; 0x34
+}
+ 8011610:	4618      	mov	r0, r3
+ 8011612:	3738      	adds	r7, #56	; 0x38
+ 8011614:	46bd      	mov	sp, r7
+ 8011616:	bd80      	pop	{r7, pc}
+
+08011618 <uxQueueMessagesWaiting>:
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+UBaseType_t uxQueueMessagesWaiting( const QueueHandle_t xQueue )
+{
+ 8011618:	b580      	push	{r7, lr}
+ 801161a:	b084      	sub	sp, #16
+ 801161c:	af00      	add	r7, sp, #0
+ 801161e:	6078      	str	r0, [r7, #4]
+UBaseType_t uxReturn;
+
+	configASSERT( xQueue );
+ 8011620:	687b      	ldr	r3, [r7, #4]
+ 8011622:	2b00      	cmp	r3, #0
+ 8011624:	d10a      	bne.n	801163c <uxQueueMessagesWaiting+0x24>
+	__asm volatile
+ 8011626:	f04f 0350 	mov.w	r3, #80	; 0x50
+ 801162a:	f383 8811 	msr	BASEPRI, r3
+ 801162e:	f3bf 8f6f 	isb	sy
+ 8011632:	f3bf 8f4f 	dsb	sy
+ 8011636:	60bb      	str	r3, [r7, #8]
+}
+ 8011638:	bf00      	nop
+ 801163a:	e7fe      	b.n	801163a <uxQueueMessagesWaiting+0x22>
+
+	taskENTER_CRITICAL();
+ 801163c:	f001 fee2 	bl	8013404 <vPortEnterCritical>
+	{
+		uxReturn = ( ( Queue_t * ) xQueue )->uxMessagesWaiting;
+ 8011640:	687b      	ldr	r3, [r7, #4]
+ 8011642:	6b9b      	ldr	r3, [r3, #56]	; 0x38
+ 8011644:	60fb      	str	r3, [r7, #12]
+	}
+	taskEXIT_CRITICAL();
+ 8011646:	f001 ff0d 	bl	8013464 <vPortExitCritical>
+
+	return uxReturn;
+ 801164a:	68fb      	ldr	r3, [r7, #12]
+} /*lint !e818 Pointer cannot be declared const as xQueue is a typedef not pointer. */
+ 801164c:	4618      	mov	r0, r3
+ 801164e:	3710      	adds	r7, #16
+ 8011650:	46bd      	mov	sp, r7
+ 8011652:	bd80      	pop	{r7, pc}
+
+08011654 <uxQueueMessagesWaitingFromISR>:
+	return uxReturn;
+} /*lint !e818 Pointer cannot be declared const as xQueue is a typedef not pointer. */
+/*-----------------------------------------------------------*/
+
+UBaseType_t uxQueueMessagesWaitingFromISR( const QueueHandle_t xQueue )
+{
+ 8011654:	b480      	push	{r7}
+ 8011656:	b087      	sub	sp, #28
+ 8011658:	af00      	add	r7, sp, #0
+ 801165a:	6078      	str	r0, [r7, #4]
+UBaseType_t uxReturn;
+Queue_t * const pxQueue = xQueue;
+ 801165c:	687b      	ldr	r3, [r7, #4]
+ 801165e:	617b      	str	r3, [r7, #20]
+
+	configASSERT( pxQueue );
+ 8011660:	697b      	ldr	r3, [r7, #20]
+ 8011662:	2b00      	cmp	r3, #0
+ 8011664:	d10a      	bne.n	801167c <uxQueueMessagesWaitingFromISR+0x28>
+	__asm volatile
+ 8011666:	f04f 0350 	mov.w	r3, #80	; 0x50
+ 801166a:	f383 8811 	msr	BASEPRI, r3
+ 801166e:	f3bf 8f6f 	isb	sy
+ 8011672:	f3bf 8f4f 	dsb	sy
+ 8011676:	60fb      	str	r3, [r7, #12]
+}
+ 8011678:	bf00      	nop
+ 801167a:	e7fe      	b.n	801167a <uxQueueMessagesWaitingFromISR+0x26>
+	uxReturn = pxQueue->uxMessagesWaiting;
+ 801167c:	697b      	ldr	r3, [r7, #20]
+ 801167e:	6b9b      	ldr	r3, [r3, #56]	; 0x38
+ 8011680:	613b      	str	r3, [r7, #16]
+
+	return uxReturn;
+ 8011682:	693b      	ldr	r3, [r7, #16]
+} /*lint !e818 Pointer cannot be declared const as xQueue is a typedef not pointer. */
+ 8011684:	4618      	mov	r0, r3
+ 8011686:	371c      	adds	r7, #28
+ 8011688:	46bd      	mov	sp, r7
+ 801168a:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 801168e:	4770      	bx	lr
+
+08011690 <vQueueDelete>:
+/*-----------------------------------------------------------*/
+
+void vQueueDelete( QueueHandle_t xQueue )
+{
+ 8011690:	b580      	push	{r7, lr}
+ 8011692:	b084      	sub	sp, #16
+ 8011694:	af00      	add	r7, sp, #0
+ 8011696:	6078      	str	r0, [r7, #4]
+Queue_t * const pxQueue = xQueue;
+ 8011698:	687b      	ldr	r3, [r7, #4]
+ 801169a:	60fb      	str	r3, [r7, #12]
+
+	configASSERT( pxQueue );
+ 801169c:	68fb      	ldr	r3, [r7, #12]
+ 801169e:	2b00      	cmp	r3, #0
+ 80116a0:	d10a      	bne.n	80116b8 <vQueueDelete+0x28>
+	__asm volatile
+ 80116a2:	f04f 0350 	mov.w	r3, #80	; 0x50
+ 80116a6:	f383 8811 	msr	BASEPRI, r3
+ 80116aa:	f3bf 8f6f 	isb	sy
+ 80116ae:	f3bf 8f4f 	dsb	sy
+ 80116b2:	60bb      	str	r3, [r7, #8]
+}
+ 80116b4:	bf00      	nop
+ 80116b6:	e7fe      	b.n	80116b6 <vQueueDelete+0x26>
+	traceQUEUE_DELETE( pxQueue );
+
+	#if ( configQUEUE_REGISTRY_SIZE > 0 )
+	{
+		vQueueUnregisterQueue( pxQueue );
+ 80116b8:	68f8      	ldr	r0, [r7, #12]
+ 80116ba:	f000 f95f 	bl	801197c <vQueueUnregisterQueue>
+	}
+	#elif( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
+	{
+		/* The queue could have been allocated statically or dynamically, so
+		check before attempting to free the memory. */
+		if( pxQueue->ucStaticallyAllocated == ( uint8_t ) pdFALSE )
+ 80116be:	68fb      	ldr	r3, [r7, #12]
+ 80116c0:	f893 3046 	ldrb.w	r3, [r3, #70]	; 0x46
+ 80116c4:	2b00      	cmp	r3, #0
+ 80116c6:	d102      	bne.n	80116ce <vQueueDelete+0x3e>
+		{
+			vPortFree( pxQueue );
+ 80116c8:	68f8      	ldr	r0, [r7, #12]
+ 80116ca:	f002 f889 	bl	80137e0 <vPortFree>
+		/* The queue must have been statically allocated, so is not going to be
+		deleted.  Avoid compiler warnings about the unused parameter. */
+		( void ) pxQueue;
+	}
+	#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+}
+ 80116ce:	bf00      	nop
+ 80116d0:	3710      	adds	r7, #16
+ 80116d2:	46bd      	mov	sp, r7
+ 80116d4:	bd80      	pop	{r7, pc}
+
+080116d6 <prvGetDisinheritPriorityAfterTimeout>:
+/*-----------------------------------------------------------*/
+
+#if( configUSE_MUTEXES == 1 )
+
+	static UBaseType_t prvGetDisinheritPriorityAfterTimeout( const Queue_t * const pxQueue )
+	{
+ 80116d6:	b480      	push	{r7}
+ 80116d8:	b085      	sub	sp, #20
+ 80116da:	af00      	add	r7, sp, #0
+ 80116dc:	6078      	str	r0, [r7, #4]
+		priority, but the waiting task times out, then the holder should
+		disinherit the priority - but only down to the highest priority of any
+		other tasks that are waiting for the same mutex.  For this purpose,
+		return the priority of the highest priority task that is waiting for the
+		mutex. */
+		if( listCURRENT_LIST_LENGTH( &( pxQueue->xTasksWaitingToReceive ) ) > 0U )
+ 80116de:	687b      	ldr	r3, [r7, #4]
+ 80116e0:	6a5b      	ldr	r3, [r3, #36]	; 0x24
+ 80116e2:	2b00      	cmp	r3, #0
+ 80116e4:	d006      	beq.n	80116f4 <prvGetDisinheritPriorityAfterTimeout+0x1e>
+		{
+			uxHighestPriorityOfWaitingTasks = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) listGET_ITEM_VALUE_OF_HEAD_ENTRY( &( pxQueue->xTasksWaitingToReceive ) );
+ 80116e6:	687b      	ldr	r3, [r7, #4]
+ 80116e8:	6b1b      	ldr	r3, [r3, #48]	; 0x30
+ 80116ea:	681b      	ldr	r3, [r3, #0]
+ 80116ec:	f1c3 0307 	rsb	r3, r3, #7
+ 80116f0:	60fb      	str	r3, [r7, #12]
+ 80116f2:	e001      	b.n	80116f8 <prvGetDisinheritPriorityAfterTimeout+0x22>
+		}
+		else
+		{
+			uxHighestPriorityOfWaitingTasks = tskIDLE_PRIORITY;
+ 80116f4:	2300      	movs	r3, #0
+ 80116f6:	60fb      	str	r3, [r7, #12]
+		}
+
+		return uxHighestPriorityOfWaitingTasks;
+ 80116f8:	68fb      	ldr	r3, [r7, #12]
+	}
+ 80116fa:	4618      	mov	r0, r3
+ 80116fc:	3714      	adds	r7, #20
+ 80116fe:	46bd      	mov	sp, r7
+ 8011700:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8011704:	4770      	bx	lr
+
+08011706 <prvCopyDataToQueue>:
+
+#endif /* configUSE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+static BaseType_t prvCopyDataToQueue( Queue_t * const pxQueue, const void *pvItemToQueue, const BaseType_t xPosition )
+{
+ 8011706:	b580      	push	{r7, lr}
+ 8011708:	b086      	sub	sp, #24
+ 801170a:	af00      	add	r7, sp, #0
+ 801170c:	60f8      	str	r0, [r7, #12]
+ 801170e:	60b9      	str	r1, [r7, #8]
+ 8011710:	607a      	str	r2, [r7, #4]
+BaseType_t xReturn = pdFALSE;
+ 8011712:	2300      	movs	r3, #0
+ 8011714:	617b      	str	r3, [r7, #20]
+UBaseType_t uxMessagesWaiting;
+
+	/* This function is called from a critical section. */
+
+	uxMessagesWaiting = pxQueue->uxMessagesWaiting;
+ 8011716:	68fb      	ldr	r3, [r7, #12]
+ 8011718:	6b9b      	ldr	r3, [r3, #56]	; 0x38
+ 801171a:	613b      	str	r3, [r7, #16]
+
+	if( pxQueue->uxItemSize == ( UBaseType_t ) 0 )
+ 801171c:	68fb      	ldr	r3, [r7, #12]
+ 801171e:	6c1b      	ldr	r3, [r3, #64]	; 0x40
+ 8011720:	2b00      	cmp	r3, #0
+ 8011722:	d10d      	bne.n	8011740 <prvCopyDataToQueue+0x3a>
+	{
+		#if ( configUSE_MUTEXES == 1 )
+		{
+			if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )
+ 8011724:	68fb      	ldr	r3, [r7, #12]
+ 8011726:	681b      	ldr	r3, [r3, #0]
+ 8011728:	2b00      	cmp	r3, #0
+ 801172a:	d14d      	bne.n	80117c8 <prvCopyDataToQueue+0xc2>
+			{
+				/* The mutex is no longer being held. */
+				xReturn = xTaskPriorityDisinherit( pxQueue->u.xSemaphore.xMutexHolder );
+ 801172c:	68fb      	ldr	r3, [r7, #12]
+ 801172e:	689b      	ldr	r3, [r3, #8]
+ 8011730:	4618      	mov	r0, r3
+ 8011732:	f001 f87d 	bl	8012830 <xTaskPriorityDisinherit>
+ 8011736:	6178      	str	r0, [r7, #20]
+				pxQueue->u.xSemaphore.xMutexHolder = NULL;
+ 8011738:	68fb      	ldr	r3, [r7, #12]
+ 801173a:	2200      	movs	r2, #0
+ 801173c:	609a      	str	r2, [r3, #8]
+ 801173e:	e043      	b.n	80117c8 <prvCopyDataToQueue+0xc2>
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		#endif /* configUSE_MUTEXES */
+	}
+	else if( xPosition == queueSEND_TO_BACK )
+ 8011740:	687b      	ldr	r3, [r7, #4]
+ 8011742:	2b00      	cmp	r3, #0
+ 8011744:	d119      	bne.n	801177a <prvCopyDataToQueue+0x74>
+	{
+		( void ) memcpy( ( void * ) pxQueue->pcWriteTo, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports, plus previous logic ensures a null pointer can only be passed to memcpy() if the copy size is 0.  Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */
+ 8011746:	68fb      	ldr	r3, [r7, #12]
+ 8011748:	6858      	ldr	r0, [r3, #4]
+ 801174a:	68fb      	ldr	r3, [r7, #12]
+ 801174c:	6c1b      	ldr	r3, [r3, #64]	; 0x40
+ 801174e:	461a      	mov	r2, r3
+ 8011750:	68b9      	ldr	r1, [r7, #8]
+ 8011752:	f010 fb48 	bl	8021de6 <memcpy>
+		pxQueue->pcWriteTo += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */
+ 8011756:	68fb      	ldr	r3, [r7, #12]
+ 8011758:	685a      	ldr	r2, [r3, #4]
+ 801175a:	68fb      	ldr	r3, [r7, #12]
+ 801175c:	6c1b      	ldr	r3, [r3, #64]	; 0x40
+ 801175e:	441a      	add	r2, r3
+ 8011760:	68fb      	ldr	r3, [r7, #12]
+ 8011762:	605a      	str	r2, [r3, #4]
+		if( pxQueue->pcWriteTo >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */
+ 8011764:	68fb      	ldr	r3, [r7, #12]
+ 8011766:	685a      	ldr	r2, [r3, #4]
+ 8011768:	68fb      	ldr	r3, [r7, #12]
+ 801176a:	689b      	ldr	r3, [r3, #8]
+ 801176c:	429a      	cmp	r2, r3
+ 801176e:	d32b      	bcc.n	80117c8 <prvCopyDataToQueue+0xc2>
+		{
+			pxQueue->pcWriteTo = pxQueue->pcHead;
+ 8011770:	68fb      	ldr	r3, [r7, #12]
+ 8011772:	681a      	ldr	r2, [r3, #0]
+ 8011774:	68fb      	ldr	r3, [r7, #12]
+ 8011776:	605a      	str	r2, [r3, #4]
+ 8011778:	e026      	b.n	80117c8 <prvCopyDataToQueue+0xc2>
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	else
+	{
+		( void ) memcpy( ( void * ) pxQueue->u.xQueue.pcReadFrom, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e9087 !e418 MISRA exception as the casts are only redundant for some ports.  Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes.  Assert checks null pointer only used when length is 0. */
+ 801177a:	68fb      	ldr	r3, [r7, #12]
+ 801177c:	68d8      	ldr	r0, [r3, #12]
+ 801177e:	68fb      	ldr	r3, [r7, #12]
+ 8011780:	6c1b      	ldr	r3, [r3, #64]	; 0x40
+ 8011782:	461a      	mov	r2, r3
+ 8011784:	68b9      	ldr	r1, [r7, #8]
+ 8011786:	f010 fb2e 	bl	8021de6 <memcpy>
+		pxQueue->u.xQueue.pcReadFrom -= pxQueue->uxItemSize;
+ 801178a:	68fb      	ldr	r3, [r7, #12]
+ 801178c:	68da      	ldr	r2, [r3, #12]
+ 801178e:	68fb      	ldr	r3, [r7, #12]
+ 8011790:	6c1b      	ldr	r3, [r3, #64]	; 0x40
+ 8011792:	425b      	negs	r3, r3
+ 8011794:	441a      	add	r2, r3
+ 8011796:	68fb      	ldr	r3, [r7, #12]
+ 8011798:	60da      	str	r2, [r3, #12]
+		if( pxQueue->u.xQueue.pcReadFrom < pxQueue->pcHead ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */
+ 801179a:	68fb      	ldr	r3, [r7, #12]
+ 801179c:	68da      	ldr	r2, [r3, #12]
+ 801179e:	68fb      	ldr	r3, [r7, #12]
+ 80117a0:	681b      	ldr	r3, [r3, #0]
+ 80117a2:	429a      	cmp	r2, r3
+ 80117a4:	d207      	bcs.n	80117b6 <prvCopyDataToQueue+0xb0>
+		{
+			pxQueue->u.xQueue.pcReadFrom = ( pxQueue->u.xQueue.pcTail - pxQueue->uxItemSize );
+ 80117a6:	68fb      	ldr	r3, [r7, #12]
+ 80117a8:	689a      	ldr	r2, [r3, #8]
+ 80117aa:	68fb      	ldr	r3, [r7, #12]
+ 80117ac:	6c1b      	ldr	r3, [r3, #64]	; 0x40
+ 80117ae:	425b      	negs	r3, r3
+ 80117b0:	441a      	add	r2, r3
+ 80117b2:	68fb      	ldr	r3, [r7, #12]
+ 80117b4:	60da      	str	r2, [r3, #12]
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		if( xPosition == queueOVERWRITE )
+ 80117b6:	687b      	ldr	r3, [r7, #4]
+ 80117b8:	2b02      	cmp	r3, #2
+ 80117ba:	d105      	bne.n	80117c8 <prvCopyDataToQueue+0xc2>
+		{
+			if( uxMessagesWaiting > ( UBaseType_t ) 0 )
+ 80117bc:	693b      	ldr	r3, [r7, #16]
+ 80117be:	2b00      	cmp	r3, #0
+ 80117c0:	d002      	beq.n	80117c8 <prvCopyDataToQueue+0xc2>
+			{
+				/* An item is not being added but overwritten, so subtract
+				one from the recorded number of items in the queue so when
+				one is added again below the number of recorded items remains
+				correct. */
+				--uxMessagesWaiting;
+ 80117c2:	693b      	ldr	r3, [r7, #16]
+ 80117c4:	3b01      	subs	r3, #1
+ 80117c6:	613b      	str	r3, [r7, #16]
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+
+	pxQueue->uxMessagesWaiting = uxMessagesWaiting + ( UBaseType_t ) 1;
+ 80117c8:	693b      	ldr	r3, [r7, #16]
+ 80117ca:	1c5a      	adds	r2, r3, #1
+ 80117cc:	68fb      	ldr	r3, [r7, #12]
+ 80117ce:	639a      	str	r2, [r3, #56]	; 0x38
+
+	return xReturn;
+ 80117d0:	697b      	ldr	r3, [r7, #20]
+}
+ 80117d2:	4618      	mov	r0, r3
+ 80117d4:	3718      	adds	r7, #24
+ 80117d6:	46bd      	mov	sp, r7
+ 80117d8:	bd80      	pop	{r7, pc}
+
+080117da <prvCopyDataFromQueue>:
+/*-----------------------------------------------------------*/
+
+static void prvCopyDataFromQueue( Queue_t * const pxQueue, void * const pvBuffer )
+{
+ 80117da:	b580      	push	{r7, lr}
+ 80117dc:	b082      	sub	sp, #8
+ 80117de:	af00      	add	r7, sp, #0
+ 80117e0:	6078      	str	r0, [r7, #4]
+ 80117e2:	6039      	str	r1, [r7, #0]
+	if( pxQueue->uxItemSize != ( UBaseType_t ) 0 )
+ 80117e4:	687b      	ldr	r3, [r7, #4]
+ 80117e6:	6c1b      	ldr	r3, [r3, #64]	; 0x40
+ 80117e8:	2b00      	cmp	r3, #0
+ 80117ea:	d018      	beq.n	801181e <prvCopyDataFromQueue+0x44>
+	{
+		pxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */
+ 80117ec:	687b      	ldr	r3, [r7, #4]
+ 80117ee:	68da      	ldr	r2, [r3, #12]
+ 80117f0:	687b      	ldr	r3, [r7, #4]
+ 80117f2:	6c1b      	ldr	r3, [r3, #64]	; 0x40
+ 80117f4:	441a      	add	r2, r3
+ 80117f6:	687b      	ldr	r3, [r7, #4]
+ 80117f8:	60da      	str	r2, [r3, #12]
+		if( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as use of the relational operator is the cleanest solutions. */
+ 80117fa:	687b      	ldr	r3, [r7, #4]
+ 80117fc:	68da      	ldr	r2, [r3, #12]
+ 80117fe:	687b      	ldr	r3, [r7, #4]
+ 8011800:	689b      	ldr	r3, [r3, #8]
+ 8011802:	429a      	cmp	r2, r3
+ 8011804:	d303      	bcc.n	801180e <prvCopyDataFromQueue+0x34>
+		{
+			pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead;
+ 8011806:	687b      	ldr	r3, [r7, #4]
+ 8011808:	681a      	ldr	r2, [r3, #0]
+ 801180a:	687b      	ldr	r3, [r7, #4]
+ 801180c:	60da      	str	r2, [r3, #12]
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+		( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.xQueue.pcReadFrom, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports.  Also previous logic ensures a null pointer can only be passed to memcpy() when the count is 0.  Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */
+ 801180e:	687b      	ldr	r3, [r7, #4]
+ 8011810:	68d9      	ldr	r1, [r3, #12]
+ 8011812:	687b      	ldr	r3, [r7, #4]
+ 8011814:	6c1b      	ldr	r3, [r3, #64]	; 0x40
+ 8011816:	461a      	mov	r2, r3
+ 8011818:	6838      	ldr	r0, [r7, #0]
+ 801181a:	f010 fae4 	bl	8021de6 <memcpy>
+	}
+}
+ 801181e:	bf00      	nop
+ 8011820:	3708      	adds	r7, #8
+ 8011822:	46bd      	mov	sp, r7
+ 8011824:	bd80      	pop	{r7, pc}
+
+08011826 <prvUnlockQueue>:
+/*-----------------------------------------------------------*/
+
+static void prvUnlockQueue( Queue_t * const pxQueue )
+{
+ 8011826:	b580      	push	{r7, lr}
+ 8011828:	b084      	sub	sp, #16
+ 801182a:	af00      	add	r7, sp, #0
+ 801182c:	6078      	str	r0, [r7, #4]
+
+	/* The lock counts contains the number of extra data items placed or
+	removed from the queue while the queue was locked.  When a queue is
+	locked items can be added or removed, but the event lists cannot be
+	updated. */
+	taskENTER_CRITICAL();
+ 801182e:	f001 fde9 	bl	8013404 <vPortEnterCritical>
+	{
+		int8_t cTxLock = pxQueue->cTxLock;
+ 8011832:	687b      	ldr	r3, [r7, #4]
+ 8011834:	f893 3045 	ldrb.w	r3, [r3, #69]	; 0x45
+ 8011838:	73fb      	strb	r3, [r7, #15]
+
+		/* See if data was added to the queue while it was locked. */
+		while( cTxLock > queueLOCKED_UNMODIFIED )
+ 801183a:	e011      	b.n	8011860 <prvUnlockQueue+0x3a>
+			}
+			#else /* configUSE_QUEUE_SETS */
+			{
+				/* Tasks that are removed from the event list will get added to
+				the pending ready list as the scheduler is still suspended. */
+				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+ 801183c:	687b      	ldr	r3, [r7, #4]
+ 801183e:	6a5b      	ldr	r3, [r3, #36]	; 0x24
+ 8011840:	2b00      	cmp	r3, #0
+ 8011842:	d012      	beq.n	801186a <prvUnlockQueue+0x44>
+				{
+					if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+ 8011844:	687b      	ldr	r3, [r7, #4]
+ 8011846:	3324      	adds	r3, #36	; 0x24
+ 8011848:	4618      	mov	r0, r3
+ 801184a:	f000 fd69 	bl	8012320 <xTaskRemoveFromEventList>
+ 801184e:	4603      	mov	r3, r0
+ 8011850:	2b00      	cmp	r3, #0
+ 8011852:	d001      	beq.n	8011858 <prvUnlockQueue+0x32>
+					{
+						/* The task waiting has a higher priority so record that
+						a context switch is required. */
+						vTaskMissedYield();
+ 8011854:	f000 fe3e 	bl	80124d4 <vTaskMissedYield>
+					break;
+				}
+			}
+			#endif /* configUSE_QUEUE_SETS */
+
+			--cTxLock;
+ 8011858:	7bfb      	ldrb	r3, [r7, #15]
+ 801185a:	3b01      	subs	r3, #1
+ 801185c:	b2db      	uxtb	r3, r3
+ 801185e:	73fb      	strb	r3, [r7, #15]
+		while( cTxLock > queueLOCKED_UNMODIFIED )
+ 8011860:	f997 300f 	ldrsb.w	r3, [r7, #15]
+ 8011864:	2b00      	cmp	r3, #0
+ 8011866:	dce9      	bgt.n	801183c <prvUnlockQueue+0x16>
+ 8011868:	e000      	b.n	801186c <prvUnlockQueue+0x46>
+					break;
+ 801186a:	bf00      	nop
+		}
+
+		pxQueue->cTxLock = queueUNLOCKED;
+ 801186c:	687b      	ldr	r3, [r7, #4]
+ 801186e:	22ff      	movs	r2, #255	; 0xff
+ 8011870:	f883 2045 	strb.w	r2, [r3, #69]	; 0x45
+	}
+	taskEXIT_CRITICAL();
+ 8011874:	f001 fdf6 	bl	8013464 <vPortExitCritical>
+
+	/* Do the same for the Rx lock. */
+	taskENTER_CRITICAL();
+ 8011878:	f001 fdc4 	bl	8013404 <vPortEnterCritical>
+	{
+		int8_t cRxLock = pxQueue->cRxLock;
+ 801187c:	687b      	ldr	r3, [r7, #4]
+ 801187e:	f893 3044 	ldrb.w	r3, [r3, #68]	; 0x44
+ 8011882:	73bb      	strb	r3, [r7, #14]
+
+		while( cRxLock > queueLOCKED_UNMODIFIED )
+ 8011884:	e011      	b.n	80118aa <prvUnlockQueue+0x84>
+		{
+			if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
+ 8011886:	687b      	ldr	r3, [r7, #4]
+ 8011888:	691b      	ldr	r3, [r3, #16]
+ 801188a:	2b00      	cmp	r3, #0
+ 801188c:	d012      	beq.n	80118b4 <prvUnlockQueue+0x8e>
+			{
+				if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
+ 801188e:	687b      	ldr	r3, [r7, #4]
+ 8011890:	3310      	adds	r3, #16
+ 8011892:	4618      	mov	r0, r3
+ 8011894:	f000 fd44 	bl	8012320 <xTaskRemoveFromEventList>
+ 8011898:	4603      	mov	r3, r0
+ 801189a:	2b00      	cmp	r3, #0
+ 801189c:	d001      	beq.n	80118a2 <prvUnlockQueue+0x7c>
+				{
+					vTaskMissedYield();
+ 801189e:	f000 fe19 	bl	80124d4 <vTaskMissedYield>
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+
+				--cRxLock;
+ 80118a2:	7bbb      	ldrb	r3, [r7, #14]
+ 80118a4:	3b01      	subs	r3, #1
+ 80118a6:	b2db      	uxtb	r3, r3
+ 80118a8:	73bb      	strb	r3, [r7, #14]
+		while( cRxLock > queueLOCKED_UNMODIFIED )
+ 80118aa:	f997 300e 	ldrsb.w	r3, [r7, #14]
+ 80118ae:	2b00      	cmp	r3, #0
+ 80118b0:	dce9      	bgt.n	8011886 <prvUnlockQueue+0x60>
+ 80118b2:	e000      	b.n	80118b6 <prvUnlockQueue+0x90>
+			}
+			else
+			{
+				break;
+ 80118b4:	bf00      	nop
+			}
+		}
+
+		pxQueue->cRxLock = queueUNLOCKED;
+ 80118b6:	687b      	ldr	r3, [r7, #4]
+ 80118b8:	22ff      	movs	r2, #255	; 0xff
+ 80118ba:	f883 2044 	strb.w	r2, [r3, #68]	; 0x44
+	}
+	taskEXIT_CRITICAL();
+ 80118be:	f001 fdd1 	bl	8013464 <vPortExitCritical>
+}
+ 80118c2:	bf00      	nop
+ 80118c4:	3710      	adds	r7, #16
+ 80118c6:	46bd      	mov	sp, r7
+ 80118c8:	bd80      	pop	{r7, pc}
+
+080118ca <prvIsQueueEmpty>:
+/*-----------------------------------------------------------*/
+
+static BaseType_t prvIsQueueEmpty( const Queue_t *pxQueue )
+{
+ 80118ca:	b580      	push	{r7, lr}
+ 80118cc:	b084      	sub	sp, #16
+ 80118ce:	af00      	add	r7, sp, #0
+ 80118d0:	6078      	str	r0, [r7, #4]
+BaseType_t xReturn;
+
+	taskENTER_CRITICAL();
+ 80118d2:	f001 fd97 	bl	8013404 <vPortEnterCritical>
+	{
+		if( pxQueue->uxMessagesWaiting == ( UBaseType_t )  0 )
+ 80118d6:	687b      	ldr	r3, [r7, #4]
+ 80118d8:	6b9b      	ldr	r3, [r3, #56]	; 0x38
+ 80118da:	2b00      	cmp	r3, #0
+ 80118dc:	d102      	bne.n	80118e4 <prvIsQueueEmpty+0x1a>
+		{
+			xReturn = pdTRUE;
+ 80118de:	2301      	movs	r3, #1
+ 80118e0:	60fb      	str	r3, [r7, #12]
+ 80118e2:	e001      	b.n	80118e8 <prvIsQueueEmpty+0x1e>
+		}
+		else
+		{
+			xReturn = pdFALSE;
+ 80118e4:	2300      	movs	r3, #0
+ 80118e6:	60fb      	str	r3, [r7, #12]
+		}
+	}
+	taskEXIT_CRITICAL();
+ 80118e8:	f001 fdbc 	bl	8013464 <vPortExitCritical>
+
+	return xReturn;
+ 80118ec:	68fb      	ldr	r3, [r7, #12]
+}
+ 80118ee:	4618      	mov	r0, r3
+ 80118f0:	3710      	adds	r7, #16
+ 80118f2:	46bd      	mov	sp, r7
+ 80118f4:	bd80      	pop	{r7, pc}
+
+080118f6 <prvIsQueueFull>:
+	return xReturn;
+} /*lint !e818 xQueue could not be pointer to const because it is a typedef. */
+/*-----------------------------------------------------------*/
+
+static BaseType_t prvIsQueueFull( const Queue_t *pxQueue )
+{
+ 80118f6:	b580      	push	{r7, lr}
+ 80118f8:	b084      	sub	sp, #16
+ 80118fa:	af00      	add	r7, sp, #0
+ 80118fc:	6078      	str	r0, [r7, #4]
+BaseType_t xReturn;
+
+	taskENTER_CRITICAL();
+ 80118fe:	f001 fd81 	bl	8013404 <vPortEnterCritical>
+	{
+		if( pxQueue->uxMessagesWaiting == pxQueue->uxLength )
+ 8011902:	687b      	ldr	r3, [r7, #4]
+ 8011904:	6b9a      	ldr	r2, [r3, #56]	; 0x38
+ 8011906:	687b      	ldr	r3, [r7, #4]
+ 8011908:	6bdb      	ldr	r3, [r3, #60]	; 0x3c
+ 801190a:	429a      	cmp	r2, r3
+ 801190c:	d102      	bne.n	8011914 <prvIsQueueFull+0x1e>
+		{
+			xReturn = pdTRUE;
+ 801190e:	2301      	movs	r3, #1
+ 8011910:	60fb      	str	r3, [r7, #12]
+ 8011912:	e001      	b.n	8011918 <prvIsQueueFull+0x22>
+		}
+		else
+		{
+			xReturn = pdFALSE;
+ 8011914:	2300      	movs	r3, #0
+ 8011916:	60fb      	str	r3, [r7, #12]
+		}
+	}
+	taskEXIT_CRITICAL();
+ 8011918:	f001 fda4 	bl	8013464 <vPortExitCritical>
+
+	return xReturn;
+ 801191c:	68fb      	ldr	r3, [r7, #12]
+}
+ 801191e:	4618      	mov	r0, r3
+ 8011920:	3710      	adds	r7, #16
+ 8011922:	46bd      	mov	sp, r7
+ 8011924:	bd80      	pop	{r7, pc}
+	...
+
+08011928 <vQueueAddToRegistry>:
+/*-----------------------------------------------------------*/
+
+#if ( configQUEUE_REGISTRY_SIZE > 0 )
+
+	void vQueueAddToRegistry( QueueHandle_t xQueue, const char *pcQueueName ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+	{
+ 8011928:	b480      	push	{r7}
+ 801192a:	b085      	sub	sp, #20
+ 801192c:	af00      	add	r7, sp, #0
+ 801192e:	6078      	str	r0, [r7, #4]
+ 8011930:	6039      	str	r1, [r7, #0]
+	UBaseType_t ux;
+
+		/* See if there is an empty space in the registry.  A NULL name denotes
+		a free slot. */
+		for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ )
+ 8011932:	2300      	movs	r3, #0
+ 8011934:	60fb      	str	r3, [r7, #12]
+ 8011936:	e014      	b.n	8011962 <vQueueAddToRegistry+0x3a>
+		{
+			if( xQueueRegistry[ ux ].pcQueueName == NULL )
+ 8011938:	4a0f      	ldr	r2, [pc, #60]	; (8011978 <vQueueAddToRegistry+0x50>)
+ 801193a:	68fb      	ldr	r3, [r7, #12]
+ 801193c:	f852 3033 	ldr.w	r3, [r2, r3, lsl #3]
+ 8011940:	2b00      	cmp	r3, #0
+ 8011942:	d10b      	bne.n	801195c <vQueueAddToRegistry+0x34>
+			{
+				/* Store the information on this queue. */
+				xQueueRegistry[ ux ].pcQueueName = pcQueueName;
+ 8011944:	490c      	ldr	r1, [pc, #48]	; (8011978 <vQueueAddToRegistry+0x50>)
+ 8011946:	68fb      	ldr	r3, [r7, #12]
+ 8011948:	683a      	ldr	r2, [r7, #0]
+ 801194a:	f841 2033 	str.w	r2, [r1, r3, lsl #3]
+				xQueueRegistry[ ux ].xHandle = xQueue;
+ 801194e:	4a0a      	ldr	r2, [pc, #40]	; (8011978 <vQueueAddToRegistry+0x50>)
+ 8011950:	68fb      	ldr	r3, [r7, #12]
+ 8011952:	00db      	lsls	r3, r3, #3
+ 8011954:	4413      	add	r3, r2
+ 8011956:	687a      	ldr	r2, [r7, #4]
+ 8011958:	605a      	str	r2, [r3, #4]
+
+				traceQUEUE_REGISTRY_ADD( xQueue, pcQueueName );
+				break;
+ 801195a:	e006      	b.n	801196a <vQueueAddToRegistry+0x42>
+		for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ )
+ 801195c:	68fb      	ldr	r3, [r7, #12]
+ 801195e:	3301      	adds	r3, #1
+ 8011960:	60fb      	str	r3, [r7, #12]
+ 8011962:	68fb      	ldr	r3, [r7, #12]
+ 8011964:	2b07      	cmp	r3, #7
+ 8011966:	d9e7      	bls.n	8011938 <vQueueAddToRegistry+0x10>
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+	}
+ 8011968:	bf00      	nop
+ 801196a:	bf00      	nop
+ 801196c:	3714      	adds	r7, #20
+ 801196e:	46bd      	mov	sp, r7
+ 8011970:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8011974:	4770      	bx	lr
+ 8011976:	bf00      	nop
+ 8011978:	2400bee0 	.word	0x2400bee0
+
+0801197c <vQueueUnregisterQueue>:
+/*-----------------------------------------------------------*/
+
+#if ( configQUEUE_REGISTRY_SIZE > 0 )
+
+	void vQueueUnregisterQueue( QueueHandle_t xQueue )
+	{
+ 801197c:	b480      	push	{r7}
+ 801197e:	b085      	sub	sp, #20
+ 8011980:	af00      	add	r7, sp, #0
+ 8011982:	6078      	str	r0, [r7, #4]
+	UBaseType_t ux;
+
+		/* See if the handle of the queue being unregistered in actually in the
+		registry. */
+		for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ )
+ 8011984:	2300      	movs	r3, #0
+ 8011986:	60fb      	str	r3, [r7, #12]
+ 8011988:	e016      	b.n	80119b8 <vQueueUnregisterQueue+0x3c>
+		{
+			if( xQueueRegistry[ ux ].xHandle == xQueue )
+ 801198a:	4a10      	ldr	r2, [pc, #64]	; (80119cc <vQueueUnregisterQueue+0x50>)
+ 801198c:	68fb      	ldr	r3, [r7, #12]
+ 801198e:	00db      	lsls	r3, r3, #3
+ 8011990:	4413      	add	r3, r2
+ 8011992:	685b      	ldr	r3, [r3, #4]
+ 8011994:	687a      	ldr	r2, [r7, #4]
+ 8011996:	429a      	cmp	r2, r3
+ 8011998:	d10b      	bne.n	80119b2 <vQueueUnregisterQueue+0x36>
+			{
+				/* Set the name to NULL to show that this slot if free again. */
+				xQueueRegistry[ ux ].pcQueueName = NULL;
+ 801199a:	4a0c      	ldr	r2, [pc, #48]	; (80119cc <vQueueUnregisterQueue+0x50>)
+ 801199c:	68fb      	ldr	r3, [r7, #12]
+ 801199e:	2100      	movs	r1, #0
+ 80119a0:	f842 1033 	str.w	r1, [r2, r3, lsl #3]
+
+				/* Set the handle to NULL to ensure the same queue handle cannot
+				appear in the registry twice if it is added, removed, then
+				added again. */
+				xQueueRegistry[ ux ].xHandle = ( QueueHandle_t ) 0;
+ 80119a4:	4a09      	ldr	r2, [pc, #36]	; (80119cc <vQueueUnregisterQueue+0x50>)
+ 80119a6:	68fb      	ldr	r3, [r7, #12]
+ 80119a8:	00db      	lsls	r3, r3, #3
+ 80119aa:	4413      	add	r3, r2
+ 80119ac:	2200      	movs	r2, #0
+ 80119ae:	605a      	str	r2, [r3, #4]
+				break;
+ 80119b0:	e006      	b.n	80119c0 <vQueueUnregisterQueue+0x44>
+		for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ )
+ 80119b2:	68fb      	ldr	r3, [r7, #12]
+ 80119b4:	3301      	adds	r3, #1
+ 80119b6:	60fb      	str	r3, [r7, #12]
+ 80119b8:	68fb      	ldr	r3, [r7, #12]
+ 80119ba:	2b07      	cmp	r3, #7
+ 80119bc:	d9e5      	bls.n	801198a <vQueueUnregisterQueue+0xe>
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+
+	} /*lint !e818 xQueue could not be pointer to const because it is a typedef. */
+ 80119be:	bf00      	nop
+ 80119c0:	bf00      	nop
+ 80119c2:	3714      	adds	r7, #20
+ 80119c4:	46bd      	mov	sp, r7
+ 80119c6:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 80119ca:	4770      	bx	lr
+ 80119cc:	2400bee0 	.word	0x2400bee0
+
+080119d0 <vQueueWaitForMessageRestricted>:
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TIMERS == 1 )
+
+	void vQueueWaitForMessageRestricted( QueueHandle_t xQueue, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely )
+	{
+ 80119d0:	b580      	push	{r7, lr}
+ 80119d2:	b086      	sub	sp, #24
+ 80119d4:	af00      	add	r7, sp, #0
+ 80119d6:	60f8      	str	r0, [r7, #12]
+ 80119d8:	60b9      	str	r1, [r7, #8]
+ 80119da:	607a      	str	r2, [r7, #4]
+	Queue_t * const pxQueue = xQueue;
+ 80119dc:	68fb      	ldr	r3, [r7, #12]
+ 80119de:	617b      	str	r3, [r7, #20]
+		will not actually cause the task to block, just place it on a blocked
+		list.  It will not block until the scheduler is unlocked - at which
+		time a yield will be performed.  If an item is added to the queue while
+		the queue is locked, and the calling task blocks on the queue, then the
+		calling task will be immediately unblocked when the queue is unlocked. */
+		prvLockQueue( pxQueue );
+ 80119e0:	f001 fd10 	bl	8013404 <vPortEnterCritical>
+ 80119e4:	697b      	ldr	r3, [r7, #20]
+ 80119e6:	f893 3044 	ldrb.w	r3, [r3, #68]	; 0x44
+ 80119ea:	b25b      	sxtb	r3, r3
+ 80119ec:	f1b3 3fff 	cmp.w	r3, #4294967295
+ 80119f0:	d103      	bne.n	80119fa <vQueueWaitForMessageRestricted+0x2a>
+ 80119f2:	697b      	ldr	r3, [r7, #20]
+ 80119f4:	2200      	movs	r2, #0
+ 80119f6:	f883 2044 	strb.w	r2, [r3, #68]	; 0x44
+ 80119fa:	697b      	ldr	r3, [r7, #20]
+ 80119fc:	f893 3045 	ldrb.w	r3, [r3, #69]	; 0x45
+ 8011a00:	b25b      	sxtb	r3, r3
+ 8011a02:	f1b3 3fff 	cmp.w	r3, #4294967295
+ 8011a06:	d103      	bne.n	8011a10 <vQueueWaitForMessageRestricted+0x40>
+ 8011a08:	697b      	ldr	r3, [r7, #20]
+ 8011a0a:	2200      	movs	r2, #0
+ 8011a0c:	f883 2045 	strb.w	r2, [r3, #69]	; 0x45
+ 8011a10:	f001 fd28 	bl	8013464 <vPortExitCritical>
+		if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0U )
+ 8011a14:	697b      	ldr	r3, [r7, #20]
+ 8011a16:	6b9b      	ldr	r3, [r3, #56]	; 0x38
+ 8011a18:	2b00      	cmp	r3, #0
+ 8011a1a:	d106      	bne.n	8011a2a <vQueueWaitForMessageRestricted+0x5a>
+		{
+			/* There is nothing in the queue, block for the specified period. */
+			vTaskPlaceOnEventListRestricted( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait, xWaitIndefinitely );
+ 8011a1c:	697b      	ldr	r3, [r7, #20]
+ 8011a1e:	3324      	adds	r3, #36	; 0x24
+ 8011a20:	687a      	ldr	r2, [r7, #4]
+ 8011a22:	68b9      	ldr	r1, [r7, #8]
+ 8011a24:	4618      	mov	r0, r3
+ 8011a26:	f000 fc4f 	bl	80122c8 <vTaskPlaceOnEventListRestricted>
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+		prvUnlockQueue( pxQueue );
+ 8011a2a:	6978      	ldr	r0, [r7, #20]
+ 8011a2c:	f7ff fefb 	bl	8011826 <prvUnlockQueue>
+	}
+ 8011a30:	bf00      	nop
+ 8011a32:	3718      	adds	r7, #24
+ 8011a34:	46bd      	mov	sp, r7
+ 8011a36:	bd80      	pop	{r7, pc}
+
+08011a38 <xTaskCreateStatic>:
+									const uint32_t ulStackDepth,
+									void * const pvParameters,
+									UBaseType_t uxPriority,
+									StackType_t * const puxStackBuffer,
+									StaticTask_t * const pxTaskBuffer )
+	{
+ 8011a38:	b580      	push	{r7, lr}
+ 8011a3a:	b08e      	sub	sp, #56	; 0x38
+ 8011a3c:	af04      	add	r7, sp, #16
+ 8011a3e:	60f8      	str	r0, [r7, #12]
+ 8011a40:	60b9      	str	r1, [r7, #8]
+ 8011a42:	607a      	str	r2, [r7, #4]
+ 8011a44:	603b      	str	r3, [r7, #0]
+	TCB_t *pxNewTCB;
+	TaskHandle_t xReturn;
+
+		configASSERT( puxStackBuffer != NULL );
+ 8011a46:	6b7b      	ldr	r3, [r7, #52]	; 0x34
+ 8011a48:	2b00      	cmp	r3, #0
+ 8011a4a:	d10a      	bne.n	8011a62 <xTaskCreateStatic+0x2a>
+	__asm volatile
+ 8011a4c:	f04f 0350 	mov.w	r3, #80	; 0x50
+ 8011a50:	f383 8811 	msr	BASEPRI, r3
+ 8011a54:	f3bf 8f6f 	isb	sy
+ 8011a58:	f3bf 8f4f 	dsb	sy
+ 8011a5c:	623b      	str	r3, [r7, #32]
+}
+ 8011a5e:	bf00      	nop
+ 8011a60:	e7fe      	b.n	8011a60 <xTaskCreateStatic+0x28>
+		configASSERT( pxTaskBuffer != NULL );
+ 8011a62:	6bbb      	ldr	r3, [r7, #56]	; 0x38
+ 8011a64:	2b00      	cmp	r3, #0
+ 8011a66:	d10a      	bne.n	8011a7e <xTaskCreateStatic+0x46>
+	__asm volatile
+ 8011a68:	f04f 0350 	mov.w	r3, #80	; 0x50
+ 8011a6c:	f383 8811 	msr	BASEPRI, r3
+ 8011a70:	f3bf 8f6f 	isb	sy
+ 8011a74:	f3bf 8f4f 	dsb	sy
+ 8011a78:	61fb      	str	r3, [r7, #28]
+}
+ 8011a7a:	bf00      	nop
+ 8011a7c:	e7fe      	b.n	8011a7c <xTaskCreateStatic+0x44>
+		#if( configASSERT_DEFINED == 1 )
+		{
+			/* Sanity check that the size of the structure used to declare a
+			variable of type StaticTask_t equals the size of the real task
+			structure. */
+			volatile size_t xSize = sizeof( StaticTask_t );
+ 8011a7e:	2354      	movs	r3, #84	; 0x54
+ 8011a80:	613b      	str	r3, [r7, #16]
+			configASSERT( xSize == sizeof( TCB_t ) );
+ 8011a82:	693b      	ldr	r3, [r7, #16]
+ 8011a84:	2b54      	cmp	r3, #84	; 0x54
+ 8011a86:	d00a      	beq.n	8011a9e <xTaskCreateStatic+0x66>
+	__asm volatile
+ 8011a88:	f04f 0350 	mov.w	r3, #80	; 0x50
+ 8011a8c:	f383 8811 	msr	BASEPRI, r3
+ 8011a90:	f3bf 8f6f 	isb	sy
+ 8011a94:	f3bf 8f4f 	dsb	sy
+ 8011a98:	61bb      	str	r3, [r7, #24]
+}
+ 8011a9a:	bf00      	nop
+ 8011a9c:	e7fe      	b.n	8011a9c <xTaskCreateStatic+0x64>
+			( void ) xSize; /* Prevent lint warning when configASSERT() is not used. */
+ 8011a9e:	693b      	ldr	r3, [r7, #16]
+		}
+		#endif /* configASSERT_DEFINED */
+
+
+		if( ( pxTaskBuffer != NULL ) && ( puxStackBuffer != NULL ) )
+ 8011aa0:	6bbb      	ldr	r3, [r7, #56]	; 0x38
+ 8011aa2:	2b00      	cmp	r3, #0
+ 8011aa4:	d01e      	beq.n	8011ae4 <xTaskCreateStatic+0xac>
+ 8011aa6:	6b7b      	ldr	r3, [r7, #52]	; 0x34
+ 8011aa8:	2b00      	cmp	r3, #0
+ 8011aaa:	d01b      	beq.n	8011ae4 <xTaskCreateStatic+0xac>
+		{
+			/* The memory used for the task's TCB and stack are passed into this
+			function - use them. */
+			pxNewTCB = ( TCB_t * ) pxTaskBuffer; /*lint !e740 !e9087 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */
+ 8011aac:	6bbb      	ldr	r3, [r7, #56]	; 0x38
+ 8011aae:	627b      	str	r3, [r7, #36]	; 0x24
+			pxNewTCB->pxStack = ( StackType_t * ) puxStackBuffer;
+ 8011ab0:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 8011ab2:	6b7a      	ldr	r2, [r7, #52]	; 0x34
+ 8011ab4:	631a      	str	r2, [r3, #48]	; 0x30
+
+			#if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */
+			{
+				/* Tasks can be created statically or dynamically, so note this
+				task was created statically in case the task is later deleted. */
+				pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_AND_TCB;
+ 8011ab6:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 8011ab8:	2202      	movs	r2, #2
+ 8011aba:	f883 2051 	strb.w	r2, [r3, #81]	; 0x51
+			}
+			#endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */
+
+			prvInitialiseNewTask( pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, &xReturn, pxNewTCB, NULL );
+ 8011abe:	2300      	movs	r3, #0
+ 8011ac0:	9303      	str	r3, [sp, #12]
+ 8011ac2:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 8011ac4:	9302      	str	r3, [sp, #8]
+ 8011ac6:	f107 0314 	add.w	r3, r7, #20
+ 8011aca:	9301      	str	r3, [sp, #4]
+ 8011acc:	6b3b      	ldr	r3, [r7, #48]	; 0x30
+ 8011ace:	9300      	str	r3, [sp, #0]
+ 8011ad0:	683b      	ldr	r3, [r7, #0]
+ 8011ad2:	687a      	ldr	r2, [r7, #4]
+ 8011ad4:	68b9      	ldr	r1, [r7, #8]
+ 8011ad6:	68f8      	ldr	r0, [r7, #12]
+ 8011ad8:	f000 f850 	bl	8011b7c <prvInitialiseNewTask>
+			prvAddNewTaskToReadyList( pxNewTCB );
+ 8011adc:	6a78      	ldr	r0, [r7, #36]	; 0x24
+ 8011ade:	f000 f8dd 	bl	8011c9c <prvAddNewTaskToReadyList>
+ 8011ae2:	e001      	b.n	8011ae8 <xTaskCreateStatic+0xb0>
+		}
+		else
+		{
+			xReturn = NULL;
+ 8011ae4:	2300      	movs	r3, #0
+ 8011ae6:	617b      	str	r3, [r7, #20]
+		}
+
+		return xReturn;
+ 8011ae8:	697b      	ldr	r3, [r7, #20]
+	}
+ 8011aea:	4618      	mov	r0, r3
+ 8011aec:	3728      	adds	r7, #40	; 0x28
+ 8011aee:	46bd      	mov	sp, r7
+ 8011af0:	bd80      	pop	{r7, pc}
+
+08011af2 <xTaskCreate>:
+							const char * const pcName,		/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+							const configSTACK_DEPTH_TYPE usStackDepth,
+							void * const pvParameters,
+							UBaseType_t uxPriority,
+							TaskHandle_t * const pxCreatedTask )
+	{
+ 8011af2:	b580      	push	{r7, lr}
+ 8011af4:	b08c      	sub	sp, #48	; 0x30
+ 8011af6:	af04      	add	r7, sp, #16
+ 8011af8:	60f8      	str	r0, [r7, #12]
+ 8011afa:	60b9      	str	r1, [r7, #8]
+ 8011afc:	603b      	str	r3, [r7, #0]
+ 8011afe:	4613      	mov	r3, r2
+ 8011b00:	80fb      	strh	r3, [r7, #6]
+		#else /* portSTACK_GROWTH */
+		{
+		StackType_t *pxStack;
+
+			/* Allocate space for the stack used by the task being created. */
+			pxStack = pvPortMalloc( ( ( ( size_t ) usStackDepth ) * sizeof( StackType_t ) ) ); /*lint !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack and this allocation is the stack. */
+ 8011b02:	88fb      	ldrh	r3, [r7, #6]
+ 8011b04:	009b      	lsls	r3, r3, #2
+ 8011b06:	4618      	mov	r0, r3
+ 8011b08:	f001 fd9e 	bl	8013648 <pvPortMalloc>
+ 8011b0c:	6178      	str	r0, [r7, #20]
+
+			if( pxStack != NULL )
+ 8011b0e:	697b      	ldr	r3, [r7, #20]
+ 8011b10:	2b00      	cmp	r3, #0
+ 8011b12:	d00e      	beq.n	8011b32 <xTaskCreate+0x40>
+			{
+				/* Allocate space for the TCB. */
+				pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) ); /*lint !e9087 !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack, and the first member of TCB_t is always a pointer to the task's stack. */
+ 8011b14:	2054      	movs	r0, #84	; 0x54
+ 8011b16:	f001 fd97 	bl	8013648 <pvPortMalloc>
+ 8011b1a:	61f8      	str	r0, [r7, #28]
+
+				if( pxNewTCB != NULL )
+ 8011b1c:	69fb      	ldr	r3, [r7, #28]
+ 8011b1e:	2b00      	cmp	r3, #0
+ 8011b20:	d003      	beq.n	8011b2a <xTaskCreate+0x38>
+				{
+					/* Store the stack location in the TCB. */
+					pxNewTCB->pxStack = pxStack;
+ 8011b22:	69fb      	ldr	r3, [r7, #28]
+ 8011b24:	697a      	ldr	r2, [r7, #20]
+ 8011b26:	631a      	str	r2, [r3, #48]	; 0x30
+ 8011b28:	e005      	b.n	8011b36 <xTaskCreate+0x44>
+				}
+				else
+				{
+					/* The stack cannot be used as the TCB was not created.  Free
+					it again. */
+					vPortFree( pxStack );
+ 8011b2a:	6978      	ldr	r0, [r7, #20]
+ 8011b2c:	f001 fe58 	bl	80137e0 <vPortFree>
+ 8011b30:	e001      	b.n	8011b36 <xTaskCreate+0x44>
+				}
+			}
+			else
+			{
+				pxNewTCB = NULL;
+ 8011b32:	2300      	movs	r3, #0
+ 8011b34:	61fb      	str	r3, [r7, #28]
+			}
+		}
+		#endif /* portSTACK_GROWTH */
+
+		if( pxNewTCB != NULL )
+ 8011b36:	69fb      	ldr	r3, [r7, #28]
+ 8011b38:	2b00      	cmp	r3, #0
+ 8011b3a:	d017      	beq.n	8011b6c <xTaskCreate+0x7a>
+		{
+			#if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e9029 !e731 Macro has been consolidated for readability reasons. */
+			{
+				/* Tasks can be created statically or dynamically, so note this
+				task was created dynamically in case it is later deleted. */
+				pxNewTCB->ucStaticallyAllocated = tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB;
+ 8011b3c:	69fb      	ldr	r3, [r7, #28]
+ 8011b3e:	2200      	movs	r2, #0
+ 8011b40:	f883 2051 	strb.w	r2, [r3, #81]	; 0x51
+			}
+			#endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */
+
+			prvInitialiseNewTask( pxTaskCode, pcName, ( uint32_t ) usStackDepth, pvParameters, uxPriority, pxCreatedTask, pxNewTCB, NULL );
+ 8011b44:	88fa      	ldrh	r2, [r7, #6]
+ 8011b46:	2300      	movs	r3, #0
+ 8011b48:	9303      	str	r3, [sp, #12]
+ 8011b4a:	69fb      	ldr	r3, [r7, #28]
+ 8011b4c:	9302      	str	r3, [sp, #8]
+ 8011b4e:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 8011b50:	9301      	str	r3, [sp, #4]
+ 8011b52:	6abb      	ldr	r3, [r7, #40]	; 0x28
+ 8011b54:	9300      	str	r3, [sp, #0]
+ 8011b56:	683b      	ldr	r3, [r7, #0]
+ 8011b58:	68b9      	ldr	r1, [r7, #8]
+ 8011b5a:	68f8      	ldr	r0, [r7, #12]
+ 8011b5c:	f000 f80e 	bl	8011b7c <prvInitialiseNewTask>
+			prvAddNewTaskToReadyList( pxNewTCB );
+ 8011b60:	69f8      	ldr	r0, [r7, #28]
+ 8011b62:	f000 f89b 	bl	8011c9c <prvAddNewTaskToReadyList>
+			xReturn = pdPASS;
+ 8011b66:	2301      	movs	r3, #1
+ 8011b68:	61bb      	str	r3, [r7, #24]
+ 8011b6a:	e002      	b.n	8011b72 <xTaskCreate+0x80>
+		}
+		else
+		{
+			xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;
+ 8011b6c:	f04f 33ff 	mov.w	r3, #4294967295
+ 8011b70:	61bb      	str	r3, [r7, #24]
+		}
+
+		return xReturn;
+ 8011b72:	69bb      	ldr	r3, [r7, #24]
+	}
+ 8011b74:	4618      	mov	r0, r3
+ 8011b76:	3720      	adds	r7, #32
+ 8011b78:	46bd      	mov	sp, r7
+ 8011b7a:	bd80      	pop	{r7, pc}
+
+08011b7c <prvInitialiseNewTask>:
+									void * const pvParameters,
+									UBaseType_t uxPriority,
+									TaskHandle_t * const pxCreatedTask,
+									TCB_t *pxNewTCB,
+									const MemoryRegion_t * const xRegions )
+{
+ 8011b7c:	b580      	push	{r7, lr}
+ 8011b7e:	b088      	sub	sp, #32
+ 8011b80:	af00      	add	r7, sp, #0
+ 8011b82:	60f8      	str	r0, [r7, #12]
+ 8011b84:	60b9      	str	r1, [r7, #8]
+ 8011b86:	607a      	str	r2, [r7, #4]
+ 8011b88:	603b      	str	r3, [r7, #0]
+
+	/* Avoid dependency on memset() if it is not required. */
+	#if( tskSET_NEW_STACKS_TO_KNOWN_VALUE == 1 )
+	{
+		/* Fill the stack with a known value to assist debugging. */
+		( void ) memset( pxNewTCB->pxStack, ( int ) tskSTACK_FILL_BYTE, ( size_t ) ulStackDepth * sizeof( StackType_t ) );
+ 8011b8a:	6b3b      	ldr	r3, [r7, #48]	; 0x30
+ 8011b8c:	6b18      	ldr	r0, [r3, #48]	; 0x30
+ 8011b8e:	687b      	ldr	r3, [r7, #4]
+ 8011b90:	009b      	lsls	r3, r3, #2
+ 8011b92:	461a      	mov	r2, r3
+ 8011b94:	21a5      	movs	r1, #165	; 0xa5
+ 8011b96:	f010 f8a3 	bl	8021ce0 <memset>
+	grows from high memory to low (as per the 80x86) or vice versa.
+	portSTACK_GROWTH is used to make the result positive or negative as required
+	by the port. */
+	#if( portSTACK_GROWTH < 0 )
+	{
+		pxTopOfStack = &( pxNewTCB->pxStack[ ulStackDepth - ( uint32_t ) 1 ] );
+ 8011b9a:	6b3b      	ldr	r3, [r7, #48]	; 0x30
+ 8011b9c:	6b1a      	ldr	r2, [r3, #48]	; 0x30
+ 8011b9e:	6879      	ldr	r1, [r7, #4]
+ 8011ba0:	f06f 4340 	mvn.w	r3, #3221225472	; 0xc0000000
+ 8011ba4:	440b      	add	r3, r1
+ 8011ba6:	009b      	lsls	r3, r3, #2
+ 8011ba8:	4413      	add	r3, r2
+ 8011baa:	61bb      	str	r3, [r7, #24]
+		pxTopOfStack = ( StackType_t * ) ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) ); /*lint !e923 !e9033 !e9078 MISRA exception.  Avoiding casts between pointers and integers is not practical.  Size differences accounted for using portPOINTER_SIZE_TYPE type.  Checked by assert(). */
+ 8011bac:	69bb      	ldr	r3, [r7, #24]
+ 8011bae:	f023 0307 	bic.w	r3, r3, #7
+ 8011bb2:	61bb      	str	r3, [r7, #24]
+
+		/* Check the alignment of the calculated top of stack is correct. */
+		configASSERT( ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack & ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) == 0UL ) );
+ 8011bb4:	69bb      	ldr	r3, [r7, #24]
+ 8011bb6:	f003 0307 	and.w	r3, r3, #7
+ 8011bba:	2b00      	cmp	r3, #0
+ 8011bbc:	d00a      	beq.n	8011bd4 <prvInitialiseNewTask+0x58>
+	__asm volatile
+ 8011bbe:	f04f 0350 	mov.w	r3, #80	; 0x50
+ 8011bc2:	f383 8811 	msr	BASEPRI, r3
+ 8011bc6:	f3bf 8f6f 	isb	sy
+ 8011bca:	f3bf 8f4f 	dsb	sy
+ 8011bce:	617b      	str	r3, [r7, #20]
+}
+ 8011bd0:	bf00      	nop
+ 8011bd2:	e7fe      	b.n	8011bd2 <prvInitialiseNewTask+0x56>
+		pxNewTCB->pxEndOfStack = pxNewTCB->pxStack + ( ulStackDepth - ( uint32_t ) 1 );
+	}
+	#endif /* portSTACK_GROWTH */
+
+	/* Store the task name in the TCB. */
+	if( pcName != NULL )
+ 8011bd4:	68bb      	ldr	r3, [r7, #8]
+ 8011bd6:	2b00      	cmp	r3, #0
+ 8011bd8:	d01f      	beq.n	8011c1a <prvInitialiseNewTask+0x9e>
+	{
+		for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ )
+ 8011bda:	2300      	movs	r3, #0
+ 8011bdc:	61fb      	str	r3, [r7, #28]
+ 8011bde:	e012      	b.n	8011c06 <prvInitialiseNewTask+0x8a>
+		{
+			pxNewTCB->pcTaskName[ x ] = pcName[ x ];
+ 8011be0:	68ba      	ldr	r2, [r7, #8]
+ 8011be2:	69fb      	ldr	r3, [r7, #28]
+ 8011be4:	4413      	add	r3, r2
+ 8011be6:	7819      	ldrb	r1, [r3, #0]
+ 8011be8:	6b3a      	ldr	r2, [r7, #48]	; 0x30
+ 8011bea:	69fb      	ldr	r3, [r7, #28]
+ 8011bec:	4413      	add	r3, r2
+ 8011bee:	3334      	adds	r3, #52	; 0x34
+ 8011bf0:	460a      	mov	r2, r1
+ 8011bf2:	701a      	strb	r2, [r3, #0]
+
+			/* Don't copy all configMAX_TASK_NAME_LEN if the string is shorter than
+			configMAX_TASK_NAME_LEN characters just in case the memory after the
+			string is not accessible (extremely unlikely). */
+			if( pcName[ x ] == ( char ) 0x00 )
+ 8011bf4:	68ba      	ldr	r2, [r7, #8]
+ 8011bf6:	69fb      	ldr	r3, [r7, #28]
+ 8011bf8:	4413      	add	r3, r2
+ 8011bfa:	781b      	ldrb	r3, [r3, #0]
+ 8011bfc:	2b00      	cmp	r3, #0
+ 8011bfe:	d006      	beq.n	8011c0e <prvInitialiseNewTask+0x92>
+		for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ )
+ 8011c00:	69fb      	ldr	r3, [r7, #28]
+ 8011c02:	3301      	adds	r3, #1
+ 8011c04:	61fb      	str	r3, [r7, #28]
+ 8011c06:	69fb      	ldr	r3, [r7, #28]
+ 8011c08:	2b0f      	cmp	r3, #15
+ 8011c0a:	d9e9      	bls.n	8011be0 <prvInitialiseNewTask+0x64>
+ 8011c0c:	e000      	b.n	8011c10 <prvInitialiseNewTask+0x94>
+			{
+				break;
+ 8011c0e:	bf00      	nop
+			}
+		}
+
+		/* Ensure the name string is terminated in the case that the string length
+		was greater or equal to configMAX_TASK_NAME_LEN. */
+		pxNewTCB->pcTaskName[ configMAX_TASK_NAME_LEN - 1 ] = '\0';
+ 8011c10:	6b3b      	ldr	r3, [r7, #48]	; 0x30
+ 8011c12:	2200      	movs	r2, #0
+ 8011c14:	f883 2043 	strb.w	r2, [r3, #67]	; 0x43
+ 8011c18:	e003      	b.n	8011c22 <prvInitialiseNewTask+0xa6>
+	}
+	else
+	{
+		/* The task has not been given a name, so just ensure there is a NULL
+		terminator when it is read out. */
+		pxNewTCB->pcTaskName[ 0 ] = 0x00;
+ 8011c1a:	6b3b      	ldr	r3, [r7, #48]	; 0x30
+ 8011c1c:	2200      	movs	r2, #0
+ 8011c1e:	f883 2034 	strb.w	r2, [r3, #52]	; 0x34
+	}
+
+	/* This is used as an array index so must ensure it's not too large.  First
+	remove the privilege bit if one is present. */
+	if( uxPriority >= ( UBaseType_t ) configMAX_PRIORITIES )
+ 8011c22:	6abb      	ldr	r3, [r7, #40]	; 0x28
+ 8011c24:	2b06      	cmp	r3, #6
+ 8011c26:	d901      	bls.n	8011c2c <prvInitialiseNewTask+0xb0>
+	{
+		uxPriority = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) 1U;
+ 8011c28:	2306      	movs	r3, #6
+ 8011c2a:	62bb      	str	r3, [r7, #40]	; 0x28
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	pxNewTCB->uxPriority = uxPriority;
+ 8011c2c:	6b3b      	ldr	r3, [r7, #48]	; 0x30
+ 8011c2e:	6aba      	ldr	r2, [r7, #40]	; 0x28
+ 8011c30:	62da      	str	r2, [r3, #44]	; 0x2c
+	#if ( configUSE_MUTEXES == 1 )
+	{
+		pxNewTCB->uxBasePriority = uxPriority;
+ 8011c32:	6b3b      	ldr	r3, [r7, #48]	; 0x30
+ 8011c34:	6aba      	ldr	r2, [r7, #40]	; 0x28
+ 8011c36:	645a      	str	r2, [r3, #68]	; 0x44
+		pxNewTCB->uxMutexesHeld = 0;
+ 8011c38:	6b3b      	ldr	r3, [r7, #48]	; 0x30
+ 8011c3a:	2200      	movs	r2, #0
+ 8011c3c:	649a      	str	r2, [r3, #72]	; 0x48
+	}
+	#endif /* configUSE_MUTEXES */
+
+	vListInitialiseItem( &( pxNewTCB->xStateListItem ) );
+ 8011c3e:	6b3b      	ldr	r3, [r7, #48]	; 0x30
+ 8011c40:	3304      	adds	r3, #4
+ 8011c42:	4618      	mov	r0, r3
+ 8011c44:	f7fe fe3b 	bl	80108be <vListInitialiseItem>
+	vListInitialiseItem( &( pxNewTCB->xEventListItem ) );
+ 8011c48:	6b3b      	ldr	r3, [r7, #48]	; 0x30
+ 8011c4a:	3318      	adds	r3, #24
+ 8011c4c:	4618      	mov	r0, r3
+ 8011c4e:	f7fe fe36 	bl	80108be <vListInitialiseItem>
+
+	/* Set the pxNewTCB as a link back from the ListItem_t.  This is so we can get
+	back to	the containing TCB from a generic item in a list. */
+	listSET_LIST_ITEM_OWNER( &( pxNewTCB->xStateListItem ), pxNewTCB );
+ 8011c52:	6b3b      	ldr	r3, [r7, #48]	; 0x30
+ 8011c54:	6b3a      	ldr	r2, [r7, #48]	; 0x30
+ 8011c56:	611a      	str	r2, [r3, #16]
+
+	/* Event lists are always in priority order. */
+	listSET_LIST_ITEM_VALUE( &( pxNewTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+ 8011c58:	6abb      	ldr	r3, [r7, #40]	; 0x28
+ 8011c5a:	f1c3 0207 	rsb	r2, r3, #7
+ 8011c5e:	6b3b      	ldr	r3, [r7, #48]	; 0x30
+ 8011c60:	619a      	str	r2, [r3, #24]
+	listSET_LIST_ITEM_OWNER( &( pxNewTCB->xEventListItem ), pxNewTCB );
+ 8011c62:	6b3b      	ldr	r3, [r7, #48]	; 0x30
+ 8011c64:	6b3a      	ldr	r2, [r7, #48]	; 0x30
+ 8011c66:	625a      	str	r2, [r3, #36]	; 0x24
+	}
+	#endif
+
+	#if ( configUSE_TASK_NOTIFICATIONS == 1 )
+	{
+		pxNewTCB->ulNotifiedValue = 0;
+ 8011c68:	6b3b      	ldr	r3, [r7, #48]	; 0x30
+ 8011c6a:	2200      	movs	r2, #0
+ 8011c6c:	64da      	str	r2, [r3, #76]	; 0x4c
+		pxNewTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION;
+ 8011c6e:	6b3b      	ldr	r3, [r7, #48]	; 0x30
+ 8011c70:	2200      	movs	r2, #0
+ 8011c72:	f883 2050 	strb.w	r2, [r3, #80]	; 0x50
+			}
+			#endif /* portSTACK_GROWTH */
+		}
+		#else /* portHAS_STACK_OVERFLOW_CHECKING */
+		{
+			pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters );
+ 8011c76:	683a      	ldr	r2, [r7, #0]
+ 8011c78:	68f9      	ldr	r1, [r7, #12]
+ 8011c7a:	69b8      	ldr	r0, [r7, #24]
+ 8011c7c:	f001 fa98 	bl	80131b0 <pxPortInitialiseStack>
+ 8011c80:	4602      	mov	r2, r0
+ 8011c82:	6b3b      	ldr	r3, [r7, #48]	; 0x30
+ 8011c84:	601a      	str	r2, [r3, #0]
+		}
+		#endif /* portHAS_STACK_OVERFLOW_CHECKING */
+	}
+	#endif /* portUSING_MPU_WRAPPERS */
+
+	if( pxCreatedTask != NULL )
+ 8011c86:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 8011c88:	2b00      	cmp	r3, #0
+ 8011c8a:	d002      	beq.n	8011c92 <prvInitialiseNewTask+0x116>
+	{
+		/* Pass the handle out in an anonymous way.  The handle can be used to
+		change the created task's priority, delete the created task, etc.*/
+		*pxCreatedTask = ( TaskHandle_t ) pxNewTCB;
+ 8011c8c:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 8011c8e:	6b3a      	ldr	r2, [r7, #48]	; 0x30
+ 8011c90:	601a      	str	r2, [r3, #0]
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+}
+ 8011c92:	bf00      	nop
+ 8011c94:	3720      	adds	r7, #32
+ 8011c96:	46bd      	mov	sp, r7
+ 8011c98:	bd80      	pop	{r7, pc}
+	...
+
+08011c9c <prvAddNewTaskToReadyList>:
+/*-----------------------------------------------------------*/
+
+static void prvAddNewTaskToReadyList( TCB_t *pxNewTCB )
+{
+ 8011c9c:	b580      	push	{r7, lr}
+ 8011c9e:	b082      	sub	sp, #8
+ 8011ca0:	af00      	add	r7, sp, #0
+ 8011ca2:	6078      	str	r0, [r7, #4]
+	/* Ensure interrupts don't access the task lists while the lists are being
+	updated. */
+	taskENTER_CRITICAL();
+ 8011ca4:	f001 fbae 	bl	8013404 <vPortEnterCritical>
+	{
+		uxCurrentNumberOfTasks++;
+ 8011ca8:	4b2a      	ldr	r3, [pc, #168]	; (8011d54 <prvAddNewTaskToReadyList+0xb8>)
+ 8011caa:	681b      	ldr	r3, [r3, #0]
+ 8011cac:	3301      	adds	r3, #1
+ 8011cae:	4a29      	ldr	r2, [pc, #164]	; (8011d54 <prvAddNewTaskToReadyList+0xb8>)
+ 8011cb0:	6013      	str	r3, [r2, #0]
+		if( pxCurrentTCB == NULL )
+ 8011cb2:	4b29      	ldr	r3, [pc, #164]	; (8011d58 <prvAddNewTaskToReadyList+0xbc>)
+ 8011cb4:	681b      	ldr	r3, [r3, #0]
+ 8011cb6:	2b00      	cmp	r3, #0
+ 8011cb8:	d109      	bne.n	8011cce <prvAddNewTaskToReadyList+0x32>
+		{
+			/* There are no other tasks, or all the other tasks are in
+			the suspended state - make this the current task. */
+			pxCurrentTCB = pxNewTCB;
+ 8011cba:	4a27      	ldr	r2, [pc, #156]	; (8011d58 <prvAddNewTaskToReadyList+0xbc>)
+ 8011cbc:	687b      	ldr	r3, [r7, #4]
+ 8011cbe:	6013      	str	r3, [r2, #0]
+
+			if( uxCurrentNumberOfTasks == ( UBaseType_t ) 1 )
+ 8011cc0:	4b24      	ldr	r3, [pc, #144]	; (8011d54 <prvAddNewTaskToReadyList+0xb8>)
+ 8011cc2:	681b      	ldr	r3, [r3, #0]
+ 8011cc4:	2b01      	cmp	r3, #1
+ 8011cc6:	d110      	bne.n	8011cea <prvAddNewTaskToReadyList+0x4e>
+			{
+				/* This is the first task to be created so do the preliminary
+				initialisation required.  We will not recover if this call
+				fails, but we will report the failure. */
+				prvInitialiseTaskLists();
+ 8011cc8:	f000 fc28 	bl	801251c <prvInitialiseTaskLists>
+ 8011ccc:	e00d      	b.n	8011cea <prvAddNewTaskToReadyList+0x4e>
+		else
+		{
+			/* If the scheduler is not already running, make this task the
+			current task if it is the highest priority task to be created
+			so far. */
+			if( xSchedulerRunning == pdFALSE )
+ 8011cce:	4b23      	ldr	r3, [pc, #140]	; (8011d5c <prvAddNewTaskToReadyList+0xc0>)
+ 8011cd0:	681b      	ldr	r3, [r3, #0]
+ 8011cd2:	2b00      	cmp	r3, #0
+ 8011cd4:	d109      	bne.n	8011cea <prvAddNewTaskToReadyList+0x4e>
+			{
+				if( pxCurrentTCB->uxPriority <= pxNewTCB->uxPriority )
+ 8011cd6:	4b20      	ldr	r3, [pc, #128]	; (8011d58 <prvAddNewTaskToReadyList+0xbc>)
+ 8011cd8:	681b      	ldr	r3, [r3, #0]
+ 8011cda:	6ada      	ldr	r2, [r3, #44]	; 0x2c
+ 8011cdc:	687b      	ldr	r3, [r7, #4]
+ 8011cde:	6adb      	ldr	r3, [r3, #44]	; 0x2c
+ 8011ce0:	429a      	cmp	r2, r3
+ 8011ce2:	d802      	bhi.n	8011cea <prvAddNewTaskToReadyList+0x4e>
+				{
+					pxCurrentTCB = pxNewTCB;
+ 8011ce4:	4a1c      	ldr	r2, [pc, #112]	; (8011d58 <prvAddNewTaskToReadyList+0xbc>)
+ 8011ce6:	687b      	ldr	r3, [r7, #4]
+ 8011ce8:	6013      	str	r3, [r2, #0]
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+
+		uxTaskNumber++;
+ 8011cea:	4b1d      	ldr	r3, [pc, #116]	; (8011d60 <prvAddNewTaskToReadyList+0xc4>)
+ 8011cec:	681b      	ldr	r3, [r3, #0]
+ 8011cee:	3301      	adds	r3, #1
+ 8011cf0:	4a1b      	ldr	r2, [pc, #108]	; (8011d60 <prvAddNewTaskToReadyList+0xc4>)
+ 8011cf2:	6013      	str	r3, [r2, #0]
+			pxNewTCB->uxTCBNumber = uxTaskNumber;
+		}
+		#endif /* configUSE_TRACE_FACILITY */
+		traceTASK_CREATE( pxNewTCB );
+
+		prvAddTaskToReadyList( pxNewTCB );
+ 8011cf4:	687b      	ldr	r3, [r7, #4]
+ 8011cf6:	6adb      	ldr	r3, [r3, #44]	; 0x2c
+ 8011cf8:	2201      	movs	r2, #1
+ 8011cfa:	409a      	lsls	r2, r3
+ 8011cfc:	4b19      	ldr	r3, [pc, #100]	; (8011d64 <prvAddNewTaskToReadyList+0xc8>)
+ 8011cfe:	681b      	ldr	r3, [r3, #0]
+ 8011d00:	4313      	orrs	r3, r2
+ 8011d02:	4a18      	ldr	r2, [pc, #96]	; (8011d64 <prvAddNewTaskToReadyList+0xc8>)
+ 8011d04:	6013      	str	r3, [r2, #0]
+ 8011d06:	687b      	ldr	r3, [r7, #4]
+ 8011d08:	6ada      	ldr	r2, [r3, #44]	; 0x2c
+ 8011d0a:	4613      	mov	r3, r2
+ 8011d0c:	009b      	lsls	r3, r3, #2
+ 8011d0e:	4413      	add	r3, r2
+ 8011d10:	009b      	lsls	r3, r3, #2
+ 8011d12:	4a15      	ldr	r2, [pc, #84]	; (8011d68 <prvAddNewTaskToReadyList+0xcc>)
+ 8011d14:	441a      	add	r2, r3
+ 8011d16:	687b      	ldr	r3, [r7, #4]
+ 8011d18:	3304      	adds	r3, #4
+ 8011d1a:	4619      	mov	r1, r3
+ 8011d1c:	4610      	mov	r0, r2
+ 8011d1e:	f7fe fddb 	bl	80108d8 <vListInsertEnd>
+
+		portSETUP_TCB( pxNewTCB );
+	}
+	taskEXIT_CRITICAL();
+ 8011d22:	f001 fb9f 	bl	8013464 <vPortExitCritical>
+
+	if( xSchedulerRunning != pdFALSE )
+ 8011d26:	4b0d      	ldr	r3, [pc, #52]	; (8011d5c <prvAddNewTaskToReadyList+0xc0>)
+ 8011d28:	681b      	ldr	r3, [r3, #0]
+ 8011d2a:	2b00      	cmp	r3, #0
+ 8011d2c:	d00e      	beq.n	8011d4c <prvAddNewTaskToReadyList+0xb0>
+	{
+		/* If the created task is of a higher priority than the current task
+		then it should run now. */
+		if( pxCurrentTCB->uxPriority < pxNewTCB->uxPriority )
+ 8011d2e:	4b0a      	ldr	r3, [pc, #40]	; (8011d58 <prvAddNewTaskToReadyList+0xbc>)
+ 8011d30:	681b      	ldr	r3, [r3, #0]
+ 8011d32:	6ada      	ldr	r2, [r3, #44]	; 0x2c
+ 8011d34:	687b      	ldr	r3, [r7, #4]
+ 8011d36:	6adb      	ldr	r3, [r3, #44]	; 0x2c
+ 8011d38:	429a      	cmp	r2, r3
+ 8011d3a:	d207      	bcs.n	8011d4c <prvAddNewTaskToReadyList+0xb0>
+		{
+			taskYIELD_IF_USING_PREEMPTION();
+ 8011d3c:	4b0b      	ldr	r3, [pc, #44]	; (8011d6c <prvAddNewTaskToReadyList+0xd0>)
+ 8011d3e:	f04f 5280 	mov.w	r2, #268435456	; 0x10000000
+ 8011d42:	601a      	str	r2, [r3, #0]
+ 8011d44:	f3bf 8f4f 	dsb	sy
+ 8011d48:	f3bf 8f6f 	isb	sy
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+}
+ 8011d4c:	bf00      	nop
+ 8011d4e:	3708      	adds	r7, #8
+ 8011d50:	46bd      	mov	sp, r7
+ 8011d52:	bd80      	pop	{r7, pc}
+ 8011d54:	2400c020 	.word	0x2400c020
+ 8011d58:	2400bf20 	.word	0x2400bf20
+ 8011d5c:	2400c02c 	.word	0x2400c02c
+ 8011d60:	2400c03c 	.word	0x2400c03c
+ 8011d64:	2400c028 	.word	0x2400c028
+ 8011d68:	2400bf24 	.word	0x2400bf24
+ 8011d6c:	e000ed04 	.word	0xe000ed04
+
+08011d70 <vTaskDelay>:
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskDelay == 1 )
+
+	void vTaskDelay( const TickType_t xTicksToDelay )
+	{
+ 8011d70:	b580      	push	{r7, lr}
+ 8011d72:	b084      	sub	sp, #16
+ 8011d74:	af00      	add	r7, sp, #0
+ 8011d76:	6078      	str	r0, [r7, #4]
+	BaseType_t xAlreadyYielded = pdFALSE;
+ 8011d78:	2300      	movs	r3, #0
+ 8011d7a:	60fb      	str	r3, [r7, #12]
+
+		/* A delay time of zero just forces a reschedule. */
+		if( xTicksToDelay > ( TickType_t ) 0U )
+ 8011d7c:	687b      	ldr	r3, [r7, #4]
+ 8011d7e:	2b00      	cmp	r3, #0
+ 8011d80:	d017      	beq.n	8011db2 <vTaskDelay+0x42>
+		{
+			configASSERT( uxSchedulerSuspended == 0 );
+ 8011d82:	4b13      	ldr	r3, [pc, #76]	; (8011dd0 <vTaskDelay+0x60>)
+ 8011d84:	681b      	ldr	r3, [r3, #0]
+ 8011d86:	2b00      	cmp	r3, #0
+ 8011d88:	d00a      	beq.n	8011da0 <vTaskDelay+0x30>
+	__asm volatile
+ 8011d8a:	f04f 0350 	mov.w	r3, #80	; 0x50
+ 8011d8e:	f383 8811 	msr	BASEPRI, r3
+ 8011d92:	f3bf 8f6f 	isb	sy
+ 8011d96:	f3bf 8f4f 	dsb	sy
+ 8011d9a:	60bb      	str	r3, [r7, #8]
+}
+ 8011d9c:	bf00      	nop
+ 8011d9e:	e7fe      	b.n	8011d9e <vTaskDelay+0x2e>
+			vTaskSuspendAll();
+ 8011da0:	f000 f880 	bl	8011ea4 <vTaskSuspendAll>
+				list or removed from the blocked list until the scheduler
+				is resumed.
+
+				This task cannot be in an event list as it is the currently
+				executing task. */
+				prvAddCurrentTaskToDelayedList( xTicksToDelay, pdFALSE );
+ 8011da4:	2100      	movs	r1, #0
+ 8011da6:	6878      	ldr	r0, [r7, #4]
+ 8011da8:	f000 fe6a 	bl	8012a80 <prvAddCurrentTaskToDelayedList>
+			}
+			xAlreadyYielded = xTaskResumeAll();
+ 8011dac:	f000 f888 	bl	8011ec0 <xTaskResumeAll>
+ 8011db0:	60f8      	str	r0, [r7, #12]
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		/* Force a reschedule if xTaskResumeAll has not already done so, we may
+		have put ourselves to sleep. */
+		if( xAlreadyYielded == pdFALSE )
+ 8011db2:	68fb      	ldr	r3, [r7, #12]
+ 8011db4:	2b00      	cmp	r3, #0
+ 8011db6:	d107      	bne.n	8011dc8 <vTaskDelay+0x58>
+		{
+			portYIELD_WITHIN_API();
+ 8011db8:	4b06      	ldr	r3, [pc, #24]	; (8011dd4 <vTaskDelay+0x64>)
+ 8011dba:	f04f 5280 	mov.w	r2, #268435456	; 0x10000000
+ 8011dbe:	601a      	str	r2, [r3, #0]
+ 8011dc0:	f3bf 8f4f 	dsb	sy
+ 8011dc4:	f3bf 8f6f 	isb	sy
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+ 8011dc8:	bf00      	nop
+ 8011dca:	3710      	adds	r7, #16
+ 8011dcc:	46bd      	mov	sp, r7
+ 8011dce:	bd80      	pop	{r7, pc}
+ 8011dd0:	2400c048 	.word	0x2400c048
+ 8011dd4:	e000ed04 	.word	0xe000ed04
+
+08011dd8 <vTaskStartScheduler>:
+
+#endif /* ( ( INCLUDE_xTaskResumeFromISR == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+void vTaskStartScheduler( void )
+{
+ 8011dd8:	b580      	push	{r7, lr}
+ 8011dda:	b08a      	sub	sp, #40	; 0x28
+ 8011ddc:	af04      	add	r7, sp, #16
+BaseType_t xReturn;
+
+	/* Add the idle task at the lowest priority. */
+	#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+	{
+		StaticTask_t *pxIdleTaskTCBBuffer = NULL;
+ 8011dde:	2300      	movs	r3, #0
+ 8011de0:	60bb      	str	r3, [r7, #8]
+		StackType_t *pxIdleTaskStackBuffer = NULL;
+ 8011de2:	2300      	movs	r3, #0
+ 8011de4:	607b      	str	r3, [r7, #4]
+		uint32_t ulIdleTaskStackSize;
+
+		/* The Idle task is created using user provided RAM - obtain the
+		address of the RAM then create the idle task. */
+		vApplicationGetIdleTaskMemory( &pxIdleTaskTCBBuffer, &pxIdleTaskStackBuffer, &ulIdleTaskStackSize );
+ 8011de6:	463a      	mov	r2, r7
+ 8011de8:	1d39      	adds	r1, r7, #4
+ 8011dea:	f107 0308 	add.w	r3, r7, #8
+ 8011dee:	4618      	mov	r0, r3
+ 8011df0:	f7ee fc80 	bl	80006f4 <vApplicationGetIdleTaskMemory>
+		xIdleTaskHandle = xTaskCreateStatic(	prvIdleTask,
+ 8011df4:	6839      	ldr	r1, [r7, #0]
+ 8011df6:	687b      	ldr	r3, [r7, #4]
+ 8011df8:	68ba      	ldr	r2, [r7, #8]
+ 8011dfa:	9202      	str	r2, [sp, #8]
+ 8011dfc:	9301      	str	r3, [sp, #4]
+ 8011dfe:	2300      	movs	r3, #0
+ 8011e00:	9300      	str	r3, [sp, #0]
+ 8011e02:	2300      	movs	r3, #0
+ 8011e04:	460a      	mov	r2, r1
+ 8011e06:	4921      	ldr	r1, [pc, #132]	; (8011e8c <vTaskStartScheduler+0xb4>)
+ 8011e08:	4821      	ldr	r0, [pc, #132]	; (8011e90 <vTaskStartScheduler+0xb8>)
+ 8011e0a:	f7ff fe15 	bl	8011a38 <xTaskCreateStatic>
+ 8011e0e:	4603      	mov	r3, r0
+ 8011e10:	4a20      	ldr	r2, [pc, #128]	; (8011e94 <vTaskStartScheduler+0xbc>)
+ 8011e12:	6013      	str	r3, [r2, #0]
+												( void * ) NULL, /*lint !e961.  The cast is not redundant for all compilers. */
+												portPRIVILEGE_BIT, /* In effect ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), but tskIDLE_PRIORITY is zero. */
+												pxIdleTaskStackBuffer,
+												pxIdleTaskTCBBuffer ); /*lint !e961 MISRA exception, justified as it is not a redundant explicit cast to all supported compilers. */
+
+		if( xIdleTaskHandle != NULL )
+ 8011e14:	4b1f      	ldr	r3, [pc, #124]	; (8011e94 <vTaskStartScheduler+0xbc>)
+ 8011e16:	681b      	ldr	r3, [r3, #0]
+ 8011e18:	2b00      	cmp	r3, #0
+ 8011e1a:	d002      	beq.n	8011e22 <vTaskStartScheduler+0x4a>
+		{
+			xReturn = pdPASS;
+ 8011e1c:	2301      	movs	r3, #1
+ 8011e1e:	617b      	str	r3, [r7, #20]
+ 8011e20:	e001      	b.n	8011e26 <vTaskStartScheduler+0x4e>
+		}
+		else
+		{
+			xReturn = pdFAIL;
+ 8011e22:	2300      	movs	r3, #0
+ 8011e24:	617b      	str	r3, [r7, #20]
+	}
+	#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+	#if ( configUSE_TIMERS == 1 )
+	{
+		if( xReturn == pdPASS )
+ 8011e26:	697b      	ldr	r3, [r7, #20]
+ 8011e28:	2b01      	cmp	r3, #1
+ 8011e2a:	d102      	bne.n	8011e32 <vTaskStartScheduler+0x5a>
+		{
+			xReturn = xTimerCreateTimerTask();
+ 8011e2c:	f000 fe8e 	bl	8012b4c <xTimerCreateTimerTask>
+ 8011e30:	6178      	str	r0, [r7, #20]
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	#endif /* configUSE_TIMERS */
+
+	if( xReturn == pdPASS )
+ 8011e32:	697b      	ldr	r3, [r7, #20]
+ 8011e34:	2b01      	cmp	r3, #1
+ 8011e36:	d116      	bne.n	8011e66 <vTaskStartScheduler+0x8e>
+	__asm volatile
+ 8011e38:	f04f 0350 	mov.w	r3, #80	; 0x50
+ 8011e3c:	f383 8811 	msr	BASEPRI, r3
+ 8011e40:	f3bf 8f6f 	isb	sy
+ 8011e44:	f3bf 8f4f 	dsb	sy
+ 8011e48:	613b      	str	r3, [r7, #16]
+}
+ 8011e4a:	bf00      	nop
+			for additional information. */
+			_impure_ptr = &( pxCurrentTCB->xNewLib_reent );
+		}
+		#endif /* configUSE_NEWLIB_REENTRANT */
+
+		xNextTaskUnblockTime = portMAX_DELAY;
+ 8011e4c:	4b12      	ldr	r3, [pc, #72]	; (8011e98 <vTaskStartScheduler+0xc0>)
+ 8011e4e:	f04f 32ff 	mov.w	r2, #4294967295
+ 8011e52:	601a      	str	r2, [r3, #0]
+		xSchedulerRunning = pdTRUE;
+ 8011e54:	4b11      	ldr	r3, [pc, #68]	; (8011e9c <vTaskStartScheduler+0xc4>)
+ 8011e56:	2201      	movs	r2, #1
+ 8011e58:	601a      	str	r2, [r3, #0]
+		xTickCount = ( TickType_t ) configINITIAL_TICK_COUNT;
+ 8011e5a:	4b11      	ldr	r3, [pc, #68]	; (8011ea0 <vTaskStartScheduler+0xc8>)
+ 8011e5c:	2200      	movs	r2, #0
+ 8011e5e:	601a      	str	r2, [r3, #0]
+
+		traceTASK_SWITCHED_IN();
+
+		/* Setting up the timer tick is hardware specific and thus in the
+		portable interface. */
+		if( xPortStartScheduler() != pdFALSE )
+ 8011e60:	f001 fa2e 	bl	80132c0 <xPortStartScheduler>
+	}
+
+	/* Prevent compiler warnings if INCLUDE_xTaskGetIdleTaskHandle is set to 0,
+	meaning xIdleTaskHandle is not used anywhere else. */
+	( void ) xIdleTaskHandle;
+}
+ 8011e64:	e00e      	b.n	8011e84 <vTaskStartScheduler+0xac>
+		configASSERT( xReturn != errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY );
+ 8011e66:	697b      	ldr	r3, [r7, #20]
+ 8011e68:	f1b3 3fff 	cmp.w	r3, #4294967295
+ 8011e6c:	d10a      	bne.n	8011e84 <vTaskStartScheduler+0xac>
+	__asm volatile
+ 8011e6e:	f04f 0350 	mov.w	r3, #80	; 0x50
+ 8011e72:	f383 8811 	msr	BASEPRI, r3
+ 8011e76:	f3bf 8f6f 	isb	sy
+ 8011e7a:	f3bf 8f4f 	dsb	sy
+ 8011e7e:	60fb      	str	r3, [r7, #12]
+}
+ 8011e80:	bf00      	nop
+ 8011e82:	e7fe      	b.n	8011e82 <vTaskStartScheduler+0xaa>
+}
+ 8011e84:	bf00      	nop
+ 8011e86:	3718      	adds	r7, #24
+ 8011e88:	46bd      	mov	sp, r7
+ 8011e8a:	bd80      	pop	{r7, pc}
+ 8011e8c:	080232b4 	.word	0x080232b4
+ 8011e90:	080124ed 	.word	0x080124ed
+ 8011e94:	2400c044 	.word	0x2400c044
+ 8011e98:	2400c040 	.word	0x2400c040
+ 8011e9c:	2400c02c 	.word	0x2400c02c
+ 8011ea0:	2400c024 	.word	0x2400c024
+
+08011ea4 <vTaskSuspendAll>:
+	vPortEndScheduler();
+}
+/*----------------------------------------------------------*/
+
+void vTaskSuspendAll( void )
+{
+ 8011ea4:	b480      	push	{r7}
+ 8011ea6:	af00      	add	r7, sp, #0
+	do not otherwise exhibit real time behaviour. */
+	portSOFTWARE_BARRIER();
+
+	/* The scheduler is suspended if uxSchedulerSuspended is non-zero.  An increment
+	is used to allow calls to vTaskSuspendAll() to nest. */
+	++uxSchedulerSuspended;
+ 8011ea8:	4b04      	ldr	r3, [pc, #16]	; (8011ebc <vTaskSuspendAll+0x18>)
+ 8011eaa:	681b      	ldr	r3, [r3, #0]
+ 8011eac:	3301      	adds	r3, #1
+ 8011eae:	4a03      	ldr	r2, [pc, #12]	; (8011ebc <vTaskSuspendAll+0x18>)
+ 8011eb0:	6013      	str	r3, [r2, #0]
+
+	/* Enforces ordering for ports and optimised compilers that may otherwise place
+	the above increment elsewhere. */
+	portMEMORY_BARRIER();
+}
+ 8011eb2:	bf00      	nop
+ 8011eb4:	46bd      	mov	sp, r7
+ 8011eb6:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8011eba:	4770      	bx	lr
+ 8011ebc:	2400c048 	.word	0x2400c048
+
+08011ec0 <xTaskResumeAll>:
+
+#endif /* configUSE_TICKLESS_IDLE */
+/*----------------------------------------------------------*/
+
+BaseType_t xTaskResumeAll( void )
+{
+ 8011ec0:	b580      	push	{r7, lr}
+ 8011ec2:	b084      	sub	sp, #16
+ 8011ec4:	af00      	add	r7, sp, #0
+TCB_t *pxTCB = NULL;
+ 8011ec6:	2300      	movs	r3, #0
+ 8011ec8:	60fb      	str	r3, [r7, #12]
+BaseType_t xAlreadyYielded = pdFALSE;
+ 8011eca:	2300      	movs	r3, #0
+ 8011ecc:	60bb      	str	r3, [r7, #8]
+
+	/* If uxSchedulerSuspended is zero then this function does not match a
+	previous call to vTaskSuspendAll(). */
+	configASSERT( uxSchedulerSuspended );
+ 8011ece:	4b41      	ldr	r3, [pc, #260]	; (8011fd4 <xTaskResumeAll+0x114>)
+ 8011ed0:	681b      	ldr	r3, [r3, #0]
+ 8011ed2:	2b00      	cmp	r3, #0
+ 8011ed4:	d10a      	bne.n	8011eec <xTaskResumeAll+0x2c>
+	__asm volatile
+ 8011ed6:	f04f 0350 	mov.w	r3, #80	; 0x50
+ 8011eda:	f383 8811 	msr	BASEPRI, r3
+ 8011ede:	f3bf 8f6f 	isb	sy
+ 8011ee2:	f3bf 8f4f 	dsb	sy
+ 8011ee6:	603b      	str	r3, [r7, #0]
+}
+ 8011ee8:	bf00      	nop
+ 8011eea:	e7fe      	b.n	8011eea <xTaskResumeAll+0x2a>
+	/* It is possible that an ISR caused a task to be removed from an event
+	list while the scheduler was suspended.  If this was the case then the
+	removed task will have been added to the xPendingReadyList.  Once the
+	scheduler has been resumed it is safe to move all the pending ready
+	tasks from this list into their appropriate ready list. */
+	taskENTER_CRITICAL();
+ 8011eec:	f001 fa8a 	bl	8013404 <vPortEnterCritical>
+	{
+		--uxSchedulerSuspended;
+ 8011ef0:	4b38      	ldr	r3, [pc, #224]	; (8011fd4 <xTaskResumeAll+0x114>)
+ 8011ef2:	681b      	ldr	r3, [r3, #0]
+ 8011ef4:	3b01      	subs	r3, #1
+ 8011ef6:	4a37      	ldr	r2, [pc, #220]	; (8011fd4 <xTaskResumeAll+0x114>)
+ 8011ef8:	6013      	str	r3, [r2, #0]
+
+		if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
+ 8011efa:	4b36      	ldr	r3, [pc, #216]	; (8011fd4 <xTaskResumeAll+0x114>)
+ 8011efc:	681b      	ldr	r3, [r3, #0]
+ 8011efe:	2b00      	cmp	r3, #0
+ 8011f00:	d161      	bne.n	8011fc6 <xTaskResumeAll+0x106>
+		{
+			if( uxCurrentNumberOfTasks > ( UBaseType_t ) 0U )
+ 8011f02:	4b35      	ldr	r3, [pc, #212]	; (8011fd8 <xTaskResumeAll+0x118>)
+ 8011f04:	681b      	ldr	r3, [r3, #0]
+ 8011f06:	2b00      	cmp	r3, #0
+ 8011f08:	d05d      	beq.n	8011fc6 <xTaskResumeAll+0x106>
+			{
+				/* Move any readied tasks from the pending list into the
+				appropriate ready list. */
+				while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE )
+ 8011f0a:	e02e      	b.n	8011f6a <xTaskResumeAll+0xaa>
+				{
+					pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xPendingReadyList ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+ 8011f0c:	4b33      	ldr	r3, [pc, #204]	; (8011fdc <xTaskResumeAll+0x11c>)
+ 8011f0e:	68db      	ldr	r3, [r3, #12]
+ 8011f10:	68db      	ldr	r3, [r3, #12]
+ 8011f12:	60fb      	str	r3, [r7, #12]
+					( void ) uxListRemove( &( pxTCB->xEventListItem ) );
+ 8011f14:	68fb      	ldr	r3, [r7, #12]
+ 8011f16:	3318      	adds	r3, #24
+ 8011f18:	4618      	mov	r0, r3
+ 8011f1a:	f7fe fd3a 	bl	8010992 <uxListRemove>
+					( void ) uxListRemove( &( pxTCB->xStateListItem ) );
+ 8011f1e:	68fb      	ldr	r3, [r7, #12]
+ 8011f20:	3304      	adds	r3, #4
+ 8011f22:	4618      	mov	r0, r3
+ 8011f24:	f7fe fd35 	bl	8010992 <uxListRemove>
+					prvAddTaskToReadyList( pxTCB );
+ 8011f28:	68fb      	ldr	r3, [r7, #12]
+ 8011f2a:	6adb      	ldr	r3, [r3, #44]	; 0x2c
+ 8011f2c:	2201      	movs	r2, #1
+ 8011f2e:	409a      	lsls	r2, r3
+ 8011f30:	4b2b      	ldr	r3, [pc, #172]	; (8011fe0 <xTaskResumeAll+0x120>)
+ 8011f32:	681b      	ldr	r3, [r3, #0]
+ 8011f34:	4313      	orrs	r3, r2
+ 8011f36:	4a2a      	ldr	r2, [pc, #168]	; (8011fe0 <xTaskResumeAll+0x120>)
+ 8011f38:	6013      	str	r3, [r2, #0]
+ 8011f3a:	68fb      	ldr	r3, [r7, #12]
+ 8011f3c:	6ada      	ldr	r2, [r3, #44]	; 0x2c
+ 8011f3e:	4613      	mov	r3, r2
+ 8011f40:	009b      	lsls	r3, r3, #2
+ 8011f42:	4413      	add	r3, r2
+ 8011f44:	009b      	lsls	r3, r3, #2
+ 8011f46:	4a27      	ldr	r2, [pc, #156]	; (8011fe4 <xTaskResumeAll+0x124>)
+ 8011f48:	441a      	add	r2, r3
+ 8011f4a:	68fb      	ldr	r3, [r7, #12]
+ 8011f4c:	3304      	adds	r3, #4
+ 8011f4e:	4619      	mov	r1, r3
+ 8011f50:	4610      	mov	r0, r2
+ 8011f52:	f7fe fcc1 	bl	80108d8 <vListInsertEnd>
+
+					/* If the moved task has a priority higher than the current
+					task then a yield must be performed. */
+					if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )
+ 8011f56:	68fb      	ldr	r3, [r7, #12]
+ 8011f58:	6ada      	ldr	r2, [r3, #44]	; 0x2c
+ 8011f5a:	4b23      	ldr	r3, [pc, #140]	; (8011fe8 <xTaskResumeAll+0x128>)
+ 8011f5c:	681b      	ldr	r3, [r3, #0]
+ 8011f5e:	6adb      	ldr	r3, [r3, #44]	; 0x2c
+ 8011f60:	429a      	cmp	r2, r3
+ 8011f62:	d302      	bcc.n	8011f6a <xTaskResumeAll+0xaa>
+					{
+						xYieldPending = pdTRUE;
+ 8011f64:	4b21      	ldr	r3, [pc, #132]	; (8011fec <xTaskResumeAll+0x12c>)
+ 8011f66:	2201      	movs	r2, #1
+ 8011f68:	601a      	str	r2, [r3, #0]
+				while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE )
+ 8011f6a:	4b1c      	ldr	r3, [pc, #112]	; (8011fdc <xTaskResumeAll+0x11c>)
+ 8011f6c:	681b      	ldr	r3, [r3, #0]
+ 8011f6e:	2b00      	cmp	r3, #0
+ 8011f70:	d1cc      	bne.n	8011f0c <xTaskResumeAll+0x4c>
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+
+				if( pxTCB != NULL )
+ 8011f72:	68fb      	ldr	r3, [r7, #12]
+ 8011f74:	2b00      	cmp	r3, #0
+ 8011f76:	d001      	beq.n	8011f7c <xTaskResumeAll+0xbc>
+					which may have prevented the next unblock time from being
+					re-calculated, in which case re-calculate it now.  Mainly
+					important for low power tickless implementations, where
+					this can prevent an unnecessary exit from low power
+					state. */
+					prvResetNextTaskUnblockTime();
+ 8011f78:	f000 fba6 	bl	80126c8 <prvResetNextTaskUnblockTime>
+				/* If any ticks occurred while the scheduler was suspended then
+				they should be processed now.  This ensures the tick count does
+				not	slip, and that any delayed tasks are resumed at the correct
+				time. */
+				{
+					TickType_t xPendedCounts = xPendedTicks; /* Non-volatile copy. */
+ 8011f7c:	4b1c      	ldr	r3, [pc, #112]	; (8011ff0 <xTaskResumeAll+0x130>)
+ 8011f7e:	681b      	ldr	r3, [r3, #0]
+ 8011f80:	607b      	str	r3, [r7, #4]
+
+					if( xPendedCounts > ( TickType_t ) 0U )
+ 8011f82:	687b      	ldr	r3, [r7, #4]
+ 8011f84:	2b00      	cmp	r3, #0
+ 8011f86:	d010      	beq.n	8011faa <xTaskResumeAll+0xea>
+					{
+						do
+						{
+							if( xTaskIncrementTick() != pdFALSE )
+ 8011f88:	f000 f858 	bl	801203c <xTaskIncrementTick>
+ 8011f8c:	4603      	mov	r3, r0
+ 8011f8e:	2b00      	cmp	r3, #0
+ 8011f90:	d002      	beq.n	8011f98 <xTaskResumeAll+0xd8>
+							{
+								xYieldPending = pdTRUE;
+ 8011f92:	4b16      	ldr	r3, [pc, #88]	; (8011fec <xTaskResumeAll+0x12c>)
+ 8011f94:	2201      	movs	r2, #1
+ 8011f96:	601a      	str	r2, [r3, #0]
+							}
+							else
+							{
+								mtCOVERAGE_TEST_MARKER();
+							}
+							--xPendedCounts;
+ 8011f98:	687b      	ldr	r3, [r7, #4]
+ 8011f9a:	3b01      	subs	r3, #1
+ 8011f9c:	607b      	str	r3, [r7, #4]
+						} while( xPendedCounts > ( TickType_t ) 0U );
+ 8011f9e:	687b      	ldr	r3, [r7, #4]
+ 8011fa0:	2b00      	cmp	r3, #0
+ 8011fa2:	d1f1      	bne.n	8011f88 <xTaskResumeAll+0xc8>
+
+						xPendedTicks = 0;
+ 8011fa4:	4b12      	ldr	r3, [pc, #72]	; (8011ff0 <xTaskResumeAll+0x130>)
+ 8011fa6:	2200      	movs	r2, #0
+ 8011fa8:	601a      	str	r2, [r3, #0]
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+
+				if( xYieldPending != pdFALSE )
+ 8011faa:	4b10      	ldr	r3, [pc, #64]	; (8011fec <xTaskResumeAll+0x12c>)
+ 8011fac:	681b      	ldr	r3, [r3, #0]
+ 8011fae:	2b00      	cmp	r3, #0
+ 8011fb0:	d009      	beq.n	8011fc6 <xTaskResumeAll+0x106>
+				{
+					#if( configUSE_PREEMPTION != 0 )
+					{
+						xAlreadyYielded = pdTRUE;
+ 8011fb2:	2301      	movs	r3, #1
+ 8011fb4:	60bb      	str	r3, [r7, #8]
+					}
+					#endif
+					taskYIELD_IF_USING_PREEMPTION();
+ 8011fb6:	4b0f      	ldr	r3, [pc, #60]	; (8011ff4 <xTaskResumeAll+0x134>)
+ 8011fb8:	f04f 5280 	mov.w	r2, #268435456	; 0x10000000
+ 8011fbc:	601a      	str	r2, [r3, #0]
+ 8011fbe:	f3bf 8f4f 	dsb	sy
+ 8011fc2:	f3bf 8f6f 	isb	sy
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	taskEXIT_CRITICAL();
+ 8011fc6:	f001 fa4d 	bl	8013464 <vPortExitCritical>
+
+	return xAlreadyYielded;
+ 8011fca:	68bb      	ldr	r3, [r7, #8]
+}
+ 8011fcc:	4618      	mov	r0, r3
+ 8011fce:	3710      	adds	r7, #16
+ 8011fd0:	46bd      	mov	sp, r7
+ 8011fd2:	bd80      	pop	{r7, pc}
+ 8011fd4:	2400c048 	.word	0x2400c048
+ 8011fd8:	2400c020 	.word	0x2400c020
+ 8011fdc:	2400bfe0 	.word	0x2400bfe0
+ 8011fe0:	2400c028 	.word	0x2400c028
+ 8011fe4:	2400bf24 	.word	0x2400bf24
+ 8011fe8:	2400bf20 	.word	0x2400bf20
+ 8011fec:	2400c034 	.word	0x2400c034
+ 8011ff0:	2400c030 	.word	0x2400c030
+ 8011ff4:	e000ed04 	.word	0xe000ed04
+
+08011ff8 <xTaskGetTickCount>:
+/*-----------------------------------------------------------*/
+
+TickType_t xTaskGetTickCount( void )
+{
+ 8011ff8:	b480      	push	{r7}
+ 8011ffa:	b083      	sub	sp, #12
+ 8011ffc:	af00      	add	r7, sp, #0
+TickType_t xTicks;
+
+	/* Critical section required if running on a 16 bit processor. */
+	portTICK_TYPE_ENTER_CRITICAL();
+	{
+		xTicks = xTickCount;
+ 8011ffe:	4b05      	ldr	r3, [pc, #20]	; (8012014 <xTaskGetTickCount+0x1c>)
+ 8012000:	681b      	ldr	r3, [r3, #0]
+ 8012002:	607b      	str	r3, [r7, #4]
+	}
+	portTICK_TYPE_EXIT_CRITICAL();
+
+	return xTicks;
+ 8012004:	687b      	ldr	r3, [r7, #4]
+}
+ 8012006:	4618      	mov	r0, r3
+ 8012008:	370c      	adds	r7, #12
+ 801200a:	46bd      	mov	sp, r7
+ 801200c:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8012010:	4770      	bx	lr
+ 8012012:	bf00      	nop
+ 8012014:	2400c024 	.word	0x2400c024
+
+08012018 <xTaskGetTickCountFromISR>:
+/*-----------------------------------------------------------*/
+
+TickType_t xTaskGetTickCountFromISR( void )
+{
+ 8012018:	b580      	push	{r7, lr}
+ 801201a:	b082      	sub	sp, #8
+ 801201c:	af00      	add	r7, sp, #0
+	that have been assigned a priority at or (logically) below the maximum
+	system call	interrupt priority.  FreeRTOS maintains a separate interrupt
+	safe API to ensure interrupt entry is as fast and as simple as possible.
+	More information (albeit Cortex-M specific) is provided on the following
+	link: https://www.freertos.org/RTOS-Cortex-M3-M4.html */
+	portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+ 801201e:	f001 fad3 	bl	80135c8 <vPortValidateInterruptPriority>
+
+	uxSavedInterruptStatus = portTICK_TYPE_SET_INTERRUPT_MASK_FROM_ISR();
+ 8012022:	2300      	movs	r3, #0
+ 8012024:	607b      	str	r3, [r7, #4]
+	{
+		xReturn = xTickCount;
+ 8012026:	4b04      	ldr	r3, [pc, #16]	; (8012038 <xTaskGetTickCountFromISR+0x20>)
+ 8012028:	681b      	ldr	r3, [r3, #0]
+ 801202a:	603b      	str	r3, [r7, #0]
+	}
+	portTICK_TYPE_CLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+	return xReturn;
+ 801202c:	683b      	ldr	r3, [r7, #0]
+}
+ 801202e:	4618      	mov	r0, r3
+ 8012030:	3708      	adds	r7, #8
+ 8012032:	46bd      	mov	sp, r7
+ 8012034:	bd80      	pop	{r7, pc}
+ 8012036:	bf00      	nop
+ 8012038:	2400c024 	.word	0x2400c024
+
+0801203c <xTaskIncrementTick>:
+
+#endif /* INCLUDE_xTaskAbortDelay */
+/*----------------------------------------------------------*/
+
+BaseType_t xTaskIncrementTick( void )
+{
+ 801203c:	b580      	push	{r7, lr}
+ 801203e:	b086      	sub	sp, #24
+ 8012040:	af00      	add	r7, sp, #0
+TCB_t * pxTCB;
+TickType_t xItemValue;
+BaseType_t xSwitchRequired = pdFALSE;
+ 8012042:	2300      	movs	r3, #0
+ 8012044:	617b      	str	r3, [r7, #20]
+
+	/* Called by the portable layer each time a tick interrupt occurs.
+	Increments the tick then checks to see if the new tick value will cause any
+	tasks to be unblocked. */
+	traceTASK_INCREMENT_TICK( xTickCount );
+	if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
+ 8012046:	4b4e      	ldr	r3, [pc, #312]	; (8012180 <xTaskIncrementTick+0x144>)
+ 8012048:	681b      	ldr	r3, [r3, #0]
+ 801204a:	2b00      	cmp	r3, #0
+ 801204c:	f040 808e 	bne.w	801216c <xTaskIncrementTick+0x130>
+	{
+		/* Minor optimisation.  The tick count cannot change in this
+		block. */
+		const TickType_t xConstTickCount = xTickCount + ( TickType_t ) 1;
+ 8012050:	4b4c      	ldr	r3, [pc, #304]	; (8012184 <xTaskIncrementTick+0x148>)
+ 8012052:	681b      	ldr	r3, [r3, #0]
+ 8012054:	3301      	adds	r3, #1
+ 8012056:	613b      	str	r3, [r7, #16]
+
+		/* Increment the RTOS tick, switching the delayed and overflowed
+		delayed lists if it wraps to 0. */
+		xTickCount = xConstTickCount;
+ 8012058:	4a4a      	ldr	r2, [pc, #296]	; (8012184 <xTaskIncrementTick+0x148>)
+ 801205a:	693b      	ldr	r3, [r7, #16]
+ 801205c:	6013      	str	r3, [r2, #0]
+
+		if( xConstTickCount == ( TickType_t ) 0U ) /*lint !e774 'if' does not always evaluate to false as it is looking for an overflow. */
+ 801205e:	693b      	ldr	r3, [r7, #16]
+ 8012060:	2b00      	cmp	r3, #0
+ 8012062:	d120      	bne.n	80120a6 <xTaskIncrementTick+0x6a>
+		{
+			taskSWITCH_DELAYED_LISTS();
+ 8012064:	4b48      	ldr	r3, [pc, #288]	; (8012188 <xTaskIncrementTick+0x14c>)
+ 8012066:	681b      	ldr	r3, [r3, #0]
+ 8012068:	681b      	ldr	r3, [r3, #0]
+ 801206a:	2b00      	cmp	r3, #0
+ 801206c:	d00a      	beq.n	8012084 <xTaskIncrementTick+0x48>
+	__asm volatile
+ 801206e:	f04f 0350 	mov.w	r3, #80	; 0x50
+ 8012072:	f383 8811 	msr	BASEPRI, r3
+ 8012076:	f3bf 8f6f 	isb	sy
+ 801207a:	f3bf 8f4f 	dsb	sy
+ 801207e:	603b      	str	r3, [r7, #0]
+}
+ 8012080:	bf00      	nop
+ 8012082:	e7fe      	b.n	8012082 <xTaskIncrementTick+0x46>
+ 8012084:	4b40      	ldr	r3, [pc, #256]	; (8012188 <xTaskIncrementTick+0x14c>)
+ 8012086:	681b      	ldr	r3, [r3, #0]
+ 8012088:	60fb      	str	r3, [r7, #12]
+ 801208a:	4b40      	ldr	r3, [pc, #256]	; (801218c <xTaskIncrementTick+0x150>)
+ 801208c:	681b      	ldr	r3, [r3, #0]
+ 801208e:	4a3e      	ldr	r2, [pc, #248]	; (8012188 <xTaskIncrementTick+0x14c>)
+ 8012090:	6013      	str	r3, [r2, #0]
+ 8012092:	4a3e      	ldr	r2, [pc, #248]	; (801218c <xTaskIncrementTick+0x150>)
+ 8012094:	68fb      	ldr	r3, [r7, #12]
+ 8012096:	6013      	str	r3, [r2, #0]
+ 8012098:	4b3d      	ldr	r3, [pc, #244]	; (8012190 <xTaskIncrementTick+0x154>)
+ 801209a:	681b      	ldr	r3, [r3, #0]
+ 801209c:	3301      	adds	r3, #1
+ 801209e:	4a3c      	ldr	r2, [pc, #240]	; (8012190 <xTaskIncrementTick+0x154>)
+ 80120a0:	6013      	str	r3, [r2, #0]
+ 80120a2:	f000 fb11 	bl	80126c8 <prvResetNextTaskUnblockTime>
+
+		/* See if this tick has made a timeout expire.  Tasks are stored in
+		the	queue in the order of their wake time - meaning once one task
+		has been found whose block time has not expired there is no need to
+		look any further down the list. */
+		if( xConstTickCount >= xNextTaskUnblockTime )
+ 80120a6:	4b3b      	ldr	r3, [pc, #236]	; (8012194 <xTaskIncrementTick+0x158>)
+ 80120a8:	681b      	ldr	r3, [r3, #0]
+ 80120aa:	693a      	ldr	r2, [r7, #16]
+ 80120ac:	429a      	cmp	r2, r3
+ 80120ae:	d348      	bcc.n	8012142 <xTaskIncrementTick+0x106>
+		{
+			for( ;; )
+			{
+				if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE )
+ 80120b0:	4b35      	ldr	r3, [pc, #212]	; (8012188 <xTaskIncrementTick+0x14c>)
+ 80120b2:	681b      	ldr	r3, [r3, #0]
+ 80120b4:	681b      	ldr	r3, [r3, #0]
+ 80120b6:	2b00      	cmp	r3, #0
+ 80120b8:	d104      	bne.n	80120c4 <xTaskIncrementTick+0x88>
+					/* The delayed list is empty.  Set xNextTaskUnblockTime
+					to the maximum possible value so it is extremely
+					unlikely that the
+					if( xTickCount >= xNextTaskUnblockTime ) test will pass
+					next time through. */
+					xNextTaskUnblockTime = portMAX_DELAY; /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+ 80120ba:	4b36      	ldr	r3, [pc, #216]	; (8012194 <xTaskIncrementTick+0x158>)
+ 80120bc:	f04f 32ff 	mov.w	r2, #4294967295
+ 80120c0:	601a      	str	r2, [r3, #0]
+					break;
+ 80120c2:	e03e      	b.n	8012142 <xTaskIncrementTick+0x106>
+				{
+					/* The delayed list is not empty, get the value of the
+					item at the head of the delayed list.  This is the time
+					at which the task at the head of the delayed list must
+					be removed from the Blocked state. */
+					pxTCB = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+ 80120c4:	4b30      	ldr	r3, [pc, #192]	; (8012188 <xTaskIncrementTick+0x14c>)
+ 80120c6:	681b      	ldr	r3, [r3, #0]
+ 80120c8:	68db      	ldr	r3, [r3, #12]
+ 80120ca:	68db      	ldr	r3, [r3, #12]
+ 80120cc:	60bb      	str	r3, [r7, #8]
+					xItemValue = listGET_LIST_ITEM_VALUE( &( pxTCB->xStateListItem ) );
+ 80120ce:	68bb      	ldr	r3, [r7, #8]
+ 80120d0:	685b      	ldr	r3, [r3, #4]
+ 80120d2:	607b      	str	r3, [r7, #4]
+
+					if( xConstTickCount < xItemValue )
+ 80120d4:	693a      	ldr	r2, [r7, #16]
+ 80120d6:	687b      	ldr	r3, [r7, #4]
+ 80120d8:	429a      	cmp	r2, r3
+ 80120da:	d203      	bcs.n	80120e4 <xTaskIncrementTick+0xa8>
+						/* It is not time to unblock this item yet, but the
+						item value is the time at which the task at the head
+						of the blocked list must be removed from the Blocked
+						state -	so record the item value in
+						xNextTaskUnblockTime. */
+						xNextTaskUnblockTime = xItemValue;
+ 80120dc:	4a2d      	ldr	r2, [pc, #180]	; (8012194 <xTaskIncrementTick+0x158>)
+ 80120de:	687b      	ldr	r3, [r7, #4]
+ 80120e0:	6013      	str	r3, [r2, #0]
+						break; /*lint !e9011 Code structure here is deedmed easier to understand with multiple breaks. */
+ 80120e2:	e02e      	b.n	8012142 <xTaskIncrementTick+0x106>
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+
+					/* It is time to remove the item from the Blocked state. */
+					( void ) uxListRemove( &( pxTCB->xStateListItem ) );
+ 80120e4:	68bb      	ldr	r3, [r7, #8]
+ 80120e6:	3304      	adds	r3, #4
+ 80120e8:	4618      	mov	r0, r3
+ 80120ea:	f7fe fc52 	bl	8010992 <uxListRemove>
+
+					/* Is the task waiting on an event also?  If so remove
+					it from the event list. */
+					if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )
+ 80120ee:	68bb      	ldr	r3, [r7, #8]
+ 80120f0:	6a9b      	ldr	r3, [r3, #40]	; 0x28
+ 80120f2:	2b00      	cmp	r3, #0
+ 80120f4:	d004      	beq.n	8012100 <xTaskIncrementTick+0xc4>
+					{
+						( void ) uxListRemove( &( pxTCB->xEventListItem ) );
+ 80120f6:	68bb      	ldr	r3, [r7, #8]
+ 80120f8:	3318      	adds	r3, #24
+ 80120fa:	4618      	mov	r0, r3
+ 80120fc:	f7fe fc49 	bl	8010992 <uxListRemove>
+						mtCOVERAGE_TEST_MARKER();
+					}
+
+					/* Place the unblocked task into the appropriate ready
+					list. */
+					prvAddTaskToReadyList( pxTCB );
+ 8012100:	68bb      	ldr	r3, [r7, #8]
+ 8012102:	6adb      	ldr	r3, [r3, #44]	; 0x2c
+ 8012104:	2201      	movs	r2, #1
+ 8012106:	409a      	lsls	r2, r3
+ 8012108:	4b23      	ldr	r3, [pc, #140]	; (8012198 <xTaskIncrementTick+0x15c>)
+ 801210a:	681b      	ldr	r3, [r3, #0]
+ 801210c:	4313      	orrs	r3, r2
+ 801210e:	4a22      	ldr	r2, [pc, #136]	; (8012198 <xTaskIncrementTick+0x15c>)
+ 8012110:	6013      	str	r3, [r2, #0]
+ 8012112:	68bb      	ldr	r3, [r7, #8]
+ 8012114:	6ada      	ldr	r2, [r3, #44]	; 0x2c
+ 8012116:	4613      	mov	r3, r2
+ 8012118:	009b      	lsls	r3, r3, #2
+ 801211a:	4413      	add	r3, r2
+ 801211c:	009b      	lsls	r3, r3, #2
+ 801211e:	4a1f      	ldr	r2, [pc, #124]	; (801219c <xTaskIncrementTick+0x160>)
+ 8012120:	441a      	add	r2, r3
+ 8012122:	68bb      	ldr	r3, [r7, #8]
+ 8012124:	3304      	adds	r3, #4
+ 8012126:	4619      	mov	r1, r3
+ 8012128:	4610      	mov	r0, r2
+ 801212a:	f7fe fbd5 	bl	80108d8 <vListInsertEnd>
+					{
+						/* Preemption is on, but a context switch should
+						only be performed if the unblocked task has a
+						priority that is equal to or higher than the
+						currently executing task. */
+						if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )
+ 801212e:	68bb      	ldr	r3, [r7, #8]
+ 8012130:	6ada      	ldr	r2, [r3, #44]	; 0x2c
+ 8012132:	4b1b      	ldr	r3, [pc, #108]	; (80121a0 <xTaskIncrementTick+0x164>)
+ 8012134:	681b      	ldr	r3, [r3, #0]
+ 8012136:	6adb      	ldr	r3, [r3, #44]	; 0x2c
+ 8012138:	429a      	cmp	r2, r3
+ 801213a:	d3b9      	bcc.n	80120b0 <xTaskIncrementTick+0x74>
+						{
+							xSwitchRequired = pdTRUE;
+ 801213c:	2301      	movs	r3, #1
+ 801213e:	617b      	str	r3, [r7, #20]
+				if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE )
+ 8012140:	e7b6      	b.n	80120b0 <xTaskIncrementTick+0x74>
+		/* Tasks of equal priority to the currently running task will share
+		processing time (time slice) if preemption is on, and the application
+		writer has not explicitly turned time slicing off. */
+		#if ( ( configUSE_PREEMPTION == 1 ) && ( configUSE_TIME_SLICING == 1 ) )
+		{
+			if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ pxCurrentTCB->uxPriority ] ) ) > ( UBaseType_t ) 1 )
+ 8012142:	4b17      	ldr	r3, [pc, #92]	; (80121a0 <xTaskIncrementTick+0x164>)
+ 8012144:	681b      	ldr	r3, [r3, #0]
+ 8012146:	6ada      	ldr	r2, [r3, #44]	; 0x2c
+ 8012148:	4914      	ldr	r1, [pc, #80]	; (801219c <xTaskIncrementTick+0x160>)
+ 801214a:	4613      	mov	r3, r2
+ 801214c:	009b      	lsls	r3, r3, #2
+ 801214e:	4413      	add	r3, r2
+ 8012150:	009b      	lsls	r3, r3, #2
+ 8012152:	440b      	add	r3, r1
+ 8012154:	681b      	ldr	r3, [r3, #0]
+ 8012156:	2b01      	cmp	r3, #1
+ 8012158:	d901      	bls.n	801215e <xTaskIncrementTick+0x122>
+			{
+				xSwitchRequired = pdTRUE;
+ 801215a:	2301      	movs	r3, #1
+ 801215c:	617b      	str	r3, [r7, #20]
+		}
+		#endif /* configUSE_TICK_HOOK */
+
+		#if ( configUSE_PREEMPTION == 1 )
+		{
+			if( xYieldPending != pdFALSE )
+ 801215e:	4b11      	ldr	r3, [pc, #68]	; (80121a4 <xTaskIncrementTick+0x168>)
+ 8012160:	681b      	ldr	r3, [r3, #0]
+ 8012162:	2b00      	cmp	r3, #0
+ 8012164:	d007      	beq.n	8012176 <xTaskIncrementTick+0x13a>
+			{
+				xSwitchRequired = pdTRUE;
+ 8012166:	2301      	movs	r3, #1
+ 8012168:	617b      	str	r3, [r7, #20]
+ 801216a:	e004      	b.n	8012176 <xTaskIncrementTick+0x13a>
+		}
+		#endif /* configUSE_PREEMPTION */
+	}
+	else
+	{
+		++xPendedTicks;
+ 801216c:	4b0e      	ldr	r3, [pc, #56]	; (80121a8 <xTaskIncrementTick+0x16c>)
+ 801216e:	681b      	ldr	r3, [r3, #0]
+ 8012170:	3301      	adds	r3, #1
+ 8012172:	4a0d      	ldr	r2, [pc, #52]	; (80121a8 <xTaskIncrementTick+0x16c>)
+ 8012174:	6013      	str	r3, [r2, #0]
+			vApplicationTickHook();
+		}
+		#endif
+	}
+
+	return xSwitchRequired;
+ 8012176:	697b      	ldr	r3, [r7, #20]
+}
+ 8012178:	4618      	mov	r0, r3
+ 801217a:	3718      	adds	r7, #24
+ 801217c:	46bd      	mov	sp, r7
+ 801217e:	bd80      	pop	{r7, pc}
+ 8012180:	2400c048 	.word	0x2400c048
+ 8012184:	2400c024 	.word	0x2400c024
+ 8012188:	2400bfd8 	.word	0x2400bfd8
+ 801218c:	2400bfdc 	.word	0x2400bfdc
+ 8012190:	2400c038 	.word	0x2400c038
+ 8012194:	2400c040 	.word	0x2400c040
+ 8012198:	2400c028 	.word	0x2400c028
+ 801219c:	2400bf24 	.word	0x2400bf24
+ 80121a0:	2400bf20 	.word	0x2400bf20
+ 80121a4:	2400c034 	.word	0x2400c034
+ 80121a8:	2400c030 	.word	0x2400c030
+
+080121ac <vTaskSwitchContext>:
+
+#endif /* configUSE_APPLICATION_TASK_TAG */
+/*-----------------------------------------------------------*/
+
+void vTaskSwitchContext( void )
+{
+ 80121ac:	b580      	push	{r7, lr}
+ 80121ae:	b086      	sub	sp, #24
+ 80121b0:	af00      	add	r7, sp, #0
+	if( uxSchedulerSuspended != ( UBaseType_t ) pdFALSE )
+ 80121b2:	4b2e      	ldr	r3, [pc, #184]	; (801226c <vTaskSwitchContext+0xc0>)
+ 80121b4:	681b      	ldr	r3, [r3, #0]
+ 80121b6:	2b00      	cmp	r3, #0
+ 80121b8:	d003      	beq.n	80121c2 <vTaskSwitchContext+0x16>
+	{
+		/* The scheduler is currently suspended - do not allow a context
+		switch. */
+		xYieldPending = pdTRUE;
+ 80121ba:	4b2d      	ldr	r3, [pc, #180]	; (8012270 <vTaskSwitchContext+0xc4>)
+ 80121bc:	2201      	movs	r2, #1
+ 80121be:	601a      	str	r2, [r3, #0]
+			for additional information. */
+			_impure_ptr = &( pxCurrentTCB->xNewLib_reent );
+		}
+		#endif /* configUSE_NEWLIB_REENTRANT */
+	}
+}
+ 80121c0:	e050      	b.n	8012264 <vTaskSwitchContext+0xb8>
+		xYieldPending = pdFALSE;
+ 80121c2:	4b2b      	ldr	r3, [pc, #172]	; (8012270 <vTaskSwitchContext+0xc4>)
+ 80121c4:	2200      	movs	r2, #0
+ 80121c6:	601a      	str	r2, [r3, #0]
+		taskCHECK_FOR_STACK_OVERFLOW();
+ 80121c8:	4b2a      	ldr	r3, [pc, #168]	; (8012274 <vTaskSwitchContext+0xc8>)
+ 80121ca:	681b      	ldr	r3, [r3, #0]
+ 80121cc:	681a      	ldr	r2, [r3, #0]
+ 80121ce:	4b29      	ldr	r3, [pc, #164]	; (8012274 <vTaskSwitchContext+0xc8>)
+ 80121d0:	681b      	ldr	r3, [r3, #0]
+ 80121d2:	6b1b      	ldr	r3, [r3, #48]	; 0x30
+ 80121d4:	429a      	cmp	r2, r3
+ 80121d6:	d808      	bhi.n	80121ea <vTaskSwitchContext+0x3e>
+ 80121d8:	4b26      	ldr	r3, [pc, #152]	; (8012274 <vTaskSwitchContext+0xc8>)
+ 80121da:	681a      	ldr	r2, [r3, #0]
+ 80121dc:	4b25      	ldr	r3, [pc, #148]	; (8012274 <vTaskSwitchContext+0xc8>)
+ 80121de:	681b      	ldr	r3, [r3, #0]
+ 80121e0:	3334      	adds	r3, #52	; 0x34
+ 80121e2:	4619      	mov	r1, r3
+ 80121e4:	4610      	mov	r0, r2
+ 80121e6:	f7ee fa79 	bl	80006dc <vApplicationStackOverflowHook>
+		taskSELECT_HIGHEST_PRIORITY_TASK(); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+ 80121ea:	4b23      	ldr	r3, [pc, #140]	; (8012278 <vTaskSwitchContext+0xcc>)
+ 80121ec:	681b      	ldr	r3, [r3, #0]
+ 80121ee:	60fb      	str	r3, [r7, #12]
+		__asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) : "memory" );
+ 80121f0:	68fb      	ldr	r3, [r7, #12]
+ 80121f2:	fab3 f383 	clz	r3, r3
+ 80121f6:	72fb      	strb	r3, [r7, #11]
+		return ucReturn;
+ 80121f8:	7afb      	ldrb	r3, [r7, #11]
+ 80121fa:	f1c3 031f 	rsb	r3, r3, #31
+ 80121fe:	617b      	str	r3, [r7, #20]
+ 8012200:	491e      	ldr	r1, [pc, #120]	; (801227c <vTaskSwitchContext+0xd0>)
+ 8012202:	697a      	ldr	r2, [r7, #20]
+ 8012204:	4613      	mov	r3, r2
+ 8012206:	009b      	lsls	r3, r3, #2
+ 8012208:	4413      	add	r3, r2
+ 801220a:	009b      	lsls	r3, r3, #2
+ 801220c:	440b      	add	r3, r1
+ 801220e:	681b      	ldr	r3, [r3, #0]
+ 8012210:	2b00      	cmp	r3, #0
+ 8012212:	d10a      	bne.n	801222a <vTaskSwitchContext+0x7e>
+	__asm volatile
+ 8012214:	f04f 0350 	mov.w	r3, #80	; 0x50
+ 8012218:	f383 8811 	msr	BASEPRI, r3
+ 801221c:	f3bf 8f6f 	isb	sy
+ 8012220:	f3bf 8f4f 	dsb	sy
+ 8012224:	607b      	str	r3, [r7, #4]
+}
+ 8012226:	bf00      	nop
+ 8012228:	e7fe      	b.n	8012228 <vTaskSwitchContext+0x7c>
+ 801222a:	697a      	ldr	r2, [r7, #20]
+ 801222c:	4613      	mov	r3, r2
+ 801222e:	009b      	lsls	r3, r3, #2
+ 8012230:	4413      	add	r3, r2
+ 8012232:	009b      	lsls	r3, r3, #2
+ 8012234:	4a11      	ldr	r2, [pc, #68]	; (801227c <vTaskSwitchContext+0xd0>)
+ 8012236:	4413      	add	r3, r2
+ 8012238:	613b      	str	r3, [r7, #16]
+ 801223a:	693b      	ldr	r3, [r7, #16]
+ 801223c:	685b      	ldr	r3, [r3, #4]
+ 801223e:	685a      	ldr	r2, [r3, #4]
+ 8012240:	693b      	ldr	r3, [r7, #16]
+ 8012242:	605a      	str	r2, [r3, #4]
+ 8012244:	693b      	ldr	r3, [r7, #16]
+ 8012246:	685a      	ldr	r2, [r3, #4]
+ 8012248:	693b      	ldr	r3, [r7, #16]
+ 801224a:	3308      	adds	r3, #8
+ 801224c:	429a      	cmp	r2, r3
+ 801224e:	d104      	bne.n	801225a <vTaskSwitchContext+0xae>
+ 8012250:	693b      	ldr	r3, [r7, #16]
+ 8012252:	685b      	ldr	r3, [r3, #4]
+ 8012254:	685a      	ldr	r2, [r3, #4]
+ 8012256:	693b      	ldr	r3, [r7, #16]
+ 8012258:	605a      	str	r2, [r3, #4]
+ 801225a:	693b      	ldr	r3, [r7, #16]
+ 801225c:	685b      	ldr	r3, [r3, #4]
+ 801225e:	68db      	ldr	r3, [r3, #12]
+ 8012260:	4a04      	ldr	r2, [pc, #16]	; (8012274 <vTaskSwitchContext+0xc8>)
+ 8012262:	6013      	str	r3, [r2, #0]
+}
+ 8012264:	bf00      	nop
+ 8012266:	3718      	adds	r7, #24
+ 8012268:	46bd      	mov	sp, r7
+ 801226a:	bd80      	pop	{r7, pc}
+ 801226c:	2400c048 	.word	0x2400c048
+ 8012270:	2400c034 	.word	0x2400c034
+ 8012274:	2400bf20 	.word	0x2400bf20
+ 8012278:	2400c028 	.word	0x2400c028
+ 801227c:	2400bf24 	.word	0x2400bf24
+
+08012280 <vTaskPlaceOnEventList>:
+/*-----------------------------------------------------------*/
+
+void vTaskPlaceOnEventList( List_t * const pxEventList, const TickType_t xTicksToWait )
+{
+ 8012280:	b580      	push	{r7, lr}
+ 8012282:	b084      	sub	sp, #16
+ 8012284:	af00      	add	r7, sp, #0
+ 8012286:	6078      	str	r0, [r7, #4]
+ 8012288:	6039      	str	r1, [r7, #0]
+	configASSERT( pxEventList );
+ 801228a:	687b      	ldr	r3, [r7, #4]
+ 801228c:	2b00      	cmp	r3, #0
+ 801228e:	d10a      	bne.n	80122a6 <vTaskPlaceOnEventList+0x26>
+	__asm volatile
+ 8012290:	f04f 0350 	mov.w	r3, #80	; 0x50
+ 8012294:	f383 8811 	msr	BASEPRI, r3
+ 8012298:	f3bf 8f6f 	isb	sy
+ 801229c:	f3bf 8f4f 	dsb	sy
+ 80122a0:	60fb      	str	r3, [r7, #12]
+}
+ 80122a2:	bf00      	nop
+ 80122a4:	e7fe      	b.n	80122a4 <vTaskPlaceOnEventList+0x24>
+
+	/* Place the event list item of the TCB in the appropriate event list.
+	This is placed in the list in priority order so the highest priority task
+	is the first to be woken by the event.  The queue that contains the event
+	list is locked, preventing simultaneous access from interrupts. */
+	vListInsert( pxEventList, &( pxCurrentTCB->xEventListItem ) );
+ 80122a6:	4b07      	ldr	r3, [pc, #28]	; (80122c4 <vTaskPlaceOnEventList+0x44>)
+ 80122a8:	681b      	ldr	r3, [r3, #0]
+ 80122aa:	3318      	adds	r3, #24
+ 80122ac:	4619      	mov	r1, r3
+ 80122ae:	6878      	ldr	r0, [r7, #4]
+ 80122b0:	f7fe fb36 	bl	8010920 <vListInsert>
+
+	prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE );
+ 80122b4:	2101      	movs	r1, #1
+ 80122b6:	6838      	ldr	r0, [r7, #0]
+ 80122b8:	f000 fbe2 	bl	8012a80 <prvAddCurrentTaskToDelayedList>
+}
+ 80122bc:	bf00      	nop
+ 80122be:	3710      	adds	r7, #16
+ 80122c0:	46bd      	mov	sp, r7
+ 80122c2:	bd80      	pop	{r7, pc}
+ 80122c4:	2400bf20 	.word	0x2400bf20
+
+080122c8 <vTaskPlaceOnEventListRestricted>:
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TIMERS == 1 )
+
+	void vTaskPlaceOnEventListRestricted( List_t * const pxEventList, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely )
+	{
+ 80122c8:	b580      	push	{r7, lr}
+ 80122ca:	b086      	sub	sp, #24
+ 80122cc:	af00      	add	r7, sp, #0
+ 80122ce:	60f8      	str	r0, [r7, #12]
+ 80122d0:	60b9      	str	r1, [r7, #8]
+ 80122d2:	607a      	str	r2, [r7, #4]
+		configASSERT( pxEventList );
+ 80122d4:	68fb      	ldr	r3, [r7, #12]
+ 80122d6:	2b00      	cmp	r3, #0
+ 80122d8:	d10a      	bne.n	80122f0 <vTaskPlaceOnEventListRestricted+0x28>
+	__asm volatile
+ 80122da:	f04f 0350 	mov.w	r3, #80	; 0x50
+ 80122de:	f383 8811 	msr	BASEPRI, r3
+ 80122e2:	f3bf 8f6f 	isb	sy
+ 80122e6:	f3bf 8f4f 	dsb	sy
+ 80122ea:	617b      	str	r3, [r7, #20]
+}
+ 80122ec:	bf00      	nop
+ 80122ee:	e7fe      	b.n	80122ee <vTaskPlaceOnEventListRestricted+0x26>
+
+		/* Place the event list item of the TCB in the appropriate event list.
+		In this case it is assume that this is the only task that is going to
+		be waiting on this event list, so the faster vListInsertEnd() function
+		can be used in place of vListInsert. */
+		vListInsertEnd( pxEventList, &( pxCurrentTCB->xEventListItem ) );
+ 80122f0:	4b0a      	ldr	r3, [pc, #40]	; (801231c <vTaskPlaceOnEventListRestricted+0x54>)
+ 80122f2:	681b      	ldr	r3, [r3, #0]
+ 80122f4:	3318      	adds	r3, #24
+ 80122f6:	4619      	mov	r1, r3
+ 80122f8:	68f8      	ldr	r0, [r7, #12]
+ 80122fa:	f7fe faed 	bl	80108d8 <vListInsertEnd>
+
+		/* If the task should block indefinitely then set the block time to a
+		value that will be recognised as an indefinite delay inside the
+		prvAddCurrentTaskToDelayedList() function. */
+		if( xWaitIndefinitely != pdFALSE )
+ 80122fe:	687b      	ldr	r3, [r7, #4]
+ 8012300:	2b00      	cmp	r3, #0
+ 8012302:	d002      	beq.n	801230a <vTaskPlaceOnEventListRestricted+0x42>
+		{
+			xTicksToWait = portMAX_DELAY;
+ 8012304:	f04f 33ff 	mov.w	r3, #4294967295
+ 8012308:	60bb      	str	r3, [r7, #8]
+		}
+
+		traceTASK_DELAY_UNTIL( ( xTickCount + xTicksToWait ) );
+		prvAddCurrentTaskToDelayedList( xTicksToWait, xWaitIndefinitely );
+ 801230a:	6879      	ldr	r1, [r7, #4]
+ 801230c:	68b8      	ldr	r0, [r7, #8]
+ 801230e:	f000 fbb7 	bl	8012a80 <prvAddCurrentTaskToDelayedList>
+	}
+ 8012312:	bf00      	nop
+ 8012314:	3718      	adds	r7, #24
+ 8012316:	46bd      	mov	sp, r7
+ 8012318:	bd80      	pop	{r7, pc}
+ 801231a:	bf00      	nop
+ 801231c:	2400bf20 	.word	0x2400bf20
+
+08012320 <xTaskRemoveFromEventList>:
+
+#endif /* configUSE_TIMERS */
+/*-----------------------------------------------------------*/
+
+BaseType_t xTaskRemoveFromEventList( const List_t * const pxEventList )
+{
+ 8012320:	b580      	push	{r7, lr}
+ 8012322:	b086      	sub	sp, #24
+ 8012324:	af00      	add	r7, sp, #0
+ 8012326:	6078      	str	r0, [r7, #4]
+	get called - the lock count on the queue will get modified instead.  This
+	means exclusive access to the event list is guaranteed here.
+
+	This function assumes that a check has already been made to ensure that
+	pxEventList is not empty. */
+	pxUnblockedTCB = listGET_OWNER_OF_HEAD_ENTRY( pxEventList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+ 8012328:	687b      	ldr	r3, [r7, #4]
+ 801232a:	68db      	ldr	r3, [r3, #12]
+ 801232c:	68db      	ldr	r3, [r3, #12]
+ 801232e:	613b      	str	r3, [r7, #16]
+	configASSERT( pxUnblockedTCB );
+ 8012330:	693b      	ldr	r3, [r7, #16]
+ 8012332:	2b00      	cmp	r3, #0
+ 8012334:	d10a      	bne.n	801234c <xTaskRemoveFromEventList+0x2c>
+	__asm volatile
+ 8012336:	f04f 0350 	mov.w	r3, #80	; 0x50
+ 801233a:	f383 8811 	msr	BASEPRI, r3
+ 801233e:	f3bf 8f6f 	isb	sy
+ 8012342:	f3bf 8f4f 	dsb	sy
+ 8012346:	60fb      	str	r3, [r7, #12]
+}
+ 8012348:	bf00      	nop
+ 801234a:	e7fe      	b.n	801234a <xTaskRemoveFromEventList+0x2a>
+	( void ) uxListRemove( &( pxUnblockedTCB->xEventListItem ) );
+ 801234c:	693b      	ldr	r3, [r7, #16]
+ 801234e:	3318      	adds	r3, #24
+ 8012350:	4618      	mov	r0, r3
+ 8012352:	f7fe fb1e 	bl	8010992 <uxListRemove>
+
+	if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
+ 8012356:	4b1d      	ldr	r3, [pc, #116]	; (80123cc <xTaskRemoveFromEventList+0xac>)
+ 8012358:	681b      	ldr	r3, [r3, #0]
+ 801235a:	2b00      	cmp	r3, #0
+ 801235c:	d11c      	bne.n	8012398 <xTaskRemoveFromEventList+0x78>
+	{
+		( void ) uxListRemove( &( pxUnblockedTCB->xStateListItem ) );
+ 801235e:	693b      	ldr	r3, [r7, #16]
+ 8012360:	3304      	adds	r3, #4
+ 8012362:	4618      	mov	r0, r3
+ 8012364:	f7fe fb15 	bl	8010992 <uxListRemove>
+		prvAddTaskToReadyList( pxUnblockedTCB );
+ 8012368:	693b      	ldr	r3, [r7, #16]
+ 801236a:	6adb      	ldr	r3, [r3, #44]	; 0x2c
+ 801236c:	2201      	movs	r2, #1
+ 801236e:	409a      	lsls	r2, r3
+ 8012370:	4b17      	ldr	r3, [pc, #92]	; (80123d0 <xTaskRemoveFromEventList+0xb0>)
+ 8012372:	681b      	ldr	r3, [r3, #0]
+ 8012374:	4313      	orrs	r3, r2
+ 8012376:	4a16      	ldr	r2, [pc, #88]	; (80123d0 <xTaskRemoveFromEventList+0xb0>)
+ 8012378:	6013      	str	r3, [r2, #0]
+ 801237a:	693b      	ldr	r3, [r7, #16]
+ 801237c:	6ada      	ldr	r2, [r3, #44]	; 0x2c
+ 801237e:	4613      	mov	r3, r2
+ 8012380:	009b      	lsls	r3, r3, #2
+ 8012382:	4413      	add	r3, r2
+ 8012384:	009b      	lsls	r3, r3, #2
+ 8012386:	4a13      	ldr	r2, [pc, #76]	; (80123d4 <xTaskRemoveFromEventList+0xb4>)
+ 8012388:	441a      	add	r2, r3
+ 801238a:	693b      	ldr	r3, [r7, #16]
+ 801238c:	3304      	adds	r3, #4
+ 801238e:	4619      	mov	r1, r3
+ 8012390:	4610      	mov	r0, r2
+ 8012392:	f7fe faa1 	bl	80108d8 <vListInsertEnd>
+ 8012396:	e005      	b.n	80123a4 <xTaskRemoveFromEventList+0x84>
+	}
+	else
+	{
+		/* The delayed and ready lists cannot be accessed, so hold this task
+		pending until the scheduler is resumed. */
+		vListInsertEnd( &( xPendingReadyList ), &( pxUnblockedTCB->xEventListItem ) );
+ 8012398:	693b      	ldr	r3, [r7, #16]
+ 801239a:	3318      	adds	r3, #24
+ 801239c:	4619      	mov	r1, r3
+ 801239e:	480e      	ldr	r0, [pc, #56]	; (80123d8 <xTaskRemoveFromEventList+0xb8>)
+ 80123a0:	f7fe fa9a 	bl	80108d8 <vListInsertEnd>
+	}
+
+	if( pxUnblockedTCB->uxPriority > pxCurrentTCB->uxPriority )
+ 80123a4:	693b      	ldr	r3, [r7, #16]
+ 80123a6:	6ada      	ldr	r2, [r3, #44]	; 0x2c
+ 80123a8:	4b0c      	ldr	r3, [pc, #48]	; (80123dc <xTaskRemoveFromEventList+0xbc>)
+ 80123aa:	681b      	ldr	r3, [r3, #0]
+ 80123ac:	6adb      	ldr	r3, [r3, #44]	; 0x2c
+ 80123ae:	429a      	cmp	r2, r3
+ 80123b0:	d905      	bls.n	80123be <xTaskRemoveFromEventList+0x9e>
+	{
+		/* Return true if the task removed from the event list has a higher
+		priority than the calling task.  This allows the calling task to know if
+		it should force a context switch now. */
+		xReturn = pdTRUE;
+ 80123b2:	2301      	movs	r3, #1
+ 80123b4:	617b      	str	r3, [r7, #20]
+
+		/* Mark that a yield is pending in case the user is not using the
+		"xHigherPriorityTaskWoken" parameter to an ISR safe FreeRTOS function. */
+		xYieldPending = pdTRUE;
+ 80123b6:	4b0a      	ldr	r3, [pc, #40]	; (80123e0 <xTaskRemoveFromEventList+0xc0>)
+ 80123b8:	2201      	movs	r2, #1
+ 80123ba:	601a      	str	r2, [r3, #0]
+ 80123bc:	e001      	b.n	80123c2 <xTaskRemoveFromEventList+0xa2>
+	}
+	else
+	{
+		xReturn = pdFALSE;
+ 80123be:	2300      	movs	r3, #0
+ 80123c0:	617b      	str	r3, [r7, #20]
+	}
+
+	return xReturn;
+ 80123c2:	697b      	ldr	r3, [r7, #20]
+}
+ 80123c4:	4618      	mov	r0, r3
+ 80123c6:	3718      	adds	r7, #24
+ 80123c8:	46bd      	mov	sp, r7
+ 80123ca:	bd80      	pop	{r7, pc}
+ 80123cc:	2400c048 	.word	0x2400c048
+ 80123d0:	2400c028 	.word	0x2400c028
+ 80123d4:	2400bf24 	.word	0x2400bf24
+ 80123d8:	2400bfe0 	.word	0x2400bfe0
+ 80123dc:	2400bf20 	.word	0x2400bf20
+ 80123e0:	2400c034 	.word	0x2400c034
+
+080123e4 <vTaskInternalSetTimeOutState>:
+	taskEXIT_CRITICAL();
+}
+/*-----------------------------------------------------------*/
+
+void vTaskInternalSetTimeOutState( TimeOut_t * const pxTimeOut )
+{
+ 80123e4:	b480      	push	{r7}
+ 80123e6:	b083      	sub	sp, #12
+ 80123e8:	af00      	add	r7, sp, #0
+ 80123ea:	6078      	str	r0, [r7, #4]
+	/* For internal use only as it does not use a critical section. */
+	pxTimeOut->xOverflowCount = xNumOfOverflows;
+ 80123ec:	4b06      	ldr	r3, [pc, #24]	; (8012408 <vTaskInternalSetTimeOutState+0x24>)
+ 80123ee:	681a      	ldr	r2, [r3, #0]
+ 80123f0:	687b      	ldr	r3, [r7, #4]
+ 80123f2:	601a      	str	r2, [r3, #0]
+	pxTimeOut->xTimeOnEntering = xTickCount;
+ 80123f4:	4b05      	ldr	r3, [pc, #20]	; (801240c <vTaskInternalSetTimeOutState+0x28>)
+ 80123f6:	681a      	ldr	r2, [r3, #0]
+ 80123f8:	687b      	ldr	r3, [r7, #4]
+ 80123fa:	605a      	str	r2, [r3, #4]
+}
+ 80123fc:	bf00      	nop
+ 80123fe:	370c      	adds	r7, #12
+ 8012400:	46bd      	mov	sp, r7
+ 8012402:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8012406:	4770      	bx	lr
+ 8012408:	2400c038 	.word	0x2400c038
+ 801240c:	2400c024 	.word	0x2400c024
+
+08012410 <xTaskCheckForTimeOut>:
+/*-----------------------------------------------------------*/
+
+BaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait )
+{
+ 8012410:	b580      	push	{r7, lr}
+ 8012412:	b088      	sub	sp, #32
+ 8012414:	af00      	add	r7, sp, #0
+ 8012416:	6078      	str	r0, [r7, #4]
+ 8012418:	6039      	str	r1, [r7, #0]
+BaseType_t xReturn;
+
+	configASSERT( pxTimeOut );
+ 801241a:	687b      	ldr	r3, [r7, #4]
+ 801241c:	2b00      	cmp	r3, #0
+ 801241e:	d10a      	bne.n	8012436 <xTaskCheckForTimeOut+0x26>
+	__asm volatile
+ 8012420:	f04f 0350 	mov.w	r3, #80	; 0x50
+ 8012424:	f383 8811 	msr	BASEPRI, r3
+ 8012428:	f3bf 8f6f 	isb	sy
+ 801242c:	f3bf 8f4f 	dsb	sy
+ 8012430:	613b      	str	r3, [r7, #16]
+}
+ 8012432:	bf00      	nop
+ 8012434:	e7fe      	b.n	8012434 <xTaskCheckForTimeOut+0x24>
+	configASSERT( pxTicksToWait );
+ 8012436:	683b      	ldr	r3, [r7, #0]
+ 8012438:	2b00      	cmp	r3, #0
+ 801243a:	d10a      	bne.n	8012452 <xTaskCheckForTimeOut+0x42>
+	__asm volatile
+ 801243c:	f04f 0350 	mov.w	r3, #80	; 0x50
+ 8012440:	f383 8811 	msr	BASEPRI, r3
+ 8012444:	f3bf 8f6f 	isb	sy
+ 8012448:	f3bf 8f4f 	dsb	sy
+ 801244c:	60fb      	str	r3, [r7, #12]
+}
+ 801244e:	bf00      	nop
+ 8012450:	e7fe      	b.n	8012450 <xTaskCheckForTimeOut+0x40>
+
+	taskENTER_CRITICAL();
+ 8012452:	f000 ffd7 	bl	8013404 <vPortEnterCritical>
+	{
+		/* Minor optimisation.  The tick count cannot change in this block. */
+		const TickType_t xConstTickCount = xTickCount;
+ 8012456:	4b1d      	ldr	r3, [pc, #116]	; (80124cc <xTaskCheckForTimeOut+0xbc>)
+ 8012458:	681b      	ldr	r3, [r3, #0]
+ 801245a:	61bb      	str	r3, [r7, #24]
+		const TickType_t xElapsedTime = xConstTickCount - pxTimeOut->xTimeOnEntering;
+ 801245c:	687b      	ldr	r3, [r7, #4]
+ 801245e:	685b      	ldr	r3, [r3, #4]
+ 8012460:	69ba      	ldr	r2, [r7, #24]
+ 8012462:	1ad3      	subs	r3, r2, r3
+ 8012464:	617b      	str	r3, [r7, #20]
+			}
+			else
+		#endif
+
+		#if ( INCLUDE_vTaskSuspend == 1 )
+			if( *pxTicksToWait == portMAX_DELAY )
+ 8012466:	683b      	ldr	r3, [r7, #0]
+ 8012468:	681b      	ldr	r3, [r3, #0]
+ 801246a:	f1b3 3fff 	cmp.w	r3, #4294967295
+ 801246e:	d102      	bne.n	8012476 <xTaskCheckForTimeOut+0x66>
+			{
+				/* If INCLUDE_vTaskSuspend is set to 1 and the block time
+				specified is the maximum block time then the task should block
+				indefinitely, and therefore never time out. */
+				xReturn = pdFALSE;
+ 8012470:	2300      	movs	r3, #0
+ 8012472:	61fb      	str	r3, [r7, #28]
+ 8012474:	e023      	b.n	80124be <xTaskCheckForTimeOut+0xae>
+			}
+			else
+		#endif
+
+		if( ( xNumOfOverflows != pxTimeOut->xOverflowCount ) && ( xConstTickCount >= pxTimeOut->xTimeOnEntering ) ) /*lint !e525 Indentation preferred as is to make code within pre-processor directives clearer. */
+ 8012476:	687b      	ldr	r3, [r7, #4]
+ 8012478:	681a      	ldr	r2, [r3, #0]
+ 801247a:	4b15      	ldr	r3, [pc, #84]	; (80124d0 <xTaskCheckForTimeOut+0xc0>)
+ 801247c:	681b      	ldr	r3, [r3, #0]
+ 801247e:	429a      	cmp	r2, r3
+ 8012480:	d007      	beq.n	8012492 <xTaskCheckForTimeOut+0x82>
+ 8012482:	687b      	ldr	r3, [r7, #4]
+ 8012484:	685b      	ldr	r3, [r3, #4]
+ 8012486:	69ba      	ldr	r2, [r7, #24]
+ 8012488:	429a      	cmp	r2, r3
+ 801248a:	d302      	bcc.n	8012492 <xTaskCheckForTimeOut+0x82>
+			/* The tick count is greater than the time at which
+			vTaskSetTimeout() was called, but has also overflowed since
+			vTaskSetTimeOut() was called.  It must have wrapped all the way
+			around and gone past again. This passed since vTaskSetTimeout()
+			was called. */
+			xReturn = pdTRUE;
+ 801248c:	2301      	movs	r3, #1
+ 801248e:	61fb      	str	r3, [r7, #28]
+ 8012490:	e015      	b.n	80124be <xTaskCheckForTimeOut+0xae>
+		}
+		else if( xElapsedTime < *pxTicksToWait ) /*lint !e961 Explicit casting is only redundant with some compilers, whereas others require it to prevent integer conversion errors. */
+ 8012492:	683b      	ldr	r3, [r7, #0]
+ 8012494:	681b      	ldr	r3, [r3, #0]
+ 8012496:	697a      	ldr	r2, [r7, #20]
+ 8012498:	429a      	cmp	r2, r3
+ 801249a:	d20b      	bcs.n	80124b4 <xTaskCheckForTimeOut+0xa4>
+		{
+			/* Not a genuine timeout. Adjust parameters for time remaining. */
+			*pxTicksToWait -= xElapsedTime;
+ 801249c:	683b      	ldr	r3, [r7, #0]
+ 801249e:	681a      	ldr	r2, [r3, #0]
+ 80124a0:	697b      	ldr	r3, [r7, #20]
+ 80124a2:	1ad2      	subs	r2, r2, r3
+ 80124a4:	683b      	ldr	r3, [r7, #0]
+ 80124a6:	601a      	str	r2, [r3, #0]
+			vTaskInternalSetTimeOutState( pxTimeOut );
+ 80124a8:	6878      	ldr	r0, [r7, #4]
+ 80124aa:	f7ff ff9b 	bl	80123e4 <vTaskInternalSetTimeOutState>
+			xReturn = pdFALSE;
+ 80124ae:	2300      	movs	r3, #0
+ 80124b0:	61fb      	str	r3, [r7, #28]
+ 80124b2:	e004      	b.n	80124be <xTaskCheckForTimeOut+0xae>
+		}
+		else
+		{
+			*pxTicksToWait = 0;
+ 80124b4:	683b      	ldr	r3, [r7, #0]
+ 80124b6:	2200      	movs	r2, #0
+ 80124b8:	601a      	str	r2, [r3, #0]
+			xReturn = pdTRUE;
+ 80124ba:	2301      	movs	r3, #1
+ 80124bc:	61fb      	str	r3, [r7, #28]
+		}
+	}
+	taskEXIT_CRITICAL();
+ 80124be:	f000 ffd1 	bl	8013464 <vPortExitCritical>
+
+	return xReturn;
+ 80124c2:	69fb      	ldr	r3, [r7, #28]
+}
+ 80124c4:	4618      	mov	r0, r3
+ 80124c6:	3720      	adds	r7, #32
+ 80124c8:	46bd      	mov	sp, r7
+ 80124ca:	bd80      	pop	{r7, pc}
+ 80124cc:	2400c024 	.word	0x2400c024
+ 80124d0:	2400c038 	.word	0x2400c038
+
+080124d4 <vTaskMissedYield>:
+/*-----------------------------------------------------------*/
+
+void vTaskMissedYield( void )
+{
+ 80124d4:	b480      	push	{r7}
+ 80124d6:	af00      	add	r7, sp, #0
+	xYieldPending = pdTRUE;
+ 80124d8:	4b03      	ldr	r3, [pc, #12]	; (80124e8 <vTaskMissedYield+0x14>)
+ 80124da:	2201      	movs	r2, #1
+ 80124dc:	601a      	str	r2, [r3, #0]
+}
+ 80124de:	bf00      	nop
+ 80124e0:	46bd      	mov	sp, r7
+ 80124e2:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 80124e6:	4770      	bx	lr
+ 80124e8:	2400c034 	.word	0x2400c034
+
+080124ec <prvIdleTask>:
+ *
+ * void prvIdleTask( void *pvParameters );
+ *
+ */
+static portTASK_FUNCTION( prvIdleTask, pvParameters )
+{
+ 80124ec:	b580      	push	{r7, lr}
+ 80124ee:	b082      	sub	sp, #8
+ 80124f0:	af00      	add	r7, sp, #0
+ 80124f2:	6078      	str	r0, [r7, #4]
+
+	for( ;; )
+	{
+		/* See if any tasks have deleted themselves - if so then the idle task
+		is responsible for freeing the deleted task's TCB and stack. */
+		prvCheckTasksWaitingTermination();
+ 80124f4:	f000 f852 	bl	801259c <prvCheckTasksWaitingTermination>
+
+			A critical region is not required here as we are just reading from
+			the list, and an occasional incorrect value will not matter.  If
+			the ready list at the idle priority contains more than one task
+			then a task other than the idle task is ready to execute. */
+			if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > ( UBaseType_t ) 1 )
+ 80124f8:	4b06      	ldr	r3, [pc, #24]	; (8012514 <prvIdleTask+0x28>)
+ 80124fa:	681b      	ldr	r3, [r3, #0]
+ 80124fc:	2b01      	cmp	r3, #1
+ 80124fe:	d9f9      	bls.n	80124f4 <prvIdleTask+0x8>
+			{
+				taskYIELD();
+ 8012500:	4b05      	ldr	r3, [pc, #20]	; (8012518 <prvIdleTask+0x2c>)
+ 8012502:	f04f 5280 	mov.w	r2, #268435456	; 0x10000000
+ 8012506:	601a      	str	r2, [r3, #0]
+ 8012508:	f3bf 8f4f 	dsb	sy
+ 801250c:	f3bf 8f6f 	isb	sy
+		prvCheckTasksWaitingTermination();
+ 8012510:	e7f0      	b.n	80124f4 <prvIdleTask+0x8>
+ 8012512:	bf00      	nop
+ 8012514:	2400bf24 	.word	0x2400bf24
+ 8012518:	e000ed04 	.word	0xe000ed04
+
+0801251c <prvInitialiseTaskLists>:
+
+#endif /* portUSING_MPU_WRAPPERS */
+/*-----------------------------------------------------------*/
+
+static void prvInitialiseTaskLists( void )
+{
+ 801251c:	b580      	push	{r7, lr}
+ 801251e:	b082      	sub	sp, #8
+ 8012520:	af00      	add	r7, sp, #0
+UBaseType_t uxPriority;
+
+	for( uxPriority = ( UBaseType_t ) 0U; uxPriority < ( UBaseType_t ) configMAX_PRIORITIES; uxPriority++ )
+ 8012522:	2300      	movs	r3, #0
+ 8012524:	607b      	str	r3, [r7, #4]
+ 8012526:	e00c      	b.n	8012542 <prvInitialiseTaskLists+0x26>
+	{
+		vListInitialise( &( pxReadyTasksLists[ uxPriority ] ) );
+ 8012528:	687a      	ldr	r2, [r7, #4]
+ 801252a:	4613      	mov	r3, r2
+ 801252c:	009b      	lsls	r3, r3, #2
+ 801252e:	4413      	add	r3, r2
+ 8012530:	009b      	lsls	r3, r3, #2
+ 8012532:	4a12      	ldr	r2, [pc, #72]	; (801257c <prvInitialiseTaskLists+0x60>)
+ 8012534:	4413      	add	r3, r2
+ 8012536:	4618      	mov	r0, r3
+ 8012538:	f7fe f9a1 	bl	801087e <vListInitialise>
+	for( uxPriority = ( UBaseType_t ) 0U; uxPriority < ( UBaseType_t ) configMAX_PRIORITIES; uxPriority++ )
+ 801253c:	687b      	ldr	r3, [r7, #4]
+ 801253e:	3301      	adds	r3, #1
+ 8012540:	607b      	str	r3, [r7, #4]
+ 8012542:	687b      	ldr	r3, [r7, #4]
+ 8012544:	2b06      	cmp	r3, #6
+ 8012546:	d9ef      	bls.n	8012528 <prvInitialiseTaskLists+0xc>
+	}
+
+	vListInitialise( &xDelayedTaskList1 );
+ 8012548:	480d      	ldr	r0, [pc, #52]	; (8012580 <prvInitialiseTaskLists+0x64>)
+ 801254a:	f7fe f998 	bl	801087e <vListInitialise>
+	vListInitialise( &xDelayedTaskList2 );
+ 801254e:	480d      	ldr	r0, [pc, #52]	; (8012584 <prvInitialiseTaskLists+0x68>)
+ 8012550:	f7fe f995 	bl	801087e <vListInitialise>
+	vListInitialise( &xPendingReadyList );
+ 8012554:	480c      	ldr	r0, [pc, #48]	; (8012588 <prvInitialiseTaskLists+0x6c>)
+ 8012556:	f7fe f992 	bl	801087e <vListInitialise>
+
+	#if ( INCLUDE_vTaskDelete == 1 )
+	{
+		vListInitialise( &xTasksWaitingTermination );
+ 801255a:	480c      	ldr	r0, [pc, #48]	; (801258c <prvInitialiseTaskLists+0x70>)
+ 801255c:	f7fe f98f 	bl	801087e <vListInitialise>
+	}
+	#endif /* INCLUDE_vTaskDelete */
+
+	#if ( INCLUDE_vTaskSuspend == 1 )
+	{
+		vListInitialise( &xSuspendedTaskList );
+ 8012560:	480b      	ldr	r0, [pc, #44]	; (8012590 <prvInitialiseTaskLists+0x74>)
+ 8012562:	f7fe f98c 	bl	801087e <vListInitialise>
+	}
+	#endif /* INCLUDE_vTaskSuspend */
+
+	/* Start with pxDelayedTaskList using list1 and the pxOverflowDelayedTaskList
+	using list2. */
+	pxDelayedTaskList = &xDelayedTaskList1;
+ 8012566:	4b0b      	ldr	r3, [pc, #44]	; (8012594 <prvInitialiseTaskLists+0x78>)
+ 8012568:	4a05      	ldr	r2, [pc, #20]	; (8012580 <prvInitialiseTaskLists+0x64>)
+ 801256a:	601a      	str	r2, [r3, #0]
+	pxOverflowDelayedTaskList = &xDelayedTaskList2;
+ 801256c:	4b0a      	ldr	r3, [pc, #40]	; (8012598 <prvInitialiseTaskLists+0x7c>)
+ 801256e:	4a05      	ldr	r2, [pc, #20]	; (8012584 <prvInitialiseTaskLists+0x68>)
+ 8012570:	601a      	str	r2, [r3, #0]
+}
+ 8012572:	bf00      	nop
+ 8012574:	3708      	adds	r7, #8
+ 8012576:	46bd      	mov	sp, r7
+ 8012578:	bd80      	pop	{r7, pc}
+ 801257a:	bf00      	nop
+ 801257c:	2400bf24 	.word	0x2400bf24
+ 8012580:	2400bfb0 	.word	0x2400bfb0
+ 8012584:	2400bfc4 	.word	0x2400bfc4
+ 8012588:	2400bfe0 	.word	0x2400bfe0
+ 801258c:	2400bff4 	.word	0x2400bff4
+ 8012590:	2400c00c 	.word	0x2400c00c
+ 8012594:	2400bfd8 	.word	0x2400bfd8
+ 8012598:	2400bfdc 	.word	0x2400bfdc
+
+0801259c <prvCheckTasksWaitingTermination>:
+/*-----------------------------------------------------------*/
+
+static void prvCheckTasksWaitingTermination( void )
+{
+ 801259c:	b580      	push	{r7, lr}
+ 801259e:	b082      	sub	sp, #8
+ 80125a0:	af00      	add	r7, sp, #0
+	{
+		TCB_t *pxTCB;
+
+		/* uxDeletedTasksWaitingCleanUp is used to prevent taskENTER_CRITICAL()
+		being called too often in the idle task. */
+		while( uxDeletedTasksWaitingCleanUp > ( UBaseType_t ) 0U )
+ 80125a2:	e019      	b.n	80125d8 <prvCheckTasksWaitingTermination+0x3c>
+		{
+			taskENTER_CRITICAL();
+ 80125a4:	f000 ff2e 	bl	8013404 <vPortEnterCritical>
+			{
+				pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xTasksWaitingTermination ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+ 80125a8:	4b10      	ldr	r3, [pc, #64]	; (80125ec <prvCheckTasksWaitingTermination+0x50>)
+ 80125aa:	68db      	ldr	r3, [r3, #12]
+ 80125ac:	68db      	ldr	r3, [r3, #12]
+ 80125ae:	607b      	str	r3, [r7, #4]
+				( void ) uxListRemove( &( pxTCB->xStateListItem ) );
+ 80125b0:	687b      	ldr	r3, [r7, #4]
+ 80125b2:	3304      	adds	r3, #4
+ 80125b4:	4618      	mov	r0, r3
+ 80125b6:	f7fe f9ec 	bl	8010992 <uxListRemove>
+				--uxCurrentNumberOfTasks;
+ 80125ba:	4b0d      	ldr	r3, [pc, #52]	; (80125f0 <prvCheckTasksWaitingTermination+0x54>)
+ 80125bc:	681b      	ldr	r3, [r3, #0]
+ 80125be:	3b01      	subs	r3, #1
+ 80125c0:	4a0b      	ldr	r2, [pc, #44]	; (80125f0 <prvCheckTasksWaitingTermination+0x54>)
+ 80125c2:	6013      	str	r3, [r2, #0]
+				--uxDeletedTasksWaitingCleanUp;
+ 80125c4:	4b0b      	ldr	r3, [pc, #44]	; (80125f4 <prvCheckTasksWaitingTermination+0x58>)
+ 80125c6:	681b      	ldr	r3, [r3, #0]
+ 80125c8:	3b01      	subs	r3, #1
+ 80125ca:	4a0a      	ldr	r2, [pc, #40]	; (80125f4 <prvCheckTasksWaitingTermination+0x58>)
+ 80125cc:	6013      	str	r3, [r2, #0]
+			}
+			taskEXIT_CRITICAL();
+ 80125ce:	f000 ff49 	bl	8013464 <vPortExitCritical>
+
+			prvDeleteTCB( pxTCB );
+ 80125d2:	6878      	ldr	r0, [r7, #4]
+ 80125d4:	f000 f848 	bl	8012668 <prvDeleteTCB>
+		while( uxDeletedTasksWaitingCleanUp > ( UBaseType_t ) 0U )
+ 80125d8:	4b06      	ldr	r3, [pc, #24]	; (80125f4 <prvCheckTasksWaitingTermination+0x58>)
+ 80125da:	681b      	ldr	r3, [r3, #0]
+ 80125dc:	2b00      	cmp	r3, #0
+ 80125de:	d1e1      	bne.n	80125a4 <prvCheckTasksWaitingTermination+0x8>
+		}
+	}
+	#endif /* INCLUDE_vTaskDelete */
+}
+ 80125e0:	bf00      	nop
+ 80125e2:	bf00      	nop
+ 80125e4:	3708      	adds	r7, #8
+ 80125e6:	46bd      	mov	sp, r7
+ 80125e8:	bd80      	pop	{r7, pc}
+ 80125ea:	bf00      	nop
+ 80125ec:	2400bff4 	.word	0x2400bff4
+ 80125f0:	2400c020 	.word	0x2400c020
+ 80125f4:	2400c008 	.word	0x2400c008
+
+080125f8 <prvTaskCheckFreeStackSpace>:
+/*-----------------------------------------------------------*/
+
+#if ( ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) )
+
+	static configSTACK_DEPTH_TYPE prvTaskCheckFreeStackSpace( const uint8_t * pucStackByte )
+	{
+ 80125f8:	b480      	push	{r7}
+ 80125fa:	b085      	sub	sp, #20
+ 80125fc:	af00      	add	r7, sp, #0
+ 80125fe:	6078      	str	r0, [r7, #4]
+	uint32_t ulCount = 0U;
+ 8012600:	2300      	movs	r3, #0
+ 8012602:	60fb      	str	r3, [r7, #12]
+
+		while( *pucStackByte == ( uint8_t ) tskSTACK_FILL_BYTE )
+ 8012604:	e005      	b.n	8012612 <prvTaskCheckFreeStackSpace+0x1a>
+		{
+			pucStackByte -= portSTACK_GROWTH;
+ 8012606:	687b      	ldr	r3, [r7, #4]
+ 8012608:	3301      	adds	r3, #1
+ 801260a:	607b      	str	r3, [r7, #4]
+			ulCount++;
+ 801260c:	68fb      	ldr	r3, [r7, #12]
+ 801260e:	3301      	adds	r3, #1
+ 8012610:	60fb      	str	r3, [r7, #12]
+		while( *pucStackByte == ( uint8_t ) tskSTACK_FILL_BYTE )
+ 8012612:	687b      	ldr	r3, [r7, #4]
+ 8012614:	781b      	ldrb	r3, [r3, #0]
+ 8012616:	2ba5      	cmp	r3, #165	; 0xa5
+ 8012618:	d0f5      	beq.n	8012606 <prvTaskCheckFreeStackSpace+0xe>
+		}
+
+		ulCount /= ( uint32_t ) sizeof( StackType_t ); /*lint !e961 Casting is not redundant on smaller architectures. */
+ 801261a:	68fb      	ldr	r3, [r7, #12]
+ 801261c:	089b      	lsrs	r3, r3, #2
+ 801261e:	60fb      	str	r3, [r7, #12]
+
+		return ( configSTACK_DEPTH_TYPE ) ulCount;
+ 8012620:	68fb      	ldr	r3, [r7, #12]
+ 8012622:	b29b      	uxth	r3, r3
+	}
+ 8012624:	4618      	mov	r0, r3
+ 8012626:	3714      	adds	r7, #20
+ 8012628:	46bd      	mov	sp, r7
+ 801262a:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 801262e:	4770      	bx	lr
+
+08012630 <uxTaskGetStackHighWaterMark>:
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 )
+
+	UBaseType_t uxTaskGetStackHighWaterMark( TaskHandle_t xTask )
+	{
+ 8012630:	b580      	push	{r7, lr}
+ 8012632:	b086      	sub	sp, #24
+ 8012634:	af00      	add	r7, sp, #0
+ 8012636:	6078      	str	r0, [r7, #4]
+	TCB_t *pxTCB;
+	uint8_t *pucEndOfStack;
+	UBaseType_t uxReturn;
+
+		pxTCB = prvGetTCBFromHandle( xTask );
+ 8012638:	687b      	ldr	r3, [r7, #4]
+ 801263a:	2b00      	cmp	r3, #0
+ 801263c:	d102      	bne.n	8012644 <uxTaskGetStackHighWaterMark+0x14>
+ 801263e:	4b09      	ldr	r3, [pc, #36]	; (8012664 <uxTaskGetStackHighWaterMark+0x34>)
+ 8012640:	681b      	ldr	r3, [r3, #0]
+ 8012642:	e000      	b.n	8012646 <uxTaskGetStackHighWaterMark+0x16>
+ 8012644:	687b      	ldr	r3, [r7, #4]
+ 8012646:	617b      	str	r3, [r7, #20]
+
+		#if portSTACK_GROWTH < 0
+		{
+			pucEndOfStack = ( uint8_t * ) pxTCB->pxStack;
+ 8012648:	697b      	ldr	r3, [r7, #20]
+ 801264a:	6b1b      	ldr	r3, [r3, #48]	; 0x30
+ 801264c:	613b      	str	r3, [r7, #16]
+		{
+			pucEndOfStack = ( uint8_t * ) pxTCB->pxEndOfStack;
+		}
+		#endif
+
+		uxReturn = ( UBaseType_t ) prvTaskCheckFreeStackSpace( pucEndOfStack );
+ 801264e:	6938      	ldr	r0, [r7, #16]
+ 8012650:	f7ff ffd2 	bl	80125f8 <prvTaskCheckFreeStackSpace>
+ 8012654:	4603      	mov	r3, r0
+ 8012656:	60fb      	str	r3, [r7, #12]
+
+		return uxReturn;
+ 8012658:	68fb      	ldr	r3, [r7, #12]
+	}
+ 801265a:	4618      	mov	r0, r3
+ 801265c:	3718      	adds	r7, #24
+ 801265e:	46bd      	mov	sp, r7
+ 8012660:	bd80      	pop	{r7, pc}
+ 8012662:	bf00      	nop
+ 8012664:	2400bf20 	.word	0x2400bf20
+
+08012668 <prvDeleteTCB>:
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskDelete == 1 )
+
+	static void prvDeleteTCB( TCB_t *pxTCB )
+	{
+ 8012668:	b580      	push	{r7, lr}
+ 801266a:	b084      	sub	sp, #16
+ 801266c:	af00      	add	r7, sp, #0
+ 801266e:	6078      	str	r0, [r7, #4]
+		#elif( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */
+		{
+			/* The task could have been allocated statically or dynamically, so
+			check what was statically allocated before trying to free the
+			memory. */
+			if( pxTCB->ucStaticallyAllocated == tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB )
+ 8012670:	687b      	ldr	r3, [r7, #4]
+ 8012672:	f893 3051 	ldrb.w	r3, [r3, #81]	; 0x51
+ 8012676:	2b00      	cmp	r3, #0
+ 8012678:	d108      	bne.n	801268c <prvDeleteTCB+0x24>
+			{
+				/* Both the stack and TCB were allocated dynamically, so both
+				must be freed. */
+				vPortFree( pxTCB->pxStack );
+ 801267a:	687b      	ldr	r3, [r7, #4]
+ 801267c:	6b1b      	ldr	r3, [r3, #48]	; 0x30
+ 801267e:	4618      	mov	r0, r3
+ 8012680:	f001 f8ae 	bl	80137e0 <vPortFree>
+				vPortFree( pxTCB );
+ 8012684:	6878      	ldr	r0, [r7, #4]
+ 8012686:	f001 f8ab 	bl	80137e0 <vPortFree>
+				configASSERT( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_AND_TCB	);
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+	}
+ 801268a:	e018      	b.n	80126be <prvDeleteTCB+0x56>
+			else if( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_ONLY )
+ 801268c:	687b      	ldr	r3, [r7, #4]
+ 801268e:	f893 3051 	ldrb.w	r3, [r3, #81]	; 0x51
+ 8012692:	2b01      	cmp	r3, #1
+ 8012694:	d103      	bne.n	801269e <prvDeleteTCB+0x36>
+				vPortFree( pxTCB );
+ 8012696:	6878      	ldr	r0, [r7, #4]
+ 8012698:	f001 f8a2 	bl	80137e0 <vPortFree>
+	}
+ 801269c:	e00f      	b.n	80126be <prvDeleteTCB+0x56>
+				configASSERT( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_AND_TCB	);
+ 801269e:	687b      	ldr	r3, [r7, #4]
+ 80126a0:	f893 3051 	ldrb.w	r3, [r3, #81]	; 0x51
+ 80126a4:	2b02      	cmp	r3, #2
+ 80126a6:	d00a      	beq.n	80126be <prvDeleteTCB+0x56>
+	__asm volatile
+ 80126a8:	f04f 0350 	mov.w	r3, #80	; 0x50
+ 80126ac:	f383 8811 	msr	BASEPRI, r3
+ 80126b0:	f3bf 8f6f 	isb	sy
+ 80126b4:	f3bf 8f4f 	dsb	sy
+ 80126b8:	60fb      	str	r3, [r7, #12]
+}
+ 80126ba:	bf00      	nop
+ 80126bc:	e7fe      	b.n	80126bc <prvDeleteTCB+0x54>
+	}
+ 80126be:	bf00      	nop
+ 80126c0:	3710      	adds	r7, #16
+ 80126c2:	46bd      	mov	sp, r7
+ 80126c4:	bd80      	pop	{r7, pc}
+	...
+
+080126c8 <prvResetNextTaskUnblockTime>:
+
+#endif /* INCLUDE_vTaskDelete */
+/*-----------------------------------------------------------*/
+
+static void prvResetNextTaskUnblockTime( void )
+{
+ 80126c8:	b480      	push	{r7}
+ 80126ca:	b083      	sub	sp, #12
+ 80126cc:	af00      	add	r7, sp, #0
+TCB_t *pxTCB;
+
+	if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE )
+ 80126ce:	4b0c      	ldr	r3, [pc, #48]	; (8012700 <prvResetNextTaskUnblockTime+0x38>)
+ 80126d0:	681b      	ldr	r3, [r3, #0]
+ 80126d2:	681b      	ldr	r3, [r3, #0]
+ 80126d4:	2b00      	cmp	r3, #0
+ 80126d6:	d104      	bne.n	80126e2 <prvResetNextTaskUnblockTime+0x1a>
+	{
+		/* The new current delayed list is empty.  Set xNextTaskUnblockTime to
+		the maximum possible value so it is	extremely unlikely that the
+		if( xTickCount >= xNextTaskUnblockTime ) test will pass until
+		there is an item in the delayed list. */
+		xNextTaskUnblockTime = portMAX_DELAY;
+ 80126d8:	4b0a      	ldr	r3, [pc, #40]	; (8012704 <prvResetNextTaskUnblockTime+0x3c>)
+ 80126da:	f04f 32ff 	mov.w	r2, #4294967295
+ 80126de:	601a      	str	r2, [r3, #0]
+		which the task at the head of the delayed list should be removed
+		from the Blocked state. */
+		( pxTCB ) = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+		xNextTaskUnblockTime = listGET_LIST_ITEM_VALUE( &( ( pxTCB )->xStateListItem ) );
+	}
+}
+ 80126e0:	e008      	b.n	80126f4 <prvResetNextTaskUnblockTime+0x2c>
+		( pxTCB ) = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+ 80126e2:	4b07      	ldr	r3, [pc, #28]	; (8012700 <prvResetNextTaskUnblockTime+0x38>)
+ 80126e4:	681b      	ldr	r3, [r3, #0]
+ 80126e6:	68db      	ldr	r3, [r3, #12]
+ 80126e8:	68db      	ldr	r3, [r3, #12]
+ 80126ea:	607b      	str	r3, [r7, #4]
+		xNextTaskUnblockTime = listGET_LIST_ITEM_VALUE( &( ( pxTCB )->xStateListItem ) );
+ 80126ec:	687b      	ldr	r3, [r7, #4]
+ 80126ee:	685b      	ldr	r3, [r3, #4]
+ 80126f0:	4a04      	ldr	r2, [pc, #16]	; (8012704 <prvResetNextTaskUnblockTime+0x3c>)
+ 80126f2:	6013      	str	r3, [r2, #0]
+}
+ 80126f4:	bf00      	nop
+ 80126f6:	370c      	adds	r7, #12
+ 80126f8:	46bd      	mov	sp, r7
+ 80126fa:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 80126fe:	4770      	bx	lr
+ 8012700:	2400bfd8 	.word	0x2400bfd8
+ 8012704:	2400c040 	.word	0x2400c040
+
+08012708 <xTaskGetSchedulerState>:
+/*-----------------------------------------------------------*/
+
+#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
+
+	BaseType_t xTaskGetSchedulerState( void )
+	{
+ 8012708:	b480      	push	{r7}
+ 801270a:	b083      	sub	sp, #12
+ 801270c:	af00      	add	r7, sp, #0
+	BaseType_t xReturn;
+
+		if( xSchedulerRunning == pdFALSE )
+ 801270e:	4b0b      	ldr	r3, [pc, #44]	; (801273c <xTaskGetSchedulerState+0x34>)
+ 8012710:	681b      	ldr	r3, [r3, #0]
+ 8012712:	2b00      	cmp	r3, #0
+ 8012714:	d102      	bne.n	801271c <xTaskGetSchedulerState+0x14>
+		{
+			xReturn = taskSCHEDULER_NOT_STARTED;
+ 8012716:	2301      	movs	r3, #1
+ 8012718:	607b      	str	r3, [r7, #4]
+ 801271a:	e008      	b.n	801272e <xTaskGetSchedulerState+0x26>
+		}
+		else
+		{
+			if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
+ 801271c:	4b08      	ldr	r3, [pc, #32]	; (8012740 <xTaskGetSchedulerState+0x38>)
+ 801271e:	681b      	ldr	r3, [r3, #0]
+ 8012720:	2b00      	cmp	r3, #0
+ 8012722:	d102      	bne.n	801272a <xTaskGetSchedulerState+0x22>
+			{
+				xReturn = taskSCHEDULER_RUNNING;
+ 8012724:	2302      	movs	r3, #2
+ 8012726:	607b      	str	r3, [r7, #4]
+ 8012728:	e001      	b.n	801272e <xTaskGetSchedulerState+0x26>
+			}
+			else
+			{
+				xReturn = taskSCHEDULER_SUSPENDED;
+ 801272a:	2300      	movs	r3, #0
+ 801272c:	607b      	str	r3, [r7, #4]
+			}
+		}
+
+		return xReturn;
+ 801272e:	687b      	ldr	r3, [r7, #4]
+	}
+ 8012730:	4618      	mov	r0, r3
+ 8012732:	370c      	adds	r7, #12
+ 8012734:	46bd      	mov	sp, r7
+ 8012736:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 801273a:	4770      	bx	lr
+ 801273c:	2400c02c 	.word	0x2400c02c
+ 8012740:	2400c048 	.word	0x2400c048
+
+08012744 <xTaskPriorityInherit>:
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_MUTEXES == 1 )
+
+	BaseType_t xTaskPriorityInherit( TaskHandle_t const pxMutexHolder )
+	{
+ 8012744:	b580      	push	{r7, lr}
+ 8012746:	b084      	sub	sp, #16
+ 8012748:	af00      	add	r7, sp, #0
+ 801274a:	6078      	str	r0, [r7, #4]
+	TCB_t * const pxMutexHolderTCB = pxMutexHolder;
+ 801274c:	687b      	ldr	r3, [r7, #4]
+ 801274e:	60bb      	str	r3, [r7, #8]
+	BaseType_t xReturn = pdFALSE;
+ 8012750:	2300      	movs	r3, #0
+ 8012752:	60fb      	str	r3, [r7, #12]
+
+		/* If the mutex was given back by an interrupt while the queue was
+		locked then the mutex holder might now be NULL.  _RB_ Is this still
+		needed as interrupts can no longer use mutexes? */
+		if( pxMutexHolder != NULL )
+ 8012754:	687b      	ldr	r3, [r7, #4]
+ 8012756:	2b00      	cmp	r3, #0
+ 8012758:	d05e      	beq.n	8012818 <xTaskPriorityInherit+0xd4>
+		{
+			/* If the holder of the mutex has a priority below the priority of
+			the task attempting to obtain the mutex then it will temporarily
+			inherit the priority of the task attempting to obtain the mutex. */
+			if( pxMutexHolderTCB->uxPriority < pxCurrentTCB->uxPriority )
+ 801275a:	68bb      	ldr	r3, [r7, #8]
+ 801275c:	6ada      	ldr	r2, [r3, #44]	; 0x2c
+ 801275e:	4b31      	ldr	r3, [pc, #196]	; (8012824 <xTaskPriorityInherit+0xe0>)
+ 8012760:	681b      	ldr	r3, [r3, #0]
+ 8012762:	6adb      	ldr	r3, [r3, #44]	; 0x2c
+ 8012764:	429a      	cmp	r2, r3
+ 8012766:	d24e      	bcs.n	8012806 <xTaskPriorityInherit+0xc2>
+			{
+				/* Adjust the mutex holder state to account for its new
+				priority.  Only reset the event list item value if the value is
+				not being used for anything else. */
+				if( ( listGET_LIST_ITEM_VALUE( &( pxMutexHolderTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL )
+ 8012768:	68bb      	ldr	r3, [r7, #8]
+ 801276a:	699b      	ldr	r3, [r3, #24]
+ 801276c:	2b00      	cmp	r3, #0
+ 801276e:	db06      	blt.n	801277e <xTaskPriorityInherit+0x3a>
+				{
+					listSET_LIST_ITEM_VALUE( &( pxMutexHolderTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxCurrentTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+ 8012770:	4b2c      	ldr	r3, [pc, #176]	; (8012824 <xTaskPriorityInherit+0xe0>)
+ 8012772:	681b      	ldr	r3, [r3, #0]
+ 8012774:	6adb      	ldr	r3, [r3, #44]	; 0x2c
+ 8012776:	f1c3 0207 	rsb	r2, r3, #7
+ 801277a:	68bb      	ldr	r3, [r7, #8]
+ 801277c:	619a      	str	r2, [r3, #24]
+					mtCOVERAGE_TEST_MARKER();
+				}
+
+				/* If the task being modified is in the ready state it will need
+				to be moved into a new list. */
+				if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ pxMutexHolderTCB->uxPriority ] ), &( pxMutexHolderTCB->xStateListItem ) ) != pdFALSE )
+ 801277e:	68bb      	ldr	r3, [r7, #8]
+ 8012780:	6959      	ldr	r1, [r3, #20]
+ 8012782:	68bb      	ldr	r3, [r7, #8]
+ 8012784:	6ada      	ldr	r2, [r3, #44]	; 0x2c
+ 8012786:	4613      	mov	r3, r2
+ 8012788:	009b      	lsls	r3, r3, #2
+ 801278a:	4413      	add	r3, r2
+ 801278c:	009b      	lsls	r3, r3, #2
+ 801278e:	4a26      	ldr	r2, [pc, #152]	; (8012828 <xTaskPriorityInherit+0xe4>)
+ 8012790:	4413      	add	r3, r2
+ 8012792:	4299      	cmp	r1, r3
+ 8012794:	d12f      	bne.n	80127f6 <xTaskPriorityInherit+0xb2>
+				{
+					if( uxListRemove( &( pxMutexHolderTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
+ 8012796:	68bb      	ldr	r3, [r7, #8]
+ 8012798:	3304      	adds	r3, #4
+ 801279a:	4618      	mov	r0, r3
+ 801279c:	f7fe f8f9 	bl	8010992 <uxListRemove>
+ 80127a0:	4603      	mov	r3, r0
+ 80127a2:	2b00      	cmp	r3, #0
+ 80127a4:	d10a      	bne.n	80127bc <xTaskPriorityInherit+0x78>
+					{
+						/* It is known that the task is in its ready list so
+						there is no need to check again and the port level
+						reset macro can be called directly. */
+						portRESET_READY_PRIORITY( pxMutexHolderTCB->uxPriority, uxTopReadyPriority );
+ 80127a6:	68bb      	ldr	r3, [r7, #8]
+ 80127a8:	6adb      	ldr	r3, [r3, #44]	; 0x2c
+ 80127aa:	2201      	movs	r2, #1
+ 80127ac:	fa02 f303 	lsl.w	r3, r2, r3
+ 80127b0:	43da      	mvns	r2, r3
+ 80127b2:	4b1e      	ldr	r3, [pc, #120]	; (801282c <xTaskPriorityInherit+0xe8>)
+ 80127b4:	681b      	ldr	r3, [r3, #0]
+ 80127b6:	4013      	ands	r3, r2
+ 80127b8:	4a1c      	ldr	r2, [pc, #112]	; (801282c <xTaskPriorityInherit+0xe8>)
+ 80127ba:	6013      	str	r3, [r2, #0]
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+
+					/* Inherit the priority before being moved into the new list. */
+					pxMutexHolderTCB->uxPriority = pxCurrentTCB->uxPriority;
+ 80127bc:	4b19      	ldr	r3, [pc, #100]	; (8012824 <xTaskPriorityInherit+0xe0>)
+ 80127be:	681b      	ldr	r3, [r3, #0]
+ 80127c0:	6ada      	ldr	r2, [r3, #44]	; 0x2c
+ 80127c2:	68bb      	ldr	r3, [r7, #8]
+ 80127c4:	62da      	str	r2, [r3, #44]	; 0x2c
+					prvAddTaskToReadyList( pxMutexHolderTCB );
+ 80127c6:	68bb      	ldr	r3, [r7, #8]
+ 80127c8:	6adb      	ldr	r3, [r3, #44]	; 0x2c
+ 80127ca:	2201      	movs	r2, #1
+ 80127cc:	409a      	lsls	r2, r3
+ 80127ce:	4b17      	ldr	r3, [pc, #92]	; (801282c <xTaskPriorityInherit+0xe8>)
+ 80127d0:	681b      	ldr	r3, [r3, #0]
+ 80127d2:	4313      	orrs	r3, r2
+ 80127d4:	4a15      	ldr	r2, [pc, #84]	; (801282c <xTaskPriorityInherit+0xe8>)
+ 80127d6:	6013      	str	r3, [r2, #0]
+ 80127d8:	68bb      	ldr	r3, [r7, #8]
+ 80127da:	6ada      	ldr	r2, [r3, #44]	; 0x2c
+ 80127dc:	4613      	mov	r3, r2
+ 80127de:	009b      	lsls	r3, r3, #2
+ 80127e0:	4413      	add	r3, r2
+ 80127e2:	009b      	lsls	r3, r3, #2
+ 80127e4:	4a10      	ldr	r2, [pc, #64]	; (8012828 <xTaskPriorityInherit+0xe4>)
+ 80127e6:	441a      	add	r2, r3
+ 80127e8:	68bb      	ldr	r3, [r7, #8]
+ 80127ea:	3304      	adds	r3, #4
+ 80127ec:	4619      	mov	r1, r3
+ 80127ee:	4610      	mov	r0, r2
+ 80127f0:	f7fe f872 	bl	80108d8 <vListInsertEnd>
+ 80127f4:	e004      	b.n	8012800 <xTaskPriorityInherit+0xbc>
+				}
+				else
+				{
+					/* Just inherit the priority. */
+					pxMutexHolderTCB->uxPriority = pxCurrentTCB->uxPriority;
+ 80127f6:	4b0b      	ldr	r3, [pc, #44]	; (8012824 <xTaskPriorityInherit+0xe0>)
+ 80127f8:	681b      	ldr	r3, [r3, #0]
+ 80127fa:	6ada      	ldr	r2, [r3, #44]	; 0x2c
+ 80127fc:	68bb      	ldr	r3, [r7, #8]
+ 80127fe:	62da      	str	r2, [r3, #44]	; 0x2c
+				}
+
+				traceTASK_PRIORITY_INHERIT( pxMutexHolderTCB, pxCurrentTCB->uxPriority );
+
+				/* Inheritance occurred. */
+				xReturn = pdTRUE;
+ 8012800:	2301      	movs	r3, #1
+ 8012802:	60fb      	str	r3, [r7, #12]
+ 8012804:	e008      	b.n	8012818 <xTaskPriorityInherit+0xd4>
+			}
+			else
+			{
+				if( pxMutexHolderTCB->uxBasePriority < pxCurrentTCB->uxPriority )
+ 8012806:	68bb      	ldr	r3, [r7, #8]
+ 8012808:	6c5a      	ldr	r2, [r3, #68]	; 0x44
+ 801280a:	4b06      	ldr	r3, [pc, #24]	; (8012824 <xTaskPriorityInherit+0xe0>)
+ 801280c:	681b      	ldr	r3, [r3, #0]
+ 801280e:	6adb      	ldr	r3, [r3, #44]	; 0x2c
+ 8012810:	429a      	cmp	r2, r3
+ 8012812:	d201      	bcs.n	8012818 <xTaskPriorityInherit+0xd4>
+					current priority of the mutex holder is not lower than the
+					priority of the task attempting to take the mutex.
+					Therefore the mutex holder must have already inherited a
+					priority, but inheritance would have occurred if that had
+					not been the case. */
+					xReturn = pdTRUE;
+ 8012814:	2301      	movs	r3, #1
+ 8012816:	60fb      	str	r3, [r7, #12]
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		return xReturn;
+ 8012818:	68fb      	ldr	r3, [r7, #12]
+	}
+ 801281a:	4618      	mov	r0, r3
+ 801281c:	3710      	adds	r7, #16
+ 801281e:	46bd      	mov	sp, r7
+ 8012820:	bd80      	pop	{r7, pc}
+ 8012822:	bf00      	nop
+ 8012824:	2400bf20 	.word	0x2400bf20
+ 8012828:	2400bf24 	.word	0x2400bf24
+ 801282c:	2400c028 	.word	0x2400c028
+
+08012830 <xTaskPriorityDisinherit>:
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_MUTEXES == 1 )
+
+	BaseType_t xTaskPriorityDisinherit( TaskHandle_t const pxMutexHolder )
+	{
+ 8012830:	b580      	push	{r7, lr}
+ 8012832:	b086      	sub	sp, #24
+ 8012834:	af00      	add	r7, sp, #0
+ 8012836:	6078      	str	r0, [r7, #4]
+	TCB_t * const pxTCB = pxMutexHolder;
+ 8012838:	687b      	ldr	r3, [r7, #4]
+ 801283a:	613b      	str	r3, [r7, #16]
+	BaseType_t xReturn = pdFALSE;
+ 801283c:	2300      	movs	r3, #0
+ 801283e:	617b      	str	r3, [r7, #20]
+
+		if( pxMutexHolder != NULL )
+ 8012840:	687b      	ldr	r3, [r7, #4]
+ 8012842:	2b00      	cmp	r3, #0
+ 8012844:	d06e      	beq.n	8012924 <xTaskPriorityDisinherit+0xf4>
+		{
+			/* A task can only have an inherited priority if it holds the mutex.
+			If the mutex is held by a task then it cannot be given from an
+			interrupt, and if a mutex is given by the holding task then it must
+			be the running state task. */
+			configASSERT( pxTCB == pxCurrentTCB );
+ 8012846:	4b3a      	ldr	r3, [pc, #232]	; (8012930 <xTaskPriorityDisinherit+0x100>)
+ 8012848:	681b      	ldr	r3, [r3, #0]
+ 801284a:	693a      	ldr	r2, [r7, #16]
+ 801284c:	429a      	cmp	r2, r3
+ 801284e:	d00a      	beq.n	8012866 <xTaskPriorityDisinherit+0x36>
+	__asm volatile
+ 8012850:	f04f 0350 	mov.w	r3, #80	; 0x50
+ 8012854:	f383 8811 	msr	BASEPRI, r3
+ 8012858:	f3bf 8f6f 	isb	sy
+ 801285c:	f3bf 8f4f 	dsb	sy
+ 8012860:	60fb      	str	r3, [r7, #12]
+}
+ 8012862:	bf00      	nop
+ 8012864:	e7fe      	b.n	8012864 <xTaskPriorityDisinherit+0x34>
+			configASSERT( pxTCB->uxMutexesHeld );
+ 8012866:	693b      	ldr	r3, [r7, #16]
+ 8012868:	6c9b      	ldr	r3, [r3, #72]	; 0x48
+ 801286a:	2b00      	cmp	r3, #0
+ 801286c:	d10a      	bne.n	8012884 <xTaskPriorityDisinherit+0x54>
+	__asm volatile
+ 801286e:	f04f 0350 	mov.w	r3, #80	; 0x50
+ 8012872:	f383 8811 	msr	BASEPRI, r3
+ 8012876:	f3bf 8f6f 	isb	sy
+ 801287a:	f3bf 8f4f 	dsb	sy
+ 801287e:	60bb      	str	r3, [r7, #8]
+}
+ 8012880:	bf00      	nop
+ 8012882:	e7fe      	b.n	8012882 <xTaskPriorityDisinherit+0x52>
+			( pxTCB->uxMutexesHeld )--;
+ 8012884:	693b      	ldr	r3, [r7, #16]
+ 8012886:	6c9b      	ldr	r3, [r3, #72]	; 0x48
+ 8012888:	1e5a      	subs	r2, r3, #1
+ 801288a:	693b      	ldr	r3, [r7, #16]
+ 801288c:	649a      	str	r2, [r3, #72]	; 0x48
+
+			/* Has the holder of the mutex inherited the priority of another
+			task? */
+			if( pxTCB->uxPriority != pxTCB->uxBasePriority )
+ 801288e:	693b      	ldr	r3, [r7, #16]
+ 8012890:	6ada      	ldr	r2, [r3, #44]	; 0x2c
+ 8012892:	693b      	ldr	r3, [r7, #16]
+ 8012894:	6c5b      	ldr	r3, [r3, #68]	; 0x44
+ 8012896:	429a      	cmp	r2, r3
+ 8012898:	d044      	beq.n	8012924 <xTaskPriorityDisinherit+0xf4>
+			{
+				/* Only disinherit if no other mutexes are held. */
+				if( pxTCB->uxMutexesHeld == ( UBaseType_t ) 0 )
+ 801289a:	693b      	ldr	r3, [r7, #16]
+ 801289c:	6c9b      	ldr	r3, [r3, #72]	; 0x48
+ 801289e:	2b00      	cmp	r3, #0
+ 80128a0:	d140      	bne.n	8012924 <xTaskPriorityDisinherit+0xf4>
+					/* A task can only have an inherited priority if it holds
+					the mutex.  If the mutex is held by a task then it cannot be
+					given from an interrupt, and if a mutex is given by the
+					holding task then it must be the running state task.  Remove
+					the holding task from the ready/delayed list. */
+					if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
+ 80128a2:	693b      	ldr	r3, [r7, #16]
+ 80128a4:	3304      	adds	r3, #4
+ 80128a6:	4618      	mov	r0, r3
+ 80128a8:	f7fe f873 	bl	8010992 <uxListRemove>
+ 80128ac:	4603      	mov	r3, r0
+ 80128ae:	2b00      	cmp	r3, #0
+ 80128b0:	d115      	bne.n	80128de <xTaskPriorityDisinherit+0xae>
+					{
+						taskRESET_READY_PRIORITY( pxTCB->uxPriority );
+ 80128b2:	693b      	ldr	r3, [r7, #16]
+ 80128b4:	6ada      	ldr	r2, [r3, #44]	; 0x2c
+ 80128b6:	491f      	ldr	r1, [pc, #124]	; (8012934 <xTaskPriorityDisinherit+0x104>)
+ 80128b8:	4613      	mov	r3, r2
+ 80128ba:	009b      	lsls	r3, r3, #2
+ 80128bc:	4413      	add	r3, r2
+ 80128be:	009b      	lsls	r3, r3, #2
+ 80128c0:	440b      	add	r3, r1
+ 80128c2:	681b      	ldr	r3, [r3, #0]
+ 80128c4:	2b00      	cmp	r3, #0
+ 80128c6:	d10a      	bne.n	80128de <xTaskPriorityDisinherit+0xae>
+ 80128c8:	693b      	ldr	r3, [r7, #16]
+ 80128ca:	6adb      	ldr	r3, [r3, #44]	; 0x2c
+ 80128cc:	2201      	movs	r2, #1
+ 80128ce:	fa02 f303 	lsl.w	r3, r2, r3
+ 80128d2:	43da      	mvns	r2, r3
+ 80128d4:	4b18      	ldr	r3, [pc, #96]	; (8012938 <xTaskPriorityDisinherit+0x108>)
+ 80128d6:	681b      	ldr	r3, [r3, #0]
+ 80128d8:	4013      	ands	r3, r2
+ 80128da:	4a17      	ldr	r2, [pc, #92]	; (8012938 <xTaskPriorityDisinherit+0x108>)
+ 80128dc:	6013      	str	r3, [r2, #0]
+					}
+
+					/* Disinherit the priority before adding the task into the
+					new	ready list. */
+					traceTASK_PRIORITY_DISINHERIT( pxTCB, pxTCB->uxBasePriority );
+					pxTCB->uxPriority = pxTCB->uxBasePriority;
+ 80128de:	693b      	ldr	r3, [r7, #16]
+ 80128e0:	6c5a      	ldr	r2, [r3, #68]	; 0x44
+ 80128e2:	693b      	ldr	r3, [r7, #16]
+ 80128e4:	62da      	str	r2, [r3, #44]	; 0x2c
+
+					/* Reset the event list item value.  It cannot be in use for
+					any other purpose if this task is running, and it must be
+					running to give back the mutex. */
+					listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+ 80128e6:	693b      	ldr	r3, [r7, #16]
+ 80128e8:	6adb      	ldr	r3, [r3, #44]	; 0x2c
+ 80128ea:	f1c3 0207 	rsb	r2, r3, #7
+ 80128ee:	693b      	ldr	r3, [r7, #16]
+ 80128f0:	619a      	str	r2, [r3, #24]
+					prvAddTaskToReadyList( pxTCB );
+ 80128f2:	693b      	ldr	r3, [r7, #16]
+ 80128f4:	6adb      	ldr	r3, [r3, #44]	; 0x2c
+ 80128f6:	2201      	movs	r2, #1
+ 80128f8:	409a      	lsls	r2, r3
+ 80128fa:	4b0f      	ldr	r3, [pc, #60]	; (8012938 <xTaskPriorityDisinherit+0x108>)
+ 80128fc:	681b      	ldr	r3, [r3, #0]
+ 80128fe:	4313      	orrs	r3, r2
+ 8012900:	4a0d      	ldr	r2, [pc, #52]	; (8012938 <xTaskPriorityDisinherit+0x108>)
+ 8012902:	6013      	str	r3, [r2, #0]
+ 8012904:	693b      	ldr	r3, [r7, #16]
+ 8012906:	6ada      	ldr	r2, [r3, #44]	; 0x2c
+ 8012908:	4613      	mov	r3, r2
+ 801290a:	009b      	lsls	r3, r3, #2
+ 801290c:	4413      	add	r3, r2
+ 801290e:	009b      	lsls	r3, r3, #2
+ 8012910:	4a08      	ldr	r2, [pc, #32]	; (8012934 <xTaskPriorityDisinherit+0x104>)
+ 8012912:	441a      	add	r2, r3
+ 8012914:	693b      	ldr	r3, [r7, #16]
+ 8012916:	3304      	adds	r3, #4
+ 8012918:	4619      	mov	r1, r3
+ 801291a:	4610      	mov	r0, r2
+ 801291c:	f7fd ffdc 	bl	80108d8 <vListInsertEnd>
+					in an order different to that in which they were taken.
+					If a context switch did not occur when the first mutex was
+					returned, even if a task was waiting on it, then a context
+					switch should occur when the last mutex is returned whether
+					a task is waiting on it or not. */
+					xReturn = pdTRUE;
+ 8012920:	2301      	movs	r3, #1
+ 8012922:	617b      	str	r3, [r7, #20]
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		return xReturn;
+ 8012924:	697b      	ldr	r3, [r7, #20]
+	}
+ 8012926:	4618      	mov	r0, r3
+ 8012928:	3718      	adds	r7, #24
+ 801292a:	46bd      	mov	sp, r7
+ 801292c:	bd80      	pop	{r7, pc}
+ 801292e:	bf00      	nop
+ 8012930:	2400bf20 	.word	0x2400bf20
+ 8012934:	2400bf24 	.word	0x2400bf24
+ 8012938:	2400c028 	.word	0x2400c028
+
+0801293c <vTaskPriorityDisinheritAfterTimeout>:
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_MUTEXES == 1 )
+
+	void vTaskPriorityDisinheritAfterTimeout( TaskHandle_t const pxMutexHolder, UBaseType_t uxHighestPriorityWaitingTask )
+	{
+ 801293c:	b580      	push	{r7, lr}
+ 801293e:	b088      	sub	sp, #32
+ 8012940:	af00      	add	r7, sp, #0
+ 8012942:	6078      	str	r0, [r7, #4]
+ 8012944:	6039      	str	r1, [r7, #0]
+	TCB_t * const pxTCB = pxMutexHolder;
+ 8012946:	687b      	ldr	r3, [r7, #4]
+ 8012948:	61bb      	str	r3, [r7, #24]
+	UBaseType_t uxPriorityUsedOnEntry, uxPriorityToUse;
+	const UBaseType_t uxOnlyOneMutexHeld = ( UBaseType_t ) 1;
+ 801294a:	2301      	movs	r3, #1
+ 801294c:	617b      	str	r3, [r7, #20]
+
+		if( pxMutexHolder != NULL )
+ 801294e:	687b      	ldr	r3, [r7, #4]
+ 8012950:	2b00      	cmp	r3, #0
+ 8012952:	d077      	beq.n	8012a44 <vTaskPriorityDisinheritAfterTimeout+0x108>
+		{
+			/* If pxMutexHolder is not NULL then the holder must hold at least
+			one mutex. */
+			configASSERT( pxTCB->uxMutexesHeld );
+ 8012954:	69bb      	ldr	r3, [r7, #24]
+ 8012956:	6c9b      	ldr	r3, [r3, #72]	; 0x48
+ 8012958:	2b00      	cmp	r3, #0
+ 801295a:	d10a      	bne.n	8012972 <vTaskPriorityDisinheritAfterTimeout+0x36>
+	__asm volatile
+ 801295c:	f04f 0350 	mov.w	r3, #80	; 0x50
+ 8012960:	f383 8811 	msr	BASEPRI, r3
+ 8012964:	f3bf 8f6f 	isb	sy
+ 8012968:	f3bf 8f4f 	dsb	sy
+ 801296c:	60fb      	str	r3, [r7, #12]
+}
+ 801296e:	bf00      	nop
+ 8012970:	e7fe      	b.n	8012970 <vTaskPriorityDisinheritAfterTimeout+0x34>
+
+			/* Determine the priority to which the priority of the task that
+			holds the mutex should be set.  This will be the greater of the
+			holding task's base priority and the priority of the highest
+			priority task that is waiting to obtain the mutex. */
+			if( pxTCB->uxBasePriority < uxHighestPriorityWaitingTask )
+ 8012972:	69bb      	ldr	r3, [r7, #24]
+ 8012974:	6c5b      	ldr	r3, [r3, #68]	; 0x44
+ 8012976:	683a      	ldr	r2, [r7, #0]
+ 8012978:	429a      	cmp	r2, r3
+ 801297a:	d902      	bls.n	8012982 <vTaskPriorityDisinheritAfterTimeout+0x46>
+			{
+				uxPriorityToUse = uxHighestPriorityWaitingTask;
+ 801297c:	683b      	ldr	r3, [r7, #0]
+ 801297e:	61fb      	str	r3, [r7, #28]
+ 8012980:	e002      	b.n	8012988 <vTaskPriorityDisinheritAfterTimeout+0x4c>
+			}
+			else
+			{
+				uxPriorityToUse = pxTCB->uxBasePriority;
+ 8012982:	69bb      	ldr	r3, [r7, #24]
+ 8012984:	6c5b      	ldr	r3, [r3, #68]	; 0x44
+ 8012986:	61fb      	str	r3, [r7, #28]
+			}
+
+			/* Does the priority need to change? */
+			if( pxTCB->uxPriority != uxPriorityToUse )
+ 8012988:	69bb      	ldr	r3, [r7, #24]
+ 801298a:	6adb      	ldr	r3, [r3, #44]	; 0x2c
+ 801298c:	69fa      	ldr	r2, [r7, #28]
+ 801298e:	429a      	cmp	r2, r3
+ 8012990:	d058      	beq.n	8012a44 <vTaskPriorityDisinheritAfterTimeout+0x108>
+			{
+				/* Only disinherit if no other mutexes are held.  This is a
+				simplification in the priority inheritance implementation.  If
+				the task that holds the mutex is also holding other mutexes then
+				the other mutexes may have caused the priority inheritance. */
+				if( pxTCB->uxMutexesHeld == uxOnlyOneMutexHeld )
+ 8012992:	69bb      	ldr	r3, [r7, #24]
+ 8012994:	6c9b      	ldr	r3, [r3, #72]	; 0x48
+ 8012996:	697a      	ldr	r2, [r7, #20]
+ 8012998:	429a      	cmp	r2, r3
+ 801299a:	d153      	bne.n	8012a44 <vTaskPriorityDisinheritAfterTimeout+0x108>
+				{
+					/* If a task has timed out because it already holds the
+					mutex it was trying to obtain then it cannot of inherited
+					its own priority. */
+					configASSERT( pxTCB != pxCurrentTCB );
+ 801299c:	4b2b      	ldr	r3, [pc, #172]	; (8012a4c <vTaskPriorityDisinheritAfterTimeout+0x110>)
+ 801299e:	681b      	ldr	r3, [r3, #0]
+ 80129a0:	69ba      	ldr	r2, [r7, #24]
+ 80129a2:	429a      	cmp	r2, r3
+ 80129a4:	d10a      	bne.n	80129bc <vTaskPriorityDisinheritAfterTimeout+0x80>
+	__asm volatile
+ 80129a6:	f04f 0350 	mov.w	r3, #80	; 0x50
+ 80129aa:	f383 8811 	msr	BASEPRI, r3
+ 80129ae:	f3bf 8f6f 	isb	sy
+ 80129b2:	f3bf 8f4f 	dsb	sy
+ 80129b6:	60bb      	str	r3, [r7, #8]
+}
+ 80129b8:	bf00      	nop
+ 80129ba:	e7fe      	b.n	80129ba <vTaskPriorityDisinheritAfterTimeout+0x7e>
+
+					/* Disinherit the priority, remembering the previous
+					priority to facilitate determining the subject task's
+					state. */
+					traceTASK_PRIORITY_DISINHERIT( pxTCB, pxTCB->uxBasePriority );
+					uxPriorityUsedOnEntry = pxTCB->uxPriority;
+ 80129bc:	69bb      	ldr	r3, [r7, #24]
+ 80129be:	6adb      	ldr	r3, [r3, #44]	; 0x2c
+ 80129c0:	613b      	str	r3, [r7, #16]
+					pxTCB->uxPriority = uxPriorityToUse;
+ 80129c2:	69bb      	ldr	r3, [r7, #24]
+ 80129c4:	69fa      	ldr	r2, [r7, #28]
+ 80129c6:	62da      	str	r2, [r3, #44]	; 0x2c
+
+					/* Only reset the event list item value if the value is not
+					being used for anything else. */
+					if( ( listGET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL )
+ 80129c8:	69bb      	ldr	r3, [r7, #24]
+ 80129ca:	699b      	ldr	r3, [r3, #24]
+ 80129cc:	2b00      	cmp	r3, #0
+ 80129ce:	db04      	blt.n	80129da <vTaskPriorityDisinheritAfterTimeout+0x9e>
+					{
+						listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriorityToUse ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+ 80129d0:	69fb      	ldr	r3, [r7, #28]
+ 80129d2:	f1c3 0207 	rsb	r2, r3, #7
+ 80129d6:	69bb      	ldr	r3, [r7, #24]
+ 80129d8:	619a      	str	r2, [r3, #24]
+					then the task that holds the mutex could be in either the
+					Ready, Blocked or Suspended states.  Only remove the task
+					from its current state list if it is in the Ready state as
+					the task's priority is going to change and there is one
+					Ready list per priority. */
+					if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ uxPriorityUsedOnEntry ] ), &( pxTCB->xStateListItem ) ) != pdFALSE )
+ 80129da:	69bb      	ldr	r3, [r7, #24]
+ 80129dc:	6959      	ldr	r1, [r3, #20]
+ 80129de:	693a      	ldr	r2, [r7, #16]
+ 80129e0:	4613      	mov	r3, r2
+ 80129e2:	009b      	lsls	r3, r3, #2
+ 80129e4:	4413      	add	r3, r2
+ 80129e6:	009b      	lsls	r3, r3, #2
+ 80129e8:	4a19      	ldr	r2, [pc, #100]	; (8012a50 <vTaskPriorityDisinheritAfterTimeout+0x114>)
+ 80129ea:	4413      	add	r3, r2
+ 80129ec:	4299      	cmp	r1, r3
+ 80129ee:	d129      	bne.n	8012a44 <vTaskPriorityDisinheritAfterTimeout+0x108>
+					{
+						if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
+ 80129f0:	69bb      	ldr	r3, [r7, #24]
+ 80129f2:	3304      	adds	r3, #4
+ 80129f4:	4618      	mov	r0, r3
+ 80129f6:	f7fd ffcc 	bl	8010992 <uxListRemove>
+ 80129fa:	4603      	mov	r3, r0
+ 80129fc:	2b00      	cmp	r3, #0
+ 80129fe:	d10a      	bne.n	8012a16 <vTaskPriorityDisinheritAfterTimeout+0xda>
+						{
+							/* It is known that the task is in its ready list so
+							there is no need to check again and the port level
+							reset macro can be called directly. */
+							portRESET_READY_PRIORITY( pxTCB->uxPriority, uxTopReadyPriority );
+ 8012a00:	69bb      	ldr	r3, [r7, #24]
+ 8012a02:	6adb      	ldr	r3, [r3, #44]	; 0x2c
+ 8012a04:	2201      	movs	r2, #1
+ 8012a06:	fa02 f303 	lsl.w	r3, r2, r3
+ 8012a0a:	43da      	mvns	r2, r3
+ 8012a0c:	4b11      	ldr	r3, [pc, #68]	; (8012a54 <vTaskPriorityDisinheritAfterTimeout+0x118>)
+ 8012a0e:	681b      	ldr	r3, [r3, #0]
+ 8012a10:	4013      	ands	r3, r2
+ 8012a12:	4a10      	ldr	r2, [pc, #64]	; (8012a54 <vTaskPriorityDisinheritAfterTimeout+0x118>)
+ 8012a14:	6013      	str	r3, [r2, #0]
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+
+						prvAddTaskToReadyList( pxTCB );
+ 8012a16:	69bb      	ldr	r3, [r7, #24]
+ 8012a18:	6adb      	ldr	r3, [r3, #44]	; 0x2c
+ 8012a1a:	2201      	movs	r2, #1
+ 8012a1c:	409a      	lsls	r2, r3
+ 8012a1e:	4b0d      	ldr	r3, [pc, #52]	; (8012a54 <vTaskPriorityDisinheritAfterTimeout+0x118>)
+ 8012a20:	681b      	ldr	r3, [r3, #0]
+ 8012a22:	4313      	orrs	r3, r2
+ 8012a24:	4a0b      	ldr	r2, [pc, #44]	; (8012a54 <vTaskPriorityDisinheritAfterTimeout+0x118>)
+ 8012a26:	6013      	str	r3, [r2, #0]
+ 8012a28:	69bb      	ldr	r3, [r7, #24]
+ 8012a2a:	6ada      	ldr	r2, [r3, #44]	; 0x2c
+ 8012a2c:	4613      	mov	r3, r2
+ 8012a2e:	009b      	lsls	r3, r3, #2
+ 8012a30:	4413      	add	r3, r2
+ 8012a32:	009b      	lsls	r3, r3, #2
+ 8012a34:	4a06      	ldr	r2, [pc, #24]	; (8012a50 <vTaskPriorityDisinheritAfterTimeout+0x114>)
+ 8012a36:	441a      	add	r2, r3
+ 8012a38:	69bb      	ldr	r3, [r7, #24]
+ 8012a3a:	3304      	adds	r3, #4
+ 8012a3c:	4619      	mov	r1, r3
+ 8012a3e:	4610      	mov	r0, r2
+ 8012a40:	f7fd ff4a 	bl	80108d8 <vListInsertEnd>
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+ 8012a44:	bf00      	nop
+ 8012a46:	3720      	adds	r7, #32
+ 8012a48:	46bd      	mov	sp, r7
+ 8012a4a:	bd80      	pop	{r7, pc}
+ 8012a4c:	2400bf20 	.word	0x2400bf20
+ 8012a50:	2400bf24 	.word	0x2400bf24
+ 8012a54:	2400c028 	.word	0x2400c028
+
+08012a58 <pvTaskIncrementMutexHeldCount>:
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_MUTEXES == 1 )
+
+	TaskHandle_t pvTaskIncrementMutexHeldCount( void )
+	{
+ 8012a58:	b480      	push	{r7}
+ 8012a5a:	af00      	add	r7, sp, #0
+		/* If xSemaphoreCreateMutex() is called before any tasks have been created
+		then pxCurrentTCB will be NULL. */
+		if( pxCurrentTCB != NULL )
+ 8012a5c:	4b07      	ldr	r3, [pc, #28]	; (8012a7c <pvTaskIncrementMutexHeldCount+0x24>)
+ 8012a5e:	681b      	ldr	r3, [r3, #0]
+ 8012a60:	2b00      	cmp	r3, #0
+ 8012a62:	d004      	beq.n	8012a6e <pvTaskIncrementMutexHeldCount+0x16>
+		{
+			( pxCurrentTCB->uxMutexesHeld )++;
+ 8012a64:	4b05      	ldr	r3, [pc, #20]	; (8012a7c <pvTaskIncrementMutexHeldCount+0x24>)
+ 8012a66:	681b      	ldr	r3, [r3, #0]
+ 8012a68:	6c9a      	ldr	r2, [r3, #72]	; 0x48
+ 8012a6a:	3201      	adds	r2, #1
+ 8012a6c:	649a      	str	r2, [r3, #72]	; 0x48
+		}
+
+		return pxCurrentTCB;
+ 8012a6e:	4b03      	ldr	r3, [pc, #12]	; (8012a7c <pvTaskIncrementMutexHeldCount+0x24>)
+ 8012a70:	681b      	ldr	r3, [r3, #0]
+	}
+ 8012a72:	4618      	mov	r0, r3
+ 8012a74:	46bd      	mov	sp, r7
+ 8012a76:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8012a7a:	4770      	bx	lr
+ 8012a7c:	2400bf20 	.word	0x2400bf20
+
+08012a80 <prvAddCurrentTaskToDelayedList>:
+
+#endif
+/*-----------------------------------------------------------*/
+
+static void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait, const BaseType_t xCanBlockIndefinitely )
+{
+ 8012a80:	b580      	push	{r7, lr}
+ 8012a82:	b084      	sub	sp, #16
+ 8012a84:	af00      	add	r7, sp, #0
+ 8012a86:	6078      	str	r0, [r7, #4]
+ 8012a88:	6039      	str	r1, [r7, #0]
+TickType_t xTimeToWake;
+const TickType_t xConstTickCount = xTickCount;
+ 8012a8a:	4b29      	ldr	r3, [pc, #164]	; (8012b30 <prvAddCurrentTaskToDelayedList+0xb0>)
+ 8012a8c:	681b      	ldr	r3, [r3, #0]
+ 8012a8e:	60fb      	str	r3, [r7, #12]
+	}
+	#endif
+
+	/* Remove the task from the ready list before adding it to the blocked list
+	as the same list item is used for both lists. */
+	if( uxListRemove( &( pxCurrentTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
+ 8012a90:	4b28      	ldr	r3, [pc, #160]	; (8012b34 <prvAddCurrentTaskToDelayedList+0xb4>)
+ 8012a92:	681b      	ldr	r3, [r3, #0]
+ 8012a94:	3304      	adds	r3, #4
+ 8012a96:	4618      	mov	r0, r3
+ 8012a98:	f7fd ff7b 	bl	8010992 <uxListRemove>
+ 8012a9c:	4603      	mov	r3, r0
+ 8012a9e:	2b00      	cmp	r3, #0
+ 8012aa0:	d10b      	bne.n	8012aba <prvAddCurrentTaskToDelayedList+0x3a>
+	{
+		/* The current task must be in a ready list, so there is no need to
+		check, and the port reset macro can be called directly. */
+		portRESET_READY_PRIORITY( pxCurrentTCB->uxPriority, uxTopReadyPriority ); /*lint !e931 pxCurrentTCB cannot change as it is the calling task.  pxCurrentTCB->uxPriority and uxTopReadyPriority cannot change as called with scheduler suspended or in a critical section. */
+ 8012aa2:	4b24      	ldr	r3, [pc, #144]	; (8012b34 <prvAddCurrentTaskToDelayedList+0xb4>)
+ 8012aa4:	681b      	ldr	r3, [r3, #0]
+ 8012aa6:	6adb      	ldr	r3, [r3, #44]	; 0x2c
+ 8012aa8:	2201      	movs	r2, #1
+ 8012aaa:	fa02 f303 	lsl.w	r3, r2, r3
+ 8012aae:	43da      	mvns	r2, r3
+ 8012ab0:	4b21      	ldr	r3, [pc, #132]	; (8012b38 <prvAddCurrentTaskToDelayedList+0xb8>)
+ 8012ab2:	681b      	ldr	r3, [r3, #0]
+ 8012ab4:	4013      	ands	r3, r2
+ 8012ab6:	4a20      	ldr	r2, [pc, #128]	; (8012b38 <prvAddCurrentTaskToDelayedList+0xb8>)
+ 8012ab8:	6013      	str	r3, [r2, #0]
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	#if ( INCLUDE_vTaskSuspend == 1 )
+	{
+		if( ( xTicksToWait == portMAX_DELAY ) && ( xCanBlockIndefinitely != pdFALSE ) )
+ 8012aba:	687b      	ldr	r3, [r7, #4]
+ 8012abc:	f1b3 3fff 	cmp.w	r3, #4294967295
+ 8012ac0:	d10a      	bne.n	8012ad8 <prvAddCurrentTaskToDelayedList+0x58>
+ 8012ac2:	683b      	ldr	r3, [r7, #0]
+ 8012ac4:	2b00      	cmp	r3, #0
+ 8012ac6:	d007      	beq.n	8012ad8 <prvAddCurrentTaskToDelayedList+0x58>
+		{
+			/* Add the task to the suspended task list instead of a delayed task
+			list to ensure it is not woken by a timing event.  It will block
+			indefinitely. */
+			vListInsertEnd( &xSuspendedTaskList, &( pxCurrentTCB->xStateListItem ) );
+ 8012ac8:	4b1a      	ldr	r3, [pc, #104]	; (8012b34 <prvAddCurrentTaskToDelayedList+0xb4>)
+ 8012aca:	681b      	ldr	r3, [r3, #0]
+ 8012acc:	3304      	adds	r3, #4
+ 8012ace:	4619      	mov	r1, r3
+ 8012ad0:	481a      	ldr	r0, [pc, #104]	; (8012b3c <prvAddCurrentTaskToDelayedList+0xbc>)
+ 8012ad2:	f7fd ff01 	bl	80108d8 <vListInsertEnd>
+
+		/* Avoid compiler warning when INCLUDE_vTaskSuspend is not 1. */
+		( void ) xCanBlockIndefinitely;
+	}
+	#endif /* INCLUDE_vTaskSuspend */
+}
+ 8012ad6:	e026      	b.n	8012b26 <prvAddCurrentTaskToDelayedList+0xa6>
+			xTimeToWake = xConstTickCount + xTicksToWait;
+ 8012ad8:	68fa      	ldr	r2, [r7, #12]
+ 8012ada:	687b      	ldr	r3, [r7, #4]
+ 8012adc:	4413      	add	r3, r2
+ 8012ade:	60bb      	str	r3, [r7, #8]
+			listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xStateListItem ), xTimeToWake );
+ 8012ae0:	4b14      	ldr	r3, [pc, #80]	; (8012b34 <prvAddCurrentTaskToDelayedList+0xb4>)
+ 8012ae2:	681b      	ldr	r3, [r3, #0]
+ 8012ae4:	68ba      	ldr	r2, [r7, #8]
+ 8012ae6:	605a      	str	r2, [r3, #4]
+			if( xTimeToWake < xConstTickCount )
+ 8012ae8:	68ba      	ldr	r2, [r7, #8]
+ 8012aea:	68fb      	ldr	r3, [r7, #12]
+ 8012aec:	429a      	cmp	r2, r3
+ 8012aee:	d209      	bcs.n	8012b04 <prvAddCurrentTaskToDelayedList+0x84>
+				vListInsert( pxOverflowDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
+ 8012af0:	4b13      	ldr	r3, [pc, #76]	; (8012b40 <prvAddCurrentTaskToDelayedList+0xc0>)
+ 8012af2:	681a      	ldr	r2, [r3, #0]
+ 8012af4:	4b0f      	ldr	r3, [pc, #60]	; (8012b34 <prvAddCurrentTaskToDelayedList+0xb4>)
+ 8012af6:	681b      	ldr	r3, [r3, #0]
+ 8012af8:	3304      	adds	r3, #4
+ 8012afa:	4619      	mov	r1, r3
+ 8012afc:	4610      	mov	r0, r2
+ 8012afe:	f7fd ff0f 	bl	8010920 <vListInsert>
+}
+ 8012b02:	e010      	b.n	8012b26 <prvAddCurrentTaskToDelayedList+0xa6>
+				vListInsert( pxDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
+ 8012b04:	4b0f      	ldr	r3, [pc, #60]	; (8012b44 <prvAddCurrentTaskToDelayedList+0xc4>)
+ 8012b06:	681a      	ldr	r2, [r3, #0]
+ 8012b08:	4b0a      	ldr	r3, [pc, #40]	; (8012b34 <prvAddCurrentTaskToDelayedList+0xb4>)
+ 8012b0a:	681b      	ldr	r3, [r3, #0]
+ 8012b0c:	3304      	adds	r3, #4
+ 8012b0e:	4619      	mov	r1, r3
+ 8012b10:	4610      	mov	r0, r2
+ 8012b12:	f7fd ff05 	bl	8010920 <vListInsert>
+				if( xTimeToWake < xNextTaskUnblockTime )
+ 8012b16:	4b0c      	ldr	r3, [pc, #48]	; (8012b48 <prvAddCurrentTaskToDelayedList+0xc8>)
+ 8012b18:	681b      	ldr	r3, [r3, #0]
+ 8012b1a:	68ba      	ldr	r2, [r7, #8]
+ 8012b1c:	429a      	cmp	r2, r3
+ 8012b1e:	d202      	bcs.n	8012b26 <prvAddCurrentTaskToDelayedList+0xa6>
+					xNextTaskUnblockTime = xTimeToWake;
+ 8012b20:	4a09      	ldr	r2, [pc, #36]	; (8012b48 <prvAddCurrentTaskToDelayedList+0xc8>)
+ 8012b22:	68bb      	ldr	r3, [r7, #8]
+ 8012b24:	6013      	str	r3, [r2, #0]
+}
+ 8012b26:	bf00      	nop
+ 8012b28:	3710      	adds	r7, #16
+ 8012b2a:	46bd      	mov	sp, r7
+ 8012b2c:	bd80      	pop	{r7, pc}
+ 8012b2e:	bf00      	nop
+ 8012b30:	2400c024 	.word	0x2400c024
+ 8012b34:	2400bf20 	.word	0x2400bf20
+ 8012b38:	2400c028 	.word	0x2400c028
+ 8012b3c:	2400c00c 	.word	0x2400c00c
+ 8012b40:	2400bfdc 	.word	0x2400bfdc
+ 8012b44:	2400bfd8 	.word	0x2400bfd8
+ 8012b48:	2400c040 	.word	0x2400c040
+
+08012b4c <xTimerCreateTimerTask>:
+									TimerCallbackFunction_t pxCallbackFunction,
+									Timer_t *pxNewTimer ) PRIVILEGED_FUNCTION;
+/*-----------------------------------------------------------*/
+
+BaseType_t xTimerCreateTimerTask( void )
+{
+ 8012b4c:	b580      	push	{r7, lr}
+ 8012b4e:	b08a      	sub	sp, #40	; 0x28
+ 8012b50:	af04      	add	r7, sp, #16
+BaseType_t xReturn = pdFAIL;
+ 8012b52:	2300      	movs	r3, #0
+ 8012b54:	617b      	str	r3, [r7, #20]
+
+	/* This function is called when the scheduler is started if
+	configUSE_TIMERS is set to 1.  Check that the infrastructure used by the
+	timer service task has been created/initialised.  If timers have already
+	been created then the initialisation will already have been performed. */
+	prvCheckForValidListAndQueue();
+ 8012b56:	f000 faeb 	bl	8013130 <prvCheckForValidListAndQueue>
+
+	if( xTimerQueue != NULL )
+ 8012b5a:	4b1c      	ldr	r3, [pc, #112]	; (8012bcc <xTimerCreateTimerTask+0x80>)
+ 8012b5c:	681b      	ldr	r3, [r3, #0]
+ 8012b5e:	2b00      	cmp	r3, #0
+ 8012b60:	d021      	beq.n	8012ba6 <xTimerCreateTimerTask+0x5a>
+	{
+		#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+		{
+			StaticTask_t *pxTimerTaskTCBBuffer = NULL;
+ 8012b62:	2300      	movs	r3, #0
+ 8012b64:	60fb      	str	r3, [r7, #12]
+			StackType_t *pxTimerTaskStackBuffer = NULL;
+ 8012b66:	2300      	movs	r3, #0
+ 8012b68:	60bb      	str	r3, [r7, #8]
+			uint32_t ulTimerTaskStackSize;
+
+			vApplicationGetTimerTaskMemory( &pxTimerTaskTCBBuffer, &pxTimerTaskStackBuffer, &ulTimerTaskStackSize );
+ 8012b6a:	1d3a      	adds	r2, r7, #4
+ 8012b6c:	f107 0108 	add.w	r1, r7, #8
+ 8012b70:	f107 030c 	add.w	r3, r7, #12
+ 8012b74:	4618      	mov	r0, r3
+ 8012b76:	f7ed fdd7 	bl	8000728 <vApplicationGetTimerTaskMemory>
+			xTimerTaskHandle = xTaskCreateStatic(	prvTimerTask,
+ 8012b7a:	6879      	ldr	r1, [r7, #4]
+ 8012b7c:	68bb      	ldr	r3, [r7, #8]
+ 8012b7e:	68fa      	ldr	r2, [r7, #12]
+ 8012b80:	9202      	str	r2, [sp, #8]
+ 8012b82:	9301      	str	r3, [sp, #4]
+ 8012b84:	2302      	movs	r3, #2
+ 8012b86:	9300      	str	r3, [sp, #0]
+ 8012b88:	2300      	movs	r3, #0
+ 8012b8a:	460a      	mov	r2, r1
+ 8012b8c:	4910      	ldr	r1, [pc, #64]	; (8012bd0 <xTimerCreateTimerTask+0x84>)
+ 8012b8e:	4811      	ldr	r0, [pc, #68]	; (8012bd4 <xTimerCreateTimerTask+0x88>)
+ 8012b90:	f7fe ff52 	bl	8011a38 <xTaskCreateStatic>
+ 8012b94:	4603      	mov	r3, r0
+ 8012b96:	4a10      	ldr	r2, [pc, #64]	; (8012bd8 <xTimerCreateTimerTask+0x8c>)
+ 8012b98:	6013      	str	r3, [r2, #0]
+													NULL,
+													( ( UBaseType_t ) configTIMER_TASK_PRIORITY ) | portPRIVILEGE_BIT,
+													pxTimerTaskStackBuffer,
+													pxTimerTaskTCBBuffer );
+
+			if( xTimerTaskHandle != NULL )
+ 8012b9a:	4b0f      	ldr	r3, [pc, #60]	; (8012bd8 <xTimerCreateTimerTask+0x8c>)
+ 8012b9c:	681b      	ldr	r3, [r3, #0]
+ 8012b9e:	2b00      	cmp	r3, #0
+ 8012ba0:	d001      	beq.n	8012ba6 <xTimerCreateTimerTask+0x5a>
+			{
+				xReturn = pdPASS;
+ 8012ba2:	2301      	movs	r3, #1
+ 8012ba4:	617b      	str	r3, [r7, #20]
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	configASSERT( xReturn );
+ 8012ba6:	697b      	ldr	r3, [r7, #20]
+ 8012ba8:	2b00      	cmp	r3, #0
+ 8012baa:	d10a      	bne.n	8012bc2 <xTimerCreateTimerTask+0x76>
+	__asm volatile
+ 8012bac:	f04f 0350 	mov.w	r3, #80	; 0x50
+ 8012bb0:	f383 8811 	msr	BASEPRI, r3
+ 8012bb4:	f3bf 8f6f 	isb	sy
+ 8012bb8:	f3bf 8f4f 	dsb	sy
+ 8012bbc:	613b      	str	r3, [r7, #16]
+}
+ 8012bbe:	bf00      	nop
+ 8012bc0:	e7fe      	b.n	8012bc0 <xTimerCreateTimerTask+0x74>
+	return xReturn;
+ 8012bc2:	697b      	ldr	r3, [r7, #20]
+}
+ 8012bc4:	4618      	mov	r0, r3
+ 8012bc6:	3718      	adds	r7, #24
+ 8012bc8:	46bd      	mov	sp, r7
+ 8012bca:	bd80      	pop	{r7, pc}
+ 8012bcc:	2400c07c 	.word	0x2400c07c
+ 8012bd0:	080232bc 	.word	0x080232bc
+ 8012bd4:	08012d11 	.word	0x08012d11
+ 8012bd8:	2400c080 	.word	0x2400c080
+
+08012bdc <xTimerGenericCommand>:
+	}
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xTimerGenericCommand( TimerHandle_t xTimer, const BaseType_t xCommandID, const TickType_t xOptionalValue, BaseType_t * const pxHigherPriorityTaskWoken, const TickType_t xTicksToWait )
+{
+ 8012bdc:	b580      	push	{r7, lr}
+ 8012bde:	b08a      	sub	sp, #40	; 0x28
+ 8012be0:	af00      	add	r7, sp, #0
+ 8012be2:	60f8      	str	r0, [r7, #12]
+ 8012be4:	60b9      	str	r1, [r7, #8]
+ 8012be6:	607a      	str	r2, [r7, #4]
+ 8012be8:	603b      	str	r3, [r7, #0]
+BaseType_t xReturn = pdFAIL;
+ 8012bea:	2300      	movs	r3, #0
+ 8012bec:	627b      	str	r3, [r7, #36]	; 0x24
+DaemonTaskMessage_t xMessage;
+
+	configASSERT( xTimer );
+ 8012bee:	68fb      	ldr	r3, [r7, #12]
+ 8012bf0:	2b00      	cmp	r3, #0
+ 8012bf2:	d10a      	bne.n	8012c0a <xTimerGenericCommand+0x2e>
+	__asm volatile
+ 8012bf4:	f04f 0350 	mov.w	r3, #80	; 0x50
+ 8012bf8:	f383 8811 	msr	BASEPRI, r3
+ 8012bfc:	f3bf 8f6f 	isb	sy
+ 8012c00:	f3bf 8f4f 	dsb	sy
+ 8012c04:	623b      	str	r3, [r7, #32]
+}
+ 8012c06:	bf00      	nop
+ 8012c08:	e7fe      	b.n	8012c08 <xTimerGenericCommand+0x2c>
+
+	/* Send a message to the timer service task to perform a particular action
+	on a particular timer definition. */
+	if( xTimerQueue != NULL )
+ 8012c0a:	4b1a      	ldr	r3, [pc, #104]	; (8012c74 <xTimerGenericCommand+0x98>)
+ 8012c0c:	681b      	ldr	r3, [r3, #0]
+ 8012c0e:	2b00      	cmp	r3, #0
+ 8012c10:	d02a      	beq.n	8012c68 <xTimerGenericCommand+0x8c>
+	{
+		/* Send a command to the timer service task to start the xTimer timer. */
+		xMessage.xMessageID = xCommandID;
+ 8012c12:	68bb      	ldr	r3, [r7, #8]
+ 8012c14:	617b      	str	r3, [r7, #20]
+		xMessage.u.xTimerParameters.xMessageValue = xOptionalValue;
+ 8012c16:	687b      	ldr	r3, [r7, #4]
+ 8012c18:	61bb      	str	r3, [r7, #24]
+		xMessage.u.xTimerParameters.pxTimer = xTimer;
+ 8012c1a:	68fb      	ldr	r3, [r7, #12]
+ 8012c1c:	61fb      	str	r3, [r7, #28]
+
+		if( xCommandID < tmrFIRST_FROM_ISR_COMMAND )
+ 8012c1e:	68bb      	ldr	r3, [r7, #8]
+ 8012c20:	2b05      	cmp	r3, #5
+ 8012c22:	dc18      	bgt.n	8012c56 <xTimerGenericCommand+0x7a>
+		{
+			if( xTaskGetSchedulerState() == taskSCHEDULER_RUNNING )
+ 8012c24:	f7ff fd70 	bl	8012708 <xTaskGetSchedulerState>
+ 8012c28:	4603      	mov	r3, r0
+ 8012c2a:	2b02      	cmp	r3, #2
+ 8012c2c:	d109      	bne.n	8012c42 <xTimerGenericCommand+0x66>
+			{
+				xReturn = xQueueSendToBack( xTimerQueue, &xMessage, xTicksToWait );
+ 8012c2e:	4b11      	ldr	r3, [pc, #68]	; (8012c74 <xTimerGenericCommand+0x98>)
+ 8012c30:	6818      	ldr	r0, [r3, #0]
+ 8012c32:	f107 0114 	add.w	r1, r7, #20
+ 8012c36:	2300      	movs	r3, #0
+ 8012c38:	6b3a      	ldr	r2, [r7, #48]	; 0x30
+ 8012c3a:	f7fe f85b 	bl	8010cf4 <xQueueGenericSend>
+ 8012c3e:	6278      	str	r0, [r7, #36]	; 0x24
+ 8012c40:	e012      	b.n	8012c68 <xTimerGenericCommand+0x8c>
+			}
+			else
+			{
+				xReturn = xQueueSendToBack( xTimerQueue, &xMessage, tmrNO_DELAY );
+ 8012c42:	4b0c      	ldr	r3, [pc, #48]	; (8012c74 <xTimerGenericCommand+0x98>)
+ 8012c44:	6818      	ldr	r0, [r3, #0]
+ 8012c46:	f107 0114 	add.w	r1, r7, #20
+ 8012c4a:	2300      	movs	r3, #0
+ 8012c4c:	2200      	movs	r2, #0
+ 8012c4e:	f7fe f851 	bl	8010cf4 <xQueueGenericSend>
+ 8012c52:	6278      	str	r0, [r7, #36]	; 0x24
+ 8012c54:	e008      	b.n	8012c68 <xTimerGenericCommand+0x8c>
+			}
+		}
+		else
+		{
+			xReturn = xQueueSendToBackFromISR( xTimerQueue, &xMessage, pxHigherPriorityTaskWoken );
+ 8012c56:	4b07      	ldr	r3, [pc, #28]	; (8012c74 <xTimerGenericCommand+0x98>)
+ 8012c58:	6818      	ldr	r0, [r3, #0]
+ 8012c5a:	f107 0114 	add.w	r1, r7, #20
+ 8012c5e:	2300      	movs	r3, #0
+ 8012c60:	683a      	ldr	r2, [r7, #0]
+ 8012c62:	f7fe f945 	bl	8010ef0 <xQueueGenericSendFromISR>
+ 8012c66:	6278      	str	r0, [r7, #36]	; 0x24
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	return xReturn;
+ 8012c68:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+}
+ 8012c6a:	4618      	mov	r0, r3
+ 8012c6c:	3728      	adds	r7, #40	; 0x28
+ 8012c6e:	46bd      	mov	sp, r7
+ 8012c70:	bd80      	pop	{r7, pc}
+ 8012c72:	bf00      	nop
+ 8012c74:	2400c07c 	.word	0x2400c07c
+
+08012c78 <prvProcessExpiredTimer>:
+	return pxTimer->pcTimerName;
+}
+/*-----------------------------------------------------------*/
+
+static void prvProcessExpiredTimer( const TickType_t xNextExpireTime, const TickType_t xTimeNow )
+{
+ 8012c78:	b580      	push	{r7, lr}
+ 8012c7a:	b088      	sub	sp, #32
+ 8012c7c:	af02      	add	r7, sp, #8
+ 8012c7e:	6078      	str	r0, [r7, #4]
+ 8012c80:	6039      	str	r1, [r7, #0]
+BaseType_t xResult;
+Timer_t * const pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList ); /*lint !e9087 !e9079 void * is used as this macro is used with tasks and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+ 8012c82:	4b22      	ldr	r3, [pc, #136]	; (8012d0c <prvProcessExpiredTimer+0x94>)
+ 8012c84:	681b      	ldr	r3, [r3, #0]
+ 8012c86:	68db      	ldr	r3, [r3, #12]
+ 8012c88:	68db      	ldr	r3, [r3, #12]
+ 8012c8a:	617b      	str	r3, [r7, #20]
+
+	/* Remove the timer from the list of active timers.  A check has already
+	been performed to ensure the list is not empty. */
+	( void ) uxListRemove( &( pxTimer->xTimerListItem ) );
+ 8012c8c:	697b      	ldr	r3, [r7, #20]
+ 8012c8e:	3304      	adds	r3, #4
+ 8012c90:	4618      	mov	r0, r3
+ 8012c92:	f7fd fe7e 	bl	8010992 <uxListRemove>
+	traceTIMER_EXPIRED( pxTimer );
+
+	/* If the timer is an auto-reload timer then calculate the next
+	expiry time and re-insert the timer in the list of active timers. */
+	if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 )
+ 8012c96:	697b      	ldr	r3, [r7, #20]
+ 8012c98:	f893 3024 	ldrb.w	r3, [r3, #36]	; 0x24
+ 8012c9c:	f003 0304 	and.w	r3, r3, #4
+ 8012ca0:	2b00      	cmp	r3, #0
+ 8012ca2:	d022      	beq.n	8012cea <prvProcessExpiredTimer+0x72>
+	{
+		/* The timer is inserted into a list using a time relative to anything
+		other than the current time.  It will therefore be inserted into the
+		correct list relative to the time this task thinks it is now. */
+		if( prvInsertTimerInActiveList( pxTimer, ( xNextExpireTime + pxTimer->xTimerPeriodInTicks ), xTimeNow, xNextExpireTime ) != pdFALSE )
+ 8012ca4:	697b      	ldr	r3, [r7, #20]
+ 8012ca6:	699a      	ldr	r2, [r3, #24]
+ 8012ca8:	687b      	ldr	r3, [r7, #4]
+ 8012caa:	18d1      	adds	r1, r2, r3
+ 8012cac:	687b      	ldr	r3, [r7, #4]
+ 8012cae:	683a      	ldr	r2, [r7, #0]
+ 8012cb0:	6978      	ldr	r0, [r7, #20]
+ 8012cb2:	f000 f8d1 	bl	8012e58 <prvInsertTimerInActiveList>
+ 8012cb6:	4603      	mov	r3, r0
+ 8012cb8:	2b00      	cmp	r3, #0
+ 8012cba:	d01f      	beq.n	8012cfc <prvProcessExpiredTimer+0x84>
+		{
+			/* The timer expired before it was added to the active timer
+			list.  Reload it now.  */
+			xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xNextExpireTime, NULL, tmrNO_DELAY );
+ 8012cbc:	2300      	movs	r3, #0
+ 8012cbe:	9300      	str	r3, [sp, #0]
+ 8012cc0:	2300      	movs	r3, #0
+ 8012cc2:	687a      	ldr	r2, [r7, #4]
+ 8012cc4:	2100      	movs	r1, #0
+ 8012cc6:	6978      	ldr	r0, [r7, #20]
+ 8012cc8:	f7ff ff88 	bl	8012bdc <xTimerGenericCommand>
+ 8012ccc:	6138      	str	r0, [r7, #16]
+			configASSERT( xResult );
+ 8012cce:	693b      	ldr	r3, [r7, #16]
+ 8012cd0:	2b00      	cmp	r3, #0
+ 8012cd2:	d113      	bne.n	8012cfc <prvProcessExpiredTimer+0x84>
+	__asm volatile
+ 8012cd4:	f04f 0350 	mov.w	r3, #80	; 0x50
+ 8012cd8:	f383 8811 	msr	BASEPRI, r3
+ 8012cdc:	f3bf 8f6f 	isb	sy
+ 8012ce0:	f3bf 8f4f 	dsb	sy
+ 8012ce4:	60fb      	str	r3, [r7, #12]
+}
+ 8012ce6:	bf00      	nop
+ 8012ce8:	e7fe      	b.n	8012ce8 <prvProcessExpiredTimer+0x70>
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	else
+	{
+		pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE;
+ 8012cea:	697b      	ldr	r3, [r7, #20]
+ 8012cec:	f893 3024 	ldrb.w	r3, [r3, #36]	; 0x24
+ 8012cf0:	f023 0301 	bic.w	r3, r3, #1
+ 8012cf4:	b2da      	uxtb	r2, r3
+ 8012cf6:	697b      	ldr	r3, [r7, #20]
+ 8012cf8:	f883 2024 	strb.w	r2, [r3, #36]	; 0x24
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	/* Call the timer callback. */
+	pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer );
+ 8012cfc:	697b      	ldr	r3, [r7, #20]
+ 8012cfe:	6a1b      	ldr	r3, [r3, #32]
+ 8012d00:	6978      	ldr	r0, [r7, #20]
+ 8012d02:	4798      	blx	r3
+}
+ 8012d04:	bf00      	nop
+ 8012d06:	3718      	adds	r7, #24
+ 8012d08:	46bd      	mov	sp, r7
+ 8012d0a:	bd80      	pop	{r7, pc}
+ 8012d0c:	2400c074 	.word	0x2400c074
+
+08012d10 <prvTimerTask>:
+/*-----------------------------------------------------------*/
+
+static portTASK_FUNCTION( prvTimerTask, pvParameters )
+{
+ 8012d10:	b580      	push	{r7, lr}
+ 8012d12:	b084      	sub	sp, #16
+ 8012d14:	af00      	add	r7, sp, #0
+ 8012d16:	6078      	str	r0, [r7, #4]
+
+	for( ;; )
+	{
+		/* Query the timers list to see if it contains any timers, and if so,
+		obtain the time at which the next timer will expire. */
+		xNextExpireTime = prvGetNextExpireTime( &xListWasEmpty );
+ 8012d18:	f107 0308 	add.w	r3, r7, #8
+ 8012d1c:	4618      	mov	r0, r3
+ 8012d1e:	f000 f857 	bl	8012dd0 <prvGetNextExpireTime>
+ 8012d22:	60f8      	str	r0, [r7, #12]
+
+		/* If a timer has expired, process it.  Otherwise, block this task
+		until either a timer does expire, or a command is received. */
+		prvProcessTimerOrBlockTask( xNextExpireTime, xListWasEmpty );
+ 8012d24:	68bb      	ldr	r3, [r7, #8]
+ 8012d26:	4619      	mov	r1, r3
+ 8012d28:	68f8      	ldr	r0, [r7, #12]
+ 8012d2a:	f000 f803 	bl	8012d34 <prvProcessTimerOrBlockTask>
+
+		/* Empty the command queue. */
+		prvProcessReceivedCommands();
+ 8012d2e:	f000 f8d5 	bl	8012edc <prvProcessReceivedCommands>
+		xNextExpireTime = prvGetNextExpireTime( &xListWasEmpty );
+ 8012d32:	e7f1      	b.n	8012d18 <prvTimerTask+0x8>
+
+08012d34 <prvProcessTimerOrBlockTask>:
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvProcessTimerOrBlockTask( const TickType_t xNextExpireTime, BaseType_t xListWasEmpty )
+{
+ 8012d34:	b580      	push	{r7, lr}
+ 8012d36:	b084      	sub	sp, #16
+ 8012d38:	af00      	add	r7, sp, #0
+ 8012d3a:	6078      	str	r0, [r7, #4]
+ 8012d3c:	6039      	str	r1, [r7, #0]
+TickType_t xTimeNow;
+BaseType_t xTimerListsWereSwitched;
+
+	vTaskSuspendAll();
+ 8012d3e:	f7ff f8b1 	bl	8011ea4 <vTaskSuspendAll>
+		/* Obtain the time now to make an assessment as to whether the timer
+		has expired or not.  If obtaining the time causes the lists to switch
+		then don't process this timer as any timers that remained in the list
+		when the lists were switched will have been processed within the
+		prvSampleTimeNow() function. */
+		xTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched );
+ 8012d42:	f107 0308 	add.w	r3, r7, #8
+ 8012d46:	4618      	mov	r0, r3
+ 8012d48:	f000 f866 	bl	8012e18 <prvSampleTimeNow>
+ 8012d4c:	60f8      	str	r0, [r7, #12]
+		if( xTimerListsWereSwitched == pdFALSE )
+ 8012d4e:	68bb      	ldr	r3, [r7, #8]
+ 8012d50:	2b00      	cmp	r3, #0
+ 8012d52:	d130      	bne.n	8012db6 <prvProcessTimerOrBlockTask+0x82>
+		{
+			/* The tick count has not overflowed, has the timer expired? */
+			if( ( xListWasEmpty == pdFALSE ) && ( xNextExpireTime <= xTimeNow ) )
+ 8012d54:	683b      	ldr	r3, [r7, #0]
+ 8012d56:	2b00      	cmp	r3, #0
+ 8012d58:	d10a      	bne.n	8012d70 <prvProcessTimerOrBlockTask+0x3c>
+ 8012d5a:	687a      	ldr	r2, [r7, #4]
+ 8012d5c:	68fb      	ldr	r3, [r7, #12]
+ 8012d5e:	429a      	cmp	r2, r3
+ 8012d60:	d806      	bhi.n	8012d70 <prvProcessTimerOrBlockTask+0x3c>
+			{
+				( void ) xTaskResumeAll();
+ 8012d62:	f7ff f8ad 	bl	8011ec0 <xTaskResumeAll>
+				prvProcessExpiredTimer( xNextExpireTime, xTimeNow );
+ 8012d66:	68f9      	ldr	r1, [r7, #12]
+ 8012d68:	6878      	ldr	r0, [r7, #4]
+ 8012d6a:	f7ff ff85 	bl	8012c78 <prvProcessExpiredTimer>
+		else
+		{
+			( void ) xTaskResumeAll();
+		}
+	}
+}
+ 8012d6e:	e024      	b.n	8012dba <prvProcessTimerOrBlockTask+0x86>
+				if( xListWasEmpty != pdFALSE )
+ 8012d70:	683b      	ldr	r3, [r7, #0]
+ 8012d72:	2b00      	cmp	r3, #0
+ 8012d74:	d008      	beq.n	8012d88 <prvProcessTimerOrBlockTask+0x54>
+					xListWasEmpty = listLIST_IS_EMPTY( pxOverflowTimerList );
+ 8012d76:	4b13      	ldr	r3, [pc, #76]	; (8012dc4 <prvProcessTimerOrBlockTask+0x90>)
+ 8012d78:	681b      	ldr	r3, [r3, #0]
+ 8012d7a:	681b      	ldr	r3, [r3, #0]
+ 8012d7c:	2b00      	cmp	r3, #0
+ 8012d7e:	d101      	bne.n	8012d84 <prvProcessTimerOrBlockTask+0x50>
+ 8012d80:	2301      	movs	r3, #1
+ 8012d82:	e000      	b.n	8012d86 <prvProcessTimerOrBlockTask+0x52>
+ 8012d84:	2300      	movs	r3, #0
+ 8012d86:	603b      	str	r3, [r7, #0]
+				vQueueWaitForMessageRestricted( xTimerQueue, ( xNextExpireTime - xTimeNow ), xListWasEmpty );
+ 8012d88:	4b0f      	ldr	r3, [pc, #60]	; (8012dc8 <prvProcessTimerOrBlockTask+0x94>)
+ 8012d8a:	6818      	ldr	r0, [r3, #0]
+ 8012d8c:	687a      	ldr	r2, [r7, #4]
+ 8012d8e:	68fb      	ldr	r3, [r7, #12]
+ 8012d90:	1ad3      	subs	r3, r2, r3
+ 8012d92:	683a      	ldr	r2, [r7, #0]
+ 8012d94:	4619      	mov	r1, r3
+ 8012d96:	f7fe fe1b 	bl	80119d0 <vQueueWaitForMessageRestricted>
+				if( xTaskResumeAll() == pdFALSE )
+ 8012d9a:	f7ff f891 	bl	8011ec0 <xTaskResumeAll>
+ 8012d9e:	4603      	mov	r3, r0
+ 8012da0:	2b00      	cmp	r3, #0
+ 8012da2:	d10a      	bne.n	8012dba <prvProcessTimerOrBlockTask+0x86>
+					portYIELD_WITHIN_API();
+ 8012da4:	4b09      	ldr	r3, [pc, #36]	; (8012dcc <prvProcessTimerOrBlockTask+0x98>)
+ 8012da6:	f04f 5280 	mov.w	r2, #268435456	; 0x10000000
+ 8012daa:	601a      	str	r2, [r3, #0]
+ 8012dac:	f3bf 8f4f 	dsb	sy
+ 8012db0:	f3bf 8f6f 	isb	sy
+}
+ 8012db4:	e001      	b.n	8012dba <prvProcessTimerOrBlockTask+0x86>
+			( void ) xTaskResumeAll();
+ 8012db6:	f7ff f883 	bl	8011ec0 <xTaskResumeAll>
+}
+ 8012dba:	bf00      	nop
+ 8012dbc:	3710      	adds	r7, #16
+ 8012dbe:	46bd      	mov	sp, r7
+ 8012dc0:	bd80      	pop	{r7, pc}
+ 8012dc2:	bf00      	nop
+ 8012dc4:	2400c078 	.word	0x2400c078
+ 8012dc8:	2400c07c 	.word	0x2400c07c
+ 8012dcc:	e000ed04 	.word	0xe000ed04
+
+08012dd0 <prvGetNextExpireTime>:
+/*-----------------------------------------------------------*/
+
+static TickType_t prvGetNextExpireTime( BaseType_t * const pxListWasEmpty )
+{
+ 8012dd0:	b480      	push	{r7}
+ 8012dd2:	b085      	sub	sp, #20
+ 8012dd4:	af00      	add	r7, sp, #0
+ 8012dd6:	6078      	str	r0, [r7, #4]
+	the timer with the nearest expiry time will expire.  If there are no
+	active timers then just set the next expire time to 0.  That will cause
+	this task to unblock when the tick count overflows, at which point the
+	timer lists will be switched and the next expiry time can be
+	re-assessed.  */
+	*pxListWasEmpty = listLIST_IS_EMPTY( pxCurrentTimerList );
+ 8012dd8:	4b0e      	ldr	r3, [pc, #56]	; (8012e14 <prvGetNextExpireTime+0x44>)
+ 8012dda:	681b      	ldr	r3, [r3, #0]
+ 8012ddc:	681b      	ldr	r3, [r3, #0]
+ 8012dde:	2b00      	cmp	r3, #0
+ 8012de0:	d101      	bne.n	8012de6 <prvGetNextExpireTime+0x16>
+ 8012de2:	2201      	movs	r2, #1
+ 8012de4:	e000      	b.n	8012de8 <prvGetNextExpireTime+0x18>
+ 8012de6:	2200      	movs	r2, #0
+ 8012de8:	687b      	ldr	r3, [r7, #4]
+ 8012dea:	601a      	str	r2, [r3, #0]
+	if( *pxListWasEmpty == pdFALSE )
+ 8012dec:	687b      	ldr	r3, [r7, #4]
+ 8012dee:	681b      	ldr	r3, [r3, #0]
+ 8012df0:	2b00      	cmp	r3, #0
+ 8012df2:	d105      	bne.n	8012e00 <prvGetNextExpireTime+0x30>
+	{
+		xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList );
+ 8012df4:	4b07      	ldr	r3, [pc, #28]	; (8012e14 <prvGetNextExpireTime+0x44>)
+ 8012df6:	681b      	ldr	r3, [r3, #0]
+ 8012df8:	68db      	ldr	r3, [r3, #12]
+ 8012dfa:	681b      	ldr	r3, [r3, #0]
+ 8012dfc:	60fb      	str	r3, [r7, #12]
+ 8012dfe:	e001      	b.n	8012e04 <prvGetNextExpireTime+0x34>
+	}
+	else
+	{
+		/* Ensure the task unblocks when the tick count rolls over. */
+		xNextExpireTime = ( TickType_t ) 0U;
+ 8012e00:	2300      	movs	r3, #0
+ 8012e02:	60fb      	str	r3, [r7, #12]
+	}
+
+	return xNextExpireTime;
+ 8012e04:	68fb      	ldr	r3, [r7, #12]
+}
+ 8012e06:	4618      	mov	r0, r3
+ 8012e08:	3714      	adds	r7, #20
+ 8012e0a:	46bd      	mov	sp, r7
+ 8012e0c:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8012e10:	4770      	bx	lr
+ 8012e12:	bf00      	nop
+ 8012e14:	2400c074 	.word	0x2400c074
+
+08012e18 <prvSampleTimeNow>:
+/*-----------------------------------------------------------*/
+
+static TickType_t prvSampleTimeNow( BaseType_t * const pxTimerListsWereSwitched )
+{
+ 8012e18:	b580      	push	{r7, lr}
+ 8012e1a:	b084      	sub	sp, #16
+ 8012e1c:	af00      	add	r7, sp, #0
+ 8012e1e:	6078      	str	r0, [r7, #4]
+TickType_t xTimeNow;
+PRIVILEGED_DATA static TickType_t xLastTime = ( TickType_t ) 0U; /*lint !e956 Variable is only accessible to one task. */
+
+	xTimeNow = xTaskGetTickCount();
+ 8012e20:	f7ff f8ea 	bl	8011ff8 <xTaskGetTickCount>
+ 8012e24:	60f8      	str	r0, [r7, #12]
+
+	if( xTimeNow < xLastTime )
+ 8012e26:	4b0b      	ldr	r3, [pc, #44]	; (8012e54 <prvSampleTimeNow+0x3c>)
+ 8012e28:	681b      	ldr	r3, [r3, #0]
+ 8012e2a:	68fa      	ldr	r2, [r7, #12]
+ 8012e2c:	429a      	cmp	r2, r3
+ 8012e2e:	d205      	bcs.n	8012e3c <prvSampleTimeNow+0x24>
+	{
+		prvSwitchTimerLists();
+ 8012e30:	f000 f91a 	bl	8013068 <prvSwitchTimerLists>
+		*pxTimerListsWereSwitched = pdTRUE;
+ 8012e34:	687b      	ldr	r3, [r7, #4]
+ 8012e36:	2201      	movs	r2, #1
+ 8012e38:	601a      	str	r2, [r3, #0]
+ 8012e3a:	e002      	b.n	8012e42 <prvSampleTimeNow+0x2a>
+	}
+	else
+	{
+		*pxTimerListsWereSwitched = pdFALSE;
+ 8012e3c:	687b      	ldr	r3, [r7, #4]
+ 8012e3e:	2200      	movs	r2, #0
+ 8012e40:	601a      	str	r2, [r3, #0]
+	}
+
+	xLastTime = xTimeNow;
+ 8012e42:	4a04      	ldr	r2, [pc, #16]	; (8012e54 <prvSampleTimeNow+0x3c>)
+ 8012e44:	68fb      	ldr	r3, [r7, #12]
+ 8012e46:	6013      	str	r3, [r2, #0]
+
+	return xTimeNow;
+ 8012e48:	68fb      	ldr	r3, [r7, #12]
+}
+ 8012e4a:	4618      	mov	r0, r3
+ 8012e4c:	3710      	adds	r7, #16
+ 8012e4e:	46bd      	mov	sp, r7
+ 8012e50:	bd80      	pop	{r7, pc}
+ 8012e52:	bf00      	nop
+ 8012e54:	2400c084 	.word	0x2400c084
+
+08012e58 <prvInsertTimerInActiveList>:
+/*-----------------------------------------------------------*/
+
+static BaseType_t prvInsertTimerInActiveList( Timer_t * const pxTimer, const TickType_t xNextExpiryTime, const TickType_t xTimeNow, const TickType_t xCommandTime )
+{
+ 8012e58:	b580      	push	{r7, lr}
+ 8012e5a:	b086      	sub	sp, #24
+ 8012e5c:	af00      	add	r7, sp, #0
+ 8012e5e:	60f8      	str	r0, [r7, #12]
+ 8012e60:	60b9      	str	r1, [r7, #8]
+ 8012e62:	607a      	str	r2, [r7, #4]
+ 8012e64:	603b      	str	r3, [r7, #0]
+BaseType_t xProcessTimerNow = pdFALSE;
+ 8012e66:	2300      	movs	r3, #0
+ 8012e68:	617b      	str	r3, [r7, #20]
+
+	listSET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ), xNextExpiryTime );
+ 8012e6a:	68fb      	ldr	r3, [r7, #12]
+ 8012e6c:	68ba      	ldr	r2, [r7, #8]
+ 8012e6e:	605a      	str	r2, [r3, #4]
+	listSET_LIST_ITEM_OWNER( &( pxTimer->xTimerListItem ), pxTimer );
+ 8012e70:	68fb      	ldr	r3, [r7, #12]
+ 8012e72:	68fa      	ldr	r2, [r7, #12]
+ 8012e74:	611a      	str	r2, [r3, #16]
+
+	if( xNextExpiryTime <= xTimeNow )
+ 8012e76:	68ba      	ldr	r2, [r7, #8]
+ 8012e78:	687b      	ldr	r3, [r7, #4]
+ 8012e7a:	429a      	cmp	r2, r3
+ 8012e7c:	d812      	bhi.n	8012ea4 <prvInsertTimerInActiveList+0x4c>
+	{
+		/* Has the expiry time elapsed between the command to start/reset a
+		timer was issued, and the time the command was processed? */
+		if( ( ( TickType_t ) ( xTimeNow - xCommandTime ) ) >= pxTimer->xTimerPeriodInTicks ) /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+ 8012e7e:	687a      	ldr	r2, [r7, #4]
+ 8012e80:	683b      	ldr	r3, [r7, #0]
+ 8012e82:	1ad2      	subs	r2, r2, r3
+ 8012e84:	68fb      	ldr	r3, [r7, #12]
+ 8012e86:	699b      	ldr	r3, [r3, #24]
+ 8012e88:	429a      	cmp	r2, r3
+ 8012e8a:	d302      	bcc.n	8012e92 <prvInsertTimerInActiveList+0x3a>
+		{
+			/* The time between a command being issued and the command being
+			processed actually exceeds the timers period.  */
+			xProcessTimerNow = pdTRUE;
+ 8012e8c:	2301      	movs	r3, #1
+ 8012e8e:	617b      	str	r3, [r7, #20]
+ 8012e90:	e01b      	b.n	8012eca <prvInsertTimerInActiveList+0x72>
+		}
+		else
+		{
+			vListInsert( pxOverflowTimerList, &( pxTimer->xTimerListItem ) );
+ 8012e92:	4b10      	ldr	r3, [pc, #64]	; (8012ed4 <prvInsertTimerInActiveList+0x7c>)
+ 8012e94:	681a      	ldr	r2, [r3, #0]
+ 8012e96:	68fb      	ldr	r3, [r7, #12]
+ 8012e98:	3304      	adds	r3, #4
+ 8012e9a:	4619      	mov	r1, r3
+ 8012e9c:	4610      	mov	r0, r2
+ 8012e9e:	f7fd fd3f 	bl	8010920 <vListInsert>
+ 8012ea2:	e012      	b.n	8012eca <prvInsertTimerInActiveList+0x72>
+		}
+	}
+	else
+	{
+		if( ( xTimeNow < xCommandTime ) && ( xNextExpiryTime >= xCommandTime ) )
+ 8012ea4:	687a      	ldr	r2, [r7, #4]
+ 8012ea6:	683b      	ldr	r3, [r7, #0]
+ 8012ea8:	429a      	cmp	r2, r3
+ 8012eaa:	d206      	bcs.n	8012eba <prvInsertTimerInActiveList+0x62>
+ 8012eac:	68ba      	ldr	r2, [r7, #8]
+ 8012eae:	683b      	ldr	r3, [r7, #0]
+ 8012eb0:	429a      	cmp	r2, r3
+ 8012eb2:	d302      	bcc.n	8012eba <prvInsertTimerInActiveList+0x62>
+		{
+			/* If, since the command was issued, the tick count has overflowed
+			but the expiry time has not, then the timer must have already passed
+			its expiry time and should be processed immediately. */
+			xProcessTimerNow = pdTRUE;
+ 8012eb4:	2301      	movs	r3, #1
+ 8012eb6:	617b      	str	r3, [r7, #20]
+ 8012eb8:	e007      	b.n	8012eca <prvInsertTimerInActiveList+0x72>
+		}
+		else
+		{
+			vListInsert( pxCurrentTimerList, &( pxTimer->xTimerListItem ) );
+ 8012eba:	4b07      	ldr	r3, [pc, #28]	; (8012ed8 <prvInsertTimerInActiveList+0x80>)
+ 8012ebc:	681a      	ldr	r2, [r3, #0]
+ 8012ebe:	68fb      	ldr	r3, [r7, #12]
+ 8012ec0:	3304      	adds	r3, #4
+ 8012ec2:	4619      	mov	r1, r3
+ 8012ec4:	4610      	mov	r0, r2
+ 8012ec6:	f7fd fd2b 	bl	8010920 <vListInsert>
+		}
+	}
+
+	return xProcessTimerNow;
+ 8012eca:	697b      	ldr	r3, [r7, #20]
+}
+ 8012ecc:	4618      	mov	r0, r3
+ 8012ece:	3718      	adds	r7, #24
+ 8012ed0:	46bd      	mov	sp, r7
+ 8012ed2:	bd80      	pop	{r7, pc}
+ 8012ed4:	2400c078 	.word	0x2400c078
+ 8012ed8:	2400c074 	.word	0x2400c074
+
+08012edc <prvProcessReceivedCommands>:
+/*-----------------------------------------------------------*/
+
+static void	prvProcessReceivedCommands( void )
+{
+ 8012edc:	b580      	push	{r7, lr}
+ 8012ede:	b08c      	sub	sp, #48	; 0x30
+ 8012ee0:	af02      	add	r7, sp, #8
+DaemonTaskMessage_t xMessage;
+Timer_t *pxTimer;
+BaseType_t xTimerListsWereSwitched, xResult;
+TickType_t xTimeNow;
+
+	while( xQueueReceive( xTimerQueue, &xMessage, tmrNO_DELAY ) != pdFAIL ) /*lint !e603 xMessage does not have to be initialised as it is passed out, not in, and it is not used unless xQueueReceive() returns pdTRUE. */
+ 8012ee2:	e0ae      	b.n	8013042 <prvProcessReceivedCommands+0x166>
+		}
+		#endif /* INCLUDE_xTimerPendFunctionCall */
+
+		/* Commands that are positive are timer commands rather than pended
+		function calls. */
+		if( xMessage.xMessageID >= ( BaseType_t ) 0 )
+ 8012ee4:	68bb      	ldr	r3, [r7, #8]
+ 8012ee6:	2b00      	cmp	r3, #0
+ 8012ee8:	f2c0 80ab 	blt.w	8013042 <prvProcessReceivedCommands+0x166>
+		{
+			/* The messages uses the xTimerParameters member to work on a
+			software timer. */
+			pxTimer = xMessage.u.xTimerParameters.pxTimer;
+ 8012eec:	693b      	ldr	r3, [r7, #16]
+ 8012eee:	627b      	str	r3, [r7, #36]	; 0x24
+
+			if( listIS_CONTAINED_WITHIN( NULL, &( pxTimer->xTimerListItem ) ) == pdFALSE ) /*lint !e961. The cast is only redundant when NULL is passed into the macro. */
+ 8012ef0:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 8012ef2:	695b      	ldr	r3, [r3, #20]
+ 8012ef4:	2b00      	cmp	r3, #0
+ 8012ef6:	d004      	beq.n	8012f02 <prvProcessReceivedCommands+0x26>
+			{
+				/* The timer is in a list, remove it. */
+				( void ) uxListRemove( &( pxTimer->xTimerListItem ) );
+ 8012ef8:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 8012efa:	3304      	adds	r3, #4
+ 8012efc:	4618      	mov	r0, r3
+ 8012efe:	f7fd fd48 	bl	8010992 <uxListRemove>
+			it must be present in the function call.  prvSampleTimeNow() must be
+			called after the message is received from xTimerQueue so there is no
+			possibility of a higher priority task adding a message to the message
+			queue with a time that is ahead of the timer daemon task (because it
+			pre-empted the timer daemon task after the xTimeNow value was set). */
+			xTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched );
+ 8012f02:	1d3b      	adds	r3, r7, #4
+ 8012f04:	4618      	mov	r0, r3
+ 8012f06:	f7ff ff87 	bl	8012e18 <prvSampleTimeNow>
+ 8012f0a:	6238      	str	r0, [r7, #32]
+
+			switch( xMessage.xMessageID )
+ 8012f0c:	68bb      	ldr	r3, [r7, #8]
+ 8012f0e:	2b09      	cmp	r3, #9
+ 8012f10:	f200 8096 	bhi.w	8013040 <prvProcessReceivedCommands+0x164>
+ 8012f14:	a201      	add	r2, pc, #4	; (adr r2, 8012f1c <prvProcessReceivedCommands+0x40>)
+ 8012f16:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
+ 8012f1a:	bf00      	nop
+ 8012f1c:	08012f45 	.word	0x08012f45
+ 8012f20:	08012f45 	.word	0x08012f45
+ 8012f24:	08012f45 	.word	0x08012f45
+ 8012f28:	08012fb9 	.word	0x08012fb9
+ 8012f2c:	08012fcd 	.word	0x08012fcd
+ 8012f30:	08013017 	.word	0x08013017
+ 8012f34:	08012f45 	.word	0x08012f45
+ 8012f38:	08012f45 	.word	0x08012f45
+ 8012f3c:	08012fb9 	.word	0x08012fb9
+ 8012f40:	08012fcd 	.word	0x08012fcd
+				case tmrCOMMAND_START_FROM_ISR :
+				case tmrCOMMAND_RESET :
+				case tmrCOMMAND_RESET_FROM_ISR :
+				case tmrCOMMAND_START_DONT_TRACE :
+					/* Start or restart a timer. */
+					pxTimer->ucStatus |= tmrSTATUS_IS_ACTIVE;
+ 8012f44:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 8012f46:	f893 3024 	ldrb.w	r3, [r3, #36]	; 0x24
+ 8012f4a:	f043 0301 	orr.w	r3, r3, #1
+ 8012f4e:	b2da      	uxtb	r2, r3
+ 8012f50:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 8012f52:	f883 2024 	strb.w	r2, [r3, #36]	; 0x24
+					if( prvInsertTimerInActiveList( pxTimer,  xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, xTimeNow, xMessage.u.xTimerParameters.xMessageValue ) != pdFALSE )
+ 8012f56:	68fa      	ldr	r2, [r7, #12]
+ 8012f58:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 8012f5a:	699b      	ldr	r3, [r3, #24]
+ 8012f5c:	18d1      	adds	r1, r2, r3
+ 8012f5e:	68fb      	ldr	r3, [r7, #12]
+ 8012f60:	6a3a      	ldr	r2, [r7, #32]
+ 8012f62:	6a78      	ldr	r0, [r7, #36]	; 0x24
+ 8012f64:	f7ff ff78 	bl	8012e58 <prvInsertTimerInActiveList>
+ 8012f68:	4603      	mov	r3, r0
+ 8012f6a:	2b00      	cmp	r3, #0
+ 8012f6c:	d069      	beq.n	8013042 <prvProcessReceivedCommands+0x166>
+					{
+						/* The timer expired before it was added to the active
+						timer list.  Process it now. */
+						pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer );
+ 8012f6e:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 8012f70:	6a1b      	ldr	r3, [r3, #32]
+ 8012f72:	6a78      	ldr	r0, [r7, #36]	; 0x24
+ 8012f74:	4798      	blx	r3
+						traceTIMER_EXPIRED( pxTimer );
+
+						if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 )
+ 8012f76:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 8012f78:	f893 3024 	ldrb.w	r3, [r3, #36]	; 0x24
+ 8012f7c:	f003 0304 	and.w	r3, r3, #4
+ 8012f80:	2b00      	cmp	r3, #0
+ 8012f82:	d05e      	beq.n	8013042 <prvProcessReceivedCommands+0x166>
+						{
+							xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, NULL, tmrNO_DELAY );
+ 8012f84:	68fa      	ldr	r2, [r7, #12]
+ 8012f86:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 8012f88:	699b      	ldr	r3, [r3, #24]
+ 8012f8a:	441a      	add	r2, r3
+ 8012f8c:	2300      	movs	r3, #0
+ 8012f8e:	9300      	str	r3, [sp, #0]
+ 8012f90:	2300      	movs	r3, #0
+ 8012f92:	2100      	movs	r1, #0
+ 8012f94:	6a78      	ldr	r0, [r7, #36]	; 0x24
+ 8012f96:	f7ff fe21 	bl	8012bdc <xTimerGenericCommand>
+ 8012f9a:	61f8      	str	r0, [r7, #28]
+							configASSERT( xResult );
+ 8012f9c:	69fb      	ldr	r3, [r7, #28]
+ 8012f9e:	2b00      	cmp	r3, #0
+ 8012fa0:	d14f      	bne.n	8013042 <prvProcessReceivedCommands+0x166>
+	__asm volatile
+ 8012fa2:	f04f 0350 	mov.w	r3, #80	; 0x50
+ 8012fa6:	f383 8811 	msr	BASEPRI, r3
+ 8012faa:	f3bf 8f6f 	isb	sy
+ 8012fae:	f3bf 8f4f 	dsb	sy
+ 8012fb2:	61bb      	str	r3, [r7, #24]
+}
+ 8012fb4:	bf00      	nop
+ 8012fb6:	e7fe      	b.n	8012fb6 <prvProcessReceivedCommands+0xda>
+					break;
+
+				case tmrCOMMAND_STOP :
+				case tmrCOMMAND_STOP_FROM_ISR :
+					/* The timer has already been removed from the active list. */
+					pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE;
+ 8012fb8:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 8012fba:	f893 3024 	ldrb.w	r3, [r3, #36]	; 0x24
+ 8012fbe:	f023 0301 	bic.w	r3, r3, #1
+ 8012fc2:	b2da      	uxtb	r2, r3
+ 8012fc4:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 8012fc6:	f883 2024 	strb.w	r2, [r3, #36]	; 0x24
+					break;
+ 8012fca:	e03a      	b.n	8013042 <prvProcessReceivedCommands+0x166>
+
+				case tmrCOMMAND_CHANGE_PERIOD :
+				case tmrCOMMAND_CHANGE_PERIOD_FROM_ISR :
+					pxTimer->ucStatus |= tmrSTATUS_IS_ACTIVE;
+ 8012fcc:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 8012fce:	f893 3024 	ldrb.w	r3, [r3, #36]	; 0x24
+ 8012fd2:	f043 0301 	orr.w	r3, r3, #1
+ 8012fd6:	b2da      	uxtb	r2, r3
+ 8012fd8:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 8012fda:	f883 2024 	strb.w	r2, [r3, #36]	; 0x24
+					pxTimer->xTimerPeriodInTicks = xMessage.u.xTimerParameters.xMessageValue;
+ 8012fde:	68fa      	ldr	r2, [r7, #12]
+ 8012fe0:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 8012fe2:	619a      	str	r2, [r3, #24]
+					configASSERT( ( pxTimer->xTimerPeriodInTicks > 0 ) );
+ 8012fe4:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 8012fe6:	699b      	ldr	r3, [r3, #24]
+ 8012fe8:	2b00      	cmp	r3, #0
+ 8012fea:	d10a      	bne.n	8013002 <prvProcessReceivedCommands+0x126>
+	__asm volatile
+ 8012fec:	f04f 0350 	mov.w	r3, #80	; 0x50
+ 8012ff0:	f383 8811 	msr	BASEPRI, r3
+ 8012ff4:	f3bf 8f6f 	isb	sy
+ 8012ff8:	f3bf 8f4f 	dsb	sy
+ 8012ffc:	617b      	str	r3, [r7, #20]
+}
+ 8012ffe:	bf00      	nop
+ 8013000:	e7fe      	b.n	8013000 <prvProcessReceivedCommands+0x124>
+					be longer or shorter than the old one.  The command time is
+					therefore set to the current time, and as the period cannot
+					be zero the next expiry time can only be in the future,
+					meaning (unlike for the xTimerStart() case above) there is
+					no fail case that needs to be handled here. */
+					( void ) prvInsertTimerInActiveList( pxTimer, ( xTimeNow + pxTimer->xTimerPeriodInTicks ), xTimeNow, xTimeNow );
+ 8013002:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 8013004:	699a      	ldr	r2, [r3, #24]
+ 8013006:	6a3b      	ldr	r3, [r7, #32]
+ 8013008:	18d1      	adds	r1, r2, r3
+ 801300a:	6a3b      	ldr	r3, [r7, #32]
+ 801300c:	6a3a      	ldr	r2, [r7, #32]
+ 801300e:	6a78      	ldr	r0, [r7, #36]	; 0x24
+ 8013010:	f7ff ff22 	bl	8012e58 <prvInsertTimerInActiveList>
+					break;
+ 8013014:	e015      	b.n	8013042 <prvProcessReceivedCommands+0x166>
+					#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+					{
+						/* The timer has already been removed from the active list,
+						just free up the memory if the memory was dynamically
+						allocated. */
+						if( ( pxTimer->ucStatus & tmrSTATUS_IS_STATICALLY_ALLOCATED ) == ( uint8_t ) 0 )
+ 8013016:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 8013018:	f893 3024 	ldrb.w	r3, [r3, #36]	; 0x24
+ 801301c:	f003 0302 	and.w	r3, r3, #2
+ 8013020:	2b00      	cmp	r3, #0
+ 8013022:	d103      	bne.n	801302c <prvProcessReceivedCommands+0x150>
+						{
+							vPortFree( pxTimer );
+ 8013024:	6a78      	ldr	r0, [r7, #36]	; 0x24
+ 8013026:	f000 fbdb 	bl	80137e0 <vPortFree>
+ 801302a:	e00a      	b.n	8013042 <prvProcessReceivedCommands+0x166>
+						}
+						else
+						{
+							pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE;
+ 801302c:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 801302e:	f893 3024 	ldrb.w	r3, [r3, #36]	; 0x24
+ 8013032:	f023 0301 	bic.w	r3, r3, #1
+ 8013036:	b2da      	uxtb	r2, r3
+ 8013038:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 801303a:	f883 2024 	strb.w	r2, [r3, #36]	; 0x24
+						no need to free the memory - just mark the timer as
+						"not active". */
+						pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE;
+					}
+					#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+					break;
+ 801303e:	e000      	b.n	8013042 <prvProcessReceivedCommands+0x166>
+
+				default	:
+					/* Don't expect to get here. */
+					break;
+ 8013040:	bf00      	nop
+	while( xQueueReceive( xTimerQueue, &xMessage, tmrNO_DELAY ) != pdFAIL ) /*lint !e603 xMessage does not have to be initialised as it is passed out, not in, and it is not used unless xQueueReceive() returns pdTRUE. */
+ 8013042:	4b08      	ldr	r3, [pc, #32]	; (8013064 <prvProcessReceivedCommands+0x188>)
+ 8013044:	681b      	ldr	r3, [r3, #0]
+ 8013046:	f107 0108 	add.w	r1, r7, #8
+ 801304a:	2200      	movs	r2, #0
+ 801304c:	4618      	mov	r0, r3
+ 801304e:	f7fe f877 	bl	8011140 <xQueueReceive>
+ 8013052:	4603      	mov	r3, r0
+ 8013054:	2b00      	cmp	r3, #0
+ 8013056:	f47f af45 	bne.w	8012ee4 <prvProcessReceivedCommands+0x8>
+			}
+		}
+	}
+}
+ 801305a:	bf00      	nop
+ 801305c:	bf00      	nop
+ 801305e:	3728      	adds	r7, #40	; 0x28
+ 8013060:	46bd      	mov	sp, r7
+ 8013062:	bd80      	pop	{r7, pc}
+ 8013064:	2400c07c 	.word	0x2400c07c
+
+08013068 <prvSwitchTimerLists>:
+/*-----------------------------------------------------------*/
+
+static void prvSwitchTimerLists( void )
+{
+ 8013068:	b580      	push	{r7, lr}
+ 801306a:	b088      	sub	sp, #32
+ 801306c:	af02      	add	r7, sp, #8
+
+	/* The tick count has overflowed.  The timer lists must be switched.
+	If there are any timers still referenced from the current timer list
+	then they must have expired and should be processed before the lists
+	are switched. */
+	while( listLIST_IS_EMPTY( pxCurrentTimerList ) == pdFALSE )
+ 801306e:	e048      	b.n	8013102 <prvSwitchTimerLists+0x9a>
+	{
+		xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList );
+ 8013070:	4b2d      	ldr	r3, [pc, #180]	; (8013128 <prvSwitchTimerLists+0xc0>)
+ 8013072:	681b      	ldr	r3, [r3, #0]
+ 8013074:	68db      	ldr	r3, [r3, #12]
+ 8013076:	681b      	ldr	r3, [r3, #0]
+ 8013078:	613b      	str	r3, [r7, #16]
+
+		/* Remove the timer from the list. */
+		pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList ); /*lint !e9087 !e9079 void * is used as this macro is used with tasks and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+ 801307a:	4b2b      	ldr	r3, [pc, #172]	; (8013128 <prvSwitchTimerLists+0xc0>)
+ 801307c:	681b      	ldr	r3, [r3, #0]
+ 801307e:	68db      	ldr	r3, [r3, #12]
+ 8013080:	68db      	ldr	r3, [r3, #12]
+ 8013082:	60fb      	str	r3, [r7, #12]
+		( void ) uxListRemove( &( pxTimer->xTimerListItem ) );
+ 8013084:	68fb      	ldr	r3, [r7, #12]
+ 8013086:	3304      	adds	r3, #4
+ 8013088:	4618      	mov	r0, r3
+ 801308a:	f7fd fc82 	bl	8010992 <uxListRemove>
+		traceTIMER_EXPIRED( pxTimer );
+
+		/* Execute its callback, then send a command to restart the timer if
+		it is an auto-reload timer.  It cannot be restarted here as the lists
+		have not yet been switched. */
+		pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer );
+ 801308e:	68fb      	ldr	r3, [r7, #12]
+ 8013090:	6a1b      	ldr	r3, [r3, #32]
+ 8013092:	68f8      	ldr	r0, [r7, #12]
+ 8013094:	4798      	blx	r3
+
+		if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 )
+ 8013096:	68fb      	ldr	r3, [r7, #12]
+ 8013098:	f893 3024 	ldrb.w	r3, [r3, #36]	; 0x24
+ 801309c:	f003 0304 	and.w	r3, r3, #4
+ 80130a0:	2b00      	cmp	r3, #0
+ 80130a2:	d02e      	beq.n	8013102 <prvSwitchTimerLists+0x9a>
+			the timer going into the same timer list then it has already expired
+			and the timer should be re-inserted into the current list so it is
+			processed again within this loop.  Otherwise a command should be sent
+			to restart the timer to ensure it is only inserted into a list after
+			the lists have been swapped. */
+			xReloadTime = ( xNextExpireTime + pxTimer->xTimerPeriodInTicks );
+ 80130a4:	68fb      	ldr	r3, [r7, #12]
+ 80130a6:	699b      	ldr	r3, [r3, #24]
+ 80130a8:	693a      	ldr	r2, [r7, #16]
+ 80130aa:	4413      	add	r3, r2
+ 80130ac:	60bb      	str	r3, [r7, #8]
+			if( xReloadTime > xNextExpireTime )
+ 80130ae:	68ba      	ldr	r2, [r7, #8]
+ 80130b0:	693b      	ldr	r3, [r7, #16]
+ 80130b2:	429a      	cmp	r2, r3
+ 80130b4:	d90e      	bls.n	80130d4 <prvSwitchTimerLists+0x6c>
+			{
+				listSET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ), xReloadTime );
+ 80130b6:	68fb      	ldr	r3, [r7, #12]
+ 80130b8:	68ba      	ldr	r2, [r7, #8]
+ 80130ba:	605a      	str	r2, [r3, #4]
+				listSET_LIST_ITEM_OWNER( &( pxTimer->xTimerListItem ), pxTimer );
+ 80130bc:	68fb      	ldr	r3, [r7, #12]
+ 80130be:	68fa      	ldr	r2, [r7, #12]
+ 80130c0:	611a      	str	r2, [r3, #16]
+				vListInsert( pxCurrentTimerList, &( pxTimer->xTimerListItem ) );
+ 80130c2:	4b19      	ldr	r3, [pc, #100]	; (8013128 <prvSwitchTimerLists+0xc0>)
+ 80130c4:	681a      	ldr	r2, [r3, #0]
+ 80130c6:	68fb      	ldr	r3, [r7, #12]
+ 80130c8:	3304      	adds	r3, #4
+ 80130ca:	4619      	mov	r1, r3
+ 80130cc:	4610      	mov	r0, r2
+ 80130ce:	f7fd fc27 	bl	8010920 <vListInsert>
+ 80130d2:	e016      	b.n	8013102 <prvSwitchTimerLists+0x9a>
+			}
+			else
+			{
+				xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xNextExpireTime, NULL, tmrNO_DELAY );
+ 80130d4:	2300      	movs	r3, #0
+ 80130d6:	9300      	str	r3, [sp, #0]
+ 80130d8:	2300      	movs	r3, #0
+ 80130da:	693a      	ldr	r2, [r7, #16]
+ 80130dc:	2100      	movs	r1, #0
+ 80130de:	68f8      	ldr	r0, [r7, #12]
+ 80130e0:	f7ff fd7c 	bl	8012bdc <xTimerGenericCommand>
+ 80130e4:	6078      	str	r0, [r7, #4]
+				configASSERT( xResult );
+ 80130e6:	687b      	ldr	r3, [r7, #4]
+ 80130e8:	2b00      	cmp	r3, #0
+ 80130ea:	d10a      	bne.n	8013102 <prvSwitchTimerLists+0x9a>
+	__asm volatile
+ 80130ec:	f04f 0350 	mov.w	r3, #80	; 0x50
+ 80130f0:	f383 8811 	msr	BASEPRI, r3
+ 80130f4:	f3bf 8f6f 	isb	sy
+ 80130f8:	f3bf 8f4f 	dsb	sy
+ 80130fc:	603b      	str	r3, [r7, #0]
+}
+ 80130fe:	bf00      	nop
+ 8013100:	e7fe      	b.n	8013100 <prvSwitchTimerLists+0x98>
+	while( listLIST_IS_EMPTY( pxCurrentTimerList ) == pdFALSE )
+ 8013102:	4b09      	ldr	r3, [pc, #36]	; (8013128 <prvSwitchTimerLists+0xc0>)
+ 8013104:	681b      	ldr	r3, [r3, #0]
+ 8013106:	681b      	ldr	r3, [r3, #0]
+ 8013108:	2b00      	cmp	r3, #0
+ 801310a:	d1b1      	bne.n	8013070 <prvSwitchTimerLists+0x8>
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+
+	pxTemp = pxCurrentTimerList;
+ 801310c:	4b06      	ldr	r3, [pc, #24]	; (8013128 <prvSwitchTimerLists+0xc0>)
+ 801310e:	681b      	ldr	r3, [r3, #0]
+ 8013110:	617b      	str	r3, [r7, #20]
+	pxCurrentTimerList = pxOverflowTimerList;
+ 8013112:	4b06      	ldr	r3, [pc, #24]	; (801312c <prvSwitchTimerLists+0xc4>)
+ 8013114:	681b      	ldr	r3, [r3, #0]
+ 8013116:	4a04      	ldr	r2, [pc, #16]	; (8013128 <prvSwitchTimerLists+0xc0>)
+ 8013118:	6013      	str	r3, [r2, #0]
+	pxOverflowTimerList = pxTemp;
+ 801311a:	4a04      	ldr	r2, [pc, #16]	; (801312c <prvSwitchTimerLists+0xc4>)
+ 801311c:	697b      	ldr	r3, [r7, #20]
+ 801311e:	6013      	str	r3, [r2, #0]
+}
+ 8013120:	bf00      	nop
+ 8013122:	3718      	adds	r7, #24
+ 8013124:	46bd      	mov	sp, r7
+ 8013126:	bd80      	pop	{r7, pc}
+ 8013128:	2400c074 	.word	0x2400c074
+ 801312c:	2400c078 	.word	0x2400c078
+
+08013130 <prvCheckForValidListAndQueue>:
+/*-----------------------------------------------------------*/
+
+static void prvCheckForValidListAndQueue( void )
+{
+ 8013130:	b580      	push	{r7, lr}
+ 8013132:	b082      	sub	sp, #8
+ 8013134:	af02      	add	r7, sp, #8
+	/* Check that the list from which active timers are referenced, and the
+	queue used to communicate with the timer service, have been
+	initialised. */
+	taskENTER_CRITICAL();
+ 8013136:	f000 f965 	bl	8013404 <vPortEnterCritical>
+	{
+		if( xTimerQueue == NULL )
+ 801313a:	4b15      	ldr	r3, [pc, #84]	; (8013190 <prvCheckForValidListAndQueue+0x60>)
+ 801313c:	681b      	ldr	r3, [r3, #0]
+ 801313e:	2b00      	cmp	r3, #0
+ 8013140:	d120      	bne.n	8013184 <prvCheckForValidListAndQueue+0x54>
+		{
+			vListInitialise( &xActiveTimerList1 );
+ 8013142:	4814      	ldr	r0, [pc, #80]	; (8013194 <prvCheckForValidListAndQueue+0x64>)
+ 8013144:	f7fd fb9b 	bl	801087e <vListInitialise>
+			vListInitialise( &xActiveTimerList2 );
+ 8013148:	4813      	ldr	r0, [pc, #76]	; (8013198 <prvCheckForValidListAndQueue+0x68>)
+ 801314a:	f7fd fb98 	bl	801087e <vListInitialise>
+			pxCurrentTimerList = &xActiveTimerList1;
+ 801314e:	4b13      	ldr	r3, [pc, #76]	; (801319c <prvCheckForValidListAndQueue+0x6c>)
+ 8013150:	4a10      	ldr	r2, [pc, #64]	; (8013194 <prvCheckForValidListAndQueue+0x64>)
+ 8013152:	601a      	str	r2, [r3, #0]
+			pxOverflowTimerList = &xActiveTimerList2;
+ 8013154:	4b12      	ldr	r3, [pc, #72]	; (80131a0 <prvCheckForValidListAndQueue+0x70>)
+ 8013156:	4a10      	ldr	r2, [pc, #64]	; (8013198 <prvCheckForValidListAndQueue+0x68>)
+ 8013158:	601a      	str	r2, [r3, #0]
+				/* The timer queue is allocated statically in case
+				configSUPPORT_DYNAMIC_ALLOCATION is 0. */
+				static StaticQueue_t xStaticTimerQueue; /*lint !e956 Ok to declare in this manner to prevent additional conditional compilation guards in other locations. */
+				static uint8_t ucStaticTimerQueueStorage[ ( size_t ) configTIMER_QUEUE_LENGTH * sizeof( DaemonTaskMessage_t ) ]; /*lint !e956 Ok to declare in this manner to prevent additional conditional compilation guards in other locations. */
+
+				xTimerQueue = xQueueCreateStatic( ( UBaseType_t ) configTIMER_QUEUE_LENGTH, ( UBaseType_t ) sizeof( DaemonTaskMessage_t ), &( ucStaticTimerQueueStorage[ 0 ] ), &xStaticTimerQueue );
+ 801315a:	2300      	movs	r3, #0
+ 801315c:	9300      	str	r3, [sp, #0]
+ 801315e:	4b11      	ldr	r3, [pc, #68]	; (80131a4 <prvCheckForValidListAndQueue+0x74>)
+ 8013160:	4a11      	ldr	r2, [pc, #68]	; (80131a8 <prvCheckForValidListAndQueue+0x78>)
+ 8013162:	210c      	movs	r1, #12
+ 8013164:	200a      	movs	r0, #10
+ 8013166:	f7fd fca7 	bl	8010ab8 <xQueueGenericCreateStatic>
+ 801316a:	4603      	mov	r3, r0
+ 801316c:	4a08      	ldr	r2, [pc, #32]	; (8013190 <prvCheckForValidListAndQueue+0x60>)
+ 801316e:	6013      	str	r3, [r2, #0]
+			}
+			#endif
+
+			#if ( configQUEUE_REGISTRY_SIZE > 0 )
+			{
+				if( xTimerQueue != NULL )
+ 8013170:	4b07      	ldr	r3, [pc, #28]	; (8013190 <prvCheckForValidListAndQueue+0x60>)
+ 8013172:	681b      	ldr	r3, [r3, #0]
+ 8013174:	2b00      	cmp	r3, #0
+ 8013176:	d005      	beq.n	8013184 <prvCheckForValidListAndQueue+0x54>
+				{
+					vQueueAddToRegistry( xTimerQueue, "TmrQ" );
+ 8013178:	4b05      	ldr	r3, [pc, #20]	; (8013190 <prvCheckForValidListAndQueue+0x60>)
+ 801317a:	681b      	ldr	r3, [r3, #0]
+ 801317c:	490b      	ldr	r1, [pc, #44]	; (80131ac <prvCheckForValidListAndQueue+0x7c>)
+ 801317e:	4618      	mov	r0, r3
+ 8013180:	f7fe fbd2 	bl	8011928 <vQueueAddToRegistry>
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	taskEXIT_CRITICAL();
+ 8013184:	f000 f96e 	bl	8013464 <vPortExitCritical>
+}
+ 8013188:	bf00      	nop
+ 801318a:	46bd      	mov	sp, r7
+ 801318c:	bd80      	pop	{r7, pc}
+ 801318e:	bf00      	nop
+ 8013190:	2400c07c 	.word	0x2400c07c
+ 8013194:	2400c04c 	.word	0x2400c04c
+ 8013198:	2400c060 	.word	0x2400c060
+ 801319c:	2400c074 	.word	0x2400c074
+ 80131a0:	2400c078 	.word	0x2400c078
+ 80131a4:	2400c100 	.word	0x2400c100
+ 80131a8:	2400c088 	.word	0x2400c088
+ 80131ac:	080232c4 	.word	0x080232c4
+
+080131b0 <pxPortInitialiseStack>:
+
+/*
+ * See header file for description.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+ 80131b0:	b480      	push	{r7}
+ 80131b2:	b085      	sub	sp, #20
+ 80131b4:	af00      	add	r7, sp, #0
+ 80131b6:	60f8      	str	r0, [r7, #12]
+ 80131b8:	60b9      	str	r1, [r7, #8]
+ 80131ba:	607a      	str	r2, [r7, #4]
+	/* Simulate the stack frame as it would be created by a context switch
+	interrupt. */
+
+	/* Offset added to account for the way the MCU uses the stack on entry/exit
+	of interrupts, and to ensure alignment. */
+	pxTopOfStack--;
+ 80131bc:	68fb      	ldr	r3, [r7, #12]
+ 80131be:	3b04      	subs	r3, #4
+ 80131c0:	60fb      	str	r3, [r7, #12]
+
+	*pxTopOfStack = portINITIAL_XPSR;	/* xPSR */
+ 80131c2:	68fb      	ldr	r3, [r7, #12]
+ 80131c4:	f04f 7280 	mov.w	r2, #16777216	; 0x1000000
+ 80131c8:	601a      	str	r2, [r3, #0]
+	pxTopOfStack--;
+ 80131ca:	68fb      	ldr	r3, [r7, #12]
+ 80131cc:	3b04      	subs	r3, #4
+ 80131ce:	60fb      	str	r3, [r7, #12]
+	*pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK;	/* PC */
+ 80131d0:	68bb      	ldr	r3, [r7, #8]
+ 80131d2:	f023 0201 	bic.w	r2, r3, #1
+ 80131d6:	68fb      	ldr	r3, [r7, #12]
+ 80131d8:	601a      	str	r2, [r3, #0]
+	pxTopOfStack--;
+ 80131da:	68fb      	ldr	r3, [r7, #12]
+ 80131dc:	3b04      	subs	r3, #4
+ 80131de:	60fb      	str	r3, [r7, #12]
+	*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;	/* LR */
+ 80131e0:	4a0c      	ldr	r2, [pc, #48]	; (8013214 <pxPortInitialiseStack+0x64>)
+ 80131e2:	68fb      	ldr	r3, [r7, #12]
+ 80131e4:	601a      	str	r2, [r3, #0]
+
+	/* Save code space by skipping register initialisation. */
+	pxTopOfStack -= 5;	/* R12, R3, R2 and R1. */
+ 80131e6:	68fb      	ldr	r3, [r7, #12]
+ 80131e8:	3b14      	subs	r3, #20
+ 80131ea:	60fb      	str	r3, [r7, #12]
+	*pxTopOfStack = ( StackType_t ) pvParameters;	/* R0 */
+ 80131ec:	687a      	ldr	r2, [r7, #4]
+ 80131ee:	68fb      	ldr	r3, [r7, #12]
+ 80131f0:	601a      	str	r2, [r3, #0]
+
+	/* A save method is being used that requires each task to maintain its
+	own exec return value. */
+	pxTopOfStack--;
+ 80131f2:	68fb      	ldr	r3, [r7, #12]
+ 80131f4:	3b04      	subs	r3, #4
+ 80131f6:	60fb      	str	r3, [r7, #12]
+	*pxTopOfStack = portINITIAL_EXC_RETURN;
+ 80131f8:	68fb      	ldr	r3, [r7, #12]
+ 80131fa:	f06f 0202 	mvn.w	r2, #2
+ 80131fe:	601a      	str	r2, [r3, #0]
+
+	pxTopOfStack -= 8;	/* R11, R10, R9, R8, R7, R6, R5 and R4. */
+ 8013200:	68fb      	ldr	r3, [r7, #12]
+ 8013202:	3b20      	subs	r3, #32
+ 8013204:	60fb      	str	r3, [r7, #12]
+
+	return pxTopOfStack;
+ 8013206:	68fb      	ldr	r3, [r7, #12]
+}
+ 8013208:	4618      	mov	r0, r3
+ 801320a:	3714      	adds	r7, #20
+ 801320c:	46bd      	mov	sp, r7
+ 801320e:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8013212:	4770      	bx	lr
+ 8013214:	08013219 	.word	0x08013219
+
+08013218 <prvTaskExitError>:
+/*-----------------------------------------------------------*/
+
+static void prvTaskExitError( void )
+{
+ 8013218:	b480      	push	{r7}
+ 801321a:	b085      	sub	sp, #20
+ 801321c:	af00      	add	r7, sp, #0
+volatile uint32_t ulDummy = 0;
+ 801321e:	2300      	movs	r3, #0
+ 8013220:	607b      	str	r3, [r7, #4]
+	its caller as there is nothing to return to.  If a task wants to exit it
+	should instead call vTaskDelete( NULL ).
+
+	Artificially force an assert() to be triggered if configASSERT() is
+	defined, then stop here so application writers can catch the error. */
+	configASSERT( uxCriticalNesting == ~0UL );
+ 8013222:	4b12      	ldr	r3, [pc, #72]	; (801326c <prvTaskExitError+0x54>)
+ 8013224:	681b      	ldr	r3, [r3, #0]
+ 8013226:	f1b3 3fff 	cmp.w	r3, #4294967295
+ 801322a:	d00a      	beq.n	8013242 <prvTaskExitError+0x2a>
+	__asm volatile
+ 801322c:	f04f 0350 	mov.w	r3, #80	; 0x50
+ 8013230:	f383 8811 	msr	BASEPRI, r3
+ 8013234:	f3bf 8f6f 	isb	sy
+ 8013238:	f3bf 8f4f 	dsb	sy
+ 801323c:	60fb      	str	r3, [r7, #12]
+}
+ 801323e:	bf00      	nop
+ 8013240:	e7fe      	b.n	8013240 <prvTaskExitError+0x28>
+	__asm volatile
+ 8013242:	f04f 0350 	mov.w	r3, #80	; 0x50
+ 8013246:	f383 8811 	msr	BASEPRI, r3
+ 801324a:	f3bf 8f6f 	isb	sy
+ 801324e:	f3bf 8f4f 	dsb	sy
+ 8013252:	60bb      	str	r3, [r7, #8]
+}
+ 8013254:	bf00      	nop
+	portDISABLE_INTERRUPTS();
+	while( ulDummy == 0 )
+ 8013256:	bf00      	nop
+ 8013258:	687b      	ldr	r3, [r7, #4]
+ 801325a:	2b00      	cmp	r3, #0
+ 801325c:	d0fc      	beq.n	8013258 <prvTaskExitError+0x40>
+		about code appearing after this function is called - making ulDummy
+		volatile makes the compiler think the function could return and
+		therefore not output an 'unreachable code' warning for code that appears
+		after it. */
+	}
+}
+ 801325e:	bf00      	nop
+ 8013260:	bf00      	nop
+ 8013262:	3714      	adds	r7, #20
+ 8013264:	46bd      	mov	sp, r7
+ 8013266:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 801326a:	4770      	bx	lr
+ 801326c:	24000038 	.word	0x24000038
+
+08013270 <SVC_Handler>:
+/*-----------------------------------------------------------*/
+
+void vPortSVCHandler( void )
+{
+	__asm volatile (
+ 8013270:	4b07      	ldr	r3, [pc, #28]	; (8013290 <pxCurrentTCBConst2>)
+ 8013272:	6819      	ldr	r1, [r3, #0]
+ 8013274:	6808      	ldr	r0, [r1, #0]
+ 8013276:	e8b0 4ff0 	ldmia.w	r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
+ 801327a:	f380 8809 	msr	PSP, r0
+ 801327e:	f3bf 8f6f 	isb	sy
+ 8013282:	f04f 0000 	mov.w	r0, #0
+ 8013286:	f380 8811 	msr	BASEPRI, r0
+ 801328a:	4770      	bx	lr
+ 801328c:	f3af 8000 	nop.w
+
+08013290 <pxCurrentTCBConst2>:
+ 8013290:	2400bf20 	.word	0x2400bf20
+					"	bx r14							\n"
+					"									\n"
+					"	.align 4						\n"
+					"pxCurrentTCBConst2: .word pxCurrentTCB				\n"
+				);
+}
+ 8013294:	bf00      	nop
+ 8013296:	bf00      	nop
+
+08013298 <prvPortStartFirstTask>:
+{
+	/* Start the first task.  This also clears the bit that indicates the FPU is
+	in use in case the FPU was used before the scheduler was started - which
+	would otherwise result in the unnecessary leaving of space in the SVC stack
+	for lazy saving of FPU registers. */
+	__asm volatile(
+ 8013298:	4808      	ldr	r0, [pc, #32]	; (80132bc <prvPortStartFirstTask+0x24>)
+ 801329a:	6800      	ldr	r0, [r0, #0]
+ 801329c:	6800      	ldr	r0, [r0, #0]
+ 801329e:	f380 8808 	msr	MSP, r0
+ 80132a2:	f04f 0000 	mov.w	r0, #0
+ 80132a6:	f380 8814 	msr	CONTROL, r0
+ 80132aa:	b662      	cpsie	i
+ 80132ac:	b661      	cpsie	f
+ 80132ae:	f3bf 8f4f 	dsb	sy
+ 80132b2:	f3bf 8f6f 	isb	sy
+ 80132b6:	df00      	svc	0
+ 80132b8:	bf00      	nop
+					" dsb					\n"
+					" isb					\n"
+					" svc 0					\n" /* System call to start first task. */
+					" nop					\n"
+				);
+}
+ 80132ba:	bf00      	nop
+ 80132bc:	e000ed08 	.word	0xe000ed08
+
+080132c0 <xPortStartScheduler>:
+
+/*
+ * See header file for description.
+ */
+BaseType_t xPortStartScheduler( void )
+{
+ 80132c0:	b580      	push	{r7, lr}
+ 80132c2:	b086      	sub	sp, #24
+ 80132c4:	af00      	add	r7, sp, #0
+	configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );
+
+	/* This port can be used on all revisions of the Cortex-M7 core other than
+	the r0p1 parts.  r0p1 parts should use the port from the
+	/source/portable/GCC/ARM_CM7/r0p1 directory. */
+	configASSERT( portCPUID != portCORTEX_M7_r0p1_ID );
+ 80132c6:	4b46      	ldr	r3, [pc, #280]	; (80133e0 <xPortStartScheduler+0x120>)
+ 80132c8:	681b      	ldr	r3, [r3, #0]
+ 80132ca:	4a46      	ldr	r2, [pc, #280]	; (80133e4 <xPortStartScheduler+0x124>)
+ 80132cc:	4293      	cmp	r3, r2
+ 80132ce:	d10a      	bne.n	80132e6 <xPortStartScheduler+0x26>
+	__asm volatile
+ 80132d0:	f04f 0350 	mov.w	r3, #80	; 0x50
+ 80132d4:	f383 8811 	msr	BASEPRI, r3
+ 80132d8:	f3bf 8f6f 	isb	sy
+ 80132dc:	f3bf 8f4f 	dsb	sy
+ 80132e0:	613b      	str	r3, [r7, #16]
+}
+ 80132e2:	bf00      	nop
+ 80132e4:	e7fe      	b.n	80132e4 <xPortStartScheduler+0x24>
+	configASSERT( portCPUID != portCORTEX_M7_r0p0_ID );
+ 80132e6:	4b3e      	ldr	r3, [pc, #248]	; (80133e0 <xPortStartScheduler+0x120>)
+ 80132e8:	681b      	ldr	r3, [r3, #0]
+ 80132ea:	4a3f      	ldr	r2, [pc, #252]	; (80133e8 <xPortStartScheduler+0x128>)
+ 80132ec:	4293      	cmp	r3, r2
+ 80132ee:	d10a      	bne.n	8013306 <xPortStartScheduler+0x46>
+	__asm volatile
+ 80132f0:	f04f 0350 	mov.w	r3, #80	; 0x50
+ 80132f4:	f383 8811 	msr	BASEPRI, r3
+ 80132f8:	f3bf 8f6f 	isb	sy
+ 80132fc:	f3bf 8f4f 	dsb	sy
+ 8013300:	60fb      	str	r3, [r7, #12]
+}
+ 8013302:	bf00      	nop
+ 8013304:	e7fe      	b.n	8013304 <xPortStartScheduler+0x44>
+
+	#if( configASSERT_DEFINED == 1 )
+	{
+		volatile uint32_t ulOriginalPriority;
+		volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
+ 8013306:	4b39      	ldr	r3, [pc, #228]	; (80133ec <xPortStartScheduler+0x12c>)
+ 8013308:	617b      	str	r3, [r7, #20]
+		functions can be called.  ISR safe functions are those that end in
+		"FromISR".  FreeRTOS maintains separate thread and ISR API functions to
+		ensure interrupt entry is as fast and simple as possible.
+
+		Save the interrupt priority value that is about to be clobbered. */
+		ulOriginalPriority = *pucFirstUserPriorityRegister;
+ 801330a:	697b      	ldr	r3, [r7, #20]
+ 801330c:	781b      	ldrb	r3, [r3, #0]
+ 801330e:	b2db      	uxtb	r3, r3
+ 8013310:	607b      	str	r3, [r7, #4]
+
+		/* Determine the number of priority bits available.  First write to all
+		possible bits. */
+		*pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
+ 8013312:	697b      	ldr	r3, [r7, #20]
+ 8013314:	22ff      	movs	r2, #255	; 0xff
+ 8013316:	701a      	strb	r2, [r3, #0]
+
+		/* Read the value back to see how many bits stuck. */
+		ucMaxPriorityValue = *pucFirstUserPriorityRegister;
+ 8013318:	697b      	ldr	r3, [r7, #20]
+ 801331a:	781b      	ldrb	r3, [r3, #0]
+ 801331c:	b2db      	uxtb	r3, r3
+ 801331e:	70fb      	strb	r3, [r7, #3]
+
+		/* Use the same mask on the maximum system call priority. */
+		ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
+ 8013320:	78fb      	ldrb	r3, [r7, #3]
+ 8013322:	b2db      	uxtb	r3, r3
+ 8013324:	f003 0350 	and.w	r3, r3, #80	; 0x50
+ 8013328:	b2da      	uxtb	r2, r3
+ 801332a:	4b31      	ldr	r3, [pc, #196]	; (80133f0 <xPortStartScheduler+0x130>)
+ 801332c:	701a      	strb	r2, [r3, #0]
+
+		/* Calculate the maximum acceptable priority group value for the number
+		of bits read back. */
+		ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
+ 801332e:	4b31      	ldr	r3, [pc, #196]	; (80133f4 <xPortStartScheduler+0x134>)
+ 8013330:	2207      	movs	r2, #7
+ 8013332:	601a      	str	r2, [r3, #0]
+		while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
+ 8013334:	e009      	b.n	801334a <xPortStartScheduler+0x8a>
+		{
+			ulMaxPRIGROUPValue--;
+ 8013336:	4b2f      	ldr	r3, [pc, #188]	; (80133f4 <xPortStartScheduler+0x134>)
+ 8013338:	681b      	ldr	r3, [r3, #0]
+ 801333a:	3b01      	subs	r3, #1
+ 801333c:	4a2d      	ldr	r2, [pc, #180]	; (80133f4 <xPortStartScheduler+0x134>)
+ 801333e:	6013      	str	r3, [r2, #0]
+			ucMaxPriorityValue <<= ( uint8_t ) 0x01;
+ 8013340:	78fb      	ldrb	r3, [r7, #3]
+ 8013342:	b2db      	uxtb	r3, r3
+ 8013344:	005b      	lsls	r3, r3, #1
+ 8013346:	b2db      	uxtb	r3, r3
+ 8013348:	70fb      	strb	r3, [r7, #3]
+		while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
+ 801334a:	78fb      	ldrb	r3, [r7, #3]
+ 801334c:	b2db      	uxtb	r3, r3
+ 801334e:	f003 0380 	and.w	r3, r3, #128	; 0x80
+ 8013352:	2b80      	cmp	r3, #128	; 0x80
+ 8013354:	d0ef      	beq.n	8013336 <xPortStartScheduler+0x76>
+		#ifdef configPRIO_BITS
+		{
+			/* Check the FreeRTOS configuration that defines the number of
+			priority bits matches the number of priority bits actually queried
+			from the hardware. */
+			configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
+ 8013356:	4b27      	ldr	r3, [pc, #156]	; (80133f4 <xPortStartScheduler+0x134>)
+ 8013358:	681b      	ldr	r3, [r3, #0]
+ 801335a:	f1c3 0307 	rsb	r3, r3, #7
+ 801335e:	2b04      	cmp	r3, #4
+ 8013360:	d00a      	beq.n	8013378 <xPortStartScheduler+0xb8>
+	__asm volatile
+ 8013362:	f04f 0350 	mov.w	r3, #80	; 0x50
+ 8013366:	f383 8811 	msr	BASEPRI, r3
+ 801336a:	f3bf 8f6f 	isb	sy
+ 801336e:	f3bf 8f4f 	dsb	sy
+ 8013372:	60bb      	str	r3, [r7, #8]
+}
+ 8013374:	bf00      	nop
+ 8013376:	e7fe      	b.n	8013376 <xPortStartScheduler+0xb6>
+		}
+		#endif
+
+		/* Shift the priority group value back to its position within the AIRCR
+		register. */
+		ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
+ 8013378:	4b1e      	ldr	r3, [pc, #120]	; (80133f4 <xPortStartScheduler+0x134>)
+ 801337a:	681b      	ldr	r3, [r3, #0]
+ 801337c:	021b      	lsls	r3, r3, #8
+ 801337e:	4a1d      	ldr	r2, [pc, #116]	; (80133f4 <xPortStartScheduler+0x134>)
+ 8013380:	6013      	str	r3, [r2, #0]
+		ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
+ 8013382:	4b1c      	ldr	r3, [pc, #112]	; (80133f4 <xPortStartScheduler+0x134>)
+ 8013384:	681b      	ldr	r3, [r3, #0]
+ 8013386:	f403 63e0 	and.w	r3, r3, #1792	; 0x700
+ 801338a:	4a1a      	ldr	r2, [pc, #104]	; (80133f4 <xPortStartScheduler+0x134>)
+ 801338c:	6013      	str	r3, [r2, #0]
+
+		/* Restore the clobbered interrupt priority register to its original
+		value. */
+		*pucFirstUserPriorityRegister = ulOriginalPriority;
+ 801338e:	687b      	ldr	r3, [r7, #4]
+ 8013390:	b2da      	uxtb	r2, r3
+ 8013392:	697b      	ldr	r3, [r7, #20]
+ 8013394:	701a      	strb	r2, [r3, #0]
+	}
+	#endif /* conifgASSERT_DEFINED */
+
+	/* Make PendSV and SysTick the lowest priority interrupts. */
+	portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;
+ 8013396:	4b18      	ldr	r3, [pc, #96]	; (80133f8 <xPortStartScheduler+0x138>)
+ 8013398:	681b      	ldr	r3, [r3, #0]
+ 801339a:	4a17      	ldr	r2, [pc, #92]	; (80133f8 <xPortStartScheduler+0x138>)
+ 801339c:	f443 0370 	orr.w	r3, r3, #15728640	; 0xf00000
+ 80133a0:	6013      	str	r3, [r2, #0]
+	portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;
+ 80133a2:	4b15      	ldr	r3, [pc, #84]	; (80133f8 <xPortStartScheduler+0x138>)
+ 80133a4:	681b      	ldr	r3, [r3, #0]
+ 80133a6:	4a14      	ldr	r2, [pc, #80]	; (80133f8 <xPortStartScheduler+0x138>)
+ 80133a8:	f043 4370 	orr.w	r3, r3, #4026531840	; 0xf0000000
+ 80133ac:	6013      	str	r3, [r2, #0]
+
+	/* Start the timer that generates the tick ISR.  Interrupts are disabled
+	here already. */
+	vPortSetupTimerInterrupt();
+ 80133ae:	f000 f8dd 	bl	801356c <vPortSetupTimerInterrupt>
+
+	/* Initialise the critical nesting count ready for the first task. */
+	uxCriticalNesting = 0;
+ 80133b2:	4b12      	ldr	r3, [pc, #72]	; (80133fc <xPortStartScheduler+0x13c>)
+ 80133b4:	2200      	movs	r2, #0
+ 80133b6:	601a      	str	r2, [r3, #0]
+
+	/* Ensure the VFP is enabled - it should be anyway. */
+	vPortEnableVFP();
+ 80133b8:	f000 f8fc 	bl	80135b4 <vPortEnableVFP>
+
+	/* Lazy save always. */
+	*( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;
+ 80133bc:	4b10      	ldr	r3, [pc, #64]	; (8013400 <xPortStartScheduler+0x140>)
+ 80133be:	681b      	ldr	r3, [r3, #0]
+ 80133c0:	4a0f      	ldr	r2, [pc, #60]	; (8013400 <xPortStartScheduler+0x140>)
+ 80133c2:	f043 4340 	orr.w	r3, r3, #3221225472	; 0xc0000000
+ 80133c6:	6013      	str	r3, [r2, #0]
+
+	/* Start the first task. */
+	prvPortStartFirstTask();
+ 80133c8:	f7ff ff66 	bl	8013298 <prvPortStartFirstTask>
+	exit error function to prevent compiler warnings about a static function
+	not being called in the case that the application writer overrides this
+	functionality by defining configTASK_RETURN_ADDRESS.  Call
+	vTaskSwitchContext() so link time optimisation does not remove the
+	symbol. */
+	vTaskSwitchContext();
+ 80133cc:	f7fe feee 	bl	80121ac <vTaskSwitchContext>
+	prvTaskExitError();
+ 80133d0:	f7ff ff22 	bl	8013218 <prvTaskExitError>
+
+	/* Should not get here! */
+	return 0;
+ 80133d4:	2300      	movs	r3, #0
+}
+ 80133d6:	4618      	mov	r0, r3
+ 80133d8:	3718      	adds	r7, #24
+ 80133da:	46bd      	mov	sp, r7
+ 80133dc:	bd80      	pop	{r7, pc}
+ 80133de:	bf00      	nop
+ 80133e0:	e000ed00 	.word	0xe000ed00
+ 80133e4:	410fc271 	.word	0x410fc271
+ 80133e8:	410fc270 	.word	0x410fc270
+ 80133ec:	e000e400 	.word	0xe000e400
+ 80133f0:	2400c148 	.word	0x2400c148
+ 80133f4:	2400c14c 	.word	0x2400c14c
+ 80133f8:	e000ed20 	.word	0xe000ed20
+ 80133fc:	24000038 	.word	0x24000038
+ 8013400:	e000ef34 	.word	0xe000ef34
+
+08013404 <vPortEnterCritical>:
+	configASSERT( uxCriticalNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void )
+{
+ 8013404:	b480      	push	{r7}
+ 8013406:	b083      	sub	sp, #12
+ 8013408:	af00      	add	r7, sp, #0
+	__asm volatile
+ 801340a:	f04f 0350 	mov.w	r3, #80	; 0x50
+ 801340e:	f383 8811 	msr	BASEPRI, r3
+ 8013412:	f3bf 8f6f 	isb	sy
+ 8013416:	f3bf 8f4f 	dsb	sy
+ 801341a:	607b      	str	r3, [r7, #4]
+}
+ 801341c:	bf00      	nop
+	portDISABLE_INTERRUPTS();
+	uxCriticalNesting++;
+ 801341e:	4b0f      	ldr	r3, [pc, #60]	; (801345c <vPortEnterCritical+0x58>)
+ 8013420:	681b      	ldr	r3, [r3, #0]
+ 8013422:	3301      	adds	r3, #1
+ 8013424:	4a0d      	ldr	r2, [pc, #52]	; (801345c <vPortEnterCritical+0x58>)
+ 8013426:	6013      	str	r3, [r2, #0]
+	/* This is not the interrupt safe version of the enter critical function so
+	assert() if it is being called from an interrupt context.  Only API
+	functions that end in "FromISR" can be used in an interrupt.  Only assert if
+	the critical nesting count is 1 to protect against recursive calls if the
+	assert function also uses a critical section. */
+	if( uxCriticalNesting == 1 )
+ 8013428:	4b0c      	ldr	r3, [pc, #48]	; (801345c <vPortEnterCritical+0x58>)
+ 801342a:	681b      	ldr	r3, [r3, #0]
+ 801342c:	2b01      	cmp	r3, #1
+ 801342e:	d10f      	bne.n	8013450 <vPortEnterCritical+0x4c>
+	{
+		configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );
+ 8013430:	4b0b      	ldr	r3, [pc, #44]	; (8013460 <vPortEnterCritical+0x5c>)
+ 8013432:	681b      	ldr	r3, [r3, #0]
+ 8013434:	b2db      	uxtb	r3, r3
+ 8013436:	2b00      	cmp	r3, #0
+ 8013438:	d00a      	beq.n	8013450 <vPortEnterCritical+0x4c>
+	__asm volatile
+ 801343a:	f04f 0350 	mov.w	r3, #80	; 0x50
+ 801343e:	f383 8811 	msr	BASEPRI, r3
+ 8013442:	f3bf 8f6f 	isb	sy
+ 8013446:	f3bf 8f4f 	dsb	sy
+ 801344a:	603b      	str	r3, [r7, #0]
+}
+ 801344c:	bf00      	nop
+ 801344e:	e7fe      	b.n	801344e <vPortEnterCritical+0x4a>
+	}
+}
+ 8013450:	bf00      	nop
+ 8013452:	370c      	adds	r7, #12
+ 8013454:	46bd      	mov	sp, r7
+ 8013456:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 801345a:	4770      	bx	lr
+ 801345c:	24000038 	.word	0x24000038
+ 8013460:	e000ed04 	.word	0xe000ed04
+
+08013464 <vPortExitCritical>:
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void )
+{
+ 8013464:	b480      	push	{r7}
+ 8013466:	b083      	sub	sp, #12
+ 8013468:	af00      	add	r7, sp, #0
+	configASSERT( uxCriticalNesting );
+ 801346a:	4b12      	ldr	r3, [pc, #72]	; (80134b4 <vPortExitCritical+0x50>)
+ 801346c:	681b      	ldr	r3, [r3, #0]
+ 801346e:	2b00      	cmp	r3, #0
+ 8013470:	d10a      	bne.n	8013488 <vPortExitCritical+0x24>
+	__asm volatile
+ 8013472:	f04f 0350 	mov.w	r3, #80	; 0x50
+ 8013476:	f383 8811 	msr	BASEPRI, r3
+ 801347a:	f3bf 8f6f 	isb	sy
+ 801347e:	f3bf 8f4f 	dsb	sy
+ 8013482:	607b      	str	r3, [r7, #4]
+}
+ 8013484:	bf00      	nop
+ 8013486:	e7fe      	b.n	8013486 <vPortExitCritical+0x22>
+	uxCriticalNesting--;
+ 8013488:	4b0a      	ldr	r3, [pc, #40]	; (80134b4 <vPortExitCritical+0x50>)
+ 801348a:	681b      	ldr	r3, [r3, #0]
+ 801348c:	3b01      	subs	r3, #1
+ 801348e:	4a09      	ldr	r2, [pc, #36]	; (80134b4 <vPortExitCritical+0x50>)
+ 8013490:	6013      	str	r3, [r2, #0]
+	if( uxCriticalNesting == 0 )
+ 8013492:	4b08      	ldr	r3, [pc, #32]	; (80134b4 <vPortExitCritical+0x50>)
+ 8013494:	681b      	ldr	r3, [r3, #0]
+ 8013496:	2b00      	cmp	r3, #0
+ 8013498:	d105      	bne.n	80134a6 <vPortExitCritical+0x42>
+ 801349a:	2300      	movs	r3, #0
+ 801349c:	603b      	str	r3, [r7, #0]
+	__asm volatile
+ 801349e:	683b      	ldr	r3, [r7, #0]
+ 80134a0:	f383 8811 	msr	BASEPRI, r3
+}
+ 80134a4:	bf00      	nop
+	{
+		portENABLE_INTERRUPTS();
+	}
+}
+ 80134a6:	bf00      	nop
+ 80134a8:	370c      	adds	r7, #12
+ 80134aa:	46bd      	mov	sp, r7
+ 80134ac:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 80134b0:	4770      	bx	lr
+ 80134b2:	bf00      	nop
+ 80134b4:	24000038 	.word	0x24000038
+	...
+
+080134c0 <PendSV_Handler>:
+
+void xPortPendSVHandler( void )
+{
+	/* This is a naked function. */
+
+	__asm volatile
+ 80134c0:	f3ef 8009 	mrs	r0, PSP
+ 80134c4:	f3bf 8f6f 	isb	sy
+ 80134c8:	4b15      	ldr	r3, [pc, #84]	; (8013520 <pxCurrentTCBConst>)
+ 80134ca:	681a      	ldr	r2, [r3, #0]
+ 80134cc:	f01e 0f10 	tst.w	lr, #16
+ 80134d0:	bf08      	it	eq
+ 80134d2:	ed20 8a10 	vstmdbeq	r0!, {s16-s31}
+ 80134d6:	e920 4ff0 	stmdb	r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
+ 80134da:	6010      	str	r0, [r2, #0]
+ 80134dc:	e92d 0009 	stmdb	sp!, {r0, r3}
+ 80134e0:	f04f 0050 	mov.w	r0, #80	; 0x50
+ 80134e4:	f380 8811 	msr	BASEPRI, r0
+ 80134e8:	f3bf 8f4f 	dsb	sy
+ 80134ec:	f3bf 8f6f 	isb	sy
+ 80134f0:	f7fe fe5c 	bl	80121ac <vTaskSwitchContext>
+ 80134f4:	f04f 0000 	mov.w	r0, #0
+ 80134f8:	f380 8811 	msr	BASEPRI, r0
+ 80134fc:	bc09      	pop	{r0, r3}
+ 80134fe:	6819      	ldr	r1, [r3, #0]
+ 8013500:	6808      	ldr	r0, [r1, #0]
+ 8013502:	e8b0 4ff0 	ldmia.w	r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
+ 8013506:	f01e 0f10 	tst.w	lr, #16
+ 801350a:	bf08      	it	eq
+ 801350c:	ecb0 8a10 	vldmiaeq	r0!, {s16-s31}
+ 8013510:	f380 8809 	msr	PSP, r0
+ 8013514:	f3bf 8f6f 	isb	sy
+ 8013518:	4770      	bx	lr
+ 801351a:	bf00      	nop
+ 801351c:	f3af 8000 	nop.w
+
+08013520 <pxCurrentTCBConst>:
+ 8013520:	2400bf20 	.word	0x2400bf20
+	"										\n"
+	"	.align 4							\n"
+	"pxCurrentTCBConst: .word pxCurrentTCB	\n"
+	::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY)
+	);
+}
+ 8013524:	bf00      	nop
+ 8013526:	bf00      	nop
+
+08013528 <SysTick_Handler>:
+/*-----------------------------------------------------------*/
+
+void xPortSysTickHandler( void )
+{
+ 8013528:	b580      	push	{r7, lr}
+ 801352a:	b082      	sub	sp, #8
+ 801352c:	af00      	add	r7, sp, #0
+	__asm volatile
+ 801352e:	f04f 0350 	mov.w	r3, #80	; 0x50
+ 8013532:	f383 8811 	msr	BASEPRI, r3
+ 8013536:	f3bf 8f6f 	isb	sy
+ 801353a:	f3bf 8f4f 	dsb	sy
+ 801353e:	607b      	str	r3, [r7, #4]
+}
+ 8013540:	bf00      	nop
+	save and then restore the interrupt mask value as its value is already
+	known. */
+	portDISABLE_INTERRUPTS();
+	{
+		/* Increment the RTOS tick. */
+		if( xTaskIncrementTick() != pdFALSE )
+ 8013542:	f7fe fd7b 	bl	801203c <xTaskIncrementTick>
+ 8013546:	4603      	mov	r3, r0
+ 8013548:	2b00      	cmp	r3, #0
+ 801354a:	d003      	beq.n	8013554 <SysTick_Handler+0x2c>
+		{
+			/* A context switch is required.  Context switching is performed in
+			the PendSV interrupt.  Pend the PendSV interrupt. */
+			portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
+ 801354c:	4b06      	ldr	r3, [pc, #24]	; (8013568 <SysTick_Handler+0x40>)
+ 801354e:	f04f 5280 	mov.w	r2, #268435456	; 0x10000000
+ 8013552:	601a      	str	r2, [r3, #0]
+ 8013554:	2300      	movs	r3, #0
+ 8013556:	603b      	str	r3, [r7, #0]
+	__asm volatile
+ 8013558:	683b      	ldr	r3, [r7, #0]
+ 801355a:	f383 8811 	msr	BASEPRI, r3
+}
+ 801355e:	bf00      	nop
+		}
+	}
+	portENABLE_INTERRUPTS();
+}
+ 8013560:	bf00      	nop
+ 8013562:	3708      	adds	r7, #8
+ 8013564:	46bd      	mov	sp, r7
+ 8013566:	bd80      	pop	{r7, pc}
+ 8013568:	e000ed04 	.word	0xe000ed04
+
+0801356c <vPortSetupTimerInterrupt>:
+/*
+ * Setup the systick timer to generate the tick interrupts at the required
+ * frequency.
+ */
+__attribute__(( weak )) void vPortSetupTimerInterrupt( void )
+{
+ 801356c:	b480      	push	{r7}
+ 801356e:	af00      	add	r7, sp, #0
+		ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
+	}
+	#endif /* configUSE_TICKLESS_IDLE */
+
+	/* Stop and clear the SysTick. */
+	portNVIC_SYSTICK_CTRL_REG = 0UL;
+ 8013570:	4b0b      	ldr	r3, [pc, #44]	; (80135a0 <vPortSetupTimerInterrupt+0x34>)
+ 8013572:	2200      	movs	r2, #0
+ 8013574:	601a      	str	r2, [r3, #0]
+	portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+ 8013576:	4b0b      	ldr	r3, [pc, #44]	; (80135a4 <vPortSetupTimerInterrupt+0x38>)
+ 8013578:	2200      	movs	r2, #0
+ 801357a:	601a      	str	r2, [r3, #0]
+
+	/* Configure SysTick to interrupt at the requested rate. */
+	portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
+ 801357c:	4b0a      	ldr	r3, [pc, #40]	; (80135a8 <vPortSetupTimerInterrupt+0x3c>)
+ 801357e:	681b      	ldr	r3, [r3, #0]
+ 8013580:	4a0a      	ldr	r2, [pc, #40]	; (80135ac <vPortSetupTimerInterrupt+0x40>)
+ 8013582:	fba2 2303 	umull	r2, r3, r2, r3
+ 8013586:	099b      	lsrs	r3, r3, #6
+ 8013588:	4a09      	ldr	r2, [pc, #36]	; (80135b0 <vPortSetupTimerInterrupt+0x44>)
+ 801358a:	3b01      	subs	r3, #1
+ 801358c:	6013      	str	r3, [r2, #0]
+	portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
+ 801358e:	4b04      	ldr	r3, [pc, #16]	; (80135a0 <vPortSetupTimerInterrupt+0x34>)
+ 8013590:	2207      	movs	r2, #7
+ 8013592:	601a      	str	r2, [r3, #0]
+}
+ 8013594:	bf00      	nop
+ 8013596:	46bd      	mov	sp, r7
+ 8013598:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 801359c:	4770      	bx	lr
+ 801359e:	bf00      	nop
+ 80135a0:	e000e010 	.word	0xe000e010
+ 80135a4:	e000e018 	.word	0xe000e018
+ 80135a8:	24000014 	.word	0x24000014
+ 80135ac:	10624dd3 	.word	0x10624dd3
+ 80135b0:	e000e014 	.word	0xe000e014
+
+080135b4 <vPortEnableVFP>:
+/*-----------------------------------------------------------*/
+
+/* This is a naked function. */
+static void vPortEnableVFP( void )
+{
+	__asm volatile
+ 80135b4:	f8df 000c 	ldr.w	r0, [pc, #12]	; 80135c4 <vPortEnableVFP+0x10>
+ 80135b8:	6801      	ldr	r1, [r0, #0]
+ 80135ba:	f441 0170 	orr.w	r1, r1, #15728640	; 0xf00000
+ 80135be:	6001      	str	r1, [r0, #0]
+ 80135c0:	4770      	bx	lr
+		"								\n"
+		"	orr r1, r1, #( 0xf << 20 )	\n" /* Enable CP10 and CP11 coprocessors, then save back. */
+		"	str r1, [r0]				\n"
+		"	bx r14						"
+	);
+}
+ 80135c2:	bf00      	nop
+ 80135c4:	e000ed88 	.word	0xe000ed88
+
+080135c8 <vPortValidateInterruptPriority>:
+/*-----------------------------------------------------------*/
+
+#if( configASSERT_DEFINED == 1 )
+
+	void vPortValidateInterruptPriority( void )
+	{
+ 80135c8:	b480      	push	{r7}
+ 80135ca:	b085      	sub	sp, #20
+ 80135cc:	af00      	add	r7, sp, #0
+	uint32_t ulCurrentInterrupt;
+	uint8_t ucCurrentPriority;
+
+		/* Obtain the number of the currently executing interrupt. */
+		__asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" );
+ 80135ce:	f3ef 8305 	mrs	r3, IPSR
+ 80135d2:	60fb      	str	r3, [r7, #12]
+
+		/* Is the interrupt number a user defined interrupt? */
+		if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
+ 80135d4:	68fb      	ldr	r3, [r7, #12]
+ 80135d6:	2b0f      	cmp	r3, #15
+ 80135d8:	d914      	bls.n	8013604 <vPortValidateInterruptPriority+0x3c>
+		{
+			/* Look up the interrupt's priority. */
+			ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
+ 80135da:	4a17      	ldr	r2, [pc, #92]	; (8013638 <vPortValidateInterruptPriority+0x70>)
+ 80135dc:	68fb      	ldr	r3, [r7, #12]
+ 80135de:	4413      	add	r3, r2
+ 80135e0:	781b      	ldrb	r3, [r3, #0]
+ 80135e2:	72fb      	strb	r3, [r7, #11]
+			interrupt entry is as fast and simple as possible.
+
+			The following links provide detailed information:
+			http://www.freertos.org/RTOS-Cortex-M3-M4.html
+			http://www.freertos.org/FAQHelp.html */
+			configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
+ 80135e4:	4b15      	ldr	r3, [pc, #84]	; (801363c <vPortValidateInterruptPriority+0x74>)
+ 80135e6:	781b      	ldrb	r3, [r3, #0]
+ 80135e8:	7afa      	ldrb	r2, [r7, #11]
+ 80135ea:	429a      	cmp	r2, r3
+ 80135ec:	d20a      	bcs.n	8013604 <vPortValidateInterruptPriority+0x3c>
+	__asm volatile
+ 80135ee:	f04f 0350 	mov.w	r3, #80	; 0x50
+ 80135f2:	f383 8811 	msr	BASEPRI, r3
+ 80135f6:	f3bf 8f6f 	isb	sy
+ 80135fa:	f3bf 8f4f 	dsb	sy
+ 80135fe:	607b      	str	r3, [r7, #4]
+}
+ 8013600:	bf00      	nop
+ 8013602:	e7fe      	b.n	8013602 <vPortValidateInterruptPriority+0x3a>
+		configuration then the correct setting can be achieved on all Cortex-M
+		devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
+		scheduler.  Note however that some vendor specific peripheral libraries
+		assume a non-zero priority group setting, in which cases using a value
+		of zero will result in unpredictable behaviour. */
+		configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
+ 8013604:	4b0e      	ldr	r3, [pc, #56]	; (8013640 <vPortValidateInterruptPriority+0x78>)
+ 8013606:	681b      	ldr	r3, [r3, #0]
+ 8013608:	f403 62e0 	and.w	r2, r3, #1792	; 0x700
+ 801360c:	4b0d      	ldr	r3, [pc, #52]	; (8013644 <vPortValidateInterruptPriority+0x7c>)
+ 801360e:	681b      	ldr	r3, [r3, #0]
+ 8013610:	429a      	cmp	r2, r3
+ 8013612:	d90a      	bls.n	801362a <vPortValidateInterruptPriority+0x62>
+	__asm volatile
+ 8013614:	f04f 0350 	mov.w	r3, #80	; 0x50
+ 8013618:	f383 8811 	msr	BASEPRI, r3
+ 801361c:	f3bf 8f6f 	isb	sy
+ 8013620:	f3bf 8f4f 	dsb	sy
+ 8013624:	603b      	str	r3, [r7, #0]
+}
+ 8013626:	bf00      	nop
+ 8013628:	e7fe      	b.n	8013628 <vPortValidateInterruptPriority+0x60>
+	}
+ 801362a:	bf00      	nop
+ 801362c:	3714      	adds	r7, #20
+ 801362e:	46bd      	mov	sp, r7
+ 8013630:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8013634:	4770      	bx	lr
+ 8013636:	bf00      	nop
+ 8013638:	e000e3f0 	.word	0xe000e3f0
+ 801363c:	2400c148 	.word	0x2400c148
+ 8013640:	e000ed0c 	.word	0xe000ed0c
+ 8013644:	2400c14c 	.word	0x2400c14c
+
+08013648 <pvPortMalloc>:
+static size_t xBlockAllocatedBit = 0;
+
+/*-----------------------------------------------------------*/
+
+void *pvPortMalloc( size_t xWantedSize )
+{
+ 8013648:	b580      	push	{r7, lr}
+ 801364a:	b08a      	sub	sp, #40	; 0x28
+ 801364c:	af00      	add	r7, sp, #0
+ 801364e:	6078      	str	r0, [r7, #4]
+BlockLink_t *pxBlock, *pxPreviousBlock, *pxNewBlockLink;
+void *pvReturn = NULL;
+ 8013650:	2300      	movs	r3, #0
+ 8013652:	61fb      	str	r3, [r7, #28]
+
+	vTaskSuspendAll();
+ 8013654:	f7fe fc26 	bl	8011ea4 <vTaskSuspendAll>
+	{
+		/* If this is the first call to malloc then the heap will require
+		initialisation to setup the list of free blocks. */
+		if( pxEnd == NULL )
+ 8013658:	4b5b      	ldr	r3, [pc, #364]	; (80137c8 <pvPortMalloc+0x180>)
+ 801365a:	681b      	ldr	r3, [r3, #0]
+ 801365c:	2b00      	cmp	r3, #0
+ 801365e:	d101      	bne.n	8013664 <pvPortMalloc+0x1c>
+		{
+			prvHeapInit();
+ 8013660:	f000 f920 	bl	80138a4 <prvHeapInit>
+
+		/* Check the requested block size is not so large that the top bit is
+		set.  The top bit of the block size member of the BlockLink_t structure
+		is used to determine who owns the block - the application or the
+		kernel, so it must be free. */
+		if( ( xWantedSize & xBlockAllocatedBit ) == 0 )
+ 8013664:	4b59      	ldr	r3, [pc, #356]	; (80137cc <pvPortMalloc+0x184>)
+ 8013666:	681a      	ldr	r2, [r3, #0]
+ 8013668:	687b      	ldr	r3, [r7, #4]
+ 801366a:	4013      	ands	r3, r2
+ 801366c:	2b00      	cmp	r3, #0
+ 801366e:	f040 8093 	bne.w	8013798 <pvPortMalloc+0x150>
+		{
+			/* The wanted size is increased so it can contain a BlockLink_t
+			structure in addition to the requested amount of bytes. */
+			if( xWantedSize > 0 )
+ 8013672:	687b      	ldr	r3, [r7, #4]
+ 8013674:	2b00      	cmp	r3, #0
+ 8013676:	d01d      	beq.n	80136b4 <pvPortMalloc+0x6c>
+			{
+				xWantedSize += xHeapStructSize;
+ 8013678:	2208      	movs	r2, #8
+ 801367a:	687b      	ldr	r3, [r7, #4]
+ 801367c:	4413      	add	r3, r2
+ 801367e:	607b      	str	r3, [r7, #4]
+
+				/* Ensure that blocks are always aligned to the required number
+				of bytes. */
+				if( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) != 0x00 )
+ 8013680:	687b      	ldr	r3, [r7, #4]
+ 8013682:	f003 0307 	and.w	r3, r3, #7
+ 8013686:	2b00      	cmp	r3, #0
+ 8013688:	d014      	beq.n	80136b4 <pvPortMalloc+0x6c>
+				{
+					/* Byte alignment required. */
+					xWantedSize += ( portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ) );
+ 801368a:	687b      	ldr	r3, [r7, #4]
+ 801368c:	f023 0307 	bic.w	r3, r3, #7
+ 8013690:	3308      	adds	r3, #8
+ 8013692:	607b      	str	r3, [r7, #4]
+					configASSERT( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) == 0 );
+ 8013694:	687b      	ldr	r3, [r7, #4]
+ 8013696:	f003 0307 	and.w	r3, r3, #7
+ 801369a:	2b00      	cmp	r3, #0
+ 801369c:	d00a      	beq.n	80136b4 <pvPortMalloc+0x6c>
+	__asm volatile
+ 801369e:	f04f 0350 	mov.w	r3, #80	; 0x50
+ 80136a2:	f383 8811 	msr	BASEPRI, r3
+ 80136a6:	f3bf 8f6f 	isb	sy
+ 80136aa:	f3bf 8f4f 	dsb	sy
+ 80136ae:	617b      	str	r3, [r7, #20]
+}
+ 80136b0:	bf00      	nop
+ 80136b2:	e7fe      	b.n	80136b2 <pvPortMalloc+0x6a>
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+
+			if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )
+ 80136b4:	687b      	ldr	r3, [r7, #4]
+ 80136b6:	2b00      	cmp	r3, #0
+ 80136b8:	d06e      	beq.n	8013798 <pvPortMalloc+0x150>
+ 80136ba:	4b45      	ldr	r3, [pc, #276]	; (80137d0 <pvPortMalloc+0x188>)
+ 80136bc:	681b      	ldr	r3, [r3, #0]
+ 80136be:	687a      	ldr	r2, [r7, #4]
+ 80136c0:	429a      	cmp	r2, r3
+ 80136c2:	d869      	bhi.n	8013798 <pvPortMalloc+0x150>
+			{
+				/* Traverse the list from the start	(lowest address) block until
+				one	of adequate size is found. */
+				pxPreviousBlock = &xStart;
+ 80136c4:	4b43      	ldr	r3, [pc, #268]	; (80137d4 <pvPortMalloc+0x18c>)
+ 80136c6:	623b      	str	r3, [r7, #32]
+				pxBlock = xStart.pxNextFreeBlock;
+ 80136c8:	4b42      	ldr	r3, [pc, #264]	; (80137d4 <pvPortMalloc+0x18c>)
+ 80136ca:	681b      	ldr	r3, [r3, #0]
+ 80136cc:	627b      	str	r3, [r7, #36]	; 0x24
+				while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )
+ 80136ce:	e004      	b.n	80136da <pvPortMalloc+0x92>
+				{
+					pxPreviousBlock = pxBlock;
+ 80136d0:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 80136d2:	623b      	str	r3, [r7, #32]
+					pxBlock = pxBlock->pxNextFreeBlock;
+ 80136d4:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 80136d6:	681b      	ldr	r3, [r3, #0]
+ 80136d8:	627b      	str	r3, [r7, #36]	; 0x24
+				while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )
+ 80136da:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 80136dc:	685b      	ldr	r3, [r3, #4]
+ 80136de:	687a      	ldr	r2, [r7, #4]
+ 80136e0:	429a      	cmp	r2, r3
+ 80136e2:	d903      	bls.n	80136ec <pvPortMalloc+0xa4>
+ 80136e4:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 80136e6:	681b      	ldr	r3, [r3, #0]
+ 80136e8:	2b00      	cmp	r3, #0
+ 80136ea:	d1f1      	bne.n	80136d0 <pvPortMalloc+0x88>
+				}
+
+				/* If the end marker was reached then a block of adequate size
+				was	not found. */
+				if( pxBlock != pxEnd )
+ 80136ec:	4b36      	ldr	r3, [pc, #216]	; (80137c8 <pvPortMalloc+0x180>)
+ 80136ee:	681b      	ldr	r3, [r3, #0]
+ 80136f0:	6a7a      	ldr	r2, [r7, #36]	; 0x24
+ 80136f2:	429a      	cmp	r2, r3
+ 80136f4:	d050      	beq.n	8013798 <pvPortMalloc+0x150>
+				{
+					/* Return the memory space pointed to - jumping over the
+					BlockLink_t structure at its start. */
+					pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize );
+ 80136f6:	6a3b      	ldr	r3, [r7, #32]
+ 80136f8:	681b      	ldr	r3, [r3, #0]
+ 80136fa:	2208      	movs	r2, #8
+ 80136fc:	4413      	add	r3, r2
+ 80136fe:	61fb      	str	r3, [r7, #28]
+
+					/* This block is being returned for use so must be taken out
+					of the list of free blocks. */
+					pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock;
+ 8013700:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 8013702:	681a      	ldr	r2, [r3, #0]
+ 8013704:	6a3b      	ldr	r3, [r7, #32]
+ 8013706:	601a      	str	r2, [r3, #0]
+
+					/* If the block is larger than required it can be split into
+					two. */
+					if( ( pxBlock->xBlockSize - xWantedSize ) > heapMINIMUM_BLOCK_SIZE )
+ 8013708:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 801370a:	685a      	ldr	r2, [r3, #4]
+ 801370c:	687b      	ldr	r3, [r7, #4]
+ 801370e:	1ad2      	subs	r2, r2, r3
+ 8013710:	2308      	movs	r3, #8
+ 8013712:	005b      	lsls	r3, r3, #1
+ 8013714:	429a      	cmp	r2, r3
+ 8013716:	d91f      	bls.n	8013758 <pvPortMalloc+0x110>
+					{
+						/* This block is to be split into two.  Create a new
+						block following the number of bytes requested. The void
+						cast is used to prevent byte alignment warnings from the
+						compiler. */
+						pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize );
+ 8013718:	6a7a      	ldr	r2, [r7, #36]	; 0x24
+ 801371a:	687b      	ldr	r3, [r7, #4]
+ 801371c:	4413      	add	r3, r2
+ 801371e:	61bb      	str	r3, [r7, #24]
+						configASSERT( ( ( ( size_t ) pxNewBlockLink ) & portBYTE_ALIGNMENT_MASK ) == 0 );
+ 8013720:	69bb      	ldr	r3, [r7, #24]
+ 8013722:	f003 0307 	and.w	r3, r3, #7
+ 8013726:	2b00      	cmp	r3, #0
+ 8013728:	d00a      	beq.n	8013740 <pvPortMalloc+0xf8>
+	__asm volatile
+ 801372a:	f04f 0350 	mov.w	r3, #80	; 0x50
+ 801372e:	f383 8811 	msr	BASEPRI, r3
+ 8013732:	f3bf 8f6f 	isb	sy
+ 8013736:	f3bf 8f4f 	dsb	sy
+ 801373a:	613b      	str	r3, [r7, #16]
+}
+ 801373c:	bf00      	nop
+ 801373e:	e7fe      	b.n	801373e <pvPortMalloc+0xf6>
+
+						/* Calculate the sizes of two blocks split from the
+						single block. */
+						pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;
+ 8013740:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 8013742:	685a      	ldr	r2, [r3, #4]
+ 8013744:	687b      	ldr	r3, [r7, #4]
+ 8013746:	1ad2      	subs	r2, r2, r3
+ 8013748:	69bb      	ldr	r3, [r7, #24]
+ 801374a:	605a      	str	r2, [r3, #4]
+						pxBlock->xBlockSize = xWantedSize;
+ 801374c:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 801374e:	687a      	ldr	r2, [r7, #4]
+ 8013750:	605a      	str	r2, [r3, #4]
+
+						/* Insert the new block into the list of free blocks. */
+						prvInsertBlockIntoFreeList( pxNewBlockLink );
+ 8013752:	69b8      	ldr	r0, [r7, #24]
+ 8013754:	f000 f908 	bl	8013968 <prvInsertBlockIntoFreeList>
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+
+					xFreeBytesRemaining -= pxBlock->xBlockSize;
+ 8013758:	4b1d      	ldr	r3, [pc, #116]	; (80137d0 <pvPortMalloc+0x188>)
+ 801375a:	681a      	ldr	r2, [r3, #0]
+ 801375c:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 801375e:	685b      	ldr	r3, [r3, #4]
+ 8013760:	1ad3      	subs	r3, r2, r3
+ 8013762:	4a1b      	ldr	r2, [pc, #108]	; (80137d0 <pvPortMalloc+0x188>)
+ 8013764:	6013      	str	r3, [r2, #0]
+
+					if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining )
+ 8013766:	4b1a      	ldr	r3, [pc, #104]	; (80137d0 <pvPortMalloc+0x188>)
+ 8013768:	681a      	ldr	r2, [r3, #0]
+ 801376a:	4b1b      	ldr	r3, [pc, #108]	; (80137d8 <pvPortMalloc+0x190>)
+ 801376c:	681b      	ldr	r3, [r3, #0]
+ 801376e:	429a      	cmp	r2, r3
+ 8013770:	d203      	bcs.n	801377a <pvPortMalloc+0x132>
+					{
+						xMinimumEverFreeBytesRemaining = xFreeBytesRemaining;
+ 8013772:	4b17      	ldr	r3, [pc, #92]	; (80137d0 <pvPortMalloc+0x188>)
+ 8013774:	681b      	ldr	r3, [r3, #0]
+ 8013776:	4a18      	ldr	r2, [pc, #96]	; (80137d8 <pvPortMalloc+0x190>)
+ 8013778:	6013      	str	r3, [r2, #0]
+						mtCOVERAGE_TEST_MARKER();
+					}
+
+					/* The block is being returned - it is allocated and owned
+					by the application and has no "next" block. */
+					pxBlock->xBlockSize |= xBlockAllocatedBit;
+ 801377a:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 801377c:	685a      	ldr	r2, [r3, #4]
+ 801377e:	4b13      	ldr	r3, [pc, #76]	; (80137cc <pvPortMalloc+0x184>)
+ 8013780:	681b      	ldr	r3, [r3, #0]
+ 8013782:	431a      	orrs	r2, r3
+ 8013784:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 8013786:	605a      	str	r2, [r3, #4]
+					pxBlock->pxNextFreeBlock = NULL;
+ 8013788:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 801378a:	2200      	movs	r2, #0
+ 801378c:	601a      	str	r2, [r3, #0]
+					xNumberOfSuccessfulAllocations++;
+ 801378e:	4b13      	ldr	r3, [pc, #76]	; (80137dc <pvPortMalloc+0x194>)
+ 8013790:	681b      	ldr	r3, [r3, #0]
+ 8013792:	3301      	adds	r3, #1
+ 8013794:	4a11      	ldr	r2, [pc, #68]	; (80137dc <pvPortMalloc+0x194>)
+ 8013796:	6013      	str	r3, [r2, #0]
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		traceMALLOC( pvReturn, xWantedSize );
+	}
+	( void ) xTaskResumeAll();
+ 8013798:	f7fe fb92 	bl	8011ec0 <xTaskResumeAll>
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	#endif
+
+	configASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) portBYTE_ALIGNMENT_MASK ) == 0 );
+ 801379c:	69fb      	ldr	r3, [r7, #28]
+ 801379e:	f003 0307 	and.w	r3, r3, #7
+ 80137a2:	2b00      	cmp	r3, #0
+ 80137a4:	d00a      	beq.n	80137bc <pvPortMalloc+0x174>
+	__asm volatile
+ 80137a6:	f04f 0350 	mov.w	r3, #80	; 0x50
+ 80137aa:	f383 8811 	msr	BASEPRI, r3
+ 80137ae:	f3bf 8f6f 	isb	sy
+ 80137b2:	f3bf 8f4f 	dsb	sy
+ 80137b6:	60fb      	str	r3, [r7, #12]
+}
+ 80137b8:	bf00      	nop
+ 80137ba:	e7fe      	b.n	80137ba <pvPortMalloc+0x172>
+	return pvReturn;
+ 80137bc:	69fb      	ldr	r3, [r7, #28]
+}
+ 80137be:	4618      	mov	r0, r3
+ 80137c0:	3728      	adds	r7, #40	; 0x28
+ 80137c2:	46bd      	mov	sp, r7
+ 80137c4:	bd80      	pop	{r7, pc}
+ 80137c6:	bf00      	nop
+ 80137c8:	24013958 	.word	0x24013958
+ 80137cc:	2401396c 	.word	0x2401396c
+ 80137d0:	2401395c 	.word	0x2401395c
+ 80137d4:	24013950 	.word	0x24013950
+ 80137d8:	24013960 	.word	0x24013960
+ 80137dc:	24013964 	.word	0x24013964
+
+080137e0 <vPortFree>:
+/*-----------------------------------------------------------*/
+
+void vPortFree( void *pv )
+{
+ 80137e0:	b580      	push	{r7, lr}
+ 80137e2:	b086      	sub	sp, #24
+ 80137e4:	af00      	add	r7, sp, #0
+ 80137e6:	6078      	str	r0, [r7, #4]
+uint8_t *puc = ( uint8_t * ) pv;
+ 80137e8:	687b      	ldr	r3, [r7, #4]
+ 80137ea:	617b      	str	r3, [r7, #20]
+BlockLink_t *pxLink;
+
+	if( pv != NULL )
+ 80137ec:	687b      	ldr	r3, [r7, #4]
+ 80137ee:	2b00      	cmp	r3, #0
+ 80137f0:	d04d      	beq.n	801388e <vPortFree+0xae>
+	{
+		/* The memory being freed will have an BlockLink_t structure immediately
+		before it. */
+		puc -= xHeapStructSize;
+ 80137f2:	2308      	movs	r3, #8
+ 80137f4:	425b      	negs	r3, r3
+ 80137f6:	697a      	ldr	r2, [r7, #20]
+ 80137f8:	4413      	add	r3, r2
+ 80137fa:	617b      	str	r3, [r7, #20]
+
+		/* This casting is to keep the compiler from issuing warnings. */
+		pxLink = ( void * ) puc;
+ 80137fc:	697b      	ldr	r3, [r7, #20]
+ 80137fe:	613b      	str	r3, [r7, #16]
+
+		/* Check the block is actually allocated. */
+		configASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 );
+ 8013800:	693b      	ldr	r3, [r7, #16]
+ 8013802:	685a      	ldr	r2, [r3, #4]
+ 8013804:	4b24      	ldr	r3, [pc, #144]	; (8013898 <vPortFree+0xb8>)
+ 8013806:	681b      	ldr	r3, [r3, #0]
+ 8013808:	4013      	ands	r3, r2
+ 801380a:	2b00      	cmp	r3, #0
+ 801380c:	d10a      	bne.n	8013824 <vPortFree+0x44>
+	__asm volatile
+ 801380e:	f04f 0350 	mov.w	r3, #80	; 0x50
+ 8013812:	f383 8811 	msr	BASEPRI, r3
+ 8013816:	f3bf 8f6f 	isb	sy
+ 801381a:	f3bf 8f4f 	dsb	sy
+ 801381e:	60fb      	str	r3, [r7, #12]
+}
+ 8013820:	bf00      	nop
+ 8013822:	e7fe      	b.n	8013822 <vPortFree+0x42>
+		configASSERT( pxLink->pxNextFreeBlock == NULL );
+ 8013824:	693b      	ldr	r3, [r7, #16]
+ 8013826:	681b      	ldr	r3, [r3, #0]
+ 8013828:	2b00      	cmp	r3, #0
+ 801382a:	d00a      	beq.n	8013842 <vPortFree+0x62>
+	__asm volatile
+ 801382c:	f04f 0350 	mov.w	r3, #80	; 0x50
+ 8013830:	f383 8811 	msr	BASEPRI, r3
+ 8013834:	f3bf 8f6f 	isb	sy
+ 8013838:	f3bf 8f4f 	dsb	sy
+ 801383c:	60bb      	str	r3, [r7, #8]
+}
+ 801383e:	bf00      	nop
+ 8013840:	e7fe      	b.n	8013840 <vPortFree+0x60>
+
+		if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 )
+ 8013842:	693b      	ldr	r3, [r7, #16]
+ 8013844:	685a      	ldr	r2, [r3, #4]
+ 8013846:	4b14      	ldr	r3, [pc, #80]	; (8013898 <vPortFree+0xb8>)
+ 8013848:	681b      	ldr	r3, [r3, #0]
+ 801384a:	4013      	ands	r3, r2
+ 801384c:	2b00      	cmp	r3, #0
+ 801384e:	d01e      	beq.n	801388e <vPortFree+0xae>
+		{
+			if( pxLink->pxNextFreeBlock == NULL )
+ 8013850:	693b      	ldr	r3, [r7, #16]
+ 8013852:	681b      	ldr	r3, [r3, #0]
+ 8013854:	2b00      	cmp	r3, #0
+ 8013856:	d11a      	bne.n	801388e <vPortFree+0xae>
+			{
+				/* The block is being returned to the heap - it is no longer
+				allocated. */
+				pxLink->xBlockSize &= ~xBlockAllocatedBit;
+ 8013858:	693b      	ldr	r3, [r7, #16]
+ 801385a:	685a      	ldr	r2, [r3, #4]
+ 801385c:	4b0e      	ldr	r3, [pc, #56]	; (8013898 <vPortFree+0xb8>)
+ 801385e:	681b      	ldr	r3, [r3, #0]
+ 8013860:	43db      	mvns	r3, r3
+ 8013862:	401a      	ands	r2, r3
+ 8013864:	693b      	ldr	r3, [r7, #16]
+ 8013866:	605a      	str	r2, [r3, #4]
+
+				vTaskSuspendAll();
+ 8013868:	f7fe fb1c 	bl	8011ea4 <vTaskSuspendAll>
+				{
+					/* Add this block to the list of free blocks. */
+					xFreeBytesRemaining += pxLink->xBlockSize;
+ 801386c:	693b      	ldr	r3, [r7, #16]
+ 801386e:	685a      	ldr	r2, [r3, #4]
+ 8013870:	4b0a      	ldr	r3, [pc, #40]	; (801389c <vPortFree+0xbc>)
+ 8013872:	681b      	ldr	r3, [r3, #0]
+ 8013874:	4413      	add	r3, r2
+ 8013876:	4a09      	ldr	r2, [pc, #36]	; (801389c <vPortFree+0xbc>)
+ 8013878:	6013      	str	r3, [r2, #0]
+					traceFREE( pv, pxLink->xBlockSize );
+					prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) );
+ 801387a:	6938      	ldr	r0, [r7, #16]
+ 801387c:	f000 f874 	bl	8013968 <prvInsertBlockIntoFreeList>
+					xNumberOfSuccessfulFrees++;
+ 8013880:	4b07      	ldr	r3, [pc, #28]	; (80138a0 <vPortFree+0xc0>)
+ 8013882:	681b      	ldr	r3, [r3, #0]
+ 8013884:	3301      	adds	r3, #1
+ 8013886:	4a06      	ldr	r2, [pc, #24]	; (80138a0 <vPortFree+0xc0>)
+ 8013888:	6013      	str	r3, [r2, #0]
+				}
+				( void ) xTaskResumeAll();
+ 801388a:	f7fe fb19 	bl	8011ec0 <xTaskResumeAll>
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+}
+ 801388e:	bf00      	nop
+ 8013890:	3718      	adds	r7, #24
+ 8013892:	46bd      	mov	sp, r7
+ 8013894:	bd80      	pop	{r7, pc}
+ 8013896:	bf00      	nop
+ 8013898:	2401396c 	.word	0x2401396c
+ 801389c:	2401395c 	.word	0x2401395c
+ 80138a0:	24013968 	.word	0x24013968
+
+080138a4 <prvHeapInit>:
+	/* This just exists to keep the linker quiet. */
+}
+/*-----------------------------------------------------------*/
+
+static void prvHeapInit( void )
+{
+ 80138a4:	b480      	push	{r7}
+ 80138a6:	b085      	sub	sp, #20
+ 80138a8:	af00      	add	r7, sp, #0
+BlockLink_t *pxFirstFreeBlock;
+uint8_t *pucAlignedHeap;
+size_t uxAddress;
+size_t xTotalHeapSize = configTOTAL_HEAP_SIZE;
+ 80138aa:	f44f 43f0 	mov.w	r3, #30720	; 0x7800
+ 80138ae:	60bb      	str	r3, [r7, #8]
+
+	/* Ensure the heap starts on a correctly aligned boundary. */
+	uxAddress = ( size_t ) ucHeap;
+ 80138b0:	4b27      	ldr	r3, [pc, #156]	; (8013950 <prvHeapInit+0xac>)
+ 80138b2:	60fb      	str	r3, [r7, #12]
+
+	if( ( uxAddress & portBYTE_ALIGNMENT_MASK ) != 0 )
+ 80138b4:	68fb      	ldr	r3, [r7, #12]
+ 80138b6:	f003 0307 	and.w	r3, r3, #7
+ 80138ba:	2b00      	cmp	r3, #0
+ 80138bc:	d00c      	beq.n	80138d8 <prvHeapInit+0x34>
+	{
+		uxAddress += ( portBYTE_ALIGNMENT - 1 );
+ 80138be:	68fb      	ldr	r3, [r7, #12]
+ 80138c0:	3307      	adds	r3, #7
+ 80138c2:	60fb      	str	r3, [r7, #12]
+		uxAddress &= ~( ( size_t ) portBYTE_ALIGNMENT_MASK );
+ 80138c4:	68fb      	ldr	r3, [r7, #12]
+ 80138c6:	f023 0307 	bic.w	r3, r3, #7
+ 80138ca:	60fb      	str	r3, [r7, #12]
+		xTotalHeapSize -= uxAddress - ( size_t ) ucHeap;
+ 80138cc:	68ba      	ldr	r2, [r7, #8]
+ 80138ce:	68fb      	ldr	r3, [r7, #12]
+ 80138d0:	1ad3      	subs	r3, r2, r3
+ 80138d2:	4a1f      	ldr	r2, [pc, #124]	; (8013950 <prvHeapInit+0xac>)
+ 80138d4:	4413      	add	r3, r2
+ 80138d6:	60bb      	str	r3, [r7, #8]
+	}
+
+	pucAlignedHeap = ( uint8_t * ) uxAddress;
+ 80138d8:	68fb      	ldr	r3, [r7, #12]
+ 80138da:	607b      	str	r3, [r7, #4]
+
+	/* xStart is used to hold a pointer to the first item in the list of free
+	blocks.  The void cast is used to prevent compiler warnings. */
+	xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap;
+ 80138dc:	4a1d      	ldr	r2, [pc, #116]	; (8013954 <prvHeapInit+0xb0>)
+ 80138de:	687b      	ldr	r3, [r7, #4]
+ 80138e0:	6013      	str	r3, [r2, #0]
+	xStart.xBlockSize = ( size_t ) 0;
+ 80138e2:	4b1c      	ldr	r3, [pc, #112]	; (8013954 <prvHeapInit+0xb0>)
+ 80138e4:	2200      	movs	r2, #0
+ 80138e6:	605a      	str	r2, [r3, #4]
+
+	/* pxEnd is used to mark the end of the list of free blocks and is inserted
+	at the end of the heap space. */
+	uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize;
+ 80138e8:	687b      	ldr	r3, [r7, #4]
+ 80138ea:	68ba      	ldr	r2, [r7, #8]
+ 80138ec:	4413      	add	r3, r2
+ 80138ee:	60fb      	str	r3, [r7, #12]
+	uxAddress -= xHeapStructSize;
+ 80138f0:	2208      	movs	r2, #8
+ 80138f2:	68fb      	ldr	r3, [r7, #12]
+ 80138f4:	1a9b      	subs	r3, r3, r2
+ 80138f6:	60fb      	str	r3, [r7, #12]
+	uxAddress &= ~( ( size_t ) portBYTE_ALIGNMENT_MASK );
+ 80138f8:	68fb      	ldr	r3, [r7, #12]
+ 80138fa:	f023 0307 	bic.w	r3, r3, #7
+ 80138fe:	60fb      	str	r3, [r7, #12]
+	pxEnd = ( void * ) uxAddress;
+ 8013900:	68fb      	ldr	r3, [r7, #12]
+ 8013902:	4a15      	ldr	r2, [pc, #84]	; (8013958 <prvHeapInit+0xb4>)
+ 8013904:	6013      	str	r3, [r2, #0]
+	pxEnd->xBlockSize = 0;
+ 8013906:	4b14      	ldr	r3, [pc, #80]	; (8013958 <prvHeapInit+0xb4>)
+ 8013908:	681b      	ldr	r3, [r3, #0]
+ 801390a:	2200      	movs	r2, #0
+ 801390c:	605a      	str	r2, [r3, #4]
+	pxEnd->pxNextFreeBlock = NULL;
+ 801390e:	4b12      	ldr	r3, [pc, #72]	; (8013958 <prvHeapInit+0xb4>)
+ 8013910:	681b      	ldr	r3, [r3, #0]
+ 8013912:	2200      	movs	r2, #0
+ 8013914:	601a      	str	r2, [r3, #0]
+
+	/* To start with there is a single free block that is sized to take up the
+	entire heap space, minus the space taken by pxEnd. */
+	pxFirstFreeBlock = ( void * ) pucAlignedHeap;
+ 8013916:	687b      	ldr	r3, [r7, #4]
+ 8013918:	603b      	str	r3, [r7, #0]
+	pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock;
+ 801391a:	683b      	ldr	r3, [r7, #0]
+ 801391c:	68fa      	ldr	r2, [r7, #12]
+ 801391e:	1ad2      	subs	r2, r2, r3
+ 8013920:	683b      	ldr	r3, [r7, #0]
+ 8013922:	605a      	str	r2, [r3, #4]
+	pxFirstFreeBlock->pxNextFreeBlock = pxEnd;
+ 8013924:	4b0c      	ldr	r3, [pc, #48]	; (8013958 <prvHeapInit+0xb4>)
+ 8013926:	681a      	ldr	r2, [r3, #0]
+ 8013928:	683b      	ldr	r3, [r7, #0]
+ 801392a:	601a      	str	r2, [r3, #0]
+
+	/* Only one block exists - and it covers the entire usable heap space. */
+	xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
+ 801392c:	683b      	ldr	r3, [r7, #0]
+ 801392e:	685b      	ldr	r3, [r3, #4]
+ 8013930:	4a0a      	ldr	r2, [pc, #40]	; (801395c <prvHeapInit+0xb8>)
+ 8013932:	6013      	str	r3, [r2, #0]
+	xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
+ 8013934:	683b      	ldr	r3, [r7, #0]
+ 8013936:	685b      	ldr	r3, [r3, #4]
+ 8013938:	4a09      	ldr	r2, [pc, #36]	; (8013960 <prvHeapInit+0xbc>)
+ 801393a:	6013      	str	r3, [r2, #0]
+
+	/* Work out the position of the top bit in a size_t variable. */
+	xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * heapBITS_PER_BYTE ) - 1 );
+ 801393c:	4b09      	ldr	r3, [pc, #36]	; (8013964 <prvHeapInit+0xc0>)
+ 801393e:	f04f 4200 	mov.w	r2, #2147483648	; 0x80000000
+ 8013942:	601a      	str	r2, [r3, #0]
+}
+ 8013944:	bf00      	nop
+ 8013946:	3714      	adds	r7, #20
+ 8013948:	46bd      	mov	sp, r7
+ 801394a:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 801394e:	4770      	bx	lr
+ 8013950:	2400c150 	.word	0x2400c150
+ 8013954:	24013950 	.word	0x24013950
+ 8013958:	24013958 	.word	0x24013958
+ 801395c:	24013960 	.word	0x24013960
+ 8013960:	2401395c 	.word	0x2401395c
+ 8013964:	2401396c 	.word	0x2401396c
+
+08013968 <prvInsertBlockIntoFreeList>:
+/*-----------------------------------------------------------*/
+
+static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert )
+{
+ 8013968:	b480      	push	{r7}
+ 801396a:	b085      	sub	sp, #20
+ 801396c:	af00      	add	r7, sp, #0
+ 801396e:	6078      	str	r0, [r7, #4]
+BlockLink_t *pxIterator;
+uint8_t *puc;
+
+	/* Iterate through the list until a block is found that has a higher address
+	than the block being inserted. */
+	for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock )
+ 8013970:	4b28      	ldr	r3, [pc, #160]	; (8013a14 <prvInsertBlockIntoFreeList+0xac>)
+ 8013972:	60fb      	str	r3, [r7, #12]
+ 8013974:	e002      	b.n	801397c <prvInsertBlockIntoFreeList+0x14>
+ 8013976:	68fb      	ldr	r3, [r7, #12]
+ 8013978:	681b      	ldr	r3, [r3, #0]
+ 801397a:	60fb      	str	r3, [r7, #12]
+ 801397c:	68fb      	ldr	r3, [r7, #12]
+ 801397e:	681b      	ldr	r3, [r3, #0]
+ 8013980:	687a      	ldr	r2, [r7, #4]
+ 8013982:	429a      	cmp	r2, r3
+ 8013984:	d8f7      	bhi.n	8013976 <prvInsertBlockIntoFreeList+0xe>
+		/* Nothing to do here, just iterate to the right position. */
+	}
+
+	/* Do the block being inserted, and the block it is being inserted after
+	make a contiguous block of memory? */
+	puc = ( uint8_t * ) pxIterator;
+ 8013986:	68fb      	ldr	r3, [r7, #12]
+ 8013988:	60bb      	str	r3, [r7, #8]
+	if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert )
+ 801398a:	68fb      	ldr	r3, [r7, #12]
+ 801398c:	685b      	ldr	r3, [r3, #4]
+ 801398e:	68ba      	ldr	r2, [r7, #8]
+ 8013990:	4413      	add	r3, r2
+ 8013992:	687a      	ldr	r2, [r7, #4]
+ 8013994:	429a      	cmp	r2, r3
+ 8013996:	d108      	bne.n	80139aa <prvInsertBlockIntoFreeList+0x42>
+	{
+		pxIterator->xBlockSize += pxBlockToInsert->xBlockSize;
+ 8013998:	68fb      	ldr	r3, [r7, #12]
+ 801399a:	685a      	ldr	r2, [r3, #4]
+ 801399c:	687b      	ldr	r3, [r7, #4]
+ 801399e:	685b      	ldr	r3, [r3, #4]
+ 80139a0:	441a      	add	r2, r3
+ 80139a2:	68fb      	ldr	r3, [r7, #12]
+ 80139a4:	605a      	str	r2, [r3, #4]
+		pxBlockToInsert = pxIterator;
+ 80139a6:	68fb      	ldr	r3, [r7, #12]
+ 80139a8:	607b      	str	r3, [r7, #4]
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	/* Do the block being inserted, and the block it is being inserted before
+	make a contiguous block of memory? */
+	puc = ( uint8_t * ) pxBlockToInsert;
+ 80139aa:	687b      	ldr	r3, [r7, #4]
+ 80139ac:	60bb      	str	r3, [r7, #8]
+	if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock )
+ 80139ae:	687b      	ldr	r3, [r7, #4]
+ 80139b0:	685b      	ldr	r3, [r3, #4]
+ 80139b2:	68ba      	ldr	r2, [r7, #8]
+ 80139b4:	441a      	add	r2, r3
+ 80139b6:	68fb      	ldr	r3, [r7, #12]
+ 80139b8:	681b      	ldr	r3, [r3, #0]
+ 80139ba:	429a      	cmp	r2, r3
+ 80139bc:	d118      	bne.n	80139f0 <prvInsertBlockIntoFreeList+0x88>
+	{
+		if( pxIterator->pxNextFreeBlock != pxEnd )
+ 80139be:	68fb      	ldr	r3, [r7, #12]
+ 80139c0:	681a      	ldr	r2, [r3, #0]
+ 80139c2:	4b15      	ldr	r3, [pc, #84]	; (8013a18 <prvInsertBlockIntoFreeList+0xb0>)
+ 80139c4:	681b      	ldr	r3, [r3, #0]
+ 80139c6:	429a      	cmp	r2, r3
+ 80139c8:	d00d      	beq.n	80139e6 <prvInsertBlockIntoFreeList+0x7e>
+		{
+			/* Form one big block from the two blocks. */
+			pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize;
+ 80139ca:	687b      	ldr	r3, [r7, #4]
+ 80139cc:	685a      	ldr	r2, [r3, #4]
+ 80139ce:	68fb      	ldr	r3, [r7, #12]
+ 80139d0:	681b      	ldr	r3, [r3, #0]
+ 80139d2:	685b      	ldr	r3, [r3, #4]
+ 80139d4:	441a      	add	r2, r3
+ 80139d6:	687b      	ldr	r3, [r7, #4]
+ 80139d8:	605a      	str	r2, [r3, #4]
+			pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock;
+ 80139da:	68fb      	ldr	r3, [r7, #12]
+ 80139dc:	681b      	ldr	r3, [r3, #0]
+ 80139de:	681a      	ldr	r2, [r3, #0]
+ 80139e0:	687b      	ldr	r3, [r7, #4]
+ 80139e2:	601a      	str	r2, [r3, #0]
+ 80139e4:	e008      	b.n	80139f8 <prvInsertBlockIntoFreeList+0x90>
+		}
+		else
+		{
+			pxBlockToInsert->pxNextFreeBlock = pxEnd;
+ 80139e6:	4b0c      	ldr	r3, [pc, #48]	; (8013a18 <prvInsertBlockIntoFreeList+0xb0>)
+ 80139e8:	681a      	ldr	r2, [r3, #0]
+ 80139ea:	687b      	ldr	r3, [r7, #4]
+ 80139ec:	601a      	str	r2, [r3, #0]
+ 80139ee:	e003      	b.n	80139f8 <prvInsertBlockIntoFreeList+0x90>
+		}
+	}
+	else
+	{
+		pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;
+ 80139f0:	68fb      	ldr	r3, [r7, #12]
+ 80139f2:	681a      	ldr	r2, [r3, #0]
+ 80139f4:	687b      	ldr	r3, [r7, #4]
+ 80139f6:	601a      	str	r2, [r3, #0]
+
+	/* If the block being inserted plugged a gab, so was merged with the block
+	before and the block after, then it's pxNextFreeBlock pointer will have
+	already been set, and should not be set here as that would make it point
+	to itself. */
+	if( pxIterator != pxBlockToInsert )
+ 80139f8:	68fa      	ldr	r2, [r7, #12]
+ 80139fa:	687b      	ldr	r3, [r7, #4]
+ 80139fc:	429a      	cmp	r2, r3
+ 80139fe:	d002      	beq.n	8013a06 <prvInsertBlockIntoFreeList+0x9e>
+	{
+		pxIterator->pxNextFreeBlock = pxBlockToInsert;
+ 8013a00:	68fb      	ldr	r3, [r7, #12]
+ 8013a02:	687a      	ldr	r2, [r7, #4]
+ 8013a04:	601a      	str	r2, [r3, #0]
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+}
+ 8013a06:	bf00      	nop
+ 8013a08:	3714      	adds	r7, #20
+ 8013a0a:	46bd      	mov	sp, r7
+ 8013a0c:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8013a10:	4770      	bx	lr
+ 8013a12:	bf00      	nop
+ 8013a14:	24013950 	.word	0x24013950
+ 8013a18:	24013958 	.word	0x24013958
+
+08013a1c <netconn_apimsg>:
+ * @param apimsg a struct containing the function to call and its parameters
+ * @return ERR_OK if the function was called, another err_t if not
+ */
+static err_t
+netconn_apimsg(tcpip_callback_fn fn, struct api_msg *apimsg)
+{
+ 8013a1c:	b580      	push	{r7, lr}
+ 8013a1e:	b084      	sub	sp, #16
+ 8013a20:	af00      	add	r7, sp, #0
+ 8013a22:	6078      	str	r0, [r7, #4]
+ 8013a24:	6039      	str	r1, [r7, #0]
+  err_t err;
+
+#ifdef LWIP_DEBUG
+  /* catch functions that don't set err */
+  apimsg->err = ERR_VAL;
+ 8013a26:	683b      	ldr	r3, [r7, #0]
+ 8013a28:	22fa      	movs	r2, #250	; 0xfa
+ 8013a2a:	711a      	strb	r2, [r3, #4]
+
+#if LWIP_NETCONN_SEM_PER_THREAD
+  apimsg->op_completed_sem = LWIP_NETCONN_THREAD_SEM_GET();
+#endif /* LWIP_NETCONN_SEM_PER_THREAD */
+
+  err = tcpip_send_msg_wait_sem(fn, apimsg, LWIP_API_MSG_SEM(apimsg));
+ 8013a2c:	683b      	ldr	r3, [r7, #0]
+ 8013a2e:	681b      	ldr	r3, [r3, #0]
+ 8013a30:	330c      	adds	r3, #12
+ 8013a32:	461a      	mov	r2, r3
+ 8013a34:	6839      	ldr	r1, [r7, #0]
+ 8013a36:	6878      	ldr	r0, [r7, #4]
+ 8013a38:	f002 fa22 	bl	8015e80 <tcpip_send_msg_wait_sem>
+ 8013a3c:	4603      	mov	r3, r0
+ 8013a3e:	73fb      	strb	r3, [r7, #15]
+  if (err == ERR_OK) {
+ 8013a40:	f997 300f 	ldrsb.w	r3, [r7, #15]
+ 8013a44:	2b00      	cmp	r3, #0
+ 8013a46:	d103      	bne.n	8013a50 <netconn_apimsg+0x34>
+    return apimsg->err;
+ 8013a48:	683b      	ldr	r3, [r7, #0]
+ 8013a4a:	f993 3004 	ldrsb.w	r3, [r3, #4]
+ 8013a4e:	e001      	b.n	8013a54 <netconn_apimsg+0x38>
+  }
+  return err;
+ 8013a50:	f997 300f 	ldrsb.w	r3, [r7, #15]
+}
+ 8013a54:	4618      	mov	r0, r3
+ 8013a56:	3710      	adds	r7, #16
+ 8013a58:	46bd      	mov	sp, r7
+ 8013a5a:	bd80      	pop	{r7, pc}
+
+08013a5c <netconn_new_with_proto_and_callback>:
+ * @return a newly allocated struct netconn or
+ *         NULL on memory error
+ */
+struct netconn *
+netconn_new_with_proto_and_callback(enum netconn_type t, u8_t proto, netconn_callback callback)
+{
+ 8013a5c:	b580      	push	{r7, lr}
+ 8013a5e:	b08c      	sub	sp, #48	; 0x30
+ 8013a60:	af00      	add	r7, sp, #0
+ 8013a62:	4603      	mov	r3, r0
+ 8013a64:	603a      	str	r2, [r7, #0]
+ 8013a66:	71fb      	strb	r3, [r7, #7]
+ 8013a68:	460b      	mov	r3, r1
+ 8013a6a:	71bb      	strb	r3, [r7, #6]
+  struct netconn *conn;
+  API_MSG_VAR_DECLARE(msg);
+  API_MSG_VAR_ALLOC_RETURN_NULL(msg);
+
+  conn = netconn_alloc(t, callback);
+ 8013a6c:	79fb      	ldrb	r3, [r7, #7]
+ 8013a6e:	6839      	ldr	r1, [r7, #0]
+ 8013a70:	4618      	mov	r0, r3
+ 8013a72:	f000 ffeb 	bl	8014a4c <netconn_alloc>
+ 8013a76:	62f8      	str	r0, [r7, #44]	; 0x2c
+  if (conn != NULL) {
+ 8013a78:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 8013a7a:	2b00      	cmp	r3, #0
+ 8013a7c:	d054      	beq.n	8013b28 <netconn_new_with_proto_and_callback+0xcc>
+    err_t err;
+
+    API_MSG_VAR_REF(msg).msg.n.proto = proto;
+ 8013a7e:	79bb      	ldrb	r3, [r7, #6]
+ 8013a80:	743b      	strb	r3, [r7, #16]
+    API_MSG_VAR_REF(msg).conn = conn;
+ 8013a82:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 8013a84:	60bb      	str	r3, [r7, #8]
+    err = netconn_apimsg(lwip_netconn_do_newconn, &API_MSG_VAR_REF(msg));
+ 8013a86:	f107 0308 	add.w	r3, r7, #8
+ 8013a8a:	4619      	mov	r1, r3
+ 8013a8c:	4829      	ldr	r0, [pc, #164]	; (8013b34 <netconn_new_with_proto_and_callback+0xd8>)
+ 8013a8e:	f7ff ffc5 	bl	8013a1c <netconn_apimsg>
+ 8013a92:	4603      	mov	r3, r0
+ 8013a94:	f887 302b 	strb.w	r3, [r7, #43]	; 0x2b
+    if (err != ERR_OK) {
+ 8013a98:	f997 302b 	ldrsb.w	r3, [r7, #43]	; 0x2b
+ 8013a9c:	2b00      	cmp	r3, #0
+ 8013a9e:	d043      	beq.n	8013b28 <netconn_new_with_proto_and_callback+0xcc>
+      LWIP_ASSERT("freeing conn without freeing pcb", conn->pcb.tcp == NULL);
+ 8013aa0:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 8013aa2:	685b      	ldr	r3, [r3, #4]
+ 8013aa4:	2b00      	cmp	r3, #0
+ 8013aa6:	d005      	beq.n	8013ab4 <netconn_new_with_proto_and_callback+0x58>
+ 8013aa8:	4b23      	ldr	r3, [pc, #140]	; (8013b38 <netconn_new_with_proto_and_callback+0xdc>)
+ 8013aaa:	22a3      	movs	r2, #163	; 0xa3
+ 8013aac:	4923      	ldr	r1, [pc, #140]	; (8013b3c <netconn_new_with_proto_and_callback+0xe0>)
+ 8013aae:	4824      	ldr	r0, [pc, #144]	; (8013b40 <netconn_new_with_proto_and_callback+0xe4>)
+ 8013ab0:	f00d ff6a 	bl	8021988 <iprintf>
+      LWIP_ASSERT("conn has no recvmbox", sys_mbox_valid(&conn->recvmbox));
+ 8013ab4:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 8013ab6:	3310      	adds	r3, #16
+ 8013ab8:	4618      	mov	r0, r3
+ 8013aba:	f00d fcb0 	bl	802141e <sys_mbox_valid>
+ 8013abe:	4603      	mov	r3, r0
+ 8013ac0:	2b00      	cmp	r3, #0
+ 8013ac2:	d105      	bne.n	8013ad0 <netconn_new_with_proto_and_callback+0x74>
+ 8013ac4:	4b1c      	ldr	r3, [pc, #112]	; (8013b38 <netconn_new_with_proto_and_callback+0xdc>)
+ 8013ac6:	22a4      	movs	r2, #164	; 0xa4
+ 8013ac8:	491e      	ldr	r1, [pc, #120]	; (8013b44 <netconn_new_with_proto_and_callback+0xe8>)
+ 8013aca:	481d      	ldr	r0, [pc, #116]	; (8013b40 <netconn_new_with_proto_and_callback+0xe4>)
+ 8013acc:	f00d ff5c 	bl	8021988 <iprintf>
+#if LWIP_TCP
+      LWIP_ASSERT("conn->acceptmbox shouldn't exist", !sys_mbox_valid(&conn->acceptmbox));
+ 8013ad0:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 8013ad2:	3314      	adds	r3, #20
+ 8013ad4:	4618      	mov	r0, r3
+ 8013ad6:	f00d fca2 	bl	802141e <sys_mbox_valid>
+ 8013ada:	4603      	mov	r3, r0
+ 8013adc:	2b00      	cmp	r3, #0
+ 8013ade:	d005      	beq.n	8013aec <netconn_new_with_proto_and_callback+0x90>
+ 8013ae0:	4b15      	ldr	r3, [pc, #84]	; (8013b38 <netconn_new_with_proto_and_callback+0xdc>)
+ 8013ae2:	22a6      	movs	r2, #166	; 0xa6
+ 8013ae4:	4918      	ldr	r1, [pc, #96]	; (8013b48 <netconn_new_with_proto_and_callback+0xec>)
+ 8013ae6:	4816      	ldr	r0, [pc, #88]	; (8013b40 <netconn_new_with_proto_and_callback+0xe4>)
+ 8013ae8:	f00d ff4e 	bl	8021988 <iprintf>
+#endif /* LWIP_TCP */
+#if !LWIP_NETCONN_SEM_PER_THREAD
+      LWIP_ASSERT("conn has no op_completed", sys_sem_valid(&conn->op_completed));
+ 8013aec:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 8013aee:	330c      	adds	r3, #12
+ 8013af0:	4618      	mov	r0, r3
+ 8013af2:	f00d fd25 	bl	8021540 <sys_sem_valid>
+ 8013af6:	4603      	mov	r3, r0
+ 8013af8:	2b00      	cmp	r3, #0
+ 8013afa:	d105      	bne.n	8013b08 <netconn_new_with_proto_and_callback+0xac>
+ 8013afc:	4b0e      	ldr	r3, [pc, #56]	; (8013b38 <netconn_new_with_proto_and_callback+0xdc>)
+ 8013afe:	22a9      	movs	r2, #169	; 0xa9
+ 8013b00:	4912      	ldr	r1, [pc, #72]	; (8013b4c <netconn_new_with_proto_and_callback+0xf0>)
+ 8013b02:	480f      	ldr	r0, [pc, #60]	; (8013b40 <netconn_new_with_proto_and_callback+0xe4>)
+ 8013b04:	f00d ff40 	bl	8021988 <iprintf>
+      sys_sem_free(&conn->op_completed);
+ 8013b08:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 8013b0a:	330c      	adds	r3, #12
+ 8013b0c:	4618      	mov	r0, r3
+ 8013b0e:	f00d fd0a 	bl	8021526 <sys_sem_free>
+#endif /* !LWIP_NETCONN_SEM_PER_THREAD */
+      sys_mbox_free(&conn->recvmbox);
+ 8013b12:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 8013b14:	3310      	adds	r3, #16
+ 8013b16:	4618      	mov	r0, r3
+ 8013b18:	f00d fbfa 	bl	8021310 <sys_mbox_free>
+      memp_free(MEMP_NETCONN, conn);
+ 8013b1c:	6af9      	ldr	r1, [r7, #44]	; 0x2c
+ 8013b1e:	2007      	movs	r0, #7
+ 8013b20:	f003 f84c 	bl	8016bbc <memp_free>
+      API_MSG_VAR_FREE(msg);
+      return NULL;
+ 8013b24:	2300      	movs	r3, #0
+ 8013b26:	e000      	b.n	8013b2a <netconn_new_with_proto_and_callback+0xce>
+    }
+  }
+  API_MSG_VAR_FREE(msg);
+  return conn;
+ 8013b28:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+}
+ 8013b2a:	4618      	mov	r0, r3
+ 8013b2c:	3730      	adds	r7, #48	; 0x30
+ 8013b2e:	46bd      	mov	sp, r7
+ 8013b30:	bd80      	pop	{r7, pc}
+ 8013b32:	bf00      	nop
+ 8013b34:	08014a21 	.word	0x08014a21
+ 8013b38:	080232cc 	.word	0x080232cc
+ 8013b3c:	08023300 	.word	0x08023300
+ 8013b40:	08023324 	.word	0x08023324
+ 8013b44:	0802334c 	.word	0x0802334c
+ 8013b48:	08023364 	.word	0x08023364
+ 8013b4c:	08023388 	.word	0x08023388
+
+08013b50 <netconn_prepare_delete>:
+ * @param conn the netconn to delete
+ * @return ERR_OK if the connection was deleted
+ */
+err_t
+netconn_prepare_delete(struct netconn *conn)
+{
+ 8013b50:	b580      	push	{r7, lr}
+ 8013b52:	b08c      	sub	sp, #48	; 0x30
+ 8013b54:	af00      	add	r7, sp, #0
+ 8013b56:	6078      	str	r0, [r7, #4]
+  err_t err;
+  API_MSG_VAR_DECLARE(msg);
+
+  /* No ASSERT here because possible to get a (conn == NULL) if we got an accept error */
+  if (conn == NULL) {
+ 8013b58:	687b      	ldr	r3, [r7, #4]
+ 8013b5a:	2b00      	cmp	r3, #0
+ 8013b5c:	d101      	bne.n	8013b62 <netconn_prepare_delete+0x12>
+    return ERR_OK;
+ 8013b5e:	2300      	movs	r3, #0
+ 8013b60:	e014      	b.n	8013b8c <netconn_prepare_delete+0x3c>
+  }
+
+  API_MSG_VAR_ALLOC(msg);
+  API_MSG_VAR_REF(msg).conn = conn;
+ 8013b62:	687b      	ldr	r3, [r7, #4]
+ 8013b64:	60fb      	str	r3, [r7, #12]
+  /* get the time we started, which is later compared to
+     sys_now() + conn->send_timeout */
+  API_MSG_VAR_REF(msg).msg.sd.time_started = sys_now();
+#else /* LWIP_SO_SNDTIMEO || LWIP_SO_LINGER */
+#if LWIP_TCP
+  API_MSG_VAR_REF(msg).msg.sd.polls_left =
+ 8013b66:	2329      	movs	r3, #41	; 0x29
+ 8013b68:	757b      	strb	r3, [r7, #21]
+    ((LWIP_TCP_CLOSE_TIMEOUT_MS_DEFAULT + TCP_SLOW_INTERVAL - 1) / TCP_SLOW_INTERVAL) + 1;
+#endif /* LWIP_TCP */
+#endif /* LWIP_SO_SNDTIMEO || LWIP_SO_LINGER */
+  err = netconn_apimsg(lwip_netconn_do_delconn, &API_MSG_VAR_REF(msg));
+ 8013b6a:	f107 030c 	add.w	r3, r7, #12
+ 8013b6e:	4619      	mov	r1, r3
+ 8013b70:	4808      	ldr	r0, [pc, #32]	; (8013b94 <netconn_prepare_delete+0x44>)
+ 8013b72:	f7ff ff53 	bl	8013a1c <netconn_apimsg>
+ 8013b76:	4603      	mov	r3, r0
+ 8013b78:	f887 302f 	strb.w	r3, [r7, #47]	; 0x2f
+  API_MSG_VAR_FREE(msg);
+
+  if (err != ERR_OK) {
+ 8013b7c:	f997 302f 	ldrsb.w	r3, [r7, #47]	; 0x2f
+ 8013b80:	2b00      	cmp	r3, #0
+ 8013b82:	d002      	beq.n	8013b8a <netconn_prepare_delete+0x3a>
+    return err;
+ 8013b84:	f997 302f 	ldrsb.w	r3, [r7, #47]	; 0x2f
+ 8013b88:	e000      	b.n	8013b8c <netconn_prepare_delete+0x3c>
+  }
+  return ERR_OK;
+ 8013b8a:	2300      	movs	r3, #0
+}
+ 8013b8c:	4618      	mov	r0, r3
+ 8013b8e:	3730      	adds	r7, #48	; 0x30
+ 8013b90:	46bd      	mov	sp, r7
+ 8013b92:	bd80      	pop	{r7, pc}
+ 8013b94:	08014f8d 	.word	0x08014f8d
+
+08013b98 <netconn_delete>:
+ * @param conn the netconn to delete
+ * @return ERR_OK if the connection was deleted
+ */
+err_t
+netconn_delete(struct netconn *conn)
+{
+ 8013b98:	b580      	push	{r7, lr}
+ 8013b9a:	b084      	sub	sp, #16
+ 8013b9c:	af00      	add	r7, sp, #0
+ 8013b9e:	6078      	str	r0, [r7, #4]
+  err_t err;
+
+  /* No ASSERT here because possible to get a (conn == NULL) if we got an accept error */
+  if (conn == NULL) {
+ 8013ba0:	687b      	ldr	r3, [r7, #4]
+ 8013ba2:	2b00      	cmp	r3, #0
+ 8013ba4:	d101      	bne.n	8013baa <netconn_delete+0x12>
+    return ERR_OK;
+ 8013ba6:	2300      	movs	r3, #0
+ 8013ba8:	e00d      	b.n	8013bc6 <netconn_delete+0x2e>
+    /* Already called netconn_prepare_delete() before */
+    err = ERR_OK;
+  } else
+#endif /* LWIP_NETCONN_FULLDUPLEX */
+  {
+    err = netconn_prepare_delete(conn);
+ 8013baa:	6878      	ldr	r0, [r7, #4]
+ 8013bac:	f7ff ffd0 	bl	8013b50 <netconn_prepare_delete>
+ 8013bb0:	4603      	mov	r3, r0
+ 8013bb2:	73fb      	strb	r3, [r7, #15]
+  }
+  if (err == ERR_OK) {
+ 8013bb4:	f997 300f 	ldrsb.w	r3, [r7, #15]
+ 8013bb8:	2b00      	cmp	r3, #0
+ 8013bba:	d102      	bne.n	8013bc2 <netconn_delete+0x2a>
+    netconn_free(conn);
+ 8013bbc:	6878      	ldr	r0, [r7, #4]
+ 8013bbe:	f000 ffb3 	bl	8014b28 <netconn_free>
+  }
+  return err;
+ 8013bc2:	f997 300f 	ldrsb.w	r3, [r7, #15]
+}
+ 8013bc6:	4618      	mov	r0, r3
+ 8013bc8:	3710      	adds	r7, #16
+ 8013bca:	46bd      	mov	sp, r7
+ 8013bcc:	bd80      	pop	{r7, pc}
+	...
+
+08013bd0 <netconn_bind>:
+ * @param port the local port to bind the netconn to (not used for RAW)
+ * @return ERR_OK if bound, any other err_t on failure
+ */
+err_t
+netconn_bind(struct netconn *conn, const ip_addr_t *addr, u16_t port)
+{
+ 8013bd0:	b580      	push	{r7, lr}
+ 8013bd2:	b08e      	sub	sp, #56	; 0x38
+ 8013bd4:	af00      	add	r7, sp, #0
+ 8013bd6:	60f8      	str	r0, [r7, #12]
+ 8013bd8:	60b9      	str	r1, [r7, #8]
+ 8013bda:	4613      	mov	r3, r2
+ 8013bdc:	80fb      	strh	r3, [r7, #6]
+  API_MSG_VAR_DECLARE(msg);
+  err_t err;
+
+  LWIP_ERROR("netconn_bind: invalid conn", (conn != NULL), return ERR_ARG;);
+ 8013bde:	68fb      	ldr	r3, [r7, #12]
+ 8013be0:	2b00      	cmp	r3, #0
+ 8013be2:	d109      	bne.n	8013bf8 <netconn_bind+0x28>
+ 8013be4:	4b11      	ldr	r3, [pc, #68]	; (8013c2c <netconn_bind+0x5c>)
+ 8013be6:	f44f 729c 	mov.w	r2, #312	; 0x138
+ 8013bea:	4911      	ldr	r1, [pc, #68]	; (8013c30 <netconn_bind+0x60>)
+ 8013bec:	4811      	ldr	r0, [pc, #68]	; (8013c34 <netconn_bind+0x64>)
+ 8013bee:	f00d fecb 	bl	8021988 <iprintf>
+ 8013bf2:	f06f 030f 	mvn.w	r3, #15
+ 8013bf6:	e015      	b.n	8013c24 <netconn_bind+0x54>
+
+#if LWIP_IPV4
+  /* Don't propagate NULL pointer (IP_ADDR_ANY alias) to subsequent functions */
+  if (addr == NULL) {
+ 8013bf8:	68bb      	ldr	r3, [r7, #8]
+ 8013bfa:	2b00      	cmp	r3, #0
+ 8013bfc:	d101      	bne.n	8013c02 <netconn_bind+0x32>
+    addr = IP4_ADDR_ANY;
+ 8013bfe:	4b0e      	ldr	r3, [pc, #56]	; (8013c38 <netconn_bind+0x68>)
+ 8013c00:	60bb      	str	r3, [r7, #8]
+    addr = IP_ANY_TYPE;
+  }
+#endif /* LWIP_IPV4 && LWIP_IPV6 */
+
+  API_MSG_VAR_ALLOC(msg);
+  API_MSG_VAR_REF(msg).conn = conn;
+ 8013c02:	68fb      	ldr	r3, [r7, #12]
+ 8013c04:	617b      	str	r3, [r7, #20]
+  API_MSG_VAR_REF(msg).msg.bc.ipaddr = API_MSG_VAR_REF(addr);
+ 8013c06:	68bb      	ldr	r3, [r7, #8]
+ 8013c08:	61fb      	str	r3, [r7, #28]
+  API_MSG_VAR_REF(msg).msg.bc.port = port;
+ 8013c0a:	88fb      	ldrh	r3, [r7, #6]
+ 8013c0c:	843b      	strh	r3, [r7, #32]
+  err = netconn_apimsg(lwip_netconn_do_bind, &API_MSG_VAR_REF(msg));
+ 8013c0e:	f107 0314 	add.w	r3, r7, #20
+ 8013c12:	4619      	mov	r1, r3
+ 8013c14:	4809      	ldr	r0, [pc, #36]	; (8013c3c <netconn_bind+0x6c>)
+ 8013c16:	f7ff ff01 	bl	8013a1c <netconn_apimsg>
+ 8013c1a:	4603      	mov	r3, r0
+ 8013c1c:	f887 3037 	strb.w	r3, [r7, #55]	; 0x37
+  API_MSG_VAR_FREE(msg);
+
+  return err;
+ 8013c20:	f997 3037 	ldrsb.w	r3, [r7, #55]	; 0x37
+}
+ 8013c24:	4618      	mov	r0, r3
+ 8013c26:	3738      	adds	r7, #56	; 0x38
+ 8013c28:	46bd      	mov	sp, r7
+ 8013c2a:	bd80      	pop	{r7, pc}
+ 8013c2c:	080232cc 	.word	0x080232cc
+ 8013c30:	08023404 	.word	0x08023404
+ 8013c34:	08023324 	.word	0x08023324
+ 8013c38:	08026cec 	.word	0x08026cec
+ 8013c3c:	08015155 	.word	0x08015155
+
+08013c40 <netconn_connect>:
+ * @param port the remote port to connect to (no used for RAW)
+ * @return ERR_OK if connected, return value of tcp_/udp_/raw_connect otherwise
+ */
+err_t
+netconn_connect(struct netconn *conn, const ip_addr_t *addr, u16_t port)
+{
+ 8013c40:	b580      	push	{r7, lr}
+ 8013c42:	b08e      	sub	sp, #56	; 0x38
+ 8013c44:	af00      	add	r7, sp, #0
+ 8013c46:	60f8      	str	r0, [r7, #12]
+ 8013c48:	60b9      	str	r1, [r7, #8]
+ 8013c4a:	4613      	mov	r3, r2
+ 8013c4c:	80fb      	strh	r3, [r7, #6]
+  API_MSG_VAR_DECLARE(msg);
+  err_t err;
+
+  LWIP_ERROR("netconn_connect: invalid conn", (conn != NULL), return ERR_ARG;);
+ 8013c4e:	68fb      	ldr	r3, [r7, #12]
+ 8013c50:	2b00      	cmp	r3, #0
+ 8013c52:	d109      	bne.n	8013c68 <netconn_connect+0x28>
+ 8013c54:	4b11      	ldr	r3, [pc, #68]	; (8013c9c <netconn_connect+0x5c>)
+ 8013c56:	f44f 72bf 	mov.w	r2, #382	; 0x17e
+ 8013c5a:	4911      	ldr	r1, [pc, #68]	; (8013ca0 <netconn_connect+0x60>)
+ 8013c5c:	4811      	ldr	r0, [pc, #68]	; (8013ca4 <netconn_connect+0x64>)
+ 8013c5e:	f00d fe93 	bl	8021988 <iprintf>
+ 8013c62:	f06f 030f 	mvn.w	r3, #15
+ 8013c66:	e015      	b.n	8013c94 <netconn_connect+0x54>
+
+#if LWIP_IPV4
+  /* Don't propagate NULL pointer (IP_ADDR_ANY alias) to subsequent functions */
+  if (addr == NULL) {
+ 8013c68:	68bb      	ldr	r3, [r7, #8]
+ 8013c6a:	2b00      	cmp	r3, #0
+ 8013c6c:	d101      	bne.n	8013c72 <netconn_connect+0x32>
+    addr = IP4_ADDR_ANY;
+ 8013c6e:	4b0e      	ldr	r3, [pc, #56]	; (8013ca8 <netconn_connect+0x68>)
+ 8013c70:	60bb      	str	r3, [r7, #8]
+  }
+#endif /* LWIP_IPV4 */
+
+  API_MSG_VAR_ALLOC(msg);
+  API_MSG_VAR_REF(msg).conn = conn;
+ 8013c72:	68fb      	ldr	r3, [r7, #12]
+ 8013c74:	617b      	str	r3, [r7, #20]
+  API_MSG_VAR_REF(msg).msg.bc.ipaddr = API_MSG_VAR_REF(addr);
+ 8013c76:	68bb      	ldr	r3, [r7, #8]
+ 8013c78:	61fb      	str	r3, [r7, #28]
+  API_MSG_VAR_REF(msg).msg.bc.port = port;
+ 8013c7a:	88fb      	ldrh	r3, [r7, #6]
+ 8013c7c:	843b      	strh	r3, [r7, #32]
+  err = netconn_apimsg(lwip_netconn_do_connect, &API_MSG_VAR_REF(msg));
+ 8013c7e:	f107 0314 	add.w	r3, r7, #20
+ 8013c82:	4619      	mov	r1, r3
+ 8013c84:	4809      	ldr	r0, [pc, #36]	; (8013cac <netconn_connect+0x6c>)
+ 8013c86:	f7ff fec9 	bl	8013a1c <netconn_apimsg>
+ 8013c8a:	4603      	mov	r3, r0
+ 8013c8c:	f887 3037 	strb.w	r3, [r7, #55]	; 0x37
+  API_MSG_VAR_FREE(msg);
+
+  return err;
+ 8013c90:	f997 3037 	ldrsb.w	r3, [r7, #55]	; 0x37
+}
+ 8013c94:	4618      	mov	r0, r3
+ 8013c96:	3738      	adds	r7, #56	; 0x38
+ 8013c98:	46bd      	mov	sp, r7
+ 8013c9a:	bd80      	pop	{r7, pc}
+ 8013c9c:	080232cc 	.word	0x080232cc
+ 8013ca0:	08023440 	.word	0x08023440
+ 8013ca4:	08023324 	.word	0x08023324
+ 8013ca8:	08026cec 	.word	0x08026cec
+ 8013cac:	080152e9 	.word	0x080152e9
+
+08013cb0 <netconn_recv_data>:
+ *         ERR_WOULDBLOCK if the netconn is nonblocking but would block to wait for data
+ *         ERR_TIMEOUT if the netconn has a receive timeout and no data was received
+ */
+static err_t
+netconn_recv_data(struct netconn *conn, void **new_buf, u8_t apiflags)
+{
+ 8013cb0:	b580      	push	{r7, lr}
+ 8013cb2:	b088      	sub	sp, #32
+ 8013cb4:	af00      	add	r7, sp, #0
+ 8013cb6:	60f8      	str	r0, [r7, #12]
+ 8013cb8:	60b9      	str	r1, [r7, #8]
+ 8013cba:	4613      	mov	r3, r2
+ 8013cbc:	71fb      	strb	r3, [r7, #7]
+  void *buf = NULL;
+ 8013cbe:	2300      	movs	r3, #0
+ 8013cc0:	61bb      	str	r3, [r7, #24]
+  u16_t len;
+
+  LWIP_ERROR("netconn_recv: invalid pointer", (new_buf != NULL), return ERR_ARG;);
+ 8013cc2:	68bb      	ldr	r3, [r7, #8]
+ 8013cc4:	2b00      	cmp	r3, #0
+ 8013cc6:	d109      	bne.n	8013cdc <netconn_recv_data+0x2c>
+ 8013cc8:	4b58      	ldr	r3, [pc, #352]	; (8013e2c <netconn_recv_data+0x17c>)
+ 8013cca:	f44f 7212 	mov.w	r2, #584	; 0x248
+ 8013cce:	4958      	ldr	r1, [pc, #352]	; (8013e30 <netconn_recv_data+0x180>)
+ 8013cd0:	4858      	ldr	r0, [pc, #352]	; (8013e34 <netconn_recv_data+0x184>)
+ 8013cd2:	f00d fe59 	bl	8021988 <iprintf>
+ 8013cd6:	f06f 030f 	mvn.w	r3, #15
+ 8013cda:	e0a2      	b.n	8013e22 <netconn_recv_data+0x172>
+  *new_buf = NULL;
+ 8013cdc:	68bb      	ldr	r3, [r7, #8]
+ 8013cde:	2200      	movs	r2, #0
+ 8013ce0:	601a      	str	r2, [r3, #0]
+  LWIP_ERROR("netconn_recv: invalid conn",    (conn != NULL),    return ERR_ARG;);
+ 8013ce2:	68fb      	ldr	r3, [r7, #12]
+ 8013ce4:	2b00      	cmp	r3, #0
+ 8013ce6:	d109      	bne.n	8013cfc <netconn_recv_data+0x4c>
+ 8013ce8:	4b50      	ldr	r3, [pc, #320]	; (8013e2c <netconn_recv_data+0x17c>)
+ 8013cea:	f240 224a 	movw	r2, #586	; 0x24a
+ 8013cee:	4952      	ldr	r1, [pc, #328]	; (8013e38 <netconn_recv_data+0x188>)
+ 8013cf0:	4850      	ldr	r0, [pc, #320]	; (8013e34 <netconn_recv_data+0x184>)
+ 8013cf2:	f00d fe49 	bl	8021988 <iprintf>
+ 8013cf6:	f06f 030f 	mvn.w	r3, #15
+ 8013cfa:	e092      	b.n	8013e22 <netconn_recv_data+0x172>
+
+  if (!NETCONN_RECVMBOX_WAITABLE(conn)) {
+ 8013cfc:	68fb      	ldr	r3, [r7, #12]
+ 8013cfe:	3310      	adds	r3, #16
+ 8013d00:	4618      	mov	r0, r3
+ 8013d02:	f00d fb8c 	bl	802141e <sys_mbox_valid>
+ 8013d06:	4603      	mov	r3, r0
+ 8013d08:	2b00      	cmp	r3, #0
+ 8013d0a:	d10e      	bne.n	8013d2a <netconn_recv_data+0x7a>
+    err_t err = netconn_err(conn);
+ 8013d0c:	68f8      	ldr	r0, [r7, #12]
+ 8013d0e:	f000 fad4 	bl	80142ba <netconn_err>
+ 8013d12:	4603      	mov	r3, r0
+ 8013d14:	773b      	strb	r3, [r7, #28]
+    if (err != ERR_OK) {
+ 8013d16:	f997 301c 	ldrsb.w	r3, [r7, #28]
+ 8013d1a:	2b00      	cmp	r3, #0
+ 8013d1c:	d002      	beq.n	8013d24 <netconn_recv_data+0x74>
+      /* return pending error */
+      return err;
+ 8013d1e:	f997 301c 	ldrsb.w	r3, [r7, #28]
+ 8013d22:	e07e      	b.n	8013e22 <netconn_recv_data+0x172>
+    }
+    return ERR_CONN;
+ 8013d24:	f06f 030a 	mvn.w	r3, #10
+ 8013d28:	e07b      	b.n	8013e22 <netconn_recv_data+0x172>
+  }
+
+  NETCONN_MBOX_WAITING_INC(conn);
+  if (netconn_is_nonblocking(conn) || (apiflags & NETCONN_DONTBLOCK) ||
+ 8013d2a:	68fb      	ldr	r3, [r7, #12]
+ 8013d2c:	7f1b      	ldrb	r3, [r3, #28]
+ 8013d2e:	f003 0302 	and.w	r3, r3, #2
+ 8013d32:	2b00      	cmp	r3, #0
+ 8013d34:	d10f      	bne.n	8013d56 <netconn_recv_data+0xa6>
+ 8013d36:	79fb      	ldrb	r3, [r7, #7]
+ 8013d38:	f003 0304 	and.w	r3, r3, #4
+ 8013d3c:	2b00      	cmp	r3, #0
+ 8013d3e:	d10a      	bne.n	8013d56 <netconn_recv_data+0xa6>
+      (conn->flags & NETCONN_FLAG_MBOXCLOSED) || (conn->pending_err != ERR_OK)) {
+ 8013d40:	68fb      	ldr	r3, [r7, #12]
+ 8013d42:	7f1b      	ldrb	r3, [r3, #28]
+ 8013d44:	f003 0301 	and.w	r3, r3, #1
+  if (netconn_is_nonblocking(conn) || (apiflags & NETCONN_DONTBLOCK) ||
+ 8013d48:	2b00      	cmp	r3, #0
+ 8013d4a:	d104      	bne.n	8013d56 <netconn_recv_data+0xa6>
+      (conn->flags & NETCONN_FLAG_MBOXCLOSED) || (conn->pending_err != ERR_OK)) {
+ 8013d4c:	68fb      	ldr	r3, [r7, #12]
+ 8013d4e:	f993 3008 	ldrsb.w	r3, [r3, #8]
+ 8013d52:	2b00      	cmp	r3, #0
+ 8013d54:	d023      	beq.n	8013d9e <netconn_recv_data+0xee>
+    if (sys_arch_mbox_tryfetch(&conn->recvmbox, &buf) == SYS_ARCH_TIMEOUT) {
+ 8013d56:	68fb      	ldr	r3, [r7, #12]
+ 8013d58:	3310      	adds	r3, #16
+ 8013d5a:	f107 0218 	add.w	r2, r7, #24
+ 8013d5e:	4611      	mov	r1, r2
+ 8013d60:	4618      	mov	r0, r3
+ 8013d62:	f00d fb40 	bl	80213e6 <sys_arch_mbox_tryfetch>
+ 8013d66:	4603      	mov	r3, r0
+ 8013d68:	f1b3 3fff 	cmp.w	r3, #4294967295
+ 8013d6c:	d11f      	bne.n	8013dae <netconn_recv_data+0xfe>
+      err_t err;
+      NETCONN_MBOX_WAITING_DEC(conn);
+      err = netconn_err(conn);
+ 8013d6e:	68f8      	ldr	r0, [r7, #12]
+ 8013d70:	f000 faa3 	bl	80142ba <netconn_err>
+ 8013d74:	4603      	mov	r3, r0
+ 8013d76:	777b      	strb	r3, [r7, #29]
+      if (err != ERR_OK) {
+ 8013d78:	f997 301d 	ldrsb.w	r3, [r7, #29]
+ 8013d7c:	2b00      	cmp	r3, #0
+ 8013d7e:	d002      	beq.n	8013d86 <netconn_recv_data+0xd6>
+        /* return pending error */
+        return err;
+ 8013d80:	f997 301d 	ldrsb.w	r3, [r7, #29]
+ 8013d84:	e04d      	b.n	8013e22 <netconn_recv_data+0x172>
+      }
+      if (conn->flags & NETCONN_FLAG_MBOXCLOSED) {
+ 8013d86:	68fb      	ldr	r3, [r7, #12]
+ 8013d88:	7f1b      	ldrb	r3, [r3, #28]
+ 8013d8a:	f003 0301 	and.w	r3, r3, #1
+ 8013d8e:	2b00      	cmp	r3, #0
+ 8013d90:	d002      	beq.n	8013d98 <netconn_recv_data+0xe8>
+        return ERR_CONN;
+ 8013d92:	f06f 030a 	mvn.w	r3, #10
+ 8013d96:	e044      	b.n	8013e22 <netconn_recv_data+0x172>
+      }
+      return ERR_WOULDBLOCK;
+ 8013d98:	f06f 0306 	mvn.w	r3, #6
+ 8013d9c:	e041      	b.n	8013e22 <netconn_recv_data+0x172>
+    if (sys_arch_mbox_fetch(&conn->recvmbox, &buf, conn->recv_timeout) == SYS_ARCH_TIMEOUT) {
+      NETCONN_MBOX_WAITING_DEC(conn);
+      return ERR_TIMEOUT;
+    }
+#else
+    sys_arch_mbox_fetch(&conn->recvmbox, &buf, 0);
+ 8013d9e:	68fb      	ldr	r3, [r7, #12]
+ 8013da0:	3310      	adds	r3, #16
+ 8013da2:	f107 0118 	add.w	r1, r7, #24
+ 8013da6:	2200      	movs	r2, #0
+ 8013da8:	4618      	mov	r0, r3
+ 8013daa:	f00d fadd 	bl	8021368 <sys_arch_mbox_fetch>
+  }
+#endif
+
+#if LWIP_TCP
+#if (LWIP_UDP || LWIP_RAW)
+  if (NETCONNTYPE_GROUP(conn->type) == NETCONN_TCP)
+ 8013dae:	68fb      	ldr	r3, [r7, #12]
+ 8013db0:	781b      	ldrb	r3, [r3, #0]
+ 8013db2:	f003 03f0 	and.w	r3, r3, #240	; 0xf0
+ 8013db6:	2b10      	cmp	r3, #16
+ 8013db8:	d117      	bne.n	8013dea <netconn_recv_data+0x13a>
+#endif /* (LWIP_UDP || LWIP_RAW) */
+  {
+    err_t err;
+    /* Check if this is an error message or a pbuf */
+    if (lwip_netconn_is_err_msg(buf, &err)) {
+ 8013dba:	69bb      	ldr	r3, [r7, #24]
+ 8013dbc:	f107 0217 	add.w	r2, r7, #23
+ 8013dc0:	4611      	mov	r1, r2
+ 8013dc2:	4618      	mov	r0, r3
+ 8013dc4:	f000 faca 	bl	801435c <lwip_netconn_is_err_msg>
+ 8013dc8:	4603      	mov	r3, r0
+ 8013dca:	2b00      	cmp	r3, #0
+ 8013dcc:	d009      	beq.n	8013de2 <netconn_recv_data+0x132>
+      /* new_buf has been zeroed above already */
+      if (err == ERR_CLSD) {
+ 8013dce:	f997 3017 	ldrsb.w	r3, [r7, #23]
+ 8013dd2:	f113 0f0f 	cmn.w	r3, #15
+ 8013dd6:	d101      	bne.n	8013ddc <netconn_recv_data+0x12c>
+        /* connection closed translates to ERR_OK with *new_buf == NULL */
+        return ERR_OK;
+ 8013dd8:	2300      	movs	r3, #0
+ 8013dda:	e022      	b.n	8013e22 <netconn_recv_data+0x172>
+      }
+      return err;
+ 8013ddc:	f997 3017 	ldrsb.w	r3, [r7, #23]
+ 8013de0:	e01f      	b.n	8013e22 <netconn_recv_data+0x172>
+    }
+    len = ((struct pbuf *)buf)->tot_len;
+ 8013de2:	69bb      	ldr	r3, [r7, #24]
+ 8013de4:	891b      	ldrh	r3, [r3, #8]
+ 8013de6:	83fb      	strh	r3, [r7, #30]
+ 8013de8:	e00d      	b.n	8013e06 <netconn_recv_data+0x156>
+#if LWIP_TCP && (LWIP_UDP || LWIP_RAW)
+  else
+#endif /* LWIP_TCP && (LWIP_UDP || LWIP_RAW) */
+#if (LWIP_UDP || LWIP_RAW)
+  {
+    LWIP_ASSERT("buf != NULL", buf != NULL);
+ 8013dea:	69bb      	ldr	r3, [r7, #24]
+ 8013dec:	2b00      	cmp	r3, #0
+ 8013dee:	d106      	bne.n	8013dfe <netconn_recv_data+0x14e>
+ 8013df0:	4b0e      	ldr	r3, [pc, #56]	; (8013e2c <netconn_recv_data+0x17c>)
+ 8013df2:	f240 2291 	movw	r2, #657	; 0x291
+ 8013df6:	4911      	ldr	r1, [pc, #68]	; (8013e3c <netconn_recv_data+0x18c>)
+ 8013df8:	480e      	ldr	r0, [pc, #56]	; (8013e34 <netconn_recv_data+0x184>)
+ 8013dfa:	f00d fdc5 	bl	8021988 <iprintf>
+    len = netbuf_len((struct netbuf *)buf);
+ 8013dfe:	69bb      	ldr	r3, [r7, #24]
+ 8013e00:	681b      	ldr	r3, [r3, #0]
+ 8013e02:	891b      	ldrh	r3, [r3, #8]
+ 8013e04:	83fb      	strh	r3, [r7, #30]
+
+#if LWIP_SO_RCVBUF
+  SYS_ARCH_DEC(conn->recv_avail, len);
+#endif /* LWIP_SO_RCVBUF */
+  /* Register event with callback */
+  API_EVENT(conn, NETCONN_EVT_RCVMINUS, len);
+ 8013e06:	68fb      	ldr	r3, [r7, #12]
+ 8013e08:	6a5b      	ldr	r3, [r3, #36]	; 0x24
+ 8013e0a:	2b00      	cmp	r3, #0
+ 8013e0c:	d005      	beq.n	8013e1a <netconn_recv_data+0x16a>
+ 8013e0e:	68fb      	ldr	r3, [r7, #12]
+ 8013e10:	6a5b      	ldr	r3, [r3, #36]	; 0x24
+ 8013e12:	8bfa      	ldrh	r2, [r7, #30]
+ 8013e14:	2101      	movs	r1, #1
+ 8013e16:	68f8      	ldr	r0, [r7, #12]
+ 8013e18:	4798      	blx	r3
+
+  LWIP_DEBUGF(API_LIB_DEBUG, ("netconn_recv_data: received %p, len=%"U16_F"\n", buf, len));
+
+  *new_buf = buf;
+ 8013e1a:	69ba      	ldr	r2, [r7, #24]
+ 8013e1c:	68bb      	ldr	r3, [r7, #8]
+ 8013e1e:	601a      	str	r2, [r3, #0]
+  /* don't set conn->last_err: it's only ERR_OK, anyway */
+  return ERR_OK;
+ 8013e20:	2300      	movs	r3, #0
+}
+ 8013e22:	4618      	mov	r0, r3
+ 8013e24:	3720      	adds	r7, #32
+ 8013e26:	46bd      	mov	sp, r7
+ 8013e28:	bd80      	pop	{r7, pc}
+ 8013e2a:	bf00      	nop
+ 8013e2c:	080232cc 	.word	0x080232cc
+ 8013e30:	080234e4 	.word	0x080234e4
+ 8013e34:	08023324 	.word	0x08023324
+ 8013e38:	08023504 	.word	0x08023504
+ 8013e3c:	08023520 	.word	0x08023520
+
+08013e40 <netconn_tcp_recvd_msg>:
+
+#if LWIP_TCP
+static err_t
+netconn_tcp_recvd_msg(struct netconn *conn, size_t len, struct api_msg *msg)
+{
+ 8013e40:	b580      	push	{r7, lr}
+ 8013e42:	b084      	sub	sp, #16
+ 8013e44:	af00      	add	r7, sp, #0
+ 8013e46:	60f8      	str	r0, [r7, #12]
+ 8013e48:	60b9      	str	r1, [r7, #8]
+ 8013e4a:	607a      	str	r2, [r7, #4]
+  LWIP_ERROR("netconn_recv_tcp_pbuf: invalid conn", (conn != NULL) &&
+ 8013e4c:	68fb      	ldr	r3, [r7, #12]
+ 8013e4e:	2b00      	cmp	r3, #0
+ 8013e50:	d005      	beq.n	8013e5e <netconn_tcp_recvd_msg+0x1e>
+ 8013e52:	68fb      	ldr	r3, [r7, #12]
+ 8013e54:	781b      	ldrb	r3, [r3, #0]
+ 8013e56:	f003 03f0 	and.w	r3, r3, #240	; 0xf0
+ 8013e5a:	2b10      	cmp	r3, #16
+ 8013e5c:	d009      	beq.n	8013e72 <netconn_tcp_recvd_msg+0x32>
+ 8013e5e:	4b0c      	ldr	r3, [pc, #48]	; (8013e90 <netconn_tcp_recvd_msg+0x50>)
+ 8013e60:	f240 22a7 	movw	r2, #679	; 0x2a7
+ 8013e64:	490b      	ldr	r1, [pc, #44]	; (8013e94 <netconn_tcp_recvd_msg+0x54>)
+ 8013e66:	480c      	ldr	r0, [pc, #48]	; (8013e98 <netconn_tcp_recvd_msg+0x58>)
+ 8013e68:	f00d fd8e 	bl	8021988 <iprintf>
+ 8013e6c:	f06f 030f 	mvn.w	r3, #15
+ 8013e70:	e00a      	b.n	8013e88 <netconn_tcp_recvd_msg+0x48>
+             NETCONNTYPE_GROUP(netconn_type(conn)) == NETCONN_TCP, return ERR_ARG;);
+
+  msg->conn = conn;
+ 8013e72:	687b      	ldr	r3, [r7, #4]
+ 8013e74:	68fa      	ldr	r2, [r7, #12]
+ 8013e76:	601a      	str	r2, [r3, #0]
+  msg->msg.r.len = len;
+ 8013e78:	687b      	ldr	r3, [r7, #4]
+ 8013e7a:	68ba      	ldr	r2, [r7, #8]
+ 8013e7c:	609a      	str	r2, [r3, #8]
+
+  return netconn_apimsg(lwip_netconn_do_recv, msg);
+ 8013e7e:	6879      	ldr	r1, [r7, #4]
+ 8013e80:	4806      	ldr	r0, [pc, #24]	; (8013e9c <netconn_tcp_recvd_msg+0x5c>)
+ 8013e82:	f7ff fdcb 	bl	8013a1c <netconn_apimsg>
+ 8013e86:	4603      	mov	r3, r0
+}
+ 8013e88:	4618      	mov	r0, r3
+ 8013e8a:	3710      	adds	r7, #16
+ 8013e8c:	46bd      	mov	sp, r7
+ 8013e8e:	bd80      	pop	{r7, pc}
+ 8013e90:	080232cc 	.word	0x080232cc
+ 8013e94:	0802352c 	.word	0x0802352c
+ 8013e98:	08023324 	.word	0x08023324
+ 8013e9c:	08015465 	.word	0x08015465
+
+08013ea0 <netconn_recv_data_tcp>:
+  return err;
+}
+
+static err_t
+netconn_recv_data_tcp(struct netconn *conn, struct pbuf **new_buf, u8_t apiflags)
+{
+ 8013ea0:	b580      	push	{r7, lr}
+ 8013ea2:	b090      	sub	sp, #64	; 0x40
+ 8013ea4:	af00      	add	r7, sp, #0
+ 8013ea6:	60f8      	str	r0, [r7, #12]
+ 8013ea8:	60b9      	str	r1, [r7, #8]
+ 8013eaa:	4613      	mov	r3, r2
+ 8013eac:	71fb      	strb	r3, [r7, #7]
+  API_MSG_VAR_DECLARE(msg);
+#if LWIP_MPU_COMPATIBLE
+  msg = NULL;
+#endif
+
+  if (!NETCONN_RECVMBOX_WAITABLE(conn)) {
+ 8013eae:	68fb      	ldr	r3, [r7, #12]
+ 8013eb0:	3310      	adds	r3, #16
+ 8013eb2:	4618      	mov	r0, r3
+ 8013eb4:	f00d fab3 	bl	802141e <sys_mbox_valid>
+ 8013eb8:	4603      	mov	r3, r0
+ 8013eba:	2b00      	cmp	r3, #0
+ 8013ebc:	d102      	bne.n	8013ec4 <netconn_recv_data_tcp+0x24>
+    /* This only happens when calling this function more than once *after* receiving FIN */
+    return ERR_CONN;
+ 8013ebe:	f06f 030a 	mvn.w	r3, #10
+ 8013ec2:	e06d      	b.n	8013fa0 <netconn_recv_data_tcp+0x100>
+  }
+  if (netconn_is_flag_set(conn, NETCONN_FIN_RX_PENDING)) {
+ 8013ec4:	68fb      	ldr	r3, [r7, #12]
+ 8013ec6:	7f1b      	ldrb	r3, [r3, #28]
+ 8013ec8:	b25b      	sxtb	r3, r3
+ 8013eca:	2b00      	cmp	r3, #0
+ 8013ecc:	da07      	bge.n	8013ede <netconn_recv_data_tcp+0x3e>
+    netconn_clear_flags(conn, NETCONN_FIN_RX_PENDING);
+ 8013ece:	68fb      	ldr	r3, [r7, #12]
+ 8013ed0:	7f1b      	ldrb	r3, [r3, #28]
+ 8013ed2:	f003 037f 	and.w	r3, r3, #127	; 0x7f
+ 8013ed6:	b2da      	uxtb	r2, r3
+ 8013ed8:	68fb      	ldr	r3, [r7, #12]
+ 8013eda:	771a      	strb	r2, [r3, #28]
+    goto handle_fin;
+ 8013edc:	e039      	b.n	8013f52 <netconn_recv_data_tcp+0xb2>
+    /* need to allocate API message here so empty message pool does not result in event loss
+      * see bug #47512: MPU_COMPATIBLE may fail on empty pool */
+    API_MSG_VAR_ALLOC(msg);
+  }
+
+  err = netconn_recv_data(conn, (void **)new_buf, apiflags);
+ 8013ede:	79fb      	ldrb	r3, [r7, #7]
+ 8013ee0:	461a      	mov	r2, r3
+ 8013ee2:	68b9      	ldr	r1, [r7, #8]
+ 8013ee4:	68f8      	ldr	r0, [r7, #12]
+ 8013ee6:	f7ff fee3 	bl	8013cb0 <netconn_recv_data>
+ 8013eea:	4603      	mov	r3, r0
+ 8013eec:	f887 303f 	strb.w	r3, [r7, #63]	; 0x3f
+  if (err != ERR_OK) {
+ 8013ef0:	f997 303f 	ldrsb.w	r3, [r7, #63]	; 0x3f
+ 8013ef4:	2b00      	cmp	r3, #0
+ 8013ef6:	d002      	beq.n	8013efe <netconn_recv_data_tcp+0x5e>
+    if (!(apiflags & NETCONN_NOAUTORCVD)) {
+      API_MSG_VAR_FREE(msg);
+    }
+    return err;
+ 8013ef8:	f997 303f 	ldrsb.w	r3, [r7, #63]	; 0x3f
+ 8013efc:	e050      	b.n	8013fa0 <netconn_recv_data_tcp+0x100>
+  }
+  buf = *new_buf;
+ 8013efe:	68bb      	ldr	r3, [r7, #8]
+ 8013f00:	681b      	ldr	r3, [r3, #0]
+ 8013f02:	63bb      	str	r3, [r7, #56]	; 0x38
+  if (!(apiflags & NETCONN_NOAUTORCVD)) {
+ 8013f04:	79fb      	ldrb	r3, [r7, #7]
+ 8013f06:	f003 0308 	and.w	r3, r3, #8
+ 8013f0a:	2b00      	cmp	r3, #0
+ 8013f0c:	d10e      	bne.n	8013f2c <netconn_recv_data_tcp+0x8c>
+    /* Let the stack know that we have taken the data. */
+    u16_t len = buf ? buf->tot_len : 1;
+ 8013f0e:	6bbb      	ldr	r3, [r7, #56]	; 0x38
+ 8013f10:	2b00      	cmp	r3, #0
+ 8013f12:	d002      	beq.n	8013f1a <netconn_recv_data_tcp+0x7a>
+ 8013f14:	6bbb      	ldr	r3, [r7, #56]	; 0x38
+ 8013f16:	891b      	ldrh	r3, [r3, #8]
+ 8013f18:	e000      	b.n	8013f1c <netconn_recv_data_tcp+0x7c>
+ 8013f1a:	2301      	movs	r3, #1
+ 8013f1c:	86fb      	strh	r3, [r7, #54]	; 0x36
+    /* don't care for the return value of lwip_netconn_do_recv */
+    /* @todo: this should really be fixed, e.g. by retrying in poll on error */
+    netconn_tcp_recvd_msg(conn, len,  &API_VAR_REF(msg));
+ 8013f1e:	8efb      	ldrh	r3, [r7, #54]	; 0x36
+ 8013f20:	f107 0214 	add.w	r2, r7, #20
+ 8013f24:	4619      	mov	r1, r3
+ 8013f26:	68f8      	ldr	r0, [r7, #12]
+ 8013f28:	f7ff ff8a 	bl	8013e40 <netconn_tcp_recvd_msg>
+    API_MSG_VAR_FREE(msg);
+  }
+
+  /* If we are closed, we indicate that we no longer wish to use the socket */
+  if (buf == NULL) {
+ 8013f2c:	6bbb      	ldr	r3, [r7, #56]	; 0x38
+ 8013f2e:	2b00      	cmp	r3, #0
+ 8013f30:	d134      	bne.n	8013f9c <netconn_recv_data_tcp+0xfc>
+    if (apiflags & NETCONN_NOFIN) {
+ 8013f32:	79fb      	ldrb	r3, [r7, #7]
+ 8013f34:	f003 0310 	and.w	r3, r3, #16
+ 8013f38:	2b00      	cmp	r3, #0
+ 8013f3a:	d009      	beq.n	8013f50 <netconn_recv_data_tcp+0xb0>
+      /* received a FIN but the caller cannot handle it right now:
+         re-enqueue it and return "no data" */
+      netconn_set_flags(conn, NETCONN_FIN_RX_PENDING);
+ 8013f3c:	68fb      	ldr	r3, [r7, #12]
+ 8013f3e:	7f1b      	ldrb	r3, [r3, #28]
+ 8013f40:	f063 037f 	orn	r3, r3, #127	; 0x7f
+ 8013f44:	b2da      	uxtb	r2, r3
+ 8013f46:	68fb      	ldr	r3, [r7, #12]
+ 8013f48:	771a      	strb	r2, [r3, #28]
+      return ERR_WOULDBLOCK;
+ 8013f4a:	f06f 0306 	mvn.w	r3, #6
+ 8013f4e:	e027      	b.n	8013fa0 <netconn_recv_data_tcp+0x100>
+    } else {
+handle_fin:
+ 8013f50:	bf00      	nop
+      API_EVENT(conn, NETCONN_EVT_RCVMINUS, 0);
+ 8013f52:	68fb      	ldr	r3, [r7, #12]
+ 8013f54:	6a5b      	ldr	r3, [r3, #36]	; 0x24
+ 8013f56:	2b00      	cmp	r3, #0
+ 8013f58:	d005      	beq.n	8013f66 <netconn_recv_data_tcp+0xc6>
+ 8013f5a:	68fb      	ldr	r3, [r7, #12]
+ 8013f5c:	6a5b      	ldr	r3, [r3, #36]	; 0x24
+ 8013f5e:	2200      	movs	r2, #0
+ 8013f60:	2101      	movs	r1, #1
+ 8013f62:	68f8      	ldr	r0, [r7, #12]
+ 8013f64:	4798      	blx	r3
+      if (conn->pcb.ip == NULL) {
+ 8013f66:	68fb      	ldr	r3, [r7, #12]
+ 8013f68:	685b      	ldr	r3, [r3, #4]
+ 8013f6a:	2b00      	cmp	r3, #0
+ 8013f6c:	d10f      	bne.n	8013f8e <netconn_recv_data_tcp+0xee>
+        /* race condition: RST during recv */
+        err = netconn_err(conn);
+ 8013f6e:	68f8      	ldr	r0, [r7, #12]
+ 8013f70:	f000 f9a3 	bl	80142ba <netconn_err>
+ 8013f74:	4603      	mov	r3, r0
+ 8013f76:	f887 303f 	strb.w	r3, [r7, #63]	; 0x3f
+        if (err != ERR_OK) {
+ 8013f7a:	f997 303f 	ldrsb.w	r3, [r7, #63]	; 0x3f
+ 8013f7e:	2b00      	cmp	r3, #0
+ 8013f80:	d002      	beq.n	8013f88 <netconn_recv_data_tcp+0xe8>
+          return err;
+ 8013f82:	f997 303f 	ldrsb.w	r3, [r7, #63]	; 0x3f
+ 8013f86:	e00b      	b.n	8013fa0 <netconn_recv_data_tcp+0x100>
+        }
+        return ERR_RST;
+ 8013f88:	f06f 030d 	mvn.w	r3, #13
+ 8013f8c:	e008      	b.n	8013fa0 <netconn_recv_data_tcp+0x100>
+      }
+      /* RX side is closed, so deallocate the recvmbox */
+      netconn_close_shutdown(conn, NETCONN_SHUT_RD);
+ 8013f8e:	2101      	movs	r1, #1
+ 8013f90:	68f8      	ldr	r0, [r7, #12]
+ 8013f92:	f000 f955 	bl	8014240 <netconn_close_shutdown>
+      /* Don' store ERR_CLSD as conn->err since we are only half-closed */
+      return ERR_CLSD;
+ 8013f96:	f06f 030e 	mvn.w	r3, #14
+ 8013f9a:	e001      	b.n	8013fa0 <netconn_recv_data_tcp+0x100>
+    }
+  }
+  return err;
+ 8013f9c:	f997 303f 	ldrsb.w	r3, [r7, #63]	; 0x3f
+}
+ 8013fa0:	4618      	mov	r0, r3
+ 8013fa2:	3740      	adds	r7, #64	; 0x40
+ 8013fa4:	46bd      	mov	sp, r7
+ 8013fa6:	bd80      	pop	{r7, pc}
+
+08013fa8 <netconn_recv>:
+ * @return ERR_OK if data has been received, an error code otherwise (timeout,
+ *                memory error or another error)
+ */
+err_t
+netconn_recv(struct netconn *conn, struct netbuf **new_buf)
+{
+ 8013fa8:	b580      	push	{r7, lr}
+ 8013faa:	b086      	sub	sp, #24
+ 8013fac:	af00      	add	r7, sp, #0
+ 8013fae:	6078      	str	r0, [r7, #4]
+ 8013fb0:	6039      	str	r1, [r7, #0]
+#if LWIP_TCP
+  struct netbuf *buf = NULL;
+ 8013fb2:	2300      	movs	r3, #0
+ 8013fb4:	617b      	str	r3, [r7, #20]
+  err_t err;
+#endif /* LWIP_TCP */
+
+  LWIP_ERROR("netconn_recv: invalid pointer", (new_buf != NULL), return ERR_ARG;);
+ 8013fb6:	683b      	ldr	r3, [r7, #0]
+ 8013fb8:	2b00      	cmp	r3, #0
+ 8013fba:	d109      	bne.n	8013fd0 <netconn_recv+0x28>
+ 8013fbc:	4b32      	ldr	r3, [pc, #200]	; (8014088 <netconn_recv+0xe0>)
+ 8013fbe:	f240 3263 	movw	r2, #867	; 0x363
+ 8013fc2:	4932      	ldr	r1, [pc, #200]	; (801408c <netconn_recv+0xe4>)
+ 8013fc4:	4832      	ldr	r0, [pc, #200]	; (8014090 <netconn_recv+0xe8>)
+ 8013fc6:	f00d fcdf 	bl	8021988 <iprintf>
+ 8013fca:	f06f 030f 	mvn.w	r3, #15
+ 8013fce:	e056      	b.n	801407e <netconn_recv+0xd6>
+  *new_buf = NULL;
+ 8013fd0:	683b      	ldr	r3, [r7, #0]
+ 8013fd2:	2200      	movs	r2, #0
+ 8013fd4:	601a      	str	r2, [r3, #0]
+  LWIP_ERROR("netconn_recv: invalid conn",    (conn != NULL),    return ERR_ARG;);
+ 8013fd6:	687b      	ldr	r3, [r7, #4]
+ 8013fd8:	2b00      	cmp	r3, #0
+ 8013fda:	d109      	bne.n	8013ff0 <netconn_recv+0x48>
+ 8013fdc:	4b2a      	ldr	r3, [pc, #168]	; (8014088 <netconn_recv+0xe0>)
+ 8013fde:	f240 3265 	movw	r2, #869	; 0x365
+ 8013fe2:	492c      	ldr	r1, [pc, #176]	; (8014094 <netconn_recv+0xec>)
+ 8013fe4:	482a      	ldr	r0, [pc, #168]	; (8014090 <netconn_recv+0xe8>)
+ 8013fe6:	f00d fccf 	bl	8021988 <iprintf>
+ 8013fea:	f06f 030f 	mvn.w	r3, #15
+ 8013fee:	e046      	b.n	801407e <netconn_recv+0xd6>
+
+#if LWIP_TCP
+#if (LWIP_UDP || LWIP_RAW)
+  if (NETCONNTYPE_GROUP(conn->type) == NETCONN_TCP)
+ 8013ff0:	687b      	ldr	r3, [r7, #4]
+ 8013ff2:	781b      	ldrb	r3, [r3, #0]
+ 8013ff4:	f003 03f0 	and.w	r3, r3, #240	; 0xf0
+ 8013ff8:	2b10      	cmp	r3, #16
+ 8013ffa:	d13a      	bne.n	8014072 <netconn_recv+0xca>
+#endif /* (LWIP_UDP || LWIP_RAW) */
+  {
+    struct pbuf *p = NULL;
+ 8013ffc:	2300      	movs	r3, #0
+ 8013ffe:	60fb      	str	r3, [r7, #12]
+    /* This is not a listening netconn, since recvmbox is set */
+
+    buf = (struct netbuf *)memp_malloc(MEMP_NETBUF);
+ 8014000:	2006      	movs	r0, #6
+ 8014002:	f002 fd65 	bl	8016ad0 <memp_malloc>
+ 8014006:	6178      	str	r0, [r7, #20]
+    if (buf == NULL) {
+ 8014008:	697b      	ldr	r3, [r7, #20]
+ 801400a:	2b00      	cmp	r3, #0
+ 801400c:	d102      	bne.n	8014014 <netconn_recv+0x6c>
+      return ERR_MEM;
+ 801400e:	f04f 33ff 	mov.w	r3, #4294967295
+ 8014012:	e034      	b.n	801407e <netconn_recv+0xd6>
+    }
+
+    err = netconn_recv_data_tcp(conn, &p, 0);
+ 8014014:	f107 030c 	add.w	r3, r7, #12
+ 8014018:	2200      	movs	r2, #0
+ 801401a:	4619      	mov	r1, r3
+ 801401c:	6878      	ldr	r0, [r7, #4]
+ 801401e:	f7ff ff3f 	bl	8013ea0 <netconn_recv_data_tcp>
+ 8014022:	4603      	mov	r3, r0
+ 8014024:	74fb      	strb	r3, [r7, #19]
+    if (err != ERR_OK) {
+ 8014026:	f997 3013 	ldrsb.w	r3, [r7, #19]
+ 801402a:	2b00      	cmp	r3, #0
+ 801402c:	d006      	beq.n	801403c <netconn_recv+0x94>
+      memp_free(MEMP_NETBUF, buf);
+ 801402e:	6979      	ldr	r1, [r7, #20]
+ 8014030:	2006      	movs	r0, #6
+ 8014032:	f002 fdc3 	bl	8016bbc <memp_free>
+      return err;
+ 8014036:	f997 3013 	ldrsb.w	r3, [r7, #19]
+ 801403a:	e020      	b.n	801407e <netconn_recv+0xd6>
+    }
+    LWIP_ASSERT("p != NULL", p != NULL);
+ 801403c:	68fb      	ldr	r3, [r7, #12]
+ 801403e:	2b00      	cmp	r3, #0
+ 8014040:	d106      	bne.n	8014050 <netconn_recv+0xa8>
+ 8014042:	4b11      	ldr	r3, [pc, #68]	; (8014088 <netconn_recv+0xe0>)
+ 8014044:	f240 3279 	movw	r2, #889	; 0x379
+ 8014048:	4913      	ldr	r1, [pc, #76]	; (8014098 <netconn_recv+0xf0>)
+ 801404a:	4811      	ldr	r0, [pc, #68]	; (8014090 <netconn_recv+0xe8>)
+ 801404c:	f00d fc9c 	bl	8021988 <iprintf>
+
+    buf->p = p;
+ 8014050:	68fa      	ldr	r2, [r7, #12]
+ 8014052:	697b      	ldr	r3, [r7, #20]
+ 8014054:	601a      	str	r2, [r3, #0]
+    buf->ptr = p;
+ 8014056:	68fa      	ldr	r2, [r7, #12]
+ 8014058:	697b      	ldr	r3, [r7, #20]
+ 801405a:	605a      	str	r2, [r3, #4]
+    buf->port = 0;
+ 801405c:	697b      	ldr	r3, [r7, #20]
+ 801405e:	2200      	movs	r2, #0
+ 8014060:	819a      	strh	r2, [r3, #12]
+    ip_addr_set_zero(&buf->addr);
+ 8014062:	697b      	ldr	r3, [r7, #20]
+ 8014064:	2200      	movs	r2, #0
+ 8014066:	609a      	str	r2, [r3, #8]
+    *new_buf = buf;
+ 8014068:	683b      	ldr	r3, [r7, #0]
+ 801406a:	697a      	ldr	r2, [r7, #20]
+ 801406c:	601a      	str	r2, [r3, #0]
+    /* don't set conn->last_err: it's only ERR_OK, anyway */
+    return ERR_OK;
+ 801406e:	2300      	movs	r3, #0
+ 8014070:	e005      	b.n	801407e <netconn_recv+0xd6>
+#if LWIP_TCP && (LWIP_UDP || LWIP_RAW)
+  else
+#endif /* LWIP_TCP && (LWIP_UDP || LWIP_RAW) */
+  {
+#if (LWIP_UDP || LWIP_RAW)
+    return netconn_recv_data(conn, (void **)new_buf, 0);
+ 8014072:	2200      	movs	r2, #0
+ 8014074:	6839      	ldr	r1, [r7, #0]
+ 8014076:	6878      	ldr	r0, [r7, #4]
+ 8014078:	f7ff fe1a 	bl	8013cb0 <netconn_recv_data>
+ 801407c:	4603      	mov	r3, r0
+#endif /* (LWIP_UDP || LWIP_RAW) */
+  }
+}
+ 801407e:	4618      	mov	r0, r3
+ 8014080:	3718      	adds	r7, #24
+ 8014082:	46bd      	mov	sp, r7
+ 8014084:	bd80      	pop	{r7, pc}
+ 8014086:	bf00      	nop
+ 8014088:	080232cc 	.word	0x080232cc
+ 801408c:	080234e4 	.word	0x080234e4
+ 8014090:	08023324 	.word	0x08023324
+ 8014094:	08023504 	.word	0x08023504
+ 8014098:	0802357c 	.word	0x0802357c
+
+0801409c <netconn_write_partly>:
+ * @return ERR_OK if data was sent, any other err_t on error
+ */
+err_t
+netconn_write_partly(struct netconn *conn, const void *dataptr, size_t size,
+                     u8_t apiflags, size_t *bytes_written)
+{
+ 801409c:	b580      	push	{r7, lr}
+ 801409e:	b088      	sub	sp, #32
+ 80140a0:	af02      	add	r7, sp, #8
+ 80140a2:	60f8      	str	r0, [r7, #12]
+ 80140a4:	60b9      	str	r1, [r7, #8]
+ 80140a6:	607a      	str	r2, [r7, #4]
+ 80140a8:	70fb      	strb	r3, [r7, #3]
+  struct netvector vector;
+  vector.ptr = dataptr;
+ 80140aa:	68bb      	ldr	r3, [r7, #8]
+ 80140ac:	613b      	str	r3, [r7, #16]
+  vector.len = size;
+ 80140ae:	687b      	ldr	r3, [r7, #4]
+ 80140b0:	617b      	str	r3, [r7, #20]
+  return netconn_write_vectors_partly(conn, &vector, 1, apiflags, bytes_written);
+ 80140b2:	78fa      	ldrb	r2, [r7, #3]
+ 80140b4:	f107 0110 	add.w	r1, r7, #16
+ 80140b8:	6a3b      	ldr	r3, [r7, #32]
+ 80140ba:	9300      	str	r3, [sp, #0]
+ 80140bc:	4613      	mov	r3, r2
+ 80140be:	2201      	movs	r2, #1
+ 80140c0:	68f8      	ldr	r0, [r7, #12]
+ 80140c2:	f000 f805 	bl	80140d0 <netconn_write_vectors_partly>
+ 80140c6:	4603      	mov	r3, r0
+}
+ 80140c8:	4618      	mov	r0, r3
+ 80140ca:	3718      	adds	r7, #24
+ 80140cc:	46bd      	mov	sp, r7
+ 80140ce:	bd80      	pop	{r7, pc}
+
+080140d0 <netconn_write_vectors_partly>:
+ * @return ERR_OK if data was sent, any other err_t on error
+ */
+err_t
+netconn_write_vectors_partly(struct netconn *conn, struct netvector *vectors, u16_t vectorcnt,
+                             u8_t apiflags, size_t *bytes_written)
+{
+ 80140d0:	b580      	push	{r7, lr}
+ 80140d2:	b092      	sub	sp, #72	; 0x48
+ 80140d4:	af00      	add	r7, sp, #0
+ 80140d6:	60f8      	str	r0, [r7, #12]
+ 80140d8:	60b9      	str	r1, [r7, #8]
+ 80140da:	4611      	mov	r1, r2
+ 80140dc:	461a      	mov	r2, r3
+ 80140de:	460b      	mov	r3, r1
+ 80140e0:	80fb      	strh	r3, [r7, #6]
+ 80140e2:	4613      	mov	r3, r2
+ 80140e4:	717b      	strb	r3, [r7, #5]
+  err_t err;
+  u8_t dontblock;
+  size_t size;
+  int i;
+
+  LWIP_ERROR("netconn_write: invalid conn",  (conn != NULL), return ERR_ARG;);
+ 80140e6:	68fb      	ldr	r3, [r7, #12]
+ 80140e8:	2b00      	cmp	r3, #0
+ 80140ea:	d109      	bne.n	8014100 <netconn_write_vectors_partly+0x30>
+ 80140ec:	4b4e      	ldr	r3, [pc, #312]	; (8014228 <netconn_write_vectors_partly+0x158>)
+ 80140ee:	f240 32ee 	movw	r2, #1006	; 0x3ee
+ 80140f2:	494e      	ldr	r1, [pc, #312]	; (801422c <netconn_write_vectors_partly+0x15c>)
+ 80140f4:	484e      	ldr	r0, [pc, #312]	; (8014230 <netconn_write_vectors_partly+0x160>)
+ 80140f6:	f00d fc47 	bl	8021988 <iprintf>
+ 80140fa:	f06f 030f 	mvn.w	r3, #15
+ 80140fe:	e08e      	b.n	801421e <netconn_write_vectors_partly+0x14e>
+  LWIP_ERROR("netconn_write: invalid conn->type",  (NETCONNTYPE_GROUP(conn->type) == NETCONN_TCP), return ERR_VAL;);
+ 8014100:	68fb      	ldr	r3, [r7, #12]
+ 8014102:	781b      	ldrb	r3, [r3, #0]
+ 8014104:	f003 03f0 	and.w	r3, r3, #240	; 0xf0
+ 8014108:	2b10      	cmp	r3, #16
+ 801410a:	d009      	beq.n	8014120 <netconn_write_vectors_partly+0x50>
+ 801410c:	4b46      	ldr	r3, [pc, #280]	; (8014228 <netconn_write_vectors_partly+0x158>)
+ 801410e:	f240 32ef 	movw	r2, #1007	; 0x3ef
+ 8014112:	4948      	ldr	r1, [pc, #288]	; (8014234 <netconn_write_vectors_partly+0x164>)
+ 8014114:	4846      	ldr	r0, [pc, #280]	; (8014230 <netconn_write_vectors_partly+0x160>)
+ 8014116:	f00d fc37 	bl	8021988 <iprintf>
+ 801411a:	f06f 0305 	mvn.w	r3, #5
+ 801411e:	e07e      	b.n	801421e <netconn_write_vectors_partly+0x14e>
+  dontblock = netconn_is_nonblocking(conn) || (apiflags & NETCONN_DONTBLOCK);
+ 8014120:	68fb      	ldr	r3, [r7, #12]
+ 8014122:	7f1b      	ldrb	r3, [r3, #28]
+ 8014124:	f003 0302 	and.w	r3, r3, #2
+ 8014128:	2b00      	cmp	r3, #0
+ 801412a:	d104      	bne.n	8014136 <netconn_write_vectors_partly+0x66>
+ 801412c:	797b      	ldrb	r3, [r7, #5]
+ 801412e:	f003 0304 	and.w	r3, r3, #4
+ 8014132:	2b00      	cmp	r3, #0
+ 8014134:	d001      	beq.n	801413a <netconn_write_vectors_partly+0x6a>
+ 8014136:	2301      	movs	r3, #1
+ 8014138:	e000      	b.n	801413c <netconn_write_vectors_partly+0x6c>
+ 801413a:	2300      	movs	r3, #0
+ 801413c:	f887 303f 	strb.w	r3, [r7, #63]	; 0x3f
+#if LWIP_SO_SNDTIMEO
+  if (conn->send_timeout != 0) {
+    dontblock = 1;
+  }
+#endif /* LWIP_SO_SNDTIMEO */
+  if (dontblock && !bytes_written) {
+ 8014140:	f897 303f 	ldrb.w	r3, [r7, #63]	; 0x3f
+ 8014144:	2b00      	cmp	r3, #0
+ 8014146:	d005      	beq.n	8014154 <netconn_write_vectors_partly+0x84>
+ 8014148:	6d3b      	ldr	r3, [r7, #80]	; 0x50
+ 801414a:	2b00      	cmp	r3, #0
+ 801414c:	d102      	bne.n	8014154 <netconn_write_vectors_partly+0x84>
+    /* This implies netconn_write() cannot be used for non-blocking send, since
+       it has no way to return the number of bytes written. */
+    return ERR_VAL;
+ 801414e:	f06f 0305 	mvn.w	r3, #5
+ 8014152:	e064      	b.n	801421e <netconn_write_vectors_partly+0x14e>
+  }
+
+  /* sum up the total size */
+  size = 0;
+ 8014154:	2300      	movs	r3, #0
+ 8014156:	647b      	str	r3, [r7, #68]	; 0x44
+  for (i = 0; i < vectorcnt; i++) {
+ 8014158:	2300      	movs	r3, #0
+ 801415a:	643b      	str	r3, [r7, #64]	; 0x40
+ 801415c:	e015      	b.n	801418a <netconn_write_vectors_partly+0xba>
+    size += vectors[i].len;
+ 801415e:	6c3b      	ldr	r3, [r7, #64]	; 0x40
+ 8014160:	00db      	lsls	r3, r3, #3
+ 8014162:	68ba      	ldr	r2, [r7, #8]
+ 8014164:	4413      	add	r3, r2
+ 8014166:	685b      	ldr	r3, [r3, #4]
+ 8014168:	6c7a      	ldr	r2, [r7, #68]	; 0x44
+ 801416a:	4413      	add	r3, r2
+ 801416c:	647b      	str	r3, [r7, #68]	; 0x44
+    if (size < vectors[i].len) {
+ 801416e:	6c3b      	ldr	r3, [r7, #64]	; 0x40
+ 8014170:	00db      	lsls	r3, r3, #3
+ 8014172:	68ba      	ldr	r2, [r7, #8]
+ 8014174:	4413      	add	r3, r2
+ 8014176:	685b      	ldr	r3, [r3, #4]
+ 8014178:	6c7a      	ldr	r2, [r7, #68]	; 0x44
+ 801417a:	429a      	cmp	r2, r3
+ 801417c:	d202      	bcs.n	8014184 <netconn_write_vectors_partly+0xb4>
+      /* overflow */
+      return ERR_VAL;
+ 801417e:	f06f 0305 	mvn.w	r3, #5
+ 8014182:	e04c      	b.n	801421e <netconn_write_vectors_partly+0x14e>
+  for (i = 0; i < vectorcnt; i++) {
+ 8014184:	6c3b      	ldr	r3, [r7, #64]	; 0x40
+ 8014186:	3301      	adds	r3, #1
+ 8014188:	643b      	str	r3, [r7, #64]	; 0x40
+ 801418a:	88fb      	ldrh	r3, [r7, #6]
+ 801418c:	6c3a      	ldr	r2, [r7, #64]	; 0x40
+ 801418e:	429a      	cmp	r2, r3
+ 8014190:	dbe5      	blt.n	801415e <netconn_write_vectors_partly+0x8e>
+    }
+  }
+  if (size == 0) {
+ 8014192:	6c7b      	ldr	r3, [r7, #68]	; 0x44
+ 8014194:	2b00      	cmp	r3, #0
+ 8014196:	d101      	bne.n	801419c <netconn_write_vectors_partly+0xcc>
+    return ERR_OK;
+ 8014198:	2300      	movs	r3, #0
+ 801419a:	e040      	b.n	801421e <netconn_write_vectors_partly+0x14e>
+  } else if (size > SSIZE_MAX) {
+ 801419c:	6c7b      	ldr	r3, [r7, #68]	; 0x44
+ 801419e:	2b00      	cmp	r3, #0
+ 80141a0:	da0a      	bge.n	80141b8 <netconn_write_vectors_partly+0xe8>
+    ssize_t limited;
+    /* this is required by the socket layer (cannot send full size_t range) */
+    if (!bytes_written) {
+ 80141a2:	6d3b      	ldr	r3, [r7, #80]	; 0x50
+ 80141a4:	2b00      	cmp	r3, #0
+ 80141a6:	d102      	bne.n	80141ae <netconn_write_vectors_partly+0xde>
+      return ERR_VAL;
+ 80141a8:	f06f 0305 	mvn.w	r3, #5
+ 80141ac:	e037      	b.n	801421e <netconn_write_vectors_partly+0x14e>
+    }
+    /* limit the amount of data to send */
+    limited = SSIZE_MAX;
+ 80141ae:	f06f 4300 	mvn.w	r3, #2147483648	; 0x80000000
+ 80141b2:	63bb      	str	r3, [r7, #56]	; 0x38
+    size = (size_t)limited;
+ 80141b4:	6bbb      	ldr	r3, [r7, #56]	; 0x38
+ 80141b6:	647b      	str	r3, [r7, #68]	; 0x44
+  }
+
+  API_MSG_VAR_ALLOC(msg);
+  /* non-blocking write sends as much  */
+  API_MSG_VAR_REF(msg).conn = conn;
+ 80141b8:	68fb      	ldr	r3, [r7, #12]
+ 80141ba:	617b      	str	r3, [r7, #20]
+  API_MSG_VAR_REF(msg).msg.w.vector = vectors;
+ 80141bc:	68bb      	ldr	r3, [r7, #8]
+ 80141be:	61fb      	str	r3, [r7, #28]
+  API_MSG_VAR_REF(msg).msg.w.vector_cnt = vectorcnt;
+ 80141c0:	88fb      	ldrh	r3, [r7, #6]
+ 80141c2:	843b      	strh	r3, [r7, #32]
+  API_MSG_VAR_REF(msg).msg.w.vector_off = 0;
+ 80141c4:	2300      	movs	r3, #0
+ 80141c6:	627b      	str	r3, [r7, #36]	; 0x24
+  API_MSG_VAR_REF(msg).msg.w.apiflags = apiflags;
+ 80141c8:	797b      	ldrb	r3, [r7, #5]
+ 80141ca:	f887 3030 	strb.w	r3, [r7, #48]	; 0x30
+  API_MSG_VAR_REF(msg).msg.w.len = size;
+ 80141ce:	6c7b      	ldr	r3, [r7, #68]	; 0x44
+ 80141d0:	62bb      	str	r3, [r7, #40]	; 0x28
+  API_MSG_VAR_REF(msg).msg.w.offset = 0;
+ 80141d2:	2300      	movs	r3, #0
+ 80141d4:	62fb      	str	r3, [r7, #44]	; 0x2c
+#endif /* LWIP_SO_SNDTIMEO */
+
+  /* For locking the core: this _can_ be delayed on low memory/low send buffer,
+     but if it is, this is done inside api_msg.c:do_write(), so we can use the
+     non-blocking version here. */
+  err = netconn_apimsg(lwip_netconn_do_write, &API_MSG_VAR_REF(msg));
+ 80141d6:	f107 0314 	add.w	r3, r7, #20
+ 80141da:	4619      	mov	r1, r3
+ 80141dc:	4816      	ldr	r0, [pc, #88]	; (8014238 <netconn_write_vectors_partly+0x168>)
+ 80141de:	f7ff fc1d 	bl	8013a1c <netconn_apimsg>
+ 80141e2:	4603      	mov	r3, r0
+ 80141e4:	f887 3037 	strb.w	r3, [r7, #55]	; 0x37
+  if (err == ERR_OK) {
+ 80141e8:	f997 3037 	ldrsb.w	r3, [r7, #55]	; 0x37
+ 80141ec:	2b00      	cmp	r3, #0
+ 80141ee:	d114      	bne.n	801421a <netconn_write_vectors_partly+0x14a>
+    if (bytes_written != NULL) {
+ 80141f0:	6d3b      	ldr	r3, [r7, #80]	; 0x50
+ 80141f2:	2b00      	cmp	r3, #0
+ 80141f4:	d002      	beq.n	80141fc <netconn_write_vectors_partly+0x12c>
+      *bytes_written = API_MSG_VAR_REF(msg).msg.w.offset;
+ 80141f6:	6afa      	ldr	r2, [r7, #44]	; 0x2c
+ 80141f8:	6d3b      	ldr	r3, [r7, #80]	; 0x50
+ 80141fa:	601a      	str	r2, [r3, #0]
+    }
+    /* for blocking, check all requested bytes were written, NOTE: send_timeout is
+       treated as dontblock (see dontblock assignment above) */
+    if (!dontblock) {
+ 80141fc:	f897 303f 	ldrb.w	r3, [r7, #63]	; 0x3f
+ 8014200:	2b00      	cmp	r3, #0
+ 8014202:	d10a      	bne.n	801421a <netconn_write_vectors_partly+0x14a>
+      LWIP_ASSERT("do_write failed to write all bytes", API_MSG_VAR_REF(msg).msg.w.offset == size);
+ 8014204:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 8014206:	6c7a      	ldr	r2, [r7, #68]	; 0x44
+ 8014208:	429a      	cmp	r2, r3
+ 801420a:	d006      	beq.n	801421a <netconn_write_vectors_partly+0x14a>
+ 801420c:	4b06      	ldr	r3, [pc, #24]	; (8014228 <netconn_write_vectors_partly+0x158>)
+ 801420e:	f44f 6286 	mov.w	r2, #1072	; 0x430
+ 8014212:	490a      	ldr	r1, [pc, #40]	; (801423c <netconn_write_vectors_partly+0x16c>)
+ 8014214:	4806      	ldr	r0, [pc, #24]	; (8014230 <netconn_write_vectors_partly+0x160>)
+ 8014216:	f00d fbb7 	bl	8021988 <iprintf>
+    }
+  }
+  API_MSG_VAR_FREE(msg);
+
+  return err;
+ 801421a:	f997 3037 	ldrsb.w	r3, [r7, #55]	; 0x37
+}
+ 801421e:	4618      	mov	r0, r3
+ 8014220:	3748      	adds	r7, #72	; 0x48
+ 8014222:	46bd      	mov	sp, r7
+ 8014224:	bd80      	pop	{r7, pc}
+ 8014226:	bf00      	nop
+ 8014228:	080232cc 	.word	0x080232cc
+ 801422c:	080235a4 	.word	0x080235a4
+ 8014230:	08023324 	.word	0x08023324
+ 8014234:	080235c0 	.word	0x080235c0
+ 8014238:	0801586d 	.word	0x0801586d
+ 801423c:	080235e4 	.word	0x080235e4
+
+08014240 <netconn_close_shutdown>:
+ * @param how fully close or only shutdown one side?
+ * @return ERR_OK if the netconn was closed, any other err_t on error
+ */
+static err_t
+netconn_close_shutdown(struct netconn *conn, u8_t how)
+{
+ 8014240:	b580      	push	{r7, lr}
+ 8014242:	b08c      	sub	sp, #48	; 0x30
+ 8014244:	af00      	add	r7, sp, #0
+ 8014246:	6078      	str	r0, [r7, #4]
+ 8014248:	460b      	mov	r3, r1
+ 801424a:	70fb      	strb	r3, [r7, #3]
+  API_MSG_VAR_DECLARE(msg);
+  err_t err;
+  LWIP_UNUSED_ARG(how);
+
+  LWIP_ERROR("netconn_close: invalid conn",  (conn != NULL), return ERR_ARG;);
+ 801424c:	687b      	ldr	r3, [r7, #4]
+ 801424e:	2b00      	cmp	r3, #0
+ 8014250:	d109      	bne.n	8014266 <netconn_close_shutdown+0x26>
+ 8014252:	4b0f      	ldr	r3, [pc, #60]	; (8014290 <netconn_close_shutdown+0x50>)
+ 8014254:	f240 4247 	movw	r2, #1095	; 0x447
+ 8014258:	490e      	ldr	r1, [pc, #56]	; (8014294 <netconn_close_shutdown+0x54>)
+ 801425a:	480f      	ldr	r0, [pc, #60]	; (8014298 <netconn_close_shutdown+0x58>)
+ 801425c:	f00d fb94 	bl	8021988 <iprintf>
+ 8014260:	f06f 030f 	mvn.w	r3, #15
+ 8014264:	e010      	b.n	8014288 <netconn_close_shutdown+0x48>
+
+  API_MSG_VAR_ALLOC(msg);
+  API_MSG_VAR_REF(msg).conn = conn;
+ 8014266:	687b      	ldr	r3, [r7, #4]
+ 8014268:	60fb      	str	r3, [r7, #12]
+#if LWIP_TCP
+  /* shutting down both ends is the same as closing */
+  API_MSG_VAR_REF(msg).msg.sd.shut = how;
+ 801426a:	78fb      	ldrb	r3, [r7, #3]
+ 801426c:	753b      	strb	r3, [r7, #20]
+#if LWIP_SO_SNDTIMEO || LWIP_SO_LINGER
+  /* get the time we started, which is later compared to
+     sys_now() + conn->send_timeout */
+  API_MSG_VAR_REF(msg).msg.sd.time_started = sys_now();
+#else /* LWIP_SO_SNDTIMEO || LWIP_SO_LINGER */
+  API_MSG_VAR_REF(msg).msg.sd.polls_left =
+ 801426e:	2329      	movs	r3, #41	; 0x29
+ 8014270:	757b      	strb	r3, [r7, #21]
+    ((LWIP_TCP_CLOSE_TIMEOUT_MS_DEFAULT + TCP_SLOW_INTERVAL - 1) / TCP_SLOW_INTERVAL) + 1;
+#endif /* LWIP_SO_SNDTIMEO || LWIP_SO_LINGER */
+#endif /* LWIP_TCP */
+  err = netconn_apimsg(lwip_netconn_do_close, &API_MSG_VAR_REF(msg));
+ 8014272:	f107 030c 	add.w	r3, r7, #12
+ 8014276:	4619      	mov	r1, r3
+ 8014278:	4808      	ldr	r0, [pc, #32]	; (801429c <netconn_close_shutdown+0x5c>)
+ 801427a:	f7ff fbcf 	bl	8013a1c <netconn_apimsg>
+ 801427e:	4603      	mov	r3, r0
+ 8014280:	f887 302f 	strb.w	r3, [r7, #47]	; 0x2f
+  API_MSG_VAR_FREE(msg);
+
+  return err;
+ 8014284:	f997 302f 	ldrsb.w	r3, [r7, #47]	; 0x2f
+}
+ 8014288:	4618      	mov	r0, r3
+ 801428a:	3730      	adds	r7, #48	; 0x30
+ 801428c:	46bd      	mov	sp, r7
+ 801428e:	bd80      	pop	{r7, pc}
+ 8014290:	080232cc 	.word	0x080232cc
+ 8014294:	08023608 	.word	0x08023608
+ 8014298:	08023324 	.word	0x08023324
+ 801429c:	08015985 	.word	0x08015985
+
+080142a0 <netconn_close>:
+ * @param conn the TCP netconn to close
+ * @return ERR_OK if the netconn was closed, any other err_t on error
+ */
+err_t
+netconn_close(struct netconn *conn)
+{
+ 80142a0:	b580      	push	{r7, lr}
+ 80142a2:	b082      	sub	sp, #8
+ 80142a4:	af00      	add	r7, sp, #0
+ 80142a6:	6078      	str	r0, [r7, #4]
+  /* shutting down both ends is the same as closing */
+  return netconn_close_shutdown(conn, NETCONN_SHUT_RDWR);
+ 80142a8:	2103      	movs	r1, #3
+ 80142aa:	6878      	ldr	r0, [r7, #4]
+ 80142ac:	f7ff ffc8 	bl	8014240 <netconn_close_shutdown>
+ 80142b0:	4603      	mov	r3, r0
+}
+ 80142b2:	4618      	mov	r0, r3
+ 80142b4:	3708      	adds	r7, #8
+ 80142b6:	46bd      	mov	sp, r7
+ 80142b8:	bd80      	pop	{r7, pc}
+
+080142ba <netconn_err>:
+ * @param conn the netconn to get the error from
+ * @return and pending error or ERR_OK if no error was pending
+ */
+err_t
+netconn_err(struct netconn *conn)
+{
+ 80142ba:	b580      	push	{r7, lr}
+ 80142bc:	b084      	sub	sp, #16
+ 80142be:	af00      	add	r7, sp, #0
+ 80142c0:	6078      	str	r0, [r7, #4]
+  err_t err;
+  SYS_ARCH_DECL_PROTECT(lev);
+  if (conn == NULL) {
+ 80142c2:	687b      	ldr	r3, [r7, #4]
+ 80142c4:	2b00      	cmp	r3, #0
+ 80142c6:	d101      	bne.n	80142cc <netconn_err+0x12>
+    return ERR_OK;
+ 80142c8:	2300      	movs	r3, #0
+ 80142ca:	e00d      	b.n	80142e8 <netconn_err+0x2e>
+  }
+  SYS_ARCH_PROTECT(lev);
+ 80142cc:	f00d f9c2 	bl	8021654 <sys_arch_protect>
+ 80142d0:	60f8      	str	r0, [r7, #12]
+  err = conn->pending_err;
+ 80142d2:	687b      	ldr	r3, [r7, #4]
+ 80142d4:	7a1b      	ldrb	r3, [r3, #8]
+ 80142d6:	72fb      	strb	r3, [r7, #11]
+  conn->pending_err = ERR_OK;
+ 80142d8:	687b      	ldr	r3, [r7, #4]
+ 80142da:	2200      	movs	r2, #0
+ 80142dc:	721a      	strb	r2, [r3, #8]
+  SYS_ARCH_UNPROTECT(lev);
+ 80142de:	68f8      	ldr	r0, [r7, #12]
+ 80142e0:	f00d f9c6 	bl	8021670 <sys_arch_unprotect>
+  return err;
+ 80142e4:	f997 300b 	ldrsb.w	r3, [r7, #11]
+}
+ 80142e8:	4618      	mov	r0, r3
+ 80142ea:	3710      	adds	r7, #16
+ 80142ec:	46bd      	mov	sp, r7
+ 80142ee:	bd80      	pop	{r7, pc}
+
+080142f0 <lwip_netconn_err_to_msg>:
+const u8_t netconn_closed = 0;
+
+/** Translate an error to a unique void* passed via an mbox */
+static void *
+lwip_netconn_err_to_msg(err_t err)
+{
+ 80142f0:	b580      	push	{r7, lr}
+ 80142f2:	b082      	sub	sp, #8
+ 80142f4:	af00      	add	r7, sp, #0
+ 80142f6:	4603      	mov	r3, r0
+ 80142f8:	71fb      	strb	r3, [r7, #7]
+  switch (err) {
+ 80142fa:	f997 3007 	ldrsb.w	r3, [r7, #7]
+ 80142fe:	f113 0f0d 	cmn.w	r3, #13
+ 8014302:	d009      	beq.n	8014318 <lwip_netconn_err_to_msg+0x28>
+ 8014304:	f113 0f0d 	cmn.w	r3, #13
+ 8014308:	dc0c      	bgt.n	8014324 <lwip_netconn_err_to_msg+0x34>
+ 801430a:	f113 0f0f 	cmn.w	r3, #15
+ 801430e:	d007      	beq.n	8014320 <lwip_netconn_err_to_msg+0x30>
+ 8014310:	f113 0f0e 	cmn.w	r3, #14
+ 8014314:	d002      	beq.n	801431c <lwip_netconn_err_to_msg+0x2c>
+ 8014316:	e005      	b.n	8014324 <lwip_netconn_err_to_msg+0x34>
+    case ERR_ABRT:
+      return LWIP_CONST_CAST(void *, &netconn_aborted);
+ 8014318:	4b0a      	ldr	r3, [pc, #40]	; (8014344 <lwip_netconn_err_to_msg+0x54>)
+ 801431a:	e00e      	b.n	801433a <lwip_netconn_err_to_msg+0x4a>
+    case ERR_RST:
+      return LWIP_CONST_CAST(void *, &netconn_reset);
+ 801431c:	4b0a      	ldr	r3, [pc, #40]	; (8014348 <lwip_netconn_err_to_msg+0x58>)
+ 801431e:	e00c      	b.n	801433a <lwip_netconn_err_to_msg+0x4a>
+    case ERR_CLSD:
+      return LWIP_CONST_CAST(void *, &netconn_closed);
+ 8014320:	4b0a      	ldr	r3, [pc, #40]	; (801434c <lwip_netconn_err_to_msg+0x5c>)
+ 8014322:	e00a      	b.n	801433a <lwip_netconn_err_to_msg+0x4a>
+    default:
+      LWIP_ASSERT("unhandled error", err == ERR_OK);
+ 8014324:	f997 3007 	ldrsb.w	r3, [r7, #7]
+ 8014328:	2b00      	cmp	r3, #0
+ 801432a:	d005      	beq.n	8014338 <lwip_netconn_err_to_msg+0x48>
+ 801432c:	4b08      	ldr	r3, [pc, #32]	; (8014350 <lwip_netconn_err_to_msg+0x60>)
+ 801432e:	227d      	movs	r2, #125	; 0x7d
+ 8014330:	4908      	ldr	r1, [pc, #32]	; (8014354 <lwip_netconn_err_to_msg+0x64>)
+ 8014332:	4809      	ldr	r0, [pc, #36]	; (8014358 <lwip_netconn_err_to_msg+0x68>)
+ 8014334:	f00d fb28 	bl	8021988 <iprintf>
+      return NULL;
+ 8014338:	2300      	movs	r3, #0
+  }
+}
+ 801433a:	4618      	mov	r0, r3
+ 801433c:	3708      	adds	r7, #8
+ 801433e:	46bd      	mov	sp, r7
+ 8014340:	bd80      	pop	{r7, pc}
+ 8014342:	bf00      	nop
+ 8014344:	08026ba4 	.word	0x08026ba4
+ 8014348:	08026ba5 	.word	0x08026ba5
+ 801434c:	08026ba6 	.word	0x08026ba6
+ 8014350:	08023624 	.word	0x08023624
+ 8014354:	08023658 	.word	0x08023658
+ 8014358:	08023668 	.word	0x08023668
+
+0801435c <lwip_netconn_is_err_msg>:
+
+int
+lwip_netconn_is_err_msg(void *msg, err_t *err)
+{
+ 801435c:	b580      	push	{r7, lr}
+ 801435e:	b082      	sub	sp, #8
+ 8014360:	af00      	add	r7, sp, #0
+ 8014362:	6078      	str	r0, [r7, #4]
+ 8014364:	6039      	str	r1, [r7, #0]
+  LWIP_ASSERT("err != NULL", err != NULL);
+ 8014366:	683b      	ldr	r3, [r7, #0]
+ 8014368:	2b00      	cmp	r3, #0
+ 801436a:	d105      	bne.n	8014378 <lwip_netconn_is_err_msg+0x1c>
+ 801436c:	4b12      	ldr	r3, [pc, #72]	; (80143b8 <lwip_netconn_is_err_msg+0x5c>)
+ 801436e:	2285      	movs	r2, #133	; 0x85
+ 8014370:	4912      	ldr	r1, [pc, #72]	; (80143bc <lwip_netconn_is_err_msg+0x60>)
+ 8014372:	4813      	ldr	r0, [pc, #76]	; (80143c0 <lwip_netconn_is_err_msg+0x64>)
+ 8014374:	f00d fb08 	bl	8021988 <iprintf>
+
+  if (msg == &netconn_aborted) {
+ 8014378:	687b      	ldr	r3, [r7, #4]
+ 801437a:	4a12      	ldr	r2, [pc, #72]	; (80143c4 <lwip_netconn_is_err_msg+0x68>)
+ 801437c:	4293      	cmp	r3, r2
+ 801437e:	d104      	bne.n	801438a <lwip_netconn_is_err_msg+0x2e>
+    *err = ERR_ABRT;
+ 8014380:	683b      	ldr	r3, [r7, #0]
+ 8014382:	22f3      	movs	r2, #243	; 0xf3
+ 8014384:	701a      	strb	r2, [r3, #0]
+    return 1;
+ 8014386:	2301      	movs	r3, #1
+ 8014388:	e012      	b.n	80143b0 <lwip_netconn_is_err_msg+0x54>
+  } else if (msg == &netconn_reset) {
+ 801438a:	687b      	ldr	r3, [r7, #4]
+ 801438c:	4a0e      	ldr	r2, [pc, #56]	; (80143c8 <lwip_netconn_is_err_msg+0x6c>)
+ 801438e:	4293      	cmp	r3, r2
+ 8014390:	d104      	bne.n	801439c <lwip_netconn_is_err_msg+0x40>
+    *err = ERR_RST;
+ 8014392:	683b      	ldr	r3, [r7, #0]
+ 8014394:	22f2      	movs	r2, #242	; 0xf2
+ 8014396:	701a      	strb	r2, [r3, #0]
+    return 1;
+ 8014398:	2301      	movs	r3, #1
+ 801439a:	e009      	b.n	80143b0 <lwip_netconn_is_err_msg+0x54>
+  } else if (msg == &netconn_closed) {
+ 801439c:	687b      	ldr	r3, [r7, #4]
+ 801439e:	4a0b      	ldr	r2, [pc, #44]	; (80143cc <lwip_netconn_is_err_msg+0x70>)
+ 80143a0:	4293      	cmp	r3, r2
+ 80143a2:	d104      	bne.n	80143ae <lwip_netconn_is_err_msg+0x52>
+    *err = ERR_CLSD;
+ 80143a4:	683b      	ldr	r3, [r7, #0]
+ 80143a6:	22f1      	movs	r2, #241	; 0xf1
+ 80143a8:	701a      	strb	r2, [r3, #0]
+    return 1;
+ 80143aa:	2301      	movs	r3, #1
+ 80143ac:	e000      	b.n	80143b0 <lwip_netconn_is_err_msg+0x54>
+  }
+  return 0;
+ 80143ae:	2300      	movs	r3, #0
+}
+ 80143b0:	4618      	mov	r0, r3
+ 80143b2:	3708      	adds	r7, #8
+ 80143b4:	46bd      	mov	sp, r7
+ 80143b6:	bd80      	pop	{r7, pc}
+ 80143b8:	08023624 	.word	0x08023624
+ 80143bc:	08023690 	.word	0x08023690
+ 80143c0:	08023668 	.word	0x08023668
+ 80143c4:	08026ba4 	.word	0x08026ba4
+ 80143c8:	08026ba5 	.word	0x08026ba5
+ 80143cc:	08026ba6 	.word	0x08026ba6
+
+080143d0 <recv_udp>:
+ * @see udp.h (struct udp_pcb.recv) for parameters
+ */
+static void
+recv_udp(void *arg, struct udp_pcb *pcb, struct pbuf *p,
+         const ip_addr_t *addr, u16_t port)
+{
+ 80143d0:	b580      	push	{r7, lr}
+ 80143d2:	b088      	sub	sp, #32
+ 80143d4:	af00      	add	r7, sp, #0
+ 80143d6:	60f8      	str	r0, [r7, #12]
+ 80143d8:	60b9      	str	r1, [r7, #8]
+ 80143da:	607a      	str	r2, [r7, #4]
+ 80143dc:	603b      	str	r3, [r7, #0]
+#if LWIP_SO_RCVBUF
+  int recv_avail;
+#endif /* LWIP_SO_RCVBUF */
+
+  LWIP_UNUSED_ARG(pcb); /* only used for asserts... */
+  LWIP_ASSERT("recv_udp must have a pcb argument", pcb != NULL);
+ 80143de:	68bb      	ldr	r3, [r7, #8]
+ 80143e0:	2b00      	cmp	r3, #0
+ 80143e2:	d105      	bne.n	80143f0 <recv_udp+0x20>
+ 80143e4:	4b34      	ldr	r3, [pc, #208]	; (80144b8 <recv_udp+0xe8>)
+ 80143e6:	22e5      	movs	r2, #229	; 0xe5
+ 80143e8:	4934      	ldr	r1, [pc, #208]	; (80144bc <recv_udp+0xec>)
+ 80143ea:	4835      	ldr	r0, [pc, #212]	; (80144c0 <recv_udp+0xf0>)
+ 80143ec:	f00d facc 	bl	8021988 <iprintf>
+  LWIP_ASSERT("recv_udp must have an argument", arg != NULL);
+ 80143f0:	68fb      	ldr	r3, [r7, #12]
+ 80143f2:	2b00      	cmp	r3, #0
+ 80143f4:	d105      	bne.n	8014402 <recv_udp+0x32>
+ 80143f6:	4b30      	ldr	r3, [pc, #192]	; (80144b8 <recv_udp+0xe8>)
+ 80143f8:	22e6      	movs	r2, #230	; 0xe6
+ 80143fa:	4932      	ldr	r1, [pc, #200]	; (80144c4 <recv_udp+0xf4>)
+ 80143fc:	4830      	ldr	r0, [pc, #192]	; (80144c0 <recv_udp+0xf0>)
+ 80143fe:	f00d fac3 	bl	8021988 <iprintf>
+  conn = (struct netconn *)arg;
+ 8014402:	68fb      	ldr	r3, [r7, #12]
+ 8014404:	61fb      	str	r3, [r7, #28]
+
+  if (conn == NULL) {
+ 8014406:	69fb      	ldr	r3, [r7, #28]
+ 8014408:	2b00      	cmp	r3, #0
+ 801440a:	d103      	bne.n	8014414 <recv_udp+0x44>
+    pbuf_free(p);
+ 801440c:	6878      	ldr	r0, [r7, #4]
+ 801440e:	f003 fb73 	bl	8017af8 <pbuf_free>
+    return;
+ 8014412:	e04d      	b.n	80144b0 <recv_udp+0xe0>
+  }
+
+  LWIP_ASSERT("recv_udp: recv for wrong pcb!", conn->pcb.udp == pcb);
+ 8014414:	69fb      	ldr	r3, [r7, #28]
+ 8014416:	685b      	ldr	r3, [r3, #4]
+ 8014418:	68ba      	ldr	r2, [r7, #8]
+ 801441a:	429a      	cmp	r2, r3
+ 801441c:	d005      	beq.n	801442a <recv_udp+0x5a>
+ 801441e:	4b26      	ldr	r3, [pc, #152]	; (80144b8 <recv_udp+0xe8>)
+ 8014420:	22ee      	movs	r2, #238	; 0xee
+ 8014422:	4929      	ldr	r1, [pc, #164]	; (80144c8 <recv_udp+0xf8>)
+ 8014424:	4826      	ldr	r0, [pc, #152]	; (80144c0 <recv_udp+0xf0>)
+ 8014426:	f00d faaf 	bl	8021988 <iprintf>
+#if LWIP_SO_RCVBUF
+  SYS_ARCH_GET(conn->recv_avail, recv_avail);
+  if (!NETCONN_MBOX_VALID(conn, &conn->recvmbox) ||
+      ((recv_avail + (int)(p->tot_len)) > conn->recv_bufsize)) {
+#else  /* LWIP_SO_RCVBUF */
+  if (!NETCONN_MBOX_VALID(conn, &conn->recvmbox)) {
+ 801442a:	69fb      	ldr	r3, [r7, #28]
+ 801442c:	3310      	adds	r3, #16
+ 801442e:	4618      	mov	r0, r3
+ 8014430:	f00c fff5 	bl	802141e <sys_mbox_valid>
+ 8014434:	4603      	mov	r3, r0
+ 8014436:	2b00      	cmp	r3, #0
+ 8014438:	d103      	bne.n	8014442 <recv_udp+0x72>
+#endif /* LWIP_SO_RCVBUF */
+    pbuf_free(p);
+ 801443a:	6878      	ldr	r0, [r7, #4]
+ 801443c:	f003 fb5c 	bl	8017af8 <pbuf_free>
+    return;
+ 8014440:	e036      	b.n	80144b0 <recv_udp+0xe0>
+  }
+
+  buf = (struct netbuf *)memp_malloc(MEMP_NETBUF);
+ 8014442:	2006      	movs	r0, #6
+ 8014444:	f002 fb44 	bl	8016ad0 <memp_malloc>
+ 8014448:	61b8      	str	r0, [r7, #24]
+  if (buf == NULL) {
+ 801444a:	69bb      	ldr	r3, [r7, #24]
+ 801444c:	2b00      	cmp	r3, #0
+ 801444e:	d103      	bne.n	8014458 <recv_udp+0x88>
+    pbuf_free(p);
+ 8014450:	6878      	ldr	r0, [r7, #4]
+ 8014452:	f003 fb51 	bl	8017af8 <pbuf_free>
+    return;
+ 8014456:	e02b      	b.n	80144b0 <recv_udp+0xe0>
+  } else {
+    buf->p = p;
+ 8014458:	69bb      	ldr	r3, [r7, #24]
+ 801445a:	687a      	ldr	r2, [r7, #4]
+ 801445c:	601a      	str	r2, [r3, #0]
+    buf->ptr = p;
+ 801445e:	69bb      	ldr	r3, [r7, #24]
+ 8014460:	687a      	ldr	r2, [r7, #4]
+ 8014462:	605a      	str	r2, [r3, #4]
+    ip_addr_set(&buf->addr, addr);
+ 8014464:	683b      	ldr	r3, [r7, #0]
+ 8014466:	2b00      	cmp	r3, #0
+ 8014468:	d002      	beq.n	8014470 <recv_udp+0xa0>
+ 801446a:	683b      	ldr	r3, [r7, #0]
+ 801446c:	681b      	ldr	r3, [r3, #0]
+ 801446e:	e000      	b.n	8014472 <recv_udp+0xa2>
+ 8014470:	2300      	movs	r3, #0
+ 8014472:	69ba      	ldr	r2, [r7, #24]
+ 8014474:	6093      	str	r3, [r2, #8]
+    buf->port = port;
+ 8014476:	69bb      	ldr	r3, [r7, #24]
+ 8014478:	8d3a      	ldrh	r2, [r7, #40]	; 0x28
+ 801447a:	819a      	strh	r2, [r3, #12]
+      buf->toport_chksum = udphdr->dest;
+    }
+#endif /* LWIP_NETBUF_RECVINFO */
+  }
+
+  len = p->tot_len;
+ 801447c:	687b      	ldr	r3, [r7, #4]
+ 801447e:	891b      	ldrh	r3, [r3, #8]
+ 8014480:	82fb      	strh	r3, [r7, #22]
+  if (sys_mbox_trypost(&conn->recvmbox, buf) != ERR_OK) {
+ 8014482:	69fb      	ldr	r3, [r7, #28]
+ 8014484:	3310      	adds	r3, #16
+ 8014486:	69b9      	ldr	r1, [r7, #24]
+ 8014488:	4618      	mov	r0, r3
+ 801448a:	f00c ff53 	bl	8021334 <sys_mbox_trypost>
+ 801448e:	4603      	mov	r3, r0
+ 8014490:	2b00      	cmp	r3, #0
+ 8014492:	d003      	beq.n	801449c <recv_udp+0xcc>
+    netbuf_delete(buf);
+ 8014494:	69b8      	ldr	r0, [r7, #24]
+ 8014496:	f001 fb01 	bl	8015a9c <netbuf_delete>
+    return;
+ 801449a:	e009      	b.n	80144b0 <recv_udp+0xe0>
+  } else {
+#if LWIP_SO_RCVBUF
+    SYS_ARCH_INC(conn->recv_avail, len);
+#endif /* LWIP_SO_RCVBUF */
+    /* Register event with callback */
+    API_EVENT(conn, NETCONN_EVT_RCVPLUS, len);
+ 801449c:	69fb      	ldr	r3, [r7, #28]
+ 801449e:	6a5b      	ldr	r3, [r3, #36]	; 0x24
+ 80144a0:	2b00      	cmp	r3, #0
+ 80144a2:	d005      	beq.n	80144b0 <recv_udp+0xe0>
+ 80144a4:	69fb      	ldr	r3, [r7, #28]
+ 80144a6:	6a5b      	ldr	r3, [r3, #36]	; 0x24
+ 80144a8:	8afa      	ldrh	r2, [r7, #22]
+ 80144aa:	2100      	movs	r1, #0
+ 80144ac:	69f8      	ldr	r0, [r7, #28]
+ 80144ae:	4798      	blx	r3
+  }
+}
+ 80144b0:	3720      	adds	r7, #32
+ 80144b2:	46bd      	mov	sp, r7
+ 80144b4:	bd80      	pop	{r7, pc}
+ 80144b6:	bf00      	nop
+ 80144b8:	08023624 	.word	0x08023624
+ 80144bc:	0802369c 	.word	0x0802369c
+ 80144c0:	08023668 	.word	0x08023668
+ 80144c4:	080236c0 	.word	0x080236c0
+ 80144c8:	080236e0 	.word	0x080236e0
+
+080144cc <recv_tcp>:
+ *
+ * @see tcp.h (struct tcp_pcb.recv) for parameters and return value
+ */
+static err_t
+recv_tcp(void *arg, struct tcp_pcb *pcb, struct pbuf *p, err_t err)
+{
+ 80144cc:	b580      	push	{r7, lr}
+ 80144ce:	b088      	sub	sp, #32
+ 80144d0:	af00      	add	r7, sp, #0
+ 80144d2:	60f8      	str	r0, [r7, #12]
+ 80144d4:	60b9      	str	r1, [r7, #8]
+ 80144d6:	607a      	str	r2, [r7, #4]
+ 80144d8:	70fb      	strb	r3, [r7, #3]
+  struct netconn *conn;
+  u16_t len;
+  void *msg;
+
+  LWIP_UNUSED_ARG(pcb);
+  LWIP_ASSERT("recv_tcp must have a pcb argument", pcb != NULL);
+ 80144da:	68bb      	ldr	r3, [r7, #8]
+ 80144dc:	2b00      	cmp	r3, #0
+ 80144de:	d106      	bne.n	80144ee <recv_tcp+0x22>
+ 80144e0:	4b36      	ldr	r3, [pc, #216]	; (80145bc <recv_tcp+0xf0>)
+ 80144e2:	f44f 7296 	mov.w	r2, #300	; 0x12c
+ 80144e6:	4936      	ldr	r1, [pc, #216]	; (80145c0 <recv_tcp+0xf4>)
+ 80144e8:	4836      	ldr	r0, [pc, #216]	; (80145c4 <recv_tcp+0xf8>)
+ 80144ea:	f00d fa4d 	bl	8021988 <iprintf>
+  LWIP_ASSERT("recv_tcp must have an argument", arg != NULL);
+ 80144ee:	68fb      	ldr	r3, [r7, #12]
+ 80144f0:	2b00      	cmp	r3, #0
+ 80144f2:	d106      	bne.n	8014502 <recv_tcp+0x36>
+ 80144f4:	4b31      	ldr	r3, [pc, #196]	; (80145bc <recv_tcp+0xf0>)
+ 80144f6:	f240 122d 	movw	r2, #301	; 0x12d
+ 80144fa:	4933      	ldr	r1, [pc, #204]	; (80145c8 <recv_tcp+0xfc>)
+ 80144fc:	4831      	ldr	r0, [pc, #196]	; (80145c4 <recv_tcp+0xf8>)
+ 80144fe:	f00d fa43 	bl	8021988 <iprintf>
+  LWIP_ASSERT("err != ERR_OK unhandled", err == ERR_OK);
+ 8014502:	f997 3003 	ldrsb.w	r3, [r7, #3]
+ 8014506:	2b00      	cmp	r3, #0
+ 8014508:	d006      	beq.n	8014518 <recv_tcp+0x4c>
+ 801450a:	4b2c      	ldr	r3, [pc, #176]	; (80145bc <recv_tcp+0xf0>)
+ 801450c:	f44f 7297 	mov.w	r2, #302	; 0x12e
+ 8014510:	492e      	ldr	r1, [pc, #184]	; (80145cc <recv_tcp+0x100>)
+ 8014512:	482c      	ldr	r0, [pc, #176]	; (80145c4 <recv_tcp+0xf8>)
+ 8014514:	f00d fa38 	bl	8021988 <iprintf>
+  LWIP_UNUSED_ARG(err); /* for LWIP_NOASSERT */
+  conn = (struct netconn *)arg;
+ 8014518:	68fb      	ldr	r3, [r7, #12]
+ 801451a:	617b      	str	r3, [r7, #20]
+
+  if (conn == NULL) {
+ 801451c:	697b      	ldr	r3, [r7, #20]
+ 801451e:	2b00      	cmp	r3, #0
+ 8014520:	d102      	bne.n	8014528 <recv_tcp+0x5c>
+    return ERR_VAL;
+ 8014522:	f06f 0305 	mvn.w	r3, #5
+ 8014526:	e045      	b.n	80145b4 <recv_tcp+0xe8>
+  }
+  LWIP_ASSERT("recv_tcp: recv for wrong pcb!", conn->pcb.tcp == pcb);
+ 8014528:	697b      	ldr	r3, [r7, #20]
+ 801452a:	685b      	ldr	r3, [r3, #4]
+ 801452c:	68ba      	ldr	r2, [r7, #8]
+ 801452e:	429a      	cmp	r2, r3
+ 8014530:	d006      	beq.n	8014540 <recv_tcp+0x74>
+ 8014532:	4b22      	ldr	r3, [pc, #136]	; (80145bc <recv_tcp+0xf0>)
+ 8014534:	f240 1235 	movw	r2, #309	; 0x135
+ 8014538:	4925      	ldr	r1, [pc, #148]	; (80145d0 <recv_tcp+0x104>)
+ 801453a:	4822      	ldr	r0, [pc, #136]	; (80145c4 <recv_tcp+0xf8>)
+ 801453c:	f00d fa24 	bl	8021988 <iprintf>
+
+  if (!NETCONN_MBOX_VALID(conn, &conn->recvmbox)) {
+ 8014540:	697b      	ldr	r3, [r7, #20]
+ 8014542:	3310      	adds	r3, #16
+ 8014544:	4618      	mov	r0, r3
+ 8014546:	f00c ff6a 	bl	802141e <sys_mbox_valid>
+ 801454a:	4603      	mov	r3, r0
+ 801454c:	2b00      	cmp	r3, #0
+ 801454e:	d10d      	bne.n	801456c <recv_tcp+0xa0>
+    /* recvmbox already deleted */
+    if (p != NULL) {
+ 8014550:	687b      	ldr	r3, [r7, #4]
+ 8014552:	2b00      	cmp	r3, #0
+ 8014554:	d008      	beq.n	8014568 <recv_tcp+0x9c>
+      tcp_recved(pcb, p->tot_len);
+ 8014556:	687b      	ldr	r3, [r7, #4]
+ 8014558:	891b      	ldrh	r3, [r3, #8]
+ 801455a:	4619      	mov	r1, r3
+ 801455c:	68b8      	ldr	r0, [r7, #8]
+ 801455e:	f004 f9b9 	bl	80188d4 <tcp_recved>
+      pbuf_free(p);
+ 8014562:	6878      	ldr	r0, [r7, #4]
+ 8014564:	f003 fac8 	bl	8017af8 <pbuf_free>
+    }
+    return ERR_OK;
+ 8014568:	2300      	movs	r3, #0
+ 801456a:	e023      	b.n	80145b4 <recv_tcp+0xe8>
+  }
+  /* Unlike for UDP or RAW pcbs, don't check for available space
+     using recv_avail since that could break the connection
+     (data is already ACKed) */
+
+  if (p != NULL) {
+ 801456c:	687b      	ldr	r3, [r7, #4]
+ 801456e:	2b00      	cmp	r3, #0
+ 8014570:	d005      	beq.n	801457e <recv_tcp+0xb2>
+    msg = p;
+ 8014572:	687b      	ldr	r3, [r7, #4]
+ 8014574:	61bb      	str	r3, [r7, #24]
+    len = p->tot_len;
+ 8014576:	687b      	ldr	r3, [r7, #4]
+ 8014578:	891b      	ldrh	r3, [r3, #8]
+ 801457a:	83fb      	strh	r3, [r7, #30]
+ 801457c:	e003      	b.n	8014586 <recv_tcp+0xba>
+  } else {
+    msg = LWIP_CONST_CAST(void *, &netconn_closed);
+ 801457e:	4b15      	ldr	r3, [pc, #84]	; (80145d4 <recv_tcp+0x108>)
+ 8014580:	61bb      	str	r3, [r7, #24]
+    len = 0;
+ 8014582:	2300      	movs	r3, #0
+ 8014584:	83fb      	strh	r3, [r7, #30]
+  }
+
+  if (sys_mbox_trypost(&conn->recvmbox, msg) != ERR_OK) {
+ 8014586:	697b      	ldr	r3, [r7, #20]
+ 8014588:	3310      	adds	r3, #16
+ 801458a:	69b9      	ldr	r1, [r7, #24]
+ 801458c:	4618      	mov	r0, r3
+ 801458e:	f00c fed1 	bl	8021334 <sys_mbox_trypost>
+ 8014592:	4603      	mov	r3, r0
+ 8014594:	2b00      	cmp	r3, #0
+ 8014596:	d002      	beq.n	801459e <recv_tcp+0xd2>
+    /* don't deallocate p: it is presented to us later again from tcp_fasttmr! */
+    return ERR_MEM;
+ 8014598:	f04f 33ff 	mov.w	r3, #4294967295
+ 801459c:	e00a      	b.n	80145b4 <recv_tcp+0xe8>
+  } else {
+#if LWIP_SO_RCVBUF
+    SYS_ARCH_INC(conn->recv_avail, len);
+#endif /* LWIP_SO_RCVBUF */
+    /* Register event with callback */
+    API_EVENT(conn, NETCONN_EVT_RCVPLUS, len);
+ 801459e:	697b      	ldr	r3, [r7, #20]
+ 80145a0:	6a5b      	ldr	r3, [r3, #36]	; 0x24
+ 80145a2:	2b00      	cmp	r3, #0
+ 80145a4:	d005      	beq.n	80145b2 <recv_tcp+0xe6>
+ 80145a6:	697b      	ldr	r3, [r7, #20]
+ 80145a8:	6a5b      	ldr	r3, [r3, #36]	; 0x24
+ 80145aa:	8bfa      	ldrh	r2, [r7, #30]
+ 80145ac:	2100      	movs	r1, #0
+ 80145ae:	6978      	ldr	r0, [r7, #20]
+ 80145b0:	4798      	blx	r3
+  }
+
+  return ERR_OK;
+ 80145b2:	2300      	movs	r3, #0
+}
+ 80145b4:	4618      	mov	r0, r3
+ 80145b6:	3720      	adds	r7, #32
+ 80145b8:	46bd      	mov	sp, r7
+ 80145ba:	bd80      	pop	{r7, pc}
+ 80145bc:	08023624 	.word	0x08023624
+ 80145c0:	08023700 	.word	0x08023700
+ 80145c4:	08023668 	.word	0x08023668
+ 80145c8:	08023724 	.word	0x08023724
+ 80145cc:	08023744 	.word	0x08023744
+ 80145d0:	0802375c 	.word	0x0802375c
+ 80145d4:	08026ba6 	.word	0x08026ba6
+
+080145d8 <poll_tcp>:
+ *
+ * @see tcp.h (struct tcp_pcb.poll) for parameters and return value
+ */
+static err_t
+poll_tcp(void *arg, struct tcp_pcb *pcb)
+{
+ 80145d8:	b580      	push	{r7, lr}
+ 80145da:	b084      	sub	sp, #16
+ 80145dc:	af00      	add	r7, sp, #0
+ 80145de:	6078      	str	r0, [r7, #4]
+ 80145e0:	6039      	str	r1, [r7, #0]
+  struct netconn *conn = (struct netconn *)arg;
+ 80145e2:	687b      	ldr	r3, [r7, #4]
+ 80145e4:	60fb      	str	r3, [r7, #12]
+
+  LWIP_UNUSED_ARG(pcb);
+  LWIP_ASSERT("conn != NULL", (conn != NULL));
+ 80145e6:	68fb      	ldr	r3, [r7, #12]
+ 80145e8:	2b00      	cmp	r3, #0
+ 80145ea:	d106      	bne.n	80145fa <poll_tcp+0x22>
+ 80145ec:	4b2a      	ldr	r3, [pc, #168]	; (8014698 <poll_tcp+0xc0>)
+ 80145ee:	f44f 72b5 	mov.w	r2, #362	; 0x16a
+ 80145f2:	492a      	ldr	r1, [pc, #168]	; (801469c <poll_tcp+0xc4>)
+ 80145f4:	482a      	ldr	r0, [pc, #168]	; (80146a0 <poll_tcp+0xc8>)
+ 80145f6:	f00d f9c7 	bl	8021988 <iprintf>
+
+  if (conn->state == NETCONN_WRITE) {
+ 80145fa:	68fb      	ldr	r3, [r7, #12]
+ 80145fc:	785b      	ldrb	r3, [r3, #1]
+ 80145fe:	2b01      	cmp	r3, #1
+ 8014600:	d104      	bne.n	801460c <poll_tcp+0x34>
+    lwip_netconn_do_writemore(conn  WRITE_DELAYED);
+ 8014602:	2101      	movs	r1, #1
+ 8014604:	68f8      	ldr	r0, [r7, #12]
+ 8014606:	f000 ff63 	bl	80154d0 <lwip_netconn_do_writemore>
+ 801460a:	e016      	b.n	801463a <poll_tcp+0x62>
+  } else if (conn->state == NETCONN_CLOSE) {
+ 801460c:	68fb      	ldr	r3, [r7, #12]
+ 801460e:	785b      	ldrb	r3, [r3, #1]
+ 8014610:	2b04      	cmp	r3, #4
+ 8014612:	d112      	bne.n	801463a <poll_tcp+0x62>
+#if !LWIP_SO_SNDTIMEO && !LWIP_SO_LINGER
+    if (conn->current_msg && conn->current_msg->msg.sd.polls_left) {
+ 8014614:	68fb      	ldr	r3, [r7, #12]
+ 8014616:	6a1b      	ldr	r3, [r3, #32]
+ 8014618:	2b00      	cmp	r3, #0
+ 801461a:	d00a      	beq.n	8014632 <poll_tcp+0x5a>
+ 801461c:	68fb      	ldr	r3, [r7, #12]
+ 801461e:	6a1b      	ldr	r3, [r3, #32]
+ 8014620:	7a5b      	ldrb	r3, [r3, #9]
+ 8014622:	2b00      	cmp	r3, #0
+ 8014624:	d005      	beq.n	8014632 <poll_tcp+0x5a>
+      conn->current_msg->msg.sd.polls_left--;
+ 8014626:	68fb      	ldr	r3, [r7, #12]
+ 8014628:	6a1b      	ldr	r3, [r3, #32]
+ 801462a:	7a5a      	ldrb	r2, [r3, #9]
+ 801462c:	3a01      	subs	r2, #1
+ 801462e:	b2d2      	uxtb	r2, r2
+ 8014630:	725a      	strb	r2, [r3, #9]
+    }
+#endif /* !LWIP_SO_SNDTIMEO && !LWIP_SO_LINGER */
+    lwip_netconn_do_close_internal(conn  WRITE_DELAYED);
+ 8014632:	2101      	movs	r1, #1
+ 8014634:	68f8      	ldr	r0, [r7, #12]
+ 8014636:	f000 fb3f 	bl	8014cb8 <lwip_netconn_do_close_internal>
+  }
+  /* @todo: implement connect timeout here? */
+
+  /* Did a nonblocking write fail before? Then check available write-space. */
+  if (conn->flags & NETCONN_FLAG_CHECK_WRITESPACE) {
+ 801463a:	68fb      	ldr	r3, [r7, #12]
+ 801463c:	7f1b      	ldrb	r3, [r3, #28]
+ 801463e:	f003 0310 	and.w	r3, r3, #16
+ 8014642:	2b00      	cmp	r3, #0
+ 8014644:	d022      	beq.n	801468c <poll_tcp+0xb4>
+    /* If the queued byte- or pbuf-count drops below the configured low-water limit,
+       let select mark this pcb as writable again. */
+    if ((conn->pcb.tcp != NULL) && (tcp_sndbuf(conn->pcb.tcp) > TCP_SNDLOWAT) &&
+ 8014646:	68fb      	ldr	r3, [r7, #12]
+ 8014648:	685b      	ldr	r3, [r3, #4]
+ 801464a:	2b00      	cmp	r3, #0
+ 801464c:	d01e      	beq.n	801468c <poll_tcp+0xb4>
+ 801464e:	68fb      	ldr	r3, [r7, #12]
+ 8014650:	685b      	ldr	r3, [r3, #4]
+ 8014652:	f8b3 3064 	ldrh.w	r3, [r3, #100]	; 0x64
+ 8014656:	f640 3269 	movw	r2, #2921	; 0xb69
+ 801465a:	4293      	cmp	r3, r2
+ 801465c:	d916      	bls.n	801468c <poll_tcp+0xb4>
+        (tcp_sndqueuelen(conn->pcb.tcp) < TCP_SNDQUEUELOWAT)) {
+ 801465e:	68fb      	ldr	r3, [r7, #12]
+ 8014660:	685b      	ldr	r3, [r3, #4]
+ 8014662:	f8b3 3066 	ldrh.w	r3, [r3, #102]	; 0x66
+    if ((conn->pcb.tcp != NULL) && (tcp_sndbuf(conn->pcb.tcp) > TCP_SNDLOWAT) &&
+ 8014666:	2b07      	cmp	r3, #7
+ 8014668:	d810      	bhi.n	801468c <poll_tcp+0xb4>
+      netconn_clear_flags(conn, NETCONN_FLAG_CHECK_WRITESPACE);
+ 801466a:	68fb      	ldr	r3, [r7, #12]
+ 801466c:	7f1b      	ldrb	r3, [r3, #28]
+ 801466e:	f023 0310 	bic.w	r3, r3, #16
+ 8014672:	b2da      	uxtb	r2, r3
+ 8014674:	68fb      	ldr	r3, [r7, #12]
+ 8014676:	771a      	strb	r2, [r3, #28]
+      API_EVENT(conn, NETCONN_EVT_SENDPLUS, 0);
+ 8014678:	68fb      	ldr	r3, [r7, #12]
+ 801467a:	6a5b      	ldr	r3, [r3, #36]	; 0x24
+ 801467c:	2b00      	cmp	r3, #0
+ 801467e:	d005      	beq.n	801468c <poll_tcp+0xb4>
+ 8014680:	68fb      	ldr	r3, [r7, #12]
+ 8014682:	6a5b      	ldr	r3, [r3, #36]	; 0x24
+ 8014684:	2200      	movs	r2, #0
+ 8014686:	2102      	movs	r1, #2
+ 8014688:	68f8      	ldr	r0, [r7, #12]
+ 801468a:	4798      	blx	r3
+    }
+  }
+
+  return ERR_OK;
+ 801468c:	2300      	movs	r3, #0
+}
+ 801468e:	4618      	mov	r0, r3
+ 8014690:	3710      	adds	r7, #16
+ 8014692:	46bd      	mov	sp, r7
+ 8014694:	bd80      	pop	{r7, pc}
+ 8014696:	bf00      	nop
+ 8014698:	08023624 	.word	0x08023624
+ 801469c:	0802377c 	.word	0x0802377c
+ 80146a0:	08023668 	.word	0x08023668
+
+080146a4 <sent_tcp>:
+ *
+ * @see tcp.h (struct tcp_pcb.sent) for parameters and return value
+ */
+static err_t
+sent_tcp(void *arg, struct tcp_pcb *pcb, u16_t len)
+{
+ 80146a4:	b580      	push	{r7, lr}
+ 80146a6:	b086      	sub	sp, #24
+ 80146a8:	af00      	add	r7, sp, #0
+ 80146aa:	60f8      	str	r0, [r7, #12]
+ 80146ac:	60b9      	str	r1, [r7, #8]
+ 80146ae:	4613      	mov	r3, r2
+ 80146b0:	80fb      	strh	r3, [r7, #6]
+  struct netconn *conn = (struct netconn *)arg;
+ 80146b2:	68fb      	ldr	r3, [r7, #12]
+ 80146b4:	617b      	str	r3, [r7, #20]
+
+  LWIP_UNUSED_ARG(pcb);
+  LWIP_ASSERT("conn != NULL", (conn != NULL));
+ 80146b6:	697b      	ldr	r3, [r7, #20]
+ 80146b8:	2b00      	cmp	r3, #0
+ 80146ba:	d106      	bne.n	80146ca <sent_tcp+0x26>
+ 80146bc:	4b21      	ldr	r3, [pc, #132]	; (8014744 <sent_tcp+0xa0>)
+ 80146be:	f240 1293 	movw	r2, #403	; 0x193
+ 80146c2:	4921      	ldr	r1, [pc, #132]	; (8014748 <sent_tcp+0xa4>)
+ 80146c4:	4821      	ldr	r0, [pc, #132]	; (801474c <sent_tcp+0xa8>)
+ 80146c6:	f00d f95f 	bl	8021988 <iprintf>
+
+  if (conn) {
+ 80146ca:	697b      	ldr	r3, [r7, #20]
+ 80146cc:	2b00      	cmp	r3, #0
+ 80146ce:	d033      	beq.n	8014738 <sent_tcp+0x94>
+    if (conn->state == NETCONN_WRITE) {
+ 80146d0:	697b      	ldr	r3, [r7, #20]
+ 80146d2:	785b      	ldrb	r3, [r3, #1]
+ 80146d4:	2b01      	cmp	r3, #1
+ 80146d6:	d104      	bne.n	80146e2 <sent_tcp+0x3e>
+      lwip_netconn_do_writemore(conn  WRITE_DELAYED);
+ 80146d8:	2101      	movs	r1, #1
+ 80146da:	6978      	ldr	r0, [r7, #20]
+ 80146dc:	f000 fef8 	bl	80154d0 <lwip_netconn_do_writemore>
+ 80146e0:	e007      	b.n	80146f2 <sent_tcp+0x4e>
+    } else if (conn->state == NETCONN_CLOSE) {
+ 80146e2:	697b      	ldr	r3, [r7, #20]
+ 80146e4:	785b      	ldrb	r3, [r3, #1]
+ 80146e6:	2b04      	cmp	r3, #4
+ 80146e8:	d103      	bne.n	80146f2 <sent_tcp+0x4e>
+      lwip_netconn_do_close_internal(conn  WRITE_DELAYED);
+ 80146ea:	2101      	movs	r1, #1
+ 80146ec:	6978      	ldr	r0, [r7, #20]
+ 80146ee:	f000 fae3 	bl	8014cb8 <lwip_netconn_do_close_internal>
+    }
+
+    /* If the queued byte- or pbuf-count drops below the configured low-water limit,
+       let select mark this pcb as writable again. */
+    if ((conn->pcb.tcp != NULL) && (tcp_sndbuf(conn->pcb.tcp) > TCP_SNDLOWAT) &&
+ 80146f2:	697b      	ldr	r3, [r7, #20]
+ 80146f4:	685b      	ldr	r3, [r3, #4]
+ 80146f6:	2b00      	cmp	r3, #0
+ 80146f8:	d01e      	beq.n	8014738 <sent_tcp+0x94>
+ 80146fa:	697b      	ldr	r3, [r7, #20]
+ 80146fc:	685b      	ldr	r3, [r3, #4]
+ 80146fe:	f8b3 3064 	ldrh.w	r3, [r3, #100]	; 0x64
+ 8014702:	f640 3269 	movw	r2, #2921	; 0xb69
+ 8014706:	4293      	cmp	r3, r2
+ 8014708:	d916      	bls.n	8014738 <sent_tcp+0x94>
+        (tcp_sndqueuelen(conn->pcb.tcp) < TCP_SNDQUEUELOWAT)) {
+ 801470a:	697b      	ldr	r3, [r7, #20]
+ 801470c:	685b      	ldr	r3, [r3, #4]
+ 801470e:	f8b3 3066 	ldrh.w	r3, [r3, #102]	; 0x66
+    if ((conn->pcb.tcp != NULL) && (tcp_sndbuf(conn->pcb.tcp) > TCP_SNDLOWAT) &&
+ 8014712:	2b07      	cmp	r3, #7
+ 8014714:	d810      	bhi.n	8014738 <sent_tcp+0x94>
+      netconn_clear_flags(conn, NETCONN_FLAG_CHECK_WRITESPACE);
+ 8014716:	697b      	ldr	r3, [r7, #20]
+ 8014718:	7f1b      	ldrb	r3, [r3, #28]
+ 801471a:	f023 0310 	bic.w	r3, r3, #16
+ 801471e:	b2da      	uxtb	r2, r3
+ 8014720:	697b      	ldr	r3, [r7, #20]
+ 8014722:	771a      	strb	r2, [r3, #28]
+      API_EVENT(conn, NETCONN_EVT_SENDPLUS, len);
+ 8014724:	697b      	ldr	r3, [r7, #20]
+ 8014726:	6a5b      	ldr	r3, [r3, #36]	; 0x24
+ 8014728:	2b00      	cmp	r3, #0
+ 801472a:	d005      	beq.n	8014738 <sent_tcp+0x94>
+ 801472c:	697b      	ldr	r3, [r7, #20]
+ 801472e:	6a5b      	ldr	r3, [r3, #36]	; 0x24
+ 8014730:	88fa      	ldrh	r2, [r7, #6]
+ 8014732:	2102      	movs	r1, #2
+ 8014734:	6978      	ldr	r0, [r7, #20]
+ 8014736:	4798      	blx	r3
+    }
+  }
+
+  return ERR_OK;
+ 8014738:	2300      	movs	r3, #0
+}
+ 801473a:	4618      	mov	r0, r3
+ 801473c:	3718      	adds	r7, #24
+ 801473e:	46bd      	mov	sp, r7
+ 8014740:	bd80      	pop	{r7, pc}
+ 8014742:	bf00      	nop
+ 8014744:	08023624 	.word	0x08023624
+ 8014748:	0802377c 	.word	0x0802377c
+ 801474c:	08023668 	.word	0x08023668
+
+08014750 <err_tcp>:
+ *
+ * @see tcp.h (struct tcp_pcb.err) for parameters
+ */
+static void
+err_tcp(void *arg, err_t err)
+{
+ 8014750:	b580      	push	{r7, lr}
+ 8014752:	b088      	sub	sp, #32
+ 8014754:	af00      	add	r7, sp, #0
+ 8014756:	6078      	str	r0, [r7, #4]
+ 8014758:	460b      	mov	r3, r1
+ 801475a:	70fb      	strb	r3, [r7, #3]
+  struct netconn *conn;
+  enum netconn_state old_state;
+  void *mbox_msg;
+  SYS_ARCH_DECL_PROTECT(lev);
+
+  conn = (struct netconn *)arg;
+ 801475c:	687b      	ldr	r3, [r7, #4]
+ 801475e:	61fb      	str	r3, [r7, #28]
+  LWIP_ASSERT("conn != NULL", (conn != NULL));
+ 8014760:	69fb      	ldr	r3, [r7, #28]
+ 8014762:	2b00      	cmp	r3, #0
+ 8014764:	d106      	bne.n	8014774 <err_tcp+0x24>
+ 8014766:	4b5f      	ldr	r3, [pc, #380]	; (80148e4 <err_tcp+0x194>)
+ 8014768:	f44f 72dc 	mov.w	r2, #440	; 0x1b8
+ 801476c:	495e      	ldr	r1, [pc, #376]	; (80148e8 <err_tcp+0x198>)
+ 801476e:	485f      	ldr	r0, [pc, #380]	; (80148ec <err_tcp+0x19c>)
+ 8014770:	f00d f90a 	bl	8021988 <iprintf>
+
+  SYS_ARCH_PROTECT(lev);
+ 8014774:	f00c ff6e 	bl	8021654 <sys_arch_protect>
+ 8014778:	61b8      	str	r0, [r7, #24]
+
+  /* when err is called, the pcb is deallocated, so delete the reference */
+  conn->pcb.tcp = NULL;
+ 801477a:	69fb      	ldr	r3, [r7, #28]
+ 801477c:	2200      	movs	r2, #0
+ 801477e:	605a      	str	r2, [r3, #4]
+  /* store pending error */
+  conn->pending_err = err;
+ 8014780:	69fb      	ldr	r3, [r7, #28]
+ 8014782:	78fa      	ldrb	r2, [r7, #3]
+ 8014784:	721a      	strb	r2, [r3, #8]
+  /* prevent application threads from blocking on 'recvmbox'/'acceptmbox' */
+  conn->flags |= NETCONN_FLAG_MBOXCLOSED;
+ 8014786:	69fb      	ldr	r3, [r7, #28]
+ 8014788:	7f1b      	ldrb	r3, [r3, #28]
+ 801478a:	f043 0301 	orr.w	r3, r3, #1
+ 801478e:	b2da      	uxtb	r2, r3
+ 8014790:	69fb      	ldr	r3, [r7, #28]
+ 8014792:	771a      	strb	r2, [r3, #28]
+
+  /* reset conn->state now before waking up other threads */
+  old_state = conn->state;
+ 8014794:	69fb      	ldr	r3, [r7, #28]
+ 8014796:	785b      	ldrb	r3, [r3, #1]
+ 8014798:	75fb      	strb	r3, [r7, #23]
+  conn->state = NETCONN_NONE;
+ 801479a:	69fb      	ldr	r3, [r7, #28]
+ 801479c:	2200      	movs	r2, #0
+ 801479e:	705a      	strb	r2, [r3, #1]
+
+  SYS_ARCH_UNPROTECT(lev);
+ 80147a0:	69b8      	ldr	r0, [r7, #24]
+ 80147a2:	f00c ff65 	bl	8021670 <sys_arch_unprotect>
+
+  /* Notify the user layer about a connection error. Used to signal select. */
+  API_EVENT(conn, NETCONN_EVT_ERROR, 0);
+ 80147a6:	69fb      	ldr	r3, [r7, #28]
+ 80147a8:	6a5b      	ldr	r3, [r3, #36]	; 0x24
+ 80147aa:	2b00      	cmp	r3, #0
+ 80147ac:	d005      	beq.n	80147ba <err_tcp+0x6a>
+ 80147ae:	69fb      	ldr	r3, [r7, #28]
+ 80147b0:	6a5b      	ldr	r3, [r3, #36]	; 0x24
+ 80147b2:	2200      	movs	r2, #0
+ 80147b4:	2104      	movs	r1, #4
+ 80147b6:	69f8      	ldr	r0, [r7, #28]
+ 80147b8:	4798      	blx	r3
+  /* Try to release selects pending on 'read' or 'write', too.
+     They will get an error if they actually try to read or write. */
+  API_EVENT(conn, NETCONN_EVT_RCVPLUS, 0);
+ 80147ba:	69fb      	ldr	r3, [r7, #28]
+ 80147bc:	6a5b      	ldr	r3, [r3, #36]	; 0x24
+ 80147be:	2b00      	cmp	r3, #0
+ 80147c0:	d005      	beq.n	80147ce <err_tcp+0x7e>
+ 80147c2:	69fb      	ldr	r3, [r7, #28]
+ 80147c4:	6a5b      	ldr	r3, [r3, #36]	; 0x24
+ 80147c6:	2200      	movs	r2, #0
+ 80147c8:	2100      	movs	r1, #0
+ 80147ca:	69f8      	ldr	r0, [r7, #28]
+ 80147cc:	4798      	blx	r3
+  API_EVENT(conn, NETCONN_EVT_SENDPLUS, 0);
+ 80147ce:	69fb      	ldr	r3, [r7, #28]
+ 80147d0:	6a5b      	ldr	r3, [r3, #36]	; 0x24
+ 80147d2:	2b00      	cmp	r3, #0
+ 80147d4:	d005      	beq.n	80147e2 <err_tcp+0x92>
+ 80147d6:	69fb      	ldr	r3, [r7, #28]
+ 80147d8:	6a5b      	ldr	r3, [r3, #36]	; 0x24
+ 80147da:	2200      	movs	r2, #0
+ 80147dc:	2102      	movs	r1, #2
+ 80147de:	69f8      	ldr	r0, [r7, #28]
+ 80147e0:	4798      	blx	r3
+
+  mbox_msg = lwip_netconn_err_to_msg(err);
+ 80147e2:	f997 3003 	ldrsb.w	r3, [r7, #3]
+ 80147e6:	4618      	mov	r0, r3
+ 80147e8:	f7ff fd82 	bl	80142f0 <lwip_netconn_err_to_msg>
+ 80147ec:	6138      	str	r0, [r7, #16]
+  /* pass error message to recvmbox to wake up pending recv */
+  if (NETCONN_MBOX_VALID(conn, &conn->recvmbox)) {
+ 80147ee:	69fb      	ldr	r3, [r7, #28]
+ 80147f0:	3310      	adds	r3, #16
+ 80147f2:	4618      	mov	r0, r3
+ 80147f4:	f00c fe13 	bl	802141e <sys_mbox_valid>
+ 80147f8:	4603      	mov	r3, r0
+ 80147fa:	2b00      	cmp	r3, #0
+ 80147fc:	d005      	beq.n	801480a <err_tcp+0xba>
+    /* use trypost to prevent deadlock */
+    sys_mbox_trypost(&conn->recvmbox, mbox_msg);
+ 80147fe:	69fb      	ldr	r3, [r7, #28]
+ 8014800:	3310      	adds	r3, #16
+ 8014802:	6939      	ldr	r1, [r7, #16]
+ 8014804:	4618      	mov	r0, r3
+ 8014806:	f00c fd95 	bl	8021334 <sys_mbox_trypost>
+  }
+  /* pass error message to acceptmbox to wake up pending accept */
+  if (NETCONN_MBOX_VALID(conn, &conn->acceptmbox)) {
+ 801480a:	69fb      	ldr	r3, [r7, #28]
+ 801480c:	3314      	adds	r3, #20
+ 801480e:	4618      	mov	r0, r3
+ 8014810:	f00c fe05 	bl	802141e <sys_mbox_valid>
+ 8014814:	4603      	mov	r3, r0
+ 8014816:	2b00      	cmp	r3, #0
+ 8014818:	d005      	beq.n	8014826 <err_tcp+0xd6>
+    /* use trypost to preven deadlock */
+    sys_mbox_trypost(&conn->acceptmbox, mbox_msg);
+ 801481a:	69fb      	ldr	r3, [r7, #28]
+ 801481c:	3314      	adds	r3, #20
+ 801481e:	6939      	ldr	r1, [r7, #16]
+ 8014820:	4618      	mov	r0, r3
+ 8014822:	f00c fd87 	bl	8021334 <sys_mbox_trypost>
+  }
+
+  if ((old_state == NETCONN_WRITE) || (old_state == NETCONN_CLOSE) ||
+ 8014826:	7dfb      	ldrb	r3, [r7, #23]
+ 8014828:	2b01      	cmp	r3, #1
+ 801482a:	d005      	beq.n	8014838 <err_tcp+0xe8>
+ 801482c:	7dfb      	ldrb	r3, [r7, #23]
+ 801482e:	2b04      	cmp	r3, #4
+ 8014830:	d002      	beq.n	8014838 <err_tcp+0xe8>
+ 8014832:	7dfb      	ldrb	r3, [r7, #23]
+ 8014834:	2b03      	cmp	r3, #3
+ 8014836:	d143      	bne.n	80148c0 <err_tcp+0x170>
+      (old_state == NETCONN_CONNECT)) {
+    /* calling lwip_netconn_do_writemore/lwip_netconn_do_close_internal is not necessary
+       since the pcb has already been deleted! */
+    int was_nonblocking_connect = IN_NONBLOCKING_CONNECT(conn);
+ 8014838:	69fb      	ldr	r3, [r7, #28]
+ 801483a:	7f1b      	ldrb	r3, [r3, #28]
+ 801483c:	f003 0304 	and.w	r3, r3, #4
+ 8014840:	2b00      	cmp	r3, #0
+ 8014842:	bf14      	ite	ne
+ 8014844:	2301      	movne	r3, #1
+ 8014846:	2300      	moveq	r3, #0
+ 8014848:	b2db      	uxtb	r3, r3
+ 801484a:	60fb      	str	r3, [r7, #12]
+    SET_NONBLOCKING_CONNECT(conn, 0);
+ 801484c:	69fb      	ldr	r3, [r7, #28]
+ 801484e:	7f1b      	ldrb	r3, [r3, #28]
+ 8014850:	f023 0304 	bic.w	r3, r3, #4
+ 8014854:	b2da      	uxtb	r2, r3
+ 8014856:	69fb      	ldr	r3, [r7, #28]
+ 8014858:	771a      	strb	r2, [r3, #28]
+
+    if (!was_nonblocking_connect) {
+ 801485a:	68fb      	ldr	r3, [r7, #12]
+ 801485c:	2b00      	cmp	r3, #0
+ 801485e:	d13b      	bne.n	80148d8 <err_tcp+0x188>
+      sys_sem_t *op_completed_sem;
+      /* set error return code */
+      LWIP_ASSERT("conn->current_msg != NULL", conn->current_msg != NULL);
+ 8014860:	69fb      	ldr	r3, [r7, #28]
+ 8014862:	6a1b      	ldr	r3, [r3, #32]
+ 8014864:	2b00      	cmp	r3, #0
+ 8014866:	d106      	bne.n	8014876 <err_tcp+0x126>
+ 8014868:	4b1e      	ldr	r3, [pc, #120]	; (80148e4 <err_tcp+0x194>)
+ 801486a:	f44f 72f3 	mov.w	r2, #486	; 0x1e6
+ 801486e:	4920      	ldr	r1, [pc, #128]	; (80148f0 <err_tcp+0x1a0>)
+ 8014870:	481e      	ldr	r0, [pc, #120]	; (80148ec <err_tcp+0x19c>)
+ 8014872:	f00d f889 	bl	8021988 <iprintf>
+      if (old_state == NETCONN_CLOSE) {
+ 8014876:	7dfb      	ldrb	r3, [r7, #23]
+ 8014878:	2b04      	cmp	r3, #4
+ 801487a:	d104      	bne.n	8014886 <err_tcp+0x136>
+        /* let close succeed: the connection is closed after all... */
+        conn->current_msg->err = ERR_OK;
+ 801487c:	69fb      	ldr	r3, [r7, #28]
+ 801487e:	6a1b      	ldr	r3, [r3, #32]
+ 8014880:	2200      	movs	r2, #0
+ 8014882:	711a      	strb	r2, [r3, #4]
+ 8014884:	e003      	b.n	801488e <err_tcp+0x13e>
+      } else {
+        /* Write and connect fail */
+        conn->current_msg->err = err;
+ 8014886:	69fb      	ldr	r3, [r7, #28]
+ 8014888:	6a1b      	ldr	r3, [r3, #32]
+ 801488a:	78fa      	ldrb	r2, [r7, #3]
+ 801488c:	711a      	strb	r2, [r3, #4]
+      }
+      op_completed_sem = LWIP_API_MSG_SEM(conn->current_msg);
+ 801488e:	69fb      	ldr	r3, [r7, #28]
+ 8014890:	6a1b      	ldr	r3, [r3, #32]
+ 8014892:	681b      	ldr	r3, [r3, #0]
+ 8014894:	330c      	adds	r3, #12
+ 8014896:	60bb      	str	r3, [r7, #8]
+      LWIP_ASSERT("inavlid op_completed_sem", sys_sem_valid(op_completed_sem));
+ 8014898:	68b8      	ldr	r0, [r7, #8]
+ 801489a:	f00c fe51 	bl	8021540 <sys_sem_valid>
+ 801489e:	4603      	mov	r3, r0
+ 80148a0:	2b00      	cmp	r3, #0
+ 80148a2:	d106      	bne.n	80148b2 <err_tcp+0x162>
+ 80148a4:	4b0f      	ldr	r3, [pc, #60]	; (80148e4 <err_tcp+0x194>)
+ 80148a6:	f240 12ef 	movw	r2, #495	; 0x1ef
+ 80148aa:	4912      	ldr	r1, [pc, #72]	; (80148f4 <err_tcp+0x1a4>)
+ 80148ac:	480f      	ldr	r0, [pc, #60]	; (80148ec <err_tcp+0x19c>)
+ 80148ae:	f00d f86b 	bl	8021988 <iprintf>
+      conn->current_msg = NULL;
+ 80148b2:	69fb      	ldr	r3, [r7, #28]
+ 80148b4:	2200      	movs	r2, #0
+ 80148b6:	621a      	str	r2, [r3, #32]
+      /* wake up the waiting task */
+      sys_sem_signal(op_completed_sem);
+ 80148b8:	68b8      	ldr	r0, [r7, #8]
+ 80148ba:	f00c fe27 	bl	802150c <sys_sem_signal>
+      (old_state == NETCONN_CONNECT)) {
+ 80148be:	e00b      	b.n	80148d8 <err_tcp+0x188>
+    } else {
+      /* @todo: test what happens for error on nonblocking connect */
+    }
+  } else {
+    LWIP_ASSERT("conn->current_msg == NULL", conn->current_msg == NULL);
+ 80148c0:	69fb      	ldr	r3, [r7, #28]
+ 80148c2:	6a1b      	ldr	r3, [r3, #32]
+ 80148c4:	2b00      	cmp	r3, #0
+ 80148c6:	d008      	beq.n	80148da <err_tcp+0x18a>
+ 80148c8:	4b06      	ldr	r3, [pc, #24]	; (80148e4 <err_tcp+0x194>)
+ 80148ca:	f240 12f7 	movw	r2, #503	; 0x1f7
+ 80148ce:	490a      	ldr	r1, [pc, #40]	; (80148f8 <err_tcp+0x1a8>)
+ 80148d0:	4806      	ldr	r0, [pc, #24]	; (80148ec <err_tcp+0x19c>)
+ 80148d2:	f00d f859 	bl	8021988 <iprintf>
+  }
+}
+ 80148d6:	e000      	b.n	80148da <err_tcp+0x18a>
+      (old_state == NETCONN_CONNECT)) {
+ 80148d8:	bf00      	nop
+}
+ 80148da:	bf00      	nop
+ 80148dc:	3720      	adds	r7, #32
+ 80148de:	46bd      	mov	sp, r7
+ 80148e0:	bd80      	pop	{r7, pc}
+ 80148e2:	bf00      	nop
+ 80148e4:	08023624 	.word	0x08023624
+ 80148e8:	0802377c 	.word	0x0802377c
+ 80148ec:	08023668 	.word	0x08023668
+ 80148f0:	0802378c 	.word	0x0802378c
+ 80148f4:	080237a8 	.word	0x080237a8
+ 80148f8:	080237c4 	.word	0x080237c4
+
+080148fc <setup_tcp>:
+ *
+ * @param conn the TCP netconn to setup
+ */
+static void
+setup_tcp(struct netconn *conn)
+{
+ 80148fc:	b580      	push	{r7, lr}
+ 80148fe:	b084      	sub	sp, #16
+ 8014900:	af00      	add	r7, sp, #0
+ 8014902:	6078      	str	r0, [r7, #4]
+  struct tcp_pcb *pcb;
+
+  pcb = conn->pcb.tcp;
+ 8014904:	687b      	ldr	r3, [r7, #4]
+ 8014906:	685b      	ldr	r3, [r3, #4]
+ 8014908:	60fb      	str	r3, [r7, #12]
+  tcp_arg(pcb, conn);
+ 801490a:	6879      	ldr	r1, [r7, #4]
+ 801490c:	68f8      	ldr	r0, [r7, #12]
+ 801490e:	f004 ffc3 	bl	8019898 <tcp_arg>
+  tcp_recv(pcb, recv_tcp);
+ 8014912:	490a      	ldr	r1, [pc, #40]	; (801493c <setup_tcp+0x40>)
+ 8014914:	68f8      	ldr	r0, [r7, #12]
+ 8014916:	f004 ffd1 	bl	80198bc <tcp_recv>
+  tcp_sent(pcb, sent_tcp);
+ 801491a:	4909      	ldr	r1, [pc, #36]	; (8014940 <setup_tcp+0x44>)
+ 801491c:	68f8      	ldr	r0, [r7, #12]
+ 801491e:	f004 ffef 	bl	8019900 <tcp_sent>
+  tcp_poll(pcb, poll_tcp, NETCONN_TCP_POLL_INTERVAL);
+ 8014922:	2202      	movs	r2, #2
+ 8014924:	4907      	ldr	r1, [pc, #28]	; (8014944 <setup_tcp+0x48>)
+ 8014926:	68f8      	ldr	r0, [r7, #12]
+ 8014928:	f005 f846 	bl	80199b8 <tcp_poll>
+  tcp_err(pcb, err_tcp);
+ 801492c:	4906      	ldr	r1, [pc, #24]	; (8014948 <setup_tcp+0x4c>)
+ 801492e:	68f8      	ldr	r0, [r7, #12]
+ 8014930:	f005 f808 	bl	8019944 <tcp_err>
+}
+ 8014934:	bf00      	nop
+ 8014936:	3710      	adds	r7, #16
+ 8014938:	46bd      	mov	sp, r7
+ 801493a:	bd80      	pop	{r7, pc}
+ 801493c:	080144cd 	.word	0x080144cd
+ 8014940:	080146a5 	.word	0x080146a5
+ 8014944:	080145d9 	.word	0x080145d9
+ 8014948:	08014751 	.word	0x08014751
+
+0801494c <pcb_new>:
+ *
+ * @param msg the api_msg describing the connection type
+ */
+static void
+pcb_new(struct api_msg *msg)
+{
+ 801494c:	b590      	push	{r4, r7, lr}
+ 801494e:	b085      	sub	sp, #20
+ 8014950:	af00      	add	r7, sp, #0
+ 8014952:	6078      	str	r0, [r7, #4]
+  enum lwip_ip_addr_type iptype = IPADDR_TYPE_V4;
+ 8014954:	2300      	movs	r3, #0
+ 8014956:	73fb      	strb	r3, [r7, #15]
+
+  LWIP_ASSERT("pcb_new: pcb already allocated", msg->conn->pcb.tcp == NULL);
+ 8014958:	687b      	ldr	r3, [r7, #4]
+ 801495a:	681b      	ldr	r3, [r3, #0]
+ 801495c:	685b      	ldr	r3, [r3, #4]
+ 801495e:	2b00      	cmp	r3, #0
+ 8014960:	d006      	beq.n	8014970 <pcb_new+0x24>
+ 8014962:	4b2b      	ldr	r3, [pc, #172]	; (8014a10 <pcb_new+0xc4>)
+ 8014964:	f240 2265 	movw	r2, #613	; 0x265
+ 8014968:	492a      	ldr	r1, [pc, #168]	; (8014a14 <pcb_new+0xc8>)
+ 801496a:	482b      	ldr	r0, [pc, #172]	; (8014a18 <pcb_new+0xcc>)
+ 801496c:	f00d f80c 	bl	8021988 <iprintf>
+    iptype = IPADDR_TYPE_ANY;
+  }
+#endif
+
+  /* Allocate a PCB for this connection */
+  switch (NETCONNTYPE_GROUP(msg->conn->type)) {
+ 8014970:	687b      	ldr	r3, [r7, #4]
+ 8014972:	681b      	ldr	r3, [r3, #0]
+ 8014974:	781b      	ldrb	r3, [r3, #0]
+ 8014976:	f003 03f0 	and.w	r3, r3, #240	; 0xf0
+ 801497a:	2b10      	cmp	r3, #16
+ 801497c:	d022      	beq.n	80149c4 <pcb_new+0x78>
+ 801497e:	2b20      	cmp	r3, #32
+ 8014980:	d133      	bne.n	80149ea <pcb_new+0x9e>
+      }
+      break;
+#endif /* LWIP_RAW */
+#if LWIP_UDP
+    case NETCONN_UDP:
+      msg->conn->pcb.udp = udp_new_ip_type(iptype);
+ 8014982:	687b      	ldr	r3, [r7, #4]
+ 8014984:	681c      	ldr	r4, [r3, #0]
+ 8014986:	7bfb      	ldrb	r3, [r7, #15]
+ 8014988:	4618      	mov	r0, r3
+ 801498a:	f00a f944 	bl	801ec16 <udp_new_ip_type>
+ 801498e:	4603      	mov	r3, r0
+ 8014990:	6063      	str	r3, [r4, #4]
+      if (msg->conn->pcb.udp != NULL) {
+ 8014992:	687b      	ldr	r3, [r7, #4]
+ 8014994:	681b      	ldr	r3, [r3, #0]
+ 8014996:	685b      	ldr	r3, [r3, #4]
+ 8014998:	2b00      	cmp	r3, #0
+ 801499a:	d02a      	beq.n	80149f2 <pcb_new+0xa6>
+#if LWIP_UDPLITE
+        if (NETCONNTYPE_ISUDPLITE(msg->conn->type)) {
+          udp_setflags(msg->conn->pcb.udp, UDP_FLAGS_UDPLITE);
+        }
+#endif /* LWIP_UDPLITE */
+        if (NETCONNTYPE_ISUDPNOCHKSUM(msg->conn->type)) {
+ 801499c:	687b      	ldr	r3, [r7, #4]
+ 801499e:	681b      	ldr	r3, [r3, #0]
+ 80149a0:	781b      	ldrb	r3, [r3, #0]
+ 80149a2:	2b22      	cmp	r3, #34	; 0x22
+ 80149a4:	d104      	bne.n	80149b0 <pcb_new+0x64>
+          udp_setflags(msg->conn->pcb.udp, UDP_FLAGS_NOCHKSUM);
+ 80149a6:	687b      	ldr	r3, [r7, #4]
+ 80149a8:	681b      	ldr	r3, [r3, #0]
+ 80149aa:	685b      	ldr	r3, [r3, #4]
+ 80149ac:	2201      	movs	r2, #1
+ 80149ae:	741a      	strb	r2, [r3, #16]
+        }
+        udp_recv(msg->conn->pcb.udp, recv_udp, msg->conn);
+ 80149b0:	687b      	ldr	r3, [r7, #4]
+ 80149b2:	681b      	ldr	r3, [r3, #0]
+ 80149b4:	6858      	ldr	r0, [r3, #4]
+ 80149b6:	687b      	ldr	r3, [r7, #4]
+ 80149b8:	681b      	ldr	r3, [r3, #0]
+ 80149ba:	461a      	mov	r2, r3
+ 80149bc:	4917      	ldr	r1, [pc, #92]	; (8014a1c <pcb_new+0xd0>)
+ 80149be:	f00a f8b1 	bl	801eb24 <udp_recv>
+      }
+      break;
+ 80149c2:	e016      	b.n	80149f2 <pcb_new+0xa6>
+#endif /* LWIP_UDP */
+#if LWIP_TCP
+    case NETCONN_TCP:
+      msg->conn->pcb.tcp = tcp_new_ip_type(iptype);
+ 80149c4:	687b      	ldr	r3, [r7, #4]
+ 80149c6:	681c      	ldr	r4, [r3, #0]
+ 80149c8:	7bfb      	ldrb	r3, [r7, #15]
+ 80149ca:	4618      	mov	r0, r3
+ 80149cc:	f004 ff56 	bl	801987c <tcp_new_ip_type>
+ 80149d0:	4603      	mov	r3, r0
+ 80149d2:	6063      	str	r3, [r4, #4]
+      if (msg->conn->pcb.tcp != NULL) {
+ 80149d4:	687b      	ldr	r3, [r7, #4]
+ 80149d6:	681b      	ldr	r3, [r3, #0]
+ 80149d8:	685b      	ldr	r3, [r3, #4]
+ 80149da:	2b00      	cmp	r3, #0
+ 80149dc:	d00b      	beq.n	80149f6 <pcb_new+0xaa>
+        setup_tcp(msg->conn);
+ 80149de:	687b      	ldr	r3, [r7, #4]
+ 80149e0:	681b      	ldr	r3, [r3, #0]
+ 80149e2:	4618      	mov	r0, r3
+ 80149e4:	f7ff ff8a 	bl	80148fc <setup_tcp>
+      }
+      break;
+ 80149e8:	e005      	b.n	80149f6 <pcb_new+0xaa>
+#endif /* LWIP_TCP */
+    default:
+      /* Unsupported netconn type, e.g. protocol disabled */
+      msg->err = ERR_VAL;
+ 80149ea:	687b      	ldr	r3, [r7, #4]
+ 80149ec:	22fa      	movs	r2, #250	; 0xfa
+ 80149ee:	711a      	strb	r2, [r3, #4]
+      return;
+ 80149f0:	e00a      	b.n	8014a08 <pcb_new+0xbc>
+      break;
+ 80149f2:	bf00      	nop
+ 80149f4:	e000      	b.n	80149f8 <pcb_new+0xac>
+      break;
+ 80149f6:	bf00      	nop
+  }
+  if (msg->conn->pcb.ip == NULL) {
+ 80149f8:	687b      	ldr	r3, [r7, #4]
+ 80149fa:	681b      	ldr	r3, [r3, #0]
+ 80149fc:	685b      	ldr	r3, [r3, #4]
+ 80149fe:	2b00      	cmp	r3, #0
+ 8014a00:	d102      	bne.n	8014a08 <pcb_new+0xbc>
+    msg->err = ERR_MEM;
+ 8014a02:	687b      	ldr	r3, [r7, #4]
+ 8014a04:	22ff      	movs	r2, #255	; 0xff
+ 8014a06:	711a      	strb	r2, [r3, #4]
+  }
+}
+ 8014a08:	3714      	adds	r7, #20
+ 8014a0a:	46bd      	mov	sp, r7
+ 8014a0c:	bd90      	pop	{r4, r7, pc}
+ 8014a0e:	bf00      	nop
+ 8014a10:	08023624 	.word	0x08023624
+ 8014a14:	08023808 	.word	0x08023808
+ 8014a18:	08023668 	.word	0x08023668
+ 8014a1c:	080143d1 	.word	0x080143d1
+
+08014a20 <lwip_netconn_do_newconn>:
+ *
+ * @param m the api_msg describing the connection type
+ */
+void
+lwip_netconn_do_newconn(void *m)
+{
+ 8014a20:	b580      	push	{r7, lr}
+ 8014a22:	b084      	sub	sp, #16
+ 8014a24:	af00      	add	r7, sp, #0
+ 8014a26:	6078      	str	r0, [r7, #4]
+  struct api_msg *msg = (struct api_msg *)m;
+ 8014a28:	687b      	ldr	r3, [r7, #4]
+ 8014a2a:	60fb      	str	r3, [r7, #12]
+
+  msg->err = ERR_OK;
+ 8014a2c:	68fb      	ldr	r3, [r7, #12]
+ 8014a2e:	2200      	movs	r2, #0
+ 8014a30:	711a      	strb	r2, [r3, #4]
+  if (msg->conn->pcb.tcp == NULL) {
+ 8014a32:	68fb      	ldr	r3, [r7, #12]
+ 8014a34:	681b      	ldr	r3, [r3, #0]
+ 8014a36:	685b      	ldr	r3, [r3, #4]
+ 8014a38:	2b00      	cmp	r3, #0
+ 8014a3a:	d102      	bne.n	8014a42 <lwip_netconn_do_newconn+0x22>
+    pcb_new(msg);
+ 8014a3c:	68f8      	ldr	r0, [r7, #12]
+ 8014a3e:	f7ff ff85 	bl	801494c <pcb_new>
+  /* Else? This "new" connection already has a PCB allocated. */
+  /* Is this an error condition? Should it be deleted? */
+  /* We currently just are happy and return. */
+
+  TCPIP_APIMSG_ACK(msg);
+}
+ 8014a42:	bf00      	nop
+ 8014a44:	3710      	adds	r7, #16
+ 8014a46:	46bd      	mov	sp, r7
+ 8014a48:	bd80      	pop	{r7, pc}
+	...
+
+08014a4c <netconn_alloc>:
+ * @return a newly allocated struct netconn or
+ *         NULL on memory error
+ */
+struct netconn *
+netconn_alloc(enum netconn_type t, netconn_callback callback)
+{
+ 8014a4c:	b580      	push	{r7, lr}
+ 8014a4e:	b086      	sub	sp, #24
+ 8014a50:	af00      	add	r7, sp, #0
+ 8014a52:	4603      	mov	r3, r0
+ 8014a54:	6039      	str	r1, [r7, #0]
+ 8014a56:	71fb      	strb	r3, [r7, #7]
+  struct netconn *conn;
+  int size;
+  u8_t init_flags = 0;
+ 8014a58:	2300      	movs	r3, #0
+ 8014a5a:	74fb      	strb	r3, [r7, #19]
+
+  conn = (struct netconn *)memp_malloc(MEMP_NETCONN);
+ 8014a5c:	2007      	movs	r0, #7
+ 8014a5e:	f002 f837 	bl	8016ad0 <memp_malloc>
+ 8014a62:	60f8      	str	r0, [r7, #12]
+  if (conn == NULL) {
+ 8014a64:	68fb      	ldr	r3, [r7, #12]
+ 8014a66:	2b00      	cmp	r3, #0
+ 8014a68:	d101      	bne.n	8014a6e <netconn_alloc+0x22>
+    return NULL;
+ 8014a6a:	2300      	movs	r3, #0
+ 8014a6c:	e052      	b.n	8014b14 <netconn_alloc+0xc8>
+  }
+
+  conn->pending_err = ERR_OK;
+ 8014a6e:	68fb      	ldr	r3, [r7, #12]
+ 8014a70:	2200      	movs	r2, #0
+ 8014a72:	721a      	strb	r2, [r3, #8]
+  conn->type = t;
+ 8014a74:	68fb      	ldr	r3, [r7, #12]
+ 8014a76:	79fa      	ldrb	r2, [r7, #7]
+ 8014a78:	701a      	strb	r2, [r3, #0]
+  conn->pcb.tcp = NULL;
+ 8014a7a:	68fb      	ldr	r3, [r7, #12]
+ 8014a7c:	2200      	movs	r2, #0
+ 8014a7e:	605a      	str	r2, [r3, #4]
+
+  /* If all sizes are the same, every compiler should optimize this switch to nothing */
+  switch (NETCONNTYPE_GROUP(t)) {
+ 8014a80:	79fb      	ldrb	r3, [r7, #7]
+ 8014a82:	f003 03f0 	and.w	r3, r3, #240	; 0xf0
+ 8014a86:	2b10      	cmp	r3, #16
+ 8014a88:	d004      	beq.n	8014a94 <netconn_alloc+0x48>
+ 8014a8a:	2b20      	cmp	r3, #32
+ 8014a8c:	d105      	bne.n	8014a9a <netconn_alloc+0x4e>
+      size = DEFAULT_RAW_RECVMBOX_SIZE;
+      break;
+#endif /* LWIP_RAW */
+#if LWIP_UDP
+    case NETCONN_UDP:
+      size = DEFAULT_UDP_RECVMBOX_SIZE;
+ 8014a8e:	2306      	movs	r3, #6
+ 8014a90:	617b      	str	r3, [r7, #20]
+#if LWIP_NETBUF_RECVINFO
+      init_flags |= NETCONN_FLAG_PKTINFO;
+#endif /* LWIP_NETBUF_RECVINFO */
+      break;
+ 8014a92:	e00a      	b.n	8014aaa <netconn_alloc+0x5e>
+#endif /* LWIP_UDP */
+#if LWIP_TCP
+    case NETCONN_TCP:
+      size = DEFAULT_TCP_RECVMBOX_SIZE;
+ 8014a94:	2306      	movs	r3, #6
+ 8014a96:	617b      	str	r3, [r7, #20]
+      break;
+ 8014a98:	e007      	b.n	8014aaa <netconn_alloc+0x5e>
+#endif /* LWIP_TCP */
+    default:
+      LWIP_ASSERT("netconn_alloc: undefined netconn_type", 0);
+ 8014a9a:	4b20      	ldr	r3, [pc, #128]	; (8014b1c <netconn_alloc+0xd0>)
+ 8014a9c:	f240 22e5 	movw	r2, #741	; 0x2e5
+ 8014aa0:	491f      	ldr	r1, [pc, #124]	; (8014b20 <netconn_alloc+0xd4>)
+ 8014aa2:	4820      	ldr	r0, [pc, #128]	; (8014b24 <netconn_alloc+0xd8>)
+ 8014aa4:	f00c ff70 	bl	8021988 <iprintf>
+      goto free_and_return;
+ 8014aa8:	e02f      	b.n	8014b0a <netconn_alloc+0xbe>
+  }
+
+  if (sys_mbox_new(&conn->recvmbox, size) != ERR_OK) {
+ 8014aaa:	68fb      	ldr	r3, [r7, #12]
+ 8014aac:	3310      	adds	r3, #16
+ 8014aae:	6979      	ldr	r1, [r7, #20]
+ 8014ab0:	4618      	mov	r0, r3
+ 8014ab2:	f00c fc0b 	bl	80212cc <sys_mbox_new>
+ 8014ab6:	4603      	mov	r3, r0
+ 8014ab8:	2b00      	cmp	r3, #0
+ 8014aba:	d125      	bne.n	8014b08 <netconn_alloc+0xbc>
+    goto free_and_return;
+  }
+#if !LWIP_NETCONN_SEM_PER_THREAD
+  if (sys_sem_new(&conn->op_completed, 0) != ERR_OK) {
+ 8014abc:	68fb      	ldr	r3, [r7, #12]
+ 8014abe:	330c      	adds	r3, #12
+ 8014ac0:	2100      	movs	r1, #0
+ 8014ac2:	4618      	mov	r0, r3
+ 8014ac4:	f00c fcc9 	bl	802145a <sys_sem_new>
+ 8014ac8:	4603      	mov	r3, r0
+ 8014aca:	2b00      	cmp	r3, #0
+ 8014acc:	d005      	beq.n	8014ada <netconn_alloc+0x8e>
+    sys_mbox_free(&conn->recvmbox);
+ 8014ace:	68fb      	ldr	r3, [r7, #12]
+ 8014ad0:	3310      	adds	r3, #16
+ 8014ad2:	4618      	mov	r0, r3
+ 8014ad4:	f00c fc1c 	bl	8021310 <sys_mbox_free>
+    goto free_and_return;
+ 8014ad8:	e017      	b.n	8014b0a <netconn_alloc+0xbe>
+  }
+#endif
+
+#if LWIP_TCP
+  sys_mbox_set_invalid(&conn->acceptmbox);
+ 8014ada:	68fb      	ldr	r3, [r7, #12]
+ 8014adc:	3314      	adds	r3, #20
+ 8014ade:	4618      	mov	r0, r3
+ 8014ae0:	f00c fcae 	bl	8021440 <sys_mbox_set_invalid>
+#endif
+  conn->state        = NETCONN_NONE;
+ 8014ae4:	68fb      	ldr	r3, [r7, #12]
+ 8014ae6:	2200      	movs	r2, #0
+ 8014ae8:	705a      	strb	r2, [r3, #1]
+#if LWIP_SOCKET
+  /* initialize socket to -1 since 0 is a valid socket */
+  conn->socket       = -1;
+ 8014aea:	68fb      	ldr	r3, [r7, #12]
+ 8014aec:	f04f 32ff 	mov.w	r2, #4294967295
+ 8014af0:	619a      	str	r2, [r3, #24]
+#endif /* LWIP_SOCKET */
+  conn->callback     = callback;
+ 8014af2:	68fb      	ldr	r3, [r7, #12]
+ 8014af4:	683a      	ldr	r2, [r7, #0]
+ 8014af6:	625a      	str	r2, [r3, #36]	; 0x24
+#if LWIP_TCP
+  conn->current_msg  = NULL;
+ 8014af8:	68fb      	ldr	r3, [r7, #12]
+ 8014afa:	2200      	movs	r2, #0
+ 8014afc:	621a      	str	r2, [r3, #32]
+  conn->recv_avail   = 0;
+#endif /* LWIP_SO_RCVBUF */
+#if LWIP_SO_LINGER
+  conn->linger = -1;
+#endif /* LWIP_SO_LINGER */
+  conn->flags = init_flags;
+ 8014afe:	68fb      	ldr	r3, [r7, #12]
+ 8014b00:	7cfa      	ldrb	r2, [r7, #19]
+ 8014b02:	771a      	strb	r2, [r3, #28]
+  return conn;
+ 8014b04:	68fb      	ldr	r3, [r7, #12]
+ 8014b06:	e005      	b.n	8014b14 <netconn_alloc+0xc8>
+    goto free_and_return;
+ 8014b08:	bf00      	nop
+free_and_return:
+  memp_free(MEMP_NETCONN, conn);
+ 8014b0a:	68f9      	ldr	r1, [r7, #12]
+ 8014b0c:	2007      	movs	r0, #7
+ 8014b0e:	f002 f855 	bl	8016bbc <memp_free>
+  return NULL;
+ 8014b12:	2300      	movs	r3, #0
+}
+ 8014b14:	4618      	mov	r0, r3
+ 8014b16:	3718      	adds	r7, #24
+ 8014b18:	46bd      	mov	sp, r7
+ 8014b1a:	bd80      	pop	{r7, pc}
+ 8014b1c:	08023624 	.word	0x08023624
+ 8014b20:	08023828 	.word	0x08023828
+ 8014b24:	08023668 	.word	0x08023668
+
+08014b28 <netconn_free>:
+ *
+ * @param conn the netconn to free
+ */
+void
+netconn_free(struct netconn *conn)
+{
+ 8014b28:	b580      	push	{r7, lr}
+ 8014b2a:	b082      	sub	sp, #8
+ 8014b2c:	af00      	add	r7, sp, #0
+ 8014b2e:	6078      	str	r0, [r7, #4]
+  LWIP_ASSERT("PCB must be deallocated outside this function", conn->pcb.tcp == NULL);
+ 8014b30:	687b      	ldr	r3, [r7, #4]
+ 8014b32:	685b      	ldr	r3, [r3, #4]
+ 8014b34:	2b00      	cmp	r3, #0
+ 8014b36:	d006      	beq.n	8014b46 <netconn_free+0x1e>
+ 8014b38:	4b1b      	ldr	r3, [pc, #108]	; (8014ba8 <netconn_free+0x80>)
+ 8014b3a:	f44f 7247 	mov.w	r2, #796	; 0x31c
+ 8014b3e:	491b      	ldr	r1, [pc, #108]	; (8014bac <netconn_free+0x84>)
+ 8014b40:	481b      	ldr	r0, [pc, #108]	; (8014bb0 <netconn_free+0x88>)
+ 8014b42:	f00c ff21 	bl	8021988 <iprintf>
+#if LWIP_NETCONN_FULLDUPLEX
+  /* in fullduplex, netconn is drained here */
+  netconn_drain(conn);
+#endif /* LWIP_NETCONN_FULLDUPLEX */
+
+  LWIP_ASSERT("recvmbox must be deallocated before calling this function",
+ 8014b46:	687b      	ldr	r3, [r7, #4]
+ 8014b48:	3310      	adds	r3, #16
+ 8014b4a:	4618      	mov	r0, r3
+ 8014b4c:	f00c fc67 	bl	802141e <sys_mbox_valid>
+ 8014b50:	4603      	mov	r3, r0
+ 8014b52:	2b00      	cmp	r3, #0
+ 8014b54:	d006      	beq.n	8014b64 <netconn_free+0x3c>
+ 8014b56:	4b14      	ldr	r3, [pc, #80]	; (8014ba8 <netconn_free+0x80>)
+ 8014b58:	f240 3223 	movw	r2, #803	; 0x323
+ 8014b5c:	4915      	ldr	r1, [pc, #84]	; (8014bb4 <netconn_free+0x8c>)
+ 8014b5e:	4814      	ldr	r0, [pc, #80]	; (8014bb0 <netconn_free+0x88>)
+ 8014b60:	f00c ff12 	bl	8021988 <iprintf>
+              !sys_mbox_valid(&conn->recvmbox));
+#if LWIP_TCP
+  LWIP_ASSERT("acceptmbox must be deallocated before calling this function",
+ 8014b64:	687b      	ldr	r3, [r7, #4]
+ 8014b66:	3314      	adds	r3, #20
+ 8014b68:	4618      	mov	r0, r3
+ 8014b6a:	f00c fc58 	bl	802141e <sys_mbox_valid>
+ 8014b6e:	4603      	mov	r3, r0
+ 8014b70:	2b00      	cmp	r3, #0
+ 8014b72:	d006      	beq.n	8014b82 <netconn_free+0x5a>
+ 8014b74:	4b0c      	ldr	r3, [pc, #48]	; (8014ba8 <netconn_free+0x80>)
+ 8014b76:	f240 3226 	movw	r2, #806	; 0x326
+ 8014b7a:	490f      	ldr	r1, [pc, #60]	; (8014bb8 <netconn_free+0x90>)
+ 8014b7c:	480c      	ldr	r0, [pc, #48]	; (8014bb0 <netconn_free+0x88>)
+ 8014b7e:	f00c ff03 	bl	8021988 <iprintf>
+              !sys_mbox_valid(&conn->acceptmbox));
+#endif /* LWIP_TCP */
+
+#if !LWIP_NETCONN_SEM_PER_THREAD
+  sys_sem_free(&conn->op_completed);
+ 8014b82:	687b      	ldr	r3, [r7, #4]
+ 8014b84:	330c      	adds	r3, #12
+ 8014b86:	4618      	mov	r0, r3
+ 8014b88:	f00c fccd 	bl	8021526 <sys_sem_free>
+  sys_sem_set_invalid(&conn->op_completed);
+ 8014b8c:	687b      	ldr	r3, [r7, #4]
+ 8014b8e:	330c      	adds	r3, #12
+ 8014b90:	4618      	mov	r0, r3
+ 8014b92:	f00c fce6 	bl	8021562 <sys_sem_set_invalid>
+#endif
+
+  memp_free(MEMP_NETCONN, conn);
+ 8014b96:	6879      	ldr	r1, [r7, #4]
+ 8014b98:	2007      	movs	r0, #7
+ 8014b9a:	f002 f80f 	bl	8016bbc <memp_free>
+}
+ 8014b9e:	bf00      	nop
+ 8014ba0:	3708      	adds	r7, #8
+ 8014ba2:	46bd      	mov	sp, r7
+ 8014ba4:	bd80      	pop	{r7, pc}
+ 8014ba6:	bf00      	nop
+ 8014ba8:	08023624 	.word	0x08023624
+ 8014bac:	08023850 	.word	0x08023850
+ 8014bb0:	08023668 	.word	0x08023668
+ 8014bb4:	08023880 	.word	0x08023880
+ 8014bb8:	080238bc 	.word	0x080238bc
+
+08014bbc <netconn_drain>:
+ * @bytes_drained bytes drained from recvmbox
+ * @accepts_drained pending connections drained from acceptmbox
+ */
+static void
+netconn_drain(struct netconn *conn)
+{
+ 8014bbc:	b580      	push	{r7, lr}
+ 8014bbe:	b086      	sub	sp, #24
+ 8014bc0:	af00      	add	r7, sp, #0
+ 8014bc2:	6078      	str	r0, [r7, #4]
+#if LWIP_NETCONN_FULLDUPLEX
+  LWIP_ASSERT("netconn marked closed", conn->flags & NETCONN_FLAG_MBOXINVALID);
+#endif /* LWIP_NETCONN_FULLDUPLEX */
+
+  /* Delete and drain the recvmbox. */
+  if (sys_mbox_valid(&conn->recvmbox)) {
+ 8014bc4:	687b      	ldr	r3, [r7, #4]
+ 8014bc6:	3310      	adds	r3, #16
+ 8014bc8:	4618      	mov	r0, r3
+ 8014bca:	f00c fc28 	bl	802141e <sys_mbox_valid>
+ 8014bce:	4603      	mov	r3, r0
+ 8014bd0:	2b00      	cmp	r3, #0
+ 8014bd2:	d02f      	beq.n	8014c34 <netconn_drain+0x78>
+    while (sys_mbox_tryfetch(&conn->recvmbox, &mem) != SYS_MBOX_EMPTY) {
+ 8014bd4:	e018      	b.n	8014c08 <netconn_drain+0x4c>
+#if LWIP_NETCONN_FULLDUPLEX
+      if (!lwip_netconn_is_deallocated_msg(mem))
+#endif /* LWIP_NETCONN_FULLDUPLEX */
+      {
+#if LWIP_TCP
+        if (NETCONNTYPE_GROUP(conn->type) == NETCONN_TCP) {
+ 8014bd6:	687b      	ldr	r3, [r7, #4]
+ 8014bd8:	781b      	ldrb	r3, [r3, #0]
+ 8014bda:	f003 03f0 	and.w	r3, r3, #240	; 0xf0
+ 8014bde:	2b10      	cmp	r3, #16
+ 8014be0:	d10e      	bne.n	8014c00 <netconn_drain+0x44>
+          err_t err;
+          if (!lwip_netconn_is_err_msg(mem, &err)) {
+ 8014be2:	693b      	ldr	r3, [r7, #16]
+ 8014be4:	f107 020f 	add.w	r2, r7, #15
+ 8014be8:	4611      	mov	r1, r2
+ 8014bea:	4618      	mov	r0, r3
+ 8014bec:	f7ff fbb6 	bl	801435c <lwip_netconn_is_err_msg>
+ 8014bf0:	4603      	mov	r3, r0
+ 8014bf2:	2b00      	cmp	r3, #0
+ 8014bf4:	d108      	bne.n	8014c08 <netconn_drain+0x4c>
+            pbuf_free((struct pbuf *)mem);
+ 8014bf6:	693b      	ldr	r3, [r7, #16]
+ 8014bf8:	4618      	mov	r0, r3
+ 8014bfa:	f002 ff7d 	bl	8017af8 <pbuf_free>
+ 8014bfe:	e003      	b.n	8014c08 <netconn_drain+0x4c>
+          }
+        } else
+#endif /* LWIP_TCP */
+        {
+          netbuf_delete((struct netbuf *)mem);
+ 8014c00:	693b      	ldr	r3, [r7, #16]
+ 8014c02:	4618      	mov	r0, r3
+ 8014c04:	f000 ff4a 	bl	8015a9c <netbuf_delete>
+    while (sys_mbox_tryfetch(&conn->recvmbox, &mem) != SYS_MBOX_EMPTY) {
+ 8014c08:	687b      	ldr	r3, [r7, #4]
+ 8014c0a:	3310      	adds	r3, #16
+ 8014c0c:	f107 0210 	add.w	r2, r7, #16
+ 8014c10:	4611      	mov	r1, r2
+ 8014c12:	4618      	mov	r0, r3
+ 8014c14:	f00c fbe7 	bl	80213e6 <sys_arch_mbox_tryfetch>
+ 8014c18:	4603      	mov	r3, r0
+ 8014c1a:	f1b3 3fff 	cmp.w	r3, #4294967295
+ 8014c1e:	d1da      	bne.n	8014bd6 <netconn_drain+0x1a>
+        }
+      }
+    }
+    sys_mbox_free(&conn->recvmbox);
+ 8014c20:	687b      	ldr	r3, [r7, #4]
+ 8014c22:	3310      	adds	r3, #16
+ 8014c24:	4618      	mov	r0, r3
+ 8014c26:	f00c fb73 	bl	8021310 <sys_mbox_free>
+    sys_mbox_set_invalid(&conn->recvmbox);
+ 8014c2a:	687b      	ldr	r3, [r7, #4]
+ 8014c2c:	3310      	adds	r3, #16
+ 8014c2e:	4618      	mov	r0, r3
+ 8014c30:	f00c fc06 	bl	8021440 <sys_mbox_set_invalid>
+  }
+
+  /* Delete and drain the acceptmbox. */
+#if LWIP_TCP
+  if (sys_mbox_valid(&conn->acceptmbox)) {
+ 8014c34:	687b      	ldr	r3, [r7, #4]
+ 8014c36:	3314      	adds	r3, #20
+ 8014c38:	4618      	mov	r0, r3
+ 8014c3a:	f00c fbf0 	bl	802141e <sys_mbox_valid>
+ 8014c3e:	4603      	mov	r3, r0
+ 8014c40:	2b00      	cmp	r3, #0
+ 8014c42:	d034      	beq.n	8014cae <netconn_drain+0xf2>
+    while (sys_mbox_tryfetch(&conn->acceptmbox, &mem) != SYS_MBOX_EMPTY) {
+ 8014c44:	e01d      	b.n	8014c82 <netconn_drain+0xc6>
+#if LWIP_NETCONN_FULLDUPLEX
+      if (!lwip_netconn_is_deallocated_msg(mem))
+#endif /* LWIP_NETCONN_FULLDUPLEX */
+      {
+        err_t err;
+        if (!lwip_netconn_is_err_msg(mem, &err)) {
+ 8014c46:	693b      	ldr	r3, [r7, #16]
+ 8014c48:	f107 020e 	add.w	r2, r7, #14
+ 8014c4c:	4611      	mov	r1, r2
+ 8014c4e:	4618      	mov	r0, r3
+ 8014c50:	f7ff fb84 	bl	801435c <lwip_netconn_is_err_msg>
+ 8014c54:	4603      	mov	r3, r0
+ 8014c56:	2b00      	cmp	r3, #0
+ 8014c58:	d113      	bne.n	8014c82 <netconn_drain+0xc6>
+          struct netconn *newconn = (struct netconn *)mem;
+ 8014c5a:	693b      	ldr	r3, [r7, #16]
+ 8014c5c:	617b      	str	r3, [r7, #20]
+          /* Only tcp pcbs have an acceptmbox, so no need to check conn->type */
+          /* pcb might be set to NULL already by err_tcp() */
+          /* drain recvmbox */
+          netconn_drain(newconn);
+ 8014c5e:	6978      	ldr	r0, [r7, #20]
+ 8014c60:	f7ff ffac 	bl	8014bbc <netconn_drain>
+          if (newconn->pcb.tcp != NULL) {
+ 8014c64:	697b      	ldr	r3, [r7, #20]
+ 8014c66:	685b      	ldr	r3, [r3, #4]
+ 8014c68:	2b00      	cmp	r3, #0
+ 8014c6a:	d007      	beq.n	8014c7c <netconn_drain+0xc0>
+            tcp_abort(newconn->pcb.tcp);
+ 8014c6c:	697b      	ldr	r3, [r7, #20]
+ 8014c6e:	685b      	ldr	r3, [r3, #4]
+ 8014c70:	4618      	mov	r0, r3
+ 8014c72:	f003 fd31 	bl	80186d8 <tcp_abort>
+            newconn->pcb.tcp = NULL;
+ 8014c76:	697b      	ldr	r3, [r7, #20]
+ 8014c78:	2200      	movs	r2, #0
+ 8014c7a:	605a      	str	r2, [r3, #4]
+          }
+          netconn_free(newconn);
+ 8014c7c:	6978      	ldr	r0, [r7, #20]
+ 8014c7e:	f7ff ff53 	bl	8014b28 <netconn_free>
+    while (sys_mbox_tryfetch(&conn->acceptmbox, &mem) != SYS_MBOX_EMPTY) {
+ 8014c82:	687b      	ldr	r3, [r7, #4]
+ 8014c84:	3314      	adds	r3, #20
+ 8014c86:	f107 0210 	add.w	r2, r7, #16
+ 8014c8a:	4611      	mov	r1, r2
+ 8014c8c:	4618      	mov	r0, r3
+ 8014c8e:	f00c fbaa 	bl	80213e6 <sys_arch_mbox_tryfetch>
+ 8014c92:	4603      	mov	r3, r0
+ 8014c94:	f1b3 3fff 	cmp.w	r3, #4294967295
+ 8014c98:	d1d5      	bne.n	8014c46 <netconn_drain+0x8a>
+        }
+      }
+    }
+    sys_mbox_free(&conn->acceptmbox);
+ 8014c9a:	687b      	ldr	r3, [r7, #4]
+ 8014c9c:	3314      	adds	r3, #20
+ 8014c9e:	4618      	mov	r0, r3
+ 8014ca0:	f00c fb36 	bl	8021310 <sys_mbox_free>
+    sys_mbox_set_invalid(&conn->acceptmbox);
+ 8014ca4:	687b      	ldr	r3, [r7, #4]
+ 8014ca6:	3314      	adds	r3, #20
+ 8014ca8:	4618      	mov	r0, r3
+ 8014caa:	f00c fbc9 	bl	8021440 <sys_mbox_set_invalid>
+  }
+#endif /* LWIP_TCP */
+}
+ 8014cae:	bf00      	nop
+ 8014cb0:	3718      	adds	r7, #24
+ 8014cb2:	46bd      	mov	sp, r7
+ 8014cb4:	bd80      	pop	{r7, pc}
+	...
+
+08014cb8 <lwip_netconn_do_close_internal>:
+ *
+ * @param conn the TCP netconn to close
+ */
+static err_t
+lwip_netconn_do_close_internal(struct netconn *conn  WRITE_DELAYED_PARAM)
+{
+ 8014cb8:	b580      	push	{r7, lr}
+ 8014cba:	b086      	sub	sp, #24
+ 8014cbc:	af00      	add	r7, sp, #0
+ 8014cbe:	6078      	str	r0, [r7, #4]
+ 8014cc0:	460b      	mov	r3, r1
+ 8014cc2:	70fb      	strb	r3, [r7, #3]
+  err_t err;
+  u8_t shut, shut_rx, shut_tx, shut_close;
+  u8_t close_finished = 0;
+ 8014cc4:	2300      	movs	r3, #0
+ 8014cc6:	757b      	strb	r3, [r7, #21]
+  struct tcp_pcb *tpcb;
+#if LWIP_SO_LINGER
+  u8_t linger_wait_required = 0;
+#endif /* LWIP_SO_LINGER */
+
+  LWIP_ASSERT("invalid conn", (conn != NULL));
+ 8014cc8:	687b      	ldr	r3, [r7, #4]
+ 8014cca:	2b00      	cmp	r3, #0
+ 8014ccc:	d106      	bne.n	8014cdc <lwip_netconn_do_close_internal+0x24>
+ 8014cce:	4b87      	ldr	r3, [pc, #540]	; (8014eec <lwip_netconn_do_close_internal+0x234>)
+ 8014cd0:	f240 32a2 	movw	r2, #930	; 0x3a2
+ 8014cd4:	4986      	ldr	r1, [pc, #536]	; (8014ef0 <lwip_netconn_do_close_internal+0x238>)
+ 8014cd6:	4887      	ldr	r0, [pc, #540]	; (8014ef4 <lwip_netconn_do_close_internal+0x23c>)
+ 8014cd8:	f00c fe56 	bl	8021988 <iprintf>
+  LWIP_ASSERT("this is for tcp netconns only", (NETCONNTYPE_GROUP(conn->type) == NETCONN_TCP));
+ 8014cdc:	687b      	ldr	r3, [r7, #4]
+ 8014cde:	781b      	ldrb	r3, [r3, #0]
+ 8014ce0:	f003 03f0 	and.w	r3, r3, #240	; 0xf0
+ 8014ce4:	2b10      	cmp	r3, #16
+ 8014ce6:	d006      	beq.n	8014cf6 <lwip_netconn_do_close_internal+0x3e>
+ 8014ce8:	4b80      	ldr	r3, [pc, #512]	; (8014eec <lwip_netconn_do_close_internal+0x234>)
+ 8014cea:	f240 32a3 	movw	r2, #931	; 0x3a3
+ 8014cee:	4982      	ldr	r1, [pc, #520]	; (8014ef8 <lwip_netconn_do_close_internal+0x240>)
+ 8014cf0:	4880      	ldr	r0, [pc, #512]	; (8014ef4 <lwip_netconn_do_close_internal+0x23c>)
+ 8014cf2:	f00c fe49 	bl	8021988 <iprintf>
+  LWIP_ASSERT("conn must be in state NETCONN_CLOSE", (conn->state == NETCONN_CLOSE));
+ 8014cf6:	687b      	ldr	r3, [r7, #4]
+ 8014cf8:	785b      	ldrb	r3, [r3, #1]
+ 8014cfa:	2b04      	cmp	r3, #4
+ 8014cfc:	d006      	beq.n	8014d0c <lwip_netconn_do_close_internal+0x54>
+ 8014cfe:	4b7b      	ldr	r3, [pc, #492]	; (8014eec <lwip_netconn_do_close_internal+0x234>)
+ 8014d00:	f44f 7269 	mov.w	r2, #932	; 0x3a4
+ 8014d04:	497d      	ldr	r1, [pc, #500]	; (8014efc <lwip_netconn_do_close_internal+0x244>)
+ 8014d06:	487b      	ldr	r0, [pc, #492]	; (8014ef4 <lwip_netconn_do_close_internal+0x23c>)
+ 8014d08:	f00c fe3e 	bl	8021988 <iprintf>
+  LWIP_ASSERT("pcb already closed", (conn->pcb.tcp != NULL));
+ 8014d0c:	687b      	ldr	r3, [r7, #4]
+ 8014d0e:	685b      	ldr	r3, [r3, #4]
+ 8014d10:	2b00      	cmp	r3, #0
+ 8014d12:	d106      	bne.n	8014d22 <lwip_netconn_do_close_internal+0x6a>
+ 8014d14:	4b75      	ldr	r3, [pc, #468]	; (8014eec <lwip_netconn_do_close_internal+0x234>)
+ 8014d16:	f240 32a5 	movw	r2, #933	; 0x3a5
+ 8014d1a:	4979      	ldr	r1, [pc, #484]	; (8014f00 <lwip_netconn_do_close_internal+0x248>)
+ 8014d1c:	4875      	ldr	r0, [pc, #468]	; (8014ef4 <lwip_netconn_do_close_internal+0x23c>)
+ 8014d1e:	f00c fe33 	bl	8021988 <iprintf>
+  LWIP_ASSERT("conn->current_msg != NULL", conn->current_msg != NULL);
+ 8014d22:	687b      	ldr	r3, [r7, #4]
+ 8014d24:	6a1b      	ldr	r3, [r3, #32]
+ 8014d26:	2b00      	cmp	r3, #0
+ 8014d28:	d106      	bne.n	8014d38 <lwip_netconn_do_close_internal+0x80>
+ 8014d2a:	4b70      	ldr	r3, [pc, #448]	; (8014eec <lwip_netconn_do_close_internal+0x234>)
+ 8014d2c:	f240 32a6 	movw	r2, #934	; 0x3a6
+ 8014d30:	4974      	ldr	r1, [pc, #464]	; (8014f04 <lwip_netconn_do_close_internal+0x24c>)
+ 8014d32:	4870      	ldr	r0, [pc, #448]	; (8014ef4 <lwip_netconn_do_close_internal+0x23c>)
+ 8014d34:	f00c fe28 	bl	8021988 <iprintf>
+
+  tpcb = conn->pcb.tcp;
+ 8014d38:	687b      	ldr	r3, [r7, #4]
+ 8014d3a:	685b      	ldr	r3, [r3, #4]
+ 8014d3c:	613b      	str	r3, [r7, #16]
+  shut = conn->current_msg->msg.sd.shut;
+ 8014d3e:	687b      	ldr	r3, [r7, #4]
+ 8014d40:	6a1b      	ldr	r3, [r3, #32]
+ 8014d42:	7a1b      	ldrb	r3, [r3, #8]
+ 8014d44:	73fb      	strb	r3, [r7, #15]
+  shut_rx = shut & NETCONN_SHUT_RD;
+ 8014d46:	7bfb      	ldrb	r3, [r7, #15]
+ 8014d48:	f003 0301 	and.w	r3, r3, #1
+ 8014d4c:	73bb      	strb	r3, [r7, #14]
+  shut_tx = shut & NETCONN_SHUT_WR;
+ 8014d4e:	7bfb      	ldrb	r3, [r7, #15]
+ 8014d50:	f003 0302 	and.w	r3, r3, #2
+ 8014d54:	737b      	strb	r3, [r7, #13]
+  /* shutting down both ends is the same as closing
+     (also if RD or WR side was shut down before already) */
+  if (shut == NETCONN_SHUT_RDWR) {
+ 8014d56:	7bfb      	ldrb	r3, [r7, #15]
+ 8014d58:	2b03      	cmp	r3, #3
+ 8014d5a:	d102      	bne.n	8014d62 <lwip_netconn_do_close_internal+0xaa>
+    shut_close = 1;
+ 8014d5c:	2301      	movs	r3, #1
+ 8014d5e:	75bb      	strb	r3, [r7, #22]
+ 8014d60:	e01f      	b.n	8014da2 <lwip_netconn_do_close_internal+0xea>
+  } else if (shut_rx &&
+ 8014d62:	7bbb      	ldrb	r3, [r7, #14]
+ 8014d64:	2b00      	cmp	r3, #0
+ 8014d66:	d00e      	beq.n	8014d86 <lwip_netconn_do_close_internal+0xce>
+             ((tpcb->state == FIN_WAIT_1) ||
+ 8014d68:	693b      	ldr	r3, [r7, #16]
+ 8014d6a:	7d1b      	ldrb	r3, [r3, #20]
+  } else if (shut_rx &&
+ 8014d6c:	2b05      	cmp	r3, #5
+ 8014d6e:	d007      	beq.n	8014d80 <lwip_netconn_do_close_internal+0xc8>
+              (tpcb->state == FIN_WAIT_2) ||
+ 8014d70:	693b      	ldr	r3, [r7, #16]
+ 8014d72:	7d1b      	ldrb	r3, [r3, #20]
+             ((tpcb->state == FIN_WAIT_1) ||
+ 8014d74:	2b06      	cmp	r3, #6
+ 8014d76:	d003      	beq.n	8014d80 <lwip_netconn_do_close_internal+0xc8>
+              (tpcb->state == CLOSING))) {
+ 8014d78:	693b      	ldr	r3, [r7, #16]
+ 8014d7a:	7d1b      	ldrb	r3, [r3, #20]
+              (tpcb->state == FIN_WAIT_2) ||
+ 8014d7c:	2b08      	cmp	r3, #8
+ 8014d7e:	d102      	bne.n	8014d86 <lwip_netconn_do_close_internal+0xce>
+    shut_close = 1;
+ 8014d80:	2301      	movs	r3, #1
+ 8014d82:	75bb      	strb	r3, [r7, #22]
+ 8014d84:	e00d      	b.n	8014da2 <lwip_netconn_do_close_internal+0xea>
+  } else if (shut_tx && ((tpcb->flags & TF_RXCLOSED) != 0)) {
+ 8014d86:	7b7b      	ldrb	r3, [r7, #13]
+ 8014d88:	2b00      	cmp	r3, #0
+ 8014d8a:	d008      	beq.n	8014d9e <lwip_netconn_do_close_internal+0xe6>
+ 8014d8c:	693b      	ldr	r3, [r7, #16]
+ 8014d8e:	8b5b      	ldrh	r3, [r3, #26]
+ 8014d90:	f003 0310 	and.w	r3, r3, #16
+ 8014d94:	2b00      	cmp	r3, #0
+ 8014d96:	d002      	beq.n	8014d9e <lwip_netconn_do_close_internal+0xe6>
+    shut_close = 1;
+ 8014d98:	2301      	movs	r3, #1
+ 8014d9a:	75bb      	strb	r3, [r7, #22]
+ 8014d9c:	e001      	b.n	8014da2 <lwip_netconn_do_close_internal+0xea>
+  } else {
+    shut_close = 0;
+ 8014d9e:	2300      	movs	r3, #0
+ 8014da0:	75bb      	strb	r3, [r7, #22]
+  }
+
+  /* Set back some callback pointers */
+  if (shut_close) {
+ 8014da2:	7dbb      	ldrb	r3, [r7, #22]
+ 8014da4:	2b00      	cmp	r3, #0
+ 8014da6:	d003      	beq.n	8014db0 <lwip_netconn_do_close_internal+0xf8>
+    tcp_arg(tpcb, NULL);
+ 8014da8:	2100      	movs	r1, #0
+ 8014daa:	6938      	ldr	r0, [r7, #16]
+ 8014dac:	f004 fd74 	bl	8019898 <tcp_arg>
+  }
+  if (tpcb->state == LISTEN) {
+ 8014db0:	693b      	ldr	r3, [r7, #16]
+ 8014db2:	7d1b      	ldrb	r3, [r3, #20]
+ 8014db4:	2b01      	cmp	r3, #1
+ 8014db6:	d104      	bne.n	8014dc2 <lwip_netconn_do_close_internal+0x10a>
+    tcp_accept(tpcb, NULL);
+ 8014db8:	2100      	movs	r1, #0
+ 8014dba:	6938      	ldr	r0, [r7, #16]
+ 8014dbc:	f004 fde4 	bl	8019988 <tcp_accept>
+ 8014dc0:	e01d      	b.n	8014dfe <lwip_netconn_do_close_internal+0x146>
+  } else {
+    /* some callbacks have to be reset if tcp_close is not successful */
+    if (shut_rx) {
+ 8014dc2:	7bbb      	ldrb	r3, [r7, #14]
+ 8014dc4:	2b00      	cmp	r3, #0
+ 8014dc6:	d007      	beq.n	8014dd8 <lwip_netconn_do_close_internal+0x120>
+      tcp_recv(tpcb, NULL);
+ 8014dc8:	2100      	movs	r1, #0
+ 8014dca:	6938      	ldr	r0, [r7, #16]
+ 8014dcc:	f004 fd76 	bl	80198bc <tcp_recv>
+      tcp_accept(tpcb, NULL);
+ 8014dd0:	2100      	movs	r1, #0
+ 8014dd2:	6938      	ldr	r0, [r7, #16]
+ 8014dd4:	f004 fdd8 	bl	8019988 <tcp_accept>
+    }
+    if (shut_tx) {
+ 8014dd8:	7b7b      	ldrb	r3, [r7, #13]
+ 8014dda:	2b00      	cmp	r3, #0
+ 8014ddc:	d003      	beq.n	8014de6 <lwip_netconn_do_close_internal+0x12e>
+      tcp_sent(tpcb, NULL);
+ 8014dde:	2100      	movs	r1, #0
+ 8014de0:	6938      	ldr	r0, [r7, #16]
+ 8014de2:	f004 fd8d 	bl	8019900 <tcp_sent>
+    }
+    if (shut_close) {
+ 8014de6:	7dbb      	ldrb	r3, [r7, #22]
+ 8014de8:	2b00      	cmp	r3, #0
+ 8014dea:	d008      	beq.n	8014dfe <lwip_netconn_do_close_internal+0x146>
+      tcp_poll(tpcb, NULL, 0);
+ 8014dec:	2200      	movs	r2, #0
+ 8014dee:	2100      	movs	r1, #0
+ 8014df0:	6938      	ldr	r0, [r7, #16]
+ 8014df2:	f004 fde1 	bl	80199b8 <tcp_poll>
+      tcp_err(tpcb, NULL);
+ 8014df6:	2100      	movs	r1, #0
+ 8014df8:	6938      	ldr	r0, [r7, #16]
+ 8014dfa:	f004 fda3 	bl	8019944 <tcp_err>
+    }
+  }
+  /* Try to close the connection */
+  if (shut_close) {
+ 8014dfe:	7dbb      	ldrb	r3, [r7, #22]
+ 8014e00:	2b00      	cmp	r3, #0
+ 8014e02:	d005      	beq.n	8014e10 <lwip_netconn_do_close_internal+0x158>
+      }
+    }
+    if ((err == ERR_OK) && (tpcb != NULL))
+#endif /* LWIP_SO_LINGER */
+    {
+      err = tcp_close(tpcb);
+ 8014e04:	6938      	ldr	r0, [r7, #16]
+ 8014e06:	f003 fb21 	bl	801844c <tcp_close>
+ 8014e0a:	4603      	mov	r3, r0
+ 8014e0c:	75fb      	strb	r3, [r7, #23]
+ 8014e0e:	e007      	b.n	8014e20 <lwip_netconn_do_close_internal+0x168>
+    }
+  } else {
+    err = tcp_shutdown(tpcb, shut_rx, shut_tx);
+ 8014e10:	7bbb      	ldrb	r3, [r7, #14]
+ 8014e12:	7b7a      	ldrb	r2, [r7, #13]
+ 8014e14:	4619      	mov	r1, r3
+ 8014e16:	6938      	ldr	r0, [r7, #16]
+ 8014e18:	f003 fb44 	bl	80184a4 <tcp_shutdown>
+ 8014e1c:	4603      	mov	r3, r0
+ 8014e1e:	75fb      	strb	r3, [r7, #23]
+  }
+  if (err == ERR_OK) {
+ 8014e20:	f997 3017 	ldrsb.w	r3, [r7, #23]
+ 8014e24:	2b00      	cmp	r3, #0
+ 8014e26:	d102      	bne.n	8014e2e <lwip_netconn_do_close_internal+0x176>
+    close_finished = 1;
+ 8014e28:	2301      	movs	r3, #1
+ 8014e2a:	757b      	strb	r3, [r7, #21]
+ 8014e2c:	e016      	b.n	8014e5c <lwip_netconn_do_close_internal+0x1a4>
+      close_finished = 0;
+      err = ERR_INPROGRESS;
+    }
+#endif /* LWIP_SO_LINGER */
+  } else {
+    if (err == ERR_MEM) {
+ 8014e2e:	f997 3017 	ldrsb.w	r3, [r7, #23]
+ 8014e32:	f1b3 3fff 	cmp.w	r3, #4294967295
+ 8014e36:	d10f      	bne.n	8014e58 <lwip_netconn_do_close_internal+0x1a0>
+        close_timeout = conn->linger * 1000U;
+      }
+#endif
+      if ((s32_t)(sys_now() - conn->current_msg->msg.sd.time_started) >= close_timeout) {
+#else /* LWIP_SO_SNDTIMEO || LWIP_SO_LINGER */
+      if (conn->current_msg->msg.sd.polls_left == 0) {
+ 8014e38:	687b      	ldr	r3, [r7, #4]
+ 8014e3a:	6a1b      	ldr	r3, [r3, #32]
+ 8014e3c:	7a5b      	ldrb	r3, [r3, #9]
+ 8014e3e:	2b00      	cmp	r3, #0
+ 8014e40:	d10c      	bne.n	8014e5c <lwip_netconn_do_close_internal+0x1a4>
+#endif /* LWIP_SO_SNDTIMEO || LWIP_SO_LINGER */
+        close_finished = 1;
+ 8014e42:	2301      	movs	r3, #1
+ 8014e44:	757b      	strb	r3, [r7, #21]
+        if (shut_close) {
+ 8014e46:	7dbb      	ldrb	r3, [r7, #22]
+ 8014e48:	2b00      	cmp	r3, #0
+ 8014e4a:	d007      	beq.n	8014e5c <lwip_netconn_do_close_internal+0x1a4>
+          /* in this case, we want to RST the connection */
+          tcp_abort(tpcb);
+ 8014e4c:	6938      	ldr	r0, [r7, #16]
+ 8014e4e:	f003 fc43 	bl	80186d8 <tcp_abort>
+          err = ERR_OK;
+ 8014e52:	2300      	movs	r3, #0
+ 8014e54:	75fb      	strb	r3, [r7, #23]
+ 8014e56:	e001      	b.n	8014e5c <lwip_netconn_do_close_internal+0x1a4>
+        }
+      }
+    } else {
+      /* Closing failed for a non-memory error: give up */
+      close_finished = 1;
+ 8014e58:	2301      	movs	r3, #1
+ 8014e5a:	757b      	strb	r3, [r7, #21]
+    }
+  }
+  if (close_finished) {
+ 8014e5c:	7d7b      	ldrb	r3, [r7, #21]
+ 8014e5e:	2b00      	cmp	r3, #0
+ 8014e60:	d052      	beq.n	8014f08 <lwip_netconn_do_close_internal+0x250>
+    /* Closing done (succeeded, non-memory error, nonblocking error or timeout) */
+    sys_sem_t *op_completed_sem = LWIP_API_MSG_SEM(conn->current_msg);
+ 8014e62:	687b      	ldr	r3, [r7, #4]
+ 8014e64:	6a1b      	ldr	r3, [r3, #32]
+ 8014e66:	681b      	ldr	r3, [r3, #0]
+ 8014e68:	330c      	adds	r3, #12
+ 8014e6a:	60bb      	str	r3, [r7, #8]
+    conn->current_msg->err = err;
+ 8014e6c:	687b      	ldr	r3, [r7, #4]
+ 8014e6e:	6a1b      	ldr	r3, [r3, #32]
+ 8014e70:	7dfa      	ldrb	r2, [r7, #23]
+ 8014e72:	711a      	strb	r2, [r3, #4]
+    conn->current_msg = NULL;
+ 8014e74:	687b      	ldr	r3, [r7, #4]
+ 8014e76:	2200      	movs	r2, #0
+ 8014e78:	621a      	str	r2, [r3, #32]
+    conn->state = NETCONN_NONE;
+ 8014e7a:	687b      	ldr	r3, [r7, #4]
+ 8014e7c:	2200      	movs	r2, #0
+ 8014e7e:	705a      	strb	r2, [r3, #1]
+    if (err == ERR_OK) {
+ 8014e80:	f997 3017 	ldrsb.w	r3, [r7, #23]
+ 8014e84:	2b00      	cmp	r3, #0
+ 8014e86:	d129      	bne.n	8014edc <lwip_netconn_do_close_internal+0x224>
+      if (shut_close) {
+ 8014e88:	7dbb      	ldrb	r3, [r7, #22]
+ 8014e8a:	2b00      	cmp	r3, #0
+ 8014e8c:	d00c      	beq.n	8014ea8 <lwip_netconn_do_close_internal+0x1f0>
+        /* Set back some callback pointers as conn is going away */
+        conn->pcb.tcp = NULL;
+ 8014e8e:	687b      	ldr	r3, [r7, #4]
+ 8014e90:	2200      	movs	r2, #0
+ 8014e92:	605a      	str	r2, [r3, #4]
+        /* Trigger select() in socket layer. Make sure everybody notices activity
+         on the connection, error first! */
+        API_EVENT(conn, NETCONN_EVT_ERROR, 0);
+ 8014e94:	687b      	ldr	r3, [r7, #4]
+ 8014e96:	6a5b      	ldr	r3, [r3, #36]	; 0x24
+ 8014e98:	2b00      	cmp	r3, #0
+ 8014e9a:	d005      	beq.n	8014ea8 <lwip_netconn_do_close_internal+0x1f0>
+ 8014e9c:	687b      	ldr	r3, [r7, #4]
+ 8014e9e:	6a5b      	ldr	r3, [r3, #36]	; 0x24
+ 8014ea0:	2200      	movs	r2, #0
+ 8014ea2:	2104      	movs	r1, #4
+ 8014ea4:	6878      	ldr	r0, [r7, #4]
+ 8014ea6:	4798      	blx	r3
+      }
+      if (shut_rx) {
+ 8014ea8:	7bbb      	ldrb	r3, [r7, #14]
+ 8014eaa:	2b00      	cmp	r3, #0
+ 8014eac:	d009      	beq.n	8014ec2 <lwip_netconn_do_close_internal+0x20a>
+        API_EVENT(conn, NETCONN_EVT_RCVPLUS, 0);
+ 8014eae:	687b      	ldr	r3, [r7, #4]
+ 8014eb0:	6a5b      	ldr	r3, [r3, #36]	; 0x24
+ 8014eb2:	2b00      	cmp	r3, #0
+ 8014eb4:	d005      	beq.n	8014ec2 <lwip_netconn_do_close_internal+0x20a>
+ 8014eb6:	687b      	ldr	r3, [r7, #4]
+ 8014eb8:	6a5b      	ldr	r3, [r3, #36]	; 0x24
+ 8014eba:	2200      	movs	r2, #0
+ 8014ebc:	2100      	movs	r1, #0
+ 8014ebe:	6878      	ldr	r0, [r7, #4]
+ 8014ec0:	4798      	blx	r3
+      }
+      if (shut_tx) {
+ 8014ec2:	7b7b      	ldrb	r3, [r7, #13]
+ 8014ec4:	2b00      	cmp	r3, #0
+ 8014ec6:	d009      	beq.n	8014edc <lwip_netconn_do_close_internal+0x224>
+        API_EVENT(conn, NETCONN_EVT_SENDPLUS, 0);
+ 8014ec8:	687b      	ldr	r3, [r7, #4]
+ 8014eca:	6a5b      	ldr	r3, [r3, #36]	; 0x24
+ 8014ecc:	2b00      	cmp	r3, #0
+ 8014ece:	d005      	beq.n	8014edc <lwip_netconn_do_close_internal+0x224>
+ 8014ed0:	687b      	ldr	r3, [r7, #4]
+ 8014ed2:	6a5b      	ldr	r3, [r3, #36]	; 0x24
+ 8014ed4:	2200      	movs	r2, #0
+ 8014ed6:	2102      	movs	r1, #2
+ 8014ed8:	6878      	ldr	r0, [r7, #4]
+ 8014eda:	4798      	blx	r3
+      }
+    }
+#if LWIP_TCPIP_CORE_LOCKING
+    if (delayed)
+ 8014edc:	78fb      	ldrb	r3, [r7, #3]
+ 8014ede:	2b00      	cmp	r3, #0
+ 8014ee0:	d002      	beq.n	8014ee8 <lwip_netconn_do_close_internal+0x230>
+#endif
+    {
+      /* wake up the application task */
+      sys_sem_signal(op_completed_sem);
+ 8014ee2:	68b8      	ldr	r0, [r7, #8]
+ 8014ee4:	f00c fb12 	bl	802150c <sys_sem_signal>
+    }
+    return ERR_OK;
+ 8014ee8:	2300      	movs	r3, #0
+ 8014eea:	e03c      	b.n	8014f66 <lwip_netconn_do_close_internal+0x2ae>
+ 8014eec:	08023624 	.word	0x08023624
+ 8014ef0:	080238f8 	.word	0x080238f8
+ 8014ef4:	08023668 	.word	0x08023668
+ 8014ef8:	08023908 	.word	0x08023908
+ 8014efc:	08023928 	.word	0x08023928
+ 8014f00:	0802394c 	.word	0x0802394c
+ 8014f04:	0802378c 	.word	0x0802378c
+  }
+  if (!close_finished) {
+ 8014f08:	7d7b      	ldrb	r3, [r7, #21]
+ 8014f0a:	2b00      	cmp	r3, #0
+ 8014f0c:	d11e      	bne.n	8014f4c <lwip_netconn_do_close_internal+0x294>
+    /* Closing failed and we want to wait: restore some of the callbacks */
+    /* Closing of listen pcb will never fail! */
+    LWIP_ASSERT("Closing a listen pcb may not fail!", (tpcb->state != LISTEN));
+ 8014f0e:	693b      	ldr	r3, [r7, #16]
+ 8014f10:	7d1b      	ldrb	r3, [r3, #20]
+ 8014f12:	2b01      	cmp	r3, #1
+ 8014f14:	d106      	bne.n	8014f24 <lwip_netconn_do_close_internal+0x26c>
+ 8014f16:	4b16      	ldr	r3, [pc, #88]	; (8014f70 <lwip_netconn_do_close_internal+0x2b8>)
+ 8014f18:	f240 4241 	movw	r2, #1089	; 0x441
+ 8014f1c:	4915      	ldr	r1, [pc, #84]	; (8014f74 <lwip_netconn_do_close_internal+0x2bc>)
+ 8014f1e:	4816      	ldr	r0, [pc, #88]	; (8014f78 <lwip_netconn_do_close_internal+0x2c0>)
+ 8014f20:	f00c fd32 	bl	8021988 <iprintf>
+    if (shut_tx) {
+ 8014f24:	7b7b      	ldrb	r3, [r7, #13]
+ 8014f26:	2b00      	cmp	r3, #0
+ 8014f28:	d003      	beq.n	8014f32 <lwip_netconn_do_close_internal+0x27a>
+      tcp_sent(tpcb, sent_tcp);
+ 8014f2a:	4914      	ldr	r1, [pc, #80]	; (8014f7c <lwip_netconn_do_close_internal+0x2c4>)
+ 8014f2c:	6938      	ldr	r0, [r7, #16]
+ 8014f2e:	f004 fce7 	bl	8019900 <tcp_sent>
+    }
+    /* when waiting for close, set up poll interval to 500ms */
+    tcp_poll(tpcb, poll_tcp, 1);
+ 8014f32:	2201      	movs	r2, #1
+ 8014f34:	4912      	ldr	r1, [pc, #72]	; (8014f80 <lwip_netconn_do_close_internal+0x2c8>)
+ 8014f36:	6938      	ldr	r0, [r7, #16]
+ 8014f38:	f004 fd3e 	bl	80199b8 <tcp_poll>
+    tcp_err(tpcb, err_tcp);
+ 8014f3c:	4911      	ldr	r1, [pc, #68]	; (8014f84 <lwip_netconn_do_close_internal+0x2cc>)
+ 8014f3e:	6938      	ldr	r0, [r7, #16]
+ 8014f40:	f004 fd00 	bl	8019944 <tcp_err>
+    tcp_arg(tpcb, conn);
+ 8014f44:	6879      	ldr	r1, [r7, #4]
+ 8014f46:	6938      	ldr	r0, [r7, #16]
+ 8014f48:	f004 fca6 	bl	8019898 <tcp_arg>
+    /* don't restore recv callback: we don't want to receive any more data */
+  }
+  /* If closing didn't succeed, we get called again either
+     from poll_tcp or from sent_tcp */
+  LWIP_ASSERT("err != ERR_OK", err != ERR_OK);
+ 8014f4c:	f997 3017 	ldrsb.w	r3, [r7, #23]
+ 8014f50:	2b00      	cmp	r3, #0
+ 8014f52:	d106      	bne.n	8014f62 <lwip_netconn_do_close_internal+0x2aa>
+ 8014f54:	4b06      	ldr	r3, [pc, #24]	; (8014f70 <lwip_netconn_do_close_internal+0x2b8>)
+ 8014f56:	f240 424d 	movw	r2, #1101	; 0x44d
+ 8014f5a:	490b      	ldr	r1, [pc, #44]	; (8014f88 <lwip_netconn_do_close_internal+0x2d0>)
+ 8014f5c:	4806      	ldr	r0, [pc, #24]	; (8014f78 <lwip_netconn_do_close_internal+0x2c0>)
+ 8014f5e:	f00c fd13 	bl	8021988 <iprintf>
+  return err;
+ 8014f62:	f997 3017 	ldrsb.w	r3, [r7, #23]
+}
+ 8014f66:	4618      	mov	r0, r3
+ 8014f68:	3718      	adds	r7, #24
+ 8014f6a:	46bd      	mov	sp, r7
+ 8014f6c:	bd80      	pop	{r7, pc}
+ 8014f6e:	bf00      	nop
+ 8014f70:	08023624 	.word	0x08023624
+ 8014f74:	08023960 	.word	0x08023960
+ 8014f78:	08023668 	.word	0x08023668
+ 8014f7c:	080146a5 	.word	0x080146a5
+ 8014f80:	080145d9 	.word	0x080145d9
+ 8014f84:	08014751 	.word	0x08014751
+ 8014f88:	08023984 	.word	0x08023984
+
+08014f8c <lwip_netconn_do_delconn>:
+ *
+ * @param m the api_msg pointing to the connection
+ */
+void
+lwip_netconn_do_delconn(void *m)
+{
+ 8014f8c:	b580      	push	{r7, lr}
+ 8014f8e:	b084      	sub	sp, #16
+ 8014f90:	af00      	add	r7, sp, #0
+ 8014f92:	6078      	str	r0, [r7, #4]
+  struct api_msg *msg = (struct api_msg *)m;
+ 8014f94:	687b      	ldr	r3, [r7, #4]
+ 8014f96:	60fb      	str	r3, [r7, #12]
+
+  enum netconn_state state = msg->conn->state;
+ 8014f98:	68fb      	ldr	r3, [r7, #12]
+ 8014f9a:	681b      	ldr	r3, [r3, #0]
+ 8014f9c:	785b      	ldrb	r3, [r3, #1]
+ 8014f9e:	72fb      	strb	r3, [r7, #11]
+  LWIP_ASSERT("netconn state error", /* this only happens for TCP netconns */
+ 8014fa0:	7afb      	ldrb	r3, [r7, #11]
+ 8014fa2:	2b00      	cmp	r3, #0
+ 8014fa4:	d00d      	beq.n	8014fc2 <lwip_netconn_do_delconn+0x36>
+ 8014fa6:	68fb      	ldr	r3, [r7, #12]
+ 8014fa8:	681b      	ldr	r3, [r3, #0]
+ 8014faa:	781b      	ldrb	r3, [r3, #0]
+ 8014fac:	f003 03f0 	and.w	r3, r3, #240	; 0xf0
+ 8014fb0:	2b10      	cmp	r3, #16
+ 8014fb2:	d006      	beq.n	8014fc2 <lwip_netconn_do_delconn+0x36>
+ 8014fb4:	4b60      	ldr	r3, [pc, #384]	; (8015138 <lwip_netconn_do_delconn+0x1ac>)
+ 8014fb6:	f240 425e 	movw	r2, #1118	; 0x45e
+ 8014fba:	4960      	ldr	r1, [pc, #384]	; (801513c <lwip_netconn_do_delconn+0x1b0>)
+ 8014fbc:	4860      	ldr	r0, [pc, #384]	; (8015140 <lwip_netconn_do_delconn+0x1b4>)
+ 8014fbe:	f00c fce3 	bl	8021988 <iprintf>
+      msg->conn->state = NETCONN_NONE;
+      sys_sem_signal(op_completed_sem);
+    }
+  }
+#else /* LWIP_NETCONN_FULLDUPLEX */
+  if (((state != NETCONN_NONE) &&
+ 8014fc2:	7afb      	ldrb	r3, [r7, #11]
+ 8014fc4:	2b00      	cmp	r3, #0
+ 8014fc6:	d005      	beq.n	8014fd4 <lwip_netconn_do_delconn+0x48>
+ 8014fc8:	7afb      	ldrb	r3, [r7, #11]
+ 8014fca:	2b02      	cmp	r3, #2
+ 8014fcc:	d002      	beq.n	8014fd4 <lwip_netconn_do_delconn+0x48>
+       (state != NETCONN_LISTEN) &&
+ 8014fce:	7afb      	ldrb	r3, [r7, #11]
+ 8014fd0:	2b03      	cmp	r3, #3
+ 8014fd2:	d109      	bne.n	8014fe8 <lwip_netconn_do_delconn+0x5c>
+       (state != NETCONN_CONNECT)) ||
+ 8014fd4:	7afb      	ldrb	r3, [r7, #11]
+ 8014fd6:	2b03      	cmp	r3, #3
+ 8014fd8:	d10a      	bne.n	8014ff0 <lwip_netconn_do_delconn+0x64>
+      ((state == NETCONN_CONNECT) && !IN_NONBLOCKING_CONNECT(msg->conn))) {
+ 8014fda:	68fb      	ldr	r3, [r7, #12]
+ 8014fdc:	681b      	ldr	r3, [r3, #0]
+ 8014fde:	7f1b      	ldrb	r3, [r3, #28]
+ 8014fe0:	f003 0304 	and.w	r3, r3, #4
+ 8014fe4:	2b00      	cmp	r3, #0
+ 8014fe6:	d103      	bne.n	8014ff0 <lwip_netconn_do_delconn+0x64>
+    /* This means either a blocking write or blocking connect is running
+       (nonblocking write returns and sets state to NONE) */
+    msg->err = ERR_INPROGRESS;
+ 8014fe8:	68fb      	ldr	r3, [r7, #12]
+ 8014fea:	22fb      	movs	r2, #251	; 0xfb
+ 8014fec:	711a      	strb	r2, [r3, #4]
+ 8014fee:	e097      	b.n	8015120 <lwip_netconn_do_delconn+0x194>
+  } else
+#endif /* LWIP_NETCONN_FULLDUPLEX */
+  {
+    LWIP_ASSERT("blocking connect in progress",
+ 8014ff0:	7afb      	ldrb	r3, [r7, #11]
+ 8014ff2:	2b03      	cmp	r3, #3
+ 8014ff4:	d10d      	bne.n	8015012 <lwip_netconn_do_delconn+0x86>
+ 8014ff6:	68fb      	ldr	r3, [r7, #12]
+ 8014ff8:	681b      	ldr	r3, [r3, #0]
+ 8014ffa:	7f1b      	ldrb	r3, [r3, #28]
+ 8014ffc:	f003 0304 	and.w	r3, r3, #4
+ 8015000:	2b00      	cmp	r3, #0
+ 8015002:	d106      	bne.n	8015012 <lwip_netconn_do_delconn+0x86>
+ 8015004:	4b4c      	ldr	r3, [pc, #304]	; (8015138 <lwip_netconn_do_delconn+0x1ac>)
+ 8015006:	f240 427a 	movw	r2, #1146	; 0x47a
+ 801500a:	494e      	ldr	r1, [pc, #312]	; (8015144 <lwip_netconn_do_delconn+0x1b8>)
+ 801500c:	484c      	ldr	r0, [pc, #304]	; (8015140 <lwip_netconn_do_delconn+0x1b4>)
+ 801500e:	f00c fcbb 	bl	8021988 <iprintf>
+                (state != NETCONN_CONNECT) || IN_NONBLOCKING_CONNECT(msg->conn));
+    msg->err = ERR_OK;
+ 8015012:	68fb      	ldr	r3, [r7, #12]
+ 8015014:	2200      	movs	r2, #0
+ 8015016:	711a      	strb	r2, [r3, #4]
+#if LWIP_NETCONN_FULLDUPLEX
+    /* Mark mboxes invalid */
+    netconn_mark_mbox_invalid(msg->conn);
+#else /* LWIP_NETCONN_FULLDUPLEX */
+    netconn_drain(msg->conn);
+ 8015018:	68fb      	ldr	r3, [r7, #12]
+ 801501a:	681b      	ldr	r3, [r3, #0]
+ 801501c:	4618      	mov	r0, r3
+ 801501e:	f7ff fdcd 	bl	8014bbc <netconn_drain>
+#endif /* LWIP_NETCONN_FULLDUPLEX */
+
+    if (msg->conn->pcb.tcp != NULL) {
+ 8015022:	68fb      	ldr	r3, [r7, #12]
+ 8015024:	681b      	ldr	r3, [r3, #0]
+ 8015026:	685b      	ldr	r3, [r3, #4]
+ 8015028:	2b00      	cmp	r3, #0
+ 801502a:	d05f      	beq.n	80150ec <lwip_netconn_do_delconn+0x160>
+
+      switch (NETCONNTYPE_GROUP(msg->conn->type)) {
+ 801502c:	68fb      	ldr	r3, [r7, #12]
+ 801502e:	681b      	ldr	r3, [r3, #0]
+ 8015030:	781b      	ldrb	r3, [r3, #0]
+ 8015032:	f003 03f0 	and.w	r3, r3, #240	; 0xf0
+ 8015036:	2b10      	cmp	r3, #16
+ 8015038:	d00d      	beq.n	8015056 <lwip_netconn_do_delconn+0xca>
+ 801503a:	2b20      	cmp	r3, #32
+ 801503c:	d151      	bne.n	80150e2 <lwip_netconn_do_delconn+0x156>
+          raw_remove(msg->conn->pcb.raw);
+          break;
+#endif /* LWIP_RAW */
+#if LWIP_UDP
+        case NETCONN_UDP:
+          msg->conn->pcb.udp->recv_arg = NULL;
+ 801503e:	68fb      	ldr	r3, [r7, #12]
+ 8015040:	681b      	ldr	r3, [r3, #0]
+ 8015042:	685b      	ldr	r3, [r3, #4]
+ 8015044:	2200      	movs	r2, #0
+ 8015046:	61da      	str	r2, [r3, #28]
+          udp_remove(msg->conn->pcb.udp);
+ 8015048:	68fb      	ldr	r3, [r7, #12]
+ 801504a:	681b      	ldr	r3, [r3, #0]
+ 801504c:	685b      	ldr	r3, [r3, #4]
+ 801504e:	4618      	mov	r0, r3
+ 8015050:	f009 fd88 	bl	801eb64 <udp_remove>
+          break;
+ 8015054:	e046      	b.n	80150e4 <lwip_netconn_do_delconn+0x158>
+#endif /* LWIP_UDP */
+#if LWIP_TCP
+        case NETCONN_TCP:
+          LWIP_ASSERT("already writing or closing", msg->conn->current_msg == NULL);
+ 8015056:	68fb      	ldr	r3, [r7, #12]
+ 8015058:	681b      	ldr	r3, [r3, #0]
+ 801505a:	6a1b      	ldr	r3, [r3, #32]
+ 801505c:	2b00      	cmp	r3, #0
+ 801505e:	d006      	beq.n	801506e <lwip_netconn_do_delconn+0xe2>
+ 8015060:	4b35      	ldr	r3, [pc, #212]	; (8015138 <lwip_netconn_do_delconn+0x1ac>)
+ 8015062:	f240 4294 	movw	r2, #1172	; 0x494
+ 8015066:	4938      	ldr	r1, [pc, #224]	; (8015148 <lwip_netconn_do_delconn+0x1bc>)
+ 8015068:	4835      	ldr	r0, [pc, #212]	; (8015140 <lwip_netconn_do_delconn+0x1b4>)
+ 801506a:	f00c fc8d 	bl	8021988 <iprintf>
+          msg->conn->state = NETCONN_CLOSE;
+ 801506e:	68fb      	ldr	r3, [r7, #12]
+ 8015070:	681b      	ldr	r3, [r3, #0]
+ 8015072:	2204      	movs	r2, #4
+ 8015074:	705a      	strb	r2, [r3, #1]
+          msg->msg.sd.shut = NETCONN_SHUT_RDWR;
+ 8015076:	68fb      	ldr	r3, [r7, #12]
+ 8015078:	2203      	movs	r2, #3
+ 801507a:	721a      	strb	r2, [r3, #8]
+          msg->conn->current_msg = msg;
+ 801507c:	68fb      	ldr	r3, [r7, #12]
+ 801507e:	681b      	ldr	r3, [r3, #0]
+ 8015080:	68fa      	ldr	r2, [r7, #12]
+ 8015082:	621a      	str	r2, [r3, #32]
+#if LWIP_TCPIP_CORE_LOCKING
+          if (lwip_netconn_do_close_internal(msg->conn, 0) != ERR_OK) {
+ 8015084:	68fb      	ldr	r3, [r7, #12]
+ 8015086:	681b      	ldr	r3, [r3, #0]
+ 8015088:	2100      	movs	r1, #0
+ 801508a:	4618      	mov	r0, r3
+ 801508c:	f7ff fe14 	bl	8014cb8 <lwip_netconn_do_close_internal>
+ 8015090:	4603      	mov	r3, r0
+ 8015092:	2b00      	cmp	r3, #0
+ 8015094:	d04b      	beq.n	801512e <lwip_netconn_do_delconn+0x1a2>
+            LWIP_ASSERT("state!", msg->conn->state == NETCONN_CLOSE);
+ 8015096:	68fb      	ldr	r3, [r7, #12]
+ 8015098:	681b      	ldr	r3, [r3, #0]
+ 801509a:	785b      	ldrb	r3, [r3, #1]
+ 801509c:	2b04      	cmp	r3, #4
+ 801509e:	d006      	beq.n	80150ae <lwip_netconn_do_delconn+0x122>
+ 80150a0:	4b25      	ldr	r3, [pc, #148]	; (8015138 <lwip_netconn_do_delconn+0x1ac>)
+ 80150a2:	f240 429a 	movw	r2, #1178	; 0x49a
+ 80150a6:	4929      	ldr	r1, [pc, #164]	; (801514c <lwip_netconn_do_delconn+0x1c0>)
+ 80150a8:	4825      	ldr	r0, [pc, #148]	; (8015140 <lwip_netconn_do_delconn+0x1b4>)
+ 80150aa:	f00c fc6d 	bl	8021988 <iprintf>
+            UNLOCK_TCPIP_CORE();
+ 80150ae:	4828      	ldr	r0, [pc, #160]	; (8015150 <lwip_netconn_do_delconn+0x1c4>)
+ 80150b0:	f00c fa9d 	bl	80215ee <sys_mutex_unlock>
+            sys_arch_sem_wait(LWIP_API_MSG_SEM(msg), 0);
+ 80150b4:	68fb      	ldr	r3, [r7, #12]
+ 80150b6:	681b      	ldr	r3, [r3, #0]
+ 80150b8:	330c      	adds	r3, #12
+ 80150ba:	2100      	movs	r1, #0
+ 80150bc:	4618      	mov	r0, r3
+ 80150be:	f00c f9f4 	bl	80214aa <sys_arch_sem_wait>
+            LOCK_TCPIP_CORE();
+ 80150c2:	4823      	ldr	r0, [pc, #140]	; (8015150 <lwip_netconn_do_delconn+0x1c4>)
+ 80150c4:	f00c fa84 	bl	80215d0 <sys_mutex_lock>
+            LWIP_ASSERT("state!", msg->conn->state == NETCONN_NONE);
+ 80150c8:	68fb      	ldr	r3, [r7, #12]
+ 80150ca:	681b      	ldr	r3, [r3, #0]
+ 80150cc:	785b      	ldrb	r3, [r3, #1]
+ 80150ce:	2b00      	cmp	r3, #0
+ 80150d0:	d02d      	beq.n	801512e <lwip_netconn_do_delconn+0x1a2>
+ 80150d2:	4b19      	ldr	r3, [pc, #100]	; (8015138 <lwip_netconn_do_delconn+0x1ac>)
+ 80150d4:	f240 429e 	movw	r2, #1182	; 0x49e
+ 80150d8:	491c      	ldr	r1, [pc, #112]	; (801514c <lwip_netconn_do_delconn+0x1c0>)
+ 80150da:	4819      	ldr	r0, [pc, #100]	; (8015140 <lwip_netconn_do_delconn+0x1b4>)
+ 80150dc:	f00c fc54 	bl	8021988 <iprintf>
+#else /* LWIP_TCPIP_CORE_LOCKING */
+          lwip_netconn_do_close_internal(msg->conn);
+#endif /* LWIP_TCPIP_CORE_LOCKING */
+          /* API_EVENT is called inside lwip_netconn_do_close_internal, before releasing
+             the application thread, so we can return at this point! */
+          return;
+ 80150e0:	e025      	b.n	801512e <lwip_netconn_do_delconn+0x1a2>
+#endif /* LWIP_TCP */
+        default:
+          break;
+ 80150e2:	bf00      	nop
+      }
+      msg->conn->pcb.tcp = NULL;
+ 80150e4:	68fb      	ldr	r3, [r7, #12]
+ 80150e6:	681b      	ldr	r3, [r3, #0]
+ 80150e8:	2200      	movs	r2, #0
+ 80150ea:	605a      	str	r2, [r3, #4]
+    }
+    /* tcp netconns don't come here! */
+
+    /* @todo: this lets select make the socket readable and writable,
+       which is wrong! errfd instead? */
+    API_EVENT(msg->conn, NETCONN_EVT_RCVPLUS, 0);
+ 80150ec:	68fb      	ldr	r3, [r7, #12]
+ 80150ee:	681b      	ldr	r3, [r3, #0]
+ 80150f0:	6a5b      	ldr	r3, [r3, #36]	; 0x24
+ 80150f2:	2b00      	cmp	r3, #0
+ 80150f4:	d007      	beq.n	8015106 <lwip_netconn_do_delconn+0x17a>
+ 80150f6:	68fb      	ldr	r3, [r7, #12]
+ 80150f8:	681b      	ldr	r3, [r3, #0]
+ 80150fa:	6a5b      	ldr	r3, [r3, #36]	; 0x24
+ 80150fc:	68fa      	ldr	r2, [r7, #12]
+ 80150fe:	6810      	ldr	r0, [r2, #0]
+ 8015100:	2200      	movs	r2, #0
+ 8015102:	2100      	movs	r1, #0
+ 8015104:	4798      	blx	r3
+    API_EVENT(msg->conn, NETCONN_EVT_SENDPLUS, 0);
+ 8015106:	68fb      	ldr	r3, [r7, #12]
+ 8015108:	681b      	ldr	r3, [r3, #0]
+ 801510a:	6a5b      	ldr	r3, [r3, #36]	; 0x24
+ 801510c:	2b00      	cmp	r3, #0
+ 801510e:	d007      	beq.n	8015120 <lwip_netconn_do_delconn+0x194>
+ 8015110:	68fb      	ldr	r3, [r7, #12]
+ 8015112:	681b      	ldr	r3, [r3, #0]
+ 8015114:	6a5b      	ldr	r3, [r3, #36]	; 0x24
+ 8015116:	68fa      	ldr	r2, [r7, #12]
+ 8015118:	6810      	ldr	r0, [r2, #0]
+ 801511a:	2200      	movs	r2, #0
+ 801511c:	2102      	movs	r1, #2
+ 801511e:	4798      	blx	r3
+  }
+  if (sys_sem_valid(LWIP_API_MSG_SEM(msg))) {
+ 8015120:	68fb      	ldr	r3, [r7, #12]
+ 8015122:	681b      	ldr	r3, [r3, #0]
+ 8015124:	330c      	adds	r3, #12
+ 8015126:	4618      	mov	r0, r3
+ 8015128:	f00c fa0a 	bl	8021540 <sys_sem_valid>
+ 801512c:	e000      	b.n	8015130 <lwip_netconn_do_delconn+0x1a4>
+          return;
+ 801512e:	bf00      	nop
+    TCPIP_APIMSG_ACK(msg);
+  }
+}
+ 8015130:	3710      	adds	r7, #16
+ 8015132:	46bd      	mov	sp, r7
+ 8015134:	bd80      	pop	{r7, pc}
+ 8015136:	bf00      	nop
+ 8015138:	08023624 	.word	0x08023624
+ 801513c:	08023994 	.word	0x08023994
+ 8015140:	08023668 	.word	0x08023668
+ 8015144:	080239a8 	.word	0x080239a8
+ 8015148:	080239c8 	.word	0x080239c8
+ 801514c:	080239e4 	.word	0x080239e4
+ 8015150:	2401397c 	.word	0x2401397c
+
+08015154 <lwip_netconn_do_bind>:
+ * @param m the api_msg pointing to the connection and containing
+ *          the IP address and port to bind to
+ */
+void
+lwip_netconn_do_bind(void *m)
+{
+ 8015154:	b580      	push	{r7, lr}
+ 8015156:	b084      	sub	sp, #16
+ 8015158:	af00      	add	r7, sp, #0
+ 801515a:	6078      	str	r0, [r7, #4]
+  struct api_msg *msg = (struct api_msg *)m;
+ 801515c:	687b      	ldr	r3, [r7, #4]
+ 801515e:	60bb      	str	r3, [r7, #8]
+  err_t err;
+
+  if (msg->conn->pcb.tcp != NULL) {
+ 8015160:	68bb      	ldr	r3, [r7, #8]
+ 8015162:	681b      	ldr	r3, [r3, #0]
+ 8015164:	685b      	ldr	r3, [r3, #4]
+ 8015166:	2b00      	cmp	r3, #0
+ 8015168:	d025      	beq.n	80151b6 <lwip_netconn_do_bind+0x62>
+    switch (NETCONNTYPE_GROUP(msg->conn->type)) {
+ 801516a:	68bb      	ldr	r3, [r7, #8]
+ 801516c:	681b      	ldr	r3, [r3, #0]
+ 801516e:	781b      	ldrb	r3, [r3, #0]
+ 8015170:	f003 03f0 	and.w	r3, r3, #240	; 0xf0
+ 8015174:	2b10      	cmp	r3, #16
+ 8015176:	d00e      	beq.n	8015196 <lwip_netconn_do_bind+0x42>
+ 8015178:	2b20      	cmp	r3, #32
+ 801517a:	d119      	bne.n	80151b0 <lwip_netconn_do_bind+0x5c>
+        err = raw_bind(msg->conn->pcb.raw, API_EXPR_REF(msg->msg.bc.ipaddr));
+        break;
+#endif /* LWIP_RAW */
+#if LWIP_UDP
+      case NETCONN_UDP:
+        err = udp_bind(msg->conn->pcb.udp, API_EXPR_REF(msg->msg.bc.ipaddr), msg->msg.bc.port);
+ 801517c:	68bb      	ldr	r3, [r7, #8]
+ 801517e:	681b      	ldr	r3, [r3, #0]
+ 8015180:	6858      	ldr	r0, [r3, #4]
+ 8015182:	68bb      	ldr	r3, [r7, #8]
+ 8015184:	6899      	ldr	r1, [r3, #8]
+ 8015186:	68bb      	ldr	r3, [r7, #8]
+ 8015188:	899b      	ldrh	r3, [r3, #12]
+ 801518a:	461a      	mov	r2, r3
+ 801518c:	f009 fbd4 	bl	801e938 <udp_bind>
+ 8015190:	4603      	mov	r3, r0
+ 8015192:	73fb      	strb	r3, [r7, #15]
+        break;
+ 8015194:	e011      	b.n	80151ba <lwip_netconn_do_bind+0x66>
+#endif /* LWIP_UDP */
+#if LWIP_TCP
+      case NETCONN_TCP:
+        err = tcp_bind(msg->conn->pcb.tcp, API_EXPR_REF(msg->msg.bc.ipaddr), msg->msg.bc.port);
+ 8015196:	68bb      	ldr	r3, [r7, #8]
+ 8015198:	681b      	ldr	r3, [r3, #0]
+ 801519a:	6858      	ldr	r0, [r3, #4]
+ 801519c:	68bb      	ldr	r3, [r7, #8]
+ 801519e:	6899      	ldr	r1, [r3, #8]
+ 80151a0:	68bb      	ldr	r3, [r7, #8]
+ 80151a2:	899b      	ldrh	r3, [r3, #12]
+ 80151a4:	461a      	mov	r2, r3
+ 80151a6:	f003 faa3 	bl	80186f0 <tcp_bind>
+ 80151aa:	4603      	mov	r3, r0
+ 80151ac:	73fb      	strb	r3, [r7, #15]
+        break;
+ 80151ae:	e004      	b.n	80151ba <lwip_netconn_do_bind+0x66>
+#endif /* LWIP_TCP */
+      default:
+        err = ERR_VAL;
+ 80151b0:	23fa      	movs	r3, #250	; 0xfa
+ 80151b2:	73fb      	strb	r3, [r7, #15]
+        break;
+ 80151b4:	e001      	b.n	80151ba <lwip_netconn_do_bind+0x66>
+    }
+  } else {
+    err = ERR_VAL;
+ 80151b6:	23fa      	movs	r3, #250	; 0xfa
+ 80151b8:	73fb      	strb	r3, [r7, #15]
+  }
+  msg->err = err;
+ 80151ba:	68bb      	ldr	r3, [r7, #8]
+ 80151bc:	7bfa      	ldrb	r2, [r7, #15]
+ 80151be:	711a      	strb	r2, [r3, #4]
+  TCPIP_APIMSG_ACK(msg);
+}
+ 80151c0:	bf00      	nop
+ 80151c2:	3710      	adds	r7, #16
+ 80151c4:	46bd      	mov	sp, r7
+ 80151c6:	bd80      	pop	{r7, pc}
+
+080151c8 <lwip_netconn_do_connected>:
+ *
+ * @see tcp.h (struct tcp_pcb.connected) for parameters and return values
+ */
+static err_t
+lwip_netconn_do_connected(void *arg, struct tcp_pcb *pcb, err_t err)
+{
+ 80151c8:	b580      	push	{r7, lr}
+ 80151ca:	b088      	sub	sp, #32
+ 80151cc:	af00      	add	r7, sp, #0
+ 80151ce:	60f8      	str	r0, [r7, #12]
+ 80151d0:	60b9      	str	r1, [r7, #8]
+ 80151d2:	4613      	mov	r3, r2
+ 80151d4:	71fb      	strb	r3, [r7, #7]
+  struct netconn *conn;
+  int was_blocking;
+  sys_sem_t *op_completed_sem = NULL;
+ 80151d6:	2300      	movs	r3, #0
+ 80151d8:	61fb      	str	r3, [r7, #28]
+
+  LWIP_UNUSED_ARG(pcb);
+
+  conn = (struct netconn *)arg;
+ 80151da:	68fb      	ldr	r3, [r7, #12]
+ 80151dc:	61bb      	str	r3, [r7, #24]
+
+  if (conn == NULL) {
+ 80151de:	69bb      	ldr	r3, [r7, #24]
+ 80151e0:	2b00      	cmp	r3, #0
+ 80151e2:	d102      	bne.n	80151ea <lwip_netconn_do_connected+0x22>
+    return ERR_VAL;
+ 80151e4:	f06f 0305 	mvn.w	r3, #5
+ 80151e8:	e070      	b.n	80152cc <lwip_netconn_do_connected+0x104>
+  }
+
+  LWIP_ASSERT("conn->state == NETCONN_CONNECT", conn->state == NETCONN_CONNECT);
+ 80151ea:	69bb      	ldr	r3, [r7, #24]
+ 80151ec:	785b      	ldrb	r3, [r3, #1]
+ 80151ee:	2b03      	cmp	r3, #3
+ 80151f0:	d006      	beq.n	8015200 <lwip_netconn_do_connected+0x38>
+ 80151f2:	4b38      	ldr	r3, [pc, #224]	; (80152d4 <lwip_netconn_do_connected+0x10c>)
+ 80151f4:	f240 5223 	movw	r2, #1315	; 0x523
+ 80151f8:	4937      	ldr	r1, [pc, #220]	; (80152d8 <lwip_netconn_do_connected+0x110>)
+ 80151fa:	4838      	ldr	r0, [pc, #224]	; (80152dc <lwip_netconn_do_connected+0x114>)
+ 80151fc:	f00c fbc4 	bl	8021988 <iprintf>
+  LWIP_ASSERT("(conn->current_msg != NULL) || conn->in_non_blocking_connect",
+ 8015200:	69bb      	ldr	r3, [r7, #24]
+ 8015202:	6a1b      	ldr	r3, [r3, #32]
+ 8015204:	2b00      	cmp	r3, #0
+ 8015206:	d10c      	bne.n	8015222 <lwip_netconn_do_connected+0x5a>
+ 8015208:	69bb      	ldr	r3, [r7, #24]
+ 801520a:	7f1b      	ldrb	r3, [r3, #28]
+ 801520c:	f003 0304 	and.w	r3, r3, #4
+ 8015210:	2b00      	cmp	r3, #0
+ 8015212:	d106      	bne.n	8015222 <lwip_netconn_do_connected+0x5a>
+ 8015214:	4b2f      	ldr	r3, [pc, #188]	; (80152d4 <lwip_netconn_do_connected+0x10c>)
+ 8015216:	f240 5224 	movw	r2, #1316	; 0x524
+ 801521a:	4931      	ldr	r1, [pc, #196]	; (80152e0 <lwip_netconn_do_connected+0x118>)
+ 801521c:	482f      	ldr	r0, [pc, #188]	; (80152dc <lwip_netconn_do_connected+0x114>)
+ 801521e:	f00c fbb3 	bl	8021988 <iprintf>
+              (conn->current_msg != NULL) || IN_NONBLOCKING_CONNECT(conn));
+
+  if (conn->current_msg != NULL) {
+ 8015222:	69bb      	ldr	r3, [r7, #24]
+ 8015224:	6a1b      	ldr	r3, [r3, #32]
+ 8015226:	2b00      	cmp	r3, #0
+ 8015228:	d008      	beq.n	801523c <lwip_netconn_do_connected+0x74>
+    conn->current_msg->err = err;
+ 801522a:	69bb      	ldr	r3, [r7, #24]
+ 801522c:	6a1b      	ldr	r3, [r3, #32]
+ 801522e:	79fa      	ldrb	r2, [r7, #7]
+ 8015230:	711a      	strb	r2, [r3, #4]
+    op_completed_sem = LWIP_API_MSG_SEM(conn->current_msg);
+ 8015232:	69bb      	ldr	r3, [r7, #24]
+ 8015234:	6a1b      	ldr	r3, [r3, #32]
+ 8015236:	681b      	ldr	r3, [r3, #0]
+ 8015238:	330c      	adds	r3, #12
+ 801523a:	61fb      	str	r3, [r7, #28]
+  }
+  if ((NETCONNTYPE_GROUP(conn->type) == NETCONN_TCP) && (err == ERR_OK)) {
+ 801523c:	69bb      	ldr	r3, [r7, #24]
+ 801523e:	781b      	ldrb	r3, [r3, #0]
+ 8015240:	f003 03f0 	and.w	r3, r3, #240	; 0xf0
+ 8015244:	2b10      	cmp	r3, #16
+ 8015246:	d106      	bne.n	8015256 <lwip_netconn_do_connected+0x8e>
+ 8015248:	f997 3007 	ldrsb.w	r3, [r7, #7]
+ 801524c:	2b00      	cmp	r3, #0
+ 801524e:	d102      	bne.n	8015256 <lwip_netconn_do_connected+0x8e>
+    setup_tcp(conn);
+ 8015250:	69b8      	ldr	r0, [r7, #24]
+ 8015252:	f7ff fb53 	bl	80148fc <setup_tcp>
+  }
+  was_blocking = !IN_NONBLOCKING_CONNECT(conn);
+ 8015256:	69bb      	ldr	r3, [r7, #24]
+ 8015258:	7f1b      	ldrb	r3, [r3, #28]
+ 801525a:	f003 0304 	and.w	r3, r3, #4
+ 801525e:	2b00      	cmp	r3, #0
+ 8015260:	bf0c      	ite	eq
+ 8015262:	2301      	moveq	r3, #1
+ 8015264:	2300      	movne	r3, #0
+ 8015266:	b2db      	uxtb	r3, r3
+ 8015268:	617b      	str	r3, [r7, #20]
+  SET_NONBLOCKING_CONNECT(conn, 0);
+ 801526a:	69bb      	ldr	r3, [r7, #24]
+ 801526c:	7f1b      	ldrb	r3, [r3, #28]
+ 801526e:	f023 0304 	bic.w	r3, r3, #4
+ 8015272:	b2da      	uxtb	r2, r3
+ 8015274:	69bb      	ldr	r3, [r7, #24]
+ 8015276:	771a      	strb	r2, [r3, #28]
+  LWIP_ASSERT("blocking connect state error",
+ 8015278:	697b      	ldr	r3, [r7, #20]
+ 801527a:	2b00      	cmp	r3, #0
+ 801527c:	d002      	beq.n	8015284 <lwip_netconn_do_connected+0xbc>
+ 801527e:	69fb      	ldr	r3, [r7, #28]
+ 8015280:	2b00      	cmp	r3, #0
+ 8015282:	d10c      	bne.n	801529e <lwip_netconn_do_connected+0xd6>
+ 8015284:	697b      	ldr	r3, [r7, #20]
+ 8015286:	2b00      	cmp	r3, #0
+ 8015288:	d102      	bne.n	8015290 <lwip_netconn_do_connected+0xc8>
+ 801528a:	69fb      	ldr	r3, [r7, #28]
+ 801528c:	2b00      	cmp	r3, #0
+ 801528e:	d006      	beq.n	801529e <lwip_netconn_do_connected+0xd6>
+ 8015290:	4b10      	ldr	r3, [pc, #64]	; (80152d4 <lwip_netconn_do_connected+0x10c>)
+ 8015292:	f44f 62a6 	mov.w	r2, #1328	; 0x530
+ 8015296:	4913      	ldr	r1, [pc, #76]	; (80152e4 <lwip_netconn_do_connected+0x11c>)
+ 8015298:	4810      	ldr	r0, [pc, #64]	; (80152dc <lwip_netconn_do_connected+0x114>)
+ 801529a:	f00c fb75 	bl	8021988 <iprintf>
+              (was_blocking && op_completed_sem != NULL) ||
+              (!was_blocking && op_completed_sem == NULL));
+  conn->current_msg = NULL;
+ 801529e:	69bb      	ldr	r3, [r7, #24]
+ 80152a0:	2200      	movs	r2, #0
+ 80152a2:	621a      	str	r2, [r3, #32]
+  conn->state = NETCONN_NONE;
+ 80152a4:	69bb      	ldr	r3, [r7, #24]
+ 80152a6:	2200      	movs	r2, #0
+ 80152a8:	705a      	strb	r2, [r3, #1]
+  API_EVENT(conn, NETCONN_EVT_SENDPLUS, 0);
+ 80152aa:	69bb      	ldr	r3, [r7, #24]
+ 80152ac:	6a5b      	ldr	r3, [r3, #36]	; 0x24
+ 80152ae:	2b00      	cmp	r3, #0
+ 80152b0:	d005      	beq.n	80152be <lwip_netconn_do_connected+0xf6>
+ 80152b2:	69bb      	ldr	r3, [r7, #24]
+ 80152b4:	6a5b      	ldr	r3, [r3, #36]	; 0x24
+ 80152b6:	2200      	movs	r2, #0
+ 80152b8:	2102      	movs	r1, #2
+ 80152ba:	69b8      	ldr	r0, [r7, #24]
+ 80152bc:	4798      	blx	r3
+
+  if (was_blocking) {
+ 80152be:	697b      	ldr	r3, [r7, #20]
+ 80152c0:	2b00      	cmp	r3, #0
+ 80152c2:	d002      	beq.n	80152ca <lwip_netconn_do_connected+0x102>
+    sys_sem_signal(op_completed_sem);
+ 80152c4:	69f8      	ldr	r0, [r7, #28]
+ 80152c6:	f00c f921 	bl	802150c <sys_sem_signal>
+  }
+  return ERR_OK;
+ 80152ca:	2300      	movs	r3, #0
+}
+ 80152cc:	4618      	mov	r0, r3
+ 80152ce:	3720      	adds	r7, #32
+ 80152d0:	46bd      	mov	sp, r7
+ 80152d2:	bd80      	pop	{r7, pc}
+ 80152d4:	08023624 	.word	0x08023624
+ 80152d8:	080239ec 	.word	0x080239ec
+ 80152dc:	08023668 	.word	0x08023668
+ 80152e0:	08023a0c 	.word	0x08023a0c
+ 80152e4:	08023a4c 	.word	0x08023a4c
+
+080152e8 <lwip_netconn_do_connect>:
+ * @param m the api_msg pointing to the connection and containing
+ *          the IP address and port to connect to
+ */
+void
+lwip_netconn_do_connect(void *m)
+{
+ 80152e8:	b580      	push	{r7, lr}
+ 80152ea:	b086      	sub	sp, #24
+ 80152ec:	af00      	add	r7, sp, #0
+ 80152ee:	6078      	str	r0, [r7, #4]
+  struct api_msg *msg = (struct api_msg *)m;
+ 80152f0:	687b      	ldr	r3, [r7, #4]
+ 80152f2:	613b      	str	r3, [r7, #16]
+  err_t err;
+
+  if (msg->conn->pcb.tcp == NULL) {
+ 80152f4:	693b      	ldr	r3, [r7, #16]
+ 80152f6:	681b      	ldr	r3, [r3, #0]
+ 80152f8:	685b      	ldr	r3, [r3, #4]
+ 80152fa:	2b00      	cmp	r3, #0
+ 80152fc:	d102      	bne.n	8015304 <lwip_netconn_do_connect+0x1c>
+    /* This may happen when calling netconn_connect() a second time */
+    err = ERR_CLSD;
+ 80152fe:	23f1      	movs	r3, #241	; 0xf1
+ 8015300:	75fb      	strb	r3, [r7, #23]
+ 8015302:	e09b      	b.n	801543c <lwip_netconn_do_connect+0x154>
+  } else {
+    switch (NETCONNTYPE_GROUP(msg->conn->type)) {
+ 8015304:	693b      	ldr	r3, [r7, #16]
+ 8015306:	681b      	ldr	r3, [r3, #0]
+ 8015308:	781b      	ldrb	r3, [r3, #0]
+ 801530a:	f003 03f0 	and.w	r3, r3, #240	; 0xf0
+ 801530e:	2b10      	cmp	r3, #16
+ 8015310:	d00f      	beq.n	8015332 <lwip_netconn_do_connect+0x4a>
+ 8015312:	2b20      	cmp	r3, #32
+ 8015314:	f040 8087 	bne.w	8015426 <lwip_netconn_do_connect+0x13e>
+        err = raw_connect(msg->conn->pcb.raw, API_EXPR_REF(msg->msg.bc.ipaddr));
+        break;
+#endif /* LWIP_RAW */
+#if LWIP_UDP
+      case NETCONN_UDP:
+        err = udp_connect(msg->conn->pcb.udp, API_EXPR_REF(msg->msg.bc.ipaddr), msg->msg.bc.port);
+ 8015318:	693b      	ldr	r3, [r7, #16]
+ 801531a:	681b      	ldr	r3, [r3, #0]
+ 801531c:	6858      	ldr	r0, [r3, #4]
+ 801531e:	693b      	ldr	r3, [r7, #16]
+ 8015320:	6899      	ldr	r1, [r3, #8]
+ 8015322:	693b      	ldr	r3, [r7, #16]
+ 8015324:	899b      	ldrh	r3, [r3, #12]
+ 8015326:	461a      	mov	r2, r3
+ 8015328:	f009 fb8e 	bl	801ea48 <udp_connect>
+ 801532c:	4603      	mov	r3, r0
+ 801532e:	75fb      	strb	r3, [r7, #23]
+        break;
+ 8015330:	e084      	b.n	801543c <lwip_netconn_do_connect+0x154>
+#endif /* LWIP_UDP */
+#if LWIP_TCP
+      case NETCONN_TCP:
+        /* Prevent connect while doing any other action. */
+        if (msg->conn->state == NETCONN_CONNECT) {
+ 8015332:	693b      	ldr	r3, [r7, #16]
+ 8015334:	681b      	ldr	r3, [r3, #0]
+ 8015336:	785b      	ldrb	r3, [r3, #1]
+ 8015338:	2b03      	cmp	r3, #3
+ 801533a:	d102      	bne.n	8015342 <lwip_netconn_do_connect+0x5a>
+          err = ERR_ALREADY;
+ 801533c:	23f7      	movs	r3, #247	; 0xf7
+ 801533e:	75fb      	strb	r3, [r7, #23]
+#endif /* LWIP_TCPIP_CORE_LOCKING */
+              return;
+            }
+          }
+        }
+        break;
+ 8015340:	e07b      	b.n	801543a <lwip_netconn_do_connect+0x152>
+        } else if (msg->conn->state != NETCONN_NONE) {
+ 8015342:	693b      	ldr	r3, [r7, #16]
+ 8015344:	681b      	ldr	r3, [r3, #0]
+ 8015346:	785b      	ldrb	r3, [r3, #1]
+ 8015348:	2b00      	cmp	r3, #0
+ 801534a:	d002      	beq.n	8015352 <lwip_netconn_do_connect+0x6a>
+          err = ERR_ISCONN;
+ 801534c:	23f6      	movs	r3, #246	; 0xf6
+ 801534e:	75fb      	strb	r3, [r7, #23]
+        break;
+ 8015350:	e073      	b.n	801543a <lwip_netconn_do_connect+0x152>
+          setup_tcp(msg->conn);
+ 8015352:	693b      	ldr	r3, [r7, #16]
+ 8015354:	681b      	ldr	r3, [r3, #0]
+ 8015356:	4618      	mov	r0, r3
+ 8015358:	f7ff fad0 	bl	80148fc <setup_tcp>
+          err = tcp_connect(msg->conn->pcb.tcp, API_EXPR_REF(msg->msg.bc.ipaddr),
+ 801535c:	693b      	ldr	r3, [r7, #16]
+ 801535e:	681b      	ldr	r3, [r3, #0]
+ 8015360:	6858      	ldr	r0, [r3, #4]
+ 8015362:	693b      	ldr	r3, [r7, #16]
+ 8015364:	6899      	ldr	r1, [r3, #8]
+ 8015366:	693b      	ldr	r3, [r7, #16]
+ 8015368:	899a      	ldrh	r2, [r3, #12]
+ 801536a:	4b38      	ldr	r3, [pc, #224]	; (801544c <lwip_netconn_do_connect+0x164>)
+ 801536c:	f003 fb4a 	bl	8018a04 <tcp_connect>
+ 8015370:	4603      	mov	r3, r0
+ 8015372:	75fb      	strb	r3, [r7, #23]
+          if (err == ERR_OK) {
+ 8015374:	f997 3017 	ldrsb.w	r3, [r7, #23]
+ 8015378:	2b00      	cmp	r3, #0
+ 801537a:	d15e      	bne.n	801543a <lwip_netconn_do_connect+0x152>
+            u8_t non_blocking = netconn_is_nonblocking(msg->conn);
+ 801537c:	693b      	ldr	r3, [r7, #16]
+ 801537e:	681b      	ldr	r3, [r3, #0]
+ 8015380:	7f1b      	ldrb	r3, [r3, #28]
+ 8015382:	f003 0302 	and.w	r3, r3, #2
+ 8015386:	2b00      	cmp	r3, #0
+ 8015388:	bf14      	ite	ne
+ 801538a:	2301      	movne	r3, #1
+ 801538c:	2300      	moveq	r3, #0
+ 801538e:	b2db      	uxtb	r3, r3
+ 8015390:	73fb      	strb	r3, [r7, #15]
+            msg->conn->state = NETCONN_CONNECT;
+ 8015392:	693b      	ldr	r3, [r7, #16]
+ 8015394:	681b      	ldr	r3, [r3, #0]
+ 8015396:	2203      	movs	r2, #3
+ 8015398:	705a      	strb	r2, [r3, #1]
+            SET_NONBLOCKING_CONNECT(msg->conn, non_blocking);
+ 801539a:	7bfb      	ldrb	r3, [r7, #15]
+ 801539c:	2b00      	cmp	r3, #0
+ 801539e:	d009      	beq.n	80153b4 <lwip_netconn_do_connect+0xcc>
+ 80153a0:	693b      	ldr	r3, [r7, #16]
+ 80153a2:	681b      	ldr	r3, [r3, #0]
+ 80153a4:	7f1a      	ldrb	r2, [r3, #28]
+ 80153a6:	693b      	ldr	r3, [r7, #16]
+ 80153a8:	681b      	ldr	r3, [r3, #0]
+ 80153aa:	f042 0204 	orr.w	r2, r2, #4
+ 80153ae:	b2d2      	uxtb	r2, r2
+ 80153b0:	771a      	strb	r2, [r3, #28]
+ 80153b2:	e008      	b.n	80153c6 <lwip_netconn_do_connect+0xde>
+ 80153b4:	693b      	ldr	r3, [r7, #16]
+ 80153b6:	681b      	ldr	r3, [r3, #0]
+ 80153b8:	7f1a      	ldrb	r2, [r3, #28]
+ 80153ba:	693b      	ldr	r3, [r7, #16]
+ 80153bc:	681b      	ldr	r3, [r3, #0]
+ 80153be:	f022 0204 	bic.w	r2, r2, #4
+ 80153c2:	b2d2      	uxtb	r2, r2
+ 80153c4:	771a      	strb	r2, [r3, #28]
+            if (non_blocking) {
+ 80153c6:	7bfb      	ldrb	r3, [r7, #15]
+ 80153c8:	2b00      	cmp	r3, #0
+ 80153ca:	d002      	beq.n	80153d2 <lwip_netconn_do_connect+0xea>
+              err = ERR_INPROGRESS;
+ 80153cc:	23fb      	movs	r3, #251	; 0xfb
+ 80153ce:	75fb      	strb	r3, [r7, #23]
+        break;
+ 80153d0:	e033      	b.n	801543a <lwip_netconn_do_connect+0x152>
+              msg->conn->current_msg = msg;
+ 80153d2:	693b      	ldr	r3, [r7, #16]
+ 80153d4:	681b      	ldr	r3, [r3, #0]
+ 80153d6:	693a      	ldr	r2, [r7, #16]
+ 80153d8:	621a      	str	r2, [r3, #32]
+              LWIP_ASSERT("state!", msg->conn->state == NETCONN_CONNECT);
+ 80153da:	693b      	ldr	r3, [r7, #16]
+ 80153dc:	681b      	ldr	r3, [r3, #0]
+ 80153de:	785b      	ldrb	r3, [r3, #1]
+ 80153e0:	2b03      	cmp	r3, #3
+ 80153e2:	d006      	beq.n	80153f2 <lwip_netconn_do_connect+0x10a>
+ 80153e4:	4b1a      	ldr	r3, [pc, #104]	; (8015450 <lwip_netconn_do_connect+0x168>)
+ 80153e6:	f44f 62ae 	mov.w	r2, #1392	; 0x570
+ 80153ea:	491a      	ldr	r1, [pc, #104]	; (8015454 <lwip_netconn_do_connect+0x16c>)
+ 80153ec:	481a      	ldr	r0, [pc, #104]	; (8015458 <lwip_netconn_do_connect+0x170>)
+ 80153ee:	f00c facb 	bl	8021988 <iprintf>
+              UNLOCK_TCPIP_CORE();
+ 80153f2:	481a      	ldr	r0, [pc, #104]	; (801545c <lwip_netconn_do_connect+0x174>)
+ 80153f4:	f00c f8fb 	bl	80215ee <sys_mutex_unlock>
+              sys_arch_sem_wait(LWIP_API_MSG_SEM(msg), 0);
+ 80153f8:	693b      	ldr	r3, [r7, #16]
+ 80153fa:	681b      	ldr	r3, [r3, #0]
+ 80153fc:	330c      	adds	r3, #12
+ 80153fe:	2100      	movs	r1, #0
+ 8015400:	4618      	mov	r0, r3
+ 8015402:	f00c f852 	bl	80214aa <sys_arch_sem_wait>
+              LOCK_TCPIP_CORE();
+ 8015406:	4815      	ldr	r0, [pc, #84]	; (801545c <lwip_netconn_do_connect+0x174>)
+ 8015408:	f00c f8e2 	bl	80215d0 <sys_mutex_lock>
+              LWIP_ASSERT("state!", msg->conn->state != NETCONN_CONNECT);
+ 801540c:	693b      	ldr	r3, [r7, #16]
+ 801540e:	681b      	ldr	r3, [r3, #0]
+ 8015410:	785b      	ldrb	r3, [r3, #1]
+ 8015412:	2b03      	cmp	r3, #3
+ 8015414:	d116      	bne.n	8015444 <lwip_netconn_do_connect+0x15c>
+ 8015416:	4b0e      	ldr	r3, [pc, #56]	; (8015450 <lwip_netconn_do_connect+0x168>)
+ 8015418:	f240 5274 	movw	r2, #1396	; 0x574
+ 801541c:	490d      	ldr	r1, [pc, #52]	; (8015454 <lwip_netconn_do_connect+0x16c>)
+ 801541e:	480e      	ldr	r0, [pc, #56]	; (8015458 <lwip_netconn_do_connect+0x170>)
+ 8015420:	f00c fab2 	bl	8021988 <iprintf>
+              return;
+ 8015424:	e00e      	b.n	8015444 <lwip_netconn_do_connect+0x15c>
+#endif /* LWIP_TCP */
+      default:
+        LWIP_ERROR("Invalid netconn type", 0, do {
+ 8015426:	4b0a      	ldr	r3, [pc, #40]	; (8015450 <lwip_netconn_do_connect+0x168>)
+ 8015428:	f240 527d 	movw	r2, #1405	; 0x57d
+ 801542c:	490c      	ldr	r1, [pc, #48]	; (8015460 <lwip_netconn_do_connect+0x178>)
+ 801542e:	480a      	ldr	r0, [pc, #40]	; (8015458 <lwip_netconn_do_connect+0x170>)
+ 8015430:	f00c faaa 	bl	8021988 <iprintf>
+ 8015434:	23fa      	movs	r3, #250	; 0xfa
+ 8015436:	75fb      	strb	r3, [r7, #23]
+          err = ERR_VAL;
+        } while (0));
+        break;
+ 8015438:	e000      	b.n	801543c <lwip_netconn_do_connect+0x154>
+        break;
+ 801543a:	bf00      	nop
+    }
+  }
+  msg->err = err;
+ 801543c:	693b      	ldr	r3, [r7, #16]
+ 801543e:	7dfa      	ldrb	r2, [r7, #23]
+ 8015440:	711a      	strb	r2, [r3, #4]
+ 8015442:	e000      	b.n	8015446 <lwip_netconn_do_connect+0x15e>
+              return;
+ 8015444:	bf00      	nop
+  /* For all other protocols, netconn_connect() calls netconn_apimsg(),
+     so use TCPIP_APIMSG_ACK() here. */
+  TCPIP_APIMSG_ACK(msg);
+}
+ 8015446:	3718      	adds	r7, #24
+ 8015448:	46bd      	mov	sp, r7
+ 801544a:	bd80      	pop	{r7, pc}
+ 801544c:	080151c9 	.word	0x080151c9
+ 8015450:	08023624 	.word	0x08023624
+ 8015454:	080239e4 	.word	0x080239e4
+ 8015458:	08023668 	.word	0x08023668
+ 801545c:	2401397c 	.word	0x2401397c
+ 8015460:	08023a6c 	.word	0x08023a6c
+
+08015464 <lwip_netconn_do_recv>:
+ *
+ * @param m the api_msg pointing to the connection
+ */
+void
+lwip_netconn_do_recv(void *m)
+{
+ 8015464:	b580      	push	{r7, lr}
+ 8015466:	b086      	sub	sp, #24
+ 8015468:	af00      	add	r7, sp, #0
+ 801546a:	6078      	str	r0, [r7, #4]
+  struct api_msg *msg = (struct api_msg *)m;
+ 801546c:	687b      	ldr	r3, [r7, #4]
+ 801546e:	613b      	str	r3, [r7, #16]
+
+  msg->err = ERR_OK;
+ 8015470:	693b      	ldr	r3, [r7, #16]
+ 8015472:	2200      	movs	r2, #0
+ 8015474:	711a      	strb	r2, [r3, #4]
+  if (msg->conn->pcb.tcp != NULL) {
+ 8015476:	693b      	ldr	r3, [r7, #16]
+ 8015478:	681b      	ldr	r3, [r3, #0]
+ 801547a:	685b      	ldr	r3, [r3, #4]
+ 801547c:	2b00      	cmp	r3, #0
+ 801547e:	d022      	beq.n	80154c6 <lwip_netconn_do_recv+0x62>
+    if (NETCONNTYPE_GROUP(msg->conn->type) == NETCONN_TCP) {
+ 8015480:	693b      	ldr	r3, [r7, #16]
+ 8015482:	681b      	ldr	r3, [r3, #0]
+ 8015484:	781b      	ldrb	r3, [r3, #0]
+ 8015486:	f003 03f0 	and.w	r3, r3, #240	; 0xf0
+ 801548a:	2b10      	cmp	r3, #16
+ 801548c:	d11b      	bne.n	80154c6 <lwip_netconn_do_recv+0x62>
+      size_t remaining = msg->msg.r.len;
+ 801548e:	693b      	ldr	r3, [r7, #16]
+ 8015490:	689b      	ldr	r3, [r3, #8]
+ 8015492:	617b      	str	r3, [r7, #20]
+      do {
+        u16_t recved = (u16_t)((remaining > 0xffff) ? 0xffff : remaining);
+ 8015494:	697b      	ldr	r3, [r7, #20]
+ 8015496:	f5b3 3f80 	cmp.w	r3, #65536	; 0x10000
+ 801549a:	d202      	bcs.n	80154a2 <lwip_netconn_do_recv+0x3e>
+ 801549c:	697b      	ldr	r3, [r7, #20]
+ 801549e:	b29b      	uxth	r3, r3
+ 80154a0:	e001      	b.n	80154a6 <lwip_netconn_do_recv+0x42>
+ 80154a2:	f64f 73ff 	movw	r3, #65535	; 0xffff
+ 80154a6:	81fb      	strh	r3, [r7, #14]
+        tcp_recved(msg->conn->pcb.tcp, recved);
+ 80154a8:	693b      	ldr	r3, [r7, #16]
+ 80154aa:	681b      	ldr	r3, [r3, #0]
+ 80154ac:	685b      	ldr	r3, [r3, #4]
+ 80154ae:	89fa      	ldrh	r2, [r7, #14]
+ 80154b0:	4611      	mov	r1, r2
+ 80154b2:	4618      	mov	r0, r3
+ 80154b4:	f003 fa0e 	bl	80188d4 <tcp_recved>
+        remaining -= recved;
+ 80154b8:	89fb      	ldrh	r3, [r7, #14]
+ 80154ba:	697a      	ldr	r2, [r7, #20]
+ 80154bc:	1ad3      	subs	r3, r2, r3
+ 80154be:	617b      	str	r3, [r7, #20]
+      } while (remaining != 0);
+ 80154c0:	697b      	ldr	r3, [r7, #20]
+ 80154c2:	2b00      	cmp	r3, #0
+ 80154c4:	d1e6      	bne.n	8015494 <lwip_netconn_do_recv+0x30>
+    }
+  }
+  TCPIP_APIMSG_ACK(msg);
+}
+ 80154c6:	bf00      	nop
+ 80154c8:	3718      	adds	r7, #24
+ 80154ca:	46bd      	mov	sp, r7
+ 80154cc:	bd80      	pop	{r7, pc}
+	...
+
+080154d0 <lwip_netconn_do_writemore>:
+ * @return ERR_OK
+ *         ERR_MEM if LWIP_TCPIP_CORE_LOCKING=1 and sending hasn't yet finished
+ */
+static err_t
+lwip_netconn_do_writemore(struct netconn *conn  WRITE_DELAYED_PARAM)
+{
+ 80154d0:	b580      	push	{r7, lr}
+ 80154d2:	b088      	sub	sp, #32
+ 80154d4:	af00      	add	r7, sp, #0
+ 80154d6:	6078      	str	r0, [r7, #4]
+ 80154d8:	460b      	mov	r3, r1
+ 80154da:	70fb      	strb	r3, [r7, #3]
+  err_t err;
+  const void *dataptr;
+  u16_t len, available;
+  u8_t write_finished = 0;
+ 80154dc:	2300      	movs	r3, #0
+ 80154de:	76fb      	strb	r3, [r7, #27]
+  size_t diff;
+  u8_t dontblock;
+  u8_t apiflags;
+  u8_t write_more;
+
+  LWIP_ASSERT("conn != NULL", conn != NULL);
+ 80154e0:	687b      	ldr	r3, [r7, #4]
+ 80154e2:	2b00      	cmp	r3, #0
+ 80154e4:	d106      	bne.n	80154f4 <lwip_netconn_do_writemore+0x24>
+ 80154e6:	4b96      	ldr	r3, [pc, #600]	; (8015740 <lwip_netconn_do_writemore+0x270>)
+ 80154e8:	f240 6273 	movw	r2, #1651	; 0x673
+ 80154ec:	4995      	ldr	r1, [pc, #596]	; (8015744 <lwip_netconn_do_writemore+0x274>)
+ 80154ee:	4896      	ldr	r0, [pc, #600]	; (8015748 <lwip_netconn_do_writemore+0x278>)
+ 80154f0:	f00c fa4a 	bl	8021988 <iprintf>
+  LWIP_ASSERT("conn->state == NETCONN_WRITE", (conn->state == NETCONN_WRITE));
+ 80154f4:	687b      	ldr	r3, [r7, #4]
+ 80154f6:	785b      	ldrb	r3, [r3, #1]
+ 80154f8:	2b01      	cmp	r3, #1
+ 80154fa:	d006      	beq.n	801550a <lwip_netconn_do_writemore+0x3a>
+ 80154fc:	4b90      	ldr	r3, [pc, #576]	; (8015740 <lwip_netconn_do_writemore+0x270>)
+ 80154fe:	f240 6274 	movw	r2, #1652	; 0x674
+ 8015502:	4992      	ldr	r1, [pc, #584]	; (801574c <lwip_netconn_do_writemore+0x27c>)
+ 8015504:	4890      	ldr	r0, [pc, #576]	; (8015748 <lwip_netconn_do_writemore+0x278>)
+ 8015506:	f00c fa3f 	bl	8021988 <iprintf>
+  LWIP_ASSERT("conn->current_msg != NULL", conn->current_msg != NULL);
+ 801550a:	687b      	ldr	r3, [r7, #4]
+ 801550c:	6a1b      	ldr	r3, [r3, #32]
+ 801550e:	2b00      	cmp	r3, #0
+ 8015510:	d106      	bne.n	8015520 <lwip_netconn_do_writemore+0x50>
+ 8015512:	4b8b      	ldr	r3, [pc, #556]	; (8015740 <lwip_netconn_do_writemore+0x270>)
+ 8015514:	f240 6275 	movw	r2, #1653	; 0x675
+ 8015518:	498d      	ldr	r1, [pc, #564]	; (8015750 <lwip_netconn_do_writemore+0x280>)
+ 801551a:	488b      	ldr	r0, [pc, #556]	; (8015748 <lwip_netconn_do_writemore+0x278>)
+ 801551c:	f00c fa34 	bl	8021988 <iprintf>
+  LWIP_ASSERT("conn->pcb.tcp != NULL", conn->pcb.tcp != NULL);
+ 8015520:	687b      	ldr	r3, [r7, #4]
+ 8015522:	685b      	ldr	r3, [r3, #4]
+ 8015524:	2b00      	cmp	r3, #0
+ 8015526:	d106      	bne.n	8015536 <lwip_netconn_do_writemore+0x66>
+ 8015528:	4b85      	ldr	r3, [pc, #532]	; (8015740 <lwip_netconn_do_writemore+0x270>)
+ 801552a:	f240 6276 	movw	r2, #1654	; 0x676
+ 801552e:	4989      	ldr	r1, [pc, #548]	; (8015754 <lwip_netconn_do_writemore+0x284>)
+ 8015530:	4885      	ldr	r0, [pc, #532]	; (8015748 <lwip_netconn_do_writemore+0x278>)
+ 8015532:	f00c fa29 	bl	8021988 <iprintf>
+  LWIP_ASSERT("conn->current_msg->msg.w.offset < conn->current_msg->msg.w.len",
+ 8015536:	687b      	ldr	r3, [r7, #4]
+ 8015538:	6a1b      	ldr	r3, [r3, #32]
+ 801553a:	699a      	ldr	r2, [r3, #24]
+ 801553c:	687b      	ldr	r3, [r7, #4]
+ 801553e:	6a1b      	ldr	r3, [r3, #32]
+ 8015540:	695b      	ldr	r3, [r3, #20]
+ 8015542:	429a      	cmp	r2, r3
+ 8015544:	d306      	bcc.n	8015554 <lwip_netconn_do_writemore+0x84>
+ 8015546:	4b7e      	ldr	r3, [pc, #504]	; (8015740 <lwip_netconn_do_writemore+0x270>)
+ 8015548:	f240 6277 	movw	r2, #1655	; 0x677
+ 801554c:	4982      	ldr	r1, [pc, #520]	; (8015758 <lwip_netconn_do_writemore+0x288>)
+ 801554e:	487e      	ldr	r0, [pc, #504]	; (8015748 <lwip_netconn_do_writemore+0x278>)
+ 8015550:	f00c fa1a 	bl	8021988 <iprintf>
+              conn->current_msg->msg.w.offset < conn->current_msg->msg.w.len);
+  LWIP_ASSERT("conn->current_msg->msg.w.vector_cnt > 0", conn->current_msg->msg.w.vector_cnt > 0);
+ 8015554:	687b      	ldr	r3, [r7, #4]
+ 8015556:	6a1b      	ldr	r3, [r3, #32]
+ 8015558:	899b      	ldrh	r3, [r3, #12]
+ 801555a:	2b00      	cmp	r3, #0
+ 801555c:	d106      	bne.n	801556c <lwip_netconn_do_writemore+0x9c>
+ 801555e:	4b78      	ldr	r3, [pc, #480]	; (8015740 <lwip_netconn_do_writemore+0x270>)
+ 8015560:	f240 6279 	movw	r2, #1657	; 0x679
+ 8015564:	497d      	ldr	r1, [pc, #500]	; (801575c <lwip_netconn_do_writemore+0x28c>)
+ 8015566:	4878      	ldr	r0, [pc, #480]	; (8015748 <lwip_netconn_do_writemore+0x278>)
+ 8015568:	f00c fa0e 	bl	8021988 <iprintf>
+
+  apiflags = conn->current_msg->msg.w.apiflags;
+ 801556c:	687b      	ldr	r3, [r7, #4]
+ 801556e:	6a1b      	ldr	r3, [r3, #32]
+ 8015570:	7f1b      	ldrb	r3, [r3, #28]
+ 8015572:	76bb      	strb	r3, [r7, #26]
+  dontblock = netconn_is_nonblocking(conn) || (apiflags & NETCONN_DONTBLOCK);
+ 8015574:	687b      	ldr	r3, [r7, #4]
+ 8015576:	7f1b      	ldrb	r3, [r3, #28]
+ 8015578:	f003 0302 	and.w	r3, r3, #2
+ 801557c:	2b00      	cmp	r3, #0
+ 801557e:	d104      	bne.n	801558a <lwip_netconn_do_writemore+0xba>
+ 8015580:	7ebb      	ldrb	r3, [r7, #26]
+ 8015582:	f003 0304 	and.w	r3, r3, #4
+ 8015586:	2b00      	cmp	r3, #0
+ 8015588:	d001      	beq.n	801558e <lwip_netconn_do_writemore+0xbe>
+ 801558a:	2301      	movs	r3, #1
+ 801558c:	e000      	b.n	8015590 <lwip_netconn_do_writemore+0xc0>
+ 801558e:	2300      	movs	r3, #0
+ 8015590:	763b      	strb	r3, [r7, #24]
+    }
+  } else
+#endif /* LWIP_SO_SNDTIMEO */
+  {
+    do {
+      dataptr = (const u8_t *)conn->current_msg->msg.w.vector->ptr + conn->current_msg->msg.w.vector_off;
+ 8015592:	687b      	ldr	r3, [r7, #4]
+ 8015594:	6a1b      	ldr	r3, [r3, #32]
+ 8015596:	689b      	ldr	r3, [r3, #8]
+ 8015598:	681a      	ldr	r2, [r3, #0]
+ 801559a:	687b      	ldr	r3, [r7, #4]
+ 801559c:	6a1b      	ldr	r3, [r3, #32]
+ 801559e:	691b      	ldr	r3, [r3, #16]
+ 80155a0:	4413      	add	r3, r2
+ 80155a2:	617b      	str	r3, [r7, #20]
+      diff = conn->current_msg->msg.w.vector->len - conn->current_msg->msg.w.vector_off;
+ 80155a4:	687b      	ldr	r3, [r7, #4]
+ 80155a6:	6a1b      	ldr	r3, [r3, #32]
+ 80155a8:	689b      	ldr	r3, [r3, #8]
+ 80155aa:	685a      	ldr	r2, [r3, #4]
+ 80155ac:	687b      	ldr	r3, [r7, #4]
+ 80155ae:	6a1b      	ldr	r3, [r3, #32]
+ 80155b0:	691b      	ldr	r3, [r3, #16]
+ 80155b2:	1ad3      	subs	r3, r2, r3
+ 80155b4:	613b      	str	r3, [r7, #16]
+      if (diff > 0xffffUL) { /* max_u16_t */
+ 80155b6:	693b      	ldr	r3, [r7, #16]
+ 80155b8:	f5b3 3f80 	cmp.w	r3, #65536	; 0x10000
+ 80155bc:	d307      	bcc.n	80155ce <lwip_netconn_do_writemore+0xfe>
+        len = 0xffff;
+ 80155be:	f64f 73ff 	movw	r3, #65535	; 0xffff
+ 80155c2:	83bb      	strh	r3, [r7, #28]
+        apiflags |= TCP_WRITE_FLAG_MORE;
+ 80155c4:	7ebb      	ldrb	r3, [r7, #26]
+ 80155c6:	f043 0302 	orr.w	r3, r3, #2
+ 80155ca:	76bb      	strb	r3, [r7, #26]
+ 80155cc:	e001      	b.n	80155d2 <lwip_netconn_do_writemore+0x102>
+      } else {
+        len = (u16_t)diff;
+ 80155ce:	693b      	ldr	r3, [r7, #16]
+ 80155d0:	83bb      	strh	r3, [r7, #28]
+      }
+      available = tcp_sndbuf(conn->pcb.tcp);
+ 80155d2:	687b      	ldr	r3, [r7, #4]
+ 80155d4:	685b      	ldr	r3, [r3, #4]
+ 80155d6:	f8b3 3064 	ldrh.w	r3, [r3, #100]	; 0x64
+ 80155da:	81fb      	strh	r3, [r7, #14]
+      if (available < len) {
+ 80155dc:	89fa      	ldrh	r2, [r7, #14]
+ 80155de:	8bbb      	ldrh	r3, [r7, #28]
+ 80155e0:	429a      	cmp	r2, r3
+ 80155e2:	d216      	bcs.n	8015612 <lwip_netconn_do_writemore+0x142>
+        /* don't try to write more than sendbuf */
+        len = available;
+ 80155e4:	89fb      	ldrh	r3, [r7, #14]
+ 80155e6:	83bb      	strh	r3, [r7, #28]
+        if (dontblock) {
+ 80155e8:	7e3b      	ldrb	r3, [r7, #24]
+ 80155ea:	2b00      	cmp	r3, #0
+ 80155ec:	d00d      	beq.n	801560a <lwip_netconn_do_writemore+0x13a>
+          if (!len) {
+ 80155ee:	8bbb      	ldrh	r3, [r7, #28]
+ 80155f0:	2b00      	cmp	r3, #0
+ 80155f2:	d10e      	bne.n	8015612 <lwip_netconn_do_writemore+0x142>
+            /* set error according to partial write or not */
+            err = (conn->current_msg->msg.w.offset == 0) ? ERR_WOULDBLOCK : ERR_OK;
+ 80155f4:	687b      	ldr	r3, [r7, #4]
+ 80155f6:	6a1b      	ldr	r3, [r3, #32]
+ 80155f8:	699b      	ldr	r3, [r3, #24]
+ 80155fa:	2b00      	cmp	r3, #0
+ 80155fc:	d102      	bne.n	8015604 <lwip_netconn_do_writemore+0x134>
+ 80155fe:	f06f 0306 	mvn.w	r3, #6
+ 8015602:	e000      	b.n	8015606 <lwip_netconn_do_writemore+0x136>
+ 8015604:	2300      	movs	r3, #0
+ 8015606:	77fb      	strb	r3, [r7, #31]
+            goto err_mem;
+ 8015608:	e07d      	b.n	8015706 <lwip_netconn_do_writemore+0x236>
+          }
+        } else {
+          apiflags |= TCP_WRITE_FLAG_MORE;
+ 801560a:	7ebb      	ldrb	r3, [r7, #26]
+ 801560c:	f043 0302 	orr.w	r3, r3, #2
+ 8015610:	76bb      	strb	r3, [r7, #26]
+        }
+      }
+      LWIP_ASSERT("lwip_netconn_do_writemore: invalid length!",
+ 8015612:	687b      	ldr	r3, [r7, #4]
+ 8015614:	6a1b      	ldr	r3, [r3, #32]
+ 8015616:	691a      	ldr	r2, [r3, #16]
+ 8015618:	8bbb      	ldrh	r3, [r7, #28]
+ 801561a:	441a      	add	r2, r3
+ 801561c:	687b      	ldr	r3, [r7, #4]
+ 801561e:	6a1b      	ldr	r3, [r3, #32]
+ 8015620:	689b      	ldr	r3, [r3, #8]
+ 8015622:	685b      	ldr	r3, [r3, #4]
+ 8015624:	429a      	cmp	r2, r3
+ 8015626:	d906      	bls.n	8015636 <lwip_netconn_do_writemore+0x166>
+ 8015628:	4b45      	ldr	r3, [pc, #276]	; (8015740 <lwip_netconn_do_writemore+0x270>)
+ 801562a:	f240 62a3 	movw	r2, #1699	; 0x6a3
+ 801562e:	494c      	ldr	r1, [pc, #304]	; (8015760 <lwip_netconn_do_writemore+0x290>)
+ 8015630:	4845      	ldr	r0, [pc, #276]	; (8015748 <lwip_netconn_do_writemore+0x278>)
+ 8015632:	f00c f9a9 	bl	8021988 <iprintf>
+                  ((conn->current_msg->msg.w.vector_off + len) <= conn->current_msg->msg.w.vector->len));
+      /* we should loop around for more sending in the following cases:
+           1) We couldn't finish the current vector because of 16-bit size limitations.
+              tcp_write() and tcp_sndbuf() both are limited to 16-bit sizes
+           2) We are sending the remainder of the current vector and have more */
+      if ((len == 0xffff && diff > 0xffffUL) ||
+ 8015636:	8bbb      	ldrh	r3, [r7, #28]
+ 8015638:	f64f 72ff 	movw	r2, #65535	; 0xffff
+ 801563c:	4293      	cmp	r3, r2
+ 801563e:	d103      	bne.n	8015648 <lwip_netconn_do_writemore+0x178>
+ 8015640:	693b      	ldr	r3, [r7, #16]
+ 8015642:	f5b3 3f80 	cmp.w	r3, #65536	; 0x10000
+ 8015646:	d209      	bcs.n	801565c <lwip_netconn_do_writemore+0x18c>
+          (len == (u16_t)diff && conn->current_msg->msg.w.vector_cnt > 1)) {
+ 8015648:	693b      	ldr	r3, [r7, #16]
+ 801564a:	b29b      	uxth	r3, r3
+      if ((len == 0xffff && diff > 0xffffUL) ||
+ 801564c:	8bba      	ldrh	r2, [r7, #28]
+ 801564e:	429a      	cmp	r2, r3
+ 8015650:	d10b      	bne.n	801566a <lwip_netconn_do_writemore+0x19a>
+          (len == (u16_t)diff && conn->current_msg->msg.w.vector_cnt > 1)) {
+ 8015652:	687b      	ldr	r3, [r7, #4]
+ 8015654:	6a1b      	ldr	r3, [r3, #32]
+ 8015656:	899b      	ldrh	r3, [r3, #12]
+ 8015658:	2b01      	cmp	r3, #1
+ 801565a:	d906      	bls.n	801566a <lwip_netconn_do_writemore+0x19a>
+        write_more = 1;
+ 801565c:	2301      	movs	r3, #1
+ 801565e:	767b      	strb	r3, [r7, #25]
+        apiflags |= TCP_WRITE_FLAG_MORE;
+ 8015660:	7ebb      	ldrb	r3, [r7, #26]
+ 8015662:	f043 0302 	orr.w	r3, r3, #2
+ 8015666:	76bb      	strb	r3, [r7, #26]
+ 8015668:	e001      	b.n	801566e <lwip_netconn_do_writemore+0x19e>
+      } else {
+        write_more = 0;
+ 801566a:	2300      	movs	r3, #0
+ 801566c:	767b      	strb	r3, [r7, #25]
+      }
+      err = tcp_write(conn->pcb.tcp, dataptr, len, apiflags);
+ 801566e:	687b      	ldr	r3, [r7, #4]
+ 8015670:	6858      	ldr	r0, [r3, #4]
+ 8015672:	7ebb      	ldrb	r3, [r7, #26]
+ 8015674:	8bba      	ldrh	r2, [r7, #28]
+ 8015676:	6979      	ldr	r1, [r7, #20]
+ 8015678:	f007 f858 	bl	801c72c <tcp_write>
+ 801567c:	4603      	mov	r3, r0
+ 801567e:	77fb      	strb	r3, [r7, #31]
+      if (err == ERR_OK) {
+ 8015680:	f997 301f 	ldrsb.w	r3, [r7, #31]
+ 8015684:	2b00      	cmp	r3, #0
+ 8015686:	d12c      	bne.n	80156e2 <lwip_netconn_do_writemore+0x212>
+        conn->current_msg->msg.w.offset += len;
+ 8015688:	687b      	ldr	r3, [r7, #4]
+ 801568a:	6a1b      	ldr	r3, [r3, #32]
+ 801568c:	6999      	ldr	r1, [r3, #24]
+ 801568e:	8bba      	ldrh	r2, [r7, #28]
+ 8015690:	687b      	ldr	r3, [r7, #4]
+ 8015692:	6a1b      	ldr	r3, [r3, #32]
+ 8015694:	440a      	add	r2, r1
+ 8015696:	619a      	str	r2, [r3, #24]
+        conn->current_msg->msg.w.vector_off += len;
+ 8015698:	687b      	ldr	r3, [r7, #4]
+ 801569a:	6a1b      	ldr	r3, [r3, #32]
+ 801569c:	6919      	ldr	r1, [r3, #16]
+ 801569e:	8bba      	ldrh	r2, [r7, #28]
+ 80156a0:	687b      	ldr	r3, [r7, #4]
+ 80156a2:	6a1b      	ldr	r3, [r3, #32]
+ 80156a4:	440a      	add	r2, r1
+ 80156a6:	611a      	str	r2, [r3, #16]
+        /* check if current vector is finished */
+        if (conn->current_msg->msg.w.vector_off == conn->current_msg->msg.w.vector->len) {
+ 80156a8:	687b      	ldr	r3, [r7, #4]
+ 80156aa:	6a1b      	ldr	r3, [r3, #32]
+ 80156ac:	691a      	ldr	r2, [r3, #16]
+ 80156ae:	687b      	ldr	r3, [r7, #4]
+ 80156b0:	6a1b      	ldr	r3, [r3, #32]
+ 80156b2:	689b      	ldr	r3, [r3, #8]
+ 80156b4:	685b      	ldr	r3, [r3, #4]
+ 80156b6:	429a      	cmp	r2, r3
+ 80156b8:	d113      	bne.n	80156e2 <lwip_netconn_do_writemore+0x212>
+          conn->current_msg->msg.w.vector_cnt--;
+ 80156ba:	687b      	ldr	r3, [r7, #4]
+ 80156bc:	6a1b      	ldr	r3, [r3, #32]
+ 80156be:	899a      	ldrh	r2, [r3, #12]
+ 80156c0:	3a01      	subs	r2, #1
+ 80156c2:	b292      	uxth	r2, r2
+ 80156c4:	819a      	strh	r2, [r3, #12]
+          /* if we have additional vectors, move on to them */
+          if (conn->current_msg->msg.w.vector_cnt > 0) {
+ 80156c6:	687b      	ldr	r3, [r7, #4]
+ 80156c8:	6a1b      	ldr	r3, [r3, #32]
+ 80156ca:	899b      	ldrh	r3, [r3, #12]
+ 80156cc:	2b00      	cmp	r3, #0
+ 80156ce:	d008      	beq.n	80156e2 <lwip_netconn_do_writemore+0x212>
+            conn->current_msg->msg.w.vector++;
+ 80156d0:	687b      	ldr	r3, [r7, #4]
+ 80156d2:	6a1b      	ldr	r3, [r3, #32]
+ 80156d4:	689a      	ldr	r2, [r3, #8]
+ 80156d6:	3208      	adds	r2, #8
+ 80156d8:	609a      	str	r2, [r3, #8]
+            conn->current_msg->msg.w.vector_off = 0;
+ 80156da:	687b      	ldr	r3, [r7, #4]
+ 80156dc:	6a1b      	ldr	r3, [r3, #32]
+ 80156de:	2200      	movs	r2, #0
+ 80156e0:	611a      	str	r2, [r3, #16]
+          }
+        }
+      }
+    } while (write_more && err == ERR_OK);
+ 80156e2:	7e7b      	ldrb	r3, [r7, #25]
+ 80156e4:	2b00      	cmp	r3, #0
+ 80156e6:	d004      	beq.n	80156f2 <lwip_netconn_do_writemore+0x222>
+ 80156e8:	f997 301f 	ldrsb.w	r3, [r7, #31]
+ 80156ec:	2b00      	cmp	r3, #0
+ 80156ee:	f43f af50 	beq.w	8015592 <lwip_netconn_do_writemore+0xc2>
+    /* if OK or memory error, check available space */
+    if ((err == ERR_OK) || (err == ERR_MEM)) {
+ 80156f2:	f997 301f 	ldrsb.w	r3, [r7, #31]
+ 80156f6:	2b00      	cmp	r3, #0
+ 80156f8:	d004      	beq.n	8015704 <lwip_netconn_do_writemore+0x234>
+ 80156fa:	f997 301f 	ldrsb.w	r3, [r7, #31]
+ 80156fe:	f1b3 3fff 	cmp.w	r3, #4294967295
+ 8015702:	d147      	bne.n	8015794 <lwip_netconn_do_writemore+0x2c4>
+err_mem:
+ 8015704:	bf00      	nop
+      if (dontblock && (conn->current_msg->msg.w.offset < conn->current_msg->msg.w.len)) {
+ 8015706:	7e3b      	ldrb	r3, [r7, #24]
+ 8015708:	2b00      	cmp	r3, #0
+ 801570a:	d02b      	beq.n	8015764 <lwip_netconn_do_writemore+0x294>
+ 801570c:	687b      	ldr	r3, [r7, #4]
+ 801570e:	6a1b      	ldr	r3, [r3, #32]
+ 8015710:	699a      	ldr	r2, [r3, #24]
+ 8015712:	687b      	ldr	r3, [r7, #4]
+ 8015714:	6a1b      	ldr	r3, [r3, #32]
+ 8015716:	695b      	ldr	r3, [r3, #20]
+ 8015718:	429a      	cmp	r2, r3
+ 801571a:	d223      	bcs.n	8015764 <lwip_netconn_do_writemore+0x294>
+        /* non-blocking write did not write everything: mark the pcb non-writable
+           and let poll_tcp check writable space to mark the pcb writable again */
+        API_EVENT(conn, NETCONN_EVT_SENDMINUS, 0);
+ 801571c:	687b      	ldr	r3, [r7, #4]
+ 801571e:	6a5b      	ldr	r3, [r3, #36]	; 0x24
+ 8015720:	2b00      	cmp	r3, #0
+ 8015722:	d005      	beq.n	8015730 <lwip_netconn_do_writemore+0x260>
+ 8015724:	687b      	ldr	r3, [r7, #4]
+ 8015726:	6a5b      	ldr	r3, [r3, #36]	; 0x24
+ 8015728:	2200      	movs	r2, #0
+ 801572a:	2103      	movs	r1, #3
+ 801572c:	6878      	ldr	r0, [r7, #4]
+ 801572e:	4798      	blx	r3
+        conn->flags |= NETCONN_FLAG_CHECK_WRITESPACE;
+ 8015730:	687b      	ldr	r3, [r7, #4]
+ 8015732:	7f1b      	ldrb	r3, [r3, #28]
+ 8015734:	f043 0310 	orr.w	r3, r3, #16
+ 8015738:	b2da      	uxtb	r2, r3
+ 801573a:	687b      	ldr	r3, [r7, #4]
+ 801573c:	771a      	strb	r2, [r3, #28]
+ 801573e:	e029      	b.n	8015794 <lwip_netconn_do_writemore+0x2c4>
+ 8015740:	08023624 	.word	0x08023624
+ 8015744:	0802377c 	.word	0x0802377c
+ 8015748:	08023668 	.word	0x08023668
+ 801574c:	08023a84 	.word	0x08023a84
+ 8015750:	0802378c 	.word	0x0802378c
+ 8015754:	08023aa4 	.word	0x08023aa4
+ 8015758:	08023abc 	.word	0x08023abc
+ 801575c:	08023afc 	.word	0x08023afc
+ 8015760:	08023b24 	.word	0x08023b24
+      } else if ((tcp_sndbuf(conn->pcb.tcp) <= TCP_SNDLOWAT) ||
+ 8015764:	687b      	ldr	r3, [r7, #4]
+ 8015766:	685b      	ldr	r3, [r3, #4]
+ 8015768:	f8b3 3064 	ldrh.w	r3, [r3, #100]	; 0x64
+ 801576c:	f640 3269 	movw	r2, #2921	; 0xb69
+ 8015770:	4293      	cmp	r3, r2
+ 8015772:	d905      	bls.n	8015780 <lwip_netconn_do_writemore+0x2b0>
+                 (tcp_sndqueuelen(conn->pcb.tcp) >= TCP_SNDQUEUELOWAT)) {
+ 8015774:	687b      	ldr	r3, [r7, #4]
+ 8015776:	685b      	ldr	r3, [r3, #4]
+ 8015778:	f8b3 3066 	ldrh.w	r3, [r3, #102]	; 0x66
+      } else if ((tcp_sndbuf(conn->pcb.tcp) <= TCP_SNDLOWAT) ||
+ 801577c:	2b07      	cmp	r3, #7
+ 801577e:	d909      	bls.n	8015794 <lwip_netconn_do_writemore+0x2c4>
+        /* The queued byte- or pbuf-count exceeds the configured low-water limit,
+           let select mark this pcb as non-writable. */
+        API_EVENT(conn, NETCONN_EVT_SENDMINUS, 0);
+ 8015780:	687b      	ldr	r3, [r7, #4]
+ 8015782:	6a5b      	ldr	r3, [r3, #36]	; 0x24
+ 8015784:	2b00      	cmp	r3, #0
+ 8015786:	d005      	beq.n	8015794 <lwip_netconn_do_writemore+0x2c4>
+ 8015788:	687b      	ldr	r3, [r7, #4]
+ 801578a:	6a5b      	ldr	r3, [r3, #36]	; 0x24
+ 801578c:	2200      	movs	r2, #0
+ 801578e:	2103      	movs	r1, #3
+ 8015790:	6878      	ldr	r0, [r7, #4]
+ 8015792:	4798      	blx	r3
+      }
+    }
+
+    if (err == ERR_OK) {
+ 8015794:	f997 301f 	ldrsb.w	r3, [r7, #31]
+ 8015798:	2b00      	cmp	r3, #0
+ 801579a:	d11d      	bne.n	80157d8 <lwip_netconn_do_writemore+0x308>
+      err_t out_err;
+      if ((conn->current_msg->msg.w.offset == conn->current_msg->msg.w.len) || dontblock) {
+ 801579c:	687b      	ldr	r3, [r7, #4]
+ 801579e:	6a1b      	ldr	r3, [r3, #32]
+ 80157a0:	699a      	ldr	r2, [r3, #24]
+ 80157a2:	687b      	ldr	r3, [r7, #4]
+ 80157a4:	6a1b      	ldr	r3, [r3, #32]
+ 80157a6:	695b      	ldr	r3, [r3, #20]
+ 80157a8:	429a      	cmp	r2, r3
+ 80157aa:	d002      	beq.n	80157b2 <lwip_netconn_do_writemore+0x2e2>
+ 80157ac:	7e3b      	ldrb	r3, [r7, #24]
+ 80157ae:	2b00      	cmp	r3, #0
+ 80157b0:	d001      	beq.n	80157b6 <lwip_netconn_do_writemore+0x2e6>
+        /* return sent length (caller reads length from msg.w.offset) */
+        write_finished = 1;
+ 80157b2:	2301      	movs	r3, #1
+ 80157b4:	76fb      	strb	r3, [r7, #27]
+      }
+      out_err = tcp_output(conn->pcb.tcp);
+ 80157b6:	687b      	ldr	r3, [r7, #4]
+ 80157b8:	685b      	ldr	r3, [r3, #4]
+ 80157ba:	4618      	mov	r0, r3
+ 80157bc:	f007 fdfe 	bl	801d3bc <tcp_output>
+ 80157c0:	4603      	mov	r3, r0
+ 80157c2:	733b      	strb	r3, [r7, #12]
+      if (out_err == ERR_RTE) {
+ 80157c4:	f997 300c 	ldrsb.w	r3, [r7, #12]
+ 80157c8:	f113 0f04 	cmn.w	r3, #4
+ 80157cc:	d12c      	bne.n	8015828 <lwip_netconn_do_writemore+0x358>
+        /* If tcp_output fails because no route is found,
+           don't try writing any more but return the error
+           to the application thread. */
+        err = out_err;
+ 80157ce:	7b3b      	ldrb	r3, [r7, #12]
+ 80157d0:	77fb      	strb	r3, [r7, #31]
+        write_finished = 1;
+ 80157d2:	2301      	movs	r3, #1
+ 80157d4:	76fb      	strb	r3, [r7, #27]
+ 80157d6:	e027      	b.n	8015828 <lwip_netconn_do_writemore+0x358>
+      }
+    } else if (err == ERR_MEM) {
+ 80157d8:	f997 301f 	ldrsb.w	r3, [r7, #31]
+ 80157dc:	f1b3 3fff 	cmp.w	r3, #4294967295
+ 80157e0:	d120      	bne.n	8015824 <lwip_netconn_do_writemore+0x354>
+         For blocking sockets, we do NOT return to the application
+         thread, since ERR_MEM is only a temporary error! Non-blocking
+         will remain non-writable until sent_tcp/poll_tcp is called */
+
+      /* tcp_write returned ERR_MEM, try tcp_output anyway */
+      err_t out_err = tcp_output(conn->pcb.tcp);
+ 80157e2:	687b      	ldr	r3, [r7, #4]
+ 80157e4:	685b      	ldr	r3, [r3, #4]
+ 80157e6:	4618      	mov	r0, r3
+ 80157e8:	f007 fde8 	bl	801d3bc <tcp_output>
+ 80157ec:	4603      	mov	r3, r0
+ 80157ee:	737b      	strb	r3, [r7, #13]
+      if (out_err == ERR_RTE) {
+ 80157f0:	f997 300d 	ldrsb.w	r3, [r7, #13]
+ 80157f4:	f113 0f04 	cmn.w	r3, #4
+ 80157f8:	d104      	bne.n	8015804 <lwip_netconn_do_writemore+0x334>
+        /* If tcp_output fails because no route is found,
+           don't try writing any more but return the error
+           to the application thread. */
+        err = out_err;
+ 80157fa:	7b7b      	ldrb	r3, [r7, #13]
+ 80157fc:	77fb      	strb	r3, [r7, #31]
+        write_finished = 1;
+ 80157fe:	2301      	movs	r3, #1
+ 8015800:	76fb      	strb	r3, [r7, #27]
+ 8015802:	e011      	b.n	8015828 <lwip_netconn_do_writemore+0x358>
+      } else if (dontblock) {
+ 8015804:	7e3b      	ldrb	r3, [r7, #24]
+ 8015806:	2b00      	cmp	r3, #0
+ 8015808:	d00e      	beq.n	8015828 <lwip_netconn_do_writemore+0x358>
+        /* non-blocking write is done on ERR_MEM, set error according
+           to partial write or not */
+        err = (conn->current_msg->msg.w.offset == 0) ? ERR_WOULDBLOCK : ERR_OK;
+ 801580a:	687b      	ldr	r3, [r7, #4]
+ 801580c:	6a1b      	ldr	r3, [r3, #32]
+ 801580e:	699b      	ldr	r3, [r3, #24]
+ 8015810:	2b00      	cmp	r3, #0
+ 8015812:	d102      	bne.n	801581a <lwip_netconn_do_writemore+0x34a>
+ 8015814:	f06f 0306 	mvn.w	r3, #6
+ 8015818:	e000      	b.n	801581c <lwip_netconn_do_writemore+0x34c>
+ 801581a:	2300      	movs	r3, #0
+ 801581c:	77fb      	strb	r3, [r7, #31]
+        write_finished = 1;
+ 801581e:	2301      	movs	r3, #1
+ 8015820:	76fb      	strb	r3, [r7, #27]
+ 8015822:	e001      	b.n	8015828 <lwip_netconn_do_writemore+0x358>
+      }
+    } else {
+      /* On errors != ERR_MEM, we don't try writing any more but return
+         the error to the application thread. */
+      write_finished = 1;
+ 8015824:	2301      	movs	r3, #1
+ 8015826:	76fb      	strb	r3, [r7, #27]
+    }
+  }
+  if (write_finished) {
+ 8015828:	7efb      	ldrb	r3, [r7, #27]
+ 801582a:	2b00      	cmp	r3, #0
+ 801582c:	d015      	beq.n	801585a <lwip_netconn_do_writemore+0x38a>
+    /* everything was written: set back connection state
+       and back to application task */
+    sys_sem_t *op_completed_sem = LWIP_API_MSG_SEM(conn->current_msg);
+ 801582e:	687b      	ldr	r3, [r7, #4]
+ 8015830:	6a1b      	ldr	r3, [r3, #32]
+ 8015832:	681b      	ldr	r3, [r3, #0]
+ 8015834:	330c      	adds	r3, #12
+ 8015836:	60bb      	str	r3, [r7, #8]
+    conn->current_msg->err = err;
+ 8015838:	687b      	ldr	r3, [r7, #4]
+ 801583a:	6a1b      	ldr	r3, [r3, #32]
+ 801583c:	7ffa      	ldrb	r2, [r7, #31]
+ 801583e:	711a      	strb	r2, [r3, #4]
+    conn->current_msg = NULL;
+ 8015840:	687b      	ldr	r3, [r7, #4]
+ 8015842:	2200      	movs	r2, #0
+ 8015844:	621a      	str	r2, [r3, #32]
+    conn->state = NETCONN_NONE;
+ 8015846:	687b      	ldr	r3, [r7, #4]
+ 8015848:	2200      	movs	r2, #0
+ 801584a:	705a      	strb	r2, [r3, #1]
+#if LWIP_TCPIP_CORE_LOCKING
+    if (delayed)
+ 801584c:	78fb      	ldrb	r3, [r7, #3]
+ 801584e:	2b00      	cmp	r3, #0
+ 8015850:	d006      	beq.n	8015860 <lwip_netconn_do_writemore+0x390>
+#endif
+    {
+      sys_sem_signal(op_completed_sem);
+ 8015852:	68b8      	ldr	r0, [r7, #8]
+ 8015854:	f00b fe5a 	bl	802150c <sys_sem_signal>
+ 8015858:	e002      	b.n	8015860 <lwip_netconn_do_writemore+0x390>
+    }
+  }
+#if LWIP_TCPIP_CORE_LOCKING
+  else {
+    return ERR_MEM;
+ 801585a:	f04f 33ff 	mov.w	r3, #4294967295
+ 801585e:	e000      	b.n	8015862 <lwip_netconn_do_writemore+0x392>
+  }
+#endif
+  return ERR_OK;
+ 8015860:	2300      	movs	r3, #0
+}
+ 8015862:	4618      	mov	r0, r3
+ 8015864:	3720      	adds	r7, #32
+ 8015866:	46bd      	mov	sp, r7
+ 8015868:	bd80      	pop	{r7, pc}
+ 801586a:	bf00      	nop
+
+0801586c <lwip_netconn_do_write>:
+ *
+ * @param m the api_msg pointing to the connection
+ */
+void
+lwip_netconn_do_write(void *m)
+{
+ 801586c:	b580      	push	{r7, lr}
+ 801586e:	b084      	sub	sp, #16
+ 8015870:	af00      	add	r7, sp, #0
+ 8015872:	6078      	str	r0, [r7, #4]
+  struct api_msg *msg = (struct api_msg *)m;
+ 8015874:	687b      	ldr	r3, [r7, #4]
+ 8015876:	60bb      	str	r3, [r7, #8]
+
+  err_t err = netconn_err(msg->conn);
+ 8015878:	68bb      	ldr	r3, [r7, #8]
+ 801587a:	681b      	ldr	r3, [r3, #0]
+ 801587c:	4618      	mov	r0, r3
+ 801587e:	f7fe fd1c 	bl	80142ba <netconn_err>
+ 8015882:	4603      	mov	r3, r0
+ 8015884:	73fb      	strb	r3, [r7, #15]
+  if (err == ERR_OK) {
+ 8015886:	f997 300f 	ldrsb.w	r3, [r7, #15]
+ 801588a:	2b00      	cmp	r3, #0
+ 801588c:	d166      	bne.n	801595c <lwip_netconn_do_write+0xf0>
+    if (NETCONNTYPE_GROUP(msg->conn->type) == NETCONN_TCP) {
+ 801588e:	68bb      	ldr	r3, [r7, #8]
+ 8015890:	681b      	ldr	r3, [r3, #0]
+ 8015892:	781b      	ldrb	r3, [r3, #0]
+ 8015894:	f003 03f0 	and.w	r3, r3, #240	; 0xf0
+ 8015898:	2b10      	cmp	r3, #16
+ 801589a:	d15d      	bne.n	8015958 <lwip_netconn_do_write+0xec>
+#if LWIP_TCP
+      if (msg->conn->state != NETCONN_NONE) {
+ 801589c:	68bb      	ldr	r3, [r7, #8]
+ 801589e:	681b      	ldr	r3, [r3, #0]
+ 80158a0:	785b      	ldrb	r3, [r3, #1]
+ 80158a2:	2b00      	cmp	r3, #0
+ 80158a4:	d002      	beq.n	80158ac <lwip_netconn_do_write+0x40>
+        /* netconn is connecting, closing or in blocking write */
+        err = ERR_INPROGRESS;
+ 80158a6:	23fb      	movs	r3, #251	; 0xfb
+ 80158a8:	73fb      	strb	r3, [r7, #15]
+ 80158aa:	e057      	b.n	801595c <lwip_netconn_do_write+0xf0>
+      } else if (msg->conn->pcb.tcp != NULL) {
+ 80158ac:	68bb      	ldr	r3, [r7, #8]
+ 80158ae:	681b      	ldr	r3, [r3, #0]
+ 80158b0:	685b      	ldr	r3, [r3, #4]
+ 80158b2:	2b00      	cmp	r3, #0
+ 80158b4:	d04d      	beq.n	8015952 <lwip_netconn_do_write+0xe6>
+        msg->conn->state = NETCONN_WRITE;
+ 80158b6:	68bb      	ldr	r3, [r7, #8]
+ 80158b8:	681b      	ldr	r3, [r3, #0]
+ 80158ba:	2201      	movs	r2, #1
+ 80158bc:	705a      	strb	r2, [r3, #1]
+        /* set all the variables used by lwip_netconn_do_writemore */
+        LWIP_ASSERT("already writing or closing", msg->conn->current_msg == NULL);
+ 80158be:	68bb      	ldr	r3, [r7, #8]
+ 80158c0:	681b      	ldr	r3, [r3, #0]
+ 80158c2:	6a1b      	ldr	r3, [r3, #32]
+ 80158c4:	2b00      	cmp	r3, #0
+ 80158c6:	d006      	beq.n	80158d6 <lwip_netconn_do_write+0x6a>
+ 80158c8:	4b28      	ldr	r3, [pc, #160]	; (801596c <lwip_netconn_do_write+0x100>)
+ 80158ca:	f240 7223 	movw	r2, #1827	; 0x723
+ 80158ce:	4928      	ldr	r1, [pc, #160]	; (8015970 <lwip_netconn_do_write+0x104>)
+ 80158d0:	4828      	ldr	r0, [pc, #160]	; (8015974 <lwip_netconn_do_write+0x108>)
+ 80158d2:	f00c f859 	bl	8021988 <iprintf>
+        LWIP_ASSERT("msg->msg.w.len != 0", msg->msg.w.len != 0);
+ 80158d6:	68bb      	ldr	r3, [r7, #8]
+ 80158d8:	695b      	ldr	r3, [r3, #20]
+ 80158da:	2b00      	cmp	r3, #0
+ 80158dc:	d106      	bne.n	80158ec <lwip_netconn_do_write+0x80>
+ 80158de:	4b23      	ldr	r3, [pc, #140]	; (801596c <lwip_netconn_do_write+0x100>)
+ 80158e0:	f240 7224 	movw	r2, #1828	; 0x724
+ 80158e4:	4924      	ldr	r1, [pc, #144]	; (8015978 <lwip_netconn_do_write+0x10c>)
+ 80158e6:	4823      	ldr	r0, [pc, #140]	; (8015974 <lwip_netconn_do_write+0x108>)
+ 80158e8:	f00c f84e 	bl	8021988 <iprintf>
+        msg->conn->current_msg = msg;
+ 80158ec:	68bb      	ldr	r3, [r7, #8]
+ 80158ee:	681b      	ldr	r3, [r3, #0]
+ 80158f0:	68ba      	ldr	r2, [r7, #8]
+ 80158f2:	621a      	str	r2, [r3, #32]
+#if LWIP_TCPIP_CORE_LOCKING
+        if (lwip_netconn_do_writemore(msg->conn, 0) != ERR_OK) {
+ 80158f4:	68bb      	ldr	r3, [r7, #8]
+ 80158f6:	681b      	ldr	r3, [r3, #0]
+ 80158f8:	2100      	movs	r1, #0
+ 80158fa:	4618      	mov	r0, r3
+ 80158fc:	f7ff fde8 	bl	80154d0 <lwip_netconn_do_writemore>
+ 8015900:	4603      	mov	r3, r0
+ 8015902:	2b00      	cmp	r3, #0
+ 8015904:	d02e      	beq.n	8015964 <lwip_netconn_do_write+0xf8>
+          LWIP_ASSERT("state!", msg->conn->state == NETCONN_WRITE);
+ 8015906:	68bb      	ldr	r3, [r7, #8]
+ 8015908:	681b      	ldr	r3, [r3, #0]
+ 801590a:	785b      	ldrb	r3, [r3, #1]
+ 801590c:	2b01      	cmp	r3, #1
+ 801590e:	d006      	beq.n	801591e <lwip_netconn_do_write+0xb2>
+ 8015910:	4b16      	ldr	r3, [pc, #88]	; (801596c <lwip_netconn_do_write+0x100>)
+ 8015912:	f44f 62e5 	mov.w	r2, #1832	; 0x728
+ 8015916:	4919      	ldr	r1, [pc, #100]	; (801597c <lwip_netconn_do_write+0x110>)
+ 8015918:	4816      	ldr	r0, [pc, #88]	; (8015974 <lwip_netconn_do_write+0x108>)
+ 801591a:	f00c f835 	bl	8021988 <iprintf>
+          UNLOCK_TCPIP_CORE();
+ 801591e:	4818      	ldr	r0, [pc, #96]	; (8015980 <lwip_netconn_do_write+0x114>)
+ 8015920:	f00b fe65 	bl	80215ee <sys_mutex_unlock>
+          sys_arch_sem_wait(LWIP_API_MSG_SEM(msg), 0);
+ 8015924:	68bb      	ldr	r3, [r7, #8]
+ 8015926:	681b      	ldr	r3, [r3, #0]
+ 8015928:	330c      	adds	r3, #12
+ 801592a:	2100      	movs	r1, #0
+ 801592c:	4618      	mov	r0, r3
+ 801592e:	f00b fdbc 	bl	80214aa <sys_arch_sem_wait>
+          LOCK_TCPIP_CORE();
+ 8015932:	4813      	ldr	r0, [pc, #76]	; (8015980 <lwip_netconn_do_write+0x114>)
+ 8015934:	f00b fe4c 	bl	80215d0 <sys_mutex_lock>
+          LWIP_ASSERT("state!", msg->conn->state != NETCONN_WRITE);
+ 8015938:	68bb      	ldr	r3, [r7, #8]
+ 801593a:	681b      	ldr	r3, [r3, #0]
+ 801593c:	785b      	ldrb	r3, [r3, #1]
+ 801593e:	2b01      	cmp	r3, #1
+ 8015940:	d110      	bne.n	8015964 <lwip_netconn_do_write+0xf8>
+ 8015942:	4b0a      	ldr	r3, [pc, #40]	; (801596c <lwip_netconn_do_write+0x100>)
+ 8015944:	f240 722c 	movw	r2, #1836	; 0x72c
+ 8015948:	490c      	ldr	r1, [pc, #48]	; (801597c <lwip_netconn_do_write+0x110>)
+ 801594a:	480a      	ldr	r0, [pc, #40]	; (8015974 <lwip_netconn_do_write+0x108>)
+ 801594c:	f00c f81c 	bl	8021988 <iprintf>
+#else /* LWIP_TCPIP_CORE_LOCKING */
+        lwip_netconn_do_writemore(msg->conn);
+#endif /* LWIP_TCPIP_CORE_LOCKING */
+        /* for both cases: if lwip_netconn_do_writemore was called, don't ACK the APIMSG
+           since lwip_netconn_do_writemore ACKs it! */
+        return;
+ 8015950:	e008      	b.n	8015964 <lwip_netconn_do_write+0xf8>
+      } else {
+        err = ERR_CONN;
+ 8015952:	23f5      	movs	r3, #245	; 0xf5
+ 8015954:	73fb      	strb	r3, [r7, #15]
+ 8015956:	e001      	b.n	801595c <lwip_netconn_do_write+0xf0>
+#else /* LWIP_TCP */
+      err = ERR_VAL;
+#endif /* LWIP_TCP */
+#if (LWIP_UDP || LWIP_RAW)
+    } else {
+      err = ERR_VAL;
+ 8015958:	23fa      	movs	r3, #250	; 0xfa
+ 801595a:	73fb      	strb	r3, [r7, #15]
+#endif /* (LWIP_UDP || LWIP_RAW) */
+    }
+  }
+  msg->err = err;
+ 801595c:	68bb      	ldr	r3, [r7, #8]
+ 801595e:	7bfa      	ldrb	r2, [r7, #15]
+ 8015960:	711a      	strb	r2, [r3, #4]
+ 8015962:	e000      	b.n	8015966 <lwip_netconn_do_write+0xfa>
+        return;
+ 8015964:	bf00      	nop
+  TCPIP_APIMSG_ACK(msg);
+}
+ 8015966:	3710      	adds	r7, #16
+ 8015968:	46bd      	mov	sp, r7
+ 801596a:	bd80      	pop	{r7, pc}
+ 801596c:	08023624 	.word	0x08023624
+ 8015970:	080239c8 	.word	0x080239c8
+ 8015974:	08023668 	.word	0x08023668
+ 8015978:	08023b50 	.word	0x08023b50
+ 801597c:	080239e4 	.word	0x080239e4
+ 8015980:	2401397c 	.word	0x2401397c
+
+08015984 <lwip_netconn_do_close>:
+ *
+ * @param m the api_msg pointing to the connection
+ */
+void
+lwip_netconn_do_close(void *m)
+{
+ 8015984:	b580      	push	{r7, lr}
+ 8015986:	b084      	sub	sp, #16
+ 8015988:	af00      	add	r7, sp, #0
+ 801598a:	6078      	str	r0, [r7, #4]
+  struct api_msg *msg = (struct api_msg *)m;
+ 801598c:	687b      	ldr	r3, [r7, #4]
+ 801598e:	60fb      	str	r3, [r7, #12]
+
+#if LWIP_TCP
+  enum netconn_state state = msg->conn->state;
+ 8015990:	68fb      	ldr	r3, [r7, #12]
+ 8015992:	681b      	ldr	r3, [r3, #0]
+ 8015994:	785b      	ldrb	r3, [r3, #1]
+ 8015996:	72fb      	strb	r3, [r7, #11]
+  /* First check if this is a TCP netconn and if it is in a correct state
+      (LISTEN doesn't support half shutdown) */
+  if ((msg->conn->pcb.tcp != NULL) &&
+ 8015998:	68fb      	ldr	r3, [r7, #12]
+ 801599a:	681b      	ldr	r3, [r3, #0]
+ 801599c:	685b      	ldr	r3, [r3, #4]
+ 801599e:	2b00      	cmp	r3, #0
+ 80159a0:	d069      	beq.n	8015a76 <lwip_netconn_do_close+0xf2>
+      (NETCONNTYPE_GROUP(msg->conn->type) == NETCONN_TCP) &&
+ 80159a2:	68fb      	ldr	r3, [r7, #12]
+ 80159a4:	681b      	ldr	r3, [r3, #0]
+ 80159a6:	781b      	ldrb	r3, [r3, #0]
+ 80159a8:	f003 03f0 	and.w	r3, r3, #240	; 0xf0
+  if ((msg->conn->pcb.tcp != NULL) &&
+ 80159ac:	2b10      	cmp	r3, #16
+ 80159ae:	d162      	bne.n	8015a76 <lwip_netconn_do_close+0xf2>
+      ((msg->msg.sd.shut == NETCONN_SHUT_RDWR) || (state != NETCONN_LISTEN))) {
+ 80159b0:	68fb      	ldr	r3, [r7, #12]
+ 80159b2:	7a1b      	ldrb	r3, [r3, #8]
+      (NETCONNTYPE_GROUP(msg->conn->type) == NETCONN_TCP) &&
+ 80159b4:	2b03      	cmp	r3, #3
+ 80159b6:	d002      	beq.n	80159be <lwip_netconn_do_close+0x3a>
+      ((msg->msg.sd.shut == NETCONN_SHUT_RDWR) || (state != NETCONN_LISTEN))) {
+ 80159b8:	7afb      	ldrb	r3, [r7, #11]
+ 80159ba:	2b02      	cmp	r3, #2
+ 80159bc:	d05b      	beq.n	8015a76 <lwip_netconn_do_close+0xf2>
+    /* Check if we are in a connected state */
+    if (state == NETCONN_CONNECT) {
+ 80159be:	7afb      	ldrb	r3, [r7, #11]
+ 80159c0:	2b03      	cmp	r3, #3
+ 80159c2:	d103      	bne.n	80159cc <lwip_netconn_do_close+0x48>
+      /* TCP connect in progress: cannot shutdown */
+      msg->err = ERR_CONN;
+ 80159c4:	68fb      	ldr	r3, [r7, #12]
+ 80159c6:	22f5      	movs	r2, #245	; 0xf5
+ 80159c8:	711a      	strb	r2, [r3, #4]
+    if (state == NETCONN_CONNECT) {
+ 80159ca:	e059      	b.n	8015a80 <lwip_netconn_do_close+0xfc>
+    } else if (state == NETCONN_WRITE) {
+ 80159cc:	7afb      	ldrb	r3, [r7, #11]
+ 80159ce:	2b01      	cmp	r3, #1
+ 80159d0:	d103      	bne.n	80159da <lwip_netconn_do_close+0x56>
+        msg->err = tcp_shutdown(msg->conn->pcb.tcp, 1, 0);
+      }
+    }
+    if (state == NETCONN_NONE) {
+#else /* LWIP_NETCONN_FULLDUPLEX */
+      msg->err = ERR_INPROGRESS;
+ 80159d2:	68fb      	ldr	r3, [r7, #12]
+ 80159d4:	22fb      	movs	r2, #251	; 0xfb
+ 80159d6:	711a      	strb	r2, [r3, #4]
+    if (state == NETCONN_CONNECT) {
+ 80159d8:	e052      	b.n	8015a80 <lwip_netconn_do_close+0xfc>
+    } else {
+#endif /* LWIP_NETCONN_FULLDUPLEX */
+      if (msg->msg.sd.shut & NETCONN_SHUT_RD) {
+ 80159da:	68fb      	ldr	r3, [r7, #12]
+ 80159dc:	7a1b      	ldrb	r3, [r3, #8]
+ 80159de:	f003 0301 	and.w	r3, r3, #1
+ 80159e2:	2b00      	cmp	r3, #0
+ 80159e4:	d004      	beq.n	80159f0 <lwip_netconn_do_close+0x6c>
+#if LWIP_NETCONN_FULLDUPLEX
+        /* Mark mboxes invalid */
+        netconn_mark_mbox_invalid(msg->conn);
+#else /* LWIP_NETCONN_FULLDUPLEX */
+        netconn_drain(msg->conn);
+ 80159e6:	68fb      	ldr	r3, [r7, #12]
+ 80159e8:	681b      	ldr	r3, [r3, #0]
+ 80159ea:	4618      	mov	r0, r3
+ 80159ec:	f7ff f8e6 	bl	8014bbc <netconn_drain>
+#endif /* LWIP_NETCONN_FULLDUPLEX */
+      }
+      LWIP_ASSERT("already writing or closing", msg->conn->current_msg == NULL);
+ 80159f0:	68fb      	ldr	r3, [r7, #12]
+ 80159f2:	681b      	ldr	r3, [r3, #0]
+ 80159f4:	6a1b      	ldr	r3, [r3, #32]
+ 80159f6:	2b00      	cmp	r3, #0
+ 80159f8:	d006      	beq.n	8015a08 <lwip_netconn_do_close+0x84>
+ 80159fa:	4b23      	ldr	r3, [pc, #140]	; (8015a88 <lwip_netconn_do_close+0x104>)
+ 80159fc:	f240 72bd 	movw	r2, #1981	; 0x7bd
+ 8015a00:	4922      	ldr	r1, [pc, #136]	; (8015a8c <lwip_netconn_do_close+0x108>)
+ 8015a02:	4823      	ldr	r0, [pc, #140]	; (8015a90 <lwip_netconn_do_close+0x10c>)
+ 8015a04:	f00b ffc0 	bl	8021988 <iprintf>
+      msg->conn->state = NETCONN_CLOSE;
+ 8015a08:	68fb      	ldr	r3, [r7, #12]
+ 8015a0a:	681b      	ldr	r3, [r3, #0]
+ 8015a0c:	2204      	movs	r2, #4
+ 8015a0e:	705a      	strb	r2, [r3, #1]
+      msg->conn->current_msg = msg;
+ 8015a10:	68fb      	ldr	r3, [r7, #12]
+ 8015a12:	681b      	ldr	r3, [r3, #0]
+ 8015a14:	68fa      	ldr	r2, [r7, #12]
+ 8015a16:	621a      	str	r2, [r3, #32]
+#if LWIP_TCPIP_CORE_LOCKING
+      if (lwip_netconn_do_close_internal(msg->conn, 0) != ERR_OK) {
+ 8015a18:	68fb      	ldr	r3, [r7, #12]
+ 8015a1a:	681b      	ldr	r3, [r3, #0]
+ 8015a1c:	2100      	movs	r1, #0
+ 8015a1e:	4618      	mov	r0, r3
+ 8015a20:	f7ff f94a 	bl	8014cb8 <lwip_netconn_do_close_internal>
+ 8015a24:	4603      	mov	r3, r0
+ 8015a26:	2b00      	cmp	r3, #0
+ 8015a28:	d029      	beq.n	8015a7e <lwip_netconn_do_close+0xfa>
+        LWIP_ASSERT("state!", msg->conn->state == NETCONN_CLOSE);
+ 8015a2a:	68fb      	ldr	r3, [r7, #12]
+ 8015a2c:	681b      	ldr	r3, [r3, #0]
+ 8015a2e:	785b      	ldrb	r3, [r3, #1]
+ 8015a30:	2b04      	cmp	r3, #4
+ 8015a32:	d006      	beq.n	8015a42 <lwip_netconn_do_close+0xbe>
+ 8015a34:	4b14      	ldr	r3, [pc, #80]	; (8015a88 <lwip_netconn_do_close+0x104>)
+ 8015a36:	f240 72c2 	movw	r2, #1986	; 0x7c2
+ 8015a3a:	4916      	ldr	r1, [pc, #88]	; (8015a94 <lwip_netconn_do_close+0x110>)
+ 8015a3c:	4814      	ldr	r0, [pc, #80]	; (8015a90 <lwip_netconn_do_close+0x10c>)
+ 8015a3e:	f00b ffa3 	bl	8021988 <iprintf>
+        UNLOCK_TCPIP_CORE();
+ 8015a42:	4815      	ldr	r0, [pc, #84]	; (8015a98 <lwip_netconn_do_close+0x114>)
+ 8015a44:	f00b fdd3 	bl	80215ee <sys_mutex_unlock>
+        sys_arch_sem_wait(LWIP_API_MSG_SEM(msg), 0);
+ 8015a48:	68fb      	ldr	r3, [r7, #12]
+ 8015a4a:	681b      	ldr	r3, [r3, #0]
+ 8015a4c:	330c      	adds	r3, #12
+ 8015a4e:	2100      	movs	r1, #0
+ 8015a50:	4618      	mov	r0, r3
+ 8015a52:	f00b fd2a 	bl	80214aa <sys_arch_sem_wait>
+        LOCK_TCPIP_CORE();
+ 8015a56:	4810      	ldr	r0, [pc, #64]	; (8015a98 <lwip_netconn_do_close+0x114>)
+ 8015a58:	f00b fdba 	bl	80215d0 <sys_mutex_lock>
+        LWIP_ASSERT("state!", msg->conn->state == NETCONN_NONE);
+ 8015a5c:	68fb      	ldr	r3, [r7, #12]
+ 8015a5e:	681b      	ldr	r3, [r3, #0]
+ 8015a60:	785b      	ldrb	r3, [r3, #1]
+ 8015a62:	2b00      	cmp	r3, #0
+ 8015a64:	d00b      	beq.n	8015a7e <lwip_netconn_do_close+0xfa>
+ 8015a66:	4b08      	ldr	r3, [pc, #32]	; (8015a88 <lwip_netconn_do_close+0x104>)
+ 8015a68:	f240 72c6 	movw	r2, #1990	; 0x7c6
+ 8015a6c:	4909      	ldr	r1, [pc, #36]	; (8015a94 <lwip_netconn_do_close+0x110>)
+ 8015a6e:	4808      	ldr	r0, [pc, #32]	; (8015a90 <lwip_netconn_do_close+0x10c>)
+ 8015a70:	f00b ff8a 	bl	8021988 <iprintf>
+      }
+#else /* LWIP_TCPIP_CORE_LOCKING */
+      lwip_netconn_do_close_internal(msg->conn);
+#endif /* LWIP_TCPIP_CORE_LOCKING */
+      /* for tcp netconns, lwip_netconn_do_close_internal ACKs the message */
+      return;
+ 8015a74:	e003      	b.n	8015a7e <lwip_netconn_do_close+0xfa>
+    }
+  } else
+#endif /* LWIP_TCP */
+  {
+    msg->err = ERR_CONN;
+ 8015a76:	68fb      	ldr	r3, [r7, #12]
+ 8015a78:	22f5      	movs	r2, #245	; 0xf5
+ 8015a7a:	711a      	strb	r2, [r3, #4]
+ 8015a7c:	e000      	b.n	8015a80 <lwip_netconn_do_close+0xfc>
+      return;
+ 8015a7e:	bf00      	nop
+  }
+  TCPIP_APIMSG_ACK(msg);
+}
+ 8015a80:	3710      	adds	r7, #16
+ 8015a82:	46bd      	mov	sp, r7
+ 8015a84:	bd80      	pop	{r7, pc}
+ 8015a86:	bf00      	nop
+ 8015a88:	08023624 	.word	0x08023624
+ 8015a8c:	080239c8 	.word	0x080239c8
+ 8015a90:	08023668 	.word	0x08023668
+ 8015a94:	080239e4 	.word	0x080239e4
+ 8015a98:	2401397c 	.word	0x2401397c
+
+08015a9c <netbuf_delete>:
+ *
+ * @param buf pointer to a netbuf allocated by netbuf_new()
+ */
+void
+netbuf_delete(struct netbuf *buf)
+{
+ 8015a9c:	b580      	push	{r7, lr}
+ 8015a9e:	b082      	sub	sp, #8
+ 8015aa0:	af00      	add	r7, sp, #0
+ 8015aa2:	6078      	str	r0, [r7, #4]
+  if (buf != NULL) {
+ 8015aa4:	687b      	ldr	r3, [r7, #4]
+ 8015aa6:	2b00      	cmp	r3, #0
+ 8015aa8:	d013      	beq.n	8015ad2 <netbuf_delete+0x36>
+    if (buf->p != NULL) {
+ 8015aaa:	687b      	ldr	r3, [r7, #4]
+ 8015aac:	681b      	ldr	r3, [r3, #0]
+ 8015aae:	2b00      	cmp	r3, #0
+ 8015ab0:	d00b      	beq.n	8015aca <netbuf_delete+0x2e>
+      pbuf_free(buf->p);
+ 8015ab2:	687b      	ldr	r3, [r7, #4]
+ 8015ab4:	681b      	ldr	r3, [r3, #0]
+ 8015ab6:	4618      	mov	r0, r3
+ 8015ab8:	f002 f81e 	bl	8017af8 <pbuf_free>
+      buf->p = buf->ptr = NULL;
+ 8015abc:	687b      	ldr	r3, [r7, #4]
+ 8015abe:	2200      	movs	r2, #0
+ 8015ac0:	605a      	str	r2, [r3, #4]
+ 8015ac2:	687b      	ldr	r3, [r7, #4]
+ 8015ac4:	685a      	ldr	r2, [r3, #4]
+ 8015ac6:	687b      	ldr	r3, [r7, #4]
+ 8015ac8:	601a      	str	r2, [r3, #0]
+    }
+    memp_free(MEMP_NETBUF, buf);
+ 8015aca:	6879      	ldr	r1, [r7, #4]
+ 8015acc:	2006      	movs	r0, #6
+ 8015ace:	f001 f875 	bl	8016bbc <memp_free>
+  }
+}
+ 8015ad2:	bf00      	nop
+ 8015ad4:	3708      	adds	r7, #8
+ 8015ad6:	46bd      	mov	sp, r7
+ 8015ad8:	bd80      	pop	{r7, pc}
+	...
+
+08015adc <netbuf_data>:
+ * @return ERR_OK if the information was retrieved,
+ *         ERR_BUF on error.
+ */
+err_t
+netbuf_data(struct netbuf *buf, void **dataptr, u16_t *len)
+{
+ 8015adc:	b580      	push	{r7, lr}
+ 8015ade:	b084      	sub	sp, #16
+ 8015ae0:	af00      	add	r7, sp, #0
+ 8015ae2:	60f8      	str	r0, [r7, #12]
+ 8015ae4:	60b9      	str	r1, [r7, #8]
+ 8015ae6:	607a      	str	r2, [r7, #4]
+  LWIP_ERROR("netbuf_data: invalid buf", (buf != NULL), return ERR_ARG;);
+ 8015ae8:	68fb      	ldr	r3, [r7, #12]
+ 8015aea:	2b00      	cmp	r3, #0
+ 8015aec:	d108      	bne.n	8015b00 <netbuf_data+0x24>
+ 8015aee:	4b1b      	ldr	r3, [pc, #108]	; (8015b5c <netbuf_data+0x80>)
+ 8015af0:	22c6      	movs	r2, #198	; 0xc6
+ 8015af2:	491b      	ldr	r1, [pc, #108]	; (8015b60 <netbuf_data+0x84>)
+ 8015af4:	481b      	ldr	r0, [pc, #108]	; (8015b64 <netbuf_data+0x88>)
+ 8015af6:	f00b ff47 	bl	8021988 <iprintf>
+ 8015afa:	f06f 030f 	mvn.w	r3, #15
+ 8015afe:	e029      	b.n	8015b54 <netbuf_data+0x78>
+  LWIP_ERROR("netbuf_data: invalid dataptr", (dataptr != NULL), return ERR_ARG;);
+ 8015b00:	68bb      	ldr	r3, [r7, #8]
+ 8015b02:	2b00      	cmp	r3, #0
+ 8015b04:	d108      	bne.n	8015b18 <netbuf_data+0x3c>
+ 8015b06:	4b15      	ldr	r3, [pc, #84]	; (8015b5c <netbuf_data+0x80>)
+ 8015b08:	22c7      	movs	r2, #199	; 0xc7
+ 8015b0a:	4917      	ldr	r1, [pc, #92]	; (8015b68 <netbuf_data+0x8c>)
+ 8015b0c:	4815      	ldr	r0, [pc, #84]	; (8015b64 <netbuf_data+0x88>)
+ 8015b0e:	f00b ff3b 	bl	8021988 <iprintf>
+ 8015b12:	f06f 030f 	mvn.w	r3, #15
+ 8015b16:	e01d      	b.n	8015b54 <netbuf_data+0x78>
+  LWIP_ERROR("netbuf_data: invalid len", (len != NULL), return ERR_ARG;);
+ 8015b18:	687b      	ldr	r3, [r7, #4]
+ 8015b1a:	2b00      	cmp	r3, #0
+ 8015b1c:	d108      	bne.n	8015b30 <netbuf_data+0x54>
+ 8015b1e:	4b0f      	ldr	r3, [pc, #60]	; (8015b5c <netbuf_data+0x80>)
+ 8015b20:	22c8      	movs	r2, #200	; 0xc8
+ 8015b22:	4912      	ldr	r1, [pc, #72]	; (8015b6c <netbuf_data+0x90>)
+ 8015b24:	480f      	ldr	r0, [pc, #60]	; (8015b64 <netbuf_data+0x88>)
+ 8015b26:	f00b ff2f 	bl	8021988 <iprintf>
+ 8015b2a:	f06f 030f 	mvn.w	r3, #15
+ 8015b2e:	e011      	b.n	8015b54 <netbuf_data+0x78>
+
+  if (buf->ptr == NULL) {
+ 8015b30:	68fb      	ldr	r3, [r7, #12]
+ 8015b32:	685b      	ldr	r3, [r3, #4]
+ 8015b34:	2b00      	cmp	r3, #0
+ 8015b36:	d102      	bne.n	8015b3e <netbuf_data+0x62>
+    return ERR_BUF;
+ 8015b38:	f06f 0301 	mvn.w	r3, #1
+ 8015b3c:	e00a      	b.n	8015b54 <netbuf_data+0x78>
+  }
+  *dataptr = buf->ptr->payload;
+ 8015b3e:	68fb      	ldr	r3, [r7, #12]
+ 8015b40:	685b      	ldr	r3, [r3, #4]
+ 8015b42:	685a      	ldr	r2, [r3, #4]
+ 8015b44:	68bb      	ldr	r3, [r7, #8]
+ 8015b46:	601a      	str	r2, [r3, #0]
+  *len = buf->ptr->len;
+ 8015b48:	68fb      	ldr	r3, [r7, #12]
+ 8015b4a:	685b      	ldr	r3, [r3, #4]
+ 8015b4c:	895a      	ldrh	r2, [r3, #10]
+ 8015b4e:	687b      	ldr	r3, [r7, #4]
+ 8015b50:	801a      	strh	r2, [r3, #0]
+  return ERR_OK;
+ 8015b52:	2300      	movs	r3, #0
+}
+ 8015b54:	4618      	mov	r0, r3
+ 8015b56:	3710      	adds	r7, #16
+ 8015b58:	46bd      	mov	sp, r7
+ 8015b5a:	bd80      	pop	{r7, pc}
+ 8015b5c:	08023b7c 	.word	0x08023b7c
+ 8015b60:	08023c84 	.word	0x08023c84
+ 8015b64:	08023bcc 	.word	0x08023bcc
+ 8015b68:	08023ca0 	.word	0x08023ca0
+ 8015b6c:	08023cc0 	.word	0x08023cc0
+
+08015b70 <netbuf_next>:
+ *         1  if moved to the next part but now there is no next part
+ *         0  if moved to the next part and there are still more parts
+ */
+s8_t
+netbuf_next(struct netbuf *buf)
+{
+ 8015b70:	b580      	push	{r7, lr}
+ 8015b72:	b082      	sub	sp, #8
+ 8015b74:	af00      	add	r7, sp, #0
+ 8015b76:	6078      	str	r0, [r7, #4]
+  LWIP_ERROR("netbuf_next: invalid buf", (buf != NULL), return -1;);
+ 8015b78:	687b      	ldr	r3, [r7, #4]
+ 8015b7a:	2b00      	cmp	r3, #0
+ 8015b7c:	d108      	bne.n	8015b90 <netbuf_next+0x20>
+ 8015b7e:	4b11      	ldr	r3, [pc, #68]	; (8015bc4 <netbuf_next+0x54>)
+ 8015b80:	22e0      	movs	r2, #224	; 0xe0
+ 8015b82:	4911      	ldr	r1, [pc, #68]	; (8015bc8 <netbuf_next+0x58>)
+ 8015b84:	4811      	ldr	r0, [pc, #68]	; (8015bcc <netbuf_next+0x5c>)
+ 8015b86:	f00b feff 	bl	8021988 <iprintf>
+ 8015b8a:	f04f 33ff 	mov.w	r3, #4294967295
+ 8015b8e:	e014      	b.n	8015bba <netbuf_next+0x4a>
+  if (buf->ptr->next == NULL) {
+ 8015b90:	687b      	ldr	r3, [r7, #4]
+ 8015b92:	685b      	ldr	r3, [r3, #4]
+ 8015b94:	681b      	ldr	r3, [r3, #0]
+ 8015b96:	2b00      	cmp	r3, #0
+ 8015b98:	d102      	bne.n	8015ba0 <netbuf_next+0x30>
+    return -1;
+ 8015b9a:	f04f 33ff 	mov.w	r3, #4294967295
+ 8015b9e:	e00c      	b.n	8015bba <netbuf_next+0x4a>
+  }
+  buf->ptr = buf->ptr->next;
+ 8015ba0:	687b      	ldr	r3, [r7, #4]
+ 8015ba2:	685b      	ldr	r3, [r3, #4]
+ 8015ba4:	681a      	ldr	r2, [r3, #0]
+ 8015ba6:	687b      	ldr	r3, [r7, #4]
+ 8015ba8:	605a      	str	r2, [r3, #4]
+  if (buf->ptr->next == NULL) {
+ 8015baa:	687b      	ldr	r3, [r7, #4]
+ 8015bac:	685b      	ldr	r3, [r3, #4]
+ 8015bae:	681b      	ldr	r3, [r3, #0]
+ 8015bb0:	2b00      	cmp	r3, #0
+ 8015bb2:	d101      	bne.n	8015bb8 <netbuf_next+0x48>
+    return 1;
+ 8015bb4:	2301      	movs	r3, #1
+ 8015bb6:	e000      	b.n	8015bba <netbuf_next+0x4a>
+  }
+  return 0;
+ 8015bb8:	2300      	movs	r3, #0
+}
+ 8015bba:	4618      	mov	r0, r3
+ 8015bbc:	3708      	adds	r7, #8
+ 8015bbe:	46bd      	mov	sp, r7
+ 8015bc0:	bd80      	pop	{r7, pc}
+ 8015bc2:	bf00      	nop
+ 8015bc4:	08023b7c 	.word	0x08023b7c
+ 8015bc8:	08023cdc 	.word	0x08023cdc
+ 8015bcc:	08023bcc 	.word	0x08023bcc
+
+08015bd0 <tcpip_timeouts_mbox_fetch>:
+ * @param mbox the mbox to fetch the message from
+ * @param msg the place to store the message
+ */
+static void
+tcpip_timeouts_mbox_fetch(sys_mbox_t *mbox, void **msg)
+{
+ 8015bd0:	b580      	push	{r7, lr}
+ 8015bd2:	b084      	sub	sp, #16
+ 8015bd4:	af00      	add	r7, sp, #0
+ 8015bd6:	6078      	str	r0, [r7, #4]
+ 8015bd8:	6039      	str	r1, [r7, #0]
+  u32_t sleeptime, res;
+
+again:
+  LWIP_ASSERT_CORE_LOCKED();
+
+  sleeptime = sys_timeouts_sleeptime();
+ 8015bda:	f008 fcb3 	bl	801e544 <sys_timeouts_sleeptime>
+ 8015bde:	60f8      	str	r0, [r7, #12]
+  if (sleeptime == SYS_TIMEOUTS_SLEEPTIME_INFINITE) {
+ 8015be0:	68fb      	ldr	r3, [r7, #12]
+ 8015be2:	f1b3 3fff 	cmp.w	r3, #4294967295
+ 8015be6:	d10b      	bne.n	8015c00 <tcpip_timeouts_mbox_fetch+0x30>
+    UNLOCK_TCPIP_CORE();
+ 8015be8:	4813      	ldr	r0, [pc, #76]	; (8015c38 <tcpip_timeouts_mbox_fetch+0x68>)
+ 8015bea:	f00b fd00 	bl	80215ee <sys_mutex_unlock>
+    sys_arch_mbox_fetch(mbox, msg, 0);
+ 8015bee:	2200      	movs	r2, #0
+ 8015bf0:	6839      	ldr	r1, [r7, #0]
+ 8015bf2:	6878      	ldr	r0, [r7, #4]
+ 8015bf4:	f00b fbb8 	bl	8021368 <sys_arch_mbox_fetch>
+    LOCK_TCPIP_CORE();
+ 8015bf8:	480f      	ldr	r0, [pc, #60]	; (8015c38 <tcpip_timeouts_mbox_fetch+0x68>)
+ 8015bfa:	f00b fce9 	bl	80215d0 <sys_mutex_lock>
+    return;
+ 8015bfe:	e018      	b.n	8015c32 <tcpip_timeouts_mbox_fetch+0x62>
+  } else if (sleeptime == 0) {
+ 8015c00:	68fb      	ldr	r3, [r7, #12]
+ 8015c02:	2b00      	cmp	r3, #0
+ 8015c04:	d102      	bne.n	8015c0c <tcpip_timeouts_mbox_fetch+0x3c>
+    sys_check_timeouts();
+ 8015c06:	f008 fc63 	bl	801e4d0 <sys_check_timeouts>
+    /* We try again to fetch a message from the mbox. */
+    goto again;
+ 8015c0a:	e7e6      	b.n	8015bda <tcpip_timeouts_mbox_fetch+0xa>
+  }
+
+  UNLOCK_TCPIP_CORE();
+ 8015c0c:	480a      	ldr	r0, [pc, #40]	; (8015c38 <tcpip_timeouts_mbox_fetch+0x68>)
+ 8015c0e:	f00b fcee 	bl	80215ee <sys_mutex_unlock>
+  res = sys_arch_mbox_fetch(mbox, msg, sleeptime);
+ 8015c12:	68fa      	ldr	r2, [r7, #12]
+ 8015c14:	6839      	ldr	r1, [r7, #0]
+ 8015c16:	6878      	ldr	r0, [r7, #4]
+ 8015c18:	f00b fba6 	bl	8021368 <sys_arch_mbox_fetch>
+ 8015c1c:	60b8      	str	r0, [r7, #8]
+  LOCK_TCPIP_CORE();
+ 8015c1e:	4806      	ldr	r0, [pc, #24]	; (8015c38 <tcpip_timeouts_mbox_fetch+0x68>)
+ 8015c20:	f00b fcd6 	bl	80215d0 <sys_mutex_lock>
+  if (res == SYS_ARCH_TIMEOUT) {
+ 8015c24:	68bb      	ldr	r3, [r7, #8]
+ 8015c26:	f1b3 3fff 	cmp.w	r3, #4294967295
+ 8015c2a:	d102      	bne.n	8015c32 <tcpip_timeouts_mbox_fetch+0x62>
+    /* If a SYS_ARCH_TIMEOUT value is returned, a timeout occurred
+       before a message could be fetched. */
+    sys_check_timeouts();
+ 8015c2c:	f008 fc50 	bl	801e4d0 <sys_check_timeouts>
+    /* We try again to fetch a message from the mbox. */
+    goto again;
+ 8015c30:	e7d3      	b.n	8015bda <tcpip_timeouts_mbox_fetch+0xa>
+  }
+}
+ 8015c32:	3710      	adds	r7, #16
+ 8015c34:	46bd      	mov	sp, r7
+ 8015c36:	bd80      	pop	{r7, pc}
+ 8015c38:	2401397c 	.word	0x2401397c
+
+08015c3c <tcpip_thread>:
+ *
+ * @param arg unused argument
+ */
+static void
+tcpip_thread(void *arg)
+{
+ 8015c3c:	b580      	push	{r7, lr}
+ 8015c3e:	b084      	sub	sp, #16
+ 8015c40:	af00      	add	r7, sp, #0
+ 8015c42:	6078      	str	r0, [r7, #4]
+  struct tcpip_msg *msg;
+  LWIP_UNUSED_ARG(arg);
+
+  LWIP_MARK_TCPIP_THREAD();
+
+  LOCK_TCPIP_CORE();
+ 8015c44:	4810      	ldr	r0, [pc, #64]	; (8015c88 <tcpip_thread+0x4c>)
+ 8015c46:	f00b fcc3 	bl	80215d0 <sys_mutex_lock>
+  if (tcpip_init_done != NULL) {
+ 8015c4a:	4b10      	ldr	r3, [pc, #64]	; (8015c8c <tcpip_thread+0x50>)
+ 8015c4c:	681b      	ldr	r3, [r3, #0]
+ 8015c4e:	2b00      	cmp	r3, #0
+ 8015c50:	d005      	beq.n	8015c5e <tcpip_thread+0x22>
+    tcpip_init_done(tcpip_init_done_arg);
+ 8015c52:	4b0e      	ldr	r3, [pc, #56]	; (8015c8c <tcpip_thread+0x50>)
+ 8015c54:	681b      	ldr	r3, [r3, #0]
+ 8015c56:	4a0e      	ldr	r2, [pc, #56]	; (8015c90 <tcpip_thread+0x54>)
+ 8015c58:	6812      	ldr	r2, [r2, #0]
+ 8015c5a:	4610      	mov	r0, r2
+ 8015c5c:	4798      	blx	r3
+  }
+
+  while (1) {                          /* MAIN Loop */
+    LWIP_TCPIP_THREAD_ALIVE();
+    /* wait for a message, timeouts are processed while waiting */
+    TCPIP_MBOX_FETCH(&tcpip_mbox, (void **)&msg);
+ 8015c5e:	f107 030c 	add.w	r3, r7, #12
+ 8015c62:	4619      	mov	r1, r3
+ 8015c64:	480b      	ldr	r0, [pc, #44]	; (8015c94 <tcpip_thread+0x58>)
+ 8015c66:	f7ff ffb3 	bl	8015bd0 <tcpip_timeouts_mbox_fetch>
+    if (msg == NULL) {
+ 8015c6a:	68fb      	ldr	r3, [r7, #12]
+ 8015c6c:	2b00      	cmp	r3, #0
+ 8015c6e:	d106      	bne.n	8015c7e <tcpip_thread+0x42>
+      LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip_thread: invalid message: NULL\n"));
+      LWIP_ASSERT("tcpip_thread: invalid message", 0);
+ 8015c70:	4b09      	ldr	r3, [pc, #36]	; (8015c98 <tcpip_thread+0x5c>)
+ 8015c72:	2291      	movs	r2, #145	; 0x91
+ 8015c74:	4909      	ldr	r1, [pc, #36]	; (8015c9c <tcpip_thread+0x60>)
+ 8015c76:	480a      	ldr	r0, [pc, #40]	; (8015ca0 <tcpip_thread+0x64>)
+ 8015c78:	f00b fe86 	bl	8021988 <iprintf>
+      continue;
+ 8015c7c:	e003      	b.n	8015c86 <tcpip_thread+0x4a>
+    }
+    tcpip_thread_handle_msg(msg);
+ 8015c7e:	68fb      	ldr	r3, [r7, #12]
+ 8015c80:	4618      	mov	r0, r3
+ 8015c82:	f000 f80f 	bl	8015ca4 <tcpip_thread_handle_msg>
+    TCPIP_MBOX_FETCH(&tcpip_mbox, (void **)&msg);
+ 8015c86:	e7ea      	b.n	8015c5e <tcpip_thread+0x22>
+ 8015c88:	2401397c 	.word	0x2401397c
+ 8015c8c:	24013970 	.word	0x24013970
+ 8015c90:	24013974 	.word	0x24013974
+ 8015c94:	24013978 	.word	0x24013978
+ 8015c98:	08023d14 	.word	0x08023d14
+ 8015c9c:	08023d44 	.word	0x08023d44
+ 8015ca0:	08023d64 	.word	0x08023d64
+
+08015ca4 <tcpip_thread_handle_msg>:
+/* Handle a single tcpip_msg
+ * This is in its own function for access by tests only.
+ */
+static void
+tcpip_thread_handle_msg(struct tcpip_msg *msg)
+{
+ 8015ca4:	b580      	push	{r7, lr}
+ 8015ca6:	b082      	sub	sp, #8
+ 8015ca8:	af00      	add	r7, sp, #0
+ 8015caa:	6078      	str	r0, [r7, #4]
+  switch (msg->type) {
+ 8015cac:	687b      	ldr	r3, [r7, #4]
+ 8015cae:	781b      	ldrb	r3, [r3, #0]
+ 8015cb0:	2b02      	cmp	r3, #2
+ 8015cb2:	d026      	beq.n	8015d02 <tcpip_thread_handle_msg+0x5e>
+ 8015cb4:	2b02      	cmp	r3, #2
+ 8015cb6:	dc2b      	bgt.n	8015d10 <tcpip_thread_handle_msg+0x6c>
+ 8015cb8:	2b00      	cmp	r3, #0
+ 8015cba:	d002      	beq.n	8015cc2 <tcpip_thread_handle_msg+0x1e>
+ 8015cbc:	2b01      	cmp	r3, #1
+ 8015cbe:	d015      	beq.n	8015cec <tcpip_thread_handle_msg+0x48>
+ 8015cc0:	e026      	b.n	8015d10 <tcpip_thread_handle_msg+0x6c>
+#endif /* !LWIP_TCPIP_CORE_LOCKING */
+
+#if !LWIP_TCPIP_CORE_LOCKING_INPUT
+    case TCPIP_MSG_INPKT:
+      LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip_thread: PACKET %p\n", (void *)msg));
+      if (msg->msg.inp.input_fn(msg->msg.inp.p, msg->msg.inp.netif) != ERR_OK) {
+ 8015cc2:	687b      	ldr	r3, [r7, #4]
+ 8015cc4:	68db      	ldr	r3, [r3, #12]
+ 8015cc6:	687a      	ldr	r2, [r7, #4]
+ 8015cc8:	6850      	ldr	r0, [r2, #4]
+ 8015cca:	687a      	ldr	r2, [r7, #4]
+ 8015ccc:	6892      	ldr	r2, [r2, #8]
+ 8015cce:	4611      	mov	r1, r2
+ 8015cd0:	4798      	blx	r3
+ 8015cd2:	4603      	mov	r3, r0
+ 8015cd4:	2b00      	cmp	r3, #0
+ 8015cd6:	d004      	beq.n	8015ce2 <tcpip_thread_handle_msg+0x3e>
+        pbuf_free(msg->msg.inp.p);
+ 8015cd8:	687b      	ldr	r3, [r7, #4]
+ 8015cda:	685b      	ldr	r3, [r3, #4]
+ 8015cdc:	4618      	mov	r0, r3
+ 8015cde:	f001 ff0b 	bl	8017af8 <pbuf_free>
+      }
+      memp_free(MEMP_TCPIP_MSG_INPKT, msg);
+ 8015ce2:	6879      	ldr	r1, [r7, #4]
+ 8015ce4:	2009      	movs	r0, #9
+ 8015ce6:	f000 ff69 	bl	8016bbc <memp_free>
+      break;
+ 8015cea:	e018      	b.n	8015d1e <tcpip_thread_handle_msg+0x7a>
+      break;
+#endif /* LWIP_TCPIP_TIMEOUT && LWIP_TIMERS */
+
+    case TCPIP_MSG_CALLBACK:
+      LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip_thread: CALLBACK %p\n", (void *)msg));
+      msg->msg.cb.function(msg->msg.cb.ctx);
+ 8015cec:	687b      	ldr	r3, [r7, #4]
+ 8015cee:	685b      	ldr	r3, [r3, #4]
+ 8015cf0:	687a      	ldr	r2, [r7, #4]
+ 8015cf2:	6892      	ldr	r2, [r2, #8]
+ 8015cf4:	4610      	mov	r0, r2
+ 8015cf6:	4798      	blx	r3
+      memp_free(MEMP_TCPIP_MSG_API, msg);
+ 8015cf8:	6879      	ldr	r1, [r7, #4]
+ 8015cfa:	2008      	movs	r0, #8
+ 8015cfc:	f000 ff5e 	bl	8016bbc <memp_free>
+      break;
+ 8015d00:	e00d      	b.n	8015d1e <tcpip_thread_handle_msg+0x7a>
+
+    case TCPIP_MSG_CALLBACK_STATIC:
+      LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip_thread: CALLBACK_STATIC %p\n", (void *)msg));
+      msg->msg.cb.function(msg->msg.cb.ctx);
+ 8015d02:	687b      	ldr	r3, [r7, #4]
+ 8015d04:	685b      	ldr	r3, [r3, #4]
+ 8015d06:	687a      	ldr	r2, [r7, #4]
+ 8015d08:	6892      	ldr	r2, [r2, #8]
+ 8015d0a:	4610      	mov	r0, r2
+ 8015d0c:	4798      	blx	r3
+      break;
+ 8015d0e:	e006      	b.n	8015d1e <tcpip_thread_handle_msg+0x7a>
+
+    default:
+      LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip_thread: invalid message: %d\n", msg->type));
+      LWIP_ASSERT("tcpip_thread: invalid message", 0);
+ 8015d10:	4b05      	ldr	r3, [pc, #20]	; (8015d28 <tcpip_thread_handle_msg+0x84>)
+ 8015d12:	22cf      	movs	r2, #207	; 0xcf
+ 8015d14:	4905      	ldr	r1, [pc, #20]	; (8015d2c <tcpip_thread_handle_msg+0x88>)
+ 8015d16:	4806      	ldr	r0, [pc, #24]	; (8015d30 <tcpip_thread_handle_msg+0x8c>)
+ 8015d18:	f00b fe36 	bl	8021988 <iprintf>
+      break;
+ 8015d1c:	bf00      	nop
+  }
+}
+ 8015d1e:	bf00      	nop
+ 8015d20:	3708      	adds	r7, #8
+ 8015d22:	46bd      	mov	sp, r7
+ 8015d24:	bd80      	pop	{r7, pc}
+ 8015d26:	bf00      	nop
+ 8015d28:	08023d14 	.word	0x08023d14
+ 8015d2c:	08023d44 	.word	0x08023d44
+ 8015d30:	08023d64 	.word	0x08023d64
+
+08015d34 <tcpip_inpkt>:
+ * @param inp the network interface on which the packet was received
+ * @param input_fn input function to call
+ */
+err_t
+tcpip_inpkt(struct pbuf *p, struct netif *inp, netif_input_fn input_fn)
+{
+ 8015d34:	b580      	push	{r7, lr}
+ 8015d36:	b086      	sub	sp, #24
+ 8015d38:	af00      	add	r7, sp, #0
+ 8015d3a:	60f8      	str	r0, [r7, #12]
+ 8015d3c:	60b9      	str	r1, [r7, #8]
+ 8015d3e:	607a      	str	r2, [r7, #4]
+  UNLOCK_TCPIP_CORE();
+  return ret;
+#else /* LWIP_TCPIP_CORE_LOCKING_INPUT */
+  struct tcpip_msg *msg;
+
+  LWIP_ASSERT("Invalid mbox", sys_mbox_valid_val(tcpip_mbox));
+ 8015d40:	481a      	ldr	r0, [pc, #104]	; (8015dac <tcpip_inpkt+0x78>)
+ 8015d42:	f00b fb6c 	bl	802141e <sys_mbox_valid>
+ 8015d46:	4603      	mov	r3, r0
+ 8015d48:	2b00      	cmp	r3, #0
+ 8015d4a:	d105      	bne.n	8015d58 <tcpip_inpkt+0x24>
+ 8015d4c:	4b18      	ldr	r3, [pc, #96]	; (8015db0 <tcpip_inpkt+0x7c>)
+ 8015d4e:	22fc      	movs	r2, #252	; 0xfc
+ 8015d50:	4918      	ldr	r1, [pc, #96]	; (8015db4 <tcpip_inpkt+0x80>)
+ 8015d52:	4819      	ldr	r0, [pc, #100]	; (8015db8 <tcpip_inpkt+0x84>)
+ 8015d54:	f00b fe18 	bl	8021988 <iprintf>
+
+  msg = (struct tcpip_msg *)memp_malloc(MEMP_TCPIP_MSG_INPKT);
+ 8015d58:	2009      	movs	r0, #9
+ 8015d5a:	f000 feb9 	bl	8016ad0 <memp_malloc>
+ 8015d5e:	6178      	str	r0, [r7, #20]
+  if (msg == NULL) {
+ 8015d60:	697b      	ldr	r3, [r7, #20]
+ 8015d62:	2b00      	cmp	r3, #0
+ 8015d64:	d102      	bne.n	8015d6c <tcpip_inpkt+0x38>
+    return ERR_MEM;
+ 8015d66:	f04f 33ff 	mov.w	r3, #4294967295
+ 8015d6a:	e01a      	b.n	8015da2 <tcpip_inpkt+0x6e>
+  }
+
+  msg->type = TCPIP_MSG_INPKT;
+ 8015d6c:	697b      	ldr	r3, [r7, #20]
+ 8015d6e:	2200      	movs	r2, #0
+ 8015d70:	701a      	strb	r2, [r3, #0]
+  msg->msg.inp.p = p;
+ 8015d72:	697b      	ldr	r3, [r7, #20]
+ 8015d74:	68fa      	ldr	r2, [r7, #12]
+ 8015d76:	605a      	str	r2, [r3, #4]
+  msg->msg.inp.netif = inp;
+ 8015d78:	697b      	ldr	r3, [r7, #20]
+ 8015d7a:	68ba      	ldr	r2, [r7, #8]
+ 8015d7c:	609a      	str	r2, [r3, #8]
+  msg->msg.inp.input_fn = input_fn;
+ 8015d7e:	697b      	ldr	r3, [r7, #20]
+ 8015d80:	687a      	ldr	r2, [r7, #4]
+ 8015d82:	60da      	str	r2, [r3, #12]
+  if (sys_mbox_trypost(&tcpip_mbox, msg) != ERR_OK) {
+ 8015d84:	6979      	ldr	r1, [r7, #20]
+ 8015d86:	4809      	ldr	r0, [pc, #36]	; (8015dac <tcpip_inpkt+0x78>)
+ 8015d88:	f00b fad4 	bl	8021334 <sys_mbox_trypost>
+ 8015d8c:	4603      	mov	r3, r0
+ 8015d8e:	2b00      	cmp	r3, #0
+ 8015d90:	d006      	beq.n	8015da0 <tcpip_inpkt+0x6c>
+    memp_free(MEMP_TCPIP_MSG_INPKT, msg);
+ 8015d92:	6979      	ldr	r1, [r7, #20]
+ 8015d94:	2009      	movs	r0, #9
+ 8015d96:	f000 ff11 	bl	8016bbc <memp_free>
+    return ERR_MEM;
+ 8015d9a:	f04f 33ff 	mov.w	r3, #4294967295
+ 8015d9e:	e000      	b.n	8015da2 <tcpip_inpkt+0x6e>
+  }
+  return ERR_OK;
+ 8015da0:	2300      	movs	r3, #0
+#endif /* LWIP_TCPIP_CORE_LOCKING_INPUT */
+}
+ 8015da2:	4618      	mov	r0, r3
+ 8015da4:	3718      	adds	r7, #24
+ 8015da6:	46bd      	mov	sp, r7
+ 8015da8:	bd80      	pop	{r7, pc}
+ 8015daa:	bf00      	nop
+ 8015dac:	24013978 	.word	0x24013978
+ 8015db0:	08023d14 	.word	0x08023d14
+ 8015db4:	08023d8c 	.word	0x08023d8c
+ 8015db8:	08023d64 	.word	0x08023d64
+
+08015dbc <tcpip_input>:
+ *          NETIF_FLAG_ETHERNET flags)
+ * @param inp the network interface on which the packet was received
+ */
+err_t
+tcpip_input(struct pbuf *p, struct netif *inp)
+{
+ 8015dbc:	b580      	push	{r7, lr}
+ 8015dbe:	b082      	sub	sp, #8
+ 8015dc0:	af00      	add	r7, sp, #0
+ 8015dc2:	6078      	str	r0, [r7, #4]
+ 8015dc4:	6039      	str	r1, [r7, #0]
+#if LWIP_ETHERNET
+  if (inp->flags & (NETIF_FLAG_ETHARP | NETIF_FLAG_ETHERNET)) {
+ 8015dc6:	683b      	ldr	r3, [r7, #0]
+ 8015dc8:	f893 302d 	ldrb.w	r3, [r3, #45]	; 0x2d
+ 8015dcc:	f003 0318 	and.w	r3, r3, #24
+ 8015dd0:	2b00      	cmp	r3, #0
+ 8015dd2:	d006      	beq.n	8015de2 <tcpip_input+0x26>
+    return tcpip_inpkt(p, inp, ethernet_input);
+ 8015dd4:	4a08      	ldr	r2, [pc, #32]	; (8015df8 <tcpip_input+0x3c>)
+ 8015dd6:	6839      	ldr	r1, [r7, #0]
+ 8015dd8:	6878      	ldr	r0, [r7, #4]
+ 8015dda:	f7ff ffab 	bl	8015d34 <tcpip_inpkt>
+ 8015dde:	4603      	mov	r3, r0
+ 8015de0:	e005      	b.n	8015dee <tcpip_input+0x32>
+  } else
+#endif /* LWIP_ETHERNET */
+    return tcpip_inpkt(p, inp, ip_input);
+ 8015de2:	4a06      	ldr	r2, [pc, #24]	; (8015dfc <tcpip_input+0x40>)
+ 8015de4:	6839      	ldr	r1, [r7, #0]
+ 8015de6:	6878      	ldr	r0, [r7, #4]
+ 8015de8:	f7ff ffa4 	bl	8015d34 <tcpip_inpkt>
+ 8015dec:	4603      	mov	r3, r0
+}
+ 8015dee:	4618      	mov	r0, r3
+ 8015df0:	3708      	adds	r7, #8
+ 8015df2:	46bd      	mov	sp, r7
+ 8015df4:	bd80      	pop	{r7, pc}
+ 8015df6:	bf00      	nop
+ 8015df8:	08021121 	.word	0x08021121
+ 8015dfc:	08020029 	.word	0x08020029
+
+08015e00 <tcpip_try_callback>:
+ *
+ * @see tcpip_callback
+ */
+err_t
+tcpip_try_callback(tcpip_callback_fn function, void *ctx)
+{
+ 8015e00:	b580      	push	{r7, lr}
+ 8015e02:	b084      	sub	sp, #16
+ 8015e04:	af00      	add	r7, sp, #0
+ 8015e06:	6078      	str	r0, [r7, #4]
+ 8015e08:	6039      	str	r1, [r7, #0]
+  struct tcpip_msg *msg;
+
+  LWIP_ASSERT("Invalid mbox", sys_mbox_valid_val(tcpip_mbox));
+ 8015e0a:	4819      	ldr	r0, [pc, #100]	; (8015e70 <tcpip_try_callback+0x70>)
+ 8015e0c:	f00b fb07 	bl	802141e <sys_mbox_valid>
+ 8015e10:	4603      	mov	r3, r0
+ 8015e12:	2b00      	cmp	r3, #0
+ 8015e14:	d106      	bne.n	8015e24 <tcpip_try_callback+0x24>
+ 8015e16:	4b17      	ldr	r3, [pc, #92]	; (8015e74 <tcpip_try_callback+0x74>)
+ 8015e18:	f240 125d 	movw	r2, #349	; 0x15d
+ 8015e1c:	4916      	ldr	r1, [pc, #88]	; (8015e78 <tcpip_try_callback+0x78>)
+ 8015e1e:	4817      	ldr	r0, [pc, #92]	; (8015e7c <tcpip_try_callback+0x7c>)
+ 8015e20:	f00b fdb2 	bl	8021988 <iprintf>
+
+  msg = (struct tcpip_msg *)memp_malloc(MEMP_TCPIP_MSG_API);
+ 8015e24:	2008      	movs	r0, #8
+ 8015e26:	f000 fe53 	bl	8016ad0 <memp_malloc>
+ 8015e2a:	60f8      	str	r0, [r7, #12]
+  if (msg == NULL) {
+ 8015e2c:	68fb      	ldr	r3, [r7, #12]
+ 8015e2e:	2b00      	cmp	r3, #0
+ 8015e30:	d102      	bne.n	8015e38 <tcpip_try_callback+0x38>
+    return ERR_MEM;
+ 8015e32:	f04f 33ff 	mov.w	r3, #4294967295
+ 8015e36:	e017      	b.n	8015e68 <tcpip_try_callback+0x68>
+  }
+
+  msg->type = TCPIP_MSG_CALLBACK;
+ 8015e38:	68fb      	ldr	r3, [r7, #12]
+ 8015e3a:	2201      	movs	r2, #1
+ 8015e3c:	701a      	strb	r2, [r3, #0]
+  msg->msg.cb.function = function;
+ 8015e3e:	68fb      	ldr	r3, [r7, #12]
+ 8015e40:	687a      	ldr	r2, [r7, #4]
+ 8015e42:	605a      	str	r2, [r3, #4]
+  msg->msg.cb.ctx = ctx;
+ 8015e44:	68fb      	ldr	r3, [r7, #12]
+ 8015e46:	683a      	ldr	r2, [r7, #0]
+ 8015e48:	609a      	str	r2, [r3, #8]
+
+  if (sys_mbox_trypost(&tcpip_mbox, msg) != ERR_OK) {
+ 8015e4a:	68f9      	ldr	r1, [r7, #12]
+ 8015e4c:	4808      	ldr	r0, [pc, #32]	; (8015e70 <tcpip_try_callback+0x70>)
+ 8015e4e:	f00b fa71 	bl	8021334 <sys_mbox_trypost>
+ 8015e52:	4603      	mov	r3, r0
+ 8015e54:	2b00      	cmp	r3, #0
+ 8015e56:	d006      	beq.n	8015e66 <tcpip_try_callback+0x66>
+    memp_free(MEMP_TCPIP_MSG_API, msg);
+ 8015e58:	68f9      	ldr	r1, [r7, #12]
+ 8015e5a:	2008      	movs	r0, #8
+ 8015e5c:	f000 feae 	bl	8016bbc <memp_free>
+    return ERR_MEM;
+ 8015e60:	f04f 33ff 	mov.w	r3, #4294967295
+ 8015e64:	e000      	b.n	8015e68 <tcpip_try_callback+0x68>
+  }
+  return ERR_OK;
+ 8015e66:	2300      	movs	r3, #0
+}
+ 8015e68:	4618      	mov	r0, r3
+ 8015e6a:	3710      	adds	r7, #16
+ 8015e6c:	46bd      	mov	sp, r7
+ 8015e6e:	bd80      	pop	{r7, pc}
+ 8015e70:	24013978 	.word	0x24013978
+ 8015e74:	08023d14 	.word	0x08023d14
+ 8015e78:	08023d8c 	.word	0x08023d8c
+ 8015e7c:	08023d64 	.word	0x08023d64
+
+08015e80 <tcpip_send_msg_wait_sem>:
+ * @param sem semaphore to wait on
+ * @return ERR_OK if the function was called, another err_t if not
+ */
+err_t
+tcpip_send_msg_wait_sem(tcpip_callback_fn fn, void *apimsg, sys_sem_t *sem)
+{
+ 8015e80:	b580      	push	{r7, lr}
+ 8015e82:	b084      	sub	sp, #16
+ 8015e84:	af00      	add	r7, sp, #0
+ 8015e86:	60f8      	str	r0, [r7, #12]
+ 8015e88:	60b9      	str	r1, [r7, #8]
+ 8015e8a:	607a      	str	r2, [r7, #4]
+#if LWIP_TCPIP_CORE_LOCKING
+  LWIP_UNUSED_ARG(sem);
+  LOCK_TCPIP_CORE();
+ 8015e8c:	4806      	ldr	r0, [pc, #24]	; (8015ea8 <tcpip_send_msg_wait_sem+0x28>)
+ 8015e8e:	f00b fb9f 	bl	80215d0 <sys_mutex_lock>
+  fn(apimsg);
+ 8015e92:	68fb      	ldr	r3, [r7, #12]
+ 8015e94:	68b8      	ldr	r0, [r7, #8]
+ 8015e96:	4798      	blx	r3
+  UNLOCK_TCPIP_CORE();
+ 8015e98:	4803      	ldr	r0, [pc, #12]	; (8015ea8 <tcpip_send_msg_wait_sem+0x28>)
+ 8015e9a:	f00b fba8 	bl	80215ee <sys_mutex_unlock>
+  return ERR_OK;
+ 8015e9e:	2300      	movs	r3, #0
+  sys_mbox_post(&tcpip_mbox, &TCPIP_MSG_VAR_REF(msg));
+  sys_arch_sem_wait(sem, 0);
+  TCPIP_MSG_VAR_FREE(msg);
+  return ERR_OK;
+#endif /* LWIP_TCPIP_CORE_LOCKING */
+}
+ 8015ea0:	4618      	mov	r0, r3
+ 8015ea2:	3710      	adds	r7, #16
+ 8015ea4:	46bd      	mov	sp, r7
+ 8015ea6:	bd80      	pop	{r7, pc}
+ 8015ea8:	2401397c 	.word	0x2401397c
+
+08015eac <tcpip_init>:
+ * @param initfunc a function to call when tcpip_thread is running and finished initializing
+ * @param arg argument to pass to initfunc
+ */
+void
+tcpip_init(tcpip_init_done_fn initfunc, void *arg)
+{
+ 8015eac:	b580      	push	{r7, lr}
+ 8015eae:	b084      	sub	sp, #16
+ 8015eb0:	af02      	add	r7, sp, #8
+ 8015eb2:	6078      	str	r0, [r7, #4]
+ 8015eb4:	6039      	str	r1, [r7, #0]
+  lwip_init();
+ 8015eb6:	f000 f92d 	bl	8016114 <lwip_init>
+
+  tcpip_init_done = initfunc;
+ 8015eba:	4a17      	ldr	r2, [pc, #92]	; (8015f18 <tcpip_init+0x6c>)
+ 8015ebc:	687b      	ldr	r3, [r7, #4]
+ 8015ebe:	6013      	str	r3, [r2, #0]
+  tcpip_init_done_arg = arg;
+ 8015ec0:	4a16      	ldr	r2, [pc, #88]	; (8015f1c <tcpip_init+0x70>)
+ 8015ec2:	683b      	ldr	r3, [r7, #0]
+ 8015ec4:	6013      	str	r3, [r2, #0]
+  if (sys_mbox_new(&tcpip_mbox, TCPIP_MBOX_SIZE) != ERR_OK) {
+ 8015ec6:	2106      	movs	r1, #6
+ 8015ec8:	4815      	ldr	r0, [pc, #84]	; (8015f20 <tcpip_init+0x74>)
+ 8015eca:	f00b f9ff 	bl	80212cc <sys_mbox_new>
+ 8015ece:	4603      	mov	r3, r0
+ 8015ed0:	2b00      	cmp	r3, #0
+ 8015ed2:	d006      	beq.n	8015ee2 <tcpip_init+0x36>
+    LWIP_ASSERT("failed to create tcpip_thread mbox", 0);
+ 8015ed4:	4b13      	ldr	r3, [pc, #76]	; (8015f24 <tcpip_init+0x78>)
+ 8015ed6:	f240 2261 	movw	r2, #609	; 0x261
+ 8015eda:	4913      	ldr	r1, [pc, #76]	; (8015f28 <tcpip_init+0x7c>)
+ 8015edc:	4813      	ldr	r0, [pc, #76]	; (8015f2c <tcpip_init+0x80>)
+ 8015ede:	f00b fd53 	bl	8021988 <iprintf>
+  }
+#if LWIP_TCPIP_CORE_LOCKING
+  if (sys_mutex_new(&lock_tcpip_core) != ERR_OK) {
+ 8015ee2:	4813      	ldr	r0, [pc, #76]	; (8015f30 <tcpip_init+0x84>)
+ 8015ee4:	f00b fb58 	bl	8021598 <sys_mutex_new>
+ 8015ee8:	4603      	mov	r3, r0
+ 8015eea:	2b00      	cmp	r3, #0
+ 8015eec:	d006      	beq.n	8015efc <tcpip_init+0x50>
+    LWIP_ASSERT("failed to create lock_tcpip_core", 0);
+ 8015eee:	4b0d      	ldr	r3, [pc, #52]	; (8015f24 <tcpip_init+0x78>)
+ 8015ef0:	f240 2265 	movw	r2, #613	; 0x265
+ 8015ef4:	490f      	ldr	r1, [pc, #60]	; (8015f34 <tcpip_init+0x88>)
+ 8015ef6:	480d      	ldr	r0, [pc, #52]	; (8015f2c <tcpip_init+0x80>)
+ 8015ef8:	f00b fd46 	bl	8021988 <iprintf>
+  }
+#endif /* LWIP_TCPIP_CORE_LOCKING */
+
+  sys_thread_new(TCPIP_THREAD_NAME, tcpip_thread, NULL, TCPIP_THREAD_STACKSIZE, TCPIP_THREAD_PRIO);
+ 8015efc:	2300      	movs	r3, #0
+ 8015efe:	9300      	str	r3, [sp, #0]
+ 8015f00:	f44f 6380 	mov.w	r3, #1024	; 0x400
+ 8015f04:	2200      	movs	r2, #0
+ 8015f06:	490c      	ldr	r1, [pc, #48]	; (8015f38 <tcpip_init+0x8c>)
+ 8015f08:	480c      	ldr	r0, [pc, #48]	; (8015f3c <tcpip_init+0x90>)
+ 8015f0a:	f00b fb7d 	bl	8021608 <sys_thread_new>
+}
+ 8015f0e:	bf00      	nop
+ 8015f10:	3708      	adds	r7, #8
+ 8015f12:	46bd      	mov	sp, r7
+ 8015f14:	bd80      	pop	{r7, pc}
+ 8015f16:	bf00      	nop
+ 8015f18:	24013970 	.word	0x24013970
+ 8015f1c:	24013974 	.word	0x24013974
+ 8015f20:	24013978 	.word	0x24013978
+ 8015f24:	08023d14 	.word	0x08023d14
+ 8015f28:	08023d9c 	.word	0x08023d9c
+ 8015f2c:	08023d64 	.word	0x08023d64
+ 8015f30:	2401397c 	.word	0x2401397c
+ 8015f34:	08023dc0 	.word	0x08023dc0
+ 8015f38:	08015c3d 	.word	0x08015c3d
+ 8015f3c:	08023de4 	.word	0x08023de4
+
+08015f40 <lwip_htons>:
+ * @param n u16_t in host byte order
+ * @return n in network byte order
+ */
+u16_t
+lwip_htons(u16_t n)
+{
+ 8015f40:	b480      	push	{r7}
+ 8015f42:	b083      	sub	sp, #12
+ 8015f44:	af00      	add	r7, sp, #0
+ 8015f46:	4603      	mov	r3, r0
+ 8015f48:	80fb      	strh	r3, [r7, #6]
+  return PP_HTONS(n);
+ 8015f4a:	88fb      	ldrh	r3, [r7, #6]
+ 8015f4c:	021b      	lsls	r3, r3, #8
+ 8015f4e:	b21a      	sxth	r2, r3
+ 8015f50:	88fb      	ldrh	r3, [r7, #6]
+ 8015f52:	0a1b      	lsrs	r3, r3, #8
+ 8015f54:	b29b      	uxth	r3, r3
+ 8015f56:	b21b      	sxth	r3, r3
+ 8015f58:	4313      	orrs	r3, r2
+ 8015f5a:	b21b      	sxth	r3, r3
+ 8015f5c:	b29b      	uxth	r3, r3
+}
+ 8015f5e:	4618      	mov	r0, r3
+ 8015f60:	370c      	adds	r7, #12
+ 8015f62:	46bd      	mov	sp, r7
+ 8015f64:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8015f68:	4770      	bx	lr
+
+08015f6a <lwip_htonl>:
+ * @param n u32_t in host byte order
+ * @return n in network byte order
+ */
+u32_t
+lwip_htonl(u32_t n)
+{
+ 8015f6a:	b480      	push	{r7}
+ 8015f6c:	b083      	sub	sp, #12
+ 8015f6e:	af00      	add	r7, sp, #0
+ 8015f70:	6078      	str	r0, [r7, #4]
+  return PP_HTONL(n);
+ 8015f72:	687b      	ldr	r3, [r7, #4]
+ 8015f74:	061a      	lsls	r2, r3, #24
+ 8015f76:	687b      	ldr	r3, [r7, #4]
+ 8015f78:	021b      	lsls	r3, r3, #8
+ 8015f7a:	f403 037f 	and.w	r3, r3, #16711680	; 0xff0000
+ 8015f7e:	431a      	orrs	r2, r3
+ 8015f80:	687b      	ldr	r3, [r7, #4]
+ 8015f82:	0a1b      	lsrs	r3, r3, #8
+ 8015f84:	f403 437f 	and.w	r3, r3, #65280	; 0xff00
+ 8015f88:	431a      	orrs	r2, r3
+ 8015f8a:	687b      	ldr	r3, [r7, #4]
+ 8015f8c:	0e1b      	lsrs	r3, r3, #24
+ 8015f8e:	4313      	orrs	r3, r2
+}
+ 8015f90:	4618      	mov	r0, r3
+ 8015f92:	370c      	adds	r7, #12
+ 8015f94:	46bd      	mov	sp, r7
+ 8015f96:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8015f9a:	4770      	bx	lr
+
+08015f9c <lwip_standard_chksum>:
+ * @param len length of data to be summed
+ * @return host order (!) lwip checksum (non-inverted Internet sum)
+ */
+u16_t
+lwip_standard_chksum(const void *dataptr, int len)
+{
+ 8015f9c:	b480      	push	{r7}
+ 8015f9e:	b089      	sub	sp, #36	; 0x24
+ 8015fa0:	af00      	add	r7, sp, #0
+ 8015fa2:	6078      	str	r0, [r7, #4]
+ 8015fa4:	6039      	str	r1, [r7, #0]
+  const u8_t *pb = (const u8_t *)dataptr;
+ 8015fa6:	687b      	ldr	r3, [r7, #4]
+ 8015fa8:	61fb      	str	r3, [r7, #28]
+  const u16_t *ps;
+  u16_t t = 0;
+ 8015faa:	2300      	movs	r3, #0
+ 8015fac:	81fb      	strh	r3, [r7, #14]
+  u32_t sum = 0;
+ 8015fae:	2300      	movs	r3, #0
+ 8015fb0:	617b      	str	r3, [r7, #20]
+  int odd = ((mem_ptr_t)pb & 1);
+ 8015fb2:	69fb      	ldr	r3, [r7, #28]
+ 8015fb4:	f003 0301 	and.w	r3, r3, #1
+ 8015fb8:	613b      	str	r3, [r7, #16]
+
+  /* Get aligned to u16_t */
+  if (odd && len > 0) {
+ 8015fba:	693b      	ldr	r3, [r7, #16]
+ 8015fbc:	2b00      	cmp	r3, #0
+ 8015fbe:	d00d      	beq.n	8015fdc <lwip_standard_chksum+0x40>
+ 8015fc0:	683b      	ldr	r3, [r7, #0]
+ 8015fc2:	2b00      	cmp	r3, #0
+ 8015fc4:	dd0a      	ble.n	8015fdc <lwip_standard_chksum+0x40>
+    ((u8_t *)&t)[1] = *pb++;
+ 8015fc6:	69fa      	ldr	r2, [r7, #28]
+ 8015fc8:	1c53      	adds	r3, r2, #1
+ 8015fca:	61fb      	str	r3, [r7, #28]
+ 8015fcc:	f107 030e 	add.w	r3, r7, #14
+ 8015fd0:	3301      	adds	r3, #1
+ 8015fd2:	7812      	ldrb	r2, [r2, #0]
+ 8015fd4:	701a      	strb	r2, [r3, #0]
+    len--;
+ 8015fd6:	683b      	ldr	r3, [r7, #0]
+ 8015fd8:	3b01      	subs	r3, #1
+ 8015fda:	603b      	str	r3, [r7, #0]
+  }
+
+  /* Add the bulk of the data */
+  ps = (const u16_t *)(const void *)pb;
+ 8015fdc:	69fb      	ldr	r3, [r7, #28]
+ 8015fde:	61bb      	str	r3, [r7, #24]
+  while (len > 1) {
+ 8015fe0:	e00a      	b.n	8015ff8 <lwip_standard_chksum+0x5c>
+    sum += *ps++;
+ 8015fe2:	69bb      	ldr	r3, [r7, #24]
+ 8015fe4:	1c9a      	adds	r2, r3, #2
+ 8015fe6:	61ba      	str	r2, [r7, #24]
+ 8015fe8:	881b      	ldrh	r3, [r3, #0]
+ 8015fea:	461a      	mov	r2, r3
+ 8015fec:	697b      	ldr	r3, [r7, #20]
+ 8015fee:	4413      	add	r3, r2
+ 8015ff0:	617b      	str	r3, [r7, #20]
+    len -= 2;
+ 8015ff2:	683b      	ldr	r3, [r7, #0]
+ 8015ff4:	3b02      	subs	r3, #2
+ 8015ff6:	603b      	str	r3, [r7, #0]
+  while (len > 1) {
+ 8015ff8:	683b      	ldr	r3, [r7, #0]
+ 8015ffa:	2b01      	cmp	r3, #1
+ 8015ffc:	dcf1      	bgt.n	8015fe2 <lwip_standard_chksum+0x46>
+  }
+
+  /* Consume left-over byte, if any */
+  if (len > 0) {
+ 8015ffe:	683b      	ldr	r3, [r7, #0]
+ 8016000:	2b00      	cmp	r3, #0
+ 8016002:	dd04      	ble.n	801600e <lwip_standard_chksum+0x72>
+    ((u8_t *)&t)[0] = *(const u8_t *)ps;
+ 8016004:	f107 030e 	add.w	r3, r7, #14
+ 8016008:	69ba      	ldr	r2, [r7, #24]
+ 801600a:	7812      	ldrb	r2, [r2, #0]
+ 801600c:	701a      	strb	r2, [r3, #0]
+  }
+
+  /* Add end bytes */
+  sum += t;
+ 801600e:	89fb      	ldrh	r3, [r7, #14]
+ 8016010:	461a      	mov	r2, r3
+ 8016012:	697b      	ldr	r3, [r7, #20]
+ 8016014:	4413      	add	r3, r2
+ 8016016:	617b      	str	r3, [r7, #20]
+
+  /* Fold 32-bit sum to 16 bits
+     calling this twice is probably faster than if statements... */
+  sum = FOLD_U32T(sum);
+ 8016018:	697b      	ldr	r3, [r7, #20]
+ 801601a:	0c1a      	lsrs	r2, r3, #16
+ 801601c:	697b      	ldr	r3, [r7, #20]
+ 801601e:	b29b      	uxth	r3, r3
+ 8016020:	4413      	add	r3, r2
+ 8016022:	617b      	str	r3, [r7, #20]
+  sum = FOLD_U32T(sum);
+ 8016024:	697b      	ldr	r3, [r7, #20]
+ 8016026:	0c1a      	lsrs	r2, r3, #16
+ 8016028:	697b      	ldr	r3, [r7, #20]
+ 801602a:	b29b      	uxth	r3, r3
+ 801602c:	4413      	add	r3, r2
+ 801602e:	617b      	str	r3, [r7, #20]
+
+  /* Swap if alignment was odd */
+  if (odd) {
+ 8016030:	693b      	ldr	r3, [r7, #16]
+ 8016032:	2b00      	cmp	r3, #0
+ 8016034:	d007      	beq.n	8016046 <lwip_standard_chksum+0xaa>
+    sum = SWAP_BYTES_IN_WORD(sum);
+ 8016036:	697b      	ldr	r3, [r7, #20]
+ 8016038:	021b      	lsls	r3, r3, #8
+ 801603a:	b29a      	uxth	r2, r3
+ 801603c:	697b      	ldr	r3, [r7, #20]
+ 801603e:	0a1b      	lsrs	r3, r3, #8
+ 8016040:	b2db      	uxtb	r3, r3
+ 8016042:	4313      	orrs	r3, r2
+ 8016044:	617b      	str	r3, [r7, #20]
+  }
+
+  return (u16_t)sum;
+ 8016046:	697b      	ldr	r3, [r7, #20]
+ 8016048:	b29b      	uxth	r3, r3
+}
+ 801604a:	4618      	mov	r0, r3
+ 801604c:	3724      	adds	r7, #36	; 0x24
+ 801604e:	46bd      	mov	sp, r7
+ 8016050:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8016054:	4770      	bx	lr
+
+08016056 <inet_chksum>:
+ * @return checksum (as u16_t) to be saved directly in the protocol header
+ */
+
+u16_t
+inet_chksum(const void *dataptr, u16_t len)
+{
+ 8016056:	b580      	push	{r7, lr}
+ 8016058:	b082      	sub	sp, #8
+ 801605a:	af00      	add	r7, sp, #0
+ 801605c:	6078      	str	r0, [r7, #4]
+ 801605e:	460b      	mov	r3, r1
+ 8016060:	807b      	strh	r3, [r7, #2]
+  return (u16_t)~(unsigned int)LWIP_CHKSUM(dataptr, len);
+ 8016062:	887b      	ldrh	r3, [r7, #2]
+ 8016064:	4619      	mov	r1, r3
+ 8016066:	6878      	ldr	r0, [r7, #4]
+ 8016068:	f7ff ff98 	bl	8015f9c <lwip_standard_chksum>
+ 801606c:	4603      	mov	r3, r0
+ 801606e:	43db      	mvns	r3, r3
+ 8016070:	b29b      	uxth	r3, r3
+}
+ 8016072:	4618      	mov	r0, r3
+ 8016074:	3708      	adds	r7, #8
+ 8016076:	46bd      	mov	sp, r7
+ 8016078:	bd80      	pop	{r7, pc}
+
+0801607a <inet_chksum_pbuf>:
+ * @param p pbuf chain over that the checksum should be calculated
+ * @return checksum (as u16_t) to be saved directly in the protocol header
+ */
+u16_t
+inet_chksum_pbuf(struct pbuf *p)
+{
+ 801607a:	b580      	push	{r7, lr}
+ 801607c:	b086      	sub	sp, #24
+ 801607e:	af00      	add	r7, sp, #0
+ 8016080:	6078      	str	r0, [r7, #4]
+  u32_t acc;
+  struct pbuf *q;
+  int swapped = 0;
+ 8016082:	2300      	movs	r3, #0
+ 8016084:	60fb      	str	r3, [r7, #12]
+
+  acc = 0;
+ 8016086:	2300      	movs	r3, #0
+ 8016088:	617b      	str	r3, [r7, #20]
+  for (q = p; q != NULL; q = q->next) {
+ 801608a:	687b      	ldr	r3, [r7, #4]
+ 801608c:	613b      	str	r3, [r7, #16]
+ 801608e:	e02b      	b.n	80160e8 <inet_chksum_pbuf+0x6e>
+    acc += LWIP_CHKSUM(q->payload, q->len);
+ 8016090:	693b      	ldr	r3, [r7, #16]
+ 8016092:	685a      	ldr	r2, [r3, #4]
+ 8016094:	693b      	ldr	r3, [r7, #16]
+ 8016096:	895b      	ldrh	r3, [r3, #10]
+ 8016098:	4619      	mov	r1, r3
+ 801609a:	4610      	mov	r0, r2
+ 801609c:	f7ff ff7e 	bl	8015f9c <lwip_standard_chksum>
+ 80160a0:	4603      	mov	r3, r0
+ 80160a2:	461a      	mov	r2, r3
+ 80160a4:	697b      	ldr	r3, [r7, #20]
+ 80160a6:	4413      	add	r3, r2
+ 80160a8:	617b      	str	r3, [r7, #20]
+    acc = FOLD_U32T(acc);
+ 80160aa:	697b      	ldr	r3, [r7, #20]
+ 80160ac:	0c1a      	lsrs	r2, r3, #16
+ 80160ae:	697b      	ldr	r3, [r7, #20]
+ 80160b0:	b29b      	uxth	r3, r3
+ 80160b2:	4413      	add	r3, r2
+ 80160b4:	617b      	str	r3, [r7, #20]
+    if (q->len % 2 != 0) {
+ 80160b6:	693b      	ldr	r3, [r7, #16]
+ 80160b8:	895b      	ldrh	r3, [r3, #10]
+ 80160ba:	f003 0301 	and.w	r3, r3, #1
+ 80160be:	b29b      	uxth	r3, r3
+ 80160c0:	2b00      	cmp	r3, #0
+ 80160c2:	d00e      	beq.n	80160e2 <inet_chksum_pbuf+0x68>
+      swapped = !swapped;
+ 80160c4:	68fb      	ldr	r3, [r7, #12]
+ 80160c6:	2b00      	cmp	r3, #0
+ 80160c8:	bf0c      	ite	eq
+ 80160ca:	2301      	moveq	r3, #1
+ 80160cc:	2300      	movne	r3, #0
+ 80160ce:	b2db      	uxtb	r3, r3
+ 80160d0:	60fb      	str	r3, [r7, #12]
+      acc = SWAP_BYTES_IN_WORD(acc);
+ 80160d2:	697b      	ldr	r3, [r7, #20]
+ 80160d4:	021b      	lsls	r3, r3, #8
+ 80160d6:	b29a      	uxth	r2, r3
+ 80160d8:	697b      	ldr	r3, [r7, #20]
+ 80160da:	0a1b      	lsrs	r3, r3, #8
+ 80160dc:	b2db      	uxtb	r3, r3
+ 80160de:	4313      	orrs	r3, r2
+ 80160e0:	617b      	str	r3, [r7, #20]
+  for (q = p; q != NULL; q = q->next) {
+ 80160e2:	693b      	ldr	r3, [r7, #16]
+ 80160e4:	681b      	ldr	r3, [r3, #0]
+ 80160e6:	613b      	str	r3, [r7, #16]
+ 80160e8:	693b      	ldr	r3, [r7, #16]
+ 80160ea:	2b00      	cmp	r3, #0
+ 80160ec:	d1d0      	bne.n	8016090 <inet_chksum_pbuf+0x16>
+    }
+  }
+
+  if (swapped) {
+ 80160ee:	68fb      	ldr	r3, [r7, #12]
+ 80160f0:	2b00      	cmp	r3, #0
+ 80160f2:	d007      	beq.n	8016104 <inet_chksum_pbuf+0x8a>
+    acc = SWAP_BYTES_IN_WORD(acc);
+ 80160f4:	697b      	ldr	r3, [r7, #20]
+ 80160f6:	021b      	lsls	r3, r3, #8
+ 80160f8:	b29a      	uxth	r2, r3
+ 80160fa:	697b      	ldr	r3, [r7, #20]
+ 80160fc:	0a1b      	lsrs	r3, r3, #8
+ 80160fe:	b2db      	uxtb	r3, r3
+ 8016100:	4313      	orrs	r3, r2
+ 8016102:	617b      	str	r3, [r7, #20]
+  }
+  return (u16_t)~(acc & 0xffffUL);
+ 8016104:	697b      	ldr	r3, [r7, #20]
+ 8016106:	b29b      	uxth	r3, r3
+ 8016108:	43db      	mvns	r3, r3
+ 801610a:	b29b      	uxth	r3, r3
+}
+ 801610c:	4618      	mov	r0, r3
+ 801610e:	3718      	adds	r7, #24
+ 8016110:	46bd      	mov	sp, r7
+ 8016112:	bd80      	pop	{r7, pc}
+
+08016114 <lwip_init>:
+ * Initialize all modules.
+ * Use this in NO_SYS mode. Use tcpip_init() otherwise.
+ */
+void
+lwip_init(void)
+{
+ 8016114:	b580      	push	{r7, lr}
+ 8016116:	b082      	sub	sp, #8
+ 8016118:	af00      	add	r7, sp, #0
+#ifndef LWIP_SKIP_CONST_CHECK
+  int a = 0;
+ 801611a:	2300      	movs	r3, #0
+ 801611c:	607b      	str	r3, [r7, #4]
+#endif
+
+  /* Modules initialization */
+  stats_init();
+#if !NO_SYS
+  sys_init();
+ 801611e:	f00b fa2d 	bl	802157c <sys_init>
+#endif /* !NO_SYS */
+  mem_init();
+ 8016122:	f000 f8d9 	bl	80162d8 <mem_init>
+  memp_init();
+ 8016126:	f000 fc5d 	bl	80169e4 <memp_init>
+  pbuf_init();
+  netif_init();
+ 801612a:	f000 fd71 	bl	8016c10 <netif_init>
+#endif /* LWIP_IPV4 */
+#if LWIP_RAW
+  raw_init();
+#endif /* LWIP_RAW */
+#if LWIP_UDP
+  udp_init();
+ 801612e:	f008 fa41 	bl	801e5b4 <udp_init>
+#endif /* LWIP_UDP */
+#if LWIP_TCP
+  tcp_init();
+ 8016132:	f001 ff7b 	bl	801802c <tcp_init>
+#if PPP_SUPPORT
+  ppp_init();
+#endif
+
+#if LWIP_TIMERS
+  sys_timeouts_init();
+ 8016136:	f008 f983 	bl	801e440 <sys_timeouts_init>
+#endif /* LWIP_TIMERS */
+}
+ 801613a:	bf00      	nop
+ 801613c:	3708      	adds	r7, #8
+ 801613e:	46bd      	mov	sp, r7
+ 8016140:	bd80      	pop	{r7, pc}
+	...
+
+08016144 <ptr_to_mem>:
+#define mem_overflow_check_element(mem)
+#endif /* MEM_OVERFLOW_CHECK */
+
+static struct mem *
+ptr_to_mem(mem_size_t ptr)
+{
+ 8016144:	b480      	push	{r7}
+ 8016146:	b083      	sub	sp, #12
+ 8016148:	af00      	add	r7, sp, #0
+ 801614a:	4603      	mov	r3, r0
+ 801614c:	80fb      	strh	r3, [r7, #6]
+  return (struct mem *)(void *)&ram[ptr];
+ 801614e:	4b05      	ldr	r3, [pc, #20]	; (8016164 <ptr_to_mem+0x20>)
+ 8016150:	681a      	ldr	r2, [r3, #0]
+ 8016152:	88fb      	ldrh	r3, [r7, #6]
+ 8016154:	4413      	add	r3, r2
+}
+ 8016156:	4618      	mov	r0, r3
+ 8016158:	370c      	adds	r7, #12
+ 801615a:	46bd      	mov	sp, r7
+ 801615c:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8016160:	4770      	bx	lr
+ 8016162:	bf00      	nop
+ 8016164:	24013998 	.word	0x24013998
+
+08016168 <mem_to_ptr>:
+
+static mem_size_t
+mem_to_ptr(void *mem)
+{
+ 8016168:	b480      	push	{r7}
+ 801616a:	b083      	sub	sp, #12
+ 801616c:	af00      	add	r7, sp, #0
+ 801616e:	6078      	str	r0, [r7, #4]
+  return (mem_size_t)((u8_t *)mem - ram);
+ 8016170:	4b05      	ldr	r3, [pc, #20]	; (8016188 <mem_to_ptr+0x20>)
+ 8016172:	681b      	ldr	r3, [r3, #0]
+ 8016174:	687a      	ldr	r2, [r7, #4]
+ 8016176:	1ad3      	subs	r3, r2, r3
+ 8016178:	b29b      	uxth	r3, r3
+}
+ 801617a:	4618      	mov	r0, r3
+ 801617c:	370c      	adds	r7, #12
+ 801617e:	46bd      	mov	sp, r7
+ 8016180:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8016184:	4770      	bx	lr
+ 8016186:	bf00      	nop
+ 8016188:	24013998 	.word	0x24013998
+
+0801618c <plug_holes>:
+ * This assumes access to the heap is protected by the calling function
+ * already.
+ */
+static void
+plug_holes(struct mem *mem)
+{
+ 801618c:	b590      	push	{r4, r7, lr}
+ 801618e:	b085      	sub	sp, #20
+ 8016190:	af00      	add	r7, sp, #0
+ 8016192:	6078      	str	r0, [r7, #4]
+  struct mem *nmem;
+  struct mem *pmem;
+
+  LWIP_ASSERT("plug_holes: mem >= ram", (u8_t *)mem >= ram);
+ 8016194:	4b47      	ldr	r3, [pc, #284]	; (80162b4 <plug_holes+0x128>)
+ 8016196:	681b      	ldr	r3, [r3, #0]
+ 8016198:	687a      	ldr	r2, [r7, #4]
+ 801619a:	429a      	cmp	r2, r3
+ 801619c:	d206      	bcs.n	80161ac <plug_holes+0x20>
+ 801619e:	4b46      	ldr	r3, [pc, #280]	; (80162b8 <plug_holes+0x12c>)
+ 80161a0:	f240 12df 	movw	r2, #479	; 0x1df
+ 80161a4:	4945      	ldr	r1, [pc, #276]	; (80162bc <plug_holes+0x130>)
+ 80161a6:	4846      	ldr	r0, [pc, #280]	; (80162c0 <plug_holes+0x134>)
+ 80161a8:	f00b fbee 	bl	8021988 <iprintf>
+  LWIP_ASSERT("plug_holes: mem < ram_end", (u8_t *)mem < (u8_t *)ram_end);
+ 80161ac:	4b45      	ldr	r3, [pc, #276]	; (80162c4 <plug_holes+0x138>)
+ 80161ae:	681b      	ldr	r3, [r3, #0]
+ 80161b0:	687a      	ldr	r2, [r7, #4]
+ 80161b2:	429a      	cmp	r2, r3
+ 80161b4:	d306      	bcc.n	80161c4 <plug_holes+0x38>
+ 80161b6:	4b40      	ldr	r3, [pc, #256]	; (80162b8 <plug_holes+0x12c>)
+ 80161b8:	f44f 72f0 	mov.w	r2, #480	; 0x1e0
+ 80161bc:	4942      	ldr	r1, [pc, #264]	; (80162c8 <plug_holes+0x13c>)
+ 80161be:	4840      	ldr	r0, [pc, #256]	; (80162c0 <plug_holes+0x134>)
+ 80161c0:	f00b fbe2 	bl	8021988 <iprintf>
+  LWIP_ASSERT("plug_holes: mem->used == 0", mem->used == 0);
+ 80161c4:	687b      	ldr	r3, [r7, #4]
+ 80161c6:	791b      	ldrb	r3, [r3, #4]
+ 80161c8:	2b00      	cmp	r3, #0
+ 80161ca:	d006      	beq.n	80161da <plug_holes+0x4e>
+ 80161cc:	4b3a      	ldr	r3, [pc, #232]	; (80162b8 <plug_holes+0x12c>)
+ 80161ce:	f240 12e1 	movw	r2, #481	; 0x1e1
+ 80161d2:	493e      	ldr	r1, [pc, #248]	; (80162cc <plug_holes+0x140>)
+ 80161d4:	483a      	ldr	r0, [pc, #232]	; (80162c0 <plug_holes+0x134>)
+ 80161d6:	f00b fbd7 	bl	8021988 <iprintf>
+
+  /* plug hole forward */
+  LWIP_ASSERT("plug_holes: mem->next <= MEM_SIZE_ALIGNED", mem->next <= MEM_SIZE_ALIGNED);
+ 80161da:	687b      	ldr	r3, [r7, #4]
+ 80161dc:	881b      	ldrh	r3, [r3, #0]
+ 80161de:	f647 52e8 	movw	r2, #32232	; 0x7de8
+ 80161e2:	4293      	cmp	r3, r2
+ 80161e4:	d906      	bls.n	80161f4 <plug_holes+0x68>
+ 80161e6:	4b34      	ldr	r3, [pc, #208]	; (80162b8 <plug_holes+0x12c>)
+ 80161e8:	f44f 72f2 	mov.w	r2, #484	; 0x1e4
+ 80161ec:	4938      	ldr	r1, [pc, #224]	; (80162d0 <plug_holes+0x144>)
+ 80161ee:	4834      	ldr	r0, [pc, #208]	; (80162c0 <plug_holes+0x134>)
+ 80161f0:	f00b fbca 	bl	8021988 <iprintf>
+
+  nmem = ptr_to_mem(mem->next);
+ 80161f4:	687b      	ldr	r3, [r7, #4]
+ 80161f6:	881b      	ldrh	r3, [r3, #0]
+ 80161f8:	4618      	mov	r0, r3
+ 80161fa:	f7ff ffa3 	bl	8016144 <ptr_to_mem>
+ 80161fe:	60f8      	str	r0, [r7, #12]
+  if (mem != nmem && nmem->used == 0 && (u8_t *)nmem != (u8_t *)ram_end) {
+ 8016200:	687a      	ldr	r2, [r7, #4]
+ 8016202:	68fb      	ldr	r3, [r7, #12]
+ 8016204:	429a      	cmp	r2, r3
+ 8016206:	d025      	beq.n	8016254 <plug_holes+0xc8>
+ 8016208:	68fb      	ldr	r3, [r7, #12]
+ 801620a:	791b      	ldrb	r3, [r3, #4]
+ 801620c:	2b00      	cmp	r3, #0
+ 801620e:	d121      	bne.n	8016254 <plug_holes+0xc8>
+ 8016210:	4b2c      	ldr	r3, [pc, #176]	; (80162c4 <plug_holes+0x138>)
+ 8016212:	681b      	ldr	r3, [r3, #0]
+ 8016214:	68fa      	ldr	r2, [r7, #12]
+ 8016216:	429a      	cmp	r2, r3
+ 8016218:	d01c      	beq.n	8016254 <plug_holes+0xc8>
+    /* if mem->next is unused and not end of ram, combine mem and mem->next */
+    if (lfree == nmem) {
+ 801621a:	4b2e      	ldr	r3, [pc, #184]	; (80162d4 <plug_holes+0x148>)
+ 801621c:	681b      	ldr	r3, [r3, #0]
+ 801621e:	68fa      	ldr	r2, [r7, #12]
+ 8016220:	429a      	cmp	r2, r3
+ 8016222:	d102      	bne.n	801622a <plug_holes+0x9e>
+      lfree = mem;
+ 8016224:	4a2b      	ldr	r2, [pc, #172]	; (80162d4 <plug_holes+0x148>)
+ 8016226:	687b      	ldr	r3, [r7, #4]
+ 8016228:	6013      	str	r3, [r2, #0]
+    }
+    mem->next = nmem->next;
+ 801622a:	68fb      	ldr	r3, [r7, #12]
+ 801622c:	881a      	ldrh	r2, [r3, #0]
+ 801622e:	687b      	ldr	r3, [r7, #4]
+ 8016230:	801a      	strh	r2, [r3, #0]
+    if (nmem->next != MEM_SIZE_ALIGNED) {
+ 8016232:	68fb      	ldr	r3, [r7, #12]
+ 8016234:	881b      	ldrh	r3, [r3, #0]
+ 8016236:	f647 52e8 	movw	r2, #32232	; 0x7de8
+ 801623a:	4293      	cmp	r3, r2
+ 801623c:	d00a      	beq.n	8016254 <plug_holes+0xc8>
+      ptr_to_mem(nmem->next)->prev = mem_to_ptr(mem);
+ 801623e:	68fb      	ldr	r3, [r7, #12]
+ 8016240:	881b      	ldrh	r3, [r3, #0]
+ 8016242:	4618      	mov	r0, r3
+ 8016244:	f7ff ff7e 	bl	8016144 <ptr_to_mem>
+ 8016248:	4604      	mov	r4, r0
+ 801624a:	6878      	ldr	r0, [r7, #4]
+ 801624c:	f7ff ff8c 	bl	8016168 <mem_to_ptr>
+ 8016250:	4603      	mov	r3, r0
+ 8016252:	8063      	strh	r3, [r4, #2]
+    }
+  }
+
+  /* plug hole backward */
+  pmem = ptr_to_mem(mem->prev);
+ 8016254:	687b      	ldr	r3, [r7, #4]
+ 8016256:	885b      	ldrh	r3, [r3, #2]
+ 8016258:	4618      	mov	r0, r3
+ 801625a:	f7ff ff73 	bl	8016144 <ptr_to_mem>
+ 801625e:	60b8      	str	r0, [r7, #8]
+  if (pmem != mem && pmem->used == 0) {
+ 8016260:	68ba      	ldr	r2, [r7, #8]
+ 8016262:	687b      	ldr	r3, [r7, #4]
+ 8016264:	429a      	cmp	r2, r3
+ 8016266:	d020      	beq.n	80162aa <plug_holes+0x11e>
+ 8016268:	68bb      	ldr	r3, [r7, #8]
+ 801626a:	791b      	ldrb	r3, [r3, #4]
+ 801626c:	2b00      	cmp	r3, #0
+ 801626e:	d11c      	bne.n	80162aa <plug_holes+0x11e>
+    /* if mem->prev is unused, combine mem and mem->prev */
+    if (lfree == mem) {
+ 8016270:	4b18      	ldr	r3, [pc, #96]	; (80162d4 <plug_holes+0x148>)
+ 8016272:	681b      	ldr	r3, [r3, #0]
+ 8016274:	687a      	ldr	r2, [r7, #4]
+ 8016276:	429a      	cmp	r2, r3
+ 8016278:	d102      	bne.n	8016280 <plug_holes+0xf4>
+      lfree = pmem;
+ 801627a:	4a16      	ldr	r2, [pc, #88]	; (80162d4 <plug_holes+0x148>)
+ 801627c:	68bb      	ldr	r3, [r7, #8]
+ 801627e:	6013      	str	r3, [r2, #0]
+    }
+    pmem->next = mem->next;
+ 8016280:	687b      	ldr	r3, [r7, #4]
+ 8016282:	881a      	ldrh	r2, [r3, #0]
+ 8016284:	68bb      	ldr	r3, [r7, #8]
+ 8016286:	801a      	strh	r2, [r3, #0]
+    if (mem->next != MEM_SIZE_ALIGNED) {
+ 8016288:	687b      	ldr	r3, [r7, #4]
+ 801628a:	881b      	ldrh	r3, [r3, #0]
+ 801628c:	f647 52e8 	movw	r2, #32232	; 0x7de8
+ 8016290:	4293      	cmp	r3, r2
+ 8016292:	d00a      	beq.n	80162aa <plug_holes+0x11e>
+      ptr_to_mem(mem->next)->prev = mem_to_ptr(pmem);
+ 8016294:	687b      	ldr	r3, [r7, #4]
+ 8016296:	881b      	ldrh	r3, [r3, #0]
+ 8016298:	4618      	mov	r0, r3
+ 801629a:	f7ff ff53 	bl	8016144 <ptr_to_mem>
+ 801629e:	4604      	mov	r4, r0
+ 80162a0:	68b8      	ldr	r0, [r7, #8]
+ 80162a2:	f7ff ff61 	bl	8016168 <mem_to_ptr>
+ 80162a6:	4603      	mov	r3, r0
+ 80162a8:	8063      	strh	r3, [r4, #2]
+    }
+  }
+}
+ 80162aa:	bf00      	nop
+ 80162ac:	3714      	adds	r7, #20
+ 80162ae:	46bd      	mov	sp, r7
+ 80162b0:	bd90      	pop	{r4, r7, pc}
+ 80162b2:	bf00      	nop
+ 80162b4:	24013998 	.word	0x24013998
+ 80162b8:	08023df4 	.word	0x08023df4
+ 80162bc:	08023e24 	.word	0x08023e24
+ 80162c0:	08023e3c 	.word	0x08023e3c
+ 80162c4:	2401399c 	.word	0x2401399c
+ 80162c8:	08023e64 	.word	0x08023e64
+ 80162cc:	08023e80 	.word	0x08023e80
+ 80162d0:	08023e9c 	.word	0x08023e9c
+ 80162d4:	240139a4 	.word	0x240139a4
+
+080162d8 <mem_init>:
+/**
+ * Zero the heap and initialize start, end and lowest-free
+ */
+void
+mem_init(void)
+{
+ 80162d8:	b580      	push	{r7, lr}
+ 80162da:	b082      	sub	sp, #8
+ 80162dc:	af00      	add	r7, sp, #0
+
+  LWIP_ASSERT("Sanity check alignment",
+              (SIZEOF_STRUCT_MEM & (MEM_ALIGNMENT - 1)) == 0);
+
+  /* align the heap */
+  ram = (u8_t *)LWIP_MEM_ALIGN(LWIP_RAM_HEAP_POINTER);
+ 80162de:	4b1d      	ldr	r3, [pc, #116]	; (8016354 <mem_init+0x7c>)
+ 80162e0:	4a1d      	ldr	r2, [pc, #116]	; (8016358 <mem_init+0x80>)
+ 80162e2:	601a      	str	r2, [r3, #0]
+  /* initialize the start of the heap */
+  mem = (struct mem *)(void *)ram;
+ 80162e4:	4b1b      	ldr	r3, [pc, #108]	; (8016354 <mem_init+0x7c>)
+ 80162e6:	681b      	ldr	r3, [r3, #0]
+ 80162e8:	607b      	str	r3, [r7, #4]
+  mem->next = MEM_SIZE_ALIGNED;
+ 80162ea:	687b      	ldr	r3, [r7, #4]
+ 80162ec:	f647 52e8 	movw	r2, #32232	; 0x7de8
+ 80162f0:	801a      	strh	r2, [r3, #0]
+  mem->prev = 0;
+ 80162f2:	687b      	ldr	r3, [r7, #4]
+ 80162f4:	2200      	movs	r2, #0
+ 80162f6:	805a      	strh	r2, [r3, #2]
+  mem->used = 0;
+ 80162f8:	687b      	ldr	r3, [r7, #4]
+ 80162fa:	2200      	movs	r2, #0
+ 80162fc:	711a      	strb	r2, [r3, #4]
+  /* initialize the end of the heap */
+  ram_end = ptr_to_mem(MEM_SIZE_ALIGNED);
+ 80162fe:	f647 50e8 	movw	r0, #32232	; 0x7de8
+ 8016302:	f7ff ff1f 	bl	8016144 <ptr_to_mem>
+ 8016306:	4603      	mov	r3, r0
+ 8016308:	4a14      	ldr	r2, [pc, #80]	; (801635c <mem_init+0x84>)
+ 801630a:	6013      	str	r3, [r2, #0]
+  ram_end->used = 1;
+ 801630c:	4b13      	ldr	r3, [pc, #76]	; (801635c <mem_init+0x84>)
+ 801630e:	681b      	ldr	r3, [r3, #0]
+ 8016310:	2201      	movs	r2, #1
+ 8016312:	711a      	strb	r2, [r3, #4]
+  ram_end->next = MEM_SIZE_ALIGNED;
+ 8016314:	4b11      	ldr	r3, [pc, #68]	; (801635c <mem_init+0x84>)
+ 8016316:	681b      	ldr	r3, [r3, #0]
+ 8016318:	f647 52e8 	movw	r2, #32232	; 0x7de8
+ 801631c:	801a      	strh	r2, [r3, #0]
+  ram_end->prev = MEM_SIZE_ALIGNED;
+ 801631e:	4b0f      	ldr	r3, [pc, #60]	; (801635c <mem_init+0x84>)
+ 8016320:	681b      	ldr	r3, [r3, #0]
+ 8016322:	f647 52e8 	movw	r2, #32232	; 0x7de8
+ 8016326:	805a      	strh	r2, [r3, #2]
+  MEM_SANITY();
+
+  /* initialize the lowest-free pointer to the start of the heap */
+  lfree = (struct mem *)(void *)ram;
+ 8016328:	4b0a      	ldr	r3, [pc, #40]	; (8016354 <mem_init+0x7c>)
+ 801632a:	681b      	ldr	r3, [r3, #0]
+ 801632c:	4a0c      	ldr	r2, [pc, #48]	; (8016360 <mem_init+0x88>)
+ 801632e:	6013      	str	r3, [r2, #0]
+
+  MEM_STATS_AVAIL(avail, MEM_SIZE_ALIGNED);
+
+  if (sys_mutex_new(&mem_mutex) != ERR_OK) {
+ 8016330:	480c      	ldr	r0, [pc, #48]	; (8016364 <mem_init+0x8c>)
+ 8016332:	f00b f931 	bl	8021598 <sys_mutex_new>
+ 8016336:	4603      	mov	r3, r0
+ 8016338:	2b00      	cmp	r3, #0
+ 801633a:	d006      	beq.n	801634a <mem_init+0x72>
+    LWIP_ASSERT("failed to create mem_mutex", 0);
+ 801633c:	4b0a      	ldr	r3, [pc, #40]	; (8016368 <mem_init+0x90>)
+ 801633e:	f240 221f 	movw	r2, #543	; 0x21f
+ 8016342:	490a      	ldr	r1, [pc, #40]	; (801636c <mem_init+0x94>)
+ 8016344:	480a      	ldr	r0, [pc, #40]	; (8016370 <mem_init+0x98>)
+ 8016346:	f00b fb1f 	bl	8021988 <iprintf>
+  }
+}
+ 801634a:	bf00      	nop
+ 801634c:	3708      	adds	r7, #8
+ 801634e:	46bd      	mov	sp, r7
+ 8016350:	bd80      	pop	{r7, pc}
+ 8016352:	bf00      	nop
+ 8016354:	24013998 	.word	0x24013998
+ 8016358:	30000200 	.word	0x30000200
+ 801635c:	2401399c 	.word	0x2401399c
+ 8016360:	240139a4 	.word	0x240139a4
+ 8016364:	240139a0 	.word	0x240139a0
+ 8016368:	08023df4 	.word	0x08023df4
+ 801636c:	08023ec8 	.word	0x08023ec8
+ 8016370:	08023e3c 	.word	0x08023e3c
+
+08016374 <mem_link_valid>:
+/* Check if a struct mem is correctly linked.
+ * If not, double-free is a possible reason.
+ */
+static int
+mem_link_valid(struct mem *mem)
+{
+ 8016374:	b580      	push	{r7, lr}
+ 8016376:	b086      	sub	sp, #24
+ 8016378:	af00      	add	r7, sp, #0
+ 801637a:	6078      	str	r0, [r7, #4]
+  struct mem *nmem, *pmem;
+  mem_size_t rmem_idx;
+  rmem_idx = mem_to_ptr(mem);
+ 801637c:	6878      	ldr	r0, [r7, #4]
+ 801637e:	f7ff fef3 	bl	8016168 <mem_to_ptr>
+ 8016382:	4603      	mov	r3, r0
+ 8016384:	82fb      	strh	r3, [r7, #22]
+  nmem = ptr_to_mem(mem->next);
+ 8016386:	687b      	ldr	r3, [r7, #4]
+ 8016388:	881b      	ldrh	r3, [r3, #0]
+ 801638a:	4618      	mov	r0, r3
+ 801638c:	f7ff feda 	bl	8016144 <ptr_to_mem>
+ 8016390:	6138      	str	r0, [r7, #16]
+  pmem = ptr_to_mem(mem->prev);
+ 8016392:	687b      	ldr	r3, [r7, #4]
+ 8016394:	885b      	ldrh	r3, [r3, #2]
+ 8016396:	4618      	mov	r0, r3
+ 8016398:	f7ff fed4 	bl	8016144 <ptr_to_mem>
+ 801639c:	60f8      	str	r0, [r7, #12]
+  if ((mem->next > MEM_SIZE_ALIGNED) || (mem->prev > MEM_SIZE_ALIGNED) ||
+ 801639e:	687b      	ldr	r3, [r7, #4]
+ 80163a0:	881b      	ldrh	r3, [r3, #0]
+ 80163a2:	f647 52e8 	movw	r2, #32232	; 0x7de8
+ 80163a6:	4293      	cmp	r3, r2
+ 80163a8:	d819      	bhi.n	80163de <mem_link_valid+0x6a>
+ 80163aa:	687b      	ldr	r3, [r7, #4]
+ 80163ac:	885b      	ldrh	r3, [r3, #2]
+ 80163ae:	f647 52e8 	movw	r2, #32232	; 0x7de8
+ 80163b2:	4293      	cmp	r3, r2
+ 80163b4:	d813      	bhi.n	80163de <mem_link_valid+0x6a>
+      ((mem->prev != rmem_idx) && (pmem->next != rmem_idx)) ||
+ 80163b6:	687b      	ldr	r3, [r7, #4]
+ 80163b8:	885b      	ldrh	r3, [r3, #2]
+  if ((mem->next > MEM_SIZE_ALIGNED) || (mem->prev > MEM_SIZE_ALIGNED) ||
+ 80163ba:	8afa      	ldrh	r2, [r7, #22]
+ 80163bc:	429a      	cmp	r2, r3
+ 80163be:	d004      	beq.n	80163ca <mem_link_valid+0x56>
+      ((mem->prev != rmem_idx) && (pmem->next != rmem_idx)) ||
+ 80163c0:	68fb      	ldr	r3, [r7, #12]
+ 80163c2:	881b      	ldrh	r3, [r3, #0]
+ 80163c4:	8afa      	ldrh	r2, [r7, #22]
+ 80163c6:	429a      	cmp	r2, r3
+ 80163c8:	d109      	bne.n	80163de <mem_link_valid+0x6a>
+      ((nmem != ram_end) && (nmem->prev != rmem_idx))) {
+ 80163ca:	4b08      	ldr	r3, [pc, #32]	; (80163ec <mem_link_valid+0x78>)
+ 80163cc:	681b      	ldr	r3, [r3, #0]
+      ((mem->prev != rmem_idx) && (pmem->next != rmem_idx)) ||
+ 80163ce:	693a      	ldr	r2, [r7, #16]
+ 80163d0:	429a      	cmp	r2, r3
+ 80163d2:	d006      	beq.n	80163e2 <mem_link_valid+0x6e>
+      ((nmem != ram_end) && (nmem->prev != rmem_idx))) {
+ 80163d4:	693b      	ldr	r3, [r7, #16]
+ 80163d6:	885b      	ldrh	r3, [r3, #2]
+ 80163d8:	8afa      	ldrh	r2, [r7, #22]
+ 80163da:	429a      	cmp	r2, r3
+ 80163dc:	d001      	beq.n	80163e2 <mem_link_valid+0x6e>
+    return 0;
+ 80163de:	2300      	movs	r3, #0
+ 80163e0:	e000      	b.n	80163e4 <mem_link_valid+0x70>
+  }
+  return 1;
+ 80163e2:	2301      	movs	r3, #1
+}
+ 80163e4:	4618      	mov	r0, r3
+ 80163e6:	3718      	adds	r7, #24
+ 80163e8:	46bd      	mov	sp, r7
+ 80163ea:	bd80      	pop	{r7, pc}
+ 80163ec:	2401399c 	.word	0x2401399c
+
+080163f0 <mem_free>:
+ * @param rmem is the data portion of a struct mem as returned by a previous
+ *             call to mem_malloc()
+ */
+void
+mem_free(void *rmem)
+{
+ 80163f0:	b580      	push	{r7, lr}
+ 80163f2:	b088      	sub	sp, #32
+ 80163f4:	af00      	add	r7, sp, #0
+ 80163f6:	6078      	str	r0, [r7, #4]
+  struct mem *mem;
+  LWIP_MEM_FREE_DECL_PROTECT();
+
+  if (rmem == NULL) {
+ 80163f8:	687b      	ldr	r3, [r7, #4]
+ 80163fa:	2b00      	cmp	r3, #0
+ 80163fc:	d103      	bne.n	8016406 <mem_free+0x16>
+    LWIP_DEBUGF(MEM_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, ("mem_free(p == NULL) was called.\n"));
+ 80163fe:	4841      	ldr	r0, [pc, #260]	; (8016504 <mem_free+0x114>)
+ 8016400:	f00b fb30 	bl	8021a64 <puts>
+    return;
+ 8016404:	e07b      	b.n	80164fe <mem_free+0x10e>
+  }
+  if ((((mem_ptr_t)rmem) & (MEM_ALIGNMENT - 1)) != 0) {
+ 8016406:	687b      	ldr	r3, [r7, #4]
+ 8016408:	f003 0303 	and.w	r3, r3, #3
+ 801640c:	2b00      	cmp	r3, #0
+ 801640e:	d010      	beq.n	8016432 <mem_free+0x42>
+    LWIP_MEM_ILLEGAL_FREE("mem_free: sanity check alignment");
+ 8016410:	4b3d      	ldr	r3, [pc, #244]	; (8016508 <mem_free+0x118>)
+ 8016412:	f240 2273 	movw	r2, #627	; 0x273
+ 8016416:	493d      	ldr	r1, [pc, #244]	; (801650c <mem_free+0x11c>)
+ 8016418:	483d      	ldr	r0, [pc, #244]	; (8016510 <mem_free+0x120>)
+ 801641a:	f00b fab5 	bl	8021988 <iprintf>
+    LWIP_DEBUGF(MEM_DEBUG | LWIP_DBG_LEVEL_SEVERE, ("mem_free: sanity check alignment\n"));
+ 801641e:	483b      	ldr	r0, [pc, #236]	; (801650c <mem_free+0x11c>)
+ 8016420:	f00b fb20 	bl	8021a64 <puts>
+    /* protect mem stats from concurrent access */
+    MEM_STATS_INC_LOCKED(illegal);
+ 8016424:	f00b f916 	bl	8021654 <sys_arch_protect>
+ 8016428:	60f8      	str	r0, [r7, #12]
+ 801642a:	68f8      	ldr	r0, [r7, #12]
+ 801642c:	f00b f920 	bl	8021670 <sys_arch_unprotect>
+    return;
+ 8016430:	e065      	b.n	80164fe <mem_free+0x10e>
+  }
+
+  /* Get the corresponding struct mem: */
+  /* cast through void* to get rid of alignment warnings */
+  mem = (struct mem *)(void *)((u8_t *)rmem - (SIZEOF_STRUCT_MEM + MEM_SANITY_OFFSET));
+ 8016432:	687b      	ldr	r3, [r7, #4]
+ 8016434:	3b08      	subs	r3, #8
+ 8016436:	61fb      	str	r3, [r7, #28]
+
+  if ((u8_t *)mem < ram || (u8_t *)rmem + MIN_SIZE_ALIGNED > (u8_t *)ram_end) {
+ 8016438:	4b36      	ldr	r3, [pc, #216]	; (8016514 <mem_free+0x124>)
+ 801643a:	681b      	ldr	r3, [r3, #0]
+ 801643c:	69fa      	ldr	r2, [r7, #28]
+ 801643e:	429a      	cmp	r2, r3
+ 8016440:	d306      	bcc.n	8016450 <mem_free+0x60>
+ 8016442:	687b      	ldr	r3, [r7, #4]
+ 8016444:	f103 020c 	add.w	r2, r3, #12
+ 8016448:	4b33      	ldr	r3, [pc, #204]	; (8016518 <mem_free+0x128>)
+ 801644a:	681b      	ldr	r3, [r3, #0]
+ 801644c:	429a      	cmp	r2, r3
+ 801644e:	d910      	bls.n	8016472 <mem_free+0x82>
+    LWIP_MEM_ILLEGAL_FREE("mem_free: illegal memory");
+ 8016450:	4b2d      	ldr	r3, [pc, #180]	; (8016508 <mem_free+0x118>)
+ 8016452:	f240 227f 	movw	r2, #639	; 0x27f
+ 8016456:	4931      	ldr	r1, [pc, #196]	; (801651c <mem_free+0x12c>)
+ 8016458:	482d      	ldr	r0, [pc, #180]	; (8016510 <mem_free+0x120>)
+ 801645a:	f00b fa95 	bl	8021988 <iprintf>
+    LWIP_DEBUGF(MEM_DEBUG | LWIP_DBG_LEVEL_SEVERE, ("mem_free: illegal memory\n"));
+ 801645e:	482f      	ldr	r0, [pc, #188]	; (801651c <mem_free+0x12c>)
+ 8016460:	f00b fb00 	bl	8021a64 <puts>
+    /* protect mem stats from concurrent access */
+    MEM_STATS_INC_LOCKED(illegal);
+ 8016464:	f00b f8f6 	bl	8021654 <sys_arch_protect>
+ 8016468:	6138      	str	r0, [r7, #16]
+ 801646a:	6938      	ldr	r0, [r7, #16]
+ 801646c:	f00b f900 	bl	8021670 <sys_arch_unprotect>
+    return;
+ 8016470:	e045      	b.n	80164fe <mem_free+0x10e>
+  }
+#if MEM_OVERFLOW_CHECK
+  mem_overflow_check_element(mem);
+#endif
+  /* protect the heap from concurrent access */
+  LWIP_MEM_FREE_PROTECT();
+ 8016472:	482b      	ldr	r0, [pc, #172]	; (8016520 <mem_free+0x130>)
+ 8016474:	f00b f8ac 	bl	80215d0 <sys_mutex_lock>
+  /* mem has to be in a used state */
+  if (!mem->used) {
+ 8016478:	69fb      	ldr	r3, [r7, #28]
+ 801647a:	791b      	ldrb	r3, [r3, #4]
+ 801647c:	2b00      	cmp	r3, #0
+ 801647e:	d113      	bne.n	80164a8 <mem_free+0xb8>
+    LWIP_MEM_ILLEGAL_FREE("mem_free: illegal memory: double free");
+ 8016480:	4b21      	ldr	r3, [pc, #132]	; (8016508 <mem_free+0x118>)
+ 8016482:	f44f 7223 	mov.w	r2, #652	; 0x28c
+ 8016486:	4927      	ldr	r1, [pc, #156]	; (8016524 <mem_free+0x134>)
+ 8016488:	4821      	ldr	r0, [pc, #132]	; (8016510 <mem_free+0x120>)
+ 801648a:	f00b fa7d 	bl	8021988 <iprintf>
+    LWIP_MEM_FREE_UNPROTECT();
+ 801648e:	4824      	ldr	r0, [pc, #144]	; (8016520 <mem_free+0x130>)
+ 8016490:	f00b f8ad 	bl	80215ee <sys_mutex_unlock>
+    LWIP_DEBUGF(MEM_DEBUG | LWIP_DBG_LEVEL_SEVERE, ("mem_free: illegal memory: double free?\n"));
+ 8016494:	4824      	ldr	r0, [pc, #144]	; (8016528 <mem_free+0x138>)
+ 8016496:	f00b fae5 	bl	8021a64 <puts>
+    /* protect mem stats from concurrent access */
+    MEM_STATS_INC_LOCKED(illegal);
+ 801649a:	f00b f8db 	bl	8021654 <sys_arch_protect>
+ 801649e:	6178      	str	r0, [r7, #20]
+ 80164a0:	6978      	ldr	r0, [r7, #20]
+ 80164a2:	f00b f8e5 	bl	8021670 <sys_arch_unprotect>
+    return;
+ 80164a6:	e02a      	b.n	80164fe <mem_free+0x10e>
+  }
+
+  if (!mem_link_valid(mem)) {
+ 80164a8:	69f8      	ldr	r0, [r7, #28]
+ 80164aa:	f7ff ff63 	bl	8016374 <mem_link_valid>
+ 80164ae:	4603      	mov	r3, r0
+ 80164b0:	2b00      	cmp	r3, #0
+ 80164b2:	d113      	bne.n	80164dc <mem_free+0xec>
+    LWIP_MEM_ILLEGAL_FREE("mem_free: illegal memory: non-linked: double free");
+ 80164b4:	4b14      	ldr	r3, [pc, #80]	; (8016508 <mem_free+0x118>)
+ 80164b6:	f240 2295 	movw	r2, #661	; 0x295
+ 80164ba:	491c      	ldr	r1, [pc, #112]	; (801652c <mem_free+0x13c>)
+ 80164bc:	4814      	ldr	r0, [pc, #80]	; (8016510 <mem_free+0x120>)
+ 80164be:	f00b fa63 	bl	8021988 <iprintf>
+    LWIP_MEM_FREE_UNPROTECT();
+ 80164c2:	4817      	ldr	r0, [pc, #92]	; (8016520 <mem_free+0x130>)
+ 80164c4:	f00b f893 	bl	80215ee <sys_mutex_unlock>
+    LWIP_DEBUGF(MEM_DEBUG | LWIP_DBG_LEVEL_SEVERE, ("mem_free: illegal memory: non-linked: double free?\n"));
+ 80164c8:	4819      	ldr	r0, [pc, #100]	; (8016530 <mem_free+0x140>)
+ 80164ca:	f00b facb 	bl	8021a64 <puts>
+    /* protect mem stats from concurrent access */
+    MEM_STATS_INC_LOCKED(illegal);
+ 80164ce:	f00b f8c1 	bl	8021654 <sys_arch_protect>
+ 80164d2:	61b8      	str	r0, [r7, #24]
+ 80164d4:	69b8      	ldr	r0, [r7, #24]
+ 80164d6:	f00b f8cb 	bl	8021670 <sys_arch_unprotect>
+    return;
+ 80164da:	e010      	b.n	80164fe <mem_free+0x10e>
+  }
+
+  /* mem is now unused. */
+  mem->used = 0;
+ 80164dc:	69fb      	ldr	r3, [r7, #28]
+ 80164de:	2200      	movs	r2, #0
+ 80164e0:	711a      	strb	r2, [r3, #4]
+
+  if (mem < lfree) {
+ 80164e2:	4b14      	ldr	r3, [pc, #80]	; (8016534 <mem_free+0x144>)
+ 80164e4:	681b      	ldr	r3, [r3, #0]
+ 80164e6:	69fa      	ldr	r2, [r7, #28]
+ 80164e8:	429a      	cmp	r2, r3
+ 80164ea:	d202      	bcs.n	80164f2 <mem_free+0x102>
+    /* the newly freed struct is now the lowest */
+    lfree = mem;
+ 80164ec:	4a11      	ldr	r2, [pc, #68]	; (8016534 <mem_free+0x144>)
+ 80164ee:	69fb      	ldr	r3, [r7, #28]
+ 80164f0:	6013      	str	r3, [r2, #0]
+  }
+
+  MEM_STATS_DEC_USED(used, mem->next - (mem_size_t)(((u8_t *)mem - ram)));
+
+  /* finally, see if prev or next are free also */
+  plug_holes(mem);
+ 80164f2:	69f8      	ldr	r0, [r7, #28]
+ 80164f4:	f7ff fe4a 	bl	801618c <plug_holes>
+  MEM_SANITY();
+#if LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT
+  mem_free_count = 1;
+#endif /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */
+  LWIP_MEM_FREE_UNPROTECT();
+ 80164f8:	4809      	ldr	r0, [pc, #36]	; (8016520 <mem_free+0x130>)
+ 80164fa:	f00b f878 	bl	80215ee <sys_mutex_unlock>
+}
+ 80164fe:	3720      	adds	r7, #32
+ 8016500:	46bd      	mov	sp, r7
+ 8016502:	bd80      	pop	{r7, pc}
+ 8016504:	08023ee4 	.word	0x08023ee4
+ 8016508:	08023df4 	.word	0x08023df4
+ 801650c:	08023f04 	.word	0x08023f04
+ 8016510:	08023e3c 	.word	0x08023e3c
+ 8016514:	24013998 	.word	0x24013998
+ 8016518:	2401399c 	.word	0x2401399c
+ 801651c:	08023f28 	.word	0x08023f28
+ 8016520:	240139a0 	.word	0x240139a0
+ 8016524:	08023f44 	.word	0x08023f44
+ 8016528:	08023f6c 	.word	0x08023f6c
+ 801652c:	08023f94 	.word	0x08023f94
+ 8016530:	08023fc8 	.word	0x08023fc8
+ 8016534:	240139a4 	.word	0x240139a4
+
+08016538 <mem_trim>:
+ *         or NULL if newsize is > old size, in which case rmem is NOT touched
+ *         or freed!
+ */
+void *
+mem_trim(void *rmem, mem_size_t new_size)
+{
+ 8016538:	b580      	push	{r7, lr}
+ 801653a:	b088      	sub	sp, #32
+ 801653c:	af00      	add	r7, sp, #0
+ 801653e:	6078      	str	r0, [r7, #4]
+ 8016540:	460b      	mov	r3, r1
+ 8016542:	807b      	strh	r3, [r7, #2]
+  /* use the FREE_PROTECT here: it protects with sem OR SYS_ARCH_PROTECT */
+  LWIP_MEM_FREE_DECL_PROTECT();
+
+  /* Expand the size of the allocated memory region so that we can
+     adjust for alignment. */
+  newsize = (mem_size_t)LWIP_MEM_ALIGN_SIZE(new_size);
+ 8016544:	887b      	ldrh	r3, [r7, #2]
+ 8016546:	3303      	adds	r3, #3
+ 8016548:	b29b      	uxth	r3, r3
+ 801654a:	f023 0303 	bic.w	r3, r3, #3
+ 801654e:	83fb      	strh	r3, [r7, #30]
+  if (newsize < MIN_SIZE_ALIGNED) {
+ 8016550:	8bfb      	ldrh	r3, [r7, #30]
+ 8016552:	2b0b      	cmp	r3, #11
+ 8016554:	d801      	bhi.n	801655a <mem_trim+0x22>
+    /* every data block must be at least MIN_SIZE_ALIGNED long */
+    newsize = MIN_SIZE_ALIGNED;
+ 8016556:	230c      	movs	r3, #12
+ 8016558:	83fb      	strh	r3, [r7, #30]
+  }
+#if MEM_OVERFLOW_CHECK
+  newsize += MEM_SANITY_REGION_BEFORE_ALIGNED + MEM_SANITY_REGION_AFTER_ALIGNED;
+#endif
+  if ((newsize > MEM_SIZE_ALIGNED) || (newsize < new_size)) {
+ 801655a:	8bfb      	ldrh	r3, [r7, #30]
+ 801655c:	f647 52e8 	movw	r2, #32232	; 0x7de8
+ 8016560:	4293      	cmp	r3, r2
+ 8016562:	d803      	bhi.n	801656c <mem_trim+0x34>
+ 8016564:	8bfa      	ldrh	r2, [r7, #30]
+ 8016566:	887b      	ldrh	r3, [r7, #2]
+ 8016568:	429a      	cmp	r2, r3
+ 801656a:	d201      	bcs.n	8016570 <mem_trim+0x38>
+    return NULL;
+ 801656c:	2300      	movs	r3, #0
+ 801656e:	e0df      	b.n	8016730 <mem_trim+0x1f8>
+  }
+
+  LWIP_ASSERT("mem_trim: legal memory", (u8_t *)rmem >= (u8_t *)ram &&
+ 8016570:	4b71      	ldr	r3, [pc, #452]	; (8016738 <mem_trim+0x200>)
+ 8016572:	681b      	ldr	r3, [r3, #0]
+ 8016574:	687a      	ldr	r2, [r7, #4]
+ 8016576:	429a      	cmp	r2, r3
+ 8016578:	d304      	bcc.n	8016584 <mem_trim+0x4c>
+ 801657a:	4b70      	ldr	r3, [pc, #448]	; (801673c <mem_trim+0x204>)
+ 801657c:	681b      	ldr	r3, [r3, #0]
+ 801657e:	687a      	ldr	r2, [r7, #4]
+ 8016580:	429a      	cmp	r2, r3
+ 8016582:	d306      	bcc.n	8016592 <mem_trim+0x5a>
+ 8016584:	4b6e      	ldr	r3, [pc, #440]	; (8016740 <mem_trim+0x208>)
+ 8016586:	f240 22d1 	movw	r2, #721	; 0x2d1
+ 801658a:	496e      	ldr	r1, [pc, #440]	; (8016744 <mem_trim+0x20c>)
+ 801658c:	486e      	ldr	r0, [pc, #440]	; (8016748 <mem_trim+0x210>)
+ 801658e:	f00b f9fb 	bl	8021988 <iprintf>
+              (u8_t *)rmem < (u8_t *)ram_end);
+
+  if ((u8_t *)rmem < (u8_t *)ram || (u8_t *)rmem >= (u8_t *)ram_end) {
+ 8016592:	4b69      	ldr	r3, [pc, #420]	; (8016738 <mem_trim+0x200>)
+ 8016594:	681b      	ldr	r3, [r3, #0]
+ 8016596:	687a      	ldr	r2, [r7, #4]
+ 8016598:	429a      	cmp	r2, r3
+ 801659a:	d304      	bcc.n	80165a6 <mem_trim+0x6e>
+ 801659c:	4b67      	ldr	r3, [pc, #412]	; (801673c <mem_trim+0x204>)
+ 801659e:	681b      	ldr	r3, [r3, #0]
+ 80165a0:	687a      	ldr	r2, [r7, #4]
+ 80165a2:	429a      	cmp	r2, r3
+ 80165a4:	d30a      	bcc.n	80165bc <mem_trim+0x84>
+    LWIP_DEBUGF(MEM_DEBUG | LWIP_DBG_LEVEL_SEVERE, ("mem_trim: illegal memory\n"));
+ 80165a6:	4869      	ldr	r0, [pc, #420]	; (801674c <mem_trim+0x214>)
+ 80165a8:	f00b fa5c 	bl	8021a64 <puts>
+    /* protect mem stats from concurrent access */
+    MEM_STATS_INC_LOCKED(illegal);
+ 80165ac:	f00b f852 	bl	8021654 <sys_arch_protect>
+ 80165b0:	60b8      	str	r0, [r7, #8]
+ 80165b2:	68b8      	ldr	r0, [r7, #8]
+ 80165b4:	f00b f85c 	bl	8021670 <sys_arch_unprotect>
+    return rmem;
+ 80165b8:	687b      	ldr	r3, [r7, #4]
+ 80165ba:	e0b9      	b.n	8016730 <mem_trim+0x1f8>
+  }
+  /* Get the corresponding struct mem ... */
+  /* cast through void* to get rid of alignment warnings */
+  mem = (struct mem *)(void *)((u8_t *)rmem - (SIZEOF_STRUCT_MEM + MEM_SANITY_OFFSET));
+ 80165bc:	687b      	ldr	r3, [r7, #4]
+ 80165be:	3b08      	subs	r3, #8
+ 80165c0:	61bb      	str	r3, [r7, #24]
+#if MEM_OVERFLOW_CHECK
+  mem_overflow_check_element(mem);
+#endif
+  /* ... and its offset pointer */
+  ptr = mem_to_ptr(mem);
+ 80165c2:	69b8      	ldr	r0, [r7, #24]
+ 80165c4:	f7ff fdd0 	bl	8016168 <mem_to_ptr>
+ 80165c8:	4603      	mov	r3, r0
+ 80165ca:	82fb      	strh	r3, [r7, #22]
+
+  size = (mem_size_t)((mem_size_t)(mem->next - ptr) - (SIZEOF_STRUCT_MEM + MEM_SANITY_OVERHEAD));
+ 80165cc:	69bb      	ldr	r3, [r7, #24]
+ 80165ce:	881a      	ldrh	r2, [r3, #0]
+ 80165d0:	8afb      	ldrh	r3, [r7, #22]
+ 80165d2:	1ad3      	subs	r3, r2, r3
+ 80165d4:	b29b      	uxth	r3, r3
+ 80165d6:	3b08      	subs	r3, #8
+ 80165d8:	82bb      	strh	r3, [r7, #20]
+  LWIP_ASSERT("mem_trim can only shrink memory", newsize <= size);
+ 80165da:	8bfa      	ldrh	r2, [r7, #30]
+ 80165dc:	8abb      	ldrh	r3, [r7, #20]
+ 80165de:	429a      	cmp	r2, r3
+ 80165e0:	d906      	bls.n	80165f0 <mem_trim+0xb8>
+ 80165e2:	4b57      	ldr	r3, [pc, #348]	; (8016740 <mem_trim+0x208>)
+ 80165e4:	f44f 7239 	mov.w	r2, #740	; 0x2e4
+ 80165e8:	4959      	ldr	r1, [pc, #356]	; (8016750 <mem_trim+0x218>)
+ 80165ea:	4857      	ldr	r0, [pc, #348]	; (8016748 <mem_trim+0x210>)
+ 80165ec:	f00b f9cc 	bl	8021988 <iprintf>
+  if (newsize > size) {
+ 80165f0:	8bfa      	ldrh	r2, [r7, #30]
+ 80165f2:	8abb      	ldrh	r3, [r7, #20]
+ 80165f4:	429a      	cmp	r2, r3
+ 80165f6:	d901      	bls.n	80165fc <mem_trim+0xc4>
+    /* not supported */
+    return NULL;
+ 80165f8:	2300      	movs	r3, #0
+ 80165fa:	e099      	b.n	8016730 <mem_trim+0x1f8>
+  }
+  if (newsize == size) {
+ 80165fc:	8bfa      	ldrh	r2, [r7, #30]
+ 80165fe:	8abb      	ldrh	r3, [r7, #20]
+ 8016600:	429a      	cmp	r2, r3
+ 8016602:	d101      	bne.n	8016608 <mem_trim+0xd0>
+    /* No change in size, simply return */
+    return rmem;
+ 8016604:	687b      	ldr	r3, [r7, #4]
+ 8016606:	e093      	b.n	8016730 <mem_trim+0x1f8>
+  }
+
+  /* protect the heap from concurrent access */
+  LWIP_MEM_FREE_PROTECT();
+ 8016608:	4852      	ldr	r0, [pc, #328]	; (8016754 <mem_trim+0x21c>)
+ 801660a:	f00a ffe1 	bl	80215d0 <sys_mutex_lock>
+
+  mem2 = ptr_to_mem(mem->next);
+ 801660e:	69bb      	ldr	r3, [r7, #24]
+ 8016610:	881b      	ldrh	r3, [r3, #0]
+ 8016612:	4618      	mov	r0, r3
+ 8016614:	f7ff fd96 	bl	8016144 <ptr_to_mem>
+ 8016618:	6138      	str	r0, [r7, #16]
+  if (mem2->used == 0) {
+ 801661a:	693b      	ldr	r3, [r7, #16]
+ 801661c:	791b      	ldrb	r3, [r3, #4]
+ 801661e:	2b00      	cmp	r3, #0
+ 8016620:	d141      	bne.n	80166a6 <mem_trim+0x16e>
+    /* The next struct is unused, we can simply move it at little */
+    mem_size_t next;
+    LWIP_ASSERT("invalid next ptr", mem->next != MEM_SIZE_ALIGNED);
+ 8016622:	69bb      	ldr	r3, [r7, #24]
+ 8016624:	881b      	ldrh	r3, [r3, #0]
+ 8016626:	f647 52e8 	movw	r2, #32232	; 0x7de8
+ 801662a:	4293      	cmp	r3, r2
+ 801662c:	d106      	bne.n	801663c <mem_trim+0x104>
+ 801662e:	4b44      	ldr	r3, [pc, #272]	; (8016740 <mem_trim+0x208>)
+ 8016630:	f240 22f5 	movw	r2, #757	; 0x2f5
+ 8016634:	4948      	ldr	r1, [pc, #288]	; (8016758 <mem_trim+0x220>)
+ 8016636:	4844      	ldr	r0, [pc, #272]	; (8016748 <mem_trim+0x210>)
+ 8016638:	f00b f9a6 	bl	8021988 <iprintf>
+    /* remember the old next pointer */
+    next = mem2->next;
+ 801663c:	693b      	ldr	r3, [r7, #16]
+ 801663e:	881b      	ldrh	r3, [r3, #0]
+ 8016640:	81bb      	strh	r3, [r7, #12]
+    /* create new struct mem which is moved directly after the shrinked mem */
+    ptr2 = (mem_size_t)(ptr + SIZEOF_STRUCT_MEM + newsize);
+ 8016642:	8afa      	ldrh	r2, [r7, #22]
+ 8016644:	8bfb      	ldrh	r3, [r7, #30]
+ 8016646:	4413      	add	r3, r2
+ 8016648:	b29b      	uxth	r3, r3
+ 801664a:	3308      	adds	r3, #8
+ 801664c:	81fb      	strh	r3, [r7, #14]
+    if (lfree == mem2) {
+ 801664e:	4b43      	ldr	r3, [pc, #268]	; (801675c <mem_trim+0x224>)
+ 8016650:	681b      	ldr	r3, [r3, #0]
+ 8016652:	693a      	ldr	r2, [r7, #16]
+ 8016654:	429a      	cmp	r2, r3
+ 8016656:	d106      	bne.n	8016666 <mem_trim+0x12e>
+      lfree = ptr_to_mem(ptr2);
+ 8016658:	89fb      	ldrh	r3, [r7, #14]
+ 801665a:	4618      	mov	r0, r3
+ 801665c:	f7ff fd72 	bl	8016144 <ptr_to_mem>
+ 8016660:	4603      	mov	r3, r0
+ 8016662:	4a3e      	ldr	r2, [pc, #248]	; (801675c <mem_trim+0x224>)
+ 8016664:	6013      	str	r3, [r2, #0]
+    }
+    mem2 = ptr_to_mem(ptr2);
+ 8016666:	89fb      	ldrh	r3, [r7, #14]
+ 8016668:	4618      	mov	r0, r3
+ 801666a:	f7ff fd6b 	bl	8016144 <ptr_to_mem>
+ 801666e:	6138      	str	r0, [r7, #16]
+    mem2->used = 0;
+ 8016670:	693b      	ldr	r3, [r7, #16]
+ 8016672:	2200      	movs	r2, #0
+ 8016674:	711a      	strb	r2, [r3, #4]
+    /* restore the next pointer */
+    mem2->next = next;
+ 8016676:	693b      	ldr	r3, [r7, #16]
+ 8016678:	89ba      	ldrh	r2, [r7, #12]
+ 801667a:	801a      	strh	r2, [r3, #0]
+    /* link it back to mem */
+    mem2->prev = ptr;
+ 801667c:	693b      	ldr	r3, [r7, #16]
+ 801667e:	8afa      	ldrh	r2, [r7, #22]
+ 8016680:	805a      	strh	r2, [r3, #2]
+    /* link mem to it */
+    mem->next = ptr2;
+ 8016682:	69bb      	ldr	r3, [r7, #24]
+ 8016684:	89fa      	ldrh	r2, [r7, #14]
+ 8016686:	801a      	strh	r2, [r3, #0]
+    /* last thing to restore linked list: as we have moved mem2,
+     * let 'mem2->next->prev' point to mem2 again. but only if mem2->next is not
+     * the end of the heap */
+    if (mem2->next != MEM_SIZE_ALIGNED) {
+ 8016688:	693b      	ldr	r3, [r7, #16]
+ 801668a:	881b      	ldrh	r3, [r3, #0]
+ 801668c:	f647 52e8 	movw	r2, #32232	; 0x7de8
+ 8016690:	4293      	cmp	r3, r2
+ 8016692:	d049      	beq.n	8016728 <mem_trim+0x1f0>
+      ptr_to_mem(mem2->next)->prev = ptr2;
+ 8016694:	693b      	ldr	r3, [r7, #16]
+ 8016696:	881b      	ldrh	r3, [r3, #0]
+ 8016698:	4618      	mov	r0, r3
+ 801669a:	f7ff fd53 	bl	8016144 <ptr_to_mem>
+ 801669e:	4602      	mov	r2, r0
+ 80166a0:	89fb      	ldrh	r3, [r7, #14]
+ 80166a2:	8053      	strh	r3, [r2, #2]
+ 80166a4:	e040      	b.n	8016728 <mem_trim+0x1f0>
+    }
+    MEM_STATS_DEC_USED(used, (size - newsize));
+    /* no need to plug holes, we've already done that */
+  } else if (newsize + SIZEOF_STRUCT_MEM + MIN_SIZE_ALIGNED <= size) {
+ 80166a6:	8bfb      	ldrh	r3, [r7, #30]
+ 80166a8:	f103 0214 	add.w	r2, r3, #20
+ 80166ac:	8abb      	ldrh	r3, [r7, #20]
+ 80166ae:	429a      	cmp	r2, r3
+ 80166b0:	d83a      	bhi.n	8016728 <mem_trim+0x1f0>
+     * Old size ('size') must be big enough to contain at least 'newsize' plus a struct mem
+     * ('SIZEOF_STRUCT_MEM') with some data ('MIN_SIZE_ALIGNED').
+     * @todo we could leave out MIN_SIZE_ALIGNED. We would create an empty
+     *       region that couldn't hold data, but when mem->next gets freed,
+     *       the 2 regions would be combined, resulting in more free memory */
+    ptr2 = (mem_size_t)(ptr + SIZEOF_STRUCT_MEM + newsize);
+ 80166b2:	8afa      	ldrh	r2, [r7, #22]
+ 80166b4:	8bfb      	ldrh	r3, [r7, #30]
+ 80166b6:	4413      	add	r3, r2
+ 80166b8:	b29b      	uxth	r3, r3
+ 80166ba:	3308      	adds	r3, #8
+ 80166bc:	81fb      	strh	r3, [r7, #14]
+    LWIP_ASSERT("invalid next ptr", mem->next != MEM_SIZE_ALIGNED);
+ 80166be:	69bb      	ldr	r3, [r7, #24]
+ 80166c0:	881b      	ldrh	r3, [r3, #0]
+ 80166c2:	f647 52e8 	movw	r2, #32232	; 0x7de8
+ 80166c6:	4293      	cmp	r3, r2
+ 80166c8:	d106      	bne.n	80166d8 <mem_trim+0x1a0>
+ 80166ca:	4b1d      	ldr	r3, [pc, #116]	; (8016740 <mem_trim+0x208>)
+ 80166cc:	f240 3216 	movw	r2, #790	; 0x316
+ 80166d0:	4921      	ldr	r1, [pc, #132]	; (8016758 <mem_trim+0x220>)
+ 80166d2:	481d      	ldr	r0, [pc, #116]	; (8016748 <mem_trim+0x210>)
+ 80166d4:	f00b f958 	bl	8021988 <iprintf>
+    mem2 = ptr_to_mem(ptr2);
+ 80166d8:	89fb      	ldrh	r3, [r7, #14]
+ 80166da:	4618      	mov	r0, r3
+ 80166dc:	f7ff fd32 	bl	8016144 <ptr_to_mem>
+ 80166e0:	6138      	str	r0, [r7, #16]
+    if (mem2 < lfree) {
+ 80166e2:	4b1e      	ldr	r3, [pc, #120]	; (801675c <mem_trim+0x224>)
+ 80166e4:	681b      	ldr	r3, [r3, #0]
+ 80166e6:	693a      	ldr	r2, [r7, #16]
+ 80166e8:	429a      	cmp	r2, r3
+ 80166ea:	d202      	bcs.n	80166f2 <mem_trim+0x1ba>
+      lfree = mem2;
+ 80166ec:	4a1b      	ldr	r2, [pc, #108]	; (801675c <mem_trim+0x224>)
+ 80166ee:	693b      	ldr	r3, [r7, #16]
+ 80166f0:	6013      	str	r3, [r2, #0]
+    }
+    mem2->used = 0;
+ 80166f2:	693b      	ldr	r3, [r7, #16]
+ 80166f4:	2200      	movs	r2, #0
+ 80166f6:	711a      	strb	r2, [r3, #4]
+    mem2->next = mem->next;
+ 80166f8:	69bb      	ldr	r3, [r7, #24]
+ 80166fa:	881a      	ldrh	r2, [r3, #0]
+ 80166fc:	693b      	ldr	r3, [r7, #16]
+ 80166fe:	801a      	strh	r2, [r3, #0]
+    mem2->prev = ptr;
+ 8016700:	693b      	ldr	r3, [r7, #16]
+ 8016702:	8afa      	ldrh	r2, [r7, #22]
+ 8016704:	805a      	strh	r2, [r3, #2]
+    mem->next = ptr2;
+ 8016706:	69bb      	ldr	r3, [r7, #24]
+ 8016708:	89fa      	ldrh	r2, [r7, #14]
+ 801670a:	801a      	strh	r2, [r3, #0]
+    if (mem2->next != MEM_SIZE_ALIGNED) {
+ 801670c:	693b      	ldr	r3, [r7, #16]
+ 801670e:	881b      	ldrh	r3, [r3, #0]
+ 8016710:	f647 52e8 	movw	r2, #32232	; 0x7de8
+ 8016714:	4293      	cmp	r3, r2
+ 8016716:	d007      	beq.n	8016728 <mem_trim+0x1f0>
+      ptr_to_mem(mem2->next)->prev = ptr2;
+ 8016718:	693b      	ldr	r3, [r7, #16]
+ 801671a:	881b      	ldrh	r3, [r3, #0]
+ 801671c:	4618      	mov	r0, r3
+ 801671e:	f7ff fd11 	bl	8016144 <ptr_to_mem>
+ 8016722:	4602      	mov	r2, r0
+ 8016724:	89fb      	ldrh	r3, [r7, #14]
+ 8016726:	8053      	strh	r3, [r2, #2]
+#endif
+  MEM_SANITY();
+#if LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT
+  mem_free_count = 1;
+#endif /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */
+  LWIP_MEM_FREE_UNPROTECT();
+ 8016728:	480a      	ldr	r0, [pc, #40]	; (8016754 <mem_trim+0x21c>)
+ 801672a:	f00a ff60 	bl	80215ee <sys_mutex_unlock>
+  return rmem;
+ 801672e:	687b      	ldr	r3, [r7, #4]
+}
+ 8016730:	4618      	mov	r0, r3
+ 8016732:	3720      	adds	r7, #32
+ 8016734:	46bd      	mov	sp, r7
+ 8016736:	bd80      	pop	{r7, pc}
+ 8016738:	24013998 	.word	0x24013998
+ 801673c:	2401399c 	.word	0x2401399c
+ 8016740:	08023df4 	.word	0x08023df4
+ 8016744:	08023ffc 	.word	0x08023ffc
+ 8016748:	08023e3c 	.word	0x08023e3c
+ 801674c:	08024014 	.word	0x08024014
+ 8016750:	08024030 	.word	0x08024030
+ 8016754:	240139a0 	.word	0x240139a0
+ 8016758:	08024050 	.word	0x08024050
+ 801675c:	240139a4 	.word	0x240139a4
+
+08016760 <mem_malloc>:
+ *
+ * Note that the returned value will always be aligned (as defined by MEM_ALIGNMENT).
+ */
+void *
+mem_malloc(mem_size_t size_in)
+{
+ 8016760:	b580      	push	{r7, lr}
+ 8016762:	b088      	sub	sp, #32
+ 8016764:	af00      	add	r7, sp, #0
+ 8016766:	4603      	mov	r3, r0
+ 8016768:	80fb      	strh	r3, [r7, #6]
+#if LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT
+  u8_t local_mem_free_count = 0;
+#endif /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */
+  LWIP_MEM_ALLOC_DECL_PROTECT();
+
+  if (size_in == 0) {
+ 801676a:	88fb      	ldrh	r3, [r7, #6]
+ 801676c:	2b00      	cmp	r3, #0
+ 801676e:	d101      	bne.n	8016774 <mem_malloc+0x14>
+    return NULL;
+ 8016770:	2300      	movs	r3, #0
+ 8016772:	e0ec      	b.n	801694e <mem_malloc+0x1ee>
+  }
+
+  /* Expand the size of the allocated memory region so that we can
+     adjust for alignment. */
+  size = (mem_size_t)LWIP_MEM_ALIGN_SIZE(size_in);
+ 8016774:	88fb      	ldrh	r3, [r7, #6]
+ 8016776:	3303      	adds	r3, #3
+ 8016778:	b29b      	uxth	r3, r3
+ 801677a:	f023 0303 	bic.w	r3, r3, #3
+ 801677e:	83bb      	strh	r3, [r7, #28]
+  if (size < MIN_SIZE_ALIGNED) {
+ 8016780:	8bbb      	ldrh	r3, [r7, #28]
+ 8016782:	2b0b      	cmp	r3, #11
+ 8016784:	d801      	bhi.n	801678a <mem_malloc+0x2a>
+    /* every data block must be at least MIN_SIZE_ALIGNED long */
+    size = MIN_SIZE_ALIGNED;
+ 8016786:	230c      	movs	r3, #12
+ 8016788:	83bb      	strh	r3, [r7, #28]
+  }
+#if MEM_OVERFLOW_CHECK
+  size += MEM_SANITY_REGION_BEFORE_ALIGNED + MEM_SANITY_REGION_AFTER_ALIGNED;
+#endif
+  if ((size > MEM_SIZE_ALIGNED) || (size < size_in)) {
+ 801678a:	8bbb      	ldrh	r3, [r7, #28]
+ 801678c:	f647 52e8 	movw	r2, #32232	; 0x7de8
+ 8016790:	4293      	cmp	r3, r2
+ 8016792:	d803      	bhi.n	801679c <mem_malloc+0x3c>
+ 8016794:	8bba      	ldrh	r2, [r7, #28]
+ 8016796:	88fb      	ldrh	r3, [r7, #6]
+ 8016798:	429a      	cmp	r2, r3
+ 801679a:	d201      	bcs.n	80167a0 <mem_malloc+0x40>
+    return NULL;
+ 801679c:	2300      	movs	r3, #0
+ 801679e:	e0d6      	b.n	801694e <mem_malloc+0x1ee>
+  }
+
+  /* protect the heap from concurrent access */
+  sys_mutex_lock(&mem_mutex);
+ 80167a0:	486d      	ldr	r0, [pc, #436]	; (8016958 <mem_malloc+0x1f8>)
+ 80167a2:	f00a ff15 	bl	80215d0 <sys_mutex_lock>
+#endif /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */
+
+    /* Scan through the heap searching for a free block that is big enough,
+     * beginning with the lowest free block.
+     */
+    for (ptr = mem_to_ptr(lfree); ptr < MEM_SIZE_ALIGNED - size;
+ 80167a6:	4b6d      	ldr	r3, [pc, #436]	; (801695c <mem_malloc+0x1fc>)
+ 80167a8:	681b      	ldr	r3, [r3, #0]
+ 80167aa:	4618      	mov	r0, r3
+ 80167ac:	f7ff fcdc 	bl	8016168 <mem_to_ptr>
+ 80167b0:	4603      	mov	r3, r0
+ 80167b2:	83fb      	strh	r3, [r7, #30]
+ 80167b4:	e0b9      	b.n	801692a <mem_malloc+0x1ca>
+         ptr = ptr_to_mem(ptr)->next) {
+      mem = ptr_to_mem(ptr);
+ 80167b6:	8bfb      	ldrh	r3, [r7, #30]
+ 80167b8:	4618      	mov	r0, r3
+ 80167ba:	f7ff fcc3 	bl	8016144 <ptr_to_mem>
+ 80167be:	6178      	str	r0, [r7, #20]
+        local_mem_free_count = 1;
+        break;
+      }
+#endif /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */
+
+      if ((!mem->used) &&
+ 80167c0:	697b      	ldr	r3, [r7, #20]
+ 80167c2:	791b      	ldrb	r3, [r3, #4]
+ 80167c4:	2b00      	cmp	r3, #0
+ 80167c6:	f040 80a9 	bne.w	801691c <mem_malloc+0x1bc>
+          (mem->next - (ptr + SIZEOF_STRUCT_MEM)) >= size) {
+ 80167ca:	697b      	ldr	r3, [r7, #20]
+ 80167cc:	881b      	ldrh	r3, [r3, #0]
+ 80167ce:	461a      	mov	r2, r3
+ 80167d0:	8bfb      	ldrh	r3, [r7, #30]
+ 80167d2:	1ad3      	subs	r3, r2, r3
+ 80167d4:	f1a3 0208 	sub.w	r2, r3, #8
+ 80167d8:	8bbb      	ldrh	r3, [r7, #28]
+      if ((!mem->used) &&
+ 80167da:	429a      	cmp	r2, r3
+ 80167dc:	f0c0 809e 	bcc.w	801691c <mem_malloc+0x1bc>
+        /* mem is not used and at least perfect fit is possible:
+         * mem->next - (ptr + SIZEOF_STRUCT_MEM) gives us the 'user data size' of mem */
+
+        if (mem->next - (ptr + SIZEOF_STRUCT_MEM) >= (size + SIZEOF_STRUCT_MEM + MIN_SIZE_ALIGNED)) {
+ 80167e0:	697b      	ldr	r3, [r7, #20]
+ 80167e2:	881b      	ldrh	r3, [r3, #0]
+ 80167e4:	461a      	mov	r2, r3
+ 80167e6:	8bfb      	ldrh	r3, [r7, #30]
+ 80167e8:	1ad3      	subs	r3, r2, r3
+ 80167ea:	f1a3 0208 	sub.w	r2, r3, #8
+ 80167ee:	8bbb      	ldrh	r3, [r7, #28]
+ 80167f0:	3314      	adds	r3, #20
+ 80167f2:	429a      	cmp	r2, r3
+ 80167f4:	d335      	bcc.n	8016862 <mem_malloc+0x102>
+           * struct mem would fit in but no data between mem2 and mem2->next
+           * @todo we could leave out MIN_SIZE_ALIGNED. We would create an empty
+           *       region that couldn't hold data, but when mem->next gets freed,
+           *       the 2 regions would be combined, resulting in more free memory
+           */
+          ptr2 = (mem_size_t)(ptr + SIZEOF_STRUCT_MEM + size);
+ 80167f6:	8bfa      	ldrh	r2, [r7, #30]
+ 80167f8:	8bbb      	ldrh	r3, [r7, #28]
+ 80167fa:	4413      	add	r3, r2
+ 80167fc:	b29b      	uxth	r3, r3
+ 80167fe:	3308      	adds	r3, #8
+ 8016800:	827b      	strh	r3, [r7, #18]
+          LWIP_ASSERT("invalid next ptr",ptr2 != MEM_SIZE_ALIGNED);
+ 8016802:	8a7b      	ldrh	r3, [r7, #18]
+ 8016804:	f647 52e8 	movw	r2, #32232	; 0x7de8
+ 8016808:	4293      	cmp	r3, r2
+ 801680a:	d106      	bne.n	801681a <mem_malloc+0xba>
+ 801680c:	4b54      	ldr	r3, [pc, #336]	; (8016960 <mem_malloc+0x200>)
+ 801680e:	f240 3287 	movw	r2, #903	; 0x387
+ 8016812:	4954      	ldr	r1, [pc, #336]	; (8016964 <mem_malloc+0x204>)
+ 8016814:	4854      	ldr	r0, [pc, #336]	; (8016968 <mem_malloc+0x208>)
+ 8016816:	f00b f8b7 	bl	8021988 <iprintf>
+          /* create mem2 struct */
+          mem2 = ptr_to_mem(ptr2);
+ 801681a:	8a7b      	ldrh	r3, [r7, #18]
+ 801681c:	4618      	mov	r0, r3
+ 801681e:	f7ff fc91 	bl	8016144 <ptr_to_mem>
+ 8016822:	60f8      	str	r0, [r7, #12]
+          mem2->used = 0;
+ 8016824:	68fb      	ldr	r3, [r7, #12]
+ 8016826:	2200      	movs	r2, #0
+ 8016828:	711a      	strb	r2, [r3, #4]
+          mem2->next = mem->next;
+ 801682a:	697b      	ldr	r3, [r7, #20]
+ 801682c:	881a      	ldrh	r2, [r3, #0]
+ 801682e:	68fb      	ldr	r3, [r7, #12]
+ 8016830:	801a      	strh	r2, [r3, #0]
+          mem2->prev = ptr;
+ 8016832:	68fb      	ldr	r3, [r7, #12]
+ 8016834:	8bfa      	ldrh	r2, [r7, #30]
+ 8016836:	805a      	strh	r2, [r3, #2]
+          /* and insert it between mem and mem->next */
+          mem->next = ptr2;
+ 8016838:	697b      	ldr	r3, [r7, #20]
+ 801683a:	8a7a      	ldrh	r2, [r7, #18]
+ 801683c:	801a      	strh	r2, [r3, #0]
+          mem->used = 1;
+ 801683e:	697b      	ldr	r3, [r7, #20]
+ 8016840:	2201      	movs	r2, #1
+ 8016842:	711a      	strb	r2, [r3, #4]
+
+          if (mem2->next != MEM_SIZE_ALIGNED) {
+ 8016844:	68fb      	ldr	r3, [r7, #12]
+ 8016846:	881b      	ldrh	r3, [r3, #0]
+ 8016848:	f647 52e8 	movw	r2, #32232	; 0x7de8
+ 801684c:	4293      	cmp	r3, r2
+ 801684e:	d00b      	beq.n	8016868 <mem_malloc+0x108>
+            ptr_to_mem(mem2->next)->prev = ptr2;
+ 8016850:	68fb      	ldr	r3, [r7, #12]
+ 8016852:	881b      	ldrh	r3, [r3, #0]
+ 8016854:	4618      	mov	r0, r3
+ 8016856:	f7ff fc75 	bl	8016144 <ptr_to_mem>
+ 801685a:	4602      	mov	r2, r0
+ 801685c:	8a7b      	ldrh	r3, [r7, #18]
+ 801685e:	8053      	strh	r3, [r2, #2]
+ 8016860:	e002      	b.n	8016868 <mem_malloc+0x108>
+           * take care of this).
+           * -> near fit or exact fit: do not split, no mem2 creation
+           * also can't move mem->next directly behind mem, since mem->next
+           * will always be used at this point!
+           */
+          mem->used = 1;
+ 8016862:	697b      	ldr	r3, [r7, #20]
+ 8016864:	2201      	movs	r2, #1
+ 8016866:	711a      	strb	r2, [r3, #4]
+          MEM_STATS_INC_USED(used, mem->next - mem_to_ptr(mem));
+        }
+#if LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT
+mem_malloc_adjust_lfree:
+#endif /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */
+        if (mem == lfree) {
+ 8016868:	4b3c      	ldr	r3, [pc, #240]	; (801695c <mem_malloc+0x1fc>)
+ 801686a:	681b      	ldr	r3, [r3, #0]
+ 801686c:	697a      	ldr	r2, [r7, #20]
+ 801686e:	429a      	cmp	r2, r3
+ 8016870:	d127      	bne.n	80168c2 <mem_malloc+0x162>
+          struct mem *cur = lfree;
+ 8016872:	4b3a      	ldr	r3, [pc, #232]	; (801695c <mem_malloc+0x1fc>)
+ 8016874:	681b      	ldr	r3, [r3, #0]
+ 8016876:	61bb      	str	r3, [r7, #24]
+          /* Find next free block after mem and update lowest free pointer */
+          while (cur->used && cur != ram_end) {
+ 8016878:	e005      	b.n	8016886 <mem_malloc+0x126>
+              /* If mem_free or mem_trim have run, we have to restart since they
+                 could have altered our current struct mem or lfree. */
+              goto mem_malloc_adjust_lfree;
+            }
+#endif /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */
+            cur = ptr_to_mem(cur->next);
+ 801687a:	69bb      	ldr	r3, [r7, #24]
+ 801687c:	881b      	ldrh	r3, [r3, #0]
+ 801687e:	4618      	mov	r0, r3
+ 8016880:	f7ff fc60 	bl	8016144 <ptr_to_mem>
+ 8016884:	61b8      	str	r0, [r7, #24]
+          while (cur->used && cur != ram_end) {
+ 8016886:	69bb      	ldr	r3, [r7, #24]
+ 8016888:	791b      	ldrb	r3, [r3, #4]
+ 801688a:	2b00      	cmp	r3, #0
+ 801688c:	d004      	beq.n	8016898 <mem_malloc+0x138>
+ 801688e:	4b37      	ldr	r3, [pc, #220]	; (801696c <mem_malloc+0x20c>)
+ 8016890:	681b      	ldr	r3, [r3, #0]
+ 8016892:	69ba      	ldr	r2, [r7, #24]
+ 8016894:	429a      	cmp	r2, r3
+ 8016896:	d1f0      	bne.n	801687a <mem_malloc+0x11a>
+          }
+          lfree = cur;
+ 8016898:	4a30      	ldr	r2, [pc, #192]	; (801695c <mem_malloc+0x1fc>)
+ 801689a:	69bb      	ldr	r3, [r7, #24]
+ 801689c:	6013      	str	r3, [r2, #0]
+          LWIP_ASSERT("mem_malloc: !lfree->used", ((lfree == ram_end) || (!lfree->used)));
+ 801689e:	4b2f      	ldr	r3, [pc, #188]	; (801695c <mem_malloc+0x1fc>)
+ 80168a0:	681a      	ldr	r2, [r3, #0]
+ 80168a2:	4b32      	ldr	r3, [pc, #200]	; (801696c <mem_malloc+0x20c>)
+ 80168a4:	681b      	ldr	r3, [r3, #0]
+ 80168a6:	429a      	cmp	r2, r3
+ 80168a8:	d00b      	beq.n	80168c2 <mem_malloc+0x162>
+ 80168aa:	4b2c      	ldr	r3, [pc, #176]	; (801695c <mem_malloc+0x1fc>)
+ 80168ac:	681b      	ldr	r3, [r3, #0]
+ 80168ae:	791b      	ldrb	r3, [r3, #4]
+ 80168b0:	2b00      	cmp	r3, #0
+ 80168b2:	d006      	beq.n	80168c2 <mem_malloc+0x162>
+ 80168b4:	4b2a      	ldr	r3, [pc, #168]	; (8016960 <mem_malloc+0x200>)
+ 80168b6:	f240 32b5 	movw	r2, #949	; 0x3b5
+ 80168ba:	492d      	ldr	r1, [pc, #180]	; (8016970 <mem_malloc+0x210>)
+ 80168bc:	482a      	ldr	r0, [pc, #168]	; (8016968 <mem_malloc+0x208>)
+ 80168be:	f00b f863 	bl	8021988 <iprintf>
+        }
+        LWIP_MEM_ALLOC_UNPROTECT();
+        sys_mutex_unlock(&mem_mutex);
+ 80168c2:	4825      	ldr	r0, [pc, #148]	; (8016958 <mem_malloc+0x1f8>)
+ 80168c4:	f00a fe93 	bl	80215ee <sys_mutex_unlock>
+        LWIP_ASSERT("mem_malloc: allocated memory not above ram_end.",
+ 80168c8:	8bba      	ldrh	r2, [r7, #28]
+ 80168ca:	697b      	ldr	r3, [r7, #20]
+ 80168cc:	4413      	add	r3, r2
+ 80168ce:	3308      	adds	r3, #8
+ 80168d0:	4a26      	ldr	r2, [pc, #152]	; (801696c <mem_malloc+0x20c>)
+ 80168d2:	6812      	ldr	r2, [r2, #0]
+ 80168d4:	4293      	cmp	r3, r2
+ 80168d6:	d906      	bls.n	80168e6 <mem_malloc+0x186>
+ 80168d8:	4b21      	ldr	r3, [pc, #132]	; (8016960 <mem_malloc+0x200>)
+ 80168da:	f240 32b9 	movw	r2, #953	; 0x3b9
+ 80168de:	4925      	ldr	r1, [pc, #148]	; (8016974 <mem_malloc+0x214>)
+ 80168e0:	4821      	ldr	r0, [pc, #132]	; (8016968 <mem_malloc+0x208>)
+ 80168e2:	f00b f851 	bl	8021988 <iprintf>
+                    (mem_ptr_t)mem + SIZEOF_STRUCT_MEM + size <= (mem_ptr_t)ram_end);
+        LWIP_ASSERT("mem_malloc: allocated memory properly aligned.",
+ 80168e6:	697b      	ldr	r3, [r7, #20]
+ 80168e8:	f003 0303 	and.w	r3, r3, #3
+ 80168ec:	2b00      	cmp	r3, #0
+ 80168ee:	d006      	beq.n	80168fe <mem_malloc+0x19e>
+ 80168f0:	4b1b      	ldr	r3, [pc, #108]	; (8016960 <mem_malloc+0x200>)
+ 80168f2:	f240 32bb 	movw	r2, #955	; 0x3bb
+ 80168f6:	4920      	ldr	r1, [pc, #128]	; (8016978 <mem_malloc+0x218>)
+ 80168f8:	481b      	ldr	r0, [pc, #108]	; (8016968 <mem_malloc+0x208>)
+ 80168fa:	f00b f845 	bl	8021988 <iprintf>
+                    ((mem_ptr_t)mem + SIZEOF_STRUCT_MEM) % MEM_ALIGNMENT == 0);
+        LWIP_ASSERT("mem_malloc: sanity check alignment",
+ 80168fe:	697b      	ldr	r3, [r7, #20]
+ 8016900:	f003 0303 	and.w	r3, r3, #3
+ 8016904:	2b00      	cmp	r3, #0
+ 8016906:	d006      	beq.n	8016916 <mem_malloc+0x1b6>
+ 8016908:	4b15      	ldr	r3, [pc, #84]	; (8016960 <mem_malloc+0x200>)
+ 801690a:	f240 32bd 	movw	r2, #957	; 0x3bd
+ 801690e:	491b      	ldr	r1, [pc, #108]	; (801697c <mem_malloc+0x21c>)
+ 8016910:	4815      	ldr	r0, [pc, #84]	; (8016968 <mem_malloc+0x208>)
+ 8016912:	f00b f839 	bl	8021988 <iprintf>
+
+#if MEM_OVERFLOW_CHECK
+        mem_overflow_init_element(mem, size_in);
+#endif
+        MEM_SANITY();
+        return (u8_t *)mem + SIZEOF_STRUCT_MEM + MEM_SANITY_OFFSET;
+ 8016916:	697b      	ldr	r3, [r7, #20]
+ 8016918:	3308      	adds	r3, #8
+ 801691a:	e018      	b.n	801694e <mem_malloc+0x1ee>
+         ptr = ptr_to_mem(ptr)->next) {
+ 801691c:	8bfb      	ldrh	r3, [r7, #30]
+ 801691e:	4618      	mov	r0, r3
+ 8016920:	f7ff fc10 	bl	8016144 <ptr_to_mem>
+ 8016924:	4603      	mov	r3, r0
+ 8016926:	881b      	ldrh	r3, [r3, #0]
+ 8016928:	83fb      	strh	r3, [r7, #30]
+    for (ptr = mem_to_ptr(lfree); ptr < MEM_SIZE_ALIGNED - size;
+ 801692a:	8bfa      	ldrh	r2, [r7, #30]
+ 801692c:	8bb9      	ldrh	r1, [r7, #28]
+ 801692e:	f647 53e8 	movw	r3, #32232	; 0x7de8
+ 8016932:	1a5b      	subs	r3, r3, r1
+ 8016934:	429a      	cmp	r2, r3
+ 8016936:	f4ff af3e 	bcc.w	80167b6 <mem_malloc+0x56>
+    /* if we got interrupted by a mem_free, try again */
+  } while (local_mem_free_count != 0);
+#endif /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */
+  MEM_STATS_INC(err);
+  LWIP_MEM_ALLOC_UNPROTECT();
+  sys_mutex_unlock(&mem_mutex);
+ 801693a:	4807      	ldr	r0, [pc, #28]	; (8016958 <mem_malloc+0x1f8>)
+ 801693c:	f00a fe57 	bl	80215ee <sys_mutex_unlock>
+  LWIP_DEBUGF(MEM_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("mem_malloc: could not allocate %"S16_F" bytes\n", (s16_t)size));
+ 8016940:	f9b7 301c 	ldrsh.w	r3, [r7, #28]
+ 8016944:	4619      	mov	r1, r3
+ 8016946:	480e      	ldr	r0, [pc, #56]	; (8016980 <mem_malloc+0x220>)
+ 8016948:	f00b f81e 	bl	8021988 <iprintf>
+  return NULL;
+ 801694c:	2300      	movs	r3, #0
+}
+ 801694e:	4618      	mov	r0, r3
+ 8016950:	3720      	adds	r7, #32
+ 8016952:	46bd      	mov	sp, r7
+ 8016954:	bd80      	pop	{r7, pc}
+ 8016956:	bf00      	nop
+ 8016958:	240139a0 	.word	0x240139a0
+ 801695c:	240139a4 	.word	0x240139a4
+ 8016960:	08023df4 	.word	0x08023df4
+ 8016964:	08024050 	.word	0x08024050
+ 8016968:	08023e3c 	.word	0x08023e3c
+ 801696c:	2401399c 	.word	0x2401399c
+ 8016970:	08024064 	.word	0x08024064
+ 8016974:	08024080 	.word	0x08024080
+ 8016978:	080240b0 	.word	0x080240b0
+ 801697c:	080240e0 	.word	0x080240e0
+ 8016980:	08024104 	.word	0x08024104
+
+08016984 <memp_init_pool>:
+ *
+ * @param desc pool to initialize
+ */
+void
+memp_init_pool(const struct memp_desc *desc)
+{
+ 8016984:	b480      	push	{r7}
+ 8016986:	b085      	sub	sp, #20
+ 8016988:	af00      	add	r7, sp, #0
+ 801698a:	6078      	str	r0, [r7, #4]
+  LWIP_UNUSED_ARG(desc);
+#else
+  int i;
+  struct memp *memp;
+
+  *desc->tab = NULL;
+ 801698c:	687b      	ldr	r3, [r7, #4]
+ 801698e:	68db      	ldr	r3, [r3, #12]
+ 8016990:	2200      	movs	r2, #0
+ 8016992:	601a      	str	r2, [r3, #0]
+  memp = (struct memp *)LWIP_MEM_ALIGN(desc->base);
+ 8016994:	687b      	ldr	r3, [r7, #4]
+ 8016996:	689b      	ldr	r3, [r3, #8]
+ 8016998:	3303      	adds	r3, #3
+ 801699a:	f023 0303 	bic.w	r3, r3, #3
+ 801699e:	60bb      	str	r3, [r7, #8]
+                                       + MEM_SANITY_REGION_AFTER_ALIGNED
+#endif
+                                      ));
+#endif
+  /* create a linked list of memp elements */
+  for (i = 0; i < desc->num; ++i) {
+ 80169a0:	2300      	movs	r3, #0
+ 80169a2:	60fb      	str	r3, [r7, #12]
+ 80169a4:	e011      	b.n	80169ca <memp_init_pool+0x46>
+    memp->next = *desc->tab;
+ 80169a6:	687b      	ldr	r3, [r7, #4]
+ 80169a8:	68db      	ldr	r3, [r3, #12]
+ 80169aa:	681a      	ldr	r2, [r3, #0]
+ 80169ac:	68bb      	ldr	r3, [r7, #8]
+ 80169ae:	601a      	str	r2, [r3, #0]
+    *desc->tab = memp;
+ 80169b0:	687b      	ldr	r3, [r7, #4]
+ 80169b2:	68db      	ldr	r3, [r3, #12]
+ 80169b4:	68ba      	ldr	r2, [r7, #8]
+ 80169b6:	601a      	str	r2, [r3, #0]
+#if MEMP_OVERFLOW_CHECK
+    memp_overflow_init_element(memp, desc);
+#endif /* MEMP_OVERFLOW_CHECK */
+    /* cast through void* to get rid of alignment warnings */
+    memp = (struct memp *)(void *)((u8_t *)memp + MEMP_SIZE + desc->size
+ 80169b8:	687b      	ldr	r3, [r7, #4]
+ 80169ba:	889b      	ldrh	r3, [r3, #4]
+ 80169bc:	461a      	mov	r2, r3
+ 80169be:	68bb      	ldr	r3, [r7, #8]
+ 80169c0:	4413      	add	r3, r2
+ 80169c2:	60bb      	str	r3, [r7, #8]
+  for (i = 0; i < desc->num; ++i) {
+ 80169c4:	68fb      	ldr	r3, [r7, #12]
+ 80169c6:	3301      	adds	r3, #1
+ 80169c8:	60fb      	str	r3, [r7, #12]
+ 80169ca:	687b      	ldr	r3, [r7, #4]
+ 80169cc:	88db      	ldrh	r3, [r3, #6]
+ 80169ce:	461a      	mov	r2, r3
+ 80169d0:	68fb      	ldr	r3, [r7, #12]
+ 80169d2:	4293      	cmp	r3, r2
+ 80169d4:	dbe7      	blt.n	80169a6 <memp_init_pool+0x22>
+#endif /* !MEMP_MEM_MALLOC */
+
+#if MEMP_STATS && (defined(LWIP_DEBUG) || LWIP_STATS_DISPLAY)
+  desc->stats->name  = desc->desc;
+#endif /* MEMP_STATS && (defined(LWIP_DEBUG) || LWIP_STATS_DISPLAY) */
+}
+ 80169d6:	bf00      	nop
+ 80169d8:	bf00      	nop
+ 80169da:	3714      	adds	r7, #20
+ 80169dc:	46bd      	mov	sp, r7
+ 80169de:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 80169e2:	4770      	bx	lr
+
+080169e4 <memp_init>:
+ *
+ * Carves out memp_memory into linked lists for each pool-type.
+ */
+void
+memp_init(void)
+{
+ 80169e4:	b580      	push	{r7, lr}
+ 80169e6:	b082      	sub	sp, #8
+ 80169e8:	af00      	add	r7, sp, #0
+  u16_t i;
+
+  /* for every pool: */
+  for (i = 0; i < LWIP_ARRAYSIZE(memp_pools); i++) {
+ 80169ea:	2300      	movs	r3, #0
+ 80169ec:	80fb      	strh	r3, [r7, #6]
+ 80169ee:	e009      	b.n	8016a04 <memp_init+0x20>
+    memp_init_pool(memp_pools[i]);
+ 80169f0:	88fb      	ldrh	r3, [r7, #6]
+ 80169f2:	4a08      	ldr	r2, [pc, #32]	; (8016a14 <memp_init+0x30>)
+ 80169f4:	f852 3023 	ldr.w	r3, [r2, r3, lsl #2]
+ 80169f8:	4618      	mov	r0, r3
+ 80169fa:	f7ff ffc3 	bl	8016984 <memp_init_pool>
+  for (i = 0; i < LWIP_ARRAYSIZE(memp_pools); i++) {
+ 80169fe:	88fb      	ldrh	r3, [r7, #6]
+ 8016a00:	3301      	adds	r3, #1
+ 8016a02:	80fb      	strh	r3, [r7, #6]
+ 8016a04:	88fb      	ldrh	r3, [r7, #6]
+ 8016a06:	2b0c      	cmp	r3, #12
+ 8016a08:	d9f2      	bls.n	80169f0 <memp_init+0xc>
+
+#if MEMP_OVERFLOW_CHECK >= 2
+  /* check everything a first time to see if it worked */
+  memp_overflow_check_all();
+#endif /* MEMP_OVERFLOW_CHECK >= 2 */
+}
+ 8016a0a:	bf00      	nop
+ 8016a0c:	bf00      	nop
+ 8016a0e:	3708      	adds	r7, #8
+ 8016a10:	46bd      	mov	sp, r7
+ 8016a12:	bd80      	pop	{r7, pc}
+ 8016a14:	08026c78 	.word	0x08026c78
+
+08016a18 <do_memp_malloc_pool>:
+#if !MEMP_OVERFLOW_CHECK
+do_memp_malloc_pool(const struct memp_desc *desc)
+#else
+do_memp_malloc_pool_fn(const struct memp_desc *desc, const char *file, const int line)
+#endif
+{
+ 8016a18:	b580      	push	{r7, lr}
+ 8016a1a:	b084      	sub	sp, #16
+ 8016a1c:	af00      	add	r7, sp, #0
+ 8016a1e:	6078      	str	r0, [r7, #4]
+
+#if MEMP_MEM_MALLOC
+  memp = (struct memp *)mem_malloc(MEMP_SIZE + MEMP_ALIGN_SIZE(desc->size));
+  SYS_ARCH_PROTECT(old_level);
+#else /* MEMP_MEM_MALLOC */
+  SYS_ARCH_PROTECT(old_level);
+ 8016a20:	f00a fe18 	bl	8021654 <sys_arch_protect>
+ 8016a24:	60f8      	str	r0, [r7, #12]
+
+  memp = *desc->tab;
+ 8016a26:	687b      	ldr	r3, [r7, #4]
+ 8016a28:	68db      	ldr	r3, [r3, #12]
+ 8016a2a:	681b      	ldr	r3, [r3, #0]
+ 8016a2c:	60bb      	str	r3, [r7, #8]
+#endif /* MEMP_MEM_MALLOC */
+
+  if (memp != NULL) {
+ 8016a2e:	68bb      	ldr	r3, [r7, #8]
+ 8016a30:	2b00      	cmp	r3, #0
+ 8016a32:	d015      	beq.n	8016a60 <do_memp_malloc_pool+0x48>
+#if !MEMP_MEM_MALLOC
+#if MEMP_OVERFLOW_CHECK == 1
+    memp_overflow_check_element(memp, desc);
+#endif /* MEMP_OVERFLOW_CHECK */
+
+    *desc->tab = memp->next;
+ 8016a34:	687b      	ldr	r3, [r7, #4]
+ 8016a36:	68db      	ldr	r3, [r3, #12]
+ 8016a38:	68ba      	ldr	r2, [r7, #8]
+ 8016a3a:	6812      	ldr	r2, [r2, #0]
+ 8016a3c:	601a      	str	r2, [r3, #0]
+    memp->line = line;
+#if MEMP_MEM_MALLOC
+    memp_overflow_init_element(memp, desc);
+#endif /* MEMP_MEM_MALLOC */
+#endif /* MEMP_OVERFLOW_CHECK */
+    LWIP_ASSERT("memp_malloc: memp properly aligned",
+ 8016a3e:	68bb      	ldr	r3, [r7, #8]
+ 8016a40:	f003 0303 	and.w	r3, r3, #3
+ 8016a44:	2b00      	cmp	r3, #0
+ 8016a46:	d006      	beq.n	8016a56 <do_memp_malloc_pool+0x3e>
+ 8016a48:	4b0c      	ldr	r3, [pc, #48]	; (8016a7c <do_memp_malloc_pool+0x64>)
+ 8016a4a:	f44f 728c 	mov.w	r2, #280	; 0x118
+ 8016a4e:	490c      	ldr	r1, [pc, #48]	; (8016a80 <do_memp_malloc_pool+0x68>)
+ 8016a50:	480c      	ldr	r0, [pc, #48]	; (8016a84 <do_memp_malloc_pool+0x6c>)
+ 8016a52:	f00a ff99 	bl	8021988 <iprintf>
+    desc->stats->used++;
+    if (desc->stats->used > desc->stats->max) {
+      desc->stats->max = desc->stats->used;
+    }
+#endif
+    SYS_ARCH_UNPROTECT(old_level);
+ 8016a56:	68f8      	ldr	r0, [r7, #12]
+ 8016a58:	f00a fe0a 	bl	8021670 <sys_arch_unprotect>
+    /* cast through u8_t* to get rid of alignment warnings */
+    return ((u8_t *)memp + MEMP_SIZE);
+ 8016a5c:	68bb      	ldr	r3, [r7, #8]
+ 8016a5e:	e009      	b.n	8016a74 <do_memp_malloc_pool+0x5c>
+  } else {
+#if MEMP_STATS
+    desc->stats->err++;
+#endif
+    SYS_ARCH_UNPROTECT(old_level);
+ 8016a60:	68f8      	ldr	r0, [r7, #12]
+ 8016a62:	f00a fe05 	bl	8021670 <sys_arch_unprotect>
+    LWIP_DEBUGF(MEMP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("memp_malloc: out of memory in pool %s\n", desc->desc));
+ 8016a66:	687b      	ldr	r3, [r7, #4]
+ 8016a68:	681b      	ldr	r3, [r3, #0]
+ 8016a6a:	4619      	mov	r1, r3
+ 8016a6c:	4806      	ldr	r0, [pc, #24]	; (8016a88 <do_memp_malloc_pool+0x70>)
+ 8016a6e:	f00a ff8b 	bl	8021988 <iprintf>
+  }
+
+  return NULL;
+ 8016a72:	2300      	movs	r3, #0
+}
+ 8016a74:	4618      	mov	r0, r3
+ 8016a76:	3710      	adds	r7, #16
+ 8016a78:	46bd      	mov	sp, r7
+ 8016a7a:	bd80      	pop	{r7, pc}
+ 8016a7c:	080241f4 	.word	0x080241f4
+ 8016a80:	08024224 	.word	0x08024224
+ 8016a84:	08024248 	.word	0x08024248
+ 8016a88:	08024270 	.word	0x08024270
+
+08016a8c <memp_malloc_pool>:
+#if !MEMP_OVERFLOW_CHECK
+memp_malloc_pool(const struct memp_desc *desc)
+#else
+memp_malloc_pool_fn(const struct memp_desc *desc, const char *file, const int line)
+#endif
+{
+ 8016a8c:	b580      	push	{r7, lr}
+ 8016a8e:	b082      	sub	sp, #8
+ 8016a90:	af00      	add	r7, sp, #0
+ 8016a92:	6078      	str	r0, [r7, #4]
+  LWIP_ASSERT("invalid pool desc", desc != NULL);
+ 8016a94:	687b      	ldr	r3, [r7, #4]
+ 8016a96:	2b00      	cmp	r3, #0
+ 8016a98:	d106      	bne.n	8016aa8 <memp_malloc_pool+0x1c>
+ 8016a9a:	4b0a      	ldr	r3, [pc, #40]	; (8016ac4 <memp_malloc_pool+0x38>)
+ 8016a9c:	f44f 729e 	mov.w	r2, #316	; 0x13c
+ 8016aa0:	4909      	ldr	r1, [pc, #36]	; (8016ac8 <memp_malloc_pool+0x3c>)
+ 8016aa2:	480a      	ldr	r0, [pc, #40]	; (8016acc <memp_malloc_pool+0x40>)
+ 8016aa4:	f00a ff70 	bl	8021988 <iprintf>
+  if (desc == NULL) {
+ 8016aa8:	687b      	ldr	r3, [r7, #4]
+ 8016aaa:	2b00      	cmp	r3, #0
+ 8016aac:	d101      	bne.n	8016ab2 <memp_malloc_pool+0x26>
+    return NULL;
+ 8016aae:	2300      	movs	r3, #0
+ 8016ab0:	e003      	b.n	8016aba <memp_malloc_pool+0x2e>
+  }
+
+#if !MEMP_OVERFLOW_CHECK
+  return do_memp_malloc_pool(desc);
+ 8016ab2:	6878      	ldr	r0, [r7, #4]
+ 8016ab4:	f7ff ffb0 	bl	8016a18 <do_memp_malloc_pool>
+ 8016ab8:	4603      	mov	r3, r0
+#else
+  return do_memp_malloc_pool_fn(desc, file, line);
+#endif
+}
+ 8016aba:	4618      	mov	r0, r3
+ 8016abc:	3708      	adds	r7, #8
+ 8016abe:	46bd      	mov	sp, r7
+ 8016ac0:	bd80      	pop	{r7, pc}
+ 8016ac2:	bf00      	nop
+ 8016ac4:	080241f4 	.word	0x080241f4
+ 8016ac8:	08024298 	.word	0x08024298
+ 8016acc:	08024248 	.word	0x08024248
+
+08016ad0 <memp_malloc>:
+#if !MEMP_OVERFLOW_CHECK
+memp_malloc(memp_t type)
+#else
+memp_malloc_fn(memp_t type, const char *file, const int line)
+#endif
+{
+ 8016ad0:	b580      	push	{r7, lr}
+ 8016ad2:	b084      	sub	sp, #16
+ 8016ad4:	af00      	add	r7, sp, #0
+ 8016ad6:	4603      	mov	r3, r0
+ 8016ad8:	71fb      	strb	r3, [r7, #7]
+  void *memp;
+  LWIP_ERROR("memp_malloc: type < MEMP_MAX", (type < MEMP_MAX), return NULL;);
+ 8016ada:	79fb      	ldrb	r3, [r7, #7]
+ 8016adc:	2b0c      	cmp	r3, #12
+ 8016ade:	d908      	bls.n	8016af2 <memp_malloc+0x22>
+ 8016ae0:	4b0a      	ldr	r3, [pc, #40]	; (8016b0c <memp_malloc+0x3c>)
+ 8016ae2:	f240 1257 	movw	r2, #343	; 0x157
+ 8016ae6:	490a      	ldr	r1, [pc, #40]	; (8016b10 <memp_malloc+0x40>)
+ 8016ae8:	480a      	ldr	r0, [pc, #40]	; (8016b14 <memp_malloc+0x44>)
+ 8016aea:	f00a ff4d 	bl	8021988 <iprintf>
+ 8016aee:	2300      	movs	r3, #0
+ 8016af0:	e008      	b.n	8016b04 <memp_malloc+0x34>
+#if MEMP_OVERFLOW_CHECK >= 2
+  memp_overflow_check_all();
+#endif /* MEMP_OVERFLOW_CHECK >= 2 */
+
+#if !MEMP_OVERFLOW_CHECK
+  memp = do_memp_malloc_pool(memp_pools[type]);
+ 8016af2:	79fb      	ldrb	r3, [r7, #7]
+ 8016af4:	4a08      	ldr	r2, [pc, #32]	; (8016b18 <memp_malloc+0x48>)
+ 8016af6:	f852 3023 	ldr.w	r3, [r2, r3, lsl #2]
+ 8016afa:	4618      	mov	r0, r3
+ 8016afc:	f7ff ff8c 	bl	8016a18 <do_memp_malloc_pool>
+ 8016b00:	60f8      	str	r0, [r7, #12]
+#else
+  memp = do_memp_malloc_pool_fn(memp_pools[type], file, line);
+#endif
+
+  return memp;
+ 8016b02:	68fb      	ldr	r3, [r7, #12]
+}
+ 8016b04:	4618      	mov	r0, r3
+ 8016b06:	3710      	adds	r7, #16
+ 8016b08:	46bd      	mov	sp, r7
+ 8016b0a:	bd80      	pop	{r7, pc}
+ 8016b0c:	080241f4 	.word	0x080241f4
+ 8016b10:	080242ac 	.word	0x080242ac
+ 8016b14:	08024248 	.word	0x08024248
+ 8016b18:	08026c78 	.word	0x08026c78
+
+08016b1c <do_memp_free_pool>:
+
+static void
+do_memp_free_pool(const struct memp_desc *desc, void *mem)
+{
+ 8016b1c:	b580      	push	{r7, lr}
+ 8016b1e:	b084      	sub	sp, #16
+ 8016b20:	af00      	add	r7, sp, #0
+ 8016b22:	6078      	str	r0, [r7, #4]
+ 8016b24:	6039      	str	r1, [r7, #0]
+  struct memp *memp;
+  SYS_ARCH_DECL_PROTECT(old_level);
+
+  LWIP_ASSERT("memp_free: mem properly aligned",
+ 8016b26:	683b      	ldr	r3, [r7, #0]
+ 8016b28:	f003 0303 	and.w	r3, r3, #3
+ 8016b2c:	2b00      	cmp	r3, #0
+ 8016b2e:	d006      	beq.n	8016b3e <do_memp_free_pool+0x22>
+ 8016b30:	4b0d      	ldr	r3, [pc, #52]	; (8016b68 <do_memp_free_pool+0x4c>)
+ 8016b32:	f44f 72b6 	mov.w	r2, #364	; 0x16c
+ 8016b36:	490d      	ldr	r1, [pc, #52]	; (8016b6c <do_memp_free_pool+0x50>)
+ 8016b38:	480d      	ldr	r0, [pc, #52]	; (8016b70 <do_memp_free_pool+0x54>)
+ 8016b3a:	f00a ff25 	bl	8021988 <iprintf>
+              ((mem_ptr_t)mem % MEM_ALIGNMENT) == 0);
+
+  /* cast through void* to get rid of alignment warnings */
+  memp = (struct memp *)(void *)((u8_t *)mem - MEMP_SIZE);
+ 8016b3e:	683b      	ldr	r3, [r7, #0]
+ 8016b40:	60fb      	str	r3, [r7, #12]
+
+  SYS_ARCH_PROTECT(old_level);
+ 8016b42:	f00a fd87 	bl	8021654 <sys_arch_protect>
+ 8016b46:	60b8      	str	r0, [r7, #8]
+#if MEMP_MEM_MALLOC
+  LWIP_UNUSED_ARG(desc);
+  SYS_ARCH_UNPROTECT(old_level);
+  mem_free(memp);
+#else /* MEMP_MEM_MALLOC */
+  memp->next = *desc->tab;
+ 8016b48:	687b      	ldr	r3, [r7, #4]
+ 8016b4a:	68db      	ldr	r3, [r3, #12]
+ 8016b4c:	681a      	ldr	r2, [r3, #0]
+ 8016b4e:	68fb      	ldr	r3, [r7, #12]
+ 8016b50:	601a      	str	r2, [r3, #0]
+  *desc->tab = memp;
+ 8016b52:	687b      	ldr	r3, [r7, #4]
+ 8016b54:	68db      	ldr	r3, [r3, #12]
+ 8016b56:	68fa      	ldr	r2, [r7, #12]
+ 8016b58:	601a      	str	r2, [r3, #0]
+
+#if MEMP_SANITY_CHECK
+  LWIP_ASSERT("memp sanity", memp_sanity(desc));
+#endif /* MEMP_SANITY_CHECK */
+
+  SYS_ARCH_UNPROTECT(old_level);
+ 8016b5a:	68b8      	ldr	r0, [r7, #8]
+ 8016b5c:	f00a fd88 	bl	8021670 <sys_arch_unprotect>
+#endif /* !MEMP_MEM_MALLOC */
+}
+ 8016b60:	bf00      	nop
+ 8016b62:	3710      	adds	r7, #16
+ 8016b64:	46bd      	mov	sp, r7
+ 8016b66:	bd80      	pop	{r7, pc}
+ 8016b68:	080241f4 	.word	0x080241f4
+ 8016b6c:	080242cc 	.word	0x080242cc
+ 8016b70:	08024248 	.word	0x08024248
+
+08016b74 <memp_free_pool>:
+ * @param desc the pool where to put mem
+ * @param mem the memp element to free
+ */
+void
+memp_free_pool(const struct memp_desc *desc, void *mem)
+{
+ 8016b74:	b580      	push	{r7, lr}
+ 8016b76:	b082      	sub	sp, #8
+ 8016b78:	af00      	add	r7, sp, #0
+ 8016b7a:	6078      	str	r0, [r7, #4]
+ 8016b7c:	6039      	str	r1, [r7, #0]
+  LWIP_ASSERT("invalid pool desc", desc != NULL);
+ 8016b7e:	687b      	ldr	r3, [r7, #4]
+ 8016b80:	2b00      	cmp	r3, #0
+ 8016b82:	d106      	bne.n	8016b92 <memp_free_pool+0x1e>
+ 8016b84:	4b0a      	ldr	r3, [pc, #40]	; (8016bb0 <memp_free_pool+0x3c>)
+ 8016b86:	f240 1295 	movw	r2, #405	; 0x195
+ 8016b8a:	490a      	ldr	r1, [pc, #40]	; (8016bb4 <memp_free_pool+0x40>)
+ 8016b8c:	480a      	ldr	r0, [pc, #40]	; (8016bb8 <memp_free_pool+0x44>)
+ 8016b8e:	f00a fefb 	bl	8021988 <iprintf>
+  if ((desc == NULL) || (mem == NULL)) {
+ 8016b92:	687b      	ldr	r3, [r7, #4]
+ 8016b94:	2b00      	cmp	r3, #0
+ 8016b96:	d007      	beq.n	8016ba8 <memp_free_pool+0x34>
+ 8016b98:	683b      	ldr	r3, [r7, #0]
+ 8016b9a:	2b00      	cmp	r3, #0
+ 8016b9c:	d004      	beq.n	8016ba8 <memp_free_pool+0x34>
+    return;
+  }
+
+  do_memp_free_pool(desc, mem);
+ 8016b9e:	6839      	ldr	r1, [r7, #0]
+ 8016ba0:	6878      	ldr	r0, [r7, #4]
+ 8016ba2:	f7ff ffbb 	bl	8016b1c <do_memp_free_pool>
+ 8016ba6:	e000      	b.n	8016baa <memp_free_pool+0x36>
+    return;
+ 8016ba8:	bf00      	nop
+}
+ 8016baa:	3708      	adds	r7, #8
+ 8016bac:	46bd      	mov	sp, r7
+ 8016bae:	bd80      	pop	{r7, pc}
+ 8016bb0:	080241f4 	.word	0x080241f4
+ 8016bb4:	08024298 	.word	0x08024298
+ 8016bb8:	08024248 	.word	0x08024248
+
+08016bbc <memp_free>:
+ * @param type the pool where to put mem
+ * @param mem the memp element to free
+ */
+void
+memp_free(memp_t type, void *mem)
+{
+ 8016bbc:	b580      	push	{r7, lr}
+ 8016bbe:	b082      	sub	sp, #8
+ 8016bc0:	af00      	add	r7, sp, #0
+ 8016bc2:	4603      	mov	r3, r0
+ 8016bc4:	6039      	str	r1, [r7, #0]
+ 8016bc6:	71fb      	strb	r3, [r7, #7]
+#ifdef LWIP_HOOK_MEMP_AVAILABLE
+  struct memp *old_first;
+#endif
+
+  LWIP_ERROR("memp_free: type < MEMP_MAX", (type < MEMP_MAX), return;);
+ 8016bc8:	79fb      	ldrb	r3, [r7, #7]
+ 8016bca:	2b0c      	cmp	r3, #12
+ 8016bcc:	d907      	bls.n	8016bde <memp_free+0x22>
+ 8016bce:	4b0c      	ldr	r3, [pc, #48]	; (8016c00 <memp_free+0x44>)
+ 8016bd0:	f44f 72d5 	mov.w	r2, #426	; 0x1aa
+ 8016bd4:	490b      	ldr	r1, [pc, #44]	; (8016c04 <memp_free+0x48>)
+ 8016bd6:	480c      	ldr	r0, [pc, #48]	; (8016c08 <memp_free+0x4c>)
+ 8016bd8:	f00a fed6 	bl	8021988 <iprintf>
+ 8016bdc:	e00c      	b.n	8016bf8 <memp_free+0x3c>
+
+  if (mem == NULL) {
+ 8016bde:	683b      	ldr	r3, [r7, #0]
+ 8016be0:	2b00      	cmp	r3, #0
+ 8016be2:	d008      	beq.n	8016bf6 <memp_free+0x3a>
+
+#ifdef LWIP_HOOK_MEMP_AVAILABLE
+  old_first = *memp_pools[type]->tab;
+#endif
+
+  do_memp_free_pool(memp_pools[type], mem);
+ 8016be4:	79fb      	ldrb	r3, [r7, #7]
+ 8016be6:	4a09      	ldr	r2, [pc, #36]	; (8016c0c <memp_free+0x50>)
+ 8016be8:	f852 3023 	ldr.w	r3, [r2, r3, lsl #2]
+ 8016bec:	6839      	ldr	r1, [r7, #0]
+ 8016bee:	4618      	mov	r0, r3
+ 8016bf0:	f7ff ff94 	bl	8016b1c <do_memp_free_pool>
+ 8016bf4:	e000      	b.n	8016bf8 <memp_free+0x3c>
+    return;
+ 8016bf6:	bf00      	nop
+#ifdef LWIP_HOOK_MEMP_AVAILABLE
+  if (old_first == NULL) {
+    LWIP_HOOK_MEMP_AVAILABLE(type);
+  }
+#endif
+}
+ 8016bf8:	3708      	adds	r7, #8
+ 8016bfa:	46bd      	mov	sp, r7
+ 8016bfc:	bd80      	pop	{r7, pc}
+ 8016bfe:	bf00      	nop
+ 8016c00:	080241f4 	.word	0x080241f4
+ 8016c04:	080242ec 	.word	0x080242ec
+ 8016c08:	08024248 	.word	0x08024248
+ 8016c0c:	08026c78 	.word	0x08026c78
+
+08016c10 <netif_init>:
+}
+#endif /* LWIP_HAVE_LOOPIF */
+
+void
+netif_init(void)
+{
+ 8016c10:	b480      	push	{r7}
+ 8016c12:	af00      	add	r7, sp, #0
+
+  netif_set_link_up(&loop_netif);
+  netif_set_up(&loop_netif);
+
+#endif /* LWIP_HAVE_LOOPIF */
+}
+ 8016c14:	bf00      	nop
+ 8016c16:	46bd      	mov	sp, r7
+ 8016c18:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8016c1c:	4770      	bx	lr
+	...
+
+08016c20 <netif_add>:
+netif_add(struct netif *netif,
+#if LWIP_IPV4
+          const ip4_addr_t *ipaddr, const ip4_addr_t *netmask, const ip4_addr_t *gw,
+#endif /* LWIP_IPV4 */
+          void *state, netif_init_fn init, netif_input_fn input)
+{
+ 8016c20:	b580      	push	{r7, lr}
+ 8016c22:	b088      	sub	sp, #32
+ 8016c24:	af02      	add	r7, sp, #8
+ 8016c26:	60f8      	str	r0, [r7, #12]
+ 8016c28:	60b9      	str	r1, [r7, #8]
+ 8016c2a:	607a      	str	r2, [r7, #4]
+ 8016c2c:	603b      	str	r3, [r7, #0]
+    LWIP_ASSERT("single netif already set", 0);
+    return NULL;
+  }
+#endif
+
+  LWIP_ERROR("netif_add: invalid netif", netif != NULL, return NULL);
+ 8016c2e:	68fb      	ldr	r3, [r7, #12]
+ 8016c30:	2b00      	cmp	r3, #0
+ 8016c32:	d108      	bne.n	8016c46 <netif_add+0x26>
+ 8016c34:	4b96      	ldr	r3, [pc, #600]	; (8016e90 <netif_add+0x270>)
+ 8016c36:	f240 1227 	movw	r2, #295	; 0x127
+ 8016c3a:	4996      	ldr	r1, [pc, #600]	; (8016e94 <netif_add+0x274>)
+ 8016c3c:	4896      	ldr	r0, [pc, #600]	; (8016e98 <netif_add+0x278>)
+ 8016c3e:	f00a fea3 	bl	8021988 <iprintf>
+ 8016c42:	2300      	movs	r3, #0
+ 8016c44:	e14c      	b.n	8016ee0 <netif_add+0x2c0>
+  LWIP_ERROR("netif_add: No init function given", init != NULL, return NULL);
+ 8016c46:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 8016c48:	2b00      	cmp	r3, #0
+ 8016c4a:	d108      	bne.n	8016c5e <netif_add+0x3e>
+ 8016c4c:	4b90      	ldr	r3, [pc, #576]	; (8016e90 <netif_add+0x270>)
+ 8016c4e:	f44f 7294 	mov.w	r2, #296	; 0x128
+ 8016c52:	4992      	ldr	r1, [pc, #584]	; (8016e9c <netif_add+0x27c>)
+ 8016c54:	4890      	ldr	r0, [pc, #576]	; (8016e98 <netif_add+0x278>)
+ 8016c56:	f00a fe97 	bl	8021988 <iprintf>
+ 8016c5a:	2300      	movs	r3, #0
+ 8016c5c:	e140      	b.n	8016ee0 <netif_add+0x2c0>
+
+#if LWIP_IPV4
+  if (ipaddr == NULL) {
+ 8016c5e:	68bb      	ldr	r3, [r7, #8]
+ 8016c60:	2b00      	cmp	r3, #0
+ 8016c62:	d101      	bne.n	8016c68 <netif_add+0x48>
+    ipaddr = ip_2_ip4(IP4_ADDR_ANY);
+ 8016c64:	4b8e      	ldr	r3, [pc, #568]	; (8016ea0 <netif_add+0x280>)
+ 8016c66:	60bb      	str	r3, [r7, #8]
+  }
+  if (netmask == NULL) {
+ 8016c68:	687b      	ldr	r3, [r7, #4]
+ 8016c6a:	2b00      	cmp	r3, #0
+ 8016c6c:	d101      	bne.n	8016c72 <netif_add+0x52>
+    netmask = ip_2_ip4(IP4_ADDR_ANY);
+ 8016c6e:	4b8c      	ldr	r3, [pc, #560]	; (8016ea0 <netif_add+0x280>)
+ 8016c70:	607b      	str	r3, [r7, #4]
+  }
+  if (gw == NULL) {
+ 8016c72:	683b      	ldr	r3, [r7, #0]
+ 8016c74:	2b00      	cmp	r3, #0
+ 8016c76:	d101      	bne.n	8016c7c <netif_add+0x5c>
+    gw = ip_2_ip4(IP4_ADDR_ANY);
+ 8016c78:	4b89      	ldr	r3, [pc, #548]	; (8016ea0 <netif_add+0x280>)
+ 8016c7a:	603b      	str	r3, [r7, #0]
+  }
+
+  /* reset new interface configuration state */
+  ip_addr_set_zero_ip4(&netif->ip_addr);
+ 8016c7c:	68fb      	ldr	r3, [r7, #12]
+ 8016c7e:	2200      	movs	r2, #0
+ 8016c80:	605a      	str	r2, [r3, #4]
+  ip_addr_set_zero_ip4(&netif->netmask);
+ 8016c82:	68fb      	ldr	r3, [r7, #12]
+ 8016c84:	2200      	movs	r2, #0
+ 8016c86:	609a      	str	r2, [r3, #8]
+  ip_addr_set_zero_ip4(&netif->gw);
+ 8016c88:	68fb      	ldr	r3, [r7, #12]
+ 8016c8a:	2200      	movs	r2, #0
+ 8016c8c:	60da      	str	r2, [r3, #12]
+  netif->output = netif_null_output_ip4;
+ 8016c8e:	68fb      	ldr	r3, [r7, #12]
+ 8016c90:	4a84      	ldr	r2, [pc, #528]	; (8016ea4 <netif_add+0x284>)
+ 8016c92:	615a      	str	r2, [r3, #20]
+#endif /* LWIP_IPV6_ADDRESS_LIFETIMES */
+  }
+  netif->output_ip6 = netif_null_output_ip6;
+#endif /* LWIP_IPV6 */
+  NETIF_SET_CHECKSUM_CTRL(netif, NETIF_CHECKSUM_ENABLE_ALL);
+  netif->mtu = 0;
+ 8016c94:	68fb      	ldr	r3, [r7, #12]
+ 8016c96:	2200      	movs	r2, #0
+ 8016c98:	849a      	strh	r2, [r3, #36]	; 0x24
+  netif->flags = 0;
+ 8016c9a:	68fb      	ldr	r3, [r7, #12]
+ 8016c9c:	2200      	movs	r2, #0
+ 8016c9e:	f883 202d 	strb.w	r2, [r3, #45]	; 0x2d
+#endif /* LWIP_IPV6 */
+#if LWIP_NETIF_STATUS_CALLBACK
+  netif->status_callback = NULL;
+#endif /* LWIP_NETIF_STATUS_CALLBACK */
+#if LWIP_NETIF_LINK_CALLBACK
+  netif->link_callback = NULL;
+ 8016ca2:	68fb      	ldr	r3, [r7, #12]
+ 8016ca4:	2200      	movs	r2, #0
+ 8016ca6:	61da      	str	r2, [r3, #28]
+  netif->loop_first = NULL;
+  netif->loop_last = NULL;
+#endif /* ENABLE_LOOPBACK */
+
+  /* remember netif specific state information data */
+  netif->state = state;
+ 8016ca8:	68fb      	ldr	r3, [r7, #12]
+ 8016caa:	6a3a      	ldr	r2, [r7, #32]
+ 8016cac:	621a      	str	r2, [r3, #32]
+  netif->num = netif_num;
+ 8016cae:	4b7e      	ldr	r3, [pc, #504]	; (8016ea8 <netif_add+0x288>)
+ 8016cb0:	781a      	ldrb	r2, [r3, #0]
+ 8016cb2:	68fb      	ldr	r3, [r7, #12]
+ 8016cb4:	f883 2030 	strb.w	r2, [r3, #48]	; 0x30
+  netif->input = input;
+ 8016cb8:	68fb      	ldr	r3, [r7, #12]
+ 8016cba:	6aba      	ldr	r2, [r7, #40]	; 0x28
+ 8016cbc:	611a      	str	r2, [r3, #16]
+#if ENABLE_LOOPBACK && LWIP_LOOPBACK_MAX_PBUFS
+  netif->loop_cnt_current = 0;
+#endif /* ENABLE_LOOPBACK && LWIP_LOOPBACK_MAX_PBUFS */
+
+#if LWIP_IPV4
+  netif_set_addr(netif, ipaddr, netmask, gw);
+ 8016cbe:	683b      	ldr	r3, [r7, #0]
+ 8016cc0:	687a      	ldr	r2, [r7, #4]
+ 8016cc2:	68b9      	ldr	r1, [r7, #8]
+ 8016cc4:	68f8      	ldr	r0, [r7, #12]
+ 8016cc6:	f000 f9f5 	bl	80170b4 <netif_set_addr>
+#endif /* LWIP_IPV4 */
+
+  /* call user specified initialization function for netif */
+  if (init(netif) != ERR_OK) {
+ 8016cca:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 8016ccc:	68f8      	ldr	r0, [r7, #12]
+ 8016cce:	4798      	blx	r3
+ 8016cd0:	4603      	mov	r3, r0
+ 8016cd2:	2b00      	cmp	r3, #0
+ 8016cd4:	d001      	beq.n	8016cda <netif_add+0xba>
+    return NULL;
+ 8016cd6:	2300      	movs	r3, #0
+ 8016cd8:	e102      	b.n	8016ee0 <netif_add+0x2c0>
+     */
+  {
+    struct netif *netif2;
+    int num_netifs;
+    do {
+      if (netif->num == 255) {
+ 8016cda:	68fb      	ldr	r3, [r7, #12]
+ 8016cdc:	f893 3030 	ldrb.w	r3, [r3, #48]	; 0x30
+ 8016ce0:	2bff      	cmp	r3, #255	; 0xff
+ 8016ce2:	d103      	bne.n	8016cec <netif_add+0xcc>
+        netif->num = 0;
+ 8016ce4:	68fb      	ldr	r3, [r7, #12]
+ 8016ce6:	2200      	movs	r2, #0
+ 8016ce8:	f883 2030 	strb.w	r2, [r3, #48]	; 0x30
+      }
+      num_netifs = 0;
+ 8016cec:	2300      	movs	r3, #0
+ 8016cee:	613b      	str	r3, [r7, #16]
+      for (netif2 = netif_list; netif2 != NULL; netif2 = netif2->next) {
+ 8016cf0:	4b6e      	ldr	r3, [pc, #440]	; (8016eac <netif_add+0x28c>)
+ 8016cf2:	681b      	ldr	r3, [r3, #0]
+ 8016cf4:	617b      	str	r3, [r7, #20]
+ 8016cf6:	e02b      	b.n	8016d50 <netif_add+0x130>
+        LWIP_ASSERT("netif already added", netif2 != netif);
+ 8016cf8:	697a      	ldr	r2, [r7, #20]
+ 8016cfa:	68fb      	ldr	r3, [r7, #12]
+ 8016cfc:	429a      	cmp	r2, r3
+ 8016cfe:	d106      	bne.n	8016d0e <netif_add+0xee>
+ 8016d00:	4b63      	ldr	r3, [pc, #396]	; (8016e90 <netif_add+0x270>)
+ 8016d02:	f240 128b 	movw	r2, #395	; 0x18b
+ 8016d06:	496a      	ldr	r1, [pc, #424]	; (8016eb0 <netif_add+0x290>)
+ 8016d08:	4863      	ldr	r0, [pc, #396]	; (8016e98 <netif_add+0x278>)
+ 8016d0a:	f00a fe3d 	bl	8021988 <iprintf>
+        num_netifs++;
+ 8016d0e:	693b      	ldr	r3, [r7, #16]
+ 8016d10:	3301      	adds	r3, #1
+ 8016d12:	613b      	str	r3, [r7, #16]
+        LWIP_ASSERT("too many netifs, max. supported number is 255", num_netifs <= 255);
+ 8016d14:	693b      	ldr	r3, [r7, #16]
+ 8016d16:	2bff      	cmp	r3, #255	; 0xff
+ 8016d18:	dd06      	ble.n	8016d28 <netif_add+0x108>
+ 8016d1a:	4b5d      	ldr	r3, [pc, #372]	; (8016e90 <netif_add+0x270>)
+ 8016d1c:	f240 128d 	movw	r2, #397	; 0x18d
+ 8016d20:	4964      	ldr	r1, [pc, #400]	; (8016eb4 <netif_add+0x294>)
+ 8016d22:	485d      	ldr	r0, [pc, #372]	; (8016e98 <netif_add+0x278>)
+ 8016d24:	f00a fe30 	bl	8021988 <iprintf>
+        if (netif2->num == netif->num) {
+ 8016d28:	697b      	ldr	r3, [r7, #20]
+ 8016d2a:	f893 2030 	ldrb.w	r2, [r3, #48]	; 0x30
+ 8016d2e:	68fb      	ldr	r3, [r7, #12]
+ 8016d30:	f893 3030 	ldrb.w	r3, [r3, #48]	; 0x30
+ 8016d34:	429a      	cmp	r2, r3
+ 8016d36:	d108      	bne.n	8016d4a <netif_add+0x12a>
+          netif->num++;
+ 8016d38:	68fb      	ldr	r3, [r7, #12]
+ 8016d3a:	f893 3030 	ldrb.w	r3, [r3, #48]	; 0x30
+ 8016d3e:	3301      	adds	r3, #1
+ 8016d40:	b2da      	uxtb	r2, r3
+ 8016d42:	68fb      	ldr	r3, [r7, #12]
+ 8016d44:	f883 2030 	strb.w	r2, [r3, #48]	; 0x30
+          break;
+ 8016d48:	e005      	b.n	8016d56 <netif_add+0x136>
+      for (netif2 = netif_list; netif2 != NULL; netif2 = netif2->next) {
+ 8016d4a:	697b      	ldr	r3, [r7, #20]
+ 8016d4c:	681b      	ldr	r3, [r3, #0]
+ 8016d4e:	617b      	str	r3, [r7, #20]
+ 8016d50:	697b      	ldr	r3, [r7, #20]
+ 8016d52:	2b00      	cmp	r3, #0
+ 8016d54:	d1d0      	bne.n	8016cf8 <netif_add+0xd8>
+        }
+      }
+    } while (netif2 != NULL);
+ 8016d56:	697b      	ldr	r3, [r7, #20]
+ 8016d58:	2b00      	cmp	r3, #0
+ 8016d5a:	d1be      	bne.n	8016cda <netif_add+0xba>
+  }
+  if (netif->num == 254) {
+ 8016d5c:	68fb      	ldr	r3, [r7, #12]
+ 8016d5e:	f893 3030 	ldrb.w	r3, [r3, #48]	; 0x30
+ 8016d62:	2bfe      	cmp	r3, #254	; 0xfe
+ 8016d64:	d103      	bne.n	8016d6e <netif_add+0x14e>
+    netif_num = 0;
+ 8016d66:	4b50      	ldr	r3, [pc, #320]	; (8016ea8 <netif_add+0x288>)
+ 8016d68:	2200      	movs	r2, #0
+ 8016d6a:	701a      	strb	r2, [r3, #0]
+ 8016d6c:	e006      	b.n	8016d7c <netif_add+0x15c>
+  } else {
+    netif_num = (u8_t)(netif->num + 1);
+ 8016d6e:	68fb      	ldr	r3, [r7, #12]
+ 8016d70:	f893 3030 	ldrb.w	r3, [r3, #48]	; 0x30
+ 8016d74:	3301      	adds	r3, #1
+ 8016d76:	b2da      	uxtb	r2, r3
+ 8016d78:	4b4b      	ldr	r3, [pc, #300]	; (8016ea8 <netif_add+0x288>)
+ 8016d7a:	701a      	strb	r2, [r3, #0]
+  }
+
+  /* add this netif to the list */
+  netif->next = netif_list;
+ 8016d7c:	4b4b      	ldr	r3, [pc, #300]	; (8016eac <netif_add+0x28c>)
+ 8016d7e:	681a      	ldr	r2, [r3, #0]
+ 8016d80:	68fb      	ldr	r3, [r7, #12]
+ 8016d82:	601a      	str	r2, [r3, #0]
+  netif_list = netif;
+ 8016d84:	4a49      	ldr	r2, [pc, #292]	; (8016eac <netif_add+0x28c>)
+ 8016d86:	68fb      	ldr	r3, [r7, #12]
+ 8016d88:	6013      	str	r3, [r2, #0]
+  if (netif->flags & NETIF_FLAG_IGMP) {
+    igmp_start(netif);
+  }
+#endif /* LWIP_IGMP */
+
+  LWIP_DEBUGF(NETIF_DEBUG, ("netif: added interface %c%c IP",
+ 8016d8a:	68fb      	ldr	r3, [r7, #12]
+ 8016d8c:	f893 302e 	ldrb.w	r3, [r3, #46]	; 0x2e
+ 8016d90:	4619      	mov	r1, r3
+ 8016d92:	68fb      	ldr	r3, [r7, #12]
+ 8016d94:	f893 302f 	ldrb.w	r3, [r3, #47]	; 0x2f
+ 8016d98:	461a      	mov	r2, r3
+ 8016d9a:	4847      	ldr	r0, [pc, #284]	; (8016eb8 <netif_add+0x298>)
+ 8016d9c:	f00a fdf4 	bl	8021988 <iprintf>
+                            netif->name[0], netif->name[1]));
+#if LWIP_IPV4
+  LWIP_DEBUGF(NETIF_DEBUG, (" addr "));
+ 8016da0:	4846      	ldr	r0, [pc, #280]	; (8016ebc <netif_add+0x29c>)
+ 8016da2:	f00a fdf1 	bl	8021988 <iprintf>
+  ip4_addr_debug_print(NETIF_DEBUG, ipaddr);
+ 8016da6:	68bb      	ldr	r3, [r7, #8]
+ 8016da8:	2b00      	cmp	r3, #0
+ 8016daa:	d003      	beq.n	8016db4 <netif_add+0x194>
+ 8016dac:	68bb      	ldr	r3, [r7, #8]
+ 8016dae:	781b      	ldrb	r3, [r3, #0]
+ 8016db0:	4619      	mov	r1, r3
+ 8016db2:	e000      	b.n	8016db6 <netif_add+0x196>
+ 8016db4:	2100      	movs	r1, #0
+ 8016db6:	68bb      	ldr	r3, [r7, #8]
+ 8016db8:	2b00      	cmp	r3, #0
+ 8016dba:	d004      	beq.n	8016dc6 <netif_add+0x1a6>
+ 8016dbc:	68bb      	ldr	r3, [r7, #8]
+ 8016dbe:	3301      	adds	r3, #1
+ 8016dc0:	781b      	ldrb	r3, [r3, #0]
+ 8016dc2:	461a      	mov	r2, r3
+ 8016dc4:	e000      	b.n	8016dc8 <netif_add+0x1a8>
+ 8016dc6:	2200      	movs	r2, #0
+ 8016dc8:	68bb      	ldr	r3, [r7, #8]
+ 8016dca:	2b00      	cmp	r3, #0
+ 8016dcc:	d004      	beq.n	8016dd8 <netif_add+0x1b8>
+ 8016dce:	68bb      	ldr	r3, [r7, #8]
+ 8016dd0:	3302      	adds	r3, #2
+ 8016dd2:	781b      	ldrb	r3, [r3, #0]
+ 8016dd4:	4618      	mov	r0, r3
+ 8016dd6:	e000      	b.n	8016dda <netif_add+0x1ba>
+ 8016dd8:	2000      	movs	r0, #0
+ 8016dda:	68bb      	ldr	r3, [r7, #8]
+ 8016ddc:	2b00      	cmp	r3, #0
+ 8016dde:	d003      	beq.n	8016de8 <netif_add+0x1c8>
+ 8016de0:	68bb      	ldr	r3, [r7, #8]
+ 8016de2:	3303      	adds	r3, #3
+ 8016de4:	781b      	ldrb	r3, [r3, #0]
+ 8016de6:	e000      	b.n	8016dea <netif_add+0x1ca>
+ 8016de8:	2300      	movs	r3, #0
+ 8016dea:	9300      	str	r3, [sp, #0]
+ 8016dec:	4603      	mov	r3, r0
+ 8016dee:	4834      	ldr	r0, [pc, #208]	; (8016ec0 <netif_add+0x2a0>)
+ 8016df0:	f00a fdca 	bl	8021988 <iprintf>
+  LWIP_DEBUGF(NETIF_DEBUG, (" netmask "));
+ 8016df4:	4833      	ldr	r0, [pc, #204]	; (8016ec4 <netif_add+0x2a4>)
+ 8016df6:	f00a fdc7 	bl	8021988 <iprintf>
+  ip4_addr_debug_print(NETIF_DEBUG, netmask);
+ 8016dfa:	687b      	ldr	r3, [r7, #4]
+ 8016dfc:	2b00      	cmp	r3, #0
+ 8016dfe:	d003      	beq.n	8016e08 <netif_add+0x1e8>
+ 8016e00:	687b      	ldr	r3, [r7, #4]
+ 8016e02:	781b      	ldrb	r3, [r3, #0]
+ 8016e04:	4619      	mov	r1, r3
+ 8016e06:	e000      	b.n	8016e0a <netif_add+0x1ea>
+ 8016e08:	2100      	movs	r1, #0
+ 8016e0a:	687b      	ldr	r3, [r7, #4]
+ 8016e0c:	2b00      	cmp	r3, #0
+ 8016e0e:	d004      	beq.n	8016e1a <netif_add+0x1fa>
+ 8016e10:	687b      	ldr	r3, [r7, #4]
+ 8016e12:	3301      	adds	r3, #1
+ 8016e14:	781b      	ldrb	r3, [r3, #0]
+ 8016e16:	461a      	mov	r2, r3
+ 8016e18:	e000      	b.n	8016e1c <netif_add+0x1fc>
+ 8016e1a:	2200      	movs	r2, #0
+ 8016e1c:	687b      	ldr	r3, [r7, #4]
+ 8016e1e:	2b00      	cmp	r3, #0
+ 8016e20:	d004      	beq.n	8016e2c <netif_add+0x20c>
+ 8016e22:	687b      	ldr	r3, [r7, #4]
+ 8016e24:	3302      	adds	r3, #2
+ 8016e26:	781b      	ldrb	r3, [r3, #0]
+ 8016e28:	4618      	mov	r0, r3
+ 8016e2a:	e000      	b.n	8016e2e <netif_add+0x20e>
+ 8016e2c:	2000      	movs	r0, #0
+ 8016e2e:	687b      	ldr	r3, [r7, #4]
+ 8016e30:	2b00      	cmp	r3, #0
+ 8016e32:	d003      	beq.n	8016e3c <netif_add+0x21c>
+ 8016e34:	687b      	ldr	r3, [r7, #4]
+ 8016e36:	3303      	adds	r3, #3
+ 8016e38:	781b      	ldrb	r3, [r3, #0]
+ 8016e3a:	e000      	b.n	8016e3e <netif_add+0x21e>
+ 8016e3c:	2300      	movs	r3, #0
+ 8016e3e:	9300      	str	r3, [sp, #0]
+ 8016e40:	4603      	mov	r3, r0
+ 8016e42:	481f      	ldr	r0, [pc, #124]	; (8016ec0 <netif_add+0x2a0>)
+ 8016e44:	f00a fda0 	bl	8021988 <iprintf>
+  LWIP_DEBUGF(NETIF_DEBUG, (" gw "));
+ 8016e48:	481f      	ldr	r0, [pc, #124]	; (8016ec8 <netif_add+0x2a8>)
+ 8016e4a:	f00a fd9d 	bl	8021988 <iprintf>
+  ip4_addr_debug_print(NETIF_DEBUG, gw);
+ 8016e4e:	683b      	ldr	r3, [r7, #0]
+ 8016e50:	2b00      	cmp	r3, #0
+ 8016e52:	d003      	beq.n	8016e5c <netif_add+0x23c>
+ 8016e54:	683b      	ldr	r3, [r7, #0]
+ 8016e56:	781b      	ldrb	r3, [r3, #0]
+ 8016e58:	4619      	mov	r1, r3
+ 8016e5a:	e000      	b.n	8016e5e <netif_add+0x23e>
+ 8016e5c:	2100      	movs	r1, #0
+ 8016e5e:	683b      	ldr	r3, [r7, #0]
+ 8016e60:	2b00      	cmp	r3, #0
+ 8016e62:	d004      	beq.n	8016e6e <netif_add+0x24e>
+ 8016e64:	683b      	ldr	r3, [r7, #0]
+ 8016e66:	3301      	adds	r3, #1
+ 8016e68:	781b      	ldrb	r3, [r3, #0]
+ 8016e6a:	461a      	mov	r2, r3
+ 8016e6c:	e000      	b.n	8016e70 <netif_add+0x250>
+ 8016e6e:	2200      	movs	r2, #0
+ 8016e70:	683b      	ldr	r3, [r7, #0]
+ 8016e72:	2b00      	cmp	r3, #0
+ 8016e74:	d004      	beq.n	8016e80 <netif_add+0x260>
+ 8016e76:	683b      	ldr	r3, [r7, #0]
+ 8016e78:	3302      	adds	r3, #2
+ 8016e7a:	781b      	ldrb	r3, [r3, #0]
+ 8016e7c:	4618      	mov	r0, r3
+ 8016e7e:	e000      	b.n	8016e82 <netif_add+0x262>
+ 8016e80:	2000      	movs	r0, #0
+ 8016e82:	683b      	ldr	r3, [r7, #0]
+ 8016e84:	2b00      	cmp	r3, #0
+ 8016e86:	d021      	beq.n	8016ecc <netif_add+0x2ac>
+ 8016e88:	683b      	ldr	r3, [r7, #0]
+ 8016e8a:	3303      	adds	r3, #3
+ 8016e8c:	781b      	ldrb	r3, [r3, #0]
+ 8016e8e:	e01e      	b.n	8016ece <netif_add+0x2ae>
+ 8016e90:	08024308 	.word	0x08024308
+ 8016e94:	0802439c 	.word	0x0802439c
+ 8016e98:	08024358 	.word	0x08024358
+ 8016e9c:	080243b8 	.word	0x080243b8
+ 8016ea0:	08026cec 	.word	0x08026cec
+ 8016ea4:	080173b7 	.word	0x080173b7
+ 8016ea8:	2401a47c 	.word	0x2401a47c
+ 8016eac:	2401a474 	.word	0x2401a474
+ 8016eb0:	080243dc 	.word	0x080243dc
+ 8016eb4:	080243f0 	.word	0x080243f0
+ 8016eb8:	08024420 	.word	0x08024420
+ 8016ebc:	08024440 	.word	0x08024440
+ 8016ec0:	08024448 	.word	0x08024448
+ 8016ec4:	08024458 	.word	0x08024458
+ 8016ec8:	08024464 	.word	0x08024464
+ 8016ecc:	2300      	movs	r3, #0
+ 8016ece:	9300      	str	r3, [sp, #0]
+ 8016ed0:	4603      	mov	r3, r0
+ 8016ed2:	4805      	ldr	r0, [pc, #20]	; (8016ee8 <netif_add+0x2c8>)
+ 8016ed4:	f00a fd58 	bl	8021988 <iprintf>
+#endif /* LWIP_IPV4 */
+  LWIP_DEBUGF(NETIF_DEBUG, ("\n"));
+ 8016ed8:	200a      	movs	r0, #10
+ 8016eda:	f00a fd67 	bl	80219ac <putchar>
+
+  netif_invoke_ext_callback(netif, LWIP_NSC_NETIF_ADDED, NULL);
+
+  return netif;
+ 8016ede:	68fb      	ldr	r3, [r7, #12]
+}
+ 8016ee0:	4618      	mov	r0, r3
+ 8016ee2:	3718      	adds	r7, #24
+ 8016ee4:	46bd      	mov	sp, r7
+ 8016ee6:	bd80      	pop	{r7, pc}
+ 8016ee8:	08024448 	.word	0x08024448
+
+08016eec <netif_do_ip_addr_changed>:
+
+static void
+netif_do_ip_addr_changed(const ip_addr_t *old_addr, const ip_addr_t *new_addr)
+{
+ 8016eec:	b580      	push	{r7, lr}
+ 8016eee:	b082      	sub	sp, #8
+ 8016ef0:	af00      	add	r7, sp, #0
+ 8016ef2:	6078      	str	r0, [r7, #4]
+ 8016ef4:	6039      	str	r1, [r7, #0]
+#if LWIP_TCP
+  tcp_netif_ip_addr_changed(old_addr, new_addr);
+ 8016ef6:	6839      	ldr	r1, [r7, #0]
+ 8016ef8:	6878      	ldr	r0, [r7, #4]
+ 8016efa:	f002 ff09 	bl	8019d10 <tcp_netif_ip_addr_changed>
+#endif /* LWIP_TCP */
+#if LWIP_UDP
+  udp_netif_ip_addr_changed(old_addr, new_addr);
+ 8016efe:	6839      	ldr	r1, [r7, #0]
+ 8016f00:	6878      	ldr	r0, [r7, #4]
+ 8016f02:	f007 fe95 	bl	801ec30 <udp_netif_ip_addr_changed>
+#endif /* LWIP_UDP */
+#if LWIP_RAW
+  raw_netif_ip_addr_changed(old_addr, new_addr);
+#endif /* LWIP_RAW */
+}
+ 8016f06:	bf00      	nop
+ 8016f08:	3708      	adds	r7, #8
+ 8016f0a:	46bd      	mov	sp, r7
+ 8016f0c:	bd80      	pop	{r7, pc}
+	...
+
+08016f10 <netif_do_set_ipaddr>:
+
+#if LWIP_IPV4
+static int
+netif_do_set_ipaddr(struct netif *netif, const ip4_addr_t *ipaddr, ip_addr_t *old_addr)
+{
+ 8016f10:	b580      	push	{r7, lr}
+ 8016f12:	b086      	sub	sp, #24
+ 8016f14:	af00      	add	r7, sp, #0
+ 8016f16:	60f8      	str	r0, [r7, #12]
+ 8016f18:	60b9      	str	r1, [r7, #8]
+ 8016f1a:	607a      	str	r2, [r7, #4]
+  LWIP_ASSERT("invalid pointer", ipaddr != NULL);
+ 8016f1c:	68bb      	ldr	r3, [r7, #8]
+ 8016f1e:	2b00      	cmp	r3, #0
+ 8016f20:	d106      	bne.n	8016f30 <netif_do_set_ipaddr+0x20>
+ 8016f22:	4b1e      	ldr	r3, [pc, #120]	; (8016f9c <netif_do_set_ipaddr+0x8c>)
+ 8016f24:	f240 12cb 	movw	r2, #459	; 0x1cb
+ 8016f28:	491d      	ldr	r1, [pc, #116]	; (8016fa0 <netif_do_set_ipaddr+0x90>)
+ 8016f2a:	481e      	ldr	r0, [pc, #120]	; (8016fa4 <netif_do_set_ipaddr+0x94>)
+ 8016f2c:	f00a fd2c 	bl	8021988 <iprintf>
+  LWIP_ASSERT("invalid pointer", old_addr != NULL);
+ 8016f30:	687b      	ldr	r3, [r7, #4]
+ 8016f32:	2b00      	cmp	r3, #0
+ 8016f34:	d106      	bne.n	8016f44 <netif_do_set_ipaddr+0x34>
+ 8016f36:	4b19      	ldr	r3, [pc, #100]	; (8016f9c <netif_do_set_ipaddr+0x8c>)
+ 8016f38:	f44f 72e6 	mov.w	r2, #460	; 0x1cc
+ 8016f3c:	4918      	ldr	r1, [pc, #96]	; (8016fa0 <netif_do_set_ipaddr+0x90>)
+ 8016f3e:	4819      	ldr	r0, [pc, #100]	; (8016fa4 <netif_do_set_ipaddr+0x94>)
+ 8016f40:	f00a fd22 	bl	8021988 <iprintf>
+
+  /* address is actually being changed? */
+  if (ip4_addr_cmp(ipaddr, netif_ip4_addr(netif)) == 0) {
+ 8016f44:	68bb      	ldr	r3, [r7, #8]
+ 8016f46:	681a      	ldr	r2, [r3, #0]
+ 8016f48:	68fb      	ldr	r3, [r7, #12]
+ 8016f4a:	3304      	adds	r3, #4
+ 8016f4c:	681b      	ldr	r3, [r3, #0]
+ 8016f4e:	429a      	cmp	r2, r3
+ 8016f50:	d01f      	beq.n	8016f92 <netif_do_set_ipaddr+0x82>
+    ip_addr_t new_addr;
+    *ip_2_ip4(&new_addr) = *ipaddr;
+ 8016f52:	68bb      	ldr	r3, [r7, #8]
+ 8016f54:	681b      	ldr	r3, [r3, #0]
+ 8016f56:	617b      	str	r3, [r7, #20]
+    IP_SET_TYPE_VAL(new_addr, IPADDR_TYPE_V4);
+
+    ip_addr_copy(*old_addr, *netif_ip_addr4(netif));
+ 8016f58:	68fb      	ldr	r3, [r7, #12]
+ 8016f5a:	3304      	adds	r3, #4
+ 8016f5c:	681a      	ldr	r2, [r3, #0]
+ 8016f5e:	687b      	ldr	r3, [r7, #4]
+ 8016f60:	601a      	str	r2, [r3, #0]
+
+    LWIP_DEBUGF(NETIF_DEBUG | LWIP_DBG_STATE, ("netif_set_ipaddr: netif address being changed\n"));
+ 8016f62:	4811      	ldr	r0, [pc, #68]	; (8016fa8 <netif_do_set_ipaddr+0x98>)
+ 8016f64:	f00a fd7e 	bl	8021a64 <puts>
+    netif_do_ip_addr_changed(old_addr, &new_addr);
+ 8016f68:	f107 0314 	add.w	r3, r7, #20
+ 8016f6c:	4619      	mov	r1, r3
+ 8016f6e:	6878      	ldr	r0, [r7, #4]
+ 8016f70:	f7ff ffbc 	bl	8016eec <netif_do_ip_addr_changed>
+
+    mib2_remove_ip4(netif);
+    mib2_remove_route_ip4(0, netif);
+    /* set new IP address to netif */
+    ip4_addr_set(ip_2_ip4(&netif->ip_addr), ipaddr);
+ 8016f74:	68bb      	ldr	r3, [r7, #8]
+ 8016f76:	2b00      	cmp	r3, #0
+ 8016f78:	d002      	beq.n	8016f80 <netif_do_set_ipaddr+0x70>
+ 8016f7a:	68bb      	ldr	r3, [r7, #8]
+ 8016f7c:	681b      	ldr	r3, [r3, #0]
+ 8016f7e:	e000      	b.n	8016f82 <netif_do_set_ipaddr+0x72>
+ 8016f80:	2300      	movs	r3, #0
+ 8016f82:	68fa      	ldr	r2, [r7, #12]
+ 8016f84:	6053      	str	r3, [r2, #4]
+    IP_SET_TYPE_VAL(netif->ip_addr, IPADDR_TYPE_V4);
+    mib2_add_ip4(netif);
+    mib2_add_route_ip4(0, netif);
+
+    netif_issue_reports(netif, NETIF_REPORT_TYPE_IPV4);
+ 8016f86:	2101      	movs	r1, #1
+ 8016f88:	68f8      	ldr	r0, [r7, #12]
+ 8016f8a:	f000 f92d 	bl	80171e8 <netif_issue_reports>
+
+    NETIF_STATUS_CALLBACK(netif);
+    return 1; /* address changed */
+ 8016f8e:	2301      	movs	r3, #1
+ 8016f90:	e000      	b.n	8016f94 <netif_do_set_ipaddr+0x84>
+  }
+  return 0; /* address unchanged */
+ 8016f92:	2300      	movs	r3, #0
+}
+ 8016f94:	4618      	mov	r0, r3
+ 8016f96:	3718      	adds	r7, #24
+ 8016f98:	46bd      	mov	sp, r7
+ 8016f9a:	bd80      	pop	{r7, pc}
+ 8016f9c:	08024308 	.word	0x08024308
+ 8016fa0:	0802446c 	.word	0x0802446c
+ 8016fa4:	08024358 	.word	0x08024358
+ 8016fa8:	0802447c 	.word	0x0802447c
+
+08016fac <netif_do_set_netmask>:
+  }
+}
+
+static int
+netif_do_set_netmask(struct netif *netif, const ip4_addr_t *netmask, ip_addr_t *old_nm)
+{
+ 8016fac:	b5b0      	push	{r4, r5, r7, lr}
+ 8016fae:	b088      	sub	sp, #32
+ 8016fb0:	af04      	add	r7, sp, #16
+ 8016fb2:	60f8      	str	r0, [r7, #12]
+ 8016fb4:	60b9      	str	r1, [r7, #8]
+ 8016fb6:	607a      	str	r2, [r7, #4]
+  /* address is actually being changed? */
+  if (ip4_addr_cmp(netmask, netif_ip4_netmask(netif)) == 0) {
+ 8016fb8:	68bb      	ldr	r3, [r7, #8]
+ 8016fba:	681a      	ldr	r2, [r3, #0]
+ 8016fbc:	68fb      	ldr	r3, [r7, #12]
+ 8016fbe:	3308      	adds	r3, #8
+ 8016fc0:	681b      	ldr	r3, [r3, #0]
+ 8016fc2:	429a      	cmp	r2, r3
+ 8016fc4:	d02d      	beq.n	8017022 <netif_do_set_netmask+0x76>
+#else
+    LWIP_UNUSED_ARG(old_nm);
+#endif
+    mib2_remove_route_ip4(0, netif);
+    /* set new netmask to netif */
+    ip4_addr_set(ip_2_ip4(&netif->netmask), netmask);
+ 8016fc6:	68bb      	ldr	r3, [r7, #8]
+ 8016fc8:	2b00      	cmp	r3, #0
+ 8016fca:	d002      	beq.n	8016fd2 <netif_do_set_netmask+0x26>
+ 8016fcc:	68bb      	ldr	r3, [r7, #8]
+ 8016fce:	681b      	ldr	r3, [r3, #0]
+ 8016fd0:	e000      	b.n	8016fd4 <netif_do_set_netmask+0x28>
+ 8016fd2:	2300      	movs	r3, #0
+ 8016fd4:	68fa      	ldr	r2, [r7, #12]
+ 8016fd6:	6093      	str	r3, [r2, #8]
+    IP_SET_TYPE_VAL(netif->netmask, IPADDR_TYPE_V4);
+    mib2_add_route_ip4(0, netif);
+    LWIP_DEBUGF(NETIF_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("netif: netmask of interface %c%c set to %"U16_F".%"U16_F".%"U16_F".%"U16_F"\n",
+ 8016fd8:	68fb      	ldr	r3, [r7, #12]
+ 8016fda:	f893 302e 	ldrb.w	r3, [r3, #46]	; 0x2e
+ 8016fde:	4618      	mov	r0, r3
+ 8016fe0:	68fb      	ldr	r3, [r7, #12]
+ 8016fe2:	f893 302f 	ldrb.w	r3, [r3, #47]	; 0x2f
+ 8016fe6:	461c      	mov	r4, r3
+ 8016fe8:	68fb      	ldr	r3, [r7, #12]
+ 8016fea:	3308      	adds	r3, #8
+ 8016fec:	781b      	ldrb	r3, [r3, #0]
+ 8016fee:	461d      	mov	r5, r3
+ 8016ff0:	68fb      	ldr	r3, [r7, #12]
+ 8016ff2:	3308      	adds	r3, #8
+ 8016ff4:	3301      	adds	r3, #1
+ 8016ff6:	781b      	ldrb	r3, [r3, #0]
+ 8016ff8:	461a      	mov	r2, r3
+ 8016ffa:	68fb      	ldr	r3, [r7, #12]
+ 8016ffc:	3308      	adds	r3, #8
+ 8016ffe:	3302      	adds	r3, #2
+ 8017000:	781b      	ldrb	r3, [r3, #0]
+ 8017002:	4619      	mov	r1, r3
+ 8017004:	68fb      	ldr	r3, [r7, #12]
+ 8017006:	3308      	adds	r3, #8
+ 8017008:	3303      	adds	r3, #3
+ 801700a:	781b      	ldrb	r3, [r3, #0]
+ 801700c:	9302      	str	r3, [sp, #8]
+ 801700e:	9101      	str	r1, [sp, #4]
+ 8017010:	9200      	str	r2, [sp, #0]
+ 8017012:	462b      	mov	r3, r5
+ 8017014:	4622      	mov	r2, r4
+ 8017016:	4601      	mov	r1, r0
+ 8017018:	4804      	ldr	r0, [pc, #16]	; (801702c <netif_do_set_netmask+0x80>)
+ 801701a:	f00a fcb5 	bl	8021988 <iprintf>
+                netif->name[0], netif->name[1],
+                ip4_addr1_16(netif_ip4_netmask(netif)),
+                ip4_addr2_16(netif_ip4_netmask(netif)),
+                ip4_addr3_16(netif_ip4_netmask(netif)),
+                ip4_addr4_16(netif_ip4_netmask(netif))));
+    return 1; /* netmask changed */
+ 801701e:	2301      	movs	r3, #1
+ 8017020:	e000      	b.n	8017024 <netif_do_set_netmask+0x78>
+  }
+  return 0; /* netmask unchanged */
+ 8017022:	2300      	movs	r3, #0
+}
+ 8017024:	4618      	mov	r0, r3
+ 8017026:	3710      	adds	r7, #16
+ 8017028:	46bd      	mov	sp, r7
+ 801702a:	bdb0      	pop	{r4, r5, r7, pc}
+ 801702c:	080244cc 	.word	0x080244cc
+
+08017030 <netif_do_set_gw>:
+  }
+}
+
+static int
+netif_do_set_gw(struct netif *netif, const ip4_addr_t *gw, ip_addr_t *old_gw)
+{
+ 8017030:	b5b0      	push	{r4, r5, r7, lr}
+ 8017032:	b088      	sub	sp, #32
+ 8017034:	af04      	add	r7, sp, #16
+ 8017036:	60f8      	str	r0, [r7, #12]
+ 8017038:	60b9      	str	r1, [r7, #8]
+ 801703a:	607a      	str	r2, [r7, #4]
+  /* address is actually being changed? */
+  if (ip4_addr_cmp(gw, netif_ip4_gw(netif)) == 0) {
+ 801703c:	68bb      	ldr	r3, [r7, #8]
+ 801703e:	681a      	ldr	r2, [r3, #0]
+ 8017040:	68fb      	ldr	r3, [r7, #12]
+ 8017042:	330c      	adds	r3, #12
+ 8017044:	681b      	ldr	r3, [r3, #0]
+ 8017046:	429a      	cmp	r2, r3
+ 8017048:	d02d      	beq.n	80170a6 <netif_do_set_gw+0x76>
+    ip_addr_copy(*old_gw, *netif_ip_gw4(netif));
+#else
+    LWIP_UNUSED_ARG(old_gw);
+#endif
+
+    ip4_addr_set(ip_2_ip4(&netif->gw), gw);
+ 801704a:	68bb      	ldr	r3, [r7, #8]
+ 801704c:	2b00      	cmp	r3, #0
+ 801704e:	d002      	beq.n	8017056 <netif_do_set_gw+0x26>
+ 8017050:	68bb      	ldr	r3, [r7, #8]
+ 8017052:	681b      	ldr	r3, [r3, #0]
+ 8017054:	e000      	b.n	8017058 <netif_do_set_gw+0x28>
+ 8017056:	2300      	movs	r3, #0
+ 8017058:	68fa      	ldr	r2, [r7, #12]
+ 801705a:	60d3      	str	r3, [r2, #12]
+    IP_SET_TYPE_VAL(netif->gw, IPADDR_TYPE_V4);
+    LWIP_DEBUGF(NETIF_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("netif: GW address of interface %c%c set to %"U16_F".%"U16_F".%"U16_F".%"U16_F"\n",
+ 801705c:	68fb      	ldr	r3, [r7, #12]
+ 801705e:	f893 302e 	ldrb.w	r3, [r3, #46]	; 0x2e
+ 8017062:	4618      	mov	r0, r3
+ 8017064:	68fb      	ldr	r3, [r7, #12]
+ 8017066:	f893 302f 	ldrb.w	r3, [r3, #47]	; 0x2f
+ 801706a:	461c      	mov	r4, r3
+ 801706c:	68fb      	ldr	r3, [r7, #12]
+ 801706e:	330c      	adds	r3, #12
+ 8017070:	781b      	ldrb	r3, [r3, #0]
+ 8017072:	461d      	mov	r5, r3
+ 8017074:	68fb      	ldr	r3, [r7, #12]
+ 8017076:	330c      	adds	r3, #12
+ 8017078:	3301      	adds	r3, #1
+ 801707a:	781b      	ldrb	r3, [r3, #0]
+ 801707c:	461a      	mov	r2, r3
+ 801707e:	68fb      	ldr	r3, [r7, #12]
+ 8017080:	330c      	adds	r3, #12
+ 8017082:	3302      	adds	r3, #2
+ 8017084:	781b      	ldrb	r3, [r3, #0]
+ 8017086:	4619      	mov	r1, r3
+ 8017088:	68fb      	ldr	r3, [r7, #12]
+ 801708a:	330c      	adds	r3, #12
+ 801708c:	3303      	adds	r3, #3
+ 801708e:	781b      	ldrb	r3, [r3, #0]
+ 8017090:	9302      	str	r3, [sp, #8]
+ 8017092:	9101      	str	r1, [sp, #4]
+ 8017094:	9200      	str	r2, [sp, #0]
+ 8017096:	462b      	mov	r3, r5
+ 8017098:	4622      	mov	r2, r4
+ 801709a:	4601      	mov	r1, r0
+ 801709c:	4804      	ldr	r0, [pc, #16]	; (80170b0 <netif_do_set_gw+0x80>)
+ 801709e:	f00a fc73 	bl	8021988 <iprintf>
+                netif->name[0], netif->name[1],
+                ip4_addr1_16(netif_ip4_gw(netif)),
+                ip4_addr2_16(netif_ip4_gw(netif)),
+                ip4_addr3_16(netif_ip4_gw(netif)),
+                ip4_addr4_16(netif_ip4_gw(netif))));
+    return 1; /* gateway changed */
+ 80170a2:	2301      	movs	r3, #1
+ 80170a4:	e000      	b.n	80170a8 <netif_do_set_gw+0x78>
+  }
+  return 0; /* gateway unchanged */
+ 80170a6:	2300      	movs	r3, #0
+}
+ 80170a8:	4618      	mov	r0, r3
+ 80170aa:	3710      	adds	r7, #16
+ 80170ac:	46bd      	mov	sp, r7
+ 80170ae:	bdb0      	pop	{r4, r5, r7, pc}
+ 80170b0:	0802452c 	.word	0x0802452c
+
+080170b4 <netif_set_addr>:
+ * @param gw the new default gateway
+ */
+void
+netif_set_addr(struct netif *netif, const ip4_addr_t *ipaddr, const ip4_addr_t *netmask,
+               const ip4_addr_t *gw)
+{
+ 80170b4:	b580      	push	{r7, lr}
+ 80170b6:	b088      	sub	sp, #32
+ 80170b8:	af00      	add	r7, sp, #0
+ 80170ba:	60f8      	str	r0, [r7, #12]
+ 80170bc:	60b9      	str	r1, [r7, #8]
+ 80170be:	607a      	str	r2, [r7, #4]
+ 80170c0:	603b      	str	r3, [r7, #0]
+  ip_addr_t old_nm_val;
+  ip_addr_t old_gw_val;
+  ip_addr_t *old_nm = &old_nm_val;
+  ip_addr_t *old_gw = &old_gw_val;
+#else
+  ip_addr_t *old_nm = NULL;
+ 80170c2:	2300      	movs	r3, #0
+ 80170c4:	61fb      	str	r3, [r7, #28]
+  ip_addr_t *old_gw = NULL;
+ 80170c6:	2300      	movs	r3, #0
+ 80170c8:	61bb      	str	r3, [r7, #24]
+  int remove;
+
+  LWIP_ASSERT_CORE_LOCKED();
+
+  /* Don't propagate NULL pointer (IPv4 ANY) to subsequent functions */
+  if (ipaddr == NULL) {
+ 80170ca:	68bb      	ldr	r3, [r7, #8]
+ 80170cc:	2b00      	cmp	r3, #0
+ 80170ce:	d101      	bne.n	80170d4 <netif_set_addr+0x20>
+    ipaddr = IP4_ADDR_ANY4;
+ 80170d0:	4b1c      	ldr	r3, [pc, #112]	; (8017144 <netif_set_addr+0x90>)
+ 80170d2:	60bb      	str	r3, [r7, #8]
+  }
+  if (netmask == NULL) {
+ 80170d4:	687b      	ldr	r3, [r7, #4]
+ 80170d6:	2b00      	cmp	r3, #0
+ 80170d8:	d101      	bne.n	80170de <netif_set_addr+0x2a>
+    netmask = IP4_ADDR_ANY4;
+ 80170da:	4b1a      	ldr	r3, [pc, #104]	; (8017144 <netif_set_addr+0x90>)
+ 80170dc:	607b      	str	r3, [r7, #4]
+  }
+  if (gw == NULL) {
+ 80170de:	683b      	ldr	r3, [r7, #0]
+ 80170e0:	2b00      	cmp	r3, #0
+ 80170e2:	d101      	bne.n	80170e8 <netif_set_addr+0x34>
+    gw = IP4_ADDR_ANY4;
+ 80170e4:	4b17      	ldr	r3, [pc, #92]	; (8017144 <netif_set_addr+0x90>)
+ 80170e6:	603b      	str	r3, [r7, #0]
+  }
+
+  remove = ip4_addr_isany(ipaddr);
+ 80170e8:	68bb      	ldr	r3, [r7, #8]
+ 80170ea:	2b00      	cmp	r3, #0
+ 80170ec:	d003      	beq.n	80170f6 <netif_set_addr+0x42>
+ 80170ee:	68bb      	ldr	r3, [r7, #8]
+ 80170f0:	681b      	ldr	r3, [r3, #0]
+ 80170f2:	2b00      	cmp	r3, #0
+ 80170f4:	d101      	bne.n	80170fa <netif_set_addr+0x46>
+ 80170f6:	2301      	movs	r3, #1
+ 80170f8:	e000      	b.n	80170fc <netif_set_addr+0x48>
+ 80170fa:	2300      	movs	r3, #0
+ 80170fc:	617b      	str	r3, [r7, #20]
+  if (remove) {
+ 80170fe:	697b      	ldr	r3, [r7, #20]
+ 8017100:	2b00      	cmp	r3, #0
+ 8017102:	d006      	beq.n	8017112 <netif_set_addr+0x5e>
+    /* when removing an address, we have to remove it *before* changing netmask/gw
+       to ensure that tcp RST segment can be sent correctly */
+    if (netif_do_set_ipaddr(netif, ipaddr, &old_addr)) {
+ 8017104:	f107 0310 	add.w	r3, r7, #16
+ 8017108:	461a      	mov	r2, r3
+ 801710a:	68b9      	ldr	r1, [r7, #8]
+ 801710c:	68f8      	ldr	r0, [r7, #12]
+ 801710e:	f7ff feff 	bl	8016f10 <netif_do_set_ipaddr>
+      change_reason |= LWIP_NSC_IPV4_ADDRESS_CHANGED;
+      cb_args.ipv4_changed.old_address = &old_addr;
+#endif
+    }
+  }
+  if (netif_do_set_netmask(netif, netmask, old_nm)) {
+ 8017112:	69fa      	ldr	r2, [r7, #28]
+ 8017114:	6879      	ldr	r1, [r7, #4]
+ 8017116:	68f8      	ldr	r0, [r7, #12]
+ 8017118:	f7ff ff48 	bl	8016fac <netif_do_set_netmask>
+#if LWIP_NETIF_EXT_STATUS_CALLBACK
+    change_reason |= LWIP_NSC_IPV4_NETMASK_CHANGED;
+    cb_args.ipv4_changed.old_netmask = old_nm;
+#endif
+  }
+  if (netif_do_set_gw(netif, gw, old_gw)) {
+ 801711c:	69ba      	ldr	r2, [r7, #24]
+ 801711e:	6839      	ldr	r1, [r7, #0]
+ 8017120:	68f8      	ldr	r0, [r7, #12]
+ 8017122:	f7ff ff85 	bl	8017030 <netif_do_set_gw>
+#if LWIP_NETIF_EXT_STATUS_CALLBACK
+    change_reason |= LWIP_NSC_IPV4_GATEWAY_CHANGED;
+    cb_args.ipv4_changed.old_gw = old_gw;
+#endif
+  }
+  if (!remove) {
+ 8017126:	697b      	ldr	r3, [r7, #20]
+ 8017128:	2b00      	cmp	r3, #0
+ 801712a:	d106      	bne.n	801713a <netif_set_addr+0x86>
+    /* set ipaddr last to ensure netmask/gw have been set when status callback is called */
+    if (netif_do_set_ipaddr(netif, ipaddr, &old_addr)) {
+ 801712c:	f107 0310 	add.w	r3, r7, #16
+ 8017130:	461a      	mov	r2, r3
+ 8017132:	68b9      	ldr	r1, [r7, #8]
+ 8017134:	68f8      	ldr	r0, [r7, #12]
+ 8017136:	f7ff feeb 	bl	8016f10 <netif_do_set_ipaddr>
+  if (change_reason != LWIP_NSC_NONE) {
+    change_reason |= LWIP_NSC_IPV4_SETTINGS_CHANGED;
+    netif_invoke_ext_callback(netif, change_reason, &cb_args);
+  }
+#endif
+}
+ 801713a:	bf00      	nop
+ 801713c:	3720      	adds	r7, #32
+ 801713e:	46bd      	mov	sp, r7
+ 8017140:	bd80      	pop	{r7, pc}
+ 8017142:	bf00      	nop
+ 8017144:	08026cec 	.word	0x08026cec
+
+08017148 <netif_set_default>:
+ *
+ * @param netif the default network interface
+ */
+void
+netif_set_default(struct netif *netif)
+{
+ 8017148:	b580      	push	{r7, lr}
+ 801714a:	b082      	sub	sp, #8
+ 801714c:	af00      	add	r7, sp, #0
+ 801714e:	6078      	str	r0, [r7, #4]
+    mib2_remove_route_ip4(1, netif);
+  } else {
+    /* install default route */
+    mib2_add_route_ip4(1, netif);
+  }
+  netif_default = netif;
+ 8017150:	4a0d      	ldr	r2, [pc, #52]	; (8017188 <netif_set_default+0x40>)
+ 8017152:	687b      	ldr	r3, [r7, #4]
+ 8017154:	6013      	str	r3, [r2, #0]
+  LWIP_DEBUGF(NETIF_DEBUG, ("netif: setting default interface %c%c\n",
+ 8017156:	687b      	ldr	r3, [r7, #4]
+ 8017158:	2b00      	cmp	r3, #0
+ 801715a:	d004      	beq.n	8017166 <netif_set_default+0x1e>
+ 801715c:	687b      	ldr	r3, [r7, #4]
+ 801715e:	f893 302e 	ldrb.w	r3, [r3, #46]	; 0x2e
+ 8017162:	4619      	mov	r1, r3
+ 8017164:	e000      	b.n	8017168 <netif_set_default+0x20>
+ 8017166:	2127      	movs	r1, #39	; 0x27
+ 8017168:	687b      	ldr	r3, [r7, #4]
+ 801716a:	2b00      	cmp	r3, #0
+ 801716c:	d003      	beq.n	8017176 <netif_set_default+0x2e>
+ 801716e:	687b      	ldr	r3, [r7, #4]
+ 8017170:	f893 302f 	ldrb.w	r3, [r3, #47]	; 0x2f
+ 8017174:	e000      	b.n	8017178 <netif_set_default+0x30>
+ 8017176:	2327      	movs	r3, #39	; 0x27
+ 8017178:	461a      	mov	r2, r3
+ 801717a:	4804      	ldr	r0, [pc, #16]	; (801718c <netif_set_default+0x44>)
+ 801717c:	f00a fc04 	bl	8021988 <iprintf>
+                            netif ? netif->name[0] : '\'', netif ? netif->name[1] : '\''));
+}
+ 8017180:	bf00      	nop
+ 8017182:	3708      	adds	r7, #8
+ 8017184:	46bd      	mov	sp, r7
+ 8017186:	bd80      	pop	{r7, pc}
+ 8017188:	2401a478 	.word	0x2401a478
+ 801718c:	080245a0 	.word	0x080245a0
+
+08017190 <netif_set_up>:
+ * Bring an interface up, available for processing
+ * traffic.
+ */
+void
+netif_set_up(struct netif *netif)
+{
+ 8017190:	b580      	push	{r7, lr}
+ 8017192:	b082      	sub	sp, #8
+ 8017194:	af00      	add	r7, sp, #0
+ 8017196:	6078      	str	r0, [r7, #4]
+  LWIP_ASSERT_CORE_LOCKED();
+
+  LWIP_ERROR("netif_set_up: invalid netif", netif != NULL, return);
+ 8017198:	687b      	ldr	r3, [r7, #4]
+ 801719a:	2b00      	cmp	r3, #0
+ 801719c:	d107      	bne.n	80171ae <netif_set_up+0x1e>
+ 801719e:	4b0f      	ldr	r3, [pc, #60]	; (80171dc <netif_set_up+0x4c>)
+ 80171a0:	f44f 7254 	mov.w	r2, #848	; 0x350
+ 80171a4:	490e      	ldr	r1, [pc, #56]	; (80171e0 <netif_set_up+0x50>)
+ 80171a6:	480f      	ldr	r0, [pc, #60]	; (80171e4 <netif_set_up+0x54>)
+ 80171a8:	f00a fbee 	bl	8021988 <iprintf>
+ 80171ac:	e013      	b.n	80171d6 <netif_set_up+0x46>
+
+  if (!(netif->flags & NETIF_FLAG_UP)) {
+ 80171ae:	687b      	ldr	r3, [r7, #4]
+ 80171b0:	f893 302d 	ldrb.w	r3, [r3, #45]	; 0x2d
+ 80171b4:	f003 0301 	and.w	r3, r3, #1
+ 80171b8:	2b00      	cmp	r3, #0
+ 80171ba:	d10c      	bne.n	80171d6 <netif_set_up+0x46>
+    netif_set_flags(netif, NETIF_FLAG_UP);
+ 80171bc:	687b      	ldr	r3, [r7, #4]
+ 80171be:	f893 302d 	ldrb.w	r3, [r3, #45]	; 0x2d
+ 80171c2:	f043 0301 	orr.w	r3, r3, #1
+ 80171c6:	b2da      	uxtb	r2, r3
+ 80171c8:	687b      	ldr	r3, [r7, #4]
+ 80171ca:	f883 202d 	strb.w	r2, [r3, #45]	; 0x2d
+      args.status_changed.state = 1;
+      netif_invoke_ext_callback(netif, LWIP_NSC_STATUS_CHANGED, &args);
+    }
+#endif
+
+    netif_issue_reports(netif, NETIF_REPORT_TYPE_IPV4 | NETIF_REPORT_TYPE_IPV6);
+ 80171ce:	2103      	movs	r1, #3
+ 80171d0:	6878      	ldr	r0, [r7, #4]
+ 80171d2:	f000 f809 	bl	80171e8 <netif_issue_reports>
+#if LWIP_IPV6
+    nd6_restart_netif(netif);
+#endif /* LWIP_IPV6 */
+  }
+}
+ 80171d6:	3708      	adds	r7, #8
+ 80171d8:	46bd      	mov	sp, r7
+ 80171da:	bd80      	pop	{r7, pc}
+ 80171dc:	08024308 	.word	0x08024308
+ 80171e0:	080245c8 	.word	0x080245c8
+ 80171e4:	08024358 	.word	0x08024358
+
+080171e8 <netif_issue_reports>:
+
+/** Send ARP/IGMP/MLD/RS events, e.g. on link-up/netif-up or addr-change
+ */
+static void
+netif_issue_reports(struct netif *netif, u8_t report_type)
+{
+ 80171e8:	b580      	push	{r7, lr}
+ 80171ea:	b082      	sub	sp, #8
+ 80171ec:	af00      	add	r7, sp, #0
+ 80171ee:	6078      	str	r0, [r7, #4]
+ 80171f0:	460b      	mov	r3, r1
+ 80171f2:	70fb      	strb	r3, [r7, #3]
+  LWIP_ASSERT("netif_issue_reports: invalid netif", netif != NULL);
+ 80171f4:	687b      	ldr	r3, [r7, #4]
+ 80171f6:	2b00      	cmp	r3, #0
+ 80171f8:	d106      	bne.n	8017208 <netif_issue_reports+0x20>
+ 80171fa:	4b18      	ldr	r3, [pc, #96]	; (801725c <netif_issue_reports+0x74>)
+ 80171fc:	f240 326d 	movw	r2, #877	; 0x36d
+ 8017200:	4917      	ldr	r1, [pc, #92]	; (8017260 <netif_issue_reports+0x78>)
+ 8017202:	4818      	ldr	r0, [pc, #96]	; (8017264 <netif_issue_reports+0x7c>)
+ 8017204:	f00a fbc0 	bl	8021988 <iprintf>
+
+  /* Only send reports when both link and admin states are up */
+  if (!(netif->flags & NETIF_FLAG_LINK_UP) ||
+ 8017208:	687b      	ldr	r3, [r7, #4]
+ 801720a:	f893 302d 	ldrb.w	r3, [r3, #45]	; 0x2d
+ 801720e:	f003 0304 	and.w	r3, r3, #4
+ 8017212:	2b00      	cmp	r3, #0
+ 8017214:	d01e      	beq.n	8017254 <netif_issue_reports+0x6c>
+      !(netif->flags & NETIF_FLAG_UP)) {
+ 8017216:	687b      	ldr	r3, [r7, #4]
+ 8017218:	f893 302d 	ldrb.w	r3, [r3, #45]	; 0x2d
+ 801721c:	f003 0301 	and.w	r3, r3, #1
+  if (!(netif->flags & NETIF_FLAG_LINK_UP) ||
+ 8017220:	2b00      	cmp	r3, #0
+ 8017222:	d017      	beq.n	8017254 <netif_issue_reports+0x6c>
+    return;
+  }
+
+#if LWIP_IPV4
+  if ((report_type & NETIF_REPORT_TYPE_IPV4) &&
+ 8017224:	78fb      	ldrb	r3, [r7, #3]
+ 8017226:	f003 0301 	and.w	r3, r3, #1
+ 801722a:	2b00      	cmp	r3, #0
+ 801722c:	d013      	beq.n	8017256 <netif_issue_reports+0x6e>
+      !ip4_addr_isany_val(*netif_ip4_addr(netif))) {
+ 801722e:	687b      	ldr	r3, [r7, #4]
+ 8017230:	3304      	adds	r3, #4
+ 8017232:	681b      	ldr	r3, [r3, #0]
+  if ((report_type & NETIF_REPORT_TYPE_IPV4) &&
+ 8017234:	2b00      	cmp	r3, #0
+ 8017236:	d00e      	beq.n	8017256 <netif_issue_reports+0x6e>
+#if LWIP_ARP
+    /* For Ethernet network interfaces, we would like to send a "gratuitous ARP" */
+    if (netif->flags & (NETIF_FLAG_ETHARP)) {
+ 8017238:	687b      	ldr	r3, [r7, #4]
+ 801723a:	f893 302d 	ldrb.w	r3, [r3, #45]	; 0x2d
+ 801723e:	f003 0308 	and.w	r3, r3, #8
+ 8017242:	2b00      	cmp	r3, #0
+ 8017244:	d007      	beq.n	8017256 <netif_issue_reports+0x6e>
+      etharp_gratuitous(netif);
+ 8017246:	687b      	ldr	r3, [r7, #4]
+ 8017248:	3304      	adds	r3, #4
+ 801724a:	4619      	mov	r1, r3
+ 801724c:	6878      	ldr	r0, [r7, #4]
+ 801724e:	f008 fc87 	bl	801fb60 <etharp_request>
+ 8017252:	e000      	b.n	8017256 <netif_issue_reports+0x6e>
+    return;
+ 8017254:	bf00      	nop
+    /* send mld memberships */
+    mld6_report_groups(netif);
+#endif /* LWIP_IPV6_MLD */
+  }
+#endif /* LWIP_IPV6 */
+}
+ 8017256:	3708      	adds	r7, #8
+ 8017258:	46bd      	mov	sp, r7
+ 801725a:	bd80      	pop	{r7, pc}
+ 801725c:	08024308 	.word	0x08024308
+ 8017260:	080245e4 	.word	0x080245e4
+ 8017264:	08024358 	.word	0x08024358
+
+08017268 <netif_set_down>:
+ * @ingroup netif
+ * Bring an interface down, disabling any traffic processing.
+ */
+void
+netif_set_down(struct netif *netif)
+{
+ 8017268:	b580      	push	{r7, lr}
+ 801726a:	b082      	sub	sp, #8
+ 801726c:	af00      	add	r7, sp, #0
+ 801726e:	6078      	str	r0, [r7, #4]
+  LWIP_ASSERT_CORE_LOCKED();
+
+  LWIP_ERROR("netif_set_down: invalid netif", netif != NULL, return);
+ 8017270:	687b      	ldr	r3, [r7, #4]
+ 8017272:	2b00      	cmp	r3, #0
+ 8017274:	d107      	bne.n	8017286 <netif_set_down+0x1e>
+ 8017276:	4b12      	ldr	r3, [pc, #72]	; (80172c0 <netif_set_down+0x58>)
+ 8017278:	f240 329b 	movw	r2, #923	; 0x39b
+ 801727c:	4911      	ldr	r1, [pc, #68]	; (80172c4 <netif_set_down+0x5c>)
+ 801727e:	4812      	ldr	r0, [pc, #72]	; (80172c8 <netif_set_down+0x60>)
+ 8017280:	f00a fb82 	bl	8021988 <iprintf>
+ 8017284:	e019      	b.n	80172ba <netif_set_down+0x52>
+
+  if (netif->flags & NETIF_FLAG_UP) {
+ 8017286:	687b      	ldr	r3, [r7, #4]
+ 8017288:	f893 302d 	ldrb.w	r3, [r3, #45]	; 0x2d
+ 801728c:	f003 0301 	and.w	r3, r3, #1
+ 8017290:	2b00      	cmp	r3, #0
+ 8017292:	d012      	beq.n	80172ba <netif_set_down+0x52>
+      args.status_changed.state = 0;
+      netif_invoke_ext_callback(netif, LWIP_NSC_STATUS_CHANGED, &args);
+    }
+#endif
+
+    netif_clear_flags(netif, NETIF_FLAG_UP);
+ 8017294:	687b      	ldr	r3, [r7, #4]
+ 8017296:	f893 302d 	ldrb.w	r3, [r3, #45]	; 0x2d
+ 801729a:	f023 0301 	bic.w	r3, r3, #1
+ 801729e:	b2da      	uxtb	r2, r3
+ 80172a0:	687b      	ldr	r3, [r7, #4]
+ 80172a2:	f883 202d 	strb.w	r2, [r3, #45]	; 0x2d
+    MIB2_COPY_SYSUPTIME_TO(&netif->ts);
+
+#if LWIP_IPV4 && LWIP_ARP
+    if (netif->flags & NETIF_FLAG_ETHARP) {
+ 80172a6:	687b      	ldr	r3, [r7, #4]
+ 80172a8:	f893 302d 	ldrb.w	r3, [r3, #45]	; 0x2d
+ 80172ac:	f003 0308 	and.w	r3, r3, #8
+ 80172b0:	2b00      	cmp	r3, #0
+ 80172b2:	d002      	beq.n	80172ba <netif_set_down+0x52>
+      etharp_cleanup_netif(netif);
+ 80172b4:	6878      	ldr	r0, [r7, #4]
+ 80172b6:	f008 f811 	bl	801f2dc <etharp_cleanup_netif>
+    nd6_cleanup_netif(netif);
+#endif /* LWIP_IPV6 */
+
+    NETIF_STATUS_CALLBACK(netif);
+  }
+}
+ 80172ba:	3708      	adds	r7, #8
+ 80172bc:	46bd      	mov	sp, r7
+ 80172be:	bd80      	pop	{r7, pc}
+ 80172c0:	08024308 	.word	0x08024308
+ 80172c4:	08024608 	.word	0x08024608
+ 80172c8:	08024358 	.word	0x08024358
+
+080172cc <netif_set_link_up>:
+ * @ingroup netif
+ * Called by a driver when its link goes up
+ */
+void
+netif_set_link_up(struct netif *netif)
+{
+ 80172cc:	b580      	push	{r7, lr}
+ 80172ce:	b082      	sub	sp, #8
+ 80172d0:	af00      	add	r7, sp, #0
+ 80172d2:	6078      	str	r0, [r7, #4]
+  LWIP_ASSERT_CORE_LOCKED();
+
+  LWIP_ERROR("netif_set_link_up: invalid netif", netif != NULL, return);
+ 80172d4:	687b      	ldr	r3, [r7, #4]
+ 80172d6:	2b00      	cmp	r3, #0
+ 80172d8:	d107      	bne.n	80172ea <netif_set_link_up+0x1e>
+ 80172da:	4b13      	ldr	r3, [pc, #76]	; (8017328 <netif_set_link_up+0x5c>)
+ 80172dc:	f44f 7278 	mov.w	r2, #992	; 0x3e0
+ 80172e0:	4912      	ldr	r1, [pc, #72]	; (801732c <netif_set_link_up+0x60>)
+ 80172e2:	4813      	ldr	r0, [pc, #76]	; (8017330 <netif_set_link_up+0x64>)
+ 80172e4:	f00a fb50 	bl	8021988 <iprintf>
+ 80172e8:	e01b      	b.n	8017322 <netif_set_link_up+0x56>
+
+  if (!(netif->flags & NETIF_FLAG_LINK_UP)) {
+ 80172ea:	687b      	ldr	r3, [r7, #4]
+ 80172ec:	f893 302d 	ldrb.w	r3, [r3, #45]	; 0x2d
+ 80172f0:	f003 0304 	and.w	r3, r3, #4
+ 80172f4:	2b00      	cmp	r3, #0
+ 80172f6:	d114      	bne.n	8017322 <netif_set_link_up+0x56>
+    netif_set_flags(netif, NETIF_FLAG_LINK_UP);
+ 80172f8:	687b      	ldr	r3, [r7, #4]
+ 80172fa:	f893 302d 	ldrb.w	r3, [r3, #45]	; 0x2d
+ 80172fe:	f043 0304 	orr.w	r3, r3, #4
+ 8017302:	b2da      	uxtb	r2, r3
+ 8017304:	687b      	ldr	r3, [r7, #4]
+ 8017306:	f883 202d 	strb.w	r2, [r3, #45]	; 0x2d
+
+#if LWIP_AUTOIP
+    autoip_network_changed(netif);
+#endif /* LWIP_AUTOIP */
+
+    netif_issue_reports(netif, NETIF_REPORT_TYPE_IPV4 | NETIF_REPORT_TYPE_IPV6);
+ 801730a:	2103      	movs	r1, #3
+ 801730c:	6878      	ldr	r0, [r7, #4]
+ 801730e:	f7ff ff6b 	bl	80171e8 <netif_issue_reports>
+#if LWIP_IPV6
+    nd6_restart_netif(netif);
+#endif /* LWIP_IPV6 */
+
+    NETIF_LINK_CALLBACK(netif);
+ 8017312:	687b      	ldr	r3, [r7, #4]
+ 8017314:	69db      	ldr	r3, [r3, #28]
+ 8017316:	2b00      	cmp	r3, #0
+ 8017318:	d003      	beq.n	8017322 <netif_set_link_up+0x56>
+ 801731a:	687b      	ldr	r3, [r7, #4]
+ 801731c:	69db      	ldr	r3, [r3, #28]
+ 801731e:	6878      	ldr	r0, [r7, #4]
+ 8017320:	4798      	blx	r3
+      args.link_changed.state = 1;
+      netif_invoke_ext_callback(netif, LWIP_NSC_LINK_CHANGED, &args);
+    }
+#endif
+  }
+}
+ 8017322:	3708      	adds	r7, #8
+ 8017324:	46bd      	mov	sp, r7
+ 8017326:	bd80      	pop	{r7, pc}
+ 8017328:	08024308 	.word	0x08024308
+ 801732c:	08024628 	.word	0x08024628
+ 8017330:	08024358 	.word	0x08024358
+
+08017334 <netif_set_link_down>:
+ * @ingroup netif
+ * Called by a driver when its link goes down
+ */
+void
+netif_set_link_down(struct netif *netif)
+{
+ 8017334:	b580      	push	{r7, lr}
+ 8017336:	b082      	sub	sp, #8
+ 8017338:	af00      	add	r7, sp, #0
+ 801733a:	6078      	str	r0, [r7, #4]
+  LWIP_ASSERT_CORE_LOCKED();
+
+  LWIP_ERROR("netif_set_link_down: invalid netif", netif != NULL, return);
+ 801733c:	687b      	ldr	r3, [r7, #4]
+ 801733e:	2b00      	cmp	r3, #0
+ 8017340:	d107      	bne.n	8017352 <netif_set_link_down+0x1e>
+ 8017342:	4b11      	ldr	r3, [pc, #68]	; (8017388 <netif_set_link_down+0x54>)
+ 8017344:	f240 4206 	movw	r2, #1030	; 0x406
+ 8017348:	4910      	ldr	r1, [pc, #64]	; (801738c <netif_set_link_down+0x58>)
+ 801734a:	4811      	ldr	r0, [pc, #68]	; (8017390 <netif_set_link_down+0x5c>)
+ 801734c:	f00a fb1c 	bl	8021988 <iprintf>
+ 8017350:	e017      	b.n	8017382 <netif_set_link_down+0x4e>
+
+  if (netif->flags & NETIF_FLAG_LINK_UP) {
+ 8017352:	687b      	ldr	r3, [r7, #4]
+ 8017354:	f893 302d 	ldrb.w	r3, [r3, #45]	; 0x2d
+ 8017358:	f003 0304 	and.w	r3, r3, #4
+ 801735c:	2b00      	cmp	r3, #0
+ 801735e:	d010      	beq.n	8017382 <netif_set_link_down+0x4e>
+    netif_clear_flags(netif, NETIF_FLAG_LINK_UP);
+ 8017360:	687b      	ldr	r3, [r7, #4]
+ 8017362:	f893 302d 	ldrb.w	r3, [r3, #45]	; 0x2d
+ 8017366:	f023 0304 	bic.w	r3, r3, #4
+ 801736a:	b2da      	uxtb	r2, r3
+ 801736c:	687b      	ldr	r3, [r7, #4]
+ 801736e:	f883 202d 	strb.w	r2, [r3, #45]	; 0x2d
+    NETIF_LINK_CALLBACK(netif);
+ 8017372:	687b      	ldr	r3, [r7, #4]
+ 8017374:	69db      	ldr	r3, [r3, #28]
+ 8017376:	2b00      	cmp	r3, #0
+ 8017378:	d003      	beq.n	8017382 <netif_set_link_down+0x4e>
+ 801737a:	687b      	ldr	r3, [r7, #4]
+ 801737c:	69db      	ldr	r3, [r3, #28]
+ 801737e:	6878      	ldr	r0, [r7, #4]
+ 8017380:	4798      	blx	r3
+      args.link_changed.state = 0;
+      netif_invoke_ext_callback(netif, LWIP_NSC_LINK_CHANGED, &args);
+    }
+#endif
+  }
+}
+ 8017382:	3708      	adds	r7, #8
+ 8017384:	46bd      	mov	sp, r7
+ 8017386:	bd80      	pop	{r7, pc}
+ 8017388:	08024308 	.word	0x08024308
+ 801738c:	0802464c 	.word	0x0802464c
+ 8017390:	08024358 	.word	0x08024358
+
+08017394 <netif_set_link_callback>:
+ * @ingroup netif
+ * Set callback to be called when link is brought up/down
+ */
+void
+netif_set_link_callback(struct netif *netif, netif_status_callback_fn link_callback)
+{
+ 8017394:	b480      	push	{r7}
+ 8017396:	b083      	sub	sp, #12
+ 8017398:	af00      	add	r7, sp, #0
+ 801739a:	6078      	str	r0, [r7, #4]
+ 801739c:	6039      	str	r1, [r7, #0]
+  LWIP_ASSERT_CORE_LOCKED();
+
+  if (netif) {
+ 801739e:	687b      	ldr	r3, [r7, #4]
+ 80173a0:	2b00      	cmp	r3, #0
+ 80173a2:	d002      	beq.n	80173aa <netif_set_link_callback+0x16>
+    netif->link_callback = link_callback;
+ 80173a4:	687b      	ldr	r3, [r7, #4]
+ 80173a6:	683a      	ldr	r2, [r7, #0]
+ 80173a8:	61da      	str	r2, [r3, #28]
+  }
+}
+ 80173aa:	bf00      	nop
+ 80173ac:	370c      	adds	r7, #12
+ 80173ae:	46bd      	mov	sp, r7
+ 80173b0:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 80173b4:	4770      	bx	lr
+
+080173b6 <netif_null_output_ip4>:
+#if LWIP_IPV4
+/** Dummy IPv4 output function for netifs not supporting IPv4
+ */
+static err_t
+netif_null_output_ip4(struct netif *netif, struct pbuf *p, const ip4_addr_t *ipaddr)
+{
+ 80173b6:	b480      	push	{r7}
+ 80173b8:	b085      	sub	sp, #20
+ 80173ba:	af00      	add	r7, sp, #0
+ 80173bc:	60f8      	str	r0, [r7, #12]
+ 80173be:	60b9      	str	r1, [r7, #8]
+ 80173c0:	607a      	str	r2, [r7, #4]
+  LWIP_UNUSED_ARG(netif);
+  LWIP_UNUSED_ARG(p);
+  LWIP_UNUSED_ARG(ipaddr);
+
+  return ERR_IF;
+ 80173c2:	f06f 030b 	mvn.w	r3, #11
+}
+ 80173c6:	4618      	mov	r0, r3
+ 80173c8:	3714      	adds	r7, #20
+ 80173ca:	46bd      	mov	sp, r7
+ 80173cc:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 80173d0:	4770      	bx	lr
+	...
+
+080173d4 <netif_get_by_index>:
+*
+* @param idx index of netif to find
+*/
+struct netif *
+netif_get_by_index(u8_t idx)
+{
+ 80173d4:	b480      	push	{r7}
+ 80173d6:	b085      	sub	sp, #20
+ 80173d8:	af00      	add	r7, sp, #0
+ 80173da:	4603      	mov	r3, r0
+ 80173dc:	71fb      	strb	r3, [r7, #7]
+  struct netif *netif;
+
+  LWIP_ASSERT_CORE_LOCKED();
+
+  if (idx != NETIF_NO_INDEX) {
+ 80173de:	79fb      	ldrb	r3, [r7, #7]
+ 80173e0:	2b00      	cmp	r3, #0
+ 80173e2:	d013      	beq.n	801740c <netif_get_by_index+0x38>
+    NETIF_FOREACH(netif) {
+ 80173e4:	4b0d      	ldr	r3, [pc, #52]	; (801741c <netif_get_by_index+0x48>)
+ 80173e6:	681b      	ldr	r3, [r3, #0]
+ 80173e8:	60fb      	str	r3, [r7, #12]
+ 80173ea:	e00c      	b.n	8017406 <netif_get_by_index+0x32>
+      if (idx == netif_get_index(netif)) {
+ 80173ec:	68fb      	ldr	r3, [r7, #12]
+ 80173ee:	f893 3030 	ldrb.w	r3, [r3, #48]	; 0x30
+ 80173f2:	3301      	adds	r3, #1
+ 80173f4:	b2db      	uxtb	r3, r3
+ 80173f6:	79fa      	ldrb	r2, [r7, #7]
+ 80173f8:	429a      	cmp	r2, r3
+ 80173fa:	d101      	bne.n	8017400 <netif_get_by_index+0x2c>
+        return netif; /* found! */
+ 80173fc:	68fb      	ldr	r3, [r7, #12]
+ 80173fe:	e006      	b.n	801740e <netif_get_by_index+0x3a>
+    NETIF_FOREACH(netif) {
+ 8017400:	68fb      	ldr	r3, [r7, #12]
+ 8017402:	681b      	ldr	r3, [r3, #0]
+ 8017404:	60fb      	str	r3, [r7, #12]
+ 8017406:	68fb      	ldr	r3, [r7, #12]
+ 8017408:	2b00      	cmp	r3, #0
+ 801740a:	d1ef      	bne.n	80173ec <netif_get_by_index+0x18>
+      }
+    }
+  }
+
+  return NULL;
+ 801740c:	2300      	movs	r3, #0
+}
+ 801740e:	4618      	mov	r0, r3
+ 8017410:	3714      	adds	r7, #20
+ 8017412:	46bd      	mov	sp, r7
+ 8017414:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8017418:	4770      	bx	lr
+ 801741a:	bf00      	nop
+ 801741c:	2401a474 	.word	0x2401a474
+
+08017420 <pbuf_free_ooseq>:
+#if !NO_SYS
+static
+#endif /* !NO_SYS */
+void
+pbuf_free_ooseq(void)
+{
+ 8017420:	b580      	push	{r7, lr}
+ 8017422:	b082      	sub	sp, #8
+ 8017424:	af00      	add	r7, sp, #0
+  struct tcp_pcb *pcb;
+  SYS_ARCH_SET(pbuf_free_ooseq_pending, 0);
+ 8017426:	f00a f915 	bl	8021654 <sys_arch_protect>
+ 801742a:	6038      	str	r0, [r7, #0]
+ 801742c:	4b0d      	ldr	r3, [pc, #52]	; (8017464 <pbuf_free_ooseq+0x44>)
+ 801742e:	2200      	movs	r2, #0
+ 8017430:	701a      	strb	r2, [r3, #0]
+ 8017432:	6838      	ldr	r0, [r7, #0]
+ 8017434:	f00a f91c 	bl	8021670 <sys_arch_unprotect>
+
+  for (pcb = tcp_active_pcbs; NULL != pcb; pcb = pcb->next) {
+ 8017438:	4b0b      	ldr	r3, [pc, #44]	; (8017468 <pbuf_free_ooseq+0x48>)
+ 801743a:	681b      	ldr	r3, [r3, #0]
+ 801743c:	607b      	str	r3, [r7, #4]
+ 801743e:	e00a      	b.n	8017456 <pbuf_free_ooseq+0x36>
+    if (pcb->ooseq != NULL) {
+ 8017440:	687b      	ldr	r3, [r7, #4]
+ 8017442:	6f5b      	ldr	r3, [r3, #116]	; 0x74
+ 8017444:	2b00      	cmp	r3, #0
+ 8017446:	d003      	beq.n	8017450 <pbuf_free_ooseq+0x30>
+      /** Free the ooseq pbufs of one PCB only */
+      LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_free_ooseq: freeing out-of-sequence pbufs\n"));
+      tcp_free_ooseq(pcb);
+ 8017448:	6878      	ldr	r0, [r7, #4]
+ 801744a:	f002 fc9f 	bl	8019d8c <tcp_free_ooseq>
+      return;
+ 801744e:	e005      	b.n	801745c <pbuf_free_ooseq+0x3c>
+  for (pcb = tcp_active_pcbs; NULL != pcb; pcb = pcb->next) {
+ 8017450:	687b      	ldr	r3, [r7, #4]
+ 8017452:	68db      	ldr	r3, [r3, #12]
+ 8017454:	607b      	str	r3, [r7, #4]
+ 8017456:	687b      	ldr	r3, [r7, #4]
+ 8017458:	2b00      	cmp	r3, #0
+ 801745a:	d1f1      	bne.n	8017440 <pbuf_free_ooseq+0x20>
+    }
+  }
+}
+ 801745c:	3708      	adds	r7, #8
+ 801745e:	46bd      	mov	sp, r7
+ 8017460:	bd80      	pop	{r7, pc}
+ 8017462:	bf00      	nop
+ 8017464:	2401a47d 	.word	0x2401a47d
+ 8017468:	2401a48c 	.word	0x2401a48c
+
+0801746c <pbuf_free_ooseq_callback>:
+/**
+ * Just a callback function for tcpip_callback() that calls pbuf_free_ooseq().
+ */
+static void
+pbuf_free_ooseq_callback(void *arg)
+{
+ 801746c:	b580      	push	{r7, lr}
+ 801746e:	b082      	sub	sp, #8
+ 8017470:	af00      	add	r7, sp, #0
+ 8017472:	6078      	str	r0, [r7, #4]
+  LWIP_UNUSED_ARG(arg);
+  pbuf_free_ooseq();
+ 8017474:	f7ff ffd4 	bl	8017420 <pbuf_free_ooseq>
+}
+ 8017478:	bf00      	nop
+ 801747a:	3708      	adds	r7, #8
+ 801747c:	46bd      	mov	sp, r7
+ 801747e:	bd80      	pop	{r7, pc}
+
+08017480 <pbuf_pool_is_empty>:
+#endif /* !NO_SYS */
+
+/** Queue a call to pbuf_free_ooseq if not already queued. */
+static void
+pbuf_pool_is_empty(void)
+{
+ 8017480:	b580      	push	{r7, lr}
+ 8017482:	b082      	sub	sp, #8
+ 8017484:	af00      	add	r7, sp, #0
+#ifndef PBUF_POOL_FREE_OOSEQ_QUEUE_CALL
+  SYS_ARCH_SET(pbuf_free_ooseq_pending, 1);
+#else /* PBUF_POOL_FREE_OOSEQ_QUEUE_CALL */
+  u8_t queued;
+  SYS_ARCH_DECL_PROTECT(old_level);
+  SYS_ARCH_PROTECT(old_level);
+ 8017486:	f00a f8e5 	bl	8021654 <sys_arch_protect>
+ 801748a:	6078      	str	r0, [r7, #4]
+  queued = pbuf_free_ooseq_pending;
+ 801748c:	4b0f      	ldr	r3, [pc, #60]	; (80174cc <pbuf_pool_is_empty+0x4c>)
+ 801748e:	781b      	ldrb	r3, [r3, #0]
+ 8017490:	70fb      	strb	r3, [r7, #3]
+  pbuf_free_ooseq_pending = 1;
+ 8017492:	4b0e      	ldr	r3, [pc, #56]	; (80174cc <pbuf_pool_is_empty+0x4c>)
+ 8017494:	2201      	movs	r2, #1
+ 8017496:	701a      	strb	r2, [r3, #0]
+  SYS_ARCH_UNPROTECT(old_level);
+ 8017498:	6878      	ldr	r0, [r7, #4]
+ 801749a:	f00a f8e9 	bl	8021670 <sys_arch_unprotect>
+
+  if (!queued) {
+ 801749e:	78fb      	ldrb	r3, [r7, #3]
+ 80174a0:	2b00      	cmp	r3, #0
+ 80174a2:	d10f      	bne.n	80174c4 <pbuf_pool_is_empty+0x44>
+    /* queue a call to pbuf_free_ooseq if not already queued */
+    PBUF_POOL_FREE_OOSEQ_QUEUE_CALL();
+ 80174a4:	2100      	movs	r1, #0
+ 80174a6:	480a      	ldr	r0, [pc, #40]	; (80174d0 <pbuf_pool_is_empty+0x50>)
+ 80174a8:	f7fe fcaa 	bl	8015e00 <tcpip_try_callback>
+ 80174ac:	4603      	mov	r3, r0
+ 80174ae:	2b00      	cmp	r3, #0
+ 80174b0:	d008      	beq.n	80174c4 <pbuf_pool_is_empty+0x44>
+ 80174b2:	f00a f8cf 	bl	8021654 <sys_arch_protect>
+ 80174b6:	6078      	str	r0, [r7, #4]
+ 80174b8:	4b04      	ldr	r3, [pc, #16]	; (80174cc <pbuf_pool_is_empty+0x4c>)
+ 80174ba:	2200      	movs	r2, #0
+ 80174bc:	701a      	strb	r2, [r3, #0]
+ 80174be:	6878      	ldr	r0, [r7, #4]
+ 80174c0:	f00a f8d6 	bl	8021670 <sys_arch_unprotect>
+  }
+#endif /* PBUF_POOL_FREE_OOSEQ_QUEUE_CALL */
+}
+ 80174c4:	bf00      	nop
+ 80174c6:	3708      	adds	r7, #8
+ 80174c8:	46bd      	mov	sp, r7
+ 80174ca:	bd80      	pop	{r7, pc}
+ 80174cc:	2401a47d 	.word	0x2401a47d
+ 80174d0:	0801746d 	.word	0x0801746d
+
+080174d4 <pbuf_init_alloced_pbuf>:
+#endif /* !LWIP_TCP || !TCP_QUEUE_OOSEQ || !PBUF_POOL_FREE_OOSEQ */
+
+/* Initialize members of struct pbuf after allocation */
+static void
+pbuf_init_alloced_pbuf(struct pbuf *p, void *payload, u16_t tot_len, u16_t len, pbuf_type type, u8_t flags)
+{
+ 80174d4:	b480      	push	{r7}
+ 80174d6:	b085      	sub	sp, #20
+ 80174d8:	af00      	add	r7, sp, #0
+ 80174da:	60f8      	str	r0, [r7, #12]
+ 80174dc:	60b9      	str	r1, [r7, #8]
+ 80174de:	4611      	mov	r1, r2
+ 80174e0:	461a      	mov	r2, r3
+ 80174e2:	460b      	mov	r3, r1
+ 80174e4:	80fb      	strh	r3, [r7, #6]
+ 80174e6:	4613      	mov	r3, r2
+ 80174e8:	80bb      	strh	r3, [r7, #4]
+  p->next = NULL;
+ 80174ea:	68fb      	ldr	r3, [r7, #12]
+ 80174ec:	2200      	movs	r2, #0
+ 80174ee:	601a      	str	r2, [r3, #0]
+  p->payload = payload;
+ 80174f0:	68fb      	ldr	r3, [r7, #12]
+ 80174f2:	68ba      	ldr	r2, [r7, #8]
+ 80174f4:	605a      	str	r2, [r3, #4]
+  p->tot_len = tot_len;
+ 80174f6:	68fb      	ldr	r3, [r7, #12]
+ 80174f8:	88fa      	ldrh	r2, [r7, #6]
+ 80174fa:	811a      	strh	r2, [r3, #8]
+  p->len = len;
+ 80174fc:	68fb      	ldr	r3, [r7, #12]
+ 80174fe:	88ba      	ldrh	r2, [r7, #4]
+ 8017500:	815a      	strh	r2, [r3, #10]
+  p->type_internal = (u8_t)type;
+ 8017502:	8b3b      	ldrh	r3, [r7, #24]
+ 8017504:	b2da      	uxtb	r2, r3
+ 8017506:	68fb      	ldr	r3, [r7, #12]
+ 8017508:	731a      	strb	r2, [r3, #12]
+  p->flags = flags;
+ 801750a:	68fb      	ldr	r3, [r7, #12]
+ 801750c:	7f3a      	ldrb	r2, [r7, #28]
+ 801750e:	735a      	strb	r2, [r3, #13]
+  p->ref = 1;
+ 8017510:	68fb      	ldr	r3, [r7, #12]
+ 8017512:	2201      	movs	r2, #1
+ 8017514:	739a      	strb	r2, [r3, #14]
+  p->if_idx = NETIF_NO_INDEX;
+ 8017516:	68fb      	ldr	r3, [r7, #12]
+ 8017518:	2200      	movs	r2, #0
+ 801751a:	73da      	strb	r2, [r3, #15]
+}
+ 801751c:	bf00      	nop
+ 801751e:	3714      	adds	r7, #20
+ 8017520:	46bd      	mov	sp, r7
+ 8017522:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8017526:	4770      	bx	lr
+
+08017528 <pbuf_alloc>:
+ * @return the allocated pbuf. If multiple pbufs where allocated, this
+ * is the first pbuf of a pbuf chain.
+ */
+struct pbuf *
+pbuf_alloc(pbuf_layer layer, u16_t length, pbuf_type type)
+{
+ 8017528:	b580      	push	{r7, lr}
+ 801752a:	b08c      	sub	sp, #48	; 0x30
+ 801752c:	af02      	add	r7, sp, #8
+ 801752e:	4603      	mov	r3, r0
+ 8017530:	71fb      	strb	r3, [r7, #7]
+ 8017532:	460b      	mov	r3, r1
+ 8017534:	80bb      	strh	r3, [r7, #4]
+ 8017536:	4613      	mov	r3, r2
+ 8017538:	807b      	strh	r3, [r7, #2]
+  struct pbuf *p;
+  u16_t offset = (u16_t)layer;
+ 801753a:	79fb      	ldrb	r3, [r7, #7]
+ 801753c:	847b      	strh	r3, [r7, #34]	; 0x22
+  LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_alloc(length=%"U16_F")\n", length));
+
+  switch (type) {
+ 801753e:	887b      	ldrh	r3, [r7, #2]
+ 8017540:	f5b3 7f20 	cmp.w	r3, #640	; 0x280
+ 8017544:	f000 8082 	beq.w	801764c <pbuf_alloc+0x124>
+ 8017548:	f5b3 7f20 	cmp.w	r3, #640	; 0x280
+ 801754c:	f300 80ca 	bgt.w	80176e4 <pbuf_alloc+0x1bc>
+ 8017550:	f5b3 7fc1 	cmp.w	r3, #386	; 0x182
+ 8017554:	d010      	beq.n	8017578 <pbuf_alloc+0x50>
+ 8017556:	f5b3 7fc1 	cmp.w	r3, #386	; 0x182
+ 801755a:	f300 80c3 	bgt.w	80176e4 <pbuf_alloc+0x1bc>
+ 801755e:	2b01      	cmp	r3, #1
+ 8017560:	d002      	beq.n	8017568 <pbuf_alloc+0x40>
+ 8017562:	2b41      	cmp	r3, #65	; 0x41
+ 8017564:	f040 80be 	bne.w	80176e4 <pbuf_alloc+0x1bc>
+    case PBUF_REF: /* fall through */
+    case PBUF_ROM:
+      p = pbuf_alloc_reference(NULL, length, type);
+ 8017568:	887a      	ldrh	r2, [r7, #2]
+ 801756a:	88bb      	ldrh	r3, [r7, #4]
+ 801756c:	4619      	mov	r1, r3
+ 801756e:	2000      	movs	r0, #0
+ 8017570:	f000 f8d4 	bl	801771c <pbuf_alloc_reference>
+ 8017574:	6278      	str	r0, [r7, #36]	; 0x24
+      break;
+ 8017576:	e0bf      	b.n	80176f8 <pbuf_alloc+0x1d0>
+    case PBUF_POOL: {
+      struct pbuf *q, *last;
+      u16_t rem_len; /* remaining length */
+      p = NULL;
+ 8017578:	2300      	movs	r3, #0
+ 801757a:	627b      	str	r3, [r7, #36]	; 0x24
+      last = NULL;
+ 801757c:	2300      	movs	r3, #0
+ 801757e:	61fb      	str	r3, [r7, #28]
+      rem_len = length;
+ 8017580:	88bb      	ldrh	r3, [r7, #4]
+ 8017582:	837b      	strh	r3, [r7, #26]
+      do {
+        u16_t qlen;
+        q = (struct pbuf *)memp_malloc(MEMP_PBUF_POOL);
+ 8017584:	200c      	movs	r0, #12
+ 8017586:	f7ff faa3 	bl	8016ad0 <memp_malloc>
+ 801758a:	6138      	str	r0, [r7, #16]
+        if (q == NULL) {
+ 801758c:	693b      	ldr	r3, [r7, #16]
+ 801758e:	2b00      	cmp	r3, #0
+ 8017590:	d109      	bne.n	80175a6 <pbuf_alloc+0x7e>
+          PBUF_POOL_IS_EMPTY();
+ 8017592:	f7ff ff75 	bl	8017480 <pbuf_pool_is_empty>
+          /* free chain so far allocated */
+          if (p) {
+ 8017596:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 8017598:	2b00      	cmp	r3, #0
+ 801759a:	d002      	beq.n	80175a2 <pbuf_alloc+0x7a>
+            pbuf_free(p);
+ 801759c:	6a78      	ldr	r0, [r7, #36]	; 0x24
+ 801759e:	f000 faab 	bl	8017af8 <pbuf_free>
+          }
+          /* bail out unsuccessfully */
+          return NULL;
+ 80175a2:	2300      	movs	r3, #0
+ 80175a4:	e0a9      	b.n	80176fa <pbuf_alloc+0x1d2>
+        }
+        qlen = LWIP_MIN(rem_len, (u16_t)(PBUF_POOL_BUFSIZE_ALIGNED - LWIP_MEM_ALIGN_SIZE(offset)));
+ 80175a6:	8c7b      	ldrh	r3, [r7, #34]	; 0x22
+ 80175a8:	3303      	adds	r3, #3
+ 80175aa:	b29b      	uxth	r3, r3
+ 80175ac:	f023 0303 	bic.w	r3, r3, #3
+ 80175b0:	b29a      	uxth	r2, r3
+ 80175b2:	f240 53ec 	movw	r3, #1516	; 0x5ec
+ 80175b6:	1a9b      	subs	r3, r3, r2
+ 80175b8:	b29b      	uxth	r3, r3
+ 80175ba:	8b7a      	ldrh	r2, [r7, #26]
+ 80175bc:	4293      	cmp	r3, r2
+ 80175be:	bf28      	it	cs
+ 80175c0:	4613      	movcs	r3, r2
+ 80175c2:	81fb      	strh	r3, [r7, #14]
+        pbuf_init_alloced_pbuf(q, LWIP_MEM_ALIGN((void *)((u8_t *)q + SIZEOF_STRUCT_PBUF + offset)),
+ 80175c4:	8c7b      	ldrh	r3, [r7, #34]	; 0x22
+ 80175c6:	3310      	adds	r3, #16
+ 80175c8:	693a      	ldr	r2, [r7, #16]
+ 80175ca:	4413      	add	r3, r2
+ 80175cc:	3303      	adds	r3, #3
+ 80175ce:	f023 0303 	bic.w	r3, r3, #3
+ 80175d2:	4618      	mov	r0, r3
+ 80175d4:	89f9      	ldrh	r1, [r7, #14]
+ 80175d6:	8b7a      	ldrh	r2, [r7, #26]
+ 80175d8:	2300      	movs	r3, #0
+ 80175da:	9301      	str	r3, [sp, #4]
+ 80175dc:	887b      	ldrh	r3, [r7, #2]
+ 80175de:	9300      	str	r3, [sp, #0]
+ 80175e0:	460b      	mov	r3, r1
+ 80175e2:	4601      	mov	r1, r0
+ 80175e4:	6938      	ldr	r0, [r7, #16]
+ 80175e6:	f7ff ff75 	bl	80174d4 <pbuf_init_alloced_pbuf>
+                               rem_len, qlen, type, 0);
+        LWIP_ASSERT("pbuf_alloc: pbuf q->payload properly aligned",
+ 80175ea:	693b      	ldr	r3, [r7, #16]
+ 80175ec:	685b      	ldr	r3, [r3, #4]
+ 80175ee:	f003 0303 	and.w	r3, r3, #3
+ 80175f2:	2b00      	cmp	r3, #0
+ 80175f4:	d006      	beq.n	8017604 <pbuf_alloc+0xdc>
+ 80175f6:	4b43      	ldr	r3, [pc, #268]	; (8017704 <pbuf_alloc+0x1dc>)
+ 80175f8:	f44f 7280 	mov.w	r2, #256	; 0x100
+ 80175fc:	4942      	ldr	r1, [pc, #264]	; (8017708 <pbuf_alloc+0x1e0>)
+ 80175fe:	4843      	ldr	r0, [pc, #268]	; (801770c <pbuf_alloc+0x1e4>)
+ 8017600:	f00a f9c2 	bl	8021988 <iprintf>
+                    ((mem_ptr_t)q->payload % MEM_ALIGNMENT) == 0);
+        LWIP_ASSERT("PBUF_POOL_BUFSIZE must be bigger than MEM_ALIGNMENT",
+ 8017604:	8c7b      	ldrh	r3, [r7, #34]	; 0x22
+ 8017606:	3303      	adds	r3, #3
+ 8017608:	f023 0303 	bic.w	r3, r3, #3
+ 801760c:	f240 52ec 	movw	r2, #1516	; 0x5ec
+ 8017610:	4293      	cmp	r3, r2
+ 8017612:	d106      	bne.n	8017622 <pbuf_alloc+0xfa>
+ 8017614:	4b3b      	ldr	r3, [pc, #236]	; (8017704 <pbuf_alloc+0x1dc>)
+ 8017616:	f44f 7281 	mov.w	r2, #258	; 0x102
+ 801761a:	493d      	ldr	r1, [pc, #244]	; (8017710 <pbuf_alloc+0x1e8>)
+ 801761c:	483b      	ldr	r0, [pc, #236]	; (801770c <pbuf_alloc+0x1e4>)
+ 801761e:	f00a f9b3 	bl	8021988 <iprintf>
+                    (PBUF_POOL_BUFSIZE_ALIGNED - LWIP_MEM_ALIGN_SIZE(offset)) > 0 );
+        if (p == NULL) {
+ 8017622:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 8017624:	2b00      	cmp	r3, #0
+ 8017626:	d102      	bne.n	801762e <pbuf_alloc+0x106>
+          /* allocated head of pbuf chain (into p) */
+          p = q;
+ 8017628:	693b      	ldr	r3, [r7, #16]
+ 801762a:	627b      	str	r3, [r7, #36]	; 0x24
+ 801762c:	e002      	b.n	8017634 <pbuf_alloc+0x10c>
+        } else {
+          /* make previous pbuf point to this pbuf */
+          last->next = q;
+ 801762e:	69fb      	ldr	r3, [r7, #28]
+ 8017630:	693a      	ldr	r2, [r7, #16]
+ 8017632:	601a      	str	r2, [r3, #0]
+        }
+        last = q;
+ 8017634:	693b      	ldr	r3, [r7, #16]
+ 8017636:	61fb      	str	r3, [r7, #28]
+        rem_len = (u16_t)(rem_len - qlen);
+ 8017638:	8b7a      	ldrh	r2, [r7, #26]
+ 801763a:	89fb      	ldrh	r3, [r7, #14]
+ 801763c:	1ad3      	subs	r3, r2, r3
+ 801763e:	837b      	strh	r3, [r7, #26]
+        offset = 0;
+ 8017640:	2300      	movs	r3, #0
+ 8017642:	847b      	strh	r3, [r7, #34]	; 0x22
+      } while (rem_len > 0);
+ 8017644:	8b7b      	ldrh	r3, [r7, #26]
+ 8017646:	2b00      	cmp	r3, #0
+ 8017648:	d19c      	bne.n	8017584 <pbuf_alloc+0x5c>
+      break;
+ 801764a:	e055      	b.n	80176f8 <pbuf_alloc+0x1d0>
+    }
+    case PBUF_RAM: {
+      u16_t payload_len = (u16_t)(LWIP_MEM_ALIGN_SIZE(offset) + LWIP_MEM_ALIGN_SIZE(length));
+ 801764c:	8c7b      	ldrh	r3, [r7, #34]	; 0x22
+ 801764e:	3303      	adds	r3, #3
+ 8017650:	b29b      	uxth	r3, r3
+ 8017652:	f023 0303 	bic.w	r3, r3, #3
+ 8017656:	b29a      	uxth	r2, r3
+ 8017658:	88bb      	ldrh	r3, [r7, #4]
+ 801765a:	3303      	adds	r3, #3
+ 801765c:	b29b      	uxth	r3, r3
+ 801765e:	f023 0303 	bic.w	r3, r3, #3
+ 8017662:	b29b      	uxth	r3, r3
+ 8017664:	4413      	add	r3, r2
+ 8017666:	833b      	strh	r3, [r7, #24]
+      mem_size_t alloc_len = (mem_size_t)(LWIP_MEM_ALIGN_SIZE(SIZEOF_STRUCT_PBUF) + payload_len);
+ 8017668:	8b3b      	ldrh	r3, [r7, #24]
+ 801766a:	3310      	adds	r3, #16
+ 801766c:	82fb      	strh	r3, [r7, #22]
+
+      /* bug #50040: Check for integer overflow when calculating alloc_len */
+      if ((payload_len < LWIP_MEM_ALIGN_SIZE(length)) ||
+ 801766e:	8b3a      	ldrh	r2, [r7, #24]
+ 8017670:	88bb      	ldrh	r3, [r7, #4]
+ 8017672:	3303      	adds	r3, #3
+ 8017674:	f023 0303 	bic.w	r3, r3, #3
+ 8017678:	429a      	cmp	r2, r3
+ 801767a:	d306      	bcc.n	801768a <pbuf_alloc+0x162>
+          (alloc_len < LWIP_MEM_ALIGN_SIZE(length))) {
+ 801767c:	8afa      	ldrh	r2, [r7, #22]
+ 801767e:	88bb      	ldrh	r3, [r7, #4]
+ 8017680:	3303      	adds	r3, #3
+ 8017682:	f023 0303 	bic.w	r3, r3, #3
+      if ((payload_len < LWIP_MEM_ALIGN_SIZE(length)) ||
+ 8017686:	429a      	cmp	r2, r3
+ 8017688:	d201      	bcs.n	801768e <pbuf_alloc+0x166>
+        return NULL;
+ 801768a:	2300      	movs	r3, #0
+ 801768c:	e035      	b.n	80176fa <pbuf_alloc+0x1d2>
+      }
+
+      /* If pbuf is to be allocated in RAM, allocate memory for it. */
+      p = (struct pbuf *)mem_malloc(alloc_len);
+ 801768e:	8afb      	ldrh	r3, [r7, #22]
+ 8017690:	4618      	mov	r0, r3
+ 8017692:	f7ff f865 	bl	8016760 <mem_malloc>
+ 8017696:	6278      	str	r0, [r7, #36]	; 0x24
+      if (p == NULL) {
+ 8017698:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 801769a:	2b00      	cmp	r3, #0
+ 801769c:	d101      	bne.n	80176a2 <pbuf_alloc+0x17a>
+        return NULL;
+ 801769e:	2300      	movs	r3, #0
+ 80176a0:	e02b      	b.n	80176fa <pbuf_alloc+0x1d2>
+      }
+      pbuf_init_alloced_pbuf(p, LWIP_MEM_ALIGN((void *)((u8_t *)p + SIZEOF_STRUCT_PBUF + offset)),
+ 80176a2:	8c7b      	ldrh	r3, [r7, #34]	; 0x22
+ 80176a4:	3310      	adds	r3, #16
+ 80176a6:	6a7a      	ldr	r2, [r7, #36]	; 0x24
+ 80176a8:	4413      	add	r3, r2
+ 80176aa:	3303      	adds	r3, #3
+ 80176ac:	f023 0303 	bic.w	r3, r3, #3
+ 80176b0:	4618      	mov	r0, r3
+ 80176b2:	88b9      	ldrh	r1, [r7, #4]
+ 80176b4:	88ba      	ldrh	r2, [r7, #4]
+ 80176b6:	2300      	movs	r3, #0
+ 80176b8:	9301      	str	r3, [sp, #4]
+ 80176ba:	887b      	ldrh	r3, [r7, #2]
+ 80176bc:	9300      	str	r3, [sp, #0]
+ 80176be:	460b      	mov	r3, r1
+ 80176c0:	4601      	mov	r1, r0
+ 80176c2:	6a78      	ldr	r0, [r7, #36]	; 0x24
+ 80176c4:	f7ff ff06 	bl	80174d4 <pbuf_init_alloced_pbuf>
+                             length, length, type, 0);
+      LWIP_ASSERT("pbuf_alloc: pbuf->payload properly aligned",
+ 80176c8:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 80176ca:	685b      	ldr	r3, [r3, #4]
+ 80176cc:	f003 0303 	and.w	r3, r3, #3
+ 80176d0:	2b00      	cmp	r3, #0
+ 80176d2:	d010      	beq.n	80176f6 <pbuf_alloc+0x1ce>
+ 80176d4:	4b0b      	ldr	r3, [pc, #44]	; (8017704 <pbuf_alloc+0x1dc>)
+ 80176d6:	f44f 7291 	mov.w	r2, #290	; 0x122
+ 80176da:	490e      	ldr	r1, [pc, #56]	; (8017714 <pbuf_alloc+0x1ec>)
+ 80176dc:	480b      	ldr	r0, [pc, #44]	; (801770c <pbuf_alloc+0x1e4>)
+ 80176de:	f00a f953 	bl	8021988 <iprintf>
+                  ((mem_ptr_t)p->payload % MEM_ALIGNMENT) == 0);
+      break;
+ 80176e2:	e008      	b.n	80176f6 <pbuf_alloc+0x1ce>
+    }
+    default:
+      LWIP_ASSERT("pbuf_alloc: erroneous type", 0);
+ 80176e4:	4b07      	ldr	r3, [pc, #28]	; (8017704 <pbuf_alloc+0x1dc>)
+ 80176e6:	f240 1227 	movw	r2, #295	; 0x127
+ 80176ea:	490b      	ldr	r1, [pc, #44]	; (8017718 <pbuf_alloc+0x1f0>)
+ 80176ec:	4807      	ldr	r0, [pc, #28]	; (801770c <pbuf_alloc+0x1e4>)
+ 80176ee:	f00a f94b 	bl	8021988 <iprintf>
+      return NULL;
+ 80176f2:	2300      	movs	r3, #0
+ 80176f4:	e001      	b.n	80176fa <pbuf_alloc+0x1d2>
+      break;
+ 80176f6:	bf00      	nop
+  }
+  LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_alloc(length=%"U16_F") == %p\n", length, (void *)p));
+  return p;
+ 80176f8:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+}
+ 80176fa:	4618      	mov	r0, r3
+ 80176fc:	3728      	adds	r7, #40	; 0x28
+ 80176fe:	46bd      	mov	sp, r7
+ 8017700:	bd80      	pop	{r7, pc}
+ 8017702:	bf00      	nop
+ 8017704:	080246a8 	.word	0x080246a8
+ 8017708:	080246d8 	.word	0x080246d8
+ 801770c:	08024708 	.word	0x08024708
+ 8017710:	08024730 	.word	0x08024730
+ 8017714:	08024764 	.word	0x08024764
+ 8017718:	08024790 	.word	0x08024790
+
+0801771c <pbuf_alloc_reference>:
+ *
+ * @return the allocated pbuf.
+ */
+struct pbuf *
+pbuf_alloc_reference(void *payload, u16_t length, pbuf_type type)
+{
+ 801771c:	b580      	push	{r7, lr}
+ 801771e:	b086      	sub	sp, #24
+ 8017720:	af02      	add	r7, sp, #8
+ 8017722:	6078      	str	r0, [r7, #4]
+ 8017724:	460b      	mov	r3, r1
+ 8017726:	807b      	strh	r3, [r7, #2]
+ 8017728:	4613      	mov	r3, r2
+ 801772a:	803b      	strh	r3, [r7, #0]
+  struct pbuf *p;
+  LWIP_ASSERT("invalid pbuf_type", (type == PBUF_REF) || (type == PBUF_ROM));
+ 801772c:	883b      	ldrh	r3, [r7, #0]
+ 801772e:	2b41      	cmp	r3, #65	; 0x41
+ 8017730:	d009      	beq.n	8017746 <pbuf_alloc_reference+0x2a>
+ 8017732:	883b      	ldrh	r3, [r7, #0]
+ 8017734:	2b01      	cmp	r3, #1
+ 8017736:	d006      	beq.n	8017746 <pbuf_alloc_reference+0x2a>
+ 8017738:	4b0f      	ldr	r3, [pc, #60]	; (8017778 <pbuf_alloc_reference+0x5c>)
+ 801773a:	f44f 72a5 	mov.w	r2, #330	; 0x14a
+ 801773e:	490f      	ldr	r1, [pc, #60]	; (801777c <pbuf_alloc_reference+0x60>)
+ 8017740:	480f      	ldr	r0, [pc, #60]	; (8017780 <pbuf_alloc_reference+0x64>)
+ 8017742:	f00a f921 	bl	8021988 <iprintf>
+  /* only allocate memory for the pbuf structure */
+  p = (struct pbuf *)memp_malloc(MEMP_PBUF);
+ 8017746:	200b      	movs	r0, #11
+ 8017748:	f7ff f9c2 	bl	8016ad0 <memp_malloc>
+ 801774c:	60f8      	str	r0, [r7, #12]
+  if (p == NULL) {
+ 801774e:	68fb      	ldr	r3, [r7, #12]
+ 8017750:	2b00      	cmp	r3, #0
+ 8017752:	d101      	bne.n	8017758 <pbuf_alloc_reference+0x3c>
+    LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_LEVEL_SERIOUS,
+                ("pbuf_alloc_reference: Could not allocate MEMP_PBUF for PBUF_%s.\n",
+                 (type == PBUF_ROM) ? "ROM" : "REF"));
+    return NULL;
+ 8017754:	2300      	movs	r3, #0
+ 8017756:	e00b      	b.n	8017770 <pbuf_alloc_reference+0x54>
+  }
+  pbuf_init_alloced_pbuf(p, payload, length, length, type, 0);
+ 8017758:	8879      	ldrh	r1, [r7, #2]
+ 801775a:	887a      	ldrh	r2, [r7, #2]
+ 801775c:	2300      	movs	r3, #0
+ 801775e:	9301      	str	r3, [sp, #4]
+ 8017760:	883b      	ldrh	r3, [r7, #0]
+ 8017762:	9300      	str	r3, [sp, #0]
+ 8017764:	460b      	mov	r3, r1
+ 8017766:	6879      	ldr	r1, [r7, #4]
+ 8017768:	68f8      	ldr	r0, [r7, #12]
+ 801776a:	f7ff feb3 	bl	80174d4 <pbuf_init_alloced_pbuf>
+  return p;
+ 801776e:	68fb      	ldr	r3, [r7, #12]
+}
+ 8017770:	4618      	mov	r0, r3
+ 8017772:	3710      	adds	r7, #16
+ 8017774:	46bd      	mov	sp, r7
+ 8017776:	bd80      	pop	{r7, pc}
+ 8017778:	080246a8 	.word	0x080246a8
+ 801777c:	080247ac 	.word	0x080247ac
+ 8017780:	08024708 	.word	0x08024708
+
+08017784 <pbuf_alloced_custom>:
+ *        big enough to hold 'length' plus the header size
+ */
+struct pbuf *
+pbuf_alloced_custom(pbuf_layer l, u16_t length, pbuf_type type, struct pbuf_custom *p,
+                    void *payload_mem, u16_t payload_mem_len)
+{
+ 8017784:	b580      	push	{r7, lr}
+ 8017786:	b088      	sub	sp, #32
+ 8017788:	af02      	add	r7, sp, #8
+ 801778a:	607b      	str	r3, [r7, #4]
+ 801778c:	4603      	mov	r3, r0
+ 801778e:	73fb      	strb	r3, [r7, #15]
+ 8017790:	460b      	mov	r3, r1
+ 8017792:	81bb      	strh	r3, [r7, #12]
+ 8017794:	4613      	mov	r3, r2
+ 8017796:	817b      	strh	r3, [r7, #10]
+  u16_t offset = (u16_t)l;
+ 8017798:	7bfb      	ldrb	r3, [r7, #15]
+ 801779a:	827b      	strh	r3, [r7, #18]
+  void *payload;
+  LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_alloced_custom(length=%"U16_F")\n", length));
+
+  if (LWIP_MEM_ALIGN_SIZE(offset) + length > payload_mem_len) {
+ 801779c:	8a7b      	ldrh	r3, [r7, #18]
+ 801779e:	3303      	adds	r3, #3
+ 80177a0:	f023 0203 	bic.w	r2, r3, #3
+ 80177a4:	89bb      	ldrh	r3, [r7, #12]
+ 80177a6:	441a      	add	r2, r3
+ 80177a8:	8cbb      	ldrh	r3, [r7, #36]	; 0x24
+ 80177aa:	429a      	cmp	r2, r3
+ 80177ac:	d901      	bls.n	80177b2 <pbuf_alloced_custom+0x2e>
+    LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_LEVEL_WARNING, ("pbuf_alloced_custom(length=%"U16_F") buffer too short\n", length));
+    return NULL;
+ 80177ae:	2300      	movs	r3, #0
+ 80177b0:	e018      	b.n	80177e4 <pbuf_alloced_custom+0x60>
+  }
+
+  if (payload_mem != NULL) {
+ 80177b2:	6a3b      	ldr	r3, [r7, #32]
+ 80177b4:	2b00      	cmp	r3, #0
+ 80177b6:	d007      	beq.n	80177c8 <pbuf_alloced_custom+0x44>
+    payload = (u8_t *)payload_mem + LWIP_MEM_ALIGN_SIZE(offset);
+ 80177b8:	8a7b      	ldrh	r3, [r7, #18]
+ 80177ba:	3303      	adds	r3, #3
+ 80177bc:	f023 0303 	bic.w	r3, r3, #3
+ 80177c0:	6a3a      	ldr	r2, [r7, #32]
+ 80177c2:	4413      	add	r3, r2
+ 80177c4:	617b      	str	r3, [r7, #20]
+ 80177c6:	e001      	b.n	80177cc <pbuf_alloced_custom+0x48>
+  } else {
+    payload = NULL;
+ 80177c8:	2300      	movs	r3, #0
+ 80177ca:	617b      	str	r3, [r7, #20]
+  }
+  pbuf_init_alloced_pbuf(&p->pbuf, payload, length, length, type, PBUF_FLAG_IS_CUSTOM);
+ 80177cc:	6878      	ldr	r0, [r7, #4]
+ 80177ce:	89b9      	ldrh	r1, [r7, #12]
+ 80177d0:	89ba      	ldrh	r2, [r7, #12]
+ 80177d2:	2302      	movs	r3, #2
+ 80177d4:	9301      	str	r3, [sp, #4]
+ 80177d6:	897b      	ldrh	r3, [r7, #10]
+ 80177d8:	9300      	str	r3, [sp, #0]
+ 80177da:	460b      	mov	r3, r1
+ 80177dc:	6979      	ldr	r1, [r7, #20]
+ 80177de:	f7ff fe79 	bl	80174d4 <pbuf_init_alloced_pbuf>
+  return &p->pbuf;
+ 80177e2:	687b      	ldr	r3, [r7, #4]
+}
+ 80177e4:	4618      	mov	r0, r3
+ 80177e6:	3718      	adds	r7, #24
+ 80177e8:	46bd      	mov	sp, r7
+ 80177ea:	bd80      	pop	{r7, pc}
+
+080177ec <pbuf_realloc>:
+ *
+ * @note Despite its name, pbuf_realloc cannot grow the size of a pbuf (chain).
+ */
+void
+pbuf_realloc(struct pbuf *p, u16_t new_len)
+{
+ 80177ec:	b580      	push	{r7, lr}
+ 80177ee:	b084      	sub	sp, #16
+ 80177f0:	af00      	add	r7, sp, #0
+ 80177f2:	6078      	str	r0, [r7, #4]
+ 80177f4:	460b      	mov	r3, r1
+ 80177f6:	807b      	strh	r3, [r7, #2]
+  struct pbuf *q;
+  u16_t rem_len; /* remaining length */
+  u16_t shrink;
+
+  LWIP_ASSERT("pbuf_realloc: p != NULL", p != NULL);
+ 80177f8:	687b      	ldr	r3, [r7, #4]
+ 80177fa:	2b00      	cmp	r3, #0
+ 80177fc:	d106      	bne.n	801780c <pbuf_realloc+0x20>
+ 80177fe:	4b3a      	ldr	r3, [pc, #232]	; (80178e8 <pbuf_realloc+0xfc>)
+ 8017800:	f44f 72cc 	mov.w	r2, #408	; 0x198
+ 8017804:	4939      	ldr	r1, [pc, #228]	; (80178ec <pbuf_realloc+0x100>)
+ 8017806:	483a      	ldr	r0, [pc, #232]	; (80178f0 <pbuf_realloc+0x104>)
+ 8017808:	f00a f8be 	bl	8021988 <iprintf>
+
+  /* desired length larger than current length? */
+  if (new_len >= p->tot_len) {
+ 801780c:	687b      	ldr	r3, [r7, #4]
+ 801780e:	891b      	ldrh	r3, [r3, #8]
+ 8017810:	887a      	ldrh	r2, [r7, #2]
+ 8017812:	429a      	cmp	r2, r3
+ 8017814:	d263      	bcs.n	80178de <pbuf_realloc+0xf2>
+    return;
+  }
+
+  /* the pbuf chain grows by (new_len - p->tot_len) bytes
+   * (which may be negative in case of shrinking) */
+  shrink = (u16_t)(p->tot_len - new_len);
+ 8017816:	687b      	ldr	r3, [r7, #4]
+ 8017818:	891a      	ldrh	r2, [r3, #8]
+ 801781a:	887b      	ldrh	r3, [r7, #2]
+ 801781c:	1ad3      	subs	r3, r2, r3
+ 801781e:	813b      	strh	r3, [r7, #8]
+
+  /* first, step over any pbufs that should remain in the chain */
+  rem_len = new_len;
+ 8017820:	887b      	ldrh	r3, [r7, #2]
+ 8017822:	817b      	strh	r3, [r7, #10]
+  q = p;
+ 8017824:	687b      	ldr	r3, [r7, #4]
+ 8017826:	60fb      	str	r3, [r7, #12]
+  /* should this pbuf be kept? */
+  while (rem_len > q->len) {
+ 8017828:	e018      	b.n	801785c <pbuf_realloc+0x70>
+    /* decrease remaining length by pbuf length */
+    rem_len = (u16_t)(rem_len - q->len);
+ 801782a:	68fb      	ldr	r3, [r7, #12]
+ 801782c:	895b      	ldrh	r3, [r3, #10]
+ 801782e:	897a      	ldrh	r2, [r7, #10]
+ 8017830:	1ad3      	subs	r3, r2, r3
+ 8017832:	817b      	strh	r3, [r7, #10]
+    /* decrease total length indicator */
+    q->tot_len = (u16_t)(q->tot_len - shrink);
+ 8017834:	68fb      	ldr	r3, [r7, #12]
+ 8017836:	891a      	ldrh	r2, [r3, #8]
+ 8017838:	893b      	ldrh	r3, [r7, #8]
+ 801783a:	1ad3      	subs	r3, r2, r3
+ 801783c:	b29a      	uxth	r2, r3
+ 801783e:	68fb      	ldr	r3, [r7, #12]
+ 8017840:	811a      	strh	r2, [r3, #8]
+    /* proceed to next pbuf in chain */
+    q = q->next;
+ 8017842:	68fb      	ldr	r3, [r7, #12]
+ 8017844:	681b      	ldr	r3, [r3, #0]
+ 8017846:	60fb      	str	r3, [r7, #12]
+    LWIP_ASSERT("pbuf_realloc: q != NULL", q != NULL);
+ 8017848:	68fb      	ldr	r3, [r7, #12]
+ 801784a:	2b00      	cmp	r3, #0
+ 801784c:	d106      	bne.n	801785c <pbuf_realloc+0x70>
+ 801784e:	4b26      	ldr	r3, [pc, #152]	; (80178e8 <pbuf_realloc+0xfc>)
+ 8017850:	f240 12af 	movw	r2, #431	; 0x1af
+ 8017854:	4927      	ldr	r1, [pc, #156]	; (80178f4 <pbuf_realloc+0x108>)
+ 8017856:	4826      	ldr	r0, [pc, #152]	; (80178f0 <pbuf_realloc+0x104>)
+ 8017858:	f00a f896 	bl	8021988 <iprintf>
+  while (rem_len > q->len) {
+ 801785c:	68fb      	ldr	r3, [r7, #12]
+ 801785e:	895b      	ldrh	r3, [r3, #10]
+ 8017860:	897a      	ldrh	r2, [r7, #10]
+ 8017862:	429a      	cmp	r2, r3
+ 8017864:	d8e1      	bhi.n	801782a <pbuf_realloc+0x3e>
+  /* we have now reached the new last pbuf (in q) */
+  /* rem_len == desired length for pbuf q */
+
+  /* shrink allocated memory for PBUF_RAM */
+  /* (other types merely adjust their length fields */
+  if (pbuf_match_allocsrc(q, PBUF_TYPE_ALLOC_SRC_MASK_STD_HEAP) && (rem_len != q->len)
+ 8017866:	68fb      	ldr	r3, [r7, #12]
+ 8017868:	7b1b      	ldrb	r3, [r3, #12]
+ 801786a:	f003 030f 	and.w	r3, r3, #15
+ 801786e:	2b00      	cmp	r3, #0
+ 8017870:	d121      	bne.n	80178b6 <pbuf_realloc+0xca>
+ 8017872:	68fb      	ldr	r3, [r7, #12]
+ 8017874:	895b      	ldrh	r3, [r3, #10]
+ 8017876:	897a      	ldrh	r2, [r7, #10]
+ 8017878:	429a      	cmp	r2, r3
+ 801787a:	d01c      	beq.n	80178b6 <pbuf_realloc+0xca>
+#if LWIP_SUPPORT_CUSTOM_PBUF
+      && ((q->flags & PBUF_FLAG_IS_CUSTOM) == 0)
+ 801787c:	68fb      	ldr	r3, [r7, #12]
+ 801787e:	7b5b      	ldrb	r3, [r3, #13]
+ 8017880:	f003 0302 	and.w	r3, r3, #2
+ 8017884:	2b00      	cmp	r3, #0
+ 8017886:	d116      	bne.n	80178b6 <pbuf_realloc+0xca>
+#endif /* LWIP_SUPPORT_CUSTOM_PBUF */
+     ) {
+    /* reallocate and adjust the length of the pbuf that will be split */
+    q = (struct pbuf *)mem_trim(q, (mem_size_t)(((u8_t *)q->payload - (u8_t *)q) + rem_len));
+ 8017888:	68fb      	ldr	r3, [r7, #12]
+ 801788a:	685a      	ldr	r2, [r3, #4]
+ 801788c:	68fb      	ldr	r3, [r7, #12]
+ 801788e:	1ad3      	subs	r3, r2, r3
+ 8017890:	b29a      	uxth	r2, r3
+ 8017892:	897b      	ldrh	r3, [r7, #10]
+ 8017894:	4413      	add	r3, r2
+ 8017896:	b29b      	uxth	r3, r3
+ 8017898:	4619      	mov	r1, r3
+ 801789a:	68f8      	ldr	r0, [r7, #12]
+ 801789c:	f7fe fe4c 	bl	8016538 <mem_trim>
+ 80178a0:	60f8      	str	r0, [r7, #12]
+    LWIP_ASSERT("mem_trim returned q == NULL", q != NULL);
+ 80178a2:	68fb      	ldr	r3, [r7, #12]
+ 80178a4:	2b00      	cmp	r3, #0
+ 80178a6:	d106      	bne.n	80178b6 <pbuf_realloc+0xca>
+ 80178a8:	4b0f      	ldr	r3, [pc, #60]	; (80178e8 <pbuf_realloc+0xfc>)
+ 80178aa:	f240 12bd 	movw	r2, #445	; 0x1bd
+ 80178ae:	4912      	ldr	r1, [pc, #72]	; (80178f8 <pbuf_realloc+0x10c>)
+ 80178b0:	480f      	ldr	r0, [pc, #60]	; (80178f0 <pbuf_realloc+0x104>)
+ 80178b2:	f00a f869 	bl	8021988 <iprintf>
+  }
+  /* adjust length fields for new last pbuf */
+  q->len = rem_len;
+ 80178b6:	68fb      	ldr	r3, [r7, #12]
+ 80178b8:	897a      	ldrh	r2, [r7, #10]
+ 80178ba:	815a      	strh	r2, [r3, #10]
+  q->tot_len = q->len;
+ 80178bc:	68fb      	ldr	r3, [r7, #12]
+ 80178be:	895a      	ldrh	r2, [r3, #10]
+ 80178c0:	68fb      	ldr	r3, [r7, #12]
+ 80178c2:	811a      	strh	r2, [r3, #8]
+
+  /* any remaining pbufs in chain? */
+  if (q->next != NULL) {
+ 80178c4:	68fb      	ldr	r3, [r7, #12]
+ 80178c6:	681b      	ldr	r3, [r3, #0]
+ 80178c8:	2b00      	cmp	r3, #0
+ 80178ca:	d004      	beq.n	80178d6 <pbuf_realloc+0xea>
+    /* free remaining pbufs in chain */
+    pbuf_free(q->next);
+ 80178cc:	68fb      	ldr	r3, [r7, #12]
+ 80178ce:	681b      	ldr	r3, [r3, #0]
+ 80178d0:	4618      	mov	r0, r3
+ 80178d2:	f000 f911 	bl	8017af8 <pbuf_free>
+  }
+  /* q is last packet in chain */
+  q->next = NULL;
+ 80178d6:	68fb      	ldr	r3, [r7, #12]
+ 80178d8:	2200      	movs	r2, #0
+ 80178da:	601a      	str	r2, [r3, #0]
+ 80178dc:	e000      	b.n	80178e0 <pbuf_realloc+0xf4>
+    return;
+ 80178de:	bf00      	nop
+
+}
+ 80178e0:	3710      	adds	r7, #16
+ 80178e2:	46bd      	mov	sp, r7
+ 80178e4:	bd80      	pop	{r7, pc}
+ 80178e6:	bf00      	nop
+ 80178e8:	080246a8 	.word	0x080246a8
+ 80178ec:	080247c0 	.word	0x080247c0
+ 80178f0:	08024708 	.word	0x08024708
+ 80178f4:	080247d8 	.word	0x080247d8
+ 80178f8:	080247f0 	.word	0x080247f0
+
+080178fc <pbuf_add_header_impl>:
+ * @return non-zero on failure, zero on success.
+ *
+ */
+static u8_t
+pbuf_add_header_impl(struct pbuf *p, size_t header_size_increment, u8_t force)
+{
+ 80178fc:	b580      	push	{r7, lr}
+ 80178fe:	b086      	sub	sp, #24
+ 8017900:	af00      	add	r7, sp, #0
+ 8017902:	60f8      	str	r0, [r7, #12]
+ 8017904:	60b9      	str	r1, [r7, #8]
+ 8017906:	4613      	mov	r3, r2
+ 8017908:	71fb      	strb	r3, [r7, #7]
+  u16_t type_internal;
+  void *payload;
+  u16_t increment_magnitude;
+
+  LWIP_ASSERT("p != NULL", p != NULL);
+ 801790a:	68fb      	ldr	r3, [r7, #12]
+ 801790c:	2b00      	cmp	r3, #0
+ 801790e:	d106      	bne.n	801791e <pbuf_add_header_impl+0x22>
+ 8017910:	4b2b      	ldr	r3, [pc, #172]	; (80179c0 <pbuf_add_header_impl+0xc4>)
+ 8017912:	f240 12df 	movw	r2, #479	; 0x1df
+ 8017916:	492b      	ldr	r1, [pc, #172]	; (80179c4 <pbuf_add_header_impl+0xc8>)
+ 8017918:	482b      	ldr	r0, [pc, #172]	; (80179c8 <pbuf_add_header_impl+0xcc>)
+ 801791a:	f00a f835 	bl	8021988 <iprintf>
+  if ((p == NULL) || (header_size_increment > 0xFFFF)) {
+ 801791e:	68fb      	ldr	r3, [r7, #12]
+ 8017920:	2b00      	cmp	r3, #0
+ 8017922:	d003      	beq.n	801792c <pbuf_add_header_impl+0x30>
+ 8017924:	68bb      	ldr	r3, [r7, #8]
+ 8017926:	f5b3 3f80 	cmp.w	r3, #65536	; 0x10000
+ 801792a:	d301      	bcc.n	8017930 <pbuf_add_header_impl+0x34>
+    return 1;
+ 801792c:	2301      	movs	r3, #1
+ 801792e:	e043      	b.n	80179b8 <pbuf_add_header_impl+0xbc>
+  }
+  if (header_size_increment == 0) {
+ 8017930:	68bb      	ldr	r3, [r7, #8]
+ 8017932:	2b00      	cmp	r3, #0
+ 8017934:	d101      	bne.n	801793a <pbuf_add_header_impl+0x3e>
+    return 0;
+ 8017936:	2300      	movs	r3, #0
+ 8017938:	e03e      	b.n	80179b8 <pbuf_add_header_impl+0xbc>
+  }
+
+  increment_magnitude = (u16_t)header_size_increment;
+ 801793a:	68bb      	ldr	r3, [r7, #8]
+ 801793c:	827b      	strh	r3, [r7, #18]
+  /* Do not allow tot_len to wrap as a result. */
+  if ((u16_t)(increment_magnitude + p->tot_len) < increment_magnitude) {
+ 801793e:	68fb      	ldr	r3, [r7, #12]
+ 8017940:	891a      	ldrh	r2, [r3, #8]
+ 8017942:	8a7b      	ldrh	r3, [r7, #18]
+ 8017944:	4413      	add	r3, r2
+ 8017946:	b29b      	uxth	r3, r3
+ 8017948:	8a7a      	ldrh	r2, [r7, #18]
+ 801794a:	429a      	cmp	r2, r3
+ 801794c:	d901      	bls.n	8017952 <pbuf_add_header_impl+0x56>
+    return 1;
+ 801794e:	2301      	movs	r3, #1
+ 8017950:	e032      	b.n	80179b8 <pbuf_add_header_impl+0xbc>
+  }
+
+  type_internal = p->type_internal;
+ 8017952:	68fb      	ldr	r3, [r7, #12]
+ 8017954:	7b1b      	ldrb	r3, [r3, #12]
+ 8017956:	823b      	strh	r3, [r7, #16]
+
+  /* pbuf types containing payloads? */
+  if (type_internal & PBUF_TYPE_FLAG_STRUCT_DATA_CONTIGUOUS) {
+ 8017958:	8a3b      	ldrh	r3, [r7, #16]
+ 801795a:	f003 0380 	and.w	r3, r3, #128	; 0x80
+ 801795e:	2b00      	cmp	r3, #0
+ 8017960:	d00c      	beq.n	801797c <pbuf_add_header_impl+0x80>
+    /* set new payload pointer */
+    payload = (u8_t *)p->payload - header_size_increment;
+ 8017962:	68fb      	ldr	r3, [r7, #12]
+ 8017964:	685a      	ldr	r2, [r3, #4]
+ 8017966:	68bb      	ldr	r3, [r7, #8]
+ 8017968:	425b      	negs	r3, r3
+ 801796a:	4413      	add	r3, r2
+ 801796c:	617b      	str	r3, [r7, #20]
+    /* boundary check fails? */
+    if ((u8_t *)payload < (u8_t *)p + SIZEOF_STRUCT_PBUF) {
+ 801796e:	68fb      	ldr	r3, [r7, #12]
+ 8017970:	3310      	adds	r3, #16
+ 8017972:	697a      	ldr	r2, [r7, #20]
+ 8017974:	429a      	cmp	r2, r3
+ 8017976:	d20d      	bcs.n	8017994 <pbuf_add_header_impl+0x98>
+      LWIP_DEBUGF( PBUF_DEBUG | LWIP_DBG_TRACE,
+                   ("pbuf_add_header: failed as %p < %p (not enough space for new header size)\n",
+                    (void *)payload, (void *)((u8_t *)p + SIZEOF_STRUCT_PBUF)));
+      /* bail out unsuccessfully */
+      return 1;
+ 8017978:	2301      	movs	r3, #1
+ 801797a:	e01d      	b.n	80179b8 <pbuf_add_header_impl+0xbc>
+    }
+    /* pbuf types referring to external payloads? */
+  } else {
+    /* hide a header in the payload? */
+    if (force) {
+ 801797c:	79fb      	ldrb	r3, [r7, #7]
+ 801797e:	2b00      	cmp	r3, #0
+ 8017980:	d006      	beq.n	8017990 <pbuf_add_header_impl+0x94>
+      payload = (u8_t *)p->payload - header_size_increment;
+ 8017982:	68fb      	ldr	r3, [r7, #12]
+ 8017984:	685a      	ldr	r2, [r3, #4]
+ 8017986:	68bb      	ldr	r3, [r7, #8]
+ 8017988:	425b      	negs	r3, r3
+ 801798a:	4413      	add	r3, r2
+ 801798c:	617b      	str	r3, [r7, #20]
+ 801798e:	e001      	b.n	8017994 <pbuf_add_header_impl+0x98>
+    } else {
+      /* cannot expand payload to front (yet!)
+       * bail out unsuccessfully */
+      return 1;
+ 8017990:	2301      	movs	r3, #1
+ 8017992:	e011      	b.n	80179b8 <pbuf_add_header_impl+0xbc>
+  }
+  LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_add_header: old %p new %p (%"U16_F")\n",
+              (void *)p->payload, (void *)payload, increment_magnitude));
+
+  /* modify pbuf fields */
+  p->payload = payload;
+ 8017994:	68fb      	ldr	r3, [r7, #12]
+ 8017996:	697a      	ldr	r2, [r7, #20]
+ 8017998:	605a      	str	r2, [r3, #4]
+  p->len = (u16_t)(p->len + increment_magnitude);
+ 801799a:	68fb      	ldr	r3, [r7, #12]
+ 801799c:	895a      	ldrh	r2, [r3, #10]
+ 801799e:	8a7b      	ldrh	r3, [r7, #18]
+ 80179a0:	4413      	add	r3, r2
+ 80179a2:	b29a      	uxth	r2, r3
+ 80179a4:	68fb      	ldr	r3, [r7, #12]
+ 80179a6:	815a      	strh	r2, [r3, #10]
+  p->tot_len = (u16_t)(p->tot_len + increment_magnitude);
+ 80179a8:	68fb      	ldr	r3, [r7, #12]
+ 80179aa:	891a      	ldrh	r2, [r3, #8]
+ 80179ac:	8a7b      	ldrh	r3, [r7, #18]
+ 80179ae:	4413      	add	r3, r2
+ 80179b0:	b29a      	uxth	r2, r3
+ 80179b2:	68fb      	ldr	r3, [r7, #12]
+ 80179b4:	811a      	strh	r2, [r3, #8]
+
+
+  return 0;
+ 80179b6:	2300      	movs	r3, #0
+}
+ 80179b8:	4618      	mov	r0, r3
+ 80179ba:	3718      	adds	r7, #24
+ 80179bc:	46bd      	mov	sp, r7
+ 80179be:	bd80      	pop	{r7, pc}
+ 80179c0:	080246a8 	.word	0x080246a8
+ 80179c4:	0802480c 	.word	0x0802480c
+ 80179c8:	08024708 	.word	0x08024708
+
+080179cc <pbuf_add_header>:
+ * @return non-zero on failure, zero on success.
+ *
+ */
+u8_t
+pbuf_add_header(struct pbuf *p, size_t header_size_increment)
+{
+ 80179cc:	b580      	push	{r7, lr}
+ 80179ce:	b082      	sub	sp, #8
+ 80179d0:	af00      	add	r7, sp, #0
+ 80179d2:	6078      	str	r0, [r7, #4]
+ 80179d4:	6039      	str	r1, [r7, #0]
+  return pbuf_add_header_impl(p, header_size_increment, 0);
+ 80179d6:	2200      	movs	r2, #0
+ 80179d8:	6839      	ldr	r1, [r7, #0]
+ 80179da:	6878      	ldr	r0, [r7, #4]
+ 80179dc:	f7ff ff8e 	bl	80178fc <pbuf_add_header_impl>
+ 80179e0:	4603      	mov	r3, r0
+}
+ 80179e2:	4618      	mov	r0, r3
+ 80179e4:	3708      	adds	r7, #8
+ 80179e6:	46bd      	mov	sp, r7
+ 80179e8:	bd80      	pop	{r7, pc}
+	...
+
+080179ec <pbuf_remove_header>:
+ * @return non-zero on failure, zero on success.
+ *
+ */
+u8_t
+pbuf_remove_header(struct pbuf *p, size_t header_size_decrement)
+{
+ 80179ec:	b580      	push	{r7, lr}
+ 80179ee:	b084      	sub	sp, #16
+ 80179f0:	af00      	add	r7, sp, #0
+ 80179f2:	6078      	str	r0, [r7, #4]
+ 80179f4:	6039      	str	r1, [r7, #0]
+  void *payload;
+  u16_t increment_magnitude;
+
+  LWIP_ASSERT("p != NULL", p != NULL);
+ 80179f6:	687b      	ldr	r3, [r7, #4]
+ 80179f8:	2b00      	cmp	r3, #0
+ 80179fa:	d106      	bne.n	8017a0a <pbuf_remove_header+0x1e>
+ 80179fc:	4b20      	ldr	r3, [pc, #128]	; (8017a80 <pbuf_remove_header+0x94>)
+ 80179fe:	f240 224b 	movw	r2, #587	; 0x24b
+ 8017a02:	4920      	ldr	r1, [pc, #128]	; (8017a84 <pbuf_remove_header+0x98>)
+ 8017a04:	4820      	ldr	r0, [pc, #128]	; (8017a88 <pbuf_remove_header+0x9c>)
+ 8017a06:	f009 ffbf 	bl	8021988 <iprintf>
+  if ((p == NULL) || (header_size_decrement > 0xFFFF)) {
+ 8017a0a:	687b      	ldr	r3, [r7, #4]
+ 8017a0c:	2b00      	cmp	r3, #0
+ 8017a0e:	d003      	beq.n	8017a18 <pbuf_remove_header+0x2c>
+ 8017a10:	683b      	ldr	r3, [r7, #0]
+ 8017a12:	f5b3 3f80 	cmp.w	r3, #65536	; 0x10000
+ 8017a16:	d301      	bcc.n	8017a1c <pbuf_remove_header+0x30>
+    return 1;
+ 8017a18:	2301      	movs	r3, #1
+ 8017a1a:	e02c      	b.n	8017a76 <pbuf_remove_header+0x8a>
+  }
+  if (header_size_decrement == 0) {
+ 8017a1c:	683b      	ldr	r3, [r7, #0]
+ 8017a1e:	2b00      	cmp	r3, #0
+ 8017a20:	d101      	bne.n	8017a26 <pbuf_remove_header+0x3a>
+    return 0;
+ 8017a22:	2300      	movs	r3, #0
+ 8017a24:	e027      	b.n	8017a76 <pbuf_remove_header+0x8a>
+  }
+
+  increment_magnitude = (u16_t)header_size_decrement;
+ 8017a26:	683b      	ldr	r3, [r7, #0]
+ 8017a28:	81fb      	strh	r3, [r7, #14]
+  /* Check that we aren't going to move off the end of the pbuf */
+  LWIP_ERROR("increment_magnitude <= p->len", (increment_magnitude <= p->len), return 1;);
+ 8017a2a:	687b      	ldr	r3, [r7, #4]
+ 8017a2c:	895b      	ldrh	r3, [r3, #10]
+ 8017a2e:	89fa      	ldrh	r2, [r7, #14]
+ 8017a30:	429a      	cmp	r2, r3
+ 8017a32:	d908      	bls.n	8017a46 <pbuf_remove_header+0x5a>
+ 8017a34:	4b12      	ldr	r3, [pc, #72]	; (8017a80 <pbuf_remove_header+0x94>)
+ 8017a36:	f240 2255 	movw	r2, #597	; 0x255
+ 8017a3a:	4914      	ldr	r1, [pc, #80]	; (8017a8c <pbuf_remove_header+0xa0>)
+ 8017a3c:	4812      	ldr	r0, [pc, #72]	; (8017a88 <pbuf_remove_header+0x9c>)
+ 8017a3e:	f009 ffa3 	bl	8021988 <iprintf>
+ 8017a42:	2301      	movs	r3, #1
+ 8017a44:	e017      	b.n	8017a76 <pbuf_remove_header+0x8a>
+
+  /* remember current payload pointer */
+  payload = p->payload;
+ 8017a46:	687b      	ldr	r3, [r7, #4]
+ 8017a48:	685b      	ldr	r3, [r3, #4]
+ 8017a4a:	60bb      	str	r3, [r7, #8]
+  LWIP_UNUSED_ARG(payload); /* only used in LWIP_DEBUGF below */
+
+  /* increase payload pointer (guarded by length check above) */
+  p->payload = (u8_t *)p->payload + header_size_decrement;
+ 8017a4c:	687b      	ldr	r3, [r7, #4]
+ 8017a4e:	685a      	ldr	r2, [r3, #4]
+ 8017a50:	683b      	ldr	r3, [r7, #0]
+ 8017a52:	441a      	add	r2, r3
+ 8017a54:	687b      	ldr	r3, [r7, #4]
+ 8017a56:	605a      	str	r2, [r3, #4]
+  /* modify pbuf length fields */
+  p->len = (u16_t)(p->len - increment_magnitude);
+ 8017a58:	687b      	ldr	r3, [r7, #4]
+ 8017a5a:	895a      	ldrh	r2, [r3, #10]
+ 8017a5c:	89fb      	ldrh	r3, [r7, #14]
+ 8017a5e:	1ad3      	subs	r3, r2, r3
+ 8017a60:	b29a      	uxth	r2, r3
+ 8017a62:	687b      	ldr	r3, [r7, #4]
+ 8017a64:	815a      	strh	r2, [r3, #10]
+  p->tot_len = (u16_t)(p->tot_len - increment_magnitude);
+ 8017a66:	687b      	ldr	r3, [r7, #4]
+ 8017a68:	891a      	ldrh	r2, [r3, #8]
+ 8017a6a:	89fb      	ldrh	r3, [r7, #14]
+ 8017a6c:	1ad3      	subs	r3, r2, r3
+ 8017a6e:	b29a      	uxth	r2, r3
+ 8017a70:	687b      	ldr	r3, [r7, #4]
+ 8017a72:	811a      	strh	r2, [r3, #8]
+
+  LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_remove_header: old %p new %p (%"U16_F")\n",
+              (void *)payload, (void *)p->payload, increment_magnitude));
+
+  return 0;
+ 8017a74:	2300      	movs	r3, #0
+}
+ 8017a76:	4618      	mov	r0, r3
+ 8017a78:	3710      	adds	r7, #16
+ 8017a7a:	46bd      	mov	sp, r7
+ 8017a7c:	bd80      	pop	{r7, pc}
+ 8017a7e:	bf00      	nop
+ 8017a80:	080246a8 	.word	0x080246a8
+ 8017a84:	0802480c 	.word	0x0802480c
+ 8017a88:	08024708 	.word	0x08024708
+ 8017a8c:	08024818 	.word	0x08024818
+
+08017a90 <pbuf_header_impl>:
+
+static u8_t
+pbuf_header_impl(struct pbuf *p, s16_t header_size_increment, u8_t force)
+{
+ 8017a90:	b580      	push	{r7, lr}
+ 8017a92:	b082      	sub	sp, #8
+ 8017a94:	af00      	add	r7, sp, #0
+ 8017a96:	6078      	str	r0, [r7, #4]
+ 8017a98:	460b      	mov	r3, r1
+ 8017a9a:	807b      	strh	r3, [r7, #2]
+ 8017a9c:	4613      	mov	r3, r2
+ 8017a9e:	707b      	strb	r3, [r7, #1]
+  if (header_size_increment < 0) {
+ 8017aa0:	f9b7 3002 	ldrsh.w	r3, [r7, #2]
+ 8017aa4:	2b00      	cmp	r3, #0
+ 8017aa6:	da08      	bge.n	8017aba <pbuf_header_impl+0x2a>
+    return pbuf_remove_header(p, (size_t) - header_size_increment);
+ 8017aa8:	f9b7 3002 	ldrsh.w	r3, [r7, #2]
+ 8017aac:	425b      	negs	r3, r3
+ 8017aae:	4619      	mov	r1, r3
+ 8017ab0:	6878      	ldr	r0, [r7, #4]
+ 8017ab2:	f7ff ff9b 	bl	80179ec <pbuf_remove_header>
+ 8017ab6:	4603      	mov	r3, r0
+ 8017ab8:	e007      	b.n	8017aca <pbuf_header_impl+0x3a>
+  } else {
+    return pbuf_add_header_impl(p, (size_t)header_size_increment, force);
+ 8017aba:	f9b7 3002 	ldrsh.w	r3, [r7, #2]
+ 8017abe:	787a      	ldrb	r2, [r7, #1]
+ 8017ac0:	4619      	mov	r1, r3
+ 8017ac2:	6878      	ldr	r0, [r7, #4]
+ 8017ac4:	f7ff ff1a 	bl	80178fc <pbuf_add_header_impl>
+ 8017ac8:	4603      	mov	r3, r0
+  }
+}
+ 8017aca:	4618      	mov	r0, r3
+ 8017acc:	3708      	adds	r7, #8
+ 8017ace:	46bd      	mov	sp, r7
+ 8017ad0:	bd80      	pop	{r7, pc}
+
+08017ad2 <pbuf_header_force>:
+ * Same as pbuf_header but does not check if 'header_size > 0' is allowed.
+ * This is used internally only, to allow PBUF_REF for RX.
+ */
+u8_t
+pbuf_header_force(struct pbuf *p, s16_t header_size_increment)
+{
+ 8017ad2:	b580      	push	{r7, lr}
+ 8017ad4:	b082      	sub	sp, #8
+ 8017ad6:	af00      	add	r7, sp, #0
+ 8017ad8:	6078      	str	r0, [r7, #4]
+ 8017ada:	460b      	mov	r3, r1
+ 8017adc:	807b      	strh	r3, [r7, #2]
+  return pbuf_header_impl(p, header_size_increment, 1);
+ 8017ade:	f9b7 3002 	ldrsh.w	r3, [r7, #2]
+ 8017ae2:	2201      	movs	r2, #1
+ 8017ae4:	4619      	mov	r1, r3
+ 8017ae6:	6878      	ldr	r0, [r7, #4]
+ 8017ae8:	f7ff ffd2 	bl	8017a90 <pbuf_header_impl>
+ 8017aec:	4603      	mov	r3, r0
+}
+ 8017aee:	4618      	mov	r0, r3
+ 8017af0:	3708      	adds	r7, #8
+ 8017af2:	46bd      	mov	sp, r7
+ 8017af4:	bd80      	pop	{r7, pc}
+	...
+
+08017af8 <pbuf_free>:
+ * 1->1->1 becomes .......
+ *
+ */
+u8_t
+pbuf_free(struct pbuf *p)
+{
+ 8017af8:	b580      	push	{r7, lr}
+ 8017afa:	b088      	sub	sp, #32
+ 8017afc:	af00      	add	r7, sp, #0
+ 8017afe:	6078      	str	r0, [r7, #4]
+  u8_t alloc_src;
+  struct pbuf *q;
+  u8_t count;
+
+  if (p == NULL) {
+ 8017b00:	687b      	ldr	r3, [r7, #4]
+ 8017b02:	2b00      	cmp	r3, #0
+ 8017b04:	d10b      	bne.n	8017b1e <pbuf_free+0x26>
+    LWIP_ASSERT("p != NULL", p != NULL);
+ 8017b06:	687b      	ldr	r3, [r7, #4]
+ 8017b08:	2b00      	cmp	r3, #0
+ 8017b0a:	d106      	bne.n	8017b1a <pbuf_free+0x22>
+ 8017b0c:	4b3b      	ldr	r3, [pc, #236]	; (8017bfc <pbuf_free+0x104>)
+ 8017b0e:	f44f 7237 	mov.w	r2, #732	; 0x2dc
+ 8017b12:	493b      	ldr	r1, [pc, #236]	; (8017c00 <pbuf_free+0x108>)
+ 8017b14:	483b      	ldr	r0, [pc, #236]	; (8017c04 <pbuf_free+0x10c>)
+ 8017b16:	f009 ff37 	bl	8021988 <iprintf>
+    /* if assertions are disabled, proceed with debug output */
+    LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_LEVEL_SERIOUS,
+                ("pbuf_free(p == NULL) was called.\n"));
+    return 0;
+ 8017b1a:	2300      	movs	r3, #0
+ 8017b1c:	e069      	b.n	8017bf2 <pbuf_free+0xfa>
+  }
+  LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_free(%p)\n", (void *)p));
+
+  PERF_START;
+
+  count = 0;
+ 8017b1e:	2300      	movs	r3, #0
+ 8017b20:	77fb      	strb	r3, [r7, #31]
+  /* de-allocate all consecutive pbufs from the head of the chain that
+   * obtain a zero reference count after decrementing*/
+  while (p != NULL) {
+ 8017b22:	e062      	b.n	8017bea <pbuf_free+0xf2>
+    LWIP_PBUF_REF_T ref;
+    SYS_ARCH_DECL_PROTECT(old_level);
+    /* Since decrementing ref cannot be guaranteed to be a single machine operation
+     * we must protect it. We put the new ref into a local variable to prevent
+     * further protection. */
+    SYS_ARCH_PROTECT(old_level);
+ 8017b24:	f009 fd96 	bl	8021654 <sys_arch_protect>
+ 8017b28:	61b8      	str	r0, [r7, #24]
+    /* all pbufs in a chain are referenced at least once */
+    LWIP_ASSERT("pbuf_free: p->ref > 0", p->ref > 0);
+ 8017b2a:	687b      	ldr	r3, [r7, #4]
+ 8017b2c:	7b9b      	ldrb	r3, [r3, #14]
+ 8017b2e:	2b00      	cmp	r3, #0
+ 8017b30:	d106      	bne.n	8017b40 <pbuf_free+0x48>
+ 8017b32:	4b32      	ldr	r3, [pc, #200]	; (8017bfc <pbuf_free+0x104>)
+ 8017b34:	f240 22f1 	movw	r2, #753	; 0x2f1
+ 8017b38:	4933      	ldr	r1, [pc, #204]	; (8017c08 <pbuf_free+0x110>)
+ 8017b3a:	4832      	ldr	r0, [pc, #200]	; (8017c04 <pbuf_free+0x10c>)
+ 8017b3c:	f009 ff24 	bl	8021988 <iprintf>
+    /* decrease reference count (number of pointers to pbuf) */
+    ref = --(p->ref);
+ 8017b40:	687b      	ldr	r3, [r7, #4]
+ 8017b42:	7b9b      	ldrb	r3, [r3, #14]
+ 8017b44:	3b01      	subs	r3, #1
+ 8017b46:	b2da      	uxtb	r2, r3
+ 8017b48:	687b      	ldr	r3, [r7, #4]
+ 8017b4a:	739a      	strb	r2, [r3, #14]
+ 8017b4c:	687b      	ldr	r3, [r7, #4]
+ 8017b4e:	7b9b      	ldrb	r3, [r3, #14]
+ 8017b50:	75fb      	strb	r3, [r7, #23]
+    SYS_ARCH_UNPROTECT(old_level);
+ 8017b52:	69b8      	ldr	r0, [r7, #24]
+ 8017b54:	f009 fd8c 	bl	8021670 <sys_arch_unprotect>
+    /* this pbuf is no longer referenced to? */
+    if (ref == 0) {
+ 8017b58:	7dfb      	ldrb	r3, [r7, #23]
+ 8017b5a:	2b00      	cmp	r3, #0
+ 8017b5c:	d143      	bne.n	8017be6 <pbuf_free+0xee>
+      /* remember next pbuf in chain for next iteration */
+      q = p->next;
+ 8017b5e:	687b      	ldr	r3, [r7, #4]
+ 8017b60:	681b      	ldr	r3, [r3, #0]
+ 8017b62:	613b      	str	r3, [r7, #16]
+      LWIP_DEBUGF( PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_free: deallocating %p\n", (void *)p));
+      alloc_src = pbuf_get_allocsrc(p);
+ 8017b64:	687b      	ldr	r3, [r7, #4]
+ 8017b66:	7b1b      	ldrb	r3, [r3, #12]
+ 8017b68:	f003 030f 	and.w	r3, r3, #15
+ 8017b6c:	73fb      	strb	r3, [r7, #15]
+#if LWIP_SUPPORT_CUSTOM_PBUF
+      /* is this a custom pbuf? */
+      if ((p->flags & PBUF_FLAG_IS_CUSTOM) != 0) {
+ 8017b6e:	687b      	ldr	r3, [r7, #4]
+ 8017b70:	7b5b      	ldrb	r3, [r3, #13]
+ 8017b72:	f003 0302 	and.w	r3, r3, #2
+ 8017b76:	2b00      	cmp	r3, #0
+ 8017b78:	d011      	beq.n	8017b9e <pbuf_free+0xa6>
+        struct pbuf_custom *pc = (struct pbuf_custom *)p;
+ 8017b7a:	687b      	ldr	r3, [r7, #4]
+ 8017b7c:	60bb      	str	r3, [r7, #8]
+        LWIP_ASSERT("pc->custom_free_function != NULL", pc->custom_free_function != NULL);
+ 8017b7e:	68bb      	ldr	r3, [r7, #8]
+ 8017b80:	691b      	ldr	r3, [r3, #16]
+ 8017b82:	2b00      	cmp	r3, #0
+ 8017b84:	d106      	bne.n	8017b94 <pbuf_free+0x9c>
+ 8017b86:	4b1d      	ldr	r3, [pc, #116]	; (8017bfc <pbuf_free+0x104>)
+ 8017b88:	f240 22ff 	movw	r2, #767	; 0x2ff
+ 8017b8c:	491f      	ldr	r1, [pc, #124]	; (8017c0c <pbuf_free+0x114>)
+ 8017b8e:	481d      	ldr	r0, [pc, #116]	; (8017c04 <pbuf_free+0x10c>)
+ 8017b90:	f009 fefa 	bl	8021988 <iprintf>
+        pc->custom_free_function(p);
+ 8017b94:	68bb      	ldr	r3, [r7, #8]
+ 8017b96:	691b      	ldr	r3, [r3, #16]
+ 8017b98:	6878      	ldr	r0, [r7, #4]
+ 8017b9a:	4798      	blx	r3
+ 8017b9c:	e01d      	b.n	8017bda <pbuf_free+0xe2>
+      } else
+#endif /* LWIP_SUPPORT_CUSTOM_PBUF */
+      {
+        /* is this a pbuf from the pool? */
+        if (alloc_src == PBUF_TYPE_ALLOC_SRC_MASK_STD_MEMP_PBUF_POOL) {
+ 8017b9e:	7bfb      	ldrb	r3, [r7, #15]
+ 8017ba0:	2b02      	cmp	r3, #2
+ 8017ba2:	d104      	bne.n	8017bae <pbuf_free+0xb6>
+          memp_free(MEMP_PBUF_POOL, p);
+ 8017ba4:	6879      	ldr	r1, [r7, #4]
+ 8017ba6:	200c      	movs	r0, #12
+ 8017ba8:	f7ff f808 	bl	8016bbc <memp_free>
+ 8017bac:	e015      	b.n	8017bda <pbuf_free+0xe2>
+          /* is this a ROM or RAM referencing pbuf? */
+        } else if (alloc_src == PBUF_TYPE_ALLOC_SRC_MASK_STD_MEMP_PBUF) {
+ 8017bae:	7bfb      	ldrb	r3, [r7, #15]
+ 8017bb0:	2b01      	cmp	r3, #1
+ 8017bb2:	d104      	bne.n	8017bbe <pbuf_free+0xc6>
+          memp_free(MEMP_PBUF, p);
+ 8017bb4:	6879      	ldr	r1, [r7, #4]
+ 8017bb6:	200b      	movs	r0, #11
+ 8017bb8:	f7ff f800 	bl	8016bbc <memp_free>
+ 8017bbc:	e00d      	b.n	8017bda <pbuf_free+0xe2>
+          /* type == PBUF_RAM */
+        } else if (alloc_src == PBUF_TYPE_ALLOC_SRC_MASK_STD_HEAP) {
+ 8017bbe:	7bfb      	ldrb	r3, [r7, #15]
+ 8017bc0:	2b00      	cmp	r3, #0
+ 8017bc2:	d103      	bne.n	8017bcc <pbuf_free+0xd4>
+          mem_free(p);
+ 8017bc4:	6878      	ldr	r0, [r7, #4]
+ 8017bc6:	f7fe fc13 	bl	80163f0 <mem_free>
+ 8017bca:	e006      	b.n	8017bda <pbuf_free+0xe2>
+        } else {
+          /* @todo: support freeing other types */
+          LWIP_ASSERT("invalid pbuf type", 0);
+ 8017bcc:	4b0b      	ldr	r3, [pc, #44]	; (8017bfc <pbuf_free+0x104>)
+ 8017bce:	f240 320f 	movw	r2, #783	; 0x30f
+ 8017bd2:	490f      	ldr	r1, [pc, #60]	; (8017c10 <pbuf_free+0x118>)
+ 8017bd4:	480b      	ldr	r0, [pc, #44]	; (8017c04 <pbuf_free+0x10c>)
+ 8017bd6:	f009 fed7 	bl	8021988 <iprintf>
+        }
+      }
+      count++;
+ 8017bda:	7ffb      	ldrb	r3, [r7, #31]
+ 8017bdc:	3301      	adds	r3, #1
+ 8017bde:	77fb      	strb	r3, [r7, #31]
+      /* proceed to next pbuf */
+      p = q;
+ 8017be0:	693b      	ldr	r3, [r7, #16]
+ 8017be2:	607b      	str	r3, [r7, #4]
+ 8017be4:	e001      	b.n	8017bea <pbuf_free+0xf2>
+      /* p->ref > 0, this pbuf is still referenced to */
+      /* (and so the remaining pbufs in chain as well) */
+    } else {
+      LWIP_DEBUGF( PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_free: %p has ref %"U16_F", ending here.\n", (void *)p, (u16_t)ref));
+      /* stop walking through the chain */
+      p = NULL;
+ 8017be6:	2300      	movs	r3, #0
+ 8017be8:	607b      	str	r3, [r7, #4]
+  while (p != NULL) {
+ 8017bea:	687b      	ldr	r3, [r7, #4]
+ 8017bec:	2b00      	cmp	r3, #0
+ 8017bee:	d199      	bne.n	8017b24 <pbuf_free+0x2c>
+    }
+  }
+  PERF_STOP("pbuf_free");
+  /* return number of de-allocated pbufs */
+  return count;
+ 8017bf0:	7ffb      	ldrb	r3, [r7, #31]
+}
+ 8017bf2:	4618      	mov	r0, r3
+ 8017bf4:	3720      	adds	r7, #32
+ 8017bf6:	46bd      	mov	sp, r7
+ 8017bf8:	bd80      	pop	{r7, pc}
+ 8017bfa:	bf00      	nop
+ 8017bfc:	080246a8 	.word	0x080246a8
+ 8017c00:	0802480c 	.word	0x0802480c
+ 8017c04:	08024708 	.word	0x08024708
+ 8017c08:	08024838 	.word	0x08024838
+ 8017c0c:	08024850 	.word	0x08024850
+ 8017c10:	08024874 	.word	0x08024874
+
+08017c14 <pbuf_clen>:
+ * @param p first pbuf of chain
+ * @return the number of pbufs in a chain
+ */
+u16_t
+pbuf_clen(const struct pbuf *p)
+{
+ 8017c14:	b480      	push	{r7}
+ 8017c16:	b085      	sub	sp, #20
+ 8017c18:	af00      	add	r7, sp, #0
+ 8017c1a:	6078      	str	r0, [r7, #4]
+  u16_t len;
+
+  len = 0;
+ 8017c1c:	2300      	movs	r3, #0
+ 8017c1e:	81fb      	strh	r3, [r7, #14]
+  while (p != NULL) {
+ 8017c20:	e005      	b.n	8017c2e <pbuf_clen+0x1a>
+    ++len;
+ 8017c22:	89fb      	ldrh	r3, [r7, #14]
+ 8017c24:	3301      	adds	r3, #1
+ 8017c26:	81fb      	strh	r3, [r7, #14]
+    p = p->next;
+ 8017c28:	687b      	ldr	r3, [r7, #4]
+ 8017c2a:	681b      	ldr	r3, [r3, #0]
+ 8017c2c:	607b      	str	r3, [r7, #4]
+  while (p != NULL) {
+ 8017c2e:	687b      	ldr	r3, [r7, #4]
+ 8017c30:	2b00      	cmp	r3, #0
+ 8017c32:	d1f6      	bne.n	8017c22 <pbuf_clen+0xe>
+  }
+  return len;
+ 8017c34:	89fb      	ldrh	r3, [r7, #14]
+}
+ 8017c36:	4618      	mov	r0, r3
+ 8017c38:	3714      	adds	r7, #20
+ 8017c3a:	46bd      	mov	sp, r7
+ 8017c3c:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8017c40:	4770      	bx	lr
+	...
+
+08017c44 <pbuf_ref>:
+ * @param p pbuf to increase reference counter of
+ *
+ */
+void
+pbuf_ref(struct pbuf *p)
+{
+ 8017c44:	b580      	push	{r7, lr}
+ 8017c46:	b084      	sub	sp, #16
+ 8017c48:	af00      	add	r7, sp, #0
+ 8017c4a:	6078      	str	r0, [r7, #4]
+  /* pbuf given? */
+  if (p != NULL) {
+ 8017c4c:	687b      	ldr	r3, [r7, #4]
+ 8017c4e:	2b00      	cmp	r3, #0
+ 8017c50:	d016      	beq.n	8017c80 <pbuf_ref+0x3c>
+    SYS_ARCH_SET(p->ref, (LWIP_PBUF_REF_T)(p->ref + 1));
+ 8017c52:	f009 fcff 	bl	8021654 <sys_arch_protect>
+ 8017c56:	60f8      	str	r0, [r7, #12]
+ 8017c58:	687b      	ldr	r3, [r7, #4]
+ 8017c5a:	7b9b      	ldrb	r3, [r3, #14]
+ 8017c5c:	3301      	adds	r3, #1
+ 8017c5e:	b2da      	uxtb	r2, r3
+ 8017c60:	687b      	ldr	r3, [r7, #4]
+ 8017c62:	739a      	strb	r2, [r3, #14]
+ 8017c64:	68f8      	ldr	r0, [r7, #12]
+ 8017c66:	f009 fd03 	bl	8021670 <sys_arch_unprotect>
+    LWIP_ASSERT("pbuf ref overflow", p->ref > 0);
+ 8017c6a:	687b      	ldr	r3, [r7, #4]
+ 8017c6c:	7b9b      	ldrb	r3, [r3, #14]
+ 8017c6e:	2b00      	cmp	r3, #0
+ 8017c70:	d106      	bne.n	8017c80 <pbuf_ref+0x3c>
+ 8017c72:	4b05      	ldr	r3, [pc, #20]	; (8017c88 <pbuf_ref+0x44>)
+ 8017c74:	f240 3242 	movw	r2, #834	; 0x342
+ 8017c78:	4904      	ldr	r1, [pc, #16]	; (8017c8c <pbuf_ref+0x48>)
+ 8017c7a:	4805      	ldr	r0, [pc, #20]	; (8017c90 <pbuf_ref+0x4c>)
+ 8017c7c:	f009 fe84 	bl	8021988 <iprintf>
+  }
+}
+ 8017c80:	bf00      	nop
+ 8017c82:	3710      	adds	r7, #16
+ 8017c84:	46bd      	mov	sp, r7
+ 8017c86:	bd80      	pop	{r7, pc}
+ 8017c88:	080246a8 	.word	0x080246a8
+ 8017c8c:	08024888 	.word	0x08024888
+ 8017c90:	08024708 	.word	0x08024708
+
+08017c94 <pbuf_cat>:
+ *
+ * @see pbuf_chain()
+ */
+void
+pbuf_cat(struct pbuf *h, struct pbuf *t)
+{
+ 8017c94:	b580      	push	{r7, lr}
+ 8017c96:	b084      	sub	sp, #16
+ 8017c98:	af00      	add	r7, sp, #0
+ 8017c9a:	6078      	str	r0, [r7, #4]
+ 8017c9c:	6039      	str	r1, [r7, #0]
+  struct pbuf *p;
+
+  LWIP_ERROR("(h != NULL) && (t != NULL) (programmer violates API)",
+ 8017c9e:	687b      	ldr	r3, [r7, #4]
+ 8017ca0:	2b00      	cmp	r3, #0
+ 8017ca2:	d002      	beq.n	8017caa <pbuf_cat+0x16>
+ 8017ca4:	683b      	ldr	r3, [r7, #0]
+ 8017ca6:	2b00      	cmp	r3, #0
+ 8017ca8:	d107      	bne.n	8017cba <pbuf_cat+0x26>
+ 8017caa:	4b20      	ldr	r3, [pc, #128]	; (8017d2c <pbuf_cat+0x98>)
+ 8017cac:	f240 3259 	movw	r2, #857	; 0x359
+ 8017cb0:	491f      	ldr	r1, [pc, #124]	; (8017d30 <pbuf_cat+0x9c>)
+ 8017cb2:	4820      	ldr	r0, [pc, #128]	; (8017d34 <pbuf_cat+0xa0>)
+ 8017cb4:	f009 fe68 	bl	8021988 <iprintf>
+ 8017cb8:	e034      	b.n	8017d24 <pbuf_cat+0x90>
+             ((h != NULL) && (t != NULL)), return;);
+
+  /* proceed to last pbuf of chain */
+  for (p = h; p->next != NULL; p = p->next) {
+ 8017cba:	687b      	ldr	r3, [r7, #4]
+ 8017cbc:	60fb      	str	r3, [r7, #12]
+ 8017cbe:	e00a      	b.n	8017cd6 <pbuf_cat+0x42>
+    /* add total length of second chain to all totals of first chain */
+    p->tot_len = (u16_t)(p->tot_len + t->tot_len);
+ 8017cc0:	68fb      	ldr	r3, [r7, #12]
+ 8017cc2:	891a      	ldrh	r2, [r3, #8]
+ 8017cc4:	683b      	ldr	r3, [r7, #0]
+ 8017cc6:	891b      	ldrh	r3, [r3, #8]
+ 8017cc8:	4413      	add	r3, r2
+ 8017cca:	b29a      	uxth	r2, r3
+ 8017ccc:	68fb      	ldr	r3, [r7, #12]
+ 8017cce:	811a      	strh	r2, [r3, #8]
+  for (p = h; p->next != NULL; p = p->next) {
+ 8017cd0:	68fb      	ldr	r3, [r7, #12]
+ 8017cd2:	681b      	ldr	r3, [r3, #0]
+ 8017cd4:	60fb      	str	r3, [r7, #12]
+ 8017cd6:	68fb      	ldr	r3, [r7, #12]
+ 8017cd8:	681b      	ldr	r3, [r3, #0]
+ 8017cda:	2b00      	cmp	r3, #0
+ 8017cdc:	d1f0      	bne.n	8017cc0 <pbuf_cat+0x2c>
+  }
+  /* { p is last pbuf of first h chain, p->next == NULL } */
+  LWIP_ASSERT("p->tot_len == p->len (of last pbuf in chain)", p->tot_len == p->len);
+ 8017cde:	68fb      	ldr	r3, [r7, #12]
+ 8017ce0:	891a      	ldrh	r2, [r3, #8]
+ 8017ce2:	68fb      	ldr	r3, [r7, #12]
+ 8017ce4:	895b      	ldrh	r3, [r3, #10]
+ 8017ce6:	429a      	cmp	r2, r3
+ 8017ce8:	d006      	beq.n	8017cf8 <pbuf_cat+0x64>
+ 8017cea:	4b10      	ldr	r3, [pc, #64]	; (8017d2c <pbuf_cat+0x98>)
+ 8017cec:	f240 3262 	movw	r2, #866	; 0x362
+ 8017cf0:	4911      	ldr	r1, [pc, #68]	; (8017d38 <pbuf_cat+0xa4>)
+ 8017cf2:	4810      	ldr	r0, [pc, #64]	; (8017d34 <pbuf_cat+0xa0>)
+ 8017cf4:	f009 fe48 	bl	8021988 <iprintf>
+  LWIP_ASSERT("p->next == NULL", p->next == NULL);
+ 8017cf8:	68fb      	ldr	r3, [r7, #12]
+ 8017cfa:	681b      	ldr	r3, [r3, #0]
+ 8017cfc:	2b00      	cmp	r3, #0
+ 8017cfe:	d006      	beq.n	8017d0e <pbuf_cat+0x7a>
+ 8017d00:	4b0a      	ldr	r3, [pc, #40]	; (8017d2c <pbuf_cat+0x98>)
+ 8017d02:	f240 3263 	movw	r2, #867	; 0x363
+ 8017d06:	490d      	ldr	r1, [pc, #52]	; (8017d3c <pbuf_cat+0xa8>)
+ 8017d08:	480a      	ldr	r0, [pc, #40]	; (8017d34 <pbuf_cat+0xa0>)
+ 8017d0a:	f009 fe3d 	bl	8021988 <iprintf>
+  /* add total length of second chain to last pbuf total of first chain */
+  p->tot_len = (u16_t)(p->tot_len + t->tot_len);
+ 8017d0e:	68fb      	ldr	r3, [r7, #12]
+ 8017d10:	891a      	ldrh	r2, [r3, #8]
+ 8017d12:	683b      	ldr	r3, [r7, #0]
+ 8017d14:	891b      	ldrh	r3, [r3, #8]
+ 8017d16:	4413      	add	r3, r2
+ 8017d18:	b29a      	uxth	r2, r3
+ 8017d1a:	68fb      	ldr	r3, [r7, #12]
+ 8017d1c:	811a      	strh	r2, [r3, #8]
+  /* chain last pbuf of head (p) with first of tail (t) */
+  p->next = t;
+ 8017d1e:	68fb      	ldr	r3, [r7, #12]
+ 8017d20:	683a      	ldr	r2, [r7, #0]
+ 8017d22:	601a      	str	r2, [r3, #0]
+  /* p->next now references t, but the caller will drop its reference to t,
+   * so netto there is no change to the reference count of t.
+   */
+}
+ 8017d24:	3710      	adds	r7, #16
+ 8017d26:	46bd      	mov	sp, r7
+ 8017d28:	bd80      	pop	{r7, pc}
+ 8017d2a:	bf00      	nop
+ 8017d2c:	080246a8 	.word	0x080246a8
+ 8017d30:	0802489c 	.word	0x0802489c
+ 8017d34:	08024708 	.word	0x08024708
+ 8017d38:	080248d4 	.word	0x080248d4
+ 8017d3c:	08024904 	.word	0x08024904
+
+08017d40 <pbuf_copy>:
+ *         ERR_ARG if one of the pbufs is NULL or p_to is not big
+ *                 enough to hold p_from
+ */
+err_t
+pbuf_copy(struct pbuf *p_to, const struct pbuf *p_from)
+{
+ 8017d40:	b580      	push	{r7, lr}
+ 8017d42:	b086      	sub	sp, #24
+ 8017d44:	af00      	add	r7, sp, #0
+ 8017d46:	6078      	str	r0, [r7, #4]
+ 8017d48:	6039      	str	r1, [r7, #0]
+  size_t offset_to = 0, offset_from = 0, len;
+ 8017d4a:	2300      	movs	r3, #0
+ 8017d4c:	617b      	str	r3, [r7, #20]
+ 8017d4e:	2300      	movs	r3, #0
+ 8017d50:	613b      	str	r3, [r7, #16]
+
+  LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_copy(%p, %p)\n",
+              (const void *)p_to, (const void *)p_from));
+
+  /* is the target big enough to hold the source? */
+  LWIP_ERROR("pbuf_copy: target not big enough to hold source", ((p_to != NULL) &&
+ 8017d52:	687b      	ldr	r3, [r7, #4]
+ 8017d54:	2b00      	cmp	r3, #0
+ 8017d56:	d008      	beq.n	8017d6a <pbuf_copy+0x2a>
+ 8017d58:	683b      	ldr	r3, [r7, #0]
+ 8017d5a:	2b00      	cmp	r3, #0
+ 8017d5c:	d005      	beq.n	8017d6a <pbuf_copy+0x2a>
+ 8017d5e:	687b      	ldr	r3, [r7, #4]
+ 8017d60:	891a      	ldrh	r2, [r3, #8]
+ 8017d62:	683b      	ldr	r3, [r7, #0]
+ 8017d64:	891b      	ldrh	r3, [r3, #8]
+ 8017d66:	429a      	cmp	r2, r3
+ 8017d68:	d209      	bcs.n	8017d7e <pbuf_copy+0x3e>
+ 8017d6a:	4b57      	ldr	r3, [pc, #348]	; (8017ec8 <pbuf_copy+0x188>)
+ 8017d6c:	f240 32c9 	movw	r2, #969	; 0x3c9
+ 8017d70:	4956      	ldr	r1, [pc, #344]	; (8017ecc <pbuf_copy+0x18c>)
+ 8017d72:	4857      	ldr	r0, [pc, #348]	; (8017ed0 <pbuf_copy+0x190>)
+ 8017d74:	f009 fe08 	bl	8021988 <iprintf>
+ 8017d78:	f06f 030f 	mvn.w	r3, #15
+ 8017d7c:	e09f      	b.n	8017ebe <pbuf_copy+0x17e>
+             (p_from != NULL) && (p_to->tot_len >= p_from->tot_len)), return ERR_ARG;);
+
+  /* iterate through pbuf chain */
+  do {
+    /* copy one part of the original chain */
+    if ((p_to->len - offset_to) >= (p_from->len - offset_from)) {
+ 8017d7e:	687b      	ldr	r3, [r7, #4]
+ 8017d80:	895b      	ldrh	r3, [r3, #10]
+ 8017d82:	461a      	mov	r2, r3
+ 8017d84:	697b      	ldr	r3, [r7, #20]
+ 8017d86:	1ad2      	subs	r2, r2, r3
+ 8017d88:	683b      	ldr	r3, [r7, #0]
+ 8017d8a:	895b      	ldrh	r3, [r3, #10]
+ 8017d8c:	4619      	mov	r1, r3
+ 8017d8e:	693b      	ldr	r3, [r7, #16]
+ 8017d90:	1acb      	subs	r3, r1, r3
+ 8017d92:	429a      	cmp	r2, r3
+ 8017d94:	d306      	bcc.n	8017da4 <pbuf_copy+0x64>
+      /* complete current p_from fits into current p_to */
+      len = p_from->len - offset_from;
+ 8017d96:	683b      	ldr	r3, [r7, #0]
+ 8017d98:	895b      	ldrh	r3, [r3, #10]
+ 8017d9a:	461a      	mov	r2, r3
+ 8017d9c:	693b      	ldr	r3, [r7, #16]
+ 8017d9e:	1ad3      	subs	r3, r2, r3
+ 8017da0:	60fb      	str	r3, [r7, #12]
+ 8017da2:	e005      	b.n	8017db0 <pbuf_copy+0x70>
+    } else {
+      /* current p_from does not fit into current p_to */
+      len = p_to->len - offset_to;
+ 8017da4:	687b      	ldr	r3, [r7, #4]
+ 8017da6:	895b      	ldrh	r3, [r3, #10]
+ 8017da8:	461a      	mov	r2, r3
+ 8017daa:	697b      	ldr	r3, [r7, #20]
+ 8017dac:	1ad3      	subs	r3, r2, r3
+ 8017dae:	60fb      	str	r3, [r7, #12]
+    }
+    MEMCPY((u8_t *)p_to->payload + offset_to, (u8_t *)p_from->payload + offset_from, len);
+ 8017db0:	687b      	ldr	r3, [r7, #4]
+ 8017db2:	685a      	ldr	r2, [r3, #4]
+ 8017db4:	697b      	ldr	r3, [r7, #20]
+ 8017db6:	18d0      	adds	r0, r2, r3
+ 8017db8:	683b      	ldr	r3, [r7, #0]
+ 8017dba:	685a      	ldr	r2, [r3, #4]
+ 8017dbc:	693b      	ldr	r3, [r7, #16]
+ 8017dbe:	4413      	add	r3, r2
+ 8017dc0:	68fa      	ldr	r2, [r7, #12]
+ 8017dc2:	4619      	mov	r1, r3
+ 8017dc4:	f00a f80f 	bl	8021de6 <memcpy>
+    offset_to += len;
+ 8017dc8:	697a      	ldr	r2, [r7, #20]
+ 8017dca:	68fb      	ldr	r3, [r7, #12]
+ 8017dcc:	4413      	add	r3, r2
+ 8017dce:	617b      	str	r3, [r7, #20]
+    offset_from += len;
+ 8017dd0:	693a      	ldr	r2, [r7, #16]
+ 8017dd2:	68fb      	ldr	r3, [r7, #12]
+ 8017dd4:	4413      	add	r3, r2
+ 8017dd6:	613b      	str	r3, [r7, #16]
+    LWIP_ASSERT("offset_to <= p_to->len", offset_to <= p_to->len);
+ 8017dd8:	687b      	ldr	r3, [r7, #4]
+ 8017dda:	895b      	ldrh	r3, [r3, #10]
+ 8017ddc:	461a      	mov	r2, r3
+ 8017dde:	697b      	ldr	r3, [r7, #20]
+ 8017de0:	4293      	cmp	r3, r2
+ 8017de2:	d906      	bls.n	8017df2 <pbuf_copy+0xb2>
+ 8017de4:	4b38      	ldr	r3, [pc, #224]	; (8017ec8 <pbuf_copy+0x188>)
+ 8017de6:	f240 32d9 	movw	r2, #985	; 0x3d9
+ 8017dea:	493a      	ldr	r1, [pc, #232]	; (8017ed4 <pbuf_copy+0x194>)
+ 8017dec:	4838      	ldr	r0, [pc, #224]	; (8017ed0 <pbuf_copy+0x190>)
+ 8017dee:	f009 fdcb 	bl	8021988 <iprintf>
+    LWIP_ASSERT("offset_from <= p_from->len", offset_from <= p_from->len);
+ 8017df2:	683b      	ldr	r3, [r7, #0]
+ 8017df4:	895b      	ldrh	r3, [r3, #10]
+ 8017df6:	461a      	mov	r2, r3
+ 8017df8:	693b      	ldr	r3, [r7, #16]
+ 8017dfa:	4293      	cmp	r3, r2
+ 8017dfc:	d906      	bls.n	8017e0c <pbuf_copy+0xcc>
+ 8017dfe:	4b32      	ldr	r3, [pc, #200]	; (8017ec8 <pbuf_copy+0x188>)
+ 8017e00:	f240 32da 	movw	r2, #986	; 0x3da
+ 8017e04:	4934      	ldr	r1, [pc, #208]	; (8017ed8 <pbuf_copy+0x198>)
+ 8017e06:	4832      	ldr	r0, [pc, #200]	; (8017ed0 <pbuf_copy+0x190>)
+ 8017e08:	f009 fdbe 	bl	8021988 <iprintf>
+    if (offset_from >= p_from->len) {
+ 8017e0c:	683b      	ldr	r3, [r7, #0]
+ 8017e0e:	895b      	ldrh	r3, [r3, #10]
+ 8017e10:	461a      	mov	r2, r3
+ 8017e12:	693b      	ldr	r3, [r7, #16]
+ 8017e14:	4293      	cmp	r3, r2
+ 8017e16:	d304      	bcc.n	8017e22 <pbuf_copy+0xe2>
+      /* on to next p_from (if any) */
+      offset_from = 0;
+ 8017e18:	2300      	movs	r3, #0
+ 8017e1a:	613b      	str	r3, [r7, #16]
+      p_from = p_from->next;
+ 8017e1c:	683b      	ldr	r3, [r7, #0]
+ 8017e1e:	681b      	ldr	r3, [r3, #0]
+ 8017e20:	603b      	str	r3, [r7, #0]
+    }
+    if (offset_to == p_to->len) {
+ 8017e22:	687b      	ldr	r3, [r7, #4]
+ 8017e24:	895b      	ldrh	r3, [r3, #10]
+ 8017e26:	461a      	mov	r2, r3
+ 8017e28:	697b      	ldr	r3, [r7, #20]
+ 8017e2a:	4293      	cmp	r3, r2
+ 8017e2c:	d114      	bne.n	8017e58 <pbuf_copy+0x118>
+      /* on to next p_to (if any) */
+      offset_to = 0;
+ 8017e2e:	2300      	movs	r3, #0
+ 8017e30:	617b      	str	r3, [r7, #20]
+      p_to = p_to->next;
+ 8017e32:	687b      	ldr	r3, [r7, #4]
+ 8017e34:	681b      	ldr	r3, [r3, #0]
+ 8017e36:	607b      	str	r3, [r7, #4]
+      LWIP_ERROR("p_to != NULL", (p_to != NULL) || (p_from == NULL), return ERR_ARG;);
+ 8017e38:	687b      	ldr	r3, [r7, #4]
+ 8017e3a:	2b00      	cmp	r3, #0
+ 8017e3c:	d10c      	bne.n	8017e58 <pbuf_copy+0x118>
+ 8017e3e:	683b      	ldr	r3, [r7, #0]
+ 8017e40:	2b00      	cmp	r3, #0
+ 8017e42:	d009      	beq.n	8017e58 <pbuf_copy+0x118>
+ 8017e44:	4b20      	ldr	r3, [pc, #128]	; (8017ec8 <pbuf_copy+0x188>)
+ 8017e46:	f44f 7279 	mov.w	r2, #996	; 0x3e4
+ 8017e4a:	4924      	ldr	r1, [pc, #144]	; (8017edc <pbuf_copy+0x19c>)
+ 8017e4c:	4820      	ldr	r0, [pc, #128]	; (8017ed0 <pbuf_copy+0x190>)
+ 8017e4e:	f009 fd9b 	bl	8021988 <iprintf>
+ 8017e52:	f06f 030f 	mvn.w	r3, #15
+ 8017e56:	e032      	b.n	8017ebe <pbuf_copy+0x17e>
+    }
+
+    if ((p_from != NULL) && (p_from->len == p_from->tot_len)) {
+ 8017e58:	683b      	ldr	r3, [r7, #0]
+ 8017e5a:	2b00      	cmp	r3, #0
+ 8017e5c:	d013      	beq.n	8017e86 <pbuf_copy+0x146>
+ 8017e5e:	683b      	ldr	r3, [r7, #0]
+ 8017e60:	895a      	ldrh	r2, [r3, #10]
+ 8017e62:	683b      	ldr	r3, [r7, #0]
+ 8017e64:	891b      	ldrh	r3, [r3, #8]
+ 8017e66:	429a      	cmp	r2, r3
+ 8017e68:	d10d      	bne.n	8017e86 <pbuf_copy+0x146>
+      /* don't copy more than one packet! */
+      LWIP_ERROR("pbuf_copy() does not allow packet queues!",
+ 8017e6a:	683b      	ldr	r3, [r7, #0]
+ 8017e6c:	681b      	ldr	r3, [r3, #0]
+ 8017e6e:	2b00      	cmp	r3, #0
+ 8017e70:	d009      	beq.n	8017e86 <pbuf_copy+0x146>
+ 8017e72:	4b15      	ldr	r3, [pc, #84]	; (8017ec8 <pbuf_copy+0x188>)
+ 8017e74:	f240 32e9 	movw	r2, #1001	; 0x3e9
+ 8017e78:	4919      	ldr	r1, [pc, #100]	; (8017ee0 <pbuf_copy+0x1a0>)
+ 8017e7a:	4815      	ldr	r0, [pc, #84]	; (8017ed0 <pbuf_copy+0x190>)
+ 8017e7c:	f009 fd84 	bl	8021988 <iprintf>
+ 8017e80:	f06f 0305 	mvn.w	r3, #5
+ 8017e84:	e01b      	b.n	8017ebe <pbuf_copy+0x17e>
+                 (p_from->next == NULL), return ERR_VAL;);
+    }
+    if ((p_to != NULL) && (p_to->len == p_to->tot_len)) {
+ 8017e86:	687b      	ldr	r3, [r7, #4]
+ 8017e88:	2b00      	cmp	r3, #0
+ 8017e8a:	d013      	beq.n	8017eb4 <pbuf_copy+0x174>
+ 8017e8c:	687b      	ldr	r3, [r7, #4]
+ 8017e8e:	895a      	ldrh	r2, [r3, #10]
+ 8017e90:	687b      	ldr	r3, [r7, #4]
+ 8017e92:	891b      	ldrh	r3, [r3, #8]
+ 8017e94:	429a      	cmp	r2, r3
+ 8017e96:	d10d      	bne.n	8017eb4 <pbuf_copy+0x174>
+      /* don't copy more than one packet! */
+      LWIP_ERROR("pbuf_copy() does not allow packet queues!",
+ 8017e98:	687b      	ldr	r3, [r7, #4]
+ 8017e9a:	681b      	ldr	r3, [r3, #0]
+ 8017e9c:	2b00      	cmp	r3, #0
+ 8017e9e:	d009      	beq.n	8017eb4 <pbuf_copy+0x174>
+ 8017ea0:	4b09      	ldr	r3, [pc, #36]	; (8017ec8 <pbuf_copy+0x188>)
+ 8017ea2:	f240 32ee 	movw	r2, #1006	; 0x3ee
+ 8017ea6:	490e      	ldr	r1, [pc, #56]	; (8017ee0 <pbuf_copy+0x1a0>)
+ 8017ea8:	4809      	ldr	r0, [pc, #36]	; (8017ed0 <pbuf_copy+0x190>)
+ 8017eaa:	f009 fd6d 	bl	8021988 <iprintf>
+ 8017eae:	f06f 0305 	mvn.w	r3, #5
+ 8017eb2:	e004      	b.n	8017ebe <pbuf_copy+0x17e>
+                 (p_to->next == NULL), return ERR_VAL;);
+    }
+  } while (p_from);
+ 8017eb4:	683b      	ldr	r3, [r7, #0]
+ 8017eb6:	2b00      	cmp	r3, #0
+ 8017eb8:	f47f af61 	bne.w	8017d7e <pbuf_copy+0x3e>
+  LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_copy: end of chain reached.\n"));
+  return ERR_OK;
+ 8017ebc:	2300      	movs	r3, #0
+}
+ 8017ebe:	4618      	mov	r0, r3
+ 8017ec0:	3718      	adds	r7, #24
+ 8017ec2:	46bd      	mov	sp, r7
+ 8017ec4:	bd80      	pop	{r7, pc}
+ 8017ec6:	bf00      	nop
+ 8017ec8:	080246a8 	.word	0x080246a8
+ 8017ecc:	08024950 	.word	0x08024950
+ 8017ed0:	08024708 	.word	0x08024708
+ 8017ed4:	08024980 	.word	0x08024980
+ 8017ed8:	08024998 	.word	0x08024998
+ 8017edc:	080249b4 	.word	0x080249b4
+ 8017ee0:	080249c4 	.word	0x080249c4
+
+08017ee4 <pbuf_copy_partial>:
+ * @param offset offset into the packet buffer from where to begin copying len bytes
+ * @return the number of bytes copied, or 0 on failure
+ */
+u16_t
+pbuf_copy_partial(const struct pbuf *buf, void *dataptr, u16_t len, u16_t offset)
+{
+ 8017ee4:	b580      	push	{r7, lr}
+ 8017ee6:	b088      	sub	sp, #32
+ 8017ee8:	af00      	add	r7, sp, #0
+ 8017eea:	60f8      	str	r0, [r7, #12]
+ 8017eec:	60b9      	str	r1, [r7, #8]
+ 8017eee:	4611      	mov	r1, r2
+ 8017ef0:	461a      	mov	r2, r3
+ 8017ef2:	460b      	mov	r3, r1
+ 8017ef4:	80fb      	strh	r3, [r7, #6]
+ 8017ef6:	4613      	mov	r3, r2
+ 8017ef8:	80bb      	strh	r3, [r7, #4]
+  const struct pbuf *p;
+  u16_t left = 0;
+ 8017efa:	2300      	movs	r3, #0
+ 8017efc:	837b      	strh	r3, [r7, #26]
+  u16_t buf_copy_len;
+  u16_t copied_total = 0;
+ 8017efe:	2300      	movs	r3, #0
+ 8017f00:	82fb      	strh	r3, [r7, #22]
+
+  LWIP_ERROR("pbuf_copy_partial: invalid buf", (buf != NULL), return 0;);
+ 8017f02:	68fb      	ldr	r3, [r7, #12]
+ 8017f04:	2b00      	cmp	r3, #0
+ 8017f06:	d108      	bne.n	8017f1a <pbuf_copy_partial+0x36>
+ 8017f08:	4b2b      	ldr	r3, [pc, #172]	; (8017fb8 <pbuf_copy_partial+0xd4>)
+ 8017f0a:	f240 420a 	movw	r2, #1034	; 0x40a
+ 8017f0e:	492b      	ldr	r1, [pc, #172]	; (8017fbc <pbuf_copy_partial+0xd8>)
+ 8017f10:	482b      	ldr	r0, [pc, #172]	; (8017fc0 <pbuf_copy_partial+0xdc>)
+ 8017f12:	f009 fd39 	bl	8021988 <iprintf>
+ 8017f16:	2300      	movs	r3, #0
+ 8017f18:	e04a      	b.n	8017fb0 <pbuf_copy_partial+0xcc>
+  LWIP_ERROR("pbuf_copy_partial: invalid dataptr", (dataptr != NULL), return 0;);
+ 8017f1a:	68bb      	ldr	r3, [r7, #8]
+ 8017f1c:	2b00      	cmp	r3, #0
+ 8017f1e:	d108      	bne.n	8017f32 <pbuf_copy_partial+0x4e>
+ 8017f20:	4b25      	ldr	r3, [pc, #148]	; (8017fb8 <pbuf_copy_partial+0xd4>)
+ 8017f22:	f240 420b 	movw	r2, #1035	; 0x40b
+ 8017f26:	4927      	ldr	r1, [pc, #156]	; (8017fc4 <pbuf_copy_partial+0xe0>)
+ 8017f28:	4825      	ldr	r0, [pc, #148]	; (8017fc0 <pbuf_copy_partial+0xdc>)
+ 8017f2a:	f009 fd2d 	bl	8021988 <iprintf>
+ 8017f2e:	2300      	movs	r3, #0
+ 8017f30:	e03e      	b.n	8017fb0 <pbuf_copy_partial+0xcc>
+
+  /* Note some systems use byte copy if dataptr or one of the pbuf payload pointers are unaligned. */
+  for (p = buf; len != 0 && p != NULL; p = p->next) {
+ 8017f32:	68fb      	ldr	r3, [r7, #12]
+ 8017f34:	61fb      	str	r3, [r7, #28]
+ 8017f36:	e034      	b.n	8017fa2 <pbuf_copy_partial+0xbe>
+    if ((offset != 0) && (offset >= p->len)) {
+ 8017f38:	88bb      	ldrh	r3, [r7, #4]
+ 8017f3a:	2b00      	cmp	r3, #0
+ 8017f3c:	d00a      	beq.n	8017f54 <pbuf_copy_partial+0x70>
+ 8017f3e:	69fb      	ldr	r3, [r7, #28]
+ 8017f40:	895b      	ldrh	r3, [r3, #10]
+ 8017f42:	88ba      	ldrh	r2, [r7, #4]
+ 8017f44:	429a      	cmp	r2, r3
+ 8017f46:	d305      	bcc.n	8017f54 <pbuf_copy_partial+0x70>
+      /* don't copy from this buffer -> on to the next */
+      offset = (u16_t)(offset - p->len);
+ 8017f48:	69fb      	ldr	r3, [r7, #28]
+ 8017f4a:	895b      	ldrh	r3, [r3, #10]
+ 8017f4c:	88ba      	ldrh	r2, [r7, #4]
+ 8017f4e:	1ad3      	subs	r3, r2, r3
+ 8017f50:	80bb      	strh	r3, [r7, #4]
+ 8017f52:	e023      	b.n	8017f9c <pbuf_copy_partial+0xb8>
+    } else {
+      /* copy from this buffer. maybe only partially. */
+      buf_copy_len = (u16_t)(p->len - offset);
+ 8017f54:	69fb      	ldr	r3, [r7, #28]
+ 8017f56:	895a      	ldrh	r2, [r3, #10]
+ 8017f58:	88bb      	ldrh	r3, [r7, #4]
+ 8017f5a:	1ad3      	subs	r3, r2, r3
+ 8017f5c:	833b      	strh	r3, [r7, #24]
+      if (buf_copy_len > len) {
+ 8017f5e:	8b3a      	ldrh	r2, [r7, #24]
+ 8017f60:	88fb      	ldrh	r3, [r7, #6]
+ 8017f62:	429a      	cmp	r2, r3
+ 8017f64:	d901      	bls.n	8017f6a <pbuf_copy_partial+0x86>
+        buf_copy_len = len;
+ 8017f66:	88fb      	ldrh	r3, [r7, #6]
+ 8017f68:	833b      	strh	r3, [r7, #24]
+      }
+      /* copy the necessary parts of the buffer */
+      MEMCPY(&((char *)dataptr)[left], &((char *)p->payload)[offset], buf_copy_len);
+ 8017f6a:	8b7b      	ldrh	r3, [r7, #26]
+ 8017f6c:	68ba      	ldr	r2, [r7, #8]
+ 8017f6e:	18d0      	adds	r0, r2, r3
+ 8017f70:	69fb      	ldr	r3, [r7, #28]
+ 8017f72:	685a      	ldr	r2, [r3, #4]
+ 8017f74:	88bb      	ldrh	r3, [r7, #4]
+ 8017f76:	4413      	add	r3, r2
+ 8017f78:	8b3a      	ldrh	r2, [r7, #24]
+ 8017f7a:	4619      	mov	r1, r3
+ 8017f7c:	f009 ff33 	bl	8021de6 <memcpy>
+      copied_total = (u16_t)(copied_total + buf_copy_len);
+ 8017f80:	8afa      	ldrh	r2, [r7, #22]
+ 8017f82:	8b3b      	ldrh	r3, [r7, #24]
+ 8017f84:	4413      	add	r3, r2
+ 8017f86:	82fb      	strh	r3, [r7, #22]
+      left = (u16_t)(left + buf_copy_len);
+ 8017f88:	8b7a      	ldrh	r2, [r7, #26]
+ 8017f8a:	8b3b      	ldrh	r3, [r7, #24]
+ 8017f8c:	4413      	add	r3, r2
+ 8017f8e:	837b      	strh	r3, [r7, #26]
+      len = (u16_t)(len - buf_copy_len);
+ 8017f90:	88fa      	ldrh	r2, [r7, #6]
+ 8017f92:	8b3b      	ldrh	r3, [r7, #24]
+ 8017f94:	1ad3      	subs	r3, r2, r3
+ 8017f96:	80fb      	strh	r3, [r7, #6]
+      offset = 0;
+ 8017f98:	2300      	movs	r3, #0
+ 8017f9a:	80bb      	strh	r3, [r7, #4]
+  for (p = buf; len != 0 && p != NULL; p = p->next) {
+ 8017f9c:	69fb      	ldr	r3, [r7, #28]
+ 8017f9e:	681b      	ldr	r3, [r3, #0]
+ 8017fa0:	61fb      	str	r3, [r7, #28]
+ 8017fa2:	88fb      	ldrh	r3, [r7, #6]
+ 8017fa4:	2b00      	cmp	r3, #0
+ 8017fa6:	d002      	beq.n	8017fae <pbuf_copy_partial+0xca>
+ 8017fa8:	69fb      	ldr	r3, [r7, #28]
+ 8017faa:	2b00      	cmp	r3, #0
+ 8017fac:	d1c4      	bne.n	8017f38 <pbuf_copy_partial+0x54>
+    }
+  }
+  return copied_total;
+ 8017fae:	8afb      	ldrh	r3, [r7, #22]
+}
+ 8017fb0:	4618      	mov	r0, r3
+ 8017fb2:	3720      	adds	r7, #32
+ 8017fb4:	46bd      	mov	sp, r7
+ 8017fb6:	bd80      	pop	{r7, pc}
+ 8017fb8:	080246a8 	.word	0x080246a8
+ 8017fbc:	080249f0 	.word	0x080249f0
+ 8017fc0:	08024708 	.word	0x08024708
+ 8017fc4:	08024a10 	.word	0x08024a10
+
+08017fc8 <pbuf_clone>:
+ *
+ * @return a new pbuf or NULL if allocation fails
+ */
+struct pbuf *
+pbuf_clone(pbuf_layer layer, pbuf_type type, struct pbuf *p)
+{
+ 8017fc8:	b580      	push	{r7, lr}
+ 8017fca:	b084      	sub	sp, #16
+ 8017fcc:	af00      	add	r7, sp, #0
+ 8017fce:	4603      	mov	r3, r0
+ 8017fd0:	603a      	str	r2, [r7, #0]
+ 8017fd2:	71fb      	strb	r3, [r7, #7]
+ 8017fd4:	460b      	mov	r3, r1
+ 8017fd6:	80bb      	strh	r3, [r7, #4]
+  struct pbuf *q;
+  err_t err;
+  q = pbuf_alloc(layer, p->tot_len, type);
+ 8017fd8:	683b      	ldr	r3, [r7, #0]
+ 8017fda:	8919      	ldrh	r1, [r3, #8]
+ 8017fdc:	88ba      	ldrh	r2, [r7, #4]
+ 8017fde:	79fb      	ldrb	r3, [r7, #7]
+ 8017fe0:	4618      	mov	r0, r3
+ 8017fe2:	f7ff faa1 	bl	8017528 <pbuf_alloc>
+ 8017fe6:	60f8      	str	r0, [r7, #12]
+  if (q == NULL) {
+ 8017fe8:	68fb      	ldr	r3, [r7, #12]
+ 8017fea:	2b00      	cmp	r3, #0
+ 8017fec:	d101      	bne.n	8017ff2 <pbuf_clone+0x2a>
+    return NULL;
+ 8017fee:	2300      	movs	r3, #0
+ 8017ff0:	e011      	b.n	8018016 <pbuf_clone+0x4e>
+  }
+  err = pbuf_copy(q, p);
+ 8017ff2:	6839      	ldr	r1, [r7, #0]
+ 8017ff4:	68f8      	ldr	r0, [r7, #12]
+ 8017ff6:	f7ff fea3 	bl	8017d40 <pbuf_copy>
+ 8017ffa:	4603      	mov	r3, r0
+ 8017ffc:	72fb      	strb	r3, [r7, #11]
+  LWIP_UNUSED_ARG(err); /* in case of LWIP_NOASSERT */
+  LWIP_ASSERT("pbuf_copy failed", err == ERR_OK);
+ 8017ffe:	f997 300b 	ldrsb.w	r3, [r7, #11]
+ 8018002:	2b00      	cmp	r3, #0
+ 8018004:	d006      	beq.n	8018014 <pbuf_clone+0x4c>
+ 8018006:	4b06      	ldr	r3, [pc, #24]	; (8018020 <pbuf_clone+0x58>)
+ 8018008:	f240 5224 	movw	r2, #1316	; 0x524
+ 801800c:	4905      	ldr	r1, [pc, #20]	; (8018024 <pbuf_clone+0x5c>)
+ 801800e:	4806      	ldr	r0, [pc, #24]	; (8018028 <pbuf_clone+0x60>)
+ 8018010:	f009 fcba 	bl	8021988 <iprintf>
+  return q;
+ 8018014:	68fb      	ldr	r3, [r7, #12]
+}
+ 8018016:	4618      	mov	r0, r3
+ 8018018:	3710      	adds	r7, #16
+ 801801a:	46bd      	mov	sp, r7
+ 801801c:	bd80      	pop	{r7, pc}
+ 801801e:	bf00      	nop
+ 8018020:	080246a8 	.word	0x080246a8
+ 8018024:	08024b1c 	.word	0x08024b1c
+ 8018028:	08024708 	.word	0x08024708
+
+0801802c <tcp_init>:
+/**
+ * Initialize this module.
+ */
+void
+tcp_init(void)
+{
+ 801802c:	b580      	push	{r7, lr}
+ 801802e:	af00      	add	r7, sp, #0
+#ifdef LWIP_RAND
+  tcp_port = TCP_ENSURE_LOCAL_PORT_RANGE(LWIP_RAND());
+ 8018030:	f009 fb2e 	bl	8021690 <rand>
+ 8018034:	4603      	mov	r3, r0
+ 8018036:	b29b      	uxth	r3, r3
+ 8018038:	f3c3 030d 	ubfx	r3, r3, #0, #14
+ 801803c:	b29b      	uxth	r3, r3
+ 801803e:	f5a3 4380 	sub.w	r3, r3, #16384	; 0x4000
+ 8018042:	b29a      	uxth	r2, r3
+ 8018044:	4b01      	ldr	r3, [pc, #4]	; (801804c <tcp_init+0x20>)
+ 8018046:	801a      	strh	r2, [r3, #0]
+#endif /* LWIP_RAND */
+}
+ 8018048:	bf00      	nop
+ 801804a:	bd80      	pop	{r7, pc}
+ 801804c:	2400003c 	.word	0x2400003c
+
+08018050 <tcp_free>:
+
+/** Free a tcp pcb */
+void
+tcp_free(struct tcp_pcb *pcb)
+{
+ 8018050:	b580      	push	{r7, lr}
+ 8018052:	b082      	sub	sp, #8
+ 8018054:	af00      	add	r7, sp, #0
+ 8018056:	6078      	str	r0, [r7, #4]
+  LWIP_ASSERT("tcp_free: LISTEN", pcb->state != LISTEN);
+ 8018058:	687b      	ldr	r3, [r7, #4]
+ 801805a:	7d1b      	ldrb	r3, [r3, #20]
+ 801805c:	2b01      	cmp	r3, #1
+ 801805e:	d105      	bne.n	801806c <tcp_free+0x1c>
+ 8018060:	4b06      	ldr	r3, [pc, #24]	; (801807c <tcp_free+0x2c>)
+ 8018062:	22d4      	movs	r2, #212	; 0xd4
+ 8018064:	4906      	ldr	r1, [pc, #24]	; (8018080 <tcp_free+0x30>)
+ 8018066:	4807      	ldr	r0, [pc, #28]	; (8018084 <tcp_free+0x34>)
+ 8018068:	f009 fc8e 	bl	8021988 <iprintf>
+#if LWIP_TCP_PCB_NUM_EXT_ARGS
+  tcp_ext_arg_invoke_callbacks_destroyed(pcb->ext_args);
+#endif
+  memp_free(MEMP_TCP_PCB, pcb);
+ 801806c:	6879      	ldr	r1, [r7, #4]
+ 801806e:	2001      	movs	r0, #1
+ 8018070:	f7fe fda4 	bl	8016bbc <memp_free>
+}
+ 8018074:	bf00      	nop
+ 8018076:	3708      	adds	r7, #8
+ 8018078:	46bd      	mov	sp, r7
+ 801807a:	bd80      	pop	{r7, pc}
+ 801807c:	08024ba8 	.word	0x08024ba8
+ 8018080:	08024bd8 	.word	0x08024bd8
+ 8018084:	08024bec 	.word	0x08024bec
+
+08018088 <tcp_free_listen>:
+
+/** Free a tcp listen pcb */
+static void
+tcp_free_listen(struct tcp_pcb *pcb)
+{
+ 8018088:	b580      	push	{r7, lr}
+ 801808a:	b082      	sub	sp, #8
+ 801808c:	af00      	add	r7, sp, #0
+ 801808e:	6078      	str	r0, [r7, #4]
+  LWIP_ASSERT("tcp_free_listen: !LISTEN", pcb->state != LISTEN);
+ 8018090:	687b      	ldr	r3, [r7, #4]
+ 8018092:	7d1b      	ldrb	r3, [r3, #20]
+ 8018094:	2b01      	cmp	r3, #1
+ 8018096:	d105      	bne.n	80180a4 <tcp_free_listen+0x1c>
+ 8018098:	4b06      	ldr	r3, [pc, #24]	; (80180b4 <tcp_free_listen+0x2c>)
+ 801809a:	22df      	movs	r2, #223	; 0xdf
+ 801809c:	4906      	ldr	r1, [pc, #24]	; (80180b8 <tcp_free_listen+0x30>)
+ 801809e:	4807      	ldr	r0, [pc, #28]	; (80180bc <tcp_free_listen+0x34>)
+ 80180a0:	f009 fc72 	bl	8021988 <iprintf>
+#if LWIP_TCP_PCB_NUM_EXT_ARGS
+  tcp_ext_arg_invoke_callbacks_destroyed(pcb->ext_args);
+#endif
+  memp_free(MEMP_TCP_PCB_LISTEN, pcb);
+ 80180a4:	6879      	ldr	r1, [r7, #4]
+ 80180a6:	2002      	movs	r0, #2
+ 80180a8:	f7fe fd88 	bl	8016bbc <memp_free>
+}
+ 80180ac:	bf00      	nop
+ 80180ae:	3708      	adds	r7, #8
+ 80180b0:	46bd      	mov	sp, r7
+ 80180b2:	bd80      	pop	{r7, pc}
+ 80180b4:	08024ba8 	.word	0x08024ba8
+ 80180b8:	08024c14 	.word	0x08024c14
+ 80180bc:	08024bec 	.word	0x08024bec
+
+080180c0 <tcp_tmr>:
+/**
+ * Called periodically to dispatch TCP timers.
+ */
+void
+tcp_tmr(void)
+{
+ 80180c0:	b580      	push	{r7, lr}
+ 80180c2:	af00      	add	r7, sp, #0
+  /* Call tcp_fasttmr() every 250 ms */
+  tcp_fasttmr();
+ 80180c4:	f001 f8f6 	bl	80192b4 <tcp_fasttmr>
+
+  if (++tcp_timer & 1) {
+ 80180c8:	4b07      	ldr	r3, [pc, #28]	; (80180e8 <tcp_tmr+0x28>)
+ 80180ca:	781b      	ldrb	r3, [r3, #0]
+ 80180cc:	3301      	adds	r3, #1
+ 80180ce:	b2da      	uxtb	r2, r3
+ 80180d0:	4b05      	ldr	r3, [pc, #20]	; (80180e8 <tcp_tmr+0x28>)
+ 80180d2:	701a      	strb	r2, [r3, #0]
+ 80180d4:	4b04      	ldr	r3, [pc, #16]	; (80180e8 <tcp_tmr+0x28>)
+ 80180d6:	781b      	ldrb	r3, [r3, #0]
+ 80180d8:	f003 0301 	and.w	r3, r3, #1
+ 80180dc:	2b00      	cmp	r3, #0
+ 80180de:	d001      	beq.n	80180e4 <tcp_tmr+0x24>
+    /* Call tcp_slowtmr() every 500 ms, i.e., every other timer
+       tcp_tmr() is called. */
+    tcp_slowtmr();
+ 80180e0:	f000 fda8 	bl	8018c34 <tcp_slowtmr>
+  }
+}
+ 80180e4:	bf00      	nop
+ 80180e6:	bd80      	pop	{r7, pc}
+ 80180e8:	2401a495 	.word	0x2401a495
+
+080180ec <tcp_remove_listener>:
+/** Called when a listen pcb is closed. Iterates one pcb list and removes the
+ * closed listener pcb from pcb->listener if matching.
+ */
+static void
+tcp_remove_listener(struct tcp_pcb *list, struct tcp_pcb_listen *lpcb)
+{
+ 80180ec:	b580      	push	{r7, lr}
+ 80180ee:	b084      	sub	sp, #16
+ 80180f0:	af00      	add	r7, sp, #0
+ 80180f2:	6078      	str	r0, [r7, #4]
+ 80180f4:	6039      	str	r1, [r7, #0]
+  struct tcp_pcb *pcb;
+
+  LWIP_ASSERT("tcp_remove_listener: invalid listener", lpcb != NULL);
+ 80180f6:	683b      	ldr	r3, [r7, #0]
+ 80180f8:	2b00      	cmp	r3, #0
+ 80180fa:	d105      	bne.n	8018108 <tcp_remove_listener+0x1c>
+ 80180fc:	4b0d      	ldr	r3, [pc, #52]	; (8018134 <tcp_remove_listener+0x48>)
+ 80180fe:	22ff      	movs	r2, #255	; 0xff
+ 8018100:	490d      	ldr	r1, [pc, #52]	; (8018138 <tcp_remove_listener+0x4c>)
+ 8018102:	480e      	ldr	r0, [pc, #56]	; (801813c <tcp_remove_listener+0x50>)
+ 8018104:	f009 fc40 	bl	8021988 <iprintf>
+
+  for (pcb = list; pcb != NULL; pcb = pcb->next) {
+ 8018108:	687b      	ldr	r3, [r7, #4]
+ 801810a:	60fb      	str	r3, [r7, #12]
+ 801810c:	e00a      	b.n	8018124 <tcp_remove_listener+0x38>
+    if (pcb->listener == lpcb) {
+ 801810e:	68fb      	ldr	r3, [r7, #12]
+ 8018110:	6fdb      	ldr	r3, [r3, #124]	; 0x7c
+ 8018112:	683a      	ldr	r2, [r7, #0]
+ 8018114:	429a      	cmp	r2, r3
+ 8018116:	d102      	bne.n	801811e <tcp_remove_listener+0x32>
+      pcb->listener = NULL;
+ 8018118:	68fb      	ldr	r3, [r7, #12]
+ 801811a:	2200      	movs	r2, #0
+ 801811c:	67da      	str	r2, [r3, #124]	; 0x7c
+  for (pcb = list; pcb != NULL; pcb = pcb->next) {
+ 801811e:	68fb      	ldr	r3, [r7, #12]
+ 8018120:	68db      	ldr	r3, [r3, #12]
+ 8018122:	60fb      	str	r3, [r7, #12]
+ 8018124:	68fb      	ldr	r3, [r7, #12]
+ 8018126:	2b00      	cmp	r3, #0
+ 8018128:	d1f1      	bne.n	801810e <tcp_remove_listener+0x22>
+    }
+  }
+}
+ 801812a:	bf00      	nop
+ 801812c:	bf00      	nop
+ 801812e:	3710      	adds	r7, #16
+ 8018130:	46bd      	mov	sp, r7
+ 8018132:	bd80      	pop	{r7, pc}
+ 8018134:	08024ba8 	.word	0x08024ba8
+ 8018138:	08024c30 	.word	0x08024c30
+ 801813c:	08024bec 	.word	0x08024bec
+
+08018140 <tcp_listen_closed>:
+/** Called when a listen pcb is closed. Iterates all pcb lists and removes the
+ * closed listener pcb from pcb->listener if matching.
+ */
+static void
+tcp_listen_closed(struct tcp_pcb *pcb)
+{
+ 8018140:	b580      	push	{r7, lr}
+ 8018142:	b084      	sub	sp, #16
+ 8018144:	af00      	add	r7, sp, #0
+ 8018146:	6078      	str	r0, [r7, #4]
+#if LWIP_CALLBACK_API || TCP_LISTEN_BACKLOG
+  size_t i;
+  LWIP_ASSERT("pcb != NULL", pcb != NULL);
+ 8018148:	687b      	ldr	r3, [r7, #4]
+ 801814a:	2b00      	cmp	r3, #0
+ 801814c:	d106      	bne.n	801815c <tcp_listen_closed+0x1c>
+ 801814e:	4b14      	ldr	r3, [pc, #80]	; (80181a0 <tcp_listen_closed+0x60>)
+ 8018150:	f240 1211 	movw	r2, #273	; 0x111
+ 8018154:	4913      	ldr	r1, [pc, #76]	; (80181a4 <tcp_listen_closed+0x64>)
+ 8018156:	4814      	ldr	r0, [pc, #80]	; (80181a8 <tcp_listen_closed+0x68>)
+ 8018158:	f009 fc16 	bl	8021988 <iprintf>
+  LWIP_ASSERT("pcb->state == LISTEN", pcb->state == LISTEN);
+ 801815c:	687b      	ldr	r3, [r7, #4]
+ 801815e:	7d1b      	ldrb	r3, [r3, #20]
+ 8018160:	2b01      	cmp	r3, #1
+ 8018162:	d006      	beq.n	8018172 <tcp_listen_closed+0x32>
+ 8018164:	4b0e      	ldr	r3, [pc, #56]	; (80181a0 <tcp_listen_closed+0x60>)
+ 8018166:	f44f 7289 	mov.w	r2, #274	; 0x112
+ 801816a:	4910      	ldr	r1, [pc, #64]	; (80181ac <tcp_listen_closed+0x6c>)
+ 801816c:	480e      	ldr	r0, [pc, #56]	; (80181a8 <tcp_listen_closed+0x68>)
+ 801816e:	f009 fc0b 	bl	8021988 <iprintf>
+  for (i = 1; i < LWIP_ARRAYSIZE(tcp_pcb_lists); i++) {
+ 8018172:	2301      	movs	r3, #1
+ 8018174:	60fb      	str	r3, [r7, #12]
+ 8018176:	e00b      	b.n	8018190 <tcp_listen_closed+0x50>
+    tcp_remove_listener(*tcp_pcb_lists[i], (struct tcp_pcb_listen *)pcb);
+ 8018178:	4a0d      	ldr	r2, [pc, #52]	; (80181b0 <tcp_listen_closed+0x70>)
+ 801817a:	68fb      	ldr	r3, [r7, #12]
+ 801817c:	f852 3023 	ldr.w	r3, [r2, r3, lsl #2]
+ 8018180:	681b      	ldr	r3, [r3, #0]
+ 8018182:	6879      	ldr	r1, [r7, #4]
+ 8018184:	4618      	mov	r0, r3
+ 8018186:	f7ff ffb1 	bl	80180ec <tcp_remove_listener>
+  for (i = 1; i < LWIP_ARRAYSIZE(tcp_pcb_lists); i++) {
+ 801818a:	68fb      	ldr	r3, [r7, #12]
+ 801818c:	3301      	adds	r3, #1
+ 801818e:	60fb      	str	r3, [r7, #12]
+ 8018190:	68fb      	ldr	r3, [r7, #12]
+ 8018192:	2b03      	cmp	r3, #3
+ 8018194:	d9f0      	bls.n	8018178 <tcp_listen_closed+0x38>
+  }
+#endif
+  LWIP_UNUSED_ARG(pcb);
+}
+ 8018196:	bf00      	nop
+ 8018198:	bf00      	nop
+ 801819a:	3710      	adds	r7, #16
+ 801819c:	46bd      	mov	sp, r7
+ 801819e:	bd80      	pop	{r7, pc}
+ 80181a0:	08024ba8 	.word	0x08024ba8
+ 80181a4:	08024c58 	.word	0x08024c58
+ 80181a8:	08024bec 	.word	0x08024bec
+ 80181ac:	08024c64 	.word	0x08024c64
+ 80181b0:	08026cc4 	.word	0x08026cc4
+
+080181b4 <tcp_close_shutdown>:
+ * @return ERR_OK if connection has been closed
+ *         another err_t if closing failed and pcb is not freed
+ */
+static err_t
+tcp_close_shutdown(struct tcp_pcb *pcb, u8_t rst_on_unacked_data)
+{
+ 80181b4:	b5b0      	push	{r4, r5, r7, lr}
+ 80181b6:	b088      	sub	sp, #32
+ 80181b8:	af04      	add	r7, sp, #16
+ 80181ba:	6078      	str	r0, [r7, #4]
+ 80181bc:	460b      	mov	r3, r1
+ 80181be:	70fb      	strb	r3, [r7, #3]
+  LWIP_ASSERT("tcp_close_shutdown: invalid pcb", pcb != NULL);
+ 80181c0:	687b      	ldr	r3, [r7, #4]
+ 80181c2:	2b00      	cmp	r3, #0
+ 80181c4:	d106      	bne.n	80181d4 <tcp_close_shutdown+0x20>
+ 80181c6:	4b63      	ldr	r3, [pc, #396]	; (8018354 <tcp_close_shutdown+0x1a0>)
+ 80181c8:	f44f 72af 	mov.w	r2, #350	; 0x15e
+ 80181cc:	4962      	ldr	r1, [pc, #392]	; (8018358 <tcp_close_shutdown+0x1a4>)
+ 80181ce:	4863      	ldr	r0, [pc, #396]	; (801835c <tcp_close_shutdown+0x1a8>)
+ 80181d0:	f009 fbda 	bl	8021988 <iprintf>
+
+  if (rst_on_unacked_data && ((pcb->state == ESTABLISHED) || (pcb->state == CLOSE_WAIT))) {
+ 80181d4:	78fb      	ldrb	r3, [r7, #3]
+ 80181d6:	2b00      	cmp	r3, #0
+ 80181d8:	d067      	beq.n	80182aa <tcp_close_shutdown+0xf6>
+ 80181da:	687b      	ldr	r3, [r7, #4]
+ 80181dc:	7d1b      	ldrb	r3, [r3, #20]
+ 80181de:	2b04      	cmp	r3, #4
+ 80181e0:	d003      	beq.n	80181ea <tcp_close_shutdown+0x36>
+ 80181e2:	687b      	ldr	r3, [r7, #4]
+ 80181e4:	7d1b      	ldrb	r3, [r3, #20]
+ 80181e6:	2b07      	cmp	r3, #7
+ 80181e8:	d15f      	bne.n	80182aa <tcp_close_shutdown+0xf6>
+    if ((pcb->refused_data != NULL) || (pcb->rcv_wnd != TCP_WND_MAX(pcb))) {
+ 80181ea:	687b      	ldr	r3, [r7, #4]
+ 80181ec:	6f9b      	ldr	r3, [r3, #120]	; 0x78
+ 80181ee:	2b00      	cmp	r3, #0
+ 80181f0:	d105      	bne.n	80181fe <tcp_close_shutdown+0x4a>
+ 80181f2:	687b      	ldr	r3, [r7, #4]
+ 80181f4:	8d1b      	ldrh	r3, [r3, #40]	; 0x28
+ 80181f6:	f241 62d0 	movw	r2, #5840	; 0x16d0
+ 80181fa:	4293      	cmp	r3, r2
+ 80181fc:	d055      	beq.n	80182aa <tcp_close_shutdown+0xf6>
+      /* Not all data received by application, send RST to tell the remote
+         side about this. */
+      LWIP_ASSERT("pcb->flags & TF_RXCLOSED", pcb->flags & TF_RXCLOSED);
+ 80181fe:	687b      	ldr	r3, [r7, #4]
+ 8018200:	8b5b      	ldrh	r3, [r3, #26]
+ 8018202:	f003 0310 	and.w	r3, r3, #16
+ 8018206:	2b00      	cmp	r3, #0
+ 8018208:	d106      	bne.n	8018218 <tcp_close_shutdown+0x64>
+ 801820a:	4b52      	ldr	r3, [pc, #328]	; (8018354 <tcp_close_shutdown+0x1a0>)
+ 801820c:	f44f 72b2 	mov.w	r2, #356	; 0x164
+ 8018210:	4953      	ldr	r1, [pc, #332]	; (8018360 <tcp_close_shutdown+0x1ac>)
+ 8018212:	4852      	ldr	r0, [pc, #328]	; (801835c <tcp_close_shutdown+0x1a8>)
+ 8018214:	f009 fbb8 	bl	8021988 <iprintf>
+
+      /* don't call tcp_abort here: we must not deallocate the pcb since
+         that might not be expected when calling tcp_close */
+      tcp_rst(pcb, pcb->snd_nxt, pcb->rcv_nxt, &pcb->local_ip, &pcb->remote_ip,
+ 8018218:	687b      	ldr	r3, [r7, #4]
+ 801821a:	6d18      	ldr	r0, [r3, #80]	; 0x50
+ 801821c:	687b      	ldr	r3, [r7, #4]
+ 801821e:	6a5c      	ldr	r4, [r3, #36]	; 0x24
+ 8018220:	687d      	ldr	r5, [r7, #4]
+ 8018222:	687b      	ldr	r3, [r7, #4]
+ 8018224:	3304      	adds	r3, #4
+ 8018226:	687a      	ldr	r2, [r7, #4]
+ 8018228:	8ad2      	ldrh	r2, [r2, #22]
+ 801822a:	6879      	ldr	r1, [r7, #4]
+ 801822c:	8b09      	ldrh	r1, [r1, #24]
+ 801822e:	9102      	str	r1, [sp, #8]
+ 8018230:	9201      	str	r2, [sp, #4]
+ 8018232:	9300      	str	r3, [sp, #0]
+ 8018234:	462b      	mov	r3, r5
+ 8018236:	4622      	mov	r2, r4
+ 8018238:	4601      	mov	r1, r0
+ 801823a:	6878      	ldr	r0, [r7, #4]
+ 801823c:	f005 fe7e 	bl	801df3c <tcp_rst>
+              pcb->local_port, pcb->remote_port);
+
+      tcp_pcb_purge(pcb);
+ 8018240:	6878      	ldr	r0, [r7, #4]
+ 8018242:	f001 fbe9 	bl	8019a18 <tcp_pcb_purge>
+      TCP_RMV_ACTIVE(pcb);
+ 8018246:	4b47      	ldr	r3, [pc, #284]	; (8018364 <tcp_close_shutdown+0x1b0>)
+ 8018248:	681b      	ldr	r3, [r3, #0]
+ 801824a:	687a      	ldr	r2, [r7, #4]
+ 801824c:	429a      	cmp	r2, r3
+ 801824e:	d105      	bne.n	801825c <tcp_close_shutdown+0xa8>
+ 8018250:	4b44      	ldr	r3, [pc, #272]	; (8018364 <tcp_close_shutdown+0x1b0>)
+ 8018252:	681b      	ldr	r3, [r3, #0]
+ 8018254:	68db      	ldr	r3, [r3, #12]
+ 8018256:	4a43      	ldr	r2, [pc, #268]	; (8018364 <tcp_close_shutdown+0x1b0>)
+ 8018258:	6013      	str	r3, [r2, #0]
+ 801825a:	e013      	b.n	8018284 <tcp_close_shutdown+0xd0>
+ 801825c:	4b41      	ldr	r3, [pc, #260]	; (8018364 <tcp_close_shutdown+0x1b0>)
+ 801825e:	681b      	ldr	r3, [r3, #0]
+ 8018260:	60fb      	str	r3, [r7, #12]
+ 8018262:	e00c      	b.n	801827e <tcp_close_shutdown+0xca>
+ 8018264:	68fb      	ldr	r3, [r7, #12]
+ 8018266:	68db      	ldr	r3, [r3, #12]
+ 8018268:	687a      	ldr	r2, [r7, #4]
+ 801826a:	429a      	cmp	r2, r3
+ 801826c:	d104      	bne.n	8018278 <tcp_close_shutdown+0xc4>
+ 801826e:	687b      	ldr	r3, [r7, #4]
+ 8018270:	68da      	ldr	r2, [r3, #12]
+ 8018272:	68fb      	ldr	r3, [r7, #12]
+ 8018274:	60da      	str	r2, [r3, #12]
+ 8018276:	e005      	b.n	8018284 <tcp_close_shutdown+0xd0>
+ 8018278:	68fb      	ldr	r3, [r7, #12]
+ 801827a:	68db      	ldr	r3, [r3, #12]
+ 801827c:	60fb      	str	r3, [r7, #12]
+ 801827e:	68fb      	ldr	r3, [r7, #12]
+ 8018280:	2b00      	cmp	r3, #0
+ 8018282:	d1ef      	bne.n	8018264 <tcp_close_shutdown+0xb0>
+ 8018284:	687b      	ldr	r3, [r7, #4]
+ 8018286:	2200      	movs	r2, #0
+ 8018288:	60da      	str	r2, [r3, #12]
+ 801828a:	4b37      	ldr	r3, [pc, #220]	; (8018368 <tcp_close_shutdown+0x1b4>)
+ 801828c:	2201      	movs	r2, #1
+ 801828e:	701a      	strb	r2, [r3, #0]
+      /* Deallocate the pcb since we already sent a RST for it */
+      if (tcp_input_pcb == pcb) {
+ 8018290:	4b36      	ldr	r3, [pc, #216]	; (801836c <tcp_close_shutdown+0x1b8>)
+ 8018292:	681b      	ldr	r3, [r3, #0]
+ 8018294:	687a      	ldr	r2, [r7, #4]
+ 8018296:	429a      	cmp	r2, r3
+ 8018298:	d102      	bne.n	80182a0 <tcp_close_shutdown+0xec>
+        /* prevent using a deallocated pcb: free it from tcp_input later */
+        tcp_trigger_input_pcb_close();
+ 801829a:	f004 f887 	bl	801c3ac <tcp_trigger_input_pcb_close>
+ 801829e:	e002      	b.n	80182a6 <tcp_close_shutdown+0xf2>
+      } else {
+        tcp_free(pcb);
+ 80182a0:	6878      	ldr	r0, [r7, #4]
+ 80182a2:	f7ff fed5 	bl	8018050 <tcp_free>
+      }
+      return ERR_OK;
+ 80182a6:	2300      	movs	r3, #0
+ 80182a8:	e050      	b.n	801834c <tcp_close_shutdown+0x198>
+    }
+  }
+
+  /* - states which free the pcb are handled here,
+     - states which send FIN and change state are handled in tcp_close_shutdown_fin() */
+  switch (pcb->state) {
+ 80182aa:	687b      	ldr	r3, [r7, #4]
+ 80182ac:	7d1b      	ldrb	r3, [r3, #20]
+ 80182ae:	2b02      	cmp	r3, #2
+ 80182b0:	d03b      	beq.n	801832a <tcp_close_shutdown+0x176>
+ 80182b2:	2b02      	cmp	r3, #2
+ 80182b4:	dc44      	bgt.n	8018340 <tcp_close_shutdown+0x18c>
+ 80182b6:	2b00      	cmp	r3, #0
+ 80182b8:	d002      	beq.n	80182c0 <tcp_close_shutdown+0x10c>
+ 80182ba:	2b01      	cmp	r3, #1
+ 80182bc:	d02a      	beq.n	8018314 <tcp_close_shutdown+0x160>
+ 80182be:	e03f      	b.n	8018340 <tcp_close_shutdown+0x18c>
+       * and the user needs some way to free it should the need arise.
+       * Calling tcp_close() with a pcb that has already been closed, (i.e. twice)
+       * or for a pcb that has been used and then entered the CLOSED state
+       * is erroneous, but this should never happen as the pcb has in those cases
+       * been freed, and so any remaining handles are bogus. */
+      if (pcb->local_port != 0) {
+ 80182c0:	687b      	ldr	r3, [r7, #4]
+ 80182c2:	8adb      	ldrh	r3, [r3, #22]
+ 80182c4:	2b00      	cmp	r3, #0
+ 80182c6:	d021      	beq.n	801830c <tcp_close_shutdown+0x158>
+        TCP_RMV(&tcp_bound_pcbs, pcb);
+ 80182c8:	4b29      	ldr	r3, [pc, #164]	; (8018370 <tcp_close_shutdown+0x1bc>)
+ 80182ca:	681b      	ldr	r3, [r3, #0]
+ 80182cc:	687a      	ldr	r2, [r7, #4]
+ 80182ce:	429a      	cmp	r2, r3
+ 80182d0:	d105      	bne.n	80182de <tcp_close_shutdown+0x12a>
+ 80182d2:	4b27      	ldr	r3, [pc, #156]	; (8018370 <tcp_close_shutdown+0x1bc>)
+ 80182d4:	681b      	ldr	r3, [r3, #0]
+ 80182d6:	68db      	ldr	r3, [r3, #12]
+ 80182d8:	4a25      	ldr	r2, [pc, #148]	; (8018370 <tcp_close_shutdown+0x1bc>)
+ 80182da:	6013      	str	r3, [r2, #0]
+ 80182dc:	e013      	b.n	8018306 <tcp_close_shutdown+0x152>
+ 80182de:	4b24      	ldr	r3, [pc, #144]	; (8018370 <tcp_close_shutdown+0x1bc>)
+ 80182e0:	681b      	ldr	r3, [r3, #0]
+ 80182e2:	60bb      	str	r3, [r7, #8]
+ 80182e4:	e00c      	b.n	8018300 <tcp_close_shutdown+0x14c>
+ 80182e6:	68bb      	ldr	r3, [r7, #8]
+ 80182e8:	68db      	ldr	r3, [r3, #12]
+ 80182ea:	687a      	ldr	r2, [r7, #4]
+ 80182ec:	429a      	cmp	r2, r3
+ 80182ee:	d104      	bne.n	80182fa <tcp_close_shutdown+0x146>
+ 80182f0:	687b      	ldr	r3, [r7, #4]
+ 80182f2:	68da      	ldr	r2, [r3, #12]
+ 80182f4:	68bb      	ldr	r3, [r7, #8]
+ 80182f6:	60da      	str	r2, [r3, #12]
+ 80182f8:	e005      	b.n	8018306 <tcp_close_shutdown+0x152>
+ 80182fa:	68bb      	ldr	r3, [r7, #8]
+ 80182fc:	68db      	ldr	r3, [r3, #12]
+ 80182fe:	60bb      	str	r3, [r7, #8]
+ 8018300:	68bb      	ldr	r3, [r7, #8]
+ 8018302:	2b00      	cmp	r3, #0
+ 8018304:	d1ef      	bne.n	80182e6 <tcp_close_shutdown+0x132>
+ 8018306:	687b      	ldr	r3, [r7, #4]
+ 8018308:	2200      	movs	r2, #0
+ 801830a:	60da      	str	r2, [r3, #12]
+      }
+      tcp_free(pcb);
+ 801830c:	6878      	ldr	r0, [r7, #4]
+ 801830e:	f7ff fe9f 	bl	8018050 <tcp_free>
+      break;
+ 8018312:	e01a      	b.n	801834a <tcp_close_shutdown+0x196>
+    case LISTEN:
+      tcp_listen_closed(pcb);
+ 8018314:	6878      	ldr	r0, [r7, #4]
+ 8018316:	f7ff ff13 	bl	8018140 <tcp_listen_closed>
+      tcp_pcb_remove(&tcp_listen_pcbs.pcbs, pcb);
+ 801831a:	6879      	ldr	r1, [r7, #4]
+ 801831c:	4815      	ldr	r0, [pc, #84]	; (8018374 <tcp_close_shutdown+0x1c0>)
+ 801831e:	f001 fbcb 	bl	8019ab8 <tcp_pcb_remove>
+      tcp_free_listen(pcb);
+ 8018322:	6878      	ldr	r0, [r7, #4]
+ 8018324:	f7ff feb0 	bl	8018088 <tcp_free_listen>
+      break;
+ 8018328:	e00f      	b.n	801834a <tcp_close_shutdown+0x196>
+    case SYN_SENT:
+      TCP_PCB_REMOVE_ACTIVE(pcb);
+ 801832a:	6879      	ldr	r1, [r7, #4]
+ 801832c:	480d      	ldr	r0, [pc, #52]	; (8018364 <tcp_close_shutdown+0x1b0>)
+ 801832e:	f001 fbc3 	bl	8019ab8 <tcp_pcb_remove>
+ 8018332:	4b0d      	ldr	r3, [pc, #52]	; (8018368 <tcp_close_shutdown+0x1b4>)
+ 8018334:	2201      	movs	r2, #1
+ 8018336:	701a      	strb	r2, [r3, #0]
+      tcp_free(pcb);
+ 8018338:	6878      	ldr	r0, [r7, #4]
+ 801833a:	f7ff fe89 	bl	8018050 <tcp_free>
+      MIB2_STATS_INC(mib2.tcpattemptfails);
+      break;
+ 801833e:	e004      	b.n	801834a <tcp_close_shutdown+0x196>
+    default:
+      return tcp_close_shutdown_fin(pcb);
+ 8018340:	6878      	ldr	r0, [r7, #4]
+ 8018342:	f000 f819 	bl	8018378 <tcp_close_shutdown_fin>
+ 8018346:	4603      	mov	r3, r0
+ 8018348:	e000      	b.n	801834c <tcp_close_shutdown+0x198>
+  }
+  return ERR_OK;
+ 801834a:	2300      	movs	r3, #0
+}
+ 801834c:	4618      	mov	r0, r3
+ 801834e:	3710      	adds	r7, #16
+ 8018350:	46bd      	mov	sp, r7
+ 8018352:	bdb0      	pop	{r4, r5, r7, pc}
+ 8018354:	08024ba8 	.word	0x08024ba8
+ 8018358:	08024c7c 	.word	0x08024c7c
+ 801835c:	08024bec 	.word	0x08024bec
+ 8018360:	08024c9c 	.word	0x08024c9c
+ 8018364:	2401a48c 	.word	0x2401a48c
+ 8018368:	2401a494 	.word	0x2401a494
+ 801836c:	2401a4d0 	.word	0x2401a4d0
+ 8018370:	2401a484 	.word	0x2401a484
+ 8018374:	2401a488 	.word	0x2401a488
+
+08018378 <tcp_close_shutdown_fin>:
+
+static err_t
+tcp_close_shutdown_fin(struct tcp_pcb *pcb)
+{
+ 8018378:	b580      	push	{r7, lr}
+ 801837a:	b084      	sub	sp, #16
+ 801837c:	af00      	add	r7, sp, #0
+ 801837e:	6078      	str	r0, [r7, #4]
+  err_t err;
+  LWIP_ASSERT("pcb != NULL", pcb != NULL);
+ 8018380:	687b      	ldr	r3, [r7, #4]
+ 8018382:	2b00      	cmp	r3, #0
+ 8018384:	d106      	bne.n	8018394 <tcp_close_shutdown_fin+0x1c>
+ 8018386:	4b2e      	ldr	r3, [pc, #184]	; (8018440 <tcp_close_shutdown_fin+0xc8>)
+ 8018388:	f44f 72ce 	mov.w	r2, #412	; 0x19c
+ 801838c:	492d      	ldr	r1, [pc, #180]	; (8018444 <tcp_close_shutdown_fin+0xcc>)
+ 801838e:	482e      	ldr	r0, [pc, #184]	; (8018448 <tcp_close_shutdown_fin+0xd0>)
+ 8018390:	f009 fafa 	bl	8021988 <iprintf>
+
+  switch (pcb->state) {
+ 8018394:	687b      	ldr	r3, [r7, #4]
+ 8018396:	7d1b      	ldrb	r3, [r3, #20]
+ 8018398:	2b07      	cmp	r3, #7
+ 801839a:	d020      	beq.n	80183de <tcp_close_shutdown_fin+0x66>
+ 801839c:	2b07      	cmp	r3, #7
+ 801839e:	dc2b      	bgt.n	80183f8 <tcp_close_shutdown_fin+0x80>
+ 80183a0:	2b03      	cmp	r3, #3
+ 80183a2:	d002      	beq.n	80183aa <tcp_close_shutdown_fin+0x32>
+ 80183a4:	2b04      	cmp	r3, #4
+ 80183a6:	d00d      	beq.n	80183c4 <tcp_close_shutdown_fin+0x4c>
+ 80183a8:	e026      	b.n	80183f8 <tcp_close_shutdown_fin+0x80>
+    case SYN_RCVD:
+      err = tcp_send_fin(pcb);
+ 80183aa:	6878      	ldr	r0, [r7, #4]
+ 80183ac:	f004 fec8 	bl	801d140 <tcp_send_fin>
+ 80183b0:	4603      	mov	r3, r0
+ 80183b2:	73fb      	strb	r3, [r7, #15]
+      if (err == ERR_OK) {
+ 80183b4:	f997 300f 	ldrsb.w	r3, [r7, #15]
+ 80183b8:	2b00      	cmp	r3, #0
+ 80183ba:	d11f      	bne.n	80183fc <tcp_close_shutdown_fin+0x84>
+        tcp_backlog_accepted(pcb);
+        MIB2_STATS_INC(mib2.tcpattemptfails);
+        pcb->state = FIN_WAIT_1;
+ 80183bc:	687b      	ldr	r3, [r7, #4]
+ 80183be:	2205      	movs	r2, #5
+ 80183c0:	751a      	strb	r2, [r3, #20]
+      }
+      break;
+ 80183c2:	e01b      	b.n	80183fc <tcp_close_shutdown_fin+0x84>
+    case ESTABLISHED:
+      err = tcp_send_fin(pcb);
+ 80183c4:	6878      	ldr	r0, [r7, #4]
+ 80183c6:	f004 febb 	bl	801d140 <tcp_send_fin>
+ 80183ca:	4603      	mov	r3, r0
+ 80183cc:	73fb      	strb	r3, [r7, #15]
+      if (err == ERR_OK) {
+ 80183ce:	f997 300f 	ldrsb.w	r3, [r7, #15]
+ 80183d2:	2b00      	cmp	r3, #0
+ 80183d4:	d114      	bne.n	8018400 <tcp_close_shutdown_fin+0x88>
+        MIB2_STATS_INC(mib2.tcpestabresets);
+        pcb->state = FIN_WAIT_1;
+ 80183d6:	687b      	ldr	r3, [r7, #4]
+ 80183d8:	2205      	movs	r2, #5
+ 80183da:	751a      	strb	r2, [r3, #20]
+      }
+      break;
+ 80183dc:	e010      	b.n	8018400 <tcp_close_shutdown_fin+0x88>
+    case CLOSE_WAIT:
+      err = tcp_send_fin(pcb);
+ 80183de:	6878      	ldr	r0, [r7, #4]
+ 80183e0:	f004 feae 	bl	801d140 <tcp_send_fin>
+ 80183e4:	4603      	mov	r3, r0
+ 80183e6:	73fb      	strb	r3, [r7, #15]
+      if (err == ERR_OK) {
+ 80183e8:	f997 300f 	ldrsb.w	r3, [r7, #15]
+ 80183ec:	2b00      	cmp	r3, #0
+ 80183ee:	d109      	bne.n	8018404 <tcp_close_shutdown_fin+0x8c>
+        MIB2_STATS_INC(mib2.tcpestabresets);
+        pcb->state = LAST_ACK;
+ 80183f0:	687b      	ldr	r3, [r7, #4]
+ 80183f2:	2209      	movs	r2, #9
+ 80183f4:	751a      	strb	r2, [r3, #20]
+      }
+      break;
+ 80183f6:	e005      	b.n	8018404 <tcp_close_shutdown_fin+0x8c>
+    default:
+      /* Has already been closed, do nothing. */
+      return ERR_OK;
+ 80183f8:	2300      	movs	r3, #0
+ 80183fa:	e01c      	b.n	8018436 <tcp_close_shutdown_fin+0xbe>
+      break;
+ 80183fc:	bf00      	nop
+ 80183fe:	e002      	b.n	8018406 <tcp_close_shutdown_fin+0x8e>
+      break;
+ 8018400:	bf00      	nop
+ 8018402:	e000      	b.n	8018406 <tcp_close_shutdown_fin+0x8e>
+      break;
+ 8018404:	bf00      	nop
+  }
+
+  if (err == ERR_OK) {
+ 8018406:	f997 300f 	ldrsb.w	r3, [r7, #15]
+ 801840a:	2b00      	cmp	r3, #0
+ 801840c:	d103      	bne.n	8018416 <tcp_close_shutdown_fin+0x9e>
+    /* To ensure all data has been sent when tcp_close returns, we have
+       to make sure tcp_output doesn't fail.
+       Since we don't really have to ensure all data has been sent when tcp_close
+       returns (unsent data is sent from tcp timer functions, also), we don't care
+       for the return value of tcp_output for now. */
+    tcp_output(pcb);
+ 801840e:	6878      	ldr	r0, [r7, #4]
+ 8018410:	f004 ffd4 	bl	801d3bc <tcp_output>
+ 8018414:	e00d      	b.n	8018432 <tcp_close_shutdown_fin+0xba>
+  } else if (err == ERR_MEM) {
+ 8018416:	f997 300f 	ldrsb.w	r3, [r7, #15]
+ 801841a:	f1b3 3fff 	cmp.w	r3, #4294967295
+ 801841e:	d108      	bne.n	8018432 <tcp_close_shutdown_fin+0xba>
+    /* Mark this pcb for closing. Closing is retried from tcp_tmr. */
+    tcp_set_flags(pcb, TF_CLOSEPEND);
+ 8018420:	687b      	ldr	r3, [r7, #4]
+ 8018422:	8b5b      	ldrh	r3, [r3, #26]
+ 8018424:	f043 0308 	orr.w	r3, r3, #8
+ 8018428:	b29a      	uxth	r2, r3
+ 801842a:	687b      	ldr	r3, [r7, #4]
+ 801842c:	835a      	strh	r2, [r3, #26]
+    /* We have to return ERR_OK from here to indicate to the callers that this
+       pcb should not be used any more as it will be freed soon via tcp_tmr.
+       This is OK here since sending FIN does not guarantee a time frime for
+       actually freeing the pcb, either (it is left in closure states for
+       remote ACK or timeout) */
+    return ERR_OK;
+ 801842e:	2300      	movs	r3, #0
+ 8018430:	e001      	b.n	8018436 <tcp_close_shutdown_fin+0xbe>
+  }
+  return err;
+ 8018432:	f997 300f 	ldrsb.w	r3, [r7, #15]
+}
+ 8018436:	4618      	mov	r0, r3
+ 8018438:	3710      	adds	r7, #16
+ 801843a:	46bd      	mov	sp, r7
+ 801843c:	bd80      	pop	{r7, pc}
+ 801843e:	bf00      	nop
+ 8018440:	08024ba8 	.word	0x08024ba8
+ 8018444:	08024c58 	.word	0x08024c58
+ 8018448:	08024bec 	.word	0x08024bec
+
+0801844c <tcp_close>:
+ * @return ERR_OK if connection has been closed
+ *         another err_t if closing failed and pcb is not freed
+ */
+err_t
+tcp_close(struct tcp_pcb *pcb)
+{
+ 801844c:	b580      	push	{r7, lr}
+ 801844e:	b082      	sub	sp, #8
+ 8018450:	af00      	add	r7, sp, #0
+ 8018452:	6078      	str	r0, [r7, #4]
+  LWIP_ASSERT_CORE_LOCKED();
+
+  LWIP_ERROR("tcp_close: invalid pcb", pcb != NULL, return ERR_ARG);
+ 8018454:	687b      	ldr	r3, [r7, #4]
+ 8018456:	2b00      	cmp	r3, #0
+ 8018458:	d109      	bne.n	801846e <tcp_close+0x22>
+ 801845a:	4b0f      	ldr	r3, [pc, #60]	; (8018498 <tcp_close+0x4c>)
+ 801845c:	f44f 72f4 	mov.w	r2, #488	; 0x1e8
+ 8018460:	490e      	ldr	r1, [pc, #56]	; (801849c <tcp_close+0x50>)
+ 8018462:	480f      	ldr	r0, [pc, #60]	; (80184a0 <tcp_close+0x54>)
+ 8018464:	f009 fa90 	bl	8021988 <iprintf>
+ 8018468:	f06f 030f 	mvn.w	r3, #15
+ 801846c:	e00f      	b.n	801848e <tcp_close+0x42>
+  LWIP_DEBUGF(TCP_DEBUG, ("tcp_close: closing in "));
+
+  tcp_debug_print_state(pcb->state);
+
+  if (pcb->state != LISTEN) {
+ 801846e:	687b      	ldr	r3, [r7, #4]
+ 8018470:	7d1b      	ldrb	r3, [r3, #20]
+ 8018472:	2b01      	cmp	r3, #1
+ 8018474:	d006      	beq.n	8018484 <tcp_close+0x38>
+    /* Set a flag not to receive any more data... */
+    tcp_set_flags(pcb, TF_RXCLOSED);
+ 8018476:	687b      	ldr	r3, [r7, #4]
+ 8018478:	8b5b      	ldrh	r3, [r3, #26]
+ 801847a:	f043 0310 	orr.w	r3, r3, #16
+ 801847e:	b29a      	uxth	r2, r3
+ 8018480:	687b      	ldr	r3, [r7, #4]
+ 8018482:	835a      	strh	r2, [r3, #26]
+  }
+  /* ... and close */
+  return tcp_close_shutdown(pcb, 1);
+ 8018484:	2101      	movs	r1, #1
+ 8018486:	6878      	ldr	r0, [r7, #4]
+ 8018488:	f7ff fe94 	bl	80181b4 <tcp_close_shutdown>
+ 801848c:	4603      	mov	r3, r0
+}
+ 801848e:	4618      	mov	r0, r3
+ 8018490:	3708      	adds	r7, #8
+ 8018492:	46bd      	mov	sp, r7
+ 8018494:	bd80      	pop	{r7, pc}
+ 8018496:	bf00      	nop
+ 8018498:	08024ba8 	.word	0x08024ba8
+ 801849c:	08024cb8 	.word	0x08024cb8
+ 80184a0:	08024bec 	.word	0x08024bec
+
+080184a4 <tcp_shutdown>:
+ * @return ERR_OK if shutdown succeeded (or the PCB has already been shut down)
+ *         another err_t on error.
+ */
+err_t
+tcp_shutdown(struct tcp_pcb *pcb, int shut_rx, int shut_tx)
+{
+ 80184a4:	b580      	push	{r7, lr}
+ 80184a6:	b084      	sub	sp, #16
+ 80184a8:	af00      	add	r7, sp, #0
+ 80184aa:	60f8      	str	r0, [r7, #12]
+ 80184ac:	60b9      	str	r1, [r7, #8]
+ 80184ae:	607a      	str	r2, [r7, #4]
+  LWIP_ASSERT_CORE_LOCKED();
+
+  LWIP_ERROR("tcp_shutdown: invalid pcb", pcb != NULL, return ERR_ARG);
+ 80184b0:	68fb      	ldr	r3, [r7, #12]
+ 80184b2:	2b00      	cmp	r3, #0
+ 80184b4:	d109      	bne.n	80184ca <tcp_shutdown+0x26>
+ 80184b6:	4b26      	ldr	r3, [pc, #152]	; (8018550 <tcp_shutdown+0xac>)
+ 80184b8:	f240 2207 	movw	r2, #519	; 0x207
+ 80184bc:	4925      	ldr	r1, [pc, #148]	; (8018554 <tcp_shutdown+0xb0>)
+ 80184be:	4826      	ldr	r0, [pc, #152]	; (8018558 <tcp_shutdown+0xb4>)
+ 80184c0:	f009 fa62 	bl	8021988 <iprintf>
+ 80184c4:	f06f 030f 	mvn.w	r3, #15
+ 80184c8:	e03d      	b.n	8018546 <tcp_shutdown+0xa2>
+
+  if (pcb->state == LISTEN) {
+ 80184ca:	68fb      	ldr	r3, [r7, #12]
+ 80184cc:	7d1b      	ldrb	r3, [r3, #20]
+ 80184ce:	2b01      	cmp	r3, #1
+ 80184d0:	d102      	bne.n	80184d8 <tcp_shutdown+0x34>
+    return ERR_CONN;
+ 80184d2:	f06f 030a 	mvn.w	r3, #10
+ 80184d6:	e036      	b.n	8018546 <tcp_shutdown+0xa2>
+  }
+  if (shut_rx) {
+ 80184d8:	68bb      	ldr	r3, [r7, #8]
+ 80184da:	2b00      	cmp	r3, #0
+ 80184dc:	d01b      	beq.n	8018516 <tcp_shutdown+0x72>
+    /* shut down the receive side: set a flag not to receive any more data... */
+    tcp_set_flags(pcb, TF_RXCLOSED);
+ 80184de:	68fb      	ldr	r3, [r7, #12]
+ 80184e0:	8b5b      	ldrh	r3, [r3, #26]
+ 80184e2:	f043 0310 	orr.w	r3, r3, #16
+ 80184e6:	b29a      	uxth	r2, r3
+ 80184e8:	68fb      	ldr	r3, [r7, #12]
+ 80184ea:	835a      	strh	r2, [r3, #26]
+    if (shut_tx) {
+ 80184ec:	687b      	ldr	r3, [r7, #4]
+ 80184ee:	2b00      	cmp	r3, #0
+ 80184f0:	d005      	beq.n	80184fe <tcp_shutdown+0x5a>
+      /* shutting down the tx AND rx side is the same as closing for the raw API */
+      return tcp_close_shutdown(pcb, 1);
+ 80184f2:	2101      	movs	r1, #1
+ 80184f4:	68f8      	ldr	r0, [r7, #12]
+ 80184f6:	f7ff fe5d 	bl	80181b4 <tcp_close_shutdown>
+ 80184fa:	4603      	mov	r3, r0
+ 80184fc:	e023      	b.n	8018546 <tcp_shutdown+0xa2>
+    }
+    /* ... and free buffered data */
+    if (pcb->refused_data != NULL) {
+ 80184fe:	68fb      	ldr	r3, [r7, #12]
+ 8018500:	6f9b      	ldr	r3, [r3, #120]	; 0x78
+ 8018502:	2b00      	cmp	r3, #0
+ 8018504:	d007      	beq.n	8018516 <tcp_shutdown+0x72>
+      pbuf_free(pcb->refused_data);
+ 8018506:	68fb      	ldr	r3, [r7, #12]
+ 8018508:	6f9b      	ldr	r3, [r3, #120]	; 0x78
+ 801850a:	4618      	mov	r0, r3
+ 801850c:	f7ff faf4 	bl	8017af8 <pbuf_free>
+      pcb->refused_data = NULL;
+ 8018510:	68fb      	ldr	r3, [r7, #12]
+ 8018512:	2200      	movs	r2, #0
+ 8018514:	679a      	str	r2, [r3, #120]	; 0x78
+    }
+  }
+  if (shut_tx) {
+ 8018516:	687b      	ldr	r3, [r7, #4]
+ 8018518:	2b00      	cmp	r3, #0
+ 801851a:	d013      	beq.n	8018544 <tcp_shutdown+0xa0>
+    /* This can't happen twice since if it succeeds, the pcb's state is changed.
+       Only close in these states as the others directly deallocate the PCB */
+    switch (pcb->state) {
+ 801851c:	68fb      	ldr	r3, [r7, #12]
+ 801851e:	7d1b      	ldrb	r3, [r3, #20]
+ 8018520:	2b04      	cmp	r3, #4
+ 8018522:	dc02      	bgt.n	801852a <tcp_shutdown+0x86>
+ 8018524:	2b03      	cmp	r3, #3
+ 8018526:	da02      	bge.n	801852e <tcp_shutdown+0x8a>
+ 8018528:	e009      	b.n	801853e <tcp_shutdown+0x9a>
+ 801852a:	2b07      	cmp	r3, #7
+ 801852c:	d107      	bne.n	801853e <tcp_shutdown+0x9a>
+      case SYN_RCVD:
+      case ESTABLISHED:
+      case CLOSE_WAIT:
+        return tcp_close_shutdown(pcb, (u8_t)shut_rx);
+ 801852e:	68bb      	ldr	r3, [r7, #8]
+ 8018530:	b2db      	uxtb	r3, r3
+ 8018532:	4619      	mov	r1, r3
+ 8018534:	68f8      	ldr	r0, [r7, #12]
+ 8018536:	f7ff fe3d 	bl	80181b4 <tcp_close_shutdown>
+ 801853a:	4603      	mov	r3, r0
+ 801853c:	e003      	b.n	8018546 <tcp_shutdown+0xa2>
+      default:
+        /* Not (yet?) connected, cannot shutdown the TX side as that would bring us
+          into CLOSED state, where the PCB is deallocated. */
+        return ERR_CONN;
+ 801853e:	f06f 030a 	mvn.w	r3, #10
+ 8018542:	e000      	b.n	8018546 <tcp_shutdown+0xa2>
+    }
+  }
+  return ERR_OK;
+ 8018544:	2300      	movs	r3, #0
+}
+ 8018546:	4618      	mov	r0, r3
+ 8018548:	3710      	adds	r7, #16
+ 801854a:	46bd      	mov	sp, r7
+ 801854c:	bd80      	pop	{r7, pc}
+ 801854e:	bf00      	nop
+ 8018550:	08024ba8 	.word	0x08024ba8
+ 8018554:	08024cd0 	.word	0x08024cd0
+ 8018558:	08024bec 	.word	0x08024bec
+
+0801855c <tcp_abandon>:
+ * @param pcb the tcp_pcb to abort
+ * @param reset boolean to indicate whether a reset should be sent
+ */
+void
+tcp_abandon(struct tcp_pcb *pcb, int reset)
+{
+ 801855c:	b580      	push	{r7, lr}
+ 801855e:	b08e      	sub	sp, #56	; 0x38
+ 8018560:	af04      	add	r7, sp, #16
+ 8018562:	6078      	str	r0, [r7, #4]
+ 8018564:	6039      	str	r1, [r7, #0]
+#endif /* LWIP_CALLBACK_API */
+  void *errf_arg;
+
+  LWIP_ASSERT_CORE_LOCKED();
+
+  LWIP_ERROR("tcp_abandon: invalid pcb", pcb != NULL, return);
+ 8018566:	687b      	ldr	r3, [r7, #4]
+ 8018568:	2b00      	cmp	r3, #0
+ 801856a:	d107      	bne.n	801857c <tcp_abandon+0x20>
+ 801856c:	4b52      	ldr	r3, [pc, #328]	; (80186b8 <tcp_abandon+0x15c>)
+ 801856e:	f240 223d 	movw	r2, #573	; 0x23d
+ 8018572:	4952      	ldr	r1, [pc, #328]	; (80186bc <tcp_abandon+0x160>)
+ 8018574:	4852      	ldr	r0, [pc, #328]	; (80186c0 <tcp_abandon+0x164>)
+ 8018576:	f009 fa07 	bl	8021988 <iprintf>
+ 801857a:	e099      	b.n	80186b0 <tcp_abandon+0x154>
+
+  /* pcb->state LISTEN not allowed here */
+  LWIP_ASSERT("don't call tcp_abort/tcp_abandon for listen-pcbs",
+ 801857c:	687b      	ldr	r3, [r7, #4]
+ 801857e:	7d1b      	ldrb	r3, [r3, #20]
+ 8018580:	2b01      	cmp	r3, #1
+ 8018582:	d106      	bne.n	8018592 <tcp_abandon+0x36>
+ 8018584:	4b4c      	ldr	r3, [pc, #304]	; (80186b8 <tcp_abandon+0x15c>)
+ 8018586:	f44f 7210 	mov.w	r2, #576	; 0x240
+ 801858a:	494e      	ldr	r1, [pc, #312]	; (80186c4 <tcp_abandon+0x168>)
+ 801858c:	484c      	ldr	r0, [pc, #304]	; (80186c0 <tcp_abandon+0x164>)
+ 801858e:	f009 f9fb 	bl	8021988 <iprintf>
+              pcb->state != LISTEN);
+  /* Figure out on which TCP PCB list we are, and remove us. If we
+     are in an active state, call the receive function associated with
+     the PCB with a NULL argument, and send an RST to the remote end. */
+  if (pcb->state == TIME_WAIT) {
+ 8018592:	687b      	ldr	r3, [r7, #4]
+ 8018594:	7d1b      	ldrb	r3, [r3, #20]
+ 8018596:	2b0a      	cmp	r3, #10
+ 8018598:	d107      	bne.n	80185aa <tcp_abandon+0x4e>
+    tcp_pcb_remove(&tcp_tw_pcbs, pcb);
+ 801859a:	6879      	ldr	r1, [r7, #4]
+ 801859c:	484a      	ldr	r0, [pc, #296]	; (80186c8 <tcp_abandon+0x16c>)
+ 801859e:	f001 fa8b 	bl	8019ab8 <tcp_pcb_remove>
+    tcp_free(pcb);
+ 80185a2:	6878      	ldr	r0, [r7, #4]
+ 80185a4:	f7ff fd54 	bl	8018050 <tcp_free>
+ 80185a8:	e082      	b.n	80186b0 <tcp_abandon+0x154>
+  } else {
+    int send_rst = 0;
+ 80185aa:	2300      	movs	r3, #0
+ 80185ac:	627b      	str	r3, [r7, #36]	; 0x24
+    u16_t local_port = 0;
+ 80185ae:	2300      	movs	r3, #0
+ 80185b0:	847b      	strh	r3, [r7, #34]	; 0x22
+    enum tcp_state last_state;
+    seqno = pcb->snd_nxt;
+ 80185b2:	687b      	ldr	r3, [r7, #4]
+ 80185b4:	6d1b      	ldr	r3, [r3, #80]	; 0x50
+ 80185b6:	61bb      	str	r3, [r7, #24]
+    ackno = pcb->rcv_nxt;
+ 80185b8:	687b      	ldr	r3, [r7, #4]
+ 80185ba:	6a5b      	ldr	r3, [r3, #36]	; 0x24
+ 80185bc:	617b      	str	r3, [r7, #20]
+#if LWIP_CALLBACK_API
+    errf = pcb->errf;
+ 80185be:	687b      	ldr	r3, [r7, #4]
+ 80185c0:	f8d3 3090 	ldr.w	r3, [r3, #144]	; 0x90
+ 80185c4:	613b      	str	r3, [r7, #16]
+#endif /* LWIP_CALLBACK_API */
+    errf_arg = pcb->callback_arg;
+ 80185c6:	687b      	ldr	r3, [r7, #4]
+ 80185c8:	691b      	ldr	r3, [r3, #16]
+ 80185ca:	60fb      	str	r3, [r7, #12]
+    if (pcb->state == CLOSED) {
+ 80185cc:	687b      	ldr	r3, [r7, #4]
+ 80185ce:	7d1b      	ldrb	r3, [r3, #20]
+ 80185d0:	2b00      	cmp	r3, #0
+ 80185d2:	d126      	bne.n	8018622 <tcp_abandon+0xc6>
+      if (pcb->local_port != 0) {
+ 80185d4:	687b      	ldr	r3, [r7, #4]
+ 80185d6:	8adb      	ldrh	r3, [r3, #22]
+ 80185d8:	2b00      	cmp	r3, #0
+ 80185da:	d02e      	beq.n	801863a <tcp_abandon+0xde>
+        /* bound, not yet opened */
+        TCP_RMV(&tcp_bound_pcbs, pcb);
+ 80185dc:	4b3b      	ldr	r3, [pc, #236]	; (80186cc <tcp_abandon+0x170>)
+ 80185de:	681b      	ldr	r3, [r3, #0]
+ 80185e0:	687a      	ldr	r2, [r7, #4]
+ 80185e2:	429a      	cmp	r2, r3
+ 80185e4:	d105      	bne.n	80185f2 <tcp_abandon+0x96>
+ 80185e6:	4b39      	ldr	r3, [pc, #228]	; (80186cc <tcp_abandon+0x170>)
+ 80185e8:	681b      	ldr	r3, [r3, #0]
+ 80185ea:	68db      	ldr	r3, [r3, #12]
+ 80185ec:	4a37      	ldr	r2, [pc, #220]	; (80186cc <tcp_abandon+0x170>)
+ 80185ee:	6013      	str	r3, [r2, #0]
+ 80185f0:	e013      	b.n	801861a <tcp_abandon+0xbe>
+ 80185f2:	4b36      	ldr	r3, [pc, #216]	; (80186cc <tcp_abandon+0x170>)
+ 80185f4:	681b      	ldr	r3, [r3, #0]
+ 80185f6:	61fb      	str	r3, [r7, #28]
+ 80185f8:	e00c      	b.n	8018614 <tcp_abandon+0xb8>
+ 80185fa:	69fb      	ldr	r3, [r7, #28]
+ 80185fc:	68db      	ldr	r3, [r3, #12]
+ 80185fe:	687a      	ldr	r2, [r7, #4]
+ 8018600:	429a      	cmp	r2, r3
+ 8018602:	d104      	bne.n	801860e <tcp_abandon+0xb2>
+ 8018604:	687b      	ldr	r3, [r7, #4]
+ 8018606:	68da      	ldr	r2, [r3, #12]
+ 8018608:	69fb      	ldr	r3, [r7, #28]
+ 801860a:	60da      	str	r2, [r3, #12]
+ 801860c:	e005      	b.n	801861a <tcp_abandon+0xbe>
+ 801860e:	69fb      	ldr	r3, [r7, #28]
+ 8018610:	68db      	ldr	r3, [r3, #12]
+ 8018612:	61fb      	str	r3, [r7, #28]
+ 8018614:	69fb      	ldr	r3, [r7, #28]
+ 8018616:	2b00      	cmp	r3, #0
+ 8018618:	d1ef      	bne.n	80185fa <tcp_abandon+0x9e>
+ 801861a:	687b      	ldr	r3, [r7, #4]
+ 801861c:	2200      	movs	r2, #0
+ 801861e:	60da      	str	r2, [r3, #12]
+ 8018620:	e00b      	b.n	801863a <tcp_abandon+0xde>
+      }
+    } else {
+      send_rst = reset;
+ 8018622:	683b      	ldr	r3, [r7, #0]
+ 8018624:	627b      	str	r3, [r7, #36]	; 0x24
+      local_port = pcb->local_port;
+ 8018626:	687b      	ldr	r3, [r7, #4]
+ 8018628:	8adb      	ldrh	r3, [r3, #22]
+ 801862a:	847b      	strh	r3, [r7, #34]	; 0x22
+      TCP_PCB_REMOVE_ACTIVE(pcb);
+ 801862c:	6879      	ldr	r1, [r7, #4]
+ 801862e:	4828      	ldr	r0, [pc, #160]	; (80186d0 <tcp_abandon+0x174>)
+ 8018630:	f001 fa42 	bl	8019ab8 <tcp_pcb_remove>
+ 8018634:	4b27      	ldr	r3, [pc, #156]	; (80186d4 <tcp_abandon+0x178>)
+ 8018636:	2201      	movs	r2, #1
+ 8018638:	701a      	strb	r2, [r3, #0]
+    }
+    if (pcb->unacked != NULL) {
+ 801863a:	687b      	ldr	r3, [r7, #4]
+ 801863c:	6f1b      	ldr	r3, [r3, #112]	; 0x70
+ 801863e:	2b00      	cmp	r3, #0
+ 8018640:	d004      	beq.n	801864c <tcp_abandon+0xf0>
+      tcp_segs_free(pcb->unacked);
+ 8018642:	687b      	ldr	r3, [r7, #4]
+ 8018644:	6f1b      	ldr	r3, [r3, #112]	; 0x70
+ 8018646:	4618      	mov	r0, r3
+ 8018648:	f000 ff16 	bl	8019478 <tcp_segs_free>
+    }
+    if (pcb->unsent != NULL) {
+ 801864c:	687b      	ldr	r3, [r7, #4]
+ 801864e:	6edb      	ldr	r3, [r3, #108]	; 0x6c
+ 8018650:	2b00      	cmp	r3, #0
+ 8018652:	d004      	beq.n	801865e <tcp_abandon+0x102>
+      tcp_segs_free(pcb->unsent);
+ 8018654:	687b      	ldr	r3, [r7, #4]
+ 8018656:	6edb      	ldr	r3, [r3, #108]	; 0x6c
+ 8018658:	4618      	mov	r0, r3
+ 801865a:	f000 ff0d 	bl	8019478 <tcp_segs_free>
+    }
+#if TCP_QUEUE_OOSEQ
+    if (pcb->ooseq != NULL) {
+ 801865e:	687b      	ldr	r3, [r7, #4]
+ 8018660:	6f5b      	ldr	r3, [r3, #116]	; 0x74
+ 8018662:	2b00      	cmp	r3, #0
+ 8018664:	d004      	beq.n	8018670 <tcp_abandon+0x114>
+      tcp_segs_free(pcb->ooseq);
+ 8018666:	687b      	ldr	r3, [r7, #4]
+ 8018668:	6f5b      	ldr	r3, [r3, #116]	; 0x74
+ 801866a:	4618      	mov	r0, r3
+ 801866c:	f000 ff04 	bl	8019478 <tcp_segs_free>
+    }
+#endif /* TCP_QUEUE_OOSEQ */
+    tcp_backlog_accepted(pcb);
+    if (send_rst) {
+ 8018670:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 8018672:	2b00      	cmp	r3, #0
+ 8018674:	d00e      	beq.n	8018694 <tcp_abandon+0x138>
+      LWIP_DEBUGF(TCP_RST_DEBUG, ("tcp_abandon: sending RST\n"));
+      tcp_rst(pcb, seqno, ackno, &pcb->local_ip, &pcb->remote_ip, local_port, pcb->remote_port);
+ 8018676:	6879      	ldr	r1, [r7, #4]
+ 8018678:	687b      	ldr	r3, [r7, #4]
+ 801867a:	3304      	adds	r3, #4
+ 801867c:	687a      	ldr	r2, [r7, #4]
+ 801867e:	8b12      	ldrh	r2, [r2, #24]
+ 8018680:	9202      	str	r2, [sp, #8]
+ 8018682:	8c7a      	ldrh	r2, [r7, #34]	; 0x22
+ 8018684:	9201      	str	r2, [sp, #4]
+ 8018686:	9300      	str	r3, [sp, #0]
+ 8018688:	460b      	mov	r3, r1
+ 801868a:	697a      	ldr	r2, [r7, #20]
+ 801868c:	69b9      	ldr	r1, [r7, #24]
+ 801868e:	6878      	ldr	r0, [r7, #4]
+ 8018690:	f005 fc54 	bl	801df3c <tcp_rst>
+    }
+    last_state = pcb->state;
+ 8018694:	687b      	ldr	r3, [r7, #4]
+ 8018696:	7d1b      	ldrb	r3, [r3, #20]
+ 8018698:	72fb      	strb	r3, [r7, #11]
+    tcp_free(pcb);
+ 801869a:	6878      	ldr	r0, [r7, #4]
+ 801869c:	f7ff fcd8 	bl	8018050 <tcp_free>
+    TCP_EVENT_ERR(last_state, errf, errf_arg, ERR_ABRT);
+ 80186a0:	693b      	ldr	r3, [r7, #16]
+ 80186a2:	2b00      	cmp	r3, #0
+ 80186a4:	d004      	beq.n	80186b0 <tcp_abandon+0x154>
+ 80186a6:	693b      	ldr	r3, [r7, #16]
+ 80186a8:	f06f 010c 	mvn.w	r1, #12
+ 80186ac:	68f8      	ldr	r0, [r7, #12]
+ 80186ae:	4798      	blx	r3
+  }
+}
+ 80186b0:	3728      	adds	r7, #40	; 0x28
+ 80186b2:	46bd      	mov	sp, r7
+ 80186b4:	bd80      	pop	{r7, pc}
+ 80186b6:	bf00      	nop
+ 80186b8:	08024ba8 	.word	0x08024ba8
+ 80186bc:	08024cec 	.word	0x08024cec
+ 80186c0:	08024bec 	.word	0x08024bec
+ 80186c4:	08024d08 	.word	0x08024d08
+ 80186c8:	2401a490 	.word	0x2401a490
+ 80186cc:	2401a484 	.word	0x2401a484
+ 80186d0:	2401a48c 	.word	0x2401a48c
+ 80186d4:	2401a494 	.word	0x2401a494
+
+080186d8 <tcp_abort>:
+ *
+ * @param pcb the tcp pcb to abort
+ */
+void
+tcp_abort(struct tcp_pcb *pcb)
+{
+ 80186d8:	b580      	push	{r7, lr}
+ 80186da:	b082      	sub	sp, #8
+ 80186dc:	af00      	add	r7, sp, #0
+ 80186de:	6078      	str	r0, [r7, #4]
+  tcp_abandon(pcb, 1);
+ 80186e0:	2101      	movs	r1, #1
+ 80186e2:	6878      	ldr	r0, [r7, #4]
+ 80186e4:	f7ff ff3a 	bl	801855c <tcp_abandon>
+}
+ 80186e8:	bf00      	nop
+ 80186ea:	3708      	adds	r7, #8
+ 80186ec:	46bd      	mov	sp, r7
+ 80186ee:	bd80      	pop	{r7, pc}
+
+080186f0 <tcp_bind>:
+ *         ERR_VAL if bind failed because the PCB is not in a valid state
+ *         ERR_OK if bound
+ */
+err_t
+tcp_bind(struct tcp_pcb *pcb, const ip_addr_t *ipaddr, u16_t port)
+{
+ 80186f0:	b580      	push	{r7, lr}
+ 80186f2:	b088      	sub	sp, #32
+ 80186f4:	af00      	add	r7, sp, #0
+ 80186f6:	60f8      	str	r0, [r7, #12]
+ 80186f8:	60b9      	str	r1, [r7, #8]
+ 80186fa:	4613      	mov	r3, r2
+ 80186fc:	80fb      	strh	r3, [r7, #6]
+  int i;
+  int max_pcb_list = NUM_TCP_PCB_LISTS;
+ 80186fe:	2304      	movs	r3, #4
+ 8018700:	617b      	str	r3, [r7, #20]
+
+  LWIP_ASSERT_CORE_LOCKED();
+
+#if LWIP_IPV4
+  /* Don't propagate NULL pointer (IPv4 ANY) to subsequent functions */
+  if (ipaddr == NULL) {
+ 8018702:	68bb      	ldr	r3, [r7, #8]
+ 8018704:	2b00      	cmp	r3, #0
+ 8018706:	d101      	bne.n	801870c <tcp_bind+0x1c>
+    ipaddr = IP4_ADDR_ANY;
+ 8018708:	4b3e      	ldr	r3, [pc, #248]	; (8018804 <tcp_bind+0x114>)
+ 801870a:	60bb      	str	r3, [r7, #8]
+  }
+#else /* LWIP_IPV4 */
+  LWIP_ERROR("tcp_bind: invalid ipaddr", ipaddr != NULL, return ERR_ARG);
+#endif /* LWIP_IPV4 */
+
+  LWIP_ERROR("tcp_bind: invalid pcb", pcb != NULL, return ERR_ARG);
+ 801870c:	68fb      	ldr	r3, [r7, #12]
+ 801870e:	2b00      	cmp	r3, #0
+ 8018710:	d109      	bne.n	8018726 <tcp_bind+0x36>
+ 8018712:	4b3d      	ldr	r3, [pc, #244]	; (8018808 <tcp_bind+0x118>)
+ 8018714:	f240 22a9 	movw	r2, #681	; 0x2a9
+ 8018718:	493c      	ldr	r1, [pc, #240]	; (801880c <tcp_bind+0x11c>)
+ 801871a:	483d      	ldr	r0, [pc, #244]	; (8018810 <tcp_bind+0x120>)
+ 801871c:	f009 f934 	bl	8021988 <iprintf>
+ 8018720:	f06f 030f 	mvn.w	r3, #15
+ 8018724:	e06a      	b.n	80187fc <tcp_bind+0x10c>
+
+  LWIP_ERROR("tcp_bind: can only bind in state CLOSED", pcb->state == CLOSED, return ERR_VAL);
+ 8018726:	68fb      	ldr	r3, [r7, #12]
+ 8018728:	7d1b      	ldrb	r3, [r3, #20]
+ 801872a:	2b00      	cmp	r3, #0
+ 801872c:	d009      	beq.n	8018742 <tcp_bind+0x52>
+ 801872e:	4b36      	ldr	r3, [pc, #216]	; (8018808 <tcp_bind+0x118>)
+ 8018730:	f240 22ab 	movw	r2, #683	; 0x2ab
+ 8018734:	4937      	ldr	r1, [pc, #220]	; (8018814 <tcp_bind+0x124>)
+ 8018736:	4836      	ldr	r0, [pc, #216]	; (8018810 <tcp_bind+0x120>)
+ 8018738:	f009 f926 	bl	8021988 <iprintf>
+ 801873c:	f06f 0305 	mvn.w	r3, #5
+ 8018740:	e05c      	b.n	80187fc <tcp_bind+0x10c>
+    ip6_addr_select_zone(ip_2_ip6(&zoned_ipaddr), ip_2_ip6(&zoned_ipaddr));
+    ipaddr = &zoned_ipaddr;
+  }
+#endif /* LWIP_IPV6 && LWIP_IPV6_SCOPES */
+
+  if (port == 0) {
+ 8018742:	88fb      	ldrh	r3, [r7, #6]
+ 8018744:	2b00      	cmp	r3, #0
+ 8018746:	d109      	bne.n	801875c <tcp_bind+0x6c>
+    port = tcp_new_port();
+ 8018748:	f000 f916 	bl	8018978 <tcp_new_port>
+ 801874c:	4603      	mov	r3, r0
+ 801874e:	80fb      	strh	r3, [r7, #6]
+    if (port == 0) {
+ 8018750:	88fb      	ldrh	r3, [r7, #6]
+ 8018752:	2b00      	cmp	r3, #0
+ 8018754:	d135      	bne.n	80187c2 <tcp_bind+0xd2>
+      return ERR_BUF;
+ 8018756:	f06f 0301 	mvn.w	r3, #1
+ 801875a:	e04f      	b.n	80187fc <tcp_bind+0x10c>
+    }
+  } else {
+    /* Check if the address already is in use (on all lists) */
+    for (i = 0; i < max_pcb_list; i++) {
+ 801875c:	2300      	movs	r3, #0
+ 801875e:	61fb      	str	r3, [r7, #28]
+ 8018760:	e02b      	b.n	80187ba <tcp_bind+0xca>
+      for (cpcb = *tcp_pcb_lists[i]; cpcb != NULL; cpcb = cpcb->next) {
+ 8018762:	4a2d      	ldr	r2, [pc, #180]	; (8018818 <tcp_bind+0x128>)
+ 8018764:	69fb      	ldr	r3, [r7, #28]
+ 8018766:	f852 3023 	ldr.w	r3, [r2, r3, lsl #2]
+ 801876a:	681b      	ldr	r3, [r3, #0]
+ 801876c:	61bb      	str	r3, [r7, #24]
+ 801876e:	e01e      	b.n	80187ae <tcp_bind+0xbe>
+        if (cpcb->local_port == port) {
+ 8018770:	69bb      	ldr	r3, [r7, #24]
+ 8018772:	8adb      	ldrh	r3, [r3, #22]
+ 8018774:	88fa      	ldrh	r2, [r7, #6]
+ 8018776:	429a      	cmp	r2, r3
+ 8018778:	d116      	bne.n	80187a8 <tcp_bind+0xb8>
+              !ip_get_option(cpcb, SOF_REUSEADDR))
+#endif /* SO_REUSE */
+          {
+            /* @todo: check accept_any_ip_version */
+            if ((IP_IS_V6(ipaddr) == IP_IS_V6_VAL(cpcb->local_ip)) &&
+                (ip_addr_isany(&cpcb->local_ip) ||
+ 801877a:	69bb      	ldr	r3, [r7, #24]
+            if ((IP_IS_V6(ipaddr) == IP_IS_V6_VAL(cpcb->local_ip)) &&
+ 801877c:	2b00      	cmp	r3, #0
+ 801877e:	d010      	beq.n	80187a2 <tcp_bind+0xb2>
+                (ip_addr_isany(&cpcb->local_ip) ||
+ 8018780:	69bb      	ldr	r3, [r7, #24]
+ 8018782:	681b      	ldr	r3, [r3, #0]
+ 8018784:	2b00      	cmp	r3, #0
+ 8018786:	d00c      	beq.n	80187a2 <tcp_bind+0xb2>
+ 8018788:	68bb      	ldr	r3, [r7, #8]
+ 801878a:	2b00      	cmp	r3, #0
+ 801878c:	d009      	beq.n	80187a2 <tcp_bind+0xb2>
+                 ip_addr_isany(ipaddr) ||
+ 801878e:	68bb      	ldr	r3, [r7, #8]
+ 8018790:	681b      	ldr	r3, [r3, #0]
+ 8018792:	2b00      	cmp	r3, #0
+ 8018794:	d005      	beq.n	80187a2 <tcp_bind+0xb2>
+                 ip_addr_cmp(&cpcb->local_ip, ipaddr))) {
+ 8018796:	69bb      	ldr	r3, [r7, #24]
+ 8018798:	681a      	ldr	r2, [r3, #0]
+ 801879a:	68bb      	ldr	r3, [r7, #8]
+ 801879c:	681b      	ldr	r3, [r3, #0]
+            if ((IP_IS_V6(ipaddr) == IP_IS_V6_VAL(cpcb->local_ip)) &&
+ 801879e:	429a      	cmp	r2, r3
+ 80187a0:	d102      	bne.n	80187a8 <tcp_bind+0xb8>
+              return ERR_USE;
+ 80187a2:	f06f 0307 	mvn.w	r3, #7
+ 80187a6:	e029      	b.n	80187fc <tcp_bind+0x10c>
+      for (cpcb = *tcp_pcb_lists[i]; cpcb != NULL; cpcb = cpcb->next) {
+ 80187a8:	69bb      	ldr	r3, [r7, #24]
+ 80187aa:	68db      	ldr	r3, [r3, #12]
+ 80187ac:	61bb      	str	r3, [r7, #24]
+ 80187ae:	69bb      	ldr	r3, [r7, #24]
+ 80187b0:	2b00      	cmp	r3, #0
+ 80187b2:	d1dd      	bne.n	8018770 <tcp_bind+0x80>
+    for (i = 0; i < max_pcb_list; i++) {
+ 80187b4:	69fb      	ldr	r3, [r7, #28]
+ 80187b6:	3301      	adds	r3, #1
+ 80187b8:	61fb      	str	r3, [r7, #28]
+ 80187ba:	69fa      	ldr	r2, [r7, #28]
+ 80187bc:	697b      	ldr	r3, [r7, #20]
+ 80187be:	429a      	cmp	r2, r3
+ 80187c0:	dbcf      	blt.n	8018762 <tcp_bind+0x72>
+        }
+      }
+    }
+  }
+
+  if (!ip_addr_isany(ipaddr)
+ 80187c2:	68bb      	ldr	r3, [r7, #8]
+ 80187c4:	2b00      	cmp	r3, #0
+ 80187c6:	d00c      	beq.n	80187e2 <tcp_bind+0xf2>
+ 80187c8:	68bb      	ldr	r3, [r7, #8]
+ 80187ca:	681b      	ldr	r3, [r3, #0]
+ 80187cc:	2b00      	cmp	r3, #0
+ 80187ce:	d008      	beq.n	80187e2 <tcp_bind+0xf2>
+#if LWIP_IPV4 && LWIP_IPV6
+      || (IP_GET_TYPE(ipaddr) != IP_GET_TYPE(&pcb->local_ip))
+#endif /* LWIP_IPV4 && LWIP_IPV6 */
+     ) {
+    ip_addr_set(&pcb->local_ip, ipaddr);
+ 80187d0:	68bb      	ldr	r3, [r7, #8]
+ 80187d2:	2b00      	cmp	r3, #0
+ 80187d4:	d002      	beq.n	80187dc <tcp_bind+0xec>
+ 80187d6:	68bb      	ldr	r3, [r7, #8]
+ 80187d8:	681b      	ldr	r3, [r3, #0]
+ 80187da:	e000      	b.n	80187de <tcp_bind+0xee>
+ 80187dc:	2300      	movs	r3, #0
+ 80187de:	68fa      	ldr	r2, [r7, #12]
+ 80187e0:	6013      	str	r3, [r2, #0]
+  }
+  pcb->local_port = port;
+ 80187e2:	68fb      	ldr	r3, [r7, #12]
+ 80187e4:	88fa      	ldrh	r2, [r7, #6]
+ 80187e6:	82da      	strh	r2, [r3, #22]
+  TCP_REG(&tcp_bound_pcbs, pcb);
+ 80187e8:	4b0c      	ldr	r3, [pc, #48]	; (801881c <tcp_bind+0x12c>)
+ 80187ea:	681a      	ldr	r2, [r3, #0]
+ 80187ec:	68fb      	ldr	r3, [r7, #12]
+ 80187ee:	60da      	str	r2, [r3, #12]
+ 80187f0:	4a0a      	ldr	r2, [pc, #40]	; (801881c <tcp_bind+0x12c>)
+ 80187f2:	68fb      	ldr	r3, [r7, #12]
+ 80187f4:	6013      	str	r3, [r2, #0]
+ 80187f6:	f005 fd63 	bl	801e2c0 <tcp_timer_needed>
+  LWIP_DEBUGF(TCP_DEBUG, ("tcp_bind: bind to port %"U16_F"\n", port));
+  return ERR_OK;
+ 80187fa:	2300      	movs	r3, #0
+}
+ 80187fc:	4618      	mov	r0, r3
+ 80187fe:	3720      	adds	r7, #32
+ 8018800:	46bd      	mov	sp, r7
+ 8018802:	bd80      	pop	{r7, pc}
+ 8018804:	08026cec 	.word	0x08026cec
+ 8018808:	08024ba8 	.word	0x08024ba8
+ 801880c:	08024d3c 	.word	0x08024d3c
+ 8018810:	08024bec 	.word	0x08024bec
+ 8018814:	08024d54 	.word	0x08024d54
+ 8018818:	08026cc4 	.word	0x08026cc4
+ 801881c:	2401a484 	.word	0x2401a484
+
+08018820 <tcp_update_rcv_ann_wnd>:
+ * Returns how much extra window would be advertised if we sent an
+ * update now.
+ */
+u32_t
+tcp_update_rcv_ann_wnd(struct tcp_pcb *pcb)
+{
+ 8018820:	b580      	push	{r7, lr}
+ 8018822:	b084      	sub	sp, #16
+ 8018824:	af00      	add	r7, sp, #0
+ 8018826:	6078      	str	r0, [r7, #4]
+  u32_t new_right_edge;
+
+  LWIP_ASSERT("tcp_update_rcv_ann_wnd: invalid pcb", pcb != NULL);
+ 8018828:	687b      	ldr	r3, [r7, #4]
+ 801882a:	2b00      	cmp	r3, #0
+ 801882c:	d106      	bne.n	801883c <tcp_update_rcv_ann_wnd+0x1c>
+ 801882e:	4b25      	ldr	r3, [pc, #148]	; (80188c4 <tcp_update_rcv_ann_wnd+0xa4>)
+ 8018830:	f240 32a6 	movw	r2, #934	; 0x3a6
+ 8018834:	4924      	ldr	r1, [pc, #144]	; (80188c8 <tcp_update_rcv_ann_wnd+0xa8>)
+ 8018836:	4825      	ldr	r0, [pc, #148]	; (80188cc <tcp_update_rcv_ann_wnd+0xac>)
+ 8018838:	f009 f8a6 	bl	8021988 <iprintf>
+  new_right_edge = pcb->rcv_nxt + pcb->rcv_wnd;
+ 801883c:	687b      	ldr	r3, [r7, #4]
+ 801883e:	6a5b      	ldr	r3, [r3, #36]	; 0x24
+ 8018840:	687a      	ldr	r2, [r7, #4]
+ 8018842:	8d12      	ldrh	r2, [r2, #40]	; 0x28
+ 8018844:	4413      	add	r3, r2
+ 8018846:	60fb      	str	r3, [r7, #12]
+
+  if (TCP_SEQ_GEQ(new_right_edge, pcb->rcv_ann_right_edge + LWIP_MIN((TCP_WND / 2), pcb->mss))) {
+ 8018848:	687b      	ldr	r3, [r7, #4]
+ 801884a:	6adb      	ldr	r3, [r3, #44]	; 0x2c
+ 801884c:	687a      	ldr	r2, [r7, #4]
+ 801884e:	8e52      	ldrh	r2, [r2, #50]	; 0x32
+ 8018850:	f640 3168 	movw	r1, #2920	; 0xb68
+ 8018854:	428a      	cmp	r2, r1
+ 8018856:	bf28      	it	cs
+ 8018858:	460a      	movcs	r2, r1
+ 801885a:	b292      	uxth	r2, r2
+ 801885c:	4413      	add	r3, r2
+ 801885e:	68fa      	ldr	r2, [r7, #12]
+ 8018860:	1ad3      	subs	r3, r2, r3
+ 8018862:	2b00      	cmp	r3, #0
+ 8018864:	db08      	blt.n	8018878 <tcp_update_rcv_ann_wnd+0x58>
+    /* we can advertise more window */
+    pcb->rcv_ann_wnd = pcb->rcv_wnd;
+ 8018866:	687b      	ldr	r3, [r7, #4]
+ 8018868:	8d1a      	ldrh	r2, [r3, #40]	; 0x28
+ 801886a:	687b      	ldr	r3, [r7, #4]
+ 801886c:	855a      	strh	r2, [r3, #42]	; 0x2a
+    return new_right_edge - pcb->rcv_ann_right_edge;
+ 801886e:	687b      	ldr	r3, [r7, #4]
+ 8018870:	6adb      	ldr	r3, [r3, #44]	; 0x2c
+ 8018872:	68fa      	ldr	r2, [r7, #12]
+ 8018874:	1ad3      	subs	r3, r2, r3
+ 8018876:	e020      	b.n	80188ba <tcp_update_rcv_ann_wnd+0x9a>
+  } else {
+    if (TCP_SEQ_GT(pcb->rcv_nxt, pcb->rcv_ann_right_edge)) {
+ 8018878:	687b      	ldr	r3, [r7, #4]
+ 801887a:	6a5a      	ldr	r2, [r3, #36]	; 0x24
+ 801887c:	687b      	ldr	r3, [r7, #4]
+ 801887e:	6adb      	ldr	r3, [r3, #44]	; 0x2c
+ 8018880:	1ad3      	subs	r3, r2, r3
+ 8018882:	2b00      	cmp	r3, #0
+ 8018884:	dd03      	ble.n	801888e <tcp_update_rcv_ann_wnd+0x6e>
+      /* Can happen due to other end sending out of advertised window,
+       * but within actual available (but not yet advertised) window */
+      pcb->rcv_ann_wnd = 0;
+ 8018886:	687b      	ldr	r3, [r7, #4]
+ 8018888:	2200      	movs	r2, #0
+ 801888a:	855a      	strh	r2, [r3, #42]	; 0x2a
+ 801888c:	e014      	b.n	80188b8 <tcp_update_rcv_ann_wnd+0x98>
+    } else {
+      /* keep the right edge of window constant */
+      u32_t new_rcv_ann_wnd = pcb->rcv_ann_right_edge - pcb->rcv_nxt;
+ 801888e:	687b      	ldr	r3, [r7, #4]
+ 8018890:	6ada      	ldr	r2, [r3, #44]	; 0x2c
+ 8018892:	687b      	ldr	r3, [r7, #4]
+ 8018894:	6a5b      	ldr	r3, [r3, #36]	; 0x24
+ 8018896:	1ad3      	subs	r3, r2, r3
+ 8018898:	60bb      	str	r3, [r7, #8]
+#if !LWIP_WND_SCALE
+      LWIP_ASSERT("new_rcv_ann_wnd <= 0xffff", new_rcv_ann_wnd <= 0xffff);
+ 801889a:	68bb      	ldr	r3, [r7, #8]
+ 801889c:	f5b3 3f80 	cmp.w	r3, #65536	; 0x10000
+ 80188a0:	d306      	bcc.n	80188b0 <tcp_update_rcv_ann_wnd+0x90>
+ 80188a2:	4b08      	ldr	r3, [pc, #32]	; (80188c4 <tcp_update_rcv_ann_wnd+0xa4>)
+ 80188a4:	f240 32b6 	movw	r2, #950	; 0x3b6
+ 80188a8:	4909      	ldr	r1, [pc, #36]	; (80188d0 <tcp_update_rcv_ann_wnd+0xb0>)
+ 80188aa:	4808      	ldr	r0, [pc, #32]	; (80188cc <tcp_update_rcv_ann_wnd+0xac>)
+ 80188ac:	f009 f86c 	bl	8021988 <iprintf>
+#endif
+      pcb->rcv_ann_wnd = (tcpwnd_size_t)new_rcv_ann_wnd;
+ 80188b0:	68bb      	ldr	r3, [r7, #8]
+ 80188b2:	b29a      	uxth	r2, r3
+ 80188b4:	687b      	ldr	r3, [r7, #4]
+ 80188b6:	855a      	strh	r2, [r3, #42]	; 0x2a
+    }
+    return 0;
+ 80188b8:	2300      	movs	r3, #0
+  }
+}
+ 80188ba:	4618      	mov	r0, r3
+ 80188bc:	3710      	adds	r7, #16
+ 80188be:	46bd      	mov	sp, r7
+ 80188c0:	bd80      	pop	{r7, pc}
+ 80188c2:	bf00      	nop
+ 80188c4:	08024ba8 	.word	0x08024ba8
+ 80188c8:	08024e04 	.word	0x08024e04
+ 80188cc:	08024bec 	.word	0x08024bec
+ 80188d0:	08024e28 	.word	0x08024e28
+
+080188d4 <tcp_recved>:
+ * @param pcb the tcp_pcb for which data is read
+ * @param len the amount of bytes that have been read by the application
+ */
+void
+tcp_recved(struct tcp_pcb *pcb, u16_t len)
+{
+ 80188d4:	b580      	push	{r7, lr}
+ 80188d6:	b084      	sub	sp, #16
+ 80188d8:	af00      	add	r7, sp, #0
+ 80188da:	6078      	str	r0, [r7, #4]
+ 80188dc:	460b      	mov	r3, r1
+ 80188de:	807b      	strh	r3, [r7, #2]
+  u32_t wnd_inflation;
+  tcpwnd_size_t rcv_wnd;
+
+  LWIP_ASSERT_CORE_LOCKED();
+
+  LWIP_ERROR("tcp_recved: invalid pcb", pcb != NULL, return);
+ 80188e0:	687b      	ldr	r3, [r7, #4]
+ 80188e2:	2b00      	cmp	r3, #0
+ 80188e4:	d107      	bne.n	80188f6 <tcp_recved+0x22>
+ 80188e6:	4b20      	ldr	r3, [pc, #128]	; (8018968 <tcp_recved+0x94>)
+ 80188e8:	f240 32cf 	movw	r2, #975	; 0x3cf
+ 80188ec:	491f      	ldr	r1, [pc, #124]	; (801896c <tcp_recved+0x98>)
+ 80188ee:	4820      	ldr	r0, [pc, #128]	; (8018970 <tcp_recved+0x9c>)
+ 80188f0:	f009 f84a 	bl	8021988 <iprintf>
+ 80188f4:	e034      	b.n	8018960 <tcp_recved+0x8c>
+
+  /* pcb->state LISTEN not allowed here */
+  LWIP_ASSERT("don't call tcp_recved for listen-pcbs",
+ 80188f6:	687b      	ldr	r3, [r7, #4]
+ 80188f8:	7d1b      	ldrb	r3, [r3, #20]
+ 80188fa:	2b01      	cmp	r3, #1
+ 80188fc:	d106      	bne.n	801890c <tcp_recved+0x38>
+ 80188fe:	4b1a      	ldr	r3, [pc, #104]	; (8018968 <tcp_recved+0x94>)
+ 8018900:	f240 32d2 	movw	r2, #978	; 0x3d2
+ 8018904:	491b      	ldr	r1, [pc, #108]	; (8018974 <tcp_recved+0xa0>)
+ 8018906:	481a      	ldr	r0, [pc, #104]	; (8018970 <tcp_recved+0x9c>)
+ 8018908:	f009 f83e 	bl	8021988 <iprintf>
+              pcb->state != LISTEN);
+
+  rcv_wnd = (tcpwnd_size_t)(pcb->rcv_wnd + len);
+ 801890c:	687b      	ldr	r3, [r7, #4]
+ 801890e:	8d1a      	ldrh	r2, [r3, #40]	; 0x28
+ 8018910:	887b      	ldrh	r3, [r7, #2]
+ 8018912:	4413      	add	r3, r2
+ 8018914:	81fb      	strh	r3, [r7, #14]
+  if ((rcv_wnd > TCP_WND_MAX(pcb)) || (rcv_wnd < pcb->rcv_wnd)) {
+ 8018916:	89fb      	ldrh	r3, [r7, #14]
+ 8018918:	f241 62d0 	movw	r2, #5840	; 0x16d0
+ 801891c:	4293      	cmp	r3, r2
+ 801891e:	d804      	bhi.n	801892a <tcp_recved+0x56>
+ 8018920:	687b      	ldr	r3, [r7, #4]
+ 8018922:	8d1b      	ldrh	r3, [r3, #40]	; 0x28
+ 8018924:	89fa      	ldrh	r2, [r7, #14]
+ 8018926:	429a      	cmp	r2, r3
+ 8018928:	d204      	bcs.n	8018934 <tcp_recved+0x60>
+    /* window got too big or tcpwnd_size_t overflow */
+    LWIP_DEBUGF(TCP_DEBUG, ("tcp_recved: window got too big or tcpwnd_size_t overflow\n"));
+    pcb->rcv_wnd = TCP_WND_MAX(pcb);
+ 801892a:	687b      	ldr	r3, [r7, #4]
+ 801892c:	f241 62d0 	movw	r2, #5840	; 0x16d0
+ 8018930:	851a      	strh	r2, [r3, #40]	; 0x28
+ 8018932:	e002      	b.n	801893a <tcp_recved+0x66>
+  } else  {
+    pcb->rcv_wnd = rcv_wnd;
+ 8018934:	687b      	ldr	r3, [r7, #4]
+ 8018936:	89fa      	ldrh	r2, [r7, #14]
+ 8018938:	851a      	strh	r2, [r3, #40]	; 0x28
+  }
+
+  wnd_inflation = tcp_update_rcv_ann_wnd(pcb);
+ 801893a:	6878      	ldr	r0, [r7, #4]
+ 801893c:	f7ff ff70 	bl	8018820 <tcp_update_rcv_ann_wnd>
+ 8018940:	60b8      	str	r0, [r7, #8]
+
+  /* If the change in the right edge of window is significant (default
+   * watermark is TCP_WND/4), then send an explicit update now.
+   * Otherwise wait for a packet to be sent in the normal course of
+   * events (or more window to be available later) */
+  if (wnd_inflation >= TCP_WND_UPDATE_THRESHOLD) {
+ 8018942:	68bb      	ldr	r3, [r7, #8]
+ 8018944:	f240 52b3 	movw	r2, #1459	; 0x5b3
+ 8018948:	4293      	cmp	r3, r2
+ 801894a:	d909      	bls.n	8018960 <tcp_recved+0x8c>
+    tcp_ack_now(pcb);
+ 801894c:	687b      	ldr	r3, [r7, #4]
+ 801894e:	8b5b      	ldrh	r3, [r3, #26]
+ 8018950:	f043 0302 	orr.w	r3, r3, #2
+ 8018954:	b29a      	uxth	r2, r3
+ 8018956:	687b      	ldr	r3, [r7, #4]
+ 8018958:	835a      	strh	r2, [r3, #26]
+    tcp_output(pcb);
+ 801895a:	6878      	ldr	r0, [r7, #4]
+ 801895c:	f004 fd2e 	bl	801d3bc <tcp_output>
+  }
+
+  LWIP_DEBUGF(TCP_DEBUG, ("tcp_recved: received %"U16_F" bytes, wnd %"TCPWNDSIZE_F" (%"TCPWNDSIZE_F").\n",
+                          len, pcb->rcv_wnd, (u16_t)(TCP_WND_MAX(pcb) - pcb->rcv_wnd)));
+}
+ 8018960:	3710      	adds	r7, #16
+ 8018962:	46bd      	mov	sp, r7
+ 8018964:	bd80      	pop	{r7, pc}
+ 8018966:	bf00      	nop
+ 8018968:	08024ba8 	.word	0x08024ba8
+ 801896c:	08024e44 	.word	0x08024e44
+ 8018970:	08024bec 	.word	0x08024bec
+ 8018974:	08024e5c 	.word	0x08024e5c
+
+08018978 <tcp_new_port>:
+ *
+ * @return a new (free) local TCP port number
+ */
+static u16_t
+tcp_new_port(void)
+{
+ 8018978:	b480      	push	{r7}
+ 801897a:	b083      	sub	sp, #12
+ 801897c:	af00      	add	r7, sp, #0
+  u8_t i;
+  u16_t n = 0;
+ 801897e:	2300      	movs	r3, #0
+ 8018980:	80bb      	strh	r3, [r7, #4]
+  struct tcp_pcb *pcb;
+
+again:
+  tcp_port++;
+ 8018982:	4b1e      	ldr	r3, [pc, #120]	; (80189fc <tcp_new_port+0x84>)
+ 8018984:	881b      	ldrh	r3, [r3, #0]
+ 8018986:	3301      	adds	r3, #1
+ 8018988:	b29a      	uxth	r2, r3
+ 801898a:	4b1c      	ldr	r3, [pc, #112]	; (80189fc <tcp_new_port+0x84>)
+ 801898c:	801a      	strh	r2, [r3, #0]
+  if (tcp_port == TCP_LOCAL_PORT_RANGE_END) {
+ 801898e:	4b1b      	ldr	r3, [pc, #108]	; (80189fc <tcp_new_port+0x84>)
+ 8018990:	881b      	ldrh	r3, [r3, #0]
+ 8018992:	f64f 72ff 	movw	r2, #65535	; 0xffff
+ 8018996:	4293      	cmp	r3, r2
+ 8018998:	d103      	bne.n	80189a2 <tcp_new_port+0x2a>
+    tcp_port = TCP_LOCAL_PORT_RANGE_START;
+ 801899a:	4b18      	ldr	r3, [pc, #96]	; (80189fc <tcp_new_port+0x84>)
+ 801899c:	f44f 4240 	mov.w	r2, #49152	; 0xc000
+ 80189a0:	801a      	strh	r2, [r3, #0]
+  }
+  /* Check all PCB lists. */
+  for (i = 0; i < NUM_TCP_PCB_LISTS; i++) {
+ 80189a2:	2300      	movs	r3, #0
+ 80189a4:	71fb      	strb	r3, [r7, #7]
+ 80189a6:	e01e      	b.n	80189e6 <tcp_new_port+0x6e>
+    for (pcb = *tcp_pcb_lists[i]; pcb != NULL; pcb = pcb->next) {
+ 80189a8:	79fb      	ldrb	r3, [r7, #7]
+ 80189aa:	4a15      	ldr	r2, [pc, #84]	; (8018a00 <tcp_new_port+0x88>)
+ 80189ac:	f852 3023 	ldr.w	r3, [r2, r3, lsl #2]
+ 80189b0:	681b      	ldr	r3, [r3, #0]
+ 80189b2:	603b      	str	r3, [r7, #0]
+ 80189b4:	e011      	b.n	80189da <tcp_new_port+0x62>
+      if (pcb->local_port == tcp_port) {
+ 80189b6:	683b      	ldr	r3, [r7, #0]
+ 80189b8:	8ada      	ldrh	r2, [r3, #22]
+ 80189ba:	4b10      	ldr	r3, [pc, #64]	; (80189fc <tcp_new_port+0x84>)
+ 80189bc:	881b      	ldrh	r3, [r3, #0]
+ 80189be:	429a      	cmp	r2, r3
+ 80189c0:	d108      	bne.n	80189d4 <tcp_new_port+0x5c>
+        n++;
+ 80189c2:	88bb      	ldrh	r3, [r7, #4]
+ 80189c4:	3301      	adds	r3, #1
+ 80189c6:	80bb      	strh	r3, [r7, #4]
+        if (n > (TCP_LOCAL_PORT_RANGE_END - TCP_LOCAL_PORT_RANGE_START)) {
+ 80189c8:	88bb      	ldrh	r3, [r7, #4]
+ 80189ca:	f5b3 4f80 	cmp.w	r3, #16384	; 0x4000
+ 80189ce:	d3d8      	bcc.n	8018982 <tcp_new_port+0xa>
+          return 0;
+ 80189d0:	2300      	movs	r3, #0
+ 80189d2:	e00d      	b.n	80189f0 <tcp_new_port+0x78>
+    for (pcb = *tcp_pcb_lists[i]; pcb != NULL; pcb = pcb->next) {
+ 80189d4:	683b      	ldr	r3, [r7, #0]
+ 80189d6:	68db      	ldr	r3, [r3, #12]
+ 80189d8:	603b      	str	r3, [r7, #0]
+ 80189da:	683b      	ldr	r3, [r7, #0]
+ 80189dc:	2b00      	cmp	r3, #0
+ 80189de:	d1ea      	bne.n	80189b6 <tcp_new_port+0x3e>
+  for (i = 0; i < NUM_TCP_PCB_LISTS; i++) {
+ 80189e0:	79fb      	ldrb	r3, [r7, #7]
+ 80189e2:	3301      	adds	r3, #1
+ 80189e4:	71fb      	strb	r3, [r7, #7]
+ 80189e6:	79fb      	ldrb	r3, [r7, #7]
+ 80189e8:	2b03      	cmp	r3, #3
+ 80189ea:	d9dd      	bls.n	80189a8 <tcp_new_port+0x30>
+        }
+        goto again;
+      }
+    }
+  }
+  return tcp_port;
+ 80189ec:	4b03      	ldr	r3, [pc, #12]	; (80189fc <tcp_new_port+0x84>)
+ 80189ee:	881b      	ldrh	r3, [r3, #0]
+}
+ 80189f0:	4618      	mov	r0, r3
+ 80189f2:	370c      	adds	r7, #12
+ 80189f4:	46bd      	mov	sp, r7
+ 80189f6:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 80189fa:	4770      	bx	lr
+ 80189fc:	2400003c 	.word	0x2400003c
+ 8018a00:	08026cc4 	.word	0x08026cc4
+
+08018a04 <tcp_connect>:
+ *         other err_t values if connect request couldn't be sent
+ */
+err_t
+tcp_connect(struct tcp_pcb *pcb, const ip_addr_t *ipaddr, u16_t port,
+            tcp_connected_fn connected)
+{
+ 8018a04:	b580      	push	{r7, lr}
+ 8018a06:	b08a      	sub	sp, #40	; 0x28
+ 8018a08:	af00      	add	r7, sp, #0
+ 8018a0a:	60f8      	str	r0, [r7, #12]
+ 8018a0c:	60b9      	str	r1, [r7, #8]
+ 8018a0e:	603b      	str	r3, [r7, #0]
+ 8018a10:	4613      	mov	r3, r2
+ 8018a12:	80fb      	strh	r3, [r7, #6]
+  struct netif *netif = NULL;
+ 8018a14:	2300      	movs	r3, #0
+ 8018a16:	627b      	str	r3, [r7, #36]	; 0x24
+  u32_t iss;
+  u16_t old_local_port;
+
+  LWIP_ASSERT_CORE_LOCKED();
+
+  LWIP_ERROR("tcp_connect: invalid pcb", pcb != NULL, return ERR_ARG);
+ 8018a18:	68fb      	ldr	r3, [r7, #12]
+ 8018a1a:	2b00      	cmp	r3, #0
+ 8018a1c:	d109      	bne.n	8018a32 <tcp_connect+0x2e>
+ 8018a1e:	4b7d      	ldr	r3, [pc, #500]	; (8018c14 <tcp_connect+0x210>)
+ 8018a20:	f240 4235 	movw	r2, #1077	; 0x435
+ 8018a24:	497c      	ldr	r1, [pc, #496]	; (8018c18 <tcp_connect+0x214>)
+ 8018a26:	487d      	ldr	r0, [pc, #500]	; (8018c1c <tcp_connect+0x218>)
+ 8018a28:	f008 ffae 	bl	8021988 <iprintf>
+ 8018a2c:	f06f 030f 	mvn.w	r3, #15
+ 8018a30:	e0ec      	b.n	8018c0c <tcp_connect+0x208>
+  LWIP_ERROR("tcp_connect: invalid ipaddr", ipaddr != NULL, return ERR_ARG);
+ 8018a32:	68bb      	ldr	r3, [r7, #8]
+ 8018a34:	2b00      	cmp	r3, #0
+ 8018a36:	d109      	bne.n	8018a4c <tcp_connect+0x48>
+ 8018a38:	4b76      	ldr	r3, [pc, #472]	; (8018c14 <tcp_connect+0x210>)
+ 8018a3a:	f240 4236 	movw	r2, #1078	; 0x436
+ 8018a3e:	4978      	ldr	r1, [pc, #480]	; (8018c20 <tcp_connect+0x21c>)
+ 8018a40:	4876      	ldr	r0, [pc, #472]	; (8018c1c <tcp_connect+0x218>)
+ 8018a42:	f008 ffa1 	bl	8021988 <iprintf>
+ 8018a46:	f06f 030f 	mvn.w	r3, #15
+ 8018a4a:	e0df      	b.n	8018c0c <tcp_connect+0x208>
+
+  LWIP_ERROR("tcp_connect: can only connect from state CLOSED", pcb->state == CLOSED, return ERR_ISCONN);
+ 8018a4c:	68fb      	ldr	r3, [r7, #12]
+ 8018a4e:	7d1b      	ldrb	r3, [r3, #20]
+ 8018a50:	2b00      	cmp	r3, #0
+ 8018a52:	d009      	beq.n	8018a68 <tcp_connect+0x64>
+ 8018a54:	4b6f      	ldr	r3, [pc, #444]	; (8018c14 <tcp_connect+0x210>)
+ 8018a56:	f44f 6287 	mov.w	r2, #1080	; 0x438
+ 8018a5a:	4972      	ldr	r1, [pc, #456]	; (8018c24 <tcp_connect+0x220>)
+ 8018a5c:	486f      	ldr	r0, [pc, #444]	; (8018c1c <tcp_connect+0x218>)
+ 8018a5e:	f008 ff93 	bl	8021988 <iprintf>
+ 8018a62:	f06f 0309 	mvn.w	r3, #9
+ 8018a66:	e0d1      	b.n	8018c0c <tcp_connect+0x208>
+
+  LWIP_DEBUGF(TCP_DEBUG, ("tcp_connect to port %"U16_F"\n", port));
+  ip_addr_set(&pcb->remote_ip, ipaddr);
+ 8018a68:	68bb      	ldr	r3, [r7, #8]
+ 8018a6a:	2b00      	cmp	r3, #0
+ 8018a6c:	d002      	beq.n	8018a74 <tcp_connect+0x70>
+ 8018a6e:	68bb      	ldr	r3, [r7, #8]
+ 8018a70:	681b      	ldr	r3, [r3, #0]
+ 8018a72:	e000      	b.n	8018a76 <tcp_connect+0x72>
+ 8018a74:	2300      	movs	r3, #0
+ 8018a76:	68fa      	ldr	r2, [r7, #12]
+ 8018a78:	6053      	str	r3, [r2, #4]
+  pcb->remote_port = port;
+ 8018a7a:	68fb      	ldr	r3, [r7, #12]
+ 8018a7c:	88fa      	ldrh	r2, [r7, #6]
+ 8018a7e:	831a      	strh	r2, [r3, #24]
+
+  if (pcb->netif_idx != NETIF_NO_INDEX) {
+ 8018a80:	68fb      	ldr	r3, [r7, #12]
+ 8018a82:	7a1b      	ldrb	r3, [r3, #8]
+ 8018a84:	2b00      	cmp	r3, #0
+ 8018a86:	d006      	beq.n	8018a96 <tcp_connect+0x92>
+    netif = netif_get_by_index(pcb->netif_idx);
+ 8018a88:	68fb      	ldr	r3, [r7, #12]
+ 8018a8a:	7a1b      	ldrb	r3, [r3, #8]
+ 8018a8c:	4618      	mov	r0, r3
+ 8018a8e:	f7fe fca1 	bl	80173d4 <netif_get_by_index>
+ 8018a92:	6278      	str	r0, [r7, #36]	; 0x24
+ 8018a94:	e005      	b.n	8018aa2 <tcp_connect+0x9e>
+  } else {
+    /* check if we have a route to the remote host */
+    netif = ip_route(&pcb->local_ip, &pcb->remote_ip);
+ 8018a96:	68fb      	ldr	r3, [r7, #12]
+ 8018a98:	3304      	adds	r3, #4
+ 8018a9a:	4618      	mov	r0, r3
+ 8018a9c:	f007 fa2a 	bl	801fef4 <ip4_route>
+ 8018aa0:	6278      	str	r0, [r7, #36]	; 0x24
+  }
+  if (netif == NULL) {
+ 8018aa2:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 8018aa4:	2b00      	cmp	r3, #0
+ 8018aa6:	d102      	bne.n	8018aae <tcp_connect+0xaa>
+    /* Don't even try to send a SYN packet if we have no route since that will fail. */
+    return ERR_RTE;
+ 8018aa8:	f06f 0303 	mvn.w	r3, #3
+ 8018aac:	e0ae      	b.n	8018c0c <tcp_connect+0x208>
+  }
+
+  /* check if local IP has been assigned to pcb, if not, get one */
+  if (ip_addr_isany(&pcb->local_ip)) {
+ 8018aae:	68fb      	ldr	r3, [r7, #12]
+ 8018ab0:	2b00      	cmp	r3, #0
+ 8018ab2:	d003      	beq.n	8018abc <tcp_connect+0xb8>
+ 8018ab4:	68fb      	ldr	r3, [r7, #12]
+ 8018ab6:	681b      	ldr	r3, [r3, #0]
+ 8018ab8:	2b00      	cmp	r3, #0
+ 8018aba:	d111      	bne.n	8018ae0 <tcp_connect+0xdc>
+    const ip_addr_t *local_ip = ip_netif_get_local_ip(netif, ipaddr);
+ 8018abc:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 8018abe:	2b00      	cmp	r3, #0
+ 8018ac0:	d002      	beq.n	8018ac8 <tcp_connect+0xc4>
+ 8018ac2:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 8018ac4:	3304      	adds	r3, #4
+ 8018ac6:	e000      	b.n	8018aca <tcp_connect+0xc6>
+ 8018ac8:	2300      	movs	r3, #0
+ 8018aca:	61fb      	str	r3, [r7, #28]
+    if (local_ip == NULL) {
+ 8018acc:	69fb      	ldr	r3, [r7, #28]
+ 8018ace:	2b00      	cmp	r3, #0
+ 8018ad0:	d102      	bne.n	8018ad8 <tcp_connect+0xd4>
+      return ERR_RTE;
+ 8018ad2:	f06f 0303 	mvn.w	r3, #3
+ 8018ad6:	e099      	b.n	8018c0c <tcp_connect+0x208>
+    }
+    ip_addr_copy(pcb->local_ip, *local_ip);
+ 8018ad8:	69fb      	ldr	r3, [r7, #28]
+ 8018ada:	681a      	ldr	r2, [r3, #0]
+ 8018adc:	68fb      	ldr	r3, [r7, #12]
+ 8018ade:	601a      	str	r2, [r3, #0]
+      ip6_addr_lacks_zone(ip_2_ip6(&pcb->remote_ip), IP6_UNICAST)) {
+    ip6_addr_assign_zone(ip_2_ip6(&pcb->remote_ip), IP6_UNICAST, netif);
+  }
+#endif /* LWIP_IPV6 && LWIP_IPV6_SCOPES */
+
+  old_local_port = pcb->local_port;
+ 8018ae0:	68fb      	ldr	r3, [r7, #12]
+ 8018ae2:	8adb      	ldrh	r3, [r3, #22]
+ 8018ae4:	837b      	strh	r3, [r7, #26]
+  if (pcb->local_port == 0) {
+ 8018ae6:	68fb      	ldr	r3, [r7, #12]
+ 8018ae8:	8adb      	ldrh	r3, [r3, #22]
+ 8018aea:	2b00      	cmp	r3, #0
+ 8018aec:	d10c      	bne.n	8018b08 <tcp_connect+0x104>
+    pcb->local_port = tcp_new_port();
+ 8018aee:	f7ff ff43 	bl	8018978 <tcp_new_port>
+ 8018af2:	4603      	mov	r3, r0
+ 8018af4:	461a      	mov	r2, r3
+ 8018af6:	68fb      	ldr	r3, [r7, #12]
+ 8018af8:	82da      	strh	r2, [r3, #22]
+    if (pcb->local_port == 0) {
+ 8018afa:	68fb      	ldr	r3, [r7, #12]
+ 8018afc:	8adb      	ldrh	r3, [r3, #22]
+ 8018afe:	2b00      	cmp	r3, #0
+ 8018b00:	d102      	bne.n	8018b08 <tcp_connect+0x104>
+      return ERR_BUF;
+ 8018b02:	f06f 0301 	mvn.w	r3, #1
+ 8018b06:	e081      	b.n	8018c0c <tcp_connect+0x208>
+      }
+    }
+#endif /* SO_REUSE */
+  }
+
+  iss = tcp_next_iss(pcb);
+ 8018b08:	68f8      	ldr	r0, [r7, #12]
+ 8018b0a:	f001 f869 	bl	8019be0 <tcp_next_iss>
+ 8018b0e:	6178      	str	r0, [r7, #20]
+  pcb->rcv_nxt = 0;
+ 8018b10:	68fb      	ldr	r3, [r7, #12]
+ 8018b12:	2200      	movs	r2, #0
+ 8018b14:	625a      	str	r2, [r3, #36]	; 0x24
+  pcb->snd_nxt = iss;
+ 8018b16:	68fb      	ldr	r3, [r7, #12]
+ 8018b18:	697a      	ldr	r2, [r7, #20]
+ 8018b1a:	651a      	str	r2, [r3, #80]	; 0x50
+  pcb->lastack = iss - 1;
+ 8018b1c:	697b      	ldr	r3, [r7, #20]
+ 8018b1e:	1e5a      	subs	r2, r3, #1
+ 8018b20:	68fb      	ldr	r3, [r7, #12]
+ 8018b22:	645a      	str	r2, [r3, #68]	; 0x44
+  pcb->snd_wl2 = iss - 1;
+ 8018b24:	697b      	ldr	r3, [r7, #20]
+ 8018b26:	1e5a      	subs	r2, r3, #1
+ 8018b28:	68fb      	ldr	r3, [r7, #12]
+ 8018b2a:	659a      	str	r2, [r3, #88]	; 0x58
+  pcb->snd_lbb = iss - 1;
+ 8018b2c:	697b      	ldr	r3, [r7, #20]
+ 8018b2e:	1e5a      	subs	r2, r3, #1
+ 8018b30:	68fb      	ldr	r3, [r7, #12]
+ 8018b32:	65da      	str	r2, [r3, #92]	; 0x5c
+  /* Start with a window that does not need scaling. When window scaling is
+     enabled and used, the window is enlarged when both sides agree on scaling. */
+  pcb->rcv_wnd = pcb->rcv_ann_wnd = TCPWND_MIN16(TCP_WND);
+ 8018b34:	68fb      	ldr	r3, [r7, #12]
+ 8018b36:	f241 62d0 	movw	r2, #5840	; 0x16d0
+ 8018b3a:	855a      	strh	r2, [r3, #42]	; 0x2a
+ 8018b3c:	68fb      	ldr	r3, [r7, #12]
+ 8018b3e:	8d5a      	ldrh	r2, [r3, #42]	; 0x2a
+ 8018b40:	68fb      	ldr	r3, [r7, #12]
+ 8018b42:	851a      	strh	r2, [r3, #40]	; 0x28
+  pcb->rcv_ann_right_edge = pcb->rcv_nxt;
+ 8018b44:	68fb      	ldr	r3, [r7, #12]
+ 8018b46:	6a5a      	ldr	r2, [r3, #36]	; 0x24
+ 8018b48:	68fb      	ldr	r3, [r7, #12]
+ 8018b4a:	62da      	str	r2, [r3, #44]	; 0x2c
+  pcb->snd_wnd = TCP_WND;
+ 8018b4c:	68fb      	ldr	r3, [r7, #12]
+ 8018b4e:	f241 62d0 	movw	r2, #5840	; 0x16d0
+ 8018b52:	f8a3 2060 	strh.w	r2, [r3, #96]	; 0x60
+  /* As initial send MSS, we use TCP_MSS but limit it to 536.
+     The send MSS is updated when an MSS option is received. */
+  pcb->mss = INITIAL_MSS;
+ 8018b56:	68fb      	ldr	r3, [r7, #12]
+ 8018b58:	f44f 7206 	mov.w	r2, #536	; 0x218
+ 8018b5c:	865a      	strh	r2, [r3, #50]	; 0x32
+#if TCP_CALCULATE_EFF_SEND_MSS
+  pcb->mss = tcp_eff_send_mss_netif(pcb->mss, netif, &pcb->remote_ip);
+ 8018b5e:	68fb      	ldr	r3, [r7, #12]
+ 8018b60:	8e58      	ldrh	r0, [r3, #50]	; 0x32
+ 8018b62:	68fb      	ldr	r3, [r7, #12]
+ 8018b64:	3304      	adds	r3, #4
+ 8018b66:	461a      	mov	r2, r3
+ 8018b68:	6a79      	ldr	r1, [r7, #36]	; 0x24
+ 8018b6a:	f001 f85f 	bl	8019c2c <tcp_eff_send_mss_netif>
+ 8018b6e:	4603      	mov	r3, r0
+ 8018b70:	461a      	mov	r2, r3
+ 8018b72:	68fb      	ldr	r3, [r7, #12]
+ 8018b74:	865a      	strh	r2, [r3, #50]	; 0x32
+#endif /* TCP_CALCULATE_EFF_SEND_MSS */
+  pcb->cwnd = 1;
+ 8018b76:	68fb      	ldr	r3, [r7, #12]
+ 8018b78:	2201      	movs	r2, #1
+ 8018b7a:	f8a3 2048 	strh.w	r2, [r3, #72]	; 0x48
+#if LWIP_CALLBACK_API
+  pcb->connected = connected;
+ 8018b7e:	68fb      	ldr	r3, [r7, #12]
+ 8018b80:	683a      	ldr	r2, [r7, #0]
+ 8018b82:	f8c3 2088 	str.w	r2, [r3, #136]	; 0x88
+#else /* LWIP_CALLBACK_API */
+  LWIP_UNUSED_ARG(connected);
+#endif /* LWIP_CALLBACK_API */
+
+  /* Send a SYN together with the MSS option. */
+  ret = tcp_enqueue_flags(pcb, TCP_SYN);
+ 8018b86:	2102      	movs	r1, #2
+ 8018b88:	68f8      	ldr	r0, [r7, #12]
+ 8018b8a:	f004 fb29 	bl	801d1e0 <tcp_enqueue_flags>
+ 8018b8e:	4603      	mov	r3, r0
+ 8018b90:	74fb      	strb	r3, [r7, #19]
+  if (ret == ERR_OK) {
+ 8018b92:	f997 3013 	ldrsb.w	r3, [r7, #19]
+ 8018b96:	2b00      	cmp	r3, #0
+ 8018b98:	d136      	bne.n	8018c08 <tcp_connect+0x204>
+    /* SYN segment was enqueued, changed the pcbs state now */
+    pcb->state = SYN_SENT;
+ 8018b9a:	68fb      	ldr	r3, [r7, #12]
+ 8018b9c:	2202      	movs	r2, #2
+ 8018b9e:	751a      	strb	r2, [r3, #20]
+    if (old_local_port != 0) {
+ 8018ba0:	8b7b      	ldrh	r3, [r7, #26]
+ 8018ba2:	2b00      	cmp	r3, #0
+ 8018ba4:	d021      	beq.n	8018bea <tcp_connect+0x1e6>
+      TCP_RMV(&tcp_bound_pcbs, pcb);
+ 8018ba6:	4b20      	ldr	r3, [pc, #128]	; (8018c28 <tcp_connect+0x224>)
+ 8018ba8:	681b      	ldr	r3, [r3, #0]
+ 8018baa:	68fa      	ldr	r2, [r7, #12]
+ 8018bac:	429a      	cmp	r2, r3
+ 8018bae:	d105      	bne.n	8018bbc <tcp_connect+0x1b8>
+ 8018bb0:	4b1d      	ldr	r3, [pc, #116]	; (8018c28 <tcp_connect+0x224>)
+ 8018bb2:	681b      	ldr	r3, [r3, #0]
+ 8018bb4:	68db      	ldr	r3, [r3, #12]
+ 8018bb6:	4a1c      	ldr	r2, [pc, #112]	; (8018c28 <tcp_connect+0x224>)
+ 8018bb8:	6013      	str	r3, [r2, #0]
+ 8018bba:	e013      	b.n	8018be4 <tcp_connect+0x1e0>
+ 8018bbc:	4b1a      	ldr	r3, [pc, #104]	; (8018c28 <tcp_connect+0x224>)
+ 8018bbe:	681b      	ldr	r3, [r3, #0]
+ 8018bc0:	623b      	str	r3, [r7, #32]
+ 8018bc2:	e00c      	b.n	8018bde <tcp_connect+0x1da>
+ 8018bc4:	6a3b      	ldr	r3, [r7, #32]
+ 8018bc6:	68db      	ldr	r3, [r3, #12]
+ 8018bc8:	68fa      	ldr	r2, [r7, #12]
+ 8018bca:	429a      	cmp	r2, r3
+ 8018bcc:	d104      	bne.n	8018bd8 <tcp_connect+0x1d4>
+ 8018bce:	68fb      	ldr	r3, [r7, #12]
+ 8018bd0:	68da      	ldr	r2, [r3, #12]
+ 8018bd2:	6a3b      	ldr	r3, [r7, #32]
+ 8018bd4:	60da      	str	r2, [r3, #12]
+ 8018bd6:	e005      	b.n	8018be4 <tcp_connect+0x1e0>
+ 8018bd8:	6a3b      	ldr	r3, [r7, #32]
+ 8018bda:	68db      	ldr	r3, [r3, #12]
+ 8018bdc:	623b      	str	r3, [r7, #32]
+ 8018bde:	6a3b      	ldr	r3, [r7, #32]
+ 8018be0:	2b00      	cmp	r3, #0
+ 8018be2:	d1ef      	bne.n	8018bc4 <tcp_connect+0x1c0>
+ 8018be4:	68fb      	ldr	r3, [r7, #12]
+ 8018be6:	2200      	movs	r2, #0
+ 8018be8:	60da      	str	r2, [r3, #12]
+    }
+    TCP_REG_ACTIVE(pcb);
+ 8018bea:	4b10      	ldr	r3, [pc, #64]	; (8018c2c <tcp_connect+0x228>)
+ 8018bec:	681a      	ldr	r2, [r3, #0]
+ 8018bee:	68fb      	ldr	r3, [r7, #12]
+ 8018bf0:	60da      	str	r2, [r3, #12]
+ 8018bf2:	4a0e      	ldr	r2, [pc, #56]	; (8018c2c <tcp_connect+0x228>)
+ 8018bf4:	68fb      	ldr	r3, [r7, #12]
+ 8018bf6:	6013      	str	r3, [r2, #0]
+ 8018bf8:	f005 fb62 	bl	801e2c0 <tcp_timer_needed>
+ 8018bfc:	4b0c      	ldr	r3, [pc, #48]	; (8018c30 <tcp_connect+0x22c>)
+ 8018bfe:	2201      	movs	r2, #1
+ 8018c00:	701a      	strb	r2, [r3, #0]
+    MIB2_STATS_INC(mib2.tcpactiveopens);
+
+    tcp_output(pcb);
+ 8018c02:	68f8      	ldr	r0, [r7, #12]
+ 8018c04:	f004 fbda 	bl	801d3bc <tcp_output>
+  }
+  return ret;
+ 8018c08:	f997 3013 	ldrsb.w	r3, [r7, #19]
+}
+ 8018c0c:	4618      	mov	r0, r3
+ 8018c0e:	3728      	adds	r7, #40	; 0x28
+ 8018c10:	46bd      	mov	sp, r7
+ 8018c12:	bd80      	pop	{r7, pc}
+ 8018c14:	08024ba8 	.word	0x08024ba8
+ 8018c18:	08024e84 	.word	0x08024e84
+ 8018c1c:	08024bec 	.word	0x08024bec
+ 8018c20:	08024ea0 	.word	0x08024ea0
+ 8018c24:	08024ebc 	.word	0x08024ebc
+ 8018c28:	2401a484 	.word	0x2401a484
+ 8018c2c:	2401a48c 	.word	0x2401a48c
+ 8018c30:	2401a494 	.word	0x2401a494
+
+08018c34 <tcp_slowtmr>:
+ *
+ * Automatically called from tcp_tmr().
+ */
+void
+tcp_slowtmr(void)
+{
+ 8018c34:	b5b0      	push	{r4, r5, r7, lr}
+ 8018c36:	b090      	sub	sp, #64	; 0x40
+ 8018c38:	af04      	add	r7, sp, #16
+  tcpwnd_size_t eff_wnd;
+  u8_t pcb_remove;      /* flag if a PCB should be removed */
+  u8_t pcb_reset;       /* flag if a RST should be sent when removing */
+  err_t err;
+
+  err = ERR_OK;
+ 8018c3a:	2300      	movs	r3, #0
+ 8018c3c:	f887 3025 	strb.w	r3, [r7, #37]	; 0x25
+
+  ++tcp_ticks;
+ 8018c40:	4b94      	ldr	r3, [pc, #592]	; (8018e94 <tcp_slowtmr+0x260>)
+ 8018c42:	681b      	ldr	r3, [r3, #0]
+ 8018c44:	3301      	adds	r3, #1
+ 8018c46:	4a93      	ldr	r2, [pc, #588]	; (8018e94 <tcp_slowtmr+0x260>)
+ 8018c48:	6013      	str	r3, [r2, #0]
+  ++tcp_timer_ctr;
+ 8018c4a:	4b93      	ldr	r3, [pc, #588]	; (8018e98 <tcp_slowtmr+0x264>)
+ 8018c4c:	781b      	ldrb	r3, [r3, #0]
+ 8018c4e:	3301      	adds	r3, #1
+ 8018c50:	b2da      	uxtb	r2, r3
+ 8018c52:	4b91      	ldr	r3, [pc, #580]	; (8018e98 <tcp_slowtmr+0x264>)
+ 8018c54:	701a      	strb	r2, [r3, #0]
+
+tcp_slowtmr_start:
+  /* Steps through all of the active PCBs. */
+  prev = NULL;
+ 8018c56:	2300      	movs	r3, #0
+ 8018c58:	62bb      	str	r3, [r7, #40]	; 0x28
+  pcb = tcp_active_pcbs;
+ 8018c5a:	4b90      	ldr	r3, [pc, #576]	; (8018e9c <tcp_slowtmr+0x268>)
+ 8018c5c:	681b      	ldr	r3, [r3, #0]
+ 8018c5e:	62fb      	str	r3, [r7, #44]	; 0x2c
+  if (pcb == NULL) {
+    LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: no active pcbs\n"));
+  }
+  while (pcb != NULL) {
+ 8018c60:	e29d      	b.n	801919e <tcp_slowtmr+0x56a>
+    LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: processing active pcb\n"));
+    LWIP_ASSERT("tcp_slowtmr: active pcb->state != CLOSED\n", pcb->state != CLOSED);
+ 8018c62:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 8018c64:	7d1b      	ldrb	r3, [r3, #20]
+ 8018c66:	2b00      	cmp	r3, #0
+ 8018c68:	d106      	bne.n	8018c78 <tcp_slowtmr+0x44>
+ 8018c6a:	4b8d      	ldr	r3, [pc, #564]	; (8018ea0 <tcp_slowtmr+0x26c>)
+ 8018c6c:	f240 42be 	movw	r2, #1214	; 0x4be
+ 8018c70:	498c      	ldr	r1, [pc, #560]	; (8018ea4 <tcp_slowtmr+0x270>)
+ 8018c72:	488d      	ldr	r0, [pc, #564]	; (8018ea8 <tcp_slowtmr+0x274>)
+ 8018c74:	f008 fe88 	bl	8021988 <iprintf>
+    LWIP_ASSERT("tcp_slowtmr: active pcb->state != LISTEN\n", pcb->state != LISTEN);
+ 8018c78:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 8018c7a:	7d1b      	ldrb	r3, [r3, #20]
+ 8018c7c:	2b01      	cmp	r3, #1
+ 8018c7e:	d106      	bne.n	8018c8e <tcp_slowtmr+0x5a>
+ 8018c80:	4b87      	ldr	r3, [pc, #540]	; (8018ea0 <tcp_slowtmr+0x26c>)
+ 8018c82:	f240 42bf 	movw	r2, #1215	; 0x4bf
+ 8018c86:	4989      	ldr	r1, [pc, #548]	; (8018eac <tcp_slowtmr+0x278>)
+ 8018c88:	4887      	ldr	r0, [pc, #540]	; (8018ea8 <tcp_slowtmr+0x274>)
+ 8018c8a:	f008 fe7d 	bl	8021988 <iprintf>
+    LWIP_ASSERT("tcp_slowtmr: active pcb->state != TIME-WAIT\n", pcb->state != TIME_WAIT);
+ 8018c8e:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 8018c90:	7d1b      	ldrb	r3, [r3, #20]
+ 8018c92:	2b0a      	cmp	r3, #10
+ 8018c94:	d106      	bne.n	8018ca4 <tcp_slowtmr+0x70>
+ 8018c96:	4b82      	ldr	r3, [pc, #520]	; (8018ea0 <tcp_slowtmr+0x26c>)
+ 8018c98:	f44f 6298 	mov.w	r2, #1216	; 0x4c0
+ 8018c9c:	4984      	ldr	r1, [pc, #528]	; (8018eb0 <tcp_slowtmr+0x27c>)
+ 8018c9e:	4882      	ldr	r0, [pc, #520]	; (8018ea8 <tcp_slowtmr+0x274>)
+ 8018ca0:	f008 fe72 	bl	8021988 <iprintf>
+    if (pcb->last_timer == tcp_timer_ctr) {
+ 8018ca4:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 8018ca6:	7f9a      	ldrb	r2, [r3, #30]
+ 8018ca8:	4b7b      	ldr	r3, [pc, #492]	; (8018e98 <tcp_slowtmr+0x264>)
+ 8018caa:	781b      	ldrb	r3, [r3, #0]
+ 8018cac:	429a      	cmp	r2, r3
+ 8018cae:	d105      	bne.n	8018cbc <tcp_slowtmr+0x88>
+      /* skip this pcb, we have already processed it */
+      prev = pcb;
+ 8018cb0:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 8018cb2:	62bb      	str	r3, [r7, #40]	; 0x28
+      pcb = pcb->next;
+ 8018cb4:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 8018cb6:	68db      	ldr	r3, [r3, #12]
+ 8018cb8:	62fb      	str	r3, [r7, #44]	; 0x2c
+      continue;
+ 8018cba:	e270      	b.n	801919e <tcp_slowtmr+0x56a>
+    }
+    pcb->last_timer = tcp_timer_ctr;
+ 8018cbc:	4b76      	ldr	r3, [pc, #472]	; (8018e98 <tcp_slowtmr+0x264>)
+ 8018cbe:	781a      	ldrb	r2, [r3, #0]
+ 8018cc0:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 8018cc2:	779a      	strb	r2, [r3, #30]
+
+    pcb_remove = 0;
+ 8018cc4:	2300      	movs	r3, #0
+ 8018cc6:	f887 3027 	strb.w	r3, [r7, #39]	; 0x27
+    pcb_reset = 0;
+ 8018cca:	2300      	movs	r3, #0
+ 8018ccc:	f887 3026 	strb.w	r3, [r7, #38]	; 0x26
+
+    if (pcb->state == SYN_SENT && pcb->nrtx >= TCP_SYNMAXRTX) {
+ 8018cd0:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 8018cd2:	7d1b      	ldrb	r3, [r3, #20]
+ 8018cd4:	2b02      	cmp	r3, #2
+ 8018cd6:	d10a      	bne.n	8018cee <tcp_slowtmr+0xba>
+ 8018cd8:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 8018cda:	f893 3042 	ldrb.w	r3, [r3, #66]	; 0x42
+ 8018cde:	2b05      	cmp	r3, #5
+ 8018ce0:	d905      	bls.n	8018cee <tcp_slowtmr+0xba>
+      ++pcb_remove;
+ 8018ce2:	f897 3027 	ldrb.w	r3, [r7, #39]	; 0x27
+ 8018ce6:	3301      	adds	r3, #1
+ 8018ce8:	f887 3027 	strb.w	r3, [r7, #39]	; 0x27
+      LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: max SYN retries reached\n"));
+ 8018cec:	e11e      	b.n	8018f2c <tcp_slowtmr+0x2f8>
+    } else if (pcb->nrtx >= TCP_MAXRTX) {
+ 8018cee:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 8018cf0:	f893 3042 	ldrb.w	r3, [r3, #66]	; 0x42
+ 8018cf4:	2b0b      	cmp	r3, #11
+ 8018cf6:	d905      	bls.n	8018d04 <tcp_slowtmr+0xd0>
+      ++pcb_remove;
+ 8018cf8:	f897 3027 	ldrb.w	r3, [r7, #39]	; 0x27
+ 8018cfc:	3301      	adds	r3, #1
+ 8018cfe:	f887 3027 	strb.w	r3, [r7, #39]	; 0x27
+ 8018d02:	e113      	b.n	8018f2c <tcp_slowtmr+0x2f8>
+      LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: max DATA retries reached\n"));
+    } else {
+      if (pcb->persist_backoff > 0) {
+ 8018d04:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 8018d06:	f893 3099 	ldrb.w	r3, [r3, #153]	; 0x99
+ 8018d0a:	2b00      	cmp	r3, #0
+ 8018d0c:	d075      	beq.n	8018dfa <tcp_slowtmr+0x1c6>
+        LWIP_ASSERT("tcp_slowtimr: persist ticking with in-flight data", pcb->unacked == NULL);
+ 8018d0e:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 8018d10:	6f1b      	ldr	r3, [r3, #112]	; 0x70
+ 8018d12:	2b00      	cmp	r3, #0
+ 8018d14:	d006      	beq.n	8018d24 <tcp_slowtmr+0xf0>
+ 8018d16:	4b62      	ldr	r3, [pc, #392]	; (8018ea0 <tcp_slowtmr+0x26c>)
+ 8018d18:	f240 42d4 	movw	r2, #1236	; 0x4d4
+ 8018d1c:	4965      	ldr	r1, [pc, #404]	; (8018eb4 <tcp_slowtmr+0x280>)
+ 8018d1e:	4862      	ldr	r0, [pc, #392]	; (8018ea8 <tcp_slowtmr+0x274>)
+ 8018d20:	f008 fe32 	bl	8021988 <iprintf>
+        LWIP_ASSERT("tcp_slowtimr: persist ticking with empty send buffer", pcb->unsent != NULL);
+ 8018d24:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 8018d26:	6edb      	ldr	r3, [r3, #108]	; 0x6c
+ 8018d28:	2b00      	cmp	r3, #0
+ 8018d2a:	d106      	bne.n	8018d3a <tcp_slowtmr+0x106>
+ 8018d2c:	4b5c      	ldr	r3, [pc, #368]	; (8018ea0 <tcp_slowtmr+0x26c>)
+ 8018d2e:	f240 42d5 	movw	r2, #1237	; 0x4d5
+ 8018d32:	4961      	ldr	r1, [pc, #388]	; (8018eb8 <tcp_slowtmr+0x284>)
+ 8018d34:	485c      	ldr	r0, [pc, #368]	; (8018ea8 <tcp_slowtmr+0x274>)
+ 8018d36:	f008 fe27 	bl	8021988 <iprintf>
+        if (pcb->persist_probe >= TCP_MAXRTX) {
+ 8018d3a:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 8018d3c:	f893 309a 	ldrb.w	r3, [r3, #154]	; 0x9a
+ 8018d40:	2b0b      	cmp	r3, #11
+ 8018d42:	d905      	bls.n	8018d50 <tcp_slowtmr+0x11c>
+          ++pcb_remove; /* max probes reached */
+ 8018d44:	f897 3027 	ldrb.w	r3, [r7, #39]	; 0x27
+ 8018d48:	3301      	adds	r3, #1
+ 8018d4a:	f887 3027 	strb.w	r3, [r7, #39]	; 0x27
+ 8018d4e:	e0ed      	b.n	8018f2c <tcp_slowtmr+0x2f8>
+        } else {
+          u8_t backoff_cnt = tcp_persist_backoff[pcb->persist_backoff - 1];
+ 8018d50:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 8018d52:	f893 3099 	ldrb.w	r3, [r3, #153]	; 0x99
+ 8018d56:	3b01      	subs	r3, #1
+ 8018d58:	4a58      	ldr	r2, [pc, #352]	; (8018ebc <tcp_slowtmr+0x288>)
+ 8018d5a:	5cd3      	ldrb	r3, [r2, r3]
+ 8018d5c:	747b      	strb	r3, [r7, #17]
+          if (pcb->persist_cnt < backoff_cnt) {
+ 8018d5e:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 8018d60:	f893 3098 	ldrb.w	r3, [r3, #152]	; 0x98
+ 8018d64:	7c7a      	ldrb	r2, [r7, #17]
+ 8018d66:	429a      	cmp	r2, r3
+ 8018d68:	d907      	bls.n	8018d7a <tcp_slowtmr+0x146>
+            pcb->persist_cnt++;
+ 8018d6a:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 8018d6c:	f893 3098 	ldrb.w	r3, [r3, #152]	; 0x98
+ 8018d70:	3301      	adds	r3, #1
+ 8018d72:	b2da      	uxtb	r2, r3
+ 8018d74:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 8018d76:	f883 2098 	strb.w	r2, [r3, #152]	; 0x98
+          }
+          if (pcb->persist_cnt >= backoff_cnt) {
+ 8018d7a:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 8018d7c:	f893 3098 	ldrb.w	r3, [r3, #152]	; 0x98
+ 8018d80:	7c7a      	ldrb	r2, [r7, #17]
+ 8018d82:	429a      	cmp	r2, r3
+ 8018d84:	f200 80d2 	bhi.w	8018f2c <tcp_slowtmr+0x2f8>
+            int next_slot = 1; /* increment timer to next slot */
+ 8018d88:	2301      	movs	r3, #1
+ 8018d8a:	623b      	str	r3, [r7, #32]
+            /* If snd_wnd is zero, send 1 byte probes */
+            if (pcb->snd_wnd == 0) {
+ 8018d8c:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 8018d8e:	f8b3 3060 	ldrh.w	r3, [r3, #96]	; 0x60
+ 8018d92:	2b00      	cmp	r3, #0
+ 8018d94:	d108      	bne.n	8018da8 <tcp_slowtmr+0x174>
+              if (tcp_zero_window_probe(pcb) != ERR_OK) {
+ 8018d96:	6af8      	ldr	r0, [r7, #44]	; 0x2c
+ 8018d98:	f005 f9c4 	bl	801e124 <tcp_zero_window_probe>
+ 8018d9c:	4603      	mov	r3, r0
+ 8018d9e:	2b00      	cmp	r3, #0
+ 8018da0:	d014      	beq.n	8018dcc <tcp_slowtmr+0x198>
+                next_slot = 0; /* try probe again with current slot */
+ 8018da2:	2300      	movs	r3, #0
+ 8018da4:	623b      	str	r3, [r7, #32]
+ 8018da6:	e011      	b.n	8018dcc <tcp_slowtmr+0x198>
+              }
+              /* snd_wnd not fully closed, split unsent head and fill window */
+            } else {
+              if (tcp_split_unsent_seg(pcb, (u16_t)pcb->snd_wnd) == ERR_OK) {
+ 8018da8:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 8018daa:	f8b3 3060 	ldrh.w	r3, [r3, #96]	; 0x60
+ 8018dae:	4619      	mov	r1, r3
+ 8018db0:	6af8      	ldr	r0, [r7, #44]	; 0x2c
+ 8018db2:	f004 f879 	bl	801cea8 <tcp_split_unsent_seg>
+ 8018db6:	4603      	mov	r3, r0
+ 8018db8:	2b00      	cmp	r3, #0
+ 8018dba:	d107      	bne.n	8018dcc <tcp_slowtmr+0x198>
+                if (tcp_output(pcb) == ERR_OK) {
+ 8018dbc:	6af8      	ldr	r0, [r7, #44]	; 0x2c
+ 8018dbe:	f004 fafd 	bl	801d3bc <tcp_output>
+ 8018dc2:	4603      	mov	r3, r0
+ 8018dc4:	2b00      	cmp	r3, #0
+ 8018dc6:	d101      	bne.n	8018dcc <tcp_slowtmr+0x198>
+                  /* sending will cancel persist timer, else retry with current slot */
+                  next_slot = 0;
+ 8018dc8:	2300      	movs	r3, #0
+ 8018dca:	623b      	str	r3, [r7, #32]
+                }
+              }
+            }
+            if (next_slot) {
+ 8018dcc:	6a3b      	ldr	r3, [r7, #32]
+ 8018dce:	2b00      	cmp	r3, #0
+ 8018dd0:	f000 80ac 	beq.w	8018f2c <tcp_slowtmr+0x2f8>
+              pcb->persist_cnt = 0;
+ 8018dd4:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 8018dd6:	2200      	movs	r2, #0
+ 8018dd8:	f883 2098 	strb.w	r2, [r3, #152]	; 0x98
+              if (pcb->persist_backoff < sizeof(tcp_persist_backoff)) {
+ 8018ddc:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 8018dde:	f893 3099 	ldrb.w	r3, [r3, #153]	; 0x99
+ 8018de2:	2b06      	cmp	r3, #6
+ 8018de4:	f200 80a2 	bhi.w	8018f2c <tcp_slowtmr+0x2f8>
+                pcb->persist_backoff++;
+ 8018de8:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 8018dea:	f893 3099 	ldrb.w	r3, [r3, #153]	; 0x99
+ 8018dee:	3301      	adds	r3, #1
+ 8018df0:	b2da      	uxtb	r2, r3
+ 8018df2:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 8018df4:	f883 2099 	strb.w	r2, [r3, #153]	; 0x99
+ 8018df8:	e098      	b.n	8018f2c <tcp_slowtmr+0x2f8>
+            }
+          }
+        }
+      } else {
+        /* Increase the retransmission timer if it is running */
+        if ((pcb->rtime >= 0) && (pcb->rtime < 0x7FFF)) {
+ 8018dfa:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 8018dfc:	f9b3 3030 	ldrsh.w	r3, [r3, #48]	; 0x30
+ 8018e00:	2b00      	cmp	r3, #0
+ 8018e02:	db0f      	blt.n	8018e24 <tcp_slowtmr+0x1f0>
+ 8018e04:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 8018e06:	f9b3 3030 	ldrsh.w	r3, [r3, #48]	; 0x30
+ 8018e0a:	f647 72ff 	movw	r2, #32767	; 0x7fff
+ 8018e0e:	4293      	cmp	r3, r2
+ 8018e10:	d008      	beq.n	8018e24 <tcp_slowtmr+0x1f0>
+          ++pcb->rtime;
+ 8018e12:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 8018e14:	f9b3 3030 	ldrsh.w	r3, [r3, #48]	; 0x30
+ 8018e18:	b29b      	uxth	r3, r3
+ 8018e1a:	3301      	adds	r3, #1
+ 8018e1c:	b29b      	uxth	r3, r3
+ 8018e1e:	b21a      	sxth	r2, r3
+ 8018e20:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 8018e22:	861a      	strh	r2, [r3, #48]	; 0x30
+        }
+
+        if (pcb->rtime >= pcb->rto) {
+ 8018e24:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 8018e26:	f9b3 2030 	ldrsh.w	r2, [r3, #48]	; 0x30
+ 8018e2a:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 8018e2c:	f9b3 3040 	ldrsh.w	r3, [r3, #64]	; 0x40
+ 8018e30:	429a      	cmp	r2, r3
+ 8018e32:	db7b      	blt.n	8018f2c <tcp_slowtmr+0x2f8>
+                                      " pcb->rto %"S16_F"\n",
+                                      pcb->rtime, pcb->rto));
+          /* If prepare phase fails but we have unsent data but no unacked data,
+             still execute the backoff calculations below, as this means we somehow
+             failed to send segment. */
+          if ((tcp_rexmit_rto_prepare(pcb) == ERR_OK) || ((pcb->unacked == NULL) && (pcb->unsent != NULL))) {
+ 8018e34:	6af8      	ldr	r0, [r7, #44]	; 0x2c
+ 8018e36:	f004 fdb7 	bl	801d9a8 <tcp_rexmit_rto_prepare>
+ 8018e3a:	4603      	mov	r3, r0
+ 8018e3c:	2b00      	cmp	r3, #0
+ 8018e3e:	d007      	beq.n	8018e50 <tcp_slowtmr+0x21c>
+ 8018e40:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 8018e42:	6f1b      	ldr	r3, [r3, #112]	; 0x70
+ 8018e44:	2b00      	cmp	r3, #0
+ 8018e46:	d171      	bne.n	8018f2c <tcp_slowtmr+0x2f8>
+ 8018e48:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 8018e4a:	6edb      	ldr	r3, [r3, #108]	; 0x6c
+ 8018e4c:	2b00      	cmp	r3, #0
+ 8018e4e:	d06d      	beq.n	8018f2c <tcp_slowtmr+0x2f8>
+            /* Double retransmission time-out unless we are trying to
+             * connect to somebody (i.e., we are in SYN_SENT). */
+            if (pcb->state != SYN_SENT) {
+ 8018e50:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 8018e52:	7d1b      	ldrb	r3, [r3, #20]
+ 8018e54:	2b02      	cmp	r3, #2
+ 8018e56:	d03a      	beq.n	8018ece <tcp_slowtmr+0x29a>
+              u8_t backoff_idx = LWIP_MIN(pcb->nrtx, sizeof(tcp_backoff) - 1);
+ 8018e58:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 8018e5a:	f893 3042 	ldrb.w	r3, [r3, #66]	; 0x42
+ 8018e5e:	2b0c      	cmp	r3, #12
+ 8018e60:	bf28      	it	cs
+ 8018e62:	230c      	movcs	r3, #12
+ 8018e64:	76fb      	strb	r3, [r7, #27]
+              int calc_rto = ((pcb->sa >> 3) + pcb->sv) << tcp_backoff[backoff_idx];
+ 8018e66:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 8018e68:	f9b3 303c 	ldrsh.w	r3, [r3, #60]	; 0x3c
+ 8018e6c:	10db      	asrs	r3, r3, #3
+ 8018e6e:	b21b      	sxth	r3, r3
+ 8018e70:	461a      	mov	r2, r3
+ 8018e72:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 8018e74:	f9b3 303e 	ldrsh.w	r3, [r3, #62]	; 0x3e
+ 8018e78:	4413      	add	r3, r2
+ 8018e7a:	7efa      	ldrb	r2, [r7, #27]
+ 8018e7c:	4910      	ldr	r1, [pc, #64]	; (8018ec0 <tcp_slowtmr+0x28c>)
+ 8018e7e:	5c8a      	ldrb	r2, [r1, r2]
+ 8018e80:	4093      	lsls	r3, r2
+ 8018e82:	617b      	str	r3, [r7, #20]
+              pcb->rto = (s16_t)LWIP_MIN(calc_rto, 0x7FFF);
+ 8018e84:	697b      	ldr	r3, [r7, #20]
+ 8018e86:	f647 72fe 	movw	r2, #32766	; 0x7ffe
+ 8018e8a:	4293      	cmp	r3, r2
+ 8018e8c:	dc1a      	bgt.n	8018ec4 <tcp_slowtmr+0x290>
+ 8018e8e:	697b      	ldr	r3, [r7, #20]
+ 8018e90:	b21a      	sxth	r2, r3
+ 8018e92:	e019      	b.n	8018ec8 <tcp_slowtmr+0x294>
+ 8018e94:	2401a480 	.word	0x2401a480
+ 8018e98:	2401a496 	.word	0x2401a496
+ 8018e9c:	2401a48c 	.word	0x2401a48c
+ 8018ea0:	08024ba8 	.word	0x08024ba8
+ 8018ea4:	08024eec 	.word	0x08024eec
+ 8018ea8:	08024bec 	.word	0x08024bec
+ 8018eac:	08024f18 	.word	0x08024f18
+ 8018eb0:	08024f44 	.word	0x08024f44
+ 8018eb4:	08024f74 	.word	0x08024f74
+ 8018eb8:	08024fa8 	.word	0x08024fa8
+ 8018ebc:	08026cbc 	.word	0x08026cbc
+ 8018ec0:	08026cac 	.word	0x08026cac
+ 8018ec4:	f647 72ff 	movw	r2, #32767	; 0x7fff
+ 8018ec8:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 8018eca:	f8a3 2040 	strh.w	r2, [r3, #64]	; 0x40
+            }
+
+            /* Reset the retransmission timer. */
+            pcb->rtime = 0;
+ 8018ece:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 8018ed0:	2200      	movs	r2, #0
+ 8018ed2:	861a      	strh	r2, [r3, #48]	; 0x30
+
+            /* Reduce congestion window and ssthresh. */
+            eff_wnd = LWIP_MIN(pcb->cwnd, pcb->snd_wnd);
+ 8018ed4:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 8018ed6:	f8b3 2060 	ldrh.w	r2, [r3, #96]	; 0x60
+ 8018eda:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 8018edc:	f8b3 3048 	ldrh.w	r3, [r3, #72]	; 0x48
+ 8018ee0:	4293      	cmp	r3, r2
+ 8018ee2:	bf28      	it	cs
+ 8018ee4:	4613      	movcs	r3, r2
+ 8018ee6:	827b      	strh	r3, [r7, #18]
+            pcb->ssthresh = eff_wnd >> 1;
+ 8018ee8:	8a7b      	ldrh	r3, [r7, #18]
+ 8018eea:	085b      	lsrs	r3, r3, #1
+ 8018eec:	b29a      	uxth	r2, r3
+ 8018eee:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 8018ef0:	f8a3 204a 	strh.w	r2, [r3, #74]	; 0x4a
+            if (pcb->ssthresh < (tcpwnd_size_t)(pcb->mss << 1)) {
+ 8018ef4:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 8018ef6:	f8b3 204a 	ldrh.w	r2, [r3, #74]	; 0x4a
+ 8018efa:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 8018efc:	8e5b      	ldrh	r3, [r3, #50]	; 0x32
+ 8018efe:	005b      	lsls	r3, r3, #1
+ 8018f00:	b29b      	uxth	r3, r3
+ 8018f02:	429a      	cmp	r2, r3
+ 8018f04:	d206      	bcs.n	8018f14 <tcp_slowtmr+0x2e0>
+              pcb->ssthresh = (tcpwnd_size_t)(pcb->mss << 1);
+ 8018f06:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 8018f08:	8e5b      	ldrh	r3, [r3, #50]	; 0x32
+ 8018f0a:	005b      	lsls	r3, r3, #1
+ 8018f0c:	b29a      	uxth	r2, r3
+ 8018f0e:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 8018f10:	f8a3 204a 	strh.w	r2, [r3, #74]	; 0x4a
+            }
+            pcb->cwnd = pcb->mss;
+ 8018f14:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 8018f16:	8e5a      	ldrh	r2, [r3, #50]	; 0x32
+ 8018f18:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 8018f1a:	f8a3 2048 	strh.w	r2, [r3, #72]	; 0x48
+            LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_slowtmr: cwnd %"TCPWNDSIZE_F
+                                         " ssthresh %"TCPWNDSIZE_F"\n",
+                                         pcb->cwnd, pcb->ssthresh));
+            pcb->bytes_acked = 0;
+ 8018f1e:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 8018f20:	2200      	movs	r2, #0
+ 8018f22:	f8a3 206a 	strh.w	r2, [r3, #106]	; 0x6a
+
+            /* The following needs to be called AFTER cwnd is set to one
+               mss - STJ */
+            tcp_rexmit_rto_commit(pcb);
+ 8018f26:	6af8      	ldr	r0, [r7, #44]	; 0x2c
+ 8018f28:	f004 fdb8 	bl	801da9c <tcp_rexmit_rto_commit>
+          }
+        }
+      }
+    }
+    /* Check if this PCB has stayed too long in FIN-WAIT-2 */
+    if (pcb->state == FIN_WAIT_2) {
+ 8018f2c:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 8018f2e:	7d1b      	ldrb	r3, [r3, #20]
+ 8018f30:	2b06      	cmp	r3, #6
+ 8018f32:	d111      	bne.n	8018f58 <tcp_slowtmr+0x324>
+      /* If this PCB is in FIN_WAIT_2 because of SHUT_WR don't let it time out. */
+      if (pcb->flags & TF_RXCLOSED) {
+ 8018f34:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 8018f36:	8b5b      	ldrh	r3, [r3, #26]
+ 8018f38:	f003 0310 	and.w	r3, r3, #16
+ 8018f3c:	2b00      	cmp	r3, #0
+ 8018f3e:	d00b      	beq.n	8018f58 <tcp_slowtmr+0x324>
+        /* PCB was fully closed (either through close() or SHUT_RDWR):
+           normal FIN-WAIT timeout handling. */
+        if ((u32_t)(tcp_ticks - pcb->tmr) >
+ 8018f40:	4b9c      	ldr	r3, [pc, #624]	; (80191b4 <tcp_slowtmr+0x580>)
+ 8018f42:	681a      	ldr	r2, [r3, #0]
+ 8018f44:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 8018f46:	6a1b      	ldr	r3, [r3, #32]
+ 8018f48:	1ad3      	subs	r3, r2, r3
+ 8018f4a:	2b28      	cmp	r3, #40	; 0x28
+ 8018f4c:	d904      	bls.n	8018f58 <tcp_slowtmr+0x324>
+            TCP_FIN_WAIT_TIMEOUT / TCP_SLOW_INTERVAL) {
+          ++pcb_remove;
+ 8018f4e:	f897 3027 	ldrb.w	r3, [r7, #39]	; 0x27
+ 8018f52:	3301      	adds	r3, #1
+ 8018f54:	f887 3027 	strb.w	r3, [r7, #39]	; 0x27
+        }
+      }
+    }
+
+    /* Check if KEEPALIVE should be sent */
+    if (ip_get_option(pcb, SOF_KEEPALIVE) &&
+ 8018f58:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 8018f5a:	7a5b      	ldrb	r3, [r3, #9]
+ 8018f5c:	f003 0308 	and.w	r3, r3, #8
+ 8018f60:	2b00      	cmp	r3, #0
+ 8018f62:	d04a      	beq.n	8018ffa <tcp_slowtmr+0x3c6>
+        ((pcb->state == ESTABLISHED) ||
+ 8018f64:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 8018f66:	7d1b      	ldrb	r3, [r3, #20]
+    if (ip_get_option(pcb, SOF_KEEPALIVE) &&
+ 8018f68:	2b04      	cmp	r3, #4
+ 8018f6a:	d003      	beq.n	8018f74 <tcp_slowtmr+0x340>
+         (pcb->state == CLOSE_WAIT))) {
+ 8018f6c:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 8018f6e:	7d1b      	ldrb	r3, [r3, #20]
+        ((pcb->state == ESTABLISHED) ||
+ 8018f70:	2b07      	cmp	r3, #7
+ 8018f72:	d142      	bne.n	8018ffa <tcp_slowtmr+0x3c6>
+      if ((u32_t)(tcp_ticks - pcb->tmr) >
+ 8018f74:	4b8f      	ldr	r3, [pc, #572]	; (80191b4 <tcp_slowtmr+0x580>)
+ 8018f76:	681a      	ldr	r2, [r3, #0]
+ 8018f78:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 8018f7a:	6a1b      	ldr	r3, [r3, #32]
+ 8018f7c:	1ad2      	subs	r2, r2, r3
+          (pcb->keep_idle + TCP_KEEP_DUR(pcb)) / TCP_SLOW_INTERVAL) {
+ 8018f7e:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 8018f80:	f8d3 1094 	ldr.w	r1, [r3, #148]	; 0x94
+ 8018f84:	4b8c      	ldr	r3, [pc, #560]	; (80191b8 <tcp_slowtmr+0x584>)
+ 8018f86:	440b      	add	r3, r1
+ 8018f88:	498c      	ldr	r1, [pc, #560]	; (80191bc <tcp_slowtmr+0x588>)
+ 8018f8a:	fba1 1303 	umull	r1, r3, r1, r3
+ 8018f8e:	095b      	lsrs	r3, r3, #5
+      if ((u32_t)(tcp_ticks - pcb->tmr) >
+ 8018f90:	429a      	cmp	r2, r3
+ 8018f92:	d90a      	bls.n	8018faa <tcp_slowtmr+0x376>
+        LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: KEEPALIVE timeout. Aborting connection to "));
+        ip_addr_debug_print_val(TCP_DEBUG, pcb->remote_ip);
+        LWIP_DEBUGF(TCP_DEBUG, ("\n"));
+
+        ++pcb_remove;
+ 8018f94:	f897 3027 	ldrb.w	r3, [r7, #39]	; 0x27
+ 8018f98:	3301      	adds	r3, #1
+ 8018f9a:	f887 3027 	strb.w	r3, [r7, #39]	; 0x27
+        ++pcb_reset;
+ 8018f9e:	f897 3026 	ldrb.w	r3, [r7, #38]	; 0x26
+ 8018fa2:	3301      	adds	r3, #1
+ 8018fa4:	f887 3026 	strb.w	r3, [r7, #38]	; 0x26
+ 8018fa8:	e027      	b.n	8018ffa <tcp_slowtmr+0x3c6>
+      } else if ((u32_t)(tcp_ticks - pcb->tmr) >
+ 8018faa:	4b82      	ldr	r3, [pc, #520]	; (80191b4 <tcp_slowtmr+0x580>)
+ 8018fac:	681a      	ldr	r2, [r3, #0]
+ 8018fae:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 8018fb0:	6a1b      	ldr	r3, [r3, #32]
+ 8018fb2:	1ad2      	subs	r2, r2, r3
+                 (pcb->keep_idle + pcb->keep_cnt_sent * TCP_KEEP_INTVL(pcb))
+ 8018fb4:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 8018fb6:	f8d3 1094 	ldr.w	r1, [r3, #148]	; 0x94
+ 8018fba:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 8018fbc:	f893 309b 	ldrb.w	r3, [r3, #155]	; 0x9b
+ 8018fc0:	4618      	mov	r0, r3
+ 8018fc2:	4b7f      	ldr	r3, [pc, #508]	; (80191c0 <tcp_slowtmr+0x58c>)
+ 8018fc4:	fb00 f303 	mul.w	r3, r0, r3
+ 8018fc8:	440b      	add	r3, r1
+                 / TCP_SLOW_INTERVAL) {
+ 8018fca:	497c      	ldr	r1, [pc, #496]	; (80191bc <tcp_slowtmr+0x588>)
+ 8018fcc:	fba1 1303 	umull	r1, r3, r1, r3
+ 8018fd0:	095b      	lsrs	r3, r3, #5
+      } else if ((u32_t)(tcp_ticks - pcb->tmr) >
+ 8018fd2:	429a      	cmp	r2, r3
+ 8018fd4:	d911      	bls.n	8018ffa <tcp_slowtmr+0x3c6>
+        err = tcp_keepalive(pcb);
+ 8018fd6:	6af8      	ldr	r0, [r7, #44]	; 0x2c
+ 8018fd8:	f005 f864 	bl	801e0a4 <tcp_keepalive>
+ 8018fdc:	4603      	mov	r3, r0
+ 8018fde:	f887 3025 	strb.w	r3, [r7, #37]	; 0x25
+        if (err == ERR_OK) {
+ 8018fe2:	f997 3025 	ldrsb.w	r3, [r7, #37]	; 0x25
+ 8018fe6:	2b00      	cmp	r3, #0
+ 8018fe8:	d107      	bne.n	8018ffa <tcp_slowtmr+0x3c6>
+          pcb->keep_cnt_sent++;
+ 8018fea:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 8018fec:	f893 309b 	ldrb.w	r3, [r3, #155]	; 0x9b
+ 8018ff0:	3301      	adds	r3, #1
+ 8018ff2:	b2da      	uxtb	r2, r3
+ 8018ff4:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 8018ff6:	f883 209b 	strb.w	r2, [r3, #155]	; 0x9b
+
+    /* If this PCB has queued out of sequence data, but has been
+       inactive for too long, will drop the data (it will eventually
+       be retransmitted). */
+#if TCP_QUEUE_OOSEQ
+    if (pcb->ooseq != NULL &&
+ 8018ffa:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 8018ffc:	6f5b      	ldr	r3, [r3, #116]	; 0x74
+ 8018ffe:	2b00      	cmp	r3, #0
+ 8019000:	d011      	beq.n	8019026 <tcp_slowtmr+0x3f2>
+        (tcp_ticks - pcb->tmr >= (u32_t)pcb->rto * TCP_OOSEQ_TIMEOUT)) {
+ 8019002:	4b6c      	ldr	r3, [pc, #432]	; (80191b4 <tcp_slowtmr+0x580>)
+ 8019004:	681a      	ldr	r2, [r3, #0]
+ 8019006:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 8019008:	6a1b      	ldr	r3, [r3, #32]
+ 801900a:	1ad2      	subs	r2, r2, r3
+ 801900c:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 801900e:	f9b3 3040 	ldrsh.w	r3, [r3, #64]	; 0x40
+ 8019012:	4619      	mov	r1, r3
+ 8019014:	460b      	mov	r3, r1
+ 8019016:	005b      	lsls	r3, r3, #1
+ 8019018:	440b      	add	r3, r1
+ 801901a:	005b      	lsls	r3, r3, #1
+    if (pcb->ooseq != NULL &&
+ 801901c:	429a      	cmp	r2, r3
+ 801901e:	d302      	bcc.n	8019026 <tcp_slowtmr+0x3f2>
+      LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_slowtmr: dropping OOSEQ queued data\n"));
+      tcp_free_ooseq(pcb);
+ 8019020:	6af8      	ldr	r0, [r7, #44]	; 0x2c
+ 8019022:	f000 feb3 	bl	8019d8c <tcp_free_ooseq>
+    }
+#endif /* TCP_QUEUE_OOSEQ */
+
+    /* Check if this PCB has stayed too long in SYN-RCVD */
+    if (pcb->state == SYN_RCVD) {
+ 8019026:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 8019028:	7d1b      	ldrb	r3, [r3, #20]
+ 801902a:	2b03      	cmp	r3, #3
+ 801902c:	d10b      	bne.n	8019046 <tcp_slowtmr+0x412>
+      if ((u32_t)(tcp_ticks - pcb->tmr) >
+ 801902e:	4b61      	ldr	r3, [pc, #388]	; (80191b4 <tcp_slowtmr+0x580>)
+ 8019030:	681a      	ldr	r2, [r3, #0]
+ 8019032:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 8019034:	6a1b      	ldr	r3, [r3, #32]
+ 8019036:	1ad3      	subs	r3, r2, r3
+ 8019038:	2b28      	cmp	r3, #40	; 0x28
+ 801903a:	d904      	bls.n	8019046 <tcp_slowtmr+0x412>
+          TCP_SYN_RCVD_TIMEOUT / TCP_SLOW_INTERVAL) {
+        ++pcb_remove;
+ 801903c:	f897 3027 	ldrb.w	r3, [r7, #39]	; 0x27
+ 8019040:	3301      	adds	r3, #1
+ 8019042:	f887 3027 	strb.w	r3, [r7, #39]	; 0x27
+        LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: removing pcb stuck in SYN-RCVD\n"));
+      }
+    }
+
+    /* Check if this PCB has stayed too long in LAST-ACK */
+    if (pcb->state == LAST_ACK) {
+ 8019046:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 8019048:	7d1b      	ldrb	r3, [r3, #20]
+ 801904a:	2b09      	cmp	r3, #9
+ 801904c:	d10b      	bne.n	8019066 <tcp_slowtmr+0x432>
+      if ((u32_t)(tcp_ticks - pcb->tmr) > 2 * TCP_MSL / TCP_SLOW_INTERVAL) {
+ 801904e:	4b59      	ldr	r3, [pc, #356]	; (80191b4 <tcp_slowtmr+0x580>)
+ 8019050:	681a      	ldr	r2, [r3, #0]
+ 8019052:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 8019054:	6a1b      	ldr	r3, [r3, #32]
+ 8019056:	1ad3      	subs	r3, r2, r3
+ 8019058:	2bf0      	cmp	r3, #240	; 0xf0
+ 801905a:	d904      	bls.n	8019066 <tcp_slowtmr+0x432>
+        ++pcb_remove;
+ 801905c:	f897 3027 	ldrb.w	r3, [r7, #39]	; 0x27
+ 8019060:	3301      	adds	r3, #1
+ 8019062:	f887 3027 	strb.w	r3, [r7, #39]	; 0x27
+        LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: removing pcb stuck in LAST-ACK\n"));
+      }
+    }
+
+    /* If the PCB should be removed, do it. */
+    if (pcb_remove) {
+ 8019066:	f897 3027 	ldrb.w	r3, [r7, #39]	; 0x27
+ 801906a:	2b00      	cmp	r3, #0
+ 801906c:	d060      	beq.n	8019130 <tcp_slowtmr+0x4fc>
+      struct tcp_pcb *pcb2;
+#if LWIP_CALLBACK_API
+      tcp_err_fn err_fn = pcb->errf;
+ 801906e:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 8019070:	f8d3 3090 	ldr.w	r3, [r3, #144]	; 0x90
+ 8019074:	60fb      	str	r3, [r7, #12]
+#endif /* LWIP_CALLBACK_API */
+      void *err_arg;
+      enum tcp_state last_state;
+      tcp_pcb_purge(pcb);
+ 8019076:	6af8      	ldr	r0, [r7, #44]	; 0x2c
+ 8019078:	f000 fcce 	bl	8019a18 <tcp_pcb_purge>
+      /* Remove PCB from tcp_active_pcbs list. */
+      if (prev != NULL) {
+ 801907c:	6abb      	ldr	r3, [r7, #40]	; 0x28
+ 801907e:	2b00      	cmp	r3, #0
+ 8019080:	d010      	beq.n	80190a4 <tcp_slowtmr+0x470>
+        LWIP_ASSERT("tcp_slowtmr: middle tcp != tcp_active_pcbs", pcb != tcp_active_pcbs);
+ 8019082:	4b50      	ldr	r3, [pc, #320]	; (80191c4 <tcp_slowtmr+0x590>)
+ 8019084:	681b      	ldr	r3, [r3, #0]
+ 8019086:	6afa      	ldr	r2, [r7, #44]	; 0x2c
+ 8019088:	429a      	cmp	r2, r3
+ 801908a:	d106      	bne.n	801909a <tcp_slowtmr+0x466>
+ 801908c:	4b4e      	ldr	r3, [pc, #312]	; (80191c8 <tcp_slowtmr+0x594>)
+ 801908e:	f240 526d 	movw	r2, #1389	; 0x56d
+ 8019092:	494e      	ldr	r1, [pc, #312]	; (80191cc <tcp_slowtmr+0x598>)
+ 8019094:	484e      	ldr	r0, [pc, #312]	; (80191d0 <tcp_slowtmr+0x59c>)
+ 8019096:	f008 fc77 	bl	8021988 <iprintf>
+        prev->next = pcb->next;
+ 801909a:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 801909c:	68da      	ldr	r2, [r3, #12]
+ 801909e:	6abb      	ldr	r3, [r7, #40]	; 0x28
+ 80190a0:	60da      	str	r2, [r3, #12]
+ 80190a2:	e00f      	b.n	80190c4 <tcp_slowtmr+0x490>
+      } else {
+        /* This PCB was the first. */
+        LWIP_ASSERT("tcp_slowtmr: first pcb == tcp_active_pcbs", tcp_active_pcbs == pcb);
+ 80190a4:	4b47      	ldr	r3, [pc, #284]	; (80191c4 <tcp_slowtmr+0x590>)
+ 80190a6:	681b      	ldr	r3, [r3, #0]
+ 80190a8:	6afa      	ldr	r2, [r7, #44]	; 0x2c
+ 80190aa:	429a      	cmp	r2, r3
+ 80190ac:	d006      	beq.n	80190bc <tcp_slowtmr+0x488>
+ 80190ae:	4b46      	ldr	r3, [pc, #280]	; (80191c8 <tcp_slowtmr+0x594>)
+ 80190b0:	f240 5271 	movw	r2, #1393	; 0x571
+ 80190b4:	4947      	ldr	r1, [pc, #284]	; (80191d4 <tcp_slowtmr+0x5a0>)
+ 80190b6:	4846      	ldr	r0, [pc, #280]	; (80191d0 <tcp_slowtmr+0x59c>)
+ 80190b8:	f008 fc66 	bl	8021988 <iprintf>
+        tcp_active_pcbs = pcb->next;
+ 80190bc:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 80190be:	68db      	ldr	r3, [r3, #12]
+ 80190c0:	4a40      	ldr	r2, [pc, #256]	; (80191c4 <tcp_slowtmr+0x590>)
+ 80190c2:	6013      	str	r3, [r2, #0]
+      }
+
+      if (pcb_reset) {
+ 80190c4:	f897 3026 	ldrb.w	r3, [r7, #38]	; 0x26
+ 80190c8:	2b00      	cmp	r3, #0
+ 80190ca:	d013      	beq.n	80190f4 <tcp_slowtmr+0x4c0>
+        tcp_rst(pcb, pcb->snd_nxt, pcb->rcv_nxt, &pcb->local_ip, &pcb->remote_ip,
+ 80190cc:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 80190ce:	6d18      	ldr	r0, [r3, #80]	; 0x50
+ 80190d0:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 80190d2:	6a5c      	ldr	r4, [r3, #36]	; 0x24
+ 80190d4:	6afd      	ldr	r5, [r7, #44]	; 0x2c
+ 80190d6:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 80190d8:	3304      	adds	r3, #4
+ 80190da:	6afa      	ldr	r2, [r7, #44]	; 0x2c
+ 80190dc:	8ad2      	ldrh	r2, [r2, #22]
+ 80190de:	6af9      	ldr	r1, [r7, #44]	; 0x2c
+ 80190e0:	8b09      	ldrh	r1, [r1, #24]
+ 80190e2:	9102      	str	r1, [sp, #8]
+ 80190e4:	9201      	str	r2, [sp, #4]
+ 80190e6:	9300      	str	r3, [sp, #0]
+ 80190e8:	462b      	mov	r3, r5
+ 80190ea:	4622      	mov	r2, r4
+ 80190ec:	4601      	mov	r1, r0
+ 80190ee:	6af8      	ldr	r0, [r7, #44]	; 0x2c
+ 80190f0:	f004 ff24 	bl	801df3c <tcp_rst>
+                pcb->local_port, pcb->remote_port);
+      }
+
+      err_arg = pcb->callback_arg;
+ 80190f4:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 80190f6:	691b      	ldr	r3, [r3, #16]
+ 80190f8:	60bb      	str	r3, [r7, #8]
+      last_state = pcb->state;
+ 80190fa:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 80190fc:	7d1b      	ldrb	r3, [r3, #20]
+ 80190fe:	71fb      	strb	r3, [r7, #7]
+      pcb2 = pcb;
+ 8019100:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 8019102:	603b      	str	r3, [r7, #0]
+      pcb = pcb->next;
+ 8019104:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 8019106:	68db      	ldr	r3, [r3, #12]
+ 8019108:	62fb      	str	r3, [r7, #44]	; 0x2c
+      tcp_free(pcb2);
+ 801910a:	6838      	ldr	r0, [r7, #0]
+ 801910c:	f7fe ffa0 	bl	8018050 <tcp_free>
+
+      tcp_active_pcbs_changed = 0;
+ 8019110:	4b31      	ldr	r3, [pc, #196]	; (80191d8 <tcp_slowtmr+0x5a4>)
+ 8019112:	2200      	movs	r2, #0
+ 8019114:	701a      	strb	r2, [r3, #0]
+      TCP_EVENT_ERR(last_state, err_fn, err_arg, ERR_ABRT);
+ 8019116:	68fb      	ldr	r3, [r7, #12]
+ 8019118:	2b00      	cmp	r3, #0
+ 801911a:	d004      	beq.n	8019126 <tcp_slowtmr+0x4f2>
+ 801911c:	68fb      	ldr	r3, [r7, #12]
+ 801911e:	f06f 010c 	mvn.w	r1, #12
+ 8019122:	68b8      	ldr	r0, [r7, #8]
+ 8019124:	4798      	blx	r3
+      if (tcp_active_pcbs_changed) {
+ 8019126:	4b2c      	ldr	r3, [pc, #176]	; (80191d8 <tcp_slowtmr+0x5a4>)
+ 8019128:	781b      	ldrb	r3, [r3, #0]
+ 801912a:	2b00      	cmp	r3, #0
+ 801912c:	d037      	beq.n	801919e <tcp_slowtmr+0x56a>
+        goto tcp_slowtmr_start;
+ 801912e:	e592      	b.n	8018c56 <tcp_slowtmr+0x22>
+      }
+    } else {
+      /* get the 'next' element now and work with 'prev' below (in case of abort) */
+      prev = pcb;
+ 8019130:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 8019132:	62bb      	str	r3, [r7, #40]	; 0x28
+      pcb = pcb->next;
+ 8019134:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 8019136:	68db      	ldr	r3, [r3, #12]
+ 8019138:	62fb      	str	r3, [r7, #44]	; 0x2c
+
+      /* We check if we should poll the connection. */
+      ++prev->polltmr;
+ 801913a:	6abb      	ldr	r3, [r7, #40]	; 0x28
+ 801913c:	7f1b      	ldrb	r3, [r3, #28]
+ 801913e:	3301      	adds	r3, #1
+ 8019140:	b2da      	uxtb	r2, r3
+ 8019142:	6abb      	ldr	r3, [r7, #40]	; 0x28
+ 8019144:	771a      	strb	r2, [r3, #28]
+      if (prev->polltmr >= prev->pollinterval) {
+ 8019146:	6abb      	ldr	r3, [r7, #40]	; 0x28
+ 8019148:	7f1a      	ldrb	r2, [r3, #28]
+ 801914a:	6abb      	ldr	r3, [r7, #40]	; 0x28
+ 801914c:	7f5b      	ldrb	r3, [r3, #29]
+ 801914e:	429a      	cmp	r2, r3
+ 8019150:	d325      	bcc.n	801919e <tcp_slowtmr+0x56a>
+        prev->polltmr = 0;
+ 8019152:	6abb      	ldr	r3, [r7, #40]	; 0x28
+ 8019154:	2200      	movs	r2, #0
+ 8019156:	771a      	strb	r2, [r3, #28]
+        LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: polling application\n"));
+        tcp_active_pcbs_changed = 0;
+ 8019158:	4b1f      	ldr	r3, [pc, #124]	; (80191d8 <tcp_slowtmr+0x5a4>)
+ 801915a:	2200      	movs	r2, #0
+ 801915c:	701a      	strb	r2, [r3, #0]
+        TCP_EVENT_POLL(prev, err);
+ 801915e:	6abb      	ldr	r3, [r7, #40]	; 0x28
+ 8019160:	f8d3 308c 	ldr.w	r3, [r3, #140]	; 0x8c
+ 8019164:	2b00      	cmp	r3, #0
+ 8019166:	d00b      	beq.n	8019180 <tcp_slowtmr+0x54c>
+ 8019168:	6abb      	ldr	r3, [r7, #40]	; 0x28
+ 801916a:	f8d3 308c 	ldr.w	r3, [r3, #140]	; 0x8c
+ 801916e:	6aba      	ldr	r2, [r7, #40]	; 0x28
+ 8019170:	6912      	ldr	r2, [r2, #16]
+ 8019172:	6ab9      	ldr	r1, [r7, #40]	; 0x28
+ 8019174:	4610      	mov	r0, r2
+ 8019176:	4798      	blx	r3
+ 8019178:	4603      	mov	r3, r0
+ 801917a:	f887 3025 	strb.w	r3, [r7, #37]	; 0x25
+ 801917e:	e002      	b.n	8019186 <tcp_slowtmr+0x552>
+ 8019180:	2300      	movs	r3, #0
+ 8019182:	f887 3025 	strb.w	r3, [r7, #37]	; 0x25
+        if (tcp_active_pcbs_changed) {
+ 8019186:	4b14      	ldr	r3, [pc, #80]	; (80191d8 <tcp_slowtmr+0x5a4>)
+ 8019188:	781b      	ldrb	r3, [r3, #0]
+ 801918a:	2b00      	cmp	r3, #0
+ 801918c:	d000      	beq.n	8019190 <tcp_slowtmr+0x55c>
+          goto tcp_slowtmr_start;
+ 801918e:	e562      	b.n	8018c56 <tcp_slowtmr+0x22>
+        }
+        /* if err == ERR_ABRT, 'prev' is already deallocated */
+        if (err == ERR_OK) {
+ 8019190:	f997 3025 	ldrsb.w	r3, [r7, #37]	; 0x25
+ 8019194:	2b00      	cmp	r3, #0
+ 8019196:	d102      	bne.n	801919e <tcp_slowtmr+0x56a>
+          tcp_output(prev);
+ 8019198:	6ab8      	ldr	r0, [r7, #40]	; 0x28
+ 801919a:	f004 f90f 	bl	801d3bc <tcp_output>
+  while (pcb != NULL) {
+ 801919e:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 80191a0:	2b00      	cmp	r3, #0
+ 80191a2:	f47f ad5e 	bne.w	8018c62 <tcp_slowtmr+0x2e>
+    }
+  }
+
+
+  /* Steps through all of the TIME-WAIT PCBs. */
+  prev = NULL;
+ 80191a6:	2300      	movs	r3, #0
+ 80191a8:	62bb      	str	r3, [r7, #40]	; 0x28
+  pcb = tcp_tw_pcbs;
+ 80191aa:	4b0c      	ldr	r3, [pc, #48]	; (80191dc <tcp_slowtmr+0x5a8>)
+ 80191ac:	681b      	ldr	r3, [r3, #0]
+ 80191ae:	62fb      	str	r3, [r7, #44]	; 0x2c
+  while (pcb != NULL) {
+ 80191b0:	e069      	b.n	8019286 <tcp_slowtmr+0x652>
+ 80191b2:	bf00      	nop
+ 80191b4:	2401a480 	.word	0x2401a480
+ 80191b8:	000a4cb8 	.word	0x000a4cb8
+ 80191bc:	10624dd3 	.word	0x10624dd3
+ 80191c0:	000124f8 	.word	0x000124f8
+ 80191c4:	2401a48c 	.word	0x2401a48c
+ 80191c8:	08024ba8 	.word	0x08024ba8
+ 80191cc:	08024fe0 	.word	0x08024fe0
+ 80191d0:	08024bec 	.word	0x08024bec
+ 80191d4:	0802500c 	.word	0x0802500c
+ 80191d8:	2401a494 	.word	0x2401a494
+ 80191dc:	2401a490 	.word	0x2401a490
+    LWIP_ASSERT("tcp_slowtmr: TIME-WAIT pcb->state == TIME-WAIT", pcb->state == TIME_WAIT);
+ 80191e0:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 80191e2:	7d1b      	ldrb	r3, [r3, #20]
+ 80191e4:	2b0a      	cmp	r3, #10
+ 80191e6:	d006      	beq.n	80191f6 <tcp_slowtmr+0x5c2>
+ 80191e8:	4b2b      	ldr	r3, [pc, #172]	; (8019298 <tcp_slowtmr+0x664>)
+ 80191ea:	f240 52a1 	movw	r2, #1441	; 0x5a1
+ 80191ee:	492b      	ldr	r1, [pc, #172]	; (801929c <tcp_slowtmr+0x668>)
+ 80191f0:	482b      	ldr	r0, [pc, #172]	; (80192a0 <tcp_slowtmr+0x66c>)
+ 80191f2:	f008 fbc9 	bl	8021988 <iprintf>
+    pcb_remove = 0;
+ 80191f6:	2300      	movs	r3, #0
+ 80191f8:	f887 3027 	strb.w	r3, [r7, #39]	; 0x27
+
+    /* Check if this PCB has stayed long enough in TIME-WAIT */
+    if ((u32_t)(tcp_ticks - pcb->tmr) > 2 * TCP_MSL / TCP_SLOW_INTERVAL) {
+ 80191fc:	4b29      	ldr	r3, [pc, #164]	; (80192a4 <tcp_slowtmr+0x670>)
+ 80191fe:	681a      	ldr	r2, [r3, #0]
+ 8019200:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 8019202:	6a1b      	ldr	r3, [r3, #32]
+ 8019204:	1ad3      	subs	r3, r2, r3
+ 8019206:	2bf0      	cmp	r3, #240	; 0xf0
+ 8019208:	d904      	bls.n	8019214 <tcp_slowtmr+0x5e0>
+      ++pcb_remove;
+ 801920a:	f897 3027 	ldrb.w	r3, [r7, #39]	; 0x27
+ 801920e:	3301      	adds	r3, #1
+ 8019210:	f887 3027 	strb.w	r3, [r7, #39]	; 0x27
+    }
+
+    /* If the PCB should be removed, do it. */
+    if (pcb_remove) {
+ 8019214:	f897 3027 	ldrb.w	r3, [r7, #39]	; 0x27
+ 8019218:	2b00      	cmp	r3, #0
+ 801921a:	d02f      	beq.n	801927c <tcp_slowtmr+0x648>
+      struct tcp_pcb *pcb2;
+      tcp_pcb_purge(pcb);
+ 801921c:	6af8      	ldr	r0, [r7, #44]	; 0x2c
+ 801921e:	f000 fbfb 	bl	8019a18 <tcp_pcb_purge>
+      /* Remove PCB from tcp_tw_pcbs list. */
+      if (prev != NULL) {
+ 8019222:	6abb      	ldr	r3, [r7, #40]	; 0x28
+ 8019224:	2b00      	cmp	r3, #0
+ 8019226:	d010      	beq.n	801924a <tcp_slowtmr+0x616>
+        LWIP_ASSERT("tcp_slowtmr: middle tcp != tcp_tw_pcbs", pcb != tcp_tw_pcbs);
+ 8019228:	4b1f      	ldr	r3, [pc, #124]	; (80192a8 <tcp_slowtmr+0x674>)
+ 801922a:	681b      	ldr	r3, [r3, #0]
+ 801922c:	6afa      	ldr	r2, [r7, #44]	; 0x2c
+ 801922e:	429a      	cmp	r2, r3
+ 8019230:	d106      	bne.n	8019240 <tcp_slowtmr+0x60c>
+ 8019232:	4b19      	ldr	r3, [pc, #100]	; (8019298 <tcp_slowtmr+0x664>)
+ 8019234:	f240 52af 	movw	r2, #1455	; 0x5af
+ 8019238:	491c      	ldr	r1, [pc, #112]	; (80192ac <tcp_slowtmr+0x678>)
+ 801923a:	4819      	ldr	r0, [pc, #100]	; (80192a0 <tcp_slowtmr+0x66c>)
+ 801923c:	f008 fba4 	bl	8021988 <iprintf>
+        prev->next = pcb->next;
+ 8019240:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 8019242:	68da      	ldr	r2, [r3, #12]
+ 8019244:	6abb      	ldr	r3, [r7, #40]	; 0x28
+ 8019246:	60da      	str	r2, [r3, #12]
+ 8019248:	e00f      	b.n	801926a <tcp_slowtmr+0x636>
+      } else {
+        /* This PCB was the first. */
+        LWIP_ASSERT("tcp_slowtmr: first pcb == tcp_tw_pcbs", tcp_tw_pcbs == pcb);
+ 801924a:	4b17      	ldr	r3, [pc, #92]	; (80192a8 <tcp_slowtmr+0x674>)
+ 801924c:	681b      	ldr	r3, [r3, #0]
+ 801924e:	6afa      	ldr	r2, [r7, #44]	; 0x2c
+ 8019250:	429a      	cmp	r2, r3
+ 8019252:	d006      	beq.n	8019262 <tcp_slowtmr+0x62e>
+ 8019254:	4b10      	ldr	r3, [pc, #64]	; (8019298 <tcp_slowtmr+0x664>)
+ 8019256:	f240 52b3 	movw	r2, #1459	; 0x5b3
+ 801925a:	4915      	ldr	r1, [pc, #84]	; (80192b0 <tcp_slowtmr+0x67c>)
+ 801925c:	4810      	ldr	r0, [pc, #64]	; (80192a0 <tcp_slowtmr+0x66c>)
+ 801925e:	f008 fb93 	bl	8021988 <iprintf>
+        tcp_tw_pcbs = pcb->next;
+ 8019262:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 8019264:	68db      	ldr	r3, [r3, #12]
+ 8019266:	4a10      	ldr	r2, [pc, #64]	; (80192a8 <tcp_slowtmr+0x674>)
+ 8019268:	6013      	str	r3, [r2, #0]
+      }
+      pcb2 = pcb;
+ 801926a:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 801926c:	61fb      	str	r3, [r7, #28]
+      pcb = pcb->next;
+ 801926e:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 8019270:	68db      	ldr	r3, [r3, #12]
+ 8019272:	62fb      	str	r3, [r7, #44]	; 0x2c
+      tcp_free(pcb2);
+ 8019274:	69f8      	ldr	r0, [r7, #28]
+ 8019276:	f7fe feeb 	bl	8018050 <tcp_free>
+ 801927a:	e004      	b.n	8019286 <tcp_slowtmr+0x652>
+    } else {
+      prev = pcb;
+ 801927c:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 801927e:	62bb      	str	r3, [r7, #40]	; 0x28
+      pcb = pcb->next;
+ 8019280:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 8019282:	68db      	ldr	r3, [r3, #12]
+ 8019284:	62fb      	str	r3, [r7, #44]	; 0x2c
+  while (pcb != NULL) {
+ 8019286:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 8019288:	2b00      	cmp	r3, #0
+ 801928a:	d1a9      	bne.n	80191e0 <tcp_slowtmr+0x5ac>
+    }
+  }
+}
+ 801928c:	bf00      	nop
+ 801928e:	bf00      	nop
+ 8019290:	3730      	adds	r7, #48	; 0x30
+ 8019292:	46bd      	mov	sp, r7
+ 8019294:	bdb0      	pop	{r4, r5, r7, pc}
+ 8019296:	bf00      	nop
+ 8019298:	08024ba8 	.word	0x08024ba8
+ 801929c:	08025038 	.word	0x08025038
+ 80192a0:	08024bec 	.word	0x08024bec
+ 80192a4:	2401a480 	.word	0x2401a480
+ 80192a8:	2401a490 	.word	0x2401a490
+ 80192ac:	08025068 	.word	0x08025068
+ 80192b0:	08025090 	.word	0x08025090
+
+080192b4 <tcp_fasttmr>:
+ *
+ * Automatically called from tcp_tmr().
+ */
+void
+tcp_fasttmr(void)
+{
+ 80192b4:	b580      	push	{r7, lr}
+ 80192b6:	b082      	sub	sp, #8
+ 80192b8:	af00      	add	r7, sp, #0
+  struct tcp_pcb *pcb;
+
+  ++tcp_timer_ctr;
+ 80192ba:	4b2d      	ldr	r3, [pc, #180]	; (8019370 <tcp_fasttmr+0xbc>)
+ 80192bc:	781b      	ldrb	r3, [r3, #0]
+ 80192be:	3301      	adds	r3, #1
+ 80192c0:	b2da      	uxtb	r2, r3
+ 80192c2:	4b2b      	ldr	r3, [pc, #172]	; (8019370 <tcp_fasttmr+0xbc>)
+ 80192c4:	701a      	strb	r2, [r3, #0]
+
+tcp_fasttmr_start:
+  pcb = tcp_active_pcbs;
+ 80192c6:	4b2b      	ldr	r3, [pc, #172]	; (8019374 <tcp_fasttmr+0xc0>)
+ 80192c8:	681b      	ldr	r3, [r3, #0]
+ 80192ca:	607b      	str	r3, [r7, #4]
+
+  while (pcb != NULL) {
+ 80192cc:	e048      	b.n	8019360 <tcp_fasttmr+0xac>
+    if (pcb->last_timer != tcp_timer_ctr) {
+ 80192ce:	687b      	ldr	r3, [r7, #4]
+ 80192d0:	7f9a      	ldrb	r2, [r3, #30]
+ 80192d2:	4b27      	ldr	r3, [pc, #156]	; (8019370 <tcp_fasttmr+0xbc>)
+ 80192d4:	781b      	ldrb	r3, [r3, #0]
+ 80192d6:	429a      	cmp	r2, r3
+ 80192d8:	d03f      	beq.n	801935a <tcp_fasttmr+0xa6>
+      struct tcp_pcb *next;
+      pcb->last_timer = tcp_timer_ctr;
+ 80192da:	4b25      	ldr	r3, [pc, #148]	; (8019370 <tcp_fasttmr+0xbc>)
+ 80192dc:	781a      	ldrb	r2, [r3, #0]
+ 80192de:	687b      	ldr	r3, [r7, #4]
+ 80192e0:	779a      	strb	r2, [r3, #30]
+      /* send delayed ACKs */
+      if (pcb->flags & TF_ACK_DELAY) {
+ 80192e2:	687b      	ldr	r3, [r7, #4]
+ 80192e4:	8b5b      	ldrh	r3, [r3, #26]
+ 80192e6:	f003 0301 	and.w	r3, r3, #1
+ 80192ea:	2b00      	cmp	r3, #0
+ 80192ec:	d010      	beq.n	8019310 <tcp_fasttmr+0x5c>
+        LWIP_DEBUGF(TCP_DEBUG, ("tcp_fasttmr: delayed ACK\n"));
+        tcp_ack_now(pcb);
+ 80192ee:	687b      	ldr	r3, [r7, #4]
+ 80192f0:	8b5b      	ldrh	r3, [r3, #26]
+ 80192f2:	f043 0302 	orr.w	r3, r3, #2
+ 80192f6:	b29a      	uxth	r2, r3
+ 80192f8:	687b      	ldr	r3, [r7, #4]
+ 80192fa:	835a      	strh	r2, [r3, #26]
+        tcp_output(pcb);
+ 80192fc:	6878      	ldr	r0, [r7, #4]
+ 80192fe:	f004 f85d 	bl	801d3bc <tcp_output>
+        tcp_clear_flags(pcb, TF_ACK_DELAY | TF_ACK_NOW);
+ 8019302:	687b      	ldr	r3, [r7, #4]
+ 8019304:	8b5b      	ldrh	r3, [r3, #26]
+ 8019306:	f023 0303 	bic.w	r3, r3, #3
+ 801930a:	b29a      	uxth	r2, r3
+ 801930c:	687b      	ldr	r3, [r7, #4]
+ 801930e:	835a      	strh	r2, [r3, #26]
+      }
+      /* send pending FIN */
+      if (pcb->flags & TF_CLOSEPEND) {
+ 8019310:	687b      	ldr	r3, [r7, #4]
+ 8019312:	8b5b      	ldrh	r3, [r3, #26]
+ 8019314:	f003 0308 	and.w	r3, r3, #8
+ 8019318:	2b00      	cmp	r3, #0
+ 801931a:	d009      	beq.n	8019330 <tcp_fasttmr+0x7c>
+        LWIP_DEBUGF(TCP_DEBUG, ("tcp_fasttmr: pending FIN\n"));
+        tcp_clear_flags(pcb, TF_CLOSEPEND);
+ 801931c:	687b      	ldr	r3, [r7, #4]
+ 801931e:	8b5b      	ldrh	r3, [r3, #26]
+ 8019320:	f023 0308 	bic.w	r3, r3, #8
+ 8019324:	b29a      	uxth	r2, r3
+ 8019326:	687b      	ldr	r3, [r7, #4]
+ 8019328:	835a      	strh	r2, [r3, #26]
+        tcp_close_shutdown_fin(pcb);
+ 801932a:	6878      	ldr	r0, [r7, #4]
+ 801932c:	f7ff f824 	bl	8018378 <tcp_close_shutdown_fin>
+      }
+
+      next = pcb->next;
+ 8019330:	687b      	ldr	r3, [r7, #4]
+ 8019332:	68db      	ldr	r3, [r3, #12]
+ 8019334:	603b      	str	r3, [r7, #0]
+
+      /* If there is data which was previously "refused" by upper layer */
+      if (pcb->refused_data != NULL) {
+ 8019336:	687b      	ldr	r3, [r7, #4]
+ 8019338:	6f9b      	ldr	r3, [r3, #120]	; 0x78
+ 801933a:	2b00      	cmp	r3, #0
+ 801933c:	d00a      	beq.n	8019354 <tcp_fasttmr+0xa0>
+        tcp_active_pcbs_changed = 0;
+ 801933e:	4b0e      	ldr	r3, [pc, #56]	; (8019378 <tcp_fasttmr+0xc4>)
+ 8019340:	2200      	movs	r2, #0
+ 8019342:	701a      	strb	r2, [r3, #0]
+        tcp_process_refused_data(pcb);
+ 8019344:	6878      	ldr	r0, [r7, #4]
+ 8019346:	f000 f819 	bl	801937c <tcp_process_refused_data>
+        if (tcp_active_pcbs_changed) {
+ 801934a:	4b0b      	ldr	r3, [pc, #44]	; (8019378 <tcp_fasttmr+0xc4>)
+ 801934c:	781b      	ldrb	r3, [r3, #0]
+ 801934e:	2b00      	cmp	r3, #0
+ 8019350:	d000      	beq.n	8019354 <tcp_fasttmr+0xa0>
+          /* application callback has changed the pcb list: restart the loop */
+          goto tcp_fasttmr_start;
+ 8019352:	e7b8      	b.n	80192c6 <tcp_fasttmr+0x12>
+        }
+      }
+      pcb = next;
+ 8019354:	683b      	ldr	r3, [r7, #0]
+ 8019356:	607b      	str	r3, [r7, #4]
+ 8019358:	e002      	b.n	8019360 <tcp_fasttmr+0xac>
+    } else {
+      pcb = pcb->next;
+ 801935a:	687b      	ldr	r3, [r7, #4]
+ 801935c:	68db      	ldr	r3, [r3, #12]
+ 801935e:	607b      	str	r3, [r7, #4]
+  while (pcb != NULL) {
+ 8019360:	687b      	ldr	r3, [r7, #4]
+ 8019362:	2b00      	cmp	r3, #0
+ 8019364:	d1b3      	bne.n	80192ce <tcp_fasttmr+0x1a>
+    }
+  }
+}
+ 8019366:	bf00      	nop
+ 8019368:	bf00      	nop
+ 801936a:	3708      	adds	r7, #8
+ 801936c:	46bd      	mov	sp, r7
+ 801936e:	bd80      	pop	{r7, pc}
+ 8019370:	2401a496 	.word	0x2401a496
+ 8019374:	2401a48c 	.word	0x2401a48c
+ 8019378:	2401a494 	.word	0x2401a494
+
+0801937c <tcp_process_refused_data>:
+}
+
+/** Pass pcb->refused_data to the recv callback */
+err_t
+tcp_process_refused_data(struct tcp_pcb *pcb)
+{
+ 801937c:	b590      	push	{r4, r7, lr}
+ 801937e:	b085      	sub	sp, #20
+ 8019380:	af00      	add	r7, sp, #0
+ 8019382:	6078      	str	r0, [r7, #4]
+#if TCP_QUEUE_OOSEQ && LWIP_WND_SCALE
+  struct pbuf *rest;
+#endif /* TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */
+
+  LWIP_ERROR("tcp_process_refused_data: invalid pcb", pcb != NULL, return ERR_ARG);
+ 8019384:	687b      	ldr	r3, [r7, #4]
+ 8019386:	2b00      	cmp	r3, #0
+ 8019388:	d109      	bne.n	801939e <tcp_process_refused_data+0x22>
+ 801938a:	4b38      	ldr	r3, [pc, #224]	; (801946c <tcp_process_refused_data+0xf0>)
+ 801938c:	f240 6209 	movw	r2, #1545	; 0x609
+ 8019390:	4937      	ldr	r1, [pc, #220]	; (8019470 <tcp_process_refused_data+0xf4>)
+ 8019392:	4838      	ldr	r0, [pc, #224]	; (8019474 <tcp_process_refused_data+0xf8>)
+ 8019394:	f008 faf8 	bl	8021988 <iprintf>
+ 8019398:	f06f 030f 	mvn.w	r3, #15
+ 801939c:	e061      	b.n	8019462 <tcp_process_refused_data+0xe6>
+#if TCP_QUEUE_OOSEQ && LWIP_WND_SCALE
+  while (pcb->refused_data != NULL)
+#endif /* TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */
+  {
+    err_t err;
+    u8_t refused_flags = pcb->refused_data->flags;
+ 801939e:	687b      	ldr	r3, [r7, #4]
+ 80193a0:	6f9b      	ldr	r3, [r3, #120]	; 0x78
+ 80193a2:	7b5b      	ldrb	r3, [r3, #13]
+ 80193a4:	73bb      	strb	r3, [r7, #14]
+    /* set pcb->refused_data to NULL in case the callback frees it and then
+       closes the pcb */
+    struct pbuf *refused_data = pcb->refused_data;
+ 80193a6:	687b      	ldr	r3, [r7, #4]
+ 80193a8:	6f9b      	ldr	r3, [r3, #120]	; 0x78
+ 80193aa:	60bb      	str	r3, [r7, #8]
+#if TCP_QUEUE_OOSEQ && LWIP_WND_SCALE
+    pbuf_split_64k(refused_data, &rest);
+    pcb->refused_data = rest;
+#else /* TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */
+    pcb->refused_data = NULL;
+ 80193ac:	687b      	ldr	r3, [r7, #4]
+ 80193ae:	2200      	movs	r2, #0
+ 80193b0:	679a      	str	r2, [r3, #120]	; 0x78
+#endif /* TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */
+    /* Notify again application with data previously received. */
+    LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: notify kept packet\n"));
+    TCP_EVENT_RECV(pcb, refused_data, ERR_OK, err);
+ 80193b2:	687b      	ldr	r3, [r7, #4]
+ 80193b4:	f8d3 3084 	ldr.w	r3, [r3, #132]	; 0x84
+ 80193b8:	2b00      	cmp	r3, #0
+ 80193ba:	d00b      	beq.n	80193d4 <tcp_process_refused_data+0x58>
+ 80193bc:	687b      	ldr	r3, [r7, #4]
+ 80193be:	f8d3 4084 	ldr.w	r4, [r3, #132]	; 0x84
+ 80193c2:	687b      	ldr	r3, [r7, #4]
+ 80193c4:	6918      	ldr	r0, [r3, #16]
+ 80193c6:	2300      	movs	r3, #0
+ 80193c8:	68ba      	ldr	r2, [r7, #8]
+ 80193ca:	6879      	ldr	r1, [r7, #4]
+ 80193cc:	47a0      	blx	r4
+ 80193ce:	4603      	mov	r3, r0
+ 80193d0:	73fb      	strb	r3, [r7, #15]
+ 80193d2:	e007      	b.n	80193e4 <tcp_process_refused_data+0x68>
+ 80193d4:	2300      	movs	r3, #0
+ 80193d6:	68ba      	ldr	r2, [r7, #8]
+ 80193d8:	6879      	ldr	r1, [r7, #4]
+ 80193da:	2000      	movs	r0, #0
+ 80193dc:	f000 f8a6 	bl	801952c <tcp_recv_null>
+ 80193e0:	4603      	mov	r3, r0
+ 80193e2:	73fb      	strb	r3, [r7, #15]
+    if (err == ERR_OK) {
+ 80193e4:	f997 300f 	ldrsb.w	r3, [r7, #15]
+ 80193e8:	2b00      	cmp	r3, #0
+ 80193ea:	d12b      	bne.n	8019444 <tcp_process_refused_data+0xc8>
+      /* did refused_data include a FIN? */
+      if ((refused_flags & PBUF_FLAG_TCP_FIN)
+ 80193ec:	7bbb      	ldrb	r3, [r7, #14]
+ 80193ee:	f003 0320 	and.w	r3, r3, #32
+ 80193f2:	2b00      	cmp	r3, #0
+ 80193f4:	d034      	beq.n	8019460 <tcp_process_refused_data+0xe4>
+          && (rest == NULL)
+#endif /* TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */
+         ) {
+        /* correct rcv_wnd as the application won't call tcp_recved()
+           for the FIN's seqno */
+        if (pcb->rcv_wnd != TCP_WND_MAX(pcb)) {
+ 80193f6:	687b      	ldr	r3, [r7, #4]
+ 80193f8:	8d1b      	ldrh	r3, [r3, #40]	; 0x28
+ 80193fa:	f241 62d0 	movw	r2, #5840	; 0x16d0
+ 80193fe:	4293      	cmp	r3, r2
+ 8019400:	d005      	beq.n	801940e <tcp_process_refused_data+0x92>
+          pcb->rcv_wnd++;
+ 8019402:	687b      	ldr	r3, [r7, #4]
+ 8019404:	8d1b      	ldrh	r3, [r3, #40]	; 0x28
+ 8019406:	3301      	adds	r3, #1
+ 8019408:	b29a      	uxth	r2, r3
+ 801940a:	687b      	ldr	r3, [r7, #4]
+ 801940c:	851a      	strh	r2, [r3, #40]	; 0x28
+        }
+        TCP_EVENT_CLOSED(pcb, err);
+ 801940e:	687b      	ldr	r3, [r7, #4]
+ 8019410:	f8d3 3084 	ldr.w	r3, [r3, #132]	; 0x84
+ 8019414:	2b00      	cmp	r3, #0
+ 8019416:	d00b      	beq.n	8019430 <tcp_process_refused_data+0xb4>
+ 8019418:	687b      	ldr	r3, [r7, #4]
+ 801941a:	f8d3 4084 	ldr.w	r4, [r3, #132]	; 0x84
+ 801941e:	687b      	ldr	r3, [r7, #4]
+ 8019420:	6918      	ldr	r0, [r3, #16]
+ 8019422:	2300      	movs	r3, #0
+ 8019424:	2200      	movs	r2, #0
+ 8019426:	6879      	ldr	r1, [r7, #4]
+ 8019428:	47a0      	blx	r4
+ 801942a:	4603      	mov	r3, r0
+ 801942c:	73fb      	strb	r3, [r7, #15]
+ 801942e:	e001      	b.n	8019434 <tcp_process_refused_data+0xb8>
+ 8019430:	2300      	movs	r3, #0
+ 8019432:	73fb      	strb	r3, [r7, #15]
+        if (err == ERR_ABRT) {
+ 8019434:	f997 300f 	ldrsb.w	r3, [r7, #15]
+ 8019438:	f113 0f0d 	cmn.w	r3, #13
+ 801943c:	d110      	bne.n	8019460 <tcp_process_refused_data+0xe4>
+          return ERR_ABRT;
+ 801943e:	f06f 030c 	mvn.w	r3, #12
+ 8019442:	e00e      	b.n	8019462 <tcp_process_refused_data+0xe6>
+        }
+      }
+    } else if (err == ERR_ABRT) {
+ 8019444:	f997 300f 	ldrsb.w	r3, [r7, #15]
+ 8019448:	f113 0f0d 	cmn.w	r3, #13
+ 801944c:	d102      	bne.n	8019454 <tcp_process_refused_data+0xd8>
+      /* if err == ERR_ABRT, 'pcb' is already deallocated */
+      /* Drop incoming packets because pcb is "full" (only if the incoming
+         segment contains data). */
+      LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: drop incoming packets, because pcb is \"full\"\n"));
+      return ERR_ABRT;
+ 801944e:	f06f 030c 	mvn.w	r3, #12
+ 8019452:	e006      	b.n	8019462 <tcp_process_refused_data+0xe6>
+#if TCP_QUEUE_OOSEQ && LWIP_WND_SCALE
+      if (rest != NULL) {
+        pbuf_cat(refused_data, rest);
+      }
+#endif /* TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */
+      pcb->refused_data = refused_data;
+ 8019454:	687b      	ldr	r3, [r7, #4]
+ 8019456:	68ba      	ldr	r2, [r7, #8]
+ 8019458:	679a      	str	r2, [r3, #120]	; 0x78
+      return ERR_INPROGRESS;
+ 801945a:	f06f 0304 	mvn.w	r3, #4
+ 801945e:	e000      	b.n	8019462 <tcp_process_refused_data+0xe6>
+    }
+  }
+  return ERR_OK;
+ 8019460:	2300      	movs	r3, #0
+}
+ 8019462:	4618      	mov	r0, r3
+ 8019464:	3714      	adds	r7, #20
+ 8019466:	46bd      	mov	sp, r7
+ 8019468:	bd90      	pop	{r4, r7, pc}
+ 801946a:	bf00      	nop
+ 801946c:	08024ba8 	.word	0x08024ba8
+ 8019470:	080250b8 	.word	0x080250b8
+ 8019474:	08024bec 	.word	0x08024bec
+
+08019478 <tcp_segs_free>:
+ *
+ * @param seg tcp_seg list of TCP segments to free
+ */
+void
+tcp_segs_free(struct tcp_seg *seg)
+{
+ 8019478:	b580      	push	{r7, lr}
+ 801947a:	b084      	sub	sp, #16
+ 801947c:	af00      	add	r7, sp, #0
+ 801947e:	6078      	str	r0, [r7, #4]
+  while (seg != NULL) {
+ 8019480:	e007      	b.n	8019492 <tcp_segs_free+0x1a>
+    struct tcp_seg *next = seg->next;
+ 8019482:	687b      	ldr	r3, [r7, #4]
+ 8019484:	681b      	ldr	r3, [r3, #0]
+ 8019486:	60fb      	str	r3, [r7, #12]
+    tcp_seg_free(seg);
+ 8019488:	6878      	ldr	r0, [r7, #4]
+ 801948a:	f000 f80a 	bl	80194a2 <tcp_seg_free>
+    seg = next;
+ 801948e:	68fb      	ldr	r3, [r7, #12]
+ 8019490:	607b      	str	r3, [r7, #4]
+  while (seg != NULL) {
+ 8019492:	687b      	ldr	r3, [r7, #4]
+ 8019494:	2b00      	cmp	r3, #0
+ 8019496:	d1f4      	bne.n	8019482 <tcp_segs_free+0xa>
+  }
+}
+ 8019498:	bf00      	nop
+ 801949a:	bf00      	nop
+ 801949c:	3710      	adds	r7, #16
+ 801949e:	46bd      	mov	sp, r7
+ 80194a0:	bd80      	pop	{r7, pc}
+
+080194a2 <tcp_seg_free>:
+ *
+ * @param seg single tcp_seg to free
+ */
+void
+tcp_seg_free(struct tcp_seg *seg)
+{
+ 80194a2:	b580      	push	{r7, lr}
+ 80194a4:	b082      	sub	sp, #8
+ 80194a6:	af00      	add	r7, sp, #0
+ 80194a8:	6078      	str	r0, [r7, #4]
+  if (seg != NULL) {
+ 80194aa:	687b      	ldr	r3, [r7, #4]
+ 80194ac:	2b00      	cmp	r3, #0
+ 80194ae:	d00c      	beq.n	80194ca <tcp_seg_free+0x28>
+    if (seg->p != NULL) {
+ 80194b0:	687b      	ldr	r3, [r7, #4]
+ 80194b2:	685b      	ldr	r3, [r3, #4]
+ 80194b4:	2b00      	cmp	r3, #0
+ 80194b6:	d004      	beq.n	80194c2 <tcp_seg_free+0x20>
+      pbuf_free(seg->p);
+ 80194b8:	687b      	ldr	r3, [r7, #4]
+ 80194ba:	685b      	ldr	r3, [r3, #4]
+ 80194bc:	4618      	mov	r0, r3
+ 80194be:	f7fe fb1b 	bl	8017af8 <pbuf_free>
+#if TCP_DEBUG
+      seg->p = NULL;
+#endif /* TCP_DEBUG */
+    }
+    memp_free(MEMP_TCP_SEG, seg);
+ 80194c2:	6879      	ldr	r1, [r7, #4]
+ 80194c4:	2003      	movs	r0, #3
+ 80194c6:	f7fd fb79 	bl	8016bbc <memp_free>
+  }
+}
+ 80194ca:	bf00      	nop
+ 80194cc:	3708      	adds	r7, #8
+ 80194ce:	46bd      	mov	sp, r7
+ 80194d0:	bd80      	pop	{r7, pc}
+	...
+
+080194d4 <tcp_seg_copy>:
+ * @param seg the old tcp_seg
+ * @return a copy of seg
+ */
+struct tcp_seg *
+tcp_seg_copy(struct tcp_seg *seg)
+{
+ 80194d4:	b580      	push	{r7, lr}
+ 80194d6:	b084      	sub	sp, #16
+ 80194d8:	af00      	add	r7, sp, #0
+ 80194da:	6078      	str	r0, [r7, #4]
+  struct tcp_seg *cseg;
+
+  LWIP_ASSERT("tcp_seg_copy: invalid seg", seg != NULL);
+ 80194dc:	687b      	ldr	r3, [r7, #4]
+ 80194de:	2b00      	cmp	r3, #0
+ 80194e0:	d106      	bne.n	80194f0 <tcp_seg_copy+0x1c>
+ 80194e2:	4b0f      	ldr	r3, [pc, #60]	; (8019520 <tcp_seg_copy+0x4c>)
+ 80194e4:	f240 6282 	movw	r2, #1666	; 0x682
+ 80194e8:	490e      	ldr	r1, [pc, #56]	; (8019524 <tcp_seg_copy+0x50>)
+ 80194ea:	480f      	ldr	r0, [pc, #60]	; (8019528 <tcp_seg_copy+0x54>)
+ 80194ec:	f008 fa4c 	bl	8021988 <iprintf>
+
+  cseg = (struct tcp_seg *)memp_malloc(MEMP_TCP_SEG);
+ 80194f0:	2003      	movs	r0, #3
+ 80194f2:	f7fd faed 	bl	8016ad0 <memp_malloc>
+ 80194f6:	60f8      	str	r0, [r7, #12]
+  if (cseg == NULL) {
+ 80194f8:	68fb      	ldr	r3, [r7, #12]
+ 80194fa:	2b00      	cmp	r3, #0
+ 80194fc:	d101      	bne.n	8019502 <tcp_seg_copy+0x2e>
+    return NULL;
+ 80194fe:	2300      	movs	r3, #0
+ 8019500:	e00a      	b.n	8019518 <tcp_seg_copy+0x44>
+  }
+  SMEMCPY((u8_t *)cseg, (const u8_t *)seg, sizeof(struct tcp_seg));
+ 8019502:	2214      	movs	r2, #20
+ 8019504:	6879      	ldr	r1, [r7, #4]
+ 8019506:	68f8      	ldr	r0, [r7, #12]
+ 8019508:	f008 fc6d 	bl	8021de6 <memcpy>
+  pbuf_ref(cseg->p);
+ 801950c:	68fb      	ldr	r3, [r7, #12]
+ 801950e:	685b      	ldr	r3, [r3, #4]
+ 8019510:	4618      	mov	r0, r3
+ 8019512:	f7fe fb97 	bl	8017c44 <pbuf_ref>
+  return cseg;
+ 8019516:	68fb      	ldr	r3, [r7, #12]
+}
+ 8019518:	4618      	mov	r0, r3
+ 801951a:	3710      	adds	r7, #16
+ 801951c:	46bd      	mov	sp, r7
+ 801951e:	bd80      	pop	{r7, pc}
+ 8019520:	08024ba8 	.word	0x08024ba8
+ 8019524:	080250fc 	.word	0x080250fc
+ 8019528:	08024bec 	.word	0x08024bec
+
+0801952c <tcp_recv_null>:
+ * Default receive callback that is called if the user didn't register
+ * a recv callback for the pcb.
+ */
+err_t
+tcp_recv_null(void *arg, struct tcp_pcb *pcb, struct pbuf *p, err_t err)
+{
+ 801952c:	b580      	push	{r7, lr}
+ 801952e:	b084      	sub	sp, #16
+ 8019530:	af00      	add	r7, sp, #0
+ 8019532:	60f8      	str	r0, [r7, #12]
+ 8019534:	60b9      	str	r1, [r7, #8]
+ 8019536:	607a      	str	r2, [r7, #4]
+ 8019538:	70fb      	strb	r3, [r7, #3]
+  LWIP_UNUSED_ARG(arg);
+
+  LWIP_ERROR("tcp_recv_null: invalid pcb", pcb != NULL, return ERR_ARG);
+ 801953a:	68bb      	ldr	r3, [r7, #8]
+ 801953c:	2b00      	cmp	r3, #0
+ 801953e:	d109      	bne.n	8019554 <tcp_recv_null+0x28>
+ 8019540:	4b12      	ldr	r3, [pc, #72]	; (801958c <tcp_recv_null+0x60>)
+ 8019542:	f44f 62d3 	mov.w	r2, #1688	; 0x698
+ 8019546:	4912      	ldr	r1, [pc, #72]	; (8019590 <tcp_recv_null+0x64>)
+ 8019548:	4812      	ldr	r0, [pc, #72]	; (8019594 <tcp_recv_null+0x68>)
+ 801954a:	f008 fa1d 	bl	8021988 <iprintf>
+ 801954e:	f06f 030f 	mvn.w	r3, #15
+ 8019552:	e016      	b.n	8019582 <tcp_recv_null+0x56>
+
+  if (p != NULL) {
+ 8019554:	687b      	ldr	r3, [r7, #4]
+ 8019556:	2b00      	cmp	r3, #0
+ 8019558:	d009      	beq.n	801956e <tcp_recv_null+0x42>
+    tcp_recved(pcb, p->tot_len);
+ 801955a:	687b      	ldr	r3, [r7, #4]
+ 801955c:	891b      	ldrh	r3, [r3, #8]
+ 801955e:	4619      	mov	r1, r3
+ 8019560:	68b8      	ldr	r0, [r7, #8]
+ 8019562:	f7ff f9b7 	bl	80188d4 <tcp_recved>
+    pbuf_free(p);
+ 8019566:	6878      	ldr	r0, [r7, #4]
+ 8019568:	f7fe fac6 	bl	8017af8 <pbuf_free>
+ 801956c:	e008      	b.n	8019580 <tcp_recv_null+0x54>
+  } else if (err == ERR_OK) {
+ 801956e:	f997 3003 	ldrsb.w	r3, [r7, #3]
+ 8019572:	2b00      	cmp	r3, #0
+ 8019574:	d104      	bne.n	8019580 <tcp_recv_null+0x54>
+    return tcp_close(pcb);
+ 8019576:	68b8      	ldr	r0, [r7, #8]
+ 8019578:	f7fe ff68 	bl	801844c <tcp_close>
+ 801957c:	4603      	mov	r3, r0
+ 801957e:	e000      	b.n	8019582 <tcp_recv_null+0x56>
+  }
+  return ERR_OK;
+ 8019580:	2300      	movs	r3, #0
+}
+ 8019582:	4618      	mov	r0, r3
+ 8019584:	3710      	adds	r7, #16
+ 8019586:	46bd      	mov	sp, r7
+ 8019588:	bd80      	pop	{r7, pc}
+ 801958a:	bf00      	nop
+ 801958c:	08024ba8 	.word	0x08024ba8
+ 8019590:	08025118 	.word	0x08025118
+ 8019594:	08024bec 	.word	0x08024bec
+
+08019598 <tcp_kill_prio>:
+ *
+ * @param prio minimum priority
+ */
+static void
+tcp_kill_prio(u8_t prio)
+{
+ 8019598:	b580      	push	{r7, lr}
+ 801959a:	b086      	sub	sp, #24
+ 801959c:	af00      	add	r7, sp, #0
+ 801959e:	4603      	mov	r3, r0
+ 80195a0:	71fb      	strb	r3, [r7, #7]
+  struct tcp_pcb *pcb, *inactive;
+  u32_t inactivity;
+  u8_t mprio;
+
+  mprio = LWIP_MIN(TCP_PRIO_MAX, prio);
+ 80195a2:	f997 3007 	ldrsb.w	r3, [r7, #7]
+ 80195a6:	2b00      	cmp	r3, #0
+ 80195a8:	db01      	blt.n	80195ae <tcp_kill_prio+0x16>
+ 80195aa:	79fb      	ldrb	r3, [r7, #7]
+ 80195ac:	e000      	b.n	80195b0 <tcp_kill_prio+0x18>
+ 80195ae:	237f      	movs	r3, #127	; 0x7f
+ 80195b0:	72fb      	strb	r3, [r7, #11]
+
+  /* We want to kill connections with a lower prio, so bail out if 
+   * supplied prio is 0 - there can never be a lower prio
+   */
+  if (mprio == 0) {
+ 80195b2:	7afb      	ldrb	r3, [r7, #11]
+ 80195b4:	2b00      	cmp	r3, #0
+ 80195b6:	d034      	beq.n	8019622 <tcp_kill_prio+0x8a>
+  /* We only want kill connections with a lower prio, so decrement prio by one 
+   * and start searching for oldest connection with same or lower priority than mprio.
+   * We want to find the connections with the lowest possible prio, and among
+   * these the one with the longest inactivity time.
+   */
+  mprio--;
+ 80195b8:	7afb      	ldrb	r3, [r7, #11]
+ 80195ba:	3b01      	subs	r3, #1
+ 80195bc:	72fb      	strb	r3, [r7, #11]
+
+  inactivity = 0;
+ 80195be:	2300      	movs	r3, #0
+ 80195c0:	60fb      	str	r3, [r7, #12]
+  inactive = NULL;
+ 80195c2:	2300      	movs	r3, #0
+ 80195c4:	613b      	str	r3, [r7, #16]
+  for (pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) {
+ 80195c6:	4b19      	ldr	r3, [pc, #100]	; (801962c <tcp_kill_prio+0x94>)
+ 80195c8:	681b      	ldr	r3, [r3, #0]
+ 80195ca:	617b      	str	r3, [r7, #20]
+ 80195cc:	e01f      	b.n	801960e <tcp_kill_prio+0x76>
+        /* lower prio is always a kill candidate */
+    if ((pcb->prio < mprio) ||
+ 80195ce:	697b      	ldr	r3, [r7, #20]
+ 80195d0:	7d5b      	ldrb	r3, [r3, #21]
+ 80195d2:	7afa      	ldrb	r2, [r7, #11]
+ 80195d4:	429a      	cmp	r2, r3
+ 80195d6:	d80c      	bhi.n	80195f2 <tcp_kill_prio+0x5a>
+        /* longer inactivity is also a kill candidate */
+        ((pcb->prio == mprio) && ((u32_t)(tcp_ticks - pcb->tmr) >= inactivity))) {
+ 80195d8:	697b      	ldr	r3, [r7, #20]
+ 80195da:	7d5b      	ldrb	r3, [r3, #21]
+    if ((pcb->prio < mprio) ||
+ 80195dc:	7afa      	ldrb	r2, [r7, #11]
+ 80195de:	429a      	cmp	r2, r3
+ 80195e0:	d112      	bne.n	8019608 <tcp_kill_prio+0x70>
+        ((pcb->prio == mprio) && ((u32_t)(tcp_ticks - pcb->tmr) >= inactivity))) {
+ 80195e2:	4b13      	ldr	r3, [pc, #76]	; (8019630 <tcp_kill_prio+0x98>)
+ 80195e4:	681a      	ldr	r2, [r3, #0]
+ 80195e6:	697b      	ldr	r3, [r7, #20]
+ 80195e8:	6a1b      	ldr	r3, [r3, #32]
+ 80195ea:	1ad3      	subs	r3, r2, r3
+ 80195ec:	68fa      	ldr	r2, [r7, #12]
+ 80195ee:	429a      	cmp	r2, r3
+ 80195f0:	d80a      	bhi.n	8019608 <tcp_kill_prio+0x70>
+      inactivity = tcp_ticks - pcb->tmr;
+ 80195f2:	4b0f      	ldr	r3, [pc, #60]	; (8019630 <tcp_kill_prio+0x98>)
+ 80195f4:	681a      	ldr	r2, [r3, #0]
+ 80195f6:	697b      	ldr	r3, [r7, #20]
+ 80195f8:	6a1b      	ldr	r3, [r3, #32]
+ 80195fa:	1ad3      	subs	r3, r2, r3
+ 80195fc:	60fb      	str	r3, [r7, #12]
+      inactive   = pcb;
+ 80195fe:	697b      	ldr	r3, [r7, #20]
+ 8019600:	613b      	str	r3, [r7, #16]
+      mprio      = pcb->prio;
+ 8019602:	697b      	ldr	r3, [r7, #20]
+ 8019604:	7d5b      	ldrb	r3, [r3, #21]
+ 8019606:	72fb      	strb	r3, [r7, #11]
+  for (pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) {
+ 8019608:	697b      	ldr	r3, [r7, #20]
+ 801960a:	68db      	ldr	r3, [r3, #12]
+ 801960c:	617b      	str	r3, [r7, #20]
+ 801960e:	697b      	ldr	r3, [r7, #20]
+ 8019610:	2b00      	cmp	r3, #0
+ 8019612:	d1dc      	bne.n	80195ce <tcp_kill_prio+0x36>
+    }
+  }
+  if (inactive != NULL) {
+ 8019614:	693b      	ldr	r3, [r7, #16]
+ 8019616:	2b00      	cmp	r3, #0
+ 8019618:	d004      	beq.n	8019624 <tcp_kill_prio+0x8c>
+    LWIP_DEBUGF(TCP_DEBUG, ("tcp_kill_prio: killing oldest PCB %p (%"S32_F")\n",
+                            (void *)inactive, inactivity));
+    tcp_abort(inactive);
+ 801961a:	6938      	ldr	r0, [r7, #16]
+ 801961c:	f7ff f85c 	bl	80186d8 <tcp_abort>
+ 8019620:	e000      	b.n	8019624 <tcp_kill_prio+0x8c>
+    return;
+ 8019622:	bf00      	nop
+  }
+}
+ 8019624:	3718      	adds	r7, #24
+ 8019626:	46bd      	mov	sp, r7
+ 8019628:	bd80      	pop	{r7, pc}
+ 801962a:	bf00      	nop
+ 801962c:	2401a48c 	.word	0x2401a48c
+ 8019630:	2401a480 	.word	0x2401a480
+
+08019634 <tcp_kill_state>:
+ * Kills the oldest connection that is in specific state.
+ * Called from tcp_alloc() for LAST_ACK and CLOSING if no more connections are available.
+ */
+static void
+tcp_kill_state(enum tcp_state state)
+{
+ 8019634:	b580      	push	{r7, lr}
+ 8019636:	b086      	sub	sp, #24
+ 8019638:	af00      	add	r7, sp, #0
+ 801963a:	4603      	mov	r3, r0
+ 801963c:	71fb      	strb	r3, [r7, #7]
+  struct tcp_pcb *pcb, *inactive;
+  u32_t inactivity;
+
+  LWIP_ASSERT("invalid state", (state == CLOSING) || (state == LAST_ACK));
+ 801963e:	79fb      	ldrb	r3, [r7, #7]
+ 8019640:	2b08      	cmp	r3, #8
+ 8019642:	d009      	beq.n	8019658 <tcp_kill_state+0x24>
+ 8019644:	79fb      	ldrb	r3, [r7, #7]
+ 8019646:	2b09      	cmp	r3, #9
+ 8019648:	d006      	beq.n	8019658 <tcp_kill_state+0x24>
+ 801964a:	4b1a      	ldr	r3, [pc, #104]	; (80196b4 <tcp_kill_state+0x80>)
+ 801964c:	f240 62dd 	movw	r2, #1757	; 0x6dd
+ 8019650:	4919      	ldr	r1, [pc, #100]	; (80196b8 <tcp_kill_state+0x84>)
+ 8019652:	481a      	ldr	r0, [pc, #104]	; (80196bc <tcp_kill_state+0x88>)
+ 8019654:	f008 f998 	bl	8021988 <iprintf>
+
+  inactivity = 0;
+ 8019658:	2300      	movs	r3, #0
+ 801965a:	60fb      	str	r3, [r7, #12]
+  inactive = NULL;
+ 801965c:	2300      	movs	r3, #0
+ 801965e:	613b      	str	r3, [r7, #16]
+  /* Go through the list of active pcbs and get the oldest pcb that is in state
+     CLOSING/LAST_ACK. */
+  for (pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) {
+ 8019660:	4b17      	ldr	r3, [pc, #92]	; (80196c0 <tcp_kill_state+0x8c>)
+ 8019662:	681b      	ldr	r3, [r3, #0]
+ 8019664:	617b      	str	r3, [r7, #20]
+ 8019666:	e017      	b.n	8019698 <tcp_kill_state+0x64>
+    if (pcb->state == state) {
+ 8019668:	697b      	ldr	r3, [r7, #20]
+ 801966a:	7d1b      	ldrb	r3, [r3, #20]
+ 801966c:	79fa      	ldrb	r2, [r7, #7]
+ 801966e:	429a      	cmp	r2, r3
+ 8019670:	d10f      	bne.n	8019692 <tcp_kill_state+0x5e>
+      if ((u32_t)(tcp_ticks - pcb->tmr) >= inactivity) {
+ 8019672:	4b14      	ldr	r3, [pc, #80]	; (80196c4 <tcp_kill_state+0x90>)
+ 8019674:	681a      	ldr	r2, [r3, #0]
+ 8019676:	697b      	ldr	r3, [r7, #20]
+ 8019678:	6a1b      	ldr	r3, [r3, #32]
+ 801967a:	1ad3      	subs	r3, r2, r3
+ 801967c:	68fa      	ldr	r2, [r7, #12]
+ 801967e:	429a      	cmp	r2, r3
+ 8019680:	d807      	bhi.n	8019692 <tcp_kill_state+0x5e>
+        inactivity = tcp_ticks - pcb->tmr;
+ 8019682:	4b10      	ldr	r3, [pc, #64]	; (80196c4 <tcp_kill_state+0x90>)
+ 8019684:	681a      	ldr	r2, [r3, #0]
+ 8019686:	697b      	ldr	r3, [r7, #20]
+ 8019688:	6a1b      	ldr	r3, [r3, #32]
+ 801968a:	1ad3      	subs	r3, r2, r3
+ 801968c:	60fb      	str	r3, [r7, #12]
+        inactive = pcb;
+ 801968e:	697b      	ldr	r3, [r7, #20]
+ 8019690:	613b      	str	r3, [r7, #16]
+  for (pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) {
+ 8019692:	697b      	ldr	r3, [r7, #20]
+ 8019694:	68db      	ldr	r3, [r3, #12]
+ 8019696:	617b      	str	r3, [r7, #20]
+ 8019698:	697b      	ldr	r3, [r7, #20]
+ 801969a:	2b00      	cmp	r3, #0
+ 801969c:	d1e4      	bne.n	8019668 <tcp_kill_state+0x34>
+      }
+    }
+  }
+  if (inactive != NULL) {
+ 801969e:	693b      	ldr	r3, [r7, #16]
+ 80196a0:	2b00      	cmp	r3, #0
+ 80196a2:	d003      	beq.n	80196ac <tcp_kill_state+0x78>
+    LWIP_DEBUGF(TCP_DEBUG, ("tcp_kill_closing: killing oldest %s PCB %p (%"S32_F")\n",
+                            tcp_state_str[state], (void *)inactive, inactivity));
+    /* Don't send a RST, since no data is lost. */
+    tcp_abandon(inactive, 0);
+ 80196a4:	2100      	movs	r1, #0
+ 80196a6:	6938      	ldr	r0, [r7, #16]
+ 80196a8:	f7fe ff58 	bl	801855c <tcp_abandon>
+  }
+}
+ 80196ac:	bf00      	nop
+ 80196ae:	3718      	adds	r7, #24
+ 80196b0:	46bd      	mov	sp, r7
+ 80196b2:	bd80      	pop	{r7, pc}
+ 80196b4:	08024ba8 	.word	0x08024ba8
+ 80196b8:	08025134 	.word	0x08025134
+ 80196bc:	08024bec 	.word	0x08024bec
+ 80196c0:	2401a48c 	.word	0x2401a48c
+ 80196c4:	2401a480 	.word	0x2401a480
+
+080196c8 <tcp_kill_timewait>:
+ * Kills the oldest connection that is in TIME_WAIT state.
+ * Called from tcp_alloc() if no more connections are available.
+ */
+static void
+tcp_kill_timewait(void)
+{
+ 80196c8:	b580      	push	{r7, lr}
+ 80196ca:	b084      	sub	sp, #16
+ 80196cc:	af00      	add	r7, sp, #0
+  struct tcp_pcb *pcb, *inactive;
+  u32_t inactivity;
+
+  inactivity = 0;
+ 80196ce:	2300      	movs	r3, #0
+ 80196d0:	607b      	str	r3, [r7, #4]
+  inactive = NULL;
+ 80196d2:	2300      	movs	r3, #0
+ 80196d4:	60bb      	str	r3, [r7, #8]
+  /* Go through the list of TIME_WAIT pcbs and get the oldest pcb. */
+  for (pcb = tcp_tw_pcbs; pcb != NULL; pcb = pcb->next) {
+ 80196d6:	4b12      	ldr	r3, [pc, #72]	; (8019720 <tcp_kill_timewait+0x58>)
+ 80196d8:	681b      	ldr	r3, [r3, #0]
+ 80196da:	60fb      	str	r3, [r7, #12]
+ 80196dc:	e012      	b.n	8019704 <tcp_kill_timewait+0x3c>
+    if ((u32_t)(tcp_ticks - pcb->tmr) >= inactivity) {
+ 80196de:	4b11      	ldr	r3, [pc, #68]	; (8019724 <tcp_kill_timewait+0x5c>)
+ 80196e0:	681a      	ldr	r2, [r3, #0]
+ 80196e2:	68fb      	ldr	r3, [r7, #12]
+ 80196e4:	6a1b      	ldr	r3, [r3, #32]
+ 80196e6:	1ad3      	subs	r3, r2, r3
+ 80196e8:	687a      	ldr	r2, [r7, #4]
+ 80196ea:	429a      	cmp	r2, r3
+ 80196ec:	d807      	bhi.n	80196fe <tcp_kill_timewait+0x36>
+      inactivity = tcp_ticks - pcb->tmr;
+ 80196ee:	4b0d      	ldr	r3, [pc, #52]	; (8019724 <tcp_kill_timewait+0x5c>)
+ 80196f0:	681a      	ldr	r2, [r3, #0]
+ 80196f2:	68fb      	ldr	r3, [r7, #12]
+ 80196f4:	6a1b      	ldr	r3, [r3, #32]
+ 80196f6:	1ad3      	subs	r3, r2, r3
+ 80196f8:	607b      	str	r3, [r7, #4]
+      inactive = pcb;
+ 80196fa:	68fb      	ldr	r3, [r7, #12]
+ 80196fc:	60bb      	str	r3, [r7, #8]
+  for (pcb = tcp_tw_pcbs; pcb != NULL; pcb = pcb->next) {
+ 80196fe:	68fb      	ldr	r3, [r7, #12]
+ 8019700:	68db      	ldr	r3, [r3, #12]
+ 8019702:	60fb      	str	r3, [r7, #12]
+ 8019704:	68fb      	ldr	r3, [r7, #12]
+ 8019706:	2b00      	cmp	r3, #0
+ 8019708:	d1e9      	bne.n	80196de <tcp_kill_timewait+0x16>
+    }
+  }
+  if (inactive != NULL) {
+ 801970a:	68bb      	ldr	r3, [r7, #8]
+ 801970c:	2b00      	cmp	r3, #0
+ 801970e:	d002      	beq.n	8019716 <tcp_kill_timewait+0x4e>
+    LWIP_DEBUGF(TCP_DEBUG, ("tcp_kill_timewait: killing oldest TIME-WAIT PCB %p (%"S32_F")\n",
+                            (void *)inactive, inactivity));
+    tcp_abort(inactive);
+ 8019710:	68b8      	ldr	r0, [r7, #8]
+ 8019712:	f7fe ffe1 	bl	80186d8 <tcp_abort>
+  }
+}
+ 8019716:	bf00      	nop
+ 8019718:	3710      	adds	r7, #16
+ 801971a:	46bd      	mov	sp, r7
+ 801971c:	bd80      	pop	{r7, pc}
+ 801971e:	bf00      	nop
+ 8019720:	2401a490 	.word	0x2401a490
+ 8019724:	2401a480 	.word	0x2401a480
+
+08019728 <tcp_handle_closepend>:
+ * now send the FIN (which failed before), the pcb might be in a state that is
+ * OK for us to now free it.
+ */
+static void
+tcp_handle_closepend(void)
+{
+ 8019728:	b580      	push	{r7, lr}
+ 801972a:	b082      	sub	sp, #8
+ 801972c:	af00      	add	r7, sp, #0
+  struct tcp_pcb *pcb = tcp_active_pcbs;
+ 801972e:	4b10      	ldr	r3, [pc, #64]	; (8019770 <tcp_handle_closepend+0x48>)
+ 8019730:	681b      	ldr	r3, [r3, #0]
+ 8019732:	607b      	str	r3, [r7, #4]
+
+  while (pcb != NULL) {
+ 8019734:	e014      	b.n	8019760 <tcp_handle_closepend+0x38>
+    struct tcp_pcb *next = pcb->next;
+ 8019736:	687b      	ldr	r3, [r7, #4]
+ 8019738:	68db      	ldr	r3, [r3, #12]
+ 801973a:	603b      	str	r3, [r7, #0]
+    /* send pending FIN */
+    if (pcb->flags & TF_CLOSEPEND) {
+ 801973c:	687b      	ldr	r3, [r7, #4]
+ 801973e:	8b5b      	ldrh	r3, [r3, #26]
+ 8019740:	f003 0308 	and.w	r3, r3, #8
+ 8019744:	2b00      	cmp	r3, #0
+ 8019746:	d009      	beq.n	801975c <tcp_handle_closepend+0x34>
+      LWIP_DEBUGF(TCP_DEBUG, ("tcp_handle_closepend: pending FIN\n"));
+      tcp_clear_flags(pcb, TF_CLOSEPEND);
+ 8019748:	687b      	ldr	r3, [r7, #4]
+ 801974a:	8b5b      	ldrh	r3, [r3, #26]
+ 801974c:	f023 0308 	bic.w	r3, r3, #8
+ 8019750:	b29a      	uxth	r2, r3
+ 8019752:	687b      	ldr	r3, [r7, #4]
+ 8019754:	835a      	strh	r2, [r3, #26]
+      tcp_close_shutdown_fin(pcb);
+ 8019756:	6878      	ldr	r0, [r7, #4]
+ 8019758:	f7fe fe0e 	bl	8018378 <tcp_close_shutdown_fin>
+    }
+    pcb = next;
+ 801975c:	683b      	ldr	r3, [r7, #0]
+ 801975e:	607b      	str	r3, [r7, #4]
+  while (pcb != NULL) {
+ 8019760:	687b      	ldr	r3, [r7, #4]
+ 8019762:	2b00      	cmp	r3, #0
+ 8019764:	d1e7      	bne.n	8019736 <tcp_handle_closepend+0xe>
+  }
+}
+ 8019766:	bf00      	nop
+ 8019768:	bf00      	nop
+ 801976a:	3708      	adds	r7, #8
+ 801976c:	46bd      	mov	sp, r7
+ 801976e:	bd80      	pop	{r7, pc}
+ 8019770:	2401a48c 	.word	0x2401a48c
+
+08019774 <tcp_alloc>:
+ * @param prio priority for the new pcb
+ * @return a new tcp_pcb that initially is in state CLOSED
+ */
+struct tcp_pcb *
+tcp_alloc(u8_t prio)
+{
+ 8019774:	b580      	push	{r7, lr}
+ 8019776:	b084      	sub	sp, #16
+ 8019778:	af00      	add	r7, sp, #0
+ 801977a:	4603      	mov	r3, r0
+ 801977c:	71fb      	strb	r3, [r7, #7]
+  struct tcp_pcb *pcb;
+
+  LWIP_ASSERT_CORE_LOCKED();
+
+  pcb = (struct tcp_pcb *)memp_malloc(MEMP_TCP_PCB);
+ 801977e:	2001      	movs	r0, #1
+ 8019780:	f7fd f9a6 	bl	8016ad0 <memp_malloc>
+ 8019784:	60f8      	str	r0, [r7, #12]
+  if (pcb == NULL) {
+ 8019786:	68fb      	ldr	r3, [r7, #12]
+ 8019788:	2b00      	cmp	r3, #0
+ 801978a:	d126      	bne.n	80197da <tcp_alloc+0x66>
+    /* Try to send FIN for all pcbs stuck in TF_CLOSEPEND first */
+    tcp_handle_closepend();
+ 801978c:	f7ff ffcc 	bl	8019728 <tcp_handle_closepend>
+
+    /* Try killing oldest connection in TIME-WAIT. */
+    LWIP_DEBUGF(TCP_DEBUG, ("tcp_alloc: killing off oldest TIME-WAIT connection\n"));
+    tcp_kill_timewait();
+ 8019790:	f7ff ff9a 	bl	80196c8 <tcp_kill_timewait>
+    /* Try to allocate a tcp_pcb again. */
+    pcb = (struct tcp_pcb *)memp_malloc(MEMP_TCP_PCB);
+ 8019794:	2001      	movs	r0, #1
+ 8019796:	f7fd f99b 	bl	8016ad0 <memp_malloc>
+ 801979a:	60f8      	str	r0, [r7, #12]
+    if (pcb == NULL) {
+ 801979c:	68fb      	ldr	r3, [r7, #12]
+ 801979e:	2b00      	cmp	r3, #0
+ 80197a0:	d11b      	bne.n	80197da <tcp_alloc+0x66>
+      /* Try killing oldest connection in LAST-ACK (these wouldn't go to TIME-WAIT). */
+      LWIP_DEBUGF(TCP_DEBUG, ("tcp_alloc: killing off oldest LAST-ACK connection\n"));
+      tcp_kill_state(LAST_ACK);
+ 80197a2:	2009      	movs	r0, #9
+ 80197a4:	f7ff ff46 	bl	8019634 <tcp_kill_state>
+      /* Try to allocate a tcp_pcb again. */
+      pcb = (struct tcp_pcb *)memp_malloc(MEMP_TCP_PCB);
+ 80197a8:	2001      	movs	r0, #1
+ 80197aa:	f7fd f991 	bl	8016ad0 <memp_malloc>
+ 80197ae:	60f8      	str	r0, [r7, #12]
+      if (pcb == NULL) {
+ 80197b0:	68fb      	ldr	r3, [r7, #12]
+ 80197b2:	2b00      	cmp	r3, #0
+ 80197b4:	d111      	bne.n	80197da <tcp_alloc+0x66>
+        /* Try killing oldest connection in CLOSING. */
+        LWIP_DEBUGF(TCP_DEBUG, ("tcp_alloc: killing off oldest CLOSING connection\n"));
+        tcp_kill_state(CLOSING);
+ 80197b6:	2008      	movs	r0, #8
+ 80197b8:	f7ff ff3c 	bl	8019634 <tcp_kill_state>
+        /* Try to allocate a tcp_pcb again. */
+        pcb = (struct tcp_pcb *)memp_malloc(MEMP_TCP_PCB);
+ 80197bc:	2001      	movs	r0, #1
+ 80197be:	f7fd f987 	bl	8016ad0 <memp_malloc>
+ 80197c2:	60f8      	str	r0, [r7, #12]
+        if (pcb == NULL) {
+ 80197c4:	68fb      	ldr	r3, [r7, #12]
+ 80197c6:	2b00      	cmp	r3, #0
+ 80197c8:	d107      	bne.n	80197da <tcp_alloc+0x66>
+          /* Try killing oldest active connection with lower priority than the new one. */
+          LWIP_DEBUGF(TCP_DEBUG, ("tcp_alloc: killing oldest connection with prio lower than %d\n", prio));
+          tcp_kill_prio(prio);
+ 80197ca:	79fb      	ldrb	r3, [r7, #7]
+ 80197cc:	4618      	mov	r0, r3
+ 80197ce:	f7ff fee3 	bl	8019598 <tcp_kill_prio>
+          /* Try to allocate a tcp_pcb again. */
+          pcb = (struct tcp_pcb *)memp_malloc(MEMP_TCP_PCB);
+ 80197d2:	2001      	movs	r0, #1
+ 80197d4:	f7fd f97c 	bl	8016ad0 <memp_malloc>
+ 80197d8:	60f8      	str	r0, [r7, #12]
+    if (pcb != NULL) {
+      /* adjust err stats: memp_malloc failed above */
+      MEMP_STATS_DEC(err, MEMP_TCP_PCB);
+    }
+  }
+  if (pcb != NULL) {
+ 80197da:	68fb      	ldr	r3, [r7, #12]
+ 80197dc:	2b00      	cmp	r3, #0
+ 80197de:	d03f      	beq.n	8019860 <tcp_alloc+0xec>
+    /* zero out the whole pcb, so there is no need to initialize members to zero */
+    memset(pcb, 0, sizeof(struct tcp_pcb));
+ 80197e0:	229c      	movs	r2, #156	; 0x9c
+ 80197e2:	2100      	movs	r1, #0
+ 80197e4:	68f8      	ldr	r0, [r7, #12]
+ 80197e6:	f008 fa7b 	bl	8021ce0 <memset>
+    pcb->prio = prio;
+ 80197ea:	68fb      	ldr	r3, [r7, #12]
+ 80197ec:	79fa      	ldrb	r2, [r7, #7]
+ 80197ee:	755a      	strb	r2, [r3, #21]
+    pcb->snd_buf = TCP_SND_BUF;
+ 80197f0:	68fb      	ldr	r3, [r7, #12]
+ 80197f2:	f241 62d0 	movw	r2, #5840	; 0x16d0
+ 80197f6:	f8a3 2064 	strh.w	r2, [r3, #100]	; 0x64
+    /* Start with a window that does not need scaling. When window scaling is
+       enabled and used, the window is enlarged when both sides agree on scaling. */
+    pcb->rcv_wnd = pcb->rcv_ann_wnd = TCPWND_MIN16(TCP_WND);
+ 80197fa:	68fb      	ldr	r3, [r7, #12]
+ 80197fc:	f241 62d0 	movw	r2, #5840	; 0x16d0
+ 8019800:	855a      	strh	r2, [r3, #42]	; 0x2a
+ 8019802:	68fb      	ldr	r3, [r7, #12]
+ 8019804:	8d5a      	ldrh	r2, [r3, #42]	; 0x2a
+ 8019806:	68fb      	ldr	r3, [r7, #12]
+ 8019808:	851a      	strh	r2, [r3, #40]	; 0x28
+    pcb->ttl = TCP_TTL;
+ 801980a:	68fb      	ldr	r3, [r7, #12]
+ 801980c:	22ff      	movs	r2, #255	; 0xff
+ 801980e:	72da      	strb	r2, [r3, #11]
+    /* As initial send MSS, we use TCP_MSS but limit it to 536.
+       The send MSS is updated when an MSS option is received. */
+    pcb->mss = INITIAL_MSS;
+ 8019810:	68fb      	ldr	r3, [r7, #12]
+ 8019812:	f44f 7206 	mov.w	r2, #536	; 0x218
+ 8019816:	865a      	strh	r2, [r3, #50]	; 0x32
+    pcb->rto = 3000 / TCP_SLOW_INTERVAL;
+ 8019818:	68fb      	ldr	r3, [r7, #12]
+ 801981a:	2206      	movs	r2, #6
+ 801981c:	f8a3 2040 	strh.w	r2, [r3, #64]	; 0x40
+    pcb->sv = 3000 / TCP_SLOW_INTERVAL;
+ 8019820:	68fb      	ldr	r3, [r7, #12]
+ 8019822:	2206      	movs	r2, #6
+ 8019824:	87da      	strh	r2, [r3, #62]	; 0x3e
+    pcb->rtime = -1;
+ 8019826:	68fb      	ldr	r3, [r7, #12]
+ 8019828:	f64f 72ff 	movw	r2, #65535	; 0xffff
+ 801982c:	861a      	strh	r2, [r3, #48]	; 0x30
+    pcb->cwnd = 1;
+ 801982e:	68fb      	ldr	r3, [r7, #12]
+ 8019830:	2201      	movs	r2, #1
+ 8019832:	f8a3 2048 	strh.w	r2, [r3, #72]	; 0x48
+    pcb->tmr = tcp_ticks;
+ 8019836:	4b0d      	ldr	r3, [pc, #52]	; (801986c <tcp_alloc+0xf8>)
+ 8019838:	681a      	ldr	r2, [r3, #0]
+ 801983a:	68fb      	ldr	r3, [r7, #12]
+ 801983c:	621a      	str	r2, [r3, #32]
+    pcb->last_timer = tcp_timer_ctr;
+ 801983e:	4b0c      	ldr	r3, [pc, #48]	; (8019870 <tcp_alloc+0xfc>)
+ 8019840:	781a      	ldrb	r2, [r3, #0]
+ 8019842:	68fb      	ldr	r3, [r7, #12]
+ 8019844:	779a      	strb	r2, [r3, #30]
+    of using the largest advertised receive window.  We've seen complications with
+    receiving TCPs that use window scaling and/or window auto-tuning where the
+    initial advertised window is very small and then grows rapidly once the
+    connection is established. To avoid these complications, we set ssthresh to the
+    largest effective cwnd (amount of in-flight data) that the sender can have. */
+    pcb->ssthresh = TCP_SND_BUF;
+ 8019846:	68fb      	ldr	r3, [r7, #12]
+ 8019848:	f241 62d0 	movw	r2, #5840	; 0x16d0
+ 801984c:	f8a3 204a 	strh.w	r2, [r3, #74]	; 0x4a
+
+#if LWIP_CALLBACK_API
+    pcb->recv = tcp_recv_null;
+ 8019850:	68fb      	ldr	r3, [r7, #12]
+ 8019852:	4a08      	ldr	r2, [pc, #32]	; (8019874 <tcp_alloc+0x100>)
+ 8019854:	f8c3 2084 	str.w	r2, [r3, #132]	; 0x84
+#endif /* LWIP_CALLBACK_API */
+
+    /* Init KEEPALIVE timer */
+    pcb->keep_idle  = TCP_KEEPIDLE_DEFAULT;
+ 8019858:	68fb      	ldr	r3, [r7, #12]
+ 801985a:	4a07      	ldr	r2, [pc, #28]	; (8019878 <tcp_alloc+0x104>)
+ 801985c:	f8c3 2094 	str.w	r2, [r3, #148]	; 0x94
+#if LWIP_TCP_KEEPALIVE
+    pcb->keep_intvl = TCP_KEEPINTVL_DEFAULT;
+    pcb->keep_cnt   = TCP_KEEPCNT_DEFAULT;
+#endif /* LWIP_TCP_KEEPALIVE */
+  }
+  return pcb;
+ 8019860:	68fb      	ldr	r3, [r7, #12]
+}
+ 8019862:	4618      	mov	r0, r3
+ 8019864:	3710      	adds	r7, #16
+ 8019866:	46bd      	mov	sp, r7
+ 8019868:	bd80      	pop	{r7, pc}
+ 801986a:	bf00      	nop
+ 801986c:	2401a480 	.word	0x2401a480
+ 8019870:	2401a496 	.word	0x2401a496
+ 8019874:	0801952d 	.word	0x0801952d
+ 8019878:	006ddd00 	.word	0x006ddd00
+
+0801987c <tcp_new_ip_type>:
+ * supply @ref IPADDR_TYPE_ANY as argument and bind to @ref IP_ANY_TYPE.
+ * @return a new tcp_pcb that initially is in state CLOSED
+ */
+struct tcp_pcb *
+tcp_new_ip_type(u8_t type)
+{
+ 801987c:	b580      	push	{r7, lr}
+ 801987e:	b084      	sub	sp, #16
+ 8019880:	af00      	add	r7, sp, #0
+ 8019882:	4603      	mov	r3, r0
+ 8019884:	71fb      	strb	r3, [r7, #7]
+  struct tcp_pcb *pcb;
+  pcb = tcp_alloc(TCP_PRIO_NORMAL);
+ 8019886:	2040      	movs	r0, #64	; 0x40
+ 8019888:	f7ff ff74 	bl	8019774 <tcp_alloc>
+ 801988c:	60f8      	str	r0, [r7, #12]
+    IP_SET_TYPE_VAL(pcb->remote_ip, type);
+  }
+#else
+  LWIP_UNUSED_ARG(type);
+#endif /* LWIP_IPV4 && LWIP_IPV6 */
+  return pcb;
+ 801988e:	68fb      	ldr	r3, [r7, #12]
+}
+ 8019890:	4618      	mov	r0, r3
+ 8019892:	3710      	adds	r7, #16
+ 8019894:	46bd      	mov	sp, r7
+ 8019896:	bd80      	pop	{r7, pc}
+
+08019898 <tcp_arg>:
+ * @param pcb tcp_pcb to set the callback argument
+ * @param arg void pointer argument to pass to callback functions
+ */
+void
+tcp_arg(struct tcp_pcb *pcb, void *arg)
+{
+ 8019898:	b480      	push	{r7}
+ 801989a:	b083      	sub	sp, #12
+ 801989c:	af00      	add	r7, sp, #0
+ 801989e:	6078      	str	r0, [r7, #4]
+ 80198a0:	6039      	str	r1, [r7, #0]
+  LWIP_ASSERT_CORE_LOCKED();
+  /* This function is allowed to be called for both listen pcbs and
+     connection pcbs. */
+  if (pcb != NULL) {
+ 80198a2:	687b      	ldr	r3, [r7, #4]
+ 80198a4:	2b00      	cmp	r3, #0
+ 80198a6:	d002      	beq.n	80198ae <tcp_arg+0x16>
+    pcb->callback_arg = arg;
+ 80198a8:	687b      	ldr	r3, [r7, #4]
+ 80198aa:	683a      	ldr	r2, [r7, #0]
+ 80198ac:	611a      	str	r2, [r3, #16]
+  }
+}
+ 80198ae:	bf00      	nop
+ 80198b0:	370c      	adds	r7, #12
+ 80198b2:	46bd      	mov	sp, r7
+ 80198b4:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 80198b8:	4770      	bx	lr
+	...
+
+080198bc <tcp_recv>:
+ * @param pcb tcp_pcb to set the recv callback
+ * @param recv callback function to call for this pcb when data is received
+ */
+void
+tcp_recv(struct tcp_pcb *pcb, tcp_recv_fn recv)
+{
+ 80198bc:	b580      	push	{r7, lr}
+ 80198be:	b082      	sub	sp, #8
+ 80198c0:	af00      	add	r7, sp, #0
+ 80198c2:	6078      	str	r0, [r7, #4]
+ 80198c4:	6039      	str	r1, [r7, #0]
+  LWIP_ASSERT_CORE_LOCKED();
+  if (pcb != NULL) {
+ 80198c6:	687b      	ldr	r3, [r7, #4]
+ 80198c8:	2b00      	cmp	r3, #0
+ 80198ca:	d00e      	beq.n	80198ea <tcp_recv+0x2e>
+    LWIP_ASSERT("invalid socket state for recv callback", pcb->state != LISTEN);
+ 80198cc:	687b      	ldr	r3, [r7, #4]
+ 80198ce:	7d1b      	ldrb	r3, [r3, #20]
+ 80198d0:	2b01      	cmp	r3, #1
+ 80198d2:	d106      	bne.n	80198e2 <tcp_recv+0x26>
+ 80198d4:	4b07      	ldr	r3, [pc, #28]	; (80198f4 <tcp_recv+0x38>)
+ 80198d6:	f240 72df 	movw	r2, #2015	; 0x7df
+ 80198da:	4907      	ldr	r1, [pc, #28]	; (80198f8 <tcp_recv+0x3c>)
+ 80198dc:	4807      	ldr	r0, [pc, #28]	; (80198fc <tcp_recv+0x40>)
+ 80198de:	f008 f853 	bl	8021988 <iprintf>
+    pcb->recv = recv;
+ 80198e2:	687b      	ldr	r3, [r7, #4]
+ 80198e4:	683a      	ldr	r2, [r7, #0]
+ 80198e6:	f8c3 2084 	str.w	r2, [r3, #132]	; 0x84
+  }
+}
+ 80198ea:	bf00      	nop
+ 80198ec:	3708      	adds	r7, #8
+ 80198ee:	46bd      	mov	sp, r7
+ 80198f0:	bd80      	pop	{r7, pc}
+ 80198f2:	bf00      	nop
+ 80198f4:	08024ba8 	.word	0x08024ba8
+ 80198f8:	08025144 	.word	0x08025144
+ 80198fc:	08024bec 	.word	0x08024bec
+
+08019900 <tcp_sent>:
+ * @param pcb tcp_pcb to set the sent callback
+ * @param sent callback function to call for this pcb when data is successfully sent
+ */
+void
+tcp_sent(struct tcp_pcb *pcb, tcp_sent_fn sent)
+{
+ 8019900:	b580      	push	{r7, lr}
+ 8019902:	b082      	sub	sp, #8
+ 8019904:	af00      	add	r7, sp, #0
+ 8019906:	6078      	str	r0, [r7, #4]
+ 8019908:	6039      	str	r1, [r7, #0]
+  LWIP_ASSERT_CORE_LOCKED();
+  if (pcb != NULL) {
+ 801990a:	687b      	ldr	r3, [r7, #4]
+ 801990c:	2b00      	cmp	r3, #0
+ 801990e:	d00e      	beq.n	801992e <tcp_sent+0x2e>
+    LWIP_ASSERT("invalid socket state for sent callback", pcb->state != LISTEN);
+ 8019910:	687b      	ldr	r3, [r7, #4]
+ 8019912:	7d1b      	ldrb	r3, [r3, #20]
+ 8019914:	2b01      	cmp	r3, #1
+ 8019916:	d106      	bne.n	8019926 <tcp_sent+0x26>
+ 8019918:	4b07      	ldr	r3, [pc, #28]	; (8019938 <tcp_sent+0x38>)
+ 801991a:	f240 72f3 	movw	r2, #2035	; 0x7f3
+ 801991e:	4907      	ldr	r1, [pc, #28]	; (801993c <tcp_sent+0x3c>)
+ 8019920:	4807      	ldr	r0, [pc, #28]	; (8019940 <tcp_sent+0x40>)
+ 8019922:	f008 f831 	bl	8021988 <iprintf>
+    pcb->sent = sent;
+ 8019926:	687b      	ldr	r3, [r7, #4]
+ 8019928:	683a      	ldr	r2, [r7, #0]
+ 801992a:	f8c3 2080 	str.w	r2, [r3, #128]	; 0x80
+  }
+}
+ 801992e:	bf00      	nop
+ 8019930:	3708      	adds	r7, #8
+ 8019932:	46bd      	mov	sp, r7
+ 8019934:	bd80      	pop	{r7, pc}
+ 8019936:	bf00      	nop
+ 8019938:	08024ba8 	.word	0x08024ba8
+ 801993c:	0802516c 	.word	0x0802516c
+ 8019940:	08024bec 	.word	0x08024bec
+
+08019944 <tcp_err>:
+ * @param err callback function to call for this pcb when a fatal error
+ *        has occurred on the connection
+ */
+void
+tcp_err(struct tcp_pcb *pcb, tcp_err_fn err)
+{
+ 8019944:	b580      	push	{r7, lr}
+ 8019946:	b082      	sub	sp, #8
+ 8019948:	af00      	add	r7, sp, #0
+ 801994a:	6078      	str	r0, [r7, #4]
+ 801994c:	6039      	str	r1, [r7, #0]
+  LWIP_ASSERT_CORE_LOCKED();
+  if (pcb != NULL) {
+ 801994e:	687b      	ldr	r3, [r7, #4]
+ 8019950:	2b00      	cmp	r3, #0
+ 8019952:	d00e      	beq.n	8019972 <tcp_err+0x2e>
+    LWIP_ASSERT("invalid socket state for err callback", pcb->state != LISTEN);
+ 8019954:	687b      	ldr	r3, [r7, #4]
+ 8019956:	7d1b      	ldrb	r3, [r3, #20]
+ 8019958:	2b01      	cmp	r3, #1
+ 801995a:	d106      	bne.n	801996a <tcp_err+0x26>
+ 801995c:	4b07      	ldr	r3, [pc, #28]	; (801997c <tcp_err+0x38>)
+ 801995e:	f640 020d 	movw	r2, #2061	; 0x80d
+ 8019962:	4907      	ldr	r1, [pc, #28]	; (8019980 <tcp_err+0x3c>)
+ 8019964:	4807      	ldr	r0, [pc, #28]	; (8019984 <tcp_err+0x40>)
+ 8019966:	f008 f80f 	bl	8021988 <iprintf>
+    pcb->errf = err;
+ 801996a:	687b      	ldr	r3, [r7, #4]
+ 801996c:	683a      	ldr	r2, [r7, #0]
+ 801996e:	f8c3 2090 	str.w	r2, [r3, #144]	; 0x90
+  }
+}
+ 8019972:	bf00      	nop
+ 8019974:	3708      	adds	r7, #8
+ 8019976:	46bd      	mov	sp, r7
+ 8019978:	bd80      	pop	{r7, pc}
+ 801997a:	bf00      	nop
+ 801997c:	08024ba8 	.word	0x08024ba8
+ 8019980:	08025194 	.word	0x08025194
+ 8019984:	08024bec 	.word	0x08024bec
+
+08019988 <tcp_accept>:
+ * @param accept callback function to call for this pcb when LISTENing
+ *        connection has been connected to another host
+ */
+void
+tcp_accept(struct tcp_pcb *pcb, tcp_accept_fn accept)
+{
+ 8019988:	b480      	push	{r7}
+ 801998a:	b085      	sub	sp, #20
+ 801998c:	af00      	add	r7, sp, #0
+ 801998e:	6078      	str	r0, [r7, #4]
+ 8019990:	6039      	str	r1, [r7, #0]
+  LWIP_ASSERT_CORE_LOCKED();
+  if ((pcb != NULL) && (pcb->state == LISTEN)) {
+ 8019992:	687b      	ldr	r3, [r7, #4]
+ 8019994:	2b00      	cmp	r3, #0
+ 8019996:	d008      	beq.n	80199aa <tcp_accept+0x22>
+ 8019998:	687b      	ldr	r3, [r7, #4]
+ 801999a:	7d1b      	ldrb	r3, [r3, #20]
+ 801999c:	2b01      	cmp	r3, #1
+ 801999e:	d104      	bne.n	80199aa <tcp_accept+0x22>
+    struct tcp_pcb_listen *lpcb = (struct tcp_pcb_listen *)pcb;
+ 80199a0:	687b      	ldr	r3, [r7, #4]
+ 80199a2:	60fb      	str	r3, [r7, #12]
+    lpcb->accept = accept;
+ 80199a4:	68fb      	ldr	r3, [r7, #12]
+ 80199a6:	683a      	ldr	r2, [r7, #0]
+ 80199a8:	619a      	str	r2, [r3, #24]
+  }
+}
+ 80199aa:	bf00      	nop
+ 80199ac:	3714      	adds	r7, #20
+ 80199ae:	46bd      	mov	sp, r7
+ 80199b0:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 80199b4:	4770      	bx	lr
+	...
+
+080199b8 <tcp_poll>:
+ * the application may use the polling functionality to call tcp_write()
+ * again when the connection has been idle for a while.
+ */
+void
+tcp_poll(struct tcp_pcb *pcb, tcp_poll_fn poll, u8_t interval)
+{
+ 80199b8:	b580      	push	{r7, lr}
+ 80199ba:	b084      	sub	sp, #16
+ 80199bc:	af00      	add	r7, sp, #0
+ 80199be:	60f8      	str	r0, [r7, #12]
+ 80199c0:	60b9      	str	r1, [r7, #8]
+ 80199c2:	4613      	mov	r3, r2
+ 80199c4:	71fb      	strb	r3, [r7, #7]
+  LWIP_ASSERT_CORE_LOCKED();
+
+  LWIP_ERROR("tcp_poll: invalid pcb", pcb != NULL, return);
+ 80199c6:	68fb      	ldr	r3, [r7, #12]
+ 80199c8:	2b00      	cmp	r3, #0
+ 80199ca:	d107      	bne.n	80199dc <tcp_poll+0x24>
+ 80199cc:	4b0e      	ldr	r3, [pc, #56]	; (8019a08 <tcp_poll+0x50>)
+ 80199ce:	f640 023d 	movw	r2, #2109	; 0x83d
+ 80199d2:	490e      	ldr	r1, [pc, #56]	; (8019a0c <tcp_poll+0x54>)
+ 80199d4:	480e      	ldr	r0, [pc, #56]	; (8019a10 <tcp_poll+0x58>)
+ 80199d6:	f007 ffd7 	bl	8021988 <iprintf>
+ 80199da:	e011      	b.n	8019a00 <tcp_poll+0x48>
+  LWIP_ASSERT("invalid socket state for poll", pcb->state != LISTEN);
+ 80199dc:	68fb      	ldr	r3, [r7, #12]
+ 80199de:	7d1b      	ldrb	r3, [r3, #20]
+ 80199e0:	2b01      	cmp	r3, #1
+ 80199e2:	d106      	bne.n	80199f2 <tcp_poll+0x3a>
+ 80199e4:	4b08      	ldr	r3, [pc, #32]	; (8019a08 <tcp_poll+0x50>)
+ 80199e6:	f640 023e 	movw	r2, #2110	; 0x83e
+ 80199ea:	490a      	ldr	r1, [pc, #40]	; (8019a14 <tcp_poll+0x5c>)
+ 80199ec:	4808      	ldr	r0, [pc, #32]	; (8019a10 <tcp_poll+0x58>)
+ 80199ee:	f007 ffcb 	bl	8021988 <iprintf>
+
+#if LWIP_CALLBACK_API
+  pcb->poll = poll;
+ 80199f2:	68fb      	ldr	r3, [r7, #12]
+ 80199f4:	68ba      	ldr	r2, [r7, #8]
+ 80199f6:	f8c3 208c 	str.w	r2, [r3, #140]	; 0x8c
+#else /* LWIP_CALLBACK_API */
+  LWIP_UNUSED_ARG(poll);
+#endif /* LWIP_CALLBACK_API */
+  pcb->pollinterval = interval;
+ 80199fa:	68fb      	ldr	r3, [r7, #12]
+ 80199fc:	79fa      	ldrb	r2, [r7, #7]
+ 80199fe:	775a      	strb	r2, [r3, #29]
+}
+ 8019a00:	3710      	adds	r7, #16
+ 8019a02:	46bd      	mov	sp, r7
+ 8019a04:	bd80      	pop	{r7, pc}
+ 8019a06:	bf00      	nop
+ 8019a08:	08024ba8 	.word	0x08024ba8
+ 8019a0c:	080251bc 	.word	0x080251bc
+ 8019a10:	08024bec 	.word	0x08024bec
+ 8019a14:	080251d4 	.word	0x080251d4
+
+08019a18 <tcp_pcb_purge>:
+ *
+ * @param pcb tcp_pcb to purge. The pcb itself is not deallocated!
+ */
+void
+tcp_pcb_purge(struct tcp_pcb *pcb)
+{
+ 8019a18:	b580      	push	{r7, lr}
+ 8019a1a:	b082      	sub	sp, #8
+ 8019a1c:	af00      	add	r7, sp, #0
+ 8019a1e:	6078      	str	r0, [r7, #4]
+  LWIP_ERROR("tcp_pcb_purge: invalid pcb", pcb != NULL, return);
+ 8019a20:	687b      	ldr	r3, [r7, #4]
+ 8019a22:	2b00      	cmp	r3, #0
+ 8019a24:	d107      	bne.n	8019a36 <tcp_pcb_purge+0x1e>
+ 8019a26:	4b21      	ldr	r3, [pc, #132]	; (8019aac <tcp_pcb_purge+0x94>)
+ 8019a28:	f640 0251 	movw	r2, #2129	; 0x851
+ 8019a2c:	4920      	ldr	r1, [pc, #128]	; (8019ab0 <tcp_pcb_purge+0x98>)
+ 8019a2e:	4821      	ldr	r0, [pc, #132]	; (8019ab4 <tcp_pcb_purge+0x9c>)
+ 8019a30:	f007 ffaa 	bl	8021988 <iprintf>
+ 8019a34:	e037      	b.n	8019aa6 <tcp_pcb_purge+0x8e>
+
+  if (pcb->state != CLOSED &&
+ 8019a36:	687b      	ldr	r3, [r7, #4]
+ 8019a38:	7d1b      	ldrb	r3, [r3, #20]
+ 8019a3a:	2b00      	cmp	r3, #0
+ 8019a3c:	d033      	beq.n	8019aa6 <tcp_pcb_purge+0x8e>
+      pcb->state != TIME_WAIT &&
+ 8019a3e:	687b      	ldr	r3, [r7, #4]
+ 8019a40:	7d1b      	ldrb	r3, [r3, #20]
+  if (pcb->state != CLOSED &&
+ 8019a42:	2b0a      	cmp	r3, #10
+ 8019a44:	d02f      	beq.n	8019aa6 <tcp_pcb_purge+0x8e>
+      pcb->state != LISTEN) {
+ 8019a46:	687b      	ldr	r3, [r7, #4]
+ 8019a48:	7d1b      	ldrb	r3, [r3, #20]
+      pcb->state != TIME_WAIT &&
+ 8019a4a:	2b01      	cmp	r3, #1
+ 8019a4c:	d02b      	beq.n	8019aa6 <tcp_pcb_purge+0x8e>
+
+    LWIP_DEBUGF(TCP_DEBUG, ("tcp_pcb_purge\n"));
+
+    tcp_backlog_accepted(pcb);
+
+    if (pcb->refused_data != NULL) {
+ 8019a4e:	687b      	ldr	r3, [r7, #4]
+ 8019a50:	6f9b      	ldr	r3, [r3, #120]	; 0x78
+ 8019a52:	2b00      	cmp	r3, #0
+ 8019a54:	d007      	beq.n	8019a66 <tcp_pcb_purge+0x4e>
+      LWIP_DEBUGF(TCP_DEBUG, ("tcp_pcb_purge: data left on ->refused_data\n"));
+      pbuf_free(pcb->refused_data);
+ 8019a56:	687b      	ldr	r3, [r7, #4]
+ 8019a58:	6f9b      	ldr	r3, [r3, #120]	; 0x78
+ 8019a5a:	4618      	mov	r0, r3
+ 8019a5c:	f7fe f84c 	bl	8017af8 <pbuf_free>
+      pcb->refused_data = NULL;
+ 8019a60:	687b      	ldr	r3, [r7, #4]
+ 8019a62:	2200      	movs	r2, #0
+ 8019a64:	679a      	str	r2, [r3, #120]	; 0x78
+    }
+    if (pcb->unacked != NULL) {
+      LWIP_DEBUGF(TCP_DEBUG, ("tcp_pcb_purge: data left on ->unacked\n"));
+    }
+#if TCP_QUEUE_OOSEQ
+    if (pcb->ooseq != NULL) {
+ 8019a66:	687b      	ldr	r3, [r7, #4]
+ 8019a68:	6f5b      	ldr	r3, [r3, #116]	; 0x74
+ 8019a6a:	2b00      	cmp	r3, #0
+ 8019a6c:	d002      	beq.n	8019a74 <tcp_pcb_purge+0x5c>
+      LWIP_DEBUGF(TCP_DEBUG, ("tcp_pcb_purge: data left on ->ooseq\n"));
+      tcp_free_ooseq(pcb);
+ 8019a6e:	6878      	ldr	r0, [r7, #4]
+ 8019a70:	f000 f98c 	bl	8019d8c <tcp_free_ooseq>
+    }
+#endif /* TCP_QUEUE_OOSEQ */
+
+    /* Stop the retransmission timer as it will expect data on unacked
+       queue if it fires */
+    pcb->rtime = -1;
+ 8019a74:	687b      	ldr	r3, [r7, #4]
+ 8019a76:	f64f 72ff 	movw	r2, #65535	; 0xffff
+ 8019a7a:	861a      	strh	r2, [r3, #48]	; 0x30
+
+    tcp_segs_free(pcb->unsent);
+ 8019a7c:	687b      	ldr	r3, [r7, #4]
+ 8019a7e:	6edb      	ldr	r3, [r3, #108]	; 0x6c
+ 8019a80:	4618      	mov	r0, r3
+ 8019a82:	f7ff fcf9 	bl	8019478 <tcp_segs_free>
+    tcp_segs_free(pcb->unacked);
+ 8019a86:	687b      	ldr	r3, [r7, #4]
+ 8019a88:	6f1b      	ldr	r3, [r3, #112]	; 0x70
+ 8019a8a:	4618      	mov	r0, r3
+ 8019a8c:	f7ff fcf4 	bl	8019478 <tcp_segs_free>
+    pcb->unacked = pcb->unsent = NULL;
+ 8019a90:	687b      	ldr	r3, [r7, #4]
+ 8019a92:	2200      	movs	r2, #0
+ 8019a94:	66da      	str	r2, [r3, #108]	; 0x6c
+ 8019a96:	687b      	ldr	r3, [r7, #4]
+ 8019a98:	6eda      	ldr	r2, [r3, #108]	; 0x6c
+ 8019a9a:	687b      	ldr	r3, [r7, #4]
+ 8019a9c:	671a      	str	r2, [r3, #112]	; 0x70
+#if TCP_OVERSIZE
+    pcb->unsent_oversize = 0;
+ 8019a9e:	687b      	ldr	r3, [r7, #4]
+ 8019aa0:	2200      	movs	r2, #0
+ 8019aa2:	f8a3 2068 	strh.w	r2, [r3, #104]	; 0x68
+#endif /* TCP_OVERSIZE */
+  }
+}
+ 8019aa6:	3708      	adds	r7, #8
+ 8019aa8:	46bd      	mov	sp, r7
+ 8019aaa:	bd80      	pop	{r7, pc}
+ 8019aac:	08024ba8 	.word	0x08024ba8
+ 8019ab0:	080251f4 	.word	0x080251f4
+ 8019ab4:	08024bec 	.word	0x08024bec
+
+08019ab8 <tcp_pcb_remove>:
+ * @param pcblist PCB list to purge.
+ * @param pcb tcp_pcb to purge. The pcb itself is NOT deallocated!
+ */
+void
+tcp_pcb_remove(struct tcp_pcb **pcblist, struct tcp_pcb *pcb)
+{
+ 8019ab8:	b580      	push	{r7, lr}
+ 8019aba:	b084      	sub	sp, #16
+ 8019abc:	af00      	add	r7, sp, #0
+ 8019abe:	6078      	str	r0, [r7, #4]
+ 8019ac0:	6039      	str	r1, [r7, #0]
+  LWIP_ASSERT("tcp_pcb_remove: invalid pcb", pcb != NULL);
+ 8019ac2:	683b      	ldr	r3, [r7, #0]
+ 8019ac4:	2b00      	cmp	r3, #0
+ 8019ac6:	d106      	bne.n	8019ad6 <tcp_pcb_remove+0x1e>
+ 8019ac8:	4b3e      	ldr	r3, [pc, #248]	; (8019bc4 <tcp_pcb_remove+0x10c>)
+ 8019aca:	f640 0283 	movw	r2, #2179	; 0x883
+ 8019ace:	493e      	ldr	r1, [pc, #248]	; (8019bc8 <tcp_pcb_remove+0x110>)
+ 8019ad0:	483e      	ldr	r0, [pc, #248]	; (8019bcc <tcp_pcb_remove+0x114>)
+ 8019ad2:	f007 ff59 	bl	8021988 <iprintf>
+  LWIP_ASSERT("tcp_pcb_remove: invalid pcblist", pcblist != NULL);
+ 8019ad6:	687b      	ldr	r3, [r7, #4]
+ 8019ad8:	2b00      	cmp	r3, #0
+ 8019ada:	d106      	bne.n	8019aea <tcp_pcb_remove+0x32>
+ 8019adc:	4b39      	ldr	r3, [pc, #228]	; (8019bc4 <tcp_pcb_remove+0x10c>)
+ 8019ade:	f640 0284 	movw	r2, #2180	; 0x884
+ 8019ae2:	493b      	ldr	r1, [pc, #236]	; (8019bd0 <tcp_pcb_remove+0x118>)
+ 8019ae4:	4839      	ldr	r0, [pc, #228]	; (8019bcc <tcp_pcb_remove+0x114>)
+ 8019ae6:	f007 ff4f 	bl	8021988 <iprintf>
+
+  TCP_RMV(pcblist, pcb);
+ 8019aea:	687b      	ldr	r3, [r7, #4]
+ 8019aec:	681b      	ldr	r3, [r3, #0]
+ 8019aee:	683a      	ldr	r2, [r7, #0]
+ 8019af0:	429a      	cmp	r2, r3
+ 8019af2:	d105      	bne.n	8019b00 <tcp_pcb_remove+0x48>
+ 8019af4:	687b      	ldr	r3, [r7, #4]
+ 8019af6:	681b      	ldr	r3, [r3, #0]
+ 8019af8:	68da      	ldr	r2, [r3, #12]
+ 8019afa:	687b      	ldr	r3, [r7, #4]
+ 8019afc:	601a      	str	r2, [r3, #0]
+ 8019afe:	e013      	b.n	8019b28 <tcp_pcb_remove+0x70>
+ 8019b00:	687b      	ldr	r3, [r7, #4]
+ 8019b02:	681b      	ldr	r3, [r3, #0]
+ 8019b04:	60fb      	str	r3, [r7, #12]
+ 8019b06:	e00c      	b.n	8019b22 <tcp_pcb_remove+0x6a>
+ 8019b08:	68fb      	ldr	r3, [r7, #12]
+ 8019b0a:	68db      	ldr	r3, [r3, #12]
+ 8019b0c:	683a      	ldr	r2, [r7, #0]
+ 8019b0e:	429a      	cmp	r2, r3
+ 8019b10:	d104      	bne.n	8019b1c <tcp_pcb_remove+0x64>
+ 8019b12:	683b      	ldr	r3, [r7, #0]
+ 8019b14:	68da      	ldr	r2, [r3, #12]
+ 8019b16:	68fb      	ldr	r3, [r7, #12]
+ 8019b18:	60da      	str	r2, [r3, #12]
+ 8019b1a:	e005      	b.n	8019b28 <tcp_pcb_remove+0x70>
+ 8019b1c:	68fb      	ldr	r3, [r7, #12]
+ 8019b1e:	68db      	ldr	r3, [r3, #12]
+ 8019b20:	60fb      	str	r3, [r7, #12]
+ 8019b22:	68fb      	ldr	r3, [r7, #12]
+ 8019b24:	2b00      	cmp	r3, #0
+ 8019b26:	d1ef      	bne.n	8019b08 <tcp_pcb_remove+0x50>
+ 8019b28:	683b      	ldr	r3, [r7, #0]
+ 8019b2a:	2200      	movs	r2, #0
+ 8019b2c:	60da      	str	r2, [r3, #12]
+
+  tcp_pcb_purge(pcb);
+ 8019b2e:	6838      	ldr	r0, [r7, #0]
+ 8019b30:	f7ff ff72 	bl	8019a18 <tcp_pcb_purge>
+
+  /* if there is an outstanding delayed ACKs, send it */
+  if ((pcb->state != TIME_WAIT) &&
+ 8019b34:	683b      	ldr	r3, [r7, #0]
+ 8019b36:	7d1b      	ldrb	r3, [r3, #20]
+ 8019b38:	2b0a      	cmp	r3, #10
+ 8019b3a:	d013      	beq.n	8019b64 <tcp_pcb_remove+0xac>
+      (pcb->state != LISTEN) &&
+ 8019b3c:	683b      	ldr	r3, [r7, #0]
+ 8019b3e:	7d1b      	ldrb	r3, [r3, #20]
+  if ((pcb->state != TIME_WAIT) &&
+ 8019b40:	2b01      	cmp	r3, #1
+ 8019b42:	d00f      	beq.n	8019b64 <tcp_pcb_remove+0xac>
+      (pcb->flags & TF_ACK_DELAY)) {
+ 8019b44:	683b      	ldr	r3, [r7, #0]
+ 8019b46:	8b5b      	ldrh	r3, [r3, #26]
+ 8019b48:	f003 0301 	and.w	r3, r3, #1
+      (pcb->state != LISTEN) &&
+ 8019b4c:	2b00      	cmp	r3, #0
+ 8019b4e:	d009      	beq.n	8019b64 <tcp_pcb_remove+0xac>
+    tcp_ack_now(pcb);
+ 8019b50:	683b      	ldr	r3, [r7, #0]
+ 8019b52:	8b5b      	ldrh	r3, [r3, #26]
+ 8019b54:	f043 0302 	orr.w	r3, r3, #2
+ 8019b58:	b29a      	uxth	r2, r3
+ 8019b5a:	683b      	ldr	r3, [r7, #0]
+ 8019b5c:	835a      	strh	r2, [r3, #26]
+    tcp_output(pcb);
+ 8019b5e:	6838      	ldr	r0, [r7, #0]
+ 8019b60:	f003 fc2c 	bl	801d3bc <tcp_output>
+  }
+
+  if (pcb->state != LISTEN) {
+ 8019b64:	683b      	ldr	r3, [r7, #0]
+ 8019b66:	7d1b      	ldrb	r3, [r3, #20]
+ 8019b68:	2b01      	cmp	r3, #1
+ 8019b6a:	d020      	beq.n	8019bae <tcp_pcb_remove+0xf6>
+    LWIP_ASSERT("unsent segments leaking", pcb->unsent == NULL);
+ 8019b6c:	683b      	ldr	r3, [r7, #0]
+ 8019b6e:	6edb      	ldr	r3, [r3, #108]	; 0x6c
+ 8019b70:	2b00      	cmp	r3, #0
+ 8019b72:	d006      	beq.n	8019b82 <tcp_pcb_remove+0xca>
+ 8019b74:	4b13      	ldr	r3, [pc, #76]	; (8019bc4 <tcp_pcb_remove+0x10c>)
+ 8019b76:	f640 0293 	movw	r2, #2195	; 0x893
+ 8019b7a:	4916      	ldr	r1, [pc, #88]	; (8019bd4 <tcp_pcb_remove+0x11c>)
+ 8019b7c:	4813      	ldr	r0, [pc, #76]	; (8019bcc <tcp_pcb_remove+0x114>)
+ 8019b7e:	f007 ff03 	bl	8021988 <iprintf>
+    LWIP_ASSERT("unacked segments leaking", pcb->unacked == NULL);
+ 8019b82:	683b      	ldr	r3, [r7, #0]
+ 8019b84:	6f1b      	ldr	r3, [r3, #112]	; 0x70
+ 8019b86:	2b00      	cmp	r3, #0
+ 8019b88:	d006      	beq.n	8019b98 <tcp_pcb_remove+0xe0>
+ 8019b8a:	4b0e      	ldr	r3, [pc, #56]	; (8019bc4 <tcp_pcb_remove+0x10c>)
+ 8019b8c:	f640 0294 	movw	r2, #2196	; 0x894
+ 8019b90:	4911      	ldr	r1, [pc, #68]	; (8019bd8 <tcp_pcb_remove+0x120>)
+ 8019b92:	480e      	ldr	r0, [pc, #56]	; (8019bcc <tcp_pcb_remove+0x114>)
+ 8019b94:	f007 fef8 	bl	8021988 <iprintf>
+#if TCP_QUEUE_OOSEQ
+    LWIP_ASSERT("ooseq segments leaking", pcb->ooseq == NULL);
+ 8019b98:	683b      	ldr	r3, [r7, #0]
+ 8019b9a:	6f5b      	ldr	r3, [r3, #116]	; 0x74
+ 8019b9c:	2b00      	cmp	r3, #0
+ 8019b9e:	d006      	beq.n	8019bae <tcp_pcb_remove+0xf6>
+ 8019ba0:	4b08      	ldr	r3, [pc, #32]	; (8019bc4 <tcp_pcb_remove+0x10c>)
+ 8019ba2:	f640 0296 	movw	r2, #2198	; 0x896
+ 8019ba6:	490d      	ldr	r1, [pc, #52]	; (8019bdc <tcp_pcb_remove+0x124>)
+ 8019ba8:	4808      	ldr	r0, [pc, #32]	; (8019bcc <tcp_pcb_remove+0x114>)
+ 8019baa:	f007 feed 	bl	8021988 <iprintf>
+#endif /* TCP_QUEUE_OOSEQ */
+  }
+
+  pcb->state = CLOSED;
+ 8019bae:	683b      	ldr	r3, [r7, #0]
+ 8019bb0:	2200      	movs	r2, #0
+ 8019bb2:	751a      	strb	r2, [r3, #20]
+  /* reset the local port to prevent the pcb from being 'bound' */
+  pcb->local_port = 0;
+ 8019bb4:	683b      	ldr	r3, [r7, #0]
+ 8019bb6:	2200      	movs	r2, #0
+ 8019bb8:	82da      	strh	r2, [r3, #22]
+
+  LWIP_ASSERT("tcp_pcb_remove: tcp_pcbs_sane()", tcp_pcbs_sane());
+}
+ 8019bba:	bf00      	nop
+ 8019bbc:	3710      	adds	r7, #16
+ 8019bbe:	46bd      	mov	sp, r7
+ 8019bc0:	bd80      	pop	{r7, pc}
+ 8019bc2:	bf00      	nop
+ 8019bc4:	08024ba8 	.word	0x08024ba8
+ 8019bc8:	08025210 	.word	0x08025210
+ 8019bcc:	08024bec 	.word	0x08024bec
+ 8019bd0:	0802522c 	.word	0x0802522c
+ 8019bd4:	0802524c 	.word	0x0802524c
+ 8019bd8:	08025264 	.word	0x08025264
+ 8019bdc:	08025280 	.word	0x08025280
+
+08019be0 <tcp_next_iss>:
+ *
+ * @return u32_t pseudo random sequence number
+ */
+u32_t
+tcp_next_iss(struct tcp_pcb *pcb)
+{
+ 8019be0:	b580      	push	{r7, lr}
+ 8019be2:	b082      	sub	sp, #8
+ 8019be4:	af00      	add	r7, sp, #0
+ 8019be6:	6078      	str	r0, [r7, #4]
+  LWIP_ASSERT("tcp_next_iss: invalid pcb", pcb != NULL);
+  return LWIP_HOOK_TCP_ISN(&pcb->local_ip, pcb->local_port, &pcb->remote_ip, pcb->remote_port);
+#else /* LWIP_HOOK_TCP_ISN */
+  static u32_t iss = 6510;
+
+  LWIP_ASSERT("tcp_next_iss: invalid pcb", pcb != NULL);
+ 8019be8:	687b      	ldr	r3, [r7, #4]
+ 8019bea:	2b00      	cmp	r3, #0
+ 8019bec:	d106      	bne.n	8019bfc <tcp_next_iss+0x1c>
+ 8019bee:	4b0a      	ldr	r3, [pc, #40]	; (8019c18 <tcp_next_iss+0x38>)
+ 8019bf0:	f640 02af 	movw	r2, #2223	; 0x8af
+ 8019bf4:	4909      	ldr	r1, [pc, #36]	; (8019c1c <tcp_next_iss+0x3c>)
+ 8019bf6:	480a      	ldr	r0, [pc, #40]	; (8019c20 <tcp_next_iss+0x40>)
+ 8019bf8:	f007 fec6 	bl	8021988 <iprintf>
+  LWIP_UNUSED_ARG(pcb);
+
+  iss += tcp_ticks;       /* XXX */
+ 8019bfc:	4b09      	ldr	r3, [pc, #36]	; (8019c24 <tcp_next_iss+0x44>)
+ 8019bfe:	681a      	ldr	r2, [r3, #0]
+ 8019c00:	4b09      	ldr	r3, [pc, #36]	; (8019c28 <tcp_next_iss+0x48>)
+ 8019c02:	681b      	ldr	r3, [r3, #0]
+ 8019c04:	4413      	add	r3, r2
+ 8019c06:	4a07      	ldr	r2, [pc, #28]	; (8019c24 <tcp_next_iss+0x44>)
+ 8019c08:	6013      	str	r3, [r2, #0]
+  return iss;
+ 8019c0a:	4b06      	ldr	r3, [pc, #24]	; (8019c24 <tcp_next_iss+0x44>)
+ 8019c0c:	681b      	ldr	r3, [r3, #0]
+#endif /* LWIP_HOOK_TCP_ISN */
+}
+ 8019c0e:	4618      	mov	r0, r3
+ 8019c10:	3708      	adds	r7, #8
+ 8019c12:	46bd      	mov	sp, r7
+ 8019c14:	bd80      	pop	{r7, pc}
+ 8019c16:	bf00      	nop
+ 8019c18:	08024ba8 	.word	0x08024ba8
+ 8019c1c:	08025298 	.word	0x08025298
+ 8019c20:	08024bec 	.word	0x08024bec
+ 8019c24:	24000040 	.word	0x24000040
+ 8019c28:	2401a480 	.word	0x2401a480
+
+08019c2c <tcp_eff_send_mss_netif>:
+ * by calculating the minimum of TCP_MSS and the mtu (if set) of the target
+ * netif (if not NULL).
+ */
+u16_t
+tcp_eff_send_mss_netif(u16_t sendmss, struct netif *outif, const ip_addr_t *dest)
+{
+ 8019c2c:	b580      	push	{r7, lr}
+ 8019c2e:	b086      	sub	sp, #24
+ 8019c30:	af00      	add	r7, sp, #0
+ 8019c32:	4603      	mov	r3, r0
+ 8019c34:	60b9      	str	r1, [r7, #8]
+ 8019c36:	607a      	str	r2, [r7, #4]
+ 8019c38:	81fb      	strh	r3, [r7, #14]
+  u16_t mss_s;
+  u16_t mtu;
+
+  LWIP_UNUSED_ARG(dest); /* in case IPv6 is disabled */
+
+  LWIP_ASSERT("tcp_eff_send_mss_netif: invalid dst_ip", dest != NULL);
+ 8019c3a:	687b      	ldr	r3, [r7, #4]
+ 8019c3c:	2b00      	cmp	r3, #0
+ 8019c3e:	d106      	bne.n	8019c4e <tcp_eff_send_mss_netif+0x22>
+ 8019c40:	4b14      	ldr	r3, [pc, #80]	; (8019c94 <tcp_eff_send_mss_netif+0x68>)
+ 8019c42:	f640 02c5 	movw	r2, #2245	; 0x8c5
+ 8019c46:	4914      	ldr	r1, [pc, #80]	; (8019c98 <tcp_eff_send_mss_netif+0x6c>)
+ 8019c48:	4814      	ldr	r0, [pc, #80]	; (8019c9c <tcp_eff_send_mss_netif+0x70>)
+ 8019c4a:	f007 fe9d 	bl	8021988 <iprintf>
+  else
+#endif /* LWIP_IPV4 */
+#endif /* LWIP_IPV6 */
+#if LWIP_IPV4
+  {
+    if (outif == NULL) {
+ 8019c4e:	68bb      	ldr	r3, [r7, #8]
+ 8019c50:	2b00      	cmp	r3, #0
+ 8019c52:	d101      	bne.n	8019c58 <tcp_eff_send_mss_netif+0x2c>
+      return sendmss;
+ 8019c54:	89fb      	ldrh	r3, [r7, #14]
+ 8019c56:	e019      	b.n	8019c8c <tcp_eff_send_mss_netif+0x60>
+    }
+    mtu = outif->mtu;
+ 8019c58:	68bb      	ldr	r3, [r7, #8]
+ 8019c5a:	8c9b      	ldrh	r3, [r3, #36]	; 0x24
+ 8019c5c:	82fb      	strh	r3, [r7, #22]
+  }
+#endif /* LWIP_IPV4 */
+
+  if (mtu != 0) {
+ 8019c5e:	8afb      	ldrh	r3, [r7, #22]
+ 8019c60:	2b00      	cmp	r3, #0
+ 8019c62:	d012      	beq.n	8019c8a <tcp_eff_send_mss_netif+0x5e>
+    else
+#endif /* LWIP_IPV4 */
+#endif /* LWIP_IPV6 */
+#if LWIP_IPV4
+    {
+      offset = IP_HLEN + TCP_HLEN;
+ 8019c64:	2328      	movs	r3, #40	; 0x28
+ 8019c66:	82bb      	strh	r3, [r7, #20]
+    }
+#endif /* LWIP_IPV4 */
+    mss_s = (mtu > offset) ? (u16_t)(mtu - offset) : 0;
+ 8019c68:	8afa      	ldrh	r2, [r7, #22]
+ 8019c6a:	8abb      	ldrh	r3, [r7, #20]
+ 8019c6c:	429a      	cmp	r2, r3
+ 8019c6e:	d904      	bls.n	8019c7a <tcp_eff_send_mss_netif+0x4e>
+ 8019c70:	8afa      	ldrh	r2, [r7, #22]
+ 8019c72:	8abb      	ldrh	r3, [r7, #20]
+ 8019c74:	1ad3      	subs	r3, r2, r3
+ 8019c76:	b29b      	uxth	r3, r3
+ 8019c78:	e000      	b.n	8019c7c <tcp_eff_send_mss_netif+0x50>
+ 8019c7a:	2300      	movs	r3, #0
+ 8019c7c:	827b      	strh	r3, [r7, #18]
+    /* RFC 1122, chap 4.2.2.6:
+     * Eff.snd.MSS = min(SendMSS+20, MMS_S) - TCPhdrsize - IPoptionsize
+     * We correct for TCP options in tcp_write(), and don't support IP options.
+     */
+    sendmss = LWIP_MIN(sendmss, mss_s);
+ 8019c7e:	8a7a      	ldrh	r2, [r7, #18]
+ 8019c80:	89fb      	ldrh	r3, [r7, #14]
+ 8019c82:	4293      	cmp	r3, r2
+ 8019c84:	bf28      	it	cs
+ 8019c86:	4613      	movcs	r3, r2
+ 8019c88:	81fb      	strh	r3, [r7, #14]
+  }
+  return sendmss;
+ 8019c8a:	89fb      	ldrh	r3, [r7, #14]
+}
+ 8019c8c:	4618      	mov	r0, r3
+ 8019c8e:	3718      	adds	r7, #24
+ 8019c90:	46bd      	mov	sp, r7
+ 8019c92:	bd80      	pop	{r7, pc}
+ 8019c94:	08024ba8 	.word	0x08024ba8
+ 8019c98:	080252b4 	.word	0x080252b4
+ 8019c9c:	08024bec 	.word	0x08024bec
+
+08019ca0 <tcp_netif_ip_addr_changed_pcblist>:
+#endif /* TCP_CALCULATE_EFF_SEND_MSS */
+
+/** Helper function for tcp_netif_ip_addr_changed() that iterates a pcb list */
+static void
+tcp_netif_ip_addr_changed_pcblist(const ip_addr_t *old_addr, struct tcp_pcb *pcb_list)
+{
+ 8019ca0:	b580      	push	{r7, lr}
+ 8019ca2:	b084      	sub	sp, #16
+ 8019ca4:	af00      	add	r7, sp, #0
+ 8019ca6:	6078      	str	r0, [r7, #4]
+ 8019ca8:	6039      	str	r1, [r7, #0]
+  struct tcp_pcb *pcb;
+  pcb = pcb_list;
+ 8019caa:	683b      	ldr	r3, [r7, #0]
+ 8019cac:	60fb      	str	r3, [r7, #12]
+
+  LWIP_ASSERT("tcp_netif_ip_addr_changed_pcblist: invalid old_addr", old_addr != NULL);
+ 8019cae:	687b      	ldr	r3, [r7, #4]
+ 8019cb0:	2b00      	cmp	r3, #0
+ 8019cb2:	d11d      	bne.n	8019cf0 <tcp_netif_ip_addr_changed_pcblist+0x50>
+ 8019cb4:	4b12      	ldr	r3, [pc, #72]	; (8019d00 <tcp_netif_ip_addr_changed_pcblist+0x60>)
+ 8019cb6:	f44f 6210 	mov.w	r2, #2304	; 0x900
+ 8019cba:	4912      	ldr	r1, [pc, #72]	; (8019d04 <tcp_netif_ip_addr_changed_pcblist+0x64>)
+ 8019cbc:	4812      	ldr	r0, [pc, #72]	; (8019d08 <tcp_netif_ip_addr_changed_pcblist+0x68>)
+ 8019cbe:	f007 fe63 	bl	8021988 <iprintf>
+
+  while (pcb != NULL) {
+ 8019cc2:	e015      	b.n	8019cf0 <tcp_netif_ip_addr_changed_pcblist+0x50>
+    /* PCB bound to current local interface address? */
+    if (ip_addr_cmp(&pcb->local_ip, old_addr)
+ 8019cc4:	68fb      	ldr	r3, [r7, #12]
+ 8019cc6:	681a      	ldr	r2, [r3, #0]
+ 8019cc8:	687b      	ldr	r3, [r7, #4]
+ 8019cca:	681b      	ldr	r3, [r3, #0]
+ 8019ccc:	429a      	cmp	r2, r3
+ 8019cce:	d10c      	bne.n	8019cea <tcp_netif_ip_addr_changed_pcblist+0x4a>
+        /* connections to link-local addresses must persist (RFC3927 ch. 1.9) */
+        && (!IP_IS_V4_VAL(pcb->local_ip) || !ip4_addr_islinklocal(ip_2_ip4(&pcb->local_ip)))
+#endif /* LWIP_AUTOIP */
+       ) {
+      /* this connection must be aborted */
+      struct tcp_pcb *next = pcb->next;
+ 8019cd0:	68fb      	ldr	r3, [r7, #12]
+ 8019cd2:	68db      	ldr	r3, [r3, #12]
+ 8019cd4:	60bb      	str	r3, [r7, #8]
+      LWIP_DEBUGF(NETIF_DEBUG | LWIP_DBG_STATE, ("netif_set_ipaddr: aborting TCP pcb %p\n", (void *)pcb));
+ 8019cd6:	68f9      	ldr	r1, [r7, #12]
+ 8019cd8:	480c      	ldr	r0, [pc, #48]	; (8019d0c <tcp_netif_ip_addr_changed_pcblist+0x6c>)
+ 8019cda:	f007 fe55 	bl	8021988 <iprintf>
+      tcp_abort(pcb);
+ 8019cde:	68f8      	ldr	r0, [r7, #12]
+ 8019ce0:	f7fe fcfa 	bl	80186d8 <tcp_abort>
+      pcb = next;
+ 8019ce4:	68bb      	ldr	r3, [r7, #8]
+ 8019ce6:	60fb      	str	r3, [r7, #12]
+ 8019ce8:	e002      	b.n	8019cf0 <tcp_netif_ip_addr_changed_pcblist+0x50>
+    } else {
+      pcb = pcb->next;
+ 8019cea:	68fb      	ldr	r3, [r7, #12]
+ 8019cec:	68db      	ldr	r3, [r3, #12]
+ 8019cee:	60fb      	str	r3, [r7, #12]
+  while (pcb != NULL) {
+ 8019cf0:	68fb      	ldr	r3, [r7, #12]
+ 8019cf2:	2b00      	cmp	r3, #0
+ 8019cf4:	d1e6      	bne.n	8019cc4 <tcp_netif_ip_addr_changed_pcblist+0x24>
+    }
+  }
+}
+ 8019cf6:	bf00      	nop
+ 8019cf8:	bf00      	nop
+ 8019cfa:	3710      	adds	r7, #16
+ 8019cfc:	46bd      	mov	sp, r7
+ 8019cfe:	bd80      	pop	{r7, pc}
+ 8019d00:	08024ba8 	.word	0x08024ba8
+ 8019d04:	080252dc 	.word	0x080252dc
+ 8019d08:	08024bec 	.word	0x08024bec
+ 8019d0c:	08025310 	.word	0x08025310
+
+08019d10 <tcp_netif_ip_addr_changed>:
+ * @param old_addr IP address of the netif before change
+ * @param new_addr IP address of the netif after change or NULL if netif has been removed
+ */
+void
+tcp_netif_ip_addr_changed(const ip_addr_t *old_addr, const ip_addr_t *new_addr)
+{
+ 8019d10:	b580      	push	{r7, lr}
+ 8019d12:	b084      	sub	sp, #16
+ 8019d14:	af00      	add	r7, sp, #0
+ 8019d16:	6078      	str	r0, [r7, #4]
+ 8019d18:	6039      	str	r1, [r7, #0]
+  struct tcp_pcb_listen *lpcb;
+
+  if (!ip_addr_isany(old_addr)) {
+ 8019d1a:	687b      	ldr	r3, [r7, #4]
+ 8019d1c:	2b00      	cmp	r3, #0
+ 8019d1e:	d02a      	beq.n	8019d76 <tcp_netif_ip_addr_changed+0x66>
+ 8019d20:	687b      	ldr	r3, [r7, #4]
+ 8019d22:	681b      	ldr	r3, [r3, #0]
+ 8019d24:	2b00      	cmp	r3, #0
+ 8019d26:	d026      	beq.n	8019d76 <tcp_netif_ip_addr_changed+0x66>
+    tcp_netif_ip_addr_changed_pcblist(old_addr, tcp_active_pcbs);
+ 8019d28:	4b15      	ldr	r3, [pc, #84]	; (8019d80 <tcp_netif_ip_addr_changed+0x70>)
+ 8019d2a:	681b      	ldr	r3, [r3, #0]
+ 8019d2c:	4619      	mov	r1, r3
+ 8019d2e:	6878      	ldr	r0, [r7, #4]
+ 8019d30:	f7ff ffb6 	bl	8019ca0 <tcp_netif_ip_addr_changed_pcblist>
+    tcp_netif_ip_addr_changed_pcblist(old_addr, tcp_bound_pcbs);
+ 8019d34:	4b13      	ldr	r3, [pc, #76]	; (8019d84 <tcp_netif_ip_addr_changed+0x74>)
+ 8019d36:	681b      	ldr	r3, [r3, #0]
+ 8019d38:	4619      	mov	r1, r3
+ 8019d3a:	6878      	ldr	r0, [r7, #4]
+ 8019d3c:	f7ff ffb0 	bl	8019ca0 <tcp_netif_ip_addr_changed_pcblist>
+
+    if (!ip_addr_isany(new_addr)) {
+ 8019d40:	683b      	ldr	r3, [r7, #0]
+ 8019d42:	2b00      	cmp	r3, #0
+ 8019d44:	d017      	beq.n	8019d76 <tcp_netif_ip_addr_changed+0x66>
+ 8019d46:	683b      	ldr	r3, [r7, #0]
+ 8019d48:	681b      	ldr	r3, [r3, #0]
+ 8019d4a:	2b00      	cmp	r3, #0
+ 8019d4c:	d013      	beq.n	8019d76 <tcp_netif_ip_addr_changed+0x66>
+      /* PCB bound to current local interface address? */
+      for (lpcb = tcp_listen_pcbs.listen_pcbs; lpcb != NULL; lpcb = lpcb->next) {
+ 8019d4e:	4b0e      	ldr	r3, [pc, #56]	; (8019d88 <tcp_netif_ip_addr_changed+0x78>)
+ 8019d50:	681b      	ldr	r3, [r3, #0]
+ 8019d52:	60fb      	str	r3, [r7, #12]
+ 8019d54:	e00c      	b.n	8019d70 <tcp_netif_ip_addr_changed+0x60>
+        /* PCB bound to current local interface address? */
+        if (ip_addr_cmp(&lpcb->local_ip, old_addr)) {
+ 8019d56:	68fb      	ldr	r3, [r7, #12]
+ 8019d58:	681a      	ldr	r2, [r3, #0]
+ 8019d5a:	687b      	ldr	r3, [r7, #4]
+ 8019d5c:	681b      	ldr	r3, [r3, #0]
+ 8019d5e:	429a      	cmp	r2, r3
+ 8019d60:	d103      	bne.n	8019d6a <tcp_netif_ip_addr_changed+0x5a>
+          /* The PCB is listening to the old ipaddr and
+            * is set to listen to the new one instead */
+          ip_addr_copy(lpcb->local_ip, *new_addr);
+ 8019d62:	683b      	ldr	r3, [r7, #0]
+ 8019d64:	681a      	ldr	r2, [r3, #0]
+ 8019d66:	68fb      	ldr	r3, [r7, #12]
+ 8019d68:	601a      	str	r2, [r3, #0]
+      for (lpcb = tcp_listen_pcbs.listen_pcbs; lpcb != NULL; lpcb = lpcb->next) {
+ 8019d6a:	68fb      	ldr	r3, [r7, #12]
+ 8019d6c:	68db      	ldr	r3, [r3, #12]
+ 8019d6e:	60fb      	str	r3, [r7, #12]
+ 8019d70:	68fb      	ldr	r3, [r7, #12]
+ 8019d72:	2b00      	cmp	r3, #0
+ 8019d74:	d1ef      	bne.n	8019d56 <tcp_netif_ip_addr_changed+0x46>
+        }
+      }
+    }
+  }
+}
+ 8019d76:	bf00      	nop
+ 8019d78:	3710      	adds	r7, #16
+ 8019d7a:	46bd      	mov	sp, r7
+ 8019d7c:	bd80      	pop	{r7, pc}
+ 8019d7e:	bf00      	nop
+ 8019d80:	2401a48c 	.word	0x2401a48c
+ 8019d84:	2401a484 	.word	0x2401a484
+ 8019d88:	2401a488 	.word	0x2401a488
+
+08019d8c <tcp_free_ooseq>:
+
+#if TCP_QUEUE_OOSEQ
+/* Free all ooseq pbufs (and possibly reset SACK state) */
+void
+tcp_free_ooseq(struct tcp_pcb *pcb)
+{
+ 8019d8c:	b580      	push	{r7, lr}
+ 8019d8e:	b082      	sub	sp, #8
+ 8019d90:	af00      	add	r7, sp, #0
+ 8019d92:	6078      	str	r0, [r7, #4]
+  if (pcb->ooseq) {
+ 8019d94:	687b      	ldr	r3, [r7, #4]
+ 8019d96:	6f5b      	ldr	r3, [r3, #116]	; 0x74
+ 8019d98:	2b00      	cmp	r3, #0
+ 8019d9a:	d007      	beq.n	8019dac <tcp_free_ooseq+0x20>
+    tcp_segs_free(pcb->ooseq);
+ 8019d9c:	687b      	ldr	r3, [r7, #4]
+ 8019d9e:	6f5b      	ldr	r3, [r3, #116]	; 0x74
+ 8019da0:	4618      	mov	r0, r3
+ 8019da2:	f7ff fb69 	bl	8019478 <tcp_segs_free>
+    pcb->ooseq = NULL;
+ 8019da6:	687b      	ldr	r3, [r7, #4]
+ 8019da8:	2200      	movs	r2, #0
+ 8019daa:	675a      	str	r2, [r3, #116]	; 0x74
+#if LWIP_TCP_SACK_OUT
+    memset(pcb->rcv_sacks, 0, sizeof(pcb->rcv_sacks));
+#endif /* LWIP_TCP_SACK_OUT */
+  }
+}
+ 8019dac:	bf00      	nop
+ 8019dae:	3708      	adds	r7, #8
+ 8019db0:	46bd      	mov	sp, r7
+ 8019db2:	bd80      	pop	{r7, pc}
+
+08019db4 <tcp_input>:
+ * @param p received TCP segment to process (p->payload pointing to the TCP header)
+ * @param inp network interface on which this segment was received
+ */
+void
+tcp_input(struct pbuf *p, struct netif *inp)
+{
+ 8019db4:	b590      	push	{r4, r7, lr}
+ 8019db6:	b08d      	sub	sp, #52	; 0x34
+ 8019db8:	af04      	add	r7, sp, #16
+ 8019dba:	6078      	str	r0, [r7, #4]
+ 8019dbc:	6039      	str	r1, [r7, #0]
+  u8_t hdrlen_bytes;
+  err_t err;
+
+  LWIP_UNUSED_ARG(inp);
+  LWIP_ASSERT_CORE_LOCKED();
+  LWIP_ASSERT("tcp_input: invalid pbuf", p != NULL);
+ 8019dbe:	687b      	ldr	r3, [r7, #4]
+ 8019dc0:	2b00      	cmp	r3, #0
+ 8019dc2:	d105      	bne.n	8019dd0 <tcp_input+0x1c>
+ 8019dc4:	4b9b      	ldr	r3, [pc, #620]	; (801a034 <tcp_input+0x280>)
+ 8019dc6:	2283      	movs	r2, #131	; 0x83
+ 8019dc8:	499b      	ldr	r1, [pc, #620]	; (801a038 <tcp_input+0x284>)
+ 8019dca:	489c      	ldr	r0, [pc, #624]	; (801a03c <tcp_input+0x288>)
+ 8019dcc:	f007 fddc 	bl	8021988 <iprintf>
+  PERF_START;
+
+  TCP_STATS_INC(tcp.recv);
+  MIB2_STATS_INC(mib2.tcpinsegs);
+
+  tcphdr = (struct tcp_hdr *)p->payload;
+ 8019dd0:	687b      	ldr	r3, [r7, #4]
+ 8019dd2:	685b      	ldr	r3, [r3, #4]
+ 8019dd4:	4a9a      	ldr	r2, [pc, #616]	; (801a040 <tcp_input+0x28c>)
+ 8019dd6:	6013      	str	r3, [r2, #0]
+#if TCP_INPUT_DEBUG
+  tcp_debug_print(tcphdr);
+#endif
+
+  /* Check that TCP header fits in payload */
+  if (p->len < TCP_HLEN) {
+ 8019dd8:	687b      	ldr	r3, [r7, #4]
+ 8019dda:	895b      	ldrh	r3, [r3, #10]
+ 8019ddc:	2b13      	cmp	r3, #19
+ 8019dde:	f240 83d1 	bls.w	801a584 <tcp_input+0x7d0>
+    TCP_STATS_INC(tcp.lenerr);
+    goto dropped;
+  }
+
+  /* Don't even process incoming broadcasts/multicasts. */
+  if (ip_addr_isbroadcast(ip_current_dest_addr(), ip_current_netif()) ||
+ 8019de2:	4b98      	ldr	r3, [pc, #608]	; (801a044 <tcp_input+0x290>)
+ 8019de4:	695b      	ldr	r3, [r3, #20]
+ 8019de6:	4a97      	ldr	r2, [pc, #604]	; (801a044 <tcp_input+0x290>)
+ 8019de8:	6812      	ldr	r2, [r2, #0]
+ 8019dea:	4611      	mov	r1, r2
+ 8019dec:	4618      	mov	r0, r3
+ 8019dee:	f006 fb17 	bl	8020420 <ip4_addr_isbroadcast_u32>
+ 8019df2:	4603      	mov	r3, r0
+ 8019df4:	2b00      	cmp	r3, #0
+ 8019df6:	f040 83c7 	bne.w	801a588 <tcp_input+0x7d4>
+      ip_addr_ismulticast(ip_current_dest_addr())) {
+ 8019dfa:	4b92      	ldr	r3, [pc, #584]	; (801a044 <tcp_input+0x290>)
+ 8019dfc:	695b      	ldr	r3, [r3, #20]
+ 8019dfe:	f003 03f0 	and.w	r3, r3, #240	; 0xf0
+  if (ip_addr_isbroadcast(ip_current_dest_addr(), ip_current_netif()) ||
+ 8019e02:	2be0      	cmp	r3, #224	; 0xe0
+ 8019e04:	f000 83c0 	beq.w	801a588 <tcp_input+0x7d4>
+    }
+  }
+#endif /* CHECKSUM_CHECK_TCP */
+
+  /* sanity-check header length */
+  hdrlen_bytes = TCPH_HDRLEN_BYTES(tcphdr);
+ 8019e08:	4b8d      	ldr	r3, [pc, #564]	; (801a040 <tcp_input+0x28c>)
+ 8019e0a:	681b      	ldr	r3, [r3, #0]
+ 8019e0c:	899b      	ldrh	r3, [r3, #12]
+ 8019e0e:	b29b      	uxth	r3, r3
+ 8019e10:	4618      	mov	r0, r3
+ 8019e12:	f7fc f895 	bl	8015f40 <lwip_htons>
+ 8019e16:	4603      	mov	r3, r0
+ 8019e18:	0b1b      	lsrs	r3, r3, #12
+ 8019e1a:	b29b      	uxth	r3, r3
+ 8019e1c:	b2db      	uxtb	r3, r3
+ 8019e1e:	009b      	lsls	r3, r3, #2
+ 8019e20:	74bb      	strb	r3, [r7, #18]
+  if ((hdrlen_bytes < TCP_HLEN) || (hdrlen_bytes > p->tot_len)) {
+ 8019e22:	7cbb      	ldrb	r3, [r7, #18]
+ 8019e24:	2b13      	cmp	r3, #19
+ 8019e26:	f240 83b1 	bls.w	801a58c <tcp_input+0x7d8>
+ 8019e2a:	7cbb      	ldrb	r3, [r7, #18]
+ 8019e2c:	b29a      	uxth	r2, r3
+ 8019e2e:	687b      	ldr	r3, [r7, #4]
+ 8019e30:	891b      	ldrh	r3, [r3, #8]
+ 8019e32:	429a      	cmp	r2, r3
+ 8019e34:	f200 83aa 	bhi.w	801a58c <tcp_input+0x7d8>
+    goto dropped;
+  }
+
+  /* Move the payload pointer in the pbuf so that it points to the
+     TCP data instead of the TCP header. */
+  tcphdr_optlen = (u16_t)(hdrlen_bytes - TCP_HLEN);
+ 8019e38:	7cbb      	ldrb	r3, [r7, #18]
+ 8019e3a:	b29b      	uxth	r3, r3
+ 8019e3c:	3b14      	subs	r3, #20
+ 8019e3e:	b29a      	uxth	r2, r3
+ 8019e40:	4b81      	ldr	r3, [pc, #516]	; (801a048 <tcp_input+0x294>)
+ 8019e42:	801a      	strh	r2, [r3, #0]
+  tcphdr_opt2 = NULL;
+ 8019e44:	4b81      	ldr	r3, [pc, #516]	; (801a04c <tcp_input+0x298>)
+ 8019e46:	2200      	movs	r2, #0
+ 8019e48:	601a      	str	r2, [r3, #0]
+  if (p->len >= hdrlen_bytes) {
+ 8019e4a:	687b      	ldr	r3, [r7, #4]
+ 8019e4c:	895a      	ldrh	r2, [r3, #10]
+ 8019e4e:	7cbb      	ldrb	r3, [r7, #18]
+ 8019e50:	b29b      	uxth	r3, r3
+ 8019e52:	429a      	cmp	r2, r3
+ 8019e54:	d309      	bcc.n	8019e6a <tcp_input+0xb6>
+    /* all options are in the first pbuf */
+    tcphdr_opt1len = tcphdr_optlen;
+ 8019e56:	4b7c      	ldr	r3, [pc, #496]	; (801a048 <tcp_input+0x294>)
+ 8019e58:	881a      	ldrh	r2, [r3, #0]
+ 8019e5a:	4b7d      	ldr	r3, [pc, #500]	; (801a050 <tcp_input+0x29c>)
+ 8019e5c:	801a      	strh	r2, [r3, #0]
+    pbuf_remove_header(p, hdrlen_bytes); /* cannot fail */
+ 8019e5e:	7cbb      	ldrb	r3, [r7, #18]
+ 8019e60:	4619      	mov	r1, r3
+ 8019e62:	6878      	ldr	r0, [r7, #4]
+ 8019e64:	f7fd fdc2 	bl	80179ec <pbuf_remove_header>
+ 8019e68:	e04e      	b.n	8019f08 <tcp_input+0x154>
+  } else {
+    u16_t opt2len;
+    /* TCP header fits into first pbuf, options don't - data is in the next pbuf */
+    /* there must be a next pbuf, due to hdrlen_bytes sanity check above */
+    LWIP_ASSERT("p->next != NULL", p->next != NULL);
+ 8019e6a:	687b      	ldr	r3, [r7, #4]
+ 8019e6c:	681b      	ldr	r3, [r3, #0]
+ 8019e6e:	2b00      	cmp	r3, #0
+ 8019e70:	d105      	bne.n	8019e7e <tcp_input+0xca>
+ 8019e72:	4b70      	ldr	r3, [pc, #448]	; (801a034 <tcp_input+0x280>)
+ 8019e74:	22c2      	movs	r2, #194	; 0xc2
+ 8019e76:	4977      	ldr	r1, [pc, #476]	; (801a054 <tcp_input+0x2a0>)
+ 8019e78:	4870      	ldr	r0, [pc, #448]	; (801a03c <tcp_input+0x288>)
+ 8019e7a:	f007 fd85 	bl	8021988 <iprintf>
+
+    /* advance over the TCP header (cannot fail) */
+    pbuf_remove_header(p, TCP_HLEN);
+ 8019e7e:	2114      	movs	r1, #20
+ 8019e80:	6878      	ldr	r0, [r7, #4]
+ 8019e82:	f7fd fdb3 	bl	80179ec <pbuf_remove_header>
+
+    /* determine how long the first and second parts of the options are */
+    tcphdr_opt1len = p->len;
+ 8019e86:	687b      	ldr	r3, [r7, #4]
+ 8019e88:	895a      	ldrh	r2, [r3, #10]
+ 8019e8a:	4b71      	ldr	r3, [pc, #452]	; (801a050 <tcp_input+0x29c>)
+ 8019e8c:	801a      	strh	r2, [r3, #0]
+    opt2len = (u16_t)(tcphdr_optlen - tcphdr_opt1len);
+ 8019e8e:	4b6e      	ldr	r3, [pc, #440]	; (801a048 <tcp_input+0x294>)
+ 8019e90:	881a      	ldrh	r2, [r3, #0]
+ 8019e92:	4b6f      	ldr	r3, [pc, #444]	; (801a050 <tcp_input+0x29c>)
+ 8019e94:	881b      	ldrh	r3, [r3, #0]
+ 8019e96:	1ad3      	subs	r3, r2, r3
+ 8019e98:	823b      	strh	r3, [r7, #16]
+
+    /* options continue in the next pbuf: set p to zero length and hide the
+        options in the next pbuf (adjusting p->tot_len) */
+    pbuf_remove_header(p, tcphdr_opt1len);
+ 8019e9a:	4b6d      	ldr	r3, [pc, #436]	; (801a050 <tcp_input+0x29c>)
+ 8019e9c:	881b      	ldrh	r3, [r3, #0]
+ 8019e9e:	4619      	mov	r1, r3
+ 8019ea0:	6878      	ldr	r0, [r7, #4]
+ 8019ea2:	f7fd fda3 	bl	80179ec <pbuf_remove_header>
+
+    /* check that the options fit in the second pbuf */
+    if (opt2len > p->next->len) {
+ 8019ea6:	687b      	ldr	r3, [r7, #4]
+ 8019ea8:	681b      	ldr	r3, [r3, #0]
+ 8019eaa:	895b      	ldrh	r3, [r3, #10]
+ 8019eac:	8a3a      	ldrh	r2, [r7, #16]
+ 8019eae:	429a      	cmp	r2, r3
+ 8019eb0:	f200 836e 	bhi.w	801a590 <tcp_input+0x7dc>
+      TCP_STATS_INC(tcp.lenerr);
+      goto dropped;
+    }
+
+    /* remember the pointer to the second part of the options */
+    tcphdr_opt2 = (u8_t *)p->next->payload;
+ 8019eb4:	687b      	ldr	r3, [r7, #4]
+ 8019eb6:	681b      	ldr	r3, [r3, #0]
+ 8019eb8:	685b      	ldr	r3, [r3, #4]
+ 8019eba:	4a64      	ldr	r2, [pc, #400]	; (801a04c <tcp_input+0x298>)
+ 8019ebc:	6013      	str	r3, [r2, #0]
+
+    /* advance p->next to point after the options, and manually
+        adjust p->tot_len to keep it consistent with the changed p->next */
+    pbuf_remove_header(p->next, opt2len);
+ 8019ebe:	687b      	ldr	r3, [r7, #4]
+ 8019ec0:	681b      	ldr	r3, [r3, #0]
+ 8019ec2:	8a3a      	ldrh	r2, [r7, #16]
+ 8019ec4:	4611      	mov	r1, r2
+ 8019ec6:	4618      	mov	r0, r3
+ 8019ec8:	f7fd fd90 	bl	80179ec <pbuf_remove_header>
+    p->tot_len = (u16_t)(p->tot_len - opt2len);
+ 8019ecc:	687b      	ldr	r3, [r7, #4]
+ 8019ece:	891a      	ldrh	r2, [r3, #8]
+ 8019ed0:	8a3b      	ldrh	r3, [r7, #16]
+ 8019ed2:	1ad3      	subs	r3, r2, r3
+ 8019ed4:	b29a      	uxth	r2, r3
+ 8019ed6:	687b      	ldr	r3, [r7, #4]
+ 8019ed8:	811a      	strh	r2, [r3, #8]
+
+    LWIP_ASSERT("p->len == 0", p->len == 0);
+ 8019eda:	687b      	ldr	r3, [r7, #4]
+ 8019edc:	895b      	ldrh	r3, [r3, #10]
+ 8019ede:	2b00      	cmp	r3, #0
+ 8019ee0:	d005      	beq.n	8019eee <tcp_input+0x13a>
+ 8019ee2:	4b54      	ldr	r3, [pc, #336]	; (801a034 <tcp_input+0x280>)
+ 8019ee4:	22df      	movs	r2, #223	; 0xdf
+ 8019ee6:	495c      	ldr	r1, [pc, #368]	; (801a058 <tcp_input+0x2a4>)
+ 8019ee8:	4854      	ldr	r0, [pc, #336]	; (801a03c <tcp_input+0x288>)
+ 8019eea:	f007 fd4d 	bl	8021988 <iprintf>
+    LWIP_ASSERT("p->tot_len == p->next->tot_len", p->tot_len == p->next->tot_len);
+ 8019eee:	687b      	ldr	r3, [r7, #4]
+ 8019ef0:	891a      	ldrh	r2, [r3, #8]
+ 8019ef2:	687b      	ldr	r3, [r7, #4]
+ 8019ef4:	681b      	ldr	r3, [r3, #0]
+ 8019ef6:	891b      	ldrh	r3, [r3, #8]
+ 8019ef8:	429a      	cmp	r2, r3
+ 8019efa:	d005      	beq.n	8019f08 <tcp_input+0x154>
+ 8019efc:	4b4d      	ldr	r3, [pc, #308]	; (801a034 <tcp_input+0x280>)
+ 8019efe:	22e0      	movs	r2, #224	; 0xe0
+ 8019f00:	4956      	ldr	r1, [pc, #344]	; (801a05c <tcp_input+0x2a8>)
+ 8019f02:	484e      	ldr	r0, [pc, #312]	; (801a03c <tcp_input+0x288>)
+ 8019f04:	f007 fd40 	bl	8021988 <iprintf>
+  }
+
+  /* Convert fields in TCP header to host byte order. */
+  tcphdr->src = lwip_ntohs(tcphdr->src);
+ 8019f08:	4b4d      	ldr	r3, [pc, #308]	; (801a040 <tcp_input+0x28c>)
+ 8019f0a:	681b      	ldr	r3, [r3, #0]
+ 8019f0c:	881b      	ldrh	r3, [r3, #0]
+ 8019f0e:	b29b      	uxth	r3, r3
+ 8019f10:	4a4b      	ldr	r2, [pc, #300]	; (801a040 <tcp_input+0x28c>)
+ 8019f12:	6814      	ldr	r4, [r2, #0]
+ 8019f14:	4618      	mov	r0, r3
+ 8019f16:	f7fc f813 	bl	8015f40 <lwip_htons>
+ 8019f1a:	4603      	mov	r3, r0
+ 8019f1c:	8023      	strh	r3, [r4, #0]
+  tcphdr->dest = lwip_ntohs(tcphdr->dest);
+ 8019f1e:	4b48      	ldr	r3, [pc, #288]	; (801a040 <tcp_input+0x28c>)
+ 8019f20:	681b      	ldr	r3, [r3, #0]
+ 8019f22:	885b      	ldrh	r3, [r3, #2]
+ 8019f24:	b29b      	uxth	r3, r3
+ 8019f26:	4a46      	ldr	r2, [pc, #280]	; (801a040 <tcp_input+0x28c>)
+ 8019f28:	6814      	ldr	r4, [r2, #0]
+ 8019f2a:	4618      	mov	r0, r3
+ 8019f2c:	f7fc f808 	bl	8015f40 <lwip_htons>
+ 8019f30:	4603      	mov	r3, r0
+ 8019f32:	8063      	strh	r3, [r4, #2]
+  seqno = tcphdr->seqno = lwip_ntohl(tcphdr->seqno);
+ 8019f34:	4b42      	ldr	r3, [pc, #264]	; (801a040 <tcp_input+0x28c>)
+ 8019f36:	681b      	ldr	r3, [r3, #0]
+ 8019f38:	685b      	ldr	r3, [r3, #4]
+ 8019f3a:	4a41      	ldr	r2, [pc, #260]	; (801a040 <tcp_input+0x28c>)
+ 8019f3c:	6814      	ldr	r4, [r2, #0]
+ 8019f3e:	4618      	mov	r0, r3
+ 8019f40:	f7fc f813 	bl	8015f6a <lwip_htonl>
+ 8019f44:	4603      	mov	r3, r0
+ 8019f46:	6063      	str	r3, [r4, #4]
+ 8019f48:	6863      	ldr	r3, [r4, #4]
+ 8019f4a:	4a45      	ldr	r2, [pc, #276]	; (801a060 <tcp_input+0x2ac>)
+ 8019f4c:	6013      	str	r3, [r2, #0]
+  ackno = tcphdr->ackno = lwip_ntohl(tcphdr->ackno);
+ 8019f4e:	4b3c      	ldr	r3, [pc, #240]	; (801a040 <tcp_input+0x28c>)
+ 8019f50:	681b      	ldr	r3, [r3, #0]
+ 8019f52:	689b      	ldr	r3, [r3, #8]
+ 8019f54:	4a3a      	ldr	r2, [pc, #232]	; (801a040 <tcp_input+0x28c>)
+ 8019f56:	6814      	ldr	r4, [r2, #0]
+ 8019f58:	4618      	mov	r0, r3
+ 8019f5a:	f7fc f806 	bl	8015f6a <lwip_htonl>
+ 8019f5e:	4603      	mov	r3, r0
+ 8019f60:	60a3      	str	r3, [r4, #8]
+ 8019f62:	68a3      	ldr	r3, [r4, #8]
+ 8019f64:	4a3f      	ldr	r2, [pc, #252]	; (801a064 <tcp_input+0x2b0>)
+ 8019f66:	6013      	str	r3, [r2, #0]
+  tcphdr->wnd = lwip_ntohs(tcphdr->wnd);
+ 8019f68:	4b35      	ldr	r3, [pc, #212]	; (801a040 <tcp_input+0x28c>)
+ 8019f6a:	681b      	ldr	r3, [r3, #0]
+ 8019f6c:	89db      	ldrh	r3, [r3, #14]
+ 8019f6e:	b29b      	uxth	r3, r3
+ 8019f70:	4a33      	ldr	r2, [pc, #204]	; (801a040 <tcp_input+0x28c>)
+ 8019f72:	6814      	ldr	r4, [r2, #0]
+ 8019f74:	4618      	mov	r0, r3
+ 8019f76:	f7fb ffe3 	bl	8015f40 <lwip_htons>
+ 8019f7a:	4603      	mov	r3, r0
+ 8019f7c:	81e3      	strh	r3, [r4, #14]
+
+  flags = TCPH_FLAGS(tcphdr);
+ 8019f7e:	4b30      	ldr	r3, [pc, #192]	; (801a040 <tcp_input+0x28c>)
+ 8019f80:	681b      	ldr	r3, [r3, #0]
+ 8019f82:	899b      	ldrh	r3, [r3, #12]
+ 8019f84:	b29b      	uxth	r3, r3
+ 8019f86:	4618      	mov	r0, r3
+ 8019f88:	f7fb ffda 	bl	8015f40 <lwip_htons>
+ 8019f8c:	4603      	mov	r3, r0
+ 8019f8e:	b2db      	uxtb	r3, r3
+ 8019f90:	f003 033f 	and.w	r3, r3, #63	; 0x3f
+ 8019f94:	b2da      	uxtb	r2, r3
+ 8019f96:	4b34      	ldr	r3, [pc, #208]	; (801a068 <tcp_input+0x2b4>)
+ 8019f98:	701a      	strb	r2, [r3, #0]
+  tcplen = p->tot_len;
+ 8019f9a:	687b      	ldr	r3, [r7, #4]
+ 8019f9c:	891a      	ldrh	r2, [r3, #8]
+ 8019f9e:	4b33      	ldr	r3, [pc, #204]	; (801a06c <tcp_input+0x2b8>)
+ 8019fa0:	801a      	strh	r2, [r3, #0]
+  if (flags & (TCP_FIN | TCP_SYN)) {
+ 8019fa2:	4b31      	ldr	r3, [pc, #196]	; (801a068 <tcp_input+0x2b4>)
+ 8019fa4:	781b      	ldrb	r3, [r3, #0]
+ 8019fa6:	f003 0303 	and.w	r3, r3, #3
+ 8019faa:	2b00      	cmp	r3, #0
+ 8019fac:	d00c      	beq.n	8019fc8 <tcp_input+0x214>
+    tcplen++;
+ 8019fae:	4b2f      	ldr	r3, [pc, #188]	; (801a06c <tcp_input+0x2b8>)
+ 8019fb0:	881b      	ldrh	r3, [r3, #0]
+ 8019fb2:	3301      	adds	r3, #1
+ 8019fb4:	b29a      	uxth	r2, r3
+ 8019fb6:	4b2d      	ldr	r3, [pc, #180]	; (801a06c <tcp_input+0x2b8>)
+ 8019fb8:	801a      	strh	r2, [r3, #0]
+    if (tcplen < p->tot_len) {
+ 8019fba:	687b      	ldr	r3, [r7, #4]
+ 8019fbc:	891a      	ldrh	r2, [r3, #8]
+ 8019fbe:	4b2b      	ldr	r3, [pc, #172]	; (801a06c <tcp_input+0x2b8>)
+ 8019fc0:	881b      	ldrh	r3, [r3, #0]
+ 8019fc2:	429a      	cmp	r2, r3
+ 8019fc4:	f200 82e6 	bhi.w	801a594 <tcp_input+0x7e0>
+    }
+  }
+
+  /* Demultiplex an incoming segment. First, we check if it is destined
+     for an active connection. */
+  prev = NULL;
+ 8019fc8:	2300      	movs	r3, #0
+ 8019fca:	61fb      	str	r3, [r7, #28]
+
+  for (pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) {
+ 8019fcc:	4b28      	ldr	r3, [pc, #160]	; (801a070 <tcp_input+0x2bc>)
+ 8019fce:	681b      	ldr	r3, [r3, #0]
+ 8019fd0:	61bb      	str	r3, [r7, #24]
+ 8019fd2:	e09d      	b.n	801a110 <tcp_input+0x35c>
+    LWIP_ASSERT("tcp_input: active pcb->state != CLOSED", pcb->state != CLOSED);
+ 8019fd4:	69bb      	ldr	r3, [r7, #24]
+ 8019fd6:	7d1b      	ldrb	r3, [r3, #20]
+ 8019fd8:	2b00      	cmp	r3, #0
+ 8019fda:	d105      	bne.n	8019fe8 <tcp_input+0x234>
+ 8019fdc:	4b15      	ldr	r3, [pc, #84]	; (801a034 <tcp_input+0x280>)
+ 8019fde:	22fb      	movs	r2, #251	; 0xfb
+ 8019fe0:	4924      	ldr	r1, [pc, #144]	; (801a074 <tcp_input+0x2c0>)
+ 8019fe2:	4816      	ldr	r0, [pc, #88]	; (801a03c <tcp_input+0x288>)
+ 8019fe4:	f007 fcd0 	bl	8021988 <iprintf>
+    LWIP_ASSERT("tcp_input: active pcb->state != TIME-WAIT", pcb->state != TIME_WAIT);
+ 8019fe8:	69bb      	ldr	r3, [r7, #24]
+ 8019fea:	7d1b      	ldrb	r3, [r3, #20]
+ 8019fec:	2b0a      	cmp	r3, #10
+ 8019fee:	d105      	bne.n	8019ffc <tcp_input+0x248>
+ 8019ff0:	4b10      	ldr	r3, [pc, #64]	; (801a034 <tcp_input+0x280>)
+ 8019ff2:	22fc      	movs	r2, #252	; 0xfc
+ 8019ff4:	4920      	ldr	r1, [pc, #128]	; (801a078 <tcp_input+0x2c4>)
+ 8019ff6:	4811      	ldr	r0, [pc, #68]	; (801a03c <tcp_input+0x288>)
+ 8019ff8:	f007 fcc6 	bl	8021988 <iprintf>
+    LWIP_ASSERT("tcp_input: active pcb->state != LISTEN", pcb->state != LISTEN);
+ 8019ffc:	69bb      	ldr	r3, [r7, #24]
+ 8019ffe:	7d1b      	ldrb	r3, [r3, #20]
+ 801a000:	2b01      	cmp	r3, #1
+ 801a002:	d105      	bne.n	801a010 <tcp_input+0x25c>
+ 801a004:	4b0b      	ldr	r3, [pc, #44]	; (801a034 <tcp_input+0x280>)
+ 801a006:	22fd      	movs	r2, #253	; 0xfd
+ 801a008:	491c      	ldr	r1, [pc, #112]	; (801a07c <tcp_input+0x2c8>)
+ 801a00a:	480c      	ldr	r0, [pc, #48]	; (801a03c <tcp_input+0x288>)
+ 801a00c:	f007 fcbc 	bl	8021988 <iprintf>
+
+    /* check if PCB is bound to specific netif */
+    if ((pcb->netif_idx != NETIF_NO_INDEX) &&
+ 801a010:	69bb      	ldr	r3, [r7, #24]
+ 801a012:	7a1b      	ldrb	r3, [r3, #8]
+ 801a014:	2b00      	cmp	r3, #0
+ 801a016:	d033      	beq.n	801a080 <tcp_input+0x2cc>
+        (pcb->netif_idx != netif_get_index(ip_data.current_input_netif))) {
+ 801a018:	69bb      	ldr	r3, [r7, #24]
+ 801a01a:	7a1a      	ldrb	r2, [r3, #8]
+ 801a01c:	4b09      	ldr	r3, [pc, #36]	; (801a044 <tcp_input+0x290>)
+ 801a01e:	685b      	ldr	r3, [r3, #4]
+ 801a020:	f893 3030 	ldrb.w	r3, [r3, #48]	; 0x30
+ 801a024:	3301      	adds	r3, #1
+ 801a026:	b2db      	uxtb	r3, r3
+    if ((pcb->netif_idx != NETIF_NO_INDEX) &&
+ 801a028:	429a      	cmp	r2, r3
+ 801a02a:	d029      	beq.n	801a080 <tcp_input+0x2cc>
+      prev = pcb;
+ 801a02c:	69bb      	ldr	r3, [r7, #24]
+ 801a02e:	61fb      	str	r3, [r7, #28]
+      continue;
+ 801a030:	e06b      	b.n	801a10a <tcp_input+0x356>
+ 801a032:	bf00      	nop
+ 801a034:	08025338 	.word	0x08025338
+ 801a038:	0802536c 	.word	0x0802536c
+ 801a03c:	08025384 	.word	0x08025384
+ 801a040:	2401a4ac 	.word	0x2401a4ac
+ 801a044:	24013980 	.word	0x24013980
+ 801a048:	2401a4b0 	.word	0x2401a4b0
+ 801a04c:	2401a4b4 	.word	0x2401a4b4
+ 801a050:	2401a4b2 	.word	0x2401a4b2
+ 801a054:	080253ac 	.word	0x080253ac
+ 801a058:	080253bc 	.word	0x080253bc
+ 801a05c:	080253c8 	.word	0x080253c8
+ 801a060:	2401a4bc 	.word	0x2401a4bc
+ 801a064:	2401a4c0 	.word	0x2401a4c0
+ 801a068:	2401a4c8 	.word	0x2401a4c8
+ 801a06c:	2401a4c6 	.word	0x2401a4c6
+ 801a070:	2401a48c 	.word	0x2401a48c
+ 801a074:	080253e8 	.word	0x080253e8
+ 801a078:	08025410 	.word	0x08025410
+ 801a07c:	0802543c 	.word	0x0802543c
+    }
+
+    if (pcb->remote_port == tcphdr->src &&
+ 801a080:	69bb      	ldr	r3, [r7, #24]
+ 801a082:	8b1a      	ldrh	r2, [r3, #24]
+ 801a084:	4b72      	ldr	r3, [pc, #456]	; (801a250 <tcp_input+0x49c>)
+ 801a086:	681b      	ldr	r3, [r3, #0]
+ 801a088:	881b      	ldrh	r3, [r3, #0]
+ 801a08a:	b29b      	uxth	r3, r3
+ 801a08c:	429a      	cmp	r2, r3
+ 801a08e:	d13a      	bne.n	801a106 <tcp_input+0x352>
+        pcb->local_port == tcphdr->dest &&
+ 801a090:	69bb      	ldr	r3, [r7, #24]
+ 801a092:	8ada      	ldrh	r2, [r3, #22]
+ 801a094:	4b6e      	ldr	r3, [pc, #440]	; (801a250 <tcp_input+0x49c>)
+ 801a096:	681b      	ldr	r3, [r3, #0]
+ 801a098:	885b      	ldrh	r3, [r3, #2]
+ 801a09a:	b29b      	uxth	r3, r3
+    if (pcb->remote_port == tcphdr->src &&
+ 801a09c:	429a      	cmp	r2, r3
+ 801a09e:	d132      	bne.n	801a106 <tcp_input+0x352>
+        ip_addr_cmp(&pcb->remote_ip, ip_current_src_addr()) &&
+ 801a0a0:	69bb      	ldr	r3, [r7, #24]
+ 801a0a2:	685a      	ldr	r2, [r3, #4]
+ 801a0a4:	4b6b      	ldr	r3, [pc, #428]	; (801a254 <tcp_input+0x4a0>)
+ 801a0a6:	691b      	ldr	r3, [r3, #16]
+        pcb->local_port == tcphdr->dest &&
+ 801a0a8:	429a      	cmp	r2, r3
+ 801a0aa:	d12c      	bne.n	801a106 <tcp_input+0x352>
+        ip_addr_cmp(&pcb->local_ip, ip_current_dest_addr())) {
+ 801a0ac:	69bb      	ldr	r3, [r7, #24]
+ 801a0ae:	681a      	ldr	r2, [r3, #0]
+ 801a0b0:	4b68      	ldr	r3, [pc, #416]	; (801a254 <tcp_input+0x4a0>)
+ 801a0b2:	695b      	ldr	r3, [r3, #20]
+        ip_addr_cmp(&pcb->remote_ip, ip_current_src_addr()) &&
+ 801a0b4:	429a      	cmp	r2, r3
+ 801a0b6:	d126      	bne.n	801a106 <tcp_input+0x352>
+      /* Move this PCB to the front of the list so that subsequent
+         lookups will be faster (we exploit locality in TCP segment
+         arrivals). */
+      LWIP_ASSERT("tcp_input: pcb->next != pcb (before cache)", pcb->next != pcb);
+ 801a0b8:	69bb      	ldr	r3, [r7, #24]
+ 801a0ba:	68db      	ldr	r3, [r3, #12]
+ 801a0bc:	69ba      	ldr	r2, [r7, #24]
+ 801a0be:	429a      	cmp	r2, r3
+ 801a0c0:	d106      	bne.n	801a0d0 <tcp_input+0x31c>
+ 801a0c2:	4b65      	ldr	r3, [pc, #404]	; (801a258 <tcp_input+0x4a4>)
+ 801a0c4:	f240 120d 	movw	r2, #269	; 0x10d
+ 801a0c8:	4964      	ldr	r1, [pc, #400]	; (801a25c <tcp_input+0x4a8>)
+ 801a0ca:	4865      	ldr	r0, [pc, #404]	; (801a260 <tcp_input+0x4ac>)
+ 801a0cc:	f007 fc5c 	bl	8021988 <iprintf>
+      if (prev != NULL) {
+ 801a0d0:	69fb      	ldr	r3, [r7, #28]
+ 801a0d2:	2b00      	cmp	r3, #0
+ 801a0d4:	d00a      	beq.n	801a0ec <tcp_input+0x338>
+        prev->next = pcb->next;
+ 801a0d6:	69bb      	ldr	r3, [r7, #24]
+ 801a0d8:	68da      	ldr	r2, [r3, #12]
+ 801a0da:	69fb      	ldr	r3, [r7, #28]
+ 801a0dc:	60da      	str	r2, [r3, #12]
+        pcb->next = tcp_active_pcbs;
+ 801a0de:	4b61      	ldr	r3, [pc, #388]	; (801a264 <tcp_input+0x4b0>)
+ 801a0e0:	681a      	ldr	r2, [r3, #0]
+ 801a0e2:	69bb      	ldr	r3, [r7, #24]
+ 801a0e4:	60da      	str	r2, [r3, #12]
+        tcp_active_pcbs = pcb;
+ 801a0e6:	4a5f      	ldr	r2, [pc, #380]	; (801a264 <tcp_input+0x4b0>)
+ 801a0e8:	69bb      	ldr	r3, [r7, #24]
+ 801a0ea:	6013      	str	r3, [r2, #0]
+      } else {
+        TCP_STATS_INC(tcp.cachehit);
+      }
+      LWIP_ASSERT("tcp_input: pcb->next != pcb (after cache)", pcb->next != pcb);
+ 801a0ec:	69bb      	ldr	r3, [r7, #24]
+ 801a0ee:	68db      	ldr	r3, [r3, #12]
+ 801a0f0:	69ba      	ldr	r2, [r7, #24]
+ 801a0f2:	429a      	cmp	r2, r3
+ 801a0f4:	d111      	bne.n	801a11a <tcp_input+0x366>
+ 801a0f6:	4b58      	ldr	r3, [pc, #352]	; (801a258 <tcp_input+0x4a4>)
+ 801a0f8:	f240 1215 	movw	r2, #277	; 0x115
+ 801a0fc:	495a      	ldr	r1, [pc, #360]	; (801a268 <tcp_input+0x4b4>)
+ 801a0fe:	4858      	ldr	r0, [pc, #352]	; (801a260 <tcp_input+0x4ac>)
+ 801a100:	f007 fc42 	bl	8021988 <iprintf>
+      break;
+ 801a104:	e009      	b.n	801a11a <tcp_input+0x366>
+    }
+    prev = pcb;
+ 801a106:	69bb      	ldr	r3, [r7, #24]
+ 801a108:	61fb      	str	r3, [r7, #28]
+  for (pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) {
+ 801a10a:	69bb      	ldr	r3, [r7, #24]
+ 801a10c:	68db      	ldr	r3, [r3, #12]
+ 801a10e:	61bb      	str	r3, [r7, #24]
+ 801a110:	69bb      	ldr	r3, [r7, #24]
+ 801a112:	2b00      	cmp	r3, #0
+ 801a114:	f47f af5e 	bne.w	8019fd4 <tcp_input+0x220>
+ 801a118:	e000      	b.n	801a11c <tcp_input+0x368>
+      break;
+ 801a11a:	bf00      	nop
+  }
+
+  if (pcb == NULL) {
+ 801a11c:	69bb      	ldr	r3, [r7, #24]
+ 801a11e:	2b00      	cmp	r3, #0
+ 801a120:	f040 80aa 	bne.w	801a278 <tcp_input+0x4c4>
+    /* If it did not go to an active connection, we check the connections
+       in the TIME-WAIT state. */
+    for (pcb = tcp_tw_pcbs; pcb != NULL; pcb = pcb->next) {
+ 801a124:	4b51      	ldr	r3, [pc, #324]	; (801a26c <tcp_input+0x4b8>)
+ 801a126:	681b      	ldr	r3, [r3, #0]
+ 801a128:	61bb      	str	r3, [r7, #24]
+ 801a12a:	e03f      	b.n	801a1ac <tcp_input+0x3f8>
+      LWIP_ASSERT("tcp_input: TIME-WAIT pcb->state == TIME-WAIT", pcb->state == TIME_WAIT);
+ 801a12c:	69bb      	ldr	r3, [r7, #24]
+ 801a12e:	7d1b      	ldrb	r3, [r3, #20]
+ 801a130:	2b0a      	cmp	r3, #10
+ 801a132:	d006      	beq.n	801a142 <tcp_input+0x38e>
+ 801a134:	4b48      	ldr	r3, [pc, #288]	; (801a258 <tcp_input+0x4a4>)
+ 801a136:	f240 121f 	movw	r2, #287	; 0x11f
+ 801a13a:	494d      	ldr	r1, [pc, #308]	; (801a270 <tcp_input+0x4bc>)
+ 801a13c:	4848      	ldr	r0, [pc, #288]	; (801a260 <tcp_input+0x4ac>)
+ 801a13e:	f007 fc23 	bl	8021988 <iprintf>
+
+      /* check if PCB is bound to specific netif */
+      if ((pcb->netif_idx != NETIF_NO_INDEX) &&
+ 801a142:	69bb      	ldr	r3, [r7, #24]
+ 801a144:	7a1b      	ldrb	r3, [r3, #8]
+ 801a146:	2b00      	cmp	r3, #0
+ 801a148:	d009      	beq.n	801a15e <tcp_input+0x3aa>
+          (pcb->netif_idx != netif_get_index(ip_data.current_input_netif))) {
+ 801a14a:	69bb      	ldr	r3, [r7, #24]
+ 801a14c:	7a1a      	ldrb	r2, [r3, #8]
+ 801a14e:	4b41      	ldr	r3, [pc, #260]	; (801a254 <tcp_input+0x4a0>)
+ 801a150:	685b      	ldr	r3, [r3, #4]
+ 801a152:	f893 3030 	ldrb.w	r3, [r3, #48]	; 0x30
+ 801a156:	3301      	adds	r3, #1
+ 801a158:	b2db      	uxtb	r3, r3
+      if ((pcb->netif_idx != NETIF_NO_INDEX) &&
+ 801a15a:	429a      	cmp	r2, r3
+ 801a15c:	d122      	bne.n	801a1a4 <tcp_input+0x3f0>
+        continue;
+      }
+
+      if (pcb->remote_port == tcphdr->src &&
+ 801a15e:	69bb      	ldr	r3, [r7, #24]
+ 801a160:	8b1a      	ldrh	r2, [r3, #24]
+ 801a162:	4b3b      	ldr	r3, [pc, #236]	; (801a250 <tcp_input+0x49c>)
+ 801a164:	681b      	ldr	r3, [r3, #0]
+ 801a166:	881b      	ldrh	r3, [r3, #0]
+ 801a168:	b29b      	uxth	r3, r3
+ 801a16a:	429a      	cmp	r2, r3
+ 801a16c:	d11b      	bne.n	801a1a6 <tcp_input+0x3f2>
+          pcb->local_port == tcphdr->dest &&
+ 801a16e:	69bb      	ldr	r3, [r7, #24]
+ 801a170:	8ada      	ldrh	r2, [r3, #22]
+ 801a172:	4b37      	ldr	r3, [pc, #220]	; (801a250 <tcp_input+0x49c>)
+ 801a174:	681b      	ldr	r3, [r3, #0]
+ 801a176:	885b      	ldrh	r3, [r3, #2]
+ 801a178:	b29b      	uxth	r3, r3
+      if (pcb->remote_port == tcphdr->src &&
+ 801a17a:	429a      	cmp	r2, r3
+ 801a17c:	d113      	bne.n	801a1a6 <tcp_input+0x3f2>
+          ip_addr_cmp(&pcb->remote_ip, ip_current_src_addr()) &&
+ 801a17e:	69bb      	ldr	r3, [r7, #24]
+ 801a180:	685a      	ldr	r2, [r3, #4]
+ 801a182:	4b34      	ldr	r3, [pc, #208]	; (801a254 <tcp_input+0x4a0>)
+ 801a184:	691b      	ldr	r3, [r3, #16]
+          pcb->local_port == tcphdr->dest &&
+ 801a186:	429a      	cmp	r2, r3
+ 801a188:	d10d      	bne.n	801a1a6 <tcp_input+0x3f2>
+          ip_addr_cmp(&pcb->local_ip, ip_current_dest_addr())) {
+ 801a18a:	69bb      	ldr	r3, [r7, #24]
+ 801a18c:	681a      	ldr	r2, [r3, #0]
+ 801a18e:	4b31      	ldr	r3, [pc, #196]	; (801a254 <tcp_input+0x4a0>)
+ 801a190:	695b      	ldr	r3, [r3, #20]
+          ip_addr_cmp(&pcb->remote_ip, ip_current_src_addr()) &&
+ 801a192:	429a      	cmp	r2, r3
+ 801a194:	d107      	bne.n	801a1a6 <tcp_input+0x3f2>
+#ifdef LWIP_HOOK_TCP_INPACKET_PCB
+        if (LWIP_HOOK_TCP_INPACKET_PCB(pcb, tcphdr, tcphdr_optlen, tcphdr_opt1len,
+                                       tcphdr_opt2, p) == ERR_OK)
+#endif
+        {
+          tcp_timewait_input(pcb);
+ 801a196:	69b8      	ldr	r0, [r7, #24]
+ 801a198:	f000 fb56 	bl	801a848 <tcp_timewait_input>
+        }
+        pbuf_free(p);
+ 801a19c:	6878      	ldr	r0, [r7, #4]
+ 801a19e:	f7fd fcab 	bl	8017af8 <pbuf_free>
+        return;
+ 801a1a2:	e1fd      	b.n	801a5a0 <tcp_input+0x7ec>
+        continue;
+ 801a1a4:	bf00      	nop
+    for (pcb = tcp_tw_pcbs; pcb != NULL; pcb = pcb->next) {
+ 801a1a6:	69bb      	ldr	r3, [r7, #24]
+ 801a1a8:	68db      	ldr	r3, [r3, #12]
+ 801a1aa:	61bb      	str	r3, [r7, #24]
+ 801a1ac:	69bb      	ldr	r3, [r7, #24]
+ 801a1ae:	2b00      	cmp	r3, #0
+ 801a1b0:	d1bc      	bne.n	801a12c <tcp_input+0x378>
+      }
+    }
+
+    /* Finally, if we still did not get a match, we check all PCBs that
+       are LISTENing for incoming connections. */
+    prev = NULL;
+ 801a1b2:	2300      	movs	r3, #0
+ 801a1b4:	61fb      	str	r3, [r7, #28]
+    for (lpcb = tcp_listen_pcbs.listen_pcbs; lpcb != NULL; lpcb = lpcb->next) {
+ 801a1b6:	4b2f      	ldr	r3, [pc, #188]	; (801a274 <tcp_input+0x4c0>)
+ 801a1b8:	681b      	ldr	r3, [r3, #0]
+ 801a1ba:	617b      	str	r3, [r7, #20]
+ 801a1bc:	e02a      	b.n	801a214 <tcp_input+0x460>
+      /* check if PCB is bound to specific netif */
+      if ((lpcb->netif_idx != NETIF_NO_INDEX) &&
+ 801a1be:	697b      	ldr	r3, [r7, #20]
+ 801a1c0:	7a1b      	ldrb	r3, [r3, #8]
+ 801a1c2:	2b00      	cmp	r3, #0
+ 801a1c4:	d00c      	beq.n	801a1e0 <tcp_input+0x42c>
+          (lpcb->netif_idx != netif_get_index(ip_data.current_input_netif))) {
+ 801a1c6:	697b      	ldr	r3, [r7, #20]
+ 801a1c8:	7a1a      	ldrb	r2, [r3, #8]
+ 801a1ca:	4b22      	ldr	r3, [pc, #136]	; (801a254 <tcp_input+0x4a0>)
+ 801a1cc:	685b      	ldr	r3, [r3, #4]
+ 801a1ce:	f893 3030 	ldrb.w	r3, [r3, #48]	; 0x30
+ 801a1d2:	3301      	adds	r3, #1
+ 801a1d4:	b2db      	uxtb	r3, r3
+      if ((lpcb->netif_idx != NETIF_NO_INDEX) &&
+ 801a1d6:	429a      	cmp	r2, r3
+ 801a1d8:	d002      	beq.n	801a1e0 <tcp_input+0x42c>
+        prev = (struct tcp_pcb *)lpcb;
+ 801a1da:	697b      	ldr	r3, [r7, #20]
+ 801a1dc:	61fb      	str	r3, [r7, #28]
+        continue;
+ 801a1de:	e016      	b.n	801a20e <tcp_input+0x45a>
+      }
+
+      if (lpcb->local_port == tcphdr->dest) {
+ 801a1e0:	697b      	ldr	r3, [r7, #20]
+ 801a1e2:	8ada      	ldrh	r2, [r3, #22]
+ 801a1e4:	4b1a      	ldr	r3, [pc, #104]	; (801a250 <tcp_input+0x49c>)
+ 801a1e6:	681b      	ldr	r3, [r3, #0]
+ 801a1e8:	885b      	ldrh	r3, [r3, #2]
+ 801a1ea:	b29b      	uxth	r3, r3
+ 801a1ec:	429a      	cmp	r2, r3
+ 801a1ee:	d10c      	bne.n	801a20a <tcp_input+0x456>
+          lpcb_prev = prev;
+#else /* SO_REUSE */
+          break;
+#endif /* SO_REUSE */
+        } else if (IP_ADDR_PCB_VERSION_MATCH_EXACT(lpcb, ip_current_dest_addr())) {
+          if (ip_addr_cmp(&lpcb->local_ip, ip_current_dest_addr())) {
+ 801a1f0:	697b      	ldr	r3, [r7, #20]
+ 801a1f2:	681a      	ldr	r2, [r3, #0]
+ 801a1f4:	4b17      	ldr	r3, [pc, #92]	; (801a254 <tcp_input+0x4a0>)
+ 801a1f6:	695b      	ldr	r3, [r3, #20]
+ 801a1f8:	429a      	cmp	r2, r3
+ 801a1fa:	d00f      	beq.n	801a21c <tcp_input+0x468>
+            /* found an exact match */
+            break;
+          } else if (ip_addr_isany(&lpcb->local_ip)) {
+ 801a1fc:	697b      	ldr	r3, [r7, #20]
+ 801a1fe:	2b00      	cmp	r3, #0
+ 801a200:	d00d      	beq.n	801a21e <tcp_input+0x46a>
+ 801a202:	697b      	ldr	r3, [r7, #20]
+ 801a204:	681b      	ldr	r3, [r3, #0]
+ 801a206:	2b00      	cmp	r3, #0
+ 801a208:	d009      	beq.n	801a21e <tcp_input+0x46a>
+            break;
+#endif /* SO_REUSE */
+          }
+        }
+      }
+      prev = (struct tcp_pcb *)lpcb;
+ 801a20a:	697b      	ldr	r3, [r7, #20]
+ 801a20c:	61fb      	str	r3, [r7, #28]
+    for (lpcb = tcp_listen_pcbs.listen_pcbs; lpcb != NULL; lpcb = lpcb->next) {
+ 801a20e:	697b      	ldr	r3, [r7, #20]
+ 801a210:	68db      	ldr	r3, [r3, #12]
+ 801a212:	617b      	str	r3, [r7, #20]
+ 801a214:	697b      	ldr	r3, [r7, #20]
+ 801a216:	2b00      	cmp	r3, #0
+ 801a218:	d1d1      	bne.n	801a1be <tcp_input+0x40a>
+ 801a21a:	e000      	b.n	801a21e <tcp_input+0x46a>
+            break;
+ 801a21c:	bf00      	nop
+      /* only pass to ANY if no specific local IP has been found */
+      lpcb = lpcb_any;
+      prev = lpcb_prev;
+    }
+#endif /* SO_REUSE */
+    if (lpcb != NULL) {
+ 801a21e:	697b      	ldr	r3, [r7, #20]
+ 801a220:	2b00      	cmp	r3, #0
+ 801a222:	d029      	beq.n	801a278 <tcp_input+0x4c4>
+      /* Move this PCB to the front of the list so that subsequent
+         lookups will be faster (we exploit locality in TCP segment
+         arrivals). */
+      if (prev != NULL) {
+ 801a224:	69fb      	ldr	r3, [r7, #28]
+ 801a226:	2b00      	cmp	r3, #0
+ 801a228:	d00a      	beq.n	801a240 <tcp_input+0x48c>
+        ((struct tcp_pcb_listen *)prev)->next = lpcb->next;
+ 801a22a:	697b      	ldr	r3, [r7, #20]
+ 801a22c:	68da      	ldr	r2, [r3, #12]
+ 801a22e:	69fb      	ldr	r3, [r7, #28]
+ 801a230:	60da      	str	r2, [r3, #12]
+        /* our successor is the remainder of the listening list */
+        lpcb->next = tcp_listen_pcbs.listen_pcbs;
+ 801a232:	4b10      	ldr	r3, [pc, #64]	; (801a274 <tcp_input+0x4c0>)
+ 801a234:	681a      	ldr	r2, [r3, #0]
+ 801a236:	697b      	ldr	r3, [r7, #20]
+ 801a238:	60da      	str	r2, [r3, #12]
+        /* put this listening pcb at the head of the listening list */
+        tcp_listen_pcbs.listen_pcbs = lpcb;
+ 801a23a:	4a0e      	ldr	r2, [pc, #56]	; (801a274 <tcp_input+0x4c0>)
+ 801a23c:	697b      	ldr	r3, [r7, #20]
+ 801a23e:	6013      	str	r3, [r2, #0]
+#ifdef LWIP_HOOK_TCP_INPACKET_PCB
+      if (LWIP_HOOK_TCP_INPACKET_PCB((struct tcp_pcb *)lpcb, tcphdr, tcphdr_optlen,
+                                     tcphdr_opt1len, tcphdr_opt2, p) == ERR_OK)
+#endif
+      {
+        tcp_listen_input(lpcb);
+ 801a240:	6978      	ldr	r0, [r7, #20]
+ 801a242:	f000 fa03 	bl	801a64c <tcp_listen_input>
+      }
+      pbuf_free(p);
+ 801a246:	6878      	ldr	r0, [r7, #4]
+ 801a248:	f7fd fc56 	bl	8017af8 <pbuf_free>
+      return;
+ 801a24c:	e1a8      	b.n	801a5a0 <tcp_input+0x7ec>
+ 801a24e:	bf00      	nop
+ 801a250:	2401a4ac 	.word	0x2401a4ac
+ 801a254:	24013980 	.word	0x24013980
+ 801a258:	08025338 	.word	0x08025338
+ 801a25c:	08025464 	.word	0x08025464
+ 801a260:	08025384 	.word	0x08025384
+ 801a264:	2401a48c 	.word	0x2401a48c
+ 801a268:	08025490 	.word	0x08025490
+ 801a26c:	2401a490 	.word	0x2401a490
+ 801a270:	080254bc 	.word	0x080254bc
+ 801a274:	2401a488 	.word	0x2401a488
+      tcphdr_opt1len, tcphdr_opt2, p) != ERR_OK) {
+    pbuf_free(p);
+    return;
+  }
+#endif
+  if (pcb != NULL) {
+ 801a278:	69bb      	ldr	r3, [r7, #24]
+ 801a27a:	2b00      	cmp	r3, #0
+ 801a27c:	f000 8158 	beq.w	801a530 <tcp_input+0x77c>
+#if TCP_INPUT_DEBUG
+    tcp_debug_print_state(pcb->state);
+#endif /* TCP_INPUT_DEBUG */
+
+    /* Set up a tcp_seg structure. */
+    inseg.next = NULL;
+ 801a280:	4b95      	ldr	r3, [pc, #596]	; (801a4d8 <tcp_input+0x724>)
+ 801a282:	2200      	movs	r2, #0
+ 801a284:	601a      	str	r2, [r3, #0]
+    inseg.len = p->tot_len;
+ 801a286:	687b      	ldr	r3, [r7, #4]
+ 801a288:	891a      	ldrh	r2, [r3, #8]
+ 801a28a:	4b93      	ldr	r3, [pc, #588]	; (801a4d8 <tcp_input+0x724>)
+ 801a28c:	811a      	strh	r2, [r3, #8]
+    inseg.p = p;
+ 801a28e:	4a92      	ldr	r2, [pc, #584]	; (801a4d8 <tcp_input+0x724>)
+ 801a290:	687b      	ldr	r3, [r7, #4]
+ 801a292:	6053      	str	r3, [r2, #4]
+    inseg.tcphdr = tcphdr;
+ 801a294:	4b91      	ldr	r3, [pc, #580]	; (801a4dc <tcp_input+0x728>)
+ 801a296:	681b      	ldr	r3, [r3, #0]
+ 801a298:	4a8f      	ldr	r2, [pc, #572]	; (801a4d8 <tcp_input+0x724>)
+ 801a29a:	6113      	str	r3, [r2, #16]
+
+    recv_data = NULL;
+ 801a29c:	4b90      	ldr	r3, [pc, #576]	; (801a4e0 <tcp_input+0x72c>)
+ 801a29e:	2200      	movs	r2, #0
+ 801a2a0:	601a      	str	r2, [r3, #0]
+    recv_flags = 0;
+ 801a2a2:	4b90      	ldr	r3, [pc, #576]	; (801a4e4 <tcp_input+0x730>)
+ 801a2a4:	2200      	movs	r2, #0
+ 801a2a6:	701a      	strb	r2, [r3, #0]
+    recv_acked = 0;
+ 801a2a8:	4b8f      	ldr	r3, [pc, #572]	; (801a4e8 <tcp_input+0x734>)
+ 801a2aa:	2200      	movs	r2, #0
+ 801a2ac:	801a      	strh	r2, [r3, #0]
+
+    if (flags & TCP_PSH) {
+ 801a2ae:	4b8f      	ldr	r3, [pc, #572]	; (801a4ec <tcp_input+0x738>)
+ 801a2b0:	781b      	ldrb	r3, [r3, #0]
+ 801a2b2:	f003 0308 	and.w	r3, r3, #8
+ 801a2b6:	2b00      	cmp	r3, #0
+ 801a2b8:	d006      	beq.n	801a2c8 <tcp_input+0x514>
+      p->flags |= PBUF_FLAG_PUSH;
+ 801a2ba:	687b      	ldr	r3, [r7, #4]
+ 801a2bc:	7b5b      	ldrb	r3, [r3, #13]
+ 801a2be:	f043 0301 	orr.w	r3, r3, #1
+ 801a2c2:	b2da      	uxtb	r2, r3
+ 801a2c4:	687b      	ldr	r3, [r7, #4]
+ 801a2c6:	735a      	strb	r2, [r3, #13]
+    }
+
+    /* If there is data which was previously "refused" by upper layer */
+    if (pcb->refused_data != NULL) {
+ 801a2c8:	69bb      	ldr	r3, [r7, #24]
+ 801a2ca:	6f9b      	ldr	r3, [r3, #120]	; 0x78
+ 801a2cc:	2b00      	cmp	r3, #0
+ 801a2ce:	d017      	beq.n	801a300 <tcp_input+0x54c>
+      if ((tcp_process_refused_data(pcb) == ERR_ABRT) ||
+ 801a2d0:	69b8      	ldr	r0, [r7, #24]
+ 801a2d2:	f7ff f853 	bl	801937c <tcp_process_refused_data>
+ 801a2d6:	4603      	mov	r3, r0
+ 801a2d8:	f113 0f0d 	cmn.w	r3, #13
+ 801a2dc:	d007      	beq.n	801a2ee <tcp_input+0x53a>
+          ((pcb->refused_data != NULL) && (tcplen > 0))) {
+ 801a2de:	69bb      	ldr	r3, [r7, #24]
+ 801a2e0:	6f9b      	ldr	r3, [r3, #120]	; 0x78
+      if ((tcp_process_refused_data(pcb) == ERR_ABRT) ||
+ 801a2e2:	2b00      	cmp	r3, #0
+ 801a2e4:	d00c      	beq.n	801a300 <tcp_input+0x54c>
+          ((pcb->refused_data != NULL) && (tcplen > 0))) {
+ 801a2e6:	4b82      	ldr	r3, [pc, #520]	; (801a4f0 <tcp_input+0x73c>)
+ 801a2e8:	881b      	ldrh	r3, [r3, #0]
+ 801a2ea:	2b00      	cmp	r3, #0
+ 801a2ec:	d008      	beq.n	801a300 <tcp_input+0x54c>
+        /* pcb has been aborted or refused data is still refused and the new
+           segment contains data */
+        if (pcb->rcv_ann_wnd == 0) {
+ 801a2ee:	69bb      	ldr	r3, [r7, #24]
+ 801a2f0:	8d5b      	ldrh	r3, [r3, #42]	; 0x2a
+ 801a2f2:	2b00      	cmp	r3, #0
+ 801a2f4:	f040 80e4 	bne.w	801a4c0 <tcp_input+0x70c>
+          /* this is a zero-window probe, we respond to it with current RCV.NXT
+          and drop the data segment */
+          tcp_send_empty_ack(pcb);
+ 801a2f8:	69b8      	ldr	r0, [r7, #24]
+ 801a2fa:	f003 fe71 	bl	801dfe0 <tcp_send_empty_ack>
+        }
+        TCP_STATS_INC(tcp.drop);
+        MIB2_STATS_INC(mib2.tcpinerrs);
+        goto aborted;
+ 801a2fe:	e0df      	b.n	801a4c0 <tcp_input+0x70c>
+      }
+    }
+    tcp_input_pcb = pcb;
+ 801a300:	4a7c      	ldr	r2, [pc, #496]	; (801a4f4 <tcp_input+0x740>)
+ 801a302:	69bb      	ldr	r3, [r7, #24]
+ 801a304:	6013      	str	r3, [r2, #0]
+    err = tcp_process(pcb);
+ 801a306:	69b8      	ldr	r0, [r7, #24]
+ 801a308:	f000 fb18 	bl	801a93c <tcp_process>
+ 801a30c:	4603      	mov	r3, r0
+ 801a30e:	74fb      	strb	r3, [r7, #19]
+    /* A return value of ERR_ABRT means that tcp_abort() was called
+       and that the pcb has been freed. If so, we don't do anything. */
+    if (err != ERR_ABRT) {
+ 801a310:	f997 3013 	ldrsb.w	r3, [r7, #19]
+ 801a314:	f113 0f0d 	cmn.w	r3, #13
+ 801a318:	f000 80d4 	beq.w	801a4c4 <tcp_input+0x710>
+      if (recv_flags & TF_RESET) {
+ 801a31c:	4b71      	ldr	r3, [pc, #452]	; (801a4e4 <tcp_input+0x730>)
+ 801a31e:	781b      	ldrb	r3, [r3, #0]
+ 801a320:	f003 0308 	and.w	r3, r3, #8
+ 801a324:	2b00      	cmp	r3, #0
+ 801a326:	d015      	beq.n	801a354 <tcp_input+0x5a0>
+        /* TF_RESET means that the connection was reset by the other
+           end. We then call the error callback to inform the
+           application that the connection is dead before we
+           deallocate the PCB. */
+        TCP_EVENT_ERR(pcb->state, pcb->errf, pcb->callback_arg, ERR_RST);
+ 801a328:	69bb      	ldr	r3, [r7, #24]
+ 801a32a:	f8d3 3090 	ldr.w	r3, [r3, #144]	; 0x90
+ 801a32e:	2b00      	cmp	r3, #0
+ 801a330:	d008      	beq.n	801a344 <tcp_input+0x590>
+ 801a332:	69bb      	ldr	r3, [r7, #24]
+ 801a334:	f8d3 3090 	ldr.w	r3, [r3, #144]	; 0x90
+ 801a338:	69ba      	ldr	r2, [r7, #24]
+ 801a33a:	6912      	ldr	r2, [r2, #16]
+ 801a33c:	f06f 010d 	mvn.w	r1, #13
+ 801a340:	4610      	mov	r0, r2
+ 801a342:	4798      	blx	r3
+        tcp_pcb_remove(&tcp_active_pcbs, pcb);
+ 801a344:	69b9      	ldr	r1, [r7, #24]
+ 801a346:	486c      	ldr	r0, [pc, #432]	; (801a4f8 <tcp_input+0x744>)
+ 801a348:	f7ff fbb6 	bl	8019ab8 <tcp_pcb_remove>
+        tcp_free(pcb);
+ 801a34c:	69b8      	ldr	r0, [r7, #24]
+ 801a34e:	f7fd fe7f 	bl	8018050 <tcp_free>
+ 801a352:	e0da      	b.n	801a50a <tcp_input+0x756>
+      } else {
+        err = ERR_OK;
+ 801a354:	2300      	movs	r3, #0
+ 801a356:	74fb      	strb	r3, [r7, #19]
+        /* If the application has registered a "sent" function to be
+           called when new send buffer space is available, we call it
+           now. */
+        if (recv_acked > 0) {
+ 801a358:	4b63      	ldr	r3, [pc, #396]	; (801a4e8 <tcp_input+0x734>)
+ 801a35a:	881b      	ldrh	r3, [r3, #0]
+ 801a35c:	2b00      	cmp	r3, #0
+ 801a35e:	d01d      	beq.n	801a39c <tcp_input+0x5e8>
+          while (acked > 0) {
+            acked16 = (u16_t)LWIP_MIN(acked, 0xffffu);
+            acked -= acked16;
+#else
+          {
+            acked16 = recv_acked;
+ 801a360:	4b61      	ldr	r3, [pc, #388]	; (801a4e8 <tcp_input+0x734>)
+ 801a362:	881b      	ldrh	r3, [r3, #0]
+ 801a364:	81fb      	strh	r3, [r7, #14]
+#endif
+            TCP_EVENT_SENT(pcb, (u16_t)acked16, err);
+ 801a366:	69bb      	ldr	r3, [r7, #24]
+ 801a368:	f8d3 3080 	ldr.w	r3, [r3, #128]	; 0x80
+ 801a36c:	2b00      	cmp	r3, #0
+ 801a36e:	d00a      	beq.n	801a386 <tcp_input+0x5d2>
+ 801a370:	69bb      	ldr	r3, [r7, #24]
+ 801a372:	f8d3 3080 	ldr.w	r3, [r3, #128]	; 0x80
+ 801a376:	69ba      	ldr	r2, [r7, #24]
+ 801a378:	6910      	ldr	r0, [r2, #16]
+ 801a37a:	89fa      	ldrh	r2, [r7, #14]
+ 801a37c:	69b9      	ldr	r1, [r7, #24]
+ 801a37e:	4798      	blx	r3
+ 801a380:	4603      	mov	r3, r0
+ 801a382:	74fb      	strb	r3, [r7, #19]
+ 801a384:	e001      	b.n	801a38a <tcp_input+0x5d6>
+ 801a386:	2300      	movs	r3, #0
+ 801a388:	74fb      	strb	r3, [r7, #19]
+            if (err == ERR_ABRT) {
+ 801a38a:	f997 3013 	ldrsb.w	r3, [r7, #19]
+ 801a38e:	f113 0f0d 	cmn.w	r3, #13
+ 801a392:	f000 8099 	beq.w	801a4c8 <tcp_input+0x714>
+              goto aborted;
+            }
+          }
+          recv_acked = 0;
+ 801a396:	4b54      	ldr	r3, [pc, #336]	; (801a4e8 <tcp_input+0x734>)
+ 801a398:	2200      	movs	r2, #0
+ 801a39a:	801a      	strh	r2, [r3, #0]
+        }
+        if (tcp_input_delayed_close(pcb)) {
+ 801a39c:	69b8      	ldr	r0, [r7, #24]
+ 801a39e:	f000 f915 	bl	801a5cc <tcp_input_delayed_close>
+ 801a3a2:	4603      	mov	r3, r0
+ 801a3a4:	2b00      	cmp	r3, #0
+ 801a3a6:	f040 8091 	bne.w	801a4cc <tcp_input+0x718>
+#if TCP_QUEUE_OOSEQ && LWIP_WND_SCALE
+        while (recv_data != NULL) {
+          struct pbuf *rest = NULL;
+          pbuf_split_64k(recv_data, &rest);
+#else /* TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */
+        if (recv_data != NULL) {
+ 801a3aa:	4b4d      	ldr	r3, [pc, #308]	; (801a4e0 <tcp_input+0x72c>)
+ 801a3ac:	681b      	ldr	r3, [r3, #0]
+ 801a3ae:	2b00      	cmp	r3, #0
+ 801a3b0:	d041      	beq.n	801a436 <tcp_input+0x682>
+#endif /* TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */
+
+          LWIP_ASSERT("pcb->refused_data == NULL", pcb->refused_data == NULL);
+ 801a3b2:	69bb      	ldr	r3, [r7, #24]
+ 801a3b4:	6f9b      	ldr	r3, [r3, #120]	; 0x78
+ 801a3b6:	2b00      	cmp	r3, #0
+ 801a3b8:	d006      	beq.n	801a3c8 <tcp_input+0x614>
+ 801a3ba:	4b50      	ldr	r3, [pc, #320]	; (801a4fc <tcp_input+0x748>)
+ 801a3bc:	f44f 72f3 	mov.w	r2, #486	; 0x1e6
+ 801a3c0:	494f      	ldr	r1, [pc, #316]	; (801a500 <tcp_input+0x74c>)
+ 801a3c2:	4850      	ldr	r0, [pc, #320]	; (801a504 <tcp_input+0x750>)
+ 801a3c4:	f007 fae0 	bl	8021988 <iprintf>
+          if (pcb->flags & TF_RXCLOSED) {
+ 801a3c8:	69bb      	ldr	r3, [r7, #24]
+ 801a3ca:	8b5b      	ldrh	r3, [r3, #26]
+ 801a3cc:	f003 0310 	and.w	r3, r3, #16
+ 801a3d0:	2b00      	cmp	r3, #0
+ 801a3d2:	d008      	beq.n	801a3e6 <tcp_input+0x632>
+            /* received data although already closed -> abort (send RST) to
+               notify the remote host that not all data has been processed */
+            pbuf_free(recv_data);
+ 801a3d4:	4b42      	ldr	r3, [pc, #264]	; (801a4e0 <tcp_input+0x72c>)
+ 801a3d6:	681b      	ldr	r3, [r3, #0]
+ 801a3d8:	4618      	mov	r0, r3
+ 801a3da:	f7fd fb8d 	bl	8017af8 <pbuf_free>
+#if TCP_QUEUE_OOSEQ && LWIP_WND_SCALE
+            if (rest != NULL) {
+              pbuf_free(rest);
+            }
+#endif /* TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */
+            tcp_abort(pcb);
+ 801a3de:	69b8      	ldr	r0, [r7, #24]
+ 801a3e0:	f7fe f97a 	bl	80186d8 <tcp_abort>
+            goto aborted;
+ 801a3e4:	e091      	b.n	801a50a <tcp_input+0x756>
+          }
+
+          /* Notify application that data has been received. */
+          TCP_EVENT_RECV(pcb, recv_data, ERR_OK, err);
+ 801a3e6:	69bb      	ldr	r3, [r7, #24]
+ 801a3e8:	f8d3 3084 	ldr.w	r3, [r3, #132]	; 0x84
+ 801a3ec:	2b00      	cmp	r3, #0
+ 801a3ee:	d00c      	beq.n	801a40a <tcp_input+0x656>
+ 801a3f0:	69bb      	ldr	r3, [r7, #24]
+ 801a3f2:	f8d3 4084 	ldr.w	r4, [r3, #132]	; 0x84
+ 801a3f6:	69bb      	ldr	r3, [r7, #24]
+ 801a3f8:	6918      	ldr	r0, [r3, #16]
+ 801a3fa:	4b39      	ldr	r3, [pc, #228]	; (801a4e0 <tcp_input+0x72c>)
+ 801a3fc:	681a      	ldr	r2, [r3, #0]
+ 801a3fe:	2300      	movs	r3, #0
+ 801a400:	69b9      	ldr	r1, [r7, #24]
+ 801a402:	47a0      	blx	r4
+ 801a404:	4603      	mov	r3, r0
+ 801a406:	74fb      	strb	r3, [r7, #19]
+ 801a408:	e008      	b.n	801a41c <tcp_input+0x668>
+ 801a40a:	4b35      	ldr	r3, [pc, #212]	; (801a4e0 <tcp_input+0x72c>)
+ 801a40c:	681a      	ldr	r2, [r3, #0]
+ 801a40e:	2300      	movs	r3, #0
+ 801a410:	69b9      	ldr	r1, [r7, #24]
+ 801a412:	2000      	movs	r0, #0
+ 801a414:	f7ff f88a 	bl	801952c <tcp_recv_null>
+ 801a418:	4603      	mov	r3, r0
+ 801a41a:	74fb      	strb	r3, [r7, #19]
+          if (err == ERR_ABRT) {
+ 801a41c:	f997 3013 	ldrsb.w	r3, [r7, #19]
+ 801a420:	f113 0f0d 	cmn.w	r3, #13
+ 801a424:	d054      	beq.n	801a4d0 <tcp_input+0x71c>
+#endif /* TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */
+            goto aborted;
+          }
+
+          /* If the upper layer can't receive this data, store it */
+          if (err != ERR_OK) {
+ 801a426:	f997 3013 	ldrsb.w	r3, [r7, #19]
+ 801a42a:	2b00      	cmp	r3, #0
+ 801a42c:	d003      	beq.n	801a436 <tcp_input+0x682>
+#if TCP_QUEUE_OOSEQ && LWIP_WND_SCALE
+            if (rest != NULL) {
+              pbuf_cat(recv_data, rest);
+            }
+#endif /* TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */
+            pcb->refused_data = recv_data;
+ 801a42e:	4b2c      	ldr	r3, [pc, #176]	; (801a4e0 <tcp_input+0x72c>)
+ 801a430:	681a      	ldr	r2, [r3, #0]
+ 801a432:	69bb      	ldr	r3, [r7, #24]
+ 801a434:	679a      	str	r2, [r3, #120]	; 0x78
+          }
+        }
+
+        /* If a FIN segment was received, we call the callback
+           function with a NULL buffer to indicate EOF. */
+        if (recv_flags & TF_GOT_FIN) {
+ 801a436:	4b2b      	ldr	r3, [pc, #172]	; (801a4e4 <tcp_input+0x730>)
+ 801a438:	781b      	ldrb	r3, [r3, #0]
+ 801a43a:	f003 0320 	and.w	r3, r3, #32
+ 801a43e:	2b00      	cmp	r3, #0
+ 801a440:	d031      	beq.n	801a4a6 <tcp_input+0x6f2>
+          if (pcb->refused_data != NULL) {
+ 801a442:	69bb      	ldr	r3, [r7, #24]
+ 801a444:	6f9b      	ldr	r3, [r3, #120]	; 0x78
+ 801a446:	2b00      	cmp	r3, #0
+ 801a448:	d009      	beq.n	801a45e <tcp_input+0x6aa>
+            /* Delay this if we have refused data. */
+            pcb->refused_data->flags |= PBUF_FLAG_TCP_FIN;
+ 801a44a:	69bb      	ldr	r3, [r7, #24]
+ 801a44c:	6f9b      	ldr	r3, [r3, #120]	; 0x78
+ 801a44e:	7b5a      	ldrb	r2, [r3, #13]
+ 801a450:	69bb      	ldr	r3, [r7, #24]
+ 801a452:	6f9b      	ldr	r3, [r3, #120]	; 0x78
+ 801a454:	f042 0220 	orr.w	r2, r2, #32
+ 801a458:	b2d2      	uxtb	r2, r2
+ 801a45a:	735a      	strb	r2, [r3, #13]
+ 801a45c:	e023      	b.n	801a4a6 <tcp_input+0x6f2>
+          } else {
+            /* correct rcv_wnd as the application won't call tcp_recved()
+               for the FIN's seqno */
+            if (pcb->rcv_wnd != TCP_WND_MAX(pcb)) {
+ 801a45e:	69bb      	ldr	r3, [r7, #24]
+ 801a460:	8d1b      	ldrh	r3, [r3, #40]	; 0x28
+ 801a462:	f241 62d0 	movw	r2, #5840	; 0x16d0
+ 801a466:	4293      	cmp	r3, r2
+ 801a468:	d005      	beq.n	801a476 <tcp_input+0x6c2>
+              pcb->rcv_wnd++;
+ 801a46a:	69bb      	ldr	r3, [r7, #24]
+ 801a46c:	8d1b      	ldrh	r3, [r3, #40]	; 0x28
+ 801a46e:	3301      	adds	r3, #1
+ 801a470:	b29a      	uxth	r2, r3
+ 801a472:	69bb      	ldr	r3, [r7, #24]
+ 801a474:	851a      	strh	r2, [r3, #40]	; 0x28
+            }
+            TCP_EVENT_CLOSED(pcb, err);
+ 801a476:	69bb      	ldr	r3, [r7, #24]
+ 801a478:	f8d3 3084 	ldr.w	r3, [r3, #132]	; 0x84
+ 801a47c:	2b00      	cmp	r3, #0
+ 801a47e:	d00b      	beq.n	801a498 <tcp_input+0x6e4>
+ 801a480:	69bb      	ldr	r3, [r7, #24]
+ 801a482:	f8d3 4084 	ldr.w	r4, [r3, #132]	; 0x84
+ 801a486:	69bb      	ldr	r3, [r7, #24]
+ 801a488:	6918      	ldr	r0, [r3, #16]
+ 801a48a:	2300      	movs	r3, #0
+ 801a48c:	2200      	movs	r2, #0
+ 801a48e:	69b9      	ldr	r1, [r7, #24]
+ 801a490:	47a0      	blx	r4
+ 801a492:	4603      	mov	r3, r0
+ 801a494:	74fb      	strb	r3, [r7, #19]
+ 801a496:	e001      	b.n	801a49c <tcp_input+0x6e8>
+ 801a498:	2300      	movs	r3, #0
+ 801a49a:	74fb      	strb	r3, [r7, #19]
+            if (err == ERR_ABRT) {
+ 801a49c:	f997 3013 	ldrsb.w	r3, [r7, #19]
+ 801a4a0:	f113 0f0d 	cmn.w	r3, #13
+ 801a4a4:	d016      	beq.n	801a4d4 <tcp_input+0x720>
+              goto aborted;
+            }
+          }
+        }
+
+        tcp_input_pcb = NULL;
+ 801a4a6:	4b13      	ldr	r3, [pc, #76]	; (801a4f4 <tcp_input+0x740>)
+ 801a4a8:	2200      	movs	r2, #0
+ 801a4aa:	601a      	str	r2, [r3, #0]
+        if (tcp_input_delayed_close(pcb)) {
+ 801a4ac:	69b8      	ldr	r0, [r7, #24]
+ 801a4ae:	f000 f88d 	bl	801a5cc <tcp_input_delayed_close>
+ 801a4b2:	4603      	mov	r3, r0
+ 801a4b4:	2b00      	cmp	r3, #0
+ 801a4b6:	d127      	bne.n	801a508 <tcp_input+0x754>
+          goto aborted;
+        }
+        /* Try to send something out. */
+        tcp_output(pcb);
+ 801a4b8:	69b8      	ldr	r0, [r7, #24]
+ 801a4ba:	f002 ff7f 	bl	801d3bc <tcp_output>
+ 801a4be:	e024      	b.n	801a50a <tcp_input+0x756>
+        goto aborted;
+ 801a4c0:	bf00      	nop
+ 801a4c2:	e022      	b.n	801a50a <tcp_input+0x756>
+#endif /* TCP_INPUT_DEBUG */
+      }
+    }
+    /* Jump target if pcb has been aborted in a callback (by calling tcp_abort()).
+       Below this line, 'pcb' may not be dereferenced! */
+aborted:
+ 801a4c4:	bf00      	nop
+ 801a4c6:	e020      	b.n	801a50a <tcp_input+0x756>
+              goto aborted;
+ 801a4c8:	bf00      	nop
+ 801a4ca:	e01e      	b.n	801a50a <tcp_input+0x756>
+          goto aborted;
+ 801a4cc:	bf00      	nop
+ 801a4ce:	e01c      	b.n	801a50a <tcp_input+0x756>
+            goto aborted;
+ 801a4d0:	bf00      	nop
+ 801a4d2:	e01a      	b.n	801a50a <tcp_input+0x756>
+              goto aborted;
+ 801a4d4:	bf00      	nop
+ 801a4d6:	e018      	b.n	801a50a <tcp_input+0x756>
+ 801a4d8:	2401a498 	.word	0x2401a498
+ 801a4dc:	2401a4ac 	.word	0x2401a4ac
+ 801a4e0:	2401a4cc 	.word	0x2401a4cc
+ 801a4e4:	2401a4c9 	.word	0x2401a4c9
+ 801a4e8:	2401a4c4 	.word	0x2401a4c4
+ 801a4ec:	2401a4c8 	.word	0x2401a4c8
+ 801a4f0:	2401a4c6 	.word	0x2401a4c6
+ 801a4f4:	2401a4d0 	.word	0x2401a4d0
+ 801a4f8:	2401a48c 	.word	0x2401a48c
+ 801a4fc:	08025338 	.word	0x08025338
+ 801a500:	080254ec 	.word	0x080254ec
+ 801a504:	08025384 	.word	0x08025384
+          goto aborted;
+ 801a508:	bf00      	nop
+    tcp_input_pcb = NULL;
+ 801a50a:	4b27      	ldr	r3, [pc, #156]	; (801a5a8 <tcp_input+0x7f4>)
+ 801a50c:	2200      	movs	r2, #0
+ 801a50e:	601a      	str	r2, [r3, #0]
+    recv_data = NULL;
+ 801a510:	4b26      	ldr	r3, [pc, #152]	; (801a5ac <tcp_input+0x7f8>)
+ 801a512:	2200      	movs	r2, #0
+ 801a514:	601a      	str	r2, [r3, #0]
+
+    /* give up our reference to inseg.p */
+    if (inseg.p != NULL) {
+ 801a516:	4b26      	ldr	r3, [pc, #152]	; (801a5b0 <tcp_input+0x7fc>)
+ 801a518:	685b      	ldr	r3, [r3, #4]
+ 801a51a:	2b00      	cmp	r3, #0
+ 801a51c:	d03f      	beq.n	801a59e <tcp_input+0x7ea>
+      pbuf_free(inseg.p);
+ 801a51e:	4b24      	ldr	r3, [pc, #144]	; (801a5b0 <tcp_input+0x7fc>)
+ 801a520:	685b      	ldr	r3, [r3, #4]
+ 801a522:	4618      	mov	r0, r3
+ 801a524:	f7fd fae8 	bl	8017af8 <pbuf_free>
+      inseg.p = NULL;
+ 801a528:	4b21      	ldr	r3, [pc, #132]	; (801a5b0 <tcp_input+0x7fc>)
+ 801a52a:	2200      	movs	r2, #0
+ 801a52c:	605a      	str	r2, [r3, #4]
+    pbuf_free(p);
+  }
+
+  LWIP_ASSERT("tcp_input: tcp_pcbs_sane()", tcp_pcbs_sane());
+  PERF_STOP("tcp_input");
+  return;
+ 801a52e:	e036      	b.n	801a59e <tcp_input+0x7ea>
+    if (!(TCPH_FLAGS(tcphdr) & TCP_RST)) {
+ 801a530:	4b20      	ldr	r3, [pc, #128]	; (801a5b4 <tcp_input+0x800>)
+ 801a532:	681b      	ldr	r3, [r3, #0]
+ 801a534:	899b      	ldrh	r3, [r3, #12]
+ 801a536:	b29b      	uxth	r3, r3
+ 801a538:	4618      	mov	r0, r3
+ 801a53a:	f7fb fd01 	bl	8015f40 <lwip_htons>
+ 801a53e:	4603      	mov	r3, r0
+ 801a540:	b2db      	uxtb	r3, r3
+ 801a542:	f003 0304 	and.w	r3, r3, #4
+ 801a546:	2b00      	cmp	r3, #0
+ 801a548:	d118      	bne.n	801a57c <tcp_input+0x7c8>
+      tcp_rst(NULL, ackno, seqno + tcplen, ip_current_dest_addr(),
+ 801a54a:	4b1b      	ldr	r3, [pc, #108]	; (801a5b8 <tcp_input+0x804>)
+ 801a54c:	6819      	ldr	r1, [r3, #0]
+ 801a54e:	4b1b      	ldr	r3, [pc, #108]	; (801a5bc <tcp_input+0x808>)
+ 801a550:	881b      	ldrh	r3, [r3, #0]
+ 801a552:	461a      	mov	r2, r3
+ 801a554:	4b1a      	ldr	r3, [pc, #104]	; (801a5c0 <tcp_input+0x80c>)
+ 801a556:	681b      	ldr	r3, [r3, #0]
+ 801a558:	18d0      	adds	r0, r2, r3
+              ip_current_src_addr(), tcphdr->dest, tcphdr->src);
+ 801a55a:	4b16      	ldr	r3, [pc, #88]	; (801a5b4 <tcp_input+0x800>)
+ 801a55c:	681b      	ldr	r3, [r3, #0]
+      tcp_rst(NULL, ackno, seqno + tcplen, ip_current_dest_addr(),
+ 801a55e:	885b      	ldrh	r3, [r3, #2]
+ 801a560:	b29b      	uxth	r3, r3
+              ip_current_src_addr(), tcphdr->dest, tcphdr->src);
+ 801a562:	4a14      	ldr	r2, [pc, #80]	; (801a5b4 <tcp_input+0x800>)
+ 801a564:	6812      	ldr	r2, [r2, #0]
+      tcp_rst(NULL, ackno, seqno + tcplen, ip_current_dest_addr(),
+ 801a566:	8812      	ldrh	r2, [r2, #0]
+ 801a568:	b292      	uxth	r2, r2
+ 801a56a:	9202      	str	r2, [sp, #8]
+ 801a56c:	9301      	str	r3, [sp, #4]
+ 801a56e:	4b15      	ldr	r3, [pc, #84]	; (801a5c4 <tcp_input+0x810>)
+ 801a570:	9300      	str	r3, [sp, #0]
+ 801a572:	4b15      	ldr	r3, [pc, #84]	; (801a5c8 <tcp_input+0x814>)
+ 801a574:	4602      	mov	r2, r0
+ 801a576:	2000      	movs	r0, #0
+ 801a578:	f003 fce0 	bl	801df3c <tcp_rst>
+    pbuf_free(p);
+ 801a57c:	6878      	ldr	r0, [r7, #4]
+ 801a57e:	f7fd fabb 	bl	8017af8 <pbuf_free>
+  return;
+ 801a582:	e00c      	b.n	801a59e <tcp_input+0x7ea>
+    goto dropped;
+ 801a584:	bf00      	nop
+ 801a586:	e006      	b.n	801a596 <tcp_input+0x7e2>
+    goto dropped;
+ 801a588:	bf00      	nop
+ 801a58a:	e004      	b.n	801a596 <tcp_input+0x7e2>
+    goto dropped;
+ 801a58c:	bf00      	nop
+ 801a58e:	e002      	b.n	801a596 <tcp_input+0x7e2>
+      goto dropped;
+ 801a590:	bf00      	nop
+ 801a592:	e000      	b.n	801a596 <tcp_input+0x7e2>
+      goto dropped;
+ 801a594:	bf00      	nop
+dropped:
+  TCP_STATS_INC(tcp.drop);
+  MIB2_STATS_INC(mib2.tcpinerrs);
+  pbuf_free(p);
+ 801a596:	6878      	ldr	r0, [r7, #4]
+ 801a598:	f7fd faae 	bl	8017af8 <pbuf_free>
+ 801a59c:	e000      	b.n	801a5a0 <tcp_input+0x7ec>
+  return;
+ 801a59e:	bf00      	nop
+}
+ 801a5a0:	3724      	adds	r7, #36	; 0x24
+ 801a5a2:	46bd      	mov	sp, r7
+ 801a5a4:	bd90      	pop	{r4, r7, pc}
+ 801a5a6:	bf00      	nop
+ 801a5a8:	2401a4d0 	.word	0x2401a4d0
+ 801a5ac:	2401a4cc 	.word	0x2401a4cc
+ 801a5b0:	2401a498 	.word	0x2401a498
+ 801a5b4:	2401a4ac 	.word	0x2401a4ac
+ 801a5b8:	2401a4c0 	.word	0x2401a4c0
+ 801a5bc:	2401a4c6 	.word	0x2401a4c6
+ 801a5c0:	2401a4bc 	.word	0x2401a4bc
+ 801a5c4:	24013990 	.word	0x24013990
+ 801a5c8:	24013994 	.word	0x24013994
+
+0801a5cc <tcp_input_delayed_close>:
+ * any more.
+ * @returns 1 if the pcb has been closed and deallocated, 0 otherwise
+ */
+static int
+tcp_input_delayed_close(struct tcp_pcb *pcb)
+{
+ 801a5cc:	b580      	push	{r7, lr}
+ 801a5ce:	b082      	sub	sp, #8
+ 801a5d0:	af00      	add	r7, sp, #0
+ 801a5d2:	6078      	str	r0, [r7, #4]
+  LWIP_ASSERT("tcp_input_delayed_close: invalid pcb", pcb != NULL);
+ 801a5d4:	687b      	ldr	r3, [r7, #4]
+ 801a5d6:	2b00      	cmp	r3, #0
+ 801a5d8:	d106      	bne.n	801a5e8 <tcp_input_delayed_close+0x1c>
+ 801a5da:	4b17      	ldr	r3, [pc, #92]	; (801a638 <tcp_input_delayed_close+0x6c>)
+ 801a5dc:	f240 225a 	movw	r2, #602	; 0x25a
+ 801a5e0:	4916      	ldr	r1, [pc, #88]	; (801a63c <tcp_input_delayed_close+0x70>)
+ 801a5e2:	4817      	ldr	r0, [pc, #92]	; (801a640 <tcp_input_delayed_close+0x74>)
+ 801a5e4:	f007 f9d0 	bl	8021988 <iprintf>
+
+  if (recv_flags & TF_CLOSED) {
+ 801a5e8:	4b16      	ldr	r3, [pc, #88]	; (801a644 <tcp_input_delayed_close+0x78>)
+ 801a5ea:	781b      	ldrb	r3, [r3, #0]
+ 801a5ec:	f003 0310 	and.w	r3, r3, #16
+ 801a5f0:	2b00      	cmp	r3, #0
+ 801a5f2:	d01c      	beq.n	801a62e <tcp_input_delayed_close+0x62>
+    /* The connection has been closed and we will deallocate the
+        PCB. */
+    if (!(pcb->flags & TF_RXCLOSED)) {
+ 801a5f4:	687b      	ldr	r3, [r7, #4]
+ 801a5f6:	8b5b      	ldrh	r3, [r3, #26]
+ 801a5f8:	f003 0310 	and.w	r3, r3, #16
+ 801a5fc:	2b00      	cmp	r3, #0
+ 801a5fe:	d10d      	bne.n	801a61c <tcp_input_delayed_close+0x50>
+      /* Connection closed although the application has only shut down the
+          tx side: call the PCB's err callback and indicate the closure to
+          ensure the application doesn't continue using the PCB. */
+      TCP_EVENT_ERR(pcb->state, pcb->errf, pcb->callback_arg, ERR_CLSD);
+ 801a600:	687b      	ldr	r3, [r7, #4]
+ 801a602:	f8d3 3090 	ldr.w	r3, [r3, #144]	; 0x90
+ 801a606:	2b00      	cmp	r3, #0
+ 801a608:	d008      	beq.n	801a61c <tcp_input_delayed_close+0x50>
+ 801a60a:	687b      	ldr	r3, [r7, #4]
+ 801a60c:	f8d3 3090 	ldr.w	r3, [r3, #144]	; 0x90
+ 801a610:	687a      	ldr	r2, [r7, #4]
+ 801a612:	6912      	ldr	r2, [r2, #16]
+ 801a614:	f06f 010e 	mvn.w	r1, #14
+ 801a618:	4610      	mov	r0, r2
+ 801a61a:	4798      	blx	r3
+    }
+    tcp_pcb_remove(&tcp_active_pcbs, pcb);
+ 801a61c:	6879      	ldr	r1, [r7, #4]
+ 801a61e:	480a      	ldr	r0, [pc, #40]	; (801a648 <tcp_input_delayed_close+0x7c>)
+ 801a620:	f7ff fa4a 	bl	8019ab8 <tcp_pcb_remove>
+    tcp_free(pcb);
+ 801a624:	6878      	ldr	r0, [r7, #4]
+ 801a626:	f7fd fd13 	bl	8018050 <tcp_free>
+    return 1;
+ 801a62a:	2301      	movs	r3, #1
+ 801a62c:	e000      	b.n	801a630 <tcp_input_delayed_close+0x64>
+  }
+  return 0;
+ 801a62e:	2300      	movs	r3, #0
+}
+ 801a630:	4618      	mov	r0, r3
+ 801a632:	3708      	adds	r7, #8
+ 801a634:	46bd      	mov	sp, r7
+ 801a636:	bd80      	pop	{r7, pc}
+ 801a638:	08025338 	.word	0x08025338
+ 801a63c:	08025508 	.word	0x08025508
+ 801a640:	08025384 	.word	0x08025384
+ 801a644:	2401a4c9 	.word	0x2401a4c9
+ 801a648:	2401a48c 	.word	0x2401a48c
+
+0801a64c <tcp_listen_input>:
+ * @note the segment which arrived is saved in global variables, therefore only the pcb
+ *       involved is passed as a parameter to this function
+ */
+static void
+tcp_listen_input(struct tcp_pcb_listen *pcb)
+{
+ 801a64c:	b590      	push	{r4, r7, lr}
+ 801a64e:	b08b      	sub	sp, #44	; 0x2c
+ 801a650:	af04      	add	r7, sp, #16
+ 801a652:	6078      	str	r0, [r7, #4]
+  struct tcp_pcb *npcb;
+  u32_t iss;
+  err_t rc;
+
+  if (flags & TCP_RST) {
+ 801a654:	4b6f      	ldr	r3, [pc, #444]	; (801a814 <tcp_listen_input+0x1c8>)
+ 801a656:	781b      	ldrb	r3, [r3, #0]
+ 801a658:	f003 0304 	and.w	r3, r3, #4
+ 801a65c:	2b00      	cmp	r3, #0
+ 801a65e:	f040 80d2 	bne.w	801a806 <tcp_listen_input+0x1ba>
+    /* An incoming RST should be ignored. Return. */
+    return;
+  }
+
+  LWIP_ASSERT("tcp_listen_input: invalid pcb", pcb != NULL);
+ 801a662:	687b      	ldr	r3, [r7, #4]
+ 801a664:	2b00      	cmp	r3, #0
+ 801a666:	d106      	bne.n	801a676 <tcp_listen_input+0x2a>
+ 801a668:	4b6b      	ldr	r3, [pc, #428]	; (801a818 <tcp_listen_input+0x1cc>)
+ 801a66a:	f240 2281 	movw	r2, #641	; 0x281
+ 801a66e:	496b      	ldr	r1, [pc, #428]	; (801a81c <tcp_listen_input+0x1d0>)
+ 801a670:	486b      	ldr	r0, [pc, #428]	; (801a820 <tcp_listen_input+0x1d4>)
+ 801a672:	f007 f989 	bl	8021988 <iprintf>
+
+  /* In the LISTEN state, we check for incoming SYN segments,
+     creates a new PCB, and responds with a SYN|ACK. */
+  if (flags & TCP_ACK) {
+ 801a676:	4b67      	ldr	r3, [pc, #412]	; (801a814 <tcp_listen_input+0x1c8>)
+ 801a678:	781b      	ldrb	r3, [r3, #0]
+ 801a67a:	f003 0310 	and.w	r3, r3, #16
+ 801a67e:	2b00      	cmp	r3, #0
+ 801a680:	d019      	beq.n	801a6b6 <tcp_listen_input+0x6a>
+    /* For incoming segments with the ACK flag set, respond with a
+       RST. */
+    LWIP_DEBUGF(TCP_RST_DEBUG, ("tcp_listen_input: ACK in LISTEN, sending reset\n"));
+    tcp_rst((const struct tcp_pcb *)pcb, ackno, seqno + tcplen, ip_current_dest_addr(),
+ 801a682:	4b68      	ldr	r3, [pc, #416]	; (801a824 <tcp_listen_input+0x1d8>)
+ 801a684:	6819      	ldr	r1, [r3, #0]
+ 801a686:	4b68      	ldr	r3, [pc, #416]	; (801a828 <tcp_listen_input+0x1dc>)
+ 801a688:	881b      	ldrh	r3, [r3, #0]
+ 801a68a:	461a      	mov	r2, r3
+ 801a68c:	4b67      	ldr	r3, [pc, #412]	; (801a82c <tcp_listen_input+0x1e0>)
+ 801a68e:	681b      	ldr	r3, [r3, #0]
+ 801a690:	18d0      	adds	r0, r2, r3
+            ip_current_src_addr(), tcphdr->dest, tcphdr->src);
+ 801a692:	4b67      	ldr	r3, [pc, #412]	; (801a830 <tcp_listen_input+0x1e4>)
+ 801a694:	681b      	ldr	r3, [r3, #0]
+    tcp_rst((const struct tcp_pcb *)pcb, ackno, seqno + tcplen, ip_current_dest_addr(),
+ 801a696:	885b      	ldrh	r3, [r3, #2]
+ 801a698:	b29b      	uxth	r3, r3
+            ip_current_src_addr(), tcphdr->dest, tcphdr->src);
+ 801a69a:	4a65      	ldr	r2, [pc, #404]	; (801a830 <tcp_listen_input+0x1e4>)
+ 801a69c:	6812      	ldr	r2, [r2, #0]
+    tcp_rst((const struct tcp_pcb *)pcb, ackno, seqno + tcplen, ip_current_dest_addr(),
+ 801a69e:	8812      	ldrh	r2, [r2, #0]
+ 801a6a0:	b292      	uxth	r2, r2
+ 801a6a2:	9202      	str	r2, [sp, #8]
+ 801a6a4:	9301      	str	r3, [sp, #4]
+ 801a6a6:	4b63      	ldr	r3, [pc, #396]	; (801a834 <tcp_listen_input+0x1e8>)
+ 801a6a8:	9300      	str	r3, [sp, #0]
+ 801a6aa:	4b63      	ldr	r3, [pc, #396]	; (801a838 <tcp_listen_input+0x1ec>)
+ 801a6ac:	4602      	mov	r2, r0
+ 801a6ae:	6878      	ldr	r0, [r7, #4]
+ 801a6b0:	f003 fc44 	bl	801df3c <tcp_rst>
+      tcp_abandon(npcb, 0);
+      return;
+    }
+    tcp_output(npcb);
+  }
+  return;
+ 801a6b4:	e0a9      	b.n	801a80a <tcp_listen_input+0x1be>
+  } else if (flags & TCP_SYN) {
+ 801a6b6:	4b57      	ldr	r3, [pc, #348]	; (801a814 <tcp_listen_input+0x1c8>)
+ 801a6b8:	781b      	ldrb	r3, [r3, #0]
+ 801a6ba:	f003 0302 	and.w	r3, r3, #2
+ 801a6be:	2b00      	cmp	r3, #0
+ 801a6c0:	f000 80a3 	beq.w	801a80a <tcp_listen_input+0x1be>
+    npcb = tcp_alloc(pcb->prio);
+ 801a6c4:	687b      	ldr	r3, [r7, #4]
+ 801a6c6:	7d5b      	ldrb	r3, [r3, #21]
+ 801a6c8:	4618      	mov	r0, r3
+ 801a6ca:	f7ff f853 	bl	8019774 <tcp_alloc>
+ 801a6ce:	6178      	str	r0, [r7, #20]
+    if (npcb == NULL) {
+ 801a6d0:	697b      	ldr	r3, [r7, #20]
+ 801a6d2:	2b00      	cmp	r3, #0
+ 801a6d4:	d111      	bne.n	801a6fa <tcp_listen_input+0xae>
+      TCP_EVENT_ACCEPT(pcb, NULL, pcb->callback_arg, ERR_MEM, err);
+ 801a6d6:	687b      	ldr	r3, [r7, #4]
+ 801a6d8:	699b      	ldr	r3, [r3, #24]
+ 801a6da:	2b00      	cmp	r3, #0
+ 801a6dc:	d00a      	beq.n	801a6f4 <tcp_listen_input+0xa8>
+ 801a6de:	687b      	ldr	r3, [r7, #4]
+ 801a6e0:	699b      	ldr	r3, [r3, #24]
+ 801a6e2:	687a      	ldr	r2, [r7, #4]
+ 801a6e4:	6910      	ldr	r0, [r2, #16]
+ 801a6e6:	f04f 32ff 	mov.w	r2, #4294967295
+ 801a6ea:	2100      	movs	r1, #0
+ 801a6ec:	4798      	blx	r3
+ 801a6ee:	4603      	mov	r3, r0
+ 801a6f0:	73bb      	strb	r3, [r7, #14]
+      return;
+ 801a6f2:	e08b      	b.n	801a80c <tcp_listen_input+0x1c0>
+      TCP_EVENT_ACCEPT(pcb, NULL, pcb->callback_arg, ERR_MEM, err);
+ 801a6f4:	23f0      	movs	r3, #240	; 0xf0
+ 801a6f6:	73bb      	strb	r3, [r7, #14]
+      return;
+ 801a6f8:	e088      	b.n	801a80c <tcp_listen_input+0x1c0>
+    ip_addr_copy(npcb->local_ip, *ip_current_dest_addr());
+ 801a6fa:	4b50      	ldr	r3, [pc, #320]	; (801a83c <tcp_listen_input+0x1f0>)
+ 801a6fc:	695a      	ldr	r2, [r3, #20]
+ 801a6fe:	697b      	ldr	r3, [r7, #20]
+ 801a700:	601a      	str	r2, [r3, #0]
+    ip_addr_copy(npcb->remote_ip, *ip_current_src_addr());
+ 801a702:	4b4e      	ldr	r3, [pc, #312]	; (801a83c <tcp_listen_input+0x1f0>)
+ 801a704:	691a      	ldr	r2, [r3, #16]
+ 801a706:	697b      	ldr	r3, [r7, #20]
+ 801a708:	605a      	str	r2, [r3, #4]
+    npcb->local_port = pcb->local_port;
+ 801a70a:	687b      	ldr	r3, [r7, #4]
+ 801a70c:	8ada      	ldrh	r2, [r3, #22]
+ 801a70e:	697b      	ldr	r3, [r7, #20]
+ 801a710:	82da      	strh	r2, [r3, #22]
+    npcb->remote_port = tcphdr->src;
+ 801a712:	4b47      	ldr	r3, [pc, #284]	; (801a830 <tcp_listen_input+0x1e4>)
+ 801a714:	681b      	ldr	r3, [r3, #0]
+ 801a716:	881b      	ldrh	r3, [r3, #0]
+ 801a718:	b29a      	uxth	r2, r3
+ 801a71a:	697b      	ldr	r3, [r7, #20]
+ 801a71c:	831a      	strh	r2, [r3, #24]
+    npcb->state = SYN_RCVD;
+ 801a71e:	697b      	ldr	r3, [r7, #20]
+ 801a720:	2203      	movs	r2, #3
+ 801a722:	751a      	strb	r2, [r3, #20]
+    npcb->rcv_nxt = seqno + 1;
+ 801a724:	4b41      	ldr	r3, [pc, #260]	; (801a82c <tcp_listen_input+0x1e0>)
+ 801a726:	681b      	ldr	r3, [r3, #0]
+ 801a728:	1c5a      	adds	r2, r3, #1
+ 801a72a:	697b      	ldr	r3, [r7, #20]
+ 801a72c:	625a      	str	r2, [r3, #36]	; 0x24
+    npcb->rcv_ann_right_edge = npcb->rcv_nxt;
+ 801a72e:	697b      	ldr	r3, [r7, #20]
+ 801a730:	6a5a      	ldr	r2, [r3, #36]	; 0x24
+ 801a732:	697b      	ldr	r3, [r7, #20]
+ 801a734:	62da      	str	r2, [r3, #44]	; 0x2c
+    iss = tcp_next_iss(npcb);
+ 801a736:	6978      	ldr	r0, [r7, #20]
+ 801a738:	f7ff fa52 	bl	8019be0 <tcp_next_iss>
+ 801a73c:	6138      	str	r0, [r7, #16]
+    npcb->snd_wl2 = iss;
+ 801a73e:	697b      	ldr	r3, [r7, #20]
+ 801a740:	693a      	ldr	r2, [r7, #16]
+ 801a742:	659a      	str	r2, [r3, #88]	; 0x58
+    npcb->snd_nxt = iss;
+ 801a744:	697b      	ldr	r3, [r7, #20]
+ 801a746:	693a      	ldr	r2, [r7, #16]
+ 801a748:	651a      	str	r2, [r3, #80]	; 0x50
+    npcb->lastack = iss;
+ 801a74a:	697b      	ldr	r3, [r7, #20]
+ 801a74c:	693a      	ldr	r2, [r7, #16]
+ 801a74e:	645a      	str	r2, [r3, #68]	; 0x44
+    npcb->snd_lbb = iss;
+ 801a750:	697b      	ldr	r3, [r7, #20]
+ 801a752:	693a      	ldr	r2, [r7, #16]
+ 801a754:	65da      	str	r2, [r3, #92]	; 0x5c
+    npcb->snd_wl1 = seqno - 1;/* initialise to seqno-1 to force window update */
+ 801a756:	4b35      	ldr	r3, [pc, #212]	; (801a82c <tcp_listen_input+0x1e0>)
+ 801a758:	681b      	ldr	r3, [r3, #0]
+ 801a75a:	1e5a      	subs	r2, r3, #1
+ 801a75c:	697b      	ldr	r3, [r7, #20]
+ 801a75e:	655a      	str	r2, [r3, #84]	; 0x54
+    npcb->callback_arg = pcb->callback_arg;
+ 801a760:	687b      	ldr	r3, [r7, #4]
+ 801a762:	691a      	ldr	r2, [r3, #16]
+ 801a764:	697b      	ldr	r3, [r7, #20]
+ 801a766:	611a      	str	r2, [r3, #16]
+    npcb->listener = pcb;
+ 801a768:	697b      	ldr	r3, [r7, #20]
+ 801a76a:	687a      	ldr	r2, [r7, #4]
+ 801a76c:	67da      	str	r2, [r3, #124]	; 0x7c
+    npcb->so_options = pcb->so_options & SOF_INHERITED;
+ 801a76e:	687b      	ldr	r3, [r7, #4]
+ 801a770:	7a5b      	ldrb	r3, [r3, #9]
+ 801a772:	f003 030c 	and.w	r3, r3, #12
+ 801a776:	b2da      	uxtb	r2, r3
+ 801a778:	697b      	ldr	r3, [r7, #20]
+ 801a77a:	725a      	strb	r2, [r3, #9]
+    npcb->netif_idx = pcb->netif_idx;
+ 801a77c:	687b      	ldr	r3, [r7, #4]
+ 801a77e:	7a1a      	ldrb	r2, [r3, #8]
+ 801a780:	697b      	ldr	r3, [r7, #20]
+ 801a782:	721a      	strb	r2, [r3, #8]
+    TCP_REG_ACTIVE(npcb);
+ 801a784:	4b2e      	ldr	r3, [pc, #184]	; (801a840 <tcp_listen_input+0x1f4>)
+ 801a786:	681a      	ldr	r2, [r3, #0]
+ 801a788:	697b      	ldr	r3, [r7, #20]
+ 801a78a:	60da      	str	r2, [r3, #12]
+ 801a78c:	4a2c      	ldr	r2, [pc, #176]	; (801a840 <tcp_listen_input+0x1f4>)
+ 801a78e:	697b      	ldr	r3, [r7, #20]
+ 801a790:	6013      	str	r3, [r2, #0]
+ 801a792:	f003 fd95 	bl	801e2c0 <tcp_timer_needed>
+ 801a796:	4b2b      	ldr	r3, [pc, #172]	; (801a844 <tcp_listen_input+0x1f8>)
+ 801a798:	2201      	movs	r2, #1
+ 801a79a:	701a      	strb	r2, [r3, #0]
+    tcp_parseopt(npcb);
+ 801a79c:	6978      	ldr	r0, [r7, #20]
+ 801a79e:	f001 fd8f 	bl	801c2c0 <tcp_parseopt>
+    npcb->snd_wnd = tcphdr->wnd;
+ 801a7a2:	4b23      	ldr	r3, [pc, #140]	; (801a830 <tcp_listen_input+0x1e4>)
+ 801a7a4:	681b      	ldr	r3, [r3, #0]
+ 801a7a6:	89db      	ldrh	r3, [r3, #14]
+ 801a7a8:	b29a      	uxth	r2, r3
+ 801a7aa:	697b      	ldr	r3, [r7, #20]
+ 801a7ac:	f8a3 2060 	strh.w	r2, [r3, #96]	; 0x60
+    npcb->snd_wnd_max = npcb->snd_wnd;
+ 801a7b0:	697b      	ldr	r3, [r7, #20]
+ 801a7b2:	f8b3 2060 	ldrh.w	r2, [r3, #96]	; 0x60
+ 801a7b6:	697b      	ldr	r3, [r7, #20]
+ 801a7b8:	f8a3 2062 	strh.w	r2, [r3, #98]	; 0x62
+    npcb->mss = tcp_eff_send_mss(npcb->mss, &npcb->local_ip, &npcb->remote_ip);
+ 801a7bc:	697b      	ldr	r3, [r7, #20]
+ 801a7be:	8e5c      	ldrh	r4, [r3, #50]	; 0x32
+ 801a7c0:	697b      	ldr	r3, [r7, #20]
+ 801a7c2:	3304      	adds	r3, #4
+ 801a7c4:	4618      	mov	r0, r3
+ 801a7c6:	f005 fb95 	bl	801fef4 <ip4_route>
+ 801a7ca:	4601      	mov	r1, r0
+ 801a7cc:	697b      	ldr	r3, [r7, #20]
+ 801a7ce:	3304      	adds	r3, #4
+ 801a7d0:	461a      	mov	r2, r3
+ 801a7d2:	4620      	mov	r0, r4
+ 801a7d4:	f7ff fa2a 	bl	8019c2c <tcp_eff_send_mss_netif>
+ 801a7d8:	4603      	mov	r3, r0
+ 801a7da:	461a      	mov	r2, r3
+ 801a7dc:	697b      	ldr	r3, [r7, #20]
+ 801a7de:	865a      	strh	r2, [r3, #50]	; 0x32
+    rc = tcp_enqueue_flags(npcb, TCP_SYN | TCP_ACK);
+ 801a7e0:	2112      	movs	r1, #18
+ 801a7e2:	6978      	ldr	r0, [r7, #20]
+ 801a7e4:	f002 fcfc 	bl	801d1e0 <tcp_enqueue_flags>
+ 801a7e8:	4603      	mov	r3, r0
+ 801a7ea:	73fb      	strb	r3, [r7, #15]
+    if (rc != ERR_OK) {
+ 801a7ec:	f997 300f 	ldrsb.w	r3, [r7, #15]
+ 801a7f0:	2b00      	cmp	r3, #0
+ 801a7f2:	d004      	beq.n	801a7fe <tcp_listen_input+0x1b2>
+      tcp_abandon(npcb, 0);
+ 801a7f4:	2100      	movs	r1, #0
+ 801a7f6:	6978      	ldr	r0, [r7, #20]
+ 801a7f8:	f7fd feb0 	bl	801855c <tcp_abandon>
+      return;
+ 801a7fc:	e006      	b.n	801a80c <tcp_listen_input+0x1c0>
+    tcp_output(npcb);
+ 801a7fe:	6978      	ldr	r0, [r7, #20]
+ 801a800:	f002 fddc 	bl	801d3bc <tcp_output>
+  return;
+ 801a804:	e001      	b.n	801a80a <tcp_listen_input+0x1be>
+    return;
+ 801a806:	bf00      	nop
+ 801a808:	e000      	b.n	801a80c <tcp_listen_input+0x1c0>
+  return;
+ 801a80a:	bf00      	nop
+}
+ 801a80c:	371c      	adds	r7, #28
+ 801a80e:	46bd      	mov	sp, r7
+ 801a810:	bd90      	pop	{r4, r7, pc}
+ 801a812:	bf00      	nop
+ 801a814:	2401a4c8 	.word	0x2401a4c8
+ 801a818:	08025338 	.word	0x08025338
+ 801a81c:	08025530 	.word	0x08025530
+ 801a820:	08025384 	.word	0x08025384
+ 801a824:	2401a4c0 	.word	0x2401a4c0
+ 801a828:	2401a4c6 	.word	0x2401a4c6
+ 801a82c:	2401a4bc 	.word	0x2401a4bc
+ 801a830:	2401a4ac 	.word	0x2401a4ac
+ 801a834:	24013990 	.word	0x24013990
+ 801a838:	24013994 	.word	0x24013994
+ 801a83c:	24013980 	.word	0x24013980
+ 801a840:	2401a48c 	.word	0x2401a48c
+ 801a844:	2401a494 	.word	0x2401a494
+
+0801a848 <tcp_timewait_input>:
+ * @note the segment which arrived is saved in global variables, therefore only the pcb
+ *       involved is passed as a parameter to this function
+ */
+static void
+tcp_timewait_input(struct tcp_pcb *pcb)
+{
+ 801a848:	b580      	push	{r7, lr}
+ 801a84a:	b086      	sub	sp, #24
+ 801a84c:	af04      	add	r7, sp, #16
+ 801a84e:	6078      	str	r0, [r7, #4]
+  /* RFC 1337: in TIME_WAIT, ignore RST and ACK FINs + any 'acceptable' segments */
+  /* RFC 793 3.9 Event Processing - Segment Arrives:
+   * - first check sequence number - we skip that one in TIME_WAIT (always
+   *   acceptable since we only send ACKs)
+   * - second check the RST bit (... return) */
+  if (flags & TCP_RST) {
+ 801a850:	4b2f      	ldr	r3, [pc, #188]	; (801a910 <tcp_timewait_input+0xc8>)
+ 801a852:	781b      	ldrb	r3, [r3, #0]
+ 801a854:	f003 0304 	and.w	r3, r3, #4
+ 801a858:	2b00      	cmp	r3, #0
+ 801a85a:	d153      	bne.n	801a904 <tcp_timewait_input+0xbc>
+    return;
+  }
+
+  LWIP_ASSERT("tcp_timewait_input: invalid pcb", pcb != NULL);
+ 801a85c:	687b      	ldr	r3, [r7, #4]
+ 801a85e:	2b00      	cmp	r3, #0
+ 801a860:	d106      	bne.n	801a870 <tcp_timewait_input+0x28>
+ 801a862:	4b2c      	ldr	r3, [pc, #176]	; (801a914 <tcp_timewait_input+0xcc>)
+ 801a864:	f240 22ee 	movw	r2, #750	; 0x2ee
+ 801a868:	492b      	ldr	r1, [pc, #172]	; (801a918 <tcp_timewait_input+0xd0>)
+ 801a86a:	482c      	ldr	r0, [pc, #176]	; (801a91c <tcp_timewait_input+0xd4>)
+ 801a86c:	f007 f88c 	bl	8021988 <iprintf>
+
+  /* - fourth, check the SYN bit, */
+  if (flags & TCP_SYN) {
+ 801a870:	4b27      	ldr	r3, [pc, #156]	; (801a910 <tcp_timewait_input+0xc8>)
+ 801a872:	781b      	ldrb	r3, [r3, #0]
+ 801a874:	f003 0302 	and.w	r3, r3, #2
+ 801a878:	2b00      	cmp	r3, #0
+ 801a87a:	d02a      	beq.n	801a8d2 <tcp_timewait_input+0x8a>
+    /* If an incoming segment is not acceptable, an acknowledgment
+       should be sent in reply */
+    if (TCP_SEQ_BETWEEN(seqno, pcb->rcv_nxt, pcb->rcv_nxt + pcb->rcv_wnd)) {
+ 801a87c:	4b28      	ldr	r3, [pc, #160]	; (801a920 <tcp_timewait_input+0xd8>)
+ 801a87e:	681a      	ldr	r2, [r3, #0]
+ 801a880:	687b      	ldr	r3, [r7, #4]
+ 801a882:	6a5b      	ldr	r3, [r3, #36]	; 0x24
+ 801a884:	1ad3      	subs	r3, r2, r3
+ 801a886:	2b00      	cmp	r3, #0
+ 801a888:	db2d      	blt.n	801a8e6 <tcp_timewait_input+0x9e>
+ 801a88a:	4b25      	ldr	r3, [pc, #148]	; (801a920 <tcp_timewait_input+0xd8>)
+ 801a88c:	681a      	ldr	r2, [r3, #0]
+ 801a88e:	687b      	ldr	r3, [r7, #4]
+ 801a890:	6a5b      	ldr	r3, [r3, #36]	; 0x24
+ 801a892:	6879      	ldr	r1, [r7, #4]
+ 801a894:	8d09      	ldrh	r1, [r1, #40]	; 0x28
+ 801a896:	440b      	add	r3, r1
+ 801a898:	1ad3      	subs	r3, r2, r3
+ 801a89a:	2b00      	cmp	r3, #0
+ 801a89c:	dc23      	bgt.n	801a8e6 <tcp_timewait_input+0x9e>
+      /* If the SYN is in the window it is an error, send a reset */
+      tcp_rst(pcb, ackno, seqno + tcplen, ip_current_dest_addr(),
+ 801a89e:	4b21      	ldr	r3, [pc, #132]	; (801a924 <tcp_timewait_input+0xdc>)
+ 801a8a0:	6819      	ldr	r1, [r3, #0]
+ 801a8a2:	4b21      	ldr	r3, [pc, #132]	; (801a928 <tcp_timewait_input+0xe0>)
+ 801a8a4:	881b      	ldrh	r3, [r3, #0]
+ 801a8a6:	461a      	mov	r2, r3
+ 801a8a8:	4b1d      	ldr	r3, [pc, #116]	; (801a920 <tcp_timewait_input+0xd8>)
+ 801a8aa:	681b      	ldr	r3, [r3, #0]
+ 801a8ac:	18d0      	adds	r0, r2, r3
+              ip_current_src_addr(), tcphdr->dest, tcphdr->src);
+ 801a8ae:	4b1f      	ldr	r3, [pc, #124]	; (801a92c <tcp_timewait_input+0xe4>)
+ 801a8b0:	681b      	ldr	r3, [r3, #0]
+      tcp_rst(pcb, ackno, seqno + tcplen, ip_current_dest_addr(),
+ 801a8b2:	885b      	ldrh	r3, [r3, #2]
+ 801a8b4:	b29b      	uxth	r3, r3
+              ip_current_src_addr(), tcphdr->dest, tcphdr->src);
+ 801a8b6:	4a1d      	ldr	r2, [pc, #116]	; (801a92c <tcp_timewait_input+0xe4>)
+ 801a8b8:	6812      	ldr	r2, [r2, #0]
+      tcp_rst(pcb, ackno, seqno + tcplen, ip_current_dest_addr(),
+ 801a8ba:	8812      	ldrh	r2, [r2, #0]
+ 801a8bc:	b292      	uxth	r2, r2
+ 801a8be:	9202      	str	r2, [sp, #8]
+ 801a8c0:	9301      	str	r3, [sp, #4]
+ 801a8c2:	4b1b      	ldr	r3, [pc, #108]	; (801a930 <tcp_timewait_input+0xe8>)
+ 801a8c4:	9300      	str	r3, [sp, #0]
+ 801a8c6:	4b1b      	ldr	r3, [pc, #108]	; (801a934 <tcp_timewait_input+0xec>)
+ 801a8c8:	4602      	mov	r2, r0
+ 801a8ca:	6878      	ldr	r0, [r7, #4]
+ 801a8cc:	f003 fb36 	bl	801df3c <tcp_rst>
+      return;
+ 801a8d0:	e01b      	b.n	801a90a <tcp_timewait_input+0xc2>
+    }
+  } else if (flags & TCP_FIN) {
+ 801a8d2:	4b0f      	ldr	r3, [pc, #60]	; (801a910 <tcp_timewait_input+0xc8>)
+ 801a8d4:	781b      	ldrb	r3, [r3, #0]
+ 801a8d6:	f003 0301 	and.w	r3, r3, #1
+ 801a8da:	2b00      	cmp	r3, #0
+ 801a8dc:	d003      	beq.n	801a8e6 <tcp_timewait_input+0x9e>
+    /* - eighth, check the FIN bit: Remain in the TIME-WAIT state.
+         Restart the 2 MSL time-wait timeout.*/
+    pcb->tmr = tcp_ticks;
+ 801a8de:	4b16      	ldr	r3, [pc, #88]	; (801a938 <tcp_timewait_input+0xf0>)
+ 801a8e0:	681a      	ldr	r2, [r3, #0]
+ 801a8e2:	687b      	ldr	r3, [r7, #4]
+ 801a8e4:	621a      	str	r2, [r3, #32]
+  }
+
+  if ((tcplen > 0)) {
+ 801a8e6:	4b10      	ldr	r3, [pc, #64]	; (801a928 <tcp_timewait_input+0xe0>)
+ 801a8e8:	881b      	ldrh	r3, [r3, #0]
+ 801a8ea:	2b00      	cmp	r3, #0
+ 801a8ec:	d00c      	beq.n	801a908 <tcp_timewait_input+0xc0>
+    /* Acknowledge data, FIN or out-of-window SYN */
+    tcp_ack_now(pcb);
+ 801a8ee:	687b      	ldr	r3, [r7, #4]
+ 801a8f0:	8b5b      	ldrh	r3, [r3, #26]
+ 801a8f2:	f043 0302 	orr.w	r3, r3, #2
+ 801a8f6:	b29a      	uxth	r2, r3
+ 801a8f8:	687b      	ldr	r3, [r7, #4]
+ 801a8fa:	835a      	strh	r2, [r3, #26]
+    tcp_output(pcb);
+ 801a8fc:	6878      	ldr	r0, [r7, #4]
+ 801a8fe:	f002 fd5d 	bl	801d3bc <tcp_output>
+  }
+  return;
+ 801a902:	e001      	b.n	801a908 <tcp_timewait_input+0xc0>
+    return;
+ 801a904:	bf00      	nop
+ 801a906:	e000      	b.n	801a90a <tcp_timewait_input+0xc2>
+  return;
+ 801a908:	bf00      	nop
+}
+ 801a90a:	3708      	adds	r7, #8
+ 801a90c:	46bd      	mov	sp, r7
+ 801a90e:	bd80      	pop	{r7, pc}
+ 801a910:	2401a4c8 	.word	0x2401a4c8
+ 801a914:	08025338 	.word	0x08025338
+ 801a918:	08025550 	.word	0x08025550
+ 801a91c:	08025384 	.word	0x08025384
+ 801a920:	2401a4bc 	.word	0x2401a4bc
+ 801a924:	2401a4c0 	.word	0x2401a4c0
+ 801a928:	2401a4c6 	.word	0x2401a4c6
+ 801a92c:	2401a4ac 	.word	0x2401a4ac
+ 801a930:	24013990 	.word	0x24013990
+ 801a934:	24013994 	.word	0x24013994
+ 801a938:	2401a480 	.word	0x2401a480
+
+0801a93c <tcp_process>:
+ * @note the segment which arrived is saved in global variables, therefore only the pcb
+ *       involved is passed as a parameter to this function
+ */
+static err_t
+tcp_process(struct tcp_pcb *pcb)
+{
+ 801a93c:	b590      	push	{r4, r7, lr}
+ 801a93e:	b08d      	sub	sp, #52	; 0x34
+ 801a940:	af04      	add	r7, sp, #16
+ 801a942:	6078      	str	r0, [r7, #4]
+  struct tcp_seg *rseg;
+  u8_t acceptable = 0;
+ 801a944:	2300      	movs	r3, #0
+ 801a946:	77fb      	strb	r3, [r7, #31]
+  err_t err;
+
+  err = ERR_OK;
+ 801a948:	2300      	movs	r3, #0
+ 801a94a:	77bb      	strb	r3, [r7, #30]
+
+  LWIP_ASSERT("tcp_process: invalid pcb", pcb != NULL);
+ 801a94c:	687b      	ldr	r3, [r7, #4]
+ 801a94e:	2b00      	cmp	r3, #0
+ 801a950:	d106      	bne.n	801a960 <tcp_process+0x24>
+ 801a952:	4b9d      	ldr	r3, [pc, #628]	; (801abc8 <tcp_process+0x28c>)
+ 801a954:	f44f 7247 	mov.w	r2, #796	; 0x31c
+ 801a958:	499c      	ldr	r1, [pc, #624]	; (801abcc <tcp_process+0x290>)
+ 801a95a:	489d      	ldr	r0, [pc, #628]	; (801abd0 <tcp_process+0x294>)
+ 801a95c:	f007 f814 	bl	8021988 <iprintf>
+
+  /* Process incoming RST segments. */
+  if (flags & TCP_RST) {
+ 801a960:	4b9c      	ldr	r3, [pc, #624]	; (801abd4 <tcp_process+0x298>)
+ 801a962:	781b      	ldrb	r3, [r3, #0]
+ 801a964:	f003 0304 	and.w	r3, r3, #4
+ 801a968:	2b00      	cmp	r3, #0
+ 801a96a:	d04e      	beq.n	801aa0a <tcp_process+0xce>
+    /* First, determine if the reset is acceptable. */
+    if (pcb->state == SYN_SENT) {
+ 801a96c:	687b      	ldr	r3, [r7, #4]
+ 801a96e:	7d1b      	ldrb	r3, [r3, #20]
+ 801a970:	2b02      	cmp	r3, #2
+ 801a972:	d108      	bne.n	801a986 <tcp_process+0x4a>
+      /* "In the SYN-SENT state (a RST received in response to an initial SYN),
+          the RST is acceptable if the ACK field acknowledges the SYN." */
+      if (ackno == pcb->snd_nxt) {
+ 801a974:	687b      	ldr	r3, [r7, #4]
+ 801a976:	6d1a      	ldr	r2, [r3, #80]	; 0x50
+ 801a978:	4b97      	ldr	r3, [pc, #604]	; (801abd8 <tcp_process+0x29c>)
+ 801a97a:	681b      	ldr	r3, [r3, #0]
+ 801a97c:	429a      	cmp	r2, r3
+ 801a97e:	d123      	bne.n	801a9c8 <tcp_process+0x8c>
+        acceptable = 1;
+ 801a980:	2301      	movs	r3, #1
+ 801a982:	77fb      	strb	r3, [r7, #31]
+ 801a984:	e020      	b.n	801a9c8 <tcp_process+0x8c>
+      }
+    } else {
+      /* "In all states except SYN-SENT, all reset (RST) segments are validated
+          by checking their SEQ-fields." */
+      if (seqno == pcb->rcv_nxt) {
+ 801a986:	687b      	ldr	r3, [r7, #4]
+ 801a988:	6a5a      	ldr	r2, [r3, #36]	; 0x24
+ 801a98a:	4b94      	ldr	r3, [pc, #592]	; (801abdc <tcp_process+0x2a0>)
+ 801a98c:	681b      	ldr	r3, [r3, #0]
+ 801a98e:	429a      	cmp	r2, r3
+ 801a990:	d102      	bne.n	801a998 <tcp_process+0x5c>
+        acceptable = 1;
+ 801a992:	2301      	movs	r3, #1
+ 801a994:	77fb      	strb	r3, [r7, #31]
+ 801a996:	e017      	b.n	801a9c8 <tcp_process+0x8c>
+      } else  if (TCP_SEQ_BETWEEN(seqno, pcb->rcv_nxt,
+ 801a998:	4b90      	ldr	r3, [pc, #576]	; (801abdc <tcp_process+0x2a0>)
+ 801a99a:	681a      	ldr	r2, [r3, #0]
+ 801a99c:	687b      	ldr	r3, [r7, #4]
+ 801a99e:	6a5b      	ldr	r3, [r3, #36]	; 0x24
+ 801a9a0:	1ad3      	subs	r3, r2, r3
+ 801a9a2:	2b00      	cmp	r3, #0
+ 801a9a4:	db10      	blt.n	801a9c8 <tcp_process+0x8c>
+ 801a9a6:	4b8d      	ldr	r3, [pc, #564]	; (801abdc <tcp_process+0x2a0>)
+ 801a9a8:	681a      	ldr	r2, [r3, #0]
+ 801a9aa:	687b      	ldr	r3, [r7, #4]
+ 801a9ac:	6a5b      	ldr	r3, [r3, #36]	; 0x24
+ 801a9ae:	6879      	ldr	r1, [r7, #4]
+ 801a9b0:	8d09      	ldrh	r1, [r1, #40]	; 0x28
+ 801a9b2:	440b      	add	r3, r1
+ 801a9b4:	1ad3      	subs	r3, r2, r3
+ 801a9b6:	2b00      	cmp	r3, #0
+ 801a9b8:	dc06      	bgt.n	801a9c8 <tcp_process+0x8c>
+                                  pcb->rcv_nxt + pcb->rcv_wnd)) {
+        /* If the sequence number is inside the window, we send a challenge ACK
+           and wait for a re-send with matching sequence number.
+           This follows RFC 5961 section 3.2 and addresses CVE-2004-0230
+           (RST spoofing attack), which is present in RFC 793 RST handling. */
+        tcp_ack_now(pcb);
+ 801a9ba:	687b      	ldr	r3, [r7, #4]
+ 801a9bc:	8b5b      	ldrh	r3, [r3, #26]
+ 801a9be:	f043 0302 	orr.w	r3, r3, #2
+ 801a9c2:	b29a      	uxth	r2, r3
+ 801a9c4:	687b      	ldr	r3, [r7, #4]
+ 801a9c6:	835a      	strh	r2, [r3, #26]
+      }
+    }
+
+    if (acceptable) {
+ 801a9c8:	7ffb      	ldrb	r3, [r7, #31]
+ 801a9ca:	2b00      	cmp	r3, #0
+ 801a9cc:	d01b      	beq.n	801aa06 <tcp_process+0xca>
+      LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_process: Connection RESET\n"));
+      LWIP_ASSERT("tcp_input: pcb->state != CLOSED", pcb->state != CLOSED);
+ 801a9ce:	687b      	ldr	r3, [r7, #4]
+ 801a9d0:	7d1b      	ldrb	r3, [r3, #20]
+ 801a9d2:	2b00      	cmp	r3, #0
+ 801a9d4:	d106      	bne.n	801a9e4 <tcp_process+0xa8>
+ 801a9d6:	4b7c      	ldr	r3, [pc, #496]	; (801abc8 <tcp_process+0x28c>)
+ 801a9d8:	f44f 724e 	mov.w	r2, #824	; 0x338
+ 801a9dc:	4980      	ldr	r1, [pc, #512]	; (801abe0 <tcp_process+0x2a4>)
+ 801a9de:	487c      	ldr	r0, [pc, #496]	; (801abd0 <tcp_process+0x294>)
+ 801a9e0:	f006 ffd2 	bl	8021988 <iprintf>
+      recv_flags |= TF_RESET;
+ 801a9e4:	4b7f      	ldr	r3, [pc, #508]	; (801abe4 <tcp_process+0x2a8>)
+ 801a9e6:	781b      	ldrb	r3, [r3, #0]
+ 801a9e8:	f043 0308 	orr.w	r3, r3, #8
+ 801a9ec:	b2da      	uxtb	r2, r3
+ 801a9ee:	4b7d      	ldr	r3, [pc, #500]	; (801abe4 <tcp_process+0x2a8>)
+ 801a9f0:	701a      	strb	r2, [r3, #0]
+      tcp_clear_flags(pcb, TF_ACK_DELAY);
+ 801a9f2:	687b      	ldr	r3, [r7, #4]
+ 801a9f4:	8b5b      	ldrh	r3, [r3, #26]
+ 801a9f6:	f023 0301 	bic.w	r3, r3, #1
+ 801a9fa:	b29a      	uxth	r2, r3
+ 801a9fc:	687b      	ldr	r3, [r7, #4]
+ 801a9fe:	835a      	strh	r2, [r3, #26]
+      return ERR_RST;
+ 801aa00:	f06f 030d 	mvn.w	r3, #13
+ 801aa04:	e37a      	b.n	801b0fc <tcp_process+0x7c0>
+    } else {
+      LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_process: unacceptable reset seqno %"U32_F" rcv_nxt %"U32_F"\n",
+                                    seqno, pcb->rcv_nxt));
+      LWIP_DEBUGF(TCP_DEBUG, ("tcp_process: unacceptable reset seqno %"U32_F" rcv_nxt %"U32_F"\n",
+                              seqno, pcb->rcv_nxt));
+      return ERR_OK;
+ 801aa06:	2300      	movs	r3, #0
+ 801aa08:	e378      	b.n	801b0fc <tcp_process+0x7c0>
+    }
+  }
+
+  if ((flags & TCP_SYN) && (pcb->state != SYN_SENT && pcb->state != SYN_RCVD)) {
+ 801aa0a:	4b72      	ldr	r3, [pc, #456]	; (801abd4 <tcp_process+0x298>)
+ 801aa0c:	781b      	ldrb	r3, [r3, #0]
+ 801aa0e:	f003 0302 	and.w	r3, r3, #2
+ 801aa12:	2b00      	cmp	r3, #0
+ 801aa14:	d010      	beq.n	801aa38 <tcp_process+0xfc>
+ 801aa16:	687b      	ldr	r3, [r7, #4]
+ 801aa18:	7d1b      	ldrb	r3, [r3, #20]
+ 801aa1a:	2b02      	cmp	r3, #2
+ 801aa1c:	d00c      	beq.n	801aa38 <tcp_process+0xfc>
+ 801aa1e:	687b      	ldr	r3, [r7, #4]
+ 801aa20:	7d1b      	ldrb	r3, [r3, #20]
+ 801aa22:	2b03      	cmp	r3, #3
+ 801aa24:	d008      	beq.n	801aa38 <tcp_process+0xfc>
+    /* Cope with new connection attempt after remote end crashed */
+    tcp_ack_now(pcb);
+ 801aa26:	687b      	ldr	r3, [r7, #4]
+ 801aa28:	8b5b      	ldrh	r3, [r3, #26]
+ 801aa2a:	f043 0302 	orr.w	r3, r3, #2
+ 801aa2e:	b29a      	uxth	r2, r3
+ 801aa30:	687b      	ldr	r3, [r7, #4]
+ 801aa32:	835a      	strh	r2, [r3, #26]
+    return ERR_OK;
+ 801aa34:	2300      	movs	r3, #0
+ 801aa36:	e361      	b.n	801b0fc <tcp_process+0x7c0>
+  }
+
+  if ((pcb->flags & TF_RXCLOSED) == 0) {
+ 801aa38:	687b      	ldr	r3, [r7, #4]
+ 801aa3a:	8b5b      	ldrh	r3, [r3, #26]
+ 801aa3c:	f003 0310 	and.w	r3, r3, #16
+ 801aa40:	2b00      	cmp	r3, #0
+ 801aa42:	d103      	bne.n	801aa4c <tcp_process+0x110>
+    /* Update the PCB (in)activity timer unless rx is closed (see tcp_shutdown) */
+    pcb->tmr = tcp_ticks;
+ 801aa44:	4b68      	ldr	r3, [pc, #416]	; (801abe8 <tcp_process+0x2ac>)
+ 801aa46:	681a      	ldr	r2, [r3, #0]
+ 801aa48:	687b      	ldr	r3, [r7, #4]
+ 801aa4a:	621a      	str	r2, [r3, #32]
+  }
+  pcb->keep_cnt_sent = 0;
+ 801aa4c:	687b      	ldr	r3, [r7, #4]
+ 801aa4e:	2200      	movs	r2, #0
+ 801aa50:	f883 209b 	strb.w	r2, [r3, #155]	; 0x9b
+  pcb->persist_probe = 0;
+ 801aa54:	687b      	ldr	r3, [r7, #4]
+ 801aa56:	2200      	movs	r2, #0
+ 801aa58:	f883 209a 	strb.w	r2, [r3, #154]	; 0x9a
+
+  tcp_parseopt(pcb);
+ 801aa5c:	6878      	ldr	r0, [r7, #4]
+ 801aa5e:	f001 fc2f 	bl	801c2c0 <tcp_parseopt>
+
+  /* Do different things depending on the TCP state. */
+  switch (pcb->state) {
+ 801aa62:	687b      	ldr	r3, [r7, #4]
+ 801aa64:	7d1b      	ldrb	r3, [r3, #20]
+ 801aa66:	3b02      	subs	r3, #2
+ 801aa68:	2b07      	cmp	r3, #7
+ 801aa6a:	f200 8337 	bhi.w	801b0dc <tcp_process+0x7a0>
+ 801aa6e:	a201      	add	r2, pc, #4	; (adr r2, 801aa74 <tcp_process+0x138>)
+ 801aa70:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
+ 801aa74:	0801aa95 	.word	0x0801aa95
+ 801aa78:	0801acc5 	.word	0x0801acc5
+ 801aa7c:	0801ae3d 	.word	0x0801ae3d
+ 801aa80:	0801ae67 	.word	0x0801ae67
+ 801aa84:	0801af8b 	.word	0x0801af8b
+ 801aa88:	0801ae3d 	.word	0x0801ae3d
+ 801aa8c:	0801b017 	.word	0x0801b017
+ 801aa90:	0801b0a7 	.word	0x0801b0a7
+    case SYN_SENT:
+      LWIP_DEBUGF(TCP_INPUT_DEBUG, ("SYN-SENT: ackno %"U32_F" pcb->snd_nxt %"U32_F" unacked %"U32_F"\n", ackno,
+                                    pcb->snd_nxt, lwip_ntohl(pcb->unacked->tcphdr->seqno)));
+      /* received SYN ACK with expected sequence number? */
+      if ((flags & TCP_ACK) && (flags & TCP_SYN)
+ 801aa94:	4b4f      	ldr	r3, [pc, #316]	; (801abd4 <tcp_process+0x298>)
+ 801aa96:	781b      	ldrb	r3, [r3, #0]
+ 801aa98:	f003 0310 	and.w	r3, r3, #16
+ 801aa9c:	2b00      	cmp	r3, #0
+ 801aa9e:	f000 80e4 	beq.w	801ac6a <tcp_process+0x32e>
+ 801aaa2:	4b4c      	ldr	r3, [pc, #304]	; (801abd4 <tcp_process+0x298>)
+ 801aaa4:	781b      	ldrb	r3, [r3, #0]
+ 801aaa6:	f003 0302 	and.w	r3, r3, #2
+ 801aaaa:	2b00      	cmp	r3, #0
+ 801aaac:	f000 80dd 	beq.w	801ac6a <tcp_process+0x32e>
+          && (ackno == pcb->lastack + 1)) {
+ 801aab0:	687b      	ldr	r3, [r7, #4]
+ 801aab2:	6c5b      	ldr	r3, [r3, #68]	; 0x44
+ 801aab4:	1c5a      	adds	r2, r3, #1
+ 801aab6:	4b48      	ldr	r3, [pc, #288]	; (801abd8 <tcp_process+0x29c>)
+ 801aab8:	681b      	ldr	r3, [r3, #0]
+ 801aaba:	429a      	cmp	r2, r3
+ 801aabc:	f040 80d5 	bne.w	801ac6a <tcp_process+0x32e>
+        pcb->rcv_nxt = seqno + 1;
+ 801aac0:	4b46      	ldr	r3, [pc, #280]	; (801abdc <tcp_process+0x2a0>)
+ 801aac2:	681b      	ldr	r3, [r3, #0]
+ 801aac4:	1c5a      	adds	r2, r3, #1
+ 801aac6:	687b      	ldr	r3, [r7, #4]
+ 801aac8:	625a      	str	r2, [r3, #36]	; 0x24
+        pcb->rcv_ann_right_edge = pcb->rcv_nxt;
+ 801aaca:	687b      	ldr	r3, [r7, #4]
+ 801aacc:	6a5a      	ldr	r2, [r3, #36]	; 0x24
+ 801aace:	687b      	ldr	r3, [r7, #4]
+ 801aad0:	62da      	str	r2, [r3, #44]	; 0x2c
+        pcb->lastack = ackno;
+ 801aad2:	4b41      	ldr	r3, [pc, #260]	; (801abd8 <tcp_process+0x29c>)
+ 801aad4:	681a      	ldr	r2, [r3, #0]
+ 801aad6:	687b      	ldr	r3, [r7, #4]
+ 801aad8:	645a      	str	r2, [r3, #68]	; 0x44
+        pcb->snd_wnd = tcphdr->wnd;
+ 801aada:	4b44      	ldr	r3, [pc, #272]	; (801abec <tcp_process+0x2b0>)
+ 801aadc:	681b      	ldr	r3, [r3, #0]
+ 801aade:	89db      	ldrh	r3, [r3, #14]
+ 801aae0:	b29a      	uxth	r2, r3
+ 801aae2:	687b      	ldr	r3, [r7, #4]
+ 801aae4:	f8a3 2060 	strh.w	r2, [r3, #96]	; 0x60
+        pcb->snd_wnd_max = pcb->snd_wnd;
+ 801aae8:	687b      	ldr	r3, [r7, #4]
+ 801aaea:	f8b3 2060 	ldrh.w	r2, [r3, #96]	; 0x60
+ 801aaee:	687b      	ldr	r3, [r7, #4]
+ 801aaf0:	f8a3 2062 	strh.w	r2, [r3, #98]	; 0x62
+        pcb->snd_wl1 = seqno - 1; /* initialise to seqno - 1 to force window update */
+ 801aaf4:	4b39      	ldr	r3, [pc, #228]	; (801abdc <tcp_process+0x2a0>)
+ 801aaf6:	681b      	ldr	r3, [r3, #0]
+ 801aaf8:	1e5a      	subs	r2, r3, #1
+ 801aafa:	687b      	ldr	r3, [r7, #4]
+ 801aafc:	655a      	str	r2, [r3, #84]	; 0x54
+        pcb->state = ESTABLISHED;
+ 801aafe:	687b      	ldr	r3, [r7, #4]
+ 801ab00:	2204      	movs	r2, #4
+ 801ab02:	751a      	strb	r2, [r3, #20]
+
+#if TCP_CALCULATE_EFF_SEND_MSS
+        pcb->mss = tcp_eff_send_mss(pcb->mss, &pcb->local_ip, &pcb->remote_ip);
+ 801ab04:	687b      	ldr	r3, [r7, #4]
+ 801ab06:	8e5c      	ldrh	r4, [r3, #50]	; 0x32
+ 801ab08:	687b      	ldr	r3, [r7, #4]
+ 801ab0a:	3304      	adds	r3, #4
+ 801ab0c:	4618      	mov	r0, r3
+ 801ab0e:	f005 f9f1 	bl	801fef4 <ip4_route>
+ 801ab12:	4601      	mov	r1, r0
+ 801ab14:	687b      	ldr	r3, [r7, #4]
+ 801ab16:	3304      	adds	r3, #4
+ 801ab18:	461a      	mov	r2, r3
+ 801ab1a:	4620      	mov	r0, r4
+ 801ab1c:	f7ff f886 	bl	8019c2c <tcp_eff_send_mss_netif>
+ 801ab20:	4603      	mov	r3, r0
+ 801ab22:	461a      	mov	r2, r3
+ 801ab24:	687b      	ldr	r3, [r7, #4]
+ 801ab26:	865a      	strh	r2, [r3, #50]	; 0x32
+#endif /* TCP_CALCULATE_EFF_SEND_MSS */
+
+        pcb->cwnd = LWIP_TCP_CALC_INITIAL_CWND(pcb->mss);
+ 801ab28:	687b      	ldr	r3, [r7, #4]
+ 801ab2a:	8e5b      	ldrh	r3, [r3, #50]	; 0x32
+ 801ab2c:	009a      	lsls	r2, r3, #2
+ 801ab2e:	687b      	ldr	r3, [r7, #4]
+ 801ab30:	8e5b      	ldrh	r3, [r3, #50]	; 0x32
+ 801ab32:	005b      	lsls	r3, r3, #1
+ 801ab34:	f241 111c 	movw	r1, #4380	; 0x111c
+ 801ab38:	428b      	cmp	r3, r1
+ 801ab3a:	bf38      	it	cc
+ 801ab3c:	460b      	movcc	r3, r1
+ 801ab3e:	429a      	cmp	r2, r3
+ 801ab40:	d204      	bcs.n	801ab4c <tcp_process+0x210>
+ 801ab42:	687b      	ldr	r3, [r7, #4]
+ 801ab44:	8e5b      	ldrh	r3, [r3, #50]	; 0x32
+ 801ab46:	009b      	lsls	r3, r3, #2
+ 801ab48:	b29b      	uxth	r3, r3
+ 801ab4a:	e00d      	b.n	801ab68 <tcp_process+0x22c>
+ 801ab4c:	687b      	ldr	r3, [r7, #4]
+ 801ab4e:	8e5b      	ldrh	r3, [r3, #50]	; 0x32
+ 801ab50:	005b      	lsls	r3, r3, #1
+ 801ab52:	f241 121c 	movw	r2, #4380	; 0x111c
+ 801ab56:	4293      	cmp	r3, r2
+ 801ab58:	d904      	bls.n	801ab64 <tcp_process+0x228>
+ 801ab5a:	687b      	ldr	r3, [r7, #4]
+ 801ab5c:	8e5b      	ldrh	r3, [r3, #50]	; 0x32
+ 801ab5e:	005b      	lsls	r3, r3, #1
+ 801ab60:	b29b      	uxth	r3, r3
+ 801ab62:	e001      	b.n	801ab68 <tcp_process+0x22c>
+ 801ab64:	f241 131c 	movw	r3, #4380	; 0x111c
+ 801ab68:	687a      	ldr	r2, [r7, #4]
+ 801ab6a:	f8a2 3048 	strh.w	r3, [r2, #72]	; 0x48
+        LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_process (SENT): cwnd %"TCPWNDSIZE_F
+                                     " ssthresh %"TCPWNDSIZE_F"\n",
+                                     pcb->cwnd, pcb->ssthresh));
+        LWIP_ASSERT("pcb->snd_queuelen > 0", (pcb->snd_queuelen > 0));
+ 801ab6e:	687b      	ldr	r3, [r7, #4]
+ 801ab70:	f8b3 3066 	ldrh.w	r3, [r3, #102]	; 0x66
+ 801ab74:	2b00      	cmp	r3, #0
+ 801ab76:	d106      	bne.n	801ab86 <tcp_process+0x24a>
+ 801ab78:	4b13      	ldr	r3, [pc, #76]	; (801abc8 <tcp_process+0x28c>)
+ 801ab7a:	f44f 725b 	mov.w	r2, #876	; 0x36c
+ 801ab7e:	491c      	ldr	r1, [pc, #112]	; (801abf0 <tcp_process+0x2b4>)
+ 801ab80:	4813      	ldr	r0, [pc, #76]	; (801abd0 <tcp_process+0x294>)
+ 801ab82:	f006 ff01 	bl	8021988 <iprintf>
+        --pcb->snd_queuelen;
+ 801ab86:	687b      	ldr	r3, [r7, #4]
+ 801ab88:	f8b3 3066 	ldrh.w	r3, [r3, #102]	; 0x66
+ 801ab8c:	3b01      	subs	r3, #1
+ 801ab8e:	b29a      	uxth	r2, r3
+ 801ab90:	687b      	ldr	r3, [r7, #4]
+ 801ab92:	f8a3 2066 	strh.w	r2, [r3, #102]	; 0x66
+        LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_process: SYN-SENT --queuelen %"TCPWNDSIZE_F"\n", (tcpwnd_size_t)pcb->snd_queuelen));
+        rseg = pcb->unacked;
+ 801ab96:	687b      	ldr	r3, [r7, #4]
+ 801ab98:	6f1b      	ldr	r3, [r3, #112]	; 0x70
+ 801ab9a:	617b      	str	r3, [r7, #20]
+        if (rseg == NULL) {
+ 801ab9c:	697b      	ldr	r3, [r7, #20]
+ 801ab9e:	2b00      	cmp	r3, #0
+ 801aba0:	d12a      	bne.n	801abf8 <tcp_process+0x2bc>
+          /* might happen if tcp_output fails in tcp_rexmit_rto()
+             in which case the segment is on the unsent list */
+          rseg = pcb->unsent;
+ 801aba2:	687b      	ldr	r3, [r7, #4]
+ 801aba4:	6edb      	ldr	r3, [r3, #108]	; 0x6c
+ 801aba6:	617b      	str	r3, [r7, #20]
+          LWIP_ASSERT("no segment to free", rseg != NULL);
+ 801aba8:	697b      	ldr	r3, [r7, #20]
+ 801abaa:	2b00      	cmp	r3, #0
+ 801abac:	d106      	bne.n	801abbc <tcp_process+0x280>
+ 801abae:	4b06      	ldr	r3, [pc, #24]	; (801abc8 <tcp_process+0x28c>)
+ 801abb0:	f44f 725d 	mov.w	r2, #884	; 0x374
+ 801abb4:	490f      	ldr	r1, [pc, #60]	; (801abf4 <tcp_process+0x2b8>)
+ 801abb6:	4806      	ldr	r0, [pc, #24]	; (801abd0 <tcp_process+0x294>)
+ 801abb8:	f006 fee6 	bl	8021988 <iprintf>
+          pcb->unsent = rseg->next;
+ 801abbc:	697b      	ldr	r3, [r7, #20]
+ 801abbe:	681a      	ldr	r2, [r3, #0]
+ 801abc0:	687b      	ldr	r3, [r7, #4]
+ 801abc2:	66da      	str	r2, [r3, #108]	; 0x6c
+ 801abc4:	e01c      	b.n	801ac00 <tcp_process+0x2c4>
+ 801abc6:	bf00      	nop
+ 801abc8:	08025338 	.word	0x08025338
+ 801abcc:	08025570 	.word	0x08025570
+ 801abd0:	08025384 	.word	0x08025384
+ 801abd4:	2401a4c8 	.word	0x2401a4c8
+ 801abd8:	2401a4c0 	.word	0x2401a4c0
+ 801abdc:	2401a4bc 	.word	0x2401a4bc
+ 801abe0:	0802558c 	.word	0x0802558c
+ 801abe4:	2401a4c9 	.word	0x2401a4c9
+ 801abe8:	2401a480 	.word	0x2401a480
+ 801abec:	2401a4ac 	.word	0x2401a4ac
+ 801abf0:	080255ac 	.word	0x080255ac
+ 801abf4:	080255c4 	.word	0x080255c4
+        } else {
+          pcb->unacked = rseg->next;
+ 801abf8:	697b      	ldr	r3, [r7, #20]
+ 801abfa:	681a      	ldr	r2, [r3, #0]
+ 801abfc:	687b      	ldr	r3, [r7, #4]
+ 801abfe:	671a      	str	r2, [r3, #112]	; 0x70
+        }
+        tcp_seg_free(rseg);
+ 801ac00:	6978      	ldr	r0, [r7, #20]
+ 801ac02:	f7fe fc4e 	bl	80194a2 <tcp_seg_free>
+
+        /* If there's nothing left to acknowledge, stop the retransmit
+           timer, otherwise reset it to start again */
+        if (pcb->unacked == NULL) {
+ 801ac06:	687b      	ldr	r3, [r7, #4]
+ 801ac08:	6f1b      	ldr	r3, [r3, #112]	; 0x70
+ 801ac0a:	2b00      	cmp	r3, #0
+ 801ac0c:	d104      	bne.n	801ac18 <tcp_process+0x2dc>
+          pcb->rtime = -1;
+ 801ac0e:	687b      	ldr	r3, [r7, #4]
+ 801ac10:	f64f 72ff 	movw	r2, #65535	; 0xffff
+ 801ac14:	861a      	strh	r2, [r3, #48]	; 0x30
+ 801ac16:	e006      	b.n	801ac26 <tcp_process+0x2ea>
+        } else {
+          pcb->rtime = 0;
+ 801ac18:	687b      	ldr	r3, [r7, #4]
+ 801ac1a:	2200      	movs	r2, #0
+ 801ac1c:	861a      	strh	r2, [r3, #48]	; 0x30
+          pcb->nrtx = 0;
+ 801ac1e:	687b      	ldr	r3, [r7, #4]
+ 801ac20:	2200      	movs	r2, #0
+ 801ac22:	f883 2042 	strb.w	r2, [r3, #66]	; 0x42
+        }
+
+        /* Call the user specified function to call when successfully
+         * connected. */
+        TCP_EVENT_CONNECTED(pcb, ERR_OK, err);
+ 801ac26:	687b      	ldr	r3, [r7, #4]
+ 801ac28:	f8d3 3088 	ldr.w	r3, [r3, #136]	; 0x88
+ 801ac2c:	2b00      	cmp	r3, #0
+ 801ac2e:	d00a      	beq.n	801ac46 <tcp_process+0x30a>
+ 801ac30:	687b      	ldr	r3, [r7, #4]
+ 801ac32:	f8d3 3088 	ldr.w	r3, [r3, #136]	; 0x88
+ 801ac36:	687a      	ldr	r2, [r7, #4]
+ 801ac38:	6910      	ldr	r0, [r2, #16]
+ 801ac3a:	2200      	movs	r2, #0
+ 801ac3c:	6879      	ldr	r1, [r7, #4]
+ 801ac3e:	4798      	blx	r3
+ 801ac40:	4603      	mov	r3, r0
+ 801ac42:	77bb      	strb	r3, [r7, #30]
+ 801ac44:	e001      	b.n	801ac4a <tcp_process+0x30e>
+ 801ac46:	2300      	movs	r3, #0
+ 801ac48:	77bb      	strb	r3, [r7, #30]
+        if (err == ERR_ABRT) {
+ 801ac4a:	f997 301e 	ldrsb.w	r3, [r7, #30]
+ 801ac4e:	f113 0f0d 	cmn.w	r3, #13
+ 801ac52:	d102      	bne.n	801ac5a <tcp_process+0x31e>
+          return ERR_ABRT;
+ 801ac54:	f06f 030c 	mvn.w	r3, #12
+ 801ac58:	e250      	b.n	801b0fc <tcp_process+0x7c0>
+        }
+        tcp_ack_now(pcb);
+ 801ac5a:	687b      	ldr	r3, [r7, #4]
+ 801ac5c:	8b5b      	ldrh	r3, [r3, #26]
+ 801ac5e:	f043 0302 	orr.w	r3, r3, #2
+ 801ac62:	b29a      	uxth	r2, r3
+ 801ac64:	687b      	ldr	r3, [r7, #4]
+ 801ac66:	835a      	strh	r2, [r3, #26]
+        if (pcb->nrtx < TCP_SYNMAXRTX) {
+          pcb->rtime = 0;
+          tcp_rexmit_rto(pcb);
+        }
+      }
+      break;
+ 801ac68:	e23a      	b.n	801b0e0 <tcp_process+0x7a4>
+      else if (flags & TCP_ACK) {
+ 801ac6a:	4b98      	ldr	r3, [pc, #608]	; (801aecc <tcp_process+0x590>)
+ 801ac6c:	781b      	ldrb	r3, [r3, #0]
+ 801ac6e:	f003 0310 	and.w	r3, r3, #16
+ 801ac72:	2b00      	cmp	r3, #0
+ 801ac74:	f000 8234 	beq.w	801b0e0 <tcp_process+0x7a4>
+        tcp_rst(pcb, ackno, seqno + tcplen, ip_current_dest_addr(),
+ 801ac78:	4b95      	ldr	r3, [pc, #596]	; (801aed0 <tcp_process+0x594>)
+ 801ac7a:	6819      	ldr	r1, [r3, #0]
+ 801ac7c:	4b95      	ldr	r3, [pc, #596]	; (801aed4 <tcp_process+0x598>)
+ 801ac7e:	881b      	ldrh	r3, [r3, #0]
+ 801ac80:	461a      	mov	r2, r3
+ 801ac82:	4b95      	ldr	r3, [pc, #596]	; (801aed8 <tcp_process+0x59c>)
+ 801ac84:	681b      	ldr	r3, [r3, #0]
+ 801ac86:	18d0      	adds	r0, r2, r3
+                ip_current_src_addr(), tcphdr->dest, tcphdr->src);
+ 801ac88:	4b94      	ldr	r3, [pc, #592]	; (801aedc <tcp_process+0x5a0>)
+ 801ac8a:	681b      	ldr	r3, [r3, #0]
+        tcp_rst(pcb, ackno, seqno + tcplen, ip_current_dest_addr(),
+ 801ac8c:	885b      	ldrh	r3, [r3, #2]
+ 801ac8e:	b29b      	uxth	r3, r3
+                ip_current_src_addr(), tcphdr->dest, tcphdr->src);
+ 801ac90:	4a92      	ldr	r2, [pc, #584]	; (801aedc <tcp_process+0x5a0>)
+ 801ac92:	6812      	ldr	r2, [r2, #0]
+        tcp_rst(pcb, ackno, seqno + tcplen, ip_current_dest_addr(),
+ 801ac94:	8812      	ldrh	r2, [r2, #0]
+ 801ac96:	b292      	uxth	r2, r2
+ 801ac98:	9202      	str	r2, [sp, #8]
+ 801ac9a:	9301      	str	r3, [sp, #4]
+ 801ac9c:	4b90      	ldr	r3, [pc, #576]	; (801aee0 <tcp_process+0x5a4>)
+ 801ac9e:	9300      	str	r3, [sp, #0]
+ 801aca0:	4b90      	ldr	r3, [pc, #576]	; (801aee4 <tcp_process+0x5a8>)
+ 801aca2:	4602      	mov	r2, r0
+ 801aca4:	6878      	ldr	r0, [r7, #4]
+ 801aca6:	f003 f949 	bl	801df3c <tcp_rst>
+        if (pcb->nrtx < TCP_SYNMAXRTX) {
+ 801acaa:	687b      	ldr	r3, [r7, #4]
+ 801acac:	f893 3042 	ldrb.w	r3, [r3, #66]	; 0x42
+ 801acb0:	2b05      	cmp	r3, #5
+ 801acb2:	f200 8215 	bhi.w	801b0e0 <tcp_process+0x7a4>
+          pcb->rtime = 0;
+ 801acb6:	687b      	ldr	r3, [r7, #4]
+ 801acb8:	2200      	movs	r2, #0
+ 801acba:	861a      	strh	r2, [r3, #48]	; 0x30
+          tcp_rexmit_rto(pcb);
+ 801acbc:	6878      	ldr	r0, [r7, #4]
+ 801acbe:	f002 ff15 	bl	801daec <tcp_rexmit_rto>
+      break;
+ 801acc2:	e20d      	b.n	801b0e0 <tcp_process+0x7a4>
+    case SYN_RCVD:
+      if (flags & TCP_ACK) {
+ 801acc4:	4b81      	ldr	r3, [pc, #516]	; (801aecc <tcp_process+0x590>)
+ 801acc6:	781b      	ldrb	r3, [r3, #0]
+ 801acc8:	f003 0310 	and.w	r3, r3, #16
+ 801accc:	2b00      	cmp	r3, #0
+ 801acce:	f000 80a1 	beq.w	801ae14 <tcp_process+0x4d8>
+        /* expected ACK number? */
+        if (TCP_SEQ_BETWEEN(ackno, pcb->lastack + 1, pcb->snd_nxt)) {
+ 801acd2:	4b7f      	ldr	r3, [pc, #508]	; (801aed0 <tcp_process+0x594>)
+ 801acd4:	681a      	ldr	r2, [r3, #0]
+ 801acd6:	687b      	ldr	r3, [r7, #4]
+ 801acd8:	6c5b      	ldr	r3, [r3, #68]	; 0x44
+ 801acda:	1ad3      	subs	r3, r2, r3
+ 801acdc:	3b01      	subs	r3, #1
+ 801acde:	2b00      	cmp	r3, #0
+ 801ace0:	db7e      	blt.n	801ade0 <tcp_process+0x4a4>
+ 801ace2:	4b7b      	ldr	r3, [pc, #492]	; (801aed0 <tcp_process+0x594>)
+ 801ace4:	681a      	ldr	r2, [r3, #0]
+ 801ace6:	687b      	ldr	r3, [r7, #4]
+ 801ace8:	6d1b      	ldr	r3, [r3, #80]	; 0x50
+ 801acea:	1ad3      	subs	r3, r2, r3
+ 801acec:	2b00      	cmp	r3, #0
+ 801acee:	dc77      	bgt.n	801ade0 <tcp_process+0x4a4>
+          pcb->state = ESTABLISHED;
+ 801acf0:	687b      	ldr	r3, [r7, #4]
+ 801acf2:	2204      	movs	r2, #4
+ 801acf4:	751a      	strb	r2, [r3, #20]
+          LWIP_DEBUGF(TCP_DEBUG, ("TCP connection established %"U16_F" -> %"U16_F".\n", inseg.tcphdr->src, inseg.tcphdr->dest));
+#if LWIP_CALLBACK_API || TCP_LISTEN_BACKLOG
+          if (pcb->listener == NULL) {
+ 801acf6:	687b      	ldr	r3, [r7, #4]
+ 801acf8:	6fdb      	ldr	r3, [r3, #124]	; 0x7c
+ 801acfa:	2b00      	cmp	r3, #0
+ 801acfc:	d102      	bne.n	801ad04 <tcp_process+0x3c8>
+            /* listen pcb might be closed by now */
+            err = ERR_VAL;
+ 801acfe:	23fa      	movs	r3, #250	; 0xfa
+ 801ad00:	77bb      	strb	r3, [r7, #30]
+ 801ad02:	e01d      	b.n	801ad40 <tcp_process+0x404>
+          } else
+#endif /* LWIP_CALLBACK_API || TCP_LISTEN_BACKLOG */
+          {
+#if LWIP_CALLBACK_API
+            LWIP_ASSERT("pcb->listener->accept != NULL", pcb->listener->accept != NULL);
+ 801ad04:	687b      	ldr	r3, [r7, #4]
+ 801ad06:	6fdb      	ldr	r3, [r3, #124]	; 0x7c
+ 801ad08:	699b      	ldr	r3, [r3, #24]
+ 801ad0a:	2b00      	cmp	r3, #0
+ 801ad0c:	d106      	bne.n	801ad1c <tcp_process+0x3e0>
+ 801ad0e:	4b76      	ldr	r3, [pc, #472]	; (801aee8 <tcp_process+0x5ac>)
+ 801ad10:	f44f 726a 	mov.w	r2, #936	; 0x3a8
+ 801ad14:	4975      	ldr	r1, [pc, #468]	; (801aeec <tcp_process+0x5b0>)
+ 801ad16:	4876      	ldr	r0, [pc, #472]	; (801aef0 <tcp_process+0x5b4>)
+ 801ad18:	f006 fe36 	bl	8021988 <iprintf>
+#endif
+            tcp_backlog_accepted(pcb);
+            /* Call the accept function. */
+            TCP_EVENT_ACCEPT(pcb->listener, pcb, pcb->callback_arg, ERR_OK, err);
+ 801ad1c:	687b      	ldr	r3, [r7, #4]
+ 801ad1e:	6fdb      	ldr	r3, [r3, #124]	; 0x7c
+ 801ad20:	699b      	ldr	r3, [r3, #24]
+ 801ad22:	2b00      	cmp	r3, #0
+ 801ad24:	d00a      	beq.n	801ad3c <tcp_process+0x400>
+ 801ad26:	687b      	ldr	r3, [r7, #4]
+ 801ad28:	6fdb      	ldr	r3, [r3, #124]	; 0x7c
+ 801ad2a:	699b      	ldr	r3, [r3, #24]
+ 801ad2c:	687a      	ldr	r2, [r7, #4]
+ 801ad2e:	6910      	ldr	r0, [r2, #16]
+ 801ad30:	2200      	movs	r2, #0
+ 801ad32:	6879      	ldr	r1, [r7, #4]
+ 801ad34:	4798      	blx	r3
+ 801ad36:	4603      	mov	r3, r0
+ 801ad38:	77bb      	strb	r3, [r7, #30]
+ 801ad3a:	e001      	b.n	801ad40 <tcp_process+0x404>
+ 801ad3c:	23f0      	movs	r3, #240	; 0xf0
+ 801ad3e:	77bb      	strb	r3, [r7, #30]
+          }
+          if (err != ERR_OK) {
+ 801ad40:	f997 301e 	ldrsb.w	r3, [r7, #30]
+ 801ad44:	2b00      	cmp	r3, #0
+ 801ad46:	d00a      	beq.n	801ad5e <tcp_process+0x422>
+            /* If the accept function returns with an error, we abort
+             * the connection. */
+            /* Already aborted? */
+            if (err != ERR_ABRT) {
+ 801ad48:	f997 301e 	ldrsb.w	r3, [r7, #30]
+ 801ad4c:	f113 0f0d 	cmn.w	r3, #13
+ 801ad50:	d002      	beq.n	801ad58 <tcp_process+0x41c>
+              tcp_abort(pcb);
+ 801ad52:	6878      	ldr	r0, [r7, #4]
+ 801ad54:	f7fd fcc0 	bl	80186d8 <tcp_abort>
+            }
+            return ERR_ABRT;
+ 801ad58:	f06f 030c 	mvn.w	r3, #12
+ 801ad5c:	e1ce      	b.n	801b0fc <tcp_process+0x7c0>
+          }
+          /* If there was any data contained within this ACK,
+           * we'd better pass it on to the application as well. */
+          tcp_receive(pcb);
+ 801ad5e:	6878      	ldr	r0, [r7, #4]
+ 801ad60:	f000 fae0 	bl	801b324 <tcp_receive>
+
+          /* Prevent ACK for SYN to generate a sent event */
+          if (recv_acked != 0) {
+ 801ad64:	4b63      	ldr	r3, [pc, #396]	; (801aef4 <tcp_process+0x5b8>)
+ 801ad66:	881b      	ldrh	r3, [r3, #0]
+ 801ad68:	2b00      	cmp	r3, #0
+ 801ad6a:	d005      	beq.n	801ad78 <tcp_process+0x43c>
+            recv_acked--;
+ 801ad6c:	4b61      	ldr	r3, [pc, #388]	; (801aef4 <tcp_process+0x5b8>)
+ 801ad6e:	881b      	ldrh	r3, [r3, #0]
+ 801ad70:	3b01      	subs	r3, #1
+ 801ad72:	b29a      	uxth	r2, r3
+ 801ad74:	4b5f      	ldr	r3, [pc, #380]	; (801aef4 <tcp_process+0x5b8>)
+ 801ad76:	801a      	strh	r2, [r3, #0]
+          }
+
+          pcb->cwnd = LWIP_TCP_CALC_INITIAL_CWND(pcb->mss);
+ 801ad78:	687b      	ldr	r3, [r7, #4]
+ 801ad7a:	8e5b      	ldrh	r3, [r3, #50]	; 0x32
+ 801ad7c:	009a      	lsls	r2, r3, #2
+ 801ad7e:	687b      	ldr	r3, [r7, #4]
+ 801ad80:	8e5b      	ldrh	r3, [r3, #50]	; 0x32
+ 801ad82:	005b      	lsls	r3, r3, #1
+ 801ad84:	f241 111c 	movw	r1, #4380	; 0x111c
+ 801ad88:	428b      	cmp	r3, r1
+ 801ad8a:	bf38      	it	cc
+ 801ad8c:	460b      	movcc	r3, r1
+ 801ad8e:	429a      	cmp	r2, r3
+ 801ad90:	d204      	bcs.n	801ad9c <tcp_process+0x460>
+ 801ad92:	687b      	ldr	r3, [r7, #4]
+ 801ad94:	8e5b      	ldrh	r3, [r3, #50]	; 0x32
+ 801ad96:	009b      	lsls	r3, r3, #2
+ 801ad98:	b29b      	uxth	r3, r3
+ 801ad9a:	e00d      	b.n	801adb8 <tcp_process+0x47c>
+ 801ad9c:	687b      	ldr	r3, [r7, #4]
+ 801ad9e:	8e5b      	ldrh	r3, [r3, #50]	; 0x32
+ 801ada0:	005b      	lsls	r3, r3, #1
+ 801ada2:	f241 121c 	movw	r2, #4380	; 0x111c
+ 801ada6:	4293      	cmp	r3, r2
+ 801ada8:	d904      	bls.n	801adb4 <tcp_process+0x478>
+ 801adaa:	687b      	ldr	r3, [r7, #4]
+ 801adac:	8e5b      	ldrh	r3, [r3, #50]	; 0x32
+ 801adae:	005b      	lsls	r3, r3, #1
+ 801adb0:	b29b      	uxth	r3, r3
+ 801adb2:	e001      	b.n	801adb8 <tcp_process+0x47c>
+ 801adb4:	f241 131c 	movw	r3, #4380	; 0x111c
+ 801adb8:	687a      	ldr	r2, [r7, #4]
+ 801adba:	f8a2 3048 	strh.w	r3, [r2, #72]	; 0x48
+          LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_process (SYN_RCVD): cwnd %"TCPWNDSIZE_F
+                                       " ssthresh %"TCPWNDSIZE_F"\n",
+                                       pcb->cwnd, pcb->ssthresh));
+
+          if (recv_flags & TF_GOT_FIN) {
+ 801adbe:	4b4e      	ldr	r3, [pc, #312]	; (801aef8 <tcp_process+0x5bc>)
+ 801adc0:	781b      	ldrb	r3, [r3, #0]
+ 801adc2:	f003 0320 	and.w	r3, r3, #32
+ 801adc6:	2b00      	cmp	r3, #0
+ 801adc8:	d037      	beq.n	801ae3a <tcp_process+0x4fe>
+            tcp_ack_now(pcb);
+ 801adca:	687b      	ldr	r3, [r7, #4]
+ 801adcc:	8b5b      	ldrh	r3, [r3, #26]
+ 801adce:	f043 0302 	orr.w	r3, r3, #2
+ 801add2:	b29a      	uxth	r2, r3
+ 801add4:	687b      	ldr	r3, [r7, #4]
+ 801add6:	835a      	strh	r2, [r3, #26]
+            pcb->state = CLOSE_WAIT;
+ 801add8:	687b      	ldr	r3, [r7, #4]
+ 801adda:	2207      	movs	r2, #7
+ 801addc:	751a      	strb	r2, [r3, #20]
+          if (recv_flags & TF_GOT_FIN) {
+ 801adde:	e02c      	b.n	801ae3a <tcp_process+0x4fe>
+          }
+        } else {
+          /* incorrect ACK number, send RST */
+          tcp_rst(pcb, ackno, seqno + tcplen, ip_current_dest_addr(),
+ 801ade0:	4b3b      	ldr	r3, [pc, #236]	; (801aed0 <tcp_process+0x594>)
+ 801ade2:	6819      	ldr	r1, [r3, #0]
+ 801ade4:	4b3b      	ldr	r3, [pc, #236]	; (801aed4 <tcp_process+0x598>)
+ 801ade6:	881b      	ldrh	r3, [r3, #0]
+ 801ade8:	461a      	mov	r2, r3
+ 801adea:	4b3b      	ldr	r3, [pc, #236]	; (801aed8 <tcp_process+0x59c>)
+ 801adec:	681b      	ldr	r3, [r3, #0]
+ 801adee:	18d0      	adds	r0, r2, r3
+                  ip_current_src_addr(), tcphdr->dest, tcphdr->src);
+ 801adf0:	4b3a      	ldr	r3, [pc, #232]	; (801aedc <tcp_process+0x5a0>)
+ 801adf2:	681b      	ldr	r3, [r3, #0]
+          tcp_rst(pcb, ackno, seqno + tcplen, ip_current_dest_addr(),
+ 801adf4:	885b      	ldrh	r3, [r3, #2]
+ 801adf6:	b29b      	uxth	r3, r3
+                  ip_current_src_addr(), tcphdr->dest, tcphdr->src);
+ 801adf8:	4a38      	ldr	r2, [pc, #224]	; (801aedc <tcp_process+0x5a0>)
+ 801adfa:	6812      	ldr	r2, [r2, #0]
+          tcp_rst(pcb, ackno, seqno + tcplen, ip_current_dest_addr(),
+ 801adfc:	8812      	ldrh	r2, [r2, #0]
+ 801adfe:	b292      	uxth	r2, r2
+ 801ae00:	9202      	str	r2, [sp, #8]
+ 801ae02:	9301      	str	r3, [sp, #4]
+ 801ae04:	4b36      	ldr	r3, [pc, #216]	; (801aee0 <tcp_process+0x5a4>)
+ 801ae06:	9300      	str	r3, [sp, #0]
+ 801ae08:	4b36      	ldr	r3, [pc, #216]	; (801aee4 <tcp_process+0x5a8>)
+ 801ae0a:	4602      	mov	r2, r0
+ 801ae0c:	6878      	ldr	r0, [r7, #4]
+ 801ae0e:	f003 f895 	bl	801df3c <tcp_rst>
+        }
+      } else if ((flags & TCP_SYN) && (seqno == pcb->rcv_nxt - 1)) {
+        /* Looks like another copy of the SYN - retransmit our SYN-ACK */
+        tcp_rexmit(pcb);
+      }
+      break;
+ 801ae12:	e167      	b.n	801b0e4 <tcp_process+0x7a8>
+      } else if ((flags & TCP_SYN) && (seqno == pcb->rcv_nxt - 1)) {
+ 801ae14:	4b2d      	ldr	r3, [pc, #180]	; (801aecc <tcp_process+0x590>)
+ 801ae16:	781b      	ldrb	r3, [r3, #0]
+ 801ae18:	f003 0302 	and.w	r3, r3, #2
+ 801ae1c:	2b00      	cmp	r3, #0
+ 801ae1e:	f000 8161 	beq.w	801b0e4 <tcp_process+0x7a8>
+ 801ae22:	687b      	ldr	r3, [r7, #4]
+ 801ae24:	6a5b      	ldr	r3, [r3, #36]	; 0x24
+ 801ae26:	1e5a      	subs	r2, r3, #1
+ 801ae28:	4b2b      	ldr	r3, [pc, #172]	; (801aed8 <tcp_process+0x59c>)
+ 801ae2a:	681b      	ldr	r3, [r3, #0]
+ 801ae2c:	429a      	cmp	r2, r3
+ 801ae2e:	f040 8159 	bne.w	801b0e4 <tcp_process+0x7a8>
+        tcp_rexmit(pcb);
+ 801ae32:	6878      	ldr	r0, [r7, #4]
+ 801ae34:	f002 fe7c 	bl	801db30 <tcp_rexmit>
+      break;
+ 801ae38:	e154      	b.n	801b0e4 <tcp_process+0x7a8>
+ 801ae3a:	e153      	b.n	801b0e4 <tcp_process+0x7a8>
+    case CLOSE_WAIT:
+    /* FALLTHROUGH */
+    case ESTABLISHED:
+      tcp_receive(pcb);
+ 801ae3c:	6878      	ldr	r0, [r7, #4]
+ 801ae3e:	f000 fa71 	bl	801b324 <tcp_receive>
+      if (recv_flags & TF_GOT_FIN) { /* passive close */
+ 801ae42:	4b2d      	ldr	r3, [pc, #180]	; (801aef8 <tcp_process+0x5bc>)
+ 801ae44:	781b      	ldrb	r3, [r3, #0]
+ 801ae46:	f003 0320 	and.w	r3, r3, #32
+ 801ae4a:	2b00      	cmp	r3, #0
+ 801ae4c:	f000 814c 	beq.w	801b0e8 <tcp_process+0x7ac>
+        tcp_ack_now(pcb);
+ 801ae50:	687b      	ldr	r3, [r7, #4]
+ 801ae52:	8b5b      	ldrh	r3, [r3, #26]
+ 801ae54:	f043 0302 	orr.w	r3, r3, #2
+ 801ae58:	b29a      	uxth	r2, r3
+ 801ae5a:	687b      	ldr	r3, [r7, #4]
+ 801ae5c:	835a      	strh	r2, [r3, #26]
+        pcb->state = CLOSE_WAIT;
+ 801ae5e:	687b      	ldr	r3, [r7, #4]
+ 801ae60:	2207      	movs	r2, #7
+ 801ae62:	751a      	strb	r2, [r3, #20]
+      }
+      break;
+ 801ae64:	e140      	b.n	801b0e8 <tcp_process+0x7ac>
+    case FIN_WAIT_1:
+      tcp_receive(pcb);
+ 801ae66:	6878      	ldr	r0, [r7, #4]
+ 801ae68:	f000 fa5c 	bl	801b324 <tcp_receive>
+      if (recv_flags & TF_GOT_FIN) {
+ 801ae6c:	4b22      	ldr	r3, [pc, #136]	; (801aef8 <tcp_process+0x5bc>)
+ 801ae6e:	781b      	ldrb	r3, [r3, #0]
+ 801ae70:	f003 0320 	and.w	r3, r3, #32
+ 801ae74:	2b00      	cmp	r3, #0
+ 801ae76:	d071      	beq.n	801af5c <tcp_process+0x620>
+        if ((flags & TCP_ACK) && (ackno == pcb->snd_nxt) &&
+ 801ae78:	4b14      	ldr	r3, [pc, #80]	; (801aecc <tcp_process+0x590>)
+ 801ae7a:	781b      	ldrb	r3, [r3, #0]
+ 801ae7c:	f003 0310 	and.w	r3, r3, #16
+ 801ae80:	2b00      	cmp	r3, #0
+ 801ae82:	d060      	beq.n	801af46 <tcp_process+0x60a>
+ 801ae84:	687b      	ldr	r3, [r7, #4]
+ 801ae86:	6d1a      	ldr	r2, [r3, #80]	; 0x50
+ 801ae88:	4b11      	ldr	r3, [pc, #68]	; (801aed0 <tcp_process+0x594>)
+ 801ae8a:	681b      	ldr	r3, [r3, #0]
+ 801ae8c:	429a      	cmp	r2, r3
+ 801ae8e:	d15a      	bne.n	801af46 <tcp_process+0x60a>
+            pcb->unsent == NULL) {
+ 801ae90:	687b      	ldr	r3, [r7, #4]
+ 801ae92:	6edb      	ldr	r3, [r3, #108]	; 0x6c
+        if ((flags & TCP_ACK) && (ackno == pcb->snd_nxt) &&
+ 801ae94:	2b00      	cmp	r3, #0
+ 801ae96:	d156      	bne.n	801af46 <tcp_process+0x60a>
+          LWIP_DEBUGF(TCP_DEBUG,
+                      ("TCP connection closed: FIN_WAIT_1 %"U16_F" -> %"U16_F".\n", inseg.tcphdr->src, inseg.tcphdr->dest));
+          tcp_ack_now(pcb);
+ 801ae98:	687b      	ldr	r3, [r7, #4]
+ 801ae9a:	8b5b      	ldrh	r3, [r3, #26]
+ 801ae9c:	f043 0302 	orr.w	r3, r3, #2
+ 801aea0:	b29a      	uxth	r2, r3
+ 801aea2:	687b      	ldr	r3, [r7, #4]
+ 801aea4:	835a      	strh	r2, [r3, #26]
+          tcp_pcb_purge(pcb);
+ 801aea6:	6878      	ldr	r0, [r7, #4]
+ 801aea8:	f7fe fdb6 	bl	8019a18 <tcp_pcb_purge>
+          TCP_RMV_ACTIVE(pcb);
+ 801aeac:	4b13      	ldr	r3, [pc, #76]	; (801aefc <tcp_process+0x5c0>)
+ 801aeae:	681b      	ldr	r3, [r3, #0]
+ 801aeb0:	687a      	ldr	r2, [r7, #4]
+ 801aeb2:	429a      	cmp	r2, r3
+ 801aeb4:	d105      	bne.n	801aec2 <tcp_process+0x586>
+ 801aeb6:	4b11      	ldr	r3, [pc, #68]	; (801aefc <tcp_process+0x5c0>)
+ 801aeb8:	681b      	ldr	r3, [r3, #0]
+ 801aeba:	68db      	ldr	r3, [r3, #12]
+ 801aebc:	4a0f      	ldr	r2, [pc, #60]	; (801aefc <tcp_process+0x5c0>)
+ 801aebe:	6013      	str	r3, [r2, #0]
+ 801aec0:	e02e      	b.n	801af20 <tcp_process+0x5e4>
+ 801aec2:	4b0e      	ldr	r3, [pc, #56]	; (801aefc <tcp_process+0x5c0>)
+ 801aec4:	681b      	ldr	r3, [r3, #0]
+ 801aec6:	613b      	str	r3, [r7, #16]
+ 801aec8:	e027      	b.n	801af1a <tcp_process+0x5de>
+ 801aeca:	bf00      	nop
+ 801aecc:	2401a4c8 	.word	0x2401a4c8
+ 801aed0:	2401a4c0 	.word	0x2401a4c0
+ 801aed4:	2401a4c6 	.word	0x2401a4c6
+ 801aed8:	2401a4bc 	.word	0x2401a4bc
+ 801aedc:	2401a4ac 	.word	0x2401a4ac
+ 801aee0:	24013990 	.word	0x24013990
+ 801aee4:	24013994 	.word	0x24013994
+ 801aee8:	08025338 	.word	0x08025338
+ 801aeec:	080255d8 	.word	0x080255d8
+ 801aef0:	08025384 	.word	0x08025384
+ 801aef4:	2401a4c4 	.word	0x2401a4c4
+ 801aef8:	2401a4c9 	.word	0x2401a4c9
+ 801aefc:	2401a48c 	.word	0x2401a48c
+ 801af00:	693b      	ldr	r3, [r7, #16]
+ 801af02:	68db      	ldr	r3, [r3, #12]
+ 801af04:	687a      	ldr	r2, [r7, #4]
+ 801af06:	429a      	cmp	r2, r3
+ 801af08:	d104      	bne.n	801af14 <tcp_process+0x5d8>
+ 801af0a:	687b      	ldr	r3, [r7, #4]
+ 801af0c:	68da      	ldr	r2, [r3, #12]
+ 801af0e:	693b      	ldr	r3, [r7, #16]
+ 801af10:	60da      	str	r2, [r3, #12]
+ 801af12:	e005      	b.n	801af20 <tcp_process+0x5e4>
+ 801af14:	693b      	ldr	r3, [r7, #16]
+ 801af16:	68db      	ldr	r3, [r3, #12]
+ 801af18:	613b      	str	r3, [r7, #16]
+ 801af1a:	693b      	ldr	r3, [r7, #16]
+ 801af1c:	2b00      	cmp	r3, #0
+ 801af1e:	d1ef      	bne.n	801af00 <tcp_process+0x5c4>
+ 801af20:	687b      	ldr	r3, [r7, #4]
+ 801af22:	2200      	movs	r2, #0
+ 801af24:	60da      	str	r2, [r3, #12]
+ 801af26:	4b77      	ldr	r3, [pc, #476]	; (801b104 <tcp_process+0x7c8>)
+ 801af28:	2201      	movs	r2, #1
+ 801af2a:	701a      	strb	r2, [r3, #0]
+          pcb->state = TIME_WAIT;
+ 801af2c:	687b      	ldr	r3, [r7, #4]
+ 801af2e:	220a      	movs	r2, #10
+ 801af30:	751a      	strb	r2, [r3, #20]
+          TCP_REG(&tcp_tw_pcbs, pcb);
+ 801af32:	4b75      	ldr	r3, [pc, #468]	; (801b108 <tcp_process+0x7cc>)
+ 801af34:	681a      	ldr	r2, [r3, #0]
+ 801af36:	687b      	ldr	r3, [r7, #4]
+ 801af38:	60da      	str	r2, [r3, #12]
+ 801af3a:	4a73      	ldr	r2, [pc, #460]	; (801b108 <tcp_process+0x7cc>)
+ 801af3c:	687b      	ldr	r3, [r7, #4]
+ 801af3e:	6013      	str	r3, [r2, #0]
+ 801af40:	f003 f9be 	bl	801e2c0 <tcp_timer_needed>
+        }
+      } else if ((flags & TCP_ACK) && (ackno == pcb->snd_nxt) &&
+                 pcb->unsent == NULL) {
+        pcb->state = FIN_WAIT_2;
+      }
+      break;
+ 801af44:	e0d2      	b.n	801b0ec <tcp_process+0x7b0>
+          tcp_ack_now(pcb);
+ 801af46:	687b      	ldr	r3, [r7, #4]
+ 801af48:	8b5b      	ldrh	r3, [r3, #26]
+ 801af4a:	f043 0302 	orr.w	r3, r3, #2
+ 801af4e:	b29a      	uxth	r2, r3
+ 801af50:	687b      	ldr	r3, [r7, #4]
+ 801af52:	835a      	strh	r2, [r3, #26]
+          pcb->state = CLOSING;
+ 801af54:	687b      	ldr	r3, [r7, #4]
+ 801af56:	2208      	movs	r2, #8
+ 801af58:	751a      	strb	r2, [r3, #20]
+      break;
+ 801af5a:	e0c7      	b.n	801b0ec <tcp_process+0x7b0>
+      } else if ((flags & TCP_ACK) && (ackno == pcb->snd_nxt) &&
+ 801af5c:	4b6b      	ldr	r3, [pc, #428]	; (801b10c <tcp_process+0x7d0>)
+ 801af5e:	781b      	ldrb	r3, [r3, #0]
+ 801af60:	f003 0310 	and.w	r3, r3, #16
+ 801af64:	2b00      	cmp	r3, #0
+ 801af66:	f000 80c1 	beq.w	801b0ec <tcp_process+0x7b0>
+ 801af6a:	687b      	ldr	r3, [r7, #4]
+ 801af6c:	6d1a      	ldr	r2, [r3, #80]	; 0x50
+ 801af6e:	4b68      	ldr	r3, [pc, #416]	; (801b110 <tcp_process+0x7d4>)
+ 801af70:	681b      	ldr	r3, [r3, #0]
+ 801af72:	429a      	cmp	r2, r3
+ 801af74:	f040 80ba 	bne.w	801b0ec <tcp_process+0x7b0>
+                 pcb->unsent == NULL) {
+ 801af78:	687b      	ldr	r3, [r7, #4]
+ 801af7a:	6edb      	ldr	r3, [r3, #108]	; 0x6c
+      } else if ((flags & TCP_ACK) && (ackno == pcb->snd_nxt) &&
+ 801af7c:	2b00      	cmp	r3, #0
+ 801af7e:	f040 80b5 	bne.w	801b0ec <tcp_process+0x7b0>
+        pcb->state = FIN_WAIT_2;
+ 801af82:	687b      	ldr	r3, [r7, #4]
+ 801af84:	2206      	movs	r2, #6
+ 801af86:	751a      	strb	r2, [r3, #20]
+      break;
+ 801af88:	e0b0      	b.n	801b0ec <tcp_process+0x7b0>
+    case FIN_WAIT_2:
+      tcp_receive(pcb);
+ 801af8a:	6878      	ldr	r0, [r7, #4]
+ 801af8c:	f000 f9ca 	bl	801b324 <tcp_receive>
+      if (recv_flags & TF_GOT_FIN) {
+ 801af90:	4b60      	ldr	r3, [pc, #384]	; (801b114 <tcp_process+0x7d8>)
+ 801af92:	781b      	ldrb	r3, [r3, #0]
+ 801af94:	f003 0320 	and.w	r3, r3, #32
+ 801af98:	2b00      	cmp	r3, #0
+ 801af9a:	f000 80a9 	beq.w	801b0f0 <tcp_process+0x7b4>
+        LWIP_DEBUGF(TCP_DEBUG, ("TCP connection closed: FIN_WAIT_2 %"U16_F" -> %"U16_F".\n", inseg.tcphdr->src, inseg.tcphdr->dest));
+        tcp_ack_now(pcb);
+ 801af9e:	687b      	ldr	r3, [r7, #4]
+ 801afa0:	8b5b      	ldrh	r3, [r3, #26]
+ 801afa2:	f043 0302 	orr.w	r3, r3, #2
+ 801afa6:	b29a      	uxth	r2, r3
+ 801afa8:	687b      	ldr	r3, [r7, #4]
+ 801afaa:	835a      	strh	r2, [r3, #26]
+        tcp_pcb_purge(pcb);
+ 801afac:	6878      	ldr	r0, [r7, #4]
+ 801afae:	f7fe fd33 	bl	8019a18 <tcp_pcb_purge>
+        TCP_RMV_ACTIVE(pcb);
+ 801afb2:	4b59      	ldr	r3, [pc, #356]	; (801b118 <tcp_process+0x7dc>)
+ 801afb4:	681b      	ldr	r3, [r3, #0]
+ 801afb6:	687a      	ldr	r2, [r7, #4]
+ 801afb8:	429a      	cmp	r2, r3
+ 801afba:	d105      	bne.n	801afc8 <tcp_process+0x68c>
+ 801afbc:	4b56      	ldr	r3, [pc, #344]	; (801b118 <tcp_process+0x7dc>)
+ 801afbe:	681b      	ldr	r3, [r3, #0]
+ 801afc0:	68db      	ldr	r3, [r3, #12]
+ 801afc2:	4a55      	ldr	r2, [pc, #340]	; (801b118 <tcp_process+0x7dc>)
+ 801afc4:	6013      	str	r3, [r2, #0]
+ 801afc6:	e013      	b.n	801aff0 <tcp_process+0x6b4>
+ 801afc8:	4b53      	ldr	r3, [pc, #332]	; (801b118 <tcp_process+0x7dc>)
+ 801afca:	681b      	ldr	r3, [r3, #0]
+ 801afcc:	60fb      	str	r3, [r7, #12]
+ 801afce:	e00c      	b.n	801afea <tcp_process+0x6ae>
+ 801afd0:	68fb      	ldr	r3, [r7, #12]
+ 801afd2:	68db      	ldr	r3, [r3, #12]
+ 801afd4:	687a      	ldr	r2, [r7, #4]
+ 801afd6:	429a      	cmp	r2, r3
+ 801afd8:	d104      	bne.n	801afe4 <tcp_process+0x6a8>
+ 801afda:	687b      	ldr	r3, [r7, #4]
+ 801afdc:	68da      	ldr	r2, [r3, #12]
+ 801afde:	68fb      	ldr	r3, [r7, #12]
+ 801afe0:	60da      	str	r2, [r3, #12]
+ 801afe2:	e005      	b.n	801aff0 <tcp_process+0x6b4>
+ 801afe4:	68fb      	ldr	r3, [r7, #12]
+ 801afe6:	68db      	ldr	r3, [r3, #12]
+ 801afe8:	60fb      	str	r3, [r7, #12]
+ 801afea:	68fb      	ldr	r3, [r7, #12]
+ 801afec:	2b00      	cmp	r3, #0
+ 801afee:	d1ef      	bne.n	801afd0 <tcp_process+0x694>
+ 801aff0:	687b      	ldr	r3, [r7, #4]
+ 801aff2:	2200      	movs	r2, #0
+ 801aff4:	60da      	str	r2, [r3, #12]
+ 801aff6:	4b43      	ldr	r3, [pc, #268]	; (801b104 <tcp_process+0x7c8>)
+ 801aff8:	2201      	movs	r2, #1
+ 801affa:	701a      	strb	r2, [r3, #0]
+        pcb->state = TIME_WAIT;
+ 801affc:	687b      	ldr	r3, [r7, #4]
+ 801affe:	220a      	movs	r2, #10
+ 801b000:	751a      	strb	r2, [r3, #20]
+        TCP_REG(&tcp_tw_pcbs, pcb);
+ 801b002:	4b41      	ldr	r3, [pc, #260]	; (801b108 <tcp_process+0x7cc>)
+ 801b004:	681a      	ldr	r2, [r3, #0]
+ 801b006:	687b      	ldr	r3, [r7, #4]
+ 801b008:	60da      	str	r2, [r3, #12]
+ 801b00a:	4a3f      	ldr	r2, [pc, #252]	; (801b108 <tcp_process+0x7cc>)
+ 801b00c:	687b      	ldr	r3, [r7, #4]
+ 801b00e:	6013      	str	r3, [r2, #0]
+ 801b010:	f003 f956 	bl	801e2c0 <tcp_timer_needed>
+      }
+      break;
+ 801b014:	e06c      	b.n	801b0f0 <tcp_process+0x7b4>
+    case CLOSING:
+      tcp_receive(pcb);
+ 801b016:	6878      	ldr	r0, [r7, #4]
+ 801b018:	f000 f984 	bl	801b324 <tcp_receive>
+      if ((flags & TCP_ACK) && ackno == pcb->snd_nxt && pcb->unsent == NULL) {
+ 801b01c:	4b3b      	ldr	r3, [pc, #236]	; (801b10c <tcp_process+0x7d0>)
+ 801b01e:	781b      	ldrb	r3, [r3, #0]
+ 801b020:	f003 0310 	and.w	r3, r3, #16
+ 801b024:	2b00      	cmp	r3, #0
+ 801b026:	d065      	beq.n	801b0f4 <tcp_process+0x7b8>
+ 801b028:	687b      	ldr	r3, [r7, #4]
+ 801b02a:	6d1a      	ldr	r2, [r3, #80]	; 0x50
+ 801b02c:	4b38      	ldr	r3, [pc, #224]	; (801b110 <tcp_process+0x7d4>)
+ 801b02e:	681b      	ldr	r3, [r3, #0]
+ 801b030:	429a      	cmp	r2, r3
+ 801b032:	d15f      	bne.n	801b0f4 <tcp_process+0x7b8>
+ 801b034:	687b      	ldr	r3, [r7, #4]
+ 801b036:	6edb      	ldr	r3, [r3, #108]	; 0x6c
+ 801b038:	2b00      	cmp	r3, #0
+ 801b03a:	d15b      	bne.n	801b0f4 <tcp_process+0x7b8>
+        LWIP_DEBUGF(TCP_DEBUG, ("TCP connection closed: CLOSING %"U16_F" -> %"U16_F".\n", inseg.tcphdr->src, inseg.tcphdr->dest));
+        tcp_pcb_purge(pcb);
+ 801b03c:	6878      	ldr	r0, [r7, #4]
+ 801b03e:	f7fe fceb 	bl	8019a18 <tcp_pcb_purge>
+        TCP_RMV_ACTIVE(pcb);
+ 801b042:	4b35      	ldr	r3, [pc, #212]	; (801b118 <tcp_process+0x7dc>)
+ 801b044:	681b      	ldr	r3, [r3, #0]
+ 801b046:	687a      	ldr	r2, [r7, #4]
+ 801b048:	429a      	cmp	r2, r3
+ 801b04a:	d105      	bne.n	801b058 <tcp_process+0x71c>
+ 801b04c:	4b32      	ldr	r3, [pc, #200]	; (801b118 <tcp_process+0x7dc>)
+ 801b04e:	681b      	ldr	r3, [r3, #0]
+ 801b050:	68db      	ldr	r3, [r3, #12]
+ 801b052:	4a31      	ldr	r2, [pc, #196]	; (801b118 <tcp_process+0x7dc>)
+ 801b054:	6013      	str	r3, [r2, #0]
+ 801b056:	e013      	b.n	801b080 <tcp_process+0x744>
+ 801b058:	4b2f      	ldr	r3, [pc, #188]	; (801b118 <tcp_process+0x7dc>)
+ 801b05a:	681b      	ldr	r3, [r3, #0]
+ 801b05c:	61bb      	str	r3, [r7, #24]
+ 801b05e:	e00c      	b.n	801b07a <tcp_process+0x73e>
+ 801b060:	69bb      	ldr	r3, [r7, #24]
+ 801b062:	68db      	ldr	r3, [r3, #12]
+ 801b064:	687a      	ldr	r2, [r7, #4]
+ 801b066:	429a      	cmp	r2, r3
+ 801b068:	d104      	bne.n	801b074 <tcp_process+0x738>
+ 801b06a:	687b      	ldr	r3, [r7, #4]
+ 801b06c:	68da      	ldr	r2, [r3, #12]
+ 801b06e:	69bb      	ldr	r3, [r7, #24]
+ 801b070:	60da      	str	r2, [r3, #12]
+ 801b072:	e005      	b.n	801b080 <tcp_process+0x744>
+ 801b074:	69bb      	ldr	r3, [r7, #24]
+ 801b076:	68db      	ldr	r3, [r3, #12]
+ 801b078:	61bb      	str	r3, [r7, #24]
+ 801b07a:	69bb      	ldr	r3, [r7, #24]
+ 801b07c:	2b00      	cmp	r3, #0
+ 801b07e:	d1ef      	bne.n	801b060 <tcp_process+0x724>
+ 801b080:	687b      	ldr	r3, [r7, #4]
+ 801b082:	2200      	movs	r2, #0
+ 801b084:	60da      	str	r2, [r3, #12]
+ 801b086:	4b1f      	ldr	r3, [pc, #124]	; (801b104 <tcp_process+0x7c8>)
+ 801b088:	2201      	movs	r2, #1
+ 801b08a:	701a      	strb	r2, [r3, #0]
+        pcb->state = TIME_WAIT;
+ 801b08c:	687b      	ldr	r3, [r7, #4]
+ 801b08e:	220a      	movs	r2, #10
+ 801b090:	751a      	strb	r2, [r3, #20]
+        TCP_REG(&tcp_tw_pcbs, pcb);
+ 801b092:	4b1d      	ldr	r3, [pc, #116]	; (801b108 <tcp_process+0x7cc>)
+ 801b094:	681a      	ldr	r2, [r3, #0]
+ 801b096:	687b      	ldr	r3, [r7, #4]
+ 801b098:	60da      	str	r2, [r3, #12]
+ 801b09a:	4a1b      	ldr	r2, [pc, #108]	; (801b108 <tcp_process+0x7cc>)
+ 801b09c:	687b      	ldr	r3, [r7, #4]
+ 801b09e:	6013      	str	r3, [r2, #0]
+ 801b0a0:	f003 f90e 	bl	801e2c0 <tcp_timer_needed>
+      }
+      break;
+ 801b0a4:	e026      	b.n	801b0f4 <tcp_process+0x7b8>
+    case LAST_ACK:
+      tcp_receive(pcb);
+ 801b0a6:	6878      	ldr	r0, [r7, #4]
+ 801b0a8:	f000 f93c 	bl	801b324 <tcp_receive>
+      if ((flags & TCP_ACK) && ackno == pcb->snd_nxt && pcb->unsent == NULL) {
+ 801b0ac:	4b17      	ldr	r3, [pc, #92]	; (801b10c <tcp_process+0x7d0>)
+ 801b0ae:	781b      	ldrb	r3, [r3, #0]
+ 801b0b0:	f003 0310 	and.w	r3, r3, #16
+ 801b0b4:	2b00      	cmp	r3, #0
+ 801b0b6:	d01f      	beq.n	801b0f8 <tcp_process+0x7bc>
+ 801b0b8:	687b      	ldr	r3, [r7, #4]
+ 801b0ba:	6d1a      	ldr	r2, [r3, #80]	; 0x50
+ 801b0bc:	4b14      	ldr	r3, [pc, #80]	; (801b110 <tcp_process+0x7d4>)
+ 801b0be:	681b      	ldr	r3, [r3, #0]
+ 801b0c0:	429a      	cmp	r2, r3
+ 801b0c2:	d119      	bne.n	801b0f8 <tcp_process+0x7bc>
+ 801b0c4:	687b      	ldr	r3, [r7, #4]
+ 801b0c6:	6edb      	ldr	r3, [r3, #108]	; 0x6c
+ 801b0c8:	2b00      	cmp	r3, #0
+ 801b0ca:	d115      	bne.n	801b0f8 <tcp_process+0x7bc>
+        LWIP_DEBUGF(TCP_DEBUG, ("TCP connection closed: LAST_ACK %"U16_F" -> %"U16_F".\n", inseg.tcphdr->src, inseg.tcphdr->dest));
+        /* bugfix #21699: don't set pcb->state to CLOSED here or we risk leaking segments */
+        recv_flags |= TF_CLOSED;
+ 801b0cc:	4b11      	ldr	r3, [pc, #68]	; (801b114 <tcp_process+0x7d8>)
+ 801b0ce:	781b      	ldrb	r3, [r3, #0]
+ 801b0d0:	f043 0310 	orr.w	r3, r3, #16
+ 801b0d4:	b2da      	uxtb	r2, r3
+ 801b0d6:	4b0f      	ldr	r3, [pc, #60]	; (801b114 <tcp_process+0x7d8>)
+ 801b0d8:	701a      	strb	r2, [r3, #0]
+      }
+      break;
+ 801b0da:	e00d      	b.n	801b0f8 <tcp_process+0x7bc>
+    default:
+      break;
+ 801b0dc:	bf00      	nop
+ 801b0de:	e00c      	b.n	801b0fa <tcp_process+0x7be>
+      break;
+ 801b0e0:	bf00      	nop
+ 801b0e2:	e00a      	b.n	801b0fa <tcp_process+0x7be>
+      break;
+ 801b0e4:	bf00      	nop
+ 801b0e6:	e008      	b.n	801b0fa <tcp_process+0x7be>
+      break;
+ 801b0e8:	bf00      	nop
+ 801b0ea:	e006      	b.n	801b0fa <tcp_process+0x7be>
+      break;
+ 801b0ec:	bf00      	nop
+ 801b0ee:	e004      	b.n	801b0fa <tcp_process+0x7be>
+      break;
+ 801b0f0:	bf00      	nop
+ 801b0f2:	e002      	b.n	801b0fa <tcp_process+0x7be>
+      break;
+ 801b0f4:	bf00      	nop
+ 801b0f6:	e000      	b.n	801b0fa <tcp_process+0x7be>
+      break;
+ 801b0f8:	bf00      	nop
+  }
+  return ERR_OK;
+ 801b0fa:	2300      	movs	r3, #0
+}
+ 801b0fc:	4618      	mov	r0, r3
+ 801b0fe:	3724      	adds	r7, #36	; 0x24
+ 801b100:	46bd      	mov	sp, r7
+ 801b102:	bd90      	pop	{r4, r7, pc}
+ 801b104:	2401a494 	.word	0x2401a494
+ 801b108:	2401a490 	.word	0x2401a490
+ 801b10c:	2401a4c8 	.word	0x2401a4c8
+ 801b110:	2401a4c0 	.word	0x2401a4c0
+ 801b114:	2401a4c9 	.word	0x2401a4c9
+ 801b118:	2401a48c 	.word	0x2401a48c
+
+0801b11c <tcp_oos_insert_segment>:
+ *
+ * Called from tcp_receive()
+ */
+static void
+tcp_oos_insert_segment(struct tcp_seg *cseg, struct tcp_seg *next)
+{
+ 801b11c:	b590      	push	{r4, r7, lr}
+ 801b11e:	b085      	sub	sp, #20
+ 801b120:	af00      	add	r7, sp, #0
+ 801b122:	6078      	str	r0, [r7, #4]
+ 801b124:	6039      	str	r1, [r7, #0]
+  struct tcp_seg *old_seg;
+
+  LWIP_ASSERT("tcp_oos_insert_segment: invalid cseg", cseg != NULL);
+ 801b126:	687b      	ldr	r3, [r7, #4]
+ 801b128:	2b00      	cmp	r3, #0
+ 801b12a:	d106      	bne.n	801b13a <tcp_oos_insert_segment+0x1e>
+ 801b12c:	4b3b      	ldr	r3, [pc, #236]	; (801b21c <tcp_oos_insert_segment+0x100>)
+ 801b12e:	f240 421f 	movw	r2, #1055	; 0x41f
+ 801b132:	493b      	ldr	r1, [pc, #236]	; (801b220 <tcp_oos_insert_segment+0x104>)
+ 801b134:	483b      	ldr	r0, [pc, #236]	; (801b224 <tcp_oos_insert_segment+0x108>)
+ 801b136:	f006 fc27 	bl	8021988 <iprintf>
+
+  if (TCPH_FLAGS(cseg->tcphdr) & TCP_FIN) {
+ 801b13a:	687b      	ldr	r3, [r7, #4]
+ 801b13c:	691b      	ldr	r3, [r3, #16]
+ 801b13e:	899b      	ldrh	r3, [r3, #12]
+ 801b140:	b29b      	uxth	r3, r3
+ 801b142:	4618      	mov	r0, r3
+ 801b144:	f7fa fefc 	bl	8015f40 <lwip_htons>
+ 801b148:	4603      	mov	r3, r0
+ 801b14a:	b2db      	uxtb	r3, r3
+ 801b14c:	f003 0301 	and.w	r3, r3, #1
+ 801b150:	2b00      	cmp	r3, #0
+ 801b152:	d028      	beq.n	801b1a6 <tcp_oos_insert_segment+0x8a>
+    /* received segment overlaps all following segments */
+    tcp_segs_free(next);
+ 801b154:	6838      	ldr	r0, [r7, #0]
+ 801b156:	f7fe f98f 	bl	8019478 <tcp_segs_free>
+    next = NULL;
+ 801b15a:	2300      	movs	r3, #0
+ 801b15c:	603b      	str	r3, [r7, #0]
+ 801b15e:	e056      	b.n	801b20e <tcp_oos_insert_segment+0xf2>
+       oos queue may have segments with FIN flag */
+    while (next &&
+           TCP_SEQ_GEQ((seqno + cseg->len),
+                       (next->tcphdr->seqno + next->len))) {
+      /* cseg with FIN already processed */
+      if (TCPH_FLAGS(next->tcphdr) & TCP_FIN) {
+ 801b160:	683b      	ldr	r3, [r7, #0]
+ 801b162:	691b      	ldr	r3, [r3, #16]
+ 801b164:	899b      	ldrh	r3, [r3, #12]
+ 801b166:	b29b      	uxth	r3, r3
+ 801b168:	4618      	mov	r0, r3
+ 801b16a:	f7fa fee9 	bl	8015f40 <lwip_htons>
+ 801b16e:	4603      	mov	r3, r0
+ 801b170:	b2db      	uxtb	r3, r3
+ 801b172:	f003 0301 	and.w	r3, r3, #1
+ 801b176:	2b00      	cmp	r3, #0
+ 801b178:	d00d      	beq.n	801b196 <tcp_oos_insert_segment+0x7a>
+        TCPH_SET_FLAG(cseg->tcphdr, TCP_FIN);
+ 801b17a:	687b      	ldr	r3, [r7, #4]
+ 801b17c:	691b      	ldr	r3, [r3, #16]
+ 801b17e:	899b      	ldrh	r3, [r3, #12]
+ 801b180:	b29c      	uxth	r4, r3
+ 801b182:	2001      	movs	r0, #1
+ 801b184:	f7fa fedc 	bl	8015f40 <lwip_htons>
+ 801b188:	4603      	mov	r3, r0
+ 801b18a:	461a      	mov	r2, r3
+ 801b18c:	687b      	ldr	r3, [r7, #4]
+ 801b18e:	691b      	ldr	r3, [r3, #16]
+ 801b190:	4322      	orrs	r2, r4
+ 801b192:	b292      	uxth	r2, r2
+ 801b194:	819a      	strh	r2, [r3, #12]
+      }
+      old_seg = next;
+ 801b196:	683b      	ldr	r3, [r7, #0]
+ 801b198:	60fb      	str	r3, [r7, #12]
+      next = next->next;
+ 801b19a:	683b      	ldr	r3, [r7, #0]
+ 801b19c:	681b      	ldr	r3, [r3, #0]
+ 801b19e:	603b      	str	r3, [r7, #0]
+      tcp_seg_free(old_seg);
+ 801b1a0:	68f8      	ldr	r0, [r7, #12]
+ 801b1a2:	f7fe f97e 	bl	80194a2 <tcp_seg_free>
+    while (next &&
+ 801b1a6:	683b      	ldr	r3, [r7, #0]
+ 801b1a8:	2b00      	cmp	r3, #0
+ 801b1aa:	d00e      	beq.n	801b1ca <tcp_oos_insert_segment+0xae>
+           TCP_SEQ_GEQ((seqno + cseg->len),
+ 801b1ac:	687b      	ldr	r3, [r7, #4]
+ 801b1ae:	891b      	ldrh	r3, [r3, #8]
+ 801b1b0:	461a      	mov	r2, r3
+ 801b1b2:	4b1d      	ldr	r3, [pc, #116]	; (801b228 <tcp_oos_insert_segment+0x10c>)
+ 801b1b4:	681b      	ldr	r3, [r3, #0]
+ 801b1b6:	441a      	add	r2, r3
+ 801b1b8:	683b      	ldr	r3, [r7, #0]
+ 801b1ba:	691b      	ldr	r3, [r3, #16]
+ 801b1bc:	685b      	ldr	r3, [r3, #4]
+ 801b1be:	6839      	ldr	r1, [r7, #0]
+ 801b1c0:	8909      	ldrh	r1, [r1, #8]
+ 801b1c2:	440b      	add	r3, r1
+ 801b1c4:	1ad3      	subs	r3, r2, r3
+    while (next &&
+ 801b1c6:	2b00      	cmp	r3, #0
+ 801b1c8:	daca      	bge.n	801b160 <tcp_oos_insert_segment+0x44>
+    }
+    if (next &&
+ 801b1ca:	683b      	ldr	r3, [r7, #0]
+ 801b1cc:	2b00      	cmp	r3, #0
+ 801b1ce:	d01e      	beq.n	801b20e <tcp_oos_insert_segment+0xf2>
+        TCP_SEQ_GT(seqno + cseg->len, next->tcphdr->seqno)) {
+ 801b1d0:	687b      	ldr	r3, [r7, #4]
+ 801b1d2:	891b      	ldrh	r3, [r3, #8]
+ 801b1d4:	461a      	mov	r2, r3
+ 801b1d6:	4b14      	ldr	r3, [pc, #80]	; (801b228 <tcp_oos_insert_segment+0x10c>)
+ 801b1d8:	681b      	ldr	r3, [r3, #0]
+ 801b1da:	441a      	add	r2, r3
+ 801b1dc:	683b      	ldr	r3, [r7, #0]
+ 801b1de:	691b      	ldr	r3, [r3, #16]
+ 801b1e0:	685b      	ldr	r3, [r3, #4]
+ 801b1e2:	1ad3      	subs	r3, r2, r3
+    if (next &&
+ 801b1e4:	2b00      	cmp	r3, #0
+ 801b1e6:	dd12      	ble.n	801b20e <tcp_oos_insert_segment+0xf2>
+      /* We need to trim the incoming segment. */
+      cseg->len = (u16_t)(next->tcphdr->seqno - seqno);
+ 801b1e8:	683b      	ldr	r3, [r7, #0]
+ 801b1ea:	691b      	ldr	r3, [r3, #16]
+ 801b1ec:	685b      	ldr	r3, [r3, #4]
+ 801b1ee:	b29a      	uxth	r2, r3
+ 801b1f0:	4b0d      	ldr	r3, [pc, #52]	; (801b228 <tcp_oos_insert_segment+0x10c>)
+ 801b1f2:	681b      	ldr	r3, [r3, #0]
+ 801b1f4:	b29b      	uxth	r3, r3
+ 801b1f6:	1ad3      	subs	r3, r2, r3
+ 801b1f8:	b29a      	uxth	r2, r3
+ 801b1fa:	687b      	ldr	r3, [r7, #4]
+ 801b1fc:	811a      	strh	r2, [r3, #8]
+      pbuf_realloc(cseg->p, cseg->len);
+ 801b1fe:	687b      	ldr	r3, [r7, #4]
+ 801b200:	685a      	ldr	r2, [r3, #4]
+ 801b202:	687b      	ldr	r3, [r7, #4]
+ 801b204:	891b      	ldrh	r3, [r3, #8]
+ 801b206:	4619      	mov	r1, r3
+ 801b208:	4610      	mov	r0, r2
+ 801b20a:	f7fc faef 	bl	80177ec <pbuf_realloc>
+    }
+  }
+  cseg->next = next;
+ 801b20e:	687b      	ldr	r3, [r7, #4]
+ 801b210:	683a      	ldr	r2, [r7, #0]
+ 801b212:	601a      	str	r2, [r3, #0]
+}
+ 801b214:	bf00      	nop
+ 801b216:	3714      	adds	r7, #20
+ 801b218:	46bd      	mov	sp, r7
+ 801b21a:	bd90      	pop	{r4, r7, pc}
+ 801b21c:	08025338 	.word	0x08025338
+ 801b220:	080255f8 	.word	0x080255f8
+ 801b224:	08025384 	.word	0x08025384
+ 801b228:	2401a4bc 	.word	0x2401a4bc
+
+0801b22c <tcp_free_acked_segments>:
+
+/** Remove segments from a list if the incoming ACK acknowledges them */
+static struct tcp_seg *
+tcp_free_acked_segments(struct tcp_pcb *pcb, struct tcp_seg *seg_list, const char *dbg_list_name,
+                        struct tcp_seg *dbg_other_seg_list)
+{
+ 801b22c:	b5b0      	push	{r4, r5, r7, lr}
+ 801b22e:	b086      	sub	sp, #24
+ 801b230:	af00      	add	r7, sp, #0
+ 801b232:	60f8      	str	r0, [r7, #12]
+ 801b234:	60b9      	str	r1, [r7, #8]
+ 801b236:	607a      	str	r2, [r7, #4]
+ 801b238:	603b      	str	r3, [r7, #0]
+  u16_t clen;
+
+  LWIP_UNUSED_ARG(dbg_list_name);
+  LWIP_UNUSED_ARG(dbg_other_seg_list);
+
+  while (seg_list != NULL &&
+ 801b23a:	e03e      	b.n	801b2ba <tcp_free_acked_segments+0x8e>
+    LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: removing %"U32_F":%"U32_F" from pcb->%s\n",
+                                  lwip_ntohl(seg_list->tcphdr->seqno),
+                                  lwip_ntohl(seg_list->tcphdr->seqno) + TCP_TCPLEN(seg_list),
+                                  dbg_list_name));
+
+    next = seg_list;
+ 801b23c:	68bb      	ldr	r3, [r7, #8]
+ 801b23e:	617b      	str	r3, [r7, #20]
+    seg_list = seg_list->next;
+ 801b240:	68bb      	ldr	r3, [r7, #8]
+ 801b242:	681b      	ldr	r3, [r3, #0]
+ 801b244:	60bb      	str	r3, [r7, #8]
+
+    clen = pbuf_clen(next->p);
+ 801b246:	697b      	ldr	r3, [r7, #20]
+ 801b248:	685b      	ldr	r3, [r3, #4]
+ 801b24a:	4618      	mov	r0, r3
+ 801b24c:	f7fc fce2 	bl	8017c14 <pbuf_clen>
+ 801b250:	4603      	mov	r3, r0
+ 801b252:	827b      	strh	r3, [r7, #18]
+    LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_receive: queuelen %"TCPWNDSIZE_F" ... ",
+                                 (tcpwnd_size_t)pcb->snd_queuelen));
+    LWIP_ASSERT("pcb->snd_queuelen >= pbuf_clen(next->p)", (pcb->snd_queuelen >= clen));
+ 801b254:	68fb      	ldr	r3, [r7, #12]
+ 801b256:	f8b3 3066 	ldrh.w	r3, [r3, #102]	; 0x66
+ 801b25a:	8a7a      	ldrh	r2, [r7, #18]
+ 801b25c:	429a      	cmp	r2, r3
+ 801b25e:	d906      	bls.n	801b26e <tcp_free_acked_segments+0x42>
+ 801b260:	4b2a      	ldr	r3, [pc, #168]	; (801b30c <tcp_free_acked_segments+0xe0>)
+ 801b262:	f240 4257 	movw	r2, #1111	; 0x457
+ 801b266:	492a      	ldr	r1, [pc, #168]	; (801b310 <tcp_free_acked_segments+0xe4>)
+ 801b268:	482a      	ldr	r0, [pc, #168]	; (801b314 <tcp_free_acked_segments+0xe8>)
+ 801b26a:	f006 fb8d 	bl	8021988 <iprintf>
+
+    pcb->snd_queuelen = (u16_t)(pcb->snd_queuelen - clen);
+ 801b26e:	68fb      	ldr	r3, [r7, #12]
+ 801b270:	f8b3 2066 	ldrh.w	r2, [r3, #102]	; 0x66
+ 801b274:	8a7b      	ldrh	r3, [r7, #18]
+ 801b276:	1ad3      	subs	r3, r2, r3
+ 801b278:	b29a      	uxth	r2, r3
+ 801b27a:	68fb      	ldr	r3, [r7, #12]
+ 801b27c:	f8a3 2066 	strh.w	r2, [r3, #102]	; 0x66
+    recv_acked = (tcpwnd_size_t)(recv_acked + next->len);
+ 801b280:	697b      	ldr	r3, [r7, #20]
+ 801b282:	891a      	ldrh	r2, [r3, #8]
+ 801b284:	4b24      	ldr	r3, [pc, #144]	; (801b318 <tcp_free_acked_segments+0xec>)
+ 801b286:	881b      	ldrh	r3, [r3, #0]
+ 801b288:	4413      	add	r3, r2
+ 801b28a:	b29a      	uxth	r2, r3
+ 801b28c:	4b22      	ldr	r3, [pc, #136]	; (801b318 <tcp_free_acked_segments+0xec>)
+ 801b28e:	801a      	strh	r2, [r3, #0]
+    tcp_seg_free(next);
+ 801b290:	6978      	ldr	r0, [r7, #20]
+ 801b292:	f7fe f906 	bl	80194a2 <tcp_seg_free>
+
+    LWIP_DEBUGF(TCP_QLEN_DEBUG, ("%"TCPWNDSIZE_F" (after freeing %s)\n",
+                                 (tcpwnd_size_t)pcb->snd_queuelen,
+                                 dbg_list_name));
+    if (pcb->snd_queuelen != 0) {
+ 801b296:	68fb      	ldr	r3, [r7, #12]
+ 801b298:	f8b3 3066 	ldrh.w	r3, [r3, #102]	; 0x66
+ 801b29c:	2b00      	cmp	r3, #0
+ 801b29e:	d00c      	beq.n	801b2ba <tcp_free_acked_segments+0x8e>
+      LWIP_ASSERT("tcp_receive: valid queue length",
+ 801b2a0:	68bb      	ldr	r3, [r7, #8]
+ 801b2a2:	2b00      	cmp	r3, #0
+ 801b2a4:	d109      	bne.n	801b2ba <tcp_free_acked_segments+0x8e>
+ 801b2a6:	683b      	ldr	r3, [r7, #0]
+ 801b2a8:	2b00      	cmp	r3, #0
+ 801b2aa:	d106      	bne.n	801b2ba <tcp_free_acked_segments+0x8e>
+ 801b2ac:	4b17      	ldr	r3, [pc, #92]	; (801b30c <tcp_free_acked_segments+0xe0>)
+ 801b2ae:	f240 4261 	movw	r2, #1121	; 0x461
+ 801b2b2:	491a      	ldr	r1, [pc, #104]	; (801b31c <tcp_free_acked_segments+0xf0>)
+ 801b2b4:	4817      	ldr	r0, [pc, #92]	; (801b314 <tcp_free_acked_segments+0xe8>)
+ 801b2b6:	f006 fb67 	bl	8021988 <iprintf>
+  while (seg_list != NULL &&
+ 801b2ba:	68bb      	ldr	r3, [r7, #8]
+ 801b2bc:	2b00      	cmp	r3, #0
+ 801b2be:	d020      	beq.n	801b302 <tcp_free_acked_segments+0xd6>
+         TCP_SEQ_LEQ(lwip_ntohl(seg_list->tcphdr->seqno) +
+ 801b2c0:	68bb      	ldr	r3, [r7, #8]
+ 801b2c2:	691b      	ldr	r3, [r3, #16]
+ 801b2c4:	685b      	ldr	r3, [r3, #4]
+ 801b2c6:	4618      	mov	r0, r3
+ 801b2c8:	f7fa fe4f 	bl	8015f6a <lwip_htonl>
+ 801b2cc:	4604      	mov	r4, r0
+ 801b2ce:	68bb      	ldr	r3, [r7, #8]
+ 801b2d0:	891b      	ldrh	r3, [r3, #8]
+ 801b2d2:	461d      	mov	r5, r3
+ 801b2d4:	68bb      	ldr	r3, [r7, #8]
+ 801b2d6:	691b      	ldr	r3, [r3, #16]
+ 801b2d8:	899b      	ldrh	r3, [r3, #12]
+ 801b2da:	b29b      	uxth	r3, r3
+ 801b2dc:	4618      	mov	r0, r3
+ 801b2de:	f7fa fe2f 	bl	8015f40 <lwip_htons>
+ 801b2e2:	4603      	mov	r3, r0
+ 801b2e4:	b2db      	uxtb	r3, r3
+ 801b2e6:	f003 0303 	and.w	r3, r3, #3
+ 801b2ea:	2b00      	cmp	r3, #0
+ 801b2ec:	d001      	beq.n	801b2f2 <tcp_free_acked_segments+0xc6>
+ 801b2ee:	2301      	movs	r3, #1
+ 801b2f0:	e000      	b.n	801b2f4 <tcp_free_acked_segments+0xc8>
+ 801b2f2:	2300      	movs	r3, #0
+ 801b2f4:	442b      	add	r3, r5
+ 801b2f6:	18e2      	adds	r2, r4, r3
+ 801b2f8:	4b09      	ldr	r3, [pc, #36]	; (801b320 <tcp_free_acked_segments+0xf4>)
+ 801b2fa:	681b      	ldr	r3, [r3, #0]
+ 801b2fc:	1ad3      	subs	r3, r2, r3
+  while (seg_list != NULL &&
+ 801b2fe:	2b00      	cmp	r3, #0
+ 801b300:	dd9c      	ble.n	801b23c <tcp_free_acked_segments+0x10>
+                  seg_list != NULL || dbg_other_seg_list != NULL);
+    }
+  }
+  return seg_list;
+ 801b302:	68bb      	ldr	r3, [r7, #8]
+}
+ 801b304:	4618      	mov	r0, r3
+ 801b306:	3718      	adds	r7, #24
+ 801b308:	46bd      	mov	sp, r7
+ 801b30a:	bdb0      	pop	{r4, r5, r7, pc}
+ 801b30c:	08025338 	.word	0x08025338
+ 801b310:	08025620 	.word	0x08025620
+ 801b314:	08025384 	.word	0x08025384
+ 801b318:	2401a4c4 	.word	0x2401a4c4
+ 801b31c:	08025648 	.word	0x08025648
+ 801b320:	2401a4c0 	.word	0x2401a4c0
+
+0801b324 <tcp_receive>:
+ *
+ * Called from tcp_process().
+ */
+static void
+tcp_receive(struct tcp_pcb *pcb)
+{
+ 801b324:	b5b0      	push	{r4, r5, r7, lr}
+ 801b326:	b094      	sub	sp, #80	; 0x50
+ 801b328:	af00      	add	r7, sp, #0
+ 801b32a:	6078      	str	r0, [r7, #4]
+  s16_t m;
+  u32_t right_wnd_edge;
+  int found_dupack = 0;
+ 801b32c:	2300      	movs	r3, #0
+ 801b32e:	64bb      	str	r3, [r7, #72]	; 0x48
+
+  LWIP_ASSERT("tcp_receive: invalid pcb", pcb != NULL);
+ 801b330:	687b      	ldr	r3, [r7, #4]
+ 801b332:	2b00      	cmp	r3, #0
+ 801b334:	d106      	bne.n	801b344 <tcp_receive+0x20>
+ 801b336:	4b91      	ldr	r3, [pc, #580]	; (801b57c <tcp_receive+0x258>)
+ 801b338:	f240 427b 	movw	r2, #1147	; 0x47b
+ 801b33c:	4990      	ldr	r1, [pc, #576]	; (801b580 <tcp_receive+0x25c>)
+ 801b33e:	4891      	ldr	r0, [pc, #580]	; (801b584 <tcp_receive+0x260>)
+ 801b340:	f006 fb22 	bl	8021988 <iprintf>
+  LWIP_ASSERT("tcp_receive: wrong state", pcb->state >= ESTABLISHED);
+ 801b344:	687b      	ldr	r3, [r7, #4]
+ 801b346:	7d1b      	ldrb	r3, [r3, #20]
+ 801b348:	2b03      	cmp	r3, #3
+ 801b34a:	d806      	bhi.n	801b35a <tcp_receive+0x36>
+ 801b34c:	4b8b      	ldr	r3, [pc, #556]	; (801b57c <tcp_receive+0x258>)
+ 801b34e:	f240 427c 	movw	r2, #1148	; 0x47c
+ 801b352:	498d      	ldr	r1, [pc, #564]	; (801b588 <tcp_receive+0x264>)
+ 801b354:	488b      	ldr	r0, [pc, #556]	; (801b584 <tcp_receive+0x260>)
+ 801b356:	f006 fb17 	bl	8021988 <iprintf>
+
+  if (flags & TCP_ACK) {
+ 801b35a:	4b8c      	ldr	r3, [pc, #560]	; (801b58c <tcp_receive+0x268>)
+ 801b35c:	781b      	ldrb	r3, [r3, #0]
+ 801b35e:	f003 0310 	and.w	r3, r3, #16
+ 801b362:	2b00      	cmp	r3, #0
+ 801b364:	f000 8264 	beq.w	801b830 <tcp_receive+0x50c>
+    right_wnd_edge = pcb->snd_wnd + pcb->snd_wl2;
+ 801b368:	687b      	ldr	r3, [r7, #4]
+ 801b36a:	f8b3 3060 	ldrh.w	r3, [r3, #96]	; 0x60
+ 801b36e:	461a      	mov	r2, r3
+ 801b370:	687b      	ldr	r3, [r7, #4]
+ 801b372:	6d9b      	ldr	r3, [r3, #88]	; 0x58
+ 801b374:	4413      	add	r3, r2
+ 801b376:	633b      	str	r3, [r7, #48]	; 0x30
+
+    /* Update window. */
+    if (TCP_SEQ_LT(pcb->snd_wl1, seqno) ||
+ 801b378:	687b      	ldr	r3, [r7, #4]
+ 801b37a:	6d5a      	ldr	r2, [r3, #84]	; 0x54
+ 801b37c:	4b84      	ldr	r3, [pc, #528]	; (801b590 <tcp_receive+0x26c>)
+ 801b37e:	681b      	ldr	r3, [r3, #0]
+ 801b380:	1ad3      	subs	r3, r2, r3
+ 801b382:	2b00      	cmp	r3, #0
+ 801b384:	db1b      	blt.n	801b3be <tcp_receive+0x9a>
+        (pcb->snd_wl1 == seqno && TCP_SEQ_LT(pcb->snd_wl2, ackno)) ||
+ 801b386:	687b      	ldr	r3, [r7, #4]
+ 801b388:	6d5a      	ldr	r2, [r3, #84]	; 0x54
+ 801b38a:	4b81      	ldr	r3, [pc, #516]	; (801b590 <tcp_receive+0x26c>)
+ 801b38c:	681b      	ldr	r3, [r3, #0]
+    if (TCP_SEQ_LT(pcb->snd_wl1, seqno) ||
+ 801b38e:	429a      	cmp	r2, r3
+ 801b390:	d106      	bne.n	801b3a0 <tcp_receive+0x7c>
+        (pcb->snd_wl1 == seqno && TCP_SEQ_LT(pcb->snd_wl2, ackno)) ||
+ 801b392:	687b      	ldr	r3, [r7, #4]
+ 801b394:	6d9a      	ldr	r2, [r3, #88]	; 0x58
+ 801b396:	4b7f      	ldr	r3, [pc, #508]	; (801b594 <tcp_receive+0x270>)
+ 801b398:	681b      	ldr	r3, [r3, #0]
+ 801b39a:	1ad3      	subs	r3, r2, r3
+ 801b39c:	2b00      	cmp	r3, #0
+ 801b39e:	db0e      	blt.n	801b3be <tcp_receive+0x9a>
+        (pcb->snd_wl2 == ackno && (u32_t)SND_WND_SCALE(pcb, tcphdr->wnd) > pcb->snd_wnd)) {
+ 801b3a0:	687b      	ldr	r3, [r7, #4]
+ 801b3a2:	6d9a      	ldr	r2, [r3, #88]	; 0x58
+ 801b3a4:	4b7b      	ldr	r3, [pc, #492]	; (801b594 <tcp_receive+0x270>)
+ 801b3a6:	681b      	ldr	r3, [r3, #0]
+        (pcb->snd_wl1 == seqno && TCP_SEQ_LT(pcb->snd_wl2, ackno)) ||
+ 801b3a8:	429a      	cmp	r2, r3
+ 801b3aa:	d125      	bne.n	801b3f8 <tcp_receive+0xd4>
+        (pcb->snd_wl2 == ackno && (u32_t)SND_WND_SCALE(pcb, tcphdr->wnd) > pcb->snd_wnd)) {
+ 801b3ac:	4b7a      	ldr	r3, [pc, #488]	; (801b598 <tcp_receive+0x274>)
+ 801b3ae:	681b      	ldr	r3, [r3, #0]
+ 801b3b0:	89db      	ldrh	r3, [r3, #14]
+ 801b3b2:	b29a      	uxth	r2, r3
+ 801b3b4:	687b      	ldr	r3, [r7, #4]
+ 801b3b6:	f8b3 3060 	ldrh.w	r3, [r3, #96]	; 0x60
+ 801b3ba:	429a      	cmp	r2, r3
+ 801b3bc:	d91c      	bls.n	801b3f8 <tcp_receive+0xd4>
+      pcb->snd_wnd = SND_WND_SCALE(pcb, tcphdr->wnd);
+ 801b3be:	4b76      	ldr	r3, [pc, #472]	; (801b598 <tcp_receive+0x274>)
+ 801b3c0:	681b      	ldr	r3, [r3, #0]
+ 801b3c2:	89db      	ldrh	r3, [r3, #14]
+ 801b3c4:	b29a      	uxth	r2, r3
+ 801b3c6:	687b      	ldr	r3, [r7, #4]
+ 801b3c8:	f8a3 2060 	strh.w	r2, [r3, #96]	; 0x60
+      /* keep track of the biggest window announced by the remote host to calculate
+         the maximum segment size */
+      if (pcb->snd_wnd_max < pcb->snd_wnd) {
+ 801b3cc:	687b      	ldr	r3, [r7, #4]
+ 801b3ce:	f8b3 2062 	ldrh.w	r2, [r3, #98]	; 0x62
+ 801b3d2:	687b      	ldr	r3, [r7, #4]
+ 801b3d4:	f8b3 3060 	ldrh.w	r3, [r3, #96]	; 0x60
+ 801b3d8:	429a      	cmp	r2, r3
+ 801b3da:	d205      	bcs.n	801b3e8 <tcp_receive+0xc4>
+        pcb->snd_wnd_max = pcb->snd_wnd;
+ 801b3dc:	687b      	ldr	r3, [r7, #4]
+ 801b3de:	f8b3 2060 	ldrh.w	r2, [r3, #96]	; 0x60
+ 801b3e2:	687b      	ldr	r3, [r7, #4]
+ 801b3e4:	f8a3 2062 	strh.w	r2, [r3, #98]	; 0x62
+      }
+      pcb->snd_wl1 = seqno;
+ 801b3e8:	4b69      	ldr	r3, [pc, #420]	; (801b590 <tcp_receive+0x26c>)
+ 801b3ea:	681a      	ldr	r2, [r3, #0]
+ 801b3ec:	687b      	ldr	r3, [r7, #4]
+ 801b3ee:	655a      	str	r2, [r3, #84]	; 0x54
+      pcb->snd_wl2 = ackno;
+ 801b3f0:	4b68      	ldr	r3, [pc, #416]	; (801b594 <tcp_receive+0x270>)
+ 801b3f2:	681a      	ldr	r2, [r3, #0]
+ 801b3f4:	687b      	ldr	r3, [r7, #4]
+ 801b3f6:	659a      	str	r2, [r3, #88]	; 0x58
+     * If it only passes 1, should reset dupack counter
+     *
+     */
+
+    /* Clause 1 */
+    if (TCP_SEQ_LEQ(ackno, pcb->lastack)) {
+ 801b3f8:	4b66      	ldr	r3, [pc, #408]	; (801b594 <tcp_receive+0x270>)
+ 801b3fa:	681a      	ldr	r2, [r3, #0]
+ 801b3fc:	687b      	ldr	r3, [r7, #4]
+ 801b3fe:	6c5b      	ldr	r3, [r3, #68]	; 0x44
+ 801b400:	1ad3      	subs	r3, r2, r3
+ 801b402:	2b00      	cmp	r3, #0
+ 801b404:	dc58      	bgt.n	801b4b8 <tcp_receive+0x194>
+      /* Clause 2 */
+      if (tcplen == 0) {
+ 801b406:	4b65      	ldr	r3, [pc, #404]	; (801b59c <tcp_receive+0x278>)
+ 801b408:	881b      	ldrh	r3, [r3, #0]
+ 801b40a:	2b00      	cmp	r3, #0
+ 801b40c:	d14b      	bne.n	801b4a6 <tcp_receive+0x182>
+        /* Clause 3 */
+        if (pcb->snd_wl2 + pcb->snd_wnd == right_wnd_edge) {
+ 801b40e:	687b      	ldr	r3, [r7, #4]
+ 801b410:	6d9b      	ldr	r3, [r3, #88]	; 0x58
+ 801b412:	687a      	ldr	r2, [r7, #4]
+ 801b414:	f8b2 2060 	ldrh.w	r2, [r2, #96]	; 0x60
+ 801b418:	4413      	add	r3, r2
+ 801b41a:	6b3a      	ldr	r2, [r7, #48]	; 0x30
+ 801b41c:	429a      	cmp	r2, r3
+ 801b41e:	d142      	bne.n	801b4a6 <tcp_receive+0x182>
+          /* Clause 4 */
+          if (pcb->rtime >= 0) {
+ 801b420:	687b      	ldr	r3, [r7, #4]
+ 801b422:	f9b3 3030 	ldrsh.w	r3, [r3, #48]	; 0x30
+ 801b426:	2b00      	cmp	r3, #0
+ 801b428:	db3d      	blt.n	801b4a6 <tcp_receive+0x182>
+            /* Clause 5 */
+            if (pcb->lastack == ackno) {
+ 801b42a:	687b      	ldr	r3, [r7, #4]
+ 801b42c:	6c5a      	ldr	r2, [r3, #68]	; 0x44
+ 801b42e:	4b59      	ldr	r3, [pc, #356]	; (801b594 <tcp_receive+0x270>)
+ 801b430:	681b      	ldr	r3, [r3, #0]
+ 801b432:	429a      	cmp	r2, r3
+ 801b434:	d137      	bne.n	801b4a6 <tcp_receive+0x182>
+              found_dupack = 1;
+ 801b436:	2301      	movs	r3, #1
+ 801b438:	64bb      	str	r3, [r7, #72]	; 0x48
+              if ((u8_t)(pcb->dupacks + 1) > pcb->dupacks) {
+ 801b43a:	687b      	ldr	r3, [r7, #4]
+ 801b43c:	f893 3043 	ldrb.w	r3, [r3, #67]	; 0x43
+ 801b440:	2bff      	cmp	r3, #255	; 0xff
+ 801b442:	d007      	beq.n	801b454 <tcp_receive+0x130>
+                ++pcb->dupacks;
+ 801b444:	687b      	ldr	r3, [r7, #4]
+ 801b446:	f893 3043 	ldrb.w	r3, [r3, #67]	; 0x43
+ 801b44a:	3301      	adds	r3, #1
+ 801b44c:	b2da      	uxtb	r2, r3
+ 801b44e:	687b      	ldr	r3, [r7, #4]
+ 801b450:	f883 2043 	strb.w	r2, [r3, #67]	; 0x43
+              }
+              if (pcb->dupacks > 3) {
+ 801b454:	687b      	ldr	r3, [r7, #4]
+ 801b456:	f893 3043 	ldrb.w	r3, [r3, #67]	; 0x43
+ 801b45a:	2b03      	cmp	r3, #3
+ 801b45c:	d91b      	bls.n	801b496 <tcp_receive+0x172>
+                /* Inflate the congestion window */
+                TCP_WND_INC(pcb->cwnd, pcb->mss);
+ 801b45e:	687b      	ldr	r3, [r7, #4]
+ 801b460:	f8b3 2048 	ldrh.w	r2, [r3, #72]	; 0x48
+ 801b464:	687b      	ldr	r3, [r7, #4]
+ 801b466:	8e5b      	ldrh	r3, [r3, #50]	; 0x32
+ 801b468:	4413      	add	r3, r2
+ 801b46a:	b29a      	uxth	r2, r3
+ 801b46c:	687b      	ldr	r3, [r7, #4]
+ 801b46e:	f8b3 3048 	ldrh.w	r3, [r3, #72]	; 0x48
+ 801b472:	429a      	cmp	r2, r3
+ 801b474:	d30a      	bcc.n	801b48c <tcp_receive+0x168>
+ 801b476:	687b      	ldr	r3, [r7, #4]
+ 801b478:	f8b3 2048 	ldrh.w	r2, [r3, #72]	; 0x48
+ 801b47c:	687b      	ldr	r3, [r7, #4]
+ 801b47e:	8e5b      	ldrh	r3, [r3, #50]	; 0x32
+ 801b480:	4413      	add	r3, r2
+ 801b482:	b29a      	uxth	r2, r3
+ 801b484:	687b      	ldr	r3, [r7, #4]
+ 801b486:	f8a3 2048 	strh.w	r2, [r3, #72]	; 0x48
+ 801b48a:	e004      	b.n	801b496 <tcp_receive+0x172>
+ 801b48c:	687b      	ldr	r3, [r7, #4]
+ 801b48e:	f64f 72ff 	movw	r2, #65535	; 0xffff
+ 801b492:	f8a3 2048 	strh.w	r2, [r3, #72]	; 0x48
+              }
+              if (pcb->dupacks >= 3) {
+ 801b496:	687b      	ldr	r3, [r7, #4]
+ 801b498:	f893 3043 	ldrb.w	r3, [r3, #67]	; 0x43
+ 801b49c:	2b02      	cmp	r3, #2
+ 801b49e:	d902      	bls.n	801b4a6 <tcp_receive+0x182>
+                /* Do fast retransmit (checked via TF_INFR, not via dupacks count) */
+                tcp_rexmit_fast(pcb);
+ 801b4a0:	6878      	ldr	r0, [r7, #4]
+ 801b4a2:	f002 fbb1 	bl	801dc08 <tcp_rexmit_fast>
+          }
+        }
+      }
+      /* If Clause (1) or more is true, but not a duplicate ack, reset
+       * count of consecutive duplicate acks */
+      if (!found_dupack) {
+ 801b4a6:	6cbb      	ldr	r3, [r7, #72]	; 0x48
+ 801b4a8:	2b00      	cmp	r3, #0
+ 801b4aa:	f040 8161 	bne.w	801b770 <tcp_receive+0x44c>
+        pcb->dupacks = 0;
+ 801b4ae:	687b      	ldr	r3, [r7, #4]
+ 801b4b0:	2200      	movs	r2, #0
+ 801b4b2:	f883 2043 	strb.w	r2, [r3, #67]	; 0x43
+ 801b4b6:	e15b      	b.n	801b770 <tcp_receive+0x44c>
+      }
+    } else if (TCP_SEQ_BETWEEN(ackno, pcb->lastack + 1, pcb->snd_nxt)) {
+ 801b4b8:	4b36      	ldr	r3, [pc, #216]	; (801b594 <tcp_receive+0x270>)
+ 801b4ba:	681a      	ldr	r2, [r3, #0]
+ 801b4bc:	687b      	ldr	r3, [r7, #4]
+ 801b4be:	6c5b      	ldr	r3, [r3, #68]	; 0x44
+ 801b4c0:	1ad3      	subs	r3, r2, r3
+ 801b4c2:	3b01      	subs	r3, #1
+ 801b4c4:	2b00      	cmp	r3, #0
+ 801b4c6:	f2c0 814e 	blt.w	801b766 <tcp_receive+0x442>
+ 801b4ca:	4b32      	ldr	r3, [pc, #200]	; (801b594 <tcp_receive+0x270>)
+ 801b4cc:	681a      	ldr	r2, [r3, #0]
+ 801b4ce:	687b      	ldr	r3, [r7, #4]
+ 801b4d0:	6d1b      	ldr	r3, [r3, #80]	; 0x50
+ 801b4d2:	1ad3      	subs	r3, r2, r3
+ 801b4d4:	2b00      	cmp	r3, #0
+ 801b4d6:	f300 8146 	bgt.w	801b766 <tcp_receive+0x442>
+      tcpwnd_size_t acked;
+
+      /* Reset the "IN Fast Retransmit" flag, since we are no longer
+         in fast retransmit. Also reset the congestion window to the
+         slow start threshold. */
+      if (pcb->flags & TF_INFR) {
+ 801b4da:	687b      	ldr	r3, [r7, #4]
+ 801b4dc:	8b5b      	ldrh	r3, [r3, #26]
+ 801b4de:	f003 0304 	and.w	r3, r3, #4
+ 801b4e2:	2b00      	cmp	r3, #0
+ 801b4e4:	d010      	beq.n	801b508 <tcp_receive+0x1e4>
+        tcp_clear_flags(pcb, TF_INFR);
+ 801b4e6:	687b      	ldr	r3, [r7, #4]
+ 801b4e8:	8b5b      	ldrh	r3, [r3, #26]
+ 801b4ea:	f023 0304 	bic.w	r3, r3, #4
+ 801b4ee:	b29a      	uxth	r2, r3
+ 801b4f0:	687b      	ldr	r3, [r7, #4]
+ 801b4f2:	835a      	strh	r2, [r3, #26]
+        pcb->cwnd = pcb->ssthresh;
+ 801b4f4:	687b      	ldr	r3, [r7, #4]
+ 801b4f6:	f8b3 204a 	ldrh.w	r2, [r3, #74]	; 0x4a
+ 801b4fa:	687b      	ldr	r3, [r7, #4]
+ 801b4fc:	f8a3 2048 	strh.w	r2, [r3, #72]	; 0x48
+        pcb->bytes_acked = 0;
+ 801b500:	687b      	ldr	r3, [r7, #4]
+ 801b502:	2200      	movs	r2, #0
+ 801b504:	f8a3 206a 	strh.w	r2, [r3, #106]	; 0x6a
+      }
+
+      /* Reset the number of retransmissions. */
+      pcb->nrtx = 0;
+ 801b508:	687b      	ldr	r3, [r7, #4]
+ 801b50a:	2200      	movs	r2, #0
+ 801b50c:	f883 2042 	strb.w	r2, [r3, #66]	; 0x42
+
+      /* Reset the retransmission time-out. */
+      pcb->rto = (s16_t)((pcb->sa >> 3) + pcb->sv);
+ 801b510:	687b      	ldr	r3, [r7, #4]
+ 801b512:	f9b3 303c 	ldrsh.w	r3, [r3, #60]	; 0x3c
+ 801b516:	10db      	asrs	r3, r3, #3
+ 801b518:	b21b      	sxth	r3, r3
+ 801b51a:	b29a      	uxth	r2, r3
+ 801b51c:	687b      	ldr	r3, [r7, #4]
+ 801b51e:	f9b3 303e 	ldrsh.w	r3, [r3, #62]	; 0x3e
+ 801b522:	b29b      	uxth	r3, r3
+ 801b524:	4413      	add	r3, r2
+ 801b526:	b29b      	uxth	r3, r3
+ 801b528:	b21a      	sxth	r2, r3
+ 801b52a:	687b      	ldr	r3, [r7, #4]
+ 801b52c:	f8a3 2040 	strh.w	r2, [r3, #64]	; 0x40
+
+      /* Record how much data this ACK acks */
+      acked = (tcpwnd_size_t)(ackno - pcb->lastack);
+ 801b530:	4b18      	ldr	r3, [pc, #96]	; (801b594 <tcp_receive+0x270>)
+ 801b532:	681b      	ldr	r3, [r3, #0]
+ 801b534:	b29a      	uxth	r2, r3
+ 801b536:	687b      	ldr	r3, [r7, #4]
+ 801b538:	6c5b      	ldr	r3, [r3, #68]	; 0x44
+ 801b53a:	b29b      	uxth	r3, r3
+ 801b53c:	1ad3      	subs	r3, r2, r3
+ 801b53e:	85fb      	strh	r3, [r7, #46]	; 0x2e
+
+      /* Reset the fast retransmit variables. */
+      pcb->dupacks = 0;
+ 801b540:	687b      	ldr	r3, [r7, #4]
+ 801b542:	2200      	movs	r2, #0
+ 801b544:	f883 2043 	strb.w	r2, [r3, #67]	; 0x43
+      pcb->lastack = ackno;
+ 801b548:	4b12      	ldr	r3, [pc, #72]	; (801b594 <tcp_receive+0x270>)
+ 801b54a:	681a      	ldr	r2, [r3, #0]
+ 801b54c:	687b      	ldr	r3, [r7, #4]
+ 801b54e:	645a      	str	r2, [r3, #68]	; 0x44
+
+      /* Update the congestion control variables (cwnd and
+         ssthresh). */
+      if (pcb->state >= ESTABLISHED) {
+ 801b550:	687b      	ldr	r3, [r7, #4]
+ 801b552:	7d1b      	ldrb	r3, [r3, #20]
+ 801b554:	2b03      	cmp	r3, #3
+ 801b556:	f240 8097 	bls.w	801b688 <tcp_receive+0x364>
+        if (pcb->cwnd < pcb->ssthresh) {
+ 801b55a:	687b      	ldr	r3, [r7, #4]
+ 801b55c:	f8b3 2048 	ldrh.w	r2, [r3, #72]	; 0x48
+ 801b560:	687b      	ldr	r3, [r7, #4]
+ 801b562:	f8b3 304a 	ldrh.w	r3, [r3, #74]	; 0x4a
+ 801b566:	429a      	cmp	r2, r3
+ 801b568:	d245      	bcs.n	801b5f6 <tcp_receive+0x2d2>
+          tcpwnd_size_t increase;
+          /* limit to 1 SMSS segment during period following RTO */
+          u8_t num_seg = (pcb->flags & TF_RTO) ? 1 : 2;
+ 801b56a:	687b      	ldr	r3, [r7, #4]
+ 801b56c:	8b5b      	ldrh	r3, [r3, #26]
+ 801b56e:	f403 6300 	and.w	r3, r3, #2048	; 0x800
+ 801b572:	2b00      	cmp	r3, #0
+ 801b574:	d014      	beq.n	801b5a0 <tcp_receive+0x27c>
+ 801b576:	2301      	movs	r3, #1
+ 801b578:	e013      	b.n	801b5a2 <tcp_receive+0x27e>
+ 801b57a:	bf00      	nop
+ 801b57c:	08025338 	.word	0x08025338
+ 801b580:	08025668 	.word	0x08025668
+ 801b584:	08025384 	.word	0x08025384
+ 801b588:	08025684 	.word	0x08025684
+ 801b58c:	2401a4c8 	.word	0x2401a4c8
+ 801b590:	2401a4bc 	.word	0x2401a4bc
+ 801b594:	2401a4c0 	.word	0x2401a4c0
+ 801b598:	2401a4ac 	.word	0x2401a4ac
+ 801b59c:	2401a4c6 	.word	0x2401a4c6
+ 801b5a0:	2302      	movs	r3, #2
+ 801b5a2:	f887 302d 	strb.w	r3, [r7, #45]	; 0x2d
+          /* RFC 3465, section 2.2 Slow Start */
+          increase = LWIP_MIN(acked, (tcpwnd_size_t)(num_seg * pcb->mss));
+ 801b5a6:	f897 302d 	ldrb.w	r3, [r7, #45]	; 0x2d
+ 801b5aa:	b29a      	uxth	r2, r3
+ 801b5ac:	687b      	ldr	r3, [r7, #4]
+ 801b5ae:	8e5b      	ldrh	r3, [r3, #50]	; 0x32
+ 801b5b0:	fb12 f303 	smulbb	r3, r2, r3
+ 801b5b4:	b29b      	uxth	r3, r3
+ 801b5b6:	8dfa      	ldrh	r2, [r7, #46]	; 0x2e
+ 801b5b8:	4293      	cmp	r3, r2
+ 801b5ba:	bf28      	it	cs
+ 801b5bc:	4613      	movcs	r3, r2
+ 801b5be:	857b      	strh	r3, [r7, #42]	; 0x2a
+          TCP_WND_INC(pcb->cwnd, increase);
+ 801b5c0:	687b      	ldr	r3, [r7, #4]
+ 801b5c2:	f8b3 2048 	ldrh.w	r2, [r3, #72]	; 0x48
+ 801b5c6:	8d7b      	ldrh	r3, [r7, #42]	; 0x2a
+ 801b5c8:	4413      	add	r3, r2
+ 801b5ca:	b29a      	uxth	r2, r3
+ 801b5cc:	687b      	ldr	r3, [r7, #4]
+ 801b5ce:	f8b3 3048 	ldrh.w	r3, [r3, #72]	; 0x48
+ 801b5d2:	429a      	cmp	r2, r3
+ 801b5d4:	d309      	bcc.n	801b5ea <tcp_receive+0x2c6>
+ 801b5d6:	687b      	ldr	r3, [r7, #4]
+ 801b5d8:	f8b3 2048 	ldrh.w	r2, [r3, #72]	; 0x48
+ 801b5dc:	8d7b      	ldrh	r3, [r7, #42]	; 0x2a
+ 801b5de:	4413      	add	r3, r2
+ 801b5e0:	b29a      	uxth	r2, r3
+ 801b5e2:	687b      	ldr	r3, [r7, #4]
+ 801b5e4:	f8a3 2048 	strh.w	r2, [r3, #72]	; 0x48
+ 801b5e8:	e04e      	b.n	801b688 <tcp_receive+0x364>
+ 801b5ea:	687b      	ldr	r3, [r7, #4]
+ 801b5ec:	f64f 72ff 	movw	r2, #65535	; 0xffff
+ 801b5f0:	f8a3 2048 	strh.w	r2, [r3, #72]	; 0x48
+ 801b5f4:	e048      	b.n	801b688 <tcp_receive+0x364>
+          LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_receive: slow start cwnd %"TCPWNDSIZE_F"\n", pcb->cwnd));
+        } else {
+          /* RFC 3465, section 2.1 Congestion Avoidance */
+          TCP_WND_INC(pcb->bytes_acked, acked);
+ 801b5f6:	687b      	ldr	r3, [r7, #4]
+ 801b5f8:	f8b3 206a 	ldrh.w	r2, [r3, #106]	; 0x6a
+ 801b5fc:	8dfb      	ldrh	r3, [r7, #46]	; 0x2e
+ 801b5fe:	4413      	add	r3, r2
+ 801b600:	b29a      	uxth	r2, r3
+ 801b602:	687b      	ldr	r3, [r7, #4]
+ 801b604:	f8b3 306a 	ldrh.w	r3, [r3, #106]	; 0x6a
+ 801b608:	429a      	cmp	r2, r3
+ 801b60a:	d309      	bcc.n	801b620 <tcp_receive+0x2fc>
+ 801b60c:	687b      	ldr	r3, [r7, #4]
+ 801b60e:	f8b3 206a 	ldrh.w	r2, [r3, #106]	; 0x6a
+ 801b612:	8dfb      	ldrh	r3, [r7, #46]	; 0x2e
+ 801b614:	4413      	add	r3, r2
+ 801b616:	b29a      	uxth	r2, r3
+ 801b618:	687b      	ldr	r3, [r7, #4]
+ 801b61a:	f8a3 206a 	strh.w	r2, [r3, #106]	; 0x6a
+ 801b61e:	e004      	b.n	801b62a <tcp_receive+0x306>
+ 801b620:	687b      	ldr	r3, [r7, #4]
+ 801b622:	f64f 72ff 	movw	r2, #65535	; 0xffff
+ 801b626:	f8a3 206a 	strh.w	r2, [r3, #106]	; 0x6a
+          if (pcb->bytes_acked >= pcb->cwnd) {
+ 801b62a:	687b      	ldr	r3, [r7, #4]
+ 801b62c:	f8b3 206a 	ldrh.w	r2, [r3, #106]	; 0x6a
+ 801b630:	687b      	ldr	r3, [r7, #4]
+ 801b632:	f8b3 3048 	ldrh.w	r3, [r3, #72]	; 0x48
+ 801b636:	429a      	cmp	r2, r3
+ 801b638:	d326      	bcc.n	801b688 <tcp_receive+0x364>
+            pcb->bytes_acked = (tcpwnd_size_t)(pcb->bytes_acked - pcb->cwnd);
+ 801b63a:	687b      	ldr	r3, [r7, #4]
+ 801b63c:	f8b3 206a 	ldrh.w	r2, [r3, #106]	; 0x6a
+ 801b640:	687b      	ldr	r3, [r7, #4]
+ 801b642:	f8b3 3048 	ldrh.w	r3, [r3, #72]	; 0x48
+ 801b646:	1ad3      	subs	r3, r2, r3
+ 801b648:	b29a      	uxth	r2, r3
+ 801b64a:	687b      	ldr	r3, [r7, #4]
+ 801b64c:	f8a3 206a 	strh.w	r2, [r3, #106]	; 0x6a
+            TCP_WND_INC(pcb->cwnd, pcb->mss);
+ 801b650:	687b      	ldr	r3, [r7, #4]
+ 801b652:	f8b3 2048 	ldrh.w	r2, [r3, #72]	; 0x48
+ 801b656:	687b      	ldr	r3, [r7, #4]
+ 801b658:	8e5b      	ldrh	r3, [r3, #50]	; 0x32
+ 801b65a:	4413      	add	r3, r2
+ 801b65c:	b29a      	uxth	r2, r3
+ 801b65e:	687b      	ldr	r3, [r7, #4]
+ 801b660:	f8b3 3048 	ldrh.w	r3, [r3, #72]	; 0x48
+ 801b664:	429a      	cmp	r2, r3
+ 801b666:	d30a      	bcc.n	801b67e <tcp_receive+0x35a>
+ 801b668:	687b      	ldr	r3, [r7, #4]
+ 801b66a:	f8b3 2048 	ldrh.w	r2, [r3, #72]	; 0x48
+ 801b66e:	687b      	ldr	r3, [r7, #4]
+ 801b670:	8e5b      	ldrh	r3, [r3, #50]	; 0x32
+ 801b672:	4413      	add	r3, r2
+ 801b674:	b29a      	uxth	r2, r3
+ 801b676:	687b      	ldr	r3, [r7, #4]
+ 801b678:	f8a3 2048 	strh.w	r2, [r3, #72]	; 0x48
+ 801b67c:	e004      	b.n	801b688 <tcp_receive+0x364>
+ 801b67e:	687b      	ldr	r3, [r7, #4]
+ 801b680:	f64f 72ff 	movw	r2, #65535	; 0xffff
+ 801b684:	f8a3 2048 	strh.w	r2, [r3, #72]	; 0x48
+                                    pcb->unacked != NULL ?
+                                    lwip_ntohl(pcb->unacked->tcphdr->seqno) + TCP_TCPLEN(pcb->unacked) : 0));
+
+      /* Remove segment from the unacknowledged list if the incoming
+         ACK acknowledges them. */
+      pcb->unacked = tcp_free_acked_segments(pcb, pcb->unacked, "unacked", pcb->unsent);
+ 801b688:	687b      	ldr	r3, [r7, #4]
+ 801b68a:	6f19      	ldr	r1, [r3, #112]	; 0x70
+ 801b68c:	687b      	ldr	r3, [r7, #4]
+ 801b68e:	6edb      	ldr	r3, [r3, #108]	; 0x6c
+ 801b690:	4a98      	ldr	r2, [pc, #608]	; (801b8f4 <tcp_receive+0x5d0>)
+ 801b692:	6878      	ldr	r0, [r7, #4]
+ 801b694:	f7ff fdca 	bl	801b22c <tcp_free_acked_segments>
+ 801b698:	4602      	mov	r2, r0
+ 801b69a:	687b      	ldr	r3, [r7, #4]
+ 801b69c:	671a      	str	r2, [r3, #112]	; 0x70
+         on the list are acknowledged by the ACK. This may seem
+         strange since an "unsent" segment shouldn't be acked. The
+         rationale is that lwIP puts all outstanding segments on the
+         ->unsent list after a retransmission, so these segments may
+         in fact have been sent once. */
+      pcb->unsent = tcp_free_acked_segments(pcb, pcb->unsent, "unsent", pcb->unacked);
+ 801b69e:	687b      	ldr	r3, [r7, #4]
+ 801b6a0:	6ed9      	ldr	r1, [r3, #108]	; 0x6c
+ 801b6a2:	687b      	ldr	r3, [r7, #4]
+ 801b6a4:	6f1b      	ldr	r3, [r3, #112]	; 0x70
+ 801b6a6:	4a94      	ldr	r2, [pc, #592]	; (801b8f8 <tcp_receive+0x5d4>)
+ 801b6a8:	6878      	ldr	r0, [r7, #4]
+ 801b6aa:	f7ff fdbf 	bl	801b22c <tcp_free_acked_segments>
+ 801b6ae:	4602      	mov	r2, r0
+ 801b6b0:	687b      	ldr	r3, [r7, #4]
+ 801b6b2:	66da      	str	r2, [r3, #108]	; 0x6c
+
+      /* If there's nothing left to acknowledge, stop the retransmit
+         timer, otherwise reset it to start again */
+      if (pcb->unacked == NULL) {
+ 801b6b4:	687b      	ldr	r3, [r7, #4]
+ 801b6b6:	6f1b      	ldr	r3, [r3, #112]	; 0x70
+ 801b6b8:	2b00      	cmp	r3, #0
+ 801b6ba:	d104      	bne.n	801b6c6 <tcp_receive+0x3a2>
+        pcb->rtime = -1;
+ 801b6bc:	687b      	ldr	r3, [r7, #4]
+ 801b6be:	f64f 72ff 	movw	r2, #65535	; 0xffff
+ 801b6c2:	861a      	strh	r2, [r3, #48]	; 0x30
+ 801b6c4:	e002      	b.n	801b6cc <tcp_receive+0x3a8>
+      } else {
+        pcb->rtime = 0;
+ 801b6c6:	687b      	ldr	r3, [r7, #4]
+ 801b6c8:	2200      	movs	r2, #0
+ 801b6ca:	861a      	strh	r2, [r3, #48]	; 0x30
+      }
+
+      pcb->polltmr = 0;
+ 801b6cc:	687b      	ldr	r3, [r7, #4]
+ 801b6ce:	2200      	movs	r2, #0
+ 801b6d0:	771a      	strb	r2, [r3, #28]
+
+#if TCP_OVERSIZE
+      if (pcb->unsent == NULL) {
+ 801b6d2:	687b      	ldr	r3, [r7, #4]
+ 801b6d4:	6edb      	ldr	r3, [r3, #108]	; 0x6c
+ 801b6d6:	2b00      	cmp	r3, #0
+ 801b6d8:	d103      	bne.n	801b6e2 <tcp_receive+0x3be>
+        pcb->unsent_oversize = 0;
+ 801b6da:	687b      	ldr	r3, [r7, #4]
+ 801b6dc:	2200      	movs	r2, #0
+ 801b6de:	f8a3 2068 	strh.w	r2, [r3, #104]	; 0x68
+        /* Inform neighbor reachability of forward progress. */
+        nd6_reachability_hint(ip6_current_src_addr());
+      }
+#endif /* LWIP_IPV6 && LWIP_ND6_TCP_REACHABILITY_HINTS*/
+
+      pcb->snd_buf = (tcpwnd_size_t)(pcb->snd_buf + recv_acked);
+ 801b6e2:	687b      	ldr	r3, [r7, #4]
+ 801b6e4:	f8b3 2064 	ldrh.w	r2, [r3, #100]	; 0x64
+ 801b6e8:	4b84      	ldr	r3, [pc, #528]	; (801b8fc <tcp_receive+0x5d8>)
+ 801b6ea:	881b      	ldrh	r3, [r3, #0]
+ 801b6ec:	4413      	add	r3, r2
+ 801b6ee:	b29a      	uxth	r2, r3
+ 801b6f0:	687b      	ldr	r3, [r7, #4]
+ 801b6f2:	f8a3 2064 	strh.w	r2, [r3, #100]	; 0x64
+      /* check if this ACK ends our retransmission of in-flight data */
+      if (pcb->flags & TF_RTO) {
+ 801b6f6:	687b      	ldr	r3, [r7, #4]
+ 801b6f8:	8b5b      	ldrh	r3, [r3, #26]
+ 801b6fa:	f403 6300 	and.w	r3, r3, #2048	; 0x800
+ 801b6fe:	2b00      	cmp	r3, #0
+ 801b700:	d035      	beq.n	801b76e <tcp_receive+0x44a>
+        /* RTO is done if
+            1) both queues are empty or
+            2) unacked is empty and unsent head contains data not part of RTO or
+            3) unacked head contains data not part of RTO */
+        if (pcb->unacked == NULL) {
+ 801b702:	687b      	ldr	r3, [r7, #4]
+ 801b704:	6f1b      	ldr	r3, [r3, #112]	; 0x70
+ 801b706:	2b00      	cmp	r3, #0
+ 801b708:	d118      	bne.n	801b73c <tcp_receive+0x418>
+          if ((pcb->unsent == NULL) ||
+ 801b70a:	687b      	ldr	r3, [r7, #4]
+ 801b70c:	6edb      	ldr	r3, [r3, #108]	; 0x6c
+ 801b70e:	2b00      	cmp	r3, #0
+ 801b710:	d00c      	beq.n	801b72c <tcp_receive+0x408>
+              (TCP_SEQ_LEQ(pcb->rto_end, lwip_ntohl(pcb->unsent->tcphdr->seqno)))) {
+ 801b712:	687b      	ldr	r3, [r7, #4]
+ 801b714:	6cdc      	ldr	r4, [r3, #76]	; 0x4c
+ 801b716:	687b      	ldr	r3, [r7, #4]
+ 801b718:	6edb      	ldr	r3, [r3, #108]	; 0x6c
+ 801b71a:	691b      	ldr	r3, [r3, #16]
+ 801b71c:	685b      	ldr	r3, [r3, #4]
+ 801b71e:	4618      	mov	r0, r3
+ 801b720:	f7fa fc23 	bl	8015f6a <lwip_htonl>
+ 801b724:	4603      	mov	r3, r0
+ 801b726:	1ae3      	subs	r3, r4, r3
+          if ((pcb->unsent == NULL) ||
+ 801b728:	2b00      	cmp	r3, #0
+ 801b72a:	dc20      	bgt.n	801b76e <tcp_receive+0x44a>
+            tcp_clear_flags(pcb, TF_RTO);
+ 801b72c:	687b      	ldr	r3, [r7, #4]
+ 801b72e:	8b5b      	ldrh	r3, [r3, #26]
+ 801b730:	f423 6300 	bic.w	r3, r3, #2048	; 0x800
+ 801b734:	b29a      	uxth	r2, r3
+ 801b736:	687b      	ldr	r3, [r7, #4]
+ 801b738:	835a      	strh	r2, [r3, #26]
+    } else if (TCP_SEQ_BETWEEN(ackno, pcb->lastack + 1, pcb->snd_nxt)) {
+ 801b73a:	e018      	b.n	801b76e <tcp_receive+0x44a>
+          }
+        } else if (TCP_SEQ_LEQ(pcb->rto_end, lwip_ntohl(pcb->unacked->tcphdr->seqno))) {
+ 801b73c:	687b      	ldr	r3, [r7, #4]
+ 801b73e:	6cdc      	ldr	r4, [r3, #76]	; 0x4c
+ 801b740:	687b      	ldr	r3, [r7, #4]
+ 801b742:	6f1b      	ldr	r3, [r3, #112]	; 0x70
+ 801b744:	691b      	ldr	r3, [r3, #16]
+ 801b746:	685b      	ldr	r3, [r3, #4]
+ 801b748:	4618      	mov	r0, r3
+ 801b74a:	f7fa fc0e 	bl	8015f6a <lwip_htonl>
+ 801b74e:	4603      	mov	r3, r0
+ 801b750:	1ae3      	subs	r3, r4, r3
+ 801b752:	2b00      	cmp	r3, #0
+ 801b754:	dc0b      	bgt.n	801b76e <tcp_receive+0x44a>
+          tcp_clear_flags(pcb, TF_RTO);
+ 801b756:	687b      	ldr	r3, [r7, #4]
+ 801b758:	8b5b      	ldrh	r3, [r3, #26]
+ 801b75a:	f423 6300 	bic.w	r3, r3, #2048	; 0x800
+ 801b75e:	b29a      	uxth	r2, r3
+ 801b760:	687b      	ldr	r3, [r7, #4]
+ 801b762:	835a      	strh	r2, [r3, #26]
+    } else if (TCP_SEQ_BETWEEN(ackno, pcb->lastack + 1, pcb->snd_nxt)) {
+ 801b764:	e003      	b.n	801b76e <tcp_receive+0x44a>
+        }
+      }
+      /* End of ACK for new data processing. */
+    } else {
+      /* Out of sequence ACK, didn't really ack anything */
+      tcp_send_empty_ack(pcb);
+ 801b766:	6878      	ldr	r0, [r7, #4]
+ 801b768:	f002 fc3a 	bl	801dfe0 <tcp_send_empty_ack>
+ 801b76c:	e000      	b.n	801b770 <tcp_receive+0x44c>
+    } else if (TCP_SEQ_BETWEEN(ackno, pcb->lastack + 1, pcb->snd_nxt)) {
+ 801b76e:	bf00      	nop
+                                pcb->rttest, pcb->rtseq, ackno));
+
+    /* RTT estimation calculations. This is done by checking if the
+       incoming segment acknowledges the segment we use to take a
+       round-trip time measurement. */
+    if (pcb->rttest && TCP_SEQ_LT(pcb->rtseq, ackno)) {
+ 801b770:	687b      	ldr	r3, [r7, #4]
+ 801b772:	6b5b      	ldr	r3, [r3, #52]	; 0x34
+ 801b774:	2b00      	cmp	r3, #0
+ 801b776:	d05b      	beq.n	801b830 <tcp_receive+0x50c>
+ 801b778:	687b      	ldr	r3, [r7, #4]
+ 801b77a:	6b9a      	ldr	r2, [r3, #56]	; 0x38
+ 801b77c:	4b60      	ldr	r3, [pc, #384]	; (801b900 <tcp_receive+0x5dc>)
+ 801b77e:	681b      	ldr	r3, [r3, #0]
+ 801b780:	1ad3      	subs	r3, r2, r3
+ 801b782:	2b00      	cmp	r3, #0
+ 801b784:	da54      	bge.n	801b830 <tcp_receive+0x50c>
+      /* diff between this shouldn't exceed 32K since this are tcp timer ticks
+         and a round-trip shouldn't be that long... */
+      m = (s16_t)(tcp_ticks - pcb->rttest);
+ 801b786:	4b5f      	ldr	r3, [pc, #380]	; (801b904 <tcp_receive+0x5e0>)
+ 801b788:	681b      	ldr	r3, [r3, #0]
+ 801b78a:	b29a      	uxth	r2, r3
+ 801b78c:	687b      	ldr	r3, [r7, #4]
+ 801b78e:	6b5b      	ldr	r3, [r3, #52]	; 0x34
+ 801b790:	b29b      	uxth	r3, r3
+ 801b792:	1ad3      	subs	r3, r2, r3
+ 801b794:	b29b      	uxth	r3, r3
+ 801b796:	f8a7 304e 	strh.w	r3, [r7, #78]	; 0x4e
+
+      LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_receive: experienced rtt %"U16_F" ticks (%"U16_F" msec).\n",
+                                  m, (u16_t)(m * TCP_SLOW_INTERVAL)));
+
+      /* This is taken directly from VJs original code in his paper */
+      m = (s16_t)(m - (pcb->sa >> 3));
+ 801b79a:	f8b7 204e 	ldrh.w	r2, [r7, #78]	; 0x4e
+ 801b79e:	687b      	ldr	r3, [r7, #4]
+ 801b7a0:	f9b3 303c 	ldrsh.w	r3, [r3, #60]	; 0x3c
+ 801b7a4:	10db      	asrs	r3, r3, #3
+ 801b7a6:	b21b      	sxth	r3, r3
+ 801b7a8:	b29b      	uxth	r3, r3
+ 801b7aa:	1ad3      	subs	r3, r2, r3
+ 801b7ac:	b29b      	uxth	r3, r3
+ 801b7ae:	f8a7 304e 	strh.w	r3, [r7, #78]	; 0x4e
+      pcb->sa = (s16_t)(pcb->sa + m);
+ 801b7b2:	687b      	ldr	r3, [r7, #4]
+ 801b7b4:	f9b3 303c 	ldrsh.w	r3, [r3, #60]	; 0x3c
+ 801b7b8:	b29a      	uxth	r2, r3
+ 801b7ba:	f8b7 304e 	ldrh.w	r3, [r7, #78]	; 0x4e
+ 801b7be:	4413      	add	r3, r2
+ 801b7c0:	b29b      	uxth	r3, r3
+ 801b7c2:	b21a      	sxth	r2, r3
+ 801b7c4:	687b      	ldr	r3, [r7, #4]
+ 801b7c6:	879a      	strh	r2, [r3, #60]	; 0x3c
+      if (m < 0) {
+ 801b7c8:	f9b7 304e 	ldrsh.w	r3, [r7, #78]	; 0x4e
+ 801b7cc:	2b00      	cmp	r3, #0
+ 801b7ce:	da05      	bge.n	801b7dc <tcp_receive+0x4b8>
+        m = (s16_t) - m;
+ 801b7d0:	f8b7 304e 	ldrh.w	r3, [r7, #78]	; 0x4e
+ 801b7d4:	425b      	negs	r3, r3
+ 801b7d6:	b29b      	uxth	r3, r3
+ 801b7d8:	f8a7 304e 	strh.w	r3, [r7, #78]	; 0x4e
+      }
+      m = (s16_t)(m - (pcb->sv >> 2));
+ 801b7dc:	f8b7 204e 	ldrh.w	r2, [r7, #78]	; 0x4e
+ 801b7e0:	687b      	ldr	r3, [r7, #4]
+ 801b7e2:	f9b3 303e 	ldrsh.w	r3, [r3, #62]	; 0x3e
+ 801b7e6:	109b      	asrs	r3, r3, #2
+ 801b7e8:	b21b      	sxth	r3, r3
+ 801b7ea:	b29b      	uxth	r3, r3
+ 801b7ec:	1ad3      	subs	r3, r2, r3
+ 801b7ee:	b29b      	uxth	r3, r3
+ 801b7f0:	f8a7 304e 	strh.w	r3, [r7, #78]	; 0x4e
+      pcb->sv = (s16_t)(pcb->sv + m);
+ 801b7f4:	687b      	ldr	r3, [r7, #4]
+ 801b7f6:	f9b3 303e 	ldrsh.w	r3, [r3, #62]	; 0x3e
+ 801b7fa:	b29a      	uxth	r2, r3
+ 801b7fc:	f8b7 304e 	ldrh.w	r3, [r7, #78]	; 0x4e
+ 801b800:	4413      	add	r3, r2
+ 801b802:	b29b      	uxth	r3, r3
+ 801b804:	b21a      	sxth	r2, r3
+ 801b806:	687b      	ldr	r3, [r7, #4]
+ 801b808:	87da      	strh	r2, [r3, #62]	; 0x3e
+      pcb->rto = (s16_t)((pcb->sa >> 3) + pcb->sv);
+ 801b80a:	687b      	ldr	r3, [r7, #4]
+ 801b80c:	f9b3 303c 	ldrsh.w	r3, [r3, #60]	; 0x3c
+ 801b810:	10db      	asrs	r3, r3, #3
+ 801b812:	b21b      	sxth	r3, r3
+ 801b814:	b29a      	uxth	r2, r3
+ 801b816:	687b      	ldr	r3, [r7, #4]
+ 801b818:	f9b3 303e 	ldrsh.w	r3, [r3, #62]	; 0x3e
+ 801b81c:	b29b      	uxth	r3, r3
+ 801b81e:	4413      	add	r3, r2
+ 801b820:	b29b      	uxth	r3, r3
+ 801b822:	b21a      	sxth	r2, r3
+ 801b824:	687b      	ldr	r3, [r7, #4]
+ 801b826:	f8a3 2040 	strh.w	r2, [r3, #64]	; 0x40
+
+      LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_receive: RTO %"U16_F" (%"U16_F" milliseconds)\n",
+                                  pcb->rto, (u16_t)(pcb->rto * TCP_SLOW_INTERVAL)));
+
+      pcb->rttest = 0;
+ 801b82a:	687b      	ldr	r3, [r7, #4]
+ 801b82c:	2200      	movs	r2, #0
+ 801b82e:	635a      	str	r2, [r3, #52]	; 0x34
+
+  /* If the incoming segment contains data, we must process it
+     further unless the pcb already received a FIN.
+     (RFC 793, chapter 3.9, "SEGMENT ARRIVES" in states CLOSE-WAIT, CLOSING,
+     LAST-ACK and TIME-WAIT: "Ignore the segment text.") */
+  if ((tcplen > 0) && (pcb->state < CLOSE_WAIT)) {
+ 801b830:	4b35      	ldr	r3, [pc, #212]	; (801b908 <tcp_receive+0x5e4>)
+ 801b832:	881b      	ldrh	r3, [r3, #0]
+ 801b834:	2b00      	cmp	r3, #0
+ 801b836:	f000 84e2 	beq.w	801c1fe <tcp_receive+0xeda>
+ 801b83a:	687b      	ldr	r3, [r7, #4]
+ 801b83c:	7d1b      	ldrb	r3, [r3, #20]
+ 801b83e:	2b06      	cmp	r3, #6
+ 801b840:	f200 84dd 	bhi.w	801c1fe <tcp_receive+0xeda>
+       this if the sequence number of the incoming segment is less
+       than rcv_nxt, and the sequence number plus the length of the
+       segment is larger than rcv_nxt. */
+    /*    if (TCP_SEQ_LT(seqno, pcb->rcv_nxt)) {
+          if (TCP_SEQ_LT(pcb->rcv_nxt, seqno + tcplen)) {*/
+    if (TCP_SEQ_BETWEEN(pcb->rcv_nxt, seqno + 1, seqno + tcplen - 1)) {
+ 801b844:	687b      	ldr	r3, [r7, #4]
+ 801b846:	6a5a      	ldr	r2, [r3, #36]	; 0x24
+ 801b848:	4b30      	ldr	r3, [pc, #192]	; (801b90c <tcp_receive+0x5e8>)
+ 801b84a:	681b      	ldr	r3, [r3, #0]
+ 801b84c:	1ad3      	subs	r3, r2, r3
+ 801b84e:	3b01      	subs	r3, #1
+ 801b850:	2b00      	cmp	r3, #0
+ 801b852:	f2c0 808f 	blt.w	801b974 <tcp_receive+0x650>
+ 801b856:	687b      	ldr	r3, [r7, #4]
+ 801b858:	6a5a      	ldr	r2, [r3, #36]	; 0x24
+ 801b85a:	4b2b      	ldr	r3, [pc, #172]	; (801b908 <tcp_receive+0x5e4>)
+ 801b85c:	881b      	ldrh	r3, [r3, #0]
+ 801b85e:	4619      	mov	r1, r3
+ 801b860:	4b2a      	ldr	r3, [pc, #168]	; (801b90c <tcp_receive+0x5e8>)
+ 801b862:	681b      	ldr	r3, [r3, #0]
+ 801b864:	440b      	add	r3, r1
+ 801b866:	1ad3      	subs	r3, r2, r3
+ 801b868:	3301      	adds	r3, #1
+ 801b86a:	2b00      	cmp	r3, #0
+ 801b86c:	f300 8082 	bgt.w	801b974 <tcp_receive+0x650>
+
+         After we are done with adjusting the pbuf pointers we must
+         adjust the ->data pointer in the seg and the segment
+         length.*/
+
+      struct pbuf *p = inseg.p;
+ 801b870:	4b27      	ldr	r3, [pc, #156]	; (801b910 <tcp_receive+0x5ec>)
+ 801b872:	685b      	ldr	r3, [r3, #4]
+ 801b874:	647b      	str	r3, [r7, #68]	; 0x44
+      u32_t off32 = pcb->rcv_nxt - seqno;
+ 801b876:	687b      	ldr	r3, [r7, #4]
+ 801b878:	6a5a      	ldr	r2, [r3, #36]	; 0x24
+ 801b87a:	4b24      	ldr	r3, [pc, #144]	; (801b90c <tcp_receive+0x5e8>)
+ 801b87c:	681b      	ldr	r3, [r3, #0]
+ 801b87e:	1ad3      	subs	r3, r2, r3
+ 801b880:	627b      	str	r3, [r7, #36]	; 0x24
+      u16_t new_tot_len, off;
+      LWIP_ASSERT("inseg.p != NULL", inseg.p);
+ 801b882:	4b23      	ldr	r3, [pc, #140]	; (801b910 <tcp_receive+0x5ec>)
+ 801b884:	685b      	ldr	r3, [r3, #4]
+ 801b886:	2b00      	cmp	r3, #0
+ 801b888:	d106      	bne.n	801b898 <tcp_receive+0x574>
+ 801b88a:	4b22      	ldr	r3, [pc, #136]	; (801b914 <tcp_receive+0x5f0>)
+ 801b88c:	f240 5294 	movw	r2, #1428	; 0x594
+ 801b890:	4921      	ldr	r1, [pc, #132]	; (801b918 <tcp_receive+0x5f4>)
+ 801b892:	4822      	ldr	r0, [pc, #136]	; (801b91c <tcp_receive+0x5f8>)
+ 801b894:	f006 f878 	bl	8021988 <iprintf>
+      LWIP_ASSERT("insane offset!", (off32 < 0xffff));
+ 801b898:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 801b89a:	f64f 72fe 	movw	r2, #65534	; 0xfffe
+ 801b89e:	4293      	cmp	r3, r2
+ 801b8a0:	d906      	bls.n	801b8b0 <tcp_receive+0x58c>
+ 801b8a2:	4b1c      	ldr	r3, [pc, #112]	; (801b914 <tcp_receive+0x5f0>)
+ 801b8a4:	f240 5295 	movw	r2, #1429	; 0x595
+ 801b8a8:	491d      	ldr	r1, [pc, #116]	; (801b920 <tcp_receive+0x5fc>)
+ 801b8aa:	481c      	ldr	r0, [pc, #112]	; (801b91c <tcp_receive+0x5f8>)
+ 801b8ac:	f006 f86c 	bl	8021988 <iprintf>
+      off = (u16_t)off32;
+ 801b8b0:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 801b8b2:	f8a7 3042 	strh.w	r3, [r7, #66]	; 0x42
+      LWIP_ASSERT("pbuf too short!", (((s32_t)inseg.p->tot_len) >= off));
+ 801b8b6:	4b16      	ldr	r3, [pc, #88]	; (801b910 <tcp_receive+0x5ec>)
+ 801b8b8:	685b      	ldr	r3, [r3, #4]
+ 801b8ba:	891b      	ldrh	r3, [r3, #8]
+ 801b8bc:	f8b7 2042 	ldrh.w	r2, [r7, #66]	; 0x42
+ 801b8c0:	429a      	cmp	r2, r3
+ 801b8c2:	d906      	bls.n	801b8d2 <tcp_receive+0x5ae>
+ 801b8c4:	4b13      	ldr	r3, [pc, #76]	; (801b914 <tcp_receive+0x5f0>)
+ 801b8c6:	f240 5297 	movw	r2, #1431	; 0x597
+ 801b8ca:	4916      	ldr	r1, [pc, #88]	; (801b924 <tcp_receive+0x600>)
+ 801b8cc:	4813      	ldr	r0, [pc, #76]	; (801b91c <tcp_receive+0x5f8>)
+ 801b8ce:	f006 f85b 	bl	8021988 <iprintf>
+      inseg.len -= off;
+ 801b8d2:	4b0f      	ldr	r3, [pc, #60]	; (801b910 <tcp_receive+0x5ec>)
+ 801b8d4:	891a      	ldrh	r2, [r3, #8]
+ 801b8d6:	f8b7 3042 	ldrh.w	r3, [r7, #66]	; 0x42
+ 801b8da:	1ad3      	subs	r3, r2, r3
+ 801b8dc:	b29a      	uxth	r2, r3
+ 801b8de:	4b0c      	ldr	r3, [pc, #48]	; (801b910 <tcp_receive+0x5ec>)
+ 801b8e0:	811a      	strh	r2, [r3, #8]
+      new_tot_len = (u16_t)(inseg.p->tot_len - off);
+ 801b8e2:	4b0b      	ldr	r3, [pc, #44]	; (801b910 <tcp_receive+0x5ec>)
+ 801b8e4:	685b      	ldr	r3, [r3, #4]
+ 801b8e6:	891a      	ldrh	r2, [r3, #8]
+ 801b8e8:	f8b7 3042 	ldrh.w	r3, [r7, #66]	; 0x42
+ 801b8ec:	1ad3      	subs	r3, r2, r3
+ 801b8ee:	847b      	strh	r3, [r7, #34]	; 0x22
+      while (p->len < off) {
+ 801b8f0:	e02a      	b.n	801b948 <tcp_receive+0x624>
+ 801b8f2:	bf00      	nop
+ 801b8f4:	080256a0 	.word	0x080256a0
+ 801b8f8:	080256a8 	.word	0x080256a8
+ 801b8fc:	2401a4c4 	.word	0x2401a4c4
+ 801b900:	2401a4c0 	.word	0x2401a4c0
+ 801b904:	2401a480 	.word	0x2401a480
+ 801b908:	2401a4c6 	.word	0x2401a4c6
+ 801b90c:	2401a4bc 	.word	0x2401a4bc
+ 801b910:	2401a498 	.word	0x2401a498
+ 801b914:	08025338 	.word	0x08025338
+ 801b918:	080256b0 	.word	0x080256b0
+ 801b91c:	08025384 	.word	0x08025384
+ 801b920:	080256c0 	.word	0x080256c0
+ 801b924:	080256d0 	.word	0x080256d0
+        off -= p->len;
+ 801b928:	6c7b      	ldr	r3, [r7, #68]	; 0x44
+ 801b92a:	895b      	ldrh	r3, [r3, #10]
+ 801b92c:	f8b7 2042 	ldrh.w	r2, [r7, #66]	; 0x42
+ 801b930:	1ad3      	subs	r3, r2, r3
+ 801b932:	f8a7 3042 	strh.w	r3, [r7, #66]	; 0x42
+        /* all pbufs up to and including this one have len==0, so tot_len is equal */
+        p->tot_len = new_tot_len;
+ 801b936:	6c7b      	ldr	r3, [r7, #68]	; 0x44
+ 801b938:	8c7a      	ldrh	r2, [r7, #34]	; 0x22
+ 801b93a:	811a      	strh	r2, [r3, #8]
+        p->len = 0;
+ 801b93c:	6c7b      	ldr	r3, [r7, #68]	; 0x44
+ 801b93e:	2200      	movs	r2, #0
+ 801b940:	815a      	strh	r2, [r3, #10]
+        p = p->next;
+ 801b942:	6c7b      	ldr	r3, [r7, #68]	; 0x44
+ 801b944:	681b      	ldr	r3, [r3, #0]
+ 801b946:	647b      	str	r3, [r7, #68]	; 0x44
+      while (p->len < off) {
+ 801b948:	6c7b      	ldr	r3, [r7, #68]	; 0x44
+ 801b94a:	895b      	ldrh	r3, [r3, #10]
+ 801b94c:	f8b7 2042 	ldrh.w	r2, [r7, #66]	; 0x42
+ 801b950:	429a      	cmp	r2, r3
+ 801b952:	d8e9      	bhi.n	801b928 <tcp_receive+0x604>
+      }
+      /* cannot fail... */
+      pbuf_remove_header(p, off);
+ 801b954:	f8b7 3042 	ldrh.w	r3, [r7, #66]	; 0x42
+ 801b958:	4619      	mov	r1, r3
+ 801b95a:	6c78      	ldr	r0, [r7, #68]	; 0x44
+ 801b95c:	f7fc f846 	bl	80179ec <pbuf_remove_header>
+      inseg.tcphdr->seqno = seqno = pcb->rcv_nxt;
+ 801b960:	687b      	ldr	r3, [r7, #4]
+ 801b962:	6a5b      	ldr	r3, [r3, #36]	; 0x24
+ 801b964:	4a91      	ldr	r2, [pc, #580]	; (801bbac <tcp_receive+0x888>)
+ 801b966:	6013      	str	r3, [r2, #0]
+ 801b968:	4b91      	ldr	r3, [pc, #580]	; (801bbb0 <tcp_receive+0x88c>)
+ 801b96a:	691b      	ldr	r3, [r3, #16]
+ 801b96c:	4a8f      	ldr	r2, [pc, #572]	; (801bbac <tcp_receive+0x888>)
+ 801b96e:	6812      	ldr	r2, [r2, #0]
+ 801b970:	605a      	str	r2, [r3, #4]
+    if (TCP_SEQ_BETWEEN(pcb->rcv_nxt, seqno + 1, seqno + tcplen - 1)) {
+ 801b972:	e00d      	b.n	801b990 <tcp_receive+0x66c>
+    } else {
+      if (TCP_SEQ_LT(seqno, pcb->rcv_nxt)) {
+ 801b974:	4b8d      	ldr	r3, [pc, #564]	; (801bbac <tcp_receive+0x888>)
+ 801b976:	681a      	ldr	r2, [r3, #0]
+ 801b978:	687b      	ldr	r3, [r7, #4]
+ 801b97a:	6a5b      	ldr	r3, [r3, #36]	; 0x24
+ 801b97c:	1ad3      	subs	r3, r2, r3
+ 801b97e:	2b00      	cmp	r3, #0
+ 801b980:	da06      	bge.n	801b990 <tcp_receive+0x66c>
+        /* the whole segment is < rcv_nxt */
+        /* must be a duplicate of a packet that has already been correctly handled */
+
+        LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: duplicate seqno %"U32_F"\n", seqno));
+        tcp_ack_now(pcb);
+ 801b982:	687b      	ldr	r3, [r7, #4]
+ 801b984:	8b5b      	ldrh	r3, [r3, #26]
+ 801b986:	f043 0302 	orr.w	r3, r3, #2
+ 801b98a:	b29a      	uxth	r2, r3
+ 801b98c:	687b      	ldr	r3, [r7, #4]
+ 801b98e:	835a      	strh	r2, [r3, #26]
+    }
+
+    /* The sequence number must be within the window (above rcv_nxt
+       and below rcv_nxt + rcv_wnd) in order to be further
+       processed. */
+    if (TCP_SEQ_BETWEEN(seqno, pcb->rcv_nxt,
+ 801b990:	4b86      	ldr	r3, [pc, #536]	; (801bbac <tcp_receive+0x888>)
+ 801b992:	681a      	ldr	r2, [r3, #0]
+ 801b994:	687b      	ldr	r3, [r7, #4]
+ 801b996:	6a5b      	ldr	r3, [r3, #36]	; 0x24
+ 801b998:	1ad3      	subs	r3, r2, r3
+ 801b99a:	2b00      	cmp	r3, #0
+ 801b99c:	f2c0 842a 	blt.w	801c1f4 <tcp_receive+0xed0>
+ 801b9a0:	4b82      	ldr	r3, [pc, #520]	; (801bbac <tcp_receive+0x888>)
+ 801b9a2:	681a      	ldr	r2, [r3, #0]
+ 801b9a4:	687b      	ldr	r3, [r7, #4]
+ 801b9a6:	6a5b      	ldr	r3, [r3, #36]	; 0x24
+ 801b9a8:	6879      	ldr	r1, [r7, #4]
+ 801b9aa:	8d09      	ldrh	r1, [r1, #40]	; 0x28
+ 801b9ac:	440b      	add	r3, r1
+ 801b9ae:	1ad3      	subs	r3, r2, r3
+ 801b9b0:	3301      	adds	r3, #1
+ 801b9b2:	2b00      	cmp	r3, #0
+ 801b9b4:	f300 841e 	bgt.w	801c1f4 <tcp_receive+0xed0>
+                        pcb->rcv_nxt + pcb->rcv_wnd - 1)) {
+      if (pcb->rcv_nxt == seqno) {
+ 801b9b8:	687b      	ldr	r3, [r7, #4]
+ 801b9ba:	6a5a      	ldr	r2, [r3, #36]	; 0x24
+ 801b9bc:	4b7b      	ldr	r3, [pc, #492]	; (801bbac <tcp_receive+0x888>)
+ 801b9be:	681b      	ldr	r3, [r3, #0]
+ 801b9c0:	429a      	cmp	r2, r3
+ 801b9c2:	f040 829a 	bne.w	801befa <tcp_receive+0xbd6>
+        /* The incoming segment is the next in sequence. We check if
+           we have to trim the end of the segment and update rcv_nxt
+           and pass the data to the application. */
+        tcplen = TCP_TCPLEN(&inseg);
+ 801b9c6:	4b7a      	ldr	r3, [pc, #488]	; (801bbb0 <tcp_receive+0x88c>)
+ 801b9c8:	891c      	ldrh	r4, [r3, #8]
+ 801b9ca:	4b79      	ldr	r3, [pc, #484]	; (801bbb0 <tcp_receive+0x88c>)
+ 801b9cc:	691b      	ldr	r3, [r3, #16]
+ 801b9ce:	899b      	ldrh	r3, [r3, #12]
+ 801b9d0:	b29b      	uxth	r3, r3
+ 801b9d2:	4618      	mov	r0, r3
+ 801b9d4:	f7fa fab4 	bl	8015f40 <lwip_htons>
+ 801b9d8:	4603      	mov	r3, r0
+ 801b9da:	b2db      	uxtb	r3, r3
+ 801b9dc:	f003 0303 	and.w	r3, r3, #3
+ 801b9e0:	2b00      	cmp	r3, #0
+ 801b9e2:	d001      	beq.n	801b9e8 <tcp_receive+0x6c4>
+ 801b9e4:	2301      	movs	r3, #1
+ 801b9e6:	e000      	b.n	801b9ea <tcp_receive+0x6c6>
+ 801b9e8:	2300      	movs	r3, #0
+ 801b9ea:	4423      	add	r3, r4
+ 801b9ec:	b29a      	uxth	r2, r3
+ 801b9ee:	4b71      	ldr	r3, [pc, #452]	; (801bbb4 <tcp_receive+0x890>)
+ 801b9f0:	801a      	strh	r2, [r3, #0]
+
+        if (tcplen > pcb->rcv_wnd) {
+ 801b9f2:	687b      	ldr	r3, [r7, #4]
+ 801b9f4:	8d1a      	ldrh	r2, [r3, #40]	; 0x28
+ 801b9f6:	4b6f      	ldr	r3, [pc, #444]	; (801bbb4 <tcp_receive+0x890>)
+ 801b9f8:	881b      	ldrh	r3, [r3, #0]
+ 801b9fa:	429a      	cmp	r2, r3
+ 801b9fc:	d275      	bcs.n	801baea <tcp_receive+0x7c6>
+          LWIP_DEBUGF(TCP_INPUT_DEBUG,
+                      ("tcp_receive: other end overran receive window"
+                       "seqno %"U32_F" len %"U16_F" right edge %"U32_F"\n",
+                       seqno, tcplen, pcb->rcv_nxt + pcb->rcv_wnd));
+          if (TCPH_FLAGS(inseg.tcphdr) & TCP_FIN) {
+ 801b9fe:	4b6c      	ldr	r3, [pc, #432]	; (801bbb0 <tcp_receive+0x88c>)
+ 801ba00:	691b      	ldr	r3, [r3, #16]
+ 801ba02:	899b      	ldrh	r3, [r3, #12]
+ 801ba04:	b29b      	uxth	r3, r3
+ 801ba06:	4618      	mov	r0, r3
+ 801ba08:	f7fa fa9a 	bl	8015f40 <lwip_htons>
+ 801ba0c:	4603      	mov	r3, r0
+ 801ba0e:	b2db      	uxtb	r3, r3
+ 801ba10:	f003 0301 	and.w	r3, r3, #1
+ 801ba14:	2b00      	cmp	r3, #0
+ 801ba16:	d01f      	beq.n	801ba58 <tcp_receive+0x734>
+            /* Must remove the FIN from the header as we're trimming
+             * that byte of sequence-space from the packet */
+            TCPH_FLAGS_SET(inseg.tcphdr, TCPH_FLAGS(inseg.tcphdr) & ~(unsigned int)TCP_FIN);
+ 801ba18:	4b65      	ldr	r3, [pc, #404]	; (801bbb0 <tcp_receive+0x88c>)
+ 801ba1a:	691b      	ldr	r3, [r3, #16]
+ 801ba1c:	899b      	ldrh	r3, [r3, #12]
+ 801ba1e:	b29b      	uxth	r3, r3
+ 801ba20:	b21b      	sxth	r3, r3
+ 801ba22:	f423 537c 	bic.w	r3, r3, #16128	; 0x3f00
+ 801ba26:	b21c      	sxth	r4, r3
+ 801ba28:	4b61      	ldr	r3, [pc, #388]	; (801bbb0 <tcp_receive+0x88c>)
+ 801ba2a:	691b      	ldr	r3, [r3, #16]
+ 801ba2c:	899b      	ldrh	r3, [r3, #12]
+ 801ba2e:	b29b      	uxth	r3, r3
+ 801ba30:	4618      	mov	r0, r3
+ 801ba32:	f7fa fa85 	bl	8015f40 <lwip_htons>
+ 801ba36:	4603      	mov	r3, r0
+ 801ba38:	b2db      	uxtb	r3, r3
+ 801ba3a:	b29b      	uxth	r3, r3
+ 801ba3c:	f003 033e 	and.w	r3, r3, #62	; 0x3e
+ 801ba40:	b29b      	uxth	r3, r3
+ 801ba42:	4618      	mov	r0, r3
+ 801ba44:	f7fa fa7c 	bl	8015f40 <lwip_htons>
+ 801ba48:	4603      	mov	r3, r0
+ 801ba4a:	b21b      	sxth	r3, r3
+ 801ba4c:	4323      	orrs	r3, r4
+ 801ba4e:	b21a      	sxth	r2, r3
+ 801ba50:	4b57      	ldr	r3, [pc, #348]	; (801bbb0 <tcp_receive+0x88c>)
+ 801ba52:	691b      	ldr	r3, [r3, #16]
+ 801ba54:	b292      	uxth	r2, r2
+ 801ba56:	819a      	strh	r2, [r3, #12]
+          }
+          /* Adjust length of segment to fit in the window. */
+          TCPWND_CHECK16(pcb->rcv_wnd);
+          inseg.len = (u16_t)pcb->rcv_wnd;
+ 801ba58:	687b      	ldr	r3, [r7, #4]
+ 801ba5a:	8d1a      	ldrh	r2, [r3, #40]	; 0x28
+ 801ba5c:	4b54      	ldr	r3, [pc, #336]	; (801bbb0 <tcp_receive+0x88c>)
+ 801ba5e:	811a      	strh	r2, [r3, #8]
+          if (TCPH_FLAGS(inseg.tcphdr) & TCP_SYN) {
+ 801ba60:	4b53      	ldr	r3, [pc, #332]	; (801bbb0 <tcp_receive+0x88c>)
+ 801ba62:	691b      	ldr	r3, [r3, #16]
+ 801ba64:	899b      	ldrh	r3, [r3, #12]
+ 801ba66:	b29b      	uxth	r3, r3
+ 801ba68:	4618      	mov	r0, r3
+ 801ba6a:	f7fa fa69 	bl	8015f40 <lwip_htons>
+ 801ba6e:	4603      	mov	r3, r0
+ 801ba70:	b2db      	uxtb	r3, r3
+ 801ba72:	f003 0302 	and.w	r3, r3, #2
+ 801ba76:	2b00      	cmp	r3, #0
+ 801ba78:	d005      	beq.n	801ba86 <tcp_receive+0x762>
+            inseg.len -= 1;
+ 801ba7a:	4b4d      	ldr	r3, [pc, #308]	; (801bbb0 <tcp_receive+0x88c>)
+ 801ba7c:	891b      	ldrh	r3, [r3, #8]
+ 801ba7e:	3b01      	subs	r3, #1
+ 801ba80:	b29a      	uxth	r2, r3
+ 801ba82:	4b4b      	ldr	r3, [pc, #300]	; (801bbb0 <tcp_receive+0x88c>)
+ 801ba84:	811a      	strh	r2, [r3, #8]
+          }
+          pbuf_realloc(inseg.p, inseg.len);
+ 801ba86:	4b4a      	ldr	r3, [pc, #296]	; (801bbb0 <tcp_receive+0x88c>)
+ 801ba88:	685b      	ldr	r3, [r3, #4]
+ 801ba8a:	4a49      	ldr	r2, [pc, #292]	; (801bbb0 <tcp_receive+0x88c>)
+ 801ba8c:	8912      	ldrh	r2, [r2, #8]
+ 801ba8e:	4611      	mov	r1, r2
+ 801ba90:	4618      	mov	r0, r3
+ 801ba92:	f7fb feab 	bl	80177ec <pbuf_realloc>
+          tcplen = TCP_TCPLEN(&inseg);
+ 801ba96:	4b46      	ldr	r3, [pc, #280]	; (801bbb0 <tcp_receive+0x88c>)
+ 801ba98:	891c      	ldrh	r4, [r3, #8]
+ 801ba9a:	4b45      	ldr	r3, [pc, #276]	; (801bbb0 <tcp_receive+0x88c>)
+ 801ba9c:	691b      	ldr	r3, [r3, #16]
+ 801ba9e:	899b      	ldrh	r3, [r3, #12]
+ 801baa0:	b29b      	uxth	r3, r3
+ 801baa2:	4618      	mov	r0, r3
+ 801baa4:	f7fa fa4c 	bl	8015f40 <lwip_htons>
+ 801baa8:	4603      	mov	r3, r0
+ 801baaa:	b2db      	uxtb	r3, r3
+ 801baac:	f003 0303 	and.w	r3, r3, #3
+ 801bab0:	2b00      	cmp	r3, #0
+ 801bab2:	d001      	beq.n	801bab8 <tcp_receive+0x794>
+ 801bab4:	2301      	movs	r3, #1
+ 801bab6:	e000      	b.n	801baba <tcp_receive+0x796>
+ 801bab8:	2300      	movs	r3, #0
+ 801baba:	4423      	add	r3, r4
+ 801babc:	b29a      	uxth	r2, r3
+ 801babe:	4b3d      	ldr	r3, [pc, #244]	; (801bbb4 <tcp_receive+0x890>)
+ 801bac0:	801a      	strh	r2, [r3, #0]
+          LWIP_ASSERT("tcp_receive: segment not trimmed correctly to rcv_wnd\n",
+ 801bac2:	4b3c      	ldr	r3, [pc, #240]	; (801bbb4 <tcp_receive+0x890>)
+ 801bac4:	881b      	ldrh	r3, [r3, #0]
+ 801bac6:	461a      	mov	r2, r3
+ 801bac8:	4b38      	ldr	r3, [pc, #224]	; (801bbac <tcp_receive+0x888>)
+ 801baca:	681b      	ldr	r3, [r3, #0]
+ 801bacc:	441a      	add	r2, r3
+ 801bace:	687b      	ldr	r3, [r7, #4]
+ 801bad0:	6a5b      	ldr	r3, [r3, #36]	; 0x24
+ 801bad2:	6879      	ldr	r1, [r7, #4]
+ 801bad4:	8d09      	ldrh	r1, [r1, #40]	; 0x28
+ 801bad6:	440b      	add	r3, r1
+ 801bad8:	429a      	cmp	r2, r3
+ 801bada:	d006      	beq.n	801baea <tcp_receive+0x7c6>
+ 801badc:	4b36      	ldr	r3, [pc, #216]	; (801bbb8 <tcp_receive+0x894>)
+ 801bade:	f240 52cb 	movw	r2, #1483	; 0x5cb
+ 801bae2:	4936      	ldr	r1, [pc, #216]	; (801bbbc <tcp_receive+0x898>)
+ 801bae4:	4836      	ldr	r0, [pc, #216]	; (801bbc0 <tcp_receive+0x89c>)
+ 801bae6:	f005 ff4f 	bl	8021988 <iprintf>
+        }
+#if TCP_QUEUE_OOSEQ
+        /* Received in-sequence data, adjust ooseq data if:
+           - FIN has been received or
+           - inseq overlaps with ooseq */
+        if (pcb->ooseq != NULL) {
+ 801baea:	687b      	ldr	r3, [r7, #4]
+ 801baec:	6f5b      	ldr	r3, [r3, #116]	; 0x74
+ 801baee:	2b00      	cmp	r3, #0
+ 801baf0:	f000 80e7 	beq.w	801bcc2 <tcp_receive+0x99e>
+          if (TCPH_FLAGS(inseg.tcphdr) & TCP_FIN) {
+ 801baf4:	4b2e      	ldr	r3, [pc, #184]	; (801bbb0 <tcp_receive+0x88c>)
+ 801baf6:	691b      	ldr	r3, [r3, #16]
+ 801baf8:	899b      	ldrh	r3, [r3, #12]
+ 801bafa:	b29b      	uxth	r3, r3
+ 801bafc:	4618      	mov	r0, r3
+ 801bafe:	f7fa fa1f 	bl	8015f40 <lwip_htons>
+ 801bb02:	4603      	mov	r3, r0
+ 801bb04:	b2db      	uxtb	r3, r3
+ 801bb06:	f003 0301 	and.w	r3, r3, #1
+ 801bb0a:	2b00      	cmp	r3, #0
+ 801bb0c:	d010      	beq.n	801bb30 <tcp_receive+0x80c>
+            LWIP_DEBUGF(TCP_INPUT_DEBUG,
+                        ("tcp_receive: received in-order FIN, binning ooseq queue\n"));
+            /* Received in-order FIN means anything that was received
+             * out of order must now have been received in-order, so
+             * bin the ooseq queue */
+            while (pcb->ooseq != NULL) {
+ 801bb0e:	e00a      	b.n	801bb26 <tcp_receive+0x802>
+              struct tcp_seg *old_ooseq = pcb->ooseq;
+ 801bb10:	687b      	ldr	r3, [r7, #4]
+ 801bb12:	6f5b      	ldr	r3, [r3, #116]	; 0x74
+ 801bb14:	60fb      	str	r3, [r7, #12]
+              pcb->ooseq = pcb->ooseq->next;
+ 801bb16:	687b      	ldr	r3, [r7, #4]
+ 801bb18:	6f5b      	ldr	r3, [r3, #116]	; 0x74
+ 801bb1a:	681a      	ldr	r2, [r3, #0]
+ 801bb1c:	687b      	ldr	r3, [r7, #4]
+ 801bb1e:	675a      	str	r2, [r3, #116]	; 0x74
+              tcp_seg_free(old_ooseq);
+ 801bb20:	68f8      	ldr	r0, [r7, #12]
+ 801bb22:	f7fd fcbe 	bl	80194a2 <tcp_seg_free>
+            while (pcb->ooseq != NULL) {
+ 801bb26:	687b      	ldr	r3, [r7, #4]
+ 801bb28:	6f5b      	ldr	r3, [r3, #116]	; 0x74
+ 801bb2a:	2b00      	cmp	r3, #0
+ 801bb2c:	d1f0      	bne.n	801bb10 <tcp_receive+0x7ec>
+ 801bb2e:	e0c8      	b.n	801bcc2 <tcp_receive+0x99e>
+            }
+          } else {
+            struct tcp_seg *next = pcb->ooseq;
+ 801bb30:	687b      	ldr	r3, [r7, #4]
+ 801bb32:	6f5b      	ldr	r3, [r3, #116]	; 0x74
+ 801bb34:	63fb      	str	r3, [r7, #60]	; 0x3c
+            /* Remove all segments on ooseq that are covered by inseg already.
+             * FIN is copied from ooseq to inseg if present. */
+            while (next &&
+ 801bb36:	e052      	b.n	801bbde <tcp_receive+0x8ba>
+                   TCP_SEQ_GEQ(seqno + tcplen,
+                               next->tcphdr->seqno + next->len)) {
+              struct tcp_seg *tmp;
+              /* inseg cannot have FIN here (already processed above) */
+              if ((TCPH_FLAGS(next->tcphdr) & TCP_FIN) != 0 &&
+ 801bb38:	6bfb      	ldr	r3, [r7, #60]	; 0x3c
+ 801bb3a:	691b      	ldr	r3, [r3, #16]
+ 801bb3c:	899b      	ldrh	r3, [r3, #12]
+ 801bb3e:	b29b      	uxth	r3, r3
+ 801bb40:	4618      	mov	r0, r3
+ 801bb42:	f7fa f9fd 	bl	8015f40 <lwip_htons>
+ 801bb46:	4603      	mov	r3, r0
+ 801bb48:	b2db      	uxtb	r3, r3
+ 801bb4a:	f003 0301 	and.w	r3, r3, #1
+ 801bb4e:	2b00      	cmp	r3, #0
+ 801bb50:	d03d      	beq.n	801bbce <tcp_receive+0x8aa>
+                  (TCPH_FLAGS(inseg.tcphdr) & TCP_SYN) == 0) {
+ 801bb52:	4b17      	ldr	r3, [pc, #92]	; (801bbb0 <tcp_receive+0x88c>)
+ 801bb54:	691b      	ldr	r3, [r3, #16]
+ 801bb56:	899b      	ldrh	r3, [r3, #12]
+ 801bb58:	b29b      	uxth	r3, r3
+ 801bb5a:	4618      	mov	r0, r3
+ 801bb5c:	f7fa f9f0 	bl	8015f40 <lwip_htons>
+ 801bb60:	4603      	mov	r3, r0
+ 801bb62:	b2db      	uxtb	r3, r3
+ 801bb64:	f003 0302 	and.w	r3, r3, #2
+              if ((TCPH_FLAGS(next->tcphdr) & TCP_FIN) != 0 &&
+ 801bb68:	2b00      	cmp	r3, #0
+ 801bb6a:	d130      	bne.n	801bbce <tcp_receive+0x8aa>
+                TCPH_SET_FLAG(inseg.tcphdr, TCP_FIN);
+ 801bb6c:	4b10      	ldr	r3, [pc, #64]	; (801bbb0 <tcp_receive+0x88c>)
+ 801bb6e:	691b      	ldr	r3, [r3, #16]
+ 801bb70:	899b      	ldrh	r3, [r3, #12]
+ 801bb72:	b29c      	uxth	r4, r3
+ 801bb74:	2001      	movs	r0, #1
+ 801bb76:	f7fa f9e3 	bl	8015f40 <lwip_htons>
+ 801bb7a:	4603      	mov	r3, r0
+ 801bb7c:	461a      	mov	r2, r3
+ 801bb7e:	4b0c      	ldr	r3, [pc, #48]	; (801bbb0 <tcp_receive+0x88c>)
+ 801bb80:	691b      	ldr	r3, [r3, #16]
+ 801bb82:	4322      	orrs	r2, r4
+ 801bb84:	b292      	uxth	r2, r2
+ 801bb86:	819a      	strh	r2, [r3, #12]
+                tcplen = TCP_TCPLEN(&inseg);
+ 801bb88:	4b09      	ldr	r3, [pc, #36]	; (801bbb0 <tcp_receive+0x88c>)
+ 801bb8a:	891c      	ldrh	r4, [r3, #8]
+ 801bb8c:	4b08      	ldr	r3, [pc, #32]	; (801bbb0 <tcp_receive+0x88c>)
+ 801bb8e:	691b      	ldr	r3, [r3, #16]
+ 801bb90:	899b      	ldrh	r3, [r3, #12]
+ 801bb92:	b29b      	uxth	r3, r3
+ 801bb94:	4618      	mov	r0, r3
+ 801bb96:	f7fa f9d3 	bl	8015f40 <lwip_htons>
+ 801bb9a:	4603      	mov	r3, r0
+ 801bb9c:	b2db      	uxtb	r3, r3
+ 801bb9e:	f003 0303 	and.w	r3, r3, #3
+ 801bba2:	2b00      	cmp	r3, #0
+ 801bba4:	d00e      	beq.n	801bbc4 <tcp_receive+0x8a0>
+ 801bba6:	2301      	movs	r3, #1
+ 801bba8:	e00d      	b.n	801bbc6 <tcp_receive+0x8a2>
+ 801bbaa:	bf00      	nop
+ 801bbac:	2401a4bc 	.word	0x2401a4bc
+ 801bbb0:	2401a498 	.word	0x2401a498
+ 801bbb4:	2401a4c6 	.word	0x2401a4c6
+ 801bbb8:	08025338 	.word	0x08025338
+ 801bbbc:	080256e0 	.word	0x080256e0
+ 801bbc0:	08025384 	.word	0x08025384
+ 801bbc4:	2300      	movs	r3, #0
+ 801bbc6:	4423      	add	r3, r4
+ 801bbc8:	b29a      	uxth	r2, r3
+ 801bbca:	4b98      	ldr	r3, [pc, #608]	; (801be2c <tcp_receive+0xb08>)
+ 801bbcc:	801a      	strh	r2, [r3, #0]
+              }
+              tmp = next;
+ 801bbce:	6bfb      	ldr	r3, [r7, #60]	; 0x3c
+ 801bbd0:	613b      	str	r3, [r7, #16]
+              next = next->next;
+ 801bbd2:	6bfb      	ldr	r3, [r7, #60]	; 0x3c
+ 801bbd4:	681b      	ldr	r3, [r3, #0]
+ 801bbd6:	63fb      	str	r3, [r7, #60]	; 0x3c
+              tcp_seg_free(tmp);
+ 801bbd8:	6938      	ldr	r0, [r7, #16]
+ 801bbda:	f7fd fc62 	bl	80194a2 <tcp_seg_free>
+            while (next &&
+ 801bbde:	6bfb      	ldr	r3, [r7, #60]	; 0x3c
+ 801bbe0:	2b00      	cmp	r3, #0
+ 801bbe2:	d00e      	beq.n	801bc02 <tcp_receive+0x8de>
+                   TCP_SEQ_GEQ(seqno + tcplen,
+ 801bbe4:	4b91      	ldr	r3, [pc, #580]	; (801be2c <tcp_receive+0xb08>)
+ 801bbe6:	881b      	ldrh	r3, [r3, #0]
+ 801bbe8:	461a      	mov	r2, r3
+ 801bbea:	4b91      	ldr	r3, [pc, #580]	; (801be30 <tcp_receive+0xb0c>)
+ 801bbec:	681b      	ldr	r3, [r3, #0]
+ 801bbee:	441a      	add	r2, r3
+ 801bbf0:	6bfb      	ldr	r3, [r7, #60]	; 0x3c
+ 801bbf2:	691b      	ldr	r3, [r3, #16]
+ 801bbf4:	685b      	ldr	r3, [r3, #4]
+ 801bbf6:	6bf9      	ldr	r1, [r7, #60]	; 0x3c
+ 801bbf8:	8909      	ldrh	r1, [r1, #8]
+ 801bbfa:	440b      	add	r3, r1
+ 801bbfc:	1ad3      	subs	r3, r2, r3
+            while (next &&
+ 801bbfe:	2b00      	cmp	r3, #0
+ 801bc00:	da9a      	bge.n	801bb38 <tcp_receive+0x814>
+            }
+            /* Now trim right side of inseg if it overlaps with the first
+             * segment on ooseq */
+            if (next &&
+ 801bc02:	6bfb      	ldr	r3, [r7, #60]	; 0x3c
+ 801bc04:	2b00      	cmp	r3, #0
+ 801bc06:	d059      	beq.n	801bcbc <tcp_receive+0x998>
+                TCP_SEQ_GT(seqno + tcplen,
+ 801bc08:	4b88      	ldr	r3, [pc, #544]	; (801be2c <tcp_receive+0xb08>)
+ 801bc0a:	881b      	ldrh	r3, [r3, #0]
+ 801bc0c:	461a      	mov	r2, r3
+ 801bc0e:	4b88      	ldr	r3, [pc, #544]	; (801be30 <tcp_receive+0xb0c>)
+ 801bc10:	681b      	ldr	r3, [r3, #0]
+ 801bc12:	441a      	add	r2, r3
+ 801bc14:	6bfb      	ldr	r3, [r7, #60]	; 0x3c
+ 801bc16:	691b      	ldr	r3, [r3, #16]
+ 801bc18:	685b      	ldr	r3, [r3, #4]
+ 801bc1a:	1ad3      	subs	r3, r2, r3
+            if (next &&
+ 801bc1c:	2b00      	cmp	r3, #0
+ 801bc1e:	dd4d      	ble.n	801bcbc <tcp_receive+0x998>
+                           next->tcphdr->seqno)) {
+              /* inseg cannot have FIN here (already processed above) */
+              inseg.len = (u16_t)(next->tcphdr->seqno - seqno);
+ 801bc20:	6bfb      	ldr	r3, [r7, #60]	; 0x3c
+ 801bc22:	691b      	ldr	r3, [r3, #16]
+ 801bc24:	685b      	ldr	r3, [r3, #4]
+ 801bc26:	b29a      	uxth	r2, r3
+ 801bc28:	4b81      	ldr	r3, [pc, #516]	; (801be30 <tcp_receive+0xb0c>)
+ 801bc2a:	681b      	ldr	r3, [r3, #0]
+ 801bc2c:	b29b      	uxth	r3, r3
+ 801bc2e:	1ad3      	subs	r3, r2, r3
+ 801bc30:	b29a      	uxth	r2, r3
+ 801bc32:	4b80      	ldr	r3, [pc, #512]	; (801be34 <tcp_receive+0xb10>)
+ 801bc34:	811a      	strh	r2, [r3, #8]
+              if (TCPH_FLAGS(inseg.tcphdr) & TCP_SYN) {
+ 801bc36:	4b7f      	ldr	r3, [pc, #508]	; (801be34 <tcp_receive+0xb10>)
+ 801bc38:	691b      	ldr	r3, [r3, #16]
+ 801bc3a:	899b      	ldrh	r3, [r3, #12]
+ 801bc3c:	b29b      	uxth	r3, r3
+ 801bc3e:	4618      	mov	r0, r3
+ 801bc40:	f7fa f97e 	bl	8015f40 <lwip_htons>
+ 801bc44:	4603      	mov	r3, r0
+ 801bc46:	b2db      	uxtb	r3, r3
+ 801bc48:	f003 0302 	and.w	r3, r3, #2
+ 801bc4c:	2b00      	cmp	r3, #0
+ 801bc4e:	d005      	beq.n	801bc5c <tcp_receive+0x938>
+                inseg.len -= 1;
+ 801bc50:	4b78      	ldr	r3, [pc, #480]	; (801be34 <tcp_receive+0xb10>)
+ 801bc52:	891b      	ldrh	r3, [r3, #8]
+ 801bc54:	3b01      	subs	r3, #1
+ 801bc56:	b29a      	uxth	r2, r3
+ 801bc58:	4b76      	ldr	r3, [pc, #472]	; (801be34 <tcp_receive+0xb10>)
+ 801bc5a:	811a      	strh	r2, [r3, #8]
+              }
+              pbuf_realloc(inseg.p, inseg.len);
+ 801bc5c:	4b75      	ldr	r3, [pc, #468]	; (801be34 <tcp_receive+0xb10>)
+ 801bc5e:	685b      	ldr	r3, [r3, #4]
+ 801bc60:	4a74      	ldr	r2, [pc, #464]	; (801be34 <tcp_receive+0xb10>)
+ 801bc62:	8912      	ldrh	r2, [r2, #8]
+ 801bc64:	4611      	mov	r1, r2
+ 801bc66:	4618      	mov	r0, r3
+ 801bc68:	f7fb fdc0 	bl	80177ec <pbuf_realloc>
+              tcplen = TCP_TCPLEN(&inseg);
+ 801bc6c:	4b71      	ldr	r3, [pc, #452]	; (801be34 <tcp_receive+0xb10>)
+ 801bc6e:	891c      	ldrh	r4, [r3, #8]
+ 801bc70:	4b70      	ldr	r3, [pc, #448]	; (801be34 <tcp_receive+0xb10>)
+ 801bc72:	691b      	ldr	r3, [r3, #16]
+ 801bc74:	899b      	ldrh	r3, [r3, #12]
+ 801bc76:	b29b      	uxth	r3, r3
+ 801bc78:	4618      	mov	r0, r3
+ 801bc7a:	f7fa f961 	bl	8015f40 <lwip_htons>
+ 801bc7e:	4603      	mov	r3, r0
+ 801bc80:	b2db      	uxtb	r3, r3
+ 801bc82:	f003 0303 	and.w	r3, r3, #3
+ 801bc86:	2b00      	cmp	r3, #0
+ 801bc88:	d001      	beq.n	801bc8e <tcp_receive+0x96a>
+ 801bc8a:	2301      	movs	r3, #1
+ 801bc8c:	e000      	b.n	801bc90 <tcp_receive+0x96c>
+ 801bc8e:	2300      	movs	r3, #0
+ 801bc90:	4423      	add	r3, r4
+ 801bc92:	b29a      	uxth	r2, r3
+ 801bc94:	4b65      	ldr	r3, [pc, #404]	; (801be2c <tcp_receive+0xb08>)
+ 801bc96:	801a      	strh	r2, [r3, #0]
+              LWIP_ASSERT("tcp_receive: segment not trimmed correctly to ooseq queue\n",
+ 801bc98:	4b64      	ldr	r3, [pc, #400]	; (801be2c <tcp_receive+0xb08>)
+ 801bc9a:	881b      	ldrh	r3, [r3, #0]
+ 801bc9c:	461a      	mov	r2, r3
+ 801bc9e:	4b64      	ldr	r3, [pc, #400]	; (801be30 <tcp_receive+0xb0c>)
+ 801bca0:	681b      	ldr	r3, [r3, #0]
+ 801bca2:	441a      	add	r2, r3
+ 801bca4:	6bfb      	ldr	r3, [r7, #60]	; 0x3c
+ 801bca6:	691b      	ldr	r3, [r3, #16]
+ 801bca8:	685b      	ldr	r3, [r3, #4]
+ 801bcaa:	429a      	cmp	r2, r3
+ 801bcac:	d006      	beq.n	801bcbc <tcp_receive+0x998>
+ 801bcae:	4b62      	ldr	r3, [pc, #392]	; (801be38 <tcp_receive+0xb14>)
+ 801bcb0:	f240 52fc 	movw	r2, #1532	; 0x5fc
+ 801bcb4:	4961      	ldr	r1, [pc, #388]	; (801be3c <tcp_receive+0xb18>)
+ 801bcb6:	4862      	ldr	r0, [pc, #392]	; (801be40 <tcp_receive+0xb1c>)
+ 801bcb8:	f005 fe66 	bl	8021988 <iprintf>
+                          (seqno + tcplen) == next->tcphdr->seqno);
+            }
+            pcb->ooseq = next;
+ 801bcbc:	687b      	ldr	r3, [r7, #4]
+ 801bcbe:	6bfa      	ldr	r2, [r7, #60]	; 0x3c
+ 801bcc0:	675a      	str	r2, [r3, #116]	; 0x74
+          }
+        }
+#endif /* TCP_QUEUE_OOSEQ */
+
+        pcb->rcv_nxt = seqno + tcplen;
+ 801bcc2:	4b5a      	ldr	r3, [pc, #360]	; (801be2c <tcp_receive+0xb08>)
+ 801bcc4:	881b      	ldrh	r3, [r3, #0]
+ 801bcc6:	461a      	mov	r2, r3
+ 801bcc8:	4b59      	ldr	r3, [pc, #356]	; (801be30 <tcp_receive+0xb0c>)
+ 801bcca:	681b      	ldr	r3, [r3, #0]
+ 801bccc:	441a      	add	r2, r3
+ 801bcce:	687b      	ldr	r3, [r7, #4]
+ 801bcd0:	625a      	str	r2, [r3, #36]	; 0x24
+
+        /* Update the receiver's (our) window. */
+        LWIP_ASSERT("tcp_receive: tcplen > rcv_wnd\n", pcb->rcv_wnd >= tcplen);
+ 801bcd2:	687b      	ldr	r3, [r7, #4]
+ 801bcd4:	8d1a      	ldrh	r2, [r3, #40]	; 0x28
+ 801bcd6:	4b55      	ldr	r3, [pc, #340]	; (801be2c <tcp_receive+0xb08>)
+ 801bcd8:	881b      	ldrh	r3, [r3, #0]
+ 801bcda:	429a      	cmp	r2, r3
+ 801bcdc:	d206      	bcs.n	801bcec <tcp_receive+0x9c8>
+ 801bcde:	4b56      	ldr	r3, [pc, #344]	; (801be38 <tcp_receive+0xb14>)
+ 801bce0:	f240 6207 	movw	r2, #1543	; 0x607
+ 801bce4:	4957      	ldr	r1, [pc, #348]	; (801be44 <tcp_receive+0xb20>)
+ 801bce6:	4856      	ldr	r0, [pc, #344]	; (801be40 <tcp_receive+0xb1c>)
+ 801bce8:	f005 fe4e 	bl	8021988 <iprintf>
+        pcb->rcv_wnd -= tcplen;
+ 801bcec:	687b      	ldr	r3, [r7, #4]
+ 801bcee:	8d1a      	ldrh	r2, [r3, #40]	; 0x28
+ 801bcf0:	4b4e      	ldr	r3, [pc, #312]	; (801be2c <tcp_receive+0xb08>)
+ 801bcf2:	881b      	ldrh	r3, [r3, #0]
+ 801bcf4:	1ad3      	subs	r3, r2, r3
+ 801bcf6:	b29a      	uxth	r2, r3
+ 801bcf8:	687b      	ldr	r3, [r7, #4]
+ 801bcfa:	851a      	strh	r2, [r3, #40]	; 0x28
+
+        tcp_update_rcv_ann_wnd(pcb);
+ 801bcfc:	6878      	ldr	r0, [r7, #4]
+ 801bcfe:	f7fc fd8f 	bl	8018820 <tcp_update_rcv_ann_wnd>
+           chains its data on this pbuf as well.
+
+           If the segment was a FIN, we set the TF_GOT_FIN flag that will
+           be used to indicate to the application that the remote side has
+           closed its end of the connection. */
+        if (inseg.p->tot_len > 0) {
+ 801bd02:	4b4c      	ldr	r3, [pc, #304]	; (801be34 <tcp_receive+0xb10>)
+ 801bd04:	685b      	ldr	r3, [r3, #4]
+ 801bd06:	891b      	ldrh	r3, [r3, #8]
+ 801bd08:	2b00      	cmp	r3, #0
+ 801bd0a:	d006      	beq.n	801bd1a <tcp_receive+0x9f6>
+          recv_data = inseg.p;
+ 801bd0c:	4b49      	ldr	r3, [pc, #292]	; (801be34 <tcp_receive+0xb10>)
+ 801bd0e:	685b      	ldr	r3, [r3, #4]
+ 801bd10:	4a4d      	ldr	r2, [pc, #308]	; (801be48 <tcp_receive+0xb24>)
+ 801bd12:	6013      	str	r3, [r2, #0]
+          /* Since this pbuf now is the responsibility of the
+             application, we delete our reference to it so that we won't
+             (mistakingly) deallocate it. */
+          inseg.p = NULL;
+ 801bd14:	4b47      	ldr	r3, [pc, #284]	; (801be34 <tcp_receive+0xb10>)
+ 801bd16:	2200      	movs	r2, #0
+ 801bd18:	605a      	str	r2, [r3, #4]
+        }
+        if (TCPH_FLAGS(inseg.tcphdr) & TCP_FIN) {
+ 801bd1a:	4b46      	ldr	r3, [pc, #280]	; (801be34 <tcp_receive+0xb10>)
+ 801bd1c:	691b      	ldr	r3, [r3, #16]
+ 801bd1e:	899b      	ldrh	r3, [r3, #12]
+ 801bd20:	b29b      	uxth	r3, r3
+ 801bd22:	4618      	mov	r0, r3
+ 801bd24:	f7fa f90c 	bl	8015f40 <lwip_htons>
+ 801bd28:	4603      	mov	r3, r0
+ 801bd2a:	b2db      	uxtb	r3, r3
+ 801bd2c:	f003 0301 	and.w	r3, r3, #1
+ 801bd30:	2b00      	cmp	r3, #0
+ 801bd32:	f000 80b8 	beq.w	801bea6 <tcp_receive+0xb82>
+          LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: received FIN.\n"));
+          recv_flags |= TF_GOT_FIN;
+ 801bd36:	4b45      	ldr	r3, [pc, #276]	; (801be4c <tcp_receive+0xb28>)
+ 801bd38:	781b      	ldrb	r3, [r3, #0]
+ 801bd3a:	f043 0320 	orr.w	r3, r3, #32
+ 801bd3e:	b2da      	uxtb	r2, r3
+ 801bd40:	4b42      	ldr	r3, [pc, #264]	; (801be4c <tcp_receive+0xb28>)
+ 801bd42:	701a      	strb	r2, [r3, #0]
+        }
+
+#if TCP_QUEUE_OOSEQ
+        /* We now check if we have segments on the ->ooseq queue that
+           are now in sequence. */
+        while (pcb->ooseq != NULL &&
+ 801bd44:	e0af      	b.n	801bea6 <tcp_receive+0xb82>
+               pcb->ooseq->tcphdr->seqno == pcb->rcv_nxt) {
+
+          struct tcp_seg *cseg = pcb->ooseq;
+ 801bd46:	687b      	ldr	r3, [r7, #4]
+ 801bd48:	6f5b      	ldr	r3, [r3, #116]	; 0x74
+ 801bd4a:	60bb      	str	r3, [r7, #8]
+          seqno = pcb->ooseq->tcphdr->seqno;
+ 801bd4c:	687b      	ldr	r3, [r7, #4]
+ 801bd4e:	6f5b      	ldr	r3, [r3, #116]	; 0x74
+ 801bd50:	691b      	ldr	r3, [r3, #16]
+ 801bd52:	685b      	ldr	r3, [r3, #4]
+ 801bd54:	4a36      	ldr	r2, [pc, #216]	; (801be30 <tcp_receive+0xb0c>)
+ 801bd56:	6013      	str	r3, [r2, #0]
+
+          pcb->rcv_nxt += TCP_TCPLEN(cseg);
+ 801bd58:	68bb      	ldr	r3, [r7, #8]
+ 801bd5a:	891b      	ldrh	r3, [r3, #8]
+ 801bd5c:	461c      	mov	r4, r3
+ 801bd5e:	68bb      	ldr	r3, [r7, #8]
+ 801bd60:	691b      	ldr	r3, [r3, #16]
+ 801bd62:	899b      	ldrh	r3, [r3, #12]
+ 801bd64:	b29b      	uxth	r3, r3
+ 801bd66:	4618      	mov	r0, r3
+ 801bd68:	f7fa f8ea 	bl	8015f40 <lwip_htons>
+ 801bd6c:	4603      	mov	r3, r0
+ 801bd6e:	b2db      	uxtb	r3, r3
+ 801bd70:	f003 0303 	and.w	r3, r3, #3
+ 801bd74:	2b00      	cmp	r3, #0
+ 801bd76:	d001      	beq.n	801bd7c <tcp_receive+0xa58>
+ 801bd78:	2301      	movs	r3, #1
+ 801bd7a:	e000      	b.n	801bd7e <tcp_receive+0xa5a>
+ 801bd7c:	2300      	movs	r3, #0
+ 801bd7e:	191a      	adds	r2, r3, r4
+ 801bd80:	687b      	ldr	r3, [r7, #4]
+ 801bd82:	6a5b      	ldr	r3, [r3, #36]	; 0x24
+ 801bd84:	441a      	add	r2, r3
+ 801bd86:	687b      	ldr	r3, [r7, #4]
+ 801bd88:	625a      	str	r2, [r3, #36]	; 0x24
+          LWIP_ASSERT("tcp_receive: ooseq tcplen > rcv_wnd\n",
+ 801bd8a:	687b      	ldr	r3, [r7, #4]
+ 801bd8c:	8d1b      	ldrh	r3, [r3, #40]	; 0x28
+ 801bd8e:	461c      	mov	r4, r3
+ 801bd90:	68bb      	ldr	r3, [r7, #8]
+ 801bd92:	891b      	ldrh	r3, [r3, #8]
+ 801bd94:	461d      	mov	r5, r3
+ 801bd96:	68bb      	ldr	r3, [r7, #8]
+ 801bd98:	691b      	ldr	r3, [r3, #16]
+ 801bd9a:	899b      	ldrh	r3, [r3, #12]
+ 801bd9c:	b29b      	uxth	r3, r3
+ 801bd9e:	4618      	mov	r0, r3
+ 801bda0:	f7fa f8ce 	bl	8015f40 <lwip_htons>
+ 801bda4:	4603      	mov	r3, r0
+ 801bda6:	b2db      	uxtb	r3, r3
+ 801bda8:	f003 0303 	and.w	r3, r3, #3
+ 801bdac:	2b00      	cmp	r3, #0
+ 801bdae:	d001      	beq.n	801bdb4 <tcp_receive+0xa90>
+ 801bdb0:	2301      	movs	r3, #1
+ 801bdb2:	e000      	b.n	801bdb6 <tcp_receive+0xa92>
+ 801bdb4:	2300      	movs	r3, #0
+ 801bdb6:	442b      	add	r3, r5
+ 801bdb8:	429c      	cmp	r4, r3
+ 801bdba:	d206      	bcs.n	801bdca <tcp_receive+0xaa6>
+ 801bdbc:	4b1e      	ldr	r3, [pc, #120]	; (801be38 <tcp_receive+0xb14>)
+ 801bdbe:	f240 622b 	movw	r2, #1579	; 0x62b
+ 801bdc2:	4923      	ldr	r1, [pc, #140]	; (801be50 <tcp_receive+0xb2c>)
+ 801bdc4:	481e      	ldr	r0, [pc, #120]	; (801be40 <tcp_receive+0xb1c>)
+ 801bdc6:	f005 fddf 	bl	8021988 <iprintf>
+                      pcb->rcv_wnd >= TCP_TCPLEN(cseg));
+          pcb->rcv_wnd -= TCP_TCPLEN(cseg);
+ 801bdca:	68bb      	ldr	r3, [r7, #8]
+ 801bdcc:	891b      	ldrh	r3, [r3, #8]
+ 801bdce:	461c      	mov	r4, r3
+ 801bdd0:	68bb      	ldr	r3, [r7, #8]
+ 801bdd2:	691b      	ldr	r3, [r3, #16]
+ 801bdd4:	899b      	ldrh	r3, [r3, #12]
+ 801bdd6:	b29b      	uxth	r3, r3
+ 801bdd8:	4618      	mov	r0, r3
+ 801bdda:	f7fa f8b1 	bl	8015f40 <lwip_htons>
+ 801bdde:	4603      	mov	r3, r0
+ 801bde0:	b2db      	uxtb	r3, r3
+ 801bde2:	f003 0303 	and.w	r3, r3, #3
+ 801bde6:	2b00      	cmp	r3, #0
+ 801bde8:	d001      	beq.n	801bdee <tcp_receive+0xaca>
+ 801bdea:	2301      	movs	r3, #1
+ 801bdec:	e000      	b.n	801bdf0 <tcp_receive+0xacc>
+ 801bdee:	2300      	movs	r3, #0
+ 801bdf0:	1919      	adds	r1, r3, r4
+ 801bdf2:	687b      	ldr	r3, [r7, #4]
+ 801bdf4:	8d1a      	ldrh	r2, [r3, #40]	; 0x28
+ 801bdf6:	b28b      	uxth	r3, r1
+ 801bdf8:	1ad3      	subs	r3, r2, r3
+ 801bdfa:	b29a      	uxth	r2, r3
+ 801bdfc:	687b      	ldr	r3, [r7, #4]
+ 801bdfe:	851a      	strh	r2, [r3, #40]	; 0x28
+
+          tcp_update_rcv_ann_wnd(pcb);
+ 801be00:	6878      	ldr	r0, [r7, #4]
+ 801be02:	f7fc fd0d 	bl	8018820 <tcp_update_rcv_ann_wnd>
+
+          if (cseg->p->tot_len > 0) {
+ 801be06:	68bb      	ldr	r3, [r7, #8]
+ 801be08:	685b      	ldr	r3, [r3, #4]
+ 801be0a:	891b      	ldrh	r3, [r3, #8]
+ 801be0c:	2b00      	cmp	r3, #0
+ 801be0e:	d028      	beq.n	801be62 <tcp_receive+0xb3e>
+            /* Chain this pbuf onto the pbuf that we will pass to
+               the application. */
+            /* With window scaling, this can overflow recv_data->tot_len, but
+               that's not a problem since we explicitly fix that before passing
+               recv_data to the application. */
+            if (recv_data) {
+ 801be10:	4b0d      	ldr	r3, [pc, #52]	; (801be48 <tcp_receive+0xb24>)
+ 801be12:	681b      	ldr	r3, [r3, #0]
+ 801be14:	2b00      	cmp	r3, #0
+ 801be16:	d01d      	beq.n	801be54 <tcp_receive+0xb30>
+              pbuf_cat(recv_data, cseg->p);
+ 801be18:	4b0b      	ldr	r3, [pc, #44]	; (801be48 <tcp_receive+0xb24>)
+ 801be1a:	681a      	ldr	r2, [r3, #0]
+ 801be1c:	68bb      	ldr	r3, [r7, #8]
+ 801be1e:	685b      	ldr	r3, [r3, #4]
+ 801be20:	4619      	mov	r1, r3
+ 801be22:	4610      	mov	r0, r2
+ 801be24:	f7fb ff36 	bl	8017c94 <pbuf_cat>
+ 801be28:	e018      	b.n	801be5c <tcp_receive+0xb38>
+ 801be2a:	bf00      	nop
+ 801be2c:	2401a4c6 	.word	0x2401a4c6
+ 801be30:	2401a4bc 	.word	0x2401a4bc
+ 801be34:	2401a498 	.word	0x2401a498
+ 801be38:	08025338 	.word	0x08025338
+ 801be3c:	08025718 	.word	0x08025718
+ 801be40:	08025384 	.word	0x08025384
+ 801be44:	08025754 	.word	0x08025754
+ 801be48:	2401a4cc 	.word	0x2401a4cc
+ 801be4c:	2401a4c9 	.word	0x2401a4c9
+ 801be50:	08025774 	.word	0x08025774
+            } else {
+              recv_data = cseg->p;
+ 801be54:	68bb      	ldr	r3, [r7, #8]
+ 801be56:	685b      	ldr	r3, [r3, #4]
+ 801be58:	4a70      	ldr	r2, [pc, #448]	; (801c01c <tcp_receive+0xcf8>)
+ 801be5a:	6013      	str	r3, [r2, #0]
+            }
+            cseg->p = NULL;
+ 801be5c:	68bb      	ldr	r3, [r7, #8]
+ 801be5e:	2200      	movs	r2, #0
+ 801be60:	605a      	str	r2, [r3, #4]
+          }
+          if (TCPH_FLAGS(cseg->tcphdr) & TCP_FIN) {
+ 801be62:	68bb      	ldr	r3, [r7, #8]
+ 801be64:	691b      	ldr	r3, [r3, #16]
+ 801be66:	899b      	ldrh	r3, [r3, #12]
+ 801be68:	b29b      	uxth	r3, r3
+ 801be6a:	4618      	mov	r0, r3
+ 801be6c:	f7fa f868 	bl	8015f40 <lwip_htons>
+ 801be70:	4603      	mov	r3, r0
+ 801be72:	b2db      	uxtb	r3, r3
+ 801be74:	f003 0301 	and.w	r3, r3, #1
+ 801be78:	2b00      	cmp	r3, #0
+ 801be7a:	d00d      	beq.n	801be98 <tcp_receive+0xb74>
+            LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: dequeued FIN.\n"));
+            recv_flags |= TF_GOT_FIN;
+ 801be7c:	4b68      	ldr	r3, [pc, #416]	; (801c020 <tcp_receive+0xcfc>)
+ 801be7e:	781b      	ldrb	r3, [r3, #0]
+ 801be80:	f043 0320 	orr.w	r3, r3, #32
+ 801be84:	b2da      	uxtb	r2, r3
+ 801be86:	4b66      	ldr	r3, [pc, #408]	; (801c020 <tcp_receive+0xcfc>)
+ 801be88:	701a      	strb	r2, [r3, #0]
+            if (pcb->state == ESTABLISHED) { /* force passive close or we can move to active close */
+ 801be8a:	687b      	ldr	r3, [r7, #4]
+ 801be8c:	7d1b      	ldrb	r3, [r3, #20]
+ 801be8e:	2b04      	cmp	r3, #4
+ 801be90:	d102      	bne.n	801be98 <tcp_receive+0xb74>
+              pcb->state = CLOSE_WAIT;
+ 801be92:	687b      	ldr	r3, [r7, #4]
+ 801be94:	2207      	movs	r2, #7
+ 801be96:	751a      	strb	r2, [r3, #20]
+            }
+          }
+
+          pcb->ooseq = cseg->next;
+ 801be98:	68bb      	ldr	r3, [r7, #8]
+ 801be9a:	681a      	ldr	r2, [r3, #0]
+ 801be9c:	687b      	ldr	r3, [r7, #4]
+ 801be9e:	675a      	str	r2, [r3, #116]	; 0x74
+          tcp_seg_free(cseg);
+ 801bea0:	68b8      	ldr	r0, [r7, #8]
+ 801bea2:	f7fd fafe 	bl	80194a2 <tcp_seg_free>
+        while (pcb->ooseq != NULL &&
+ 801bea6:	687b      	ldr	r3, [r7, #4]
+ 801bea8:	6f5b      	ldr	r3, [r3, #116]	; 0x74
+ 801beaa:	2b00      	cmp	r3, #0
+ 801beac:	d008      	beq.n	801bec0 <tcp_receive+0xb9c>
+               pcb->ooseq->tcphdr->seqno == pcb->rcv_nxt) {
+ 801beae:	687b      	ldr	r3, [r7, #4]
+ 801beb0:	6f5b      	ldr	r3, [r3, #116]	; 0x74
+ 801beb2:	691b      	ldr	r3, [r3, #16]
+ 801beb4:	685a      	ldr	r2, [r3, #4]
+ 801beb6:	687b      	ldr	r3, [r7, #4]
+ 801beb8:	6a5b      	ldr	r3, [r3, #36]	; 0x24
+        while (pcb->ooseq != NULL &&
+ 801beba:	429a      	cmp	r2, r3
+ 801bebc:	f43f af43 	beq.w	801bd46 <tcp_receive+0xa22>
+#endif /* LWIP_TCP_SACK_OUT */
+#endif /* TCP_QUEUE_OOSEQ */
+
+
+        /* Acknowledge the segment(s). */
+        tcp_ack(pcb);
+ 801bec0:	687b      	ldr	r3, [r7, #4]
+ 801bec2:	8b5b      	ldrh	r3, [r3, #26]
+ 801bec4:	f003 0301 	and.w	r3, r3, #1
+ 801bec8:	2b00      	cmp	r3, #0
+ 801beca:	d00e      	beq.n	801beea <tcp_receive+0xbc6>
+ 801becc:	687b      	ldr	r3, [r7, #4]
+ 801bece:	8b5b      	ldrh	r3, [r3, #26]
+ 801bed0:	f023 0301 	bic.w	r3, r3, #1
+ 801bed4:	b29a      	uxth	r2, r3
+ 801bed6:	687b      	ldr	r3, [r7, #4]
+ 801bed8:	835a      	strh	r2, [r3, #26]
+ 801beda:	687b      	ldr	r3, [r7, #4]
+ 801bedc:	8b5b      	ldrh	r3, [r3, #26]
+ 801bede:	f043 0302 	orr.w	r3, r3, #2
+ 801bee2:	b29a      	uxth	r2, r3
+ 801bee4:	687b      	ldr	r3, [r7, #4]
+ 801bee6:	835a      	strh	r2, [r3, #26]
+      if (pcb->rcv_nxt == seqno) {
+ 801bee8:	e188      	b.n	801c1fc <tcp_receive+0xed8>
+        tcp_ack(pcb);
+ 801beea:	687b      	ldr	r3, [r7, #4]
+ 801beec:	8b5b      	ldrh	r3, [r3, #26]
+ 801beee:	f043 0301 	orr.w	r3, r3, #1
+ 801bef2:	b29a      	uxth	r2, r3
+ 801bef4:	687b      	ldr	r3, [r7, #4]
+ 801bef6:	835a      	strh	r2, [r3, #26]
+      if (pcb->rcv_nxt == seqno) {
+ 801bef8:	e180      	b.n	801c1fc <tcp_receive+0xed8>
+      } else {
+        /* We get here if the incoming segment is out-of-sequence. */
+
+#if TCP_QUEUE_OOSEQ
+        /* We queue the segment on the ->ooseq queue. */
+        if (pcb->ooseq == NULL) {
+ 801befa:	687b      	ldr	r3, [r7, #4]
+ 801befc:	6f5b      	ldr	r3, [r3, #116]	; 0x74
+ 801befe:	2b00      	cmp	r3, #0
+ 801bf00:	d106      	bne.n	801bf10 <tcp_receive+0xbec>
+          pcb->ooseq = tcp_seg_copy(&inseg);
+ 801bf02:	4848      	ldr	r0, [pc, #288]	; (801c024 <tcp_receive+0xd00>)
+ 801bf04:	f7fd fae6 	bl	80194d4 <tcp_seg_copy>
+ 801bf08:	4602      	mov	r2, r0
+ 801bf0a:	687b      	ldr	r3, [r7, #4]
+ 801bf0c:	675a      	str	r2, [r3, #116]	; 0x74
+ 801bf0e:	e16d      	b.n	801c1ec <tcp_receive+0xec8>
+#if LWIP_TCP_SACK_OUT
+          /* This is the left edge of the lowest possible SACK range.
+             It may start before the newly received segment (possibly adjusted below). */
+          u32_t sackbeg = TCP_SEQ_LT(seqno, pcb->ooseq->tcphdr->seqno) ? seqno : pcb->ooseq->tcphdr->seqno;
+#endif /* LWIP_TCP_SACK_OUT */
+          struct tcp_seg *next, *prev = NULL;
+ 801bf10:	2300      	movs	r3, #0
+ 801bf12:	637b      	str	r3, [r7, #52]	; 0x34
+          for (next = pcb->ooseq; next != NULL; next = next->next) {
+ 801bf14:	687b      	ldr	r3, [r7, #4]
+ 801bf16:	6f5b      	ldr	r3, [r3, #116]	; 0x74
+ 801bf18:	63bb      	str	r3, [r7, #56]	; 0x38
+ 801bf1a:	e157      	b.n	801c1cc <tcp_receive+0xea8>
+            if (seqno == next->tcphdr->seqno) {
+ 801bf1c:	6bbb      	ldr	r3, [r7, #56]	; 0x38
+ 801bf1e:	691b      	ldr	r3, [r3, #16]
+ 801bf20:	685a      	ldr	r2, [r3, #4]
+ 801bf22:	4b41      	ldr	r3, [pc, #260]	; (801c028 <tcp_receive+0xd04>)
+ 801bf24:	681b      	ldr	r3, [r3, #0]
+ 801bf26:	429a      	cmp	r2, r3
+ 801bf28:	d11d      	bne.n	801bf66 <tcp_receive+0xc42>
+              /* The sequence number of the incoming segment is the
+                 same as the sequence number of the segment on
+                 ->ooseq. We check the lengths to see which one to
+                 discard. */
+              if (inseg.len > next->len) {
+ 801bf2a:	4b3e      	ldr	r3, [pc, #248]	; (801c024 <tcp_receive+0xd00>)
+ 801bf2c:	891a      	ldrh	r2, [r3, #8]
+ 801bf2e:	6bbb      	ldr	r3, [r7, #56]	; 0x38
+ 801bf30:	891b      	ldrh	r3, [r3, #8]
+ 801bf32:	429a      	cmp	r2, r3
+ 801bf34:	f240 814f 	bls.w	801c1d6 <tcp_receive+0xeb2>
+                /* The incoming segment is larger than the old
+                   segment. We replace some segments with the new
+                   one. */
+                struct tcp_seg *cseg = tcp_seg_copy(&inseg);
+ 801bf38:	483a      	ldr	r0, [pc, #232]	; (801c024 <tcp_receive+0xd00>)
+ 801bf3a:	f7fd facb 	bl	80194d4 <tcp_seg_copy>
+ 801bf3e:	6178      	str	r0, [r7, #20]
+                if (cseg != NULL) {
+ 801bf40:	697b      	ldr	r3, [r7, #20]
+ 801bf42:	2b00      	cmp	r3, #0
+ 801bf44:	f000 8149 	beq.w	801c1da <tcp_receive+0xeb6>
+                  if (prev != NULL) {
+ 801bf48:	6b7b      	ldr	r3, [r7, #52]	; 0x34
+ 801bf4a:	2b00      	cmp	r3, #0
+ 801bf4c:	d003      	beq.n	801bf56 <tcp_receive+0xc32>
+                    prev->next = cseg;
+ 801bf4e:	6b7b      	ldr	r3, [r7, #52]	; 0x34
+ 801bf50:	697a      	ldr	r2, [r7, #20]
+ 801bf52:	601a      	str	r2, [r3, #0]
+ 801bf54:	e002      	b.n	801bf5c <tcp_receive+0xc38>
+                  } else {
+                    pcb->ooseq = cseg;
+ 801bf56:	687b      	ldr	r3, [r7, #4]
+ 801bf58:	697a      	ldr	r2, [r7, #20]
+ 801bf5a:	675a      	str	r2, [r3, #116]	; 0x74
+                  }
+                  tcp_oos_insert_segment(cseg, next);
+ 801bf5c:	6bb9      	ldr	r1, [r7, #56]	; 0x38
+ 801bf5e:	6978      	ldr	r0, [r7, #20]
+ 801bf60:	f7ff f8dc 	bl	801b11c <tcp_oos_insert_segment>
+                }
+                break;
+ 801bf64:	e139      	b.n	801c1da <tcp_receive+0xeb6>
+                   segment was smaller than the old one; in either
+                   case, we ditch the incoming segment. */
+                break;
+              }
+            } else {
+              if (prev == NULL) {
+ 801bf66:	6b7b      	ldr	r3, [r7, #52]	; 0x34
+ 801bf68:	2b00      	cmp	r3, #0
+ 801bf6a:	d117      	bne.n	801bf9c <tcp_receive+0xc78>
+                if (TCP_SEQ_LT(seqno, next->tcphdr->seqno)) {
+ 801bf6c:	4b2e      	ldr	r3, [pc, #184]	; (801c028 <tcp_receive+0xd04>)
+ 801bf6e:	681a      	ldr	r2, [r3, #0]
+ 801bf70:	6bbb      	ldr	r3, [r7, #56]	; 0x38
+ 801bf72:	691b      	ldr	r3, [r3, #16]
+ 801bf74:	685b      	ldr	r3, [r3, #4]
+ 801bf76:	1ad3      	subs	r3, r2, r3
+ 801bf78:	2b00      	cmp	r3, #0
+ 801bf7a:	da57      	bge.n	801c02c <tcp_receive+0xd08>
+                  /* The sequence number of the incoming segment is lower
+                     than the sequence number of the first segment on the
+                     queue. We put the incoming segment first on the
+                     queue. */
+                  struct tcp_seg *cseg = tcp_seg_copy(&inseg);
+ 801bf7c:	4829      	ldr	r0, [pc, #164]	; (801c024 <tcp_receive+0xd00>)
+ 801bf7e:	f7fd faa9 	bl	80194d4 <tcp_seg_copy>
+ 801bf82:	61b8      	str	r0, [r7, #24]
+                  if (cseg != NULL) {
+ 801bf84:	69bb      	ldr	r3, [r7, #24]
+ 801bf86:	2b00      	cmp	r3, #0
+ 801bf88:	f000 8129 	beq.w	801c1de <tcp_receive+0xeba>
+                    pcb->ooseq = cseg;
+ 801bf8c:	687b      	ldr	r3, [r7, #4]
+ 801bf8e:	69ba      	ldr	r2, [r7, #24]
+ 801bf90:	675a      	str	r2, [r3, #116]	; 0x74
+                    tcp_oos_insert_segment(cseg, next);
+ 801bf92:	6bb9      	ldr	r1, [r7, #56]	; 0x38
+ 801bf94:	69b8      	ldr	r0, [r7, #24]
+ 801bf96:	f7ff f8c1 	bl	801b11c <tcp_oos_insert_segment>
+                  }
+                  break;
+ 801bf9a:	e120      	b.n	801c1de <tcp_receive+0xeba>
+                }
+              } else {
+                /*if (TCP_SEQ_LT(prev->tcphdr->seqno, seqno) &&
+                  TCP_SEQ_LT(seqno, next->tcphdr->seqno)) {*/
+                if (TCP_SEQ_BETWEEN(seqno, prev->tcphdr->seqno + 1, next->tcphdr->seqno - 1)) {
+ 801bf9c:	4b22      	ldr	r3, [pc, #136]	; (801c028 <tcp_receive+0xd04>)
+ 801bf9e:	681a      	ldr	r2, [r3, #0]
+ 801bfa0:	6b7b      	ldr	r3, [r7, #52]	; 0x34
+ 801bfa2:	691b      	ldr	r3, [r3, #16]
+ 801bfa4:	685b      	ldr	r3, [r3, #4]
+ 801bfa6:	1ad3      	subs	r3, r2, r3
+ 801bfa8:	3b01      	subs	r3, #1
+ 801bfaa:	2b00      	cmp	r3, #0
+ 801bfac:	db3e      	blt.n	801c02c <tcp_receive+0xd08>
+ 801bfae:	4b1e      	ldr	r3, [pc, #120]	; (801c028 <tcp_receive+0xd04>)
+ 801bfb0:	681a      	ldr	r2, [r3, #0]
+ 801bfb2:	6bbb      	ldr	r3, [r7, #56]	; 0x38
+ 801bfb4:	691b      	ldr	r3, [r3, #16]
+ 801bfb6:	685b      	ldr	r3, [r3, #4]
+ 801bfb8:	1ad3      	subs	r3, r2, r3
+ 801bfba:	3301      	adds	r3, #1
+ 801bfbc:	2b00      	cmp	r3, #0
+ 801bfbe:	dc35      	bgt.n	801c02c <tcp_receive+0xd08>
+                  /* The sequence number of the incoming segment is in
+                     between the sequence numbers of the previous and
+                     the next segment on ->ooseq. We trim trim the previous
+                     segment, delete next segments that included in received segment
+                     and trim received, if needed. */
+                  struct tcp_seg *cseg = tcp_seg_copy(&inseg);
+ 801bfc0:	4818      	ldr	r0, [pc, #96]	; (801c024 <tcp_receive+0xd00>)
+ 801bfc2:	f7fd fa87 	bl	80194d4 <tcp_seg_copy>
+ 801bfc6:	61f8      	str	r0, [r7, #28]
+                  if (cseg != NULL) {
+ 801bfc8:	69fb      	ldr	r3, [r7, #28]
+ 801bfca:	2b00      	cmp	r3, #0
+ 801bfcc:	f000 8109 	beq.w	801c1e2 <tcp_receive+0xebe>
+                    if (TCP_SEQ_GT(prev->tcphdr->seqno + prev->len, seqno)) {
+ 801bfd0:	6b7b      	ldr	r3, [r7, #52]	; 0x34
+ 801bfd2:	691b      	ldr	r3, [r3, #16]
+ 801bfd4:	685b      	ldr	r3, [r3, #4]
+ 801bfd6:	6b7a      	ldr	r2, [r7, #52]	; 0x34
+ 801bfd8:	8912      	ldrh	r2, [r2, #8]
+ 801bfda:	441a      	add	r2, r3
+ 801bfdc:	4b12      	ldr	r3, [pc, #72]	; (801c028 <tcp_receive+0xd04>)
+ 801bfde:	681b      	ldr	r3, [r3, #0]
+ 801bfe0:	1ad3      	subs	r3, r2, r3
+ 801bfe2:	2b00      	cmp	r3, #0
+ 801bfe4:	dd12      	ble.n	801c00c <tcp_receive+0xce8>
+                      /* We need to trim the prev segment. */
+                      prev->len = (u16_t)(seqno - prev->tcphdr->seqno);
+ 801bfe6:	4b10      	ldr	r3, [pc, #64]	; (801c028 <tcp_receive+0xd04>)
+ 801bfe8:	681b      	ldr	r3, [r3, #0]
+ 801bfea:	b29a      	uxth	r2, r3
+ 801bfec:	6b7b      	ldr	r3, [r7, #52]	; 0x34
+ 801bfee:	691b      	ldr	r3, [r3, #16]
+ 801bff0:	685b      	ldr	r3, [r3, #4]
+ 801bff2:	b29b      	uxth	r3, r3
+ 801bff4:	1ad3      	subs	r3, r2, r3
+ 801bff6:	b29a      	uxth	r2, r3
+ 801bff8:	6b7b      	ldr	r3, [r7, #52]	; 0x34
+ 801bffa:	811a      	strh	r2, [r3, #8]
+                      pbuf_realloc(prev->p, prev->len);
+ 801bffc:	6b7b      	ldr	r3, [r7, #52]	; 0x34
+ 801bffe:	685a      	ldr	r2, [r3, #4]
+ 801c000:	6b7b      	ldr	r3, [r7, #52]	; 0x34
+ 801c002:	891b      	ldrh	r3, [r3, #8]
+ 801c004:	4619      	mov	r1, r3
+ 801c006:	4610      	mov	r0, r2
+ 801c008:	f7fb fbf0 	bl	80177ec <pbuf_realloc>
+                    }
+                    prev->next = cseg;
+ 801c00c:	6b7b      	ldr	r3, [r7, #52]	; 0x34
+ 801c00e:	69fa      	ldr	r2, [r7, #28]
+ 801c010:	601a      	str	r2, [r3, #0]
+                    tcp_oos_insert_segment(cseg, next);
+ 801c012:	6bb9      	ldr	r1, [r7, #56]	; 0x38
+ 801c014:	69f8      	ldr	r0, [r7, #28]
+ 801c016:	f7ff f881 	bl	801b11c <tcp_oos_insert_segment>
+                  }
+                  break;
+ 801c01a:	e0e2      	b.n	801c1e2 <tcp_receive+0xebe>
+ 801c01c:	2401a4cc 	.word	0x2401a4cc
+ 801c020:	2401a4c9 	.word	0x2401a4c9
+ 801c024:	2401a498 	.word	0x2401a498
+ 801c028:	2401a4bc 	.word	0x2401a4bc
+#endif /* LWIP_TCP_SACK_OUT */
+
+              /* We don't use 'prev' below, so let's set it to current 'next'.
+                 This way even if we break the loop below, 'prev' will be pointing
+                 at the segment right in front of the newly added one. */
+              prev = next;
+ 801c02c:	6bbb      	ldr	r3, [r7, #56]	; 0x38
+ 801c02e:	637b      	str	r3, [r7, #52]	; 0x34
+
+              /* If the "next" segment is the last segment on the
+                 ooseq queue, we add the incoming segment to the end
+                 of the list. */
+              if (next->next == NULL &&
+ 801c030:	6bbb      	ldr	r3, [r7, #56]	; 0x38
+ 801c032:	681b      	ldr	r3, [r3, #0]
+ 801c034:	2b00      	cmp	r3, #0
+ 801c036:	f040 80c6 	bne.w	801c1c6 <tcp_receive+0xea2>
+                  TCP_SEQ_GT(seqno, next->tcphdr->seqno)) {
+ 801c03a:	4b80      	ldr	r3, [pc, #512]	; (801c23c <tcp_receive+0xf18>)
+ 801c03c:	681a      	ldr	r2, [r3, #0]
+ 801c03e:	6bbb      	ldr	r3, [r7, #56]	; 0x38
+ 801c040:	691b      	ldr	r3, [r3, #16]
+ 801c042:	685b      	ldr	r3, [r3, #4]
+ 801c044:	1ad3      	subs	r3, r2, r3
+              if (next->next == NULL &&
+ 801c046:	2b00      	cmp	r3, #0
+ 801c048:	f340 80bd 	ble.w	801c1c6 <tcp_receive+0xea2>
+                if (TCPH_FLAGS(next->tcphdr) & TCP_FIN) {
+ 801c04c:	6bbb      	ldr	r3, [r7, #56]	; 0x38
+ 801c04e:	691b      	ldr	r3, [r3, #16]
+ 801c050:	899b      	ldrh	r3, [r3, #12]
+ 801c052:	b29b      	uxth	r3, r3
+ 801c054:	4618      	mov	r0, r3
+ 801c056:	f7f9 ff73 	bl	8015f40 <lwip_htons>
+ 801c05a:	4603      	mov	r3, r0
+ 801c05c:	b2db      	uxtb	r3, r3
+ 801c05e:	f003 0301 	and.w	r3, r3, #1
+ 801c062:	2b00      	cmp	r3, #0
+ 801c064:	f040 80bf 	bne.w	801c1e6 <tcp_receive+0xec2>
+                  /* segment "next" already contains all data */
+                  break;
+                }
+                next->next = tcp_seg_copy(&inseg);
+ 801c068:	4875      	ldr	r0, [pc, #468]	; (801c240 <tcp_receive+0xf1c>)
+ 801c06a:	f7fd fa33 	bl	80194d4 <tcp_seg_copy>
+ 801c06e:	4602      	mov	r2, r0
+ 801c070:	6bbb      	ldr	r3, [r7, #56]	; 0x38
+ 801c072:	601a      	str	r2, [r3, #0]
+                if (next->next != NULL) {
+ 801c074:	6bbb      	ldr	r3, [r7, #56]	; 0x38
+ 801c076:	681b      	ldr	r3, [r3, #0]
+ 801c078:	2b00      	cmp	r3, #0
+ 801c07a:	f000 80b6 	beq.w	801c1ea <tcp_receive+0xec6>
+                  if (TCP_SEQ_GT(next->tcphdr->seqno + next->len, seqno)) {
+ 801c07e:	6bbb      	ldr	r3, [r7, #56]	; 0x38
+ 801c080:	691b      	ldr	r3, [r3, #16]
+ 801c082:	685b      	ldr	r3, [r3, #4]
+ 801c084:	6bba      	ldr	r2, [r7, #56]	; 0x38
+ 801c086:	8912      	ldrh	r2, [r2, #8]
+ 801c088:	441a      	add	r2, r3
+ 801c08a:	4b6c      	ldr	r3, [pc, #432]	; (801c23c <tcp_receive+0xf18>)
+ 801c08c:	681b      	ldr	r3, [r3, #0]
+ 801c08e:	1ad3      	subs	r3, r2, r3
+ 801c090:	2b00      	cmp	r3, #0
+ 801c092:	dd12      	ble.n	801c0ba <tcp_receive+0xd96>
+                    /* We need to trim the last segment. */
+                    next->len = (u16_t)(seqno - next->tcphdr->seqno);
+ 801c094:	4b69      	ldr	r3, [pc, #420]	; (801c23c <tcp_receive+0xf18>)
+ 801c096:	681b      	ldr	r3, [r3, #0]
+ 801c098:	b29a      	uxth	r2, r3
+ 801c09a:	6bbb      	ldr	r3, [r7, #56]	; 0x38
+ 801c09c:	691b      	ldr	r3, [r3, #16]
+ 801c09e:	685b      	ldr	r3, [r3, #4]
+ 801c0a0:	b29b      	uxth	r3, r3
+ 801c0a2:	1ad3      	subs	r3, r2, r3
+ 801c0a4:	b29a      	uxth	r2, r3
+ 801c0a6:	6bbb      	ldr	r3, [r7, #56]	; 0x38
+ 801c0a8:	811a      	strh	r2, [r3, #8]
+                    pbuf_realloc(next->p, next->len);
+ 801c0aa:	6bbb      	ldr	r3, [r7, #56]	; 0x38
+ 801c0ac:	685a      	ldr	r2, [r3, #4]
+ 801c0ae:	6bbb      	ldr	r3, [r7, #56]	; 0x38
+ 801c0b0:	891b      	ldrh	r3, [r3, #8]
+ 801c0b2:	4619      	mov	r1, r3
+ 801c0b4:	4610      	mov	r0, r2
+ 801c0b6:	f7fb fb99 	bl	80177ec <pbuf_realloc>
+                  }
+                  /* check if the remote side overruns our receive window */
+                  if (TCP_SEQ_GT((u32_t)tcplen + seqno, pcb->rcv_nxt + (u32_t)pcb->rcv_wnd)) {
+ 801c0ba:	4b62      	ldr	r3, [pc, #392]	; (801c244 <tcp_receive+0xf20>)
+ 801c0bc:	881b      	ldrh	r3, [r3, #0]
+ 801c0be:	461a      	mov	r2, r3
+ 801c0c0:	4b5e      	ldr	r3, [pc, #376]	; (801c23c <tcp_receive+0xf18>)
+ 801c0c2:	681b      	ldr	r3, [r3, #0]
+ 801c0c4:	441a      	add	r2, r3
+ 801c0c6:	687b      	ldr	r3, [r7, #4]
+ 801c0c8:	6a5b      	ldr	r3, [r3, #36]	; 0x24
+ 801c0ca:	6879      	ldr	r1, [r7, #4]
+ 801c0cc:	8d09      	ldrh	r1, [r1, #40]	; 0x28
+ 801c0ce:	440b      	add	r3, r1
+ 801c0d0:	1ad3      	subs	r3, r2, r3
+ 801c0d2:	2b00      	cmp	r3, #0
+ 801c0d4:	f340 8089 	ble.w	801c1ea <tcp_receive+0xec6>
+                    LWIP_DEBUGF(TCP_INPUT_DEBUG,
+                                ("tcp_receive: other end overran receive window"
+                                 "seqno %"U32_F" len %"U16_F" right edge %"U32_F"\n",
+                                 seqno, tcplen, pcb->rcv_nxt + pcb->rcv_wnd));
+                    if (TCPH_FLAGS(next->next->tcphdr) & TCP_FIN) {
+ 801c0d8:	6bbb      	ldr	r3, [r7, #56]	; 0x38
+ 801c0da:	681b      	ldr	r3, [r3, #0]
+ 801c0dc:	691b      	ldr	r3, [r3, #16]
+ 801c0de:	899b      	ldrh	r3, [r3, #12]
+ 801c0e0:	b29b      	uxth	r3, r3
+ 801c0e2:	4618      	mov	r0, r3
+ 801c0e4:	f7f9 ff2c 	bl	8015f40 <lwip_htons>
+ 801c0e8:	4603      	mov	r3, r0
+ 801c0ea:	b2db      	uxtb	r3, r3
+ 801c0ec:	f003 0301 	and.w	r3, r3, #1
+ 801c0f0:	2b00      	cmp	r3, #0
+ 801c0f2:	d022      	beq.n	801c13a <tcp_receive+0xe16>
+                      /* Must remove the FIN from the header as we're trimming
+                       * that byte of sequence-space from the packet */
+                      TCPH_FLAGS_SET(next->next->tcphdr, TCPH_FLAGS(next->next->tcphdr) & ~TCP_FIN);
+ 801c0f4:	6bbb      	ldr	r3, [r7, #56]	; 0x38
+ 801c0f6:	681b      	ldr	r3, [r3, #0]
+ 801c0f8:	691b      	ldr	r3, [r3, #16]
+ 801c0fa:	899b      	ldrh	r3, [r3, #12]
+ 801c0fc:	b29b      	uxth	r3, r3
+ 801c0fe:	b21b      	sxth	r3, r3
+ 801c100:	f423 537c 	bic.w	r3, r3, #16128	; 0x3f00
+ 801c104:	b21c      	sxth	r4, r3
+ 801c106:	6bbb      	ldr	r3, [r7, #56]	; 0x38
+ 801c108:	681b      	ldr	r3, [r3, #0]
+ 801c10a:	691b      	ldr	r3, [r3, #16]
+ 801c10c:	899b      	ldrh	r3, [r3, #12]
+ 801c10e:	b29b      	uxth	r3, r3
+ 801c110:	4618      	mov	r0, r3
+ 801c112:	f7f9 ff15 	bl	8015f40 <lwip_htons>
+ 801c116:	4603      	mov	r3, r0
+ 801c118:	b2db      	uxtb	r3, r3
+ 801c11a:	b29b      	uxth	r3, r3
+ 801c11c:	f003 033e 	and.w	r3, r3, #62	; 0x3e
+ 801c120:	b29b      	uxth	r3, r3
+ 801c122:	4618      	mov	r0, r3
+ 801c124:	f7f9 ff0c 	bl	8015f40 <lwip_htons>
+ 801c128:	4603      	mov	r3, r0
+ 801c12a:	b21b      	sxth	r3, r3
+ 801c12c:	4323      	orrs	r3, r4
+ 801c12e:	b21a      	sxth	r2, r3
+ 801c130:	6bbb      	ldr	r3, [r7, #56]	; 0x38
+ 801c132:	681b      	ldr	r3, [r3, #0]
+ 801c134:	691b      	ldr	r3, [r3, #16]
+ 801c136:	b292      	uxth	r2, r2
+ 801c138:	819a      	strh	r2, [r3, #12]
+                    }
+                    /* Adjust length of segment to fit in the window. */
+                    next->next->len = (u16_t)(pcb->rcv_nxt + pcb->rcv_wnd - seqno);
+ 801c13a:	687b      	ldr	r3, [r7, #4]
+ 801c13c:	6a5b      	ldr	r3, [r3, #36]	; 0x24
+ 801c13e:	b29a      	uxth	r2, r3
+ 801c140:	687b      	ldr	r3, [r7, #4]
+ 801c142:	8d1b      	ldrh	r3, [r3, #40]	; 0x28
+ 801c144:	4413      	add	r3, r2
+ 801c146:	b299      	uxth	r1, r3
+ 801c148:	4b3c      	ldr	r3, [pc, #240]	; (801c23c <tcp_receive+0xf18>)
+ 801c14a:	681b      	ldr	r3, [r3, #0]
+ 801c14c:	b29a      	uxth	r2, r3
+ 801c14e:	6bbb      	ldr	r3, [r7, #56]	; 0x38
+ 801c150:	681b      	ldr	r3, [r3, #0]
+ 801c152:	1a8a      	subs	r2, r1, r2
+ 801c154:	b292      	uxth	r2, r2
+ 801c156:	811a      	strh	r2, [r3, #8]
+                    pbuf_realloc(next->next->p, next->next->len);
+ 801c158:	6bbb      	ldr	r3, [r7, #56]	; 0x38
+ 801c15a:	681b      	ldr	r3, [r3, #0]
+ 801c15c:	685a      	ldr	r2, [r3, #4]
+ 801c15e:	6bbb      	ldr	r3, [r7, #56]	; 0x38
+ 801c160:	681b      	ldr	r3, [r3, #0]
+ 801c162:	891b      	ldrh	r3, [r3, #8]
+ 801c164:	4619      	mov	r1, r3
+ 801c166:	4610      	mov	r0, r2
+ 801c168:	f7fb fb40 	bl	80177ec <pbuf_realloc>
+                    tcplen = TCP_TCPLEN(next->next);
+ 801c16c:	6bbb      	ldr	r3, [r7, #56]	; 0x38
+ 801c16e:	681b      	ldr	r3, [r3, #0]
+ 801c170:	891c      	ldrh	r4, [r3, #8]
+ 801c172:	6bbb      	ldr	r3, [r7, #56]	; 0x38
+ 801c174:	681b      	ldr	r3, [r3, #0]
+ 801c176:	691b      	ldr	r3, [r3, #16]
+ 801c178:	899b      	ldrh	r3, [r3, #12]
+ 801c17a:	b29b      	uxth	r3, r3
+ 801c17c:	4618      	mov	r0, r3
+ 801c17e:	f7f9 fedf 	bl	8015f40 <lwip_htons>
+ 801c182:	4603      	mov	r3, r0
+ 801c184:	b2db      	uxtb	r3, r3
+ 801c186:	f003 0303 	and.w	r3, r3, #3
+ 801c18a:	2b00      	cmp	r3, #0
+ 801c18c:	d001      	beq.n	801c192 <tcp_receive+0xe6e>
+ 801c18e:	2301      	movs	r3, #1
+ 801c190:	e000      	b.n	801c194 <tcp_receive+0xe70>
+ 801c192:	2300      	movs	r3, #0
+ 801c194:	4423      	add	r3, r4
+ 801c196:	b29a      	uxth	r2, r3
+ 801c198:	4b2a      	ldr	r3, [pc, #168]	; (801c244 <tcp_receive+0xf20>)
+ 801c19a:	801a      	strh	r2, [r3, #0]
+                    LWIP_ASSERT("tcp_receive: segment not trimmed correctly to rcv_wnd\n",
+ 801c19c:	4b29      	ldr	r3, [pc, #164]	; (801c244 <tcp_receive+0xf20>)
+ 801c19e:	881b      	ldrh	r3, [r3, #0]
+ 801c1a0:	461a      	mov	r2, r3
+ 801c1a2:	4b26      	ldr	r3, [pc, #152]	; (801c23c <tcp_receive+0xf18>)
+ 801c1a4:	681b      	ldr	r3, [r3, #0]
+ 801c1a6:	441a      	add	r2, r3
+ 801c1a8:	687b      	ldr	r3, [r7, #4]
+ 801c1aa:	6a5b      	ldr	r3, [r3, #36]	; 0x24
+ 801c1ac:	6879      	ldr	r1, [r7, #4]
+ 801c1ae:	8d09      	ldrh	r1, [r1, #40]	; 0x28
+ 801c1b0:	440b      	add	r3, r1
+ 801c1b2:	429a      	cmp	r2, r3
+ 801c1b4:	d019      	beq.n	801c1ea <tcp_receive+0xec6>
+ 801c1b6:	4b24      	ldr	r3, [pc, #144]	; (801c248 <tcp_receive+0xf24>)
+ 801c1b8:	f44f 62df 	mov.w	r2, #1784	; 0x6f8
+ 801c1bc:	4923      	ldr	r1, [pc, #140]	; (801c24c <tcp_receive+0xf28>)
+ 801c1be:	4824      	ldr	r0, [pc, #144]	; (801c250 <tcp_receive+0xf2c>)
+ 801c1c0:	f005 fbe2 	bl	8021988 <iprintf>
+                                (seqno + tcplen) == (pcb->rcv_nxt + pcb->rcv_wnd));
+                  }
+                }
+                break;
+ 801c1c4:	e011      	b.n	801c1ea <tcp_receive+0xec6>
+          for (next = pcb->ooseq; next != NULL; next = next->next) {
+ 801c1c6:	6bbb      	ldr	r3, [r7, #56]	; 0x38
+ 801c1c8:	681b      	ldr	r3, [r3, #0]
+ 801c1ca:	63bb      	str	r3, [r7, #56]	; 0x38
+ 801c1cc:	6bbb      	ldr	r3, [r7, #56]	; 0x38
+ 801c1ce:	2b00      	cmp	r3, #0
+ 801c1d0:	f47f aea4 	bne.w	801bf1c <tcp_receive+0xbf8>
+ 801c1d4:	e00a      	b.n	801c1ec <tcp_receive+0xec8>
+                break;
+ 801c1d6:	bf00      	nop
+ 801c1d8:	e008      	b.n	801c1ec <tcp_receive+0xec8>
+                break;
+ 801c1da:	bf00      	nop
+ 801c1dc:	e006      	b.n	801c1ec <tcp_receive+0xec8>
+                  break;
+ 801c1de:	bf00      	nop
+ 801c1e0:	e004      	b.n	801c1ec <tcp_receive+0xec8>
+                  break;
+ 801c1e2:	bf00      	nop
+ 801c1e4:	e002      	b.n	801c1ec <tcp_receive+0xec8>
+                  break;
+ 801c1e6:	bf00      	nop
+ 801c1e8:	e000      	b.n	801c1ec <tcp_receive+0xec8>
+                break;
+ 801c1ea:	bf00      	nop
+#endif /* TCP_OOSEQ_BYTES_LIMIT || TCP_OOSEQ_PBUFS_LIMIT */
+#endif /* TCP_QUEUE_OOSEQ */
+
+        /* We send the ACK packet after we've (potentially) dealt with SACKs,
+           so they can be included in the acknowledgment. */
+        tcp_send_empty_ack(pcb);
+ 801c1ec:	6878      	ldr	r0, [r7, #4]
+ 801c1ee:	f001 fef7 	bl	801dfe0 <tcp_send_empty_ack>
+      if (pcb->rcv_nxt == seqno) {
+ 801c1f2:	e003      	b.n	801c1fc <tcp_receive+0xed8>
+      }
+    } else {
+      /* The incoming segment is not within the window. */
+      tcp_send_empty_ack(pcb);
+ 801c1f4:	6878      	ldr	r0, [r7, #4]
+ 801c1f6:	f001 fef3 	bl	801dfe0 <tcp_send_empty_ack>
+    if (TCP_SEQ_BETWEEN(seqno, pcb->rcv_nxt,
+ 801c1fa:	e01a      	b.n	801c232 <tcp_receive+0xf0e>
+ 801c1fc:	e019      	b.n	801c232 <tcp_receive+0xf0e>
+    }
+  } else {
+    /* Segments with length 0 is taken care of here. Segments that
+       fall out of the window are ACKed. */
+    if (!TCP_SEQ_BETWEEN(seqno, pcb->rcv_nxt, pcb->rcv_nxt + pcb->rcv_wnd - 1)) {
+ 801c1fe:	4b0f      	ldr	r3, [pc, #60]	; (801c23c <tcp_receive+0xf18>)
+ 801c200:	681a      	ldr	r2, [r3, #0]
+ 801c202:	687b      	ldr	r3, [r7, #4]
+ 801c204:	6a5b      	ldr	r3, [r3, #36]	; 0x24
+ 801c206:	1ad3      	subs	r3, r2, r3
+ 801c208:	2b00      	cmp	r3, #0
+ 801c20a:	db0a      	blt.n	801c222 <tcp_receive+0xefe>
+ 801c20c:	4b0b      	ldr	r3, [pc, #44]	; (801c23c <tcp_receive+0xf18>)
+ 801c20e:	681a      	ldr	r2, [r3, #0]
+ 801c210:	687b      	ldr	r3, [r7, #4]
+ 801c212:	6a5b      	ldr	r3, [r3, #36]	; 0x24
+ 801c214:	6879      	ldr	r1, [r7, #4]
+ 801c216:	8d09      	ldrh	r1, [r1, #40]	; 0x28
+ 801c218:	440b      	add	r3, r1
+ 801c21a:	1ad3      	subs	r3, r2, r3
+ 801c21c:	3301      	adds	r3, #1
+ 801c21e:	2b00      	cmp	r3, #0
+ 801c220:	dd07      	ble.n	801c232 <tcp_receive+0xf0e>
+      tcp_ack_now(pcb);
+ 801c222:	687b      	ldr	r3, [r7, #4]
+ 801c224:	8b5b      	ldrh	r3, [r3, #26]
+ 801c226:	f043 0302 	orr.w	r3, r3, #2
+ 801c22a:	b29a      	uxth	r2, r3
+ 801c22c:	687b      	ldr	r3, [r7, #4]
+ 801c22e:	835a      	strh	r2, [r3, #26]
+    }
+  }
+}
+ 801c230:	e7ff      	b.n	801c232 <tcp_receive+0xf0e>
+ 801c232:	bf00      	nop
+ 801c234:	3750      	adds	r7, #80	; 0x50
+ 801c236:	46bd      	mov	sp, r7
+ 801c238:	bdb0      	pop	{r4, r5, r7, pc}
+ 801c23a:	bf00      	nop
+ 801c23c:	2401a4bc 	.word	0x2401a4bc
+ 801c240:	2401a498 	.word	0x2401a498
+ 801c244:	2401a4c6 	.word	0x2401a4c6
+ 801c248:	08025338 	.word	0x08025338
+ 801c24c:	080256e0 	.word	0x080256e0
+ 801c250:	08025384 	.word	0x08025384
+
+0801c254 <tcp_get_next_optbyte>:
+
+static u8_t
+tcp_get_next_optbyte(void)
+{
+ 801c254:	b480      	push	{r7}
+ 801c256:	b083      	sub	sp, #12
+ 801c258:	af00      	add	r7, sp, #0
+  u16_t optidx = tcp_optidx++;
+ 801c25a:	4b15      	ldr	r3, [pc, #84]	; (801c2b0 <tcp_get_next_optbyte+0x5c>)
+ 801c25c:	881b      	ldrh	r3, [r3, #0]
+ 801c25e:	1c5a      	adds	r2, r3, #1
+ 801c260:	b291      	uxth	r1, r2
+ 801c262:	4a13      	ldr	r2, [pc, #76]	; (801c2b0 <tcp_get_next_optbyte+0x5c>)
+ 801c264:	8011      	strh	r1, [r2, #0]
+ 801c266:	80fb      	strh	r3, [r7, #6]
+  if ((tcphdr_opt2 == NULL) || (optidx < tcphdr_opt1len)) {
+ 801c268:	4b12      	ldr	r3, [pc, #72]	; (801c2b4 <tcp_get_next_optbyte+0x60>)
+ 801c26a:	681b      	ldr	r3, [r3, #0]
+ 801c26c:	2b00      	cmp	r3, #0
+ 801c26e:	d004      	beq.n	801c27a <tcp_get_next_optbyte+0x26>
+ 801c270:	4b11      	ldr	r3, [pc, #68]	; (801c2b8 <tcp_get_next_optbyte+0x64>)
+ 801c272:	881b      	ldrh	r3, [r3, #0]
+ 801c274:	88fa      	ldrh	r2, [r7, #6]
+ 801c276:	429a      	cmp	r2, r3
+ 801c278:	d208      	bcs.n	801c28c <tcp_get_next_optbyte+0x38>
+    u8_t *opts = (u8_t *)tcphdr + TCP_HLEN;
+ 801c27a:	4b10      	ldr	r3, [pc, #64]	; (801c2bc <tcp_get_next_optbyte+0x68>)
+ 801c27c:	681b      	ldr	r3, [r3, #0]
+ 801c27e:	3314      	adds	r3, #20
+ 801c280:	603b      	str	r3, [r7, #0]
+    return opts[optidx];
+ 801c282:	88fb      	ldrh	r3, [r7, #6]
+ 801c284:	683a      	ldr	r2, [r7, #0]
+ 801c286:	4413      	add	r3, r2
+ 801c288:	781b      	ldrb	r3, [r3, #0]
+ 801c28a:	e00b      	b.n	801c2a4 <tcp_get_next_optbyte+0x50>
+  } else {
+    u8_t idx = (u8_t)(optidx - tcphdr_opt1len);
+ 801c28c:	88fb      	ldrh	r3, [r7, #6]
+ 801c28e:	b2da      	uxtb	r2, r3
+ 801c290:	4b09      	ldr	r3, [pc, #36]	; (801c2b8 <tcp_get_next_optbyte+0x64>)
+ 801c292:	881b      	ldrh	r3, [r3, #0]
+ 801c294:	b2db      	uxtb	r3, r3
+ 801c296:	1ad3      	subs	r3, r2, r3
+ 801c298:	717b      	strb	r3, [r7, #5]
+    return tcphdr_opt2[idx];
+ 801c29a:	4b06      	ldr	r3, [pc, #24]	; (801c2b4 <tcp_get_next_optbyte+0x60>)
+ 801c29c:	681a      	ldr	r2, [r3, #0]
+ 801c29e:	797b      	ldrb	r3, [r7, #5]
+ 801c2a0:	4413      	add	r3, r2
+ 801c2a2:	781b      	ldrb	r3, [r3, #0]
+  }
+}
+ 801c2a4:	4618      	mov	r0, r3
+ 801c2a6:	370c      	adds	r7, #12
+ 801c2a8:	46bd      	mov	sp, r7
+ 801c2aa:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 801c2ae:	4770      	bx	lr
+ 801c2b0:	2401a4b8 	.word	0x2401a4b8
+ 801c2b4:	2401a4b4 	.word	0x2401a4b4
+ 801c2b8:	2401a4b2 	.word	0x2401a4b2
+ 801c2bc:	2401a4ac 	.word	0x2401a4ac
+
+0801c2c0 <tcp_parseopt>:
+ *
+ * @param pcb the tcp_pcb for which a segment arrived
+ */
+static void
+tcp_parseopt(struct tcp_pcb *pcb)
+{
+ 801c2c0:	b580      	push	{r7, lr}
+ 801c2c2:	b084      	sub	sp, #16
+ 801c2c4:	af00      	add	r7, sp, #0
+ 801c2c6:	6078      	str	r0, [r7, #4]
+  u16_t mss;
+#if LWIP_TCP_TIMESTAMPS
+  u32_t tsval;
+#endif
+
+  LWIP_ASSERT("tcp_parseopt: invalid pcb", pcb != NULL);
+ 801c2c8:	687b      	ldr	r3, [r7, #4]
+ 801c2ca:	2b00      	cmp	r3, #0
+ 801c2cc:	d106      	bne.n	801c2dc <tcp_parseopt+0x1c>
+ 801c2ce:	4b32      	ldr	r3, [pc, #200]	; (801c398 <tcp_parseopt+0xd8>)
+ 801c2d0:	f240 727d 	movw	r2, #1917	; 0x77d
+ 801c2d4:	4931      	ldr	r1, [pc, #196]	; (801c39c <tcp_parseopt+0xdc>)
+ 801c2d6:	4832      	ldr	r0, [pc, #200]	; (801c3a0 <tcp_parseopt+0xe0>)
+ 801c2d8:	f005 fb56 	bl	8021988 <iprintf>
+
+  /* Parse the TCP MSS option, if present. */
+  if (tcphdr_optlen != 0) {
+ 801c2dc:	4b31      	ldr	r3, [pc, #196]	; (801c3a4 <tcp_parseopt+0xe4>)
+ 801c2de:	881b      	ldrh	r3, [r3, #0]
+ 801c2e0:	2b00      	cmp	r3, #0
+ 801c2e2:	d056      	beq.n	801c392 <tcp_parseopt+0xd2>
+    for (tcp_optidx = 0; tcp_optidx < tcphdr_optlen; ) {
+ 801c2e4:	4b30      	ldr	r3, [pc, #192]	; (801c3a8 <tcp_parseopt+0xe8>)
+ 801c2e6:	2200      	movs	r2, #0
+ 801c2e8:	801a      	strh	r2, [r3, #0]
+ 801c2ea:	e046      	b.n	801c37a <tcp_parseopt+0xba>
+      u8_t opt = tcp_get_next_optbyte();
+ 801c2ec:	f7ff ffb2 	bl	801c254 <tcp_get_next_optbyte>
+ 801c2f0:	4603      	mov	r3, r0
+ 801c2f2:	73fb      	strb	r3, [r7, #15]
+      switch (opt) {
+ 801c2f4:	7bfb      	ldrb	r3, [r7, #15]
+ 801c2f6:	2b02      	cmp	r3, #2
+ 801c2f8:	d006      	beq.n	801c308 <tcp_parseopt+0x48>
+ 801c2fa:	2b02      	cmp	r3, #2
+ 801c2fc:	dc2c      	bgt.n	801c358 <tcp_parseopt+0x98>
+ 801c2fe:	2b00      	cmp	r3, #0
+ 801c300:	d042      	beq.n	801c388 <tcp_parseopt+0xc8>
+ 801c302:	2b01      	cmp	r3, #1
+ 801c304:	d128      	bne.n	801c358 <tcp_parseopt+0x98>
+          LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_parseopt: EOL\n"));
+          return;
+        case LWIP_TCP_OPT_NOP:
+          /* NOP option. */
+          LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_parseopt: NOP\n"));
+          break;
+ 801c306:	e038      	b.n	801c37a <tcp_parseopt+0xba>
+        case LWIP_TCP_OPT_MSS:
+          LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_parseopt: MSS\n"));
+          if (tcp_get_next_optbyte() != LWIP_TCP_OPT_LEN_MSS || (tcp_optidx - 2 + LWIP_TCP_OPT_LEN_MSS) > tcphdr_optlen) {
+ 801c308:	f7ff ffa4 	bl	801c254 <tcp_get_next_optbyte>
+ 801c30c:	4603      	mov	r3, r0
+ 801c30e:	2b04      	cmp	r3, #4
+ 801c310:	d13c      	bne.n	801c38c <tcp_parseopt+0xcc>
+ 801c312:	4b25      	ldr	r3, [pc, #148]	; (801c3a8 <tcp_parseopt+0xe8>)
+ 801c314:	881b      	ldrh	r3, [r3, #0]
+ 801c316:	3301      	adds	r3, #1
+ 801c318:	4a22      	ldr	r2, [pc, #136]	; (801c3a4 <tcp_parseopt+0xe4>)
+ 801c31a:	8812      	ldrh	r2, [r2, #0]
+ 801c31c:	4293      	cmp	r3, r2
+ 801c31e:	da35      	bge.n	801c38c <tcp_parseopt+0xcc>
+            /* Bad length */
+            LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_parseopt: bad length\n"));
+            return;
+          }
+          /* An MSS option with the right option length. */
+          mss = (u16_t)(tcp_get_next_optbyte() << 8);
+ 801c320:	f7ff ff98 	bl	801c254 <tcp_get_next_optbyte>
+ 801c324:	4603      	mov	r3, r0
+ 801c326:	b29b      	uxth	r3, r3
+ 801c328:	021b      	lsls	r3, r3, #8
+ 801c32a:	81bb      	strh	r3, [r7, #12]
+          mss |= tcp_get_next_optbyte();
+ 801c32c:	f7ff ff92 	bl	801c254 <tcp_get_next_optbyte>
+ 801c330:	4603      	mov	r3, r0
+ 801c332:	b29a      	uxth	r2, r3
+ 801c334:	89bb      	ldrh	r3, [r7, #12]
+ 801c336:	4313      	orrs	r3, r2
+ 801c338:	81bb      	strh	r3, [r7, #12]
+          /* Limit the mss to the configured TCP_MSS and prevent division by zero */
+          pcb->mss = ((mss > TCP_MSS) || (mss == 0)) ? TCP_MSS : mss;
+ 801c33a:	89bb      	ldrh	r3, [r7, #12]
+ 801c33c:	f240 52b4 	movw	r2, #1460	; 0x5b4
+ 801c340:	4293      	cmp	r3, r2
+ 801c342:	d804      	bhi.n	801c34e <tcp_parseopt+0x8e>
+ 801c344:	89bb      	ldrh	r3, [r7, #12]
+ 801c346:	2b00      	cmp	r3, #0
+ 801c348:	d001      	beq.n	801c34e <tcp_parseopt+0x8e>
+ 801c34a:	89ba      	ldrh	r2, [r7, #12]
+ 801c34c:	e001      	b.n	801c352 <tcp_parseopt+0x92>
+ 801c34e:	f240 52b4 	movw	r2, #1460	; 0x5b4
+ 801c352:	687b      	ldr	r3, [r7, #4]
+ 801c354:	865a      	strh	r2, [r3, #50]	; 0x32
+          break;
+ 801c356:	e010      	b.n	801c37a <tcp_parseopt+0xba>
+          }
+          break;
+#endif /* LWIP_TCP_SACK_OUT */
+        default:
+          LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_parseopt: other\n"));
+          data = tcp_get_next_optbyte();
+ 801c358:	f7ff ff7c 	bl	801c254 <tcp_get_next_optbyte>
+ 801c35c:	4603      	mov	r3, r0
+ 801c35e:	72fb      	strb	r3, [r7, #11]
+          if (data < 2) {
+ 801c360:	7afb      	ldrb	r3, [r7, #11]
+ 801c362:	2b01      	cmp	r3, #1
+ 801c364:	d914      	bls.n	801c390 <tcp_parseopt+0xd0>
+               and we don't process them further. */
+            return;
+          }
+          /* All other options have a length field, so that we easily
+             can skip past them. */
+          tcp_optidx += data - 2;
+ 801c366:	7afb      	ldrb	r3, [r7, #11]
+ 801c368:	b29a      	uxth	r2, r3
+ 801c36a:	4b0f      	ldr	r3, [pc, #60]	; (801c3a8 <tcp_parseopt+0xe8>)
+ 801c36c:	881b      	ldrh	r3, [r3, #0]
+ 801c36e:	4413      	add	r3, r2
+ 801c370:	b29b      	uxth	r3, r3
+ 801c372:	3b02      	subs	r3, #2
+ 801c374:	b29a      	uxth	r2, r3
+ 801c376:	4b0c      	ldr	r3, [pc, #48]	; (801c3a8 <tcp_parseopt+0xe8>)
+ 801c378:	801a      	strh	r2, [r3, #0]
+    for (tcp_optidx = 0; tcp_optidx < tcphdr_optlen; ) {
+ 801c37a:	4b0b      	ldr	r3, [pc, #44]	; (801c3a8 <tcp_parseopt+0xe8>)
+ 801c37c:	881a      	ldrh	r2, [r3, #0]
+ 801c37e:	4b09      	ldr	r3, [pc, #36]	; (801c3a4 <tcp_parseopt+0xe4>)
+ 801c380:	881b      	ldrh	r3, [r3, #0]
+ 801c382:	429a      	cmp	r2, r3
+ 801c384:	d3b2      	bcc.n	801c2ec <tcp_parseopt+0x2c>
+ 801c386:	e004      	b.n	801c392 <tcp_parseopt+0xd2>
+          return;
+ 801c388:	bf00      	nop
+ 801c38a:	e002      	b.n	801c392 <tcp_parseopt+0xd2>
+            return;
+ 801c38c:	bf00      	nop
+ 801c38e:	e000      	b.n	801c392 <tcp_parseopt+0xd2>
+            return;
+ 801c390:	bf00      	nop
+      }
+    }
+  }
+}
+ 801c392:	3710      	adds	r7, #16
+ 801c394:	46bd      	mov	sp, r7
+ 801c396:	bd80      	pop	{r7, pc}
+ 801c398:	08025338 	.word	0x08025338
+ 801c39c:	0802579c 	.word	0x0802579c
+ 801c3a0:	08025384 	.word	0x08025384
+ 801c3a4:	2401a4b0 	.word	0x2401a4b0
+ 801c3a8:	2401a4b8 	.word	0x2401a4b8
+
+0801c3ac <tcp_trigger_input_pcb_close>:
+
+void
+tcp_trigger_input_pcb_close(void)
+{
+ 801c3ac:	b480      	push	{r7}
+ 801c3ae:	af00      	add	r7, sp, #0
+  recv_flags |= TF_CLOSED;
+ 801c3b0:	4b05      	ldr	r3, [pc, #20]	; (801c3c8 <tcp_trigger_input_pcb_close+0x1c>)
+ 801c3b2:	781b      	ldrb	r3, [r3, #0]
+ 801c3b4:	f043 0310 	orr.w	r3, r3, #16
+ 801c3b8:	b2da      	uxtb	r2, r3
+ 801c3ba:	4b03      	ldr	r3, [pc, #12]	; (801c3c8 <tcp_trigger_input_pcb_close+0x1c>)
+ 801c3bc:	701a      	strb	r2, [r3, #0]
+}
+ 801c3be:	bf00      	nop
+ 801c3c0:	46bd      	mov	sp, r7
+ 801c3c2:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 801c3c6:	4770      	bx	lr
+ 801c3c8:	2401a4c9 	.word	0x2401a4c9
+
+0801c3cc <tcp_route>:
+static err_t tcp_output_segment(struct tcp_seg *seg, struct tcp_pcb *pcb, struct netif *netif);
+
+/* tcp_route: common code that returns a fixed bound netif or calls ip_route */
+static struct netif *
+tcp_route(const struct tcp_pcb *pcb, const ip_addr_t *src, const ip_addr_t *dst)
+{
+ 801c3cc:	b580      	push	{r7, lr}
+ 801c3ce:	b084      	sub	sp, #16
+ 801c3d0:	af00      	add	r7, sp, #0
+ 801c3d2:	60f8      	str	r0, [r7, #12]
+ 801c3d4:	60b9      	str	r1, [r7, #8]
+ 801c3d6:	607a      	str	r2, [r7, #4]
+  LWIP_UNUSED_ARG(src); /* in case IPv4-only and source-based routing is disabled */
+
+  if ((pcb != NULL) && (pcb->netif_idx != NETIF_NO_INDEX)) {
+ 801c3d8:	68fb      	ldr	r3, [r7, #12]
+ 801c3da:	2b00      	cmp	r3, #0
+ 801c3dc:	d00a      	beq.n	801c3f4 <tcp_route+0x28>
+ 801c3de:	68fb      	ldr	r3, [r7, #12]
+ 801c3e0:	7a1b      	ldrb	r3, [r3, #8]
+ 801c3e2:	2b00      	cmp	r3, #0
+ 801c3e4:	d006      	beq.n	801c3f4 <tcp_route+0x28>
+    return netif_get_by_index(pcb->netif_idx);
+ 801c3e6:	68fb      	ldr	r3, [r7, #12]
+ 801c3e8:	7a1b      	ldrb	r3, [r3, #8]
+ 801c3ea:	4618      	mov	r0, r3
+ 801c3ec:	f7fa fff2 	bl	80173d4 <netif_get_by_index>
+ 801c3f0:	4603      	mov	r3, r0
+ 801c3f2:	e003      	b.n	801c3fc <tcp_route+0x30>
+  } else {
+    return ip_route(src, dst);
+ 801c3f4:	6878      	ldr	r0, [r7, #4]
+ 801c3f6:	f003 fd7d 	bl	801fef4 <ip4_route>
+ 801c3fa:	4603      	mov	r3, r0
+  }
+}
+ 801c3fc:	4618      	mov	r0, r3
+ 801c3fe:	3710      	adds	r7, #16
+ 801c400:	46bd      	mov	sp, r7
+ 801c402:	bd80      	pop	{r7, pc}
+
+0801c404 <tcp_create_segment>:
+ * The TCP header is filled in except ackno and wnd.
+ * p is freed on failure.
+ */
+static struct tcp_seg *
+tcp_create_segment(const struct tcp_pcb *pcb, struct pbuf *p, u8_t hdrflags, u32_t seqno, u8_t optflags)
+{
+ 801c404:	b590      	push	{r4, r7, lr}
+ 801c406:	b087      	sub	sp, #28
+ 801c408:	af00      	add	r7, sp, #0
+ 801c40a:	60f8      	str	r0, [r7, #12]
+ 801c40c:	60b9      	str	r1, [r7, #8]
+ 801c40e:	603b      	str	r3, [r7, #0]
+ 801c410:	4613      	mov	r3, r2
+ 801c412:	71fb      	strb	r3, [r7, #7]
+  struct tcp_seg *seg;
+  u8_t optlen;
+
+  LWIP_ASSERT("tcp_create_segment: invalid pcb", pcb != NULL);
+ 801c414:	68fb      	ldr	r3, [r7, #12]
+ 801c416:	2b00      	cmp	r3, #0
+ 801c418:	d105      	bne.n	801c426 <tcp_create_segment+0x22>
+ 801c41a:	4b45      	ldr	r3, [pc, #276]	; (801c530 <tcp_create_segment+0x12c>)
+ 801c41c:	22a3      	movs	r2, #163	; 0xa3
+ 801c41e:	4945      	ldr	r1, [pc, #276]	; (801c534 <tcp_create_segment+0x130>)
+ 801c420:	4845      	ldr	r0, [pc, #276]	; (801c538 <tcp_create_segment+0x134>)
+ 801c422:	f005 fab1 	bl	8021988 <iprintf>
+  LWIP_ASSERT("tcp_create_segment: invalid pbuf", p != NULL);
+ 801c426:	68bb      	ldr	r3, [r7, #8]
+ 801c428:	2b00      	cmp	r3, #0
+ 801c42a:	d105      	bne.n	801c438 <tcp_create_segment+0x34>
+ 801c42c:	4b40      	ldr	r3, [pc, #256]	; (801c530 <tcp_create_segment+0x12c>)
+ 801c42e:	22a4      	movs	r2, #164	; 0xa4
+ 801c430:	4942      	ldr	r1, [pc, #264]	; (801c53c <tcp_create_segment+0x138>)
+ 801c432:	4841      	ldr	r0, [pc, #260]	; (801c538 <tcp_create_segment+0x134>)
+ 801c434:	f005 faa8 	bl	8021988 <iprintf>
+
+  optlen = LWIP_TCP_OPT_LENGTH_SEGMENT(optflags, pcb);
+ 801c438:	f897 3028 	ldrb.w	r3, [r7, #40]	; 0x28
+ 801c43c:	009b      	lsls	r3, r3, #2
+ 801c43e:	b2db      	uxtb	r3, r3
+ 801c440:	f003 0304 	and.w	r3, r3, #4
+ 801c444:	75fb      	strb	r3, [r7, #23]
+
+  if ((seg = (struct tcp_seg *)memp_malloc(MEMP_TCP_SEG)) == NULL) {
+ 801c446:	2003      	movs	r0, #3
+ 801c448:	f7fa fb42 	bl	8016ad0 <memp_malloc>
+ 801c44c:	6138      	str	r0, [r7, #16]
+ 801c44e:	693b      	ldr	r3, [r7, #16]
+ 801c450:	2b00      	cmp	r3, #0
+ 801c452:	d104      	bne.n	801c45e <tcp_create_segment+0x5a>
+    LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("tcp_create_segment: no memory.\n"));
+    pbuf_free(p);
+ 801c454:	68b8      	ldr	r0, [r7, #8]
+ 801c456:	f7fb fb4f 	bl	8017af8 <pbuf_free>
+    return NULL;
+ 801c45a:	2300      	movs	r3, #0
+ 801c45c:	e064      	b.n	801c528 <tcp_create_segment+0x124>
+  }
+  seg->flags = optflags;
+ 801c45e:	693b      	ldr	r3, [r7, #16]
+ 801c460:	f897 2028 	ldrb.w	r2, [r7, #40]	; 0x28
+ 801c464:	731a      	strb	r2, [r3, #12]
+  seg->next = NULL;
+ 801c466:	693b      	ldr	r3, [r7, #16]
+ 801c468:	2200      	movs	r2, #0
+ 801c46a:	601a      	str	r2, [r3, #0]
+  seg->p = p;
+ 801c46c:	693b      	ldr	r3, [r7, #16]
+ 801c46e:	68ba      	ldr	r2, [r7, #8]
+ 801c470:	605a      	str	r2, [r3, #4]
+  LWIP_ASSERT("p->tot_len >= optlen", p->tot_len >= optlen);
+ 801c472:	68bb      	ldr	r3, [r7, #8]
+ 801c474:	891a      	ldrh	r2, [r3, #8]
+ 801c476:	7dfb      	ldrb	r3, [r7, #23]
+ 801c478:	b29b      	uxth	r3, r3
+ 801c47a:	429a      	cmp	r2, r3
+ 801c47c:	d205      	bcs.n	801c48a <tcp_create_segment+0x86>
+ 801c47e:	4b2c      	ldr	r3, [pc, #176]	; (801c530 <tcp_create_segment+0x12c>)
+ 801c480:	22b0      	movs	r2, #176	; 0xb0
+ 801c482:	492f      	ldr	r1, [pc, #188]	; (801c540 <tcp_create_segment+0x13c>)
+ 801c484:	482c      	ldr	r0, [pc, #176]	; (801c538 <tcp_create_segment+0x134>)
+ 801c486:	f005 fa7f 	bl	8021988 <iprintf>
+  seg->len = p->tot_len - optlen;
+ 801c48a:	68bb      	ldr	r3, [r7, #8]
+ 801c48c:	891a      	ldrh	r2, [r3, #8]
+ 801c48e:	7dfb      	ldrb	r3, [r7, #23]
+ 801c490:	b29b      	uxth	r3, r3
+ 801c492:	1ad3      	subs	r3, r2, r3
+ 801c494:	b29a      	uxth	r2, r3
+ 801c496:	693b      	ldr	r3, [r7, #16]
+ 801c498:	811a      	strh	r2, [r3, #8]
+#if TCP_OVERSIZE_DBGCHECK
+  seg->oversize_left = 0;
+ 801c49a:	693b      	ldr	r3, [r7, #16]
+ 801c49c:	2200      	movs	r2, #0
+ 801c49e:	815a      	strh	r2, [r3, #10]
+  LWIP_ASSERT("invalid optflags passed: TF_SEG_DATA_CHECKSUMMED",
+              (optflags & TF_SEG_DATA_CHECKSUMMED) == 0);
+#endif /* TCP_CHECKSUM_ON_COPY */
+
+  /* build TCP header */
+  if (pbuf_add_header(p, TCP_HLEN)) {
+ 801c4a0:	2114      	movs	r1, #20
+ 801c4a2:	68b8      	ldr	r0, [r7, #8]
+ 801c4a4:	f7fb fa92 	bl	80179cc <pbuf_add_header>
+ 801c4a8:	4603      	mov	r3, r0
+ 801c4aa:	2b00      	cmp	r3, #0
+ 801c4ac:	d004      	beq.n	801c4b8 <tcp_create_segment+0xb4>
+    LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("tcp_create_segment: no room for TCP header in pbuf.\n"));
+    TCP_STATS_INC(tcp.err);
+    tcp_seg_free(seg);
+ 801c4ae:	6938      	ldr	r0, [r7, #16]
+ 801c4b0:	f7fc fff7 	bl	80194a2 <tcp_seg_free>
+    return NULL;
+ 801c4b4:	2300      	movs	r3, #0
+ 801c4b6:	e037      	b.n	801c528 <tcp_create_segment+0x124>
+  }
+  seg->tcphdr = (struct tcp_hdr *)seg->p->payload;
+ 801c4b8:	693b      	ldr	r3, [r7, #16]
+ 801c4ba:	685b      	ldr	r3, [r3, #4]
+ 801c4bc:	685a      	ldr	r2, [r3, #4]
+ 801c4be:	693b      	ldr	r3, [r7, #16]
+ 801c4c0:	611a      	str	r2, [r3, #16]
+  seg->tcphdr->src = lwip_htons(pcb->local_port);
+ 801c4c2:	68fb      	ldr	r3, [r7, #12]
+ 801c4c4:	8ada      	ldrh	r2, [r3, #22]
+ 801c4c6:	693b      	ldr	r3, [r7, #16]
+ 801c4c8:	691c      	ldr	r4, [r3, #16]
+ 801c4ca:	4610      	mov	r0, r2
+ 801c4cc:	f7f9 fd38 	bl	8015f40 <lwip_htons>
+ 801c4d0:	4603      	mov	r3, r0
+ 801c4d2:	8023      	strh	r3, [r4, #0]
+  seg->tcphdr->dest = lwip_htons(pcb->remote_port);
+ 801c4d4:	68fb      	ldr	r3, [r7, #12]
+ 801c4d6:	8b1a      	ldrh	r2, [r3, #24]
+ 801c4d8:	693b      	ldr	r3, [r7, #16]
+ 801c4da:	691c      	ldr	r4, [r3, #16]
+ 801c4dc:	4610      	mov	r0, r2
+ 801c4de:	f7f9 fd2f 	bl	8015f40 <lwip_htons>
+ 801c4e2:	4603      	mov	r3, r0
+ 801c4e4:	8063      	strh	r3, [r4, #2]
+  seg->tcphdr->seqno = lwip_htonl(seqno);
+ 801c4e6:	693b      	ldr	r3, [r7, #16]
+ 801c4e8:	691c      	ldr	r4, [r3, #16]
+ 801c4ea:	6838      	ldr	r0, [r7, #0]
+ 801c4ec:	f7f9 fd3d 	bl	8015f6a <lwip_htonl>
+ 801c4f0:	4603      	mov	r3, r0
+ 801c4f2:	6063      	str	r3, [r4, #4]
+  /* ackno is set in tcp_output */
+  TCPH_HDRLEN_FLAGS_SET(seg->tcphdr, (5 + optlen / 4), hdrflags);
+ 801c4f4:	7dfb      	ldrb	r3, [r7, #23]
+ 801c4f6:	089b      	lsrs	r3, r3, #2
+ 801c4f8:	b2db      	uxtb	r3, r3
+ 801c4fa:	b29b      	uxth	r3, r3
+ 801c4fc:	3305      	adds	r3, #5
+ 801c4fe:	b29b      	uxth	r3, r3
+ 801c500:	031b      	lsls	r3, r3, #12
+ 801c502:	b29a      	uxth	r2, r3
+ 801c504:	79fb      	ldrb	r3, [r7, #7]
+ 801c506:	b29b      	uxth	r3, r3
+ 801c508:	4313      	orrs	r3, r2
+ 801c50a:	b29a      	uxth	r2, r3
+ 801c50c:	693b      	ldr	r3, [r7, #16]
+ 801c50e:	691c      	ldr	r4, [r3, #16]
+ 801c510:	4610      	mov	r0, r2
+ 801c512:	f7f9 fd15 	bl	8015f40 <lwip_htons>
+ 801c516:	4603      	mov	r3, r0
+ 801c518:	81a3      	strh	r3, [r4, #12]
+  /* wnd and chksum are set in tcp_output */
+  seg->tcphdr->urgp = 0;
+ 801c51a:	693b      	ldr	r3, [r7, #16]
+ 801c51c:	691b      	ldr	r3, [r3, #16]
+ 801c51e:	2200      	movs	r2, #0
+ 801c520:	749a      	strb	r2, [r3, #18]
+ 801c522:	2200      	movs	r2, #0
+ 801c524:	74da      	strb	r2, [r3, #19]
+  return seg;
+ 801c526:	693b      	ldr	r3, [r7, #16]
+}
+ 801c528:	4618      	mov	r0, r3
+ 801c52a:	371c      	adds	r7, #28
+ 801c52c:	46bd      	mov	sp, r7
+ 801c52e:	bd90      	pop	{r4, r7, pc}
+ 801c530:	080257b8 	.word	0x080257b8
+ 801c534:	080257ec 	.word	0x080257ec
+ 801c538:	0802580c 	.word	0x0802580c
+ 801c53c:	08025834 	.word	0x08025834
+ 801c540:	08025858 	.word	0x08025858
+
+0801c544 <tcp_pbuf_prealloc>:
+#if TCP_OVERSIZE
+static struct pbuf *
+tcp_pbuf_prealloc(pbuf_layer layer, u16_t length, u16_t max_length,
+                  u16_t *oversize, const struct tcp_pcb *pcb, u8_t apiflags,
+                  u8_t first_seg)
+{
+ 801c544:	b580      	push	{r7, lr}
+ 801c546:	b086      	sub	sp, #24
+ 801c548:	af00      	add	r7, sp, #0
+ 801c54a:	607b      	str	r3, [r7, #4]
+ 801c54c:	4603      	mov	r3, r0
+ 801c54e:	73fb      	strb	r3, [r7, #15]
+ 801c550:	460b      	mov	r3, r1
+ 801c552:	81bb      	strh	r3, [r7, #12]
+ 801c554:	4613      	mov	r3, r2
+ 801c556:	817b      	strh	r3, [r7, #10]
+  struct pbuf *p;
+  u16_t alloc = length;
+ 801c558:	89bb      	ldrh	r3, [r7, #12]
+ 801c55a:	82fb      	strh	r3, [r7, #22]
+
+  LWIP_ASSERT("tcp_pbuf_prealloc: invalid oversize", oversize != NULL);
+ 801c55c:	687b      	ldr	r3, [r7, #4]
+ 801c55e:	2b00      	cmp	r3, #0
+ 801c560:	d105      	bne.n	801c56e <tcp_pbuf_prealloc+0x2a>
+ 801c562:	4b30      	ldr	r3, [pc, #192]	; (801c624 <tcp_pbuf_prealloc+0xe0>)
+ 801c564:	22e8      	movs	r2, #232	; 0xe8
+ 801c566:	4930      	ldr	r1, [pc, #192]	; (801c628 <tcp_pbuf_prealloc+0xe4>)
+ 801c568:	4830      	ldr	r0, [pc, #192]	; (801c62c <tcp_pbuf_prealloc+0xe8>)
+ 801c56a:	f005 fa0d 	bl	8021988 <iprintf>
+  LWIP_ASSERT("tcp_pbuf_prealloc: invalid pcb", pcb != NULL);
+ 801c56e:	6a3b      	ldr	r3, [r7, #32]
+ 801c570:	2b00      	cmp	r3, #0
+ 801c572:	d105      	bne.n	801c580 <tcp_pbuf_prealloc+0x3c>
+ 801c574:	4b2b      	ldr	r3, [pc, #172]	; (801c624 <tcp_pbuf_prealloc+0xe0>)
+ 801c576:	22e9      	movs	r2, #233	; 0xe9
+ 801c578:	492d      	ldr	r1, [pc, #180]	; (801c630 <tcp_pbuf_prealloc+0xec>)
+ 801c57a:	482c      	ldr	r0, [pc, #176]	; (801c62c <tcp_pbuf_prealloc+0xe8>)
+ 801c57c:	f005 fa04 	bl	8021988 <iprintf>
+  LWIP_UNUSED_ARG(pcb);
+  LWIP_UNUSED_ARG(apiflags);
+  LWIP_UNUSED_ARG(first_seg);
+  alloc = max_length;
+#else /* LWIP_NETIF_TX_SINGLE_PBUF */
+  if (length < max_length) {
+ 801c580:	89ba      	ldrh	r2, [r7, #12]
+ 801c582:	897b      	ldrh	r3, [r7, #10]
+ 801c584:	429a      	cmp	r2, r3
+ 801c586:	d221      	bcs.n	801c5cc <tcp_pbuf_prealloc+0x88>
+     *
+     * Did the user set TCP_WRITE_FLAG_MORE?
+     *
+     * Will the Nagle algorithm defer transmission of this segment?
+     */
+    if ((apiflags & TCP_WRITE_FLAG_MORE) ||
+ 801c588:	f897 3024 	ldrb.w	r3, [r7, #36]	; 0x24
+ 801c58c:	f003 0302 	and.w	r3, r3, #2
+ 801c590:	2b00      	cmp	r3, #0
+ 801c592:	d111      	bne.n	801c5b8 <tcp_pbuf_prealloc+0x74>
+        (!(pcb->flags & TF_NODELAY) &&
+ 801c594:	6a3b      	ldr	r3, [r7, #32]
+ 801c596:	8b5b      	ldrh	r3, [r3, #26]
+ 801c598:	f003 0340 	and.w	r3, r3, #64	; 0x40
+    if ((apiflags & TCP_WRITE_FLAG_MORE) ||
+ 801c59c:	2b00      	cmp	r3, #0
+ 801c59e:	d115      	bne.n	801c5cc <tcp_pbuf_prealloc+0x88>
+        (!(pcb->flags & TF_NODELAY) &&
+ 801c5a0:	f897 3028 	ldrb.w	r3, [r7, #40]	; 0x28
+ 801c5a4:	2b00      	cmp	r3, #0
+ 801c5a6:	d007      	beq.n	801c5b8 <tcp_pbuf_prealloc+0x74>
+         (!first_seg ||
+          pcb->unsent != NULL ||
+ 801c5a8:	6a3b      	ldr	r3, [r7, #32]
+ 801c5aa:	6edb      	ldr	r3, [r3, #108]	; 0x6c
+         (!first_seg ||
+ 801c5ac:	2b00      	cmp	r3, #0
+ 801c5ae:	d103      	bne.n	801c5b8 <tcp_pbuf_prealloc+0x74>
+          pcb->unacked != NULL))) {
+ 801c5b0:	6a3b      	ldr	r3, [r7, #32]
+ 801c5b2:	6f1b      	ldr	r3, [r3, #112]	; 0x70
+          pcb->unsent != NULL ||
+ 801c5b4:	2b00      	cmp	r3, #0
+ 801c5b6:	d009      	beq.n	801c5cc <tcp_pbuf_prealloc+0x88>
+      alloc = LWIP_MIN(max_length, LWIP_MEM_ALIGN_SIZE(TCP_OVERSIZE_CALC_LENGTH(length)));
+ 801c5b8:	89bb      	ldrh	r3, [r7, #12]
+ 801c5ba:	f203 53b7 	addw	r3, r3, #1463	; 0x5b7
+ 801c5be:	f023 0203 	bic.w	r2, r3, #3
+ 801c5c2:	897b      	ldrh	r3, [r7, #10]
+ 801c5c4:	4293      	cmp	r3, r2
+ 801c5c6:	bf28      	it	cs
+ 801c5c8:	4613      	movcs	r3, r2
+ 801c5ca:	82fb      	strh	r3, [r7, #22]
+    }
+  }
+#endif /* LWIP_NETIF_TX_SINGLE_PBUF */
+  p = pbuf_alloc(layer, alloc, PBUF_RAM);
+ 801c5cc:	8af9      	ldrh	r1, [r7, #22]
+ 801c5ce:	7bfb      	ldrb	r3, [r7, #15]
+ 801c5d0:	f44f 7220 	mov.w	r2, #640	; 0x280
+ 801c5d4:	4618      	mov	r0, r3
+ 801c5d6:	f7fa ffa7 	bl	8017528 <pbuf_alloc>
+ 801c5da:	6138      	str	r0, [r7, #16]
+  if (p == NULL) {
+ 801c5dc:	693b      	ldr	r3, [r7, #16]
+ 801c5de:	2b00      	cmp	r3, #0
+ 801c5e0:	d101      	bne.n	801c5e6 <tcp_pbuf_prealloc+0xa2>
+    return NULL;
+ 801c5e2:	2300      	movs	r3, #0
+ 801c5e4:	e019      	b.n	801c61a <tcp_pbuf_prealloc+0xd6>
+  }
+  LWIP_ASSERT("need unchained pbuf", p->next == NULL);
+ 801c5e6:	693b      	ldr	r3, [r7, #16]
+ 801c5e8:	681b      	ldr	r3, [r3, #0]
+ 801c5ea:	2b00      	cmp	r3, #0
+ 801c5ec:	d006      	beq.n	801c5fc <tcp_pbuf_prealloc+0xb8>
+ 801c5ee:	4b0d      	ldr	r3, [pc, #52]	; (801c624 <tcp_pbuf_prealloc+0xe0>)
+ 801c5f0:	f240 120b 	movw	r2, #267	; 0x10b
+ 801c5f4:	490f      	ldr	r1, [pc, #60]	; (801c634 <tcp_pbuf_prealloc+0xf0>)
+ 801c5f6:	480d      	ldr	r0, [pc, #52]	; (801c62c <tcp_pbuf_prealloc+0xe8>)
+ 801c5f8:	f005 f9c6 	bl	8021988 <iprintf>
+  *oversize = p->len - length;
+ 801c5fc:	693b      	ldr	r3, [r7, #16]
+ 801c5fe:	895a      	ldrh	r2, [r3, #10]
+ 801c600:	89bb      	ldrh	r3, [r7, #12]
+ 801c602:	1ad3      	subs	r3, r2, r3
+ 801c604:	b29a      	uxth	r2, r3
+ 801c606:	687b      	ldr	r3, [r7, #4]
+ 801c608:	801a      	strh	r2, [r3, #0]
+  /* trim p->len to the currently used size */
+  p->len = p->tot_len = length;
+ 801c60a:	693b      	ldr	r3, [r7, #16]
+ 801c60c:	89ba      	ldrh	r2, [r7, #12]
+ 801c60e:	811a      	strh	r2, [r3, #8]
+ 801c610:	693b      	ldr	r3, [r7, #16]
+ 801c612:	891a      	ldrh	r2, [r3, #8]
+ 801c614:	693b      	ldr	r3, [r7, #16]
+ 801c616:	815a      	strh	r2, [r3, #10]
+  return p;
+ 801c618:	693b      	ldr	r3, [r7, #16]
+}
+ 801c61a:	4618      	mov	r0, r3
+ 801c61c:	3718      	adds	r7, #24
+ 801c61e:	46bd      	mov	sp, r7
+ 801c620:	bd80      	pop	{r7, pc}
+ 801c622:	bf00      	nop
+ 801c624:	080257b8 	.word	0x080257b8
+ 801c628:	08025870 	.word	0x08025870
+ 801c62c:	0802580c 	.word	0x0802580c
+ 801c630:	08025894 	.word	0x08025894
+ 801c634:	080258b4 	.word	0x080258b4
+
+0801c638 <tcp_write_checks>:
+ * @param len length of data to send (checked agains snd_buf)
+ * @return ERR_OK if tcp_write is allowed to proceed, another err_t otherwise
+ */
+static err_t
+tcp_write_checks(struct tcp_pcb *pcb, u16_t len)
+{
+ 801c638:	b580      	push	{r7, lr}
+ 801c63a:	b082      	sub	sp, #8
+ 801c63c:	af00      	add	r7, sp, #0
+ 801c63e:	6078      	str	r0, [r7, #4]
+ 801c640:	460b      	mov	r3, r1
+ 801c642:	807b      	strh	r3, [r7, #2]
+  LWIP_ASSERT("tcp_write_checks: invalid pcb", pcb != NULL);
+ 801c644:	687b      	ldr	r3, [r7, #4]
+ 801c646:	2b00      	cmp	r3, #0
+ 801c648:	d106      	bne.n	801c658 <tcp_write_checks+0x20>
+ 801c64a:	4b33      	ldr	r3, [pc, #204]	; (801c718 <tcp_write_checks+0xe0>)
+ 801c64c:	f240 1233 	movw	r2, #307	; 0x133
+ 801c650:	4932      	ldr	r1, [pc, #200]	; (801c71c <tcp_write_checks+0xe4>)
+ 801c652:	4833      	ldr	r0, [pc, #204]	; (801c720 <tcp_write_checks+0xe8>)
+ 801c654:	f005 f998 	bl	8021988 <iprintf>
+
+  /* connection is in invalid state for data transmission? */
+  if ((pcb->state != ESTABLISHED) &&
+ 801c658:	687b      	ldr	r3, [r7, #4]
+ 801c65a:	7d1b      	ldrb	r3, [r3, #20]
+ 801c65c:	2b04      	cmp	r3, #4
+ 801c65e:	d00e      	beq.n	801c67e <tcp_write_checks+0x46>
+      (pcb->state != CLOSE_WAIT) &&
+ 801c660:	687b      	ldr	r3, [r7, #4]
+ 801c662:	7d1b      	ldrb	r3, [r3, #20]
+  if ((pcb->state != ESTABLISHED) &&
+ 801c664:	2b07      	cmp	r3, #7
+ 801c666:	d00a      	beq.n	801c67e <tcp_write_checks+0x46>
+      (pcb->state != SYN_SENT) &&
+ 801c668:	687b      	ldr	r3, [r7, #4]
+ 801c66a:	7d1b      	ldrb	r3, [r3, #20]
+      (pcb->state != CLOSE_WAIT) &&
+ 801c66c:	2b02      	cmp	r3, #2
+ 801c66e:	d006      	beq.n	801c67e <tcp_write_checks+0x46>
+      (pcb->state != SYN_RCVD)) {
+ 801c670:	687b      	ldr	r3, [r7, #4]
+ 801c672:	7d1b      	ldrb	r3, [r3, #20]
+      (pcb->state != SYN_SENT) &&
+ 801c674:	2b03      	cmp	r3, #3
+ 801c676:	d002      	beq.n	801c67e <tcp_write_checks+0x46>
+    LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_STATE | LWIP_DBG_LEVEL_SEVERE, ("tcp_write() called in invalid state\n"));
+    return ERR_CONN;
+ 801c678:	f06f 030a 	mvn.w	r3, #10
+ 801c67c:	e048      	b.n	801c710 <tcp_write_checks+0xd8>
+  } else if (len == 0) {
+ 801c67e:	887b      	ldrh	r3, [r7, #2]
+ 801c680:	2b00      	cmp	r3, #0
+ 801c682:	d101      	bne.n	801c688 <tcp_write_checks+0x50>
+    return ERR_OK;
+ 801c684:	2300      	movs	r3, #0
+ 801c686:	e043      	b.n	801c710 <tcp_write_checks+0xd8>
+  }
+
+  /* fail on too much data */
+  if (len > pcb->snd_buf) {
+ 801c688:	687b      	ldr	r3, [r7, #4]
+ 801c68a:	f8b3 3064 	ldrh.w	r3, [r3, #100]	; 0x64
+ 801c68e:	887a      	ldrh	r2, [r7, #2]
+ 801c690:	429a      	cmp	r2, r3
+ 801c692:	d909      	bls.n	801c6a8 <tcp_write_checks+0x70>
+    LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_LEVEL_SEVERE, ("tcp_write: too much data (len=%"U16_F" > snd_buf=%"TCPWNDSIZE_F")\n",
+                len, pcb->snd_buf));
+    tcp_set_flags(pcb, TF_NAGLEMEMERR);
+ 801c694:	687b      	ldr	r3, [r7, #4]
+ 801c696:	8b5b      	ldrh	r3, [r3, #26]
+ 801c698:	f043 0380 	orr.w	r3, r3, #128	; 0x80
+ 801c69c:	b29a      	uxth	r2, r3
+ 801c69e:	687b      	ldr	r3, [r7, #4]
+ 801c6a0:	835a      	strh	r2, [r3, #26]
+    return ERR_MEM;
+ 801c6a2:	f04f 33ff 	mov.w	r3, #4294967295
+ 801c6a6:	e033      	b.n	801c710 <tcp_write_checks+0xd8>
+  LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_write: queuelen: %"TCPWNDSIZE_F"\n", (tcpwnd_size_t)pcb->snd_queuelen));
+
+  /* If total number of pbufs on the unsent/unacked queues exceeds the
+   * configured maximum, return an error */
+  /* check for configured max queuelen and possible overflow */
+  if (pcb->snd_queuelen >= LWIP_MIN(TCP_SND_QUEUELEN, (TCP_SNDQUEUELEN_OVERFLOW + 1))) {
+ 801c6a8:	687b      	ldr	r3, [r7, #4]
+ 801c6aa:	f8b3 3066 	ldrh.w	r3, [r3, #102]	; 0x66
+ 801c6ae:	2b0f      	cmp	r3, #15
+ 801c6b0:	d909      	bls.n	801c6c6 <tcp_write_checks+0x8e>
+    LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_LEVEL_SEVERE, ("tcp_write: too long queue %"U16_F" (max %"U16_F")\n",
+                pcb->snd_queuelen, (u16_t)TCP_SND_QUEUELEN));
+    TCP_STATS_INC(tcp.memerr);
+    tcp_set_flags(pcb, TF_NAGLEMEMERR);
+ 801c6b2:	687b      	ldr	r3, [r7, #4]
+ 801c6b4:	8b5b      	ldrh	r3, [r3, #26]
+ 801c6b6:	f043 0380 	orr.w	r3, r3, #128	; 0x80
+ 801c6ba:	b29a      	uxth	r2, r3
+ 801c6bc:	687b      	ldr	r3, [r7, #4]
+ 801c6be:	835a      	strh	r2, [r3, #26]
+    return ERR_MEM;
+ 801c6c0:	f04f 33ff 	mov.w	r3, #4294967295
+ 801c6c4:	e024      	b.n	801c710 <tcp_write_checks+0xd8>
+  }
+  if (pcb->snd_queuelen != 0) {
+ 801c6c6:	687b      	ldr	r3, [r7, #4]
+ 801c6c8:	f8b3 3066 	ldrh.w	r3, [r3, #102]	; 0x66
+ 801c6cc:	2b00      	cmp	r3, #0
+ 801c6ce:	d00f      	beq.n	801c6f0 <tcp_write_checks+0xb8>
+    LWIP_ASSERT("tcp_write: pbufs on queue => at least one queue non-empty",
+ 801c6d0:	687b      	ldr	r3, [r7, #4]
+ 801c6d2:	6f1b      	ldr	r3, [r3, #112]	; 0x70
+ 801c6d4:	2b00      	cmp	r3, #0
+ 801c6d6:	d11a      	bne.n	801c70e <tcp_write_checks+0xd6>
+ 801c6d8:	687b      	ldr	r3, [r7, #4]
+ 801c6da:	6edb      	ldr	r3, [r3, #108]	; 0x6c
+ 801c6dc:	2b00      	cmp	r3, #0
+ 801c6de:	d116      	bne.n	801c70e <tcp_write_checks+0xd6>
+ 801c6e0:	4b0d      	ldr	r3, [pc, #52]	; (801c718 <tcp_write_checks+0xe0>)
+ 801c6e2:	f240 1255 	movw	r2, #341	; 0x155
+ 801c6e6:	490f      	ldr	r1, [pc, #60]	; (801c724 <tcp_write_checks+0xec>)
+ 801c6e8:	480d      	ldr	r0, [pc, #52]	; (801c720 <tcp_write_checks+0xe8>)
+ 801c6ea:	f005 f94d 	bl	8021988 <iprintf>
+ 801c6ee:	e00e      	b.n	801c70e <tcp_write_checks+0xd6>
+                pcb->unacked != NULL || pcb->unsent != NULL);
+  } else {
+    LWIP_ASSERT("tcp_write: no pbufs on queue => both queues empty",
+ 801c6f0:	687b      	ldr	r3, [r7, #4]
+ 801c6f2:	6f1b      	ldr	r3, [r3, #112]	; 0x70
+ 801c6f4:	2b00      	cmp	r3, #0
+ 801c6f6:	d103      	bne.n	801c700 <tcp_write_checks+0xc8>
+ 801c6f8:	687b      	ldr	r3, [r7, #4]
+ 801c6fa:	6edb      	ldr	r3, [r3, #108]	; 0x6c
+ 801c6fc:	2b00      	cmp	r3, #0
+ 801c6fe:	d006      	beq.n	801c70e <tcp_write_checks+0xd6>
+ 801c700:	4b05      	ldr	r3, [pc, #20]	; (801c718 <tcp_write_checks+0xe0>)
+ 801c702:	f44f 72ac 	mov.w	r2, #344	; 0x158
+ 801c706:	4908      	ldr	r1, [pc, #32]	; (801c728 <tcp_write_checks+0xf0>)
+ 801c708:	4805      	ldr	r0, [pc, #20]	; (801c720 <tcp_write_checks+0xe8>)
+ 801c70a:	f005 f93d 	bl	8021988 <iprintf>
+                pcb->unacked == NULL && pcb->unsent == NULL);
+  }
+  return ERR_OK;
+ 801c70e:	2300      	movs	r3, #0
+}
+ 801c710:	4618      	mov	r0, r3
+ 801c712:	3708      	adds	r7, #8
+ 801c714:	46bd      	mov	sp, r7
+ 801c716:	bd80      	pop	{r7, pc}
+ 801c718:	080257b8 	.word	0x080257b8
+ 801c71c:	080258c8 	.word	0x080258c8
+ 801c720:	0802580c 	.word	0x0802580c
+ 801c724:	080258e8 	.word	0x080258e8
+ 801c728:	08025924 	.word	0x08025924
+
+0801c72c <tcp_write>:
+ * - TCP_WRITE_FLAG_MORE (0x02) for TCP connection, PSH flag will not be set on last segment sent,
+ * @return ERR_OK if enqueued, another err_t on error
+ */
+err_t
+tcp_write(struct tcp_pcb *pcb, const void *arg, u16_t len, u8_t apiflags)
+{
+ 801c72c:	b590      	push	{r4, r7, lr}
+ 801c72e:	b09d      	sub	sp, #116	; 0x74
+ 801c730:	af04      	add	r7, sp, #16
+ 801c732:	60f8      	str	r0, [r7, #12]
+ 801c734:	60b9      	str	r1, [r7, #8]
+ 801c736:	4611      	mov	r1, r2
+ 801c738:	461a      	mov	r2, r3
+ 801c73a:	460b      	mov	r3, r1
+ 801c73c:	80fb      	strh	r3, [r7, #6]
+ 801c73e:	4613      	mov	r3, r2
+ 801c740:	717b      	strb	r3, [r7, #5]
+  struct pbuf *concat_p = NULL;
+ 801c742:	2300      	movs	r3, #0
+ 801c744:	63fb      	str	r3, [r7, #60]	; 0x3c
+  struct tcp_seg *last_unsent = NULL, *seg = NULL, *prev_seg = NULL, *queue = NULL;
+ 801c746:	2300      	movs	r3, #0
+ 801c748:	643b      	str	r3, [r7, #64]	; 0x40
+ 801c74a:	2300      	movs	r3, #0
+ 801c74c:	657b      	str	r3, [r7, #84]	; 0x54
+ 801c74e:	2300      	movs	r3, #0
+ 801c750:	653b      	str	r3, [r7, #80]	; 0x50
+ 801c752:	2300      	movs	r3, #0
+ 801c754:	64fb      	str	r3, [r7, #76]	; 0x4c
+  u16_t pos = 0; /* position in 'arg' data */
+ 801c756:	2300      	movs	r3, #0
+ 801c758:	f8a7 304a 	strh.w	r3, [r7, #74]	; 0x4a
+  u16_t queuelen;
+  u8_t optlen;
+  u8_t optflags = 0;
+ 801c75c:	2300      	movs	r3, #0
+ 801c75e:	f887 302b 	strb.w	r3, [r7, #43]	; 0x2b
+#if TCP_OVERSIZE
+  u16_t oversize = 0;
+ 801c762:	2300      	movs	r3, #0
+ 801c764:	82fb      	strh	r3, [r7, #22]
+  u16_t oversize_used = 0;
+ 801c766:	2300      	movs	r3, #0
+ 801c768:	f8a7 3046 	strh.w	r3, [r7, #70]	; 0x46
+#if TCP_OVERSIZE_DBGCHECK
+  u16_t oversize_add = 0;
+ 801c76c:	2300      	movs	r3, #0
+ 801c76e:	f8a7 305a 	strh.w	r3, [r7, #90]	; 0x5a
+#endif /* TCP_OVERSIZE_DBGCHECK*/
+#endif /* TCP_OVERSIZE */
+  u16_t extendlen = 0;
+ 801c772:	2300      	movs	r3, #0
+ 801c774:	f8a7 305e 	strh.w	r3, [r7, #94]	; 0x5e
+  u16_t concat_chksummed = 0;
+#endif /* TCP_CHECKSUM_ON_COPY */
+  err_t err;
+  u16_t mss_local;
+
+  LWIP_ERROR("tcp_write: invalid pcb", pcb != NULL, return ERR_ARG);
+ 801c778:	68fb      	ldr	r3, [r7, #12]
+ 801c77a:	2b00      	cmp	r3, #0
+ 801c77c:	d109      	bne.n	801c792 <tcp_write+0x66>
+ 801c77e:	4b9c      	ldr	r3, [pc, #624]	; (801c9f0 <tcp_write+0x2c4>)
+ 801c780:	f44f 72cf 	mov.w	r2, #414	; 0x19e
+ 801c784:	499b      	ldr	r1, [pc, #620]	; (801c9f4 <tcp_write+0x2c8>)
+ 801c786:	489c      	ldr	r0, [pc, #624]	; (801c9f8 <tcp_write+0x2cc>)
+ 801c788:	f005 f8fe 	bl	8021988 <iprintf>
+ 801c78c:	f06f 030f 	mvn.w	r3, #15
+ 801c790:	e379      	b.n	801ce86 <tcp_write+0x75a>
+
+  /* don't allocate segments bigger than half the maximum window we ever received */
+  mss_local = LWIP_MIN(pcb->mss, TCPWND_MIN16(pcb->snd_wnd_max / 2));
+ 801c792:	68fb      	ldr	r3, [r7, #12]
+ 801c794:	f8b3 3062 	ldrh.w	r3, [r3, #98]	; 0x62
+ 801c798:	085b      	lsrs	r3, r3, #1
+ 801c79a:	b29a      	uxth	r2, r3
+ 801c79c:	68fb      	ldr	r3, [r7, #12]
+ 801c79e:	8e5b      	ldrh	r3, [r3, #50]	; 0x32
+ 801c7a0:	4293      	cmp	r3, r2
+ 801c7a2:	bf28      	it	cs
+ 801c7a4:	4613      	movcs	r3, r2
+ 801c7a6:	853b      	strh	r3, [r7, #40]	; 0x28
+  mss_local = mss_local ? mss_local : pcb->mss;
+ 801c7a8:	8d3b      	ldrh	r3, [r7, #40]	; 0x28
+ 801c7aa:	2b00      	cmp	r3, #0
+ 801c7ac:	d102      	bne.n	801c7b4 <tcp_write+0x88>
+ 801c7ae:	68fb      	ldr	r3, [r7, #12]
+ 801c7b0:	8e5b      	ldrh	r3, [r3, #50]	; 0x32
+ 801c7b2:	e000      	b.n	801c7b6 <tcp_write+0x8a>
+ 801c7b4:	8d3b      	ldrh	r3, [r7, #40]	; 0x28
+ 801c7b6:	853b      	strh	r3, [r7, #40]	; 0x28
+  apiflags |= TCP_WRITE_FLAG_COPY;
+#endif /* LWIP_NETIF_TX_SINGLE_PBUF */
+
+  LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_write(pcb=%p, data=%p, len=%"U16_F", apiflags=%"U16_F")\n",
+                                 (void *)pcb, arg, len, (u16_t)apiflags));
+  LWIP_ERROR("tcp_write: arg == NULL (programmer violates API)",
+ 801c7b8:	68bb      	ldr	r3, [r7, #8]
+ 801c7ba:	2b00      	cmp	r3, #0
+ 801c7bc:	d109      	bne.n	801c7d2 <tcp_write+0xa6>
+ 801c7be:	4b8c      	ldr	r3, [pc, #560]	; (801c9f0 <tcp_write+0x2c4>)
+ 801c7c0:	f240 12ad 	movw	r2, #429	; 0x1ad
+ 801c7c4:	498d      	ldr	r1, [pc, #564]	; (801c9fc <tcp_write+0x2d0>)
+ 801c7c6:	488c      	ldr	r0, [pc, #560]	; (801c9f8 <tcp_write+0x2cc>)
+ 801c7c8:	f005 f8de 	bl	8021988 <iprintf>
+ 801c7cc:	f06f 030f 	mvn.w	r3, #15
+ 801c7d0:	e359      	b.n	801ce86 <tcp_write+0x75a>
+             arg != NULL, return ERR_ARG;);
+
+  err = tcp_write_checks(pcb, len);
+ 801c7d2:	88fb      	ldrh	r3, [r7, #6]
+ 801c7d4:	4619      	mov	r1, r3
+ 801c7d6:	68f8      	ldr	r0, [r7, #12]
+ 801c7d8:	f7ff ff2e 	bl	801c638 <tcp_write_checks>
+ 801c7dc:	4603      	mov	r3, r0
+ 801c7de:	f887 3027 	strb.w	r3, [r7, #39]	; 0x27
+  if (err != ERR_OK) {
+ 801c7e2:	f997 3027 	ldrsb.w	r3, [r7, #39]	; 0x27
+ 801c7e6:	2b00      	cmp	r3, #0
+ 801c7e8:	d002      	beq.n	801c7f0 <tcp_write+0xc4>
+    return err;
+ 801c7ea:	f997 3027 	ldrsb.w	r3, [r7, #39]	; 0x27
+ 801c7ee:	e34a      	b.n	801ce86 <tcp_write+0x75a>
+  }
+  queuelen = pcb->snd_queuelen;
+ 801c7f0:	68fb      	ldr	r3, [r7, #12]
+ 801c7f2:	f8b3 3066 	ldrh.w	r3, [r3, #102]	; 0x66
+ 801c7f6:	f8a7 3048 	strh.w	r3, [r7, #72]	; 0x48
+    /* ensure that segments can hold at least one data byte... */
+    mss_local = LWIP_MAX(mss_local, LWIP_TCP_OPT_LEN_TS + 1);
+  } else
+#endif /* LWIP_TCP_TIMESTAMPS */
+  {
+    optlen = LWIP_TCP_OPT_LENGTH_SEGMENT(0, pcb);
+ 801c7fa:	2300      	movs	r3, #0
+ 801c7fc:	f887 3026 	strb.w	r3, [r7, #38]	; 0x26
+   *
+   * pos records progress as data is segmented.
+   */
+
+  /* Find the tail of the unsent queue. */
+  if (pcb->unsent != NULL) {
+ 801c800:	68fb      	ldr	r3, [r7, #12]
+ 801c802:	6edb      	ldr	r3, [r3, #108]	; 0x6c
+ 801c804:	2b00      	cmp	r3, #0
+ 801c806:	f000 8127 	beq.w	801ca58 <tcp_write+0x32c>
+    u16_t space;
+    u16_t unsent_optlen;
+
+    /* @todo: this could be sped up by keeping last_unsent in the pcb */
+    for (last_unsent = pcb->unsent; last_unsent->next != NULL;
+ 801c80a:	68fb      	ldr	r3, [r7, #12]
+ 801c80c:	6edb      	ldr	r3, [r3, #108]	; 0x6c
+ 801c80e:	643b      	str	r3, [r7, #64]	; 0x40
+ 801c810:	e002      	b.n	801c818 <tcp_write+0xec>
+         last_unsent = last_unsent->next);
+ 801c812:	6c3b      	ldr	r3, [r7, #64]	; 0x40
+ 801c814:	681b      	ldr	r3, [r3, #0]
+ 801c816:	643b      	str	r3, [r7, #64]	; 0x40
+    for (last_unsent = pcb->unsent; last_unsent->next != NULL;
+ 801c818:	6c3b      	ldr	r3, [r7, #64]	; 0x40
+ 801c81a:	681b      	ldr	r3, [r3, #0]
+ 801c81c:	2b00      	cmp	r3, #0
+ 801c81e:	d1f8      	bne.n	801c812 <tcp_write+0xe6>
+
+    /* Usable space at the end of the last unsent segment */
+    unsent_optlen = LWIP_TCP_OPT_LENGTH_SEGMENT(last_unsent->flags, pcb);
+ 801c820:	6c3b      	ldr	r3, [r7, #64]	; 0x40
+ 801c822:	7b1b      	ldrb	r3, [r3, #12]
+ 801c824:	009b      	lsls	r3, r3, #2
+ 801c826:	b29b      	uxth	r3, r3
+ 801c828:	f003 0304 	and.w	r3, r3, #4
+ 801c82c:	84bb      	strh	r3, [r7, #36]	; 0x24
+    LWIP_ASSERT("mss_local is too small", mss_local >= last_unsent->len + unsent_optlen);
+ 801c82e:	8d3a      	ldrh	r2, [r7, #40]	; 0x28
+ 801c830:	6c3b      	ldr	r3, [r7, #64]	; 0x40
+ 801c832:	891b      	ldrh	r3, [r3, #8]
+ 801c834:	4619      	mov	r1, r3
+ 801c836:	8cbb      	ldrh	r3, [r7, #36]	; 0x24
+ 801c838:	440b      	add	r3, r1
+ 801c83a:	429a      	cmp	r2, r3
+ 801c83c:	da06      	bge.n	801c84c <tcp_write+0x120>
+ 801c83e:	4b6c      	ldr	r3, [pc, #432]	; (801c9f0 <tcp_write+0x2c4>)
+ 801c840:	f44f 72f3 	mov.w	r2, #486	; 0x1e6
+ 801c844:	496e      	ldr	r1, [pc, #440]	; (801ca00 <tcp_write+0x2d4>)
+ 801c846:	486c      	ldr	r0, [pc, #432]	; (801c9f8 <tcp_write+0x2cc>)
+ 801c848:	f005 f89e 	bl	8021988 <iprintf>
+    space = mss_local - (last_unsent->len + unsent_optlen);
+ 801c84c:	6c3b      	ldr	r3, [r7, #64]	; 0x40
+ 801c84e:	891a      	ldrh	r2, [r3, #8]
+ 801c850:	8cbb      	ldrh	r3, [r7, #36]	; 0x24
+ 801c852:	4413      	add	r3, r2
+ 801c854:	b29b      	uxth	r3, r3
+ 801c856:	8d3a      	ldrh	r2, [r7, #40]	; 0x28
+ 801c858:	1ad3      	subs	r3, r2, r3
+ 801c85a:	f8a7 305c 	strh.w	r3, [r7, #92]	; 0x5c
+     * function.
+     */
+#if TCP_OVERSIZE
+#if TCP_OVERSIZE_DBGCHECK
+    /* check that pcb->unsent_oversize matches last_unsent->oversize_left */
+    LWIP_ASSERT("unsent_oversize mismatch (pcb vs. last_unsent)",
+ 801c85e:	68fb      	ldr	r3, [r7, #12]
+ 801c860:	f8b3 2068 	ldrh.w	r2, [r3, #104]	; 0x68
+ 801c864:	6c3b      	ldr	r3, [r7, #64]	; 0x40
+ 801c866:	895b      	ldrh	r3, [r3, #10]
+ 801c868:	429a      	cmp	r2, r3
+ 801c86a:	d006      	beq.n	801c87a <tcp_write+0x14e>
+ 801c86c:	4b60      	ldr	r3, [pc, #384]	; (801c9f0 <tcp_write+0x2c4>)
+ 801c86e:	f240 12f3 	movw	r2, #499	; 0x1f3
+ 801c872:	4964      	ldr	r1, [pc, #400]	; (801ca04 <tcp_write+0x2d8>)
+ 801c874:	4860      	ldr	r0, [pc, #384]	; (801c9f8 <tcp_write+0x2cc>)
+ 801c876:	f005 f887 	bl	8021988 <iprintf>
+                pcb->unsent_oversize == last_unsent->oversize_left);
+#endif /* TCP_OVERSIZE_DBGCHECK */
+    oversize = pcb->unsent_oversize;
+ 801c87a:	68fb      	ldr	r3, [r7, #12]
+ 801c87c:	f8b3 3068 	ldrh.w	r3, [r3, #104]	; 0x68
+ 801c880:	82fb      	strh	r3, [r7, #22]
+    if (oversize > 0) {
+ 801c882:	8afb      	ldrh	r3, [r7, #22]
+ 801c884:	2b00      	cmp	r3, #0
+ 801c886:	d02e      	beq.n	801c8e6 <tcp_write+0x1ba>
+      LWIP_ASSERT("inconsistent oversize vs. space", oversize <= space);
+ 801c888:	8afb      	ldrh	r3, [r7, #22]
+ 801c88a:	f8b7 205c 	ldrh.w	r2, [r7, #92]	; 0x5c
+ 801c88e:	429a      	cmp	r2, r3
+ 801c890:	d206      	bcs.n	801c8a0 <tcp_write+0x174>
+ 801c892:	4b57      	ldr	r3, [pc, #348]	; (801c9f0 <tcp_write+0x2c4>)
+ 801c894:	f44f 72fc 	mov.w	r2, #504	; 0x1f8
+ 801c898:	495b      	ldr	r1, [pc, #364]	; (801ca08 <tcp_write+0x2dc>)
+ 801c89a:	4857      	ldr	r0, [pc, #348]	; (801c9f8 <tcp_write+0x2cc>)
+ 801c89c:	f005 f874 	bl	8021988 <iprintf>
+      seg = last_unsent;
+ 801c8a0:	6c3b      	ldr	r3, [r7, #64]	; 0x40
+ 801c8a2:	657b      	str	r3, [r7, #84]	; 0x54
+      oversize_used = LWIP_MIN(space, LWIP_MIN(oversize, len));
+ 801c8a4:	8afb      	ldrh	r3, [r7, #22]
+ 801c8a6:	88fa      	ldrh	r2, [r7, #6]
+ 801c8a8:	4293      	cmp	r3, r2
+ 801c8aa:	bf28      	it	cs
+ 801c8ac:	4613      	movcs	r3, r2
+ 801c8ae:	b29b      	uxth	r3, r3
+ 801c8b0:	f8b7 205c 	ldrh.w	r2, [r7, #92]	; 0x5c
+ 801c8b4:	4293      	cmp	r3, r2
+ 801c8b6:	bf28      	it	cs
+ 801c8b8:	4613      	movcs	r3, r2
+ 801c8ba:	f8a7 3046 	strh.w	r3, [r7, #70]	; 0x46
+      pos += oversize_used;
+ 801c8be:	f8b7 204a 	ldrh.w	r2, [r7, #74]	; 0x4a
+ 801c8c2:	f8b7 3046 	ldrh.w	r3, [r7, #70]	; 0x46
+ 801c8c6:	4413      	add	r3, r2
+ 801c8c8:	f8a7 304a 	strh.w	r3, [r7, #74]	; 0x4a
+      oversize -= oversize_used;
+ 801c8cc:	8afa      	ldrh	r2, [r7, #22]
+ 801c8ce:	f8b7 3046 	ldrh.w	r3, [r7, #70]	; 0x46
+ 801c8d2:	1ad3      	subs	r3, r2, r3
+ 801c8d4:	b29b      	uxth	r3, r3
+ 801c8d6:	82fb      	strh	r3, [r7, #22]
+      space -= oversize_used;
+ 801c8d8:	f8b7 205c 	ldrh.w	r2, [r7, #92]	; 0x5c
+ 801c8dc:	f8b7 3046 	ldrh.w	r3, [r7, #70]	; 0x46
+ 801c8e0:	1ad3      	subs	r3, r2, r3
+ 801c8e2:	f8a7 305c 	strh.w	r3, [r7, #92]	; 0x5c
+    }
+    /* now we are either finished or oversize is zero */
+    LWIP_ASSERT("inconsistent oversize vs. len", (oversize == 0) || (pos == len));
+ 801c8e6:	8afb      	ldrh	r3, [r7, #22]
+ 801c8e8:	2b00      	cmp	r3, #0
+ 801c8ea:	d00b      	beq.n	801c904 <tcp_write+0x1d8>
+ 801c8ec:	f8b7 204a 	ldrh.w	r2, [r7, #74]	; 0x4a
+ 801c8f0:	88fb      	ldrh	r3, [r7, #6]
+ 801c8f2:	429a      	cmp	r2, r3
+ 801c8f4:	d006      	beq.n	801c904 <tcp_write+0x1d8>
+ 801c8f6:	4b3e      	ldr	r3, [pc, #248]	; (801c9f0 <tcp_write+0x2c4>)
+ 801c8f8:	f44f 7200 	mov.w	r2, #512	; 0x200
+ 801c8fc:	4943      	ldr	r1, [pc, #268]	; (801ca0c <tcp_write+0x2e0>)
+ 801c8fe:	483e      	ldr	r0, [pc, #248]	; (801c9f8 <tcp_write+0x2cc>)
+ 801c900:	f005 f842 	bl	8021988 <iprintf>
+     *
+     * This phase is skipped for LWIP_NETIF_TX_SINGLE_PBUF as we could only execute
+     * it after rexmit puts a segment from unacked to unsent and at this point,
+     * oversize info is lost.
+     */
+    if ((pos < len) && (space > 0) && (last_unsent->len > 0)) {
+ 801c904:	f8b7 204a 	ldrh.w	r2, [r7, #74]	; 0x4a
+ 801c908:	88fb      	ldrh	r3, [r7, #6]
+ 801c90a:	429a      	cmp	r2, r3
+ 801c90c:	f080 8172 	bcs.w	801cbf4 <tcp_write+0x4c8>
+ 801c910:	f8b7 305c 	ldrh.w	r3, [r7, #92]	; 0x5c
+ 801c914:	2b00      	cmp	r3, #0
+ 801c916:	f000 816d 	beq.w	801cbf4 <tcp_write+0x4c8>
+ 801c91a:	6c3b      	ldr	r3, [r7, #64]	; 0x40
+ 801c91c:	891b      	ldrh	r3, [r3, #8]
+ 801c91e:	2b00      	cmp	r3, #0
+ 801c920:	f000 8168 	beq.w	801cbf4 <tcp_write+0x4c8>
+      u16_t seglen = LWIP_MIN(space, len - pos);
+ 801c924:	88fa      	ldrh	r2, [r7, #6]
+ 801c926:	f8b7 304a 	ldrh.w	r3, [r7, #74]	; 0x4a
+ 801c92a:	1ad2      	subs	r2, r2, r3
+ 801c92c:	f8b7 305c 	ldrh.w	r3, [r7, #92]	; 0x5c
+ 801c930:	4293      	cmp	r3, r2
+ 801c932:	bfa8      	it	ge
+ 801c934:	4613      	movge	r3, r2
+ 801c936:	847b      	strh	r3, [r7, #34]	; 0x22
+      seg = last_unsent;
+ 801c938:	6c3b      	ldr	r3, [r7, #64]	; 0x40
+ 801c93a:	657b      	str	r3, [r7, #84]	; 0x54
+
+      /* Create a pbuf with a copy or reference to seglen bytes. We
+       * can use PBUF_RAW here since the data appears in the middle of
+       * a segment. A header will never be prepended. */
+      if (apiflags & TCP_WRITE_FLAG_COPY) {
+ 801c93c:	797b      	ldrb	r3, [r7, #5]
+ 801c93e:	f003 0301 	and.w	r3, r3, #1
+ 801c942:	2b00      	cmp	r3, #0
+ 801c944:	d02b      	beq.n	801c99e <tcp_write+0x272>
+        /* Data is copied */
+        if ((concat_p = tcp_pbuf_prealloc(PBUF_RAW, seglen, space, &oversize, pcb, apiflags, 1)) == NULL) {
+ 801c946:	f107 0016 	add.w	r0, r7, #22
+ 801c94a:	f8b7 205c 	ldrh.w	r2, [r7, #92]	; 0x5c
+ 801c94e:	8c79      	ldrh	r1, [r7, #34]	; 0x22
+ 801c950:	2301      	movs	r3, #1
+ 801c952:	9302      	str	r3, [sp, #8]
+ 801c954:	797b      	ldrb	r3, [r7, #5]
+ 801c956:	9301      	str	r3, [sp, #4]
+ 801c958:	68fb      	ldr	r3, [r7, #12]
+ 801c95a:	9300      	str	r3, [sp, #0]
+ 801c95c:	4603      	mov	r3, r0
+ 801c95e:	2000      	movs	r0, #0
+ 801c960:	f7ff fdf0 	bl	801c544 <tcp_pbuf_prealloc>
+ 801c964:	63f8      	str	r0, [r7, #60]	; 0x3c
+ 801c966:	6bfb      	ldr	r3, [r7, #60]	; 0x3c
+ 801c968:	2b00      	cmp	r3, #0
+ 801c96a:	f000 825a 	beq.w	801ce22 <tcp_write+0x6f6>
+                      ("tcp_write : could not allocate memory for pbuf copy size %"U16_F"\n",
+                       seglen));
+          goto memerr;
+        }
+#if TCP_OVERSIZE_DBGCHECK
+        oversize_add = oversize;
+ 801c96e:	8afb      	ldrh	r3, [r7, #22]
+ 801c970:	f8a7 305a 	strh.w	r3, [r7, #90]	; 0x5a
+#endif /* TCP_OVERSIZE_DBGCHECK */
+        TCP_DATA_COPY2(concat_p->payload, (const u8_t *)arg + pos, seglen, &concat_chksum, &concat_chksum_swapped);
+ 801c974:	6bfb      	ldr	r3, [r7, #60]	; 0x3c
+ 801c976:	6858      	ldr	r0, [r3, #4]
+ 801c978:	f8b7 304a 	ldrh.w	r3, [r7, #74]	; 0x4a
+ 801c97c:	68ba      	ldr	r2, [r7, #8]
+ 801c97e:	4413      	add	r3, r2
+ 801c980:	8c7a      	ldrh	r2, [r7, #34]	; 0x22
+ 801c982:	4619      	mov	r1, r3
+ 801c984:	f005 fa2f 	bl	8021de6 <memcpy>
+#if TCP_CHECKSUM_ON_COPY
+        concat_chksummed += seglen;
+#endif /* TCP_CHECKSUM_ON_COPY */
+        queuelen += pbuf_clen(concat_p);
+ 801c988:	6bf8      	ldr	r0, [r7, #60]	; 0x3c
+ 801c98a:	f7fb f943 	bl	8017c14 <pbuf_clen>
+ 801c98e:	4603      	mov	r3, r0
+ 801c990:	461a      	mov	r2, r3
+ 801c992:	f8b7 3048 	ldrh.w	r3, [r7, #72]	; 0x48
+ 801c996:	4413      	add	r3, r2
+ 801c998:	f8a7 3048 	strh.w	r3, [r7, #72]	; 0x48
+ 801c99c:	e055      	b.n	801ca4a <tcp_write+0x31e>
+      } else {
+        /* Data is not copied */
+        /* If the last unsent pbuf is of type PBUF_ROM, try to extend it. */
+        struct pbuf *p;
+        for (p = last_unsent->p; p->next != NULL; p = p->next);
+ 801c99e:	6c3b      	ldr	r3, [r7, #64]	; 0x40
+ 801c9a0:	685b      	ldr	r3, [r3, #4]
+ 801c9a2:	63bb      	str	r3, [r7, #56]	; 0x38
+ 801c9a4:	e002      	b.n	801c9ac <tcp_write+0x280>
+ 801c9a6:	6bbb      	ldr	r3, [r7, #56]	; 0x38
+ 801c9a8:	681b      	ldr	r3, [r3, #0]
+ 801c9aa:	63bb      	str	r3, [r7, #56]	; 0x38
+ 801c9ac:	6bbb      	ldr	r3, [r7, #56]	; 0x38
+ 801c9ae:	681b      	ldr	r3, [r3, #0]
+ 801c9b0:	2b00      	cmp	r3, #0
+ 801c9b2:	d1f8      	bne.n	801c9a6 <tcp_write+0x27a>
+        if (((p->type_internal & (PBUF_TYPE_FLAG_STRUCT_DATA_CONTIGUOUS | PBUF_TYPE_FLAG_DATA_VOLATILE)) == 0) &&
+ 801c9b4:	6bbb      	ldr	r3, [r7, #56]	; 0x38
+ 801c9b6:	7b1b      	ldrb	r3, [r3, #12]
+ 801c9b8:	f003 03c0 	and.w	r3, r3, #192	; 0xc0
+ 801c9bc:	2b00      	cmp	r3, #0
+ 801c9be:	d129      	bne.n	801ca14 <tcp_write+0x2e8>
+            (const u8_t *)p->payload + p->len == (const u8_t *)arg) {
+ 801c9c0:	6bbb      	ldr	r3, [r7, #56]	; 0x38
+ 801c9c2:	685b      	ldr	r3, [r3, #4]
+ 801c9c4:	6bba      	ldr	r2, [r7, #56]	; 0x38
+ 801c9c6:	8952      	ldrh	r2, [r2, #10]
+ 801c9c8:	4413      	add	r3, r2
+        if (((p->type_internal & (PBUF_TYPE_FLAG_STRUCT_DATA_CONTIGUOUS | PBUF_TYPE_FLAG_DATA_VOLATILE)) == 0) &&
+ 801c9ca:	68ba      	ldr	r2, [r7, #8]
+ 801c9cc:	429a      	cmp	r2, r3
+ 801c9ce:	d121      	bne.n	801ca14 <tcp_write+0x2e8>
+          LWIP_ASSERT("tcp_write: ROM pbufs cannot be oversized", pos == 0);
+ 801c9d0:	f8b7 304a 	ldrh.w	r3, [r7, #74]	; 0x4a
+ 801c9d4:	2b00      	cmp	r3, #0
+ 801c9d6:	d006      	beq.n	801c9e6 <tcp_write+0x2ba>
+ 801c9d8:	4b05      	ldr	r3, [pc, #20]	; (801c9f0 <tcp_write+0x2c4>)
+ 801c9da:	f240 2231 	movw	r2, #561	; 0x231
+ 801c9de:	490c      	ldr	r1, [pc, #48]	; (801ca10 <tcp_write+0x2e4>)
+ 801c9e0:	4805      	ldr	r0, [pc, #20]	; (801c9f8 <tcp_write+0x2cc>)
+ 801c9e2:	f004 ffd1 	bl	8021988 <iprintf>
+          extendlen = seglen;
+ 801c9e6:	8c7b      	ldrh	r3, [r7, #34]	; 0x22
+ 801c9e8:	f8a7 305e 	strh.w	r3, [r7, #94]	; 0x5e
+ 801c9ec:	e02d      	b.n	801ca4a <tcp_write+0x31e>
+ 801c9ee:	bf00      	nop
+ 801c9f0:	080257b8 	.word	0x080257b8
+ 801c9f4:	08025958 	.word	0x08025958
+ 801c9f8:	0802580c 	.word	0x0802580c
+ 801c9fc:	08025970 	.word	0x08025970
+ 801ca00:	080259a4 	.word	0x080259a4
+ 801ca04:	080259bc 	.word	0x080259bc
+ 801ca08:	080259ec 	.word	0x080259ec
+ 801ca0c:	08025a0c 	.word	0x08025a0c
+ 801ca10:	08025a2c 	.word	0x08025a2c
+        } else {
+          if ((concat_p = pbuf_alloc(PBUF_RAW, seglen, PBUF_ROM)) == NULL) {
+ 801ca14:	8c7b      	ldrh	r3, [r7, #34]	; 0x22
+ 801ca16:	2201      	movs	r2, #1
+ 801ca18:	4619      	mov	r1, r3
+ 801ca1a:	2000      	movs	r0, #0
+ 801ca1c:	f7fa fd84 	bl	8017528 <pbuf_alloc>
+ 801ca20:	63f8      	str	r0, [r7, #60]	; 0x3c
+ 801ca22:	6bfb      	ldr	r3, [r7, #60]	; 0x3c
+ 801ca24:	2b00      	cmp	r3, #0
+ 801ca26:	f000 81fe 	beq.w	801ce26 <tcp_write+0x6fa>
+            LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_LEVEL_SERIOUS,
+                        ("tcp_write: could not allocate memory for zero-copy pbuf\n"));
+            goto memerr;
+          }
+          /* reference the non-volatile payload data */
+          ((struct pbuf_rom *)concat_p)->payload = (const u8_t *)arg + pos;
+ 801ca2a:	f8b7 304a 	ldrh.w	r3, [r7, #74]	; 0x4a
+ 801ca2e:	68ba      	ldr	r2, [r7, #8]
+ 801ca30:	441a      	add	r2, r3
+ 801ca32:	6bfb      	ldr	r3, [r7, #60]	; 0x3c
+ 801ca34:	605a      	str	r2, [r3, #4]
+          queuelen += pbuf_clen(concat_p);
+ 801ca36:	6bf8      	ldr	r0, [r7, #60]	; 0x3c
+ 801ca38:	f7fb f8ec 	bl	8017c14 <pbuf_clen>
+ 801ca3c:	4603      	mov	r3, r0
+ 801ca3e:	461a      	mov	r2, r3
+ 801ca40:	f8b7 3048 	ldrh.w	r3, [r7, #72]	; 0x48
+ 801ca44:	4413      	add	r3, r2
+ 801ca46:	f8a7 3048 	strh.w	r3, [r7, #72]	; 0x48
+                           &concat_chksum, &concat_chksum_swapped);
+        concat_chksummed += seglen;
+#endif /* TCP_CHECKSUM_ON_COPY */
+      }
+
+      pos += seglen;
+ 801ca4a:	f8b7 204a 	ldrh.w	r2, [r7, #74]	; 0x4a
+ 801ca4e:	8c7b      	ldrh	r3, [r7, #34]	; 0x22
+ 801ca50:	4413      	add	r3, r2
+ 801ca52:	f8a7 304a 	strh.w	r3, [r7, #74]	; 0x4a
+ 801ca56:	e0cd      	b.n	801cbf4 <tcp_write+0x4c8>
+    }
+#endif /* !LWIP_NETIF_TX_SINGLE_PBUF */
+  } else {
+#if TCP_OVERSIZE
+    LWIP_ASSERT("unsent_oversize mismatch (pcb->unsent is NULL)",
+ 801ca58:	68fb      	ldr	r3, [r7, #12]
+ 801ca5a:	f8b3 3068 	ldrh.w	r3, [r3, #104]	; 0x68
+ 801ca5e:	2b00      	cmp	r3, #0
+ 801ca60:	f000 80c8 	beq.w	801cbf4 <tcp_write+0x4c8>
+ 801ca64:	4b72      	ldr	r3, [pc, #456]	; (801cc30 <tcp_write+0x504>)
+ 801ca66:	f240 224a 	movw	r2, #586	; 0x24a
+ 801ca6a:	4972      	ldr	r1, [pc, #456]	; (801cc34 <tcp_write+0x508>)
+ 801ca6c:	4872      	ldr	r0, [pc, #456]	; (801cc38 <tcp_write+0x50c>)
+ 801ca6e:	f004 ff8b 	bl	8021988 <iprintf>
+   * Phase 3: Create new segments.
+   *
+   * The new segments are chained together in the local 'queue'
+   * variable, ready to be appended to pcb->unsent.
+   */
+  while (pos < len) {
+ 801ca72:	e0bf      	b.n	801cbf4 <tcp_write+0x4c8>
+    struct pbuf *p;
+    u16_t left = len - pos;
+ 801ca74:	88fa      	ldrh	r2, [r7, #6]
+ 801ca76:	f8b7 304a 	ldrh.w	r3, [r7, #74]	; 0x4a
+ 801ca7a:	1ad3      	subs	r3, r2, r3
+ 801ca7c:	843b      	strh	r3, [r7, #32]
+    u16_t max_len = mss_local - optlen;
+ 801ca7e:	f897 3026 	ldrb.w	r3, [r7, #38]	; 0x26
+ 801ca82:	b29b      	uxth	r3, r3
+ 801ca84:	8d3a      	ldrh	r2, [r7, #40]	; 0x28
+ 801ca86:	1ad3      	subs	r3, r2, r3
+ 801ca88:	83fb      	strh	r3, [r7, #30]
+    u16_t seglen = LWIP_MIN(left, max_len);
+ 801ca8a:	8bfa      	ldrh	r2, [r7, #30]
+ 801ca8c:	8c3b      	ldrh	r3, [r7, #32]
+ 801ca8e:	4293      	cmp	r3, r2
+ 801ca90:	bf28      	it	cs
+ 801ca92:	4613      	movcs	r3, r2
+ 801ca94:	83bb      	strh	r3, [r7, #28]
+#if TCP_CHECKSUM_ON_COPY
+    u16_t chksum = 0;
+    u8_t chksum_swapped = 0;
+#endif /* TCP_CHECKSUM_ON_COPY */
+
+    if (apiflags & TCP_WRITE_FLAG_COPY) {
+ 801ca96:	797b      	ldrb	r3, [r7, #5]
+ 801ca98:	f003 0301 	and.w	r3, r3, #1
+ 801ca9c:	2b00      	cmp	r3, #0
+ 801ca9e:	d036      	beq.n	801cb0e <tcp_write+0x3e2>
+      /* If copy is set, memory should be allocated and data copied
+       * into pbuf */
+      if ((p = tcp_pbuf_prealloc(PBUF_TRANSPORT, seglen + optlen, mss_local, &oversize, pcb, apiflags, queue == NULL)) == NULL) {
+ 801caa0:	f897 3026 	ldrb.w	r3, [r7, #38]	; 0x26
+ 801caa4:	b29a      	uxth	r2, r3
+ 801caa6:	8bbb      	ldrh	r3, [r7, #28]
+ 801caa8:	4413      	add	r3, r2
+ 801caaa:	b299      	uxth	r1, r3
+ 801caac:	6cfb      	ldr	r3, [r7, #76]	; 0x4c
+ 801caae:	2b00      	cmp	r3, #0
+ 801cab0:	bf0c      	ite	eq
+ 801cab2:	2301      	moveq	r3, #1
+ 801cab4:	2300      	movne	r3, #0
+ 801cab6:	b2db      	uxtb	r3, r3
+ 801cab8:	f107 0016 	add.w	r0, r7, #22
+ 801cabc:	8d3a      	ldrh	r2, [r7, #40]	; 0x28
+ 801cabe:	9302      	str	r3, [sp, #8]
+ 801cac0:	797b      	ldrb	r3, [r7, #5]
+ 801cac2:	9301      	str	r3, [sp, #4]
+ 801cac4:	68fb      	ldr	r3, [r7, #12]
+ 801cac6:	9300      	str	r3, [sp, #0]
+ 801cac8:	4603      	mov	r3, r0
+ 801caca:	2036      	movs	r0, #54	; 0x36
+ 801cacc:	f7ff fd3a 	bl	801c544 <tcp_pbuf_prealloc>
+ 801cad0:	6378      	str	r0, [r7, #52]	; 0x34
+ 801cad2:	6b7b      	ldr	r3, [r7, #52]	; 0x34
+ 801cad4:	2b00      	cmp	r3, #0
+ 801cad6:	f000 81a8 	beq.w	801ce2a <tcp_write+0x6fe>
+        LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("tcp_write : could not allocate memory for pbuf copy size %"U16_F"\n", seglen));
+        goto memerr;
+      }
+      LWIP_ASSERT("tcp_write: check that first pbuf can hold the complete seglen",
+ 801cada:	6b7b      	ldr	r3, [r7, #52]	; 0x34
+ 801cadc:	895b      	ldrh	r3, [r3, #10]
+ 801cade:	8bba      	ldrh	r2, [r7, #28]
+ 801cae0:	429a      	cmp	r2, r3
+ 801cae2:	d906      	bls.n	801caf2 <tcp_write+0x3c6>
+ 801cae4:	4b52      	ldr	r3, [pc, #328]	; (801cc30 <tcp_write+0x504>)
+ 801cae6:	f240 2266 	movw	r2, #614	; 0x266
+ 801caea:	4954      	ldr	r1, [pc, #336]	; (801cc3c <tcp_write+0x510>)
+ 801caec:	4852      	ldr	r0, [pc, #328]	; (801cc38 <tcp_write+0x50c>)
+ 801caee:	f004 ff4b 	bl	8021988 <iprintf>
+                  (p->len >= seglen));
+      TCP_DATA_COPY2((char *)p->payload + optlen, (const u8_t *)arg + pos, seglen, &chksum, &chksum_swapped);
+ 801caf2:	6b7b      	ldr	r3, [r7, #52]	; 0x34
+ 801caf4:	685a      	ldr	r2, [r3, #4]
+ 801caf6:	f897 3026 	ldrb.w	r3, [r7, #38]	; 0x26
+ 801cafa:	18d0      	adds	r0, r2, r3
+ 801cafc:	f8b7 304a 	ldrh.w	r3, [r7, #74]	; 0x4a
+ 801cb00:	68ba      	ldr	r2, [r7, #8]
+ 801cb02:	4413      	add	r3, r2
+ 801cb04:	8bba      	ldrh	r2, [r7, #28]
+ 801cb06:	4619      	mov	r1, r3
+ 801cb08:	f005 f96d 	bl	8021de6 <memcpy>
+ 801cb0c:	e02f      	b.n	801cb6e <tcp_write+0x442>
+       * sent out on the link (as it has to be ACKed by the remote
+       * party) we can safely use PBUF_ROM instead of PBUF_REF here.
+       */
+      struct pbuf *p2;
+#if TCP_OVERSIZE
+      LWIP_ASSERT("oversize == 0", oversize == 0);
+ 801cb0e:	8afb      	ldrh	r3, [r7, #22]
+ 801cb10:	2b00      	cmp	r3, #0
+ 801cb12:	d006      	beq.n	801cb22 <tcp_write+0x3f6>
+ 801cb14:	4b46      	ldr	r3, [pc, #280]	; (801cc30 <tcp_write+0x504>)
+ 801cb16:	f240 2271 	movw	r2, #625	; 0x271
+ 801cb1a:	4949      	ldr	r1, [pc, #292]	; (801cc40 <tcp_write+0x514>)
+ 801cb1c:	4846      	ldr	r0, [pc, #280]	; (801cc38 <tcp_write+0x50c>)
+ 801cb1e:	f004 ff33 	bl	8021988 <iprintf>
+#endif /* TCP_OVERSIZE */
+      if ((p2 = pbuf_alloc(PBUF_TRANSPORT, seglen, PBUF_ROM)) == NULL) {
+ 801cb22:	8bbb      	ldrh	r3, [r7, #28]
+ 801cb24:	2201      	movs	r2, #1
+ 801cb26:	4619      	mov	r1, r3
+ 801cb28:	2036      	movs	r0, #54	; 0x36
+ 801cb2a:	f7fa fcfd 	bl	8017528 <pbuf_alloc>
+ 801cb2e:	61b8      	str	r0, [r7, #24]
+ 801cb30:	69bb      	ldr	r3, [r7, #24]
+ 801cb32:	2b00      	cmp	r3, #0
+ 801cb34:	f000 817b 	beq.w	801ce2e <tcp_write+0x702>
+        chksum_swapped = 1;
+        chksum = SWAP_BYTES_IN_WORD(chksum);
+      }
+#endif /* TCP_CHECKSUM_ON_COPY */
+      /* reference the non-volatile payload data */
+      ((struct pbuf_rom *)p2)->payload = (const u8_t *)arg + pos;
+ 801cb38:	f8b7 304a 	ldrh.w	r3, [r7, #74]	; 0x4a
+ 801cb3c:	68ba      	ldr	r2, [r7, #8]
+ 801cb3e:	441a      	add	r2, r3
+ 801cb40:	69bb      	ldr	r3, [r7, #24]
+ 801cb42:	605a      	str	r2, [r3, #4]
+
+      /* Second, allocate a pbuf for the headers. */
+      if ((p = pbuf_alloc(PBUF_TRANSPORT, optlen, PBUF_RAM)) == NULL) {
+ 801cb44:	f897 3026 	ldrb.w	r3, [r7, #38]	; 0x26
+ 801cb48:	b29b      	uxth	r3, r3
+ 801cb4a:	f44f 7220 	mov.w	r2, #640	; 0x280
+ 801cb4e:	4619      	mov	r1, r3
+ 801cb50:	2036      	movs	r0, #54	; 0x36
+ 801cb52:	f7fa fce9 	bl	8017528 <pbuf_alloc>
+ 801cb56:	6378      	str	r0, [r7, #52]	; 0x34
+ 801cb58:	6b7b      	ldr	r3, [r7, #52]	; 0x34
+ 801cb5a:	2b00      	cmp	r3, #0
+ 801cb5c:	d103      	bne.n	801cb66 <tcp_write+0x43a>
+        /* If allocation fails, we have to deallocate the data pbuf as
+         * well. */
+        pbuf_free(p2);
+ 801cb5e:	69b8      	ldr	r0, [r7, #24]
+ 801cb60:	f7fa ffca 	bl	8017af8 <pbuf_free>
+        LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("tcp_write: could not allocate memory for header pbuf\n"));
+        goto memerr;
+ 801cb64:	e166      	b.n	801ce34 <tcp_write+0x708>
+      }
+      /* Concatenate the headers and data pbufs together. */
+      pbuf_cat(p/*header*/, p2/*data*/);
+ 801cb66:	69b9      	ldr	r1, [r7, #24]
+ 801cb68:	6b78      	ldr	r0, [r7, #52]	; 0x34
+ 801cb6a:	f7fb f893 	bl	8017c94 <pbuf_cat>
+    }
+
+    queuelen += pbuf_clen(p);
+ 801cb6e:	6b78      	ldr	r0, [r7, #52]	; 0x34
+ 801cb70:	f7fb f850 	bl	8017c14 <pbuf_clen>
+ 801cb74:	4603      	mov	r3, r0
+ 801cb76:	461a      	mov	r2, r3
+ 801cb78:	f8b7 3048 	ldrh.w	r3, [r7, #72]	; 0x48
+ 801cb7c:	4413      	add	r3, r2
+ 801cb7e:	f8a7 3048 	strh.w	r3, [r7, #72]	; 0x48
+
+    /* Now that there are more segments queued, we check again if the
+     * length of the queue exceeds the configured maximum or
+     * overflows. */
+    if (queuelen > LWIP_MIN(TCP_SND_QUEUELEN, TCP_SNDQUEUELEN_OVERFLOW)) {
+ 801cb82:	f8b7 3048 	ldrh.w	r3, [r7, #72]	; 0x48
+ 801cb86:	2b10      	cmp	r3, #16
+ 801cb88:	d903      	bls.n	801cb92 <tcp_write+0x466>
+      LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("tcp_write: queue too long %"U16_F" (%d)\n",
+                  queuelen, (int)TCP_SND_QUEUELEN));
+      pbuf_free(p);
+ 801cb8a:	6b78      	ldr	r0, [r7, #52]	; 0x34
+ 801cb8c:	f7fa ffb4 	bl	8017af8 <pbuf_free>
+      goto memerr;
+ 801cb90:	e150      	b.n	801ce34 <tcp_write+0x708>
+    }
+
+    if ((seg = tcp_create_segment(pcb, p, 0, pcb->snd_lbb + pos, optflags)) == NULL) {
+ 801cb92:	68fb      	ldr	r3, [r7, #12]
+ 801cb94:	6dda      	ldr	r2, [r3, #92]	; 0x5c
+ 801cb96:	f8b7 304a 	ldrh.w	r3, [r7, #74]	; 0x4a
+ 801cb9a:	441a      	add	r2, r3
+ 801cb9c:	f897 302b 	ldrb.w	r3, [r7, #43]	; 0x2b
+ 801cba0:	9300      	str	r3, [sp, #0]
+ 801cba2:	4613      	mov	r3, r2
+ 801cba4:	2200      	movs	r2, #0
+ 801cba6:	6b79      	ldr	r1, [r7, #52]	; 0x34
+ 801cba8:	68f8      	ldr	r0, [r7, #12]
+ 801cbaa:	f7ff fc2b 	bl	801c404 <tcp_create_segment>
+ 801cbae:	6578      	str	r0, [r7, #84]	; 0x54
+ 801cbb0:	6d7b      	ldr	r3, [r7, #84]	; 0x54
+ 801cbb2:	2b00      	cmp	r3, #0
+ 801cbb4:	f000 813d 	beq.w	801ce32 <tcp_write+0x706>
+      goto memerr;
+    }
+#if TCP_OVERSIZE_DBGCHECK
+    seg->oversize_left = oversize;
+ 801cbb8:	8afa      	ldrh	r2, [r7, #22]
+ 801cbba:	6d7b      	ldr	r3, [r7, #84]	; 0x54
+ 801cbbc:	815a      	strh	r2, [r3, #10]
+    seg->chksum_swapped = chksum_swapped;
+    seg->flags |= TF_SEG_DATA_CHECKSUMMED;
+#endif /* TCP_CHECKSUM_ON_COPY */
+
+    /* first segment of to-be-queued data? */
+    if (queue == NULL) {
+ 801cbbe:	6cfb      	ldr	r3, [r7, #76]	; 0x4c
+ 801cbc0:	2b00      	cmp	r3, #0
+ 801cbc2:	d102      	bne.n	801cbca <tcp_write+0x49e>
+      queue = seg;
+ 801cbc4:	6d7b      	ldr	r3, [r7, #84]	; 0x54
+ 801cbc6:	64fb      	str	r3, [r7, #76]	; 0x4c
+ 801cbc8:	e00c      	b.n	801cbe4 <tcp_write+0x4b8>
+    } else {
+      /* Attach the segment to the end of the queued segments */
+      LWIP_ASSERT("prev_seg != NULL", prev_seg != NULL);
+ 801cbca:	6d3b      	ldr	r3, [r7, #80]	; 0x50
+ 801cbcc:	2b00      	cmp	r3, #0
+ 801cbce:	d106      	bne.n	801cbde <tcp_write+0x4b2>
+ 801cbd0:	4b17      	ldr	r3, [pc, #92]	; (801cc30 <tcp_write+0x504>)
+ 801cbd2:	f240 22ab 	movw	r2, #683	; 0x2ab
+ 801cbd6:	491b      	ldr	r1, [pc, #108]	; (801cc44 <tcp_write+0x518>)
+ 801cbd8:	4817      	ldr	r0, [pc, #92]	; (801cc38 <tcp_write+0x50c>)
+ 801cbda:	f004 fed5 	bl	8021988 <iprintf>
+      prev_seg->next = seg;
+ 801cbde:	6d3b      	ldr	r3, [r7, #80]	; 0x50
+ 801cbe0:	6d7a      	ldr	r2, [r7, #84]	; 0x54
+ 801cbe2:	601a      	str	r2, [r3, #0]
+    }
+    /* remember last segment of to-be-queued data for next iteration */
+    prev_seg = seg;
+ 801cbe4:	6d7b      	ldr	r3, [r7, #84]	; 0x54
+ 801cbe6:	653b      	str	r3, [r7, #80]	; 0x50
+
+    LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_TRACE, ("tcp_write: queueing %"U32_F":%"U32_F"\n",
+                lwip_ntohl(seg->tcphdr->seqno),
+                lwip_ntohl(seg->tcphdr->seqno) + TCP_TCPLEN(seg)));
+
+    pos += seglen;
+ 801cbe8:	f8b7 204a 	ldrh.w	r2, [r7, #74]	; 0x4a
+ 801cbec:	8bbb      	ldrh	r3, [r7, #28]
+ 801cbee:	4413      	add	r3, r2
+ 801cbf0:	f8a7 304a 	strh.w	r3, [r7, #74]	; 0x4a
+  while (pos < len) {
+ 801cbf4:	f8b7 204a 	ldrh.w	r2, [r7, #74]	; 0x4a
+ 801cbf8:	88fb      	ldrh	r3, [r7, #6]
+ 801cbfa:	429a      	cmp	r2, r3
+ 801cbfc:	f4ff af3a 	bcc.w	801ca74 <tcp_write+0x348>
+  /*
+   * All three segmentation phases were successful. We can commit the
+   * transaction.
+   */
+#if TCP_OVERSIZE_DBGCHECK
+  if ((last_unsent != NULL) && (oversize_add != 0)) {
+ 801cc00:	6c3b      	ldr	r3, [r7, #64]	; 0x40
+ 801cc02:	2b00      	cmp	r3, #0
+ 801cc04:	d00b      	beq.n	801cc1e <tcp_write+0x4f2>
+ 801cc06:	f8b7 305a 	ldrh.w	r3, [r7, #90]	; 0x5a
+ 801cc0a:	2b00      	cmp	r3, #0
+ 801cc0c:	d007      	beq.n	801cc1e <tcp_write+0x4f2>
+    last_unsent->oversize_left += oversize_add;
+ 801cc0e:	6c3b      	ldr	r3, [r7, #64]	; 0x40
+ 801cc10:	895a      	ldrh	r2, [r3, #10]
+ 801cc12:	f8b7 305a 	ldrh.w	r3, [r7, #90]	; 0x5a
+ 801cc16:	4413      	add	r3, r2
+ 801cc18:	b29a      	uxth	r2, r3
+ 801cc1a:	6c3b      	ldr	r3, [r7, #64]	; 0x40
+ 801cc1c:	815a      	strh	r2, [r3, #10]
+  /*
+   * Phase 1: If data has been added to the preallocated tail of
+   * last_unsent, we update the length fields of the pbuf chain.
+   */
+#if TCP_OVERSIZE
+  if (oversize_used > 0) {
+ 801cc1e:	f8b7 3046 	ldrh.w	r3, [r7, #70]	; 0x46
+ 801cc22:	2b00      	cmp	r3, #0
+ 801cc24:	d052      	beq.n	801cccc <tcp_write+0x5a0>
+    struct pbuf *p;
+    /* Bump tot_len of whole chain, len of tail */
+    for (p = last_unsent->p; p; p = p->next) {
+ 801cc26:	6c3b      	ldr	r3, [r7, #64]	; 0x40
+ 801cc28:	685b      	ldr	r3, [r3, #4]
+ 801cc2a:	633b      	str	r3, [r7, #48]	; 0x30
+ 801cc2c:	e02e      	b.n	801cc8c <tcp_write+0x560>
+ 801cc2e:	bf00      	nop
+ 801cc30:	080257b8 	.word	0x080257b8
+ 801cc34:	08025a58 	.word	0x08025a58
+ 801cc38:	0802580c 	.word	0x0802580c
+ 801cc3c:	08025a88 	.word	0x08025a88
+ 801cc40:	08025ac8 	.word	0x08025ac8
+ 801cc44:	08025ad8 	.word	0x08025ad8
+      p->tot_len += oversize_used;
+ 801cc48:	6b3b      	ldr	r3, [r7, #48]	; 0x30
+ 801cc4a:	891a      	ldrh	r2, [r3, #8]
+ 801cc4c:	f8b7 3046 	ldrh.w	r3, [r7, #70]	; 0x46
+ 801cc50:	4413      	add	r3, r2
+ 801cc52:	b29a      	uxth	r2, r3
+ 801cc54:	6b3b      	ldr	r3, [r7, #48]	; 0x30
+ 801cc56:	811a      	strh	r2, [r3, #8]
+      if (p->next == NULL) {
+ 801cc58:	6b3b      	ldr	r3, [r7, #48]	; 0x30
+ 801cc5a:	681b      	ldr	r3, [r3, #0]
+ 801cc5c:	2b00      	cmp	r3, #0
+ 801cc5e:	d112      	bne.n	801cc86 <tcp_write+0x55a>
+        TCP_DATA_COPY((char *)p->payload + p->len, arg, oversize_used, last_unsent);
+ 801cc60:	6b3b      	ldr	r3, [r7, #48]	; 0x30
+ 801cc62:	685b      	ldr	r3, [r3, #4]
+ 801cc64:	6b3a      	ldr	r2, [r7, #48]	; 0x30
+ 801cc66:	8952      	ldrh	r2, [r2, #10]
+ 801cc68:	4413      	add	r3, r2
+ 801cc6a:	f8b7 2046 	ldrh.w	r2, [r7, #70]	; 0x46
+ 801cc6e:	68b9      	ldr	r1, [r7, #8]
+ 801cc70:	4618      	mov	r0, r3
+ 801cc72:	f005 f8b8 	bl	8021de6 <memcpy>
+        p->len += oversize_used;
+ 801cc76:	6b3b      	ldr	r3, [r7, #48]	; 0x30
+ 801cc78:	895a      	ldrh	r2, [r3, #10]
+ 801cc7a:	f8b7 3046 	ldrh.w	r3, [r7, #70]	; 0x46
+ 801cc7e:	4413      	add	r3, r2
+ 801cc80:	b29a      	uxth	r2, r3
+ 801cc82:	6b3b      	ldr	r3, [r7, #48]	; 0x30
+ 801cc84:	815a      	strh	r2, [r3, #10]
+    for (p = last_unsent->p; p; p = p->next) {
+ 801cc86:	6b3b      	ldr	r3, [r7, #48]	; 0x30
+ 801cc88:	681b      	ldr	r3, [r3, #0]
+ 801cc8a:	633b      	str	r3, [r7, #48]	; 0x30
+ 801cc8c:	6b3b      	ldr	r3, [r7, #48]	; 0x30
+ 801cc8e:	2b00      	cmp	r3, #0
+ 801cc90:	d1da      	bne.n	801cc48 <tcp_write+0x51c>
+      }
+    }
+    last_unsent->len += oversize_used;
+ 801cc92:	6c3b      	ldr	r3, [r7, #64]	; 0x40
+ 801cc94:	891a      	ldrh	r2, [r3, #8]
+ 801cc96:	f8b7 3046 	ldrh.w	r3, [r7, #70]	; 0x46
+ 801cc9a:	4413      	add	r3, r2
+ 801cc9c:	b29a      	uxth	r2, r3
+ 801cc9e:	6c3b      	ldr	r3, [r7, #64]	; 0x40
+ 801cca0:	811a      	strh	r2, [r3, #8]
+#if TCP_OVERSIZE_DBGCHECK
+    LWIP_ASSERT("last_unsent->oversize_left >= oversize_used",
+ 801cca2:	6c3b      	ldr	r3, [r7, #64]	; 0x40
+ 801cca4:	895b      	ldrh	r3, [r3, #10]
+ 801cca6:	f8b7 2046 	ldrh.w	r2, [r7, #70]	; 0x46
+ 801ccaa:	429a      	cmp	r2, r3
+ 801ccac:	d906      	bls.n	801ccbc <tcp_write+0x590>
+ 801ccae:	4b78      	ldr	r3, [pc, #480]	; (801ce90 <tcp_write+0x764>)
+ 801ccb0:	f240 22d3 	movw	r2, #723	; 0x2d3
+ 801ccb4:	4977      	ldr	r1, [pc, #476]	; (801ce94 <tcp_write+0x768>)
+ 801ccb6:	4878      	ldr	r0, [pc, #480]	; (801ce98 <tcp_write+0x76c>)
+ 801ccb8:	f004 fe66 	bl	8021988 <iprintf>
+                last_unsent->oversize_left >= oversize_used);
+    last_unsent->oversize_left -= oversize_used;
+ 801ccbc:	6c3b      	ldr	r3, [r7, #64]	; 0x40
+ 801ccbe:	895a      	ldrh	r2, [r3, #10]
+ 801ccc0:	f8b7 3046 	ldrh.w	r3, [r7, #70]	; 0x46
+ 801ccc4:	1ad3      	subs	r3, r2, r3
+ 801ccc6:	b29a      	uxth	r2, r3
+ 801ccc8:	6c3b      	ldr	r3, [r7, #64]	; 0x40
+ 801ccca:	815a      	strh	r2, [r3, #10]
+#endif /* TCP_OVERSIZE_DBGCHECK */
+  }
+  pcb->unsent_oversize = oversize;
+ 801cccc:	8afa      	ldrh	r2, [r7, #22]
+ 801ccce:	68fb      	ldr	r3, [r7, #12]
+ 801ccd0:	f8a3 2068 	strh.w	r2, [r3, #104]	; 0x68
+
+  /*
+   * Phase 2: concat_p can be concatenated onto last_unsent->p, unless we
+   * determined that the last ROM pbuf can be extended to include the new data.
+   */
+  if (concat_p != NULL) {
+ 801ccd4:	6bfb      	ldr	r3, [r7, #60]	; 0x3c
+ 801ccd6:	2b00      	cmp	r3, #0
+ 801ccd8:	d018      	beq.n	801cd0c <tcp_write+0x5e0>
+    LWIP_ASSERT("tcp_write: cannot concatenate when pcb->unsent is empty",
+ 801ccda:	6c3b      	ldr	r3, [r7, #64]	; 0x40
+ 801ccdc:	2b00      	cmp	r3, #0
+ 801ccde:	d106      	bne.n	801ccee <tcp_write+0x5c2>
+ 801cce0:	4b6b      	ldr	r3, [pc, #428]	; (801ce90 <tcp_write+0x764>)
+ 801cce2:	f44f 7238 	mov.w	r2, #736	; 0x2e0
+ 801cce6:	496d      	ldr	r1, [pc, #436]	; (801ce9c <tcp_write+0x770>)
+ 801cce8:	486b      	ldr	r0, [pc, #428]	; (801ce98 <tcp_write+0x76c>)
+ 801ccea:	f004 fe4d 	bl	8021988 <iprintf>
+                (last_unsent != NULL));
+    pbuf_cat(last_unsent->p, concat_p);
+ 801ccee:	6c3b      	ldr	r3, [r7, #64]	; 0x40
+ 801ccf0:	685b      	ldr	r3, [r3, #4]
+ 801ccf2:	6bf9      	ldr	r1, [r7, #60]	; 0x3c
+ 801ccf4:	4618      	mov	r0, r3
+ 801ccf6:	f7fa ffcd 	bl	8017c94 <pbuf_cat>
+    last_unsent->len += concat_p->tot_len;
+ 801ccfa:	6c3b      	ldr	r3, [r7, #64]	; 0x40
+ 801ccfc:	891a      	ldrh	r2, [r3, #8]
+ 801ccfe:	6bfb      	ldr	r3, [r7, #60]	; 0x3c
+ 801cd00:	891b      	ldrh	r3, [r3, #8]
+ 801cd02:	4413      	add	r3, r2
+ 801cd04:	b29a      	uxth	r2, r3
+ 801cd06:	6c3b      	ldr	r3, [r7, #64]	; 0x40
+ 801cd08:	811a      	strh	r2, [r3, #8]
+ 801cd0a:	e03c      	b.n	801cd86 <tcp_write+0x65a>
+  } else if (extendlen > 0) {
+ 801cd0c:	f8b7 305e 	ldrh.w	r3, [r7, #94]	; 0x5e
+ 801cd10:	2b00      	cmp	r3, #0
+ 801cd12:	d038      	beq.n	801cd86 <tcp_write+0x65a>
+    struct pbuf *p;
+    LWIP_ASSERT("tcp_write: extension of reference requires reference",
+ 801cd14:	6c3b      	ldr	r3, [r7, #64]	; 0x40
+ 801cd16:	2b00      	cmp	r3, #0
+ 801cd18:	d003      	beq.n	801cd22 <tcp_write+0x5f6>
+ 801cd1a:	6c3b      	ldr	r3, [r7, #64]	; 0x40
+ 801cd1c:	685b      	ldr	r3, [r3, #4]
+ 801cd1e:	2b00      	cmp	r3, #0
+ 801cd20:	d106      	bne.n	801cd30 <tcp_write+0x604>
+ 801cd22:	4b5b      	ldr	r3, [pc, #364]	; (801ce90 <tcp_write+0x764>)
+ 801cd24:	f240 22e6 	movw	r2, #742	; 0x2e6
+ 801cd28:	495d      	ldr	r1, [pc, #372]	; (801cea0 <tcp_write+0x774>)
+ 801cd2a:	485b      	ldr	r0, [pc, #364]	; (801ce98 <tcp_write+0x76c>)
+ 801cd2c:	f004 fe2c 	bl	8021988 <iprintf>
+                last_unsent != NULL && last_unsent->p != NULL);
+    for (p = last_unsent->p; p->next != NULL; p = p->next) {
+ 801cd30:	6c3b      	ldr	r3, [r7, #64]	; 0x40
+ 801cd32:	685b      	ldr	r3, [r3, #4]
+ 801cd34:	62fb      	str	r3, [r7, #44]	; 0x2c
+ 801cd36:	e00a      	b.n	801cd4e <tcp_write+0x622>
+      p->tot_len += extendlen;
+ 801cd38:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 801cd3a:	891a      	ldrh	r2, [r3, #8]
+ 801cd3c:	f8b7 305e 	ldrh.w	r3, [r7, #94]	; 0x5e
+ 801cd40:	4413      	add	r3, r2
+ 801cd42:	b29a      	uxth	r2, r3
+ 801cd44:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 801cd46:	811a      	strh	r2, [r3, #8]
+    for (p = last_unsent->p; p->next != NULL; p = p->next) {
+ 801cd48:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 801cd4a:	681b      	ldr	r3, [r3, #0]
+ 801cd4c:	62fb      	str	r3, [r7, #44]	; 0x2c
+ 801cd4e:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 801cd50:	681b      	ldr	r3, [r3, #0]
+ 801cd52:	2b00      	cmp	r3, #0
+ 801cd54:	d1f0      	bne.n	801cd38 <tcp_write+0x60c>
+    }
+    p->tot_len += extendlen;
+ 801cd56:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 801cd58:	891a      	ldrh	r2, [r3, #8]
+ 801cd5a:	f8b7 305e 	ldrh.w	r3, [r7, #94]	; 0x5e
+ 801cd5e:	4413      	add	r3, r2
+ 801cd60:	b29a      	uxth	r2, r3
+ 801cd62:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 801cd64:	811a      	strh	r2, [r3, #8]
+    p->len += extendlen;
+ 801cd66:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 801cd68:	895a      	ldrh	r2, [r3, #10]
+ 801cd6a:	f8b7 305e 	ldrh.w	r3, [r7, #94]	; 0x5e
+ 801cd6e:	4413      	add	r3, r2
+ 801cd70:	b29a      	uxth	r2, r3
+ 801cd72:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 801cd74:	815a      	strh	r2, [r3, #10]
+    last_unsent->len += extendlen;
+ 801cd76:	6c3b      	ldr	r3, [r7, #64]	; 0x40
+ 801cd78:	891a      	ldrh	r2, [r3, #8]
+ 801cd7a:	f8b7 305e 	ldrh.w	r3, [r7, #94]	; 0x5e
+ 801cd7e:	4413      	add	r3, r2
+ 801cd80:	b29a      	uxth	r2, r3
+ 801cd82:	6c3b      	ldr	r3, [r7, #64]	; 0x40
+ 801cd84:	811a      	strh	r2, [r3, #8]
+
+  /*
+   * Phase 3: Append queue to pcb->unsent. Queue may be NULL, but that
+   * is harmless
+   */
+  if (last_unsent == NULL) {
+ 801cd86:	6c3b      	ldr	r3, [r7, #64]	; 0x40
+ 801cd88:	2b00      	cmp	r3, #0
+ 801cd8a:	d103      	bne.n	801cd94 <tcp_write+0x668>
+    pcb->unsent = queue;
+ 801cd8c:	68fb      	ldr	r3, [r7, #12]
+ 801cd8e:	6cfa      	ldr	r2, [r7, #76]	; 0x4c
+ 801cd90:	66da      	str	r2, [r3, #108]	; 0x6c
+ 801cd92:	e002      	b.n	801cd9a <tcp_write+0x66e>
+  } else {
+    last_unsent->next = queue;
+ 801cd94:	6c3b      	ldr	r3, [r7, #64]	; 0x40
+ 801cd96:	6cfa      	ldr	r2, [r7, #76]	; 0x4c
+ 801cd98:	601a      	str	r2, [r3, #0]
+  }
+
+  /*
+   * Finally update the pcb state.
+   */
+  pcb->snd_lbb += len;
+ 801cd9a:	68fb      	ldr	r3, [r7, #12]
+ 801cd9c:	6dda      	ldr	r2, [r3, #92]	; 0x5c
+ 801cd9e:	88fb      	ldrh	r3, [r7, #6]
+ 801cda0:	441a      	add	r2, r3
+ 801cda2:	68fb      	ldr	r3, [r7, #12]
+ 801cda4:	65da      	str	r2, [r3, #92]	; 0x5c
+  pcb->snd_buf -= len;
+ 801cda6:	68fb      	ldr	r3, [r7, #12]
+ 801cda8:	f8b3 2064 	ldrh.w	r2, [r3, #100]	; 0x64
+ 801cdac:	88fb      	ldrh	r3, [r7, #6]
+ 801cdae:	1ad3      	subs	r3, r2, r3
+ 801cdb0:	b29a      	uxth	r2, r3
+ 801cdb2:	68fb      	ldr	r3, [r7, #12]
+ 801cdb4:	f8a3 2064 	strh.w	r2, [r3, #100]	; 0x64
+  pcb->snd_queuelen = queuelen;
+ 801cdb8:	68fb      	ldr	r3, [r7, #12]
+ 801cdba:	f8b7 2048 	ldrh.w	r2, [r7, #72]	; 0x48
+ 801cdbe:	f8a3 2066 	strh.w	r2, [r3, #102]	; 0x66
+
+  LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_write: %"S16_F" (after enqueued)\n",
+                               pcb->snd_queuelen));
+  if (pcb->snd_queuelen != 0) {
+ 801cdc2:	68fb      	ldr	r3, [r7, #12]
+ 801cdc4:	f8b3 3066 	ldrh.w	r3, [r3, #102]	; 0x66
+ 801cdc8:	2b00      	cmp	r3, #0
+ 801cdca:	d00e      	beq.n	801cdea <tcp_write+0x6be>
+    LWIP_ASSERT("tcp_write: valid queue length",
+ 801cdcc:	68fb      	ldr	r3, [r7, #12]
+ 801cdce:	6f1b      	ldr	r3, [r3, #112]	; 0x70
+ 801cdd0:	2b00      	cmp	r3, #0
+ 801cdd2:	d10a      	bne.n	801cdea <tcp_write+0x6be>
+ 801cdd4:	68fb      	ldr	r3, [r7, #12]
+ 801cdd6:	6edb      	ldr	r3, [r3, #108]	; 0x6c
+ 801cdd8:	2b00      	cmp	r3, #0
+ 801cdda:	d106      	bne.n	801cdea <tcp_write+0x6be>
+ 801cddc:	4b2c      	ldr	r3, [pc, #176]	; (801ce90 <tcp_write+0x764>)
+ 801cdde:	f240 3212 	movw	r2, #786	; 0x312
+ 801cde2:	4930      	ldr	r1, [pc, #192]	; (801cea4 <tcp_write+0x778>)
+ 801cde4:	482c      	ldr	r0, [pc, #176]	; (801ce98 <tcp_write+0x76c>)
+ 801cde6:	f004 fdcf 	bl	8021988 <iprintf>
+                pcb->unacked != NULL || pcb->unsent != NULL);
+  }
+
+  /* Set the PSH flag in the last segment that we enqueued. */
+  if (seg != NULL && seg->tcphdr != NULL && ((apiflags & TCP_WRITE_FLAG_MORE) == 0)) {
+ 801cdea:	6d7b      	ldr	r3, [r7, #84]	; 0x54
+ 801cdec:	2b00      	cmp	r3, #0
+ 801cdee:	d016      	beq.n	801ce1e <tcp_write+0x6f2>
+ 801cdf0:	6d7b      	ldr	r3, [r7, #84]	; 0x54
+ 801cdf2:	691b      	ldr	r3, [r3, #16]
+ 801cdf4:	2b00      	cmp	r3, #0
+ 801cdf6:	d012      	beq.n	801ce1e <tcp_write+0x6f2>
+ 801cdf8:	797b      	ldrb	r3, [r7, #5]
+ 801cdfa:	f003 0302 	and.w	r3, r3, #2
+ 801cdfe:	2b00      	cmp	r3, #0
+ 801ce00:	d10d      	bne.n	801ce1e <tcp_write+0x6f2>
+    TCPH_SET_FLAG(seg->tcphdr, TCP_PSH);
+ 801ce02:	6d7b      	ldr	r3, [r7, #84]	; 0x54
+ 801ce04:	691b      	ldr	r3, [r3, #16]
+ 801ce06:	899b      	ldrh	r3, [r3, #12]
+ 801ce08:	b29c      	uxth	r4, r3
+ 801ce0a:	2008      	movs	r0, #8
+ 801ce0c:	f7f9 f898 	bl	8015f40 <lwip_htons>
+ 801ce10:	4603      	mov	r3, r0
+ 801ce12:	461a      	mov	r2, r3
+ 801ce14:	6d7b      	ldr	r3, [r7, #84]	; 0x54
+ 801ce16:	691b      	ldr	r3, [r3, #16]
+ 801ce18:	4322      	orrs	r2, r4
+ 801ce1a:	b292      	uxth	r2, r2
+ 801ce1c:	819a      	strh	r2, [r3, #12]
+  }
+
+  return ERR_OK;
+ 801ce1e:	2300      	movs	r3, #0
+ 801ce20:	e031      	b.n	801ce86 <tcp_write+0x75a>
+          goto memerr;
+ 801ce22:	bf00      	nop
+ 801ce24:	e006      	b.n	801ce34 <tcp_write+0x708>
+            goto memerr;
+ 801ce26:	bf00      	nop
+ 801ce28:	e004      	b.n	801ce34 <tcp_write+0x708>
+        goto memerr;
+ 801ce2a:	bf00      	nop
+ 801ce2c:	e002      	b.n	801ce34 <tcp_write+0x708>
+        goto memerr;
+ 801ce2e:	bf00      	nop
+ 801ce30:	e000      	b.n	801ce34 <tcp_write+0x708>
+      goto memerr;
+ 801ce32:	bf00      	nop
+memerr:
+  tcp_set_flags(pcb, TF_NAGLEMEMERR);
+ 801ce34:	68fb      	ldr	r3, [r7, #12]
+ 801ce36:	8b5b      	ldrh	r3, [r3, #26]
+ 801ce38:	f043 0380 	orr.w	r3, r3, #128	; 0x80
+ 801ce3c:	b29a      	uxth	r2, r3
+ 801ce3e:	68fb      	ldr	r3, [r7, #12]
+ 801ce40:	835a      	strh	r2, [r3, #26]
+  TCP_STATS_INC(tcp.memerr);
+
+  if (concat_p != NULL) {
+ 801ce42:	6bfb      	ldr	r3, [r7, #60]	; 0x3c
+ 801ce44:	2b00      	cmp	r3, #0
+ 801ce46:	d002      	beq.n	801ce4e <tcp_write+0x722>
+    pbuf_free(concat_p);
+ 801ce48:	6bf8      	ldr	r0, [r7, #60]	; 0x3c
+ 801ce4a:	f7fa fe55 	bl	8017af8 <pbuf_free>
+  }
+  if (queue != NULL) {
+ 801ce4e:	6cfb      	ldr	r3, [r7, #76]	; 0x4c
+ 801ce50:	2b00      	cmp	r3, #0
+ 801ce52:	d002      	beq.n	801ce5a <tcp_write+0x72e>
+    tcp_segs_free(queue);
+ 801ce54:	6cf8      	ldr	r0, [r7, #76]	; 0x4c
+ 801ce56:	f7fc fb0f 	bl	8019478 <tcp_segs_free>
+  }
+  if (pcb->snd_queuelen != 0) {
+ 801ce5a:	68fb      	ldr	r3, [r7, #12]
+ 801ce5c:	f8b3 3066 	ldrh.w	r3, [r3, #102]	; 0x66
+ 801ce60:	2b00      	cmp	r3, #0
+ 801ce62:	d00e      	beq.n	801ce82 <tcp_write+0x756>
+    LWIP_ASSERT("tcp_write: valid queue length", pcb->unacked != NULL ||
+ 801ce64:	68fb      	ldr	r3, [r7, #12]
+ 801ce66:	6f1b      	ldr	r3, [r3, #112]	; 0x70
+ 801ce68:	2b00      	cmp	r3, #0
+ 801ce6a:	d10a      	bne.n	801ce82 <tcp_write+0x756>
+ 801ce6c:	68fb      	ldr	r3, [r7, #12]
+ 801ce6e:	6edb      	ldr	r3, [r3, #108]	; 0x6c
+ 801ce70:	2b00      	cmp	r3, #0
+ 801ce72:	d106      	bne.n	801ce82 <tcp_write+0x756>
+ 801ce74:	4b06      	ldr	r3, [pc, #24]	; (801ce90 <tcp_write+0x764>)
+ 801ce76:	f240 3227 	movw	r2, #807	; 0x327
+ 801ce7a:	490a      	ldr	r1, [pc, #40]	; (801cea4 <tcp_write+0x778>)
+ 801ce7c:	4806      	ldr	r0, [pc, #24]	; (801ce98 <tcp_write+0x76c>)
+ 801ce7e:	f004 fd83 	bl	8021988 <iprintf>
+                pcb->unsent != NULL);
+  }
+  LWIP_DEBUGF(TCP_QLEN_DEBUG | LWIP_DBG_STATE, ("tcp_write: %"S16_F" (with mem err)\n", pcb->snd_queuelen));
+  return ERR_MEM;
+ 801ce82:	f04f 33ff 	mov.w	r3, #4294967295
+}
+ 801ce86:	4618      	mov	r0, r3
+ 801ce88:	3764      	adds	r7, #100	; 0x64
+ 801ce8a:	46bd      	mov	sp, r7
+ 801ce8c:	bd90      	pop	{r4, r7, pc}
+ 801ce8e:	bf00      	nop
+ 801ce90:	080257b8 	.word	0x080257b8
+ 801ce94:	08025aec 	.word	0x08025aec
+ 801ce98:	0802580c 	.word	0x0802580c
+ 801ce9c:	08025b18 	.word	0x08025b18
+ 801cea0:	08025b50 	.word	0x08025b50
+ 801cea4:	08025b88 	.word	0x08025b88
+
+0801cea8 <tcp_split_unsent_seg>:
+ * @param pcb the tcp_pcb for which to split the unsent head
+ * @param split the amount of payload to remain in the head
+ */
+err_t
+tcp_split_unsent_seg(struct tcp_pcb *pcb, u16_t split)
+{
+ 801cea8:	b590      	push	{r4, r7, lr}
+ 801ceaa:	b08b      	sub	sp, #44	; 0x2c
+ 801ceac:	af02      	add	r7, sp, #8
+ 801ceae:	6078      	str	r0, [r7, #4]
+ 801ceb0:	460b      	mov	r3, r1
+ 801ceb2:	807b      	strh	r3, [r7, #2]
+  struct tcp_seg *seg = NULL, *useg = NULL;
+ 801ceb4:	2300      	movs	r3, #0
+ 801ceb6:	61bb      	str	r3, [r7, #24]
+ 801ceb8:	2300      	movs	r3, #0
+ 801ceba:	617b      	str	r3, [r7, #20]
+  struct pbuf *p = NULL;
+ 801cebc:	2300      	movs	r3, #0
+ 801cebe:	613b      	str	r3, [r7, #16]
+  u16_t chksum = 0;
+  u8_t chksum_swapped = 0;
+  struct pbuf *q;
+#endif /* TCP_CHECKSUM_ON_COPY */
+
+  LWIP_ASSERT("tcp_split_unsent_seg: invalid pcb", pcb != NULL);
+ 801cec0:	687b      	ldr	r3, [r7, #4]
+ 801cec2:	2b00      	cmp	r3, #0
+ 801cec4:	d106      	bne.n	801ced4 <tcp_split_unsent_seg+0x2c>
+ 801cec6:	4b97      	ldr	r3, [pc, #604]	; (801d124 <tcp_split_unsent_seg+0x27c>)
+ 801cec8:	f240 324b 	movw	r2, #843	; 0x34b
+ 801cecc:	4996      	ldr	r1, [pc, #600]	; (801d128 <tcp_split_unsent_seg+0x280>)
+ 801cece:	4897      	ldr	r0, [pc, #604]	; (801d12c <tcp_split_unsent_seg+0x284>)
+ 801ced0:	f004 fd5a 	bl	8021988 <iprintf>
+
+  useg = pcb->unsent;
+ 801ced4:	687b      	ldr	r3, [r7, #4]
+ 801ced6:	6edb      	ldr	r3, [r3, #108]	; 0x6c
+ 801ced8:	617b      	str	r3, [r7, #20]
+  if (useg == NULL) {
+ 801ceda:	697b      	ldr	r3, [r7, #20]
+ 801cedc:	2b00      	cmp	r3, #0
+ 801cede:	d102      	bne.n	801cee6 <tcp_split_unsent_seg+0x3e>
+    return ERR_MEM;
+ 801cee0:	f04f 33ff 	mov.w	r3, #4294967295
+ 801cee4:	e119      	b.n	801d11a <tcp_split_unsent_seg+0x272>
+  }
+
+  if (split == 0) {
+ 801cee6:	887b      	ldrh	r3, [r7, #2]
+ 801cee8:	2b00      	cmp	r3, #0
+ 801ceea:	d109      	bne.n	801cf00 <tcp_split_unsent_seg+0x58>
+    LWIP_ASSERT("Can't split segment into length 0", 0);
+ 801ceec:	4b8d      	ldr	r3, [pc, #564]	; (801d124 <tcp_split_unsent_seg+0x27c>)
+ 801ceee:	f240 3253 	movw	r2, #851	; 0x353
+ 801cef2:	498f      	ldr	r1, [pc, #572]	; (801d130 <tcp_split_unsent_seg+0x288>)
+ 801cef4:	488d      	ldr	r0, [pc, #564]	; (801d12c <tcp_split_unsent_seg+0x284>)
+ 801cef6:	f004 fd47 	bl	8021988 <iprintf>
+    return ERR_VAL;
+ 801cefa:	f06f 0305 	mvn.w	r3, #5
+ 801cefe:	e10c      	b.n	801d11a <tcp_split_unsent_seg+0x272>
+  }
+
+  if (useg->len <= split) {
+ 801cf00:	697b      	ldr	r3, [r7, #20]
+ 801cf02:	891b      	ldrh	r3, [r3, #8]
+ 801cf04:	887a      	ldrh	r2, [r7, #2]
+ 801cf06:	429a      	cmp	r2, r3
+ 801cf08:	d301      	bcc.n	801cf0e <tcp_split_unsent_seg+0x66>
+    return ERR_OK;
+ 801cf0a:	2300      	movs	r3, #0
+ 801cf0c:	e105      	b.n	801d11a <tcp_split_unsent_seg+0x272>
+  }
+
+  LWIP_ASSERT("split <= mss", split <= pcb->mss);
+ 801cf0e:	687b      	ldr	r3, [r7, #4]
+ 801cf10:	8e5b      	ldrh	r3, [r3, #50]	; 0x32
+ 801cf12:	887a      	ldrh	r2, [r7, #2]
+ 801cf14:	429a      	cmp	r2, r3
+ 801cf16:	d906      	bls.n	801cf26 <tcp_split_unsent_seg+0x7e>
+ 801cf18:	4b82      	ldr	r3, [pc, #520]	; (801d124 <tcp_split_unsent_seg+0x27c>)
+ 801cf1a:	f240 325b 	movw	r2, #859	; 0x35b
+ 801cf1e:	4985      	ldr	r1, [pc, #532]	; (801d134 <tcp_split_unsent_seg+0x28c>)
+ 801cf20:	4882      	ldr	r0, [pc, #520]	; (801d12c <tcp_split_unsent_seg+0x284>)
+ 801cf22:	f004 fd31 	bl	8021988 <iprintf>
+  LWIP_ASSERT("useg->len > 0", useg->len > 0);
+ 801cf26:	697b      	ldr	r3, [r7, #20]
+ 801cf28:	891b      	ldrh	r3, [r3, #8]
+ 801cf2a:	2b00      	cmp	r3, #0
+ 801cf2c:	d106      	bne.n	801cf3c <tcp_split_unsent_seg+0x94>
+ 801cf2e:	4b7d      	ldr	r3, [pc, #500]	; (801d124 <tcp_split_unsent_seg+0x27c>)
+ 801cf30:	f44f 7257 	mov.w	r2, #860	; 0x35c
+ 801cf34:	4980      	ldr	r1, [pc, #512]	; (801d138 <tcp_split_unsent_seg+0x290>)
+ 801cf36:	487d      	ldr	r0, [pc, #500]	; (801d12c <tcp_split_unsent_seg+0x284>)
+ 801cf38:	f004 fd26 	bl	8021988 <iprintf>
+   * to split this packet so we may actually exceed the max value by
+   * one!
+   */
+  LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_enqueue: split_unsent_seg: %u\n", (unsigned int)pcb->snd_queuelen));
+
+  optflags = useg->flags;
+ 801cf3c:	697b      	ldr	r3, [r7, #20]
+ 801cf3e:	7b1b      	ldrb	r3, [r3, #12]
+ 801cf40:	73fb      	strb	r3, [r7, #15]
+#if TCP_CHECKSUM_ON_COPY
+  /* Remove since checksum is not stored until after tcp_create_segment() */
+  optflags &= ~TF_SEG_DATA_CHECKSUMMED;
+#endif /* TCP_CHECKSUM_ON_COPY */
+  optlen = LWIP_TCP_OPT_LENGTH(optflags);
+ 801cf42:	7bfb      	ldrb	r3, [r7, #15]
+ 801cf44:	009b      	lsls	r3, r3, #2
+ 801cf46:	b2db      	uxtb	r3, r3
+ 801cf48:	f003 0304 	and.w	r3, r3, #4
+ 801cf4c:	73bb      	strb	r3, [r7, #14]
+  remainder = useg->len - split;
+ 801cf4e:	697b      	ldr	r3, [r7, #20]
+ 801cf50:	891a      	ldrh	r2, [r3, #8]
+ 801cf52:	887b      	ldrh	r3, [r7, #2]
+ 801cf54:	1ad3      	subs	r3, r2, r3
+ 801cf56:	81bb      	strh	r3, [r7, #12]
+
+  /* Create new pbuf for the remainder of the split */
+  p = pbuf_alloc(PBUF_TRANSPORT, remainder + optlen, PBUF_RAM);
+ 801cf58:	7bbb      	ldrb	r3, [r7, #14]
+ 801cf5a:	b29a      	uxth	r2, r3
+ 801cf5c:	89bb      	ldrh	r3, [r7, #12]
+ 801cf5e:	4413      	add	r3, r2
+ 801cf60:	b29b      	uxth	r3, r3
+ 801cf62:	f44f 7220 	mov.w	r2, #640	; 0x280
+ 801cf66:	4619      	mov	r1, r3
+ 801cf68:	2036      	movs	r0, #54	; 0x36
+ 801cf6a:	f7fa fadd 	bl	8017528 <pbuf_alloc>
+ 801cf6e:	6138      	str	r0, [r7, #16]
+  if (p == NULL) {
+ 801cf70:	693b      	ldr	r3, [r7, #16]
+ 801cf72:	2b00      	cmp	r3, #0
+ 801cf74:	f000 80ba 	beq.w	801d0ec <tcp_split_unsent_seg+0x244>
+                ("tcp_split_unsent_seg: could not allocate memory for pbuf remainder %u\n", remainder));
+    goto memerr;
+  }
+
+  /* Offset into the original pbuf is past TCP/IP headers, options, and split amount */
+  offset = useg->p->tot_len - useg->len + split;
+ 801cf78:	697b      	ldr	r3, [r7, #20]
+ 801cf7a:	685b      	ldr	r3, [r3, #4]
+ 801cf7c:	891a      	ldrh	r2, [r3, #8]
+ 801cf7e:	697b      	ldr	r3, [r7, #20]
+ 801cf80:	891b      	ldrh	r3, [r3, #8]
+ 801cf82:	1ad3      	subs	r3, r2, r3
+ 801cf84:	b29a      	uxth	r2, r3
+ 801cf86:	887b      	ldrh	r3, [r7, #2]
+ 801cf88:	4413      	add	r3, r2
+ 801cf8a:	817b      	strh	r3, [r7, #10]
+  /* Copy remainder into new pbuf, headers and options will not be filled out */
+  if (pbuf_copy_partial(useg->p, (u8_t *)p->payload + optlen, remainder, offset ) != remainder) {
+ 801cf8c:	697b      	ldr	r3, [r7, #20]
+ 801cf8e:	6858      	ldr	r0, [r3, #4]
+ 801cf90:	693b      	ldr	r3, [r7, #16]
+ 801cf92:	685a      	ldr	r2, [r3, #4]
+ 801cf94:	7bbb      	ldrb	r3, [r7, #14]
+ 801cf96:	18d1      	adds	r1, r2, r3
+ 801cf98:	897b      	ldrh	r3, [r7, #10]
+ 801cf9a:	89ba      	ldrh	r2, [r7, #12]
+ 801cf9c:	f7fa ffa2 	bl	8017ee4 <pbuf_copy_partial>
+ 801cfa0:	4603      	mov	r3, r0
+ 801cfa2:	461a      	mov	r2, r3
+ 801cfa4:	89bb      	ldrh	r3, [r7, #12]
+ 801cfa6:	4293      	cmp	r3, r2
+ 801cfa8:	f040 80a2 	bne.w	801d0f0 <tcp_split_unsent_seg+0x248>
+#endif /* TCP_CHECKSUM_ON_COPY */
+
+  /* Options are created when calling tcp_output() */
+
+  /* Migrate flags from original segment */
+  split_flags = TCPH_FLAGS(useg->tcphdr);
+ 801cfac:	697b      	ldr	r3, [r7, #20]
+ 801cfae:	691b      	ldr	r3, [r3, #16]
+ 801cfb0:	899b      	ldrh	r3, [r3, #12]
+ 801cfb2:	b29b      	uxth	r3, r3
+ 801cfb4:	4618      	mov	r0, r3
+ 801cfb6:	f7f8 ffc3 	bl	8015f40 <lwip_htons>
+ 801cfba:	4603      	mov	r3, r0
+ 801cfbc:	b2db      	uxtb	r3, r3
+ 801cfbe:	f003 033f 	and.w	r3, r3, #63	; 0x3f
+ 801cfc2:	77fb      	strb	r3, [r7, #31]
+  remainder_flags = 0; /* ACK added in tcp_output() */
+ 801cfc4:	2300      	movs	r3, #0
+ 801cfc6:	77bb      	strb	r3, [r7, #30]
+
+  if (split_flags & TCP_PSH) {
+ 801cfc8:	7ffb      	ldrb	r3, [r7, #31]
+ 801cfca:	f003 0308 	and.w	r3, r3, #8
+ 801cfce:	2b00      	cmp	r3, #0
+ 801cfd0:	d007      	beq.n	801cfe2 <tcp_split_unsent_seg+0x13a>
+    split_flags &= ~TCP_PSH;
+ 801cfd2:	7ffb      	ldrb	r3, [r7, #31]
+ 801cfd4:	f023 0308 	bic.w	r3, r3, #8
+ 801cfd8:	77fb      	strb	r3, [r7, #31]
+    remainder_flags |= TCP_PSH;
+ 801cfda:	7fbb      	ldrb	r3, [r7, #30]
+ 801cfdc:	f043 0308 	orr.w	r3, r3, #8
+ 801cfe0:	77bb      	strb	r3, [r7, #30]
+  }
+  if (split_flags & TCP_FIN) {
+ 801cfe2:	7ffb      	ldrb	r3, [r7, #31]
+ 801cfe4:	f003 0301 	and.w	r3, r3, #1
+ 801cfe8:	2b00      	cmp	r3, #0
+ 801cfea:	d007      	beq.n	801cffc <tcp_split_unsent_seg+0x154>
+    split_flags &= ~TCP_FIN;
+ 801cfec:	7ffb      	ldrb	r3, [r7, #31]
+ 801cfee:	f023 0301 	bic.w	r3, r3, #1
+ 801cff2:	77fb      	strb	r3, [r7, #31]
+    remainder_flags |= TCP_FIN;
+ 801cff4:	7fbb      	ldrb	r3, [r7, #30]
+ 801cff6:	f043 0301 	orr.w	r3, r3, #1
+ 801cffa:	77bb      	strb	r3, [r7, #30]
+  }
+  /* SYN should be left on split, RST should not be present with data */
+
+  seg = tcp_create_segment(pcb, p, remainder_flags, lwip_ntohl(useg->tcphdr->seqno) + split, optflags);
+ 801cffc:	697b      	ldr	r3, [r7, #20]
+ 801cffe:	691b      	ldr	r3, [r3, #16]
+ 801d000:	685b      	ldr	r3, [r3, #4]
+ 801d002:	4618      	mov	r0, r3
+ 801d004:	f7f8 ffb1 	bl	8015f6a <lwip_htonl>
+ 801d008:	4602      	mov	r2, r0
+ 801d00a:	887b      	ldrh	r3, [r7, #2]
+ 801d00c:	18d1      	adds	r1, r2, r3
+ 801d00e:	7fba      	ldrb	r2, [r7, #30]
+ 801d010:	7bfb      	ldrb	r3, [r7, #15]
+ 801d012:	9300      	str	r3, [sp, #0]
+ 801d014:	460b      	mov	r3, r1
+ 801d016:	6939      	ldr	r1, [r7, #16]
+ 801d018:	6878      	ldr	r0, [r7, #4]
+ 801d01a:	f7ff f9f3 	bl	801c404 <tcp_create_segment>
+ 801d01e:	61b8      	str	r0, [r7, #24]
+  if (seg == NULL) {
+ 801d020:	69bb      	ldr	r3, [r7, #24]
+ 801d022:	2b00      	cmp	r3, #0
+ 801d024:	d066      	beq.n	801d0f4 <tcp_split_unsent_seg+0x24c>
+  seg->chksum_swapped = chksum_swapped;
+  seg->flags |= TF_SEG_DATA_CHECKSUMMED;
+#endif /* TCP_CHECKSUM_ON_COPY */
+
+  /* Remove this segment from the queue since trimming it may free pbufs */
+  pcb->snd_queuelen -= pbuf_clen(useg->p);
+ 801d026:	697b      	ldr	r3, [r7, #20]
+ 801d028:	685b      	ldr	r3, [r3, #4]
+ 801d02a:	4618      	mov	r0, r3
+ 801d02c:	f7fa fdf2 	bl	8017c14 <pbuf_clen>
+ 801d030:	4603      	mov	r3, r0
+ 801d032:	461a      	mov	r2, r3
+ 801d034:	687b      	ldr	r3, [r7, #4]
+ 801d036:	f8b3 3066 	ldrh.w	r3, [r3, #102]	; 0x66
+ 801d03a:	1a9b      	subs	r3, r3, r2
+ 801d03c:	b29a      	uxth	r2, r3
+ 801d03e:	687b      	ldr	r3, [r7, #4]
+ 801d040:	f8a3 2066 	strh.w	r2, [r3, #102]	; 0x66
+
+  /* Trim the original pbuf into our split size.  At this point our remainder segment must be setup
+  successfully because we are modifying the original segment */
+  pbuf_realloc(useg->p, useg->p->tot_len - remainder);
+ 801d044:	697b      	ldr	r3, [r7, #20]
+ 801d046:	6858      	ldr	r0, [r3, #4]
+ 801d048:	697b      	ldr	r3, [r7, #20]
+ 801d04a:	685b      	ldr	r3, [r3, #4]
+ 801d04c:	891a      	ldrh	r2, [r3, #8]
+ 801d04e:	89bb      	ldrh	r3, [r7, #12]
+ 801d050:	1ad3      	subs	r3, r2, r3
+ 801d052:	b29b      	uxth	r3, r3
+ 801d054:	4619      	mov	r1, r3
+ 801d056:	f7fa fbc9 	bl	80177ec <pbuf_realloc>
+  useg->len -= remainder;
+ 801d05a:	697b      	ldr	r3, [r7, #20]
+ 801d05c:	891a      	ldrh	r2, [r3, #8]
+ 801d05e:	89bb      	ldrh	r3, [r7, #12]
+ 801d060:	1ad3      	subs	r3, r2, r3
+ 801d062:	b29a      	uxth	r2, r3
+ 801d064:	697b      	ldr	r3, [r7, #20]
+ 801d066:	811a      	strh	r2, [r3, #8]
+  TCPH_SET_FLAG(useg->tcphdr, split_flags);
+ 801d068:	697b      	ldr	r3, [r7, #20]
+ 801d06a:	691b      	ldr	r3, [r3, #16]
+ 801d06c:	899b      	ldrh	r3, [r3, #12]
+ 801d06e:	b29c      	uxth	r4, r3
+ 801d070:	7ffb      	ldrb	r3, [r7, #31]
+ 801d072:	b29b      	uxth	r3, r3
+ 801d074:	4618      	mov	r0, r3
+ 801d076:	f7f8 ff63 	bl	8015f40 <lwip_htons>
+ 801d07a:	4603      	mov	r3, r0
+ 801d07c:	461a      	mov	r2, r3
+ 801d07e:	697b      	ldr	r3, [r7, #20]
+ 801d080:	691b      	ldr	r3, [r3, #16]
+ 801d082:	4322      	orrs	r2, r4
+ 801d084:	b292      	uxth	r2, r2
+ 801d086:	819a      	strh	r2, [r3, #12]
+#if TCP_OVERSIZE_DBGCHECK
+  /* By trimming, realloc may have actually shrunk the pbuf, so clear oversize_left */
+  useg->oversize_left = 0;
+ 801d088:	697b      	ldr	r3, [r7, #20]
+ 801d08a:	2200      	movs	r2, #0
+ 801d08c:	815a      	strh	r2, [r3, #10]
+#endif /* TCP_OVERSIZE_DBGCHECK */
+
+  /* Add back to the queue with new trimmed pbuf */
+  pcb->snd_queuelen += pbuf_clen(useg->p);
+ 801d08e:	697b      	ldr	r3, [r7, #20]
+ 801d090:	685b      	ldr	r3, [r3, #4]
+ 801d092:	4618      	mov	r0, r3
+ 801d094:	f7fa fdbe 	bl	8017c14 <pbuf_clen>
+ 801d098:	4603      	mov	r3, r0
+ 801d09a:	461a      	mov	r2, r3
+ 801d09c:	687b      	ldr	r3, [r7, #4]
+ 801d09e:	f8b3 3066 	ldrh.w	r3, [r3, #102]	; 0x66
+ 801d0a2:	4413      	add	r3, r2
+ 801d0a4:	b29a      	uxth	r2, r3
+ 801d0a6:	687b      	ldr	r3, [r7, #4]
+ 801d0a8:	f8a3 2066 	strh.w	r2, [r3, #102]	; 0x66
+#endif /* TCP_CHECKSUM_ON_COPY */
+
+  /* Update number of segments on the queues. Note that length now may
+   * exceed TCP_SND_QUEUELEN! We don't have to touch pcb->snd_buf
+   * because the total amount of data is constant when packet is split */
+  pcb->snd_queuelen += pbuf_clen(seg->p);
+ 801d0ac:	69bb      	ldr	r3, [r7, #24]
+ 801d0ae:	685b      	ldr	r3, [r3, #4]
+ 801d0b0:	4618      	mov	r0, r3
+ 801d0b2:	f7fa fdaf 	bl	8017c14 <pbuf_clen>
+ 801d0b6:	4603      	mov	r3, r0
+ 801d0b8:	461a      	mov	r2, r3
+ 801d0ba:	687b      	ldr	r3, [r7, #4]
+ 801d0bc:	f8b3 3066 	ldrh.w	r3, [r3, #102]	; 0x66
+ 801d0c0:	4413      	add	r3, r2
+ 801d0c2:	b29a      	uxth	r2, r3
+ 801d0c4:	687b      	ldr	r3, [r7, #4]
+ 801d0c6:	f8a3 2066 	strh.w	r2, [r3, #102]	; 0x66
+
+  /* Finally insert remainder into queue after split (which stays head) */
+  seg->next = useg->next;
+ 801d0ca:	697b      	ldr	r3, [r7, #20]
+ 801d0cc:	681a      	ldr	r2, [r3, #0]
+ 801d0ce:	69bb      	ldr	r3, [r7, #24]
+ 801d0d0:	601a      	str	r2, [r3, #0]
+  useg->next = seg;
+ 801d0d2:	697b      	ldr	r3, [r7, #20]
+ 801d0d4:	69ba      	ldr	r2, [r7, #24]
+ 801d0d6:	601a      	str	r2, [r3, #0]
+
+#if TCP_OVERSIZE
+  /* If remainder is last segment on the unsent, ensure we clear the oversize amount
+   * because the remainder is always sized to the exact remaining amount */
+  if (seg->next == NULL) {
+ 801d0d8:	69bb      	ldr	r3, [r7, #24]
+ 801d0da:	681b      	ldr	r3, [r3, #0]
+ 801d0dc:	2b00      	cmp	r3, #0
+ 801d0de:	d103      	bne.n	801d0e8 <tcp_split_unsent_seg+0x240>
+    pcb->unsent_oversize = 0;
+ 801d0e0:	687b      	ldr	r3, [r7, #4]
+ 801d0e2:	2200      	movs	r2, #0
+ 801d0e4:	f8a3 2068 	strh.w	r2, [r3, #104]	; 0x68
+  }
+#endif /* TCP_OVERSIZE */
+
+  return ERR_OK;
+ 801d0e8:	2300      	movs	r3, #0
+ 801d0ea:	e016      	b.n	801d11a <tcp_split_unsent_seg+0x272>
+    goto memerr;
+ 801d0ec:	bf00      	nop
+ 801d0ee:	e002      	b.n	801d0f6 <tcp_split_unsent_seg+0x24e>
+    goto memerr;
+ 801d0f0:	bf00      	nop
+ 801d0f2:	e000      	b.n	801d0f6 <tcp_split_unsent_seg+0x24e>
+    goto memerr;
+ 801d0f4:	bf00      	nop
+memerr:
+  TCP_STATS_INC(tcp.memerr);
+
+  LWIP_ASSERT("seg == NULL", seg == NULL);
+ 801d0f6:	69bb      	ldr	r3, [r7, #24]
+ 801d0f8:	2b00      	cmp	r3, #0
+ 801d0fa:	d006      	beq.n	801d10a <tcp_split_unsent_seg+0x262>
+ 801d0fc:	4b09      	ldr	r3, [pc, #36]	; (801d124 <tcp_split_unsent_seg+0x27c>)
+ 801d0fe:	f44f 7276 	mov.w	r2, #984	; 0x3d8
+ 801d102:	490e      	ldr	r1, [pc, #56]	; (801d13c <tcp_split_unsent_seg+0x294>)
+ 801d104:	4809      	ldr	r0, [pc, #36]	; (801d12c <tcp_split_unsent_seg+0x284>)
+ 801d106:	f004 fc3f 	bl	8021988 <iprintf>
+  if (p != NULL) {
+ 801d10a:	693b      	ldr	r3, [r7, #16]
+ 801d10c:	2b00      	cmp	r3, #0
+ 801d10e:	d002      	beq.n	801d116 <tcp_split_unsent_seg+0x26e>
+    pbuf_free(p);
+ 801d110:	6938      	ldr	r0, [r7, #16]
+ 801d112:	f7fa fcf1 	bl	8017af8 <pbuf_free>
+  }
+
+  return ERR_MEM;
+ 801d116:	f04f 33ff 	mov.w	r3, #4294967295
+}
+ 801d11a:	4618      	mov	r0, r3
+ 801d11c:	3724      	adds	r7, #36	; 0x24
+ 801d11e:	46bd      	mov	sp, r7
+ 801d120:	bd90      	pop	{r4, r7, pc}
+ 801d122:	bf00      	nop
+ 801d124:	080257b8 	.word	0x080257b8
+ 801d128:	08025ba8 	.word	0x08025ba8
+ 801d12c:	0802580c 	.word	0x0802580c
+ 801d130:	08025bcc 	.word	0x08025bcc
+ 801d134:	08025bf0 	.word	0x08025bf0
+ 801d138:	08025c00 	.word	0x08025c00
+ 801d13c:	08025c10 	.word	0x08025c10
+
+0801d140 <tcp_send_fin>:
+ * @param pcb the tcp_pcb over which to send a segment
+ * @return ERR_OK if sent, another err_t otherwise
+ */
+err_t
+tcp_send_fin(struct tcp_pcb *pcb)
+{
+ 801d140:	b590      	push	{r4, r7, lr}
+ 801d142:	b085      	sub	sp, #20
+ 801d144:	af00      	add	r7, sp, #0
+ 801d146:	6078      	str	r0, [r7, #4]
+  LWIP_ASSERT("tcp_send_fin: invalid pcb", pcb != NULL);
+ 801d148:	687b      	ldr	r3, [r7, #4]
+ 801d14a:	2b00      	cmp	r3, #0
+ 801d14c:	d106      	bne.n	801d15c <tcp_send_fin+0x1c>
+ 801d14e:	4b21      	ldr	r3, [pc, #132]	; (801d1d4 <tcp_send_fin+0x94>)
+ 801d150:	f240 32eb 	movw	r2, #1003	; 0x3eb
+ 801d154:	4920      	ldr	r1, [pc, #128]	; (801d1d8 <tcp_send_fin+0x98>)
+ 801d156:	4821      	ldr	r0, [pc, #132]	; (801d1dc <tcp_send_fin+0x9c>)
+ 801d158:	f004 fc16 	bl	8021988 <iprintf>
+
+  /* first, try to add the fin to the last unsent segment */
+  if (pcb->unsent != NULL) {
+ 801d15c:	687b      	ldr	r3, [r7, #4]
+ 801d15e:	6edb      	ldr	r3, [r3, #108]	; 0x6c
+ 801d160:	2b00      	cmp	r3, #0
+ 801d162:	d02e      	beq.n	801d1c2 <tcp_send_fin+0x82>
+    struct tcp_seg *last_unsent;
+    for (last_unsent = pcb->unsent; last_unsent->next != NULL;
+ 801d164:	687b      	ldr	r3, [r7, #4]
+ 801d166:	6edb      	ldr	r3, [r3, #108]	; 0x6c
+ 801d168:	60fb      	str	r3, [r7, #12]
+ 801d16a:	e002      	b.n	801d172 <tcp_send_fin+0x32>
+         last_unsent = last_unsent->next);
+ 801d16c:	68fb      	ldr	r3, [r7, #12]
+ 801d16e:	681b      	ldr	r3, [r3, #0]
+ 801d170:	60fb      	str	r3, [r7, #12]
+    for (last_unsent = pcb->unsent; last_unsent->next != NULL;
+ 801d172:	68fb      	ldr	r3, [r7, #12]
+ 801d174:	681b      	ldr	r3, [r3, #0]
+ 801d176:	2b00      	cmp	r3, #0
+ 801d178:	d1f8      	bne.n	801d16c <tcp_send_fin+0x2c>
+
+    if ((TCPH_FLAGS(last_unsent->tcphdr) & (TCP_SYN | TCP_FIN | TCP_RST)) == 0) {
+ 801d17a:	68fb      	ldr	r3, [r7, #12]
+ 801d17c:	691b      	ldr	r3, [r3, #16]
+ 801d17e:	899b      	ldrh	r3, [r3, #12]
+ 801d180:	b29b      	uxth	r3, r3
+ 801d182:	4618      	mov	r0, r3
+ 801d184:	f7f8 fedc 	bl	8015f40 <lwip_htons>
+ 801d188:	4603      	mov	r3, r0
+ 801d18a:	b2db      	uxtb	r3, r3
+ 801d18c:	f003 0307 	and.w	r3, r3, #7
+ 801d190:	2b00      	cmp	r3, #0
+ 801d192:	d116      	bne.n	801d1c2 <tcp_send_fin+0x82>
+      /* no SYN/FIN/RST flag in the header, we can add the FIN flag */
+      TCPH_SET_FLAG(last_unsent->tcphdr, TCP_FIN);
+ 801d194:	68fb      	ldr	r3, [r7, #12]
+ 801d196:	691b      	ldr	r3, [r3, #16]
+ 801d198:	899b      	ldrh	r3, [r3, #12]
+ 801d19a:	b29c      	uxth	r4, r3
+ 801d19c:	2001      	movs	r0, #1
+ 801d19e:	f7f8 fecf 	bl	8015f40 <lwip_htons>
+ 801d1a2:	4603      	mov	r3, r0
+ 801d1a4:	461a      	mov	r2, r3
+ 801d1a6:	68fb      	ldr	r3, [r7, #12]
+ 801d1a8:	691b      	ldr	r3, [r3, #16]
+ 801d1aa:	4322      	orrs	r2, r4
+ 801d1ac:	b292      	uxth	r2, r2
+ 801d1ae:	819a      	strh	r2, [r3, #12]
+      tcp_set_flags(pcb, TF_FIN);
+ 801d1b0:	687b      	ldr	r3, [r7, #4]
+ 801d1b2:	8b5b      	ldrh	r3, [r3, #26]
+ 801d1b4:	f043 0320 	orr.w	r3, r3, #32
+ 801d1b8:	b29a      	uxth	r2, r3
+ 801d1ba:	687b      	ldr	r3, [r7, #4]
+ 801d1bc:	835a      	strh	r2, [r3, #26]
+      return ERR_OK;
+ 801d1be:	2300      	movs	r3, #0
+ 801d1c0:	e004      	b.n	801d1cc <tcp_send_fin+0x8c>
+    }
+  }
+  /* no data, no length, flags, copy=1, no optdata */
+  return tcp_enqueue_flags(pcb, TCP_FIN);
+ 801d1c2:	2101      	movs	r1, #1
+ 801d1c4:	6878      	ldr	r0, [r7, #4]
+ 801d1c6:	f000 f80b 	bl	801d1e0 <tcp_enqueue_flags>
+ 801d1ca:	4603      	mov	r3, r0
+}
+ 801d1cc:	4618      	mov	r0, r3
+ 801d1ce:	3714      	adds	r7, #20
+ 801d1d0:	46bd      	mov	sp, r7
+ 801d1d2:	bd90      	pop	{r4, r7, pc}
+ 801d1d4:	080257b8 	.word	0x080257b8
+ 801d1d8:	08025c1c 	.word	0x08025c1c
+ 801d1dc:	0802580c 	.word	0x0802580c
+
+0801d1e0 <tcp_enqueue_flags>:
+ * @param pcb Protocol control block for the TCP connection.
+ * @param flags TCP header flags to set in the outgoing segment.
+ */
+err_t
+tcp_enqueue_flags(struct tcp_pcb *pcb, u8_t flags)
+{
+ 801d1e0:	b580      	push	{r7, lr}
+ 801d1e2:	b088      	sub	sp, #32
+ 801d1e4:	af02      	add	r7, sp, #8
+ 801d1e6:	6078      	str	r0, [r7, #4]
+ 801d1e8:	460b      	mov	r3, r1
+ 801d1ea:	70fb      	strb	r3, [r7, #3]
+  struct pbuf *p;
+  struct tcp_seg *seg;
+  u8_t optflags = 0;
+ 801d1ec:	2300      	movs	r3, #0
+ 801d1ee:	75fb      	strb	r3, [r7, #23]
+  u8_t optlen = 0;
+ 801d1f0:	2300      	movs	r3, #0
+ 801d1f2:	75bb      	strb	r3, [r7, #22]
+
+  LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_enqueue_flags: queuelen: %"U16_F"\n", (u16_t)pcb->snd_queuelen));
+
+  LWIP_ASSERT("tcp_enqueue_flags: need either TCP_SYN or TCP_FIN in flags (programmer violates API)",
+ 801d1f4:	78fb      	ldrb	r3, [r7, #3]
+ 801d1f6:	f003 0303 	and.w	r3, r3, #3
+ 801d1fa:	2b00      	cmp	r3, #0
+ 801d1fc:	d106      	bne.n	801d20c <tcp_enqueue_flags+0x2c>
+ 801d1fe:	4b67      	ldr	r3, [pc, #412]	; (801d39c <tcp_enqueue_flags+0x1bc>)
+ 801d200:	f240 4211 	movw	r2, #1041	; 0x411
+ 801d204:	4966      	ldr	r1, [pc, #408]	; (801d3a0 <tcp_enqueue_flags+0x1c0>)
+ 801d206:	4867      	ldr	r0, [pc, #412]	; (801d3a4 <tcp_enqueue_flags+0x1c4>)
+ 801d208:	f004 fbbe 	bl	8021988 <iprintf>
+              (flags & (TCP_SYN | TCP_FIN)) != 0);
+  LWIP_ASSERT("tcp_enqueue_flags: invalid pcb", pcb != NULL);
+ 801d20c:	687b      	ldr	r3, [r7, #4]
+ 801d20e:	2b00      	cmp	r3, #0
+ 801d210:	d106      	bne.n	801d220 <tcp_enqueue_flags+0x40>
+ 801d212:	4b62      	ldr	r3, [pc, #392]	; (801d39c <tcp_enqueue_flags+0x1bc>)
+ 801d214:	f240 4213 	movw	r2, #1043	; 0x413
+ 801d218:	4963      	ldr	r1, [pc, #396]	; (801d3a8 <tcp_enqueue_flags+0x1c8>)
+ 801d21a:	4862      	ldr	r0, [pc, #392]	; (801d3a4 <tcp_enqueue_flags+0x1c4>)
+ 801d21c:	f004 fbb4 	bl	8021988 <iprintf>
+
+  /* No need to check pcb->snd_queuelen if only SYN or FIN are allowed! */
+
+  /* Get options for this segment. This is a special case since this is the
+     only place where a SYN can be sent. */
+  if (flags & TCP_SYN) {
+ 801d220:	78fb      	ldrb	r3, [r7, #3]
+ 801d222:	f003 0302 	and.w	r3, r3, #2
+ 801d226:	2b00      	cmp	r3, #0
+ 801d228:	d001      	beq.n	801d22e <tcp_enqueue_flags+0x4e>
+    optflags = TF_SEG_OPTS_MSS;
+ 801d22a:	2301      	movs	r3, #1
+ 801d22c:	75fb      	strb	r3, [r7, #23]
+    /* Make sure the timestamp option is only included in data segments if we
+       agreed about it with the remote host (and in active open SYN segments). */
+    optflags |= TF_SEG_OPTS_TS;
+  }
+#endif /* LWIP_TCP_TIMESTAMPS */
+  optlen = LWIP_TCP_OPT_LENGTH_SEGMENT(optflags, pcb);
+ 801d22e:	7dfb      	ldrb	r3, [r7, #23]
+ 801d230:	009b      	lsls	r3, r3, #2
+ 801d232:	b2db      	uxtb	r3, r3
+ 801d234:	f003 0304 	and.w	r3, r3, #4
+ 801d238:	75bb      	strb	r3, [r7, #22]
+
+  /* Allocate pbuf with room for TCP header + options */
+  if ((p = pbuf_alloc(PBUF_TRANSPORT, optlen, PBUF_RAM)) == NULL) {
+ 801d23a:	7dbb      	ldrb	r3, [r7, #22]
+ 801d23c:	b29b      	uxth	r3, r3
+ 801d23e:	f44f 7220 	mov.w	r2, #640	; 0x280
+ 801d242:	4619      	mov	r1, r3
+ 801d244:	2036      	movs	r0, #54	; 0x36
+ 801d246:	f7fa f96f 	bl	8017528 <pbuf_alloc>
+ 801d24a:	60f8      	str	r0, [r7, #12]
+ 801d24c:	68fb      	ldr	r3, [r7, #12]
+ 801d24e:	2b00      	cmp	r3, #0
+ 801d250:	d109      	bne.n	801d266 <tcp_enqueue_flags+0x86>
+    tcp_set_flags(pcb, TF_NAGLEMEMERR);
+ 801d252:	687b      	ldr	r3, [r7, #4]
+ 801d254:	8b5b      	ldrh	r3, [r3, #26]
+ 801d256:	f043 0380 	orr.w	r3, r3, #128	; 0x80
+ 801d25a:	b29a      	uxth	r2, r3
+ 801d25c:	687b      	ldr	r3, [r7, #4]
+ 801d25e:	835a      	strh	r2, [r3, #26]
+    TCP_STATS_INC(tcp.memerr);
+    return ERR_MEM;
+ 801d260:	f04f 33ff 	mov.w	r3, #4294967295
+ 801d264:	e095      	b.n	801d392 <tcp_enqueue_flags+0x1b2>
+  }
+  LWIP_ASSERT("tcp_enqueue_flags: check that first pbuf can hold optlen",
+ 801d266:	68fb      	ldr	r3, [r7, #12]
+ 801d268:	895a      	ldrh	r2, [r3, #10]
+ 801d26a:	7dbb      	ldrb	r3, [r7, #22]
+ 801d26c:	b29b      	uxth	r3, r3
+ 801d26e:	429a      	cmp	r2, r3
+ 801d270:	d206      	bcs.n	801d280 <tcp_enqueue_flags+0xa0>
+ 801d272:	4b4a      	ldr	r3, [pc, #296]	; (801d39c <tcp_enqueue_flags+0x1bc>)
+ 801d274:	f240 4239 	movw	r2, #1081	; 0x439
+ 801d278:	494c      	ldr	r1, [pc, #304]	; (801d3ac <tcp_enqueue_flags+0x1cc>)
+ 801d27a:	484a      	ldr	r0, [pc, #296]	; (801d3a4 <tcp_enqueue_flags+0x1c4>)
+ 801d27c:	f004 fb84 	bl	8021988 <iprintf>
+              (p->len >= optlen));
+
+  /* Allocate memory for tcp_seg, and fill in fields. */
+  if ((seg = tcp_create_segment(pcb, p, flags, pcb->snd_lbb, optflags)) == NULL) {
+ 801d280:	687b      	ldr	r3, [r7, #4]
+ 801d282:	6dd9      	ldr	r1, [r3, #92]	; 0x5c
+ 801d284:	78fa      	ldrb	r2, [r7, #3]
+ 801d286:	7dfb      	ldrb	r3, [r7, #23]
+ 801d288:	9300      	str	r3, [sp, #0]
+ 801d28a:	460b      	mov	r3, r1
+ 801d28c:	68f9      	ldr	r1, [r7, #12]
+ 801d28e:	6878      	ldr	r0, [r7, #4]
+ 801d290:	f7ff f8b8 	bl	801c404 <tcp_create_segment>
+ 801d294:	60b8      	str	r0, [r7, #8]
+ 801d296:	68bb      	ldr	r3, [r7, #8]
+ 801d298:	2b00      	cmp	r3, #0
+ 801d29a:	d109      	bne.n	801d2b0 <tcp_enqueue_flags+0xd0>
+    tcp_set_flags(pcb, TF_NAGLEMEMERR);
+ 801d29c:	687b      	ldr	r3, [r7, #4]
+ 801d29e:	8b5b      	ldrh	r3, [r3, #26]
+ 801d2a0:	f043 0380 	orr.w	r3, r3, #128	; 0x80
+ 801d2a4:	b29a      	uxth	r2, r3
+ 801d2a6:	687b      	ldr	r3, [r7, #4]
+ 801d2a8:	835a      	strh	r2, [r3, #26]
+    TCP_STATS_INC(tcp.memerr);
+    return ERR_MEM;
+ 801d2aa:	f04f 33ff 	mov.w	r3, #4294967295
+ 801d2ae:	e070      	b.n	801d392 <tcp_enqueue_flags+0x1b2>
+  }
+  LWIP_ASSERT("seg->tcphdr not aligned", ((mem_ptr_t)seg->tcphdr % LWIP_MIN(MEM_ALIGNMENT, 4)) == 0);
+ 801d2b0:	68bb      	ldr	r3, [r7, #8]
+ 801d2b2:	691b      	ldr	r3, [r3, #16]
+ 801d2b4:	f003 0303 	and.w	r3, r3, #3
+ 801d2b8:	2b00      	cmp	r3, #0
+ 801d2ba:	d006      	beq.n	801d2ca <tcp_enqueue_flags+0xea>
+ 801d2bc:	4b37      	ldr	r3, [pc, #220]	; (801d39c <tcp_enqueue_flags+0x1bc>)
+ 801d2be:	f240 4242 	movw	r2, #1090	; 0x442
+ 801d2c2:	493b      	ldr	r1, [pc, #236]	; (801d3b0 <tcp_enqueue_flags+0x1d0>)
+ 801d2c4:	4837      	ldr	r0, [pc, #220]	; (801d3a4 <tcp_enqueue_flags+0x1c4>)
+ 801d2c6:	f004 fb5f 	bl	8021988 <iprintf>
+  LWIP_ASSERT("tcp_enqueue_flags: invalid segment length", seg->len == 0);
+ 801d2ca:	68bb      	ldr	r3, [r7, #8]
+ 801d2cc:	891b      	ldrh	r3, [r3, #8]
+ 801d2ce:	2b00      	cmp	r3, #0
+ 801d2d0:	d006      	beq.n	801d2e0 <tcp_enqueue_flags+0x100>
+ 801d2d2:	4b32      	ldr	r3, [pc, #200]	; (801d39c <tcp_enqueue_flags+0x1bc>)
+ 801d2d4:	f240 4243 	movw	r2, #1091	; 0x443
+ 801d2d8:	4936      	ldr	r1, [pc, #216]	; (801d3b4 <tcp_enqueue_flags+0x1d4>)
+ 801d2da:	4832      	ldr	r0, [pc, #200]	; (801d3a4 <tcp_enqueue_flags+0x1c4>)
+ 801d2dc:	f004 fb54 	bl	8021988 <iprintf>
+               lwip_ntohl(seg->tcphdr->seqno),
+               lwip_ntohl(seg->tcphdr->seqno) + TCP_TCPLEN(seg),
+               (u16_t)flags));
+
+  /* Now append seg to pcb->unsent queue */
+  if (pcb->unsent == NULL) {
+ 801d2e0:	687b      	ldr	r3, [r7, #4]
+ 801d2e2:	6edb      	ldr	r3, [r3, #108]	; 0x6c
+ 801d2e4:	2b00      	cmp	r3, #0
+ 801d2e6:	d103      	bne.n	801d2f0 <tcp_enqueue_flags+0x110>
+    pcb->unsent = seg;
+ 801d2e8:	687b      	ldr	r3, [r7, #4]
+ 801d2ea:	68ba      	ldr	r2, [r7, #8]
+ 801d2ec:	66da      	str	r2, [r3, #108]	; 0x6c
+ 801d2ee:	e00d      	b.n	801d30c <tcp_enqueue_flags+0x12c>
+  } else {
+    struct tcp_seg *useg;
+    for (useg = pcb->unsent; useg->next != NULL; useg = useg->next);
+ 801d2f0:	687b      	ldr	r3, [r7, #4]
+ 801d2f2:	6edb      	ldr	r3, [r3, #108]	; 0x6c
+ 801d2f4:	613b      	str	r3, [r7, #16]
+ 801d2f6:	e002      	b.n	801d2fe <tcp_enqueue_flags+0x11e>
+ 801d2f8:	693b      	ldr	r3, [r7, #16]
+ 801d2fa:	681b      	ldr	r3, [r3, #0]
+ 801d2fc:	613b      	str	r3, [r7, #16]
+ 801d2fe:	693b      	ldr	r3, [r7, #16]
+ 801d300:	681b      	ldr	r3, [r3, #0]
+ 801d302:	2b00      	cmp	r3, #0
+ 801d304:	d1f8      	bne.n	801d2f8 <tcp_enqueue_flags+0x118>
+    useg->next = seg;
+ 801d306:	693b      	ldr	r3, [r7, #16]
+ 801d308:	68ba      	ldr	r2, [r7, #8]
+ 801d30a:	601a      	str	r2, [r3, #0]
+  }
+#if TCP_OVERSIZE
+  /* The new unsent tail has no space */
+  pcb->unsent_oversize = 0;
+ 801d30c:	687b      	ldr	r3, [r7, #4]
+ 801d30e:	2200      	movs	r2, #0
+ 801d310:	f8a3 2068 	strh.w	r2, [r3, #104]	; 0x68
+#endif /* TCP_OVERSIZE */
+
+  /* SYN and FIN bump the sequence number */
+  if ((flags & TCP_SYN) || (flags & TCP_FIN)) {
+ 801d314:	78fb      	ldrb	r3, [r7, #3]
+ 801d316:	f003 0302 	and.w	r3, r3, #2
+ 801d31a:	2b00      	cmp	r3, #0
+ 801d31c:	d104      	bne.n	801d328 <tcp_enqueue_flags+0x148>
+ 801d31e:	78fb      	ldrb	r3, [r7, #3]
+ 801d320:	f003 0301 	and.w	r3, r3, #1
+ 801d324:	2b00      	cmp	r3, #0
+ 801d326:	d004      	beq.n	801d332 <tcp_enqueue_flags+0x152>
+    pcb->snd_lbb++;
+ 801d328:	687b      	ldr	r3, [r7, #4]
+ 801d32a:	6ddb      	ldr	r3, [r3, #92]	; 0x5c
+ 801d32c:	1c5a      	adds	r2, r3, #1
+ 801d32e:	687b      	ldr	r3, [r7, #4]
+ 801d330:	65da      	str	r2, [r3, #92]	; 0x5c
+    /* optlen does not influence snd_buf */
+  }
+  if (flags & TCP_FIN) {
+ 801d332:	78fb      	ldrb	r3, [r7, #3]
+ 801d334:	f003 0301 	and.w	r3, r3, #1
+ 801d338:	2b00      	cmp	r3, #0
+ 801d33a:	d006      	beq.n	801d34a <tcp_enqueue_flags+0x16a>
+    tcp_set_flags(pcb, TF_FIN);
+ 801d33c:	687b      	ldr	r3, [r7, #4]
+ 801d33e:	8b5b      	ldrh	r3, [r3, #26]
+ 801d340:	f043 0320 	orr.w	r3, r3, #32
+ 801d344:	b29a      	uxth	r2, r3
+ 801d346:	687b      	ldr	r3, [r7, #4]
+ 801d348:	835a      	strh	r2, [r3, #26]
+  }
+
+  /* update number of segments on the queues */
+  pcb->snd_queuelen += pbuf_clen(seg->p);
+ 801d34a:	68bb      	ldr	r3, [r7, #8]
+ 801d34c:	685b      	ldr	r3, [r3, #4]
+ 801d34e:	4618      	mov	r0, r3
+ 801d350:	f7fa fc60 	bl	8017c14 <pbuf_clen>
+ 801d354:	4603      	mov	r3, r0
+ 801d356:	461a      	mov	r2, r3
+ 801d358:	687b      	ldr	r3, [r7, #4]
+ 801d35a:	f8b3 3066 	ldrh.w	r3, [r3, #102]	; 0x66
+ 801d35e:	4413      	add	r3, r2
+ 801d360:	b29a      	uxth	r2, r3
+ 801d362:	687b      	ldr	r3, [r7, #4]
+ 801d364:	f8a3 2066 	strh.w	r2, [r3, #102]	; 0x66
+  LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_enqueue_flags: %"S16_F" (after enqueued)\n", pcb->snd_queuelen));
+  if (pcb->snd_queuelen != 0) {
+ 801d368:	687b      	ldr	r3, [r7, #4]
+ 801d36a:	f8b3 3066 	ldrh.w	r3, [r3, #102]	; 0x66
+ 801d36e:	2b00      	cmp	r3, #0
+ 801d370:	d00e      	beq.n	801d390 <tcp_enqueue_flags+0x1b0>
+    LWIP_ASSERT("tcp_enqueue_flags: invalid queue length",
+ 801d372:	687b      	ldr	r3, [r7, #4]
+ 801d374:	6f1b      	ldr	r3, [r3, #112]	; 0x70
+ 801d376:	2b00      	cmp	r3, #0
+ 801d378:	d10a      	bne.n	801d390 <tcp_enqueue_flags+0x1b0>
+ 801d37a:	687b      	ldr	r3, [r7, #4]
+ 801d37c:	6edb      	ldr	r3, [r3, #108]	; 0x6c
+ 801d37e:	2b00      	cmp	r3, #0
+ 801d380:	d106      	bne.n	801d390 <tcp_enqueue_flags+0x1b0>
+ 801d382:	4b06      	ldr	r3, [pc, #24]	; (801d39c <tcp_enqueue_flags+0x1bc>)
+ 801d384:	f240 4265 	movw	r2, #1125	; 0x465
+ 801d388:	490b      	ldr	r1, [pc, #44]	; (801d3b8 <tcp_enqueue_flags+0x1d8>)
+ 801d38a:	4806      	ldr	r0, [pc, #24]	; (801d3a4 <tcp_enqueue_flags+0x1c4>)
+ 801d38c:	f004 fafc 	bl	8021988 <iprintf>
+                pcb->unacked != NULL || pcb->unsent != NULL);
+  }
+
+  return ERR_OK;
+ 801d390:	2300      	movs	r3, #0
+}
+ 801d392:	4618      	mov	r0, r3
+ 801d394:	3718      	adds	r7, #24
+ 801d396:	46bd      	mov	sp, r7
+ 801d398:	bd80      	pop	{r7, pc}
+ 801d39a:	bf00      	nop
+ 801d39c:	080257b8 	.word	0x080257b8
+ 801d3a0:	08025c38 	.word	0x08025c38
+ 801d3a4:	0802580c 	.word	0x0802580c
+ 801d3a8:	08025c90 	.word	0x08025c90
+ 801d3ac:	08025cb0 	.word	0x08025cb0
+ 801d3b0:	08025cec 	.word	0x08025cec
+ 801d3b4:	08025d04 	.word	0x08025d04
+ 801d3b8:	08025d30 	.word	0x08025d30
+
+0801d3bc <tcp_output>:
+ * @return ERR_OK if data has been sent or nothing to send
+ *         another err_t on error
+ */
+err_t
+tcp_output(struct tcp_pcb *pcb)
+{
+ 801d3bc:	b5b0      	push	{r4, r5, r7, lr}
+ 801d3be:	b08a      	sub	sp, #40	; 0x28
+ 801d3c0:	af00      	add	r7, sp, #0
+ 801d3c2:	6078      	str	r0, [r7, #4]
+  s16_t i = 0;
+#endif /* TCP_CWND_DEBUG */
+
+  LWIP_ASSERT_CORE_LOCKED();
+
+  LWIP_ASSERT("tcp_output: invalid pcb", pcb != NULL);
+ 801d3c4:	687b      	ldr	r3, [r7, #4]
+ 801d3c6:	2b00      	cmp	r3, #0
+ 801d3c8:	d106      	bne.n	801d3d8 <tcp_output+0x1c>
+ 801d3ca:	4b8a      	ldr	r3, [pc, #552]	; (801d5f4 <tcp_output+0x238>)
+ 801d3cc:	f240 42e1 	movw	r2, #1249	; 0x4e1
+ 801d3d0:	4989      	ldr	r1, [pc, #548]	; (801d5f8 <tcp_output+0x23c>)
+ 801d3d2:	488a      	ldr	r0, [pc, #552]	; (801d5fc <tcp_output+0x240>)
+ 801d3d4:	f004 fad8 	bl	8021988 <iprintf>
+  /* pcb->state LISTEN not allowed here */
+  LWIP_ASSERT("don't call tcp_output for listen-pcbs",
+ 801d3d8:	687b      	ldr	r3, [r7, #4]
+ 801d3da:	7d1b      	ldrb	r3, [r3, #20]
+ 801d3dc:	2b01      	cmp	r3, #1
+ 801d3de:	d106      	bne.n	801d3ee <tcp_output+0x32>
+ 801d3e0:	4b84      	ldr	r3, [pc, #528]	; (801d5f4 <tcp_output+0x238>)
+ 801d3e2:	f240 42e3 	movw	r2, #1251	; 0x4e3
+ 801d3e6:	4986      	ldr	r1, [pc, #536]	; (801d600 <tcp_output+0x244>)
+ 801d3e8:	4884      	ldr	r0, [pc, #528]	; (801d5fc <tcp_output+0x240>)
+ 801d3ea:	f004 facd 	bl	8021988 <iprintf>
+
+  /* First, check if we are invoked by the TCP input processing
+     code. If so, we do not output anything. Instead, we rely on the
+     input processing code to call us when input processing is done
+     with. */
+  if (tcp_input_pcb == pcb) {
+ 801d3ee:	4b85      	ldr	r3, [pc, #532]	; (801d604 <tcp_output+0x248>)
+ 801d3f0:	681b      	ldr	r3, [r3, #0]
+ 801d3f2:	687a      	ldr	r2, [r7, #4]
+ 801d3f4:	429a      	cmp	r2, r3
+ 801d3f6:	d101      	bne.n	801d3fc <tcp_output+0x40>
+    return ERR_OK;
+ 801d3f8:	2300      	movs	r3, #0
+ 801d3fa:	e1d1      	b.n	801d7a0 <tcp_output+0x3e4>
+  }
+
+  wnd = LWIP_MIN(pcb->snd_wnd, pcb->cwnd);
+ 801d3fc:	687b      	ldr	r3, [r7, #4]
+ 801d3fe:	f8b3 2048 	ldrh.w	r2, [r3, #72]	; 0x48
+ 801d402:	687b      	ldr	r3, [r7, #4]
+ 801d404:	f8b3 3060 	ldrh.w	r3, [r3, #96]	; 0x60
+ 801d408:	4293      	cmp	r3, r2
+ 801d40a:	bf28      	it	cs
+ 801d40c:	4613      	movcs	r3, r2
+ 801d40e:	b29b      	uxth	r3, r3
+ 801d410:	61bb      	str	r3, [r7, #24]
+
+  seg = pcb->unsent;
+ 801d412:	687b      	ldr	r3, [r7, #4]
+ 801d414:	6edb      	ldr	r3, [r3, #108]	; 0x6c
+ 801d416:	627b      	str	r3, [r7, #36]	; 0x24
+
+  if (seg == NULL) {
+ 801d418:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 801d41a:	2b00      	cmp	r3, #0
+ 801d41c:	d10b      	bne.n	801d436 <tcp_output+0x7a>
+                                 ", seg == NULL, ack %"U32_F"\n",
+                                 pcb->snd_wnd, pcb->cwnd, wnd, pcb->lastack));
+
+    /* If the TF_ACK_NOW flag is set and the ->unsent queue is empty, construct
+     * an empty ACK segment and send it. */
+    if (pcb->flags & TF_ACK_NOW) {
+ 801d41e:	687b      	ldr	r3, [r7, #4]
+ 801d420:	8b5b      	ldrh	r3, [r3, #26]
+ 801d422:	f003 0302 	and.w	r3, r3, #2
+ 801d426:	2b00      	cmp	r3, #0
+ 801d428:	f000 81ad 	beq.w	801d786 <tcp_output+0x3ca>
+      return tcp_send_empty_ack(pcb);
+ 801d42c:	6878      	ldr	r0, [r7, #4]
+ 801d42e:	f000 fdd7 	bl	801dfe0 <tcp_send_empty_ack>
+ 801d432:	4603      	mov	r3, r0
+ 801d434:	e1b4      	b.n	801d7a0 <tcp_output+0x3e4>
+                 pcb->snd_wnd, pcb->cwnd, wnd,
+                 lwip_ntohl(seg->tcphdr->seqno) - pcb->lastack + seg->len,
+                 lwip_ntohl(seg->tcphdr->seqno), pcb->lastack));
+  }
+
+  netif = tcp_route(pcb, &pcb->local_ip, &pcb->remote_ip);
+ 801d436:	6879      	ldr	r1, [r7, #4]
+ 801d438:	687b      	ldr	r3, [r7, #4]
+ 801d43a:	3304      	adds	r3, #4
+ 801d43c:	461a      	mov	r2, r3
+ 801d43e:	6878      	ldr	r0, [r7, #4]
+ 801d440:	f7fe ffc4 	bl	801c3cc <tcp_route>
+ 801d444:	6178      	str	r0, [r7, #20]
+  if (netif == NULL) {
+ 801d446:	697b      	ldr	r3, [r7, #20]
+ 801d448:	2b00      	cmp	r3, #0
+ 801d44a:	d102      	bne.n	801d452 <tcp_output+0x96>
+    return ERR_RTE;
+ 801d44c:	f06f 0303 	mvn.w	r3, #3
+ 801d450:	e1a6      	b.n	801d7a0 <tcp_output+0x3e4>
+  }
+
+  /* If we don't have a local IP address, we get one from netif */
+  if (ip_addr_isany(&pcb->local_ip)) {
+ 801d452:	687b      	ldr	r3, [r7, #4]
+ 801d454:	2b00      	cmp	r3, #0
+ 801d456:	d003      	beq.n	801d460 <tcp_output+0xa4>
+ 801d458:	687b      	ldr	r3, [r7, #4]
+ 801d45a:	681b      	ldr	r3, [r3, #0]
+ 801d45c:	2b00      	cmp	r3, #0
+ 801d45e:	d111      	bne.n	801d484 <tcp_output+0xc8>
+    const ip_addr_t *local_ip = ip_netif_get_local_ip(netif, &pcb->remote_ip);
+ 801d460:	697b      	ldr	r3, [r7, #20]
+ 801d462:	2b00      	cmp	r3, #0
+ 801d464:	d002      	beq.n	801d46c <tcp_output+0xb0>
+ 801d466:	697b      	ldr	r3, [r7, #20]
+ 801d468:	3304      	adds	r3, #4
+ 801d46a:	e000      	b.n	801d46e <tcp_output+0xb2>
+ 801d46c:	2300      	movs	r3, #0
+ 801d46e:	613b      	str	r3, [r7, #16]
+    if (local_ip == NULL) {
+ 801d470:	693b      	ldr	r3, [r7, #16]
+ 801d472:	2b00      	cmp	r3, #0
+ 801d474:	d102      	bne.n	801d47c <tcp_output+0xc0>
+      return ERR_RTE;
+ 801d476:	f06f 0303 	mvn.w	r3, #3
+ 801d47a:	e191      	b.n	801d7a0 <tcp_output+0x3e4>
+    }
+    ip_addr_copy(pcb->local_ip, *local_ip);
+ 801d47c:	693b      	ldr	r3, [r7, #16]
+ 801d47e:	681a      	ldr	r2, [r3, #0]
+ 801d480:	687b      	ldr	r3, [r7, #4]
+ 801d482:	601a      	str	r2, [r3, #0]
+  }
+
+  /* Handle the current segment not fitting within the window */
+  if (lwip_ntohl(seg->tcphdr->seqno) - pcb->lastack + seg->len > wnd) {
+ 801d484:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 801d486:	691b      	ldr	r3, [r3, #16]
+ 801d488:	685b      	ldr	r3, [r3, #4]
+ 801d48a:	4618      	mov	r0, r3
+ 801d48c:	f7f8 fd6d 	bl	8015f6a <lwip_htonl>
+ 801d490:	4602      	mov	r2, r0
+ 801d492:	687b      	ldr	r3, [r7, #4]
+ 801d494:	6c5b      	ldr	r3, [r3, #68]	; 0x44
+ 801d496:	1ad3      	subs	r3, r2, r3
+ 801d498:	6a7a      	ldr	r2, [r7, #36]	; 0x24
+ 801d49a:	8912      	ldrh	r2, [r2, #8]
+ 801d49c:	4413      	add	r3, r2
+ 801d49e:	69ba      	ldr	r2, [r7, #24]
+ 801d4a0:	429a      	cmp	r2, r3
+ 801d4a2:	d227      	bcs.n	801d4f4 <tcp_output+0x138>
+     * within the remaining (could be 0) send window and RTO timer is not running (we
+     * have no in-flight data). If window is still too small after persist timer fires,
+     * then we split the segment. We don't consider the congestion window since a cwnd
+     * smaller than 1 SMSS implies in-flight data
+     */
+    if (wnd == pcb->snd_wnd && pcb->unacked == NULL && pcb->persist_backoff == 0) {
+ 801d4a4:	687b      	ldr	r3, [r7, #4]
+ 801d4a6:	f8b3 3060 	ldrh.w	r3, [r3, #96]	; 0x60
+ 801d4aa:	461a      	mov	r2, r3
+ 801d4ac:	69bb      	ldr	r3, [r7, #24]
+ 801d4ae:	4293      	cmp	r3, r2
+ 801d4b0:	d114      	bne.n	801d4dc <tcp_output+0x120>
+ 801d4b2:	687b      	ldr	r3, [r7, #4]
+ 801d4b4:	6f1b      	ldr	r3, [r3, #112]	; 0x70
+ 801d4b6:	2b00      	cmp	r3, #0
+ 801d4b8:	d110      	bne.n	801d4dc <tcp_output+0x120>
+ 801d4ba:	687b      	ldr	r3, [r7, #4]
+ 801d4bc:	f893 3099 	ldrb.w	r3, [r3, #153]	; 0x99
+ 801d4c0:	2b00      	cmp	r3, #0
+ 801d4c2:	d10b      	bne.n	801d4dc <tcp_output+0x120>
+      pcb->persist_cnt = 0;
+ 801d4c4:	687b      	ldr	r3, [r7, #4]
+ 801d4c6:	2200      	movs	r2, #0
+ 801d4c8:	f883 2098 	strb.w	r2, [r3, #152]	; 0x98
+      pcb->persist_backoff = 1;
+ 801d4cc:	687b      	ldr	r3, [r7, #4]
+ 801d4ce:	2201      	movs	r2, #1
+ 801d4d0:	f883 2099 	strb.w	r2, [r3, #153]	; 0x99
+      pcb->persist_probe = 0;
+ 801d4d4:	687b      	ldr	r3, [r7, #4]
+ 801d4d6:	2200      	movs	r2, #0
+ 801d4d8:	f883 209a 	strb.w	r2, [r3, #154]	; 0x9a
+    }
+    /* We need an ACK, but can't send data now, so send an empty ACK */
+    if (pcb->flags & TF_ACK_NOW) {
+ 801d4dc:	687b      	ldr	r3, [r7, #4]
+ 801d4de:	8b5b      	ldrh	r3, [r3, #26]
+ 801d4e0:	f003 0302 	and.w	r3, r3, #2
+ 801d4e4:	2b00      	cmp	r3, #0
+ 801d4e6:	f000 8150 	beq.w	801d78a <tcp_output+0x3ce>
+      return tcp_send_empty_ack(pcb);
+ 801d4ea:	6878      	ldr	r0, [r7, #4]
+ 801d4ec:	f000 fd78 	bl	801dfe0 <tcp_send_empty_ack>
+ 801d4f0:	4603      	mov	r3, r0
+ 801d4f2:	e155      	b.n	801d7a0 <tcp_output+0x3e4>
+    }
+    goto output_done;
+  }
+  /* Stop persist timer, above conditions are not active */
+  pcb->persist_backoff = 0;
+ 801d4f4:	687b      	ldr	r3, [r7, #4]
+ 801d4f6:	2200      	movs	r2, #0
+ 801d4f8:	f883 2099 	strb.w	r2, [r3, #153]	; 0x99
+
+  /* useg should point to last segment on unacked queue */
+  useg = pcb->unacked;
+ 801d4fc:	687b      	ldr	r3, [r7, #4]
+ 801d4fe:	6f1b      	ldr	r3, [r3, #112]	; 0x70
+ 801d500:	623b      	str	r3, [r7, #32]
+  if (useg != NULL) {
+ 801d502:	6a3b      	ldr	r3, [r7, #32]
+ 801d504:	2b00      	cmp	r3, #0
+ 801d506:	f000 811f 	beq.w	801d748 <tcp_output+0x38c>
+    for (; useg->next != NULL; useg = useg->next);
+ 801d50a:	e002      	b.n	801d512 <tcp_output+0x156>
+ 801d50c:	6a3b      	ldr	r3, [r7, #32]
+ 801d50e:	681b      	ldr	r3, [r3, #0]
+ 801d510:	623b      	str	r3, [r7, #32]
+ 801d512:	6a3b      	ldr	r3, [r7, #32]
+ 801d514:	681b      	ldr	r3, [r3, #0]
+ 801d516:	2b00      	cmp	r3, #0
+ 801d518:	d1f8      	bne.n	801d50c <tcp_output+0x150>
+  }
+  /* data available and window allows it to be sent? */
+  while (seg != NULL &&
+ 801d51a:	e115      	b.n	801d748 <tcp_output+0x38c>
+         lwip_ntohl(seg->tcphdr->seqno) - pcb->lastack + seg->len <= wnd) {
+    LWIP_ASSERT("RST not expected here!",
+ 801d51c:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 801d51e:	691b      	ldr	r3, [r3, #16]
+ 801d520:	899b      	ldrh	r3, [r3, #12]
+ 801d522:	b29b      	uxth	r3, r3
+ 801d524:	4618      	mov	r0, r3
+ 801d526:	f7f8 fd0b 	bl	8015f40 <lwip_htons>
+ 801d52a:	4603      	mov	r3, r0
+ 801d52c:	b2db      	uxtb	r3, r3
+ 801d52e:	f003 0304 	and.w	r3, r3, #4
+ 801d532:	2b00      	cmp	r3, #0
+ 801d534:	d006      	beq.n	801d544 <tcp_output+0x188>
+ 801d536:	4b2f      	ldr	r3, [pc, #188]	; (801d5f4 <tcp_output+0x238>)
+ 801d538:	f240 5236 	movw	r2, #1334	; 0x536
+ 801d53c:	4932      	ldr	r1, [pc, #200]	; (801d608 <tcp_output+0x24c>)
+ 801d53e:	482f      	ldr	r0, [pc, #188]	; (801d5fc <tcp_output+0x240>)
+ 801d540:	f004 fa22 	bl	8021988 <iprintf>
+     * - if tcp_write had a memory error before (prevent delayed ACK timeout) or
+     * - if FIN was already enqueued for this PCB (SYN is always alone in a segment -
+     *   either seg->next != NULL or pcb->unacked == NULL;
+     *   RST is no sent using tcp_write/tcp_output.
+     */
+    if ((tcp_do_output_nagle(pcb) == 0) &&
+ 801d544:	687b      	ldr	r3, [r7, #4]
+ 801d546:	6f1b      	ldr	r3, [r3, #112]	; 0x70
+ 801d548:	2b00      	cmp	r3, #0
+ 801d54a:	d01f      	beq.n	801d58c <tcp_output+0x1d0>
+ 801d54c:	687b      	ldr	r3, [r7, #4]
+ 801d54e:	8b5b      	ldrh	r3, [r3, #26]
+ 801d550:	f003 0344 	and.w	r3, r3, #68	; 0x44
+ 801d554:	2b00      	cmp	r3, #0
+ 801d556:	d119      	bne.n	801d58c <tcp_output+0x1d0>
+ 801d558:	687b      	ldr	r3, [r7, #4]
+ 801d55a:	6edb      	ldr	r3, [r3, #108]	; 0x6c
+ 801d55c:	2b00      	cmp	r3, #0
+ 801d55e:	d00b      	beq.n	801d578 <tcp_output+0x1bc>
+ 801d560:	687b      	ldr	r3, [r7, #4]
+ 801d562:	6edb      	ldr	r3, [r3, #108]	; 0x6c
+ 801d564:	681b      	ldr	r3, [r3, #0]
+ 801d566:	2b00      	cmp	r3, #0
+ 801d568:	d110      	bne.n	801d58c <tcp_output+0x1d0>
+ 801d56a:	687b      	ldr	r3, [r7, #4]
+ 801d56c:	6edb      	ldr	r3, [r3, #108]	; 0x6c
+ 801d56e:	891a      	ldrh	r2, [r3, #8]
+ 801d570:	687b      	ldr	r3, [r7, #4]
+ 801d572:	8e5b      	ldrh	r3, [r3, #50]	; 0x32
+ 801d574:	429a      	cmp	r2, r3
+ 801d576:	d209      	bcs.n	801d58c <tcp_output+0x1d0>
+ 801d578:	687b      	ldr	r3, [r7, #4]
+ 801d57a:	f8b3 3064 	ldrh.w	r3, [r3, #100]	; 0x64
+ 801d57e:	2b00      	cmp	r3, #0
+ 801d580:	d004      	beq.n	801d58c <tcp_output+0x1d0>
+ 801d582:	687b      	ldr	r3, [r7, #4]
+ 801d584:	f8b3 3066 	ldrh.w	r3, [r3, #102]	; 0x66
+ 801d588:	2b0f      	cmp	r3, #15
+ 801d58a:	d901      	bls.n	801d590 <tcp_output+0x1d4>
+ 801d58c:	2301      	movs	r3, #1
+ 801d58e:	e000      	b.n	801d592 <tcp_output+0x1d6>
+ 801d590:	2300      	movs	r3, #0
+ 801d592:	2b00      	cmp	r3, #0
+ 801d594:	d106      	bne.n	801d5a4 <tcp_output+0x1e8>
+        ((pcb->flags & (TF_NAGLEMEMERR | TF_FIN)) == 0)) {
+ 801d596:	687b      	ldr	r3, [r7, #4]
+ 801d598:	8b5b      	ldrh	r3, [r3, #26]
+ 801d59a:	f003 03a0 	and.w	r3, r3, #160	; 0xa0
+    if ((tcp_do_output_nagle(pcb) == 0) &&
+ 801d59e:	2b00      	cmp	r3, #0
+ 801d5a0:	f000 80e7 	beq.w	801d772 <tcp_output+0x3b6>
+                                 pcb->lastack,
+                                 lwip_ntohl(seg->tcphdr->seqno), pcb->lastack, i));
+    ++i;
+#endif /* TCP_CWND_DEBUG */
+
+    if (pcb->state != SYN_SENT) {
+ 801d5a4:	687b      	ldr	r3, [r7, #4]
+ 801d5a6:	7d1b      	ldrb	r3, [r3, #20]
+ 801d5a8:	2b02      	cmp	r3, #2
+ 801d5aa:	d00d      	beq.n	801d5c8 <tcp_output+0x20c>
+      TCPH_SET_FLAG(seg->tcphdr, TCP_ACK);
+ 801d5ac:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 801d5ae:	691b      	ldr	r3, [r3, #16]
+ 801d5b0:	899b      	ldrh	r3, [r3, #12]
+ 801d5b2:	b29c      	uxth	r4, r3
+ 801d5b4:	2010      	movs	r0, #16
+ 801d5b6:	f7f8 fcc3 	bl	8015f40 <lwip_htons>
+ 801d5ba:	4603      	mov	r3, r0
+ 801d5bc:	461a      	mov	r2, r3
+ 801d5be:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 801d5c0:	691b      	ldr	r3, [r3, #16]
+ 801d5c2:	4322      	orrs	r2, r4
+ 801d5c4:	b292      	uxth	r2, r2
+ 801d5c6:	819a      	strh	r2, [r3, #12]
+    }
+
+    err = tcp_output_segment(seg, pcb, netif);
+ 801d5c8:	697a      	ldr	r2, [r7, #20]
+ 801d5ca:	6879      	ldr	r1, [r7, #4]
+ 801d5cc:	6a78      	ldr	r0, [r7, #36]	; 0x24
+ 801d5ce:	f000 f90b 	bl	801d7e8 <tcp_output_segment>
+ 801d5d2:	4603      	mov	r3, r0
+ 801d5d4:	73fb      	strb	r3, [r7, #15]
+    if (err != ERR_OK) {
+ 801d5d6:	f997 300f 	ldrsb.w	r3, [r7, #15]
+ 801d5da:	2b00      	cmp	r3, #0
+ 801d5dc:	d016      	beq.n	801d60c <tcp_output+0x250>
+      /* segment could not be sent, for whatever reason */
+      tcp_set_flags(pcb, TF_NAGLEMEMERR);
+ 801d5de:	687b      	ldr	r3, [r7, #4]
+ 801d5e0:	8b5b      	ldrh	r3, [r3, #26]
+ 801d5e2:	f043 0380 	orr.w	r3, r3, #128	; 0x80
+ 801d5e6:	b29a      	uxth	r2, r3
+ 801d5e8:	687b      	ldr	r3, [r7, #4]
+ 801d5ea:	835a      	strh	r2, [r3, #26]
+      return err;
+ 801d5ec:	f997 300f 	ldrsb.w	r3, [r7, #15]
+ 801d5f0:	e0d6      	b.n	801d7a0 <tcp_output+0x3e4>
+ 801d5f2:	bf00      	nop
+ 801d5f4:	080257b8 	.word	0x080257b8
+ 801d5f8:	08025d58 	.word	0x08025d58
+ 801d5fc:	0802580c 	.word	0x0802580c
+ 801d600:	08025d70 	.word	0x08025d70
+ 801d604:	2401a4d0 	.word	0x2401a4d0
+ 801d608:	08025d98 	.word	0x08025d98
+    }
+#if TCP_OVERSIZE_DBGCHECK
+    seg->oversize_left = 0;
+ 801d60c:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 801d60e:	2200      	movs	r2, #0
+ 801d610:	815a      	strh	r2, [r3, #10]
+#endif /* TCP_OVERSIZE_DBGCHECK */
+    pcb->unsent = seg->next;
+ 801d612:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 801d614:	681a      	ldr	r2, [r3, #0]
+ 801d616:	687b      	ldr	r3, [r7, #4]
+ 801d618:	66da      	str	r2, [r3, #108]	; 0x6c
+    if (pcb->state != SYN_SENT) {
+ 801d61a:	687b      	ldr	r3, [r7, #4]
+ 801d61c:	7d1b      	ldrb	r3, [r3, #20]
+ 801d61e:	2b02      	cmp	r3, #2
+ 801d620:	d006      	beq.n	801d630 <tcp_output+0x274>
+      tcp_clear_flags(pcb, TF_ACK_DELAY | TF_ACK_NOW);
+ 801d622:	687b      	ldr	r3, [r7, #4]
+ 801d624:	8b5b      	ldrh	r3, [r3, #26]
+ 801d626:	f023 0303 	bic.w	r3, r3, #3
+ 801d62a:	b29a      	uxth	r2, r3
+ 801d62c:	687b      	ldr	r3, [r7, #4]
+ 801d62e:	835a      	strh	r2, [r3, #26]
+    }
+    snd_nxt = lwip_ntohl(seg->tcphdr->seqno) + TCP_TCPLEN(seg);
+ 801d630:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 801d632:	691b      	ldr	r3, [r3, #16]
+ 801d634:	685b      	ldr	r3, [r3, #4]
+ 801d636:	4618      	mov	r0, r3
+ 801d638:	f7f8 fc97 	bl	8015f6a <lwip_htonl>
+ 801d63c:	4604      	mov	r4, r0
+ 801d63e:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 801d640:	891b      	ldrh	r3, [r3, #8]
+ 801d642:	461d      	mov	r5, r3
+ 801d644:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 801d646:	691b      	ldr	r3, [r3, #16]
+ 801d648:	899b      	ldrh	r3, [r3, #12]
+ 801d64a:	b29b      	uxth	r3, r3
+ 801d64c:	4618      	mov	r0, r3
+ 801d64e:	f7f8 fc77 	bl	8015f40 <lwip_htons>
+ 801d652:	4603      	mov	r3, r0
+ 801d654:	b2db      	uxtb	r3, r3
+ 801d656:	f003 0303 	and.w	r3, r3, #3
+ 801d65a:	2b00      	cmp	r3, #0
+ 801d65c:	d001      	beq.n	801d662 <tcp_output+0x2a6>
+ 801d65e:	2301      	movs	r3, #1
+ 801d660:	e000      	b.n	801d664 <tcp_output+0x2a8>
+ 801d662:	2300      	movs	r3, #0
+ 801d664:	442b      	add	r3, r5
+ 801d666:	4423      	add	r3, r4
+ 801d668:	60bb      	str	r3, [r7, #8]
+    if (TCP_SEQ_LT(pcb->snd_nxt, snd_nxt)) {
+ 801d66a:	687b      	ldr	r3, [r7, #4]
+ 801d66c:	6d1a      	ldr	r2, [r3, #80]	; 0x50
+ 801d66e:	68bb      	ldr	r3, [r7, #8]
+ 801d670:	1ad3      	subs	r3, r2, r3
+ 801d672:	2b00      	cmp	r3, #0
+ 801d674:	da02      	bge.n	801d67c <tcp_output+0x2c0>
+      pcb->snd_nxt = snd_nxt;
+ 801d676:	687b      	ldr	r3, [r7, #4]
+ 801d678:	68ba      	ldr	r2, [r7, #8]
+ 801d67a:	651a      	str	r2, [r3, #80]	; 0x50
+    }
+    /* put segment on unacknowledged list if length > 0 */
+    if (TCP_TCPLEN(seg) > 0) {
+ 801d67c:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 801d67e:	891b      	ldrh	r3, [r3, #8]
+ 801d680:	461c      	mov	r4, r3
+ 801d682:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 801d684:	691b      	ldr	r3, [r3, #16]
+ 801d686:	899b      	ldrh	r3, [r3, #12]
+ 801d688:	b29b      	uxth	r3, r3
+ 801d68a:	4618      	mov	r0, r3
+ 801d68c:	f7f8 fc58 	bl	8015f40 <lwip_htons>
+ 801d690:	4603      	mov	r3, r0
+ 801d692:	b2db      	uxtb	r3, r3
+ 801d694:	f003 0303 	and.w	r3, r3, #3
+ 801d698:	2b00      	cmp	r3, #0
+ 801d69a:	d001      	beq.n	801d6a0 <tcp_output+0x2e4>
+ 801d69c:	2301      	movs	r3, #1
+ 801d69e:	e000      	b.n	801d6a2 <tcp_output+0x2e6>
+ 801d6a0:	2300      	movs	r3, #0
+ 801d6a2:	4423      	add	r3, r4
+ 801d6a4:	2b00      	cmp	r3, #0
+ 801d6a6:	d049      	beq.n	801d73c <tcp_output+0x380>
+      seg->next = NULL;
+ 801d6a8:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 801d6aa:	2200      	movs	r2, #0
+ 801d6ac:	601a      	str	r2, [r3, #0]
+      /* unacked list is empty? */
+      if (pcb->unacked == NULL) {
+ 801d6ae:	687b      	ldr	r3, [r7, #4]
+ 801d6b0:	6f1b      	ldr	r3, [r3, #112]	; 0x70
+ 801d6b2:	2b00      	cmp	r3, #0
+ 801d6b4:	d105      	bne.n	801d6c2 <tcp_output+0x306>
+        pcb->unacked = seg;
+ 801d6b6:	687b      	ldr	r3, [r7, #4]
+ 801d6b8:	6a7a      	ldr	r2, [r7, #36]	; 0x24
+ 801d6ba:	671a      	str	r2, [r3, #112]	; 0x70
+        useg = seg;
+ 801d6bc:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 801d6be:	623b      	str	r3, [r7, #32]
+ 801d6c0:	e03f      	b.n	801d742 <tcp_output+0x386>
+        /* unacked list is not empty? */
+      } else {
+        /* In the case of fast retransmit, the packet should not go to the tail
+         * of the unacked queue, but rather somewhere before it. We need to check for
+         * this case. -STJ Jul 27, 2004 */
+        if (TCP_SEQ_LT(lwip_ntohl(seg->tcphdr->seqno), lwip_ntohl(useg->tcphdr->seqno))) {
+ 801d6c2:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 801d6c4:	691b      	ldr	r3, [r3, #16]
+ 801d6c6:	685b      	ldr	r3, [r3, #4]
+ 801d6c8:	4618      	mov	r0, r3
+ 801d6ca:	f7f8 fc4e 	bl	8015f6a <lwip_htonl>
+ 801d6ce:	4604      	mov	r4, r0
+ 801d6d0:	6a3b      	ldr	r3, [r7, #32]
+ 801d6d2:	691b      	ldr	r3, [r3, #16]
+ 801d6d4:	685b      	ldr	r3, [r3, #4]
+ 801d6d6:	4618      	mov	r0, r3
+ 801d6d8:	f7f8 fc47 	bl	8015f6a <lwip_htonl>
+ 801d6dc:	4603      	mov	r3, r0
+ 801d6de:	1ae3      	subs	r3, r4, r3
+ 801d6e0:	2b00      	cmp	r3, #0
+ 801d6e2:	da24      	bge.n	801d72e <tcp_output+0x372>
+          /* add segment to before tail of unacked list, keeping the list sorted */
+          struct tcp_seg **cur_seg = &(pcb->unacked);
+ 801d6e4:	687b      	ldr	r3, [r7, #4]
+ 801d6e6:	3370      	adds	r3, #112	; 0x70
+ 801d6e8:	61fb      	str	r3, [r7, #28]
+          while (*cur_seg &&
+ 801d6ea:	e002      	b.n	801d6f2 <tcp_output+0x336>
+                 TCP_SEQ_LT(lwip_ntohl((*cur_seg)->tcphdr->seqno), lwip_ntohl(seg->tcphdr->seqno))) {
+            cur_seg = &((*cur_seg)->next );
+ 801d6ec:	69fb      	ldr	r3, [r7, #28]
+ 801d6ee:	681b      	ldr	r3, [r3, #0]
+ 801d6f0:	61fb      	str	r3, [r7, #28]
+          while (*cur_seg &&
+ 801d6f2:	69fb      	ldr	r3, [r7, #28]
+ 801d6f4:	681b      	ldr	r3, [r3, #0]
+ 801d6f6:	2b00      	cmp	r3, #0
+ 801d6f8:	d011      	beq.n	801d71e <tcp_output+0x362>
+                 TCP_SEQ_LT(lwip_ntohl((*cur_seg)->tcphdr->seqno), lwip_ntohl(seg->tcphdr->seqno))) {
+ 801d6fa:	69fb      	ldr	r3, [r7, #28]
+ 801d6fc:	681b      	ldr	r3, [r3, #0]
+ 801d6fe:	691b      	ldr	r3, [r3, #16]
+ 801d700:	685b      	ldr	r3, [r3, #4]
+ 801d702:	4618      	mov	r0, r3
+ 801d704:	f7f8 fc31 	bl	8015f6a <lwip_htonl>
+ 801d708:	4604      	mov	r4, r0
+ 801d70a:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 801d70c:	691b      	ldr	r3, [r3, #16]
+ 801d70e:	685b      	ldr	r3, [r3, #4]
+ 801d710:	4618      	mov	r0, r3
+ 801d712:	f7f8 fc2a 	bl	8015f6a <lwip_htonl>
+ 801d716:	4603      	mov	r3, r0
+ 801d718:	1ae3      	subs	r3, r4, r3
+          while (*cur_seg &&
+ 801d71a:	2b00      	cmp	r3, #0
+ 801d71c:	dbe6      	blt.n	801d6ec <tcp_output+0x330>
+          }
+          seg->next = (*cur_seg);
+ 801d71e:	69fb      	ldr	r3, [r7, #28]
+ 801d720:	681a      	ldr	r2, [r3, #0]
+ 801d722:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 801d724:	601a      	str	r2, [r3, #0]
+          (*cur_seg) = seg;
+ 801d726:	69fb      	ldr	r3, [r7, #28]
+ 801d728:	6a7a      	ldr	r2, [r7, #36]	; 0x24
+ 801d72a:	601a      	str	r2, [r3, #0]
+ 801d72c:	e009      	b.n	801d742 <tcp_output+0x386>
+        } else {
+          /* add segment to tail of unacked list */
+          useg->next = seg;
+ 801d72e:	6a3b      	ldr	r3, [r7, #32]
+ 801d730:	6a7a      	ldr	r2, [r7, #36]	; 0x24
+ 801d732:	601a      	str	r2, [r3, #0]
+          useg = useg->next;
+ 801d734:	6a3b      	ldr	r3, [r7, #32]
+ 801d736:	681b      	ldr	r3, [r3, #0]
+ 801d738:	623b      	str	r3, [r7, #32]
+ 801d73a:	e002      	b.n	801d742 <tcp_output+0x386>
+        }
+      }
+      /* do not queue empty segments on the unacked list */
+    } else {
+      tcp_seg_free(seg);
+ 801d73c:	6a78      	ldr	r0, [r7, #36]	; 0x24
+ 801d73e:	f7fb feb0 	bl	80194a2 <tcp_seg_free>
+    }
+    seg = pcb->unsent;
+ 801d742:	687b      	ldr	r3, [r7, #4]
+ 801d744:	6edb      	ldr	r3, [r3, #108]	; 0x6c
+ 801d746:	627b      	str	r3, [r7, #36]	; 0x24
+  while (seg != NULL &&
+ 801d748:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 801d74a:	2b00      	cmp	r3, #0
+ 801d74c:	d012      	beq.n	801d774 <tcp_output+0x3b8>
+         lwip_ntohl(seg->tcphdr->seqno) - pcb->lastack + seg->len <= wnd) {
+ 801d74e:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 801d750:	691b      	ldr	r3, [r3, #16]
+ 801d752:	685b      	ldr	r3, [r3, #4]
+ 801d754:	4618      	mov	r0, r3
+ 801d756:	f7f8 fc08 	bl	8015f6a <lwip_htonl>
+ 801d75a:	4602      	mov	r2, r0
+ 801d75c:	687b      	ldr	r3, [r7, #4]
+ 801d75e:	6c5b      	ldr	r3, [r3, #68]	; 0x44
+ 801d760:	1ad3      	subs	r3, r2, r3
+ 801d762:	6a7a      	ldr	r2, [r7, #36]	; 0x24
+ 801d764:	8912      	ldrh	r2, [r2, #8]
+ 801d766:	4413      	add	r3, r2
+  while (seg != NULL &&
+ 801d768:	69ba      	ldr	r2, [r7, #24]
+ 801d76a:	429a      	cmp	r2, r3
+ 801d76c:	f4bf aed6 	bcs.w	801d51c <tcp_output+0x160>
+ 801d770:	e000      	b.n	801d774 <tcp_output+0x3b8>
+      break;
+ 801d772:	bf00      	nop
+  }
+#if TCP_OVERSIZE
+  if (pcb->unsent == NULL) {
+ 801d774:	687b      	ldr	r3, [r7, #4]
+ 801d776:	6edb      	ldr	r3, [r3, #108]	; 0x6c
+ 801d778:	2b00      	cmp	r3, #0
+ 801d77a:	d108      	bne.n	801d78e <tcp_output+0x3d2>
+    /* last unsent has been removed, reset unsent_oversize */
+    pcb->unsent_oversize = 0;
+ 801d77c:	687b      	ldr	r3, [r7, #4]
+ 801d77e:	2200      	movs	r2, #0
+ 801d780:	f8a3 2068 	strh.w	r2, [r3, #104]	; 0x68
+ 801d784:	e004      	b.n	801d790 <tcp_output+0x3d4>
+    goto output_done;
+ 801d786:	bf00      	nop
+ 801d788:	e002      	b.n	801d790 <tcp_output+0x3d4>
+    goto output_done;
+ 801d78a:	bf00      	nop
+ 801d78c:	e000      	b.n	801d790 <tcp_output+0x3d4>
+  }
+#endif /* TCP_OVERSIZE */
+
+output_done:
+ 801d78e:	bf00      	nop
+  tcp_clear_flags(pcb, TF_NAGLEMEMERR);
+ 801d790:	687b      	ldr	r3, [r7, #4]
+ 801d792:	8b5b      	ldrh	r3, [r3, #26]
+ 801d794:	f023 0380 	bic.w	r3, r3, #128	; 0x80
+ 801d798:	b29a      	uxth	r2, r3
+ 801d79a:	687b      	ldr	r3, [r7, #4]
+ 801d79c:	835a      	strh	r2, [r3, #26]
+  return ERR_OK;
+ 801d79e:	2300      	movs	r3, #0
+}
+ 801d7a0:	4618      	mov	r0, r3
+ 801d7a2:	3728      	adds	r7, #40	; 0x28
+ 801d7a4:	46bd      	mov	sp, r7
+ 801d7a6:	bdb0      	pop	{r4, r5, r7, pc}
+
+0801d7a8 <tcp_output_segment_busy>:
+ * @arg seg the tcp segment to check
+ * @return 1 if ref != 1, 0 if ref == 1
+ */
+static int
+tcp_output_segment_busy(const struct tcp_seg *seg)
+{
+ 801d7a8:	b580      	push	{r7, lr}
+ 801d7aa:	b082      	sub	sp, #8
+ 801d7ac:	af00      	add	r7, sp, #0
+ 801d7ae:	6078      	str	r0, [r7, #4]
+  LWIP_ASSERT("tcp_output_segment_busy: invalid seg", seg != NULL);
+ 801d7b0:	687b      	ldr	r3, [r7, #4]
+ 801d7b2:	2b00      	cmp	r3, #0
+ 801d7b4:	d106      	bne.n	801d7c4 <tcp_output_segment_busy+0x1c>
+ 801d7b6:	4b09      	ldr	r3, [pc, #36]	; (801d7dc <tcp_output_segment_busy+0x34>)
+ 801d7b8:	f240 529a 	movw	r2, #1434	; 0x59a
+ 801d7bc:	4908      	ldr	r1, [pc, #32]	; (801d7e0 <tcp_output_segment_busy+0x38>)
+ 801d7be:	4809      	ldr	r0, [pc, #36]	; (801d7e4 <tcp_output_segment_busy+0x3c>)
+ 801d7c0:	f004 f8e2 	bl	8021988 <iprintf>
+
+  /* We only need to check the first pbuf here:
+     If a pbuf is queued for transmission, a driver calls pbuf_ref(),
+     which only changes the ref count of the first pbuf */
+  if (seg->p->ref != 1) {
+ 801d7c4:	687b      	ldr	r3, [r7, #4]
+ 801d7c6:	685b      	ldr	r3, [r3, #4]
+ 801d7c8:	7b9b      	ldrb	r3, [r3, #14]
+ 801d7ca:	2b01      	cmp	r3, #1
+ 801d7cc:	d001      	beq.n	801d7d2 <tcp_output_segment_busy+0x2a>
+    /* other reference found */
+    return 1;
+ 801d7ce:	2301      	movs	r3, #1
+ 801d7d0:	e000      	b.n	801d7d4 <tcp_output_segment_busy+0x2c>
+  }
+  /* no other references found */
+  return 0;
+ 801d7d2:	2300      	movs	r3, #0
+}
+ 801d7d4:	4618      	mov	r0, r3
+ 801d7d6:	3708      	adds	r7, #8
+ 801d7d8:	46bd      	mov	sp, r7
+ 801d7da:	bd80      	pop	{r7, pc}
+ 801d7dc:	080257b8 	.word	0x080257b8
+ 801d7e0:	08025db0 	.word	0x08025db0
+ 801d7e4:	0802580c 	.word	0x0802580c
+
+0801d7e8 <tcp_output_segment>:
+ * @param pcb the tcp_pcb for the TCP connection used to send the segment
+ * @param netif the netif used to send the segment
+ */
+static err_t
+tcp_output_segment(struct tcp_seg *seg, struct tcp_pcb *pcb, struct netif *netif)
+{
+ 801d7e8:	b5b0      	push	{r4, r5, r7, lr}
+ 801d7ea:	b08c      	sub	sp, #48	; 0x30
+ 801d7ec:	af04      	add	r7, sp, #16
+ 801d7ee:	60f8      	str	r0, [r7, #12]
+ 801d7f0:	60b9      	str	r1, [r7, #8]
+ 801d7f2:	607a      	str	r2, [r7, #4]
+  u32_t *opts;
+#if TCP_CHECKSUM_ON_COPY
+  int seg_chksum_was_swapped = 0;
+#endif
+
+  LWIP_ASSERT("tcp_output_segment: invalid seg", seg != NULL);
+ 801d7f4:	68fb      	ldr	r3, [r7, #12]
+ 801d7f6:	2b00      	cmp	r3, #0
+ 801d7f8:	d106      	bne.n	801d808 <tcp_output_segment+0x20>
+ 801d7fa:	4b64      	ldr	r3, [pc, #400]	; (801d98c <tcp_output_segment+0x1a4>)
+ 801d7fc:	f44f 62b7 	mov.w	r2, #1464	; 0x5b8
+ 801d800:	4963      	ldr	r1, [pc, #396]	; (801d990 <tcp_output_segment+0x1a8>)
+ 801d802:	4864      	ldr	r0, [pc, #400]	; (801d994 <tcp_output_segment+0x1ac>)
+ 801d804:	f004 f8c0 	bl	8021988 <iprintf>
+  LWIP_ASSERT("tcp_output_segment: invalid pcb", pcb != NULL);
+ 801d808:	68bb      	ldr	r3, [r7, #8]
+ 801d80a:	2b00      	cmp	r3, #0
+ 801d80c:	d106      	bne.n	801d81c <tcp_output_segment+0x34>
+ 801d80e:	4b5f      	ldr	r3, [pc, #380]	; (801d98c <tcp_output_segment+0x1a4>)
+ 801d810:	f240 52b9 	movw	r2, #1465	; 0x5b9
+ 801d814:	4960      	ldr	r1, [pc, #384]	; (801d998 <tcp_output_segment+0x1b0>)
+ 801d816:	485f      	ldr	r0, [pc, #380]	; (801d994 <tcp_output_segment+0x1ac>)
+ 801d818:	f004 f8b6 	bl	8021988 <iprintf>
+  LWIP_ASSERT("tcp_output_segment: invalid netif", netif != NULL);
+ 801d81c:	687b      	ldr	r3, [r7, #4]
+ 801d81e:	2b00      	cmp	r3, #0
+ 801d820:	d106      	bne.n	801d830 <tcp_output_segment+0x48>
+ 801d822:	4b5a      	ldr	r3, [pc, #360]	; (801d98c <tcp_output_segment+0x1a4>)
+ 801d824:	f240 52ba 	movw	r2, #1466	; 0x5ba
+ 801d828:	495c      	ldr	r1, [pc, #368]	; (801d99c <tcp_output_segment+0x1b4>)
+ 801d82a:	485a      	ldr	r0, [pc, #360]	; (801d994 <tcp_output_segment+0x1ac>)
+ 801d82c:	f004 f8ac 	bl	8021988 <iprintf>
+
+  if (tcp_output_segment_busy(seg)) {
+ 801d830:	68f8      	ldr	r0, [r7, #12]
+ 801d832:	f7ff ffb9 	bl	801d7a8 <tcp_output_segment_busy>
+ 801d836:	4603      	mov	r3, r0
+ 801d838:	2b00      	cmp	r3, #0
+ 801d83a:	d001      	beq.n	801d840 <tcp_output_segment+0x58>
+    /* This should not happen: rexmit functions should have checked this.
+       However, since this function modifies p->len, we must not continue in this case. */
+    LWIP_DEBUGF(TCP_RTO_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("tcp_output_segment: segment busy\n"));
+    return ERR_OK;
+ 801d83c:	2300      	movs	r3, #0
+ 801d83e:	e0a1      	b.n	801d984 <tcp_output_segment+0x19c>
+  }
+
+  /* The TCP header has already been constructed, but the ackno and
+   wnd fields remain. */
+  seg->tcphdr->ackno = lwip_htonl(pcb->rcv_nxt);
+ 801d840:	68bb      	ldr	r3, [r7, #8]
+ 801d842:	6a5a      	ldr	r2, [r3, #36]	; 0x24
+ 801d844:	68fb      	ldr	r3, [r7, #12]
+ 801d846:	691c      	ldr	r4, [r3, #16]
+ 801d848:	4610      	mov	r0, r2
+ 801d84a:	f7f8 fb8e 	bl	8015f6a <lwip_htonl>
+ 801d84e:	4603      	mov	r3, r0
+ 801d850:	60a3      	str	r3, [r4, #8]
+       the window scale option) is never scaled. */
+    seg->tcphdr->wnd = lwip_htons(TCPWND_MIN16(pcb->rcv_ann_wnd));
+  } else
+#endif /* LWIP_WND_SCALE */
+  {
+    seg->tcphdr->wnd = lwip_htons(TCPWND_MIN16(RCV_WND_SCALE(pcb, pcb->rcv_ann_wnd)));
+ 801d852:	68bb      	ldr	r3, [r7, #8]
+ 801d854:	8d5a      	ldrh	r2, [r3, #42]	; 0x2a
+ 801d856:	68fb      	ldr	r3, [r7, #12]
+ 801d858:	691c      	ldr	r4, [r3, #16]
+ 801d85a:	4610      	mov	r0, r2
+ 801d85c:	f7f8 fb70 	bl	8015f40 <lwip_htons>
+ 801d860:	4603      	mov	r3, r0
+ 801d862:	81e3      	strh	r3, [r4, #14]
+  }
+
+  pcb->rcv_ann_right_edge = pcb->rcv_nxt + pcb->rcv_ann_wnd;
+ 801d864:	68bb      	ldr	r3, [r7, #8]
+ 801d866:	6a5b      	ldr	r3, [r3, #36]	; 0x24
+ 801d868:	68ba      	ldr	r2, [r7, #8]
+ 801d86a:	8d52      	ldrh	r2, [r2, #42]	; 0x2a
+ 801d86c:	441a      	add	r2, r3
+ 801d86e:	68bb      	ldr	r3, [r7, #8]
+ 801d870:	62da      	str	r2, [r3, #44]	; 0x2c
+
+  /* Add any requested options.  NB MSS option is only set on SYN
+     packets, so ignore it here */
+  /* cast through void* to get rid of alignment warnings */
+  opts = (u32_t *)(void *)(seg->tcphdr + 1);
+ 801d872:	68fb      	ldr	r3, [r7, #12]
+ 801d874:	691b      	ldr	r3, [r3, #16]
+ 801d876:	3314      	adds	r3, #20
+ 801d878:	61fb      	str	r3, [r7, #28]
+  if (seg->flags & TF_SEG_OPTS_MSS) {
+ 801d87a:	68fb      	ldr	r3, [r7, #12]
+ 801d87c:	7b1b      	ldrb	r3, [r3, #12]
+ 801d87e:	f003 0301 	and.w	r3, r3, #1
+ 801d882:	2b00      	cmp	r3, #0
+ 801d884:	d015      	beq.n	801d8b2 <tcp_output_segment+0xca>
+    u16_t mss;
+#if TCP_CALCULATE_EFF_SEND_MSS
+    mss = tcp_eff_send_mss_netif(TCP_MSS, netif, &pcb->remote_ip);
+ 801d886:	68bb      	ldr	r3, [r7, #8]
+ 801d888:	3304      	adds	r3, #4
+ 801d88a:	461a      	mov	r2, r3
+ 801d88c:	6879      	ldr	r1, [r7, #4]
+ 801d88e:	f240 50b4 	movw	r0, #1460	; 0x5b4
+ 801d892:	f7fc f9cb 	bl	8019c2c <tcp_eff_send_mss_netif>
+ 801d896:	4603      	mov	r3, r0
+ 801d898:	837b      	strh	r3, [r7, #26]
+#else /* TCP_CALCULATE_EFF_SEND_MSS */
+    mss = TCP_MSS;
+#endif /* TCP_CALCULATE_EFF_SEND_MSS */
+    *opts = TCP_BUILD_MSS_OPTION(mss);
+ 801d89a:	8b7b      	ldrh	r3, [r7, #26]
+ 801d89c:	f043 7301 	orr.w	r3, r3, #33816576	; 0x2040000
+ 801d8a0:	4618      	mov	r0, r3
+ 801d8a2:	f7f8 fb62 	bl	8015f6a <lwip_htonl>
+ 801d8a6:	4602      	mov	r2, r0
+ 801d8a8:	69fb      	ldr	r3, [r7, #28]
+ 801d8aa:	601a      	str	r2, [r3, #0]
+    opts += 1;
+ 801d8ac:	69fb      	ldr	r3, [r7, #28]
+ 801d8ae:	3304      	adds	r3, #4
+ 801d8b0:	61fb      	str	r3, [r7, #28]
+  }
+#endif
+
+  /* Set retransmission timer running if it is not currently enabled
+     This must be set before checking the route. */
+  if (pcb->rtime < 0) {
+ 801d8b2:	68bb      	ldr	r3, [r7, #8]
+ 801d8b4:	f9b3 3030 	ldrsh.w	r3, [r3, #48]	; 0x30
+ 801d8b8:	2b00      	cmp	r3, #0
+ 801d8ba:	da02      	bge.n	801d8c2 <tcp_output_segment+0xda>
+    pcb->rtime = 0;
+ 801d8bc:	68bb      	ldr	r3, [r7, #8]
+ 801d8be:	2200      	movs	r2, #0
+ 801d8c0:	861a      	strh	r2, [r3, #48]	; 0x30
+  }
+
+  if (pcb->rttest == 0) {
+ 801d8c2:	68bb      	ldr	r3, [r7, #8]
+ 801d8c4:	6b5b      	ldr	r3, [r3, #52]	; 0x34
+ 801d8c6:	2b00      	cmp	r3, #0
+ 801d8c8:	d10c      	bne.n	801d8e4 <tcp_output_segment+0xfc>
+    pcb->rttest = tcp_ticks;
+ 801d8ca:	4b35      	ldr	r3, [pc, #212]	; (801d9a0 <tcp_output_segment+0x1b8>)
+ 801d8cc:	681a      	ldr	r2, [r3, #0]
+ 801d8ce:	68bb      	ldr	r3, [r7, #8]
+ 801d8d0:	635a      	str	r2, [r3, #52]	; 0x34
+    pcb->rtseq = lwip_ntohl(seg->tcphdr->seqno);
+ 801d8d2:	68fb      	ldr	r3, [r7, #12]
+ 801d8d4:	691b      	ldr	r3, [r3, #16]
+ 801d8d6:	685b      	ldr	r3, [r3, #4]
+ 801d8d8:	4618      	mov	r0, r3
+ 801d8da:	f7f8 fb46 	bl	8015f6a <lwip_htonl>
+ 801d8de:	4602      	mov	r2, r0
+ 801d8e0:	68bb      	ldr	r3, [r7, #8]
+ 801d8e2:	639a      	str	r2, [r3, #56]	; 0x38
+  }
+  LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_output_segment: %"U32_F":%"U32_F"\n",
+                                 lwip_htonl(seg->tcphdr->seqno), lwip_htonl(seg->tcphdr->seqno) +
+                                 seg->len));
+
+  len = (u16_t)((u8_t *)seg->tcphdr - (u8_t *)seg->p->payload);
+ 801d8e4:	68fb      	ldr	r3, [r7, #12]
+ 801d8e6:	691a      	ldr	r2, [r3, #16]
+ 801d8e8:	68fb      	ldr	r3, [r7, #12]
+ 801d8ea:	685b      	ldr	r3, [r3, #4]
+ 801d8ec:	685b      	ldr	r3, [r3, #4]
+ 801d8ee:	1ad3      	subs	r3, r2, r3
+ 801d8f0:	833b      	strh	r3, [r7, #24]
+  if (len == 0) {
+    /** Exclude retransmitted segments from this count. */
+    MIB2_STATS_INC(mib2.tcpoutsegs);
+  }
+
+  seg->p->len -= len;
+ 801d8f2:	68fb      	ldr	r3, [r7, #12]
+ 801d8f4:	685b      	ldr	r3, [r3, #4]
+ 801d8f6:	8959      	ldrh	r1, [r3, #10]
+ 801d8f8:	68fb      	ldr	r3, [r7, #12]
+ 801d8fa:	685b      	ldr	r3, [r3, #4]
+ 801d8fc:	8b3a      	ldrh	r2, [r7, #24]
+ 801d8fe:	1a8a      	subs	r2, r1, r2
+ 801d900:	b292      	uxth	r2, r2
+ 801d902:	815a      	strh	r2, [r3, #10]
+  seg->p->tot_len -= len;
+ 801d904:	68fb      	ldr	r3, [r7, #12]
+ 801d906:	685b      	ldr	r3, [r3, #4]
+ 801d908:	8919      	ldrh	r1, [r3, #8]
+ 801d90a:	68fb      	ldr	r3, [r7, #12]
+ 801d90c:	685b      	ldr	r3, [r3, #4]
+ 801d90e:	8b3a      	ldrh	r2, [r7, #24]
+ 801d910:	1a8a      	subs	r2, r1, r2
+ 801d912:	b292      	uxth	r2, r2
+ 801d914:	811a      	strh	r2, [r3, #8]
+
+  seg->p->payload = seg->tcphdr;
+ 801d916:	68fb      	ldr	r3, [r7, #12]
+ 801d918:	685b      	ldr	r3, [r3, #4]
+ 801d91a:	68fa      	ldr	r2, [r7, #12]
+ 801d91c:	6912      	ldr	r2, [r2, #16]
+ 801d91e:	605a      	str	r2, [r3, #4]
+
+  seg->tcphdr->chksum = 0;
+ 801d920:	68fb      	ldr	r3, [r7, #12]
+ 801d922:	691b      	ldr	r3, [r3, #16]
+ 801d924:	2200      	movs	r2, #0
+ 801d926:	741a      	strb	r2, [r3, #16]
+ 801d928:	2200      	movs	r2, #0
+ 801d92a:	745a      	strb	r2, [r3, #17]
+
+#ifdef LWIP_HOOK_TCP_OUT_ADD_TCPOPTS
+  opts = LWIP_HOOK_TCP_OUT_ADD_TCPOPTS(seg->p, seg->tcphdr, pcb, opts);
+#endif
+  LWIP_ASSERT("options not filled", (u8_t *)opts == ((u8_t *)(seg->tcphdr + 1)) + LWIP_TCP_OPT_LENGTH_SEGMENT(seg->flags, pcb));
+ 801d92c:	68fb      	ldr	r3, [r7, #12]
+ 801d92e:	691a      	ldr	r2, [r3, #16]
+ 801d930:	68fb      	ldr	r3, [r7, #12]
+ 801d932:	7b1b      	ldrb	r3, [r3, #12]
+ 801d934:	f003 0301 	and.w	r3, r3, #1
+ 801d938:	2b00      	cmp	r3, #0
+ 801d93a:	d001      	beq.n	801d940 <tcp_output_segment+0x158>
+ 801d93c:	2318      	movs	r3, #24
+ 801d93e:	e000      	b.n	801d942 <tcp_output_segment+0x15a>
+ 801d940:	2314      	movs	r3, #20
+ 801d942:	4413      	add	r3, r2
+ 801d944:	69fa      	ldr	r2, [r7, #28]
+ 801d946:	429a      	cmp	r2, r3
+ 801d948:	d006      	beq.n	801d958 <tcp_output_segment+0x170>
+ 801d94a:	4b10      	ldr	r3, [pc, #64]	; (801d98c <tcp_output_segment+0x1a4>)
+ 801d94c:	f240 621c 	movw	r2, #1564	; 0x61c
+ 801d950:	4914      	ldr	r1, [pc, #80]	; (801d9a4 <tcp_output_segment+0x1bc>)
+ 801d952:	4810      	ldr	r0, [pc, #64]	; (801d994 <tcp_output_segment+0x1ac>)
+ 801d954:	f004 f818 	bl	8021988 <iprintf>
+  }
+#endif /* CHECKSUM_GEN_TCP */
+  TCP_STATS_INC(tcp.xmit);
+
+  NETIF_SET_HINTS(netif, &(pcb->netif_hints));
+  err = ip_output_if(seg->p, &pcb->local_ip, &pcb->remote_ip, pcb->ttl,
+ 801d958:	68fb      	ldr	r3, [r7, #12]
+ 801d95a:	6858      	ldr	r0, [r3, #4]
+ 801d95c:	68b9      	ldr	r1, [r7, #8]
+ 801d95e:	68bb      	ldr	r3, [r7, #8]
+ 801d960:	1d1c      	adds	r4, r3, #4
+ 801d962:	68bb      	ldr	r3, [r7, #8]
+ 801d964:	7add      	ldrb	r5, [r3, #11]
+ 801d966:	68bb      	ldr	r3, [r7, #8]
+ 801d968:	7a9b      	ldrb	r3, [r3, #10]
+ 801d96a:	687a      	ldr	r2, [r7, #4]
+ 801d96c:	9202      	str	r2, [sp, #8]
+ 801d96e:	2206      	movs	r2, #6
+ 801d970:	9201      	str	r2, [sp, #4]
+ 801d972:	9300      	str	r3, [sp, #0]
+ 801d974:	462b      	mov	r3, r5
+ 801d976:	4622      	mov	r2, r4
+ 801d978:	f002 fc7a 	bl	8020270 <ip4_output_if>
+ 801d97c:	4603      	mov	r3, r0
+ 801d97e:	75fb      	strb	r3, [r7, #23]
+    seg->chksum = SWAP_BYTES_IN_WORD(seg->chksum);
+    seg->chksum_swapped = 1;
+  }
+#endif
+
+  return err;
+ 801d980:	f997 3017 	ldrsb.w	r3, [r7, #23]
+}
+ 801d984:	4618      	mov	r0, r3
+ 801d986:	3720      	adds	r7, #32
+ 801d988:	46bd      	mov	sp, r7
+ 801d98a:	bdb0      	pop	{r4, r5, r7, pc}
+ 801d98c:	080257b8 	.word	0x080257b8
+ 801d990:	08025dd8 	.word	0x08025dd8
+ 801d994:	0802580c 	.word	0x0802580c
+ 801d998:	08025df8 	.word	0x08025df8
+ 801d99c:	08025e18 	.word	0x08025e18
+ 801d9a0:	2401a480 	.word	0x2401a480
+ 801d9a4:	08025e3c 	.word	0x08025e3c
+
+0801d9a8 <tcp_rexmit_rto_prepare>:
+ *
+ * @param pcb the tcp_pcb for which to re-enqueue all unacked segments
+ */
+err_t
+tcp_rexmit_rto_prepare(struct tcp_pcb *pcb)
+{
+ 801d9a8:	b5b0      	push	{r4, r5, r7, lr}
+ 801d9aa:	b084      	sub	sp, #16
+ 801d9ac:	af00      	add	r7, sp, #0
+ 801d9ae:	6078      	str	r0, [r7, #4]
+  struct tcp_seg *seg;
+
+  LWIP_ASSERT("tcp_rexmit_rto_prepare: invalid pcb", pcb != NULL);
+ 801d9b0:	687b      	ldr	r3, [r7, #4]
+ 801d9b2:	2b00      	cmp	r3, #0
+ 801d9b4:	d106      	bne.n	801d9c4 <tcp_rexmit_rto_prepare+0x1c>
+ 801d9b6:	4b36      	ldr	r3, [pc, #216]	; (801da90 <tcp_rexmit_rto_prepare+0xe8>)
+ 801d9b8:	f240 6263 	movw	r2, #1635	; 0x663
+ 801d9bc:	4935      	ldr	r1, [pc, #212]	; (801da94 <tcp_rexmit_rto_prepare+0xec>)
+ 801d9be:	4836      	ldr	r0, [pc, #216]	; (801da98 <tcp_rexmit_rto_prepare+0xf0>)
+ 801d9c0:	f003 ffe2 	bl	8021988 <iprintf>
+
+  if (pcb->unacked == NULL) {
+ 801d9c4:	687b      	ldr	r3, [r7, #4]
+ 801d9c6:	6f1b      	ldr	r3, [r3, #112]	; 0x70
+ 801d9c8:	2b00      	cmp	r3, #0
+ 801d9ca:	d102      	bne.n	801d9d2 <tcp_rexmit_rto_prepare+0x2a>
+    return ERR_VAL;
+ 801d9cc:	f06f 0305 	mvn.w	r3, #5
+ 801d9d0:	e059      	b.n	801da86 <tcp_rexmit_rto_prepare+0xde>
+
+  /* Move all unacked segments to the head of the unsent queue.
+     However, give up if any of the unsent pbufs are still referenced by the
+     netif driver due to deferred transmission. No point loading the link further
+     if it is struggling to flush its buffered writes. */
+  for (seg = pcb->unacked; seg->next != NULL; seg = seg->next) {
+ 801d9d2:	687b      	ldr	r3, [r7, #4]
+ 801d9d4:	6f1b      	ldr	r3, [r3, #112]	; 0x70
+ 801d9d6:	60fb      	str	r3, [r7, #12]
+ 801d9d8:	e00b      	b.n	801d9f2 <tcp_rexmit_rto_prepare+0x4a>
+    if (tcp_output_segment_busy(seg)) {
+ 801d9da:	68f8      	ldr	r0, [r7, #12]
+ 801d9dc:	f7ff fee4 	bl	801d7a8 <tcp_output_segment_busy>
+ 801d9e0:	4603      	mov	r3, r0
+ 801d9e2:	2b00      	cmp	r3, #0
+ 801d9e4:	d002      	beq.n	801d9ec <tcp_rexmit_rto_prepare+0x44>
+      LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_rexmit_rto: segment busy\n"));
+      return ERR_VAL;
+ 801d9e6:	f06f 0305 	mvn.w	r3, #5
+ 801d9ea:	e04c      	b.n	801da86 <tcp_rexmit_rto_prepare+0xde>
+  for (seg = pcb->unacked; seg->next != NULL; seg = seg->next) {
+ 801d9ec:	68fb      	ldr	r3, [r7, #12]
+ 801d9ee:	681b      	ldr	r3, [r3, #0]
+ 801d9f0:	60fb      	str	r3, [r7, #12]
+ 801d9f2:	68fb      	ldr	r3, [r7, #12]
+ 801d9f4:	681b      	ldr	r3, [r3, #0]
+ 801d9f6:	2b00      	cmp	r3, #0
+ 801d9f8:	d1ef      	bne.n	801d9da <tcp_rexmit_rto_prepare+0x32>
+    }
+  }
+  if (tcp_output_segment_busy(seg)) {
+ 801d9fa:	68f8      	ldr	r0, [r7, #12]
+ 801d9fc:	f7ff fed4 	bl	801d7a8 <tcp_output_segment_busy>
+ 801da00:	4603      	mov	r3, r0
+ 801da02:	2b00      	cmp	r3, #0
+ 801da04:	d002      	beq.n	801da0c <tcp_rexmit_rto_prepare+0x64>
+    LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_rexmit_rto: segment busy\n"));
+    return ERR_VAL;
+ 801da06:	f06f 0305 	mvn.w	r3, #5
+ 801da0a:	e03c      	b.n	801da86 <tcp_rexmit_rto_prepare+0xde>
+  }
+  /* concatenate unsent queue after unacked queue */
+  seg->next = pcb->unsent;
+ 801da0c:	687b      	ldr	r3, [r7, #4]
+ 801da0e:	6eda      	ldr	r2, [r3, #108]	; 0x6c
+ 801da10:	68fb      	ldr	r3, [r7, #12]
+ 801da12:	601a      	str	r2, [r3, #0]
+#if TCP_OVERSIZE_DBGCHECK
+  /* if last unsent changed, we need to update unsent_oversize */
+  if (pcb->unsent == NULL) {
+ 801da14:	687b      	ldr	r3, [r7, #4]
+ 801da16:	6edb      	ldr	r3, [r3, #108]	; 0x6c
+ 801da18:	2b00      	cmp	r3, #0
+ 801da1a:	d104      	bne.n	801da26 <tcp_rexmit_rto_prepare+0x7e>
+    pcb->unsent_oversize = seg->oversize_left;
+ 801da1c:	68fb      	ldr	r3, [r7, #12]
+ 801da1e:	895a      	ldrh	r2, [r3, #10]
+ 801da20:	687b      	ldr	r3, [r7, #4]
+ 801da22:	f8a3 2068 	strh.w	r2, [r3, #104]	; 0x68
+  }
+#endif /* TCP_OVERSIZE_DBGCHECK */
+  /* unsent queue is the concatenated queue (of unacked, unsent) */
+  pcb->unsent = pcb->unacked;
+ 801da26:	687b      	ldr	r3, [r7, #4]
+ 801da28:	6f1a      	ldr	r2, [r3, #112]	; 0x70
+ 801da2a:	687b      	ldr	r3, [r7, #4]
+ 801da2c:	66da      	str	r2, [r3, #108]	; 0x6c
+  /* unacked queue is now empty */
+  pcb->unacked = NULL;
+ 801da2e:	687b      	ldr	r3, [r7, #4]
+ 801da30:	2200      	movs	r2, #0
+ 801da32:	671a      	str	r2, [r3, #112]	; 0x70
+
+  /* Mark RTO in-progress */
+  tcp_set_flags(pcb, TF_RTO);
+ 801da34:	687b      	ldr	r3, [r7, #4]
+ 801da36:	8b5b      	ldrh	r3, [r3, #26]
+ 801da38:	f443 6300 	orr.w	r3, r3, #2048	; 0x800
+ 801da3c:	b29a      	uxth	r2, r3
+ 801da3e:	687b      	ldr	r3, [r7, #4]
+ 801da40:	835a      	strh	r2, [r3, #26]
+  /* Record the next byte following retransmit */
+  pcb->rto_end = lwip_ntohl(seg->tcphdr->seqno) + TCP_TCPLEN(seg);
+ 801da42:	68fb      	ldr	r3, [r7, #12]
+ 801da44:	691b      	ldr	r3, [r3, #16]
+ 801da46:	685b      	ldr	r3, [r3, #4]
+ 801da48:	4618      	mov	r0, r3
+ 801da4a:	f7f8 fa8e 	bl	8015f6a <lwip_htonl>
+ 801da4e:	4604      	mov	r4, r0
+ 801da50:	68fb      	ldr	r3, [r7, #12]
+ 801da52:	891b      	ldrh	r3, [r3, #8]
+ 801da54:	461d      	mov	r5, r3
+ 801da56:	68fb      	ldr	r3, [r7, #12]
+ 801da58:	691b      	ldr	r3, [r3, #16]
+ 801da5a:	899b      	ldrh	r3, [r3, #12]
+ 801da5c:	b29b      	uxth	r3, r3
+ 801da5e:	4618      	mov	r0, r3
+ 801da60:	f7f8 fa6e 	bl	8015f40 <lwip_htons>
+ 801da64:	4603      	mov	r3, r0
+ 801da66:	b2db      	uxtb	r3, r3
+ 801da68:	f003 0303 	and.w	r3, r3, #3
+ 801da6c:	2b00      	cmp	r3, #0
+ 801da6e:	d001      	beq.n	801da74 <tcp_rexmit_rto_prepare+0xcc>
+ 801da70:	2301      	movs	r3, #1
+ 801da72:	e000      	b.n	801da76 <tcp_rexmit_rto_prepare+0xce>
+ 801da74:	2300      	movs	r3, #0
+ 801da76:	442b      	add	r3, r5
+ 801da78:	18e2      	adds	r2, r4, r3
+ 801da7a:	687b      	ldr	r3, [r7, #4]
+ 801da7c:	64da      	str	r2, [r3, #76]	; 0x4c
+  /* Don't take any RTT measurements after retransmitting. */
+  pcb->rttest = 0;
+ 801da7e:	687b      	ldr	r3, [r7, #4]
+ 801da80:	2200      	movs	r2, #0
+ 801da82:	635a      	str	r2, [r3, #52]	; 0x34
+
+  return ERR_OK;
+ 801da84:	2300      	movs	r3, #0
+}
+ 801da86:	4618      	mov	r0, r3
+ 801da88:	3710      	adds	r7, #16
+ 801da8a:	46bd      	mov	sp, r7
+ 801da8c:	bdb0      	pop	{r4, r5, r7, pc}
+ 801da8e:	bf00      	nop
+ 801da90:	080257b8 	.word	0x080257b8
+ 801da94:	08025e50 	.word	0x08025e50
+ 801da98:	0802580c 	.word	0x0802580c
+
+0801da9c <tcp_rexmit_rto_commit>:
+ *
+ * @param pcb the tcp_pcb for which to re-enqueue all unacked segments
+ */
+void
+tcp_rexmit_rto_commit(struct tcp_pcb *pcb)
+{
+ 801da9c:	b580      	push	{r7, lr}
+ 801da9e:	b082      	sub	sp, #8
+ 801daa0:	af00      	add	r7, sp, #0
+ 801daa2:	6078      	str	r0, [r7, #4]
+  LWIP_ASSERT("tcp_rexmit_rto_commit: invalid pcb", pcb != NULL);
+ 801daa4:	687b      	ldr	r3, [r7, #4]
+ 801daa6:	2b00      	cmp	r3, #0
+ 801daa8:	d106      	bne.n	801dab8 <tcp_rexmit_rto_commit+0x1c>
+ 801daaa:	4b0d      	ldr	r3, [pc, #52]	; (801dae0 <tcp_rexmit_rto_commit+0x44>)
+ 801daac:	f44f 62d3 	mov.w	r2, #1688	; 0x698
+ 801dab0:	490c      	ldr	r1, [pc, #48]	; (801dae4 <tcp_rexmit_rto_commit+0x48>)
+ 801dab2:	480d      	ldr	r0, [pc, #52]	; (801dae8 <tcp_rexmit_rto_commit+0x4c>)
+ 801dab4:	f003 ff68 	bl	8021988 <iprintf>
+
+  /* increment number of retransmissions */
+  if (pcb->nrtx < 0xFF) {
+ 801dab8:	687b      	ldr	r3, [r7, #4]
+ 801daba:	f893 3042 	ldrb.w	r3, [r3, #66]	; 0x42
+ 801dabe:	2bff      	cmp	r3, #255	; 0xff
+ 801dac0:	d007      	beq.n	801dad2 <tcp_rexmit_rto_commit+0x36>
+    ++pcb->nrtx;
+ 801dac2:	687b      	ldr	r3, [r7, #4]
+ 801dac4:	f893 3042 	ldrb.w	r3, [r3, #66]	; 0x42
+ 801dac8:	3301      	adds	r3, #1
+ 801daca:	b2da      	uxtb	r2, r3
+ 801dacc:	687b      	ldr	r3, [r7, #4]
+ 801dace:	f883 2042 	strb.w	r2, [r3, #66]	; 0x42
+  }
+  /* Do the actual retransmission */
+  tcp_output(pcb);
+ 801dad2:	6878      	ldr	r0, [r7, #4]
+ 801dad4:	f7ff fc72 	bl	801d3bc <tcp_output>
+}
+ 801dad8:	bf00      	nop
+ 801dada:	3708      	adds	r7, #8
+ 801dadc:	46bd      	mov	sp, r7
+ 801dade:	bd80      	pop	{r7, pc}
+ 801dae0:	080257b8 	.word	0x080257b8
+ 801dae4:	08025e74 	.word	0x08025e74
+ 801dae8:	0802580c 	.word	0x0802580c
+
+0801daec <tcp_rexmit_rto>:
+ *
+ * @param pcb the tcp_pcb for which to re-enqueue all unacked segments
+ */
+void
+tcp_rexmit_rto(struct tcp_pcb *pcb)
+{
+ 801daec:	b580      	push	{r7, lr}
+ 801daee:	b082      	sub	sp, #8
+ 801daf0:	af00      	add	r7, sp, #0
+ 801daf2:	6078      	str	r0, [r7, #4]
+  LWIP_ASSERT("tcp_rexmit_rto: invalid pcb", pcb != NULL);
+ 801daf4:	687b      	ldr	r3, [r7, #4]
+ 801daf6:	2b00      	cmp	r3, #0
+ 801daf8:	d106      	bne.n	801db08 <tcp_rexmit_rto+0x1c>
+ 801dafa:	4b0a      	ldr	r3, [pc, #40]	; (801db24 <tcp_rexmit_rto+0x38>)
+ 801dafc:	f240 62ad 	movw	r2, #1709	; 0x6ad
+ 801db00:	4909      	ldr	r1, [pc, #36]	; (801db28 <tcp_rexmit_rto+0x3c>)
+ 801db02:	480a      	ldr	r0, [pc, #40]	; (801db2c <tcp_rexmit_rto+0x40>)
+ 801db04:	f003 ff40 	bl	8021988 <iprintf>
+
+  if (tcp_rexmit_rto_prepare(pcb) == ERR_OK) {
+ 801db08:	6878      	ldr	r0, [r7, #4]
+ 801db0a:	f7ff ff4d 	bl	801d9a8 <tcp_rexmit_rto_prepare>
+ 801db0e:	4603      	mov	r3, r0
+ 801db10:	2b00      	cmp	r3, #0
+ 801db12:	d102      	bne.n	801db1a <tcp_rexmit_rto+0x2e>
+    tcp_rexmit_rto_commit(pcb);
+ 801db14:	6878      	ldr	r0, [r7, #4]
+ 801db16:	f7ff ffc1 	bl	801da9c <tcp_rexmit_rto_commit>
+  }
+}
+ 801db1a:	bf00      	nop
+ 801db1c:	3708      	adds	r7, #8
+ 801db1e:	46bd      	mov	sp, r7
+ 801db20:	bd80      	pop	{r7, pc}
+ 801db22:	bf00      	nop
+ 801db24:	080257b8 	.word	0x080257b8
+ 801db28:	08025e98 	.word	0x08025e98
+ 801db2c:	0802580c 	.word	0x0802580c
+
+0801db30 <tcp_rexmit>:
+ *
+ * @param pcb the tcp_pcb for which to retransmit the first unacked segment
+ */
+err_t
+tcp_rexmit(struct tcp_pcb *pcb)
+{
+ 801db30:	b590      	push	{r4, r7, lr}
+ 801db32:	b085      	sub	sp, #20
+ 801db34:	af00      	add	r7, sp, #0
+ 801db36:	6078      	str	r0, [r7, #4]
+  struct tcp_seg *seg;
+  struct tcp_seg **cur_seg;
+
+  LWIP_ASSERT("tcp_rexmit: invalid pcb", pcb != NULL);
+ 801db38:	687b      	ldr	r3, [r7, #4]
+ 801db3a:	2b00      	cmp	r3, #0
+ 801db3c:	d106      	bne.n	801db4c <tcp_rexmit+0x1c>
+ 801db3e:	4b2f      	ldr	r3, [pc, #188]	; (801dbfc <tcp_rexmit+0xcc>)
+ 801db40:	f240 62c1 	movw	r2, #1729	; 0x6c1
+ 801db44:	492e      	ldr	r1, [pc, #184]	; (801dc00 <tcp_rexmit+0xd0>)
+ 801db46:	482f      	ldr	r0, [pc, #188]	; (801dc04 <tcp_rexmit+0xd4>)
+ 801db48:	f003 ff1e 	bl	8021988 <iprintf>
+
+  if (pcb->unacked == NULL) {
+ 801db4c:	687b      	ldr	r3, [r7, #4]
+ 801db4e:	6f1b      	ldr	r3, [r3, #112]	; 0x70
+ 801db50:	2b00      	cmp	r3, #0
+ 801db52:	d102      	bne.n	801db5a <tcp_rexmit+0x2a>
+    return ERR_VAL;
+ 801db54:	f06f 0305 	mvn.w	r3, #5
+ 801db58:	e04c      	b.n	801dbf4 <tcp_rexmit+0xc4>
+  }
+
+  seg = pcb->unacked;
+ 801db5a:	687b      	ldr	r3, [r7, #4]
+ 801db5c:	6f1b      	ldr	r3, [r3, #112]	; 0x70
+ 801db5e:	60bb      	str	r3, [r7, #8]
+
+  /* Give up if the segment is still referenced by the netif driver
+     due to deferred transmission. */
+  if (tcp_output_segment_busy(seg)) {
+ 801db60:	68b8      	ldr	r0, [r7, #8]
+ 801db62:	f7ff fe21 	bl	801d7a8 <tcp_output_segment_busy>
+ 801db66:	4603      	mov	r3, r0
+ 801db68:	2b00      	cmp	r3, #0
+ 801db6a:	d002      	beq.n	801db72 <tcp_rexmit+0x42>
+    LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_rexmit busy\n"));
+    return ERR_VAL;
+ 801db6c:	f06f 0305 	mvn.w	r3, #5
+ 801db70:	e040      	b.n	801dbf4 <tcp_rexmit+0xc4>
+  }
+
+  /* Move the first unacked segment to the unsent queue */
+  /* Keep the unsent queue sorted. */
+  pcb->unacked = seg->next;
+ 801db72:	68bb      	ldr	r3, [r7, #8]
+ 801db74:	681a      	ldr	r2, [r3, #0]
+ 801db76:	687b      	ldr	r3, [r7, #4]
+ 801db78:	671a      	str	r2, [r3, #112]	; 0x70
+
+  cur_seg = &(pcb->unsent);
+ 801db7a:	687b      	ldr	r3, [r7, #4]
+ 801db7c:	336c      	adds	r3, #108	; 0x6c
+ 801db7e:	60fb      	str	r3, [r7, #12]
+  while (*cur_seg &&
+ 801db80:	e002      	b.n	801db88 <tcp_rexmit+0x58>
+         TCP_SEQ_LT(lwip_ntohl((*cur_seg)->tcphdr->seqno), lwip_ntohl(seg->tcphdr->seqno))) {
+    cur_seg = &((*cur_seg)->next );
+ 801db82:	68fb      	ldr	r3, [r7, #12]
+ 801db84:	681b      	ldr	r3, [r3, #0]
+ 801db86:	60fb      	str	r3, [r7, #12]
+  while (*cur_seg &&
+ 801db88:	68fb      	ldr	r3, [r7, #12]
+ 801db8a:	681b      	ldr	r3, [r3, #0]
+ 801db8c:	2b00      	cmp	r3, #0
+ 801db8e:	d011      	beq.n	801dbb4 <tcp_rexmit+0x84>
+         TCP_SEQ_LT(lwip_ntohl((*cur_seg)->tcphdr->seqno), lwip_ntohl(seg->tcphdr->seqno))) {
+ 801db90:	68fb      	ldr	r3, [r7, #12]
+ 801db92:	681b      	ldr	r3, [r3, #0]
+ 801db94:	691b      	ldr	r3, [r3, #16]
+ 801db96:	685b      	ldr	r3, [r3, #4]
+ 801db98:	4618      	mov	r0, r3
+ 801db9a:	f7f8 f9e6 	bl	8015f6a <lwip_htonl>
+ 801db9e:	4604      	mov	r4, r0
+ 801dba0:	68bb      	ldr	r3, [r7, #8]
+ 801dba2:	691b      	ldr	r3, [r3, #16]
+ 801dba4:	685b      	ldr	r3, [r3, #4]
+ 801dba6:	4618      	mov	r0, r3
+ 801dba8:	f7f8 f9df 	bl	8015f6a <lwip_htonl>
+ 801dbac:	4603      	mov	r3, r0
+ 801dbae:	1ae3      	subs	r3, r4, r3
+  while (*cur_seg &&
+ 801dbb0:	2b00      	cmp	r3, #0
+ 801dbb2:	dbe6      	blt.n	801db82 <tcp_rexmit+0x52>
+  }
+  seg->next = *cur_seg;
+ 801dbb4:	68fb      	ldr	r3, [r7, #12]
+ 801dbb6:	681a      	ldr	r2, [r3, #0]
+ 801dbb8:	68bb      	ldr	r3, [r7, #8]
+ 801dbba:	601a      	str	r2, [r3, #0]
+  *cur_seg = seg;
+ 801dbbc:	68fb      	ldr	r3, [r7, #12]
+ 801dbbe:	68ba      	ldr	r2, [r7, #8]
+ 801dbc0:	601a      	str	r2, [r3, #0]
+#if TCP_OVERSIZE
+  if (seg->next == NULL) {
+ 801dbc2:	68bb      	ldr	r3, [r7, #8]
+ 801dbc4:	681b      	ldr	r3, [r3, #0]
+ 801dbc6:	2b00      	cmp	r3, #0
+ 801dbc8:	d103      	bne.n	801dbd2 <tcp_rexmit+0xa2>
+    /* the retransmitted segment is last in unsent, so reset unsent_oversize */
+    pcb->unsent_oversize = 0;
+ 801dbca:	687b      	ldr	r3, [r7, #4]
+ 801dbcc:	2200      	movs	r2, #0
+ 801dbce:	f8a3 2068 	strh.w	r2, [r3, #104]	; 0x68
+  }
+#endif /* TCP_OVERSIZE */
+
+  if (pcb->nrtx < 0xFF) {
+ 801dbd2:	687b      	ldr	r3, [r7, #4]
+ 801dbd4:	f893 3042 	ldrb.w	r3, [r3, #66]	; 0x42
+ 801dbd8:	2bff      	cmp	r3, #255	; 0xff
+ 801dbda:	d007      	beq.n	801dbec <tcp_rexmit+0xbc>
+    ++pcb->nrtx;
+ 801dbdc:	687b      	ldr	r3, [r7, #4]
+ 801dbde:	f893 3042 	ldrb.w	r3, [r3, #66]	; 0x42
+ 801dbe2:	3301      	adds	r3, #1
+ 801dbe4:	b2da      	uxtb	r2, r3
+ 801dbe6:	687b      	ldr	r3, [r7, #4]
+ 801dbe8:	f883 2042 	strb.w	r2, [r3, #66]	; 0x42
+  }
+
+  /* Don't take any rtt measurements after retransmitting. */
+  pcb->rttest = 0;
+ 801dbec:	687b      	ldr	r3, [r7, #4]
+ 801dbee:	2200      	movs	r2, #0
+ 801dbf0:	635a      	str	r2, [r3, #52]	; 0x34
+
+  /* Do the actual retransmission. */
+  MIB2_STATS_INC(mib2.tcpretranssegs);
+  /* No need to call tcp_output: we are always called from tcp_input()
+     and thus tcp_output directly returns. */
+  return ERR_OK;
+ 801dbf2:	2300      	movs	r3, #0
+}
+ 801dbf4:	4618      	mov	r0, r3
+ 801dbf6:	3714      	adds	r7, #20
+ 801dbf8:	46bd      	mov	sp, r7
+ 801dbfa:	bd90      	pop	{r4, r7, pc}
+ 801dbfc:	080257b8 	.word	0x080257b8
+ 801dc00:	08025eb4 	.word	0x08025eb4
+ 801dc04:	0802580c 	.word	0x0802580c
+
+0801dc08 <tcp_rexmit_fast>:
+ *
+ * @param pcb the tcp_pcb for which to retransmit the first unacked segment
+ */
+void
+tcp_rexmit_fast(struct tcp_pcb *pcb)
+{
+ 801dc08:	b580      	push	{r7, lr}
+ 801dc0a:	b082      	sub	sp, #8
+ 801dc0c:	af00      	add	r7, sp, #0
+ 801dc0e:	6078      	str	r0, [r7, #4]
+  LWIP_ASSERT("tcp_rexmit_fast: invalid pcb", pcb != NULL);
+ 801dc10:	687b      	ldr	r3, [r7, #4]
+ 801dc12:	2b00      	cmp	r3, #0
+ 801dc14:	d106      	bne.n	801dc24 <tcp_rexmit_fast+0x1c>
+ 801dc16:	4b2a      	ldr	r3, [pc, #168]	; (801dcc0 <tcp_rexmit_fast+0xb8>)
+ 801dc18:	f240 62f9 	movw	r2, #1785	; 0x6f9
+ 801dc1c:	4929      	ldr	r1, [pc, #164]	; (801dcc4 <tcp_rexmit_fast+0xbc>)
+ 801dc1e:	482a      	ldr	r0, [pc, #168]	; (801dcc8 <tcp_rexmit_fast+0xc0>)
+ 801dc20:	f003 feb2 	bl	8021988 <iprintf>
+
+  if (pcb->unacked != NULL && !(pcb->flags & TF_INFR)) {
+ 801dc24:	687b      	ldr	r3, [r7, #4]
+ 801dc26:	6f1b      	ldr	r3, [r3, #112]	; 0x70
+ 801dc28:	2b00      	cmp	r3, #0
+ 801dc2a:	d045      	beq.n	801dcb8 <tcp_rexmit_fast+0xb0>
+ 801dc2c:	687b      	ldr	r3, [r7, #4]
+ 801dc2e:	8b5b      	ldrh	r3, [r3, #26]
+ 801dc30:	f003 0304 	and.w	r3, r3, #4
+ 801dc34:	2b00      	cmp	r3, #0
+ 801dc36:	d13f      	bne.n	801dcb8 <tcp_rexmit_fast+0xb0>
+    LWIP_DEBUGF(TCP_FR_DEBUG,
+                ("tcp_receive: dupacks %"U16_F" (%"U32_F
+                 "), fast retransmit %"U32_F"\n",
+                 (u16_t)pcb->dupacks, pcb->lastack,
+                 lwip_ntohl(pcb->unacked->tcphdr->seqno)));
+    if (tcp_rexmit(pcb) == ERR_OK) {
+ 801dc38:	6878      	ldr	r0, [r7, #4]
+ 801dc3a:	f7ff ff79 	bl	801db30 <tcp_rexmit>
+ 801dc3e:	4603      	mov	r3, r0
+ 801dc40:	2b00      	cmp	r3, #0
+ 801dc42:	d139      	bne.n	801dcb8 <tcp_rexmit_fast+0xb0>
+      /* Set ssthresh to half of the minimum of the current
+       * cwnd and the advertised window */
+      pcb->ssthresh = LWIP_MIN(pcb->cwnd, pcb->snd_wnd) / 2;
+ 801dc44:	687b      	ldr	r3, [r7, #4]
+ 801dc46:	f8b3 2060 	ldrh.w	r2, [r3, #96]	; 0x60
+ 801dc4a:	687b      	ldr	r3, [r7, #4]
+ 801dc4c:	f8b3 3048 	ldrh.w	r3, [r3, #72]	; 0x48
+ 801dc50:	4293      	cmp	r3, r2
+ 801dc52:	bf28      	it	cs
+ 801dc54:	4613      	movcs	r3, r2
+ 801dc56:	b29b      	uxth	r3, r3
+ 801dc58:	2b00      	cmp	r3, #0
+ 801dc5a:	da00      	bge.n	801dc5e <tcp_rexmit_fast+0x56>
+ 801dc5c:	3301      	adds	r3, #1
+ 801dc5e:	105b      	asrs	r3, r3, #1
+ 801dc60:	b29a      	uxth	r2, r3
+ 801dc62:	687b      	ldr	r3, [r7, #4]
+ 801dc64:	f8a3 204a 	strh.w	r2, [r3, #74]	; 0x4a
+
+      /* The minimum value for ssthresh should be 2 MSS */
+      if (pcb->ssthresh < (2U * pcb->mss)) {
+ 801dc68:	687b      	ldr	r3, [r7, #4]
+ 801dc6a:	f8b3 304a 	ldrh.w	r3, [r3, #74]	; 0x4a
+ 801dc6e:	461a      	mov	r2, r3
+ 801dc70:	687b      	ldr	r3, [r7, #4]
+ 801dc72:	8e5b      	ldrh	r3, [r3, #50]	; 0x32
+ 801dc74:	005b      	lsls	r3, r3, #1
+ 801dc76:	429a      	cmp	r2, r3
+ 801dc78:	d206      	bcs.n	801dc88 <tcp_rexmit_fast+0x80>
+        LWIP_DEBUGF(TCP_FR_DEBUG,
+                    ("tcp_receive: The minimum value for ssthresh %"TCPWNDSIZE_F
+                     " should be min 2 mss %"U16_F"...\n",
+                     pcb->ssthresh, (u16_t)(2 * pcb->mss)));
+        pcb->ssthresh = 2 * pcb->mss;
+ 801dc7a:	687b      	ldr	r3, [r7, #4]
+ 801dc7c:	8e5b      	ldrh	r3, [r3, #50]	; 0x32
+ 801dc7e:	005b      	lsls	r3, r3, #1
+ 801dc80:	b29a      	uxth	r2, r3
+ 801dc82:	687b      	ldr	r3, [r7, #4]
+ 801dc84:	f8a3 204a 	strh.w	r2, [r3, #74]	; 0x4a
+      }
+
+      pcb->cwnd = pcb->ssthresh + 3 * pcb->mss;
+ 801dc88:	687b      	ldr	r3, [r7, #4]
+ 801dc8a:	f8b3 204a 	ldrh.w	r2, [r3, #74]	; 0x4a
+ 801dc8e:	687b      	ldr	r3, [r7, #4]
+ 801dc90:	8e5b      	ldrh	r3, [r3, #50]	; 0x32
+ 801dc92:	4619      	mov	r1, r3
+ 801dc94:	0049      	lsls	r1, r1, #1
+ 801dc96:	440b      	add	r3, r1
+ 801dc98:	b29b      	uxth	r3, r3
+ 801dc9a:	4413      	add	r3, r2
+ 801dc9c:	b29a      	uxth	r2, r3
+ 801dc9e:	687b      	ldr	r3, [r7, #4]
+ 801dca0:	f8a3 2048 	strh.w	r2, [r3, #72]	; 0x48
+      tcp_set_flags(pcb, TF_INFR);
+ 801dca4:	687b      	ldr	r3, [r7, #4]
+ 801dca6:	8b5b      	ldrh	r3, [r3, #26]
+ 801dca8:	f043 0304 	orr.w	r3, r3, #4
+ 801dcac:	b29a      	uxth	r2, r3
+ 801dcae:	687b      	ldr	r3, [r7, #4]
+ 801dcb0:	835a      	strh	r2, [r3, #26]
+
+      /* Reset the retransmission timer to prevent immediate rto retransmissions */
+      pcb->rtime = 0;
+ 801dcb2:	687b      	ldr	r3, [r7, #4]
+ 801dcb4:	2200      	movs	r2, #0
+ 801dcb6:	861a      	strh	r2, [r3, #48]	; 0x30
+    }
+  }
+}
+ 801dcb8:	bf00      	nop
+ 801dcba:	3708      	adds	r7, #8
+ 801dcbc:	46bd      	mov	sp, r7
+ 801dcbe:	bd80      	pop	{r7, pc}
+ 801dcc0:	080257b8 	.word	0x080257b8
+ 801dcc4:	08025ecc 	.word	0x08025ecc
+ 801dcc8:	0802580c 	.word	0x0802580c
+
+0801dccc <tcp_output_alloc_header_common>:
+
+static struct pbuf *
+tcp_output_alloc_header_common(u32_t ackno, u16_t optlen, u16_t datalen,
+                        u32_t seqno_be /* already in network byte order */,
+                        u16_t src_port, u16_t dst_port, u8_t flags, u16_t wnd)
+{
+ 801dccc:	b580      	push	{r7, lr}
+ 801dcce:	b086      	sub	sp, #24
+ 801dcd0:	af00      	add	r7, sp, #0
+ 801dcd2:	60f8      	str	r0, [r7, #12]
+ 801dcd4:	607b      	str	r3, [r7, #4]
+ 801dcd6:	460b      	mov	r3, r1
+ 801dcd8:	817b      	strh	r3, [r7, #10]
+ 801dcda:	4613      	mov	r3, r2
+ 801dcdc:	813b      	strh	r3, [r7, #8]
+  struct tcp_hdr *tcphdr;
+  struct pbuf *p;
+
+  p = pbuf_alloc(PBUF_IP, TCP_HLEN + optlen + datalen, PBUF_RAM);
+ 801dcde:	897a      	ldrh	r2, [r7, #10]
+ 801dce0:	893b      	ldrh	r3, [r7, #8]
+ 801dce2:	4413      	add	r3, r2
+ 801dce4:	b29b      	uxth	r3, r3
+ 801dce6:	3314      	adds	r3, #20
+ 801dce8:	b29b      	uxth	r3, r3
+ 801dcea:	f44f 7220 	mov.w	r2, #640	; 0x280
+ 801dcee:	4619      	mov	r1, r3
+ 801dcf0:	2022      	movs	r0, #34	; 0x22
+ 801dcf2:	f7f9 fc19 	bl	8017528 <pbuf_alloc>
+ 801dcf6:	6178      	str	r0, [r7, #20]
+  if (p != NULL) {
+ 801dcf8:	697b      	ldr	r3, [r7, #20]
+ 801dcfa:	2b00      	cmp	r3, #0
+ 801dcfc:	d04d      	beq.n	801dd9a <tcp_output_alloc_header_common+0xce>
+    LWIP_ASSERT("check that first pbuf can hold struct tcp_hdr",
+ 801dcfe:	897b      	ldrh	r3, [r7, #10]
+ 801dd00:	3313      	adds	r3, #19
+ 801dd02:	697a      	ldr	r2, [r7, #20]
+ 801dd04:	8952      	ldrh	r2, [r2, #10]
+ 801dd06:	4293      	cmp	r3, r2
+ 801dd08:	db06      	blt.n	801dd18 <tcp_output_alloc_header_common+0x4c>
+ 801dd0a:	4b26      	ldr	r3, [pc, #152]	; (801dda4 <tcp_output_alloc_header_common+0xd8>)
+ 801dd0c:	f240 7223 	movw	r2, #1827	; 0x723
+ 801dd10:	4925      	ldr	r1, [pc, #148]	; (801dda8 <tcp_output_alloc_header_common+0xdc>)
+ 801dd12:	4826      	ldr	r0, [pc, #152]	; (801ddac <tcp_output_alloc_header_common+0xe0>)
+ 801dd14:	f003 fe38 	bl	8021988 <iprintf>
+                (p->len >= TCP_HLEN + optlen));
+    tcphdr = (struct tcp_hdr *)p->payload;
+ 801dd18:	697b      	ldr	r3, [r7, #20]
+ 801dd1a:	685b      	ldr	r3, [r3, #4]
+ 801dd1c:	613b      	str	r3, [r7, #16]
+    tcphdr->src = lwip_htons(src_port);
+ 801dd1e:	8c3b      	ldrh	r3, [r7, #32]
+ 801dd20:	4618      	mov	r0, r3
+ 801dd22:	f7f8 f90d 	bl	8015f40 <lwip_htons>
+ 801dd26:	4603      	mov	r3, r0
+ 801dd28:	461a      	mov	r2, r3
+ 801dd2a:	693b      	ldr	r3, [r7, #16]
+ 801dd2c:	801a      	strh	r2, [r3, #0]
+    tcphdr->dest = lwip_htons(dst_port);
+ 801dd2e:	8cbb      	ldrh	r3, [r7, #36]	; 0x24
+ 801dd30:	4618      	mov	r0, r3
+ 801dd32:	f7f8 f905 	bl	8015f40 <lwip_htons>
+ 801dd36:	4603      	mov	r3, r0
+ 801dd38:	461a      	mov	r2, r3
+ 801dd3a:	693b      	ldr	r3, [r7, #16]
+ 801dd3c:	805a      	strh	r2, [r3, #2]
+    tcphdr->seqno = seqno_be;
+ 801dd3e:	693b      	ldr	r3, [r7, #16]
+ 801dd40:	687a      	ldr	r2, [r7, #4]
+ 801dd42:	605a      	str	r2, [r3, #4]
+    tcphdr->ackno = lwip_htonl(ackno);
+ 801dd44:	68f8      	ldr	r0, [r7, #12]
+ 801dd46:	f7f8 f910 	bl	8015f6a <lwip_htonl>
+ 801dd4a:	4602      	mov	r2, r0
+ 801dd4c:	693b      	ldr	r3, [r7, #16]
+ 801dd4e:	609a      	str	r2, [r3, #8]
+    TCPH_HDRLEN_FLAGS_SET(tcphdr, (5 + optlen / 4), flags);
+ 801dd50:	897b      	ldrh	r3, [r7, #10]
+ 801dd52:	089b      	lsrs	r3, r3, #2
+ 801dd54:	b29b      	uxth	r3, r3
+ 801dd56:	3305      	adds	r3, #5
+ 801dd58:	b29b      	uxth	r3, r3
+ 801dd5a:	031b      	lsls	r3, r3, #12
+ 801dd5c:	b29a      	uxth	r2, r3
+ 801dd5e:	f897 3028 	ldrb.w	r3, [r7, #40]	; 0x28
+ 801dd62:	b29b      	uxth	r3, r3
+ 801dd64:	4313      	orrs	r3, r2
+ 801dd66:	b29b      	uxth	r3, r3
+ 801dd68:	4618      	mov	r0, r3
+ 801dd6a:	f7f8 f8e9 	bl	8015f40 <lwip_htons>
+ 801dd6e:	4603      	mov	r3, r0
+ 801dd70:	461a      	mov	r2, r3
+ 801dd72:	693b      	ldr	r3, [r7, #16]
+ 801dd74:	819a      	strh	r2, [r3, #12]
+    tcphdr->wnd = lwip_htons(wnd);
+ 801dd76:	8dbb      	ldrh	r3, [r7, #44]	; 0x2c
+ 801dd78:	4618      	mov	r0, r3
+ 801dd7a:	f7f8 f8e1 	bl	8015f40 <lwip_htons>
+ 801dd7e:	4603      	mov	r3, r0
+ 801dd80:	461a      	mov	r2, r3
+ 801dd82:	693b      	ldr	r3, [r7, #16]
+ 801dd84:	81da      	strh	r2, [r3, #14]
+    tcphdr->chksum = 0;
+ 801dd86:	693b      	ldr	r3, [r7, #16]
+ 801dd88:	2200      	movs	r2, #0
+ 801dd8a:	741a      	strb	r2, [r3, #16]
+ 801dd8c:	2200      	movs	r2, #0
+ 801dd8e:	745a      	strb	r2, [r3, #17]
+    tcphdr->urgp = 0;
+ 801dd90:	693b      	ldr	r3, [r7, #16]
+ 801dd92:	2200      	movs	r2, #0
+ 801dd94:	749a      	strb	r2, [r3, #18]
+ 801dd96:	2200      	movs	r2, #0
+ 801dd98:	74da      	strb	r2, [r3, #19]
+  }
+  return p;
+ 801dd9a:	697b      	ldr	r3, [r7, #20]
+}
+ 801dd9c:	4618      	mov	r0, r3
+ 801dd9e:	3718      	adds	r7, #24
+ 801dda0:	46bd      	mov	sp, r7
+ 801dda2:	bd80      	pop	{r7, pc}
+ 801dda4:	080257b8 	.word	0x080257b8
+ 801dda8:	08025eec 	.word	0x08025eec
+ 801ddac:	0802580c 	.word	0x0802580c
+
+0801ddb0 <tcp_output_alloc_header>:
+ * @return pbuf with p->payload being the tcp_hdr
+ */
+static struct pbuf *
+tcp_output_alloc_header(struct tcp_pcb *pcb, u16_t optlen, u16_t datalen,
+                        u32_t seqno_be /* already in network byte order */)
+{
+ 801ddb0:	b5b0      	push	{r4, r5, r7, lr}
+ 801ddb2:	b08a      	sub	sp, #40	; 0x28
+ 801ddb4:	af04      	add	r7, sp, #16
+ 801ddb6:	60f8      	str	r0, [r7, #12]
+ 801ddb8:	607b      	str	r3, [r7, #4]
+ 801ddba:	460b      	mov	r3, r1
+ 801ddbc:	817b      	strh	r3, [r7, #10]
+ 801ddbe:	4613      	mov	r3, r2
+ 801ddc0:	813b      	strh	r3, [r7, #8]
+  struct pbuf *p;
+
+  LWIP_ASSERT("tcp_output_alloc_header: invalid pcb", pcb != NULL);
+ 801ddc2:	68fb      	ldr	r3, [r7, #12]
+ 801ddc4:	2b00      	cmp	r3, #0
+ 801ddc6:	d106      	bne.n	801ddd6 <tcp_output_alloc_header+0x26>
+ 801ddc8:	4b15      	ldr	r3, [pc, #84]	; (801de20 <tcp_output_alloc_header+0x70>)
+ 801ddca:	f240 7242 	movw	r2, #1858	; 0x742
+ 801ddce:	4915      	ldr	r1, [pc, #84]	; (801de24 <tcp_output_alloc_header+0x74>)
+ 801ddd0:	4815      	ldr	r0, [pc, #84]	; (801de28 <tcp_output_alloc_header+0x78>)
+ 801ddd2:	f003 fdd9 	bl	8021988 <iprintf>
+
+  p = tcp_output_alloc_header_common(pcb->rcv_nxt, optlen, datalen,
+ 801ddd6:	68fb      	ldr	r3, [r7, #12]
+ 801ddd8:	6a58      	ldr	r0, [r3, #36]	; 0x24
+ 801ddda:	68fb      	ldr	r3, [r7, #12]
+ 801dddc:	8adb      	ldrh	r3, [r3, #22]
+ 801ddde:	68fa      	ldr	r2, [r7, #12]
+ 801dde0:	8b12      	ldrh	r2, [r2, #24]
+ 801dde2:	68f9      	ldr	r1, [r7, #12]
+ 801dde4:	8d49      	ldrh	r1, [r1, #42]	; 0x2a
+ 801dde6:	893d      	ldrh	r5, [r7, #8]
+ 801dde8:	897c      	ldrh	r4, [r7, #10]
+ 801ddea:	9103      	str	r1, [sp, #12]
+ 801ddec:	2110      	movs	r1, #16
+ 801ddee:	9102      	str	r1, [sp, #8]
+ 801ddf0:	9201      	str	r2, [sp, #4]
+ 801ddf2:	9300      	str	r3, [sp, #0]
+ 801ddf4:	687b      	ldr	r3, [r7, #4]
+ 801ddf6:	462a      	mov	r2, r5
+ 801ddf8:	4621      	mov	r1, r4
+ 801ddfa:	f7ff ff67 	bl	801dccc <tcp_output_alloc_header_common>
+ 801ddfe:	6178      	str	r0, [r7, #20]
+    seqno_be, pcb->local_port, pcb->remote_port, TCP_ACK,
+    TCPWND_MIN16(RCV_WND_SCALE(pcb, pcb->rcv_ann_wnd)));
+  if (p != NULL) {
+ 801de00:	697b      	ldr	r3, [r7, #20]
+ 801de02:	2b00      	cmp	r3, #0
+ 801de04:	d006      	beq.n	801de14 <tcp_output_alloc_header+0x64>
+    /* If we're sending a packet, update the announced right window edge */
+    pcb->rcv_ann_right_edge = pcb->rcv_nxt + pcb->rcv_ann_wnd;
+ 801de06:	68fb      	ldr	r3, [r7, #12]
+ 801de08:	6a5b      	ldr	r3, [r3, #36]	; 0x24
+ 801de0a:	68fa      	ldr	r2, [r7, #12]
+ 801de0c:	8d52      	ldrh	r2, [r2, #42]	; 0x2a
+ 801de0e:	441a      	add	r2, r3
+ 801de10:	68fb      	ldr	r3, [r7, #12]
+ 801de12:	62da      	str	r2, [r3, #44]	; 0x2c
+  }
+  return p;
+ 801de14:	697b      	ldr	r3, [r7, #20]
+}
+ 801de16:	4618      	mov	r0, r3
+ 801de18:	3718      	adds	r7, #24
+ 801de1a:	46bd      	mov	sp, r7
+ 801de1c:	bdb0      	pop	{r4, r5, r7, pc}
+ 801de1e:	bf00      	nop
+ 801de20:	080257b8 	.word	0x080257b8
+ 801de24:	08025f1c 	.word	0x08025f1c
+ 801de28:	0802580c 	.word	0x0802580c
+
+0801de2c <tcp_output_fill_options>:
+
+/* Fill in options for control segments */
+static void
+tcp_output_fill_options(const struct tcp_pcb *pcb, struct pbuf *p, u8_t optflags, u8_t num_sacks)
+{
+ 801de2c:	b580      	push	{r7, lr}
+ 801de2e:	b088      	sub	sp, #32
+ 801de30:	af00      	add	r7, sp, #0
+ 801de32:	60f8      	str	r0, [r7, #12]
+ 801de34:	60b9      	str	r1, [r7, #8]
+ 801de36:	4611      	mov	r1, r2
+ 801de38:	461a      	mov	r2, r3
+ 801de3a:	460b      	mov	r3, r1
+ 801de3c:	71fb      	strb	r3, [r7, #7]
+ 801de3e:	4613      	mov	r3, r2
+ 801de40:	71bb      	strb	r3, [r7, #6]
+  struct tcp_hdr *tcphdr;
+  u32_t *opts;
+  u16_t sacks_len = 0;
+ 801de42:	2300      	movs	r3, #0
+ 801de44:	83fb      	strh	r3, [r7, #30]
+
+  LWIP_ASSERT("tcp_output_fill_options: invalid pbuf", p != NULL);
+ 801de46:	68bb      	ldr	r3, [r7, #8]
+ 801de48:	2b00      	cmp	r3, #0
+ 801de4a:	d106      	bne.n	801de5a <tcp_output_fill_options+0x2e>
+ 801de4c:	4b12      	ldr	r3, [pc, #72]	; (801de98 <tcp_output_fill_options+0x6c>)
+ 801de4e:	f240 7256 	movw	r2, #1878	; 0x756
+ 801de52:	4912      	ldr	r1, [pc, #72]	; (801de9c <tcp_output_fill_options+0x70>)
+ 801de54:	4812      	ldr	r0, [pc, #72]	; (801dea0 <tcp_output_fill_options+0x74>)
+ 801de56:	f003 fd97 	bl	8021988 <iprintf>
+
+  tcphdr = (struct tcp_hdr *)p->payload;
+ 801de5a:	68bb      	ldr	r3, [r7, #8]
+ 801de5c:	685b      	ldr	r3, [r3, #4]
+ 801de5e:	61bb      	str	r3, [r7, #24]
+  opts = (u32_t *)(void *)(tcphdr + 1);
+ 801de60:	69bb      	ldr	r3, [r7, #24]
+ 801de62:	3314      	adds	r3, #20
+ 801de64:	617b      	str	r3, [r7, #20]
+  opts = LWIP_HOOK_TCP_OUT_ADD_TCPOPTS(p, tcphdr, pcb, opts);
+#endif
+
+  LWIP_UNUSED_ARG(pcb);
+  LWIP_UNUSED_ARG(sacks_len);
+  LWIP_ASSERT("options not filled", (u8_t *)opts == ((u8_t *)(tcphdr + 1)) + sacks_len * 4 + LWIP_TCP_OPT_LENGTH_SEGMENT(optflags, pcb));
+ 801de66:	8bfb      	ldrh	r3, [r7, #30]
+ 801de68:	009b      	lsls	r3, r3, #2
+ 801de6a:	461a      	mov	r2, r3
+ 801de6c:	79fb      	ldrb	r3, [r7, #7]
+ 801de6e:	009b      	lsls	r3, r3, #2
+ 801de70:	f003 0304 	and.w	r3, r3, #4
+ 801de74:	4413      	add	r3, r2
+ 801de76:	3314      	adds	r3, #20
+ 801de78:	69ba      	ldr	r2, [r7, #24]
+ 801de7a:	4413      	add	r3, r2
+ 801de7c:	697a      	ldr	r2, [r7, #20]
+ 801de7e:	429a      	cmp	r2, r3
+ 801de80:	d006      	beq.n	801de90 <tcp_output_fill_options+0x64>
+ 801de82:	4b05      	ldr	r3, [pc, #20]	; (801de98 <tcp_output_fill_options+0x6c>)
+ 801de84:	f240 7275 	movw	r2, #1909	; 0x775
+ 801de88:	4906      	ldr	r1, [pc, #24]	; (801dea4 <tcp_output_fill_options+0x78>)
+ 801de8a:	4805      	ldr	r0, [pc, #20]	; (801dea0 <tcp_output_fill_options+0x74>)
+ 801de8c:	f003 fd7c 	bl	8021988 <iprintf>
+  LWIP_UNUSED_ARG(optflags); /* for LWIP_NOASSERT */
+  LWIP_UNUSED_ARG(opts); /* for LWIP_NOASSERT */
+}
+ 801de90:	bf00      	nop
+ 801de92:	3720      	adds	r7, #32
+ 801de94:	46bd      	mov	sp, r7
+ 801de96:	bd80      	pop	{r7, pc}
+ 801de98:	080257b8 	.word	0x080257b8
+ 801de9c:	08025f44 	.word	0x08025f44
+ 801dea0:	0802580c 	.word	0x0802580c
+ 801dea4:	08025e3c 	.word	0x08025e3c
+
+0801dea8 <tcp_output_control_segment>:
+ * header checksum and calling ip_output_if while handling netif hints and stats.
+ */
+static err_t
+tcp_output_control_segment(const struct tcp_pcb *pcb, struct pbuf *p,
+                           const ip_addr_t *src, const ip_addr_t *dst)
+{
+ 801dea8:	b580      	push	{r7, lr}
+ 801deaa:	b08a      	sub	sp, #40	; 0x28
+ 801deac:	af04      	add	r7, sp, #16
+ 801deae:	60f8      	str	r0, [r7, #12]
+ 801deb0:	60b9      	str	r1, [r7, #8]
+ 801deb2:	607a      	str	r2, [r7, #4]
+ 801deb4:	603b      	str	r3, [r7, #0]
+  err_t err;
+  struct netif *netif;
+
+  LWIP_ASSERT("tcp_output_control_segment: invalid pbuf", p != NULL);
+ 801deb6:	68bb      	ldr	r3, [r7, #8]
+ 801deb8:	2b00      	cmp	r3, #0
+ 801deba:	d106      	bne.n	801deca <tcp_output_control_segment+0x22>
+ 801debc:	4b1c      	ldr	r3, [pc, #112]	; (801df30 <tcp_output_control_segment+0x88>)
+ 801debe:	f240 7287 	movw	r2, #1927	; 0x787
+ 801dec2:	491c      	ldr	r1, [pc, #112]	; (801df34 <tcp_output_control_segment+0x8c>)
+ 801dec4:	481c      	ldr	r0, [pc, #112]	; (801df38 <tcp_output_control_segment+0x90>)
+ 801dec6:	f003 fd5f 	bl	8021988 <iprintf>
+
+  netif = tcp_route(pcb, src, dst);
+ 801deca:	683a      	ldr	r2, [r7, #0]
+ 801decc:	6879      	ldr	r1, [r7, #4]
+ 801dece:	68f8      	ldr	r0, [r7, #12]
+ 801ded0:	f7fe fa7c 	bl	801c3cc <tcp_route>
+ 801ded4:	6138      	str	r0, [r7, #16]
+  if (netif == NULL) {
+ 801ded6:	693b      	ldr	r3, [r7, #16]
+ 801ded8:	2b00      	cmp	r3, #0
+ 801deda:	d102      	bne.n	801dee2 <tcp_output_control_segment+0x3a>
+    err = ERR_RTE;
+ 801dedc:	23fc      	movs	r3, #252	; 0xfc
+ 801dede:	75fb      	strb	r3, [r7, #23]
+ 801dee0:	e01c      	b.n	801df1c <tcp_output_control_segment+0x74>
+      struct tcp_hdr *tcphdr = (struct tcp_hdr *)p->payload;
+      tcphdr->chksum = ip_chksum_pseudo(p, IP_PROTO_TCP, p->tot_len,
+                                        src, dst);
+    }
+#endif
+    if (pcb != NULL) {
+ 801dee2:	68fb      	ldr	r3, [r7, #12]
+ 801dee4:	2b00      	cmp	r3, #0
+ 801dee6:	d006      	beq.n	801def6 <tcp_output_control_segment+0x4e>
+      NETIF_SET_HINTS(netif, LWIP_CONST_CAST(struct netif_hint*, &(pcb->netif_hints)));
+      ttl = pcb->ttl;
+ 801dee8:	68fb      	ldr	r3, [r7, #12]
+ 801deea:	7adb      	ldrb	r3, [r3, #11]
+ 801deec:	75bb      	strb	r3, [r7, #22]
+      tos = pcb->tos;
+ 801deee:	68fb      	ldr	r3, [r7, #12]
+ 801def0:	7a9b      	ldrb	r3, [r3, #10]
+ 801def2:	757b      	strb	r3, [r7, #21]
+ 801def4:	e003      	b.n	801defe <tcp_output_control_segment+0x56>
+    } else {
+      /* Send output with hardcoded TTL/HL since we have no access to the pcb */
+      ttl = TCP_TTL;
+ 801def6:	23ff      	movs	r3, #255	; 0xff
+ 801def8:	75bb      	strb	r3, [r7, #22]
+      tos = 0;
+ 801defa:	2300      	movs	r3, #0
+ 801defc:	757b      	strb	r3, [r7, #21]
+    }
+    TCP_STATS_INC(tcp.xmit);
+    err = ip_output_if(p, src, dst, ttl, tos, IP_PROTO_TCP, netif);
+ 801defe:	7dba      	ldrb	r2, [r7, #22]
+ 801df00:	693b      	ldr	r3, [r7, #16]
+ 801df02:	9302      	str	r3, [sp, #8]
+ 801df04:	2306      	movs	r3, #6
+ 801df06:	9301      	str	r3, [sp, #4]
+ 801df08:	7d7b      	ldrb	r3, [r7, #21]
+ 801df0a:	9300      	str	r3, [sp, #0]
+ 801df0c:	4613      	mov	r3, r2
+ 801df0e:	683a      	ldr	r2, [r7, #0]
+ 801df10:	6879      	ldr	r1, [r7, #4]
+ 801df12:	68b8      	ldr	r0, [r7, #8]
+ 801df14:	f002 f9ac 	bl	8020270 <ip4_output_if>
+ 801df18:	4603      	mov	r3, r0
+ 801df1a:	75fb      	strb	r3, [r7, #23]
+    NETIF_RESET_HINTS(netif);
+  }
+  pbuf_free(p);
+ 801df1c:	68b8      	ldr	r0, [r7, #8]
+ 801df1e:	f7f9 fdeb 	bl	8017af8 <pbuf_free>
+  return err;
+ 801df22:	f997 3017 	ldrsb.w	r3, [r7, #23]
+}
+ 801df26:	4618      	mov	r0, r3
+ 801df28:	3718      	adds	r7, #24
+ 801df2a:	46bd      	mov	sp, r7
+ 801df2c:	bd80      	pop	{r7, pc}
+ 801df2e:	bf00      	nop
+ 801df30:	080257b8 	.word	0x080257b8
+ 801df34:	08025f6c 	.word	0x08025f6c
+ 801df38:	0802580c 	.word	0x0802580c
+
+0801df3c <tcp_rst>:
+ */
+void
+tcp_rst(const struct tcp_pcb *pcb, u32_t seqno, u32_t ackno,
+        const ip_addr_t *local_ip, const ip_addr_t *remote_ip,
+        u16_t local_port, u16_t remote_port)
+{
+ 801df3c:	b590      	push	{r4, r7, lr}
+ 801df3e:	b08b      	sub	sp, #44	; 0x2c
+ 801df40:	af04      	add	r7, sp, #16
+ 801df42:	60f8      	str	r0, [r7, #12]
+ 801df44:	60b9      	str	r1, [r7, #8]
+ 801df46:	607a      	str	r2, [r7, #4]
+ 801df48:	603b      	str	r3, [r7, #0]
+  struct pbuf *p;
+  u16_t wnd;
+  u8_t optlen;
+
+  LWIP_ASSERT("tcp_rst: invalid local_ip", local_ip != NULL);
+ 801df4a:	683b      	ldr	r3, [r7, #0]
+ 801df4c:	2b00      	cmp	r3, #0
+ 801df4e:	d106      	bne.n	801df5e <tcp_rst+0x22>
+ 801df50:	4b1f      	ldr	r3, [pc, #124]	; (801dfd0 <tcp_rst+0x94>)
+ 801df52:	f240 72c4 	movw	r2, #1988	; 0x7c4
+ 801df56:	491f      	ldr	r1, [pc, #124]	; (801dfd4 <tcp_rst+0x98>)
+ 801df58:	481f      	ldr	r0, [pc, #124]	; (801dfd8 <tcp_rst+0x9c>)
+ 801df5a:	f003 fd15 	bl	8021988 <iprintf>
+  LWIP_ASSERT("tcp_rst: invalid remote_ip", remote_ip != NULL);
+ 801df5e:	6abb      	ldr	r3, [r7, #40]	; 0x28
+ 801df60:	2b00      	cmp	r3, #0
+ 801df62:	d106      	bne.n	801df72 <tcp_rst+0x36>
+ 801df64:	4b1a      	ldr	r3, [pc, #104]	; (801dfd0 <tcp_rst+0x94>)
+ 801df66:	f240 72c5 	movw	r2, #1989	; 0x7c5
+ 801df6a:	491c      	ldr	r1, [pc, #112]	; (801dfdc <tcp_rst+0xa0>)
+ 801df6c:	481a      	ldr	r0, [pc, #104]	; (801dfd8 <tcp_rst+0x9c>)
+ 801df6e:	f003 fd0b 	bl	8021988 <iprintf>
+
+  optlen = LWIP_TCP_OPT_LENGTH_SEGMENT(0, pcb);
+ 801df72:	2300      	movs	r3, #0
+ 801df74:	75fb      	strb	r3, [r7, #23]
+
+#if LWIP_WND_SCALE
+  wnd = PP_HTONS(((TCP_WND >> TCP_RCV_SCALE) & 0xFFFF));
+#else
+  wnd = PP_HTONS(TCP_WND);
+ 801df76:	f24d 0316 	movw	r3, #53270	; 0xd016
+ 801df7a:	82bb      	strh	r3, [r7, #20]
+#endif
+
+  p = tcp_output_alloc_header_common(ackno, optlen, 0, lwip_htonl(seqno), local_port,
+ 801df7c:	7dfb      	ldrb	r3, [r7, #23]
+ 801df7e:	b29c      	uxth	r4, r3
+ 801df80:	68b8      	ldr	r0, [r7, #8]
+ 801df82:	f7f7 fff2 	bl	8015f6a <lwip_htonl>
+ 801df86:	4602      	mov	r2, r0
+ 801df88:	8abb      	ldrh	r3, [r7, #20]
+ 801df8a:	9303      	str	r3, [sp, #12]
+ 801df8c:	2314      	movs	r3, #20
+ 801df8e:	9302      	str	r3, [sp, #8]
+ 801df90:	8e3b      	ldrh	r3, [r7, #48]	; 0x30
+ 801df92:	9301      	str	r3, [sp, #4]
+ 801df94:	8dbb      	ldrh	r3, [r7, #44]	; 0x2c
+ 801df96:	9300      	str	r3, [sp, #0]
+ 801df98:	4613      	mov	r3, r2
+ 801df9a:	2200      	movs	r2, #0
+ 801df9c:	4621      	mov	r1, r4
+ 801df9e:	6878      	ldr	r0, [r7, #4]
+ 801dfa0:	f7ff fe94 	bl	801dccc <tcp_output_alloc_header_common>
+ 801dfa4:	6138      	str	r0, [r7, #16]
+    remote_port, TCP_RST | TCP_ACK, wnd);
+  if (p == NULL) {
+ 801dfa6:	693b      	ldr	r3, [r7, #16]
+ 801dfa8:	2b00      	cmp	r3, #0
+ 801dfaa:	d00c      	beq.n	801dfc6 <tcp_rst+0x8a>
+    LWIP_DEBUGF(TCP_DEBUG, ("tcp_rst: could not allocate memory for pbuf\n"));
+    return;
+  }
+  tcp_output_fill_options(pcb, p, 0, optlen);
+ 801dfac:	7dfb      	ldrb	r3, [r7, #23]
+ 801dfae:	2200      	movs	r2, #0
+ 801dfb0:	6939      	ldr	r1, [r7, #16]
+ 801dfb2:	68f8      	ldr	r0, [r7, #12]
+ 801dfb4:	f7ff ff3a 	bl	801de2c <tcp_output_fill_options>
+
+  MIB2_STATS_INC(mib2.tcpoutrsts);
+
+  tcp_output_control_segment(pcb, p, local_ip, remote_ip);
+ 801dfb8:	6abb      	ldr	r3, [r7, #40]	; 0x28
+ 801dfba:	683a      	ldr	r2, [r7, #0]
+ 801dfbc:	6939      	ldr	r1, [r7, #16]
+ 801dfbe:	68f8      	ldr	r0, [r7, #12]
+ 801dfc0:	f7ff ff72 	bl	801dea8 <tcp_output_control_segment>
+ 801dfc4:	e000      	b.n	801dfc8 <tcp_rst+0x8c>
+    return;
+ 801dfc6:	bf00      	nop
+  LWIP_DEBUGF(TCP_RST_DEBUG, ("tcp_rst: seqno %"U32_F" ackno %"U32_F".\n", seqno, ackno));
+}
+ 801dfc8:	371c      	adds	r7, #28
+ 801dfca:	46bd      	mov	sp, r7
+ 801dfcc:	bd90      	pop	{r4, r7, pc}
+ 801dfce:	bf00      	nop
+ 801dfd0:	080257b8 	.word	0x080257b8
+ 801dfd4:	08025f98 	.word	0x08025f98
+ 801dfd8:	0802580c 	.word	0x0802580c
+ 801dfdc:	08025fb4 	.word	0x08025fb4
+
+0801dfe0 <tcp_send_empty_ack>:
+ *
+ * @param pcb Protocol control block for the TCP connection to send the ACK
+ */
+err_t
+tcp_send_empty_ack(struct tcp_pcb *pcb)
+{
+ 801dfe0:	b590      	push	{r4, r7, lr}
+ 801dfe2:	b087      	sub	sp, #28
+ 801dfe4:	af00      	add	r7, sp, #0
+ 801dfe6:	6078      	str	r0, [r7, #4]
+  err_t err;
+  struct pbuf *p;
+  u8_t optlen, optflags = 0;
+ 801dfe8:	2300      	movs	r3, #0
+ 801dfea:	75fb      	strb	r3, [r7, #23]
+  u8_t num_sacks = 0;
+ 801dfec:	2300      	movs	r3, #0
+ 801dfee:	75bb      	strb	r3, [r7, #22]
+
+  LWIP_ASSERT("tcp_send_empty_ack: invalid pcb", pcb != NULL);
+ 801dff0:	687b      	ldr	r3, [r7, #4]
+ 801dff2:	2b00      	cmp	r3, #0
+ 801dff4:	d106      	bne.n	801e004 <tcp_send_empty_ack+0x24>
+ 801dff6:	4b28      	ldr	r3, [pc, #160]	; (801e098 <tcp_send_empty_ack+0xb8>)
+ 801dff8:	f240 72ea 	movw	r2, #2026	; 0x7ea
+ 801dffc:	4927      	ldr	r1, [pc, #156]	; (801e09c <tcp_send_empty_ack+0xbc>)
+ 801dffe:	4828      	ldr	r0, [pc, #160]	; (801e0a0 <tcp_send_empty_ack+0xc0>)
+ 801e000:	f003 fcc2 	bl	8021988 <iprintf>
+#if LWIP_TCP_TIMESTAMPS
+  if (pcb->flags & TF_TIMESTAMP) {
+    optflags = TF_SEG_OPTS_TS;
+  }
+#endif
+  optlen = LWIP_TCP_OPT_LENGTH_SEGMENT(optflags, pcb);
+ 801e004:	7dfb      	ldrb	r3, [r7, #23]
+ 801e006:	009b      	lsls	r3, r3, #2
+ 801e008:	b2db      	uxtb	r3, r3
+ 801e00a:	f003 0304 	and.w	r3, r3, #4
+ 801e00e:	757b      	strb	r3, [r7, #21]
+  if ((num_sacks = tcp_get_num_sacks(pcb, optlen)) > 0) {
+    optlen += 4 + num_sacks * 8; /* 4 bytes for header (including 2*NOP), plus 8B for each SACK */
+  }
+#endif
+
+  p = tcp_output_alloc_header(pcb, optlen, 0, lwip_htonl(pcb->snd_nxt));
+ 801e010:	7d7b      	ldrb	r3, [r7, #21]
+ 801e012:	b29c      	uxth	r4, r3
+ 801e014:	687b      	ldr	r3, [r7, #4]
+ 801e016:	6d1b      	ldr	r3, [r3, #80]	; 0x50
+ 801e018:	4618      	mov	r0, r3
+ 801e01a:	f7f7 ffa6 	bl	8015f6a <lwip_htonl>
+ 801e01e:	4603      	mov	r3, r0
+ 801e020:	2200      	movs	r2, #0
+ 801e022:	4621      	mov	r1, r4
+ 801e024:	6878      	ldr	r0, [r7, #4]
+ 801e026:	f7ff fec3 	bl	801ddb0 <tcp_output_alloc_header>
+ 801e02a:	6138      	str	r0, [r7, #16]
+  if (p == NULL) {
+ 801e02c:	693b      	ldr	r3, [r7, #16]
+ 801e02e:	2b00      	cmp	r3, #0
+ 801e030:	d109      	bne.n	801e046 <tcp_send_empty_ack+0x66>
+    /* let tcp_fasttmr retry sending this ACK */
+    tcp_set_flags(pcb, TF_ACK_DELAY | TF_ACK_NOW);
+ 801e032:	687b      	ldr	r3, [r7, #4]
+ 801e034:	8b5b      	ldrh	r3, [r3, #26]
+ 801e036:	f043 0303 	orr.w	r3, r3, #3
+ 801e03a:	b29a      	uxth	r2, r3
+ 801e03c:	687b      	ldr	r3, [r7, #4]
+ 801e03e:	835a      	strh	r2, [r3, #26]
+    LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_output: (ACK) could not allocate pbuf\n"));
+    return ERR_BUF;
+ 801e040:	f06f 0301 	mvn.w	r3, #1
+ 801e044:	e023      	b.n	801e08e <tcp_send_empty_ack+0xae>
+  }
+  tcp_output_fill_options(pcb, p, optflags, num_sacks);
+ 801e046:	7dbb      	ldrb	r3, [r7, #22]
+ 801e048:	7dfa      	ldrb	r2, [r7, #23]
+ 801e04a:	6939      	ldr	r1, [r7, #16]
+ 801e04c:	6878      	ldr	r0, [r7, #4]
+ 801e04e:	f7ff feed 	bl	801de2c <tcp_output_fill_options>
+  pcb->ts_lastacksent = pcb->rcv_nxt;
+#endif
+
+  LWIP_DEBUGF(TCP_OUTPUT_DEBUG,
+              ("tcp_output: sending ACK for %"U32_F"\n", pcb->rcv_nxt));
+  err = tcp_output_control_segment(pcb, p, &pcb->local_ip, &pcb->remote_ip);
+ 801e052:	687a      	ldr	r2, [r7, #4]
+ 801e054:	687b      	ldr	r3, [r7, #4]
+ 801e056:	3304      	adds	r3, #4
+ 801e058:	6939      	ldr	r1, [r7, #16]
+ 801e05a:	6878      	ldr	r0, [r7, #4]
+ 801e05c:	f7ff ff24 	bl	801dea8 <tcp_output_control_segment>
+ 801e060:	4603      	mov	r3, r0
+ 801e062:	73fb      	strb	r3, [r7, #15]
+  if (err != ERR_OK) {
+ 801e064:	f997 300f 	ldrsb.w	r3, [r7, #15]
+ 801e068:	2b00      	cmp	r3, #0
+ 801e06a:	d007      	beq.n	801e07c <tcp_send_empty_ack+0x9c>
+    /* let tcp_fasttmr retry sending this ACK */
+    tcp_set_flags(pcb, TF_ACK_DELAY | TF_ACK_NOW);
+ 801e06c:	687b      	ldr	r3, [r7, #4]
+ 801e06e:	8b5b      	ldrh	r3, [r3, #26]
+ 801e070:	f043 0303 	orr.w	r3, r3, #3
+ 801e074:	b29a      	uxth	r2, r3
+ 801e076:	687b      	ldr	r3, [r7, #4]
+ 801e078:	835a      	strh	r2, [r3, #26]
+ 801e07a:	e006      	b.n	801e08a <tcp_send_empty_ack+0xaa>
+  } else {
+    /* remove ACK flags from the PCB, as we sent an empty ACK now */
+    tcp_clear_flags(pcb, TF_ACK_DELAY | TF_ACK_NOW);
+ 801e07c:	687b      	ldr	r3, [r7, #4]
+ 801e07e:	8b5b      	ldrh	r3, [r3, #26]
+ 801e080:	f023 0303 	bic.w	r3, r3, #3
+ 801e084:	b29a      	uxth	r2, r3
+ 801e086:	687b      	ldr	r3, [r7, #4]
+ 801e088:	835a      	strh	r2, [r3, #26]
+  }
+
+  return err;
+ 801e08a:	f997 300f 	ldrsb.w	r3, [r7, #15]
+}
+ 801e08e:	4618      	mov	r0, r3
+ 801e090:	371c      	adds	r7, #28
+ 801e092:	46bd      	mov	sp, r7
+ 801e094:	bd90      	pop	{r4, r7, pc}
+ 801e096:	bf00      	nop
+ 801e098:	080257b8 	.word	0x080257b8
+ 801e09c:	08025fd0 	.word	0x08025fd0
+ 801e0a0:	0802580c 	.word	0x0802580c
+
+0801e0a4 <tcp_keepalive>:
+ *
+ * @param pcb the tcp_pcb for which to send a keepalive packet
+ */
+err_t
+tcp_keepalive(struct tcp_pcb *pcb)
+{
+ 801e0a4:	b590      	push	{r4, r7, lr}
+ 801e0a6:	b085      	sub	sp, #20
+ 801e0a8:	af00      	add	r7, sp, #0
+ 801e0aa:	6078      	str	r0, [r7, #4]
+  err_t err;
+  struct pbuf *p;
+  u8_t optlen = LWIP_TCP_OPT_LENGTH_SEGMENT(0, pcb);
+ 801e0ac:	2300      	movs	r3, #0
+ 801e0ae:	72bb      	strb	r3, [r7, #10]
+
+  LWIP_ASSERT("tcp_keepalive: invalid pcb", pcb != NULL);
+ 801e0b0:	687b      	ldr	r3, [r7, #4]
+ 801e0b2:	2b00      	cmp	r3, #0
+ 801e0b4:	d106      	bne.n	801e0c4 <tcp_keepalive+0x20>
+ 801e0b6:	4b18      	ldr	r3, [pc, #96]	; (801e118 <tcp_keepalive+0x74>)
+ 801e0b8:	f640 0224 	movw	r2, #2084	; 0x824
+ 801e0bc:	4917      	ldr	r1, [pc, #92]	; (801e11c <tcp_keepalive+0x78>)
+ 801e0be:	4818      	ldr	r0, [pc, #96]	; (801e120 <tcp_keepalive+0x7c>)
+ 801e0c0:	f003 fc62 	bl	8021988 <iprintf>
+  LWIP_DEBUGF(TCP_DEBUG, ("\n"));
+
+  LWIP_DEBUGF(TCP_DEBUG, ("tcp_keepalive: tcp_ticks %"U32_F"   pcb->tmr %"U32_F" pcb->keep_cnt_sent %"U16_F"\n",
+                          tcp_ticks, pcb->tmr, (u16_t)pcb->keep_cnt_sent));
+
+  p = tcp_output_alloc_header(pcb, optlen, 0, lwip_htonl(pcb->snd_nxt - 1));
+ 801e0c4:	7abb      	ldrb	r3, [r7, #10]
+ 801e0c6:	b29c      	uxth	r4, r3
+ 801e0c8:	687b      	ldr	r3, [r7, #4]
+ 801e0ca:	6d1b      	ldr	r3, [r3, #80]	; 0x50
+ 801e0cc:	3b01      	subs	r3, #1
+ 801e0ce:	4618      	mov	r0, r3
+ 801e0d0:	f7f7 ff4b 	bl	8015f6a <lwip_htonl>
+ 801e0d4:	4603      	mov	r3, r0
+ 801e0d6:	2200      	movs	r2, #0
+ 801e0d8:	4621      	mov	r1, r4
+ 801e0da:	6878      	ldr	r0, [r7, #4]
+ 801e0dc:	f7ff fe68 	bl	801ddb0 <tcp_output_alloc_header>
+ 801e0e0:	60f8      	str	r0, [r7, #12]
+  if (p == NULL) {
+ 801e0e2:	68fb      	ldr	r3, [r7, #12]
+ 801e0e4:	2b00      	cmp	r3, #0
+ 801e0e6:	d102      	bne.n	801e0ee <tcp_keepalive+0x4a>
+    LWIP_DEBUGF(TCP_DEBUG,
+                ("tcp_keepalive: could not allocate memory for pbuf\n"));
+    return ERR_MEM;
+ 801e0e8:	f04f 33ff 	mov.w	r3, #4294967295
+ 801e0ec:	e010      	b.n	801e110 <tcp_keepalive+0x6c>
+  }
+  tcp_output_fill_options(pcb, p, 0, optlen);
+ 801e0ee:	7abb      	ldrb	r3, [r7, #10]
+ 801e0f0:	2200      	movs	r2, #0
+ 801e0f2:	68f9      	ldr	r1, [r7, #12]
+ 801e0f4:	6878      	ldr	r0, [r7, #4]
+ 801e0f6:	f7ff fe99 	bl	801de2c <tcp_output_fill_options>
+  err = tcp_output_control_segment(pcb, p, &pcb->local_ip, &pcb->remote_ip);
+ 801e0fa:	687a      	ldr	r2, [r7, #4]
+ 801e0fc:	687b      	ldr	r3, [r7, #4]
+ 801e0fe:	3304      	adds	r3, #4
+ 801e100:	68f9      	ldr	r1, [r7, #12]
+ 801e102:	6878      	ldr	r0, [r7, #4]
+ 801e104:	f7ff fed0 	bl	801dea8 <tcp_output_control_segment>
+ 801e108:	4603      	mov	r3, r0
+ 801e10a:	72fb      	strb	r3, [r7, #11]
+
+  LWIP_DEBUGF(TCP_DEBUG, ("tcp_keepalive: seqno %"U32_F" ackno %"U32_F" err %d.\n",
+                          pcb->snd_nxt - 1, pcb->rcv_nxt, (int)err));
+  return err;
+ 801e10c:	f997 300b 	ldrsb.w	r3, [r7, #11]
+}
+ 801e110:	4618      	mov	r0, r3
+ 801e112:	3714      	adds	r7, #20
+ 801e114:	46bd      	mov	sp, r7
+ 801e116:	bd90      	pop	{r4, r7, pc}
+ 801e118:	080257b8 	.word	0x080257b8
+ 801e11c:	08025ff0 	.word	0x08025ff0
+ 801e120:	0802580c 	.word	0x0802580c
+
+0801e124 <tcp_zero_window_probe>:
+ *
+ * @param pcb the tcp_pcb for which to send a zero-window probe packet
+ */
+err_t
+tcp_zero_window_probe(struct tcp_pcb *pcb)
+{
+ 801e124:	b590      	push	{r4, r7, lr}
+ 801e126:	b08b      	sub	sp, #44	; 0x2c
+ 801e128:	af00      	add	r7, sp, #0
+ 801e12a:	6078      	str	r0, [r7, #4]
+  struct tcp_hdr *tcphdr;
+  struct tcp_seg *seg;
+  u16_t len;
+  u8_t is_fin;
+  u32_t snd_nxt;
+  u8_t optlen = LWIP_TCP_OPT_LENGTH_SEGMENT(0, pcb);
+ 801e12c:	2300      	movs	r3, #0
+ 801e12e:	74fb      	strb	r3, [r7, #19]
+
+  LWIP_ASSERT("tcp_zero_window_probe: invalid pcb", pcb != NULL);
+ 801e130:	687b      	ldr	r3, [r7, #4]
+ 801e132:	2b00      	cmp	r3, #0
+ 801e134:	d106      	bne.n	801e144 <tcp_zero_window_probe+0x20>
+ 801e136:	4b4d      	ldr	r3, [pc, #308]	; (801e26c <tcp_zero_window_probe+0x148>)
+ 801e138:	f640 024f 	movw	r2, #2127	; 0x84f
+ 801e13c:	494c      	ldr	r1, [pc, #304]	; (801e270 <tcp_zero_window_probe+0x14c>)
+ 801e13e:	484d      	ldr	r0, [pc, #308]	; (801e274 <tcp_zero_window_probe+0x150>)
+ 801e140:	f003 fc22 	bl	8021988 <iprintf>
+              ("tcp_zero_window_probe: tcp_ticks %"U32_F
+               "   pcb->tmr %"U32_F" pcb->keep_cnt_sent %"U16_F"\n",
+               tcp_ticks, pcb->tmr, (u16_t)pcb->keep_cnt_sent));
+
+  /* Only consider unsent, persist timer should be off when there is data in-flight */
+  seg = pcb->unsent;
+ 801e144:	687b      	ldr	r3, [r7, #4]
+ 801e146:	6edb      	ldr	r3, [r3, #108]	; 0x6c
+ 801e148:	627b      	str	r3, [r7, #36]	; 0x24
+  if (seg == NULL) {
+ 801e14a:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 801e14c:	2b00      	cmp	r3, #0
+ 801e14e:	d101      	bne.n	801e154 <tcp_zero_window_probe+0x30>
+    /* Not expected, persist timer should be off when the send buffer is empty */
+    return ERR_OK;
+ 801e150:	2300      	movs	r3, #0
+ 801e152:	e087      	b.n	801e264 <tcp_zero_window_probe+0x140>
+
+  /* increment probe count. NOTE: we record probe even if it fails
+     to actually transmit due to an error. This ensures memory exhaustion/
+     routing problem doesn't leave a zero-window pcb as an indefinite zombie.
+     RTO mechanism has similar behavior, see pcb->nrtx */
+  if (pcb->persist_probe < 0xFF) {
+ 801e154:	687b      	ldr	r3, [r7, #4]
+ 801e156:	f893 309a 	ldrb.w	r3, [r3, #154]	; 0x9a
+ 801e15a:	2bff      	cmp	r3, #255	; 0xff
+ 801e15c:	d007      	beq.n	801e16e <tcp_zero_window_probe+0x4a>
+    ++pcb->persist_probe;
+ 801e15e:	687b      	ldr	r3, [r7, #4]
+ 801e160:	f893 309a 	ldrb.w	r3, [r3, #154]	; 0x9a
+ 801e164:	3301      	adds	r3, #1
+ 801e166:	b2da      	uxtb	r2, r3
+ 801e168:	687b      	ldr	r3, [r7, #4]
+ 801e16a:	f883 209a 	strb.w	r2, [r3, #154]	; 0x9a
+  }
+
+  is_fin = ((TCPH_FLAGS(seg->tcphdr) & TCP_FIN) != 0) && (seg->len == 0);
+ 801e16e:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 801e170:	691b      	ldr	r3, [r3, #16]
+ 801e172:	899b      	ldrh	r3, [r3, #12]
+ 801e174:	b29b      	uxth	r3, r3
+ 801e176:	4618      	mov	r0, r3
+ 801e178:	f7f7 fee2 	bl	8015f40 <lwip_htons>
+ 801e17c:	4603      	mov	r3, r0
+ 801e17e:	b2db      	uxtb	r3, r3
+ 801e180:	f003 0301 	and.w	r3, r3, #1
+ 801e184:	2b00      	cmp	r3, #0
+ 801e186:	d005      	beq.n	801e194 <tcp_zero_window_probe+0x70>
+ 801e188:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 801e18a:	891b      	ldrh	r3, [r3, #8]
+ 801e18c:	2b00      	cmp	r3, #0
+ 801e18e:	d101      	bne.n	801e194 <tcp_zero_window_probe+0x70>
+ 801e190:	2301      	movs	r3, #1
+ 801e192:	e000      	b.n	801e196 <tcp_zero_window_probe+0x72>
+ 801e194:	2300      	movs	r3, #0
+ 801e196:	f887 3023 	strb.w	r3, [r7, #35]	; 0x23
+  /* we want to send one seqno: either FIN or data (no options) */
+  len = is_fin ? 0 : 1;
+ 801e19a:	f897 3023 	ldrb.w	r3, [r7, #35]	; 0x23
+ 801e19e:	2b00      	cmp	r3, #0
+ 801e1a0:	bf0c      	ite	eq
+ 801e1a2:	2301      	moveq	r3, #1
+ 801e1a4:	2300      	movne	r3, #0
+ 801e1a6:	b2db      	uxtb	r3, r3
+ 801e1a8:	843b      	strh	r3, [r7, #32]
+
+  p = tcp_output_alloc_header(pcb, optlen, len, seg->tcphdr->seqno);
+ 801e1aa:	7cfb      	ldrb	r3, [r7, #19]
+ 801e1ac:	b299      	uxth	r1, r3
+ 801e1ae:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 801e1b0:	691b      	ldr	r3, [r3, #16]
+ 801e1b2:	685b      	ldr	r3, [r3, #4]
+ 801e1b4:	8c3a      	ldrh	r2, [r7, #32]
+ 801e1b6:	6878      	ldr	r0, [r7, #4]
+ 801e1b8:	f7ff fdfa 	bl	801ddb0 <tcp_output_alloc_header>
+ 801e1bc:	61f8      	str	r0, [r7, #28]
+  if (p == NULL) {
+ 801e1be:	69fb      	ldr	r3, [r7, #28]
+ 801e1c0:	2b00      	cmp	r3, #0
+ 801e1c2:	d102      	bne.n	801e1ca <tcp_zero_window_probe+0xa6>
+    LWIP_DEBUGF(TCP_DEBUG, ("tcp_zero_window_probe: no memory for pbuf\n"));
+    return ERR_MEM;
+ 801e1c4:	f04f 33ff 	mov.w	r3, #4294967295
+ 801e1c8:	e04c      	b.n	801e264 <tcp_zero_window_probe+0x140>
+  }
+  tcphdr = (struct tcp_hdr *)p->payload;
+ 801e1ca:	69fb      	ldr	r3, [r7, #28]
+ 801e1cc:	685b      	ldr	r3, [r3, #4]
+ 801e1ce:	61bb      	str	r3, [r7, #24]
+
+  if (is_fin) {
+ 801e1d0:	f897 3023 	ldrb.w	r3, [r7, #35]	; 0x23
+ 801e1d4:	2b00      	cmp	r3, #0
+ 801e1d6:	d011      	beq.n	801e1fc <tcp_zero_window_probe+0xd8>
+    /* FIN segment, no data */
+    TCPH_FLAGS_SET(tcphdr, TCP_ACK | TCP_FIN);
+ 801e1d8:	69bb      	ldr	r3, [r7, #24]
+ 801e1da:	899b      	ldrh	r3, [r3, #12]
+ 801e1dc:	b29b      	uxth	r3, r3
+ 801e1de:	b21b      	sxth	r3, r3
+ 801e1e0:	f423 537c 	bic.w	r3, r3, #16128	; 0x3f00
+ 801e1e4:	b21c      	sxth	r4, r3
+ 801e1e6:	2011      	movs	r0, #17
+ 801e1e8:	f7f7 feaa 	bl	8015f40 <lwip_htons>
+ 801e1ec:	4603      	mov	r3, r0
+ 801e1ee:	b21b      	sxth	r3, r3
+ 801e1f0:	4323      	orrs	r3, r4
+ 801e1f2:	b21b      	sxth	r3, r3
+ 801e1f4:	b29a      	uxth	r2, r3
+ 801e1f6:	69bb      	ldr	r3, [r7, #24]
+ 801e1f8:	819a      	strh	r2, [r3, #12]
+ 801e1fa:	e010      	b.n	801e21e <tcp_zero_window_probe+0xfa>
+  } else {
+    /* Data segment, copy in one byte from the head of the unacked queue */
+    char *d = ((char *)p->payload + TCP_HLEN);
+ 801e1fc:	69fb      	ldr	r3, [r7, #28]
+ 801e1fe:	685b      	ldr	r3, [r3, #4]
+ 801e200:	3314      	adds	r3, #20
+ 801e202:	617b      	str	r3, [r7, #20]
+    /* Depending on whether the segment has already been sent (unacked) or not
+       (unsent), seg->p->payload points to the IP header or TCP header.
+       Ensure we copy the first TCP data byte: */
+    pbuf_copy_partial(seg->p, d, 1, seg->p->tot_len - seg->len);
+ 801e204:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 801e206:	6858      	ldr	r0, [r3, #4]
+ 801e208:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 801e20a:	685b      	ldr	r3, [r3, #4]
+ 801e20c:	891a      	ldrh	r2, [r3, #8]
+ 801e20e:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 801e210:	891b      	ldrh	r3, [r3, #8]
+ 801e212:	1ad3      	subs	r3, r2, r3
+ 801e214:	b29b      	uxth	r3, r3
+ 801e216:	2201      	movs	r2, #1
+ 801e218:	6979      	ldr	r1, [r7, #20]
+ 801e21a:	f7f9 fe63 	bl	8017ee4 <pbuf_copy_partial>
+  }
+
+  /* The byte may be acknowledged without the window being opened. */
+  snd_nxt = lwip_ntohl(seg->tcphdr->seqno) + 1;
+ 801e21e:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 801e220:	691b      	ldr	r3, [r3, #16]
+ 801e222:	685b      	ldr	r3, [r3, #4]
+ 801e224:	4618      	mov	r0, r3
+ 801e226:	f7f7 fea0 	bl	8015f6a <lwip_htonl>
+ 801e22a:	4603      	mov	r3, r0
+ 801e22c:	3301      	adds	r3, #1
+ 801e22e:	60fb      	str	r3, [r7, #12]
+  if (TCP_SEQ_LT(pcb->snd_nxt, snd_nxt)) {
+ 801e230:	687b      	ldr	r3, [r7, #4]
+ 801e232:	6d1a      	ldr	r2, [r3, #80]	; 0x50
+ 801e234:	68fb      	ldr	r3, [r7, #12]
+ 801e236:	1ad3      	subs	r3, r2, r3
+ 801e238:	2b00      	cmp	r3, #0
+ 801e23a:	da02      	bge.n	801e242 <tcp_zero_window_probe+0x11e>
+    pcb->snd_nxt = snd_nxt;
+ 801e23c:	687b      	ldr	r3, [r7, #4]
+ 801e23e:	68fa      	ldr	r2, [r7, #12]
+ 801e240:	651a      	str	r2, [r3, #80]	; 0x50
+  }
+  tcp_output_fill_options(pcb, p, 0, optlen);
+ 801e242:	7cfb      	ldrb	r3, [r7, #19]
+ 801e244:	2200      	movs	r2, #0
+ 801e246:	69f9      	ldr	r1, [r7, #28]
+ 801e248:	6878      	ldr	r0, [r7, #4]
+ 801e24a:	f7ff fdef 	bl	801de2c <tcp_output_fill_options>
+
+  err = tcp_output_control_segment(pcb, p, &pcb->local_ip, &pcb->remote_ip);
+ 801e24e:	687a      	ldr	r2, [r7, #4]
+ 801e250:	687b      	ldr	r3, [r7, #4]
+ 801e252:	3304      	adds	r3, #4
+ 801e254:	69f9      	ldr	r1, [r7, #28]
+ 801e256:	6878      	ldr	r0, [r7, #4]
+ 801e258:	f7ff fe26 	bl	801dea8 <tcp_output_control_segment>
+ 801e25c:	4603      	mov	r3, r0
+ 801e25e:	72fb      	strb	r3, [r7, #11]
+
+  LWIP_DEBUGF(TCP_DEBUG, ("tcp_zero_window_probe: seqno %"U32_F
+                          " ackno %"U32_F" err %d.\n",
+                          pcb->snd_nxt - 1, pcb->rcv_nxt, (int)err));
+  return err;
+ 801e260:	f997 300b 	ldrsb.w	r3, [r7, #11]
+}
+ 801e264:	4618      	mov	r0, r3
+ 801e266:	372c      	adds	r7, #44	; 0x2c
+ 801e268:	46bd      	mov	sp, r7
+ 801e26a:	bd90      	pop	{r4, r7, pc}
+ 801e26c:	080257b8 	.word	0x080257b8
+ 801e270:	0802600c 	.word	0x0802600c
+ 801e274:	0802580c 	.word	0x0802580c
+
+0801e278 <tcpip_tcp_timer>:
+ *
+ * @param arg unused argument
+ */
+static void
+tcpip_tcp_timer(void *arg)
+{
+ 801e278:	b580      	push	{r7, lr}
+ 801e27a:	b082      	sub	sp, #8
+ 801e27c:	af00      	add	r7, sp, #0
+ 801e27e:	6078      	str	r0, [r7, #4]
+  LWIP_UNUSED_ARG(arg);
+
+  /* call TCP timer handler */
+  tcp_tmr();
+ 801e280:	f7f9 ff1e 	bl	80180c0 <tcp_tmr>
+  /* timer still needed? */
+  if (tcp_active_pcbs || tcp_tw_pcbs) {
+ 801e284:	4b0a      	ldr	r3, [pc, #40]	; (801e2b0 <tcpip_tcp_timer+0x38>)
+ 801e286:	681b      	ldr	r3, [r3, #0]
+ 801e288:	2b00      	cmp	r3, #0
+ 801e28a:	d103      	bne.n	801e294 <tcpip_tcp_timer+0x1c>
+ 801e28c:	4b09      	ldr	r3, [pc, #36]	; (801e2b4 <tcpip_tcp_timer+0x3c>)
+ 801e28e:	681b      	ldr	r3, [r3, #0]
+ 801e290:	2b00      	cmp	r3, #0
+ 801e292:	d005      	beq.n	801e2a0 <tcpip_tcp_timer+0x28>
+    /* restart timer */
+    sys_timeout(TCP_TMR_INTERVAL, tcpip_tcp_timer, NULL);
+ 801e294:	2200      	movs	r2, #0
+ 801e296:	4908      	ldr	r1, [pc, #32]	; (801e2b8 <tcpip_tcp_timer+0x40>)
+ 801e298:	20fa      	movs	r0, #250	; 0xfa
+ 801e29a:	f000 f8f3 	bl	801e484 <sys_timeout>
+ 801e29e:	e003      	b.n	801e2a8 <tcpip_tcp_timer+0x30>
+  } else {
+    /* disable timer */
+    tcpip_tcp_timer_active = 0;
+ 801e2a0:	4b06      	ldr	r3, [pc, #24]	; (801e2bc <tcpip_tcp_timer+0x44>)
+ 801e2a2:	2200      	movs	r2, #0
+ 801e2a4:	601a      	str	r2, [r3, #0]
+  }
+}
+ 801e2a6:	bf00      	nop
+ 801e2a8:	bf00      	nop
+ 801e2aa:	3708      	adds	r7, #8
+ 801e2ac:	46bd      	mov	sp, r7
+ 801e2ae:	bd80      	pop	{r7, pc}
+ 801e2b0:	2401a48c 	.word	0x2401a48c
+ 801e2b4:	2401a490 	.word	0x2401a490
+ 801e2b8:	0801e279 	.word	0x0801e279
+ 801e2bc:	2401a4dc 	.word	0x2401a4dc
+
+0801e2c0 <tcp_timer_needed>:
+ * the reason is to have the TCP timer only running when
+ * there are active (or time-wait) PCBs.
+ */
+void
+tcp_timer_needed(void)
+{
+ 801e2c0:	b580      	push	{r7, lr}
+ 801e2c2:	af00      	add	r7, sp, #0
+  LWIP_ASSERT_CORE_LOCKED();
+
+  /* timer is off but needed again? */
+  if (!tcpip_tcp_timer_active && (tcp_active_pcbs || tcp_tw_pcbs)) {
+ 801e2c4:	4b0a      	ldr	r3, [pc, #40]	; (801e2f0 <tcp_timer_needed+0x30>)
+ 801e2c6:	681b      	ldr	r3, [r3, #0]
+ 801e2c8:	2b00      	cmp	r3, #0
+ 801e2ca:	d10f      	bne.n	801e2ec <tcp_timer_needed+0x2c>
+ 801e2cc:	4b09      	ldr	r3, [pc, #36]	; (801e2f4 <tcp_timer_needed+0x34>)
+ 801e2ce:	681b      	ldr	r3, [r3, #0]
+ 801e2d0:	2b00      	cmp	r3, #0
+ 801e2d2:	d103      	bne.n	801e2dc <tcp_timer_needed+0x1c>
+ 801e2d4:	4b08      	ldr	r3, [pc, #32]	; (801e2f8 <tcp_timer_needed+0x38>)
+ 801e2d6:	681b      	ldr	r3, [r3, #0]
+ 801e2d8:	2b00      	cmp	r3, #0
+ 801e2da:	d007      	beq.n	801e2ec <tcp_timer_needed+0x2c>
+    /* enable and start timer */
+    tcpip_tcp_timer_active = 1;
+ 801e2dc:	4b04      	ldr	r3, [pc, #16]	; (801e2f0 <tcp_timer_needed+0x30>)
+ 801e2de:	2201      	movs	r2, #1
+ 801e2e0:	601a      	str	r2, [r3, #0]
+    sys_timeout(TCP_TMR_INTERVAL, tcpip_tcp_timer, NULL);
+ 801e2e2:	2200      	movs	r2, #0
+ 801e2e4:	4905      	ldr	r1, [pc, #20]	; (801e2fc <tcp_timer_needed+0x3c>)
+ 801e2e6:	20fa      	movs	r0, #250	; 0xfa
+ 801e2e8:	f000 f8cc 	bl	801e484 <sys_timeout>
+  }
+}
+ 801e2ec:	bf00      	nop
+ 801e2ee:	bd80      	pop	{r7, pc}
+ 801e2f0:	2401a4dc 	.word	0x2401a4dc
+ 801e2f4:	2401a48c 	.word	0x2401a48c
+ 801e2f8:	2401a490 	.word	0x2401a490
+ 801e2fc:	0801e279 	.word	0x0801e279
+
+0801e300 <sys_timeout_abs>:
+#if LWIP_DEBUG_TIMERNAMES
+sys_timeout_abs(u32_t abs_time, sys_timeout_handler handler, void *arg, const char *handler_name)
+#else /* LWIP_DEBUG_TIMERNAMES */
+sys_timeout_abs(u32_t abs_time, sys_timeout_handler handler, void *arg)
+#endif
+{
+ 801e300:	b580      	push	{r7, lr}
+ 801e302:	b086      	sub	sp, #24
+ 801e304:	af00      	add	r7, sp, #0
+ 801e306:	60f8      	str	r0, [r7, #12]
+ 801e308:	60b9      	str	r1, [r7, #8]
+ 801e30a:	607a      	str	r2, [r7, #4]
+  struct sys_timeo *timeout, *t;
+
+  timeout = (struct sys_timeo *)memp_malloc(MEMP_SYS_TIMEOUT);
+ 801e30c:	200a      	movs	r0, #10
+ 801e30e:	f7f8 fbdf 	bl	8016ad0 <memp_malloc>
+ 801e312:	6138      	str	r0, [r7, #16]
+  if (timeout == NULL) {
+ 801e314:	693b      	ldr	r3, [r7, #16]
+ 801e316:	2b00      	cmp	r3, #0
+ 801e318:	d109      	bne.n	801e32e <sys_timeout_abs+0x2e>
+    LWIP_ASSERT("sys_timeout: timeout != NULL, pool MEMP_SYS_TIMEOUT is empty", timeout != NULL);
+ 801e31a:	693b      	ldr	r3, [r7, #16]
+ 801e31c:	2b00      	cmp	r3, #0
+ 801e31e:	d151      	bne.n	801e3c4 <sys_timeout_abs+0xc4>
+ 801e320:	4b2a      	ldr	r3, [pc, #168]	; (801e3cc <sys_timeout_abs+0xcc>)
+ 801e322:	22be      	movs	r2, #190	; 0xbe
+ 801e324:	492a      	ldr	r1, [pc, #168]	; (801e3d0 <sys_timeout_abs+0xd0>)
+ 801e326:	482b      	ldr	r0, [pc, #172]	; (801e3d4 <sys_timeout_abs+0xd4>)
+ 801e328:	f003 fb2e 	bl	8021988 <iprintf>
+    return;
+ 801e32c:	e04a      	b.n	801e3c4 <sys_timeout_abs+0xc4>
+  }
+
+  timeout->next = NULL;
+ 801e32e:	693b      	ldr	r3, [r7, #16]
+ 801e330:	2200      	movs	r2, #0
+ 801e332:	601a      	str	r2, [r3, #0]
+  timeout->h = handler;
+ 801e334:	693b      	ldr	r3, [r7, #16]
+ 801e336:	68ba      	ldr	r2, [r7, #8]
+ 801e338:	609a      	str	r2, [r3, #8]
+  timeout->arg = arg;
+ 801e33a:	693b      	ldr	r3, [r7, #16]
+ 801e33c:	687a      	ldr	r2, [r7, #4]
+ 801e33e:	60da      	str	r2, [r3, #12]
+  timeout->time = abs_time;
+ 801e340:	693b      	ldr	r3, [r7, #16]
+ 801e342:	68fa      	ldr	r2, [r7, #12]
+ 801e344:	605a      	str	r2, [r3, #4]
+  timeout->handler_name = handler_name;
+  LWIP_DEBUGF(TIMERS_DEBUG, ("sys_timeout: %p abs_time=%"U32_F" handler=%s arg=%p\n",
+                             (void *)timeout, abs_time, handler_name, (void *)arg));
+#endif /* LWIP_DEBUG_TIMERNAMES */
+
+  if (next_timeout == NULL) {
+ 801e346:	4b24      	ldr	r3, [pc, #144]	; (801e3d8 <sys_timeout_abs+0xd8>)
+ 801e348:	681b      	ldr	r3, [r3, #0]
+ 801e34a:	2b00      	cmp	r3, #0
+ 801e34c:	d103      	bne.n	801e356 <sys_timeout_abs+0x56>
+    next_timeout = timeout;
+ 801e34e:	4a22      	ldr	r2, [pc, #136]	; (801e3d8 <sys_timeout_abs+0xd8>)
+ 801e350:	693b      	ldr	r3, [r7, #16]
+ 801e352:	6013      	str	r3, [r2, #0]
+    return;
+ 801e354:	e037      	b.n	801e3c6 <sys_timeout_abs+0xc6>
+  }
+  if (TIME_LESS_THAN(timeout->time, next_timeout->time)) {
+ 801e356:	693b      	ldr	r3, [r7, #16]
+ 801e358:	685a      	ldr	r2, [r3, #4]
+ 801e35a:	4b1f      	ldr	r3, [pc, #124]	; (801e3d8 <sys_timeout_abs+0xd8>)
+ 801e35c:	681b      	ldr	r3, [r3, #0]
+ 801e35e:	685b      	ldr	r3, [r3, #4]
+ 801e360:	1ad3      	subs	r3, r2, r3
+ 801e362:	0fdb      	lsrs	r3, r3, #31
+ 801e364:	f003 0301 	and.w	r3, r3, #1
+ 801e368:	b2db      	uxtb	r3, r3
+ 801e36a:	2b00      	cmp	r3, #0
+ 801e36c:	d007      	beq.n	801e37e <sys_timeout_abs+0x7e>
+    timeout->next = next_timeout;
+ 801e36e:	4b1a      	ldr	r3, [pc, #104]	; (801e3d8 <sys_timeout_abs+0xd8>)
+ 801e370:	681a      	ldr	r2, [r3, #0]
+ 801e372:	693b      	ldr	r3, [r7, #16]
+ 801e374:	601a      	str	r2, [r3, #0]
+    next_timeout = timeout;
+ 801e376:	4a18      	ldr	r2, [pc, #96]	; (801e3d8 <sys_timeout_abs+0xd8>)
+ 801e378:	693b      	ldr	r3, [r7, #16]
+ 801e37a:	6013      	str	r3, [r2, #0]
+ 801e37c:	e023      	b.n	801e3c6 <sys_timeout_abs+0xc6>
+  } else {
+    for (t = next_timeout; t != NULL; t = t->next) {
+ 801e37e:	4b16      	ldr	r3, [pc, #88]	; (801e3d8 <sys_timeout_abs+0xd8>)
+ 801e380:	681b      	ldr	r3, [r3, #0]
+ 801e382:	617b      	str	r3, [r7, #20]
+ 801e384:	e01a      	b.n	801e3bc <sys_timeout_abs+0xbc>
+      if ((t->next == NULL) || TIME_LESS_THAN(timeout->time, t->next->time)) {
+ 801e386:	697b      	ldr	r3, [r7, #20]
+ 801e388:	681b      	ldr	r3, [r3, #0]
+ 801e38a:	2b00      	cmp	r3, #0
+ 801e38c:	d00b      	beq.n	801e3a6 <sys_timeout_abs+0xa6>
+ 801e38e:	693b      	ldr	r3, [r7, #16]
+ 801e390:	685a      	ldr	r2, [r3, #4]
+ 801e392:	697b      	ldr	r3, [r7, #20]
+ 801e394:	681b      	ldr	r3, [r3, #0]
+ 801e396:	685b      	ldr	r3, [r3, #4]
+ 801e398:	1ad3      	subs	r3, r2, r3
+ 801e39a:	0fdb      	lsrs	r3, r3, #31
+ 801e39c:	f003 0301 	and.w	r3, r3, #1
+ 801e3a0:	b2db      	uxtb	r3, r3
+ 801e3a2:	2b00      	cmp	r3, #0
+ 801e3a4:	d007      	beq.n	801e3b6 <sys_timeout_abs+0xb6>
+        timeout->next = t->next;
+ 801e3a6:	697b      	ldr	r3, [r7, #20]
+ 801e3a8:	681a      	ldr	r2, [r3, #0]
+ 801e3aa:	693b      	ldr	r3, [r7, #16]
+ 801e3ac:	601a      	str	r2, [r3, #0]
+        t->next = timeout;
+ 801e3ae:	697b      	ldr	r3, [r7, #20]
+ 801e3b0:	693a      	ldr	r2, [r7, #16]
+ 801e3b2:	601a      	str	r2, [r3, #0]
+        break;
+ 801e3b4:	e007      	b.n	801e3c6 <sys_timeout_abs+0xc6>
+    for (t = next_timeout; t != NULL; t = t->next) {
+ 801e3b6:	697b      	ldr	r3, [r7, #20]
+ 801e3b8:	681b      	ldr	r3, [r3, #0]
+ 801e3ba:	617b      	str	r3, [r7, #20]
+ 801e3bc:	697b      	ldr	r3, [r7, #20]
+ 801e3be:	2b00      	cmp	r3, #0
+ 801e3c0:	d1e1      	bne.n	801e386 <sys_timeout_abs+0x86>
+ 801e3c2:	e000      	b.n	801e3c6 <sys_timeout_abs+0xc6>
+    return;
+ 801e3c4:	bf00      	nop
+      }
+    }
+  }
+}
+ 801e3c6:	3718      	adds	r7, #24
+ 801e3c8:	46bd      	mov	sp, r7
+ 801e3ca:	bd80      	pop	{r7, pc}
+ 801e3cc:	08026030 	.word	0x08026030
+ 801e3d0:	08026064 	.word	0x08026064
+ 801e3d4:	080260a4 	.word	0x080260a4
+ 801e3d8:	2401a4d4 	.word	0x2401a4d4
+
+0801e3dc <lwip_cyclic_timer>:
+#if !LWIP_TESTMODE
+static
+#endif
+void
+lwip_cyclic_timer(void *arg)
+{
+ 801e3dc:	b580      	push	{r7, lr}
+ 801e3de:	b086      	sub	sp, #24
+ 801e3e0:	af00      	add	r7, sp, #0
+ 801e3e2:	6078      	str	r0, [r7, #4]
+  u32_t now;
+  u32_t next_timeout_time;
+  const struct lwip_cyclic_timer *cyclic = (const struct lwip_cyclic_timer *)arg;
+ 801e3e4:	687b      	ldr	r3, [r7, #4]
+ 801e3e6:	617b      	str	r3, [r7, #20]
+
+#if LWIP_DEBUG_TIMERNAMES
+  LWIP_DEBUGF(TIMERS_DEBUG, ("tcpip: %s()\n", cyclic->handler_name));
+#endif
+  cyclic->handler();
+ 801e3e8:	697b      	ldr	r3, [r7, #20]
+ 801e3ea:	685b      	ldr	r3, [r3, #4]
+ 801e3ec:	4798      	blx	r3
+
+  now = sys_now();
+ 801e3ee:	f7f1 fc97 	bl	800fd20 <sys_now>
+ 801e3f2:	6138      	str	r0, [r7, #16]
+  next_timeout_time = (u32_t)(current_timeout_due_time + cyclic->interval_ms);  /* overflow handled by TIME_LESS_THAN macro */ 
+ 801e3f4:	697b      	ldr	r3, [r7, #20]
+ 801e3f6:	681a      	ldr	r2, [r3, #0]
+ 801e3f8:	4b0f      	ldr	r3, [pc, #60]	; (801e438 <lwip_cyclic_timer+0x5c>)
+ 801e3fa:	681b      	ldr	r3, [r3, #0]
+ 801e3fc:	4413      	add	r3, r2
+ 801e3fe:	60fb      	str	r3, [r7, #12]
+  if (TIME_LESS_THAN(next_timeout_time, now)) {
+ 801e400:	68fa      	ldr	r2, [r7, #12]
+ 801e402:	693b      	ldr	r3, [r7, #16]
+ 801e404:	1ad3      	subs	r3, r2, r3
+ 801e406:	0fdb      	lsrs	r3, r3, #31
+ 801e408:	f003 0301 	and.w	r3, r3, #1
+ 801e40c:	b2db      	uxtb	r3, r3
+ 801e40e:	2b00      	cmp	r3, #0
+ 801e410:	d009      	beq.n	801e426 <lwip_cyclic_timer+0x4a>
+    /* timer would immediately expire again -> "overload" -> restart without any correction */
+#if LWIP_DEBUG_TIMERNAMES
+    sys_timeout_abs((u32_t)(now + cyclic->interval_ms), lwip_cyclic_timer, arg, cyclic->handler_name);
+#else
+    sys_timeout_abs((u32_t)(now + cyclic->interval_ms), lwip_cyclic_timer, arg);
+ 801e412:	697b      	ldr	r3, [r7, #20]
+ 801e414:	681a      	ldr	r2, [r3, #0]
+ 801e416:	693b      	ldr	r3, [r7, #16]
+ 801e418:	4413      	add	r3, r2
+ 801e41a:	687a      	ldr	r2, [r7, #4]
+ 801e41c:	4907      	ldr	r1, [pc, #28]	; (801e43c <lwip_cyclic_timer+0x60>)
+ 801e41e:	4618      	mov	r0, r3
+ 801e420:	f7ff ff6e 	bl	801e300 <sys_timeout_abs>
+    sys_timeout_abs(next_timeout_time, lwip_cyclic_timer, arg, cyclic->handler_name);
+#else
+    sys_timeout_abs(next_timeout_time, lwip_cyclic_timer, arg);
+#endif
+  }
+}
+ 801e424:	e004      	b.n	801e430 <lwip_cyclic_timer+0x54>
+    sys_timeout_abs(next_timeout_time, lwip_cyclic_timer, arg);
+ 801e426:	687a      	ldr	r2, [r7, #4]
+ 801e428:	4904      	ldr	r1, [pc, #16]	; (801e43c <lwip_cyclic_timer+0x60>)
+ 801e42a:	68f8      	ldr	r0, [r7, #12]
+ 801e42c:	f7ff ff68 	bl	801e300 <sys_timeout_abs>
+}
+ 801e430:	bf00      	nop
+ 801e432:	3718      	adds	r7, #24
+ 801e434:	46bd      	mov	sp, r7
+ 801e436:	bd80      	pop	{r7, pc}
+ 801e438:	2401a4d8 	.word	0x2401a4d8
+ 801e43c:	0801e3dd 	.word	0x0801e3dd
+
+0801e440 <sys_timeouts_init>:
+
+/** Initialize this module */
+void sys_timeouts_init(void)
+{
+ 801e440:	b580      	push	{r7, lr}
+ 801e442:	b082      	sub	sp, #8
+ 801e444:	af00      	add	r7, sp, #0
+  size_t i;
+  /* tcp_tmr() at index 0 is started on demand */
+  for (i = (LWIP_TCP ? 1 : 0); i < LWIP_ARRAYSIZE(lwip_cyclic_timers); i++) {
+ 801e446:	2301      	movs	r3, #1
+ 801e448:	607b      	str	r3, [r7, #4]
+ 801e44a:	e00e      	b.n	801e46a <sys_timeouts_init+0x2a>
+    /* we have to cast via size_t to get rid of const warning
+      (this is OK as cyclic_timer() casts back to const* */
+    sys_timeout(lwip_cyclic_timers[i].interval_ms, lwip_cyclic_timer, LWIP_CONST_CAST(void *, &lwip_cyclic_timers[i]));
+ 801e44c:	4a0b      	ldr	r2, [pc, #44]	; (801e47c <sys_timeouts_init+0x3c>)
+ 801e44e:	687b      	ldr	r3, [r7, #4]
+ 801e450:	f852 0033 	ldr.w	r0, [r2, r3, lsl #3]
+ 801e454:	687b      	ldr	r3, [r7, #4]
+ 801e456:	00db      	lsls	r3, r3, #3
+ 801e458:	4a08      	ldr	r2, [pc, #32]	; (801e47c <sys_timeouts_init+0x3c>)
+ 801e45a:	4413      	add	r3, r2
+ 801e45c:	461a      	mov	r2, r3
+ 801e45e:	4908      	ldr	r1, [pc, #32]	; (801e480 <sys_timeouts_init+0x40>)
+ 801e460:	f000 f810 	bl	801e484 <sys_timeout>
+  for (i = (LWIP_TCP ? 1 : 0); i < LWIP_ARRAYSIZE(lwip_cyclic_timers); i++) {
+ 801e464:	687b      	ldr	r3, [r7, #4]
+ 801e466:	3301      	adds	r3, #1
+ 801e468:	607b      	str	r3, [r7, #4]
+ 801e46a:	687b      	ldr	r3, [r7, #4]
+ 801e46c:	2b02      	cmp	r3, #2
+ 801e46e:	d9ed      	bls.n	801e44c <sys_timeouts_init+0xc>
+  }
+}
+ 801e470:	bf00      	nop
+ 801e472:	bf00      	nop
+ 801e474:	3708      	adds	r7, #8
+ 801e476:	46bd      	mov	sp, r7
+ 801e478:	bd80      	pop	{r7, pc}
+ 801e47a:	bf00      	nop
+ 801e47c:	08026cd4 	.word	0x08026cd4
+ 801e480:	0801e3dd 	.word	0x0801e3dd
+
+0801e484 <sys_timeout>:
+sys_timeout_debug(u32_t msecs, sys_timeout_handler handler, void *arg, const char *handler_name)
+#else /* LWIP_DEBUG_TIMERNAMES */
+void
+sys_timeout(u32_t msecs, sys_timeout_handler handler, void *arg)
+#endif /* LWIP_DEBUG_TIMERNAMES */
+{
+ 801e484:	b580      	push	{r7, lr}
+ 801e486:	b086      	sub	sp, #24
+ 801e488:	af00      	add	r7, sp, #0
+ 801e48a:	60f8      	str	r0, [r7, #12]
+ 801e48c:	60b9      	str	r1, [r7, #8]
+ 801e48e:	607a      	str	r2, [r7, #4]
+  u32_t next_timeout_time;
+
+  LWIP_ASSERT_CORE_LOCKED();
+
+  LWIP_ASSERT("Timeout time too long, max is LWIP_UINT32_MAX/4 msecs", msecs <= (LWIP_UINT32_MAX / 4));
+ 801e490:	68fb      	ldr	r3, [r7, #12]
+ 801e492:	f1b3 4f80 	cmp.w	r3, #1073741824	; 0x40000000
+ 801e496:	d306      	bcc.n	801e4a6 <sys_timeout+0x22>
+ 801e498:	4b0a      	ldr	r3, [pc, #40]	; (801e4c4 <sys_timeout+0x40>)
+ 801e49a:	f240 1229 	movw	r2, #297	; 0x129
+ 801e49e:	490a      	ldr	r1, [pc, #40]	; (801e4c8 <sys_timeout+0x44>)
+ 801e4a0:	480a      	ldr	r0, [pc, #40]	; (801e4cc <sys_timeout+0x48>)
+ 801e4a2:	f003 fa71 	bl	8021988 <iprintf>
+
+  next_timeout_time = (u32_t)(sys_now() + msecs); /* overflow handled by TIME_LESS_THAN macro */ 
+ 801e4a6:	f7f1 fc3b 	bl	800fd20 <sys_now>
+ 801e4aa:	4602      	mov	r2, r0
+ 801e4ac:	68fb      	ldr	r3, [r7, #12]
+ 801e4ae:	4413      	add	r3, r2
+ 801e4b0:	617b      	str	r3, [r7, #20]
+
+#if LWIP_DEBUG_TIMERNAMES
+  sys_timeout_abs(next_timeout_time, handler, arg, handler_name);
+#else
+  sys_timeout_abs(next_timeout_time, handler, arg);
+ 801e4b2:	687a      	ldr	r2, [r7, #4]
+ 801e4b4:	68b9      	ldr	r1, [r7, #8]
+ 801e4b6:	6978      	ldr	r0, [r7, #20]
+ 801e4b8:	f7ff ff22 	bl	801e300 <sys_timeout_abs>
+#endif
+}
+ 801e4bc:	bf00      	nop
+ 801e4be:	3718      	adds	r7, #24
+ 801e4c0:	46bd      	mov	sp, r7
+ 801e4c2:	bd80      	pop	{r7, pc}
+ 801e4c4:	08026030 	.word	0x08026030
+ 801e4c8:	080260cc 	.word	0x080260cc
+ 801e4cc:	080260a4 	.word	0x080260a4
+
+0801e4d0 <sys_check_timeouts>:
+ *
+ * Must be called periodically from your main loop.
+ */
+void
+sys_check_timeouts(void)
+{
+ 801e4d0:	b580      	push	{r7, lr}
+ 801e4d2:	b084      	sub	sp, #16
+ 801e4d4:	af00      	add	r7, sp, #0
+  u32_t now;
+
+  LWIP_ASSERT_CORE_LOCKED();
+
+  /* Process only timers expired at the start of the function. */
+  now = sys_now();
+ 801e4d6:	f7f1 fc23 	bl	800fd20 <sys_now>
+ 801e4da:	60f8      	str	r0, [r7, #12]
+    sys_timeout_handler handler;
+    void *arg;
+
+    PBUF_CHECK_FREE_OOSEQ();
+
+    tmptimeout = next_timeout;
+ 801e4dc:	4b17      	ldr	r3, [pc, #92]	; (801e53c <sys_check_timeouts+0x6c>)
+ 801e4de:	681b      	ldr	r3, [r3, #0]
+ 801e4e0:	60bb      	str	r3, [r7, #8]
+    if (tmptimeout == NULL) {
+ 801e4e2:	68bb      	ldr	r3, [r7, #8]
+ 801e4e4:	2b00      	cmp	r3, #0
+ 801e4e6:	d022      	beq.n	801e52e <sys_check_timeouts+0x5e>
+      return;
+    }
+
+    if (TIME_LESS_THAN(now, tmptimeout->time)) {
+ 801e4e8:	68bb      	ldr	r3, [r7, #8]
+ 801e4ea:	685b      	ldr	r3, [r3, #4]
+ 801e4ec:	68fa      	ldr	r2, [r7, #12]
+ 801e4ee:	1ad3      	subs	r3, r2, r3
+ 801e4f0:	0fdb      	lsrs	r3, r3, #31
+ 801e4f2:	f003 0301 	and.w	r3, r3, #1
+ 801e4f6:	b2db      	uxtb	r3, r3
+ 801e4f8:	2b00      	cmp	r3, #0
+ 801e4fa:	d11a      	bne.n	801e532 <sys_check_timeouts+0x62>
+      return;
+    }
+
+    /* Timeout has expired */
+    next_timeout = tmptimeout->next;
+ 801e4fc:	68bb      	ldr	r3, [r7, #8]
+ 801e4fe:	681b      	ldr	r3, [r3, #0]
+ 801e500:	4a0e      	ldr	r2, [pc, #56]	; (801e53c <sys_check_timeouts+0x6c>)
+ 801e502:	6013      	str	r3, [r2, #0]
+    handler = tmptimeout->h;
+ 801e504:	68bb      	ldr	r3, [r7, #8]
+ 801e506:	689b      	ldr	r3, [r3, #8]
+ 801e508:	607b      	str	r3, [r7, #4]
+    arg = tmptimeout->arg;
+ 801e50a:	68bb      	ldr	r3, [r7, #8]
+ 801e50c:	68db      	ldr	r3, [r3, #12]
+ 801e50e:	603b      	str	r3, [r7, #0]
+    current_timeout_due_time = tmptimeout->time;
+ 801e510:	68bb      	ldr	r3, [r7, #8]
+ 801e512:	685b      	ldr	r3, [r3, #4]
+ 801e514:	4a0a      	ldr	r2, [pc, #40]	; (801e540 <sys_check_timeouts+0x70>)
+ 801e516:	6013      	str	r3, [r2, #0]
+    if (handler != NULL) {
+      LWIP_DEBUGF(TIMERS_DEBUG, ("sct calling h=%s t=%"U32_F" arg=%p\n",
+                                 tmptimeout->handler_name, sys_now() - tmptimeout->time, arg));
+    }
+#endif /* LWIP_DEBUG_TIMERNAMES */
+    memp_free(MEMP_SYS_TIMEOUT, tmptimeout);
+ 801e518:	68b9      	ldr	r1, [r7, #8]
+ 801e51a:	200a      	movs	r0, #10
+ 801e51c:	f7f8 fb4e 	bl	8016bbc <memp_free>
+    if (handler != NULL) {
+ 801e520:	687b      	ldr	r3, [r7, #4]
+ 801e522:	2b00      	cmp	r3, #0
+ 801e524:	d0da      	beq.n	801e4dc <sys_check_timeouts+0xc>
+      handler(arg);
+ 801e526:	687b      	ldr	r3, [r7, #4]
+ 801e528:	6838      	ldr	r0, [r7, #0]
+ 801e52a:	4798      	blx	r3
+  do {
+ 801e52c:	e7d6      	b.n	801e4dc <sys_check_timeouts+0xc>
+      return;
+ 801e52e:	bf00      	nop
+ 801e530:	e000      	b.n	801e534 <sys_check_timeouts+0x64>
+      return;
+ 801e532:	bf00      	nop
+    }
+    LWIP_TCPIP_THREAD_ALIVE();
+
+    /* Repeat until all expired timers have been called */
+  } while (1);
+}
+ 801e534:	3710      	adds	r7, #16
+ 801e536:	46bd      	mov	sp, r7
+ 801e538:	bd80      	pop	{r7, pc}
+ 801e53a:	bf00      	nop
+ 801e53c:	2401a4d4 	.word	0x2401a4d4
+ 801e540:	2401a4d8 	.word	0x2401a4d8
+
+0801e544 <sys_timeouts_sleeptime>:
+/** Return the time left before the next timeout is due. If no timeouts are
+ * enqueued, returns 0xffffffff
+ */
+u32_t
+sys_timeouts_sleeptime(void)
+{
+ 801e544:	b580      	push	{r7, lr}
+ 801e546:	b082      	sub	sp, #8
+ 801e548:	af00      	add	r7, sp, #0
+  u32_t now;
+
+  LWIP_ASSERT_CORE_LOCKED();
+
+  if (next_timeout == NULL) {
+ 801e54a:	4b16      	ldr	r3, [pc, #88]	; (801e5a4 <sys_timeouts_sleeptime+0x60>)
+ 801e54c:	681b      	ldr	r3, [r3, #0]
+ 801e54e:	2b00      	cmp	r3, #0
+ 801e550:	d102      	bne.n	801e558 <sys_timeouts_sleeptime+0x14>
+    return SYS_TIMEOUTS_SLEEPTIME_INFINITE;
+ 801e552:	f04f 33ff 	mov.w	r3, #4294967295
+ 801e556:	e020      	b.n	801e59a <sys_timeouts_sleeptime+0x56>
+  }
+  now = sys_now();
+ 801e558:	f7f1 fbe2 	bl	800fd20 <sys_now>
+ 801e55c:	6078      	str	r0, [r7, #4]
+  if (TIME_LESS_THAN(next_timeout->time, now)) {
+ 801e55e:	4b11      	ldr	r3, [pc, #68]	; (801e5a4 <sys_timeouts_sleeptime+0x60>)
+ 801e560:	681b      	ldr	r3, [r3, #0]
+ 801e562:	685a      	ldr	r2, [r3, #4]
+ 801e564:	687b      	ldr	r3, [r7, #4]
+ 801e566:	1ad3      	subs	r3, r2, r3
+ 801e568:	0fdb      	lsrs	r3, r3, #31
+ 801e56a:	f003 0301 	and.w	r3, r3, #1
+ 801e56e:	b2db      	uxtb	r3, r3
+ 801e570:	2b00      	cmp	r3, #0
+ 801e572:	d001      	beq.n	801e578 <sys_timeouts_sleeptime+0x34>
+    return 0;
+ 801e574:	2300      	movs	r3, #0
+ 801e576:	e010      	b.n	801e59a <sys_timeouts_sleeptime+0x56>
+  } else {
+    u32_t ret = (u32_t)(next_timeout->time - now);
+ 801e578:	4b0a      	ldr	r3, [pc, #40]	; (801e5a4 <sys_timeouts_sleeptime+0x60>)
+ 801e57a:	681b      	ldr	r3, [r3, #0]
+ 801e57c:	685a      	ldr	r2, [r3, #4]
+ 801e57e:	687b      	ldr	r3, [r7, #4]
+ 801e580:	1ad3      	subs	r3, r2, r3
+ 801e582:	603b      	str	r3, [r7, #0]
+    LWIP_ASSERT("invalid sleeptime", ret <= LWIP_MAX_TIMEOUT);
+ 801e584:	683b      	ldr	r3, [r7, #0]
+ 801e586:	2b00      	cmp	r3, #0
+ 801e588:	da06      	bge.n	801e598 <sys_timeouts_sleeptime+0x54>
+ 801e58a:	4b07      	ldr	r3, [pc, #28]	; (801e5a8 <sys_timeouts_sleeptime+0x64>)
+ 801e58c:	f44f 72dc 	mov.w	r2, #440	; 0x1b8
+ 801e590:	4906      	ldr	r1, [pc, #24]	; (801e5ac <sys_timeouts_sleeptime+0x68>)
+ 801e592:	4807      	ldr	r0, [pc, #28]	; (801e5b0 <sys_timeouts_sleeptime+0x6c>)
+ 801e594:	f003 f9f8 	bl	8021988 <iprintf>
+    return ret;
+ 801e598:	683b      	ldr	r3, [r7, #0]
+  }
+}
+ 801e59a:	4618      	mov	r0, r3
+ 801e59c:	3708      	adds	r7, #8
+ 801e59e:	46bd      	mov	sp, r7
+ 801e5a0:	bd80      	pop	{r7, pc}
+ 801e5a2:	bf00      	nop
+ 801e5a4:	2401a4d4 	.word	0x2401a4d4
+ 801e5a8:	08026030 	.word	0x08026030
+ 801e5ac:	08026104 	.word	0x08026104
+ 801e5b0:	080260a4 	.word	0x080260a4
+
+0801e5b4 <udp_init>:
+/**
+ * Initialize this module.
+ */
+void
+udp_init(void)
+{
+ 801e5b4:	b580      	push	{r7, lr}
+ 801e5b6:	af00      	add	r7, sp, #0
+#ifdef LWIP_RAND
+  udp_port = UDP_ENSURE_LOCAL_PORT_RANGE(LWIP_RAND());
+ 801e5b8:	f003 f86a 	bl	8021690 <rand>
+ 801e5bc:	4603      	mov	r3, r0
+ 801e5be:	b29b      	uxth	r3, r3
+ 801e5c0:	f3c3 030d 	ubfx	r3, r3, #0, #14
+ 801e5c4:	b29b      	uxth	r3, r3
+ 801e5c6:	f5a3 4380 	sub.w	r3, r3, #16384	; 0x4000
+ 801e5ca:	b29a      	uxth	r2, r3
+ 801e5cc:	4b01      	ldr	r3, [pc, #4]	; (801e5d4 <udp_init+0x20>)
+ 801e5ce:	801a      	strh	r2, [r3, #0]
+#endif /* LWIP_RAND */
+}
+ 801e5d0:	bf00      	nop
+ 801e5d2:	bd80      	pop	{r7, pc}
+ 801e5d4:	24000044 	.word	0x24000044
+
+0801e5d8 <udp_new_port>:
+ *
+ * @return a new (free) local UDP port number
+ */
+static u16_t
+udp_new_port(void)
+{
+ 801e5d8:	b480      	push	{r7}
+ 801e5da:	b083      	sub	sp, #12
+ 801e5dc:	af00      	add	r7, sp, #0
+  u16_t n = 0;
+ 801e5de:	2300      	movs	r3, #0
+ 801e5e0:	80fb      	strh	r3, [r7, #6]
+  struct udp_pcb *pcb;
+
+again:
+  if (udp_port++ == UDP_LOCAL_PORT_RANGE_END) {
+ 801e5e2:	4b17      	ldr	r3, [pc, #92]	; (801e640 <udp_new_port+0x68>)
+ 801e5e4:	881b      	ldrh	r3, [r3, #0]
+ 801e5e6:	1c5a      	adds	r2, r3, #1
+ 801e5e8:	b291      	uxth	r1, r2
+ 801e5ea:	4a15      	ldr	r2, [pc, #84]	; (801e640 <udp_new_port+0x68>)
+ 801e5ec:	8011      	strh	r1, [r2, #0]
+ 801e5ee:	f64f 72ff 	movw	r2, #65535	; 0xffff
+ 801e5f2:	4293      	cmp	r3, r2
+ 801e5f4:	d103      	bne.n	801e5fe <udp_new_port+0x26>
+    udp_port = UDP_LOCAL_PORT_RANGE_START;
+ 801e5f6:	4b12      	ldr	r3, [pc, #72]	; (801e640 <udp_new_port+0x68>)
+ 801e5f8:	f44f 4240 	mov.w	r2, #49152	; 0xc000
+ 801e5fc:	801a      	strh	r2, [r3, #0]
+  }
+  /* Check all PCBs. */
+  for (pcb = udp_pcbs; pcb != NULL; pcb = pcb->next) {
+ 801e5fe:	4b11      	ldr	r3, [pc, #68]	; (801e644 <udp_new_port+0x6c>)
+ 801e600:	681b      	ldr	r3, [r3, #0]
+ 801e602:	603b      	str	r3, [r7, #0]
+ 801e604:	e011      	b.n	801e62a <udp_new_port+0x52>
+    if (pcb->local_port == udp_port) {
+ 801e606:	683b      	ldr	r3, [r7, #0]
+ 801e608:	8a5a      	ldrh	r2, [r3, #18]
+ 801e60a:	4b0d      	ldr	r3, [pc, #52]	; (801e640 <udp_new_port+0x68>)
+ 801e60c:	881b      	ldrh	r3, [r3, #0]
+ 801e60e:	429a      	cmp	r2, r3
+ 801e610:	d108      	bne.n	801e624 <udp_new_port+0x4c>
+      if (++n > (UDP_LOCAL_PORT_RANGE_END - UDP_LOCAL_PORT_RANGE_START)) {
+ 801e612:	88fb      	ldrh	r3, [r7, #6]
+ 801e614:	3301      	adds	r3, #1
+ 801e616:	80fb      	strh	r3, [r7, #6]
+ 801e618:	88fb      	ldrh	r3, [r7, #6]
+ 801e61a:	f5b3 4f80 	cmp.w	r3, #16384	; 0x4000
+ 801e61e:	d3e0      	bcc.n	801e5e2 <udp_new_port+0xa>
+        return 0;
+ 801e620:	2300      	movs	r3, #0
+ 801e622:	e007      	b.n	801e634 <udp_new_port+0x5c>
+  for (pcb = udp_pcbs; pcb != NULL; pcb = pcb->next) {
+ 801e624:	683b      	ldr	r3, [r7, #0]
+ 801e626:	68db      	ldr	r3, [r3, #12]
+ 801e628:	603b      	str	r3, [r7, #0]
+ 801e62a:	683b      	ldr	r3, [r7, #0]
+ 801e62c:	2b00      	cmp	r3, #0
+ 801e62e:	d1ea      	bne.n	801e606 <udp_new_port+0x2e>
+      }
+      goto again;
+    }
+  }
+  return udp_port;
+ 801e630:	4b03      	ldr	r3, [pc, #12]	; (801e640 <udp_new_port+0x68>)
+ 801e632:	881b      	ldrh	r3, [r3, #0]
+}
+ 801e634:	4618      	mov	r0, r3
+ 801e636:	370c      	adds	r7, #12
+ 801e638:	46bd      	mov	sp, r7
+ 801e63a:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 801e63e:	4770      	bx	lr
+ 801e640:	24000044 	.word	0x24000044
+ 801e644:	2401a4e0 	.word	0x2401a4e0
+
+0801e648 <udp_input_local_match>:
+ * @param broadcast 1 if his is an IPv4 broadcast (global or subnet-only), 0 otherwise (only used for IPv4)
+ * @return 1 on match, 0 otherwise
+ */
+static u8_t
+udp_input_local_match(struct udp_pcb *pcb, struct netif *inp, u8_t broadcast)
+{
+ 801e648:	b580      	push	{r7, lr}
+ 801e64a:	b084      	sub	sp, #16
+ 801e64c:	af00      	add	r7, sp, #0
+ 801e64e:	60f8      	str	r0, [r7, #12]
+ 801e650:	60b9      	str	r1, [r7, #8]
+ 801e652:	4613      	mov	r3, r2
+ 801e654:	71fb      	strb	r3, [r7, #7]
+  LWIP_UNUSED_ARG(inp);       /* in IPv6 only case */
+  LWIP_UNUSED_ARG(broadcast); /* in IPv6 only case */
+
+  LWIP_ASSERT("udp_input_local_match: invalid pcb", pcb != NULL);
+ 801e656:	68fb      	ldr	r3, [r7, #12]
+ 801e658:	2b00      	cmp	r3, #0
+ 801e65a:	d105      	bne.n	801e668 <udp_input_local_match+0x20>
+ 801e65c:	4b27      	ldr	r3, [pc, #156]	; (801e6fc <udp_input_local_match+0xb4>)
+ 801e65e:	2287      	movs	r2, #135	; 0x87
+ 801e660:	4927      	ldr	r1, [pc, #156]	; (801e700 <udp_input_local_match+0xb8>)
+ 801e662:	4828      	ldr	r0, [pc, #160]	; (801e704 <udp_input_local_match+0xbc>)
+ 801e664:	f003 f990 	bl	8021988 <iprintf>
+  LWIP_ASSERT("udp_input_local_match: invalid netif", inp != NULL);
+ 801e668:	68bb      	ldr	r3, [r7, #8]
+ 801e66a:	2b00      	cmp	r3, #0
+ 801e66c:	d105      	bne.n	801e67a <udp_input_local_match+0x32>
+ 801e66e:	4b23      	ldr	r3, [pc, #140]	; (801e6fc <udp_input_local_match+0xb4>)
+ 801e670:	2288      	movs	r2, #136	; 0x88
+ 801e672:	4925      	ldr	r1, [pc, #148]	; (801e708 <udp_input_local_match+0xc0>)
+ 801e674:	4823      	ldr	r0, [pc, #140]	; (801e704 <udp_input_local_match+0xbc>)
+ 801e676:	f003 f987 	bl	8021988 <iprintf>
+
+  /* check if PCB is bound to specific netif */
+  if ((pcb->netif_idx != NETIF_NO_INDEX) &&
+ 801e67a:	68fb      	ldr	r3, [r7, #12]
+ 801e67c:	7a1b      	ldrb	r3, [r3, #8]
+ 801e67e:	2b00      	cmp	r3, #0
+ 801e680:	d00b      	beq.n	801e69a <udp_input_local_match+0x52>
+      (pcb->netif_idx != netif_get_index(ip_data.current_input_netif))) {
+ 801e682:	68fb      	ldr	r3, [r7, #12]
+ 801e684:	7a1a      	ldrb	r2, [r3, #8]
+ 801e686:	4b21      	ldr	r3, [pc, #132]	; (801e70c <udp_input_local_match+0xc4>)
+ 801e688:	685b      	ldr	r3, [r3, #4]
+ 801e68a:	f893 3030 	ldrb.w	r3, [r3, #48]	; 0x30
+ 801e68e:	3301      	adds	r3, #1
+ 801e690:	b2db      	uxtb	r3, r3
+  if ((pcb->netif_idx != NETIF_NO_INDEX) &&
+ 801e692:	429a      	cmp	r2, r3
+ 801e694:	d001      	beq.n	801e69a <udp_input_local_match+0x52>
+    return 0;
+ 801e696:	2300      	movs	r3, #0
+ 801e698:	e02b      	b.n	801e6f2 <udp_input_local_match+0xaa>
+  /* Only need to check PCB if incoming IP version matches PCB IP version */
+  if (IP_ADDR_PCB_VERSION_MATCH_EXACT(pcb, ip_current_dest_addr())) {
+#if LWIP_IPV4
+    /* Special case: IPv4 broadcast: all or broadcasts in my subnet
+     * Note: broadcast variable can only be 1 if it is an IPv4 broadcast */
+    if (broadcast != 0) {
+ 801e69a:	79fb      	ldrb	r3, [r7, #7]
+ 801e69c:	2b00      	cmp	r3, #0
+ 801e69e:	d018      	beq.n	801e6d2 <udp_input_local_match+0x8a>
+#if IP_SOF_BROADCAST_RECV
+      if (ip_get_option(pcb, SOF_BROADCAST))
+#endif /* IP_SOF_BROADCAST_RECV */
+      {
+        if (ip4_addr_isany(ip_2_ip4(&pcb->local_ip)) ||
+ 801e6a0:	68fb      	ldr	r3, [r7, #12]
+ 801e6a2:	2b00      	cmp	r3, #0
+ 801e6a4:	d013      	beq.n	801e6ce <udp_input_local_match+0x86>
+ 801e6a6:	68fb      	ldr	r3, [r7, #12]
+ 801e6a8:	681b      	ldr	r3, [r3, #0]
+ 801e6aa:	2b00      	cmp	r3, #0
+ 801e6ac:	d00f      	beq.n	801e6ce <udp_input_local_match+0x86>
+            ((ip4_current_dest_addr()->addr == IPADDR_BROADCAST)) ||
+ 801e6ae:	4b17      	ldr	r3, [pc, #92]	; (801e70c <udp_input_local_match+0xc4>)
+ 801e6b0:	695b      	ldr	r3, [r3, #20]
+        if (ip4_addr_isany(ip_2_ip4(&pcb->local_ip)) ||
+ 801e6b2:	f1b3 3fff 	cmp.w	r3, #4294967295
+ 801e6b6:	d00a      	beq.n	801e6ce <udp_input_local_match+0x86>
+            ip4_addr_netcmp(ip_2_ip4(&pcb->local_ip), ip4_current_dest_addr(), netif_ip4_netmask(inp))) {
+ 801e6b8:	68fb      	ldr	r3, [r7, #12]
+ 801e6ba:	681a      	ldr	r2, [r3, #0]
+ 801e6bc:	4b13      	ldr	r3, [pc, #76]	; (801e70c <udp_input_local_match+0xc4>)
+ 801e6be:	695b      	ldr	r3, [r3, #20]
+ 801e6c0:	405a      	eors	r2, r3
+ 801e6c2:	68bb      	ldr	r3, [r7, #8]
+ 801e6c4:	3308      	adds	r3, #8
+ 801e6c6:	681b      	ldr	r3, [r3, #0]
+ 801e6c8:	4013      	ands	r3, r2
+            ((ip4_current_dest_addr()->addr == IPADDR_BROADCAST)) ||
+ 801e6ca:	2b00      	cmp	r3, #0
+ 801e6cc:	d110      	bne.n	801e6f0 <udp_input_local_match+0xa8>
+          return 1;
+ 801e6ce:	2301      	movs	r3, #1
+ 801e6d0:	e00f      	b.n	801e6f2 <udp_input_local_match+0xaa>
+        }
+      }
+    } else
+#endif /* LWIP_IPV4 */
+      /* Handle IPv4 and IPv6: all or exact match */
+      if (ip_addr_isany(&pcb->local_ip) || ip_addr_cmp(&pcb->local_ip, ip_current_dest_addr())) {
+ 801e6d2:	68fb      	ldr	r3, [r7, #12]
+ 801e6d4:	2b00      	cmp	r3, #0
+ 801e6d6:	d009      	beq.n	801e6ec <udp_input_local_match+0xa4>
+ 801e6d8:	68fb      	ldr	r3, [r7, #12]
+ 801e6da:	681b      	ldr	r3, [r3, #0]
+ 801e6dc:	2b00      	cmp	r3, #0
+ 801e6de:	d005      	beq.n	801e6ec <udp_input_local_match+0xa4>
+ 801e6e0:	68fb      	ldr	r3, [r7, #12]
+ 801e6e2:	681a      	ldr	r2, [r3, #0]
+ 801e6e4:	4b09      	ldr	r3, [pc, #36]	; (801e70c <udp_input_local_match+0xc4>)
+ 801e6e6:	695b      	ldr	r3, [r3, #20]
+ 801e6e8:	429a      	cmp	r2, r3
+ 801e6ea:	d101      	bne.n	801e6f0 <udp_input_local_match+0xa8>
+        return 1;
+ 801e6ec:	2301      	movs	r3, #1
+ 801e6ee:	e000      	b.n	801e6f2 <udp_input_local_match+0xaa>
+      }
+  }
+
+  return 0;
+ 801e6f0:	2300      	movs	r3, #0
+}
+ 801e6f2:	4618      	mov	r0, r3
+ 801e6f4:	3710      	adds	r7, #16
+ 801e6f6:	46bd      	mov	sp, r7
+ 801e6f8:	bd80      	pop	{r7, pc}
+ 801e6fa:	bf00      	nop
+ 801e6fc:	08026118 	.word	0x08026118
+ 801e700:	08026148 	.word	0x08026148
+ 801e704:	0802616c 	.word	0x0802616c
+ 801e708:	08026194 	.word	0x08026194
+ 801e70c:	24013980 	.word	0x24013980
+
+0801e710 <udp_input>:
+ * @param inp network interface on which the datagram was received.
+ *
+ */
+void
+udp_input(struct pbuf *p, struct netif *inp)
+{
+ 801e710:	b590      	push	{r4, r7, lr}
+ 801e712:	b08d      	sub	sp, #52	; 0x34
+ 801e714:	af02      	add	r7, sp, #8
+ 801e716:	6078      	str	r0, [r7, #4]
+ 801e718:	6039      	str	r1, [r7, #0]
+  struct udp_hdr *udphdr;
+  struct udp_pcb *pcb, *prev;
+  struct udp_pcb *uncon_pcb;
+  u16_t src, dest;
+  u8_t broadcast;
+  u8_t for_us = 0;
+ 801e71a:	2300      	movs	r3, #0
+ 801e71c:	77fb      	strb	r3, [r7, #31]
+
+  LWIP_UNUSED_ARG(inp);
+
+  LWIP_ASSERT_CORE_LOCKED();
+
+  LWIP_ASSERT("udp_input: invalid pbuf", p != NULL);
+ 801e71e:	687b      	ldr	r3, [r7, #4]
+ 801e720:	2b00      	cmp	r3, #0
+ 801e722:	d105      	bne.n	801e730 <udp_input+0x20>
+ 801e724:	4b7c      	ldr	r3, [pc, #496]	; (801e918 <udp_input+0x208>)
+ 801e726:	22cf      	movs	r2, #207	; 0xcf
+ 801e728:	497c      	ldr	r1, [pc, #496]	; (801e91c <udp_input+0x20c>)
+ 801e72a:	487d      	ldr	r0, [pc, #500]	; (801e920 <udp_input+0x210>)
+ 801e72c:	f003 f92c 	bl	8021988 <iprintf>
+  LWIP_ASSERT("udp_input: invalid netif", inp != NULL);
+ 801e730:	683b      	ldr	r3, [r7, #0]
+ 801e732:	2b00      	cmp	r3, #0
+ 801e734:	d105      	bne.n	801e742 <udp_input+0x32>
+ 801e736:	4b78      	ldr	r3, [pc, #480]	; (801e918 <udp_input+0x208>)
+ 801e738:	22d0      	movs	r2, #208	; 0xd0
+ 801e73a:	497a      	ldr	r1, [pc, #488]	; (801e924 <udp_input+0x214>)
+ 801e73c:	4878      	ldr	r0, [pc, #480]	; (801e920 <udp_input+0x210>)
+ 801e73e:	f003 f923 	bl	8021988 <iprintf>
+  PERF_START;
+
+  UDP_STATS_INC(udp.recv);
+
+  /* Check minimum length (UDP header) */
+  if (p->len < UDP_HLEN) {
+ 801e742:	687b      	ldr	r3, [r7, #4]
+ 801e744:	895b      	ldrh	r3, [r3, #10]
+ 801e746:	2b07      	cmp	r3, #7
+ 801e748:	d803      	bhi.n	801e752 <udp_input+0x42>
+    LWIP_DEBUGF(UDP_DEBUG,
+                ("udp_input: short UDP datagram (%"U16_F" bytes) discarded\n", p->tot_len));
+    UDP_STATS_INC(udp.lenerr);
+    UDP_STATS_INC(udp.drop);
+    MIB2_STATS_INC(mib2.udpinerrors);
+    pbuf_free(p);
+ 801e74a:	6878      	ldr	r0, [r7, #4]
+ 801e74c:	f7f9 f9d4 	bl	8017af8 <pbuf_free>
+    goto end;
+ 801e750:	e0de      	b.n	801e910 <udp_input+0x200>
+  }
+
+  udphdr = (struct udp_hdr *)p->payload;
+ 801e752:	687b      	ldr	r3, [r7, #4]
+ 801e754:	685b      	ldr	r3, [r3, #4]
+ 801e756:	617b      	str	r3, [r7, #20]
+
+  /* is broadcast packet ? */
+  broadcast = ip_addr_isbroadcast(ip_current_dest_addr(), ip_current_netif());
+ 801e758:	4b73      	ldr	r3, [pc, #460]	; (801e928 <udp_input+0x218>)
+ 801e75a:	695b      	ldr	r3, [r3, #20]
+ 801e75c:	4a72      	ldr	r2, [pc, #456]	; (801e928 <udp_input+0x218>)
+ 801e75e:	6812      	ldr	r2, [r2, #0]
+ 801e760:	4611      	mov	r1, r2
+ 801e762:	4618      	mov	r0, r3
+ 801e764:	f001 fe5c 	bl	8020420 <ip4_addr_isbroadcast_u32>
+ 801e768:	4603      	mov	r3, r0
+ 801e76a:	74fb      	strb	r3, [r7, #19]
+
+  LWIP_DEBUGF(UDP_DEBUG, ("udp_input: received datagram of length %"U16_F"\n", p->tot_len));
+
+  /* convert src and dest ports to host byte order */
+  src = lwip_ntohs(udphdr->src);
+ 801e76c:	697b      	ldr	r3, [r7, #20]
+ 801e76e:	881b      	ldrh	r3, [r3, #0]
+ 801e770:	b29b      	uxth	r3, r3
+ 801e772:	4618      	mov	r0, r3
+ 801e774:	f7f7 fbe4 	bl	8015f40 <lwip_htons>
+ 801e778:	4603      	mov	r3, r0
+ 801e77a:	823b      	strh	r3, [r7, #16]
+  dest = lwip_ntohs(udphdr->dest);
+ 801e77c:	697b      	ldr	r3, [r7, #20]
+ 801e77e:	885b      	ldrh	r3, [r3, #2]
+ 801e780:	b29b      	uxth	r3, r3
+ 801e782:	4618      	mov	r0, r3
+ 801e784:	f7f7 fbdc 	bl	8015f40 <lwip_htons>
+ 801e788:	4603      	mov	r3, r0
+ 801e78a:	81fb      	strh	r3, [r7, #14]
+  ip_addr_debug_print_val(UDP_DEBUG, *ip_current_dest_addr());
+  LWIP_DEBUGF(UDP_DEBUG, (", %"U16_F") <-- (", lwip_ntohs(udphdr->dest)));
+  ip_addr_debug_print_val(UDP_DEBUG, *ip_current_src_addr());
+  LWIP_DEBUGF(UDP_DEBUG, (", %"U16_F")\n", lwip_ntohs(udphdr->src)));
+
+  pcb = NULL;
+ 801e78c:	2300      	movs	r3, #0
+ 801e78e:	623b      	str	r3, [r7, #32]
+  prev = NULL;
+ 801e790:	2300      	movs	r3, #0
+ 801e792:	627b      	str	r3, [r7, #36]	; 0x24
+  uncon_pcb = NULL;
+ 801e794:	2300      	movs	r3, #0
+ 801e796:	61bb      	str	r3, [r7, #24]
+  /* Iterate through the UDP pcb list for a matching pcb.
+   * 'Perfect match' pcbs (connected to the remote port & ip address) are
+   * preferred. If no perfect match is found, the first unconnected pcb that
+   * matches the local port and ip address gets the datagram. */
+  for (pcb = udp_pcbs; pcb != NULL; pcb = pcb->next) {
+ 801e798:	4b64      	ldr	r3, [pc, #400]	; (801e92c <udp_input+0x21c>)
+ 801e79a:	681b      	ldr	r3, [r3, #0]
+ 801e79c:	623b      	str	r3, [r7, #32]
+ 801e79e:	e054      	b.n	801e84a <udp_input+0x13a>
+    LWIP_DEBUGF(UDP_DEBUG, (", %"U16_F") <-- (", pcb->local_port));
+    ip_addr_debug_print_val(UDP_DEBUG, pcb->remote_ip);
+    LWIP_DEBUGF(UDP_DEBUG, (", %"U16_F")\n", pcb->remote_port));
+
+    /* compare PCB local addr+port to UDP destination addr+port */
+    if ((pcb->local_port == dest) &&
+ 801e7a0:	6a3b      	ldr	r3, [r7, #32]
+ 801e7a2:	8a5b      	ldrh	r3, [r3, #18]
+ 801e7a4:	89fa      	ldrh	r2, [r7, #14]
+ 801e7a6:	429a      	cmp	r2, r3
+ 801e7a8:	d14a      	bne.n	801e840 <udp_input+0x130>
+        (udp_input_local_match(pcb, inp, broadcast) != 0)) {
+ 801e7aa:	7cfb      	ldrb	r3, [r7, #19]
+ 801e7ac:	461a      	mov	r2, r3
+ 801e7ae:	6839      	ldr	r1, [r7, #0]
+ 801e7b0:	6a38      	ldr	r0, [r7, #32]
+ 801e7b2:	f7ff ff49 	bl	801e648 <udp_input_local_match>
+ 801e7b6:	4603      	mov	r3, r0
+    if ((pcb->local_port == dest) &&
+ 801e7b8:	2b00      	cmp	r3, #0
+ 801e7ba:	d041      	beq.n	801e840 <udp_input+0x130>
+      if ((pcb->flags & UDP_FLAGS_CONNECTED) == 0) {
+ 801e7bc:	6a3b      	ldr	r3, [r7, #32]
+ 801e7be:	7c1b      	ldrb	r3, [r3, #16]
+ 801e7c0:	f003 0304 	and.w	r3, r3, #4
+ 801e7c4:	2b00      	cmp	r3, #0
+ 801e7c6:	d11d      	bne.n	801e804 <udp_input+0xf4>
+        if (uncon_pcb == NULL) {
+ 801e7c8:	69bb      	ldr	r3, [r7, #24]
+ 801e7ca:	2b00      	cmp	r3, #0
+ 801e7cc:	d102      	bne.n	801e7d4 <udp_input+0xc4>
+          /* the first unconnected matching PCB */
+          uncon_pcb = pcb;
+ 801e7ce:	6a3b      	ldr	r3, [r7, #32]
+ 801e7d0:	61bb      	str	r3, [r7, #24]
+ 801e7d2:	e017      	b.n	801e804 <udp_input+0xf4>
+#if LWIP_IPV4
+        } else if (broadcast && ip4_current_dest_addr()->addr == IPADDR_BROADCAST) {
+ 801e7d4:	7cfb      	ldrb	r3, [r7, #19]
+ 801e7d6:	2b00      	cmp	r3, #0
+ 801e7d8:	d014      	beq.n	801e804 <udp_input+0xf4>
+ 801e7da:	4b53      	ldr	r3, [pc, #332]	; (801e928 <udp_input+0x218>)
+ 801e7dc:	695b      	ldr	r3, [r3, #20]
+ 801e7de:	f1b3 3fff 	cmp.w	r3, #4294967295
+ 801e7e2:	d10f      	bne.n	801e804 <udp_input+0xf4>
+          /* global broadcast address (only valid for IPv4; match was checked before) */
+          if (!IP_IS_V4_VAL(uncon_pcb->local_ip) || !ip4_addr_cmp(ip_2_ip4(&uncon_pcb->local_ip), netif_ip4_addr(inp))) {
+ 801e7e4:	69bb      	ldr	r3, [r7, #24]
+ 801e7e6:	681a      	ldr	r2, [r3, #0]
+ 801e7e8:	683b      	ldr	r3, [r7, #0]
+ 801e7ea:	3304      	adds	r3, #4
+ 801e7ec:	681b      	ldr	r3, [r3, #0]
+ 801e7ee:	429a      	cmp	r2, r3
+ 801e7f0:	d008      	beq.n	801e804 <udp_input+0xf4>
+            /* uncon_pcb does not match the input netif, check this pcb */
+            if (IP_IS_V4_VAL(pcb->local_ip) && ip4_addr_cmp(ip_2_ip4(&pcb->local_ip), netif_ip4_addr(inp))) {
+ 801e7f2:	6a3b      	ldr	r3, [r7, #32]
+ 801e7f4:	681a      	ldr	r2, [r3, #0]
+ 801e7f6:	683b      	ldr	r3, [r7, #0]
+ 801e7f8:	3304      	adds	r3, #4
+ 801e7fa:	681b      	ldr	r3, [r3, #0]
+ 801e7fc:	429a      	cmp	r2, r3
+ 801e7fe:	d101      	bne.n	801e804 <udp_input+0xf4>
+              /* better match */
+              uncon_pcb = pcb;
+ 801e800:	6a3b      	ldr	r3, [r7, #32]
+ 801e802:	61bb      	str	r3, [r7, #24]
+        }
+#endif /* SO_REUSE */
+      }
+
+      /* compare PCB remote addr+port to UDP source addr+port */
+      if ((pcb->remote_port == src) &&
+ 801e804:	6a3b      	ldr	r3, [r7, #32]
+ 801e806:	8a9b      	ldrh	r3, [r3, #20]
+ 801e808:	8a3a      	ldrh	r2, [r7, #16]
+ 801e80a:	429a      	cmp	r2, r3
+ 801e80c:	d118      	bne.n	801e840 <udp_input+0x130>
+          (ip_addr_isany_val(pcb->remote_ip) ||
+ 801e80e:	6a3b      	ldr	r3, [r7, #32]
+ 801e810:	685b      	ldr	r3, [r3, #4]
+      if ((pcb->remote_port == src) &&
+ 801e812:	2b00      	cmp	r3, #0
+ 801e814:	d005      	beq.n	801e822 <udp_input+0x112>
+           ip_addr_cmp(&pcb->remote_ip, ip_current_src_addr()))) {
+ 801e816:	6a3b      	ldr	r3, [r7, #32]
+ 801e818:	685a      	ldr	r2, [r3, #4]
+ 801e81a:	4b43      	ldr	r3, [pc, #268]	; (801e928 <udp_input+0x218>)
+ 801e81c:	691b      	ldr	r3, [r3, #16]
+          (ip_addr_isany_val(pcb->remote_ip) ||
+ 801e81e:	429a      	cmp	r2, r3
+ 801e820:	d10e      	bne.n	801e840 <udp_input+0x130>
+        /* the first fully matching PCB */
+        if (prev != NULL) {
+ 801e822:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 801e824:	2b00      	cmp	r3, #0
+ 801e826:	d014      	beq.n	801e852 <udp_input+0x142>
+          /* move the pcb to the front of udp_pcbs so that is
+             found faster next time */
+          prev->next = pcb->next;
+ 801e828:	6a3b      	ldr	r3, [r7, #32]
+ 801e82a:	68da      	ldr	r2, [r3, #12]
+ 801e82c:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 801e82e:	60da      	str	r2, [r3, #12]
+          pcb->next = udp_pcbs;
+ 801e830:	4b3e      	ldr	r3, [pc, #248]	; (801e92c <udp_input+0x21c>)
+ 801e832:	681a      	ldr	r2, [r3, #0]
+ 801e834:	6a3b      	ldr	r3, [r7, #32]
+ 801e836:	60da      	str	r2, [r3, #12]
+          udp_pcbs = pcb;
+ 801e838:	4a3c      	ldr	r2, [pc, #240]	; (801e92c <udp_input+0x21c>)
+ 801e83a:	6a3b      	ldr	r3, [r7, #32]
+ 801e83c:	6013      	str	r3, [r2, #0]
+        } else {
+          UDP_STATS_INC(udp.cachehit);
+        }
+        break;
+ 801e83e:	e008      	b.n	801e852 <udp_input+0x142>
+      }
+    }
+
+    prev = pcb;
+ 801e840:	6a3b      	ldr	r3, [r7, #32]
+ 801e842:	627b      	str	r3, [r7, #36]	; 0x24
+  for (pcb = udp_pcbs; pcb != NULL; pcb = pcb->next) {
+ 801e844:	6a3b      	ldr	r3, [r7, #32]
+ 801e846:	68db      	ldr	r3, [r3, #12]
+ 801e848:	623b      	str	r3, [r7, #32]
+ 801e84a:	6a3b      	ldr	r3, [r7, #32]
+ 801e84c:	2b00      	cmp	r3, #0
+ 801e84e:	d1a7      	bne.n	801e7a0 <udp_input+0x90>
+ 801e850:	e000      	b.n	801e854 <udp_input+0x144>
+        break;
+ 801e852:	bf00      	nop
+  }
+  /* no fully matching pcb found? then look for an unconnected pcb */
+  if (pcb == NULL) {
+ 801e854:	6a3b      	ldr	r3, [r7, #32]
+ 801e856:	2b00      	cmp	r3, #0
+ 801e858:	d101      	bne.n	801e85e <udp_input+0x14e>
+    pcb = uncon_pcb;
+ 801e85a:	69bb      	ldr	r3, [r7, #24]
+ 801e85c:	623b      	str	r3, [r7, #32]
+  }
+
+  /* Check checksum if this is a match or if it was directed at us. */
+  if (pcb != NULL) {
+ 801e85e:	6a3b      	ldr	r3, [r7, #32]
+ 801e860:	2b00      	cmp	r3, #0
+ 801e862:	d002      	beq.n	801e86a <udp_input+0x15a>
+    for_us = 1;
+ 801e864:	2301      	movs	r3, #1
+ 801e866:	77fb      	strb	r3, [r7, #31]
+ 801e868:	e00a      	b.n	801e880 <udp_input+0x170>
+      for_us = netif_get_ip6_addr_match(inp, ip6_current_dest_addr()) >= 0;
+    }
+#endif /* LWIP_IPV6 */
+#if LWIP_IPV4
+    if (!ip_current_is_v6()) {
+      for_us = ip4_addr_cmp(netif_ip4_addr(inp), ip4_current_dest_addr());
+ 801e86a:	683b      	ldr	r3, [r7, #0]
+ 801e86c:	3304      	adds	r3, #4
+ 801e86e:	681a      	ldr	r2, [r3, #0]
+ 801e870:	4b2d      	ldr	r3, [pc, #180]	; (801e928 <udp_input+0x218>)
+ 801e872:	695b      	ldr	r3, [r3, #20]
+ 801e874:	429a      	cmp	r2, r3
+ 801e876:	bf0c      	ite	eq
+ 801e878:	2301      	moveq	r3, #1
+ 801e87a:	2300      	movne	r3, #0
+ 801e87c:	b2db      	uxtb	r3, r3
+ 801e87e:	77fb      	strb	r3, [r7, #31]
+    }
+#endif /* LWIP_IPV4 */
+  }
+
+  if (for_us) {
+ 801e880:	7ffb      	ldrb	r3, [r7, #31]
+ 801e882:	2b00      	cmp	r3, #0
+ 801e884:	d041      	beq.n	801e90a <udp_input+0x1fa>
+          }
+        }
+      }
+    }
+#endif /* CHECKSUM_CHECK_UDP */
+    if (pbuf_remove_header(p, UDP_HLEN)) {
+ 801e886:	2108      	movs	r1, #8
+ 801e888:	6878      	ldr	r0, [r7, #4]
+ 801e88a:	f7f9 f8af 	bl	80179ec <pbuf_remove_header>
+ 801e88e:	4603      	mov	r3, r0
+ 801e890:	2b00      	cmp	r3, #0
+ 801e892:	d00a      	beq.n	801e8aa <udp_input+0x19a>
+      /* Can we cope with this failing? Just assert for now */
+      LWIP_ASSERT("pbuf_remove_header failed\n", 0);
+ 801e894:	4b20      	ldr	r3, [pc, #128]	; (801e918 <udp_input+0x208>)
+ 801e896:	f44f 72b8 	mov.w	r2, #368	; 0x170
+ 801e89a:	4925      	ldr	r1, [pc, #148]	; (801e930 <udp_input+0x220>)
+ 801e89c:	4820      	ldr	r0, [pc, #128]	; (801e920 <udp_input+0x210>)
+ 801e89e:	f003 f873 	bl	8021988 <iprintf>
+      UDP_STATS_INC(udp.drop);
+      MIB2_STATS_INC(mib2.udpinerrors);
+      pbuf_free(p);
+ 801e8a2:	6878      	ldr	r0, [r7, #4]
+ 801e8a4:	f7f9 f928 	bl	8017af8 <pbuf_free>
+      goto end;
+ 801e8a8:	e032      	b.n	801e910 <udp_input+0x200>
+    }
+
+    if (pcb != NULL) {
+ 801e8aa:	6a3b      	ldr	r3, [r7, #32]
+ 801e8ac:	2b00      	cmp	r3, #0
+ 801e8ae:	d012      	beq.n	801e8d6 <udp_input+0x1c6>
+          }
+        }
+      }
+#endif /* SO_REUSE && SO_REUSE_RXTOALL */
+      /* callback */
+      if (pcb->recv != NULL) {
+ 801e8b0:	6a3b      	ldr	r3, [r7, #32]
+ 801e8b2:	699b      	ldr	r3, [r3, #24]
+ 801e8b4:	2b00      	cmp	r3, #0
+ 801e8b6:	d00a      	beq.n	801e8ce <udp_input+0x1be>
+        /* now the recv function is responsible for freeing p */
+        pcb->recv(pcb->recv_arg, pcb, p, ip_current_src_addr(), src);
+ 801e8b8:	6a3b      	ldr	r3, [r7, #32]
+ 801e8ba:	699c      	ldr	r4, [r3, #24]
+ 801e8bc:	6a3b      	ldr	r3, [r7, #32]
+ 801e8be:	69d8      	ldr	r0, [r3, #28]
+ 801e8c0:	8a3b      	ldrh	r3, [r7, #16]
+ 801e8c2:	9300      	str	r3, [sp, #0]
+ 801e8c4:	4b1b      	ldr	r3, [pc, #108]	; (801e934 <udp_input+0x224>)
+ 801e8c6:	687a      	ldr	r2, [r7, #4]
+ 801e8c8:	6a39      	ldr	r1, [r7, #32]
+ 801e8ca:	47a0      	blx	r4
+  } else {
+    pbuf_free(p);
+  }
+end:
+  PERF_STOP("udp_input");
+  return;
+ 801e8cc:	e021      	b.n	801e912 <udp_input+0x202>
+        pbuf_free(p);
+ 801e8ce:	6878      	ldr	r0, [r7, #4]
+ 801e8d0:	f7f9 f912 	bl	8017af8 <pbuf_free>
+        goto end;
+ 801e8d4:	e01c      	b.n	801e910 <udp_input+0x200>
+      if (!broadcast && !ip_addr_ismulticast(ip_current_dest_addr())) {
+ 801e8d6:	7cfb      	ldrb	r3, [r7, #19]
+ 801e8d8:	2b00      	cmp	r3, #0
+ 801e8da:	d112      	bne.n	801e902 <udp_input+0x1f2>
+ 801e8dc:	4b12      	ldr	r3, [pc, #72]	; (801e928 <udp_input+0x218>)
+ 801e8de:	695b      	ldr	r3, [r3, #20]
+ 801e8e0:	f003 03f0 	and.w	r3, r3, #240	; 0xf0
+ 801e8e4:	2be0      	cmp	r3, #224	; 0xe0
+ 801e8e6:	d00c      	beq.n	801e902 <udp_input+0x1f2>
+        pbuf_header_force(p, (s16_t)(ip_current_header_tot_len() + UDP_HLEN));
+ 801e8e8:	4b0f      	ldr	r3, [pc, #60]	; (801e928 <udp_input+0x218>)
+ 801e8ea:	899b      	ldrh	r3, [r3, #12]
+ 801e8ec:	3308      	adds	r3, #8
+ 801e8ee:	b29b      	uxth	r3, r3
+ 801e8f0:	b21b      	sxth	r3, r3
+ 801e8f2:	4619      	mov	r1, r3
+ 801e8f4:	6878      	ldr	r0, [r7, #4]
+ 801e8f6:	f7f9 f8ec 	bl	8017ad2 <pbuf_header_force>
+        icmp_port_unreach(ip_current_is_v6(), p);
+ 801e8fa:	2103      	movs	r1, #3
+ 801e8fc:	6878      	ldr	r0, [r7, #4]
+ 801e8fe:	f001 fa65 	bl	801fdcc <icmp_dest_unreach>
+      pbuf_free(p);
+ 801e902:	6878      	ldr	r0, [r7, #4]
+ 801e904:	f7f9 f8f8 	bl	8017af8 <pbuf_free>
+  return;
+ 801e908:	e003      	b.n	801e912 <udp_input+0x202>
+    pbuf_free(p);
+ 801e90a:	6878      	ldr	r0, [r7, #4]
+ 801e90c:	f7f9 f8f4 	bl	8017af8 <pbuf_free>
+  return;
+ 801e910:	bf00      	nop
+  UDP_STATS_INC(udp.drop);
+  MIB2_STATS_INC(mib2.udpinerrors);
+  pbuf_free(p);
+  PERF_STOP("udp_input");
+#endif /* CHECKSUM_CHECK_UDP */
+}
+ 801e912:	372c      	adds	r7, #44	; 0x2c
+ 801e914:	46bd      	mov	sp, r7
+ 801e916:	bd90      	pop	{r4, r7, pc}
+ 801e918:	08026118 	.word	0x08026118
+ 801e91c:	080261bc 	.word	0x080261bc
+ 801e920:	0802616c 	.word	0x0802616c
+ 801e924:	080261d4 	.word	0x080261d4
+ 801e928:	24013980 	.word	0x24013980
+ 801e92c:	2401a4e0 	.word	0x2401a4e0
+ 801e930:	080261f0 	.word	0x080261f0
+ 801e934:	24013990 	.word	0x24013990
+
+0801e938 <udp_bind>:
+ *
+ * @see udp_disconnect()
+ */
+err_t
+udp_bind(struct udp_pcb *pcb, const ip_addr_t *ipaddr, u16_t port)
+{
+ 801e938:	b580      	push	{r7, lr}
+ 801e93a:	b086      	sub	sp, #24
+ 801e93c:	af00      	add	r7, sp, #0
+ 801e93e:	60f8      	str	r0, [r7, #12]
+ 801e940:	60b9      	str	r1, [r7, #8]
+ 801e942:	4613      	mov	r3, r2
+ 801e944:	80fb      	strh	r3, [r7, #6]
+
+  LWIP_ASSERT_CORE_LOCKED();
+
+#if LWIP_IPV4
+  /* Don't propagate NULL pointer (IPv4 ANY) to subsequent functions */
+  if (ipaddr == NULL) {
+ 801e946:	68bb      	ldr	r3, [r7, #8]
+ 801e948:	2b00      	cmp	r3, #0
+ 801e94a:	d101      	bne.n	801e950 <udp_bind+0x18>
+    ipaddr = IP4_ADDR_ANY;
+ 801e94c:	4b39      	ldr	r3, [pc, #228]	; (801ea34 <udp_bind+0xfc>)
+ 801e94e:	60bb      	str	r3, [r7, #8]
+  }
+#else /* LWIP_IPV4 */
+  LWIP_ERROR("udp_bind: invalid ipaddr", ipaddr != NULL, return ERR_ARG);
+#endif /* LWIP_IPV4 */
+
+  LWIP_ERROR("udp_bind: invalid pcb", pcb != NULL, return ERR_ARG);
+ 801e950:	68fb      	ldr	r3, [r7, #12]
+ 801e952:	2b00      	cmp	r3, #0
+ 801e954:	d109      	bne.n	801e96a <udp_bind+0x32>
+ 801e956:	4b38      	ldr	r3, [pc, #224]	; (801ea38 <udp_bind+0x100>)
+ 801e958:	f240 32b7 	movw	r2, #951	; 0x3b7
+ 801e95c:	4937      	ldr	r1, [pc, #220]	; (801ea3c <udp_bind+0x104>)
+ 801e95e:	4838      	ldr	r0, [pc, #224]	; (801ea40 <udp_bind+0x108>)
+ 801e960:	f003 f812 	bl	8021988 <iprintf>
+ 801e964:	f06f 030f 	mvn.w	r3, #15
+ 801e968:	e060      	b.n	801ea2c <udp_bind+0xf4>
+
+  LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE, ("udp_bind(ipaddr = "));
+  ip_addr_debug_print(UDP_DEBUG | LWIP_DBG_TRACE, ipaddr);
+  LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE, (", port = %"U16_F")\n", port));
+
+  rebind = 0;
+ 801e96a:	2300      	movs	r3, #0
+ 801e96c:	74fb      	strb	r3, [r7, #19]
+  /* Check for double bind and rebind of the same pcb */
+  for (ipcb = udp_pcbs; ipcb != NULL; ipcb = ipcb->next) {
+ 801e96e:	4b35      	ldr	r3, [pc, #212]	; (801ea44 <udp_bind+0x10c>)
+ 801e970:	681b      	ldr	r3, [r3, #0]
+ 801e972:	617b      	str	r3, [r7, #20]
+ 801e974:	e009      	b.n	801e98a <udp_bind+0x52>
+    /* is this UDP PCB already on active list? */
+    if (pcb == ipcb) {
+ 801e976:	68fa      	ldr	r2, [r7, #12]
+ 801e978:	697b      	ldr	r3, [r7, #20]
+ 801e97a:	429a      	cmp	r2, r3
+ 801e97c:	d102      	bne.n	801e984 <udp_bind+0x4c>
+      rebind = 1;
+ 801e97e:	2301      	movs	r3, #1
+ 801e980:	74fb      	strb	r3, [r7, #19]
+      break;
+ 801e982:	e005      	b.n	801e990 <udp_bind+0x58>
+  for (ipcb = udp_pcbs; ipcb != NULL; ipcb = ipcb->next) {
+ 801e984:	697b      	ldr	r3, [r7, #20]
+ 801e986:	68db      	ldr	r3, [r3, #12]
+ 801e988:	617b      	str	r3, [r7, #20]
+ 801e98a:	697b      	ldr	r3, [r7, #20]
+ 801e98c:	2b00      	cmp	r3, #0
+ 801e98e:	d1f2      	bne.n	801e976 <udp_bind+0x3e>
+    ipaddr = &zoned_ipaddr;
+  }
+#endif /* LWIP_IPV6 && LWIP_IPV6_SCOPES */
+
+  /* no port specified? */
+  if (port == 0) {
+ 801e990:	88fb      	ldrh	r3, [r7, #6]
+ 801e992:	2b00      	cmp	r3, #0
+ 801e994:	d109      	bne.n	801e9aa <udp_bind+0x72>
+    port = udp_new_port();
+ 801e996:	f7ff fe1f 	bl	801e5d8 <udp_new_port>
+ 801e99a:	4603      	mov	r3, r0
+ 801e99c:	80fb      	strh	r3, [r7, #6]
+    if (port == 0) {
+ 801e99e:	88fb      	ldrh	r3, [r7, #6]
+ 801e9a0:	2b00      	cmp	r3, #0
+ 801e9a2:	d12c      	bne.n	801e9fe <udp_bind+0xc6>
+      /* no more ports available in local range */
+      LWIP_DEBUGF(UDP_DEBUG, ("udp_bind: out of free UDP ports\n"));
+      return ERR_USE;
+ 801e9a4:	f06f 0307 	mvn.w	r3, #7
+ 801e9a8:	e040      	b.n	801ea2c <udp_bind+0xf4>
+    }
+  } else {
+    for (ipcb = udp_pcbs; ipcb != NULL; ipcb = ipcb->next) {
+ 801e9aa:	4b26      	ldr	r3, [pc, #152]	; (801ea44 <udp_bind+0x10c>)
+ 801e9ac:	681b      	ldr	r3, [r3, #0]
+ 801e9ae:	617b      	str	r3, [r7, #20]
+ 801e9b0:	e022      	b.n	801e9f8 <udp_bind+0xc0>
+      if (pcb != ipcb) {
+ 801e9b2:	68fa      	ldr	r2, [r7, #12]
+ 801e9b4:	697b      	ldr	r3, [r7, #20]
+ 801e9b6:	429a      	cmp	r2, r3
+ 801e9b8:	d01b      	beq.n	801e9f2 <udp_bind+0xba>
+        if (!ip_get_option(pcb, SOF_REUSEADDR) ||
+            !ip_get_option(ipcb, SOF_REUSEADDR))
+#endif /* SO_REUSE */
+        {
+          /* port matches that of PCB in list and REUSEADDR not set -> reject */
+          if ((ipcb->local_port == port) &&
+ 801e9ba:	697b      	ldr	r3, [r7, #20]
+ 801e9bc:	8a5b      	ldrh	r3, [r3, #18]
+ 801e9be:	88fa      	ldrh	r2, [r7, #6]
+ 801e9c0:	429a      	cmp	r2, r3
+ 801e9c2:	d116      	bne.n	801e9f2 <udp_bind+0xba>
+              /* IP address matches or any IP used? */
+              (ip_addr_cmp(&ipcb->local_ip, ipaddr) || ip_addr_isany(ipaddr) ||
+ 801e9c4:	697b      	ldr	r3, [r7, #20]
+ 801e9c6:	681a      	ldr	r2, [r3, #0]
+ 801e9c8:	68bb      	ldr	r3, [r7, #8]
+ 801e9ca:	681b      	ldr	r3, [r3, #0]
+          if ((ipcb->local_port == port) &&
+ 801e9cc:	429a      	cmp	r2, r3
+ 801e9ce:	d00d      	beq.n	801e9ec <udp_bind+0xb4>
+              (ip_addr_cmp(&ipcb->local_ip, ipaddr) || ip_addr_isany(ipaddr) ||
+ 801e9d0:	68bb      	ldr	r3, [r7, #8]
+ 801e9d2:	2b00      	cmp	r3, #0
+ 801e9d4:	d00a      	beq.n	801e9ec <udp_bind+0xb4>
+ 801e9d6:	68bb      	ldr	r3, [r7, #8]
+ 801e9d8:	681b      	ldr	r3, [r3, #0]
+ 801e9da:	2b00      	cmp	r3, #0
+ 801e9dc:	d006      	beq.n	801e9ec <udp_bind+0xb4>
+              ip_addr_isany(&ipcb->local_ip))) {
+ 801e9de:	697b      	ldr	r3, [r7, #20]
+              (ip_addr_cmp(&ipcb->local_ip, ipaddr) || ip_addr_isany(ipaddr) ||
+ 801e9e0:	2b00      	cmp	r3, #0
+ 801e9e2:	d003      	beq.n	801e9ec <udp_bind+0xb4>
+              ip_addr_isany(&ipcb->local_ip))) {
+ 801e9e4:	697b      	ldr	r3, [r7, #20]
+ 801e9e6:	681b      	ldr	r3, [r3, #0]
+ 801e9e8:	2b00      	cmp	r3, #0
+ 801e9ea:	d102      	bne.n	801e9f2 <udp_bind+0xba>
+            /* other PCB already binds to this local IP and port */
+            LWIP_DEBUGF(UDP_DEBUG,
+                        ("udp_bind: local port %"U16_F" already bound by another pcb\n", port));
+            return ERR_USE;
+ 801e9ec:	f06f 0307 	mvn.w	r3, #7
+ 801e9f0:	e01c      	b.n	801ea2c <udp_bind+0xf4>
+    for (ipcb = udp_pcbs; ipcb != NULL; ipcb = ipcb->next) {
+ 801e9f2:	697b      	ldr	r3, [r7, #20]
+ 801e9f4:	68db      	ldr	r3, [r3, #12]
+ 801e9f6:	617b      	str	r3, [r7, #20]
+ 801e9f8:	697b      	ldr	r3, [r7, #20]
+ 801e9fa:	2b00      	cmp	r3, #0
+ 801e9fc:	d1d9      	bne.n	801e9b2 <udp_bind+0x7a>
+        }
+      }
+    }
+  }
+
+  ip_addr_set_ipaddr(&pcb->local_ip, ipaddr);
+ 801e9fe:	68bb      	ldr	r3, [r7, #8]
+ 801ea00:	2b00      	cmp	r3, #0
+ 801ea02:	d002      	beq.n	801ea0a <udp_bind+0xd2>
+ 801ea04:	68bb      	ldr	r3, [r7, #8]
+ 801ea06:	681b      	ldr	r3, [r3, #0]
+ 801ea08:	e000      	b.n	801ea0c <udp_bind+0xd4>
+ 801ea0a:	2300      	movs	r3, #0
+ 801ea0c:	68fa      	ldr	r2, [r7, #12]
+ 801ea0e:	6013      	str	r3, [r2, #0]
+
+  pcb->local_port = port;
+ 801ea10:	68fb      	ldr	r3, [r7, #12]
+ 801ea12:	88fa      	ldrh	r2, [r7, #6]
+ 801ea14:	825a      	strh	r2, [r3, #18]
+  mib2_udp_bind(pcb);
+  /* pcb not active yet? */
+  if (rebind == 0) {
+ 801ea16:	7cfb      	ldrb	r3, [r7, #19]
+ 801ea18:	2b00      	cmp	r3, #0
+ 801ea1a:	d106      	bne.n	801ea2a <udp_bind+0xf2>
+    /* place the PCB on the active list if not already there */
+    pcb->next = udp_pcbs;
+ 801ea1c:	4b09      	ldr	r3, [pc, #36]	; (801ea44 <udp_bind+0x10c>)
+ 801ea1e:	681a      	ldr	r2, [r3, #0]
+ 801ea20:	68fb      	ldr	r3, [r7, #12]
+ 801ea22:	60da      	str	r2, [r3, #12]
+    udp_pcbs = pcb;
+ 801ea24:	4a07      	ldr	r2, [pc, #28]	; (801ea44 <udp_bind+0x10c>)
+ 801ea26:	68fb      	ldr	r3, [r7, #12]
+ 801ea28:	6013      	str	r3, [r2, #0]
+  }
+  LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("udp_bind: bound to "));
+  ip_addr_debug_print_val(UDP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, pcb->local_ip);
+  LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, (", port %"U16_F")\n", pcb->local_port));
+  return ERR_OK;
+ 801ea2a:	2300      	movs	r3, #0
+}
+ 801ea2c:	4618      	mov	r0, r3
+ 801ea2e:	3718      	adds	r7, #24
+ 801ea30:	46bd      	mov	sp, r7
+ 801ea32:	bd80      	pop	{r7, pc}
+ 801ea34:	08026cec 	.word	0x08026cec
+ 801ea38:	08026118 	.word	0x08026118
+ 801ea3c:	080263e0 	.word	0x080263e0
+ 801ea40:	0802616c 	.word	0x0802616c
+ 801ea44:	2401a4e0 	.word	0x2401a4e0
+
+0801ea48 <udp_connect>:
+ *
+ * @see udp_disconnect()
+ */
+err_t
+udp_connect(struct udp_pcb *pcb, const ip_addr_t *ipaddr, u16_t port)
+{
+ 801ea48:	b580      	push	{r7, lr}
+ 801ea4a:	b086      	sub	sp, #24
+ 801ea4c:	af00      	add	r7, sp, #0
+ 801ea4e:	60f8      	str	r0, [r7, #12]
+ 801ea50:	60b9      	str	r1, [r7, #8]
+ 801ea52:	4613      	mov	r3, r2
+ 801ea54:	80fb      	strh	r3, [r7, #6]
+  struct udp_pcb *ipcb;
+
+  LWIP_ASSERT_CORE_LOCKED();
+
+  LWIP_ERROR("udp_connect: invalid pcb", pcb != NULL, return ERR_ARG);
+ 801ea56:	68fb      	ldr	r3, [r7, #12]
+ 801ea58:	2b00      	cmp	r3, #0
+ 801ea5a:	d109      	bne.n	801ea70 <udp_connect+0x28>
+ 801ea5c:	4b2c      	ldr	r3, [pc, #176]	; (801eb10 <udp_connect+0xc8>)
+ 801ea5e:	f240 4235 	movw	r2, #1077	; 0x435
+ 801ea62:	492c      	ldr	r1, [pc, #176]	; (801eb14 <udp_connect+0xcc>)
+ 801ea64:	482c      	ldr	r0, [pc, #176]	; (801eb18 <udp_connect+0xd0>)
+ 801ea66:	f002 ff8f 	bl	8021988 <iprintf>
+ 801ea6a:	f06f 030f 	mvn.w	r3, #15
+ 801ea6e:	e04b      	b.n	801eb08 <udp_connect+0xc0>
+  LWIP_ERROR("udp_connect: invalid ipaddr", ipaddr != NULL, return ERR_ARG);
+ 801ea70:	68bb      	ldr	r3, [r7, #8]
+ 801ea72:	2b00      	cmp	r3, #0
+ 801ea74:	d109      	bne.n	801ea8a <udp_connect+0x42>
+ 801ea76:	4b26      	ldr	r3, [pc, #152]	; (801eb10 <udp_connect+0xc8>)
+ 801ea78:	f240 4236 	movw	r2, #1078	; 0x436
+ 801ea7c:	4927      	ldr	r1, [pc, #156]	; (801eb1c <udp_connect+0xd4>)
+ 801ea7e:	4826      	ldr	r0, [pc, #152]	; (801eb18 <udp_connect+0xd0>)
+ 801ea80:	f002 ff82 	bl	8021988 <iprintf>
+ 801ea84:	f06f 030f 	mvn.w	r3, #15
+ 801ea88:	e03e      	b.n	801eb08 <udp_connect+0xc0>
+
+  if (pcb->local_port == 0) {
+ 801ea8a:	68fb      	ldr	r3, [r7, #12]
+ 801ea8c:	8a5b      	ldrh	r3, [r3, #18]
+ 801ea8e:	2b00      	cmp	r3, #0
+ 801ea90:	d10f      	bne.n	801eab2 <udp_connect+0x6a>
+    err_t err = udp_bind(pcb, &pcb->local_ip, pcb->local_port);
+ 801ea92:	68f9      	ldr	r1, [r7, #12]
+ 801ea94:	68fb      	ldr	r3, [r7, #12]
+ 801ea96:	8a5b      	ldrh	r3, [r3, #18]
+ 801ea98:	461a      	mov	r2, r3
+ 801ea9a:	68f8      	ldr	r0, [r7, #12]
+ 801ea9c:	f7ff ff4c 	bl	801e938 <udp_bind>
+ 801eaa0:	4603      	mov	r3, r0
+ 801eaa2:	75fb      	strb	r3, [r7, #23]
+    if (err != ERR_OK) {
+ 801eaa4:	f997 3017 	ldrsb.w	r3, [r7, #23]
+ 801eaa8:	2b00      	cmp	r3, #0
+ 801eaaa:	d002      	beq.n	801eab2 <udp_connect+0x6a>
+      return err;
+ 801eaac:	f997 3017 	ldrsb.w	r3, [r7, #23]
+ 801eab0:	e02a      	b.n	801eb08 <udp_connect+0xc0>
+    }
+  }
+
+  ip_addr_set_ipaddr(&pcb->remote_ip, ipaddr);
+ 801eab2:	68bb      	ldr	r3, [r7, #8]
+ 801eab4:	2b00      	cmp	r3, #0
+ 801eab6:	d002      	beq.n	801eabe <udp_connect+0x76>
+ 801eab8:	68bb      	ldr	r3, [r7, #8]
+ 801eaba:	681b      	ldr	r3, [r3, #0]
+ 801eabc:	e000      	b.n	801eac0 <udp_connect+0x78>
+ 801eabe:	2300      	movs	r3, #0
+ 801eac0:	68fa      	ldr	r2, [r7, #12]
+ 801eac2:	6053      	str	r3, [r2, #4]
+      ip6_addr_lacks_zone(ip_2_ip6(&pcb->remote_ip), IP6_UNKNOWN)) {
+    ip6_addr_select_zone(ip_2_ip6(&pcb->remote_ip), ip_2_ip6(&pcb->local_ip));
+  }
+#endif /* LWIP_IPV6 && LWIP_IPV6_SCOPES */
+
+  pcb->remote_port = port;
+ 801eac4:	68fb      	ldr	r3, [r7, #12]
+ 801eac6:	88fa      	ldrh	r2, [r7, #6]
+ 801eac8:	829a      	strh	r2, [r3, #20]
+  pcb->flags |= UDP_FLAGS_CONNECTED;
+ 801eaca:	68fb      	ldr	r3, [r7, #12]
+ 801eacc:	7c1b      	ldrb	r3, [r3, #16]
+ 801eace:	f043 0304 	orr.w	r3, r3, #4
+ 801ead2:	b2da      	uxtb	r2, r3
+ 801ead4:	68fb      	ldr	r3, [r7, #12]
+ 801ead6:	741a      	strb	r2, [r3, #16]
+  ip_addr_debug_print_val(UDP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE,
+                          pcb->remote_ip);
+  LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, (", port %"U16_F")\n", pcb->remote_port));
+
+  /* Insert UDP PCB into the list of active UDP PCBs. */
+  for (ipcb = udp_pcbs; ipcb != NULL; ipcb = ipcb->next) {
+ 801ead8:	4b11      	ldr	r3, [pc, #68]	; (801eb20 <udp_connect+0xd8>)
+ 801eada:	681b      	ldr	r3, [r3, #0]
+ 801eadc:	613b      	str	r3, [r7, #16]
+ 801eade:	e008      	b.n	801eaf2 <udp_connect+0xaa>
+    if (pcb == ipcb) {
+ 801eae0:	68fa      	ldr	r2, [r7, #12]
+ 801eae2:	693b      	ldr	r3, [r7, #16]
+ 801eae4:	429a      	cmp	r2, r3
+ 801eae6:	d101      	bne.n	801eaec <udp_connect+0xa4>
+      /* already on the list, just return */
+      return ERR_OK;
+ 801eae8:	2300      	movs	r3, #0
+ 801eaea:	e00d      	b.n	801eb08 <udp_connect+0xc0>
+  for (ipcb = udp_pcbs; ipcb != NULL; ipcb = ipcb->next) {
+ 801eaec:	693b      	ldr	r3, [r7, #16]
+ 801eaee:	68db      	ldr	r3, [r3, #12]
+ 801eaf0:	613b      	str	r3, [r7, #16]
+ 801eaf2:	693b      	ldr	r3, [r7, #16]
+ 801eaf4:	2b00      	cmp	r3, #0
+ 801eaf6:	d1f3      	bne.n	801eae0 <udp_connect+0x98>
+    }
+  }
+  /* PCB not yet on the list, add PCB now */
+  pcb->next = udp_pcbs;
+ 801eaf8:	4b09      	ldr	r3, [pc, #36]	; (801eb20 <udp_connect+0xd8>)
+ 801eafa:	681a      	ldr	r2, [r3, #0]
+ 801eafc:	68fb      	ldr	r3, [r7, #12]
+ 801eafe:	60da      	str	r2, [r3, #12]
+  udp_pcbs = pcb;
+ 801eb00:	4a07      	ldr	r2, [pc, #28]	; (801eb20 <udp_connect+0xd8>)
+ 801eb02:	68fb      	ldr	r3, [r7, #12]
+ 801eb04:	6013      	str	r3, [r2, #0]
+  return ERR_OK;
+ 801eb06:	2300      	movs	r3, #0
+}
+ 801eb08:	4618      	mov	r0, r3
+ 801eb0a:	3718      	adds	r7, #24
+ 801eb0c:	46bd      	mov	sp, r7
+ 801eb0e:	bd80      	pop	{r7, pc}
+ 801eb10:	08026118 	.word	0x08026118
+ 801eb14:	080263f8 	.word	0x080263f8
+ 801eb18:	0802616c 	.word	0x0802616c
+ 801eb1c:	08026414 	.word	0x08026414
+ 801eb20:	2401a4e0 	.word	0x2401a4e0
+
+0801eb24 <udp_recv>:
+ * @param recv function pointer of the callback function
+ * @param recv_arg additional argument to pass to the callback function
+ */
+void
+udp_recv(struct udp_pcb *pcb, udp_recv_fn recv, void *recv_arg)
+{
+ 801eb24:	b580      	push	{r7, lr}
+ 801eb26:	b084      	sub	sp, #16
+ 801eb28:	af00      	add	r7, sp, #0
+ 801eb2a:	60f8      	str	r0, [r7, #12]
+ 801eb2c:	60b9      	str	r1, [r7, #8]
+ 801eb2e:	607a      	str	r2, [r7, #4]
+  LWIP_ASSERT_CORE_LOCKED();
+
+  LWIP_ERROR("udp_recv: invalid pcb", pcb != NULL, return);
+ 801eb30:	68fb      	ldr	r3, [r7, #12]
+ 801eb32:	2b00      	cmp	r3, #0
+ 801eb34:	d107      	bne.n	801eb46 <udp_recv+0x22>
+ 801eb36:	4b08      	ldr	r3, [pc, #32]	; (801eb58 <udp_recv+0x34>)
+ 801eb38:	f240 428a 	movw	r2, #1162	; 0x48a
+ 801eb3c:	4907      	ldr	r1, [pc, #28]	; (801eb5c <udp_recv+0x38>)
+ 801eb3e:	4808      	ldr	r0, [pc, #32]	; (801eb60 <udp_recv+0x3c>)
+ 801eb40:	f002 ff22 	bl	8021988 <iprintf>
+ 801eb44:	e005      	b.n	801eb52 <udp_recv+0x2e>
+
+  /* remember recv() callback and user data */
+  pcb->recv = recv;
+ 801eb46:	68fb      	ldr	r3, [r7, #12]
+ 801eb48:	68ba      	ldr	r2, [r7, #8]
+ 801eb4a:	619a      	str	r2, [r3, #24]
+  pcb->recv_arg = recv_arg;
+ 801eb4c:	68fb      	ldr	r3, [r7, #12]
+ 801eb4e:	687a      	ldr	r2, [r7, #4]
+ 801eb50:	61da      	str	r2, [r3, #28]
+}
+ 801eb52:	3710      	adds	r7, #16
+ 801eb54:	46bd      	mov	sp, r7
+ 801eb56:	bd80      	pop	{r7, pc}
+ 801eb58:	08026118 	.word	0x08026118
+ 801eb5c:	0802644c 	.word	0x0802644c
+ 801eb60:	0802616c 	.word	0x0802616c
+
+0801eb64 <udp_remove>:
+ *
+ * @see udp_new()
+ */
+void
+udp_remove(struct udp_pcb *pcb)
+{
+ 801eb64:	b580      	push	{r7, lr}
+ 801eb66:	b084      	sub	sp, #16
+ 801eb68:	af00      	add	r7, sp, #0
+ 801eb6a:	6078      	str	r0, [r7, #4]
+  struct udp_pcb *pcb2;
+
+  LWIP_ASSERT_CORE_LOCKED();
+
+  LWIP_ERROR("udp_remove: invalid pcb", pcb != NULL, return);
+ 801eb6c:	687b      	ldr	r3, [r7, #4]
+ 801eb6e:	2b00      	cmp	r3, #0
+ 801eb70:	d107      	bne.n	801eb82 <udp_remove+0x1e>
+ 801eb72:	4b19      	ldr	r3, [pc, #100]	; (801ebd8 <udp_remove+0x74>)
+ 801eb74:	f240 42a1 	movw	r2, #1185	; 0x4a1
+ 801eb78:	4918      	ldr	r1, [pc, #96]	; (801ebdc <udp_remove+0x78>)
+ 801eb7a:	4819      	ldr	r0, [pc, #100]	; (801ebe0 <udp_remove+0x7c>)
+ 801eb7c:	f002 ff04 	bl	8021988 <iprintf>
+ 801eb80:	e026      	b.n	801ebd0 <udp_remove+0x6c>
+
+  mib2_udp_unbind(pcb);
+  /* pcb to be removed is first in list? */
+  if (udp_pcbs == pcb) {
+ 801eb82:	4b18      	ldr	r3, [pc, #96]	; (801ebe4 <udp_remove+0x80>)
+ 801eb84:	681b      	ldr	r3, [r3, #0]
+ 801eb86:	687a      	ldr	r2, [r7, #4]
+ 801eb88:	429a      	cmp	r2, r3
+ 801eb8a:	d105      	bne.n	801eb98 <udp_remove+0x34>
+    /* make list start at 2nd pcb */
+    udp_pcbs = udp_pcbs->next;
+ 801eb8c:	4b15      	ldr	r3, [pc, #84]	; (801ebe4 <udp_remove+0x80>)
+ 801eb8e:	681b      	ldr	r3, [r3, #0]
+ 801eb90:	68db      	ldr	r3, [r3, #12]
+ 801eb92:	4a14      	ldr	r2, [pc, #80]	; (801ebe4 <udp_remove+0x80>)
+ 801eb94:	6013      	str	r3, [r2, #0]
+ 801eb96:	e017      	b.n	801ebc8 <udp_remove+0x64>
+    /* pcb not 1st in list */
+  } else {
+    for (pcb2 = udp_pcbs; pcb2 != NULL; pcb2 = pcb2->next) {
+ 801eb98:	4b12      	ldr	r3, [pc, #72]	; (801ebe4 <udp_remove+0x80>)
+ 801eb9a:	681b      	ldr	r3, [r3, #0]
+ 801eb9c:	60fb      	str	r3, [r7, #12]
+ 801eb9e:	e010      	b.n	801ebc2 <udp_remove+0x5e>
+      /* find pcb in udp_pcbs list */
+      if (pcb2->next != NULL && pcb2->next == pcb) {
+ 801eba0:	68fb      	ldr	r3, [r7, #12]
+ 801eba2:	68db      	ldr	r3, [r3, #12]
+ 801eba4:	2b00      	cmp	r3, #0
+ 801eba6:	d009      	beq.n	801ebbc <udp_remove+0x58>
+ 801eba8:	68fb      	ldr	r3, [r7, #12]
+ 801ebaa:	68db      	ldr	r3, [r3, #12]
+ 801ebac:	687a      	ldr	r2, [r7, #4]
+ 801ebae:	429a      	cmp	r2, r3
+ 801ebb0:	d104      	bne.n	801ebbc <udp_remove+0x58>
+        /* remove pcb from list */
+        pcb2->next = pcb->next;
+ 801ebb2:	687b      	ldr	r3, [r7, #4]
+ 801ebb4:	68da      	ldr	r2, [r3, #12]
+ 801ebb6:	68fb      	ldr	r3, [r7, #12]
+ 801ebb8:	60da      	str	r2, [r3, #12]
+        break;
+ 801ebba:	e005      	b.n	801ebc8 <udp_remove+0x64>
+    for (pcb2 = udp_pcbs; pcb2 != NULL; pcb2 = pcb2->next) {
+ 801ebbc:	68fb      	ldr	r3, [r7, #12]
+ 801ebbe:	68db      	ldr	r3, [r3, #12]
+ 801ebc0:	60fb      	str	r3, [r7, #12]
+ 801ebc2:	68fb      	ldr	r3, [r7, #12]
+ 801ebc4:	2b00      	cmp	r3, #0
+ 801ebc6:	d1eb      	bne.n	801eba0 <udp_remove+0x3c>
+      }
+    }
+  }
+  memp_free(MEMP_UDP_PCB, pcb);
+ 801ebc8:	6879      	ldr	r1, [r7, #4]
+ 801ebca:	2000      	movs	r0, #0
+ 801ebcc:	f7f7 fff6 	bl	8016bbc <memp_free>
+}
+ 801ebd0:	3710      	adds	r7, #16
+ 801ebd2:	46bd      	mov	sp, r7
+ 801ebd4:	bd80      	pop	{r7, pc}
+ 801ebd6:	bf00      	nop
+ 801ebd8:	08026118 	.word	0x08026118
+ 801ebdc:	08026464 	.word	0x08026464
+ 801ebe0:	0802616c 	.word	0x0802616c
+ 801ebe4:	2401a4e0 	.word	0x2401a4e0
+
+0801ebe8 <udp_new>:
+ *
+ * @see udp_remove()
+ */
+struct udp_pcb *
+udp_new(void)
+{
+ 801ebe8:	b580      	push	{r7, lr}
+ 801ebea:	b082      	sub	sp, #8
+ 801ebec:	af00      	add	r7, sp, #0
+  struct udp_pcb *pcb;
+
+  LWIP_ASSERT_CORE_LOCKED();
+
+  pcb = (struct udp_pcb *)memp_malloc(MEMP_UDP_PCB);
+ 801ebee:	2000      	movs	r0, #0
+ 801ebf0:	f7f7 ff6e 	bl	8016ad0 <memp_malloc>
+ 801ebf4:	6078      	str	r0, [r7, #4]
+  /* could allocate UDP PCB? */
+  if (pcb != NULL) {
+ 801ebf6:	687b      	ldr	r3, [r7, #4]
+ 801ebf8:	2b00      	cmp	r3, #0
+ 801ebfa:	d007      	beq.n	801ec0c <udp_new+0x24>
+    /* UDP Lite: by initializing to all zeroes, chksum_len is set to 0
+     * which means checksum is generated over the whole datagram per default
+     * (recommended as default by RFC 3828). */
+    /* initialize PCB to all zeroes */
+    memset(pcb, 0, sizeof(struct udp_pcb));
+ 801ebfc:	2220      	movs	r2, #32
+ 801ebfe:	2100      	movs	r1, #0
+ 801ec00:	6878      	ldr	r0, [r7, #4]
+ 801ec02:	f003 f86d 	bl	8021ce0 <memset>
+    pcb->ttl = UDP_TTL;
+ 801ec06:	687b      	ldr	r3, [r7, #4]
+ 801ec08:	22ff      	movs	r2, #255	; 0xff
+ 801ec0a:	72da      	strb	r2, [r3, #11]
+#if LWIP_MULTICAST_TX_OPTIONS
+    udp_set_multicast_ttl(pcb, UDP_TTL);
+#endif /* LWIP_MULTICAST_TX_OPTIONS */
+  }
+  return pcb;
+ 801ec0c:	687b      	ldr	r3, [r7, #4]
+}
+ 801ec0e:	4618      	mov	r0, r3
+ 801ec10:	3708      	adds	r7, #8
+ 801ec12:	46bd      	mov	sp, r7
+ 801ec14:	bd80      	pop	{r7, pc}
+
+0801ec16 <udp_new_ip_type>:
+ *
+ * @see udp_remove()
+ */
+struct udp_pcb *
+udp_new_ip_type(u8_t type)
+{
+ 801ec16:	b580      	push	{r7, lr}
+ 801ec18:	b084      	sub	sp, #16
+ 801ec1a:	af00      	add	r7, sp, #0
+ 801ec1c:	4603      	mov	r3, r0
+ 801ec1e:	71fb      	strb	r3, [r7, #7]
+  struct udp_pcb *pcb;
+
+  LWIP_ASSERT_CORE_LOCKED();
+
+  pcb = udp_new();
+ 801ec20:	f7ff ffe2 	bl	801ebe8 <udp_new>
+ 801ec24:	60f8      	str	r0, [r7, #12]
+    IP_SET_TYPE_VAL(pcb->remote_ip, type);
+  }
+#else
+  LWIP_UNUSED_ARG(type);
+#endif /* LWIP_IPV4 && LWIP_IPV6 */
+  return pcb;
+ 801ec26:	68fb      	ldr	r3, [r7, #12]
+}
+ 801ec28:	4618      	mov	r0, r3
+ 801ec2a:	3710      	adds	r7, #16
+ 801ec2c:	46bd      	mov	sp, r7
+ 801ec2e:	bd80      	pop	{r7, pc}
+
+0801ec30 <udp_netif_ip_addr_changed>:
+ *
+ * @param old_addr IP address of the netif before change
+ * @param new_addr IP address of the netif after change
+ */
+void udp_netif_ip_addr_changed(const ip_addr_t *old_addr, const ip_addr_t *new_addr)
+{
+ 801ec30:	b480      	push	{r7}
+ 801ec32:	b085      	sub	sp, #20
+ 801ec34:	af00      	add	r7, sp, #0
+ 801ec36:	6078      	str	r0, [r7, #4]
+ 801ec38:	6039      	str	r1, [r7, #0]
+  struct udp_pcb *upcb;
+
+  if (!ip_addr_isany(old_addr) && !ip_addr_isany(new_addr)) {
+ 801ec3a:	687b      	ldr	r3, [r7, #4]
+ 801ec3c:	2b00      	cmp	r3, #0
+ 801ec3e:	d01e      	beq.n	801ec7e <udp_netif_ip_addr_changed+0x4e>
+ 801ec40:	687b      	ldr	r3, [r7, #4]
+ 801ec42:	681b      	ldr	r3, [r3, #0]
+ 801ec44:	2b00      	cmp	r3, #0
+ 801ec46:	d01a      	beq.n	801ec7e <udp_netif_ip_addr_changed+0x4e>
+ 801ec48:	683b      	ldr	r3, [r7, #0]
+ 801ec4a:	2b00      	cmp	r3, #0
+ 801ec4c:	d017      	beq.n	801ec7e <udp_netif_ip_addr_changed+0x4e>
+ 801ec4e:	683b      	ldr	r3, [r7, #0]
+ 801ec50:	681b      	ldr	r3, [r3, #0]
+ 801ec52:	2b00      	cmp	r3, #0
+ 801ec54:	d013      	beq.n	801ec7e <udp_netif_ip_addr_changed+0x4e>
+    for (upcb = udp_pcbs; upcb != NULL; upcb = upcb->next) {
+ 801ec56:	4b0d      	ldr	r3, [pc, #52]	; (801ec8c <udp_netif_ip_addr_changed+0x5c>)
+ 801ec58:	681b      	ldr	r3, [r3, #0]
+ 801ec5a:	60fb      	str	r3, [r7, #12]
+ 801ec5c:	e00c      	b.n	801ec78 <udp_netif_ip_addr_changed+0x48>
+      /* PCB bound to current local interface address? */
+      if (ip_addr_cmp(&upcb->local_ip, old_addr)) {
+ 801ec5e:	68fb      	ldr	r3, [r7, #12]
+ 801ec60:	681a      	ldr	r2, [r3, #0]
+ 801ec62:	687b      	ldr	r3, [r7, #4]
+ 801ec64:	681b      	ldr	r3, [r3, #0]
+ 801ec66:	429a      	cmp	r2, r3
+ 801ec68:	d103      	bne.n	801ec72 <udp_netif_ip_addr_changed+0x42>
+        /* The PCB is bound to the old ipaddr and
+         * is set to bound to the new one instead */
+        ip_addr_copy(upcb->local_ip, *new_addr);
+ 801ec6a:	683b      	ldr	r3, [r7, #0]
+ 801ec6c:	681a      	ldr	r2, [r3, #0]
+ 801ec6e:	68fb      	ldr	r3, [r7, #12]
+ 801ec70:	601a      	str	r2, [r3, #0]
+    for (upcb = udp_pcbs; upcb != NULL; upcb = upcb->next) {
+ 801ec72:	68fb      	ldr	r3, [r7, #12]
+ 801ec74:	68db      	ldr	r3, [r3, #12]
+ 801ec76:	60fb      	str	r3, [r7, #12]
+ 801ec78:	68fb      	ldr	r3, [r7, #12]
+ 801ec7a:	2b00      	cmp	r3, #0
+ 801ec7c:	d1ef      	bne.n	801ec5e <udp_netif_ip_addr_changed+0x2e>
+      }
+    }
+  }
+}
+ 801ec7e:	bf00      	nop
+ 801ec80:	3714      	adds	r7, #20
+ 801ec82:	46bd      	mov	sp, r7
+ 801ec84:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 801ec88:	4770      	bx	lr
+ 801ec8a:	bf00      	nop
+ 801ec8c:	2401a4e0 	.word	0x2401a4e0
+
+0801ec90 <etharp_free_entry>:
+#endif /* ARP_QUEUEING */
+
+/** Clean up ARP table entries */
+static void
+etharp_free_entry(int i)
+{
+ 801ec90:	b580      	push	{r7, lr}
+ 801ec92:	b082      	sub	sp, #8
+ 801ec94:	af00      	add	r7, sp, #0
+ 801ec96:	6078      	str	r0, [r7, #4]
+  /* remove from SNMP ARP index tree */
+  mib2_remove_arp_entry(arp_table[i].netif, &arp_table[i].ipaddr);
+  /* and empty packet queue */
+  if (arp_table[i].q != NULL) {
+ 801ec98:	492b      	ldr	r1, [pc, #172]	; (801ed48 <etharp_free_entry+0xb8>)
+ 801ec9a:	687a      	ldr	r2, [r7, #4]
+ 801ec9c:	4613      	mov	r3, r2
+ 801ec9e:	005b      	lsls	r3, r3, #1
+ 801eca0:	4413      	add	r3, r2
+ 801eca2:	00db      	lsls	r3, r3, #3
+ 801eca4:	440b      	add	r3, r1
+ 801eca6:	681b      	ldr	r3, [r3, #0]
+ 801eca8:	2b00      	cmp	r3, #0
+ 801ecaa:	d013      	beq.n	801ecd4 <etharp_free_entry+0x44>
+    /* remove all queued packets */
+    LWIP_DEBUGF(ETHARP_DEBUG, ("etharp_free_entry: freeing entry %"U16_F", packet queue %p.\n", (u16_t)i, (void *)(arp_table[i].q)));
+    free_etharp_q(arp_table[i].q);
+ 801ecac:	4926      	ldr	r1, [pc, #152]	; (801ed48 <etharp_free_entry+0xb8>)
+ 801ecae:	687a      	ldr	r2, [r7, #4]
+ 801ecb0:	4613      	mov	r3, r2
+ 801ecb2:	005b      	lsls	r3, r3, #1
+ 801ecb4:	4413      	add	r3, r2
+ 801ecb6:	00db      	lsls	r3, r3, #3
+ 801ecb8:	440b      	add	r3, r1
+ 801ecba:	681b      	ldr	r3, [r3, #0]
+ 801ecbc:	4618      	mov	r0, r3
+ 801ecbe:	f7f8 ff1b 	bl	8017af8 <pbuf_free>
+    arp_table[i].q = NULL;
+ 801ecc2:	4921      	ldr	r1, [pc, #132]	; (801ed48 <etharp_free_entry+0xb8>)
+ 801ecc4:	687a      	ldr	r2, [r7, #4]
+ 801ecc6:	4613      	mov	r3, r2
+ 801ecc8:	005b      	lsls	r3, r3, #1
+ 801ecca:	4413      	add	r3, r2
+ 801eccc:	00db      	lsls	r3, r3, #3
+ 801ecce:	440b      	add	r3, r1
+ 801ecd0:	2200      	movs	r2, #0
+ 801ecd2:	601a      	str	r2, [r3, #0]
+  }
+  /* recycle entry for re-use */
+  arp_table[i].state = ETHARP_STATE_EMPTY;
+ 801ecd4:	491c      	ldr	r1, [pc, #112]	; (801ed48 <etharp_free_entry+0xb8>)
+ 801ecd6:	687a      	ldr	r2, [r7, #4]
+ 801ecd8:	4613      	mov	r3, r2
+ 801ecda:	005b      	lsls	r3, r3, #1
+ 801ecdc:	4413      	add	r3, r2
+ 801ecde:	00db      	lsls	r3, r3, #3
+ 801ece0:	440b      	add	r3, r1
+ 801ece2:	3314      	adds	r3, #20
+ 801ece4:	2200      	movs	r2, #0
+ 801ece6:	701a      	strb	r2, [r3, #0]
+#ifdef LWIP_DEBUG
+  /* for debugging, clean out the complete entry */
+  arp_table[i].ctime = 0;
+ 801ece8:	4917      	ldr	r1, [pc, #92]	; (801ed48 <etharp_free_entry+0xb8>)
+ 801ecea:	687a      	ldr	r2, [r7, #4]
+ 801ecec:	4613      	mov	r3, r2
+ 801ecee:	005b      	lsls	r3, r3, #1
+ 801ecf0:	4413      	add	r3, r2
+ 801ecf2:	00db      	lsls	r3, r3, #3
+ 801ecf4:	440b      	add	r3, r1
+ 801ecf6:	3312      	adds	r3, #18
+ 801ecf8:	2200      	movs	r2, #0
+ 801ecfa:	801a      	strh	r2, [r3, #0]
+  arp_table[i].netif = NULL;
+ 801ecfc:	4912      	ldr	r1, [pc, #72]	; (801ed48 <etharp_free_entry+0xb8>)
+ 801ecfe:	687a      	ldr	r2, [r7, #4]
+ 801ed00:	4613      	mov	r3, r2
+ 801ed02:	005b      	lsls	r3, r3, #1
+ 801ed04:	4413      	add	r3, r2
+ 801ed06:	00db      	lsls	r3, r3, #3
+ 801ed08:	440b      	add	r3, r1
+ 801ed0a:	3308      	adds	r3, #8
+ 801ed0c:	2200      	movs	r2, #0
+ 801ed0e:	601a      	str	r2, [r3, #0]
+  ip4_addr_set_zero(&arp_table[i].ipaddr);
+ 801ed10:	490d      	ldr	r1, [pc, #52]	; (801ed48 <etharp_free_entry+0xb8>)
+ 801ed12:	687a      	ldr	r2, [r7, #4]
+ 801ed14:	4613      	mov	r3, r2
+ 801ed16:	005b      	lsls	r3, r3, #1
+ 801ed18:	4413      	add	r3, r2
+ 801ed1a:	00db      	lsls	r3, r3, #3
+ 801ed1c:	440b      	add	r3, r1
+ 801ed1e:	3304      	adds	r3, #4
+ 801ed20:	2200      	movs	r2, #0
+ 801ed22:	601a      	str	r2, [r3, #0]
+  arp_table[i].ethaddr = ethzero;
+ 801ed24:	4908      	ldr	r1, [pc, #32]	; (801ed48 <etharp_free_entry+0xb8>)
+ 801ed26:	687a      	ldr	r2, [r7, #4]
+ 801ed28:	4613      	mov	r3, r2
+ 801ed2a:	005b      	lsls	r3, r3, #1
+ 801ed2c:	4413      	add	r3, r2
+ 801ed2e:	00db      	lsls	r3, r3, #3
+ 801ed30:	440b      	add	r3, r1
+ 801ed32:	3308      	adds	r3, #8
+ 801ed34:	4a05      	ldr	r2, [pc, #20]	; (801ed4c <etharp_free_entry+0xbc>)
+ 801ed36:	3304      	adds	r3, #4
+ 801ed38:	6810      	ldr	r0, [r2, #0]
+ 801ed3a:	6018      	str	r0, [r3, #0]
+ 801ed3c:	8892      	ldrh	r2, [r2, #4]
+ 801ed3e:	809a      	strh	r2, [r3, #4]
+#endif /* LWIP_DEBUG */
+}
+ 801ed40:	bf00      	nop
+ 801ed42:	3708      	adds	r7, #8
+ 801ed44:	46bd      	mov	sp, r7
+ 801ed46:	bd80      	pop	{r7, pc}
+ 801ed48:	2401a4e4 	.word	0x2401a4e4
+ 801ed4c:	08026cf8 	.word	0x08026cf8
+
+0801ed50 <etharp_tmr>:
+ * This function should be called every ARP_TMR_INTERVAL milliseconds (1 second),
+ * in order to expire entries in the ARP table.
+ */
+void
+etharp_tmr(void)
+{
+ 801ed50:	b580      	push	{r7, lr}
+ 801ed52:	b082      	sub	sp, #8
+ 801ed54:	af00      	add	r7, sp, #0
+  int i;
+
+  LWIP_DEBUGF(ETHARP_DEBUG, ("etharp_timer\n"));
+  /* remove expired entries from the ARP table */
+  for (i = 0; i < ARP_TABLE_SIZE; ++i) {
+ 801ed56:	2300      	movs	r3, #0
+ 801ed58:	607b      	str	r3, [r7, #4]
+ 801ed5a:	e096      	b.n	801ee8a <etharp_tmr+0x13a>
+    u8_t state = arp_table[i].state;
+ 801ed5c:	494f      	ldr	r1, [pc, #316]	; (801ee9c <etharp_tmr+0x14c>)
+ 801ed5e:	687a      	ldr	r2, [r7, #4]
+ 801ed60:	4613      	mov	r3, r2
+ 801ed62:	005b      	lsls	r3, r3, #1
+ 801ed64:	4413      	add	r3, r2
+ 801ed66:	00db      	lsls	r3, r3, #3
+ 801ed68:	440b      	add	r3, r1
+ 801ed6a:	3314      	adds	r3, #20
+ 801ed6c:	781b      	ldrb	r3, [r3, #0]
+ 801ed6e:	70fb      	strb	r3, [r7, #3]
+    if (state != ETHARP_STATE_EMPTY
+ 801ed70:	78fb      	ldrb	r3, [r7, #3]
+ 801ed72:	2b00      	cmp	r3, #0
+ 801ed74:	f000 8086 	beq.w	801ee84 <etharp_tmr+0x134>
+#if ETHARP_SUPPORT_STATIC_ENTRIES
+        && (state != ETHARP_STATE_STATIC)
+#endif /* ETHARP_SUPPORT_STATIC_ENTRIES */
+       ) {
+      arp_table[i].ctime++;
+ 801ed78:	4948      	ldr	r1, [pc, #288]	; (801ee9c <etharp_tmr+0x14c>)
+ 801ed7a:	687a      	ldr	r2, [r7, #4]
+ 801ed7c:	4613      	mov	r3, r2
+ 801ed7e:	005b      	lsls	r3, r3, #1
+ 801ed80:	4413      	add	r3, r2
+ 801ed82:	00db      	lsls	r3, r3, #3
+ 801ed84:	440b      	add	r3, r1
+ 801ed86:	3312      	adds	r3, #18
+ 801ed88:	881b      	ldrh	r3, [r3, #0]
+ 801ed8a:	3301      	adds	r3, #1
+ 801ed8c:	b298      	uxth	r0, r3
+ 801ed8e:	4943      	ldr	r1, [pc, #268]	; (801ee9c <etharp_tmr+0x14c>)
+ 801ed90:	687a      	ldr	r2, [r7, #4]
+ 801ed92:	4613      	mov	r3, r2
+ 801ed94:	005b      	lsls	r3, r3, #1
+ 801ed96:	4413      	add	r3, r2
+ 801ed98:	00db      	lsls	r3, r3, #3
+ 801ed9a:	440b      	add	r3, r1
+ 801ed9c:	3312      	adds	r3, #18
+ 801ed9e:	4602      	mov	r2, r0
+ 801eda0:	801a      	strh	r2, [r3, #0]
+      if ((arp_table[i].ctime >= ARP_MAXAGE) ||
+ 801eda2:	493e      	ldr	r1, [pc, #248]	; (801ee9c <etharp_tmr+0x14c>)
+ 801eda4:	687a      	ldr	r2, [r7, #4]
+ 801eda6:	4613      	mov	r3, r2
+ 801eda8:	005b      	lsls	r3, r3, #1
+ 801edaa:	4413      	add	r3, r2
+ 801edac:	00db      	lsls	r3, r3, #3
+ 801edae:	440b      	add	r3, r1
+ 801edb0:	3312      	adds	r3, #18
+ 801edb2:	881b      	ldrh	r3, [r3, #0]
+ 801edb4:	f5b3 7f96 	cmp.w	r3, #300	; 0x12c
+ 801edb8:	d215      	bcs.n	801ede6 <etharp_tmr+0x96>
+          ((arp_table[i].state == ETHARP_STATE_PENDING)  &&
+ 801edba:	4938      	ldr	r1, [pc, #224]	; (801ee9c <etharp_tmr+0x14c>)
+ 801edbc:	687a      	ldr	r2, [r7, #4]
+ 801edbe:	4613      	mov	r3, r2
+ 801edc0:	005b      	lsls	r3, r3, #1
+ 801edc2:	4413      	add	r3, r2
+ 801edc4:	00db      	lsls	r3, r3, #3
+ 801edc6:	440b      	add	r3, r1
+ 801edc8:	3314      	adds	r3, #20
+ 801edca:	781b      	ldrb	r3, [r3, #0]
+      if ((arp_table[i].ctime >= ARP_MAXAGE) ||
+ 801edcc:	2b01      	cmp	r3, #1
+ 801edce:	d10e      	bne.n	801edee <etharp_tmr+0x9e>
+           (arp_table[i].ctime >= ARP_MAXPENDING))) {
+ 801edd0:	4932      	ldr	r1, [pc, #200]	; (801ee9c <etharp_tmr+0x14c>)
+ 801edd2:	687a      	ldr	r2, [r7, #4]
+ 801edd4:	4613      	mov	r3, r2
+ 801edd6:	005b      	lsls	r3, r3, #1
+ 801edd8:	4413      	add	r3, r2
+ 801edda:	00db      	lsls	r3, r3, #3
+ 801eddc:	440b      	add	r3, r1
+ 801edde:	3312      	adds	r3, #18
+ 801ede0:	881b      	ldrh	r3, [r3, #0]
+          ((arp_table[i].state == ETHARP_STATE_PENDING)  &&
+ 801ede2:	2b04      	cmp	r3, #4
+ 801ede4:	d903      	bls.n	801edee <etharp_tmr+0x9e>
+        /* pending or stable entry has become old! */
+        LWIP_DEBUGF(ETHARP_DEBUG, ("etharp_timer: expired %s entry %d.\n",
+                                   arp_table[i].state >= ETHARP_STATE_STABLE ? "stable" : "pending", i));
+        /* clean up entries that have just been expired */
+        etharp_free_entry(i);
+ 801ede6:	6878      	ldr	r0, [r7, #4]
+ 801ede8:	f7ff ff52 	bl	801ec90 <etharp_free_entry>
+ 801edec:	e04a      	b.n	801ee84 <etharp_tmr+0x134>
+      } else if (arp_table[i].state == ETHARP_STATE_STABLE_REREQUESTING_1) {
+ 801edee:	492b      	ldr	r1, [pc, #172]	; (801ee9c <etharp_tmr+0x14c>)
+ 801edf0:	687a      	ldr	r2, [r7, #4]
+ 801edf2:	4613      	mov	r3, r2
+ 801edf4:	005b      	lsls	r3, r3, #1
+ 801edf6:	4413      	add	r3, r2
+ 801edf8:	00db      	lsls	r3, r3, #3
+ 801edfa:	440b      	add	r3, r1
+ 801edfc:	3314      	adds	r3, #20
+ 801edfe:	781b      	ldrb	r3, [r3, #0]
+ 801ee00:	2b03      	cmp	r3, #3
+ 801ee02:	d10a      	bne.n	801ee1a <etharp_tmr+0xca>
+        /* Don't send more than one request every 2 seconds. */
+        arp_table[i].state = ETHARP_STATE_STABLE_REREQUESTING_2;
+ 801ee04:	4925      	ldr	r1, [pc, #148]	; (801ee9c <etharp_tmr+0x14c>)
+ 801ee06:	687a      	ldr	r2, [r7, #4]
+ 801ee08:	4613      	mov	r3, r2
+ 801ee0a:	005b      	lsls	r3, r3, #1
+ 801ee0c:	4413      	add	r3, r2
+ 801ee0e:	00db      	lsls	r3, r3, #3
+ 801ee10:	440b      	add	r3, r1
+ 801ee12:	3314      	adds	r3, #20
+ 801ee14:	2204      	movs	r2, #4
+ 801ee16:	701a      	strb	r2, [r3, #0]
+ 801ee18:	e034      	b.n	801ee84 <etharp_tmr+0x134>
+      } else if (arp_table[i].state == ETHARP_STATE_STABLE_REREQUESTING_2) {
+ 801ee1a:	4920      	ldr	r1, [pc, #128]	; (801ee9c <etharp_tmr+0x14c>)
+ 801ee1c:	687a      	ldr	r2, [r7, #4]
+ 801ee1e:	4613      	mov	r3, r2
+ 801ee20:	005b      	lsls	r3, r3, #1
+ 801ee22:	4413      	add	r3, r2
+ 801ee24:	00db      	lsls	r3, r3, #3
+ 801ee26:	440b      	add	r3, r1
+ 801ee28:	3314      	adds	r3, #20
+ 801ee2a:	781b      	ldrb	r3, [r3, #0]
+ 801ee2c:	2b04      	cmp	r3, #4
+ 801ee2e:	d10a      	bne.n	801ee46 <etharp_tmr+0xf6>
+        /* Reset state to stable, so that the next transmitted packet will
+           re-send an ARP request. */
+        arp_table[i].state = ETHARP_STATE_STABLE;
+ 801ee30:	491a      	ldr	r1, [pc, #104]	; (801ee9c <etharp_tmr+0x14c>)
+ 801ee32:	687a      	ldr	r2, [r7, #4]
+ 801ee34:	4613      	mov	r3, r2
+ 801ee36:	005b      	lsls	r3, r3, #1
+ 801ee38:	4413      	add	r3, r2
+ 801ee3a:	00db      	lsls	r3, r3, #3
+ 801ee3c:	440b      	add	r3, r1
+ 801ee3e:	3314      	adds	r3, #20
+ 801ee40:	2202      	movs	r2, #2
+ 801ee42:	701a      	strb	r2, [r3, #0]
+ 801ee44:	e01e      	b.n	801ee84 <etharp_tmr+0x134>
+      } else if (arp_table[i].state == ETHARP_STATE_PENDING) {
+ 801ee46:	4915      	ldr	r1, [pc, #84]	; (801ee9c <etharp_tmr+0x14c>)
+ 801ee48:	687a      	ldr	r2, [r7, #4]
+ 801ee4a:	4613      	mov	r3, r2
+ 801ee4c:	005b      	lsls	r3, r3, #1
+ 801ee4e:	4413      	add	r3, r2
+ 801ee50:	00db      	lsls	r3, r3, #3
+ 801ee52:	440b      	add	r3, r1
+ 801ee54:	3314      	adds	r3, #20
+ 801ee56:	781b      	ldrb	r3, [r3, #0]
+ 801ee58:	2b01      	cmp	r3, #1
+ 801ee5a:	d113      	bne.n	801ee84 <etharp_tmr+0x134>
+        /* still pending, resend an ARP query */
+        etharp_request(arp_table[i].netif, &arp_table[i].ipaddr);
+ 801ee5c:	490f      	ldr	r1, [pc, #60]	; (801ee9c <etharp_tmr+0x14c>)
+ 801ee5e:	687a      	ldr	r2, [r7, #4]
+ 801ee60:	4613      	mov	r3, r2
+ 801ee62:	005b      	lsls	r3, r3, #1
+ 801ee64:	4413      	add	r3, r2
+ 801ee66:	00db      	lsls	r3, r3, #3
+ 801ee68:	440b      	add	r3, r1
+ 801ee6a:	3308      	adds	r3, #8
+ 801ee6c:	6818      	ldr	r0, [r3, #0]
+ 801ee6e:	687a      	ldr	r2, [r7, #4]
+ 801ee70:	4613      	mov	r3, r2
+ 801ee72:	005b      	lsls	r3, r3, #1
+ 801ee74:	4413      	add	r3, r2
+ 801ee76:	00db      	lsls	r3, r3, #3
+ 801ee78:	4a08      	ldr	r2, [pc, #32]	; (801ee9c <etharp_tmr+0x14c>)
+ 801ee7a:	4413      	add	r3, r2
+ 801ee7c:	3304      	adds	r3, #4
+ 801ee7e:	4619      	mov	r1, r3
+ 801ee80:	f000 fe6e 	bl	801fb60 <etharp_request>
+  for (i = 0; i < ARP_TABLE_SIZE; ++i) {
+ 801ee84:	687b      	ldr	r3, [r7, #4]
+ 801ee86:	3301      	adds	r3, #1
+ 801ee88:	607b      	str	r3, [r7, #4]
+ 801ee8a:	687b      	ldr	r3, [r7, #4]
+ 801ee8c:	2b09      	cmp	r3, #9
+ 801ee8e:	f77f af65 	ble.w	801ed5c <etharp_tmr+0xc>
+      }
+    }
+  }
+}
+ 801ee92:	bf00      	nop
+ 801ee94:	bf00      	nop
+ 801ee96:	3708      	adds	r7, #8
+ 801ee98:	46bd      	mov	sp, r7
+ 801ee9a:	bd80      	pop	{r7, pc}
+ 801ee9c:	2401a4e4 	.word	0x2401a4e4
+
+0801eea0 <etharp_find_entry>:
+ * @return The ARP entry index that matched or is created, ERR_MEM if no
+ * entry is found or could be recycled.
+ */
+static s16_t
+etharp_find_entry(const ip4_addr_t *ipaddr, u8_t flags, struct netif *netif)
+{
+ 801eea0:	b580      	push	{r7, lr}
+ 801eea2:	b08a      	sub	sp, #40	; 0x28
+ 801eea4:	af00      	add	r7, sp, #0
+ 801eea6:	60f8      	str	r0, [r7, #12]
+ 801eea8:	460b      	mov	r3, r1
+ 801eeaa:	607a      	str	r2, [r7, #4]
+ 801eeac:	72fb      	strb	r3, [r7, #11]
+  s16_t old_pending = ARP_TABLE_SIZE, old_stable = ARP_TABLE_SIZE;
+ 801eeae:	230a      	movs	r3, #10
+ 801eeb0:	843b      	strh	r3, [r7, #32]
+ 801eeb2:	230a      	movs	r3, #10
+ 801eeb4:	847b      	strh	r3, [r7, #34]	; 0x22
+  s16_t empty = ARP_TABLE_SIZE;
+ 801eeb6:	230a      	movs	r3, #10
+ 801eeb8:	84bb      	strh	r3, [r7, #36]	; 0x24
+  s16_t i = 0;
+ 801eeba:	2300      	movs	r3, #0
+ 801eebc:	84fb      	strh	r3, [r7, #38]	; 0x26
+  /* oldest entry with packets on queue */
+  s16_t old_queue = ARP_TABLE_SIZE;
+ 801eebe:	230a      	movs	r3, #10
+ 801eec0:	83fb      	strh	r3, [r7, #30]
+  /* its age */
+  u16_t age_queue = 0, age_pending = 0, age_stable = 0;
+ 801eec2:	2300      	movs	r3, #0
+ 801eec4:	83bb      	strh	r3, [r7, #28]
+ 801eec6:	2300      	movs	r3, #0
+ 801eec8:	837b      	strh	r3, [r7, #26]
+ 801eeca:	2300      	movs	r3, #0
+ 801eecc:	833b      	strh	r3, [r7, #24]
+   * 4) remember the oldest pending entry with queued packets (if any)
+   * 5) search for a matching IP entry, either pending or stable
+   *    until 5 matches, or all entries are searched for.
+   */
+
+  for (i = 0; i < ARP_TABLE_SIZE; ++i) {
+ 801eece:	2300      	movs	r3, #0
+ 801eed0:	84fb      	strh	r3, [r7, #38]	; 0x26
+ 801eed2:	e0ae      	b.n	801f032 <etharp_find_entry+0x192>
+    u8_t state = arp_table[i].state;
+ 801eed4:	f9b7 2026 	ldrsh.w	r2, [r7, #38]	; 0x26
+ 801eed8:	49a6      	ldr	r1, [pc, #664]	; (801f174 <etharp_find_entry+0x2d4>)
+ 801eeda:	4613      	mov	r3, r2
+ 801eedc:	005b      	lsls	r3, r3, #1
+ 801eede:	4413      	add	r3, r2
+ 801eee0:	00db      	lsls	r3, r3, #3
+ 801eee2:	440b      	add	r3, r1
+ 801eee4:	3314      	adds	r3, #20
+ 801eee6:	781b      	ldrb	r3, [r3, #0]
+ 801eee8:	75fb      	strb	r3, [r7, #23]
+    /* no empty entry found yet and now we do find one? */
+    if ((empty == ARP_TABLE_SIZE) && (state == ETHARP_STATE_EMPTY)) {
+ 801eeea:	f9b7 3024 	ldrsh.w	r3, [r7, #36]	; 0x24
+ 801eeee:	2b0a      	cmp	r3, #10
+ 801eef0:	d105      	bne.n	801eefe <etharp_find_entry+0x5e>
+ 801eef2:	7dfb      	ldrb	r3, [r7, #23]
+ 801eef4:	2b00      	cmp	r3, #0
+ 801eef6:	d102      	bne.n	801eefe <etharp_find_entry+0x5e>
+      LWIP_DEBUGF(ETHARP_DEBUG, ("etharp_find_entry: found empty entry %d\n", (int)i));
+      /* remember first empty entry */
+      empty = i;
+ 801eef8:	8cfb      	ldrh	r3, [r7, #38]	; 0x26
+ 801eefa:	84bb      	strh	r3, [r7, #36]	; 0x24
+ 801eefc:	e095      	b.n	801f02a <etharp_find_entry+0x18a>
+    } else if (state != ETHARP_STATE_EMPTY) {
+ 801eefe:	7dfb      	ldrb	r3, [r7, #23]
+ 801ef00:	2b00      	cmp	r3, #0
+ 801ef02:	f000 8092 	beq.w	801f02a <etharp_find_entry+0x18a>
+      LWIP_ASSERT("state == ETHARP_STATE_PENDING || state >= ETHARP_STATE_STABLE",
+ 801ef06:	7dfb      	ldrb	r3, [r7, #23]
+ 801ef08:	2b01      	cmp	r3, #1
+ 801ef0a:	d009      	beq.n	801ef20 <etharp_find_entry+0x80>
+ 801ef0c:	7dfb      	ldrb	r3, [r7, #23]
+ 801ef0e:	2b01      	cmp	r3, #1
+ 801ef10:	d806      	bhi.n	801ef20 <etharp_find_entry+0x80>
+ 801ef12:	4b99      	ldr	r3, [pc, #612]	; (801f178 <etharp_find_entry+0x2d8>)
+ 801ef14:	f240 1223 	movw	r2, #291	; 0x123
+ 801ef18:	4998      	ldr	r1, [pc, #608]	; (801f17c <etharp_find_entry+0x2dc>)
+ 801ef1a:	4899      	ldr	r0, [pc, #612]	; (801f180 <etharp_find_entry+0x2e0>)
+ 801ef1c:	f002 fd34 	bl	8021988 <iprintf>
+                  state == ETHARP_STATE_PENDING || state >= ETHARP_STATE_STABLE);
+      /* if given, does IP address match IP address in ARP entry? */
+      if (ipaddr && ip4_addr_cmp(ipaddr, &arp_table[i].ipaddr)
+ 801ef20:	68fb      	ldr	r3, [r7, #12]
+ 801ef22:	2b00      	cmp	r3, #0
+ 801ef24:	d020      	beq.n	801ef68 <etharp_find_entry+0xc8>
+ 801ef26:	68fb      	ldr	r3, [r7, #12]
+ 801ef28:	6819      	ldr	r1, [r3, #0]
+ 801ef2a:	f9b7 2026 	ldrsh.w	r2, [r7, #38]	; 0x26
+ 801ef2e:	4891      	ldr	r0, [pc, #580]	; (801f174 <etharp_find_entry+0x2d4>)
+ 801ef30:	4613      	mov	r3, r2
+ 801ef32:	005b      	lsls	r3, r3, #1
+ 801ef34:	4413      	add	r3, r2
+ 801ef36:	00db      	lsls	r3, r3, #3
+ 801ef38:	4403      	add	r3, r0
+ 801ef3a:	3304      	adds	r3, #4
+ 801ef3c:	681b      	ldr	r3, [r3, #0]
+ 801ef3e:	4299      	cmp	r1, r3
+ 801ef40:	d112      	bne.n	801ef68 <etharp_find_entry+0xc8>
+#if ETHARP_TABLE_MATCH_NETIF
+          && ((netif == NULL) || (netif == arp_table[i].netif))
+ 801ef42:	687b      	ldr	r3, [r7, #4]
+ 801ef44:	2b00      	cmp	r3, #0
+ 801ef46:	d00c      	beq.n	801ef62 <etharp_find_entry+0xc2>
+ 801ef48:	f9b7 2026 	ldrsh.w	r2, [r7, #38]	; 0x26
+ 801ef4c:	4989      	ldr	r1, [pc, #548]	; (801f174 <etharp_find_entry+0x2d4>)
+ 801ef4e:	4613      	mov	r3, r2
+ 801ef50:	005b      	lsls	r3, r3, #1
+ 801ef52:	4413      	add	r3, r2
+ 801ef54:	00db      	lsls	r3, r3, #3
+ 801ef56:	440b      	add	r3, r1
+ 801ef58:	3308      	adds	r3, #8
+ 801ef5a:	681b      	ldr	r3, [r3, #0]
+ 801ef5c:	687a      	ldr	r2, [r7, #4]
+ 801ef5e:	429a      	cmp	r2, r3
+ 801ef60:	d102      	bne.n	801ef68 <etharp_find_entry+0xc8>
+#endif /* ETHARP_TABLE_MATCH_NETIF */
+         ) {
+        LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_find_entry: found matching entry %d\n", (int)i));
+        /* found exact IP address match, simply bail out */
+        return i;
+ 801ef62:	f9b7 3026 	ldrsh.w	r3, [r7, #38]	; 0x26
+ 801ef66:	e100      	b.n	801f16a <etharp_find_entry+0x2ca>
+      }
+      /* pending entry? */
+      if (state == ETHARP_STATE_PENDING) {
+ 801ef68:	7dfb      	ldrb	r3, [r7, #23]
+ 801ef6a:	2b01      	cmp	r3, #1
+ 801ef6c:	d140      	bne.n	801eff0 <etharp_find_entry+0x150>
+        /* pending with queued packets? */
+        if (arp_table[i].q != NULL) {
+ 801ef6e:	f9b7 2026 	ldrsh.w	r2, [r7, #38]	; 0x26
+ 801ef72:	4980      	ldr	r1, [pc, #512]	; (801f174 <etharp_find_entry+0x2d4>)
+ 801ef74:	4613      	mov	r3, r2
+ 801ef76:	005b      	lsls	r3, r3, #1
+ 801ef78:	4413      	add	r3, r2
+ 801ef7a:	00db      	lsls	r3, r3, #3
+ 801ef7c:	440b      	add	r3, r1
+ 801ef7e:	681b      	ldr	r3, [r3, #0]
+ 801ef80:	2b00      	cmp	r3, #0
+ 801ef82:	d01a      	beq.n	801efba <etharp_find_entry+0x11a>
+          if (arp_table[i].ctime >= age_queue) {
+ 801ef84:	f9b7 2026 	ldrsh.w	r2, [r7, #38]	; 0x26
+ 801ef88:	497a      	ldr	r1, [pc, #488]	; (801f174 <etharp_find_entry+0x2d4>)
+ 801ef8a:	4613      	mov	r3, r2
+ 801ef8c:	005b      	lsls	r3, r3, #1
+ 801ef8e:	4413      	add	r3, r2
+ 801ef90:	00db      	lsls	r3, r3, #3
+ 801ef92:	440b      	add	r3, r1
+ 801ef94:	3312      	adds	r3, #18
+ 801ef96:	881b      	ldrh	r3, [r3, #0]
+ 801ef98:	8bba      	ldrh	r2, [r7, #28]
+ 801ef9a:	429a      	cmp	r2, r3
+ 801ef9c:	d845      	bhi.n	801f02a <etharp_find_entry+0x18a>
+            old_queue = i;
+ 801ef9e:	8cfb      	ldrh	r3, [r7, #38]	; 0x26
+ 801efa0:	83fb      	strh	r3, [r7, #30]
+            age_queue = arp_table[i].ctime;
+ 801efa2:	f9b7 2026 	ldrsh.w	r2, [r7, #38]	; 0x26
+ 801efa6:	4973      	ldr	r1, [pc, #460]	; (801f174 <etharp_find_entry+0x2d4>)
+ 801efa8:	4613      	mov	r3, r2
+ 801efaa:	005b      	lsls	r3, r3, #1
+ 801efac:	4413      	add	r3, r2
+ 801efae:	00db      	lsls	r3, r3, #3
+ 801efb0:	440b      	add	r3, r1
+ 801efb2:	3312      	adds	r3, #18
+ 801efb4:	881b      	ldrh	r3, [r3, #0]
+ 801efb6:	83bb      	strh	r3, [r7, #28]
+ 801efb8:	e037      	b.n	801f02a <etharp_find_entry+0x18a>
+          }
+        } else
+          /* pending without queued packets? */
+        {
+          if (arp_table[i].ctime >= age_pending) {
+ 801efba:	f9b7 2026 	ldrsh.w	r2, [r7, #38]	; 0x26
+ 801efbe:	496d      	ldr	r1, [pc, #436]	; (801f174 <etharp_find_entry+0x2d4>)
+ 801efc0:	4613      	mov	r3, r2
+ 801efc2:	005b      	lsls	r3, r3, #1
+ 801efc4:	4413      	add	r3, r2
+ 801efc6:	00db      	lsls	r3, r3, #3
+ 801efc8:	440b      	add	r3, r1
+ 801efca:	3312      	adds	r3, #18
+ 801efcc:	881b      	ldrh	r3, [r3, #0]
+ 801efce:	8b7a      	ldrh	r2, [r7, #26]
+ 801efd0:	429a      	cmp	r2, r3
+ 801efd2:	d82a      	bhi.n	801f02a <etharp_find_entry+0x18a>
+            old_pending = i;
+ 801efd4:	8cfb      	ldrh	r3, [r7, #38]	; 0x26
+ 801efd6:	843b      	strh	r3, [r7, #32]
+            age_pending = arp_table[i].ctime;
+ 801efd8:	f9b7 2026 	ldrsh.w	r2, [r7, #38]	; 0x26
+ 801efdc:	4965      	ldr	r1, [pc, #404]	; (801f174 <etharp_find_entry+0x2d4>)
+ 801efde:	4613      	mov	r3, r2
+ 801efe0:	005b      	lsls	r3, r3, #1
+ 801efe2:	4413      	add	r3, r2
+ 801efe4:	00db      	lsls	r3, r3, #3
+ 801efe6:	440b      	add	r3, r1
+ 801efe8:	3312      	adds	r3, #18
+ 801efea:	881b      	ldrh	r3, [r3, #0]
+ 801efec:	837b      	strh	r3, [r7, #26]
+ 801efee:	e01c      	b.n	801f02a <etharp_find_entry+0x18a>
+          }
+        }
+        /* stable entry? */
+      } else if (state >= ETHARP_STATE_STABLE) {
+ 801eff0:	7dfb      	ldrb	r3, [r7, #23]
+ 801eff2:	2b01      	cmp	r3, #1
+ 801eff4:	d919      	bls.n	801f02a <etharp_find_entry+0x18a>
+        /* don't record old_stable for static entries since they never expire */
+        if (state < ETHARP_STATE_STATIC)
+#endif /* ETHARP_SUPPORT_STATIC_ENTRIES */
+        {
+          /* remember entry with oldest stable entry in oldest, its age in maxtime */
+          if (arp_table[i].ctime >= age_stable) {
+ 801eff6:	f9b7 2026 	ldrsh.w	r2, [r7, #38]	; 0x26
+ 801effa:	495e      	ldr	r1, [pc, #376]	; (801f174 <etharp_find_entry+0x2d4>)
+ 801effc:	4613      	mov	r3, r2
+ 801effe:	005b      	lsls	r3, r3, #1
+ 801f000:	4413      	add	r3, r2
+ 801f002:	00db      	lsls	r3, r3, #3
+ 801f004:	440b      	add	r3, r1
+ 801f006:	3312      	adds	r3, #18
+ 801f008:	881b      	ldrh	r3, [r3, #0]
+ 801f00a:	8b3a      	ldrh	r2, [r7, #24]
+ 801f00c:	429a      	cmp	r2, r3
+ 801f00e:	d80c      	bhi.n	801f02a <etharp_find_entry+0x18a>
+            old_stable = i;
+ 801f010:	8cfb      	ldrh	r3, [r7, #38]	; 0x26
+ 801f012:	847b      	strh	r3, [r7, #34]	; 0x22
+            age_stable = arp_table[i].ctime;
+ 801f014:	f9b7 2026 	ldrsh.w	r2, [r7, #38]	; 0x26
+ 801f018:	4956      	ldr	r1, [pc, #344]	; (801f174 <etharp_find_entry+0x2d4>)
+ 801f01a:	4613      	mov	r3, r2
+ 801f01c:	005b      	lsls	r3, r3, #1
+ 801f01e:	4413      	add	r3, r2
+ 801f020:	00db      	lsls	r3, r3, #3
+ 801f022:	440b      	add	r3, r1
+ 801f024:	3312      	adds	r3, #18
+ 801f026:	881b      	ldrh	r3, [r3, #0]
+ 801f028:	833b      	strh	r3, [r7, #24]
+  for (i = 0; i < ARP_TABLE_SIZE; ++i) {
+ 801f02a:	8cfb      	ldrh	r3, [r7, #38]	; 0x26
+ 801f02c:	3301      	adds	r3, #1
+ 801f02e:	b29b      	uxth	r3, r3
+ 801f030:	84fb      	strh	r3, [r7, #38]	; 0x26
+ 801f032:	f9b7 3026 	ldrsh.w	r3, [r7, #38]	; 0x26
+ 801f036:	2b09      	cmp	r3, #9
+ 801f038:	f77f af4c 	ble.w	801eed4 <etharp_find_entry+0x34>
+    }
+  }
+  /* { we have no match } => try to create a new entry */
+
+  /* don't create new entry, only search? */
+  if (((flags & ETHARP_FLAG_FIND_ONLY) != 0) ||
+ 801f03c:	7afb      	ldrb	r3, [r7, #11]
+ 801f03e:	f003 0302 	and.w	r3, r3, #2
+ 801f042:	2b00      	cmp	r3, #0
+ 801f044:	d108      	bne.n	801f058 <etharp_find_entry+0x1b8>
+ 801f046:	f9b7 3024 	ldrsh.w	r3, [r7, #36]	; 0x24
+ 801f04a:	2b0a      	cmp	r3, #10
+ 801f04c:	d107      	bne.n	801f05e <etharp_find_entry+0x1be>
+      /* or no empty entry found and not allowed to recycle? */
+      ((empty == ARP_TABLE_SIZE) && ((flags & ETHARP_FLAG_TRY_HARD) == 0))) {
+ 801f04e:	7afb      	ldrb	r3, [r7, #11]
+ 801f050:	f003 0301 	and.w	r3, r3, #1
+ 801f054:	2b00      	cmp	r3, #0
+ 801f056:	d102      	bne.n	801f05e <etharp_find_entry+0x1be>
+    LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_find_entry: no empty entry found and not allowed to recycle\n"));
+    return (s16_t)ERR_MEM;
+ 801f058:	f04f 33ff 	mov.w	r3, #4294967295
+ 801f05c:	e085      	b.n	801f16a <etharp_find_entry+0x2ca>
+   *
+   * { ETHARP_FLAG_TRY_HARD is set at this point }
+   */
+
+  /* 1) empty entry available? */
+  if (empty < ARP_TABLE_SIZE) {
+ 801f05e:	f9b7 3024 	ldrsh.w	r3, [r7, #36]	; 0x24
+ 801f062:	2b09      	cmp	r3, #9
+ 801f064:	dc02      	bgt.n	801f06c <etharp_find_entry+0x1cc>
+    i = empty;
+ 801f066:	8cbb      	ldrh	r3, [r7, #36]	; 0x24
+ 801f068:	84fb      	strh	r3, [r7, #38]	; 0x26
+ 801f06a:	e039      	b.n	801f0e0 <etharp_find_entry+0x240>
+    LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_find_entry: selecting empty entry %d\n", (int)i));
+  } else {
+    /* 2) found recyclable stable entry? */
+    if (old_stable < ARP_TABLE_SIZE) {
+ 801f06c:	f9b7 3022 	ldrsh.w	r3, [r7, #34]	; 0x22
+ 801f070:	2b09      	cmp	r3, #9
+ 801f072:	dc14      	bgt.n	801f09e <etharp_find_entry+0x1fe>
+      /* recycle oldest stable*/
+      i = old_stable;
+ 801f074:	8c7b      	ldrh	r3, [r7, #34]	; 0x22
+ 801f076:	84fb      	strh	r3, [r7, #38]	; 0x26
+      LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_find_entry: selecting oldest stable entry %d\n", (int)i));
+      /* no queued packets should exist on stable entries */
+      LWIP_ASSERT("arp_table[i].q == NULL", arp_table[i].q == NULL);
+ 801f078:	f9b7 2026 	ldrsh.w	r2, [r7, #38]	; 0x26
+ 801f07c:	493d      	ldr	r1, [pc, #244]	; (801f174 <etharp_find_entry+0x2d4>)
+ 801f07e:	4613      	mov	r3, r2
+ 801f080:	005b      	lsls	r3, r3, #1
+ 801f082:	4413      	add	r3, r2
+ 801f084:	00db      	lsls	r3, r3, #3
+ 801f086:	440b      	add	r3, r1
+ 801f088:	681b      	ldr	r3, [r3, #0]
+ 801f08a:	2b00      	cmp	r3, #0
+ 801f08c:	d018      	beq.n	801f0c0 <etharp_find_entry+0x220>
+ 801f08e:	4b3a      	ldr	r3, [pc, #232]	; (801f178 <etharp_find_entry+0x2d8>)
+ 801f090:	f240 126d 	movw	r2, #365	; 0x16d
+ 801f094:	493b      	ldr	r1, [pc, #236]	; (801f184 <etharp_find_entry+0x2e4>)
+ 801f096:	483a      	ldr	r0, [pc, #232]	; (801f180 <etharp_find_entry+0x2e0>)
+ 801f098:	f002 fc76 	bl	8021988 <iprintf>
+ 801f09c:	e010      	b.n	801f0c0 <etharp_find_entry+0x220>
+      /* 3) found recyclable pending entry without queued packets? */
+    } else if (old_pending < ARP_TABLE_SIZE) {
+ 801f09e:	f9b7 3020 	ldrsh.w	r3, [r7, #32]
+ 801f0a2:	2b09      	cmp	r3, #9
+ 801f0a4:	dc02      	bgt.n	801f0ac <etharp_find_entry+0x20c>
+      /* recycle oldest pending */
+      i = old_pending;
+ 801f0a6:	8c3b      	ldrh	r3, [r7, #32]
+ 801f0a8:	84fb      	strh	r3, [r7, #38]	; 0x26
+ 801f0aa:	e009      	b.n	801f0c0 <etharp_find_entry+0x220>
+      LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_find_entry: selecting oldest pending entry %d (without queue)\n", (int)i));
+      /* 4) found recyclable pending entry with queued packets? */
+    } else if (old_queue < ARP_TABLE_SIZE) {
+ 801f0ac:	f9b7 301e 	ldrsh.w	r3, [r7, #30]
+ 801f0b0:	2b09      	cmp	r3, #9
+ 801f0b2:	dc02      	bgt.n	801f0ba <etharp_find_entry+0x21a>
+      /* recycle oldest pending (queued packets are free in etharp_free_entry) */
+      i = old_queue;
+ 801f0b4:	8bfb      	ldrh	r3, [r7, #30]
+ 801f0b6:	84fb      	strh	r3, [r7, #38]	; 0x26
+ 801f0b8:	e002      	b.n	801f0c0 <etharp_find_entry+0x220>
+      LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_find_entry: selecting oldest pending entry %d, freeing packet queue %p\n", (int)i, (void *)(arp_table[i].q)));
+      /* no empty or recyclable entries found */
+    } else {
+      LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_find_entry: no empty or recyclable entries found\n"));
+      return (s16_t)ERR_MEM;
+ 801f0ba:	f04f 33ff 	mov.w	r3, #4294967295
+ 801f0be:	e054      	b.n	801f16a <etharp_find_entry+0x2ca>
+    }
+
+    /* { empty or recyclable entry found } */
+    LWIP_ASSERT("i < ARP_TABLE_SIZE", i < ARP_TABLE_SIZE);
+ 801f0c0:	f9b7 3026 	ldrsh.w	r3, [r7, #38]	; 0x26
+ 801f0c4:	2b09      	cmp	r3, #9
+ 801f0c6:	dd06      	ble.n	801f0d6 <etharp_find_entry+0x236>
+ 801f0c8:	4b2b      	ldr	r3, [pc, #172]	; (801f178 <etharp_find_entry+0x2d8>)
+ 801f0ca:	f240 127f 	movw	r2, #383	; 0x17f
+ 801f0ce:	492e      	ldr	r1, [pc, #184]	; (801f188 <etharp_find_entry+0x2e8>)
+ 801f0d0:	482b      	ldr	r0, [pc, #172]	; (801f180 <etharp_find_entry+0x2e0>)
+ 801f0d2:	f002 fc59 	bl	8021988 <iprintf>
+    etharp_free_entry(i);
+ 801f0d6:	f9b7 3026 	ldrsh.w	r3, [r7, #38]	; 0x26
+ 801f0da:	4618      	mov	r0, r3
+ 801f0dc:	f7ff fdd8 	bl	801ec90 <etharp_free_entry>
+  }
+
+  LWIP_ASSERT("i < ARP_TABLE_SIZE", i < ARP_TABLE_SIZE);
+ 801f0e0:	f9b7 3026 	ldrsh.w	r3, [r7, #38]	; 0x26
+ 801f0e4:	2b09      	cmp	r3, #9
+ 801f0e6:	dd06      	ble.n	801f0f6 <etharp_find_entry+0x256>
+ 801f0e8:	4b23      	ldr	r3, [pc, #140]	; (801f178 <etharp_find_entry+0x2d8>)
+ 801f0ea:	f240 1283 	movw	r2, #387	; 0x183
+ 801f0ee:	4926      	ldr	r1, [pc, #152]	; (801f188 <etharp_find_entry+0x2e8>)
+ 801f0f0:	4823      	ldr	r0, [pc, #140]	; (801f180 <etharp_find_entry+0x2e0>)
+ 801f0f2:	f002 fc49 	bl	8021988 <iprintf>
+  LWIP_ASSERT("arp_table[i].state == ETHARP_STATE_EMPTY",
+ 801f0f6:	f9b7 2026 	ldrsh.w	r2, [r7, #38]	; 0x26
+ 801f0fa:	491e      	ldr	r1, [pc, #120]	; (801f174 <etharp_find_entry+0x2d4>)
+ 801f0fc:	4613      	mov	r3, r2
+ 801f0fe:	005b      	lsls	r3, r3, #1
+ 801f100:	4413      	add	r3, r2
+ 801f102:	00db      	lsls	r3, r3, #3
+ 801f104:	440b      	add	r3, r1
+ 801f106:	3314      	adds	r3, #20
+ 801f108:	781b      	ldrb	r3, [r3, #0]
+ 801f10a:	2b00      	cmp	r3, #0
+ 801f10c:	d006      	beq.n	801f11c <etharp_find_entry+0x27c>
+ 801f10e:	4b1a      	ldr	r3, [pc, #104]	; (801f178 <etharp_find_entry+0x2d8>)
+ 801f110:	f44f 72c2 	mov.w	r2, #388	; 0x184
+ 801f114:	491d      	ldr	r1, [pc, #116]	; (801f18c <etharp_find_entry+0x2ec>)
+ 801f116:	481a      	ldr	r0, [pc, #104]	; (801f180 <etharp_find_entry+0x2e0>)
+ 801f118:	f002 fc36 	bl	8021988 <iprintf>
+              arp_table[i].state == ETHARP_STATE_EMPTY);
+
+  /* IP address given? */
+  if (ipaddr != NULL) {
+ 801f11c:	68fb      	ldr	r3, [r7, #12]
+ 801f11e:	2b00      	cmp	r3, #0
+ 801f120:	d00b      	beq.n	801f13a <etharp_find_entry+0x29a>
+    /* set IP address */
+    ip4_addr_copy(arp_table[i].ipaddr, *ipaddr);
+ 801f122:	f9b7 2026 	ldrsh.w	r2, [r7, #38]	; 0x26
+ 801f126:	68fb      	ldr	r3, [r7, #12]
+ 801f128:	6819      	ldr	r1, [r3, #0]
+ 801f12a:	4812      	ldr	r0, [pc, #72]	; (801f174 <etharp_find_entry+0x2d4>)
+ 801f12c:	4613      	mov	r3, r2
+ 801f12e:	005b      	lsls	r3, r3, #1
+ 801f130:	4413      	add	r3, r2
+ 801f132:	00db      	lsls	r3, r3, #3
+ 801f134:	4403      	add	r3, r0
+ 801f136:	3304      	adds	r3, #4
+ 801f138:	6019      	str	r1, [r3, #0]
+  }
+  arp_table[i].ctime = 0;
+ 801f13a:	f9b7 2026 	ldrsh.w	r2, [r7, #38]	; 0x26
+ 801f13e:	490d      	ldr	r1, [pc, #52]	; (801f174 <etharp_find_entry+0x2d4>)
+ 801f140:	4613      	mov	r3, r2
+ 801f142:	005b      	lsls	r3, r3, #1
+ 801f144:	4413      	add	r3, r2
+ 801f146:	00db      	lsls	r3, r3, #3
+ 801f148:	440b      	add	r3, r1
+ 801f14a:	3312      	adds	r3, #18
+ 801f14c:	2200      	movs	r2, #0
+ 801f14e:	801a      	strh	r2, [r3, #0]
+#if ETHARP_TABLE_MATCH_NETIF
+  arp_table[i].netif = netif;
+ 801f150:	f9b7 2026 	ldrsh.w	r2, [r7, #38]	; 0x26
+ 801f154:	4907      	ldr	r1, [pc, #28]	; (801f174 <etharp_find_entry+0x2d4>)
+ 801f156:	4613      	mov	r3, r2
+ 801f158:	005b      	lsls	r3, r3, #1
+ 801f15a:	4413      	add	r3, r2
+ 801f15c:	00db      	lsls	r3, r3, #3
+ 801f15e:	440b      	add	r3, r1
+ 801f160:	3308      	adds	r3, #8
+ 801f162:	687a      	ldr	r2, [r7, #4]
+ 801f164:	601a      	str	r2, [r3, #0]
+#endif /* ETHARP_TABLE_MATCH_NETIF */
+  return (s16_t)i;
+ 801f166:	f9b7 3026 	ldrsh.w	r3, [r7, #38]	; 0x26
+}
+ 801f16a:	4618      	mov	r0, r3
+ 801f16c:	3728      	adds	r7, #40	; 0x28
+ 801f16e:	46bd      	mov	sp, r7
+ 801f170:	bd80      	pop	{r7, pc}
+ 801f172:	bf00      	nop
+ 801f174:	2401a4e4 	.word	0x2401a4e4
+ 801f178:	0802647c 	.word	0x0802647c
+ 801f17c:	080264b4 	.word	0x080264b4
+ 801f180:	080264f4 	.word	0x080264f4
+ 801f184:	0802651c 	.word	0x0802651c
+ 801f188:	08026534 	.word	0x08026534
+ 801f18c:	08026548 	.word	0x08026548
+
+0801f190 <etharp_update_arp_entry>:
+ *
+ * @see pbuf_free()
+ */
+static err_t
+etharp_update_arp_entry(struct netif *netif, const ip4_addr_t *ipaddr, struct eth_addr *ethaddr, u8_t flags)
+{
+ 801f190:	b580      	push	{r7, lr}
+ 801f192:	b088      	sub	sp, #32
+ 801f194:	af02      	add	r7, sp, #8
+ 801f196:	60f8      	str	r0, [r7, #12]
+ 801f198:	60b9      	str	r1, [r7, #8]
+ 801f19a:	607a      	str	r2, [r7, #4]
+ 801f19c:	70fb      	strb	r3, [r7, #3]
+  s16_t i;
+  LWIP_ASSERT("netif->hwaddr_len == ETH_HWADDR_LEN", netif->hwaddr_len == ETH_HWADDR_LEN);
+ 801f19e:	68fb      	ldr	r3, [r7, #12]
+ 801f1a0:	f893 302c 	ldrb.w	r3, [r3, #44]	; 0x2c
+ 801f1a4:	2b06      	cmp	r3, #6
+ 801f1a6:	d006      	beq.n	801f1b6 <etharp_update_arp_entry+0x26>
+ 801f1a8:	4b48      	ldr	r3, [pc, #288]	; (801f2cc <etharp_update_arp_entry+0x13c>)
+ 801f1aa:	f240 12a9 	movw	r2, #425	; 0x1a9
+ 801f1ae:	4948      	ldr	r1, [pc, #288]	; (801f2d0 <etharp_update_arp_entry+0x140>)
+ 801f1b0:	4848      	ldr	r0, [pc, #288]	; (801f2d4 <etharp_update_arp_entry+0x144>)
+ 801f1b2:	f002 fbe9 	bl	8021988 <iprintf>
+  LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_update_arp_entry: %"U16_F".%"U16_F".%"U16_F".%"U16_F" - %02"X16_F":%02"X16_F":%02"X16_F":%02"X16_F":%02"X16_F":%02"X16_F"\n",
+              ip4_addr1_16(ipaddr), ip4_addr2_16(ipaddr), ip4_addr3_16(ipaddr), ip4_addr4_16(ipaddr),
+              (u16_t)ethaddr->addr[0], (u16_t)ethaddr->addr[1], (u16_t)ethaddr->addr[2],
+              (u16_t)ethaddr->addr[3], (u16_t)ethaddr->addr[4], (u16_t)ethaddr->addr[5]));
+  /* non-unicast address? */
+  if (ip4_addr_isany(ipaddr) ||
+ 801f1b6:	68bb      	ldr	r3, [r7, #8]
+ 801f1b8:	2b00      	cmp	r3, #0
+ 801f1ba:	d012      	beq.n	801f1e2 <etharp_update_arp_entry+0x52>
+ 801f1bc:	68bb      	ldr	r3, [r7, #8]
+ 801f1be:	681b      	ldr	r3, [r3, #0]
+ 801f1c0:	2b00      	cmp	r3, #0
+ 801f1c2:	d00e      	beq.n	801f1e2 <etharp_update_arp_entry+0x52>
+      ip4_addr_isbroadcast(ipaddr, netif) ||
+ 801f1c4:	68bb      	ldr	r3, [r7, #8]
+ 801f1c6:	681b      	ldr	r3, [r3, #0]
+ 801f1c8:	68f9      	ldr	r1, [r7, #12]
+ 801f1ca:	4618      	mov	r0, r3
+ 801f1cc:	f001 f928 	bl	8020420 <ip4_addr_isbroadcast_u32>
+ 801f1d0:	4603      	mov	r3, r0
+  if (ip4_addr_isany(ipaddr) ||
+ 801f1d2:	2b00      	cmp	r3, #0
+ 801f1d4:	d105      	bne.n	801f1e2 <etharp_update_arp_entry+0x52>
+      ip4_addr_ismulticast(ipaddr)) {
+ 801f1d6:	68bb      	ldr	r3, [r7, #8]
+ 801f1d8:	681b      	ldr	r3, [r3, #0]
+ 801f1da:	f003 03f0 	and.w	r3, r3, #240	; 0xf0
+      ip4_addr_isbroadcast(ipaddr, netif) ||
+ 801f1de:	2be0      	cmp	r3, #224	; 0xe0
+ 801f1e0:	d102      	bne.n	801f1e8 <etharp_update_arp_entry+0x58>
+    LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_update_arp_entry: will not add non-unicast IP address to ARP cache\n"));
+    return ERR_ARG;
+ 801f1e2:	f06f 030f 	mvn.w	r3, #15
+ 801f1e6:	e06c      	b.n	801f2c2 <etharp_update_arp_entry+0x132>
+  }
+  /* find or create ARP entry */
+  i = etharp_find_entry(ipaddr, flags, netif);
+ 801f1e8:	78fb      	ldrb	r3, [r7, #3]
+ 801f1ea:	68fa      	ldr	r2, [r7, #12]
+ 801f1ec:	4619      	mov	r1, r3
+ 801f1ee:	68b8      	ldr	r0, [r7, #8]
+ 801f1f0:	f7ff fe56 	bl	801eea0 <etharp_find_entry>
+ 801f1f4:	4603      	mov	r3, r0
+ 801f1f6:	82fb      	strh	r3, [r7, #22]
+  /* bail out if no entry could be found */
+  if (i < 0) {
+ 801f1f8:	f9b7 3016 	ldrsh.w	r3, [r7, #22]
+ 801f1fc:	2b00      	cmp	r3, #0
+ 801f1fe:	da02      	bge.n	801f206 <etharp_update_arp_entry+0x76>
+    return (err_t)i;
+ 801f200:	8afb      	ldrh	r3, [r7, #22]
+ 801f202:	b25b      	sxtb	r3, r3
+ 801f204:	e05d      	b.n	801f2c2 <etharp_update_arp_entry+0x132>
+    return ERR_VAL;
+  } else
+#endif /* ETHARP_SUPPORT_STATIC_ENTRIES */
+  {
+    /* mark it stable */
+    arp_table[i].state = ETHARP_STATE_STABLE;
+ 801f206:	f9b7 2016 	ldrsh.w	r2, [r7, #22]
+ 801f20a:	4933      	ldr	r1, [pc, #204]	; (801f2d8 <etharp_update_arp_entry+0x148>)
+ 801f20c:	4613      	mov	r3, r2
+ 801f20e:	005b      	lsls	r3, r3, #1
+ 801f210:	4413      	add	r3, r2
+ 801f212:	00db      	lsls	r3, r3, #3
+ 801f214:	440b      	add	r3, r1
+ 801f216:	3314      	adds	r3, #20
+ 801f218:	2202      	movs	r2, #2
+ 801f21a:	701a      	strb	r2, [r3, #0]
+  }
+
+  /* record network interface */
+  arp_table[i].netif = netif;
+ 801f21c:	f9b7 2016 	ldrsh.w	r2, [r7, #22]
+ 801f220:	492d      	ldr	r1, [pc, #180]	; (801f2d8 <etharp_update_arp_entry+0x148>)
+ 801f222:	4613      	mov	r3, r2
+ 801f224:	005b      	lsls	r3, r3, #1
+ 801f226:	4413      	add	r3, r2
+ 801f228:	00db      	lsls	r3, r3, #3
+ 801f22a:	440b      	add	r3, r1
+ 801f22c:	3308      	adds	r3, #8
+ 801f22e:	68fa      	ldr	r2, [r7, #12]
+ 801f230:	601a      	str	r2, [r3, #0]
+  /* insert in SNMP ARP index tree */
+  mib2_add_arp_entry(netif, &arp_table[i].ipaddr);
+
+  LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_update_arp_entry: updating stable entry %"S16_F"\n", i));
+  /* update address */
+  SMEMCPY(&arp_table[i].ethaddr, ethaddr, ETH_HWADDR_LEN);
+ 801f232:	f9b7 2016 	ldrsh.w	r2, [r7, #22]
+ 801f236:	4613      	mov	r3, r2
+ 801f238:	005b      	lsls	r3, r3, #1
+ 801f23a:	4413      	add	r3, r2
+ 801f23c:	00db      	lsls	r3, r3, #3
+ 801f23e:	3308      	adds	r3, #8
+ 801f240:	4a25      	ldr	r2, [pc, #148]	; (801f2d8 <etharp_update_arp_entry+0x148>)
+ 801f242:	4413      	add	r3, r2
+ 801f244:	3304      	adds	r3, #4
+ 801f246:	2206      	movs	r2, #6
+ 801f248:	6879      	ldr	r1, [r7, #4]
+ 801f24a:	4618      	mov	r0, r3
+ 801f24c:	f002 fdcb 	bl	8021de6 <memcpy>
+  /* reset time stamp */
+  arp_table[i].ctime = 0;
+ 801f250:	f9b7 2016 	ldrsh.w	r2, [r7, #22]
+ 801f254:	4920      	ldr	r1, [pc, #128]	; (801f2d8 <etharp_update_arp_entry+0x148>)
+ 801f256:	4613      	mov	r3, r2
+ 801f258:	005b      	lsls	r3, r3, #1
+ 801f25a:	4413      	add	r3, r2
+ 801f25c:	00db      	lsls	r3, r3, #3
+ 801f25e:	440b      	add	r3, r1
+ 801f260:	3312      	adds	r3, #18
+ 801f262:	2200      	movs	r2, #0
+ 801f264:	801a      	strh	r2, [r3, #0]
+    /* get the packet pointer */
+    p = q->p;
+    /* now queue entry can be freed */
+    memp_free(MEMP_ARP_QUEUE, q);
+#else /* ARP_QUEUEING */
+  if (arp_table[i].q != NULL) {
+ 801f266:	f9b7 2016 	ldrsh.w	r2, [r7, #22]
+ 801f26a:	491b      	ldr	r1, [pc, #108]	; (801f2d8 <etharp_update_arp_entry+0x148>)
+ 801f26c:	4613      	mov	r3, r2
+ 801f26e:	005b      	lsls	r3, r3, #1
+ 801f270:	4413      	add	r3, r2
+ 801f272:	00db      	lsls	r3, r3, #3
+ 801f274:	440b      	add	r3, r1
+ 801f276:	681b      	ldr	r3, [r3, #0]
+ 801f278:	2b00      	cmp	r3, #0
+ 801f27a:	d021      	beq.n	801f2c0 <etharp_update_arp_entry+0x130>
+    struct pbuf *p = arp_table[i].q;
+ 801f27c:	f9b7 2016 	ldrsh.w	r2, [r7, #22]
+ 801f280:	4915      	ldr	r1, [pc, #84]	; (801f2d8 <etharp_update_arp_entry+0x148>)
+ 801f282:	4613      	mov	r3, r2
+ 801f284:	005b      	lsls	r3, r3, #1
+ 801f286:	4413      	add	r3, r2
+ 801f288:	00db      	lsls	r3, r3, #3
+ 801f28a:	440b      	add	r3, r1
+ 801f28c:	681b      	ldr	r3, [r3, #0]
+ 801f28e:	613b      	str	r3, [r7, #16]
+    arp_table[i].q = NULL;
+ 801f290:	f9b7 2016 	ldrsh.w	r2, [r7, #22]
+ 801f294:	4910      	ldr	r1, [pc, #64]	; (801f2d8 <etharp_update_arp_entry+0x148>)
+ 801f296:	4613      	mov	r3, r2
+ 801f298:	005b      	lsls	r3, r3, #1
+ 801f29a:	4413      	add	r3, r2
+ 801f29c:	00db      	lsls	r3, r3, #3
+ 801f29e:	440b      	add	r3, r1
+ 801f2a0:	2200      	movs	r2, #0
+ 801f2a2:	601a      	str	r2, [r3, #0]
+#endif /* ARP_QUEUEING */
+    /* send the queued IP packet */
+    ethernet_output(netif, p, (struct eth_addr *)(netif->hwaddr), ethaddr, ETHTYPE_IP);
+ 801f2a4:	68fb      	ldr	r3, [r7, #12]
+ 801f2a6:	f103 0226 	add.w	r2, r3, #38	; 0x26
+ 801f2aa:	f44f 6300 	mov.w	r3, #2048	; 0x800
+ 801f2ae:	9300      	str	r3, [sp, #0]
+ 801f2b0:	687b      	ldr	r3, [r7, #4]
+ 801f2b2:	6939      	ldr	r1, [r7, #16]
+ 801f2b4:	68f8      	ldr	r0, [r7, #12]
+ 801f2b6:	f001 ffc1 	bl	802123c <ethernet_output>
+    /* free the queued IP packet */
+    pbuf_free(p);
+ 801f2ba:	6938      	ldr	r0, [r7, #16]
+ 801f2bc:	f7f8 fc1c 	bl	8017af8 <pbuf_free>
+  }
+  return ERR_OK;
+ 801f2c0:	2300      	movs	r3, #0
+}
+ 801f2c2:	4618      	mov	r0, r3
+ 801f2c4:	3718      	adds	r7, #24
+ 801f2c6:	46bd      	mov	sp, r7
+ 801f2c8:	bd80      	pop	{r7, pc}
+ 801f2ca:	bf00      	nop
+ 801f2cc:	0802647c 	.word	0x0802647c
+ 801f2d0:	08026574 	.word	0x08026574
+ 801f2d4:	080264f4 	.word	0x080264f4
+ 801f2d8:	2401a4e4 	.word	0x2401a4e4
+
+0801f2dc <etharp_cleanup_netif>:
+ *
+ * @param netif points to a network interface
+ */
+void
+etharp_cleanup_netif(struct netif *netif)
+{
+ 801f2dc:	b580      	push	{r7, lr}
+ 801f2de:	b084      	sub	sp, #16
+ 801f2e0:	af00      	add	r7, sp, #0
+ 801f2e2:	6078      	str	r0, [r7, #4]
+  int i;
+
+  for (i = 0; i < ARP_TABLE_SIZE; ++i) {
+ 801f2e4:	2300      	movs	r3, #0
+ 801f2e6:	60fb      	str	r3, [r7, #12]
+ 801f2e8:	e01e      	b.n	801f328 <etharp_cleanup_netif+0x4c>
+    u8_t state = arp_table[i].state;
+ 801f2ea:	4913      	ldr	r1, [pc, #76]	; (801f338 <etharp_cleanup_netif+0x5c>)
+ 801f2ec:	68fa      	ldr	r2, [r7, #12]
+ 801f2ee:	4613      	mov	r3, r2
+ 801f2f0:	005b      	lsls	r3, r3, #1
+ 801f2f2:	4413      	add	r3, r2
+ 801f2f4:	00db      	lsls	r3, r3, #3
+ 801f2f6:	440b      	add	r3, r1
+ 801f2f8:	3314      	adds	r3, #20
+ 801f2fa:	781b      	ldrb	r3, [r3, #0]
+ 801f2fc:	72fb      	strb	r3, [r7, #11]
+    if ((state != ETHARP_STATE_EMPTY) && (arp_table[i].netif == netif)) {
+ 801f2fe:	7afb      	ldrb	r3, [r7, #11]
+ 801f300:	2b00      	cmp	r3, #0
+ 801f302:	d00e      	beq.n	801f322 <etharp_cleanup_netif+0x46>
+ 801f304:	490c      	ldr	r1, [pc, #48]	; (801f338 <etharp_cleanup_netif+0x5c>)
+ 801f306:	68fa      	ldr	r2, [r7, #12]
+ 801f308:	4613      	mov	r3, r2
+ 801f30a:	005b      	lsls	r3, r3, #1
+ 801f30c:	4413      	add	r3, r2
+ 801f30e:	00db      	lsls	r3, r3, #3
+ 801f310:	440b      	add	r3, r1
+ 801f312:	3308      	adds	r3, #8
+ 801f314:	681b      	ldr	r3, [r3, #0]
+ 801f316:	687a      	ldr	r2, [r7, #4]
+ 801f318:	429a      	cmp	r2, r3
+ 801f31a:	d102      	bne.n	801f322 <etharp_cleanup_netif+0x46>
+      etharp_free_entry(i);
+ 801f31c:	68f8      	ldr	r0, [r7, #12]
+ 801f31e:	f7ff fcb7 	bl	801ec90 <etharp_free_entry>
+  for (i = 0; i < ARP_TABLE_SIZE; ++i) {
+ 801f322:	68fb      	ldr	r3, [r7, #12]
+ 801f324:	3301      	adds	r3, #1
+ 801f326:	60fb      	str	r3, [r7, #12]
+ 801f328:	68fb      	ldr	r3, [r7, #12]
+ 801f32a:	2b09      	cmp	r3, #9
+ 801f32c:	dddd      	ble.n	801f2ea <etharp_cleanup_netif+0xe>
+    }
+  }
+}
+ 801f32e:	bf00      	nop
+ 801f330:	bf00      	nop
+ 801f332:	3710      	adds	r7, #16
+ 801f334:	46bd      	mov	sp, r7
+ 801f336:	bd80      	pop	{r7, pc}
+ 801f338:	2401a4e4 	.word	0x2401a4e4
+
+0801f33c <etharp_input>:
+ *
+ * @see pbuf_free()
+ */
+void
+etharp_input(struct pbuf *p, struct netif *netif)
+{
+ 801f33c:	b5b0      	push	{r4, r5, r7, lr}
+ 801f33e:	b08a      	sub	sp, #40	; 0x28
+ 801f340:	af04      	add	r7, sp, #16
+ 801f342:	6078      	str	r0, [r7, #4]
+ 801f344:	6039      	str	r1, [r7, #0]
+  ip4_addr_t sipaddr, dipaddr;
+  u8_t for_us;
+
+  LWIP_ASSERT_CORE_LOCKED();
+
+  LWIP_ERROR("netif != NULL", (netif != NULL), return;);
+ 801f346:	683b      	ldr	r3, [r7, #0]
+ 801f348:	2b00      	cmp	r3, #0
+ 801f34a:	d107      	bne.n	801f35c <etharp_input+0x20>
+ 801f34c:	4b3d      	ldr	r3, [pc, #244]	; (801f444 <etharp_input+0x108>)
+ 801f34e:	f240 228a 	movw	r2, #650	; 0x28a
+ 801f352:	493d      	ldr	r1, [pc, #244]	; (801f448 <etharp_input+0x10c>)
+ 801f354:	483d      	ldr	r0, [pc, #244]	; (801f44c <etharp_input+0x110>)
+ 801f356:	f002 fb17 	bl	8021988 <iprintf>
+ 801f35a:	e06f      	b.n	801f43c <etharp_input+0x100>
+
+  hdr = (struct etharp_hdr *)p->payload;
+ 801f35c:	687b      	ldr	r3, [r7, #4]
+ 801f35e:	685b      	ldr	r3, [r3, #4]
+ 801f360:	617b      	str	r3, [r7, #20]
+
+  /* RFC 826 "Packet Reception": */
+  if ((hdr->hwtype != PP_HTONS(LWIP_IANA_HWTYPE_ETHERNET)) ||
+ 801f362:	697b      	ldr	r3, [r7, #20]
+ 801f364:	881b      	ldrh	r3, [r3, #0]
+ 801f366:	b29b      	uxth	r3, r3
+ 801f368:	f5b3 7f80 	cmp.w	r3, #256	; 0x100
+ 801f36c:	d10c      	bne.n	801f388 <etharp_input+0x4c>
+      (hdr->hwlen != ETH_HWADDR_LEN) ||
+ 801f36e:	697b      	ldr	r3, [r7, #20]
+ 801f370:	791b      	ldrb	r3, [r3, #4]
+  if ((hdr->hwtype != PP_HTONS(LWIP_IANA_HWTYPE_ETHERNET)) ||
+ 801f372:	2b06      	cmp	r3, #6
+ 801f374:	d108      	bne.n	801f388 <etharp_input+0x4c>
+      (hdr->protolen != sizeof(ip4_addr_t)) ||
+ 801f376:	697b      	ldr	r3, [r7, #20]
+ 801f378:	795b      	ldrb	r3, [r3, #5]
+      (hdr->hwlen != ETH_HWADDR_LEN) ||
+ 801f37a:	2b04      	cmp	r3, #4
+ 801f37c:	d104      	bne.n	801f388 <etharp_input+0x4c>
+      (hdr->proto != PP_HTONS(ETHTYPE_IP)))  {
+ 801f37e:	697b      	ldr	r3, [r7, #20]
+ 801f380:	885b      	ldrh	r3, [r3, #2]
+ 801f382:	b29b      	uxth	r3, r3
+      (hdr->protolen != sizeof(ip4_addr_t)) ||
+ 801f384:	2b08      	cmp	r3, #8
+ 801f386:	d003      	beq.n	801f390 <etharp_input+0x54>
+    LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_WARNING,
+                ("etharp_input: packet dropped, wrong hw type, hwlen, proto, protolen or ethernet type (%"U16_F"/%"U16_F"/%"U16_F"/%"U16_F")\n",
+                 hdr->hwtype, (u16_t)hdr->hwlen, hdr->proto, (u16_t)hdr->protolen));
+    ETHARP_STATS_INC(etharp.proterr);
+    ETHARP_STATS_INC(etharp.drop);
+    pbuf_free(p);
+ 801f388:	6878      	ldr	r0, [r7, #4]
+ 801f38a:	f7f8 fbb5 	bl	8017af8 <pbuf_free>
+    return;
+ 801f38e:	e055      	b.n	801f43c <etharp_input+0x100>
+  autoip_arp_reply(netif, hdr);
+#endif /* LWIP_AUTOIP */
+
+  /* Copy struct ip4_addr_wordaligned to aligned ip4_addr, to support compilers without
+   * structure packing (not using structure copy which breaks strict-aliasing rules). */
+  IPADDR_WORDALIGNED_COPY_TO_IP4_ADDR_T(&sipaddr, &hdr->sipaddr);
+ 801f390:	697b      	ldr	r3, [r7, #20]
+ 801f392:	330e      	adds	r3, #14
+ 801f394:	681b      	ldr	r3, [r3, #0]
+ 801f396:	60fb      	str	r3, [r7, #12]
+  IPADDR_WORDALIGNED_COPY_TO_IP4_ADDR_T(&dipaddr, &hdr->dipaddr);
+ 801f398:	697b      	ldr	r3, [r7, #20]
+ 801f39a:	3318      	adds	r3, #24
+ 801f39c:	681b      	ldr	r3, [r3, #0]
+ 801f39e:	60bb      	str	r3, [r7, #8]
+
+  /* this interface is not configured? */
+  if (ip4_addr_isany_val(*netif_ip4_addr(netif))) {
+ 801f3a0:	683b      	ldr	r3, [r7, #0]
+ 801f3a2:	3304      	adds	r3, #4
+ 801f3a4:	681b      	ldr	r3, [r3, #0]
+ 801f3a6:	2b00      	cmp	r3, #0
+ 801f3a8:	d102      	bne.n	801f3b0 <etharp_input+0x74>
+    for_us = 0;
+ 801f3aa:	2300      	movs	r3, #0
+ 801f3ac:	74fb      	strb	r3, [r7, #19]
+ 801f3ae:	e009      	b.n	801f3c4 <etharp_input+0x88>
+  } else {
+    /* ARP packet directed to us? */
+    for_us = (u8_t)ip4_addr_cmp(&dipaddr, netif_ip4_addr(netif));
+ 801f3b0:	68ba      	ldr	r2, [r7, #8]
+ 801f3b2:	683b      	ldr	r3, [r7, #0]
+ 801f3b4:	3304      	adds	r3, #4
+ 801f3b6:	681b      	ldr	r3, [r3, #0]
+ 801f3b8:	429a      	cmp	r2, r3
+ 801f3ba:	bf0c      	ite	eq
+ 801f3bc:	2301      	moveq	r3, #1
+ 801f3be:	2300      	movne	r3, #0
+ 801f3c0:	b2db      	uxtb	r3, r3
+ 801f3c2:	74fb      	strb	r3, [r7, #19]
+  /* ARP message directed to us?
+      -> add IP address in ARP cache; assume requester wants to talk to us,
+         can result in directly sending the queued packets for this host.
+     ARP message not directed to us?
+      ->  update the source IP address in the cache, if present */
+  etharp_update_arp_entry(netif, &sipaddr, &(hdr->shwaddr),
+ 801f3c4:	697b      	ldr	r3, [r7, #20]
+ 801f3c6:	f103 0208 	add.w	r2, r3, #8
+ 801f3ca:	7cfb      	ldrb	r3, [r7, #19]
+ 801f3cc:	2b00      	cmp	r3, #0
+ 801f3ce:	d001      	beq.n	801f3d4 <etharp_input+0x98>
+ 801f3d0:	2301      	movs	r3, #1
+ 801f3d2:	e000      	b.n	801f3d6 <etharp_input+0x9a>
+ 801f3d4:	2302      	movs	r3, #2
+ 801f3d6:	f107 010c 	add.w	r1, r7, #12
+ 801f3da:	6838      	ldr	r0, [r7, #0]
+ 801f3dc:	f7ff fed8 	bl	801f190 <etharp_update_arp_entry>
+                          for_us ? ETHARP_FLAG_TRY_HARD : ETHARP_FLAG_FIND_ONLY);
+
+  /* now act on the message itself */
+  switch (hdr->opcode) {
+ 801f3e0:	697b      	ldr	r3, [r7, #20]
+ 801f3e2:	88db      	ldrh	r3, [r3, #6]
+ 801f3e4:	b29b      	uxth	r3, r3
+ 801f3e6:	f5b3 7f80 	cmp.w	r3, #256	; 0x100
+ 801f3ea:	d003      	beq.n	801f3f4 <etharp_input+0xb8>
+ 801f3ec:	f5b3 7f00 	cmp.w	r3, #512	; 0x200
+ 801f3f0:	d01e      	beq.n	801f430 <etharp_input+0xf4>
+#endif /* (LWIP_DHCP && DHCP_DOES_ARP_CHECK) */
+      break;
+    default:
+      LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_input: ARP unknown opcode type %"S16_F"\n", lwip_htons(hdr->opcode)));
+      ETHARP_STATS_INC(etharp.err);
+      break;
+ 801f3f2:	e020      	b.n	801f436 <etharp_input+0xfa>
+      if (for_us) {
+ 801f3f4:	7cfb      	ldrb	r3, [r7, #19]
+ 801f3f6:	2b00      	cmp	r3, #0
+ 801f3f8:	d01c      	beq.n	801f434 <etharp_input+0xf8>
+                   (struct eth_addr *)netif->hwaddr, &hdr->shwaddr,
+ 801f3fa:	683b      	ldr	r3, [r7, #0]
+ 801f3fc:	f103 0026 	add.w	r0, r3, #38	; 0x26
+ 801f400:	697b      	ldr	r3, [r7, #20]
+ 801f402:	f103 0408 	add.w	r4, r3, #8
+                   (struct eth_addr *)netif->hwaddr, netif_ip4_addr(netif),
+ 801f406:	683b      	ldr	r3, [r7, #0]
+ 801f408:	f103 0526 	add.w	r5, r3, #38	; 0x26
+ 801f40c:	683b      	ldr	r3, [r7, #0]
+ 801f40e:	3304      	adds	r3, #4
+                   &hdr->shwaddr, &sipaddr,
+ 801f410:	697a      	ldr	r2, [r7, #20]
+ 801f412:	3208      	adds	r2, #8
+        etharp_raw(netif,
+ 801f414:	2102      	movs	r1, #2
+ 801f416:	9103      	str	r1, [sp, #12]
+ 801f418:	f107 010c 	add.w	r1, r7, #12
+ 801f41c:	9102      	str	r1, [sp, #8]
+ 801f41e:	9201      	str	r2, [sp, #4]
+ 801f420:	9300      	str	r3, [sp, #0]
+ 801f422:	462b      	mov	r3, r5
+ 801f424:	4622      	mov	r2, r4
+ 801f426:	4601      	mov	r1, r0
+ 801f428:	6838      	ldr	r0, [r7, #0]
+ 801f42a:	f000 faeb 	bl	801fa04 <etharp_raw>
+      break;
+ 801f42e:	e001      	b.n	801f434 <etharp_input+0xf8>
+      break;
+ 801f430:	bf00      	nop
+ 801f432:	e000      	b.n	801f436 <etharp_input+0xfa>
+      break;
+ 801f434:	bf00      	nop
+  }
+  /* free ARP packet */
+  pbuf_free(p);
+ 801f436:	6878      	ldr	r0, [r7, #4]
+ 801f438:	f7f8 fb5e 	bl	8017af8 <pbuf_free>
+}
+ 801f43c:	3718      	adds	r7, #24
+ 801f43e:	46bd      	mov	sp, r7
+ 801f440:	bdb0      	pop	{r4, r5, r7, pc}
+ 801f442:	bf00      	nop
+ 801f444:	0802647c 	.word	0x0802647c
+ 801f448:	080265cc 	.word	0x080265cc
+ 801f44c:	080264f4 	.word	0x080264f4
+
+0801f450 <etharp_output_to_arp_index>:
+/** Just a small helper function that sends a pbuf to an ethernet address
+ * in the arp_table specified by the index 'arp_idx'.
+ */
+static err_t
+etharp_output_to_arp_index(struct netif *netif, struct pbuf *q, netif_addr_idx_t arp_idx)
+{
+ 801f450:	b580      	push	{r7, lr}
+ 801f452:	b086      	sub	sp, #24
+ 801f454:	af02      	add	r7, sp, #8
+ 801f456:	60f8      	str	r0, [r7, #12]
+ 801f458:	60b9      	str	r1, [r7, #8]
+ 801f45a:	4613      	mov	r3, r2
+ 801f45c:	71fb      	strb	r3, [r7, #7]
+  LWIP_ASSERT("arp_table[arp_idx].state >= ETHARP_STATE_STABLE",
+ 801f45e:	79fa      	ldrb	r2, [r7, #7]
+ 801f460:	4944      	ldr	r1, [pc, #272]	; (801f574 <etharp_output_to_arp_index+0x124>)
+ 801f462:	4613      	mov	r3, r2
+ 801f464:	005b      	lsls	r3, r3, #1
+ 801f466:	4413      	add	r3, r2
+ 801f468:	00db      	lsls	r3, r3, #3
+ 801f46a:	440b      	add	r3, r1
+ 801f46c:	3314      	adds	r3, #20
+ 801f46e:	781b      	ldrb	r3, [r3, #0]
+ 801f470:	2b01      	cmp	r3, #1
+ 801f472:	d806      	bhi.n	801f482 <etharp_output_to_arp_index+0x32>
+ 801f474:	4b40      	ldr	r3, [pc, #256]	; (801f578 <etharp_output_to_arp_index+0x128>)
+ 801f476:	f240 22ee 	movw	r2, #750	; 0x2ee
+ 801f47a:	4940      	ldr	r1, [pc, #256]	; (801f57c <etharp_output_to_arp_index+0x12c>)
+ 801f47c:	4840      	ldr	r0, [pc, #256]	; (801f580 <etharp_output_to_arp_index+0x130>)
+ 801f47e:	f002 fa83 	bl	8021988 <iprintf>
+              arp_table[arp_idx].state >= ETHARP_STATE_STABLE);
+  /* if arp table entry is about to expire: re-request it,
+     but only if its state is ETHARP_STATE_STABLE to prevent flooding the
+     network with ARP requests if this address is used frequently. */
+  if (arp_table[arp_idx].state == ETHARP_STATE_STABLE) {
+ 801f482:	79fa      	ldrb	r2, [r7, #7]
+ 801f484:	493b      	ldr	r1, [pc, #236]	; (801f574 <etharp_output_to_arp_index+0x124>)
+ 801f486:	4613      	mov	r3, r2
+ 801f488:	005b      	lsls	r3, r3, #1
+ 801f48a:	4413      	add	r3, r2
+ 801f48c:	00db      	lsls	r3, r3, #3
+ 801f48e:	440b      	add	r3, r1
+ 801f490:	3314      	adds	r3, #20
+ 801f492:	781b      	ldrb	r3, [r3, #0]
+ 801f494:	2b02      	cmp	r3, #2
+ 801f496:	d153      	bne.n	801f540 <etharp_output_to_arp_index+0xf0>
+    if (arp_table[arp_idx].ctime >= ARP_AGE_REREQUEST_USED_BROADCAST) {
+ 801f498:	79fa      	ldrb	r2, [r7, #7]
+ 801f49a:	4936      	ldr	r1, [pc, #216]	; (801f574 <etharp_output_to_arp_index+0x124>)
+ 801f49c:	4613      	mov	r3, r2
+ 801f49e:	005b      	lsls	r3, r3, #1
+ 801f4a0:	4413      	add	r3, r2
+ 801f4a2:	00db      	lsls	r3, r3, #3
+ 801f4a4:	440b      	add	r3, r1
+ 801f4a6:	3312      	adds	r3, #18
+ 801f4a8:	881b      	ldrh	r3, [r3, #0]
+ 801f4aa:	f5b3 7f8e 	cmp.w	r3, #284	; 0x11c
+ 801f4ae:	d919      	bls.n	801f4e4 <etharp_output_to_arp_index+0x94>
+      /* issue a standard request using broadcast */
+      if (etharp_request(netif, &arp_table[arp_idx].ipaddr) == ERR_OK) {
+ 801f4b0:	79fa      	ldrb	r2, [r7, #7]
+ 801f4b2:	4613      	mov	r3, r2
+ 801f4b4:	005b      	lsls	r3, r3, #1
+ 801f4b6:	4413      	add	r3, r2
+ 801f4b8:	00db      	lsls	r3, r3, #3
+ 801f4ba:	4a2e      	ldr	r2, [pc, #184]	; (801f574 <etharp_output_to_arp_index+0x124>)
+ 801f4bc:	4413      	add	r3, r2
+ 801f4be:	3304      	adds	r3, #4
+ 801f4c0:	4619      	mov	r1, r3
+ 801f4c2:	68f8      	ldr	r0, [r7, #12]
+ 801f4c4:	f000 fb4c 	bl	801fb60 <etharp_request>
+ 801f4c8:	4603      	mov	r3, r0
+ 801f4ca:	2b00      	cmp	r3, #0
+ 801f4cc:	d138      	bne.n	801f540 <etharp_output_to_arp_index+0xf0>
+        arp_table[arp_idx].state = ETHARP_STATE_STABLE_REREQUESTING_1;
+ 801f4ce:	79fa      	ldrb	r2, [r7, #7]
+ 801f4d0:	4928      	ldr	r1, [pc, #160]	; (801f574 <etharp_output_to_arp_index+0x124>)
+ 801f4d2:	4613      	mov	r3, r2
+ 801f4d4:	005b      	lsls	r3, r3, #1
+ 801f4d6:	4413      	add	r3, r2
+ 801f4d8:	00db      	lsls	r3, r3, #3
+ 801f4da:	440b      	add	r3, r1
+ 801f4dc:	3314      	adds	r3, #20
+ 801f4de:	2203      	movs	r2, #3
+ 801f4e0:	701a      	strb	r2, [r3, #0]
+ 801f4e2:	e02d      	b.n	801f540 <etharp_output_to_arp_index+0xf0>
+      }
+    } else if (arp_table[arp_idx].ctime >= ARP_AGE_REREQUEST_USED_UNICAST) {
+ 801f4e4:	79fa      	ldrb	r2, [r7, #7]
+ 801f4e6:	4923      	ldr	r1, [pc, #140]	; (801f574 <etharp_output_to_arp_index+0x124>)
+ 801f4e8:	4613      	mov	r3, r2
+ 801f4ea:	005b      	lsls	r3, r3, #1
+ 801f4ec:	4413      	add	r3, r2
+ 801f4ee:	00db      	lsls	r3, r3, #3
+ 801f4f0:	440b      	add	r3, r1
+ 801f4f2:	3312      	adds	r3, #18
+ 801f4f4:	881b      	ldrh	r3, [r3, #0]
+ 801f4f6:	f5b3 7f87 	cmp.w	r3, #270	; 0x10e
+ 801f4fa:	d321      	bcc.n	801f540 <etharp_output_to_arp_index+0xf0>
+      /* issue a unicast request (for 15 seconds) to prevent unnecessary broadcast */
+      if (etharp_request_dst(netif, &arp_table[arp_idx].ipaddr, &arp_table[arp_idx].ethaddr) == ERR_OK) {
+ 801f4fc:	79fa      	ldrb	r2, [r7, #7]
+ 801f4fe:	4613      	mov	r3, r2
+ 801f500:	005b      	lsls	r3, r3, #1
+ 801f502:	4413      	add	r3, r2
+ 801f504:	00db      	lsls	r3, r3, #3
+ 801f506:	4a1b      	ldr	r2, [pc, #108]	; (801f574 <etharp_output_to_arp_index+0x124>)
+ 801f508:	4413      	add	r3, r2
+ 801f50a:	1d19      	adds	r1, r3, #4
+ 801f50c:	79fa      	ldrb	r2, [r7, #7]
+ 801f50e:	4613      	mov	r3, r2
+ 801f510:	005b      	lsls	r3, r3, #1
+ 801f512:	4413      	add	r3, r2
+ 801f514:	00db      	lsls	r3, r3, #3
+ 801f516:	3308      	adds	r3, #8
+ 801f518:	4a16      	ldr	r2, [pc, #88]	; (801f574 <etharp_output_to_arp_index+0x124>)
+ 801f51a:	4413      	add	r3, r2
+ 801f51c:	3304      	adds	r3, #4
+ 801f51e:	461a      	mov	r2, r3
+ 801f520:	68f8      	ldr	r0, [r7, #12]
+ 801f522:	f000 fafb 	bl	801fb1c <etharp_request_dst>
+ 801f526:	4603      	mov	r3, r0
+ 801f528:	2b00      	cmp	r3, #0
+ 801f52a:	d109      	bne.n	801f540 <etharp_output_to_arp_index+0xf0>
+        arp_table[arp_idx].state = ETHARP_STATE_STABLE_REREQUESTING_1;
+ 801f52c:	79fa      	ldrb	r2, [r7, #7]
+ 801f52e:	4911      	ldr	r1, [pc, #68]	; (801f574 <etharp_output_to_arp_index+0x124>)
+ 801f530:	4613      	mov	r3, r2
+ 801f532:	005b      	lsls	r3, r3, #1
+ 801f534:	4413      	add	r3, r2
+ 801f536:	00db      	lsls	r3, r3, #3
+ 801f538:	440b      	add	r3, r1
+ 801f53a:	3314      	adds	r3, #20
+ 801f53c:	2203      	movs	r2, #3
+ 801f53e:	701a      	strb	r2, [r3, #0]
+      }
+    }
+  }
+
+  return ethernet_output(netif, q, (struct eth_addr *)(netif->hwaddr), &arp_table[arp_idx].ethaddr, ETHTYPE_IP);
+ 801f540:	68fb      	ldr	r3, [r7, #12]
+ 801f542:	f103 0126 	add.w	r1, r3, #38	; 0x26
+ 801f546:	79fa      	ldrb	r2, [r7, #7]
+ 801f548:	4613      	mov	r3, r2
+ 801f54a:	005b      	lsls	r3, r3, #1
+ 801f54c:	4413      	add	r3, r2
+ 801f54e:	00db      	lsls	r3, r3, #3
+ 801f550:	3308      	adds	r3, #8
+ 801f552:	4a08      	ldr	r2, [pc, #32]	; (801f574 <etharp_output_to_arp_index+0x124>)
+ 801f554:	4413      	add	r3, r2
+ 801f556:	3304      	adds	r3, #4
+ 801f558:	f44f 6200 	mov.w	r2, #2048	; 0x800
+ 801f55c:	9200      	str	r2, [sp, #0]
+ 801f55e:	460a      	mov	r2, r1
+ 801f560:	68b9      	ldr	r1, [r7, #8]
+ 801f562:	68f8      	ldr	r0, [r7, #12]
+ 801f564:	f001 fe6a 	bl	802123c <ethernet_output>
+ 801f568:	4603      	mov	r3, r0
+}
+ 801f56a:	4618      	mov	r0, r3
+ 801f56c:	3710      	adds	r7, #16
+ 801f56e:	46bd      	mov	sp, r7
+ 801f570:	bd80      	pop	{r7, pc}
+ 801f572:	bf00      	nop
+ 801f574:	2401a4e4 	.word	0x2401a4e4
+ 801f578:	0802647c 	.word	0x0802647c
+ 801f57c:	080265ec 	.word	0x080265ec
+ 801f580:	080264f4 	.word	0x080264f4
+
+0801f584 <etharp_output>:
+ * - ERR_RTE No route to destination (no gateway to external networks),
+ * or the return type of either etharp_query() or ethernet_output().
+ */
+err_t
+etharp_output(struct netif *netif, struct pbuf *q, const ip4_addr_t *ipaddr)
+{
+ 801f584:	b580      	push	{r7, lr}
+ 801f586:	b08a      	sub	sp, #40	; 0x28
+ 801f588:	af02      	add	r7, sp, #8
+ 801f58a:	60f8      	str	r0, [r7, #12]
+ 801f58c:	60b9      	str	r1, [r7, #8]
+ 801f58e:	607a      	str	r2, [r7, #4]
+  const struct eth_addr *dest;
+  struct eth_addr mcastaddr;
+  const ip4_addr_t *dst_addr = ipaddr;
+ 801f590:	687b      	ldr	r3, [r7, #4]
+ 801f592:	61bb      	str	r3, [r7, #24]
+
+  LWIP_ASSERT_CORE_LOCKED();
+  LWIP_ASSERT("netif != NULL", netif != NULL);
+ 801f594:	68fb      	ldr	r3, [r7, #12]
+ 801f596:	2b00      	cmp	r3, #0
+ 801f598:	d106      	bne.n	801f5a8 <etharp_output+0x24>
+ 801f59a:	4b73      	ldr	r3, [pc, #460]	; (801f768 <etharp_output+0x1e4>)
+ 801f59c:	f240 321e 	movw	r2, #798	; 0x31e
+ 801f5a0:	4972      	ldr	r1, [pc, #456]	; (801f76c <etharp_output+0x1e8>)
+ 801f5a2:	4873      	ldr	r0, [pc, #460]	; (801f770 <etharp_output+0x1ec>)
+ 801f5a4:	f002 f9f0 	bl	8021988 <iprintf>
+  LWIP_ASSERT("q != NULL", q != NULL);
+ 801f5a8:	68bb      	ldr	r3, [r7, #8]
+ 801f5aa:	2b00      	cmp	r3, #0
+ 801f5ac:	d106      	bne.n	801f5bc <etharp_output+0x38>
+ 801f5ae:	4b6e      	ldr	r3, [pc, #440]	; (801f768 <etharp_output+0x1e4>)
+ 801f5b0:	f240 321f 	movw	r2, #799	; 0x31f
+ 801f5b4:	496f      	ldr	r1, [pc, #444]	; (801f774 <etharp_output+0x1f0>)
+ 801f5b6:	486e      	ldr	r0, [pc, #440]	; (801f770 <etharp_output+0x1ec>)
+ 801f5b8:	f002 f9e6 	bl	8021988 <iprintf>
+  LWIP_ASSERT("ipaddr != NULL", ipaddr != NULL);
+ 801f5bc:	687b      	ldr	r3, [r7, #4]
+ 801f5be:	2b00      	cmp	r3, #0
+ 801f5c0:	d106      	bne.n	801f5d0 <etharp_output+0x4c>
+ 801f5c2:	4b69      	ldr	r3, [pc, #420]	; (801f768 <etharp_output+0x1e4>)
+ 801f5c4:	f44f 7248 	mov.w	r2, #800	; 0x320
+ 801f5c8:	496b      	ldr	r1, [pc, #428]	; (801f778 <etharp_output+0x1f4>)
+ 801f5ca:	4869      	ldr	r0, [pc, #420]	; (801f770 <etharp_output+0x1ec>)
+ 801f5cc:	f002 f9dc 	bl	8021988 <iprintf>
+
+  /* Determine on destination hardware address. Broadcasts and multicasts
+   * are special, other IP addresses are looked up in the ARP table. */
+
+  /* broadcast destination IP address? */
+  if (ip4_addr_isbroadcast(ipaddr, netif)) {
+ 801f5d0:	687b      	ldr	r3, [r7, #4]
+ 801f5d2:	681b      	ldr	r3, [r3, #0]
+ 801f5d4:	68f9      	ldr	r1, [r7, #12]
+ 801f5d6:	4618      	mov	r0, r3
+ 801f5d8:	f000 ff22 	bl	8020420 <ip4_addr_isbroadcast_u32>
+ 801f5dc:	4603      	mov	r3, r0
+ 801f5de:	2b00      	cmp	r3, #0
+ 801f5e0:	d002      	beq.n	801f5e8 <etharp_output+0x64>
+    /* broadcast on Ethernet also */
+    dest = (const struct eth_addr *)&ethbroadcast;
+ 801f5e2:	4b66      	ldr	r3, [pc, #408]	; (801f77c <etharp_output+0x1f8>)
+ 801f5e4:	61fb      	str	r3, [r7, #28]
+ 801f5e6:	e0af      	b.n	801f748 <etharp_output+0x1c4>
+    /* multicast destination IP address? */
+  } else if (ip4_addr_ismulticast(ipaddr)) {
+ 801f5e8:	687b      	ldr	r3, [r7, #4]
+ 801f5ea:	681b      	ldr	r3, [r3, #0]
+ 801f5ec:	f003 03f0 	and.w	r3, r3, #240	; 0xf0
+ 801f5f0:	2be0      	cmp	r3, #224	; 0xe0
+ 801f5f2:	d118      	bne.n	801f626 <etharp_output+0xa2>
+    /* Hash IP multicast address to MAC address.*/
+    mcastaddr.addr[0] = LL_IP4_MULTICAST_ADDR_0;
+ 801f5f4:	2301      	movs	r3, #1
+ 801f5f6:	743b      	strb	r3, [r7, #16]
+    mcastaddr.addr[1] = LL_IP4_MULTICAST_ADDR_1;
+ 801f5f8:	2300      	movs	r3, #0
+ 801f5fa:	747b      	strb	r3, [r7, #17]
+    mcastaddr.addr[2] = LL_IP4_MULTICAST_ADDR_2;
+ 801f5fc:	235e      	movs	r3, #94	; 0x5e
+ 801f5fe:	74bb      	strb	r3, [r7, #18]
+    mcastaddr.addr[3] = ip4_addr2(ipaddr) & 0x7f;
+ 801f600:	687b      	ldr	r3, [r7, #4]
+ 801f602:	3301      	adds	r3, #1
+ 801f604:	781b      	ldrb	r3, [r3, #0]
+ 801f606:	f003 037f 	and.w	r3, r3, #127	; 0x7f
+ 801f60a:	b2db      	uxtb	r3, r3
+ 801f60c:	74fb      	strb	r3, [r7, #19]
+    mcastaddr.addr[4] = ip4_addr3(ipaddr);
+ 801f60e:	687b      	ldr	r3, [r7, #4]
+ 801f610:	3302      	adds	r3, #2
+ 801f612:	781b      	ldrb	r3, [r3, #0]
+ 801f614:	753b      	strb	r3, [r7, #20]
+    mcastaddr.addr[5] = ip4_addr4(ipaddr);
+ 801f616:	687b      	ldr	r3, [r7, #4]
+ 801f618:	3303      	adds	r3, #3
+ 801f61a:	781b      	ldrb	r3, [r3, #0]
+ 801f61c:	757b      	strb	r3, [r7, #21]
+    /* destination Ethernet address is multicast */
+    dest = &mcastaddr;
+ 801f61e:	f107 0310 	add.w	r3, r7, #16
+ 801f622:	61fb      	str	r3, [r7, #28]
+ 801f624:	e090      	b.n	801f748 <etharp_output+0x1c4>
+    /* unicast destination IP address? */
+  } else {
+    netif_addr_idx_t i;
+    /* outside local network? if so, this can neither be a global broadcast nor
+       a subnet broadcast. */
+    if (!ip4_addr_netcmp(ipaddr, netif_ip4_addr(netif), netif_ip4_netmask(netif)) &&
+ 801f626:	687b      	ldr	r3, [r7, #4]
+ 801f628:	681a      	ldr	r2, [r3, #0]
+ 801f62a:	68fb      	ldr	r3, [r7, #12]
+ 801f62c:	3304      	adds	r3, #4
+ 801f62e:	681b      	ldr	r3, [r3, #0]
+ 801f630:	405a      	eors	r2, r3
+ 801f632:	68fb      	ldr	r3, [r7, #12]
+ 801f634:	3308      	adds	r3, #8
+ 801f636:	681b      	ldr	r3, [r3, #0]
+ 801f638:	4013      	ands	r3, r2
+ 801f63a:	2b00      	cmp	r3, #0
+ 801f63c:	d012      	beq.n	801f664 <etharp_output+0xe0>
+        !ip4_addr_islinklocal(ipaddr)) {
+ 801f63e:	687b      	ldr	r3, [r7, #4]
+ 801f640:	681b      	ldr	r3, [r3, #0]
+ 801f642:	b29b      	uxth	r3, r3
+    if (!ip4_addr_netcmp(ipaddr, netif_ip4_addr(netif), netif_ip4_netmask(netif)) &&
+ 801f644:	f64f 62a9 	movw	r2, #65193	; 0xfea9
+ 801f648:	4293      	cmp	r3, r2
+ 801f64a:	d00b      	beq.n	801f664 <etharp_output+0xe0>
+        dst_addr = LWIP_HOOK_ETHARP_GET_GW(netif, ipaddr);
+        if (dst_addr == NULL)
+#endif /* LWIP_HOOK_ETHARP_GET_GW */
+        {
+          /* interface has default gateway? */
+          if (!ip4_addr_isany_val(*netif_ip4_gw(netif))) {
+ 801f64c:	68fb      	ldr	r3, [r7, #12]
+ 801f64e:	330c      	adds	r3, #12
+ 801f650:	681b      	ldr	r3, [r3, #0]
+ 801f652:	2b00      	cmp	r3, #0
+ 801f654:	d003      	beq.n	801f65e <etharp_output+0xda>
+            /* send to hardware address of default gateway IP address */
+            dst_addr = netif_ip4_gw(netif);
+ 801f656:	68fb      	ldr	r3, [r7, #12]
+ 801f658:	330c      	adds	r3, #12
+ 801f65a:	61bb      	str	r3, [r7, #24]
+ 801f65c:	e002      	b.n	801f664 <etharp_output+0xe0>
+            /* no default gateway available */
+          } else {
+            /* no route to destination error (default gateway missing) */
+            return ERR_RTE;
+ 801f65e:	f06f 0303 	mvn.w	r3, #3
+ 801f662:	e07d      	b.n	801f760 <etharp_output+0x1dc>
+    if (netif->hints != NULL) {
+      /* per-pcb cached entry was given */
+      netif_addr_idx_t etharp_cached_entry = netif->hints->addr_hint;
+      if (etharp_cached_entry < ARP_TABLE_SIZE) {
+#endif /* LWIP_NETIF_HWADDRHINT */
+        if ((arp_table[etharp_cached_entry].state >= ETHARP_STATE_STABLE) &&
+ 801f664:	4b46      	ldr	r3, [pc, #280]	; (801f780 <etharp_output+0x1fc>)
+ 801f666:	781b      	ldrb	r3, [r3, #0]
+ 801f668:	4619      	mov	r1, r3
+ 801f66a:	4a46      	ldr	r2, [pc, #280]	; (801f784 <etharp_output+0x200>)
+ 801f66c:	460b      	mov	r3, r1
+ 801f66e:	005b      	lsls	r3, r3, #1
+ 801f670:	440b      	add	r3, r1
+ 801f672:	00db      	lsls	r3, r3, #3
+ 801f674:	4413      	add	r3, r2
+ 801f676:	3314      	adds	r3, #20
+ 801f678:	781b      	ldrb	r3, [r3, #0]
+ 801f67a:	2b01      	cmp	r3, #1
+ 801f67c:	d925      	bls.n	801f6ca <etharp_output+0x146>
+#if ETHARP_TABLE_MATCH_NETIF
+            (arp_table[etharp_cached_entry].netif == netif) &&
+ 801f67e:	4b40      	ldr	r3, [pc, #256]	; (801f780 <etharp_output+0x1fc>)
+ 801f680:	781b      	ldrb	r3, [r3, #0]
+ 801f682:	4619      	mov	r1, r3
+ 801f684:	4a3f      	ldr	r2, [pc, #252]	; (801f784 <etharp_output+0x200>)
+ 801f686:	460b      	mov	r3, r1
+ 801f688:	005b      	lsls	r3, r3, #1
+ 801f68a:	440b      	add	r3, r1
+ 801f68c:	00db      	lsls	r3, r3, #3
+ 801f68e:	4413      	add	r3, r2
+ 801f690:	3308      	adds	r3, #8
+ 801f692:	681b      	ldr	r3, [r3, #0]
+        if ((arp_table[etharp_cached_entry].state >= ETHARP_STATE_STABLE) &&
+ 801f694:	68fa      	ldr	r2, [r7, #12]
+ 801f696:	429a      	cmp	r2, r3
+ 801f698:	d117      	bne.n	801f6ca <etharp_output+0x146>
+#endif
+            (ip4_addr_cmp(dst_addr, &arp_table[etharp_cached_entry].ipaddr))) {
+ 801f69a:	69bb      	ldr	r3, [r7, #24]
+ 801f69c:	681a      	ldr	r2, [r3, #0]
+ 801f69e:	4b38      	ldr	r3, [pc, #224]	; (801f780 <etharp_output+0x1fc>)
+ 801f6a0:	781b      	ldrb	r3, [r3, #0]
+ 801f6a2:	4618      	mov	r0, r3
+ 801f6a4:	4937      	ldr	r1, [pc, #220]	; (801f784 <etharp_output+0x200>)
+ 801f6a6:	4603      	mov	r3, r0
+ 801f6a8:	005b      	lsls	r3, r3, #1
+ 801f6aa:	4403      	add	r3, r0
+ 801f6ac:	00db      	lsls	r3, r3, #3
+ 801f6ae:	440b      	add	r3, r1
+ 801f6b0:	3304      	adds	r3, #4
+ 801f6b2:	681b      	ldr	r3, [r3, #0]
+            (arp_table[etharp_cached_entry].netif == netif) &&
+ 801f6b4:	429a      	cmp	r2, r3
+ 801f6b6:	d108      	bne.n	801f6ca <etharp_output+0x146>
+          /* the per-pcb-cached entry is stable and the right one! */
+          ETHARP_STATS_INC(etharp.cachehit);
+          return etharp_output_to_arp_index(netif, q, etharp_cached_entry);
+ 801f6b8:	4b31      	ldr	r3, [pc, #196]	; (801f780 <etharp_output+0x1fc>)
+ 801f6ba:	781b      	ldrb	r3, [r3, #0]
+ 801f6bc:	461a      	mov	r2, r3
+ 801f6be:	68b9      	ldr	r1, [r7, #8]
+ 801f6c0:	68f8      	ldr	r0, [r7, #12]
+ 801f6c2:	f7ff fec5 	bl	801f450 <etharp_output_to_arp_index>
+ 801f6c6:	4603      	mov	r3, r0
+ 801f6c8:	e04a      	b.n	801f760 <etharp_output+0x1dc>
+    }
+#endif /* LWIP_NETIF_HWADDRHINT */
+
+    /* find stable entry: do this here since this is a critical path for
+       throughput and etharp_find_entry() is kind of slow */
+    for (i = 0; i < ARP_TABLE_SIZE; i++) {
+ 801f6ca:	2300      	movs	r3, #0
+ 801f6cc:	75fb      	strb	r3, [r7, #23]
+ 801f6ce:	e031      	b.n	801f734 <etharp_output+0x1b0>
+      if ((arp_table[i].state >= ETHARP_STATE_STABLE) &&
+ 801f6d0:	7dfa      	ldrb	r2, [r7, #23]
+ 801f6d2:	492c      	ldr	r1, [pc, #176]	; (801f784 <etharp_output+0x200>)
+ 801f6d4:	4613      	mov	r3, r2
+ 801f6d6:	005b      	lsls	r3, r3, #1
+ 801f6d8:	4413      	add	r3, r2
+ 801f6da:	00db      	lsls	r3, r3, #3
+ 801f6dc:	440b      	add	r3, r1
+ 801f6de:	3314      	adds	r3, #20
+ 801f6e0:	781b      	ldrb	r3, [r3, #0]
+ 801f6e2:	2b01      	cmp	r3, #1
+ 801f6e4:	d923      	bls.n	801f72e <etharp_output+0x1aa>
+#if ETHARP_TABLE_MATCH_NETIF
+          (arp_table[i].netif == netif) &&
+ 801f6e6:	7dfa      	ldrb	r2, [r7, #23]
+ 801f6e8:	4926      	ldr	r1, [pc, #152]	; (801f784 <etharp_output+0x200>)
+ 801f6ea:	4613      	mov	r3, r2
+ 801f6ec:	005b      	lsls	r3, r3, #1
+ 801f6ee:	4413      	add	r3, r2
+ 801f6f0:	00db      	lsls	r3, r3, #3
+ 801f6f2:	440b      	add	r3, r1
+ 801f6f4:	3308      	adds	r3, #8
+ 801f6f6:	681b      	ldr	r3, [r3, #0]
+      if ((arp_table[i].state >= ETHARP_STATE_STABLE) &&
+ 801f6f8:	68fa      	ldr	r2, [r7, #12]
+ 801f6fa:	429a      	cmp	r2, r3
+ 801f6fc:	d117      	bne.n	801f72e <etharp_output+0x1aa>
+#endif
+          (ip4_addr_cmp(dst_addr, &arp_table[i].ipaddr))) {
+ 801f6fe:	69bb      	ldr	r3, [r7, #24]
+ 801f700:	6819      	ldr	r1, [r3, #0]
+ 801f702:	7dfa      	ldrb	r2, [r7, #23]
+ 801f704:	481f      	ldr	r0, [pc, #124]	; (801f784 <etharp_output+0x200>)
+ 801f706:	4613      	mov	r3, r2
+ 801f708:	005b      	lsls	r3, r3, #1
+ 801f70a:	4413      	add	r3, r2
+ 801f70c:	00db      	lsls	r3, r3, #3
+ 801f70e:	4403      	add	r3, r0
+ 801f710:	3304      	adds	r3, #4
+ 801f712:	681b      	ldr	r3, [r3, #0]
+          (arp_table[i].netif == netif) &&
+ 801f714:	4299      	cmp	r1, r3
+ 801f716:	d10a      	bne.n	801f72e <etharp_output+0x1aa>
+        /* found an existing, stable entry */
+        ETHARP_SET_ADDRHINT(netif, i);
+ 801f718:	4a19      	ldr	r2, [pc, #100]	; (801f780 <etharp_output+0x1fc>)
+ 801f71a:	7dfb      	ldrb	r3, [r7, #23]
+ 801f71c:	7013      	strb	r3, [r2, #0]
+        return etharp_output_to_arp_index(netif, q, i);
+ 801f71e:	7dfb      	ldrb	r3, [r7, #23]
+ 801f720:	461a      	mov	r2, r3
+ 801f722:	68b9      	ldr	r1, [r7, #8]
+ 801f724:	68f8      	ldr	r0, [r7, #12]
+ 801f726:	f7ff fe93 	bl	801f450 <etharp_output_to_arp_index>
+ 801f72a:	4603      	mov	r3, r0
+ 801f72c:	e018      	b.n	801f760 <etharp_output+0x1dc>
+    for (i = 0; i < ARP_TABLE_SIZE; i++) {
+ 801f72e:	7dfb      	ldrb	r3, [r7, #23]
+ 801f730:	3301      	adds	r3, #1
+ 801f732:	75fb      	strb	r3, [r7, #23]
+ 801f734:	7dfb      	ldrb	r3, [r7, #23]
+ 801f736:	2b09      	cmp	r3, #9
+ 801f738:	d9ca      	bls.n	801f6d0 <etharp_output+0x14c>
+      }
+    }
+    /* no stable entry found, use the (slower) query function:
+       queue on destination Ethernet address belonging to ipaddr */
+    return etharp_query(netif, dst_addr, q);
+ 801f73a:	68ba      	ldr	r2, [r7, #8]
+ 801f73c:	69b9      	ldr	r1, [r7, #24]
+ 801f73e:	68f8      	ldr	r0, [r7, #12]
+ 801f740:	f000 f822 	bl	801f788 <etharp_query>
+ 801f744:	4603      	mov	r3, r0
+ 801f746:	e00b      	b.n	801f760 <etharp_output+0x1dc>
+  }
+
+  /* continuation for multicast/broadcast destinations */
+  /* obtain source Ethernet address of the given interface */
+  /* send packet directly on the link */
+  return ethernet_output(netif, q, (struct eth_addr *)(netif->hwaddr), dest, ETHTYPE_IP);
+ 801f748:	68fb      	ldr	r3, [r7, #12]
+ 801f74a:	f103 0226 	add.w	r2, r3, #38	; 0x26
+ 801f74e:	f44f 6300 	mov.w	r3, #2048	; 0x800
+ 801f752:	9300      	str	r3, [sp, #0]
+ 801f754:	69fb      	ldr	r3, [r7, #28]
+ 801f756:	68b9      	ldr	r1, [r7, #8]
+ 801f758:	68f8      	ldr	r0, [r7, #12]
+ 801f75a:	f001 fd6f 	bl	802123c <ethernet_output>
+ 801f75e:	4603      	mov	r3, r0
+}
+ 801f760:	4618      	mov	r0, r3
+ 801f762:	3720      	adds	r7, #32
+ 801f764:	46bd      	mov	sp, r7
+ 801f766:	bd80      	pop	{r7, pc}
+ 801f768:	0802647c 	.word	0x0802647c
+ 801f76c:	080265cc 	.word	0x080265cc
+ 801f770:	080264f4 	.word	0x080264f4
+ 801f774:	0802661c 	.word	0x0802661c
+ 801f778:	080265bc 	.word	0x080265bc
+ 801f77c:	08026cf0 	.word	0x08026cf0
+ 801f780:	2401a5d4 	.word	0x2401a5d4
+ 801f784:	2401a4e4 	.word	0x2401a4e4
+
+0801f788 <etharp_query>:
+ * - ERR_ARG Non-unicast address given, those will not appear in ARP cache.
+ *
+ */
+err_t
+etharp_query(struct netif *netif, const ip4_addr_t *ipaddr, struct pbuf *q)
+{
+ 801f788:	b580      	push	{r7, lr}
+ 801f78a:	b08c      	sub	sp, #48	; 0x30
+ 801f78c:	af02      	add	r7, sp, #8
+ 801f78e:	60f8      	str	r0, [r7, #12]
+ 801f790:	60b9      	str	r1, [r7, #8]
+ 801f792:	607a      	str	r2, [r7, #4]
+  struct eth_addr *srcaddr = (struct eth_addr *)netif->hwaddr;
+ 801f794:	68fb      	ldr	r3, [r7, #12]
+ 801f796:	3326      	adds	r3, #38	; 0x26
+ 801f798:	617b      	str	r3, [r7, #20]
+  err_t result = ERR_MEM;
+ 801f79a:	23ff      	movs	r3, #255	; 0xff
+ 801f79c:	f887 3027 	strb.w	r3, [r7, #39]	; 0x27
+  int is_new_entry = 0;
+ 801f7a0:	2300      	movs	r3, #0
+ 801f7a2:	623b      	str	r3, [r7, #32]
+  s16_t i_err;
+  netif_addr_idx_t i;
+
+  /* non-unicast address? */
+  if (ip4_addr_isbroadcast(ipaddr, netif) ||
+ 801f7a4:	68bb      	ldr	r3, [r7, #8]
+ 801f7a6:	681b      	ldr	r3, [r3, #0]
+ 801f7a8:	68f9      	ldr	r1, [r7, #12]
+ 801f7aa:	4618      	mov	r0, r3
+ 801f7ac:	f000 fe38 	bl	8020420 <ip4_addr_isbroadcast_u32>
+ 801f7b0:	4603      	mov	r3, r0
+ 801f7b2:	2b00      	cmp	r3, #0
+ 801f7b4:	d10c      	bne.n	801f7d0 <etharp_query+0x48>
+      ip4_addr_ismulticast(ipaddr) ||
+ 801f7b6:	68bb      	ldr	r3, [r7, #8]
+ 801f7b8:	681b      	ldr	r3, [r3, #0]
+ 801f7ba:	f003 03f0 	and.w	r3, r3, #240	; 0xf0
+  if (ip4_addr_isbroadcast(ipaddr, netif) ||
+ 801f7be:	2be0      	cmp	r3, #224	; 0xe0
+ 801f7c0:	d006      	beq.n	801f7d0 <etharp_query+0x48>
+      ip4_addr_ismulticast(ipaddr) ||
+ 801f7c2:	68bb      	ldr	r3, [r7, #8]
+ 801f7c4:	2b00      	cmp	r3, #0
+ 801f7c6:	d003      	beq.n	801f7d0 <etharp_query+0x48>
+      ip4_addr_isany(ipaddr)) {
+ 801f7c8:	68bb      	ldr	r3, [r7, #8]
+ 801f7ca:	681b      	ldr	r3, [r3, #0]
+ 801f7cc:	2b00      	cmp	r3, #0
+ 801f7ce:	d102      	bne.n	801f7d6 <etharp_query+0x4e>
+    LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_query: will not add non-unicast IP address to ARP cache\n"));
+    return ERR_ARG;
+ 801f7d0:	f06f 030f 	mvn.w	r3, #15
+ 801f7d4:	e101      	b.n	801f9da <etharp_query+0x252>
+  }
+
+  /* find entry in ARP cache, ask to create entry if queueing packet */
+  i_err = etharp_find_entry(ipaddr, ETHARP_FLAG_TRY_HARD, netif);
+ 801f7d6:	68fa      	ldr	r2, [r7, #12]
+ 801f7d8:	2101      	movs	r1, #1
+ 801f7da:	68b8      	ldr	r0, [r7, #8]
+ 801f7dc:	f7ff fb60 	bl	801eea0 <etharp_find_entry>
+ 801f7e0:	4603      	mov	r3, r0
+ 801f7e2:	827b      	strh	r3, [r7, #18]
+
+  /* could not find or create entry? */
+  if (i_err < 0) {
+ 801f7e4:	f9b7 3012 	ldrsh.w	r3, [r7, #18]
+ 801f7e8:	2b00      	cmp	r3, #0
+ 801f7ea:	da02      	bge.n	801f7f2 <etharp_query+0x6a>
+    LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_query: could not create ARP entry\n"));
+    if (q) {
+      LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_query: packet dropped\n"));
+      ETHARP_STATS_INC(etharp.memerr);
+    }
+    return (err_t)i_err;
+ 801f7ec:	8a7b      	ldrh	r3, [r7, #18]
+ 801f7ee:	b25b      	sxtb	r3, r3
+ 801f7f0:	e0f3      	b.n	801f9da <etharp_query+0x252>
+  }
+  LWIP_ASSERT("type overflow", (size_t)i_err < NETIF_ADDR_IDX_MAX);
+ 801f7f2:	8a7b      	ldrh	r3, [r7, #18]
+ 801f7f4:	2b7e      	cmp	r3, #126	; 0x7e
+ 801f7f6:	d906      	bls.n	801f806 <etharp_query+0x7e>
+ 801f7f8:	4b7a      	ldr	r3, [pc, #488]	; (801f9e4 <etharp_query+0x25c>)
+ 801f7fa:	f240 32c1 	movw	r2, #961	; 0x3c1
+ 801f7fe:	497a      	ldr	r1, [pc, #488]	; (801f9e8 <etharp_query+0x260>)
+ 801f800:	487a      	ldr	r0, [pc, #488]	; (801f9ec <etharp_query+0x264>)
+ 801f802:	f002 f8c1 	bl	8021988 <iprintf>
+  i = (netif_addr_idx_t)i_err;
+ 801f806:	8a7b      	ldrh	r3, [r7, #18]
+ 801f808:	747b      	strb	r3, [r7, #17]
+
+  /* mark a fresh entry as pending (we just sent a request) */
+  if (arp_table[i].state == ETHARP_STATE_EMPTY) {
+ 801f80a:	7c7a      	ldrb	r2, [r7, #17]
+ 801f80c:	4978      	ldr	r1, [pc, #480]	; (801f9f0 <etharp_query+0x268>)
+ 801f80e:	4613      	mov	r3, r2
+ 801f810:	005b      	lsls	r3, r3, #1
+ 801f812:	4413      	add	r3, r2
+ 801f814:	00db      	lsls	r3, r3, #3
+ 801f816:	440b      	add	r3, r1
+ 801f818:	3314      	adds	r3, #20
+ 801f81a:	781b      	ldrb	r3, [r3, #0]
+ 801f81c:	2b00      	cmp	r3, #0
+ 801f81e:	d115      	bne.n	801f84c <etharp_query+0xc4>
+    is_new_entry = 1;
+ 801f820:	2301      	movs	r3, #1
+ 801f822:	623b      	str	r3, [r7, #32]
+    arp_table[i].state = ETHARP_STATE_PENDING;
+ 801f824:	7c7a      	ldrb	r2, [r7, #17]
+ 801f826:	4972      	ldr	r1, [pc, #456]	; (801f9f0 <etharp_query+0x268>)
+ 801f828:	4613      	mov	r3, r2
+ 801f82a:	005b      	lsls	r3, r3, #1
+ 801f82c:	4413      	add	r3, r2
+ 801f82e:	00db      	lsls	r3, r3, #3
+ 801f830:	440b      	add	r3, r1
+ 801f832:	3314      	adds	r3, #20
+ 801f834:	2201      	movs	r2, #1
+ 801f836:	701a      	strb	r2, [r3, #0]
+    /* record network interface for re-sending arp request in etharp_tmr */
+    arp_table[i].netif = netif;
+ 801f838:	7c7a      	ldrb	r2, [r7, #17]
+ 801f83a:	496d      	ldr	r1, [pc, #436]	; (801f9f0 <etharp_query+0x268>)
+ 801f83c:	4613      	mov	r3, r2
+ 801f83e:	005b      	lsls	r3, r3, #1
+ 801f840:	4413      	add	r3, r2
+ 801f842:	00db      	lsls	r3, r3, #3
+ 801f844:	440b      	add	r3, r1
+ 801f846:	3308      	adds	r3, #8
+ 801f848:	68fa      	ldr	r2, [r7, #12]
+ 801f84a:	601a      	str	r2, [r3, #0]
+  }
+
+  /* { i is either a STABLE or (new or existing) PENDING entry } */
+  LWIP_ASSERT("arp_table[i].state == PENDING or STABLE",
+ 801f84c:	7c7a      	ldrb	r2, [r7, #17]
+ 801f84e:	4968      	ldr	r1, [pc, #416]	; (801f9f0 <etharp_query+0x268>)
+ 801f850:	4613      	mov	r3, r2
+ 801f852:	005b      	lsls	r3, r3, #1
+ 801f854:	4413      	add	r3, r2
+ 801f856:	00db      	lsls	r3, r3, #3
+ 801f858:	440b      	add	r3, r1
+ 801f85a:	3314      	adds	r3, #20
+ 801f85c:	781b      	ldrb	r3, [r3, #0]
+ 801f85e:	2b01      	cmp	r3, #1
+ 801f860:	d011      	beq.n	801f886 <etharp_query+0xfe>
+ 801f862:	7c7a      	ldrb	r2, [r7, #17]
+ 801f864:	4962      	ldr	r1, [pc, #392]	; (801f9f0 <etharp_query+0x268>)
+ 801f866:	4613      	mov	r3, r2
+ 801f868:	005b      	lsls	r3, r3, #1
+ 801f86a:	4413      	add	r3, r2
+ 801f86c:	00db      	lsls	r3, r3, #3
+ 801f86e:	440b      	add	r3, r1
+ 801f870:	3314      	adds	r3, #20
+ 801f872:	781b      	ldrb	r3, [r3, #0]
+ 801f874:	2b01      	cmp	r3, #1
+ 801f876:	d806      	bhi.n	801f886 <etharp_query+0xfe>
+ 801f878:	4b5a      	ldr	r3, [pc, #360]	; (801f9e4 <etharp_query+0x25c>)
+ 801f87a:	f240 32cd 	movw	r2, #973	; 0x3cd
+ 801f87e:	495d      	ldr	r1, [pc, #372]	; (801f9f4 <etharp_query+0x26c>)
+ 801f880:	485a      	ldr	r0, [pc, #360]	; (801f9ec <etharp_query+0x264>)
+ 801f882:	f002 f881 	bl	8021988 <iprintf>
+              ((arp_table[i].state == ETHARP_STATE_PENDING) ||
+               (arp_table[i].state >= ETHARP_STATE_STABLE)));
+
+  /* do we have a new entry? or an implicit query request? */
+  if (is_new_entry || (q == NULL)) {
+ 801f886:	6a3b      	ldr	r3, [r7, #32]
+ 801f888:	2b00      	cmp	r3, #0
+ 801f88a:	d102      	bne.n	801f892 <etharp_query+0x10a>
+ 801f88c:	687b      	ldr	r3, [r7, #4]
+ 801f88e:	2b00      	cmp	r3, #0
+ 801f890:	d10c      	bne.n	801f8ac <etharp_query+0x124>
+    /* try to resolve it; send out ARP request */
+    result = etharp_request(netif, ipaddr);
+ 801f892:	68b9      	ldr	r1, [r7, #8]
+ 801f894:	68f8      	ldr	r0, [r7, #12]
+ 801f896:	f000 f963 	bl	801fb60 <etharp_request>
+ 801f89a:	4603      	mov	r3, r0
+ 801f89c:	f887 3027 	strb.w	r3, [r7, #39]	; 0x27
+      /* ARP request couldn't be sent */
+      /* We don't re-send arp request in etharp_tmr, but we still queue packets,
+         since this failure could be temporary, and the next packet calling
+         etharp_query again could lead to sending the queued packets. */
+    }
+    if (q == NULL) {
+ 801f8a0:	687b      	ldr	r3, [r7, #4]
+ 801f8a2:	2b00      	cmp	r3, #0
+ 801f8a4:	d102      	bne.n	801f8ac <etharp_query+0x124>
+      return result;
+ 801f8a6:	f997 3027 	ldrsb.w	r3, [r7, #39]	; 0x27
+ 801f8aa:	e096      	b.n	801f9da <etharp_query+0x252>
+    }
+  }
+
+  /* packet given? */
+  LWIP_ASSERT("q != NULL", q != NULL);
+ 801f8ac:	687b      	ldr	r3, [r7, #4]
+ 801f8ae:	2b00      	cmp	r3, #0
+ 801f8b0:	d106      	bne.n	801f8c0 <etharp_query+0x138>
+ 801f8b2:	4b4c      	ldr	r3, [pc, #304]	; (801f9e4 <etharp_query+0x25c>)
+ 801f8b4:	f240 32e1 	movw	r2, #993	; 0x3e1
+ 801f8b8:	494f      	ldr	r1, [pc, #316]	; (801f9f8 <etharp_query+0x270>)
+ 801f8ba:	484c      	ldr	r0, [pc, #304]	; (801f9ec <etharp_query+0x264>)
+ 801f8bc:	f002 f864 	bl	8021988 <iprintf>
+  /* stable entry? */
+  if (arp_table[i].state >= ETHARP_STATE_STABLE) {
+ 801f8c0:	7c7a      	ldrb	r2, [r7, #17]
+ 801f8c2:	494b      	ldr	r1, [pc, #300]	; (801f9f0 <etharp_query+0x268>)
+ 801f8c4:	4613      	mov	r3, r2
+ 801f8c6:	005b      	lsls	r3, r3, #1
+ 801f8c8:	4413      	add	r3, r2
+ 801f8ca:	00db      	lsls	r3, r3, #3
+ 801f8cc:	440b      	add	r3, r1
+ 801f8ce:	3314      	adds	r3, #20
+ 801f8d0:	781b      	ldrb	r3, [r3, #0]
+ 801f8d2:	2b01      	cmp	r3, #1
+ 801f8d4:	d917      	bls.n	801f906 <etharp_query+0x17e>
+    /* we have a valid IP->Ethernet address mapping */
+    ETHARP_SET_ADDRHINT(netif, i);
+ 801f8d6:	4a49      	ldr	r2, [pc, #292]	; (801f9fc <etharp_query+0x274>)
+ 801f8d8:	7c7b      	ldrb	r3, [r7, #17]
+ 801f8da:	7013      	strb	r3, [r2, #0]
+    /* send the packet */
+    result = ethernet_output(netif, q, srcaddr, &(arp_table[i].ethaddr), ETHTYPE_IP);
+ 801f8dc:	7c7a      	ldrb	r2, [r7, #17]
+ 801f8de:	4613      	mov	r3, r2
+ 801f8e0:	005b      	lsls	r3, r3, #1
+ 801f8e2:	4413      	add	r3, r2
+ 801f8e4:	00db      	lsls	r3, r3, #3
+ 801f8e6:	3308      	adds	r3, #8
+ 801f8e8:	4a41      	ldr	r2, [pc, #260]	; (801f9f0 <etharp_query+0x268>)
+ 801f8ea:	4413      	add	r3, r2
+ 801f8ec:	3304      	adds	r3, #4
+ 801f8ee:	f44f 6200 	mov.w	r2, #2048	; 0x800
+ 801f8f2:	9200      	str	r2, [sp, #0]
+ 801f8f4:	697a      	ldr	r2, [r7, #20]
+ 801f8f6:	6879      	ldr	r1, [r7, #4]
+ 801f8f8:	68f8      	ldr	r0, [r7, #12]
+ 801f8fa:	f001 fc9f 	bl	802123c <ethernet_output>
+ 801f8fe:	4603      	mov	r3, r0
+ 801f900:	f887 3027 	strb.w	r3, [r7, #39]	; 0x27
+ 801f904:	e067      	b.n	801f9d6 <etharp_query+0x24e>
+    /* pending entry? (either just created or already pending */
+  } else if (arp_table[i].state == ETHARP_STATE_PENDING) {
+ 801f906:	7c7a      	ldrb	r2, [r7, #17]
+ 801f908:	4939      	ldr	r1, [pc, #228]	; (801f9f0 <etharp_query+0x268>)
+ 801f90a:	4613      	mov	r3, r2
+ 801f90c:	005b      	lsls	r3, r3, #1
+ 801f90e:	4413      	add	r3, r2
+ 801f910:	00db      	lsls	r3, r3, #3
+ 801f912:	440b      	add	r3, r1
+ 801f914:	3314      	adds	r3, #20
+ 801f916:	781b      	ldrb	r3, [r3, #0]
+ 801f918:	2b01      	cmp	r3, #1
+ 801f91a:	d15c      	bne.n	801f9d6 <etharp_query+0x24e>
+    /* entry is still pending, queue the given packet 'q' */
+    struct pbuf *p;
+    int copy_needed = 0;
+ 801f91c:	2300      	movs	r3, #0
+ 801f91e:	61bb      	str	r3, [r7, #24]
+    /* IF q includes a pbuf that must be copied, copy the whole chain into a
+     * new PBUF_RAM. See the definition of PBUF_NEEDS_COPY for details. */
+    p = q;
+ 801f920:	687b      	ldr	r3, [r7, #4]
+ 801f922:	61fb      	str	r3, [r7, #28]
+    while (p) {
+ 801f924:	e01c      	b.n	801f960 <etharp_query+0x1d8>
+      LWIP_ASSERT("no packet queues allowed!", (p->len != p->tot_len) || (p->next == 0));
+ 801f926:	69fb      	ldr	r3, [r7, #28]
+ 801f928:	895a      	ldrh	r2, [r3, #10]
+ 801f92a:	69fb      	ldr	r3, [r7, #28]
+ 801f92c:	891b      	ldrh	r3, [r3, #8]
+ 801f92e:	429a      	cmp	r2, r3
+ 801f930:	d10a      	bne.n	801f948 <etharp_query+0x1c0>
+ 801f932:	69fb      	ldr	r3, [r7, #28]
+ 801f934:	681b      	ldr	r3, [r3, #0]
+ 801f936:	2b00      	cmp	r3, #0
+ 801f938:	d006      	beq.n	801f948 <etharp_query+0x1c0>
+ 801f93a:	4b2a      	ldr	r3, [pc, #168]	; (801f9e4 <etharp_query+0x25c>)
+ 801f93c:	f240 32f1 	movw	r2, #1009	; 0x3f1
+ 801f940:	492f      	ldr	r1, [pc, #188]	; (801fa00 <etharp_query+0x278>)
+ 801f942:	482a      	ldr	r0, [pc, #168]	; (801f9ec <etharp_query+0x264>)
+ 801f944:	f002 f820 	bl	8021988 <iprintf>
+      if (PBUF_NEEDS_COPY(p)) {
+ 801f948:	69fb      	ldr	r3, [r7, #28]
+ 801f94a:	7b1b      	ldrb	r3, [r3, #12]
+ 801f94c:	f003 0340 	and.w	r3, r3, #64	; 0x40
+ 801f950:	2b00      	cmp	r3, #0
+ 801f952:	d002      	beq.n	801f95a <etharp_query+0x1d2>
+        copy_needed = 1;
+ 801f954:	2301      	movs	r3, #1
+ 801f956:	61bb      	str	r3, [r7, #24]
+        break;
+ 801f958:	e005      	b.n	801f966 <etharp_query+0x1de>
+      }
+      p = p->next;
+ 801f95a:	69fb      	ldr	r3, [r7, #28]
+ 801f95c:	681b      	ldr	r3, [r3, #0]
+ 801f95e:	61fb      	str	r3, [r7, #28]
+    while (p) {
+ 801f960:	69fb      	ldr	r3, [r7, #28]
+ 801f962:	2b00      	cmp	r3, #0
+ 801f964:	d1df      	bne.n	801f926 <etharp_query+0x19e>
+    }
+    if (copy_needed) {
+ 801f966:	69bb      	ldr	r3, [r7, #24]
+ 801f968:	2b00      	cmp	r3, #0
+ 801f96a:	d007      	beq.n	801f97c <etharp_query+0x1f4>
+      /* copy the whole packet into new pbufs */
+      p = pbuf_clone(PBUF_LINK, PBUF_RAM, q);
+ 801f96c:	687a      	ldr	r2, [r7, #4]
+ 801f96e:	f44f 7120 	mov.w	r1, #640	; 0x280
+ 801f972:	200e      	movs	r0, #14
+ 801f974:	f7f8 fb28 	bl	8017fc8 <pbuf_clone>
+ 801f978:	61f8      	str	r0, [r7, #28]
+ 801f97a:	e004      	b.n	801f986 <etharp_query+0x1fe>
+    } else {
+      /* referencing the old pbuf is enough */
+      p = q;
+ 801f97c:	687b      	ldr	r3, [r7, #4]
+ 801f97e:	61fb      	str	r3, [r7, #28]
+      pbuf_ref(p);
+ 801f980:	69f8      	ldr	r0, [r7, #28]
+ 801f982:	f7f8 f95f 	bl	8017c44 <pbuf_ref>
+    }
+    /* packet could be taken over? */
+    if (p != NULL) {
+ 801f986:	69fb      	ldr	r3, [r7, #28]
+ 801f988:	2b00      	cmp	r3, #0
+ 801f98a:	d021      	beq.n	801f9d0 <etharp_query+0x248>
+        LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_query: could not queue a copy of PBUF_REF packet %p (out of memory)\n", (void *)q));
+        result = ERR_MEM;
+      }
+#else /* ARP_QUEUEING */
+      /* always queue one packet per ARP request only, freeing a previously queued packet */
+      if (arp_table[i].q != NULL) {
+ 801f98c:	7c7a      	ldrb	r2, [r7, #17]
+ 801f98e:	4918      	ldr	r1, [pc, #96]	; (801f9f0 <etharp_query+0x268>)
+ 801f990:	4613      	mov	r3, r2
+ 801f992:	005b      	lsls	r3, r3, #1
+ 801f994:	4413      	add	r3, r2
+ 801f996:	00db      	lsls	r3, r3, #3
+ 801f998:	440b      	add	r3, r1
+ 801f99a:	681b      	ldr	r3, [r3, #0]
+ 801f99c:	2b00      	cmp	r3, #0
+ 801f99e:	d00a      	beq.n	801f9b6 <etharp_query+0x22e>
+        LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_query: dropped previously queued packet %p for ARP entry %"U16_F"\n", (void *)q, (u16_t)i));
+        pbuf_free(arp_table[i].q);
+ 801f9a0:	7c7a      	ldrb	r2, [r7, #17]
+ 801f9a2:	4913      	ldr	r1, [pc, #76]	; (801f9f0 <etharp_query+0x268>)
+ 801f9a4:	4613      	mov	r3, r2
+ 801f9a6:	005b      	lsls	r3, r3, #1
+ 801f9a8:	4413      	add	r3, r2
+ 801f9aa:	00db      	lsls	r3, r3, #3
+ 801f9ac:	440b      	add	r3, r1
+ 801f9ae:	681b      	ldr	r3, [r3, #0]
+ 801f9b0:	4618      	mov	r0, r3
+ 801f9b2:	f7f8 f8a1 	bl	8017af8 <pbuf_free>
+      }
+      arp_table[i].q = p;
+ 801f9b6:	7c7a      	ldrb	r2, [r7, #17]
+ 801f9b8:	490d      	ldr	r1, [pc, #52]	; (801f9f0 <etharp_query+0x268>)
+ 801f9ba:	4613      	mov	r3, r2
+ 801f9bc:	005b      	lsls	r3, r3, #1
+ 801f9be:	4413      	add	r3, r2
+ 801f9c0:	00db      	lsls	r3, r3, #3
+ 801f9c2:	440b      	add	r3, r1
+ 801f9c4:	69fa      	ldr	r2, [r7, #28]
+ 801f9c6:	601a      	str	r2, [r3, #0]
+      result = ERR_OK;
+ 801f9c8:	2300      	movs	r3, #0
+ 801f9ca:	f887 3027 	strb.w	r3, [r7, #39]	; 0x27
+ 801f9ce:	e002      	b.n	801f9d6 <etharp_query+0x24e>
+      LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_query: queued packet %p on ARP entry %"U16_F"\n", (void *)q, (u16_t)i));
+#endif /* ARP_QUEUEING */
+    } else {
+      ETHARP_STATS_INC(etharp.memerr);
+      LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_query: could not queue a copy of PBUF_REF packet %p (out of memory)\n", (void *)q));
+      result = ERR_MEM;
+ 801f9d0:	23ff      	movs	r3, #255	; 0xff
+ 801f9d2:	f887 3027 	strb.w	r3, [r7, #39]	; 0x27
+    }
+  }
+  return result;
+ 801f9d6:	f997 3027 	ldrsb.w	r3, [r7, #39]	; 0x27
+}
+ 801f9da:	4618      	mov	r0, r3
+ 801f9dc:	3728      	adds	r7, #40	; 0x28
+ 801f9de:	46bd      	mov	sp, r7
+ 801f9e0:	bd80      	pop	{r7, pc}
+ 801f9e2:	bf00      	nop
+ 801f9e4:	0802647c 	.word	0x0802647c
+ 801f9e8:	08026628 	.word	0x08026628
+ 801f9ec:	080264f4 	.word	0x080264f4
+ 801f9f0:	2401a4e4 	.word	0x2401a4e4
+ 801f9f4:	08026638 	.word	0x08026638
+ 801f9f8:	0802661c 	.word	0x0802661c
+ 801f9fc:	2401a5d4 	.word	0x2401a5d4
+ 801fa00:	08026660 	.word	0x08026660
+
+0801fa04 <etharp_raw>:
+etharp_raw(struct netif *netif, const struct eth_addr *ethsrc_addr,
+           const struct eth_addr *ethdst_addr,
+           const struct eth_addr *hwsrc_addr, const ip4_addr_t *ipsrc_addr,
+           const struct eth_addr *hwdst_addr, const ip4_addr_t *ipdst_addr,
+           const u16_t opcode)
+{
+ 801fa04:	b580      	push	{r7, lr}
+ 801fa06:	b08a      	sub	sp, #40	; 0x28
+ 801fa08:	af02      	add	r7, sp, #8
+ 801fa0a:	60f8      	str	r0, [r7, #12]
+ 801fa0c:	60b9      	str	r1, [r7, #8]
+ 801fa0e:	607a      	str	r2, [r7, #4]
+ 801fa10:	603b      	str	r3, [r7, #0]
+  struct pbuf *p;
+  err_t result = ERR_OK;
+ 801fa12:	2300      	movs	r3, #0
+ 801fa14:	77fb      	strb	r3, [r7, #31]
+  struct etharp_hdr *hdr;
+
+  LWIP_ASSERT("netif != NULL", netif != NULL);
+ 801fa16:	68fb      	ldr	r3, [r7, #12]
+ 801fa18:	2b00      	cmp	r3, #0
+ 801fa1a:	d106      	bne.n	801fa2a <etharp_raw+0x26>
+ 801fa1c:	4b3a      	ldr	r3, [pc, #232]	; (801fb08 <etharp_raw+0x104>)
+ 801fa1e:	f240 4257 	movw	r2, #1111	; 0x457
+ 801fa22:	493a      	ldr	r1, [pc, #232]	; (801fb0c <etharp_raw+0x108>)
+ 801fa24:	483a      	ldr	r0, [pc, #232]	; (801fb10 <etharp_raw+0x10c>)
+ 801fa26:	f001 ffaf 	bl	8021988 <iprintf>
+
+  /* allocate a pbuf for the outgoing ARP request packet */
+  p = pbuf_alloc(PBUF_LINK, SIZEOF_ETHARP_HDR, PBUF_RAM);
+ 801fa2a:	f44f 7220 	mov.w	r2, #640	; 0x280
+ 801fa2e:	211c      	movs	r1, #28
+ 801fa30:	200e      	movs	r0, #14
+ 801fa32:	f7f7 fd79 	bl	8017528 <pbuf_alloc>
+ 801fa36:	61b8      	str	r0, [r7, #24]
+  /* could allocate a pbuf for an ARP request? */
+  if (p == NULL) {
+ 801fa38:	69bb      	ldr	r3, [r7, #24]
+ 801fa3a:	2b00      	cmp	r3, #0
+ 801fa3c:	d102      	bne.n	801fa44 <etharp_raw+0x40>
+    LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS,
+                ("etharp_raw: could not allocate pbuf for ARP request.\n"));
+    ETHARP_STATS_INC(etharp.memerr);
+    return ERR_MEM;
+ 801fa3e:	f04f 33ff 	mov.w	r3, #4294967295
+ 801fa42:	e05d      	b.n	801fb00 <etharp_raw+0xfc>
+  }
+  LWIP_ASSERT("check that first pbuf can hold struct etharp_hdr",
+ 801fa44:	69bb      	ldr	r3, [r7, #24]
+ 801fa46:	895b      	ldrh	r3, [r3, #10]
+ 801fa48:	2b1b      	cmp	r3, #27
+ 801fa4a:	d806      	bhi.n	801fa5a <etharp_raw+0x56>
+ 801fa4c:	4b2e      	ldr	r3, [pc, #184]	; (801fb08 <etharp_raw+0x104>)
+ 801fa4e:	f240 4262 	movw	r2, #1122	; 0x462
+ 801fa52:	4930      	ldr	r1, [pc, #192]	; (801fb14 <etharp_raw+0x110>)
+ 801fa54:	482e      	ldr	r0, [pc, #184]	; (801fb10 <etharp_raw+0x10c>)
+ 801fa56:	f001 ff97 	bl	8021988 <iprintf>
+              (p->len >= SIZEOF_ETHARP_HDR));
+
+  hdr = (struct etharp_hdr *)p->payload;
+ 801fa5a:	69bb      	ldr	r3, [r7, #24]
+ 801fa5c:	685b      	ldr	r3, [r3, #4]
+ 801fa5e:	617b      	str	r3, [r7, #20]
+  LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_raw: sending raw ARP packet.\n"));
+  hdr->opcode = lwip_htons(opcode);
+ 801fa60:	8ebb      	ldrh	r3, [r7, #52]	; 0x34
+ 801fa62:	4618      	mov	r0, r3
+ 801fa64:	f7f6 fa6c 	bl	8015f40 <lwip_htons>
+ 801fa68:	4603      	mov	r3, r0
+ 801fa6a:	461a      	mov	r2, r3
+ 801fa6c:	697b      	ldr	r3, [r7, #20]
+ 801fa6e:	80da      	strh	r2, [r3, #6]
+
+  LWIP_ASSERT("netif->hwaddr_len must be the same as ETH_HWADDR_LEN for etharp!",
+ 801fa70:	68fb      	ldr	r3, [r7, #12]
+ 801fa72:	f893 302c 	ldrb.w	r3, [r3, #44]	; 0x2c
+ 801fa76:	2b06      	cmp	r3, #6
+ 801fa78:	d006      	beq.n	801fa88 <etharp_raw+0x84>
+ 801fa7a:	4b23      	ldr	r3, [pc, #140]	; (801fb08 <etharp_raw+0x104>)
+ 801fa7c:	f240 4269 	movw	r2, #1129	; 0x469
+ 801fa80:	4925      	ldr	r1, [pc, #148]	; (801fb18 <etharp_raw+0x114>)
+ 801fa82:	4823      	ldr	r0, [pc, #140]	; (801fb10 <etharp_raw+0x10c>)
+ 801fa84:	f001 ff80 	bl	8021988 <iprintf>
+              (netif->hwaddr_len == ETH_HWADDR_LEN));
+
+  /* Write the ARP MAC-Addresses */
+  SMEMCPY(&hdr->shwaddr, hwsrc_addr, ETH_HWADDR_LEN);
+ 801fa88:	697b      	ldr	r3, [r7, #20]
+ 801fa8a:	3308      	adds	r3, #8
+ 801fa8c:	2206      	movs	r2, #6
+ 801fa8e:	6839      	ldr	r1, [r7, #0]
+ 801fa90:	4618      	mov	r0, r3
+ 801fa92:	f002 f9a8 	bl	8021de6 <memcpy>
+  SMEMCPY(&hdr->dhwaddr, hwdst_addr, ETH_HWADDR_LEN);
+ 801fa96:	697b      	ldr	r3, [r7, #20]
+ 801fa98:	3312      	adds	r3, #18
+ 801fa9a:	2206      	movs	r2, #6
+ 801fa9c:	6af9      	ldr	r1, [r7, #44]	; 0x2c
+ 801fa9e:	4618      	mov	r0, r3
+ 801faa0:	f002 f9a1 	bl	8021de6 <memcpy>
+  /* Copy struct ip4_addr_wordaligned to aligned ip4_addr, to support compilers without
+   * structure packing. */
+  IPADDR_WORDALIGNED_COPY_FROM_IP4_ADDR_T(&hdr->sipaddr, ipsrc_addr);
+ 801faa4:	697b      	ldr	r3, [r7, #20]
+ 801faa6:	330e      	adds	r3, #14
+ 801faa8:	6aba      	ldr	r2, [r7, #40]	; 0x28
+ 801faaa:	6812      	ldr	r2, [r2, #0]
+ 801faac:	601a      	str	r2, [r3, #0]
+  IPADDR_WORDALIGNED_COPY_FROM_IP4_ADDR_T(&hdr->dipaddr, ipdst_addr);
+ 801faae:	697b      	ldr	r3, [r7, #20]
+ 801fab0:	3318      	adds	r3, #24
+ 801fab2:	6b3a      	ldr	r2, [r7, #48]	; 0x30
+ 801fab4:	6812      	ldr	r2, [r2, #0]
+ 801fab6:	601a      	str	r2, [r3, #0]
+
+  hdr->hwtype = PP_HTONS(LWIP_IANA_HWTYPE_ETHERNET);
+ 801fab8:	697b      	ldr	r3, [r7, #20]
+ 801faba:	2200      	movs	r2, #0
+ 801fabc:	701a      	strb	r2, [r3, #0]
+ 801fabe:	2200      	movs	r2, #0
+ 801fac0:	f042 0201 	orr.w	r2, r2, #1
+ 801fac4:	705a      	strb	r2, [r3, #1]
+  hdr->proto = PP_HTONS(ETHTYPE_IP);
+ 801fac6:	697b      	ldr	r3, [r7, #20]
+ 801fac8:	2200      	movs	r2, #0
+ 801faca:	f042 0208 	orr.w	r2, r2, #8
+ 801face:	709a      	strb	r2, [r3, #2]
+ 801fad0:	2200      	movs	r2, #0
+ 801fad2:	70da      	strb	r2, [r3, #3]
+  /* set hwlen and protolen */
+  hdr->hwlen = ETH_HWADDR_LEN;
+ 801fad4:	697b      	ldr	r3, [r7, #20]
+ 801fad6:	2206      	movs	r2, #6
+ 801fad8:	711a      	strb	r2, [r3, #4]
+  hdr->protolen = sizeof(ip4_addr_t);
+ 801fada:	697b      	ldr	r3, [r7, #20]
+ 801fadc:	2204      	movs	r2, #4
+ 801fade:	715a      	strb	r2, [r3, #5]
+  if (ip4_addr_islinklocal(ipsrc_addr)) {
+    ethernet_output(netif, p, ethsrc_addr, &ethbroadcast, ETHTYPE_ARP);
+  } else
+#endif /* LWIP_AUTOIP */
+  {
+    ethernet_output(netif, p, ethsrc_addr, ethdst_addr, ETHTYPE_ARP);
+ 801fae0:	f640 0306 	movw	r3, #2054	; 0x806
+ 801fae4:	9300      	str	r3, [sp, #0]
+ 801fae6:	687b      	ldr	r3, [r7, #4]
+ 801fae8:	68ba      	ldr	r2, [r7, #8]
+ 801faea:	69b9      	ldr	r1, [r7, #24]
+ 801faec:	68f8      	ldr	r0, [r7, #12]
+ 801faee:	f001 fba5 	bl	802123c <ethernet_output>
+  }
+
+  ETHARP_STATS_INC(etharp.xmit);
+  /* free ARP query packet */
+  pbuf_free(p);
+ 801faf2:	69b8      	ldr	r0, [r7, #24]
+ 801faf4:	f7f8 f800 	bl	8017af8 <pbuf_free>
+  p = NULL;
+ 801faf8:	2300      	movs	r3, #0
+ 801fafa:	61bb      	str	r3, [r7, #24]
+  /* could not allocate pbuf for ARP request */
+
+  return result;
+ 801fafc:	f997 301f 	ldrsb.w	r3, [r7, #31]
+}
+ 801fb00:	4618      	mov	r0, r3
+ 801fb02:	3720      	adds	r7, #32
+ 801fb04:	46bd      	mov	sp, r7
+ 801fb06:	bd80      	pop	{r7, pc}
+ 801fb08:	0802647c 	.word	0x0802647c
+ 801fb0c:	080265cc 	.word	0x080265cc
+ 801fb10:	080264f4 	.word	0x080264f4
+ 801fb14:	0802667c 	.word	0x0802667c
+ 801fb18:	080266b0 	.word	0x080266b0
+
+0801fb1c <etharp_request_dst>:
+ *         ERR_MEM if the ARP packet couldn't be allocated
+ *         any other err_t on failure
+ */
+static err_t
+etharp_request_dst(struct netif *netif, const ip4_addr_t *ipaddr, const struct eth_addr *hw_dst_addr)
+{
+ 801fb1c:	b580      	push	{r7, lr}
+ 801fb1e:	b088      	sub	sp, #32
+ 801fb20:	af04      	add	r7, sp, #16
+ 801fb22:	60f8      	str	r0, [r7, #12]
+ 801fb24:	60b9      	str	r1, [r7, #8]
+ 801fb26:	607a      	str	r2, [r7, #4]
+  return etharp_raw(netif, (struct eth_addr *)netif->hwaddr, hw_dst_addr,
+ 801fb28:	68fb      	ldr	r3, [r7, #12]
+ 801fb2a:	f103 0126 	add.w	r1, r3, #38	; 0x26
+                    (struct eth_addr *)netif->hwaddr, netif_ip4_addr(netif), &ethzero,
+ 801fb2e:	68fb      	ldr	r3, [r7, #12]
+ 801fb30:	f103 0026 	add.w	r0, r3, #38	; 0x26
+ 801fb34:	68fb      	ldr	r3, [r7, #12]
+ 801fb36:	3304      	adds	r3, #4
+  return etharp_raw(netif, (struct eth_addr *)netif->hwaddr, hw_dst_addr,
+ 801fb38:	2201      	movs	r2, #1
+ 801fb3a:	9203      	str	r2, [sp, #12]
+ 801fb3c:	68ba      	ldr	r2, [r7, #8]
+ 801fb3e:	9202      	str	r2, [sp, #8]
+ 801fb40:	4a06      	ldr	r2, [pc, #24]	; (801fb5c <etharp_request_dst+0x40>)
+ 801fb42:	9201      	str	r2, [sp, #4]
+ 801fb44:	9300      	str	r3, [sp, #0]
+ 801fb46:	4603      	mov	r3, r0
+ 801fb48:	687a      	ldr	r2, [r7, #4]
+ 801fb4a:	68f8      	ldr	r0, [r7, #12]
+ 801fb4c:	f7ff ff5a 	bl	801fa04 <etharp_raw>
+ 801fb50:	4603      	mov	r3, r0
+                    ipaddr, ARP_REQUEST);
+}
+ 801fb52:	4618      	mov	r0, r3
+ 801fb54:	3710      	adds	r7, #16
+ 801fb56:	46bd      	mov	sp, r7
+ 801fb58:	bd80      	pop	{r7, pc}
+ 801fb5a:	bf00      	nop
+ 801fb5c:	08026cf8 	.word	0x08026cf8
+
+0801fb60 <etharp_request>:
+ *         ERR_MEM if the ARP packet couldn't be allocated
+ *         any other err_t on failure
+ */
+err_t
+etharp_request(struct netif *netif, const ip4_addr_t *ipaddr)
+{
+ 801fb60:	b580      	push	{r7, lr}
+ 801fb62:	b082      	sub	sp, #8
+ 801fb64:	af00      	add	r7, sp, #0
+ 801fb66:	6078      	str	r0, [r7, #4]
+ 801fb68:	6039      	str	r1, [r7, #0]
+  LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_request: sending ARP request.\n"));
+  return etharp_request_dst(netif, ipaddr, &ethbroadcast);
+ 801fb6a:	4a05      	ldr	r2, [pc, #20]	; (801fb80 <etharp_request+0x20>)
+ 801fb6c:	6839      	ldr	r1, [r7, #0]
+ 801fb6e:	6878      	ldr	r0, [r7, #4]
+ 801fb70:	f7ff ffd4 	bl	801fb1c <etharp_request_dst>
+ 801fb74:	4603      	mov	r3, r0
+}
+ 801fb76:	4618      	mov	r0, r3
+ 801fb78:	3708      	adds	r7, #8
+ 801fb7a:	46bd      	mov	sp, r7
+ 801fb7c:	bd80      	pop	{r7, pc}
+ 801fb7e:	bf00      	nop
+ 801fb80:	08026cf0 	.word	0x08026cf0
+
+0801fb84 <icmp_input>:
+ * @param p the icmp echo request packet, p->payload pointing to the icmp header
+ * @param inp the netif on which this packet was received
+ */
+void
+icmp_input(struct pbuf *p, struct netif *inp)
+{
+ 801fb84:	b580      	push	{r7, lr}
+ 801fb86:	b08e      	sub	sp, #56	; 0x38
+ 801fb88:	af04      	add	r7, sp, #16
+ 801fb8a:	6078      	str	r0, [r7, #4]
+ 801fb8c:	6039      	str	r1, [r7, #0]
+  const ip4_addr_t *src;
+
+  ICMP_STATS_INC(icmp.recv);
+  MIB2_STATS_INC(mib2.icmpinmsgs);
+
+  iphdr_in = ip4_current_header();
+ 801fb8e:	4b89      	ldr	r3, [pc, #548]	; (801fdb4 <icmp_input+0x230>)
+ 801fb90:	689b      	ldr	r3, [r3, #8]
+ 801fb92:	627b      	str	r3, [r7, #36]	; 0x24
+  hlen = IPH_HL_BYTES(iphdr_in);
+ 801fb94:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 801fb96:	781b      	ldrb	r3, [r3, #0]
+ 801fb98:	f003 030f 	and.w	r3, r3, #15
+ 801fb9c:	b2db      	uxtb	r3, r3
+ 801fb9e:	009b      	lsls	r3, r3, #2
+ 801fba0:	b2db      	uxtb	r3, r3
+ 801fba2:	847b      	strh	r3, [r7, #34]	; 0x22
+  if (hlen < IP_HLEN) {
+ 801fba4:	8c7b      	ldrh	r3, [r7, #34]	; 0x22
+ 801fba6:	2b13      	cmp	r3, #19
+ 801fba8:	f240 80ed 	bls.w	801fd86 <icmp_input+0x202>
+    LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: short IP header (%"S16_F" bytes) received\n", hlen));
+    goto lenerr;
+  }
+  if (p->len < sizeof(u16_t) * 2) {
+ 801fbac:	687b      	ldr	r3, [r7, #4]
+ 801fbae:	895b      	ldrh	r3, [r3, #10]
+ 801fbb0:	2b03      	cmp	r3, #3
+ 801fbb2:	f240 80ea 	bls.w	801fd8a <icmp_input+0x206>
+    LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: short ICMP (%"U16_F" bytes) received\n", p->tot_len));
+    goto lenerr;
+  }
+
+  type = *((u8_t *)p->payload);
+ 801fbb6:	687b      	ldr	r3, [r7, #4]
+ 801fbb8:	685b      	ldr	r3, [r3, #4]
+ 801fbba:	781b      	ldrb	r3, [r3, #0]
+ 801fbbc:	f887 3021 	strb.w	r3, [r7, #33]	; 0x21
+#ifdef LWIP_DEBUG
+  code = *(((u8_t *)p->payload) + 1);
+ 801fbc0:	687b      	ldr	r3, [r7, #4]
+ 801fbc2:	685b      	ldr	r3, [r3, #4]
+ 801fbc4:	785b      	ldrb	r3, [r3, #1]
+ 801fbc6:	f887 3020 	strb.w	r3, [r7, #32]
+  /* if debug is enabled but debug statement below is somehow disabled: */
+  LWIP_UNUSED_ARG(code);
+#endif /* LWIP_DEBUG */
+  switch (type) {
+ 801fbca:	f897 3021 	ldrb.w	r3, [r7, #33]	; 0x21
+ 801fbce:	2b00      	cmp	r3, #0
+ 801fbd0:	f000 80d2 	beq.w	801fd78 <icmp_input+0x1f4>
+ 801fbd4:	2b08      	cmp	r3, #8
+ 801fbd6:	f040 80d2 	bne.w	801fd7e <icmp_input+0x1fa>
+         (as obviously, an echo request has been sent, too). */
+      MIB2_STATS_INC(mib2.icmpinechoreps);
+      break;
+    case ICMP_ECHO:
+      MIB2_STATS_INC(mib2.icmpinechos);
+      src = ip4_current_dest_addr();
+ 801fbda:	4b77      	ldr	r3, [pc, #476]	; (801fdb8 <icmp_input+0x234>)
+ 801fbdc:	61fb      	str	r3, [r7, #28]
+      /* multicast destination address? */
+      if (ip4_addr_ismulticast(ip4_current_dest_addr())) {
+ 801fbde:	4b75      	ldr	r3, [pc, #468]	; (801fdb4 <icmp_input+0x230>)
+ 801fbe0:	695b      	ldr	r3, [r3, #20]
+ 801fbe2:	f003 03f0 	and.w	r3, r3, #240	; 0xf0
+ 801fbe6:	2be0      	cmp	r3, #224	; 0xe0
+ 801fbe8:	f000 80d6 	beq.w	801fd98 <icmp_input+0x214>
+        LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: Not echoing to multicast pings\n"));
+        goto icmperr;
+#endif /* LWIP_MULTICAST_PING */
+      }
+      /* broadcast destination address? */
+      if (ip4_addr_isbroadcast(ip4_current_dest_addr(), ip_current_netif())) {
+ 801fbec:	4b71      	ldr	r3, [pc, #452]	; (801fdb4 <icmp_input+0x230>)
+ 801fbee:	695b      	ldr	r3, [r3, #20]
+ 801fbf0:	4a70      	ldr	r2, [pc, #448]	; (801fdb4 <icmp_input+0x230>)
+ 801fbf2:	6812      	ldr	r2, [r2, #0]
+ 801fbf4:	4611      	mov	r1, r2
+ 801fbf6:	4618      	mov	r0, r3
+ 801fbf8:	f000 fc12 	bl	8020420 <ip4_addr_isbroadcast_u32>
+ 801fbfc:	4603      	mov	r3, r0
+ 801fbfe:	2b00      	cmp	r3, #0
+ 801fc00:	f040 80cc 	bne.w	801fd9c <icmp_input+0x218>
+        LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: Not echoing to broadcast pings\n"));
+        goto icmperr;
+#endif /* LWIP_BROADCAST_PING */
+      }
+      LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: ping\n"));
+      if (p->tot_len < sizeof(struct icmp_echo_hdr)) {
+ 801fc04:	687b      	ldr	r3, [r7, #4]
+ 801fc06:	891b      	ldrh	r3, [r3, #8]
+ 801fc08:	2b07      	cmp	r3, #7
+ 801fc0a:	f240 80c0 	bls.w	801fd8e <icmp_input+0x20a>
+        LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: bad ICMP echo received\n"));
+        goto lenerr;
+      }
+#if CHECKSUM_CHECK_ICMP
+      IF__NETIF_CHECKSUM_ENABLED(inp, NETIF_CHECKSUM_CHECK_ICMP) {
+        if (inet_chksum_pbuf(p) != 0) {
+ 801fc0e:	6878      	ldr	r0, [r7, #4]
+ 801fc10:	f7f6 fa33 	bl	801607a <inet_chksum_pbuf>
+ 801fc14:	4603      	mov	r3, r0
+ 801fc16:	2b00      	cmp	r3, #0
+ 801fc18:	d003      	beq.n	801fc22 <icmp_input+0x9e>
+          LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: checksum failed for received ICMP echo\n"));
+          pbuf_free(p);
+ 801fc1a:	6878      	ldr	r0, [r7, #4]
+ 801fc1c:	f7f7 ff6c 	bl	8017af8 <pbuf_free>
+          ICMP_STATS_INC(icmp.chkerr);
+          MIB2_STATS_INC(mib2.icmpinerrors);
+          return;
+ 801fc20:	e0c5      	b.n	801fdae <icmp_input+0x22a>
+        }
+      }
+#endif
+#if LWIP_ICMP_ECHO_CHECK_INPUT_PBUF_LEN
+      if (pbuf_add_header(p, hlen + PBUF_LINK_HLEN + PBUF_LINK_ENCAPSULATION_HLEN)) {
+ 801fc22:	8c7b      	ldrh	r3, [r7, #34]	; 0x22
+ 801fc24:	330e      	adds	r3, #14
+ 801fc26:	4619      	mov	r1, r3
+ 801fc28:	6878      	ldr	r0, [r7, #4]
+ 801fc2a:	f7f7 fecf 	bl	80179cc <pbuf_add_header>
+ 801fc2e:	4603      	mov	r3, r0
+ 801fc30:	2b00      	cmp	r3, #0
+ 801fc32:	d04b      	beq.n	801fccc <icmp_input+0x148>
+        /* p is not big enough to contain link headers
+         * allocate a new one and copy p into it
+         */
+        struct pbuf *r;
+        u16_t alloc_len = (u16_t)(p->tot_len + hlen);
+ 801fc34:	687b      	ldr	r3, [r7, #4]
+ 801fc36:	891a      	ldrh	r2, [r3, #8]
+ 801fc38:	8c7b      	ldrh	r3, [r7, #34]	; 0x22
+ 801fc3a:	4413      	add	r3, r2
+ 801fc3c:	837b      	strh	r3, [r7, #26]
+        if (alloc_len < p->tot_len) {
+ 801fc3e:	687b      	ldr	r3, [r7, #4]
+ 801fc40:	891b      	ldrh	r3, [r3, #8]
+ 801fc42:	8b7a      	ldrh	r2, [r7, #26]
+ 801fc44:	429a      	cmp	r2, r3
+ 801fc46:	f0c0 80ab 	bcc.w	801fda0 <icmp_input+0x21c>
+          LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: allocating new pbuf failed (tot_len overflow)\n"));
+          goto icmperr;
+        }
+        /* allocate new packet buffer with space for link headers */
+        r = pbuf_alloc(PBUF_LINK, alloc_len, PBUF_RAM);
+ 801fc4a:	8b7b      	ldrh	r3, [r7, #26]
+ 801fc4c:	f44f 7220 	mov.w	r2, #640	; 0x280
+ 801fc50:	4619      	mov	r1, r3
+ 801fc52:	200e      	movs	r0, #14
+ 801fc54:	f7f7 fc68 	bl	8017528 <pbuf_alloc>
+ 801fc58:	6178      	str	r0, [r7, #20]
+        if (r == NULL) {
+ 801fc5a:	697b      	ldr	r3, [r7, #20]
+ 801fc5c:	2b00      	cmp	r3, #0
+ 801fc5e:	f000 80a1 	beq.w	801fda4 <icmp_input+0x220>
+          LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: allocating new pbuf failed\n"));
+          goto icmperr;
+        }
+        if (r->len < hlen + sizeof(struct icmp_echo_hdr)) {
+ 801fc62:	697b      	ldr	r3, [r7, #20]
+ 801fc64:	895b      	ldrh	r3, [r3, #10]
+ 801fc66:	461a      	mov	r2, r3
+ 801fc68:	8c7b      	ldrh	r3, [r7, #34]	; 0x22
+ 801fc6a:	3308      	adds	r3, #8
+ 801fc6c:	429a      	cmp	r2, r3
+ 801fc6e:	d203      	bcs.n	801fc78 <icmp_input+0xf4>
+          LWIP_DEBUGF(ICMP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("first pbuf cannot hold the ICMP header"));
+          pbuf_free(r);
+ 801fc70:	6978      	ldr	r0, [r7, #20]
+ 801fc72:	f7f7 ff41 	bl	8017af8 <pbuf_free>
+          goto icmperr;
+ 801fc76:	e096      	b.n	801fda6 <icmp_input+0x222>
+        }
+        /* copy the ip header */
+        MEMCPY(r->payload, iphdr_in, hlen);
+ 801fc78:	697b      	ldr	r3, [r7, #20]
+ 801fc7a:	685b      	ldr	r3, [r3, #4]
+ 801fc7c:	8c7a      	ldrh	r2, [r7, #34]	; 0x22
+ 801fc7e:	6a79      	ldr	r1, [r7, #36]	; 0x24
+ 801fc80:	4618      	mov	r0, r3
+ 801fc82:	f002 f8b0 	bl	8021de6 <memcpy>
+        /* switch r->payload back to icmp header (cannot fail) */
+        if (pbuf_remove_header(r, hlen)) {
+ 801fc86:	8c7b      	ldrh	r3, [r7, #34]	; 0x22
+ 801fc88:	4619      	mov	r1, r3
+ 801fc8a:	6978      	ldr	r0, [r7, #20]
+ 801fc8c:	f7f7 feae 	bl	80179ec <pbuf_remove_header>
+ 801fc90:	4603      	mov	r3, r0
+ 801fc92:	2b00      	cmp	r3, #0
+ 801fc94:	d009      	beq.n	801fcaa <icmp_input+0x126>
+          LWIP_ASSERT("icmp_input: moving r->payload to icmp header failed\n", 0);
+ 801fc96:	4b49      	ldr	r3, [pc, #292]	; (801fdbc <icmp_input+0x238>)
+ 801fc98:	22b6      	movs	r2, #182	; 0xb6
+ 801fc9a:	4949      	ldr	r1, [pc, #292]	; (801fdc0 <icmp_input+0x23c>)
+ 801fc9c:	4849      	ldr	r0, [pc, #292]	; (801fdc4 <icmp_input+0x240>)
+ 801fc9e:	f001 fe73 	bl	8021988 <iprintf>
+          pbuf_free(r);
+ 801fca2:	6978      	ldr	r0, [r7, #20]
+ 801fca4:	f7f7 ff28 	bl	8017af8 <pbuf_free>
+          goto icmperr;
+ 801fca8:	e07d      	b.n	801fda6 <icmp_input+0x222>
+        }
+        /* copy the rest of the packet without ip header */
+        if (pbuf_copy(r, p) != ERR_OK) {
+ 801fcaa:	6879      	ldr	r1, [r7, #4]
+ 801fcac:	6978      	ldr	r0, [r7, #20]
+ 801fcae:	f7f8 f847 	bl	8017d40 <pbuf_copy>
+ 801fcb2:	4603      	mov	r3, r0
+ 801fcb4:	2b00      	cmp	r3, #0
+ 801fcb6:	d003      	beq.n	801fcc0 <icmp_input+0x13c>
+          LWIP_DEBUGF(ICMP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("icmp_input: copying to new pbuf failed"));
+          pbuf_free(r);
+ 801fcb8:	6978      	ldr	r0, [r7, #20]
+ 801fcba:	f7f7 ff1d 	bl	8017af8 <pbuf_free>
+          goto icmperr;
+ 801fcbe:	e072      	b.n	801fda6 <icmp_input+0x222>
+        }
+        /* free the original p */
+        pbuf_free(p);
+ 801fcc0:	6878      	ldr	r0, [r7, #4]
+ 801fcc2:	f7f7 ff19 	bl	8017af8 <pbuf_free>
+        /* we now have an identical copy of p that has room for link headers */
+        p = r;
+ 801fcc6:	697b      	ldr	r3, [r7, #20]
+ 801fcc8:	607b      	str	r3, [r7, #4]
+ 801fcca:	e00f      	b.n	801fcec <icmp_input+0x168>
+      } else {
+        /* restore p->payload to point to icmp header (cannot fail) */
+        if (pbuf_remove_header(p, hlen + PBUF_LINK_HLEN + PBUF_LINK_ENCAPSULATION_HLEN)) {
+ 801fccc:	8c7b      	ldrh	r3, [r7, #34]	; 0x22
+ 801fcce:	330e      	adds	r3, #14
+ 801fcd0:	4619      	mov	r1, r3
+ 801fcd2:	6878      	ldr	r0, [r7, #4]
+ 801fcd4:	f7f7 fe8a 	bl	80179ec <pbuf_remove_header>
+ 801fcd8:	4603      	mov	r3, r0
+ 801fcda:	2b00      	cmp	r3, #0
+ 801fcdc:	d006      	beq.n	801fcec <icmp_input+0x168>
+          LWIP_ASSERT("icmp_input: restoring original p->payload failed\n", 0);
+ 801fcde:	4b37      	ldr	r3, [pc, #220]	; (801fdbc <icmp_input+0x238>)
+ 801fce0:	22c7      	movs	r2, #199	; 0xc7
+ 801fce2:	4939      	ldr	r1, [pc, #228]	; (801fdc8 <icmp_input+0x244>)
+ 801fce4:	4837      	ldr	r0, [pc, #220]	; (801fdc4 <icmp_input+0x240>)
+ 801fce6:	f001 fe4f 	bl	8021988 <iprintf>
+          goto icmperr;
+ 801fcea:	e05c      	b.n	801fda6 <icmp_input+0x222>
+      }
+#endif /* LWIP_ICMP_ECHO_CHECK_INPUT_PBUF_LEN */
+      /* At this point, all checks are OK. */
+      /* We generate an answer by switching the dest and src ip addresses,
+       * setting the icmp type to ECHO_RESPONSE and updating the checksum. */
+      iecho = (struct icmp_echo_hdr *)p->payload;
+ 801fcec:	687b      	ldr	r3, [r7, #4]
+ 801fcee:	685b      	ldr	r3, [r3, #4]
+ 801fcf0:	613b      	str	r3, [r7, #16]
+      if (pbuf_add_header(p, hlen)) {
+ 801fcf2:	8c7b      	ldrh	r3, [r7, #34]	; 0x22
+ 801fcf4:	4619      	mov	r1, r3
+ 801fcf6:	6878      	ldr	r0, [r7, #4]
+ 801fcf8:	f7f7 fe68 	bl	80179cc <pbuf_add_header>
+ 801fcfc:	4603      	mov	r3, r0
+ 801fcfe:	2b00      	cmp	r3, #0
+ 801fd00:	d13c      	bne.n	801fd7c <icmp_input+0x1f8>
+        LWIP_DEBUGF(ICMP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("Can't move over header in packet"));
+      } else {
+        err_t ret;
+        struct ip_hdr *iphdr = (struct ip_hdr *)p->payload;
+ 801fd02:	687b      	ldr	r3, [r7, #4]
+ 801fd04:	685b      	ldr	r3, [r3, #4]
+ 801fd06:	60fb      	str	r3, [r7, #12]
+        ip4_addr_copy(iphdr->src, *src);
+ 801fd08:	69fb      	ldr	r3, [r7, #28]
+ 801fd0a:	681a      	ldr	r2, [r3, #0]
+ 801fd0c:	68fb      	ldr	r3, [r7, #12]
+ 801fd0e:	60da      	str	r2, [r3, #12]
+        ip4_addr_copy(iphdr->dest, *ip4_current_src_addr());
+ 801fd10:	4b28      	ldr	r3, [pc, #160]	; (801fdb4 <icmp_input+0x230>)
+ 801fd12:	691a      	ldr	r2, [r3, #16]
+ 801fd14:	68fb      	ldr	r3, [r7, #12]
+ 801fd16:	611a      	str	r2, [r3, #16]
+        ICMPH_TYPE_SET(iecho, ICMP_ER);
+ 801fd18:	693b      	ldr	r3, [r7, #16]
+ 801fd1a:	2200      	movs	r2, #0
+ 801fd1c:	701a      	strb	r2, [r3, #0]
+#if CHECKSUM_GEN_ICMP
+        IF__NETIF_CHECKSUM_ENABLED(inp, NETIF_CHECKSUM_GEN_ICMP) {
+          /* adjust the checksum */
+          if (iecho->chksum > PP_HTONS(0xffffU - (ICMP_ECHO << 8))) {
+ 801fd1e:	693b      	ldr	r3, [r7, #16]
+ 801fd20:	885b      	ldrh	r3, [r3, #2]
+ 801fd22:	b29b      	uxth	r3, r3
+ 801fd24:	f64f 72f7 	movw	r2, #65527	; 0xfff7
+ 801fd28:	4293      	cmp	r3, r2
+ 801fd2a:	d907      	bls.n	801fd3c <icmp_input+0x1b8>
+            iecho->chksum = (u16_t)(iecho->chksum + PP_HTONS((u16_t)(ICMP_ECHO << 8)) + 1);
+ 801fd2c:	693b      	ldr	r3, [r7, #16]
+ 801fd2e:	885b      	ldrh	r3, [r3, #2]
+ 801fd30:	b29b      	uxth	r3, r3
+ 801fd32:	3309      	adds	r3, #9
+ 801fd34:	b29a      	uxth	r2, r3
+ 801fd36:	693b      	ldr	r3, [r7, #16]
+ 801fd38:	805a      	strh	r2, [r3, #2]
+ 801fd3a:	e006      	b.n	801fd4a <icmp_input+0x1c6>
+          } else {
+            iecho->chksum = (u16_t)(iecho->chksum + PP_HTONS(ICMP_ECHO << 8));
+ 801fd3c:	693b      	ldr	r3, [r7, #16]
+ 801fd3e:	885b      	ldrh	r3, [r3, #2]
+ 801fd40:	b29b      	uxth	r3, r3
+ 801fd42:	3308      	adds	r3, #8
+ 801fd44:	b29a      	uxth	r2, r3
+ 801fd46:	693b      	ldr	r3, [r7, #16]
+ 801fd48:	805a      	strh	r2, [r3, #2]
+#else /* CHECKSUM_GEN_ICMP */
+        iecho->chksum = 0;
+#endif /* CHECKSUM_GEN_ICMP */
+
+        /* Set the correct TTL and recalculate the header checksum. */
+        IPH_TTL_SET(iphdr, ICMP_TTL);
+ 801fd4a:	68fb      	ldr	r3, [r7, #12]
+ 801fd4c:	22ff      	movs	r2, #255	; 0xff
+ 801fd4e:	721a      	strb	r2, [r3, #8]
+        IPH_CHKSUM_SET(iphdr, 0);
+ 801fd50:	68fb      	ldr	r3, [r7, #12]
+ 801fd52:	2200      	movs	r2, #0
+ 801fd54:	729a      	strb	r2, [r3, #10]
+ 801fd56:	2200      	movs	r2, #0
+ 801fd58:	72da      	strb	r2, [r3, #11]
+        MIB2_STATS_INC(mib2.icmpoutmsgs);
+        /* increase number of echo replies attempted to send */
+        MIB2_STATS_INC(mib2.icmpoutechoreps);
+
+        /* send an ICMP packet */
+        ret = ip4_output_if(p, src, LWIP_IP_HDRINCL,
+ 801fd5a:	683b      	ldr	r3, [r7, #0]
+ 801fd5c:	9302      	str	r3, [sp, #8]
+ 801fd5e:	2301      	movs	r3, #1
+ 801fd60:	9301      	str	r3, [sp, #4]
+ 801fd62:	2300      	movs	r3, #0
+ 801fd64:	9300      	str	r3, [sp, #0]
+ 801fd66:	23ff      	movs	r3, #255	; 0xff
+ 801fd68:	2200      	movs	r2, #0
+ 801fd6a:	69f9      	ldr	r1, [r7, #28]
+ 801fd6c:	6878      	ldr	r0, [r7, #4]
+ 801fd6e:	f000 fa7f 	bl	8020270 <ip4_output_if>
+ 801fd72:	4603      	mov	r3, r0
+ 801fd74:	72fb      	strb	r3, [r7, #11]
+                            ICMP_TTL, 0, IP_PROTO_ICMP, inp);
+        if (ret != ERR_OK) {
+          LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: ip_output_if returned an error: %s\n", lwip_strerr(ret)));
+        }
+      }
+      break;
+ 801fd76:	e001      	b.n	801fd7c <icmp_input+0x1f8>
+      break;
+ 801fd78:	bf00      	nop
+ 801fd7a:	e000      	b.n	801fd7e <icmp_input+0x1fa>
+      break;
+ 801fd7c:	bf00      	nop
+      LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: ICMP type %"S16_F" code %"S16_F" not supported.\n",
+                               (s16_t)type, (s16_t)code));
+      ICMP_STATS_INC(icmp.proterr);
+      ICMP_STATS_INC(icmp.drop);
+  }
+  pbuf_free(p);
+ 801fd7e:	6878      	ldr	r0, [r7, #4]
+ 801fd80:	f7f7 feba 	bl	8017af8 <pbuf_free>
+  return;
+ 801fd84:	e013      	b.n	801fdae <icmp_input+0x22a>
+    goto lenerr;
+ 801fd86:	bf00      	nop
+ 801fd88:	e002      	b.n	801fd90 <icmp_input+0x20c>
+    goto lenerr;
+ 801fd8a:	bf00      	nop
+ 801fd8c:	e000      	b.n	801fd90 <icmp_input+0x20c>
+        goto lenerr;
+ 801fd8e:	bf00      	nop
+lenerr:
+  pbuf_free(p);
+ 801fd90:	6878      	ldr	r0, [r7, #4]
+ 801fd92:	f7f7 feb1 	bl	8017af8 <pbuf_free>
+  ICMP_STATS_INC(icmp.lenerr);
+  MIB2_STATS_INC(mib2.icmpinerrors);
+  return;
+ 801fd96:	e00a      	b.n	801fdae <icmp_input+0x22a>
+        goto icmperr;
+ 801fd98:	bf00      	nop
+ 801fd9a:	e004      	b.n	801fda6 <icmp_input+0x222>
+        goto icmperr;
+ 801fd9c:	bf00      	nop
+ 801fd9e:	e002      	b.n	801fda6 <icmp_input+0x222>
+          goto icmperr;
+ 801fda0:	bf00      	nop
+ 801fda2:	e000      	b.n	801fda6 <icmp_input+0x222>
+          goto icmperr;
+ 801fda4:	bf00      	nop
+#if LWIP_ICMP_ECHO_CHECK_INPUT_PBUF_LEN || !LWIP_MULTICAST_PING || !LWIP_BROADCAST_PING
+icmperr:
+  pbuf_free(p);
+ 801fda6:	6878      	ldr	r0, [r7, #4]
+ 801fda8:	f7f7 fea6 	bl	8017af8 <pbuf_free>
+  ICMP_STATS_INC(icmp.err);
+  MIB2_STATS_INC(mib2.icmpinerrors);
+  return;
+ 801fdac:	bf00      	nop
+#endif /* LWIP_ICMP_ECHO_CHECK_INPUT_PBUF_LEN || !LWIP_MULTICAST_PING || !LWIP_BROADCAST_PING */
+}
+ 801fdae:	3728      	adds	r7, #40	; 0x28
+ 801fdb0:	46bd      	mov	sp, r7
+ 801fdb2:	bd80      	pop	{r7, pc}
+ 801fdb4:	24013980 	.word	0x24013980
+ 801fdb8:	24013994 	.word	0x24013994
+ 801fdbc:	080266f4 	.word	0x080266f4
+ 801fdc0:	0802672c 	.word	0x0802672c
+ 801fdc4:	08026764 	.word	0x08026764
+ 801fdc8:	0802678c 	.word	0x0802678c
+
+0801fdcc <icmp_dest_unreach>:
+ *          p->payload pointing to the IP header
+ * @param t type of the 'unreachable' packet
+ */
+void
+icmp_dest_unreach(struct pbuf *p, enum icmp_dur_type t)
+{
+ 801fdcc:	b580      	push	{r7, lr}
+ 801fdce:	b082      	sub	sp, #8
+ 801fdd0:	af00      	add	r7, sp, #0
+ 801fdd2:	6078      	str	r0, [r7, #4]
+ 801fdd4:	460b      	mov	r3, r1
+ 801fdd6:	70fb      	strb	r3, [r7, #3]
+  MIB2_STATS_INC(mib2.icmpoutdestunreachs);
+  icmp_send_response(p, ICMP_DUR, t);
+ 801fdd8:	78fb      	ldrb	r3, [r7, #3]
+ 801fdda:	461a      	mov	r2, r3
+ 801fddc:	2103      	movs	r1, #3
+ 801fdde:	6878      	ldr	r0, [r7, #4]
+ 801fde0:	f000 f814 	bl	801fe0c <icmp_send_response>
+}
+ 801fde4:	bf00      	nop
+ 801fde6:	3708      	adds	r7, #8
+ 801fde8:	46bd      	mov	sp, r7
+ 801fdea:	bd80      	pop	{r7, pc}
+
+0801fdec <icmp_time_exceeded>:
+ *          p->payload pointing to the IP header
+ * @param t type of the 'time exceeded' packet
+ */
+void
+icmp_time_exceeded(struct pbuf *p, enum icmp_te_type t)
+{
+ 801fdec:	b580      	push	{r7, lr}
+ 801fdee:	b082      	sub	sp, #8
+ 801fdf0:	af00      	add	r7, sp, #0
+ 801fdf2:	6078      	str	r0, [r7, #4]
+ 801fdf4:	460b      	mov	r3, r1
+ 801fdf6:	70fb      	strb	r3, [r7, #3]
+  MIB2_STATS_INC(mib2.icmpouttimeexcds);
+  icmp_send_response(p, ICMP_TE, t);
+ 801fdf8:	78fb      	ldrb	r3, [r7, #3]
+ 801fdfa:	461a      	mov	r2, r3
+ 801fdfc:	210b      	movs	r1, #11
+ 801fdfe:	6878      	ldr	r0, [r7, #4]
+ 801fe00:	f000 f804 	bl	801fe0c <icmp_send_response>
+}
+ 801fe04:	bf00      	nop
+ 801fe06:	3708      	adds	r7, #8
+ 801fe08:	46bd      	mov	sp, r7
+ 801fe0a:	bd80      	pop	{r7, pc}
+
+0801fe0c <icmp_send_response>:
+ * @param type Type of the ICMP header
+ * @param code Code of the ICMP header
+ */
+static void
+icmp_send_response(struct pbuf *p, u8_t type, u8_t code)
+{
+ 801fe0c:	b580      	push	{r7, lr}
+ 801fe0e:	b08c      	sub	sp, #48	; 0x30
+ 801fe10:	af04      	add	r7, sp, #16
+ 801fe12:	6078      	str	r0, [r7, #4]
+ 801fe14:	460b      	mov	r3, r1
+ 801fe16:	70fb      	strb	r3, [r7, #3]
+ 801fe18:	4613      	mov	r3, r2
+ 801fe1a:	70bb      	strb	r3, [r7, #2]
+
+  /* increase number of messages attempted to send */
+  MIB2_STATS_INC(mib2.icmpoutmsgs);
+
+  /* ICMP header + IP header + 8 bytes of data */
+  q = pbuf_alloc(PBUF_IP, sizeof(struct icmp_echo_hdr) + IP_HLEN + ICMP_DEST_UNREACH_DATASIZE,
+ 801fe1c:	f44f 7220 	mov.w	r2, #640	; 0x280
+ 801fe20:	2124      	movs	r1, #36	; 0x24
+ 801fe22:	2022      	movs	r0, #34	; 0x22
+ 801fe24:	f7f7 fb80 	bl	8017528 <pbuf_alloc>
+ 801fe28:	61b8      	str	r0, [r7, #24]
+                 PBUF_RAM);
+  if (q == NULL) {
+ 801fe2a:	69bb      	ldr	r3, [r7, #24]
+ 801fe2c:	2b00      	cmp	r3, #0
+ 801fe2e:	d056      	beq.n	801fede <icmp_send_response+0xd2>
+    LWIP_DEBUGF(ICMP_DEBUG, ("icmp_time_exceeded: failed to allocate pbuf for ICMP packet.\n"));
+    MIB2_STATS_INC(mib2.icmpouterrors);
+    return;
+  }
+  LWIP_ASSERT("check that first pbuf can hold icmp message",
+ 801fe30:	69bb      	ldr	r3, [r7, #24]
+ 801fe32:	895b      	ldrh	r3, [r3, #10]
+ 801fe34:	2b23      	cmp	r3, #35	; 0x23
+ 801fe36:	d806      	bhi.n	801fe46 <icmp_send_response+0x3a>
+ 801fe38:	4b2b      	ldr	r3, [pc, #172]	; (801fee8 <icmp_send_response+0xdc>)
+ 801fe3a:	f44f 72b4 	mov.w	r2, #360	; 0x168
+ 801fe3e:	492b      	ldr	r1, [pc, #172]	; (801feec <icmp_send_response+0xe0>)
+ 801fe40:	482b      	ldr	r0, [pc, #172]	; (801fef0 <icmp_send_response+0xe4>)
+ 801fe42:	f001 fda1 	bl	8021988 <iprintf>
+              (q->len >= (sizeof(struct icmp_echo_hdr) + IP_HLEN + ICMP_DEST_UNREACH_DATASIZE)));
+
+  iphdr = (struct ip_hdr *)p->payload;
+ 801fe46:	687b      	ldr	r3, [r7, #4]
+ 801fe48:	685b      	ldr	r3, [r3, #4]
+ 801fe4a:	617b      	str	r3, [r7, #20]
+  ip4_addr_debug_print_val(ICMP_DEBUG, iphdr->src);
+  LWIP_DEBUGF(ICMP_DEBUG, (" to "));
+  ip4_addr_debug_print_val(ICMP_DEBUG, iphdr->dest);
+  LWIP_DEBUGF(ICMP_DEBUG, ("\n"));
+
+  icmphdr = (struct icmp_echo_hdr *)q->payload;
+ 801fe4c:	69bb      	ldr	r3, [r7, #24]
+ 801fe4e:	685b      	ldr	r3, [r3, #4]
+ 801fe50:	613b      	str	r3, [r7, #16]
+  icmphdr->type = type;
+ 801fe52:	693b      	ldr	r3, [r7, #16]
+ 801fe54:	78fa      	ldrb	r2, [r7, #3]
+ 801fe56:	701a      	strb	r2, [r3, #0]
+  icmphdr->code = code;
+ 801fe58:	693b      	ldr	r3, [r7, #16]
+ 801fe5a:	78ba      	ldrb	r2, [r7, #2]
+ 801fe5c:	705a      	strb	r2, [r3, #1]
+  icmphdr->id = 0;
+ 801fe5e:	693b      	ldr	r3, [r7, #16]
+ 801fe60:	2200      	movs	r2, #0
+ 801fe62:	711a      	strb	r2, [r3, #4]
+ 801fe64:	2200      	movs	r2, #0
+ 801fe66:	715a      	strb	r2, [r3, #5]
+  icmphdr->seqno = 0;
+ 801fe68:	693b      	ldr	r3, [r7, #16]
+ 801fe6a:	2200      	movs	r2, #0
+ 801fe6c:	719a      	strb	r2, [r3, #6]
+ 801fe6e:	2200      	movs	r2, #0
+ 801fe70:	71da      	strb	r2, [r3, #7]
+
+  /* copy fields from original packet */
+  SMEMCPY((u8_t *)q->payload + sizeof(struct icmp_echo_hdr), (u8_t *)p->payload,
+ 801fe72:	69bb      	ldr	r3, [r7, #24]
+ 801fe74:	685b      	ldr	r3, [r3, #4]
+ 801fe76:	f103 0008 	add.w	r0, r3, #8
+ 801fe7a:	687b      	ldr	r3, [r7, #4]
+ 801fe7c:	685b      	ldr	r3, [r3, #4]
+ 801fe7e:	221c      	movs	r2, #28
+ 801fe80:	4619      	mov	r1, r3
+ 801fe82:	f001 ffb0 	bl	8021de6 <memcpy>
+          IP_HLEN + ICMP_DEST_UNREACH_DATASIZE);
+
+  ip4_addr_copy(iphdr_src, iphdr->src);
+ 801fe86:	697b      	ldr	r3, [r7, #20]
+ 801fe88:	68db      	ldr	r3, [r3, #12]
+ 801fe8a:	60fb      	str	r3, [r7, #12]
+    ip4_addr_t iphdr_dst;
+    ip4_addr_copy(iphdr_dst, iphdr->dest);
+    netif = ip4_route_src(&iphdr_dst, &iphdr_src);
+  }
+#else
+  netif = ip4_route(&iphdr_src);
+ 801fe8c:	f107 030c 	add.w	r3, r7, #12
+ 801fe90:	4618      	mov	r0, r3
+ 801fe92:	f000 f82f 	bl	801fef4 <ip4_route>
+ 801fe96:	61f8      	str	r0, [r7, #28]
+#endif
+  if (netif != NULL) {
+ 801fe98:	69fb      	ldr	r3, [r7, #28]
+ 801fe9a:	2b00      	cmp	r3, #0
+ 801fe9c:	d01b      	beq.n	801fed6 <icmp_send_response+0xca>
+    /* calculate checksum */
+    icmphdr->chksum = 0;
+ 801fe9e:	693b      	ldr	r3, [r7, #16]
+ 801fea0:	2200      	movs	r2, #0
+ 801fea2:	709a      	strb	r2, [r3, #2]
+ 801fea4:	2200      	movs	r2, #0
+ 801fea6:	70da      	strb	r2, [r3, #3]
+#if CHECKSUM_GEN_ICMP
+    IF__NETIF_CHECKSUM_ENABLED(netif, NETIF_CHECKSUM_GEN_ICMP) {
+      icmphdr->chksum = inet_chksum(icmphdr, q->len);
+ 801fea8:	69bb      	ldr	r3, [r7, #24]
+ 801feaa:	895b      	ldrh	r3, [r3, #10]
+ 801feac:	4619      	mov	r1, r3
+ 801feae:	6938      	ldr	r0, [r7, #16]
+ 801feb0:	f7f6 f8d1 	bl	8016056 <inet_chksum>
+ 801feb4:	4603      	mov	r3, r0
+ 801feb6:	461a      	mov	r2, r3
+ 801feb8:	693b      	ldr	r3, [r7, #16]
+ 801feba:	805a      	strh	r2, [r3, #2]
+    }
+#endif
+    ICMP_STATS_INC(icmp.xmit);
+    ip4_output_if(q, NULL, &iphdr_src, ICMP_TTL, 0, IP_PROTO_ICMP, netif);
+ 801febc:	f107 020c 	add.w	r2, r7, #12
+ 801fec0:	69fb      	ldr	r3, [r7, #28]
+ 801fec2:	9302      	str	r3, [sp, #8]
+ 801fec4:	2301      	movs	r3, #1
+ 801fec6:	9301      	str	r3, [sp, #4]
+ 801fec8:	2300      	movs	r3, #0
+ 801feca:	9300      	str	r3, [sp, #0]
+ 801fecc:	23ff      	movs	r3, #255	; 0xff
+ 801fece:	2100      	movs	r1, #0
+ 801fed0:	69b8      	ldr	r0, [r7, #24]
+ 801fed2:	f000 f9cd 	bl	8020270 <ip4_output_if>
+  }
+  pbuf_free(q);
+ 801fed6:	69b8      	ldr	r0, [r7, #24]
+ 801fed8:	f7f7 fe0e 	bl	8017af8 <pbuf_free>
+ 801fedc:	e000      	b.n	801fee0 <icmp_send_response+0xd4>
+    return;
+ 801fede:	bf00      	nop
+}
+ 801fee0:	3720      	adds	r7, #32
+ 801fee2:	46bd      	mov	sp, r7
+ 801fee4:	bd80      	pop	{r7, pc}
+ 801fee6:	bf00      	nop
+ 801fee8:	080266f4 	.word	0x080266f4
+ 801feec:	080267c0 	.word	0x080267c0
+ 801fef0:	08026764 	.word	0x08026764
+
+0801fef4 <ip4_route>:
+ * @param dest the destination IP address for which to find the route
+ * @return the netif on which to send to reach dest
+ */
+struct netif *
+ip4_route(const ip4_addr_t *dest)
+{
+ 801fef4:	b480      	push	{r7}
+ 801fef6:	b085      	sub	sp, #20
+ 801fef8:	af00      	add	r7, sp, #0
+ 801fefa:	6078      	str	r0, [r7, #4]
+
+  /* bug #54569: in case LWIP_SINGLE_NETIF=1 and LWIP_DEBUGF() disabled, the following loop is optimized away */
+  LWIP_UNUSED_ARG(dest);
+
+  /* iterate through netifs */
+  NETIF_FOREACH(netif) {
+ 801fefc:	4b33      	ldr	r3, [pc, #204]	; (801ffcc <ip4_route+0xd8>)
+ 801fefe:	681b      	ldr	r3, [r3, #0]
+ 801ff00:	60fb      	str	r3, [r7, #12]
+ 801ff02:	e036      	b.n	801ff72 <ip4_route+0x7e>
+    /* is the netif up, does it have a link and a valid address? */
+    if (netif_is_up(netif) && netif_is_link_up(netif) && !ip4_addr_isany_val(*netif_ip4_addr(netif))) {
+ 801ff04:	68fb      	ldr	r3, [r7, #12]
+ 801ff06:	f893 302d 	ldrb.w	r3, [r3, #45]	; 0x2d
+ 801ff0a:	f003 0301 	and.w	r3, r3, #1
+ 801ff0e:	b2db      	uxtb	r3, r3
+ 801ff10:	2b00      	cmp	r3, #0
+ 801ff12:	d02b      	beq.n	801ff6c <ip4_route+0x78>
+ 801ff14:	68fb      	ldr	r3, [r7, #12]
+ 801ff16:	f893 302d 	ldrb.w	r3, [r3, #45]	; 0x2d
+ 801ff1a:	089b      	lsrs	r3, r3, #2
+ 801ff1c:	f003 0301 	and.w	r3, r3, #1
+ 801ff20:	b2db      	uxtb	r3, r3
+ 801ff22:	2b00      	cmp	r3, #0
+ 801ff24:	d022      	beq.n	801ff6c <ip4_route+0x78>
+ 801ff26:	68fb      	ldr	r3, [r7, #12]
+ 801ff28:	3304      	adds	r3, #4
+ 801ff2a:	681b      	ldr	r3, [r3, #0]
+ 801ff2c:	2b00      	cmp	r3, #0
+ 801ff2e:	d01d      	beq.n	801ff6c <ip4_route+0x78>
+      /* network mask matches? */
+      if (ip4_addr_netcmp(dest, netif_ip4_addr(netif), netif_ip4_netmask(netif))) {
+ 801ff30:	687b      	ldr	r3, [r7, #4]
+ 801ff32:	681a      	ldr	r2, [r3, #0]
+ 801ff34:	68fb      	ldr	r3, [r7, #12]
+ 801ff36:	3304      	adds	r3, #4
+ 801ff38:	681b      	ldr	r3, [r3, #0]
+ 801ff3a:	405a      	eors	r2, r3
+ 801ff3c:	68fb      	ldr	r3, [r7, #12]
+ 801ff3e:	3308      	adds	r3, #8
+ 801ff40:	681b      	ldr	r3, [r3, #0]
+ 801ff42:	4013      	ands	r3, r2
+ 801ff44:	2b00      	cmp	r3, #0
+ 801ff46:	d101      	bne.n	801ff4c <ip4_route+0x58>
+        /* return netif on which to forward IP packet */
+        return netif;
+ 801ff48:	68fb      	ldr	r3, [r7, #12]
+ 801ff4a:	e038      	b.n	801ffbe <ip4_route+0xca>
+      }
+      /* gateway matches on a non broadcast interface? (i.e. peer in a point to point interface) */
+      if (((netif->flags & NETIF_FLAG_BROADCAST) == 0) && ip4_addr_cmp(dest, netif_ip4_gw(netif))) {
+ 801ff4c:	68fb      	ldr	r3, [r7, #12]
+ 801ff4e:	f893 302d 	ldrb.w	r3, [r3, #45]	; 0x2d
+ 801ff52:	f003 0302 	and.w	r3, r3, #2
+ 801ff56:	2b00      	cmp	r3, #0
+ 801ff58:	d108      	bne.n	801ff6c <ip4_route+0x78>
+ 801ff5a:	687b      	ldr	r3, [r7, #4]
+ 801ff5c:	681a      	ldr	r2, [r3, #0]
+ 801ff5e:	68fb      	ldr	r3, [r7, #12]
+ 801ff60:	330c      	adds	r3, #12
+ 801ff62:	681b      	ldr	r3, [r3, #0]
+ 801ff64:	429a      	cmp	r2, r3
+ 801ff66:	d101      	bne.n	801ff6c <ip4_route+0x78>
+        /* return netif on which to forward IP packet */
+        return netif;
+ 801ff68:	68fb      	ldr	r3, [r7, #12]
+ 801ff6a:	e028      	b.n	801ffbe <ip4_route+0xca>
+  NETIF_FOREACH(netif) {
+ 801ff6c:	68fb      	ldr	r3, [r7, #12]
+ 801ff6e:	681b      	ldr	r3, [r3, #0]
+ 801ff70:	60fb      	str	r3, [r7, #12]
+ 801ff72:	68fb      	ldr	r3, [r7, #12]
+ 801ff74:	2b00      	cmp	r3, #0
+ 801ff76:	d1c5      	bne.n	801ff04 <ip4_route+0x10>
+    return netif;
+  }
+#endif
+#endif /* !LWIP_SINGLE_NETIF */
+
+  if ((netif_default == NULL) || !netif_is_up(netif_default) || !netif_is_link_up(netif_default) ||
+ 801ff78:	4b15      	ldr	r3, [pc, #84]	; (801ffd0 <ip4_route+0xdc>)
+ 801ff7a:	681b      	ldr	r3, [r3, #0]
+ 801ff7c:	2b00      	cmp	r3, #0
+ 801ff7e:	d01a      	beq.n	801ffb6 <ip4_route+0xc2>
+ 801ff80:	4b13      	ldr	r3, [pc, #76]	; (801ffd0 <ip4_route+0xdc>)
+ 801ff82:	681b      	ldr	r3, [r3, #0]
+ 801ff84:	f893 302d 	ldrb.w	r3, [r3, #45]	; 0x2d
+ 801ff88:	f003 0301 	and.w	r3, r3, #1
+ 801ff8c:	2b00      	cmp	r3, #0
+ 801ff8e:	d012      	beq.n	801ffb6 <ip4_route+0xc2>
+ 801ff90:	4b0f      	ldr	r3, [pc, #60]	; (801ffd0 <ip4_route+0xdc>)
+ 801ff92:	681b      	ldr	r3, [r3, #0]
+ 801ff94:	f893 302d 	ldrb.w	r3, [r3, #45]	; 0x2d
+ 801ff98:	f003 0304 	and.w	r3, r3, #4
+ 801ff9c:	2b00      	cmp	r3, #0
+ 801ff9e:	d00a      	beq.n	801ffb6 <ip4_route+0xc2>
+      ip4_addr_isany_val(*netif_ip4_addr(netif_default)) || ip4_addr_isloopback(dest)) {
+ 801ffa0:	4b0b      	ldr	r3, [pc, #44]	; (801ffd0 <ip4_route+0xdc>)
+ 801ffa2:	681b      	ldr	r3, [r3, #0]
+ 801ffa4:	3304      	adds	r3, #4
+ 801ffa6:	681b      	ldr	r3, [r3, #0]
+  if ((netif_default == NULL) || !netif_is_up(netif_default) || !netif_is_link_up(netif_default) ||
+ 801ffa8:	2b00      	cmp	r3, #0
+ 801ffaa:	d004      	beq.n	801ffb6 <ip4_route+0xc2>
+      ip4_addr_isany_val(*netif_ip4_addr(netif_default)) || ip4_addr_isloopback(dest)) {
+ 801ffac:	687b      	ldr	r3, [r7, #4]
+ 801ffae:	681b      	ldr	r3, [r3, #0]
+ 801ffb0:	b2db      	uxtb	r3, r3
+ 801ffb2:	2b7f      	cmp	r3, #127	; 0x7f
+ 801ffb4:	d101      	bne.n	801ffba <ip4_route+0xc6>
+       If this is not good enough for you, use LWIP_HOOK_IP4_ROUTE() */
+    LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("ip4_route: No route to %"U16_F".%"U16_F".%"U16_F".%"U16_F"\n",
+                ip4_addr1_16(dest), ip4_addr2_16(dest), ip4_addr3_16(dest), ip4_addr4_16(dest)));
+    IP_STATS_INC(ip.rterr);
+    MIB2_STATS_INC(mib2.ipoutnoroutes);
+    return NULL;
+ 801ffb6:	2300      	movs	r3, #0
+ 801ffb8:	e001      	b.n	801ffbe <ip4_route+0xca>
+  }
+
+  return netif_default;
+ 801ffba:	4b05      	ldr	r3, [pc, #20]	; (801ffd0 <ip4_route+0xdc>)
+ 801ffbc:	681b      	ldr	r3, [r3, #0]
+}
+ 801ffbe:	4618      	mov	r0, r3
+ 801ffc0:	3714      	adds	r7, #20
+ 801ffc2:	46bd      	mov	sp, r7
+ 801ffc4:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 801ffc8:	4770      	bx	lr
+ 801ffca:	bf00      	nop
+ 801ffcc:	2401a474 	.word	0x2401a474
+ 801ffd0:	2401a478 	.word	0x2401a478
+
+0801ffd4 <ip4_input_accept>:
+#endif /* IP_FORWARD */
+
+/** Return true if the current input packet should be accepted on this netif */
+static int
+ip4_input_accept(struct netif *netif)
+{
+ 801ffd4:	b580      	push	{r7, lr}
+ 801ffd6:	b082      	sub	sp, #8
+ 801ffd8:	af00      	add	r7, sp, #0
+ 801ffda:	6078      	str	r0, [r7, #4]
+                         ip4_addr_get_u32(ip4_current_dest_addr()) & ip4_addr_get_u32(netif_ip4_netmask(netif)),
+                         ip4_addr_get_u32(netif_ip4_addr(netif)) & ip4_addr_get_u32(netif_ip4_netmask(netif)),
+                         ip4_addr_get_u32(ip4_current_dest_addr()) & ~ip4_addr_get_u32(netif_ip4_netmask(netif))));
+
+  /* interface is up and configured? */
+  if ((netif_is_up(netif)) && (!ip4_addr_isany_val(*netif_ip4_addr(netif)))) {
+ 801ffdc:	687b      	ldr	r3, [r7, #4]
+ 801ffde:	f893 302d 	ldrb.w	r3, [r3, #45]	; 0x2d
+ 801ffe2:	f003 0301 	and.w	r3, r3, #1
+ 801ffe6:	b2db      	uxtb	r3, r3
+ 801ffe8:	2b00      	cmp	r3, #0
+ 801ffea:	d016      	beq.n	802001a <ip4_input_accept+0x46>
+ 801ffec:	687b      	ldr	r3, [r7, #4]
+ 801ffee:	3304      	adds	r3, #4
+ 801fff0:	681b      	ldr	r3, [r3, #0]
+ 801fff2:	2b00      	cmp	r3, #0
+ 801fff4:	d011      	beq.n	802001a <ip4_input_accept+0x46>
+    /* unicast to this interface address? */
+    if (ip4_addr_cmp(ip4_current_dest_addr(), netif_ip4_addr(netif)) ||
+ 801fff6:	4b0b      	ldr	r3, [pc, #44]	; (8020024 <ip4_input_accept+0x50>)
+ 801fff8:	695a      	ldr	r2, [r3, #20]
+ 801fffa:	687b      	ldr	r3, [r7, #4]
+ 801fffc:	3304      	adds	r3, #4
+ 801fffe:	681b      	ldr	r3, [r3, #0]
+ 8020000:	429a      	cmp	r2, r3
+ 8020002:	d008      	beq.n	8020016 <ip4_input_accept+0x42>
+        /* or broadcast on this interface network address? */
+        ip4_addr_isbroadcast(ip4_current_dest_addr(), netif)
+ 8020004:	4b07      	ldr	r3, [pc, #28]	; (8020024 <ip4_input_accept+0x50>)
+ 8020006:	695b      	ldr	r3, [r3, #20]
+ 8020008:	6879      	ldr	r1, [r7, #4]
+ 802000a:	4618      	mov	r0, r3
+ 802000c:	f000 fa08 	bl	8020420 <ip4_addr_isbroadcast_u32>
+ 8020010:	4603      	mov	r3, r0
+    if (ip4_addr_cmp(ip4_current_dest_addr(), netif_ip4_addr(netif)) ||
+ 8020012:	2b00      	cmp	r3, #0
+ 8020014:	d001      	beq.n	802001a <ip4_input_accept+0x46>
+#endif /* LWIP_NETIF_LOOPBACK && !LWIP_HAVE_LOOPIF */
+       ) {
+      LWIP_DEBUGF(IP_DEBUG, ("ip4_input: packet accepted on interface %c%c\n",
+                             netif->name[0], netif->name[1]));
+      /* accept on this netif */
+      return 1;
+ 8020016:	2301      	movs	r3, #1
+ 8020018:	e000      	b.n	802001c <ip4_input_accept+0x48>
+      /* accept on this netif */
+      return 1;
+    }
+#endif /* LWIP_AUTOIP */
+  }
+  return 0;
+ 802001a:	2300      	movs	r3, #0
+}
+ 802001c:	4618      	mov	r0, r3
+ 802001e:	3708      	adds	r7, #8
+ 8020020:	46bd      	mov	sp, r7
+ 8020022:	bd80      	pop	{r7, pc}
+ 8020024:	24013980 	.word	0x24013980
+
+08020028 <ip4_input>:
+ * @return ERR_OK if the packet was processed (could return ERR_* if it wasn't
+ *         processed, but currently always returns ERR_OK)
+ */
+err_t
+ip4_input(struct pbuf *p, struct netif *inp)
+{
+ 8020028:	b580      	push	{r7, lr}
+ 802002a:	b086      	sub	sp, #24
+ 802002c:	af00      	add	r7, sp, #0
+ 802002e:	6078      	str	r0, [r7, #4]
+ 8020030:	6039      	str	r1, [r7, #0]
+
+  IP_STATS_INC(ip.recv);
+  MIB2_STATS_INC(mib2.ipinreceives);
+
+  /* identify the IP header */
+  iphdr = (struct ip_hdr *)p->payload;
+ 8020032:	687b      	ldr	r3, [r7, #4]
+ 8020034:	685b      	ldr	r3, [r3, #4]
+ 8020036:	613b      	str	r3, [r7, #16]
+  if (IPH_V(iphdr) != 4) {
+ 8020038:	693b      	ldr	r3, [r7, #16]
+ 802003a:	781b      	ldrb	r3, [r3, #0]
+ 802003c:	091b      	lsrs	r3, r3, #4
+ 802003e:	b2db      	uxtb	r3, r3
+ 8020040:	2b04      	cmp	r3, #4
+ 8020042:	d004      	beq.n	802004e <ip4_input+0x26>
+    LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_LEVEL_WARNING, ("IP packet dropped due to bad version number %"U16_F"\n", (u16_t)IPH_V(iphdr)));
+    ip4_debug_print(p);
+    pbuf_free(p);
+ 8020044:	6878      	ldr	r0, [r7, #4]
+ 8020046:	f7f7 fd57 	bl	8017af8 <pbuf_free>
+    IP_STATS_INC(ip.err);
+    IP_STATS_INC(ip.drop);
+    MIB2_STATS_INC(mib2.ipinhdrerrors);
+    return ERR_OK;
+ 802004a:	2300      	movs	r3, #0
+ 802004c:	e107      	b.n	802025e <ip4_input+0x236>
+    return ERR_OK;
+  }
+#endif
+
+  /* obtain IP header length in bytes */
+  iphdr_hlen = IPH_HL_BYTES(iphdr);
+ 802004e:	693b      	ldr	r3, [r7, #16]
+ 8020050:	781b      	ldrb	r3, [r3, #0]
+ 8020052:	f003 030f 	and.w	r3, r3, #15
+ 8020056:	b2db      	uxtb	r3, r3
+ 8020058:	009b      	lsls	r3, r3, #2
+ 802005a:	b2db      	uxtb	r3, r3
+ 802005c:	81fb      	strh	r3, [r7, #14]
+  /* obtain ip length in bytes */
+  iphdr_len = lwip_ntohs(IPH_LEN(iphdr));
+ 802005e:	693b      	ldr	r3, [r7, #16]
+ 8020060:	885b      	ldrh	r3, [r3, #2]
+ 8020062:	b29b      	uxth	r3, r3
+ 8020064:	4618      	mov	r0, r3
+ 8020066:	f7f5 ff6b 	bl	8015f40 <lwip_htons>
+ 802006a:	4603      	mov	r3, r0
+ 802006c:	81bb      	strh	r3, [r7, #12]
+
+  /* Trim pbuf. This is especially required for packets < 60 bytes. */
+  if (iphdr_len < p->tot_len) {
+ 802006e:	687b      	ldr	r3, [r7, #4]
+ 8020070:	891b      	ldrh	r3, [r3, #8]
+ 8020072:	89ba      	ldrh	r2, [r7, #12]
+ 8020074:	429a      	cmp	r2, r3
+ 8020076:	d204      	bcs.n	8020082 <ip4_input+0x5a>
+    pbuf_realloc(p, iphdr_len);
+ 8020078:	89bb      	ldrh	r3, [r7, #12]
+ 802007a:	4619      	mov	r1, r3
+ 802007c:	6878      	ldr	r0, [r7, #4]
+ 802007e:	f7f7 fbb5 	bl	80177ec <pbuf_realloc>
+  }
+
+  /* header length exceeds first pbuf length, or ip length exceeds total pbuf length? */
+  if ((iphdr_hlen > p->len) || (iphdr_len > p->tot_len) || (iphdr_hlen < IP_HLEN)) {
+ 8020082:	687b      	ldr	r3, [r7, #4]
+ 8020084:	895b      	ldrh	r3, [r3, #10]
+ 8020086:	89fa      	ldrh	r2, [r7, #14]
+ 8020088:	429a      	cmp	r2, r3
+ 802008a:	d807      	bhi.n	802009c <ip4_input+0x74>
+ 802008c:	687b      	ldr	r3, [r7, #4]
+ 802008e:	891b      	ldrh	r3, [r3, #8]
+ 8020090:	89ba      	ldrh	r2, [r7, #12]
+ 8020092:	429a      	cmp	r2, r3
+ 8020094:	d802      	bhi.n	802009c <ip4_input+0x74>
+ 8020096:	89fb      	ldrh	r3, [r7, #14]
+ 8020098:	2b13      	cmp	r3, #19
+ 802009a:	d804      	bhi.n	80200a6 <ip4_input+0x7e>
+      LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_LEVEL_SERIOUS,
+                  ("IP (len %"U16_F") is longer than pbuf (len %"U16_F"), IP packet dropped.\n",
+                   iphdr_len, p->tot_len));
+    }
+    /* free (drop) packet pbufs */
+    pbuf_free(p);
+ 802009c:	6878      	ldr	r0, [r7, #4]
+ 802009e:	f7f7 fd2b 	bl	8017af8 <pbuf_free>
+    IP_STATS_INC(ip.lenerr);
+    IP_STATS_INC(ip.drop);
+    MIB2_STATS_INC(mib2.ipindiscards);
+    return ERR_OK;
+ 80200a2:	2300      	movs	r3, #0
+ 80200a4:	e0db      	b.n	802025e <ip4_input+0x236>
+    }
+  }
+#endif
+
+  /* copy IP addresses to aligned ip_addr_t */
+  ip_addr_copy_from_ip4(ip_data.current_iphdr_dest, iphdr->dest);
+ 80200a6:	693b      	ldr	r3, [r7, #16]
+ 80200a8:	691b      	ldr	r3, [r3, #16]
+ 80200aa:	4a6f      	ldr	r2, [pc, #444]	; (8020268 <ip4_input+0x240>)
+ 80200ac:	6153      	str	r3, [r2, #20]
+  ip_addr_copy_from_ip4(ip_data.current_iphdr_src, iphdr->src);
+ 80200ae:	693b      	ldr	r3, [r7, #16]
+ 80200b0:	68db      	ldr	r3, [r3, #12]
+ 80200b2:	4a6d      	ldr	r2, [pc, #436]	; (8020268 <ip4_input+0x240>)
+ 80200b4:	6113      	str	r3, [r2, #16]
+
+  /* match packet against an interface, i.e. is this packet for us? */
+  if (ip4_addr_ismulticast(ip4_current_dest_addr())) {
+ 80200b6:	4b6c      	ldr	r3, [pc, #432]	; (8020268 <ip4_input+0x240>)
+ 80200b8:	695b      	ldr	r3, [r3, #20]
+ 80200ba:	f003 03f0 	and.w	r3, r3, #240	; 0xf0
+ 80200be:	2be0      	cmp	r3, #224	; 0xe0
+ 80200c0:	d112      	bne.n	80200e8 <ip4_input+0xc0>
+      netif = inp;
+    } else {
+      netif = NULL;
+    }
+#else /* LWIP_IGMP */
+    if ((netif_is_up(inp)) && (!ip4_addr_isany_val(*netif_ip4_addr(inp)))) {
+ 80200c2:	683b      	ldr	r3, [r7, #0]
+ 80200c4:	f893 302d 	ldrb.w	r3, [r3, #45]	; 0x2d
+ 80200c8:	f003 0301 	and.w	r3, r3, #1
+ 80200cc:	b2db      	uxtb	r3, r3
+ 80200ce:	2b00      	cmp	r3, #0
+ 80200d0:	d007      	beq.n	80200e2 <ip4_input+0xba>
+ 80200d2:	683b      	ldr	r3, [r7, #0]
+ 80200d4:	3304      	adds	r3, #4
+ 80200d6:	681b      	ldr	r3, [r3, #0]
+ 80200d8:	2b00      	cmp	r3, #0
+ 80200da:	d002      	beq.n	80200e2 <ip4_input+0xba>
+      netif = inp;
+ 80200dc:	683b      	ldr	r3, [r7, #0]
+ 80200de:	617b      	str	r3, [r7, #20]
+ 80200e0:	e02a      	b.n	8020138 <ip4_input+0x110>
+    } else {
+      netif = NULL;
+ 80200e2:	2300      	movs	r3, #0
+ 80200e4:	617b      	str	r3, [r7, #20]
+ 80200e6:	e027      	b.n	8020138 <ip4_input+0x110>
+    }
+#endif /* LWIP_IGMP */
+  } else {
+    /* start trying with inp. if that's not acceptable, start walking the
+       list of configured netifs. */
+    if (ip4_input_accept(inp)) {
+ 80200e8:	6838      	ldr	r0, [r7, #0]
+ 80200ea:	f7ff ff73 	bl	801ffd4 <ip4_input_accept>
+ 80200ee:	4603      	mov	r3, r0
+ 80200f0:	2b00      	cmp	r3, #0
+ 80200f2:	d002      	beq.n	80200fa <ip4_input+0xd2>
+      netif = inp;
+ 80200f4:	683b      	ldr	r3, [r7, #0]
+ 80200f6:	617b      	str	r3, [r7, #20]
+ 80200f8:	e01e      	b.n	8020138 <ip4_input+0x110>
+    } else {
+      netif = NULL;
+ 80200fa:	2300      	movs	r3, #0
+ 80200fc:	617b      	str	r3, [r7, #20]
+#if !LWIP_NETIF_LOOPBACK || LWIP_HAVE_LOOPIF
+      /* Packets sent to the loopback address must not be accepted on an
+       * interface that does not have the loopback address assigned to it,
+       * unless a non-loopback interface is used for loopback traffic. */
+      if (!ip4_addr_isloopback(ip4_current_dest_addr()))
+ 80200fe:	4b5a      	ldr	r3, [pc, #360]	; (8020268 <ip4_input+0x240>)
+ 8020100:	695b      	ldr	r3, [r3, #20]
+ 8020102:	b2db      	uxtb	r3, r3
+ 8020104:	2b7f      	cmp	r3, #127	; 0x7f
+ 8020106:	d017      	beq.n	8020138 <ip4_input+0x110>
+#endif /* !LWIP_NETIF_LOOPBACK || LWIP_HAVE_LOOPIF */
+      {
+#if !LWIP_SINGLE_NETIF
+        NETIF_FOREACH(netif) {
+ 8020108:	4b58      	ldr	r3, [pc, #352]	; (802026c <ip4_input+0x244>)
+ 802010a:	681b      	ldr	r3, [r3, #0]
+ 802010c:	617b      	str	r3, [r7, #20]
+ 802010e:	e00e      	b.n	802012e <ip4_input+0x106>
+          if (netif == inp) {
+ 8020110:	697a      	ldr	r2, [r7, #20]
+ 8020112:	683b      	ldr	r3, [r7, #0]
+ 8020114:	429a      	cmp	r2, r3
+ 8020116:	d006      	beq.n	8020126 <ip4_input+0xfe>
+            /* we checked that before already */
+            continue;
+          }
+          if (ip4_input_accept(netif)) {
+ 8020118:	6978      	ldr	r0, [r7, #20]
+ 802011a:	f7ff ff5b 	bl	801ffd4 <ip4_input_accept>
+ 802011e:	4603      	mov	r3, r0
+ 8020120:	2b00      	cmp	r3, #0
+ 8020122:	d108      	bne.n	8020136 <ip4_input+0x10e>
+ 8020124:	e000      	b.n	8020128 <ip4_input+0x100>
+            continue;
+ 8020126:	bf00      	nop
+        NETIF_FOREACH(netif) {
+ 8020128:	697b      	ldr	r3, [r7, #20]
+ 802012a:	681b      	ldr	r3, [r3, #0]
+ 802012c:	617b      	str	r3, [r7, #20]
+ 802012e:	697b      	ldr	r3, [r7, #20]
+ 8020130:	2b00      	cmp	r3, #0
+ 8020132:	d1ed      	bne.n	8020110 <ip4_input+0xe8>
+ 8020134:	e000      	b.n	8020138 <ip4_input+0x110>
+            break;
+ 8020136:	bf00      	nop
+      && !ip4_addr_isany_val(*ip4_current_src_addr())
+#endif /* IP_ACCEPT_LINK_LAYER_ADDRESSING */
+     )
+#endif /* LWIP_IGMP || IP_ACCEPT_LINK_LAYER_ADDRESSING */
+  {
+    if ((ip4_addr_isbroadcast(ip4_current_src_addr(), inp)) ||
+ 8020138:	4b4b      	ldr	r3, [pc, #300]	; (8020268 <ip4_input+0x240>)
+ 802013a:	691b      	ldr	r3, [r3, #16]
+ 802013c:	6839      	ldr	r1, [r7, #0]
+ 802013e:	4618      	mov	r0, r3
+ 8020140:	f000 f96e 	bl	8020420 <ip4_addr_isbroadcast_u32>
+ 8020144:	4603      	mov	r3, r0
+ 8020146:	2b00      	cmp	r3, #0
+ 8020148:	d105      	bne.n	8020156 <ip4_input+0x12e>
+        (ip4_addr_ismulticast(ip4_current_src_addr()))) {
+ 802014a:	4b47      	ldr	r3, [pc, #284]	; (8020268 <ip4_input+0x240>)
+ 802014c:	691b      	ldr	r3, [r3, #16]
+ 802014e:	f003 03f0 	and.w	r3, r3, #240	; 0xf0
+    if ((ip4_addr_isbroadcast(ip4_current_src_addr(), inp)) ||
+ 8020152:	2be0      	cmp	r3, #224	; 0xe0
+ 8020154:	d104      	bne.n	8020160 <ip4_input+0x138>
+      /* packet source is not valid */
+      LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_WARNING, ("ip4_input: packet source is not valid.\n"));
+      /* free (drop) packet pbufs */
+      pbuf_free(p);
+ 8020156:	6878      	ldr	r0, [r7, #4]
+ 8020158:	f7f7 fcce 	bl	8017af8 <pbuf_free>
+      IP_STATS_INC(ip.drop);
+      MIB2_STATS_INC(mib2.ipinaddrerrors);
+      MIB2_STATS_INC(mib2.ipindiscards);
+      return ERR_OK;
+ 802015c:	2300      	movs	r3, #0
+ 802015e:	e07e      	b.n	802025e <ip4_input+0x236>
+    }
+  }
+
+  /* packet not for us? */
+  if (netif == NULL) {
+ 8020160:	697b      	ldr	r3, [r7, #20]
+ 8020162:	2b00      	cmp	r3, #0
+ 8020164:	d104      	bne.n	8020170 <ip4_input+0x148>
+    {
+      IP_STATS_INC(ip.drop);
+      MIB2_STATS_INC(mib2.ipinaddrerrors);
+      MIB2_STATS_INC(mib2.ipindiscards);
+    }
+    pbuf_free(p);
+ 8020166:	6878      	ldr	r0, [r7, #4]
+ 8020168:	f7f7 fcc6 	bl	8017af8 <pbuf_free>
+    return ERR_OK;
+ 802016c:	2300      	movs	r3, #0
+ 802016e:	e076      	b.n	802025e <ip4_input+0x236>
+  }
+  /* packet consists of multiple fragments? */
+  if ((IPH_OFFSET(iphdr) & PP_HTONS(IP_OFFMASK | IP_MF)) != 0) {
+ 8020170:	693b      	ldr	r3, [r7, #16]
+ 8020172:	88db      	ldrh	r3, [r3, #6]
+ 8020174:	b29b      	uxth	r3, r3
+ 8020176:	461a      	mov	r2, r3
+ 8020178:	f64f 733f 	movw	r3, #65343	; 0xff3f
+ 802017c:	4013      	ands	r3, r2
+ 802017e:	2b00      	cmp	r3, #0
+ 8020180:	d00b      	beq.n	802019a <ip4_input+0x172>
+#if IP_REASSEMBLY /* packet fragment reassembly code present? */
+    LWIP_DEBUGF(IP_DEBUG, ("IP packet is a fragment (id=0x%04"X16_F" tot_len=%"U16_F" len=%"U16_F" MF=%"U16_F" offset=%"U16_F"), calling ip4_reass()\n",
+                           lwip_ntohs(IPH_ID(iphdr)), p->tot_len, lwip_ntohs(IPH_LEN(iphdr)), (u16_t)!!(IPH_OFFSET(iphdr) & PP_HTONS(IP_MF)), (u16_t)((lwip_ntohs(IPH_OFFSET(iphdr)) & IP_OFFMASK) * 8)));
+    /* reassemble the packet*/
+    p = ip4_reass(p);
+ 8020182:	6878      	ldr	r0, [r7, #4]
+ 8020184:	f000 fc92 	bl	8020aac <ip4_reass>
+ 8020188:	6078      	str	r0, [r7, #4]
+    /* packet not fully reassembled yet? */
+    if (p == NULL) {
+ 802018a:	687b      	ldr	r3, [r7, #4]
+ 802018c:	2b00      	cmp	r3, #0
+ 802018e:	d101      	bne.n	8020194 <ip4_input+0x16c>
+      return ERR_OK;
+ 8020190:	2300      	movs	r3, #0
+ 8020192:	e064      	b.n	802025e <ip4_input+0x236>
+    }
+    iphdr = (const struct ip_hdr *)p->payload;
+ 8020194:	687b      	ldr	r3, [r7, #4]
+ 8020196:	685b      	ldr	r3, [r3, #4]
+ 8020198:	613b      	str	r3, [r7, #16]
+  /* send to upper layers */
+  LWIP_DEBUGF(IP_DEBUG, ("ip4_input: \n"));
+  ip4_debug_print(p);
+  LWIP_DEBUGF(IP_DEBUG, ("ip4_input: p->len %"U16_F" p->tot_len %"U16_F"\n", p->len, p->tot_len));
+
+  ip_data.current_netif = netif;
+ 802019a:	4a33      	ldr	r2, [pc, #204]	; (8020268 <ip4_input+0x240>)
+ 802019c:	697b      	ldr	r3, [r7, #20]
+ 802019e:	6013      	str	r3, [r2, #0]
+  ip_data.current_input_netif = inp;
+ 80201a0:	4a31      	ldr	r2, [pc, #196]	; (8020268 <ip4_input+0x240>)
+ 80201a2:	683b      	ldr	r3, [r7, #0]
+ 80201a4:	6053      	str	r3, [r2, #4]
+  ip_data.current_ip4_header = iphdr;
+ 80201a6:	4a30      	ldr	r2, [pc, #192]	; (8020268 <ip4_input+0x240>)
+ 80201a8:	693b      	ldr	r3, [r7, #16]
+ 80201aa:	6093      	str	r3, [r2, #8]
+  ip_data.current_ip_header_tot_len = IPH_HL_BYTES(iphdr);
+ 80201ac:	693b      	ldr	r3, [r7, #16]
+ 80201ae:	781b      	ldrb	r3, [r3, #0]
+ 80201b0:	f003 030f 	and.w	r3, r3, #15
+ 80201b4:	b2db      	uxtb	r3, r3
+ 80201b6:	009b      	lsls	r3, r3, #2
+ 80201b8:	b2db      	uxtb	r3, r3
+ 80201ba:	b29a      	uxth	r2, r3
+ 80201bc:	4b2a      	ldr	r3, [pc, #168]	; (8020268 <ip4_input+0x240>)
+ 80201be:	819a      	strh	r2, [r3, #12]
+  /* raw input did not eat the packet? */
+  raw_status = raw_input(p, inp);
+  if (raw_status != RAW_INPUT_EATEN)
+#endif /* LWIP_RAW */
+  {
+    pbuf_remove_header(p, iphdr_hlen); /* Move to payload, no check necessary. */
+ 80201c0:	89fb      	ldrh	r3, [r7, #14]
+ 80201c2:	4619      	mov	r1, r3
+ 80201c4:	6878      	ldr	r0, [r7, #4]
+ 80201c6:	f7f7 fc11 	bl	80179ec <pbuf_remove_header>
+
+    switch (IPH_PROTO(iphdr)) {
+ 80201ca:	693b      	ldr	r3, [r7, #16]
+ 80201cc:	7a5b      	ldrb	r3, [r3, #9]
+ 80201ce:	2b11      	cmp	r3, #17
+ 80201d0:	d006      	beq.n	80201e0 <ip4_input+0x1b8>
+ 80201d2:	2b11      	cmp	r3, #17
+ 80201d4:	dc13      	bgt.n	80201fe <ip4_input+0x1d6>
+ 80201d6:	2b01      	cmp	r3, #1
+ 80201d8:	d00c      	beq.n	80201f4 <ip4_input+0x1cc>
+ 80201da:	2b06      	cmp	r3, #6
+ 80201dc:	d005      	beq.n	80201ea <ip4_input+0x1c2>
+ 80201de:	e00e      	b.n	80201fe <ip4_input+0x1d6>
+      case IP_PROTO_UDP:
+#if LWIP_UDPLITE
+      case IP_PROTO_UDPLITE:
+#endif /* LWIP_UDPLITE */
+        MIB2_STATS_INC(mib2.ipindelivers);
+        udp_input(p, inp);
+ 80201e0:	6839      	ldr	r1, [r7, #0]
+ 80201e2:	6878      	ldr	r0, [r7, #4]
+ 80201e4:	f7fe fa94 	bl	801e710 <udp_input>
+        break;
+ 80201e8:	e026      	b.n	8020238 <ip4_input+0x210>
+#endif /* LWIP_UDP */
+#if LWIP_TCP
+      case IP_PROTO_TCP:
+        MIB2_STATS_INC(mib2.ipindelivers);
+        tcp_input(p, inp);
+ 80201ea:	6839      	ldr	r1, [r7, #0]
+ 80201ec:	6878      	ldr	r0, [r7, #4]
+ 80201ee:	f7f9 fde1 	bl	8019db4 <tcp_input>
+        break;
+ 80201f2:	e021      	b.n	8020238 <ip4_input+0x210>
+#endif /* LWIP_TCP */
+#if LWIP_ICMP
+      case IP_PROTO_ICMP:
+        MIB2_STATS_INC(mib2.ipindelivers);
+        icmp_input(p, inp);
+ 80201f4:	6839      	ldr	r1, [r7, #0]
+ 80201f6:	6878      	ldr	r0, [r7, #4]
+ 80201f8:	f7ff fcc4 	bl	801fb84 <icmp_input>
+        break;
+ 80201fc:	e01c      	b.n	8020238 <ip4_input+0x210>
+        } else
+#endif /* LWIP_RAW */
+        {
+#if LWIP_ICMP
+          /* send ICMP destination protocol unreachable unless is was a broadcast */
+          if (!ip4_addr_isbroadcast(ip4_current_dest_addr(), netif) &&
+ 80201fe:	4b1a      	ldr	r3, [pc, #104]	; (8020268 <ip4_input+0x240>)
+ 8020200:	695b      	ldr	r3, [r3, #20]
+ 8020202:	6979      	ldr	r1, [r7, #20]
+ 8020204:	4618      	mov	r0, r3
+ 8020206:	f000 f90b 	bl	8020420 <ip4_addr_isbroadcast_u32>
+ 802020a:	4603      	mov	r3, r0
+ 802020c:	2b00      	cmp	r3, #0
+ 802020e:	d10f      	bne.n	8020230 <ip4_input+0x208>
+              !ip4_addr_ismulticast(ip4_current_dest_addr())) {
+ 8020210:	4b15      	ldr	r3, [pc, #84]	; (8020268 <ip4_input+0x240>)
+ 8020212:	695b      	ldr	r3, [r3, #20]
+ 8020214:	f003 03f0 	and.w	r3, r3, #240	; 0xf0
+          if (!ip4_addr_isbroadcast(ip4_current_dest_addr(), netif) &&
+ 8020218:	2be0      	cmp	r3, #224	; 0xe0
+ 802021a:	d009      	beq.n	8020230 <ip4_input+0x208>
+            pbuf_header_force(p, (s16_t)iphdr_hlen); /* Move to ip header, no check necessary. */
+ 802021c:	f9b7 300e 	ldrsh.w	r3, [r7, #14]
+ 8020220:	4619      	mov	r1, r3
+ 8020222:	6878      	ldr	r0, [r7, #4]
+ 8020224:	f7f7 fc55 	bl	8017ad2 <pbuf_header_force>
+            icmp_dest_unreach(p, ICMP_DUR_PROTO);
+ 8020228:	2102      	movs	r1, #2
+ 802022a:	6878      	ldr	r0, [r7, #4]
+ 802022c:	f7ff fdce 	bl	801fdcc <icmp_dest_unreach>
+
+          IP_STATS_INC(ip.proterr);
+          IP_STATS_INC(ip.drop);
+          MIB2_STATS_INC(mib2.ipinunknownprotos);
+        }
+        pbuf_free(p);
+ 8020230:	6878      	ldr	r0, [r7, #4]
+ 8020232:	f7f7 fc61 	bl	8017af8 <pbuf_free>
+        break;
+ 8020236:	bf00      	nop
+    }
+  }
+
+  /* @todo: this is not really necessary... */
+  ip_data.current_netif = NULL;
+ 8020238:	4b0b      	ldr	r3, [pc, #44]	; (8020268 <ip4_input+0x240>)
+ 802023a:	2200      	movs	r2, #0
+ 802023c:	601a      	str	r2, [r3, #0]
+  ip_data.current_input_netif = NULL;
+ 802023e:	4b0a      	ldr	r3, [pc, #40]	; (8020268 <ip4_input+0x240>)
+ 8020240:	2200      	movs	r2, #0
+ 8020242:	605a      	str	r2, [r3, #4]
+  ip_data.current_ip4_header = NULL;
+ 8020244:	4b08      	ldr	r3, [pc, #32]	; (8020268 <ip4_input+0x240>)
+ 8020246:	2200      	movs	r2, #0
+ 8020248:	609a      	str	r2, [r3, #8]
+  ip_data.current_ip_header_tot_len = 0;
+ 802024a:	4b07      	ldr	r3, [pc, #28]	; (8020268 <ip4_input+0x240>)
+ 802024c:	2200      	movs	r2, #0
+ 802024e:	819a      	strh	r2, [r3, #12]
+  ip4_addr_set_any(ip4_current_src_addr());
+ 8020250:	4b05      	ldr	r3, [pc, #20]	; (8020268 <ip4_input+0x240>)
+ 8020252:	2200      	movs	r2, #0
+ 8020254:	611a      	str	r2, [r3, #16]
+  ip4_addr_set_any(ip4_current_dest_addr());
+ 8020256:	4b04      	ldr	r3, [pc, #16]	; (8020268 <ip4_input+0x240>)
+ 8020258:	2200      	movs	r2, #0
+ 802025a:	615a      	str	r2, [r3, #20]
+
+  return ERR_OK;
+ 802025c:	2300      	movs	r3, #0
+}
+ 802025e:	4618      	mov	r0, r3
+ 8020260:	3718      	adds	r7, #24
+ 8020262:	46bd      	mov	sp, r7
+ 8020264:	bd80      	pop	{r7, pc}
+ 8020266:	bf00      	nop
+ 8020268:	24013980 	.word	0x24013980
+ 802026c:	2401a474 	.word	0x2401a474
+
+08020270 <ip4_output_if>:
+ */
+err_t
+ip4_output_if(struct pbuf *p, const ip4_addr_t *src, const ip4_addr_t *dest,
+              u8_t ttl, u8_t tos,
+              u8_t proto, struct netif *netif)
+{
+ 8020270:	b580      	push	{r7, lr}
+ 8020272:	b08a      	sub	sp, #40	; 0x28
+ 8020274:	af04      	add	r7, sp, #16
+ 8020276:	60f8      	str	r0, [r7, #12]
+ 8020278:	60b9      	str	r1, [r7, #8]
+ 802027a:	607a      	str	r2, [r7, #4]
+ 802027c:	70fb      	strb	r3, [r7, #3]
+ip4_output_if_opt(struct pbuf *p, const ip4_addr_t *src, const ip4_addr_t *dest,
+                  u8_t ttl, u8_t tos, u8_t proto, struct netif *netif, void *ip_options,
+                  u16_t optlen)
+{
+#endif /* IP_OPTIONS_SEND */
+  const ip4_addr_t *src_used = src;
+ 802027e:	68bb      	ldr	r3, [r7, #8]
+ 8020280:	617b      	str	r3, [r7, #20]
+  if (dest != LWIP_IP_HDRINCL) {
+ 8020282:	687b      	ldr	r3, [r7, #4]
+ 8020284:	2b00      	cmp	r3, #0
+ 8020286:	d009      	beq.n	802029c <ip4_output_if+0x2c>
+    if (ip4_addr_isany(src)) {
+ 8020288:	68bb      	ldr	r3, [r7, #8]
+ 802028a:	2b00      	cmp	r3, #0
+ 802028c:	d003      	beq.n	8020296 <ip4_output_if+0x26>
+ 802028e:	68bb      	ldr	r3, [r7, #8]
+ 8020290:	681b      	ldr	r3, [r3, #0]
+ 8020292:	2b00      	cmp	r3, #0
+ 8020294:	d102      	bne.n	802029c <ip4_output_if+0x2c>
+      src_used = netif_ip4_addr(netif);
+ 8020296:	6abb      	ldr	r3, [r7, #40]	; 0x28
+ 8020298:	3304      	adds	r3, #4
+ 802029a:	617b      	str	r3, [r7, #20]
+
+#if IP_OPTIONS_SEND
+  return ip4_output_if_opt_src(p, src_used, dest, ttl, tos, proto, netif,
+                               ip_options, optlen);
+#else /* IP_OPTIONS_SEND */
+  return ip4_output_if_src(p, src_used, dest, ttl, tos, proto, netif);
+ 802029c:	78fa      	ldrb	r2, [r7, #3]
+ 802029e:	6abb      	ldr	r3, [r7, #40]	; 0x28
+ 80202a0:	9302      	str	r3, [sp, #8]
+ 80202a2:	f897 3024 	ldrb.w	r3, [r7, #36]	; 0x24
+ 80202a6:	9301      	str	r3, [sp, #4]
+ 80202a8:	f897 3020 	ldrb.w	r3, [r7, #32]
+ 80202ac:	9300      	str	r3, [sp, #0]
+ 80202ae:	4613      	mov	r3, r2
+ 80202b0:	687a      	ldr	r2, [r7, #4]
+ 80202b2:	6979      	ldr	r1, [r7, #20]
+ 80202b4:	68f8      	ldr	r0, [r7, #12]
+ 80202b6:	f000 f805 	bl	80202c4 <ip4_output_if_src>
+ 80202ba:	4603      	mov	r3, r0
+#endif /* IP_OPTIONS_SEND */
+}
+ 80202bc:	4618      	mov	r0, r3
+ 80202be:	3718      	adds	r7, #24
+ 80202c0:	46bd      	mov	sp, r7
+ 80202c2:	bd80      	pop	{r7, pc}
+
+080202c4 <ip4_output_if_src>:
+ */
+err_t
+ip4_output_if_src(struct pbuf *p, const ip4_addr_t *src, const ip4_addr_t *dest,
+                  u8_t ttl, u8_t tos,
+                  u8_t proto, struct netif *netif)
+{
+ 80202c4:	b580      	push	{r7, lr}
+ 80202c6:	b088      	sub	sp, #32
+ 80202c8:	af00      	add	r7, sp, #0
+ 80202ca:	60f8      	str	r0, [r7, #12]
+ 80202cc:	60b9      	str	r1, [r7, #8]
+ 80202ce:	607a      	str	r2, [r7, #4]
+ 80202d0:	70fb      	strb	r3, [r7, #3]
+#if CHECKSUM_GEN_IP_INLINE
+  u32_t chk_sum = 0;
+#endif /* CHECKSUM_GEN_IP_INLINE */
+
+  LWIP_ASSERT_CORE_LOCKED();
+  LWIP_IP_CHECK_PBUF_REF_COUNT_FOR_TX(p);
+ 80202d2:	68fb      	ldr	r3, [r7, #12]
+ 80202d4:	7b9b      	ldrb	r3, [r3, #14]
+ 80202d6:	2b01      	cmp	r3, #1
+ 80202d8:	d006      	beq.n	80202e8 <ip4_output_if_src+0x24>
+ 80202da:	4b4b      	ldr	r3, [pc, #300]	; (8020408 <ip4_output_if_src+0x144>)
+ 80202dc:	f44f 7255 	mov.w	r2, #852	; 0x354
+ 80202e0:	494a      	ldr	r1, [pc, #296]	; (802040c <ip4_output_if_src+0x148>)
+ 80202e2:	484b      	ldr	r0, [pc, #300]	; (8020410 <ip4_output_if_src+0x14c>)
+ 80202e4:	f001 fb50 	bl	8021988 <iprintf>
+
+  MIB2_STATS_INC(mib2.ipoutrequests);
+
+  /* Should the IP header be generated or is it already included in p? */
+  if (dest != LWIP_IP_HDRINCL) {
+ 80202e8:	687b      	ldr	r3, [r7, #4]
+ 80202ea:	2b00      	cmp	r3, #0
+ 80202ec:	d060      	beq.n	80203b0 <ip4_output_if_src+0xec>
+    u16_t ip_hlen = IP_HLEN;
+ 80202ee:	2314      	movs	r3, #20
+ 80202f0:	837b      	strh	r3, [r7, #26]
+      }
+#endif /* CHECKSUM_GEN_IP_INLINE */
+    }
+#endif /* IP_OPTIONS_SEND */
+    /* generate IP header */
+    if (pbuf_add_header(p, IP_HLEN)) {
+ 80202f2:	2114      	movs	r1, #20
+ 80202f4:	68f8      	ldr	r0, [r7, #12]
+ 80202f6:	f7f7 fb69 	bl	80179cc <pbuf_add_header>
+ 80202fa:	4603      	mov	r3, r0
+ 80202fc:	2b00      	cmp	r3, #0
+ 80202fe:	d002      	beq.n	8020306 <ip4_output_if_src+0x42>
+      LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("ip4_output: not enough room for IP header in pbuf\n"));
+
+      IP_STATS_INC(ip.err);
+      MIB2_STATS_INC(mib2.ipoutdiscards);
+      return ERR_BUF;
+ 8020300:	f06f 0301 	mvn.w	r3, #1
+ 8020304:	e07c      	b.n	8020400 <ip4_output_if_src+0x13c>
+    }
+
+    iphdr = (struct ip_hdr *)p->payload;
+ 8020306:	68fb      	ldr	r3, [r7, #12]
+ 8020308:	685b      	ldr	r3, [r3, #4]
+ 802030a:	61fb      	str	r3, [r7, #28]
+    LWIP_ASSERT("check that first pbuf can hold struct ip_hdr",
+ 802030c:	68fb      	ldr	r3, [r7, #12]
+ 802030e:	895b      	ldrh	r3, [r3, #10]
+ 8020310:	2b13      	cmp	r3, #19
+ 8020312:	d806      	bhi.n	8020322 <ip4_output_if_src+0x5e>
+ 8020314:	4b3c      	ldr	r3, [pc, #240]	; (8020408 <ip4_output_if_src+0x144>)
+ 8020316:	f44f 7262 	mov.w	r2, #904	; 0x388
+ 802031a:	493e      	ldr	r1, [pc, #248]	; (8020414 <ip4_output_if_src+0x150>)
+ 802031c:	483c      	ldr	r0, [pc, #240]	; (8020410 <ip4_output_if_src+0x14c>)
+ 802031e:	f001 fb33 	bl	8021988 <iprintf>
+                (p->len >= sizeof(struct ip_hdr)));
+
+    IPH_TTL_SET(iphdr, ttl);
+ 8020322:	69fb      	ldr	r3, [r7, #28]
+ 8020324:	78fa      	ldrb	r2, [r7, #3]
+ 8020326:	721a      	strb	r2, [r3, #8]
+    IPH_PROTO_SET(iphdr, proto);
+ 8020328:	69fb      	ldr	r3, [r7, #28]
+ 802032a:	f897 202c 	ldrb.w	r2, [r7, #44]	; 0x2c
+ 802032e:	725a      	strb	r2, [r3, #9]
+#if CHECKSUM_GEN_IP_INLINE
+    chk_sum += PP_NTOHS(proto | (ttl << 8));
+#endif /* CHECKSUM_GEN_IP_INLINE */
+
+    /* dest cannot be NULL here */
+    ip4_addr_copy(iphdr->dest, *dest);
+ 8020330:	687b      	ldr	r3, [r7, #4]
+ 8020332:	681a      	ldr	r2, [r3, #0]
+ 8020334:	69fb      	ldr	r3, [r7, #28]
+ 8020336:	611a      	str	r2, [r3, #16]
+#if CHECKSUM_GEN_IP_INLINE
+    chk_sum += ip4_addr_get_u32(&iphdr->dest) & 0xFFFF;
+    chk_sum += ip4_addr_get_u32(&iphdr->dest) >> 16;
+#endif /* CHECKSUM_GEN_IP_INLINE */
+
+    IPH_VHL_SET(iphdr, 4, ip_hlen / 4);
+ 8020338:	8b7b      	ldrh	r3, [r7, #26]
+ 802033a:	089b      	lsrs	r3, r3, #2
+ 802033c:	b29b      	uxth	r3, r3
+ 802033e:	b2db      	uxtb	r3, r3
+ 8020340:	f043 0340 	orr.w	r3, r3, #64	; 0x40
+ 8020344:	b2da      	uxtb	r2, r3
+ 8020346:	69fb      	ldr	r3, [r7, #28]
+ 8020348:	701a      	strb	r2, [r3, #0]
+    IPH_TOS_SET(iphdr, tos);
+ 802034a:	69fb      	ldr	r3, [r7, #28]
+ 802034c:	f897 2028 	ldrb.w	r2, [r7, #40]	; 0x28
+ 8020350:	705a      	strb	r2, [r3, #1]
+#if CHECKSUM_GEN_IP_INLINE
+    chk_sum += PP_NTOHS(tos | (iphdr->_v_hl << 8));
+#endif /* CHECKSUM_GEN_IP_INLINE */
+    IPH_LEN_SET(iphdr, lwip_htons(p->tot_len));
+ 8020352:	68fb      	ldr	r3, [r7, #12]
+ 8020354:	891b      	ldrh	r3, [r3, #8]
+ 8020356:	4618      	mov	r0, r3
+ 8020358:	f7f5 fdf2 	bl	8015f40 <lwip_htons>
+ 802035c:	4603      	mov	r3, r0
+ 802035e:	461a      	mov	r2, r3
+ 8020360:	69fb      	ldr	r3, [r7, #28]
+ 8020362:	805a      	strh	r2, [r3, #2]
+#if CHECKSUM_GEN_IP_INLINE
+    chk_sum += iphdr->_len;
+#endif /* CHECKSUM_GEN_IP_INLINE */
+    IPH_OFFSET_SET(iphdr, 0);
+ 8020364:	69fb      	ldr	r3, [r7, #28]
+ 8020366:	2200      	movs	r2, #0
+ 8020368:	719a      	strb	r2, [r3, #6]
+ 802036a:	2200      	movs	r2, #0
+ 802036c:	71da      	strb	r2, [r3, #7]
+    IPH_ID_SET(iphdr, lwip_htons(ip_id));
+ 802036e:	4b2a      	ldr	r3, [pc, #168]	; (8020418 <ip4_output_if_src+0x154>)
+ 8020370:	881b      	ldrh	r3, [r3, #0]
+ 8020372:	4618      	mov	r0, r3
+ 8020374:	f7f5 fde4 	bl	8015f40 <lwip_htons>
+ 8020378:	4603      	mov	r3, r0
+ 802037a:	461a      	mov	r2, r3
+ 802037c:	69fb      	ldr	r3, [r7, #28]
+ 802037e:	809a      	strh	r2, [r3, #4]
+#if CHECKSUM_GEN_IP_INLINE
+    chk_sum += iphdr->_id;
+#endif /* CHECKSUM_GEN_IP_INLINE */
+    ++ip_id;
+ 8020380:	4b25      	ldr	r3, [pc, #148]	; (8020418 <ip4_output_if_src+0x154>)
+ 8020382:	881b      	ldrh	r3, [r3, #0]
+ 8020384:	3301      	adds	r3, #1
+ 8020386:	b29a      	uxth	r2, r3
+ 8020388:	4b23      	ldr	r3, [pc, #140]	; (8020418 <ip4_output_if_src+0x154>)
+ 802038a:	801a      	strh	r2, [r3, #0]
+
+    if (src == NULL) {
+ 802038c:	68bb      	ldr	r3, [r7, #8]
+ 802038e:	2b00      	cmp	r3, #0
+ 8020390:	d104      	bne.n	802039c <ip4_output_if_src+0xd8>
+      ip4_addr_copy(iphdr->src, *IP4_ADDR_ANY4);
+ 8020392:	4b22      	ldr	r3, [pc, #136]	; (802041c <ip4_output_if_src+0x158>)
+ 8020394:	681a      	ldr	r2, [r3, #0]
+ 8020396:	69fb      	ldr	r3, [r7, #28]
+ 8020398:	60da      	str	r2, [r3, #12]
+ 802039a:	e003      	b.n	80203a4 <ip4_output_if_src+0xe0>
+    } else {
+      /* src cannot be NULL here */
+      ip4_addr_copy(iphdr->src, *src);
+ 802039c:	68bb      	ldr	r3, [r7, #8]
+ 802039e:	681a      	ldr	r2, [r3, #0]
+ 80203a0:	69fb      	ldr	r3, [r7, #28]
+ 80203a2:	60da      	str	r2, [r3, #12]
+    else {
+      IPH_CHKSUM_SET(iphdr, 0);
+    }
+#endif /* LWIP_CHECKSUM_CTRL_PER_NETIF*/
+#else /* CHECKSUM_GEN_IP_INLINE */
+    IPH_CHKSUM_SET(iphdr, 0);
+ 80203a4:	69fb      	ldr	r3, [r7, #28]
+ 80203a6:	2200      	movs	r2, #0
+ 80203a8:	729a      	strb	r2, [r3, #10]
+ 80203aa:	2200      	movs	r2, #0
+ 80203ac:	72da      	strb	r2, [r3, #11]
+ 80203ae:	e00f      	b.n	80203d0 <ip4_output_if_src+0x10c>
+    }
+#endif /* CHECKSUM_GEN_IP */
+#endif /* CHECKSUM_GEN_IP_INLINE */
+  } else {
+    /* IP header already included in p */
+    if (p->len < IP_HLEN) {
+ 80203b0:	68fb      	ldr	r3, [r7, #12]
+ 80203b2:	895b      	ldrh	r3, [r3, #10]
+ 80203b4:	2b13      	cmp	r3, #19
+ 80203b6:	d802      	bhi.n	80203be <ip4_output_if_src+0xfa>
+      LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("ip4_output: LWIP_IP_HDRINCL but pbuf is too short\n"));
+      IP_STATS_INC(ip.err);
+      MIB2_STATS_INC(mib2.ipoutdiscards);
+      return ERR_BUF;
+ 80203b8:	f06f 0301 	mvn.w	r3, #1
+ 80203bc:	e020      	b.n	8020400 <ip4_output_if_src+0x13c>
+    }
+    iphdr = (struct ip_hdr *)p->payload;
+ 80203be:	68fb      	ldr	r3, [r7, #12]
+ 80203c0:	685b      	ldr	r3, [r3, #4]
+ 80203c2:	61fb      	str	r3, [r7, #28]
+    ip4_addr_copy(dest_addr, iphdr->dest);
+ 80203c4:	69fb      	ldr	r3, [r7, #28]
+ 80203c6:	691b      	ldr	r3, [r3, #16]
+ 80203c8:	617b      	str	r3, [r7, #20]
+    dest = &dest_addr;
+ 80203ca:	f107 0314 	add.w	r3, r7, #20
+ 80203ce:	607b      	str	r3, [r7, #4]
+  }
+#endif /* LWIP_MULTICAST_TX_OPTIONS */
+#endif /* ENABLE_LOOPBACK */
+#if IP_FRAG
+  /* don't fragment if interface has mtu set to 0 [loopif] */
+  if (netif->mtu && (p->tot_len > netif->mtu)) {
+ 80203d0:	6b3b      	ldr	r3, [r7, #48]	; 0x30
+ 80203d2:	8c9b      	ldrh	r3, [r3, #36]	; 0x24
+ 80203d4:	2b00      	cmp	r3, #0
+ 80203d6:	d00c      	beq.n	80203f2 <ip4_output_if_src+0x12e>
+ 80203d8:	68fb      	ldr	r3, [r7, #12]
+ 80203da:	891a      	ldrh	r2, [r3, #8]
+ 80203dc:	6b3b      	ldr	r3, [r7, #48]	; 0x30
+ 80203de:	8c9b      	ldrh	r3, [r3, #36]	; 0x24
+ 80203e0:	429a      	cmp	r2, r3
+ 80203e2:	d906      	bls.n	80203f2 <ip4_output_if_src+0x12e>
+    return ip4_frag(p, netif, dest);
+ 80203e4:	687a      	ldr	r2, [r7, #4]
+ 80203e6:	6b39      	ldr	r1, [r7, #48]	; 0x30
+ 80203e8:	68f8      	ldr	r0, [r7, #12]
+ 80203ea:	f000 fd53 	bl	8020e94 <ip4_frag>
+ 80203ee:	4603      	mov	r3, r0
+ 80203f0:	e006      	b.n	8020400 <ip4_output_if_src+0x13c>
+  }
+#endif /* IP_FRAG */
+
+  LWIP_DEBUGF(IP_DEBUG, ("ip4_output_if: call netif->output()\n"));
+  return netif->output(netif, p, dest);
+ 80203f2:	6b3b      	ldr	r3, [r7, #48]	; 0x30
+ 80203f4:	695b      	ldr	r3, [r3, #20]
+ 80203f6:	687a      	ldr	r2, [r7, #4]
+ 80203f8:	68f9      	ldr	r1, [r7, #12]
+ 80203fa:	6b38      	ldr	r0, [r7, #48]	; 0x30
+ 80203fc:	4798      	blx	r3
+ 80203fe:	4603      	mov	r3, r0
+}
+ 8020400:	4618      	mov	r0, r3
+ 8020402:	3720      	adds	r7, #32
+ 8020404:	46bd      	mov	sp, r7
+ 8020406:	bd80      	pop	{r7, pc}
+ 8020408:	080267ec 	.word	0x080267ec
+ 802040c:	08026820 	.word	0x08026820
+ 8020410:	0802682c 	.word	0x0802682c
+ 8020414:	08026854 	.word	0x08026854
+ 8020418:	2401a5d6 	.word	0x2401a5d6
+ 802041c:	08026cec 	.word	0x08026cec
+
+08020420 <ip4_addr_isbroadcast_u32>:
+ * @param netif the network interface against which the address is checked
+ * @return returns non-zero if the address is a broadcast address
+ */
+u8_t
+ip4_addr_isbroadcast_u32(u32_t addr, const struct netif *netif)
+{
+ 8020420:	b480      	push	{r7}
+ 8020422:	b085      	sub	sp, #20
+ 8020424:	af00      	add	r7, sp, #0
+ 8020426:	6078      	str	r0, [r7, #4]
+ 8020428:	6039      	str	r1, [r7, #0]
+  ip4_addr_t ipaddr;
+  ip4_addr_set_u32(&ipaddr, addr);
+ 802042a:	687b      	ldr	r3, [r7, #4]
+ 802042c:	60fb      	str	r3, [r7, #12]
+
+  /* all ones (broadcast) or all zeroes (old skool broadcast) */
+  if ((~addr == IPADDR_ANY) ||
+ 802042e:	687b      	ldr	r3, [r7, #4]
+ 8020430:	f1b3 3fff 	cmp.w	r3, #4294967295
+ 8020434:	d002      	beq.n	802043c <ip4_addr_isbroadcast_u32+0x1c>
+ 8020436:	687b      	ldr	r3, [r7, #4]
+ 8020438:	2b00      	cmp	r3, #0
+ 802043a:	d101      	bne.n	8020440 <ip4_addr_isbroadcast_u32+0x20>
+      (addr == IPADDR_ANY)) {
+    return 1;
+ 802043c:	2301      	movs	r3, #1
+ 802043e:	e02a      	b.n	8020496 <ip4_addr_isbroadcast_u32+0x76>
+    /* no broadcast support on this network interface? */
+  } else if ((netif->flags & NETIF_FLAG_BROADCAST) == 0) {
+ 8020440:	683b      	ldr	r3, [r7, #0]
+ 8020442:	f893 302d 	ldrb.w	r3, [r3, #45]	; 0x2d
+ 8020446:	f003 0302 	and.w	r3, r3, #2
+ 802044a:	2b00      	cmp	r3, #0
+ 802044c:	d101      	bne.n	8020452 <ip4_addr_isbroadcast_u32+0x32>
+    /* the given address cannot be a broadcast address
+     * nor can we check against any broadcast addresses */
+    return 0;
+ 802044e:	2300      	movs	r3, #0
+ 8020450:	e021      	b.n	8020496 <ip4_addr_isbroadcast_u32+0x76>
+    /* address matches network interface address exactly? => no broadcast */
+  } else if (addr == ip4_addr_get_u32(netif_ip4_addr(netif))) {
+ 8020452:	683b      	ldr	r3, [r7, #0]
+ 8020454:	3304      	adds	r3, #4
+ 8020456:	681b      	ldr	r3, [r3, #0]
+ 8020458:	687a      	ldr	r2, [r7, #4]
+ 802045a:	429a      	cmp	r2, r3
+ 802045c:	d101      	bne.n	8020462 <ip4_addr_isbroadcast_u32+0x42>
+    return 0;
+ 802045e:	2300      	movs	r3, #0
+ 8020460:	e019      	b.n	8020496 <ip4_addr_isbroadcast_u32+0x76>
+    /*  on the same (sub) network... */
+  } else if (ip4_addr_netcmp(&ipaddr, netif_ip4_addr(netif), netif_ip4_netmask(netif))
+ 8020462:	68fa      	ldr	r2, [r7, #12]
+ 8020464:	683b      	ldr	r3, [r7, #0]
+ 8020466:	3304      	adds	r3, #4
+ 8020468:	681b      	ldr	r3, [r3, #0]
+ 802046a:	405a      	eors	r2, r3
+ 802046c:	683b      	ldr	r3, [r7, #0]
+ 802046e:	3308      	adds	r3, #8
+ 8020470:	681b      	ldr	r3, [r3, #0]
+ 8020472:	4013      	ands	r3, r2
+ 8020474:	2b00      	cmp	r3, #0
+ 8020476:	d10d      	bne.n	8020494 <ip4_addr_isbroadcast_u32+0x74>
+             /* ...and host identifier bits are all ones? =>... */
+             && ((addr & ~ip4_addr_get_u32(netif_ip4_netmask(netif))) ==
+ 8020478:	683b      	ldr	r3, [r7, #0]
+ 802047a:	3308      	adds	r3, #8
+ 802047c:	681b      	ldr	r3, [r3, #0]
+ 802047e:	43da      	mvns	r2, r3
+ 8020480:	687b      	ldr	r3, [r7, #4]
+ 8020482:	401a      	ands	r2, r3
+                 (IPADDR_BROADCAST & ~ip4_addr_get_u32(netif_ip4_netmask(netif))))) {
+ 8020484:	683b      	ldr	r3, [r7, #0]
+ 8020486:	3308      	adds	r3, #8
+ 8020488:	681b      	ldr	r3, [r3, #0]
+ 802048a:	43db      	mvns	r3, r3
+             && ((addr & ~ip4_addr_get_u32(netif_ip4_netmask(netif))) ==
+ 802048c:	429a      	cmp	r2, r3
+ 802048e:	d101      	bne.n	8020494 <ip4_addr_isbroadcast_u32+0x74>
+    /* => network broadcast address */
+    return 1;
+ 8020490:	2301      	movs	r3, #1
+ 8020492:	e000      	b.n	8020496 <ip4_addr_isbroadcast_u32+0x76>
+  } else {
+    return 0;
+ 8020494:	2300      	movs	r3, #0
+  }
+}
+ 8020496:	4618      	mov	r0, r3
+ 8020498:	3714      	adds	r7, #20
+ 802049a:	46bd      	mov	sp, r7
+ 802049c:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 80204a0:	4770      	bx	lr
+	...
+
+080204a4 <ip_reass_tmr>:
+ *
+ * Should be called every 1000 msec (defined by IP_TMR_INTERVAL).
+ */
+void
+ip_reass_tmr(void)
+{
+ 80204a4:	b580      	push	{r7, lr}
+ 80204a6:	b084      	sub	sp, #16
+ 80204a8:	af00      	add	r7, sp, #0
+  struct ip_reassdata *r, *prev = NULL;
+ 80204aa:	2300      	movs	r3, #0
+ 80204ac:	60bb      	str	r3, [r7, #8]
+
+  r = reassdatagrams;
+ 80204ae:	4b12      	ldr	r3, [pc, #72]	; (80204f8 <ip_reass_tmr+0x54>)
+ 80204b0:	681b      	ldr	r3, [r3, #0]
+ 80204b2:	60fb      	str	r3, [r7, #12]
+  while (r != NULL) {
+ 80204b4:	e018      	b.n	80204e8 <ip_reass_tmr+0x44>
+    /* Decrement the timer. Once it reaches 0,
+     * clean up the incomplete fragment assembly */
+    if (r->timer > 0) {
+ 80204b6:	68fb      	ldr	r3, [r7, #12]
+ 80204b8:	7fdb      	ldrb	r3, [r3, #31]
+ 80204ba:	2b00      	cmp	r3, #0
+ 80204bc:	d00b      	beq.n	80204d6 <ip_reass_tmr+0x32>
+      r->timer--;
+ 80204be:	68fb      	ldr	r3, [r7, #12]
+ 80204c0:	7fdb      	ldrb	r3, [r3, #31]
+ 80204c2:	3b01      	subs	r3, #1
+ 80204c4:	b2da      	uxtb	r2, r3
+ 80204c6:	68fb      	ldr	r3, [r7, #12]
+ 80204c8:	77da      	strb	r2, [r3, #31]
+      LWIP_DEBUGF(IP_REASS_DEBUG, ("ip_reass_tmr: timer dec %"U16_F"\n", (u16_t)r->timer));
+      prev = r;
+ 80204ca:	68fb      	ldr	r3, [r7, #12]
+ 80204cc:	60bb      	str	r3, [r7, #8]
+      r = r->next;
+ 80204ce:	68fb      	ldr	r3, [r7, #12]
+ 80204d0:	681b      	ldr	r3, [r3, #0]
+ 80204d2:	60fb      	str	r3, [r7, #12]
+ 80204d4:	e008      	b.n	80204e8 <ip_reass_tmr+0x44>
+    } else {
+      /* reassembly timed out */
+      struct ip_reassdata *tmp;
+      LWIP_DEBUGF(IP_REASS_DEBUG, ("ip_reass_tmr: timer timed out\n"));
+      tmp = r;
+ 80204d6:	68fb      	ldr	r3, [r7, #12]
+ 80204d8:	607b      	str	r3, [r7, #4]
+      /* get the next pointer before freeing */
+      r = r->next;
+ 80204da:	68fb      	ldr	r3, [r7, #12]
+ 80204dc:	681b      	ldr	r3, [r3, #0]
+ 80204de:	60fb      	str	r3, [r7, #12]
+      /* free the helper struct and all enqueued pbufs */
+      ip_reass_free_complete_datagram(tmp, prev);
+ 80204e0:	68b9      	ldr	r1, [r7, #8]
+ 80204e2:	6878      	ldr	r0, [r7, #4]
+ 80204e4:	f000 f80a 	bl	80204fc <ip_reass_free_complete_datagram>
+  while (r != NULL) {
+ 80204e8:	68fb      	ldr	r3, [r7, #12]
+ 80204ea:	2b00      	cmp	r3, #0
+ 80204ec:	d1e3      	bne.n	80204b6 <ip_reass_tmr+0x12>
+    }
+  }
+}
+ 80204ee:	bf00      	nop
+ 80204f0:	bf00      	nop
+ 80204f2:	3710      	adds	r7, #16
+ 80204f4:	46bd      	mov	sp, r7
+ 80204f6:	bd80      	pop	{r7, pc}
+ 80204f8:	2401a5d8 	.word	0x2401a5d8
+
+080204fc <ip_reass_free_complete_datagram>:
+ * @param prev the previous datagram in the linked list
+ * @return the number of pbufs freed
+ */
+static int
+ip_reass_free_complete_datagram(struct ip_reassdata *ipr, struct ip_reassdata *prev)
+{
+ 80204fc:	b580      	push	{r7, lr}
+ 80204fe:	b088      	sub	sp, #32
+ 8020500:	af00      	add	r7, sp, #0
+ 8020502:	6078      	str	r0, [r7, #4]
+ 8020504:	6039      	str	r1, [r7, #0]
+  u16_t pbufs_freed = 0;
+ 8020506:	2300      	movs	r3, #0
+ 8020508:	83fb      	strh	r3, [r7, #30]
+  u16_t clen;
+  struct pbuf *p;
+  struct ip_reass_helper *iprh;
+
+  LWIP_ASSERT("prev != ipr", prev != ipr);
+ 802050a:	683a      	ldr	r2, [r7, #0]
+ 802050c:	687b      	ldr	r3, [r7, #4]
+ 802050e:	429a      	cmp	r2, r3
+ 8020510:	d105      	bne.n	802051e <ip_reass_free_complete_datagram+0x22>
+ 8020512:	4b45      	ldr	r3, [pc, #276]	; (8020628 <ip_reass_free_complete_datagram+0x12c>)
+ 8020514:	22ab      	movs	r2, #171	; 0xab
+ 8020516:	4945      	ldr	r1, [pc, #276]	; (802062c <ip_reass_free_complete_datagram+0x130>)
+ 8020518:	4845      	ldr	r0, [pc, #276]	; (8020630 <ip_reass_free_complete_datagram+0x134>)
+ 802051a:	f001 fa35 	bl	8021988 <iprintf>
+  if (prev != NULL) {
+ 802051e:	683b      	ldr	r3, [r7, #0]
+ 8020520:	2b00      	cmp	r3, #0
+ 8020522:	d00a      	beq.n	802053a <ip_reass_free_complete_datagram+0x3e>
+    LWIP_ASSERT("prev->next == ipr", prev->next == ipr);
+ 8020524:	683b      	ldr	r3, [r7, #0]
+ 8020526:	681b      	ldr	r3, [r3, #0]
+ 8020528:	687a      	ldr	r2, [r7, #4]
+ 802052a:	429a      	cmp	r2, r3
+ 802052c:	d005      	beq.n	802053a <ip_reass_free_complete_datagram+0x3e>
+ 802052e:	4b3e      	ldr	r3, [pc, #248]	; (8020628 <ip_reass_free_complete_datagram+0x12c>)
+ 8020530:	22ad      	movs	r2, #173	; 0xad
+ 8020532:	4940      	ldr	r1, [pc, #256]	; (8020634 <ip_reass_free_complete_datagram+0x138>)
+ 8020534:	483e      	ldr	r0, [pc, #248]	; (8020630 <ip_reass_free_complete_datagram+0x134>)
+ 8020536:	f001 fa27 	bl	8021988 <iprintf>
+  }
+
+  MIB2_STATS_INC(mib2.ipreasmfails);
+#if LWIP_ICMP
+  iprh = (struct ip_reass_helper *)ipr->p->payload;
+ 802053a:	687b      	ldr	r3, [r7, #4]
+ 802053c:	685b      	ldr	r3, [r3, #4]
+ 802053e:	685b      	ldr	r3, [r3, #4]
+ 8020540:	617b      	str	r3, [r7, #20]
+  if (iprh->start == 0) {
+ 8020542:	697b      	ldr	r3, [r7, #20]
+ 8020544:	889b      	ldrh	r3, [r3, #4]
+ 8020546:	b29b      	uxth	r3, r3
+ 8020548:	2b00      	cmp	r3, #0
+ 802054a:	d12a      	bne.n	80205a2 <ip_reass_free_complete_datagram+0xa6>
+    /* The first fragment was received, send ICMP time exceeded. */
+    /* First, de-queue the first pbuf from r->p. */
+    p = ipr->p;
+ 802054c:	687b      	ldr	r3, [r7, #4]
+ 802054e:	685b      	ldr	r3, [r3, #4]
+ 8020550:	61bb      	str	r3, [r7, #24]
+    ipr->p = iprh->next_pbuf;
+ 8020552:	697b      	ldr	r3, [r7, #20]
+ 8020554:	681a      	ldr	r2, [r3, #0]
+ 8020556:	687b      	ldr	r3, [r7, #4]
+ 8020558:	605a      	str	r2, [r3, #4]
+    /* Then, copy the original header into it. */
+    SMEMCPY(p->payload, &ipr->iphdr, IP_HLEN);
+ 802055a:	69bb      	ldr	r3, [r7, #24]
+ 802055c:	6858      	ldr	r0, [r3, #4]
+ 802055e:	687b      	ldr	r3, [r7, #4]
+ 8020560:	3308      	adds	r3, #8
+ 8020562:	2214      	movs	r2, #20
+ 8020564:	4619      	mov	r1, r3
+ 8020566:	f001 fc3e 	bl	8021de6 <memcpy>
+    icmp_time_exceeded(p, ICMP_TE_FRAG);
+ 802056a:	2101      	movs	r1, #1
+ 802056c:	69b8      	ldr	r0, [r7, #24]
+ 802056e:	f7ff fc3d 	bl	801fdec <icmp_time_exceeded>
+    clen = pbuf_clen(p);
+ 8020572:	69b8      	ldr	r0, [r7, #24]
+ 8020574:	f7f7 fb4e 	bl	8017c14 <pbuf_clen>
+ 8020578:	4603      	mov	r3, r0
+ 802057a:	827b      	strh	r3, [r7, #18]
+    LWIP_ASSERT("pbufs_freed + clen <= 0xffff", pbufs_freed + clen <= 0xffff);
+ 802057c:	8bfa      	ldrh	r2, [r7, #30]
+ 802057e:	8a7b      	ldrh	r3, [r7, #18]
+ 8020580:	4413      	add	r3, r2
+ 8020582:	f5b3 3f80 	cmp.w	r3, #65536	; 0x10000
+ 8020586:	db05      	blt.n	8020594 <ip_reass_free_complete_datagram+0x98>
+ 8020588:	4b27      	ldr	r3, [pc, #156]	; (8020628 <ip_reass_free_complete_datagram+0x12c>)
+ 802058a:	22bc      	movs	r2, #188	; 0xbc
+ 802058c:	492a      	ldr	r1, [pc, #168]	; (8020638 <ip_reass_free_complete_datagram+0x13c>)
+ 802058e:	4828      	ldr	r0, [pc, #160]	; (8020630 <ip_reass_free_complete_datagram+0x134>)
+ 8020590:	f001 f9fa 	bl	8021988 <iprintf>
+    pbufs_freed = (u16_t)(pbufs_freed + clen);
+ 8020594:	8bfa      	ldrh	r2, [r7, #30]
+ 8020596:	8a7b      	ldrh	r3, [r7, #18]
+ 8020598:	4413      	add	r3, r2
+ 802059a:	83fb      	strh	r3, [r7, #30]
+    pbuf_free(p);
+ 802059c:	69b8      	ldr	r0, [r7, #24]
+ 802059e:	f7f7 faab 	bl	8017af8 <pbuf_free>
+  }
+#endif /* LWIP_ICMP */
+
+  /* First, free all received pbufs.  The individual pbufs need to be released
+     separately as they have not yet been chained */
+  p = ipr->p;
+ 80205a2:	687b      	ldr	r3, [r7, #4]
+ 80205a4:	685b      	ldr	r3, [r3, #4]
+ 80205a6:	61bb      	str	r3, [r7, #24]
+  while (p != NULL) {
+ 80205a8:	e01f      	b.n	80205ea <ip_reass_free_complete_datagram+0xee>
+    struct pbuf *pcur;
+    iprh = (struct ip_reass_helper *)p->payload;
+ 80205aa:	69bb      	ldr	r3, [r7, #24]
+ 80205ac:	685b      	ldr	r3, [r3, #4]
+ 80205ae:	617b      	str	r3, [r7, #20]
+    pcur = p;
+ 80205b0:	69bb      	ldr	r3, [r7, #24]
+ 80205b2:	60fb      	str	r3, [r7, #12]
+    /* get the next pointer before freeing */
+    p = iprh->next_pbuf;
+ 80205b4:	697b      	ldr	r3, [r7, #20]
+ 80205b6:	681b      	ldr	r3, [r3, #0]
+ 80205b8:	61bb      	str	r3, [r7, #24]
+    clen = pbuf_clen(pcur);
+ 80205ba:	68f8      	ldr	r0, [r7, #12]
+ 80205bc:	f7f7 fb2a 	bl	8017c14 <pbuf_clen>
+ 80205c0:	4603      	mov	r3, r0
+ 80205c2:	827b      	strh	r3, [r7, #18]
+    LWIP_ASSERT("pbufs_freed + clen <= 0xffff", pbufs_freed + clen <= 0xffff);
+ 80205c4:	8bfa      	ldrh	r2, [r7, #30]
+ 80205c6:	8a7b      	ldrh	r3, [r7, #18]
+ 80205c8:	4413      	add	r3, r2
+ 80205ca:	f5b3 3f80 	cmp.w	r3, #65536	; 0x10000
+ 80205ce:	db05      	blt.n	80205dc <ip_reass_free_complete_datagram+0xe0>
+ 80205d0:	4b15      	ldr	r3, [pc, #84]	; (8020628 <ip_reass_free_complete_datagram+0x12c>)
+ 80205d2:	22cc      	movs	r2, #204	; 0xcc
+ 80205d4:	4918      	ldr	r1, [pc, #96]	; (8020638 <ip_reass_free_complete_datagram+0x13c>)
+ 80205d6:	4816      	ldr	r0, [pc, #88]	; (8020630 <ip_reass_free_complete_datagram+0x134>)
+ 80205d8:	f001 f9d6 	bl	8021988 <iprintf>
+    pbufs_freed = (u16_t)(pbufs_freed + clen);
+ 80205dc:	8bfa      	ldrh	r2, [r7, #30]
+ 80205de:	8a7b      	ldrh	r3, [r7, #18]
+ 80205e0:	4413      	add	r3, r2
+ 80205e2:	83fb      	strh	r3, [r7, #30]
+    pbuf_free(pcur);
+ 80205e4:	68f8      	ldr	r0, [r7, #12]
+ 80205e6:	f7f7 fa87 	bl	8017af8 <pbuf_free>
+  while (p != NULL) {
+ 80205ea:	69bb      	ldr	r3, [r7, #24]
+ 80205ec:	2b00      	cmp	r3, #0
+ 80205ee:	d1dc      	bne.n	80205aa <ip_reass_free_complete_datagram+0xae>
+  }
+  /* Then, unchain the struct ip_reassdata from the list and free it. */
+  ip_reass_dequeue_datagram(ipr, prev);
+ 80205f0:	6839      	ldr	r1, [r7, #0]
+ 80205f2:	6878      	ldr	r0, [r7, #4]
+ 80205f4:	f000 f8c2 	bl	802077c <ip_reass_dequeue_datagram>
+  LWIP_ASSERT("ip_reass_pbufcount >= pbufs_freed", ip_reass_pbufcount >= pbufs_freed);
+ 80205f8:	4b10      	ldr	r3, [pc, #64]	; (802063c <ip_reass_free_complete_datagram+0x140>)
+ 80205fa:	881b      	ldrh	r3, [r3, #0]
+ 80205fc:	8bfa      	ldrh	r2, [r7, #30]
+ 80205fe:	429a      	cmp	r2, r3
+ 8020600:	d905      	bls.n	802060e <ip_reass_free_complete_datagram+0x112>
+ 8020602:	4b09      	ldr	r3, [pc, #36]	; (8020628 <ip_reass_free_complete_datagram+0x12c>)
+ 8020604:	22d2      	movs	r2, #210	; 0xd2
+ 8020606:	490e      	ldr	r1, [pc, #56]	; (8020640 <ip_reass_free_complete_datagram+0x144>)
+ 8020608:	4809      	ldr	r0, [pc, #36]	; (8020630 <ip_reass_free_complete_datagram+0x134>)
+ 802060a:	f001 f9bd 	bl	8021988 <iprintf>
+  ip_reass_pbufcount = (u16_t)(ip_reass_pbufcount - pbufs_freed);
+ 802060e:	4b0b      	ldr	r3, [pc, #44]	; (802063c <ip_reass_free_complete_datagram+0x140>)
+ 8020610:	881a      	ldrh	r2, [r3, #0]
+ 8020612:	8bfb      	ldrh	r3, [r7, #30]
+ 8020614:	1ad3      	subs	r3, r2, r3
+ 8020616:	b29a      	uxth	r2, r3
+ 8020618:	4b08      	ldr	r3, [pc, #32]	; (802063c <ip_reass_free_complete_datagram+0x140>)
+ 802061a:	801a      	strh	r2, [r3, #0]
+
+  return pbufs_freed;
+ 802061c:	8bfb      	ldrh	r3, [r7, #30]
+}
+ 802061e:	4618      	mov	r0, r3
+ 8020620:	3720      	adds	r7, #32
+ 8020622:	46bd      	mov	sp, r7
+ 8020624:	bd80      	pop	{r7, pc}
+ 8020626:	bf00      	nop
+ 8020628:	08026884 	.word	0x08026884
+ 802062c:	080268c0 	.word	0x080268c0
+ 8020630:	080268cc 	.word	0x080268cc
+ 8020634:	080268f4 	.word	0x080268f4
+ 8020638:	08026908 	.word	0x08026908
+ 802063c:	2401a5dc 	.word	0x2401a5dc
+ 8020640:	08026928 	.word	0x08026928
+
+08020644 <ip_reass_remove_oldest_datagram>:
+ *        (used for freeing other datagrams if not enough space)
+ * @return the number of pbufs freed
+ */
+static int
+ip_reass_remove_oldest_datagram(struct ip_hdr *fraghdr, int pbufs_needed)
+{
+ 8020644:	b580      	push	{r7, lr}
+ 8020646:	b08a      	sub	sp, #40	; 0x28
+ 8020648:	af00      	add	r7, sp, #0
+ 802064a:	6078      	str	r0, [r7, #4]
+ 802064c:	6039      	str	r1, [r7, #0]
+  /* @todo Can't we simply remove the last datagram in the
+   *       linked list behind reassdatagrams?
+   */
+  struct ip_reassdata *r, *oldest, *prev, *oldest_prev;
+  int pbufs_freed = 0, pbufs_freed_current;
+ 802064e:	2300      	movs	r3, #0
+ 8020650:	617b      	str	r3, [r7, #20]
+  int other_datagrams;
+
+  /* Free datagrams until being allowed to enqueue 'pbufs_needed' pbufs,
+   * but don't free the datagram that 'fraghdr' belongs to! */
+  do {
+    oldest = NULL;
+ 8020652:	2300      	movs	r3, #0
+ 8020654:	623b      	str	r3, [r7, #32]
+    prev = NULL;
+ 8020656:	2300      	movs	r3, #0
+ 8020658:	61fb      	str	r3, [r7, #28]
+    oldest_prev = NULL;
+ 802065a:	2300      	movs	r3, #0
+ 802065c:	61bb      	str	r3, [r7, #24]
+    other_datagrams = 0;
+ 802065e:	2300      	movs	r3, #0
+ 8020660:	613b      	str	r3, [r7, #16]
+    r = reassdatagrams;
+ 8020662:	4b28      	ldr	r3, [pc, #160]	; (8020704 <ip_reass_remove_oldest_datagram+0xc0>)
+ 8020664:	681b      	ldr	r3, [r3, #0]
+ 8020666:	627b      	str	r3, [r7, #36]	; 0x24
+    while (r != NULL) {
+ 8020668:	e030      	b.n	80206cc <ip_reass_remove_oldest_datagram+0x88>
+      if (!IP_ADDRESSES_AND_ID_MATCH(&r->iphdr, fraghdr)) {
+ 802066a:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 802066c:	695a      	ldr	r2, [r3, #20]
+ 802066e:	687b      	ldr	r3, [r7, #4]
+ 8020670:	68db      	ldr	r3, [r3, #12]
+ 8020672:	429a      	cmp	r2, r3
+ 8020674:	d10c      	bne.n	8020690 <ip_reass_remove_oldest_datagram+0x4c>
+ 8020676:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 8020678:	699a      	ldr	r2, [r3, #24]
+ 802067a:	687b      	ldr	r3, [r7, #4]
+ 802067c:	691b      	ldr	r3, [r3, #16]
+ 802067e:	429a      	cmp	r2, r3
+ 8020680:	d106      	bne.n	8020690 <ip_reass_remove_oldest_datagram+0x4c>
+ 8020682:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 8020684:	899a      	ldrh	r2, [r3, #12]
+ 8020686:	687b      	ldr	r3, [r7, #4]
+ 8020688:	889b      	ldrh	r3, [r3, #4]
+ 802068a:	b29b      	uxth	r3, r3
+ 802068c:	429a      	cmp	r2, r3
+ 802068e:	d014      	beq.n	80206ba <ip_reass_remove_oldest_datagram+0x76>
+        /* Not the same datagram as fraghdr */
+        other_datagrams++;
+ 8020690:	693b      	ldr	r3, [r7, #16]
+ 8020692:	3301      	adds	r3, #1
+ 8020694:	613b      	str	r3, [r7, #16]
+        if (oldest == NULL) {
+ 8020696:	6a3b      	ldr	r3, [r7, #32]
+ 8020698:	2b00      	cmp	r3, #0
+ 802069a:	d104      	bne.n	80206a6 <ip_reass_remove_oldest_datagram+0x62>
+          oldest = r;
+ 802069c:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 802069e:	623b      	str	r3, [r7, #32]
+          oldest_prev = prev;
+ 80206a0:	69fb      	ldr	r3, [r7, #28]
+ 80206a2:	61bb      	str	r3, [r7, #24]
+ 80206a4:	e009      	b.n	80206ba <ip_reass_remove_oldest_datagram+0x76>
+        } else if (r->timer <= oldest->timer) {
+ 80206a6:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 80206a8:	7fda      	ldrb	r2, [r3, #31]
+ 80206aa:	6a3b      	ldr	r3, [r7, #32]
+ 80206ac:	7fdb      	ldrb	r3, [r3, #31]
+ 80206ae:	429a      	cmp	r2, r3
+ 80206b0:	d803      	bhi.n	80206ba <ip_reass_remove_oldest_datagram+0x76>
+          /* older than the previous oldest */
+          oldest = r;
+ 80206b2:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 80206b4:	623b      	str	r3, [r7, #32]
+          oldest_prev = prev;
+ 80206b6:	69fb      	ldr	r3, [r7, #28]
+ 80206b8:	61bb      	str	r3, [r7, #24]
+        }
+      }
+      if (r->next != NULL) {
+ 80206ba:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 80206bc:	681b      	ldr	r3, [r3, #0]
+ 80206be:	2b00      	cmp	r3, #0
+ 80206c0:	d001      	beq.n	80206c6 <ip_reass_remove_oldest_datagram+0x82>
+        prev = r;
+ 80206c2:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 80206c4:	61fb      	str	r3, [r7, #28]
+      }
+      r = r->next;
+ 80206c6:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 80206c8:	681b      	ldr	r3, [r3, #0]
+ 80206ca:	627b      	str	r3, [r7, #36]	; 0x24
+    while (r != NULL) {
+ 80206cc:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 80206ce:	2b00      	cmp	r3, #0
+ 80206d0:	d1cb      	bne.n	802066a <ip_reass_remove_oldest_datagram+0x26>
+    }
+    if (oldest != NULL) {
+ 80206d2:	6a3b      	ldr	r3, [r7, #32]
+ 80206d4:	2b00      	cmp	r3, #0
+ 80206d6:	d008      	beq.n	80206ea <ip_reass_remove_oldest_datagram+0xa6>
+      pbufs_freed_current = ip_reass_free_complete_datagram(oldest, oldest_prev);
+ 80206d8:	69b9      	ldr	r1, [r7, #24]
+ 80206da:	6a38      	ldr	r0, [r7, #32]
+ 80206dc:	f7ff ff0e 	bl	80204fc <ip_reass_free_complete_datagram>
+ 80206e0:	60f8      	str	r0, [r7, #12]
+      pbufs_freed += pbufs_freed_current;
+ 80206e2:	697a      	ldr	r2, [r7, #20]
+ 80206e4:	68fb      	ldr	r3, [r7, #12]
+ 80206e6:	4413      	add	r3, r2
+ 80206e8:	617b      	str	r3, [r7, #20]
+    }
+  } while ((pbufs_freed < pbufs_needed) && (other_datagrams > 1));
+ 80206ea:	697a      	ldr	r2, [r7, #20]
+ 80206ec:	683b      	ldr	r3, [r7, #0]
+ 80206ee:	429a      	cmp	r2, r3
+ 80206f0:	da02      	bge.n	80206f8 <ip_reass_remove_oldest_datagram+0xb4>
+ 80206f2:	693b      	ldr	r3, [r7, #16]
+ 80206f4:	2b01      	cmp	r3, #1
+ 80206f6:	dcac      	bgt.n	8020652 <ip_reass_remove_oldest_datagram+0xe>
+  return pbufs_freed;
+ 80206f8:	697b      	ldr	r3, [r7, #20]
+}
+ 80206fa:	4618      	mov	r0, r3
+ 80206fc:	3728      	adds	r7, #40	; 0x28
+ 80206fe:	46bd      	mov	sp, r7
+ 8020700:	bd80      	pop	{r7, pc}
+ 8020702:	bf00      	nop
+ 8020704:	2401a5d8 	.word	0x2401a5d8
+
+08020708 <ip_reass_enqueue_new_datagram>:
+ * @param clen number of pbufs needed to enqueue (used for freeing other datagrams if not enough space)
+ * @return A pointer to the queue location into which the fragment was enqueued
+ */
+static struct ip_reassdata *
+ip_reass_enqueue_new_datagram(struct ip_hdr *fraghdr, int clen)
+{
+ 8020708:	b580      	push	{r7, lr}
+ 802070a:	b084      	sub	sp, #16
+ 802070c:	af00      	add	r7, sp, #0
+ 802070e:	6078      	str	r0, [r7, #4]
+ 8020710:	6039      	str	r1, [r7, #0]
+#if ! IP_REASS_FREE_OLDEST
+  LWIP_UNUSED_ARG(clen);
+#endif
+
+  /* No matching previous fragment found, allocate a new reassdata struct */
+  ipr = (struct ip_reassdata *)memp_malloc(MEMP_REASSDATA);
+ 8020712:	2004      	movs	r0, #4
+ 8020714:	f7f6 f9dc 	bl	8016ad0 <memp_malloc>
+ 8020718:	60f8      	str	r0, [r7, #12]
+  if (ipr == NULL) {
+ 802071a:	68fb      	ldr	r3, [r7, #12]
+ 802071c:	2b00      	cmp	r3, #0
+ 802071e:	d110      	bne.n	8020742 <ip_reass_enqueue_new_datagram+0x3a>
+#if IP_REASS_FREE_OLDEST
+    if (ip_reass_remove_oldest_datagram(fraghdr, clen) >= clen) {
+ 8020720:	6839      	ldr	r1, [r7, #0]
+ 8020722:	6878      	ldr	r0, [r7, #4]
+ 8020724:	f7ff ff8e 	bl	8020644 <ip_reass_remove_oldest_datagram>
+ 8020728:	4602      	mov	r2, r0
+ 802072a:	683b      	ldr	r3, [r7, #0]
+ 802072c:	4293      	cmp	r3, r2
+ 802072e:	dc03      	bgt.n	8020738 <ip_reass_enqueue_new_datagram+0x30>
+      ipr = (struct ip_reassdata *)memp_malloc(MEMP_REASSDATA);
+ 8020730:	2004      	movs	r0, #4
+ 8020732:	f7f6 f9cd 	bl	8016ad0 <memp_malloc>
+ 8020736:	60f8      	str	r0, [r7, #12]
+    }
+    if (ipr == NULL)
+ 8020738:	68fb      	ldr	r3, [r7, #12]
+ 802073a:	2b00      	cmp	r3, #0
+ 802073c:	d101      	bne.n	8020742 <ip_reass_enqueue_new_datagram+0x3a>
+#endif /* IP_REASS_FREE_OLDEST */
+    {
+      IPFRAG_STATS_INC(ip_frag.memerr);
+      LWIP_DEBUGF(IP_REASS_DEBUG, ("Failed to alloc reassdata struct\n"));
+      return NULL;
+ 802073e:	2300      	movs	r3, #0
+ 8020740:	e016      	b.n	8020770 <ip_reass_enqueue_new_datagram+0x68>
+    }
+  }
+  memset(ipr, 0, sizeof(struct ip_reassdata));
+ 8020742:	2220      	movs	r2, #32
+ 8020744:	2100      	movs	r1, #0
+ 8020746:	68f8      	ldr	r0, [r7, #12]
+ 8020748:	f001 faca 	bl	8021ce0 <memset>
+  ipr->timer = IP_REASS_MAXAGE;
+ 802074c:	68fb      	ldr	r3, [r7, #12]
+ 802074e:	220f      	movs	r2, #15
+ 8020750:	77da      	strb	r2, [r3, #31]
+
+  /* enqueue the new structure to the front of the list */
+  ipr->next = reassdatagrams;
+ 8020752:	4b09      	ldr	r3, [pc, #36]	; (8020778 <ip_reass_enqueue_new_datagram+0x70>)
+ 8020754:	681a      	ldr	r2, [r3, #0]
+ 8020756:	68fb      	ldr	r3, [r7, #12]
+ 8020758:	601a      	str	r2, [r3, #0]
+  reassdatagrams = ipr;
+ 802075a:	4a07      	ldr	r2, [pc, #28]	; (8020778 <ip_reass_enqueue_new_datagram+0x70>)
+ 802075c:	68fb      	ldr	r3, [r7, #12]
+ 802075e:	6013      	str	r3, [r2, #0]
+  /* copy the ip header for later tests and input */
+  /* @todo: no ip options supported? */
+  SMEMCPY(&(ipr->iphdr), fraghdr, IP_HLEN);
+ 8020760:	68fb      	ldr	r3, [r7, #12]
+ 8020762:	3308      	adds	r3, #8
+ 8020764:	2214      	movs	r2, #20
+ 8020766:	6879      	ldr	r1, [r7, #4]
+ 8020768:	4618      	mov	r0, r3
+ 802076a:	f001 fb3c 	bl	8021de6 <memcpy>
+  return ipr;
+ 802076e:	68fb      	ldr	r3, [r7, #12]
+}
+ 8020770:	4618      	mov	r0, r3
+ 8020772:	3710      	adds	r7, #16
+ 8020774:	46bd      	mov	sp, r7
+ 8020776:	bd80      	pop	{r7, pc}
+ 8020778:	2401a5d8 	.word	0x2401a5d8
+
+0802077c <ip_reass_dequeue_datagram>:
+ * Dequeues a datagram from the datagram queue. Doesn't deallocate the pbufs.
+ * @param ipr points to the queue entry to dequeue
+ */
+static void
+ip_reass_dequeue_datagram(struct ip_reassdata *ipr, struct ip_reassdata *prev)
+{
+ 802077c:	b580      	push	{r7, lr}
+ 802077e:	b082      	sub	sp, #8
+ 8020780:	af00      	add	r7, sp, #0
+ 8020782:	6078      	str	r0, [r7, #4]
+ 8020784:	6039      	str	r1, [r7, #0]
+  /* dequeue the reass struct  */
+  if (reassdatagrams == ipr) {
+ 8020786:	4b10      	ldr	r3, [pc, #64]	; (80207c8 <ip_reass_dequeue_datagram+0x4c>)
+ 8020788:	681b      	ldr	r3, [r3, #0]
+ 802078a:	687a      	ldr	r2, [r7, #4]
+ 802078c:	429a      	cmp	r2, r3
+ 802078e:	d104      	bne.n	802079a <ip_reass_dequeue_datagram+0x1e>
+    /* it was the first in the list */
+    reassdatagrams = ipr->next;
+ 8020790:	687b      	ldr	r3, [r7, #4]
+ 8020792:	681b      	ldr	r3, [r3, #0]
+ 8020794:	4a0c      	ldr	r2, [pc, #48]	; (80207c8 <ip_reass_dequeue_datagram+0x4c>)
+ 8020796:	6013      	str	r3, [r2, #0]
+ 8020798:	e00d      	b.n	80207b6 <ip_reass_dequeue_datagram+0x3a>
+  } else {
+    /* it wasn't the first, so it must have a valid 'prev' */
+    LWIP_ASSERT("sanity check linked list", prev != NULL);
+ 802079a:	683b      	ldr	r3, [r7, #0]
+ 802079c:	2b00      	cmp	r3, #0
+ 802079e:	d106      	bne.n	80207ae <ip_reass_dequeue_datagram+0x32>
+ 80207a0:	4b0a      	ldr	r3, [pc, #40]	; (80207cc <ip_reass_dequeue_datagram+0x50>)
+ 80207a2:	f240 1245 	movw	r2, #325	; 0x145
+ 80207a6:	490a      	ldr	r1, [pc, #40]	; (80207d0 <ip_reass_dequeue_datagram+0x54>)
+ 80207a8:	480a      	ldr	r0, [pc, #40]	; (80207d4 <ip_reass_dequeue_datagram+0x58>)
+ 80207aa:	f001 f8ed 	bl	8021988 <iprintf>
+    prev->next = ipr->next;
+ 80207ae:	687b      	ldr	r3, [r7, #4]
+ 80207b0:	681a      	ldr	r2, [r3, #0]
+ 80207b2:	683b      	ldr	r3, [r7, #0]
+ 80207b4:	601a      	str	r2, [r3, #0]
+  }
+
+  /* now we can free the ip_reassdata struct */
+  memp_free(MEMP_REASSDATA, ipr);
+ 80207b6:	6879      	ldr	r1, [r7, #4]
+ 80207b8:	2004      	movs	r0, #4
+ 80207ba:	f7f6 f9ff 	bl	8016bbc <memp_free>
+}
+ 80207be:	bf00      	nop
+ 80207c0:	3708      	adds	r7, #8
+ 80207c2:	46bd      	mov	sp, r7
+ 80207c4:	bd80      	pop	{r7, pc}
+ 80207c6:	bf00      	nop
+ 80207c8:	2401a5d8 	.word	0x2401a5d8
+ 80207cc:	08026884 	.word	0x08026884
+ 80207d0:	0802694c 	.word	0x0802694c
+ 80207d4:	080268cc 	.word	0x080268cc
+
+080207d8 <ip_reass_chain_frag_into_datagram_and_validate>:
+ * @param is_last is 1 if this pbuf has MF==0 (ipr->flags not updated yet)
+ * @return see IP_REASS_VALIDATE_* defines
+ */
+static int
+ip_reass_chain_frag_into_datagram_and_validate(struct ip_reassdata *ipr, struct pbuf *new_p, int is_last)
+{
+ 80207d8:	b580      	push	{r7, lr}
+ 80207da:	b08c      	sub	sp, #48	; 0x30
+ 80207dc:	af00      	add	r7, sp, #0
+ 80207de:	60f8      	str	r0, [r7, #12]
+ 80207e0:	60b9      	str	r1, [r7, #8]
+ 80207e2:	607a      	str	r2, [r7, #4]
+  struct ip_reass_helper *iprh, *iprh_tmp, *iprh_prev = NULL;
+ 80207e4:	2300      	movs	r3, #0
+ 80207e6:	62bb      	str	r3, [r7, #40]	; 0x28
+  struct pbuf *q;
+  u16_t offset, len;
+  u8_t hlen;
+  struct ip_hdr *fraghdr;
+  int valid = 1;
+ 80207e8:	2301      	movs	r3, #1
+ 80207ea:	623b      	str	r3, [r7, #32]
+
+  /* Extract length and fragment offset from current fragment */
+  fraghdr = (struct ip_hdr *)new_p->payload;
+ 80207ec:	68bb      	ldr	r3, [r7, #8]
+ 80207ee:	685b      	ldr	r3, [r3, #4]
+ 80207f0:	61fb      	str	r3, [r7, #28]
+  len = lwip_ntohs(IPH_LEN(fraghdr));
+ 80207f2:	69fb      	ldr	r3, [r7, #28]
+ 80207f4:	885b      	ldrh	r3, [r3, #2]
+ 80207f6:	b29b      	uxth	r3, r3
+ 80207f8:	4618      	mov	r0, r3
+ 80207fa:	f7f5 fba1 	bl	8015f40 <lwip_htons>
+ 80207fe:	4603      	mov	r3, r0
+ 8020800:	837b      	strh	r3, [r7, #26]
+  hlen = IPH_HL_BYTES(fraghdr);
+ 8020802:	69fb      	ldr	r3, [r7, #28]
+ 8020804:	781b      	ldrb	r3, [r3, #0]
+ 8020806:	f003 030f 	and.w	r3, r3, #15
+ 802080a:	b2db      	uxtb	r3, r3
+ 802080c:	009b      	lsls	r3, r3, #2
+ 802080e:	767b      	strb	r3, [r7, #25]
+  if (hlen > len) {
+ 8020810:	7e7b      	ldrb	r3, [r7, #25]
+ 8020812:	b29b      	uxth	r3, r3
+ 8020814:	8b7a      	ldrh	r2, [r7, #26]
+ 8020816:	429a      	cmp	r2, r3
+ 8020818:	d202      	bcs.n	8020820 <ip_reass_chain_frag_into_datagram_and_validate+0x48>
+    /* invalid datagram */
+    return IP_REASS_VALIDATE_PBUF_DROPPED;
+ 802081a:	f04f 33ff 	mov.w	r3, #4294967295
+ 802081e:	e135      	b.n	8020a8c <ip_reass_chain_frag_into_datagram_and_validate+0x2b4>
+  }
+  len = (u16_t)(len - hlen);
+ 8020820:	7e7b      	ldrb	r3, [r7, #25]
+ 8020822:	b29b      	uxth	r3, r3
+ 8020824:	8b7a      	ldrh	r2, [r7, #26]
+ 8020826:	1ad3      	subs	r3, r2, r3
+ 8020828:	837b      	strh	r3, [r7, #26]
+  offset = IPH_OFFSET_BYTES(fraghdr);
+ 802082a:	69fb      	ldr	r3, [r7, #28]
+ 802082c:	88db      	ldrh	r3, [r3, #6]
+ 802082e:	b29b      	uxth	r3, r3
+ 8020830:	4618      	mov	r0, r3
+ 8020832:	f7f5 fb85 	bl	8015f40 <lwip_htons>
+ 8020836:	4603      	mov	r3, r0
+ 8020838:	f3c3 030c 	ubfx	r3, r3, #0, #13
+ 802083c:	b29b      	uxth	r3, r3
+ 802083e:	00db      	lsls	r3, r3, #3
+ 8020840:	82fb      	strh	r3, [r7, #22]
+  /* overwrite the fragment's ip header from the pbuf with our helper struct,
+   * and setup the embedded helper structure. */
+  /* make sure the struct ip_reass_helper fits into the IP header */
+  LWIP_ASSERT("sizeof(struct ip_reass_helper) <= IP_HLEN",
+              sizeof(struct ip_reass_helper) <= IP_HLEN);
+  iprh = (struct ip_reass_helper *)new_p->payload;
+ 8020842:	68bb      	ldr	r3, [r7, #8]
+ 8020844:	685b      	ldr	r3, [r3, #4]
+ 8020846:	62fb      	str	r3, [r7, #44]	; 0x2c
+  iprh->next_pbuf = NULL;
+ 8020848:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 802084a:	2200      	movs	r2, #0
+ 802084c:	701a      	strb	r2, [r3, #0]
+ 802084e:	2200      	movs	r2, #0
+ 8020850:	705a      	strb	r2, [r3, #1]
+ 8020852:	2200      	movs	r2, #0
+ 8020854:	709a      	strb	r2, [r3, #2]
+ 8020856:	2200      	movs	r2, #0
+ 8020858:	70da      	strb	r2, [r3, #3]
+  iprh->start = offset;
+ 802085a:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 802085c:	8afa      	ldrh	r2, [r7, #22]
+ 802085e:	809a      	strh	r2, [r3, #4]
+  iprh->end = (u16_t)(offset + len);
+ 8020860:	8afa      	ldrh	r2, [r7, #22]
+ 8020862:	8b7b      	ldrh	r3, [r7, #26]
+ 8020864:	4413      	add	r3, r2
+ 8020866:	b29a      	uxth	r2, r3
+ 8020868:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 802086a:	80da      	strh	r2, [r3, #6]
+  if (iprh->end < offset) {
+ 802086c:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 802086e:	88db      	ldrh	r3, [r3, #6]
+ 8020870:	b29b      	uxth	r3, r3
+ 8020872:	8afa      	ldrh	r2, [r7, #22]
+ 8020874:	429a      	cmp	r2, r3
+ 8020876:	d902      	bls.n	802087e <ip_reass_chain_frag_into_datagram_and_validate+0xa6>
+    /* u16_t overflow, cannot handle this */
+    return IP_REASS_VALIDATE_PBUF_DROPPED;
+ 8020878:	f04f 33ff 	mov.w	r3, #4294967295
+ 802087c:	e106      	b.n	8020a8c <ip_reass_chain_frag_into_datagram_and_validate+0x2b4>
+  }
+
+  /* Iterate through until we either get to the end of the list (append),
+   * or we find one with a larger offset (insert). */
+  for (q = ipr->p; q != NULL;) {
+ 802087e:	68fb      	ldr	r3, [r7, #12]
+ 8020880:	685b      	ldr	r3, [r3, #4]
+ 8020882:	627b      	str	r3, [r7, #36]	; 0x24
+ 8020884:	e068      	b.n	8020958 <ip_reass_chain_frag_into_datagram_and_validate+0x180>
+    iprh_tmp = (struct ip_reass_helper *)q->payload;
+ 8020886:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 8020888:	685b      	ldr	r3, [r3, #4]
+ 802088a:	613b      	str	r3, [r7, #16]
+    if (iprh->start < iprh_tmp->start) {
+ 802088c:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 802088e:	889b      	ldrh	r3, [r3, #4]
+ 8020890:	b29a      	uxth	r2, r3
+ 8020892:	693b      	ldr	r3, [r7, #16]
+ 8020894:	889b      	ldrh	r3, [r3, #4]
+ 8020896:	b29b      	uxth	r3, r3
+ 8020898:	429a      	cmp	r2, r3
+ 802089a:	d235      	bcs.n	8020908 <ip_reass_chain_frag_into_datagram_and_validate+0x130>
+      /* the new pbuf should be inserted before this */
+      iprh->next_pbuf = q;
+ 802089c:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 802089e:	6a7a      	ldr	r2, [r7, #36]	; 0x24
+ 80208a0:	601a      	str	r2, [r3, #0]
+      if (iprh_prev != NULL) {
+ 80208a2:	6abb      	ldr	r3, [r7, #40]	; 0x28
+ 80208a4:	2b00      	cmp	r3, #0
+ 80208a6:	d020      	beq.n	80208ea <ip_reass_chain_frag_into_datagram_and_validate+0x112>
+        /* not the fragment with the lowest offset */
+#if IP_REASS_CHECK_OVERLAP
+        if ((iprh->start < iprh_prev->end) || (iprh->end > iprh_tmp->start)) {
+ 80208a8:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 80208aa:	889b      	ldrh	r3, [r3, #4]
+ 80208ac:	b29a      	uxth	r2, r3
+ 80208ae:	6abb      	ldr	r3, [r7, #40]	; 0x28
+ 80208b0:	88db      	ldrh	r3, [r3, #6]
+ 80208b2:	b29b      	uxth	r3, r3
+ 80208b4:	429a      	cmp	r2, r3
+ 80208b6:	d307      	bcc.n	80208c8 <ip_reass_chain_frag_into_datagram_and_validate+0xf0>
+ 80208b8:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 80208ba:	88db      	ldrh	r3, [r3, #6]
+ 80208bc:	b29a      	uxth	r2, r3
+ 80208be:	693b      	ldr	r3, [r7, #16]
+ 80208c0:	889b      	ldrh	r3, [r3, #4]
+ 80208c2:	b29b      	uxth	r3, r3
+ 80208c4:	429a      	cmp	r2, r3
+ 80208c6:	d902      	bls.n	80208ce <ip_reass_chain_frag_into_datagram_and_validate+0xf6>
+          /* fragment overlaps with previous or following, throw away */
+          return IP_REASS_VALIDATE_PBUF_DROPPED;
+ 80208c8:	f04f 33ff 	mov.w	r3, #4294967295
+ 80208cc:	e0de      	b.n	8020a8c <ip_reass_chain_frag_into_datagram_and_validate+0x2b4>
+        }
+#endif /* IP_REASS_CHECK_OVERLAP */
+        iprh_prev->next_pbuf = new_p;
+ 80208ce:	6abb      	ldr	r3, [r7, #40]	; 0x28
+ 80208d0:	68ba      	ldr	r2, [r7, #8]
+ 80208d2:	601a      	str	r2, [r3, #0]
+        if (iprh_prev->end != iprh->start) {
+ 80208d4:	6abb      	ldr	r3, [r7, #40]	; 0x28
+ 80208d6:	88db      	ldrh	r3, [r3, #6]
+ 80208d8:	b29a      	uxth	r2, r3
+ 80208da:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 80208dc:	889b      	ldrh	r3, [r3, #4]
+ 80208de:	b29b      	uxth	r3, r3
+ 80208e0:	429a      	cmp	r2, r3
+ 80208e2:	d03d      	beq.n	8020960 <ip_reass_chain_frag_into_datagram_and_validate+0x188>
+          /* There is a fragment missing between the current
+           * and the previous fragment */
+          valid = 0;
+ 80208e4:	2300      	movs	r3, #0
+ 80208e6:	623b      	str	r3, [r7, #32]
+        }
+#endif /* IP_REASS_CHECK_OVERLAP */
+        /* fragment with the lowest offset */
+        ipr->p = new_p;
+      }
+      break;
+ 80208e8:	e03a      	b.n	8020960 <ip_reass_chain_frag_into_datagram_and_validate+0x188>
+        if (iprh->end > iprh_tmp->start) {
+ 80208ea:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 80208ec:	88db      	ldrh	r3, [r3, #6]
+ 80208ee:	b29a      	uxth	r2, r3
+ 80208f0:	693b      	ldr	r3, [r7, #16]
+ 80208f2:	889b      	ldrh	r3, [r3, #4]
+ 80208f4:	b29b      	uxth	r3, r3
+ 80208f6:	429a      	cmp	r2, r3
+ 80208f8:	d902      	bls.n	8020900 <ip_reass_chain_frag_into_datagram_and_validate+0x128>
+          return IP_REASS_VALIDATE_PBUF_DROPPED;
+ 80208fa:	f04f 33ff 	mov.w	r3, #4294967295
+ 80208fe:	e0c5      	b.n	8020a8c <ip_reass_chain_frag_into_datagram_and_validate+0x2b4>
+        ipr->p = new_p;
+ 8020900:	68fb      	ldr	r3, [r7, #12]
+ 8020902:	68ba      	ldr	r2, [r7, #8]
+ 8020904:	605a      	str	r2, [r3, #4]
+      break;
+ 8020906:	e02b      	b.n	8020960 <ip_reass_chain_frag_into_datagram_and_validate+0x188>
+    } else if (iprh->start == iprh_tmp->start) {
+ 8020908:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 802090a:	889b      	ldrh	r3, [r3, #4]
+ 802090c:	b29a      	uxth	r2, r3
+ 802090e:	693b      	ldr	r3, [r7, #16]
+ 8020910:	889b      	ldrh	r3, [r3, #4]
+ 8020912:	b29b      	uxth	r3, r3
+ 8020914:	429a      	cmp	r2, r3
+ 8020916:	d102      	bne.n	802091e <ip_reass_chain_frag_into_datagram_and_validate+0x146>
+      /* received the same datagram twice: no need to keep the datagram */
+      return IP_REASS_VALIDATE_PBUF_DROPPED;
+ 8020918:	f04f 33ff 	mov.w	r3, #4294967295
+ 802091c:	e0b6      	b.n	8020a8c <ip_reass_chain_frag_into_datagram_and_validate+0x2b4>
+#if IP_REASS_CHECK_OVERLAP
+    } else if (iprh->start < iprh_tmp->end) {
+ 802091e:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 8020920:	889b      	ldrh	r3, [r3, #4]
+ 8020922:	b29a      	uxth	r2, r3
+ 8020924:	693b      	ldr	r3, [r7, #16]
+ 8020926:	88db      	ldrh	r3, [r3, #6]
+ 8020928:	b29b      	uxth	r3, r3
+ 802092a:	429a      	cmp	r2, r3
+ 802092c:	d202      	bcs.n	8020934 <ip_reass_chain_frag_into_datagram_and_validate+0x15c>
+      /* overlap: no need to keep the new datagram */
+      return IP_REASS_VALIDATE_PBUF_DROPPED;
+ 802092e:	f04f 33ff 	mov.w	r3, #4294967295
+ 8020932:	e0ab      	b.n	8020a8c <ip_reass_chain_frag_into_datagram_and_validate+0x2b4>
+#endif /* IP_REASS_CHECK_OVERLAP */
+    } else {
+      /* Check if the fragments received so far have no holes. */
+      if (iprh_prev != NULL) {
+ 8020934:	6abb      	ldr	r3, [r7, #40]	; 0x28
+ 8020936:	2b00      	cmp	r3, #0
+ 8020938:	d009      	beq.n	802094e <ip_reass_chain_frag_into_datagram_and_validate+0x176>
+        if (iprh_prev->end != iprh_tmp->start) {
+ 802093a:	6abb      	ldr	r3, [r7, #40]	; 0x28
+ 802093c:	88db      	ldrh	r3, [r3, #6]
+ 802093e:	b29a      	uxth	r2, r3
+ 8020940:	693b      	ldr	r3, [r7, #16]
+ 8020942:	889b      	ldrh	r3, [r3, #4]
+ 8020944:	b29b      	uxth	r3, r3
+ 8020946:	429a      	cmp	r2, r3
+ 8020948:	d001      	beq.n	802094e <ip_reass_chain_frag_into_datagram_and_validate+0x176>
+          /* There is a fragment missing between the current
+           * and the previous fragment */
+          valid = 0;
+ 802094a:	2300      	movs	r3, #0
+ 802094c:	623b      	str	r3, [r7, #32]
+        }
+      }
+    }
+    q = iprh_tmp->next_pbuf;
+ 802094e:	693b      	ldr	r3, [r7, #16]
+ 8020950:	681b      	ldr	r3, [r3, #0]
+ 8020952:	627b      	str	r3, [r7, #36]	; 0x24
+    iprh_prev = iprh_tmp;
+ 8020954:	693b      	ldr	r3, [r7, #16]
+ 8020956:	62bb      	str	r3, [r7, #40]	; 0x28
+  for (q = ipr->p; q != NULL;) {
+ 8020958:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 802095a:	2b00      	cmp	r3, #0
+ 802095c:	d193      	bne.n	8020886 <ip_reass_chain_frag_into_datagram_and_validate+0xae>
+ 802095e:	e000      	b.n	8020962 <ip_reass_chain_frag_into_datagram_and_validate+0x18a>
+      break;
+ 8020960:	bf00      	nop
+  }
+
+  /* If q is NULL, then we made it to the end of the list. Determine what to do now */
+  if (q == NULL) {
+ 8020962:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 8020964:	2b00      	cmp	r3, #0
+ 8020966:	d12d      	bne.n	80209c4 <ip_reass_chain_frag_into_datagram_and_validate+0x1ec>
+    if (iprh_prev != NULL) {
+ 8020968:	6abb      	ldr	r3, [r7, #40]	; 0x28
+ 802096a:	2b00      	cmp	r3, #0
+ 802096c:	d01c      	beq.n	80209a8 <ip_reass_chain_frag_into_datagram_and_validate+0x1d0>
+      /* this is (for now), the fragment with the highest offset:
+       * chain it to the last fragment */
+#if IP_REASS_CHECK_OVERLAP
+      LWIP_ASSERT("check fragments don't overlap", iprh_prev->end <= iprh->start);
+ 802096e:	6abb      	ldr	r3, [r7, #40]	; 0x28
+ 8020970:	88db      	ldrh	r3, [r3, #6]
+ 8020972:	b29a      	uxth	r2, r3
+ 8020974:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 8020976:	889b      	ldrh	r3, [r3, #4]
+ 8020978:	b29b      	uxth	r3, r3
+ 802097a:	429a      	cmp	r2, r3
+ 802097c:	d906      	bls.n	802098c <ip_reass_chain_frag_into_datagram_and_validate+0x1b4>
+ 802097e:	4b45      	ldr	r3, [pc, #276]	; (8020a94 <ip_reass_chain_frag_into_datagram_and_validate+0x2bc>)
+ 8020980:	f44f 72db 	mov.w	r2, #438	; 0x1b6
+ 8020984:	4944      	ldr	r1, [pc, #272]	; (8020a98 <ip_reass_chain_frag_into_datagram_and_validate+0x2c0>)
+ 8020986:	4845      	ldr	r0, [pc, #276]	; (8020a9c <ip_reass_chain_frag_into_datagram_and_validate+0x2c4>)
+ 8020988:	f000 fffe 	bl	8021988 <iprintf>
+#endif /* IP_REASS_CHECK_OVERLAP */
+      iprh_prev->next_pbuf = new_p;
+ 802098c:	6abb      	ldr	r3, [r7, #40]	; 0x28
+ 802098e:	68ba      	ldr	r2, [r7, #8]
+ 8020990:	601a      	str	r2, [r3, #0]
+      if (iprh_prev->end != iprh->start) {
+ 8020992:	6abb      	ldr	r3, [r7, #40]	; 0x28
+ 8020994:	88db      	ldrh	r3, [r3, #6]
+ 8020996:	b29a      	uxth	r2, r3
+ 8020998:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 802099a:	889b      	ldrh	r3, [r3, #4]
+ 802099c:	b29b      	uxth	r3, r3
+ 802099e:	429a      	cmp	r2, r3
+ 80209a0:	d010      	beq.n	80209c4 <ip_reass_chain_frag_into_datagram_and_validate+0x1ec>
+        valid = 0;
+ 80209a2:	2300      	movs	r3, #0
+ 80209a4:	623b      	str	r3, [r7, #32]
+ 80209a6:	e00d      	b.n	80209c4 <ip_reass_chain_frag_into_datagram_and_validate+0x1ec>
+      }
+    } else {
+#if IP_REASS_CHECK_OVERLAP
+      LWIP_ASSERT("no previous fragment, this must be the first fragment!",
+ 80209a8:	68fb      	ldr	r3, [r7, #12]
+ 80209aa:	685b      	ldr	r3, [r3, #4]
+ 80209ac:	2b00      	cmp	r3, #0
+ 80209ae:	d006      	beq.n	80209be <ip_reass_chain_frag_into_datagram_and_validate+0x1e6>
+ 80209b0:	4b38      	ldr	r3, [pc, #224]	; (8020a94 <ip_reass_chain_frag_into_datagram_and_validate+0x2bc>)
+ 80209b2:	f44f 72df 	mov.w	r2, #446	; 0x1be
+ 80209b6:	493a      	ldr	r1, [pc, #232]	; (8020aa0 <ip_reass_chain_frag_into_datagram_and_validate+0x2c8>)
+ 80209b8:	4838      	ldr	r0, [pc, #224]	; (8020a9c <ip_reass_chain_frag_into_datagram_and_validate+0x2c4>)
+ 80209ba:	f000 ffe5 	bl	8021988 <iprintf>
+                  ipr->p == NULL);
+#endif /* IP_REASS_CHECK_OVERLAP */
+      /* this is the first fragment we ever received for this ip datagram */
+      ipr->p = new_p;
+ 80209be:	68fb      	ldr	r3, [r7, #12]
+ 80209c0:	68ba      	ldr	r2, [r7, #8]
+ 80209c2:	605a      	str	r2, [r3, #4]
+    }
+  }
+
+  /* At this point, the validation part begins: */
+  /* If we already received the last fragment */
+  if (is_last || ((ipr->flags & IP_REASS_FLAG_LASTFRAG) != 0)) {
+ 80209c4:	687b      	ldr	r3, [r7, #4]
+ 80209c6:	2b00      	cmp	r3, #0
+ 80209c8:	d105      	bne.n	80209d6 <ip_reass_chain_frag_into_datagram_and_validate+0x1fe>
+ 80209ca:	68fb      	ldr	r3, [r7, #12]
+ 80209cc:	7f9b      	ldrb	r3, [r3, #30]
+ 80209ce:	f003 0301 	and.w	r3, r3, #1
+ 80209d2:	2b00      	cmp	r3, #0
+ 80209d4:	d059      	beq.n	8020a8a <ip_reass_chain_frag_into_datagram_and_validate+0x2b2>
+    /* and had no holes so far */
+    if (valid) {
+ 80209d6:	6a3b      	ldr	r3, [r7, #32]
+ 80209d8:	2b00      	cmp	r3, #0
+ 80209da:	d04f      	beq.n	8020a7c <ip_reass_chain_frag_into_datagram_and_validate+0x2a4>
+      /* then check if the rest of the fragments is here */
+      /* Check if the queue starts with the first datagram */
+      if ((ipr->p == NULL) || (((struct ip_reass_helper *)ipr->p->payload)->start != 0)) {
+ 80209dc:	68fb      	ldr	r3, [r7, #12]
+ 80209de:	685b      	ldr	r3, [r3, #4]
+ 80209e0:	2b00      	cmp	r3, #0
+ 80209e2:	d006      	beq.n	80209f2 <ip_reass_chain_frag_into_datagram_and_validate+0x21a>
+ 80209e4:	68fb      	ldr	r3, [r7, #12]
+ 80209e6:	685b      	ldr	r3, [r3, #4]
+ 80209e8:	685b      	ldr	r3, [r3, #4]
+ 80209ea:	889b      	ldrh	r3, [r3, #4]
+ 80209ec:	b29b      	uxth	r3, r3
+ 80209ee:	2b00      	cmp	r3, #0
+ 80209f0:	d002      	beq.n	80209f8 <ip_reass_chain_frag_into_datagram_and_validate+0x220>
+        valid = 0;
+ 80209f2:	2300      	movs	r3, #0
+ 80209f4:	623b      	str	r3, [r7, #32]
+ 80209f6:	e041      	b.n	8020a7c <ip_reass_chain_frag_into_datagram_and_validate+0x2a4>
+      } else {
+        /* and check that there are no holes after this datagram */
+        iprh_prev = iprh;
+ 80209f8:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 80209fa:	62bb      	str	r3, [r7, #40]	; 0x28
+        q = iprh->next_pbuf;
+ 80209fc:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 80209fe:	681b      	ldr	r3, [r3, #0]
+ 8020a00:	627b      	str	r3, [r7, #36]	; 0x24
+        while (q != NULL) {
+ 8020a02:	e012      	b.n	8020a2a <ip_reass_chain_frag_into_datagram_and_validate+0x252>
+          iprh = (struct ip_reass_helper *)q->payload;
+ 8020a04:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 8020a06:	685b      	ldr	r3, [r3, #4]
+ 8020a08:	62fb      	str	r3, [r7, #44]	; 0x2c
+          if (iprh_prev->end != iprh->start) {
+ 8020a0a:	6abb      	ldr	r3, [r7, #40]	; 0x28
+ 8020a0c:	88db      	ldrh	r3, [r3, #6]
+ 8020a0e:	b29a      	uxth	r2, r3
+ 8020a10:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 8020a12:	889b      	ldrh	r3, [r3, #4]
+ 8020a14:	b29b      	uxth	r3, r3
+ 8020a16:	429a      	cmp	r2, r3
+ 8020a18:	d002      	beq.n	8020a20 <ip_reass_chain_frag_into_datagram_and_validate+0x248>
+            valid = 0;
+ 8020a1a:	2300      	movs	r3, #0
+ 8020a1c:	623b      	str	r3, [r7, #32]
+            break;
+ 8020a1e:	e007      	b.n	8020a30 <ip_reass_chain_frag_into_datagram_and_validate+0x258>
+          }
+          iprh_prev = iprh;
+ 8020a20:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 8020a22:	62bb      	str	r3, [r7, #40]	; 0x28
+          q = iprh->next_pbuf;
+ 8020a24:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 8020a26:	681b      	ldr	r3, [r3, #0]
+ 8020a28:	627b      	str	r3, [r7, #36]	; 0x24
+        while (q != NULL) {
+ 8020a2a:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 8020a2c:	2b00      	cmp	r3, #0
+ 8020a2e:	d1e9      	bne.n	8020a04 <ip_reass_chain_frag_into_datagram_and_validate+0x22c>
+        }
+        /* if still valid, all fragments are received
+         * (because to the MF==0 already arrived */
+        if (valid) {
+ 8020a30:	6a3b      	ldr	r3, [r7, #32]
+ 8020a32:	2b00      	cmp	r3, #0
+ 8020a34:	d022      	beq.n	8020a7c <ip_reass_chain_frag_into_datagram_and_validate+0x2a4>
+          LWIP_ASSERT("sanity check", ipr->p != NULL);
+ 8020a36:	68fb      	ldr	r3, [r7, #12]
+ 8020a38:	685b      	ldr	r3, [r3, #4]
+ 8020a3a:	2b00      	cmp	r3, #0
+ 8020a3c:	d106      	bne.n	8020a4c <ip_reass_chain_frag_into_datagram_and_validate+0x274>
+ 8020a3e:	4b15      	ldr	r3, [pc, #84]	; (8020a94 <ip_reass_chain_frag_into_datagram_and_validate+0x2bc>)
+ 8020a40:	f240 12df 	movw	r2, #479	; 0x1df
+ 8020a44:	4917      	ldr	r1, [pc, #92]	; (8020aa4 <ip_reass_chain_frag_into_datagram_and_validate+0x2cc>)
+ 8020a46:	4815      	ldr	r0, [pc, #84]	; (8020a9c <ip_reass_chain_frag_into_datagram_and_validate+0x2c4>)
+ 8020a48:	f000 ff9e 	bl	8021988 <iprintf>
+          LWIP_ASSERT("sanity check",
+ 8020a4c:	68fb      	ldr	r3, [r7, #12]
+ 8020a4e:	685b      	ldr	r3, [r3, #4]
+ 8020a50:	685b      	ldr	r3, [r3, #4]
+ 8020a52:	6afa      	ldr	r2, [r7, #44]	; 0x2c
+ 8020a54:	429a      	cmp	r2, r3
+ 8020a56:	d106      	bne.n	8020a66 <ip_reass_chain_frag_into_datagram_and_validate+0x28e>
+ 8020a58:	4b0e      	ldr	r3, [pc, #56]	; (8020a94 <ip_reass_chain_frag_into_datagram_and_validate+0x2bc>)
+ 8020a5a:	f44f 72f0 	mov.w	r2, #480	; 0x1e0
+ 8020a5e:	4911      	ldr	r1, [pc, #68]	; (8020aa4 <ip_reass_chain_frag_into_datagram_and_validate+0x2cc>)
+ 8020a60:	480e      	ldr	r0, [pc, #56]	; (8020a9c <ip_reass_chain_frag_into_datagram_and_validate+0x2c4>)
+ 8020a62:	f000 ff91 	bl	8021988 <iprintf>
+                      ((struct ip_reass_helper *)ipr->p->payload) != iprh);
+          LWIP_ASSERT("validate_datagram:next_pbuf!=NULL",
+ 8020a66:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 8020a68:	681b      	ldr	r3, [r3, #0]
+ 8020a6a:	2b00      	cmp	r3, #0
+ 8020a6c:	d006      	beq.n	8020a7c <ip_reass_chain_frag_into_datagram_and_validate+0x2a4>
+ 8020a6e:	4b09      	ldr	r3, [pc, #36]	; (8020a94 <ip_reass_chain_frag_into_datagram_and_validate+0x2bc>)
+ 8020a70:	f44f 72f1 	mov.w	r2, #482	; 0x1e2
+ 8020a74:	490c      	ldr	r1, [pc, #48]	; (8020aa8 <ip_reass_chain_frag_into_datagram_and_validate+0x2d0>)
+ 8020a76:	4809      	ldr	r0, [pc, #36]	; (8020a9c <ip_reass_chain_frag_into_datagram_and_validate+0x2c4>)
+ 8020a78:	f000 ff86 	bl	8021988 <iprintf>
+      }
+    }
+    /* If valid is 0 here, there are some fragments missing in the middle
+     * (since MF == 0 has already arrived). Such datagrams simply time out if
+     * no more fragments are received... */
+    return valid ? IP_REASS_VALIDATE_TELEGRAM_FINISHED : IP_REASS_VALIDATE_PBUF_QUEUED;
+ 8020a7c:	6a3b      	ldr	r3, [r7, #32]
+ 8020a7e:	2b00      	cmp	r3, #0
+ 8020a80:	bf14      	ite	ne
+ 8020a82:	2301      	movne	r3, #1
+ 8020a84:	2300      	moveq	r3, #0
+ 8020a86:	b2db      	uxtb	r3, r3
+ 8020a88:	e000      	b.n	8020a8c <ip_reass_chain_frag_into_datagram_and_validate+0x2b4>
+  }
+  /* If we come here, not all fragments were received, yet! */
+  return IP_REASS_VALIDATE_PBUF_QUEUED; /* not yet valid! */
+ 8020a8a:	2300      	movs	r3, #0
+}
+ 8020a8c:	4618      	mov	r0, r3
+ 8020a8e:	3730      	adds	r7, #48	; 0x30
+ 8020a90:	46bd      	mov	sp, r7
+ 8020a92:	bd80      	pop	{r7, pc}
+ 8020a94:	08026884 	.word	0x08026884
+ 8020a98:	08026968 	.word	0x08026968
+ 8020a9c:	080268cc 	.word	0x080268cc
+ 8020aa0:	08026988 	.word	0x08026988
+ 8020aa4:	080269c0 	.word	0x080269c0
+ 8020aa8:	080269d0 	.word	0x080269d0
+
+08020aac <ip4_reass>:
+ * @param p points to a pbuf chain of the fragment
+ * @return NULL if reassembly is incomplete, ? otherwise
+ */
+struct pbuf *
+ip4_reass(struct pbuf *p)
+{
+ 8020aac:	b580      	push	{r7, lr}
+ 8020aae:	b08e      	sub	sp, #56	; 0x38
+ 8020ab0:	af00      	add	r7, sp, #0
+ 8020ab2:	6078      	str	r0, [r7, #4]
+  int is_last;
+
+  IPFRAG_STATS_INC(ip_frag.recv);
+  MIB2_STATS_INC(mib2.ipreasmreqds);
+
+  fraghdr = (struct ip_hdr *)p->payload;
+ 8020ab4:	687b      	ldr	r3, [r7, #4]
+ 8020ab6:	685b      	ldr	r3, [r3, #4]
+ 8020ab8:	62bb      	str	r3, [r7, #40]	; 0x28
+
+  if (IPH_HL_BYTES(fraghdr) != IP_HLEN) {
+ 8020aba:	6abb      	ldr	r3, [r7, #40]	; 0x28
+ 8020abc:	781b      	ldrb	r3, [r3, #0]
+ 8020abe:	f003 030f 	and.w	r3, r3, #15
+ 8020ac2:	b2db      	uxtb	r3, r3
+ 8020ac4:	009b      	lsls	r3, r3, #2
+ 8020ac6:	b2db      	uxtb	r3, r3
+ 8020ac8:	2b14      	cmp	r3, #20
+ 8020aca:	f040 8171 	bne.w	8020db0 <ip4_reass+0x304>
+    LWIP_DEBUGF(IP_REASS_DEBUG, ("ip4_reass: IP options currently not supported!\n"));
+    IPFRAG_STATS_INC(ip_frag.err);
+    goto nullreturn;
+  }
+
+  offset = IPH_OFFSET_BYTES(fraghdr);
+ 8020ace:	6abb      	ldr	r3, [r7, #40]	; 0x28
+ 8020ad0:	88db      	ldrh	r3, [r3, #6]
+ 8020ad2:	b29b      	uxth	r3, r3
+ 8020ad4:	4618      	mov	r0, r3
+ 8020ad6:	f7f5 fa33 	bl	8015f40 <lwip_htons>
+ 8020ada:	4603      	mov	r3, r0
+ 8020adc:	f3c3 030c 	ubfx	r3, r3, #0, #13
+ 8020ae0:	b29b      	uxth	r3, r3
+ 8020ae2:	00db      	lsls	r3, r3, #3
+ 8020ae4:	84fb      	strh	r3, [r7, #38]	; 0x26
+  len = lwip_ntohs(IPH_LEN(fraghdr));
+ 8020ae6:	6abb      	ldr	r3, [r7, #40]	; 0x28
+ 8020ae8:	885b      	ldrh	r3, [r3, #2]
+ 8020aea:	b29b      	uxth	r3, r3
+ 8020aec:	4618      	mov	r0, r3
+ 8020aee:	f7f5 fa27 	bl	8015f40 <lwip_htons>
+ 8020af2:	4603      	mov	r3, r0
+ 8020af4:	84bb      	strh	r3, [r7, #36]	; 0x24
+  hlen = IPH_HL_BYTES(fraghdr);
+ 8020af6:	6abb      	ldr	r3, [r7, #40]	; 0x28
+ 8020af8:	781b      	ldrb	r3, [r3, #0]
+ 8020afa:	f003 030f 	and.w	r3, r3, #15
+ 8020afe:	b2db      	uxtb	r3, r3
+ 8020b00:	009b      	lsls	r3, r3, #2
+ 8020b02:	f887 3023 	strb.w	r3, [r7, #35]	; 0x23
+  if (hlen > len) {
+ 8020b06:	f897 3023 	ldrb.w	r3, [r7, #35]	; 0x23
+ 8020b0a:	b29b      	uxth	r3, r3
+ 8020b0c:	8cba      	ldrh	r2, [r7, #36]	; 0x24
+ 8020b0e:	429a      	cmp	r2, r3
+ 8020b10:	f0c0 8150 	bcc.w	8020db4 <ip4_reass+0x308>
+    /* invalid datagram */
+    goto nullreturn;
+  }
+  len = (u16_t)(len - hlen);
+ 8020b14:	f897 3023 	ldrb.w	r3, [r7, #35]	; 0x23
+ 8020b18:	b29b      	uxth	r3, r3
+ 8020b1a:	8cba      	ldrh	r2, [r7, #36]	; 0x24
+ 8020b1c:	1ad3      	subs	r3, r2, r3
+ 8020b1e:	84bb      	strh	r3, [r7, #36]	; 0x24
+
+  /* Check if we are allowed to enqueue more datagrams. */
+  clen = pbuf_clen(p);
+ 8020b20:	6878      	ldr	r0, [r7, #4]
+ 8020b22:	f7f7 f877 	bl	8017c14 <pbuf_clen>
+ 8020b26:	4603      	mov	r3, r0
+ 8020b28:	843b      	strh	r3, [r7, #32]
+  if ((ip_reass_pbufcount + clen) > IP_REASS_MAX_PBUFS) {
+ 8020b2a:	4b8c      	ldr	r3, [pc, #560]	; (8020d5c <ip4_reass+0x2b0>)
+ 8020b2c:	881b      	ldrh	r3, [r3, #0]
+ 8020b2e:	461a      	mov	r2, r3
+ 8020b30:	8c3b      	ldrh	r3, [r7, #32]
+ 8020b32:	4413      	add	r3, r2
+ 8020b34:	2b0a      	cmp	r3, #10
+ 8020b36:	dd10      	ble.n	8020b5a <ip4_reass+0xae>
+#if IP_REASS_FREE_OLDEST
+    if (!ip_reass_remove_oldest_datagram(fraghdr, clen) ||
+ 8020b38:	8c3b      	ldrh	r3, [r7, #32]
+ 8020b3a:	4619      	mov	r1, r3
+ 8020b3c:	6ab8      	ldr	r0, [r7, #40]	; 0x28
+ 8020b3e:	f7ff fd81 	bl	8020644 <ip_reass_remove_oldest_datagram>
+ 8020b42:	4603      	mov	r3, r0
+ 8020b44:	2b00      	cmp	r3, #0
+ 8020b46:	f000 8137 	beq.w	8020db8 <ip4_reass+0x30c>
+        ((ip_reass_pbufcount + clen) > IP_REASS_MAX_PBUFS))
+ 8020b4a:	4b84      	ldr	r3, [pc, #528]	; (8020d5c <ip4_reass+0x2b0>)
+ 8020b4c:	881b      	ldrh	r3, [r3, #0]
+ 8020b4e:	461a      	mov	r2, r3
+ 8020b50:	8c3b      	ldrh	r3, [r7, #32]
+ 8020b52:	4413      	add	r3, r2
+    if (!ip_reass_remove_oldest_datagram(fraghdr, clen) ||
+ 8020b54:	2b0a      	cmp	r3, #10
+ 8020b56:	f300 812f 	bgt.w	8020db8 <ip4_reass+0x30c>
+    }
+  }
+
+  /* Look for the datagram the fragment belongs to in the current datagram queue,
+   * remembering the previous in the queue for later dequeueing. */
+  for (ipr = reassdatagrams; ipr != NULL; ipr = ipr->next) {
+ 8020b5a:	4b81      	ldr	r3, [pc, #516]	; (8020d60 <ip4_reass+0x2b4>)
+ 8020b5c:	681b      	ldr	r3, [r3, #0]
+ 8020b5e:	633b      	str	r3, [r7, #48]	; 0x30
+ 8020b60:	e015      	b.n	8020b8e <ip4_reass+0xe2>
+    /* Check if the incoming fragment matches the one currently present
+       in the reassembly buffer. If so, we proceed with copying the
+       fragment into the buffer. */
+    if (IP_ADDRESSES_AND_ID_MATCH(&ipr->iphdr, fraghdr)) {
+ 8020b62:	6b3b      	ldr	r3, [r7, #48]	; 0x30
+ 8020b64:	695a      	ldr	r2, [r3, #20]
+ 8020b66:	6abb      	ldr	r3, [r7, #40]	; 0x28
+ 8020b68:	68db      	ldr	r3, [r3, #12]
+ 8020b6a:	429a      	cmp	r2, r3
+ 8020b6c:	d10c      	bne.n	8020b88 <ip4_reass+0xdc>
+ 8020b6e:	6b3b      	ldr	r3, [r7, #48]	; 0x30
+ 8020b70:	699a      	ldr	r2, [r3, #24]
+ 8020b72:	6abb      	ldr	r3, [r7, #40]	; 0x28
+ 8020b74:	691b      	ldr	r3, [r3, #16]
+ 8020b76:	429a      	cmp	r2, r3
+ 8020b78:	d106      	bne.n	8020b88 <ip4_reass+0xdc>
+ 8020b7a:	6b3b      	ldr	r3, [r7, #48]	; 0x30
+ 8020b7c:	899a      	ldrh	r2, [r3, #12]
+ 8020b7e:	6abb      	ldr	r3, [r7, #40]	; 0x28
+ 8020b80:	889b      	ldrh	r3, [r3, #4]
+ 8020b82:	b29b      	uxth	r3, r3
+ 8020b84:	429a      	cmp	r2, r3
+ 8020b86:	d006      	beq.n	8020b96 <ip4_reass+0xea>
+  for (ipr = reassdatagrams; ipr != NULL; ipr = ipr->next) {
+ 8020b88:	6b3b      	ldr	r3, [r7, #48]	; 0x30
+ 8020b8a:	681b      	ldr	r3, [r3, #0]
+ 8020b8c:	633b      	str	r3, [r7, #48]	; 0x30
+ 8020b8e:	6b3b      	ldr	r3, [r7, #48]	; 0x30
+ 8020b90:	2b00      	cmp	r3, #0
+ 8020b92:	d1e6      	bne.n	8020b62 <ip4_reass+0xb6>
+ 8020b94:	e000      	b.n	8020b98 <ip4_reass+0xec>
+      LWIP_DEBUGF(IP_REASS_DEBUG, ("ip4_reass: matching previous fragment ID=%"X16_F"\n",
+                                   lwip_ntohs(IPH_ID(fraghdr))));
+      IPFRAG_STATS_INC(ip_frag.cachehit);
+      break;
+ 8020b96:	bf00      	nop
+    }
+  }
+
+  if (ipr == NULL) {
+ 8020b98:	6b3b      	ldr	r3, [r7, #48]	; 0x30
+ 8020b9a:	2b00      	cmp	r3, #0
+ 8020b9c:	d109      	bne.n	8020bb2 <ip4_reass+0x106>
+    /* Enqueue a new datagram into the datagram queue */
+    ipr = ip_reass_enqueue_new_datagram(fraghdr, clen);
+ 8020b9e:	8c3b      	ldrh	r3, [r7, #32]
+ 8020ba0:	4619      	mov	r1, r3
+ 8020ba2:	6ab8      	ldr	r0, [r7, #40]	; 0x28
+ 8020ba4:	f7ff fdb0 	bl	8020708 <ip_reass_enqueue_new_datagram>
+ 8020ba8:	6338      	str	r0, [r7, #48]	; 0x30
+    /* Bail if unable to enqueue */
+    if (ipr == NULL) {
+ 8020baa:	6b3b      	ldr	r3, [r7, #48]	; 0x30
+ 8020bac:	2b00      	cmp	r3, #0
+ 8020bae:	d11c      	bne.n	8020bea <ip4_reass+0x13e>
+      goto nullreturn;
+ 8020bb0:	e105      	b.n	8020dbe <ip4_reass+0x312>
+    }
+  } else {
+    if (((lwip_ntohs(IPH_OFFSET(fraghdr)) & IP_OFFMASK) == 0) &&
+ 8020bb2:	6abb      	ldr	r3, [r7, #40]	; 0x28
+ 8020bb4:	88db      	ldrh	r3, [r3, #6]
+ 8020bb6:	b29b      	uxth	r3, r3
+ 8020bb8:	4618      	mov	r0, r3
+ 8020bba:	f7f5 f9c1 	bl	8015f40 <lwip_htons>
+ 8020bbe:	4603      	mov	r3, r0
+ 8020bc0:	f3c3 030c 	ubfx	r3, r3, #0, #13
+ 8020bc4:	2b00      	cmp	r3, #0
+ 8020bc6:	d110      	bne.n	8020bea <ip4_reass+0x13e>
+        ((lwip_ntohs(IPH_OFFSET(&ipr->iphdr)) & IP_OFFMASK) != 0)) {
+ 8020bc8:	6b3b      	ldr	r3, [r7, #48]	; 0x30
+ 8020bca:	89db      	ldrh	r3, [r3, #14]
+ 8020bcc:	4618      	mov	r0, r3
+ 8020bce:	f7f5 f9b7 	bl	8015f40 <lwip_htons>
+ 8020bd2:	4603      	mov	r3, r0
+ 8020bd4:	f3c3 030c 	ubfx	r3, r3, #0, #13
+    if (((lwip_ntohs(IPH_OFFSET(fraghdr)) & IP_OFFMASK) == 0) &&
+ 8020bd8:	2b00      	cmp	r3, #0
+ 8020bda:	d006      	beq.n	8020bea <ip4_reass+0x13e>
+      /* ipr->iphdr is not the header from the first fragment, but fraghdr is
+       * -> copy fraghdr into ipr->iphdr since we want to have the header
+       * of the first fragment (for ICMP time exceeded and later, for copying
+       * all options, if supported)*/
+      SMEMCPY(&ipr->iphdr, fraghdr, IP_HLEN);
+ 8020bdc:	6b3b      	ldr	r3, [r7, #48]	; 0x30
+ 8020bde:	3308      	adds	r3, #8
+ 8020be0:	2214      	movs	r2, #20
+ 8020be2:	6ab9      	ldr	r1, [r7, #40]	; 0x28
+ 8020be4:	4618      	mov	r0, r3
+ 8020be6:	f001 f8fe 	bl	8021de6 <memcpy>
+
+  /* At this point, we have either created a new entry or pointing
+   * to an existing one */
+
+  /* check for 'no more fragments', and update queue entry*/
+  is_last = (IPH_OFFSET(fraghdr) & PP_NTOHS(IP_MF)) == 0;
+ 8020bea:	6abb      	ldr	r3, [r7, #40]	; 0x28
+ 8020bec:	88db      	ldrh	r3, [r3, #6]
+ 8020bee:	b29b      	uxth	r3, r3
+ 8020bf0:	f003 0320 	and.w	r3, r3, #32
+ 8020bf4:	2b00      	cmp	r3, #0
+ 8020bf6:	bf0c      	ite	eq
+ 8020bf8:	2301      	moveq	r3, #1
+ 8020bfa:	2300      	movne	r3, #0
+ 8020bfc:	b2db      	uxtb	r3, r3
+ 8020bfe:	61fb      	str	r3, [r7, #28]
+  if (is_last) {
+ 8020c00:	69fb      	ldr	r3, [r7, #28]
+ 8020c02:	2b00      	cmp	r3, #0
+ 8020c04:	d00e      	beq.n	8020c24 <ip4_reass+0x178>
+    u16_t datagram_len = (u16_t)(offset + len);
+ 8020c06:	8cfa      	ldrh	r2, [r7, #38]	; 0x26
+ 8020c08:	8cbb      	ldrh	r3, [r7, #36]	; 0x24
+ 8020c0a:	4413      	add	r3, r2
+ 8020c0c:	837b      	strh	r3, [r7, #26]
+    if ((datagram_len < offset) || (datagram_len > (0xFFFF - IP_HLEN))) {
+ 8020c0e:	8b7a      	ldrh	r2, [r7, #26]
+ 8020c10:	8cfb      	ldrh	r3, [r7, #38]	; 0x26
+ 8020c12:	429a      	cmp	r2, r3
+ 8020c14:	f0c0 80a0 	bcc.w	8020d58 <ip4_reass+0x2ac>
+ 8020c18:	8b7b      	ldrh	r3, [r7, #26]
+ 8020c1a:	f64f 72eb 	movw	r2, #65515	; 0xffeb
+ 8020c1e:	4293      	cmp	r3, r2
+ 8020c20:	f200 809a 	bhi.w	8020d58 <ip4_reass+0x2ac>
+      goto nullreturn_ipr;
+    }
+  }
+  /* find the right place to insert this pbuf */
+  /* @todo: trim pbufs if fragments are overlapping */
+  valid = ip_reass_chain_frag_into_datagram_and_validate(ipr, p, is_last);
+ 8020c24:	69fa      	ldr	r2, [r7, #28]
+ 8020c26:	6879      	ldr	r1, [r7, #4]
+ 8020c28:	6b38      	ldr	r0, [r7, #48]	; 0x30
+ 8020c2a:	f7ff fdd5 	bl	80207d8 <ip_reass_chain_frag_into_datagram_and_validate>
+ 8020c2e:	6178      	str	r0, [r7, #20]
+  if (valid == IP_REASS_VALIDATE_PBUF_DROPPED) {
+ 8020c30:	697b      	ldr	r3, [r7, #20]
+ 8020c32:	f1b3 3fff 	cmp.w	r3, #4294967295
+ 8020c36:	f000 809b 	beq.w	8020d70 <ip4_reass+0x2c4>
+  /* if we come here, the pbuf has been enqueued */
+
+  /* Track the current number of pbufs current 'in-flight', in order to limit
+     the number of fragments that may be enqueued at any one time
+     (overflow checked by testing against IP_REASS_MAX_PBUFS) */
+  ip_reass_pbufcount = (u16_t)(ip_reass_pbufcount + clen);
+ 8020c3a:	4b48      	ldr	r3, [pc, #288]	; (8020d5c <ip4_reass+0x2b0>)
+ 8020c3c:	881a      	ldrh	r2, [r3, #0]
+ 8020c3e:	8c3b      	ldrh	r3, [r7, #32]
+ 8020c40:	4413      	add	r3, r2
+ 8020c42:	b29a      	uxth	r2, r3
+ 8020c44:	4b45      	ldr	r3, [pc, #276]	; (8020d5c <ip4_reass+0x2b0>)
+ 8020c46:	801a      	strh	r2, [r3, #0]
+  if (is_last) {
+ 8020c48:	69fb      	ldr	r3, [r7, #28]
+ 8020c4a:	2b00      	cmp	r3, #0
+ 8020c4c:	d00d      	beq.n	8020c6a <ip4_reass+0x1be>
+    u16_t datagram_len = (u16_t)(offset + len);
+ 8020c4e:	8cfa      	ldrh	r2, [r7, #38]	; 0x26
+ 8020c50:	8cbb      	ldrh	r3, [r7, #36]	; 0x24
+ 8020c52:	4413      	add	r3, r2
+ 8020c54:	827b      	strh	r3, [r7, #18]
+    ipr->datagram_len = datagram_len;
+ 8020c56:	6b3b      	ldr	r3, [r7, #48]	; 0x30
+ 8020c58:	8a7a      	ldrh	r2, [r7, #18]
+ 8020c5a:	839a      	strh	r2, [r3, #28]
+    ipr->flags |= IP_REASS_FLAG_LASTFRAG;
+ 8020c5c:	6b3b      	ldr	r3, [r7, #48]	; 0x30
+ 8020c5e:	7f9b      	ldrb	r3, [r3, #30]
+ 8020c60:	f043 0301 	orr.w	r3, r3, #1
+ 8020c64:	b2da      	uxtb	r2, r3
+ 8020c66:	6b3b      	ldr	r3, [r7, #48]	; 0x30
+ 8020c68:	779a      	strb	r2, [r3, #30]
+    LWIP_DEBUGF(IP_REASS_DEBUG,
+                ("ip4_reass: last fragment seen, total len %"S16_F"\n",
+                 ipr->datagram_len));
+  }
+
+  if (valid == IP_REASS_VALIDATE_TELEGRAM_FINISHED) {
+ 8020c6a:	697b      	ldr	r3, [r7, #20]
+ 8020c6c:	2b01      	cmp	r3, #1
+ 8020c6e:	d171      	bne.n	8020d54 <ip4_reass+0x2a8>
+    struct ip_reassdata *ipr_prev;
+    /* the totally last fragment (flag more fragments = 0) was received at least
+     * once AND all fragments are received */
+    u16_t datagram_len = (u16_t)(ipr->datagram_len + IP_HLEN);
+ 8020c70:	6b3b      	ldr	r3, [r7, #48]	; 0x30
+ 8020c72:	8b9b      	ldrh	r3, [r3, #28]
+ 8020c74:	3314      	adds	r3, #20
+ 8020c76:	823b      	strh	r3, [r7, #16]
+
+    /* save the second pbuf before copying the header over the pointer */
+    r = ((struct ip_reass_helper *)ipr->p->payload)->next_pbuf;
+ 8020c78:	6b3b      	ldr	r3, [r7, #48]	; 0x30
+ 8020c7a:	685b      	ldr	r3, [r3, #4]
+ 8020c7c:	685b      	ldr	r3, [r3, #4]
+ 8020c7e:	681b      	ldr	r3, [r3, #0]
+ 8020c80:	62fb      	str	r3, [r7, #44]	; 0x2c
+
+    /* copy the original ip header back to the first pbuf */
+    fraghdr = (struct ip_hdr *)(ipr->p->payload);
+ 8020c82:	6b3b      	ldr	r3, [r7, #48]	; 0x30
+ 8020c84:	685b      	ldr	r3, [r3, #4]
+ 8020c86:	685b      	ldr	r3, [r3, #4]
+ 8020c88:	62bb      	str	r3, [r7, #40]	; 0x28
+    SMEMCPY(fraghdr, &ipr->iphdr, IP_HLEN);
+ 8020c8a:	6b3b      	ldr	r3, [r7, #48]	; 0x30
+ 8020c8c:	3308      	adds	r3, #8
+ 8020c8e:	2214      	movs	r2, #20
+ 8020c90:	4619      	mov	r1, r3
+ 8020c92:	6ab8      	ldr	r0, [r7, #40]	; 0x28
+ 8020c94:	f001 f8a7 	bl	8021de6 <memcpy>
+    IPH_LEN_SET(fraghdr, lwip_htons(datagram_len));
+ 8020c98:	8a3b      	ldrh	r3, [r7, #16]
+ 8020c9a:	4618      	mov	r0, r3
+ 8020c9c:	f7f5 f950 	bl	8015f40 <lwip_htons>
+ 8020ca0:	4603      	mov	r3, r0
+ 8020ca2:	461a      	mov	r2, r3
+ 8020ca4:	6abb      	ldr	r3, [r7, #40]	; 0x28
+ 8020ca6:	805a      	strh	r2, [r3, #2]
+    IPH_OFFSET_SET(fraghdr, 0);
+ 8020ca8:	6abb      	ldr	r3, [r7, #40]	; 0x28
+ 8020caa:	2200      	movs	r2, #0
+ 8020cac:	719a      	strb	r2, [r3, #6]
+ 8020cae:	2200      	movs	r2, #0
+ 8020cb0:	71da      	strb	r2, [r3, #7]
+    IPH_CHKSUM_SET(fraghdr, 0);
+ 8020cb2:	6abb      	ldr	r3, [r7, #40]	; 0x28
+ 8020cb4:	2200      	movs	r2, #0
+ 8020cb6:	729a      	strb	r2, [r3, #10]
+ 8020cb8:	2200      	movs	r2, #0
+ 8020cba:	72da      	strb	r2, [r3, #11]
+    IF__NETIF_CHECKSUM_ENABLED(ip_current_input_netif(), NETIF_CHECKSUM_GEN_IP) {
+      IPH_CHKSUM_SET(fraghdr, inet_chksum(fraghdr, IP_HLEN));
+    }
+#endif /* CHECKSUM_GEN_IP */
+
+    p = ipr->p;
+ 8020cbc:	6b3b      	ldr	r3, [r7, #48]	; 0x30
+ 8020cbe:	685b      	ldr	r3, [r3, #4]
+ 8020cc0:	607b      	str	r3, [r7, #4]
+
+    /* chain together the pbufs contained within the reass_data list. */
+    while (r != NULL) {
+ 8020cc2:	e00d      	b.n	8020ce0 <ip4_reass+0x234>
+      iprh = (struct ip_reass_helper *)r->payload;
+ 8020cc4:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 8020cc6:	685b      	ldr	r3, [r3, #4]
+ 8020cc8:	60fb      	str	r3, [r7, #12]
+
+      /* hide the ip header for every succeeding fragment */
+      pbuf_remove_header(r, IP_HLEN);
+ 8020cca:	2114      	movs	r1, #20
+ 8020ccc:	6af8      	ldr	r0, [r7, #44]	; 0x2c
+ 8020cce:	f7f6 fe8d 	bl	80179ec <pbuf_remove_header>
+      pbuf_cat(p, r);
+ 8020cd2:	6af9      	ldr	r1, [r7, #44]	; 0x2c
+ 8020cd4:	6878      	ldr	r0, [r7, #4]
+ 8020cd6:	f7f6 ffdd 	bl	8017c94 <pbuf_cat>
+      r = iprh->next_pbuf;
+ 8020cda:	68fb      	ldr	r3, [r7, #12]
+ 8020cdc:	681b      	ldr	r3, [r3, #0]
+ 8020cde:	62fb      	str	r3, [r7, #44]	; 0x2c
+    while (r != NULL) {
+ 8020ce0:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 8020ce2:	2b00      	cmp	r3, #0
+ 8020ce4:	d1ee      	bne.n	8020cc4 <ip4_reass+0x218>
+    }
+
+    /* find the previous entry in the linked list */
+    if (ipr == reassdatagrams) {
+ 8020ce6:	4b1e      	ldr	r3, [pc, #120]	; (8020d60 <ip4_reass+0x2b4>)
+ 8020ce8:	681b      	ldr	r3, [r3, #0]
+ 8020cea:	6b3a      	ldr	r2, [r7, #48]	; 0x30
+ 8020cec:	429a      	cmp	r2, r3
+ 8020cee:	d102      	bne.n	8020cf6 <ip4_reass+0x24a>
+      ipr_prev = NULL;
+ 8020cf0:	2300      	movs	r3, #0
+ 8020cf2:	637b      	str	r3, [r7, #52]	; 0x34
+ 8020cf4:	e010      	b.n	8020d18 <ip4_reass+0x26c>
+    } else {
+      for (ipr_prev = reassdatagrams; ipr_prev != NULL; ipr_prev = ipr_prev->next) {
+ 8020cf6:	4b1a      	ldr	r3, [pc, #104]	; (8020d60 <ip4_reass+0x2b4>)
+ 8020cf8:	681b      	ldr	r3, [r3, #0]
+ 8020cfa:	637b      	str	r3, [r7, #52]	; 0x34
+ 8020cfc:	e007      	b.n	8020d0e <ip4_reass+0x262>
+        if (ipr_prev->next == ipr) {
+ 8020cfe:	6b7b      	ldr	r3, [r7, #52]	; 0x34
+ 8020d00:	681b      	ldr	r3, [r3, #0]
+ 8020d02:	6b3a      	ldr	r2, [r7, #48]	; 0x30
+ 8020d04:	429a      	cmp	r2, r3
+ 8020d06:	d006      	beq.n	8020d16 <ip4_reass+0x26a>
+      for (ipr_prev = reassdatagrams; ipr_prev != NULL; ipr_prev = ipr_prev->next) {
+ 8020d08:	6b7b      	ldr	r3, [r7, #52]	; 0x34
+ 8020d0a:	681b      	ldr	r3, [r3, #0]
+ 8020d0c:	637b      	str	r3, [r7, #52]	; 0x34
+ 8020d0e:	6b7b      	ldr	r3, [r7, #52]	; 0x34
+ 8020d10:	2b00      	cmp	r3, #0
+ 8020d12:	d1f4      	bne.n	8020cfe <ip4_reass+0x252>
+ 8020d14:	e000      	b.n	8020d18 <ip4_reass+0x26c>
+          break;
+ 8020d16:	bf00      	nop
+        }
+      }
+    }
+
+    /* release the sources allocate for the fragment queue entry */
+    ip_reass_dequeue_datagram(ipr, ipr_prev);
+ 8020d18:	6b79      	ldr	r1, [r7, #52]	; 0x34
+ 8020d1a:	6b38      	ldr	r0, [r7, #48]	; 0x30
+ 8020d1c:	f7ff fd2e 	bl	802077c <ip_reass_dequeue_datagram>
+
+    /* and adjust the number of pbufs currently queued for reassembly. */
+    clen = pbuf_clen(p);
+ 8020d20:	6878      	ldr	r0, [r7, #4]
+ 8020d22:	f7f6 ff77 	bl	8017c14 <pbuf_clen>
+ 8020d26:	4603      	mov	r3, r0
+ 8020d28:	843b      	strh	r3, [r7, #32]
+    LWIP_ASSERT("ip_reass_pbufcount >= clen", ip_reass_pbufcount >= clen);
+ 8020d2a:	4b0c      	ldr	r3, [pc, #48]	; (8020d5c <ip4_reass+0x2b0>)
+ 8020d2c:	881b      	ldrh	r3, [r3, #0]
+ 8020d2e:	8c3a      	ldrh	r2, [r7, #32]
+ 8020d30:	429a      	cmp	r2, r3
+ 8020d32:	d906      	bls.n	8020d42 <ip4_reass+0x296>
+ 8020d34:	4b0b      	ldr	r3, [pc, #44]	; (8020d64 <ip4_reass+0x2b8>)
+ 8020d36:	f240 229b 	movw	r2, #667	; 0x29b
+ 8020d3a:	490b      	ldr	r1, [pc, #44]	; (8020d68 <ip4_reass+0x2bc>)
+ 8020d3c:	480b      	ldr	r0, [pc, #44]	; (8020d6c <ip4_reass+0x2c0>)
+ 8020d3e:	f000 fe23 	bl	8021988 <iprintf>
+    ip_reass_pbufcount = (u16_t)(ip_reass_pbufcount - clen);
+ 8020d42:	4b06      	ldr	r3, [pc, #24]	; (8020d5c <ip4_reass+0x2b0>)
+ 8020d44:	881a      	ldrh	r2, [r3, #0]
+ 8020d46:	8c3b      	ldrh	r3, [r7, #32]
+ 8020d48:	1ad3      	subs	r3, r2, r3
+ 8020d4a:	b29a      	uxth	r2, r3
+ 8020d4c:	4b03      	ldr	r3, [pc, #12]	; (8020d5c <ip4_reass+0x2b0>)
+ 8020d4e:	801a      	strh	r2, [r3, #0]
+
+    MIB2_STATS_INC(mib2.ipreasmoks);
+
+    /* Return the pbuf chain */
+    return p;
+ 8020d50:	687b      	ldr	r3, [r7, #4]
+ 8020d52:	e038      	b.n	8020dc6 <ip4_reass+0x31a>
+  }
+  /* the datagram is not (yet?) reassembled completely */
+  LWIP_DEBUGF(IP_REASS_DEBUG, ("ip_reass_pbufcount: %d out\n", ip_reass_pbufcount));
+  return NULL;
+ 8020d54:	2300      	movs	r3, #0
+ 8020d56:	e036      	b.n	8020dc6 <ip4_reass+0x31a>
+      goto nullreturn_ipr;
+ 8020d58:	bf00      	nop
+ 8020d5a:	e00a      	b.n	8020d72 <ip4_reass+0x2c6>
+ 8020d5c:	2401a5dc 	.word	0x2401a5dc
+ 8020d60:	2401a5d8 	.word	0x2401a5d8
+ 8020d64:	08026884 	.word	0x08026884
+ 8020d68:	080269f4 	.word	0x080269f4
+ 8020d6c:	080268cc 	.word	0x080268cc
+    goto nullreturn_ipr;
+ 8020d70:	bf00      	nop
+
+nullreturn_ipr:
+  LWIP_ASSERT("ipr != NULL", ipr != NULL);
+ 8020d72:	6b3b      	ldr	r3, [r7, #48]	; 0x30
+ 8020d74:	2b00      	cmp	r3, #0
+ 8020d76:	d106      	bne.n	8020d86 <ip4_reass+0x2da>
+ 8020d78:	4b15      	ldr	r3, [pc, #84]	; (8020dd0 <ip4_reass+0x324>)
+ 8020d7a:	f44f 722a 	mov.w	r2, #680	; 0x2a8
+ 8020d7e:	4915      	ldr	r1, [pc, #84]	; (8020dd4 <ip4_reass+0x328>)
+ 8020d80:	4815      	ldr	r0, [pc, #84]	; (8020dd8 <ip4_reass+0x32c>)
+ 8020d82:	f000 fe01 	bl	8021988 <iprintf>
+  if (ipr->p == NULL) {
+ 8020d86:	6b3b      	ldr	r3, [r7, #48]	; 0x30
+ 8020d88:	685b      	ldr	r3, [r3, #4]
+ 8020d8a:	2b00      	cmp	r3, #0
+ 8020d8c:	d116      	bne.n	8020dbc <ip4_reass+0x310>
+    /* dropped pbuf after creating a new datagram entry: remove the entry, too */
+    LWIP_ASSERT("not firstalthough just enqueued", ipr == reassdatagrams);
+ 8020d8e:	4b13      	ldr	r3, [pc, #76]	; (8020ddc <ip4_reass+0x330>)
+ 8020d90:	681b      	ldr	r3, [r3, #0]
+ 8020d92:	6b3a      	ldr	r2, [r7, #48]	; 0x30
+ 8020d94:	429a      	cmp	r2, r3
+ 8020d96:	d006      	beq.n	8020da6 <ip4_reass+0x2fa>
+ 8020d98:	4b0d      	ldr	r3, [pc, #52]	; (8020dd0 <ip4_reass+0x324>)
+ 8020d9a:	f240 22ab 	movw	r2, #683	; 0x2ab
+ 8020d9e:	4910      	ldr	r1, [pc, #64]	; (8020de0 <ip4_reass+0x334>)
+ 8020da0:	480d      	ldr	r0, [pc, #52]	; (8020dd8 <ip4_reass+0x32c>)
+ 8020da2:	f000 fdf1 	bl	8021988 <iprintf>
+    ip_reass_dequeue_datagram(ipr, NULL);
+ 8020da6:	2100      	movs	r1, #0
+ 8020da8:	6b38      	ldr	r0, [r7, #48]	; 0x30
+ 8020daa:	f7ff fce7 	bl	802077c <ip_reass_dequeue_datagram>
+ 8020dae:	e006      	b.n	8020dbe <ip4_reass+0x312>
+    goto nullreturn;
+ 8020db0:	bf00      	nop
+ 8020db2:	e004      	b.n	8020dbe <ip4_reass+0x312>
+    goto nullreturn;
+ 8020db4:	bf00      	nop
+ 8020db6:	e002      	b.n	8020dbe <ip4_reass+0x312>
+      goto nullreturn;
+ 8020db8:	bf00      	nop
+ 8020dba:	e000      	b.n	8020dbe <ip4_reass+0x312>
+  }
+
+nullreturn:
+ 8020dbc:	bf00      	nop
+  LWIP_DEBUGF(IP_REASS_DEBUG, ("ip4_reass: nullreturn\n"));
+  IPFRAG_STATS_INC(ip_frag.drop);
+  pbuf_free(p);
+ 8020dbe:	6878      	ldr	r0, [r7, #4]
+ 8020dc0:	f7f6 fe9a 	bl	8017af8 <pbuf_free>
+  return NULL;
+ 8020dc4:	2300      	movs	r3, #0
+}
+ 8020dc6:	4618      	mov	r0, r3
+ 8020dc8:	3738      	adds	r7, #56	; 0x38
+ 8020dca:	46bd      	mov	sp, r7
+ 8020dcc:	bd80      	pop	{r7, pc}
+ 8020dce:	bf00      	nop
+ 8020dd0:	08026884 	.word	0x08026884
+ 8020dd4:	08026a10 	.word	0x08026a10
+ 8020dd8:	080268cc 	.word	0x080268cc
+ 8020ddc:	2401a5d8 	.word	0x2401a5d8
+ 8020de0:	08026a1c 	.word	0x08026a1c
+
+08020de4 <ip_frag_alloc_pbuf_custom_ref>:
+#if IP_FRAG
+#if !LWIP_NETIF_TX_SINGLE_PBUF
+/** Allocate a new struct pbuf_custom_ref */
+static struct pbuf_custom_ref *
+ip_frag_alloc_pbuf_custom_ref(void)
+{
+ 8020de4:	b580      	push	{r7, lr}
+ 8020de6:	af00      	add	r7, sp, #0
+  return (struct pbuf_custom_ref *)memp_malloc(MEMP_FRAG_PBUF);
+ 8020de8:	2005      	movs	r0, #5
+ 8020dea:	f7f5 fe71 	bl	8016ad0 <memp_malloc>
+ 8020dee:	4603      	mov	r3, r0
+}
+ 8020df0:	4618      	mov	r0, r3
+ 8020df2:	bd80      	pop	{r7, pc}
+
+08020df4 <ip_frag_free_pbuf_custom_ref>:
+
+/** Free a struct pbuf_custom_ref */
+static void
+ip_frag_free_pbuf_custom_ref(struct pbuf_custom_ref *p)
+{
+ 8020df4:	b580      	push	{r7, lr}
+ 8020df6:	b082      	sub	sp, #8
+ 8020df8:	af00      	add	r7, sp, #0
+ 8020dfa:	6078      	str	r0, [r7, #4]
+  LWIP_ASSERT("p != NULL", p != NULL);
+ 8020dfc:	687b      	ldr	r3, [r7, #4]
+ 8020dfe:	2b00      	cmp	r3, #0
+ 8020e00:	d106      	bne.n	8020e10 <ip_frag_free_pbuf_custom_ref+0x1c>
+ 8020e02:	4b07      	ldr	r3, [pc, #28]	; (8020e20 <ip_frag_free_pbuf_custom_ref+0x2c>)
+ 8020e04:	f44f 7231 	mov.w	r2, #708	; 0x2c4
+ 8020e08:	4906      	ldr	r1, [pc, #24]	; (8020e24 <ip_frag_free_pbuf_custom_ref+0x30>)
+ 8020e0a:	4807      	ldr	r0, [pc, #28]	; (8020e28 <ip_frag_free_pbuf_custom_ref+0x34>)
+ 8020e0c:	f000 fdbc 	bl	8021988 <iprintf>
+  memp_free(MEMP_FRAG_PBUF, p);
+ 8020e10:	6879      	ldr	r1, [r7, #4]
+ 8020e12:	2005      	movs	r0, #5
+ 8020e14:	f7f5 fed2 	bl	8016bbc <memp_free>
+}
+ 8020e18:	bf00      	nop
+ 8020e1a:	3708      	adds	r7, #8
+ 8020e1c:	46bd      	mov	sp, r7
+ 8020e1e:	bd80      	pop	{r7, pc}
+ 8020e20:	08026884 	.word	0x08026884
+ 8020e24:	08026a3c 	.word	0x08026a3c
+ 8020e28:	080268cc 	.word	0x080268cc
+
+08020e2c <ipfrag_free_pbuf_custom>:
+
+/** Free-callback function to free a 'struct pbuf_custom_ref', called by
+ * pbuf_free. */
+static void
+ipfrag_free_pbuf_custom(struct pbuf *p)
+{
+ 8020e2c:	b580      	push	{r7, lr}
+ 8020e2e:	b084      	sub	sp, #16
+ 8020e30:	af00      	add	r7, sp, #0
+ 8020e32:	6078      	str	r0, [r7, #4]
+  struct pbuf_custom_ref *pcr = (struct pbuf_custom_ref *)p;
+ 8020e34:	687b      	ldr	r3, [r7, #4]
+ 8020e36:	60fb      	str	r3, [r7, #12]
+  LWIP_ASSERT("pcr != NULL", pcr != NULL);
+ 8020e38:	68fb      	ldr	r3, [r7, #12]
+ 8020e3a:	2b00      	cmp	r3, #0
+ 8020e3c:	d106      	bne.n	8020e4c <ipfrag_free_pbuf_custom+0x20>
+ 8020e3e:	4b11      	ldr	r3, [pc, #68]	; (8020e84 <ipfrag_free_pbuf_custom+0x58>)
+ 8020e40:	f240 22ce 	movw	r2, #718	; 0x2ce
+ 8020e44:	4910      	ldr	r1, [pc, #64]	; (8020e88 <ipfrag_free_pbuf_custom+0x5c>)
+ 8020e46:	4811      	ldr	r0, [pc, #68]	; (8020e8c <ipfrag_free_pbuf_custom+0x60>)
+ 8020e48:	f000 fd9e 	bl	8021988 <iprintf>
+  LWIP_ASSERT("pcr == p", (void *)pcr == (void *)p);
+ 8020e4c:	68fa      	ldr	r2, [r7, #12]
+ 8020e4e:	687b      	ldr	r3, [r7, #4]
+ 8020e50:	429a      	cmp	r2, r3
+ 8020e52:	d006      	beq.n	8020e62 <ipfrag_free_pbuf_custom+0x36>
+ 8020e54:	4b0b      	ldr	r3, [pc, #44]	; (8020e84 <ipfrag_free_pbuf_custom+0x58>)
+ 8020e56:	f240 22cf 	movw	r2, #719	; 0x2cf
+ 8020e5a:	490d      	ldr	r1, [pc, #52]	; (8020e90 <ipfrag_free_pbuf_custom+0x64>)
+ 8020e5c:	480b      	ldr	r0, [pc, #44]	; (8020e8c <ipfrag_free_pbuf_custom+0x60>)
+ 8020e5e:	f000 fd93 	bl	8021988 <iprintf>
+  if (pcr->original != NULL) {
+ 8020e62:	68fb      	ldr	r3, [r7, #12]
+ 8020e64:	695b      	ldr	r3, [r3, #20]
+ 8020e66:	2b00      	cmp	r3, #0
+ 8020e68:	d004      	beq.n	8020e74 <ipfrag_free_pbuf_custom+0x48>
+    pbuf_free(pcr->original);
+ 8020e6a:	68fb      	ldr	r3, [r7, #12]
+ 8020e6c:	695b      	ldr	r3, [r3, #20]
+ 8020e6e:	4618      	mov	r0, r3
+ 8020e70:	f7f6 fe42 	bl	8017af8 <pbuf_free>
+  }
+  ip_frag_free_pbuf_custom_ref(pcr);
+ 8020e74:	68f8      	ldr	r0, [r7, #12]
+ 8020e76:	f7ff ffbd 	bl	8020df4 <ip_frag_free_pbuf_custom_ref>
+}
+ 8020e7a:	bf00      	nop
+ 8020e7c:	3710      	adds	r7, #16
+ 8020e7e:	46bd      	mov	sp, r7
+ 8020e80:	bd80      	pop	{r7, pc}
+ 8020e82:	bf00      	nop
+ 8020e84:	08026884 	.word	0x08026884
+ 8020e88:	08026a48 	.word	0x08026a48
+ 8020e8c:	080268cc 	.word	0x080268cc
+ 8020e90:	08026a54 	.word	0x08026a54
+
+08020e94 <ip4_frag>:
+ *
+ * @return ERR_OK if sent successfully, err_t otherwise
+ */
+err_t
+ip4_frag(struct pbuf *p, struct netif *netif, const ip4_addr_t *dest)
+{
+ 8020e94:	b580      	push	{r7, lr}
+ 8020e96:	b094      	sub	sp, #80	; 0x50
+ 8020e98:	af02      	add	r7, sp, #8
+ 8020e9a:	60f8      	str	r0, [r7, #12]
+ 8020e9c:	60b9      	str	r1, [r7, #8]
+ 8020e9e:	607a      	str	r2, [r7, #4]
+  struct pbuf *rambuf;
+#if !LWIP_NETIF_TX_SINGLE_PBUF
+  struct pbuf *newpbuf;
+  u16_t newpbuflen = 0;
+ 8020ea0:	2300      	movs	r3, #0
+ 8020ea2:	f8a7 3046 	strh.w	r3, [r7, #70]	; 0x46
+  u16_t left_to_copy;
+#endif
+  struct ip_hdr *original_iphdr;
+  struct ip_hdr *iphdr;
+  const u16_t nfb = (u16_t)((netif->mtu - IP_HLEN) / 8);
+ 8020ea6:	68bb      	ldr	r3, [r7, #8]
+ 8020ea8:	8c9b      	ldrh	r3, [r3, #36]	; 0x24
+ 8020eaa:	3b14      	subs	r3, #20
+ 8020eac:	2b00      	cmp	r3, #0
+ 8020eae:	da00      	bge.n	8020eb2 <ip4_frag+0x1e>
+ 8020eb0:	3307      	adds	r3, #7
+ 8020eb2:	10db      	asrs	r3, r3, #3
+ 8020eb4:	877b      	strh	r3, [r7, #58]	; 0x3a
+  u16_t left, fragsize;
+  u16_t ofo;
+  int last;
+  u16_t poff = IP_HLEN;
+ 8020eb6:	2314      	movs	r3, #20
+ 8020eb8:	87fb      	strh	r3, [r7, #62]	; 0x3e
+  u16_t tmp;
+  int mf_set;
+
+  original_iphdr = (struct ip_hdr *)p->payload;
+ 8020eba:	68fb      	ldr	r3, [r7, #12]
+ 8020ebc:	685b      	ldr	r3, [r3, #4]
+ 8020ebe:	637b      	str	r3, [r7, #52]	; 0x34
+  iphdr = original_iphdr;
+ 8020ec0:	6b7b      	ldr	r3, [r7, #52]	; 0x34
+ 8020ec2:	633b      	str	r3, [r7, #48]	; 0x30
+  if (IPH_HL_BYTES(iphdr) != IP_HLEN) {
+ 8020ec4:	6b3b      	ldr	r3, [r7, #48]	; 0x30
+ 8020ec6:	781b      	ldrb	r3, [r3, #0]
+ 8020ec8:	f003 030f 	and.w	r3, r3, #15
+ 8020ecc:	b2db      	uxtb	r3, r3
+ 8020ece:	009b      	lsls	r3, r3, #2
+ 8020ed0:	b2db      	uxtb	r3, r3
+ 8020ed2:	2b14      	cmp	r3, #20
+ 8020ed4:	d002      	beq.n	8020edc <ip4_frag+0x48>
+    /* ip4_frag() does not support IP options */
+    return ERR_VAL;
+ 8020ed6:	f06f 0305 	mvn.w	r3, #5
+ 8020eda:	e110      	b.n	80210fe <ip4_frag+0x26a>
+  }
+  LWIP_ERROR("ip4_frag(): pbuf too short", p->len >= IP_HLEN, return ERR_VAL);
+ 8020edc:	68fb      	ldr	r3, [r7, #12]
+ 8020ede:	895b      	ldrh	r3, [r3, #10]
+ 8020ee0:	2b13      	cmp	r3, #19
+ 8020ee2:	d809      	bhi.n	8020ef8 <ip4_frag+0x64>
+ 8020ee4:	4b88      	ldr	r3, [pc, #544]	; (8021108 <ip4_frag+0x274>)
+ 8020ee6:	f44f 723f 	mov.w	r2, #764	; 0x2fc
+ 8020eea:	4988      	ldr	r1, [pc, #544]	; (802110c <ip4_frag+0x278>)
+ 8020eec:	4888      	ldr	r0, [pc, #544]	; (8021110 <ip4_frag+0x27c>)
+ 8020eee:	f000 fd4b 	bl	8021988 <iprintf>
+ 8020ef2:	f06f 0305 	mvn.w	r3, #5
+ 8020ef6:	e102      	b.n	80210fe <ip4_frag+0x26a>
+
+  /* Save original offset */
+  tmp = lwip_ntohs(IPH_OFFSET(iphdr));
+ 8020ef8:	6b3b      	ldr	r3, [r7, #48]	; 0x30
+ 8020efa:	88db      	ldrh	r3, [r3, #6]
+ 8020efc:	b29b      	uxth	r3, r3
+ 8020efe:	4618      	mov	r0, r3
+ 8020f00:	f7f5 f81e 	bl	8015f40 <lwip_htons>
+ 8020f04:	4603      	mov	r3, r0
+ 8020f06:	87bb      	strh	r3, [r7, #60]	; 0x3c
+  ofo = tmp & IP_OFFMASK;
+ 8020f08:	8fbb      	ldrh	r3, [r7, #60]	; 0x3c
+ 8020f0a:	f3c3 030c 	ubfx	r3, r3, #0, #13
+ 8020f0e:	f8a7 3040 	strh.w	r3, [r7, #64]	; 0x40
+  /* already fragmented? if so, the last fragment we create must have MF, too */
+  mf_set = tmp & IP_MF;
+ 8020f12:	8fbb      	ldrh	r3, [r7, #60]	; 0x3c
+ 8020f14:	f403 5300 	and.w	r3, r3, #8192	; 0x2000
+ 8020f18:	62fb      	str	r3, [r7, #44]	; 0x2c
+
+  left = (u16_t)(p->tot_len - IP_HLEN);
+ 8020f1a:	68fb      	ldr	r3, [r7, #12]
+ 8020f1c:	891b      	ldrh	r3, [r3, #8]
+ 8020f1e:	3b14      	subs	r3, #20
+ 8020f20:	f8a7 3042 	strh.w	r3, [r7, #66]	; 0x42
+
+  while (left) {
+ 8020f24:	e0e1      	b.n	80210ea <ip4_frag+0x256>
+    /* Fill this fragment */
+    fragsize = LWIP_MIN(left, (u16_t)(nfb * 8));
+ 8020f26:	8f7b      	ldrh	r3, [r7, #58]	; 0x3a
+ 8020f28:	00db      	lsls	r3, r3, #3
+ 8020f2a:	b29b      	uxth	r3, r3
+ 8020f2c:	f8b7 2042 	ldrh.w	r2, [r7, #66]	; 0x42
+ 8020f30:	4293      	cmp	r3, r2
+ 8020f32:	bf28      	it	cs
+ 8020f34:	4613      	movcs	r3, r2
+ 8020f36:	857b      	strh	r3, [r7, #42]	; 0x2a
+    /* When not using a static buffer, create a chain of pbufs.
+     * The first will be a PBUF_RAM holding the link and IP header.
+     * The rest will be PBUF_REFs mirroring the pbuf chain to be fragged,
+     * but limited to the size of an mtu.
+     */
+    rambuf = pbuf_alloc(PBUF_LINK, IP_HLEN, PBUF_RAM);
+ 8020f38:	f44f 7220 	mov.w	r2, #640	; 0x280
+ 8020f3c:	2114      	movs	r1, #20
+ 8020f3e:	200e      	movs	r0, #14
+ 8020f40:	f7f6 faf2 	bl	8017528 <pbuf_alloc>
+ 8020f44:	6278      	str	r0, [r7, #36]	; 0x24
+    if (rambuf == NULL) {
+ 8020f46:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 8020f48:	2b00      	cmp	r3, #0
+ 8020f4a:	f000 80d5 	beq.w	80210f8 <ip4_frag+0x264>
+      goto memerr;
+    }
+    LWIP_ASSERT("this needs a pbuf in one piece!",
+ 8020f4e:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 8020f50:	895b      	ldrh	r3, [r3, #10]
+ 8020f52:	2b13      	cmp	r3, #19
+ 8020f54:	d806      	bhi.n	8020f64 <ip4_frag+0xd0>
+ 8020f56:	4b6c      	ldr	r3, [pc, #432]	; (8021108 <ip4_frag+0x274>)
+ 8020f58:	f44f 7249 	mov.w	r2, #804	; 0x324
+ 8020f5c:	496d      	ldr	r1, [pc, #436]	; (8021114 <ip4_frag+0x280>)
+ 8020f5e:	486c      	ldr	r0, [pc, #432]	; (8021110 <ip4_frag+0x27c>)
+ 8020f60:	f000 fd12 	bl	8021988 <iprintf>
+                (rambuf->len >= (IP_HLEN)));
+    SMEMCPY(rambuf->payload, original_iphdr, IP_HLEN);
+ 8020f64:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 8020f66:	685b      	ldr	r3, [r3, #4]
+ 8020f68:	2214      	movs	r2, #20
+ 8020f6a:	6b79      	ldr	r1, [r7, #52]	; 0x34
+ 8020f6c:	4618      	mov	r0, r3
+ 8020f6e:	f000 ff3a 	bl	8021de6 <memcpy>
+    iphdr = (struct ip_hdr *)rambuf->payload;
+ 8020f72:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 8020f74:	685b      	ldr	r3, [r3, #4]
+ 8020f76:	633b      	str	r3, [r7, #48]	; 0x30
+
+    left_to_copy = fragsize;
+ 8020f78:	8d7b      	ldrh	r3, [r7, #42]	; 0x2a
+ 8020f7a:	f8a7 3044 	strh.w	r3, [r7, #68]	; 0x44
+    while (left_to_copy) {
+ 8020f7e:	e064      	b.n	802104a <ip4_frag+0x1b6>
+      struct pbuf_custom_ref *pcr;
+      u16_t plen = (u16_t)(p->len - poff);
+ 8020f80:	68fb      	ldr	r3, [r7, #12]
+ 8020f82:	895a      	ldrh	r2, [r3, #10]
+ 8020f84:	8ffb      	ldrh	r3, [r7, #62]	; 0x3e
+ 8020f86:	1ad3      	subs	r3, r2, r3
+ 8020f88:	83fb      	strh	r3, [r7, #30]
+      LWIP_ASSERT("p->len >= poff", p->len >= poff);
+ 8020f8a:	68fb      	ldr	r3, [r7, #12]
+ 8020f8c:	895b      	ldrh	r3, [r3, #10]
+ 8020f8e:	8ffa      	ldrh	r2, [r7, #62]	; 0x3e
+ 8020f90:	429a      	cmp	r2, r3
+ 8020f92:	d906      	bls.n	8020fa2 <ip4_frag+0x10e>
+ 8020f94:	4b5c      	ldr	r3, [pc, #368]	; (8021108 <ip4_frag+0x274>)
+ 8020f96:	f240 322d 	movw	r2, #813	; 0x32d
+ 8020f9a:	495f      	ldr	r1, [pc, #380]	; (8021118 <ip4_frag+0x284>)
+ 8020f9c:	485c      	ldr	r0, [pc, #368]	; (8021110 <ip4_frag+0x27c>)
+ 8020f9e:	f000 fcf3 	bl	8021988 <iprintf>
+      newpbuflen = LWIP_MIN(left_to_copy, plen);
+ 8020fa2:	8bfa      	ldrh	r2, [r7, #30]
+ 8020fa4:	f8b7 3044 	ldrh.w	r3, [r7, #68]	; 0x44
+ 8020fa8:	4293      	cmp	r3, r2
+ 8020faa:	bf28      	it	cs
+ 8020fac:	4613      	movcs	r3, r2
+ 8020fae:	f8a7 3046 	strh.w	r3, [r7, #70]	; 0x46
+      /* Is this pbuf already empty? */
+      if (!newpbuflen) {
+ 8020fb2:	f8b7 3046 	ldrh.w	r3, [r7, #70]	; 0x46
+ 8020fb6:	2b00      	cmp	r3, #0
+ 8020fb8:	d105      	bne.n	8020fc6 <ip4_frag+0x132>
+        poff = 0;
+ 8020fba:	2300      	movs	r3, #0
+ 8020fbc:	87fb      	strh	r3, [r7, #62]	; 0x3e
+        p = p->next;
+ 8020fbe:	68fb      	ldr	r3, [r7, #12]
+ 8020fc0:	681b      	ldr	r3, [r3, #0]
+ 8020fc2:	60fb      	str	r3, [r7, #12]
+        continue;
+ 8020fc4:	e041      	b.n	802104a <ip4_frag+0x1b6>
+      }
+      pcr = ip_frag_alloc_pbuf_custom_ref();
+ 8020fc6:	f7ff ff0d 	bl	8020de4 <ip_frag_alloc_pbuf_custom_ref>
+ 8020fca:	61b8      	str	r0, [r7, #24]
+      if (pcr == NULL) {
+ 8020fcc:	69bb      	ldr	r3, [r7, #24]
+ 8020fce:	2b00      	cmp	r3, #0
+ 8020fd0:	d103      	bne.n	8020fda <ip4_frag+0x146>
+        pbuf_free(rambuf);
+ 8020fd2:	6a78      	ldr	r0, [r7, #36]	; 0x24
+ 8020fd4:	f7f6 fd90 	bl	8017af8 <pbuf_free>
+        goto memerr;
+ 8020fd8:	e08f      	b.n	80210fa <ip4_frag+0x266>
+      }
+      /* Mirror this pbuf, although we might not need all of it. */
+      newpbuf = pbuf_alloced_custom(PBUF_RAW, newpbuflen, PBUF_REF, &pcr->pc,
+ 8020fda:	69b8      	ldr	r0, [r7, #24]
+                                    (u8_t *)p->payload + poff, newpbuflen);
+ 8020fdc:	68fb      	ldr	r3, [r7, #12]
+ 8020fde:	685a      	ldr	r2, [r3, #4]
+      newpbuf = pbuf_alloced_custom(PBUF_RAW, newpbuflen, PBUF_REF, &pcr->pc,
+ 8020fe0:	8ffb      	ldrh	r3, [r7, #62]	; 0x3e
+ 8020fe2:	4413      	add	r3, r2
+ 8020fe4:	f8b7 1046 	ldrh.w	r1, [r7, #70]	; 0x46
+ 8020fe8:	f8b7 2046 	ldrh.w	r2, [r7, #70]	; 0x46
+ 8020fec:	9201      	str	r2, [sp, #4]
+ 8020fee:	9300      	str	r3, [sp, #0]
+ 8020ff0:	4603      	mov	r3, r0
+ 8020ff2:	2241      	movs	r2, #65	; 0x41
+ 8020ff4:	2000      	movs	r0, #0
+ 8020ff6:	f7f6 fbc5 	bl	8017784 <pbuf_alloced_custom>
+ 8020ffa:	6178      	str	r0, [r7, #20]
+      if (newpbuf == NULL) {
+ 8020ffc:	697b      	ldr	r3, [r7, #20]
+ 8020ffe:	2b00      	cmp	r3, #0
+ 8021000:	d106      	bne.n	8021010 <ip4_frag+0x17c>
+        ip_frag_free_pbuf_custom_ref(pcr);
+ 8021002:	69b8      	ldr	r0, [r7, #24]
+ 8021004:	f7ff fef6 	bl	8020df4 <ip_frag_free_pbuf_custom_ref>
+        pbuf_free(rambuf);
+ 8021008:	6a78      	ldr	r0, [r7, #36]	; 0x24
+ 802100a:	f7f6 fd75 	bl	8017af8 <pbuf_free>
+        goto memerr;
+ 802100e:	e074      	b.n	80210fa <ip4_frag+0x266>
+      }
+      pbuf_ref(p);
+ 8021010:	68f8      	ldr	r0, [r7, #12]
+ 8021012:	f7f6 fe17 	bl	8017c44 <pbuf_ref>
+      pcr->original = p;
+ 8021016:	69bb      	ldr	r3, [r7, #24]
+ 8021018:	68fa      	ldr	r2, [r7, #12]
+ 802101a:	615a      	str	r2, [r3, #20]
+      pcr->pc.custom_free_function = ipfrag_free_pbuf_custom;
+ 802101c:	69bb      	ldr	r3, [r7, #24]
+ 802101e:	4a3f      	ldr	r2, [pc, #252]	; (802111c <ip4_frag+0x288>)
+ 8021020:	611a      	str	r2, [r3, #16]
+
+      /* Add it to end of rambuf's chain, but using pbuf_cat, not pbuf_chain
+       * so that it is removed when pbuf_dechain is later called on rambuf.
+       */
+      pbuf_cat(rambuf, newpbuf);
+ 8021022:	6979      	ldr	r1, [r7, #20]
+ 8021024:	6a78      	ldr	r0, [r7, #36]	; 0x24
+ 8021026:	f7f6 fe35 	bl	8017c94 <pbuf_cat>
+      left_to_copy = (u16_t)(left_to_copy - newpbuflen);
+ 802102a:	f8b7 2044 	ldrh.w	r2, [r7, #68]	; 0x44
+ 802102e:	f8b7 3046 	ldrh.w	r3, [r7, #70]	; 0x46
+ 8021032:	1ad3      	subs	r3, r2, r3
+ 8021034:	f8a7 3044 	strh.w	r3, [r7, #68]	; 0x44
+      if (left_to_copy) {
+ 8021038:	f8b7 3044 	ldrh.w	r3, [r7, #68]	; 0x44
+ 802103c:	2b00      	cmp	r3, #0
+ 802103e:	d004      	beq.n	802104a <ip4_frag+0x1b6>
+        poff = 0;
+ 8021040:	2300      	movs	r3, #0
+ 8021042:	87fb      	strh	r3, [r7, #62]	; 0x3e
+        p = p->next;
+ 8021044:	68fb      	ldr	r3, [r7, #12]
+ 8021046:	681b      	ldr	r3, [r3, #0]
+ 8021048:	60fb      	str	r3, [r7, #12]
+    while (left_to_copy) {
+ 802104a:	f8b7 3044 	ldrh.w	r3, [r7, #68]	; 0x44
+ 802104e:	2b00      	cmp	r3, #0
+ 8021050:	d196      	bne.n	8020f80 <ip4_frag+0xec>
+      }
+    }
+    poff = (u16_t)(poff + newpbuflen);
+ 8021052:	8ffa      	ldrh	r2, [r7, #62]	; 0x3e
+ 8021054:	f8b7 3046 	ldrh.w	r3, [r7, #70]	; 0x46
+ 8021058:	4413      	add	r3, r2
+ 802105a:	87fb      	strh	r3, [r7, #62]	; 0x3e
+#endif /* LWIP_NETIF_TX_SINGLE_PBUF */
+
+    /* Correct header */
+    last = (left <= netif->mtu - IP_HLEN);
+ 802105c:	68bb      	ldr	r3, [r7, #8]
+ 802105e:	8c9b      	ldrh	r3, [r3, #36]	; 0x24
+ 8021060:	f1a3 0213 	sub.w	r2, r3, #19
+ 8021064:	f8b7 3042 	ldrh.w	r3, [r7, #66]	; 0x42
+ 8021068:	429a      	cmp	r2, r3
+ 802106a:	bfcc      	ite	gt
+ 802106c:	2301      	movgt	r3, #1
+ 802106e:	2300      	movle	r3, #0
+ 8021070:	b2db      	uxtb	r3, r3
+ 8021072:	623b      	str	r3, [r7, #32]
+
+    /* Set new offset and MF flag */
+    tmp = (IP_OFFMASK & (ofo));
+ 8021074:	f8b7 3040 	ldrh.w	r3, [r7, #64]	; 0x40
+ 8021078:	f3c3 030c 	ubfx	r3, r3, #0, #13
+ 802107c:	87bb      	strh	r3, [r7, #60]	; 0x3c
+    if (!last || mf_set) {
+ 802107e:	6a3b      	ldr	r3, [r7, #32]
+ 8021080:	2b00      	cmp	r3, #0
+ 8021082:	d002      	beq.n	802108a <ip4_frag+0x1f6>
+ 8021084:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 8021086:	2b00      	cmp	r3, #0
+ 8021088:	d003      	beq.n	8021092 <ip4_frag+0x1fe>
+      /* the last fragment has MF set if the input frame had it */
+      tmp = tmp | IP_MF;
+ 802108a:	8fbb      	ldrh	r3, [r7, #60]	; 0x3c
+ 802108c:	f443 5300 	orr.w	r3, r3, #8192	; 0x2000
+ 8021090:	87bb      	strh	r3, [r7, #60]	; 0x3c
+    }
+    IPH_OFFSET_SET(iphdr, lwip_htons(tmp));
+ 8021092:	8fbb      	ldrh	r3, [r7, #60]	; 0x3c
+ 8021094:	4618      	mov	r0, r3
+ 8021096:	f7f4 ff53 	bl	8015f40 <lwip_htons>
+ 802109a:	4603      	mov	r3, r0
+ 802109c:	461a      	mov	r2, r3
+ 802109e:	6b3b      	ldr	r3, [r7, #48]	; 0x30
+ 80210a0:	80da      	strh	r2, [r3, #6]
+    IPH_LEN_SET(iphdr, lwip_htons((u16_t)(fragsize + IP_HLEN)));
+ 80210a2:	8d7b      	ldrh	r3, [r7, #42]	; 0x2a
+ 80210a4:	3314      	adds	r3, #20
+ 80210a6:	b29b      	uxth	r3, r3
+ 80210a8:	4618      	mov	r0, r3
+ 80210aa:	f7f4 ff49 	bl	8015f40 <lwip_htons>
+ 80210ae:	4603      	mov	r3, r0
+ 80210b0:	461a      	mov	r2, r3
+ 80210b2:	6b3b      	ldr	r3, [r7, #48]	; 0x30
+ 80210b4:	805a      	strh	r2, [r3, #2]
+    IPH_CHKSUM_SET(iphdr, 0);
+ 80210b6:	6b3b      	ldr	r3, [r7, #48]	; 0x30
+ 80210b8:	2200      	movs	r2, #0
+ 80210ba:	729a      	strb	r2, [r3, #10]
+ 80210bc:	2200      	movs	r2, #0
+ 80210be:	72da      	strb	r2, [r3, #11]
+#endif /* CHECKSUM_GEN_IP */
+
+    /* No need for separate header pbuf - we allowed room for it in rambuf
+     * when allocated.
+     */
+    netif->output(netif, rambuf, dest);
+ 80210c0:	68bb      	ldr	r3, [r7, #8]
+ 80210c2:	695b      	ldr	r3, [r3, #20]
+ 80210c4:	687a      	ldr	r2, [r7, #4]
+ 80210c6:	6a79      	ldr	r1, [r7, #36]	; 0x24
+ 80210c8:	68b8      	ldr	r0, [r7, #8]
+ 80210ca:	4798      	blx	r3
+     * recreate it next time round the loop. If we're lucky the hardware
+     * will have already sent the packet, the free will really free, and
+     * there will be zero memory penalty.
+     */
+
+    pbuf_free(rambuf);
+ 80210cc:	6a78      	ldr	r0, [r7, #36]	; 0x24
+ 80210ce:	f7f6 fd13 	bl	8017af8 <pbuf_free>
+    left = (u16_t)(left - fragsize);
+ 80210d2:	f8b7 2042 	ldrh.w	r2, [r7, #66]	; 0x42
+ 80210d6:	8d7b      	ldrh	r3, [r7, #42]	; 0x2a
+ 80210d8:	1ad3      	subs	r3, r2, r3
+ 80210da:	f8a7 3042 	strh.w	r3, [r7, #66]	; 0x42
+    ofo = (u16_t)(ofo + nfb);
+ 80210de:	f8b7 2040 	ldrh.w	r2, [r7, #64]	; 0x40
+ 80210e2:	8f7b      	ldrh	r3, [r7, #58]	; 0x3a
+ 80210e4:	4413      	add	r3, r2
+ 80210e6:	f8a7 3040 	strh.w	r3, [r7, #64]	; 0x40
+  while (left) {
+ 80210ea:	f8b7 3042 	ldrh.w	r3, [r7, #66]	; 0x42
+ 80210ee:	2b00      	cmp	r3, #0
+ 80210f0:	f47f af19 	bne.w	8020f26 <ip4_frag+0x92>
+  }
+  MIB2_STATS_INC(mib2.ipfragoks);
+  return ERR_OK;
+ 80210f4:	2300      	movs	r3, #0
+ 80210f6:	e002      	b.n	80210fe <ip4_frag+0x26a>
+      goto memerr;
+ 80210f8:	bf00      	nop
+memerr:
+  MIB2_STATS_INC(mib2.ipfragfails);
+  return ERR_MEM;
+ 80210fa:	f04f 33ff 	mov.w	r3, #4294967295
+}
+ 80210fe:	4618      	mov	r0, r3
+ 8021100:	3748      	adds	r7, #72	; 0x48
+ 8021102:	46bd      	mov	sp, r7
+ 8021104:	bd80      	pop	{r7, pc}
+ 8021106:	bf00      	nop
+ 8021108:	08026884 	.word	0x08026884
+ 802110c:	08026a60 	.word	0x08026a60
+ 8021110:	080268cc 	.word	0x080268cc
+ 8021114:	08026a7c 	.word	0x08026a7c
+ 8021118:	08026a9c 	.word	0x08026a9c
+ 802111c:	08020e2d 	.word	0x08020e2d
+
+08021120 <ethernet_input>:
+ * @see ETHARP_SUPPORT_VLAN
+ * @see LWIP_HOOK_VLAN_CHECK
+ */
+err_t
+ethernet_input(struct pbuf *p, struct netif *netif)
+{
+ 8021120:	b580      	push	{r7, lr}
+ 8021122:	b086      	sub	sp, #24
+ 8021124:	af00      	add	r7, sp, #0
+ 8021126:	6078      	str	r0, [r7, #4]
+ 8021128:	6039      	str	r1, [r7, #0]
+  struct eth_hdr *ethhdr;
+  u16_t type;
+#if LWIP_ARP || ETHARP_SUPPORT_VLAN || LWIP_IPV6
+  u16_t next_hdr_offset = SIZEOF_ETH_HDR;
+ 802112a:	230e      	movs	r3, #14
+ 802112c:	82fb      	strh	r3, [r7, #22]
+#endif /* LWIP_ARP || ETHARP_SUPPORT_VLAN */
+
+  LWIP_ASSERT_CORE_LOCKED();
+
+  if (p->len <= SIZEOF_ETH_HDR) {
+ 802112e:	687b      	ldr	r3, [r7, #4]
+ 8021130:	895b      	ldrh	r3, [r3, #10]
+ 8021132:	2b0e      	cmp	r3, #14
+ 8021134:	d96e      	bls.n	8021214 <ethernet_input+0xf4>
+    ETHARP_STATS_INC(etharp.drop);
+    MIB2_STATS_NETIF_INC(netif, ifinerrors);
+    goto free_and_return;
+  }
+
+  if (p->if_idx == NETIF_NO_INDEX) {
+ 8021136:	687b      	ldr	r3, [r7, #4]
+ 8021138:	7bdb      	ldrb	r3, [r3, #15]
+ 802113a:	2b00      	cmp	r3, #0
+ 802113c:	d106      	bne.n	802114c <ethernet_input+0x2c>
+    p->if_idx = netif_get_index(netif);
+ 802113e:	683b      	ldr	r3, [r7, #0]
+ 8021140:	f893 3030 	ldrb.w	r3, [r3, #48]	; 0x30
+ 8021144:	3301      	adds	r3, #1
+ 8021146:	b2da      	uxtb	r2, r3
+ 8021148:	687b      	ldr	r3, [r7, #4]
+ 802114a:	73da      	strb	r2, [r3, #15]
+  }
+
+  /* points to packet payload, which starts with an Ethernet header */
+  ethhdr = (struct eth_hdr *)p->payload;
+ 802114c:	687b      	ldr	r3, [r7, #4]
+ 802114e:	685b      	ldr	r3, [r3, #4]
+ 8021150:	613b      	str	r3, [r7, #16]
+               (unsigned char)ethhdr->dest.addr[3], (unsigned char)ethhdr->dest.addr[4], (unsigned char)ethhdr->dest.addr[5],
+               (unsigned char)ethhdr->src.addr[0],  (unsigned char)ethhdr->src.addr[1],  (unsigned char)ethhdr->src.addr[2],
+               (unsigned char)ethhdr->src.addr[3],  (unsigned char)ethhdr->src.addr[4],  (unsigned char)ethhdr->src.addr[5],
+               lwip_htons(ethhdr->type)));
+
+  type = ethhdr->type;
+ 8021152:	693b      	ldr	r3, [r7, #16]
+ 8021154:	7b1a      	ldrb	r2, [r3, #12]
+ 8021156:	7b5b      	ldrb	r3, [r3, #13]
+ 8021158:	021b      	lsls	r3, r3, #8
+ 802115a:	4313      	orrs	r3, r2
+ 802115c:	81fb      	strh	r3, [r7, #14]
+
+#if LWIP_ARP_FILTER_NETIF
+  netif = LWIP_ARP_FILTER_NETIF_FN(p, netif, lwip_htons(type));
+#endif /* LWIP_ARP_FILTER_NETIF*/
+
+  if (ethhdr->dest.addr[0] & 1) {
+ 802115e:	693b      	ldr	r3, [r7, #16]
+ 8021160:	781b      	ldrb	r3, [r3, #0]
+ 8021162:	f003 0301 	and.w	r3, r3, #1
+ 8021166:	2b00      	cmp	r3, #0
+ 8021168:	d023      	beq.n	80211b2 <ethernet_input+0x92>
+    /* this might be a multicast or broadcast packet */
+    if (ethhdr->dest.addr[0] == LL_IP4_MULTICAST_ADDR_0) {
+ 802116a:	693b      	ldr	r3, [r7, #16]
+ 802116c:	781b      	ldrb	r3, [r3, #0]
+ 802116e:	2b01      	cmp	r3, #1
+ 8021170:	d10f      	bne.n	8021192 <ethernet_input+0x72>
+#if LWIP_IPV4
+      if ((ethhdr->dest.addr[1] == LL_IP4_MULTICAST_ADDR_1) &&
+ 8021172:	693b      	ldr	r3, [r7, #16]
+ 8021174:	785b      	ldrb	r3, [r3, #1]
+ 8021176:	2b00      	cmp	r3, #0
+ 8021178:	d11b      	bne.n	80211b2 <ethernet_input+0x92>
+          (ethhdr->dest.addr[2] == LL_IP4_MULTICAST_ADDR_2)) {
+ 802117a:	693b      	ldr	r3, [r7, #16]
+ 802117c:	789b      	ldrb	r3, [r3, #2]
+      if ((ethhdr->dest.addr[1] == LL_IP4_MULTICAST_ADDR_1) &&
+ 802117e:	2b5e      	cmp	r3, #94	; 0x5e
+ 8021180:	d117      	bne.n	80211b2 <ethernet_input+0x92>
+        /* mark the pbuf as link-layer multicast */
+        p->flags |= PBUF_FLAG_LLMCAST;
+ 8021182:	687b      	ldr	r3, [r7, #4]
+ 8021184:	7b5b      	ldrb	r3, [r3, #13]
+ 8021186:	f043 0310 	orr.w	r3, r3, #16
+ 802118a:	b2da      	uxtb	r2, r3
+ 802118c:	687b      	ldr	r3, [r7, #4]
+ 802118e:	735a      	strb	r2, [r3, #13]
+ 8021190:	e00f      	b.n	80211b2 <ethernet_input+0x92>
+             (ethhdr->dest.addr[1] == LL_IP6_MULTICAST_ADDR_1)) {
+      /* mark the pbuf as link-layer multicast */
+      p->flags |= PBUF_FLAG_LLMCAST;
+    }
+#endif /* LWIP_IPV6 */
+    else if (eth_addr_cmp(&ethhdr->dest, &ethbroadcast)) {
+ 8021192:	693b      	ldr	r3, [r7, #16]
+ 8021194:	2206      	movs	r2, #6
+ 8021196:	4928      	ldr	r1, [pc, #160]	; (8021238 <ethernet_input+0x118>)
+ 8021198:	4618      	mov	r0, r3
+ 802119a:	f000 fd77 	bl	8021c8c <memcmp>
+ 802119e:	4603      	mov	r3, r0
+ 80211a0:	2b00      	cmp	r3, #0
+ 80211a2:	d106      	bne.n	80211b2 <ethernet_input+0x92>
+      /* mark the pbuf as link-layer broadcast */
+      p->flags |= PBUF_FLAG_LLBCAST;
+ 80211a4:	687b      	ldr	r3, [r7, #4]
+ 80211a6:	7b5b      	ldrb	r3, [r3, #13]
+ 80211a8:	f043 0308 	orr.w	r3, r3, #8
+ 80211ac:	b2da      	uxtb	r2, r3
+ 80211ae:	687b      	ldr	r3, [r7, #4]
+ 80211b0:	735a      	strb	r2, [r3, #13]
+    }
+  }
+
+  switch (type) {
+ 80211b2:	89fb      	ldrh	r3, [r7, #14]
+ 80211b4:	2b08      	cmp	r3, #8
+ 80211b6:	d003      	beq.n	80211c0 <ethernet_input+0xa0>
+ 80211b8:	f5b3 6fc1 	cmp.w	r3, #1544	; 0x608
+ 80211bc:	d014      	beq.n	80211e8 <ethernet_input+0xc8>
+      }
+#endif
+      ETHARP_STATS_INC(etharp.proterr);
+      ETHARP_STATS_INC(etharp.drop);
+      MIB2_STATS_NETIF_INC(netif, ifinunknownprotos);
+      goto free_and_return;
+ 80211be:	e032      	b.n	8021226 <ethernet_input+0x106>
+      if (!(netif->flags & NETIF_FLAG_ETHARP)) {
+ 80211c0:	683b      	ldr	r3, [r7, #0]
+ 80211c2:	f893 302d 	ldrb.w	r3, [r3, #45]	; 0x2d
+ 80211c6:	f003 0308 	and.w	r3, r3, #8
+ 80211ca:	2b00      	cmp	r3, #0
+ 80211cc:	d024      	beq.n	8021218 <ethernet_input+0xf8>
+      if (pbuf_remove_header(p, next_hdr_offset)) {
+ 80211ce:	8afb      	ldrh	r3, [r7, #22]
+ 80211d0:	4619      	mov	r1, r3
+ 80211d2:	6878      	ldr	r0, [r7, #4]
+ 80211d4:	f7f6 fc0a 	bl	80179ec <pbuf_remove_header>
+ 80211d8:	4603      	mov	r3, r0
+ 80211da:	2b00      	cmp	r3, #0
+ 80211dc:	d11e      	bne.n	802121c <ethernet_input+0xfc>
+        ip4_input(p, netif);
+ 80211de:	6839      	ldr	r1, [r7, #0]
+ 80211e0:	6878      	ldr	r0, [r7, #4]
+ 80211e2:	f7fe ff21 	bl	8020028 <ip4_input>
+      break;
+ 80211e6:	e013      	b.n	8021210 <ethernet_input+0xf0>
+      if (!(netif->flags & NETIF_FLAG_ETHARP)) {
+ 80211e8:	683b      	ldr	r3, [r7, #0]
+ 80211ea:	f893 302d 	ldrb.w	r3, [r3, #45]	; 0x2d
+ 80211ee:	f003 0308 	and.w	r3, r3, #8
+ 80211f2:	2b00      	cmp	r3, #0
+ 80211f4:	d014      	beq.n	8021220 <ethernet_input+0x100>
+      if (pbuf_remove_header(p, next_hdr_offset)) {
+ 80211f6:	8afb      	ldrh	r3, [r7, #22]
+ 80211f8:	4619      	mov	r1, r3
+ 80211fa:	6878      	ldr	r0, [r7, #4]
+ 80211fc:	f7f6 fbf6 	bl	80179ec <pbuf_remove_header>
+ 8021200:	4603      	mov	r3, r0
+ 8021202:	2b00      	cmp	r3, #0
+ 8021204:	d10e      	bne.n	8021224 <ethernet_input+0x104>
+        etharp_input(p, netif);
+ 8021206:	6839      	ldr	r1, [r7, #0]
+ 8021208:	6878      	ldr	r0, [r7, #4]
+ 802120a:	f7fe f897 	bl	801f33c <etharp_input>
+      break;
+ 802120e:	bf00      	nop
+  }
+
+  /* This means the pbuf is freed or consumed,
+     so the caller doesn't have to free it again */
+  return ERR_OK;
+ 8021210:	2300      	movs	r3, #0
+ 8021212:	e00c      	b.n	802122e <ethernet_input+0x10e>
+    goto free_and_return;
+ 8021214:	bf00      	nop
+ 8021216:	e006      	b.n	8021226 <ethernet_input+0x106>
+        goto free_and_return;
+ 8021218:	bf00      	nop
+ 802121a:	e004      	b.n	8021226 <ethernet_input+0x106>
+        goto free_and_return;
+ 802121c:	bf00      	nop
+ 802121e:	e002      	b.n	8021226 <ethernet_input+0x106>
+        goto free_and_return;
+ 8021220:	bf00      	nop
+ 8021222:	e000      	b.n	8021226 <ethernet_input+0x106>
+        goto free_and_return;
+ 8021224:	bf00      	nop
+
+free_and_return:
+  pbuf_free(p);
+ 8021226:	6878      	ldr	r0, [r7, #4]
+ 8021228:	f7f6 fc66 	bl	8017af8 <pbuf_free>
+  return ERR_OK;
+ 802122c:	2300      	movs	r3, #0
+}
+ 802122e:	4618      	mov	r0, r3
+ 8021230:	3718      	adds	r7, #24
+ 8021232:	46bd      	mov	sp, r7
+ 8021234:	bd80      	pop	{r7, pc}
+ 8021236:	bf00      	nop
+ 8021238:	08026cf0 	.word	0x08026cf0
+
+0802123c <ethernet_output>:
+ * @return ERR_OK if the packet was sent, any other err_t on failure
+ */
+err_t
+ethernet_output(struct netif * netif, struct pbuf * p,
+                const struct eth_addr * src, const struct eth_addr * dst,
+                u16_t eth_type) {
+ 802123c:	b580      	push	{r7, lr}
+ 802123e:	b086      	sub	sp, #24
+ 8021240:	af00      	add	r7, sp, #0
+ 8021242:	60f8      	str	r0, [r7, #12]
+ 8021244:	60b9      	str	r1, [r7, #8]
+ 8021246:	607a      	str	r2, [r7, #4]
+ 8021248:	603b      	str	r3, [r7, #0]
+  struct eth_hdr *ethhdr;
+  u16_t eth_type_be = lwip_htons(eth_type);
+ 802124a:	8c3b      	ldrh	r3, [r7, #32]
+ 802124c:	4618      	mov	r0, r3
+ 802124e:	f7f4 fe77 	bl	8015f40 <lwip_htons>
+ 8021252:	4603      	mov	r3, r0
+ 8021254:	82fb      	strh	r3, [r7, #22]
+
+    eth_type_be = PP_HTONS(ETHTYPE_VLAN);
+  } else
+#endif /* ETHARP_SUPPORT_VLAN && defined(LWIP_HOOK_VLAN_SET) */
+  {
+    if (pbuf_add_header(p, SIZEOF_ETH_HDR) != 0) {
+ 8021256:	210e      	movs	r1, #14
+ 8021258:	68b8      	ldr	r0, [r7, #8]
+ 802125a:	f7f6 fbb7 	bl	80179cc <pbuf_add_header>
+ 802125e:	4603      	mov	r3, r0
+ 8021260:	2b00      	cmp	r3, #0
+ 8021262:	d125      	bne.n	80212b0 <ethernet_output+0x74>
+    }
+  }
+
+  LWIP_ASSERT_CORE_LOCKED();
+
+  ethhdr = (struct eth_hdr *)p->payload;
+ 8021264:	68bb      	ldr	r3, [r7, #8]
+ 8021266:	685b      	ldr	r3, [r3, #4]
+ 8021268:	613b      	str	r3, [r7, #16]
+  ethhdr->type = eth_type_be;
+ 802126a:	693b      	ldr	r3, [r7, #16]
+ 802126c:	8afa      	ldrh	r2, [r7, #22]
+ 802126e:	819a      	strh	r2, [r3, #12]
+  SMEMCPY(&ethhdr->dest, dst, ETH_HWADDR_LEN);
+ 8021270:	693b      	ldr	r3, [r7, #16]
+ 8021272:	2206      	movs	r2, #6
+ 8021274:	6839      	ldr	r1, [r7, #0]
+ 8021276:	4618      	mov	r0, r3
+ 8021278:	f000 fdb5 	bl	8021de6 <memcpy>
+  SMEMCPY(&ethhdr->src,  src, ETH_HWADDR_LEN);
+ 802127c:	693b      	ldr	r3, [r7, #16]
+ 802127e:	3306      	adds	r3, #6
+ 8021280:	2206      	movs	r2, #6
+ 8021282:	6879      	ldr	r1, [r7, #4]
+ 8021284:	4618      	mov	r0, r3
+ 8021286:	f000 fdae 	bl	8021de6 <memcpy>
+
+  LWIP_ASSERT("netif->hwaddr_len must be 6 for ethernet_output!",
+ 802128a:	68fb      	ldr	r3, [r7, #12]
+ 802128c:	f893 302c 	ldrb.w	r3, [r3, #44]	; 0x2c
+ 8021290:	2b06      	cmp	r3, #6
+ 8021292:	d006      	beq.n	80212a2 <ethernet_output+0x66>
+ 8021294:	4b0a      	ldr	r3, [pc, #40]	; (80212c0 <ethernet_output+0x84>)
+ 8021296:	f44f 7299 	mov.w	r2, #306	; 0x132
+ 802129a:	490a      	ldr	r1, [pc, #40]	; (80212c4 <ethernet_output+0x88>)
+ 802129c:	480a      	ldr	r0, [pc, #40]	; (80212c8 <ethernet_output+0x8c>)
+ 802129e:	f000 fb73 	bl	8021988 <iprintf>
+              (netif->hwaddr_len == ETH_HWADDR_LEN));
+  LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE,
+              ("ethernet_output: sending packet %p\n", (void *)p));
+
+  /* send the packet */
+  return netif->linkoutput(netif, p);
+ 80212a2:	68fb      	ldr	r3, [r7, #12]
+ 80212a4:	699b      	ldr	r3, [r3, #24]
+ 80212a6:	68b9      	ldr	r1, [r7, #8]
+ 80212a8:	68f8      	ldr	r0, [r7, #12]
+ 80212aa:	4798      	blx	r3
+ 80212ac:	4603      	mov	r3, r0
+ 80212ae:	e002      	b.n	80212b6 <ethernet_output+0x7a>
+      goto pbuf_header_failed;
+ 80212b0:	bf00      	nop
+
+pbuf_header_failed:
+  LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS,
+              ("ethernet_output: could not allocate room for header.\n"));
+  LINK_STATS_INC(link.lenerr);
+  return ERR_BUF;
+ 80212b2:	f06f 0301 	mvn.w	r3, #1
+}
+ 80212b6:	4618      	mov	r0, r3
+ 80212b8:	3718      	adds	r7, #24
+ 80212ba:	46bd      	mov	sp, r7
+ 80212bc:	bd80      	pop	{r7, pc}
+ 80212be:	bf00      	nop
+ 80212c0:	08026aac 	.word	0x08026aac
+ 80212c4:	08026ae4 	.word	0x08026ae4
+ 80212c8:	08026b18 	.word	0x08026b18
+
+080212cc <sys_mbox_new>:
+#endif
+
+/*-----------------------------------------------------------------------------------*/
+//  Creates an empty mailbox.
+err_t sys_mbox_new(sys_mbox_t *mbox, int size)
+{
+ 80212cc:	b580      	push	{r7, lr}
+ 80212ce:	b086      	sub	sp, #24
+ 80212d0:	af00      	add	r7, sp, #0
+ 80212d2:	6078      	str	r0, [r7, #4]
+ 80212d4:	6039      	str	r1, [r7, #0]
+#if (osCMSIS < 0x20000U)
+  osMessageQDef(QUEUE, size, void *);
+ 80212d6:	683b      	ldr	r3, [r7, #0]
+ 80212d8:	60bb      	str	r3, [r7, #8]
+ 80212da:	2304      	movs	r3, #4
+ 80212dc:	60fb      	str	r3, [r7, #12]
+ 80212de:	2300      	movs	r3, #0
+ 80212e0:	613b      	str	r3, [r7, #16]
+ 80212e2:	2300      	movs	r3, #0
+ 80212e4:	617b      	str	r3, [r7, #20]
+  *mbox = osMessageCreate(osMessageQ(QUEUE), NULL);
+ 80212e6:	f107 0308 	add.w	r3, r7, #8
+ 80212ea:	2100      	movs	r1, #0
+ 80212ec:	4618      	mov	r0, r3
+ 80212ee:	f7ef f9c0 	bl	8010672 <osMessageCreate>
+ 80212f2:	4602      	mov	r2, r0
+ 80212f4:	687b      	ldr	r3, [r7, #4]
+ 80212f6:	601a      	str	r2, [r3, #0]
+  if(lwip_stats.sys.mbox.max < lwip_stats.sys.mbox.used)
+  {
+    lwip_stats.sys.mbox.max = lwip_stats.sys.mbox.used;
+  }
+#endif /* SYS_STATS */
+  if(*mbox == NULL)
+ 80212f8:	687b      	ldr	r3, [r7, #4]
+ 80212fa:	681b      	ldr	r3, [r3, #0]
+ 80212fc:	2b00      	cmp	r3, #0
+ 80212fe:	d102      	bne.n	8021306 <sys_mbox_new+0x3a>
+    return ERR_MEM;
+ 8021300:	f04f 33ff 	mov.w	r3, #4294967295
+ 8021304:	e000      	b.n	8021308 <sys_mbox_new+0x3c>
+
+  return ERR_OK;
+ 8021306:	2300      	movs	r3, #0
+}
+ 8021308:	4618      	mov	r0, r3
+ 802130a:	3718      	adds	r7, #24
+ 802130c:	46bd      	mov	sp, r7
+ 802130e:	bd80      	pop	{r7, pc}
+
+08021310 <sys_mbox_free>:
+  Deallocates a mailbox. If there are messages still present in the
+  mailbox when the mailbox is deallocated, it is an indication of a
+  programming error in lwIP and the developer should be notified.
+*/
+void sys_mbox_free(sys_mbox_t *mbox)
+{
+ 8021310:	b580      	push	{r7, lr}
+ 8021312:	b082      	sub	sp, #8
+ 8021314:	af00      	add	r7, sp, #0
+ 8021316:	6078      	str	r0, [r7, #4]
+#if (osCMSIS < 0x20000U)
+  if(osMessageWaiting(*mbox))
+ 8021318:	687b      	ldr	r3, [r7, #4]
+ 802131a:	681b      	ldr	r3, [r3, #0]
+ 802131c:	4618      	mov	r0, r3
+ 802131e:	f7ef fa85 	bl	801082c <osMessageWaiting>
+    lwip_stats.sys.mbox.err++;
+#endif /* SYS_STATS */
+
+  }
+#if (osCMSIS < 0x20000U)
+  osMessageDelete(*mbox);
+ 8021322:	687b      	ldr	r3, [r7, #4]
+ 8021324:	681b      	ldr	r3, [r3, #0]
+ 8021326:	4618      	mov	r0, r3
+ 8021328:	f7ef fa96 	bl	8010858 <osMessageDelete>
+  osMessageQueueDelete(*mbox);
+#endif
+#if SYS_STATS
+  --lwip_stats.sys.mbox.used;
+#endif /* SYS_STATS */
+}
+ 802132c:	bf00      	nop
+ 802132e:	3708      	adds	r7, #8
+ 8021330:	46bd      	mov	sp, r7
+ 8021332:	bd80      	pop	{r7, pc}
+
+08021334 <sys_mbox_trypost>:
+
+
+/*-----------------------------------------------------------------------------------*/
+//   Try to post the "msg" to the mailbox.
+err_t sys_mbox_trypost(sys_mbox_t *mbox, void *msg)
+{
+ 8021334:	b580      	push	{r7, lr}
+ 8021336:	b084      	sub	sp, #16
+ 8021338:	af00      	add	r7, sp, #0
+ 802133a:	6078      	str	r0, [r7, #4]
+ 802133c:	6039      	str	r1, [r7, #0]
+  err_t result;
+#if (osCMSIS < 0x20000U)
+  if(osMessagePut(*mbox, (uint32_t)msg, 0) == osOK)
+ 802133e:	687b      	ldr	r3, [r7, #4]
+ 8021340:	681b      	ldr	r3, [r3, #0]
+ 8021342:	6839      	ldr	r1, [r7, #0]
+ 8021344:	2200      	movs	r2, #0
+ 8021346:	4618      	mov	r0, r3
+ 8021348:	f7ef f9bc 	bl	80106c4 <osMessagePut>
+ 802134c:	4603      	mov	r3, r0
+ 802134e:	2b00      	cmp	r3, #0
+ 8021350:	d102      	bne.n	8021358 <sys_mbox_trypost+0x24>
+#else
+  if(osMessageQueuePut(*mbox, &msg, 0, 0) == osOK)
+#endif
+  {
+    result = ERR_OK;
+ 8021352:	2300      	movs	r3, #0
+ 8021354:	73fb      	strb	r3, [r7, #15]
+ 8021356:	e001      	b.n	802135c <sys_mbox_trypost+0x28>
+  }
+  else
+  {
+    // could not post, queue must be full
+    result = ERR_MEM;
+ 8021358:	23ff      	movs	r3, #255	; 0xff
+ 802135a:	73fb      	strb	r3, [r7, #15]
+#if SYS_STATS
+    lwip_stats.sys.mbox.err++;
+#endif /* SYS_STATS */
+  }
+
+  return result;
+ 802135c:	f997 300f 	ldrsb.w	r3, [r7, #15]
+}
+ 8021360:	4618      	mov	r0, r3
+ 8021362:	3710      	adds	r7, #16
+ 8021364:	46bd      	mov	sp, r7
+ 8021366:	bd80      	pop	{r7, pc}
+
+08021368 <sys_arch_mbox_fetch>:
+
+  Note that a function with a similar name, sys_mbox_fetch(), is
+  implemented by lwIP.
+*/
+u32_t sys_arch_mbox_fetch(sys_mbox_t *mbox, void **msg, u32_t timeout)
+{
+ 8021368:	b580      	push	{r7, lr}
+ 802136a:	b08c      	sub	sp, #48	; 0x30
+ 802136c:	af00      	add	r7, sp, #0
+ 802136e:	61f8      	str	r0, [r7, #28]
+ 8021370:	61b9      	str	r1, [r7, #24]
+ 8021372:	617a      	str	r2, [r7, #20]
+#if (osCMSIS < 0x20000U)
+  osEvent event;
+  uint32_t starttime = osKernelSysTick();
+ 8021374:	f7ee ffa8 	bl	80102c8 <osKernelSysTick>
+ 8021378:	62f8      	str	r0, [r7, #44]	; 0x2c
+#else
+  osStatus_t status;
+  uint32_t starttime = osKernelGetTickCount();
+#endif
+  if(timeout != 0)
+ 802137a:	697b      	ldr	r3, [r7, #20]
+ 802137c:	2b00      	cmp	r3, #0
+ 802137e:	d017      	beq.n	80213b0 <sys_arch_mbox_fetch+0x48>
+  {
+#if (osCMSIS < 0x20000U)
+    event = osMessageGet (*mbox, timeout);
+ 8021380:	69fb      	ldr	r3, [r7, #28]
+ 8021382:	6819      	ldr	r1, [r3, #0]
+ 8021384:	f107 0320 	add.w	r3, r7, #32
+ 8021388:	697a      	ldr	r2, [r7, #20]
+ 802138a:	4618      	mov	r0, r3
+ 802138c:	f7ef f9da 	bl	8010744 <osMessageGet>
+
+    if(event.status == osEventMessage)
+ 8021390:	6a3b      	ldr	r3, [r7, #32]
+ 8021392:	2b10      	cmp	r3, #16
+ 8021394:	d109      	bne.n	80213aa <sys_arch_mbox_fetch+0x42>
+    {
+      *msg = (void *)event.value.v;
+ 8021396:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 8021398:	461a      	mov	r2, r3
+ 802139a:	69bb      	ldr	r3, [r7, #24]
+ 802139c:	601a      	str	r2, [r3, #0]
+      return (osKernelSysTick() - starttime);
+ 802139e:	f7ee ff93 	bl	80102c8 <osKernelSysTick>
+ 80213a2:	4602      	mov	r2, r0
+ 80213a4:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 80213a6:	1ad3      	subs	r3, r2, r3
+ 80213a8:	e019      	b.n	80213de <sys_arch_mbox_fetch+0x76>
+      return (osKernelGetTickCount() - starttime);
+    }
+#endif
+    else
+    {
+      return SYS_ARCH_TIMEOUT;
+ 80213aa:	f04f 33ff 	mov.w	r3, #4294967295
+ 80213ae:	e016      	b.n	80213de <sys_arch_mbox_fetch+0x76>
+    }
+  }
+  else
+  {
+#if (osCMSIS < 0x20000U)
+    event = osMessageGet (*mbox, osWaitForever);
+ 80213b0:	69fb      	ldr	r3, [r7, #28]
+ 80213b2:	6819      	ldr	r1, [r3, #0]
+ 80213b4:	463b      	mov	r3, r7
+ 80213b6:	f04f 32ff 	mov.w	r2, #4294967295
+ 80213ba:	4618      	mov	r0, r3
+ 80213bc:	f7ef f9c2 	bl	8010744 <osMessageGet>
+ 80213c0:	f107 0320 	add.w	r3, r7, #32
+ 80213c4:	463a      	mov	r2, r7
+ 80213c6:	ca07      	ldmia	r2, {r0, r1, r2}
+ 80213c8:	e883 0007 	stmia.w	r3, {r0, r1, r2}
+    *msg = (void *)event.value.v;
+ 80213cc:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 80213ce:	461a      	mov	r2, r3
+ 80213d0:	69bb      	ldr	r3, [r7, #24]
+ 80213d2:	601a      	str	r2, [r3, #0]
+    return (osKernelSysTick() - starttime);
+ 80213d4:	f7ee ff78 	bl	80102c8 <osKernelSysTick>
+ 80213d8:	4602      	mov	r2, r0
+ 80213da:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 80213dc:	1ad3      	subs	r3, r2, r3
+#else
+    osMessageQueueGet(*mbox, msg, 0, osWaitForever );
+    return (osKernelGetTickCount() - starttime);
+#endif
+  }
+}
+ 80213de:	4618      	mov	r0, r3
+ 80213e0:	3730      	adds	r7, #48	; 0x30
+ 80213e2:	46bd      	mov	sp, r7
+ 80213e4:	bd80      	pop	{r7, pc}
+
+080213e6 <sys_arch_mbox_tryfetch>:
+/*
+  Similar to sys_arch_mbox_fetch, but if message is not ready immediately, we'll
+  return with SYS_MBOX_EMPTY.  On success, 0 is returned.
+*/
+u32_t sys_arch_mbox_tryfetch(sys_mbox_t *mbox, void **msg)
+{
+ 80213e6:	b580      	push	{r7, lr}
+ 80213e8:	b086      	sub	sp, #24
+ 80213ea:	af00      	add	r7, sp, #0
+ 80213ec:	6078      	str	r0, [r7, #4]
+ 80213ee:	6039      	str	r1, [r7, #0]
+#if (osCMSIS < 0x20000U)
+  osEvent event;
+
+  event = osMessageGet (*mbox, 0);
+ 80213f0:	687b      	ldr	r3, [r7, #4]
+ 80213f2:	6819      	ldr	r1, [r3, #0]
+ 80213f4:	f107 030c 	add.w	r3, r7, #12
+ 80213f8:	2200      	movs	r2, #0
+ 80213fa:	4618      	mov	r0, r3
+ 80213fc:	f7ef f9a2 	bl	8010744 <osMessageGet>
+
+  if(event.status == osEventMessage)
+ 8021400:	68fb      	ldr	r3, [r7, #12]
+ 8021402:	2b10      	cmp	r3, #16
+ 8021404:	d105      	bne.n	8021412 <sys_arch_mbox_tryfetch+0x2c>
+  {
+    *msg = (void *)event.value.v;
+ 8021406:	693b      	ldr	r3, [r7, #16]
+ 8021408:	461a      	mov	r2, r3
+ 802140a:	683b      	ldr	r3, [r7, #0]
+ 802140c:	601a      	str	r2, [r3, #0]
+#else
+  if (osMessageQueueGet(*mbox, msg, 0, 0) == osOK)
+  {
+#endif
+    return ERR_OK;
+ 802140e:	2300      	movs	r3, #0
+ 8021410:	e001      	b.n	8021416 <sys_arch_mbox_tryfetch+0x30>
+  }
+  else
+  {
+    return SYS_MBOX_EMPTY;
+ 8021412:	f04f 33ff 	mov.w	r3, #4294967295
+  }
+}
+ 8021416:	4618      	mov	r0, r3
+ 8021418:	3718      	adds	r7, #24
+ 802141a:	46bd      	mov	sp, r7
+ 802141c:	bd80      	pop	{r7, pc}
+
+0802141e <sys_mbox_valid>:
+/*----------------------------------------------------------------------------------*/
+int sys_mbox_valid(sys_mbox_t *mbox)
+{
+ 802141e:	b480      	push	{r7}
+ 8021420:	b083      	sub	sp, #12
+ 8021422:	af00      	add	r7, sp, #0
+ 8021424:	6078      	str	r0, [r7, #4]
+  if (*mbox == SYS_MBOX_NULL)
+ 8021426:	687b      	ldr	r3, [r7, #4]
+ 8021428:	681b      	ldr	r3, [r3, #0]
+ 802142a:	2b00      	cmp	r3, #0
+ 802142c:	d101      	bne.n	8021432 <sys_mbox_valid+0x14>
+    return 0;
+ 802142e:	2300      	movs	r3, #0
+ 8021430:	e000      	b.n	8021434 <sys_mbox_valid+0x16>
+  else
+    return 1;
+ 8021432:	2301      	movs	r3, #1
+}
+ 8021434:	4618      	mov	r0, r3
+ 8021436:	370c      	adds	r7, #12
+ 8021438:	46bd      	mov	sp, r7
+ 802143a:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 802143e:	4770      	bx	lr
+
+08021440 <sys_mbox_set_invalid>:
+/*-----------------------------------------------------------------------------------*/
+void sys_mbox_set_invalid(sys_mbox_t *mbox)
+{
+ 8021440:	b480      	push	{r7}
+ 8021442:	b083      	sub	sp, #12
+ 8021444:	af00      	add	r7, sp, #0
+ 8021446:	6078      	str	r0, [r7, #4]
+  *mbox = SYS_MBOX_NULL;
+ 8021448:	687b      	ldr	r3, [r7, #4]
+ 802144a:	2200      	movs	r2, #0
+ 802144c:	601a      	str	r2, [r3, #0]
+}
+ 802144e:	bf00      	nop
+ 8021450:	370c      	adds	r7, #12
+ 8021452:	46bd      	mov	sp, r7
+ 8021454:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8021458:	4770      	bx	lr
+
+0802145a <sys_sem_new>:
+
+/*-----------------------------------------------------------------------------------*/
+//  Creates a new semaphore. The "count" argument specifies
+//  the initial state of the semaphore.
+err_t sys_sem_new(sys_sem_t *sem, u8_t count)
+{
+ 802145a:	b580      	push	{r7, lr}
+ 802145c:	b084      	sub	sp, #16
+ 802145e:	af00      	add	r7, sp, #0
+ 8021460:	6078      	str	r0, [r7, #4]
+ 8021462:	460b      	mov	r3, r1
+ 8021464:	70fb      	strb	r3, [r7, #3]
+#if (osCMSIS < 0x20000U)
+  osSemaphoreDef(SEM);
+ 8021466:	2300      	movs	r3, #0
+ 8021468:	60bb      	str	r3, [r7, #8]
+ 802146a:	2300      	movs	r3, #0
+ 802146c:	60fb      	str	r3, [r7, #12]
+  *sem = osSemaphoreCreate (osSemaphore(SEM), 1);
+ 802146e:	f107 0308 	add.w	r3, r7, #8
+ 8021472:	2101      	movs	r1, #1
+ 8021474:	4618      	mov	r0, r3
+ 8021476:	f7ef f833 	bl	80104e0 <osSemaphoreCreate>
+ 802147a:	4602      	mov	r2, r0
+ 802147c:	687b      	ldr	r3, [r7, #4]
+ 802147e:	601a      	str	r2, [r3, #0]
+#else
+  *sem = osSemaphoreNew(UINT16_MAX, count, NULL);
+#endif
+
+  if(*sem == NULL)
+ 8021480:	687b      	ldr	r3, [r7, #4]
+ 8021482:	681b      	ldr	r3, [r3, #0]
+ 8021484:	2b00      	cmp	r3, #0
+ 8021486:	d102      	bne.n	802148e <sys_sem_new+0x34>
+  {
+#if SYS_STATS
+    ++lwip_stats.sys.sem.err;
+#endif /* SYS_STATS */
+    return ERR_MEM;
+ 8021488:	f04f 33ff 	mov.w	r3, #4294967295
+ 802148c:	e009      	b.n	80214a2 <sys_sem_new+0x48>
+  }
+
+  if(count == 0)	// Means it can't be taken
+ 802148e:	78fb      	ldrb	r3, [r7, #3]
+ 8021490:	2b00      	cmp	r3, #0
+ 8021492:	d105      	bne.n	80214a0 <sys_sem_new+0x46>
+  {
+#if (osCMSIS < 0x20000U)
+    osSemaphoreWait(*sem, 0);
+ 8021494:	687b      	ldr	r3, [r7, #4]
+ 8021496:	681b      	ldr	r3, [r3, #0]
+ 8021498:	2100      	movs	r1, #0
+ 802149a:	4618      	mov	r0, r3
+ 802149c:	f7ef f852 	bl	8010544 <osSemaphoreWait>
+  if (lwip_stats.sys.sem.max < lwip_stats.sys.sem.used) {
+    lwip_stats.sys.sem.max = lwip_stats.sys.sem.used;
+  }
+#endif /* SYS_STATS */
+
+  return ERR_OK;
+ 80214a0:	2300      	movs	r3, #0
+}
+ 80214a2:	4618      	mov	r0, r3
+ 80214a4:	3710      	adds	r7, #16
+ 80214a6:	46bd      	mov	sp, r7
+ 80214a8:	bd80      	pop	{r7, pc}
+
+080214aa <sys_arch_sem_wait>:
+
+  Notice that lwIP implements a function with a similar name,
+  sys_sem_wait(), that uses the sys_arch_sem_wait() function.
+*/
+u32_t sys_arch_sem_wait(sys_sem_t *sem, u32_t timeout)
+{
+ 80214aa:	b580      	push	{r7, lr}
+ 80214ac:	b084      	sub	sp, #16
+ 80214ae:	af00      	add	r7, sp, #0
+ 80214b0:	6078      	str	r0, [r7, #4]
+ 80214b2:	6039      	str	r1, [r7, #0]
+#if (osCMSIS < 0x20000U)
+  uint32_t starttime = osKernelSysTick();
+ 80214b4:	f7ee ff08 	bl	80102c8 <osKernelSysTick>
+ 80214b8:	60f8      	str	r0, [r7, #12]
+#else
+  uint32_t starttime = osKernelGetTickCount();
+#endif
+  if(timeout != 0)
+ 80214ba:	683b      	ldr	r3, [r7, #0]
+ 80214bc:	2b00      	cmp	r3, #0
+ 80214be:	d011      	beq.n	80214e4 <sys_arch_sem_wait+0x3a>
+  {
+#if (osCMSIS < 0x20000U)
+    if(osSemaphoreWait (*sem, timeout) == osOK)
+ 80214c0:	687b      	ldr	r3, [r7, #4]
+ 80214c2:	681b      	ldr	r3, [r3, #0]
+ 80214c4:	6839      	ldr	r1, [r7, #0]
+ 80214c6:	4618      	mov	r0, r3
+ 80214c8:	f7ef f83c 	bl	8010544 <osSemaphoreWait>
+ 80214cc:	4603      	mov	r3, r0
+ 80214ce:	2b00      	cmp	r3, #0
+ 80214d0:	d105      	bne.n	80214de <sys_arch_sem_wait+0x34>
+    {
+      return (osKernelSysTick() - starttime);
+ 80214d2:	f7ee fef9 	bl	80102c8 <osKernelSysTick>
+ 80214d6:	4602      	mov	r2, r0
+ 80214d8:	68fb      	ldr	r3, [r7, #12]
+ 80214da:	1ad3      	subs	r3, r2, r3
+ 80214dc:	e012      	b.n	8021504 <sys_arch_sem_wait+0x5a>
+        return (osKernelGetTickCount() - starttime);
+#endif
+    }
+    else
+    {
+      return SYS_ARCH_TIMEOUT;
+ 80214de:	f04f 33ff 	mov.w	r3, #4294967295
+ 80214e2:	e00f      	b.n	8021504 <sys_arch_sem_wait+0x5a>
+    }
+  }
+  else
+  {
+#if (osCMSIS < 0x20000U)
+    while(osSemaphoreWait (*sem, osWaitForever) != osOK);
+ 80214e4:	bf00      	nop
+ 80214e6:	687b      	ldr	r3, [r7, #4]
+ 80214e8:	681b      	ldr	r3, [r3, #0]
+ 80214ea:	f04f 31ff 	mov.w	r1, #4294967295
+ 80214ee:	4618      	mov	r0, r3
+ 80214f0:	f7ef f828 	bl	8010544 <osSemaphoreWait>
+ 80214f4:	4603      	mov	r3, r0
+ 80214f6:	2b00      	cmp	r3, #0
+ 80214f8:	d1f5      	bne.n	80214e6 <sys_arch_sem_wait+0x3c>
+    return (osKernelSysTick() - starttime);
+ 80214fa:	f7ee fee5 	bl	80102c8 <osKernelSysTick>
+ 80214fe:	4602      	mov	r2, r0
+ 8021500:	68fb      	ldr	r3, [r7, #12]
+ 8021502:	1ad3      	subs	r3, r2, r3
+#else
+    while(osSemaphoreAcquire(*sem, osWaitForever) != osOK);
+    return (osKernelGetTickCount() - starttime);
+#endif
+  }
+}
+ 8021504:	4618      	mov	r0, r3
+ 8021506:	3710      	adds	r7, #16
+ 8021508:	46bd      	mov	sp, r7
+ 802150a:	bd80      	pop	{r7, pc}
+
+0802150c <sys_sem_signal>:
+
+/*-----------------------------------------------------------------------------------*/
+// Signals a semaphore
+void sys_sem_signal(sys_sem_t *sem)
+{
+ 802150c:	b580      	push	{r7, lr}
+ 802150e:	b082      	sub	sp, #8
+ 8021510:	af00      	add	r7, sp, #0
+ 8021512:	6078      	str	r0, [r7, #4]
+  osSemaphoreRelease(*sem);
+ 8021514:	687b      	ldr	r3, [r7, #4]
+ 8021516:	681b      	ldr	r3, [r3, #0]
+ 8021518:	4618      	mov	r0, r3
+ 802151a:	f7ef f861 	bl	80105e0 <osSemaphoreRelease>
+}
+ 802151e:	bf00      	nop
+ 8021520:	3708      	adds	r7, #8
+ 8021522:	46bd      	mov	sp, r7
+ 8021524:	bd80      	pop	{r7, pc}
+
+08021526 <sys_sem_free>:
+
+/*-----------------------------------------------------------------------------------*/
+// Deallocates a semaphore
+void sys_sem_free(sys_sem_t *sem)
+{
+ 8021526:	b580      	push	{r7, lr}
+ 8021528:	b082      	sub	sp, #8
+ 802152a:	af00      	add	r7, sp, #0
+ 802152c:	6078      	str	r0, [r7, #4]
+#if SYS_STATS
+  --lwip_stats.sys.sem.used;
+#endif /* SYS_STATS */
+
+  osSemaphoreDelete(*sem);
+ 802152e:	687b      	ldr	r3, [r7, #4]
+ 8021530:	681b      	ldr	r3, [r3, #0]
+ 8021532:	4618      	mov	r0, r3
+ 8021534:	f7ef f88a 	bl	801064c <osSemaphoreDelete>
+}
+ 8021538:	bf00      	nop
+ 802153a:	3708      	adds	r7, #8
+ 802153c:	46bd      	mov	sp, r7
+ 802153e:	bd80      	pop	{r7, pc}
+
+08021540 <sys_sem_valid>:
+/*-----------------------------------------------------------------------------------*/
+int sys_sem_valid(sys_sem_t *sem)
+{
+ 8021540:	b480      	push	{r7}
+ 8021542:	b083      	sub	sp, #12
+ 8021544:	af00      	add	r7, sp, #0
+ 8021546:	6078      	str	r0, [r7, #4]
+  if (*sem == SYS_SEM_NULL)
+ 8021548:	687b      	ldr	r3, [r7, #4]
+ 802154a:	681b      	ldr	r3, [r3, #0]
+ 802154c:	2b00      	cmp	r3, #0
+ 802154e:	d101      	bne.n	8021554 <sys_sem_valid+0x14>
+    return 0;
+ 8021550:	2300      	movs	r3, #0
+ 8021552:	e000      	b.n	8021556 <sys_sem_valid+0x16>
+  else
+    return 1;
+ 8021554:	2301      	movs	r3, #1
+}
+ 8021556:	4618      	mov	r0, r3
+ 8021558:	370c      	adds	r7, #12
+ 802155a:	46bd      	mov	sp, r7
+ 802155c:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8021560:	4770      	bx	lr
+
+08021562 <sys_sem_set_invalid>:
+
+/*-----------------------------------------------------------------------------------*/
+void sys_sem_set_invalid(sys_sem_t *sem)
+{
+ 8021562:	b480      	push	{r7}
+ 8021564:	b083      	sub	sp, #12
+ 8021566:	af00      	add	r7, sp, #0
+ 8021568:	6078      	str	r0, [r7, #4]
+  *sem = SYS_SEM_NULL;
+ 802156a:	687b      	ldr	r3, [r7, #4]
+ 802156c:	2200      	movs	r2, #0
+ 802156e:	601a      	str	r2, [r3, #0]
+}
+ 8021570:	bf00      	nop
+ 8021572:	370c      	adds	r7, #12
+ 8021574:	46bd      	mov	sp, r7
+ 8021576:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 802157a:	4770      	bx	lr
+
+0802157c <sys_init>:
+#else
+osMutexId_t lwip_sys_mutex;
+#endif
+// Initialize sys arch
+void sys_init(void)
+{
+ 802157c:	b580      	push	{r7, lr}
+ 802157e:	af00      	add	r7, sp, #0
+#if (osCMSIS < 0x20000U)
+  lwip_sys_mutex = osMutexCreate(osMutex(lwip_sys_mutex));
+ 8021580:	4803      	ldr	r0, [pc, #12]	; (8021590 <sys_init+0x14>)
+ 8021582:	f7ee ff11 	bl	80103a8 <osMutexCreate>
+ 8021586:	4603      	mov	r3, r0
+ 8021588:	4a02      	ldr	r2, [pc, #8]	; (8021594 <sys_init+0x18>)
+ 802158a:	6013      	str	r3, [r2, #0]
+#else
+  lwip_sys_mutex = osMutexNew(NULL);
+#endif
+}
+ 802158c:	bf00      	nop
+ 802158e:	bd80      	pop	{r7, pc}
+ 8021590:	08026d00 	.word	0x08026d00
+ 8021594:	2401a5e4 	.word	0x2401a5e4
+
+08021598 <sys_mutex_new>:
+                                      /* Mutexes*/
+/*-----------------------------------------------------------------------------------*/
+/*-----------------------------------------------------------------------------------*/
+#if LWIP_COMPAT_MUTEX == 0
+/* Create a new mutex*/
+err_t sys_mutex_new(sys_mutex_t *mutex) {
+ 8021598:	b580      	push	{r7, lr}
+ 802159a:	b084      	sub	sp, #16
+ 802159c:	af00      	add	r7, sp, #0
+ 802159e:	6078      	str	r0, [r7, #4]
+
+#if (osCMSIS < 0x20000U)
+  osMutexDef(MUTEX);
+ 80215a0:	2300      	movs	r3, #0
+ 80215a2:	60bb      	str	r3, [r7, #8]
+ 80215a4:	2300      	movs	r3, #0
+ 80215a6:	60fb      	str	r3, [r7, #12]
+  *mutex = osMutexCreate(osMutex(MUTEX));
+ 80215a8:	f107 0308 	add.w	r3, r7, #8
+ 80215ac:	4618      	mov	r0, r3
+ 80215ae:	f7ee fefb 	bl	80103a8 <osMutexCreate>
+ 80215b2:	4602      	mov	r2, r0
+ 80215b4:	687b      	ldr	r3, [r7, #4]
+ 80215b6:	601a      	str	r2, [r3, #0]
+#else
+  *mutex = osMutexNew(NULL);
+#endif
+
+  if(*mutex == NULL)
+ 80215b8:	687b      	ldr	r3, [r7, #4]
+ 80215ba:	681b      	ldr	r3, [r3, #0]
+ 80215bc:	2b00      	cmp	r3, #0
+ 80215be:	d102      	bne.n	80215c6 <sys_mutex_new+0x2e>
+  {
+#if SYS_STATS
+    ++lwip_stats.sys.mutex.err;
+#endif /* SYS_STATS */
+    return ERR_MEM;
+ 80215c0:	f04f 33ff 	mov.w	r3, #4294967295
+ 80215c4:	e000      	b.n	80215c8 <sys_mutex_new+0x30>
+  ++lwip_stats.sys.mutex.used;
+  if (lwip_stats.sys.mutex.max < lwip_stats.sys.mutex.used) {
+    lwip_stats.sys.mutex.max = lwip_stats.sys.mutex.used;
+  }
+#endif /* SYS_STATS */
+  return ERR_OK;
+ 80215c6:	2300      	movs	r3, #0
+}
+ 80215c8:	4618      	mov	r0, r3
+ 80215ca:	3710      	adds	r7, #16
+ 80215cc:	46bd      	mov	sp, r7
+ 80215ce:	bd80      	pop	{r7, pc}
+
+080215d0 <sys_mutex_lock>:
+  osMutexDelete(*mutex);
+}
+/*-----------------------------------------------------------------------------------*/
+/* Lock a mutex*/
+void sys_mutex_lock(sys_mutex_t *mutex)
+{
+ 80215d0:	b580      	push	{r7, lr}
+ 80215d2:	b082      	sub	sp, #8
+ 80215d4:	af00      	add	r7, sp, #0
+ 80215d6:	6078      	str	r0, [r7, #4]
+#if (osCMSIS < 0x20000U)
+  osMutexWait(*mutex, osWaitForever);
+ 80215d8:	687b      	ldr	r3, [r7, #4]
+ 80215da:	681b      	ldr	r3, [r3, #0]
+ 80215dc:	f04f 31ff 	mov.w	r1, #4294967295
+ 80215e0:	4618      	mov	r0, r3
+ 80215e2:	f7ee fef9 	bl	80103d8 <osMutexWait>
+#else
+  osMutexAcquire(*mutex, osWaitForever);
+#endif
+}
+ 80215e6:	bf00      	nop
+ 80215e8:	3708      	adds	r7, #8
+ 80215ea:	46bd      	mov	sp, r7
+ 80215ec:	bd80      	pop	{r7, pc}
+
+080215ee <sys_mutex_unlock>:
+
+/*-----------------------------------------------------------------------------------*/
+/* Unlock a mutex*/
+void sys_mutex_unlock(sys_mutex_t *mutex)
+{
+ 80215ee:	b580      	push	{r7, lr}
+ 80215f0:	b082      	sub	sp, #8
+ 80215f2:	af00      	add	r7, sp, #0
+ 80215f4:	6078      	str	r0, [r7, #4]
+  osMutexRelease(*mutex);
+ 80215f6:	687b      	ldr	r3, [r7, #4]
+ 80215f8:	681b      	ldr	r3, [r3, #0]
+ 80215fa:	4618      	mov	r0, r3
+ 80215fc:	f7ee ff3a 	bl	8010474 <osMutexRelease>
+}
+ 8021600:	bf00      	nop
+ 8021602:	3708      	adds	r7, #8
+ 8021604:	46bd      	mov	sp, r7
+ 8021606:	bd80      	pop	{r7, pc}
+
+08021608 <sys_thread_new>:
+  function "thread()". The "arg" argument will be passed as an argument to the
+  thread() function. The id of the new thread is returned. Both the id and
+  the priority are system dependent.
+*/
+sys_thread_t sys_thread_new(const char *name, lwip_thread_fn thread , void *arg, int stacksize, int prio)
+{
+ 8021608:	b580      	push	{r7, lr}
+ 802160a:	b08c      	sub	sp, #48	; 0x30
+ 802160c:	af00      	add	r7, sp, #0
+ 802160e:	60f8      	str	r0, [r7, #12]
+ 8021610:	60b9      	str	r1, [r7, #8]
+ 8021612:	607a      	str	r2, [r7, #4]
+ 8021614:	603b      	str	r3, [r7, #0]
+#if (osCMSIS < 0x20000U)
+  const osThreadDef_t os_thread_def = { (char *)name, (os_pthread)thread, (osPriority)prio, 0, stacksize};
+ 8021616:	f107 0314 	add.w	r3, r7, #20
+ 802161a:	2200      	movs	r2, #0
+ 802161c:	601a      	str	r2, [r3, #0]
+ 802161e:	605a      	str	r2, [r3, #4]
+ 8021620:	609a      	str	r2, [r3, #8]
+ 8021622:	60da      	str	r2, [r3, #12]
+ 8021624:	611a      	str	r2, [r3, #16]
+ 8021626:	615a      	str	r2, [r3, #20]
+ 8021628:	619a      	str	r2, [r3, #24]
+ 802162a:	68fb      	ldr	r3, [r7, #12]
+ 802162c:	617b      	str	r3, [r7, #20]
+ 802162e:	68bb      	ldr	r3, [r7, #8]
+ 8021630:	61bb      	str	r3, [r7, #24]
+ 8021632:	6bbb      	ldr	r3, [r7, #56]	; 0x38
+ 8021634:	b21b      	sxth	r3, r3
+ 8021636:	83bb      	strh	r3, [r7, #28]
+ 8021638:	683b      	ldr	r3, [r7, #0]
+ 802163a:	627b      	str	r3, [r7, #36]	; 0x24
+  return osThreadCreate(&os_thread_def, arg);
+ 802163c:	f107 0314 	add.w	r3, r7, #20
+ 8021640:	6879      	ldr	r1, [r7, #4]
+ 8021642:	4618      	mov	r0, r3
+ 8021644:	f7ee fe50 	bl	80102e8 <osThreadCreate>
+ 8021648:	4603      	mov	r3, r0
+                        .stack_size = stacksize,
+                        .priority = (osPriority_t)prio,
+                      };
+  return osThreadNew(thread, arg, &attributes);
+#endif
+}
+ 802164a:	4618      	mov	r0, r3
+ 802164c:	3730      	adds	r7, #48	; 0x30
+ 802164e:	46bd      	mov	sp, r7
+ 8021650:	bd80      	pop	{r7, pc}
+	...
+
+08021654 <sys_arch_protect>:
+
+  Note: This function is based on FreeRTOS API, because no equivalent CMSIS-RTOS
+        API is available
+*/
+sys_prot_t sys_arch_protect(void)
+{
+ 8021654:	b580      	push	{r7, lr}
+ 8021656:	af00      	add	r7, sp, #0
+#if (osCMSIS < 0x20000U)
+  osMutexWait(lwip_sys_mutex, osWaitForever);
+ 8021658:	4b04      	ldr	r3, [pc, #16]	; (802166c <sys_arch_protect+0x18>)
+ 802165a:	681b      	ldr	r3, [r3, #0]
+ 802165c:	f04f 31ff 	mov.w	r1, #4294967295
+ 8021660:	4618      	mov	r0, r3
+ 8021662:	f7ee feb9 	bl	80103d8 <osMutexWait>
+#else
+  osMutexAcquire(lwip_sys_mutex, osWaitForever);
+#endif
+  return (sys_prot_t)1;
+ 8021666:	2301      	movs	r3, #1
+}
+ 8021668:	4618      	mov	r0, r3
+ 802166a:	bd80      	pop	{r7, pc}
+ 802166c:	2401a5e4 	.word	0x2401a5e4
+
+08021670 <sys_arch_unprotect>:
+
+  Note: This function is based on FreeRTOS API, because no equivalent CMSIS-RTOS
+        API is available
+*/
+void sys_arch_unprotect(sys_prot_t pval)
+{
+ 8021670:	b580      	push	{r7, lr}
+ 8021672:	b082      	sub	sp, #8
+ 8021674:	af00      	add	r7, sp, #0
+ 8021676:	6078      	str	r0, [r7, #4]
+  ( void ) pval;
+  osMutexRelease(lwip_sys_mutex);
+ 8021678:	4b04      	ldr	r3, [pc, #16]	; (802168c <sys_arch_unprotect+0x1c>)
+ 802167a:	681b      	ldr	r3, [r3, #0]
+ 802167c:	4618      	mov	r0, r3
+ 802167e:	f7ee fef9 	bl	8010474 <osMutexRelease>
+}
+ 8021682:	bf00      	nop
+ 8021684:	3708      	adds	r7, #8
+ 8021686:	46bd      	mov	sp, r7
+ 8021688:	bd80      	pop	{r7, pc}
+ 802168a:	bf00      	nop
+ 802168c:	2401a5e4 	.word	0x2401a5e4
+
+08021690 <rand>:
+ 8021690:	4b16      	ldr	r3, [pc, #88]	; (80216ec <rand+0x5c>)
+ 8021692:	b510      	push	{r4, lr}
+ 8021694:	681c      	ldr	r4, [r3, #0]
+ 8021696:	6b23      	ldr	r3, [r4, #48]	; 0x30
+ 8021698:	b9b3      	cbnz	r3, 80216c8 <rand+0x38>
+ 802169a:	2018      	movs	r0, #24
+ 802169c:	f000 fc1c 	bl	8021ed8 <malloc>
+ 80216a0:	4602      	mov	r2, r0
+ 80216a2:	6320      	str	r0, [r4, #48]	; 0x30
+ 80216a4:	b920      	cbnz	r0, 80216b0 <rand+0x20>
+ 80216a6:	4b12      	ldr	r3, [pc, #72]	; (80216f0 <rand+0x60>)
+ 80216a8:	4812      	ldr	r0, [pc, #72]	; (80216f4 <rand+0x64>)
+ 80216aa:	2152      	movs	r1, #82	; 0x52
+ 80216ac:	f000 fbaa 	bl	8021e04 <__assert_func>
+ 80216b0:	4911      	ldr	r1, [pc, #68]	; (80216f8 <rand+0x68>)
+ 80216b2:	4b12      	ldr	r3, [pc, #72]	; (80216fc <rand+0x6c>)
+ 80216b4:	e9c0 1300 	strd	r1, r3, [r0]
+ 80216b8:	4b11      	ldr	r3, [pc, #68]	; (8021700 <rand+0x70>)
+ 80216ba:	6083      	str	r3, [r0, #8]
+ 80216bc:	230b      	movs	r3, #11
+ 80216be:	8183      	strh	r3, [r0, #12]
+ 80216c0:	2100      	movs	r1, #0
+ 80216c2:	2001      	movs	r0, #1
+ 80216c4:	e9c2 0104 	strd	r0, r1, [r2, #16]
+ 80216c8:	6b21      	ldr	r1, [r4, #48]	; 0x30
+ 80216ca:	480e      	ldr	r0, [pc, #56]	; (8021704 <rand+0x74>)
+ 80216cc:	690b      	ldr	r3, [r1, #16]
+ 80216ce:	694c      	ldr	r4, [r1, #20]
+ 80216d0:	4a0d      	ldr	r2, [pc, #52]	; (8021708 <rand+0x78>)
+ 80216d2:	4358      	muls	r0, r3
+ 80216d4:	fb02 0004 	mla	r0, r2, r4, r0
+ 80216d8:	fba3 3202 	umull	r3, r2, r3, r2
+ 80216dc:	3301      	adds	r3, #1
+ 80216de:	eb40 0002 	adc.w	r0, r0, r2
+ 80216e2:	e9c1 3004 	strd	r3, r0, [r1, #16]
+ 80216e6:	f020 4000 	bic.w	r0, r0, #2147483648	; 0x80000000
+ 80216ea:	bd10      	pop	{r4, pc}
+ 80216ec:	240000a0 	.word	0x240000a0
+ 80216f0:	08026d08 	.word	0x08026d08
+ 80216f4:	08026d1f 	.word	0x08026d1f
+ 80216f8:	abcd330e 	.word	0xabcd330e
+ 80216fc:	e66d1234 	.word	0xe66d1234
+ 8021700:	0005deec 	.word	0x0005deec
+ 8021704:	5851f42d 	.word	0x5851f42d
+ 8021708:	4c957f2d 	.word	0x4c957f2d
+
+0802170c <_strtoul_l.constprop.0>:
+ 802170c:	e92d 43f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, lr}
+ 8021710:	4f36      	ldr	r7, [pc, #216]	; (80217ec <_strtoul_l.constprop.0+0xe0>)
+ 8021712:	4686      	mov	lr, r0
+ 8021714:	460d      	mov	r5, r1
+ 8021716:	4628      	mov	r0, r5
+ 8021718:	f815 4b01 	ldrb.w	r4, [r5], #1
+ 802171c:	5d3e      	ldrb	r6, [r7, r4]
+ 802171e:	f016 0608 	ands.w	r6, r6, #8
+ 8021722:	d1f8      	bne.n	8021716 <_strtoul_l.constprop.0+0xa>
+ 8021724:	2c2d      	cmp	r4, #45	; 0x2d
+ 8021726:	d130      	bne.n	802178a <_strtoul_l.constprop.0+0x7e>
+ 8021728:	782c      	ldrb	r4, [r5, #0]
+ 802172a:	2601      	movs	r6, #1
+ 802172c:	1c85      	adds	r5, r0, #2
+ 802172e:	2b00      	cmp	r3, #0
+ 8021730:	d057      	beq.n	80217e2 <_strtoul_l.constprop.0+0xd6>
+ 8021732:	2b10      	cmp	r3, #16
+ 8021734:	d109      	bne.n	802174a <_strtoul_l.constprop.0+0x3e>
+ 8021736:	2c30      	cmp	r4, #48	; 0x30
+ 8021738:	d107      	bne.n	802174a <_strtoul_l.constprop.0+0x3e>
+ 802173a:	7828      	ldrb	r0, [r5, #0]
+ 802173c:	f000 00df 	and.w	r0, r0, #223	; 0xdf
+ 8021740:	2858      	cmp	r0, #88	; 0x58
+ 8021742:	d149      	bne.n	80217d8 <_strtoul_l.constprop.0+0xcc>
+ 8021744:	786c      	ldrb	r4, [r5, #1]
+ 8021746:	2310      	movs	r3, #16
+ 8021748:	3502      	adds	r5, #2
+ 802174a:	f04f 38ff 	mov.w	r8, #4294967295
+ 802174e:	2700      	movs	r7, #0
+ 8021750:	fbb8 f8f3 	udiv	r8, r8, r3
+ 8021754:	fb03 f908 	mul.w	r9, r3, r8
+ 8021758:	ea6f 0909 	mvn.w	r9, r9
+ 802175c:	4638      	mov	r0, r7
+ 802175e:	f1a4 0c30 	sub.w	ip, r4, #48	; 0x30
+ 8021762:	f1bc 0f09 	cmp.w	ip, #9
+ 8021766:	d815      	bhi.n	8021794 <_strtoul_l.constprop.0+0x88>
+ 8021768:	4664      	mov	r4, ip
+ 802176a:	42a3      	cmp	r3, r4
+ 802176c:	dd23      	ble.n	80217b6 <_strtoul_l.constprop.0+0xaa>
+ 802176e:	f1b7 3fff 	cmp.w	r7, #4294967295
+ 8021772:	d007      	beq.n	8021784 <_strtoul_l.constprop.0+0x78>
+ 8021774:	4580      	cmp	r8, r0
+ 8021776:	d31b      	bcc.n	80217b0 <_strtoul_l.constprop.0+0xa4>
+ 8021778:	d101      	bne.n	802177e <_strtoul_l.constprop.0+0x72>
+ 802177a:	45a1      	cmp	r9, r4
+ 802177c:	db18      	blt.n	80217b0 <_strtoul_l.constprop.0+0xa4>
+ 802177e:	fb00 4003 	mla	r0, r0, r3, r4
+ 8021782:	2701      	movs	r7, #1
+ 8021784:	f815 4b01 	ldrb.w	r4, [r5], #1
+ 8021788:	e7e9      	b.n	802175e <_strtoul_l.constprop.0+0x52>
+ 802178a:	2c2b      	cmp	r4, #43	; 0x2b
+ 802178c:	bf04      	itt	eq
+ 802178e:	782c      	ldrbeq	r4, [r5, #0]
+ 8021790:	1c85      	addeq	r5, r0, #2
+ 8021792:	e7cc      	b.n	802172e <_strtoul_l.constprop.0+0x22>
+ 8021794:	f1a4 0c41 	sub.w	ip, r4, #65	; 0x41
+ 8021798:	f1bc 0f19 	cmp.w	ip, #25
+ 802179c:	d801      	bhi.n	80217a2 <_strtoul_l.constprop.0+0x96>
+ 802179e:	3c37      	subs	r4, #55	; 0x37
+ 80217a0:	e7e3      	b.n	802176a <_strtoul_l.constprop.0+0x5e>
+ 80217a2:	f1a4 0c61 	sub.w	ip, r4, #97	; 0x61
+ 80217a6:	f1bc 0f19 	cmp.w	ip, #25
+ 80217aa:	d804      	bhi.n	80217b6 <_strtoul_l.constprop.0+0xaa>
+ 80217ac:	3c57      	subs	r4, #87	; 0x57
+ 80217ae:	e7dc      	b.n	802176a <_strtoul_l.constprop.0+0x5e>
+ 80217b0:	f04f 37ff 	mov.w	r7, #4294967295
+ 80217b4:	e7e6      	b.n	8021784 <_strtoul_l.constprop.0+0x78>
+ 80217b6:	1c7b      	adds	r3, r7, #1
+ 80217b8:	d106      	bne.n	80217c8 <_strtoul_l.constprop.0+0xbc>
+ 80217ba:	2322      	movs	r3, #34	; 0x22
+ 80217bc:	f8ce 3000 	str.w	r3, [lr]
+ 80217c0:	4638      	mov	r0, r7
+ 80217c2:	b932      	cbnz	r2, 80217d2 <_strtoul_l.constprop.0+0xc6>
+ 80217c4:	e8bd 83f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, pc}
+ 80217c8:	b106      	cbz	r6, 80217cc <_strtoul_l.constprop.0+0xc0>
+ 80217ca:	4240      	negs	r0, r0
+ 80217cc:	2a00      	cmp	r2, #0
+ 80217ce:	d0f9      	beq.n	80217c4 <_strtoul_l.constprop.0+0xb8>
+ 80217d0:	b107      	cbz	r7, 80217d4 <_strtoul_l.constprop.0+0xc8>
+ 80217d2:	1e69      	subs	r1, r5, #1
+ 80217d4:	6011      	str	r1, [r2, #0]
+ 80217d6:	e7f5      	b.n	80217c4 <_strtoul_l.constprop.0+0xb8>
+ 80217d8:	2430      	movs	r4, #48	; 0x30
+ 80217da:	2b00      	cmp	r3, #0
+ 80217dc:	d1b5      	bne.n	802174a <_strtoul_l.constprop.0+0x3e>
+ 80217de:	2308      	movs	r3, #8
+ 80217e0:	e7b3      	b.n	802174a <_strtoul_l.constprop.0+0x3e>
+ 80217e2:	2c30      	cmp	r4, #48	; 0x30
+ 80217e4:	d0a9      	beq.n	802173a <_strtoul_l.constprop.0+0x2e>
+ 80217e6:	230a      	movs	r3, #10
+ 80217e8:	e7af      	b.n	802174a <_strtoul_l.constprop.0+0x3e>
+ 80217ea:	bf00      	nop
+ 80217ec:	08026d78 	.word	0x08026d78
+
+080217f0 <strtoul>:
+ 80217f0:	4613      	mov	r3, r2
+ 80217f2:	460a      	mov	r2, r1
+ 80217f4:	4601      	mov	r1, r0
+ 80217f6:	4802      	ldr	r0, [pc, #8]	; (8021800 <strtoul+0x10>)
+ 80217f8:	6800      	ldr	r0, [r0, #0]
+ 80217fa:	f7ff bf87 	b.w	802170c <_strtoul_l.constprop.0>
+ 80217fe:	bf00      	nop
+ 8021800:	240000a0 	.word	0x240000a0
+
+08021804 <std>:
+ 8021804:	2300      	movs	r3, #0
+ 8021806:	b510      	push	{r4, lr}
+ 8021808:	4604      	mov	r4, r0
+ 802180a:	e9c0 3300 	strd	r3, r3, [r0]
+ 802180e:	e9c0 3304 	strd	r3, r3, [r0, #16]
+ 8021812:	6083      	str	r3, [r0, #8]
+ 8021814:	8181      	strh	r1, [r0, #12]
+ 8021816:	6643      	str	r3, [r0, #100]	; 0x64
+ 8021818:	81c2      	strh	r2, [r0, #14]
+ 802181a:	6183      	str	r3, [r0, #24]
+ 802181c:	4619      	mov	r1, r3
+ 802181e:	2208      	movs	r2, #8
+ 8021820:	305c      	adds	r0, #92	; 0x5c
+ 8021822:	f000 fa5d 	bl	8021ce0 <memset>
+ 8021826:	4b0d      	ldr	r3, [pc, #52]	; (802185c <std+0x58>)
+ 8021828:	6263      	str	r3, [r4, #36]	; 0x24
+ 802182a:	4b0d      	ldr	r3, [pc, #52]	; (8021860 <std+0x5c>)
+ 802182c:	62a3      	str	r3, [r4, #40]	; 0x28
+ 802182e:	4b0d      	ldr	r3, [pc, #52]	; (8021864 <std+0x60>)
+ 8021830:	62e3      	str	r3, [r4, #44]	; 0x2c
+ 8021832:	4b0d      	ldr	r3, [pc, #52]	; (8021868 <std+0x64>)
+ 8021834:	6323      	str	r3, [r4, #48]	; 0x30
+ 8021836:	4b0d      	ldr	r3, [pc, #52]	; (802186c <std+0x68>)
+ 8021838:	6224      	str	r4, [r4, #32]
+ 802183a:	429c      	cmp	r4, r3
+ 802183c:	d006      	beq.n	802184c <std+0x48>
+ 802183e:	f103 0268 	add.w	r2, r3, #104	; 0x68
+ 8021842:	4294      	cmp	r4, r2
+ 8021844:	d002      	beq.n	802184c <std+0x48>
+ 8021846:	33d0      	adds	r3, #208	; 0xd0
+ 8021848:	429c      	cmp	r4, r3
+ 802184a:	d105      	bne.n	8021858 <std+0x54>
+ 802184c:	f104 0058 	add.w	r0, r4, #88	; 0x58
+ 8021850:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
+ 8021854:	f000 bac4 	b.w	8021de0 <__retarget_lock_init_recursive>
+ 8021858:	bd10      	pop	{r4, pc}
+ 802185a:	bf00      	nop
+ 802185c:	08021add 	.word	0x08021add
+ 8021860:	08021aff 	.word	0x08021aff
+ 8021864:	08021b37 	.word	0x08021b37
+ 8021868:	08021b5b 	.word	0x08021b5b
+ 802186c:	2401a5e8 	.word	0x2401a5e8
+
+08021870 <stdio_exit_handler>:
+ 8021870:	4a02      	ldr	r2, [pc, #8]	; (802187c <stdio_exit_handler+0xc>)
+ 8021872:	4903      	ldr	r1, [pc, #12]	; (8021880 <stdio_exit_handler+0x10>)
+ 8021874:	4803      	ldr	r0, [pc, #12]	; (8021884 <stdio_exit_handler+0x14>)
+ 8021876:	f000 b869 	b.w	802194c <_fwalk_sglue>
+ 802187a:	bf00      	nop
+ 802187c:	24000048 	.word	0x24000048
+ 8021880:	080229a5 	.word	0x080229a5
+ 8021884:	24000054 	.word	0x24000054
+
+08021888 <cleanup_stdio>:
+ 8021888:	6841      	ldr	r1, [r0, #4]
+ 802188a:	4b0c      	ldr	r3, [pc, #48]	; (80218bc <cleanup_stdio+0x34>)
+ 802188c:	4299      	cmp	r1, r3
+ 802188e:	b510      	push	{r4, lr}
+ 8021890:	4604      	mov	r4, r0
+ 8021892:	d001      	beq.n	8021898 <cleanup_stdio+0x10>
+ 8021894:	f001 f886 	bl	80229a4 <_fflush_r>
+ 8021898:	68a1      	ldr	r1, [r4, #8]
+ 802189a:	4b09      	ldr	r3, [pc, #36]	; (80218c0 <cleanup_stdio+0x38>)
+ 802189c:	4299      	cmp	r1, r3
+ 802189e:	d002      	beq.n	80218a6 <cleanup_stdio+0x1e>
+ 80218a0:	4620      	mov	r0, r4
+ 80218a2:	f001 f87f 	bl	80229a4 <_fflush_r>
+ 80218a6:	68e1      	ldr	r1, [r4, #12]
+ 80218a8:	4b06      	ldr	r3, [pc, #24]	; (80218c4 <cleanup_stdio+0x3c>)
+ 80218aa:	4299      	cmp	r1, r3
+ 80218ac:	d004      	beq.n	80218b8 <cleanup_stdio+0x30>
+ 80218ae:	4620      	mov	r0, r4
+ 80218b0:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
+ 80218b4:	f001 b876 	b.w	80229a4 <_fflush_r>
+ 80218b8:	bd10      	pop	{r4, pc}
+ 80218ba:	bf00      	nop
+ 80218bc:	2401a5e8 	.word	0x2401a5e8
+ 80218c0:	2401a650 	.word	0x2401a650
+ 80218c4:	2401a6b8 	.word	0x2401a6b8
+
+080218c8 <global_stdio_init.part.0>:
+ 80218c8:	b510      	push	{r4, lr}
+ 80218ca:	4b0b      	ldr	r3, [pc, #44]	; (80218f8 <global_stdio_init.part.0+0x30>)
+ 80218cc:	4c0b      	ldr	r4, [pc, #44]	; (80218fc <global_stdio_init.part.0+0x34>)
+ 80218ce:	4a0c      	ldr	r2, [pc, #48]	; (8021900 <global_stdio_init.part.0+0x38>)
+ 80218d0:	601a      	str	r2, [r3, #0]
+ 80218d2:	4620      	mov	r0, r4
+ 80218d4:	2200      	movs	r2, #0
+ 80218d6:	2104      	movs	r1, #4
+ 80218d8:	f7ff ff94 	bl	8021804 <std>
+ 80218dc:	f104 0068 	add.w	r0, r4, #104	; 0x68
+ 80218e0:	2201      	movs	r2, #1
+ 80218e2:	2109      	movs	r1, #9
+ 80218e4:	f7ff ff8e 	bl	8021804 <std>
+ 80218e8:	f104 00d0 	add.w	r0, r4, #208	; 0xd0
+ 80218ec:	2202      	movs	r2, #2
+ 80218ee:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
+ 80218f2:	2112      	movs	r1, #18
+ 80218f4:	f7ff bf86 	b.w	8021804 <std>
+ 80218f8:	2401a720 	.word	0x2401a720
+ 80218fc:	2401a5e8 	.word	0x2401a5e8
+ 8021900:	08021871 	.word	0x08021871
+
+08021904 <__sfp_lock_acquire>:
+ 8021904:	4801      	ldr	r0, [pc, #4]	; (802190c <__sfp_lock_acquire+0x8>)
+ 8021906:	f000 ba6c 	b.w	8021de2 <__retarget_lock_acquire_recursive>
+ 802190a:	bf00      	nop
+ 802190c:	2401a725 	.word	0x2401a725
+
+08021910 <__sfp_lock_release>:
+ 8021910:	4801      	ldr	r0, [pc, #4]	; (8021918 <__sfp_lock_release+0x8>)
+ 8021912:	f000 ba67 	b.w	8021de4 <__retarget_lock_release_recursive>
+ 8021916:	bf00      	nop
+ 8021918:	2401a725 	.word	0x2401a725
+
+0802191c <__sinit>:
+ 802191c:	b510      	push	{r4, lr}
+ 802191e:	4604      	mov	r4, r0
+ 8021920:	f7ff fff0 	bl	8021904 <__sfp_lock_acquire>
+ 8021924:	6a23      	ldr	r3, [r4, #32]
+ 8021926:	b11b      	cbz	r3, 8021930 <__sinit+0x14>
+ 8021928:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
+ 802192c:	f7ff bff0 	b.w	8021910 <__sfp_lock_release>
+ 8021930:	4b04      	ldr	r3, [pc, #16]	; (8021944 <__sinit+0x28>)
+ 8021932:	6223      	str	r3, [r4, #32]
+ 8021934:	4b04      	ldr	r3, [pc, #16]	; (8021948 <__sinit+0x2c>)
+ 8021936:	681b      	ldr	r3, [r3, #0]
+ 8021938:	2b00      	cmp	r3, #0
+ 802193a:	d1f5      	bne.n	8021928 <__sinit+0xc>
+ 802193c:	f7ff ffc4 	bl	80218c8 <global_stdio_init.part.0>
+ 8021940:	e7f2      	b.n	8021928 <__sinit+0xc>
+ 8021942:	bf00      	nop
+ 8021944:	08021889 	.word	0x08021889
+ 8021948:	2401a720 	.word	0x2401a720
+
+0802194c <_fwalk_sglue>:
+ 802194c:	e92d 43f8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
+ 8021950:	4607      	mov	r7, r0
+ 8021952:	4688      	mov	r8, r1
+ 8021954:	4614      	mov	r4, r2
+ 8021956:	2600      	movs	r6, #0
+ 8021958:	e9d4 9501 	ldrd	r9, r5, [r4, #4]
+ 802195c:	f1b9 0901 	subs.w	r9, r9, #1
+ 8021960:	d505      	bpl.n	802196e <_fwalk_sglue+0x22>
+ 8021962:	6824      	ldr	r4, [r4, #0]
+ 8021964:	2c00      	cmp	r4, #0
+ 8021966:	d1f7      	bne.n	8021958 <_fwalk_sglue+0xc>
+ 8021968:	4630      	mov	r0, r6
+ 802196a:	e8bd 83f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
+ 802196e:	89ab      	ldrh	r3, [r5, #12]
+ 8021970:	2b01      	cmp	r3, #1
+ 8021972:	d907      	bls.n	8021984 <_fwalk_sglue+0x38>
+ 8021974:	f9b5 300e 	ldrsh.w	r3, [r5, #14]
+ 8021978:	3301      	adds	r3, #1
+ 802197a:	d003      	beq.n	8021984 <_fwalk_sglue+0x38>
+ 802197c:	4629      	mov	r1, r5
+ 802197e:	4638      	mov	r0, r7
+ 8021980:	47c0      	blx	r8
+ 8021982:	4306      	orrs	r6, r0
+ 8021984:	3568      	adds	r5, #104	; 0x68
+ 8021986:	e7e9      	b.n	802195c <_fwalk_sglue+0x10>
+
+08021988 <iprintf>:
+ 8021988:	b40f      	push	{r0, r1, r2, r3}
+ 802198a:	b507      	push	{r0, r1, r2, lr}
+ 802198c:	4906      	ldr	r1, [pc, #24]	; (80219a8 <iprintf+0x20>)
+ 802198e:	ab04      	add	r3, sp, #16
+ 8021990:	6808      	ldr	r0, [r1, #0]
+ 8021992:	f853 2b04 	ldr.w	r2, [r3], #4
+ 8021996:	6881      	ldr	r1, [r0, #8]
+ 8021998:	9301      	str	r3, [sp, #4]
+ 802199a:	f000 fcd3 	bl	8022344 <_vfiprintf_r>
+ 802199e:	b003      	add	sp, #12
+ 80219a0:	f85d eb04 	ldr.w	lr, [sp], #4
+ 80219a4:	b004      	add	sp, #16
+ 80219a6:	4770      	bx	lr
+ 80219a8:	240000a0 	.word	0x240000a0
+
+080219ac <putchar>:
+ 80219ac:	4b02      	ldr	r3, [pc, #8]	; (80219b8 <putchar+0xc>)
+ 80219ae:	4601      	mov	r1, r0
+ 80219b0:	6818      	ldr	r0, [r3, #0]
+ 80219b2:	6882      	ldr	r2, [r0, #8]
+ 80219b4:	f001 b892 	b.w	8022adc <_putc_r>
+ 80219b8:	240000a0 	.word	0x240000a0
+
+080219bc <_puts_r>:
+ 80219bc:	6a03      	ldr	r3, [r0, #32]
+ 80219be:	b570      	push	{r4, r5, r6, lr}
+ 80219c0:	6884      	ldr	r4, [r0, #8]
+ 80219c2:	4605      	mov	r5, r0
+ 80219c4:	460e      	mov	r6, r1
+ 80219c6:	b90b      	cbnz	r3, 80219cc <_puts_r+0x10>
+ 80219c8:	f7ff ffa8 	bl	802191c <__sinit>
+ 80219cc:	6e63      	ldr	r3, [r4, #100]	; 0x64
+ 80219ce:	07db      	lsls	r3, r3, #31
+ 80219d0:	d405      	bmi.n	80219de <_puts_r+0x22>
+ 80219d2:	89a3      	ldrh	r3, [r4, #12]
+ 80219d4:	0598      	lsls	r0, r3, #22
+ 80219d6:	d402      	bmi.n	80219de <_puts_r+0x22>
+ 80219d8:	6da0      	ldr	r0, [r4, #88]	; 0x58
+ 80219da:	f000 fa02 	bl	8021de2 <__retarget_lock_acquire_recursive>
+ 80219de:	89a3      	ldrh	r3, [r4, #12]
+ 80219e0:	0719      	lsls	r1, r3, #28
+ 80219e2:	d513      	bpl.n	8021a0c <_puts_r+0x50>
+ 80219e4:	6923      	ldr	r3, [r4, #16]
+ 80219e6:	b18b      	cbz	r3, 8021a0c <_puts_r+0x50>
+ 80219e8:	3e01      	subs	r6, #1
+ 80219ea:	68a3      	ldr	r3, [r4, #8]
+ 80219ec:	f816 1f01 	ldrb.w	r1, [r6, #1]!
+ 80219f0:	3b01      	subs	r3, #1
+ 80219f2:	60a3      	str	r3, [r4, #8]
+ 80219f4:	b9e9      	cbnz	r1, 8021a32 <_puts_r+0x76>
+ 80219f6:	2b00      	cmp	r3, #0
+ 80219f8:	da2e      	bge.n	8021a58 <_puts_r+0x9c>
+ 80219fa:	4622      	mov	r2, r4
+ 80219fc:	210a      	movs	r1, #10
+ 80219fe:	4628      	mov	r0, r5
+ 8021a00:	f000 f8af 	bl	8021b62 <__swbuf_r>
+ 8021a04:	3001      	adds	r0, #1
+ 8021a06:	d007      	beq.n	8021a18 <_puts_r+0x5c>
+ 8021a08:	250a      	movs	r5, #10
+ 8021a0a:	e007      	b.n	8021a1c <_puts_r+0x60>
+ 8021a0c:	4621      	mov	r1, r4
+ 8021a0e:	4628      	mov	r0, r5
+ 8021a10:	f000 f8e4 	bl	8021bdc <__swsetup_r>
+ 8021a14:	2800      	cmp	r0, #0
+ 8021a16:	d0e7      	beq.n	80219e8 <_puts_r+0x2c>
+ 8021a18:	f04f 35ff 	mov.w	r5, #4294967295
+ 8021a1c:	6e63      	ldr	r3, [r4, #100]	; 0x64
+ 8021a1e:	07da      	lsls	r2, r3, #31
+ 8021a20:	d405      	bmi.n	8021a2e <_puts_r+0x72>
+ 8021a22:	89a3      	ldrh	r3, [r4, #12]
+ 8021a24:	059b      	lsls	r3, r3, #22
+ 8021a26:	d402      	bmi.n	8021a2e <_puts_r+0x72>
+ 8021a28:	6da0      	ldr	r0, [r4, #88]	; 0x58
+ 8021a2a:	f000 f9db 	bl	8021de4 <__retarget_lock_release_recursive>
+ 8021a2e:	4628      	mov	r0, r5
+ 8021a30:	bd70      	pop	{r4, r5, r6, pc}
+ 8021a32:	2b00      	cmp	r3, #0
+ 8021a34:	da04      	bge.n	8021a40 <_puts_r+0x84>
+ 8021a36:	69a2      	ldr	r2, [r4, #24]
+ 8021a38:	429a      	cmp	r2, r3
+ 8021a3a:	dc06      	bgt.n	8021a4a <_puts_r+0x8e>
+ 8021a3c:	290a      	cmp	r1, #10
+ 8021a3e:	d004      	beq.n	8021a4a <_puts_r+0x8e>
+ 8021a40:	6823      	ldr	r3, [r4, #0]
+ 8021a42:	1c5a      	adds	r2, r3, #1
+ 8021a44:	6022      	str	r2, [r4, #0]
+ 8021a46:	7019      	strb	r1, [r3, #0]
+ 8021a48:	e7cf      	b.n	80219ea <_puts_r+0x2e>
+ 8021a4a:	4622      	mov	r2, r4
+ 8021a4c:	4628      	mov	r0, r5
+ 8021a4e:	f000 f888 	bl	8021b62 <__swbuf_r>
+ 8021a52:	3001      	adds	r0, #1
+ 8021a54:	d1c9      	bne.n	80219ea <_puts_r+0x2e>
+ 8021a56:	e7df      	b.n	8021a18 <_puts_r+0x5c>
+ 8021a58:	6823      	ldr	r3, [r4, #0]
+ 8021a5a:	250a      	movs	r5, #10
+ 8021a5c:	1c5a      	adds	r2, r3, #1
+ 8021a5e:	6022      	str	r2, [r4, #0]
+ 8021a60:	701d      	strb	r5, [r3, #0]
+ 8021a62:	e7db      	b.n	8021a1c <_puts_r+0x60>
+
+08021a64 <puts>:
+ 8021a64:	4b02      	ldr	r3, [pc, #8]	; (8021a70 <puts+0xc>)
+ 8021a66:	4601      	mov	r1, r0
+ 8021a68:	6818      	ldr	r0, [r3, #0]
+ 8021a6a:	f7ff bfa7 	b.w	80219bc <_puts_r>
+ 8021a6e:	bf00      	nop
+ 8021a70:	240000a0 	.word	0x240000a0
+
+08021a74 <sniprintf>:
+ 8021a74:	b40c      	push	{r2, r3}
+ 8021a76:	b530      	push	{r4, r5, lr}
+ 8021a78:	4b17      	ldr	r3, [pc, #92]	; (8021ad8 <sniprintf+0x64>)
+ 8021a7a:	1e0c      	subs	r4, r1, #0
+ 8021a7c:	681d      	ldr	r5, [r3, #0]
+ 8021a7e:	b09d      	sub	sp, #116	; 0x74
+ 8021a80:	da08      	bge.n	8021a94 <sniprintf+0x20>
+ 8021a82:	238b      	movs	r3, #139	; 0x8b
+ 8021a84:	602b      	str	r3, [r5, #0]
+ 8021a86:	f04f 30ff 	mov.w	r0, #4294967295
+ 8021a8a:	b01d      	add	sp, #116	; 0x74
+ 8021a8c:	e8bd 4030 	ldmia.w	sp!, {r4, r5, lr}
+ 8021a90:	b002      	add	sp, #8
+ 8021a92:	4770      	bx	lr
+ 8021a94:	f44f 7302 	mov.w	r3, #520	; 0x208
+ 8021a98:	f8ad 3014 	strh.w	r3, [sp, #20]
+ 8021a9c:	bf14      	ite	ne
+ 8021a9e:	f104 33ff 	addne.w	r3, r4, #4294967295
+ 8021aa2:	4623      	moveq	r3, r4
+ 8021aa4:	9304      	str	r3, [sp, #16]
+ 8021aa6:	9307      	str	r3, [sp, #28]
+ 8021aa8:	f64f 73ff 	movw	r3, #65535	; 0xffff
+ 8021aac:	9002      	str	r0, [sp, #8]
+ 8021aae:	9006      	str	r0, [sp, #24]
+ 8021ab0:	f8ad 3016 	strh.w	r3, [sp, #22]
+ 8021ab4:	9a20      	ldr	r2, [sp, #128]	; 0x80
+ 8021ab6:	ab21      	add	r3, sp, #132	; 0x84
+ 8021ab8:	a902      	add	r1, sp, #8
+ 8021aba:	4628      	mov	r0, r5
+ 8021abc:	9301      	str	r3, [sp, #4]
+ 8021abe:	f000 fb19 	bl	80220f4 <_svfiprintf_r>
+ 8021ac2:	1c43      	adds	r3, r0, #1
+ 8021ac4:	bfbc      	itt	lt
+ 8021ac6:	238b      	movlt	r3, #139	; 0x8b
+ 8021ac8:	602b      	strlt	r3, [r5, #0]
+ 8021aca:	2c00      	cmp	r4, #0
+ 8021acc:	d0dd      	beq.n	8021a8a <sniprintf+0x16>
+ 8021ace:	9b02      	ldr	r3, [sp, #8]
+ 8021ad0:	2200      	movs	r2, #0
+ 8021ad2:	701a      	strb	r2, [r3, #0]
+ 8021ad4:	e7d9      	b.n	8021a8a <sniprintf+0x16>
+ 8021ad6:	bf00      	nop
+ 8021ad8:	240000a0 	.word	0x240000a0
+
+08021adc <__sread>:
+ 8021adc:	b510      	push	{r4, lr}
+ 8021ade:	460c      	mov	r4, r1
+ 8021ae0:	f9b1 100e 	ldrsh.w	r1, [r1, #14]
+ 8021ae4:	f000 f934 	bl	8021d50 <_read_r>
+ 8021ae8:	2800      	cmp	r0, #0
+ 8021aea:	bfab      	itete	ge
+ 8021aec:	6d63      	ldrge	r3, [r4, #84]	; 0x54
+ 8021aee:	89a3      	ldrhlt	r3, [r4, #12]
+ 8021af0:	181b      	addge	r3, r3, r0
+ 8021af2:	f423 5380 	biclt.w	r3, r3, #4096	; 0x1000
+ 8021af6:	bfac      	ite	ge
+ 8021af8:	6563      	strge	r3, [r4, #84]	; 0x54
+ 8021afa:	81a3      	strhlt	r3, [r4, #12]
+ 8021afc:	bd10      	pop	{r4, pc}
+
+08021afe <__swrite>:
+ 8021afe:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
+ 8021b02:	461f      	mov	r7, r3
+ 8021b04:	898b      	ldrh	r3, [r1, #12]
+ 8021b06:	05db      	lsls	r3, r3, #23
+ 8021b08:	4605      	mov	r5, r0
+ 8021b0a:	460c      	mov	r4, r1
+ 8021b0c:	4616      	mov	r6, r2
+ 8021b0e:	d505      	bpl.n	8021b1c <__swrite+0x1e>
+ 8021b10:	f9b1 100e 	ldrsh.w	r1, [r1, #14]
+ 8021b14:	2302      	movs	r3, #2
+ 8021b16:	2200      	movs	r2, #0
+ 8021b18:	f000 f908 	bl	8021d2c <_lseek_r>
+ 8021b1c:	89a3      	ldrh	r3, [r4, #12]
+ 8021b1e:	f9b4 100e 	ldrsh.w	r1, [r4, #14]
+ 8021b22:	f423 5380 	bic.w	r3, r3, #4096	; 0x1000
+ 8021b26:	81a3      	strh	r3, [r4, #12]
+ 8021b28:	4632      	mov	r2, r6
+ 8021b2a:	463b      	mov	r3, r7
+ 8021b2c:	4628      	mov	r0, r5
+ 8021b2e:	e8bd 41f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, lr}
+ 8021b32:	f000 b91f 	b.w	8021d74 <_write_r>
+
+08021b36 <__sseek>:
+ 8021b36:	b510      	push	{r4, lr}
+ 8021b38:	460c      	mov	r4, r1
+ 8021b3a:	f9b1 100e 	ldrsh.w	r1, [r1, #14]
+ 8021b3e:	f000 f8f5 	bl	8021d2c <_lseek_r>
+ 8021b42:	1c43      	adds	r3, r0, #1
+ 8021b44:	89a3      	ldrh	r3, [r4, #12]
+ 8021b46:	bf15      	itete	ne
+ 8021b48:	6560      	strne	r0, [r4, #84]	; 0x54
+ 8021b4a:	f423 5380 	biceq.w	r3, r3, #4096	; 0x1000
+ 8021b4e:	f443 5380 	orrne.w	r3, r3, #4096	; 0x1000
+ 8021b52:	81a3      	strheq	r3, [r4, #12]
+ 8021b54:	bf18      	it	ne
+ 8021b56:	81a3      	strhne	r3, [r4, #12]
+ 8021b58:	bd10      	pop	{r4, pc}
+
+08021b5a <__sclose>:
+ 8021b5a:	f9b1 100e 	ldrsh.w	r1, [r1, #14]
+ 8021b5e:	f000 b8d5 	b.w	8021d0c <_close_r>
+
+08021b62 <__swbuf_r>:
+ 8021b62:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
+ 8021b64:	460e      	mov	r6, r1
+ 8021b66:	4614      	mov	r4, r2
+ 8021b68:	4605      	mov	r5, r0
+ 8021b6a:	b118      	cbz	r0, 8021b74 <__swbuf_r+0x12>
+ 8021b6c:	6a03      	ldr	r3, [r0, #32]
+ 8021b6e:	b90b      	cbnz	r3, 8021b74 <__swbuf_r+0x12>
+ 8021b70:	f7ff fed4 	bl	802191c <__sinit>
+ 8021b74:	69a3      	ldr	r3, [r4, #24]
+ 8021b76:	60a3      	str	r3, [r4, #8]
+ 8021b78:	89a3      	ldrh	r3, [r4, #12]
+ 8021b7a:	071a      	lsls	r2, r3, #28
+ 8021b7c:	d525      	bpl.n	8021bca <__swbuf_r+0x68>
+ 8021b7e:	6923      	ldr	r3, [r4, #16]
+ 8021b80:	b31b      	cbz	r3, 8021bca <__swbuf_r+0x68>
+ 8021b82:	6823      	ldr	r3, [r4, #0]
+ 8021b84:	6922      	ldr	r2, [r4, #16]
+ 8021b86:	1a98      	subs	r0, r3, r2
+ 8021b88:	6963      	ldr	r3, [r4, #20]
+ 8021b8a:	b2f6      	uxtb	r6, r6
+ 8021b8c:	4283      	cmp	r3, r0
+ 8021b8e:	4637      	mov	r7, r6
+ 8021b90:	dc04      	bgt.n	8021b9c <__swbuf_r+0x3a>
+ 8021b92:	4621      	mov	r1, r4
+ 8021b94:	4628      	mov	r0, r5
+ 8021b96:	f000 ff05 	bl	80229a4 <_fflush_r>
+ 8021b9a:	b9e0      	cbnz	r0, 8021bd6 <__swbuf_r+0x74>
+ 8021b9c:	68a3      	ldr	r3, [r4, #8]
+ 8021b9e:	3b01      	subs	r3, #1
+ 8021ba0:	60a3      	str	r3, [r4, #8]
+ 8021ba2:	6823      	ldr	r3, [r4, #0]
+ 8021ba4:	1c5a      	adds	r2, r3, #1
+ 8021ba6:	6022      	str	r2, [r4, #0]
+ 8021ba8:	701e      	strb	r6, [r3, #0]
+ 8021baa:	6962      	ldr	r2, [r4, #20]
+ 8021bac:	1c43      	adds	r3, r0, #1
+ 8021bae:	429a      	cmp	r2, r3
+ 8021bb0:	d004      	beq.n	8021bbc <__swbuf_r+0x5a>
+ 8021bb2:	89a3      	ldrh	r3, [r4, #12]
+ 8021bb4:	07db      	lsls	r3, r3, #31
+ 8021bb6:	d506      	bpl.n	8021bc6 <__swbuf_r+0x64>
+ 8021bb8:	2e0a      	cmp	r6, #10
+ 8021bba:	d104      	bne.n	8021bc6 <__swbuf_r+0x64>
+ 8021bbc:	4621      	mov	r1, r4
+ 8021bbe:	4628      	mov	r0, r5
+ 8021bc0:	f000 fef0 	bl	80229a4 <_fflush_r>
+ 8021bc4:	b938      	cbnz	r0, 8021bd6 <__swbuf_r+0x74>
+ 8021bc6:	4638      	mov	r0, r7
+ 8021bc8:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
+ 8021bca:	4621      	mov	r1, r4
+ 8021bcc:	4628      	mov	r0, r5
+ 8021bce:	f000 f805 	bl	8021bdc <__swsetup_r>
+ 8021bd2:	2800      	cmp	r0, #0
+ 8021bd4:	d0d5      	beq.n	8021b82 <__swbuf_r+0x20>
+ 8021bd6:	f04f 37ff 	mov.w	r7, #4294967295
+ 8021bda:	e7f4      	b.n	8021bc6 <__swbuf_r+0x64>
+
+08021bdc <__swsetup_r>:
+ 8021bdc:	b538      	push	{r3, r4, r5, lr}
+ 8021bde:	4b2a      	ldr	r3, [pc, #168]	; (8021c88 <__swsetup_r+0xac>)
+ 8021be0:	4605      	mov	r5, r0
+ 8021be2:	6818      	ldr	r0, [r3, #0]
+ 8021be4:	460c      	mov	r4, r1
+ 8021be6:	b118      	cbz	r0, 8021bf0 <__swsetup_r+0x14>
+ 8021be8:	6a03      	ldr	r3, [r0, #32]
+ 8021bea:	b90b      	cbnz	r3, 8021bf0 <__swsetup_r+0x14>
+ 8021bec:	f7ff fe96 	bl	802191c <__sinit>
+ 8021bf0:	89a3      	ldrh	r3, [r4, #12]
+ 8021bf2:	f9b4 200c 	ldrsh.w	r2, [r4, #12]
+ 8021bf6:	0718      	lsls	r0, r3, #28
+ 8021bf8:	d422      	bmi.n	8021c40 <__swsetup_r+0x64>
+ 8021bfa:	06d9      	lsls	r1, r3, #27
+ 8021bfc:	d407      	bmi.n	8021c0e <__swsetup_r+0x32>
+ 8021bfe:	2309      	movs	r3, #9
+ 8021c00:	602b      	str	r3, [r5, #0]
+ 8021c02:	f042 0340 	orr.w	r3, r2, #64	; 0x40
+ 8021c06:	81a3      	strh	r3, [r4, #12]
+ 8021c08:	f04f 30ff 	mov.w	r0, #4294967295
+ 8021c0c:	e034      	b.n	8021c78 <__swsetup_r+0x9c>
+ 8021c0e:	0758      	lsls	r0, r3, #29
+ 8021c10:	d512      	bpl.n	8021c38 <__swsetup_r+0x5c>
+ 8021c12:	6b61      	ldr	r1, [r4, #52]	; 0x34
+ 8021c14:	b141      	cbz	r1, 8021c28 <__swsetup_r+0x4c>
+ 8021c16:	f104 0344 	add.w	r3, r4, #68	; 0x44
+ 8021c1a:	4299      	cmp	r1, r3
+ 8021c1c:	d002      	beq.n	8021c24 <__swsetup_r+0x48>
+ 8021c1e:	4628      	mov	r0, r5
+ 8021c20:	f000 f90e 	bl	8021e40 <_free_r>
+ 8021c24:	2300      	movs	r3, #0
+ 8021c26:	6363      	str	r3, [r4, #52]	; 0x34
+ 8021c28:	89a3      	ldrh	r3, [r4, #12]
+ 8021c2a:	f023 0324 	bic.w	r3, r3, #36	; 0x24
+ 8021c2e:	81a3      	strh	r3, [r4, #12]
+ 8021c30:	2300      	movs	r3, #0
+ 8021c32:	6063      	str	r3, [r4, #4]
+ 8021c34:	6923      	ldr	r3, [r4, #16]
+ 8021c36:	6023      	str	r3, [r4, #0]
+ 8021c38:	89a3      	ldrh	r3, [r4, #12]
+ 8021c3a:	f043 0308 	orr.w	r3, r3, #8
+ 8021c3e:	81a3      	strh	r3, [r4, #12]
+ 8021c40:	6923      	ldr	r3, [r4, #16]
+ 8021c42:	b94b      	cbnz	r3, 8021c58 <__swsetup_r+0x7c>
+ 8021c44:	89a3      	ldrh	r3, [r4, #12]
+ 8021c46:	f403 7320 	and.w	r3, r3, #640	; 0x280
+ 8021c4a:	f5b3 7f00 	cmp.w	r3, #512	; 0x200
+ 8021c4e:	d003      	beq.n	8021c58 <__swsetup_r+0x7c>
+ 8021c50:	4621      	mov	r1, r4
+ 8021c52:	4628      	mov	r0, r5
+ 8021c54:	f000 ff06 	bl	8022a64 <__smakebuf_r>
+ 8021c58:	89a0      	ldrh	r0, [r4, #12]
+ 8021c5a:	f9b4 200c 	ldrsh.w	r2, [r4, #12]
+ 8021c5e:	f010 0301 	ands.w	r3, r0, #1
+ 8021c62:	d00a      	beq.n	8021c7a <__swsetup_r+0x9e>
+ 8021c64:	2300      	movs	r3, #0
+ 8021c66:	60a3      	str	r3, [r4, #8]
+ 8021c68:	6963      	ldr	r3, [r4, #20]
+ 8021c6a:	425b      	negs	r3, r3
+ 8021c6c:	61a3      	str	r3, [r4, #24]
+ 8021c6e:	6923      	ldr	r3, [r4, #16]
+ 8021c70:	b943      	cbnz	r3, 8021c84 <__swsetup_r+0xa8>
+ 8021c72:	f010 0080 	ands.w	r0, r0, #128	; 0x80
+ 8021c76:	d1c4      	bne.n	8021c02 <__swsetup_r+0x26>
+ 8021c78:	bd38      	pop	{r3, r4, r5, pc}
+ 8021c7a:	0781      	lsls	r1, r0, #30
+ 8021c7c:	bf58      	it	pl
+ 8021c7e:	6963      	ldrpl	r3, [r4, #20]
+ 8021c80:	60a3      	str	r3, [r4, #8]
+ 8021c82:	e7f4      	b.n	8021c6e <__swsetup_r+0x92>
+ 8021c84:	2000      	movs	r0, #0
+ 8021c86:	e7f7      	b.n	8021c78 <__swsetup_r+0x9c>
+ 8021c88:	240000a0 	.word	0x240000a0
+
+08021c8c <memcmp>:
+ 8021c8c:	b510      	push	{r4, lr}
+ 8021c8e:	3901      	subs	r1, #1
+ 8021c90:	4402      	add	r2, r0
+ 8021c92:	4290      	cmp	r0, r2
+ 8021c94:	d101      	bne.n	8021c9a <memcmp+0xe>
+ 8021c96:	2000      	movs	r0, #0
+ 8021c98:	e005      	b.n	8021ca6 <memcmp+0x1a>
+ 8021c9a:	7803      	ldrb	r3, [r0, #0]
+ 8021c9c:	f811 4f01 	ldrb.w	r4, [r1, #1]!
+ 8021ca0:	42a3      	cmp	r3, r4
+ 8021ca2:	d001      	beq.n	8021ca8 <memcmp+0x1c>
+ 8021ca4:	1b18      	subs	r0, r3, r4
+ 8021ca6:	bd10      	pop	{r4, pc}
+ 8021ca8:	3001      	adds	r0, #1
+ 8021caa:	e7f2      	b.n	8021c92 <memcmp+0x6>
+
+08021cac <memmove>:
+ 8021cac:	4288      	cmp	r0, r1
+ 8021cae:	b510      	push	{r4, lr}
+ 8021cb0:	eb01 0402 	add.w	r4, r1, r2
+ 8021cb4:	d902      	bls.n	8021cbc <memmove+0x10>
+ 8021cb6:	4284      	cmp	r4, r0
+ 8021cb8:	4623      	mov	r3, r4
+ 8021cba:	d807      	bhi.n	8021ccc <memmove+0x20>
+ 8021cbc:	1e43      	subs	r3, r0, #1
+ 8021cbe:	42a1      	cmp	r1, r4
+ 8021cc0:	d008      	beq.n	8021cd4 <memmove+0x28>
+ 8021cc2:	f811 2b01 	ldrb.w	r2, [r1], #1
+ 8021cc6:	f803 2f01 	strb.w	r2, [r3, #1]!
+ 8021cca:	e7f8      	b.n	8021cbe <memmove+0x12>
+ 8021ccc:	4402      	add	r2, r0
+ 8021cce:	4601      	mov	r1, r0
+ 8021cd0:	428a      	cmp	r2, r1
+ 8021cd2:	d100      	bne.n	8021cd6 <memmove+0x2a>
+ 8021cd4:	bd10      	pop	{r4, pc}
+ 8021cd6:	f813 4d01 	ldrb.w	r4, [r3, #-1]!
+ 8021cda:	f802 4d01 	strb.w	r4, [r2, #-1]!
+ 8021cde:	e7f7      	b.n	8021cd0 <memmove+0x24>
+
+08021ce0 <memset>:
+ 8021ce0:	4402      	add	r2, r0
+ 8021ce2:	4603      	mov	r3, r0
+ 8021ce4:	4293      	cmp	r3, r2
+ 8021ce6:	d100      	bne.n	8021cea <memset+0xa>
+ 8021ce8:	4770      	bx	lr
+ 8021cea:	f803 1b01 	strb.w	r1, [r3], #1
+ 8021cee:	e7f9      	b.n	8021ce4 <memset+0x4>
+
+08021cf0 <strchr>:
+ 8021cf0:	b2c9      	uxtb	r1, r1
+ 8021cf2:	4603      	mov	r3, r0
+ 8021cf4:	f810 2b01 	ldrb.w	r2, [r0], #1
+ 8021cf8:	b11a      	cbz	r2, 8021d02 <strchr+0x12>
+ 8021cfa:	428a      	cmp	r2, r1
+ 8021cfc:	d1f9      	bne.n	8021cf2 <strchr+0x2>
+ 8021cfe:	4618      	mov	r0, r3
+ 8021d00:	4770      	bx	lr
+ 8021d02:	2900      	cmp	r1, #0
+ 8021d04:	bf18      	it	ne
+ 8021d06:	2300      	movne	r3, #0
+ 8021d08:	e7f9      	b.n	8021cfe <strchr+0xe>
+	...
+
+08021d0c <_close_r>:
+ 8021d0c:	b538      	push	{r3, r4, r5, lr}
+ 8021d0e:	4d06      	ldr	r5, [pc, #24]	; (8021d28 <_close_r+0x1c>)
+ 8021d10:	2300      	movs	r3, #0
+ 8021d12:	4604      	mov	r4, r0
+ 8021d14:	4608      	mov	r0, r1
+ 8021d16:	602b      	str	r3, [r5, #0]
+ 8021d18:	f7e0 f855 	bl	8001dc6 <_close>
+ 8021d1c:	1c43      	adds	r3, r0, #1
+ 8021d1e:	d102      	bne.n	8021d26 <_close_r+0x1a>
+ 8021d20:	682b      	ldr	r3, [r5, #0]
+ 8021d22:	b103      	cbz	r3, 8021d26 <_close_r+0x1a>
+ 8021d24:	6023      	str	r3, [r4, #0]
+ 8021d26:	bd38      	pop	{r3, r4, r5, pc}
+ 8021d28:	2401a5e0 	.word	0x2401a5e0
+
+08021d2c <_lseek_r>:
+ 8021d2c:	b538      	push	{r3, r4, r5, lr}
+ 8021d2e:	4d07      	ldr	r5, [pc, #28]	; (8021d4c <_lseek_r+0x20>)
+ 8021d30:	4604      	mov	r4, r0
+ 8021d32:	4608      	mov	r0, r1
+ 8021d34:	4611      	mov	r1, r2
+ 8021d36:	2200      	movs	r2, #0
+ 8021d38:	602a      	str	r2, [r5, #0]
+ 8021d3a:	461a      	mov	r2, r3
+ 8021d3c:	f7e0 f86a 	bl	8001e14 <_lseek>
+ 8021d40:	1c43      	adds	r3, r0, #1
+ 8021d42:	d102      	bne.n	8021d4a <_lseek_r+0x1e>
+ 8021d44:	682b      	ldr	r3, [r5, #0]
+ 8021d46:	b103      	cbz	r3, 8021d4a <_lseek_r+0x1e>
+ 8021d48:	6023      	str	r3, [r4, #0]
+ 8021d4a:	bd38      	pop	{r3, r4, r5, pc}
+ 8021d4c:	2401a5e0 	.word	0x2401a5e0
+
+08021d50 <_read_r>:
+ 8021d50:	b538      	push	{r3, r4, r5, lr}
+ 8021d52:	4d07      	ldr	r5, [pc, #28]	; (8021d70 <_read_r+0x20>)
+ 8021d54:	4604      	mov	r4, r0
+ 8021d56:	4608      	mov	r0, r1
+ 8021d58:	4611      	mov	r1, r2
+ 8021d5a:	2200      	movs	r2, #0
+ 8021d5c:	602a      	str	r2, [r5, #0]
+ 8021d5e:	461a      	mov	r2, r3
+ 8021d60:	f7e0 f814 	bl	8001d8c <_read>
+ 8021d64:	1c43      	adds	r3, r0, #1
+ 8021d66:	d102      	bne.n	8021d6e <_read_r+0x1e>
+ 8021d68:	682b      	ldr	r3, [r5, #0]
+ 8021d6a:	b103      	cbz	r3, 8021d6e <_read_r+0x1e>
+ 8021d6c:	6023      	str	r3, [r4, #0]
+ 8021d6e:	bd38      	pop	{r3, r4, r5, pc}
+ 8021d70:	2401a5e0 	.word	0x2401a5e0
+
+08021d74 <_write_r>:
+ 8021d74:	b538      	push	{r3, r4, r5, lr}
+ 8021d76:	4d07      	ldr	r5, [pc, #28]	; (8021d94 <_write_r+0x20>)
+ 8021d78:	4604      	mov	r4, r0
+ 8021d7a:	4608      	mov	r0, r1
+ 8021d7c:	4611      	mov	r1, r2
+ 8021d7e:	2200      	movs	r2, #0
+ 8021d80:	602a      	str	r2, [r5, #0]
+ 8021d82:	461a      	mov	r2, r3
+ 8021d84:	f7de fd11 	bl	80007aa <_write>
+ 8021d88:	1c43      	adds	r3, r0, #1
+ 8021d8a:	d102      	bne.n	8021d92 <_write_r+0x1e>
+ 8021d8c:	682b      	ldr	r3, [r5, #0]
+ 8021d8e:	b103      	cbz	r3, 8021d92 <_write_r+0x1e>
+ 8021d90:	6023      	str	r3, [r4, #0]
+ 8021d92:	bd38      	pop	{r3, r4, r5, pc}
+ 8021d94:	2401a5e0 	.word	0x2401a5e0
+
+08021d98 <__libc_init_array>:
+ 8021d98:	b570      	push	{r4, r5, r6, lr}
+ 8021d9a:	4d0d      	ldr	r5, [pc, #52]	; (8021dd0 <__libc_init_array+0x38>)
+ 8021d9c:	4c0d      	ldr	r4, [pc, #52]	; (8021dd4 <__libc_init_array+0x3c>)
+ 8021d9e:	1b64      	subs	r4, r4, r5
+ 8021da0:	10a4      	asrs	r4, r4, #2
+ 8021da2:	2600      	movs	r6, #0
+ 8021da4:	42a6      	cmp	r6, r4
+ 8021da6:	d109      	bne.n	8021dbc <__libc_init_array+0x24>
+ 8021da8:	4d0b      	ldr	r5, [pc, #44]	; (8021dd8 <__libc_init_array+0x40>)
+ 8021daa:	4c0c      	ldr	r4, [pc, #48]	; (8021ddc <__libc_init_array+0x44>)
+ 8021dac:	f000 ff7e 	bl	8022cac <_init>
+ 8021db0:	1b64      	subs	r4, r4, r5
+ 8021db2:	10a4      	asrs	r4, r4, #2
+ 8021db4:	2600      	movs	r6, #0
+ 8021db6:	42a6      	cmp	r6, r4
+ 8021db8:	d105      	bne.n	8021dc6 <__libc_init_array+0x2e>
+ 8021dba:	bd70      	pop	{r4, r5, r6, pc}
+ 8021dbc:	f855 3b04 	ldr.w	r3, [r5], #4
+ 8021dc0:	4798      	blx	r3
+ 8021dc2:	3601      	adds	r6, #1
+ 8021dc4:	e7ee      	b.n	8021da4 <__libc_init_array+0xc>
+ 8021dc6:	f855 3b04 	ldr.w	r3, [r5], #4
+ 8021dca:	4798      	blx	r3
+ 8021dcc:	3601      	adds	r6, #1
+ 8021dce:	e7f2      	b.n	8021db6 <__libc_init_array+0x1e>
+ 8021dd0:	08026ef0 	.word	0x08026ef0
+ 8021dd4:	08026ef0 	.word	0x08026ef0
+ 8021dd8:	08026ef0 	.word	0x08026ef0
+ 8021ddc:	08026ef4 	.word	0x08026ef4
+
+08021de0 <__retarget_lock_init_recursive>:
+ 8021de0:	4770      	bx	lr
+
+08021de2 <__retarget_lock_acquire_recursive>:
+ 8021de2:	4770      	bx	lr
+
+08021de4 <__retarget_lock_release_recursive>:
+ 8021de4:	4770      	bx	lr
+
+08021de6 <memcpy>:
+ 8021de6:	440a      	add	r2, r1
+ 8021de8:	4291      	cmp	r1, r2
+ 8021dea:	f100 33ff 	add.w	r3, r0, #4294967295
+ 8021dee:	d100      	bne.n	8021df2 <memcpy+0xc>
+ 8021df0:	4770      	bx	lr
+ 8021df2:	b510      	push	{r4, lr}
+ 8021df4:	f811 4b01 	ldrb.w	r4, [r1], #1
+ 8021df8:	f803 4f01 	strb.w	r4, [r3, #1]!
+ 8021dfc:	4291      	cmp	r1, r2
+ 8021dfe:	d1f9      	bne.n	8021df4 <memcpy+0xe>
+ 8021e00:	bd10      	pop	{r4, pc}
+	...
+
+08021e04 <__assert_func>:
+ 8021e04:	b51f      	push	{r0, r1, r2, r3, r4, lr}
+ 8021e06:	4614      	mov	r4, r2
+ 8021e08:	461a      	mov	r2, r3
+ 8021e0a:	4b09      	ldr	r3, [pc, #36]	; (8021e30 <__assert_func+0x2c>)
+ 8021e0c:	681b      	ldr	r3, [r3, #0]
+ 8021e0e:	4605      	mov	r5, r0
+ 8021e10:	68d8      	ldr	r0, [r3, #12]
+ 8021e12:	b14c      	cbz	r4, 8021e28 <__assert_func+0x24>
+ 8021e14:	4b07      	ldr	r3, [pc, #28]	; (8021e34 <__assert_func+0x30>)
+ 8021e16:	9100      	str	r1, [sp, #0]
+ 8021e18:	e9cd 3401 	strd	r3, r4, [sp, #4]
+ 8021e1c:	4906      	ldr	r1, [pc, #24]	; (8021e38 <__assert_func+0x34>)
+ 8021e1e:	462b      	mov	r3, r5
+ 8021e20:	f000 fde8 	bl	80229f4 <fiprintf>
+ 8021e24:	f000 fec0 	bl	8022ba8 <abort>
+ 8021e28:	4b04      	ldr	r3, [pc, #16]	; (8021e3c <__assert_func+0x38>)
+ 8021e2a:	461c      	mov	r4, r3
+ 8021e2c:	e7f3      	b.n	8021e16 <__assert_func+0x12>
+ 8021e2e:	bf00      	nop
+ 8021e30:	240000a0 	.word	0x240000a0
+ 8021e34:	08026e78 	.word	0x08026e78
+ 8021e38:	08026e85 	.word	0x08026e85
+ 8021e3c:	08026eb3 	.word	0x08026eb3
+
+08021e40 <_free_r>:
+ 8021e40:	b537      	push	{r0, r1, r2, r4, r5, lr}
+ 8021e42:	2900      	cmp	r1, #0
+ 8021e44:	d044      	beq.n	8021ed0 <_free_r+0x90>
+ 8021e46:	f851 3c04 	ldr.w	r3, [r1, #-4]
+ 8021e4a:	9001      	str	r0, [sp, #4]
+ 8021e4c:	2b00      	cmp	r3, #0
+ 8021e4e:	f1a1 0404 	sub.w	r4, r1, #4
+ 8021e52:	bfb8      	it	lt
+ 8021e54:	18e4      	addlt	r4, r4, r3
+ 8021e56:	f000 f8e7 	bl	8022028 <__malloc_lock>
+ 8021e5a:	4a1e      	ldr	r2, [pc, #120]	; (8021ed4 <_free_r+0x94>)
+ 8021e5c:	9801      	ldr	r0, [sp, #4]
+ 8021e5e:	6813      	ldr	r3, [r2, #0]
+ 8021e60:	b933      	cbnz	r3, 8021e70 <_free_r+0x30>
+ 8021e62:	6063      	str	r3, [r4, #4]
+ 8021e64:	6014      	str	r4, [r2, #0]
+ 8021e66:	b003      	add	sp, #12
+ 8021e68:	e8bd 4030 	ldmia.w	sp!, {r4, r5, lr}
+ 8021e6c:	f000 b8e2 	b.w	8022034 <__malloc_unlock>
+ 8021e70:	42a3      	cmp	r3, r4
+ 8021e72:	d908      	bls.n	8021e86 <_free_r+0x46>
+ 8021e74:	6825      	ldr	r5, [r4, #0]
+ 8021e76:	1961      	adds	r1, r4, r5
+ 8021e78:	428b      	cmp	r3, r1
+ 8021e7a:	bf01      	itttt	eq
+ 8021e7c:	6819      	ldreq	r1, [r3, #0]
+ 8021e7e:	685b      	ldreq	r3, [r3, #4]
+ 8021e80:	1949      	addeq	r1, r1, r5
+ 8021e82:	6021      	streq	r1, [r4, #0]
+ 8021e84:	e7ed      	b.n	8021e62 <_free_r+0x22>
+ 8021e86:	461a      	mov	r2, r3
+ 8021e88:	685b      	ldr	r3, [r3, #4]
+ 8021e8a:	b10b      	cbz	r3, 8021e90 <_free_r+0x50>
+ 8021e8c:	42a3      	cmp	r3, r4
+ 8021e8e:	d9fa      	bls.n	8021e86 <_free_r+0x46>
+ 8021e90:	6811      	ldr	r1, [r2, #0]
+ 8021e92:	1855      	adds	r5, r2, r1
+ 8021e94:	42a5      	cmp	r5, r4
+ 8021e96:	d10b      	bne.n	8021eb0 <_free_r+0x70>
+ 8021e98:	6824      	ldr	r4, [r4, #0]
+ 8021e9a:	4421      	add	r1, r4
+ 8021e9c:	1854      	adds	r4, r2, r1
+ 8021e9e:	42a3      	cmp	r3, r4
+ 8021ea0:	6011      	str	r1, [r2, #0]
+ 8021ea2:	d1e0      	bne.n	8021e66 <_free_r+0x26>
+ 8021ea4:	681c      	ldr	r4, [r3, #0]
+ 8021ea6:	685b      	ldr	r3, [r3, #4]
+ 8021ea8:	6053      	str	r3, [r2, #4]
+ 8021eaa:	440c      	add	r4, r1
+ 8021eac:	6014      	str	r4, [r2, #0]
+ 8021eae:	e7da      	b.n	8021e66 <_free_r+0x26>
+ 8021eb0:	d902      	bls.n	8021eb8 <_free_r+0x78>
+ 8021eb2:	230c      	movs	r3, #12
+ 8021eb4:	6003      	str	r3, [r0, #0]
+ 8021eb6:	e7d6      	b.n	8021e66 <_free_r+0x26>
+ 8021eb8:	6825      	ldr	r5, [r4, #0]
+ 8021eba:	1961      	adds	r1, r4, r5
+ 8021ebc:	428b      	cmp	r3, r1
+ 8021ebe:	bf04      	itt	eq
+ 8021ec0:	6819      	ldreq	r1, [r3, #0]
+ 8021ec2:	685b      	ldreq	r3, [r3, #4]
+ 8021ec4:	6063      	str	r3, [r4, #4]
+ 8021ec6:	bf04      	itt	eq
+ 8021ec8:	1949      	addeq	r1, r1, r5
+ 8021eca:	6021      	streq	r1, [r4, #0]
+ 8021ecc:	6054      	str	r4, [r2, #4]
+ 8021ece:	e7ca      	b.n	8021e66 <_free_r+0x26>
+ 8021ed0:	b003      	add	sp, #12
+ 8021ed2:	bd30      	pop	{r4, r5, pc}
+ 8021ed4:	2401a728 	.word	0x2401a728
+
+08021ed8 <malloc>:
+ 8021ed8:	4b02      	ldr	r3, [pc, #8]	; (8021ee4 <malloc+0xc>)
+ 8021eda:	4601      	mov	r1, r0
+ 8021edc:	6818      	ldr	r0, [r3, #0]
+ 8021ede:	f000 b823 	b.w	8021f28 <_malloc_r>
+ 8021ee2:	bf00      	nop
+ 8021ee4:	240000a0 	.word	0x240000a0
+
+08021ee8 <sbrk_aligned>:
+ 8021ee8:	b570      	push	{r4, r5, r6, lr}
+ 8021eea:	4e0e      	ldr	r6, [pc, #56]	; (8021f24 <sbrk_aligned+0x3c>)
+ 8021eec:	460c      	mov	r4, r1
+ 8021eee:	6831      	ldr	r1, [r6, #0]
+ 8021ef0:	4605      	mov	r5, r0
+ 8021ef2:	b911      	cbnz	r1, 8021efa <sbrk_aligned+0x12>
+ 8021ef4:	f000 fe48 	bl	8022b88 <_sbrk_r>
+ 8021ef8:	6030      	str	r0, [r6, #0]
+ 8021efa:	4621      	mov	r1, r4
+ 8021efc:	4628      	mov	r0, r5
+ 8021efe:	f000 fe43 	bl	8022b88 <_sbrk_r>
+ 8021f02:	1c43      	adds	r3, r0, #1
+ 8021f04:	d00a      	beq.n	8021f1c <sbrk_aligned+0x34>
+ 8021f06:	1cc4      	adds	r4, r0, #3
+ 8021f08:	f024 0403 	bic.w	r4, r4, #3
+ 8021f0c:	42a0      	cmp	r0, r4
+ 8021f0e:	d007      	beq.n	8021f20 <sbrk_aligned+0x38>
+ 8021f10:	1a21      	subs	r1, r4, r0
+ 8021f12:	4628      	mov	r0, r5
+ 8021f14:	f000 fe38 	bl	8022b88 <_sbrk_r>
+ 8021f18:	3001      	adds	r0, #1
+ 8021f1a:	d101      	bne.n	8021f20 <sbrk_aligned+0x38>
+ 8021f1c:	f04f 34ff 	mov.w	r4, #4294967295
+ 8021f20:	4620      	mov	r0, r4
+ 8021f22:	bd70      	pop	{r4, r5, r6, pc}
+ 8021f24:	2401a72c 	.word	0x2401a72c
+
+08021f28 <_malloc_r>:
+ 8021f28:	e92d 43f8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
+ 8021f2c:	1ccd      	adds	r5, r1, #3
+ 8021f2e:	f025 0503 	bic.w	r5, r5, #3
+ 8021f32:	3508      	adds	r5, #8
+ 8021f34:	2d0c      	cmp	r5, #12
+ 8021f36:	bf38      	it	cc
+ 8021f38:	250c      	movcc	r5, #12
+ 8021f3a:	2d00      	cmp	r5, #0
+ 8021f3c:	4607      	mov	r7, r0
+ 8021f3e:	db01      	blt.n	8021f44 <_malloc_r+0x1c>
+ 8021f40:	42a9      	cmp	r1, r5
+ 8021f42:	d905      	bls.n	8021f50 <_malloc_r+0x28>
+ 8021f44:	230c      	movs	r3, #12
+ 8021f46:	603b      	str	r3, [r7, #0]
+ 8021f48:	2600      	movs	r6, #0
+ 8021f4a:	4630      	mov	r0, r6
+ 8021f4c:	e8bd 83f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
+ 8021f50:	f8df 80d0 	ldr.w	r8, [pc, #208]	; 8022024 <_malloc_r+0xfc>
+ 8021f54:	f000 f868 	bl	8022028 <__malloc_lock>
+ 8021f58:	f8d8 3000 	ldr.w	r3, [r8]
+ 8021f5c:	461c      	mov	r4, r3
+ 8021f5e:	bb5c      	cbnz	r4, 8021fb8 <_malloc_r+0x90>
+ 8021f60:	4629      	mov	r1, r5
+ 8021f62:	4638      	mov	r0, r7
+ 8021f64:	f7ff ffc0 	bl	8021ee8 <sbrk_aligned>
+ 8021f68:	1c43      	adds	r3, r0, #1
+ 8021f6a:	4604      	mov	r4, r0
+ 8021f6c:	d155      	bne.n	802201a <_malloc_r+0xf2>
+ 8021f6e:	f8d8 4000 	ldr.w	r4, [r8]
+ 8021f72:	4626      	mov	r6, r4
+ 8021f74:	2e00      	cmp	r6, #0
+ 8021f76:	d145      	bne.n	8022004 <_malloc_r+0xdc>
+ 8021f78:	2c00      	cmp	r4, #0
+ 8021f7a:	d048      	beq.n	802200e <_malloc_r+0xe6>
+ 8021f7c:	6823      	ldr	r3, [r4, #0]
+ 8021f7e:	4631      	mov	r1, r6
+ 8021f80:	4638      	mov	r0, r7
+ 8021f82:	eb04 0903 	add.w	r9, r4, r3
+ 8021f86:	f000 fdff 	bl	8022b88 <_sbrk_r>
+ 8021f8a:	4581      	cmp	r9, r0
+ 8021f8c:	d13f      	bne.n	802200e <_malloc_r+0xe6>
+ 8021f8e:	6821      	ldr	r1, [r4, #0]
+ 8021f90:	1a6d      	subs	r5, r5, r1
+ 8021f92:	4629      	mov	r1, r5
+ 8021f94:	4638      	mov	r0, r7
+ 8021f96:	f7ff ffa7 	bl	8021ee8 <sbrk_aligned>
+ 8021f9a:	3001      	adds	r0, #1
+ 8021f9c:	d037      	beq.n	802200e <_malloc_r+0xe6>
+ 8021f9e:	6823      	ldr	r3, [r4, #0]
+ 8021fa0:	442b      	add	r3, r5
+ 8021fa2:	6023      	str	r3, [r4, #0]
+ 8021fa4:	f8d8 3000 	ldr.w	r3, [r8]
+ 8021fa8:	2b00      	cmp	r3, #0
+ 8021faa:	d038      	beq.n	802201e <_malloc_r+0xf6>
+ 8021fac:	685a      	ldr	r2, [r3, #4]
+ 8021fae:	42a2      	cmp	r2, r4
+ 8021fb0:	d12b      	bne.n	802200a <_malloc_r+0xe2>
+ 8021fb2:	2200      	movs	r2, #0
+ 8021fb4:	605a      	str	r2, [r3, #4]
+ 8021fb6:	e00f      	b.n	8021fd8 <_malloc_r+0xb0>
+ 8021fb8:	6822      	ldr	r2, [r4, #0]
+ 8021fba:	1b52      	subs	r2, r2, r5
+ 8021fbc:	d41f      	bmi.n	8021ffe <_malloc_r+0xd6>
+ 8021fbe:	2a0b      	cmp	r2, #11
+ 8021fc0:	d917      	bls.n	8021ff2 <_malloc_r+0xca>
+ 8021fc2:	1961      	adds	r1, r4, r5
+ 8021fc4:	42a3      	cmp	r3, r4
+ 8021fc6:	6025      	str	r5, [r4, #0]
+ 8021fc8:	bf18      	it	ne
+ 8021fca:	6059      	strne	r1, [r3, #4]
+ 8021fcc:	6863      	ldr	r3, [r4, #4]
+ 8021fce:	bf08      	it	eq
+ 8021fd0:	f8c8 1000 	streq.w	r1, [r8]
+ 8021fd4:	5162      	str	r2, [r4, r5]
+ 8021fd6:	604b      	str	r3, [r1, #4]
+ 8021fd8:	4638      	mov	r0, r7
+ 8021fda:	f104 060b 	add.w	r6, r4, #11
+ 8021fde:	f000 f829 	bl	8022034 <__malloc_unlock>
+ 8021fe2:	f026 0607 	bic.w	r6, r6, #7
+ 8021fe6:	1d23      	adds	r3, r4, #4
+ 8021fe8:	1af2      	subs	r2, r6, r3
+ 8021fea:	d0ae      	beq.n	8021f4a <_malloc_r+0x22>
+ 8021fec:	1b9b      	subs	r3, r3, r6
+ 8021fee:	50a3      	str	r3, [r4, r2]
+ 8021ff0:	e7ab      	b.n	8021f4a <_malloc_r+0x22>
+ 8021ff2:	42a3      	cmp	r3, r4
+ 8021ff4:	6862      	ldr	r2, [r4, #4]
+ 8021ff6:	d1dd      	bne.n	8021fb4 <_malloc_r+0x8c>
+ 8021ff8:	f8c8 2000 	str.w	r2, [r8]
+ 8021ffc:	e7ec      	b.n	8021fd8 <_malloc_r+0xb0>
+ 8021ffe:	4623      	mov	r3, r4
+ 8022000:	6864      	ldr	r4, [r4, #4]
+ 8022002:	e7ac      	b.n	8021f5e <_malloc_r+0x36>
+ 8022004:	4634      	mov	r4, r6
+ 8022006:	6876      	ldr	r6, [r6, #4]
+ 8022008:	e7b4      	b.n	8021f74 <_malloc_r+0x4c>
+ 802200a:	4613      	mov	r3, r2
+ 802200c:	e7cc      	b.n	8021fa8 <_malloc_r+0x80>
+ 802200e:	230c      	movs	r3, #12
+ 8022010:	603b      	str	r3, [r7, #0]
+ 8022012:	4638      	mov	r0, r7
+ 8022014:	f000 f80e 	bl	8022034 <__malloc_unlock>
+ 8022018:	e797      	b.n	8021f4a <_malloc_r+0x22>
+ 802201a:	6025      	str	r5, [r4, #0]
+ 802201c:	e7dc      	b.n	8021fd8 <_malloc_r+0xb0>
+ 802201e:	605b      	str	r3, [r3, #4]
+ 8022020:	deff      	udf	#255	; 0xff
+ 8022022:	bf00      	nop
+ 8022024:	2401a728 	.word	0x2401a728
+
+08022028 <__malloc_lock>:
+ 8022028:	4801      	ldr	r0, [pc, #4]	; (8022030 <__malloc_lock+0x8>)
+ 802202a:	f7ff beda 	b.w	8021de2 <__retarget_lock_acquire_recursive>
+ 802202e:	bf00      	nop
+ 8022030:	2401a724 	.word	0x2401a724
+
+08022034 <__malloc_unlock>:
+ 8022034:	4801      	ldr	r0, [pc, #4]	; (802203c <__malloc_unlock+0x8>)
+ 8022036:	f7ff bed5 	b.w	8021de4 <__retarget_lock_release_recursive>
+ 802203a:	bf00      	nop
+ 802203c:	2401a724 	.word	0x2401a724
+
+08022040 <__ssputs_r>:
+ 8022040:	e92d 47f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
+ 8022044:	688e      	ldr	r6, [r1, #8]
+ 8022046:	461f      	mov	r7, r3
+ 8022048:	42be      	cmp	r6, r7
+ 802204a:	680b      	ldr	r3, [r1, #0]
+ 802204c:	4682      	mov	sl, r0
+ 802204e:	460c      	mov	r4, r1
+ 8022050:	4690      	mov	r8, r2
+ 8022052:	d82c      	bhi.n	80220ae <__ssputs_r+0x6e>
+ 8022054:	898a      	ldrh	r2, [r1, #12]
+ 8022056:	f412 6f90 	tst.w	r2, #1152	; 0x480
+ 802205a:	d026      	beq.n	80220aa <__ssputs_r+0x6a>
+ 802205c:	6965      	ldr	r5, [r4, #20]
+ 802205e:	6909      	ldr	r1, [r1, #16]
+ 8022060:	eb05 0545 	add.w	r5, r5, r5, lsl #1
+ 8022064:	eba3 0901 	sub.w	r9, r3, r1
+ 8022068:	eb05 75d5 	add.w	r5, r5, r5, lsr #31
+ 802206c:	1c7b      	adds	r3, r7, #1
+ 802206e:	444b      	add	r3, r9
+ 8022070:	106d      	asrs	r5, r5, #1
+ 8022072:	429d      	cmp	r5, r3
+ 8022074:	bf38      	it	cc
+ 8022076:	461d      	movcc	r5, r3
+ 8022078:	0553      	lsls	r3, r2, #21
+ 802207a:	d527      	bpl.n	80220cc <__ssputs_r+0x8c>
+ 802207c:	4629      	mov	r1, r5
+ 802207e:	f7ff ff53 	bl	8021f28 <_malloc_r>
+ 8022082:	4606      	mov	r6, r0
+ 8022084:	b360      	cbz	r0, 80220e0 <__ssputs_r+0xa0>
+ 8022086:	6921      	ldr	r1, [r4, #16]
+ 8022088:	464a      	mov	r2, r9
+ 802208a:	f7ff feac 	bl	8021de6 <memcpy>
+ 802208e:	89a3      	ldrh	r3, [r4, #12]
+ 8022090:	f423 6390 	bic.w	r3, r3, #1152	; 0x480
+ 8022094:	f043 0380 	orr.w	r3, r3, #128	; 0x80
+ 8022098:	81a3      	strh	r3, [r4, #12]
+ 802209a:	6126      	str	r6, [r4, #16]
+ 802209c:	6165      	str	r5, [r4, #20]
+ 802209e:	444e      	add	r6, r9
+ 80220a0:	eba5 0509 	sub.w	r5, r5, r9
+ 80220a4:	6026      	str	r6, [r4, #0]
+ 80220a6:	60a5      	str	r5, [r4, #8]
+ 80220a8:	463e      	mov	r6, r7
+ 80220aa:	42be      	cmp	r6, r7
+ 80220ac:	d900      	bls.n	80220b0 <__ssputs_r+0x70>
+ 80220ae:	463e      	mov	r6, r7
+ 80220b0:	6820      	ldr	r0, [r4, #0]
+ 80220b2:	4632      	mov	r2, r6
+ 80220b4:	4641      	mov	r1, r8
+ 80220b6:	f7ff fdf9 	bl	8021cac <memmove>
+ 80220ba:	68a3      	ldr	r3, [r4, #8]
+ 80220bc:	1b9b      	subs	r3, r3, r6
+ 80220be:	60a3      	str	r3, [r4, #8]
+ 80220c0:	6823      	ldr	r3, [r4, #0]
+ 80220c2:	4433      	add	r3, r6
+ 80220c4:	6023      	str	r3, [r4, #0]
+ 80220c6:	2000      	movs	r0, #0
+ 80220c8:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
+ 80220cc:	462a      	mov	r2, r5
+ 80220ce:	f000 fd72 	bl	8022bb6 <_realloc_r>
+ 80220d2:	4606      	mov	r6, r0
+ 80220d4:	2800      	cmp	r0, #0
+ 80220d6:	d1e0      	bne.n	802209a <__ssputs_r+0x5a>
+ 80220d8:	6921      	ldr	r1, [r4, #16]
+ 80220da:	4650      	mov	r0, sl
+ 80220dc:	f7ff feb0 	bl	8021e40 <_free_r>
+ 80220e0:	230c      	movs	r3, #12
+ 80220e2:	f8ca 3000 	str.w	r3, [sl]
+ 80220e6:	89a3      	ldrh	r3, [r4, #12]
+ 80220e8:	f043 0340 	orr.w	r3, r3, #64	; 0x40
+ 80220ec:	81a3      	strh	r3, [r4, #12]
+ 80220ee:	f04f 30ff 	mov.w	r0, #4294967295
+ 80220f2:	e7e9      	b.n	80220c8 <__ssputs_r+0x88>
+
+080220f4 <_svfiprintf_r>:
+ 80220f4:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
+ 80220f8:	4698      	mov	r8, r3
+ 80220fa:	898b      	ldrh	r3, [r1, #12]
+ 80220fc:	061b      	lsls	r3, r3, #24
+ 80220fe:	b09d      	sub	sp, #116	; 0x74
+ 8022100:	4607      	mov	r7, r0
+ 8022102:	460d      	mov	r5, r1
+ 8022104:	4614      	mov	r4, r2
+ 8022106:	d50e      	bpl.n	8022126 <_svfiprintf_r+0x32>
+ 8022108:	690b      	ldr	r3, [r1, #16]
+ 802210a:	b963      	cbnz	r3, 8022126 <_svfiprintf_r+0x32>
+ 802210c:	2140      	movs	r1, #64	; 0x40
+ 802210e:	f7ff ff0b 	bl	8021f28 <_malloc_r>
+ 8022112:	6028      	str	r0, [r5, #0]
+ 8022114:	6128      	str	r0, [r5, #16]
+ 8022116:	b920      	cbnz	r0, 8022122 <_svfiprintf_r+0x2e>
+ 8022118:	230c      	movs	r3, #12
+ 802211a:	603b      	str	r3, [r7, #0]
+ 802211c:	f04f 30ff 	mov.w	r0, #4294967295
+ 8022120:	e0d0      	b.n	80222c4 <_svfiprintf_r+0x1d0>
+ 8022122:	2340      	movs	r3, #64	; 0x40
+ 8022124:	616b      	str	r3, [r5, #20]
+ 8022126:	2300      	movs	r3, #0
+ 8022128:	9309      	str	r3, [sp, #36]	; 0x24
+ 802212a:	2320      	movs	r3, #32
+ 802212c:	f88d 3029 	strb.w	r3, [sp, #41]	; 0x29
+ 8022130:	f8cd 800c 	str.w	r8, [sp, #12]
+ 8022134:	2330      	movs	r3, #48	; 0x30
+ 8022136:	f8df 81a4 	ldr.w	r8, [pc, #420]	; 80222dc <_svfiprintf_r+0x1e8>
+ 802213a:	f88d 302a 	strb.w	r3, [sp, #42]	; 0x2a
+ 802213e:	f04f 0901 	mov.w	r9, #1
+ 8022142:	4623      	mov	r3, r4
+ 8022144:	469a      	mov	sl, r3
+ 8022146:	f813 2b01 	ldrb.w	r2, [r3], #1
+ 802214a:	b10a      	cbz	r2, 8022150 <_svfiprintf_r+0x5c>
+ 802214c:	2a25      	cmp	r2, #37	; 0x25
+ 802214e:	d1f9      	bne.n	8022144 <_svfiprintf_r+0x50>
+ 8022150:	ebba 0b04 	subs.w	fp, sl, r4
+ 8022154:	d00b      	beq.n	802216e <_svfiprintf_r+0x7a>
+ 8022156:	465b      	mov	r3, fp
+ 8022158:	4622      	mov	r2, r4
+ 802215a:	4629      	mov	r1, r5
+ 802215c:	4638      	mov	r0, r7
+ 802215e:	f7ff ff6f 	bl	8022040 <__ssputs_r>
+ 8022162:	3001      	adds	r0, #1
+ 8022164:	f000 80a9 	beq.w	80222ba <_svfiprintf_r+0x1c6>
+ 8022168:	9a09      	ldr	r2, [sp, #36]	; 0x24
+ 802216a:	445a      	add	r2, fp
+ 802216c:	9209      	str	r2, [sp, #36]	; 0x24
+ 802216e:	f89a 3000 	ldrb.w	r3, [sl]
+ 8022172:	2b00      	cmp	r3, #0
+ 8022174:	f000 80a1 	beq.w	80222ba <_svfiprintf_r+0x1c6>
+ 8022178:	2300      	movs	r3, #0
+ 802217a:	f04f 32ff 	mov.w	r2, #4294967295
+ 802217e:	e9cd 2305 	strd	r2, r3, [sp, #20]
+ 8022182:	f10a 0a01 	add.w	sl, sl, #1
+ 8022186:	9304      	str	r3, [sp, #16]
+ 8022188:	9307      	str	r3, [sp, #28]
+ 802218a:	f88d 3053 	strb.w	r3, [sp, #83]	; 0x53
+ 802218e:	931a      	str	r3, [sp, #104]	; 0x68
+ 8022190:	4654      	mov	r4, sl
+ 8022192:	2205      	movs	r2, #5
+ 8022194:	f814 1b01 	ldrb.w	r1, [r4], #1
+ 8022198:	4850      	ldr	r0, [pc, #320]	; (80222dc <_svfiprintf_r+0x1e8>)
+ 802219a:	f7de f8d1 	bl	8000340 <memchr>
+ 802219e:	9a04      	ldr	r2, [sp, #16]
+ 80221a0:	b9d8      	cbnz	r0, 80221da <_svfiprintf_r+0xe6>
+ 80221a2:	06d0      	lsls	r0, r2, #27
+ 80221a4:	bf44      	itt	mi
+ 80221a6:	2320      	movmi	r3, #32
+ 80221a8:	f88d 3053 	strbmi.w	r3, [sp, #83]	; 0x53
+ 80221ac:	0711      	lsls	r1, r2, #28
+ 80221ae:	bf44      	itt	mi
+ 80221b0:	232b      	movmi	r3, #43	; 0x2b
+ 80221b2:	f88d 3053 	strbmi.w	r3, [sp, #83]	; 0x53
+ 80221b6:	f89a 3000 	ldrb.w	r3, [sl]
+ 80221ba:	2b2a      	cmp	r3, #42	; 0x2a
+ 80221bc:	d015      	beq.n	80221ea <_svfiprintf_r+0xf6>
+ 80221be:	9a07      	ldr	r2, [sp, #28]
+ 80221c0:	4654      	mov	r4, sl
+ 80221c2:	2000      	movs	r0, #0
+ 80221c4:	f04f 0c0a 	mov.w	ip, #10
+ 80221c8:	4621      	mov	r1, r4
+ 80221ca:	f811 3b01 	ldrb.w	r3, [r1], #1
+ 80221ce:	3b30      	subs	r3, #48	; 0x30
+ 80221d0:	2b09      	cmp	r3, #9
+ 80221d2:	d94d      	bls.n	8022270 <_svfiprintf_r+0x17c>
+ 80221d4:	b1b0      	cbz	r0, 8022204 <_svfiprintf_r+0x110>
+ 80221d6:	9207      	str	r2, [sp, #28]
+ 80221d8:	e014      	b.n	8022204 <_svfiprintf_r+0x110>
+ 80221da:	eba0 0308 	sub.w	r3, r0, r8
+ 80221de:	fa09 f303 	lsl.w	r3, r9, r3
+ 80221e2:	4313      	orrs	r3, r2
+ 80221e4:	9304      	str	r3, [sp, #16]
+ 80221e6:	46a2      	mov	sl, r4
+ 80221e8:	e7d2      	b.n	8022190 <_svfiprintf_r+0x9c>
+ 80221ea:	9b03      	ldr	r3, [sp, #12]
+ 80221ec:	1d19      	adds	r1, r3, #4
+ 80221ee:	681b      	ldr	r3, [r3, #0]
+ 80221f0:	9103      	str	r1, [sp, #12]
+ 80221f2:	2b00      	cmp	r3, #0
+ 80221f4:	bfbb      	ittet	lt
+ 80221f6:	425b      	neglt	r3, r3
+ 80221f8:	f042 0202 	orrlt.w	r2, r2, #2
+ 80221fc:	9307      	strge	r3, [sp, #28]
+ 80221fe:	9307      	strlt	r3, [sp, #28]
+ 8022200:	bfb8      	it	lt
+ 8022202:	9204      	strlt	r2, [sp, #16]
+ 8022204:	7823      	ldrb	r3, [r4, #0]
+ 8022206:	2b2e      	cmp	r3, #46	; 0x2e
+ 8022208:	d10c      	bne.n	8022224 <_svfiprintf_r+0x130>
+ 802220a:	7863      	ldrb	r3, [r4, #1]
+ 802220c:	2b2a      	cmp	r3, #42	; 0x2a
+ 802220e:	d134      	bne.n	802227a <_svfiprintf_r+0x186>
+ 8022210:	9b03      	ldr	r3, [sp, #12]
+ 8022212:	1d1a      	adds	r2, r3, #4
+ 8022214:	681b      	ldr	r3, [r3, #0]
+ 8022216:	9203      	str	r2, [sp, #12]
+ 8022218:	2b00      	cmp	r3, #0
+ 802221a:	bfb8      	it	lt
+ 802221c:	f04f 33ff 	movlt.w	r3, #4294967295
+ 8022220:	3402      	adds	r4, #2
+ 8022222:	9305      	str	r3, [sp, #20]
+ 8022224:	f8df a0c4 	ldr.w	sl, [pc, #196]	; 80222ec <_svfiprintf_r+0x1f8>
+ 8022228:	7821      	ldrb	r1, [r4, #0]
+ 802222a:	2203      	movs	r2, #3
+ 802222c:	4650      	mov	r0, sl
+ 802222e:	f7de f887 	bl	8000340 <memchr>
+ 8022232:	b138      	cbz	r0, 8022244 <_svfiprintf_r+0x150>
+ 8022234:	9b04      	ldr	r3, [sp, #16]
+ 8022236:	eba0 000a 	sub.w	r0, r0, sl
+ 802223a:	2240      	movs	r2, #64	; 0x40
+ 802223c:	4082      	lsls	r2, r0
+ 802223e:	4313      	orrs	r3, r2
+ 8022240:	3401      	adds	r4, #1
+ 8022242:	9304      	str	r3, [sp, #16]
+ 8022244:	f814 1b01 	ldrb.w	r1, [r4], #1
+ 8022248:	4825      	ldr	r0, [pc, #148]	; (80222e0 <_svfiprintf_r+0x1ec>)
+ 802224a:	f88d 1028 	strb.w	r1, [sp, #40]	; 0x28
+ 802224e:	2206      	movs	r2, #6
+ 8022250:	f7de f876 	bl	8000340 <memchr>
+ 8022254:	2800      	cmp	r0, #0
+ 8022256:	d038      	beq.n	80222ca <_svfiprintf_r+0x1d6>
+ 8022258:	4b22      	ldr	r3, [pc, #136]	; (80222e4 <_svfiprintf_r+0x1f0>)
+ 802225a:	bb1b      	cbnz	r3, 80222a4 <_svfiprintf_r+0x1b0>
+ 802225c:	9b03      	ldr	r3, [sp, #12]
+ 802225e:	3307      	adds	r3, #7
+ 8022260:	f023 0307 	bic.w	r3, r3, #7
+ 8022264:	3308      	adds	r3, #8
+ 8022266:	9303      	str	r3, [sp, #12]
+ 8022268:	9b09      	ldr	r3, [sp, #36]	; 0x24
+ 802226a:	4433      	add	r3, r6
+ 802226c:	9309      	str	r3, [sp, #36]	; 0x24
+ 802226e:	e768      	b.n	8022142 <_svfiprintf_r+0x4e>
+ 8022270:	fb0c 3202 	mla	r2, ip, r2, r3
+ 8022274:	460c      	mov	r4, r1
+ 8022276:	2001      	movs	r0, #1
+ 8022278:	e7a6      	b.n	80221c8 <_svfiprintf_r+0xd4>
+ 802227a:	2300      	movs	r3, #0
+ 802227c:	3401      	adds	r4, #1
+ 802227e:	9305      	str	r3, [sp, #20]
+ 8022280:	4619      	mov	r1, r3
+ 8022282:	f04f 0c0a 	mov.w	ip, #10
+ 8022286:	4620      	mov	r0, r4
+ 8022288:	f810 2b01 	ldrb.w	r2, [r0], #1
+ 802228c:	3a30      	subs	r2, #48	; 0x30
+ 802228e:	2a09      	cmp	r2, #9
+ 8022290:	d903      	bls.n	802229a <_svfiprintf_r+0x1a6>
+ 8022292:	2b00      	cmp	r3, #0
+ 8022294:	d0c6      	beq.n	8022224 <_svfiprintf_r+0x130>
+ 8022296:	9105      	str	r1, [sp, #20]
+ 8022298:	e7c4      	b.n	8022224 <_svfiprintf_r+0x130>
+ 802229a:	fb0c 2101 	mla	r1, ip, r1, r2
+ 802229e:	4604      	mov	r4, r0
+ 80222a0:	2301      	movs	r3, #1
+ 80222a2:	e7f0      	b.n	8022286 <_svfiprintf_r+0x192>
+ 80222a4:	ab03      	add	r3, sp, #12
+ 80222a6:	9300      	str	r3, [sp, #0]
+ 80222a8:	462a      	mov	r2, r5
+ 80222aa:	4b0f      	ldr	r3, [pc, #60]	; (80222e8 <_svfiprintf_r+0x1f4>)
+ 80222ac:	a904      	add	r1, sp, #16
+ 80222ae:	4638      	mov	r0, r7
+ 80222b0:	f3af 8000 	nop.w
+ 80222b4:	1c42      	adds	r2, r0, #1
+ 80222b6:	4606      	mov	r6, r0
+ 80222b8:	d1d6      	bne.n	8022268 <_svfiprintf_r+0x174>
+ 80222ba:	89ab      	ldrh	r3, [r5, #12]
+ 80222bc:	065b      	lsls	r3, r3, #25
+ 80222be:	f53f af2d 	bmi.w	802211c <_svfiprintf_r+0x28>
+ 80222c2:	9809      	ldr	r0, [sp, #36]	; 0x24
+ 80222c4:	b01d      	add	sp, #116	; 0x74
+ 80222c6:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
+ 80222ca:	ab03      	add	r3, sp, #12
+ 80222cc:	9300      	str	r3, [sp, #0]
+ 80222ce:	462a      	mov	r2, r5
+ 80222d0:	4b05      	ldr	r3, [pc, #20]	; (80222e8 <_svfiprintf_r+0x1f4>)
+ 80222d2:	a904      	add	r1, sp, #16
+ 80222d4:	4638      	mov	r0, r7
+ 80222d6:	f000 f9bd 	bl	8022654 <_printf_i>
+ 80222da:	e7eb      	b.n	80222b4 <_svfiprintf_r+0x1c0>
+ 80222dc:	08026eb4 	.word	0x08026eb4
+ 80222e0:	08026ebe 	.word	0x08026ebe
+ 80222e4:	00000000 	.word	0x00000000
+ 80222e8:	08022041 	.word	0x08022041
+ 80222ec:	08026eba 	.word	0x08026eba
+
+080222f0 <__sfputc_r>:
+ 80222f0:	6893      	ldr	r3, [r2, #8]
+ 80222f2:	3b01      	subs	r3, #1
+ 80222f4:	2b00      	cmp	r3, #0
+ 80222f6:	b410      	push	{r4}
+ 80222f8:	6093      	str	r3, [r2, #8]
+ 80222fa:	da08      	bge.n	802230e <__sfputc_r+0x1e>
+ 80222fc:	6994      	ldr	r4, [r2, #24]
+ 80222fe:	42a3      	cmp	r3, r4
+ 8022300:	db01      	blt.n	8022306 <__sfputc_r+0x16>
+ 8022302:	290a      	cmp	r1, #10
+ 8022304:	d103      	bne.n	802230e <__sfputc_r+0x1e>
+ 8022306:	f85d 4b04 	ldr.w	r4, [sp], #4
+ 802230a:	f7ff bc2a 	b.w	8021b62 <__swbuf_r>
+ 802230e:	6813      	ldr	r3, [r2, #0]
+ 8022310:	1c58      	adds	r0, r3, #1
+ 8022312:	6010      	str	r0, [r2, #0]
+ 8022314:	7019      	strb	r1, [r3, #0]
+ 8022316:	4608      	mov	r0, r1
+ 8022318:	f85d 4b04 	ldr.w	r4, [sp], #4
+ 802231c:	4770      	bx	lr
+
+0802231e <__sfputs_r>:
+ 802231e:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
+ 8022320:	4606      	mov	r6, r0
+ 8022322:	460f      	mov	r7, r1
+ 8022324:	4614      	mov	r4, r2
+ 8022326:	18d5      	adds	r5, r2, r3
+ 8022328:	42ac      	cmp	r4, r5
+ 802232a:	d101      	bne.n	8022330 <__sfputs_r+0x12>
+ 802232c:	2000      	movs	r0, #0
+ 802232e:	e007      	b.n	8022340 <__sfputs_r+0x22>
+ 8022330:	f814 1b01 	ldrb.w	r1, [r4], #1
+ 8022334:	463a      	mov	r2, r7
+ 8022336:	4630      	mov	r0, r6
+ 8022338:	f7ff ffda 	bl	80222f0 <__sfputc_r>
+ 802233c:	1c43      	adds	r3, r0, #1
+ 802233e:	d1f3      	bne.n	8022328 <__sfputs_r+0xa>
+ 8022340:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
+	...
+
+08022344 <_vfiprintf_r>:
+ 8022344:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
+ 8022348:	460d      	mov	r5, r1
+ 802234a:	b09d      	sub	sp, #116	; 0x74
+ 802234c:	4614      	mov	r4, r2
+ 802234e:	4698      	mov	r8, r3
+ 8022350:	4606      	mov	r6, r0
+ 8022352:	b118      	cbz	r0, 802235c <_vfiprintf_r+0x18>
+ 8022354:	6a03      	ldr	r3, [r0, #32]
+ 8022356:	b90b      	cbnz	r3, 802235c <_vfiprintf_r+0x18>
+ 8022358:	f7ff fae0 	bl	802191c <__sinit>
+ 802235c:	6e6b      	ldr	r3, [r5, #100]	; 0x64
+ 802235e:	07d9      	lsls	r1, r3, #31
+ 8022360:	d405      	bmi.n	802236e <_vfiprintf_r+0x2a>
+ 8022362:	89ab      	ldrh	r3, [r5, #12]
+ 8022364:	059a      	lsls	r2, r3, #22
+ 8022366:	d402      	bmi.n	802236e <_vfiprintf_r+0x2a>
+ 8022368:	6da8      	ldr	r0, [r5, #88]	; 0x58
+ 802236a:	f7ff fd3a 	bl	8021de2 <__retarget_lock_acquire_recursive>
+ 802236e:	89ab      	ldrh	r3, [r5, #12]
+ 8022370:	071b      	lsls	r3, r3, #28
+ 8022372:	d501      	bpl.n	8022378 <_vfiprintf_r+0x34>
+ 8022374:	692b      	ldr	r3, [r5, #16]
+ 8022376:	b99b      	cbnz	r3, 80223a0 <_vfiprintf_r+0x5c>
+ 8022378:	4629      	mov	r1, r5
+ 802237a:	4630      	mov	r0, r6
+ 802237c:	f7ff fc2e 	bl	8021bdc <__swsetup_r>
+ 8022380:	b170      	cbz	r0, 80223a0 <_vfiprintf_r+0x5c>
+ 8022382:	6e6b      	ldr	r3, [r5, #100]	; 0x64
+ 8022384:	07dc      	lsls	r4, r3, #31
+ 8022386:	d504      	bpl.n	8022392 <_vfiprintf_r+0x4e>
+ 8022388:	f04f 30ff 	mov.w	r0, #4294967295
+ 802238c:	b01d      	add	sp, #116	; 0x74
+ 802238e:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
+ 8022392:	89ab      	ldrh	r3, [r5, #12]
+ 8022394:	0598      	lsls	r0, r3, #22
+ 8022396:	d4f7      	bmi.n	8022388 <_vfiprintf_r+0x44>
+ 8022398:	6da8      	ldr	r0, [r5, #88]	; 0x58
+ 802239a:	f7ff fd23 	bl	8021de4 <__retarget_lock_release_recursive>
+ 802239e:	e7f3      	b.n	8022388 <_vfiprintf_r+0x44>
+ 80223a0:	2300      	movs	r3, #0
+ 80223a2:	9309      	str	r3, [sp, #36]	; 0x24
+ 80223a4:	2320      	movs	r3, #32
+ 80223a6:	f88d 3029 	strb.w	r3, [sp, #41]	; 0x29
+ 80223aa:	f8cd 800c 	str.w	r8, [sp, #12]
+ 80223ae:	2330      	movs	r3, #48	; 0x30
+ 80223b0:	f8df 81b0 	ldr.w	r8, [pc, #432]	; 8022564 <_vfiprintf_r+0x220>
+ 80223b4:	f88d 302a 	strb.w	r3, [sp, #42]	; 0x2a
+ 80223b8:	f04f 0901 	mov.w	r9, #1
+ 80223bc:	4623      	mov	r3, r4
+ 80223be:	469a      	mov	sl, r3
+ 80223c0:	f813 2b01 	ldrb.w	r2, [r3], #1
+ 80223c4:	b10a      	cbz	r2, 80223ca <_vfiprintf_r+0x86>
+ 80223c6:	2a25      	cmp	r2, #37	; 0x25
+ 80223c8:	d1f9      	bne.n	80223be <_vfiprintf_r+0x7a>
+ 80223ca:	ebba 0b04 	subs.w	fp, sl, r4
+ 80223ce:	d00b      	beq.n	80223e8 <_vfiprintf_r+0xa4>
+ 80223d0:	465b      	mov	r3, fp
+ 80223d2:	4622      	mov	r2, r4
+ 80223d4:	4629      	mov	r1, r5
+ 80223d6:	4630      	mov	r0, r6
+ 80223d8:	f7ff ffa1 	bl	802231e <__sfputs_r>
+ 80223dc:	3001      	adds	r0, #1
+ 80223de:	f000 80a9 	beq.w	8022534 <_vfiprintf_r+0x1f0>
+ 80223e2:	9a09      	ldr	r2, [sp, #36]	; 0x24
+ 80223e4:	445a      	add	r2, fp
+ 80223e6:	9209      	str	r2, [sp, #36]	; 0x24
+ 80223e8:	f89a 3000 	ldrb.w	r3, [sl]
+ 80223ec:	2b00      	cmp	r3, #0
+ 80223ee:	f000 80a1 	beq.w	8022534 <_vfiprintf_r+0x1f0>
+ 80223f2:	2300      	movs	r3, #0
+ 80223f4:	f04f 32ff 	mov.w	r2, #4294967295
+ 80223f8:	e9cd 2305 	strd	r2, r3, [sp, #20]
+ 80223fc:	f10a 0a01 	add.w	sl, sl, #1
+ 8022400:	9304      	str	r3, [sp, #16]
+ 8022402:	9307      	str	r3, [sp, #28]
+ 8022404:	f88d 3053 	strb.w	r3, [sp, #83]	; 0x53
+ 8022408:	931a      	str	r3, [sp, #104]	; 0x68
+ 802240a:	4654      	mov	r4, sl
+ 802240c:	2205      	movs	r2, #5
+ 802240e:	f814 1b01 	ldrb.w	r1, [r4], #1
+ 8022412:	4854      	ldr	r0, [pc, #336]	; (8022564 <_vfiprintf_r+0x220>)
+ 8022414:	f7dd ff94 	bl	8000340 <memchr>
+ 8022418:	9a04      	ldr	r2, [sp, #16]
+ 802241a:	b9d8      	cbnz	r0, 8022454 <_vfiprintf_r+0x110>
+ 802241c:	06d1      	lsls	r1, r2, #27
+ 802241e:	bf44      	itt	mi
+ 8022420:	2320      	movmi	r3, #32
+ 8022422:	f88d 3053 	strbmi.w	r3, [sp, #83]	; 0x53
+ 8022426:	0713      	lsls	r3, r2, #28
+ 8022428:	bf44      	itt	mi
+ 802242a:	232b      	movmi	r3, #43	; 0x2b
+ 802242c:	f88d 3053 	strbmi.w	r3, [sp, #83]	; 0x53
+ 8022430:	f89a 3000 	ldrb.w	r3, [sl]
+ 8022434:	2b2a      	cmp	r3, #42	; 0x2a
+ 8022436:	d015      	beq.n	8022464 <_vfiprintf_r+0x120>
+ 8022438:	9a07      	ldr	r2, [sp, #28]
+ 802243a:	4654      	mov	r4, sl
+ 802243c:	2000      	movs	r0, #0
+ 802243e:	f04f 0c0a 	mov.w	ip, #10
+ 8022442:	4621      	mov	r1, r4
+ 8022444:	f811 3b01 	ldrb.w	r3, [r1], #1
+ 8022448:	3b30      	subs	r3, #48	; 0x30
+ 802244a:	2b09      	cmp	r3, #9
+ 802244c:	d94d      	bls.n	80224ea <_vfiprintf_r+0x1a6>
+ 802244e:	b1b0      	cbz	r0, 802247e <_vfiprintf_r+0x13a>
+ 8022450:	9207      	str	r2, [sp, #28]
+ 8022452:	e014      	b.n	802247e <_vfiprintf_r+0x13a>
+ 8022454:	eba0 0308 	sub.w	r3, r0, r8
+ 8022458:	fa09 f303 	lsl.w	r3, r9, r3
+ 802245c:	4313      	orrs	r3, r2
+ 802245e:	9304      	str	r3, [sp, #16]
+ 8022460:	46a2      	mov	sl, r4
+ 8022462:	e7d2      	b.n	802240a <_vfiprintf_r+0xc6>
+ 8022464:	9b03      	ldr	r3, [sp, #12]
+ 8022466:	1d19      	adds	r1, r3, #4
+ 8022468:	681b      	ldr	r3, [r3, #0]
+ 802246a:	9103      	str	r1, [sp, #12]
+ 802246c:	2b00      	cmp	r3, #0
+ 802246e:	bfbb      	ittet	lt
+ 8022470:	425b      	neglt	r3, r3
+ 8022472:	f042 0202 	orrlt.w	r2, r2, #2
+ 8022476:	9307      	strge	r3, [sp, #28]
+ 8022478:	9307      	strlt	r3, [sp, #28]
+ 802247a:	bfb8      	it	lt
+ 802247c:	9204      	strlt	r2, [sp, #16]
+ 802247e:	7823      	ldrb	r3, [r4, #0]
+ 8022480:	2b2e      	cmp	r3, #46	; 0x2e
+ 8022482:	d10c      	bne.n	802249e <_vfiprintf_r+0x15a>
+ 8022484:	7863      	ldrb	r3, [r4, #1]
+ 8022486:	2b2a      	cmp	r3, #42	; 0x2a
+ 8022488:	d134      	bne.n	80224f4 <_vfiprintf_r+0x1b0>
+ 802248a:	9b03      	ldr	r3, [sp, #12]
+ 802248c:	1d1a      	adds	r2, r3, #4
+ 802248e:	681b      	ldr	r3, [r3, #0]
+ 8022490:	9203      	str	r2, [sp, #12]
+ 8022492:	2b00      	cmp	r3, #0
+ 8022494:	bfb8      	it	lt
+ 8022496:	f04f 33ff 	movlt.w	r3, #4294967295
+ 802249a:	3402      	adds	r4, #2
+ 802249c:	9305      	str	r3, [sp, #20]
+ 802249e:	f8df a0d4 	ldr.w	sl, [pc, #212]	; 8022574 <_vfiprintf_r+0x230>
+ 80224a2:	7821      	ldrb	r1, [r4, #0]
+ 80224a4:	2203      	movs	r2, #3
+ 80224a6:	4650      	mov	r0, sl
+ 80224a8:	f7dd ff4a 	bl	8000340 <memchr>
+ 80224ac:	b138      	cbz	r0, 80224be <_vfiprintf_r+0x17a>
+ 80224ae:	9b04      	ldr	r3, [sp, #16]
+ 80224b0:	eba0 000a 	sub.w	r0, r0, sl
+ 80224b4:	2240      	movs	r2, #64	; 0x40
+ 80224b6:	4082      	lsls	r2, r0
+ 80224b8:	4313      	orrs	r3, r2
+ 80224ba:	3401      	adds	r4, #1
+ 80224bc:	9304      	str	r3, [sp, #16]
+ 80224be:	f814 1b01 	ldrb.w	r1, [r4], #1
+ 80224c2:	4829      	ldr	r0, [pc, #164]	; (8022568 <_vfiprintf_r+0x224>)
+ 80224c4:	f88d 1028 	strb.w	r1, [sp, #40]	; 0x28
+ 80224c8:	2206      	movs	r2, #6
+ 80224ca:	f7dd ff39 	bl	8000340 <memchr>
+ 80224ce:	2800      	cmp	r0, #0
+ 80224d0:	d03f      	beq.n	8022552 <_vfiprintf_r+0x20e>
+ 80224d2:	4b26      	ldr	r3, [pc, #152]	; (802256c <_vfiprintf_r+0x228>)
+ 80224d4:	bb1b      	cbnz	r3, 802251e <_vfiprintf_r+0x1da>
+ 80224d6:	9b03      	ldr	r3, [sp, #12]
+ 80224d8:	3307      	adds	r3, #7
+ 80224da:	f023 0307 	bic.w	r3, r3, #7
+ 80224de:	3308      	adds	r3, #8
+ 80224e0:	9303      	str	r3, [sp, #12]
+ 80224e2:	9b09      	ldr	r3, [sp, #36]	; 0x24
+ 80224e4:	443b      	add	r3, r7
+ 80224e6:	9309      	str	r3, [sp, #36]	; 0x24
+ 80224e8:	e768      	b.n	80223bc <_vfiprintf_r+0x78>
+ 80224ea:	fb0c 3202 	mla	r2, ip, r2, r3
+ 80224ee:	460c      	mov	r4, r1
+ 80224f0:	2001      	movs	r0, #1
+ 80224f2:	e7a6      	b.n	8022442 <_vfiprintf_r+0xfe>
+ 80224f4:	2300      	movs	r3, #0
+ 80224f6:	3401      	adds	r4, #1
+ 80224f8:	9305      	str	r3, [sp, #20]
+ 80224fa:	4619      	mov	r1, r3
+ 80224fc:	f04f 0c0a 	mov.w	ip, #10
+ 8022500:	4620      	mov	r0, r4
+ 8022502:	f810 2b01 	ldrb.w	r2, [r0], #1
+ 8022506:	3a30      	subs	r2, #48	; 0x30
+ 8022508:	2a09      	cmp	r2, #9
+ 802250a:	d903      	bls.n	8022514 <_vfiprintf_r+0x1d0>
+ 802250c:	2b00      	cmp	r3, #0
+ 802250e:	d0c6      	beq.n	802249e <_vfiprintf_r+0x15a>
+ 8022510:	9105      	str	r1, [sp, #20]
+ 8022512:	e7c4      	b.n	802249e <_vfiprintf_r+0x15a>
+ 8022514:	fb0c 2101 	mla	r1, ip, r1, r2
+ 8022518:	4604      	mov	r4, r0
+ 802251a:	2301      	movs	r3, #1
+ 802251c:	e7f0      	b.n	8022500 <_vfiprintf_r+0x1bc>
+ 802251e:	ab03      	add	r3, sp, #12
+ 8022520:	9300      	str	r3, [sp, #0]
+ 8022522:	462a      	mov	r2, r5
+ 8022524:	4b12      	ldr	r3, [pc, #72]	; (8022570 <_vfiprintf_r+0x22c>)
+ 8022526:	a904      	add	r1, sp, #16
+ 8022528:	4630      	mov	r0, r6
+ 802252a:	f3af 8000 	nop.w
+ 802252e:	4607      	mov	r7, r0
+ 8022530:	1c78      	adds	r0, r7, #1
+ 8022532:	d1d6      	bne.n	80224e2 <_vfiprintf_r+0x19e>
+ 8022534:	6e6b      	ldr	r3, [r5, #100]	; 0x64
+ 8022536:	07d9      	lsls	r1, r3, #31
+ 8022538:	d405      	bmi.n	8022546 <_vfiprintf_r+0x202>
+ 802253a:	89ab      	ldrh	r3, [r5, #12]
+ 802253c:	059a      	lsls	r2, r3, #22
+ 802253e:	d402      	bmi.n	8022546 <_vfiprintf_r+0x202>
+ 8022540:	6da8      	ldr	r0, [r5, #88]	; 0x58
+ 8022542:	f7ff fc4f 	bl	8021de4 <__retarget_lock_release_recursive>
+ 8022546:	89ab      	ldrh	r3, [r5, #12]
+ 8022548:	065b      	lsls	r3, r3, #25
+ 802254a:	f53f af1d 	bmi.w	8022388 <_vfiprintf_r+0x44>
+ 802254e:	9809      	ldr	r0, [sp, #36]	; 0x24
+ 8022550:	e71c      	b.n	802238c <_vfiprintf_r+0x48>
+ 8022552:	ab03      	add	r3, sp, #12
+ 8022554:	9300      	str	r3, [sp, #0]
+ 8022556:	462a      	mov	r2, r5
+ 8022558:	4b05      	ldr	r3, [pc, #20]	; (8022570 <_vfiprintf_r+0x22c>)
+ 802255a:	a904      	add	r1, sp, #16
+ 802255c:	4630      	mov	r0, r6
+ 802255e:	f000 f879 	bl	8022654 <_printf_i>
+ 8022562:	e7e4      	b.n	802252e <_vfiprintf_r+0x1ea>
+ 8022564:	08026eb4 	.word	0x08026eb4
+ 8022568:	08026ebe 	.word	0x08026ebe
+ 802256c:	00000000 	.word	0x00000000
+ 8022570:	0802231f 	.word	0x0802231f
+ 8022574:	08026eba 	.word	0x08026eba
+
+08022578 <_printf_common>:
+ 8022578:	e92d 47f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
+ 802257c:	4616      	mov	r6, r2
+ 802257e:	4699      	mov	r9, r3
+ 8022580:	688a      	ldr	r2, [r1, #8]
+ 8022582:	690b      	ldr	r3, [r1, #16]
+ 8022584:	f8dd 8020 	ldr.w	r8, [sp, #32]
+ 8022588:	4293      	cmp	r3, r2
+ 802258a:	bfb8      	it	lt
+ 802258c:	4613      	movlt	r3, r2
+ 802258e:	6033      	str	r3, [r6, #0]
+ 8022590:	f891 2043 	ldrb.w	r2, [r1, #67]	; 0x43
+ 8022594:	4607      	mov	r7, r0
+ 8022596:	460c      	mov	r4, r1
+ 8022598:	b10a      	cbz	r2, 802259e <_printf_common+0x26>
+ 802259a:	3301      	adds	r3, #1
+ 802259c:	6033      	str	r3, [r6, #0]
+ 802259e:	6823      	ldr	r3, [r4, #0]
+ 80225a0:	0699      	lsls	r1, r3, #26
+ 80225a2:	bf42      	ittt	mi
+ 80225a4:	6833      	ldrmi	r3, [r6, #0]
+ 80225a6:	3302      	addmi	r3, #2
+ 80225a8:	6033      	strmi	r3, [r6, #0]
+ 80225aa:	6825      	ldr	r5, [r4, #0]
+ 80225ac:	f015 0506 	ands.w	r5, r5, #6
+ 80225b0:	d106      	bne.n	80225c0 <_printf_common+0x48>
+ 80225b2:	f104 0a19 	add.w	sl, r4, #25
+ 80225b6:	68e3      	ldr	r3, [r4, #12]
+ 80225b8:	6832      	ldr	r2, [r6, #0]
+ 80225ba:	1a9b      	subs	r3, r3, r2
+ 80225bc:	42ab      	cmp	r3, r5
+ 80225be:	dc26      	bgt.n	802260e <_printf_common+0x96>
+ 80225c0:	f894 2043 	ldrb.w	r2, [r4, #67]	; 0x43
+ 80225c4:	1e13      	subs	r3, r2, #0
+ 80225c6:	6822      	ldr	r2, [r4, #0]
+ 80225c8:	bf18      	it	ne
+ 80225ca:	2301      	movne	r3, #1
+ 80225cc:	0692      	lsls	r2, r2, #26
+ 80225ce:	d42b      	bmi.n	8022628 <_printf_common+0xb0>
+ 80225d0:	f104 0243 	add.w	r2, r4, #67	; 0x43
+ 80225d4:	4649      	mov	r1, r9
+ 80225d6:	4638      	mov	r0, r7
+ 80225d8:	47c0      	blx	r8
+ 80225da:	3001      	adds	r0, #1
+ 80225dc:	d01e      	beq.n	802261c <_printf_common+0xa4>
+ 80225de:	6823      	ldr	r3, [r4, #0]
+ 80225e0:	6922      	ldr	r2, [r4, #16]
+ 80225e2:	f003 0306 	and.w	r3, r3, #6
+ 80225e6:	2b04      	cmp	r3, #4
+ 80225e8:	bf02      	ittt	eq
+ 80225ea:	68e5      	ldreq	r5, [r4, #12]
+ 80225ec:	6833      	ldreq	r3, [r6, #0]
+ 80225ee:	1aed      	subeq	r5, r5, r3
+ 80225f0:	68a3      	ldr	r3, [r4, #8]
+ 80225f2:	bf0c      	ite	eq
+ 80225f4:	ea25 75e5 	biceq.w	r5, r5, r5, asr #31
+ 80225f8:	2500      	movne	r5, #0
+ 80225fa:	4293      	cmp	r3, r2
+ 80225fc:	bfc4      	itt	gt
+ 80225fe:	1a9b      	subgt	r3, r3, r2
+ 8022600:	18ed      	addgt	r5, r5, r3
+ 8022602:	2600      	movs	r6, #0
+ 8022604:	341a      	adds	r4, #26
+ 8022606:	42b5      	cmp	r5, r6
+ 8022608:	d11a      	bne.n	8022640 <_printf_common+0xc8>
+ 802260a:	2000      	movs	r0, #0
+ 802260c:	e008      	b.n	8022620 <_printf_common+0xa8>
+ 802260e:	2301      	movs	r3, #1
+ 8022610:	4652      	mov	r2, sl
+ 8022612:	4649      	mov	r1, r9
+ 8022614:	4638      	mov	r0, r7
+ 8022616:	47c0      	blx	r8
+ 8022618:	3001      	adds	r0, #1
+ 802261a:	d103      	bne.n	8022624 <_printf_common+0xac>
+ 802261c:	f04f 30ff 	mov.w	r0, #4294967295
+ 8022620:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
+ 8022624:	3501      	adds	r5, #1
+ 8022626:	e7c6      	b.n	80225b6 <_printf_common+0x3e>
+ 8022628:	18e1      	adds	r1, r4, r3
+ 802262a:	1c5a      	adds	r2, r3, #1
+ 802262c:	2030      	movs	r0, #48	; 0x30
+ 802262e:	f881 0043 	strb.w	r0, [r1, #67]	; 0x43
+ 8022632:	4422      	add	r2, r4
+ 8022634:	f894 1045 	ldrb.w	r1, [r4, #69]	; 0x45
+ 8022638:	f882 1043 	strb.w	r1, [r2, #67]	; 0x43
+ 802263c:	3302      	adds	r3, #2
+ 802263e:	e7c7      	b.n	80225d0 <_printf_common+0x58>
+ 8022640:	2301      	movs	r3, #1
+ 8022642:	4622      	mov	r2, r4
+ 8022644:	4649      	mov	r1, r9
+ 8022646:	4638      	mov	r0, r7
+ 8022648:	47c0      	blx	r8
+ 802264a:	3001      	adds	r0, #1
+ 802264c:	d0e6      	beq.n	802261c <_printf_common+0xa4>
+ 802264e:	3601      	adds	r6, #1
+ 8022650:	e7d9      	b.n	8022606 <_printf_common+0x8e>
+	...
+
+08022654 <_printf_i>:
+ 8022654:	e92d 47ff 	stmdb	sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, lr}
+ 8022658:	7e0f      	ldrb	r7, [r1, #24]
+ 802265a:	9d0c      	ldr	r5, [sp, #48]	; 0x30
+ 802265c:	2f78      	cmp	r7, #120	; 0x78
+ 802265e:	4691      	mov	r9, r2
+ 8022660:	4680      	mov	r8, r0
+ 8022662:	460c      	mov	r4, r1
+ 8022664:	469a      	mov	sl, r3
+ 8022666:	f101 0243 	add.w	r2, r1, #67	; 0x43
+ 802266a:	d807      	bhi.n	802267c <_printf_i+0x28>
+ 802266c:	2f62      	cmp	r7, #98	; 0x62
+ 802266e:	d80a      	bhi.n	8022686 <_printf_i+0x32>
+ 8022670:	2f00      	cmp	r7, #0
+ 8022672:	f000 80d4 	beq.w	802281e <_printf_i+0x1ca>
+ 8022676:	2f58      	cmp	r7, #88	; 0x58
+ 8022678:	f000 80c0 	beq.w	80227fc <_printf_i+0x1a8>
+ 802267c:	f104 0542 	add.w	r5, r4, #66	; 0x42
+ 8022680:	f884 7042 	strb.w	r7, [r4, #66]	; 0x42
+ 8022684:	e03a      	b.n	80226fc <_printf_i+0xa8>
+ 8022686:	f1a7 0363 	sub.w	r3, r7, #99	; 0x63
+ 802268a:	2b15      	cmp	r3, #21
+ 802268c:	d8f6      	bhi.n	802267c <_printf_i+0x28>
+ 802268e:	a101      	add	r1, pc, #4	; (adr r1, 8022694 <_printf_i+0x40>)
+ 8022690:	f851 f023 	ldr.w	pc, [r1, r3, lsl #2]
+ 8022694:	080226ed 	.word	0x080226ed
+ 8022698:	08022701 	.word	0x08022701
+ 802269c:	0802267d 	.word	0x0802267d
+ 80226a0:	0802267d 	.word	0x0802267d
+ 80226a4:	0802267d 	.word	0x0802267d
+ 80226a8:	0802267d 	.word	0x0802267d
+ 80226ac:	08022701 	.word	0x08022701
+ 80226b0:	0802267d 	.word	0x0802267d
+ 80226b4:	0802267d 	.word	0x0802267d
+ 80226b8:	0802267d 	.word	0x0802267d
+ 80226bc:	0802267d 	.word	0x0802267d
+ 80226c0:	08022805 	.word	0x08022805
+ 80226c4:	0802272d 	.word	0x0802272d
+ 80226c8:	080227bf 	.word	0x080227bf
+ 80226cc:	0802267d 	.word	0x0802267d
+ 80226d0:	0802267d 	.word	0x0802267d
+ 80226d4:	08022827 	.word	0x08022827
+ 80226d8:	0802267d 	.word	0x0802267d
+ 80226dc:	0802272d 	.word	0x0802272d
+ 80226e0:	0802267d 	.word	0x0802267d
+ 80226e4:	0802267d 	.word	0x0802267d
+ 80226e8:	080227c7 	.word	0x080227c7
+ 80226ec:	682b      	ldr	r3, [r5, #0]
+ 80226ee:	1d1a      	adds	r2, r3, #4
+ 80226f0:	681b      	ldr	r3, [r3, #0]
+ 80226f2:	602a      	str	r2, [r5, #0]
+ 80226f4:	f104 0542 	add.w	r5, r4, #66	; 0x42
+ 80226f8:	f884 3042 	strb.w	r3, [r4, #66]	; 0x42
+ 80226fc:	2301      	movs	r3, #1
+ 80226fe:	e09f      	b.n	8022840 <_printf_i+0x1ec>
+ 8022700:	6820      	ldr	r0, [r4, #0]
+ 8022702:	682b      	ldr	r3, [r5, #0]
+ 8022704:	0607      	lsls	r7, r0, #24
+ 8022706:	f103 0104 	add.w	r1, r3, #4
+ 802270a:	6029      	str	r1, [r5, #0]
+ 802270c:	d501      	bpl.n	8022712 <_printf_i+0xbe>
+ 802270e:	681e      	ldr	r6, [r3, #0]
+ 8022710:	e003      	b.n	802271a <_printf_i+0xc6>
+ 8022712:	0646      	lsls	r6, r0, #25
+ 8022714:	d5fb      	bpl.n	802270e <_printf_i+0xba>
+ 8022716:	f9b3 6000 	ldrsh.w	r6, [r3]
+ 802271a:	2e00      	cmp	r6, #0
+ 802271c:	da03      	bge.n	8022726 <_printf_i+0xd2>
+ 802271e:	232d      	movs	r3, #45	; 0x2d
+ 8022720:	4276      	negs	r6, r6
+ 8022722:	f884 3043 	strb.w	r3, [r4, #67]	; 0x43
+ 8022726:	485a      	ldr	r0, [pc, #360]	; (8022890 <_printf_i+0x23c>)
+ 8022728:	230a      	movs	r3, #10
+ 802272a:	e012      	b.n	8022752 <_printf_i+0xfe>
+ 802272c:	682b      	ldr	r3, [r5, #0]
+ 802272e:	6820      	ldr	r0, [r4, #0]
+ 8022730:	1d19      	adds	r1, r3, #4
+ 8022732:	6029      	str	r1, [r5, #0]
+ 8022734:	0605      	lsls	r5, r0, #24
+ 8022736:	d501      	bpl.n	802273c <_printf_i+0xe8>
+ 8022738:	681e      	ldr	r6, [r3, #0]
+ 802273a:	e002      	b.n	8022742 <_printf_i+0xee>
+ 802273c:	0641      	lsls	r1, r0, #25
+ 802273e:	d5fb      	bpl.n	8022738 <_printf_i+0xe4>
+ 8022740:	881e      	ldrh	r6, [r3, #0]
+ 8022742:	4853      	ldr	r0, [pc, #332]	; (8022890 <_printf_i+0x23c>)
+ 8022744:	2f6f      	cmp	r7, #111	; 0x6f
+ 8022746:	bf0c      	ite	eq
+ 8022748:	2308      	moveq	r3, #8
+ 802274a:	230a      	movne	r3, #10
+ 802274c:	2100      	movs	r1, #0
+ 802274e:	f884 1043 	strb.w	r1, [r4, #67]	; 0x43
+ 8022752:	6865      	ldr	r5, [r4, #4]
+ 8022754:	60a5      	str	r5, [r4, #8]
+ 8022756:	2d00      	cmp	r5, #0
+ 8022758:	bfa2      	ittt	ge
+ 802275a:	6821      	ldrge	r1, [r4, #0]
+ 802275c:	f021 0104 	bicge.w	r1, r1, #4
+ 8022760:	6021      	strge	r1, [r4, #0]
+ 8022762:	b90e      	cbnz	r6, 8022768 <_printf_i+0x114>
+ 8022764:	2d00      	cmp	r5, #0
+ 8022766:	d04b      	beq.n	8022800 <_printf_i+0x1ac>
+ 8022768:	4615      	mov	r5, r2
+ 802276a:	fbb6 f1f3 	udiv	r1, r6, r3
+ 802276e:	fb03 6711 	mls	r7, r3, r1, r6
+ 8022772:	5dc7      	ldrb	r7, [r0, r7]
+ 8022774:	f805 7d01 	strb.w	r7, [r5, #-1]!
+ 8022778:	4637      	mov	r7, r6
+ 802277a:	42bb      	cmp	r3, r7
+ 802277c:	460e      	mov	r6, r1
+ 802277e:	d9f4      	bls.n	802276a <_printf_i+0x116>
+ 8022780:	2b08      	cmp	r3, #8
+ 8022782:	d10b      	bne.n	802279c <_printf_i+0x148>
+ 8022784:	6823      	ldr	r3, [r4, #0]
+ 8022786:	07de      	lsls	r6, r3, #31
+ 8022788:	d508      	bpl.n	802279c <_printf_i+0x148>
+ 802278a:	6923      	ldr	r3, [r4, #16]
+ 802278c:	6861      	ldr	r1, [r4, #4]
+ 802278e:	4299      	cmp	r1, r3
+ 8022790:	bfde      	ittt	le
+ 8022792:	2330      	movle	r3, #48	; 0x30
+ 8022794:	f805 3c01 	strble.w	r3, [r5, #-1]
+ 8022798:	f105 35ff 	addle.w	r5, r5, #4294967295
+ 802279c:	1b52      	subs	r2, r2, r5
+ 802279e:	6122      	str	r2, [r4, #16]
+ 80227a0:	f8cd a000 	str.w	sl, [sp]
+ 80227a4:	464b      	mov	r3, r9
+ 80227a6:	aa03      	add	r2, sp, #12
+ 80227a8:	4621      	mov	r1, r4
+ 80227aa:	4640      	mov	r0, r8
+ 80227ac:	f7ff fee4 	bl	8022578 <_printf_common>
+ 80227b0:	3001      	adds	r0, #1
+ 80227b2:	d14a      	bne.n	802284a <_printf_i+0x1f6>
+ 80227b4:	f04f 30ff 	mov.w	r0, #4294967295
+ 80227b8:	b004      	add	sp, #16
+ 80227ba:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
+ 80227be:	6823      	ldr	r3, [r4, #0]
+ 80227c0:	f043 0320 	orr.w	r3, r3, #32
+ 80227c4:	6023      	str	r3, [r4, #0]
+ 80227c6:	4833      	ldr	r0, [pc, #204]	; (8022894 <_printf_i+0x240>)
+ 80227c8:	2778      	movs	r7, #120	; 0x78
+ 80227ca:	f884 7045 	strb.w	r7, [r4, #69]	; 0x45
+ 80227ce:	6823      	ldr	r3, [r4, #0]
+ 80227d0:	6829      	ldr	r1, [r5, #0]
+ 80227d2:	061f      	lsls	r7, r3, #24
+ 80227d4:	f851 6b04 	ldr.w	r6, [r1], #4
+ 80227d8:	d402      	bmi.n	80227e0 <_printf_i+0x18c>
+ 80227da:	065f      	lsls	r7, r3, #25
+ 80227dc:	bf48      	it	mi
+ 80227de:	b2b6      	uxthmi	r6, r6
+ 80227e0:	07df      	lsls	r7, r3, #31
+ 80227e2:	bf48      	it	mi
+ 80227e4:	f043 0320 	orrmi.w	r3, r3, #32
+ 80227e8:	6029      	str	r1, [r5, #0]
+ 80227ea:	bf48      	it	mi
+ 80227ec:	6023      	strmi	r3, [r4, #0]
+ 80227ee:	b91e      	cbnz	r6, 80227f8 <_printf_i+0x1a4>
+ 80227f0:	6823      	ldr	r3, [r4, #0]
+ 80227f2:	f023 0320 	bic.w	r3, r3, #32
+ 80227f6:	6023      	str	r3, [r4, #0]
+ 80227f8:	2310      	movs	r3, #16
+ 80227fa:	e7a7      	b.n	802274c <_printf_i+0xf8>
+ 80227fc:	4824      	ldr	r0, [pc, #144]	; (8022890 <_printf_i+0x23c>)
+ 80227fe:	e7e4      	b.n	80227ca <_printf_i+0x176>
+ 8022800:	4615      	mov	r5, r2
+ 8022802:	e7bd      	b.n	8022780 <_printf_i+0x12c>
+ 8022804:	682b      	ldr	r3, [r5, #0]
+ 8022806:	6826      	ldr	r6, [r4, #0]
+ 8022808:	6961      	ldr	r1, [r4, #20]
+ 802280a:	1d18      	adds	r0, r3, #4
+ 802280c:	6028      	str	r0, [r5, #0]
+ 802280e:	0635      	lsls	r5, r6, #24
+ 8022810:	681b      	ldr	r3, [r3, #0]
+ 8022812:	d501      	bpl.n	8022818 <_printf_i+0x1c4>
+ 8022814:	6019      	str	r1, [r3, #0]
+ 8022816:	e002      	b.n	802281e <_printf_i+0x1ca>
+ 8022818:	0670      	lsls	r0, r6, #25
+ 802281a:	d5fb      	bpl.n	8022814 <_printf_i+0x1c0>
+ 802281c:	8019      	strh	r1, [r3, #0]
+ 802281e:	2300      	movs	r3, #0
+ 8022820:	6123      	str	r3, [r4, #16]
+ 8022822:	4615      	mov	r5, r2
+ 8022824:	e7bc      	b.n	80227a0 <_printf_i+0x14c>
+ 8022826:	682b      	ldr	r3, [r5, #0]
+ 8022828:	1d1a      	adds	r2, r3, #4
+ 802282a:	602a      	str	r2, [r5, #0]
+ 802282c:	681d      	ldr	r5, [r3, #0]
+ 802282e:	6862      	ldr	r2, [r4, #4]
+ 8022830:	2100      	movs	r1, #0
+ 8022832:	4628      	mov	r0, r5
+ 8022834:	f7dd fd84 	bl	8000340 <memchr>
+ 8022838:	b108      	cbz	r0, 802283e <_printf_i+0x1ea>
+ 802283a:	1b40      	subs	r0, r0, r5
+ 802283c:	6060      	str	r0, [r4, #4]
+ 802283e:	6863      	ldr	r3, [r4, #4]
+ 8022840:	6123      	str	r3, [r4, #16]
+ 8022842:	2300      	movs	r3, #0
+ 8022844:	f884 3043 	strb.w	r3, [r4, #67]	; 0x43
+ 8022848:	e7aa      	b.n	80227a0 <_printf_i+0x14c>
+ 802284a:	6923      	ldr	r3, [r4, #16]
+ 802284c:	462a      	mov	r2, r5
+ 802284e:	4649      	mov	r1, r9
+ 8022850:	4640      	mov	r0, r8
+ 8022852:	47d0      	blx	sl
+ 8022854:	3001      	adds	r0, #1
+ 8022856:	d0ad      	beq.n	80227b4 <_printf_i+0x160>
+ 8022858:	6823      	ldr	r3, [r4, #0]
+ 802285a:	079b      	lsls	r3, r3, #30
+ 802285c:	d413      	bmi.n	8022886 <_printf_i+0x232>
+ 802285e:	68e0      	ldr	r0, [r4, #12]
+ 8022860:	9b03      	ldr	r3, [sp, #12]
+ 8022862:	4298      	cmp	r0, r3
+ 8022864:	bfb8      	it	lt
+ 8022866:	4618      	movlt	r0, r3
+ 8022868:	e7a6      	b.n	80227b8 <_printf_i+0x164>
+ 802286a:	2301      	movs	r3, #1
+ 802286c:	4632      	mov	r2, r6
+ 802286e:	4649      	mov	r1, r9
+ 8022870:	4640      	mov	r0, r8
+ 8022872:	47d0      	blx	sl
+ 8022874:	3001      	adds	r0, #1
+ 8022876:	d09d      	beq.n	80227b4 <_printf_i+0x160>
+ 8022878:	3501      	adds	r5, #1
+ 802287a:	68e3      	ldr	r3, [r4, #12]
+ 802287c:	9903      	ldr	r1, [sp, #12]
+ 802287e:	1a5b      	subs	r3, r3, r1
+ 8022880:	42ab      	cmp	r3, r5
+ 8022882:	dcf2      	bgt.n	802286a <_printf_i+0x216>
+ 8022884:	e7eb      	b.n	802285e <_printf_i+0x20a>
+ 8022886:	2500      	movs	r5, #0
+ 8022888:	f104 0619 	add.w	r6, r4, #25
+ 802288c:	e7f5      	b.n	802287a <_printf_i+0x226>
+ 802288e:	bf00      	nop
+ 8022890:	08026ec5 	.word	0x08026ec5
+ 8022894:	08026ed6 	.word	0x08026ed6
+
+08022898 <__sflush_r>:
+ 8022898:	898a      	ldrh	r2, [r1, #12]
+ 802289a:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
+ 802289e:	4605      	mov	r5, r0
+ 80228a0:	0710      	lsls	r0, r2, #28
+ 80228a2:	460c      	mov	r4, r1
+ 80228a4:	d458      	bmi.n	8022958 <__sflush_r+0xc0>
+ 80228a6:	684b      	ldr	r3, [r1, #4]
+ 80228a8:	2b00      	cmp	r3, #0
+ 80228aa:	dc05      	bgt.n	80228b8 <__sflush_r+0x20>
+ 80228ac:	6c0b      	ldr	r3, [r1, #64]	; 0x40
+ 80228ae:	2b00      	cmp	r3, #0
+ 80228b0:	dc02      	bgt.n	80228b8 <__sflush_r+0x20>
+ 80228b2:	2000      	movs	r0, #0
+ 80228b4:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
+ 80228b8:	6ae6      	ldr	r6, [r4, #44]	; 0x2c
+ 80228ba:	2e00      	cmp	r6, #0
+ 80228bc:	d0f9      	beq.n	80228b2 <__sflush_r+0x1a>
+ 80228be:	2300      	movs	r3, #0
+ 80228c0:	f412 5280 	ands.w	r2, r2, #4096	; 0x1000
+ 80228c4:	682f      	ldr	r7, [r5, #0]
+ 80228c6:	6a21      	ldr	r1, [r4, #32]
+ 80228c8:	602b      	str	r3, [r5, #0]
+ 80228ca:	d032      	beq.n	8022932 <__sflush_r+0x9a>
+ 80228cc:	6d60      	ldr	r0, [r4, #84]	; 0x54
+ 80228ce:	89a3      	ldrh	r3, [r4, #12]
+ 80228d0:	075a      	lsls	r2, r3, #29
+ 80228d2:	d505      	bpl.n	80228e0 <__sflush_r+0x48>
+ 80228d4:	6863      	ldr	r3, [r4, #4]
+ 80228d6:	1ac0      	subs	r0, r0, r3
+ 80228d8:	6b63      	ldr	r3, [r4, #52]	; 0x34
+ 80228da:	b10b      	cbz	r3, 80228e0 <__sflush_r+0x48>
+ 80228dc:	6c23      	ldr	r3, [r4, #64]	; 0x40
+ 80228de:	1ac0      	subs	r0, r0, r3
+ 80228e0:	2300      	movs	r3, #0
+ 80228e2:	4602      	mov	r2, r0
+ 80228e4:	6ae6      	ldr	r6, [r4, #44]	; 0x2c
+ 80228e6:	6a21      	ldr	r1, [r4, #32]
+ 80228e8:	4628      	mov	r0, r5
+ 80228ea:	47b0      	blx	r6
+ 80228ec:	1c43      	adds	r3, r0, #1
+ 80228ee:	89a3      	ldrh	r3, [r4, #12]
+ 80228f0:	d106      	bne.n	8022900 <__sflush_r+0x68>
+ 80228f2:	6829      	ldr	r1, [r5, #0]
+ 80228f4:	291d      	cmp	r1, #29
+ 80228f6:	d82b      	bhi.n	8022950 <__sflush_r+0xb8>
+ 80228f8:	4a29      	ldr	r2, [pc, #164]	; (80229a0 <__sflush_r+0x108>)
+ 80228fa:	410a      	asrs	r2, r1
+ 80228fc:	07d6      	lsls	r6, r2, #31
+ 80228fe:	d427      	bmi.n	8022950 <__sflush_r+0xb8>
+ 8022900:	2200      	movs	r2, #0
+ 8022902:	6062      	str	r2, [r4, #4]
+ 8022904:	04d9      	lsls	r1, r3, #19
+ 8022906:	6922      	ldr	r2, [r4, #16]
+ 8022908:	6022      	str	r2, [r4, #0]
+ 802290a:	d504      	bpl.n	8022916 <__sflush_r+0x7e>
+ 802290c:	1c42      	adds	r2, r0, #1
+ 802290e:	d101      	bne.n	8022914 <__sflush_r+0x7c>
+ 8022910:	682b      	ldr	r3, [r5, #0]
+ 8022912:	b903      	cbnz	r3, 8022916 <__sflush_r+0x7e>
+ 8022914:	6560      	str	r0, [r4, #84]	; 0x54
+ 8022916:	6b61      	ldr	r1, [r4, #52]	; 0x34
+ 8022918:	602f      	str	r7, [r5, #0]
+ 802291a:	2900      	cmp	r1, #0
+ 802291c:	d0c9      	beq.n	80228b2 <__sflush_r+0x1a>
+ 802291e:	f104 0344 	add.w	r3, r4, #68	; 0x44
+ 8022922:	4299      	cmp	r1, r3
+ 8022924:	d002      	beq.n	802292c <__sflush_r+0x94>
+ 8022926:	4628      	mov	r0, r5
+ 8022928:	f7ff fa8a 	bl	8021e40 <_free_r>
+ 802292c:	2000      	movs	r0, #0
+ 802292e:	6360      	str	r0, [r4, #52]	; 0x34
+ 8022930:	e7c0      	b.n	80228b4 <__sflush_r+0x1c>
+ 8022932:	2301      	movs	r3, #1
+ 8022934:	4628      	mov	r0, r5
+ 8022936:	47b0      	blx	r6
+ 8022938:	1c41      	adds	r1, r0, #1
+ 802293a:	d1c8      	bne.n	80228ce <__sflush_r+0x36>
+ 802293c:	682b      	ldr	r3, [r5, #0]
+ 802293e:	2b00      	cmp	r3, #0
+ 8022940:	d0c5      	beq.n	80228ce <__sflush_r+0x36>
+ 8022942:	2b1d      	cmp	r3, #29
+ 8022944:	d001      	beq.n	802294a <__sflush_r+0xb2>
+ 8022946:	2b16      	cmp	r3, #22
+ 8022948:	d101      	bne.n	802294e <__sflush_r+0xb6>
+ 802294a:	602f      	str	r7, [r5, #0]
+ 802294c:	e7b1      	b.n	80228b2 <__sflush_r+0x1a>
+ 802294e:	89a3      	ldrh	r3, [r4, #12]
+ 8022950:	f043 0340 	orr.w	r3, r3, #64	; 0x40
+ 8022954:	81a3      	strh	r3, [r4, #12]
+ 8022956:	e7ad      	b.n	80228b4 <__sflush_r+0x1c>
+ 8022958:	690f      	ldr	r7, [r1, #16]
+ 802295a:	2f00      	cmp	r7, #0
+ 802295c:	d0a9      	beq.n	80228b2 <__sflush_r+0x1a>
+ 802295e:	0793      	lsls	r3, r2, #30
+ 8022960:	680e      	ldr	r6, [r1, #0]
+ 8022962:	bf08      	it	eq
+ 8022964:	694b      	ldreq	r3, [r1, #20]
+ 8022966:	600f      	str	r7, [r1, #0]
+ 8022968:	bf18      	it	ne
+ 802296a:	2300      	movne	r3, #0
+ 802296c:	eba6 0807 	sub.w	r8, r6, r7
+ 8022970:	608b      	str	r3, [r1, #8]
+ 8022972:	f1b8 0f00 	cmp.w	r8, #0
+ 8022976:	dd9c      	ble.n	80228b2 <__sflush_r+0x1a>
+ 8022978:	6a21      	ldr	r1, [r4, #32]
+ 802297a:	6aa6      	ldr	r6, [r4, #40]	; 0x28
+ 802297c:	4643      	mov	r3, r8
+ 802297e:	463a      	mov	r2, r7
+ 8022980:	4628      	mov	r0, r5
+ 8022982:	47b0      	blx	r6
+ 8022984:	2800      	cmp	r0, #0
+ 8022986:	dc06      	bgt.n	8022996 <__sflush_r+0xfe>
+ 8022988:	89a3      	ldrh	r3, [r4, #12]
+ 802298a:	f043 0340 	orr.w	r3, r3, #64	; 0x40
+ 802298e:	81a3      	strh	r3, [r4, #12]
+ 8022990:	f04f 30ff 	mov.w	r0, #4294967295
+ 8022994:	e78e      	b.n	80228b4 <__sflush_r+0x1c>
+ 8022996:	4407      	add	r7, r0
+ 8022998:	eba8 0800 	sub.w	r8, r8, r0
+ 802299c:	e7e9      	b.n	8022972 <__sflush_r+0xda>
+ 802299e:	bf00      	nop
+ 80229a0:	dfbffffe 	.word	0xdfbffffe
+
+080229a4 <_fflush_r>:
+ 80229a4:	b538      	push	{r3, r4, r5, lr}
+ 80229a6:	690b      	ldr	r3, [r1, #16]
+ 80229a8:	4605      	mov	r5, r0
+ 80229aa:	460c      	mov	r4, r1
+ 80229ac:	b913      	cbnz	r3, 80229b4 <_fflush_r+0x10>
+ 80229ae:	2500      	movs	r5, #0
+ 80229b0:	4628      	mov	r0, r5
+ 80229b2:	bd38      	pop	{r3, r4, r5, pc}
+ 80229b4:	b118      	cbz	r0, 80229be <_fflush_r+0x1a>
+ 80229b6:	6a03      	ldr	r3, [r0, #32]
+ 80229b8:	b90b      	cbnz	r3, 80229be <_fflush_r+0x1a>
+ 80229ba:	f7fe ffaf 	bl	802191c <__sinit>
+ 80229be:	f9b4 300c 	ldrsh.w	r3, [r4, #12]
+ 80229c2:	2b00      	cmp	r3, #0
+ 80229c4:	d0f3      	beq.n	80229ae <_fflush_r+0xa>
+ 80229c6:	6e62      	ldr	r2, [r4, #100]	; 0x64
+ 80229c8:	07d0      	lsls	r0, r2, #31
+ 80229ca:	d404      	bmi.n	80229d6 <_fflush_r+0x32>
+ 80229cc:	0599      	lsls	r1, r3, #22
+ 80229ce:	d402      	bmi.n	80229d6 <_fflush_r+0x32>
+ 80229d0:	6da0      	ldr	r0, [r4, #88]	; 0x58
+ 80229d2:	f7ff fa06 	bl	8021de2 <__retarget_lock_acquire_recursive>
+ 80229d6:	4628      	mov	r0, r5
+ 80229d8:	4621      	mov	r1, r4
+ 80229da:	f7ff ff5d 	bl	8022898 <__sflush_r>
+ 80229de:	6e63      	ldr	r3, [r4, #100]	; 0x64
+ 80229e0:	07da      	lsls	r2, r3, #31
+ 80229e2:	4605      	mov	r5, r0
+ 80229e4:	d4e4      	bmi.n	80229b0 <_fflush_r+0xc>
+ 80229e6:	89a3      	ldrh	r3, [r4, #12]
+ 80229e8:	059b      	lsls	r3, r3, #22
+ 80229ea:	d4e1      	bmi.n	80229b0 <_fflush_r+0xc>
+ 80229ec:	6da0      	ldr	r0, [r4, #88]	; 0x58
+ 80229ee:	f7ff f9f9 	bl	8021de4 <__retarget_lock_release_recursive>
+ 80229f2:	e7dd      	b.n	80229b0 <_fflush_r+0xc>
+
+080229f4 <fiprintf>:
+ 80229f4:	b40e      	push	{r1, r2, r3}
+ 80229f6:	b503      	push	{r0, r1, lr}
+ 80229f8:	4601      	mov	r1, r0
+ 80229fa:	ab03      	add	r3, sp, #12
+ 80229fc:	4805      	ldr	r0, [pc, #20]	; (8022a14 <fiprintf+0x20>)
+ 80229fe:	f853 2b04 	ldr.w	r2, [r3], #4
+ 8022a02:	6800      	ldr	r0, [r0, #0]
+ 8022a04:	9301      	str	r3, [sp, #4]
+ 8022a06:	f7ff fc9d 	bl	8022344 <_vfiprintf_r>
+ 8022a0a:	b002      	add	sp, #8
+ 8022a0c:	f85d eb04 	ldr.w	lr, [sp], #4
+ 8022a10:	b003      	add	sp, #12
+ 8022a12:	4770      	bx	lr
+ 8022a14:	240000a0 	.word	0x240000a0
+
+08022a18 <__swhatbuf_r>:
+ 8022a18:	b570      	push	{r4, r5, r6, lr}
+ 8022a1a:	460c      	mov	r4, r1
+ 8022a1c:	f9b1 100e 	ldrsh.w	r1, [r1, #14]
+ 8022a20:	2900      	cmp	r1, #0
+ 8022a22:	b096      	sub	sp, #88	; 0x58
+ 8022a24:	4615      	mov	r5, r2
+ 8022a26:	461e      	mov	r6, r3
+ 8022a28:	da0d      	bge.n	8022a46 <__swhatbuf_r+0x2e>
+ 8022a2a:	89a3      	ldrh	r3, [r4, #12]
+ 8022a2c:	f013 0f80 	tst.w	r3, #128	; 0x80
+ 8022a30:	f04f 0100 	mov.w	r1, #0
+ 8022a34:	bf0c      	ite	eq
+ 8022a36:	f44f 6380 	moveq.w	r3, #1024	; 0x400
+ 8022a3a:	2340      	movne	r3, #64	; 0x40
+ 8022a3c:	2000      	movs	r0, #0
+ 8022a3e:	6031      	str	r1, [r6, #0]
+ 8022a40:	602b      	str	r3, [r5, #0]
+ 8022a42:	b016      	add	sp, #88	; 0x58
+ 8022a44:	bd70      	pop	{r4, r5, r6, pc}
+ 8022a46:	466a      	mov	r2, sp
+ 8022a48:	f000 f87c 	bl	8022b44 <_fstat_r>
+ 8022a4c:	2800      	cmp	r0, #0
+ 8022a4e:	dbec      	blt.n	8022a2a <__swhatbuf_r+0x12>
+ 8022a50:	9901      	ldr	r1, [sp, #4]
+ 8022a52:	f401 4170 	and.w	r1, r1, #61440	; 0xf000
+ 8022a56:	f5a1 5300 	sub.w	r3, r1, #8192	; 0x2000
+ 8022a5a:	4259      	negs	r1, r3
+ 8022a5c:	4159      	adcs	r1, r3
+ 8022a5e:	f44f 6380 	mov.w	r3, #1024	; 0x400
+ 8022a62:	e7eb      	b.n	8022a3c <__swhatbuf_r+0x24>
+
+08022a64 <__smakebuf_r>:
+ 8022a64:	898b      	ldrh	r3, [r1, #12]
+ 8022a66:	b573      	push	{r0, r1, r4, r5, r6, lr}
+ 8022a68:	079d      	lsls	r5, r3, #30
+ 8022a6a:	4606      	mov	r6, r0
+ 8022a6c:	460c      	mov	r4, r1
+ 8022a6e:	d507      	bpl.n	8022a80 <__smakebuf_r+0x1c>
+ 8022a70:	f104 0347 	add.w	r3, r4, #71	; 0x47
+ 8022a74:	6023      	str	r3, [r4, #0]
+ 8022a76:	6123      	str	r3, [r4, #16]
+ 8022a78:	2301      	movs	r3, #1
+ 8022a7a:	6163      	str	r3, [r4, #20]
+ 8022a7c:	b002      	add	sp, #8
+ 8022a7e:	bd70      	pop	{r4, r5, r6, pc}
+ 8022a80:	ab01      	add	r3, sp, #4
+ 8022a82:	466a      	mov	r2, sp
+ 8022a84:	f7ff ffc8 	bl	8022a18 <__swhatbuf_r>
+ 8022a88:	9900      	ldr	r1, [sp, #0]
+ 8022a8a:	4605      	mov	r5, r0
+ 8022a8c:	4630      	mov	r0, r6
+ 8022a8e:	f7ff fa4b 	bl	8021f28 <_malloc_r>
+ 8022a92:	b948      	cbnz	r0, 8022aa8 <__smakebuf_r+0x44>
+ 8022a94:	f9b4 300c 	ldrsh.w	r3, [r4, #12]
+ 8022a98:	059a      	lsls	r2, r3, #22
+ 8022a9a:	d4ef      	bmi.n	8022a7c <__smakebuf_r+0x18>
+ 8022a9c:	f023 0303 	bic.w	r3, r3, #3
+ 8022aa0:	f043 0302 	orr.w	r3, r3, #2
+ 8022aa4:	81a3      	strh	r3, [r4, #12]
+ 8022aa6:	e7e3      	b.n	8022a70 <__smakebuf_r+0xc>
+ 8022aa8:	89a3      	ldrh	r3, [r4, #12]
+ 8022aaa:	6020      	str	r0, [r4, #0]
+ 8022aac:	f043 0380 	orr.w	r3, r3, #128	; 0x80
+ 8022ab0:	81a3      	strh	r3, [r4, #12]
+ 8022ab2:	9b00      	ldr	r3, [sp, #0]
+ 8022ab4:	6163      	str	r3, [r4, #20]
+ 8022ab6:	9b01      	ldr	r3, [sp, #4]
+ 8022ab8:	6120      	str	r0, [r4, #16]
+ 8022aba:	b15b      	cbz	r3, 8022ad4 <__smakebuf_r+0x70>
+ 8022abc:	f9b4 100e 	ldrsh.w	r1, [r4, #14]
+ 8022ac0:	4630      	mov	r0, r6
+ 8022ac2:	f000 f851 	bl	8022b68 <_isatty_r>
+ 8022ac6:	b128      	cbz	r0, 8022ad4 <__smakebuf_r+0x70>
+ 8022ac8:	89a3      	ldrh	r3, [r4, #12]
+ 8022aca:	f023 0303 	bic.w	r3, r3, #3
+ 8022ace:	f043 0301 	orr.w	r3, r3, #1
+ 8022ad2:	81a3      	strh	r3, [r4, #12]
+ 8022ad4:	89a3      	ldrh	r3, [r4, #12]
+ 8022ad6:	431d      	orrs	r5, r3
+ 8022ad8:	81a5      	strh	r5, [r4, #12]
+ 8022ada:	e7cf      	b.n	8022a7c <__smakebuf_r+0x18>
+
+08022adc <_putc_r>:
+ 8022adc:	b570      	push	{r4, r5, r6, lr}
+ 8022ade:	460d      	mov	r5, r1
+ 8022ae0:	4614      	mov	r4, r2
+ 8022ae2:	4606      	mov	r6, r0
+ 8022ae4:	b118      	cbz	r0, 8022aee <_putc_r+0x12>
+ 8022ae6:	6a03      	ldr	r3, [r0, #32]
+ 8022ae8:	b90b      	cbnz	r3, 8022aee <_putc_r+0x12>
+ 8022aea:	f7fe ff17 	bl	802191c <__sinit>
+ 8022aee:	6e63      	ldr	r3, [r4, #100]	; 0x64
+ 8022af0:	07d8      	lsls	r0, r3, #31
+ 8022af2:	d405      	bmi.n	8022b00 <_putc_r+0x24>
+ 8022af4:	89a3      	ldrh	r3, [r4, #12]
+ 8022af6:	0599      	lsls	r1, r3, #22
+ 8022af8:	d402      	bmi.n	8022b00 <_putc_r+0x24>
+ 8022afa:	6da0      	ldr	r0, [r4, #88]	; 0x58
+ 8022afc:	f7ff f971 	bl	8021de2 <__retarget_lock_acquire_recursive>
+ 8022b00:	68a3      	ldr	r3, [r4, #8]
+ 8022b02:	3b01      	subs	r3, #1
+ 8022b04:	2b00      	cmp	r3, #0
+ 8022b06:	60a3      	str	r3, [r4, #8]
+ 8022b08:	da05      	bge.n	8022b16 <_putc_r+0x3a>
+ 8022b0a:	69a2      	ldr	r2, [r4, #24]
+ 8022b0c:	4293      	cmp	r3, r2
+ 8022b0e:	db12      	blt.n	8022b36 <_putc_r+0x5a>
+ 8022b10:	b2eb      	uxtb	r3, r5
+ 8022b12:	2b0a      	cmp	r3, #10
+ 8022b14:	d00f      	beq.n	8022b36 <_putc_r+0x5a>
+ 8022b16:	6823      	ldr	r3, [r4, #0]
+ 8022b18:	1c5a      	adds	r2, r3, #1
+ 8022b1a:	6022      	str	r2, [r4, #0]
+ 8022b1c:	701d      	strb	r5, [r3, #0]
+ 8022b1e:	b2ed      	uxtb	r5, r5
+ 8022b20:	6e63      	ldr	r3, [r4, #100]	; 0x64
+ 8022b22:	07da      	lsls	r2, r3, #31
+ 8022b24:	d405      	bmi.n	8022b32 <_putc_r+0x56>
+ 8022b26:	89a3      	ldrh	r3, [r4, #12]
+ 8022b28:	059b      	lsls	r3, r3, #22
+ 8022b2a:	d402      	bmi.n	8022b32 <_putc_r+0x56>
+ 8022b2c:	6da0      	ldr	r0, [r4, #88]	; 0x58
+ 8022b2e:	f7ff f959 	bl	8021de4 <__retarget_lock_release_recursive>
+ 8022b32:	4628      	mov	r0, r5
+ 8022b34:	bd70      	pop	{r4, r5, r6, pc}
+ 8022b36:	4629      	mov	r1, r5
+ 8022b38:	4622      	mov	r2, r4
+ 8022b3a:	4630      	mov	r0, r6
+ 8022b3c:	f7ff f811 	bl	8021b62 <__swbuf_r>
+ 8022b40:	4605      	mov	r5, r0
+ 8022b42:	e7ed      	b.n	8022b20 <_putc_r+0x44>
+
+08022b44 <_fstat_r>:
+ 8022b44:	b538      	push	{r3, r4, r5, lr}
+ 8022b46:	4d07      	ldr	r5, [pc, #28]	; (8022b64 <_fstat_r+0x20>)
+ 8022b48:	2300      	movs	r3, #0
+ 8022b4a:	4604      	mov	r4, r0
+ 8022b4c:	4608      	mov	r0, r1
+ 8022b4e:	4611      	mov	r1, r2
+ 8022b50:	602b      	str	r3, [r5, #0]
+ 8022b52:	f7df f944 	bl	8001dde <_fstat>
+ 8022b56:	1c43      	adds	r3, r0, #1
+ 8022b58:	d102      	bne.n	8022b60 <_fstat_r+0x1c>
+ 8022b5a:	682b      	ldr	r3, [r5, #0]
+ 8022b5c:	b103      	cbz	r3, 8022b60 <_fstat_r+0x1c>
+ 8022b5e:	6023      	str	r3, [r4, #0]
+ 8022b60:	bd38      	pop	{r3, r4, r5, pc}
+ 8022b62:	bf00      	nop
+ 8022b64:	2401a5e0 	.word	0x2401a5e0
+
+08022b68 <_isatty_r>:
+ 8022b68:	b538      	push	{r3, r4, r5, lr}
+ 8022b6a:	4d06      	ldr	r5, [pc, #24]	; (8022b84 <_isatty_r+0x1c>)
+ 8022b6c:	2300      	movs	r3, #0
+ 8022b6e:	4604      	mov	r4, r0
+ 8022b70:	4608      	mov	r0, r1
+ 8022b72:	602b      	str	r3, [r5, #0]
+ 8022b74:	f7df f943 	bl	8001dfe <_isatty>
+ 8022b78:	1c43      	adds	r3, r0, #1
+ 8022b7a:	d102      	bne.n	8022b82 <_isatty_r+0x1a>
+ 8022b7c:	682b      	ldr	r3, [r5, #0]
+ 8022b7e:	b103      	cbz	r3, 8022b82 <_isatty_r+0x1a>
+ 8022b80:	6023      	str	r3, [r4, #0]
+ 8022b82:	bd38      	pop	{r3, r4, r5, pc}
+ 8022b84:	2401a5e0 	.word	0x2401a5e0
+
+08022b88 <_sbrk_r>:
+ 8022b88:	b538      	push	{r3, r4, r5, lr}
+ 8022b8a:	4d06      	ldr	r5, [pc, #24]	; (8022ba4 <_sbrk_r+0x1c>)
+ 8022b8c:	2300      	movs	r3, #0
+ 8022b8e:	4604      	mov	r4, r0
+ 8022b90:	4608      	mov	r0, r1
+ 8022b92:	602b      	str	r3, [r5, #0]
+ 8022b94:	f7df f94c 	bl	8001e30 <_sbrk>
+ 8022b98:	1c43      	adds	r3, r0, #1
+ 8022b9a:	d102      	bne.n	8022ba2 <_sbrk_r+0x1a>
+ 8022b9c:	682b      	ldr	r3, [r5, #0]
+ 8022b9e:	b103      	cbz	r3, 8022ba2 <_sbrk_r+0x1a>
+ 8022ba0:	6023      	str	r3, [r4, #0]
+ 8022ba2:	bd38      	pop	{r3, r4, r5, pc}
+ 8022ba4:	2401a5e0 	.word	0x2401a5e0
+
+08022ba8 <abort>:
+ 8022ba8:	b508      	push	{r3, lr}
+ 8022baa:	2006      	movs	r0, #6
+ 8022bac:	f000 f85a 	bl	8022c64 <raise>
+ 8022bb0:	2001      	movs	r0, #1
+ 8022bb2:	f7df f8e1 	bl	8001d78 <_exit>
+
+08022bb6 <_realloc_r>:
+ 8022bb6:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
+ 8022bba:	4680      	mov	r8, r0
+ 8022bbc:	4614      	mov	r4, r2
+ 8022bbe:	460e      	mov	r6, r1
+ 8022bc0:	b921      	cbnz	r1, 8022bcc <_realloc_r+0x16>
+ 8022bc2:	e8bd 41f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, lr}
+ 8022bc6:	4611      	mov	r1, r2
+ 8022bc8:	f7ff b9ae 	b.w	8021f28 <_malloc_r>
+ 8022bcc:	b92a      	cbnz	r2, 8022bda <_realloc_r+0x24>
+ 8022bce:	f7ff f937 	bl	8021e40 <_free_r>
+ 8022bd2:	4625      	mov	r5, r4
+ 8022bd4:	4628      	mov	r0, r5
+ 8022bd6:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
+ 8022bda:	f000 f85f 	bl	8022c9c <_malloc_usable_size_r>
+ 8022bde:	4284      	cmp	r4, r0
+ 8022be0:	4607      	mov	r7, r0
+ 8022be2:	d802      	bhi.n	8022bea <_realloc_r+0x34>
+ 8022be4:	ebb4 0f50 	cmp.w	r4, r0, lsr #1
+ 8022be8:	d812      	bhi.n	8022c10 <_realloc_r+0x5a>
+ 8022bea:	4621      	mov	r1, r4
+ 8022bec:	4640      	mov	r0, r8
+ 8022bee:	f7ff f99b 	bl	8021f28 <_malloc_r>
+ 8022bf2:	4605      	mov	r5, r0
+ 8022bf4:	2800      	cmp	r0, #0
+ 8022bf6:	d0ed      	beq.n	8022bd4 <_realloc_r+0x1e>
+ 8022bf8:	42bc      	cmp	r4, r7
+ 8022bfa:	4622      	mov	r2, r4
+ 8022bfc:	4631      	mov	r1, r6
+ 8022bfe:	bf28      	it	cs
+ 8022c00:	463a      	movcs	r2, r7
+ 8022c02:	f7ff f8f0 	bl	8021de6 <memcpy>
+ 8022c06:	4631      	mov	r1, r6
+ 8022c08:	4640      	mov	r0, r8
+ 8022c0a:	f7ff f919 	bl	8021e40 <_free_r>
+ 8022c0e:	e7e1      	b.n	8022bd4 <_realloc_r+0x1e>
+ 8022c10:	4635      	mov	r5, r6
+ 8022c12:	e7df      	b.n	8022bd4 <_realloc_r+0x1e>
+
+08022c14 <_raise_r>:
+ 8022c14:	291f      	cmp	r1, #31
+ 8022c16:	b538      	push	{r3, r4, r5, lr}
+ 8022c18:	4604      	mov	r4, r0
+ 8022c1a:	460d      	mov	r5, r1
+ 8022c1c:	d904      	bls.n	8022c28 <_raise_r+0x14>
+ 8022c1e:	2316      	movs	r3, #22
+ 8022c20:	6003      	str	r3, [r0, #0]
+ 8022c22:	f04f 30ff 	mov.w	r0, #4294967295
+ 8022c26:	bd38      	pop	{r3, r4, r5, pc}
+ 8022c28:	6bc2      	ldr	r2, [r0, #60]	; 0x3c
+ 8022c2a:	b112      	cbz	r2, 8022c32 <_raise_r+0x1e>
+ 8022c2c:	f852 3021 	ldr.w	r3, [r2, r1, lsl #2]
+ 8022c30:	b94b      	cbnz	r3, 8022c46 <_raise_r+0x32>
+ 8022c32:	4620      	mov	r0, r4
+ 8022c34:	f000 f830 	bl	8022c98 <_getpid_r>
+ 8022c38:	462a      	mov	r2, r5
+ 8022c3a:	4601      	mov	r1, r0
+ 8022c3c:	4620      	mov	r0, r4
+ 8022c3e:	e8bd 4038 	ldmia.w	sp!, {r3, r4, r5, lr}
+ 8022c42:	f000 b817 	b.w	8022c74 <_kill_r>
+ 8022c46:	2b01      	cmp	r3, #1
+ 8022c48:	d00a      	beq.n	8022c60 <_raise_r+0x4c>
+ 8022c4a:	1c59      	adds	r1, r3, #1
+ 8022c4c:	d103      	bne.n	8022c56 <_raise_r+0x42>
+ 8022c4e:	2316      	movs	r3, #22
+ 8022c50:	6003      	str	r3, [r0, #0]
+ 8022c52:	2001      	movs	r0, #1
+ 8022c54:	e7e7      	b.n	8022c26 <_raise_r+0x12>
+ 8022c56:	2400      	movs	r4, #0
+ 8022c58:	f842 4025 	str.w	r4, [r2, r5, lsl #2]
+ 8022c5c:	4628      	mov	r0, r5
+ 8022c5e:	4798      	blx	r3
+ 8022c60:	2000      	movs	r0, #0
+ 8022c62:	e7e0      	b.n	8022c26 <_raise_r+0x12>
+
+08022c64 <raise>:
+ 8022c64:	4b02      	ldr	r3, [pc, #8]	; (8022c70 <raise+0xc>)
+ 8022c66:	4601      	mov	r1, r0
+ 8022c68:	6818      	ldr	r0, [r3, #0]
+ 8022c6a:	f7ff bfd3 	b.w	8022c14 <_raise_r>
+ 8022c6e:	bf00      	nop
+ 8022c70:	240000a0 	.word	0x240000a0
+
+08022c74 <_kill_r>:
+ 8022c74:	b538      	push	{r3, r4, r5, lr}
+ 8022c76:	4d07      	ldr	r5, [pc, #28]	; (8022c94 <_kill_r+0x20>)
+ 8022c78:	2300      	movs	r3, #0
+ 8022c7a:	4604      	mov	r4, r0
+ 8022c7c:	4608      	mov	r0, r1
+ 8022c7e:	4611      	mov	r1, r2
+ 8022c80:	602b      	str	r3, [r5, #0]
+ 8022c82:	f7df f867 	bl	8001d54 <_kill>
+ 8022c86:	1c43      	adds	r3, r0, #1
+ 8022c88:	d102      	bne.n	8022c90 <_kill_r+0x1c>
+ 8022c8a:	682b      	ldr	r3, [r5, #0]
+ 8022c8c:	b103      	cbz	r3, 8022c90 <_kill_r+0x1c>
+ 8022c8e:	6023      	str	r3, [r4, #0]
+ 8022c90:	bd38      	pop	{r3, r4, r5, pc}
+ 8022c92:	bf00      	nop
+ 8022c94:	2401a5e0 	.word	0x2401a5e0
+
+08022c98 <_getpid_r>:
+ 8022c98:	f7df b854 	b.w	8001d44 <_getpid>
+
+08022c9c <_malloc_usable_size_r>:
+ 8022c9c:	f851 3c04 	ldr.w	r3, [r1, #-4]
+ 8022ca0:	1f18      	subs	r0, r3, #4
+ 8022ca2:	2b00      	cmp	r3, #0
+ 8022ca4:	bfbc      	itt	lt
+ 8022ca6:	580b      	ldrlt	r3, [r1, r0]
+ 8022ca8:	18c0      	addlt	r0, r0, r3
+ 8022caa:	4770      	bx	lr
+
+08022cac <_init>:
+ 8022cac:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
+ 8022cae:	bf00      	nop
+ 8022cb0:	bcf8      	pop	{r3, r4, r5, r6, r7}
+ 8022cb2:	bc08      	pop	{r3}
+ 8022cb4:	469e      	mov	lr, r3
+ 8022cb6:	4770      	bx	lr
+
+08022cb8 <_fini>:
+ 8022cb8:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
+ 8022cba:	bf00      	nop
+ 8022cbc:	bcf8      	pop	{r3, r4, r5, r6, r7}
+ 8022cbe:	bc08      	pop	{r3}
+ 8022cc0:	469e      	mov	lr, r3
+ 8022cc2:	4770      	bx	lr
diff --git a/Debug/lwip_test.map b/Debug/TBD_TaxiBoard.map
similarity index 70%
rename from Debug/lwip_test.map
rename to Debug/TBD_TaxiBoard.map
index d954933..13637b2 100644
--- a/Debug/lwip_test.map
+++ b/Debug/TBD_TaxiBoard.map
@@ -9,7 +9,7 @@ C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.external
 C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-strtol.o)
                               C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-atoi.o) (_strtol_r)
 C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-strtoul.o)
-                              ./LWFTP/lwftp.o (strtoul)
+                              ./LWFTPC/lwftpc.o (strtoul)
 C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-ctype_.o)
                               ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.o (_ctype_)
 C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-findfp.o)
@@ -21,7 +21,9 @@ C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.external
 C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-putchar.o)
                               ./Middlewares/Third_Party/LwIP/src/core/netif.o (putchar)
 C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-puts.o)
-                              ./LWFTP/lwftp.o (puts)
+                              ./LWFTPC/lwftpc.o (puts)
+C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-snprintf.o)
+                              ./LWFTPC/lwftpc.o (snprintf)
 C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-stdio.o)
                               C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-findfp.o) (__sread)
 C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-wbuf.o)
@@ -35,13 +37,11 @@ C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.external
 C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-memset.o)
                               C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/crt0.o (memset)
 C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-strchr.o)
-                              ./LWFTP/lwftp.o (strchr)
+                              ./LWFTPC/lwftpc.o (strchr)
 C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-strncmp.o)
                               ./Middlewares/Third_Party/LwIP/src/core/def.o (strncmp)
 C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-closer.o)
                               C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-stdio.o) (_close_r)
-C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-reent.o)
-                              ./Core/Src/syscalls.o (errno)
 C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-impure.o)
                               C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-rand.o) (_impure_ptr)
 C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-lseekr.o)
@@ -56,10 +56,12 @@ C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.external
                               C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/crt0.o (__libc_init_array)
 C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-lock.o)
                               C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-findfp.o) (__retarget_lock_init_recursive)
+C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-strcmp.o)
+                              ./LWFTPC/lwftpc.o (strcmp)
 C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-memcpy-stub.o)
-                              ./Core/Src/main.o (memcpy)
+                              ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o (memcpy)
 C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-strlen.o)
-                              ./LWFTP/lwftp.o (strlen)
+                              ./LWFTPC/lwftpc.o (strlen)
 C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-assert.o)
                               C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-rand.o) (__assert_func)
 C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-freer.o)
@@ -70,10 +72,12 @@ C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.external
                               C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-findfp.o) (_malloc_r)
 C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-mlock.o)
                               C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-freer.o) (__malloc_lock)
+C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-nano-svfprintf.o)
+                              C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-snprintf.o) (_svfprintf_r)
 C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-nano-vfprintf.o)
                               C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-printf.o) (_vfprintf_r)
 C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-nano-vfprintf_i.o)
-                              C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-nano-vfprintf.o) (_printf_i)
+                              C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-nano-svfprintf.o) (_printf_i)
 C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-fflush.o)
                               C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-findfp.o) (_fflush_r)
 C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-fprintf.o)
@@ -91,17 +95,23 @@ C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.external
 C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-sbrkr.o)
                               C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-mallocr.o) (_sbrk_r)
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@@ -325,8 +522,16 @@ Discarded input sections
  .text          0x0000000000000000        0x0 ./Core/Src/stm32h7xx_hal_msp.o
  .data          0x0000000000000000        0x0 ./Core/Src/stm32h7xx_hal_msp.o
  .bss           0x0000000000000000        0x0 ./Core/Src/stm32h7xx_hal_msp.o
+ .text.HAL_FDCAN_MspDeInit
+                0x0000000000000000       0xe4 ./Core/Src/stm32h7xx_hal_msp.o
+ .text.HAL_SD_MspDeInit
+                0x0000000000000000       0x54 ./Core/Src/stm32h7xx_hal_msp.o
+ .text.HAL_TIM_Base_MspDeInit
+                0x0000000000000000       0x38 ./Core/Src/stm32h7xx_hal_msp.o
+ .text.HAL_UART_MspDeInit
+                0x0000000000000000       0xa0 ./Core/Src/stm32h7xx_hal_msp.o
  .debug_macro   0x0000000000000000      0xac6 ./Core/Src/stm32h7xx_hal_msp.o
- .debug_macro   0x0000000000000000      0x232 ./Core/Src/stm32h7xx_hal_msp.o
+ .debug_macro   0x0000000000000000      0x24a ./Core/Src/stm32h7xx_hal_msp.o
  .debug_macro   0x0000000000000000       0x2e ./Core/Src/stm32h7xx_hal_msp.o
  .debug_macro   0x0000000000000000       0x3b ./Core/Src/stm32h7xx_hal_msp.o
  .debug_macro   0x0000000000000000       0x22 ./Core/Src/stm32h7xx_hal_msp.o
@@ -374,6 +579,7 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x129 ./Core/Src/stm32h7xx_hal_msp.o
  .debug_macro   0x0000000000000000      0x3f9 ./Core/Src/stm32h7xx_hal_msp.o
  .debug_macro   0x0000000000000000      0x275 ./Core/Src/stm32h7xx_hal_msp.o
+ .debug_macro   0x0000000000000000      0xe42 ./Core/Src/stm32h7xx_hal_msp.o
  .debug_macro   0x0000000000000000      0x3ca ./Core/Src/stm32h7xx_hal_msp.o
  .debug_macro   0x0000000000000000      0x45c ./Core/Src/stm32h7xx_hal_msp.o
  .debug_macro   0x0000000000000000       0x3c ./Core/Src/stm32h7xx_hal_msp.o
@@ -384,7 +590,167 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x1c4 ./Core/Src/stm32h7xx_hal_msp.o
  .debug_macro   0x0000000000000000      0x22a ./Core/Src/stm32h7xx_hal_msp.o
  .debug_macro   0x0000000000000000       0x35 ./Core/Src/stm32h7xx_hal_msp.o
+ .debug_macro   0x0000000000000000      0x830 ./Core/Src/stm32h7xx_hal_msp.o
+ .debug_macro   0x0000000000000000       0x16 ./Core/Src/stm32h7xx_hal_msp.o
+ .debug_macro   0x0000000000000000      0x1ce ./Core/Src/stm32h7xx_hal_msp.o
+ .debug_macro   0x0000000000000000      0xb1d ./Core/Src/stm32h7xx_hal_msp.o
+ .debug_macro   0x0000000000000000      0x29f ./Core/Src/stm32h7xx_hal_msp.o
+ .debug_macro   0x0000000000000000      0x693 ./Core/Src/stm32h7xx_hal_msp.o
+ .debug_macro   0x0000000000000000       0xa6 ./Core/Src/stm32h7xx_hal_msp.o
  .debug_macro   0x0000000000000000      0x5e6 ./Core/Src/stm32h7xx_hal_msp.o
+ .debug_macro   0x0000000000000000       0x58 ./Core/Src/stm32h7xx_hal_msp.o
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+ .group         0x0000000000000000        0xc ./Core/Src/stm32h7xx_hal_timebase_tim.o
+ .text          0x0000000000000000        0x0 ./Core/Src/stm32h7xx_hal_timebase_tim.o
+ .data          0x0000000000000000        0x0 ./Core/Src/stm32h7xx_hal_timebase_tim.o
+ .bss           0x0000000000000000        0x0 ./Core/Src/stm32h7xx_hal_timebase_tim.o
+ .text.HAL_SuspendTick
+                0x0000000000000000       0x24 ./Core/Src/stm32h7xx_hal_timebase_tim.o
+ .text.HAL_ResumeTick
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+ .group         0x0000000000000000        0xc ./Core/Src/stm32h7xx_it.o
+ .group         0x0000000000000000        0xc ./Core/Src/stm32h7xx_it.o
+ .group         0x0000000000000000        0xc ./Core/Src/stm32h7xx_it.o
+ .group         0x0000000000000000        0xc ./Core/Src/stm32h7xx_it.o
+ .group         0x0000000000000000        0xc ./Core/Src/stm32h7xx_it.o
+ .group         0x0000000000000000        0xc ./Core/Src/stm32h7xx_it.o
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  .group         0x0000000000000000        0xc ./Core/Src/stm32h7xx_it.o
  .group         0x0000000000000000        0xc ./Core/Src/stm32h7xx_it.o
  .group         0x0000000000000000        0xc ./Core/Src/stm32h7xx_it.o
@@ -449,7 +815,7 @@ Discarded input sections
  .data          0x0000000000000000        0x0 ./Core/Src/stm32h7xx_it.o
  .bss           0x0000000000000000        0x0 ./Core/Src/stm32h7xx_it.o
  .debug_macro   0x0000000000000000      0xac6 ./Core/Src/stm32h7xx_it.o
- .debug_macro   0x0000000000000000      0x232 ./Core/Src/stm32h7xx_it.o
+ .debug_macro   0x0000000000000000      0x24a ./Core/Src/stm32h7xx_it.o
  .debug_macro   0x0000000000000000       0x2e ./Core/Src/stm32h7xx_it.o
  .debug_macro   0x0000000000000000       0x3b ./Core/Src/stm32h7xx_it.o
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@@ -497,6 +863,7 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x129 ./Core/Src/stm32h7xx_it.o
  .debug_macro   0x0000000000000000      0x3f9 ./Core/Src/stm32h7xx_it.o
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+ .debug_macro   0x0000000000000000      0xe42 ./Core/Src/stm32h7xx_it.o
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  .debug_macro   0x0000000000000000      0x45c ./Core/Src/stm32h7xx_it.o
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@@ -507,7 +874,24 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x1c4 ./Core/Src/stm32h7xx_it.o
  .debug_macro   0x0000000000000000      0x22a ./Core/Src/stm32h7xx_it.o
  .debug_macro   0x0000000000000000       0x35 ./Core/Src/stm32h7xx_it.o
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  .debug_macro   0x0000000000000000      0x5e6 ./Core/Src/stm32h7xx_it.o
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  .group         0x0000000000000000        0xc ./Core/Src/syscalls.o
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@@ -658,7 +1042,7 @@ Discarded input sections
  .debug_macro   0x0000000000000000       0x16 ./Core/Src/syscalls.o
  .debug_macro   0x0000000000000000       0x16 ./Core/Src/syscalls.o
  .debug_macro   0x0000000000000000       0x29 ./Core/Src/syscalls.o
- .debug_macro   0x0000000000000000      0x232 ./Core/Src/syscalls.o
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  .debug_macro   0x0000000000000000       0x2e ./Core/Src/syscalls.o
  .debug_macro   0x0000000000000000       0x3b ./Core/Src/syscalls.o
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@@ -688,6 +1072,7 @@ Discarded input sections
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  .debug_macro   0x0000000000000000      0x3f9 ./Core/Src/syscalls.o
  .debug_macro   0x0000000000000000      0x275 ./Core/Src/syscalls.o
+ .debug_macro   0x0000000000000000      0xe42 ./Core/Src/syscalls.o
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  .debug_macro   0x0000000000000000      0x45c ./Core/Src/syscalls.o
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@@ -698,7 +1083,15 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x1c4 ./Core/Src/syscalls.o
  .debug_macro   0x0000000000000000      0x22a ./Core/Src/syscalls.o
  .debug_macro   0x0000000000000000       0x35 ./Core/Src/syscalls.o
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  .debug_macro   0x0000000000000000      0x5e6 ./Core/Src/syscalls.o
+ .debug_macro   0x0000000000000000       0x58 ./Core/Src/syscalls.o
  .debug_macro   0x0000000000000000       0x1c ./Core/Src/syscalls.o
  .debug_macro   0x0000000000000000       0x10 ./Core/Src/syscalls.o
  .debug_macro   0x0000000000000000       0x16 ./Core/Src/syscalls.o
@@ -717,7 +1110,16 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x11f ./Core/Src/syscalls.o
  .debug_macro   0x0000000000000000       0x82 ./Core/Src/syscalls.o
  .debug_macro   0x0000000000000000       0x66 ./Core/Src/syscalls.o
- .debug_macro   0x0000000000000000      0x756 ./Core/Src/syscalls.o
+ .debug_macro   0x0000000000000000      0x739 ./Core/Src/syscalls.o
+ .group         0x0000000000000000        0xc ./Core/Src/sysmem.o
+ .group         0x0000000000000000        0xc ./Core/Src/sysmem.o
+ .group         0x0000000000000000        0xc ./Core/Src/sysmem.o
+ .group         0x0000000000000000        0xc ./Core/Src/sysmem.o
+ .group         0x0000000000000000        0xc ./Core/Src/sysmem.o
+ .group         0x0000000000000000        0xc ./Core/Src/sysmem.o
+ .group         0x0000000000000000        0xc ./Core/Src/sysmem.o
+ .group         0x0000000000000000        0xc ./Core/Src/sysmem.o
+ .group         0x0000000000000000        0xc ./Core/Src/sysmem.o
  .group         0x0000000000000000        0xc ./Core/Src/sysmem.o
  .group         0x0000000000000000        0xc ./Core/Src/sysmem.o
  .group         0x0000000000000000        0xc ./Core/Src/sysmem.o
@@ -824,7 +1226,7 @@ Discarded input sections
  .data          0x0000000000000000        0x0 ./Core/Src/sysmem.o
  .bss           0x0000000000000000        0x0 ./Core/Src/sysmem.o
  .debug_macro   0x0000000000000000      0xac6 ./Core/Src/sysmem.o
- .debug_macro   0x0000000000000000      0x232 ./Core/Src/sysmem.o
+ .debug_macro   0x0000000000000000      0x24a ./Core/Src/sysmem.o
  .debug_macro   0x0000000000000000       0x2e ./Core/Src/sysmem.o
  .debug_macro   0x0000000000000000       0x3b ./Core/Src/sysmem.o
  .debug_macro   0x0000000000000000       0x22 ./Core/Src/sysmem.o
@@ -872,6 +1274,7 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x129 ./Core/Src/sysmem.o
  .debug_macro   0x0000000000000000      0x3f9 ./Core/Src/sysmem.o
  .debug_macro   0x0000000000000000      0x275 ./Core/Src/sysmem.o
+ .debug_macro   0x0000000000000000      0xe42 ./Core/Src/sysmem.o
  .debug_macro   0x0000000000000000      0x3ca ./Core/Src/sysmem.o
  .debug_macro   0x0000000000000000      0x45c ./Core/Src/sysmem.o
  .debug_macro   0x0000000000000000       0x3c ./Core/Src/sysmem.o
@@ -882,8 +1285,16 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x1c4 ./Core/Src/sysmem.o
  .debug_macro   0x0000000000000000      0x22a ./Core/Src/sysmem.o
  .debug_macro   0x0000000000000000       0x35 ./Core/Src/sysmem.o
+ .debug_macro   0x0000000000000000      0x830 ./Core/Src/sysmem.o
+ .debug_macro   0x0000000000000000       0x16 ./Core/Src/sysmem.o
+ .debug_macro   0x0000000000000000      0x1ce ./Core/Src/sysmem.o
+ .debug_macro   0x0000000000000000      0xb1d ./Core/Src/sysmem.o
+ .debug_macro   0x0000000000000000      0x29f ./Core/Src/sysmem.o
+ .debug_macro   0x0000000000000000      0x693 ./Core/Src/sysmem.o
+ .debug_macro   0x0000000000000000       0xa6 ./Core/Src/sysmem.o
  .debug_macro   0x0000000000000000      0x5e6 ./Core/Src/sysmem.o
- .debug_macro   0x0000000000000000       0xd0 ./Core/Src/sysmem.o
+ .debug_macro   0x0000000000000000       0x58 ./Core/Src/sysmem.o
+ .debug_macro   0x0000000000000000       0xe8 ./Core/Src/sysmem.o
  .debug_macro   0x0000000000000000       0x16 ./Core/Src/sysmem.o
  .debug_macro   0x0000000000000000       0x10 ./Core/Src/sysmem.o
  .debug_macro   0x0000000000000000       0x16 ./Core/Src/sysmem.o
@@ -923,7 +1334,7 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x11f ./Core/Src/sysmem.o
  .debug_macro   0x0000000000000000       0x82 ./Core/Src/sysmem.o
  .debug_macro   0x0000000000000000       0x66 ./Core/Src/sysmem.o
- .debug_macro   0x0000000000000000      0x756 ./Core/Src/sysmem.o
+ .debug_macro   0x0000000000000000      0x739 ./Core/Src/sysmem.o
  .debug_macro   0x0000000000000000      0x31a ./Core/Src/sysmem.o
  .group         0x0000000000000000        0xc ./Core/Src/system_stm32h7xx.o
  .group         0x0000000000000000        0xc ./Core/Src/system_stm32h7xx.o
@@ -985,6 +1396,14 @@ Discarded input sections
  .group         0x0000000000000000        0xc ./Core/Src/system_stm32h7xx.o
  .group         0x0000000000000000        0xc ./Core/Src/system_stm32h7xx.o
  .group         0x0000000000000000        0xc ./Core/Src/system_stm32h7xx.o
+ .group         0x0000000000000000        0xc ./Core/Src/system_stm32h7xx.o
+ .group         0x0000000000000000        0xc ./Core/Src/system_stm32h7xx.o
+ .group         0x0000000000000000        0xc ./Core/Src/system_stm32h7xx.o
+ .group         0x0000000000000000        0xc ./Core/Src/system_stm32h7xx.o
+ .group         0x0000000000000000        0xc ./Core/Src/system_stm32h7xx.o
+ .group         0x0000000000000000        0xc ./Core/Src/system_stm32h7xx.o
+ .group         0x0000000000000000        0xc ./Core/Src/system_stm32h7xx.o
+ .group         0x0000000000000000        0xc ./Core/Src/system_stm32h7xx.o
  .text          0x0000000000000000        0x0 ./Core/Src/system_stm32h7xx.o
  .data          0x0000000000000000        0x0 ./Core/Src/system_stm32h7xx.o
  .bss           0x0000000000000000        0x0 ./Core/Src/system_stm32h7xx.o
@@ -1007,7 +1426,7 @@ Discarded input sections
  .debug_macro   0x0000000000000000       0x27 ./Core/Src/system_stm32h7xx.o
  .debug_macro   0x0000000000000000    0x211d1 ./Core/Src/system_stm32h7xx.o
  .debug_macro   0x0000000000000000       0x6d ./Core/Src/system_stm32h7xx.o
- .debug_macro   0x0000000000000000      0x232 ./Core/Src/system_stm32h7xx.o
+ .debug_macro   0x0000000000000000      0x24a ./Core/Src/system_stm32h7xx.o
  .debug_macro   0x0000000000000000     0x3d48 ./Core/Src/system_stm32h7xx.o
  .debug_macro   0x0000000000000000      0x174 ./Core/Src/system_stm32h7xx.o
  .debug_macro   0x0000000000000000       0x61 ./Core/Src/system_stm32h7xx.o
@@ -1039,6 +1458,7 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x129 ./Core/Src/system_stm32h7xx.o
  .debug_macro   0x0000000000000000      0x3f9 ./Core/Src/system_stm32h7xx.o
  .debug_macro   0x0000000000000000      0x275 ./Core/Src/system_stm32h7xx.o
+ .debug_macro   0x0000000000000000      0xe42 ./Core/Src/system_stm32h7xx.o
  .debug_macro   0x0000000000000000      0x3ca ./Core/Src/system_stm32h7xx.o
  .debug_macro   0x0000000000000000      0x45c ./Core/Src/system_stm32h7xx.o
  .debug_macro   0x0000000000000000       0x3c ./Core/Src/system_stm32h7xx.o
@@ -1049,6 +1469,13 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x1c4 ./Core/Src/system_stm32h7xx.o
  .debug_macro   0x0000000000000000      0x22a ./Core/Src/system_stm32h7xx.o
  .debug_macro   0x0000000000000000       0x35 ./Core/Src/system_stm32h7xx.o
+ .debug_macro   0x0000000000000000      0x830 ./Core/Src/system_stm32h7xx.o
+ .debug_macro   0x0000000000000000       0x16 ./Core/Src/system_stm32h7xx.o
+ .debug_macro   0x0000000000000000      0x1ce ./Core/Src/system_stm32h7xx.o
+ .debug_macro   0x0000000000000000      0xb1d ./Core/Src/system_stm32h7xx.o
+ .debug_macro   0x0000000000000000      0x29f ./Core/Src/system_stm32h7xx.o
+ .debug_macro   0x0000000000000000      0x693 ./Core/Src/system_stm32h7xx.o
+ .debug_macro   0x0000000000000000       0xa6 ./Core/Src/system_stm32h7xx.o
  .debug_macro   0x0000000000000000      0x5e6 ./Core/Src/system_stm32h7xx.o
  .text          0x0000000000000000       0x14 ./Core/Startup/startup_stm32h723vghx.o
  .data          0x0000000000000000        0x0 ./Core/Startup/startup_stm32h723vghx.o
@@ -1153,6 +1580,14 @@ Discarded input sections
  .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.o
  .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.o
  .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.o
  .text          0x0000000000000000        0x0 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.o
  .data          0x0000000000000000        0x0 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.o
  .bss           0x0000000000000000        0x0 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.o
@@ -1162,14 +1597,14 @@ Discarded input sections
                 0x0000000000000000        0xe ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.o
  .text.HAL_MspDeInit
                 0x0000000000000000        0xe ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.o
+ .text.HAL_InitTick
+                0x0000000000000000       0x6c ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.o
  .text.HAL_GetTickPrio
                 0x0000000000000000       0x18 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.o
  .text.HAL_SetTickFreq
                 0x0000000000000000       0x50 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.o
  .text.HAL_GetTickFreq
                 0x0000000000000000       0x18 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.o
- .text.HAL_Delay
-                0x0000000000000000       0x48 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.o
  .text.HAL_SuspendTick
                 0x0000000000000000       0x20 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.o
  .text.HAL_ResumeTick
@@ -1255,7 +1690,7 @@ Discarded input sections
  .text.HAL_EXTI_D3_EventInputConfig
                 0x0000000000000000       0xd0 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.o
  .debug_macro   0x0000000000000000      0xac6 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.o
- .debug_macro   0x0000000000000000      0x232 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.o
+ .debug_macro   0x0000000000000000      0x24a ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.o
  .debug_macro   0x0000000000000000       0x2e ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.o
  .debug_macro   0x0000000000000000       0x3b ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.o
  .debug_macro   0x0000000000000000       0x22 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.o
@@ -1303,6 +1738,7 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x129 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.o
  .debug_macro   0x0000000000000000      0x3f9 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.o
  .debug_macro   0x0000000000000000      0x275 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.o
+ .debug_macro   0x0000000000000000      0xe42 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.o
  .debug_macro   0x0000000000000000      0x3ca ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.o
  .debug_macro   0x0000000000000000      0x45c ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.o
  .debug_macro   0x0000000000000000       0x3c ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.o
@@ -1313,6 +1749,13 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x1c4 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.o
  .debug_macro   0x0000000000000000      0x22a ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.o
  .debug_macro   0x0000000000000000       0x35 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.o
+ .debug_macro   0x0000000000000000      0x830 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.o
+ .debug_macro   0x0000000000000000       0x16 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.o
+ .debug_macro   0x0000000000000000      0x1ce ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.o
+ .debug_macro   0x0000000000000000      0xb1d ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.o
+ .debug_macro   0x0000000000000000      0x29f ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.o
+ .debug_macro   0x0000000000000000      0x693 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.o
+ .debug_macro   0x0000000000000000       0xa6 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.o
  .debug_macro   0x0000000000000000      0x5e6 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.o
  .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.o
  .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.o
@@ -1374,6 +1817,14 @@ Discarded input sections
  .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.o
  .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.o
  .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.o
  .text          0x0000000000000000        0x0 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.o
  .data          0x0000000000000000        0x0 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.o
  .bss           0x0000000000000000        0x0 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.o
@@ -1393,10 +1844,14 @@ Discarded input sections
                 0x0000000000000000       0x6e ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.o
  .text.__NVIC_SystemReset
                 0x0000000000000000       0x2c ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.o
+ .text.SysTick_Config
+                0x0000000000000000       0x44 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.o
  .text.HAL_NVIC_DisableIRQ
                 0x0000000000000000       0x1c ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.o
  .text.HAL_NVIC_SystemReset
                 0x0000000000000000        0x8 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.o
+ .text.HAL_SYSTICK_Config
+                0x0000000000000000       0x18 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.o
  .text.HAL_NVIC_GetPriorityGrouping
                 0x0000000000000000        0xe ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.o
  .text.HAL_NVIC_GetPriority
@@ -1418,7 +1873,7 @@ Discarded input sections
  .text.HAL_GetCurrentCPUID
                 0x0000000000000000       0x10 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.o
  .debug_macro   0x0000000000000000      0xac6 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.o
- .debug_macro   0x0000000000000000      0x232 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.o
+ .debug_macro   0x0000000000000000      0x24a ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.o
  .debug_macro   0x0000000000000000       0x2e ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.o
  .debug_macro   0x0000000000000000       0x3b ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.o
  .debug_macro   0x0000000000000000       0x22 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.o
@@ -1466,6 +1921,7 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x129 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.o
  .debug_macro   0x0000000000000000      0x3f9 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.o
  .debug_macro   0x0000000000000000      0x275 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.o
+ .debug_macro   0x0000000000000000      0xe42 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.o
  .debug_macro   0x0000000000000000      0x3ca ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.o
  .debug_macro   0x0000000000000000      0x45c ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.o
  .debug_macro   0x0000000000000000       0x3c ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.o
@@ -1476,6 +1932,13 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x1c4 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.o
  .debug_macro   0x0000000000000000      0x22a ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.o
  .debug_macro   0x0000000000000000       0x35 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.o
+ .debug_macro   0x0000000000000000      0x830 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.o
+ .debug_macro   0x0000000000000000       0x16 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.o
+ .debug_macro   0x0000000000000000      0x1ce ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.o
+ .debug_macro   0x0000000000000000      0xb1d ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.o
+ .debug_macro   0x0000000000000000      0x29f ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.o
+ .debug_macro   0x0000000000000000      0x693 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.o
+ .debug_macro   0x0000000000000000       0xa6 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.o
  .debug_macro   0x0000000000000000      0x5e6 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.o
  .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.o
  .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.o
@@ -1537,11 +2000,17 @@ Discarded input sections
  .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.o
  .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.o
  .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.o
  .text          0x0000000000000000        0x0 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.o
  .data          0x0000000000000000        0x0 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.o
  .bss           0x0000000000000000        0x0 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.o
- .text.HAL_DMA_Init
-                0x0000000000000000      0x6b0 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.o
  .text.HAL_DMA_DeInit
                 0x0000000000000000      0x36c ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.o
  .text.HAL_DMA_Start
@@ -1554,8 +2023,6 @@ Discarded input sections
                 0x0000000000000000      0x48c ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.o
  .text.HAL_DMA_PollForTransfer
                 0x0000000000000000      0x754 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.o
- .text.HAL_DMA_IRQHandler
-                0x0000000000000000      0xe54 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.o
  .text.HAL_DMA_RegisterCallback
                 0x0000000000000000       0xb4 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.o
  .text.HAL_DMA_UnRegisterCallback
@@ -1566,25 +2033,8 @@ Discarded input sections
                 0x0000000000000000       0x18 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.o
  .text.DMA_SetConfig
                 0x0000000000000000      0x358 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.o
- .text.DMA_CalcBaseAndBitshift
-                0x0000000000000000      0x164 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.o
- .text.DMA_CheckFifoParam
-                0x0000000000000000       0xf8 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.o
- .text.DMA_CalcDMAMUXChannelBaseAndMask
-                0x0000000000000000      0x134 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.o
- .text.DMA_CalcDMAMUXRequestGenBaseAndMask
-                0x0000000000000000       0xe8 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.o
- .rodata.flagBitshiftOffset.0
-                0x0000000000000000        0x8 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.o
- .debug_info    0x0000000000000000      0xb67 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.o
- .debug_abbrev  0x0000000000000000      0x248 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.o
- .debug_aranges
-                0x0000000000000000       0xa0 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.o
- .debug_rnglists
-                0x0000000000000000       0x82 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.o
- .debug_macro   0x0000000000000000      0x2e8 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.o
  .debug_macro   0x0000000000000000      0xac6 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.o
- .debug_macro   0x0000000000000000      0x232 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.o
+ .debug_macro   0x0000000000000000      0x24a ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.o
  .debug_macro   0x0000000000000000       0x2e ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.o
  .debug_macro   0x0000000000000000       0x3b ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.o
  .debug_macro   0x0000000000000000       0x22 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.o
@@ -1632,6 +2082,7 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x129 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.o
  .debug_macro   0x0000000000000000      0x3f9 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.o
  .debug_macro   0x0000000000000000      0x275 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.o
+ .debug_macro   0x0000000000000000      0xe42 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.o
  .debug_macro   0x0000000000000000      0x3ca ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.o
  .debug_macro   0x0000000000000000      0x45c ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.o
  .debug_macro   0x0000000000000000       0x3c ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.o
@@ -1642,13 +2093,22 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x1c4 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.o
  .debug_macro   0x0000000000000000      0x22a ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.o
  .debug_macro   0x0000000000000000       0x35 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.o
+ .debug_macro   0x0000000000000000      0x830 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.o
+ .debug_macro   0x0000000000000000       0x16 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.o
+ .debug_macro   0x0000000000000000      0x1ce ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.o
+ .debug_macro   0x0000000000000000      0xb1d ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.o
+ .debug_macro   0x0000000000000000      0x29f ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.o
+ .debug_macro   0x0000000000000000      0x693 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.o
+ .debug_macro   0x0000000000000000       0xa6 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.o
  .debug_macro   0x0000000000000000      0x5e6 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.o
- .debug_line    0x0000000000000000     0x27b0 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.o
- .debug_str     0x0000000000000000   0x139794 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.o
- .comment       0x0000000000000000       0x44 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.o
- .debug_frame   0x0000000000000000      0x2b4 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.o
- .ARM.attributes
-                0x0000000000000000       0x32 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.o
  .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.o
  .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.o
  .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.o
@@ -1736,9 +2196,9 @@ Discarded input sections
                 0x0000000000000000       0x60 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.o
  .debug_rnglists
                 0x0000000000000000       0x4a ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.o
- .debug_macro   0x0000000000000000      0x294 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.o
+ .debug_macro   0x0000000000000000      0x2f3 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.o
  .debug_macro   0x0000000000000000      0xac6 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.o
- .debug_macro   0x0000000000000000      0x232 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.o
+ .debug_macro   0x0000000000000000      0x24a ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.o
  .debug_macro   0x0000000000000000       0x2e ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.o
  .debug_macro   0x0000000000000000       0x3b ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.o
  .debug_macro   0x0000000000000000       0x22 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.o
@@ -1786,6 +2246,7 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x129 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.o
  .debug_macro   0x0000000000000000      0x3f9 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.o
  .debug_macro   0x0000000000000000      0x275 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.o
+ .debug_macro   0x0000000000000000      0xe42 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.o
  .debug_macro   0x0000000000000000      0x3ca ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.o
  .debug_macro   0x0000000000000000      0x45c ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.o
  .debug_macro   0x0000000000000000       0x3c ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.o
@@ -1796,9 +2257,16 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x1c4 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.o
  .debug_macro   0x0000000000000000      0x22a ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.o
  .debug_macro   0x0000000000000000       0x35 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.o
+ .debug_macro   0x0000000000000000      0x830 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.o
+ .debug_macro   0x0000000000000000       0x16 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.o
+ .debug_macro   0x0000000000000000      0x1ce ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.o
+ .debug_macro   0x0000000000000000      0xb1d ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.o
+ .debug_macro   0x0000000000000000      0x29f ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.o
+ .debug_macro   0x0000000000000000      0x693 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.o
+ .debug_macro   0x0000000000000000       0xa6 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.o
  .debug_macro   0x0000000000000000      0x5e6 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.o
- .debug_line    0x0000000000000000     0x11f6 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.o
- .debug_str     0x0000000000000000   0x139138 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.o
+ .debug_line    0x0000000000000000     0x12d7 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.o
+ .debug_str     0x0000000000000000   0x1577c9 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.o
  .comment       0x0000000000000000       0x44 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.o
  .debug_frame   0x0000000000000000      0x174 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.o
  .ARM.attributes
@@ -1863,6 +2331,14 @@ Discarded input sections
  .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o
  .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o
  .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o
  .text          0x0000000000000000        0x0 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o
  .data          0x0000000000000000        0x0 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o
  .bss           0x0000000000000000        0x0 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o
@@ -1872,12 +2348,12 @@ Discarded input sections
                 0x0000000000000000       0x14 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o
  .text.HAL_ETH_MspDeInit
                 0x0000000000000000       0x14 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o
- .text.HAL_ETH_Start_IT
-                0x0000000000000000      0x118 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o
- .text.HAL_ETH_Stop_IT
-                0x0000000000000000       0xf0 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o
- .text.HAL_ETH_Transmit_IT
-                0x0000000000000000       0xa2 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o
+ .text.HAL_ETH_Start
+                0x0000000000000000       0xc4 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o
+ .text.HAL_ETH_Stop
+                0x0000000000000000       0xa0 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o
+ .text.HAL_ETH_Transmit
+                0x0000000000000000      0x12e ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o
  .text.HAL_ETH_RegisterRxAllocateCallback
                 0x0000000000000000       0x2a ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o
  .text.HAL_ETH_UnRegisterRxAllocateCallback
@@ -1898,8 +2374,12 @@ Discarded input sections
                 0x0000000000000000       0x24 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o
  .text.HAL_ETH_TxFreeCallback
                 0x0000000000000000       0x14 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o
- .text.HAL_ETH_ReleaseTxPacket
-                0x0000000000000000       0xb6 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o
+ .text.HAL_ETH_TxCpltCallback
+                0x0000000000000000       0x14 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o
+ .text.HAL_ETH_RxCpltCallback
+                0x0000000000000000       0x14 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o
+ .text.HAL_ETH_ErrorCallback
+                0x0000000000000000       0x14 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o
  .text.HAL_ETH_GetDMAConfig
                 0x0000000000000000      0x138 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o
  .text.HAL_ETH_SetDMAConfig
@@ -1924,14 +2404,12 @@ Discarded input sections
                 0x0000000000000000       0x1a ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o
  .text.HAL_ETH_GetError
                 0x0000000000000000       0x1a ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o
- .text.HAL_ETH_GetDMAError
-                0x0000000000000000       0x1a ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o
  .text.HAL_ETH_GetMACError
                 0x0000000000000000       0x1a ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o
  .text.HAL_ETH_GetMACWakeUpSource
                 0x0000000000000000       0x1a ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o
  .debug_macro   0x0000000000000000      0xac6 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o
- .debug_macro   0x0000000000000000      0x232 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o
+ .debug_macro   0x0000000000000000      0x24a ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o
  .debug_macro   0x0000000000000000       0x2e ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o
  .debug_macro   0x0000000000000000       0x3b ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o
  .debug_macro   0x0000000000000000       0x22 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o
@@ -1979,6 +2457,7 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x129 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o
  .debug_macro   0x0000000000000000      0x3f9 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o
  .debug_macro   0x0000000000000000      0x275 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o
+ .debug_macro   0x0000000000000000      0xe42 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o
  .debug_macro   0x0000000000000000      0x3ca ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o
  .debug_macro   0x0000000000000000      0x45c ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o
  .debug_macro   0x0000000000000000       0x3c ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o
@@ -1989,6 +2468,13 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x1c4 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o
  .debug_macro   0x0000000000000000      0x22a ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o
  .debug_macro   0x0000000000000000       0x35 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o
+ .debug_macro   0x0000000000000000      0x830 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o
+ .debug_macro   0x0000000000000000       0x16 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o
+ .debug_macro   0x0000000000000000      0x1ce ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o
+ .debug_macro   0x0000000000000000      0xb1d ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o
+ .debug_macro   0x0000000000000000      0x29f ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o
+ .debug_macro   0x0000000000000000      0x693 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o
+ .debug_macro   0x0000000000000000       0xa6 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o
  .debug_macro   0x0000000000000000      0x5e6 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o
  .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.o
  .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.o
@@ -2050,6 +2536,14 @@ Discarded input sections
  .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.o
  .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.o
  .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.o
  .text          0x0000000000000000        0x0 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.o
  .data          0x0000000000000000        0x0 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.o
  .bss           0x0000000000000000        0x0 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.o
@@ -2099,9 +2593,9 @@ Discarded input sections
                 0x0000000000000000       0xb8 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.o
  .debug_rnglists
                 0x0000000000000000       0x8b ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.o
- .debug_macro   0x0000000000000000      0x2ac ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.o
+ .debug_macro   0x0000000000000000      0x30b ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.o
  .debug_macro   0x0000000000000000      0xac6 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.o
- .debug_macro   0x0000000000000000      0x232 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.o
+ .debug_macro   0x0000000000000000      0x24a ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.o
  .debug_macro   0x0000000000000000       0x2e ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.o
  .debug_macro   0x0000000000000000       0x3b ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.o
  .debug_macro   0x0000000000000000       0x22 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.o
@@ -2149,6 +2643,7 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x129 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.o
  .debug_macro   0x0000000000000000      0x3f9 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.o
  .debug_macro   0x0000000000000000      0x275 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.o
+ .debug_macro   0x0000000000000000      0xe42 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.o
  .debug_macro   0x0000000000000000      0x3ca ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.o
  .debug_macro   0x0000000000000000      0x45c ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.o
  .debug_macro   0x0000000000000000       0x3c ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.o
@@ -2159,9 +2654,16 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x1c4 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.o
  .debug_macro   0x0000000000000000      0x22a ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.o
  .debug_macro   0x0000000000000000       0x35 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.o
+ .debug_macro   0x0000000000000000      0x830 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.o
+ .debug_macro   0x0000000000000000       0x16 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.o
+ .debug_macro   0x0000000000000000      0x1ce ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.o
+ .debug_macro   0x0000000000000000      0xb1d ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.o
+ .debug_macro   0x0000000000000000      0x29f ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.o
+ .debug_macro   0x0000000000000000      0x693 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.o
+ .debug_macro   0x0000000000000000       0xa6 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.o
  .debug_macro   0x0000000000000000      0x5e6 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.o
- .debug_line    0x0000000000000000      0xcbb ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.o
- .debug_str     0x0000000000000000   0x139bf5 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.o
+ .debug_line    0x0000000000000000      0xd9c ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.o
+ .debug_str     0x0000000000000000   0x158286 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.o
  .comment       0x0000000000000000       0x44 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.o
  .debug_frame   0x0000000000000000      0x330 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.o
  .ARM.attributes
@@ -2226,6 +2728,14 @@ Discarded input sections
  .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.o
  .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.o
  .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.o
  .text          0x0000000000000000        0x0 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.o
  .data          0x0000000000000000        0x0 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.o
  .bss           0x0000000000000000        0x0 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.o
@@ -2253,9 +2763,9 @@ Discarded input sections
                 0x0000000000000000       0x60 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.o
  .debug_rnglists
                 0x0000000000000000       0x46 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.o
- .debug_macro   0x0000000000000000      0x2a2 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.o
+ .debug_macro   0x0000000000000000      0x301 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.o
  .debug_macro   0x0000000000000000      0xac6 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.o
- .debug_macro   0x0000000000000000      0x232 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.o
+ .debug_macro   0x0000000000000000      0x24a ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.o
  .debug_macro   0x0000000000000000       0x2e ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.o
  .debug_macro   0x0000000000000000       0x3b ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.o
  .debug_macro   0x0000000000000000       0x22 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.o
@@ -2303,6 +2813,7 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x129 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.o
  .debug_macro   0x0000000000000000      0x3f9 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.o
  .debug_macro   0x0000000000000000      0x275 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.o
+ .debug_macro   0x0000000000000000      0xe42 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.o
  .debug_macro   0x0000000000000000      0x3ca ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.o
  .debug_macro   0x0000000000000000      0x45c ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.o
  .debug_macro   0x0000000000000000       0x3c ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.o
@@ -2313,13 +2824,329 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x1c4 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.o
  .debug_macro   0x0000000000000000      0x22a ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.o
  .debug_macro   0x0000000000000000       0x35 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.o
+ .debug_macro   0x0000000000000000      0x830 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.o
+ .debug_macro   0x0000000000000000       0x16 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.o
+ .debug_macro   0x0000000000000000      0x1ce ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.o
+ .debug_macro   0x0000000000000000      0xb1d ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.o
+ .debug_macro   0x0000000000000000      0x29f ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.o
+ .debug_macro   0x0000000000000000      0x693 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.o
+ .debug_macro   0x0000000000000000       0xa6 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.o
  .debug_macro   0x0000000000000000      0x5e6 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.o
- .debug_line    0x0000000000000000      0xd37 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.o
- .debug_str     0x0000000000000000   0x138e8e ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.o
+ .debug_line    0x0000000000000000      0xe18 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.o
+ .debug_str     0x0000000000000000   0x15751f ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.o
  .comment       0x0000000000000000       0x44 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.o
  .debug_frame   0x0000000000000000      0x174 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.o
  .ARM.attributes
                 0x0000000000000000       0x32 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+ .text          0x0000000000000000        0x0 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+ .data          0x0000000000000000        0x0 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+ .bss           0x0000000000000000        0x0 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+ .rodata.DLCtoBytes
+                0x0000000000000000       0x10 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+ .text.HAL_FDCAN_DeInit
+                0x0000000000000000       0x48 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+ .text.HAL_FDCAN_MspInit
+                0x0000000000000000       0x14 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+ .text.HAL_FDCAN_MspDeInit
+                0x0000000000000000       0x14 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+ .text.HAL_FDCAN_EnterPowerDownMode
+                0x0000000000000000       0x62 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+ .text.HAL_FDCAN_ExitPowerDownMode
+                0x0000000000000000       0x72 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+ .text.HAL_FDCAN_ConfigClockCalibration
+                0x0000000000000000       0xcc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+ .text.HAL_FDCAN_GetClockCalibrationState
+                0x0000000000000000       0x20 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+ .text.HAL_FDCAN_ResetClockCalibrationState
+                0x0000000000000000       0x68 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+ .text.HAL_FDCAN_GetClockCalibrationCounter
+                0x0000000000000000       0x44 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+ .text.HAL_FDCAN_ConfigFilter
+                0x0000000000000000       0xec ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+ .text.HAL_FDCAN_ConfigGlobalFilter
+                0x0000000000000000       0x5a ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+ .text.HAL_FDCAN_ConfigExtendedIdMask
+                0x0000000000000000       0x42 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+ .text.HAL_FDCAN_ConfigRxFifoOverwrite
+                0x0000000000000000       0x72 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+ .text.HAL_FDCAN_ConfigFifoWatermark
+                0x0000000000000000       0x98 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+ .text.HAL_FDCAN_ConfigRamWatchdog
+                0x0000000000000000       0x4c ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+ .text.HAL_FDCAN_ConfigTimestampCounter
+                0x0000000000000000       0x4c ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+ .text.HAL_FDCAN_EnableTimestampCounter
+                0x0000000000000000       0x4c ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+ .text.HAL_FDCAN_DisableTimestampCounter
+                0x0000000000000000       0x46 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+ .text.HAL_FDCAN_GetTimestampCounter
+                0x0000000000000000       0x1c ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+ .text.HAL_FDCAN_ResetTimestampCounter
+                0x0000000000000000       0x40 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+ .text.HAL_FDCAN_ConfigTimeoutCounter
+                0x0000000000000000       0x56 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+ .text.HAL_FDCAN_EnableTimeoutCounter
+                0x0000000000000000       0x46 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+ .text.HAL_FDCAN_DisableTimeoutCounter
+                0x0000000000000000       0x46 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+ .text.HAL_FDCAN_GetTimeoutCounter
+                0x0000000000000000       0x1c ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+ .text.HAL_FDCAN_ResetTimeoutCounter
+                0x0000000000000000       0x40 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+ .text.HAL_FDCAN_ConfigTxDelayCompensation
+                0x0000000000000000       0x48 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+ .text.HAL_FDCAN_EnableTxDelayCompensation
+                0x0000000000000000       0x46 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+ .text.HAL_FDCAN_DisableTxDelayCompensation
+                0x0000000000000000       0x46 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+ .text.HAL_FDCAN_EnableISOMode
+                0x0000000000000000       0x46 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+ .text.HAL_FDCAN_DisableISOMode
+                0x0000000000000000       0x46 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+ .text.HAL_FDCAN_EnableEdgeFiltering
+                0x0000000000000000       0x46 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+ .text.HAL_FDCAN_DisableEdgeFiltering
+                0x0000000000000000       0x46 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+ .text.HAL_FDCAN_Start
+                0x0000000000000000       0x56 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+ .text.HAL_FDCAN_Stop
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+ .text.HAL_FDCAN_AddMessageToTxFifoQ
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+ .text.HAL_FDCAN_GetProtocolStatus
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+ .text.HAL_FDCAN_GetErrorCounters
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+ .text.HAL_FDCAN_GetTxFifoFreeLevel
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+ .text.HAL_FDCAN_TT_ConfigReferenceMessage
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+ .text.HAL_FDCAN_TT_ConfigStopWatch
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+ .text.HAL_FDCAN_TT_ConfigRegisterTimeMark
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+ .text.HAL_FDCAN_TT_SetEndOfGap
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+ .text.HAL_FDCAN_TT_EnableExternalSynchronization
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+ .text.HAL_FDCAN_TT_DisableExternalSynchronization
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+ .text.HAL_FDCAN_TT_GetOperationStatus
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+ .text.HAL_FDCAN_TT_ConfigInterruptLines
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+ .text.HAL_FDCAN_TT_ActivateNotification
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+ .text.HAL_FDCAN_TT_DeactivateNotification
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+ .text.HAL_FDCAN_GetState
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+ .text.HAL_FDCAN_GetError
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+ .text.FDCAN_CopyMessageToRAM
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+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.o
  .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.o
  .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.o
  .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.o
@@ -2418,9 +3245,9 @@ Discarded input sections
                 0x0000000000000000       0x88 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.o
  .debug_rnglists
                 0x0000000000000000       0x66 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.o
- .debug_macro   0x0000000000000000      0x29a ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.o
+ .debug_macro   0x0000000000000000      0x2f9 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.o
  .debug_macro   0x0000000000000000      0xac6 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.o
- .debug_macro   0x0000000000000000      0x232 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.o
+ .debug_macro   0x0000000000000000      0x24a ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.o
  .debug_macro   0x0000000000000000       0x2e ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.o
  .debug_macro   0x0000000000000000       0x3b ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.o
  .debug_macro   0x0000000000000000       0x22 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.o
@@ -2468,6 +3295,7 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x129 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.o
  .debug_macro   0x0000000000000000      0x3f9 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.o
  .debug_macro   0x0000000000000000      0x275 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.o
+ .debug_macro   0x0000000000000000      0xe42 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.o
  .debug_macro   0x0000000000000000      0x3ca ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.o
  .debug_macro   0x0000000000000000      0x45c ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.o
  .debug_macro   0x0000000000000000       0x3c ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.o
@@ -2478,9 +3306,16 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x1c4 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.o
  .debug_macro   0x0000000000000000      0x22a ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.o
  .debug_macro   0x0000000000000000       0x35 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.o
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  .debug_macro   0x0000000000000000      0x5e6 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.o
- .debug_line    0x0000000000000000      0xced ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.o
- .debug_str     0x0000000000000000   0x138fdb ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.o
+ .debug_line    0x0000000000000000      0xdce ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.o
+ .debug_str     0x0000000000000000   0x15766c ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.o
  .comment       0x0000000000000000       0x44 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.o
  .debug_frame   0x0000000000000000      0x1fc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.o
  .ARM.attributes
@@ -2545,6 +3380,14 @@ Discarded input sections
  .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.o
  .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.o
  .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.o
  .text          0x0000000000000000        0x0 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.o
  .data          0x0000000000000000        0x0 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.o
  .bss           0x0000000000000000        0x0 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.o
@@ -2614,9 +3457,9 @@ Discarded input sections
                 0x0000000000000000      0x108 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.o
  .debug_rnglists
                 0x0000000000000000       0xc7 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.o
- .debug_macro   0x0000000000000000      0x29a ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.o
+ .debug_macro   0x0000000000000000      0x2f9 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.o
  .debug_macro   0x0000000000000000      0xac6 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.o
- .debug_macro   0x0000000000000000      0x232 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.o
+ .debug_macro   0x0000000000000000      0x24a ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.o
  .debug_macro   0x0000000000000000       0x2e ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.o
  .debug_macro   0x0000000000000000       0x3b ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.o
  .debug_macro   0x0000000000000000       0x22 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.o
@@ -2664,6 +3507,7 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x129 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.o
  .debug_macro   0x0000000000000000      0x3f9 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.o
  .debug_macro   0x0000000000000000      0x275 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.o
+ .debug_macro   0x0000000000000000      0xe42 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.o
  .debug_macro   0x0000000000000000      0x3ca ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.o
  .debug_macro   0x0000000000000000      0x45c ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.o
  .debug_macro   0x0000000000000000       0x3c ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.o
@@ -2674,9 +3518,16 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x1c4 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.o
  .debug_macro   0x0000000000000000      0x22a ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.o
  .debug_macro   0x0000000000000000       0x35 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.o
+ .debug_macro   0x0000000000000000      0x830 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.o
+ .debug_macro   0x0000000000000000       0x16 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.o
+ .debug_macro   0x0000000000000000      0x1ce ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.o
+ .debug_macro   0x0000000000000000      0xb1d ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.o
+ .debug_macro   0x0000000000000000      0x29f ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.o
+ .debug_macro   0x0000000000000000      0x693 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.o
+ .debug_macro   0x0000000000000000       0xa6 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.o
  .debug_macro   0x0000000000000000      0x5e6 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.o
- .debug_line    0x0000000000000000      0xff1 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.o
- .debug_str     0x0000000000000000   0x1392f2 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.o
+ .debug_line    0x0000000000000000     0x10d2 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.o
+ .debug_str     0x0000000000000000   0x157983 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.o
  .comment       0x0000000000000000       0x44 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.o
  .debug_frame   0x0000000000000000      0x484 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.o
  .ARM.attributes
@@ -2741,15 +3592,19 @@ Discarded input sections
  .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.o
  .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.o
  .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.o
  .text          0x0000000000000000        0x0 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.o
  .data          0x0000000000000000        0x0 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.o
  .bss           0x0000000000000000        0x0 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.o
  .text.HAL_GPIO_DeInit
                 0x0000000000000000      0x204 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.o
- .text.HAL_GPIO_ReadPin
-                0x0000000000000000       0x30 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.o
- .text.HAL_GPIO_WritePin
-                0x0000000000000000       0x32 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.o
  .text.HAL_GPIO_TogglePin
                 0x0000000000000000       0x34 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.o
  .text.HAL_GPIO_LockPin
@@ -2759,7 +3614,7 @@ Discarded input sections
  .text.HAL_GPIO_EXTI_Callback
                 0x0000000000000000       0x16 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.o
  .debug_macro   0x0000000000000000      0xac6 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.o
- .debug_macro   0x0000000000000000      0x232 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.o
+ .debug_macro   0x0000000000000000      0x24a ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.o
  .debug_macro   0x0000000000000000       0x2e ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.o
  .debug_macro   0x0000000000000000       0x3b ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.o
  .debug_macro   0x0000000000000000       0x22 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.o
@@ -2807,6 +3662,7 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x129 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.o
  .debug_macro   0x0000000000000000      0x3f9 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.o
  .debug_macro   0x0000000000000000      0x275 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.o
+ .debug_macro   0x0000000000000000      0xe42 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.o
  .debug_macro   0x0000000000000000      0x3ca ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.o
  .debug_macro   0x0000000000000000      0x45c ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.o
  .debug_macro   0x0000000000000000       0x3c ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.o
@@ -2817,6 +3673,13 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x1c4 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.o
  .debug_macro   0x0000000000000000      0x22a ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.o
  .debug_macro   0x0000000000000000       0x35 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.o
+ .debug_macro   0x0000000000000000      0x830 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.o
+ .debug_macro   0x0000000000000000       0x16 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.o
+ .debug_macro   0x0000000000000000      0x1ce ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.o
+ .debug_macro   0x0000000000000000      0xb1d ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.o
+ .debug_macro   0x0000000000000000      0x29f ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.o
+ .debug_macro   0x0000000000000000      0x693 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.o
+ .debug_macro   0x0000000000000000       0xa6 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.o
  .debug_macro   0x0000000000000000      0x5e6 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.o
  .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.o
  .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.o
@@ -2878,6 +3741,14 @@ Discarded input sections
  .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.o
  .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.o
  .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.o
  .text          0x0000000000000000        0x0 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.o
  .data          0x0000000000000000        0x0 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.o
  .bss           0x0000000000000000        0x0 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.o
@@ -2909,9 +3780,9 @@ Discarded input sections
                 0x0000000000000000       0x70 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.o
  .debug_rnglists
                 0x0000000000000000       0x4f ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.o
- .debug_macro   0x0000000000000000      0x294 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.o
+ .debug_macro   0x0000000000000000      0x2f3 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.o
  .debug_macro   0x0000000000000000      0xac6 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.o
- .debug_macro   0x0000000000000000      0x232 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.o
+ .debug_macro   0x0000000000000000      0x24a ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.o
  .debug_macro   0x0000000000000000       0x2e ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.o
  .debug_macro   0x0000000000000000       0x3b ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.o
  .debug_macro   0x0000000000000000       0x22 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.o
@@ -2959,6 +3830,7 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x129 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.o
  .debug_macro   0x0000000000000000      0x3f9 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.o
  .debug_macro   0x0000000000000000      0x275 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.o
+ .debug_macro   0x0000000000000000      0xe42 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.o
  .debug_macro   0x0000000000000000      0x3ca ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.o
  .debug_macro   0x0000000000000000      0x45c ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.o
  .debug_macro   0x0000000000000000       0x3c ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.o
@@ -2969,9 +3841,16 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x1c4 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.o
  .debug_macro   0x0000000000000000      0x22a ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.o
  .debug_macro   0x0000000000000000       0x35 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.o
+ .debug_macro   0x0000000000000000      0x830 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.o
+ .debug_macro   0x0000000000000000       0x16 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.o
+ .debug_macro   0x0000000000000000      0x1ce ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.o
+ .debug_macro   0x0000000000000000      0xb1d ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.o
+ .debug_macro   0x0000000000000000      0x29f ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.o
+ .debug_macro   0x0000000000000000      0x693 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.o
+ .debug_macro   0x0000000000000000       0xa6 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.o
  .debug_macro   0x0000000000000000      0x5e6 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.o
- .debug_line    0x0000000000000000      0xa21 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.o
- .debug_str     0x0000000000000000   0x138cb0 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.o
+ .debug_line    0x0000000000000000      0xb02 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.o
+ .debug_str     0x0000000000000000   0x157341 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.o
  .comment       0x0000000000000000       0x44 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.o
  .debug_frame   0x0000000000000000      0x1bc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.o
  .ARM.attributes
@@ -3036,6 +3915,14 @@ Discarded input sections
  .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.o
  .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.o
  .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.o
  .text          0x0000000000000000        0x0 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.o
  .data          0x0000000000000000        0x0 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.o
  .bss           0x0000000000000000        0x0 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.o
@@ -3207,9 +4094,9 @@ Discarded input sections
                 0x0000000000000000      0x2a0 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.o
  .debug_rnglists
                 0x0000000000000000      0x22a ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.o
- .debug_macro   0x0000000000000000      0x360 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.o
+ .debug_macro   0x0000000000000000      0x3bf ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.o
  .debug_macro   0x0000000000000000      0xac6 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.o
- .debug_macro   0x0000000000000000      0x232 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.o
+ .debug_macro   0x0000000000000000      0x24a ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.o
  .debug_macro   0x0000000000000000       0x2e ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.o
  .debug_macro   0x0000000000000000       0x3b ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.o
  .debug_macro   0x0000000000000000       0x22 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.o
@@ -3257,6 +4144,7 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x129 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.o
  .debug_macro   0x0000000000000000      0x3f9 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.o
  .debug_macro   0x0000000000000000      0x275 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.o
+ .debug_macro   0x0000000000000000      0xe42 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.o
  .debug_macro   0x0000000000000000      0x3ca ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.o
  .debug_macro   0x0000000000000000      0x45c ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.o
  .debug_macro   0x0000000000000000       0x3c ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.o
@@ -3267,9 +4155,16 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x1c4 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.o
  .debug_macro   0x0000000000000000      0x22a ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.o
  .debug_macro   0x0000000000000000       0x35 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.o
+ .debug_macro   0x0000000000000000      0x830 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.o
+ .debug_macro   0x0000000000000000       0x16 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.o
+ .debug_macro   0x0000000000000000      0x1ce ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.o
+ .debug_macro   0x0000000000000000      0xb1d ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.o
+ .debug_macro   0x0000000000000000      0x29f ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.o
+ .debug_macro   0x0000000000000000      0x693 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.o
+ .debug_macro   0x0000000000000000       0xa6 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.o
  .debug_macro   0x0000000000000000      0x5e6 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.o
- .debug_line    0x0000000000000000     0x3c52 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.o
- .debug_str     0x0000000000000000   0x13a0cc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.o
+ .debug_line    0x0000000000000000     0x3d33 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.o
+ .debug_str     0x0000000000000000   0x15875d ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.o
  .comment       0x0000000000000000       0x44 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.o
  .debug_frame   0x0000000000000000      0xc40 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.o
  .ARM.attributes
@@ -3334,6 +4229,14 @@ Discarded input sections
  .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.o
  .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.o
  .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.o
  .text          0x0000000000000000        0x0 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.o
  .data          0x0000000000000000        0x0 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.o
  .bss           0x0000000000000000        0x0 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.o
@@ -3355,9 +4258,9 @@ Discarded input sections
                 0x0000000000000000       0x48 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.o
  .debug_rnglists
                 0x0000000000000000       0x35 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.o
- .debug_macro   0x0000000000000000      0x294 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.o
+ .debug_macro   0x0000000000000000      0x2f3 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.o
  .debug_macro   0x0000000000000000      0xac6 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.o
- .debug_macro   0x0000000000000000      0x232 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.o
+ .debug_macro   0x0000000000000000      0x24a ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.o
  .debug_macro   0x0000000000000000       0x2e ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.o
  .debug_macro   0x0000000000000000       0x3b ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.o
  .debug_macro   0x0000000000000000       0x22 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.o
@@ -3405,6 +4308,7 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x129 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.o
  .debug_macro   0x0000000000000000      0x3f9 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.o
  .debug_macro   0x0000000000000000      0x275 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.o
+ .debug_macro   0x0000000000000000      0xe42 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.o
  .debug_macro   0x0000000000000000      0x3ca ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.o
  .debug_macro   0x0000000000000000      0x45c ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.o
  .debug_macro   0x0000000000000000       0x3c ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.o
@@ -3415,9 +4319,16 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x1c4 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.o
  .debug_macro   0x0000000000000000      0x22a ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.o
  .debug_macro   0x0000000000000000       0x35 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.o
+ .debug_macro   0x0000000000000000      0x830 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.o
+ .debug_macro   0x0000000000000000       0x16 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.o
+ .debug_macro   0x0000000000000000      0x1ce ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.o
+ .debug_macro   0x0000000000000000      0xb1d ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.o
+ .debug_macro   0x0000000000000000      0x29f ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.o
+ .debug_macro   0x0000000000000000      0x693 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.o
+ .debug_macro   0x0000000000000000       0xa6 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.o
  .debug_macro   0x0000000000000000      0x5e6 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.o
- .debug_line    0x0000000000000000      0xacf ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.o
- .debug_str     0x0000000000000000   0x139499 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.o
+ .debug_line    0x0000000000000000      0xbb0 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.o
+ .debug_str     0x0000000000000000   0x157b2a ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.o
  .comment       0x0000000000000000       0x44 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.o
  .debug_frame   0x0000000000000000      0x100 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.o
  .ARM.attributes
@@ -3482,15 +4393,19 @@ Discarded input sections
  .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.o
  .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.o
  .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.o
  .text          0x0000000000000000        0x0 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.o
  .data          0x0000000000000000        0x0 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.o
  .bss           0x0000000000000000        0x0 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.o
- .text.HAL_MDMA_Init
-                0x0000000000000000       0x98 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.o
  .text.HAL_MDMA_DeInit
                 0x0000000000000000       0xb0 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.o
- .text.HAL_MDMA_ConfigPostRequestMask
-                0x0000000000000000       0xa4 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.o
  .text.HAL_MDMA_RegisterCallback
                 0x0000000000000000       0xb4 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.o
  .text.HAL_MDMA_UnRegisterCallback
@@ -3517,25 +4432,14 @@ Discarded input sections
                 0x0000000000000000      0x194 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.o
  .text.HAL_MDMA_GenerateSWRequest
                 0x0000000000000000       0x74 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.o
- .text.HAL_MDMA_IRQHandler
-                0x0000000000000000      0x2a8 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.o
  .text.HAL_MDMA_GetState
                 0x0000000000000000       0x1c ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.o
  .text.HAL_MDMA_GetError
                 0x0000000000000000       0x18 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.o
  .text.MDMA_SetConfig
                 0x0000000000000000       0xe0 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.o
- .text.MDMA_Init
-                0x0000000000000000      0x130 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.o
- .debug_info    0x0000000000000000      0xbbe ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.o
- .debug_abbrev  0x0000000000000000      0x1f8 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.o
- .debug_aranges
-                0x0000000000000000       0xc0 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.o
- .debug_rnglists
-                0x0000000000000000       0x9c ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.o
- .debug_macro   0x0000000000000000      0x2a3 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.o
  .debug_macro   0x0000000000000000      0xac6 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.o
- .debug_macro   0x0000000000000000      0x232 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.o
+ .debug_macro   0x0000000000000000      0x24a ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.o
  .debug_macro   0x0000000000000000       0x2e ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.o
  .debug_macro   0x0000000000000000       0x3b ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.o
  .debug_macro   0x0000000000000000       0x22 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.o
@@ -3583,6 +4487,7 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x129 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.o
  .debug_macro   0x0000000000000000      0x3f9 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.o
  .debug_macro   0x0000000000000000      0x275 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.o
+ .debug_macro   0x0000000000000000      0xe42 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.o
  .debug_macro   0x0000000000000000      0x3ca ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.o
  .debug_macro   0x0000000000000000      0x45c ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.o
  .debug_macro   0x0000000000000000       0x3c ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.o
@@ -3593,13 +4498,22 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x1c4 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.o
  .debug_macro   0x0000000000000000      0x22a ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.o
  .debug_macro   0x0000000000000000       0x35 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.o
+ .debug_macro   0x0000000000000000      0x830 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.o
+ .debug_macro   0x0000000000000000       0x16 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.o
+ .debug_macro   0x0000000000000000      0x1ce ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.o
+ .debug_macro   0x0000000000000000      0xb1d ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.o
+ .debug_macro   0x0000000000000000      0x29f ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.o
+ .debug_macro   0x0000000000000000      0x693 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.o
+ .debug_macro   0x0000000000000000       0xa6 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.o
  .debug_macro   0x0000000000000000      0x5e6 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.o
- .debug_line    0x0000000000000000     0x14d6 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.o
- .debug_str     0x0000000000000000   0x1393a5 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.o
- .comment       0x0000000000000000       0x44 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.o
- .debug_frame   0x0000000000000000      0x34c ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.o
- .ARM.attributes
-                0x0000000000000000       0x32 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.o
  .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.o
  .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.o
  .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.o
@@ -3703,9 +4617,9 @@ Discarded input sections
                 0x0000000000000000       0xa0 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.o
  .debug_rnglists
                 0x0000000000000000       0x74 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.o
- .debug_macro   0x0000000000000000      0x2b8 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.o
+ .debug_macro   0x0000000000000000      0x317 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.o
  .debug_macro   0x0000000000000000      0xac6 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.o
- .debug_macro   0x0000000000000000      0x232 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.o
+ .debug_macro   0x0000000000000000      0x24a ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.o
  .debug_macro   0x0000000000000000       0x2e ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.o
  .debug_macro   0x0000000000000000       0x3b ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.o
  .debug_macro   0x0000000000000000       0x22 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.o
@@ -3753,6 +4667,7 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x129 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.o
  .debug_macro   0x0000000000000000      0x3f9 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.o
  .debug_macro   0x0000000000000000      0x275 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.o
+ .debug_macro   0x0000000000000000      0xe42 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.o
  .debug_macro   0x0000000000000000      0x3ca ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.o
  .debug_macro   0x0000000000000000      0x45c ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.o
  .debug_macro   0x0000000000000000       0x3c ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.o
@@ -3763,9 +4678,16 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x1c4 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.o
  .debug_macro   0x0000000000000000      0x22a ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.o
  .debug_macro   0x0000000000000000       0x35 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.o
+ .debug_macro   0x0000000000000000      0x830 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.o
+ .debug_macro   0x0000000000000000       0x16 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.o
+ .debug_macro   0x0000000000000000      0x1ce ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.o
+ .debug_macro   0x0000000000000000      0xb1d ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.o
+ .debug_macro   0x0000000000000000      0x29f ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.o
+ .debug_macro   0x0000000000000000      0x693 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.o
+ .debug_macro   0x0000000000000000       0xa6 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.o
  .debug_macro   0x0000000000000000      0x5e6 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.o
- .debug_line    0x0000000000000000      0xaca ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.o
- .debug_str     0x0000000000000000   0x138fef ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.o
+ .debug_line    0x0000000000000000      0xbab ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.o
+ .debug_str     0x0000000000000000   0x157680 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.o
  .comment       0x0000000000000000       0x44 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.o
  .debug_frame   0x0000000000000000      0x254 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.o
  .ARM.attributes
@@ -3830,6 +4752,14 @@ Discarded input sections
  .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.o
  .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.o
  .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.o
  .text          0x0000000000000000        0x0 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.o
  .data          0x0000000000000000        0x0 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.o
  .bss           0x0000000000000000        0x0 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.o
@@ -3908,7 +4838,7 @@ Discarded input sections
  .text.HAL_PWREx_AVDCallback
                 0x0000000000000000        0xe ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.o
  .debug_macro   0x0000000000000000      0xac6 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.o
- .debug_macro   0x0000000000000000      0x232 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.o
+ .debug_macro   0x0000000000000000      0x24a ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.o
  .debug_macro   0x0000000000000000       0x2e ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.o
  .debug_macro   0x0000000000000000       0x3b ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.o
  .debug_macro   0x0000000000000000       0x22 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.o
@@ -3956,6 +4886,7 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x129 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.o
  .debug_macro   0x0000000000000000      0x3f9 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.o
  .debug_macro   0x0000000000000000      0x275 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.o
+ .debug_macro   0x0000000000000000      0xe42 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.o
  .debug_macro   0x0000000000000000      0x3ca ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.o
  .debug_macro   0x0000000000000000      0x45c ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.o
  .debug_macro   0x0000000000000000       0x3c ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.o
@@ -3966,6 +4897,13 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x1c4 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.o
  .debug_macro   0x0000000000000000      0x22a ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.o
  .debug_macro   0x0000000000000000       0x35 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.o
+ .debug_macro   0x0000000000000000      0x830 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.o
+ .debug_macro   0x0000000000000000       0x16 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.o
+ .debug_macro   0x0000000000000000      0x1ce ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.o
+ .debug_macro   0x0000000000000000      0xb1d ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.o
+ .debug_macro   0x0000000000000000      0x29f ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.o
+ .debug_macro   0x0000000000000000      0x693 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.o
+ .debug_macro   0x0000000000000000       0xa6 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.o
  .debug_macro   0x0000000000000000      0x5e6 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.o
  .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.o
  .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.o
@@ -4027,6 +4965,14 @@ Discarded input sections
  .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.o
  .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.o
  .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.o
  .text          0x0000000000000000        0x0 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.o
  .data          0x0000000000000000        0x0 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.o
  .bss           0x0000000000000000        0x0 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.o
@@ -4038,20 +4984,14 @@ Discarded input sections
                 0x0000000000000000       0x20 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.o
  .text.HAL_RCC_DisableCSS
                 0x0000000000000000       0x20 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.o
- .text.HAL_RCC_GetPCLK1Freq
-                0x0000000000000000       0x2c ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.o
- .text.HAL_RCC_GetPCLK2Freq
-                0x0000000000000000       0x2c ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.o
  .text.HAL_RCC_GetOscConfig
                 0x0000000000000000      0x1a4 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.o
- .text.HAL_RCC_GetClockConfig
-                0x0000000000000000       0x84 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.o
  .text.HAL_RCC_NMI_IRQHandler
                 0x0000000000000000       0x28 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.o
  .text.HAL_RCC_CSSCallback
                 0x0000000000000000        0xe ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.o
  .debug_macro   0x0000000000000000      0xac6 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.o
- .debug_macro   0x0000000000000000      0x232 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.o
+ .debug_macro   0x0000000000000000      0x24a ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.o
  .debug_macro   0x0000000000000000       0x2e ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.o
  .debug_macro   0x0000000000000000       0x3b ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.o
  .debug_macro   0x0000000000000000       0x22 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.o
@@ -4099,6 +5039,7 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x129 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.o
  .debug_macro   0x0000000000000000      0x3f9 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.o
  .debug_macro   0x0000000000000000      0x275 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.o
+ .debug_macro   0x0000000000000000      0xe42 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.o
  .debug_macro   0x0000000000000000      0x3ca ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.o
  .debug_macro   0x0000000000000000      0x45c ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.o
  .debug_macro   0x0000000000000000       0x3c ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.o
@@ -4109,6 +5050,13 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x1c4 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.o
  .debug_macro   0x0000000000000000      0x22a ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.o
  .debug_macro   0x0000000000000000       0x35 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.o
+ .debug_macro   0x0000000000000000      0x830 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.o
+ .debug_macro   0x0000000000000000       0x16 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.o
+ .debug_macro   0x0000000000000000      0x1ce ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.o
+ .debug_macro   0x0000000000000000      0xb1d ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.o
+ .debug_macro   0x0000000000000000      0x29f ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.o
+ .debug_macro   0x0000000000000000      0x693 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.o
+ .debug_macro   0x0000000000000000       0xa6 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.o
  .debug_macro   0x0000000000000000      0x5e6 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.o
  .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.o
  .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.o
@@ -4170,25 +5118,21 @@ Discarded input sections
  .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.o
  .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.o
  .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.o
  .text          0x0000000000000000        0x0 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.o
  .data          0x0000000000000000        0x0 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.o
  .bss           0x0000000000000000        0x0 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.o
- .text.HAL_RCCEx_PeriphCLKConfig
-                0x0000000000000000     0x1340 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.o
  .text.HAL_RCCEx_GetPeriphCLKConfig
                 0x0000000000000000      0x2d0 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.o
- .text.HAL_RCCEx_GetPeriphCLKFreq
-                0x0000000000000000      0x9a4 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.o
  .text.HAL_RCCEx_GetD1PCLK1Freq
                 0x0000000000000000       0x2c ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.o
- .text.HAL_RCCEx_GetD3PCLK1Freq
-                0x0000000000000000       0x2c ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.o
- .text.HAL_RCCEx_GetPLL2ClockFreq
-                0x0000000000000000      0x2a8 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.o
- .text.HAL_RCCEx_GetPLL3ClockFreq
-                0x0000000000000000      0x2a8 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.o
- .text.HAL_RCCEx_GetPLL1ClockFreq
-                0x0000000000000000      0x2a4 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.o
  .text.HAL_RCCEx_GetD1SysClockFreq
                 0x0000000000000000       0x60 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.o
  .text.HAL_RCCEx_EnableLSECSS
@@ -4221,23 +5165,12 @@ Discarded input sections
                 0x0000000000000000        0xe ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.o
  .text.HAL_RCCEx_CRS_ErrorCallback
                 0x0000000000000000       0x14 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.o
- .text.RCCEx_PLL2_Config
-                0x0000000000000000      0x164 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.o
- .text.RCCEx_PLL3_Config
-                0x0000000000000000      0x164 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.o
  .text.HAL_RCCEx_LSECSS_IRQHandler
                 0x0000000000000000       0x28 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.o
  .text.HAL_RCCEx_LSECSS_Callback
                 0x0000000000000000        0xe ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.o
- .debug_info    0x0000000000000000     0x11fc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.o
- .debug_abbrev  0x0000000000000000      0x269 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.o
- .debug_aranges
-                0x0000000000000000       0xf8 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.o
- .debug_rnglists
-                0x0000000000000000       0xc0 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.o
- .debug_macro   0x0000000000000000      0x2b2 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.o
  .debug_macro   0x0000000000000000      0xac6 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.o
- .debug_macro   0x0000000000000000      0x232 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.o
+ .debug_macro   0x0000000000000000      0x24a ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.o
  .debug_macro   0x0000000000000000       0x2e ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.o
  .debug_macro   0x0000000000000000       0x3b ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.o
  .debug_macro   0x0000000000000000       0x22 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.o
@@ -4285,6 +5218,7 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x129 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.o
  .debug_macro   0x0000000000000000      0x3f9 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.o
  .debug_macro   0x0000000000000000      0x275 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.o
+ .debug_macro   0x0000000000000000      0xe42 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.o
  .debug_macro   0x0000000000000000      0x3ca ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.o
  .debug_macro   0x0000000000000000      0x45c ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.o
  .debug_macro   0x0000000000000000       0x3c ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.o
@@ -4295,13 +5229,359 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x1c4 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.o
  .debug_macro   0x0000000000000000      0x22a ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.o
  .debug_macro   0x0000000000000000       0x35 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.o
+ .debug_macro   0x0000000000000000      0x830 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.o
+ .debug_macro   0x0000000000000000       0x16 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.o
+ .debug_macro   0x0000000000000000      0x1ce ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.o
+ .debug_macro   0x0000000000000000      0xb1d ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.o
+ .debug_macro   0x0000000000000000      0x29f ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.o
+ .debug_macro   0x0000000000000000      0x693 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.o
+ .debug_macro   0x0000000000000000       0xa6 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.o
  .debug_macro   0x0000000000000000      0x5e6 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.o
- .debug_line    0x0000000000000000     0x1c3f ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.o
- .debug_str     0x0000000000000000   0x1398c5 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.o
- .comment       0x0000000000000000       0x44 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.o
- .debug_frame   0x0000000000000000      0x414 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.o
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  .ARM.attributes
-                0x0000000000000000       0x32 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.o
+                0x0000000000000000       0x32 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd_ex.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.o
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+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.o
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  .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.o
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@@ -4365,13 +5645,224 @@ Discarded input sections
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- .debug_aranges
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+ .text.HAL_TIM_DMABurst_MultiReadStart
+                0x0000000000000000      0x2a8 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.o
+ .text.HAL_TIM_DMABurst_ReadStop
+                0x0000000000000000       0xf4 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.o
+ .text.HAL_TIM_GenerateEvent
+                0x0000000000000000       0x4e ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.o
+ .text.HAL_TIM_ConfigOCrefClear
+                0x0000000000000000      0x214 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.o
+ .text.HAL_TIM_ConfigTI1Input
+                0x0000000000000000       0x38 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.o
+ .text.HAL_TIM_SlaveConfigSynchro
+                0x0000000000000000       0x84 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.o
+ .text.HAL_TIM_SlaveConfigSynchro_IT
+                0x0000000000000000       0x84 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.o
+ .text.HAL_TIM_ReadCapturedValue
+                0x0000000000000000       0x88 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.o
+ .text.HAL_TIM_PeriodElapsedCallback
+                0x0000000000000000       0x14 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.o
+ .text.HAL_TIM_PeriodElapsedHalfCpltCallback
+                0x0000000000000000       0x14 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.o
+ .text.HAL_TIM_IC_CaptureHalfCpltCallback
+                0x0000000000000000       0x14 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.o
+ .text.HAL_TIM_PWM_PulseFinishedHalfCpltCallback
+                0x0000000000000000       0x14 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.o
+ .text.HAL_TIM_TriggerHalfCpltCallback
+                0x0000000000000000       0x14 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.o
+ .text.HAL_TIM_ErrorCallback
+                0x0000000000000000       0x14 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.o
+ .text.HAL_TIM_Base_GetState
+                0x0000000000000000       0x1c ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.o
+ .text.HAL_TIM_OC_GetState
+                0x0000000000000000       0x1c ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.o
+ .text.HAL_TIM_PWM_GetState
+                0x0000000000000000       0x1c ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.o
+ .text.HAL_TIM_IC_GetState
+                0x0000000000000000       0x1c ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.o
+ .text.HAL_TIM_OnePulse_GetState
+                0x0000000000000000       0x1c ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.o
+ .text.HAL_TIM_Encoder_GetState
+                0x0000000000000000       0x1c ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.o
+ .text.HAL_TIM_GetActiveChannel
                 0x0000000000000000       0x18 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.o
- .debug_macro   0x0000000000000000      0x295 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.o
+ .text.HAL_TIM_GetChannelState
+                0x0000000000000000       0x72 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.o
+ .text.HAL_TIM_DMABurstState
+                0x0000000000000000       0x1c ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.o
+ .text.TIM_DMAError
+                0x0000000000000000       0x92 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.o
+ .text.TIM_DMADelayPulseCplt
+                0x0000000000000000       0xa8 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.o
+ .text.TIM_DMADelayPulseHalfCplt
+                0x0000000000000000       0x68 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.o
+ .text.TIM_DMACaptureCplt
+                0x0000000000000000       0xc8 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.o
+ .text.TIM_DMACaptureHalfCplt
+                0x0000000000000000       0x68 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.o
+ .text.TIM_DMAPeriodElapsedCplt
+                0x0000000000000000       0x2e ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.o
+ .text.TIM_DMAPeriodElapsedHalfCplt
+                0x0000000000000000       0x1c ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.o
+ .text.TIM_DMATriggerCplt
+                0x0000000000000000       0x2e ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.o
+ .text.TIM_DMATriggerHalfCplt
+                0x0000000000000000       0x1c ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.o
+ .text.TIM_OC1_SetConfig
+                0x0000000000000000      0x120 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.o
+ .text.TIM_OC2_SetConfig
+                0x0000000000000000      0x114 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.o
+ .text.TIM_OC3_SetConfig
+                0x0000000000000000      0x110 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.o
+ .text.TIM_OC4_SetConfig
+                0x0000000000000000       0xd4 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.o
+ .text.TIM_OC5_SetConfig
+                0x0000000000000000       0xc8 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.o
+ .text.TIM_OC6_SetConfig
+                0x0000000000000000       0xcc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.o
+ .text.TIM_SlaveTimer_SetConfig
+                0x0000000000000000      0x1d4 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.o
+ .text.TIM_TI1_SetConfig
+                0x0000000000000000      0x100 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.o
+ .text.TIM_TI2_SetConfig
+                0x0000000000000000       0x7a ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.o
+ .text.TIM_TI3_SetConfig
+                0x0000000000000000       0x78 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.o
+ .text.TIM_TI4_SetConfig
+                0x0000000000000000       0x7a ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.o
+ .text.TIM_CCxChannelCmd
+                0x0000000000000000       0x4a ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.o
  .debug_macro   0x0000000000000000      0xac6 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.o
- .debug_macro   0x0000000000000000      0x232 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.o
+ .debug_macro   0x0000000000000000      0x24a ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.o
  .debug_macro   0x0000000000000000       0x2e ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.o
  .debug_macro   0x0000000000000000       0x3b ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.o
  .debug_macro   0x0000000000000000       0x22 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.o
@@ -4419,6 +5910,7 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x129 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.o
  .debug_macro   0x0000000000000000      0x3f9 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.o
  .debug_macro   0x0000000000000000      0x275 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.o
+ .debug_macro   0x0000000000000000      0xe42 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.o
  .debug_macro   0x0000000000000000      0x3ca ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.o
  .debug_macro   0x0000000000000000      0x45c ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.o
  .debug_macro   0x0000000000000000       0x3c ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.o
@@ -4429,12 +5921,22 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x1c4 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.o
  .debug_macro   0x0000000000000000      0x22a ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.o
  .debug_macro   0x0000000000000000       0x35 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.o
+ .debug_macro   0x0000000000000000      0x830 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.o
+ .debug_macro   0x0000000000000000       0x16 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.o
+ .debug_macro   0x0000000000000000      0x1ce ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.o
+ .debug_macro   0x0000000000000000      0xb1d ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.o
+ .debug_macro   0x0000000000000000      0x29f ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.o
+ .debug_macro   0x0000000000000000      0x693 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.o
+ .debug_macro   0x0000000000000000       0xa6 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.o
  .debug_macro   0x0000000000000000      0x5e6 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.o
- .debug_line    0x0000000000000000      0x8a7 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.o
- .debug_str     0x0000000000000000   0x138b02 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.o
- .comment       0x0000000000000000       0x44 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.o
- .ARM.attributes
-                0x0000000000000000       0x32 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.o
  .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.o
  .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.o
  .group         0x0000000000000000        0xc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.o
@@ -4498,13 +6000,96 @@ Discarded input sections
  .text          0x0000000000000000        0x0 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.o
  .data          0x0000000000000000        0x0 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.o
  .bss           0x0000000000000000        0x0 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.o
- .debug_info    0x0000000000000000       0x85 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.o
- .debug_abbrev  0x0000000000000000       0x28 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.o
- .debug_aranges
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- .debug_macro   0x0000000000000000      0x294 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.o
+ .text.HAL_TIMEx_HallSensor_Init
+                0x0000000000000000      0x15c ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.o
+ .text.HAL_TIMEx_HallSensor_DeInit
+                0x0000000000000000       0x88 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.o
+ .text.HAL_TIMEx_HallSensor_MspInit
+                0x0000000000000000       0x14 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.o
+ .text.HAL_TIMEx_HallSensor_MspDeInit
+                0x0000000000000000       0x14 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.o
+ .text.HAL_TIMEx_HallSensor_Start
+                0x0000000000000000      0x148 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.o
+ .text.HAL_TIMEx_HallSensor_Stop
+                0x0000000000000000       0x70 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.o
+ .text.HAL_TIMEx_HallSensor_Start_IT
+                0x0000000000000000      0x158 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.o
+ .text.HAL_TIMEx_HallSensor_Stop_IT
+                0x0000000000000000       0x80 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.o
+ .text.HAL_TIMEx_HallSensor_Start_DMA
+                0x0000000000000000      0x198 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.o
+ .text.HAL_TIMEx_HallSensor_Stop_DMA
+                0x0000000000000000       0x7a ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.o
+ .text.HAL_TIMEx_OCN_Start
+                0x0000000000000000      0x1a0 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.o
+ .text.HAL_TIMEx_OCN_Stop
+                0x0000000000000000       0xba ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.o
+ .text.HAL_TIMEx_OCN_Start_IT
+                0x0000000000000000      0x210 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.o
+ .text.HAL_TIMEx_OCN_Stop_IT
+                0x0000000000000000      0x13e ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.o
+ .text.HAL_TIMEx_OCN_Start_DMA
+                0x0000000000000000      0x32c ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.o
+ .text.HAL_TIMEx_OCN_Stop_DMA
+                0x0000000000000000      0x138 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.o
+ .text.HAL_TIMEx_PWMN_Start
+                0x0000000000000000      0x1a0 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.o
+ .text.HAL_TIMEx_PWMN_Stop
+                0x0000000000000000       0xba ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.o
+ .text.HAL_TIMEx_PWMN_Start_IT
+                0x0000000000000000      0x210 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.o
+ .text.HAL_TIMEx_PWMN_Stop_IT
+                0x0000000000000000      0x13e ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.o
+ .text.HAL_TIMEx_PWMN_Start_DMA
+                0x0000000000000000      0x32c ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.o
+ .text.HAL_TIMEx_PWMN_Stop_DMA
+                0x0000000000000000      0x138 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.o
+ .text.HAL_TIMEx_OnePulseN_Start
+                0x0000000000000000       0xaa ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.o
+ .text.HAL_TIMEx_OnePulseN_Stop
+                0x0000000000000000       0xbe ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.o
+ .text.HAL_TIMEx_OnePulseN_Start_IT
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+ .text.HAL_TIMEx_OnePulseN_Stop_IT
+                0x0000000000000000       0xde ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.o
+ .text.HAL_TIMEx_ConfigCommutEvent
+                0x0000000000000000       0xd8 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.o
+ .text.HAL_TIMEx_ConfigCommutEvent_IT
+                0x0000000000000000       0xd8 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.o
+ .text.HAL_TIMEx_ConfigCommutEvent_DMA
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+ .text.HAL_TIMEx_ConfigBreakDeadTime
+                0x0000000000000000      0x140 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.o
+ .text.HAL_TIMEx_ConfigBreakInput
+                0x0000000000000000      0x18c ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.o
+ .text.HAL_TIMEx_RemapConfig
+                0x0000000000000000       0x4a ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.o
+ .text.HAL_TIMEx_TISelection
+                0x0000000000000000       0xdc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.o
+ .text.HAL_TIMEx_GroupChannel5
+                0x0000000000000000       0x66 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.o
+ .text.HAL_TIMEx_DisarmBreakInput
+                0x0000000000000000       0x92 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.o
+ .text.HAL_TIMEx_ReArmBreakInput
+                0x0000000000000000       0xc2 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.o
+ .text.HAL_TIMEx_CommutHalfCpltCallback
+                0x0000000000000000       0x14 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.o
+ .text.HAL_TIMEx_HallSensor_GetState
+                0x0000000000000000       0x1c ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.o
+ .text.HAL_TIMEx_GetChannelNState
+                0x0000000000000000       0x52 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.o
+ .text.TIMEx_DMACommutationCplt
+                0x0000000000000000       0x24 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.o
+ .text.TIMEx_DMACommutationHalfCplt
+                0x0000000000000000       0x24 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.o
+ .text.TIM_DMADelayPulseNCplt
+                0x0000000000000000       0xa8 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.o
+ .text.TIM_DMAErrorCCxN
+                0x0000000000000000       0x6e ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.o
+ .text.TIM_CCxNChannelCmd
+                0x0000000000000000       0x4a ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.o
  .debug_macro   0x0000000000000000      0xac6 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.o
- .debug_macro   0x0000000000000000      0x232 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.o
+ .debug_macro   0x0000000000000000      0x24a ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.o
  .debug_macro   0x0000000000000000       0x2e ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.o
  .debug_macro   0x0000000000000000       0x3b ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.o
  .debug_macro   0x0000000000000000       0x22 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.o
@@ -4552,6 +6137,7 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x129 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.o
  .debug_macro   0x0000000000000000      0x3f9 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.o
  .debug_macro   0x0000000000000000      0x275 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.o
+ .debug_macro   0x0000000000000000      0xe42 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.o
  .debug_macro   0x0000000000000000      0x3ca ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.o
  .debug_macro   0x0000000000000000      0x45c ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.o
  .debug_macro   0x0000000000000000       0x3c ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.o
@@ -4562,277 +6148,1745 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x1c4 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.o
  .debug_macro   0x0000000000000000      0x22a ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.o
  .debug_macro   0x0000000000000000       0x35 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.o
+ .debug_macro   0x0000000000000000      0x830 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.o
+ .debug_macro   0x0000000000000000       0x16 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.o
+ .debug_macro   0x0000000000000000      0x1ce ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.o
+ .debug_macro   0x0000000000000000      0xb1d ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.o
+ .debug_macro   0x0000000000000000      0x29f ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.o
+ .debug_macro   0x0000000000000000      0x693 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.o
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+ .text.lwftp_store
+                0x0000000000000000       0xf8 ./LWFTPC/lwftpc.o
+ .text.lwftp_list
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+ .group         0x0000000000000000        0xc ./LWIP/App/lwip.o
+ .group         0x0000000000000000        0xc ./LWIP/App/lwip.o
+ .group         0x0000000000000000        0xc ./LWIP/App/lwip.o
+ .group         0x0000000000000000        0xc ./LWIP/App/lwip.o
+ .group         0x0000000000000000        0xc ./LWIP/App/lwip.o
+ .group         0x0000000000000000        0xc ./LWIP/App/lwip.o
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+ .group         0x0000000000000000        0xc ./LWIP/App/lwip.o
+ .group         0x0000000000000000        0xc ./LWIP/App/lwip.o
+ .group         0x0000000000000000        0xc ./LWIP/App/lwip.o
+ .group         0x0000000000000000        0xc ./LWIP/App/lwip.o
+ .group         0x0000000000000000        0xc ./LWIP/App/lwip.o
+ .group         0x0000000000000000        0xc ./LWIP/App/lwip.o
+ .group         0x0000000000000000        0xc ./LWIP/App/lwip.o
+ .group         0x0000000000000000        0xc ./LWIP/App/lwip.o
+ .group         0x0000000000000000        0xc ./LWIP/App/lwip.o
+ .group         0x0000000000000000        0xc ./LWIP/App/lwip.o
+ .group         0x0000000000000000        0xc ./LWIP/App/lwip.o
+ .group         0x0000000000000000        0xc ./LWIP/App/lwip.o
+ .group         0x0000000000000000        0xc ./LWIP/App/lwip.o
+ .group         0x0000000000000000        0xc ./LWIP/App/lwip.o
+ .group         0x0000000000000000        0xc ./LWIP/App/lwip.o
+ .group         0x0000000000000000        0xc ./LWIP/App/lwip.o
+ .group         0x0000000000000000        0xc ./LWIP/App/lwip.o
+ .group         0x0000000000000000        0xc ./LWIP/App/lwip.o
  .group         0x0000000000000000        0xc ./LWIP/App/lwip.o
  .group         0x0000000000000000        0xc ./LWIP/App/lwip.o
  .group         0x0000000000000000        0xc ./LWIP/App/lwip.o
@@ -4958,7 +8012,7 @@ Discarded input sections
  .data          0x0000000000000000        0x0 ./LWIP/App/lwip.o
  .bss           0x0000000000000000        0x0 ./LWIP/App/lwip.o
  .debug_macro   0x0000000000000000      0xac6 ./LWIP/App/lwip.o
- .debug_macro   0x0000000000000000      0x232 ./LWIP/App/lwip.o
+ .debug_macro   0x0000000000000000      0x24a ./LWIP/App/lwip.o
  .debug_macro   0x0000000000000000       0x2e ./LWIP/App/lwip.o
  .debug_macro   0x0000000000000000       0x3b ./LWIP/App/lwip.o
  .debug_macro   0x0000000000000000       0x22 ./LWIP/App/lwip.o
@@ -5006,6 +8060,7 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x129 ./LWIP/App/lwip.o
  .debug_macro   0x0000000000000000      0x3f9 ./LWIP/App/lwip.o
  .debug_macro   0x0000000000000000      0x275 ./LWIP/App/lwip.o
+ .debug_macro   0x0000000000000000      0xe42 ./LWIP/App/lwip.o
  .debug_macro   0x0000000000000000      0x3ca ./LWIP/App/lwip.o
  .debug_macro   0x0000000000000000      0x45c ./LWIP/App/lwip.o
  .debug_macro   0x0000000000000000       0x3c ./LWIP/App/lwip.o
@@ -5016,8 +8071,16 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x1c4 ./LWIP/App/lwip.o
  .debug_macro   0x0000000000000000      0x22a ./LWIP/App/lwip.o
  .debug_macro   0x0000000000000000       0x35 ./LWIP/App/lwip.o
+ .debug_macro   0x0000000000000000      0x830 ./LWIP/App/lwip.o
+ .debug_macro   0x0000000000000000       0x16 ./LWIP/App/lwip.o
+ .debug_macro   0x0000000000000000      0x1ce ./LWIP/App/lwip.o
+ .debug_macro   0x0000000000000000      0xb1d ./LWIP/App/lwip.o
+ .debug_macro   0x0000000000000000      0x29f ./LWIP/App/lwip.o
+ .debug_macro   0x0000000000000000      0x693 ./LWIP/App/lwip.o
+ .debug_macro   0x0000000000000000       0xa6 ./LWIP/App/lwip.o
  .debug_macro   0x0000000000000000      0x5e6 ./LWIP/App/lwip.o
- .debug_macro   0x0000000000000000       0xd0 ./LWIP/App/lwip.o
+ .debug_macro   0x0000000000000000       0x58 ./LWIP/App/lwip.o
+ .debug_macro   0x0000000000000000       0xe8 ./LWIP/App/lwip.o
  .debug_macro   0x0000000000000000       0x16 ./LWIP/App/lwip.o
  .debug_macro   0x0000000000000000       0x10 ./LWIP/App/lwip.o
  .debug_macro   0x0000000000000000       0x16 ./LWIP/App/lwip.o
@@ -5057,7 +8120,7 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x11f ./LWIP/App/lwip.o
  .debug_macro   0x0000000000000000       0x82 ./LWIP/App/lwip.o
  .debug_macro   0x0000000000000000       0x66 ./LWIP/App/lwip.o
- .debug_macro   0x0000000000000000      0x756 ./LWIP/App/lwip.o
+ .debug_macro   0x0000000000000000      0x739 ./LWIP/App/lwip.o
  .debug_macro   0x0000000000000000       0x10 ./LWIP/App/lwip.o
  .debug_macro   0x0000000000000000       0x10 ./LWIP/App/lwip.o
  .debug_macro   0x0000000000000000       0x3f ./LWIP/App/lwip.o
@@ -5077,6 +8140,49 @@ Discarded input sections
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  .debug_macro   0x0000000000000000       0x10 ./LWIP/App/lwip.o
  .debug_macro   0x0000000000000000       0x16 ./LWIP/App/lwip.o
+ .debug_macro   0x0000000000000000      0x111 ./LWIP/App/lwip.o
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+ .group         0x0000000000000000        0xc ./LWIP/Target/ethernetif.o
+ .group         0x0000000000000000        0xc ./LWIP/Target/ethernetif.o
+ .group         0x0000000000000000        0xc ./LWIP/Target/ethernetif.o
+ .group         0x0000000000000000        0xc ./LWIP/Target/ethernetif.o
+ .group         0x0000000000000000        0xc ./LWIP/Target/ethernetif.o
+ .group         0x0000000000000000        0xc ./LWIP/Target/ethernetif.o
+ .group         0x0000000000000000        0xc ./LWIP/Target/ethernetif.o
+ .group         0x0000000000000000        0xc ./LWIP/Target/ethernetif.o
+ .group         0x0000000000000000        0xc ./LWIP/Target/ethernetif.o
  .group         0x0000000000000000        0xc ./LWIP/Target/ethernetif.o
  .group         0x0000000000000000        0xc ./LWIP/Target/ethernetif.o
  .group         0x0000000000000000        0xc ./LWIP/Target/ethernetif.o
@@ -5204,10 +8310,8 @@ Discarded input sections
  .bss           0x0000000000000000        0x0 ./LWIP/Target/ethernetif.o
  .text.HAL_ETH_MspDeInit
                 0x0000000000000000       0x80 ./LWIP/Target/ethernetif.o
- .text.HAL_ETH_TxFreeCallback
-                0x0000000000000000       0x16 ./LWIP/Target/ethernetif.o
  .debug_macro   0x0000000000000000      0xac6 ./LWIP/Target/ethernetif.o
- .debug_macro   0x0000000000000000      0x232 ./LWIP/Target/ethernetif.o
+ .debug_macro   0x0000000000000000      0x24a ./LWIP/Target/ethernetif.o
  .debug_macro   0x0000000000000000       0x2e ./LWIP/Target/ethernetif.o
  .debug_macro   0x0000000000000000       0x3b ./LWIP/Target/ethernetif.o
  .debug_macro   0x0000000000000000       0x22 ./LWIP/Target/ethernetif.o
@@ -5255,6 +8359,7 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x129 ./LWIP/Target/ethernetif.o
  .debug_macro   0x0000000000000000      0x3f9 ./LWIP/Target/ethernetif.o
  .debug_macro   0x0000000000000000      0x275 ./LWIP/Target/ethernetif.o
+ .debug_macro   0x0000000000000000      0xe42 ./LWIP/Target/ethernetif.o
  .debug_macro   0x0000000000000000      0x3ca ./LWIP/Target/ethernetif.o
  .debug_macro   0x0000000000000000      0x45c ./LWIP/Target/ethernetif.o
  .debug_macro   0x0000000000000000       0x3c ./LWIP/Target/ethernetif.o
@@ -5265,8 +8370,16 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x1c4 ./LWIP/Target/ethernetif.o
  .debug_macro   0x0000000000000000      0x22a ./LWIP/Target/ethernetif.o
  .debug_macro   0x0000000000000000       0x35 ./LWIP/Target/ethernetif.o
+ .debug_macro   0x0000000000000000      0x830 ./LWIP/Target/ethernetif.o
+ .debug_macro   0x0000000000000000       0x16 ./LWIP/Target/ethernetif.o
+ .debug_macro   0x0000000000000000      0x1ce ./LWIP/Target/ethernetif.o
+ .debug_macro   0x0000000000000000      0xb1d ./LWIP/Target/ethernetif.o
+ .debug_macro   0x0000000000000000      0x29f ./LWIP/Target/ethernetif.o
+ .debug_macro   0x0000000000000000      0x693 ./LWIP/Target/ethernetif.o
+ .debug_macro   0x0000000000000000       0xa6 ./LWIP/Target/ethernetif.o
  .debug_macro   0x0000000000000000      0x5e6 ./LWIP/Target/ethernetif.o
- .debug_macro   0x0000000000000000       0xd6 ./LWIP/Target/ethernetif.o
+ .debug_macro   0x0000000000000000       0x58 ./LWIP/Target/ethernetif.o
+ .debug_macro   0x0000000000000000       0xee ./LWIP/Target/ethernetif.o
  .debug_macro   0x0000000000000000       0x16 ./LWIP/Target/ethernetif.o
  .debug_macro   0x0000000000000000       0x10 ./LWIP/Target/ethernetif.o
  .debug_macro   0x0000000000000000       0x16 ./LWIP/Target/ethernetif.o
@@ -5306,24 +8419,2150 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x11f ./LWIP/Target/ethernetif.o
  .debug_macro   0x0000000000000000       0x82 ./LWIP/Target/ethernetif.o
  .debug_macro   0x0000000000000000       0x66 ./LWIP/Target/ethernetif.o
- .debug_macro   0x0000000000000000      0x756 ./LWIP/Target/ethernetif.o
+ .debug_macro   0x0000000000000000      0x739 ./LWIP/Target/ethernetif.o
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+ .debug_macro   0x0000000000000000       0xf2 ./LWIP/Target/ethernetif.o
  .debug_macro   0x0000000000000000       0x10 ./LWIP/Target/ethernetif.o
+ .debug_macro   0x0000000000000000       0x73 ./LWIP/Target/ethernetif.o
  .debug_macro   0x0000000000000000       0x10 ./LWIP/Target/ethernetif.o
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+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/api/api_lib.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/api/api_lib.o
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  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/api/api_lib.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/api/api_lib.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/api/api_lib.o
@@ -5428,13 +10667,34 @@ Discarded input sections
  .text          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/api/api_lib.o
  .data          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/api/api_lib.o
  .bss           0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/api/api_lib.o
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- .debug_macro   0x0000000000000000      0x4a3 ./Middlewares/Third_Party/LwIP/src/api/api_lib.o
+ .text.netconn_getaddr
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+ .text.netconn_bind_if
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+ .text.netconn_disconnect
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+ .text.netconn_listen_with_backlog
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+ .text.netconn_accept
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+ .text.netconn_tcp_recvd
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+ .text.netconn_recv_tcp_pbuf
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+ .text.netconn_recv_tcp_pbuf_flags
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+ .text.netconn_recv_udp_raw_netbuf
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+ .text.netconn_recv_udp_raw_netbuf_flags
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+ .text.netconn_sendto
+                0x0000000000000000       0x44 ./Middlewares/Third_Party/LwIP/src/api/api_lib.o
+ .text.netconn_send
+                0x0000000000000000       0x5c ./Middlewares/Third_Party/LwIP/src/api/api_lib.o
+ .text.netconn_shutdown
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  .debug_macro   0x0000000000000000      0xac6 ./Middlewares/Third_Party/LwIP/src/api/api_lib.o
- .debug_macro   0x0000000000000000      0x232 ./Middlewares/Third_Party/LwIP/src/api/api_lib.o
+ .debug_macro   0x0000000000000000      0x24a ./Middlewares/Third_Party/LwIP/src/api/api_lib.o
  .debug_macro   0x0000000000000000       0x2e ./Middlewares/Third_Party/LwIP/src/api/api_lib.o
  .debug_macro   0x0000000000000000       0x3b ./Middlewares/Third_Party/LwIP/src/api/api_lib.o
  .debug_macro   0x0000000000000000       0x22 ./Middlewares/Third_Party/LwIP/src/api/api_lib.o
@@ -5482,6 +10742,7 @@ Discarded input sections
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  .debug_macro   0x0000000000000000      0x3f9 ./Middlewares/Third_Party/LwIP/src/api/api_lib.o
  .debug_macro   0x0000000000000000      0x275 ./Middlewares/Third_Party/LwIP/src/api/api_lib.o
+ .debug_macro   0x0000000000000000      0xe42 ./Middlewares/Third_Party/LwIP/src/api/api_lib.o
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@@ -5492,8 +10753,16 @@ Discarded input sections
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  .debug_macro   0x0000000000000000       0x35 ./Middlewares/Third_Party/LwIP/src/api/api_lib.o
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+ .debug_macro   0x0000000000000000       0xa6 ./Middlewares/Third_Party/LwIP/src/api/api_lib.o
  .debug_macro   0x0000000000000000      0x5e6 ./Middlewares/Third_Party/LwIP/src/api/api_lib.o
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- .ARM.attributes
-                0x0000000000000000       0x32 ./Middlewares/Third_Party/LwIP/src/api/api_lib.o
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+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/api/api_msg.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/api/api_msg.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/api/api_msg.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/api/api_msg.o
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  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/api/api_msg.o
@@ -5643,13 +10993,20 @@ Discarded input sections
  .text          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/api/api_msg.o
  .data          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/api/api_msg.o
  .bss           0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/api/api_msg.o
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- .debug_aranges
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- .debug_macro   0x0000000000000000      0x4a3 ./Middlewares/Third_Party/LwIP/src/api/api_msg.o
+ .text.accept_function
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+ .text.lwip_netconn_do_bind_if
+                0x0000000000000000       0x78 ./Middlewares/Third_Party/LwIP/src/api/api_msg.o
+ .text.lwip_netconn_do_disconnect
+                0x0000000000000000       0x3c ./Middlewares/Third_Party/LwIP/src/api/api_msg.o
+ .text.lwip_netconn_do_listen
+                0x0000000000000000      0x130 ./Middlewares/Third_Party/LwIP/src/api/api_msg.o
+ .text.lwip_netconn_do_send
+                0x0000000000000000       0x9a ./Middlewares/Third_Party/LwIP/src/api/api_msg.o
+ .text.lwip_netconn_do_getaddr
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  .debug_macro   0x0000000000000000      0xac6 ./Middlewares/Third_Party/LwIP/src/api/api_msg.o
- .debug_macro   0x0000000000000000      0x232 ./Middlewares/Third_Party/LwIP/src/api/api_msg.o
+ .debug_macro   0x0000000000000000      0x24a ./Middlewares/Third_Party/LwIP/src/api/api_msg.o
  .debug_macro   0x0000000000000000       0x2e ./Middlewares/Third_Party/LwIP/src/api/api_msg.o
  .debug_macro   0x0000000000000000       0x3b ./Middlewares/Third_Party/LwIP/src/api/api_msg.o
  .debug_macro   0x0000000000000000       0x22 ./Middlewares/Third_Party/LwIP/src/api/api_msg.o
@@ -5697,6 +11054,7 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x129 ./Middlewares/Third_Party/LwIP/src/api/api_msg.o
  .debug_macro   0x0000000000000000      0x3f9 ./Middlewares/Third_Party/LwIP/src/api/api_msg.o
  .debug_macro   0x0000000000000000      0x275 ./Middlewares/Third_Party/LwIP/src/api/api_msg.o
+ .debug_macro   0x0000000000000000      0xe42 ./Middlewares/Third_Party/LwIP/src/api/api_msg.o
  .debug_macro   0x0000000000000000      0x3ca ./Middlewares/Third_Party/LwIP/src/api/api_msg.o
  .debug_macro   0x0000000000000000      0x45c ./Middlewares/Third_Party/LwIP/src/api/api_msg.o
  .debug_macro   0x0000000000000000       0x3c ./Middlewares/Third_Party/LwIP/src/api/api_msg.o
@@ -5707,8 +11065,16 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x1c4 ./Middlewares/Third_Party/LwIP/src/api/api_msg.o
  .debug_macro   0x0000000000000000      0x22a ./Middlewares/Third_Party/LwIP/src/api/api_msg.o
  .debug_macro   0x0000000000000000       0x35 ./Middlewares/Third_Party/LwIP/src/api/api_msg.o
+ .debug_macro   0x0000000000000000      0x830 ./Middlewares/Third_Party/LwIP/src/api/api_msg.o
+ .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/api/api_msg.o
+ .debug_macro   0x0000000000000000      0x1ce ./Middlewares/Third_Party/LwIP/src/api/api_msg.o
+ .debug_macro   0x0000000000000000      0xb1d ./Middlewares/Third_Party/LwIP/src/api/api_msg.o
+ .debug_macro   0x0000000000000000      0x29f ./Middlewares/Third_Party/LwIP/src/api/api_msg.o
+ .debug_macro   0x0000000000000000      0x693 ./Middlewares/Third_Party/LwIP/src/api/api_msg.o
+ .debug_macro   0x0000000000000000       0xa6 ./Middlewares/Third_Party/LwIP/src/api/api_msg.o
  .debug_macro   0x0000000000000000      0x5e6 ./Middlewares/Third_Party/LwIP/src/api/api_msg.o
- .debug_macro   0x0000000000000000       0xd0 ./Middlewares/Third_Party/LwIP/src/api/api_msg.o
+ .debug_macro   0x0000000000000000       0x58 ./Middlewares/Third_Party/LwIP/src/api/api_msg.o
+ .debug_macro   0x0000000000000000       0xe8 ./Middlewares/Third_Party/LwIP/src/api/api_msg.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/api/api_msg.o
  .debug_macro   0x0000000000000000       0x10 ./Middlewares/Third_Party/LwIP/src/api/api_msg.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/api/api_msg.o
@@ -5748,12 +11114,76 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x11f ./Middlewares/Third_Party/LwIP/src/api/api_msg.o
  .debug_macro   0x0000000000000000       0x82 ./Middlewares/Third_Party/LwIP/src/api/api_msg.o
  .debug_macro   0x0000000000000000       0x66 ./Middlewares/Third_Party/LwIP/src/api/api_msg.o
- .debug_macro   0x0000000000000000      0x756 ./Middlewares/Third_Party/LwIP/src/api/api_msg.o
- .debug_line    0x0000000000000000      0xb77 ./Middlewares/Third_Party/LwIP/src/api/api_msg.o
- .debug_str     0x0000000000000000   0x13e826 ./Middlewares/Third_Party/LwIP/src/api/api_msg.o
- .comment       0x0000000000000000       0x44 ./Middlewares/Third_Party/LwIP/src/api/api_msg.o
- .ARM.attributes
-                0x0000000000000000       0x32 ./Middlewares/Third_Party/LwIP/src/api/api_msg.o
+ .debug_macro   0x0000000000000000      0x739 ./Middlewares/Third_Party/LwIP/src/api/api_msg.o
+ .debug_macro   0x0000000000000000       0x6a ./Middlewares/Third_Party/LwIP/src/api/api_msg.o
+ .debug_macro   0x0000000000000000      0x1c3 ./Middlewares/Third_Party/LwIP/src/api/api_msg.o
+ .debug_macro   0x0000000000000000      0x169 ./Middlewares/Third_Party/LwIP/src/api/api_msg.o
+ .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/api/api_msg.o
+ .debug_macro   0x0000000000000000      0x111 ./Middlewares/Third_Party/LwIP/src/api/api_msg.o
+ .debug_macro   0x0000000000000000      0x15a ./Middlewares/Third_Party/LwIP/src/api/api_msg.o
+ .debug_macro   0x0000000000000000       0xde ./Middlewares/Third_Party/LwIP/src/api/api_msg.o
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+ .debug_macro   0x0000000000000000       0xb5 ./Middlewares/Third_Party/LwIP/src/api/api_msg.o
+ .debug_macro   0x0000000000000000       0xaa ./Middlewares/Third_Party/LwIP/src/api/api_msg.o
+ .debug_macro   0x0000000000000000       0x91 ./Middlewares/Third_Party/LwIP/src/api/api_msg.o
+ .debug_macro   0x0000000000000000       0x8d ./Middlewares/Third_Party/LwIP/src/api/api_msg.o
+ .debug_macro   0x0000000000000000       0x7e ./Middlewares/Third_Party/LwIP/src/api/api_msg.o
+ .debug_macro   0x0000000000000000       0x19 ./Middlewares/Third_Party/LwIP/src/api/api_msg.o
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+ .debug_macro   0x0000000000000000       0x22 ./Middlewares/Third_Party/LwIP/src/api/api_msg.o
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+ .debug_macro   0x0000000000000000       0x40 ./Middlewares/Third_Party/LwIP/src/api/api_msg.o
+ .debug_macro   0x0000000000000000       0xda ./Middlewares/Third_Party/LwIP/src/api/api_msg.o
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+ .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/api/api_msg.o
+ .debug_macro   0x0000000000000000       0x4c ./Middlewares/Third_Party/LwIP/src/api/api_msg.o
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+ .debug_macro   0x0000000000000000       0xa0 ./Middlewares/Third_Party/LwIP/src/api/api_msg.o
+ .debug_macro   0x0000000000000000       0x28 ./Middlewares/Third_Party/LwIP/src/api/api_msg.o
+ .debug_macro   0x0000000000000000       0x2e ./Middlewares/Third_Party/LwIP/src/api/api_msg.o
+ .debug_macro   0x0000000000000000       0xea ./Middlewares/Third_Party/LwIP/src/api/api_msg.o
+ .debug_macro   0x0000000000000000       0x10 ./Middlewares/Third_Party/LwIP/src/api/api_msg.o
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+ .debug_macro   0x0000000000000000       0x70 ./Middlewares/Third_Party/LwIP/src/api/api_msg.o
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+ .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/api/api_msg.o
+ .debug_macro   0x0000000000000000       0x20 ./Middlewares/Third_Party/LwIP/src/api/api_msg.o
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+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/api/err.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/api/err.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/api/err.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/api/err.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/api/err.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/api/err.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/api/err.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/api/err.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/api/err.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/api/err.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/api/err.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/api/err.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/api/err.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/api/err.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/api/err.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/api/err.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/api/err.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/api/err.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/api/err.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/api/err.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/api/err.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/api/err.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/api/err.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/api/err.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/api/err.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/api/err.o
@@ -5861,8 +11291,24 @@ Discarded input sections
  .text          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/api/err.o
  .data          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/api/err.o
  .bss           0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/api/err.o
+ .rodata.err_to_errno_table
+                0x0000000000000000       0x44 ./Middlewares/Third_Party/LwIP/src/api/err.o
+ .text.err_to_errno
+                0x0000000000000000       0x3c ./Middlewares/Third_Party/LwIP/src/api/err.o
+ .rodata        0x0000000000000000      0x14b ./Middlewares/Third_Party/LwIP/src/api/err.o
+ .data.err_strerr
+                0x0000000000000000       0x44 ./Middlewares/Third_Party/LwIP/src/api/err.o
+ .text.lwip_strerr
+                0x0000000000000000       0x40 ./Middlewares/Third_Party/LwIP/src/api/err.o
+ .debug_info    0x0000000000000000      0x178 ./Middlewares/Third_Party/LwIP/src/api/err.o
+ .debug_abbrev  0x0000000000000000       0xba ./Middlewares/Third_Party/LwIP/src/api/err.o
+ .debug_aranges
+                0x0000000000000000       0x28 ./Middlewares/Third_Party/LwIP/src/api/err.o
+ .debug_rnglists
+                0x0000000000000000       0x19 ./Middlewares/Third_Party/LwIP/src/api/err.o
+ .debug_macro   0x0000000000000000      0x5f3 ./Middlewares/Third_Party/LwIP/src/api/err.o
  .debug_macro   0x0000000000000000      0xac6 ./Middlewares/Third_Party/LwIP/src/api/err.o
- .debug_macro   0x0000000000000000      0x232 ./Middlewares/Third_Party/LwIP/src/api/err.o
+ .debug_macro   0x0000000000000000      0x24a ./Middlewares/Third_Party/LwIP/src/api/err.o
  .debug_macro   0x0000000000000000       0x2e ./Middlewares/Third_Party/LwIP/src/api/err.o
  .debug_macro   0x0000000000000000       0x3b ./Middlewares/Third_Party/LwIP/src/api/err.o
  .debug_macro   0x0000000000000000       0x22 ./Middlewares/Third_Party/LwIP/src/api/err.o
@@ -5910,6 +11356,7 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x129 ./Middlewares/Third_Party/LwIP/src/api/err.o
  .debug_macro   0x0000000000000000      0x3f9 ./Middlewares/Third_Party/LwIP/src/api/err.o
  .debug_macro   0x0000000000000000      0x275 ./Middlewares/Third_Party/LwIP/src/api/err.o
+ .debug_macro   0x0000000000000000      0xe42 ./Middlewares/Third_Party/LwIP/src/api/err.o
  .debug_macro   0x0000000000000000      0x3ca ./Middlewares/Third_Party/LwIP/src/api/err.o
  .debug_macro   0x0000000000000000      0x45c ./Middlewares/Third_Party/LwIP/src/api/err.o
  .debug_macro   0x0000000000000000       0x3c ./Middlewares/Third_Party/LwIP/src/api/err.o
@@ -5920,8 +11367,16 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x1c4 ./Middlewares/Third_Party/LwIP/src/api/err.o
  .debug_macro   0x0000000000000000      0x22a ./Middlewares/Third_Party/LwIP/src/api/err.o
  .debug_macro   0x0000000000000000       0x35 ./Middlewares/Third_Party/LwIP/src/api/err.o
+ .debug_macro   0x0000000000000000      0x830 ./Middlewares/Third_Party/LwIP/src/api/err.o
+ .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/api/err.o
+ .debug_macro   0x0000000000000000      0x1ce ./Middlewares/Third_Party/LwIP/src/api/err.o
+ .debug_macro   0x0000000000000000      0xb1d ./Middlewares/Third_Party/LwIP/src/api/err.o
+ .debug_macro   0x0000000000000000      0x29f ./Middlewares/Third_Party/LwIP/src/api/err.o
+ .debug_macro   0x0000000000000000      0x693 ./Middlewares/Third_Party/LwIP/src/api/err.o
+ .debug_macro   0x0000000000000000       0xa6 ./Middlewares/Third_Party/LwIP/src/api/err.o
  .debug_macro   0x0000000000000000      0x5e6 ./Middlewares/Third_Party/LwIP/src/api/err.o
- .debug_macro   0x0000000000000000       0xd0 ./Middlewares/Third_Party/LwIP/src/api/err.o
+ .debug_macro   0x0000000000000000       0x58 ./Middlewares/Third_Party/LwIP/src/api/err.o
+ .debug_macro   0x0000000000000000       0xe8 ./Middlewares/Third_Party/LwIP/src/api/err.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/api/err.o
  .debug_macro   0x0000000000000000       0x10 ./Middlewares/Third_Party/LwIP/src/api/err.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/api/err.o
@@ -5961,8 +11416,75 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x11f ./Middlewares/Third_Party/LwIP/src/api/err.o
  .debug_macro   0x0000000000000000       0x82 ./Middlewares/Third_Party/LwIP/src/api/err.o
  .debug_macro   0x0000000000000000       0x66 ./Middlewares/Third_Party/LwIP/src/api/err.o
- .debug_macro   0x0000000000000000      0x756 ./Middlewares/Third_Party/LwIP/src/api/err.o
+ .debug_macro   0x0000000000000000      0x739 ./Middlewares/Third_Party/LwIP/src/api/err.o
  .debug_macro   0x0000000000000000       0x6a ./Middlewares/Third_Party/LwIP/src/api/err.o
+ .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/api/err.o
+ .debug_macro   0x0000000000000000      0x111 ./Middlewares/Third_Party/LwIP/src/api/err.o
+ .debug_macro   0x0000000000000000      0x15a ./Middlewares/Third_Party/LwIP/src/api/err.o
+ .debug_macro   0x0000000000000000       0xde ./Middlewares/Third_Party/LwIP/src/api/err.o
+ .debug_macro   0x0000000000000000       0x1c ./Middlewares/Third_Party/LwIP/src/api/err.o
+ .debug_macro   0x0000000000000000       0x26 ./Middlewares/Third_Party/LwIP/src/api/err.o
+ .debug_macro   0x0000000000000000      0x4ef ./Middlewares/Third_Party/LwIP/src/api/err.o
+ .debug_macro   0x0000000000000000       0xb5 ./Middlewares/Third_Party/LwIP/src/api/err.o
+ .debug_macro   0x0000000000000000       0xaa ./Middlewares/Third_Party/LwIP/src/api/err.o
+ .debug_macro   0x0000000000000000       0x91 ./Middlewares/Third_Party/LwIP/src/api/err.o
+ .debug_macro   0x0000000000000000       0x8d ./Middlewares/Third_Party/LwIP/src/api/err.o
+ .debug_macro   0x0000000000000000       0x7e ./Middlewares/Third_Party/LwIP/src/api/err.o
+ .debug_macro   0x0000000000000000       0x19 ./Middlewares/Third_Party/LwIP/src/api/err.o
+ .debug_macro   0x0000000000000000       0xf2 ./Middlewares/Third_Party/LwIP/src/api/err.o
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+ .debug_macro   0x0000000000000000       0x73 ./Middlewares/Third_Party/LwIP/src/api/err.o
+ .debug_macro   0x0000000000000000      0x320 ./Middlewares/Third_Party/LwIP/src/api/err.o
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+ .debug_str     0x0000000000000000   0x163ee9 ./Middlewares/Third_Party/LwIP/src/api/err.o
+ .comment       0x0000000000000000       0x44 ./Middlewares/Third_Party/LwIP/src/api/err.o
+ .debug_frame   0x0000000000000000       0x60 ./Middlewares/Third_Party/LwIP/src/api/err.o
+ .ARM.attributes
+                0x0000000000000000       0x32 ./Middlewares/Third_Party/LwIP/src/api/err.o
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+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/api/if_api.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/api/if_api.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/api/if_api.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/api/if_api.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/api/if_api.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/api/if_api.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/api/if_api.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/api/if_api.o
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+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/api/if_api.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/api/if_api.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/api/if_api.o
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+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/api/if_api.o
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+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/api/if_api.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/api/if_api.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/api/if_api.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/api/if_api.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/api/if_api.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/api/if_api.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/api/if_api.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/api/if_api.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/api/if_api.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/api/if_api.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/api/if_api.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/api/if_api.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/api/if_api.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/api/if_api.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/api/if_api.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/api/if_api.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/api/if_api.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/api/if_api.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/api/if_api.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/api/if_api.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/api/if_api.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/api/if_api.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/api/if_api.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/api/if_api.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/api/if_api.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/api/if_api.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/api/if_api.o
@@ -6067,13 +11589,19 @@ Discarded input sections
  .text          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/api/if_api.o
  .data          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/api/if_api.o
  .bss           0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/api/if_api.o
- .debug_info    0x0000000000000000       0x85 ./Middlewares/Third_Party/LwIP/src/api/if_api.o
- .debug_abbrev  0x0000000000000000       0x28 ./Middlewares/Third_Party/LwIP/src/api/if_api.o
+ .text.lwip_if_indextoname
+                0x0000000000000000       0x24 ./Middlewares/Third_Party/LwIP/src/api/if_api.o
+ .text.lwip_if_nametoindex
+                0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/api/if_api.o
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+ .debug_abbrev  0x0000000000000000       0x9a ./Middlewares/Third_Party/LwIP/src/api/if_api.o
  .debug_aranges
-                0x0000000000000000       0x18 ./Middlewares/Third_Party/LwIP/src/api/if_api.o
- .debug_macro   0x0000000000000000      0x4a3 ./Middlewares/Third_Party/LwIP/src/api/if_api.o
+                0x0000000000000000       0x28 ./Middlewares/Third_Party/LwIP/src/api/if_api.o
+ .debug_rnglists
+                0x0000000000000000       0x19 ./Middlewares/Third_Party/LwIP/src/api/if_api.o
+ .debug_macro   0x0000000000000000      0x6f8 ./Middlewares/Third_Party/LwIP/src/api/if_api.o
  .debug_macro   0x0000000000000000      0xac6 ./Middlewares/Third_Party/LwIP/src/api/if_api.o
- .debug_macro   0x0000000000000000      0x232 ./Middlewares/Third_Party/LwIP/src/api/if_api.o
+ .debug_macro   0x0000000000000000      0x24a ./Middlewares/Third_Party/LwIP/src/api/if_api.o
  .debug_macro   0x0000000000000000       0x2e ./Middlewares/Third_Party/LwIP/src/api/if_api.o
  .debug_macro   0x0000000000000000       0x3b ./Middlewares/Third_Party/LwIP/src/api/if_api.o
  .debug_macro   0x0000000000000000       0x22 ./Middlewares/Third_Party/LwIP/src/api/if_api.o
@@ -6121,6 +11649,7 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x129 ./Middlewares/Third_Party/LwIP/src/api/if_api.o
  .debug_macro   0x0000000000000000      0x3f9 ./Middlewares/Third_Party/LwIP/src/api/if_api.o
  .debug_macro   0x0000000000000000      0x275 ./Middlewares/Third_Party/LwIP/src/api/if_api.o
+ .debug_macro   0x0000000000000000      0xe42 ./Middlewares/Third_Party/LwIP/src/api/if_api.o
  .debug_macro   0x0000000000000000      0x3ca ./Middlewares/Third_Party/LwIP/src/api/if_api.o
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  .debug_macro   0x0000000000000000       0x3c ./Middlewares/Third_Party/LwIP/src/api/if_api.o
@@ -6131,8 +11660,16 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x1c4 ./Middlewares/Third_Party/LwIP/src/api/if_api.o
  .debug_macro   0x0000000000000000      0x22a ./Middlewares/Third_Party/LwIP/src/api/if_api.o
  .debug_macro   0x0000000000000000       0x35 ./Middlewares/Third_Party/LwIP/src/api/if_api.o
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+ .debug_macro   0x0000000000000000       0xa6 ./Middlewares/Third_Party/LwIP/src/api/if_api.o
  .debug_macro   0x0000000000000000      0x5e6 ./Middlewares/Third_Party/LwIP/src/api/if_api.o
- .debug_macro   0x0000000000000000       0xd0 ./Middlewares/Third_Party/LwIP/src/api/if_api.o
+ .debug_macro   0x0000000000000000       0x58 ./Middlewares/Third_Party/LwIP/src/api/if_api.o
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  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/api/if_api.o
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  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/api/if_api.o
@@ -6172,10 +11709,46 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x11f ./Middlewares/Third_Party/LwIP/src/api/if_api.o
  .debug_macro   0x0000000000000000       0x82 ./Middlewares/Third_Party/LwIP/src/api/if_api.o
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+ .debug_macro   0x0000000000000000       0x10 ./Middlewares/Third_Party/LwIP/src/api/if_api.o
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  .comment       0x0000000000000000       0x44 ./Middlewares/Third_Party/LwIP/src/api/if_api.o
+ .debug_frame   0x0000000000000000       0x60 ./Middlewares/Third_Party/LwIP/src/api/if_api.o
  .ARM.attributes
                 0x0000000000000000       0x32 ./Middlewares/Third_Party/LwIP/src/api/if_api.o
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@@ -6279,16 +11852,45 @@ Discarded input sections
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/api/netbuf.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/api/netbuf.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/api/netbuf.o
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- .debug_macro   0x0000000000000000      0x4a3 ./Middlewares/Third_Party/LwIP/src/api/netbuf.o
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+ .text.netbuf_alloc
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+ .text.netbuf_free
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+ .text.netbuf_ref
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+ .text.netbuf_chain
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+ .text.netbuf_first
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- .debug_macro   0x0000000000000000      0x232 ./Middlewares/Third_Party/LwIP/src/api/netbuf.o
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  .debug_macro   0x0000000000000000       0x22 ./Middlewares/Third_Party/LwIP/src/api/netbuf.o
@@ -6336,6 +11938,7 @@ Discarded input sections
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  .debug_macro   0x0000000000000000      0x275 ./Middlewares/Third_Party/LwIP/src/api/netbuf.o
+ .debug_macro   0x0000000000000000      0xe42 ./Middlewares/Third_Party/LwIP/src/api/netbuf.o
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@@ -6346,8 +11949,16 @@ Discarded input sections
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  .debug_macro   0x0000000000000000      0x22a ./Middlewares/Third_Party/LwIP/src/api/netbuf.o
  .debug_macro   0x0000000000000000       0x35 ./Middlewares/Third_Party/LwIP/src/api/netbuf.o
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@@ -6387,12 +11998,29 @@ Discarded input sections
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- .ARM.attributes
-                0x0000000000000000       0x32 ./Middlewares/Third_Party/LwIP/src/api/netbuf.o
+ .debug_macro   0x0000000000000000      0x739 ./Middlewares/Third_Party/LwIP/src/api/netbuf.o
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  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/api/netdb.o
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@@ -6501,9 +12129,9 @@ Discarded input sections
  .debug_abbrev  0x0000000000000000       0x28 ./Middlewares/Third_Party/LwIP/src/api/netdb.o
  .debug_aranges
                 0x0000000000000000       0x18 ./Middlewares/Third_Party/LwIP/src/api/netdb.o
- .debug_macro   0x0000000000000000      0x4ad ./Middlewares/Third_Party/LwIP/src/api/netdb.o
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  .debug_macro   0x0000000000000000      0xac6 ./Middlewares/Third_Party/LwIP/src/api/netdb.o
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  .debug_macro   0x0000000000000000       0x22 ./Middlewares/Third_Party/LwIP/src/api/netdb.o
@@ -6551,6 +12179,7 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x129 ./Middlewares/Third_Party/LwIP/src/api/netdb.o
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  .debug_macro   0x0000000000000000      0x275 ./Middlewares/Third_Party/LwIP/src/api/netdb.o
+ .debug_macro   0x0000000000000000      0xe42 ./Middlewares/Third_Party/LwIP/src/api/netdb.o
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@@ -6561,8 +12190,16 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x1c4 ./Middlewares/Third_Party/LwIP/src/api/netdb.o
  .debug_macro   0x0000000000000000      0x22a ./Middlewares/Third_Party/LwIP/src/api/netdb.o
  .debug_macro   0x0000000000000000       0x35 ./Middlewares/Third_Party/LwIP/src/api/netdb.o
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  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/api/netdb.o
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  .debug_macro   0x0000000000000000       0x82 ./Middlewares/Third_Party/LwIP/src/api/netdb.o
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  .ARM.attributes
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  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/api/netifapi.o
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  .debug_abbrev  0x0000000000000000       0x28 ./Middlewares/Third_Party/LwIP/src/api/netifapi.o
  .debug_aranges
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  .ARM.attributes
                 0x0000000000000000       0x32 ./Middlewares/Third_Party/LwIP/src/api/netifapi.o
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+ .bss.select_cb_list
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+ .text.lwip_socket_thread_cleanup
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+ .text.tryget_socket_unconn_nouse
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+ .text.lwip_socket_dbg_get_socket
                 0x0000000000000000       0x18 ./Middlewares/Third_Party/LwIP/src/api/sockets.o
- .debug_macro   0x0000000000000000      0x4a3 ./Middlewares/Third_Party/LwIP/src/api/sockets.o
+ .text.tryget_socket_unconn
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+ .text.tryget_socket_unconn_locked
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+ .text.tryget_socket
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+ .text.lwip_recv_tcp_from
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+ .text.lwip_recvfrom_udp_raw
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+ .text.lwip_readv
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+ .text.lwip_unlink_select_cb
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+ .text.lwip_select
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+ .debug_rnglists
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- .debug_macro   0x0000000000000000      0x232 ./Middlewares/Third_Party/LwIP/src/api/sockets.o
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@@ -6981,6 +12807,7 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x129 ./Middlewares/Third_Party/LwIP/src/api/sockets.o
  .debug_macro   0x0000000000000000      0x3f9 ./Middlewares/Third_Party/LwIP/src/api/sockets.o
  .debug_macro   0x0000000000000000      0x275 ./Middlewares/Third_Party/LwIP/src/api/sockets.o
+ .debug_macro   0x0000000000000000      0xe42 ./Middlewares/Third_Party/LwIP/src/api/sockets.o
  .debug_macro   0x0000000000000000      0x3ca ./Middlewares/Third_Party/LwIP/src/api/sockets.o
  .debug_macro   0x0000000000000000      0x45c ./Middlewares/Third_Party/LwIP/src/api/sockets.o
  .debug_macro   0x0000000000000000       0x3c ./Middlewares/Third_Party/LwIP/src/api/sockets.o
@@ -6991,8 +12818,16 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x1c4 ./Middlewares/Third_Party/LwIP/src/api/sockets.o
  .debug_macro   0x0000000000000000      0x22a ./Middlewares/Third_Party/LwIP/src/api/sockets.o
  .debug_macro   0x0000000000000000       0x35 ./Middlewares/Third_Party/LwIP/src/api/sockets.o
+ .debug_macro   0x0000000000000000      0x830 ./Middlewares/Third_Party/LwIP/src/api/sockets.o
+ .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/api/sockets.o
+ .debug_macro   0x0000000000000000      0x1ce ./Middlewares/Third_Party/LwIP/src/api/sockets.o
+ .debug_macro   0x0000000000000000      0xb1d ./Middlewares/Third_Party/LwIP/src/api/sockets.o
+ .debug_macro   0x0000000000000000      0x29f ./Middlewares/Third_Party/LwIP/src/api/sockets.o
+ .debug_macro   0x0000000000000000      0x693 ./Middlewares/Third_Party/LwIP/src/api/sockets.o
+ .debug_macro   0x0000000000000000       0xa6 ./Middlewares/Third_Party/LwIP/src/api/sockets.o
  .debug_macro   0x0000000000000000      0x5e6 ./Middlewares/Third_Party/LwIP/src/api/sockets.o
- .debug_macro   0x0000000000000000       0xd0 ./Middlewares/Third_Party/LwIP/src/api/sockets.o
+ .debug_macro   0x0000000000000000       0x58 ./Middlewares/Third_Party/LwIP/src/api/sockets.o
+ .debug_macro   0x0000000000000000       0xe8 ./Middlewares/Third_Party/LwIP/src/api/sockets.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/api/sockets.o
  .debug_macro   0x0000000000000000       0x10 ./Middlewares/Third_Party/LwIP/src/api/sockets.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/api/sockets.o
@@ -7032,10 +12867,59 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x11f ./Middlewares/Third_Party/LwIP/src/api/sockets.o
  .debug_macro   0x0000000000000000       0x82 ./Middlewares/Third_Party/LwIP/src/api/sockets.o
  .debug_macro   0x0000000000000000       0x66 ./Middlewares/Third_Party/LwIP/src/api/sockets.o
- .debug_macro   0x0000000000000000      0x756 ./Middlewares/Third_Party/LwIP/src/api/sockets.o
- .debug_line    0x0000000000000000      0xb77 ./Middlewares/Third_Party/LwIP/src/api/sockets.o
- .debug_str     0x0000000000000000   0x13e826 ./Middlewares/Third_Party/LwIP/src/api/sockets.o
+ .debug_macro   0x0000000000000000      0x739 ./Middlewares/Third_Party/LwIP/src/api/sockets.o
+ .debug_macro   0x0000000000000000       0x6a ./Middlewares/Third_Party/LwIP/src/api/sockets.o
+ .debug_macro   0x0000000000000000      0x1c3 ./Middlewares/Third_Party/LwIP/src/api/sockets.o
+ .debug_macro   0x0000000000000000      0x169 ./Middlewares/Third_Party/LwIP/src/api/sockets.o
+ .debug_macro   0x0000000000000000       0x10 ./Middlewares/Third_Party/LwIP/src/api/sockets.o
+ .debug_macro   0x0000000000000000       0xb3 ./Middlewares/Third_Party/LwIP/src/api/sockets.o
+ .debug_macro   0x0000000000000000       0x10 ./Middlewares/Third_Party/LwIP/src/api/sockets.o
+ .debug_macro   0x0000000000000000       0x10 ./Middlewares/Third_Party/LwIP/src/api/sockets.o
+ .debug_macro   0x0000000000000000       0x3f ./Middlewares/Third_Party/LwIP/src/api/sockets.o
+ .debug_macro   0x0000000000000000       0x25 ./Middlewares/Third_Party/LwIP/src/api/sockets.o
+ .debug_macro   0x0000000000000000       0x22 ./Middlewares/Third_Party/LwIP/src/api/sockets.o
+ .debug_macro   0x0000000000000000      0x15b ./Middlewares/Third_Party/LwIP/src/api/sockets.o
+ .debug_macro   0x0000000000000000      0x12f ./Middlewares/Third_Party/LwIP/src/api/sockets.o
+ .debug_macro   0x0000000000000000       0xf4 ./Middlewares/Third_Party/LwIP/src/api/sockets.o
+ .debug_macro   0x0000000000000000      0x320 ./Middlewares/Third_Party/LwIP/src/api/sockets.o
+ .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/api/sockets.o
+ .debug_macro   0x0000000000000000       0x20 ./Middlewares/Third_Party/LwIP/src/api/sockets.o
+ .debug_macro   0x0000000000000000      0x401 ./Middlewares/Third_Party/LwIP/src/api/sockets.o
+ .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/api/sockets.o
+ .debug_macro   0x0000000000000000      0x111 ./Middlewares/Third_Party/LwIP/src/api/sockets.o
+ .debug_macro   0x0000000000000000      0x15a ./Middlewares/Third_Party/LwIP/src/api/sockets.o
+ .debug_macro   0x0000000000000000       0xde ./Middlewares/Third_Party/LwIP/src/api/sockets.o
+ .debug_macro   0x0000000000000000       0x1c ./Middlewares/Third_Party/LwIP/src/api/sockets.o
+ .debug_macro   0x0000000000000000       0x26 ./Middlewares/Third_Party/LwIP/src/api/sockets.o
+ .debug_macro   0x0000000000000000      0x4ef ./Middlewares/Third_Party/LwIP/src/api/sockets.o
+ .debug_macro   0x0000000000000000       0xb5 ./Middlewares/Third_Party/LwIP/src/api/sockets.o
+ .debug_macro   0x0000000000000000       0xaa ./Middlewares/Third_Party/LwIP/src/api/sockets.o
+ .debug_macro   0x0000000000000000       0x91 ./Middlewares/Third_Party/LwIP/src/api/sockets.o
+ .debug_macro   0x0000000000000000       0x8d ./Middlewares/Third_Party/LwIP/src/api/sockets.o
+ .debug_macro   0x0000000000000000       0x7e ./Middlewares/Third_Party/LwIP/src/api/sockets.o
+ .debug_macro   0x0000000000000000       0x19 ./Middlewares/Third_Party/LwIP/src/api/sockets.o
+ .debug_macro   0x0000000000000000       0xf2 ./Middlewares/Third_Party/LwIP/src/api/sockets.o
+ .debug_macro   0x0000000000000000       0x10 ./Middlewares/Third_Party/LwIP/src/api/sockets.o
+ .debug_macro   0x0000000000000000       0x73 ./Middlewares/Third_Party/LwIP/src/api/sockets.o
+ .debug_macro   0x0000000000000000       0x24 ./Middlewares/Third_Party/LwIP/src/api/sockets.o
+ .debug_macro   0x0000000000000000       0x40 ./Middlewares/Third_Party/LwIP/src/api/sockets.o
+ .debug_macro   0x0000000000000000       0xda ./Middlewares/Third_Party/LwIP/src/api/sockets.o
+ .debug_macro   0x0000000000000000       0x2e ./Middlewares/Third_Party/LwIP/src/api/sockets.o
+ .debug_macro   0x0000000000000000       0xa0 ./Middlewares/Third_Party/LwIP/src/api/sockets.o
+ .debug_macro   0x0000000000000000       0x28 ./Middlewares/Third_Party/LwIP/src/api/sockets.o
+ .debug_macro   0x0000000000000000       0x2e ./Middlewares/Third_Party/LwIP/src/api/sockets.o
+ .debug_macro   0x0000000000000000       0xea ./Middlewares/Third_Party/LwIP/src/api/sockets.o
+ .debug_macro   0x0000000000000000       0x70 ./Middlewares/Third_Party/LwIP/src/api/sockets.o
+ .debug_macro   0x0000000000000000       0xf9 ./Middlewares/Third_Party/LwIP/src/api/sockets.o
+ .debug_macro   0x0000000000000000       0x10 ./Middlewares/Third_Party/LwIP/src/api/sockets.o
+ .debug_macro   0x0000000000000000       0x4d ./Middlewares/Third_Party/LwIP/src/api/sockets.o
+ .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/api/sockets.o
+ .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/api/sockets.o
+ .debug_macro   0x0000000000000000       0x4c ./Middlewares/Third_Party/LwIP/src/api/sockets.o
+ .debug_line    0x0000000000000000     0x2bf3 ./Middlewares/Third_Party/LwIP/src/api/sockets.o
+ .debug_str     0x0000000000000000   0x16cbc3 ./Middlewares/Third_Party/LwIP/src/api/sockets.o
  .comment       0x0000000000000000       0x44 ./Middlewares/Third_Party/LwIP/src/api/sockets.o
+ .debug_frame   0x0000000000000000      0x7e0 ./Middlewares/Third_Party/LwIP/src/api/sockets.o
  .ARM.attributes
                 0x0000000000000000       0x32 ./Middlewares/Third_Party/LwIP/src/api/sockets.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
@@ -7139,16 +13023,78 @@ Discarded input sections
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
  .text          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
  .data          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
  .bss           0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
- .debug_info    0x0000000000000000       0x85 ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
- .debug_abbrev  0x0000000000000000       0x28 ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
- .debug_aranges
+ .text.tcpip_callback
+                0x0000000000000000       0x6c ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
+ .text.tcpip_api_call
+                0x0000000000000000       0x30 ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
+ .text.tcpip_callbackmsg_new
+                0x0000000000000000       0x38 ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
+ .text.tcpip_callbackmsg_delete
                 0x0000000000000000       0x18 ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
- .debug_macro   0x0000000000000000      0x4a3 ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
+ .text.tcpip_callbackmsg_trycallback
+                0x0000000000000000       0x44 ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
+ .text.tcpip_callbackmsg_trycallback_fromisr
+                0x0000000000000000       0x44 ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
+ .text.pbuf_free_int
+                0x0000000000000000       0x1a ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
+ .text.pbuf_free_callback
+                0x0000000000000000       0x20 ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
+ .text.mem_free_callback
+                0x0000000000000000       0x20 ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
  .debug_macro   0x0000000000000000      0xac6 ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
- .debug_macro   0x0000000000000000      0x232 ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
+ .debug_macro   0x0000000000000000      0x24a ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
  .debug_macro   0x0000000000000000       0x2e ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
  .debug_macro   0x0000000000000000       0x3b ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
  .debug_macro   0x0000000000000000       0x22 ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
@@ -7196,6 +13142,7 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x129 ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
  .debug_macro   0x0000000000000000      0x3f9 ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
  .debug_macro   0x0000000000000000      0x275 ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
+ .debug_macro   0x0000000000000000      0xe42 ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
  .debug_macro   0x0000000000000000      0x3ca ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
  .debug_macro   0x0000000000000000      0x45c ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
  .debug_macro   0x0000000000000000       0x3c ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
@@ -7206,8 +13153,16 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x1c4 ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
  .debug_macro   0x0000000000000000      0x22a ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
  .debug_macro   0x0000000000000000       0x35 ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
+ .debug_macro   0x0000000000000000      0x830 ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
+ .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
+ .debug_macro   0x0000000000000000      0x1ce ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
+ .debug_macro   0x0000000000000000      0xb1d ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
+ .debug_macro   0x0000000000000000      0x29f ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
+ .debug_macro   0x0000000000000000      0x693 ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
+ .debug_macro   0x0000000000000000       0xa6 ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
  .debug_macro   0x0000000000000000      0x5e6 ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
- .debug_macro   0x0000000000000000       0xd0 ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
+ .debug_macro   0x0000000000000000       0x58 ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
+ .debug_macro   0x0000000000000000       0xe8 ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
  .debug_macro   0x0000000000000000       0x10 ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
@@ -7247,12 +13202,72 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x11f ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
  .debug_macro   0x0000000000000000       0x82 ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
  .debug_macro   0x0000000000000000       0x66 ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
- .debug_macro   0x0000000000000000      0x756 ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
- .debug_line    0x0000000000000000      0xb75 ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
- .debug_str     0x0000000000000000   0x13e824 ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
- .comment       0x0000000000000000       0x44 ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
- .ARM.attributes
-                0x0000000000000000       0x32 ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
+ .debug_macro   0x0000000000000000      0x739 ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
+ .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
+ .debug_macro   0x0000000000000000      0x111 ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
+ .debug_macro   0x0000000000000000      0x15a ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
+ .debug_macro   0x0000000000000000       0xde ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
+ .debug_macro   0x0000000000000000       0x1c ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
+ .debug_macro   0x0000000000000000       0x26 ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
+ .debug_macro   0x0000000000000000      0x4ef ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
+ .debug_macro   0x0000000000000000       0xb5 ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
+ .debug_macro   0x0000000000000000       0xaa ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
+ .debug_macro   0x0000000000000000       0x91 ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
+ .debug_macro   0x0000000000000000       0x8d ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
+ .debug_macro   0x0000000000000000       0x7e ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
+ .debug_macro   0x0000000000000000       0x19 ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
+ .debug_macro   0x0000000000000000       0xf2 ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
+ .debug_macro   0x0000000000000000       0x10 ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
+ .debug_macro   0x0000000000000000       0x73 ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
+ .debug_macro   0x0000000000000000       0x10 ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
+ .debug_macro   0x0000000000000000       0x10 ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
+ .debug_macro   0x0000000000000000       0x6a ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
+ .debug_macro   0x0000000000000000      0x1c3 ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
+ .debug_macro   0x0000000000000000      0x169 ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
+ .debug_macro   0x0000000000000000       0xb3 ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
+ .debug_macro   0x0000000000000000       0x10 ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
+ .debug_macro   0x0000000000000000       0x10 ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
+ .debug_macro   0x0000000000000000       0x3f ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
+ .debug_macro   0x0000000000000000       0x25 ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
+ .debug_macro   0x0000000000000000       0x22 ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
+ .debug_macro   0x0000000000000000      0x15b ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
+ .debug_macro   0x0000000000000000      0x12f ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
+ .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
+ .debug_macro   0x0000000000000000       0x4c ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
+ .debug_macro   0x0000000000000000       0x5e ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
+ .debug_macro   0x0000000000000000       0xa0 ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
+ .debug_macro   0x0000000000000000       0x28 ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
+ .debug_macro   0x0000000000000000       0x2e ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
+ .debug_macro   0x0000000000000000       0xea ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
+ .debug_macro   0x0000000000000000       0x46 ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
+ .debug_macro   0x0000000000000000       0x22 ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
+ .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
+ .debug_macro   0x0000000000000000       0x10 ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.o
@@ -7463,15 +13478,15 @@ Discarded input sections
                 0x0000000000000000       0x48 ./Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.o
  .text.mqtt_client_is_connected
                 0x0000000000000000       0x40 ./Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.o
- .debug_info    0x0000000000000000     0x1ca6 ./Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.o
+ .debug_info    0x0000000000000000     0x1cbe ./Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.o
  .debug_abbrev  0x0000000000000000      0x38c ./Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.o
  .debug_aranges
                 0x0000000000000000      0x150 ./Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.o
  .debug_rnglists
                 0x0000000000000000      0x130 ./Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.o
- .debug_macro   0x0000000000000000      0x67c ./Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.o
+ .debug_macro   0x0000000000000000      0x7c9 ./Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.o
  .debug_macro   0x0000000000000000      0xac6 ./Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.o
- .debug_macro   0x0000000000000000      0x232 ./Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.o
+ .debug_macro   0x0000000000000000      0x24a ./Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.o
  .debug_macro   0x0000000000000000       0x2e ./Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.o
  .debug_macro   0x0000000000000000       0x3b ./Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.o
  .debug_macro   0x0000000000000000       0x22 ./Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.o
@@ -7519,6 +13534,7 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x129 ./Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.o
  .debug_macro   0x0000000000000000      0x3f9 ./Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.o
  .debug_macro   0x0000000000000000      0x275 ./Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.o
+ .debug_macro   0x0000000000000000      0xe42 ./Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.o
  .debug_macro   0x0000000000000000      0x3ca ./Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.o
  .debug_macro   0x0000000000000000      0x45c ./Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.o
  .debug_macro   0x0000000000000000       0x3c ./Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.o
@@ -7529,8 +13545,16 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x1c4 ./Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.o
  .debug_macro   0x0000000000000000      0x22a ./Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.o
  .debug_macro   0x0000000000000000       0x35 ./Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.o
+ .debug_macro   0x0000000000000000      0x830 ./Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.o
+ .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.o
+ .debug_macro   0x0000000000000000      0x1ce ./Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.o
+ .debug_macro   0x0000000000000000      0xb1d ./Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.o
+ .debug_macro   0x0000000000000000      0x29f ./Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.o
+ .debug_macro   0x0000000000000000      0x693 ./Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.o
+ .debug_macro   0x0000000000000000       0xa6 ./Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.o
  .debug_macro   0x0000000000000000      0x5e6 ./Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.o
- .debug_macro   0x0000000000000000       0xd0 ./Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.o
+ .debug_macro   0x0000000000000000       0x58 ./Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.o
+ .debug_macro   0x0000000000000000       0xe8 ./Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.o
  .debug_macro   0x0000000000000000       0x10 ./Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.o
@@ -7570,7 +13594,7 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x11f ./Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.o
  .debug_macro   0x0000000000000000       0x82 ./Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.o
  .debug_macro   0x0000000000000000       0x66 ./Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.o
- .debug_macro   0x0000000000000000      0x756 ./Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.o
+ .debug_macro   0x0000000000000000      0x739 ./Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.o
  .debug_macro   0x0000000000000000       0x28 ./Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.o
  .debug_macro   0x0000000000000000       0x6a ./Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.o
  .debug_macro   0x0000000000000000      0x1c3 ./Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.o
@@ -7594,10 +13618,26 @@ Discarded input sections
  .debug_macro   0x0000000000000000       0xf9 ./Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.o
  .debug_macro   0x0000000000000000      0x11c ./Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.o
+ .debug_macro   0x0000000000000000      0x111 ./Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.o
+ .debug_macro   0x0000000000000000      0x15a ./Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.o
+ .debug_macro   0x0000000000000000       0xde ./Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.o
+ .debug_macro   0x0000000000000000       0x1c ./Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.o
+ .debug_macro   0x0000000000000000       0x26 ./Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.o
+ .debug_macro   0x0000000000000000      0x4ef ./Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.o
+ .debug_macro   0x0000000000000000       0xb5 ./Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.o
+ .debug_macro   0x0000000000000000       0xaa ./Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.o
+ .debug_macro   0x0000000000000000       0x91 ./Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.o
+ .debug_macro   0x0000000000000000       0x8d ./Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.o
+ .debug_macro   0x0000000000000000       0x7e ./Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.o
+ .debug_macro   0x0000000000000000       0x19 ./Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.o
+ .debug_macro   0x0000000000000000       0xf2 ./Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.o
+ .debug_macro   0x0000000000000000       0x10 ./Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.o
+ .debug_macro   0x0000000000000000       0x73 ./Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.o
+ .debug_macro   0x0000000000000000       0x10 ./Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.o
  .debug_macro   0x0000000000000000       0x20 ./Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.o
- .debug_line    0x0000000000000000     0x1c4c ./Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.o
- .debug_str     0x0000000000000000   0x144a1c ./Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.o
+ .debug_line    0x0000000000000000     0x1ec0 ./Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.o
+ .debug_str     0x0000000000000000   0x1697e2 ./Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.o
  .comment       0x0000000000000000       0x44 ./Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.o
  .debug_frame   0x0000000000000000      0x5b8 ./Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.o
  .ARM.attributes
@@ -7703,6 +13743,15 @@ Discarded input sections
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/altcp.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/altcp.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/altcp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/altcp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/altcp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/altcp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/altcp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/altcp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/altcp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/altcp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/altcp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/altcp.o
  .text          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/core/altcp.o
  .data          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/core/altcp.o
  .bss           0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/core/altcp.o
@@ -7710,9 +13759,9 @@ Discarded input sections
  .debug_abbrev  0x0000000000000000       0x28 ./Middlewares/Third_Party/LwIP/src/core/altcp.o
  .debug_aranges
                 0x0000000000000000       0x18 ./Middlewares/Third_Party/LwIP/src/core/altcp.o
- .debug_macro   0x0000000000000000      0x4a3 ./Middlewares/Third_Party/LwIP/src/core/altcp.o
+ .debug_macro   0x0000000000000000      0x507 ./Middlewares/Third_Party/LwIP/src/core/altcp.o
  .debug_macro   0x0000000000000000      0xac6 ./Middlewares/Third_Party/LwIP/src/core/altcp.o
- .debug_macro   0x0000000000000000      0x232 ./Middlewares/Third_Party/LwIP/src/core/altcp.o
+ .debug_macro   0x0000000000000000      0x24a ./Middlewares/Third_Party/LwIP/src/core/altcp.o
  .debug_macro   0x0000000000000000       0x2e ./Middlewares/Third_Party/LwIP/src/core/altcp.o
  .debug_macro   0x0000000000000000       0x3b ./Middlewares/Third_Party/LwIP/src/core/altcp.o
  .debug_macro   0x0000000000000000       0x22 ./Middlewares/Third_Party/LwIP/src/core/altcp.o
@@ -7760,6 +13809,7 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x129 ./Middlewares/Third_Party/LwIP/src/core/altcp.o
  .debug_macro   0x0000000000000000      0x3f9 ./Middlewares/Third_Party/LwIP/src/core/altcp.o
  .debug_macro   0x0000000000000000      0x275 ./Middlewares/Third_Party/LwIP/src/core/altcp.o
+ .debug_macro   0x0000000000000000      0xe42 ./Middlewares/Third_Party/LwIP/src/core/altcp.o
  .debug_macro   0x0000000000000000      0x3ca ./Middlewares/Third_Party/LwIP/src/core/altcp.o
  .debug_macro   0x0000000000000000      0x45c ./Middlewares/Third_Party/LwIP/src/core/altcp.o
  .debug_macro   0x0000000000000000       0x3c ./Middlewares/Third_Party/LwIP/src/core/altcp.o
@@ -7770,8 +13820,16 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x1c4 ./Middlewares/Third_Party/LwIP/src/core/altcp.o
  .debug_macro   0x0000000000000000      0x22a ./Middlewares/Third_Party/LwIP/src/core/altcp.o
  .debug_macro   0x0000000000000000       0x35 ./Middlewares/Third_Party/LwIP/src/core/altcp.o
+ .debug_macro   0x0000000000000000      0x830 ./Middlewares/Third_Party/LwIP/src/core/altcp.o
+ .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/core/altcp.o
+ .debug_macro   0x0000000000000000      0x1ce ./Middlewares/Third_Party/LwIP/src/core/altcp.o
+ .debug_macro   0x0000000000000000      0xb1d ./Middlewares/Third_Party/LwIP/src/core/altcp.o
+ .debug_macro   0x0000000000000000      0x29f ./Middlewares/Third_Party/LwIP/src/core/altcp.o
+ .debug_macro   0x0000000000000000      0x693 ./Middlewares/Third_Party/LwIP/src/core/altcp.o
+ .debug_macro   0x0000000000000000       0xa6 ./Middlewares/Third_Party/LwIP/src/core/altcp.o
  .debug_macro   0x0000000000000000      0x5e6 ./Middlewares/Third_Party/LwIP/src/core/altcp.o
- .debug_macro   0x0000000000000000       0xd0 ./Middlewares/Third_Party/LwIP/src/core/altcp.o
+ .debug_macro   0x0000000000000000       0x58 ./Middlewares/Third_Party/LwIP/src/core/altcp.o
+ .debug_macro   0x0000000000000000       0xe8 ./Middlewares/Third_Party/LwIP/src/core/altcp.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/core/altcp.o
  .debug_macro   0x0000000000000000       0x10 ./Middlewares/Third_Party/LwIP/src/core/altcp.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/core/altcp.o
@@ -7811,9 +13869,9 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x11f ./Middlewares/Third_Party/LwIP/src/core/altcp.o
  .debug_macro   0x0000000000000000       0x82 ./Middlewares/Third_Party/LwIP/src/core/altcp.o
  .debug_macro   0x0000000000000000       0x66 ./Middlewares/Third_Party/LwIP/src/core/altcp.o
- .debug_macro   0x0000000000000000      0x756 ./Middlewares/Third_Party/LwIP/src/core/altcp.o
- .debug_line    0x0000000000000000      0xb76 ./Middlewares/Third_Party/LwIP/src/core/altcp.o
- .debug_str     0x0000000000000000   0x13e825 ./Middlewares/Third_Party/LwIP/src/core/altcp.o
+ .debug_macro   0x0000000000000000      0x739 ./Middlewares/Third_Party/LwIP/src/core/altcp.o
+ .debug_line    0x0000000000000000      0xc57 ./Middlewares/Third_Party/LwIP/src/core/altcp.o
+ .debug_str     0x0000000000000000   0x15d099 ./Middlewares/Third_Party/LwIP/src/core/altcp.o
  .comment       0x0000000000000000       0x44 ./Middlewares/Third_Party/LwIP/src/core/altcp.o
  .ARM.attributes
                 0x0000000000000000       0x32 ./Middlewares/Third_Party/LwIP/src/core/altcp.o
@@ -7918,6 +13976,15 @@ Discarded input sections
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/altcp_alloc.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/altcp_alloc.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/altcp_alloc.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/altcp_alloc.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/altcp_alloc.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/altcp_alloc.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/altcp_alloc.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/altcp_alloc.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/altcp_alloc.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/altcp_alloc.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/altcp_alloc.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/altcp_alloc.o
  .text          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/core/altcp_alloc.o
  .data          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/core/altcp_alloc.o
  .bss           0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/core/altcp_alloc.o
@@ -7925,9 +13992,9 @@ Discarded input sections
  .debug_abbrev  0x0000000000000000       0x28 ./Middlewares/Third_Party/LwIP/src/core/altcp_alloc.o
  .debug_aranges
                 0x0000000000000000       0x18 ./Middlewares/Third_Party/LwIP/src/core/altcp_alloc.o
- .debug_macro   0x0000000000000000      0x4a3 ./Middlewares/Third_Party/LwIP/src/core/altcp_alloc.o
+ .debug_macro   0x0000000000000000      0x507 ./Middlewares/Third_Party/LwIP/src/core/altcp_alloc.o
  .debug_macro   0x0000000000000000      0xac6 ./Middlewares/Third_Party/LwIP/src/core/altcp_alloc.o
- .debug_macro   0x0000000000000000      0x232 ./Middlewares/Third_Party/LwIP/src/core/altcp_alloc.o
+ .debug_macro   0x0000000000000000      0x24a ./Middlewares/Third_Party/LwIP/src/core/altcp_alloc.o
  .debug_macro   0x0000000000000000       0x2e ./Middlewares/Third_Party/LwIP/src/core/altcp_alloc.o
  .debug_macro   0x0000000000000000       0x3b ./Middlewares/Third_Party/LwIP/src/core/altcp_alloc.o
  .debug_macro   0x0000000000000000       0x22 ./Middlewares/Third_Party/LwIP/src/core/altcp_alloc.o
@@ -7975,6 +14042,7 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x129 ./Middlewares/Third_Party/LwIP/src/core/altcp_alloc.o
  .debug_macro   0x0000000000000000      0x3f9 ./Middlewares/Third_Party/LwIP/src/core/altcp_alloc.o
  .debug_macro   0x0000000000000000      0x275 ./Middlewares/Third_Party/LwIP/src/core/altcp_alloc.o
+ .debug_macro   0x0000000000000000      0xe42 ./Middlewares/Third_Party/LwIP/src/core/altcp_alloc.o
  .debug_macro   0x0000000000000000      0x3ca ./Middlewares/Third_Party/LwIP/src/core/altcp_alloc.o
  .debug_macro   0x0000000000000000      0x45c ./Middlewares/Third_Party/LwIP/src/core/altcp_alloc.o
  .debug_macro   0x0000000000000000       0x3c ./Middlewares/Third_Party/LwIP/src/core/altcp_alloc.o
@@ -7985,8 +14053,16 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x1c4 ./Middlewares/Third_Party/LwIP/src/core/altcp_alloc.o
  .debug_macro   0x0000000000000000      0x22a ./Middlewares/Third_Party/LwIP/src/core/altcp_alloc.o
  .debug_macro   0x0000000000000000       0x35 ./Middlewares/Third_Party/LwIP/src/core/altcp_alloc.o
+ .debug_macro   0x0000000000000000      0x830 ./Middlewares/Third_Party/LwIP/src/core/altcp_alloc.o
+ .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/core/altcp_alloc.o
+ .debug_macro   0x0000000000000000      0x1ce ./Middlewares/Third_Party/LwIP/src/core/altcp_alloc.o
+ .debug_macro   0x0000000000000000      0xb1d ./Middlewares/Third_Party/LwIP/src/core/altcp_alloc.o
+ .debug_macro   0x0000000000000000      0x29f ./Middlewares/Third_Party/LwIP/src/core/altcp_alloc.o
+ .debug_macro   0x0000000000000000      0x693 ./Middlewares/Third_Party/LwIP/src/core/altcp_alloc.o
+ .debug_macro   0x0000000000000000       0xa6 ./Middlewares/Third_Party/LwIP/src/core/altcp_alloc.o
  .debug_macro   0x0000000000000000      0x5e6 ./Middlewares/Third_Party/LwIP/src/core/altcp_alloc.o
- .debug_macro   0x0000000000000000       0xd0 ./Middlewares/Third_Party/LwIP/src/core/altcp_alloc.o
+ .debug_macro   0x0000000000000000       0x58 ./Middlewares/Third_Party/LwIP/src/core/altcp_alloc.o
+ .debug_macro   0x0000000000000000       0xe8 ./Middlewares/Third_Party/LwIP/src/core/altcp_alloc.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/core/altcp_alloc.o
  .debug_macro   0x0000000000000000       0x10 ./Middlewares/Third_Party/LwIP/src/core/altcp_alloc.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/core/altcp_alloc.o
@@ -8026,9 +14102,9 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x11f ./Middlewares/Third_Party/LwIP/src/core/altcp_alloc.o
  .debug_macro   0x0000000000000000       0x82 ./Middlewares/Third_Party/LwIP/src/core/altcp_alloc.o
  .debug_macro   0x0000000000000000       0x66 ./Middlewares/Third_Party/LwIP/src/core/altcp_alloc.o
- .debug_macro   0x0000000000000000      0x756 ./Middlewares/Third_Party/LwIP/src/core/altcp_alloc.o
- .debug_line    0x0000000000000000      0xb7c ./Middlewares/Third_Party/LwIP/src/core/altcp_alloc.o
- .debug_str     0x0000000000000000   0x13e82b ./Middlewares/Third_Party/LwIP/src/core/altcp_alloc.o
+ .debug_macro   0x0000000000000000      0x739 ./Middlewares/Third_Party/LwIP/src/core/altcp_alloc.o
+ .debug_line    0x0000000000000000      0xc5d ./Middlewares/Third_Party/LwIP/src/core/altcp_alloc.o
+ .debug_str     0x0000000000000000   0x15d09f ./Middlewares/Third_Party/LwIP/src/core/altcp_alloc.o
  .comment       0x0000000000000000       0x44 ./Middlewares/Third_Party/LwIP/src/core/altcp_alloc.o
  .ARM.attributes
                 0x0000000000000000       0x32 ./Middlewares/Third_Party/LwIP/src/core/altcp_alloc.o
@@ -8133,6 +14209,15 @@ Discarded input sections
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/altcp_tcp.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/altcp_tcp.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/altcp_tcp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/altcp_tcp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/altcp_tcp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/altcp_tcp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/altcp_tcp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/altcp_tcp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/altcp_tcp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/altcp_tcp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/altcp_tcp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/altcp_tcp.o
  .text          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/core/altcp_tcp.o
  .data          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/core/altcp_tcp.o
  .bss           0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/core/altcp_tcp.o
@@ -8140,9 +14225,9 @@ Discarded input sections
  .debug_abbrev  0x0000000000000000       0x28 ./Middlewares/Third_Party/LwIP/src/core/altcp_tcp.o
  .debug_aranges
                 0x0000000000000000       0x18 ./Middlewares/Third_Party/LwIP/src/core/altcp_tcp.o
- .debug_macro   0x0000000000000000      0x4a3 ./Middlewares/Third_Party/LwIP/src/core/altcp_tcp.o
+ .debug_macro   0x0000000000000000      0x507 ./Middlewares/Third_Party/LwIP/src/core/altcp_tcp.o
  .debug_macro   0x0000000000000000      0xac6 ./Middlewares/Third_Party/LwIP/src/core/altcp_tcp.o
- .debug_macro   0x0000000000000000      0x232 ./Middlewares/Third_Party/LwIP/src/core/altcp_tcp.o
+ .debug_macro   0x0000000000000000      0x24a ./Middlewares/Third_Party/LwIP/src/core/altcp_tcp.o
  .debug_macro   0x0000000000000000       0x2e ./Middlewares/Third_Party/LwIP/src/core/altcp_tcp.o
  .debug_macro   0x0000000000000000       0x3b ./Middlewares/Third_Party/LwIP/src/core/altcp_tcp.o
  .debug_macro   0x0000000000000000       0x22 ./Middlewares/Third_Party/LwIP/src/core/altcp_tcp.o
@@ -8190,6 +14275,7 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x129 ./Middlewares/Third_Party/LwIP/src/core/altcp_tcp.o
  .debug_macro   0x0000000000000000      0x3f9 ./Middlewares/Third_Party/LwIP/src/core/altcp_tcp.o
  .debug_macro   0x0000000000000000      0x275 ./Middlewares/Third_Party/LwIP/src/core/altcp_tcp.o
+ .debug_macro   0x0000000000000000      0xe42 ./Middlewares/Third_Party/LwIP/src/core/altcp_tcp.o
  .debug_macro   0x0000000000000000      0x3ca ./Middlewares/Third_Party/LwIP/src/core/altcp_tcp.o
  .debug_macro   0x0000000000000000      0x45c ./Middlewares/Third_Party/LwIP/src/core/altcp_tcp.o
  .debug_macro   0x0000000000000000       0x3c ./Middlewares/Third_Party/LwIP/src/core/altcp_tcp.o
@@ -8200,8 +14286,16 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x1c4 ./Middlewares/Third_Party/LwIP/src/core/altcp_tcp.o
  .debug_macro   0x0000000000000000      0x22a ./Middlewares/Third_Party/LwIP/src/core/altcp_tcp.o
  .debug_macro   0x0000000000000000       0x35 ./Middlewares/Third_Party/LwIP/src/core/altcp_tcp.o
+ .debug_macro   0x0000000000000000      0x830 ./Middlewares/Third_Party/LwIP/src/core/altcp_tcp.o
+ .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/core/altcp_tcp.o
+ .debug_macro   0x0000000000000000      0x1ce ./Middlewares/Third_Party/LwIP/src/core/altcp_tcp.o
+ .debug_macro   0x0000000000000000      0xb1d ./Middlewares/Third_Party/LwIP/src/core/altcp_tcp.o
+ .debug_macro   0x0000000000000000      0x29f ./Middlewares/Third_Party/LwIP/src/core/altcp_tcp.o
+ .debug_macro   0x0000000000000000      0x693 ./Middlewares/Third_Party/LwIP/src/core/altcp_tcp.o
+ .debug_macro   0x0000000000000000       0xa6 ./Middlewares/Third_Party/LwIP/src/core/altcp_tcp.o
  .debug_macro   0x0000000000000000      0x5e6 ./Middlewares/Third_Party/LwIP/src/core/altcp_tcp.o
- .debug_macro   0x0000000000000000       0xd0 ./Middlewares/Third_Party/LwIP/src/core/altcp_tcp.o
+ .debug_macro   0x0000000000000000       0x58 ./Middlewares/Third_Party/LwIP/src/core/altcp_tcp.o
+ .debug_macro   0x0000000000000000       0xe8 ./Middlewares/Third_Party/LwIP/src/core/altcp_tcp.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/core/altcp_tcp.o
  .debug_macro   0x0000000000000000       0x10 ./Middlewares/Third_Party/LwIP/src/core/altcp_tcp.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/core/altcp_tcp.o
@@ -8241,9 +14335,9 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x11f ./Middlewares/Third_Party/LwIP/src/core/altcp_tcp.o
  .debug_macro   0x0000000000000000       0x82 ./Middlewares/Third_Party/LwIP/src/core/altcp_tcp.o
  .debug_macro   0x0000000000000000       0x66 ./Middlewares/Third_Party/LwIP/src/core/altcp_tcp.o
- .debug_macro   0x0000000000000000      0x756 ./Middlewares/Third_Party/LwIP/src/core/altcp_tcp.o
- .debug_line    0x0000000000000000      0xb7a ./Middlewares/Third_Party/LwIP/src/core/altcp_tcp.o
- .debug_str     0x0000000000000000   0x13e829 ./Middlewares/Third_Party/LwIP/src/core/altcp_tcp.o
+ .debug_macro   0x0000000000000000      0x739 ./Middlewares/Third_Party/LwIP/src/core/altcp_tcp.o
+ .debug_line    0x0000000000000000      0xc5b ./Middlewares/Third_Party/LwIP/src/core/altcp_tcp.o
+ .debug_str     0x0000000000000000   0x15d09d ./Middlewares/Third_Party/LwIP/src/core/altcp_tcp.o
  .comment       0x0000000000000000       0x44 ./Middlewares/Third_Party/LwIP/src/core/altcp_tcp.o
  .ARM.attributes
                 0x0000000000000000       0x32 ./Middlewares/Third_Party/LwIP/src/core/altcp_tcp.o
@@ -8351,6 +14445,15 @@ Discarded input sections
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/def.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/def.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/def.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/def.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/def.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/def.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/def.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/def.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/def.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/def.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/def.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/def.o
  .text          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/core/def.o
  .data          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/core/def.o
  .bss           0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/core/def.o
@@ -8363,7 +14466,7 @@ Discarded input sections
  .text.lwip_itoa
                 0x0000000000000000       0xe8 ./Middlewares/Third_Party/LwIP/src/core/def.o
  .debug_macro   0x0000000000000000      0xac6 ./Middlewares/Third_Party/LwIP/src/core/def.o
- .debug_macro   0x0000000000000000      0x232 ./Middlewares/Third_Party/LwIP/src/core/def.o
+ .debug_macro   0x0000000000000000      0x24a ./Middlewares/Third_Party/LwIP/src/core/def.o
  .debug_macro   0x0000000000000000       0x2e ./Middlewares/Third_Party/LwIP/src/core/def.o
  .debug_macro   0x0000000000000000       0x3b ./Middlewares/Third_Party/LwIP/src/core/def.o
  .debug_macro   0x0000000000000000       0x22 ./Middlewares/Third_Party/LwIP/src/core/def.o
@@ -8411,6 +14514,7 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x129 ./Middlewares/Third_Party/LwIP/src/core/def.o
  .debug_macro   0x0000000000000000      0x3f9 ./Middlewares/Third_Party/LwIP/src/core/def.o
  .debug_macro   0x0000000000000000      0x275 ./Middlewares/Third_Party/LwIP/src/core/def.o
+ .debug_macro   0x0000000000000000      0xe42 ./Middlewares/Third_Party/LwIP/src/core/def.o
  .debug_macro   0x0000000000000000      0x3ca ./Middlewares/Third_Party/LwIP/src/core/def.o
  .debug_macro   0x0000000000000000      0x45c ./Middlewares/Third_Party/LwIP/src/core/def.o
  .debug_macro   0x0000000000000000       0x3c ./Middlewares/Third_Party/LwIP/src/core/def.o
@@ -8421,8 +14525,16 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x1c4 ./Middlewares/Third_Party/LwIP/src/core/def.o
  .debug_macro   0x0000000000000000      0x22a ./Middlewares/Third_Party/LwIP/src/core/def.o
  .debug_macro   0x0000000000000000       0x35 ./Middlewares/Third_Party/LwIP/src/core/def.o
+ .debug_macro   0x0000000000000000      0x830 ./Middlewares/Third_Party/LwIP/src/core/def.o
+ .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/core/def.o
+ .debug_macro   0x0000000000000000      0x1ce ./Middlewares/Third_Party/LwIP/src/core/def.o
+ .debug_macro   0x0000000000000000      0xb1d ./Middlewares/Third_Party/LwIP/src/core/def.o
+ .debug_macro   0x0000000000000000      0x29f ./Middlewares/Third_Party/LwIP/src/core/def.o
+ .debug_macro   0x0000000000000000      0x693 ./Middlewares/Third_Party/LwIP/src/core/def.o
+ .debug_macro   0x0000000000000000       0xa6 ./Middlewares/Third_Party/LwIP/src/core/def.o
  .debug_macro   0x0000000000000000      0x5e6 ./Middlewares/Third_Party/LwIP/src/core/def.o
- .debug_macro   0x0000000000000000       0xd0 ./Middlewares/Third_Party/LwIP/src/core/def.o
+ .debug_macro   0x0000000000000000       0x58 ./Middlewares/Third_Party/LwIP/src/core/def.o
+ .debug_macro   0x0000000000000000       0xe8 ./Middlewares/Third_Party/LwIP/src/core/def.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/core/def.o
  .debug_macro   0x0000000000000000       0x10 ./Middlewares/Third_Party/LwIP/src/core/def.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/core/def.o
@@ -8462,7 +14574,7 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x11f ./Middlewares/Third_Party/LwIP/src/core/def.o
  .debug_macro   0x0000000000000000       0x82 ./Middlewares/Third_Party/LwIP/src/core/def.o
  .debug_macro   0x0000000000000000       0x66 ./Middlewares/Third_Party/LwIP/src/core/def.o
- .debug_macro   0x0000000000000000      0x756 ./Middlewares/Third_Party/LwIP/src/core/def.o
+ .debug_macro   0x0000000000000000      0x739 ./Middlewares/Third_Party/LwIP/src/core/def.o
  .debug_macro   0x0000000000000000       0x6a ./Middlewares/Third_Party/LwIP/src/core/def.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/core/def.o
  .debug_macro   0x0000000000000000       0x20 ./Middlewares/Third_Party/LwIP/src/core/def.o
@@ -8567,6 +14679,15 @@ Discarded input sections
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/dns.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/dns.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/dns.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/dns.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/dns.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/dns.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/dns.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/dns.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/dns.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/dns.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/dns.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/dns.o
  .text          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/core/dns.o
  .data          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/core/dns.o
  .bss           0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/core/dns.o
@@ -8574,9 +14695,9 @@ Discarded input sections
  .debug_abbrev  0x0000000000000000       0x28 ./Middlewares/Third_Party/LwIP/src/core/dns.o
  .debug_aranges
                 0x0000000000000000       0x18 ./Middlewares/Third_Party/LwIP/src/core/dns.o
- .debug_macro   0x0000000000000000      0x4a3 ./Middlewares/Third_Party/LwIP/src/core/dns.o
+ .debug_macro   0x0000000000000000      0x507 ./Middlewares/Third_Party/LwIP/src/core/dns.o
  .debug_macro   0x0000000000000000      0xac6 ./Middlewares/Third_Party/LwIP/src/core/dns.o
- .debug_macro   0x0000000000000000      0x232 ./Middlewares/Third_Party/LwIP/src/core/dns.o
+ .debug_macro   0x0000000000000000      0x24a ./Middlewares/Third_Party/LwIP/src/core/dns.o
  .debug_macro   0x0000000000000000       0x2e ./Middlewares/Third_Party/LwIP/src/core/dns.o
  .debug_macro   0x0000000000000000       0x3b ./Middlewares/Third_Party/LwIP/src/core/dns.o
  .debug_macro   0x0000000000000000       0x22 ./Middlewares/Third_Party/LwIP/src/core/dns.o
@@ -8624,6 +14745,7 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x129 ./Middlewares/Third_Party/LwIP/src/core/dns.o
  .debug_macro   0x0000000000000000      0x3f9 ./Middlewares/Third_Party/LwIP/src/core/dns.o
  .debug_macro   0x0000000000000000      0x275 ./Middlewares/Third_Party/LwIP/src/core/dns.o
+ .debug_macro   0x0000000000000000      0xe42 ./Middlewares/Third_Party/LwIP/src/core/dns.o
  .debug_macro   0x0000000000000000      0x3ca ./Middlewares/Third_Party/LwIP/src/core/dns.o
  .debug_macro   0x0000000000000000      0x45c ./Middlewares/Third_Party/LwIP/src/core/dns.o
  .debug_macro   0x0000000000000000       0x3c ./Middlewares/Third_Party/LwIP/src/core/dns.o
@@ -8634,8 +14756,16 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x1c4 ./Middlewares/Third_Party/LwIP/src/core/dns.o
  .debug_macro   0x0000000000000000      0x22a ./Middlewares/Third_Party/LwIP/src/core/dns.o
  .debug_macro   0x0000000000000000       0x35 ./Middlewares/Third_Party/LwIP/src/core/dns.o
+ .debug_macro   0x0000000000000000      0x830 ./Middlewares/Third_Party/LwIP/src/core/dns.o
+ .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/core/dns.o
+ .debug_macro   0x0000000000000000      0x1ce ./Middlewares/Third_Party/LwIP/src/core/dns.o
+ .debug_macro   0x0000000000000000      0xb1d ./Middlewares/Third_Party/LwIP/src/core/dns.o
+ .debug_macro   0x0000000000000000      0x29f ./Middlewares/Third_Party/LwIP/src/core/dns.o
+ .debug_macro   0x0000000000000000      0x693 ./Middlewares/Third_Party/LwIP/src/core/dns.o
+ .debug_macro   0x0000000000000000       0xa6 ./Middlewares/Third_Party/LwIP/src/core/dns.o
  .debug_macro   0x0000000000000000      0x5e6 ./Middlewares/Third_Party/LwIP/src/core/dns.o
- .debug_macro   0x0000000000000000       0xd0 ./Middlewares/Third_Party/LwIP/src/core/dns.o
+ .debug_macro   0x0000000000000000       0x58 ./Middlewares/Third_Party/LwIP/src/core/dns.o
+ .debug_macro   0x0000000000000000       0xe8 ./Middlewares/Third_Party/LwIP/src/core/dns.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/core/dns.o
  .debug_macro   0x0000000000000000       0x10 ./Middlewares/Third_Party/LwIP/src/core/dns.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/core/dns.o
@@ -8675,9 +14805,9 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x11f ./Middlewares/Third_Party/LwIP/src/core/dns.o
  .debug_macro   0x0000000000000000       0x82 ./Middlewares/Third_Party/LwIP/src/core/dns.o
  .debug_macro   0x0000000000000000       0x66 ./Middlewares/Third_Party/LwIP/src/core/dns.o
- .debug_macro   0x0000000000000000      0x756 ./Middlewares/Third_Party/LwIP/src/core/dns.o
- .debug_line    0x0000000000000000      0xb74 ./Middlewares/Third_Party/LwIP/src/core/dns.o
- .debug_str     0x0000000000000000   0x13e823 ./Middlewares/Third_Party/LwIP/src/core/dns.o
+ .debug_macro   0x0000000000000000      0x739 ./Middlewares/Third_Party/LwIP/src/core/dns.o
+ .debug_line    0x0000000000000000      0xc55 ./Middlewares/Third_Party/LwIP/src/core/dns.o
+ .debug_str     0x0000000000000000   0x15d097 ./Middlewares/Third_Party/LwIP/src/core/dns.o
  .comment       0x0000000000000000       0x44 ./Middlewares/Third_Party/LwIP/src/core/dns.o
  .ARM.attributes
                 0x0000000000000000       0x32 ./Middlewares/Third_Party/LwIP/src/core/dns.o
@@ -8789,6 +14919,15 @@ Discarded input sections
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/inet_chksum.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/inet_chksum.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/inet_chksum.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/inet_chksum.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/inet_chksum.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/inet_chksum.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/inet_chksum.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/inet_chksum.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/inet_chksum.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/inet_chksum.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/inet_chksum.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/inet_chksum.o
  .text          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/core/inet_chksum.o
  .data          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/core/inet_chksum.o
  .bss           0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/core/inet_chksum.o
@@ -8806,7 +14945,7 @@ Discarded input sections
  .text.ip_chksum_pseudo_partial
                 0x0000000000000000       0x3a ./Middlewares/Third_Party/LwIP/src/core/inet_chksum.o
  .debug_macro   0x0000000000000000      0xac6 ./Middlewares/Third_Party/LwIP/src/core/inet_chksum.o
- .debug_macro   0x0000000000000000      0x232 ./Middlewares/Third_Party/LwIP/src/core/inet_chksum.o
+ .debug_macro   0x0000000000000000      0x24a ./Middlewares/Third_Party/LwIP/src/core/inet_chksum.o
  .debug_macro   0x0000000000000000       0x2e ./Middlewares/Third_Party/LwIP/src/core/inet_chksum.o
  .debug_macro   0x0000000000000000       0x3b ./Middlewares/Third_Party/LwIP/src/core/inet_chksum.o
  .debug_macro   0x0000000000000000       0x22 ./Middlewares/Third_Party/LwIP/src/core/inet_chksum.o
@@ -8854,6 +14993,7 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x129 ./Middlewares/Third_Party/LwIP/src/core/inet_chksum.o
  .debug_macro   0x0000000000000000      0x3f9 ./Middlewares/Third_Party/LwIP/src/core/inet_chksum.o
  .debug_macro   0x0000000000000000      0x275 ./Middlewares/Third_Party/LwIP/src/core/inet_chksum.o
+ .debug_macro   0x0000000000000000      0xe42 ./Middlewares/Third_Party/LwIP/src/core/inet_chksum.o
  .debug_macro   0x0000000000000000      0x3ca ./Middlewares/Third_Party/LwIP/src/core/inet_chksum.o
  .debug_macro   0x0000000000000000      0x45c ./Middlewares/Third_Party/LwIP/src/core/inet_chksum.o
  .debug_macro   0x0000000000000000       0x3c ./Middlewares/Third_Party/LwIP/src/core/inet_chksum.o
@@ -8864,8 +15004,16 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x1c4 ./Middlewares/Third_Party/LwIP/src/core/inet_chksum.o
  .debug_macro   0x0000000000000000      0x22a ./Middlewares/Third_Party/LwIP/src/core/inet_chksum.o
  .debug_macro   0x0000000000000000       0x35 ./Middlewares/Third_Party/LwIP/src/core/inet_chksum.o
+ .debug_macro   0x0000000000000000      0x830 ./Middlewares/Third_Party/LwIP/src/core/inet_chksum.o
+ .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/core/inet_chksum.o
+ .debug_macro   0x0000000000000000      0x1ce ./Middlewares/Third_Party/LwIP/src/core/inet_chksum.o
+ .debug_macro   0x0000000000000000      0xb1d ./Middlewares/Third_Party/LwIP/src/core/inet_chksum.o
+ .debug_macro   0x0000000000000000      0x29f ./Middlewares/Third_Party/LwIP/src/core/inet_chksum.o
+ .debug_macro   0x0000000000000000      0x693 ./Middlewares/Third_Party/LwIP/src/core/inet_chksum.o
+ .debug_macro   0x0000000000000000       0xa6 ./Middlewares/Third_Party/LwIP/src/core/inet_chksum.o
  .debug_macro   0x0000000000000000      0x5e6 ./Middlewares/Third_Party/LwIP/src/core/inet_chksum.o
- .debug_macro   0x0000000000000000       0xd0 ./Middlewares/Third_Party/LwIP/src/core/inet_chksum.o
+ .debug_macro   0x0000000000000000       0x58 ./Middlewares/Third_Party/LwIP/src/core/inet_chksum.o
+ .debug_macro   0x0000000000000000       0xe8 ./Middlewares/Third_Party/LwIP/src/core/inet_chksum.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/core/inet_chksum.o
  .debug_macro   0x0000000000000000       0x10 ./Middlewares/Third_Party/LwIP/src/core/inet_chksum.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/core/inet_chksum.o
@@ -8905,7 +15053,7 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x11f ./Middlewares/Third_Party/LwIP/src/core/inet_chksum.o
  .debug_macro   0x0000000000000000       0x82 ./Middlewares/Third_Party/LwIP/src/core/inet_chksum.o
  .debug_macro   0x0000000000000000       0x66 ./Middlewares/Third_Party/LwIP/src/core/inet_chksum.o
- .debug_macro   0x0000000000000000      0x756 ./Middlewares/Third_Party/LwIP/src/core/inet_chksum.o
+ .debug_macro   0x0000000000000000      0x739 ./Middlewares/Third_Party/LwIP/src/core/inet_chksum.o
  .debug_macro   0x0000000000000000       0xad ./Middlewares/Third_Party/LwIP/src/core/inet_chksum.o
  .debug_macro   0x0000000000000000       0x6a ./Middlewares/Third_Party/LwIP/src/core/inet_chksum.o
  .debug_macro   0x0000000000000000      0x1c3 ./Middlewares/Third_Party/LwIP/src/core/inet_chksum.o
@@ -9043,11 +15191,42 @@ Discarded input sections
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/init.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/init.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/init.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/init.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/init.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/init.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/init.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/init.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/init.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/init.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/init.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/init.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/init.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/init.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/init.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/init.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/init.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/init.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/init.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/init.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/init.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/init.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/init.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/init.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/init.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/init.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/init.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/init.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/init.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/init.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/init.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/init.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/init.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/init.o
  .text          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/core/init.o
  .data          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/core/init.o
  .bss           0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/core/init.o
  .debug_macro   0x0000000000000000      0xac6 ./Middlewares/Third_Party/LwIP/src/core/init.o
- .debug_macro   0x0000000000000000      0x232 ./Middlewares/Third_Party/LwIP/src/core/init.o
+ .debug_macro   0x0000000000000000      0x24a ./Middlewares/Third_Party/LwIP/src/core/init.o
  .debug_macro   0x0000000000000000       0x2e ./Middlewares/Third_Party/LwIP/src/core/init.o
  .debug_macro   0x0000000000000000       0x3b ./Middlewares/Third_Party/LwIP/src/core/init.o
  .debug_macro   0x0000000000000000       0x22 ./Middlewares/Third_Party/LwIP/src/core/init.o
@@ -9095,6 +15274,7 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x129 ./Middlewares/Third_Party/LwIP/src/core/init.o
  .debug_macro   0x0000000000000000      0x3f9 ./Middlewares/Third_Party/LwIP/src/core/init.o
  .debug_macro   0x0000000000000000      0x275 ./Middlewares/Third_Party/LwIP/src/core/init.o
+ .debug_macro   0x0000000000000000      0xe42 ./Middlewares/Third_Party/LwIP/src/core/init.o
  .debug_macro   0x0000000000000000      0x3ca ./Middlewares/Third_Party/LwIP/src/core/init.o
  .debug_macro   0x0000000000000000      0x45c ./Middlewares/Third_Party/LwIP/src/core/init.o
  .debug_macro   0x0000000000000000       0x3c ./Middlewares/Third_Party/LwIP/src/core/init.o
@@ -9105,8 +15285,16 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x1c4 ./Middlewares/Third_Party/LwIP/src/core/init.o
  .debug_macro   0x0000000000000000      0x22a ./Middlewares/Third_Party/LwIP/src/core/init.o
  .debug_macro   0x0000000000000000       0x35 ./Middlewares/Third_Party/LwIP/src/core/init.o
+ .debug_macro   0x0000000000000000      0x830 ./Middlewares/Third_Party/LwIP/src/core/init.o
+ .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/core/init.o
+ .debug_macro   0x0000000000000000      0x1ce ./Middlewares/Third_Party/LwIP/src/core/init.o
+ .debug_macro   0x0000000000000000      0xb1d ./Middlewares/Third_Party/LwIP/src/core/init.o
+ .debug_macro   0x0000000000000000      0x29f ./Middlewares/Third_Party/LwIP/src/core/init.o
+ .debug_macro   0x0000000000000000      0x693 ./Middlewares/Third_Party/LwIP/src/core/init.o
+ .debug_macro   0x0000000000000000       0xa6 ./Middlewares/Third_Party/LwIP/src/core/init.o
  .debug_macro   0x0000000000000000      0x5e6 ./Middlewares/Third_Party/LwIP/src/core/init.o
- .debug_macro   0x0000000000000000       0xd0 ./Middlewares/Third_Party/LwIP/src/core/init.o
+ .debug_macro   0x0000000000000000       0x58 ./Middlewares/Third_Party/LwIP/src/core/init.o
+ .debug_macro   0x0000000000000000       0xe8 ./Middlewares/Third_Party/LwIP/src/core/init.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/core/init.o
  .debug_macro   0x0000000000000000       0x10 ./Middlewares/Third_Party/LwIP/src/core/init.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/core/init.o
@@ -9146,7 +15334,7 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x11f ./Middlewares/Third_Party/LwIP/src/core/init.o
  .debug_macro   0x0000000000000000       0x82 ./Middlewares/Third_Party/LwIP/src/core/init.o
  .debug_macro   0x0000000000000000       0x66 ./Middlewares/Third_Party/LwIP/src/core/init.o
- .debug_macro   0x0000000000000000      0x756 ./Middlewares/Third_Party/LwIP/src/core/init.o
+ .debug_macro   0x0000000000000000      0x739 ./Middlewares/Third_Party/LwIP/src/core/init.o
  .debug_macro   0x0000000000000000       0x5e ./Middlewares/Third_Party/LwIP/src/core/init.o
  .debug_macro   0x0000000000000000       0x10 ./Middlewares/Third_Party/LwIP/src/core/init.o
  .debug_macro   0x0000000000000000       0x10 ./Middlewares/Third_Party/LwIP/src/core/init.o
@@ -9154,24 +15342,59 @@ Discarded input sections
  .debug_macro   0x0000000000000000       0x25 ./Middlewares/Third_Party/LwIP/src/core/init.o
  .debug_macro   0x0000000000000000       0x22 ./Middlewares/Third_Party/LwIP/src/core/init.o
  .debug_macro   0x0000000000000000      0x15b ./Middlewares/Third_Party/LwIP/src/core/init.o
- .debug_macro   0x0000000000000000       0xe4 ./Middlewares/Third_Party/LwIP/src/core/init.o
- .debug_macro   0x0000000000000000       0xad ./Middlewares/Third_Party/LwIP/src/core/init.o
+ .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/core/init.o
+ .debug_macro   0x0000000000000000      0x111 ./Middlewares/Third_Party/LwIP/src/core/init.o
+ .debug_macro   0x0000000000000000      0x15a ./Middlewares/Third_Party/LwIP/src/core/init.o
+ .debug_macro   0x0000000000000000       0xde ./Middlewares/Third_Party/LwIP/src/core/init.o
+ .debug_macro   0x0000000000000000       0x1c ./Middlewares/Third_Party/LwIP/src/core/init.o
+ .debug_macro   0x0000000000000000       0x26 ./Middlewares/Third_Party/LwIP/src/core/init.o
+ .debug_macro   0x0000000000000000      0x4ef ./Middlewares/Third_Party/LwIP/src/core/init.o
+ .debug_macro   0x0000000000000000       0xb5 ./Middlewares/Third_Party/LwIP/src/core/init.o
+ .debug_macro   0x0000000000000000       0xaa ./Middlewares/Third_Party/LwIP/src/core/init.o
+ .debug_macro   0x0000000000000000       0x91 ./Middlewares/Third_Party/LwIP/src/core/init.o
+ .debug_macro   0x0000000000000000       0x8d ./Middlewares/Third_Party/LwIP/src/core/init.o
+ .debug_macro   0x0000000000000000       0x7e ./Middlewares/Third_Party/LwIP/src/core/init.o
+ .debug_macro   0x0000000000000000       0x19 ./Middlewares/Third_Party/LwIP/src/core/init.o
+ .debug_macro   0x0000000000000000       0xf2 ./Middlewares/Third_Party/LwIP/src/core/init.o
+ .debug_macro   0x0000000000000000       0x10 ./Middlewares/Third_Party/LwIP/src/core/init.o
+ .debug_macro   0x0000000000000000       0x73 ./Middlewares/Third_Party/LwIP/src/core/init.o
+ .debug_macro   0x0000000000000000       0xb3 ./Middlewares/Third_Party/LwIP/src/core/init.o
  .debug_macro   0x0000000000000000       0x10 ./Middlewares/Third_Party/LwIP/src/core/init.o
  .debug_macro   0x0000000000000000       0x6a ./Middlewares/Third_Party/LwIP/src/core/init.o
  .debug_macro   0x0000000000000000      0x1c3 ./Middlewares/Third_Party/LwIP/src/core/init.o
  .debug_macro   0x0000000000000000      0x169 ./Middlewares/Third_Party/LwIP/src/core/init.o
  .debug_macro   0x0000000000000000      0x12f ./Middlewares/Third_Party/LwIP/src/core/init.o
+ .debug_macro   0x0000000000000000       0xf4 ./Middlewares/Third_Party/LwIP/src/core/init.o
+ .debug_macro   0x0000000000000000      0x320 ./Middlewares/Third_Party/LwIP/src/core/init.o
+ .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/core/init.o
+ .debug_macro   0x0000000000000000       0x20 ./Middlewares/Third_Party/LwIP/src/core/init.o
+ .debug_macro   0x0000000000000000      0x401 ./Middlewares/Third_Party/LwIP/src/core/init.o
  .debug_macro   0x0000000000000000       0xa0 ./Middlewares/Third_Party/LwIP/src/core/init.o
  .debug_macro   0x0000000000000000       0x28 ./Middlewares/Third_Party/LwIP/src/core/init.o
  .debug_macro   0x0000000000000000       0x2e ./Middlewares/Third_Party/LwIP/src/core/init.o
  .debug_macro   0x0000000000000000       0xea ./Middlewares/Third_Party/LwIP/src/core/init.o
+ .debug_macro   0x0000000000000000       0x10 ./Middlewares/Third_Party/LwIP/src/core/init.o
+ .debug_macro   0x0000000000000000       0x4d ./Middlewares/Third_Party/LwIP/src/core/init.o
  .debug_macro   0x0000000000000000       0x2e ./Middlewares/Third_Party/LwIP/src/core/init.o
  .debug_macro   0x0000000000000000       0x70 ./Middlewares/Third_Party/LwIP/src/core/init.o
  .debug_macro   0x0000000000000000       0xf9 ./Middlewares/Third_Party/LwIP/src/core/init.o
+ .debug_macro   0x0000000000000000       0x7c ./Middlewares/Third_Party/LwIP/src/core/init.o
+ .debug_macro   0x0000000000000000      0x1d7 ./Middlewares/Third_Party/LwIP/src/core/init.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/core/init.o
  .debug_macro   0x0000000000000000       0x46 ./Middlewares/Third_Party/LwIP/src/core/init.o
  .debug_macro   0x0000000000000000       0x22 ./Middlewares/Third_Party/LwIP/src/core/init.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/core/init.o
+ .debug_macro   0x0000000000000000       0x40 ./Middlewares/Third_Party/LwIP/src/core/init.o
+ .debug_macro   0x0000000000000000       0xda ./Middlewares/Third_Party/LwIP/src/core/init.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ip.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ip.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ip.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ip.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ip.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ip.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ip.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ip.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ip.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ip.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ip.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ip.o
@@ -9293,7 +15516,7 @@ Discarded input sections
  .data          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/core/ip.o
  .bss           0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/core/ip.o
  .debug_macro   0x0000000000000000      0xac6 ./Middlewares/Third_Party/LwIP/src/core/ip.o
- .debug_macro   0x0000000000000000      0x232 ./Middlewares/Third_Party/LwIP/src/core/ip.o
+ .debug_macro   0x0000000000000000      0x24a ./Middlewares/Third_Party/LwIP/src/core/ip.o
  .debug_macro   0x0000000000000000       0x2e ./Middlewares/Third_Party/LwIP/src/core/ip.o
  .debug_macro   0x0000000000000000       0x3b ./Middlewares/Third_Party/LwIP/src/core/ip.o
  .debug_macro   0x0000000000000000       0x22 ./Middlewares/Third_Party/LwIP/src/core/ip.o
@@ -9341,6 +15564,7 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x129 ./Middlewares/Third_Party/LwIP/src/core/ip.o
  .debug_macro   0x0000000000000000      0x3f9 ./Middlewares/Third_Party/LwIP/src/core/ip.o
  .debug_macro   0x0000000000000000      0x275 ./Middlewares/Third_Party/LwIP/src/core/ip.o
+ .debug_macro   0x0000000000000000      0xe42 ./Middlewares/Third_Party/LwIP/src/core/ip.o
  .debug_macro   0x0000000000000000      0x3ca ./Middlewares/Third_Party/LwIP/src/core/ip.o
  .debug_macro   0x0000000000000000      0x45c ./Middlewares/Third_Party/LwIP/src/core/ip.o
  .debug_macro   0x0000000000000000       0x3c ./Middlewares/Third_Party/LwIP/src/core/ip.o
@@ -9351,8 +15575,16 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x1c4 ./Middlewares/Third_Party/LwIP/src/core/ip.o
  .debug_macro   0x0000000000000000      0x22a ./Middlewares/Third_Party/LwIP/src/core/ip.o
  .debug_macro   0x0000000000000000       0x35 ./Middlewares/Third_Party/LwIP/src/core/ip.o
+ .debug_macro   0x0000000000000000      0x830 ./Middlewares/Third_Party/LwIP/src/core/ip.o
+ .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/core/ip.o
+ .debug_macro   0x0000000000000000      0x1ce ./Middlewares/Third_Party/LwIP/src/core/ip.o
+ .debug_macro   0x0000000000000000      0xb1d ./Middlewares/Third_Party/LwIP/src/core/ip.o
+ .debug_macro   0x0000000000000000      0x29f ./Middlewares/Third_Party/LwIP/src/core/ip.o
+ .debug_macro   0x0000000000000000      0x693 ./Middlewares/Third_Party/LwIP/src/core/ip.o
+ .debug_macro   0x0000000000000000       0xa6 ./Middlewares/Third_Party/LwIP/src/core/ip.o
  .debug_macro   0x0000000000000000      0x5e6 ./Middlewares/Third_Party/LwIP/src/core/ip.o
- .debug_macro   0x0000000000000000       0xd0 ./Middlewares/Third_Party/LwIP/src/core/ip.o
+ .debug_macro   0x0000000000000000       0x58 ./Middlewares/Third_Party/LwIP/src/core/ip.o
+ .debug_macro   0x0000000000000000       0xe8 ./Middlewares/Third_Party/LwIP/src/core/ip.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/core/ip.o
  .debug_macro   0x0000000000000000       0x10 ./Middlewares/Third_Party/LwIP/src/core/ip.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/core/ip.o
@@ -9392,7 +15624,7 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x11f ./Middlewares/Third_Party/LwIP/src/core/ip.o
  .debug_macro   0x0000000000000000       0x82 ./Middlewares/Third_Party/LwIP/src/core/ip.o
  .debug_macro   0x0000000000000000       0x66 ./Middlewares/Third_Party/LwIP/src/core/ip.o
- .debug_macro   0x0000000000000000      0x756 ./Middlewares/Third_Party/LwIP/src/core/ip.o
+ .debug_macro   0x0000000000000000      0x739 ./Middlewares/Third_Party/LwIP/src/core/ip.o
  .debug_macro   0x0000000000000000       0x6a ./Middlewares/Third_Party/LwIP/src/core/ip.o
  .debug_macro   0x0000000000000000      0x1c3 ./Middlewares/Third_Party/LwIP/src/core/ip.o
  .debug_macro   0x0000000000000000      0x169 ./Middlewares/Third_Party/LwIP/src/core/ip.o
@@ -9520,13 +15752,37 @@ Discarded input sections
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/mem.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/mem.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/mem.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/mem.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/mem.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/mem.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/mem.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/mem.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/mem.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/mem.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/mem.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/mem.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/mem.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/mem.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/mem.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/mem.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/mem.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/mem.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/mem.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/mem.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/mem.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/mem.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/mem.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/mem.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/mem.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/mem.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/mem.o
  .text          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/core/mem.o
  .data          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/core/mem.o
  .bss           0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/core/mem.o
  .text.mem_calloc
                 0x0000000000000000       0x5c ./Middlewares/Third_Party/LwIP/src/core/mem.o
  .debug_macro   0x0000000000000000      0xac6 ./Middlewares/Third_Party/LwIP/src/core/mem.o
- .debug_macro   0x0000000000000000      0x232 ./Middlewares/Third_Party/LwIP/src/core/mem.o
+ .debug_macro   0x0000000000000000      0x24a ./Middlewares/Third_Party/LwIP/src/core/mem.o
  .debug_macro   0x0000000000000000       0x2e ./Middlewares/Third_Party/LwIP/src/core/mem.o
  .debug_macro   0x0000000000000000       0x3b ./Middlewares/Third_Party/LwIP/src/core/mem.o
  .debug_macro   0x0000000000000000       0x22 ./Middlewares/Third_Party/LwIP/src/core/mem.o
@@ -9574,6 +15830,7 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x129 ./Middlewares/Third_Party/LwIP/src/core/mem.o
  .debug_macro   0x0000000000000000      0x3f9 ./Middlewares/Third_Party/LwIP/src/core/mem.o
  .debug_macro   0x0000000000000000      0x275 ./Middlewares/Third_Party/LwIP/src/core/mem.o
+ .debug_macro   0x0000000000000000      0xe42 ./Middlewares/Third_Party/LwIP/src/core/mem.o
  .debug_macro   0x0000000000000000      0x3ca ./Middlewares/Third_Party/LwIP/src/core/mem.o
  .debug_macro   0x0000000000000000      0x45c ./Middlewares/Third_Party/LwIP/src/core/mem.o
  .debug_macro   0x0000000000000000       0x3c ./Middlewares/Third_Party/LwIP/src/core/mem.o
@@ -9584,8 +15841,16 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x1c4 ./Middlewares/Third_Party/LwIP/src/core/mem.o
  .debug_macro   0x0000000000000000      0x22a ./Middlewares/Third_Party/LwIP/src/core/mem.o
  .debug_macro   0x0000000000000000       0x35 ./Middlewares/Third_Party/LwIP/src/core/mem.o
+ .debug_macro   0x0000000000000000      0x830 ./Middlewares/Third_Party/LwIP/src/core/mem.o
+ .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/core/mem.o
+ .debug_macro   0x0000000000000000      0x1ce ./Middlewares/Third_Party/LwIP/src/core/mem.o
+ .debug_macro   0x0000000000000000      0xb1d ./Middlewares/Third_Party/LwIP/src/core/mem.o
+ .debug_macro   0x0000000000000000      0x29f ./Middlewares/Third_Party/LwIP/src/core/mem.o
+ .debug_macro   0x0000000000000000      0x693 ./Middlewares/Third_Party/LwIP/src/core/mem.o
+ .debug_macro   0x0000000000000000       0xa6 ./Middlewares/Third_Party/LwIP/src/core/mem.o
  .debug_macro   0x0000000000000000      0x5e6 ./Middlewares/Third_Party/LwIP/src/core/mem.o
- .debug_macro   0x0000000000000000       0xd0 ./Middlewares/Third_Party/LwIP/src/core/mem.o
+ .debug_macro   0x0000000000000000       0x58 ./Middlewares/Third_Party/LwIP/src/core/mem.o
+ .debug_macro   0x0000000000000000       0xe8 ./Middlewares/Third_Party/LwIP/src/core/mem.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/core/mem.o
  .debug_macro   0x0000000000000000       0x10 ./Middlewares/Third_Party/LwIP/src/core/mem.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/core/mem.o
@@ -9625,10 +15890,25 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x11f ./Middlewares/Third_Party/LwIP/src/core/mem.o
  .debug_macro   0x0000000000000000       0x82 ./Middlewares/Third_Party/LwIP/src/core/mem.o
  .debug_macro   0x0000000000000000       0x66 ./Middlewares/Third_Party/LwIP/src/core/mem.o
- .debug_macro   0x0000000000000000      0x756 ./Middlewares/Third_Party/LwIP/src/core/mem.o
+ .debug_macro   0x0000000000000000      0x739 ./Middlewares/Third_Party/LwIP/src/core/mem.o
  .debug_macro   0x0000000000000000       0x10 ./Middlewares/Third_Party/LwIP/src/core/mem.o
  .debug_macro   0x0000000000000000       0x6a ./Middlewares/Third_Party/LwIP/src/core/mem.o
- .debug_macro   0x0000000000000000       0xe4 ./Middlewares/Third_Party/LwIP/src/core/mem.o
+ .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/core/mem.o
+ .debug_macro   0x0000000000000000      0x111 ./Middlewares/Third_Party/LwIP/src/core/mem.o
+ .debug_macro   0x0000000000000000      0x15a ./Middlewares/Third_Party/LwIP/src/core/mem.o
+ .debug_macro   0x0000000000000000       0xde ./Middlewares/Third_Party/LwIP/src/core/mem.o
+ .debug_macro   0x0000000000000000       0x1c ./Middlewares/Third_Party/LwIP/src/core/mem.o
+ .debug_macro   0x0000000000000000       0x26 ./Middlewares/Third_Party/LwIP/src/core/mem.o
+ .debug_macro   0x0000000000000000      0x4ef ./Middlewares/Third_Party/LwIP/src/core/mem.o
+ .debug_macro   0x0000000000000000       0xb5 ./Middlewares/Third_Party/LwIP/src/core/mem.o
+ .debug_macro   0x0000000000000000       0xaa ./Middlewares/Third_Party/LwIP/src/core/mem.o
+ .debug_macro   0x0000000000000000       0x91 ./Middlewares/Third_Party/LwIP/src/core/mem.o
+ .debug_macro   0x0000000000000000       0x8d ./Middlewares/Third_Party/LwIP/src/core/mem.o
+ .debug_macro   0x0000000000000000       0x7e ./Middlewares/Third_Party/LwIP/src/core/mem.o
+ .debug_macro   0x0000000000000000       0x19 ./Middlewares/Third_Party/LwIP/src/core/mem.o
+ .debug_macro   0x0000000000000000       0xf2 ./Middlewares/Third_Party/LwIP/src/core/mem.o
+ .debug_macro   0x0000000000000000       0x10 ./Middlewares/Third_Party/LwIP/src/core/mem.o
+ .debug_macro   0x0000000000000000       0x73 ./Middlewares/Third_Party/LwIP/src/core/mem.o
  .debug_macro   0x0000000000000000       0x10 ./Middlewares/Third_Party/LwIP/src/core/mem.o
  .debug_macro   0x0000000000000000       0x3f ./Middlewares/Third_Party/LwIP/src/core/mem.o
  .debug_macro   0x0000000000000000       0x25 ./Middlewares/Third_Party/LwIP/src/core/mem.o
@@ -9770,11 +16050,44 @@ Discarded input sections
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/memp.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/memp.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/memp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/memp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/memp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/memp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/memp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/memp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/memp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/memp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/memp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/memp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/memp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/memp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/memp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/memp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/memp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/memp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/memp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/memp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/memp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/memp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/memp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/memp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/memp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/memp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/memp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/memp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/memp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/memp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/memp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/memp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/memp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/memp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/memp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/memp.o
  .text          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/core/memp.o
  .data          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/core/memp.o
  .bss           0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/core/memp.o
  .debug_macro   0x0000000000000000      0xac6 ./Middlewares/Third_Party/LwIP/src/core/memp.o
- .debug_macro   0x0000000000000000      0x232 ./Middlewares/Third_Party/LwIP/src/core/memp.o
+ .debug_macro   0x0000000000000000      0x24a ./Middlewares/Third_Party/LwIP/src/core/memp.o
  .debug_macro   0x0000000000000000       0x2e ./Middlewares/Third_Party/LwIP/src/core/memp.o
  .debug_macro   0x0000000000000000       0x3b ./Middlewares/Third_Party/LwIP/src/core/memp.o
  .debug_macro   0x0000000000000000       0x22 ./Middlewares/Third_Party/LwIP/src/core/memp.o
@@ -9822,6 +16135,7 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x129 ./Middlewares/Third_Party/LwIP/src/core/memp.o
  .debug_macro   0x0000000000000000      0x3f9 ./Middlewares/Third_Party/LwIP/src/core/memp.o
  .debug_macro   0x0000000000000000      0x275 ./Middlewares/Third_Party/LwIP/src/core/memp.o
+ .debug_macro   0x0000000000000000      0xe42 ./Middlewares/Third_Party/LwIP/src/core/memp.o
  .debug_macro   0x0000000000000000      0x3ca ./Middlewares/Third_Party/LwIP/src/core/memp.o
  .debug_macro   0x0000000000000000      0x45c ./Middlewares/Third_Party/LwIP/src/core/memp.o
  .debug_macro   0x0000000000000000       0x3c ./Middlewares/Third_Party/LwIP/src/core/memp.o
@@ -9832,8 +16146,16 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x1c4 ./Middlewares/Third_Party/LwIP/src/core/memp.o
  .debug_macro   0x0000000000000000      0x22a ./Middlewares/Third_Party/LwIP/src/core/memp.o
  .debug_macro   0x0000000000000000       0x35 ./Middlewares/Third_Party/LwIP/src/core/memp.o
+ .debug_macro   0x0000000000000000      0x830 ./Middlewares/Third_Party/LwIP/src/core/memp.o
+ .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/core/memp.o
+ .debug_macro   0x0000000000000000      0x1ce ./Middlewares/Third_Party/LwIP/src/core/memp.o
+ .debug_macro   0x0000000000000000      0xb1d ./Middlewares/Third_Party/LwIP/src/core/memp.o
+ .debug_macro   0x0000000000000000      0x29f ./Middlewares/Third_Party/LwIP/src/core/memp.o
+ .debug_macro   0x0000000000000000      0x693 ./Middlewares/Third_Party/LwIP/src/core/memp.o
+ .debug_macro   0x0000000000000000       0xa6 ./Middlewares/Third_Party/LwIP/src/core/memp.o
  .debug_macro   0x0000000000000000      0x5e6 ./Middlewares/Third_Party/LwIP/src/core/memp.o
- .debug_macro   0x0000000000000000       0xd0 ./Middlewares/Third_Party/LwIP/src/core/memp.o
+ .debug_macro   0x0000000000000000       0x58 ./Middlewares/Third_Party/LwIP/src/core/memp.o
+ .debug_macro   0x0000000000000000       0xe8 ./Middlewares/Third_Party/LwIP/src/core/memp.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/core/memp.o
  .debug_macro   0x0000000000000000       0x10 ./Middlewares/Third_Party/LwIP/src/core/memp.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/core/memp.o
@@ -9873,17 +16195,32 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x11f ./Middlewares/Third_Party/LwIP/src/core/memp.o
  .debug_macro   0x0000000000000000       0x82 ./Middlewares/Third_Party/LwIP/src/core/memp.o
  .debug_macro   0x0000000000000000       0x66 ./Middlewares/Third_Party/LwIP/src/core/memp.o
- .debug_macro   0x0000000000000000      0x756 ./Middlewares/Third_Party/LwIP/src/core/memp.o
+ .debug_macro   0x0000000000000000      0x739 ./Middlewares/Third_Party/LwIP/src/core/memp.o
  .debug_macro   0x0000000000000000       0x10 ./Middlewares/Third_Party/LwIP/src/core/memp.o
  .debug_macro   0x0000000000000000       0x3f ./Middlewares/Third_Party/LwIP/src/core/memp.o
  .debug_macro   0x0000000000000000       0x10 ./Middlewares/Third_Party/LwIP/src/core/memp.o
  .debug_macro   0x0000000000000000       0x25 ./Middlewares/Third_Party/LwIP/src/core/memp.o
  .debug_macro   0x0000000000000000      0x15b ./Middlewares/Third_Party/LwIP/src/core/memp.o
  .debug_macro   0x0000000000000000       0x22 ./Middlewares/Third_Party/LwIP/src/core/memp.o
- .debug_macro   0x0000000000000000       0xe4 ./Middlewares/Third_Party/LwIP/src/core/memp.o
+ .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/core/memp.o
+ .debug_macro   0x0000000000000000      0x111 ./Middlewares/Third_Party/LwIP/src/core/memp.o
+ .debug_macro   0x0000000000000000      0x15a ./Middlewares/Third_Party/LwIP/src/core/memp.o
+ .debug_macro   0x0000000000000000       0xde ./Middlewares/Third_Party/LwIP/src/core/memp.o
+ .debug_macro   0x0000000000000000       0x1c ./Middlewares/Third_Party/LwIP/src/core/memp.o
+ .debug_macro   0x0000000000000000       0x26 ./Middlewares/Third_Party/LwIP/src/core/memp.o
+ .debug_macro   0x0000000000000000      0x4ef ./Middlewares/Third_Party/LwIP/src/core/memp.o
+ .debug_macro   0x0000000000000000       0xb5 ./Middlewares/Third_Party/LwIP/src/core/memp.o
+ .debug_macro   0x0000000000000000       0xaa ./Middlewares/Third_Party/LwIP/src/core/memp.o
+ .debug_macro   0x0000000000000000       0x91 ./Middlewares/Third_Party/LwIP/src/core/memp.o
+ .debug_macro   0x0000000000000000       0x8d ./Middlewares/Third_Party/LwIP/src/core/memp.o
+ .debug_macro   0x0000000000000000       0x7e ./Middlewares/Third_Party/LwIP/src/core/memp.o
+ .debug_macro   0x0000000000000000       0x19 ./Middlewares/Third_Party/LwIP/src/core/memp.o
+ .debug_macro   0x0000000000000000       0xf2 ./Middlewares/Third_Party/LwIP/src/core/memp.o
+ .debug_macro   0x0000000000000000       0x10 ./Middlewares/Third_Party/LwIP/src/core/memp.o
+ .debug_macro   0x0000000000000000       0x73 ./Middlewares/Third_Party/LwIP/src/core/memp.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/core/memp.o
  .debug_macro   0x0000000000000000       0x20 ./Middlewares/Third_Party/LwIP/src/core/memp.o
- .debug_macro   0x0000000000000000       0xad ./Middlewares/Third_Party/LwIP/src/core/memp.o
+ .debug_macro   0x0000000000000000       0xb3 ./Middlewares/Third_Party/LwIP/src/core/memp.o
  .debug_macro   0x0000000000000000       0x10 ./Middlewares/Third_Party/LwIP/src/core/memp.o
  .debug_macro   0x0000000000000000       0x6a ./Middlewares/Third_Party/LwIP/src/core/memp.o
  .debug_macro   0x0000000000000000      0x1c3 ./Middlewares/Third_Party/LwIP/src/core/memp.o
@@ -9900,10 +16237,18 @@ Discarded input sections
  .debug_macro   0x0000000000000000       0xf9 ./Middlewares/Third_Party/LwIP/src/core/memp.o
  .debug_macro   0x0000000000000000       0x7c ./Middlewares/Third_Party/LwIP/src/core/memp.o
  .debug_macro   0x0000000000000000      0x1d7 ./Middlewares/Third_Party/LwIP/src/core/memp.o
+ .debug_macro   0x0000000000000000       0x40 ./Middlewares/Third_Party/LwIP/src/core/memp.o
+ .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/core/memp.o
+ .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/core/memp.o
+ .debug_macro   0x0000000000000000       0x4c ./Middlewares/Third_Party/LwIP/src/core/memp.o
+ .debug_macro   0x0000000000000000       0x23 ./Middlewares/Third_Party/LwIP/src/core/memp.o
+ .debug_macro   0x0000000000000000       0xf4 ./Middlewares/Third_Party/LwIP/src/core/memp.o
+ .debug_macro   0x0000000000000000      0x320 ./Middlewares/Third_Party/LwIP/src/core/memp.o
+ .debug_macro   0x0000000000000000      0x401 ./Middlewares/Third_Party/LwIP/src/core/memp.o
+ .debug_macro   0x0000000000000000       0x24 ./Middlewares/Third_Party/LwIP/src/core/memp.o
  .debug_macro   0x0000000000000000       0x46 ./Middlewares/Third_Party/LwIP/src/core/memp.o
  .debug_macro   0x0000000000000000       0x22 ./Middlewares/Third_Party/LwIP/src/core/memp.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/core/memp.o
- .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/core/memp.o
  .debug_macro   0x0000000000000000       0x35 ./Middlewares/Third_Party/LwIP/src/core/memp.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/netif.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/netif.o
@@ -10037,6 +16382,30 @@ Discarded input sections
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/netif.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/netif.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/netif.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/netif.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/netif.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/netif.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/netif.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/netif.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/netif.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/netif.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/netif.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/netif.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/netif.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/netif.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/netif.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/netif.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/netif.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/netif.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/netif.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/netif.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/netif.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/netif.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/netif.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/netif.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/netif.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/netif.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/netif.o
  .text          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/core/netif.o
  .data          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/core/netif.o
  .bss           0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/core/netif.o
@@ -10059,7 +16428,7 @@ Discarded input sections
  .text.netif_find
                 0x0000000000000000       0xa0 ./Middlewares/Third_Party/LwIP/src/core/netif.o
  .debug_macro   0x0000000000000000      0xac6 ./Middlewares/Third_Party/LwIP/src/core/netif.o
- .debug_macro   0x0000000000000000      0x232 ./Middlewares/Third_Party/LwIP/src/core/netif.o
+ .debug_macro   0x0000000000000000      0x24a ./Middlewares/Third_Party/LwIP/src/core/netif.o
  .debug_macro   0x0000000000000000       0x2e ./Middlewares/Third_Party/LwIP/src/core/netif.o
  .debug_macro   0x0000000000000000       0x3b ./Middlewares/Third_Party/LwIP/src/core/netif.o
  .debug_macro   0x0000000000000000       0x22 ./Middlewares/Third_Party/LwIP/src/core/netif.o
@@ -10107,6 +16476,7 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x129 ./Middlewares/Third_Party/LwIP/src/core/netif.o
  .debug_macro   0x0000000000000000      0x3f9 ./Middlewares/Third_Party/LwIP/src/core/netif.o
  .debug_macro   0x0000000000000000      0x275 ./Middlewares/Third_Party/LwIP/src/core/netif.o
+ .debug_macro   0x0000000000000000      0xe42 ./Middlewares/Third_Party/LwIP/src/core/netif.o
  .debug_macro   0x0000000000000000      0x3ca ./Middlewares/Third_Party/LwIP/src/core/netif.o
  .debug_macro   0x0000000000000000      0x45c ./Middlewares/Third_Party/LwIP/src/core/netif.o
  .debug_macro   0x0000000000000000       0x3c ./Middlewares/Third_Party/LwIP/src/core/netif.o
@@ -10117,8 +16487,16 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x1c4 ./Middlewares/Third_Party/LwIP/src/core/netif.o
  .debug_macro   0x0000000000000000      0x22a ./Middlewares/Third_Party/LwIP/src/core/netif.o
  .debug_macro   0x0000000000000000       0x35 ./Middlewares/Third_Party/LwIP/src/core/netif.o
+ .debug_macro   0x0000000000000000      0x830 ./Middlewares/Third_Party/LwIP/src/core/netif.o
+ .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/core/netif.o
+ .debug_macro   0x0000000000000000      0x1ce ./Middlewares/Third_Party/LwIP/src/core/netif.o
+ .debug_macro   0x0000000000000000      0xb1d ./Middlewares/Third_Party/LwIP/src/core/netif.o
+ .debug_macro   0x0000000000000000      0x29f ./Middlewares/Third_Party/LwIP/src/core/netif.o
+ .debug_macro   0x0000000000000000      0x693 ./Middlewares/Third_Party/LwIP/src/core/netif.o
+ .debug_macro   0x0000000000000000       0xa6 ./Middlewares/Third_Party/LwIP/src/core/netif.o
  .debug_macro   0x0000000000000000      0x5e6 ./Middlewares/Third_Party/LwIP/src/core/netif.o
- .debug_macro   0x0000000000000000       0xd0 ./Middlewares/Third_Party/LwIP/src/core/netif.o
+ .debug_macro   0x0000000000000000       0x58 ./Middlewares/Third_Party/LwIP/src/core/netif.o
+ .debug_macro   0x0000000000000000       0xe8 ./Middlewares/Third_Party/LwIP/src/core/netif.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/core/netif.o
  .debug_macro   0x0000000000000000       0x10 ./Middlewares/Third_Party/LwIP/src/core/netif.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/core/netif.o
@@ -10158,7 +16536,7 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x11f ./Middlewares/Third_Party/LwIP/src/core/netif.o
  .debug_macro   0x0000000000000000       0x82 ./Middlewares/Third_Party/LwIP/src/core/netif.o
  .debug_macro   0x0000000000000000       0x66 ./Middlewares/Third_Party/LwIP/src/core/netif.o
- .debug_macro   0x0000000000000000      0x756 ./Middlewares/Third_Party/LwIP/src/core/netif.o
+ .debug_macro   0x0000000000000000      0x739 ./Middlewares/Third_Party/LwIP/src/core/netif.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/core/netif.o
  .debug_macro   0x0000000000000000       0x20 ./Middlewares/Third_Party/LwIP/src/core/netif.o
  .debug_macro   0x0000000000000000       0x6a ./Middlewares/Third_Party/LwIP/src/core/netif.o
@@ -10187,8 +16565,49 @@ Discarded input sections
  .debug_macro   0x0000000000000000       0x46 ./Middlewares/Third_Party/LwIP/src/core/netif.o
  .debug_macro   0x0000000000000000       0x22 ./Middlewares/Third_Party/LwIP/src/core/netif.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/core/netif.o
- .debug_macro   0x0000000000000000       0xe4 ./Middlewares/Third_Party/LwIP/src/core/netif.o
+ .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/core/netif.o
+ .debug_macro   0x0000000000000000      0x111 ./Middlewares/Third_Party/LwIP/src/core/netif.o
+ .debug_macro   0x0000000000000000      0x15a ./Middlewares/Third_Party/LwIP/src/core/netif.o
+ .debug_macro   0x0000000000000000       0xde ./Middlewares/Third_Party/LwIP/src/core/netif.o
+ .debug_macro   0x0000000000000000       0x1c ./Middlewares/Third_Party/LwIP/src/core/netif.o
+ .debug_macro   0x0000000000000000       0x26 ./Middlewares/Third_Party/LwIP/src/core/netif.o
+ .debug_macro   0x0000000000000000      0x4ef ./Middlewares/Third_Party/LwIP/src/core/netif.o
+ .debug_macro   0x0000000000000000       0xb5 ./Middlewares/Third_Party/LwIP/src/core/netif.o
+ .debug_macro   0x0000000000000000       0xaa ./Middlewares/Third_Party/LwIP/src/core/netif.o
+ .debug_macro   0x0000000000000000       0x91 ./Middlewares/Third_Party/LwIP/src/core/netif.o
+ .debug_macro   0x0000000000000000       0x8d ./Middlewares/Third_Party/LwIP/src/core/netif.o
+ .debug_macro   0x0000000000000000       0x7e ./Middlewares/Third_Party/LwIP/src/core/netif.o
+ .debug_macro   0x0000000000000000       0x19 ./Middlewares/Third_Party/LwIP/src/core/netif.o
+ .debug_macro   0x0000000000000000       0xf2 ./Middlewares/Third_Party/LwIP/src/core/netif.o
  .debug_macro   0x0000000000000000       0x10 ./Middlewares/Third_Party/LwIP/src/core/netif.o
+ .debug_macro   0x0000000000000000       0x73 ./Middlewares/Third_Party/LwIP/src/core/netif.o
+ .debug_macro   0x0000000000000000       0x10 ./Middlewares/Third_Party/LwIP/src/core/netif.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
@@ -10352,7 +16771,7 @@ Discarded input sections
  .text.pbuf_strstr
                 0x0000000000000000       0x5a ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
  .debug_macro   0x0000000000000000      0xac6 ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
- .debug_macro   0x0000000000000000      0x232 ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
+ .debug_macro   0x0000000000000000      0x24a ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
  .debug_macro   0x0000000000000000       0x2e ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
  .debug_macro   0x0000000000000000       0x3b ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
  .debug_macro   0x0000000000000000       0x22 ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
@@ -10400,6 +16819,7 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x129 ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
  .debug_macro   0x0000000000000000      0x3f9 ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
  .debug_macro   0x0000000000000000      0x275 ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
+ .debug_macro   0x0000000000000000      0xe42 ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
  .debug_macro   0x0000000000000000      0x3ca ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
  .debug_macro   0x0000000000000000      0x45c ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
  .debug_macro   0x0000000000000000       0x3c ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
@@ -10410,8 +16830,16 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x1c4 ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
  .debug_macro   0x0000000000000000      0x22a ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
  .debug_macro   0x0000000000000000       0x35 ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
+ .debug_macro   0x0000000000000000      0x830 ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
+ .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
+ .debug_macro   0x0000000000000000      0x1ce ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
+ .debug_macro   0x0000000000000000      0xb1d ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
+ .debug_macro   0x0000000000000000      0x29f ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
+ .debug_macro   0x0000000000000000      0x693 ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
+ .debug_macro   0x0000000000000000       0xa6 ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
  .debug_macro   0x0000000000000000      0x5e6 ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
- .debug_macro   0x0000000000000000       0xd0 ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
+ .debug_macro   0x0000000000000000       0x58 ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
+ .debug_macro   0x0000000000000000       0xe8 ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
  .debug_macro   0x0000000000000000       0x10 ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
@@ -10451,7 +16879,7 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x11f ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
  .debug_macro   0x0000000000000000       0x82 ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
  .debug_macro   0x0000000000000000       0x66 ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
- .debug_macro   0x0000000000000000      0x756 ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
+ .debug_macro   0x0000000000000000      0x739 ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
  .debug_macro   0x0000000000000000       0xad ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
  .debug_macro   0x0000000000000000       0x10 ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
  .debug_macro   0x0000000000000000       0x10 ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
@@ -10460,7 +16888,22 @@ Discarded input sections
  .debug_macro   0x0000000000000000       0x22 ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
  .debug_macro   0x0000000000000000      0x15b ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
  .debug_macro   0x0000000000000000       0x6a ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
- .debug_macro   0x0000000000000000       0xe4 ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
+ .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
+ .debug_macro   0x0000000000000000      0x111 ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
+ .debug_macro   0x0000000000000000      0x15a ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
+ .debug_macro   0x0000000000000000       0xde ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
+ .debug_macro   0x0000000000000000       0x1c ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
+ .debug_macro   0x0000000000000000       0x26 ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
+ .debug_macro   0x0000000000000000      0x4ef ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
+ .debug_macro   0x0000000000000000       0xb5 ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
+ .debug_macro   0x0000000000000000       0xaa ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
+ .debug_macro   0x0000000000000000       0x91 ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
+ .debug_macro   0x0000000000000000       0x8d ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
+ .debug_macro   0x0000000000000000       0x7e ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
+ .debug_macro   0x0000000000000000       0x19 ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
+ .debug_macro   0x0000000000000000       0xf2 ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
+ .debug_macro   0x0000000000000000       0x10 ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
+ .debug_macro   0x0000000000000000       0x73 ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
  .debug_macro   0x0000000000000000       0x10 ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
  .debug_macro   0x0000000000000000      0x1c3 ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
  .debug_macro   0x0000000000000000      0x169 ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
@@ -10476,6 +16919,17 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x1d7 ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
  .debug_macro   0x0000000000000000       0x20 ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
+ .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
+ .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/raw.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/raw.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/raw.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/raw.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/raw.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/raw.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/raw.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/raw.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/raw.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/raw.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/raw.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/raw.o
@@ -10584,9 +17038,9 @@ Discarded input sections
  .debug_abbrev  0x0000000000000000       0x28 ./Middlewares/Third_Party/LwIP/src/core/raw.o
  .debug_aranges
                 0x0000000000000000       0x18 ./Middlewares/Third_Party/LwIP/src/core/raw.o
- .debug_macro   0x0000000000000000      0x4a3 ./Middlewares/Third_Party/LwIP/src/core/raw.o
+ .debug_macro   0x0000000000000000      0x507 ./Middlewares/Third_Party/LwIP/src/core/raw.o
  .debug_macro   0x0000000000000000      0xac6 ./Middlewares/Third_Party/LwIP/src/core/raw.o
- .debug_macro   0x0000000000000000      0x232 ./Middlewares/Third_Party/LwIP/src/core/raw.o
+ .debug_macro   0x0000000000000000      0x24a ./Middlewares/Third_Party/LwIP/src/core/raw.o
  .debug_macro   0x0000000000000000       0x2e ./Middlewares/Third_Party/LwIP/src/core/raw.o
  .debug_macro   0x0000000000000000       0x3b ./Middlewares/Third_Party/LwIP/src/core/raw.o
  .debug_macro   0x0000000000000000       0x22 ./Middlewares/Third_Party/LwIP/src/core/raw.o
@@ -10634,6 +17088,7 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x129 ./Middlewares/Third_Party/LwIP/src/core/raw.o
  .debug_macro   0x0000000000000000      0x3f9 ./Middlewares/Third_Party/LwIP/src/core/raw.o
  .debug_macro   0x0000000000000000      0x275 ./Middlewares/Third_Party/LwIP/src/core/raw.o
+ .debug_macro   0x0000000000000000      0xe42 ./Middlewares/Third_Party/LwIP/src/core/raw.o
  .debug_macro   0x0000000000000000      0x3ca ./Middlewares/Third_Party/LwIP/src/core/raw.o
  .debug_macro   0x0000000000000000      0x45c ./Middlewares/Third_Party/LwIP/src/core/raw.o
  .debug_macro   0x0000000000000000       0x3c ./Middlewares/Third_Party/LwIP/src/core/raw.o
@@ -10644,8 +17099,16 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x1c4 ./Middlewares/Third_Party/LwIP/src/core/raw.o
  .debug_macro   0x0000000000000000      0x22a ./Middlewares/Third_Party/LwIP/src/core/raw.o
  .debug_macro   0x0000000000000000       0x35 ./Middlewares/Third_Party/LwIP/src/core/raw.o
+ .debug_macro   0x0000000000000000      0x830 ./Middlewares/Third_Party/LwIP/src/core/raw.o
+ .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/core/raw.o
+ .debug_macro   0x0000000000000000      0x1ce ./Middlewares/Third_Party/LwIP/src/core/raw.o
+ .debug_macro   0x0000000000000000      0xb1d ./Middlewares/Third_Party/LwIP/src/core/raw.o
+ .debug_macro   0x0000000000000000      0x29f ./Middlewares/Third_Party/LwIP/src/core/raw.o
+ .debug_macro   0x0000000000000000      0x693 ./Middlewares/Third_Party/LwIP/src/core/raw.o
+ .debug_macro   0x0000000000000000       0xa6 ./Middlewares/Third_Party/LwIP/src/core/raw.o
  .debug_macro   0x0000000000000000      0x5e6 ./Middlewares/Third_Party/LwIP/src/core/raw.o
- .debug_macro   0x0000000000000000       0xd0 ./Middlewares/Third_Party/LwIP/src/core/raw.o
+ .debug_macro   0x0000000000000000       0x58 ./Middlewares/Third_Party/LwIP/src/core/raw.o
+ .debug_macro   0x0000000000000000       0xe8 ./Middlewares/Third_Party/LwIP/src/core/raw.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/core/raw.o
  .debug_macro   0x0000000000000000       0x10 ./Middlewares/Third_Party/LwIP/src/core/raw.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/core/raw.o
@@ -10685,9 +17148,9 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x11f ./Middlewares/Third_Party/LwIP/src/core/raw.o
  .debug_macro   0x0000000000000000       0x82 ./Middlewares/Third_Party/LwIP/src/core/raw.o
  .debug_macro   0x0000000000000000       0x66 ./Middlewares/Third_Party/LwIP/src/core/raw.o
- .debug_macro   0x0000000000000000      0x756 ./Middlewares/Third_Party/LwIP/src/core/raw.o
- .debug_line    0x0000000000000000      0xb74 ./Middlewares/Third_Party/LwIP/src/core/raw.o
- .debug_str     0x0000000000000000   0x13e823 ./Middlewares/Third_Party/LwIP/src/core/raw.o
+ .debug_macro   0x0000000000000000      0x739 ./Middlewares/Third_Party/LwIP/src/core/raw.o
+ .debug_line    0x0000000000000000      0xc55 ./Middlewares/Third_Party/LwIP/src/core/raw.o
+ .debug_str     0x0000000000000000   0x15d097 ./Middlewares/Third_Party/LwIP/src/core/raw.o
  .comment       0x0000000000000000       0x44 ./Middlewares/Third_Party/LwIP/src/core/raw.o
  .ARM.attributes
                 0x0000000000000000       0x32 ./Middlewares/Third_Party/LwIP/src/core/raw.o
@@ -10792,6 +17255,15 @@ Discarded input sections
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/stats.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/stats.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/stats.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/stats.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/stats.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/stats.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/stats.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/stats.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/stats.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/stats.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/stats.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/stats.o
  .text          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/core/stats.o
  .data          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/core/stats.o
  .bss           0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/core/stats.o
@@ -10799,9 +17271,9 @@ Discarded input sections
  .debug_abbrev  0x0000000000000000       0x28 ./Middlewares/Third_Party/LwIP/src/core/stats.o
  .debug_aranges
                 0x0000000000000000       0x18 ./Middlewares/Third_Party/LwIP/src/core/stats.o
- .debug_macro   0x0000000000000000      0x4a3 ./Middlewares/Third_Party/LwIP/src/core/stats.o
+ .debug_macro   0x0000000000000000      0x507 ./Middlewares/Third_Party/LwIP/src/core/stats.o
  .debug_macro   0x0000000000000000      0xac6 ./Middlewares/Third_Party/LwIP/src/core/stats.o
- .debug_macro   0x0000000000000000      0x232 ./Middlewares/Third_Party/LwIP/src/core/stats.o
+ .debug_macro   0x0000000000000000      0x24a ./Middlewares/Third_Party/LwIP/src/core/stats.o
  .debug_macro   0x0000000000000000       0x2e ./Middlewares/Third_Party/LwIP/src/core/stats.o
  .debug_macro   0x0000000000000000       0x3b ./Middlewares/Third_Party/LwIP/src/core/stats.o
  .debug_macro   0x0000000000000000       0x22 ./Middlewares/Third_Party/LwIP/src/core/stats.o
@@ -10849,6 +17321,7 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x129 ./Middlewares/Third_Party/LwIP/src/core/stats.o
  .debug_macro   0x0000000000000000      0x3f9 ./Middlewares/Third_Party/LwIP/src/core/stats.o
  .debug_macro   0x0000000000000000      0x275 ./Middlewares/Third_Party/LwIP/src/core/stats.o
+ .debug_macro   0x0000000000000000      0xe42 ./Middlewares/Third_Party/LwIP/src/core/stats.o
  .debug_macro   0x0000000000000000      0x3ca ./Middlewares/Third_Party/LwIP/src/core/stats.o
  .debug_macro   0x0000000000000000      0x45c ./Middlewares/Third_Party/LwIP/src/core/stats.o
  .debug_macro   0x0000000000000000       0x3c ./Middlewares/Third_Party/LwIP/src/core/stats.o
@@ -10859,8 +17332,16 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x1c4 ./Middlewares/Third_Party/LwIP/src/core/stats.o
  .debug_macro   0x0000000000000000      0x22a ./Middlewares/Third_Party/LwIP/src/core/stats.o
  .debug_macro   0x0000000000000000       0x35 ./Middlewares/Third_Party/LwIP/src/core/stats.o
+ .debug_macro   0x0000000000000000      0x830 ./Middlewares/Third_Party/LwIP/src/core/stats.o
+ .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/core/stats.o
+ .debug_macro   0x0000000000000000      0x1ce ./Middlewares/Third_Party/LwIP/src/core/stats.o
+ .debug_macro   0x0000000000000000      0xb1d ./Middlewares/Third_Party/LwIP/src/core/stats.o
+ .debug_macro   0x0000000000000000      0x29f ./Middlewares/Third_Party/LwIP/src/core/stats.o
+ .debug_macro   0x0000000000000000      0x693 ./Middlewares/Third_Party/LwIP/src/core/stats.o
+ .debug_macro   0x0000000000000000       0xa6 ./Middlewares/Third_Party/LwIP/src/core/stats.o
  .debug_macro   0x0000000000000000      0x5e6 ./Middlewares/Third_Party/LwIP/src/core/stats.o
- .debug_macro   0x0000000000000000       0xd0 ./Middlewares/Third_Party/LwIP/src/core/stats.o
+ .debug_macro   0x0000000000000000       0x58 ./Middlewares/Third_Party/LwIP/src/core/stats.o
+ .debug_macro   0x0000000000000000       0xe8 ./Middlewares/Third_Party/LwIP/src/core/stats.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/core/stats.o
  .debug_macro   0x0000000000000000       0x10 ./Middlewares/Third_Party/LwIP/src/core/stats.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/core/stats.o
@@ -10900,9 +17381,9 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x11f ./Middlewares/Third_Party/LwIP/src/core/stats.o
  .debug_macro   0x0000000000000000       0x82 ./Middlewares/Third_Party/LwIP/src/core/stats.o
  .debug_macro   0x0000000000000000       0x66 ./Middlewares/Third_Party/LwIP/src/core/stats.o
- .debug_macro   0x0000000000000000      0x756 ./Middlewares/Third_Party/LwIP/src/core/stats.o
- .debug_line    0x0000000000000000      0xb76 ./Middlewares/Third_Party/LwIP/src/core/stats.o
- .debug_str     0x0000000000000000   0x13e825 ./Middlewares/Third_Party/LwIP/src/core/stats.o
+ .debug_macro   0x0000000000000000      0x739 ./Middlewares/Third_Party/LwIP/src/core/stats.o
+ .debug_line    0x0000000000000000      0xc57 ./Middlewares/Third_Party/LwIP/src/core/stats.o
+ .debug_str     0x0000000000000000   0x15d099 ./Middlewares/Third_Party/LwIP/src/core/stats.o
  .comment       0x0000000000000000       0x44 ./Middlewares/Third_Party/LwIP/src/core/stats.o
  .ARM.attributes
                 0x0000000000000000       0x32 ./Middlewares/Third_Party/LwIP/src/core/stats.o
@@ -11008,16 +17489,44 @@ Discarded input sections
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/sys.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/sys.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/sys.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/sys.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/sys.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/sys.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/sys.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/sys.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/sys.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/sys.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/sys.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/sys.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/sys.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/sys.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/sys.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/sys.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/sys.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/sys.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/sys.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/sys.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/sys.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/sys.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/sys.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/sys.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/sys.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/sys.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/sys.o
  .text          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/core/sys.o
  .data          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/core/sys.o
  .bss           0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/core/sys.o
- .debug_info    0x0000000000000000       0x85 ./Middlewares/Third_Party/LwIP/src/core/sys.o
- .debug_abbrev  0x0000000000000000       0x28 ./Middlewares/Third_Party/LwIP/src/core/sys.o
+ .text.sys_msleep
+                0x0000000000000000       0x44 ./Middlewares/Third_Party/LwIP/src/core/sys.o
+ .debug_info    0x0000000000000000      0x246 ./Middlewares/Third_Party/LwIP/src/core/sys.o
+ .debug_abbrev  0x0000000000000000       0xfd ./Middlewares/Third_Party/LwIP/src/core/sys.o
  .debug_aranges
-                0x0000000000000000       0x18 ./Middlewares/Third_Party/LwIP/src/core/sys.o
- .debug_macro   0x0000000000000000      0x4ac ./Middlewares/Third_Party/LwIP/src/core/sys.o
+                0x0000000000000000       0x20 ./Middlewares/Third_Party/LwIP/src/core/sys.o
+ .debug_rnglists
+                0x0000000000000000       0x13 ./Middlewares/Third_Party/LwIP/src/core/sys.o
+ .debug_macro   0x0000000000000000      0x5e1 ./Middlewares/Third_Party/LwIP/src/core/sys.o
  .debug_macro   0x0000000000000000      0xac6 ./Middlewares/Third_Party/LwIP/src/core/sys.o
- .debug_macro   0x0000000000000000      0x232 ./Middlewares/Third_Party/LwIP/src/core/sys.o
+ .debug_macro   0x0000000000000000      0x24a ./Middlewares/Third_Party/LwIP/src/core/sys.o
  .debug_macro   0x0000000000000000       0x2e ./Middlewares/Third_Party/LwIP/src/core/sys.o
  .debug_macro   0x0000000000000000       0x3b ./Middlewares/Third_Party/LwIP/src/core/sys.o
  .debug_macro   0x0000000000000000       0x22 ./Middlewares/Third_Party/LwIP/src/core/sys.o
@@ -11065,6 +17574,7 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x129 ./Middlewares/Third_Party/LwIP/src/core/sys.o
  .debug_macro   0x0000000000000000      0x3f9 ./Middlewares/Third_Party/LwIP/src/core/sys.o
  .debug_macro   0x0000000000000000      0x275 ./Middlewares/Third_Party/LwIP/src/core/sys.o
+ .debug_macro   0x0000000000000000      0xe42 ./Middlewares/Third_Party/LwIP/src/core/sys.o
  .debug_macro   0x0000000000000000      0x3ca ./Middlewares/Third_Party/LwIP/src/core/sys.o
  .debug_macro   0x0000000000000000      0x45c ./Middlewares/Third_Party/LwIP/src/core/sys.o
  .debug_macro   0x0000000000000000       0x3c ./Middlewares/Third_Party/LwIP/src/core/sys.o
@@ -11075,8 +17585,16 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x1c4 ./Middlewares/Third_Party/LwIP/src/core/sys.o
  .debug_macro   0x0000000000000000      0x22a ./Middlewares/Third_Party/LwIP/src/core/sys.o
  .debug_macro   0x0000000000000000       0x35 ./Middlewares/Third_Party/LwIP/src/core/sys.o
+ .debug_macro   0x0000000000000000      0x830 ./Middlewares/Third_Party/LwIP/src/core/sys.o
+ .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/core/sys.o
+ .debug_macro   0x0000000000000000      0x1ce ./Middlewares/Third_Party/LwIP/src/core/sys.o
+ .debug_macro   0x0000000000000000      0xb1d ./Middlewares/Third_Party/LwIP/src/core/sys.o
+ .debug_macro   0x0000000000000000      0x29f ./Middlewares/Third_Party/LwIP/src/core/sys.o
+ .debug_macro   0x0000000000000000      0x693 ./Middlewares/Third_Party/LwIP/src/core/sys.o
+ .debug_macro   0x0000000000000000       0xa6 ./Middlewares/Third_Party/LwIP/src/core/sys.o
  .debug_macro   0x0000000000000000      0x5e6 ./Middlewares/Third_Party/LwIP/src/core/sys.o
- .debug_macro   0x0000000000000000       0xd0 ./Middlewares/Third_Party/LwIP/src/core/sys.o
+ .debug_macro   0x0000000000000000       0x58 ./Middlewares/Third_Party/LwIP/src/core/sys.o
+ .debug_macro   0x0000000000000000       0xe8 ./Middlewares/Third_Party/LwIP/src/core/sys.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/core/sys.o
  .debug_macro   0x0000000000000000       0x10 ./Middlewares/Third_Party/LwIP/src/core/sys.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/core/sys.o
@@ -11116,11 +17634,27 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x11f ./Middlewares/Third_Party/LwIP/src/core/sys.o
  .debug_macro   0x0000000000000000       0x82 ./Middlewares/Third_Party/LwIP/src/core/sys.o
  .debug_macro   0x0000000000000000       0x66 ./Middlewares/Third_Party/LwIP/src/core/sys.o
- .debug_macro   0x0000000000000000      0x756 ./Middlewares/Third_Party/LwIP/src/core/sys.o
- .debug_macro   0x0000000000000000       0xe4 ./Middlewares/Third_Party/LwIP/src/core/sys.o
- .debug_line    0x0000000000000000      0xb7d ./Middlewares/Third_Party/LwIP/src/core/sys.o
- .debug_str     0x0000000000000000   0x13ed9f ./Middlewares/Third_Party/LwIP/src/core/sys.o
+ .debug_macro   0x0000000000000000      0x739 ./Middlewares/Third_Party/LwIP/src/core/sys.o
+ .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/core/sys.o
+ .debug_macro   0x0000000000000000      0x111 ./Middlewares/Third_Party/LwIP/src/core/sys.o
+ .debug_macro   0x0000000000000000      0x15a ./Middlewares/Third_Party/LwIP/src/core/sys.o
+ .debug_macro   0x0000000000000000       0xde ./Middlewares/Third_Party/LwIP/src/core/sys.o
+ .debug_macro   0x0000000000000000       0x1c ./Middlewares/Third_Party/LwIP/src/core/sys.o
+ .debug_macro   0x0000000000000000       0x26 ./Middlewares/Third_Party/LwIP/src/core/sys.o
+ .debug_macro   0x0000000000000000      0x4ef ./Middlewares/Third_Party/LwIP/src/core/sys.o
+ .debug_macro   0x0000000000000000       0xb5 ./Middlewares/Third_Party/LwIP/src/core/sys.o
+ .debug_macro   0x0000000000000000       0xaa ./Middlewares/Third_Party/LwIP/src/core/sys.o
+ .debug_macro   0x0000000000000000       0x91 ./Middlewares/Third_Party/LwIP/src/core/sys.o
+ .debug_macro   0x0000000000000000       0x8d ./Middlewares/Third_Party/LwIP/src/core/sys.o
+ .debug_macro   0x0000000000000000       0x7e ./Middlewares/Third_Party/LwIP/src/core/sys.o
+ .debug_macro   0x0000000000000000       0x19 ./Middlewares/Third_Party/LwIP/src/core/sys.o
+ .debug_macro   0x0000000000000000       0xf2 ./Middlewares/Third_Party/LwIP/src/core/sys.o
+ .debug_macro   0x0000000000000000       0x10 ./Middlewares/Third_Party/LwIP/src/core/sys.o
+ .debug_macro   0x0000000000000000       0x73 ./Middlewares/Third_Party/LwIP/src/core/sys.o
+ .debug_line    0x0000000000000000      0xe13 ./Middlewares/Third_Party/LwIP/src/core/sys.o
+ .debug_str     0x0000000000000000   0x16376d ./Middlewares/Third_Party/LwIP/src/core/sys.o
  .comment       0x0000000000000000       0x44 ./Middlewares/Third_Party/LwIP/src/core/sys.o
+ .debug_frame   0x0000000000000000       0x34 ./Middlewares/Third_Party/LwIP/src/core/sys.o
  .ARM.attributes
                 0x0000000000000000       0x32 ./Middlewares/Third_Party/LwIP/src/core/sys.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/tcp.o
@@ -11246,15 +17780,20 @@ Discarded input sections
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/tcp.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/tcp.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/tcp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/tcp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/tcp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/tcp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/tcp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/tcp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/tcp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/tcp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/tcp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/tcp.o
  .text          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/core/tcp.o
  .data          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/core/tcp.o
  .bss           0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/core/tcp.o
  .rodata.tcp_state_str
                 0x0000000000000000       0x2c ./Middlewares/Third_Party/LwIP/src/core/tcp.o
- .text.tcp_shutdown
-                0x0000000000000000       0xb8 ./Middlewares/Third_Party/LwIP/src/core/tcp.o
- .text.tcp_bind
-                0x0000000000000000      0x130 ./Middlewares/Third_Party/LwIP/src/core/tcp.o
  .text.tcp_bind_netif
                 0x0000000000000000       0x32 ./Middlewares/Third_Party/LwIP/src/core/tcp.o
  .text.tcp_accept_null
@@ -11267,18 +17806,13 @@ Discarded input sections
                 0x0000000000000000       0x3c ./Middlewares/Third_Party/LwIP/src/core/tcp.o
  .text.tcp_setprio
                 0x0000000000000000       0x3c ./Middlewares/Third_Party/LwIP/src/core/tcp.o
- .text.tcp_new_ip_type
-                0x0000000000000000       0x1c ./Middlewares/Third_Party/LwIP/src/core/tcp.o
- .text.tcp_accept
-                0x0000000000000000       0x2e ./Middlewares/Third_Party/LwIP/src/core/tcp.o
- .text.tcp_poll
-                0x0000000000000000       0x60 ./Middlewares/Third_Party/LwIP/src/core/tcp.o
+ .text.tcp_new  0x0000000000000000       0x10 ./Middlewares/Third_Party/LwIP/src/core/tcp.o
  .text.tcp_debug_state_str
                 0x0000000000000000       0x24 ./Middlewares/Third_Party/LwIP/src/core/tcp.o
  .text.tcp_tcp_get_tcp_addrinfo
                 0x0000000000000000       0x68 ./Middlewares/Third_Party/LwIP/src/core/tcp.o
  .debug_macro   0x0000000000000000      0xac6 ./Middlewares/Third_Party/LwIP/src/core/tcp.o
- .debug_macro   0x0000000000000000      0x232 ./Middlewares/Third_Party/LwIP/src/core/tcp.o
+ .debug_macro   0x0000000000000000      0x24a ./Middlewares/Third_Party/LwIP/src/core/tcp.o
  .debug_macro   0x0000000000000000       0x2e ./Middlewares/Third_Party/LwIP/src/core/tcp.o
  .debug_macro   0x0000000000000000       0x3b ./Middlewares/Third_Party/LwIP/src/core/tcp.o
  .debug_macro   0x0000000000000000       0x22 ./Middlewares/Third_Party/LwIP/src/core/tcp.o
@@ -11326,6 +17860,7 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x129 ./Middlewares/Third_Party/LwIP/src/core/tcp.o
  .debug_macro   0x0000000000000000      0x3f9 ./Middlewares/Third_Party/LwIP/src/core/tcp.o
  .debug_macro   0x0000000000000000      0x275 ./Middlewares/Third_Party/LwIP/src/core/tcp.o
+ .debug_macro   0x0000000000000000      0xe42 ./Middlewares/Third_Party/LwIP/src/core/tcp.o
  .debug_macro   0x0000000000000000      0x3ca ./Middlewares/Third_Party/LwIP/src/core/tcp.o
  .debug_macro   0x0000000000000000      0x45c ./Middlewares/Third_Party/LwIP/src/core/tcp.o
  .debug_macro   0x0000000000000000       0x3c ./Middlewares/Third_Party/LwIP/src/core/tcp.o
@@ -11336,8 +17871,16 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x1c4 ./Middlewares/Third_Party/LwIP/src/core/tcp.o
  .debug_macro   0x0000000000000000      0x22a ./Middlewares/Third_Party/LwIP/src/core/tcp.o
  .debug_macro   0x0000000000000000       0x35 ./Middlewares/Third_Party/LwIP/src/core/tcp.o
+ .debug_macro   0x0000000000000000      0x830 ./Middlewares/Third_Party/LwIP/src/core/tcp.o
+ .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/core/tcp.o
+ .debug_macro   0x0000000000000000      0x1ce ./Middlewares/Third_Party/LwIP/src/core/tcp.o
+ .debug_macro   0x0000000000000000      0xb1d ./Middlewares/Third_Party/LwIP/src/core/tcp.o
+ .debug_macro   0x0000000000000000      0x29f ./Middlewares/Third_Party/LwIP/src/core/tcp.o
+ .debug_macro   0x0000000000000000      0x693 ./Middlewares/Third_Party/LwIP/src/core/tcp.o
+ .debug_macro   0x0000000000000000       0xa6 ./Middlewares/Third_Party/LwIP/src/core/tcp.o
  .debug_macro   0x0000000000000000      0x5e6 ./Middlewares/Third_Party/LwIP/src/core/tcp.o
- .debug_macro   0x0000000000000000       0xd0 ./Middlewares/Third_Party/LwIP/src/core/tcp.o
+ .debug_macro   0x0000000000000000       0x58 ./Middlewares/Third_Party/LwIP/src/core/tcp.o
+ .debug_macro   0x0000000000000000       0xe8 ./Middlewares/Third_Party/LwIP/src/core/tcp.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/core/tcp.o
  .debug_macro   0x0000000000000000       0x10 ./Middlewares/Third_Party/LwIP/src/core/tcp.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/core/tcp.o
@@ -11377,7 +17920,7 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x11f ./Middlewares/Third_Party/LwIP/src/core/tcp.o
  .debug_macro   0x0000000000000000       0x82 ./Middlewares/Third_Party/LwIP/src/core/tcp.o
  .debug_macro   0x0000000000000000       0x66 ./Middlewares/Third_Party/LwIP/src/core/tcp.o
- .debug_macro   0x0000000000000000      0x756 ./Middlewares/Third_Party/LwIP/src/core/tcp.o
+ .debug_macro   0x0000000000000000      0x739 ./Middlewares/Third_Party/LwIP/src/core/tcp.o
  .debug_macro   0x0000000000000000       0x6a ./Middlewares/Third_Party/LwIP/src/core/tcp.o
  .debug_macro   0x0000000000000000       0x10 ./Middlewares/Third_Party/LwIP/src/core/tcp.o
  .debug_macro   0x0000000000000000       0x10 ./Middlewares/Third_Party/LwIP/src/core/tcp.o
@@ -11389,6 +17932,7 @@ Discarded input sections
  .debug_macro   0x0000000000000000       0xad ./Middlewares/Third_Party/LwIP/src/core/tcp.o
  .debug_macro   0x0000000000000000      0x1c3 ./Middlewares/Third_Party/LwIP/src/core/tcp.o
  .debug_macro   0x0000000000000000      0x169 ./Middlewares/Third_Party/LwIP/src/core/tcp.o
+ .debug_macro   0x0000000000000000      0x13b ./Middlewares/Third_Party/LwIP/src/core/tcp.o
  .debug_macro   0x0000000000000000       0xa0 ./Middlewares/Third_Party/LwIP/src/core/tcp.o
  .debug_macro   0x0000000000000000       0x28 ./Middlewares/Third_Party/LwIP/src/core/tcp.o
  .debug_macro   0x0000000000000000       0x2e ./Middlewares/Third_Party/LwIP/src/core/tcp.o
@@ -11524,11 +18068,20 @@ Discarded input sections
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/tcp_in.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/tcp_in.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/tcp_in.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/tcp_in.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/tcp_in.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/tcp_in.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/tcp_in.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/tcp_in.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/tcp_in.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/tcp_in.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/tcp_in.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/tcp_in.o
  .text          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/core/tcp_in.o
  .data          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/core/tcp_in.o
  .bss           0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/core/tcp_in.o
  .debug_macro   0x0000000000000000      0xac6 ./Middlewares/Third_Party/LwIP/src/core/tcp_in.o
- .debug_macro   0x0000000000000000      0x232 ./Middlewares/Third_Party/LwIP/src/core/tcp_in.o
+ .debug_macro   0x0000000000000000      0x24a ./Middlewares/Third_Party/LwIP/src/core/tcp_in.o
  .debug_macro   0x0000000000000000       0x2e ./Middlewares/Third_Party/LwIP/src/core/tcp_in.o
  .debug_macro   0x0000000000000000       0x3b ./Middlewares/Third_Party/LwIP/src/core/tcp_in.o
  .debug_macro   0x0000000000000000       0x22 ./Middlewares/Third_Party/LwIP/src/core/tcp_in.o
@@ -11576,6 +18129,7 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x129 ./Middlewares/Third_Party/LwIP/src/core/tcp_in.o
  .debug_macro   0x0000000000000000      0x3f9 ./Middlewares/Third_Party/LwIP/src/core/tcp_in.o
  .debug_macro   0x0000000000000000      0x275 ./Middlewares/Third_Party/LwIP/src/core/tcp_in.o
+ .debug_macro   0x0000000000000000      0xe42 ./Middlewares/Third_Party/LwIP/src/core/tcp_in.o
  .debug_macro   0x0000000000000000      0x3ca ./Middlewares/Third_Party/LwIP/src/core/tcp_in.o
  .debug_macro   0x0000000000000000      0x45c ./Middlewares/Third_Party/LwIP/src/core/tcp_in.o
  .debug_macro   0x0000000000000000       0x3c ./Middlewares/Third_Party/LwIP/src/core/tcp_in.o
@@ -11586,8 +18140,16 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x1c4 ./Middlewares/Third_Party/LwIP/src/core/tcp_in.o
  .debug_macro   0x0000000000000000      0x22a ./Middlewares/Third_Party/LwIP/src/core/tcp_in.o
  .debug_macro   0x0000000000000000       0x35 ./Middlewares/Third_Party/LwIP/src/core/tcp_in.o
+ .debug_macro   0x0000000000000000      0x830 ./Middlewares/Third_Party/LwIP/src/core/tcp_in.o
+ .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/core/tcp_in.o
+ .debug_macro   0x0000000000000000      0x1ce ./Middlewares/Third_Party/LwIP/src/core/tcp_in.o
+ .debug_macro   0x0000000000000000      0xb1d ./Middlewares/Third_Party/LwIP/src/core/tcp_in.o
+ .debug_macro   0x0000000000000000      0x29f ./Middlewares/Third_Party/LwIP/src/core/tcp_in.o
+ .debug_macro   0x0000000000000000      0x693 ./Middlewares/Third_Party/LwIP/src/core/tcp_in.o
+ .debug_macro   0x0000000000000000       0xa6 ./Middlewares/Third_Party/LwIP/src/core/tcp_in.o
  .debug_macro   0x0000000000000000      0x5e6 ./Middlewares/Third_Party/LwIP/src/core/tcp_in.o
- .debug_macro   0x0000000000000000       0xd0 ./Middlewares/Third_Party/LwIP/src/core/tcp_in.o
+ .debug_macro   0x0000000000000000       0x58 ./Middlewares/Third_Party/LwIP/src/core/tcp_in.o
+ .debug_macro   0x0000000000000000       0xe8 ./Middlewares/Third_Party/LwIP/src/core/tcp_in.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/core/tcp_in.o
  .debug_macro   0x0000000000000000       0x10 ./Middlewares/Third_Party/LwIP/src/core/tcp_in.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/core/tcp_in.o
@@ -11627,7 +18189,7 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x11f ./Middlewares/Third_Party/LwIP/src/core/tcp_in.o
  .debug_macro   0x0000000000000000       0x82 ./Middlewares/Third_Party/LwIP/src/core/tcp_in.o
  .debug_macro   0x0000000000000000       0x66 ./Middlewares/Third_Party/LwIP/src/core/tcp_in.o
- .debug_macro   0x0000000000000000      0x756 ./Middlewares/Third_Party/LwIP/src/core/tcp_in.o
+ .debug_macro   0x0000000000000000      0x739 ./Middlewares/Third_Party/LwIP/src/core/tcp_in.o
  .debug_macro   0x0000000000000000       0x2e ./Middlewares/Third_Party/LwIP/src/core/tcp_in.o
  .debug_macro   0x0000000000000000       0x10 ./Middlewares/Third_Party/LwIP/src/core/tcp_in.o
  .debug_macro   0x0000000000000000       0xad ./Middlewares/Third_Party/LwIP/src/core/tcp_in.o
@@ -11776,11 +18338,20 @@ Discarded input sections
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/tcp_out.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/tcp_out.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/tcp_out.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/tcp_out.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/tcp_out.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/tcp_out.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/tcp_out.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/tcp_out.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/tcp_out.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/tcp_out.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/tcp_out.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/tcp_out.o
  .text          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/core/tcp_out.o
  .data          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/core/tcp_out.o
  .bss           0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/core/tcp_out.o
  .debug_macro   0x0000000000000000      0xac6 ./Middlewares/Third_Party/LwIP/src/core/tcp_out.o
- .debug_macro   0x0000000000000000      0x232 ./Middlewares/Third_Party/LwIP/src/core/tcp_out.o
+ .debug_macro   0x0000000000000000      0x24a ./Middlewares/Third_Party/LwIP/src/core/tcp_out.o
  .debug_macro   0x0000000000000000       0x2e ./Middlewares/Third_Party/LwIP/src/core/tcp_out.o
  .debug_macro   0x0000000000000000       0x3b ./Middlewares/Third_Party/LwIP/src/core/tcp_out.o
  .debug_macro   0x0000000000000000       0x22 ./Middlewares/Third_Party/LwIP/src/core/tcp_out.o
@@ -11828,6 +18399,7 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x129 ./Middlewares/Third_Party/LwIP/src/core/tcp_out.o
  .debug_macro   0x0000000000000000      0x3f9 ./Middlewares/Third_Party/LwIP/src/core/tcp_out.o
  .debug_macro   0x0000000000000000      0x275 ./Middlewares/Third_Party/LwIP/src/core/tcp_out.o
+ .debug_macro   0x0000000000000000      0xe42 ./Middlewares/Third_Party/LwIP/src/core/tcp_out.o
  .debug_macro   0x0000000000000000      0x3ca ./Middlewares/Third_Party/LwIP/src/core/tcp_out.o
  .debug_macro   0x0000000000000000      0x45c ./Middlewares/Third_Party/LwIP/src/core/tcp_out.o
  .debug_macro   0x0000000000000000       0x3c ./Middlewares/Third_Party/LwIP/src/core/tcp_out.o
@@ -11838,8 +18410,16 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x1c4 ./Middlewares/Third_Party/LwIP/src/core/tcp_out.o
  .debug_macro   0x0000000000000000      0x22a ./Middlewares/Third_Party/LwIP/src/core/tcp_out.o
  .debug_macro   0x0000000000000000       0x35 ./Middlewares/Third_Party/LwIP/src/core/tcp_out.o
+ .debug_macro   0x0000000000000000      0x830 ./Middlewares/Third_Party/LwIP/src/core/tcp_out.o
+ .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/core/tcp_out.o
+ .debug_macro   0x0000000000000000      0x1ce ./Middlewares/Third_Party/LwIP/src/core/tcp_out.o
+ .debug_macro   0x0000000000000000      0xb1d ./Middlewares/Third_Party/LwIP/src/core/tcp_out.o
+ .debug_macro   0x0000000000000000      0x29f ./Middlewares/Third_Party/LwIP/src/core/tcp_out.o
+ .debug_macro   0x0000000000000000      0x693 ./Middlewares/Third_Party/LwIP/src/core/tcp_out.o
+ .debug_macro   0x0000000000000000       0xa6 ./Middlewares/Third_Party/LwIP/src/core/tcp_out.o
  .debug_macro   0x0000000000000000      0x5e6 ./Middlewares/Third_Party/LwIP/src/core/tcp_out.o
- .debug_macro   0x0000000000000000       0xd0 ./Middlewares/Third_Party/LwIP/src/core/tcp_out.o
+ .debug_macro   0x0000000000000000       0x58 ./Middlewares/Third_Party/LwIP/src/core/tcp_out.o
+ .debug_macro   0x0000000000000000       0xe8 ./Middlewares/Third_Party/LwIP/src/core/tcp_out.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/core/tcp_out.o
  .debug_macro   0x0000000000000000       0x10 ./Middlewares/Third_Party/LwIP/src/core/tcp_out.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/core/tcp_out.o
@@ -11879,7 +18459,7 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x11f ./Middlewares/Third_Party/LwIP/src/core/tcp_out.o
  .debug_macro   0x0000000000000000       0x82 ./Middlewares/Third_Party/LwIP/src/core/tcp_out.o
  .debug_macro   0x0000000000000000       0x66 ./Middlewares/Third_Party/LwIP/src/core/tcp_out.o
- .debug_macro   0x0000000000000000      0x756 ./Middlewares/Third_Party/LwIP/src/core/tcp_out.o
+ .debug_macro   0x0000000000000000      0x739 ./Middlewares/Third_Party/LwIP/src/core/tcp_out.o
  .debug_macro   0x0000000000000000       0x2e ./Middlewares/Third_Party/LwIP/src/core/tcp_out.o
  .debug_macro   0x0000000000000000       0x10 ./Middlewares/Third_Party/LwIP/src/core/tcp_out.o
  .debug_macro   0x0000000000000000       0xad ./Middlewares/Third_Party/LwIP/src/core/tcp_out.o
@@ -12032,6 +18612,32 @@ Discarded input sections
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/timeouts.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/timeouts.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/timeouts.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/timeouts.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/timeouts.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/timeouts.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/timeouts.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/timeouts.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/timeouts.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/timeouts.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/timeouts.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/timeouts.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/timeouts.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/timeouts.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/timeouts.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/timeouts.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/timeouts.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/timeouts.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/timeouts.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/timeouts.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/timeouts.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/timeouts.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/timeouts.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/timeouts.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/timeouts.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/timeouts.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/timeouts.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/timeouts.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/timeouts.o
  .text          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/core/timeouts.o
  .data          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/core/timeouts.o
  .bss           0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/core/timeouts.o
@@ -12041,10 +18647,8 @@ Discarded input sections
                 0x0000000000000000       0x74 ./Middlewares/Third_Party/LwIP/src/core/timeouts.o
  .text.sys_restart_timeouts
                 0x0000000000000000       0x50 ./Middlewares/Third_Party/LwIP/src/core/timeouts.o
- .text.sys_timeouts_sleeptime
-                0x0000000000000000       0x70 ./Middlewares/Third_Party/LwIP/src/core/timeouts.o
  .debug_macro   0x0000000000000000      0xac6 ./Middlewares/Third_Party/LwIP/src/core/timeouts.o
- .debug_macro   0x0000000000000000      0x232 ./Middlewares/Third_Party/LwIP/src/core/timeouts.o
+ .debug_macro   0x0000000000000000      0x24a ./Middlewares/Third_Party/LwIP/src/core/timeouts.o
  .debug_macro   0x0000000000000000       0x2e ./Middlewares/Third_Party/LwIP/src/core/timeouts.o
  .debug_macro   0x0000000000000000       0x3b ./Middlewares/Third_Party/LwIP/src/core/timeouts.o
  .debug_macro   0x0000000000000000       0x22 ./Middlewares/Third_Party/LwIP/src/core/timeouts.o
@@ -12092,6 +18696,7 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x129 ./Middlewares/Third_Party/LwIP/src/core/timeouts.o
  .debug_macro   0x0000000000000000      0x3f9 ./Middlewares/Third_Party/LwIP/src/core/timeouts.o
  .debug_macro   0x0000000000000000      0x275 ./Middlewares/Third_Party/LwIP/src/core/timeouts.o
+ .debug_macro   0x0000000000000000      0xe42 ./Middlewares/Third_Party/LwIP/src/core/timeouts.o
  .debug_macro   0x0000000000000000      0x3ca ./Middlewares/Third_Party/LwIP/src/core/timeouts.o
  .debug_macro   0x0000000000000000      0x45c ./Middlewares/Third_Party/LwIP/src/core/timeouts.o
  .debug_macro   0x0000000000000000       0x3c ./Middlewares/Third_Party/LwIP/src/core/timeouts.o
@@ -12102,8 +18707,16 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x1c4 ./Middlewares/Third_Party/LwIP/src/core/timeouts.o
  .debug_macro   0x0000000000000000      0x22a ./Middlewares/Third_Party/LwIP/src/core/timeouts.o
  .debug_macro   0x0000000000000000       0x35 ./Middlewares/Third_Party/LwIP/src/core/timeouts.o
+ .debug_macro   0x0000000000000000      0x830 ./Middlewares/Third_Party/LwIP/src/core/timeouts.o
+ .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/core/timeouts.o
+ .debug_macro   0x0000000000000000      0x1ce ./Middlewares/Third_Party/LwIP/src/core/timeouts.o
+ .debug_macro   0x0000000000000000      0xb1d ./Middlewares/Third_Party/LwIP/src/core/timeouts.o
+ .debug_macro   0x0000000000000000      0x29f ./Middlewares/Third_Party/LwIP/src/core/timeouts.o
+ .debug_macro   0x0000000000000000      0x693 ./Middlewares/Third_Party/LwIP/src/core/timeouts.o
+ .debug_macro   0x0000000000000000       0xa6 ./Middlewares/Third_Party/LwIP/src/core/timeouts.o
  .debug_macro   0x0000000000000000      0x5e6 ./Middlewares/Third_Party/LwIP/src/core/timeouts.o
- .debug_macro   0x0000000000000000       0xd0 ./Middlewares/Third_Party/LwIP/src/core/timeouts.o
+ .debug_macro   0x0000000000000000       0x58 ./Middlewares/Third_Party/LwIP/src/core/timeouts.o
+ .debug_macro   0x0000000000000000       0xe8 ./Middlewares/Third_Party/LwIP/src/core/timeouts.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/core/timeouts.o
  .debug_macro   0x0000000000000000       0x10 ./Middlewares/Third_Party/LwIP/src/core/timeouts.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/core/timeouts.o
@@ -12143,7 +18756,23 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x11f ./Middlewares/Third_Party/LwIP/src/core/timeouts.o
  .debug_macro   0x0000000000000000       0x82 ./Middlewares/Third_Party/LwIP/src/core/timeouts.o
  .debug_macro   0x0000000000000000       0x66 ./Middlewares/Third_Party/LwIP/src/core/timeouts.o
- .debug_macro   0x0000000000000000      0x756 ./Middlewares/Third_Party/LwIP/src/core/timeouts.o
+ .debug_macro   0x0000000000000000      0x739 ./Middlewares/Third_Party/LwIP/src/core/timeouts.o
+ .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/core/timeouts.o
+ .debug_macro   0x0000000000000000      0x111 ./Middlewares/Third_Party/LwIP/src/core/timeouts.o
+ .debug_macro   0x0000000000000000      0x15a ./Middlewares/Third_Party/LwIP/src/core/timeouts.o
+ .debug_macro   0x0000000000000000       0xde ./Middlewares/Third_Party/LwIP/src/core/timeouts.o
+ .debug_macro   0x0000000000000000       0x1c ./Middlewares/Third_Party/LwIP/src/core/timeouts.o
+ .debug_macro   0x0000000000000000       0x26 ./Middlewares/Third_Party/LwIP/src/core/timeouts.o
+ .debug_macro   0x0000000000000000      0x4ef ./Middlewares/Third_Party/LwIP/src/core/timeouts.o
+ .debug_macro   0x0000000000000000       0xb5 ./Middlewares/Third_Party/LwIP/src/core/timeouts.o
+ .debug_macro   0x0000000000000000       0xaa ./Middlewares/Third_Party/LwIP/src/core/timeouts.o
+ .debug_macro   0x0000000000000000       0x91 ./Middlewares/Third_Party/LwIP/src/core/timeouts.o
+ .debug_macro   0x0000000000000000       0x8d ./Middlewares/Third_Party/LwIP/src/core/timeouts.o
+ .debug_macro   0x0000000000000000       0x7e ./Middlewares/Third_Party/LwIP/src/core/timeouts.o
+ .debug_macro   0x0000000000000000       0x19 ./Middlewares/Third_Party/LwIP/src/core/timeouts.o
+ .debug_macro   0x0000000000000000       0xf2 ./Middlewares/Third_Party/LwIP/src/core/timeouts.o
+ .debug_macro   0x0000000000000000       0x10 ./Middlewares/Third_Party/LwIP/src/core/timeouts.o
+ .debug_macro   0x0000000000000000       0x73 ./Middlewares/Third_Party/LwIP/src/core/timeouts.o
  .debug_macro   0x0000000000000000       0x10 ./Middlewares/Third_Party/LwIP/src/core/timeouts.o
  .debug_macro   0x0000000000000000       0x2e ./Middlewares/Third_Party/LwIP/src/core/timeouts.o
  .debug_macro   0x0000000000000000       0x10 ./Middlewares/Third_Party/LwIP/src/core/timeouts.o
@@ -12166,11 +18795,21 @@ Discarded input sections
  .debug_macro   0x0000000000000000       0xf9 ./Middlewares/Third_Party/LwIP/src/core/timeouts.o
  .debug_macro   0x0000000000000000       0x7c ./Middlewares/Third_Party/LwIP/src/core/timeouts.o
  .debug_macro   0x0000000000000000      0x1d7 ./Middlewares/Third_Party/LwIP/src/core/timeouts.o
+ .debug_macro   0x0000000000000000       0x1c ./Middlewares/Third_Party/LwIP/src/core/timeouts.o
+ .debug_macro   0x0000000000000000       0x4c ./Middlewares/Third_Party/LwIP/src/core/timeouts.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/core/timeouts.o
  .debug_macro   0x0000000000000000       0x46 ./Middlewares/Third_Party/LwIP/src/core/timeouts.o
  .debug_macro   0x0000000000000000       0x22 ./Middlewares/Third_Party/LwIP/src/core/timeouts.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/core/timeouts.o
- .debug_macro   0x0000000000000000       0xe4 ./Middlewares/Third_Party/LwIP/src/core/timeouts.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/udp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/udp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/udp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/udp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/udp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/udp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/udp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/udp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/udp.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/udp.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/udp.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/udp.o
@@ -12298,8 +18937,6 @@ Discarded input sections
  .text          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/core/udp.o
  .data          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/core/udp.o
  .bss           0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/core/udp.o
- .text.udp_new_port
-                0x0000000000000000       0x70 ./Middlewares/Third_Party/LwIP/src/core/udp.o
  .text.udp_send
                 0x0000000000000000       0x68 ./Middlewares/Third_Party/LwIP/src/core/udp.o
  .text.udp_sendto
@@ -12308,23 +18945,12 @@ Discarded input sections
                 0x0000000000000000       0xe8 ./Middlewares/Third_Party/LwIP/src/core/udp.o
  .text.udp_sendto_if_src
                 0x0000000000000000      0x1cc ./Middlewares/Third_Party/LwIP/src/core/udp.o
- .text.udp_bind
-                0x0000000000000000      0x110 ./Middlewares/Third_Party/LwIP/src/core/udp.o
  .text.udp_bind_netif
                 0x0000000000000000       0x32 ./Middlewares/Third_Party/LwIP/src/core/udp.o
- .text.udp_connect
-                0x0000000000000000       0xdc ./Middlewares/Third_Party/LwIP/src/core/udp.o
  .text.udp_disconnect
                 0x0000000000000000       0x50 ./Middlewares/Third_Party/LwIP/src/core/udp.o
- .text.udp_recv
-                0x0000000000000000       0x40 ./Middlewares/Third_Party/LwIP/src/core/udp.o
- .text.udp_remove
-                0x0000000000000000       0x84 ./Middlewares/Third_Party/LwIP/src/core/udp.o
- .text.udp_new  0x0000000000000000       0x2e ./Middlewares/Third_Party/LwIP/src/core/udp.o
- .text.udp_new_ip_type
-                0x0000000000000000       0x1a ./Middlewares/Third_Party/LwIP/src/core/udp.o
  .debug_macro   0x0000000000000000      0xac6 ./Middlewares/Third_Party/LwIP/src/core/udp.o
- .debug_macro   0x0000000000000000      0x232 ./Middlewares/Third_Party/LwIP/src/core/udp.o
+ .debug_macro   0x0000000000000000      0x24a ./Middlewares/Third_Party/LwIP/src/core/udp.o
  .debug_macro   0x0000000000000000       0x2e ./Middlewares/Third_Party/LwIP/src/core/udp.o
  .debug_macro   0x0000000000000000       0x3b ./Middlewares/Third_Party/LwIP/src/core/udp.o
  .debug_macro   0x0000000000000000       0x22 ./Middlewares/Third_Party/LwIP/src/core/udp.o
@@ -12372,6 +18998,7 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x129 ./Middlewares/Third_Party/LwIP/src/core/udp.o
  .debug_macro   0x0000000000000000      0x3f9 ./Middlewares/Third_Party/LwIP/src/core/udp.o
  .debug_macro   0x0000000000000000      0x275 ./Middlewares/Third_Party/LwIP/src/core/udp.o
+ .debug_macro   0x0000000000000000      0xe42 ./Middlewares/Third_Party/LwIP/src/core/udp.o
  .debug_macro   0x0000000000000000      0x3ca ./Middlewares/Third_Party/LwIP/src/core/udp.o
  .debug_macro   0x0000000000000000      0x45c ./Middlewares/Third_Party/LwIP/src/core/udp.o
  .debug_macro   0x0000000000000000       0x3c ./Middlewares/Third_Party/LwIP/src/core/udp.o
@@ -12382,8 +19009,16 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x1c4 ./Middlewares/Third_Party/LwIP/src/core/udp.o
  .debug_macro   0x0000000000000000      0x22a ./Middlewares/Third_Party/LwIP/src/core/udp.o
  .debug_macro   0x0000000000000000       0x35 ./Middlewares/Third_Party/LwIP/src/core/udp.o
+ .debug_macro   0x0000000000000000      0x830 ./Middlewares/Third_Party/LwIP/src/core/udp.o
+ .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/core/udp.o
+ .debug_macro   0x0000000000000000      0x1ce ./Middlewares/Third_Party/LwIP/src/core/udp.o
+ .debug_macro   0x0000000000000000      0xb1d ./Middlewares/Third_Party/LwIP/src/core/udp.o
+ .debug_macro   0x0000000000000000      0x29f ./Middlewares/Third_Party/LwIP/src/core/udp.o
+ .debug_macro   0x0000000000000000      0x693 ./Middlewares/Third_Party/LwIP/src/core/udp.o
+ .debug_macro   0x0000000000000000       0xa6 ./Middlewares/Third_Party/LwIP/src/core/udp.o
  .debug_macro   0x0000000000000000      0x5e6 ./Middlewares/Third_Party/LwIP/src/core/udp.o
- .debug_macro   0x0000000000000000       0xd0 ./Middlewares/Third_Party/LwIP/src/core/udp.o
+ .debug_macro   0x0000000000000000       0x58 ./Middlewares/Third_Party/LwIP/src/core/udp.o
+ .debug_macro   0x0000000000000000       0xe8 ./Middlewares/Third_Party/LwIP/src/core/udp.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/core/udp.o
  .debug_macro   0x0000000000000000       0x10 ./Middlewares/Third_Party/LwIP/src/core/udp.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/core/udp.o
@@ -12423,7 +19058,7 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x11f ./Middlewares/Third_Party/LwIP/src/core/udp.o
  .debug_macro   0x0000000000000000       0x82 ./Middlewares/Third_Party/LwIP/src/core/udp.o
  .debug_macro   0x0000000000000000       0x66 ./Middlewares/Third_Party/LwIP/src/core/udp.o
- .debug_macro   0x0000000000000000      0x756 ./Middlewares/Third_Party/LwIP/src/core/udp.o
+ .debug_macro   0x0000000000000000      0x739 ./Middlewares/Third_Party/LwIP/src/core/udp.o
  .debug_macro   0x0000000000000000       0xad ./Middlewares/Third_Party/LwIP/src/core/udp.o
  .debug_macro   0x0000000000000000       0x10 ./Middlewares/Third_Party/LwIP/src/core/udp.o
  .debug_macro   0x0000000000000000       0x6a ./Middlewares/Third_Party/LwIP/src/core/udp.o
@@ -12548,6 +19183,15 @@ Discarded input sections
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv4/autoip.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv4/autoip.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv4/autoip.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv4/autoip.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv4/autoip.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv4/autoip.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv4/autoip.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv4/autoip.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv4/autoip.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv4/autoip.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv4/autoip.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv4/autoip.o
  .text          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/core/ipv4/autoip.o
  .data          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/core/ipv4/autoip.o
  .bss           0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/core/ipv4/autoip.o
@@ -12555,9 +19199,9 @@ Discarded input sections
  .debug_abbrev  0x0000000000000000       0x28 ./Middlewares/Third_Party/LwIP/src/core/ipv4/autoip.o
  .debug_aranges
                 0x0000000000000000       0x18 ./Middlewares/Third_Party/LwIP/src/core/ipv4/autoip.o
- .debug_macro   0x0000000000000000      0x4a3 ./Middlewares/Third_Party/LwIP/src/core/ipv4/autoip.o
+ .debug_macro   0x0000000000000000      0x507 ./Middlewares/Third_Party/LwIP/src/core/ipv4/autoip.o
  .debug_macro   0x0000000000000000      0xac6 ./Middlewares/Third_Party/LwIP/src/core/ipv4/autoip.o
- .debug_macro   0x0000000000000000      0x232 ./Middlewares/Third_Party/LwIP/src/core/ipv4/autoip.o
+ .debug_macro   0x0000000000000000      0x24a ./Middlewares/Third_Party/LwIP/src/core/ipv4/autoip.o
  .debug_macro   0x0000000000000000       0x2e ./Middlewares/Third_Party/LwIP/src/core/ipv4/autoip.o
  .debug_macro   0x0000000000000000       0x3b ./Middlewares/Third_Party/LwIP/src/core/ipv4/autoip.o
  .debug_macro   0x0000000000000000       0x22 ./Middlewares/Third_Party/LwIP/src/core/ipv4/autoip.o
@@ -12605,6 +19249,7 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x129 ./Middlewares/Third_Party/LwIP/src/core/ipv4/autoip.o
  .debug_macro   0x0000000000000000      0x3f9 ./Middlewares/Third_Party/LwIP/src/core/ipv4/autoip.o
  .debug_macro   0x0000000000000000      0x275 ./Middlewares/Third_Party/LwIP/src/core/ipv4/autoip.o
+ .debug_macro   0x0000000000000000      0xe42 ./Middlewares/Third_Party/LwIP/src/core/ipv4/autoip.o
  .debug_macro   0x0000000000000000      0x3ca ./Middlewares/Third_Party/LwIP/src/core/ipv4/autoip.o
  .debug_macro   0x0000000000000000      0x45c ./Middlewares/Third_Party/LwIP/src/core/ipv4/autoip.o
  .debug_macro   0x0000000000000000       0x3c ./Middlewares/Third_Party/LwIP/src/core/ipv4/autoip.o
@@ -12615,8 +19260,16 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x1c4 ./Middlewares/Third_Party/LwIP/src/core/ipv4/autoip.o
  .debug_macro   0x0000000000000000      0x22a ./Middlewares/Third_Party/LwIP/src/core/ipv4/autoip.o
  .debug_macro   0x0000000000000000       0x35 ./Middlewares/Third_Party/LwIP/src/core/ipv4/autoip.o
+ .debug_macro   0x0000000000000000      0x830 ./Middlewares/Third_Party/LwIP/src/core/ipv4/autoip.o
+ .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/core/ipv4/autoip.o
+ .debug_macro   0x0000000000000000      0x1ce ./Middlewares/Third_Party/LwIP/src/core/ipv4/autoip.o
+ .debug_macro   0x0000000000000000      0xb1d ./Middlewares/Third_Party/LwIP/src/core/ipv4/autoip.o
+ .debug_macro   0x0000000000000000      0x29f ./Middlewares/Third_Party/LwIP/src/core/ipv4/autoip.o
+ .debug_macro   0x0000000000000000      0x693 ./Middlewares/Third_Party/LwIP/src/core/ipv4/autoip.o
+ .debug_macro   0x0000000000000000       0xa6 ./Middlewares/Third_Party/LwIP/src/core/ipv4/autoip.o
  .debug_macro   0x0000000000000000      0x5e6 ./Middlewares/Third_Party/LwIP/src/core/ipv4/autoip.o
- .debug_macro   0x0000000000000000       0xd0 ./Middlewares/Third_Party/LwIP/src/core/ipv4/autoip.o
+ .debug_macro   0x0000000000000000       0x58 ./Middlewares/Third_Party/LwIP/src/core/ipv4/autoip.o
+ .debug_macro   0x0000000000000000       0xe8 ./Middlewares/Third_Party/LwIP/src/core/ipv4/autoip.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/core/ipv4/autoip.o
  .debug_macro   0x0000000000000000       0x10 ./Middlewares/Third_Party/LwIP/src/core/ipv4/autoip.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/core/ipv4/autoip.o
@@ -12656,9 +19309,9 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x11f ./Middlewares/Third_Party/LwIP/src/core/ipv4/autoip.o
  .debug_macro   0x0000000000000000       0x82 ./Middlewares/Third_Party/LwIP/src/core/ipv4/autoip.o
  .debug_macro   0x0000000000000000       0x66 ./Middlewares/Third_Party/LwIP/src/core/ipv4/autoip.o
- .debug_macro   0x0000000000000000      0x756 ./Middlewares/Third_Party/LwIP/src/core/ipv4/autoip.o
- .debug_line    0x0000000000000000      0xb7c ./Middlewares/Third_Party/LwIP/src/core/ipv4/autoip.o
- .debug_str     0x0000000000000000   0x13e82b ./Middlewares/Third_Party/LwIP/src/core/ipv4/autoip.o
+ .debug_macro   0x0000000000000000      0x739 ./Middlewares/Third_Party/LwIP/src/core/ipv4/autoip.o
+ .debug_line    0x0000000000000000      0xc5d ./Middlewares/Third_Party/LwIP/src/core/ipv4/autoip.o
+ .debug_str     0x0000000000000000   0x15d09f ./Middlewares/Third_Party/LwIP/src/core/ipv4/autoip.o
  .comment       0x0000000000000000       0x44 ./Middlewares/Third_Party/LwIP/src/core/ipv4/autoip.o
  .ARM.attributes
                 0x0000000000000000       0x32 ./Middlewares/Third_Party/LwIP/src/core/ipv4/autoip.o
@@ -12763,6 +19416,15 @@ Discarded input sections
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.o
  .text          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.o
  .data          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.o
  .bss           0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.o
@@ -12770,9 +19432,9 @@ Discarded input sections
  .debug_abbrev  0x0000000000000000       0x28 ./Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.o
  .debug_aranges
                 0x0000000000000000       0x18 ./Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.o
- .debug_macro   0x0000000000000000      0x4a3 ./Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.o
+ .debug_macro   0x0000000000000000      0x507 ./Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.o
  .debug_macro   0x0000000000000000      0xac6 ./Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.o
- .debug_macro   0x0000000000000000      0x232 ./Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.o
+ .debug_macro   0x0000000000000000      0x24a ./Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.o
  .debug_macro   0x0000000000000000       0x2e ./Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.o
  .debug_macro   0x0000000000000000       0x3b ./Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.o
  .debug_macro   0x0000000000000000       0x22 ./Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.o
@@ -12820,6 +19482,7 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x129 ./Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.o
  .debug_macro   0x0000000000000000      0x3f9 ./Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.o
  .debug_macro   0x0000000000000000      0x275 ./Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.o
+ .debug_macro   0x0000000000000000      0xe42 ./Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.o
  .debug_macro   0x0000000000000000      0x3ca ./Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.o
  .debug_macro   0x0000000000000000      0x45c ./Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.o
  .debug_macro   0x0000000000000000       0x3c ./Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.o
@@ -12830,8 +19493,16 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x1c4 ./Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.o
  .debug_macro   0x0000000000000000      0x22a ./Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.o
  .debug_macro   0x0000000000000000       0x35 ./Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.o
+ .debug_macro   0x0000000000000000      0x830 ./Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.o
+ .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.o
+ .debug_macro   0x0000000000000000      0x1ce ./Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.o
+ .debug_macro   0x0000000000000000      0xb1d ./Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.o
+ .debug_macro   0x0000000000000000      0x29f ./Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.o
+ .debug_macro   0x0000000000000000      0x693 ./Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.o
+ .debug_macro   0x0000000000000000       0xa6 ./Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.o
  .debug_macro   0x0000000000000000      0x5e6 ./Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.o
- .debug_macro   0x0000000000000000       0xd0 ./Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.o
+ .debug_macro   0x0000000000000000       0x58 ./Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.o
+ .debug_macro   0x0000000000000000       0xe8 ./Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.o
  .debug_macro   0x0000000000000000       0x10 ./Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.o
@@ -12871,9 +19542,9 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x11f ./Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.o
  .debug_macro   0x0000000000000000       0x82 ./Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.o
  .debug_macro   0x0000000000000000       0x66 ./Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.o
- .debug_macro   0x0000000000000000      0x756 ./Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.o
- .debug_line    0x0000000000000000      0xb7a ./Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.o
- .debug_str     0x0000000000000000   0x13e829 ./Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.o
+ .debug_macro   0x0000000000000000      0x739 ./Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.o
+ .debug_line    0x0000000000000000      0xc5b ./Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.o
+ .debug_str     0x0000000000000000   0x15d09d ./Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.o
  .comment       0x0000000000000000       0x44 ./Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.o
  .ARM.attributes
                 0x0000000000000000       0x32 ./Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.o
@@ -12999,6 +19670,15 @@ Discarded input sections
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.o
  .text          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.o
  .data          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.o
  .bss           0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.o
@@ -13007,7 +19687,7 @@ Discarded input sections
  .text.etharp_get_entry
                 0x0000000000000000       0xcc ./Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.o
  .debug_macro   0x0000000000000000      0xac6 ./Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.o
- .debug_macro   0x0000000000000000      0x232 ./Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.o
+ .debug_macro   0x0000000000000000      0x24a ./Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.o
  .debug_macro   0x0000000000000000       0x2e ./Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.o
  .debug_macro   0x0000000000000000       0x3b ./Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.o
  .debug_macro   0x0000000000000000       0x22 ./Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.o
@@ -13055,6 +19735,7 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x129 ./Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.o
  .debug_macro   0x0000000000000000      0x3f9 ./Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.o
  .debug_macro   0x0000000000000000      0x275 ./Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.o
+ .debug_macro   0x0000000000000000      0xe42 ./Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.o
  .debug_macro   0x0000000000000000      0x3ca ./Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.o
  .debug_macro   0x0000000000000000      0x45c ./Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.o
  .debug_macro   0x0000000000000000       0x3c ./Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.o
@@ -13065,8 +19746,16 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x1c4 ./Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.o
  .debug_macro   0x0000000000000000      0x22a ./Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.o
  .debug_macro   0x0000000000000000       0x35 ./Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.o
+ .debug_macro   0x0000000000000000      0x830 ./Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.o
+ .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.o
+ .debug_macro   0x0000000000000000      0x1ce ./Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.o
+ .debug_macro   0x0000000000000000      0xb1d ./Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.o
+ .debug_macro   0x0000000000000000      0x29f ./Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.o
+ .debug_macro   0x0000000000000000      0x693 ./Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.o
+ .debug_macro   0x0000000000000000       0xa6 ./Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.o
  .debug_macro   0x0000000000000000      0x5e6 ./Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.o
- .debug_macro   0x0000000000000000       0xd0 ./Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.o
+ .debug_macro   0x0000000000000000       0x58 ./Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.o
+ .debug_macro   0x0000000000000000       0xe8 ./Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.o
  .debug_macro   0x0000000000000000       0x10 ./Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.o
@@ -13106,7 +19795,7 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x11f ./Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.o
  .debug_macro   0x0000000000000000       0x82 ./Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.o
  .debug_macro   0x0000000000000000       0x66 ./Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.o
- .debug_macro   0x0000000000000000      0x756 ./Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.o
+ .debug_macro   0x0000000000000000      0x739 ./Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.o
  .debug_macro   0x0000000000000000       0xad ./Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.o
  .debug_macro   0x0000000000000000       0x6a ./Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.o
  .debug_macro   0x0000000000000000      0x1bd ./Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.o
@@ -13249,11 +19938,20 @@ Discarded input sections
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.o
  .text          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.o
  .data          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.o
  .bss           0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.o
  .debug_macro   0x0000000000000000      0xac6 ./Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.o
- .debug_macro   0x0000000000000000      0x232 ./Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.o
+ .debug_macro   0x0000000000000000      0x24a ./Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.o
  .debug_macro   0x0000000000000000       0x2e ./Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.o
  .debug_macro   0x0000000000000000       0x3b ./Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.o
  .debug_macro   0x0000000000000000       0x22 ./Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.o
@@ -13301,6 +19999,7 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x129 ./Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.o
  .debug_macro   0x0000000000000000      0x3f9 ./Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.o
  .debug_macro   0x0000000000000000      0x275 ./Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.o
+ .debug_macro   0x0000000000000000      0xe42 ./Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.o
  .debug_macro   0x0000000000000000      0x3ca ./Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.o
  .debug_macro   0x0000000000000000      0x45c ./Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.o
  .debug_macro   0x0000000000000000       0x3c ./Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.o
@@ -13311,8 +20010,16 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x1c4 ./Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.o
  .debug_macro   0x0000000000000000      0x22a ./Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.o
  .debug_macro   0x0000000000000000       0x35 ./Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.o
+ .debug_macro   0x0000000000000000      0x830 ./Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.o
+ .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.o
+ .debug_macro   0x0000000000000000      0x1ce ./Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.o
+ .debug_macro   0x0000000000000000      0xb1d ./Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.o
+ .debug_macro   0x0000000000000000      0x29f ./Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.o
+ .debug_macro   0x0000000000000000      0x693 ./Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.o
+ .debug_macro   0x0000000000000000       0xa6 ./Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.o
  .debug_macro   0x0000000000000000      0x5e6 ./Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.o
- .debug_macro   0x0000000000000000       0xd0 ./Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.o
+ .debug_macro   0x0000000000000000       0x58 ./Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.o
+ .debug_macro   0x0000000000000000       0xe8 ./Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.o
  .debug_macro   0x0000000000000000       0x10 ./Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.o
@@ -13352,7 +20059,7 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x11f ./Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.o
  .debug_macro   0x0000000000000000       0x82 ./Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.o
  .debug_macro   0x0000000000000000       0x66 ./Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.o
- .debug_macro   0x0000000000000000      0x756 ./Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.o
+ .debug_macro   0x0000000000000000      0x739 ./Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.o
  .debug_macro   0x0000000000000000       0xad ./Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.o
  .debug_macro   0x0000000000000000       0x6a ./Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.o
  .debug_macro   0x0000000000000000      0x1c3 ./Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.o
@@ -13474,6 +20181,15 @@ Discarded input sections
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv4/igmp.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv4/igmp.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv4/igmp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv4/igmp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv4/igmp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv4/igmp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv4/igmp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv4/igmp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv4/igmp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv4/igmp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv4/igmp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv4/igmp.o
  .text          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/core/ipv4/igmp.o
  .data          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/core/ipv4/igmp.o
  .bss           0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/core/ipv4/igmp.o
@@ -13481,9 +20197,9 @@ Discarded input sections
  .debug_abbrev  0x0000000000000000       0x28 ./Middlewares/Third_Party/LwIP/src/core/ipv4/igmp.o
  .debug_aranges
                 0x0000000000000000       0x18 ./Middlewares/Third_Party/LwIP/src/core/ipv4/igmp.o
- .debug_macro   0x0000000000000000      0x4a3 ./Middlewares/Third_Party/LwIP/src/core/ipv4/igmp.o
+ .debug_macro   0x0000000000000000      0x507 ./Middlewares/Third_Party/LwIP/src/core/ipv4/igmp.o
  .debug_macro   0x0000000000000000      0xac6 ./Middlewares/Third_Party/LwIP/src/core/ipv4/igmp.o
- .debug_macro   0x0000000000000000      0x232 ./Middlewares/Third_Party/LwIP/src/core/ipv4/igmp.o
+ .debug_macro   0x0000000000000000      0x24a ./Middlewares/Third_Party/LwIP/src/core/ipv4/igmp.o
  .debug_macro   0x0000000000000000       0x2e ./Middlewares/Third_Party/LwIP/src/core/ipv4/igmp.o
  .debug_macro   0x0000000000000000       0x3b ./Middlewares/Third_Party/LwIP/src/core/ipv4/igmp.o
  .debug_macro   0x0000000000000000       0x22 ./Middlewares/Third_Party/LwIP/src/core/ipv4/igmp.o
@@ -13531,6 +20247,7 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x129 ./Middlewares/Third_Party/LwIP/src/core/ipv4/igmp.o
  .debug_macro   0x0000000000000000      0x3f9 ./Middlewares/Third_Party/LwIP/src/core/ipv4/igmp.o
  .debug_macro   0x0000000000000000      0x275 ./Middlewares/Third_Party/LwIP/src/core/ipv4/igmp.o
+ .debug_macro   0x0000000000000000      0xe42 ./Middlewares/Third_Party/LwIP/src/core/ipv4/igmp.o
  .debug_macro   0x0000000000000000      0x3ca ./Middlewares/Third_Party/LwIP/src/core/ipv4/igmp.o
  .debug_macro   0x0000000000000000      0x45c ./Middlewares/Third_Party/LwIP/src/core/ipv4/igmp.o
  .debug_macro   0x0000000000000000       0x3c ./Middlewares/Third_Party/LwIP/src/core/ipv4/igmp.o
@@ -13541,8 +20258,16 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x1c4 ./Middlewares/Third_Party/LwIP/src/core/ipv4/igmp.o
  .debug_macro   0x0000000000000000      0x22a ./Middlewares/Third_Party/LwIP/src/core/ipv4/igmp.o
  .debug_macro   0x0000000000000000       0x35 ./Middlewares/Third_Party/LwIP/src/core/ipv4/igmp.o
+ .debug_macro   0x0000000000000000      0x830 ./Middlewares/Third_Party/LwIP/src/core/ipv4/igmp.o
+ .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/core/ipv4/igmp.o
+ .debug_macro   0x0000000000000000      0x1ce ./Middlewares/Third_Party/LwIP/src/core/ipv4/igmp.o
+ .debug_macro   0x0000000000000000      0xb1d ./Middlewares/Third_Party/LwIP/src/core/ipv4/igmp.o
+ .debug_macro   0x0000000000000000      0x29f ./Middlewares/Third_Party/LwIP/src/core/ipv4/igmp.o
+ .debug_macro   0x0000000000000000      0x693 ./Middlewares/Third_Party/LwIP/src/core/ipv4/igmp.o
+ .debug_macro   0x0000000000000000       0xa6 ./Middlewares/Third_Party/LwIP/src/core/ipv4/igmp.o
  .debug_macro   0x0000000000000000      0x5e6 ./Middlewares/Third_Party/LwIP/src/core/ipv4/igmp.o
- .debug_macro   0x0000000000000000       0xd0 ./Middlewares/Third_Party/LwIP/src/core/ipv4/igmp.o
+ .debug_macro   0x0000000000000000       0x58 ./Middlewares/Third_Party/LwIP/src/core/ipv4/igmp.o
+ .debug_macro   0x0000000000000000       0xe8 ./Middlewares/Third_Party/LwIP/src/core/ipv4/igmp.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/core/ipv4/igmp.o
  .debug_macro   0x0000000000000000       0x10 ./Middlewares/Third_Party/LwIP/src/core/ipv4/igmp.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/core/ipv4/igmp.o
@@ -13582,9 +20307,9 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x11f ./Middlewares/Third_Party/LwIP/src/core/ipv4/igmp.o
  .debug_macro   0x0000000000000000       0x82 ./Middlewares/Third_Party/LwIP/src/core/ipv4/igmp.o
  .debug_macro   0x0000000000000000       0x66 ./Middlewares/Third_Party/LwIP/src/core/ipv4/igmp.o
- .debug_macro   0x0000000000000000      0x756 ./Middlewares/Third_Party/LwIP/src/core/ipv4/igmp.o
- .debug_line    0x0000000000000000      0xb7a ./Middlewares/Third_Party/LwIP/src/core/ipv4/igmp.o
- .debug_str     0x0000000000000000   0x13e829 ./Middlewares/Third_Party/LwIP/src/core/ipv4/igmp.o
+ .debug_macro   0x0000000000000000      0x739 ./Middlewares/Third_Party/LwIP/src/core/ipv4/igmp.o
+ .debug_line    0x0000000000000000      0xc5b ./Middlewares/Third_Party/LwIP/src/core/ipv4/igmp.o
+ .debug_str     0x0000000000000000   0x15d09d ./Middlewares/Third_Party/LwIP/src/core/ipv4/igmp.o
  .comment       0x0000000000000000       0x44 ./Middlewares/Third_Party/LwIP/src/core/ipv4/igmp.o
  .ARM.attributes
                 0x0000000000000000       0x32 ./Middlewares/Third_Party/LwIP/src/core/ipv4/igmp.o
@@ -13716,13 +20441,22 @@ Discarded input sections
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.o
  .text          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.o
  .data          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.o
  .bss           0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.o
  .text.ip4_output
                 0x0000000000000000       0x6c ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.o
  .debug_macro   0x0000000000000000      0xac6 ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.o
- .debug_macro   0x0000000000000000      0x232 ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.o
+ .debug_macro   0x0000000000000000      0x24a ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.o
  .debug_macro   0x0000000000000000       0x2e ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.o
  .debug_macro   0x0000000000000000       0x3b ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.o
  .debug_macro   0x0000000000000000       0x22 ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.o
@@ -13770,6 +20504,7 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x129 ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.o
  .debug_macro   0x0000000000000000      0x3f9 ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.o
  .debug_macro   0x0000000000000000      0x275 ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.o
+ .debug_macro   0x0000000000000000      0xe42 ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.o
  .debug_macro   0x0000000000000000      0x3ca ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.o
  .debug_macro   0x0000000000000000      0x45c ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.o
  .debug_macro   0x0000000000000000       0x3c ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.o
@@ -13780,8 +20515,16 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x1c4 ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.o
  .debug_macro   0x0000000000000000      0x22a ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.o
  .debug_macro   0x0000000000000000       0x35 ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.o
+ .debug_macro   0x0000000000000000      0x830 ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.o
+ .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.o
+ .debug_macro   0x0000000000000000      0x1ce ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.o
+ .debug_macro   0x0000000000000000      0xb1d ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.o
+ .debug_macro   0x0000000000000000      0x29f ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.o
+ .debug_macro   0x0000000000000000      0x693 ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.o
+ .debug_macro   0x0000000000000000       0xa6 ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.o
  .debug_macro   0x0000000000000000      0x5e6 ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.o
- .debug_macro   0x0000000000000000       0xd0 ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.o
+ .debug_macro   0x0000000000000000       0x58 ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.o
+ .debug_macro   0x0000000000000000       0xe8 ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.o
  .debug_macro   0x0000000000000000       0x10 ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.o
@@ -13821,7 +20564,7 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x11f ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.o
  .debug_macro   0x0000000000000000       0x82 ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.o
  .debug_macro   0x0000000000000000       0x66 ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.o
- .debug_macro   0x0000000000000000      0x756 ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.o
+ .debug_macro   0x0000000000000000      0x739 ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.o
  .debug_macro   0x0000000000000000       0x6a ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.o
  .debug_macro   0x0000000000000000       0xad ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.o
  .debug_macro   0x0000000000000000      0x1c3 ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.o
@@ -13962,6 +20705,15 @@ Discarded input sections
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.o
  .text          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.o
  .data          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.o
  .bss           0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.o
@@ -13980,7 +20732,7 @@ Discarded input sections
                 0x0000000000000000      0x100 ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.o
  .bss.str.0     0x0000000000000000       0x10 ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.o
  .debug_macro   0x0000000000000000      0xac6 ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.o
- .debug_macro   0x0000000000000000      0x232 ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.o
+ .debug_macro   0x0000000000000000      0x24a ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.o
  .debug_macro   0x0000000000000000       0x2e ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.o
  .debug_macro   0x0000000000000000       0x3b ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.o
  .debug_macro   0x0000000000000000       0x22 ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.o
@@ -14028,6 +20780,7 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x129 ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.o
  .debug_macro   0x0000000000000000      0x3f9 ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.o
  .debug_macro   0x0000000000000000      0x275 ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.o
+ .debug_macro   0x0000000000000000      0xe42 ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.o
  .debug_macro   0x0000000000000000      0x3ca ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.o
  .debug_macro   0x0000000000000000      0x45c ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.o
  .debug_macro   0x0000000000000000       0x3c ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.o
@@ -14038,8 +20791,16 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x1c4 ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.o
  .debug_macro   0x0000000000000000      0x22a ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.o
  .debug_macro   0x0000000000000000       0x35 ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.o
+ .debug_macro   0x0000000000000000      0x830 ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.o
+ .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.o
+ .debug_macro   0x0000000000000000      0x1ce ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.o
+ .debug_macro   0x0000000000000000      0xb1d ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.o
+ .debug_macro   0x0000000000000000      0x29f ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.o
+ .debug_macro   0x0000000000000000      0x693 ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.o
+ .debug_macro   0x0000000000000000       0xa6 ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.o
  .debug_macro   0x0000000000000000      0x5e6 ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.o
- .debug_macro   0x0000000000000000       0xd0 ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.o
+ .debug_macro   0x0000000000000000       0x58 ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.o
+ .debug_macro   0x0000000000000000       0xe8 ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.o
  .debug_macro   0x0000000000000000       0x10 ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.o
@@ -14079,7 +20840,7 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x11f ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.o
  .debug_macro   0x0000000000000000       0x82 ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.o
  .debug_macro   0x0000000000000000       0x66 ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.o
- .debug_macro   0x0000000000000000      0x756 ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.o
+ .debug_macro   0x0000000000000000      0x739 ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.o
  .debug_macro   0x0000000000000000       0x6a ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.o
  .debug_macro   0x0000000000000000      0x1c3 ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.o
  .debug_macro   0x0000000000000000      0x169 ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.o
@@ -14214,11 +20975,20 @@ Discarded input sections
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.o
  .text          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.o
  .data          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.o
  .bss           0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.o
  .debug_macro   0x0000000000000000      0xac6 ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.o
- .debug_macro   0x0000000000000000      0x232 ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.o
+ .debug_macro   0x0000000000000000      0x24a ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.o
  .debug_macro   0x0000000000000000       0x2e ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.o
  .debug_macro   0x0000000000000000       0x3b ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.o
  .debug_macro   0x0000000000000000       0x22 ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.o
@@ -14266,6 +21036,7 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x129 ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.o
  .debug_macro   0x0000000000000000      0x3f9 ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.o
  .debug_macro   0x0000000000000000      0x275 ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.o
+ .debug_macro   0x0000000000000000      0xe42 ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.o
  .debug_macro   0x0000000000000000      0x3ca ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.o
  .debug_macro   0x0000000000000000      0x45c ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.o
  .debug_macro   0x0000000000000000       0x3c ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.o
@@ -14276,8 +21047,16 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x1c4 ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.o
  .debug_macro   0x0000000000000000      0x22a ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.o
  .debug_macro   0x0000000000000000       0x35 ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.o
+ .debug_macro   0x0000000000000000      0x830 ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.o
+ .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.o
+ .debug_macro   0x0000000000000000      0x1ce ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.o
+ .debug_macro   0x0000000000000000      0xb1d ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.o
+ .debug_macro   0x0000000000000000      0x29f ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.o
+ .debug_macro   0x0000000000000000      0x693 ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.o
+ .debug_macro   0x0000000000000000       0xa6 ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.o
  .debug_macro   0x0000000000000000      0x5e6 ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.o
- .debug_macro   0x0000000000000000       0xd0 ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.o
+ .debug_macro   0x0000000000000000       0x58 ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.o
+ .debug_macro   0x0000000000000000       0xe8 ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.o
  .debug_macro   0x0000000000000000       0x10 ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.o
@@ -14317,7 +21096,7 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x11f ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.o
  .debug_macro   0x0000000000000000       0x82 ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.o
  .debug_macro   0x0000000000000000       0x66 ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.o
- .debug_macro   0x0000000000000000      0x756 ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.o
+ .debug_macro   0x0000000000000000      0x739 ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.o
  .debug_macro   0x0000000000000000       0xb3 ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.o
  .debug_macro   0x0000000000000000       0x10 ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.o
  .debug_macro   0x0000000000000000       0x6a ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.o
@@ -14439,6 +21218,15 @@ Discarded input sections
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv6/dhcp6.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv6/dhcp6.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv6/dhcp6.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv6/dhcp6.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv6/dhcp6.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv6/dhcp6.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv6/dhcp6.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv6/dhcp6.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv6/dhcp6.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv6/dhcp6.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv6/dhcp6.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv6/dhcp6.o
  .text          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/core/ipv6/dhcp6.o
  .data          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/core/ipv6/dhcp6.o
  .bss           0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/core/ipv6/dhcp6.o
@@ -14446,9 +21234,9 @@ Discarded input sections
  .debug_abbrev  0x0000000000000000       0x28 ./Middlewares/Third_Party/LwIP/src/core/ipv6/dhcp6.o
  .debug_aranges
                 0x0000000000000000       0x18 ./Middlewares/Third_Party/LwIP/src/core/ipv6/dhcp6.o
- .debug_macro   0x0000000000000000      0x4a3 ./Middlewares/Third_Party/LwIP/src/core/ipv6/dhcp6.o
+ .debug_macro   0x0000000000000000      0x507 ./Middlewares/Third_Party/LwIP/src/core/ipv6/dhcp6.o
  .debug_macro   0x0000000000000000      0xac6 ./Middlewares/Third_Party/LwIP/src/core/ipv6/dhcp6.o
- .debug_macro   0x0000000000000000      0x232 ./Middlewares/Third_Party/LwIP/src/core/ipv6/dhcp6.o
+ .debug_macro   0x0000000000000000      0x24a ./Middlewares/Third_Party/LwIP/src/core/ipv6/dhcp6.o
  .debug_macro   0x0000000000000000       0x2e ./Middlewares/Third_Party/LwIP/src/core/ipv6/dhcp6.o
  .debug_macro   0x0000000000000000       0x3b ./Middlewares/Third_Party/LwIP/src/core/ipv6/dhcp6.o
  .debug_macro   0x0000000000000000       0x22 ./Middlewares/Third_Party/LwIP/src/core/ipv6/dhcp6.o
@@ -14496,6 +21284,7 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x129 ./Middlewares/Third_Party/LwIP/src/core/ipv6/dhcp6.o
  .debug_macro   0x0000000000000000      0x3f9 ./Middlewares/Third_Party/LwIP/src/core/ipv6/dhcp6.o
  .debug_macro   0x0000000000000000      0x275 ./Middlewares/Third_Party/LwIP/src/core/ipv6/dhcp6.o
+ .debug_macro   0x0000000000000000      0xe42 ./Middlewares/Third_Party/LwIP/src/core/ipv6/dhcp6.o
  .debug_macro   0x0000000000000000      0x3ca ./Middlewares/Third_Party/LwIP/src/core/ipv6/dhcp6.o
  .debug_macro   0x0000000000000000      0x45c ./Middlewares/Third_Party/LwIP/src/core/ipv6/dhcp6.o
  .debug_macro   0x0000000000000000       0x3c ./Middlewares/Third_Party/LwIP/src/core/ipv6/dhcp6.o
@@ -14506,8 +21295,16 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x1c4 ./Middlewares/Third_Party/LwIP/src/core/ipv6/dhcp6.o
  .debug_macro   0x0000000000000000      0x22a ./Middlewares/Third_Party/LwIP/src/core/ipv6/dhcp6.o
  .debug_macro   0x0000000000000000       0x35 ./Middlewares/Third_Party/LwIP/src/core/ipv6/dhcp6.o
+ .debug_macro   0x0000000000000000      0x830 ./Middlewares/Third_Party/LwIP/src/core/ipv6/dhcp6.o
+ .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/core/ipv6/dhcp6.o
+ .debug_macro   0x0000000000000000      0x1ce ./Middlewares/Third_Party/LwIP/src/core/ipv6/dhcp6.o
+ .debug_macro   0x0000000000000000      0xb1d ./Middlewares/Third_Party/LwIP/src/core/ipv6/dhcp6.o
+ .debug_macro   0x0000000000000000      0x29f ./Middlewares/Third_Party/LwIP/src/core/ipv6/dhcp6.o
+ .debug_macro   0x0000000000000000      0x693 ./Middlewares/Third_Party/LwIP/src/core/ipv6/dhcp6.o
+ .debug_macro   0x0000000000000000       0xa6 ./Middlewares/Third_Party/LwIP/src/core/ipv6/dhcp6.o
  .debug_macro   0x0000000000000000      0x5e6 ./Middlewares/Third_Party/LwIP/src/core/ipv6/dhcp6.o
- .debug_macro   0x0000000000000000       0xd0 ./Middlewares/Third_Party/LwIP/src/core/ipv6/dhcp6.o
+ .debug_macro   0x0000000000000000       0x58 ./Middlewares/Third_Party/LwIP/src/core/ipv6/dhcp6.o
+ .debug_macro   0x0000000000000000       0xe8 ./Middlewares/Third_Party/LwIP/src/core/ipv6/dhcp6.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/core/ipv6/dhcp6.o
  .debug_macro   0x0000000000000000       0x10 ./Middlewares/Third_Party/LwIP/src/core/ipv6/dhcp6.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/core/ipv6/dhcp6.o
@@ -14547,9 +21344,9 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x11f ./Middlewares/Third_Party/LwIP/src/core/ipv6/dhcp6.o
  .debug_macro   0x0000000000000000       0x82 ./Middlewares/Third_Party/LwIP/src/core/ipv6/dhcp6.o
  .debug_macro   0x0000000000000000       0x66 ./Middlewares/Third_Party/LwIP/src/core/ipv6/dhcp6.o
- .debug_macro   0x0000000000000000      0x756 ./Middlewares/Third_Party/LwIP/src/core/ipv6/dhcp6.o
- .debug_line    0x0000000000000000      0xb7b ./Middlewares/Third_Party/LwIP/src/core/ipv6/dhcp6.o
- .debug_str     0x0000000000000000   0x13e82a ./Middlewares/Third_Party/LwIP/src/core/ipv6/dhcp6.o
+ .debug_macro   0x0000000000000000      0x739 ./Middlewares/Third_Party/LwIP/src/core/ipv6/dhcp6.o
+ .debug_line    0x0000000000000000      0xc5c ./Middlewares/Third_Party/LwIP/src/core/ipv6/dhcp6.o
+ .debug_str     0x0000000000000000   0x15d09e ./Middlewares/Third_Party/LwIP/src/core/ipv6/dhcp6.o
  .comment       0x0000000000000000       0x44 ./Middlewares/Third_Party/LwIP/src/core/ipv6/dhcp6.o
  .ARM.attributes
                 0x0000000000000000       0x32 ./Middlewares/Third_Party/LwIP/src/core/ipv6/dhcp6.o
@@ -14654,6 +21451,15 @@ Discarded input sections
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv6/ethip6.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv6/ethip6.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv6/ethip6.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv6/ethip6.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv6/ethip6.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv6/ethip6.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv6/ethip6.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv6/ethip6.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv6/ethip6.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv6/ethip6.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv6/ethip6.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv6/ethip6.o
  .text          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ethip6.o
  .data          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ethip6.o
  .bss           0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ethip6.o
@@ -14661,9 +21467,9 @@ Discarded input sections
  .debug_abbrev  0x0000000000000000       0x28 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ethip6.o
  .debug_aranges
                 0x0000000000000000       0x18 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ethip6.o
- .debug_macro   0x0000000000000000      0x4a3 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ethip6.o
+ .debug_macro   0x0000000000000000      0x507 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ethip6.o
  .debug_macro   0x0000000000000000      0xac6 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ethip6.o
- .debug_macro   0x0000000000000000      0x232 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ethip6.o
+ .debug_macro   0x0000000000000000      0x24a ./Middlewares/Third_Party/LwIP/src/core/ipv6/ethip6.o
  .debug_macro   0x0000000000000000       0x2e ./Middlewares/Third_Party/LwIP/src/core/ipv6/ethip6.o
  .debug_macro   0x0000000000000000       0x3b ./Middlewares/Third_Party/LwIP/src/core/ipv6/ethip6.o
  .debug_macro   0x0000000000000000       0x22 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ethip6.o
@@ -14711,6 +21517,7 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x129 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ethip6.o
  .debug_macro   0x0000000000000000      0x3f9 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ethip6.o
  .debug_macro   0x0000000000000000      0x275 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ethip6.o
+ .debug_macro   0x0000000000000000      0xe42 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ethip6.o
  .debug_macro   0x0000000000000000      0x3ca ./Middlewares/Third_Party/LwIP/src/core/ipv6/ethip6.o
  .debug_macro   0x0000000000000000      0x45c ./Middlewares/Third_Party/LwIP/src/core/ipv6/ethip6.o
  .debug_macro   0x0000000000000000       0x3c ./Middlewares/Third_Party/LwIP/src/core/ipv6/ethip6.o
@@ -14721,8 +21528,16 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x1c4 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ethip6.o
  .debug_macro   0x0000000000000000      0x22a ./Middlewares/Third_Party/LwIP/src/core/ipv6/ethip6.o
  .debug_macro   0x0000000000000000       0x35 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ethip6.o
+ .debug_macro   0x0000000000000000      0x830 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ethip6.o
+ .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ethip6.o
+ .debug_macro   0x0000000000000000      0x1ce ./Middlewares/Third_Party/LwIP/src/core/ipv6/ethip6.o
+ .debug_macro   0x0000000000000000      0xb1d ./Middlewares/Third_Party/LwIP/src/core/ipv6/ethip6.o
+ .debug_macro   0x0000000000000000      0x29f ./Middlewares/Third_Party/LwIP/src/core/ipv6/ethip6.o
+ .debug_macro   0x0000000000000000      0x693 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ethip6.o
+ .debug_macro   0x0000000000000000       0xa6 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ethip6.o
  .debug_macro   0x0000000000000000      0x5e6 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ethip6.o
- .debug_macro   0x0000000000000000       0xd0 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ethip6.o
+ .debug_macro   0x0000000000000000       0x58 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ethip6.o
+ .debug_macro   0x0000000000000000       0xe8 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ethip6.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ethip6.o
  .debug_macro   0x0000000000000000       0x10 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ethip6.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ethip6.o
@@ -14762,9 +21577,9 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x11f ./Middlewares/Third_Party/LwIP/src/core/ipv6/ethip6.o
  .debug_macro   0x0000000000000000       0x82 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ethip6.o
  .debug_macro   0x0000000000000000       0x66 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ethip6.o
- .debug_macro   0x0000000000000000      0x756 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ethip6.o
- .debug_line    0x0000000000000000      0xb7c ./Middlewares/Third_Party/LwIP/src/core/ipv6/ethip6.o
- .debug_str     0x0000000000000000   0x13e82b ./Middlewares/Third_Party/LwIP/src/core/ipv6/ethip6.o
+ .debug_macro   0x0000000000000000      0x739 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ethip6.o
+ .debug_line    0x0000000000000000      0xc5d ./Middlewares/Third_Party/LwIP/src/core/ipv6/ethip6.o
+ .debug_str     0x0000000000000000   0x15d09f ./Middlewares/Third_Party/LwIP/src/core/ipv6/ethip6.o
  .comment       0x0000000000000000       0x44 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ethip6.o
  .ARM.attributes
                 0x0000000000000000       0x32 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ethip6.o
@@ -14869,6 +21684,15 @@ Discarded input sections
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv6/icmp6.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv6/icmp6.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv6/icmp6.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv6/icmp6.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv6/icmp6.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv6/icmp6.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv6/icmp6.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv6/icmp6.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv6/icmp6.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv6/icmp6.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv6/icmp6.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv6/icmp6.o
  .text          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/core/ipv6/icmp6.o
  .data          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/core/ipv6/icmp6.o
  .bss           0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/core/ipv6/icmp6.o
@@ -14876,9 +21700,9 @@ Discarded input sections
  .debug_abbrev  0x0000000000000000       0x28 ./Middlewares/Third_Party/LwIP/src/core/ipv6/icmp6.o
  .debug_aranges
                 0x0000000000000000       0x18 ./Middlewares/Third_Party/LwIP/src/core/ipv6/icmp6.o
- .debug_macro   0x0000000000000000      0x4a3 ./Middlewares/Third_Party/LwIP/src/core/ipv6/icmp6.o
+ .debug_macro   0x0000000000000000      0x507 ./Middlewares/Third_Party/LwIP/src/core/ipv6/icmp6.o
  .debug_macro   0x0000000000000000      0xac6 ./Middlewares/Third_Party/LwIP/src/core/ipv6/icmp6.o
- .debug_macro   0x0000000000000000      0x232 ./Middlewares/Third_Party/LwIP/src/core/ipv6/icmp6.o
+ .debug_macro   0x0000000000000000      0x24a ./Middlewares/Third_Party/LwIP/src/core/ipv6/icmp6.o
  .debug_macro   0x0000000000000000       0x2e ./Middlewares/Third_Party/LwIP/src/core/ipv6/icmp6.o
  .debug_macro   0x0000000000000000       0x3b ./Middlewares/Third_Party/LwIP/src/core/ipv6/icmp6.o
  .debug_macro   0x0000000000000000       0x22 ./Middlewares/Third_Party/LwIP/src/core/ipv6/icmp6.o
@@ -14926,6 +21750,7 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x129 ./Middlewares/Third_Party/LwIP/src/core/ipv6/icmp6.o
  .debug_macro   0x0000000000000000      0x3f9 ./Middlewares/Third_Party/LwIP/src/core/ipv6/icmp6.o
  .debug_macro   0x0000000000000000      0x275 ./Middlewares/Third_Party/LwIP/src/core/ipv6/icmp6.o
+ .debug_macro   0x0000000000000000      0xe42 ./Middlewares/Third_Party/LwIP/src/core/ipv6/icmp6.o
  .debug_macro   0x0000000000000000      0x3ca ./Middlewares/Third_Party/LwIP/src/core/ipv6/icmp6.o
  .debug_macro   0x0000000000000000      0x45c ./Middlewares/Third_Party/LwIP/src/core/ipv6/icmp6.o
  .debug_macro   0x0000000000000000       0x3c ./Middlewares/Third_Party/LwIP/src/core/ipv6/icmp6.o
@@ -14936,8 +21761,16 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x1c4 ./Middlewares/Third_Party/LwIP/src/core/ipv6/icmp6.o
  .debug_macro   0x0000000000000000      0x22a ./Middlewares/Third_Party/LwIP/src/core/ipv6/icmp6.o
  .debug_macro   0x0000000000000000       0x35 ./Middlewares/Third_Party/LwIP/src/core/ipv6/icmp6.o
+ .debug_macro   0x0000000000000000      0x830 ./Middlewares/Third_Party/LwIP/src/core/ipv6/icmp6.o
+ .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/core/ipv6/icmp6.o
+ .debug_macro   0x0000000000000000      0x1ce ./Middlewares/Third_Party/LwIP/src/core/ipv6/icmp6.o
+ .debug_macro   0x0000000000000000      0xb1d ./Middlewares/Third_Party/LwIP/src/core/ipv6/icmp6.o
+ .debug_macro   0x0000000000000000      0x29f ./Middlewares/Third_Party/LwIP/src/core/ipv6/icmp6.o
+ .debug_macro   0x0000000000000000      0x693 ./Middlewares/Third_Party/LwIP/src/core/ipv6/icmp6.o
+ .debug_macro   0x0000000000000000       0xa6 ./Middlewares/Third_Party/LwIP/src/core/ipv6/icmp6.o
  .debug_macro   0x0000000000000000      0x5e6 ./Middlewares/Third_Party/LwIP/src/core/ipv6/icmp6.o
- .debug_macro   0x0000000000000000       0xd0 ./Middlewares/Third_Party/LwIP/src/core/ipv6/icmp6.o
+ .debug_macro   0x0000000000000000       0x58 ./Middlewares/Third_Party/LwIP/src/core/ipv6/icmp6.o
+ .debug_macro   0x0000000000000000       0xe8 ./Middlewares/Third_Party/LwIP/src/core/ipv6/icmp6.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/core/ipv6/icmp6.o
  .debug_macro   0x0000000000000000       0x10 ./Middlewares/Third_Party/LwIP/src/core/ipv6/icmp6.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/core/ipv6/icmp6.o
@@ -14977,9 +21810,9 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x11f ./Middlewares/Third_Party/LwIP/src/core/ipv6/icmp6.o
  .debug_macro   0x0000000000000000       0x82 ./Middlewares/Third_Party/LwIP/src/core/ipv6/icmp6.o
  .debug_macro   0x0000000000000000       0x66 ./Middlewares/Third_Party/LwIP/src/core/ipv6/icmp6.o
- .debug_macro   0x0000000000000000      0x756 ./Middlewares/Third_Party/LwIP/src/core/ipv6/icmp6.o
- .debug_line    0x0000000000000000      0xb7b ./Middlewares/Third_Party/LwIP/src/core/ipv6/icmp6.o
- .debug_str     0x0000000000000000   0x13e82a ./Middlewares/Third_Party/LwIP/src/core/ipv6/icmp6.o
+ .debug_macro   0x0000000000000000      0x739 ./Middlewares/Third_Party/LwIP/src/core/ipv6/icmp6.o
+ .debug_line    0x0000000000000000      0xc5c ./Middlewares/Third_Party/LwIP/src/core/ipv6/icmp6.o
+ .debug_str     0x0000000000000000   0x15d09e ./Middlewares/Third_Party/LwIP/src/core/ipv6/icmp6.o
  .comment       0x0000000000000000       0x44 ./Middlewares/Third_Party/LwIP/src/core/ipv6/icmp6.o
  .ARM.attributes
                 0x0000000000000000       0x32 ./Middlewares/Third_Party/LwIP/src/core/ipv6/icmp6.o
@@ -15084,6 +21917,15 @@ Discarded input sections
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv6/inet6.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv6/inet6.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv6/inet6.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv6/inet6.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv6/inet6.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv6/inet6.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv6/inet6.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv6/inet6.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv6/inet6.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv6/inet6.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv6/inet6.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv6/inet6.o
  .text          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/core/ipv6/inet6.o
  .data          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/core/ipv6/inet6.o
  .bss           0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/core/ipv6/inet6.o
@@ -15091,9 +21933,9 @@ Discarded input sections
  .debug_abbrev  0x0000000000000000       0x28 ./Middlewares/Third_Party/LwIP/src/core/ipv6/inet6.o
  .debug_aranges
                 0x0000000000000000       0x18 ./Middlewares/Third_Party/LwIP/src/core/ipv6/inet6.o
- .debug_macro   0x0000000000000000      0x4a3 ./Middlewares/Third_Party/LwIP/src/core/ipv6/inet6.o
+ .debug_macro   0x0000000000000000      0x507 ./Middlewares/Third_Party/LwIP/src/core/ipv6/inet6.o
  .debug_macro   0x0000000000000000      0xac6 ./Middlewares/Third_Party/LwIP/src/core/ipv6/inet6.o
- .debug_macro   0x0000000000000000      0x232 ./Middlewares/Third_Party/LwIP/src/core/ipv6/inet6.o
+ .debug_macro   0x0000000000000000      0x24a ./Middlewares/Third_Party/LwIP/src/core/ipv6/inet6.o
  .debug_macro   0x0000000000000000       0x2e ./Middlewares/Third_Party/LwIP/src/core/ipv6/inet6.o
  .debug_macro   0x0000000000000000       0x3b ./Middlewares/Third_Party/LwIP/src/core/ipv6/inet6.o
  .debug_macro   0x0000000000000000       0x22 ./Middlewares/Third_Party/LwIP/src/core/ipv6/inet6.o
@@ -15141,6 +21983,7 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x129 ./Middlewares/Third_Party/LwIP/src/core/ipv6/inet6.o
  .debug_macro   0x0000000000000000      0x3f9 ./Middlewares/Third_Party/LwIP/src/core/ipv6/inet6.o
  .debug_macro   0x0000000000000000      0x275 ./Middlewares/Third_Party/LwIP/src/core/ipv6/inet6.o
+ .debug_macro   0x0000000000000000      0xe42 ./Middlewares/Third_Party/LwIP/src/core/ipv6/inet6.o
  .debug_macro   0x0000000000000000      0x3ca ./Middlewares/Third_Party/LwIP/src/core/ipv6/inet6.o
  .debug_macro   0x0000000000000000      0x45c ./Middlewares/Third_Party/LwIP/src/core/ipv6/inet6.o
  .debug_macro   0x0000000000000000       0x3c ./Middlewares/Third_Party/LwIP/src/core/ipv6/inet6.o
@@ -15151,8 +21994,16 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x1c4 ./Middlewares/Third_Party/LwIP/src/core/ipv6/inet6.o
  .debug_macro   0x0000000000000000      0x22a ./Middlewares/Third_Party/LwIP/src/core/ipv6/inet6.o
  .debug_macro   0x0000000000000000       0x35 ./Middlewares/Third_Party/LwIP/src/core/ipv6/inet6.o
+ .debug_macro   0x0000000000000000      0x830 ./Middlewares/Third_Party/LwIP/src/core/ipv6/inet6.o
+ .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/core/ipv6/inet6.o
+ .debug_macro   0x0000000000000000      0x1ce ./Middlewares/Third_Party/LwIP/src/core/ipv6/inet6.o
+ .debug_macro   0x0000000000000000      0xb1d ./Middlewares/Third_Party/LwIP/src/core/ipv6/inet6.o
+ .debug_macro   0x0000000000000000      0x29f ./Middlewares/Third_Party/LwIP/src/core/ipv6/inet6.o
+ .debug_macro   0x0000000000000000      0x693 ./Middlewares/Third_Party/LwIP/src/core/ipv6/inet6.o
+ .debug_macro   0x0000000000000000       0xa6 ./Middlewares/Third_Party/LwIP/src/core/ipv6/inet6.o
  .debug_macro   0x0000000000000000      0x5e6 ./Middlewares/Third_Party/LwIP/src/core/ipv6/inet6.o
- .debug_macro   0x0000000000000000       0xd0 ./Middlewares/Third_Party/LwIP/src/core/ipv6/inet6.o
+ .debug_macro   0x0000000000000000       0x58 ./Middlewares/Third_Party/LwIP/src/core/ipv6/inet6.o
+ .debug_macro   0x0000000000000000       0xe8 ./Middlewares/Third_Party/LwIP/src/core/ipv6/inet6.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/core/ipv6/inet6.o
  .debug_macro   0x0000000000000000       0x10 ./Middlewares/Third_Party/LwIP/src/core/ipv6/inet6.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/core/ipv6/inet6.o
@@ -15192,9 +22043,9 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x11f ./Middlewares/Third_Party/LwIP/src/core/ipv6/inet6.o
  .debug_macro   0x0000000000000000       0x82 ./Middlewares/Third_Party/LwIP/src/core/ipv6/inet6.o
  .debug_macro   0x0000000000000000       0x66 ./Middlewares/Third_Party/LwIP/src/core/ipv6/inet6.o
- .debug_macro   0x0000000000000000      0x756 ./Middlewares/Third_Party/LwIP/src/core/ipv6/inet6.o
- .debug_line    0x0000000000000000      0xb7b ./Middlewares/Third_Party/LwIP/src/core/ipv6/inet6.o
- .debug_str     0x0000000000000000   0x13e82a ./Middlewares/Third_Party/LwIP/src/core/ipv6/inet6.o
+ .debug_macro   0x0000000000000000      0x739 ./Middlewares/Third_Party/LwIP/src/core/ipv6/inet6.o
+ .debug_line    0x0000000000000000      0xc5c ./Middlewares/Third_Party/LwIP/src/core/ipv6/inet6.o
+ .debug_str     0x0000000000000000   0x15d09e ./Middlewares/Third_Party/LwIP/src/core/ipv6/inet6.o
  .comment       0x0000000000000000       0x44 ./Middlewares/Third_Party/LwIP/src/core/ipv6/inet6.o
  .ARM.attributes
                 0x0000000000000000       0x32 ./Middlewares/Third_Party/LwIP/src/core/ipv6/inet6.o
@@ -15299,6 +22150,15 @@ Discarded input sections
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6.o
  .text          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6.o
  .data          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6.o
  .bss           0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6.o
@@ -15306,9 +22166,9 @@ Discarded input sections
  .debug_abbrev  0x0000000000000000       0x28 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6.o
  .debug_aranges
                 0x0000000000000000       0x18 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6.o
- .debug_macro   0x0000000000000000      0x4a3 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6.o
+ .debug_macro   0x0000000000000000      0x507 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6.o
  .debug_macro   0x0000000000000000      0xac6 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6.o
- .debug_macro   0x0000000000000000      0x232 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6.o
+ .debug_macro   0x0000000000000000      0x24a ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6.o
  .debug_macro   0x0000000000000000       0x2e ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6.o
  .debug_macro   0x0000000000000000       0x3b ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6.o
  .debug_macro   0x0000000000000000       0x22 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6.o
@@ -15356,6 +22216,7 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x129 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6.o
  .debug_macro   0x0000000000000000      0x3f9 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6.o
  .debug_macro   0x0000000000000000      0x275 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6.o
+ .debug_macro   0x0000000000000000      0xe42 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6.o
  .debug_macro   0x0000000000000000      0x3ca ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6.o
  .debug_macro   0x0000000000000000      0x45c ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6.o
  .debug_macro   0x0000000000000000       0x3c ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6.o
@@ -15366,8 +22227,16 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x1c4 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6.o
  .debug_macro   0x0000000000000000      0x22a ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6.o
  .debug_macro   0x0000000000000000       0x35 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6.o
+ .debug_macro   0x0000000000000000      0x830 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6.o
+ .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6.o
+ .debug_macro   0x0000000000000000      0x1ce ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6.o
+ .debug_macro   0x0000000000000000      0xb1d ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6.o
+ .debug_macro   0x0000000000000000      0x29f ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6.o
+ .debug_macro   0x0000000000000000      0x693 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6.o
+ .debug_macro   0x0000000000000000       0xa6 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6.o
  .debug_macro   0x0000000000000000      0x5e6 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6.o
- .debug_macro   0x0000000000000000       0xd0 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6.o
+ .debug_macro   0x0000000000000000       0x58 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6.o
+ .debug_macro   0x0000000000000000       0xe8 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6.o
  .debug_macro   0x0000000000000000       0x10 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6.o
@@ -15407,9 +22276,9 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x11f ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6.o
  .debug_macro   0x0000000000000000       0x82 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6.o
  .debug_macro   0x0000000000000000       0x66 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6.o
- .debug_macro   0x0000000000000000      0x756 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6.o
- .debug_line    0x0000000000000000      0xb79 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6.o
- .debug_str     0x0000000000000000   0x13e828 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6.o
+ .debug_macro   0x0000000000000000      0x739 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6.o
+ .debug_line    0x0000000000000000      0xc5a ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6.o
+ .debug_str     0x0000000000000000   0x15d09c ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6.o
  .comment       0x0000000000000000       0x44 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6.o
  .ARM.attributes
                 0x0000000000000000       0x32 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6.o
@@ -15514,6 +22383,15 @@ Discarded input sections
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_addr.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_addr.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_addr.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_addr.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_addr.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_addr.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_addr.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_addr.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_addr.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_addr.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_addr.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_addr.o
  .text          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_addr.o
  .data          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_addr.o
  .bss           0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_addr.o
@@ -15521,9 +22399,9 @@ Discarded input sections
  .debug_abbrev  0x0000000000000000       0x28 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_addr.o
  .debug_aranges
                 0x0000000000000000       0x18 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_addr.o
- .debug_macro   0x0000000000000000      0x4a3 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_addr.o
+ .debug_macro   0x0000000000000000      0x507 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_addr.o
  .debug_macro   0x0000000000000000      0xac6 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_addr.o
- .debug_macro   0x0000000000000000      0x232 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_addr.o
+ .debug_macro   0x0000000000000000      0x24a ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_addr.o
  .debug_macro   0x0000000000000000       0x2e ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_addr.o
  .debug_macro   0x0000000000000000       0x3b ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_addr.o
  .debug_macro   0x0000000000000000       0x22 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_addr.o
@@ -15571,6 +22449,7 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x129 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_addr.o
  .debug_macro   0x0000000000000000      0x3f9 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_addr.o
  .debug_macro   0x0000000000000000      0x275 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_addr.o
+ .debug_macro   0x0000000000000000      0xe42 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_addr.o
  .debug_macro   0x0000000000000000      0x3ca ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_addr.o
  .debug_macro   0x0000000000000000      0x45c ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_addr.o
  .debug_macro   0x0000000000000000       0x3c ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_addr.o
@@ -15581,8 +22460,16 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x1c4 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_addr.o
  .debug_macro   0x0000000000000000      0x22a ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_addr.o
  .debug_macro   0x0000000000000000       0x35 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_addr.o
+ .debug_macro   0x0000000000000000      0x830 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_addr.o
+ .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_addr.o
+ .debug_macro   0x0000000000000000      0x1ce ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_addr.o
+ .debug_macro   0x0000000000000000      0xb1d ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_addr.o
+ .debug_macro   0x0000000000000000      0x29f ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_addr.o
+ .debug_macro   0x0000000000000000      0x693 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_addr.o
+ .debug_macro   0x0000000000000000       0xa6 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_addr.o
  .debug_macro   0x0000000000000000      0x5e6 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_addr.o
- .debug_macro   0x0000000000000000       0xd0 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_addr.o
+ .debug_macro   0x0000000000000000       0x58 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_addr.o
+ .debug_macro   0x0000000000000000       0xe8 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_addr.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_addr.o
  .debug_macro   0x0000000000000000       0x10 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_addr.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_addr.o
@@ -15622,9 +22509,9 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x11f ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_addr.o
  .debug_macro   0x0000000000000000       0x82 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_addr.o
  .debug_macro   0x0000000000000000       0x66 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_addr.o
- .debug_macro   0x0000000000000000      0x756 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_addr.o
- .debug_line    0x0000000000000000      0xb7e ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_addr.o
- .debug_str     0x0000000000000000   0x13e82d ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_addr.o
+ .debug_macro   0x0000000000000000      0x739 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_addr.o
+ .debug_line    0x0000000000000000      0xc5f ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_addr.o
+ .debug_str     0x0000000000000000   0x15d0a1 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_addr.o
  .comment       0x0000000000000000       0x44 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_addr.o
  .ARM.attributes
                 0x0000000000000000       0x32 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_addr.o
@@ -15747,6 +22634,15 @@ Discarded input sections
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_frag.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_frag.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_frag.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_frag.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_frag.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_frag.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_frag.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_frag.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_frag.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_frag.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_frag.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_frag.o
  .text          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_frag.o
  .data          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_frag.o
  .bss           0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_frag.o
@@ -15754,9 +22650,9 @@ Discarded input sections
  .debug_abbrev  0x0000000000000000       0x28 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_frag.o
  .debug_aranges
                 0x0000000000000000       0x18 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_frag.o
- .debug_macro   0x0000000000000000      0x5dc ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_frag.o
+ .debug_macro   0x0000000000000000      0x640 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_frag.o
  .debug_macro   0x0000000000000000      0xac6 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_frag.o
- .debug_macro   0x0000000000000000      0x232 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_frag.o
+ .debug_macro   0x0000000000000000      0x24a ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_frag.o
  .debug_macro   0x0000000000000000       0x2e ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_frag.o
  .debug_macro   0x0000000000000000       0x3b ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_frag.o
  .debug_macro   0x0000000000000000       0x22 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_frag.o
@@ -15804,6 +22700,7 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x129 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_frag.o
  .debug_macro   0x0000000000000000      0x3f9 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_frag.o
  .debug_macro   0x0000000000000000      0x275 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_frag.o
+ .debug_macro   0x0000000000000000      0xe42 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_frag.o
  .debug_macro   0x0000000000000000      0x3ca ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_frag.o
  .debug_macro   0x0000000000000000      0x45c ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_frag.o
  .debug_macro   0x0000000000000000       0x3c ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_frag.o
@@ -15814,8 +22711,16 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x1c4 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_frag.o
  .debug_macro   0x0000000000000000      0x22a ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_frag.o
  .debug_macro   0x0000000000000000       0x35 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_frag.o
+ .debug_macro   0x0000000000000000      0x830 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_frag.o
+ .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_frag.o
+ .debug_macro   0x0000000000000000      0x1ce ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_frag.o
+ .debug_macro   0x0000000000000000      0xb1d ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_frag.o
+ .debug_macro   0x0000000000000000      0x29f ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_frag.o
+ .debug_macro   0x0000000000000000      0x693 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_frag.o
+ .debug_macro   0x0000000000000000       0xa6 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_frag.o
  .debug_macro   0x0000000000000000      0x5e6 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_frag.o
- .debug_macro   0x0000000000000000       0xd0 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_frag.o
+ .debug_macro   0x0000000000000000       0x58 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_frag.o
+ .debug_macro   0x0000000000000000       0xe8 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_frag.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_frag.o
  .debug_macro   0x0000000000000000       0x10 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_frag.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_frag.o
@@ -15855,7 +22760,7 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x11f ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_frag.o
  .debug_macro   0x0000000000000000       0x82 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_frag.o
  .debug_macro   0x0000000000000000       0x66 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_frag.o
- .debug_macro   0x0000000000000000      0x756 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_frag.o
+ .debug_macro   0x0000000000000000      0x739 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_frag.o
  .debug_macro   0x0000000000000000       0xad ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_frag.o
  .debug_macro   0x0000000000000000       0x6a ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_frag.o
  .debug_macro   0x0000000000000000       0x10 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_frag.o
@@ -15874,8 +22779,8 @@ Discarded input sections
  .debug_macro   0x0000000000000000       0xea ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_frag.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_frag.o
  .debug_macro   0x0000000000000000       0x20 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_frag.o
- .debug_line    0x0000000000000000      0xd00 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_frag.o
- .debug_str     0x0000000000000000   0x1427dd ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_frag.o
+ .debug_line    0x0000000000000000      0xde1 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_frag.o
+ .debug_str     0x0000000000000000   0x161011 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_frag.o
  .comment       0x0000000000000000       0x44 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_frag.o
  .ARM.attributes
                 0x0000000000000000       0x32 ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_frag.o
@@ -15980,6 +22885,15 @@ Discarded input sections
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv6/mld6.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv6/mld6.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv6/mld6.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv6/mld6.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv6/mld6.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv6/mld6.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv6/mld6.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv6/mld6.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv6/mld6.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv6/mld6.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv6/mld6.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv6/mld6.o
  .text          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/core/ipv6/mld6.o
  .data          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/core/ipv6/mld6.o
  .bss           0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/core/ipv6/mld6.o
@@ -15987,9 +22901,9 @@ Discarded input sections
  .debug_abbrev  0x0000000000000000       0x28 ./Middlewares/Third_Party/LwIP/src/core/ipv6/mld6.o
  .debug_aranges
                 0x0000000000000000       0x18 ./Middlewares/Third_Party/LwIP/src/core/ipv6/mld6.o
- .debug_macro   0x0000000000000000      0x4a3 ./Middlewares/Third_Party/LwIP/src/core/ipv6/mld6.o
+ .debug_macro   0x0000000000000000      0x507 ./Middlewares/Third_Party/LwIP/src/core/ipv6/mld6.o
  .debug_macro   0x0000000000000000      0xac6 ./Middlewares/Third_Party/LwIP/src/core/ipv6/mld6.o
- .debug_macro   0x0000000000000000      0x232 ./Middlewares/Third_Party/LwIP/src/core/ipv6/mld6.o
+ .debug_macro   0x0000000000000000      0x24a ./Middlewares/Third_Party/LwIP/src/core/ipv6/mld6.o
  .debug_macro   0x0000000000000000       0x2e ./Middlewares/Third_Party/LwIP/src/core/ipv6/mld6.o
  .debug_macro   0x0000000000000000       0x3b ./Middlewares/Third_Party/LwIP/src/core/ipv6/mld6.o
  .debug_macro   0x0000000000000000       0x22 ./Middlewares/Third_Party/LwIP/src/core/ipv6/mld6.o
@@ -16037,6 +22951,7 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x129 ./Middlewares/Third_Party/LwIP/src/core/ipv6/mld6.o
  .debug_macro   0x0000000000000000      0x3f9 ./Middlewares/Third_Party/LwIP/src/core/ipv6/mld6.o
  .debug_macro   0x0000000000000000      0x275 ./Middlewares/Third_Party/LwIP/src/core/ipv6/mld6.o
+ .debug_macro   0x0000000000000000      0xe42 ./Middlewares/Third_Party/LwIP/src/core/ipv6/mld6.o
  .debug_macro   0x0000000000000000      0x3ca ./Middlewares/Third_Party/LwIP/src/core/ipv6/mld6.o
  .debug_macro   0x0000000000000000      0x45c ./Middlewares/Third_Party/LwIP/src/core/ipv6/mld6.o
  .debug_macro   0x0000000000000000       0x3c ./Middlewares/Third_Party/LwIP/src/core/ipv6/mld6.o
@@ -16047,8 +22962,16 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x1c4 ./Middlewares/Third_Party/LwIP/src/core/ipv6/mld6.o
  .debug_macro   0x0000000000000000      0x22a ./Middlewares/Third_Party/LwIP/src/core/ipv6/mld6.o
  .debug_macro   0x0000000000000000       0x35 ./Middlewares/Third_Party/LwIP/src/core/ipv6/mld6.o
+ .debug_macro   0x0000000000000000      0x830 ./Middlewares/Third_Party/LwIP/src/core/ipv6/mld6.o
+ .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/core/ipv6/mld6.o
+ .debug_macro   0x0000000000000000      0x1ce ./Middlewares/Third_Party/LwIP/src/core/ipv6/mld6.o
+ .debug_macro   0x0000000000000000      0xb1d ./Middlewares/Third_Party/LwIP/src/core/ipv6/mld6.o
+ .debug_macro   0x0000000000000000      0x29f ./Middlewares/Third_Party/LwIP/src/core/ipv6/mld6.o
+ .debug_macro   0x0000000000000000      0x693 ./Middlewares/Third_Party/LwIP/src/core/ipv6/mld6.o
+ .debug_macro   0x0000000000000000       0xa6 ./Middlewares/Third_Party/LwIP/src/core/ipv6/mld6.o
  .debug_macro   0x0000000000000000      0x5e6 ./Middlewares/Third_Party/LwIP/src/core/ipv6/mld6.o
- .debug_macro   0x0000000000000000       0xd0 ./Middlewares/Third_Party/LwIP/src/core/ipv6/mld6.o
+ .debug_macro   0x0000000000000000       0x58 ./Middlewares/Third_Party/LwIP/src/core/ipv6/mld6.o
+ .debug_macro   0x0000000000000000       0xe8 ./Middlewares/Third_Party/LwIP/src/core/ipv6/mld6.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/core/ipv6/mld6.o
  .debug_macro   0x0000000000000000       0x10 ./Middlewares/Third_Party/LwIP/src/core/ipv6/mld6.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/core/ipv6/mld6.o
@@ -16088,9 +23011,9 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x11f ./Middlewares/Third_Party/LwIP/src/core/ipv6/mld6.o
  .debug_macro   0x0000000000000000       0x82 ./Middlewares/Third_Party/LwIP/src/core/ipv6/mld6.o
  .debug_macro   0x0000000000000000       0x66 ./Middlewares/Third_Party/LwIP/src/core/ipv6/mld6.o
- .debug_macro   0x0000000000000000      0x756 ./Middlewares/Third_Party/LwIP/src/core/ipv6/mld6.o
- .debug_line    0x0000000000000000      0xb7a ./Middlewares/Third_Party/LwIP/src/core/ipv6/mld6.o
- .debug_str     0x0000000000000000   0x13e829 ./Middlewares/Third_Party/LwIP/src/core/ipv6/mld6.o
+ .debug_macro   0x0000000000000000      0x739 ./Middlewares/Third_Party/LwIP/src/core/ipv6/mld6.o
+ .debug_line    0x0000000000000000      0xc5b ./Middlewares/Third_Party/LwIP/src/core/ipv6/mld6.o
+ .debug_str     0x0000000000000000   0x15d09d ./Middlewares/Third_Party/LwIP/src/core/ipv6/mld6.o
  .comment       0x0000000000000000       0x44 ./Middlewares/Third_Party/LwIP/src/core/ipv6/mld6.o
  .ARM.attributes
                 0x0000000000000000       0x32 ./Middlewares/Third_Party/LwIP/src/core/ipv6/mld6.o
@@ -16195,6 +23118,15 @@ Discarded input sections
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv6/nd6.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv6/nd6.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv6/nd6.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv6/nd6.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv6/nd6.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv6/nd6.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv6/nd6.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv6/nd6.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv6/nd6.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv6/nd6.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv6/nd6.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/core/ipv6/nd6.o
  .text          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/core/ipv6/nd6.o
  .data          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/core/ipv6/nd6.o
  .bss           0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/core/ipv6/nd6.o
@@ -16202,9 +23134,9 @@ Discarded input sections
  .debug_abbrev  0x0000000000000000       0x28 ./Middlewares/Third_Party/LwIP/src/core/ipv6/nd6.o
  .debug_aranges
                 0x0000000000000000       0x18 ./Middlewares/Third_Party/LwIP/src/core/ipv6/nd6.o
- .debug_macro   0x0000000000000000      0x4a3 ./Middlewares/Third_Party/LwIP/src/core/ipv6/nd6.o
+ .debug_macro   0x0000000000000000      0x507 ./Middlewares/Third_Party/LwIP/src/core/ipv6/nd6.o
  .debug_macro   0x0000000000000000      0xac6 ./Middlewares/Third_Party/LwIP/src/core/ipv6/nd6.o
- .debug_macro   0x0000000000000000      0x232 ./Middlewares/Third_Party/LwIP/src/core/ipv6/nd6.o
+ .debug_macro   0x0000000000000000      0x24a ./Middlewares/Third_Party/LwIP/src/core/ipv6/nd6.o
  .debug_macro   0x0000000000000000       0x2e ./Middlewares/Third_Party/LwIP/src/core/ipv6/nd6.o
  .debug_macro   0x0000000000000000       0x3b ./Middlewares/Third_Party/LwIP/src/core/ipv6/nd6.o
  .debug_macro   0x0000000000000000       0x22 ./Middlewares/Third_Party/LwIP/src/core/ipv6/nd6.o
@@ -16252,6 +23184,7 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x129 ./Middlewares/Third_Party/LwIP/src/core/ipv6/nd6.o
  .debug_macro   0x0000000000000000      0x3f9 ./Middlewares/Third_Party/LwIP/src/core/ipv6/nd6.o
  .debug_macro   0x0000000000000000      0x275 ./Middlewares/Third_Party/LwIP/src/core/ipv6/nd6.o
+ .debug_macro   0x0000000000000000      0xe42 ./Middlewares/Third_Party/LwIP/src/core/ipv6/nd6.o
  .debug_macro   0x0000000000000000      0x3ca ./Middlewares/Third_Party/LwIP/src/core/ipv6/nd6.o
  .debug_macro   0x0000000000000000      0x45c ./Middlewares/Third_Party/LwIP/src/core/ipv6/nd6.o
  .debug_macro   0x0000000000000000       0x3c ./Middlewares/Third_Party/LwIP/src/core/ipv6/nd6.o
@@ -16262,8 +23195,16 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x1c4 ./Middlewares/Third_Party/LwIP/src/core/ipv6/nd6.o
  .debug_macro   0x0000000000000000      0x22a ./Middlewares/Third_Party/LwIP/src/core/ipv6/nd6.o
  .debug_macro   0x0000000000000000       0x35 ./Middlewares/Third_Party/LwIP/src/core/ipv6/nd6.o
+ .debug_macro   0x0000000000000000      0x830 ./Middlewares/Third_Party/LwIP/src/core/ipv6/nd6.o
+ .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/core/ipv6/nd6.o
+ .debug_macro   0x0000000000000000      0x1ce ./Middlewares/Third_Party/LwIP/src/core/ipv6/nd6.o
+ .debug_macro   0x0000000000000000      0xb1d ./Middlewares/Third_Party/LwIP/src/core/ipv6/nd6.o
+ .debug_macro   0x0000000000000000      0x29f ./Middlewares/Third_Party/LwIP/src/core/ipv6/nd6.o
+ .debug_macro   0x0000000000000000      0x693 ./Middlewares/Third_Party/LwIP/src/core/ipv6/nd6.o
+ .debug_macro   0x0000000000000000       0xa6 ./Middlewares/Third_Party/LwIP/src/core/ipv6/nd6.o
  .debug_macro   0x0000000000000000      0x5e6 ./Middlewares/Third_Party/LwIP/src/core/ipv6/nd6.o
- .debug_macro   0x0000000000000000       0xd0 ./Middlewares/Third_Party/LwIP/src/core/ipv6/nd6.o
+ .debug_macro   0x0000000000000000       0x58 ./Middlewares/Third_Party/LwIP/src/core/ipv6/nd6.o
+ .debug_macro   0x0000000000000000       0xe8 ./Middlewares/Third_Party/LwIP/src/core/ipv6/nd6.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/core/ipv6/nd6.o
  .debug_macro   0x0000000000000000       0x10 ./Middlewares/Third_Party/LwIP/src/core/ipv6/nd6.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/core/ipv6/nd6.o
@@ -16303,9 +23244,9 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x11f ./Middlewares/Third_Party/LwIP/src/core/ipv6/nd6.o
  .debug_macro   0x0000000000000000       0x82 ./Middlewares/Third_Party/LwIP/src/core/ipv6/nd6.o
  .debug_macro   0x0000000000000000       0x66 ./Middlewares/Third_Party/LwIP/src/core/ipv6/nd6.o
- .debug_macro   0x0000000000000000      0x756 ./Middlewares/Third_Party/LwIP/src/core/ipv6/nd6.o
- .debug_line    0x0000000000000000      0xb79 ./Middlewares/Third_Party/LwIP/src/core/ipv6/nd6.o
- .debug_str     0x0000000000000000   0x13e828 ./Middlewares/Third_Party/LwIP/src/core/ipv6/nd6.o
+ .debug_macro   0x0000000000000000      0x739 ./Middlewares/Third_Party/LwIP/src/core/ipv6/nd6.o
+ .debug_line    0x0000000000000000      0xc5a ./Middlewares/Third_Party/LwIP/src/core/ipv6/nd6.o
+ .debug_str     0x0000000000000000   0x15d09c ./Middlewares/Third_Party/LwIP/src/core/ipv6/nd6.o
  .comment       0x0000000000000000       0x44 ./Middlewares/Third_Party/LwIP/src/core/ipv6/nd6.o
  .ARM.attributes
                 0x0000000000000000       0x32 ./Middlewares/Third_Party/LwIP/src/core/ipv6/nd6.o
@@ -16435,6 +23376,31 @@ Discarded input sections
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/bridgeif.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/bridgeif.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/bridgeif.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/bridgeif.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/bridgeif.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/bridgeif.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/bridgeif.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/bridgeif.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/bridgeif.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/bridgeif.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/bridgeif.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/bridgeif.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/bridgeif.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/bridgeif.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/bridgeif.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/bridgeif.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/bridgeif.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/bridgeif.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/bridgeif.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/bridgeif.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/bridgeif.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/bridgeif.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/bridgeif.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/bridgeif.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/bridgeif.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/bridgeif.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/bridgeif.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/bridgeif.o
  .text          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/netif/bridgeif.o
  .data          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/netif/bridgeif.o
  .bss           0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/netif/bridgeif.o
@@ -16442,9 +23408,9 @@ Discarded input sections
  .debug_abbrev  0x0000000000000000       0x28 ./Middlewares/Third_Party/LwIP/src/netif/bridgeif.o
  .debug_aranges
                 0x0000000000000000       0x18 ./Middlewares/Third_Party/LwIP/src/netif/bridgeif.o
- .debug_macro   0x0000000000000000      0x605 ./Middlewares/Third_Party/LwIP/src/netif/bridgeif.o
+ .debug_macro   0x0000000000000000      0x750 ./Middlewares/Third_Party/LwIP/src/netif/bridgeif.o
  .debug_macro   0x0000000000000000      0xac6 ./Middlewares/Third_Party/LwIP/src/netif/bridgeif.o
- .debug_macro   0x0000000000000000      0x232 ./Middlewares/Third_Party/LwIP/src/netif/bridgeif.o
+ .debug_macro   0x0000000000000000      0x24a ./Middlewares/Third_Party/LwIP/src/netif/bridgeif.o
  .debug_macro   0x0000000000000000       0x2e ./Middlewares/Third_Party/LwIP/src/netif/bridgeif.o
  .debug_macro   0x0000000000000000       0x3b ./Middlewares/Third_Party/LwIP/src/netif/bridgeif.o
  .debug_macro   0x0000000000000000       0x22 ./Middlewares/Third_Party/LwIP/src/netif/bridgeif.o
@@ -16492,6 +23458,7 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x129 ./Middlewares/Third_Party/LwIP/src/netif/bridgeif.o
  .debug_macro   0x0000000000000000      0x3f9 ./Middlewares/Third_Party/LwIP/src/netif/bridgeif.o
  .debug_macro   0x0000000000000000      0x275 ./Middlewares/Third_Party/LwIP/src/netif/bridgeif.o
+ .debug_macro   0x0000000000000000      0xe42 ./Middlewares/Third_Party/LwIP/src/netif/bridgeif.o
  .debug_macro   0x0000000000000000      0x3ca ./Middlewares/Third_Party/LwIP/src/netif/bridgeif.o
  .debug_macro   0x0000000000000000      0x45c ./Middlewares/Third_Party/LwIP/src/netif/bridgeif.o
  .debug_macro   0x0000000000000000       0x3c ./Middlewares/Third_Party/LwIP/src/netif/bridgeif.o
@@ -16502,8 +23469,16 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x1c4 ./Middlewares/Third_Party/LwIP/src/netif/bridgeif.o
  .debug_macro   0x0000000000000000      0x22a ./Middlewares/Third_Party/LwIP/src/netif/bridgeif.o
  .debug_macro   0x0000000000000000       0x35 ./Middlewares/Third_Party/LwIP/src/netif/bridgeif.o
+ .debug_macro   0x0000000000000000      0x830 ./Middlewares/Third_Party/LwIP/src/netif/bridgeif.o
+ .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/netif/bridgeif.o
+ .debug_macro   0x0000000000000000      0x1ce ./Middlewares/Third_Party/LwIP/src/netif/bridgeif.o
+ .debug_macro   0x0000000000000000      0xb1d ./Middlewares/Third_Party/LwIP/src/netif/bridgeif.o
+ .debug_macro   0x0000000000000000      0x29f ./Middlewares/Third_Party/LwIP/src/netif/bridgeif.o
+ .debug_macro   0x0000000000000000      0x693 ./Middlewares/Third_Party/LwIP/src/netif/bridgeif.o
+ .debug_macro   0x0000000000000000       0xa6 ./Middlewares/Third_Party/LwIP/src/netif/bridgeif.o
  .debug_macro   0x0000000000000000      0x5e6 ./Middlewares/Third_Party/LwIP/src/netif/bridgeif.o
- .debug_macro   0x0000000000000000       0xd0 ./Middlewares/Third_Party/LwIP/src/netif/bridgeif.o
+ .debug_macro   0x0000000000000000       0x58 ./Middlewares/Third_Party/LwIP/src/netif/bridgeif.o
+ .debug_macro   0x0000000000000000       0xe8 ./Middlewares/Third_Party/LwIP/src/netif/bridgeif.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/netif/bridgeif.o
  .debug_macro   0x0000000000000000       0x10 ./Middlewares/Third_Party/LwIP/src/netif/bridgeif.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/netif/bridgeif.o
@@ -16543,12 +23518,27 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x11f ./Middlewares/Third_Party/LwIP/src/netif/bridgeif.o
  .debug_macro   0x0000000000000000       0x82 ./Middlewares/Third_Party/LwIP/src/netif/bridgeif.o
  .debug_macro   0x0000000000000000       0x66 ./Middlewares/Third_Party/LwIP/src/netif/bridgeif.o
- .debug_macro   0x0000000000000000      0x756 ./Middlewares/Third_Party/LwIP/src/netif/bridgeif.o
+ .debug_macro   0x0000000000000000      0x739 ./Middlewares/Third_Party/LwIP/src/netif/bridgeif.o
  .debug_macro   0x0000000000000000       0x22 ./Middlewares/Third_Party/LwIP/src/netif/bridgeif.o
  .debug_macro   0x0000000000000000       0x46 ./Middlewares/Third_Party/LwIP/src/netif/bridgeif.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/netif/bridgeif.o
- .debug_macro   0x0000000000000000       0xe4 ./Middlewares/Third_Party/LwIP/src/netif/bridgeif.o
- .debug_macro   0x0000000000000000       0x22 ./Middlewares/Third_Party/LwIP/src/netif/bridgeif.o
+ .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/netif/bridgeif.o
+ .debug_macro   0x0000000000000000      0x111 ./Middlewares/Third_Party/LwIP/src/netif/bridgeif.o
+ .debug_macro   0x0000000000000000      0x15a ./Middlewares/Third_Party/LwIP/src/netif/bridgeif.o
+ .debug_macro   0x0000000000000000       0xde ./Middlewares/Third_Party/LwIP/src/netif/bridgeif.o
+ .debug_macro   0x0000000000000000       0x1c ./Middlewares/Third_Party/LwIP/src/netif/bridgeif.o
+ .debug_macro   0x0000000000000000       0x26 ./Middlewares/Third_Party/LwIP/src/netif/bridgeif.o
+ .debug_macro   0x0000000000000000      0x4ef ./Middlewares/Third_Party/LwIP/src/netif/bridgeif.o
+ .debug_macro   0x0000000000000000       0xb5 ./Middlewares/Third_Party/LwIP/src/netif/bridgeif.o
+ .debug_macro   0x0000000000000000       0xaa ./Middlewares/Third_Party/LwIP/src/netif/bridgeif.o
+ .debug_macro   0x0000000000000000       0x91 ./Middlewares/Third_Party/LwIP/src/netif/bridgeif.o
+ .debug_macro   0x0000000000000000       0x8d ./Middlewares/Third_Party/LwIP/src/netif/bridgeif.o
+ .debug_macro   0x0000000000000000       0x7e ./Middlewares/Third_Party/LwIP/src/netif/bridgeif.o
+ .debug_macro   0x0000000000000000       0x19 ./Middlewares/Third_Party/LwIP/src/netif/bridgeif.o
+ .debug_macro   0x0000000000000000       0xf2 ./Middlewares/Third_Party/LwIP/src/netif/bridgeif.o
+ .debug_macro   0x0000000000000000       0x10 ./Middlewares/Third_Party/LwIP/src/netif/bridgeif.o
+ .debug_macro   0x0000000000000000       0x73 ./Middlewares/Third_Party/LwIP/src/netif/bridgeif.o
+ .debug_macro   0x0000000000000000       0x10 ./Middlewares/Third_Party/LwIP/src/netif/bridgeif.o
  .debug_macro   0x0000000000000000       0x10 ./Middlewares/Third_Party/LwIP/src/netif/bridgeif.o
  .debug_macro   0x0000000000000000       0x6a ./Middlewares/Third_Party/LwIP/src/netif/bridgeif.o
  .debug_macro   0x0000000000000000      0x1c3 ./Middlewares/Third_Party/LwIP/src/netif/bridgeif.o
@@ -16561,16 +23551,17 @@ Discarded input sections
  .debug_macro   0x0000000000000000       0x22 ./Middlewares/Third_Party/LwIP/src/netif/bridgeif.o
  .debug_macro   0x0000000000000000      0x15b ./Middlewares/Third_Party/LwIP/src/netif/bridgeif.o
  .debug_macro   0x0000000000000000      0x12f ./Middlewares/Third_Party/LwIP/src/netif/bridgeif.o
+ .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/netif/bridgeif.o
+ .debug_macro   0x0000000000000000       0x22 ./Middlewares/Third_Party/LwIP/src/netif/bridgeif.o
  .debug_macro   0x0000000000000000       0xa0 ./Middlewares/Third_Party/LwIP/src/netif/bridgeif.o
  .debug_macro   0x0000000000000000       0x28 ./Middlewares/Third_Party/LwIP/src/netif/bridgeif.o
  .debug_macro   0x0000000000000000       0x22 ./Middlewares/Third_Party/LwIP/src/netif/bridgeif.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/netif/bridgeif.o
  .debug_macro   0x0000000000000000       0xc0 ./Middlewares/Third_Party/LwIP/src/netif/bridgeif.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/netif/bridgeif.o
- .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/netif/bridgeif.o
  .debug_macro   0x0000000000000000       0x20 ./Middlewares/Third_Party/LwIP/src/netif/bridgeif.o
- .debug_line    0x0000000000000000      0xd66 ./Middlewares/Third_Party/LwIP/src/netif/bridgeif.o
- .debug_str     0x0000000000000000   0x143033 ./Middlewares/Third_Party/LwIP/src/netif/bridgeif.o
+ .debug_line    0x0000000000000000      0xfdc ./Middlewares/Third_Party/LwIP/src/netif/bridgeif.o
+ .debug_str     0x0000000000000000   0x1678f2 ./Middlewares/Third_Party/LwIP/src/netif/bridgeif.o
  .comment       0x0000000000000000       0x44 ./Middlewares/Third_Party/LwIP/src/netif/bridgeif.o
  .ARM.attributes
                 0x0000000000000000       0x32 ./Middlewares/Third_Party/LwIP/src/netif/bridgeif.o
@@ -16684,6 +23675,42 @@ Discarded input sections
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o
  .text          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o
  .data          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o
  .bss           0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o
@@ -16704,9 +23731,9 @@ Discarded input sections
                 0x0000000000000000       0x40 ./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o
  .debug_rnglists
                 0x0000000000000000       0x2c ./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o
- .debug_macro   0x0000000000000000      0x536 ./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o
+ .debug_macro   0x0000000000000000      0x714 ./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o
  .debug_macro   0x0000000000000000      0xac6 ./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o
- .debug_macro   0x0000000000000000      0x232 ./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o
+ .debug_macro   0x0000000000000000      0x24a ./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o
  .debug_macro   0x0000000000000000       0x2e ./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o
  .debug_macro   0x0000000000000000       0x3b ./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o
  .debug_macro   0x0000000000000000       0x22 ./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o
@@ -16754,6 +23781,7 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x129 ./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o
  .debug_macro   0x0000000000000000      0x3f9 ./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o
  .debug_macro   0x0000000000000000      0x275 ./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o
+ .debug_macro   0x0000000000000000      0xe42 ./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o
  .debug_macro   0x0000000000000000      0x3ca ./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o
  .debug_macro   0x0000000000000000      0x45c ./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o
  .debug_macro   0x0000000000000000       0x3c ./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o
@@ -16764,8 +23792,16 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x1c4 ./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o
  .debug_macro   0x0000000000000000      0x22a ./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o
  .debug_macro   0x0000000000000000       0x35 ./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o
+ .debug_macro   0x0000000000000000      0x830 ./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o
+ .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o
+ .debug_macro   0x0000000000000000      0x1ce ./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o
+ .debug_macro   0x0000000000000000      0xb1d ./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o
+ .debug_macro   0x0000000000000000      0x29f ./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o
+ .debug_macro   0x0000000000000000      0x693 ./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o
+ .debug_macro   0x0000000000000000       0xa6 ./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o
  .debug_macro   0x0000000000000000      0x5e6 ./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o
- .debug_macro   0x0000000000000000       0xd0 ./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o
+ .debug_macro   0x0000000000000000       0x58 ./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o
+ .debug_macro   0x0000000000000000       0xe8 ./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o
  .debug_macro   0x0000000000000000       0x10 ./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o
@@ -16805,18 +23841,45 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x11f ./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o
  .debug_macro   0x0000000000000000       0x82 ./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o
  .debug_macro   0x0000000000000000       0x66 ./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o
- .debug_macro   0x0000000000000000      0x756 ./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o
+ .debug_macro   0x0000000000000000      0x739 ./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o
  .debug_macro   0x0000000000000000       0x22 ./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o
  .debug_macro   0x0000000000000000       0x46 ./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o
- .debug_macro   0x0000000000000000       0xe4 ./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o
- .debug_macro   0x0000000000000000       0x22 ./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o
- .debug_macro   0x0000000000000000       0x10 ./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o
+ .debug_macro   0x0000000000000000      0x111 ./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o
+ .debug_macro   0x0000000000000000      0x15a ./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o
+ .debug_macro   0x0000000000000000       0xde ./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o
+ .debug_macro   0x0000000000000000       0x1c ./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o
+ .debug_macro   0x0000000000000000       0x26 ./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o
+ .debug_macro   0x0000000000000000      0x4ef ./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o
+ .debug_macro   0x0000000000000000       0xb5 ./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o
+ .debug_macro   0x0000000000000000       0xaa ./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o
+ .debug_macro   0x0000000000000000       0x91 ./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o
+ .debug_macro   0x0000000000000000       0x8d ./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o
+ .debug_macro   0x0000000000000000       0x7e ./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o
+ .debug_macro   0x0000000000000000       0x19 ./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o
+ .debug_macro   0x0000000000000000       0xf2 ./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o
+ .debug_macro   0x0000000000000000       0x10 ./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o
+ .debug_macro   0x0000000000000000       0x73 ./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o
+ .debug_macro   0x0000000000000000       0x10 ./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o
+ .debug_macro   0x0000000000000000       0x10 ./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o
+ .debug_macro   0x0000000000000000       0x6a ./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o
+ .debug_macro   0x0000000000000000      0x1c3 ./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o
+ .debug_macro   0x0000000000000000      0x169 ./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o
+ .debug_macro   0x0000000000000000       0xb3 ./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o
+ .debug_macro   0x0000000000000000       0x10 ./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o
+ .debug_macro   0x0000000000000000       0x10 ./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o
+ .debug_macro   0x0000000000000000       0x3f ./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o
+ .debug_macro   0x0000000000000000       0x25 ./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o
+ .debug_macro   0x0000000000000000       0x22 ./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o
+ .debug_macro   0x0000000000000000      0x15b ./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o
+ .debug_macro   0x0000000000000000      0x12f ./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o
+ .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o
+ .debug_macro   0x0000000000000000       0x22 ./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o
  .debug_macro   0x0000000000000000       0x20 ./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o
- .debug_line    0x0000000000000000      0xe7d ./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o
- .debug_str     0x0000000000000000   0x13f5b6 ./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o
+ .debug_line    0x0000000000000000     0x11b0 ./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o
+ .debug_str     0x0000000000000000   0x167086 ./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o
  .comment       0x0000000000000000       0x44 ./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o
  .debug_frame   0x0000000000000000       0xc8 ./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o
  .ARM.attributes
@@ -16945,11 +24008,20 @@ Discarded input sections
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ethernet.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ethernet.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ethernet.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ethernet.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ethernet.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ethernet.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ethernet.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ethernet.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ethernet.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ethernet.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ethernet.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ethernet.o
  .text          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/netif/ethernet.o
  .data          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/netif/ethernet.o
  .bss           0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/netif/ethernet.o
  .debug_macro   0x0000000000000000      0xac6 ./Middlewares/Third_Party/LwIP/src/netif/ethernet.o
- .debug_macro   0x0000000000000000      0x232 ./Middlewares/Third_Party/LwIP/src/netif/ethernet.o
+ .debug_macro   0x0000000000000000      0x24a ./Middlewares/Third_Party/LwIP/src/netif/ethernet.o
  .debug_macro   0x0000000000000000       0x2e ./Middlewares/Third_Party/LwIP/src/netif/ethernet.o
  .debug_macro   0x0000000000000000       0x3b ./Middlewares/Third_Party/LwIP/src/netif/ethernet.o
  .debug_macro   0x0000000000000000       0x22 ./Middlewares/Third_Party/LwIP/src/netif/ethernet.o
@@ -16997,6 +24069,7 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x129 ./Middlewares/Third_Party/LwIP/src/netif/ethernet.o
  .debug_macro   0x0000000000000000      0x3f9 ./Middlewares/Third_Party/LwIP/src/netif/ethernet.o
  .debug_macro   0x0000000000000000      0x275 ./Middlewares/Third_Party/LwIP/src/netif/ethernet.o
+ .debug_macro   0x0000000000000000      0xe42 ./Middlewares/Third_Party/LwIP/src/netif/ethernet.o
  .debug_macro   0x0000000000000000      0x3ca ./Middlewares/Third_Party/LwIP/src/netif/ethernet.o
  .debug_macro   0x0000000000000000      0x45c ./Middlewares/Third_Party/LwIP/src/netif/ethernet.o
  .debug_macro   0x0000000000000000       0x3c ./Middlewares/Third_Party/LwIP/src/netif/ethernet.o
@@ -17007,8 +24080,16 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x1c4 ./Middlewares/Third_Party/LwIP/src/netif/ethernet.o
  .debug_macro   0x0000000000000000      0x22a ./Middlewares/Third_Party/LwIP/src/netif/ethernet.o
  .debug_macro   0x0000000000000000       0x35 ./Middlewares/Third_Party/LwIP/src/netif/ethernet.o
+ .debug_macro   0x0000000000000000      0x830 ./Middlewares/Third_Party/LwIP/src/netif/ethernet.o
+ .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/netif/ethernet.o
+ .debug_macro   0x0000000000000000      0x1ce ./Middlewares/Third_Party/LwIP/src/netif/ethernet.o
+ .debug_macro   0x0000000000000000      0xb1d ./Middlewares/Third_Party/LwIP/src/netif/ethernet.o
+ .debug_macro   0x0000000000000000      0x29f ./Middlewares/Third_Party/LwIP/src/netif/ethernet.o
+ .debug_macro   0x0000000000000000      0x693 ./Middlewares/Third_Party/LwIP/src/netif/ethernet.o
+ .debug_macro   0x0000000000000000       0xa6 ./Middlewares/Third_Party/LwIP/src/netif/ethernet.o
  .debug_macro   0x0000000000000000      0x5e6 ./Middlewares/Third_Party/LwIP/src/netif/ethernet.o
- .debug_macro   0x0000000000000000       0xd0 ./Middlewares/Third_Party/LwIP/src/netif/ethernet.o
+ .debug_macro   0x0000000000000000       0x58 ./Middlewares/Third_Party/LwIP/src/netif/ethernet.o
+ .debug_macro   0x0000000000000000       0xe8 ./Middlewares/Third_Party/LwIP/src/netif/ethernet.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/netif/ethernet.o
  .debug_macro   0x0000000000000000       0x10 ./Middlewares/Third_Party/LwIP/src/netif/ethernet.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/netif/ethernet.o
@@ -17048,7 +24129,7 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x11f ./Middlewares/Third_Party/LwIP/src/netif/ethernet.o
  .debug_macro   0x0000000000000000       0x82 ./Middlewares/Third_Party/LwIP/src/netif/ethernet.o
  .debug_macro   0x0000000000000000       0x66 ./Middlewares/Third_Party/LwIP/src/netif/ethernet.o
- .debug_macro   0x0000000000000000      0x756 ./Middlewares/Third_Party/LwIP/src/netif/ethernet.o
+ .debug_macro   0x0000000000000000      0x739 ./Middlewares/Third_Party/LwIP/src/netif/ethernet.o
  .debug_macro   0x0000000000000000       0xad ./Middlewares/Third_Party/LwIP/src/netif/ethernet.o
  .debug_macro   0x0000000000000000       0x10 ./Middlewares/Third_Party/LwIP/src/netif/ethernet.o
  .debug_macro   0x0000000000000000       0x6a ./Middlewares/Third_Party/LwIP/src/netif/ethernet.o
@@ -17174,6 +24255,15 @@ Discarded input sections
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/lowpan6.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/lowpan6.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/lowpan6.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/lowpan6.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/lowpan6.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/lowpan6.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/lowpan6.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/lowpan6.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/lowpan6.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/lowpan6.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/lowpan6.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/lowpan6.o
  .text          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/netif/lowpan6.o
  .data          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/netif/lowpan6.o
  .bss           0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/netif/lowpan6.o
@@ -17181,9 +24271,9 @@ Discarded input sections
  .debug_abbrev  0x0000000000000000       0x28 ./Middlewares/Third_Party/LwIP/src/netif/lowpan6.o
  .debug_aranges
                 0x0000000000000000       0x18 ./Middlewares/Third_Party/LwIP/src/netif/lowpan6.o
- .debug_macro   0x0000000000000000      0x4bc ./Middlewares/Third_Party/LwIP/src/netif/lowpan6.o
+ .debug_macro   0x0000000000000000      0x520 ./Middlewares/Third_Party/LwIP/src/netif/lowpan6.o
  .debug_macro   0x0000000000000000      0xac6 ./Middlewares/Third_Party/LwIP/src/netif/lowpan6.o
- .debug_macro   0x0000000000000000      0x232 ./Middlewares/Third_Party/LwIP/src/netif/lowpan6.o
+ .debug_macro   0x0000000000000000      0x24a ./Middlewares/Third_Party/LwIP/src/netif/lowpan6.o
  .debug_macro   0x0000000000000000       0x2e ./Middlewares/Third_Party/LwIP/src/netif/lowpan6.o
  .debug_macro   0x0000000000000000       0x3b ./Middlewares/Third_Party/LwIP/src/netif/lowpan6.o
  .debug_macro   0x0000000000000000       0x22 ./Middlewares/Third_Party/LwIP/src/netif/lowpan6.o
@@ -17231,6 +24321,7 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x129 ./Middlewares/Third_Party/LwIP/src/netif/lowpan6.o
  .debug_macro   0x0000000000000000      0x3f9 ./Middlewares/Third_Party/LwIP/src/netif/lowpan6.o
  .debug_macro   0x0000000000000000      0x275 ./Middlewares/Third_Party/LwIP/src/netif/lowpan6.o
+ .debug_macro   0x0000000000000000      0xe42 ./Middlewares/Third_Party/LwIP/src/netif/lowpan6.o
  .debug_macro   0x0000000000000000      0x3ca ./Middlewares/Third_Party/LwIP/src/netif/lowpan6.o
  .debug_macro   0x0000000000000000      0x45c ./Middlewares/Third_Party/LwIP/src/netif/lowpan6.o
  .debug_macro   0x0000000000000000       0x3c ./Middlewares/Third_Party/LwIP/src/netif/lowpan6.o
@@ -17241,8 +24332,16 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x1c4 ./Middlewares/Third_Party/LwIP/src/netif/lowpan6.o
  .debug_macro   0x0000000000000000      0x22a ./Middlewares/Third_Party/LwIP/src/netif/lowpan6.o
  .debug_macro   0x0000000000000000       0x35 ./Middlewares/Third_Party/LwIP/src/netif/lowpan6.o
+ .debug_macro   0x0000000000000000      0x830 ./Middlewares/Third_Party/LwIP/src/netif/lowpan6.o
+ .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/netif/lowpan6.o
+ .debug_macro   0x0000000000000000      0x1ce ./Middlewares/Third_Party/LwIP/src/netif/lowpan6.o
+ .debug_macro   0x0000000000000000      0xb1d ./Middlewares/Third_Party/LwIP/src/netif/lowpan6.o
+ .debug_macro   0x0000000000000000      0x29f ./Middlewares/Third_Party/LwIP/src/netif/lowpan6.o
+ .debug_macro   0x0000000000000000      0x693 ./Middlewares/Third_Party/LwIP/src/netif/lowpan6.o
+ .debug_macro   0x0000000000000000       0xa6 ./Middlewares/Third_Party/LwIP/src/netif/lowpan6.o
  .debug_macro   0x0000000000000000      0x5e6 ./Middlewares/Third_Party/LwIP/src/netif/lowpan6.o
- .debug_macro   0x0000000000000000       0xd0 ./Middlewares/Third_Party/LwIP/src/netif/lowpan6.o
+ .debug_macro   0x0000000000000000       0x58 ./Middlewares/Third_Party/LwIP/src/netif/lowpan6.o
+ .debug_macro   0x0000000000000000       0xe8 ./Middlewares/Third_Party/LwIP/src/netif/lowpan6.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/netif/lowpan6.o
  .debug_macro   0x0000000000000000       0x10 ./Middlewares/Third_Party/LwIP/src/netif/lowpan6.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/netif/lowpan6.o
@@ -17282,10 +24381,10 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x11f ./Middlewares/Third_Party/LwIP/src/netif/lowpan6.o
  .debug_macro   0x0000000000000000       0x82 ./Middlewares/Third_Party/LwIP/src/netif/lowpan6.o
  .debug_macro   0x0000000000000000       0x66 ./Middlewares/Third_Party/LwIP/src/netif/lowpan6.o
- .debug_macro   0x0000000000000000      0x756 ./Middlewares/Third_Party/LwIP/src/netif/lowpan6.o
+ .debug_macro   0x0000000000000000      0x739 ./Middlewares/Third_Party/LwIP/src/netif/lowpan6.o
  .debug_macro   0x0000000000000000       0x46 ./Middlewares/Third_Party/LwIP/src/netif/lowpan6.o
- .debug_line    0x0000000000000000      0xbca ./Middlewares/Third_Party/LwIP/src/netif/lowpan6.o
- .debug_str     0x0000000000000000   0x13ea02 ./Middlewares/Third_Party/LwIP/src/netif/lowpan6.o
+ .debug_line    0x0000000000000000      0xcab ./Middlewares/Third_Party/LwIP/src/netif/lowpan6.o
+ .debug_str     0x0000000000000000   0x15d276 ./Middlewares/Third_Party/LwIP/src/netif/lowpan6.o
  .comment       0x0000000000000000       0x44 ./Middlewares/Third_Party/LwIP/src/netif/lowpan6.o
  .ARM.attributes
                 0x0000000000000000       0x32 ./Middlewares/Third_Party/LwIP/src/netif/lowpan6.o
@@ -17391,6 +24490,15 @@ Discarded input sections
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_ble.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_ble.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_ble.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_ble.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_ble.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_ble.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_ble.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_ble.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_ble.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_ble.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_ble.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_ble.o
  .text          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_ble.o
  .data          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_ble.o
  .bss           0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_ble.o
@@ -17398,9 +24506,9 @@ Discarded input sections
  .debug_abbrev  0x0000000000000000       0x28 ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_ble.o
  .debug_aranges
                 0x0000000000000000       0x18 ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_ble.o
- .debug_macro   0x0000000000000000      0x4bc ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_ble.o
+ .debug_macro   0x0000000000000000      0x520 ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_ble.o
  .debug_macro   0x0000000000000000      0xac6 ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_ble.o
- .debug_macro   0x0000000000000000      0x232 ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_ble.o
+ .debug_macro   0x0000000000000000      0x24a ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_ble.o
  .debug_macro   0x0000000000000000       0x2e ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_ble.o
  .debug_macro   0x0000000000000000       0x3b ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_ble.o
  .debug_macro   0x0000000000000000       0x22 ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_ble.o
@@ -17448,6 +24556,7 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x129 ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_ble.o
  .debug_macro   0x0000000000000000      0x3f9 ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_ble.o
  .debug_macro   0x0000000000000000      0x275 ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_ble.o
+ .debug_macro   0x0000000000000000      0xe42 ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_ble.o
  .debug_macro   0x0000000000000000      0x3ca ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_ble.o
  .debug_macro   0x0000000000000000      0x45c ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_ble.o
  .debug_macro   0x0000000000000000       0x3c ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_ble.o
@@ -17458,8 +24567,16 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x1c4 ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_ble.o
  .debug_macro   0x0000000000000000      0x22a ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_ble.o
  .debug_macro   0x0000000000000000       0x35 ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_ble.o
+ .debug_macro   0x0000000000000000      0x830 ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_ble.o
+ .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_ble.o
+ .debug_macro   0x0000000000000000      0x1ce ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_ble.o
+ .debug_macro   0x0000000000000000      0xb1d ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_ble.o
+ .debug_macro   0x0000000000000000      0x29f ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_ble.o
+ .debug_macro   0x0000000000000000      0x693 ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_ble.o
+ .debug_macro   0x0000000000000000       0xa6 ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_ble.o
  .debug_macro   0x0000000000000000      0x5e6 ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_ble.o
- .debug_macro   0x0000000000000000       0xd0 ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_ble.o
+ .debug_macro   0x0000000000000000       0x58 ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_ble.o
+ .debug_macro   0x0000000000000000       0xe8 ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_ble.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_ble.o
  .debug_macro   0x0000000000000000       0x10 ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_ble.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_ble.o
@@ -17499,10 +24616,10 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x11f ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_ble.o
  .debug_macro   0x0000000000000000       0x82 ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_ble.o
  .debug_macro   0x0000000000000000       0x66 ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_ble.o
- .debug_macro   0x0000000000000000      0x756 ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_ble.o
+ .debug_macro   0x0000000000000000      0x739 ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_ble.o
  .debug_macro   0x0000000000000000       0x46 ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_ble.o
- .debug_line    0x0000000000000000      0xbd2 ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_ble.o
- .debug_str     0x0000000000000000   0x13ea0a ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_ble.o
+ .debug_line    0x0000000000000000      0xcb3 ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_ble.o
+ .debug_str     0x0000000000000000   0x15d27e ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_ble.o
  .comment       0x0000000000000000       0x44 ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_ble.o
  .ARM.attributes
                 0x0000000000000000       0x32 ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_ble.o
@@ -17608,6 +24725,15 @@ Discarded input sections
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_common.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_common.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_common.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_common.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_common.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_common.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_common.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_common.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_common.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_common.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_common.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_common.o
  .text          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_common.o
  .data          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_common.o
  .bss           0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_common.o
@@ -17615,9 +24741,9 @@ Discarded input sections
  .debug_abbrev  0x0000000000000000       0x28 ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_common.o
  .debug_aranges
                 0x0000000000000000       0x18 ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_common.o
- .debug_macro   0x0000000000000000      0x4bc ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_common.o
+ .debug_macro   0x0000000000000000      0x520 ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_common.o
  .debug_macro   0x0000000000000000      0xac6 ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_common.o
- .debug_macro   0x0000000000000000      0x232 ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_common.o
+ .debug_macro   0x0000000000000000      0x24a ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_common.o
  .debug_macro   0x0000000000000000       0x2e ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_common.o
  .debug_macro   0x0000000000000000       0x3b ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_common.o
  .debug_macro   0x0000000000000000       0x22 ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_common.o
@@ -17665,6 +24791,7 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x129 ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_common.o
  .debug_macro   0x0000000000000000      0x3f9 ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_common.o
  .debug_macro   0x0000000000000000      0x275 ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_common.o
+ .debug_macro   0x0000000000000000      0xe42 ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_common.o
  .debug_macro   0x0000000000000000      0x3ca ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_common.o
  .debug_macro   0x0000000000000000      0x45c ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_common.o
  .debug_macro   0x0000000000000000       0x3c ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_common.o
@@ -17675,8 +24802,16 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x1c4 ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_common.o
  .debug_macro   0x0000000000000000      0x22a ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_common.o
  .debug_macro   0x0000000000000000       0x35 ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_common.o
+ .debug_macro   0x0000000000000000      0x830 ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_common.o
+ .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_common.o
+ .debug_macro   0x0000000000000000      0x1ce ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_common.o
+ .debug_macro   0x0000000000000000      0xb1d ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_common.o
+ .debug_macro   0x0000000000000000      0x29f ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_common.o
+ .debug_macro   0x0000000000000000      0x693 ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_common.o
+ .debug_macro   0x0000000000000000       0xa6 ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_common.o
  .debug_macro   0x0000000000000000      0x5e6 ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_common.o
- .debug_macro   0x0000000000000000       0xd0 ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_common.o
+ .debug_macro   0x0000000000000000       0x58 ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_common.o
+ .debug_macro   0x0000000000000000       0xe8 ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_common.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_common.o
  .debug_macro   0x0000000000000000       0x10 ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_common.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_common.o
@@ -17716,10 +24851,10 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x11f ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_common.o
  .debug_macro   0x0000000000000000       0x82 ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_common.o
  .debug_macro   0x0000000000000000       0x66 ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_common.o
- .debug_macro   0x0000000000000000      0x756 ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_common.o
+ .debug_macro   0x0000000000000000      0x739 ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_common.o
  .debug_macro   0x0000000000000000       0x46 ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_common.o
- .debug_line    0x0000000000000000      0xbd8 ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_common.o
- .debug_str     0x0000000000000000   0x13ea10 ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_common.o
+ .debug_line    0x0000000000000000      0xcb9 ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_common.o
+ .debug_str     0x0000000000000000   0x15d284 ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_common.o
  .comment       0x0000000000000000       0x44 ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_common.o
  .ARM.attributes
                 0x0000000000000000       0x32 ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_common.o
@@ -17839,10 +24974,34 @@ Discarded input sections
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/slipif.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/slipif.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/slipif.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/slipif.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/slipif.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/slipif.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/slipif.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/slipif.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/slipif.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/slipif.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/slipif.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/slipif.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/slipif.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/slipif.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/slipif.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/slipif.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/slipif.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/slipif.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/slipif.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/slipif.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/slipif.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/slipif.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/slipif.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/slipif.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/slipif.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/slipif.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/slipif.o
  .text          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/netif/slipif.o
  .data          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/netif/slipif.o
  .bss           0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/netif/slipif.o
- .rodata        0x0000000000000000       0xaf ./Middlewares/Third_Party/LwIP/src/netif/slipif.o
+ .rodata        0x0000000000000000       0xbc ./Middlewares/Third_Party/LwIP/src/netif/slipif.o
  .text.slipif_output
                 0x0000000000000000      0x104 ./Middlewares/Third_Party/LwIP/src/netif/slipif.o
  .text.slipif_output_v4
@@ -17851,19 +25010,21 @@ Discarded input sections
                 0x0000000000000000      0x19c ./Middlewares/Third_Party/LwIP/src/netif/slipif.o
  .text.slipif_rxbyte_input
                 0x0000000000000000       0x3c ./Middlewares/Third_Party/LwIP/src/netif/slipif.o
+ .text.slipif_loop_thread
+                0x0000000000000000       0x34 ./Middlewares/Third_Party/LwIP/src/netif/slipif.o
  .text.slipif_init
-                0x0000000000000000       0xb8 ./Middlewares/Third_Party/LwIP/src/netif/slipif.o
+                0x0000000000000000       0xd0 ./Middlewares/Third_Party/LwIP/src/netif/slipif.o
  .text.slipif_poll
                 0x0000000000000000       0x74 ./Middlewares/Third_Party/LwIP/src/netif/slipif.o
- .debug_info    0x0000000000000000      0x7cf ./Middlewares/Third_Party/LwIP/src/netif/slipif.o
- .debug_abbrev  0x0000000000000000      0x2b3 ./Middlewares/Third_Party/LwIP/src/netif/slipif.o
+ .debug_info    0x0000000000000000      0x8b2 ./Middlewares/Third_Party/LwIP/src/netif/slipif.o
+ .debug_abbrev  0x0000000000000000      0x2be ./Middlewares/Third_Party/LwIP/src/netif/slipif.o
  .debug_aranges
-                0x0000000000000000       0x48 ./Middlewares/Third_Party/LwIP/src/netif/slipif.o
+                0x0000000000000000       0x50 ./Middlewares/Third_Party/LwIP/src/netif/slipif.o
  .debug_rnglists
-                0x0000000000000000       0x34 ./Middlewares/Third_Party/LwIP/src/netif/slipif.o
- .debug_macro   0x0000000000000000      0x59d ./Middlewares/Third_Party/LwIP/src/netif/slipif.o
+                0x0000000000000000       0x3a ./Middlewares/Third_Party/LwIP/src/netif/slipif.o
+ .debug_macro   0x0000000000000000      0x6c8 ./Middlewares/Third_Party/LwIP/src/netif/slipif.o
  .debug_macro   0x0000000000000000      0xac6 ./Middlewares/Third_Party/LwIP/src/netif/slipif.o
- .debug_macro   0x0000000000000000      0x232 ./Middlewares/Third_Party/LwIP/src/netif/slipif.o
+ .debug_macro   0x0000000000000000      0x24a ./Middlewares/Third_Party/LwIP/src/netif/slipif.o
  .debug_macro   0x0000000000000000       0x2e ./Middlewares/Third_Party/LwIP/src/netif/slipif.o
  .debug_macro   0x0000000000000000       0x3b ./Middlewares/Third_Party/LwIP/src/netif/slipif.o
  .debug_macro   0x0000000000000000       0x22 ./Middlewares/Third_Party/LwIP/src/netif/slipif.o
@@ -17911,6 +25072,7 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x129 ./Middlewares/Third_Party/LwIP/src/netif/slipif.o
  .debug_macro   0x0000000000000000      0x3f9 ./Middlewares/Third_Party/LwIP/src/netif/slipif.o
  .debug_macro   0x0000000000000000      0x275 ./Middlewares/Third_Party/LwIP/src/netif/slipif.o
+ .debug_macro   0x0000000000000000      0xe42 ./Middlewares/Third_Party/LwIP/src/netif/slipif.o
  .debug_macro   0x0000000000000000      0x3ca ./Middlewares/Third_Party/LwIP/src/netif/slipif.o
  .debug_macro   0x0000000000000000      0x45c ./Middlewares/Third_Party/LwIP/src/netif/slipif.o
  .debug_macro   0x0000000000000000       0x3c ./Middlewares/Third_Party/LwIP/src/netif/slipif.o
@@ -17921,8 +25083,16 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x1c4 ./Middlewares/Third_Party/LwIP/src/netif/slipif.o
  .debug_macro   0x0000000000000000      0x22a ./Middlewares/Third_Party/LwIP/src/netif/slipif.o
  .debug_macro   0x0000000000000000       0x35 ./Middlewares/Third_Party/LwIP/src/netif/slipif.o
+ .debug_macro   0x0000000000000000      0x830 ./Middlewares/Third_Party/LwIP/src/netif/slipif.o
+ .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/netif/slipif.o
+ .debug_macro   0x0000000000000000      0x1ce ./Middlewares/Third_Party/LwIP/src/netif/slipif.o
+ .debug_macro   0x0000000000000000      0xb1d ./Middlewares/Third_Party/LwIP/src/netif/slipif.o
+ .debug_macro   0x0000000000000000      0x29f ./Middlewares/Third_Party/LwIP/src/netif/slipif.o
+ .debug_macro   0x0000000000000000      0x693 ./Middlewares/Third_Party/LwIP/src/netif/slipif.o
+ .debug_macro   0x0000000000000000       0xa6 ./Middlewares/Third_Party/LwIP/src/netif/slipif.o
  .debug_macro   0x0000000000000000      0x5e6 ./Middlewares/Third_Party/LwIP/src/netif/slipif.o
- .debug_macro   0x0000000000000000       0xd0 ./Middlewares/Third_Party/LwIP/src/netif/slipif.o
+ .debug_macro   0x0000000000000000       0x58 ./Middlewares/Third_Party/LwIP/src/netif/slipif.o
+ .debug_macro   0x0000000000000000       0xe8 ./Middlewares/Third_Party/LwIP/src/netif/slipif.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/netif/slipif.o
  .debug_macro   0x0000000000000000       0x10 ./Middlewares/Third_Party/LwIP/src/netif/slipif.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/netif/slipif.o
@@ -17962,7 +25132,7 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x11f ./Middlewares/Third_Party/LwIP/src/netif/slipif.o
  .debug_macro   0x0000000000000000       0x82 ./Middlewares/Third_Party/LwIP/src/netif/slipif.o
  .debug_macro   0x0000000000000000       0x66 ./Middlewares/Third_Party/LwIP/src/netif/slipif.o
- .debug_macro   0x0000000000000000      0x756 ./Middlewares/Third_Party/LwIP/src/netif/slipif.o
+ .debug_macro   0x0000000000000000      0x739 ./Middlewares/Third_Party/LwIP/src/netif/slipif.o
  .debug_macro   0x0000000000000000       0x10 ./Middlewares/Third_Party/LwIP/src/netif/slipif.o
  .debug_macro   0x0000000000000000       0x6a ./Middlewares/Third_Party/LwIP/src/netif/slipif.o
  .debug_macro   0x0000000000000000      0x1c3 ./Middlewares/Third_Party/LwIP/src/netif/slipif.o
@@ -17977,11 +25147,26 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x12f ./Middlewares/Third_Party/LwIP/src/netif/slipif.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/netif/slipif.o
  .debug_macro   0x0000000000000000       0xc0 ./Middlewares/Third_Party/LwIP/src/netif/slipif.o
- .debug_macro   0x0000000000000000       0xe4 ./Middlewares/Third_Party/LwIP/src/netif/slipif.o
- .debug_line    0x0000000000000000      0xf07 ./Middlewares/Third_Party/LwIP/src/netif/slipif.o
- .debug_str     0x0000000000000000   0x142924 ./Middlewares/Third_Party/LwIP/src/netif/slipif.o
+ .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/netif/slipif.o
+ .debug_macro   0x0000000000000000      0x111 ./Middlewares/Third_Party/LwIP/src/netif/slipif.o
+ .debug_macro   0x0000000000000000      0x15a ./Middlewares/Third_Party/LwIP/src/netif/slipif.o
+ .debug_macro   0x0000000000000000       0xde ./Middlewares/Third_Party/LwIP/src/netif/slipif.o
+ .debug_macro   0x0000000000000000       0x1c ./Middlewares/Third_Party/LwIP/src/netif/slipif.o
+ .debug_macro   0x0000000000000000       0x26 ./Middlewares/Third_Party/LwIP/src/netif/slipif.o
+ .debug_macro   0x0000000000000000      0x4ef ./Middlewares/Third_Party/LwIP/src/netif/slipif.o
+ .debug_macro   0x0000000000000000       0xb5 ./Middlewares/Third_Party/LwIP/src/netif/slipif.o
+ .debug_macro   0x0000000000000000       0xaa ./Middlewares/Third_Party/LwIP/src/netif/slipif.o
+ .debug_macro   0x0000000000000000       0x91 ./Middlewares/Third_Party/LwIP/src/netif/slipif.o
+ .debug_macro   0x0000000000000000       0x8d ./Middlewares/Third_Party/LwIP/src/netif/slipif.o
+ .debug_macro   0x0000000000000000       0x7e ./Middlewares/Third_Party/LwIP/src/netif/slipif.o
+ .debug_macro   0x0000000000000000       0x19 ./Middlewares/Third_Party/LwIP/src/netif/slipif.o
+ .debug_macro   0x0000000000000000       0xf2 ./Middlewares/Third_Party/LwIP/src/netif/slipif.o
+ .debug_macro   0x0000000000000000       0x10 ./Middlewares/Third_Party/LwIP/src/netif/slipif.o
+ .debug_macro   0x0000000000000000       0x73 ./Middlewares/Third_Party/LwIP/src/netif/slipif.o
+ .debug_line    0x0000000000000000     0x1197 ./Middlewares/Third_Party/LwIP/src/netif/slipif.o
+ .debug_str     0x0000000000000000   0x1671a0 ./Middlewares/Third_Party/LwIP/src/netif/slipif.o
  .comment       0x0000000000000000       0x44 ./Middlewares/Third_Party/LwIP/src/netif/slipif.o
- .debug_frame   0x0000000000000000       0xe8 ./Middlewares/Third_Party/LwIP/src/netif/slipif.o
+ .debug_frame   0x0000000000000000      0x10c ./Middlewares/Third_Party/LwIP/src/netif/slipif.o
  .ARM.attributes
                 0x0000000000000000       0x32 ./Middlewares/Third_Party/LwIP/src/netif/slipif.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/zepif.o
@@ -18086,6 +25271,15 @@ Discarded input sections
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/zepif.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/zepif.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/zepif.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/zepif.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/zepif.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/zepif.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/zepif.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/zepif.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/zepif.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/zepif.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/zepif.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/zepif.o
  .text          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/netif/zepif.o
  .data          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/netif/zepif.o
  .bss           0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/netif/zepif.o
@@ -18093,9 +25287,9 @@ Discarded input sections
  .debug_abbrev  0x0000000000000000       0x28 ./Middlewares/Third_Party/LwIP/src/netif/zepif.o
  .debug_aranges
                 0x0000000000000000       0x18 ./Middlewares/Third_Party/LwIP/src/netif/zepif.o
- .debug_macro   0x0000000000000000      0x4c0 ./Middlewares/Third_Party/LwIP/src/netif/zepif.o
+ .debug_macro   0x0000000000000000      0x524 ./Middlewares/Third_Party/LwIP/src/netif/zepif.o
  .debug_macro   0x0000000000000000      0xac6 ./Middlewares/Third_Party/LwIP/src/netif/zepif.o
- .debug_macro   0x0000000000000000      0x232 ./Middlewares/Third_Party/LwIP/src/netif/zepif.o
+ .debug_macro   0x0000000000000000      0x24a ./Middlewares/Third_Party/LwIP/src/netif/zepif.o
  .debug_macro   0x0000000000000000       0x2e ./Middlewares/Third_Party/LwIP/src/netif/zepif.o
  .debug_macro   0x0000000000000000       0x3b ./Middlewares/Third_Party/LwIP/src/netif/zepif.o
  .debug_macro   0x0000000000000000       0x22 ./Middlewares/Third_Party/LwIP/src/netif/zepif.o
@@ -18143,6 +25337,7 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x129 ./Middlewares/Third_Party/LwIP/src/netif/zepif.o
  .debug_macro   0x0000000000000000      0x3f9 ./Middlewares/Third_Party/LwIP/src/netif/zepif.o
  .debug_macro   0x0000000000000000      0x275 ./Middlewares/Third_Party/LwIP/src/netif/zepif.o
+ .debug_macro   0x0000000000000000      0xe42 ./Middlewares/Third_Party/LwIP/src/netif/zepif.o
  .debug_macro   0x0000000000000000      0x3ca ./Middlewares/Third_Party/LwIP/src/netif/zepif.o
  .debug_macro   0x0000000000000000      0x45c ./Middlewares/Third_Party/LwIP/src/netif/zepif.o
  .debug_macro   0x0000000000000000       0x3c ./Middlewares/Third_Party/LwIP/src/netif/zepif.o
@@ -18153,8 +25348,16 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x1c4 ./Middlewares/Third_Party/LwIP/src/netif/zepif.o
  .debug_macro   0x0000000000000000      0x22a ./Middlewares/Third_Party/LwIP/src/netif/zepif.o
  .debug_macro   0x0000000000000000       0x35 ./Middlewares/Third_Party/LwIP/src/netif/zepif.o
+ .debug_macro   0x0000000000000000      0x830 ./Middlewares/Third_Party/LwIP/src/netif/zepif.o
+ .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/netif/zepif.o
+ .debug_macro   0x0000000000000000      0x1ce ./Middlewares/Third_Party/LwIP/src/netif/zepif.o
+ .debug_macro   0x0000000000000000      0xb1d ./Middlewares/Third_Party/LwIP/src/netif/zepif.o
+ .debug_macro   0x0000000000000000      0x29f ./Middlewares/Third_Party/LwIP/src/netif/zepif.o
+ .debug_macro   0x0000000000000000      0x693 ./Middlewares/Third_Party/LwIP/src/netif/zepif.o
+ .debug_macro   0x0000000000000000       0xa6 ./Middlewares/Third_Party/LwIP/src/netif/zepif.o
  .debug_macro   0x0000000000000000      0x5e6 ./Middlewares/Third_Party/LwIP/src/netif/zepif.o
- .debug_macro   0x0000000000000000       0xd0 ./Middlewares/Third_Party/LwIP/src/netif/zepif.o
+ .debug_macro   0x0000000000000000       0x58 ./Middlewares/Third_Party/LwIP/src/netif/zepif.o
+ .debug_macro   0x0000000000000000       0xe8 ./Middlewares/Third_Party/LwIP/src/netif/zepif.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/netif/zepif.o
  .debug_macro   0x0000000000000000       0x10 ./Middlewares/Third_Party/LwIP/src/netif/zepif.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/netif/zepif.o
@@ -18194,10 +25397,10 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x11f ./Middlewares/Third_Party/LwIP/src/netif/zepif.o
  .debug_macro   0x0000000000000000       0x82 ./Middlewares/Third_Party/LwIP/src/netif/zepif.o
  .debug_macro   0x0000000000000000       0x66 ./Middlewares/Third_Party/LwIP/src/netif/zepif.o
- .debug_macro   0x0000000000000000      0x756 ./Middlewares/Third_Party/LwIP/src/netif/zepif.o
+ .debug_macro   0x0000000000000000      0x739 ./Middlewares/Third_Party/LwIP/src/netif/zepif.o
  .debug_macro   0x0000000000000000       0x4c ./Middlewares/Third_Party/LwIP/src/netif/zepif.o
- .debug_line    0x0000000000000000      0xbd3 ./Middlewares/Third_Party/LwIP/src/netif/zepif.o
- .debug_str     0x0000000000000000   0x13ea12 ./Middlewares/Third_Party/LwIP/src/netif/zepif.o
+ .debug_line    0x0000000000000000      0xcb4 ./Middlewares/Third_Party/LwIP/src/netif/zepif.o
+ .debug_str     0x0000000000000000   0x15d286 ./Middlewares/Third_Party/LwIP/src/netif/zepif.o
  .comment       0x0000000000000000       0x44 ./Middlewares/Third_Party/LwIP/src/netif/zepif.o
  .ARM.attributes
                 0x0000000000000000       0x32 ./Middlewares/Third_Party/LwIP/src/netif/zepif.o
@@ -18303,6 +25506,15 @@ Discarded input sections
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/auth.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/auth.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/auth.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/auth.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/auth.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/auth.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/auth.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/auth.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/auth.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/auth.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/auth.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/auth.o
  .text          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/netif/ppp/auth.o
  .data          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/netif/ppp/auth.o
  .bss           0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/netif/ppp/auth.o
@@ -18310,9 +25522,9 @@ Discarded input sections
  .debug_abbrev  0x0000000000000000       0x28 ./Middlewares/Third_Party/LwIP/src/netif/ppp/auth.o
  .debug_aranges
                 0x0000000000000000       0x18 ./Middlewares/Third_Party/LwIP/src/netif/ppp/auth.o
- .debug_macro   0x0000000000000000      0x4b2 ./Middlewares/Third_Party/LwIP/src/netif/ppp/auth.o
+ .debug_macro   0x0000000000000000      0x516 ./Middlewares/Third_Party/LwIP/src/netif/ppp/auth.o
  .debug_macro   0x0000000000000000      0xac6 ./Middlewares/Third_Party/LwIP/src/netif/ppp/auth.o
- .debug_macro   0x0000000000000000      0x232 ./Middlewares/Third_Party/LwIP/src/netif/ppp/auth.o
+ .debug_macro   0x0000000000000000      0x24a ./Middlewares/Third_Party/LwIP/src/netif/ppp/auth.o
  .debug_macro   0x0000000000000000       0x2e ./Middlewares/Third_Party/LwIP/src/netif/ppp/auth.o
  .debug_macro   0x0000000000000000       0x3b ./Middlewares/Third_Party/LwIP/src/netif/ppp/auth.o
  .debug_macro   0x0000000000000000       0x22 ./Middlewares/Third_Party/LwIP/src/netif/ppp/auth.o
@@ -18360,6 +25572,7 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x129 ./Middlewares/Third_Party/LwIP/src/netif/ppp/auth.o
  .debug_macro   0x0000000000000000      0x3f9 ./Middlewares/Third_Party/LwIP/src/netif/ppp/auth.o
  .debug_macro   0x0000000000000000      0x275 ./Middlewares/Third_Party/LwIP/src/netif/ppp/auth.o
+ .debug_macro   0x0000000000000000      0xe42 ./Middlewares/Third_Party/LwIP/src/netif/ppp/auth.o
  .debug_macro   0x0000000000000000      0x3ca ./Middlewares/Third_Party/LwIP/src/netif/ppp/auth.o
  .debug_macro   0x0000000000000000      0x45c ./Middlewares/Third_Party/LwIP/src/netif/ppp/auth.o
  .debug_macro   0x0000000000000000       0x3c ./Middlewares/Third_Party/LwIP/src/netif/ppp/auth.o
@@ -18370,8 +25583,16 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x1c4 ./Middlewares/Third_Party/LwIP/src/netif/ppp/auth.o
  .debug_macro   0x0000000000000000      0x22a ./Middlewares/Third_Party/LwIP/src/netif/ppp/auth.o
  .debug_macro   0x0000000000000000       0x35 ./Middlewares/Third_Party/LwIP/src/netif/ppp/auth.o
+ .debug_macro   0x0000000000000000      0x830 ./Middlewares/Third_Party/LwIP/src/netif/ppp/auth.o
+ .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/netif/ppp/auth.o
+ .debug_macro   0x0000000000000000      0x1ce ./Middlewares/Third_Party/LwIP/src/netif/ppp/auth.o
+ .debug_macro   0x0000000000000000      0xb1d ./Middlewares/Third_Party/LwIP/src/netif/ppp/auth.o
+ .debug_macro   0x0000000000000000      0x29f ./Middlewares/Third_Party/LwIP/src/netif/ppp/auth.o
+ .debug_macro   0x0000000000000000      0x693 ./Middlewares/Third_Party/LwIP/src/netif/ppp/auth.o
+ .debug_macro   0x0000000000000000       0xa6 ./Middlewares/Third_Party/LwIP/src/netif/ppp/auth.o
  .debug_macro   0x0000000000000000      0x5e6 ./Middlewares/Third_Party/LwIP/src/netif/ppp/auth.o
- .debug_macro   0x0000000000000000       0xd0 ./Middlewares/Third_Party/LwIP/src/netif/ppp/auth.o
+ .debug_macro   0x0000000000000000       0x58 ./Middlewares/Third_Party/LwIP/src/netif/ppp/auth.o
+ .debug_macro   0x0000000000000000       0xe8 ./Middlewares/Third_Party/LwIP/src/netif/ppp/auth.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/netif/ppp/auth.o
  .debug_macro   0x0000000000000000       0x10 ./Middlewares/Third_Party/LwIP/src/netif/ppp/auth.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/netif/ppp/auth.o
@@ -18411,10 +25632,10 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x11f ./Middlewares/Third_Party/LwIP/src/netif/ppp/auth.o
  .debug_macro   0x0000000000000000       0x82 ./Middlewares/Third_Party/LwIP/src/netif/ppp/auth.o
  .debug_macro   0x0000000000000000       0x66 ./Middlewares/Third_Party/LwIP/src/netif/ppp/auth.o
- .debug_macro   0x0000000000000000      0x756 ./Middlewares/Third_Party/LwIP/src/netif/ppp/auth.o
+ .debug_macro   0x0000000000000000      0x739 ./Middlewares/Third_Party/LwIP/src/netif/ppp/auth.o
  .debug_macro   0x0000000000000000       0x2f ./Middlewares/Third_Party/LwIP/src/netif/ppp/auth.o
- .debug_line    0x0000000000000000      0xbbe ./Middlewares/Third_Party/LwIP/src/netif/ppp/auth.o
- .debug_str     0x0000000000000000   0x13e8eb ./Middlewares/Third_Party/LwIP/src/netif/ppp/auth.o
+ .debug_line    0x0000000000000000      0xc9f ./Middlewares/Third_Party/LwIP/src/netif/ppp/auth.o
+ .debug_str     0x0000000000000000   0x15d15f ./Middlewares/Third_Party/LwIP/src/netif/ppp/auth.o
  .comment       0x0000000000000000       0x44 ./Middlewares/Third_Party/LwIP/src/netif/ppp/auth.o
  .ARM.attributes
                 0x0000000000000000       0x32 ./Middlewares/Third_Party/LwIP/src/netif/ppp/auth.o
@@ -18520,6 +25741,15 @@ Discarded input sections
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/ccp.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/ccp.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/ccp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/ccp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/ccp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/ccp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/ccp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/ccp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/ccp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/ccp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/ccp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/ccp.o
  .text          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ccp.o
  .data          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ccp.o
  .bss           0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ccp.o
@@ -18527,9 +25757,9 @@ Discarded input sections
  .debug_abbrev  0x0000000000000000       0x28 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ccp.o
  .debug_aranges
                 0x0000000000000000       0x18 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ccp.o
- .debug_macro   0x0000000000000000      0x4b2 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ccp.o
+ .debug_macro   0x0000000000000000      0x516 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ccp.o
  .debug_macro   0x0000000000000000      0xac6 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ccp.o
- .debug_macro   0x0000000000000000      0x232 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ccp.o
+ .debug_macro   0x0000000000000000      0x24a ./Middlewares/Third_Party/LwIP/src/netif/ppp/ccp.o
  .debug_macro   0x0000000000000000       0x2e ./Middlewares/Third_Party/LwIP/src/netif/ppp/ccp.o
  .debug_macro   0x0000000000000000       0x3b ./Middlewares/Third_Party/LwIP/src/netif/ppp/ccp.o
  .debug_macro   0x0000000000000000       0x22 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ccp.o
@@ -18577,6 +25807,7 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x129 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ccp.o
  .debug_macro   0x0000000000000000      0x3f9 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ccp.o
  .debug_macro   0x0000000000000000      0x275 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ccp.o
+ .debug_macro   0x0000000000000000      0xe42 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ccp.o
  .debug_macro   0x0000000000000000      0x3ca ./Middlewares/Third_Party/LwIP/src/netif/ppp/ccp.o
  .debug_macro   0x0000000000000000      0x45c ./Middlewares/Third_Party/LwIP/src/netif/ppp/ccp.o
  .debug_macro   0x0000000000000000       0x3c ./Middlewares/Third_Party/LwIP/src/netif/ppp/ccp.o
@@ -18587,8 +25818,16 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x1c4 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ccp.o
  .debug_macro   0x0000000000000000      0x22a ./Middlewares/Third_Party/LwIP/src/netif/ppp/ccp.o
  .debug_macro   0x0000000000000000       0x35 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ccp.o
+ .debug_macro   0x0000000000000000      0x830 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ccp.o
+ .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ccp.o
+ .debug_macro   0x0000000000000000      0x1ce ./Middlewares/Third_Party/LwIP/src/netif/ppp/ccp.o
+ .debug_macro   0x0000000000000000      0xb1d ./Middlewares/Third_Party/LwIP/src/netif/ppp/ccp.o
+ .debug_macro   0x0000000000000000      0x29f ./Middlewares/Third_Party/LwIP/src/netif/ppp/ccp.o
+ .debug_macro   0x0000000000000000      0x693 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ccp.o
+ .debug_macro   0x0000000000000000       0xa6 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ccp.o
  .debug_macro   0x0000000000000000      0x5e6 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ccp.o
- .debug_macro   0x0000000000000000       0xd0 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ccp.o
+ .debug_macro   0x0000000000000000       0x58 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ccp.o
+ .debug_macro   0x0000000000000000       0xe8 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ccp.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ccp.o
  .debug_macro   0x0000000000000000       0x10 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ccp.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ccp.o
@@ -18628,10 +25867,10 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x11f ./Middlewares/Third_Party/LwIP/src/netif/ppp/ccp.o
  .debug_macro   0x0000000000000000       0x82 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ccp.o
  .debug_macro   0x0000000000000000       0x66 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ccp.o
- .debug_macro   0x0000000000000000      0x756 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ccp.o
+ .debug_macro   0x0000000000000000      0x739 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ccp.o
  .debug_macro   0x0000000000000000       0x2f ./Middlewares/Third_Party/LwIP/src/netif/ppp/ccp.o
- .debug_line    0x0000000000000000      0xbbd ./Middlewares/Third_Party/LwIP/src/netif/ppp/ccp.o
- .debug_str     0x0000000000000000   0x13e8ea ./Middlewares/Third_Party/LwIP/src/netif/ppp/ccp.o
+ .debug_line    0x0000000000000000      0xc9e ./Middlewares/Third_Party/LwIP/src/netif/ppp/ccp.o
+ .debug_str     0x0000000000000000   0x15d15e ./Middlewares/Third_Party/LwIP/src/netif/ppp/ccp.o
  .comment       0x0000000000000000       0x44 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ccp.o
  .ARM.attributes
                 0x0000000000000000       0x32 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ccp.o
@@ -18737,6 +25976,15 @@ Discarded input sections
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-md5.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-md5.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-md5.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-md5.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-md5.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-md5.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-md5.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-md5.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-md5.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-md5.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-md5.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-md5.o
  .text          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-md5.o
  .data          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-md5.o
  .bss           0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-md5.o
@@ -18744,9 +25992,9 @@ Discarded input sections
  .debug_abbrev  0x0000000000000000       0x28 ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-md5.o
  .debug_aranges
                 0x0000000000000000       0x18 ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-md5.o
- .debug_macro   0x0000000000000000      0x4b2 ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-md5.o
+ .debug_macro   0x0000000000000000      0x516 ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-md5.o
  .debug_macro   0x0000000000000000      0xac6 ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-md5.o
- .debug_macro   0x0000000000000000      0x232 ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-md5.o
+ .debug_macro   0x0000000000000000      0x24a ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-md5.o
  .debug_macro   0x0000000000000000       0x2e ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-md5.o
  .debug_macro   0x0000000000000000       0x3b ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-md5.o
  .debug_macro   0x0000000000000000       0x22 ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-md5.o
@@ -18794,6 +26042,7 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x129 ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-md5.o
  .debug_macro   0x0000000000000000      0x3f9 ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-md5.o
  .debug_macro   0x0000000000000000      0x275 ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-md5.o
+ .debug_macro   0x0000000000000000      0xe42 ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-md5.o
  .debug_macro   0x0000000000000000      0x3ca ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-md5.o
  .debug_macro   0x0000000000000000      0x45c ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-md5.o
  .debug_macro   0x0000000000000000       0x3c ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-md5.o
@@ -18804,8 +26053,16 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x1c4 ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-md5.o
  .debug_macro   0x0000000000000000      0x22a ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-md5.o
  .debug_macro   0x0000000000000000       0x35 ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-md5.o
+ .debug_macro   0x0000000000000000      0x830 ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-md5.o
+ .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-md5.o
+ .debug_macro   0x0000000000000000      0x1ce ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-md5.o
+ .debug_macro   0x0000000000000000      0xb1d ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-md5.o
+ .debug_macro   0x0000000000000000      0x29f ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-md5.o
+ .debug_macro   0x0000000000000000      0x693 ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-md5.o
+ .debug_macro   0x0000000000000000       0xa6 ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-md5.o
  .debug_macro   0x0000000000000000      0x5e6 ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-md5.o
- .debug_macro   0x0000000000000000       0xd0 ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-md5.o
+ .debug_macro   0x0000000000000000       0x58 ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-md5.o
+ .debug_macro   0x0000000000000000       0xe8 ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-md5.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-md5.o
  .debug_macro   0x0000000000000000       0x10 ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-md5.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-md5.o
@@ -18845,10 +26102,10 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x11f ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-md5.o
  .debug_macro   0x0000000000000000       0x82 ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-md5.o
  .debug_macro   0x0000000000000000       0x66 ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-md5.o
- .debug_macro   0x0000000000000000      0x756 ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-md5.o
+ .debug_macro   0x0000000000000000      0x739 ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-md5.o
  .debug_macro   0x0000000000000000       0x2f ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-md5.o
- .debug_line    0x0000000000000000      0xbc2 ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-md5.o
- .debug_str     0x0000000000000000   0x13e8ef ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-md5.o
+ .debug_line    0x0000000000000000      0xca3 ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-md5.o
+ .debug_str     0x0000000000000000   0x15d163 ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-md5.o
  .comment       0x0000000000000000       0x44 ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-md5.o
  .ARM.attributes
                 0x0000000000000000       0x32 ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-md5.o
@@ -18954,6 +26211,15 @@ Discarded input sections
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-new.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-new.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-new.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-new.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-new.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-new.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-new.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-new.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-new.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-new.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-new.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-new.o
  .text          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-new.o
  .data          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-new.o
  .bss           0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-new.o
@@ -18961,9 +26227,9 @@ Discarded input sections
  .debug_abbrev  0x0000000000000000       0x28 ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-new.o
  .debug_aranges
                 0x0000000000000000       0x18 ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-new.o
- .debug_macro   0x0000000000000000      0x4b2 ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-new.o
+ .debug_macro   0x0000000000000000      0x516 ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-new.o
  .debug_macro   0x0000000000000000      0xac6 ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-new.o
- .debug_macro   0x0000000000000000      0x232 ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-new.o
+ .debug_macro   0x0000000000000000      0x24a ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-new.o
  .debug_macro   0x0000000000000000       0x2e ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-new.o
  .debug_macro   0x0000000000000000       0x3b ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-new.o
  .debug_macro   0x0000000000000000       0x22 ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-new.o
@@ -19011,6 +26277,7 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x129 ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-new.o
  .debug_macro   0x0000000000000000      0x3f9 ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-new.o
  .debug_macro   0x0000000000000000      0x275 ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-new.o
+ .debug_macro   0x0000000000000000      0xe42 ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-new.o
  .debug_macro   0x0000000000000000      0x3ca ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-new.o
  .debug_macro   0x0000000000000000      0x45c ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-new.o
  .debug_macro   0x0000000000000000       0x3c ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-new.o
@@ -19021,8 +26288,16 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x1c4 ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-new.o
  .debug_macro   0x0000000000000000      0x22a ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-new.o
  .debug_macro   0x0000000000000000       0x35 ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-new.o
+ .debug_macro   0x0000000000000000      0x830 ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-new.o
+ .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-new.o
+ .debug_macro   0x0000000000000000      0x1ce ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-new.o
+ .debug_macro   0x0000000000000000      0xb1d ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-new.o
+ .debug_macro   0x0000000000000000      0x29f ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-new.o
+ .debug_macro   0x0000000000000000      0x693 ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-new.o
+ .debug_macro   0x0000000000000000       0xa6 ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-new.o
  .debug_macro   0x0000000000000000      0x5e6 ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-new.o
- .debug_macro   0x0000000000000000       0xd0 ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-new.o
+ .debug_macro   0x0000000000000000       0x58 ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-new.o
+ .debug_macro   0x0000000000000000       0xe8 ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-new.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-new.o
  .debug_macro   0x0000000000000000       0x10 ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-new.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-new.o
@@ -19062,10 +26337,10 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x11f ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-new.o
  .debug_macro   0x0000000000000000       0x82 ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-new.o
  .debug_macro   0x0000000000000000       0x66 ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-new.o
- .debug_macro   0x0000000000000000      0x756 ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-new.o
+ .debug_macro   0x0000000000000000      0x739 ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-new.o
  .debug_macro   0x0000000000000000       0x2f ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-new.o
- .debug_line    0x0000000000000000      0xbc2 ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-new.o
- .debug_str     0x0000000000000000   0x13e8ef ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-new.o
+ .debug_line    0x0000000000000000      0xca3 ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-new.o
+ .debug_str     0x0000000000000000   0x15d163 ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-new.o
  .comment       0x0000000000000000       0x44 ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-new.o
  .ARM.attributes
                 0x0000000000000000       0x32 ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-new.o
@@ -19171,6 +26446,15 @@ Discarded input sections
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap_ms.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap_ms.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap_ms.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap_ms.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap_ms.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap_ms.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap_ms.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap_ms.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap_ms.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap_ms.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap_ms.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap_ms.o
  .text          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap_ms.o
  .data          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap_ms.o
  .bss           0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap_ms.o
@@ -19178,9 +26462,9 @@ Discarded input sections
  .debug_abbrev  0x0000000000000000       0x28 ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap_ms.o
  .debug_aranges
                 0x0000000000000000       0x18 ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap_ms.o
- .debug_macro   0x0000000000000000      0x4b2 ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap_ms.o
+ .debug_macro   0x0000000000000000      0x516 ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap_ms.o
  .debug_macro   0x0000000000000000      0xac6 ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap_ms.o
- .debug_macro   0x0000000000000000      0x232 ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap_ms.o
+ .debug_macro   0x0000000000000000      0x24a ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap_ms.o
  .debug_macro   0x0000000000000000       0x2e ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap_ms.o
  .debug_macro   0x0000000000000000       0x3b ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap_ms.o
  .debug_macro   0x0000000000000000       0x22 ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap_ms.o
@@ -19228,6 +26512,7 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x129 ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap_ms.o
  .debug_macro   0x0000000000000000      0x3f9 ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap_ms.o
  .debug_macro   0x0000000000000000      0x275 ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap_ms.o
+ .debug_macro   0x0000000000000000      0xe42 ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap_ms.o
  .debug_macro   0x0000000000000000      0x3ca ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap_ms.o
  .debug_macro   0x0000000000000000      0x45c ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap_ms.o
  .debug_macro   0x0000000000000000       0x3c ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap_ms.o
@@ -19238,8 +26523,16 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x1c4 ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap_ms.o
  .debug_macro   0x0000000000000000      0x22a ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap_ms.o
  .debug_macro   0x0000000000000000       0x35 ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap_ms.o
+ .debug_macro   0x0000000000000000      0x830 ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap_ms.o
+ .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap_ms.o
+ .debug_macro   0x0000000000000000      0x1ce ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap_ms.o
+ .debug_macro   0x0000000000000000      0xb1d ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap_ms.o
+ .debug_macro   0x0000000000000000      0x29f ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap_ms.o
+ .debug_macro   0x0000000000000000      0x693 ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap_ms.o
+ .debug_macro   0x0000000000000000       0xa6 ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap_ms.o
  .debug_macro   0x0000000000000000      0x5e6 ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap_ms.o
- .debug_macro   0x0000000000000000       0xd0 ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap_ms.o
+ .debug_macro   0x0000000000000000       0x58 ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap_ms.o
+ .debug_macro   0x0000000000000000       0xe8 ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap_ms.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap_ms.o
  .debug_macro   0x0000000000000000       0x10 ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap_ms.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap_ms.o
@@ -19279,10 +26572,10 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x11f ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap_ms.o
  .debug_macro   0x0000000000000000       0x82 ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap_ms.o
  .debug_macro   0x0000000000000000       0x66 ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap_ms.o
- .debug_macro   0x0000000000000000      0x756 ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap_ms.o
+ .debug_macro   0x0000000000000000      0x739 ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap_ms.o
  .debug_macro   0x0000000000000000       0x2f ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap_ms.o
- .debug_line    0x0000000000000000      0xbc1 ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap_ms.o
- .debug_str     0x0000000000000000   0x13e8ee ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap_ms.o
+ .debug_line    0x0000000000000000      0xca2 ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap_ms.o
+ .debug_str     0x0000000000000000   0x15d162 ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap_ms.o
  .comment       0x0000000000000000       0x44 ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap_ms.o
  .ARM.attributes
                 0x0000000000000000       0x32 ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap_ms.o
@@ -19388,6 +26681,15 @@ Discarded input sections
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/demand.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/demand.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/demand.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/demand.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/demand.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/demand.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/demand.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/demand.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/demand.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/demand.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/demand.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/demand.o
  .text          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/netif/ppp/demand.o
  .data          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/netif/ppp/demand.o
  .bss           0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/netif/ppp/demand.o
@@ -19395,9 +26697,9 @@ Discarded input sections
  .debug_abbrev  0x0000000000000000       0x28 ./Middlewares/Third_Party/LwIP/src/netif/ppp/demand.o
  .debug_aranges
                 0x0000000000000000       0x18 ./Middlewares/Third_Party/LwIP/src/netif/ppp/demand.o
- .debug_macro   0x0000000000000000      0x4b2 ./Middlewares/Third_Party/LwIP/src/netif/ppp/demand.o
+ .debug_macro   0x0000000000000000      0x516 ./Middlewares/Third_Party/LwIP/src/netif/ppp/demand.o
  .debug_macro   0x0000000000000000      0xac6 ./Middlewares/Third_Party/LwIP/src/netif/ppp/demand.o
- .debug_macro   0x0000000000000000      0x232 ./Middlewares/Third_Party/LwIP/src/netif/ppp/demand.o
+ .debug_macro   0x0000000000000000      0x24a ./Middlewares/Third_Party/LwIP/src/netif/ppp/demand.o
  .debug_macro   0x0000000000000000       0x2e ./Middlewares/Third_Party/LwIP/src/netif/ppp/demand.o
  .debug_macro   0x0000000000000000       0x3b ./Middlewares/Third_Party/LwIP/src/netif/ppp/demand.o
  .debug_macro   0x0000000000000000       0x22 ./Middlewares/Third_Party/LwIP/src/netif/ppp/demand.o
@@ -19445,6 +26747,7 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x129 ./Middlewares/Third_Party/LwIP/src/netif/ppp/demand.o
  .debug_macro   0x0000000000000000      0x3f9 ./Middlewares/Third_Party/LwIP/src/netif/ppp/demand.o
  .debug_macro   0x0000000000000000      0x275 ./Middlewares/Third_Party/LwIP/src/netif/ppp/demand.o
+ .debug_macro   0x0000000000000000      0xe42 ./Middlewares/Third_Party/LwIP/src/netif/ppp/demand.o
  .debug_macro   0x0000000000000000      0x3ca ./Middlewares/Third_Party/LwIP/src/netif/ppp/demand.o
  .debug_macro   0x0000000000000000      0x45c ./Middlewares/Third_Party/LwIP/src/netif/ppp/demand.o
  .debug_macro   0x0000000000000000       0x3c ./Middlewares/Third_Party/LwIP/src/netif/ppp/demand.o
@@ -19455,8 +26758,16 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x1c4 ./Middlewares/Third_Party/LwIP/src/netif/ppp/demand.o
  .debug_macro   0x0000000000000000      0x22a ./Middlewares/Third_Party/LwIP/src/netif/ppp/demand.o
  .debug_macro   0x0000000000000000       0x35 ./Middlewares/Third_Party/LwIP/src/netif/ppp/demand.o
+ .debug_macro   0x0000000000000000      0x830 ./Middlewares/Third_Party/LwIP/src/netif/ppp/demand.o
+ .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/netif/ppp/demand.o
+ .debug_macro   0x0000000000000000      0x1ce ./Middlewares/Third_Party/LwIP/src/netif/ppp/demand.o
+ .debug_macro   0x0000000000000000      0xb1d ./Middlewares/Third_Party/LwIP/src/netif/ppp/demand.o
+ .debug_macro   0x0000000000000000      0x29f ./Middlewares/Third_Party/LwIP/src/netif/ppp/demand.o
+ .debug_macro   0x0000000000000000      0x693 ./Middlewares/Third_Party/LwIP/src/netif/ppp/demand.o
+ .debug_macro   0x0000000000000000       0xa6 ./Middlewares/Third_Party/LwIP/src/netif/ppp/demand.o
  .debug_macro   0x0000000000000000      0x5e6 ./Middlewares/Third_Party/LwIP/src/netif/ppp/demand.o
- .debug_macro   0x0000000000000000       0xd0 ./Middlewares/Third_Party/LwIP/src/netif/ppp/demand.o
+ .debug_macro   0x0000000000000000       0x58 ./Middlewares/Third_Party/LwIP/src/netif/ppp/demand.o
+ .debug_macro   0x0000000000000000       0xe8 ./Middlewares/Third_Party/LwIP/src/netif/ppp/demand.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/netif/ppp/demand.o
  .debug_macro   0x0000000000000000       0x10 ./Middlewares/Third_Party/LwIP/src/netif/ppp/demand.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/netif/ppp/demand.o
@@ -19496,10 +26807,10 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x11f ./Middlewares/Third_Party/LwIP/src/netif/ppp/demand.o
  .debug_macro   0x0000000000000000       0x82 ./Middlewares/Third_Party/LwIP/src/netif/ppp/demand.o
  .debug_macro   0x0000000000000000       0x66 ./Middlewares/Third_Party/LwIP/src/netif/ppp/demand.o
- .debug_macro   0x0000000000000000      0x756 ./Middlewares/Third_Party/LwIP/src/netif/ppp/demand.o
+ .debug_macro   0x0000000000000000      0x739 ./Middlewares/Third_Party/LwIP/src/netif/ppp/demand.o
  .debug_macro   0x0000000000000000       0x2f ./Middlewares/Third_Party/LwIP/src/netif/ppp/demand.o
- .debug_line    0x0000000000000000      0xbc0 ./Middlewares/Third_Party/LwIP/src/netif/ppp/demand.o
- .debug_str     0x0000000000000000   0x13e8ed ./Middlewares/Third_Party/LwIP/src/netif/ppp/demand.o
+ .debug_line    0x0000000000000000      0xca1 ./Middlewares/Third_Party/LwIP/src/netif/ppp/demand.o
+ .debug_str     0x0000000000000000   0x15d161 ./Middlewares/Third_Party/LwIP/src/netif/ppp/demand.o
  .comment       0x0000000000000000       0x44 ./Middlewares/Third_Party/LwIP/src/netif/ppp/demand.o
  .ARM.attributes
                 0x0000000000000000       0x32 ./Middlewares/Third_Party/LwIP/src/netif/ppp/demand.o
@@ -19605,6 +26916,15 @@ Discarded input sections
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/eap.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/eap.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/eap.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/eap.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/eap.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/eap.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/eap.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/eap.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/eap.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/eap.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/eap.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/eap.o
  .text          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/netif/ppp/eap.o
  .data          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/netif/ppp/eap.o
  .bss           0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/netif/ppp/eap.o
@@ -19612,9 +26932,9 @@ Discarded input sections
  .debug_abbrev  0x0000000000000000       0x28 ./Middlewares/Third_Party/LwIP/src/netif/ppp/eap.o
  .debug_aranges
                 0x0000000000000000       0x18 ./Middlewares/Third_Party/LwIP/src/netif/ppp/eap.o
- .debug_macro   0x0000000000000000      0x4b2 ./Middlewares/Third_Party/LwIP/src/netif/ppp/eap.o
+ .debug_macro   0x0000000000000000      0x516 ./Middlewares/Third_Party/LwIP/src/netif/ppp/eap.o
  .debug_macro   0x0000000000000000      0xac6 ./Middlewares/Third_Party/LwIP/src/netif/ppp/eap.o
- .debug_macro   0x0000000000000000      0x232 ./Middlewares/Third_Party/LwIP/src/netif/ppp/eap.o
+ .debug_macro   0x0000000000000000      0x24a ./Middlewares/Third_Party/LwIP/src/netif/ppp/eap.o
  .debug_macro   0x0000000000000000       0x2e ./Middlewares/Third_Party/LwIP/src/netif/ppp/eap.o
  .debug_macro   0x0000000000000000       0x3b ./Middlewares/Third_Party/LwIP/src/netif/ppp/eap.o
  .debug_macro   0x0000000000000000       0x22 ./Middlewares/Third_Party/LwIP/src/netif/ppp/eap.o
@@ -19662,6 +26982,7 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x129 ./Middlewares/Third_Party/LwIP/src/netif/ppp/eap.o
  .debug_macro   0x0000000000000000      0x3f9 ./Middlewares/Third_Party/LwIP/src/netif/ppp/eap.o
  .debug_macro   0x0000000000000000      0x275 ./Middlewares/Third_Party/LwIP/src/netif/ppp/eap.o
+ .debug_macro   0x0000000000000000      0xe42 ./Middlewares/Third_Party/LwIP/src/netif/ppp/eap.o
  .debug_macro   0x0000000000000000      0x3ca ./Middlewares/Third_Party/LwIP/src/netif/ppp/eap.o
  .debug_macro   0x0000000000000000      0x45c ./Middlewares/Third_Party/LwIP/src/netif/ppp/eap.o
  .debug_macro   0x0000000000000000       0x3c ./Middlewares/Third_Party/LwIP/src/netif/ppp/eap.o
@@ -19672,8 +26993,16 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x1c4 ./Middlewares/Third_Party/LwIP/src/netif/ppp/eap.o
  .debug_macro   0x0000000000000000      0x22a ./Middlewares/Third_Party/LwIP/src/netif/ppp/eap.o
  .debug_macro   0x0000000000000000       0x35 ./Middlewares/Third_Party/LwIP/src/netif/ppp/eap.o
+ .debug_macro   0x0000000000000000      0x830 ./Middlewares/Third_Party/LwIP/src/netif/ppp/eap.o
+ .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/netif/ppp/eap.o
+ .debug_macro   0x0000000000000000      0x1ce ./Middlewares/Third_Party/LwIP/src/netif/ppp/eap.o
+ .debug_macro   0x0000000000000000      0xb1d ./Middlewares/Third_Party/LwIP/src/netif/ppp/eap.o
+ .debug_macro   0x0000000000000000      0x29f ./Middlewares/Third_Party/LwIP/src/netif/ppp/eap.o
+ .debug_macro   0x0000000000000000      0x693 ./Middlewares/Third_Party/LwIP/src/netif/ppp/eap.o
+ .debug_macro   0x0000000000000000       0xa6 ./Middlewares/Third_Party/LwIP/src/netif/ppp/eap.o
  .debug_macro   0x0000000000000000      0x5e6 ./Middlewares/Third_Party/LwIP/src/netif/ppp/eap.o
- .debug_macro   0x0000000000000000       0xd0 ./Middlewares/Third_Party/LwIP/src/netif/ppp/eap.o
+ .debug_macro   0x0000000000000000       0x58 ./Middlewares/Third_Party/LwIP/src/netif/ppp/eap.o
+ .debug_macro   0x0000000000000000       0xe8 ./Middlewares/Third_Party/LwIP/src/netif/ppp/eap.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/netif/ppp/eap.o
  .debug_macro   0x0000000000000000       0x10 ./Middlewares/Third_Party/LwIP/src/netif/ppp/eap.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/netif/ppp/eap.o
@@ -19713,10 +27042,10 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x11f ./Middlewares/Third_Party/LwIP/src/netif/ppp/eap.o
  .debug_macro   0x0000000000000000       0x82 ./Middlewares/Third_Party/LwIP/src/netif/ppp/eap.o
  .debug_macro   0x0000000000000000       0x66 ./Middlewares/Third_Party/LwIP/src/netif/ppp/eap.o
- .debug_macro   0x0000000000000000      0x756 ./Middlewares/Third_Party/LwIP/src/netif/ppp/eap.o
+ .debug_macro   0x0000000000000000      0x739 ./Middlewares/Third_Party/LwIP/src/netif/ppp/eap.o
  .debug_macro   0x0000000000000000       0x2f ./Middlewares/Third_Party/LwIP/src/netif/ppp/eap.o
- .debug_line    0x0000000000000000      0xbbd ./Middlewares/Third_Party/LwIP/src/netif/ppp/eap.o
- .debug_str     0x0000000000000000   0x13e8ea ./Middlewares/Third_Party/LwIP/src/netif/ppp/eap.o
+ .debug_line    0x0000000000000000      0xc9e ./Middlewares/Third_Party/LwIP/src/netif/ppp/eap.o
+ .debug_str     0x0000000000000000   0x15d15e ./Middlewares/Third_Party/LwIP/src/netif/ppp/eap.o
  .comment       0x0000000000000000       0x44 ./Middlewares/Third_Party/LwIP/src/netif/ppp/eap.o
  .ARM.attributes
                 0x0000000000000000       0x32 ./Middlewares/Third_Party/LwIP/src/netif/ppp/eap.o
@@ -19822,6 +27151,15 @@ Discarded input sections
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/ecp.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/ecp.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/ecp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/ecp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/ecp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/ecp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/ecp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/ecp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/ecp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/ecp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/ecp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/ecp.o
  .text          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ecp.o
  .data          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ecp.o
  .bss           0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ecp.o
@@ -19829,9 +27167,9 @@ Discarded input sections
  .debug_abbrev  0x0000000000000000       0x28 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ecp.o
  .debug_aranges
                 0x0000000000000000       0x18 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ecp.o
- .debug_macro   0x0000000000000000      0x4b2 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ecp.o
+ .debug_macro   0x0000000000000000      0x516 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ecp.o
  .debug_macro   0x0000000000000000      0xac6 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ecp.o
- .debug_macro   0x0000000000000000      0x232 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ecp.o
+ .debug_macro   0x0000000000000000      0x24a ./Middlewares/Third_Party/LwIP/src/netif/ppp/ecp.o
  .debug_macro   0x0000000000000000       0x2e ./Middlewares/Third_Party/LwIP/src/netif/ppp/ecp.o
  .debug_macro   0x0000000000000000       0x3b ./Middlewares/Third_Party/LwIP/src/netif/ppp/ecp.o
  .debug_macro   0x0000000000000000       0x22 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ecp.o
@@ -19879,6 +27217,7 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x129 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ecp.o
  .debug_macro   0x0000000000000000      0x3f9 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ecp.o
  .debug_macro   0x0000000000000000      0x275 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ecp.o
+ .debug_macro   0x0000000000000000      0xe42 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ecp.o
  .debug_macro   0x0000000000000000      0x3ca ./Middlewares/Third_Party/LwIP/src/netif/ppp/ecp.o
  .debug_macro   0x0000000000000000      0x45c ./Middlewares/Third_Party/LwIP/src/netif/ppp/ecp.o
  .debug_macro   0x0000000000000000       0x3c ./Middlewares/Third_Party/LwIP/src/netif/ppp/ecp.o
@@ -19889,8 +27228,16 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x1c4 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ecp.o
  .debug_macro   0x0000000000000000      0x22a ./Middlewares/Third_Party/LwIP/src/netif/ppp/ecp.o
  .debug_macro   0x0000000000000000       0x35 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ecp.o
+ .debug_macro   0x0000000000000000      0x830 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ecp.o
+ .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ecp.o
+ .debug_macro   0x0000000000000000      0x1ce ./Middlewares/Third_Party/LwIP/src/netif/ppp/ecp.o
+ .debug_macro   0x0000000000000000      0xb1d ./Middlewares/Third_Party/LwIP/src/netif/ppp/ecp.o
+ .debug_macro   0x0000000000000000      0x29f ./Middlewares/Third_Party/LwIP/src/netif/ppp/ecp.o
+ .debug_macro   0x0000000000000000      0x693 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ecp.o
+ .debug_macro   0x0000000000000000       0xa6 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ecp.o
  .debug_macro   0x0000000000000000      0x5e6 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ecp.o
- .debug_macro   0x0000000000000000       0xd0 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ecp.o
+ .debug_macro   0x0000000000000000       0x58 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ecp.o
+ .debug_macro   0x0000000000000000       0xe8 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ecp.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ecp.o
  .debug_macro   0x0000000000000000       0x10 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ecp.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ecp.o
@@ -19930,10 +27277,10 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x11f ./Middlewares/Third_Party/LwIP/src/netif/ppp/ecp.o
  .debug_macro   0x0000000000000000       0x82 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ecp.o
  .debug_macro   0x0000000000000000       0x66 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ecp.o
- .debug_macro   0x0000000000000000      0x756 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ecp.o
+ .debug_macro   0x0000000000000000      0x739 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ecp.o
  .debug_macro   0x0000000000000000       0x2f ./Middlewares/Third_Party/LwIP/src/netif/ppp/ecp.o
- .debug_line    0x0000000000000000      0xbbd ./Middlewares/Third_Party/LwIP/src/netif/ppp/ecp.o
- .debug_str     0x0000000000000000   0x13e8ea ./Middlewares/Third_Party/LwIP/src/netif/ppp/ecp.o
+ .debug_line    0x0000000000000000      0xc9e ./Middlewares/Third_Party/LwIP/src/netif/ppp/ecp.o
+ .debug_str     0x0000000000000000   0x15d15e ./Middlewares/Third_Party/LwIP/src/netif/ppp/ecp.o
  .comment       0x0000000000000000       0x44 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ecp.o
  .ARM.attributes
                 0x0000000000000000       0x32 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ecp.o
@@ -20039,6 +27386,15 @@ Discarded input sections
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/eui64.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/eui64.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/eui64.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/eui64.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/eui64.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/eui64.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/eui64.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/eui64.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/eui64.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/eui64.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/eui64.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/eui64.o
  .text          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/netif/ppp/eui64.o
  .data          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/netif/ppp/eui64.o
  .bss           0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/netif/ppp/eui64.o
@@ -20046,9 +27402,9 @@ Discarded input sections
  .debug_abbrev  0x0000000000000000       0x28 ./Middlewares/Third_Party/LwIP/src/netif/ppp/eui64.o
  .debug_aranges
                 0x0000000000000000       0x18 ./Middlewares/Third_Party/LwIP/src/netif/ppp/eui64.o
- .debug_macro   0x0000000000000000      0x4b2 ./Middlewares/Third_Party/LwIP/src/netif/ppp/eui64.o
+ .debug_macro   0x0000000000000000      0x516 ./Middlewares/Third_Party/LwIP/src/netif/ppp/eui64.o
  .debug_macro   0x0000000000000000      0xac6 ./Middlewares/Third_Party/LwIP/src/netif/ppp/eui64.o
- .debug_macro   0x0000000000000000      0x232 ./Middlewares/Third_Party/LwIP/src/netif/ppp/eui64.o
+ .debug_macro   0x0000000000000000      0x24a ./Middlewares/Third_Party/LwIP/src/netif/ppp/eui64.o
  .debug_macro   0x0000000000000000       0x2e ./Middlewares/Third_Party/LwIP/src/netif/ppp/eui64.o
  .debug_macro   0x0000000000000000       0x3b ./Middlewares/Third_Party/LwIP/src/netif/ppp/eui64.o
  .debug_macro   0x0000000000000000       0x22 ./Middlewares/Third_Party/LwIP/src/netif/ppp/eui64.o
@@ -20096,6 +27452,7 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x129 ./Middlewares/Third_Party/LwIP/src/netif/ppp/eui64.o
  .debug_macro   0x0000000000000000      0x3f9 ./Middlewares/Third_Party/LwIP/src/netif/ppp/eui64.o
  .debug_macro   0x0000000000000000      0x275 ./Middlewares/Third_Party/LwIP/src/netif/ppp/eui64.o
+ .debug_macro   0x0000000000000000      0xe42 ./Middlewares/Third_Party/LwIP/src/netif/ppp/eui64.o
  .debug_macro   0x0000000000000000      0x3ca ./Middlewares/Third_Party/LwIP/src/netif/ppp/eui64.o
  .debug_macro   0x0000000000000000      0x45c ./Middlewares/Third_Party/LwIP/src/netif/ppp/eui64.o
  .debug_macro   0x0000000000000000       0x3c ./Middlewares/Third_Party/LwIP/src/netif/ppp/eui64.o
@@ -20106,8 +27463,16 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x1c4 ./Middlewares/Third_Party/LwIP/src/netif/ppp/eui64.o
  .debug_macro   0x0000000000000000      0x22a ./Middlewares/Third_Party/LwIP/src/netif/ppp/eui64.o
  .debug_macro   0x0000000000000000       0x35 ./Middlewares/Third_Party/LwIP/src/netif/ppp/eui64.o
+ .debug_macro   0x0000000000000000      0x830 ./Middlewares/Third_Party/LwIP/src/netif/ppp/eui64.o
+ .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/netif/ppp/eui64.o
+ .debug_macro   0x0000000000000000      0x1ce ./Middlewares/Third_Party/LwIP/src/netif/ppp/eui64.o
+ .debug_macro   0x0000000000000000      0xb1d ./Middlewares/Third_Party/LwIP/src/netif/ppp/eui64.o
+ .debug_macro   0x0000000000000000      0x29f ./Middlewares/Third_Party/LwIP/src/netif/ppp/eui64.o
+ .debug_macro   0x0000000000000000      0x693 ./Middlewares/Third_Party/LwIP/src/netif/ppp/eui64.o
+ .debug_macro   0x0000000000000000       0xa6 ./Middlewares/Third_Party/LwIP/src/netif/ppp/eui64.o
  .debug_macro   0x0000000000000000      0x5e6 ./Middlewares/Third_Party/LwIP/src/netif/ppp/eui64.o
- .debug_macro   0x0000000000000000       0xd0 ./Middlewares/Third_Party/LwIP/src/netif/ppp/eui64.o
+ .debug_macro   0x0000000000000000       0x58 ./Middlewares/Third_Party/LwIP/src/netif/ppp/eui64.o
+ .debug_macro   0x0000000000000000       0xe8 ./Middlewares/Third_Party/LwIP/src/netif/ppp/eui64.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/netif/ppp/eui64.o
  .debug_macro   0x0000000000000000       0x10 ./Middlewares/Third_Party/LwIP/src/netif/ppp/eui64.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/netif/ppp/eui64.o
@@ -20147,10 +27512,10 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x11f ./Middlewares/Third_Party/LwIP/src/netif/ppp/eui64.o
  .debug_macro   0x0000000000000000       0x82 ./Middlewares/Third_Party/LwIP/src/netif/ppp/eui64.o
  .debug_macro   0x0000000000000000       0x66 ./Middlewares/Third_Party/LwIP/src/netif/ppp/eui64.o
- .debug_macro   0x0000000000000000      0x756 ./Middlewares/Third_Party/LwIP/src/netif/ppp/eui64.o
+ .debug_macro   0x0000000000000000      0x739 ./Middlewares/Third_Party/LwIP/src/netif/ppp/eui64.o
  .debug_macro   0x0000000000000000       0x2f ./Middlewares/Third_Party/LwIP/src/netif/ppp/eui64.o
- .debug_line    0x0000000000000000      0xbbf ./Middlewares/Third_Party/LwIP/src/netif/ppp/eui64.o
- .debug_str     0x0000000000000000   0x13e8ec ./Middlewares/Third_Party/LwIP/src/netif/ppp/eui64.o
+ .debug_line    0x0000000000000000      0xca0 ./Middlewares/Third_Party/LwIP/src/netif/ppp/eui64.o
+ .debug_str     0x0000000000000000   0x15d160 ./Middlewares/Third_Party/LwIP/src/netif/ppp/eui64.o
  .comment       0x0000000000000000       0x44 ./Middlewares/Third_Party/LwIP/src/netif/ppp/eui64.o
  .ARM.attributes
                 0x0000000000000000       0x32 ./Middlewares/Third_Party/LwIP/src/netif/ppp/eui64.o
@@ -20256,6 +27621,15 @@ Discarded input sections
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/fsm.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/fsm.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/fsm.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/fsm.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/fsm.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/fsm.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/fsm.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/fsm.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/fsm.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/fsm.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/fsm.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/fsm.o
  .text          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/netif/ppp/fsm.o
  .data          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/netif/ppp/fsm.o
  .bss           0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/netif/ppp/fsm.o
@@ -20263,9 +27637,9 @@ Discarded input sections
  .debug_abbrev  0x0000000000000000       0x28 ./Middlewares/Third_Party/LwIP/src/netif/ppp/fsm.o
  .debug_aranges
                 0x0000000000000000       0x18 ./Middlewares/Third_Party/LwIP/src/netif/ppp/fsm.o
- .debug_macro   0x0000000000000000      0x4b2 ./Middlewares/Third_Party/LwIP/src/netif/ppp/fsm.o
+ .debug_macro   0x0000000000000000      0x516 ./Middlewares/Third_Party/LwIP/src/netif/ppp/fsm.o
  .debug_macro   0x0000000000000000      0xac6 ./Middlewares/Third_Party/LwIP/src/netif/ppp/fsm.o
- .debug_macro   0x0000000000000000      0x232 ./Middlewares/Third_Party/LwIP/src/netif/ppp/fsm.o
+ .debug_macro   0x0000000000000000      0x24a ./Middlewares/Third_Party/LwIP/src/netif/ppp/fsm.o
  .debug_macro   0x0000000000000000       0x2e ./Middlewares/Third_Party/LwIP/src/netif/ppp/fsm.o
  .debug_macro   0x0000000000000000       0x3b ./Middlewares/Third_Party/LwIP/src/netif/ppp/fsm.o
  .debug_macro   0x0000000000000000       0x22 ./Middlewares/Third_Party/LwIP/src/netif/ppp/fsm.o
@@ -20313,6 +27687,7 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x129 ./Middlewares/Third_Party/LwIP/src/netif/ppp/fsm.o
  .debug_macro   0x0000000000000000      0x3f9 ./Middlewares/Third_Party/LwIP/src/netif/ppp/fsm.o
  .debug_macro   0x0000000000000000      0x275 ./Middlewares/Third_Party/LwIP/src/netif/ppp/fsm.o
+ .debug_macro   0x0000000000000000      0xe42 ./Middlewares/Third_Party/LwIP/src/netif/ppp/fsm.o
  .debug_macro   0x0000000000000000      0x3ca ./Middlewares/Third_Party/LwIP/src/netif/ppp/fsm.o
  .debug_macro   0x0000000000000000      0x45c ./Middlewares/Third_Party/LwIP/src/netif/ppp/fsm.o
  .debug_macro   0x0000000000000000       0x3c ./Middlewares/Third_Party/LwIP/src/netif/ppp/fsm.o
@@ -20323,8 +27698,16 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x1c4 ./Middlewares/Third_Party/LwIP/src/netif/ppp/fsm.o
  .debug_macro   0x0000000000000000      0x22a ./Middlewares/Third_Party/LwIP/src/netif/ppp/fsm.o
  .debug_macro   0x0000000000000000       0x35 ./Middlewares/Third_Party/LwIP/src/netif/ppp/fsm.o
+ .debug_macro   0x0000000000000000      0x830 ./Middlewares/Third_Party/LwIP/src/netif/ppp/fsm.o
+ .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/netif/ppp/fsm.o
+ .debug_macro   0x0000000000000000      0x1ce ./Middlewares/Third_Party/LwIP/src/netif/ppp/fsm.o
+ .debug_macro   0x0000000000000000      0xb1d ./Middlewares/Third_Party/LwIP/src/netif/ppp/fsm.o
+ .debug_macro   0x0000000000000000      0x29f ./Middlewares/Third_Party/LwIP/src/netif/ppp/fsm.o
+ .debug_macro   0x0000000000000000      0x693 ./Middlewares/Third_Party/LwIP/src/netif/ppp/fsm.o
+ .debug_macro   0x0000000000000000       0xa6 ./Middlewares/Third_Party/LwIP/src/netif/ppp/fsm.o
  .debug_macro   0x0000000000000000      0x5e6 ./Middlewares/Third_Party/LwIP/src/netif/ppp/fsm.o
- .debug_macro   0x0000000000000000       0xd0 ./Middlewares/Third_Party/LwIP/src/netif/ppp/fsm.o
+ .debug_macro   0x0000000000000000       0x58 ./Middlewares/Third_Party/LwIP/src/netif/ppp/fsm.o
+ .debug_macro   0x0000000000000000       0xe8 ./Middlewares/Third_Party/LwIP/src/netif/ppp/fsm.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/netif/ppp/fsm.o
  .debug_macro   0x0000000000000000       0x10 ./Middlewares/Third_Party/LwIP/src/netif/ppp/fsm.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/netif/ppp/fsm.o
@@ -20364,10 +27747,10 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x11f ./Middlewares/Third_Party/LwIP/src/netif/ppp/fsm.o
  .debug_macro   0x0000000000000000       0x82 ./Middlewares/Third_Party/LwIP/src/netif/ppp/fsm.o
  .debug_macro   0x0000000000000000       0x66 ./Middlewares/Third_Party/LwIP/src/netif/ppp/fsm.o
- .debug_macro   0x0000000000000000      0x756 ./Middlewares/Third_Party/LwIP/src/netif/ppp/fsm.o
+ .debug_macro   0x0000000000000000      0x739 ./Middlewares/Third_Party/LwIP/src/netif/ppp/fsm.o
  .debug_macro   0x0000000000000000       0x2f ./Middlewares/Third_Party/LwIP/src/netif/ppp/fsm.o
- .debug_line    0x0000000000000000      0xbbd ./Middlewares/Third_Party/LwIP/src/netif/ppp/fsm.o
- .debug_str     0x0000000000000000   0x13e8ea ./Middlewares/Third_Party/LwIP/src/netif/ppp/fsm.o
+ .debug_line    0x0000000000000000      0xc9e ./Middlewares/Third_Party/LwIP/src/netif/ppp/fsm.o
+ .debug_str     0x0000000000000000   0x15d15e ./Middlewares/Third_Party/LwIP/src/netif/ppp/fsm.o
  .comment       0x0000000000000000       0x44 ./Middlewares/Third_Party/LwIP/src/netif/ppp/fsm.o
  .ARM.attributes
                 0x0000000000000000       0x32 ./Middlewares/Third_Party/LwIP/src/netif/ppp/fsm.o
@@ -20473,6 +27856,15 @@ Discarded input sections
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipcp.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipcp.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipcp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipcp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipcp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipcp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipcp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipcp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipcp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipcp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipcp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipcp.o
  .text          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipcp.o
  .data          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipcp.o
  .bss           0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipcp.o
@@ -20480,9 +27872,9 @@ Discarded input sections
  .debug_abbrev  0x0000000000000000       0x28 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipcp.o
  .debug_aranges
                 0x0000000000000000       0x18 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipcp.o
- .debug_macro   0x0000000000000000      0x4b2 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipcp.o
+ .debug_macro   0x0000000000000000      0x516 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipcp.o
  .debug_macro   0x0000000000000000      0xac6 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipcp.o
- .debug_macro   0x0000000000000000      0x232 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipcp.o
+ .debug_macro   0x0000000000000000      0x24a ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipcp.o
  .debug_macro   0x0000000000000000       0x2e ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipcp.o
  .debug_macro   0x0000000000000000       0x3b ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipcp.o
  .debug_macro   0x0000000000000000       0x22 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipcp.o
@@ -20530,6 +27922,7 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x129 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipcp.o
  .debug_macro   0x0000000000000000      0x3f9 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipcp.o
  .debug_macro   0x0000000000000000      0x275 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipcp.o
+ .debug_macro   0x0000000000000000      0xe42 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipcp.o
  .debug_macro   0x0000000000000000      0x3ca ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipcp.o
  .debug_macro   0x0000000000000000      0x45c ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipcp.o
  .debug_macro   0x0000000000000000       0x3c ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipcp.o
@@ -20540,8 +27933,16 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x1c4 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipcp.o
  .debug_macro   0x0000000000000000      0x22a ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipcp.o
  .debug_macro   0x0000000000000000       0x35 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipcp.o
+ .debug_macro   0x0000000000000000      0x830 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipcp.o
+ .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipcp.o
+ .debug_macro   0x0000000000000000      0x1ce ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipcp.o
+ .debug_macro   0x0000000000000000      0xb1d ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipcp.o
+ .debug_macro   0x0000000000000000      0x29f ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipcp.o
+ .debug_macro   0x0000000000000000      0x693 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipcp.o
+ .debug_macro   0x0000000000000000       0xa6 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipcp.o
  .debug_macro   0x0000000000000000      0x5e6 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipcp.o
- .debug_macro   0x0000000000000000       0xd0 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipcp.o
+ .debug_macro   0x0000000000000000       0x58 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipcp.o
+ .debug_macro   0x0000000000000000       0xe8 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipcp.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipcp.o
  .debug_macro   0x0000000000000000       0x10 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipcp.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipcp.o
@@ -20581,10 +27982,10 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x11f ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipcp.o
  .debug_macro   0x0000000000000000       0x82 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipcp.o
  .debug_macro   0x0000000000000000       0x66 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipcp.o
- .debug_macro   0x0000000000000000      0x756 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipcp.o
+ .debug_macro   0x0000000000000000      0x739 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipcp.o
  .debug_macro   0x0000000000000000       0x2f ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipcp.o
- .debug_line    0x0000000000000000      0xbbe ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipcp.o
- .debug_str     0x0000000000000000   0x13e8eb ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipcp.o
+ .debug_line    0x0000000000000000      0xc9f ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipcp.o
+ .debug_str     0x0000000000000000   0x15d15f ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipcp.o
  .comment       0x0000000000000000       0x44 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipcp.o
  .ARM.attributes
                 0x0000000000000000       0x32 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipcp.o
@@ -20690,6 +28091,15 @@ Discarded input sections
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipv6cp.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipv6cp.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipv6cp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipv6cp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipv6cp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipv6cp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipv6cp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipv6cp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipv6cp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipv6cp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipv6cp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipv6cp.o
  .text          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipv6cp.o
  .data          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipv6cp.o
  .bss           0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipv6cp.o
@@ -20697,9 +28107,9 @@ Discarded input sections
  .debug_abbrev  0x0000000000000000       0x28 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipv6cp.o
  .debug_aranges
                 0x0000000000000000       0x18 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipv6cp.o
- .debug_macro   0x0000000000000000      0x4b3 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipv6cp.o
+ .debug_macro   0x0000000000000000      0x517 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipv6cp.o
  .debug_macro   0x0000000000000000      0xac6 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipv6cp.o
- .debug_macro   0x0000000000000000      0x232 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipv6cp.o
+ .debug_macro   0x0000000000000000      0x24a ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipv6cp.o
  .debug_macro   0x0000000000000000       0x2e ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipv6cp.o
  .debug_macro   0x0000000000000000       0x3b ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipv6cp.o
  .debug_macro   0x0000000000000000       0x22 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipv6cp.o
@@ -20747,6 +28157,7 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x129 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipv6cp.o
  .debug_macro   0x0000000000000000      0x3f9 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipv6cp.o
  .debug_macro   0x0000000000000000      0x275 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipv6cp.o
+ .debug_macro   0x0000000000000000      0xe42 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipv6cp.o
  .debug_macro   0x0000000000000000      0x3ca ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipv6cp.o
  .debug_macro   0x0000000000000000      0x45c ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipv6cp.o
  .debug_macro   0x0000000000000000       0x3c ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipv6cp.o
@@ -20757,8 +28168,16 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x1c4 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipv6cp.o
  .debug_macro   0x0000000000000000      0x22a ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipv6cp.o
  .debug_macro   0x0000000000000000       0x35 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipv6cp.o
+ .debug_macro   0x0000000000000000      0x830 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipv6cp.o
+ .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipv6cp.o
+ .debug_macro   0x0000000000000000      0x1ce ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipv6cp.o
+ .debug_macro   0x0000000000000000      0xb1d ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipv6cp.o
+ .debug_macro   0x0000000000000000      0x29f ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipv6cp.o
+ .debug_macro   0x0000000000000000      0x693 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipv6cp.o
+ .debug_macro   0x0000000000000000       0xa6 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipv6cp.o
  .debug_macro   0x0000000000000000      0x5e6 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipv6cp.o
- .debug_macro   0x0000000000000000       0xd0 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipv6cp.o
+ .debug_macro   0x0000000000000000       0x58 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipv6cp.o
+ .debug_macro   0x0000000000000000       0xe8 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipv6cp.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipv6cp.o
  .debug_macro   0x0000000000000000       0x10 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipv6cp.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipv6cp.o
@@ -20798,10 +28217,10 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x11f ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipv6cp.o
  .debug_macro   0x0000000000000000       0x82 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipv6cp.o
  .debug_macro   0x0000000000000000       0x66 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipv6cp.o
- .debug_macro   0x0000000000000000      0x756 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipv6cp.o
+ .debug_macro   0x0000000000000000      0x739 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipv6cp.o
  .debug_macro   0x0000000000000000       0x2f ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipv6cp.o
- .debug_line    0x0000000000000000      0xbc0 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipv6cp.o
- .debug_str     0x0000000000000000   0x13e8ed ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipv6cp.o
+ .debug_line    0x0000000000000000      0xca1 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipv6cp.o
+ .debug_str     0x0000000000000000   0x15d161 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipv6cp.o
  .comment       0x0000000000000000       0x44 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipv6cp.o
  .ARM.attributes
                 0x0000000000000000       0x32 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipv6cp.o
@@ -20907,6 +28326,15 @@ Discarded input sections
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/lcp.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/lcp.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/lcp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/lcp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/lcp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/lcp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/lcp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/lcp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/lcp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/lcp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/lcp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/lcp.o
  .text          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/netif/ppp/lcp.o
  .data          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/netif/ppp/lcp.o
  .bss           0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/netif/ppp/lcp.o
@@ -20914,9 +28342,9 @@ Discarded input sections
  .debug_abbrev  0x0000000000000000       0x28 ./Middlewares/Third_Party/LwIP/src/netif/ppp/lcp.o
  .debug_aranges
                 0x0000000000000000       0x18 ./Middlewares/Third_Party/LwIP/src/netif/ppp/lcp.o
- .debug_macro   0x0000000000000000      0x4b2 ./Middlewares/Third_Party/LwIP/src/netif/ppp/lcp.o
+ .debug_macro   0x0000000000000000      0x516 ./Middlewares/Third_Party/LwIP/src/netif/ppp/lcp.o
  .debug_macro   0x0000000000000000      0xac6 ./Middlewares/Third_Party/LwIP/src/netif/ppp/lcp.o
- .debug_macro   0x0000000000000000      0x232 ./Middlewares/Third_Party/LwIP/src/netif/ppp/lcp.o
+ .debug_macro   0x0000000000000000      0x24a ./Middlewares/Third_Party/LwIP/src/netif/ppp/lcp.o
  .debug_macro   0x0000000000000000       0x2e ./Middlewares/Third_Party/LwIP/src/netif/ppp/lcp.o
  .debug_macro   0x0000000000000000       0x3b ./Middlewares/Third_Party/LwIP/src/netif/ppp/lcp.o
  .debug_macro   0x0000000000000000       0x22 ./Middlewares/Third_Party/LwIP/src/netif/ppp/lcp.o
@@ -20964,6 +28392,7 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x129 ./Middlewares/Third_Party/LwIP/src/netif/ppp/lcp.o
  .debug_macro   0x0000000000000000      0x3f9 ./Middlewares/Third_Party/LwIP/src/netif/ppp/lcp.o
  .debug_macro   0x0000000000000000      0x275 ./Middlewares/Third_Party/LwIP/src/netif/ppp/lcp.o
+ .debug_macro   0x0000000000000000      0xe42 ./Middlewares/Third_Party/LwIP/src/netif/ppp/lcp.o
  .debug_macro   0x0000000000000000      0x3ca ./Middlewares/Third_Party/LwIP/src/netif/ppp/lcp.o
  .debug_macro   0x0000000000000000      0x45c ./Middlewares/Third_Party/LwIP/src/netif/ppp/lcp.o
  .debug_macro   0x0000000000000000       0x3c ./Middlewares/Third_Party/LwIP/src/netif/ppp/lcp.o
@@ -20974,8 +28403,16 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x1c4 ./Middlewares/Third_Party/LwIP/src/netif/ppp/lcp.o
  .debug_macro   0x0000000000000000      0x22a ./Middlewares/Third_Party/LwIP/src/netif/ppp/lcp.o
  .debug_macro   0x0000000000000000       0x35 ./Middlewares/Third_Party/LwIP/src/netif/ppp/lcp.o
+ .debug_macro   0x0000000000000000      0x830 ./Middlewares/Third_Party/LwIP/src/netif/ppp/lcp.o
+ .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/netif/ppp/lcp.o
+ .debug_macro   0x0000000000000000      0x1ce ./Middlewares/Third_Party/LwIP/src/netif/ppp/lcp.o
+ .debug_macro   0x0000000000000000      0xb1d ./Middlewares/Third_Party/LwIP/src/netif/ppp/lcp.o
+ .debug_macro   0x0000000000000000      0x29f ./Middlewares/Third_Party/LwIP/src/netif/ppp/lcp.o
+ .debug_macro   0x0000000000000000      0x693 ./Middlewares/Third_Party/LwIP/src/netif/ppp/lcp.o
+ .debug_macro   0x0000000000000000       0xa6 ./Middlewares/Third_Party/LwIP/src/netif/ppp/lcp.o
  .debug_macro   0x0000000000000000      0x5e6 ./Middlewares/Third_Party/LwIP/src/netif/ppp/lcp.o
- .debug_macro   0x0000000000000000       0xd0 ./Middlewares/Third_Party/LwIP/src/netif/ppp/lcp.o
+ .debug_macro   0x0000000000000000       0x58 ./Middlewares/Third_Party/LwIP/src/netif/ppp/lcp.o
+ .debug_macro   0x0000000000000000       0xe8 ./Middlewares/Third_Party/LwIP/src/netif/ppp/lcp.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/netif/ppp/lcp.o
  .debug_macro   0x0000000000000000       0x10 ./Middlewares/Third_Party/LwIP/src/netif/ppp/lcp.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/netif/ppp/lcp.o
@@ -21015,10 +28452,10 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x11f ./Middlewares/Third_Party/LwIP/src/netif/ppp/lcp.o
  .debug_macro   0x0000000000000000       0x82 ./Middlewares/Third_Party/LwIP/src/netif/ppp/lcp.o
  .debug_macro   0x0000000000000000       0x66 ./Middlewares/Third_Party/LwIP/src/netif/ppp/lcp.o
- .debug_macro   0x0000000000000000      0x756 ./Middlewares/Third_Party/LwIP/src/netif/ppp/lcp.o
+ .debug_macro   0x0000000000000000      0x739 ./Middlewares/Third_Party/LwIP/src/netif/ppp/lcp.o
  .debug_macro   0x0000000000000000       0x2f ./Middlewares/Third_Party/LwIP/src/netif/ppp/lcp.o
- .debug_line    0x0000000000000000      0xbbd ./Middlewares/Third_Party/LwIP/src/netif/ppp/lcp.o
- .debug_str     0x0000000000000000   0x13e8ea ./Middlewares/Third_Party/LwIP/src/netif/ppp/lcp.o
+ .debug_line    0x0000000000000000      0xc9e ./Middlewares/Third_Party/LwIP/src/netif/ppp/lcp.o
+ .debug_str     0x0000000000000000   0x15d15e ./Middlewares/Third_Party/LwIP/src/netif/ppp/lcp.o
  .comment       0x0000000000000000       0x44 ./Middlewares/Third_Party/LwIP/src/netif/ppp/lcp.o
  .ARM.attributes
                 0x0000000000000000       0x32 ./Middlewares/Third_Party/LwIP/src/netif/ppp/lcp.o
@@ -21124,6 +28561,15 @@ Discarded input sections
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/magic.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/magic.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/magic.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/magic.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/magic.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/magic.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/magic.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/magic.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/magic.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/magic.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/magic.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/magic.o
  .text          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/netif/ppp/magic.o
  .data          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/netif/ppp/magic.o
  .bss           0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/netif/ppp/magic.o
@@ -21131,9 +28577,9 @@ Discarded input sections
  .debug_abbrev  0x0000000000000000       0x28 ./Middlewares/Third_Party/LwIP/src/netif/ppp/magic.o
  .debug_aranges
                 0x0000000000000000       0x18 ./Middlewares/Third_Party/LwIP/src/netif/ppp/magic.o
- .debug_macro   0x0000000000000000      0x4b2 ./Middlewares/Third_Party/LwIP/src/netif/ppp/magic.o
+ .debug_macro   0x0000000000000000      0x516 ./Middlewares/Third_Party/LwIP/src/netif/ppp/magic.o
  .debug_macro   0x0000000000000000      0xac6 ./Middlewares/Third_Party/LwIP/src/netif/ppp/magic.o
- .debug_macro   0x0000000000000000      0x232 ./Middlewares/Third_Party/LwIP/src/netif/ppp/magic.o
+ .debug_macro   0x0000000000000000      0x24a ./Middlewares/Third_Party/LwIP/src/netif/ppp/magic.o
  .debug_macro   0x0000000000000000       0x2e ./Middlewares/Third_Party/LwIP/src/netif/ppp/magic.o
  .debug_macro   0x0000000000000000       0x3b ./Middlewares/Third_Party/LwIP/src/netif/ppp/magic.o
  .debug_macro   0x0000000000000000       0x22 ./Middlewares/Third_Party/LwIP/src/netif/ppp/magic.o
@@ -21181,6 +28627,7 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x129 ./Middlewares/Third_Party/LwIP/src/netif/ppp/magic.o
  .debug_macro   0x0000000000000000      0x3f9 ./Middlewares/Third_Party/LwIP/src/netif/ppp/magic.o
  .debug_macro   0x0000000000000000      0x275 ./Middlewares/Third_Party/LwIP/src/netif/ppp/magic.o
+ .debug_macro   0x0000000000000000      0xe42 ./Middlewares/Third_Party/LwIP/src/netif/ppp/magic.o
  .debug_macro   0x0000000000000000      0x3ca ./Middlewares/Third_Party/LwIP/src/netif/ppp/magic.o
  .debug_macro   0x0000000000000000      0x45c ./Middlewares/Third_Party/LwIP/src/netif/ppp/magic.o
  .debug_macro   0x0000000000000000       0x3c ./Middlewares/Third_Party/LwIP/src/netif/ppp/magic.o
@@ -21191,8 +28638,16 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x1c4 ./Middlewares/Third_Party/LwIP/src/netif/ppp/magic.o
  .debug_macro   0x0000000000000000      0x22a ./Middlewares/Third_Party/LwIP/src/netif/ppp/magic.o
  .debug_macro   0x0000000000000000       0x35 ./Middlewares/Third_Party/LwIP/src/netif/ppp/magic.o
+ .debug_macro   0x0000000000000000      0x830 ./Middlewares/Third_Party/LwIP/src/netif/ppp/magic.o
+ .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/netif/ppp/magic.o
+ .debug_macro   0x0000000000000000      0x1ce ./Middlewares/Third_Party/LwIP/src/netif/ppp/magic.o
+ .debug_macro   0x0000000000000000      0xb1d ./Middlewares/Third_Party/LwIP/src/netif/ppp/magic.o
+ .debug_macro   0x0000000000000000      0x29f ./Middlewares/Third_Party/LwIP/src/netif/ppp/magic.o
+ .debug_macro   0x0000000000000000      0x693 ./Middlewares/Third_Party/LwIP/src/netif/ppp/magic.o
+ .debug_macro   0x0000000000000000       0xa6 ./Middlewares/Third_Party/LwIP/src/netif/ppp/magic.o
  .debug_macro   0x0000000000000000      0x5e6 ./Middlewares/Third_Party/LwIP/src/netif/ppp/magic.o
- .debug_macro   0x0000000000000000       0xd0 ./Middlewares/Third_Party/LwIP/src/netif/ppp/magic.o
+ .debug_macro   0x0000000000000000       0x58 ./Middlewares/Third_Party/LwIP/src/netif/ppp/magic.o
+ .debug_macro   0x0000000000000000       0xe8 ./Middlewares/Third_Party/LwIP/src/netif/ppp/magic.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/netif/ppp/magic.o
  .debug_macro   0x0000000000000000       0x10 ./Middlewares/Third_Party/LwIP/src/netif/ppp/magic.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/netif/ppp/magic.o
@@ -21232,10 +28687,10 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x11f ./Middlewares/Third_Party/LwIP/src/netif/ppp/magic.o
  .debug_macro   0x0000000000000000       0x82 ./Middlewares/Third_Party/LwIP/src/netif/ppp/magic.o
  .debug_macro   0x0000000000000000       0x66 ./Middlewares/Third_Party/LwIP/src/netif/ppp/magic.o
- .debug_macro   0x0000000000000000      0x756 ./Middlewares/Third_Party/LwIP/src/netif/ppp/magic.o
+ .debug_macro   0x0000000000000000      0x739 ./Middlewares/Third_Party/LwIP/src/netif/ppp/magic.o
  .debug_macro   0x0000000000000000       0x2f ./Middlewares/Third_Party/LwIP/src/netif/ppp/magic.o
- .debug_line    0x0000000000000000      0xbbf ./Middlewares/Third_Party/LwIP/src/netif/ppp/magic.o
- .debug_str     0x0000000000000000   0x13e8ec ./Middlewares/Third_Party/LwIP/src/netif/ppp/magic.o
+ .debug_line    0x0000000000000000      0xca0 ./Middlewares/Third_Party/LwIP/src/netif/ppp/magic.o
+ .debug_str     0x0000000000000000   0x15d160 ./Middlewares/Third_Party/LwIP/src/netif/ppp/magic.o
  .comment       0x0000000000000000       0x44 ./Middlewares/Third_Party/LwIP/src/netif/ppp/magic.o
  .ARM.attributes
                 0x0000000000000000       0x32 ./Middlewares/Third_Party/LwIP/src/netif/ppp/magic.o
@@ -21341,6 +28796,15 @@ Discarded input sections
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/mppe.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/mppe.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/mppe.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/mppe.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/mppe.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/mppe.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/mppe.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/mppe.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/mppe.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/mppe.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/mppe.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/mppe.o
  .text          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/netif/ppp/mppe.o
  .data          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/netif/ppp/mppe.o
  .bss           0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/netif/ppp/mppe.o
@@ -21348,9 +28812,9 @@ Discarded input sections
  .debug_abbrev  0x0000000000000000       0x28 ./Middlewares/Third_Party/LwIP/src/netif/ppp/mppe.o
  .debug_aranges
                 0x0000000000000000       0x18 ./Middlewares/Third_Party/LwIP/src/netif/ppp/mppe.o
- .debug_macro   0x0000000000000000      0x4b2 ./Middlewares/Third_Party/LwIP/src/netif/ppp/mppe.o
+ .debug_macro   0x0000000000000000      0x516 ./Middlewares/Third_Party/LwIP/src/netif/ppp/mppe.o
  .debug_macro   0x0000000000000000      0xac6 ./Middlewares/Third_Party/LwIP/src/netif/ppp/mppe.o
- .debug_macro   0x0000000000000000      0x232 ./Middlewares/Third_Party/LwIP/src/netif/ppp/mppe.o
+ .debug_macro   0x0000000000000000      0x24a ./Middlewares/Third_Party/LwIP/src/netif/ppp/mppe.o
  .debug_macro   0x0000000000000000       0x2e ./Middlewares/Third_Party/LwIP/src/netif/ppp/mppe.o
  .debug_macro   0x0000000000000000       0x3b ./Middlewares/Third_Party/LwIP/src/netif/ppp/mppe.o
  .debug_macro   0x0000000000000000       0x22 ./Middlewares/Third_Party/LwIP/src/netif/ppp/mppe.o
@@ -21398,6 +28862,7 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x129 ./Middlewares/Third_Party/LwIP/src/netif/ppp/mppe.o
  .debug_macro   0x0000000000000000      0x3f9 ./Middlewares/Third_Party/LwIP/src/netif/ppp/mppe.o
  .debug_macro   0x0000000000000000      0x275 ./Middlewares/Third_Party/LwIP/src/netif/ppp/mppe.o
+ .debug_macro   0x0000000000000000      0xe42 ./Middlewares/Third_Party/LwIP/src/netif/ppp/mppe.o
  .debug_macro   0x0000000000000000      0x3ca ./Middlewares/Third_Party/LwIP/src/netif/ppp/mppe.o
  .debug_macro   0x0000000000000000      0x45c ./Middlewares/Third_Party/LwIP/src/netif/ppp/mppe.o
  .debug_macro   0x0000000000000000       0x3c ./Middlewares/Third_Party/LwIP/src/netif/ppp/mppe.o
@@ -21408,8 +28873,16 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x1c4 ./Middlewares/Third_Party/LwIP/src/netif/ppp/mppe.o
  .debug_macro   0x0000000000000000      0x22a ./Middlewares/Third_Party/LwIP/src/netif/ppp/mppe.o
  .debug_macro   0x0000000000000000       0x35 ./Middlewares/Third_Party/LwIP/src/netif/ppp/mppe.o
+ .debug_macro   0x0000000000000000      0x830 ./Middlewares/Third_Party/LwIP/src/netif/ppp/mppe.o
+ .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/netif/ppp/mppe.o
+ .debug_macro   0x0000000000000000      0x1ce ./Middlewares/Third_Party/LwIP/src/netif/ppp/mppe.o
+ .debug_macro   0x0000000000000000      0xb1d ./Middlewares/Third_Party/LwIP/src/netif/ppp/mppe.o
+ .debug_macro   0x0000000000000000      0x29f ./Middlewares/Third_Party/LwIP/src/netif/ppp/mppe.o
+ .debug_macro   0x0000000000000000      0x693 ./Middlewares/Third_Party/LwIP/src/netif/ppp/mppe.o
+ .debug_macro   0x0000000000000000       0xa6 ./Middlewares/Third_Party/LwIP/src/netif/ppp/mppe.o
  .debug_macro   0x0000000000000000      0x5e6 ./Middlewares/Third_Party/LwIP/src/netif/ppp/mppe.o
- .debug_macro   0x0000000000000000       0xd0 ./Middlewares/Third_Party/LwIP/src/netif/ppp/mppe.o
+ .debug_macro   0x0000000000000000       0x58 ./Middlewares/Third_Party/LwIP/src/netif/ppp/mppe.o
+ .debug_macro   0x0000000000000000       0xe8 ./Middlewares/Third_Party/LwIP/src/netif/ppp/mppe.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/netif/ppp/mppe.o
  .debug_macro   0x0000000000000000       0x10 ./Middlewares/Third_Party/LwIP/src/netif/ppp/mppe.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/netif/ppp/mppe.o
@@ -21449,10 +28922,10 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x11f ./Middlewares/Third_Party/LwIP/src/netif/ppp/mppe.o
  .debug_macro   0x0000000000000000       0x82 ./Middlewares/Third_Party/LwIP/src/netif/ppp/mppe.o
  .debug_macro   0x0000000000000000       0x66 ./Middlewares/Third_Party/LwIP/src/netif/ppp/mppe.o
- .debug_macro   0x0000000000000000      0x756 ./Middlewares/Third_Party/LwIP/src/netif/ppp/mppe.o
+ .debug_macro   0x0000000000000000      0x739 ./Middlewares/Third_Party/LwIP/src/netif/ppp/mppe.o
  .debug_macro   0x0000000000000000       0x2f ./Middlewares/Third_Party/LwIP/src/netif/ppp/mppe.o
- .debug_line    0x0000000000000000      0xbbe ./Middlewares/Third_Party/LwIP/src/netif/ppp/mppe.o
- .debug_str     0x0000000000000000   0x13e8eb ./Middlewares/Third_Party/LwIP/src/netif/ppp/mppe.o
+ .debug_line    0x0000000000000000      0xc9f ./Middlewares/Third_Party/LwIP/src/netif/ppp/mppe.o
+ .debug_str     0x0000000000000000   0x15d15f ./Middlewares/Third_Party/LwIP/src/netif/ppp/mppe.o
  .comment       0x0000000000000000       0x44 ./Middlewares/Third_Party/LwIP/src/netif/ppp/mppe.o
  .ARM.attributes
                 0x0000000000000000       0x32 ./Middlewares/Third_Party/LwIP/src/netif/ppp/mppe.o
@@ -21558,6 +29031,15 @@ Discarded input sections
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/multilink.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/multilink.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/multilink.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/multilink.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/multilink.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/multilink.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/multilink.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/multilink.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/multilink.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/multilink.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/multilink.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/multilink.o
  .text          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/netif/ppp/multilink.o
  .data          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/netif/ppp/multilink.o
  .bss           0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/netif/ppp/multilink.o
@@ -21565,9 +29047,9 @@ Discarded input sections
  .debug_abbrev  0x0000000000000000       0x28 ./Middlewares/Third_Party/LwIP/src/netif/ppp/multilink.o
  .debug_aranges
                 0x0000000000000000       0x18 ./Middlewares/Third_Party/LwIP/src/netif/ppp/multilink.o
- .debug_macro   0x0000000000000000      0x4b2 ./Middlewares/Third_Party/LwIP/src/netif/ppp/multilink.o
+ .debug_macro   0x0000000000000000      0x516 ./Middlewares/Third_Party/LwIP/src/netif/ppp/multilink.o
  .debug_macro   0x0000000000000000      0xac6 ./Middlewares/Third_Party/LwIP/src/netif/ppp/multilink.o
- .debug_macro   0x0000000000000000      0x232 ./Middlewares/Third_Party/LwIP/src/netif/ppp/multilink.o
+ .debug_macro   0x0000000000000000      0x24a ./Middlewares/Third_Party/LwIP/src/netif/ppp/multilink.o
  .debug_macro   0x0000000000000000       0x2e ./Middlewares/Third_Party/LwIP/src/netif/ppp/multilink.o
  .debug_macro   0x0000000000000000       0x3b ./Middlewares/Third_Party/LwIP/src/netif/ppp/multilink.o
  .debug_macro   0x0000000000000000       0x22 ./Middlewares/Third_Party/LwIP/src/netif/ppp/multilink.o
@@ -21615,6 +29097,7 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x129 ./Middlewares/Third_Party/LwIP/src/netif/ppp/multilink.o
  .debug_macro   0x0000000000000000      0x3f9 ./Middlewares/Third_Party/LwIP/src/netif/ppp/multilink.o
  .debug_macro   0x0000000000000000      0x275 ./Middlewares/Third_Party/LwIP/src/netif/ppp/multilink.o
+ .debug_macro   0x0000000000000000      0xe42 ./Middlewares/Third_Party/LwIP/src/netif/ppp/multilink.o
  .debug_macro   0x0000000000000000      0x3ca ./Middlewares/Third_Party/LwIP/src/netif/ppp/multilink.o
  .debug_macro   0x0000000000000000      0x45c ./Middlewares/Third_Party/LwIP/src/netif/ppp/multilink.o
  .debug_macro   0x0000000000000000       0x3c ./Middlewares/Third_Party/LwIP/src/netif/ppp/multilink.o
@@ -21625,8 +29108,16 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x1c4 ./Middlewares/Third_Party/LwIP/src/netif/ppp/multilink.o
  .debug_macro   0x0000000000000000      0x22a ./Middlewares/Third_Party/LwIP/src/netif/ppp/multilink.o
  .debug_macro   0x0000000000000000       0x35 ./Middlewares/Third_Party/LwIP/src/netif/ppp/multilink.o
+ .debug_macro   0x0000000000000000      0x830 ./Middlewares/Third_Party/LwIP/src/netif/ppp/multilink.o
+ .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/netif/ppp/multilink.o
+ .debug_macro   0x0000000000000000      0x1ce ./Middlewares/Third_Party/LwIP/src/netif/ppp/multilink.o
+ .debug_macro   0x0000000000000000      0xb1d ./Middlewares/Third_Party/LwIP/src/netif/ppp/multilink.o
+ .debug_macro   0x0000000000000000      0x29f ./Middlewares/Third_Party/LwIP/src/netif/ppp/multilink.o
+ .debug_macro   0x0000000000000000      0x693 ./Middlewares/Third_Party/LwIP/src/netif/ppp/multilink.o
+ .debug_macro   0x0000000000000000       0xa6 ./Middlewares/Third_Party/LwIP/src/netif/ppp/multilink.o
  .debug_macro   0x0000000000000000      0x5e6 ./Middlewares/Third_Party/LwIP/src/netif/ppp/multilink.o
- .debug_macro   0x0000000000000000       0xd0 ./Middlewares/Third_Party/LwIP/src/netif/ppp/multilink.o
+ .debug_macro   0x0000000000000000       0x58 ./Middlewares/Third_Party/LwIP/src/netif/ppp/multilink.o
+ .debug_macro   0x0000000000000000       0xe8 ./Middlewares/Third_Party/LwIP/src/netif/ppp/multilink.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/netif/ppp/multilink.o
  .debug_macro   0x0000000000000000       0x10 ./Middlewares/Third_Party/LwIP/src/netif/ppp/multilink.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/netif/ppp/multilink.o
@@ -21666,10 +29157,10 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x11f ./Middlewares/Third_Party/LwIP/src/netif/ppp/multilink.o
  .debug_macro   0x0000000000000000       0x82 ./Middlewares/Third_Party/LwIP/src/netif/ppp/multilink.o
  .debug_macro   0x0000000000000000       0x66 ./Middlewares/Third_Party/LwIP/src/netif/ppp/multilink.o
- .debug_macro   0x0000000000000000      0x756 ./Middlewares/Third_Party/LwIP/src/netif/ppp/multilink.o
+ .debug_macro   0x0000000000000000      0x739 ./Middlewares/Third_Party/LwIP/src/netif/ppp/multilink.o
  .debug_macro   0x0000000000000000       0x2f ./Middlewares/Third_Party/LwIP/src/netif/ppp/multilink.o
- .debug_line    0x0000000000000000      0xbc3 ./Middlewares/Third_Party/LwIP/src/netif/ppp/multilink.o
- .debug_str     0x0000000000000000   0x13e8f0 ./Middlewares/Third_Party/LwIP/src/netif/ppp/multilink.o
+ .debug_line    0x0000000000000000      0xca4 ./Middlewares/Third_Party/LwIP/src/netif/ppp/multilink.o
+ .debug_str     0x0000000000000000   0x15d164 ./Middlewares/Third_Party/LwIP/src/netif/ppp/multilink.o
  .comment       0x0000000000000000       0x44 ./Middlewares/Third_Party/LwIP/src/netif/ppp/multilink.o
  .ARM.attributes
                 0x0000000000000000       0x32 ./Middlewares/Third_Party/LwIP/src/netif/ppp/multilink.o
@@ -21775,6 +29266,15 @@ Discarded input sections
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/ppp.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/ppp.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/ppp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/ppp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/ppp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/ppp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/ppp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/ppp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/ppp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/ppp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/ppp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/ppp.o
  .text          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ppp.o
  .data          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ppp.o
  .bss           0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ppp.o
@@ -21782,9 +29282,9 @@ Discarded input sections
  .debug_abbrev  0x0000000000000000       0x28 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ppp.o
  .debug_aranges
                 0x0000000000000000       0x18 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ppp.o
- .debug_macro   0x0000000000000000      0x4b2 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ppp.o
+ .debug_macro   0x0000000000000000      0x516 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ppp.o
  .debug_macro   0x0000000000000000      0xac6 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ppp.o
- .debug_macro   0x0000000000000000      0x232 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ppp.o
+ .debug_macro   0x0000000000000000      0x24a ./Middlewares/Third_Party/LwIP/src/netif/ppp/ppp.o
  .debug_macro   0x0000000000000000       0x2e ./Middlewares/Third_Party/LwIP/src/netif/ppp/ppp.o
  .debug_macro   0x0000000000000000       0x3b ./Middlewares/Third_Party/LwIP/src/netif/ppp/ppp.o
  .debug_macro   0x0000000000000000       0x22 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ppp.o
@@ -21832,6 +29332,7 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x129 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ppp.o
  .debug_macro   0x0000000000000000      0x3f9 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ppp.o
  .debug_macro   0x0000000000000000      0x275 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ppp.o
+ .debug_macro   0x0000000000000000      0xe42 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ppp.o
  .debug_macro   0x0000000000000000      0x3ca ./Middlewares/Third_Party/LwIP/src/netif/ppp/ppp.o
  .debug_macro   0x0000000000000000      0x45c ./Middlewares/Third_Party/LwIP/src/netif/ppp/ppp.o
  .debug_macro   0x0000000000000000       0x3c ./Middlewares/Third_Party/LwIP/src/netif/ppp/ppp.o
@@ -21842,8 +29343,16 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x1c4 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ppp.o
  .debug_macro   0x0000000000000000      0x22a ./Middlewares/Third_Party/LwIP/src/netif/ppp/ppp.o
  .debug_macro   0x0000000000000000       0x35 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ppp.o
+ .debug_macro   0x0000000000000000      0x830 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ppp.o
+ .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ppp.o
+ .debug_macro   0x0000000000000000      0x1ce ./Middlewares/Third_Party/LwIP/src/netif/ppp/ppp.o
+ .debug_macro   0x0000000000000000      0xb1d ./Middlewares/Third_Party/LwIP/src/netif/ppp/ppp.o
+ .debug_macro   0x0000000000000000      0x29f ./Middlewares/Third_Party/LwIP/src/netif/ppp/ppp.o
+ .debug_macro   0x0000000000000000      0x693 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ppp.o
+ .debug_macro   0x0000000000000000       0xa6 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ppp.o
  .debug_macro   0x0000000000000000      0x5e6 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ppp.o
- .debug_macro   0x0000000000000000       0xd0 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ppp.o
+ .debug_macro   0x0000000000000000       0x58 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ppp.o
+ .debug_macro   0x0000000000000000       0xe8 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ppp.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ppp.o
  .debug_macro   0x0000000000000000       0x10 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ppp.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ppp.o
@@ -21883,10 +29392,10 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x11f ./Middlewares/Third_Party/LwIP/src/netif/ppp/ppp.o
  .debug_macro   0x0000000000000000       0x82 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ppp.o
  .debug_macro   0x0000000000000000       0x66 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ppp.o
- .debug_macro   0x0000000000000000      0x756 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ppp.o
+ .debug_macro   0x0000000000000000      0x739 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ppp.o
  .debug_macro   0x0000000000000000       0x2f ./Middlewares/Third_Party/LwIP/src/netif/ppp/ppp.o
- .debug_line    0x0000000000000000      0xbbd ./Middlewares/Third_Party/LwIP/src/netif/ppp/ppp.o
- .debug_str     0x0000000000000000   0x13e8ea ./Middlewares/Third_Party/LwIP/src/netif/ppp/ppp.o
+ .debug_line    0x0000000000000000      0xc9e ./Middlewares/Third_Party/LwIP/src/netif/ppp/ppp.o
+ .debug_str     0x0000000000000000   0x15d15e ./Middlewares/Third_Party/LwIP/src/netif/ppp/ppp.o
  .comment       0x0000000000000000       0x44 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ppp.o
  .ARM.attributes
                 0x0000000000000000       0x32 ./Middlewares/Third_Party/LwIP/src/netif/ppp/ppp.o
@@ -21992,6 +29501,15 @@ Discarded input sections
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppapi.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppapi.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppapi.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppapi.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppapi.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppapi.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppapi.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppapi.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppapi.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppapi.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppapi.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppapi.o
  .text          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppapi.o
  .data          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppapi.o
  .bss           0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppapi.o
@@ -21999,9 +29517,9 @@ Discarded input sections
  .debug_abbrev  0x0000000000000000       0x28 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppapi.o
  .debug_aranges
                 0x0000000000000000       0x18 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppapi.o
- .debug_macro   0x0000000000000000      0x4b2 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppapi.o
+ .debug_macro   0x0000000000000000      0x516 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppapi.o
  .debug_macro   0x0000000000000000      0xac6 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppapi.o
- .debug_macro   0x0000000000000000      0x232 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppapi.o
+ .debug_macro   0x0000000000000000      0x24a ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppapi.o
  .debug_macro   0x0000000000000000       0x2e ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppapi.o
  .debug_macro   0x0000000000000000       0x3b ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppapi.o
  .debug_macro   0x0000000000000000       0x22 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppapi.o
@@ -22049,6 +29567,7 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x129 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppapi.o
  .debug_macro   0x0000000000000000      0x3f9 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppapi.o
  .debug_macro   0x0000000000000000      0x275 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppapi.o
+ .debug_macro   0x0000000000000000      0xe42 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppapi.o
  .debug_macro   0x0000000000000000      0x3ca ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppapi.o
  .debug_macro   0x0000000000000000      0x45c ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppapi.o
  .debug_macro   0x0000000000000000       0x3c ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppapi.o
@@ -22059,8 +29578,16 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x1c4 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppapi.o
  .debug_macro   0x0000000000000000      0x22a ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppapi.o
  .debug_macro   0x0000000000000000       0x35 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppapi.o
+ .debug_macro   0x0000000000000000      0x830 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppapi.o
+ .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppapi.o
+ .debug_macro   0x0000000000000000      0x1ce ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppapi.o
+ .debug_macro   0x0000000000000000      0xb1d ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppapi.o
+ .debug_macro   0x0000000000000000      0x29f ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppapi.o
+ .debug_macro   0x0000000000000000      0x693 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppapi.o
+ .debug_macro   0x0000000000000000       0xa6 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppapi.o
  .debug_macro   0x0000000000000000      0x5e6 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppapi.o
- .debug_macro   0x0000000000000000       0xd0 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppapi.o
+ .debug_macro   0x0000000000000000       0x58 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppapi.o
+ .debug_macro   0x0000000000000000       0xe8 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppapi.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppapi.o
  .debug_macro   0x0000000000000000       0x10 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppapi.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppapi.o
@@ -22100,10 +29627,10 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x11f ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppapi.o
  .debug_macro   0x0000000000000000       0x82 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppapi.o
  .debug_macro   0x0000000000000000       0x66 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppapi.o
- .debug_macro   0x0000000000000000      0x756 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppapi.o
+ .debug_macro   0x0000000000000000      0x739 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppapi.o
  .debug_macro   0x0000000000000000       0x2f ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppapi.o
- .debug_line    0x0000000000000000      0xbc0 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppapi.o
- .debug_str     0x0000000000000000   0x13e8ed ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppapi.o
+ .debug_line    0x0000000000000000      0xca1 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppapi.o
+ .debug_str     0x0000000000000000   0x15d161 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppapi.o
  .comment       0x0000000000000000       0x44 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppapi.o
  .ARM.attributes
                 0x0000000000000000       0x32 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppapi.o
@@ -22209,6 +29736,15 @@ Discarded input sections
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppcrypt.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppcrypt.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppcrypt.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppcrypt.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppcrypt.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppcrypt.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppcrypt.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppcrypt.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppcrypt.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppcrypt.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppcrypt.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppcrypt.o
  .text          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppcrypt.o
  .data          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppcrypt.o
  .bss           0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppcrypt.o
@@ -22216,9 +29752,9 @@ Discarded input sections
  .debug_abbrev  0x0000000000000000       0x28 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppcrypt.o
  .debug_aranges
                 0x0000000000000000       0x18 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppcrypt.o
- .debug_macro   0x0000000000000000      0x4b2 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppcrypt.o
+ .debug_macro   0x0000000000000000      0x516 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppcrypt.o
  .debug_macro   0x0000000000000000      0xac6 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppcrypt.o
- .debug_macro   0x0000000000000000      0x232 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppcrypt.o
+ .debug_macro   0x0000000000000000      0x24a ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppcrypt.o
  .debug_macro   0x0000000000000000       0x2e ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppcrypt.o
  .debug_macro   0x0000000000000000       0x3b ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppcrypt.o
  .debug_macro   0x0000000000000000       0x22 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppcrypt.o
@@ -22266,6 +29802,7 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x129 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppcrypt.o
  .debug_macro   0x0000000000000000      0x3f9 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppcrypt.o
  .debug_macro   0x0000000000000000      0x275 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppcrypt.o
+ .debug_macro   0x0000000000000000      0xe42 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppcrypt.o
  .debug_macro   0x0000000000000000      0x3ca ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppcrypt.o
  .debug_macro   0x0000000000000000      0x45c ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppcrypt.o
  .debug_macro   0x0000000000000000       0x3c ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppcrypt.o
@@ -22276,8 +29813,16 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x1c4 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppcrypt.o
  .debug_macro   0x0000000000000000      0x22a ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppcrypt.o
  .debug_macro   0x0000000000000000       0x35 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppcrypt.o
+ .debug_macro   0x0000000000000000      0x830 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppcrypt.o
+ .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppcrypt.o
+ .debug_macro   0x0000000000000000      0x1ce ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppcrypt.o
+ .debug_macro   0x0000000000000000      0xb1d ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppcrypt.o
+ .debug_macro   0x0000000000000000      0x29f ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppcrypt.o
+ .debug_macro   0x0000000000000000      0x693 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppcrypt.o
+ .debug_macro   0x0000000000000000       0xa6 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppcrypt.o
  .debug_macro   0x0000000000000000      0x5e6 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppcrypt.o
- .debug_macro   0x0000000000000000       0xd0 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppcrypt.o
+ .debug_macro   0x0000000000000000       0x58 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppcrypt.o
+ .debug_macro   0x0000000000000000       0xe8 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppcrypt.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppcrypt.o
  .debug_macro   0x0000000000000000       0x10 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppcrypt.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppcrypt.o
@@ -22317,10 +29862,10 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x11f ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppcrypt.o
  .debug_macro   0x0000000000000000       0x82 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppcrypt.o
  .debug_macro   0x0000000000000000       0x66 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppcrypt.o
- .debug_macro   0x0000000000000000      0x756 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppcrypt.o
+ .debug_macro   0x0000000000000000      0x739 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppcrypt.o
  .debug_macro   0x0000000000000000       0x2f ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppcrypt.o
- .debug_line    0x0000000000000000      0xbc2 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppcrypt.o
- .debug_str     0x0000000000000000   0x13e8ef ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppcrypt.o
+ .debug_line    0x0000000000000000      0xca3 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppcrypt.o
+ .debug_str     0x0000000000000000   0x15d163 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppcrypt.o
  .comment       0x0000000000000000       0x44 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppcrypt.o
  .ARM.attributes
                 0x0000000000000000       0x32 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppcrypt.o
@@ -22426,6 +29971,15 @@ Discarded input sections
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppoe.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppoe.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppoe.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppoe.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppoe.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppoe.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppoe.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppoe.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppoe.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppoe.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppoe.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppoe.o
  .text          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppoe.o
  .data          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppoe.o
  .bss           0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppoe.o
@@ -22433,9 +29987,9 @@ Discarded input sections
  .debug_abbrev  0x0000000000000000       0x28 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppoe.o
  .debug_aranges
                 0x0000000000000000       0x18 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppoe.o
- .debug_macro   0x0000000000000000      0x4b2 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppoe.o
+ .debug_macro   0x0000000000000000      0x516 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppoe.o
  .debug_macro   0x0000000000000000      0xac6 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppoe.o
- .debug_macro   0x0000000000000000      0x232 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppoe.o
+ .debug_macro   0x0000000000000000      0x24a ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppoe.o
  .debug_macro   0x0000000000000000       0x2e ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppoe.o
  .debug_macro   0x0000000000000000       0x3b ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppoe.o
  .debug_macro   0x0000000000000000       0x22 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppoe.o
@@ -22483,6 +30037,7 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x129 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppoe.o
  .debug_macro   0x0000000000000000      0x3f9 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppoe.o
  .debug_macro   0x0000000000000000      0x275 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppoe.o
+ .debug_macro   0x0000000000000000      0xe42 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppoe.o
  .debug_macro   0x0000000000000000      0x3ca ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppoe.o
  .debug_macro   0x0000000000000000      0x45c ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppoe.o
  .debug_macro   0x0000000000000000       0x3c ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppoe.o
@@ -22493,8 +30048,16 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x1c4 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppoe.o
  .debug_macro   0x0000000000000000      0x22a ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppoe.o
  .debug_macro   0x0000000000000000       0x35 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppoe.o
+ .debug_macro   0x0000000000000000      0x830 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppoe.o
+ .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppoe.o
+ .debug_macro   0x0000000000000000      0x1ce ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppoe.o
+ .debug_macro   0x0000000000000000      0xb1d ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppoe.o
+ .debug_macro   0x0000000000000000      0x29f ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppoe.o
+ .debug_macro   0x0000000000000000      0x693 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppoe.o
+ .debug_macro   0x0000000000000000       0xa6 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppoe.o
  .debug_macro   0x0000000000000000      0x5e6 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppoe.o
- .debug_macro   0x0000000000000000       0xd0 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppoe.o
+ .debug_macro   0x0000000000000000       0x58 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppoe.o
+ .debug_macro   0x0000000000000000       0xe8 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppoe.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppoe.o
  .debug_macro   0x0000000000000000       0x10 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppoe.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppoe.o
@@ -22534,10 +30097,10 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x11f ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppoe.o
  .debug_macro   0x0000000000000000       0x82 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppoe.o
  .debug_macro   0x0000000000000000       0x66 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppoe.o
- .debug_macro   0x0000000000000000      0x756 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppoe.o
+ .debug_macro   0x0000000000000000      0x739 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppoe.o
  .debug_macro   0x0000000000000000       0x2f ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppoe.o
- .debug_line    0x0000000000000000      0xbbf ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppoe.o
- .debug_str     0x0000000000000000   0x13e8ec ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppoe.o
+ .debug_line    0x0000000000000000      0xca0 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppoe.o
+ .debug_str     0x0000000000000000   0x15d160 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppoe.o
  .comment       0x0000000000000000       0x44 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppoe.o
  .ARM.attributes
                 0x0000000000000000       0x32 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppoe.o
@@ -22643,6 +30206,15 @@ Discarded input sections
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppol2tp.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppol2tp.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppol2tp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppol2tp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppol2tp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppol2tp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppol2tp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppol2tp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppol2tp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppol2tp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppol2tp.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppol2tp.o
  .text          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppol2tp.o
  .data          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppol2tp.o
  .bss           0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppol2tp.o
@@ -22650,9 +30222,9 @@ Discarded input sections
  .debug_abbrev  0x0000000000000000       0x28 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppol2tp.o
  .debug_aranges
                 0x0000000000000000       0x18 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppol2tp.o
- .debug_macro   0x0000000000000000      0x4b2 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppol2tp.o
+ .debug_macro   0x0000000000000000      0x516 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppol2tp.o
  .debug_macro   0x0000000000000000      0xac6 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppol2tp.o
- .debug_macro   0x0000000000000000      0x232 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppol2tp.o
+ .debug_macro   0x0000000000000000      0x24a ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppol2tp.o
  .debug_macro   0x0000000000000000       0x2e ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppol2tp.o
  .debug_macro   0x0000000000000000       0x3b ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppol2tp.o
  .debug_macro   0x0000000000000000       0x22 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppol2tp.o
@@ -22700,6 +30272,7 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x129 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppol2tp.o
  .debug_macro   0x0000000000000000      0x3f9 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppol2tp.o
  .debug_macro   0x0000000000000000      0x275 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppol2tp.o
+ .debug_macro   0x0000000000000000      0xe42 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppol2tp.o
  .debug_macro   0x0000000000000000      0x3ca ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppol2tp.o
  .debug_macro   0x0000000000000000      0x45c ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppol2tp.o
  .debug_macro   0x0000000000000000       0x3c ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppol2tp.o
@@ -22710,8 +30283,16 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x1c4 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppol2tp.o
  .debug_macro   0x0000000000000000      0x22a ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppol2tp.o
  .debug_macro   0x0000000000000000       0x35 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppol2tp.o
+ .debug_macro   0x0000000000000000      0x830 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppol2tp.o
+ .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppol2tp.o
+ .debug_macro   0x0000000000000000      0x1ce ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppol2tp.o
+ .debug_macro   0x0000000000000000      0xb1d ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppol2tp.o
+ .debug_macro   0x0000000000000000      0x29f ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppol2tp.o
+ .debug_macro   0x0000000000000000      0x693 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppol2tp.o
+ .debug_macro   0x0000000000000000       0xa6 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppol2tp.o
  .debug_macro   0x0000000000000000      0x5e6 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppol2tp.o
- .debug_macro   0x0000000000000000       0xd0 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppol2tp.o
+ .debug_macro   0x0000000000000000       0x58 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppol2tp.o
+ .debug_macro   0x0000000000000000       0xe8 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppol2tp.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppol2tp.o
  .debug_macro   0x0000000000000000       0x10 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppol2tp.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppol2tp.o
@@ -22751,10 +30332,10 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x11f ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppol2tp.o
  .debug_macro   0x0000000000000000       0x82 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppol2tp.o
  .debug_macro   0x0000000000000000       0x66 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppol2tp.o
- .debug_macro   0x0000000000000000      0x756 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppol2tp.o
+ .debug_macro   0x0000000000000000      0x739 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppol2tp.o
  .debug_macro   0x0000000000000000       0x2f ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppol2tp.o
- .debug_line    0x0000000000000000      0xbc2 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppol2tp.o
- .debug_str     0x0000000000000000   0x13e8ef ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppol2tp.o
+ .debug_line    0x0000000000000000      0xca3 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppol2tp.o
+ .debug_str     0x0000000000000000   0x15d163 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppol2tp.o
  .comment       0x0000000000000000       0x44 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppol2tp.o
  .ARM.attributes
                 0x0000000000000000       0x32 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppol2tp.o
@@ -22860,6 +30441,15 @@ Discarded input sections
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppos.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppos.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppos.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppos.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppos.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppos.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppos.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppos.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppos.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppos.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppos.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppos.o
  .text          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppos.o
  .data          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppos.o
  .bss           0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppos.o
@@ -22867,9 +30457,9 @@ Discarded input sections
  .debug_abbrev  0x0000000000000000       0x28 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppos.o
  .debug_aranges
                 0x0000000000000000       0x18 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppos.o
- .debug_macro   0x0000000000000000      0x4b2 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppos.o
+ .debug_macro   0x0000000000000000      0x516 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppos.o
  .debug_macro   0x0000000000000000      0xac6 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppos.o
- .debug_macro   0x0000000000000000      0x232 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppos.o
+ .debug_macro   0x0000000000000000      0x24a ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppos.o
  .debug_macro   0x0000000000000000       0x2e ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppos.o
  .debug_macro   0x0000000000000000       0x3b ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppos.o
  .debug_macro   0x0000000000000000       0x22 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppos.o
@@ -22917,6 +30507,7 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x129 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppos.o
  .debug_macro   0x0000000000000000      0x3f9 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppos.o
  .debug_macro   0x0000000000000000      0x275 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppos.o
+ .debug_macro   0x0000000000000000      0xe42 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppos.o
  .debug_macro   0x0000000000000000      0x3ca ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppos.o
  .debug_macro   0x0000000000000000      0x45c ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppos.o
  .debug_macro   0x0000000000000000       0x3c ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppos.o
@@ -22927,8 +30518,16 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x1c4 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppos.o
  .debug_macro   0x0000000000000000      0x22a ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppos.o
  .debug_macro   0x0000000000000000       0x35 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppos.o
+ .debug_macro   0x0000000000000000      0x830 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppos.o
+ .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppos.o
+ .debug_macro   0x0000000000000000      0x1ce ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppos.o
+ .debug_macro   0x0000000000000000      0xb1d ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppos.o
+ .debug_macro   0x0000000000000000      0x29f ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppos.o
+ .debug_macro   0x0000000000000000      0x693 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppos.o
+ .debug_macro   0x0000000000000000       0xa6 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppos.o
  .debug_macro   0x0000000000000000      0x5e6 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppos.o
- .debug_macro   0x0000000000000000       0xd0 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppos.o
+ .debug_macro   0x0000000000000000       0x58 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppos.o
+ .debug_macro   0x0000000000000000       0xe8 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppos.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppos.o
  .debug_macro   0x0000000000000000       0x10 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppos.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppos.o
@@ -22968,10 +30567,10 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x11f ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppos.o
  .debug_macro   0x0000000000000000       0x82 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppos.o
  .debug_macro   0x0000000000000000       0x66 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppos.o
- .debug_macro   0x0000000000000000      0x756 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppos.o
+ .debug_macro   0x0000000000000000      0x739 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppos.o
  .debug_macro   0x0000000000000000       0x2f ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppos.o
- .debug_line    0x0000000000000000      0xbbf ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppos.o
- .debug_str     0x0000000000000000   0x13e8ec ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppos.o
+ .debug_line    0x0000000000000000      0xca0 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppos.o
+ .debug_str     0x0000000000000000   0x15d160 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppos.o
  .comment       0x0000000000000000       0x44 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppos.o
  .ARM.attributes
                 0x0000000000000000       0x32 ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppos.o
@@ -23077,6 +30676,15 @@ Discarded input sections
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/upap.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/upap.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/upap.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/upap.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/upap.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/upap.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/upap.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/upap.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/upap.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/upap.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/upap.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/upap.o
  .text          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/netif/ppp/upap.o
  .data          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/netif/ppp/upap.o
  .bss           0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/netif/ppp/upap.o
@@ -23084,9 +30692,9 @@ Discarded input sections
  .debug_abbrev  0x0000000000000000       0x28 ./Middlewares/Third_Party/LwIP/src/netif/ppp/upap.o
  .debug_aranges
                 0x0000000000000000       0x18 ./Middlewares/Third_Party/LwIP/src/netif/ppp/upap.o
- .debug_macro   0x0000000000000000      0x4b2 ./Middlewares/Third_Party/LwIP/src/netif/ppp/upap.o
+ .debug_macro   0x0000000000000000      0x516 ./Middlewares/Third_Party/LwIP/src/netif/ppp/upap.o
  .debug_macro   0x0000000000000000      0xac6 ./Middlewares/Third_Party/LwIP/src/netif/ppp/upap.o
- .debug_macro   0x0000000000000000      0x232 ./Middlewares/Third_Party/LwIP/src/netif/ppp/upap.o
+ .debug_macro   0x0000000000000000      0x24a ./Middlewares/Third_Party/LwIP/src/netif/ppp/upap.o
  .debug_macro   0x0000000000000000       0x2e ./Middlewares/Third_Party/LwIP/src/netif/ppp/upap.o
  .debug_macro   0x0000000000000000       0x3b ./Middlewares/Third_Party/LwIP/src/netif/ppp/upap.o
  .debug_macro   0x0000000000000000       0x22 ./Middlewares/Third_Party/LwIP/src/netif/ppp/upap.o
@@ -23134,6 +30742,7 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x129 ./Middlewares/Third_Party/LwIP/src/netif/ppp/upap.o
  .debug_macro   0x0000000000000000      0x3f9 ./Middlewares/Third_Party/LwIP/src/netif/ppp/upap.o
  .debug_macro   0x0000000000000000      0x275 ./Middlewares/Third_Party/LwIP/src/netif/ppp/upap.o
+ .debug_macro   0x0000000000000000      0xe42 ./Middlewares/Third_Party/LwIP/src/netif/ppp/upap.o
  .debug_macro   0x0000000000000000      0x3ca ./Middlewares/Third_Party/LwIP/src/netif/ppp/upap.o
  .debug_macro   0x0000000000000000      0x45c ./Middlewares/Third_Party/LwIP/src/netif/ppp/upap.o
  .debug_macro   0x0000000000000000       0x3c ./Middlewares/Third_Party/LwIP/src/netif/ppp/upap.o
@@ -23144,8 +30753,16 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x1c4 ./Middlewares/Third_Party/LwIP/src/netif/ppp/upap.o
  .debug_macro   0x0000000000000000      0x22a ./Middlewares/Third_Party/LwIP/src/netif/ppp/upap.o
  .debug_macro   0x0000000000000000       0x35 ./Middlewares/Third_Party/LwIP/src/netif/ppp/upap.o
+ .debug_macro   0x0000000000000000      0x830 ./Middlewares/Third_Party/LwIP/src/netif/ppp/upap.o
+ .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/netif/ppp/upap.o
+ .debug_macro   0x0000000000000000      0x1ce ./Middlewares/Third_Party/LwIP/src/netif/ppp/upap.o
+ .debug_macro   0x0000000000000000      0xb1d ./Middlewares/Third_Party/LwIP/src/netif/ppp/upap.o
+ .debug_macro   0x0000000000000000      0x29f ./Middlewares/Third_Party/LwIP/src/netif/ppp/upap.o
+ .debug_macro   0x0000000000000000      0x693 ./Middlewares/Third_Party/LwIP/src/netif/ppp/upap.o
+ .debug_macro   0x0000000000000000       0xa6 ./Middlewares/Third_Party/LwIP/src/netif/ppp/upap.o
  .debug_macro   0x0000000000000000      0x5e6 ./Middlewares/Third_Party/LwIP/src/netif/ppp/upap.o
- .debug_macro   0x0000000000000000       0xd0 ./Middlewares/Third_Party/LwIP/src/netif/ppp/upap.o
+ .debug_macro   0x0000000000000000       0x58 ./Middlewares/Third_Party/LwIP/src/netif/ppp/upap.o
+ .debug_macro   0x0000000000000000       0xe8 ./Middlewares/Third_Party/LwIP/src/netif/ppp/upap.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/netif/ppp/upap.o
  .debug_macro   0x0000000000000000       0x10 ./Middlewares/Third_Party/LwIP/src/netif/ppp/upap.o
  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/netif/ppp/upap.o
@@ -23185,10 +30802,10 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x11f ./Middlewares/Third_Party/LwIP/src/netif/ppp/upap.o
  .debug_macro   0x0000000000000000       0x82 ./Middlewares/Third_Party/LwIP/src/netif/ppp/upap.o
  .debug_macro   0x0000000000000000       0x66 ./Middlewares/Third_Party/LwIP/src/netif/ppp/upap.o
- .debug_macro   0x0000000000000000      0x756 ./Middlewares/Third_Party/LwIP/src/netif/ppp/upap.o
+ .debug_macro   0x0000000000000000      0x739 ./Middlewares/Third_Party/LwIP/src/netif/ppp/upap.o
  .debug_macro   0x0000000000000000       0x2f ./Middlewares/Third_Party/LwIP/src/netif/ppp/upap.o
- .debug_line    0x0000000000000000      0xbbe ./Middlewares/Third_Party/LwIP/src/netif/ppp/upap.o
- .debug_str     0x0000000000000000   0x13e8eb ./Middlewares/Third_Party/LwIP/src/netif/ppp/upap.o
+ .debug_line    0x0000000000000000      0xc9f ./Middlewares/Third_Party/LwIP/src/netif/ppp/upap.o
+ .debug_str     0x0000000000000000   0x15d15f ./Middlewares/Third_Party/LwIP/src/netif/ppp/upap.o
  .comment       0x0000000000000000       0x44 ./Middlewares/Third_Party/LwIP/src/netif/ppp/upap.o
  .ARM.attributes
                 0x0000000000000000       0x32 ./Middlewares/Third_Party/LwIP/src/netif/ppp/upap.o
@@ -23294,6 +30911,15 @@ Discarded input sections
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/utils.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/utils.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/utils.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/utils.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/utils.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/utils.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/utils.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/utils.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/utils.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/utils.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/utils.o
+ .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/utils.o
  .text          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/netif/ppp/utils.o
  .data          0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/netif/ppp/utils.o
  .bss           0x0000000000000000        0x0 ./Middlewares/Third_Party/LwIP/src/netif/ppp/utils.o
@@ -23301,9 +30927,9 @@ Discarded input sections
  .debug_abbrev  0x0000000000000000       0x28 ./Middlewares/Third_Party/LwIP/src/netif/ppp/utils.o
  .debug_aranges
                 0x0000000000000000       0x18 ./Middlewares/Third_Party/LwIP/src/netif/ppp/utils.o
- .debug_macro   0x0000000000000000      0x4b2 ./Middlewares/Third_Party/LwIP/src/netif/ppp/utils.o
+ .debug_macro   0x0000000000000000      0x516 ./Middlewares/Third_Party/LwIP/src/netif/ppp/utils.o
  .debug_macro   0x0000000000000000      0xac6 ./Middlewares/Third_Party/LwIP/src/netif/ppp/utils.o
- .debug_macro   0x0000000000000000      0x232 ./Middlewares/Third_Party/LwIP/src/netif/ppp/utils.o
+ .debug_macro   0x0000000000000000      0x24a ./Middlewares/Third_Party/LwIP/src/netif/ppp/utils.o
  .debug_macro   0x0000000000000000       0x2e ./Middlewares/Third_Party/LwIP/src/netif/ppp/utils.o
  .debug_macro   0x0000000000000000       0x3b ./Middlewares/Third_Party/LwIP/src/netif/ppp/utils.o
  .debug_macro   0x0000000000000000       0x22 ./Middlewares/Third_Party/LwIP/src/netif/ppp/utils.o
@@ -23351,6 +30977,7 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x129 ./Middlewares/Third_Party/LwIP/src/netif/ppp/utils.o
  .debug_macro   0x0000000000000000      0x3f9 ./Middlewares/Third_Party/LwIP/src/netif/ppp/utils.o
  .debug_macro   0x0000000000000000      0x275 ./Middlewares/Third_Party/LwIP/src/netif/ppp/utils.o
+ .debug_macro   0x0000000000000000      0xe42 ./Middlewares/Third_Party/LwIP/src/netif/ppp/utils.o
  .debug_macro   0x0000000000000000      0x3ca ./Middlewares/Third_Party/LwIP/src/netif/ppp/utils.o
  .debug_macro   0x0000000000000000      0x45c ./Middlewares/Third_Party/LwIP/src/netif/ppp/utils.o
  .debug_macro   0x0000000000000000       0x3c ./Middlewares/Third_Party/LwIP/src/netif/ppp/utils.o
@@ -23361,8 +30988,16 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x1c4 ./Middlewares/Third_Party/LwIP/src/netif/ppp/utils.o
  .debug_macro   0x0000000000000000      0x22a ./Middlewares/Third_Party/LwIP/src/netif/ppp/utils.o
  .debug_macro   0x0000000000000000       0x35 ./Middlewares/Third_Party/LwIP/src/netif/ppp/utils.o
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+ .debug_macro   0x0000000000000000      0x1ce ./Middlewares/Third_Party/LwIP/src/netif/ppp/utils.o
+ .debug_macro   0x0000000000000000      0xb1d ./Middlewares/Third_Party/LwIP/src/netif/ppp/utils.o
+ .debug_macro   0x0000000000000000      0x29f ./Middlewares/Third_Party/LwIP/src/netif/ppp/utils.o
+ .debug_macro   0x0000000000000000      0x693 ./Middlewares/Third_Party/LwIP/src/netif/ppp/utils.o
+ .debug_macro   0x0000000000000000       0xa6 ./Middlewares/Third_Party/LwIP/src/netif/ppp/utils.o
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- .debug_macro   0x0000000000000000       0xd0 ./Middlewares/Third_Party/LwIP/src/netif/ppp/utils.o
+ .debug_macro   0x0000000000000000       0x58 ./Middlewares/Third_Party/LwIP/src/netif/ppp/utils.o
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  .debug_macro   0x0000000000000000       0x16 ./Middlewares/Third_Party/LwIP/src/netif/ppp/utils.o
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  .debug_macro   0x0000000000000000      0x11f ./Middlewares/Third_Party/LwIP/src/netif/ppp/utils.o
  .debug_macro   0x0000000000000000       0x82 ./Middlewares/Third_Party/LwIP/src/netif/ppp/utils.o
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- .debug_macro   0x0000000000000000      0x756 ./Middlewares/Third_Party/LwIP/src/netif/ppp/utils.o
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  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/vj.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/vj.o
  .group         0x0000000000000000        0xc ./Middlewares/Third_Party/LwIP/src/netif/ppp/vj.o
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  .debug_aranges
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- .debug_macro   0x0000000000000000      0x4b2 ./Middlewares/Third_Party/LwIP/src/netif/ppp/vj.o
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  .debug_macro   0x0000000000000000       0x2e ./Middlewares/Third_Party/LwIP/src/netif/ppp/vj.o
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  .debug_macro   0x0000000000000000      0x3f9 ./Middlewares/Third_Party/LwIP/src/netif/ppp/vj.o
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  .debug_macro   0x0000000000000000       0x35 ./Middlewares/Third_Party/LwIP/src/netif/ppp/vj.o
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+ .bss           0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+dp/hard\libgcc.a(_dvmd_tls.o)
  .text          0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+dp/hard/crtend.o
  .data          0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+dp/hard/crtend.o
  .bss           0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+dp/hard/crtend.o
@@ -23922,8 +31851,10 @@ Linker script and memory map
 LOAD C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+dp/hard/crti.o
 LOAD C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+dp/hard/crtbegin.o
 LOAD C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/crt0.o
+LOAD ./Core/Src/freertos.o
 LOAD ./Core/Src/main.o
 LOAD ./Core/Src/stm32h7xx_hal_msp.o
+LOAD ./Core/Src/stm32h7xx_hal_timebase_tim.o
 LOAD ./Core/Src/stm32h7xx_it.o
 LOAD ./Core/Src/syscalls.o
 LOAD ./Core/Src/sysmem.o
@@ -23937,6 +31868,7 @@ LOAD ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.o
 LOAD ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o
 LOAD ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.o
 LOAD ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.o
+LOAD ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
 LOAD ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.o
 LOAD ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.o
 LOAD ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.o
@@ -23948,12 +31880,36 @@ LOAD ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.o
 LOAD ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.o
 LOAD ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.o
 LOAD ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.o
+LOAD ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.o
+LOAD ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd_ex.o
 LOAD ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.o
 LOAD ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.o
-LOAD ./LWFTP/lwftp.o
-LOAD ./LWFTP/lwftp_mod.o
+LOAD ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.o
+LOAD ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.o
+LOAD ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_delayblock.o
+LOAD ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.o
+LOAD ./FATFS/App/fatfs.o
+LOAD ./FATFS/Target/bsp_driver_sd.o
+LOAD ./FATFS/Target/fatfs_platform.o
+LOAD ./FATFS/Target/sd_diskio.o
+LOAD ./LWFTPC/lwftpc.o
 LOAD ./LWIP/App/lwip.o
 LOAD ./LWIP/Target/ethernetif.o
+LOAD ./Middlewares/Third_Party/FatFs/src/diskio.o
+LOAD ./Middlewares/Third_Party/FatFs/src/ff.o
+LOAD ./Middlewares/Third_Party/FatFs/src/ff_gen_drv.o
+LOAD ./Middlewares/Third_Party/FatFs/src/option/ccsbcs.o
+LOAD ./Middlewares/Third_Party/FatFs/src/option/syscall.o
+LOAD ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o
+LOAD ./Middlewares/Third_Party/FreeRTOS/Source/croutine.o
+LOAD ./Middlewares/Third_Party/FreeRTOS/Source/event_groups.o
+LOAD ./Middlewares/Third_Party/FreeRTOS/Source/list.o
+LOAD ./Middlewares/Third_Party/FreeRTOS/Source/queue.o
+LOAD ./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o
+LOAD ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o
+LOAD ./Middlewares/Third_Party/FreeRTOS/Source/timers.o
+LOAD ./Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.o
+LOAD ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o
 LOAD ./Middlewares/Third_Party/LwIP/src/api/api_lib.o
 LOAD ./Middlewares/Third_Party/LwIP/src/api/api_msg.o
 LOAD ./Middlewares/Third_Party/LwIP/src/api/err.o
@@ -24034,6 +31990,7 @@ LOAD ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppos.o
 LOAD ./Middlewares/Third_Party/LwIP/src/netif/ppp/upap.o
 LOAD ./Middlewares/Third_Party/LwIP/src/netif/ppp/utils.o
 LOAD ./Middlewares/Third_Party/LwIP/src/netif/ppp/vj.o
+LOAD ./Middlewares/Third_Party/LwIP/system/OS/sys_arch.o
 START GROUP
 LOAD C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a
 LOAD C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libm.a
@@ -24055,8 +32012,8 @@ END GROUP
 LOAD C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+dp/hard/crtend.o
 LOAD C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+dp/hard/crtn.o
                 0x0000000024050000                _estack = (ORIGIN (RAM_D1) + LENGTH (RAM_D1))
-                0x0000000000000200                _Min_Heap_Size = 0x200
-                0x0000000000000400                _Min_Stack_Size = 0x400
+                0x0000000000002000                _Min_Heap_Size = 0x2000
+                0x0000000000004000                _Min_Stack_Size = 0x4000
 
 .isr_vector     0x0000000008000000      0x2cc
                 0x0000000008000000                . = ALIGN (0x4)
@@ -24065,1538 +32022,2791 @@ LOAD C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.ext
                 0x0000000008000000                g_pfnVectors
                 0x00000000080002cc                . = ALIGN (0x4)
 
-.text           0x00000000080002d0    0x111b4
+.text           0x00000000080002d0    0x229f4
                 0x00000000080002d0                . = ALIGN (0x4)
  *(.text)
  .text          0x00000000080002d0       0x40 C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+dp/hard/crtbegin.o
- .text          0x0000000008000310       0x10 C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-strlen.o)
-                0x0000000008000310                strlen
- .text          0x0000000008000320       0xa0 C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-memchr.o)
-                0x0000000008000320                memchr
+ .text          0x0000000008000310       0x14 C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-strcmp.o)
+                0x0000000008000310                strcmp
+ .text          0x0000000008000324       0x10 C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-strlen.o)
+                0x0000000008000324                strlen
+ *fill*         0x0000000008000334        0xc 
+ .text          0x0000000008000340       0xa0 C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-memchr.o)
+                0x0000000008000340                memchr
+ .text          0x00000000080003e0       0x30 C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+dp/hard\libgcc.a(_aeabi_uldivmod.o)
+                0x00000000080003e0                __aeabi_uldivmod
+ .text          0x0000000008000410      0x2c8 C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+dp/hard\libgcc.a(_udivmoddi4.o)
+                0x0000000008000410                __udivmoddi4
+ .text          0x00000000080006d8        0x4 C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+dp/hard\libgcc.a(_dvmd_tls.o)
+                0x00000000080006d8                __aeabi_idiv0
+                0x00000000080006d8                __aeabi_ldiv0
  *(.text*)
+ .text.vApplicationStackOverflowHook
+                0x00000000080006dc       0x16 ./Core/Src/freertos.o
+                0x00000000080006dc                vApplicationStackOverflowHook
+ *fill*         0x00000000080006f2        0x2 
+ .text.vApplicationGetIdleTaskMemory
+                0x00000000080006f4       0x34 ./Core/Src/freertos.o
+                0x00000000080006f4                vApplicationGetIdleTaskMemory
+ .text.vApplicationGetTimerTaskMemory
+                0x0000000008000728       0x34 ./Core/Src/freertos.o
+                0x0000000008000728                vApplicationGetTimerTaskMemory
  .text.ITM_SendChar
-                0x00000000080003c0       0x4e ./Core/Src/main.o
- .text._write   0x000000000800040e       0x38 ./Core/Src/main.o
-                0x000000000800040e                _write
- *fill*         0x0000000008000446        0x2 
- .text.LOG_TRACE
-                0x0000000008000448       0x1c ./Core/Src/main.o
-                0x0000000008000448                LOG_TRACE
- .text.data_source
-                0x0000000008000464       0x78 ./Core/Src/main.o
- .text.ftp_connect_callback
-                0x00000000080004dc       0x3c ./Core/Src/main.o
- .text.ftp_test
-                0x0000000008000518       0x74 ./Core/Src/main.o
- .text.main     0x000000000800058c       0xf0 ./Core/Src/main.o
-                0x000000000800058c                main
+                0x000000000800075c       0x4e ./Core/Src/main.o
+ .text._write   0x00000000080007aa       0x38 ./Core/Src/main.o
+                0x00000000080007aa                _write
+ *fill*         0x00000000080007e2        0x2 
+ .text.main     0x00000000080007e4      0x174 ./Core/Src/main.o
+                0x00000000080007e4                main
  .text.SystemClock_Config
-                0x000000000800067c       0xdc ./Core/Src/main.o
-                0x000000000800067c                SystemClock_Config
+                0x0000000008000958       0xdc ./Core/Src/main.o
+                0x0000000008000958                SystemClock_Config
+ .text.MX_FDCAN1_Init
+                0x0000000008000a34       0xcc ./Core/Src/main.o
+ .text.MX_FDCAN2_Init
+                0x0000000008000b00       0xcc ./Core/Src/main.o
+ .text.MX_FDCAN3_Init
+                0x0000000008000bcc       0xcc ./Core/Src/main.o
+ .text.MX_SDMMC1_SD_Init
+                0x0000000008000c98       0x40 ./Core/Src/main.o
+ .text.MX_TIM3_Init
+                0x0000000008000cd8       0x9c ./Core/Src/main.o
+ .text.MX_UART4_Init
+                0x0000000008000d74       0x98 ./Core/Src/main.o
+ .text.MX_UART7_Init
+                0x0000000008000e0c       0x98 ./Core/Src/main.o
+ .text.MX_UART8_Init
+                0x0000000008000ea4       0x98 ./Core/Src/main.o
+ .text.MX_DMA_Init
+                0x0000000008000f3c       0x40 ./Core/Src/main.o
+ .text.MX_MDMA_Init
+                0x0000000008000f7c       0xc8 ./Core/Src/main.o
  .text.MX_GPIO_Init
-                0x0000000008000758       0x90 ./Core/Src/main.o
+                0x0000000008001044      0x16c ./Core/Src/main.o
+ .text.lwftp_init
+                0x00000000080011b0      0x1fc ./Core/Src/main.o
+                0x00000000080011b0                lwftp_init
+ .text.StartDefaultTask
+                0x00000000080013ac       0x58 ./Core/Src/main.o
+                0x00000000080013ac                StartDefaultTask
+ .text.StartDebugTask
+                0x0000000008001404       0x10 ./Core/Src/main.o
+                0x0000000008001404                StartDebugTask
  .text.MPU_Config
-                0x00000000080007e8       0x9a ./Core/Src/main.o
+                0x0000000008001414       0xbc ./Core/Src/main.o
+ .text.HAL_TIM_PeriodElapsedCallback
+                0x00000000080014d0       0x24 ./Core/Src/main.o
+                0x00000000080014d0                HAL_TIM_PeriodElapsedCallback
  .text.Error_Handler
-                0x0000000008000882        0xa ./Core/Src/main.o
-                0x0000000008000882                Error_Handler
+                0x00000000080014f4        0xa ./Core/Src/main.o
+                0x00000000080014f4                Error_Handler
+ *fill*         0x00000000080014fe        0x2 
  .text.HAL_MspInit
-                0x000000000800088c       0x34 ./Core/Src/stm32h7xx_hal_msp.o
-                0x000000000800088c                HAL_MspInit
- .text.NMI_Handler
-                0x00000000080008c0        0x6 ./Core/Src/stm32h7xx_it.o
-                0x00000000080008c0                NMI_Handler
- .text.HardFault_Handler
-                0x00000000080008c6        0x6 ./Core/Src/stm32h7xx_it.o
-                0x00000000080008c6                HardFault_Handler
- .text.MemManage_Handler
-                0x00000000080008cc        0x6 ./Core/Src/stm32h7xx_it.o
-                0x00000000080008cc                MemManage_Handler
- .text.BusFault_Handler
-                0x00000000080008d2        0x6 ./Core/Src/stm32h7xx_it.o
-                0x00000000080008d2                BusFault_Handler
- .text.UsageFault_Handler
-                0x00000000080008d8        0x6 ./Core/Src/stm32h7xx_it.o
-                0x00000000080008d8                UsageFault_Handler
- .text.SVC_Handler
-                0x00000000080008de        0xe ./Core/Src/stm32h7xx_it.o
-                0x00000000080008de                SVC_Handler
- .text.DebugMon_Handler
-                0x00000000080008ec        0xe ./Core/Src/stm32h7xx_it.o
-                0x00000000080008ec                DebugMon_Handler
- .text.PendSV_Handler
-                0x00000000080008fa        0xe ./Core/Src/stm32h7xx_it.o
-                0x00000000080008fa                PendSV_Handler
- .text.SysTick_Handler
-                0x0000000008000908        0xc ./Core/Src/stm32h7xx_it.o
-                0x0000000008000908                SysTick_Handler
- .text.ETH_IRQHandler
-                0x0000000008000914       0x14 ./Core/Src/stm32h7xx_it.o
-                0x0000000008000914                ETH_IRQHandler
- .text._getpid  0x0000000008000928       0x10 ./Core/Src/syscalls.o
-                0x0000000008000928                _getpid
- .text._kill    0x0000000008000938       0x24 ./Core/Src/syscalls.o
-                0x0000000008000938                _kill
- .text._exit    0x000000000800095c       0x14 ./Core/Src/syscalls.o
-                0x000000000800095c                _exit
- .text._read    0x0000000008000970       0x3a ./Core/Src/syscalls.o
-                0x0000000008000970                _read
- .text._close   0x00000000080009aa       0x18 ./Core/Src/syscalls.o
-                0x00000000080009aa                _close
- .text._fstat   0x00000000080009c2       0x20 ./Core/Src/syscalls.o
-                0x00000000080009c2                _fstat
- .text._isatty  0x00000000080009e2       0x16 ./Core/Src/syscalls.o
-                0x00000000080009e2                _isatty
- .text._lseek   0x00000000080009f8       0x1a ./Core/Src/syscalls.o
-                0x00000000080009f8                _lseek
- *fill*         0x0000000008000a12        0x2 
- .text._sbrk    0x0000000008000a14       0x70 ./Core/Src/sysmem.o
-                0x0000000008000a14                _sbrk
- .text.SystemInit
-                0x0000000008000a84      0x110 ./Core/Src/system_stm32h7xx.o
-                0x0000000008000a84                SystemInit
- .text.Reset_Handler
-                0x0000000008000b94       0x50 ./Core/Startup/startup_stm32h723vghx.o
-                0x0000000008000b94                Reset_Handler
- .text.Default_Handler
-                0x0000000008000be4        0x2 ./Core/Startup/startup_stm32h723vghx.o
-                0x0000000008000be4                RTC_Alarm_IRQHandler
-                0x0000000008000be4                EXTI2_IRQHandler
-                0x0000000008000be4                TIM8_CC_IRQHandler
-                0x0000000008000be4                UART8_IRQHandler
-                0x0000000008000be4                SPI4_IRQHandler
-                0x0000000008000be4                FDCAN3_IT0_IRQHandler
-                0x0000000008000be4                TIM1_CC_IRQHandler
-                0x0000000008000be4                BDMA_Channel6_IRQHandler
-                0x0000000008000be4                DMA2_Stream5_IRQHandler
-                0x0000000008000be4                DMA1_Stream5_IRQHandler
-                0x0000000008000be4                CORDIC_IRQHandler
-                0x0000000008000be4                BDMA_Channel1_IRQHandler
-                0x0000000008000be4                TAMP_STAMP_IRQHandler
-                0x0000000008000be4                EXTI3_IRQHandler
-                0x0000000008000be4                LPTIM4_IRQHandler
-                0x0000000008000be4                TIM8_TRG_COM_TIM14_IRQHandler
-                0x0000000008000be4                LPTIM2_IRQHandler
-                0x0000000008000be4                DFSDM1_FLT1_IRQHandler
-                0x0000000008000be4                DMAMUX2_OVR_IRQHandler
-                0x0000000008000be4                TIM8_UP_TIM13_IRQHandler
-                0x0000000008000be4                I2C3_ER_IRQHandler
-                0x0000000008000be4                DFSDM1_FLT2_IRQHandler
-                0x0000000008000be4                I2C5_EV_IRQHandler
-                0x0000000008000be4                USART10_IRQHandler
-                0x0000000008000be4                MDMA_IRQHandler
-                0x0000000008000be4                LPTIM3_IRQHandler
-                0x0000000008000be4                HSEM1_IRQHandler
-                0x0000000008000be4                EXTI0_IRQHandler
-                0x0000000008000be4                I2C2_EV_IRQHandler
-                0x0000000008000be4                DMA1_Stream2_IRQHandler
-                0x0000000008000be4                FPU_IRQHandler
-                0x0000000008000be4                OTG_HS_WKUP_IRQHandler
-                0x0000000008000be4                FDCAN1_IT1_IRQHandler
-                0x0000000008000be4                LTDC_ER_IRQHandler
-                0x0000000008000be4                DMA2_Stream2_IRQHandler
-                0x0000000008000be4                SPI1_IRQHandler
-                0x0000000008000be4                OCTOSPI1_IRQHandler
-                0x0000000008000be4                TIM6_DAC_IRQHandler
-                0x0000000008000be4                DMA2_Stream3_IRQHandler
-                0x0000000008000be4                OCTOSPI2_IRQHandler
-                0x0000000008000be4                DFSDM1_FLT3_IRQHandler
-                0x0000000008000be4                TIM23_IRQHandler
-                0x0000000008000be4                USART6_IRQHandler
-                0x0000000008000be4                TIM17_IRQHandler
-                0x0000000008000be4                USART3_IRQHandler
-                0x0000000008000be4                BDMA_Channel7_IRQHandler
-                0x0000000008000be4                LPTIM5_IRQHandler
-                0x0000000008000be4                UART5_IRQHandler
-                0x0000000008000be4                ADC3_IRQHandler
-                0x0000000008000be4                DMA2_Stream0_IRQHandler
-                0x0000000008000be4                TIM4_IRQHandler
-                0x0000000008000be4                BDMA_Channel2_IRQHandler
-                0x0000000008000be4                I2C1_EV_IRQHandler
-                0x0000000008000be4                DMA1_Stream6_IRQHandler
-                0x0000000008000be4                DMAMUX1_OVR_IRQHandler
-                0x0000000008000be4                DMA1_Stream1_IRQHandler
-                0x0000000008000be4                TIM16_IRQHandler
-                0x0000000008000be4                UART4_IRQHandler
-                0x0000000008000be4                BDMA_Channel5_IRQHandler
-                0x0000000008000be4                TIM3_IRQHandler
-                0x0000000008000be4                RCC_IRQHandler
-                0x0000000008000be4                UART9_IRQHandler
-                0x0000000008000be4                TIM8_BRK_TIM12_IRQHandler
-                0x0000000008000be4                TIM1_TRG_COM_IRQHandler
-                0x0000000008000be4                Default_Handler
-                0x0000000008000be4                ECC_IRQHandler
-                0x0000000008000be4                FMAC_IRQHandler
-                0x0000000008000be4                CEC_IRQHandler
-                0x0000000008000be4                EXTI15_10_IRQHandler
-                0x0000000008000be4                BDMA_Channel0_IRQHandler
-                0x0000000008000be4                ADC_IRQHandler
-                0x0000000008000be4                I2C5_ER_IRQHandler
-                0x0000000008000be4                DMA1_Stream7_IRQHandler
-                0x0000000008000be4                SPI5_IRQHandler
-                0x0000000008000be4                TIM7_IRQHandler
-                0x0000000008000be4                FDCAN3_IT1_IRQHandler
-                0x0000000008000be4                SDMMC1_IRQHandler
-                0x0000000008000be4                TIM5_IRQHandler
-                0x0000000008000be4                DMA2_Stream7_IRQHandler
-                0x0000000008000be4                TIM15_IRQHandler
-                0x0000000008000be4                PVD_AVD_IRQHandler
-                0x0000000008000be4                I2C3_EV_IRQHandler
-                0x0000000008000be4                EXTI9_5_IRQHandler
-                0x0000000008000be4                RTC_WKUP_IRQHandler
-                0x0000000008000be4                LTDC_IRQHandler
-                0x0000000008000be4                ETH_WKUP_IRQHandler
-                0x0000000008000be4                SPDIF_RX_IRQHandler
-                0x0000000008000be4                SPI2_IRQHandler
-                0x0000000008000be4                OTG_HS_EP1_IN_IRQHandler
-                0x0000000008000be4                DMA1_Stream0_IRQHandler
-                0x0000000008000be4                TIM24_IRQHandler
-                0x0000000008000be4                CRS_IRQHandler
-                0x0000000008000be4                EXTI4_IRQHandler
-                0x0000000008000be4                RNG_IRQHandler
-                0x0000000008000be4                FDCAN2_IT1_IRQHandler
-                0x0000000008000be4                TIM1_UP_IRQHandler
-                0x0000000008000be4                BDMA_Channel4_IRQHandler
-                0x0000000008000be4                OTG_HS_EP1_OUT_IRQHandler
-                0x0000000008000be4                WWDG_IRQHandler
-                0x0000000008000be4                SPI6_IRQHandler
-                0x0000000008000be4                MDIOS_IRQHandler
-                0x0000000008000be4                I2C4_EV_IRQHandler
-                0x0000000008000be4                FDCAN2_IT0_IRQHandler
-                0x0000000008000be4                LPUART1_IRQHandler
-                0x0000000008000be4                FDCAN1_IT0_IRQHandler
-                0x0000000008000be4                TIM2_IRQHandler
-                0x0000000008000be4                OTG_HS_IRQHandler
-                0x0000000008000be4                DMA2D_IRQHandler
-                0x0000000008000be4                TIM1_BRK_IRQHandler
-                0x0000000008000be4                EXTI1_IRQHandler
-                0x0000000008000be4                SDMMC2_IRQHandler
-                0x0000000008000be4                BDMA_Channel3_IRQHandler
-                0x0000000008000be4                DTS_IRQHandler
-                0x0000000008000be4                UART7_IRQHandler
-                0x0000000008000be4                MDIOS_WKUP_IRQHandler
-                0x0000000008000be4                USART2_IRQHandler
-                0x0000000008000be4                DFSDM1_FLT0_IRQHandler
-                0x0000000008000be4                SAI4_IRQHandler
-                0x0000000008000be4                I2C2_ER_IRQHandler
-                0x0000000008000be4                DMA2_Stream1_IRQHandler
-                0x0000000008000be4                FLASH_IRQHandler
-                0x0000000008000be4                DMA2_Stream4_IRQHandler
-                0x0000000008000be4                USART1_IRQHandler
-                0x0000000008000be4                SPI3_IRQHandler
-                0x0000000008000be4                WAKEUP_PIN_IRQHandler
-                0x0000000008000be4                DMA1_Stream4_IRQHandler
-                0x0000000008000be4                I2C1_ER_IRQHandler
-                0x0000000008000be4                FMC_IRQHandler
-                0x0000000008000be4                FDCAN_CAL_IRQHandler
-                0x0000000008000be4                SWPMI1_IRQHandler
-                0x0000000008000be4                COMP1_IRQHandler
-                0x0000000008000be4                LPTIM1_IRQHandler
-                0x0000000008000be4                DCMI_PSSI_IRQHandler
-                0x0000000008000be4                I2C4_ER_IRQHandler
-                0x0000000008000be4                DMA2_Stream6_IRQHandler
-                0x0000000008000be4                SAI1_IRQHandler
-                0x0000000008000be4                DMA1_Stream3_IRQHandler
- .text.LAN8742_RegisterBusIO
-                0x0000000008000be6       0x64 ./Drivers/BSP/Components/lan8742/lan8742.o
-                0x0000000008000be6                LAN8742_RegisterBusIO
- .text.LAN8742_Init
-                0x0000000008000c4a      0x150 ./Drivers/BSP/Components/lan8742/lan8742.o
-                0x0000000008000c4a                LAN8742_Init
- .text.LAN8742_GetLinkState
-                0x0000000008000d9a      0x10e ./Drivers/BSP/Components/lan8742/lan8742.o
-                0x0000000008000d9a                LAN8742_GetLinkState
- .text.HAL_Init
-                0x0000000008000ea8       0x78 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.o
-                0x0000000008000ea8                HAL_Init
+                0x0000000008001500       0x3c ./Core/Src/stm32h7xx_hal_msp.o
+                0x0000000008001500                HAL_MspInit
+ .text.HAL_FDCAN_MspInit
+                0x000000000800153c      0x280 ./Core/Src/stm32h7xx_hal_msp.o
+                0x000000000800153c                HAL_FDCAN_MspInit
+ .text.HAL_SD_MspInit
+                0x00000000080017bc      0x12c ./Core/Src/stm32h7xx_hal_msp.o
+                0x00000000080017bc                HAL_SD_MspInit
+ .text.HAL_TIM_Base_MspInit
+                0x00000000080018e8       0x44 ./Core/Src/stm32h7xx_hal_msp.o
+                0x00000000080018e8                HAL_TIM_Base_MspInit
+ .text.HAL_UART_MspInit
+                0x000000000800192c      0x274 ./Core/Src/stm32h7xx_hal_msp.o
+                0x000000000800192c                HAL_UART_MspInit
  .text.HAL_InitTick
-                0x0000000008000f20       0x6c ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.o
-                0x0000000008000f20                HAL_InitTick
+                0x0000000008001ba0       0xd8 ./Core/Src/stm32h7xx_hal_timebase_tim.o
+                0x0000000008001ba0                HAL_InitTick
+ .text.NMI_Handler
+                0x0000000008001c78        0x6 ./Core/Src/stm32h7xx_it.o
+                0x0000000008001c78                NMI_Handler
+ .text.HardFault_Handler
+                0x0000000008001c7e        0x6 ./Core/Src/stm32h7xx_it.o
+                0x0000000008001c7e                HardFault_Handler
+ .text.MemManage_Handler
+                0x0000000008001c84        0x6 ./Core/Src/stm32h7xx_it.o
+                0x0000000008001c84                MemManage_Handler
+ .text.BusFault_Handler
+                0x0000000008001c8a        0x6 ./Core/Src/stm32h7xx_it.o
+                0x0000000008001c8a                BusFault_Handler
+ .text.UsageFault_Handler
+                0x0000000008001c90        0x6 ./Core/Src/stm32h7xx_it.o
+                0x0000000008001c90                UsageFault_Handler
+ .text.DebugMon_Handler
+                0x0000000008001c96        0xe ./Core/Src/stm32h7xx_it.o
+                0x0000000008001c96                DebugMon_Handler
+ .text.DMA1_Stream0_IRQHandler
+                0x0000000008001ca4       0x14 ./Core/Src/stm32h7xx_it.o
+                0x0000000008001ca4                DMA1_Stream0_IRQHandler
+ .text.FDCAN1_IT0_IRQHandler
+                0x0000000008001cb8       0x14 ./Core/Src/stm32h7xx_it.o
+                0x0000000008001cb8                FDCAN1_IT0_IRQHandler
+ .text.FDCAN2_IT0_IRQHandler
+                0x0000000008001ccc       0x14 ./Core/Src/stm32h7xx_it.o
+                0x0000000008001ccc                FDCAN2_IT0_IRQHandler
+ .text.SDMMC1_IRQHandler
+                0x0000000008001ce0       0x14 ./Core/Src/stm32h7xx_it.o
+                0x0000000008001ce0                SDMMC1_IRQHandler
+ .text.TIM6_DAC_IRQHandler
+                0x0000000008001cf4       0x14 ./Core/Src/stm32h7xx_it.o
+                0x0000000008001cf4                TIM6_DAC_IRQHandler
+ .text.ETH_IRQHandler
+                0x0000000008001d08       0x14 ./Core/Src/stm32h7xx_it.o
+                0x0000000008001d08                ETH_IRQHandler
+ .text.MDMA_IRQHandler
+                0x0000000008001d1c       0x14 ./Core/Src/stm32h7xx_it.o
+                0x0000000008001d1c                MDMA_IRQHandler
+ .text.FDCAN3_IT0_IRQHandler
+                0x0000000008001d30       0x14 ./Core/Src/stm32h7xx_it.o
+                0x0000000008001d30                FDCAN3_IT0_IRQHandler
+ .text._getpid  0x0000000008001d44       0x10 ./Core/Src/syscalls.o
+                0x0000000008001d44                _getpid
+ .text._kill    0x0000000008001d54       0x24 ./Core/Src/syscalls.o
+                0x0000000008001d54                _kill
+ .text._exit    0x0000000008001d78       0x14 ./Core/Src/syscalls.o
+                0x0000000008001d78                _exit
+ .text._read    0x0000000008001d8c       0x3a ./Core/Src/syscalls.o
+                0x0000000008001d8c                _read
+ .text._close   0x0000000008001dc6       0x18 ./Core/Src/syscalls.o
+                0x0000000008001dc6                _close
+ .text._fstat   0x0000000008001dde       0x20 ./Core/Src/syscalls.o
+                0x0000000008001dde                _fstat
+ .text._isatty  0x0000000008001dfe       0x16 ./Core/Src/syscalls.o
+                0x0000000008001dfe                _isatty
+ .text._lseek   0x0000000008001e14       0x1a ./Core/Src/syscalls.o
+                0x0000000008001e14                _lseek
+ *fill*         0x0000000008001e2e        0x2 
+ .text._sbrk    0x0000000008001e30       0x70 ./Core/Src/sysmem.o
+                0x0000000008001e30                _sbrk
+ .text.SystemInit
+                0x0000000008001ea0      0x110 ./Core/Src/system_stm32h7xx.o
+                0x0000000008001ea0                SystemInit
+ .text.Reset_Handler
+                0x0000000008001fb0       0x50 ./Core/Startup/startup_stm32h723vghx.o
+                0x0000000008001fb0                Reset_Handler
+ .text.Default_Handler
+                0x0000000008002000        0x2 ./Core/Startup/startup_stm32h723vghx.o
+                0x0000000008002000                RTC_Alarm_IRQHandler
+                0x0000000008002000                EXTI2_IRQHandler
+                0x0000000008002000                TIM8_CC_IRQHandler
+                0x0000000008002000                UART8_IRQHandler
+                0x0000000008002000                SPI4_IRQHandler
+                0x0000000008002000                TIM1_CC_IRQHandler
+                0x0000000008002000                BDMA_Channel6_IRQHandler
+                0x0000000008002000                DMA2_Stream5_IRQHandler
+                0x0000000008002000                DMA1_Stream5_IRQHandler
+                0x0000000008002000                CORDIC_IRQHandler
+                0x0000000008002000                BDMA_Channel1_IRQHandler
+                0x0000000008002000                TAMP_STAMP_IRQHandler
+                0x0000000008002000                EXTI3_IRQHandler
+                0x0000000008002000                LPTIM4_IRQHandler
+                0x0000000008002000                TIM8_TRG_COM_TIM14_IRQHandler
+                0x0000000008002000                LPTIM2_IRQHandler
+                0x0000000008002000                DFSDM1_FLT1_IRQHandler
+                0x0000000008002000                DMAMUX2_OVR_IRQHandler
+                0x0000000008002000                TIM8_UP_TIM13_IRQHandler
+                0x0000000008002000                I2C3_ER_IRQHandler
+                0x0000000008002000                DFSDM1_FLT2_IRQHandler
+                0x0000000008002000                I2C5_EV_IRQHandler
+                0x0000000008002000                USART10_IRQHandler
+                0x0000000008002000                LPTIM3_IRQHandler
+                0x0000000008002000                HSEM1_IRQHandler
+                0x0000000008002000                EXTI0_IRQHandler
+                0x0000000008002000                I2C2_EV_IRQHandler
+                0x0000000008002000                DMA1_Stream2_IRQHandler
+                0x0000000008002000                FPU_IRQHandler
+                0x0000000008002000                OTG_HS_WKUP_IRQHandler
+                0x0000000008002000                FDCAN1_IT1_IRQHandler
+                0x0000000008002000                LTDC_ER_IRQHandler
+                0x0000000008002000                DMA2_Stream2_IRQHandler
+                0x0000000008002000                SPI1_IRQHandler
+                0x0000000008002000                OCTOSPI1_IRQHandler
+                0x0000000008002000                DMA2_Stream3_IRQHandler
+                0x0000000008002000                OCTOSPI2_IRQHandler
+                0x0000000008002000                DFSDM1_FLT3_IRQHandler
+                0x0000000008002000                TIM23_IRQHandler
+                0x0000000008002000                USART6_IRQHandler
+                0x0000000008002000                TIM17_IRQHandler
+                0x0000000008002000                USART3_IRQHandler
+                0x0000000008002000                BDMA_Channel7_IRQHandler
+                0x0000000008002000                LPTIM5_IRQHandler
+                0x0000000008002000                UART5_IRQHandler
+                0x0000000008002000                ADC3_IRQHandler
+                0x0000000008002000                DMA2_Stream0_IRQHandler
+                0x0000000008002000                TIM4_IRQHandler
+                0x0000000008002000                BDMA_Channel2_IRQHandler
+                0x0000000008002000                I2C1_EV_IRQHandler
+                0x0000000008002000                DMA1_Stream6_IRQHandler
+                0x0000000008002000                DMAMUX1_OVR_IRQHandler
+                0x0000000008002000                DMA1_Stream1_IRQHandler
+                0x0000000008002000                TIM16_IRQHandler
+                0x0000000008002000                UART4_IRQHandler
+                0x0000000008002000                BDMA_Channel5_IRQHandler
+                0x0000000008002000                TIM3_IRQHandler
+                0x0000000008002000                RCC_IRQHandler
+                0x0000000008002000                UART9_IRQHandler
+                0x0000000008002000                TIM8_BRK_TIM12_IRQHandler
+                0x0000000008002000                TIM1_TRG_COM_IRQHandler
+                0x0000000008002000                Default_Handler
+                0x0000000008002000                ECC_IRQHandler
+                0x0000000008002000                FMAC_IRQHandler
+                0x0000000008002000                CEC_IRQHandler
+                0x0000000008002000                EXTI15_10_IRQHandler
+                0x0000000008002000                BDMA_Channel0_IRQHandler
+                0x0000000008002000                ADC_IRQHandler
+                0x0000000008002000                I2C5_ER_IRQHandler
+                0x0000000008002000                DMA1_Stream7_IRQHandler
+                0x0000000008002000                SPI5_IRQHandler
+                0x0000000008002000                TIM7_IRQHandler
+                0x0000000008002000                FDCAN3_IT1_IRQHandler
+                0x0000000008002000                TIM5_IRQHandler
+                0x0000000008002000                DMA2_Stream7_IRQHandler
+                0x0000000008002000                TIM15_IRQHandler
+                0x0000000008002000                PVD_AVD_IRQHandler
+                0x0000000008002000                I2C3_EV_IRQHandler
+                0x0000000008002000                EXTI9_5_IRQHandler
+                0x0000000008002000                RTC_WKUP_IRQHandler
+                0x0000000008002000                LTDC_IRQHandler
+                0x0000000008002000                ETH_WKUP_IRQHandler
+                0x0000000008002000                SPDIF_RX_IRQHandler
+                0x0000000008002000                SPI2_IRQHandler
+                0x0000000008002000                OTG_HS_EP1_IN_IRQHandler
+                0x0000000008002000                TIM24_IRQHandler
+                0x0000000008002000                CRS_IRQHandler
+                0x0000000008002000                EXTI4_IRQHandler
+                0x0000000008002000                RNG_IRQHandler
+                0x0000000008002000                FDCAN2_IT1_IRQHandler
+                0x0000000008002000                TIM1_UP_IRQHandler
+                0x0000000008002000                BDMA_Channel4_IRQHandler
+                0x0000000008002000                OTG_HS_EP1_OUT_IRQHandler
+                0x0000000008002000                WWDG_IRQHandler
+                0x0000000008002000                SPI6_IRQHandler
+                0x0000000008002000                MDIOS_IRQHandler
+                0x0000000008002000                I2C4_EV_IRQHandler
+                0x0000000008002000                LPUART1_IRQHandler
+                0x0000000008002000                TIM2_IRQHandler
+                0x0000000008002000                OTG_HS_IRQHandler
+                0x0000000008002000                DMA2D_IRQHandler
+                0x0000000008002000                TIM1_BRK_IRQHandler
+                0x0000000008002000                EXTI1_IRQHandler
+                0x0000000008002000                SDMMC2_IRQHandler
+                0x0000000008002000                BDMA_Channel3_IRQHandler
+                0x0000000008002000                DTS_IRQHandler
+                0x0000000008002000                UART7_IRQHandler
+                0x0000000008002000                MDIOS_WKUP_IRQHandler
+                0x0000000008002000                USART2_IRQHandler
+                0x0000000008002000                DFSDM1_FLT0_IRQHandler
+                0x0000000008002000                SAI4_IRQHandler
+                0x0000000008002000                I2C2_ER_IRQHandler
+                0x0000000008002000                DMA2_Stream1_IRQHandler
+                0x0000000008002000                FLASH_IRQHandler
+                0x0000000008002000                DMA2_Stream4_IRQHandler
+                0x0000000008002000                USART1_IRQHandler
+                0x0000000008002000                SPI3_IRQHandler
+                0x0000000008002000                WAKEUP_PIN_IRQHandler
+                0x0000000008002000                DMA1_Stream4_IRQHandler
+                0x0000000008002000                I2C1_ER_IRQHandler
+                0x0000000008002000                FMC_IRQHandler
+                0x0000000008002000                FDCAN_CAL_IRQHandler
+                0x0000000008002000                SWPMI1_IRQHandler
+                0x0000000008002000                COMP1_IRQHandler
+                0x0000000008002000                LPTIM1_IRQHandler
+                0x0000000008002000                DCMI_PSSI_IRQHandler
+                0x0000000008002000                I2C4_ER_IRQHandler
+                0x0000000008002000                DMA2_Stream6_IRQHandler
+                0x0000000008002000                SAI1_IRQHandler
+                0x0000000008002000                DMA1_Stream3_IRQHandler
+ .text.LAN8742_RegisterBusIO
+                0x0000000008002002       0x64 ./Drivers/BSP/Components/lan8742/lan8742.o
+                0x0000000008002002                LAN8742_RegisterBusIO
+ .text.LAN8742_Init
+                0x0000000008002066      0x150 ./Drivers/BSP/Components/lan8742/lan8742.o
+                0x0000000008002066                LAN8742_Init
+ .text.LAN8742_GetLinkState
+                0x00000000080021b6      0x10e ./Drivers/BSP/Components/lan8742/lan8742.o
+                0x00000000080021b6                LAN8742_GetLinkState
+ .text.HAL_Init
+                0x00000000080022c4       0x78 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.o
+                0x00000000080022c4                HAL_Init
  .text.HAL_IncTick
-                0x0000000008000f8c       0x28 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.o
-                0x0000000008000f8c                HAL_IncTick
+                0x000000000800233c       0x28 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.o
+                0x000000000800233c                HAL_IncTick
  .text.HAL_GetTick
-                0x0000000008000fb4       0x18 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.o
-                0x0000000008000fb4                HAL_GetTick
+                0x0000000008002364       0x18 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.o
+                0x0000000008002364                HAL_GetTick
+ .text.HAL_Delay
+                0x000000000800237c       0x48 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.o
+                0x000000000800237c                HAL_Delay
  .text.HAL_SYSCFG_ETHInterfaceSelect
-                0x0000000008000fcc       0x28 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.o
-                0x0000000008000fcc                HAL_SYSCFG_ETHInterfaceSelect
+                0x00000000080023c4       0x28 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.o
+                0x00000000080023c4                HAL_SYSCFG_ETHInterfaceSelect
  .text.__NVIC_SetPriorityGrouping
-                0x0000000008000ff4       0x48 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.o
+                0x00000000080023ec       0x48 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.o
  .text.__NVIC_GetPriorityGrouping
-                0x000000000800103c       0x1c ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.o
+                0x0000000008002434       0x1c ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.o
  .text.__NVIC_EnableIRQ
-                0x0000000008001058       0x3c ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.o
+                0x0000000008002450       0x3c ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.o
  .text.__NVIC_SetPriority
-                0x0000000008001094       0x54 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.o
+                0x000000000800248c       0x54 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.o
  .text.NVIC_EncodePriority
-                0x00000000080010e8       0x66 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.o
- *fill*         0x000000000800114e        0x2 
- .text.SysTick_Config
-                0x0000000008001150       0x44 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.o
+                0x00000000080024e0       0x66 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.o
  .text.HAL_NVIC_SetPriorityGrouping
-                0x0000000008001194       0x16 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.o
-                0x0000000008001194                HAL_NVIC_SetPriorityGrouping
+                0x0000000008002546       0x16 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.o
+                0x0000000008002546                HAL_NVIC_SetPriorityGrouping
  .text.HAL_NVIC_SetPriority
-                0x00000000080011aa       0x34 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.o
-                0x00000000080011aa                HAL_NVIC_SetPriority
+                0x000000000800255c       0x34 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.o
+                0x000000000800255c                HAL_NVIC_SetPriority
  .text.HAL_NVIC_EnableIRQ
-                0x00000000080011de       0x1c ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.o
-                0x00000000080011de                HAL_NVIC_EnableIRQ
- .text.HAL_SYSTICK_Config
-                0x00000000080011fa       0x18 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.o
-                0x00000000080011fa                HAL_SYSTICK_Config
- *fill*         0x0000000008001212        0x2 
+                0x0000000008002590       0x1c ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.o
+                0x0000000008002590                HAL_NVIC_EnableIRQ
  .text.HAL_MPU_Disable
-                0x0000000008001214       0x30 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.o
-                0x0000000008001214                HAL_MPU_Disable
+                0x00000000080025ac       0x30 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.o
+                0x00000000080025ac                HAL_MPU_Disable
  .text.HAL_MPU_Enable
-                0x0000000008001244       0x40 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.o
-                0x0000000008001244                HAL_MPU_Enable
+                0x00000000080025dc       0x40 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.o
+                0x00000000080025dc                HAL_MPU_Enable
  .text.HAL_MPU_ConfigRegion
-                0x0000000008001284       0x88 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.o
-                0x0000000008001284                HAL_MPU_ConfigRegion
+                0x000000000800261c       0x88 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.o
+                0x000000000800261c                HAL_MPU_ConfigRegion
+ .text.HAL_DMA_Init
+                0x00000000080026a4      0x6b0 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.o
+                0x00000000080026a4                HAL_DMA_Init
+ .text.HAL_DMA_IRQHandler
+                0x0000000008002d54      0xe54 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.o
+                0x0000000008002d54                HAL_DMA_IRQHandler
+ .text.DMA_CalcBaseAndBitshift
+                0x0000000008003ba8      0x164 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.o
+ .text.DMA_CheckFifoParam
+                0x0000000008003d0c       0xf8 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.o
+ .text.DMA_CalcDMAMUXChannelBaseAndMask
+                0x0000000008003e04      0x134 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.o
+ .text.DMA_CalcDMAMUXRequestGenBaseAndMask
+                0x0000000008003f38       0xe8 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.o
  .text.HAL_ETH_Init
-                0x000000000800130c      0x1cc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o
-                0x000000000800130c                HAL_ETH_Init
- .text.HAL_ETH_Start
-                0x00000000080014d8       0xc4 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o
-                0x00000000080014d8                HAL_ETH_Start
- .text.HAL_ETH_Stop
-                0x000000000800159c       0xa0 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o
-                0x000000000800159c                HAL_ETH_Stop
- .text.HAL_ETH_Transmit
-                0x000000000800163c      0x12e ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o
-                0x000000000800163c                HAL_ETH_Transmit
+                0x0000000008004020      0x1cc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o
+                0x0000000008004020                HAL_ETH_Init
+ .text.HAL_ETH_Start_IT
+                0x00000000080041ec      0x118 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o
+                0x00000000080041ec                HAL_ETH_Start_IT
+ .text.HAL_ETH_Stop_IT
+                0x0000000008004304       0xf0 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o
+                0x0000000008004304                HAL_ETH_Stop_IT
+ .text.HAL_ETH_Transmit_IT
+                0x00000000080043f4       0xa2 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o
+                0x00000000080043f4                HAL_ETH_Transmit_IT
  .text.HAL_ETH_ReadData
-                0x000000000800176a      0x180 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o
-                0x000000000800176a                HAL_ETH_ReadData
+                0x0000000008004496      0x180 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o
+                0x0000000008004496                HAL_ETH_ReadData
  .text.ETH_UpdateDescriptor
-                0x00000000080018ea       0xdc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o
- *fill*         0x00000000080019c6        0x2 
+                0x0000000008004616       0xdc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o
+ .text.HAL_ETH_ReleaseTxPacket
+                0x00000000080046f2       0xb6 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o
+                0x00000000080046f2                HAL_ETH_ReleaseTxPacket
  .text.HAL_ETH_IRQHandler
-                0x00000000080019c8      0x220 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o
-                0x00000000080019c8                HAL_ETH_IRQHandler
- .text.HAL_ETH_TxCpltCallback
-                0x0000000008001be8       0x14 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o
-                0x0000000008001be8                HAL_ETH_TxCpltCallback
- .text.HAL_ETH_RxCpltCallback
-                0x0000000008001bfc       0x14 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o
-                0x0000000008001bfc                HAL_ETH_RxCpltCallback
- .text.HAL_ETH_ErrorCallback
-                0x0000000008001c10       0x14 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o
-                0x0000000008001c10                HAL_ETH_ErrorCallback
+                0x00000000080047a8      0x220 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o
+                0x00000000080047a8                HAL_ETH_IRQHandler
  .text.HAL_ETH_PMTCallback
-                0x0000000008001c24       0x14 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o
-                0x0000000008001c24                HAL_ETH_PMTCallback
+                0x00000000080049c8       0x14 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o
+                0x00000000080049c8                HAL_ETH_PMTCallback
  .text.HAL_ETH_EEECallback
-                0x0000000008001c38       0x14 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o
-                0x0000000008001c38                HAL_ETH_EEECallback
+                0x00000000080049dc       0x14 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o
+                0x00000000080049dc                HAL_ETH_EEECallback
  .text.HAL_ETH_WakeUpCallback
-                0x0000000008001c4c       0x14 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o
-                0x0000000008001c4c                HAL_ETH_WakeUpCallback
+                0x00000000080049f0       0x14 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o
+                0x00000000080049f0                HAL_ETH_WakeUpCallback
  .text.HAL_ETH_ReadPHYRegister
-                0x0000000008001c60       0xa8 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o
-                0x0000000008001c60                HAL_ETH_ReadPHYRegister
+                0x0000000008004a04       0xa8 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o
+                0x0000000008004a04                HAL_ETH_ReadPHYRegister
  .text.HAL_ETH_WritePHYRegister
-                0x0000000008001d08       0xa8 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o
-                0x0000000008001d08                HAL_ETH_WritePHYRegister
+                0x0000000008004aac       0xa8 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o
+                0x0000000008004aac                HAL_ETH_WritePHYRegister
  .text.HAL_ETH_GetMACConfig
-                0x0000000008001db0      0x3a8 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o
-                0x0000000008001db0                HAL_ETH_GetMACConfig
+                0x0000000008004b54      0x3a8 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o
+                0x0000000008004b54                HAL_ETH_GetMACConfig
  .text.HAL_ETH_SetMACConfig
-                0x0000000008002158       0x34 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o
-                0x0000000008002158                HAL_ETH_SetMACConfig
+                0x0000000008004efc       0x34 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o
+                0x0000000008004efc                HAL_ETH_SetMACConfig
  .text.HAL_ETH_SetMDIOClockRange
-                0x000000000800218c       0xb0 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o
-                0x000000000800218c                HAL_ETH_SetMDIOClockRange
+                0x0000000008004f30       0xb0 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o
+                0x0000000008004f30                HAL_ETH_SetMDIOClockRange
+ .text.HAL_ETH_GetDMAError
+                0x0000000008004fe0       0x1a ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o
+                0x0000000008004fe0                HAL_ETH_GetDMAError
+ *fill*         0x0000000008004ffa        0x2 
  .text.ETH_SetMACConfig
-                0x000000000800223c      0x238 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o
+                0x0000000008004ffc      0x238 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o
  .text.ETH_SetDMAConfig
-                0x0000000008002474      0x10c ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o
+                0x0000000008005234      0x10c ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o
  .text.ETH_MACDMAConfig
-                0x0000000008002580      0x13a ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o
+                0x0000000008005340      0x13a ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o
  .text.ETH_DMATxDescListInit
-                0x00000000080026ba       0x92 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o
+                0x000000000800547a       0x92 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o
  .text.ETH_DMARxDescListInit
-                0x000000000800274c       0xba ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o
- *fill*         0x0000000008002806        0x2 
+                0x000000000800550c       0xba ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o
+ *fill*         0x00000000080055c6        0x2 
  .text.ETH_Prepare_Tx_Descriptors
-                0x0000000008002808      0x51c ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o
+                0x00000000080055c8      0x51c ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o
+ .text.HAL_FDCAN_Init
+                0x0000000008005ae4      0x3bc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+                0x0000000008005ae4                HAL_FDCAN_Init
+ .text.HAL_FDCAN_IRQHandler
+                0x0000000008005ea0      0x498 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+                0x0000000008005ea0                HAL_FDCAN_IRQHandler
+ .text.HAL_FDCAN_ClockCalibrationCallback
+                0x0000000008006338       0x16 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+                0x0000000008006338                HAL_FDCAN_ClockCalibrationCallback
+ .text.HAL_FDCAN_TxEventFifoCallback
+                0x000000000800634e       0x16 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+                0x000000000800634e                HAL_FDCAN_TxEventFifoCallback
+ .text.HAL_FDCAN_RxFifo0Callback
+                0x0000000008006364       0x16 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+                0x0000000008006364                HAL_FDCAN_RxFifo0Callback
+ .text.HAL_FDCAN_RxFifo1Callback
+                0x000000000800637a       0x16 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+                0x000000000800637a                HAL_FDCAN_RxFifo1Callback
+ .text.HAL_FDCAN_TxFifoEmptyCallback
+                0x0000000008006390       0x14 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+                0x0000000008006390                HAL_FDCAN_TxFifoEmptyCallback
+ .text.HAL_FDCAN_TxBufferCompleteCallback
+                0x00000000080063a4       0x16 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+                0x00000000080063a4                HAL_FDCAN_TxBufferCompleteCallback
+ .text.HAL_FDCAN_TxBufferAbortCallback
+                0x00000000080063ba       0x16 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+                0x00000000080063ba                HAL_FDCAN_TxBufferAbortCallback
+ .text.HAL_FDCAN_RxBufferNewMessageCallback
+                0x00000000080063d0       0x14 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+                0x00000000080063d0                HAL_FDCAN_RxBufferNewMessageCallback
+ .text.HAL_FDCAN_TimestampWraparoundCallback
+                0x00000000080063e4       0x14 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+                0x00000000080063e4                HAL_FDCAN_TimestampWraparoundCallback
+ .text.HAL_FDCAN_TimeoutOccurredCallback
+                0x00000000080063f8       0x14 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+                0x00000000080063f8                HAL_FDCAN_TimeoutOccurredCallback
+ .text.HAL_FDCAN_HighPriorityMessageCallback
+                0x000000000800640c       0x14 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+                0x000000000800640c                HAL_FDCAN_HighPriorityMessageCallback
+ .text.HAL_FDCAN_ErrorCallback
+                0x0000000008006420       0x14 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+                0x0000000008006420                HAL_FDCAN_ErrorCallback
+ .text.HAL_FDCAN_ErrorStatusCallback
+                0x0000000008006434       0x16 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+                0x0000000008006434                HAL_FDCAN_ErrorStatusCallback
+ .text.HAL_FDCAN_TT_ScheduleSyncCallback
+                0x000000000800644a       0x16 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+                0x000000000800644a                HAL_FDCAN_TT_ScheduleSyncCallback
+ .text.HAL_FDCAN_TT_TimeMarkCallback
+                0x0000000008006460       0x16 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+                0x0000000008006460                HAL_FDCAN_TT_TimeMarkCallback
+ .text.HAL_FDCAN_TT_StopWatchCallback
+                0x0000000008006476       0x18 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+                0x0000000008006476                HAL_FDCAN_TT_StopWatchCallback
+ .text.HAL_FDCAN_TT_GlobalTimeCallback
+                0x000000000800648e       0x16 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+                0x000000000800648e                HAL_FDCAN_TT_GlobalTimeCallback
+ .text.FDCAN_CalcultateRamBlockAddresses
+                0x00000000080064a4      0x30c ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
  .text.HAL_GPIO_Init
-                0x0000000008002d24      0x350 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.o
-                0x0000000008002d24                HAL_GPIO_Init
+                0x00000000080067b0      0x350 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.o
+                0x00000000080067b0                HAL_GPIO_Init
+ .text.HAL_GPIO_ReadPin
+                0x0000000008006b00       0x30 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.o
+                0x0000000008006b00                HAL_GPIO_ReadPin
+ .text.HAL_GPIO_WritePin
+                0x0000000008006b30       0x32 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.o
+                0x0000000008006b30                HAL_GPIO_WritePin
+ .text.HAL_MDMA_Init
+                0x0000000008006b62       0x98 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.o
+                0x0000000008006b62                HAL_MDMA_Init
+ .text.HAL_MDMA_ConfigPostRequestMask
+                0x0000000008006bfa       0xa4 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.o
+                0x0000000008006bfa                HAL_MDMA_ConfigPostRequestMask
+ *fill*         0x0000000008006c9e        0x2 
+ .text.HAL_MDMA_IRQHandler
+                0x0000000008006ca0      0x2a8 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.o
+                0x0000000008006ca0                HAL_MDMA_IRQHandler
+ .text.MDMA_Init
+                0x0000000008006f48      0x130 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.o
  .text.HAL_PWREx_ConfigSupply
-                0x0000000008003074       0x74 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.o
-                0x0000000008003074                HAL_PWREx_ConfigSupply
+                0x0000000008007078       0x74 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.o
+                0x0000000008007078                HAL_PWREx_ConfigSupply
  .text.HAL_RCC_OscConfig
-                0x00000000080030e8      0x7b4 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.o
-                0x00000000080030e8                HAL_RCC_OscConfig
+                0x00000000080070ec      0x7b4 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.o
+                0x00000000080070ec                HAL_RCC_OscConfig
  .text.HAL_RCC_ClockConfig
-                0x000000000800389c      0x36c ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.o
-                0x000000000800389c                HAL_RCC_ClockConfig
+                0x00000000080078a0      0x36c ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.o
+                0x00000000080078a0                HAL_RCC_ClockConfig
  .text.HAL_RCC_GetSysClockFreq
-                0x0000000008003c08      0x2f4 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.o
-                0x0000000008003c08                HAL_RCC_GetSysClockFreq
+                0x0000000008007c0c      0x2f4 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.o
+                0x0000000008007c0c                HAL_RCC_GetSysClockFreq
  .text.HAL_RCC_GetHCLKFreq
-                0x0000000008003efc       0x60 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.o
-                0x0000000008003efc                HAL_RCC_GetHCLKFreq
- .text.lwftp_pcb_close
-                0x0000000008003f5c       0x48 ./LWFTP/lwftp.o
- .text.lwftp_send_next_data
-                0x0000000008003fa4       0x94 ./LWFTP/lwftp.o
- .text.lwftp_data_recv
-                0x0000000008004038       0x8c ./LWFTP/lwftp.o
- .text.lwftp_data_sent
-                0x00000000080040c4       0x38 ./LWFTP/lwftp.o
- .text.lwftp_data_err
-                0x00000000080040fc       0x58 ./LWFTP/lwftp.o
- .text.lwftp_data_connected
-                0x0000000008004154       0x54 ./LWFTP/lwftp.o
+                0x0000000008007f00       0x60 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.o
+                0x0000000008007f00                HAL_RCC_GetHCLKFreq
+ .text.HAL_RCC_GetPCLK1Freq
+                0x0000000008007f60       0x2c ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.o
+                0x0000000008007f60                HAL_RCC_GetPCLK1Freq
+ .text.HAL_RCC_GetPCLK2Freq
+                0x0000000008007f8c       0x2c ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.o
+                0x0000000008007f8c                HAL_RCC_GetPCLK2Freq
+ .text.HAL_RCC_GetClockConfig
+                0x0000000008007fb8       0x84 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.o
+                0x0000000008007fb8                HAL_RCC_GetClockConfig
+ .text.HAL_RCCEx_PeriphCLKConfig
+                0x000000000800803c     0x1340 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.o
+                0x000000000800803c                HAL_RCCEx_PeriphCLKConfig
+ .text.HAL_RCCEx_GetPeriphCLKFreq
+                0x000000000800937c      0x9a4 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.o
+                0x000000000800937c                HAL_RCCEx_GetPeriphCLKFreq
+ .text.HAL_RCCEx_GetD3PCLK1Freq
+                0x0000000008009d20       0x2c ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.o
+                0x0000000008009d20                HAL_RCCEx_GetD3PCLK1Freq
+ .text.HAL_RCCEx_GetPLL2ClockFreq
+                0x0000000008009d4c      0x2a8 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.o
+                0x0000000008009d4c                HAL_RCCEx_GetPLL2ClockFreq
+ .text.HAL_RCCEx_GetPLL3ClockFreq
+                0x0000000008009ff4      0x2a8 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.o
+                0x0000000008009ff4                HAL_RCCEx_GetPLL3ClockFreq
+ .text.HAL_RCCEx_GetPLL1ClockFreq
+                0x000000000800a29c      0x2a4 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.o
+                0x000000000800a29c                HAL_RCCEx_GetPLL1ClockFreq
+ .text.RCCEx_PLL2_Config
+                0x000000000800a540      0x164 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.o
+ .text.RCCEx_PLL3_Config
+                0x000000000800a6a4      0x164 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.o
+ .text.HAL_SD_Init
+                0x000000000800a808      0x106 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.o
+                0x000000000800a808                HAL_SD_Init
+ *fill*         0x000000000800a90e        0x2 
+ .text.HAL_SD_InitCard
+                0x000000000800a910      0x138 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.o
+                0x000000000800a910                HAL_SD_InitCard
+ .text.HAL_SD_ReadBlocks_DMA
+                0x000000000800aa48      0x150 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.o
+                0x000000000800aa48                HAL_SD_ReadBlocks_DMA
+ .text.HAL_SD_WriteBlocks_DMA
+                0x000000000800ab98      0x150 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.o
+                0x000000000800ab98                HAL_SD_WriteBlocks_DMA
+ .text.HAL_SD_IRQHandler
+                0x000000000800ace8      0x370 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.o
+                0x000000000800ace8                HAL_SD_IRQHandler
+ .text.HAL_SD_ErrorCallback
+                0x000000000800b058       0x14 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.o
+                0x000000000800b058                HAL_SD_ErrorCallback
+ .text.HAL_SD_GetCardCSD
+                0x000000000800b06c      0x348 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.o
+                0x000000000800b06c                HAL_SD_GetCardCSD
+ .text.HAL_SD_GetCardStatus
+                0x000000000800b3b4      0x17c ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.o
+                0x000000000800b3b4                HAL_SD_GetCardStatus
+ .text.HAL_SD_GetCardInfo
+                0x000000000800b530       0x58 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.o
+                0x000000000800b530                HAL_SD_GetCardInfo
+ .text.HAL_SD_ConfigWideBusOperation
+                0x000000000800b588      0x224 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.o
+                0x000000000800b588                HAL_SD_ConfigWideBusOperation
+ .text.HAL_SD_GetCardState
+                0x000000000800b7ac       0x40 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.o
+                0x000000000800b7ac                HAL_SD_GetCardState
+ .text.SD_InitCard
+                0x000000000800b7ec      0x19c ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.o
+ .text.SD_PowerON
+                0x000000000800b988      0x11c ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.o
+ .text.SD_SendSDStatus
+                0x000000000800baa4      0x1a0 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.o
+ .text.SD_SendStatus
+                0x000000000800bc44       0x50 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.o
+ .text.SD_WideBus_Enable
+                0x000000000800bc94       0x96 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.o
+ .text.SD_WideBus_Disable
+                0x000000000800bd2a       0x96 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.o
+ .text.SD_FindSCR
+                0x000000000800bdc0      0x1a0 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.o
+ .text.SD_Read_IT
+                0x000000000800bf60       0x8c ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.o
+ .text.SD_Write_IT
+                0x000000000800bfec       0x94 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.o
+ .text.HAL_SDEx_Read_DMADoubleBuf0CpltCallback
+                0x000000000800c080       0x14 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.o
+                0x000000000800c080                HAL_SDEx_Read_DMADoubleBuf0CpltCallback
+ .text.HAL_SDEx_Read_DMADoubleBuf1CpltCallback
+                0x000000000800c094       0x14 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.o
+                0x000000000800c094                HAL_SDEx_Read_DMADoubleBuf1CpltCallback
+ .text.HAL_SDEx_Write_DMADoubleBuf0CpltCallback
+                0x000000000800c0a8       0x14 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.o
+                0x000000000800c0a8                HAL_SDEx_Write_DMADoubleBuf0CpltCallback
+ .text.HAL_SDEx_Write_DMADoubleBuf1CpltCallback
+                0x000000000800c0bc       0x14 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.o
+                0x000000000800c0bc                HAL_SDEx_Write_DMADoubleBuf1CpltCallback
+ .text.HAL_TIM_Base_Init
+                0x000000000800c0d0       0xae ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.o
+                0x000000000800c0d0                HAL_TIM_Base_Init
+ *fill*         0x000000000800c17e        0x2 
+ .text.HAL_TIM_Base_Start_IT
+                0x000000000800c180      0x10c ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.o
+                0x000000000800c180                HAL_TIM_Base_Start_IT
+ .text.HAL_TIM_IRQHandler
+                0x000000000800c28c      0x23e ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.o
+                0x000000000800c28c                HAL_TIM_IRQHandler
+ *fill*         0x000000000800c4ca        0x2 
+ .text.HAL_TIM_ConfigClockSource
+                0x000000000800c4cc      0x1f0 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.o
+                0x000000000800c4cc                HAL_TIM_ConfigClockSource
+ .text.HAL_TIM_OC_DelayElapsedCallback
+                0x000000000800c6bc       0x14 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.o
+                0x000000000800c6bc                HAL_TIM_OC_DelayElapsedCallback
+ .text.HAL_TIM_IC_CaptureCallback
+                0x000000000800c6d0       0x14 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.o
+                0x000000000800c6d0                HAL_TIM_IC_CaptureCallback
+ .text.HAL_TIM_PWM_PulseFinishedCallback
+                0x000000000800c6e4       0x14 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.o
+                0x000000000800c6e4                HAL_TIM_PWM_PulseFinishedCallback
+ .text.HAL_TIM_TriggerCallback
+                0x000000000800c6f8       0x14 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.o
+                0x000000000800c6f8                HAL_TIM_TriggerCallback
+ .text.TIM_Base_SetConfig
+                0x000000000800c70c      0x14c ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.o
+                0x000000000800c70c                TIM_Base_SetConfig
+ .text.TIM_TI1_ConfigInputStage
+                0x000000000800c858       0x5e ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.o
+ .text.TIM_TI2_ConfigInputStage
+                0x000000000800c8b6       0x60 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.o
+ *fill*         0x000000000800c916        0x2 
+ .text.TIM_ITRx_SetConfig
+                0x000000000800c918       0x3c ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.o
+ .text.TIM_ETR_SetConfig
+                0x000000000800c954       0x40 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.o
+                0x000000000800c954                TIM_ETR_SetConfig
+ .text.HAL_TIMEx_MasterConfigSynchronization
+                0x000000000800c994      0x138 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.o
+                0x000000000800c994                HAL_TIMEx_MasterConfigSynchronization
+ .text.HAL_TIMEx_CommutCallback
+                0x000000000800cacc       0x14 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.o
+                0x000000000800cacc                HAL_TIMEx_CommutCallback
+ .text.HAL_TIMEx_BreakCallback
+                0x000000000800cae0       0x14 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.o
+                0x000000000800cae0                HAL_TIMEx_BreakCallback
+ .text.HAL_TIMEx_Break2Callback
+                0x000000000800caf4       0x14 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.o
+                0x000000000800caf4                HAL_TIMEx_Break2Callback
+ .text.HAL_UART_Init
+                0x000000000800cb08       0xa0 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.o
+                0x000000000800cb08                HAL_UART_Init
+ .text.UART_SetConfig
+                0x000000000800cba8      0xcd8 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.o
+                0x000000000800cba8                UART_SetConfig
+ .text.UART_AdvFeatureConfig
+                0x000000000800d880      0x144 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.o
+                0x000000000800d880                UART_AdvFeatureConfig
+ .text.UART_CheckIdleState
+                0x000000000800d9c4      0x154 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.o
+                0x000000000800d9c4                UART_CheckIdleState
+ .text.UART_WaitOnFlagUntilTimeout
+                0x000000000800db18       0xce ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.o
+                0x000000000800db18                UART_WaitOnFlagUntilTimeout
+ *fill*         0x000000000800dbe6        0x2 
+ .text.UART_EndRxTransfer
+                0x000000000800dbe8       0xcc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.o
+ .text.HAL_UARTEx_DisableFifoMode
+                0x000000000800dcb4       0x72 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.o
+                0x000000000800dcb4                HAL_UARTEx_DisableFifoMode
+ .text.HAL_UARTEx_SetTxFifoThreshold
+                0x000000000800dd26       0x7c ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.o
+                0x000000000800dd26                HAL_UARTEx_SetTxFifoThreshold
+ .text.HAL_UARTEx_SetRxFifoThreshold
+                0x000000000800dda2       0x7c ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.o
+                0x000000000800dda2                HAL_UARTEx_SetRxFifoThreshold
+ *fill*         0x000000000800de1e        0x2 
+ .text.UARTEx_SetNbDataToProcess
+                0x000000000800de20       0x9c ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.o
+ .text.SDMMC_Init
+                0x000000000800debc       0x54 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.o
+                0x000000000800debc                SDMMC_Init
+ .text.SDMMC_ReadFIFO
+                0x000000000800df10       0x1a ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.o
+                0x000000000800df10                SDMMC_ReadFIFO
+ .text.SDMMC_WriteFIFO
+                0x000000000800df2a       0x22 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.o
+                0x000000000800df2a                SDMMC_WriteFIFO
+ .text.SDMMC_PowerState_ON
+                0x000000000800df4c       0x22 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.o
+                0x000000000800df4c                SDMMC_PowerState_ON
+ .text.SDMMC_GetPowerState
+                0x000000000800df6e       0x1c ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.o
+                0x000000000800df6e                SDMMC_GetPowerState
+ *fill*         0x000000000800df8a        0x2 
+ .text.SDMMC_SendCommand
+                0x000000000800df8c       0x54 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.o
+                0x000000000800df8c                SDMMC_SendCommand
+ .text.SDMMC_GetCommandResponse
+                0x000000000800dfe0       0x1a ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.o
+                0x000000000800dfe0                SDMMC_GetCommandResponse
+ .text.SDMMC_GetResponse
+                0x000000000800dffa       0x26 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.o
+                0x000000000800dffa                SDMMC_GetResponse
+ .text.SDMMC_ConfigData
+                0x000000000800e020       0x58 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.o
+                0x000000000800e020                SDMMC_ConfigData
+ .text.SDMMC_CmdBlockLength
+                0x000000000800e078       0x46 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.o
+                0x000000000800e078                SDMMC_CmdBlockLength
+ .text.SDMMC_CmdReadSingleBlock
+                0x000000000800e0be       0x46 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.o
+                0x000000000800e0be                SDMMC_CmdReadSingleBlock
+ .text.SDMMC_CmdReadMultiBlock
+                0x000000000800e104       0x46 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.o
+                0x000000000800e104                SDMMC_CmdReadMultiBlock
+ .text.SDMMC_CmdWriteSingleBlock
+                0x000000000800e14a       0x46 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.o
+                0x000000000800e14a                SDMMC_CmdWriteSingleBlock
+ .text.SDMMC_CmdWriteMultiBlock
+                0x000000000800e190       0x46 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.o
+                0x000000000800e190                SDMMC_CmdWriteMultiBlock
+ *fill*         0x000000000800e1d6        0x2 
+ .text.SDMMC_CmdStopTransfer
+                0x000000000800e1d8       0x78 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.o
+                0x000000000800e1d8                SDMMC_CmdStopTransfer
+ .text.SDMMC_CmdSelDesel
+                0x000000000800e250       0x46 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.o
+                0x000000000800e250                SDMMC_CmdSelDesel
+ .text.SDMMC_CmdGoIdleState
+                0x000000000800e296       0x3c ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.o
+                0x000000000800e296                SDMMC_CmdGoIdleState
+ .text.SDMMC_CmdOperCond
+                0x000000000800e2d2       0x40 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.o
+                0x000000000800e2d2                SDMMC_CmdOperCond
+ .text.SDMMC_CmdAppCommand
+                0x000000000800e312       0x46 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.o
+                0x000000000800e312                SDMMC_CmdAppCommand
+ .text.SDMMC_CmdAppOperCommand
+                0x000000000800e358       0x40 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.o
+                0x000000000800e358                SDMMC_CmdAppOperCommand
+ .text.SDMMC_CmdBusWidth
+                0x000000000800e398       0x46 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.o
+                0x000000000800e398                SDMMC_CmdBusWidth
+ .text.SDMMC_CmdSendSCR
+                0x000000000800e3de       0x44 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.o
+                0x000000000800e3de                SDMMC_CmdSendSCR
+ .text.SDMMC_CmdSendCID
+                0x000000000800e422       0x3e ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.o
+                0x000000000800e422                SDMMC_CmdSendCID
+ .text.SDMMC_CmdSendCSD
+                0x000000000800e460       0x40 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.o
+                0x000000000800e460                SDMMC_CmdSendCSD
+ .text.SDMMC_CmdSetRelAdd
+                0x000000000800e4a0       0x44 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.o
+                0x000000000800e4a0                SDMMC_CmdSetRelAdd
+ .text.SDMMC_CmdSendStatus
+                0x000000000800e4e4       0x46 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.o
+                0x000000000800e4e4                SDMMC_CmdSendStatus
+ .text.SDMMC_CmdStatusRegister
+                0x000000000800e52a       0x44 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.o
+                0x000000000800e52a                SDMMC_CmdStatusRegister
+ *fill*         0x000000000800e56e        0x2 
+ .text.SDMMC_GetCmdResp1
+                0x000000000800e570      0x1e4 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.o
+                0x000000000800e570                SDMMC_GetCmdResp1
+ .text.SDMMC_GetCmdResp2
+                0x000000000800e754       0x94 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.o
+                0x000000000800e754                SDMMC_GetCmdResp2
+ .text.SDMMC_GetCmdResp3
+                0x000000000800e7e8       0x80 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.o
+                0x000000000800e7e8                SDMMC_GetCmdResp3
+ .text.SDMMC_GetCmdResp6
+                0x000000000800e868       0xf0 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.o
+                0x000000000800e868                SDMMC_GetCmdResp6
+ .text.SDMMC_GetCmdResp7
+                0x000000000800e958       0x9c ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.o
+                0x000000000800e958                SDMMC_GetCmdResp7
+ .text.SDMMC_GetCmdError
+                0x000000000800e9f4       0x5c ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.o
+ .text.MX_FATFS_Init
+                0x000000000800ea50       0x24 ./FATFS/App/fatfs.o
+                0x000000000800ea50                MX_FATFS_Init
+ .text.BSP_SD_Init
+                0x000000000800ea74       0x4c ./FATFS/Target/bsp_driver_sd.o
+                0x000000000800ea74                BSP_SD_Init
+ .text.BSP_SD_ReadBlocks_DMA
+                0x000000000800eac0       0x34 ./FATFS/Target/bsp_driver_sd.o
+                0x000000000800eac0                BSP_SD_ReadBlocks_DMA
+ .text.BSP_SD_WriteBlocks_DMA
+                0x000000000800eaf4       0x34 ./FATFS/Target/bsp_driver_sd.o
+                0x000000000800eaf4                BSP_SD_WriteBlocks_DMA
+ .text.BSP_SD_GetCardState
+                0x000000000800eb28       0x20 ./FATFS/Target/bsp_driver_sd.o
+                0x000000000800eb28                BSP_SD_GetCardState
+ .text.BSP_SD_GetCardInfo
+                0x000000000800eb48       0x1c ./FATFS/Target/bsp_driver_sd.o
+                0x000000000800eb48                BSP_SD_GetCardInfo
+ .text.HAL_SD_TxCpltCallback
+                0x000000000800eb64       0x14 ./FATFS/Target/bsp_driver_sd.o
+                0x000000000800eb64                HAL_SD_TxCpltCallback
+ .text.HAL_SD_RxCpltCallback
+                0x000000000800eb78       0x14 ./FATFS/Target/bsp_driver_sd.o
+                0x000000000800eb78                HAL_SD_RxCpltCallback
+ .text.BSP_SD_IsDetected
+                0x000000000800eb8c       0x24 ./FATFS/Target/bsp_driver_sd.o
+                0x000000000800eb8c                BSP_SD_IsDetected
+ .text.BSP_PlatformIsDetected
+                0x000000000800ebb0       0x2c ./FATFS/Target/fatfs_platform.o
+                0x000000000800ebb0                BSP_PlatformIsDetected
+ .text.SD_CheckStatusWithTimeout
+                0x000000000800ebdc       0x3a ./FATFS/Target/sd_diskio.o
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+ .text.SD_CheckStatus
+                0x000000000800ec18       0x3c ./FATFS/Target/sd_diskio.o
+ .text.SD_initialize
+                0x000000000800ec54       0x98 ./FATFS/Target/sd_diskio.o
+                0x000000000800ec54                SD_initialize
+ .text.SD_status
+                0x000000000800ecec       0x1c ./FATFS/Target/sd_diskio.o
+                0x000000000800ecec                SD_status
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+                0x000000000800ed08                SD_read
+ .text.SD_write
+                0x000000000800eda4       0x94 ./FATFS/Target/sd_diskio.o
+                0x000000000800eda4                SD_write
+ .text.SD_ioctl
+                0x000000000800ee38       0xb0 ./FATFS/Target/sd_diskio.o
+                0x000000000800ee38                SD_ioctl
+ .text.BSP_SD_WriteCpltCallback
+                0x000000000800eee8       0x1c ./FATFS/Target/sd_diskio.o
+                0x000000000800eee8                BSP_SD_WriteCpltCallback
+ .text.BSP_SD_ReadCpltCallback
+                0x000000000800ef04       0x1c ./FATFS/Target/sd_diskio.o
+                0x000000000800ef04                BSP_SD_ReadCpltCallback
+ .text.lwftp_send
+                0x000000000800ef20       0x60 ./LWFTPC/lwftpc.o
+                0x000000000800ef20                lwftp_send
  .text.lwftp_data_open
-                0x00000000080041a8      0x198 ./LWFTP/lwftp.o
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- .text.lwftp_control_recv
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- .text.lwftp_control_sent
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- .text.lwftp_control_connected
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- .text.lwftp_connect
-                0x0000000008004964      0x110 ./LWFTP/lwftp.o
-                0x0000000008004964                lwftp_connect
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+ .text.lwftp_retrieve
+                0x000000000800f118       0x88 ./LWFTPC/lwftpc.o
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+                0x000000000800f1a0                onDataReceived
+ .text.lwftp_data_thread
+                0x000000000800f1c8       0x88 ./LWFTPC/lwftpc.o
+                0x000000000800f1c8                lwftp_data_thread
+ .text.lwftp_ctrl_thread
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  .text.MX_LWIP_Init
-                0x0000000008004a74      0x24c ./LWIP/App/lwip.o
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- .text.Ethernet_Link_Periodic_Handle
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- .text.MX_LWIP_Process
-                0x0000000008004cf4       0x1c ./LWIP/App/lwip.o
-                0x0000000008004cf4                MX_LWIP_Process
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+                0x000000000800f540                MX_LWIP_Init
  .text.ethernet_link_status_updated
-                0x0000000008004d10       0x14 ./LWIP/App/lwip.o
+                0x000000000800f7b0       0x14 ./LWIP/App/lwip.o
+ .text.HAL_ETH_RxCpltCallback
+                0x000000000800f7c4       0x20 ./LWIP/Target/ethernetif.o
+                0x000000000800f7c4                HAL_ETH_RxCpltCallback
+ .text.HAL_ETH_TxCpltCallback
+                0x000000000800f7e4       0x20 ./LWIP/Target/ethernetif.o
+                0x000000000800f7e4                HAL_ETH_TxCpltCallback
+ .text.HAL_ETH_ErrorCallback
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+                0x000000000800f804                HAL_ETH_ErrorCallback
  .text.low_level_init
-                0x0000000008004d24      0x12c ./LWIP/Target/ethernetif.o
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  .text.low_level_output
-                0x0000000008004e50      0x104 ./LWIP/Target/ethernetif.o
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  .text.low_level_input
-                0x0000000008004f54       0x34 ./LWIP/Target/ethernetif.o
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  .text.ethernetif_input
-                0x0000000008004f88       0x40 ./LWIP/Target/ethernetif.o
-                0x0000000008004f88                ethernetif_input
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  .text.ethernetif_init
-                0x0000000008004fc8       0x5c ./LWIP/Target/ethernetif.o
-                0x0000000008004fc8                ethernetif_init
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  .text.pbuf_free_custom
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+                0x000000000800fce0       0x40 ./LWIP/Target/ethernetif.o
+                0x000000000800fce0                pbuf_free_custom
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  .text.HAL_ETH_MspInit
-                0x0000000008005068      0x168 ./LWIP/Target/ethernetif.o
-                0x0000000008005068                HAL_ETH_MspInit
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  .text.ETH_PHY_IO_Init
-                0x00000000080051d0       0x14 ./LWIP/Target/ethernetif.o
-                0x00000000080051d0                ETH_PHY_IO_Init
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  .text.ETH_PHY_IO_DeInit
-                0x00000000080051e4       0x10 ./LWIP/Target/ethernetif.o
-                0x00000000080051e4                ETH_PHY_IO_DeInit
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  .text.ETH_PHY_IO_ReadReg
-                0x00000000080051f4       0x34 ./LWIP/Target/ethernetif.o
-                0x00000000080051f4                ETH_PHY_IO_ReadReg
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+                0x000000000800febc                ETH_PHY_IO_ReadReg
  .text.ETH_PHY_IO_WriteReg
-                0x0000000008005228       0x34 ./LWIP/Target/ethernetif.o
-                0x0000000008005228                ETH_PHY_IO_WriteReg
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+                0x000000000800fef0                ETH_PHY_IO_WriteReg
  .text.ETH_PHY_IO_GetTick
-                0x000000000800525c        0xe ./LWIP/Target/ethernetif.o
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- .text.ethernet_link_check_state
-                0x000000000800526c      0x118 ./LWIP/Target/ethernetif.o
-                0x000000000800526c                ethernet_link_check_state
+                0x000000000800ff24        0xe ./LWIP/Target/ethernetif.o
+                0x000000000800ff24                ETH_PHY_IO_GetTick
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+ .text.ethernet_link_thread
+                0x000000000800ff34      0x11c ./LWIP/Target/ethernetif.o
+                0x000000000800ff34                ethernet_link_thread
  .text.HAL_ETH_RxAllocateCallback
-                0x0000000008005384       0x60 ./LWIP/Target/ethernetif.o
-                0x0000000008005384                HAL_ETH_RxAllocateCallback
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  .text.HAL_ETH_RxLinkCallback
-                0x00000000080053e4       0xd0 ./LWIP/Target/ethernetif.o
-                0x00000000080053e4                HAL_ETH_RxLinkCallback
- .text.lwip_strerr
-                0x00000000080054b4       0x40 ./Middlewares/Third_Party/LwIP/src/api/err.o
-                0x00000000080054b4                lwip_strerr
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+                0x00000000080100b0                HAL_ETH_RxLinkCallback
+ .text.HAL_ETH_TxFreeCallback
+                0x0000000008010180       0x16 ./LWIP/Target/ethernetif.o
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+ .text.FATFS_LinkDriverEx
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+                0x0000000008010198                FATFS_LinkDriverEx
+ .text.FATFS_LinkDriver
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+ .text.makeFreeRtosPriority
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+ .text.inHandlerMode
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+ .text.osKernelStart
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+                0x00000000080102b0                osKernelRunning
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+                0x00000000080102c8       0x20 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o
+                0x00000000080102c8                osKernelSysTick
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+                0x0000000008010380                osDelay
+ .text.osMutexCreate
+                0x00000000080103a8       0x30 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o
+                0x00000000080103a8                osMutexCreate
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+                0x0000000008010474                osMutexRelease
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+                0x00000000080104e0                osSemaphoreCreate
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+                0x0000000008010544                osSemaphoreWait
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+                0x00000000080105e0                osSemaphoreRelease
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+                0x000000000801064c                osSemaphoreDelete
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+ .text.osMessagePut
+                0x00000000080106c4       0x80 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o
+                0x00000000080106c4                osMessagePut
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+                0x0000000008010744                osMessageGet
+ .text.osMessageWaiting
+                0x000000000801082c       0x2c ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o
+                0x000000000801082c                osMessageWaiting
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+                0x0000000008010858                osMessageDelete
+ .text.vListInitialise
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+ .text.vListInitialiseItem
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+ .text.xQueueGenericCreateStatic
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+ .text.xQueueGenericCreate
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+                0x0000000008010ba8                xQueueGenericCreate
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+ .text.prvInitialiseMutex
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+ .text.xQueueCreateMutex
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+ .text.xQueueCreateMutexStatic
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+ .text.xQueueGenericSend
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+ .text.xQueueGenericSendFromISR
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+ .text.uxQueueMessagesWaitingFromISR
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+ .text.prvGetDisinheritPriorityAfterTimeout
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+ .text.prvCopyDataToQueue
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+ .text.prvCopyDataFromQueue
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+ .text.prvUnlockQueue
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+ .text.prvIsQueueEmpty
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+ .text.prvIsQueueFull
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+ .text.vQueueUnregisterQueue
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+                0x0000000008011a38                xTaskCreateStatic
+ .text.xTaskCreate
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+ .text.prvInitialiseNewTask
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+ .text.vTaskDelay
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+ .text.xTaskGetTickCount
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+                0x0000000008012320                xTaskRemoveFromEventList
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+ .text.prvInitialiseTaskLists
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+ .text.prvCheckTasksWaitingTermination
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+ .text.prvTaskCheckFreeStackSpace
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+ .text.uxTaskGetStackHighWaterMark
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+ .text.prvResetNextTaskUnblockTime
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+ .text.xTaskGetSchedulerState
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+                0x0000000008012a58                pvTaskIncrementMutexHeldCount
+ .text.prvAddCurrentTaskToDelayedList
+                0x0000000008012a80       0xcc ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o
+ .text.xTimerCreateTimerTask
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+                0x0000000008012b4c                xTimerCreateTimerTask
+ .text.xTimerGenericCommand
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+ .text.prvProcessExpiredTimer
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+ .text.prvTimerTask
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+ .text.prvProcessTimerOrBlockTask
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+ .text.prvGetNextExpireTime
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+ .text.prvSampleTimeNow
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+ .text.prvInsertTimerInActiveList
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+ .text.prvProcessReceivedCommands
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+ .text.prvSwitchTimerLists
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+ .text.prvCheckForValidListAndQueue
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+ .text.pxPortInitialiseStack
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+                0x00000000080131b0                pxPortInitialiseStack
+ .text.prvTaskExitError
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+ .text.SVC_Handler
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+ .text.prvPortStartFirstTask
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+ .text.xPortStartScheduler
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+                0x00000000080132c0                xPortStartScheduler
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+                0x0000000008013404                vPortEnterCritical
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+ .text.PendSV_Handler
+                0x00000000080134c0       0x68 ./Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.o
+                0x00000000080134c0                PendSV_Handler
+ .text.SysTick_Handler
+                0x0000000008013528       0x44 ./Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.o
+                0x0000000008013528                SysTick_Handler
+ .text.vPortSetupTimerInterrupt
+                0x000000000801356c       0x48 ./Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.o
+                0x000000000801356c                vPortSetupTimerInterrupt
+ .text.vPortEnableVFP
+                0x00000000080135b4       0x14 ./Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.o
+ .text.vPortValidateInterruptPriority
+                0x00000000080135c8       0x80 ./Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.o
+                0x00000000080135c8                vPortValidateInterruptPriority
+ .text.pvPortMalloc
+                0x0000000008013648      0x198 ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o
+                0x0000000008013648                pvPortMalloc
+ .text.vPortFree
+                0x00000000080137e0       0xc4 ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o
+                0x00000000080137e0                vPortFree
+ .text.prvHeapInit
+                0x00000000080138a4       0xc4 ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o
+ .text.prvInsertBlockIntoFreeList
+                0x0000000008013968       0xb4 ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o
+ .text.netconn_apimsg
+                0x0000000008013a1c       0x40 ./Middlewares/Third_Party/LwIP/src/api/api_lib.o
+ .text.netconn_new_with_proto_and_callback
+                0x0000000008013a5c       0xf4 ./Middlewares/Third_Party/LwIP/src/api/api_lib.o
+                0x0000000008013a5c                netconn_new_with_proto_and_callback
+ .text.netconn_prepare_delete
+                0x0000000008013b50       0x48 ./Middlewares/Third_Party/LwIP/src/api/api_lib.o
+                0x0000000008013b50                netconn_prepare_delete
+ .text.netconn_delete
+                0x0000000008013b98       0x36 ./Middlewares/Third_Party/LwIP/src/api/api_lib.o
+                0x0000000008013b98                netconn_delete
+ *fill*         0x0000000008013bce        0x2 
+ .text.netconn_bind
+                0x0000000008013bd0       0x70 ./Middlewares/Third_Party/LwIP/src/api/api_lib.o
+                0x0000000008013bd0                netconn_bind
+ .text.netconn_connect
+                0x0000000008013c40       0x70 ./Middlewares/Third_Party/LwIP/src/api/api_lib.o
+                0x0000000008013c40                netconn_connect
+ .text.netconn_recv_data
+                0x0000000008013cb0      0x190 ./Middlewares/Third_Party/LwIP/src/api/api_lib.o
+ .text.netconn_tcp_recvd_msg
+                0x0000000008013e40       0x60 ./Middlewares/Third_Party/LwIP/src/api/api_lib.o
+ .text.netconn_recv_data_tcp
+                0x0000000008013ea0      0x108 ./Middlewares/Third_Party/LwIP/src/api/api_lib.o
+ .text.netconn_recv
+                0x0000000008013fa8       0xf4 ./Middlewares/Third_Party/LwIP/src/api/api_lib.o
+                0x0000000008013fa8                netconn_recv
+ .text.netconn_write_partly
+                0x000000000801409c       0x34 ./Middlewares/Third_Party/LwIP/src/api/api_lib.o
+                0x000000000801409c                netconn_write_partly
+ .text.netconn_write_vectors_partly
+                0x00000000080140d0      0x170 ./Middlewares/Third_Party/LwIP/src/api/api_lib.o
+                0x00000000080140d0                netconn_write_vectors_partly
+ .text.netconn_close_shutdown
+                0x0000000008014240       0x60 ./Middlewares/Third_Party/LwIP/src/api/api_lib.o
+ .text.netconn_close
+                0x00000000080142a0       0x1a ./Middlewares/Third_Party/LwIP/src/api/api_lib.o
+                0x00000000080142a0                netconn_close
+ .text.netconn_err
+                0x00000000080142ba       0x36 ./Middlewares/Third_Party/LwIP/src/api/api_lib.o
+                0x00000000080142ba                netconn_err
+ .text.lwip_netconn_err_to_msg
+                0x00000000080142f0       0x6c ./Middlewares/Third_Party/LwIP/src/api/api_msg.o
+ .text.lwip_netconn_is_err_msg
+                0x000000000801435c       0x74 ./Middlewares/Third_Party/LwIP/src/api/api_msg.o
+                0x000000000801435c                lwip_netconn_is_err_msg
+ .text.recv_udp
+                0x00000000080143d0       0xfc ./Middlewares/Third_Party/LwIP/src/api/api_msg.o
+ .text.recv_tcp
+                0x00000000080144cc      0x10c ./Middlewares/Third_Party/LwIP/src/api/api_msg.o
+ .text.poll_tcp
+                0x00000000080145d8       0xcc ./Middlewares/Third_Party/LwIP/src/api/api_msg.o
+ .text.sent_tcp
+                0x00000000080146a4       0xac ./Middlewares/Third_Party/LwIP/src/api/api_msg.o
+ .text.err_tcp  0x0000000008014750      0x1ac ./Middlewares/Third_Party/LwIP/src/api/api_msg.o
+ .text.setup_tcp
+                0x00000000080148fc       0x50 ./Middlewares/Third_Party/LwIP/src/api/api_msg.o
+ .text.pcb_new  0x000000000801494c       0xd4 ./Middlewares/Third_Party/LwIP/src/api/api_msg.o
+ .text.lwip_netconn_do_newconn
+                0x0000000008014a20       0x2a ./Middlewares/Third_Party/LwIP/src/api/api_msg.o
+                0x0000000008014a20                lwip_netconn_do_newconn
+ *fill*         0x0000000008014a4a        0x2 
+ .text.netconn_alloc
+                0x0000000008014a4c       0xdc ./Middlewares/Third_Party/LwIP/src/api/api_msg.o
+                0x0000000008014a4c                netconn_alloc
+ .text.netconn_free
+                0x0000000008014b28       0x94 ./Middlewares/Third_Party/LwIP/src/api/api_msg.o
+                0x0000000008014b28                netconn_free
+ .text.netconn_drain
+                0x0000000008014bbc       0xfa ./Middlewares/Third_Party/LwIP/src/api/api_msg.o
+ *fill*         0x0000000008014cb6        0x2 
+ .text.lwip_netconn_do_close_internal
+                0x0000000008014cb8      0x2d4 ./Middlewares/Third_Party/LwIP/src/api/api_msg.o
+ .text.lwip_netconn_do_delconn
+                0x0000000008014f8c      0x1c8 ./Middlewares/Third_Party/LwIP/src/api/api_msg.o
+                0x0000000008014f8c                lwip_netconn_do_delconn
+ .text.lwip_netconn_do_bind
+                0x0000000008015154       0x74 ./Middlewares/Third_Party/LwIP/src/api/api_msg.o
+                0x0000000008015154                lwip_netconn_do_bind
+ .text.lwip_netconn_do_connected
+                0x00000000080151c8      0x120 ./Middlewares/Third_Party/LwIP/src/api/api_msg.o
+ .text.lwip_netconn_do_connect
+                0x00000000080152e8      0x17c ./Middlewares/Third_Party/LwIP/src/api/api_msg.o
+                0x00000000080152e8                lwip_netconn_do_connect
+ .text.lwip_netconn_do_recv
+                0x0000000008015464       0x6a ./Middlewares/Third_Party/LwIP/src/api/api_msg.o
+                0x0000000008015464                lwip_netconn_do_recv
+ *fill*         0x00000000080154ce        0x2 
+ .text.lwip_netconn_do_writemore
+                0x00000000080154d0      0x39c ./Middlewares/Third_Party/LwIP/src/api/api_msg.o
+ .text.lwip_netconn_do_write
+                0x000000000801586c      0x118 ./Middlewares/Third_Party/LwIP/src/api/api_msg.o
+                0x000000000801586c                lwip_netconn_do_write
+ .text.lwip_netconn_do_close
+                0x0000000008015984      0x118 ./Middlewares/Third_Party/LwIP/src/api/api_msg.o
+                0x0000000008015984                lwip_netconn_do_close
+ .text.netbuf_delete
+                0x0000000008015a9c       0x3e ./Middlewares/Third_Party/LwIP/src/api/netbuf.o
+                0x0000000008015a9c                netbuf_delete
+ *fill*         0x0000000008015ada        0x2 
+ .text.netbuf_data
+                0x0000000008015adc       0x94 ./Middlewares/Third_Party/LwIP/src/api/netbuf.o
+                0x0000000008015adc                netbuf_data
+ .text.netbuf_next
+                0x0000000008015b70       0x60 ./Middlewares/Third_Party/LwIP/src/api/netbuf.o
+                0x0000000008015b70                netbuf_next
+ .text.tcpip_timeouts_mbox_fetch
+                0x0000000008015bd0       0x6c ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
+ .text.tcpip_thread
+                0x0000000008015c3c       0x68 ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
+ .text.tcpip_thread_handle_msg
+                0x0000000008015ca4       0x90 ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
+ .text.tcpip_inpkt
+                0x0000000008015d34       0x88 ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
+                0x0000000008015d34                tcpip_inpkt
+ .text.tcpip_input
+                0x0000000008015dbc       0x44 ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
+                0x0000000008015dbc                tcpip_input
+ .text.tcpip_try_callback
+                0x0000000008015e00       0x80 ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
+                0x0000000008015e00                tcpip_try_callback
+ .text.tcpip_send_msg_wait_sem
+                0x0000000008015e80       0x2c ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
+                0x0000000008015e80                tcpip_send_msg_wait_sem
+ .text.tcpip_init
+                0x0000000008015eac       0x94 ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
+                0x0000000008015eac                tcpip_init
  .text.lwip_htons
-                0x00000000080054f4       0x2a ./Middlewares/Third_Party/LwIP/src/core/def.o
-                0x00000000080054f4                lwip_htons
+                0x0000000008015f40       0x2a ./Middlewares/Third_Party/LwIP/src/core/def.o
+                0x0000000008015f40                lwip_htons
  .text.lwip_htonl
-                0x000000000800551e       0x32 ./Middlewares/Third_Party/LwIP/src/core/def.o
-                0x000000000800551e                lwip_htonl
+                0x0000000008015f6a       0x32 ./Middlewares/Third_Party/LwIP/src/core/def.o
+                0x0000000008015f6a                lwip_htonl
  .text.lwip_standard_chksum
-                0x0000000008005550       0xba ./Middlewares/Third_Party/LwIP/src/core/inet_chksum.o
-                0x0000000008005550                lwip_standard_chksum
+                0x0000000008015f9c       0xba ./Middlewares/Third_Party/LwIP/src/core/inet_chksum.o
+                0x0000000008015f9c                lwip_standard_chksum
  .text.inet_chksum
-                0x000000000800560a       0x24 ./Middlewares/Third_Party/LwIP/src/core/inet_chksum.o
-                0x000000000800560a                inet_chksum
+                0x0000000008016056       0x24 ./Middlewares/Third_Party/LwIP/src/core/inet_chksum.o
+                0x0000000008016056                inet_chksum
  .text.inet_chksum_pbuf
-                0x000000000800562e       0x9a ./Middlewares/Third_Party/LwIP/src/core/inet_chksum.o
-                0x000000000800562e                inet_chksum_pbuf
+                0x000000000801607a       0x9a ./Middlewares/Third_Party/LwIP/src/core/inet_chksum.o
+                0x000000000801607a                inet_chksum_pbuf
  .text.lwip_init
-                0x00000000080056c8       0x2a ./Middlewares/Third_Party/LwIP/src/core/init.o
-                0x00000000080056c8                lwip_init
- *fill*         0x00000000080056f2        0x2 
+                0x0000000008016114       0x2e ./Middlewares/Third_Party/LwIP/src/core/init.o
+                0x0000000008016114                lwip_init
+ *fill*         0x0000000008016142        0x2 
  .text.ptr_to_mem
-                0x00000000080056f4       0x24 ./Middlewares/Third_Party/LwIP/src/core/mem.o
+                0x0000000008016144       0x24 ./Middlewares/Third_Party/LwIP/src/core/mem.o
  .text.mem_to_ptr
-                0x0000000008005718       0x24 ./Middlewares/Third_Party/LwIP/src/core/mem.o
+                0x0000000008016168       0x24 ./Middlewares/Third_Party/LwIP/src/core/mem.o
  .text.plug_holes
-                0x000000000800573c      0x14c ./Middlewares/Third_Party/LwIP/src/core/mem.o
+                0x000000000801618c      0x14c ./Middlewares/Third_Party/LwIP/src/core/mem.o
  .text.mem_init
-                0x0000000008005888       0x70 ./Middlewares/Third_Party/LwIP/src/core/mem.o
-                0x0000000008005888                mem_init
+                0x00000000080162d8       0x9c ./Middlewares/Third_Party/LwIP/src/core/mem.o
+                0x00000000080162d8                mem_init
  .text.mem_link_valid
-                0x00000000080058f8       0x7c ./Middlewares/Third_Party/LwIP/src/core/mem.o
+                0x0000000008016374       0x7c ./Middlewares/Third_Party/LwIP/src/core/mem.o
  .text.mem_free
-                0x0000000008005974       0xfc ./Middlewares/Third_Party/LwIP/src/core/mem.o
-                0x0000000008005974                mem_free
+                0x00000000080163f0      0x148 ./Middlewares/Third_Party/LwIP/src/core/mem.o
+                0x00000000080163f0                mem_free
  .text.mem_trim
-                0x0000000008005a70      0x20c ./Middlewares/Third_Party/LwIP/src/core/mem.o
-                0x0000000008005a70                mem_trim
+                0x0000000008016538      0x228 ./Middlewares/Third_Party/LwIP/src/core/mem.o
+                0x0000000008016538                mem_trim
  .text.mem_malloc
-                0x0000000008005c7c      0x20c ./Middlewares/Third_Party/LwIP/src/core/mem.o
-                0x0000000008005c7c                mem_malloc
+                0x0000000008016760      0x224 ./Middlewares/Third_Party/LwIP/src/core/mem.o
+                0x0000000008016760                mem_malloc
  .text.memp_init_pool
-                0x0000000008005e88       0x60 ./Middlewares/Third_Party/LwIP/src/core/memp.o
-                0x0000000008005e88                memp_init_pool
+                0x0000000008016984       0x60 ./Middlewares/Third_Party/LwIP/src/core/memp.o
+                0x0000000008016984                memp_init_pool
  .text.memp_init
-                0x0000000008005ee8       0x34 ./Middlewares/Third_Party/LwIP/src/core/memp.o
-                0x0000000008005ee8                memp_init
+                0x00000000080169e4       0x34 ./Middlewares/Third_Party/LwIP/src/core/memp.o
+                0x00000000080169e4                memp_init
  .text.do_memp_malloc_pool
-                0x0000000008005f1c       0x64 ./Middlewares/Third_Party/LwIP/src/core/memp.o
+                0x0000000008016a18       0x74 ./Middlewares/Third_Party/LwIP/src/core/memp.o
  .text.memp_malloc_pool
-                0x0000000008005f80       0x44 ./Middlewares/Third_Party/LwIP/src/core/memp.o
-                0x0000000008005f80                memp_malloc_pool
+                0x0000000008016a8c       0x44 ./Middlewares/Third_Party/LwIP/src/core/memp.o
+                0x0000000008016a8c                memp_malloc_pool
  .text.memp_malloc
-                0x0000000008005fc4       0x4c ./Middlewares/Third_Party/LwIP/src/core/memp.o
-                0x0000000008005fc4                memp_malloc
+                0x0000000008016ad0       0x4c ./Middlewares/Third_Party/LwIP/src/core/memp.o
+                0x0000000008016ad0                memp_malloc
  .text.do_memp_free_pool
-                0x0000000008006010       0x4c ./Middlewares/Third_Party/LwIP/src/core/memp.o
+                0x0000000008016b1c       0x58 ./Middlewares/Third_Party/LwIP/src/core/memp.o
  .text.memp_free_pool
-                0x000000000800605c       0x48 ./Middlewares/Third_Party/LwIP/src/core/memp.o
-                0x000000000800605c                memp_free_pool
+                0x0000000008016b74       0x48 ./Middlewares/Third_Party/LwIP/src/core/memp.o
+                0x0000000008016b74                memp_free_pool
  .text.memp_free
-                0x00000000080060a4       0x54 ./Middlewares/Third_Party/LwIP/src/core/memp.o
-                0x00000000080060a4                memp_free
+                0x0000000008016bbc       0x54 ./Middlewares/Third_Party/LwIP/src/core/memp.o
+                0x0000000008016bbc                memp_free
  .text.netif_init
-                0x00000000080060f8        0xe ./Middlewares/Third_Party/LwIP/src/core/netif.o
-                0x00000000080060f8                netif_init
- *fill*         0x0000000008006106        0x2 
+                0x0000000008016c10        0xe ./Middlewares/Third_Party/LwIP/src/core/netif.o
+                0x0000000008016c10                netif_init
+ *fill*         0x0000000008016c1e        0x2 
  .text.netif_add
-                0x0000000008006108      0x2cc ./Middlewares/Third_Party/LwIP/src/core/netif.o
-                0x0000000008006108                netif_add
+                0x0000000008016c20      0x2cc ./Middlewares/Third_Party/LwIP/src/core/netif.o
+                0x0000000008016c20                netif_add
  .text.netif_do_ip_addr_changed
-                0x00000000080063d4       0x22 ./Middlewares/Third_Party/LwIP/src/core/netif.o
- *fill*         0x00000000080063f6        0x2 
+                0x0000000008016eec       0x22 ./Middlewares/Third_Party/LwIP/src/core/netif.o
+ *fill*         0x0000000008016f0e        0x2 
  .text.netif_do_set_ipaddr
-                0x00000000080063f8       0x9c ./Middlewares/Third_Party/LwIP/src/core/netif.o
+                0x0000000008016f10       0x9c ./Middlewares/Third_Party/LwIP/src/core/netif.o
  .text.netif_do_set_netmask
-                0x0000000008006494       0x84 ./Middlewares/Third_Party/LwIP/src/core/netif.o
+                0x0000000008016fac       0x84 ./Middlewares/Third_Party/LwIP/src/core/netif.o
  .text.netif_do_set_gw
-                0x0000000008006518       0x84 ./Middlewares/Third_Party/LwIP/src/core/netif.o
+                0x0000000008017030       0x84 ./Middlewares/Third_Party/LwIP/src/core/netif.o
  .text.netif_set_addr
-                0x000000000800659c       0x94 ./Middlewares/Third_Party/LwIP/src/core/netif.o
-                0x000000000800659c                netif_set_addr
+                0x00000000080170b4       0x94 ./Middlewares/Third_Party/LwIP/src/core/netif.o
+                0x00000000080170b4                netif_set_addr
  .text.netif_set_default
-                0x0000000008006630       0x48 ./Middlewares/Third_Party/LwIP/src/core/netif.o
-                0x0000000008006630                netif_set_default
+                0x0000000008017148       0x48 ./Middlewares/Third_Party/LwIP/src/core/netif.o
+                0x0000000008017148                netif_set_default
  .text.netif_set_up
-                0x0000000008006678       0x58 ./Middlewares/Third_Party/LwIP/src/core/netif.o
-                0x0000000008006678                netif_set_up
+                0x0000000008017190       0x58 ./Middlewares/Third_Party/LwIP/src/core/netif.o
+                0x0000000008017190                netif_set_up
  .text.netif_issue_reports
-                0x00000000080066d0       0x80 ./Middlewares/Third_Party/LwIP/src/core/netif.o
+                0x00000000080171e8       0x80 ./Middlewares/Third_Party/LwIP/src/core/netif.o
  .text.netif_set_down
-                0x0000000008006750       0x64 ./Middlewares/Third_Party/LwIP/src/core/netif.o
-                0x0000000008006750                netif_set_down
+                0x0000000008017268       0x64 ./Middlewares/Third_Party/LwIP/src/core/netif.o
+                0x0000000008017268                netif_set_down
  .text.netif_set_link_up
-                0x00000000080067b4       0x68 ./Middlewares/Third_Party/LwIP/src/core/netif.o
-                0x00000000080067b4                netif_set_link_up
+                0x00000000080172cc       0x68 ./Middlewares/Third_Party/LwIP/src/core/netif.o
+                0x00000000080172cc                netif_set_link_up
  .text.netif_set_link_down
-                0x000000000800681c       0x60 ./Middlewares/Third_Party/LwIP/src/core/netif.o
-                0x000000000800681c                netif_set_link_down
+                0x0000000008017334       0x60 ./Middlewares/Third_Party/LwIP/src/core/netif.o
+                0x0000000008017334                netif_set_link_down
  .text.netif_set_link_callback
-                0x000000000800687c       0x22 ./Middlewares/Third_Party/LwIP/src/core/netif.o
-                0x000000000800687c                netif_set_link_callback
+                0x0000000008017394       0x22 ./Middlewares/Third_Party/LwIP/src/core/netif.o
+                0x0000000008017394                netif_set_link_callback
  .text.netif_null_output_ip4
-                0x000000000800689e       0x1c ./Middlewares/Third_Party/LwIP/src/core/netif.o
- *fill*         0x00000000080068ba        0x2 
+                0x00000000080173b6       0x1c ./Middlewares/Third_Party/LwIP/src/core/netif.o
+ *fill*         0x00000000080173d2        0x2 
  .text.netif_get_by_index
-                0x00000000080068bc       0x4c ./Middlewares/Third_Party/LwIP/src/core/netif.o
-                0x00000000080068bc                netif_get_by_index
+                0x00000000080173d4       0x4c ./Middlewares/Third_Party/LwIP/src/core/netif.o
+                0x00000000080173d4                netif_get_by_index
  .text.pbuf_free_ooseq
-                0x0000000008006908       0x40 ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
-                0x0000000008006908                pbuf_free_ooseq
+                0x0000000008017420       0x4c ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
+ .text.pbuf_free_ooseq_callback
+                0x000000000801746c       0x14 ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
  .text.pbuf_pool_is_empty
-                0x0000000008006948       0x18 ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
+                0x0000000008017480       0x54 ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
  .text.pbuf_init_alloced_pbuf
-                0x0000000008006960       0x54 ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
+                0x00000000080174d4       0x54 ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
  .text.pbuf_alloc
-                0x00000000080069b4      0x1ec ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
-                0x00000000080069b4                pbuf_alloc
+                0x0000000008017528      0x1f4 ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
+                0x0000000008017528                pbuf_alloc
  .text.pbuf_alloc_reference
-                0x0000000008006ba0       0x68 ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
-                0x0000000008006ba0                pbuf_alloc_reference
+                0x000000000801771c       0x68 ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
+                0x000000000801771c                pbuf_alloc_reference
  .text.pbuf_alloced_custom
-                0x0000000008006c08       0x68 ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
-                0x0000000008006c08                pbuf_alloced_custom
+                0x0000000008017784       0x68 ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
+                0x0000000008017784                pbuf_alloced_custom
  .text.pbuf_realloc
-                0x0000000008006c70      0x110 ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
-                0x0000000008006c70                pbuf_realloc
+                0x00000000080177ec      0x110 ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
+                0x00000000080177ec                pbuf_realloc
  .text.pbuf_add_header_impl
-                0x0000000008006d80       0xd0 ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
+                0x00000000080178fc       0xd0 ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
  .text.pbuf_add_header
-                0x0000000008006e50       0x1e ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
-                0x0000000008006e50                pbuf_add_header
- *fill*         0x0000000008006e6e        0x2 
+                0x00000000080179cc       0x1e ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
+                0x00000000080179cc                pbuf_add_header
+ *fill*         0x00000000080179ea        0x2 
  .text.pbuf_remove_header
-                0x0000000008006e70       0xa4 ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
-                0x0000000008006e70                pbuf_remove_header
+                0x00000000080179ec       0xa4 ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
+                0x00000000080179ec                pbuf_remove_header
  .text.pbuf_header_impl
-                0x0000000008006f14       0x42 ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
+                0x0000000008017a90       0x42 ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
  .text.pbuf_header_force
-                0x0000000008006f56       0x24 ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
-                0x0000000008006f56                pbuf_header_force
- *fill*         0x0000000008006f7a        0x2 
+                0x0000000008017ad2       0x24 ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
+                0x0000000008017ad2                pbuf_header_force
+ *fill*         0x0000000008017af6        0x2 
  .text.pbuf_free
-                0x0000000008006f7c      0x110 ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
-                0x0000000008006f7c                pbuf_free
+                0x0000000008017af8      0x11c ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
+                0x0000000008017af8                pbuf_free
  .text.pbuf_clen
-                0x000000000800708c       0x2e ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
-                0x000000000800708c                pbuf_clen
- *fill*         0x00000000080070ba        0x2 
+                0x0000000008017c14       0x2e ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
+                0x0000000008017c14                pbuf_clen
+ *fill*         0x0000000008017c42        0x2 
  .text.pbuf_ref
-                0x00000000080070bc       0x44 ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
-                0x00000000080070bc                pbuf_ref
+                0x0000000008017c44       0x50 ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
+                0x0000000008017c44                pbuf_ref
  .text.pbuf_cat
-                0x0000000008007100       0xac ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
-                0x0000000008007100                pbuf_cat
+                0x0000000008017c94       0xac ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
+                0x0000000008017c94                pbuf_cat
  .text.pbuf_copy
-                0x00000000080071ac      0x1a4 ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
-                0x00000000080071ac                pbuf_copy
+                0x0000000008017d40      0x1a4 ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
+                0x0000000008017d40                pbuf_copy
  .text.pbuf_copy_partial
-                0x0000000008007350       0xe4 ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
-                0x0000000008007350                pbuf_copy_partial
+                0x0000000008017ee4       0xe4 ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
+                0x0000000008017ee4                pbuf_copy_partial
  .text.pbuf_clone
-                0x0000000008007434       0x64 ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
-                0x0000000008007434                pbuf_clone
+                0x0000000008017fc8       0x64 ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
+                0x0000000008017fc8                pbuf_clone
  .text.tcp_init
-                0x0000000008007498       0x24 ./Middlewares/Third_Party/LwIP/src/core/tcp.o
-                0x0000000008007498                tcp_init
+                0x000000000801802c       0x24 ./Middlewares/Third_Party/LwIP/src/core/tcp.o
+                0x000000000801802c                tcp_init
  .text.tcp_free
-                0x00000000080074bc       0x38 ./Middlewares/Third_Party/LwIP/src/core/tcp.o
-                0x00000000080074bc                tcp_free
+                0x0000000008018050       0x38 ./Middlewares/Third_Party/LwIP/src/core/tcp.o
+                0x0000000008018050                tcp_free
  .text.tcp_free_listen
-                0x00000000080074f4       0x38 ./Middlewares/Third_Party/LwIP/src/core/tcp.o
- .text.tcp_tmr  0x000000000800752c       0x2c ./Middlewares/Third_Party/LwIP/src/core/tcp.o
-                0x000000000800752c                tcp_tmr
+                0x0000000008018088       0x38 ./Middlewares/Third_Party/LwIP/src/core/tcp.o
+ .text.tcp_tmr  0x00000000080180c0       0x2c ./Middlewares/Third_Party/LwIP/src/core/tcp.o
+                0x00000000080180c0                tcp_tmr
  .text.tcp_remove_listener
-                0x0000000008007558       0x54 ./Middlewares/Third_Party/LwIP/src/core/tcp.o
+                0x00000000080180ec       0x54 ./Middlewares/Third_Party/LwIP/src/core/tcp.o
  .text.tcp_listen_closed
-                0x00000000080075ac       0x74 ./Middlewares/Third_Party/LwIP/src/core/tcp.o
+                0x0000000008018140       0x74 ./Middlewares/Third_Party/LwIP/src/core/tcp.o
  .text.tcp_close_shutdown
-                0x0000000008007620      0x1c4 ./Middlewares/Third_Party/LwIP/src/core/tcp.o
+                0x00000000080181b4      0x1c4 ./Middlewares/Third_Party/LwIP/src/core/tcp.o
  .text.tcp_close_shutdown_fin
-                0x00000000080077e4       0xd4 ./Middlewares/Third_Party/LwIP/src/core/tcp.o
+                0x0000000008018378       0xd4 ./Middlewares/Third_Party/LwIP/src/core/tcp.o
  .text.tcp_close
-                0x00000000080078b8       0x58 ./Middlewares/Third_Party/LwIP/src/core/tcp.o
-                0x00000000080078b8                tcp_close
+                0x000000000801844c       0x58 ./Middlewares/Third_Party/LwIP/src/core/tcp.o
+                0x000000000801844c                tcp_close
+ .text.tcp_shutdown
+                0x00000000080184a4       0xb8 ./Middlewares/Third_Party/LwIP/src/core/tcp.o
+                0x00000000080184a4                tcp_shutdown
  .text.tcp_abandon
-                0x0000000008007910      0x17c ./Middlewares/Third_Party/LwIP/src/core/tcp.o
-                0x0000000008007910                tcp_abandon
+                0x000000000801855c      0x17c ./Middlewares/Third_Party/LwIP/src/core/tcp.o
+                0x000000000801855c                tcp_abandon
  .text.tcp_abort
-                0x0000000008007a8c       0x18 ./Middlewares/Third_Party/LwIP/src/core/tcp.o
-                0x0000000008007a8c                tcp_abort
+                0x00000000080186d8       0x18 ./Middlewares/Third_Party/LwIP/src/core/tcp.o
+                0x00000000080186d8                tcp_abort
+ .text.tcp_bind
+                0x00000000080186f0      0x130 ./Middlewares/Third_Party/LwIP/src/core/tcp.o
+                0x00000000080186f0                tcp_bind
  .text.tcp_update_rcv_ann_wnd
-                0x0000000008007aa4       0xb4 ./Middlewares/Third_Party/LwIP/src/core/tcp.o
-                0x0000000008007aa4                tcp_update_rcv_ann_wnd
+                0x0000000008018820       0xb4 ./Middlewares/Third_Party/LwIP/src/core/tcp.o
+                0x0000000008018820                tcp_update_rcv_ann_wnd
  .text.tcp_recved
-                0x0000000008007b58       0xa0 ./Middlewares/Third_Party/LwIP/src/core/tcp.o
-                0x0000000008007b58                tcp_recved
+                0x00000000080188d4       0xa4 ./Middlewares/Third_Party/LwIP/src/core/tcp.o
+                0x00000000080188d4                tcp_recved
  .text.tcp_new_port
-                0x0000000008007bf8       0x8c ./Middlewares/Third_Party/LwIP/src/core/tcp.o
+                0x0000000008018978       0x8c ./Middlewares/Third_Party/LwIP/src/core/tcp.o
  .text.tcp_connect
-                0x0000000008007c84      0x230 ./Middlewares/Third_Party/LwIP/src/core/tcp.o
-                0x0000000008007c84                tcp_connect
+                0x0000000008018a04      0x230 ./Middlewares/Third_Party/LwIP/src/core/tcp.o
+                0x0000000008018a04                tcp_connect
  .text.tcp_slowtmr
-                0x0000000008007eb4      0x680 ./Middlewares/Third_Party/LwIP/src/core/tcp.o
-                0x0000000008007eb4                tcp_slowtmr
+                0x0000000008018c34      0x680 ./Middlewares/Third_Party/LwIP/src/core/tcp.o
+                0x0000000008018c34                tcp_slowtmr
  .text.tcp_fasttmr
-                0x0000000008008534       0xc8 ./Middlewares/Third_Party/LwIP/src/core/tcp.o
-                0x0000000008008534                tcp_fasttmr
+                0x00000000080192b4       0xc8 ./Middlewares/Third_Party/LwIP/src/core/tcp.o
+                0x00000000080192b4                tcp_fasttmr
  .text.tcp_process_refused_data
-                0x00000000080085fc       0xf8 ./Middlewares/Third_Party/LwIP/src/core/tcp.o
-                0x00000000080085fc                tcp_process_refused_data
+                0x000000000801937c       0xfc ./Middlewares/Third_Party/LwIP/src/core/tcp.o
+                0x000000000801937c                tcp_process_refused_data
  .text.tcp_segs_free
-                0x00000000080086f4       0x2a ./Middlewares/Third_Party/LwIP/src/core/tcp.o
-                0x00000000080086f4                tcp_segs_free
+                0x0000000008019478       0x2a ./Middlewares/Third_Party/LwIP/src/core/tcp.o
+                0x0000000008019478                tcp_segs_free
  .text.tcp_seg_free
-                0x000000000800871e       0x30 ./Middlewares/Third_Party/LwIP/src/core/tcp.o
-                0x000000000800871e                tcp_seg_free
- *fill*         0x000000000800874e        0x2 
+                0x00000000080194a2       0x30 ./Middlewares/Third_Party/LwIP/src/core/tcp.o
+                0x00000000080194a2                tcp_seg_free
+ *fill*         0x00000000080194d2        0x2 
  .text.tcp_seg_copy
-                0x0000000008008750       0x58 ./Middlewares/Third_Party/LwIP/src/core/tcp.o
-                0x0000000008008750                tcp_seg_copy
+                0x00000000080194d4       0x58 ./Middlewares/Third_Party/LwIP/src/core/tcp.o
+                0x00000000080194d4                tcp_seg_copy
  .text.tcp_recv_null
-                0x00000000080087a8       0x6c ./Middlewares/Third_Party/LwIP/src/core/tcp.o
-                0x00000000080087a8                tcp_recv_null
+                0x000000000801952c       0x6c ./Middlewares/Third_Party/LwIP/src/core/tcp.o
+                0x000000000801952c                tcp_recv_null
  .text.tcp_kill_prio
-                0x0000000008008814       0x9c ./Middlewares/Third_Party/LwIP/src/core/tcp.o
+                0x0000000008019598       0x9c ./Middlewares/Third_Party/LwIP/src/core/tcp.o
  .text.tcp_kill_state
-                0x00000000080088b0       0x94 ./Middlewares/Third_Party/LwIP/src/core/tcp.o
+                0x0000000008019634       0x94 ./Middlewares/Third_Party/LwIP/src/core/tcp.o
  .text.tcp_kill_timewait
-                0x0000000008008944       0x60 ./Middlewares/Third_Party/LwIP/src/core/tcp.o
+                0x00000000080196c8       0x60 ./Middlewares/Third_Party/LwIP/src/core/tcp.o
  .text.tcp_handle_closepend
-                0x00000000080089a4       0x4c ./Middlewares/Third_Party/LwIP/src/core/tcp.o
+                0x0000000008019728       0x4c ./Middlewares/Third_Party/LwIP/src/core/tcp.o
  .text.tcp_alloc
-                0x00000000080089f0      0x108 ./Middlewares/Third_Party/LwIP/src/core/tcp.o
-                0x00000000080089f0                tcp_alloc
- .text.tcp_new  0x0000000008008af8       0x10 ./Middlewares/Third_Party/LwIP/src/core/tcp.o
-                0x0000000008008af8                tcp_new
- .text.tcp_arg  0x0000000008008b08       0x22 ./Middlewares/Third_Party/LwIP/src/core/tcp.o
-                0x0000000008008b08                tcp_arg
- *fill*         0x0000000008008b2a        0x2 
+                0x0000000008019774      0x108 ./Middlewares/Third_Party/LwIP/src/core/tcp.o
+                0x0000000008019774                tcp_alloc
+ .text.tcp_new_ip_type
+                0x000000000801987c       0x1c ./Middlewares/Third_Party/LwIP/src/core/tcp.o
+                0x000000000801987c                tcp_new_ip_type
+ .text.tcp_arg  0x0000000008019898       0x22 ./Middlewares/Third_Party/LwIP/src/core/tcp.o
+                0x0000000008019898                tcp_arg
+ *fill*         0x00000000080198ba        0x2 
  .text.tcp_recv
-                0x0000000008008b2c       0x44 ./Middlewares/Third_Party/LwIP/src/core/tcp.o
-                0x0000000008008b2c                tcp_recv
+                0x00000000080198bc       0x44 ./Middlewares/Third_Party/LwIP/src/core/tcp.o
+                0x00000000080198bc                tcp_recv
  .text.tcp_sent
-                0x0000000008008b70       0x44 ./Middlewares/Third_Party/LwIP/src/core/tcp.o
-                0x0000000008008b70                tcp_sent
- .text.tcp_err  0x0000000008008bb4       0x44 ./Middlewares/Third_Party/LwIP/src/core/tcp.o
-                0x0000000008008bb4                tcp_err
+                0x0000000008019900       0x44 ./Middlewares/Third_Party/LwIP/src/core/tcp.o
+                0x0000000008019900                tcp_sent
+ .text.tcp_err  0x0000000008019944       0x44 ./Middlewares/Third_Party/LwIP/src/core/tcp.o
+                0x0000000008019944                tcp_err
+ .text.tcp_accept
+                0x0000000008019988       0x2e ./Middlewares/Third_Party/LwIP/src/core/tcp.o
+                0x0000000008019988                tcp_accept
+ *fill*         0x00000000080199b6        0x2 
+ .text.tcp_poll
+                0x00000000080199b8       0x60 ./Middlewares/Third_Party/LwIP/src/core/tcp.o
+                0x00000000080199b8                tcp_poll
  .text.tcp_pcb_purge
-                0x0000000008008bf8       0xa0 ./Middlewares/Third_Party/LwIP/src/core/tcp.o
-                0x0000000008008bf8                tcp_pcb_purge
+                0x0000000008019a18       0xa0 ./Middlewares/Third_Party/LwIP/src/core/tcp.o
+                0x0000000008019a18                tcp_pcb_purge
  .text.tcp_pcb_remove
-                0x0000000008008c98      0x128 ./Middlewares/Third_Party/LwIP/src/core/tcp.o
-                0x0000000008008c98                tcp_pcb_remove
+                0x0000000008019ab8      0x128 ./Middlewares/Third_Party/LwIP/src/core/tcp.o
+                0x0000000008019ab8                tcp_pcb_remove
  .text.tcp_next_iss
-                0x0000000008008dc0       0x4c ./Middlewares/Third_Party/LwIP/src/core/tcp.o
-                0x0000000008008dc0                tcp_next_iss
+                0x0000000008019be0       0x4c ./Middlewares/Third_Party/LwIP/src/core/tcp.o
+                0x0000000008019be0                tcp_next_iss
  .text.tcp_eff_send_mss_netif
-                0x0000000008008e0c       0x74 ./Middlewares/Third_Party/LwIP/src/core/tcp.o
-                0x0000000008008e0c                tcp_eff_send_mss_netif
+                0x0000000008019c2c       0x74 ./Middlewares/Third_Party/LwIP/src/core/tcp.o
+                0x0000000008019c2c                tcp_eff_send_mss_netif
  .text.tcp_netif_ip_addr_changed_pcblist
-                0x0000000008008e80       0x70 ./Middlewares/Third_Party/LwIP/src/core/tcp.o
+                0x0000000008019ca0       0x70 ./Middlewares/Third_Party/LwIP/src/core/tcp.o
  .text.tcp_netif_ip_addr_changed
-                0x0000000008008ef0       0x7c ./Middlewares/Third_Party/LwIP/src/core/tcp.o
-                0x0000000008008ef0                tcp_netif_ip_addr_changed
+                0x0000000008019d10       0x7c ./Middlewares/Third_Party/LwIP/src/core/tcp.o
+                0x0000000008019d10                tcp_netif_ip_addr_changed
  .text.tcp_free_ooseq
-                0x0000000008008f6c       0x28 ./Middlewares/Third_Party/LwIP/src/core/tcp.o
-                0x0000000008008f6c                tcp_free_ooseq
+                0x0000000008019d8c       0x28 ./Middlewares/Third_Party/LwIP/src/core/tcp.o
+                0x0000000008019d8c                tcp_free_ooseq
  .text.tcp_input
-                0x0000000008008f94      0x818 ./Middlewares/Third_Party/LwIP/src/core/tcp_in.o
-                0x0000000008008f94                tcp_input
+                0x0000000008019db4      0x818 ./Middlewares/Third_Party/LwIP/src/core/tcp_in.o
+                0x0000000008019db4                tcp_input
  .text.tcp_input_delayed_close
-                0x00000000080097ac       0x80 ./Middlewares/Third_Party/LwIP/src/core/tcp_in.o
+                0x000000000801a5cc       0x80 ./Middlewares/Third_Party/LwIP/src/core/tcp_in.o
  .text.tcp_listen_input
-                0x000000000800982c      0x1fc ./Middlewares/Third_Party/LwIP/src/core/tcp_in.o
+                0x000000000801a64c      0x1fc ./Middlewares/Third_Party/LwIP/src/core/tcp_in.o
  .text.tcp_timewait_input
-                0x0000000008009a28       0xf4 ./Middlewares/Third_Party/LwIP/src/core/tcp_in.o
+                0x000000000801a848       0xf4 ./Middlewares/Third_Party/LwIP/src/core/tcp_in.o
  .text.tcp_process
-                0x0000000008009b1c      0x7e0 ./Middlewares/Third_Party/LwIP/src/core/tcp_in.o
+                0x000000000801a93c      0x7e0 ./Middlewares/Third_Party/LwIP/src/core/tcp_in.o
  .text.tcp_oos_insert_segment
-                0x000000000800a2fc      0x110 ./Middlewares/Third_Party/LwIP/src/core/tcp_in.o
+                0x000000000801b11c      0x110 ./Middlewares/Third_Party/LwIP/src/core/tcp_in.o
  .text.tcp_free_acked_segments
-                0x000000000800a40c       0xf8 ./Middlewares/Third_Party/LwIP/src/core/tcp_in.o
+                0x000000000801b22c       0xf8 ./Middlewares/Third_Party/LwIP/src/core/tcp_in.o
  .text.tcp_receive
-                0x000000000800a504      0xf30 ./Middlewares/Third_Party/LwIP/src/core/tcp_in.o
+                0x000000000801b324      0xf30 ./Middlewares/Third_Party/LwIP/src/core/tcp_in.o
  .text.tcp_get_next_optbyte
-                0x000000000800b434       0x6c ./Middlewares/Third_Party/LwIP/src/core/tcp_in.o
+                0x000000000801c254       0x6c ./Middlewares/Third_Party/LwIP/src/core/tcp_in.o
  .text.tcp_parseopt
-                0x000000000800b4a0       0xec ./Middlewares/Third_Party/LwIP/src/core/tcp_in.o
+                0x000000000801c2c0       0xec ./Middlewares/Third_Party/LwIP/src/core/tcp_in.o
  .text.tcp_trigger_input_pcb_close
-                0x000000000800b58c       0x20 ./Middlewares/Third_Party/LwIP/src/core/tcp_in.o
-                0x000000000800b58c                tcp_trigger_input_pcb_close
+                0x000000000801c3ac       0x20 ./Middlewares/Third_Party/LwIP/src/core/tcp_in.o
+                0x000000000801c3ac                tcp_trigger_input_pcb_close
  .text.tcp_route
-                0x000000000800b5ac       0x38 ./Middlewares/Third_Party/LwIP/src/core/tcp_out.o
+                0x000000000801c3cc       0x38 ./Middlewares/Third_Party/LwIP/src/core/tcp_out.o
  .text.tcp_create_segment
-                0x000000000800b5e4      0x140 ./Middlewares/Third_Party/LwIP/src/core/tcp_out.o
+                0x000000000801c404      0x140 ./Middlewares/Third_Party/LwIP/src/core/tcp_out.o
  .text.tcp_pbuf_prealloc
-                0x000000000800b724       0xf4 ./Middlewares/Third_Party/LwIP/src/core/tcp_out.o
+                0x000000000801c544       0xf4 ./Middlewares/Third_Party/LwIP/src/core/tcp_out.o
  .text.tcp_write_checks
-                0x000000000800b818       0xf4 ./Middlewares/Third_Party/LwIP/src/core/tcp_out.o
+                0x000000000801c638       0xf4 ./Middlewares/Third_Party/LwIP/src/core/tcp_out.o
  .text.tcp_write
-                0x000000000800b90c      0x77c ./Middlewares/Third_Party/LwIP/src/core/tcp_out.o
-                0x000000000800b90c                tcp_write
+                0x000000000801c72c      0x77c ./Middlewares/Third_Party/LwIP/src/core/tcp_out.o
+                0x000000000801c72c                tcp_write
  .text.tcp_split_unsent_seg
-                0x000000000800c088      0x298 ./Middlewares/Third_Party/LwIP/src/core/tcp_out.o
-                0x000000000800c088                tcp_split_unsent_seg
+                0x000000000801cea8      0x298 ./Middlewares/Third_Party/LwIP/src/core/tcp_out.o
+                0x000000000801cea8                tcp_split_unsent_seg
  .text.tcp_send_fin
-                0x000000000800c320       0xa0 ./Middlewares/Third_Party/LwIP/src/core/tcp_out.o
-                0x000000000800c320                tcp_send_fin
+                0x000000000801d140       0xa0 ./Middlewares/Third_Party/LwIP/src/core/tcp_out.o
+                0x000000000801d140                tcp_send_fin
  .text.tcp_enqueue_flags
-                0x000000000800c3c0      0x1dc ./Middlewares/Third_Party/LwIP/src/core/tcp_out.o
-                0x000000000800c3c0                tcp_enqueue_flags
+                0x000000000801d1e0      0x1dc ./Middlewares/Third_Party/LwIP/src/core/tcp_out.o
+                0x000000000801d1e0                tcp_enqueue_flags
  .text.tcp_output
-                0x000000000800c59c      0x3ec ./Middlewares/Third_Party/LwIP/src/core/tcp_out.o
-                0x000000000800c59c                tcp_output
+                0x000000000801d3bc      0x3ec ./Middlewares/Third_Party/LwIP/src/core/tcp_out.o
+                0x000000000801d3bc                tcp_output
  .text.tcp_output_segment_busy
-                0x000000000800c988       0x40 ./Middlewares/Third_Party/LwIP/src/core/tcp_out.o
+                0x000000000801d7a8       0x40 ./Middlewares/Third_Party/LwIP/src/core/tcp_out.o
  .text.tcp_output_segment
-                0x000000000800c9c8      0x1c0 ./Middlewares/Third_Party/LwIP/src/core/tcp_out.o
+                0x000000000801d7e8      0x1c0 ./Middlewares/Third_Party/LwIP/src/core/tcp_out.o
  .text.tcp_rexmit_rto_prepare
-                0x000000000800cb88       0xf4 ./Middlewares/Third_Party/LwIP/src/core/tcp_out.o
-                0x000000000800cb88                tcp_rexmit_rto_prepare
+                0x000000000801d9a8       0xf4 ./Middlewares/Third_Party/LwIP/src/core/tcp_out.o
+                0x000000000801d9a8                tcp_rexmit_rto_prepare
  .text.tcp_rexmit_rto_commit
-                0x000000000800cc7c       0x50 ./Middlewares/Third_Party/LwIP/src/core/tcp_out.o
-                0x000000000800cc7c                tcp_rexmit_rto_commit
+                0x000000000801da9c       0x50 ./Middlewares/Third_Party/LwIP/src/core/tcp_out.o
+                0x000000000801da9c                tcp_rexmit_rto_commit
  .text.tcp_rexmit_rto
-                0x000000000800cccc       0x44 ./Middlewares/Third_Party/LwIP/src/core/tcp_out.o
-                0x000000000800cccc                tcp_rexmit_rto
+                0x000000000801daec       0x44 ./Middlewares/Third_Party/LwIP/src/core/tcp_out.o
+                0x000000000801daec                tcp_rexmit_rto
  .text.tcp_rexmit
-                0x000000000800cd10       0xd8 ./Middlewares/Third_Party/LwIP/src/core/tcp_out.o
-                0x000000000800cd10                tcp_rexmit
+                0x000000000801db30       0xd8 ./Middlewares/Third_Party/LwIP/src/core/tcp_out.o
+                0x000000000801db30                tcp_rexmit
  .text.tcp_rexmit_fast
-                0x000000000800cde8       0xc4 ./Middlewares/Third_Party/LwIP/src/core/tcp_out.o
-                0x000000000800cde8                tcp_rexmit_fast
+                0x000000000801dc08       0xc4 ./Middlewares/Third_Party/LwIP/src/core/tcp_out.o
+                0x000000000801dc08                tcp_rexmit_fast
  .text.tcp_output_alloc_header_common
-                0x000000000800ceac       0xe4 ./Middlewares/Third_Party/LwIP/src/core/tcp_out.o
+                0x000000000801dccc       0xe4 ./Middlewares/Third_Party/LwIP/src/core/tcp_out.o
  .text.tcp_output_alloc_header
-                0x000000000800cf90       0x7c ./Middlewares/Third_Party/LwIP/src/core/tcp_out.o
+                0x000000000801ddb0       0x7c ./Middlewares/Third_Party/LwIP/src/core/tcp_out.o
  .text.tcp_output_fill_options
-                0x000000000800d00c       0x7c ./Middlewares/Third_Party/LwIP/src/core/tcp_out.o
+                0x000000000801de2c       0x7c ./Middlewares/Third_Party/LwIP/src/core/tcp_out.o
  .text.tcp_output_control_segment
-                0x000000000800d088       0x94 ./Middlewares/Third_Party/LwIP/src/core/tcp_out.o
- .text.tcp_rst  0x000000000800d11c       0xa4 ./Middlewares/Third_Party/LwIP/src/core/tcp_out.o
-                0x000000000800d11c                tcp_rst
+                0x000000000801dea8       0x94 ./Middlewares/Third_Party/LwIP/src/core/tcp_out.o
+ .text.tcp_rst  0x000000000801df3c       0xa4 ./Middlewares/Third_Party/LwIP/src/core/tcp_out.o
+                0x000000000801df3c                tcp_rst
  .text.tcp_send_empty_ack
-                0x000000000800d1c0       0xc4 ./Middlewares/Third_Party/LwIP/src/core/tcp_out.o
-                0x000000000800d1c0                tcp_send_empty_ack
+                0x000000000801dfe0       0xc4 ./Middlewares/Third_Party/LwIP/src/core/tcp_out.o
+                0x000000000801dfe0                tcp_send_empty_ack
  .text.tcp_keepalive
-                0x000000000800d284       0x80 ./Middlewares/Third_Party/LwIP/src/core/tcp_out.o
-                0x000000000800d284                tcp_keepalive
+                0x000000000801e0a4       0x80 ./Middlewares/Third_Party/LwIP/src/core/tcp_out.o
+                0x000000000801e0a4                tcp_keepalive
  .text.tcp_zero_window_probe
-                0x000000000800d304      0x154 ./Middlewares/Third_Party/LwIP/src/core/tcp_out.o
-                0x000000000800d304                tcp_zero_window_probe
+                0x000000000801e124      0x154 ./Middlewares/Third_Party/LwIP/src/core/tcp_out.o
+                0x000000000801e124                tcp_zero_window_probe
  .text.tcpip_tcp_timer
-                0x000000000800d458       0x48 ./Middlewares/Third_Party/LwIP/src/core/timeouts.o
+                0x000000000801e278       0x48 ./Middlewares/Third_Party/LwIP/src/core/timeouts.o
  .text.tcp_timer_needed
-                0x000000000800d4a0       0x40 ./Middlewares/Third_Party/LwIP/src/core/timeouts.o
-                0x000000000800d4a0                tcp_timer_needed
+                0x000000000801e2c0       0x40 ./Middlewares/Third_Party/LwIP/src/core/timeouts.o
+                0x000000000801e2c0                tcp_timer_needed
  .text.sys_timeout_abs
-                0x000000000800d4e0       0xdc ./Middlewares/Third_Party/LwIP/src/core/timeouts.o
+                0x000000000801e300       0xdc ./Middlewares/Third_Party/LwIP/src/core/timeouts.o
  .text.lwip_cyclic_timer
-                0x000000000800d5bc       0x64 ./Middlewares/Third_Party/LwIP/src/core/timeouts.o
+                0x000000000801e3dc       0x64 ./Middlewares/Third_Party/LwIP/src/core/timeouts.o
  .text.sys_timeouts_init
-                0x000000000800d620       0x44 ./Middlewares/Third_Party/LwIP/src/core/timeouts.o
-                0x000000000800d620                sys_timeouts_init
+                0x000000000801e440       0x44 ./Middlewares/Third_Party/LwIP/src/core/timeouts.o
+                0x000000000801e440                sys_timeouts_init
  .text.sys_timeout
-                0x000000000800d664       0x4c ./Middlewares/Third_Party/LwIP/src/core/timeouts.o
-                0x000000000800d664                sys_timeout
+                0x000000000801e484       0x4c ./Middlewares/Third_Party/LwIP/src/core/timeouts.o
+                0x000000000801e484                sys_timeout
  .text.sys_check_timeouts
-                0x000000000800d6b0       0x84 ./Middlewares/Third_Party/LwIP/src/core/timeouts.o
-                0x000000000800d6b0                sys_check_timeouts
+                0x000000000801e4d0       0x74 ./Middlewares/Third_Party/LwIP/src/core/timeouts.o
+                0x000000000801e4d0                sys_check_timeouts
+ .text.sys_timeouts_sleeptime
+                0x000000000801e544       0x70 ./Middlewares/Third_Party/LwIP/src/core/timeouts.o
+                0x000000000801e544                sys_timeouts_sleeptime
  .text.udp_init
-                0x000000000800d734       0x24 ./Middlewares/Third_Party/LwIP/src/core/udp.o
-                0x000000000800d734                udp_init
+                0x000000000801e5b4       0x24 ./Middlewares/Third_Party/LwIP/src/core/udp.o
+                0x000000000801e5b4                udp_init
+ .text.udp_new_port
+                0x000000000801e5d8       0x70 ./Middlewares/Third_Party/LwIP/src/core/udp.o
  .text.udp_input_local_match
-                0x000000000800d758       0xc8 ./Middlewares/Third_Party/LwIP/src/core/udp.o
+                0x000000000801e648       0xc8 ./Middlewares/Third_Party/LwIP/src/core/udp.o
  .text.udp_input
-                0x000000000800d820      0x228 ./Middlewares/Third_Party/LwIP/src/core/udp.o
-                0x000000000800d820                udp_input
+                0x000000000801e710      0x228 ./Middlewares/Third_Party/LwIP/src/core/udp.o
+                0x000000000801e710                udp_input
+ .text.udp_bind
+                0x000000000801e938      0x110 ./Middlewares/Third_Party/LwIP/src/core/udp.o
+                0x000000000801e938                udp_bind
+ .text.udp_connect
+                0x000000000801ea48       0xdc ./Middlewares/Third_Party/LwIP/src/core/udp.o
+                0x000000000801ea48                udp_connect
+ .text.udp_recv
+                0x000000000801eb24       0x40 ./Middlewares/Third_Party/LwIP/src/core/udp.o
+                0x000000000801eb24                udp_recv
+ .text.udp_remove
+                0x000000000801eb64       0x84 ./Middlewares/Third_Party/LwIP/src/core/udp.o
+                0x000000000801eb64                udp_remove
+ .text.udp_new  0x000000000801ebe8       0x2e ./Middlewares/Third_Party/LwIP/src/core/udp.o
+                0x000000000801ebe8                udp_new
+ .text.udp_new_ip_type
+                0x000000000801ec16       0x1a ./Middlewares/Third_Party/LwIP/src/core/udp.o
+                0x000000000801ec16                udp_new_ip_type
  .text.udp_netif_ip_addr_changed
-                0x000000000800da48       0x60 ./Middlewares/Third_Party/LwIP/src/core/udp.o
-                0x000000000800da48                udp_netif_ip_addr_changed
+                0x000000000801ec30       0x60 ./Middlewares/Third_Party/LwIP/src/core/udp.o
+                0x000000000801ec30                udp_netif_ip_addr_changed
  .text.etharp_free_entry
-                0x000000000800daa8       0xc0 ./Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.o
+                0x000000000801ec90       0xc0 ./Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.o
  .text.etharp_tmr
-                0x000000000800db68      0x150 ./Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.o
-                0x000000000800db68                etharp_tmr
+                0x000000000801ed50      0x150 ./Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.o
+                0x000000000801ed50                etharp_tmr
  .text.etharp_find_entry
-                0x000000000800dcb8      0x2f0 ./Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.o
+                0x000000000801eea0      0x2f0 ./Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.o
  .text.etharp_update_arp_entry
-                0x000000000800dfa8      0x14c ./Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.o
+                0x000000000801f190      0x14c ./Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.o
  .text.etharp_cleanup_netif
-                0x000000000800e0f4       0x60 ./Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.o
-                0x000000000800e0f4                etharp_cleanup_netif
+                0x000000000801f2dc       0x60 ./Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.o
+                0x000000000801f2dc                etharp_cleanup_netif
  .text.etharp_input
-                0x000000000800e154      0x114 ./Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.o
-                0x000000000800e154                etharp_input
+                0x000000000801f33c      0x114 ./Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.o
+                0x000000000801f33c                etharp_input
  .text.etharp_output_to_arp_index
-                0x000000000800e268      0x134 ./Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.o
+                0x000000000801f450      0x134 ./Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.o
  .text.etharp_output
-                0x000000000800e39c      0x204 ./Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.o
-                0x000000000800e39c                etharp_output
+                0x000000000801f584      0x204 ./Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.o
+                0x000000000801f584                etharp_output
  .text.etharp_query
-                0x000000000800e5a0      0x27c ./Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.o
-                0x000000000800e5a0                etharp_query
+                0x000000000801f788      0x27c ./Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.o
+                0x000000000801f788                etharp_query
  .text.etharp_raw
-                0x000000000800e81c      0x118 ./Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.o
+                0x000000000801fa04      0x118 ./Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.o
  .text.etharp_request_dst
-                0x000000000800e934       0x44 ./Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.o
+                0x000000000801fb1c       0x44 ./Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.o
  .text.etharp_request
-                0x000000000800e978       0x24 ./Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.o
-                0x000000000800e978                etharp_request
+                0x000000000801fb60       0x24 ./Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.o
+                0x000000000801fb60                etharp_request
  .text.icmp_input
-                0x000000000800e99c      0x2ec ./Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.o
-                0x000000000800e99c                icmp_input
+                0x000000000801fb84      0x248 ./Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.o
+                0x000000000801fb84                icmp_input
  .text.icmp_dest_unreach
-                0x000000000800ec88       0x20 ./Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.o
-                0x000000000800ec88                icmp_dest_unreach
+                0x000000000801fdcc       0x20 ./Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.o
+                0x000000000801fdcc                icmp_dest_unreach
  .text.icmp_time_exceeded
-                0x000000000800eca8       0x20 ./Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.o
-                0x000000000800eca8                icmp_time_exceeded
+                0x000000000801fdec       0x20 ./Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.o
+                0x000000000801fdec                icmp_time_exceeded
  .text.icmp_send_response
-                0x000000000800ecc8      0x168 ./Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.o
+                0x000000000801fe0c       0xe8 ./Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.o
  .text.ip4_route
-                0x000000000800ee30       0xe0 ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.o
-                0x000000000800ee30                ip4_route
+                0x000000000801fef4       0xe0 ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.o
+                0x000000000801fef4                ip4_route
  .text.ip4_input_accept
-                0x000000000800ef10       0x54 ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.o
+                0x000000000801ffd4       0x54 ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.o
  .text.ip4_input
-                0x000000000800ef64      0x248 ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.o
-                0x000000000800ef64                ip4_input
+                0x0000000008020028      0x248 ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.o
+                0x0000000008020028                ip4_input
  .text.ip4_output_if
-                0x000000000800f1ac       0x54 ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.o
-                0x000000000800f1ac                ip4_output_if
+                0x0000000008020270       0x54 ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.o
+                0x0000000008020270                ip4_output_if
  .text.ip4_output_if_src
-                0x000000000800f200      0x15c ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.o
-                0x000000000800f200                ip4_output_if_src
+                0x00000000080202c4      0x15c ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.o
+                0x00000000080202c4                ip4_output_if_src
  .text.ip4_addr_isbroadcast_u32
-                0x000000000800f35c       0x82 ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.o
-                0x000000000800f35c                ip4_addr_isbroadcast_u32
- *fill*         0x000000000800f3de        0x2 
+                0x0000000008020420       0x82 ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.o
+                0x0000000008020420                ip4_addr_isbroadcast_u32
+ *fill*         0x00000000080204a2        0x2 
  .text.ip_reass_tmr
-                0x000000000800f3e0       0x58 ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.o
-                0x000000000800f3e0                ip_reass_tmr
+                0x00000000080204a4       0x58 ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.o
+                0x00000000080204a4                ip_reass_tmr
  .text.ip_reass_free_complete_datagram
-                0x000000000800f438      0x148 ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.o
+                0x00000000080204fc      0x148 ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.o
  .text.ip_reass_remove_oldest_datagram
-                0x000000000800f580       0xc4 ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.o
+                0x0000000008020644       0xc4 ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.o
  .text.ip_reass_enqueue_new_datagram
-                0x000000000800f644       0x74 ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.o
+                0x0000000008020708       0x74 ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.o
  .text.ip_reass_dequeue_datagram
-                0x000000000800f6b8       0x5c ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.o
+                0x000000000802077c       0x5c ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.o
  .text.ip_reass_chain_frag_into_datagram_and_validate
-                0x000000000800f714      0x2d4 ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.o
+                0x00000000080207d8      0x2d4 ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.o
  .text.ip4_reass
-                0x000000000800f9e8      0x338 ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.o
-                0x000000000800f9e8                ip4_reass
+                0x0000000008020aac      0x338 ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.o
+                0x0000000008020aac                ip4_reass
  .text.ip_frag_alloc_pbuf_custom_ref
-                0x000000000800fd20       0x10 ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.o
+                0x0000000008020de4       0x10 ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.o
  .text.ip_frag_free_pbuf_custom_ref
-                0x000000000800fd30       0x38 ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.o
+                0x0000000008020df4       0x38 ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.o
  .text.ipfrag_free_pbuf_custom
-                0x000000000800fd68       0x68 ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.o
+                0x0000000008020e2c       0x68 ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.o
  .text.ip4_frag
-                0x000000000800fdd0      0x28c ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.o
-                0x000000000800fdd0                ip4_frag
+                0x0000000008020e94      0x28c ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.o
+                0x0000000008020e94                ip4_frag
  .text.ethernet_input
-                0x000000000801005c      0x11c ./Middlewares/Third_Party/LwIP/src/netif/ethernet.o
-                0x000000000801005c                ethernet_input
+                0x0000000008021120      0x11c ./Middlewares/Third_Party/LwIP/src/netif/ethernet.o
+                0x0000000008021120                ethernet_input
  .text.ethernet_output
-                0x0000000008010178       0x90 ./Middlewares/Third_Party/LwIP/src/netif/ethernet.o
-                0x0000000008010178                ethernet_output
- .text.rand     0x0000000008010208       0x7c C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-rand.o)
-                0x0000000008010208                rand
+                0x000000000802123c       0x90 ./Middlewares/Third_Party/LwIP/src/netif/ethernet.o
+                0x000000000802123c                ethernet_output
+ .text.sys_mbox_new
+                0x00000000080212cc       0x44 ./Middlewares/Third_Party/LwIP/system/OS/sys_arch.o
+                0x00000000080212cc                sys_mbox_new
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-                0x0000000008014e37       0x22 C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-nano-vfprintf_i.o)
-                0x0000000008014e5c                . = ALIGN (0x4)
- *fill*         0x0000000008014e59        0x3 
-
-.rel.dyn        0x0000000008014e5c        0x0
- .rel.iplt      0x0000000008014e5c        0x0 C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+dp/hard/crtbegin.o
+                0x0000000008026ec5       0x22 C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-nano-vfprintf_i.o)
+                0x0000000008026ee8                . = ALIGN (0x4)
+ *fill*         0x0000000008026ee7        0x1 
 
 .ARM.extab
  *(.ARM.extab* .gnu.linkonce.armextab.*)
 
-.ARM            0x0000000008014e5c        0x0
-                0x0000000008014e5c                __exidx_start = .
+.ARM            0x0000000008026ee8        0x8
+                0x0000000008026ee8                __exidx_start = .
  *(.ARM.exidx*)
-                0x0000000008014e5c                __exidx_end = .
+ .ARM.exidx     0x0000000008026ee8        0x8 C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+dp/hard\libgcc.a(_udivmoddi4.o)
+                0x0000000008026ef0                __exidx_end = .
 
-.preinit_array  0x0000000008014e5c        0x0
-                0x0000000008014e5c                PROVIDE (__preinit_array_start = .)
+.rel.dyn        0x0000000008026ef0        0x0
+ .rel.iplt      0x0000000008026ef0        0x0 C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+dp/hard/crtbegin.o
+
+.preinit_array  0x0000000008026ef0        0x0
+                0x0000000008026ef0                PROVIDE (__preinit_array_start = .)
  *(.preinit_array*)
-                0x0000000008014e5c                PROVIDE (__preinit_array_end = .)
+                0x0000000008026ef0                PROVIDE (__preinit_array_end = .)
 
-.init_array     0x0000000008014e5c        0x4
-                0x0000000008014e5c                PROVIDE (__init_array_start = .)
+.init_array     0x0000000008026ef0        0x4
+                0x0000000008026ef0                PROVIDE (__init_array_start = .)
  *(SORT_BY_NAME(.init_array.*))
  *(.init_array*)
- .init_array    0x0000000008014e5c        0x4 C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+dp/hard/crtbegin.o
-                0x0000000008014e60                PROVIDE (__init_array_end = .)
+ .init_array    0x0000000008026ef0        0x4 C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+dp/hard/crtbegin.o
+                0x0000000008026ef4                PROVIDE (__init_array_end = .)
 
-.fini_array     0x0000000008014e60        0x4
+.fini_array     0x0000000008026ef4        0x4
                 [!provide]                        PROVIDE (__fini_array_start = .)
  *(SORT_BY_NAME(.fini_array.*))
  *(.fini_array*)
- .fini_array    0x0000000008014e60        0x4 C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+dp/hard/crtbegin.o
+ .fini_array    0x0000000008026ef4        0x4 C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+dp/hard/crtbegin.o
                 [!provide]                        PROVIDE (__fini_array_end = .)
-                0x0000000008014e64                _sidata = LOADADDR (.data)
+                0x0000000008026ef8                _sidata = LOADADDR (.data)
 
-.data           0x0000000024000000       0xd0 load address 0x0000000008014e64
+.data           0x0000000024000000       0xa4 load address 0x0000000008026ef8
                 0x0000000024000000                . = ALIGN (0x4)
                 0x0000000024000000                _sdata = .
  *(.data)
  *(.data*)
+ .data.CLI_IP   0x0000000024000000        0x4 ./Core/Src/main.o
+                0x0000000024000000                CLI_IP
+ .data.SVR_IP   0x0000000024000004        0x4 ./Core/Src/main.o
+                0x0000000024000004                SVR_IP
+ .data.SVR_PORT
+                0x0000000024000008        0x2 ./Core/Src/main.o
+                0x0000000024000008                SVR_PORT
+ *fill*         0x000000002400000a        0x2 
+ .data.USER     0x000000002400000c        0x4 ./Core/Src/main.o
+                0x000000002400000c                USER
+ .data.PASS     0x0000000024000010        0x4 ./Core/Src/main.o
+                0x0000000024000010                PASS
  .data.SystemCoreClock
-                0x0000000024000000        0x4 ./Core/Src/system_stm32h7xx.o
-                0x0000000024000000                SystemCoreClock
+                0x0000000024000014        0x4 ./Core/Src/system_stm32h7xx.o
+                0x0000000024000014                SystemCoreClock
  .data.SystemD2Clock
-                0x0000000024000004        0x4 ./Core/Src/system_stm32h7xx.o
-                0x0000000024000004                SystemD2Clock
+                0x0000000024000018        0x4 ./Core/Src/system_stm32h7xx.o
+                0x0000000024000018                SystemD2Clock
  .data.uwTickPrio
-                0x0000000024000008        0x4 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.o
-                0x0000000024000008                uwTickPrio
+                0x000000002400001c        0x4 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.o
+                0x000000002400001c                uwTickPrio
  .data.uwTickFreq
-                0x000000002400000c        0x1 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.o
-                0x000000002400000c                uwTickFreq
- *fill*         0x000000002400000d        0x3 
+                0x0000000024000020        0x1 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.o
+                0x0000000024000020                uwTickFreq
+ .data.Stat     0x0000000024000021        0x1 ./FATFS/Target/sd_diskio.o
+ *fill*         0x0000000024000022        0x2 
  .data.LAN8742_IOCtx
-                0x0000000024000010       0x14 ./LWIP/Target/ethernetif.o
-                0x0000000024000010                LAN8742_IOCtx
- .data.err_strerr
-                0x0000000024000024       0x44 ./Middlewares/Third_Party/LwIP/src/api/err.o
+                0x0000000024000024       0x14 ./LWIP/Target/ethernetif.o
+                0x0000000024000024                LAN8742_IOCtx
+ .data.uxCriticalNesting
+                0x0000000024000038        0x4 ./Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.o
  .data.tcp_port
-                0x0000000024000068        0x2 ./Middlewares/Third_Party/LwIP/src/core/tcp.o
- *fill*         0x000000002400006a        0x2 
- .data.iss.0    0x000000002400006c        0x4 ./Middlewares/Third_Party/LwIP/src/core/tcp.o
+                0x000000002400003c        0x2 ./Middlewares/Third_Party/LwIP/src/core/tcp.o
+ *fill*         0x000000002400003e        0x2 
+ .data.iss.0    0x0000000024000040        0x4 ./Middlewares/Third_Party/LwIP/src/core/tcp.o
  .data.udp_port
-                0x0000000024000070        0x2 ./Middlewares/Third_Party/LwIP/src/core/udp.o
- *fill*         0x0000000024000072        0x2 
- .data.__sglue  0x0000000024000074        0xc C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-findfp.o)
-                0x0000000024000074                __sglue
+                0x0000000024000044        0x2 ./Middlewares/Third_Party/LwIP/src/core/udp.o
+ *fill*         0x0000000024000046        0x2 
+ .data.__sglue  0x0000000024000048        0xc C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-findfp.o)
+                0x0000000024000048                __sglue
  .data._impure_data
-                0x0000000024000080       0x4c C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-impure.o)
-                0x0000000024000080                _impure_data
+                0x0000000024000054       0x4c C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-impure.o)
+                0x0000000024000054                _impure_data
  .data._impure_ptr
-                0x00000000240000cc        0x4 C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-impure.o)
-                0x00000000240000cc                _impure_ptr
+                0x00000000240000a0        0x4 C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-impure.o)
+                0x00000000240000a0                _impure_ptr
  *(.RamFunc)
  *(.RamFunc*)
-                0x00000000240000d0                . = ALIGN (0x4)
-                0x00000000240000d0                _edata = .
+                0x00000000240000a4                . = ALIGN (0x4)
+                0x00000000240000a4                _edata = .
 
-.igot.plt       0x00000000240000d0        0x0 load address 0x0000000008014f34
- .igot.plt      0x00000000240000d0        0x0 C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+dp/hard/crtbegin.o
-                0x00000000240000d0                . = ALIGN (0x4)
+.igot.plt       0x00000000240000a4        0x0 load address 0x0000000008026f9c
+ .igot.plt      0x00000000240000a4        0x0 C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+dp/hard/crtbegin.o
+                0x00000000240000a4                . = ALIGN (0x4)
 
-.bss            0x00000000240000d0     0x7d48 load address 0x0000000008014f34
-                0x00000000240000d0                _sbss = .
-                0x00000000240000d0                __bss_start__ = _sbss
+.bss            0x00000000240000a4    0x1a68c load address 0x0000000008026f9c
+                0x00000000240000a4                _sbss = .
+                0x00000000240000a4                __bss_start__ = _sbss
  *(.bss)
- .bss           0x00000000240000d0       0x1c C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+dp/hard/crtbegin.o
+ .bss           0x00000000240000a4       0x1c C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+dp/hard/crtbegin.o
  *(.bss*)
- .bss.offset.2  0x00000000240000ec        0x4 ./Core/Src/main.o
- .bss.s.0       0x00000000240000f0       0x34 ./Core/Src/main.o
+ .bss.xIdleTaskTCBBuffer
+                0x00000000240000c0       0x54 ./Core/Src/freertos.o
+ .bss.xIdleStack
+                0x0000000024000114      0x400 ./Core/Src/freertos.o
+ .bss.xTimerTaskTCBBuffer
+                0x0000000024000514       0x54 ./Core/Src/freertos.o
+ .bss.xTimerStack
+                0x0000000024000568      0x800 ./Core/Src/freertos.o
+ .bss.hfdcan1   0x0000000024000d68       0xa0 ./Core/Src/main.o
+                0x0000000024000d68                hfdcan1
+ .bss.hfdcan2   0x0000000024000e08       0xa0 ./Core/Src/main.o
+                0x0000000024000e08                hfdcan2
+ .bss.hfdcan3   0x0000000024000ea8       0xa0 ./Core/Src/main.o
+                0x0000000024000ea8                hfdcan3
+ .bss.hsd1      0x0000000024000f48       0x7c ./Core/Src/main.o
+                0x0000000024000f48                hsd1
+ .bss.htim3     0x0000000024000fc4       0x4c ./Core/Src/main.o
+                0x0000000024000fc4                htim3
+ .bss.huart4    0x0000000024001010       0x94 ./Core/Src/main.o
+                0x0000000024001010                huart4
+ .bss.huart7    0x00000000240010a4       0x94 ./Core/Src/main.o
+                0x00000000240010a4                huart7
+ .bss.huart8    0x0000000024001138       0x94 ./Core/Src/main.o
+                0x0000000024001138                huart8
+ .bss.hdma_uart8_rx
+                0x00000000240011cc       0x78 ./Core/Src/main.o
+                0x00000000240011cc                hdma_uart8_rx
+ .bss.hmdma_mdma_channel0_sdmmc1_end_data_0
+                0x0000000024001244       0x6c ./Core/Src/main.o
+                0x0000000024001244                hmdma_mdma_channel0_sdmmc1_end_data_0
+ .bss.defaultTaskHandle
+                0x00000000240012b0        0x4 ./Core/Src/main.o
+                0x00000000240012b0                defaultTaskHandle
+ .bss.defaultTaskBuffer
+                0x00000000240012b4     0x4000 ./Core/Src/main.o
+                0x00000000240012b4                defaultTaskBuffer
+ .bss.defaultTaskControlBlock
+                0x00000000240052b4       0x54 ./Core/Src/main.o
+                0x00000000240052b4                defaultTaskControlBlock
+ .bss.debugTaskHandle
+                0x0000000024005308        0x4 ./Core/Src/main.o
+                0x0000000024005308                debugTaskHandle
+ .bss.debugTaskBuffer
+                0x000000002400530c     0x2000 ./Core/Src/main.o
+                0x000000002400530c                debugTaskBuffer
+ .bss.debugTaskControlBlock
+                0x000000002400730c       0x54 ./Core/Src/main.o
+                0x000000002400730c                debugTaskControlBlock
+ .bss.s         0x0000000024007360       0x20 ./Core/Src/main.o
+ .bss.HAL_RCC_FDCAN_CLK_ENABLED
+                0x0000000024007380        0x4 ./Core/Src/stm32h7xx_hal_msp.o
+ .bss.htim6     0x0000000024007384       0x4c ./Core/Src/stm32h7xx_hal_timebase_tim.o
+                0x0000000024007384                htim6
  .bss.__sbrk_heap_end
-                0x0000000024000124        0x4 ./Core/Src/sysmem.o
- .bss.uwTick    0x0000000024000128        0x4 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.o
-                0x0000000024000128                uwTick
- .bss.EthernetLinkTimer
-                0x000000002400012c        0x4 ./LWIP/App/lwip.o
-                0x000000002400012c                EthernetLinkTimer
- .bss.gnetif    0x0000000024000130       0x34 ./LWIP/App/lwip.o
-                0x0000000024000130                gnetif
- .bss.ipaddr    0x0000000024000164        0x4 ./LWIP/App/lwip.o
-                0x0000000024000164                ipaddr
- .bss.netmask   0x0000000024000168        0x4 ./LWIP/App/lwip.o
-                0x0000000024000168                netmask
- .bss.gw        0x000000002400016c        0x4 ./LWIP/App/lwip.o
-                0x000000002400016c                gw
+                0x00000000240073d0        0x4 ./Core/Src/sysmem.o
+ .bss.uwTick    0x00000000240073d4        0x4 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.o
+                0x00000000240073d4                uwTick
+ .bss.retSD     0x00000000240073d8        0x1 ./FATFS/App/fatfs.o
+                0x00000000240073d8                retSD
+ *fill*         0x00000000240073d9        0x3 
+ .bss.SDPath    0x00000000240073dc        0x4 ./FATFS/App/fatfs.o
+                0x00000000240073dc                SDPath
+ .bss.SDQueueID
+                0x00000000240073e0        0x4 ./FATFS/Target/sd_diskio.o
+ .bss.d_buf.1   0x00000000240073e4        0x4 ./LWFTPC/lwftpc.o
+ .bss.buf.0     0x00000000240073e8        0x4 ./LWFTPC/lwftpc.o
+ .bss.gnetif    0x00000000240073ec       0x34 ./LWIP/App/lwip.o
+                0x00000000240073ec                gnetif
+ .bss.ipaddr    0x0000000024007420        0x4 ./LWIP/App/lwip.o
+                0x0000000024007420                ipaddr
+ .bss.netmask   0x0000000024007424        0x4 ./LWIP/App/lwip.o
+                0x0000000024007424                netmask
+ .bss.gw        0x0000000024007428        0x4 ./LWIP/App/lwip.o
+                0x0000000024007428                gw
  .bss.IP_ADDRESS
-                0x0000000024000170        0x4 ./LWIP/App/lwip.o
-                0x0000000024000170                IP_ADDRESS
+                0x000000002400742c        0x4 ./LWIP/App/lwip.o
+                0x000000002400742c                IP_ADDRESS
  .bss.NETMASK_ADDRESS
-                0x0000000024000174        0x4 ./LWIP/App/lwip.o
-                0x0000000024000174                NETMASK_ADDRESS
+                0x0000000024007430        0x4 ./LWIP/App/lwip.o
+                0x0000000024007430                NETMASK_ADDRESS
  .bss.GATEWAY_ADDRESS
-                0x0000000024000178        0x4 ./LWIP/App/lwip.o
-                0x0000000024000178                GATEWAY_ADDRESS
+                0x0000000024007434        0x4 ./LWIP/App/lwip.o
+                0x0000000024007434                GATEWAY_ADDRESS
  .bss.memp_memory_RX_POOL_base
-                0x000000002400017c     0x4983 ./LWIP/Target/ethernetif.o
-                0x000000002400017c                memp_memory_RX_POOL_base
- *fill*         0x0000000024004aff        0x1 
+                0x0000000024007438     0x4983 ./LWIP/Target/ethernetif.o
+                0x0000000024007438                memp_memory_RX_POOL_base
+ *fill*         0x000000002400bdbb        0x1 
  .bss.memp_tab_RX_POOL
-                0x0000000024004b00        0x4 ./LWIP/Target/ethernetif.o
+                0x000000002400bdbc        0x4 ./LWIP/Target/ethernetif.o
  .bss.RxAllocStatus
-                0x0000000024004b04        0x1 ./LWIP/Target/ethernetif.o
- *fill*         0x0000000024004b05        0x3 
- .bss.heth      0x0000000024004b08       0xb0 ./LWIP/Target/ethernetif.o
-                0x0000000024004b08                heth
- .bss.TxConfig  0x0000000024004bb8       0x38 ./LWIP/Target/ethernetif.o
-                0x0000000024004bb8                TxConfig
- .bss.LAN8742   0x0000000024004bf0       0x20 ./LWIP/Target/ethernetif.o
-                0x0000000024004bf0                LAN8742
- .bss.ip_data   0x0000000024004c10       0x18 ./Middlewares/Third_Party/LwIP/src/core/ip.o
-                0x0000000024004c10                ip_data
- .bss.ram       0x0000000024004c28        0x4 ./Middlewares/Third_Party/LwIP/src/core/mem.o
- .bss.ram_end   0x0000000024004c2c        0x4 ./Middlewares/Third_Party/LwIP/src/core/mem.o
- .bss.lfree     0x0000000024004c30        0x4 ./Middlewares/Third_Party/LwIP/src/core/mem.o
+                0x000000002400bdc0        0x1 ./LWIP/Target/ethernetif.o
+ *fill*         0x000000002400bdc1        0x3 
+ .bss.RxPktSemaphore
+                0x000000002400bdc4        0x4 ./LWIP/Target/ethernetif.o
+                0x000000002400bdc4                RxPktSemaphore
+ .bss.TxPktSemaphore
+                0x000000002400bdc8        0x4 ./LWIP/Target/ethernetif.o
+                0x000000002400bdc8                TxPktSemaphore
+ .bss.heth      0x000000002400bdcc       0xb0 ./LWIP/Target/ethernetif.o
+                0x000000002400bdcc                heth
+ .bss.TxConfig  0x000000002400be7c       0x38 ./LWIP/Target/ethernetif.o
+                0x000000002400be7c                TxConfig
+ .bss.LAN8742   0x000000002400beb4       0x20 ./LWIP/Target/ethernetif.o
+                0x000000002400beb4                LAN8742
+ .bss.disk      0x000000002400bed4        0xc ./Middlewares/Third_Party/FatFs/src/ff_gen_drv.o
+                0x000000002400bed4                disk
+ .bss.xQueueRegistry
+                0x000000002400bee0       0x40 ./Middlewares/Third_Party/FreeRTOS/Source/queue.o
+                0x000000002400bee0                xQueueRegistry
+ .bss.pxCurrentTCB
+                0x000000002400bf20        0x4 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o
+                0x000000002400bf20                pxCurrentTCB
+ .bss.pxReadyTasksLists
+                0x000000002400bf24       0x8c ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o
+ .bss.xDelayedTaskList1
+                0x000000002400bfb0       0x14 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o
+ .bss.xDelayedTaskList2
+                0x000000002400bfc4       0x14 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o
+ .bss.pxDelayedTaskList
+                0x000000002400bfd8        0x4 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o
+ .bss.pxOverflowDelayedTaskList
+                0x000000002400bfdc        0x4 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o
+ .bss.xPendingReadyList
+                0x000000002400bfe0       0x14 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o
+ .bss.xTasksWaitingTermination
+                0x000000002400bff4       0x14 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o
+ .bss.uxDeletedTasksWaitingCleanUp
+                0x000000002400c008        0x4 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o
+ .bss.xSuspendedTaskList
+                0x000000002400c00c       0x14 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o
+ .bss.uxCurrentNumberOfTasks
+                0x000000002400c020        0x4 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o
+ .bss.xTickCount
+                0x000000002400c024        0x4 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o
+ .bss.uxTopReadyPriority
+                0x000000002400c028        0x4 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o
+ .bss.xSchedulerRunning
+                0x000000002400c02c        0x4 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o
+ .bss.xPendedTicks
+                0x000000002400c030        0x4 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o
+ .bss.xYieldPending
+                0x000000002400c034        0x4 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o
+ .bss.xNumOfOverflows
+                0x000000002400c038        0x4 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o
+ .bss.uxTaskNumber
+                0x000000002400c03c        0x4 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o
+ .bss.xNextTaskUnblockTime
+                0x000000002400c040        0x4 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o
+ .bss.xIdleTaskHandle
+                0x000000002400c044        0x4 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o
+ .bss.uxSchedulerSuspended
+                0x000000002400c048        0x4 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o
+ .bss.xActiveTimerList1
+                0x000000002400c04c       0x14 ./Middlewares/Third_Party/FreeRTOS/Source/timers.o
+ .bss.xActiveTimerList2
+                0x000000002400c060       0x14 ./Middlewares/Third_Party/FreeRTOS/Source/timers.o
+ .bss.pxCurrentTimerList
+                0x000000002400c074        0x4 ./Middlewares/Third_Party/FreeRTOS/Source/timers.o
+ .bss.pxOverflowTimerList
+                0x000000002400c078        0x4 ./Middlewares/Third_Party/FreeRTOS/Source/timers.o
+ .bss.xTimerQueue
+                0x000000002400c07c        0x4 ./Middlewares/Third_Party/FreeRTOS/Source/timers.o
+ .bss.xTimerTaskHandle
+                0x000000002400c080        0x4 ./Middlewares/Third_Party/FreeRTOS/Source/timers.o
+ .bss.xLastTime.2
+                0x000000002400c084        0x4 ./Middlewares/Third_Party/FreeRTOS/Source/timers.o
+ .bss.ucStaticTimerQueueStorage.1
+                0x000000002400c088       0x78 ./Middlewares/Third_Party/FreeRTOS/Source/timers.o
+ .bss.xStaticTimerQueue.0
+                0x000000002400c100       0x48 ./Middlewares/Third_Party/FreeRTOS/Source/timers.o
+ .bss.ucMaxSysCallPriority
+                0x000000002400c148        0x1 ./Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.o
+ *fill*         0x000000002400c149        0x3 
+ .bss.ulMaxPRIGROUPValue
+                0x000000002400c14c        0x4 ./Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.o
+ .bss.ucHeap    0x000000002400c150     0x7800 ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o
+ .bss.xStart    0x0000000024013950        0x8 ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o
+ .bss.pxEnd     0x0000000024013958        0x4 ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o
+ .bss.xFreeBytesRemaining
+                0x000000002401395c        0x4 ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o
+ .bss.xMinimumEverFreeBytesRemaining
+                0x0000000024013960        0x4 ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o
+ .bss.xNumberOfSuccessfulAllocations
+                0x0000000024013964        0x4 ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o
+ .bss.xNumberOfSuccessfulFrees
+                0x0000000024013968        0x4 ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o
+ .bss.xBlockAllocatedBit
+                0x000000002401396c        0x4 ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o
+ .bss.tcpip_init_done
+                0x0000000024013970        0x4 ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
+ .bss.tcpip_init_done_arg
+                0x0000000024013974        0x4 ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
+ .bss.tcpip_mbox
+                0x0000000024013978        0x4 ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
+ .bss.lock_tcpip_core
+                0x000000002401397c        0x4 ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
+                0x000000002401397c                lock_tcpip_core
+ .bss.ip_data   0x0000000024013980       0x18 ./Middlewares/Third_Party/LwIP/src/core/ip.o
+                0x0000000024013980                ip_data
+ .bss.ram       0x0000000024013998        0x4 ./Middlewares/Third_Party/LwIP/src/core/mem.o
+ .bss.ram_end   0x000000002401399c        0x4 ./Middlewares/Third_Party/LwIP/src/core/mem.o
+ .bss.mem_mutex
+                0x00000000240139a0        0x4 ./Middlewares/Third_Party/LwIP/src/core/mem.o
+ .bss.lfree     0x00000000240139a4        0x4 ./Middlewares/Third_Party/LwIP/src/core/mem.o
  .bss.memp_memory_UDP_PCB_base
-                0x0000000024004c34       0x83 ./Middlewares/Third_Party/LwIP/src/core/memp.o
-                0x0000000024004c34                memp_memory_UDP_PCB_base
- *fill*         0x0000000024004cb7        0x1 
+                0x00000000240139a8       0x83 ./Middlewares/Third_Party/LwIP/src/core/memp.o
+                0x00000000240139a8                memp_memory_UDP_PCB_base
+ *fill*         0x0000000024013a2b        0x1 
  .bss.memp_tab_UDP_PCB
-                0x0000000024004cb8        0x4 ./Middlewares/Third_Party/LwIP/src/core/memp.o
+                0x0000000024013a2c        0x4 ./Middlewares/Third_Party/LwIP/src/core/memp.o
  .bss.memp_memory_TCP_PCB_base
-                0x0000000024004cbc      0x30f ./Middlewares/Third_Party/LwIP/src/core/memp.o
-                0x0000000024004cbc                memp_memory_TCP_PCB_base
- *fill*         0x0000000024004fcb        0x1 
+                0x0000000024013a30      0x30f ./Middlewares/Third_Party/LwIP/src/core/memp.o
+                0x0000000024013a30                memp_memory_TCP_PCB_base
+ *fill*         0x0000000024013d3f        0x1 
  .bss.memp_tab_TCP_PCB
-                0x0000000024004fcc        0x4 ./Middlewares/Third_Party/LwIP/src/core/memp.o
+                0x0000000024013d40        0x4 ./Middlewares/Third_Party/LwIP/src/core/memp.o
  .bss.memp_memory_TCP_PCB_LISTEN_base
-                0x0000000024004fd0       0xe3 ./Middlewares/Third_Party/LwIP/src/core/memp.o
-                0x0000000024004fd0                memp_memory_TCP_PCB_LISTEN_base
- *fill*         0x00000000240050b3        0x1 
+                0x0000000024013d44       0xe3 ./Middlewares/Third_Party/LwIP/src/core/memp.o
+                0x0000000024013d44                memp_memory_TCP_PCB_LISTEN_base
+ *fill*         0x0000000024013e27        0x1 
  .bss.memp_tab_TCP_PCB_LISTEN
-                0x00000000240050b4        0x4 ./Middlewares/Third_Party/LwIP/src/core/memp.o
+                0x0000000024013e28        0x4 ./Middlewares/Third_Party/LwIP/src/core/memp.o
  .bss.memp_memory_TCP_SEG_base
-                0x00000000240050b8      0x143 ./Middlewares/Third_Party/LwIP/src/core/memp.o
-                0x00000000240050b8                memp_memory_TCP_SEG_base
- *fill*         0x00000000240051fb        0x1 
+                0x0000000024013e2c      0x143 ./Middlewares/Third_Party/LwIP/src/core/memp.o
+                0x0000000024013e2c                memp_memory_TCP_SEG_base
+ *fill*         0x0000000024013f6f        0x1 
  .bss.memp_tab_TCP_SEG
-                0x00000000240051fc        0x4 ./Middlewares/Third_Party/LwIP/src/core/memp.o
+                0x0000000024013f70        0x4 ./Middlewares/Third_Party/LwIP/src/core/memp.o
  .bss.memp_memory_REASSDATA_base
-                0x0000000024005200       0xa3 ./Middlewares/Third_Party/LwIP/src/core/memp.o
-                0x0000000024005200                memp_memory_REASSDATA_base
- *fill*         0x00000000240052a3        0x1 
+                0x0000000024013f74       0xa3 ./Middlewares/Third_Party/LwIP/src/core/memp.o
+                0x0000000024013f74                memp_memory_REASSDATA_base
+ *fill*         0x0000000024014017        0x1 
  .bss.memp_tab_REASSDATA
-                0x00000000240052a4        0x4 ./Middlewares/Third_Party/LwIP/src/core/memp.o
+                0x0000000024014018        0x4 ./Middlewares/Third_Party/LwIP/src/core/memp.o
  .bss.memp_memory_FRAG_PBUF_base
-                0x00000000240052a8      0x16b ./Middlewares/Third_Party/LwIP/src/core/memp.o
-                0x00000000240052a8                memp_memory_FRAG_PBUF_base
- *fill*         0x0000000024005413        0x1 
+                0x000000002401401c      0x16b ./Middlewares/Third_Party/LwIP/src/core/memp.o
+                0x000000002401401c                memp_memory_FRAG_PBUF_base
+ *fill*         0x0000000024014187        0x1 
  .bss.memp_tab_FRAG_PBUF
-                0x0000000024005414        0x4 ./Middlewares/Third_Party/LwIP/src/core/memp.o
+                0x0000000024014188        0x4 ./Middlewares/Third_Party/LwIP/src/core/memp.o
+ .bss.memp_memory_NETBUF_base
+                0x000000002401418c       0x23 ./Middlewares/Third_Party/LwIP/src/core/memp.o
+                0x000000002401418c                memp_memory_NETBUF_base
+ *fill*         0x00000000240141af        0x1 
+ .bss.memp_tab_NETBUF
+                0x00000000240141b0        0x4 ./Middlewares/Third_Party/LwIP/src/core/memp.o
+ .bss.memp_memory_NETCONN_base
+                0x00000000240141b4       0xa3 ./Middlewares/Third_Party/LwIP/src/core/memp.o
+                0x00000000240141b4                memp_memory_NETCONN_base
+ *fill*         0x0000000024014257        0x1 
+ .bss.memp_tab_NETCONN
+                0x0000000024014258        0x4 ./Middlewares/Third_Party/LwIP/src/core/memp.o
+ .bss.memp_memory_TCPIP_MSG_API_base
+                0x000000002401425c       0x83 ./Middlewares/Third_Party/LwIP/src/core/memp.o
+                0x000000002401425c                memp_memory_TCPIP_MSG_API_base
+ *fill*         0x00000000240142df        0x1 
+ .bss.memp_tab_TCPIP_MSG_API
+                0x00000000240142e0        0x4 ./Middlewares/Third_Party/LwIP/src/core/memp.o
+ .bss.memp_memory_TCPIP_MSG_INPKT_base
+                0x00000000240142e4       0x83 ./Middlewares/Third_Party/LwIP/src/core/memp.o
+                0x00000000240142e4                memp_memory_TCPIP_MSG_INPKT_base
+ *fill*         0x0000000024014367        0x1 
+ .bss.memp_tab_TCPIP_MSG_INPKT
+                0x0000000024014368        0x4 ./Middlewares/Third_Party/LwIP/src/core/memp.o
  .bss.memp_memory_SYS_TIMEOUT_base
-                0x0000000024005418       0x33 ./Middlewares/Third_Party/LwIP/src/core/memp.o
-                0x0000000024005418                memp_memory_SYS_TIMEOUT_base
- *fill*         0x000000002400544b        0x1 
+                0x000000002401436c       0x33 ./Middlewares/Third_Party/LwIP/src/core/memp.o
+                0x000000002401436c                memp_memory_SYS_TIMEOUT_base
+ *fill*         0x000000002401439f        0x1 
  .bss.memp_tab_SYS_TIMEOUT
-                0x000000002400544c        0x4 ./Middlewares/Third_Party/LwIP/src/core/memp.o
+                0x00000000240143a0        0x4 ./Middlewares/Third_Party/LwIP/src/core/memp.o
  .bss.memp_memory_PBUF_base
-                0x0000000024005450      0x103 ./Middlewares/Third_Party/LwIP/src/core/memp.o
-                0x0000000024005450                memp_memory_PBUF_base
- *fill*         0x0000000024005553        0x1 
+                0x00000000240143a4      0x103 ./Middlewares/Third_Party/LwIP/src/core/memp.o
+                0x00000000240143a4                memp_memory_PBUF_base
+ *fill*         0x00000000240144a7        0x1 
  .bss.memp_tab_PBUF
-                0x0000000024005554        0x4 ./Middlewares/Third_Party/LwIP/src/core/memp.o
+                0x00000000240144a8        0x4 ./Middlewares/Third_Party/LwIP/src/core/memp.o
  .bss.memp_memory_PBUF_POOL_base
-                0x0000000024005558     0x2603 ./Middlewares/Third_Party/LwIP/src/core/memp.o
-                0x0000000024005558                memp_memory_PBUF_POOL_base
- *fill*         0x0000000024007b5b        0x1 
+                0x00000000240144ac     0x5fc3 ./Middlewares/Third_Party/LwIP/src/core/memp.o
+                0x00000000240144ac                memp_memory_PBUF_POOL_base
+ *fill*         0x000000002401a46f        0x1 
  .bss.memp_tab_PBUF_POOL
-                0x0000000024007b5c        0x4 ./Middlewares/Third_Party/LwIP/src/core/memp.o
+                0x000000002401a470        0x4 ./Middlewares/Third_Party/LwIP/src/core/memp.o
  .bss.netif_list
-                0x0000000024007b60        0x4 ./Middlewares/Third_Party/LwIP/src/core/netif.o
-                0x0000000024007b60                netif_list
+                0x000000002401a474        0x4 ./Middlewares/Third_Party/LwIP/src/core/netif.o
+                0x000000002401a474                netif_list
  .bss.netif_default
-                0x0000000024007b64        0x4 ./Middlewares/Third_Party/LwIP/src/core/netif.o
-                0x0000000024007b64                netif_default
+                0x000000002401a478        0x4 ./Middlewares/Third_Party/LwIP/src/core/netif.o
+                0x000000002401a478                netif_default
  .bss.netif_num
-                0x0000000024007b68        0x1 ./Middlewares/Third_Party/LwIP/src/core/netif.o
+                0x000000002401a47c        0x1 ./Middlewares/Third_Party/LwIP/src/core/netif.o
  .bss.pbuf_free_ooseq_pending
-                0x0000000024007b69        0x1 ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
-                0x0000000024007b69                pbuf_free_ooseq_pending
- *fill*         0x0000000024007b6a        0x2 
+                0x000000002401a47d        0x1 ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
+                0x000000002401a47d                pbuf_free_ooseq_pending
+ *fill*         0x000000002401a47e        0x2 
  .bss.tcp_ticks
-                0x0000000024007b6c        0x4 ./Middlewares/Third_Party/LwIP/src/core/tcp.o
-                0x0000000024007b6c                tcp_ticks
+                0x000000002401a480        0x4 ./Middlewares/Third_Party/LwIP/src/core/tcp.o
+                0x000000002401a480                tcp_ticks
  .bss.tcp_bound_pcbs
-                0x0000000024007b70        0x4 ./Middlewares/Third_Party/LwIP/src/core/tcp.o
-                0x0000000024007b70                tcp_bound_pcbs
+                0x000000002401a484        0x4 ./Middlewares/Third_Party/LwIP/src/core/tcp.o
+                0x000000002401a484                tcp_bound_pcbs
  .bss.tcp_listen_pcbs
-                0x0000000024007b74        0x4 ./Middlewares/Third_Party/LwIP/src/core/tcp.o
-                0x0000000024007b74                tcp_listen_pcbs
+                0x000000002401a488        0x4 ./Middlewares/Third_Party/LwIP/src/core/tcp.o
+                0x000000002401a488                tcp_listen_pcbs
  .bss.tcp_active_pcbs
-                0x0000000024007b78        0x4 ./Middlewares/Third_Party/LwIP/src/core/tcp.o
-                0x0000000024007b78                tcp_active_pcbs
+                0x000000002401a48c        0x4 ./Middlewares/Third_Party/LwIP/src/core/tcp.o
+                0x000000002401a48c                tcp_active_pcbs
  .bss.tcp_tw_pcbs
-                0x0000000024007b7c        0x4 ./Middlewares/Third_Party/LwIP/src/core/tcp.o
-                0x0000000024007b7c                tcp_tw_pcbs
+                0x000000002401a490        0x4 ./Middlewares/Third_Party/LwIP/src/core/tcp.o
+                0x000000002401a490                tcp_tw_pcbs
  .bss.tcp_active_pcbs_changed
-                0x0000000024007b80        0x1 ./Middlewares/Third_Party/LwIP/src/core/tcp.o
-                0x0000000024007b80                tcp_active_pcbs_changed
+                0x000000002401a494        0x1 ./Middlewares/Third_Party/LwIP/src/core/tcp.o
+                0x000000002401a494                tcp_active_pcbs_changed
  .bss.tcp_timer
-                0x0000000024007b81        0x1 ./Middlewares/Third_Party/LwIP/src/core/tcp.o
+                0x000000002401a495        0x1 ./Middlewares/Third_Party/LwIP/src/core/tcp.o
  .bss.tcp_timer_ctr
-                0x0000000024007b82        0x1 ./Middlewares/Third_Party/LwIP/src/core/tcp.o
- *fill*         0x0000000024007b83        0x1 
- .bss.inseg     0x0000000024007b84       0x14 ./Middlewares/Third_Party/LwIP/src/core/tcp_in.o
- .bss.tcphdr    0x0000000024007b98        0x4 ./Middlewares/Third_Party/LwIP/src/core/tcp_in.o
+                0x000000002401a496        0x1 ./Middlewares/Third_Party/LwIP/src/core/tcp.o
+ *fill*         0x000000002401a497        0x1 
+ .bss.inseg     0x000000002401a498       0x14 ./Middlewares/Third_Party/LwIP/src/core/tcp_in.o
+ .bss.tcphdr    0x000000002401a4ac        0x4 ./Middlewares/Third_Party/LwIP/src/core/tcp_in.o
  .bss.tcphdr_optlen
-                0x0000000024007b9c        0x2 ./Middlewares/Third_Party/LwIP/src/core/tcp_in.o
+                0x000000002401a4b0        0x2 ./Middlewares/Third_Party/LwIP/src/core/tcp_in.o
  .bss.tcphdr_opt1len
-                0x0000000024007b9e        0x2 ./Middlewares/Third_Party/LwIP/src/core/tcp_in.o
+                0x000000002401a4b2        0x2 ./Middlewares/Third_Party/LwIP/src/core/tcp_in.o
  .bss.tcphdr_opt2
-                0x0000000024007ba0        0x4 ./Middlewares/Third_Party/LwIP/src/core/tcp_in.o
+                0x000000002401a4b4        0x4 ./Middlewares/Third_Party/LwIP/src/core/tcp_in.o
  .bss.tcp_optidx
-                0x0000000024007ba4        0x2 ./Middlewares/Third_Party/LwIP/src/core/tcp_in.o
- *fill*         0x0000000024007ba6        0x2 
- .bss.seqno     0x0000000024007ba8        0x4 ./Middlewares/Third_Party/LwIP/src/core/tcp_in.o
- .bss.ackno     0x0000000024007bac        0x4 ./Middlewares/Third_Party/LwIP/src/core/tcp_in.o
+                0x000000002401a4b8        0x2 ./Middlewares/Third_Party/LwIP/src/core/tcp_in.o
+ *fill*         0x000000002401a4ba        0x2 
+ .bss.seqno     0x000000002401a4bc        0x4 ./Middlewares/Third_Party/LwIP/src/core/tcp_in.o
+ .bss.ackno     0x000000002401a4c0        0x4 ./Middlewares/Third_Party/LwIP/src/core/tcp_in.o
  .bss.recv_acked
-                0x0000000024007bb0        0x2 ./Middlewares/Third_Party/LwIP/src/core/tcp_in.o
- .bss.tcplen    0x0000000024007bb2        0x2 ./Middlewares/Third_Party/LwIP/src/core/tcp_in.o
- .bss.flags     0x0000000024007bb4        0x1 ./Middlewares/Third_Party/LwIP/src/core/tcp_in.o
+                0x000000002401a4c4        0x2 ./Middlewares/Third_Party/LwIP/src/core/tcp_in.o
+ .bss.tcplen    0x000000002401a4c6        0x2 ./Middlewares/Third_Party/LwIP/src/core/tcp_in.o
+ .bss.flags     0x000000002401a4c8        0x1 ./Middlewares/Third_Party/LwIP/src/core/tcp_in.o
  .bss.recv_flags
-                0x0000000024007bb5        0x1 ./Middlewares/Third_Party/LwIP/src/core/tcp_in.o
- *fill*         0x0000000024007bb6        0x2 
+                0x000000002401a4c9        0x1 ./Middlewares/Third_Party/LwIP/src/core/tcp_in.o
+ *fill*         0x000000002401a4ca        0x2 
  .bss.recv_data
-                0x0000000024007bb8        0x4 ./Middlewares/Third_Party/LwIP/src/core/tcp_in.o
+                0x000000002401a4cc        0x4 ./Middlewares/Third_Party/LwIP/src/core/tcp_in.o
  .bss.tcp_input_pcb
-                0x0000000024007bbc        0x4 ./Middlewares/Third_Party/LwIP/src/core/tcp_in.o
-                0x0000000024007bbc                tcp_input_pcb
+                0x000000002401a4d0        0x4 ./Middlewares/Third_Party/LwIP/src/core/tcp_in.o
+                0x000000002401a4d0                tcp_input_pcb
  .bss.next_timeout
-                0x0000000024007bc0        0x4 ./Middlewares/Third_Party/LwIP/src/core/timeouts.o
+                0x000000002401a4d4        0x4 ./Middlewares/Third_Party/LwIP/src/core/timeouts.o
  .bss.current_timeout_due_time
-                0x0000000024007bc4        0x4 ./Middlewares/Third_Party/LwIP/src/core/timeouts.o
+                0x000000002401a4d8        0x4 ./Middlewares/Third_Party/LwIP/src/core/timeouts.o
  .bss.tcpip_tcp_timer_active
-                0x0000000024007bc8        0x4 ./Middlewares/Third_Party/LwIP/src/core/timeouts.o
- .bss.udp_pcbs  0x0000000024007bcc        0x4 ./Middlewares/Third_Party/LwIP/src/core/udp.o
-                0x0000000024007bcc                udp_pcbs
+                0x000000002401a4dc        0x4 ./Middlewares/Third_Party/LwIP/src/core/timeouts.o
+ .bss.udp_pcbs  0x000000002401a4e0        0x4 ./Middlewares/Third_Party/LwIP/src/core/udp.o
+                0x000000002401a4e0                udp_pcbs
  .bss.arp_table
-                0x0000000024007bd0       0xf0 ./Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.o
+                0x000000002401a4e4       0xf0 ./Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.o
  .bss.etharp_cached_entry
-                0x0000000024007cc0        0x1 ./Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.o
- *fill*         0x0000000024007cc1        0x1 
- .bss.ip_id     0x0000000024007cc2        0x2 ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.o
+                0x000000002401a5d4        0x1 ./Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.o
+ *fill*         0x000000002401a5d5        0x1 
+ .bss.ip_id     0x000000002401a5d6        0x2 ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.o
  .bss.reassdatagrams
-                0x0000000024007cc4        0x4 ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.o
+                0x000000002401a5d8        0x4 ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.o
  .bss.ip_reass_pbufcount
-                0x0000000024007cc8        0x2 ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.o
- *fill*         0x0000000024007cca        0x2 
- .bss.__sf      0x0000000024007ccc      0x138 C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-findfp.o)
-                0x0000000024007ccc                __sf
+                0x000000002401a5dc        0x2 ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.o
+ *fill*         0x000000002401a5de        0x2 
+ .bss.errno     0x000000002401a5e0        0x4 ./Middlewares/Third_Party/LwIP/system/OS/sys_arch.o
+                0x000000002401a5e0                errno
+ .bss.lwip_sys_mutex
+                0x000000002401a5e4        0x4 ./Middlewares/Third_Party/LwIP/system/OS/sys_arch.o
+                0x000000002401a5e4                lwip_sys_mutex
+ .bss.__sf      0x000000002401a5e8      0x138 C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-findfp.o)
+                0x000000002401a5e8                __sf
  .bss.__stdio_exit_handler
-                0x0000000024007e04        0x4 C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-findfp.o)
-                0x0000000024007e04                __stdio_exit_handler
- .bss.errno     0x0000000024007e08        0x4 C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-reent.o)
-                0x0000000024007e08                errno
+                0x000000002401a720        0x4 C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-findfp.o)
+                0x000000002401a720                __stdio_exit_handler
  .bss.__lock___malloc_recursive_mutex
-                0x0000000024007e0c        0x1 C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-lock.o)
-                0x0000000024007e0c                __lock___malloc_recursive_mutex
+                0x000000002401a724        0x1 C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-lock.o)
+                0x000000002401a724                __lock___malloc_recursive_mutex
  .bss.__lock___sfp_recursive_mutex
-                0x0000000024007e0d        0x1 C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-lock.o)
-                0x0000000024007e0d                __lock___sfp_recursive_mutex
- *fill*         0x0000000024007e0e        0x2 
+                0x000000002401a725        0x1 C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-lock.o)
+                0x000000002401a725                __lock___sfp_recursive_mutex
+ *fill*         0x000000002401a726        0x2 
  .bss.__malloc_free_list
-                0x0000000024007e10        0x4 C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-mallocr.o)
-                0x0000000024007e10                __malloc_free_list
+                0x000000002401a728        0x4 C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-mallocr.o)
+                0x000000002401a728                __malloc_free_list
  .bss.__malloc_sbrk_start
-                0x0000000024007e14        0x4 C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-mallocr.o)
-                0x0000000024007e14                __malloc_sbrk_start
+                0x000000002401a72c        0x4 C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-mallocr.o)
+                0x000000002401a72c                __malloc_sbrk_start
  *(COMMON)
-                0x0000000024007e18                . = ALIGN (0x4)
-                0x0000000024007e18                _ebss = .
-                0x0000000024007e18                __bss_end__ = _ebss
+                0x000000002401a730                . = ALIGN (0x4)
+                0x000000002401a730                _ebss = .
+                0x000000002401a730                __bss_end__ = _ebss
 
 ._user_heap_stack
-                0x0000000024007e18      0x600 load address 0x0000000008014f34
-                0x0000000024007e18                . = ALIGN (0x8)
+                0x000000002401a730     0x6000 load address 0x0000000008026f9c
+                0x000000002401a730                . = ALIGN (0x8)
                 [!provide]                        PROVIDE (end = .)
-                0x0000000024007e18                PROVIDE (_end = .)
-                0x0000000024008018                . = (. + _Min_Heap_Size)
- *fill*         0x0000000024007e18      0x200 
-                0x0000000024008418                . = (. + _Min_Stack_Size)
- *fill*         0x0000000024008018      0x400 
-                0x0000000024008418                . = ALIGN (0x8)
+                0x000000002401a730                PROVIDE (_end = .)
+                0x000000002401c730                . = (. + _Min_Heap_Size)
+ *fill*         0x000000002401a730     0x2000 
+                0x0000000024020730                . = (. + _Min_Stack_Size)
+ *fill*         0x000000002401c730     0x4000 
+                0x0000000024020730                . = ALIGN (0x8)
 
 .lwip_sec       0x0000000030000000      0x160
                 0x0000000030000000                . = ABSOLUTE (0x30000000)
@@ -25624,166 +34834,238 @@ LOAD C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.ext
  .ARM.attributes
                 0x000000000000001e       0x32 C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+dp/hard/crtbegin.o
  .ARM.attributes
-                0x0000000000000050       0x32 ./Core/Src/main.o
+                0x0000000000000050       0x32 ./Core/Src/freertos.o
  .ARM.attributes
-                0x0000000000000082       0x32 ./Core/Src/stm32h7xx_hal_msp.o
+                0x0000000000000082       0x32 ./Core/Src/main.o
  .ARM.attributes
-                0x00000000000000b4       0x32 ./Core/Src/stm32h7xx_it.o
+                0x00000000000000b4       0x32 ./Core/Src/stm32h7xx_hal_msp.o
  .ARM.attributes
-                0x00000000000000e6       0x32 ./Core/Src/syscalls.o
+                0x00000000000000e6       0x32 ./Core/Src/stm32h7xx_hal_timebase_tim.o
  .ARM.attributes
-                0x0000000000000118       0x32 ./Core/Src/sysmem.o
+                0x0000000000000118       0x32 ./Core/Src/stm32h7xx_it.o
  .ARM.attributes
-                0x000000000000014a       0x32 ./Core/Src/system_stm32h7xx.o
+                0x000000000000014a       0x32 ./Core/Src/syscalls.o
  .ARM.attributes
-                0x000000000000017c       0x21 ./Core/Startup/startup_stm32h723vghx.o
+                0x000000000000017c       0x32 ./Core/Src/sysmem.o
  .ARM.attributes
-                0x000000000000019d       0x32 ./Drivers/BSP/Components/lan8742/lan8742.o
+                0x00000000000001ae       0x32 ./Core/Src/system_stm32h7xx.o
  .ARM.attributes
-                0x00000000000001cf       0x32 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.o
+                0x00000000000001e0       0x21 ./Core/Startup/startup_stm32h723vghx.o
  .ARM.attributes
-                0x0000000000000201       0x32 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.o
+                0x0000000000000201       0x32 ./Drivers/BSP/Components/lan8742/lan8742.o
  .ARM.attributes
-                0x0000000000000233       0x32 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o
+                0x0000000000000233       0x32 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.o
  .ARM.attributes
-                0x0000000000000265       0x32 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.o
+                0x0000000000000265       0x32 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.o
  .ARM.attributes
-                0x0000000000000297       0x32 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.o
+                0x0000000000000297       0x32 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.o
  .ARM.attributes
-                0x00000000000002c9       0x32 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.o
+                0x00000000000002c9       0x32 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o
  .ARM.attributes
-                0x00000000000002fb       0x32 ./LWFTP/lwftp.o
+                0x00000000000002fb       0x32 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
  .ARM.attributes
-                0x000000000000032d       0x32 ./LWIP/App/lwip.o
+                0x000000000000032d       0x32 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.o
  .ARM.attributes
-                0x000000000000035f       0x32 ./LWIP/Target/ethernetif.o
+                0x000000000000035f       0x32 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.o
  .ARM.attributes
-                0x0000000000000391       0x32 ./Middlewares/Third_Party/LwIP/src/api/err.o
+                0x0000000000000391       0x32 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.o
  .ARM.attributes
-                0x00000000000003c3       0x32 ./Middlewares/Third_Party/LwIP/src/core/def.o
+                0x00000000000003c3       0x32 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.o
  .ARM.attributes
-                0x00000000000003f5       0x32 ./Middlewares/Third_Party/LwIP/src/core/inet_chksum.o
+                0x00000000000003f5       0x32 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.o
  .ARM.attributes
-                0x0000000000000427       0x32 ./Middlewares/Third_Party/LwIP/src/core/init.o
+                0x0000000000000427       0x32 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.o
  .ARM.attributes
-                0x0000000000000459       0x32 ./Middlewares/Third_Party/LwIP/src/core/ip.o
+                0x0000000000000459       0x32 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.o
  .ARM.attributes
-                0x000000000000048b       0x32 ./Middlewares/Third_Party/LwIP/src/core/mem.o
+                0x000000000000048b       0x32 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.o
  .ARM.attributes
-                0x00000000000004bd       0x32 ./Middlewares/Third_Party/LwIP/src/core/memp.o
+                0x00000000000004bd       0x32 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.o
  .ARM.attributes
-                0x00000000000004ef       0x32 ./Middlewares/Third_Party/LwIP/src/core/netif.o
+                0x00000000000004ef       0x32 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.o
  .ARM.attributes
-                0x0000000000000521       0x32 ./Middlewares/Third_Party/LwIP/src/core/pbuf.o
+                0x0000000000000521       0x32 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.o
  .ARM.attributes
-                0x0000000000000553       0x32 ./Middlewares/Third_Party/LwIP/src/core/tcp.o
+                0x0000000000000553       0x32 ./FATFS/App/fatfs.o
  .ARM.attributes
-                0x0000000000000585       0x32 ./Middlewares/Third_Party/LwIP/src/core/tcp_in.o
+                0x0000000000000585       0x32 ./FATFS/Target/bsp_driver_sd.o
  .ARM.attributes
-                0x00000000000005b7       0x32 ./Middlewares/Third_Party/LwIP/src/core/tcp_out.o
+                0x00000000000005b7       0x32 ./FATFS/Target/fatfs_platform.o
  .ARM.attributes
-                0x00000000000005e9       0x32 ./Middlewares/Third_Party/LwIP/src/core/timeouts.o
+                0x00000000000005e9       0x32 ./FATFS/Target/sd_diskio.o
  .ARM.attributes
-                0x000000000000061b       0x32 ./Middlewares/Third_Party/LwIP/src/core/udp.o
+                0x000000000000061b       0x32 ./LWFTPC/lwftpc.o
  .ARM.attributes
-                0x000000000000064d       0x32 ./Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.o
+                0x000000000000064d       0x32 ./LWIP/App/lwip.o
  .ARM.attributes
-                0x000000000000067f       0x32 ./Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.o
+                0x000000000000067f       0x32 ./LWIP/Target/ethernetif.o
  .ARM.attributes
-                0x00000000000006b1       0x32 ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.o
+                0x00000000000006b1       0x32 ./Middlewares/Third_Party/FatFs/src/ff_gen_drv.o
  .ARM.attributes
-                0x00000000000006e3       0x32 ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.o
+                0x00000000000006e3       0x32 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o
  .ARM.attributes
-                0x0000000000000715       0x32 ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.o
+                0x0000000000000715       0x32 ./Middlewares/Third_Party/FreeRTOS/Source/list.o
  .ARM.attributes
-                0x0000000000000747       0x32 ./Middlewares/Third_Party/LwIP/src/netif/ethernet.o
+                0x0000000000000747       0x32 ./Middlewares/Third_Party/FreeRTOS/Source/queue.o
  .ARM.attributes
-                0x0000000000000779       0x32 C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-rand.o)
+                0x0000000000000779       0x32 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o
  .ARM.attributes
-                0x00000000000007ab       0x32 C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-strtoul.o)
+                0x00000000000007ab       0x32 ./Middlewares/Third_Party/FreeRTOS/Source/timers.o
  .ARM.attributes
-                0x00000000000007dd       0x32 C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-ctype_.o)
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+ .ARM.attributes
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+ .ARM.attributes
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+OUTPUT(TBD_TaxiBoard.elf elf32-littlearm)
 LOAD linker stubs
 LOAD C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc.a
 LOAD C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libm.a
@@ -25792,8 +35074,10 @@ LOAD C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.ext
 .comment        0x0000000000000000       0x43
  .comment       0x0000000000000000       0x43 C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+dp/hard/crtbegin.o
                                          0x44 (size before relaxing)
+ .comment       0x0000000000000043       0x44 ./Core/Src/freertos.o
  .comment       0x0000000000000043       0x44 ./Core/Src/main.o
  .comment       0x0000000000000043       0x44 ./Core/Src/stm32h7xx_hal_msp.o
+ .comment       0x0000000000000043       0x44 ./Core/Src/stm32h7xx_hal_timebase_tim.o
  .comment       0x0000000000000043       0x44 ./Core/Src/stm32h7xx_it.o
  .comment       0x0000000000000043       0x44 ./Core/Src/syscalls.o
  .comment       0x0000000000000043       0x44 ./Core/Src/sysmem.o
@@ -25801,14 +35085,39 @@ LOAD C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.ext
  .comment       0x0000000000000043       0x44 ./Drivers/BSP/Components/lan8742/lan8742.o
  .comment       0x0000000000000043       0x44 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.o
  .comment       0x0000000000000043       0x44 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.o
+ .comment       0x0000000000000043       0x44 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.o
  .comment       0x0000000000000043       0x44 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o
+ .comment       0x0000000000000043       0x44 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
  .comment       0x0000000000000043       0x44 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.o
+ .comment       0x0000000000000043       0x44 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.o
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- .comment       0x0000000000000043       0x44 ./LWFTP/lwftp.o
+ .comment       0x0000000000000043       0x44 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.o
+ .comment       0x0000000000000043       0x44 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.o
+ .comment       0x0000000000000043       0x44 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.o
+ .comment       0x0000000000000043       0x44 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.o
+ .comment       0x0000000000000043       0x44 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.o
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+ .comment       0x0000000000000043       0x44 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.o
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+ .comment       0x0000000000000043       0x44 ./LWFTPC/lwftpc.o
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- .comment       0x0000000000000043       0x44 ./Middlewares/Third_Party/LwIP/src/api/err.o
+ .comment       0x0000000000000043       0x44 ./Middlewares/Third_Party/FatFs/src/ff_gen_drv.o
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+ .comment       0x0000000000000043       0x44 ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o
+ .comment       0x0000000000000043       0x44 ./Middlewares/Third_Party/LwIP/src/api/api_lib.o
+ .comment       0x0000000000000043       0x44 ./Middlewares/Third_Party/LwIP/src/api/api_msg.o
+ .comment       0x0000000000000043       0x44 ./Middlewares/Third_Party/LwIP/src/api/netbuf.o
+ .comment       0x0000000000000043       0x44 ./Middlewares/Third_Party/LwIP/src/api/tcpip.o
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  .comment       0x0000000000000043       0x44 ./Middlewares/Third_Party/LwIP/src/core/init.o
@@ -25828,628 +35137,991 @@ LOAD C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.ext
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  .comment       0x0000000000000043       0x44 ./Middlewares/Third_Party/LwIP/src/netif/ethernet.o
+ .comment       0x0000000000000043       0x44 ./Middlewares/Third_Party/LwIP/system/OS/sys_arch.o
 
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+ .debug_frame   0x000000000000d7a0       0x28 C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-memcpy-stub.o)
+ .debug_frame   0x000000000000d7c8       0x40 C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-assert.o)
+ .debug_frame   0x000000000000d808       0x38 C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-freer.o)
+ .debug_frame   0x000000000000d840       0x30 C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-malloc.o)
+ .debug_frame   0x000000000000d870       0x50 C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-mallocr.o)
+ .debug_frame   0x000000000000d8c0       0x30 C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-mlock.o)
+ .debug_frame   0x000000000000d8f0       0x90 C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-nano-svfprintf.o)
+ .debug_frame   0x000000000000d980       0xa8 C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-nano-vfprintf.o)
+ .debug_frame   0x000000000000da28       0x60 C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-nano-vfprintf_i.o)
+ .debug_frame   0x000000000000da88       0x5c C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-fflush.o)
+ .debug_frame   0x000000000000dae4       0x64 C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-fprintf.o)
+ .debug_frame   0x000000000000db48       0x58 C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-makebuf.o)
+ .debug_frame   0x000000000000dba0       0x3c C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-putc.o)
+ .debug_frame   0x000000000000dbdc       0x2c C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-fstatr.o)
+ .debug_frame   0x000000000000dc08       0x2c C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-isattyr.o)
+ .debug_frame   0x000000000000dc34       0x2c C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-sbrkr.o)
+ .debug_frame   0x000000000000dc60       0x28 C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-abort.o)
+ .debug_frame   0x000000000000dc88       0x3c C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-reallocr.o)
+ .debug_frame   0x000000000000dcc4       0xcc C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-signal.o)
+ .debug_frame   0x000000000000dd90       0x3c C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-signalr.o)
+ .debug_frame   0x000000000000ddcc       0x20 C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-msizer.o)
+ .debug_frame   0x000000000000ddec       0x2c C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+dp/hard\libgcc.a(_aeabi_uldivmod.o)
+ .debug_frame   0x000000000000de18       0x34 C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+dp/hard\libgcc.a(_udivmoddi4.o)
 
 .debug_line_str
-                0x0000000000000000       0x4a
+                0x0000000000000000       0x4e
  .debug_line_str
-                0x0000000000000000       0x4a ./Core/Startup/startup_stm32h723vghx.o
-                                         0x62 (size before relaxing)
+                0x0000000000000000       0x4e ./Core/Startup/startup_stm32h723vghx.o
+                                         0x66 (size before relaxing)
diff --git a/Debug/lwip_test.list b/Debug/lwip_test.list
deleted file mode 100644
index 355ef68..0000000
--- a/Debug/lwip_test.list
+++ /dev/null
@@ -1,44508 +0,0 @@
-
-lwip_test.elf:     file format elf32-littlearm
-
-Sections:
-Idx Name          Size      VMA       LMA       File off  Algn
-  0 .isr_vector   000002cc  08000000  08000000  00010000  2**0
-                  CONTENTS, ALLOC, LOAD, READONLY, DATA
-  1 .text         000112d4  080002d0  080002d0  000102d0  2**4
-                  CONTENTS, ALLOC, LOAD, READONLY, CODE
-  2 .rodata       000039e4  080115a4  080115a4  000215a4  2**2
-                  CONTENTS, ALLOC, LOAD, READONLY, DATA
-  3 .init_array   00000004  08014f88  08014f88  00024f88  2**2
-                  CONTENTS, ALLOC, LOAD, DATA
-  4 .fini_array   00000004  08014f8c  08014f8c  00024f8c  2**2
-                  CONTENTS, ALLOC, LOAD, DATA
-  5 .data         000000d0  24000000  08014f90  00030000  2**2
-                  CONTENTS, ALLOC, LOAD, DATA
-  6 .bss          00007d48  240000d0  08015060  000300d0  2**2
-                  ALLOC
-  7 ._user_heap_stack 00000600  24007e18  08015060  00037e18  2**0
-                  ALLOC
-  8 .lwip_sec     00000160  30000000  30000000  00040000  2**2
-                  ALLOC
-  9 .ARM.attributes 0000002e  00000000  00000000  000300d0  2**0
-                  CONTENTS, READONLY
- 10 .comment      00000043  00000000  00000000  000300fe  2**0
-                  CONTENTS, READONLY
- 11 .debug_info   0001f0ff  00000000  00000000  00030141  2**0
-                  CONTENTS, READONLY, DEBUGGING, OCTETS
- 12 .debug_abbrev 000054e0  00000000  00000000  0004f240  2**0
-                  CONTENTS, READONLY, DEBUGGING, OCTETS
- 13 .debug_aranges 00001508  00000000  00000000  00054720  2**3
-                  CONTENTS, READONLY, DEBUGGING, OCTETS
- 14 .debug_rnglists 00001094  00000000  00000000  00055c28  2**0
-                  CONTENTS, READONLY, DEBUGGING, OCTETS
- 15 .debug_macro  0003e829  00000000  00000000  00056cbc  2**0
-                  CONTENTS, READONLY, DEBUGGING, OCTETS
- 16 .debug_line   00026379  00000000  00000000  000954e5  2**0
-                  CONTENTS, READONLY, DEBUGGING, OCTETS
- 17 .debug_str    00150dcb  00000000  00000000  000bb85e  2**0
-                  CONTENTS, READONLY, DEBUGGING, OCTETS
- 18 .debug_frame  00005dfc  00000000  00000000  0020c62c  2**2
-                  CONTENTS, READONLY, DEBUGGING, OCTETS
- 19 .debug_line_str 0000004a  00000000  00000000  00212428  2**0
-                  CONTENTS, READONLY, DEBUGGING, OCTETS
-
-Disassembly of section .text:
-
-080002d0 <__do_global_dtors_aux>:
- 80002d0:	b510      	push	{r4, lr}
- 80002d2:	4c05      	ldr	r4, [pc, #20]	; (80002e8 <__do_global_dtors_aux+0x18>)
- 80002d4:	7823      	ldrb	r3, [r4, #0]
- 80002d6:	b933      	cbnz	r3, 80002e6 <__do_global_dtors_aux+0x16>
- 80002d8:	4b04      	ldr	r3, [pc, #16]	; (80002ec <__do_global_dtors_aux+0x1c>)
- 80002da:	b113      	cbz	r3, 80002e2 <__do_global_dtors_aux+0x12>
- 80002dc:	4804      	ldr	r0, [pc, #16]	; (80002f0 <__do_global_dtors_aux+0x20>)
- 80002de:	f3af 8000 	nop.w
- 80002e2:	2301      	movs	r3, #1
- 80002e4:	7023      	strb	r3, [r4, #0]
- 80002e6:	bd10      	pop	{r4, pc}
- 80002e8:	240000d0 	.word	0x240000d0
- 80002ec:	00000000 	.word	0x00000000
- 80002f0:	0801158c 	.word	0x0801158c
-
-080002f4 <frame_dummy>:
- 80002f4:	b508      	push	{r3, lr}
- 80002f6:	4b03      	ldr	r3, [pc, #12]	; (8000304 <frame_dummy+0x10>)
- 80002f8:	b11b      	cbz	r3, 8000302 <frame_dummy+0xe>
- 80002fa:	4903      	ldr	r1, [pc, #12]	; (8000308 <frame_dummy+0x14>)
- 80002fc:	4803      	ldr	r0, [pc, #12]	; (800030c <frame_dummy+0x18>)
- 80002fe:	f3af 8000 	nop.w
- 8000302:	bd08      	pop	{r3, pc}
- 8000304:	00000000 	.word	0x00000000
- 8000308:	240000d4 	.word	0x240000d4
- 800030c:	0801158c 	.word	0x0801158c
-
-08000310 <memchr>:
- 8000310:	f001 01ff 	and.w	r1, r1, #255	; 0xff
- 8000314:	2a10      	cmp	r2, #16
- 8000316:	db2b      	blt.n	8000370 <memchr+0x60>
- 8000318:	f010 0f07 	tst.w	r0, #7
- 800031c:	d008      	beq.n	8000330 <memchr+0x20>
- 800031e:	f810 3b01 	ldrb.w	r3, [r0], #1
- 8000322:	3a01      	subs	r2, #1
- 8000324:	428b      	cmp	r3, r1
- 8000326:	d02d      	beq.n	8000384 <memchr+0x74>
- 8000328:	f010 0f07 	tst.w	r0, #7
- 800032c:	b342      	cbz	r2, 8000380 <memchr+0x70>
- 800032e:	d1f6      	bne.n	800031e <memchr+0xe>
- 8000330:	b4f0      	push	{r4, r5, r6, r7}
- 8000332:	ea41 2101 	orr.w	r1, r1, r1, lsl #8
- 8000336:	ea41 4101 	orr.w	r1, r1, r1, lsl #16
- 800033a:	f022 0407 	bic.w	r4, r2, #7
- 800033e:	f07f 0700 	mvns.w	r7, #0
- 8000342:	2300      	movs	r3, #0
- 8000344:	e8f0 5602 	ldrd	r5, r6, [r0], #8
- 8000348:	3c08      	subs	r4, #8
- 800034a:	ea85 0501 	eor.w	r5, r5, r1
- 800034e:	ea86 0601 	eor.w	r6, r6, r1
- 8000352:	fa85 f547 	uadd8	r5, r5, r7
- 8000356:	faa3 f587 	sel	r5, r3, r7
- 800035a:	fa86 f647 	uadd8	r6, r6, r7
- 800035e:	faa5 f687 	sel	r6, r5, r7
- 8000362:	b98e      	cbnz	r6, 8000388 <memchr+0x78>
- 8000364:	d1ee      	bne.n	8000344 <memchr+0x34>
- 8000366:	bcf0      	pop	{r4, r5, r6, r7}
- 8000368:	f001 01ff 	and.w	r1, r1, #255	; 0xff
- 800036c:	f002 0207 	and.w	r2, r2, #7
- 8000370:	b132      	cbz	r2, 8000380 <memchr+0x70>
- 8000372:	f810 3b01 	ldrb.w	r3, [r0], #1
- 8000376:	3a01      	subs	r2, #1
- 8000378:	ea83 0301 	eor.w	r3, r3, r1
- 800037c:	b113      	cbz	r3, 8000384 <memchr+0x74>
- 800037e:	d1f8      	bne.n	8000372 <memchr+0x62>
- 8000380:	2000      	movs	r0, #0
- 8000382:	4770      	bx	lr
- 8000384:	3801      	subs	r0, #1
- 8000386:	4770      	bx	lr
- 8000388:	2d00      	cmp	r5, #0
- 800038a:	bf06      	itte	eq
- 800038c:	4635      	moveq	r5, r6
- 800038e:	3803      	subeq	r0, #3
- 8000390:	3807      	subne	r0, #7
- 8000392:	f015 0f01 	tst.w	r5, #1
- 8000396:	d107      	bne.n	80003a8 <memchr+0x98>
- 8000398:	3001      	adds	r0, #1
- 800039a:	f415 7f80 	tst.w	r5, #256	; 0x100
- 800039e:	bf02      	ittt	eq
- 80003a0:	3001      	addeq	r0, #1
- 80003a2:	f415 3fc0 	tsteq.w	r5, #98304	; 0x18000
- 80003a6:	3001      	addeq	r0, #1
- 80003a8:	bcf0      	pop	{r4, r5, r6, r7}
- 80003aa:	3801      	subs	r0, #1
- 80003ac:	4770      	bx	lr
- 80003ae:	bf00      	nop
-
-080003b0 <strlen>:
- 80003b0:	4603      	mov	r3, r0
- 80003b2:	f813 2b01 	ldrb.w	r2, [r3], #1
- 80003b6:	2a00      	cmp	r2, #0
- 80003b8:	d1fb      	bne.n	80003b2 <strlen+0x2>
- 80003ba:	1a18      	subs	r0, r3, r0
- 80003bc:	3801      	subs	r0, #1
- 80003be:	4770      	bx	lr
-
-080003c0 <ITM_SendChar>:
-           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
-  \param [in]     ch  Character to transmit.
-  \returns            Character to transmit.
- */
-__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
-{
- 80003c0:	b480      	push	{r7}
- 80003c2:	b083      	sub	sp, #12
- 80003c4:	af00      	add	r7, sp, #0
- 80003c6:	6078      	str	r0, [r7, #4]
-  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
- 80003c8:	f04f 4360 	mov.w	r3, #3758096384	; 0xe0000000
- 80003cc:	f8d3 3e80 	ldr.w	r3, [r3, #3712]	; 0xe80
- 80003d0:	f003 0301 	and.w	r3, r3, #1
- 80003d4:	2b00      	cmp	r3, #0
- 80003d6:	d013      	beq.n	8000400 <ITM_SendChar+0x40>
-      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
- 80003d8:	f04f 4360 	mov.w	r3, #3758096384	; 0xe0000000
- 80003dc:	f8d3 3e00 	ldr.w	r3, [r3, #3584]	; 0xe00
- 80003e0:	f003 0301 	and.w	r3, r3, #1
-  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
- 80003e4:	2b00      	cmp	r3, #0
- 80003e6:	d00b      	beq.n	8000400 <ITM_SendChar+0x40>
-  {
-    while (ITM->PORT[0U].u32 == 0UL)
- 80003e8:	e000      	b.n	80003ec <ITM_SendChar+0x2c>
-    {
-      __NOP();
- 80003ea:	bf00      	nop
-    while (ITM->PORT[0U].u32 == 0UL)
- 80003ec:	f04f 4360 	mov.w	r3, #3758096384	; 0xe0000000
- 80003f0:	681b      	ldr	r3, [r3, #0]
- 80003f2:	2b00      	cmp	r3, #0
- 80003f4:	d0f9      	beq.n	80003ea <ITM_SendChar+0x2a>
-    }
-    ITM->PORT[0U].u8 = (uint8_t)ch;
- 80003f6:	f04f 4360 	mov.w	r3, #3758096384	; 0xe0000000
- 80003fa:	687a      	ldr	r2, [r7, #4]
- 80003fc:	b2d2      	uxtb	r2, r2
- 80003fe:	701a      	strb	r2, [r3, #0]
-  }
-  return (ch);
- 8000400:	687b      	ldr	r3, [r7, #4]
-}
- 8000402:	4618      	mov	r0, r3
- 8000404:	370c      	adds	r7, #12
- 8000406:	46bd      	mov	sp, r7
- 8000408:	f85d 7b04 	ldr.w	r7, [sp], #4
- 800040c:	4770      	bx	lr
-
-0800040e <_write>:
-/* Private user code ---------------------------------------------------------*/
-/* USER CODE BEGIN 0 */
-#define min(x, y) (x) < (y) ? (x) : (y)
-#define max(x, y) (x) > (y) ? (x) : (y)
-
-int _write(int32_t file, uint8_t *ptr, int32_t len) {
- 800040e:	b580      	push	{r7, lr}
- 8000410:	b086      	sub	sp, #24
- 8000412:	af00      	add	r7, sp, #0
- 8000414:	60f8      	str	r0, [r7, #12]
- 8000416:	60b9      	str	r1, [r7, #8]
- 8000418:	607a      	str	r2, [r7, #4]
-	for (int32_t i = 0; i < len; ++i)
- 800041a:	2300      	movs	r3, #0
- 800041c:	617b      	str	r3, [r7, #20]
- 800041e:	e009      	b.n	8000434 <_write+0x26>
-		ITM_SendChar(*ptr++);
- 8000420:	68bb      	ldr	r3, [r7, #8]
- 8000422:	1c5a      	adds	r2, r3, #1
- 8000424:	60ba      	str	r2, [r7, #8]
- 8000426:	781b      	ldrb	r3, [r3, #0]
- 8000428:	4618      	mov	r0, r3
- 800042a:	f7ff ffc9 	bl	80003c0 <ITM_SendChar>
-	for (int32_t i = 0; i < len; ++i)
- 800042e:	697b      	ldr	r3, [r7, #20]
- 8000430:	3301      	adds	r3, #1
- 8000432:	617b      	str	r3, [r7, #20]
- 8000434:	697a      	ldr	r2, [r7, #20]
- 8000436:	687b      	ldr	r3, [r7, #4]
- 8000438:	429a      	cmp	r2, r3
- 800043a:	dbf1      	blt.n	8000420 <_write+0x12>
-	return len;
- 800043c:	687b      	ldr	r3, [r7, #4]
-}
- 800043e:	4618      	mov	r0, r3
- 8000440:	3718      	adds	r7, #24
- 8000442:	46bd      	mov	sp, r7
- 8000444:	bd80      	pop	{r7, pc}
-	...
-
-08000448 <LOG_ERROR>:
-
-extern void LOG_ERROR(const char *format, ...) {
- 8000448:	b40f      	push	{r0, r1, r2, r3}
- 800044a:	b580      	push	{r7, lr}
- 800044c:	b082      	sub	sp, #8
- 800044e:	af00      	add	r7, sp, #0
-	va_list args;
-	va_start(args, format);
- 8000450:	f107 0314 	add.w	r3, r7, #20
- 8000454:	607b      	str	r3, [r7, #4]
-	fprintf(stderr, "ERROR: ");
- 8000456:	4b0f      	ldr	r3, [pc, #60]	; (8000494 <LOG_ERROR+0x4c>)
- 8000458:	681b      	ldr	r3, [r3, #0]
- 800045a:	68db      	ldr	r3, [r3, #12]
- 800045c:	2207      	movs	r2, #7
- 800045e:	2101      	movs	r1, #1
- 8000460:	480d      	ldr	r0, [pc, #52]	; (8000498 <LOG_ERROR+0x50>)
- 8000462:	f010 fba3 	bl	8010bac <fwrite>
-	vfprintf(stderr, format, args);
- 8000466:	4b0b      	ldr	r3, [pc, #44]	; (8000494 <LOG_ERROR+0x4c>)
- 8000468:	681b      	ldr	r3, [r3, #0]
- 800046a:	68db      	ldr	r3, [r3, #12]
- 800046c:	687a      	ldr	r2, [r7, #4]
- 800046e:	6939      	ldr	r1, [r7, #16]
- 8000470:	4618      	mov	r0, r3
- 8000472:	f010 f8f3 	bl	801065c <vfiprintf>
-	fprintf(stderr, "\r\n");
- 8000476:	4b07      	ldr	r3, [pc, #28]	; (8000494 <LOG_ERROR+0x4c>)
- 8000478:	681b      	ldr	r3, [r3, #0]
- 800047a:	68db      	ldr	r3, [r3, #12]
- 800047c:	2202      	movs	r2, #2
- 800047e:	2101      	movs	r1, #1
- 8000480:	4806      	ldr	r0, [pc, #24]	; (800049c <LOG_ERROR+0x54>)
- 8000482:	f010 fb93 	bl	8010bac <fwrite>
-	va_end(args);
-}
- 8000486:	bf00      	nop
- 8000488:	3708      	adds	r7, #8
- 800048a:	46bd      	mov	sp, r7
- 800048c:	e8bd 4080 	ldmia.w	sp!, {r7, lr}
- 8000490:	b004      	add	sp, #16
- 8000492:	4770      	bx	lr
- 8000494:	240000cc 	.word	0x240000cc
- 8000498:	080115a4 	.word	0x080115a4
- 800049c:	080115ac 	.word	0x080115ac
-
-080004a0 <LOG_TRACE>:
-extern void LOG_TRACE(const char *message) {
- 80004a0:	b580      	push	{r7, lr}
- 80004a2:	b082      	sub	sp, #8
- 80004a4:	af00      	add	r7, sp, #0
- 80004a6:	6078      	str	r0, [r7, #4]
-	printf("TRACE: %s \r\n", message);
- 80004a8:	6879      	ldr	r1, [r7, #4]
- 80004aa:	4803      	ldr	r0, [pc, #12]	; (80004b8 <LOG_TRACE+0x18>)
- 80004ac:	f010 fb8c 	bl	8010bc8 <iprintf>
-}
- 80004b0:	bf00      	nop
- 80004b2:	3708      	adds	r7, #8
- 80004b4:	46bd      	mov	sp, r7
- 80004b6:	bd80      	pop	{r7, pc}
- 80004b8:	080115b0 	.word	0x080115b0
-
-080004bc <data_source>:
-		LOG_ERROR("lwftp_retrieve failed (%d)", error);
-	}
-	// FTP session will continue with RETR and sink callbacks
-}
-
-static uint data_source(void *arg, const char **pptr, uint maxlen) {
- 80004bc:	b480      	push	{r7}
- 80004be:	b087      	sub	sp, #28
- 80004c0:	af00      	add	r7, sp, #0
- 80004c2:	60f8      	str	r0, [r7, #12]
- 80004c4:	60b9      	str	r1, [r7, #8]
- 80004c6:	607a      	str	r2, [r7, #4]
-	static const uint mylen = 12345;
-	static const char *const mydata = (char*) 0x20000000;
-	static uint offset = 0;
-	uint len = 0;
- 80004c8:	2300      	movs	r3, #0
- 80004ca:	617b      	str	r3, [r7, #20]
-
-	// Check for data request or data sent notice
-	if (pptr) {
- 80004cc:	68bb      	ldr	r3, [r7, #8]
- 80004ce:	2b00      	cmp	r3, #0
- 80004d0:	d013      	beq.n	80004fa <data_source+0x3e>
-		len = mylen - offset;
- 80004d2:	4b15      	ldr	r3, [pc, #84]	; (8000528 <data_source+0x6c>)
- 80004d4:	681a      	ldr	r2, [r3, #0]
- 80004d6:	4b15      	ldr	r3, [pc, #84]	; (800052c <data_source+0x70>)
- 80004d8:	681b      	ldr	r3, [r3, #0]
- 80004da:	1ad3      	subs	r3, r2, r3
- 80004dc:	617b      	str	r3, [r7, #20]
-		if (len > maxlen)
- 80004de:	697a      	ldr	r2, [r7, #20]
- 80004e0:	687b      	ldr	r3, [r7, #4]
- 80004e2:	429a      	cmp	r2, r3
- 80004e4:	d901      	bls.n	80004ea <data_source+0x2e>
-			len = maxlen;
- 80004e6:	687b      	ldr	r3, [r7, #4]
- 80004e8:	617b      	str	r3, [r7, #20]
-		*pptr = mydata + offset;
- 80004ea:	4b11      	ldr	r3, [pc, #68]	; (8000530 <data_source+0x74>)
- 80004ec:	681a      	ldr	r2, [r3, #0]
- 80004ee:	4b0f      	ldr	r3, [pc, #60]	; (800052c <data_source+0x70>)
- 80004f0:	681b      	ldr	r3, [r3, #0]
- 80004f2:	441a      	add	r2, r3
- 80004f4:	68bb      	ldr	r3, [r7, #8]
- 80004f6:	601a      	str	r2, [r3, #0]
- 80004f8:	e00f      	b.n	800051a <data_source+0x5e>
-	} else {
-		offset += maxlen;
- 80004fa:	4b0c      	ldr	r3, [pc, #48]	; (800052c <data_source+0x70>)
- 80004fc:	681a      	ldr	r2, [r3, #0]
- 80004fe:	687b      	ldr	r3, [r7, #4]
- 8000500:	4413      	add	r3, r2
- 8000502:	4a0a      	ldr	r2, [pc, #40]	; (800052c <data_source+0x70>)
- 8000504:	6013      	str	r3, [r2, #0]
-		if (offset > mylen)
- 8000506:	4b09      	ldr	r3, [pc, #36]	; (800052c <data_source+0x70>)
- 8000508:	681a      	ldr	r2, [r3, #0]
- 800050a:	4b07      	ldr	r3, [pc, #28]	; (8000528 <data_source+0x6c>)
- 800050c:	681b      	ldr	r3, [r3, #0]
- 800050e:	429a      	cmp	r2, r3
- 8000510:	d903      	bls.n	800051a <data_source+0x5e>
-			offset = mylen;
- 8000512:	4b05      	ldr	r3, [pc, #20]	; (8000528 <data_source+0x6c>)
- 8000514:	681b      	ldr	r3, [r3, #0]
- 8000516:	4a05      	ldr	r2, [pc, #20]	; (800052c <data_source+0x70>)
- 8000518:	6013      	str	r3, [r2, #0]
-	}
-	return len;
- 800051a:	697b      	ldr	r3, [r7, #20]
-}
- 800051c:	4618      	mov	r0, r3
- 800051e:	371c      	adds	r7, #28
- 8000520:	46bd      	mov	sp, r7
- 8000522:	f85d 7b04 	ldr.w	r7, [sp], #4
- 8000526:	4770      	bx	lr
- 8000528:	08014c78 	.word	0x08014c78
- 800052c:	240000ec 	.word	0x240000ec
- 8000530:	08014c7c 	.word	0x08014c7c
-
-08000534 <ftp_connect_callback>:
-
-static void ftp_connect_callback(void *arg, int result) {
- 8000534:	b580      	push	{r7, lr}
- 8000536:	b084      	sub	sp, #16
- 8000538:	af00      	add	r7, sp, #0
- 800053a:	6078      	str	r0, [r7, #4]
- 800053c:	6039      	str	r1, [r7, #0]
-	lwftp_session_t *s = (lwftp_session_t*) arg;
- 800053e:	687b      	ldr	r3, [r7, #4]
- 8000540:	60fb      	str	r3, [r7, #12]
-	err_t error;
-	if (result == LWFTP_RESULT_LOGGED) {
- 8000542:	683b      	ldr	r3, [r7, #0]
- 8000544:	2b02      	cmp	r3, #2
- 8000546:	d103      	bne.n	8000550 <ftp_connect_callback+0x1c>
-		LOG_TRACE("login success !!!!! \r\n");
- 8000548:	4806      	ldr	r0, [pc, #24]	; (8000564 <ftp_connect_callback+0x30>)
- 800054a:	f7ff ffa9 	bl	80004a0 <LOG_TRACE>
- 800054e:	e002      	b.n	8000556 <ftp_connect_callback+0x22>
-	} else {
-		LOG_TRACE("login failed !!!!! \r\n");
- 8000550:	4805      	ldr	r0, [pc, #20]	; (8000568 <ftp_connect_callback+0x34>)
- 8000552:	f7ff ffa5 	bl	80004a0 <LOG_TRACE>
-//		return lwftp_close(s);
-//	}
-
-	return
-	// Continue with STOR request
-	s->data_source = data_source;
- 8000556:	68fb      	ldr	r3, [r7, #12]
- 8000558:	4a04      	ldr	r2, [pc, #16]	; (800056c <ftp_connect_callback+0x38>)
- 800055a:	619a      	str	r2, [r3, #24]
-	error = lwftp_store(s);
-	if (error != LWFTP_RESULT_INPROGRESS) {
-		LOG_ERROR("lwftp_store failed (%d)", error);
-	}
-	// FTP session will continue with STOR and source callbacks
-}
- 800055c:	3710      	adds	r7, #16
- 800055e:	46bd      	mov	sp, r7
- 8000560:	bd80      	pop	{r7, pc}
- 8000562:	bf00      	nop
- 8000564:	08011610 	.word	0x08011610
- 8000568:	08011628 	.word	0x08011628
- 800056c:	080004bd 	.word	0x080004bd
-
-08000570 <ftp_test>:
-
-static void ftp_test(void) {
- 8000570:	b580      	push	{r7, lr}
- 8000572:	b082      	sub	sp, #8
- 8000574:	af00      	add	r7, sp, #0
-	static lwftp_session_t s;   // static content for the whole FTP session
-	err_t error;
-
-	// Initialize session data
-	memset(&s, 0, sizeof(s));
- 8000576:	2234      	movs	r2, #52	; 0x34
- 8000578:	2100      	movs	r1, #0
- 800057a:	4814      	ldr	r0, [pc, #80]	; (80005cc <ftp_test+0x5c>)
- 800057c:	f010 fc82 	bl	8010e84 <memset>
-
-	IP4_ADDR(&s.server_ip, 192, 168, 0, 100);
- 8000580:	4b12      	ldr	r3, [pc, #72]	; (80005cc <ftp_test+0x5c>)
- 8000582:	4a13      	ldr	r2, [pc, #76]	; (80005d0 <ftp_test+0x60>)
- 8000584:	601a      	str	r2, [r3, #0]
-	s.server_port = 21;
- 8000586:	4b11      	ldr	r3, [pc, #68]	; (80005cc <ftp_test+0x5c>)
- 8000588:	2215      	movs	r2, #21
- 800058a:	809a      	strh	r2, [r3, #4]
-	s.done_fn = ftp_connect_callback;
- 800058c:	4b0f      	ldr	r3, [pc, #60]	; (80005cc <ftp_test+0x5c>)
- 800058e:	4a11      	ldr	r2, [pc, #68]	; (80005d4 <ftp_test+0x64>)
- 8000590:	621a      	str	r2, [r3, #32]
-	s.user = "anonymous";	// Anonymous client
- 8000592:	4b0e      	ldr	r3, [pc, #56]	; (80005cc <ftp_test+0x5c>)
- 8000594:	4a10      	ldr	r2, [pc, #64]	; (80005d8 <ftp_test+0x68>)
- 8000596:	60da      	str	r2, [r3, #12]
-	s.pass = "space2lim@naver.com";
- 8000598:	4b0c      	ldr	r3, [pc, #48]	; (80005cc <ftp_test+0x5c>)
- 800059a:	4a10      	ldr	r2, [pc, #64]	; (80005dc <ftp_test+0x6c>)
- 800059c:	611a      	str	r2, [r3, #16]
-	// We have no extra user data, simply use the session structure
-	s.handle = &s;
- 800059e:	4b0b      	ldr	r3, [pc, #44]	; (80005cc <ftp_test+0x5c>)
- 80005a0:	4a0a      	ldr	r2, [pc, #40]	; (80005cc <ftp_test+0x5c>)
- 80005a2:	615a      	str	r2, [r3, #20]
-
-	// Start the connection state machine
-	error = lwftp_connect(&s);
- 80005a4:	4809      	ldr	r0, [pc, #36]	; (80005cc <ftp_test+0x5c>)
- 80005a6:	f004 fa09 	bl	80049bc <lwftp_connect>
- 80005aa:	4603      	mov	r3, r0
- 80005ac:	71fb      	strb	r3, [r7, #7]
-	if (error != LWFTP_RESULT_INPROGRESS) {
- 80005ae:	f997 3007 	ldrsb.w	r3, [r7, #7]
- 80005b2:	2b01      	cmp	r3, #1
- 80005b4:	d005      	beq.n	80005c2 <ftp_test+0x52>
-		LOG_ERROR("lwftp_connect failed (%d)", error);
- 80005b6:	f997 3007 	ldrsb.w	r3, [r7, #7]
- 80005ba:	4619      	mov	r1, r3
- 80005bc:	4808      	ldr	r0, [pc, #32]	; (80005e0 <ftp_test+0x70>)
- 80005be:	f7ff ff43 	bl	8000448 <LOG_ERROR>
-	}
-	// FTP session will continue with the connection callback
-}
- 80005c2:	bf00      	nop
- 80005c4:	3708      	adds	r7, #8
- 80005c6:	46bd      	mov	sp, r7
- 80005c8:	bd80      	pop	{r7, pc}
- 80005ca:	bf00      	nop
- 80005cc:	240000f0 	.word	0x240000f0
- 80005d0:	6400a8c0 	.word	0x6400a8c0
- 80005d4:	08000535 	.word	0x08000535
- 80005d8:	08011640 	.word	0x08011640
- 80005dc:	0801164c 	.word	0x0801164c
- 80005e0:	08011660 	.word	0x08011660
-
-080005e4 <main>:
-
-/**
- * @brief  The application entry point.
- * @retval int
- */
-int main(void) {
- 80005e4:	b580      	push	{r7, lr}
- 80005e6:	b084      	sub	sp, #16
- 80005e8:	af00      	add	r7, sp, #0
-	/* USER CODE BEGIN 1 */
-
-	/* USER CODE END 1 */
-
-	/* MPU Configuration--------------------------------------------------------*/
-	MPU_Config();
- 80005ea:	f000 f929 	bl	8000840 <MPU_Config>
-    if (SCB->CCR & SCB_CCR_IC_Msk) return;  /* return if ICache is already enabled */
- 80005ee:	4b38      	ldr	r3, [pc, #224]	; (80006d0 <main+0xec>)
- 80005f0:	695b      	ldr	r3, [r3, #20]
- 80005f2:	f403 3300 	and.w	r3, r3, #131072	; 0x20000
- 80005f6:	2b00      	cmp	r3, #0
- 80005f8:	d11b      	bne.n	8000632 <main+0x4e>
-  \details Acts as a special kind of Data Memory Barrier.
-           It completes when all explicit memory accesses before this instruction complete.
- */
-__STATIC_FORCEINLINE void __DSB(void)
-{
-  __ASM volatile ("dsb 0xF":::"memory");
- 80005fa:	f3bf 8f4f 	dsb	sy
-}
- 80005fe:	bf00      	nop
-  __ASM volatile ("isb 0xF":::"memory");
- 8000600:	f3bf 8f6f 	isb	sy
-}
- 8000604:	bf00      	nop
-    SCB->ICIALLU = 0UL;                     /* invalidate I-Cache */
- 8000606:	4b32      	ldr	r3, [pc, #200]	; (80006d0 <main+0xec>)
- 8000608:	2200      	movs	r2, #0
- 800060a:	f8c3 2250 	str.w	r2, [r3, #592]	; 0x250
-  __ASM volatile ("dsb 0xF":::"memory");
- 800060e:	f3bf 8f4f 	dsb	sy
-}
- 8000612:	bf00      	nop
-  __ASM volatile ("isb 0xF":::"memory");
- 8000614:	f3bf 8f6f 	isb	sy
-}
- 8000618:	bf00      	nop
-    SCB->CCR |=  (uint32_t)SCB_CCR_IC_Msk;  /* enable I-Cache */
- 800061a:	4b2d      	ldr	r3, [pc, #180]	; (80006d0 <main+0xec>)
- 800061c:	695b      	ldr	r3, [r3, #20]
- 800061e:	4a2c      	ldr	r2, [pc, #176]	; (80006d0 <main+0xec>)
- 8000620:	f443 3300 	orr.w	r3, r3, #131072	; 0x20000
- 8000624:	6153      	str	r3, [r2, #20]
-  __ASM volatile ("dsb 0xF":::"memory");
- 8000626:	f3bf 8f4f 	dsb	sy
-}
- 800062a:	bf00      	nop
-  __ASM volatile ("isb 0xF":::"memory");
- 800062c:	f3bf 8f6f 	isb	sy
-}
- 8000630:	e000      	b.n	8000634 <main+0x50>
-    if (SCB->CCR & SCB_CCR_IC_Msk) return;  /* return if ICache is already enabled */
- 8000632:	bf00      	nop
-    if (SCB->CCR & SCB_CCR_DC_Msk) return;  /* return if DCache is already enabled */
- 8000634:	4b26      	ldr	r3, [pc, #152]	; (80006d0 <main+0xec>)
- 8000636:	695b      	ldr	r3, [r3, #20]
- 8000638:	f403 3380 	and.w	r3, r3, #65536	; 0x10000
- 800063c:	2b00      	cmp	r3, #0
- 800063e:	d138      	bne.n	80006b2 <main+0xce>
-    SCB->CSSELR = 0U;                       /* select Level 1 data cache */
- 8000640:	4b23      	ldr	r3, [pc, #140]	; (80006d0 <main+0xec>)
- 8000642:	2200      	movs	r2, #0
- 8000644:	f8c3 2084 	str.w	r2, [r3, #132]	; 0x84
-  __ASM volatile ("dsb 0xF":::"memory");
- 8000648:	f3bf 8f4f 	dsb	sy
-}
- 800064c:	bf00      	nop
-    ccsidr = SCB->CCSIDR;
- 800064e:	4b20      	ldr	r3, [pc, #128]	; (80006d0 <main+0xec>)
- 8000650:	f8d3 3080 	ldr.w	r3, [r3, #128]	; 0x80
- 8000654:	60fb      	str	r3, [r7, #12]
-    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
- 8000656:	68fb      	ldr	r3, [r7, #12]
- 8000658:	0b5b      	lsrs	r3, r3, #13
- 800065a:	f3c3 030e 	ubfx	r3, r3, #0, #15
- 800065e:	60bb      	str	r3, [r7, #8]
-      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
- 8000660:	68fb      	ldr	r3, [r7, #12]
- 8000662:	08db      	lsrs	r3, r3, #3
- 8000664:	f3c3 0309 	ubfx	r3, r3, #0, #10
- 8000668:	607b      	str	r3, [r7, #4]
-        SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
- 800066a:	68bb      	ldr	r3, [r7, #8]
- 800066c:	015a      	lsls	r2, r3, #5
- 800066e:	f643 73e0 	movw	r3, #16352	; 0x3fe0
- 8000672:	4013      	ands	r3, r2
-                      ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk)  );
- 8000674:	687a      	ldr	r2, [r7, #4]
- 8000676:	0792      	lsls	r2, r2, #30
-        SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
- 8000678:	4915      	ldr	r1, [pc, #84]	; (80006d0 <main+0xec>)
- 800067a:	4313      	orrs	r3, r2
- 800067c:	f8c1 3260 	str.w	r3, [r1, #608]	; 0x260
-      } while (ways-- != 0U);
- 8000680:	687b      	ldr	r3, [r7, #4]
- 8000682:	1e5a      	subs	r2, r3, #1
- 8000684:	607a      	str	r2, [r7, #4]
- 8000686:	2b00      	cmp	r3, #0
- 8000688:	d1ef      	bne.n	800066a <main+0x86>
-    } while(sets-- != 0U);
- 800068a:	68bb      	ldr	r3, [r7, #8]
- 800068c:	1e5a      	subs	r2, r3, #1
- 800068e:	60ba      	str	r2, [r7, #8]
- 8000690:	2b00      	cmp	r3, #0
- 8000692:	d1e5      	bne.n	8000660 <main+0x7c>
-  __ASM volatile ("dsb 0xF":::"memory");
- 8000694:	f3bf 8f4f 	dsb	sy
-}
- 8000698:	bf00      	nop
-    SCB->CCR |=  (uint32_t)SCB_CCR_DC_Msk;  /* enable D-Cache */
- 800069a:	4b0d      	ldr	r3, [pc, #52]	; (80006d0 <main+0xec>)
- 800069c:	695b      	ldr	r3, [r3, #20]
- 800069e:	4a0c      	ldr	r2, [pc, #48]	; (80006d0 <main+0xec>)
- 80006a0:	f443 3380 	orr.w	r3, r3, #65536	; 0x10000
- 80006a4:	6153      	str	r3, [r2, #20]
-  __ASM volatile ("dsb 0xF":::"memory");
- 80006a6:	f3bf 8f4f 	dsb	sy
-}
- 80006aa:	bf00      	nop
-  __ASM volatile ("isb 0xF":::"memory");
- 80006ac:	f3bf 8f6f 	isb	sy
-}
- 80006b0:	e000      	b.n	80006b4 <main+0xd0>
-    if (SCB->CCR & SCB_CCR_DC_Msk) return;  /* return if DCache is already enabled */
- 80006b2:	bf00      	nop
-	SCB_EnableDCache();
-
-	/* MCU Configuration--------------------------------------------------------*/
-
-	/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
-	HAL_Init();
- 80006b4:	f000 fc24 	bl	8000f00 <HAL_Init>
-	/* USER CODE BEGIN Init */
-
-	/* USER CODE END Init */
-
-	/* Configure the system clock */
-	SystemClock_Config();
- 80006b8:	f000 f80c 	bl	80006d4 <SystemClock_Config>
-	/* USER CODE BEGIN SysInit */
-
-	/* USER CODE END SysInit */
-
-	/* Initialize all configured peripherals */
-	MX_GPIO_Init();
- 80006bc:	f000 f878 	bl	80007b0 <MX_GPIO_Init>
-	MX_LWIP_Init();
- 80006c0:	f004 fa04 	bl	8004acc <MX_LWIP_Init>
-
-	/* Infinite loop */
-	/* USER CODE BEGIN WHILE */
-
-	/* ============ LWFTP Code ============*/
-	ftp_test();
- 80006c4:	f7ff ff54 	bl	8000570 <ftp_test>
-//	ftp_connect();
-
-	while (1) {
-		MX_LWIP_Process();
- 80006c8:	f004 fb40 	bl	8004d4c <MX_LWIP_Process>
- 80006cc:	e7fc      	b.n	80006c8 <main+0xe4>
- 80006ce:	bf00      	nop
- 80006d0:	e000ed00 	.word	0xe000ed00
-
-080006d4 <SystemClock_Config>:
-
-/**
- * @brief System Clock Configuration
- * @retval None
- */
-void SystemClock_Config(void) {
- 80006d4:	b580      	push	{r7, lr}
- 80006d6:	b09c      	sub	sp, #112	; 0x70
- 80006d8:	af00      	add	r7, sp, #0
-	RCC_OscInitTypeDef RCC_OscInitStruct = { 0 };
- 80006da:	f107 0324 	add.w	r3, r7, #36	; 0x24
- 80006de:	224c      	movs	r2, #76	; 0x4c
- 80006e0:	2100      	movs	r1, #0
- 80006e2:	4618      	mov	r0, r3
- 80006e4:	f010 fbce 	bl	8010e84 <memset>
-	RCC_ClkInitTypeDef RCC_ClkInitStruct = { 0 };
- 80006e8:	1d3b      	adds	r3, r7, #4
- 80006ea:	2220      	movs	r2, #32
- 80006ec:	2100      	movs	r1, #0
- 80006ee:	4618      	mov	r0, r3
- 80006f0:	f010 fbc8 	bl	8010e84 <memset>
-
-	/** Supply configuration update enable
-	 */
-	HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY);
- 80006f4:	2002      	movs	r0, #2
- 80006f6:	f002 fce9 	bl	80030cc <HAL_PWREx_ConfigSupply>
-
-	/** Configure the main internal regulator output voltage
-	 */
-	__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE0);
- 80006fa:	2300      	movs	r3, #0
- 80006fc:	603b      	str	r3, [r7, #0]
- 80006fe:	4b2b      	ldr	r3, [pc, #172]	; (80007ac <SystemClock_Config+0xd8>)
- 8000700:	699b      	ldr	r3, [r3, #24]
- 8000702:	4a2a      	ldr	r2, [pc, #168]	; (80007ac <SystemClock_Config+0xd8>)
- 8000704:	f423 4340 	bic.w	r3, r3, #49152	; 0xc000
- 8000708:	6193      	str	r3, [r2, #24]
- 800070a:	4b28      	ldr	r3, [pc, #160]	; (80007ac <SystemClock_Config+0xd8>)
- 800070c:	699b      	ldr	r3, [r3, #24]
- 800070e:	f403 4340 	and.w	r3, r3, #49152	; 0xc000
- 8000712:	603b      	str	r3, [r7, #0]
- 8000714:	683b      	ldr	r3, [r7, #0]
-
-	while (!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {
- 8000716:	bf00      	nop
- 8000718:	4b24      	ldr	r3, [pc, #144]	; (80007ac <SystemClock_Config+0xd8>)
- 800071a:	699b      	ldr	r3, [r3, #24]
- 800071c:	f403 5300 	and.w	r3, r3, #8192	; 0x2000
- 8000720:	f5b3 5f00 	cmp.w	r3, #8192	; 0x2000
- 8000724:	d1f8      	bne.n	8000718 <SystemClock_Config+0x44>
-	}
-
-	/** Initializes the RCC Oscillators according to the specified parameters
-	 * in the RCC_OscInitTypeDef structure.
-	 */
-	RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
- 8000726:	2301      	movs	r3, #1
- 8000728:	627b      	str	r3, [r7, #36]	; 0x24
-	RCC_OscInitStruct.HSEState = RCC_HSE_ON;
- 800072a:	f44f 3380 	mov.w	r3, #65536	; 0x10000
- 800072e:	62bb      	str	r3, [r7, #40]	; 0x28
-	RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
- 8000730:	2302      	movs	r3, #2
- 8000732:	64bb      	str	r3, [r7, #72]	; 0x48
-	RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
- 8000734:	2302      	movs	r3, #2
- 8000736:	64fb      	str	r3, [r7, #76]	; 0x4c
-	RCC_OscInitStruct.PLL.PLLM = 5;
- 8000738:	2305      	movs	r3, #5
- 800073a:	653b      	str	r3, [r7, #80]	; 0x50
-	RCC_OscInitStruct.PLL.PLLN = 96;
- 800073c:	2360      	movs	r3, #96	; 0x60
- 800073e:	657b      	str	r3, [r7, #84]	; 0x54
-	RCC_OscInitStruct.PLL.PLLP = 1;
- 8000740:	2301      	movs	r3, #1
- 8000742:	65bb      	str	r3, [r7, #88]	; 0x58
-	RCC_OscInitStruct.PLL.PLLQ = 2;
- 8000744:	2302      	movs	r3, #2
- 8000746:	65fb      	str	r3, [r7, #92]	; 0x5c
-	RCC_OscInitStruct.PLL.PLLR = 2;
- 8000748:	2302      	movs	r3, #2
- 800074a:	663b      	str	r3, [r7, #96]	; 0x60
-	RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_2;
- 800074c:	2308      	movs	r3, #8
- 800074e:	667b      	str	r3, [r7, #100]	; 0x64
-	RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE;
- 8000750:	2300      	movs	r3, #0
- 8000752:	66bb      	str	r3, [r7, #104]	; 0x68
-	RCC_OscInitStruct.PLL.PLLFRACN = 0;
- 8000754:	2300      	movs	r3, #0
- 8000756:	66fb      	str	r3, [r7, #108]	; 0x6c
-	if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
- 8000758:	f107 0324 	add.w	r3, r7, #36	; 0x24
- 800075c:	4618      	mov	r0, r3
- 800075e:	f002 fcef 	bl	8003140 <HAL_RCC_OscConfig>
- 8000762:	4603      	mov	r3, r0
- 8000764:	2b00      	cmp	r3, #0
- 8000766:	d001      	beq.n	800076c <SystemClock_Config+0x98>
-		Error_Handler();
- 8000768:	f000 f8b7 	bl	80008da <Error_Handler>
-	}
-
-	/** Initializes the CPU, AHB and APB buses clocks
-	 */
-	RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
- 800076c:	233f      	movs	r3, #63	; 0x3f
- 800076e:	607b      	str	r3, [r7, #4]
-			| RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_D3PCLK1
-			| RCC_CLOCKTYPE_D1PCLK1;
-	RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
- 8000770:	2303      	movs	r3, #3
- 8000772:	60bb      	str	r3, [r7, #8]
-	RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1;
- 8000774:	2300      	movs	r3, #0
- 8000776:	60fb      	str	r3, [r7, #12]
-	RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2;
- 8000778:	2308      	movs	r3, #8
- 800077a:	613b      	str	r3, [r7, #16]
-	RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2;
- 800077c:	2340      	movs	r3, #64	; 0x40
- 800077e:	617b      	str	r3, [r7, #20]
-	RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2;
- 8000780:	2340      	movs	r3, #64	; 0x40
- 8000782:	61bb      	str	r3, [r7, #24]
-	RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2;
- 8000784:	f44f 6380 	mov.w	r3, #1024	; 0x400
- 8000788:	61fb      	str	r3, [r7, #28]
-	RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2;
- 800078a:	2340      	movs	r3, #64	; 0x40
- 800078c:	623b      	str	r3, [r7, #32]
-
-	if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK) {
- 800078e:	1d3b      	adds	r3, r7, #4
- 8000790:	2103      	movs	r1, #3
- 8000792:	4618      	mov	r0, r3
- 8000794:	f003 f8ae 	bl	80038f4 <HAL_RCC_ClockConfig>
- 8000798:	4603      	mov	r3, r0
- 800079a:	2b00      	cmp	r3, #0
- 800079c:	d001      	beq.n	80007a2 <SystemClock_Config+0xce>
-		Error_Handler();
- 800079e:	f000 f89c 	bl	80008da <Error_Handler>
-	}
-}
- 80007a2:	bf00      	nop
- 80007a4:	3770      	adds	r7, #112	; 0x70
- 80007a6:	46bd      	mov	sp, r7
- 80007a8:	bd80      	pop	{r7, pc}
- 80007aa:	bf00      	nop
- 80007ac:	58024800 	.word	0x58024800
-
-080007b0 <MX_GPIO_Init>:
-/**
- * @brief GPIO Initialization Function
- * @param None
- * @retval None
- */
-static void MX_GPIO_Init(void) {
- 80007b0:	b480      	push	{r7}
- 80007b2:	b085      	sub	sp, #20
- 80007b4:	af00      	add	r7, sp, #0
-	/* USER CODE BEGIN MX_GPIO_Init_1 */
-	/* USER CODE END MX_GPIO_Init_1 */
-
-	/* GPIO Ports Clock Enable */
-	__HAL_RCC_GPIOB_CLK_ENABLE();
- 80007b6:	4b21      	ldr	r3, [pc, #132]	; (800083c <MX_GPIO_Init+0x8c>)
- 80007b8:	f8d3 30e0 	ldr.w	r3, [r3, #224]	; 0xe0
- 80007bc:	4a1f      	ldr	r2, [pc, #124]	; (800083c <MX_GPIO_Init+0x8c>)
- 80007be:	f043 0302 	orr.w	r3, r3, #2
- 80007c2:	f8c2 30e0 	str.w	r3, [r2, #224]	; 0xe0
- 80007c6:	4b1d      	ldr	r3, [pc, #116]	; (800083c <MX_GPIO_Init+0x8c>)
- 80007c8:	f8d3 30e0 	ldr.w	r3, [r3, #224]	; 0xe0
- 80007cc:	f003 0302 	and.w	r3, r3, #2
- 80007d0:	60fb      	str	r3, [r7, #12]
- 80007d2:	68fb      	ldr	r3, [r7, #12]
-	__HAL_RCC_GPIOA_CLK_ENABLE();
- 80007d4:	4b19      	ldr	r3, [pc, #100]	; (800083c <MX_GPIO_Init+0x8c>)
- 80007d6:	f8d3 30e0 	ldr.w	r3, [r3, #224]	; 0xe0
- 80007da:	4a18      	ldr	r2, [pc, #96]	; (800083c <MX_GPIO_Init+0x8c>)
- 80007dc:	f043 0301 	orr.w	r3, r3, #1
- 80007e0:	f8c2 30e0 	str.w	r3, [r2, #224]	; 0xe0
- 80007e4:	4b15      	ldr	r3, [pc, #84]	; (800083c <MX_GPIO_Init+0x8c>)
- 80007e6:	f8d3 30e0 	ldr.w	r3, [r3, #224]	; 0xe0
- 80007ea:	f003 0301 	and.w	r3, r3, #1
- 80007ee:	60bb      	str	r3, [r7, #8]
- 80007f0:	68bb      	ldr	r3, [r7, #8]
-	__HAL_RCC_GPIOH_CLK_ENABLE();
- 80007f2:	4b12      	ldr	r3, [pc, #72]	; (800083c <MX_GPIO_Init+0x8c>)
- 80007f4:	f8d3 30e0 	ldr.w	r3, [r3, #224]	; 0xe0
- 80007f8:	4a10      	ldr	r2, [pc, #64]	; (800083c <MX_GPIO_Init+0x8c>)
- 80007fa:	f043 0380 	orr.w	r3, r3, #128	; 0x80
- 80007fe:	f8c2 30e0 	str.w	r3, [r2, #224]	; 0xe0
- 8000802:	4b0e      	ldr	r3, [pc, #56]	; (800083c <MX_GPIO_Init+0x8c>)
- 8000804:	f8d3 30e0 	ldr.w	r3, [r3, #224]	; 0xe0
- 8000808:	f003 0380 	and.w	r3, r3, #128	; 0x80
- 800080c:	607b      	str	r3, [r7, #4]
- 800080e:	687b      	ldr	r3, [r7, #4]
-	__HAL_RCC_GPIOC_CLK_ENABLE();
- 8000810:	4b0a      	ldr	r3, [pc, #40]	; (800083c <MX_GPIO_Init+0x8c>)
- 8000812:	f8d3 30e0 	ldr.w	r3, [r3, #224]	; 0xe0
- 8000816:	4a09      	ldr	r2, [pc, #36]	; (800083c <MX_GPIO_Init+0x8c>)
- 8000818:	f043 0304 	orr.w	r3, r3, #4
- 800081c:	f8c2 30e0 	str.w	r3, [r2, #224]	; 0xe0
- 8000820:	4b06      	ldr	r3, [pc, #24]	; (800083c <MX_GPIO_Init+0x8c>)
- 8000822:	f8d3 30e0 	ldr.w	r3, [r3, #224]	; 0xe0
- 8000826:	f003 0304 	and.w	r3, r3, #4
- 800082a:	603b      	str	r3, [r7, #0]
- 800082c:	683b      	ldr	r3, [r7, #0]
-
-	/* USER CODE BEGIN MX_GPIO_Init_2 */
-	/* USER CODE END MX_GPIO_Init_2 */
-}
- 800082e:	bf00      	nop
- 8000830:	3714      	adds	r7, #20
- 8000832:	46bd      	mov	sp, r7
- 8000834:	f85d 7b04 	ldr.w	r7, [sp], #4
- 8000838:	4770      	bx	lr
- 800083a:	bf00      	nop
- 800083c:	58024400 	.word	0x58024400
-
-08000840 <MPU_Config>:
-
-/* USER CODE END 4 */
-
-/* MPU Configuration */
-
-void MPU_Config(void) {
- 8000840:	b580      	push	{r7, lr}
- 8000842:	b084      	sub	sp, #16
- 8000844:	af00      	add	r7, sp, #0
-	MPU_Region_InitTypeDef MPU_InitStruct = { 0 };
- 8000846:	463b      	mov	r3, r7
- 8000848:	2200      	movs	r2, #0
- 800084a:	601a      	str	r2, [r3, #0]
- 800084c:	605a      	str	r2, [r3, #4]
- 800084e:	609a      	str	r2, [r3, #8]
- 8000850:	60da      	str	r2, [r3, #12]
-
-	/* Disables the MPU */
-	HAL_MPU_Disable();
- 8000852:	f000 fd0b 	bl	800126c <HAL_MPU_Disable>
-
-	/** Initializes and configures the Region and the memory to be protected
-	 */
-	MPU_InitStruct.Enable = MPU_REGION_ENABLE;
- 8000856:	2301      	movs	r3, #1
- 8000858:	703b      	strb	r3, [r7, #0]
-	MPU_InitStruct.Number = MPU_REGION_NUMBER0;
- 800085a:	2300      	movs	r3, #0
- 800085c:	707b      	strb	r3, [r7, #1]
-	MPU_InitStruct.BaseAddress = 0x0;
- 800085e:	2300      	movs	r3, #0
- 8000860:	607b      	str	r3, [r7, #4]
-	MPU_InitStruct.Size = MPU_REGION_SIZE_4GB;
- 8000862:	231f      	movs	r3, #31
- 8000864:	723b      	strb	r3, [r7, #8]
-	MPU_InitStruct.SubRegionDisable = 0x87;
- 8000866:	2387      	movs	r3, #135	; 0x87
- 8000868:	727b      	strb	r3, [r7, #9]
-	MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0;
- 800086a:	2300      	movs	r3, #0
- 800086c:	72bb      	strb	r3, [r7, #10]
-	MPU_InitStruct.AccessPermission = MPU_REGION_NO_ACCESS;
- 800086e:	2300      	movs	r3, #0
- 8000870:	72fb      	strb	r3, [r7, #11]
-	MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_DISABLE;
- 8000872:	2301      	movs	r3, #1
- 8000874:	733b      	strb	r3, [r7, #12]
-	MPU_InitStruct.IsShareable = MPU_ACCESS_SHAREABLE;
- 8000876:	2301      	movs	r3, #1
- 8000878:	737b      	strb	r3, [r7, #13]
-	MPU_InitStruct.IsCacheable = MPU_ACCESS_NOT_CACHEABLE;
- 800087a:	2300      	movs	r3, #0
- 800087c:	73bb      	strb	r3, [r7, #14]
-	MPU_InitStruct.IsBufferable = MPU_ACCESS_NOT_BUFFERABLE;
- 800087e:	2300      	movs	r3, #0
- 8000880:	73fb      	strb	r3, [r7, #15]
-
-	HAL_MPU_ConfigRegion(&MPU_InitStruct);
- 8000882:	463b      	mov	r3, r7
- 8000884:	4618      	mov	r0, r3
- 8000886:	f000 fd29 	bl	80012dc <HAL_MPU_ConfigRegion>
-
-	/** Initializes and configures the Region and the memory to be protected
-	 */
-	MPU_InitStruct.Number = MPU_REGION_NUMBER1;
- 800088a:	2301      	movs	r3, #1
- 800088c:	707b      	strb	r3, [r7, #1]
-	MPU_InitStruct.BaseAddress = 0x30000000;
- 800088e:	f04f 5340 	mov.w	r3, #805306368	; 0x30000000
- 8000892:	607b      	str	r3, [r7, #4]
-	MPU_InitStruct.Size = MPU_REGION_SIZE_32KB;
- 8000894:	230e      	movs	r3, #14
- 8000896:	723b      	strb	r3, [r7, #8]
-	MPU_InitStruct.SubRegionDisable = 0x0;
- 8000898:	2300      	movs	r3, #0
- 800089a:	727b      	strb	r3, [r7, #9]
-	MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL1;
- 800089c:	2301      	movs	r3, #1
- 800089e:	72bb      	strb	r3, [r7, #10]
-	MPU_InitStruct.AccessPermission = MPU_REGION_FULL_ACCESS;
- 80008a0:	2303      	movs	r3, #3
- 80008a2:	72fb      	strb	r3, [r7, #11]
-	MPU_InitStruct.IsShareable = MPU_ACCESS_NOT_SHAREABLE;
- 80008a4:	2300      	movs	r3, #0
- 80008a6:	737b      	strb	r3, [r7, #13]
-
-	HAL_MPU_ConfigRegion(&MPU_InitStruct);
- 80008a8:	463b      	mov	r3, r7
- 80008aa:	4618      	mov	r0, r3
- 80008ac:	f000 fd16 	bl	80012dc <HAL_MPU_ConfigRegion>
-
-	/** Initializes and configures the Region and the memory to be protected
-	 */
-	MPU_InitStruct.Number = MPU_REGION_NUMBER2;
- 80008b0:	2302      	movs	r3, #2
- 80008b2:	707b      	strb	r3, [r7, #1]
-	MPU_InitStruct.Size = MPU_REGION_SIZE_512B;
- 80008b4:	2308      	movs	r3, #8
- 80008b6:	723b      	strb	r3, [r7, #8]
-	MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0;
- 80008b8:	2300      	movs	r3, #0
- 80008ba:	72bb      	strb	r3, [r7, #10]
-	MPU_InitStruct.IsShareable = MPU_ACCESS_SHAREABLE;
- 80008bc:	2301      	movs	r3, #1
- 80008be:	737b      	strb	r3, [r7, #13]
-	MPU_InitStruct.IsBufferable = MPU_ACCESS_BUFFERABLE;
- 80008c0:	2301      	movs	r3, #1
- 80008c2:	73fb      	strb	r3, [r7, #15]
-
-	HAL_MPU_ConfigRegion(&MPU_InitStruct);
- 80008c4:	463b      	mov	r3, r7
- 80008c6:	4618      	mov	r0, r3
- 80008c8:	f000 fd08 	bl	80012dc <HAL_MPU_ConfigRegion>
-	/* Enables the MPU */
-	HAL_MPU_Enable(MPU_PRIVILEGED_DEFAULT);
- 80008cc:	2004      	movs	r0, #4
- 80008ce:	f000 fce5 	bl	800129c <HAL_MPU_Enable>
-
-}
- 80008d2:	bf00      	nop
- 80008d4:	3710      	adds	r7, #16
- 80008d6:	46bd      	mov	sp, r7
- 80008d8:	bd80      	pop	{r7, pc}
-
-080008da <Error_Handler>:
-
-/**
- * @brief  This function is executed in case of error occurrence.
- * @retval None
- */
-void Error_Handler(void) {
- 80008da:	b480      	push	{r7}
- 80008dc:	af00      	add	r7, sp, #0
-  __ASM volatile ("cpsid i" : : : "memory");
- 80008de:	b672      	cpsid	i
-}
- 80008e0:	bf00      	nop
-	/* USER CODE BEGIN Error_Handler_Debug */
-	/* User can add his own implementation to report the HAL error return state */
-	__disable_irq();
-	while (1) {
- 80008e2:	e7fe      	b.n	80008e2 <Error_Handler+0x8>
-
-080008e4 <HAL_MspInit>:
-/* USER CODE END 0 */
-/**
-  * Initializes the Global MSP.
-  */
-void HAL_MspInit(void)
-{
- 80008e4:	b480      	push	{r7}
- 80008e6:	b083      	sub	sp, #12
- 80008e8:	af00      	add	r7, sp, #0
-  /* USER CODE BEGIN MspInit 0 */
-
-  /* USER CODE END MspInit 0 */
-
-  __HAL_RCC_SYSCFG_CLK_ENABLE();
- 80008ea:	4b0a      	ldr	r3, [pc, #40]	; (8000914 <HAL_MspInit+0x30>)
- 80008ec:	f8d3 30f4 	ldr.w	r3, [r3, #244]	; 0xf4
- 80008f0:	4a08      	ldr	r2, [pc, #32]	; (8000914 <HAL_MspInit+0x30>)
- 80008f2:	f043 0302 	orr.w	r3, r3, #2
- 80008f6:	f8c2 30f4 	str.w	r3, [r2, #244]	; 0xf4
- 80008fa:	4b06      	ldr	r3, [pc, #24]	; (8000914 <HAL_MspInit+0x30>)
- 80008fc:	f8d3 30f4 	ldr.w	r3, [r3, #244]	; 0xf4
- 8000900:	f003 0302 	and.w	r3, r3, #2
- 8000904:	607b      	str	r3, [r7, #4]
- 8000906:	687b      	ldr	r3, [r7, #4]
-  /* System interrupt init*/
-
-  /* USER CODE BEGIN MspInit 1 */
-
-  /* USER CODE END MspInit 1 */
-}
- 8000908:	bf00      	nop
- 800090a:	370c      	adds	r7, #12
- 800090c:	46bd      	mov	sp, r7
- 800090e:	f85d 7b04 	ldr.w	r7, [sp], #4
- 8000912:	4770      	bx	lr
- 8000914:	58024400 	.word	0x58024400
-
-08000918 <NMI_Handler>:
-/******************************************************************************/
-/**
-  * @brief This function handles Non maskable interrupt.
-  */
-void NMI_Handler(void)
-{
- 8000918:	b480      	push	{r7}
- 800091a:	af00      	add	r7, sp, #0
-  /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
-
-  /* USER CODE END NonMaskableInt_IRQn 0 */
-  /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
-   while (1)
- 800091c:	e7fe      	b.n	800091c <NMI_Handler+0x4>
-
-0800091e <HardFault_Handler>:
-
-/**
-  * @brief This function handles Hard fault interrupt.
-  */
-void HardFault_Handler(void)
-{
- 800091e:	b480      	push	{r7}
- 8000920:	af00      	add	r7, sp, #0
-  /* USER CODE BEGIN HardFault_IRQn 0 */
-
-  /* USER CODE END HardFault_IRQn 0 */
-  while (1)
- 8000922:	e7fe      	b.n	8000922 <HardFault_Handler+0x4>
-
-08000924 <MemManage_Handler>:
-
-/**
-  * @brief This function handles Memory management fault.
-  */
-void MemManage_Handler(void)
-{
- 8000924:	b480      	push	{r7}
- 8000926:	af00      	add	r7, sp, #0
-  /* USER CODE BEGIN MemoryManagement_IRQn 0 */
-
-  /* USER CODE END MemoryManagement_IRQn 0 */
-  while (1)
- 8000928:	e7fe      	b.n	8000928 <MemManage_Handler+0x4>
-
-0800092a <BusFault_Handler>:
-
-/**
-  * @brief This function handles Pre-fetch fault, memory access fault.
-  */
-void BusFault_Handler(void)
-{
- 800092a:	b480      	push	{r7}
- 800092c:	af00      	add	r7, sp, #0
-  /* USER CODE BEGIN BusFault_IRQn 0 */
-
-  /* USER CODE END BusFault_IRQn 0 */
-  while (1)
- 800092e:	e7fe      	b.n	800092e <BusFault_Handler+0x4>
-
-08000930 <UsageFault_Handler>:
-
-/**
-  * @brief This function handles Undefined instruction or illegal state.
-  */
-void UsageFault_Handler(void)
-{
- 8000930:	b480      	push	{r7}
- 8000932:	af00      	add	r7, sp, #0
-  /* USER CODE BEGIN UsageFault_IRQn 0 */
-
-  /* USER CODE END UsageFault_IRQn 0 */
-  while (1)
- 8000934:	e7fe      	b.n	8000934 <UsageFault_Handler+0x4>
-
-08000936 <SVC_Handler>:
-
-/**
-  * @brief This function handles System service call via SWI instruction.
-  */
-void SVC_Handler(void)
-{
- 8000936:	b480      	push	{r7}
- 8000938:	af00      	add	r7, sp, #0
-
-  /* USER CODE END SVCall_IRQn 0 */
-  /* USER CODE BEGIN SVCall_IRQn 1 */
-
-  /* USER CODE END SVCall_IRQn 1 */
-}
- 800093a:	bf00      	nop
- 800093c:	46bd      	mov	sp, r7
- 800093e:	f85d 7b04 	ldr.w	r7, [sp], #4
- 8000942:	4770      	bx	lr
-
-08000944 <DebugMon_Handler>:
-
-/**
-  * @brief This function handles Debug monitor.
-  */
-void DebugMon_Handler(void)
-{
- 8000944:	b480      	push	{r7}
- 8000946:	af00      	add	r7, sp, #0
-
-  /* USER CODE END DebugMonitor_IRQn 0 */
-  /* USER CODE BEGIN DebugMonitor_IRQn 1 */
-
-  /* USER CODE END DebugMonitor_IRQn 1 */
-}
- 8000948:	bf00      	nop
- 800094a:	46bd      	mov	sp, r7
- 800094c:	f85d 7b04 	ldr.w	r7, [sp], #4
- 8000950:	4770      	bx	lr
-
-08000952 <PendSV_Handler>:
-
-/**
-  * @brief This function handles Pendable request for system service.
-  */
-void PendSV_Handler(void)
-{
- 8000952:	b480      	push	{r7}
- 8000954:	af00      	add	r7, sp, #0
-
-  /* USER CODE END PendSV_IRQn 0 */
-  /* USER CODE BEGIN PendSV_IRQn 1 */
-
-  /* USER CODE END PendSV_IRQn 1 */
-}
- 8000956:	bf00      	nop
- 8000958:	46bd      	mov	sp, r7
- 800095a:	f85d 7b04 	ldr.w	r7, [sp], #4
- 800095e:	4770      	bx	lr
-
-08000960 <SysTick_Handler>:
-
-/**
-  * @brief This function handles System tick timer.
-  */
-void SysTick_Handler(void)
-{
- 8000960:	b580      	push	{r7, lr}
- 8000962:	af00      	add	r7, sp, #0
-  /* USER CODE BEGIN SysTick_IRQn 0 */
-
-  /* USER CODE END SysTick_IRQn 0 */
-  HAL_IncTick();
- 8000964:	f000 fb3e 	bl	8000fe4 <HAL_IncTick>
-  /* USER CODE BEGIN SysTick_IRQn 1 */
-
-  /* USER CODE END SysTick_IRQn 1 */
-}
- 8000968:	bf00      	nop
- 800096a:	bd80      	pop	{r7, pc}
-
-0800096c <ETH_IRQHandler>:
-
-/**
-  * @brief This function handles Ethernet global interrupt.
-  */
-void ETH_IRQHandler(void)
-{
- 800096c:	b580      	push	{r7, lr}
- 800096e:	af00      	add	r7, sp, #0
-  /* USER CODE BEGIN ETH_IRQn 0 */
-
-  /* USER CODE END ETH_IRQn 0 */
-  HAL_ETH_IRQHandler(&heth);
- 8000970:	4802      	ldr	r0, [pc, #8]	; (800097c <ETH_IRQHandler+0x10>)
- 8000972:	f001 f855 	bl	8001a20 <HAL_ETH_IRQHandler>
-  /* USER CODE BEGIN ETH_IRQn 1 */
-
-  /* USER CODE END ETH_IRQn 1 */
-}
- 8000976:	bf00      	nop
- 8000978:	bd80      	pop	{r7, pc}
- 800097a:	bf00      	nop
- 800097c:	24004b08 	.word	0x24004b08
-
-08000980 <_getpid>:
-void initialise_monitor_handles()
-{
-}
-
-int _getpid(void)
-{
- 8000980:	b480      	push	{r7}
- 8000982:	af00      	add	r7, sp, #0
-  return 1;
- 8000984:	2301      	movs	r3, #1
-}
- 8000986:	4618      	mov	r0, r3
- 8000988:	46bd      	mov	sp, r7
- 800098a:	f85d 7b04 	ldr.w	r7, [sp], #4
- 800098e:	4770      	bx	lr
-
-08000990 <_kill>:
-
-int _kill(int pid, int sig)
-{
- 8000990:	b480      	push	{r7}
- 8000992:	b083      	sub	sp, #12
- 8000994:	af00      	add	r7, sp, #0
- 8000996:	6078      	str	r0, [r7, #4]
- 8000998:	6039      	str	r1, [r7, #0]
-  (void)pid;
-  (void)sig;
-  errno = EINVAL;
- 800099a:	4b05      	ldr	r3, [pc, #20]	; (80009b0 <_kill+0x20>)
- 800099c:	2216      	movs	r2, #22
- 800099e:	601a      	str	r2, [r3, #0]
-  return -1;
- 80009a0:	f04f 33ff 	mov.w	r3, #4294967295
-}
- 80009a4:	4618      	mov	r0, r3
- 80009a6:	370c      	adds	r7, #12
- 80009a8:	46bd      	mov	sp, r7
- 80009aa:	f85d 7b04 	ldr.w	r7, [sp], #4
- 80009ae:	4770      	bx	lr
- 80009b0:	24007e08 	.word	0x24007e08
-
-080009b4 <_exit>:
-
-void _exit (int status)
-{
- 80009b4:	b580      	push	{r7, lr}
- 80009b6:	b082      	sub	sp, #8
- 80009b8:	af00      	add	r7, sp, #0
- 80009ba:	6078      	str	r0, [r7, #4]
-  _kill(status, -1);
- 80009bc:	f04f 31ff 	mov.w	r1, #4294967295
- 80009c0:	6878      	ldr	r0, [r7, #4]
- 80009c2:	f7ff ffe5 	bl	8000990 <_kill>
-  while (1) {}    /* Make sure we hang here */
- 80009c6:	e7fe      	b.n	80009c6 <_exit+0x12>
-
-080009c8 <_read>:
-}
-
-__attribute__((weak)) int _read(int file, char *ptr, int len)
-{
- 80009c8:	b580      	push	{r7, lr}
- 80009ca:	b086      	sub	sp, #24
- 80009cc:	af00      	add	r7, sp, #0
- 80009ce:	60f8      	str	r0, [r7, #12]
- 80009d0:	60b9      	str	r1, [r7, #8]
- 80009d2:	607a      	str	r2, [r7, #4]
-  (void)file;
-  int DataIdx;
-
-  for (DataIdx = 0; DataIdx < len; DataIdx++)
- 80009d4:	2300      	movs	r3, #0
- 80009d6:	617b      	str	r3, [r7, #20]
- 80009d8:	e00a      	b.n	80009f0 <_read+0x28>
-  {
-    *ptr++ = __io_getchar();
- 80009da:	f3af 8000 	nop.w
- 80009de:	4601      	mov	r1, r0
- 80009e0:	68bb      	ldr	r3, [r7, #8]
- 80009e2:	1c5a      	adds	r2, r3, #1
- 80009e4:	60ba      	str	r2, [r7, #8]
- 80009e6:	b2ca      	uxtb	r2, r1
- 80009e8:	701a      	strb	r2, [r3, #0]
-  for (DataIdx = 0; DataIdx < len; DataIdx++)
- 80009ea:	697b      	ldr	r3, [r7, #20]
- 80009ec:	3301      	adds	r3, #1
- 80009ee:	617b      	str	r3, [r7, #20]
- 80009f0:	697a      	ldr	r2, [r7, #20]
- 80009f2:	687b      	ldr	r3, [r7, #4]
- 80009f4:	429a      	cmp	r2, r3
- 80009f6:	dbf0      	blt.n	80009da <_read+0x12>
-  }
-
-  return len;
- 80009f8:	687b      	ldr	r3, [r7, #4]
-}
- 80009fa:	4618      	mov	r0, r3
- 80009fc:	3718      	adds	r7, #24
- 80009fe:	46bd      	mov	sp, r7
- 8000a00:	bd80      	pop	{r7, pc}
-
-08000a02 <_close>:
-  }
-  return len;
-}
-
-int _close(int file)
-{
- 8000a02:	b480      	push	{r7}
- 8000a04:	b083      	sub	sp, #12
- 8000a06:	af00      	add	r7, sp, #0
- 8000a08:	6078      	str	r0, [r7, #4]
-  (void)file;
-  return -1;
- 8000a0a:	f04f 33ff 	mov.w	r3, #4294967295
-}
- 8000a0e:	4618      	mov	r0, r3
- 8000a10:	370c      	adds	r7, #12
- 8000a12:	46bd      	mov	sp, r7
- 8000a14:	f85d 7b04 	ldr.w	r7, [sp], #4
- 8000a18:	4770      	bx	lr
-
-08000a1a <_fstat>:
-
-
-int _fstat(int file, struct stat *st)
-{
- 8000a1a:	b480      	push	{r7}
- 8000a1c:	b083      	sub	sp, #12
- 8000a1e:	af00      	add	r7, sp, #0
- 8000a20:	6078      	str	r0, [r7, #4]
- 8000a22:	6039      	str	r1, [r7, #0]
-  (void)file;
-  st->st_mode = S_IFCHR;
- 8000a24:	683b      	ldr	r3, [r7, #0]
- 8000a26:	f44f 5200 	mov.w	r2, #8192	; 0x2000
- 8000a2a:	605a      	str	r2, [r3, #4]
-  return 0;
- 8000a2c:	2300      	movs	r3, #0
-}
- 8000a2e:	4618      	mov	r0, r3
- 8000a30:	370c      	adds	r7, #12
- 8000a32:	46bd      	mov	sp, r7
- 8000a34:	f85d 7b04 	ldr.w	r7, [sp], #4
- 8000a38:	4770      	bx	lr
-
-08000a3a <_isatty>:
-
-int _isatty(int file)
-{
- 8000a3a:	b480      	push	{r7}
- 8000a3c:	b083      	sub	sp, #12
- 8000a3e:	af00      	add	r7, sp, #0
- 8000a40:	6078      	str	r0, [r7, #4]
-  (void)file;
-  return 1;
- 8000a42:	2301      	movs	r3, #1
-}
- 8000a44:	4618      	mov	r0, r3
- 8000a46:	370c      	adds	r7, #12
- 8000a48:	46bd      	mov	sp, r7
- 8000a4a:	f85d 7b04 	ldr.w	r7, [sp], #4
- 8000a4e:	4770      	bx	lr
-
-08000a50 <_lseek>:
-
-int _lseek(int file, int ptr, int dir)
-{
- 8000a50:	b480      	push	{r7}
- 8000a52:	b085      	sub	sp, #20
- 8000a54:	af00      	add	r7, sp, #0
- 8000a56:	60f8      	str	r0, [r7, #12]
- 8000a58:	60b9      	str	r1, [r7, #8]
- 8000a5a:	607a      	str	r2, [r7, #4]
-  (void)file;
-  (void)ptr;
-  (void)dir;
-  return 0;
- 8000a5c:	2300      	movs	r3, #0
-}
- 8000a5e:	4618      	mov	r0, r3
- 8000a60:	3714      	adds	r7, #20
- 8000a62:	46bd      	mov	sp, r7
- 8000a64:	f85d 7b04 	ldr.w	r7, [sp], #4
- 8000a68:	4770      	bx	lr
-	...
-
-08000a6c <_sbrk>:
- *
- * @param incr Memory size
- * @return Pointer to allocated memory
- */
-void *_sbrk(ptrdiff_t incr)
-{
- 8000a6c:	b480      	push	{r7}
- 8000a6e:	b087      	sub	sp, #28
- 8000a70:	af00      	add	r7, sp, #0
- 8000a72:	6078      	str	r0, [r7, #4]
-  extern uint8_t _end; /* Symbol defined in the linker script */
-  extern uint8_t _estack; /* Symbol defined in the linker script */
-  extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */
-  const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size;
- 8000a74:	4a14      	ldr	r2, [pc, #80]	; (8000ac8 <_sbrk+0x5c>)
- 8000a76:	4b15      	ldr	r3, [pc, #84]	; (8000acc <_sbrk+0x60>)
- 8000a78:	1ad3      	subs	r3, r2, r3
- 8000a7a:	617b      	str	r3, [r7, #20]
-  const uint8_t *max_heap = (uint8_t *)stack_limit;
- 8000a7c:	697b      	ldr	r3, [r7, #20]
- 8000a7e:	613b      	str	r3, [r7, #16]
-  uint8_t *prev_heap_end;
-
-  /* Initialize heap end at first call */
-  if (NULL == __sbrk_heap_end)
- 8000a80:	4b13      	ldr	r3, [pc, #76]	; (8000ad0 <_sbrk+0x64>)
- 8000a82:	681b      	ldr	r3, [r3, #0]
- 8000a84:	2b00      	cmp	r3, #0
- 8000a86:	d102      	bne.n	8000a8e <_sbrk+0x22>
-  {
-    __sbrk_heap_end = &_end;
- 8000a88:	4b11      	ldr	r3, [pc, #68]	; (8000ad0 <_sbrk+0x64>)
- 8000a8a:	4a12      	ldr	r2, [pc, #72]	; (8000ad4 <_sbrk+0x68>)
- 8000a8c:	601a      	str	r2, [r3, #0]
-  }
-
-  /* Protect heap from growing into the reserved MSP stack */
-  if (__sbrk_heap_end + incr > max_heap)
- 8000a8e:	4b10      	ldr	r3, [pc, #64]	; (8000ad0 <_sbrk+0x64>)
- 8000a90:	681a      	ldr	r2, [r3, #0]
- 8000a92:	687b      	ldr	r3, [r7, #4]
- 8000a94:	4413      	add	r3, r2
- 8000a96:	693a      	ldr	r2, [r7, #16]
- 8000a98:	429a      	cmp	r2, r3
- 8000a9a:	d205      	bcs.n	8000aa8 <_sbrk+0x3c>
-  {
-    errno = ENOMEM;
- 8000a9c:	4b0e      	ldr	r3, [pc, #56]	; (8000ad8 <_sbrk+0x6c>)
- 8000a9e:	220c      	movs	r2, #12
- 8000aa0:	601a      	str	r2, [r3, #0]
-    return (void *)-1;
- 8000aa2:	f04f 33ff 	mov.w	r3, #4294967295
- 8000aa6:	e009      	b.n	8000abc <_sbrk+0x50>
-  }
-
-  prev_heap_end = __sbrk_heap_end;
- 8000aa8:	4b09      	ldr	r3, [pc, #36]	; (8000ad0 <_sbrk+0x64>)
- 8000aaa:	681b      	ldr	r3, [r3, #0]
- 8000aac:	60fb      	str	r3, [r7, #12]
-  __sbrk_heap_end += incr;
- 8000aae:	4b08      	ldr	r3, [pc, #32]	; (8000ad0 <_sbrk+0x64>)
- 8000ab0:	681a      	ldr	r2, [r3, #0]
- 8000ab2:	687b      	ldr	r3, [r7, #4]
- 8000ab4:	4413      	add	r3, r2
- 8000ab6:	4a06      	ldr	r2, [pc, #24]	; (8000ad0 <_sbrk+0x64>)
- 8000ab8:	6013      	str	r3, [r2, #0]
-
-  return (void *)prev_heap_end;
- 8000aba:	68fb      	ldr	r3, [r7, #12]
-}
- 8000abc:	4618      	mov	r0, r3
- 8000abe:	371c      	adds	r7, #28
- 8000ac0:	46bd      	mov	sp, r7
- 8000ac2:	f85d 7b04 	ldr.w	r7, [sp], #4
- 8000ac6:	4770      	bx	lr
- 8000ac8:	24050000 	.word	0x24050000
- 8000acc:	00000400 	.word	0x00000400
- 8000ad0:	24000124 	.word	0x24000124
- 8000ad4:	24007e18 	.word	0x24007e18
- 8000ad8:	24007e08 	.word	0x24007e08
-
-08000adc <SystemInit>:
-  *         configuration.
-  * @param  None
-  * @retval None
-  */
-void SystemInit (void)
-{
- 8000adc:	b480      	push	{r7}
- 8000ade:	b083      	sub	sp, #12
- 8000ae0:	af00      	add	r7, sp, #0
- __IO uint32_t tmpreg;
-#endif /* DATA_IN_D2_SRAM */
-
-  /* FPU settings ------------------------------------------------------------*/
-  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
-    SCB->CPACR |= ((3UL << (10*2))|(3UL << (11*2)));  /* set CP10 and CP11 Full Access */
- 8000ae2:	4b3a      	ldr	r3, [pc, #232]	; (8000bcc <SystemInit+0xf0>)
- 8000ae4:	f8d3 3088 	ldr.w	r3, [r3, #136]	; 0x88
- 8000ae8:	4a38      	ldr	r2, [pc, #224]	; (8000bcc <SystemInit+0xf0>)
- 8000aea:	f443 0370 	orr.w	r3, r3, #15728640	; 0xf00000
- 8000aee:	f8c2 3088 	str.w	r3, [r2, #136]	; 0x88
-  #endif
-  /* Reset the RCC clock configuration to the default reset state ------------*/
-
-   /* Increasing the CPU frequency */
-  if(FLASH_LATENCY_DEFAULT  > (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)))
- 8000af2:	4b37      	ldr	r3, [pc, #220]	; (8000bd0 <SystemInit+0xf4>)
- 8000af4:	681b      	ldr	r3, [r3, #0]
- 8000af6:	f003 030f 	and.w	r3, r3, #15
- 8000afa:	2b06      	cmp	r3, #6
- 8000afc:	d807      	bhi.n	8000b0e <SystemInit+0x32>
-  {
-    /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
-    MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT));
- 8000afe:	4b34      	ldr	r3, [pc, #208]	; (8000bd0 <SystemInit+0xf4>)
- 8000b00:	681b      	ldr	r3, [r3, #0]
- 8000b02:	f023 030f 	bic.w	r3, r3, #15
- 8000b06:	4a32      	ldr	r2, [pc, #200]	; (8000bd0 <SystemInit+0xf4>)
- 8000b08:	f043 0307 	orr.w	r3, r3, #7
- 8000b0c:	6013      	str	r3, [r2, #0]
-  }
-
-  /* Set HSION bit */
-  RCC->CR |= RCC_CR_HSION;
- 8000b0e:	4b31      	ldr	r3, [pc, #196]	; (8000bd4 <SystemInit+0xf8>)
- 8000b10:	681b      	ldr	r3, [r3, #0]
- 8000b12:	4a30      	ldr	r2, [pc, #192]	; (8000bd4 <SystemInit+0xf8>)
- 8000b14:	f043 0301 	orr.w	r3, r3, #1
- 8000b18:	6013      	str	r3, [r2, #0]
-
-  /* Reset CFGR register */
-  RCC->CFGR = 0x00000000;
- 8000b1a:	4b2e      	ldr	r3, [pc, #184]	; (8000bd4 <SystemInit+0xf8>)
- 8000b1c:	2200      	movs	r2, #0
- 8000b1e:	611a      	str	r2, [r3, #16]
-
-  /* Reset HSEON, HSECSSON, CSION, HSI48ON, CSIKERON, PLL1ON, PLL2ON and PLL3ON bits */
-  RCC->CR &= 0xEAF6ED7FU;
- 8000b20:	4b2c      	ldr	r3, [pc, #176]	; (8000bd4 <SystemInit+0xf8>)
- 8000b22:	681a      	ldr	r2, [r3, #0]
- 8000b24:	492b      	ldr	r1, [pc, #172]	; (8000bd4 <SystemInit+0xf8>)
- 8000b26:	4b2c      	ldr	r3, [pc, #176]	; (8000bd8 <SystemInit+0xfc>)
- 8000b28:	4013      	ands	r3, r2
- 8000b2a:	600b      	str	r3, [r1, #0]
-
-   /* Decreasing the number of wait states because of lower CPU frequency */
-  if(FLASH_LATENCY_DEFAULT  < (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)))
- 8000b2c:	4b28      	ldr	r3, [pc, #160]	; (8000bd0 <SystemInit+0xf4>)
- 8000b2e:	681b      	ldr	r3, [r3, #0]
- 8000b30:	f003 0308 	and.w	r3, r3, #8
- 8000b34:	2b00      	cmp	r3, #0
- 8000b36:	d007      	beq.n	8000b48 <SystemInit+0x6c>
-  {
-    /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
-    MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT));
- 8000b38:	4b25      	ldr	r3, [pc, #148]	; (8000bd0 <SystemInit+0xf4>)
- 8000b3a:	681b      	ldr	r3, [r3, #0]
- 8000b3c:	f023 030f 	bic.w	r3, r3, #15
- 8000b40:	4a23      	ldr	r2, [pc, #140]	; (8000bd0 <SystemInit+0xf4>)
- 8000b42:	f043 0307 	orr.w	r3, r3, #7
- 8000b46:	6013      	str	r3, [r2, #0]
-  }
-
-#if defined(D3_SRAM_BASE)
-  /* Reset D1CFGR register */
-  RCC->D1CFGR = 0x00000000;
- 8000b48:	4b22      	ldr	r3, [pc, #136]	; (8000bd4 <SystemInit+0xf8>)
- 8000b4a:	2200      	movs	r2, #0
- 8000b4c:	619a      	str	r2, [r3, #24]
-
-  /* Reset D2CFGR register */
-  RCC->D2CFGR = 0x00000000;
- 8000b4e:	4b21      	ldr	r3, [pc, #132]	; (8000bd4 <SystemInit+0xf8>)
- 8000b50:	2200      	movs	r2, #0
- 8000b52:	61da      	str	r2, [r3, #28]
-
-  /* Reset D3CFGR register */
-  RCC->D3CFGR = 0x00000000;
- 8000b54:	4b1f      	ldr	r3, [pc, #124]	; (8000bd4 <SystemInit+0xf8>)
- 8000b56:	2200      	movs	r2, #0
- 8000b58:	621a      	str	r2, [r3, #32]
-
-  /* Reset SRDCFGR register */
-  RCC->SRDCFGR = 0x00000000;
-#endif
-  /* Reset PLLCKSELR register */
-  RCC->PLLCKSELR = 0x02020200;
- 8000b5a:	4b1e      	ldr	r3, [pc, #120]	; (8000bd4 <SystemInit+0xf8>)
- 8000b5c:	4a1f      	ldr	r2, [pc, #124]	; (8000bdc <SystemInit+0x100>)
- 8000b5e:	629a      	str	r2, [r3, #40]	; 0x28
-
-  /* Reset PLLCFGR register */
-  RCC->PLLCFGR = 0x01FF0000;
- 8000b60:	4b1c      	ldr	r3, [pc, #112]	; (8000bd4 <SystemInit+0xf8>)
- 8000b62:	4a1f      	ldr	r2, [pc, #124]	; (8000be0 <SystemInit+0x104>)
- 8000b64:	62da      	str	r2, [r3, #44]	; 0x2c
-  /* Reset PLL1DIVR register */
-  RCC->PLL1DIVR = 0x01010280;
- 8000b66:	4b1b      	ldr	r3, [pc, #108]	; (8000bd4 <SystemInit+0xf8>)
- 8000b68:	4a1e      	ldr	r2, [pc, #120]	; (8000be4 <SystemInit+0x108>)
- 8000b6a:	631a      	str	r2, [r3, #48]	; 0x30
-  /* Reset PLL1FRACR register */
-  RCC->PLL1FRACR = 0x00000000;
- 8000b6c:	4b19      	ldr	r3, [pc, #100]	; (8000bd4 <SystemInit+0xf8>)
- 8000b6e:	2200      	movs	r2, #0
- 8000b70:	635a      	str	r2, [r3, #52]	; 0x34
-
-  /* Reset PLL2DIVR register */
-  RCC->PLL2DIVR = 0x01010280;
- 8000b72:	4b18      	ldr	r3, [pc, #96]	; (8000bd4 <SystemInit+0xf8>)
- 8000b74:	4a1b      	ldr	r2, [pc, #108]	; (8000be4 <SystemInit+0x108>)
- 8000b76:	639a      	str	r2, [r3, #56]	; 0x38
-
-  /* Reset PLL2FRACR register */
-
-  RCC->PLL2FRACR = 0x00000000;
- 8000b78:	4b16      	ldr	r3, [pc, #88]	; (8000bd4 <SystemInit+0xf8>)
- 8000b7a:	2200      	movs	r2, #0
- 8000b7c:	63da      	str	r2, [r3, #60]	; 0x3c
-  /* Reset PLL3DIVR register */
-  RCC->PLL3DIVR = 0x01010280;
- 8000b7e:	4b15      	ldr	r3, [pc, #84]	; (8000bd4 <SystemInit+0xf8>)
- 8000b80:	4a18      	ldr	r2, [pc, #96]	; (8000be4 <SystemInit+0x108>)
- 8000b82:	641a      	str	r2, [r3, #64]	; 0x40
-
-  /* Reset PLL3FRACR register */
-  RCC->PLL3FRACR = 0x00000000;
- 8000b84:	4b13      	ldr	r3, [pc, #76]	; (8000bd4 <SystemInit+0xf8>)
- 8000b86:	2200      	movs	r2, #0
- 8000b88:	645a      	str	r2, [r3, #68]	; 0x44
-
-  /* Reset HSEBYP bit */
-  RCC->CR &= 0xFFFBFFFFU;
- 8000b8a:	4b12      	ldr	r3, [pc, #72]	; (8000bd4 <SystemInit+0xf8>)
- 8000b8c:	681b      	ldr	r3, [r3, #0]
- 8000b8e:	4a11      	ldr	r2, [pc, #68]	; (8000bd4 <SystemInit+0xf8>)
- 8000b90:	f423 2380 	bic.w	r3, r3, #262144	; 0x40000
- 8000b94:	6013      	str	r3, [r2, #0]
-
-  /* Disable all interrupts */
-  RCC->CIER = 0x00000000;
- 8000b96:	4b0f      	ldr	r3, [pc, #60]	; (8000bd4 <SystemInit+0xf8>)
- 8000b98:	2200      	movs	r2, #0
- 8000b9a:	661a      	str	r2, [r3, #96]	; 0x60
-#if defined(DATA_IN_D2_SRAM)
-  /* in case of initialized data in D2 SRAM (AHB SRAM), enable the D2 SRAM clock (AHB SRAM clock) */
-#if defined(RCC_AHB2ENR_D2SRAM3EN)
-  RCC->AHB2ENR |= (RCC_AHB2ENR_D2SRAM1EN | RCC_AHB2ENR_D2SRAM2EN | RCC_AHB2ENR_D2SRAM3EN);
-#elif defined(RCC_AHB2ENR_D2SRAM2EN)
-  RCC->AHB2ENR |= (RCC_AHB2ENR_D2SRAM1EN | RCC_AHB2ENR_D2SRAM2EN);
- 8000b9c:	4b0d      	ldr	r3, [pc, #52]	; (8000bd4 <SystemInit+0xf8>)
- 8000b9e:	f8d3 30dc 	ldr.w	r3, [r3, #220]	; 0xdc
- 8000ba2:	4a0c      	ldr	r2, [pc, #48]	; (8000bd4 <SystemInit+0xf8>)
- 8000ba4:	f043 43c0 	orr.w	r3, r3, #1610612736	; 0x60000000
- 8000ba8:	f8c2 30dc 	str.w	r3, [r2, #220]	; 0xdc
-#else
-  RCC->AHB2ENR |= (RCC_AHB2ENR_AHBSRAM1EN | RCC_AHB2ENR_AHBSRAM2EN);
-#endif /* RCC_AHB2ENR_D2SRAM3EN */
-
-  tmpreg = RCC->AHB2ENR;
- 8000bac:	4b09      	ldr	r3, [pc, #36]	; (8000bd4 <SystemInit+0xf8>)
- 8000bae:	f8d3 30dc 	ldr.w	r3, [r3, #220]	; 0xdc
- 8000bb2:	607b      	str	r3, [r7, #4]
-  (void) tmpreg;
- 8000bb4:	687b      	ldr	r3, [r7, #4]
-  /*
-   * Disable the FMC bank1 (enabled after reset).
-   * This, prevents CPU speculation access on this bank which blocks the use of FMC during
-   * 24us. During this time the others FMC master (such as LTDC) cannot use it!
-   */
-  FMC_Bank1_R->BTCR[0] = 0x000030D2;
- 8000bb6:	4b0c      	ldr	r3, [pc, #48]	; (8000be8 <SystemInit+0x10c>)
- 8000bb8:	f243 02d2 	movw	r2, #12498	; 0x30d2
- 8000bbc:	601a      	str	r2, [r3, #0]
-#if defined(USER_VECT_TAB_ADDRESS)
-  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal D1 AXI-RAM or in Internal FLASH */
-#endif /* USER_VECT_TAB_ADDRESS */
-
-#endif /*DUAL_CORE && CORE_CM4*/
-}
- 8000bbe:	bf00      	nop
- 8000bc0:	370c      	adds	r7, #12
- 8000bc2:	46bd      	mov	sp, r7
- 8000bc4:	f85d 7b04 	ldr.w	r7, [sp], #4
- 8000bc8:	4770      	bx	lr
- 8000bca:	bf00      	nop
- 8000bcc:	e000ed00 	.word	0xe000ed00
- 8000bd0:	52002000 	.word	0x52002000
- 8000bd4:	58024400 	.word	0x58024400
- 8000bd8:	eaf6ed7f 	.word	0xeaf6ed7f
- 8000bdc:	02020200 	.word	0x02020200
- 8000be0:	01ff0000 	.word	0x01ff0000
- 8000be4:	01010280 	.word	0x01010280
- 8000be8:	52004000 	.word	0x52004000
-
-08000bec <Reset_Handler>:
-
-    .section  .text.Reset_Handler
-  .weak  Reset_Handler
-  .type  Reset_Handler, %function
-Reset_Handler:
-  ldr   sp, =_estack      /* set stack pointer */
- 8000bec:	f8df d034 	ldr.w	sp, [pc, #52]	; 8000c24 <LoopFillZerobss+0xe>
-
-/* Call the clock system initialization function.*/
-  bl  SystemInit
- 8000bf0:	f7ff ff74 	bl	8000adc <SystemInit>
-
-/* Copy the data segment initializers from flash to SRAM */
-  ldr r0, =_sdata
- 8000bf4:	480c      	ldr	r0, [pc, #48]	; (8000c28 <LoopFillZerobss+0x12>)
-  ldr r1, =_edata
- 8000bf6:	490d      	ldr	r1, [pc, #52]	; (8000c2c <LoopFillZerobss+0x16>)
-  ldr r2, =_sidata
- 8000bf8:	4a0d      	ldr	r2, [pc, #52]	; (8000c30 <LoopFillZerobss+0x1a>)
-  movs r3, #0
- 8000bfa:	2300      	movs	r3, #0
-  b LoopCopyDataInit
- 8000bfc:	e002      	b.n	8000c04 <LoopCopyDataInit>
-
-08000bfe <CopyDataInit>:
-
-CopyDataInit:
-  ldr r4, [r2, r3]
- 8000bfe:	58d4      	ldr	r4, [r2, r3]
-  str r4, [r0, r3]
- 8000c00:	50c4      	str	r4, [r0, r3]
-  adds r3, r3, #4
- 8000c02:	3304      	adds	r3, #4
-
-08000c04 <LoopCopyDataInit>:
-
-LoopCopyDataInit:
-  adds r4, r0, r3
- 8000c04:	18c4      	adds	r4, r0, r3
-  cmp r4, r1
- 8000c06:	428c      	cmp	r4, r1
-  bcc CopyDataInit
- 8000c08:	d3f9      	bcc.n	8000bfe <CopyDataInit>
-/* Zero fill the bss segment. */
-  ldr r2, =_sbss
- 8000c0a:	4a0a      	ldr	r2, [pc, #40]	; (8000c34 <LoopFillZerobss+0x1e>)
-  ldr r4, =_ebss
- 8000c0c:	4c0a      	ldr	r4, [pc, #40]	; (8000c38 <LoopFillZerobss+0x22>)
-  movs r3, #0
- 8000c0e:	2300      	movs	r3, #0
-  b LoopFillZerobss
- 8000c10:	e001      	b.n	8000c16 <LoopFillZerobss>
-
-08000c12 <FillZerobss>:
-
-FillZerobss:
-  str  r3, [r2]
- 8000c12:	6013      	str	r3, [r2, #0]
-  adds r2, r2, #4
- 8000c14:	3204      	adds	r2, #4
-
-08000c16 <LoopFillZerobss>:
-
-LoopFillZerobss:
-  cmp r2, r4
- 8000c16:	42a2      	cmp	r2, r4
-  bcc FillZerobss
- 8000c18:	d3fb      	bcc.n	8000c12 <FillZerobss>
-
-/* Call static constructors */
-    bl __libc_init_array
- 8000c1a:	f010 f98f 	bl	8010f3c <__libc_init_array>
-/* Call the application's entry point.*/
-  bl  main
- 8000c1e:	f7ff fce1 	bl	80005e4 <main>
-  bx  lr
- 8000c22:	4770      	bx	lr
-  ldr   sp, =_estack      /* set stack pointer */
- 8000c24:	24050000 	.word	0x24050000
-  ldr r0, =_sdata
- 8000c28:	24000000 	.word	0x24000000
-  ldr r1, =_edata
- 8000c2c:	240000d0 	.word	0x240000d0
-  ldr r2, =_sidata
- 8000c30:	08014f90 	.word	0x08014f90
-  ldr r2, =_sbss
- 8000c34:	240000d0 	.word	0x240000d0
-  ldr r4, =_ebss
- 8000c38:	24007e18 	.word	0x24007e18
-
-08000c3c <ADC3_IRQHandler>:
- * @retval None
-*/
-    .section  .text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
-  b  Infinite_Loop
- 8000c3c:	e7fe      	b.n	8000c3c <ADC3_IRQHandler>
-
-08000c3e <LAN8742_RegisterBusIO>:
-  * @param  ioctx: holds device IO functions.  
-  * @retval LAN8742_STATUS_OK  if OK
-  *         LAN8742_STATUS_ERROR if missing mandatory function
-  */
-int32_t  LAN8742_RegisterBusIO(lan8742_Object_t *pObj, lan8742_IOCtx_t *ioctx)
-{
- 8000c3e:	b480      	push	{r7}
- 8000c40:	b083      	sub	sp, #12
- 8000c42:	af00      	add	r7, sp, #0
- 8000c44:	6078      	str	r0, [r7, #4]
- 8000c46:	6039      	str	r1, [r7, #0]
-  if(!pObj || !ioctx->ReadReg || !ioctx->WriteReg || !ioctx->GetTick)
- 8000c48:	687b      	ldr	r3, [r7, #4]
- 8000c4a:	2b00      	cmp	r3, #0
- 8000c4c:	d00b      	beq.n	8000c66 <LAN8742_RegisterBusIO+0x28>
- 8000c4e:	683b      	ldr	r3, [r7, #0]
- 8000c50:	68db      	ldr	r3, [r3, #12]
- 8000c52:	2b00      	cmp	r3, #0
- 8000c54:	d007      	beq.n	8000c66 <LAN8742_RegisterBusIO+0x28>
- 8000c56:	683b      	ldr	r3, [r7, #0]
- 8000c58:	689b      	ldr	r3, [r3, #8]
- 8000c5a:	2b00      	cmp	r3, #0
- 8000c5c:	d003      	beq.n	8000c66 <LAN8742_RegisterBusIO+0x28>
- 8000c5e:	683b      	ldr	r3, [r7, #0]
- 8000c60:	691b      	ldr	r3, [r3, #16]
- 8000c62:	2b00      	cmp	r3, #0
- 8000c64:	d102      	bne.n	8000c6c <LAN8742_RegisterBusIO+0x2e>
-  {
-    return LAN8742_STATUS_ERROR;
- 8000c66:	f04f 33ff 	mov.w	r3, #4294967295
- 8000c6a:	e014      	b.n	8000c96 <LAN8742_RegisterBusIO+0x58>
-  }
-  
-  pObj->IO.Init = ioctx->Init;
- 8000c6c:	683b      	ldr	r3, [r7, #0]
- 8000c6e:	681a      	ldr	r2, [r3, #0]
- 8000c70:	687b      	ldr	r3, [r7, #4]
- 8000c72:	609a      	str	r2, [r3, #8]
-  pObj->IO.DeInit = ioctx->DeInit;
- 8000c74:	683b      	ldr	r3, [r7, #0]
- 8000c76:	685a      	ldr	r2, [r3, #4]
- 8000c78:	687b      	ldr	r3, [r7, #4]
- 8000c7a:	60da      	str	r2, [r3, #12]
-  pObj->IO.ReadReg = ioctx->ReadReg;
- 8000c7c:	683b      	ldr	r3, [r7, #0]
- 8000c7e:	68da      	ldr	r2, [r3, #12]
- 8000c80:	687b      	ldr	r3, [r7, #4]
- 8000c82:	615a      	str	r2, [r3, #20]
-  pObj->IO.WriteReg = ioctx->WriteReg;
- 8000c84:	683b      	ldr	r3, [r7, #0]
- 8000c86:	689a      	ldr	r2, [r3, #8]
- 8000c88:	687b      	ldr	r3, [r7, #4]
- 8000c8a:	611a      	str	r2, [r3, #16]
-  pObj->IO.GetTick = ioctx->GetTick;
- 8000c8c:	683b      	ldr	r3, [r7, #0]
- 8000c8e:	691a      	ldr	r2, [r3, #16]
- 8000c90:	687b      	ldr	r3, [r7, #4]
- 8000c92:	619a      	str	r2, [r3, #24]
-  
-  return LAN8742_STATUS_OK;
- 8000c94:	2300      	movs	r3, #0
-}
- 8000c96:	4618      	mov	r0, r3
- 8000c98:	370c      	adds	r7, #12
- 8000c9a:	46bd      	mov	sp, r7
- 8000c9c:	f85d 7b04 	ldr.w	r7, [sp], #4
- 8000ca0:	4770      	bx	lr
-
-08000ca2 <LAN8742_Init>:
-  *         LAN8742_STATUS_READ_ERROR if connot read register
-  *         LAN8742_STATUS_WRITE_ERROR if connot write to register
-  *         LAN8742_STATUS_RESET_TIMEOUT if cannot perform a software reset
-  */
- int32_t LAN8742_Init(lan8742_Object_t *pObj)
- {
- 8000ca2:	b580      	push	{r7, lr}
- 8000ca4:	b086      	sub	sp, #24
- 8000ca6:	af00      	add	r7, sp, #0
- 8000ca8:	6078      	str	r0, [r7, #4]
-   uint32_t tickstart = 0, regvalue = 0, addr = 0;
- 8000caa:	2300      	movs	r3, #0
- 8000cac:	60fb      	str	r3, [r7, #12]
- 8000cae:	2300      	movs	r3, #0
- 8000cb0:	60bb      	str	r3, [r7, #8]
- 8000cb2:	2300      	movs	r3, #0
- 8000cb4:	617b      	str	r3, [r7, #20]
-   int32_t status = LAN8742_STATUS_OK;
- 8000cb6:	2300      	movs	r3, #0
- 8000cb8:	613b      	str	r3, [r7, #16]
-   
-   if(pObj->Is_Initialized == 0)
- 8000cba:	687b      	ldr	r3, [r7, #4]
- 8000cbc:	685b      	ldr	r3, [r3, #4]
- 8000cbe:	2b00      	cmp	r3, #0
- 8000cc0:	d17c      	bne.n	8000dbc <LAN8742_Init+0x11a>
-   {
-     if(pObj->IO.Init != 0)
- 8000cc2:	687b      	ldr	r3, [r7, #4]
- 8000cc4:	689b      	ldr	r3, [r3, #8]
- 8000cc6:	2b00      	cmp	r3, #0
- 8000cc8:	d002      	beq.n	8000cd0 <LAN8742_Init+0x2e>
-     {
-       /* GPIO and Clocks initialization */
-       pObj->IO.Init();
- 8000cca:	687b      	ldr	r3, [r7, #4]
- 8000ccc:	689b      	ldr	r3, [r3, #8]
- 8000cce:	4798      	blx	r3
-     }
-   
-     /* for later check */
-     pObj->DevAddr = LAN8742_MAX_DEV_ADDR + 1;
- 8000cd0:	687b      	ldr	r3, [r7, #4]
- 8000cd2:	2220      	movs	r2, #32
- 8000cd4:	601a      	str	r2, [r3, #0]
-   
-     /* Get the device address from special mode register */  
-     for(addr = 0; addr <= LAN8742_MAX_DEV_ADDR; addr ++)
- 8000cd6:	2300      	movs	r3, #0
- 8000cd8:	617b      	str	r3, [r7, #20]
- 8000cda:	e01c      	b.n	8000d16 <LAN8742_Init+0x74>
-     {
-       if(pObj->IO.ReadReg(addr, LAN8742_SMR, &regvalue) < 0)
- 8000cdc:	687b      	ldr	r3, [r7, #4]
- 8000cde:	695b      	ldr	r3, [r3, #20]
- 8000ce0:	f107 0208 	add.w	r2, r7, #8
- 8000ce4:	2112      	movs	r1, #18
- 8000ce6:	6978      	ldr	r0, [r7, #20]
- 8000ce8:	4798      	blx	r3
- 8000cea:	4603      	mov	r3, r0
- 8000cec:	2b00      	cmp	r3, #0
- 8000cee:	da03      	bge.n	8000cf8 <LAN8742_Init+0x56>
-       { 
-         status = LAN8742_STATUS_READ_ERROR;
- 8000cf0:	f06f 0304 	mvn.w	r3, #4
- 8000cf4:	613b      	str	r3, [r7, #16]
-         /* Can't read from this device address 
-            continue with next address */
-         continue;
- 8000cf6:	e00b      	b.n	8000d10 <LAN8742_Init+0x6e>
-       }
-     
-       if((regvalue & LAN8742_SMR_PHY_ADDR) == addr)
- 8000cf8:	68bb      	ldr	r3, [r7, #8]
- 8000cfa:	f003 031f 	and.w	r3, r3, #31
- 8000cfe:	697a      	ldr	r2, [r7, #20]
- 8000d00:	429a      	cmp	r2, r3
- 8000d02:	d105      	bne.n	8000d10 <LAN8742_Init+0x6e>
-       {
-         pObj->DevAddr = addr;
- 8000d04:	687b      	ldr	r3, [r7, #4]
- 8000d06:	697a      	ldr	r2, [r7, #20]
- 8000d08:	601a      	str	r2, [r3, #0]
-         status = LAN8742_STATUS_OK;
- 8000d0a:	2300      	movs	r3, #0
- 8000d0c:	613b      	str	r3, [r7, #16]
-         break;
- 8000d0e:	e005      	b.n	8000d1c <LAN8742_Init+0x7a>
-     for(addr = 0; addr <= LAN8742_MAX_DEV_ADDR; addr ++)
- 8000d10:	697b      	ldr	r3, [r7, #20]
- 8000d12:	3301      	adds	r3, #1
- 8000d14:	617b      	str	r3, [r7, #20]
- 8000d16:	697b      	ldr	r3, [r7, #20]
- 8000d18:	2b1f      	cmp	r3, #31
- 8000d1a:	d9df      	bls.n	8000cdc <LAN8742_Init+0x3a>
-       }
-     }
-   
-     if(pObj->DevAddr > LAN8742_MAX_DEV_ADDR)
- 8000d1c:	687b      	ldr	r3, [r7, #4]
- 8000d1e:	681b      	ldr	r3, [r3, #0]
- 8000d20:	2b1f      	cmp	r3, #31
- 8000d22:	d902      	bls.n	8000d2a <LAN8742_Init+0x88>
-     {
-       status = LAN8742_STATUS_ADDRESS_ERROR;
- 8000d24:	f06f 0302 	mvn.w	r3, #2
- 8000d28:	613b      	str	r3, [r7, #16]
-     }
-     
-     /* if device address is matched */
-     if(status == LAN8742_STATUS_OK)
- 8000d2a:	693b      	ldr	r3, [r7, #16]
- 8000d2c:	2b00      	cmp	r3, #0
- 8000d2e:	d145      	bne.n	8000dbc <LAN8742_Init+0x11a>
-     {
-       /* set a software reset  */
-       if(pObj->IO.WriteReg(pObj->DevAddr, LAN8742_BCR, LAN8742_BCR_SOFT_RESET) >= 0)
- 8000d30:	687b      	ldr	r3, [r7, #4]
- 8000d32:	691b      	ldr	r3, [r3, #16]
- 8000d34:	687a      	ldr	r2, [r7, #4]
- 8000d36:	6810      	ldr	r0, [r2, #0]
- 8000d38:	f44f 4200 	mov.w	r2, #32768	; 0x8000
- 8000d3c:	2100      	movs	r1, #0
- 8000d3e:	4798      	blx	r3
- 8000d40:	4603      	mov	r3, r0
- 8000d42:	2b00      	cmp	r3, #0
- 8000d44:	db37      	blt.n	8000db6 <LAN8742_Init+0x114>
-       { 
-         /* get software reset status */
-         if(pObj->IO.ReadReg(pObj->DevAddr, LAN8742_BCR, &regvalue) >= 0)
- 8000d46:	687b      	ldr	r3, [r7, #4]
- 8000d48:	695b      	ldr	r3, [r3, #20]
- 8000d4a:	687a      	ldr	r2, [r7, #4]
- 8000d4c:	6810      	ldr	r0, [r2, #0]
- 8000d4e:	f107 0208 	add.w	r2, r7, #8
- 8000d52:	2100      	movs	r1, #0
- 8000d54:	4798      	blx	r3
- 8000d56:	4603      	mov	r3, r0
- 8000d58:	2b00      	cmp	r3, #0
- 8000d5a:	db28      	blt.n	8000dae <LAN8742_Init+0x10c>
-         { 
-           tickstart = pObj->IO.GetTick();
- 8000d5c:	687b      	ldr	r3, [r7, #4]
- 8000d5e:	699b      	ldr	r3, [r3, #24]
- 8000d60:	4798      	blx	r3
- 8000d62:	4603      	mov	r3, r0
- 8000d64:	60fb      	str	r3, [r7, #12]
-           
-           /* wait until software reset is done or timeout occured  */
-           while(regvalue & LAN8742_BCR_SOFT_RESET)
- 8000d66:	e01c      	b.n	8000da2 <LAN8742_Init+0x100>
-           {
-             if((pObj->IO.GetTick() - tickstart) <= LAN8742_SW_RESET_TO)
- 8000d68:	687b      	ldr	r3, [r7, #4]
- 8000d6a:	699b      	ldr	r3, [r3, #24]
- 8000d6c:	4798      	blx	r3
- 8000d6e:	4603      	mov	r3, r0
- 8000d70:	461a      	mov	r2, r3
- 8000d72:	68fb      	ldr	r3, [r7, #12]
- 8000d74:	1ad3      	subs	r3, r2, r3
- 8000d76:	f5b3 7ffa 	cmp.w	r3, #500	; 0x1f4
- 8000d7a:	d80e      	bhi.n	8000d9a <LAN8742_Init+0xf8>
-             {
-               if(pObj->IO.ReadReg(pObj->DevAddr, LAN8742_BCR, &regvalue) < 0)
- 8000d7c:	687b      	ldr	r3, [r7, #4]
- 8000d7e:	695b      	ldr	r3, [r3, #20]
- 8000d80:	687a      	ldr	r2, [r7, #4]
- 8000d82:	6810      	ldr	r0, [r2, #0]
- 8000d84:	f107 0208 	add.w	r2, r7, #8
- 8000d88:	2100      	movs	r1, #0
- 8000d8a:	4798      	blx	r3
- 8000d8c:	4603      	mov	r3, r0
- 8000d8e:	2b00      	cmp	r3, #0
- 8000d90:	da07      	bge.n	8000da2 <LAN8742_Init+0x100>
-               { 
-                 status = LAN8742_STATUS_READ_ERROR;
- 8000d92:	f06f 0304 	mvn.w	r3, #4
- 8000d96:	613b      	str	r3, [r7, #16]
-                 break;
- 8000d98:	e010      	b.n	8000dbc <LAN8742_Init+0x11a>
-               }
-             }
-             else
-             {
-               status = LAN8742_STATUS_RESET_TIMEOUT;
- 8000d9a:	f06f 0301 	mvn.w	r3, #1
- 8000d9e:	613b      	str	r3, [r7, #16]
-               break;
- 8000da0:	e00c      	b.n	8000dbc <LAN8742_Init+0x11a>
-           while(regvalue & LAN8742_BCR_SOFT_RESET)
- 8000da2:	68bb      	ldr	r3, [r7, #8]
- 8000da4:	f403 4300 	and.w	r3, r3, #32768	; 0x8000
- 8000da8:	2b00      	cmp	r3, #0
- 8000daa:	d1dd      	bne.n	8000d68 <LAN8742_Init+0xc6>
- 8000dac:	e006      	b.n	8000dbc <LAN8742_Init+0x11a>
-             }
-           } 
-         }
-         else
-         {
-           status = LAN8742_STATUS_READ_ERROR;
- 8000dae:	f06f 0304 	mvn.w	r3, #4
- 8000db2:	613b      	str	r3, [r7, #16]
- 8000db4:	e002      	b.n	8000dbc <LAN8742_Init+0x11a>
-         }
-       }
-       else
-       {
-         status = LAN8742_STATUS_WRITE_ERROR;
- 8000db6:	f06f 0303 	mvn.w	r3, #3
- 8000dba:	613b      	str	r3, [r7, #16]
-       }
-     }
-   }
-      
-   if(status == LAN8742_STATUS_OK)
- 8000dbc:	693b      	ldr	r3, [r7, #16]
- 8000dbe:	2b00      	cmp	r3, #0
- 8000dc0:	d112      	bne.n	8000de8 <LAN8742_Init+0x146>
-   {
-     tickstart =  pObj->IO.GetTick();
- 8000dc2:	687b      	ldr	r3, [r7, #4]
- 8000dc4:	699b      	ldr	r3, [r3, #24]
- 8000dc6:	4798      	blx	r3
- 8000dc8:	4603      	mov	r3, r0
- 8000dca:	60fb      	str	r3, [r7, #12]
-     
-     /* Wait for 2s to perform initialization */
-     while((pObj->IO.GetTick() - tickstart) <= LAN8742_INIT_TO)
- 8000dcc:	bf00      	nop
- 8000dce:	687b      	ldr	r3, [r7, #4]
- 8000dd0:	699b      	ldr	r3, [r3, #24]
- 8000dd2:	4798      	blx	r3
- 8000dd4:	4603      	mov	r3, r0
- 8000dd6:	461a      	mov	r2, r3
- 8000dd8:	68fb      	ldr	r3, [r7, #12]
- 8000dda:	1ad3      	subs	r3, r2, r3
- 8000ddc:	f5b3 6ffa 	cmp.w	r3, #2000	; 0x7d0
- 8000de0:	d9f5      	bls.n	8000dce <LAN8742_Init+0x12c>
-     {
-     }
-     pObj->Is_Initialized = 1;
- 8000de2:	687b      	ldr	r3, [r7, #4]
- 8000de4:	2201      	movs	r2, #1
- 8000de6:	605a      	str	r2, [r3, #4]
-   }
-   
-   return status;
- 8000de8:	693b      	ldr	r3, [r7, #16]
- }
- 8000dea:	4618      	mov	r0, r3
- 8000dec:	3718      	adds	r7, #24
- 8000dee:	46bd      	mov	sp, r7
- 8000df0:	bd80      	pop	{r7, pc}
-
-08000df2 <LAN8742_GetLinkState>:
-  *         LAN8742_STATUS_10MBITS_HALFDUPLEX  if 10Mb/s HD       
-  *         LAN8742_STATUS_READ_ERROR if connot read register
-  *         LAN8742_STATUS_WRITE_ERROR if connot write to register
-  */
-int32_t LAN8742_GetLinkState(lan8742_Object_t *pObj)
-{
- 8000df2:	b580      	push	{r7, lr}
- 8000df4:	b084      	sub	sp, #16
- 8000df6:	af00      	add	r7, sp, #0
- 8000df8:	6078      	str	r0, [r7, #4]
-  uint32_t readval = 0;
- 8000dfa:	2300      	movs	r3, #0
- 8000dfc:	60fb      	str	r3, [r7, #12]
-  
-  /* Read Status register  */
-  if(pObj->IO.ReadReg(pObj->DevAddr, LAN8742_BSR, &readval) < 0)
- 8000dfe:	687b      	ldr	r3, [r7, #4]
- 8000e00:	695b      	ldr	r3, [r3, #20]
- 8000e02:	687a      	ldr	r2, [r7, #4]
- 8000e04:	6810      	ldr	r0, [r2, #0]
- 8000e06:	f107 020c 	add.w	r2, r7, #12
- 8000e0a:	2101      	movs	r1, #1
- 8000e0c:	4798      	blx	r3
- 8000e0e:	4603      	mov	r3, r0
- 8000e10:	2b00      	cmp	r3, #0
- 8000e12:	da02      	bge.n	8000e1a <LAN8742_GetLinkState+0x28>
-  {
-    return LAN8742_STATUS_READ_ERROR;
- 8000e14:	f06f 0304 	mvn.w	r3, #4
- 8000e18:	e06e      	b.n	8000ef8 <LAN8742_GetLinkState+0x106>
-  }
-  
-  /* Read Status register again */
-  if(pObj->IO.ReadReg(pObj->DevAddr, LAN8742_BSR, &readval) < 0)
- 8000e1a:	687b      	ldr	r3, [r7, #4]
- 8000e1c:	695b      	ldr	r3, [r3, #20]
- 8000e1e:	687a      	ldr	r2, [r7, #4]
- 8000e20:	6810      	ldr	r0, [r2, #0]
- 8000e22:	f107 020c 	add.w	r2, r7, #12
- 8000e26:	2101      	movs	r1, #1
- 8000e28:	4798      	blx	r3
- 8000e2a:	4603      	mov	r3, r0
- 8000e2c:	2b00      	cmp	r3, #0
- 8000e2e:	da02      	bge.n	8000e36 <LAN8742_GetLinkState+0x44>
-  {
-    return LAN8742_STATUS_READ_ERROR;
- 8000e30:	f06f 0304 	mvn.w	r3, #4
- 8000e34:	e060      	b.n	8000ef8 <LAN8742_GetLinkState+0x106>
-  }
-  
-  if((readval & LAN8742_BSR_LINK_STATUS) == 0)
- 8000e36:	68fb      	ldr	r3, [r7, #12]
- 8000e38:	f003 0304 	and.w	r3, r3, #4
- 8000e3c:	2b00      	cmp	r3, #0
- 8000e3e:	d101      	bne.n	8000e44 <LAN8742_GetLinkState+0x52>
-  {
-    /* Return Link Down status */
-    return LAN8742_STATUS_LINK_DOWN;    
- 8000e40:	2301      	movs	r3, #1
- 8000e42:	e059      	b.n	8000ef8 <LAN8742_GetLinkState+0x106>
-  }
-  
-  /* Check Auto negotiaition */
-  if(pObj->IO.ReadReg(pObj->DevAddr, LAN8742_BCR, &readval) < 0)
- 8000e44:	687b      	ldr	r3, [r7, #4]
- 8000e46:	695b      	ldr	r3, [r3, #20]
- 8000e48:	687a      	ldr	r2, [r7, #4]
- 8000e4a:	6810      	ldr	r0, [r2, #0]
- 8000e4c:	f107 020c 	add.w	r2, r7, #12
- 8000e50:	2100      	movs	r1, #0
- 8000e52:	4798      	blx	r3
- 8000e54:	4603      	mov	r3, r0
- 8000e56:	2b00      	cmp	r3, #0
- 8000e58:	da02      	bge.n	8000e60 <LAN8742_GetLinkState+0x6e>
-  {
-    return LAN8742_STATUS_READ_ERROR;
- 8000e5a:	f06f 0304 	mvn.w	r3, #4
- 8000e5e:	e04b      	b.n	8000ef8 <LAN8742_GetLinkState+0x106>
-  }
-  
-  if((readval & LAN8742_BCR_AUTONEGO_EN) != LAN8742_BCR_AUTONEGO_EN)
- 8000e60:	68fb      	ldr	r3, [r7, #12]
- 8000e62:	f403 5380 	and.w	r3, r3, #4096	; 0x1000
- 8000e66:	2b00      	cmp	r3, #0
- 8000e68:	d11b      	bne.n	8000ea2 <LAN8742_GetLinkState+0xb0>
-  {
-    if(((readval & LAN8742_BCR_SPEED_SELECT) == LAN8742_BCR_SPEED_SELECT) && ((readval & LAN8742_BCR_DUPLEX_MODE) == LAN8742_BCR_DUPLEX_MODE)) 
- 8000e6a:	68fb      	ldr	r3, [r7, #12]
- 8000e6c:	f403 5300 	and.w	r3, r3, #8192	; 0x2000
- 8000e70:	2b00      	cmp	r3, #0
- 8000e72:	d006      	beq.n	8000e82 <LAN8742_GetLinkState+0x90>
- 8000e74:	68fb      	ldr	r3, [r7, #12]
- 8000e76:	f403 7380 	and.w	r3, r3, #256	; 0x100
- 8000e7a:	2b00      	cmp	r3, #0
- 8000e7c:	d001      	beq.n	8000e82 <LAN8742_GetLinkState+0x90>
-    {
-      return LAN8742_STATUS_100MBITS_FULLDUPLEX;
- 8000e7e:	2302      	movs	r3, #2
- 8000e80:	e03a      	b.n	8000ef8 <LAN8742_GetLinkState+0x106>
-    }
-    else if ((readval & LAN8742_BCR_SPEED_SELECT) == LAN8742_BCR_SPEED_SELECT)
- 8000e82:	68fb      	ldr	r3, [r7, #12]
- 8000e84:	f403 5300 	and.w	r3, r3, #8192	; 0x2000
- 8000e88:	2b00      	cmp	r3, #0
- 8000e8a:	d001      	beq.n	8000e90 <LAN8742_GetLinkState+0x9e>
-    {
-      return LAN8742_STATUS_100MBITS_HALFDUPLEX;
- 8000e8c:	2303      	movs	r3, #3
- 8000e8e:	e033      	b.n	8000ef8 <LAN8742_GetLinkState+0x106>
-    }        
-    else if ((readval & LAN8742_BCR_DUPLEX_MODE) == LAN8742_BCR_DUPLEX_MODE)
- 8000e90:	68fb      	ldr	r3, [r7, #12]
- 8000e92:	f403 7380 	and.w	r3, r3, #256	; 0x100
- 8000e96:	2b00      	cmp	r3, #0
- 8000e98:	d001      	beq.n	8000e9e <LAN8742_GetLinkState+0xac>
-    {
-      return LAN8742_STATUS_10MBITS_FULLDUPLEX;
- 8000e9a:	2304      	movs	r3, #4
- 8000e9c:	e02c      	b.n	8000ef8 <LAN8742_GetLinkState+0x106>
-    }
-    else
-    {
-      return LAN8742_STATUS_10MBITS_HALFDUPLEX;
- 8000e9e:	2305      	movs	r3, #5
- 8000ea0:	e02a      	b.n	8000ef8 <LAN8742_GetLinkState+0x106>
-    }  		
-  }
-  else /* Auto Nego enabled */
-  {
-    if(pObj->IO.ReadReg(pObj->DevAddr, LAN8742_PHYSCSR, &readval) < 0)
- 8000ea2:	687b      	ldr	r3, [r7, #4]
- 8000ea4:	695b      	ldr	r3, [r3, #20]
- 8000ea6:	687a      	ldr	r2, [r7, #4]
- 8000ea8:	6810      	ldr	r0, [r2, #0]
- 8000eaa:	f107 020c 	add.w	r2, r7, #12
- 8000eae:	211f      	movs	r1, #31
- 8000eb0:	4798      	blx	r3
- 8000eb2:	4603      	mov	r3, r0
- 8000eb4:	2b00      	cmp	r3, #0
- 8000eb6:	da02      	bge.n	8000ebe <LAN8742_GetLinkState+0xcc>
-    {
-      return LAN8742_STATUS_READ_ERROR;
- 8000eb8:	f06f 0304 	mvn.w	r3, #4
- 8000ebc:	e01c      	b.n	8000ef8 <LAN8742_GetLinkState+0x106>
-    }
-    
-    /* Check if auto nego not done */
-    if((readval & LAN8742_PHYSCSR_AUTONEGO_DONE) == 0)
- 8000ebe:	68fb      	ldr	r3, [r7, #12]
- 8000ec0:	f403 5380 	and.w	r3, r3, #4096	; 0x1000
- 8000ec4:	2b00      	cmp	r3, #0
- 8000ec6:	d101      	bne.n	8000ecc <LAN8742_GetLinkState+0xda>
-    {
-      return LAN8742_STATUS_AUTONEGO_NOTDONE;
- 8000ec8:	2306      	movs	r3, #6
- 8000eca:	e015      	b.n	8000ef8 <LAN8742_GetLinkState+0x106>
-    }
-    
-    if((readval & LAN8742_PHYSCSR_HCDSPEEDMASK) == LAN8742_PHYSCSR_100BTX_FD)
- 8000ecc:	68fb      	ldr	r3, [r7, #12]
- 8000ece:	f003 031c 	and.w	r3, r3, #28
- 8000ed2:	2b18      	cmp	r3, #24
- 8000ed4:	d101      	bne.n	8000eda <LAN8742_GetLinkState+0xe8>
-    {
-      return LAN8742_STATUS_100MBITS_FULLDUPLEX;
- 8000ed6:	2302      	movs	r3, #2
- 8000ed8:	e00e      	b.n	8000ef8 <LAN8742_GetLinkState+0x106>
-    }
-    else if ((readval & LAN8742_PHYSCSR_HCDSPEEDMASK) == LAN8742_PHYSCSR_100BTX_HD)
- 8000eda:	68fb      	ldr	r3, [r7, #12]
- 8000edc:	f003 031c 	and.w	r3, r3, #28
- 8000ee0:	2b08      	cmp	r3, #8
- 8000ee2:	d101      	bne.n	8000ee8 <LAN8742_GetLinkState+0xf6>
-    {
-      return LAN8742_STATUS_100MBITS_HALFDUPLEX;
- 8000ee4:	2303      	movs	r3, #3
- 8000ee6:	e007      	b.n	8000ef8 <LAN8742_GetLinkState+0x106>
-    }
-    else if ((readval & LAN8742_PHYSCSR_HCDSPEEDMASK) == LAN8742_PHYSCSR_10BT_FD)
- 8000ee8:	68fb      	ldr	r3, [r7, #12]
- 8000eea:	f003 031c 	and.w	r3, r3, #28
- 8000eee:	2b14      	cmp	r3, #20
- 8000ef0:	d101      	bne.n	8000ef6 <LAN8742_GetLinkState+0x104>
-    {
-      return LAN8742_STATUS_10MBITS_FULLDUPLEX;
- 8000ef2:	2304      	movs	r3, #4
- 8000ef4:	e000      	b.n	8000ef8 <LAN8742_GetLinkState+0x106>
-    }
-    else
-    {
-      return LAN8742_STATUS_10MBITS_HALFDUPLEX;
- 8000ef6:	2305      	movs	r3, #5
-    }				
-  }
-}
- 8000ef8:	4618      	mov	r0, r3
- 8000efa:	3710      	adds	r7, #16
- 8000efc:	46bd      	mov	sp, r7
- 8000efe:	bd80      	pop	{r7, pc}
-
-08000f00 <HAL_Init>:
-  *         need to ensure that the SysTick time base is always set to 1 millisecond
-  *         to have correct HAL operation.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_Init(void)
-{
- 8000f00:	b580      	push	{r7, lr}
- 8000f02:	b082      	sub	sp, #8
- 8000f04:	af00      	add	r7, sp, #0
-   __HAL_ART_CONFIG_BASE_ADDRESS(0x08100000UL);  /* Configure the Cortex-M4 ART Base address to the Flash Bank 2 : */
-   __HAL_ART_ENABLE();                           /* Enable the Cortex-M4 ART */
-#endif /* DUAL_CORE &&  CORE_CM4 */
-
-  /* Set Interrupt Group Priority */
-  HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
- 8000f06:	2003      	movs	r0, #3
- 8000f08:	f000 f970 	bl	80011ec <HAL_NVIC_SetPriorityGrouping>
-
-  /* Update the SystemCoreClock global variable */
-#if defined(RCC_D1CFGR_D1CPRE)
-  common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU);
- 8000f0c:	f002 fea8 	bl	8003c60 <HAL_RCC_GetSysClockFreq>
- 8000f10:	4602      	mov	r2, r0
- 8000f12:	4b15      	ldr	r3, [pc, #84]	; (8000f68 <HAL_Init+0x68>)
- 8000f14:	699b      	ldr	r3, [r3, #24]
- 8000f16:	0a1b      	lsrs	r3, r3, #8
- 8000f18:	f003 030f 	and.w	r3, r3, #15
- 8000f1c:	4913      	ldr	r1, [pc, #76]	; (8000f6c <HAL_Init+0x6c>)
- 8000f1e:	5ccb      	ldrb	r3, [r1, r3]
- 8000f20:	f003 031f 	and.w	r3, r3, #31
- 8000f24:	fa22 f303 	lsr.w	r3, r2, r3
- 8000f28:	607b      	str	r3, [r7, #4]
-  common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos]) & 0x1FU);
-#endif
-
-  /* Update the SystemD2Clock global variable */
-#if defined(RCC_D1CFGR_HPRE)
-  SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
- 8000f2a:	4b0f      	ldr	r3, [pc, #60]	; (8000f68 <HAL_Init+0x68>)
- 8000f2c:	699b      	ldr	r3, [r3, #24]
- 8000f2e:	f003 030f 	and.w	r3, r3, #15
- 8000f32:	4a0e      	ldr	r2, [pc, #56]	; (8000f6c <HAL_Init+0x6c>)
- 8000f34:	5cd3      	ldrb	r3, [r2, r3]
- 8000f36:	f003 031f 	and.w	r3, r3, #31
- 8000f3a:	687a      	ldr	r2, [r7, #4]
- 8000f3c:	fa22 f303 	lsr.w	r3, r2, r3
- 8000f40:	4a0b      	ldr	r2, [pc, #44]	; (8000f70 <HAL_Init+0x70>)
- 8000f42:	6013      	str	r3, [r2, #0]
-#endif
-
-#if defined(DUAL_CORE) && defined(CORE_CM4)
-  SystemCoreClock = SystemD2Clock;
-#else
-  SystemCoreClock = common_system_clock;
- 8000f44:	4a0b      	ldr	r2, [pc, #44]	; (8000f74 <HAL_Init+0x74>)
- 8000f46:	687b      	ldr	r3, [r7, #4]
- 8000f48:	6013      	str	r3, [r2, #0]
-#endif /* DUAL_CORE && CORE_CM4 */
-
-  /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
-  if(HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)
- 8000f4a:	200f      	movs	r0, #15
- 8000f4c:	f000 f814 	bl	8000f78 <HAL_InitTick>
- 8000f50:	4603      	mov	r3, r0
- 8000f52:	2b00      	cmp	r3, #0
- 8000f54:	d001      	beq.n	8000f5a <HAL_Init+0x5a>
-  {
-    return HAL_ERROR;
- 8000f56:	2301      	movs	r3, #1
- 8000f58:	e002      	b.n	8000f60 <HAL_Init+0x60>
-  }
-
-  /* Init the low level hardware */
-  HAL_MspInit();
- 8000f5a:	f7ff fcc3 	bl	80008e4 <HAL_MspInit>
-
-  /* Return function status */
-  return HAL_OK;
- 8000f5e:	2300      	movs	r3, #0
-}
- 8000f60:	4618      	mov	r0, r3
- 8000f62:	3708      	adds	r7, #8
- 8000f64:	46bd      	mov	sp, r7
- 8000f66:	bd80      	pop	{r7, pc}
- 8000f68:	58024400 	.word	0x58024400
- 8000f6c:	08014c80 	.word	0x08014c80
- 8000f70:	24000004 	.word	0x24000004
- 8000f74:	24000000 	.word	0x24000000
-
-08000f78 <HAL_InitTick>:
-  *       implementation  in user file.
-  * @param TickPriority: Tick interrupt priority.
-  * @retval HAL status
-  */
-__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
-{
- 8000f78:	b580      	push	{r7, lr}
- 8000f7a:	b082      	sub	sp, #8
- 8000f7c:	af00      	add	r7, sp, #0
- 8000f7e:	6078      	str	r0, [r7, #4]
-  /* Check uwTickFreq for MisraC 2012 (even if uwTickFreq is a enum type that don't take the value zero)*/
-  if((uint32_t)uwTickFreq == 0UL)
- 8000f80:	4b15      	ldr	r3, [pc, #84]	; (8000fd8 <HAL_InitTick+0x60>)
- 8000f82:	781b      	ldrb	r3, [r3, #0]
- 8000f84:	2b00      	cmp	r3, #0
- 8000f86:	d101      	bne.n	8000f8c <HAL_InitTick+0x14>
-  {
-    return HAL_ERROR;
- 8000f88:	2301      	movs	r3, #1
- 8000f8a:	e021      	b.n	8000fd0 <HAL_InitTick+0x58>
-  }
-
-    /* Configure the SysTick to have interrupt in 1ms time basis*/
-    if (HAL_SYSTICK_Config(SystemCoreClock / (1000UL / (uint32_t)uwTickFreq)) > 0U)
- 8000f8c:	4b13      	ldr	r3, [pc, #76]	; (8000fdc <HAL_InitTick+0x64>)
- 8000f8e:	681a      	ldr	r2, [r3, #0]
- 8000f90:	4b11      	ldr	r3, [pc, #68]	; (8000fd8 <HAL_InitTick+0x60>)
- 8000f92:	781b      	ldrb	r3, [r3, #0]
- 8000f94:	4619      	mov	r1, r3
- 8000f96:	f44f 737a 	mov.w	r3, #1000	; 0x3e8
- 8000f9a:	fbb3 f3f1 	udiv	r3, r3, r1
- 8000f9e:	fbb2 f3f3 	udiv	r3, r2, r3
- 8000fa2:	4618      	mov	r0, r3
- 8000fa4:	f000 f955 	bl	8001252 <HAL_SYSTICK_Config>
- 8000fa8:	4603      	mov	r3, r0
- 8000faa:	2b00      	cmp	r3, #0
- 8000fac:	d001      	beq.n	8000fb2 <HAL_InitTick+0x3a>
-    {
-      return HAL_ERROR;
- 8000fae:	2301      	movs	r3, #1
- 8000fb0:	e00e      	b.n	8000fd0 <HAL_InitTick+0x58>
-    }
-
-  /* Configure the SysTick IRQ priority */
-  if (TickPriority < (1UL << __NVIC_PRIO_BITS))
- 8000fb2:	687b      	ldr	r3, [r7, #4]
- 8000fb4:	2b0f      	cmp	r3, #15
- 8000fb6:	d80a      	bhi.n	8000fce <HAL_InitTick+0x56>
-  {
-    HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
- 8000fb8:	2200      	movs	r2, #0
- 8000fba:	6879      	ldr	r1, [r7, #4]
- 8000fbc:	f04f 30ff 	mov.w	r0, #4294967295
- 8000fc0:	f000 f91f 	bl	8001202 <HAL_NVIC_SetPriority>
-    uwTickPrio = TickPriority;
- 8000fc4:	4a06      	ldr	r2, [pc, #24]	; (8000fe0 <HAL_InitTick+0x68>)
- 8000fc6:	687b      	ldr	r3, [r7, #4]
- 8000fc8:	6013      	str	r3, [r2, #0]
-  {
-    return HAL_ERROR;
-  }
-
-  /* Return function status */
-  return HAL_OK;
- 8000fca:	2300      	movs	r3, #0
- 8000fcc:	e000      	b.n	8000fd0 <HAL_InitTick+0x58>
-    return HAL_ERROR;
- 8000fce:	2301      	movs	r3, #1
-}
- 8000fd0:	4618      	mov	r0, r3
- 8000fd2:	3708      	adds	r7, #8
- 8000fd4:	46bd      	mov	sp, r7
- 8000fd6:	bd80      	pop	{r7, pc}
- 8000fd8:	2400000c 	.word	0x2400000c
- 8000fdc:	24000000 	.word	0x24000000
- 8000fe0:	24000008 	.word	0x24000008
-
-08000fe4 <HAL_IncTick>:
- * @note This function is declared as __weak to be overwritten in case of other
-  *      implementations in user file.
-  * @retval None
-  */
-__weak void HAL_IncTick(void)
-{
- 8000fe4:	b480      	push	{r7}
- 8000fe6:	af00      	add	r7, sp, #0
-  uwTick += (uint32_t)uwTickFreq;
- 8000fe8:	4b06      	ldr	r3, [pc, #24]	; (8001004 <HAL_IncTick+0x20>)
- 8000fea:	781b      	ldrb	r3, [r3, #0]
- 8000fec:	461a      	mov	r2, r3
- 8000fee:	4b06      	ldr	r3, [pc, #24]	; (8001008 <HAL_IncTick+0x24>)
- 8000ff0:	681b      	ldr	r3, [r3, #0]
- 8000ff2:	4413      	add	r3, r2
- 8000ff4:	4a04      	ldr	r2, [pc, #16]	; (8001008 <HAL_IncTick+0x24>)
- 8000ff6:	6013      	str	r3, [r2, #0]
-}
- 8000ff8:	bf00      	nop
- 8000ffa:	46bd      	mov	sp, r7
- 8000ffc:	f85d 7b04 	ldr.w	r7, [sp], #4
- 8001000:	4770      	bx	lr
- 8001002:	bf00      	nop
- 8001004:	2400000c 	.word	0x2400000c
- 8001008:	24000128 	.word	0x24000128
-
-0800100c <HAL_GetTick>:
-  * @note This function is declared as __weak to be overwritten in case of other
-  *       implementations in user file.
-  * @retval tick value
-  */
-__weak uint32_t HAL_GetTick(void)
-{
- 800100c:	b480      	push	{r7}
- 800100e:	af00      	add	r7, sp, #0
-  return uwTick;
- 8001010:	4b03      	ldr	r3, [pc, #12]	; (8001020 <HAL_GetTick+0x14>)
- 8001012:	681b      	ldr	r3, [r3, #0]
-}
- 8001014:	4618      	mov	r0, r3
- 8001016:	46bd      	mov	sp, r7
- 8001018:	f85d 7b04 	ldr.w	r7, [sp], #4
- 800101c:	4770      	bx	lr
- 800101e:	bf00      	nop
- 8001020:	24000128 	.word	0x24000128
-
-08001024 <HAL_SYSCFG_ETHInterfaceSelect>:
-  *   @arg SYSCFG_ETH_MII : Select the Media Independent Interface
-  *   @arg SYSCFG_ETH_RMII: Select the Reduced Media Independent Interface
-  * @retval None
-  */
-void HAL_SYSCFG_ETHInterfaceSelect(uint32_t SYSCFG_ETHInterface)
-{
- 8001024:	b480      	push	{r7}
- 8001026:	b083      	sub	sp, #12
- 8001028:	af00      	add	r7, sp, #0
- 800102a:	6078      	str	r0, [r7, #4]
-  /* Check the parameter */
-  assert_param(IS_SYSCFG_ETHERNET_CONFIG(SYSCFG_ETHInterface));
-
-  MODIFY_REG(SYSCFG->PMCR, SYSCFG_PMCR_EPIS_SEL, (uint32_t)(SYSCFG_ETHInterface));
- 800102c:	4b06      	ldr	r3, [pc, #24]	; (8001048 <HAL_SYSCFG_ETHInterfaceSelect+0x24>)
- 800102e:	685b      	ldr	r3, [r3, #4]
- 8001030:	f423 0260 	bic.w	r2, r3, #14680064	; 0xe00000
- 8001034:	4904      	ldr	r1, [pc, #16]	; (8001048 <HAL_SYSCFG_ETHInterfaceSelect+0x24>)
- 8001036:	687b      	ldr	r3, [r7, #4]
- 8001038:	4313      	orrs	r3, r2
- 800103a:	604b      	str	r3, [r1, #4]
-}
- 800103c:	bf00      	nop
- 800103e:	370c      	adds	r7, #12
- 8001040:	46bd      	mov	sp, r7
- 8001042:	f85d 7b04 	ldr.w	r7, [sp], #4
- 8001046:	4770      	bx	lr
- 8001048:	58000400 	.word	0x58000400
-
-0800104c <__NVIC_SetPriorityGrouping>:
-{
- 800104c:	b480      	push	{r7}
- 800104e:	b085      	sub	sp, #20
- 8001050:	af00      	add	r7, sp, #0
- 8001052:	6078      	str	r0, [r7, #4]
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
- 8001054:	687b      	ldr	r3, [r7, #4]
- 8001056:	f003 0307 	and.w	r3, r3, #7
- 800105a:	60fb      	str	r3, [r7, #12]
-  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
- 800105c:	4b0b      	ldr	r3, [pc, #44]	; (800108c <__NVIC_SetPriorityGrouping+0x40>)
- 800105e:	68db      	ldr	r3, [r3, #12]
- 8001060:	60bb      	str	r3, [r7, #8]
-  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
- 8001062:	68ba      	ldr	r2, [r7, #8]
- 8001064:	f64f 03ff 	movw	r3, #63743	; 0xf8ff
- 8001068:	4013      	ands	r3, r2
- 800106a:	60bb      	str	r3, [r7, #8]
-                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos)  );              /* Insert write key and priority group */
- 800106c:	68fb      	ldr	r3, [r7, #12]
- 800106e:	021a      	lsls	r2, r3, #8
-                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
- 8001070:	68bb      	ldr	r3, [r7, #8]
- 8001072:	431a      	orrs	r2, r3
-  reg_value  =  (reg_value                                   |
- 8001074:	4b06      	ldr	r3, [pc, #24]	; (8001090 <__NVIC_SetPriorityGrouping+0x44>)
- 8001076:	4313      	orrs	r3, r2
- 8001078:	60bb      	str	r3, [r7, #8]
-  SCB->AIRCR =  reg_value;
- 800107a:	4a04      	ldr	r2, [pc, #16]	; (800108c <__NVIC_SetPriorityGrouping+0x40>)
- 800107c:	68bb      	ldr	r3, [r7, #8]
- 800107e:	60d3      	str	r3, [r2, #12]
-}
- 8001080:	bf00      	nop
- 8001082:	3714      	adds	r7, #20
- 8001084:	46bd      	mov	sp, r7
- 8001086:	f85d 7b04 	ldr.w	r7, [sp], #4
- 800108a:	4770      	bx	lr
- 800108c:	e000ed00 	.word	0xe000ed00
- 8001090:	05fa0000 	.word	0x05fa0000
-
-08001094 <__NVIC_GetPriorityGrouping>:
-{
- 8001094:	b480      	push	{r7}
- 8001096:	af00      	add	r7, sp, #0
-  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
- 8001098:	4b04      	ldr	r3, [pc, #16]	; (80010ac <__NVIC_GetPriorityGrouping+0x18>)
- 800109a:	68db      	ldr	r3, [r3, #12]
- 800109c:	0a1b      	lsrs	r3, r3, #8
- 800109e:	f003 0307 	and.w	r3, r3, #7
-}
- 80010a2:	4618      	mov	r0, r3
- 80010a4:	46bd      	mov	sp, r7
- 80010a6:	f85d 7b04 	ldr.w	r7, [sp], #4
- 80010aa:	4770      	bx	lr
- 80010ac:	e000ed00 	.word	0xe000ed00
-
-080010b0 <__NVIC_EnableIRQ>:
-{
- 80010b0:	b480      	push	{r7}
- 80010b2:	b083      	sub	sp, #12
- 80010b4:	af00      	add	r7, sp, #0
- 80010b6:	4603      	mov	r3, r0
- 80010b8:	80fb      	strh	r3, [r7, #6]
-  if ((int32_t)(IRQn) >= 0)
- 80010ba:	f9b7 3006 	ldrsh.w	r3, [r7, #6]
- 80010be:	2b00      	cmp	r3, #0
- 80010c0:	db0b      	blt.n	80010da <__NVIC_EnableIRQ+0x2a>
-    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
- 80010c2:	88fb      	ldrh	r3, [r7, #6]
- 80010c4:	f003 021f 	and.w	r2, r3, #31
- 80010c8:	4907      	ldr	r1, [pc, #28]	; (80010e8 <__NVIC_EnableIRQ+0x38>)
- 80010ca:	f9b7 3006 	ldrsh.w	r3, [r7, #6]
- 80010ce:	095b      	lsrs	r3, r3, #5
- 80010d0:	2001      	movs	r0, #1
- 80010d2:	fa00 f202 	lsl.w	r2, r0, r2
- 80010d6:	f841 2023 	str.w	r2, [r1, r3, lsl #2]
-}
- 80010da:	bf00      	nop
- 80010dc:	370c      	adds	r7, #12
- 80010de:	46bd      	mov	sp, r7
- 80010e0:	f85d 7b04 	ldr.w	r7, [sp], #4
- 80010e4:	4770      	bx	lr
- 80010e6:	bf00      	nop
- 80010e8:	e000e100 	.word	0xe000e100
-
-080010ec <__NVIC_SetPriority>:
-{
- 80010ec:	b480      	push	{r7}
- 80010ee:	b083      	sub	sp, #12
- 80010f0:	af00      	add	r7, sp, #0
- 80010f2:	4603      	mov	r3, r0
- 80010f4:	6039      	str	r1, [r7, #0]
- 80010f6:	80fb      	strh	r3, [r7, #6]
-  if ((int32_t)(IRQn) >= 0)
- 80010f8:	f9b7 3006 	ldrsh.w	r3, [r7, #6]
- 80010fc:	2b00      	cmp	r3, #0
- 80010fe:	db0a      	blt.n	8001116 <__NVIC_SetPriority+0x2a>
-    NVIC->IP[((uint32_t)IRQn)]                = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
- 8001100:	683b      	ldr	r3, [r7, #0]
- 8001102:	b2da      	uxtb	r2, r3
- 8001104:	490c      	ldr	r1, [pc, #48]	; (8001138 <__NVIC_SetPriority+0x4c>)
- 8001106:	f9b7 3006 	ldrsh.w	r3, [r7, #6]
- 800110a:	0112      	lsls	r2, r2, #4
- 800110c:	b2d2      	uxtb	r2, r2
- 800110e:	440b      	add	r3, r1
- 8001110:	f883 2300 	strb.w	r2, [r3, #768]	; 0x300
-}
- 8001114:	e00a      	b.n	800112c <__NVIC_SetPriority+0x40>
-    SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
- 8001116:	683b      	ldr	r3, [r7, #0]
- 8001118:	b2da      	uxtb	r2, r3
- 800111a:	4908      	ldr	r1, [pc, #32]	; (800113c <__NVIC_SetPriority+0x50>)
- 800111c:	88fb      	ldrh	r3, [r7, #6]
- 800111e:	f003 030f 	and.w	r3, r3, #15
- 8001122:	3b04      	subs	r3, #4
- 8001124:	0112      	lsls	r2, r2, #4
- 8001126:	b2d2      	uxtb	r2, r2
- 8001128:	440b      	add	r3, r1
- 800112a:	761a      	strb	r2, [r3, #24]
-}
- 800112c:	bf00      	nop
- 800112e:	370c      	adds	r7, #12
- 8001130:	46bd      	mov	sp, r7
- 8001132:	f85d 7b04 	ldr.w	r7, [sp], #4
- 8001136:	4770      	bx	lr
- 8001138:	e000e100 	.word	0xe000e100
- 800113c:	e000ed00 	.word	0xe000ed00
-
-08001140 <NVIC_EncodePriority>:
-{
- 8001140:	b480      	push	{r7}
- 8001142:	b089      	sub	sp, #36	; 0x24
- 8001144:	af00      	add	r7, sp, #0
- 8001146:	60f8      	str	r0, [r7, #12]
- 8001148:	60b9      	str	r1, [r7, #8]
- 800114a:	607a      	str	r2, [r7, #4]
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
- 800114c:	68fb      	ldr	r3, [r7, #12]
- 800114e:	f003 0307 	and.w	r3, r3, #7
- 8001152:	61fb      	str	r3, [r7, #28]
-  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
- 8001154:	69fb      	ldr	r3, [r7, #28]
- 8001156:	f1c3 0307 	rsb	r3, r3, #7
- 800115a:	2b04      	cmp	r3, #4
- 800115c:	bf28      	it	cs
- 800115e:	2304      	movcs	r3, #4
- 8001160:	61bb      	str	r3, [r7, #24]
-  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
- 8001162:	69fb      	ldr	r3, [r7, #28]
- 8001164:	3304      	adds	r3, #4
- 8001166:	2b06      	cmp	r3, #6
- 8001168:	d902      	bls.n	8001170 <NVIC_EncodePriority+0x30>
- 800116a:	69fb      	ldr	r3, [r7, #28]
- 800116c:	3b03      	subs	r3, #3
- 800116e:	e000      	b.n	8001172 <NVIC_EncodePriority+0x32>
- 8001170:	2300      	movs	r3, #0
- 8001172:	617b      	str	r3, [r7, #20]
-           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
- 8001174:	f04f 32ff 	mov.w	r2, #4294967295
- 8001178:	69bb      	ldr	r3, [r7, #24]
- 800117a:	fa02 f303 	lsl.w	r3, r2, r3
- 800117e:	43da      	mvns	r2, r3
- 8001180:	68bb      	ldr	r3, [r7, #8]
- 8001182:	401a      	ands	r2, r3
- 8001184:	697b      	ldr	r3, [r7, #20]
- 8001186:	409a      	lsls	r2, r3
-           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
- 8001188:	f04f 31ff 	mov.w	r1, #4294967295
- 800118c:	697b      	ldr	r3, [r7, #20]
- 800118e:	fa01 f303 	lsl.w	r3, r1, r3
- 8001192:	43d9      	mvns	r1, r3
- 8001194:	687b      	ldr	r3, [r7, #4]
- 8001196:	400b      	ands	r3, r1
-           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
- 8001198:	4313      	orrs	r3, r2
-}
- 800119a:	4618      	mov	r0, r3
- 800119c:	3724      	adds	r7, #36	; 0x24
- 800119e:	46bd      	mov	sp, r7
- 80011a0:	f85d 7b04 	ldr.w	r7, [sp], #4
- 80011a4:	4770      	bx	lr
-	...
-
-080011a8 <SysTick_Config>:
-{
- 80011a8:	b580      	push	{r7, lr}
- 80011aa:	b082      	sub	sp, #8
- 80011ac:	af00      	add	r7, sp, #0
- 80011ae:	6078      	str	r0, [r7, #4]
-  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
- 80011b0:	687b      	ldr	r3, [r7, #4]
- 80011b2:	3b01      	subs	r3, #1
- 80011b4:	f1b3 7f80 	cmp.w	r3, #16777216	; 0x1000000
- 80011b8:	d301      	bcc.n	80011be <SysTick_Config+0x16>
-    return (1UL);                                                   /* Reload value impossible */
- 80011ba:	2301      	movs	r3, #1
- 80011bc:	e00f      	b.n	80011de <SysTick_Config+0x36>
-  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
- 80011be:	4a0a      	ldr	r2, [pc, #40]	; (80011e8 <SysTick_Config+0x40>)
- 80011c0:	687b      	ldr	r3, [r7, #4]
- 80011c2:	3b01      	subs	r3, #1
- 80011c4:	6053      	str	r3, [r2, #4]
-  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
- 80011c6:	210f      	movs	r1, #15
- 80011c8:	f04f 30ff 	mov.w	r0, #4294967295
- 80011cc:	f7ff ff8e 	bl	80010ec <__NVIC_SetPriority>
-  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
- 80011d0:	4b05      	ldr	r3, [pc, #20]	; (80011e8 <SysTick_Config+0x40>)
- 80011d2:	2200      	movs	r2, #0
- 80011d4:	609a      	str	r2, [r3, #8]
-  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
- 80011d6:	4b04      	ldr	r3, [pc, #16]	; (80011e8 <SysTick_Config+0x40>)
- 80011d8:	2207      	movs	r2, #7
- 80011da:	601a      	str	r2, [r3, #0]
-  return (0UL);                                                     /* Function successful */
- 80011dc:	2300      	movs	r3, #0
-}
- 80011de:	4618      	mov	r0, r3
- 80011e0:	3708      	adds	r7, #8
- 80011e2:	46bd      	mov	sp, r7
- 80011e4:	bd80      	pop	{r7, pc}
- 80011e6:	bf00      	nop
- 80011e8:	e000e010 	.word	0xe000e010
-
-080011ec <HAL_NVIC_SetPriorityGrouping>:
-  * @note   When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible.
-  *         The pending IRQ priority will be managed only by the subpriority.
-  * @retval None
-  */
-void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
-{
- 80011ec:	b580      	push	{r7, lr}
- 80011ee:	b082      	sub	sp, #8
- 80011f0:	af00      	add	r7, sp, #0
- 80011f2:	6078      	str	r0, [r7, #4]
-  /* Check the parameters */
-  assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
-
-  /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
-  NVIC_SetPriorityGrouping(PriorityGroup);
- 80011f4:	6878      	ldr	r0, [r7, #4]
- 80011f6:	f7ff ff29 	bl	800104c <__NVIC_SetPriorityGrouping>
-}
- 80011fa:	bf00      	nop
- 80011fc:	3708      	adds	r7, #8
- 80011fe:	46bd      	mov	sp, r7
- 8001200:	bd80      	pop	{r7, pc}
-
-08001202 <HAL_NVIC_SetPriority>:
-  *         This parameter can be a value between 0 and 15
-  *         A lower priority value indicates a higher priority.
-  * @retval None
-  */
-void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
-{
- 8001202:	b580      	push	{r7, lr}
- 8001204:	b086      	sub	sp, #24
- 8001206:	af00      	add	r7, sp, #0
- 8001208:	4603      	mov	r3, r0
- 800120a:	60b9      	str	r1, [r7, #8]
- 800120c:	607a      	str	r2, [r7, #4]
- 800120e:	81fb      	strh	r3, [r7, #14]
-
-  /* Check the parameters */
-  assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
-  assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
-
-  prioritygroup = NVIC_GetPriorityGrouping();
- 8001210:	f7ff ff40 	bl	8001094 <__NVIC_GetPriorityGrouping>
- 8001214:	6178      	str	r0, [r7, #20]
-
-  NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
- 8001216:	687a      	ldr	r2, [r7, #4]
- 8001218:	68b9      	ldr	r1, [r7, #8]
- 800121a:	6978      	ldr	r0, [r7, #20]
- 800121c:	f7ff ff90 	bl	8001140 <NVIC_EncodePriority>
- 8001220:	4602      	mov	r2, r0
- 8001222:	f9b7 300e 	ldrsh.w	r3, [r7, #14]
- 8001226:	4611      	mov	r1, r2
- 8001228:	4618      	mov	r0, r3
- 800122a:	f7ff ff5f 	bl	80010ec <__NVIC_SetPriority>
-}
- 800122e:	bf00      	nop
- 8001230:	3718      	adds	r7, #24
- 8001232:	46bd      	mov	sp, r7
- 8001234:	bd80      	pop	{r7, pc}
-
-08001236 <HAL_NVIC_EnableIRQ>:
-  *         This parameter can be an enumerator of IRQn_Type enumeration
-  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h))
-  * @retval None
-  */
-void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
-{
- 8001236:	b580      	push	{r7, lr}
- 8001238:	b082      	sub	sp, #8
- 800123a:	af00      	add	r7, sp, #0
- 800123c:	4603      	mov	r3, r0
- 800123e:	80fb      	strh	r3, [r7, #6]
-  /* Check the parameters */
-  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
-
-  /* Enable interrupt */
-  NVIC_EnableIRQ(IRQn);
- 8001240:	f9b7 3006 	ldrsh.w	r3, [r7, #6]
- 8001244:	4618      	mov	r0, r3
- 8001246:	f7ff ff33 	bl	80010b0 <__NVIC_EnableIRQ>
-}
- 800124a:	bf00      	nop
- 800124c:	3708      	adds	r7, #8
- 800124e:	46bd      	mov	sp, r7
- 8001250:	bd80      	pop	{r7, pc}
-
-08001252 <HAL_SYSTICK_Config>:
-  * @param  TicksNumb Specifies the ticks Number of ticks between two interrupts.
-  * @retval status   - 0  Function succeeded.
-  *                  - 1  Function failed.
-  */
-uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
-{
- 8001252:	b580      	push	{r7, lr}
- 8001254:	b082      	sub	sp, #8
- 8001256:	af00      	add	r7, sp, #0
- 8001258:	6078      	str	r0, [r7, #4]
-   return SysTick_Config(TicksNumb);
- 800125a:	6878      	ldr	r0, [r7, #4]
- 800125c:	f7ff ffa4 	bl	80011a8 <SysTick_Config>
- 8001260:	4603      	mov	r3, r0
-}
- 8001262:	4618      	mov	r0, r3
- 8001264:	3708      	adds	r7, #8
- 8001266:	46bd      	mov	sp, r7
- 8001268:	bd80      	pop	{r7, pc}
-	...
-
-0800126c <HAL_MPU_Disable>:
-/**
-  * @brief  Disables the MPU
-  * @retval None
-  */
-void HAL_MPU_Disable(void)
-{
- 800126c:	b480      	push	{r7}
- 800126e:	af00      	add	r7, sp, #0
-  \details Ensures the apparent order of the explicit memory operations before
-           and after the instruction, without ensuring their completion.
- */
-__STATIC_FORCEINLINE void __DMB(void)
-{
-  __ASM volatile ("dmb 0xF":::"memory");
- 8001270:	f3bf 8f5f 	dmb	sy
-}
- 8001274:	bf00      	nop
-  /* Make sure outstanding transfers are done */
-  __DMB();
-
-  /* Disable fault exceptions */
-  SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
- 8001276:	4b07      	ldr	r3, [pc, #28]	; (8001294 <HAL_MPU_Disable+0x28>)
- 8001278:	6a5b      	ldr	r3, [r3, #36]	; 0x24
- 800127a:	4a06      	ldr	r2, [pc, #24]	; (8001294 <HAL_MPU_Disable+0x28>)
- 800127c:	f423 3380 	bic.w	r3, r3, #65536	; 0x10000
- 8001280:	6253      	str	r3, [r2, #36]	; 0x24
-
-  /* Disable the MPU and clear the control register*/
-  MPU->CTRL = 0;
- 8001282:	4b05      	ldr	r3, [pc, #20]	; (8001298 <HAL_MPU_Disable+0x2c>)
- 8001284:	2200      	movs	r2, #0
- 8001286:	605a      	str	r2, [r3, #4]
-}
- 8001288:	bf00      	nop
- 800128a:	46bd      	mov	sp, r7
- 800128c:	f85d 7b04 	ldr.w	r7, [sp], #4
- 8001290:	4770      	bx	lr
- 8001292:	bf00      	nop
- 8001294:	e000ed00 	.word	0xe000ed00
- 8001298:	e000ed90 	.word	0xe000ed90
-
-0800129c <HAL_MPU_Enable>:
-  *            @arg MPU_PRIVILEGED_DEFAULT
-  *            @arg MPU_HFNMI_PRIVDEF
-  * @retval None
-  */
-void HAL_MPU_Enable(uint32_t MPU_Control)
-{
- 800129c:	b480      	push	{r7}
- 800129e:	b083      	sub	sp, #12
- 80012a0:	af00      	add	r7, sp, #0
- 80012a2:	6078      	str	r0, [r7, #4]
-  /* Enable the MPU */
-  MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
- 80012a4:	4a0b      	ldr	r2, [pc, #44]	; (80012d4 <HAL_MPU_Enable+0x38>)
- 80012a6:	687b      	ldr	r3, [r7, #4]
- 80012a8:	f043 0301 	orr.w	r3, r3, #1
- 80012ac:	6053      	str	r3, [r2, #4]
-
-  /* Enable fault exceptions */
-  SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
- 80012ae:	4b0a      	ldr	r3, [pc, #40]	; (80012d8 <HAL_MPU_Enable+0x3c>)
- 80012b0:	6a5b      	ldr	r3, [r3, #36]	; 0x24
- 80012b2:	4a09      	ldr	r2, [pc, #36]	; (80012d8 <HAL_MPU_Enable+0x3c>)
- 80012b4:	f443 3380 	orr.w	r3, r3, #65536	; 0x10000
- 80012b8:	6253      	str	r3, [r2, #36]	; 0x24
-  __ASM volatile ("dsb 0xF":::"memory");
- 80012ba:	f3bf 8f4f 	dsb	sy
-}
- 80012be:	bf00      	nop
-  __ASM volatile ("isb 0xF":::"memory");
- 80012c0:	f3bf 8f6f 	isb	sy
-}
- 80012c4:	bf00      	nop
-
-  /* Ensure MPU setting take effects */
-  __DSB();
-  __ISB();
-}
- 80012c6:	bf00      	nop
- 80012c8:	370c      	adds	r7, #12
- 80012ca:	46bd      	mov	sp, r7
- 80012cc:	f85d 7b04 	ldr.w	r7, [sp], #4
- 80012d0:	4770      	bx	lr
- 80012d2:	bf00      	nop
- 80012d4:	e000ed90 	.word	0xe000ed90
- 80012d8:	e000ed00 	.word	0xe000ed00
-
-080012dc <HAL_MPU_ConfigRegion>:
-  * @param  MPU_Init Pointer to a MPU_Region_InitTypeDef structure that contains
-  *                  the initialization and configuration information.
-  * @retval None
-  */
-void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)
-{
- 80012dc:	b480      	push	{r7}
- 80012de:	b083      	sub	sp, #12
- 80012e0:	af00      	add	r7, sp, #0
- 80012e2:	6078      	str	r0, [r7, #4]
-  /* Check the parameters */
-  assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number));
-  assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable));
-
-  /* Set the Region number */
-  MPU->RNR = MPU_Init->Number;
- 80012e4:	687b      	ldr	r3, [r7, #4]
- 80012e6:	785a      	ldrb	r2, [r3, #1]
- 80012e8:	4b1d      	ldr	r3, [pc, #116]	; (8001360 <HAL_MPU_ConfigRegion+0x84>)
- 80012ea:	609a      	str	r2, [r3, #8]
-
-  if ((MPU_Init->Enable) != 0UL)
- 80012ec:	687b      	ldr	r3, [r7, #4]
- 80012ee:	781b      	ldrb	r3, [r3, #0]
- 80012f0:	2b00      	cmp	r3, #0
- 80012f2:	d029      	beq.n	8001348 <HAL_MPU_ConfigRegion+0x6c>
-    assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));
-    assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));
-    assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));
-    assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));
-
-    MPU->RBAR = MPU_Init->BaseAddress;
- 80012f4:	4a1a      	ldr	r2, [pc, #104]	; (8001360 <HAL_MPU_ConfigRegion+0x84>)
- 80012f6:	687b      	ldr	r3, [r7, #4]
- 80012f8:	685b      	ldr	r3, [r3, #4]
- 80012fa:	60d3      	str	r3, [r2, #12]
-    MPU->RASR = ((uint32_t)MPU_Init->DisableExec             << MPU_RASR_XN_Pos)   |
- 80012fc:	687b      	ldr	r3, [r7, #4]
- 80012fe:	7b1b      	ldrb	r3, [r3, #12]
- 8001300:	071a      	lsls	r2, r3, #28
-                ((uint32_t)MPU_Init->AccessPermission        << MPU_RASR_AP_Pos)   |
- 8001302:	687b      	ldr	r3, [r7, #4]
- 8001304:	7adb      	ldrb	r3, [r3, #11]
- 8001306:	061b      	lsls	r3, r3, #24
-    MPU->RASR = ((uint32_t)MPU_Init->DisableExec             << MPU_RASR_XN_Pos)   |
- 8001308:	431a      	orrs	r2, r3
-                ((uint32_t)MPU_Init->TypeExtField            << MPU_RASR_TEX_Pos)  |
- 800130a:	687b      	ldr	r3, [r7, #4]
- 800130c:	7a9b      	ldrb	r3, [r3, #10]
- 800130e:	04db      	lsls	r3, r3, #19
-                ((uint32_t)MPU_Init->AccessPermission        << MPU_RASR_AP_Pos)   |
- 8001310:	431a      	orrs	r2, r3
-                ((uint32_t)MPU_Init->IsShareable             << MPU_RASR_S_Pos)    |
- 8001312:	687b      	ldr	r3, [r7, #4]
- 8001314:	7b5b      	ldrb	r3, [r3, #13]
- 8001316:	049b      	lsls	r3, r3, #18
-                ((uint32_t)MPU_Init->TypeExtField            << MPU_RASR_TEX_Pos)  |
- 8001318:	431a      	orrs	r2, r3
-                ((uint32_t)MPU_Init->IsCacheable             << MPU_RASR_C_Pos)    |
- 800131a:	687b      	ldr	r3, [r7, #4]
- 800131c:	7b9b      	ldrb	r3, [r3, #14]
- 800131e:	045b      	lsls	r3, r3, #17
-                ((uint32_t)MPU_Init->IsShareable             << MPU_RASR_S_Pos)    |
- 8001320:	431a      	orrs	r2, r3
-                ((uint32_t)MPU_Init->IsBufferable            << MPU_RASR_B_Pos)    |
- 8001322:	687b      	ldr	r3, [r7, #4]
- 8001324:	7bdb      	ldrb	r3, [r3, #15]
- 8001326:	041b      	lsls	r3, r3, #16
-                ((uint32_t)MPU_Init->IsCacheable             << MPU_RASR_C_Pos)    |
- 8001328:	431a      	orrs	r2, r3
-                ((uint32_t)MPU_Init->SubRegionDisable        << MPU_RASR_SRD_Pos)  |
- 800132a:	687b      	ldr	r3, [r7, #4]
- 800132c:	7a5b      	ldrb	r3, [r3, #9]
- 800132e:	021b      	lsls	r3, r3, #8
-                ((uint32_t)MPU_Init->IsBufferable            << MPU_RASR_B_Pos)    |
- 8001330:	431a      	orrs	r2, r3
-                ((uint32_t)MPU_Init->Size                    << MPU_RASR_SIZE_Pos) |
- 8001332:	687b      	ldr	r3, [r7, #4]
- 8001334:	7a1b      	ldrb	r3, [r3, #8]
- 8001336:	005b      	lsls	r3, r3, #1
-                ((uint32_t)MPU_Init->SubRegionDisable        << MPU_RASR_SRD_Pos)  |
- 8001338:	4313      	orrs	r3, r2
-                ((uint32_t)MPU_Init->Enable                  << MPU_RASR_ENABLE_Pos);
- 800133a:	687a      	ldr	r2, [r7, #4]
- 800133c:	7812      	ldrb	r2, [r2, #0]
- 800133e:	4611      	mov	r1, r2
-    MPU->RASR = ((uint32_t)MPU_Init->DisableExec             << MPU_RASR_XN_Pos)   |
- 8001340:	4a07      	ldr	r2, [pc, #28]	; (8001360 <HAL_MPU_ConfigRegion+0x84>)
-                ((uint32_t)MPU_Init->Size                    << MPU_RASR_SIZE_Pos) |
- 8001342:	430b      	orrs	r3, r1
-    MPU->RASR = ((uint32_t)MPU_Init->DisableExec             << MPU_RASR_XN_Pos)   |
- 8001344:	6113      	str	r3, [r2, #16]
-  else
-  {
-    MPU->RBAR = 0x00;
-    MPU->RASR = 0x00;
-  }
-}
- 8001346:	e005      	b.n	8001354 <HAL_MPU_ConfigRegion+0x78>
-    MPU->RBAR = 0x00;
- 8001348:	4b05      	ldr	r3, [pc, #20]	; (8001360 <HAL_MPU_ConfigRegion+0x84>)
- 800134a:	2200      	movs	r2, #0
- 800134c:	60da      	str	r2, [r3, #12]
-    MPU->RASR = 0x00;
- 800134e:	4b04      	ldr	r3, [pc, #16]	; (8001360 <HAL_MPU_ConfigRegion+0x84>)
- 8001350:	2200      	movs	r2, #0
- 8001352:	611a      	str	r2, [r3, #16]
-}
- 8001354:	bf00      	nop
- 8001356:	370c      	adds	r7, #12
- 8001358:	46bd      	mov	sp, r7
- 800135a:	f85d 7b04 	ldr.w	r7, [sp], #4
- 800135e:	4770      	bx	lr
- 8001360:	e000ed90 	.word	0xe000ed90
-
-08001364 <HAL_ETH_Init>:
-  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
-  *         the configuration information for ETHERNET module
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)
-{
- 8001364:	b580      	push	{r7, lr}
- 8001366:	b084      	sub	sp, #16
- 8001368:	af00      	add	r7, sp, #0
- 800136a:	6078      	str	r0, [r7, #4]
-  uint32_t tickstart;
-
-  if (heth == NULL)
- 800136c:	687b      	ldr	r3, [r7, #4]
- 800136e:	2b00      	cmp	r3, #0
- 8001370:	d101      	bne.n	8001376 <HAL_ETH_Init+0x12>
-  {
-    return HAL_ERROR;
- 8001372:	2301      	movs	r3, #1
- 8001374:	e0cf      	b.n	8001516 <HAL_ETH_Init+0x1b2>
-  }
-  if (heth->gState == HAL_ETH_STATE_RESET)
- 8001376:	687b      	ldr	r3, [r7, #4]
- 8001378:	f8d3 3084 	ldr.w	r3, [r3, #132]	; 0x84
- 800137c:	2b00      	cmp	r3, #0
- 800137e:	d106      	bne.n	800138e <HAL_ETH_Init+0x2a>
-  {
-    heth->gState = HAL_ETH_STATE_BUSY;
- 8001380:	687b      	ldr	r3, [r7, #4]
- 8001382:	2223      	movs	r2, #35	; 0x23
- 8001384:	f8c3 2084 	str.w	r2, [r3, #132]	; 0x84
-
-    /* Init the low level hardware */
-    heth->MspInitCallback(heth);
-#else
-    /* Init the low level hardware : GPIO, CLOCK, NVIC. */
-    HAL_ETH_MspInit(heth);
- 8001388:	6878      	ldr	r0, [r7, #4]
- 800138a:	f003 fe99 	bl	80050c0 <HAL_ETH_MspInit>
-
-#endif /* (USE_HAL_ETH_REGISTER_CALLBACKS) */
-  }
-
-  __HAL_RCC_SYSCFG_CLK_ENABLE();
- 800138e:	4b64      	ldr	r3, [pc, #400]	; (8001520 <HAL_ETH_Init+0x1bc>)
- 8001390:	f8d3 30f4 	ldr.w	r3, [r3, #244]	; 0xf4
- 8001394:	4a62      	ldr	r2, [pc, #392]	; (8001520 <HAL_ETH_Init+0x1bc>)
- 8001396:	f043 0302 	orr.w	r3, r3, #2
- 800139a:	f8c2 30f4 	str.w	r3, [r2, #244]	; 0xf4
- 800139e:	4b60      	ldr	r3, [pc, #384]	; (8001520 <HAL_ETH_Init+0x1bc>)
- 80013a0:	f8d3 30f4 	ldr.w	r3, [r3, #244]	; 0xf4
- 80013a4:	f003 0302 	and.w	r3, r3, #2
- 80013a8:	60bb      	str	r3, [r7, #8]
- 80013aa:	68bb      	ldr	r3, [r7, #8]
-
-  if (heth->Init.MediaInterface == HAL_ETH_MII_MODE)
- 80013ac:	687b      	ldr	r3, [r7, #4]
- 80013ae:	7a1b      	ldrb	r3, [r3, #8]
- 80013b0:	2b00      	cmp	r3, #0
- 80013b2:	d103      	bne.n	80013bc <HAL_ETH_Init+0x58>
-  {
-    HAL_SYSCFG_ETHInterfaceSelect(SYSCFG_ETH_MII);
- 80013b4:	2000      	movs	r0, #0
- 80013b6:	f7ff fe35 	bl	8001024 <HAL_SYSCFG_ETHInterfaceSelect>
- 80013ba:	e003      	b.n	80013c4 <HAL_ETH_Init+0x60>
-  }
-  else
-  {
-    HAL_SYSCFG_ETHInterfaceSelect(SYSCFG_ETH_RMII);
- 80013bc:	f44f 0000 	mov.w	r0, #8388608	; 0x800000
- 80013c0:	f7ff fe30 	bl	8001024 <HAL_SYSCFG_ETHInterfaceSelect>
-  }
-
-  /* Dummy read to sync with ETH */
-  (void)SYSCFG->PMCR;
- 80013c4:	4b57      	ldr	r3, [pc, #348]	; (8001524 <HAL_ETH_Init+0x1c0>)
- 80013c6:	685b      	ldr	r3, [r3, #4]
-
-  /* Ethernet Software reset */
-  /* Set the SWR bit: resets all MAC subsystem internal registers and logic */
-  /* After reset all the registers holds their respective reset values */
-  SET_BIT(heth->Instance->DMAMR, ETH_DMAMR_SWR);
- 80013c8:	687b      	ldr	r3, [r7, #4]
- 80013ca:	681b      	ldr	r3, [r3, #0]
- 80013cc:	f503 5380 	add.w	r3, r3, #4096	; 0x1000
- 80013d0:	681b      	ldr	r3, [r3, #0]
- 80013d2:	687a      	ldr	r2, [r7, #4]
- 80013d4:	6812      	ldr	r2, [r2, #0]
- 80013d6:	f043 0301 	orr.w	r3, r3, #1
- 80013da:	f502 5280 	add.w	r2, r2, #4096	; 0x1000
- 80013de:	6013      	str	r3, [r2, #0]
-
-  /* Get tick */
-  tickstart = HAL_GetTick();
- 80013e0:	f7ff fe14 	bl	800100c <HAL_GetTick>
- 80013e4:	60f8      	str	r0, [r7, #12]
-
-  /* Wait for software reset */
-  while (READ_BIT(heth->Instance->DMAMR, ETH_DMAMR_SWR) > 0U)
- 80013e6:	e011      	b.n	800140c <HAL_ETH_Init+0xa8>
-  {
-    if (((HAL_GetTick() - tickstart) > ETH_SWRESET_TIMEOUT))
- 80013e8:	f7ff fe10 	bl	800100c <HAL_GetTick>
- 80013ec:	4602      	mov	r2, r0
- 80013ee:	68fb      	ldr	r3, [r7, #12]
- 80013f0:	1ad3      	subs	r3, r2, r3
- 80013f2:	f5b3 7ffa 	cmp.w	r3, #500	; 0x1f4
- 80013f6:	d909      	bls.n	800140c <HAL_ETH_Init+0xa8>
-    {
-      /* Set Error Code */
-      heth->ErrorCode = HAL_ETH_ERROR_TIMEOUT;
- 80013f8:	687b      	ldr	r3, [r7, #4]
- 80013fa:	2204      	movs	r2, #4
- 80013fc:	f8c3 2088 	str.w	r2, [r3, #136]	; 0x88
-      /* Set State as Error */
-      heth->gState = HAL_ETH_STATE_ERROR;
- 8001400:	687b      	ldr	r3, [r7, #4]
- 8001402:	22e0      	movs	r2, #224	; 0xe0
- 8001404:	f8c3 2084 	str.w	r2, [r3, #132]	; 0x84
-      /* Return Error */
-      return HAL_ERROR;
- 8001408:	2301      	movs	r3, #1
- 800140a:	e084      	b.n	8001516 <HAL_ETH_Init+0x1b2>
-  while (READ_BIT(heth->Instance->DMAMR, ETH_DMAMR_SWR) > 0U)
- 800140c:	687b      	ldr	r3, [r7, #4]
- 800140e:	681b      	ldr	r3, [r3, #0]
- 8001410:	f503 5380 	add.w	r3, r3, #4096	; 0x1000
- 8001414:	681b      	ldr	r3, [r3, #0]
- 8001416:	f003 0301 	and.w	r3, r3, #1
- 800141a:	2b00      	cmp	r3, #0
- 800141c:	d1e4      	bne.n	80013e8 <HAL_ETH_Init+0x84>
-    }
-  }
-
-  /*------------------ MDIO CSR Clock Range Configuration --------------------*/
-  HAL_ETH_SetMDIOClockRange(heth);
- 800141e:	6878      	ldr	r0, [r7, #4]
- 8001420:	f000 fee0 	bl	80021e4 <HAL_ETH_SetMDIOClockRange>
-
-  /*------------------ MAC LPI 1US Tic Counter Configuration --------------------*/
-  WRITE_REG(heth->Instance->MAC1USTCR, (((uint32_t)HAL_RCC_GetHCLKFreq() / ETH_MAC_US_TICK) - 1U));
- 8001424:	f002 fd96 	bl	8003f54 <HAL_RCC_GetHCLKFreq>
- 8001428:	4603      	mov	r3, r0
- 800142a:	4a3f      	ldr	r2, [pc, #252]	; (8001528 <HAL_ETH_Init+0x1c4>)
- 800142c:	fba2 2303 	umull	r2, r3, r2, r3
- 8001430:	0c9a      	lsrs	r2, r3, #18
- 8001432:	687b      	ldr	r3, [r7, #4]
- 8001434:	681b      	ldr	r3, [r3, #0]
- 8001436:	3a01      	subs	r2, #1
- 8001438:	f8c3 20dc 	str.w	r2, [r3, #220]	; 0xdc
-
-  /*------------------ MAC, MTL and DMA default Configuration ----------------*/
-  ETH_MACDMAConfig(heth);
- 800143c:	6878      	ldr	r0, [r7, #4]
- 800143e:	f001 f8cb 	bl	80025d8 <ETH_MACDMAConfig>
-
-  /* SET DSL to 64 bit */
-  MODIFY_REG(heth->Instance->DMACCR, ETH_DMACCR_DSL, ETH_DMACCR_DSL_64BIT);
- 8001442:	687b      	ldr	r3, [r7, #4]
- 8001444:	681b      	ldr	r3, [r3, #0]
- 8001446:	f503 5380 	add.w	r3, r3, #4096	; 0x1000
- 800144a:	f8d3 3100 	ldr.w	r3, [r3, #256]	; 0x100
- 800144e:	f423 13e0 	bic.w	r3, r3, #1835008	; 0x1c0000
- 8001452:	687a      	ldr	r2, [r7, #4]
- 8001454:	6812      	ldr	r2, [r2, #0]
- 8001456:	f443 2300 	orr.w	r3, r3, #524288	; 0x80000
- 800145a:	f502 5280 	add.w	r2, r2, #4096	; 0x1000
- 800145e:	f8c2 3100 	str.w	r3, [r2, #256]	; 0x100
-
-  /* Set Receive Buffers Length (must be a multiple of 4) */
-  if ((heth->Init.RxBuffLen % 0x4U) != 0x0U)
- 8001462:	687b      	ldr	r3, [r7, #4]
- 8001464:	695b      	ldr	r3, [r3, #20]
- 8001466:	f003 0303 	and.w	r3, r3, #3
- 800146a:	2b00      	cmp	r3, #0
- 800146c:	d009      	beq.n	8001482 <HAL_ETH_Init+0x11e>
-  {
-    /* Set Error Code */
-    heth->ErrorCode = HAL_ETH_ERROR_PARAM;
- 800146e:	687b      	ldr	r3, [r7, #4]
- 8001470:	2201      	movs	r2, #1
- 8001472:	f8c3 2088 	str.w	r2, [r3, #136]	; 0x88
-    /* Set State as Error */
-    heth->gState = HAL_ETH_STATE_ERROR;
- 8001476:	687b      	ldr	r3, [r7, #4]
- 8001478:	22e0      	movs	r2, #224	; 0xe0
- 800147a:	f8c3 2084 	str.w	r2, [r3, #132]	; 0x84
-    /* Return Error */
-    return HAL_ERROR;
- 800147e:	2301      	movs	r3, #1
- 8001480:	e049      	b.n	8001516 <HAL_ETH_Init+0x1b2>
-  }
-  else
-  {
-    MODIFY_REG(heth->Instance->DMACRCR, ETH_DMACRCR_RBSZ, ((heth->Init.RxBuffLen) << 1));
- 8001482:	687b      	ldr	r3, [r7, #4]
- 8001484:	681b      	ldr	r3, [r3, #0]
- 8001486:	f503 5380 	add.w	r3, r3, #4096	; 0x1000
- 800148a:	f8d3 2108 	ldr.w	r2, [r3, #264]	; 0x108
- 800148e:	4b27      	ldr	r3, [pc, #156]	; (800152c <HAL_ETH_Init+0x1c8>)
- 8001490:	4013      	ands	r3, r2
- 8001492:	687a      	ldr	r2, [r7, #4]
- 8001494:	6952      	ldr	r2, [r2, #20]
- 8001496:	0051      	lsls	r1, r2, #1
- 8001498:	687a      	ldr	r2, [r7, #4]
- 800149a:	6812      	ldr	r2, [r2, #0]
- 800149c:	430b      	orrs	r3, r1
- 800149e:	f502 5280 	add.w	r2, r2, #4096	; 0x1000
- 80014a2:	f8c2 3108 	str.w	r3, [r2, #264]	; 0x108
-  }
-
-  /*------------------ DMA Tx Descriptors Configuration ----------------------*/
-  ETH_DMATxDescListInit(heth);
- 80014a6:	6878      	ldr	r0, [r7, #4]
- 80014a8:	f001 f933 	bl	8002712 <ETH_DMATxDescListInit>
-
-  /*------------------ DMA Rx Descriptors Configuration ----------------------*/
-  ETH_DMARxDescListInit(heth);
- 80014ac:	6878      	ldr	r0, [r7, #4]
- 80014ae:	f001 f979 	bl	80027a4 <ETH_DMARxDescListInit>
-
-  /*--------------------- ETHERNET MAC Address Configuration ------------------*/
-  /* Set MAC addr bits 32 to 47 */
-  heth->Instance->MACA0HR = (((uint32_t)(heth->Init.MACAddr[5]) << 8) | (uint32_t)heth->Init.MACAddr[4]);
- 80014b2:	687b      	ldr	r3, [r7, #4]
- 80014b4:	685b      	ldr	r3, [r3, #4]
- 80014b6:	3305      	adds	r3, #5
- 80014b8:	781b      	ldrb	r3, [r3, #0]
- 80014ba:	021a      	lsls	r2, r3, #8
- 80014bc:	687b      	ldr	r3, [r7, #4]
- 80014be:	685b      	ldr	r3, [r3, #4]
- 80014c0:	3304      	adds	r3, #4
- 80014c2:	781b      	ldrb	r3, [r3, #0]
- 80014c4:	4619      	mov	r1, r3
- 80014c6:	687b      	ldr	r3, [r7, #4]
- 80014c8:	681b      	ldr	r3, [r3, #0]
- 80014ca:	430a      	orrs	r2, r1
- 80014cc:	f8c3 2300 	str.w	r2, [r3, #768]	; 0x300
-  /* Set MAC addr bits 0 to 31 */
-  heth->Instance->MACA0LR = (((uint32_t)(heth->Init.MACAddr[3]) << 24) | ((uint32_t)(heth->Init.MACAddr[2]) << 16) |
- 80014d0:	687b      	ldr	r3, [r7, #4]
- 80014d2:	685b      	ldr	r3, [r3, #4]
- 80014d4:	3303      	adds	r3, #3
- 80014d6:	781b      	ldrb	r3, [r3, #0]
- 80014d8:	061a      	lsls	r2, r3, #24
- 80014da:	687b      	ldr	r3, [r7, #4]
- 80014dc:	685b      	ldr	r3, [r3, #4]
- 80014de:	3302      	adds	r3, #2
- 80014e0:	781b      	ldrb	r3, [r3, #0]
- 80014e2:	041b      	lsls	r3, r3, #16
- 80014e4:	431a      	orrs	r2, r3
-                             ((uint32_t)(heth->Init.MACAddr[1]) << 8) | (uint32_t)heth->Init.MACAddr[0]);
- 80014e6:	687b      	ldr	r3, [r7, #4]
- 80014e8:	685b      	ldr	r3, [r3, #4]
- 80014ea:	3301      	adds	r3, #1
- 80014ec:	781b      	ldrb	r3, [r3, #0]
- 80014ee:	021b      	lsls	r3, r3, #8
-  heth->Instance->MACA0LR = (((uint32_t)(heth->Init.MACAddr[3]) << 24) | ((uint32_t)(heth->Init.MACAddr[2]) << 16) |
- 80014f0:	431a      	orrs	r2, r3
-                             ((uint32_t)(heth->Init.MACAddr[1]) << 8) | (uint32_t)heth->Init.MACAddr[0]);
- 80014f2:	687b      	ldr	r3, [r7, #4]
- 80014f4:	685b      	ldr	r3, [r3, #4]
- 80014f6:	781b      	ldrb	r3, [r3, #0]
- 80014f8:	4619      	mov	r1, r3
-  heth->Instance->MACA0LR = (((uint32_t)(heth->Init.MACAddr[3]) << 24) | ((uint32_t)(heth->Init.MACAddr[2]) << 16) |
- 80014fa:	687b      	ldr	r3, [r7, #4]
- 80014fc:	681b      	ldr	r3, [r3, #0]
-                             ((uint32_t)(heth->Init.MACAddr[1]) << 8) | (uint32_t)heth->Init.MACAddr[0]);
- 80014fe:	430a      	orrs	r2, r1
-  heth->Instance->MACA0LR = (((uint32_t)(heth->Init.MACAddr[3]) << 24) | ((uint32_t)(heth->Init.MACAddr[2]) << 16) |
- 8001500:	f8c3 2304 	str.w	r2, [r3, #772]	; 0x304
-
-  heth->ErrorCode = HAL_ETH_ERROR_NONE;
- 8001504:	687b      	ldr	r3, [r7, #4]
- 8001506:	2200      	movs	r2, #0
- 8001508:	f8c3 2088 	str.w	r2, [r3, #136]	; 0x88
-  heth->gState = HAL_ETH_STATE_READY;
- 800150c:	687b      	ldr	r3, [r7, #4]
- 800150e:	2210      	movs	r2, #16
- 8001510:	f8c3 2084 	str.w	r2, [r3, #132]	; 0x84
-
-  return HAL_OK;
- 8001514:	2300      	movs	r3, #0
-}
- 8001516:	4618      	mov	r0, r3
- 8001518:	3710      	adds	r7, #16
- 800151a:	46bd      	mov	sp, r7
- 800151c:	bd80      	pop	{r7, pc}
- 800151e:	bf00      	nop
- 8001520:	58024400 	.word	0x58024400
- 8001524:	58000400 	.word	0x58000400
- 8001528:	431bde83 	.word	0x431bde83
- 800152c:	ffff8001 	.word	0xffff8001
-
-08001530 <HAL_ETH_Start>:
-  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
-  *         the configuration information for ETHERNET module
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth)
-{
- 8001530:	b580      	push	{r7, lr}
- 8001532:	b082      	sub	sp, #8
- 8001534:	af00      	add	r7, sp, #0
- 8001536:	6078      	str	r0, [r7, #4]
-  if (heth->gState == HAL_ETH_STATE_READY)
- 8001538:	687b      	ldr	r3, [r7, #4]
- 800153a:	f8d3 3084 	ldr.w	r3, [r3, #132]	; 0x84
- 800153e:	2b10      	cmp	r3, #16
- 8001540:	d153      	bne.n	80015ea <HAL_ETH_Start+0xba>
-  {
-    heth->gState = HAL_ETH_STATE_BUSY;
- 8001542:	687b      	ldr	r3, [r7, #4]
- 8001544:	2223      	movs	r2, #35	; 0x23
- 8001546:	f8c3 2084 	str.w	r2, [r3, #132]	; 0x84
-
-    /* Set nombre of descriptors to build */
-    heth->RxDescList.RxBuildDescCnt = ETH_RX_DESC_CNT;
- 800154a:	687b      	ldr	r3, [r7, #4]
- 800154c:	2204      	movs	r2, #4
- 800154e:	66da      	str	r2, [r3, #108]	; 0x6c
-
-    /* Build all descriptors */
-    ETH_UpdateDescriptor(heth);
- 8001550:	6878      	ldr	r0, [r7, #4]
- 8001552:	f000 f9f6 	bl	8001942 <ETH_UpdateDescriptor>
-
-    /* Enable the MAC transmission */
-    SET_BIT(heth->Instance->MACCR, ETH_MACCR_TE);
- 8001556:	687b      	ldr	r3, [r7, #4]
- 8001558:	681b      	ldr	r3, [r3, #0]
- 800155a:	681a      	ldr	r2, [r3, #0]
- 800155c:	687b      	ldr	r3, [r7, #4]
- 800155e:	681b      	ldr	r3, [r3, #0]
- 8001560:	f042 0202 	orr.w	r2, r2, #2
- 8001564:	601a      	str	r2, [r3, #0]
-
-    /* Enable the MAC reception */
-    SET_BIT(heth->Instance->MACCR, ETH_MACCR_RE);
- 8001566:	687b      	ldr	r3, [r7, #4]
- 8001568:	681b      	ldr	r3, [r3, #0]
- 800156a:	681a      	ldr	r2, [r3, #0]
- 800156c:	687b      	ldr	r3, [r7, #4]
- 800156e:	681b      	ldr	r3, [r3, #0]
- 8001570:	f042 0201 	orr.w	r2, r2, #1
- 8001574:	601a      	str	r2, [r3, #0]
-
-    /* Set the Flush Transmit FIFO bit */
-    SET_BIT(heth->Instance->MTLTQOMR, ETH_MTLTQOMR_FTQ);
- 8001576:	687b      	ldr	r3, [r7, #4]
- 8001578:	681b      	ldr	r3, [r3, #0]
- 800157a:	f8d3 2d00 	ldr.w	r2, [r3, #3328]	; 0xd00
- 800157e:	687b      	ldr	r3, [r7, #4]
- 8001580:	681b      	ldr	r3, [r3, #0]
- 8001582:	f042 0201 	orr.w	r2, r2, #1
- 8001586:	f8c3 2d00 	str.w	r2, [r3, #3328]	; 0xd00
-
-    /* Enable the DMA transmission */
-    SET_BIT(heth->Instance->DMACTCR, ETH_DMACTCR_ST);
- 800158a:	687b      	ldr	r3, [r7, #4]
- 800158c:	681b      	ldr	r3, [r3, #0]
- 800158e:	f503 5380 	add.w	r3, r3, #4096	; 0x1000
- 8001592:	f8d3 3104 	ldr.w	r3, [r3, #260]	; 0x104
- 8001596:	687a      	ldr	r2, [r7, #4]
- 8001598:	6812      	ldr	r2, [r2, #0]
- 800159a:	f043 0301 	orr.w	r3, r3, #1
- 800159e:	f502 5280 	add.w	r2, r2, #4096	; 0x1000
- 80015a2:	f8c2 3104 	str.w	r3, [r2, #260]	; 0x104
-
-    /* Enable the DMA reception */
-    SET_BIT(heth->Instance->DMACRCR, ETH_DMACRCR_SR);
- 80015a6:	687b      	ldr	r3, [r7, #4]
- 80015a8:	681b      	ldr	r3, [r3, #0]
- 80015aa:	f503 5380 	add.w	r3, r3, #4096	; 0x1000
- 80015ae:	f8d3 3108 	ldr.w	r3, [r3, #264]	; 0x108
- 80015b2:	687a      	ldr	r2, [r7, #4]
- 80015b4:	6812      	ldr	r2, [r2, #0]
- 80015b6:	f043 0301 	orr.w	r3, r3, #1
- 80015ba:	f502 5280 	add.w	r2, r2, #4096	; 0x1000
- 80015be:	f8c2 3108 	str.w	r3, [r2, #264]	; 0x108
-
-    /* Clear Tx and Rx process stopped flags */
-    heth->Instance->DMACSR |= (ETH_DMACSR_TPS | ETH_DMACSR_RPS);
- 80015c2:	687b      	ldr	r3, [r7, #4]
- 80015c4:	681b      	ldr	r3, [r3, #0]
- 80015c6:	f503 5380 	add.w	r3, r3, #4096	; 0x1000
- 80015ca:	f8d3 3160 	ldr.w	r3, [r3, #352]	; 0x160
- 80015ce:	687a      	ldr	r2, [r7, #4]
- 80015d0:	6812      	ldr	r2, [r2, #0]
- 80015d2:	f443 7381 	orr.w	r3, r3, #258	; 0x102
- 80015d6:	f502 5280 	add.w	r2, r2, #4096	; 0x1000
- 80015da:	f8c2 3160 	str.w	r3, [r2, #352]	; 0x160
-
-    heth->gState = HAL_ETH_STATE_STARTED;
- 80015de:	687b      	ldr	r3, [r7, #4]
- 80015e0:	2223      	movs	r2, #35	; 0x23
- 80015e2:	f8c3 2084 	str.w	r2, [r3, #132]	; 0x84
-
-    return HAL_OK;
- 80015e6:	2300      	movs	r3, #0
- 80015e8:	e000      	b.n	80015ec <HAL_ETH_Start+0xbc>
-  }
-  else
-  {
-    return HAL_ERROR;
- 80015ea:	2301      	movs	r3, #1
-  }
-}
- 80015ec:	4618      	mov	r0, r3
- 80015ee:	3708      	adds	r7, #8
- 80015f0:	46bd      	mov	sp, r7
- 80015f2:	bd80      	pop	{r7, pc}
-
-080015f4 <HAL_ETH_Stop>:
-  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
-  *         the configuration information for ETHERNET module
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth)
-{
- 80015f4:	b480      	push	{r7}
- 80015f6:	b083      	sub	sp, #12
- 80015f8:	af00      	add	r7, sp, #0
- 80015fa:	6078      	str	r0, [r7, #4]
-  if (heth->gState == HAL_ETH_STATE_STARTED)
- 80015fc:	687b      	ldr	r3, [r7, #4]
- 80015fe:	f8d3 3084 	ldr.w	r3, [r3, #132]	; 0x84
- 8001602:	2b23      	cmp	r3, #35	; 0x23
- 8001604:	d13f      	bne.n	8001686 <HAL_ETH_Stop+0x92>
-  {
-    /* Set the ETH peripheral state to BUSY */
-    heth->gState = HAL_ETH_STATE_BUSY;
- 8001606:	687b      	ldr	r3, [r7, #4]
- 8001608:	2223      	movs	r2, #35	; 0x23
- 800160a:	f8c3 2084 	str.w	r2, [r3, #132]	; 0x84
-    /* Disable the DMA transmission */
-    CLEAR_BIT(heth->Instance->DMACTCR, ETH_DMACTCR_ST);
- 800160e:	687b      	ldr	r3, [r7, #4]
- 8001610:	681b      	ldr	r3, [r3, #0]
- 8001612:	f503 5380 	add.w	r3, r3, #4096	; 0x1000
- 8001616:	f8d3 3104 	ldr.w	r3, [r3, #260]	; 0x104
- 800161a:	687a      	ldr	r2, [r7, #4]
- 800161c:	6812      	ldr	r2, [r2, #0]
- 800161e:	f023 0301 	bic.w	r3, r3, #1
- 8001622:	f502 5280 	add.w	r2, r2, #4096	; 0x1000
- 8001626:	f8c2 3104 	str.w	r3, [r2, #260]	; 0x104
-
-    /* Disable the DMA reception */
-    CLEAR_BIT(heth->Instance->DMACRCR, ETH_DMACRCR_SR);
- 800162a:	687b      	ldr	r3, [r7, #4]
- 800162c:	681b      	ldr	r3, [r3, #0]
- 800162e:	f503 5380 	add.w	r3, r3, #4096	; 0x1000
- 8001632:	f8d3 3108 	ldr.w	r3, [r3, #264]	; 0x108
- 8001636:	687a      	ldr	r2, [r7, #4]
- 8001638:	6812      	ldr	r2, [r2, #0]
- 800163a:	f023 0301 	bic.w	r3, r3, #1
- 800163e:	f502 5280 	add.w	r2, r2, #4096	; 0x1000
- 8001642:	f8c2 3108 	str.w	r3, [r2, #264]	; 0x108
-
-    /* Disable the MAC reception */
-    CLEAR_BIT(heth->Instance->MACCR, ETH_MACCR_RE);
- 8001646:	687b      	ldr	r3, [r7, #4]
- 8001648:	681b      	ldr	r3, [r3, #0]
- 800164a:	681a      	ldr	r2, [r3, #0]
- 800164c:	687b      	ldr	r3, [r7, #4]
- 800164e:	681b      	ldr	r3, [r3, #0]
- 8001650:	f022 0201 	bic.w	r2, r2, #1
- 8001654:	601a      	str	r2, [r3, #0]
-
-    /* Set the Flush Transmit FIFO bit */
-    SET_BIT(heth->Instance->MTLTQOMR, ETH_MTLTQOMR_FTQ);
- 8001656:	687b      	ldr	r3, [r7, #4]
- 8001658:	681b      	ldr	r3, [r3, #0]
- 800165a:	f8d3 2d00 	ldr.w	r2, [r3, #3328]	; 0xd00
- 800165e:	687b      	ldr	r3, [r7, #4]
- 8001660:	681b      	ldr	r3, [r3, #0]
- 8001662:	f042 0201 	orr.w	r2, r2, #1
- 8001666:	f8c3 2d00 	str.w	r2, [r3, #3328]	; 0xd00
-
-    /* Disable the MAC transmission */
-    CLEAR_BIT(heth->Instance->MACCR, ETH_MACCR_TE);
- 800166a:	687b      	ldr	r3, [r7, #4]
- 800166c:	681b      	ldr	r3, [r3, #0]
- 800166e:	681a      	ldr	r2, [r3, #0]
- 8001670:	687b      	ldr	r3, [r7, #4]
- 8001672:	681b      	ldr	r3, [r3, #0]
- 8001674:	f022 0202 	bic.w	r2, r2, #2
- 8001678:	601a      	str	r2, [r3, #0]
-
-    heth->gState = HAL_ETH_STATE_READY;
- 800167a:	687b      	ldr	r3, [r7, #4]
- 800167c:	2210      	movs	r2, #16
- 800167e:	f8c3 2084 	str.w	r2, [r3, #132]	; 0x84
-
-    /* Return function status */
-    return HAL_OK;
- 8001682:	2300      	movs	r3, #0
- 8001684:	e000      	b.n	8001688 <HAL_ETH_Stop+0x94>
-  }
-  else
-  {
-    return HAL_ERROR;
- 8001686:	2301      	movs	r3, #1
-  }
-}
- 8001688:	4618      	mov	r0, r3
- 800168a:	370c      	adds	r7, #12
- 800168c:	46bd      	mov	sp, r7
- 800168e:	f85d 7b04 	ldr.w	r7, [sp], #4
- 8001692:	4770      	bx	lr
-
-08001694 <HAL_ETH_Transmit>:
-  * @param  pTxConfig: Hold the configuration of packet to be transmitted
-  * @param  Timeout: timeout value
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_ETH_Transmit(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig, uint32_t Timeout)
-{
- 8001694:	b580      	push	{r7, lr}
- 8001696:	b086      	sub	sp, #24
- 8001698:	af00      	add	r7, sp, #0
- 800169a:	60f8      	str	r0, [r7, #12]
- 800169c:	60b9      	str	r1, [r7, #8]
- 800169e:	607a      	str	r2, [r7, #4]
-  uint32_t tickstart;
-  ETH_DMADescTypeDef *dmatxdesc;
-
-  if (pTxConfig == NULL)
- 80016a0:	68bb      	ldr	r3, [r7, #8]
- 80016a2:	2b00      	cmp	r3, #0
- 80016a4:	d109      	bne.n	80016ba <HAL_ETH_Transmit+0x26>
-  {
-    heth->ErrorCode |= HAL_ETH_ERROR_PARAM;
- 80016a6:	68fb      	ldr	r3, [r7, #12]
- 80016a8:	f8d3 3088 	ldr.w	r3, [r3, #136]	; 0x88
- 80016ac:	f043 0201 	orr.w	r2, r3, #1
- 80016b0:	68fb      	ldr	r3, [r7, #12]
- 80016b2:	f8c3 2088 	str.w	r2, [r3, #136]	; 0x88
-    return HAL_ERROR;
- 80016b6:	2301      	movs	r3, #1
- 80016b8:	e07f      	b.n	80017ba <HAL_ETH_Transmit+0x126>
-  }
-
-  if (heth->gState == HAL_ETH_STATE_STARTED)
- 80016ba:	68fb      	ldr	r3, [r7, #12]
- 80016bc:	f8d3 3084 	ldr.w	r3, [r3, #132]	; 0x84
- 80016c0:	2b23      	cmp	r3, #35	; 0x23
- 80016c2:	d179      	bne.n	80017b8 <HAL_ETH_Transmit+0x124>
-  {
-    /* Config DMA Tx descriptor by Tx Packet info */
-    if (ETH_Prepare_Tx_Descriptors(heth, pTxConfig, 0) != HAL_ETH_ERROR_NONE)
- 80016c4:	2200      	movs	r2, #0
- 80016c6:	68b9      	ldr	r1, [r7, #8]
- 80016c8:	68f8      	ldr	r0, [r7, #12]
- 80016ca:	f001 f8c9 	bl	8002860 <ETH_Prepare_Tx_Descriptors>
- 80016ce:	4603      	mov	r3, r0
- 80016d0:	2b00      	cmp	r3, #0
- 80016d2:	d009      	beq.n	80016e8 <HAL_ETH_Transmit+0x54>
-    {
-      /* Set the ETH error code */
-      heth->ErrorCode |= HAL_ETH_ERROR_BUSY;
- 80016d4:	68fb      	ldr	r3, [r7, #12]
- 80016d6:	f8d3 3088 	ldr.w	r3, [r3, #136]	; 0x88
- 80016da:	f043 0202 	orr.w	r2, r3, #2
- 80016de:	68fb      	ldr	r3, [r7, #12]
- 80016e0:	f8c3 2088 	str.w	r2, [r3, #136]	; 0x88
-      return HAL_ERROR;
- 80016e4:	2301      	movs	r3, #1
- 80016e6:	e068      	b.n	80017ba <HAL_ETH_Transmit+0x126>
-  __ASM volatile ("dsb 0xF":::"memory");
- 80016e8:	f3bf 8f4f 	dsb	sy
-}
- 80016ec:	bf00      	nop
-    }
-
-    /* Ensure completion of descriptor preparation before transmission start */
-    __DSB();
-
-    dmatxdesc = (ETH_DMADescTypeDef *)(&heth->TxDescList)->TxDesc[heth->TxDescList.CurTxDesc];
- 80016ee:	68fb      	ldr	r3, [r7, #12]
- 80016f0:	6a9a      	ldr	r2, [r3, #40]	; 0x28
- 80016f2:	68fb      	ldr	r3, [r7, #12]
- 80016f4:	3206      	adds	r2, #6
- 80016f6:	f853 3022 	ldr.w	r3, [r3, r2, lsl #2]
- 80016fa:	617b      	str	r3, [r7, #20]
-
-    /* Incr current tx desc index */
-    INCR_TX_DESC_INDEX(heth->TxDescList.CurTxDesc, 1U);
- 80016fc:	68fb      	ldr	r3, [r7, #12]
- 80016fe:	6a9b      	ldr	r3, [r3, #40]	; 0x28
- 8001700:	1c5a      	adds	r2, r3, #1
- 8001702:	68fb      	ldr	r3, [r7, #12]
- 8001704:	629a      	str	r2, [r3, #40]	; 0x28
- 8001706:	68fb      	ldr	r3, [r7, #12]
- 8001708:	6a9b      	ldr	r3, [r3, #40]	; 0x28
- 800170a:	2b03      	cmp	r3, #3
- 800170c:	d904      	bls.n	8001718 <HAL_ETH_Transmit+0x84>
- 800170e:	68fb      	ldr	r3, [r7, #12]
- 8001710:	6a9b      	ldr	r3, [r3, #40]	; 0x28
- 8001712:	1f1a      	subs	r2, r3, #4
- 8001714:	68fb      	ldr	r3, [r7, #12]
- 8001716:	629a      	str	r2, [r3, #40]	; 0x28
-
-    /* Start transmission */
-    /* issue a poll command to Tx DMA by writing address of next immediate free descriptor */
-    WRITE_REG(heth->Instance->DMACTDTPR, (uint32_t)(heth->TxDescList.TxDesc[heth->TxDescList.CurTxDesc]));
- 8001718:	68fb      	ldr	r3, [r7, #12]
- 800171a:	6a99      	ldr	r1, [r3, #40]	; 0x28
- 800171c:	68fb      	ldr	r3, [r7, #12]
- 800171e:	681a      	ldr	r2, [r3, #0]
- 8001720:	68fb      	ldr	r3, [r7, #12]
- 8001722:	3106      	adds	r1, #6
- 8001724:	f853 3021 	ldr.w	r3, [r3, r1, lsl #2]
- 8001728:	f502 5280 	add.w	r2, r2, #4096	; 0x1000
- 800172c:	f8c2 3120 	str.w	r3, [r2, #288]	; 0x120
-
-    tickstart = HAL_GetTick();
- 8001730:	f7ff fc6c 	bl	800100c <HAL_GetTick>
- 8001734:	6138      	str	r0, [r7, #16]
-
-    /* Wait for data to be transmitted or timeout occurred */
-    while ((dmatxdesc->DESC3 & ETH_DMATXNDESCWBF_OWN) != (uint32_t)RESET)
- 8001736:	e039      	b.n	80017ac <HAL_ETH_Transmit+0x118>
-    {
-      if ((heth->Instance->DMACSR & ETH_DMACSR_FBE) != (uint32_t)RESET)
- 8001738:	68fb      	ldr	r3, [r7, #12]
- 800173a:	681b      	ldr	r3, [r3, #0]
- 800173c:	f503 5380 	add.w	r3, r3, #4096	; 0x1000
- 8001740:	f8d3 3160 	ldr.w	r3, [r3, #352]	; 0x160
- 8001744:	f403 5380 	and.w	r3, r3, #4096	; 0x1000
- 8001748:	2b00      	cmp	r3, #0
- 800174a:	d012      	beq.n	8001772 <HAL_ETH_Transmit+0xde>
-      {
-        heth->ErrorCode |= HAL_ETH_ERROR_DMA;
- 800174c:	68fb      	ldr	r3, [r7, #12]
- 800174e:	f8d3 3088 	ldr.w	r3, [r3, #136]	; 0x88
- 8001752:	f043 0208 	orr.w	r2, r3, #8
- 8001756:	68fb      	ldr	r3, [r7, #12]
- 8001758:	f8c3 2088 	str.w	r2, [r3, #136]	; 0x88
-        heth->DMAErrorCode = heth->Instance->DMACSR;
- 800175c:	68fb      	ldr	r3, [r7, #12]
- 800175e:	681b      	ldr	r3, [r3, #0]
- 8001760:	f503 5380 	add.w	r3, r3, #4096	; 0x1000
- 8001764:	f8d3 2160 	ldr.w	r2, [r3, #352]	; 0x160
- 8001768:	68fb      	ldr	r3, [r7, #12]
- 800176a:	f8c3 208c 	str.w	r2, [r3, #140]	; 0x8c
-        /* Return function status */
-        return HAL_ERROR;
- 800176e:	2301      	movs	r3, #1
- 8001770:	e023      	b.n	80017ba <HAL_ETH_Transmit+0x126>
-      }
-
-      /* Check for the Timeout */
-      if (Timeout != HAL_MAX_DELAY)
- 8001772:	687b      	ldr	r3, [r7, #4]
- 8001774:	f1b3 3fff 	cmp.w	r3, #4294967295
- 8001778:	d018      	beq.n	80017ac <HAL_ETH_Transmit+0x118>
-      {
-        if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
- 800177a:	f7ff fc47 	bl	800100c <HAL_GetTick>
- 800177e:	4602      	mov	r2, r0
- 8001780:	693b      	ldr	r3, [r7, #16]
- 8001782:	1ad3      	subs	r3, r2, r3
- 8001784:	687a      	ldr	r2, [r7, #4]
- 8001786:	429a      	cmp	r2, r3
- 8001788:	d302      	bcc.n	8001790 <HAL_ETH_Transmit+0xfc>
- 800178a:	687b      	ldr	r3, [r7, #4]
- 800178c:	2b00      	cmp	r3, #0
- 800178e:	d10d      	bne.n	80017ac <HAL_ETH_Transmit+0x118>
-        {
-          heth->ErrorCode |= HAL_ETH_ERROR_TIMEOUT;
- 8001790:	68fb      	ldr	r3, [r7, #12]
- 8001792:	f8d3 3088 	ldr.w	r3, [r3, #136]	; 0x88
- 8001796:	f043 0204 	orr.w	r2, r3, #4
- 800179a:	68fb      	ldr	r3, [r7, #12]
- 800179c:	f8c3 2088 	str.w	r2, [r3, #136]	; 0x88
-          /* Clear TX descriptor so that we can proceed */
-          dmatxdesc->DESC3 = (ETH_DMATXNDESCWBF_FD | ETH_DMATXNDESCWBF_LD);
- 80017a0:	697b      	ldr	r3, [r7, #20]
- 80017a2:	f04f 5240 	mov.w	r2, #805306368	; 0x30000000
- 80017a6:	60da      	str	r2, [r3, #12]
-          return HAL_ERROR;
- 80017a8:	2301      	movs	r3, #1
- 80017aa:	e006      	b.n	80017ba <HAL_ETH_Transmit+0x126>
-    while ((dmatxdesc->DESC3 & ETH_DMATXNDESCWBF_OWN) != (uint32_t)RESET)
- 80017ac:	697b      	ldr	r3, [r7, #20]
- 80017ae:	68db      	ldr	r3, [r3, #12]
- 80017b0:	2b00      	cmp	r3, #0
- 80017b2:	dbc1      	blt.n	8001738 <HAL_ETH_Transmit+0xa4>
-        }
-      }
-    }
-
-    /* Return function status */
-    return HAL_OK;
- 80017b4:	2300      	movs	r3, #0
- 80017b6:	e000      	b.n	80017ba <HAL_ETH_Transmit+0x126>
-  }
-  else
-  {
-    return HAL_ERROR;
- 80017b8:	2301      	movs	r3, #1
-  }
-}
- 80017ba:	4618      	mov	r0, r3
- 80017bc:	3718      	adds	r7, #24
- 80017be:	46bd      	mov	sp, r7
- 80017c0:	bd80      	pop	{r7, pc}
-
-080017c2 <HAL_ETH_ReadData>:
-  *         the configuration information for ETHERNET module
-  * @param  pAppBuff: Pointer to an application buffer to receive the packet.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_ETH_ReadData(ETH_HandleTypeDef *heth, void **pAppBuff)
-{
- 80017c2:	b580      	push	{r7, lr}
- 80017c4:	b088      	sub	sp, #32
- 80017c6:	af00      	add	r7, sp, #0
- 80017c8:	6078      	str	r0, [r7, #4]
- 80017ca:	6039      	str	r1, [r7, #0]
-  uint32_t descidx;
-  ETH_DMADescTypeDef *dmarxdesc;
-  uint32_t desccnt = 0U;
- 80017cc:	2300      	movs	r3, #0
- 80017ce:	617b      	str	r3, [r7, #20]
-  uint32_t desccntmax;
-  uint32_t bufflength;
-  uint8_t rxdataready = 0U;
- 80017d0:	2300      	movs	r3, #0
- 80017d2:	73fb      	strb	r3, [r7, #15]
-
-
-  if (pAppBuff == NULL)
- 80017d4:	683b      	ldr	r3, [r7, #0]
- 80017d6:	2b00      	cmp	r3, #0
- 80017d8:	d109      	bne.n	80017ee <HAL_ETH_ReadData+0x2c>
-  {
-    heth->ErrorCode |= HAL_ETH_ERROR_PARAM;
- 80017da:	687b      	ldr	r3, [r7, #4]
- 80017dc:	f8d3 3088 	ldr.w	r3, [r3, #136]	; 0x88
- 80017e0:	f043 0201 	orr.w	r2, r3, #1
- 80017e4:	687b      	ldr	r3, [r7, #4]
- 80017e6:	f8c3 2088 	str.w	r2, [r3, #136]	; 0x88
-    return HAL_ERROR;
- 80017ea:	2301      	movs	r3, #1
- 80017ec:	e0a5      	b.n	800193a <HAL_ETH_ReadData+0x178>
-  }
-
-  if (heth->gState != HAL_ETH_STATE_STARTED)
- 80017ee:	687b      	ldr	r3, [r7, #4]
- 80017f0:	f8d3 3084 	ldr.w	r3, [r3, #132]	; 0x84
- 80017f4:	2b23      	cmp	r3, #35	; 0x23
- 80017f6:	d001      	beq.n	80017fc <HAL_ETH_ReadData+0x3a>
-  {
-    return HAL_ERROR;
- 80017f8:	2301      	movs	r3, #1
- 80017fa:	e09e      	b.n	800193a <HAL_ETH_ReadData+0x178>
-  }
-
-  descidx = heth->RxDescList.RxDescIdx;
- 80017fc:	687b      	ldr	r3, [r7, #4]
- 80017fe:	6ddb      	ldr	r3, [r3, #92]	; 0x5c
- 8001800:	61fb      	str	r3, [r7, #28]
-  dmarxdesc = (ETH_DMADescTypeDef *)heth->RxDescList.RxDesc[descidx];
- 8001802:	687b      	ldr	r3, [r7, #4]
- 8001804:	69fa      	ldr	r2, [r7, #28]
- 8001806:	3212      	adds	r2, #18
- 8001808:	f853 3022 	ldr.w	r3, [r3, r2, lsl #2]
- 800180c:	61bb      	str	r3, [r7, #24]
-  desccntmax = ETH_RX_DESC_CNT - heth->RxDescList.RxBuildDescCnt;
- 800180e:	687b      	ldr	r3, [r7, #4]
- 8001810:	6edb      	ldr	r3, [r3, #108]	; 0x6c
- 8001812:	f1c3 0304 	rsb	r3, r3, #4
- 8001816:	60bb      	str	r3, [r7, #8]
-
-  /* Check if descriptor is not owned by DMA */
-  while ((READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_OWN) == (uint32_t)RESET) && (desccnt < desccntmax)
- 8001818:	e067      	b.n	80018ea <HAL_ETH_ReadData+0x128>
-         && (rxdataready == 0U))
-  {
-    if (READ_BIT(dmarxdesc->DESC3,  ETH_DMARXNDESCWBF_CTXT)  != (uint32_t)RESET)
- 800181a:	69bb      	ldr	r3, [r7, #24]
- 800181c:	68db      	ldr	r3, [r3, #12]
- 800181e:	f003 4380 	and.w	r3, r3, #1073741824	; 0x40000000
- 8001822:	2b00      	cmp	r3, #0
- 8001824:	d007      	beq.n	8001836 <HAL_ETH_ReadData+0x74>
-    {
-      /* Get timestamp high */
-      heth->RxDescList.TimeStamp.TimeStampHigh = dmarxdesc->DESC1;
- 8001826:	69bb      	ldr	r3, [r7, #24]
- 8001828:	685a      	ldr	r2, [r3, #4]
- 800182a:	687b      	ldr	r3, [r7, #4]
- 800182c:	679a      	str	r2, [r3, #120]	; 0x78
-      /* Get timestamp low */
-      heth->RxDescList.TimeStamp.TimeStampLow  = dmarxdesc->DESC0;
- 800182e:	69bb      	ldr	r3, [r7, #24]
- 8001830:	681a      	ldr	r2, [r3, #0]
- 8001832:	687b      	ldr	r3, [r7, #4]
- 8001834:	675a      	str	r2, [r3, #116]	; 0x74
-    }
-    if ((READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_FD) != (uint32_t)RESET) || (heth->RxDescList.pRxStart != NULL))
- 8001836:	69bb      	ldr	r3, [r7, #24]
- 8001838:	68db      	ldr	r3, [r3, #12]
- 800183a:	f003 5300 	and.w	r3, r3, #536870912	; 0x20000000
- 800183e:	2b00      	cmp	r3, #0
- 8001840:	d103      	bne.n	800184a <HAL_ETH_ReadData+0x88>
- 8001842:	687b      	ldr	r3, [r7, #4]
- 8001844:	6fdb      	ldr	r3, [r3, #124]	; 0x7c
- 8001846:	2b00      	cmp	r3, #0
- 8001848:	d03d      	beq.n	80018c6 <HAL_ETH_ReadData+0x104>
-    {
-      /* Check if first descriptor */
-      if (READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_FD) != (uint32_t)RESET)
- 800184a:	69bb      	ldr	r3, [r7, #24]
- 800184c:	68db      	ldr	r3, [r3, #12]
- 800184e:	f003 5300 	and.w	r3, r3, #536870912	; 0x20000000
- 8001852:	2b00      	cmp	r3, #0
- 8001854:	d005      	beq.n	8001862 <HAL_ETH_ReadData+0xa0>
-      {
-        heth->RxDescList.RxDescCnt = 0;
- 8001856:	687b      	ldr	r3, [r7, #4]
- 8001858:	2200      	movs	r2, #0
- 800185a:	661a      	str	r2, [r3, #96]	; 0x60
-        heth->RxDescList.RxDataLength = 0;
- 800185c:	687b      	ldr	r3, [r7, #4]
- 800185e:	2200      	movs	r2, #0
- 8001860:	665a      	str	r2, [r3, #100]	; 0x64
-      }
-
-      /* Check if last descriptor */
-      bufflength = heth->Init.RxBuffLen;
- 8001862:	687b      	ldr	r3, [r7, #4]
- 8001864:	695b      	ldr	r3, [r3, #20]
- 8001866:	613b      	str	r3, [r7, #16]
-      if (READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_LD) != (uint32_t)RESET)
- 8001868:	69bb      	ldr	r3, [r7, #24]
- 800186a:	68db      	ldr	r3, [r3, #12]
- 800186c:	f003 5380 	and.w	r3, r3, #268435456	; 0x10000000
- 8001870:	2b00      	cmp	r3, #0
- 8001872:	d00d      	beq.n	8001890 <HAL_ETH_ReadData+0xce>
-      {
-        bufflength = READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_PL) - heth->RxDescList.RxDataLength;
- 8001874:	69bb      	ldr	r3, [r7, #24]
- 8001876:	68db      	ldr	r3, [r3, #12]
- 8001878:	f3c3 020e 	ubfx	r2, r3, #0, #15
- 800187c:	687b      	ldr	r3, [r7, #4]
- 800187e:	6e5b      	ldr	r3, [r3, #100]	; 0x64
- 8001880:	1ad3      	subs	r3, r2, r3
- 8001882:	613b      	str	r3, [r7, #16]
-
-        /* Save Last descriptor index */
-        heth->RxDescList.pRxLastRxDesc = dmarxdesc->DESC3;
- 8001884:	69bb      	ldr	r3, [r7, #24]
- 8001886:	68da      	ldr	r2, [r3, #12]
- 8001888:	687b      	ldr	r3, [r7, #4]
- 800188a:	671a      	str	r2, [r3, #112]	; 0x70
-
-        /* Packet ready */
-        rxdataready = 1;
- 800188c:	2301      	movs	r3, #1
- 800188e:	73fb      	strb	r3, [r7, #15]
-      /*Call registered Link callback*/
-      heth->rxLinkCallback(&heth->RxDescList.pRxStart, &heth->RxDescList.pRxEnd,
-                           (uint8_t *)dmarxdesc->BackupAddr0, bufflength);
-#else
-      /* Link callback */
-      HAL_ETH_RxLinkCallback(&heth->RxDescList.pRxStart, &heth->RxDescList.pRxEnd,
- 8001890:	687b      	ldr	r3, [r7, #4]
- 8001892:	f103 007c 	add.w	r0, r3, #124	; 0x7c
- 8001896:	687b      	ldr	r3, [r7, #4]
- 8001898:	f103 0180 	add.w	r1, r3, #128	; 0x80
-                             (uint8_t *)dmarxdesc->BackupAddr0, (uint16_t) bufflength);
- 800189c:	69bb      	ldr	r3, [r7, #24]
- 800189e:	691b      	ldr	r3, [r3, #16]
-      HAL_ETH_RxLinkCallback(&heth->RxDescList.pRxStart, &heth->RxDescList.pRxEnd,
- 80018a0:	461a      	mov	r2, r3
- 80018a2:	693b      	ldr	r3, [r7, #16]
- 80018a4:	b29b      	uxth	r3, r3
- 80018a6:	f003 fdc9 	bl	800543c <HAL_ETH_RxLinkCallback>
-#endif  /* USE_HAL_ETH_REGISTER_CALLBACKS */
-      heth->RxDescList.RxDescCnt++;
- 80018aa:	687b      	ldr	r3, [r7, #4]
- 80018ac:	6e1b      	ldr	r3, [r3, #96]	; 0x60
- 80018ae:	1c5a      	adds	r2, r3, #1
- 80018b0:	687b      	ldr	r3, [r7, #4]
- 80018b2:	661a      	str	r2, [r3, #96]	; 0x60
-      heth->RxDescList.RxDataLength += bufflength;
- 80018b4:	687b      	ldr	r3, [r7, #4]
- 80018b6:	6e5a      	ldr	r2, [r3, #100]	; 0x64
- 80018b8:	693b      	ldr	r3, [r7, #16]
- 80018ba:	441a      	add	r2, r3
- 80018bc:	687b      	ldr	r3, [r7, #4]
- 80018be:	665a      	str	r2, [r3, #100]	; 0x64
-
-      /* Clear buffer pointer */
-      dmarxdesc->BackupAddr0 = 0;
- 80018c0:	69bb      	ldr	r3, [r7, #24]
- 80018c2:	2200      	movs	r2, #0
- 80018c4:	611a      	str	r2, [r3, #16]
-    }
-
-    /* Increment current rx descriptor index */
-    INCR_RX_DESC_INDEX(descidx, 1U);
- 80018c6:	69fb      	ldr	r3, [r7, #28]
- 80018c8:	3301      	adds	r3, #1
- 80018ca:	61fb      	str	r3, [r7, #28]
- 80018cc:	69fb      	ldr	r3, [r7, #28]
- 80018ce:	2b03      	cmp	r3, #3
- 80018d0:	d902      	bls.n	80018d8 <HAL_ETH_ReadData+0x116>
- 80018d2:	69fb      	ldr	r3, [r7, #28]
- 80018d4:	3b04      	subs	r3, #4
- 80018d6:	61fb      	str	r3, [r7, #28]
-    /* Get current descriptor address */
-    dmarxdesc = (ETH_DMADescTypeDef *)heth->RxDescList.RxDesc[descidx];
- 80018d8:	687b      	ldr	r3, [r7, #4]
- 80018da:	69fa      	ldr	r2, [r7, #28]
- 80018dc:	3212      	adds	r2, #18
- 80018de:	f853 3022 	ldr.w	r3, [r3, r2, lsl #2]
- 80018e2:	61bb      	str	r3, [r7, #24]
-    desccnt++;
- 80018e4:	697b      	ldr	r3, [r7, #20]
- 80018e6:	3301      	adds	r3, #1
- 80018e8:	617b      	str	r3, [r7, #20]
-  while ((READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_OWN) == (uint32_t)RESET) && (desccnt < desccntmax)
- 80018ea:	69bb      	ldr	r3, [r7, #24]
- 80018ec:	68db      	ldr	r3, [r3, #12]
-         && (rxdataready == 0U))
- 80018ee:	2b00      	cmp	r3, #0
- 80018f0:	db06      	blt.n	8001900 <HAL_ETH_ReadData+0x13e>
-  while ((READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_OWN) == (uint32_t)RESET) && (desccnt < desccntmax)
- 80018f2:	697a      	ldr	r2, [r7, #20]
- 80018f4:	68bb      	ldr	r3, [r7, #8]
- 80018f6:	429a      	cmp	r2, r3
- 80018f8:	d202      	bcs.n	8001900 <HAL_ETH_ReadData+0x13e>
-         && (rxdataready == 0U))
- 80018fa:	7bfb      	ldrb	r3, [r7, #15]
- 80018fc:	2b00      	cmp	r3, #0
- 80018fe:	d08c      	beq.n	800181a <HAL_ETH_ReadData+0x58>
-  }
-
-  heth->RxDescList.RxBuildDescCnt += desccnt;
- 8001900:	687b      	ldr	r3, [r7, #4]
- 8001902:	6eda      	ldr	r2, [r3, #108]	; 0x6c
- 8001904:	697b      	ldr	r3, [r7, #20]
- 8001906:	441a      	add	r2, r3
- 8001908:	687b      	ldr	r3, [r7, #4]
- 800190a:	66da      	str	r2, [r3, #108]	; 0x6c
-  if ((heth->RxDescList.RxBuildDescCnt) != 0U)
- 800190c:	687b      	ldr	r3, [r7, #4]
- 800190e:	6edb      	ldr	r3, [r3, #108]	; 0x6c
- 8001910:	2b00      	cmp	r3, #0
- 8001912:	d002      	beq.n	800191a <HAL_ETH_ReadData+0x158>
-  {
-    /* Update Descriptors */
-    ETH_UpdateDescriptor(heth);
- 8001914:	6878      	ldr	r0, [r7, #4]
- 8001916:	f000 f814 	bl	8001942 <ETH_UpdateDescriptor>
-  }
-
-  heth->RxDescList.RxDescIdx = descidx;
- 800191a:	687b      	ldr	r3, [r7, #4]
- 800191c:	69fa      	ldr	r2, [r7, #28]
- 800191e:	65da      	str	r2, [r3, #92]	; 0x5c
-
-  if (rxdataready == 1U)
- 8001920:	7bfb      	ldrb	r3, [r7, #15]
- 8001922:	2b01      	cmp	r3, #1
- 8001924:	d108      	bne.n	8001938 <HAL_ETH_ReadData+0x176>
-  {
-    /* Return received packet */
-    *pAppBuff = heth->RxDescList.pRxStart;
- 8001926:	687b      	ldr	r3, [r7, #4]
- 8001928:	6fda      	ldr	r2, [r3, #124]	; 0x7c
- 800192a:	683b      	ldr	r3, [r7, #0]
- 800192c:	601a      	str	r2, [r3, #0]
-    /* Reset first element */
-    heth->RxDescList.pRxStart = NULL;
- 800192e:	687b      	ldr	r3, [r7, #4]
- 8001930:	2200      	movs	r2, #0
- 8001932:	67da      	str	r2, [r3, #124]	; 0x7c
-
-    return HAL_OK;
- 8001934:	2300      	movs	r3, #0
- 8001936:	e000      	b.n	800193a <HAL_ETH_ReadData+0x178>
-  }
-
-  /* Packet not ready */
-  return HAL_ERROR;
- 8001938:	2301      	movs	r3, #1
-}
- 800193a:	4618      	mov	r0, r3
- 800193c:	3720      	adds	r7, #32
- 800193e:	46bd      	mov	sp, r7
- 8001940:	bd80      	pop	{r7, pc}
-
-08001942 <ETH_UpdateDescriptor>:
-  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
-  *         the configuration information for ETHERNET module
-  * @retval HAL status
-  */
-static void ETH_UpdateDescriptor(ETH_HandleTypeDef *heth)
-{
- 8001942:	b580      	push	{r7, lr}
- 8001944:	b088      	sub	sp, #32
- 8001946:	af00      	add	r7, sp, #0
- 8001948:	6078      	str	r0, [r7, #4]
-  uint32_t descidx;
-  uint32_t desccount;
-  ETH_DMADescTypeDef *dmarxdesc;
-  uint8_t *buff = NULL;
- 800194a:	2300      	movs	r3, #0
- 800194c:	60fb      	str	r3, [r7, #12]
-  uint8_t allocStatus = 1U;
- 800194e:	2301      	movs	r3, #1
- 8001950:	74fb      	strb	r3, [r7, #19]
-
-  descidx = heth->RxDescList.RxBuildDescIdx;
- 8001952:	687b      	ldr	r3, [r7, #4]
- 8001954:	6e9b      	ldr	r3, [r3, #104]	; 0x68
- 8001956:	61fb      	str	r3, [r7, #28]
-  dmarxdesc = (ETH_DMADescTypeDef *)heth->RxDescList.RxDesc[descidx];
- 8001958:	687b      	ldr	r3, [r7, #4]
- 800195a:	69fa      	ldr	r2, [r7, #28]
- 800195c:	3212      	adds	r2, #18
- 800195e:	f853 3022 	ldr.w	r3, [r3, r2, lsl #2]
- 8001962:	617b      	str	r3, [r7, #20]
-  desccount = heth->RxDescList.RxBuildDescCnt;
- 8001964:	687b      	ldr	r3, [r7, #4]
- 8001966:	6edb      	ldr	r3, [r3, #108]	; 0x6c
- 8001968:	61bb      	str	r3, [r7, #24]
-
-  while ((desccount > 0U) && (allocStatus != 0U))
- 800196a:	e03b      	b.n	80019e4 <ETH_UpdateDescriptor+0xa2>
-  {
-    /* Check if a buffer's attached the descriptor */
-    if (READ_REG(dmarxdesc->BackupAddr0) == 0U)
- 800196c:	697b      	ldr	r3, [r7, #20]
- 800196e:	691b      	ldr	r3, [r3, #16]
- 8001970:	2b00      	cmp	r3, #0
- 8001972:	d112      	bne.n	800199a <ETH_UpdateDescriptor+0x58>
-#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
-      /*Call registered Allocate callback*/
-      heth->rxAllocateCallback(&buff);
-#else
-      /* Allocate callback */
-      HAL_ETH_RxAllocateCallback(&buff);
- 8001974:	f107 030c 	add.w	r3, r7, #12
- 8001978:	4618      	mov	r0, r3
- 800197a:	f003 fd2f 	bl	80053dc <HAL_ETH_RxAllocateCallback>
-#endif  /* USE_HAL_ETH_REGISTER_CALLBACKS */
-      if (buff == NULL)
- 800197e:	68fb      	ldr	r3, [r7, #12]
- 8001980:	2b00      	cmp	r3, #0
- 8001982:	d102      	bne.n	800198a <ETH_UpdateDescriptor+0x48>
-      {
-        allocStatus = 0U;
- 8001984:	2300      	movs	r3, #0
- 8001986:	74fb      	strb	r3, [r7, #19]
- 8001988:	e007      	b.n	800199a <ETH_UpdateDescriptor+0x58>
-      }
-      else
-      {
-        WRITE_REG(dmarxdesc->BackupAddr0, (uint32_t)buff);
- 800198a:	68fb      	ldr	r3, [r7, #12]
- 800198c:	461a      	mov	r2, r3
- 800198e:	697b      	ldr	r3, [r7, #20]
- 8001990:	611a      	str	r2, [r3, #16]
-        WRITE_REG(dmarxdesc->DESC0, (uint32_t)buff);
- 8001992:	68fb      	ldr	r3, [r7, #12]
- 8001994:	461a      	mov	r2, r3
- 8001996:	697b      	ldr	r3, [r7, #20]
- 8001998:	601a      	str	r2, [r3, #0]
-      }
-    }
-
-    if (allocStatus != 0U)
- 800199a:	7cfb      	ldrb	r3, [r7, #19]
- 800199c:	2b00      	cmp	r3, #0
- 800199e:	d021      	beq.n	80019e4 <ETH_UpdateDescriptor+0xa2>
-  __ASM volatile ("dmb 0xF":::"memory");
- 80019a0:	f3bf 8f5f 	dmb	sy
-}
- 80019a4:	bf00      	nop
-    {
-      /* Ensure rest of descriptor is written to RAM before the OWN bit */
-      __DMB();
-
-      if (heth->RxDescList.ItMode != 0U)
- 80019a6:	687b      	ldr	r3, [r7, #4]
- 80019a8:	6d9b      	ldr	r3, [r3, #88]	; 0x58
- 80019aa:	2b00      	cmp	r3, #0
- 80019ac:	d004      	beq.n	80019b8 <ETH_UpdateDescriptor+0x76>
-      {
-        WRITE_REG(dmarxdesc->DESC3, ETH_DMARXNDESCRF_OWN | ETH_DMARXNDESCRF_BUF1V | ETH_DMARXNDESCRF_IOC);
- 80019ae:	697b      	ldr	r3, [r7, #20]
- 80019b0:	f04f 4241 	mov.w	r2, #3238002688	; 0xc1000000
- 80019b4:	60da      	str	r2, [r3, #12]
- 80019b6:	e003      	b.n	80019c0 <ETH_UpdateDescriptor+0x7e>
-      }
-      else
-      {
-        WRITE_REG(dmarxdesc->DESC3, ETH_DMARXNDESCRF_OWN | ETH_DMARXNDESCRF_BUF1V);
- 80019b8:	697b      	ldr	r3, [r7, #20]
- 80019ba:	f04f 4201 	mov.w	r2, #2164260864	; 0x81000000
- 80019be:	60da      	str	r2, [r3, #12]
-      }
-
-      /* Increment current rx descriptor index */
-      INCR_RX_DESC_INDEX(descidx, 1U);
- 80019c0:	69fb      	ldr	r3, [r7, #28]
- 80019c2:	3301      	adds	r3, #1
- 80019c4:	61fb      	str	r3, [r7, #28]
- 80019c6:	69fb      	ldr	r3, [r7, #28]
- 80019c8:	2b03      	cmp	r3, #3
- 80019ca:	d902      	bls.n	80019d2 <ETH_UpdateDescriptor+0x90>
- 80019cc:	69fb      	ldr	r3, [r7, #28]
- 80019ce:	3b04      	subs	r3, #4
- 80019d0:	61fb      	str	r3, [r7, #28]
-      /* Get current descriptor address */
-      dmarxdesc = (ETH_DMADescTypeDef *)heth->RxDescList.RxDesc[descidx];
- 80019d2:	687b      	ldr	r3, [r7, #4]
- 80019d4:	69fa      	ldr	r2, [r7, #28]
- 80019d6:	3212      	adds	r2, #18
- 80019d8:	f853 3022 	ldr.w	r3, [r3, r2, lsl #2]
- 80019dc:	617b      	str	r3, [r7, #20]
-      desccount--;
- 80019de:	69bb      	ldr	r3, [r7, #24]
- 80019e0:	3b01      	subs	r3, #1
- 80019e2:	61bb      	str	r3, [r7, #24]
-  while ((desccount > 0U) && (allocStatus != 0U))
- 80019e4:	69bb      	ldr	r3, [r7, #24]
- 80019e6:	2b00      	cmp	r3, #0
- 80019e8:	d002      	beq.n	80019f0 <ETH_UpdateDescriptor+0xae>
- 80019ea:	7cfb      	ldrb	r3, [r7, #19]
- 80019ec:	2b00      	cmp	r3, #0
- 80019ee:	d1bd      	bne.n	800196c <ETH_UpdateDescriptor+0x2a>
-    }
-  }
-
-  if (heth->RxDescList.RxBuildDescCnt != desccount)
- 80019f0:	687b      	ldr	r3, [r7, #4]
- 80019f2:	6edb      	ldr	r3, [r3, #108]	; 0x6c
- 80019f4:	69ba      	ldr	r2, [r7, #24]
- 80019f6:	429a      	cmp	r2, r3
- 80019f8:	d00d      	beq.n	8001a16 <ETH_UpdateDescriptor+0xd4>
-  {
-    /* Set the Tail pointer address */
-    WRITE_REG(heth->Instance->DMACRDTPR, 0);
- 80019fa:	687b      	ldr	r3, [r7, #4]
- 80019fc:	681b      	ldr	r3, [r3, #0]
- 80019fe:	f503 5380 	add.w	r3, r3, #4096	; 0x1000
- 8001a02:	461a      	mov	r2, r3
- 8001a04:	2300      	movs	r3, #0
- 8001a06:	f8c2 3128 	str.w	r3, [r2, #296]	; 0x128
-
-    heth->RxDescList.RxBuildDescIdx = descidx;
- 8001a0a:	687b      	ldr	r3, [r7, #4]
- 8001a0c:	69fa      	ldr	r2, [r7, #28]
- 8001a0e:	669a      	str	r2, [r3, #104]	; 0x68
-    heth->RxDescList.RxBuildDescCnt = desccount;
- 8001a10:	687b      	ldr	r3, [r7, #4]
- 8001a12:	69ba      	ldr	r2, [r7, #24]
- 8001a14:	66da      	str	r2, [r3, #108]	; 0x6c
-  }
-}
- 8001a16:	bf00      	nop
- 8001a18:	3720      	adds	r7, #32
- 8001a1a:	46bd      	mov	sp, r7
- 8001a1c:	bd80      	pop	{r7, pc}
-	...
-
-08001a20 <HAL_ETH_IRQHandler>:
-  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
-  *         the configuration information for ETHERNET module
-  * @retval HAL status
-  */
-void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth)
-{
- 8001a20:	b580      	push	{r7, lr}
- 8001a22:	b084      	sub	sp, #16
- 8001a24:	af00      	add	r7, sp, #0
- 8001a26:	6078      	str	r0, [r7, #4]
-  uint32_t macirqenable;
-  /* Packet received */
-  if (__HAL_ETH_DMA_GET_IT(heth, ETH_DMACSR_RI))
- 8001a28:	687b      	ldr	r3, [r7, #4]
- 8001a2a:	681b      	ldr	r3, [r3, #0]
- 8001a2c:	f503 5380 	add.w	r3, r3, #4096	; 0x1000
- 8001a30:	f8d3 3160 	ldr.w	r3, [r3, #352]	; 0x160
- 8001a34:	f003 0340 	and.w	r3, r3, #64	; 0x40
- 8001a38:	2b40      	cmp	r3, #64	; 0x40
- 8001a3a:	d115      	bne.n	8001a68 <HAL_ETH_IRQHandler+0x48>
-  {
-    if (__HAL_ETH_DMA_GET_IT_SOURCE(heth, ETH_DMACIER_RIE))
- 8001a3c:	687b      	ldr	r3, [r7, #4]
- 8001a3e:	681b      	ldr	r3, [r3, #0]
- 8001a40:	f503 5380 	add.w	r3, r3, #4096	; 0x1000
- 8001a44:	f8d3 3134 	ldr.w	r3, [r3, #308]	; 0x134
- 8001a48:	f003 0340 	and.w	r3, r3, #64	; 0x40
- 8001a4c:	2b40      	cmp	r3, #64	; 0x40
- 8001a4e:	d10b      	bne.n	8001a68 <HAL_ETH_IRQHandler+0x48>
-    {
-      /* Clear the Eth DMA Rx IT pending bits */
-      __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMACSR_RI | ETH_DMACSR_NIS);
- 8001a50:	687b      	ldr	r3, [r7, #4]
- 8001a52:	681b      	ldr	r3, [r3, #0]
- 8001a54:	f503 5380 	add.w	r3, r3, #4096	; 0x1000
- 8001a58:	461a      	mov	r2, r3
- 8001a5a:	f248 0340 	movw	r3, #32832	; 0x8040
- 8001a5e:	f8c2 3160 	str.w	r3, [r2, #352]	; 0x160
-#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
-      /*Call registered Receive complete callback*/
-      heth->RxCpltCallback(heth);
-#else
-      /* Receive complete callback */
-      HAL_ETH_RxCpltCallback(heth);
- 8001a62:	6878      	ldr	r0, [r7, #4]
- 8001a64:	f000 f8f6 	bl	8001c54 <HAL_ETH_RxCpltCallback>
-#endif  /* USE_HAL_ETH_REGISTER_CALLBACKS */
-    }
-  }
-
-  /* Packet transmitted */
-  if (__HAL_ETH_DMA_GET_IT(heth, ETH_DMACSR_TI))
- 8001a68:	687b      	ldr	r3, [r7, #4]
- 8001a6a:	681b      	ldr	r3, [r3, #0]
- 8001a6c:	f503 5380 	add.w	r3, r3, #4096	; 0x1000
- 8001a70:	f8d3 3160 	ldr.w	r3, [r3, #352]	; 0x160
- 8001a74:	f003 0301 	and.w	r3, r3, #1
- 8001a78:	2b01      	cmp	r3, #1
- 8001a7a:	d115      	bne.n	8001aa8 <HAL_ETH_IRQHandler+0x88>
-  {
-    if (__HAL_ETH_DMA_GET_IT_SOURCE(heth, ETH_DMACIER_TIE))
- 8001a7c:	687b      	ldr	r3, [r7, #4]
- 8001a7e:	681b      	ldr	r3, [r3, #0]
- 8001a80:	f503 5380 	add.w	r3, r3, #4096	; 0x1000
- 8001a84:	f8d3 3134 	ldr.w	r3, [r3, #308]	; 0x134
- 8001a88:	f003 0301 	and.w	r3, r3, #1
- 8001a8c:	2b01      	cmp	r3, #1
- 8001a8e:	d10b      	bne.n	8001aa8 <HAL_ETH_IRQHandler+0x88>
-    {
-      /* Clear the Eth DMA Tx IT pending bits */
-      __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMACSR_TI | ETH_DMACSR_NIS);
- 8001a90:	687b      	ldr	r3, [r7, #4]
- 8001a92:	681b      	ldr	r3, [r3, #0]
- 8001a94:	f503 5380 	add.w	r3, r3, #4096	; 0x1000
- 8001a98:	461a      	mov	r2, r3
- 8001a9a:	f248 0301 	movw	r3, #32769	; 0x8001
- 8001a9e:	f8c2 3160 	str.w	r3, [r2, #352]	; 0x160
-#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
-      /*Call registered Transmit complete callback*/
-      heth->TxCpltCallback(heth);
-#else
-      /* Transfer complete callback */
-      HAL_ETH_TxCpltCallback(heth);
- 8001aa2:	6878      	ldr	r0, [r7, #4]
- 8001aa4:	f000 f8cc 	bl	8001c40 <HAL_ETH_TxCpltCallback>
-    }
-  }
-
-
-  /* ETH DMA Error */
-  if (__HAL_ETH_DMA_GET_IT(heth, ETH_DMACSR_AIS))
- 8001aa8:	687b      	ldr	r3, [r7, #4]
- 8001aaa:	681b      	ldr	r3, [r3, #0]
- 8001aac:	f503 5380 	add.w	r3, r3, #4096	; 0x1000
- 8001ab0:	f8d3 3160 	ldr.w	r3, [r3, #352]	; 0x160
- 8001ab4:	f403 4380 	and.w	r3, r3, #16384	; 0x4000
- 8001ab8:	f5b3 4f80 	cmp.w	r3, #16384	; 0x4000
- 8001abc:	d153      	bne.n	8001b66 <HAL_ETH_IRQHandler+0x146>
-  {
-    if (__HAL_ETH_DMA_GET_IT_SOURCE(heth, ETH_DMACIER_AIE))
- 8001abe:	687b      	ldr	r3, [r7, #4]
- 8001ac0:	681b      	ldr	r3, [r3, #0]
- 8001ac2:	f503 5380 	add.w	r3, r3, #4096	; 0x1000
- 8001ac6:	f8d3 3134 	ldr.w	r3, [r3, #308]	; 0x134
- 8001aca:	f403 4380 	and.w	r3, r3, #16384	; 0x4000
- 8001ace:	f5b3 4f80 	cmp.w	r3, #16384	; 0x4000
- 8001ad2:	d148      	bne.n	8001b66 <HAL_ETH_IRQHandler+0x146>
-    {
-      heth->ErrorCode |= HAL_ETH_ERROR_DMA;
- 8001ad4:	687b      	ldr	r3, [r7, #4]
- 8001ad6:	f8d3 3088 	ldr.w	r3, [r3, #136]	; 0x88
- 8001ada:	f043 0208 	orr.w	r2, r3, #8
- 8001ade:	687b      	ldr	r3, [r7, #4]
- 8001ae0:	f8c3 2088 	str.w	r2, [r3, #136]	; 0x88
-
-      /* if fatal bus error occurred */
-      if (__HAL_ETH_DMA_GET_IT(heth, ETH_DMACSR_FBE))
- 8001ae4:	687b      	ldr	r3, [r7, #4]
- 8001ae6:	681b      	ldr	r3, [r3, #0]
- 8001ae8:	f503 5380 	add.w	r3, r3, #4096	; 0x1000
- 8001aec:	f8d3 3160 	ldr.w	r3, [r3, #352]	; 0x160
- 8001af0:	f403 5380 	and.w	r3, r3, #4096	; 0x1000
- 8001af4:	f5b3 5f80 	cmp.w	r3, #4096	; 0x1000
- 8001af8:	d11e      	bne.n	8001b38 <HAL_ETH_IRQHandler+0x118>
-      {
-        /* Get DMA error code  */
-        heth->DMAErrorCode = READ_BIT(heth->Instance->DMACSR, (ETH_DMACSR_FBE | ETH_DMACSR_TPS | ETH_DMACSR_RPS));
- 8001afa:	687b      	ldr	r3, [r7, #4]
- 8001afc:	681b      	ldr	r3, [r3, #0]
- 8001afe:	f503 5380 	add.w	r3, r3, #4096	; 0x1000
- 8001b02:	f8d3 2160 	ldr.w	r2, [r3, #352]	; 0x160
- 8001b06:	f241 1302 	movw	r3, #4354	; 0x1102
- 8001b0a:	4013      	ands	r3, r2
- 8001b0c:	687a      	ldr	r2, [r7, #4]
- 8001b0e:	f8c2 308c 	str.w	r3, [r2, #140]	; 0x8c
-
-        /* Disable all interrupts */
-        __HAL_ETH_DMA_DISABLE_IT(heth, ETH_DMACIER_NIE | ETH_DMACIER_AIE);
- 8001b12:	687b      	ldr	r3, [r7, #4]
- 8001b14:	681b      	ldr	r3, [r3, #0]
- 8001b16:	f503 5380 	add.w	r3, r3, #4096	; 0x1000
- 8001b1a:	f8d3 3134 	ldr.w	r3, [r3, #308]	; 0x134
- 8001b1e:	687a      	ldr	r2, [r7, #4]
- 8001b20:	6812      	ldr	r2, [r2, #0]
- 8001b22:	f423 4340 	bic.w	r3, r3, #49152	; 0xc000
- 8001b26:	f502 5280 	add.w	r2, r2, #4096	; 0x1000
- 8001b2a:	f8c2 3134 	str.w	r3, [r2, #308]	; 0x134
-
-        /* Set HAL state to ERROR */
-        heth->gState = HAL_ETH_STATE_ERROR;
- 8001b2e:	687b      	ldr	r3, [r7, #4]
- 8001b30:	22e0      	movs	r2, #224	; 0xe0
- 8001b32:	f8c3 2084 	str.w	r2, [r3, #132]	; 0x84
- 8001b36:	e013      	b.n	8001b60 <HAL_ETH_IRQHandler+0x140>
-      }
-      else
-      {
-        /* Get DMA error status  */
-        heth->DMAErrorCode = READ_BIT(heth->Instance->DMACSR, (ETH_DMACSR_CDE | ETH_DMACSR_ETI | ETH_DMACSR_RWT |
- 8001b38:	687b      	ldr	r3, [r7, #4]
- 8001b3a:	681b      	ldr	r3, [r3, #0]
- 8001b3c:	f503 5380 	add.w	r3, r3, #4096	; 0x1000
- 8001b40:	f8d3 3160 	ldr.w	r3, [r3, #352]	; 0x160
- 8001b44:	f403 42cd 	and.w	r2, r3, #26240	; 0x6680
- 8001b48:	687b      	ldr	r3, [r7, #4]
- 8001b4a:	f8c3 208c 	str.w	r2, [r3, #140]	; 0x8c
-                                                               ETH_DMACSR_RBU | ETH_DMACSR_AIS));
-
-        /* Clear the interrupt summary flag */
-        __HAL_ETH_DMA_CLEAR_IT(heth, (ETH_DMACSR_CDE | ETH_DMACSR_ETI | ETH_DMACSR_RWT |
- 8001b4e:	687b      	ldr	r3, [r7, #4]
- 8001b50:	681b      	ldr	r3, [r3, #0]
- 8001b52:	f503 5380 	add.w	r3, r3, #4096	; 0x1000
- 8001b56:	461a      	mov	r2, r3
- 8001b58:	f44f 43cd 	mov.w	r3, #26240	; 0x6680
- 8001b5c:	f8c2 3160 	str.w	r3, [r2, #352]	; 0x160
-#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
-      /* Call registered Error callback*/
-      heth->ErrorCallback(heth);
-#else
-      /* Ethernet DMA Error callback */
-      HAL_ETH_ErrorCallback(heth);
- 8001b60:	6878      	ldr	r0, [r7, #4]
- 8001b62:	f000 f881 	bl	8001c68 <HAL_ETH_ErrorCallback>
-
-    }
-  }
-
-  /* ETH MAC Error IT */
-  macirqenable = heth->Instance->MACIER;
- 8001b66:	687b      	ldr	r3, [r7, #4]
- 8001b68:	681b      	ldr	r3, [r3, #0]
- 8001b6a:	f8d3 30b4 	ldr.w	r3, [r3, #180]	; 0xb4
- 8001b6e:	60fb      	str	r3, [r7, #12]
-  if (((macirqenable & ETH_MACIER_RXSTSIE) == ETH_MACIER_RXSTSIE) || \
- 8001b70:	68fb      	ldr	r3, [r7, #12]
- 8001b72:	f403 4380 	and.w	r3, r3, #16384	; 0x4000
- 8001b76:	2b00      	cmp	r3, #0
- 8001b78:	d104      	bne.n	8001b84 <HAL_ETH_IRQHandler+0x164>
-      ((macirqenable & ETH_MACIER_TXSTSIE) == ETH_MACIER_TXSTSIE))
- 8001b7a:	68fb      	ldr	r3, [r7, #12]
- 8001b7c:	f403 5300 	and.w	r3, r3, #8192	; 0x2000
-  if (((macirqenable & ETH_MACIER_RXSTSIE) == ETH_MACIER_RXSTSIE) || \
- 8001b80:	2b00      	cmp	r3, #0
- 8001b82:	d019      	beq.n	8001bb8 <HAL_ETH_IRQHandler+0x198>
-  {
-    heth->ErrorCode |= HAL_ETH_ERROR_MAC;
- 8001b84:	687b      	ldr	r3, [r7, #4]
- 8001b86:	f8d3 3088 	ldr.w	r3, [r3, #136]	; 0x88
- 8001b8a:	f043 0210 	orr.w	r2, r3, #16
- 8001b8e:	687b      	ldr	r3, [r7, #4]
- 8001b90:	f8c3 2088 	str.w	r2, [r3, #136]	; 0x88
-
-    /* Get MAC Rx Tx status and clear Status register pending bit */
-    heth->MACErrorCode = READ_REG(heth->Instance->MACRXTXSR);
- 8001b94:	687b      	ldr	r3, [r7, #4]
- 8001b96:	681b      	ldr	r3, [r3, #0]
- 8001b98:	f8d3 20b8 	ldr.w	r2, [r3, #184]	; 0xb8
- 8001b9c:	687b      	ldr	r3, [r7, #4]
- 8001b9e:	f8c3 2090 	str.w	r2, [r3, #144]	; 0x90
-
-    heth->gState = HAL_ETH_STATE_ERROR;
- 8001ba2:	687b      	ldr	r3, [r7, #4]
- 8001ba4:	22e0      	movs	r2, #224	; 0xe0
- 8001ba6:	f8c3 2084 	str.w	r2, [r3, #132]	; 0x84
-#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
-    /* Call registered Error callback*/
-    heth->ErrorCallback(heth);
-#else
-    /* Ethernet Error callback */
-    HAL_ETH_ErrorCallback(heth);
- 8001baa:	6878      	ldr	r0, [r7, #4]
- 8001bac:	f000 f85c 	bl	8001c68 <HAL_ETH_ErrorCallback>
-#endif  /* USE_HAL_ETH_REGISTER_CALLBACKS */
-
-    heth->MACErrorCode = (uint32_t)(0x0U);
- 8001bb0:	687b      	ldr	r3, [r7, #4]
- 8001bb2:	2200      	movs	r2, #0
- 8001bb4:	f8c3 2090 	str.w	r2, [r3, #144]	; 0x90
-  }
-
-  /* ETH PMT IT */
-  if (__HAL_ETH_MAC_GET_IT(heth, ETH_MAC_PMT_IT))
- 8001bb8:	687b      	ldr	r3, [r7, #4]
- 8001bba:	681b      	ldr	r3, [r3, #0]
- 8001bbc:	f8d3 30b0 	ldr.w	r3, [r3, #176]	; 0xb0
- 8001bc0:	f003 0310 	and.w	r3, r3, #16
- 8001bc4:	2b10      	cmp	r3, #16
- 8001bc6:	d10f      	bne.n	8001be8 <HAL_ETH_IRQHandler+0x1c8>
-  {
-    /* Get MAC Wake-up source and clear the status register pending bit */
-    heth->MACWakeUpEvent = READ_BIT(heth->Instance->MACPCSR, (ETH_MACPCSR_RWKPRCVD | ETH_MACPCSR_MGKPRCVD));
- 8001bc8:	687b      	ldr	r3, [r7, #4]
- 8001bca:	681b      	ldr	r3, [r3, #0]
- 8001bcc:	f8d3 30c0 	ldr.w	r3, [r3, #192]	; 0xc0
- 8001bd0:	f003 0260 	and.w	r2, r3, #96	; 0x60
- 8001bd4:	687b      	ldr	r3, [r7, #4]
- 8001bd6:	f8c3 2094 	str.w	r2, [r3, #148]	; 0x94
-#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
-    /* Call registered PMT callback*/
-    heth->PMTCallback(heth);
-#else
-    /* Ethernet PMT callback */
-    HAL_ETH_PMTCallback(heth);
- 8001bda:	6878      	ldr	r0, [r7, #4]
- 8001bdc:	f000 f84e 	bl	8001c7c <HAL_ETH_PMTCallback>
-#endif  /* USE_HAL_ETH_REGISTER_CALLBACKS */
-
-    heth->MACWakeUpEvent = (uint32_t)(0x0U);
- 8001be0:	687b      	ldr	r3, [r7, #4]
- 8001be2:	2200      	movs	r2, #0
- 8001be4:	f8c3 2094 	str.w	r2, [r3, #148]	; 0x94
-  }
-
-  /* ETH EEE IT */
-  if (__HAL_ETH_MAC_GET_IT(heth, ETH_MAC_LPI_IT))
- 8001be8:	687b      	ldr	r3, [r7, #4]
- 8001bea:	681b      	ldr	r3, [r3, #0]
- 8001bec:	f8d3 30b0 	ldr.w	r3, [r3, #176]	; 0xb0
- 8001bf0:	f003 0320 	and.w	r3, r3, #32
- 8001bf4:	2b20      	cmp	r3, #32
- 8001bf6:	d10f      	bne.n	8001c18 <HAL_ETH_IRQHandler+0x1f8>
-  {
-    /* Get MAC LPI interrupt source and clear the status register pending bit */
-    heth->MACLPIEvent = READ_BIT(heth->Instance->MACPCSR, 0x0000000FU);
- 8001bf8:	687b      	ldr	r3, [r7, #4]
- 8001bfa:	681b      	ldr	r3, [r3, #0]
- 8001bfc:	f8d3 30c0 	ldr.w	r3, [r3, #192]	; 0xc0
- 8001c00:	f003 020f 	and.w	r2, r3, #15
- 8001c04:	687b      	ldr	r3, [r7, #4]
- 8001c06:	f8c3 2098 	str.w	r2, [r3, #152]	; 0x98
-#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
-    /* Call registered EEE callback*/
-    heth->EEECallback(heth);
-#else
-    /* Ethernet EEE callback */
-    HAL_ETH_EEECallback(heth);
- 8001c0a:	6878      	ldr	r0, [r7, #4]
- 8001c0c:	f000 f840 	bl	8001c90 <HAL_ETH_EEECallback>
-#endif  /* USE_HAL_ETH_REGISTER_CALLBACKS */
-
-    heth->MACLPIEvent = (uint32_t)(0x0U);
- 8001c10:	687b      	ldr	r3, [r7, #4]
- 8001c12:	2200      	movs	r2, #0
- 8001c14:	f8c3 2098 	str.w	r2, [r3, #152]	; 0x98
-#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
-    }
-  }
-#else /* USE_HAL_ETH_REGISTER_CALLBACKS */
-  /* check ETH WAKEUP exti flag */
-  if (__HAL_ETH_WAKEUP_EXTI_GET_FLAG(ETH_WAKEUP_EXTI_LINE) != (uint32_t)RESET)
- 8001c18:	4b08      	ldr	r3, [pc, #32]	; (8001c3c <HAL_ETH_IRQHandler+0x21c>)
- 8001c1a:	6a9b      	ldr	r3, [r3, #40]	; 0x28
- 8001c1c:	f403 0380 	and.w	r3, r3, #4194304	; 0x400000
- 8001c20:	2b00      	cmp	r3, #0
- 8001c22:	d006      	beq.n	8001c32 <HAL_ETH_IRQHandler+0x212>
-  {
-    /* Clear ETH WAKEUP Exti pending bit */
-    __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG(ETH_WAKEUP_EXTI_LINE);
- 8001c24:	4b05      	ldr	r3, [pc, #20]	; (8001c3c <HAL_ETH_IRQHandler+0x21c>)
- 8001c26:	f44f 0280 	mov.w	r2, #4194304	; 0x400000
- 8001c2a:	629a      	str	r2, [r3, #40]	; 0x28
-#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
-    /* Call registered WakeUp callback*/
-    heth->WakeUpCallback(heth);
-#else
-    /* ETH WAKEUP callback */
-    HAL_ETH_WakeUpCallback(heth);
- 8001c2c:	6878      	ldr	r0, [r7, #4]
- 8001c2e:	f000 f839 	bl	8001ca4 <HAL_ETH_WakeUpCallback>
-#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
-  }
-#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
-}
- 8001c32:	bf00      	nop
- 8001c34:	3710      	adds	r7, #16
- 8001c36:	46bd      	mov	sp, r7
- 8001c38:	bd80      	pop	{r7, pc}
- 8001c3a:	bf00      	nop
- 8001c3c:	58000080 	.word	0x58000080
-
-08001c40 <HAL_ETH_TxCpltCallback>:
-  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
-  *         the configuration information for ETHERNET module
-  * @retval None
-  */
-__weak void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth)
-{
- 8001c40:	b480      	push	{r7}
- 8001c42:	b083      	sub	sp, #12
- 8001c44:	af00      	add	r7, sp, #0
- 8001c46:	6078      	str	r0, [r7, #4]
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(heth);
-  /* NOTE : This function Should not be modified, when the callback is needed,
-  the HAL_ETH_TxCpltCallback could be implemented in the user file
-  */
-}
- 8001c48:	bf00      	nop
- 8001c4a:	370c      	adds	r7, #12
- 8001c4c:	46bd      	mov	sp, r7
- 8001c4e:	f85d 7b04 	ldr.w	r7, [sp], #4
- 8001c52:	4770      	bx	lr
-
-08001c54 <HAL_ETH_RxCpltCallback>:
-  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
-  *         the configuration information for ETHERNET module
-  * @retval None
-  */
-__weak void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth)
-{
- 8001c54:	b480      	push	{r7}
- 8001c56:	b083      	sub	sp, #12
- 8001c58:	af00      	add	r7, sp, #0
- 8001c5a:	6078      	str	r0, [r7, #4]
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(heth);
-  /* NOTE : This function Should not be modified, when the callback is needed,
-  the HAL_ETH_RxCpltCallback could be implemented in the user file
-  */
-}
- 8001c5c:	bf00      	nop
- 8001c5e:	370c      	adds	r7, #12
- 8001c60:	46bd      	mov	sp, r7
- 8001c62:	f85d 7b04 	ldr.w	r7, [sp], #4
- 8001c66:	4770      	bx	lr
-
-08001c68 <HAL_ETH_ErrorCallback>:
-  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
-  *         the configuration information for ETHERNET module
-  * @retval None
-  */
-__weak void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth)
-{
- 8001c68:	b480      	push	{r7}
- 8001c6a:	b083      	sub	sp, #12
- 8001c6c:	af00      	add	r7, sp, #0
- 8001c6e:	6078      	str	r0, [r7, #4]
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(heth);
-  /* NOTE : This function Should not be modified, when the callback is needed,
-  the HAL_ETH_ErrorCallback could be implemented in the user file
-  */
-}
- 8001c70:	bf00      	nop
- 8001c72:	370c      	adds	r7, #12
- 8001c74:	46bd      	mov	sp, r7
- 8001c76:	f85d 7b04 	ldr.w	r7, [sp], #4
- 8001c7a:	4770      	bx	lr
-
-08001c7c <HAL_ETH_PMTCallback>:
-  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
-  *         the configuration information for ETHERNET module
-  * @retval None
-  */
-__weak void HAL_ETH_PMTCallback(ETH_HandleTypeDef *heth)
-{
- 8001c7c:	b480      	push	{r7}
- 8001c7e:	b083      	sub	sp, #12
- 8001c80:	af00      	add	r7, sp, #0
- 8001c82:	6078      	str	r0, [r7, #4]
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(heth);
-  /* NOTE : This function Should not be modified, when the callback is needed,
-  the HAL_ETH_PMTCallback could be implemented in the user file
-  */
-}
- 8001c84:	bf00      	nop
- 8001c86:	370c      	adds	r7, #12
- 8001c88:	46bd      	mov	sp, r7
- 8001c8a:	f85d 7b04 	ldr.w	r7, [sp], #4
- 8001c8e:	4770      	bx	lr
-
-08001c90 <HAL_ETH_EEECallback>:
-  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
-  *         the configuration information for ETHERNET module
-  * @retval None
-  */
-__weak void HAL_ETH_EEECallback(ETH_HandleTypeDef *heth)
-{
- 8001c90:	b480      	push	{r7}
- 8001c92:	b083      	sub	sp, #12
- 8001c94:	af00      	add	r7, sp, #0
- 8001c96:	6078      	str	r0, [r7, #4]
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(heth);
-  /* NOTE : This function Should not be modified, when the callback is needed,
-  the HAL_ETH_EEECallback could be implemented in the user file
-  */
-}
- 8001c98:	bf00      	nop
- 8001c9a:	370c      	adds	r7, #12
- 8001c9c:	46bd      	mov	sp, r7
- 8001c9e:	f85d 7b04 	ldr.w	r7, [sp], #4
- 8001ca2:	4770      	bx	lr
-
-08001ca4 <HAL_ETH_WakeUpCallback>:
-  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
-  *         the configuration information for ETHERNET module
-  * @retval None
-  */
-__weak void HAL_ETH_WakeUpCallback(ETH_HandleTypeDef *heth)
-{
- 8001ca4:	b480      	push	{r7}
- 8001ca6:	b083      	sub	sp, #12
- 8001ca8:	af00      	add	r7, sp, #0
- 8001caa:	6078      	str	r0, [r7, #4]
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(heth);
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_ETH_WakeUpCallback could be implemented in the user file
-   */
-}
- 8001cac:	bf00      	nop
- 8001cae:	370c      	adds	r7, #12
- 8001cb0:	46bd      	mov	sp, r7
- 8001cb2:	f85d 7b04 	ldr.w	r7, [sp], #4
- 8001cb6:	4770      	bx	lr
-
-08001cb8 <HAL_ETH_ReadPHYRegister>:
-  * @param pRegValue: parameter to hold read value
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg,
-                                          uint32_t *pRegValue)
-{
- 8001cb8:	b580      	push	{r7, lr}
- 8001cba:	b086      	sub	sp, #24
- 8001cbc:	af00      	add	r7, sp, #0
- 8001cbe:	60f8      	str	r0, [r7, #12]
- 8001cc0:	60b9      	str	r1, [r7, #8]
- 8001cc2:	607a      	str	r2, [r7, #4]
- 8001cc4:	603b      	str	r3, [r7, #0]
-  uint32_t tickstart;
-  uint32_t tmpreg;
-
-  /* Check for the Busy flag */
-  if (READ_BIT(heth->Instance->MACMDIOAR, ETH_MACMDIOAR_MB) != (uint32_t)RESET)
- 8001cc6:	68fb      	ldr	r3, [r7, #12]
- 8001cc8:	681b      	ldr	r3, [r3, #0]
- 8001cca:	f8d3 3200 	ldr.w	r3, [r3, #512]	; 0x200
- 8001cce:	f003 0301 	and.w	r3, r3, #1
- 8001cd2:	2b00      	cmp	r3, #0
- 8001cd4:	d001      	beq.n	8001cda <HAL_ETH_ReadPHYRegister+0x22>
-  {
-    return HAL_ERROR;
- 8001cd6:	2301      	movs	r3, #1
- 8001cd8:	e03e      	b.n	8001d58 <HAL_ETH_ReadPHYRegister+0xa0>
-  }
-
-  /* Get the  MACMDIOAR value */
-  WRITE_REG(tmpreg, heth->Instance->MACMDIOAR);
- 8001cda:	68fb      	ldr	r3, [r7, #12]
- 8001cdc:	681b      	ldr	r3, [r3, #0]
- 8001cde:	f8d3 3200 	ldr.w	r3, [r3, #512]	; 0x200
- 8001ce2:	617b      	str	r3, [r7, #20]
-     - Set the PHY device address
-     - Set the PHY register address
-     - Set the read mode
-     - Set the MII Busy bit */
-
-  MODIFY_REG(tmpreg, ETH_MACMDIOAR_PA, (PHYAddr << 21));
- 8001ce4:	697b      	ldr	r3, [r7, #20]
- 8001ce6:	f023 7278 	bic.w	r2, r3, #65011712	; 0x3e00000
- 8001cea:	68bb      	ldr	r3, [r7, #8]
- 8001cec:	055b      	lsls	r3, r3, #21
- 8001cee:	4313      	orrs	r3, r2
- 8001cf0:	617b      	str	r3, [r7, #20]
-  MODIFY_REG(tmpreg, ETH_MACMDIOAR_RDA, (PHYReg << 16));
- 8001cf2:	697b      	ldr	r3, [r7, #20]
- 8001cf4:	f423 12f8 	bic.w	r2, r3, #2031616	; 0x1f0000
- 8001cf8:	687b      	ldr	r3, [r7, #4]
- 8001cfa:	041b      	lsls	r3, r3, #16
- 8001cfc:	4313      	orrs	r3, r2
- 8001cfe:	617b      	str	r3, [r7, #20]
-  MODIFY_REG(tmpreg, ETH_MACMDIOAR_MOC, ETH_MACMDIOAR_MOC_RD);
- 8001d00:	697b      	ldr	r3, [r7, #20]
- 8001d02:	f043 030c 	orr.w	r3, r3, #12
- 8001d06:	617b      	str	r3, [r7, #20]
-  SET_BIT(tmpreg, ETH_MACMDIOAR_MB);
- 8001d08:	697b      	ldr	r3, [r7, #20]
- 8001d0a:	f043 0301 	orr.w	r3, r3, #1
- 8001d0e:	617b      	str	r3, [r7, #20]
-
-  /* Write the result value into the MDII Address register */
-  WRITE_REG(heth->Instance->MACMDIOAR, tmpreg);
- 8001d10:	68fb      	ldr	r3, [r7, #12]
- 8001d12:	681b      	ldr	r3, [r3, #0]
- 8001d14:	697a      	ldr	r2, [r7, #20]
- 8001d16:	f8c3 2200 	str.w	r2, [r3, #512]	; 0x200
-
-  tickstart = HAL_GetTick();
- 8001d1a:	f7ff f977 	bl	800100c <HAL_GetTick>
- 8001d1e:	6138      	str	r0, [r7, #16]
-
-  /* Wait for the Busy flag */
-  while (READ_BIT(heth->Instance->MACMDIOAR, ETH_MACMDIOAR_MB) > 0U)
- 8001d20:	e009      	b.n	8001d36 <HAL_ETH_ReadPHYRegister+0x7e>
-  {
-    if (((HAL_GetTick() - tickstart) > ETH_MDIO_BUS_TIMEOUT))
- 8001d22:	f7ff f973 	bl	800100c <HAL_GetTick>
- 8001d26:	4602      	mov	r2, r0
- 8001d28:	693b      	ldr	r3, [r7, #16]
- 8001d2a:	1ad3      	subs	r3, r2, r3
- 8001d2c:	f5b3 7f7a 	cmp.w	r3, #1000	; 0x3e8
- 8001d30:	d901      	bls.n	8001d36 <HAL_ETH_ReadPHYRegister+0x7e>
-    {
-      return HAL_ERROR;
- 8001d32:	2301      	movs	r3, #1
- 8001d34:	e010      	b.n	8001d58 <HAL_ETH_ReadPHYRegister+0xa0>
-  while (READ_BIT(heth->Instance->MACMDIOAR, ETH_MACMDIOAR_MB) > 0U)
- 8001d36:	68fb      	ldr	r3, [r7, #12]
- 8001d38:	681b      	ldr	r3, [r3, #0]
- 8001d3a:	f8d3 3200 	ldr.w	r3, [r3, #512]	; 0x200
- 8001d3e:	f003 0301 	and.w	r3, r3, #1
- 8001d42:	2b00      	cmp	r3, #0
- 8001d44:	d1ed      	bne.n	8001d22 <HAL_ETH_ReadPHYRegister+0x6a>
-    }
-  }
-
-  /* Get MACMIIDR value */
-  WRITE_REG(*pRegValue, (uint16_t)heth->Instance->MACMDIODR);
- 8001d46:	68fb      	ldr	r3, [r7, #12]
- 8001d48:	681b      	ldr	r3, [r3, #0]
- 8001d4a:	f8d3 3204 	ldr.w	r3, [r3, #516]	; 0x204
- 8001d4e:	b29b      	uxth	r3, r3
- 8001d50:	461a      	mov	r2, r3
- 8001d52:	683b      	ldr	r3, [r7, #0]
- 8001d54:	601a      	str	r2, [r3, #0]
-
-  return HAL_OK;
- 8001d56:	2300      	movs	r3, #0
-}
- 8001d58:	4618      	mov	r0, r3
- 8001d5a:	3718      	adds	r7, #24
- 8001d5c:	46bd      	mov	sp, r7
- 8001d5e:	bd80      	pop	{r7, pc}
-
-08001d60 <HAL_ETH_WritePHYRegister>:
-  * @param  RegValue: the value to write
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg,
-                                           uint32_t RegValue)
-{
- 8001d60:	b580      	push	{r7, lr}
- 8001d62:	b086      	sub	sp, #24
- 8001d64:	af00      	add	r7, sp, #0
- 8001d66:	60f8      	str	r0, [r7, #12]
- 8001d68:	60b9      	str	r1, [r7, #8]
- 8001d6a:	607a      	str	r2, [r7, #4]
- 8001d6c:	603b      	str	r3, [r7, #0]
-  uint32_t tickstart;
-  uint32_t tmpreg;
-
-  /* Check for the Busy flag */
-  if (READ_BIT(heth->Instance->MACMDIOAR, ETH_MACMDIOAR_MB) != (uint32_t)RESET)
- 8001d6e:	68fb      	ldr	r3, [r7, #12]
- 8001d70:	681b      	ldr	r3, [r3, #0]
- 8001d72:	f8d3 3200 	ldr.w	r3, [r3, #512]	; 0x200
- 8001d76:	f003 0301 	and.w	r3, r3, #1
- 8001d7a:	2b00      	cmp	r3, #0
- 8001d7c:	d001      	beq.n	8001d82 <HAL_ETH_WritePHYRegister+0x22>
-  {
-    return HAL_ERROR;
- 8001d7e:	2301      	movs	r3, #1
- 8001d80:	e03c      	b.n	8001dfc <HAL_ETH_WritePHYRegister+0x9c>
-  }
-
-  /* Get the  MACMDIOAR value */
-  WRITE_REG(tmpreg, heth->Instance->MACMDIOAR);
- 8001d82:	68fb      	ldr	r3, [r7, #12]
- 8001d84:	681b      	ldr	r3, [r3, #0]
- 8001d86:	f8d3 3200 	ldr.w	r3, [r3, #512]	; 0x200
- 8001d8a:	617b      	str	r3, [r7, #20]
-     - Set the PHY device address
-     - Set the PHY register address
-     - Set the write mode
-     - Set the MII Busy bit */
-
-  MODIFY_REG(tmpreg, ETH_MACMDIOAR_PA, (PHYAddr << 21));
- 8001d8c:	697b      	ldr	r3, [r7, #20]
- 8001d8e:	f023 7278 	bic.w	r2, r3, #65011712	; 0x3e00000
- 8001d92:	68bb      	ldr	r3, [r7, #8]
- 8001d94:	055b      	lsls	r3, r3, #21
- 8001d96:	4313      	orrs	r3, r2
- 8001d98:	617b      	str	r3, [r7, #20]
-  MODIFY_REG(tmpreg, ETH_MACMDIOAR_RDA, (PHYReg << 16));
- 8001d9a:	697b      	ldr	r3, [r7, #20]
- 8001d9c:	f423 12f8 	bic.w	r2, r3, #2031616	; 0x1f0000
- 8001da0:	687b      	ldr	r3, [r7, #4]
- 8001da2:	041b      	lsls	r3, r3, #16
- 8001da4:	4313      	orrs	r3, r2
- 8001da6:	617b      	str	r3, [r7, #20]
-  MODIFY_REG(tmpreg, ETH_MACMDIOAR_MOC, ETH_MACMDIOAR_MOC_WR);
- 8001da8:	697b      	ldr	r3, [r7, #20]
- 8001daa:	f023 030c 	bic.w	r3, r3, #12
- 8001dae:	f043 0304 	orr.w	r3, r3, #4
- 8001db2:	617b      	str	r3, [r7, #20]
-  SET_BIT(tmpreg, ETH_MACMDIOAR_MB);
- 8001db4:	697b      	ldr	r3, [r7, #20]
- 8001db6:	f043 0301 	orr.w	r3, r3, #1
- 8001dba:	617b      	str	r3, [r7, #20]
-
-
-  /* Give the value to the MII data register */
-  WRITE_REG(ETH->MACMDIODR, (uint16_t)RegValue);
- 8001dbc:	683b      	ldr	r3, [r7, #0]
- 8001dbe:	b29a      	uxth	r2, r3
- 8001dc0:	4b10      	ldr	r3, [pc, #64]	; (8001e04 <HAL_ETH_WritePHYRegister+0xa4>)
- 8001dc2:	f8c3 2204 	str.w	r2, [r3, #516]	; 0x204
-
-  /* Write the result value into the MII Address register */
-  WRITE_REG(ETH->MACMDIOAR, tmpreg);
- 8001dc6:	4a0f      	ldr	r2, [pc, #60]	; (8001e04 <HAL_ETH_WritePHYRegister+0xa4>)
- 8001dc8:	697b      	ldr	r3, [r7, #20]
- 8001dca:	f8c2 3200 	str.w	r3, [r2, #512]	; 0x200
-
-  tickstart = HAL_GetTick();
- 8001dce:	f7ff f91d 	bl	800100c <HAL_GetTick>
- 8001dd2:	6138      	str	r0, [r7, #16]
-
-  /* Wait for the Busy flag */
-  while (READ_BIT(heth->Instance->MACMDIOAR, ETH_MACMDIOAR_MB) > 0U)
- 8001dd4:	e009      	b.n	8001dea <HAL_ETH_WritePHYRegister+0x8a>
-  {
-    if (((HAL_GetTick() - tickstart) > ETH_MDIO_BUS_TIMEOUT))
- 8001dd6:	f7ff f919 	bl	800100c <HAL_GetTick>
- 8001dda:	4602      	mov	r2, r0
- 8001ddc:	693b      	ldr	r3, [r7, #16]
- 8001dde:	1ad3      	subs	r3, r2, r3
- 8001de0:	f5b3 7f7a 	cmp.w	r3, #1000	; 0x3e8
- 8001de4:	d901      	bls.n	8001dea <HAL_ETH_WritePHYRegister+0x8a>
-    {
-      return HAL_ERROR;
- 8001de6:	2301      	movs	r3, #1
- 8001de8:	e008      	b.n	8001dfc <HAL_ETH_WritePHYRegister+0x9c>
-  while (READ_BIT(heth->Instance->MACMDIOAR, ETH_MACMDIOAR_MB) > 0U)
- 8001dea:	68fb      	ldr	r3, [r7, #12]
- 8001dec:	681b      	ldr	r3, [r3, #0]
- 8001dee:	f8d3 3200 	ldr.w	r3, [r3, #512]	; 0x200
- 8001df2:	f003 0301 	and.w	r3, r3, #1
- 8001df6:	2b00      	cmp	r3, #0
- 8001df8:	d1ed      	bne.n	8001dd6 <HAL_ETH_WritePHYRegister+0x76>
-    }
-  }
-
-  return HAL_OK;
- 8001dfa:	2300      	movs	r3, #0
-}
- 8001dfc:	4618      	mov	r0, r3
- 8001dfe:	3718      	adds	r7, #24
- 8001e00:	46bd      	mov	sp, r7
- 8001e02:	bd80      	pop	{r7, pc}
- 8001e04:	40028000 	.word	0x40028000
-
-08001e08 <HAL_ETH_GetMACConfig>:
-  * @param  macconf: pointer to a ETH_MACConfigTypeDef structure that will hold
-  *         the configuration of the MAC.
-  * @retval HAL Status
-  */
-HAL_StatusTypeDef HAL_ETH_GetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf)
-{
- 8001e08:	b480      	push	{r7}
- 8001e0a:	b083      	sub	sp, #12
- 8001e0c:	af00      	add	r7, sp, #0
- 8001e0e:	6078      	str	r0, [r7, #4]
- 8001e10:	6039      	str	r1, [r7, #0]
-  if (macconf == NULL)
- 8001e12:	683b      	ldr	r3, [r7, #0]
- 8001e14:	2b00      	cmp	r3, #0
- 8001e16:	d101      	bne.n	8001e1c <HAL_ETH_GetMACConfig+0x14>
-  {
-    return HAL_ERROR;
- 8001e18:	2301      	movs	r3, #1
- 8001e1a:	e1c3      	b.n	80021a4 <HAL_ETH_GetMACConfig+0x39c>
-  }
-
-  /* Get MAC parameters */
-  macconf->PreambleLength = READ_BIT(heth->Instance->MACCR, ETH_MACCR_PRELEN);
- 8001e1c:	687b      	ldr	r3, [r7, #4]
- 8001e1e:	681b      	ldr	r3, [r3, #0]
- 8001e20:	681b      	ldr	r3, [r3, #0]
- 8001e22:	f003 020c 	and.w	r2, r3, #12
- 8001e26:	683b      	ldr	r3, [r7, #0]
- 8001e28:	62da      	str	r2, [r3, #44]	; 0x2c
-  macconf->DeferralCheck = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_DC) >> 4) > 0U) ? ENABLE : DISABLE;
- 8001e2a:	687b      	ldr	r3, [r7, #4]
- 8001e2c:	681b      	ldr	r3, [r3, #0]
- 8001e2e:	681b      	ldr	r3, [r3, #0]
- 8001e30:	f003 0310 	and.w	r3, r3, #16
- 8001e34:	2b00      	cmp	r3, #0
- 8001e36:	bf14      	ite	ne
- 8001e38:	2301      	movne	r3, #1
- 8001e3a:	2300      	moveq	r3, #0
- 8001e3c:	b2db      	uxtb	r3, r3
- 8001e3e:	461a      	mov	r2, r3
- 8001e40:	683b      	ldr	r3, [r7, #0]
- 8001e42:	f883 2028 	strb.w	r2, [r3, #40]	; 0x28
-  macconf->BackOffLimit = READ_BIT(heth->Instance->MACCR, ETH_MACCR_BL);
- 8001e46:	687b      	ldr	r3, [r7, #4]
- 8001e48:	681b      	ldr	r3, [r3, #0]
- 8001e4a:	681b      	ldr	r3, [r3, #0]
- 8001e4c:	f003 0260 	and.w	r2, r3, #96	; 0x60
- 8001e50:	683b      	ldr	r3, [r7, #0]
- 8001e52:	625a      	str	r2, [r3, #36]	; 0x24
-  macconf->RetryTransmission = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_DR) >> 8) == 0U) ? ENABLE : DISABLE;
- 8001e54:	687b      	ldr	r3, [r7, #4]
- 8001e56:	681b      	ldr	r3, [r3, #0]
- 8001e58:	681b      	ldr	r3, [r3, #0]
- 8001e5a:	f403 7380 	and.w	r3, r3, #256	; 0x100
- 8001e5e:	2b00      	cmp	r3, #0
- 8001e60:	bf0c      	ite	eq
- 8001e62:	2301      	moveq	r3, #1
- 8001e64:	2300      	movne	r3, #0
- 8001e66:	b2db      	uxtb	r3, r3
- 8001e68:	461a      	mov	r2, r3
- 8001e6a:	683b      	ldr	r3, [r7, #0]
- 8001e6c:	f883 2020 	strb.w	r2, [r3, #32]
-  macconf->CarrierSenseDuringTransmit = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_DCRS) >> 9) > 0U)
- 8001e70:	687b      	ldr	r3, [r7, #4]
- 8001e72:	681b      	ldr	r3, [r3, #0]
- 8001e74:	681b      	ldr	r3, [r3, #0]
- 8001e76:	f403 7300 	and.w	r3, r3, #512	; 0x200
-                                        ? ENABLE : DISABLE;
- 8001e7a:	2b00      	cmp	r3, #0
- 8001e7c:	bf14      	ite	ne
- 8001e7e:	2301      	movne	r3, #1
- 8001e80:	2300      	moveq	r3, #0
- 8001e82:	b2db      	uxtb	r3, r3
- 8001e84:	461a      	mov	r2, r3
-  macconf->CarrierSenseDuringTransmit = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_DCRS) >> 9) > 0U)
- 8001e86:	683b      	ldr	r3, [r7, #0]
- 8001e88:	77da      	strb	r2, [r3, #31]
-  macconf->ReceiveOwn = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_DO) >> 10) == 0U) ? ENABLE : DISABLE;
- 8001e8a:	687b      	ldr	r3, [r7, #4]
- 8001e8c:	681b      	ldr	r3, [r3, #0]
- 8001e8e:	681b      	ldr	r3, [r3, #0]
- 8001e90:	f403 6380 	and.w	r3, r3, #1024	; 0x400
- 8001e94:	2b00      	cmp	r3, #0
- 8001e96:	bf0c      	ite	eq
- 8001e98:	2301      	moveq	r3, #1
- 8001e9a:	2300      	movne	r3, #0
- 8001e9c:	b2db      	uxtb	r3, r3
- 8001e9e:	461a      	mov	r2, r3
- 8001ea0:	683b      	ldr	r3, [r7, #0]
- 8001ea2:	779a      	strb	r2, [r3, #30]
-  macconf->CarrierSenseBeforeTransmit = ((READ_BIT(heth->Instance->MACCR,
- 8001ea4:	687b      	ldr	r3, [r7, #4]
- 8001ea6:	681b      	ldr	r3, [r3, #0]
- 8001ea8:	681b      	ldr	r3, [r3, #0]
-                                                   ETH_MACCR_ECRSFD) >> 11) > 0U) ? ENABLE : DISABLE;
- 8001eaa:	f403 6300 	and.w	r3, r3, #2048	; 0x800
- 8001eae:	2b00      	cmp	r3, #0
- 8001eb0:	bf14      	ite	ne
- 8001eb2:	2301      	movne	r3, #1
- 8001eb4:	2300      	moveq	r3, #0
- 8001eb6:	b2db      	uxtb	r3, r3
- 8001eb8:	461a      	mov	r2, r3
-  macconf->CarrierSenseBeforeTransmit = ((READ_BIT(heth->Instance->MACCR,
- 8001eba:	683b      	ldr	r3, [r7, #0]
- 8001ebc:	775a      	strb	r2, [r3, #29]
-  macconf->LoopbackMode = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_LM) >> 12) > 0U) ? ENABLE : DISABLE;
- 8001ebe:	687b      	ldr	r3, [r7, #4]
- 8001ec0:	681b      	ldr	r3, [r3, #0]
- 8001ec2:	681b      	ldr	r3, [r3, #0]
- 8001ec4:	f403 5380 	and.w	r3, r3, #4096	; 0x1000
- 8001ec8:	2b00      	cmp	r3, #0
- 8001eca:	bf14      	ite	ne
- 8001ecc:	2301      	movne	r3, #1
- 8001ece:	2300      	moveq	r3, #0
- 8001ed0:	b2db      	uxtb	r3, r3
- 8001ed2:	461a      	mov	r2, r3
- 8001ed4:	683b      	ldr	r3, [r7, #0]
- 8001ed6:	771a      	strb	r2, [r3, #28]
-  macconf->DuplexMode = READ_BIT(heth->Instance->MACCR, ETH_MACCR_DM);
- 8001ed8:	687b      	ldr	r3, [r7, #4]
- 8001eda:	681b      	ldr	r3, [r3, #0]
- 8001edc:	681b      	ldr	r3, [r3, #0]
- 8001ede:	f403 5200 	and.w	r2, r3, #8192	; 0x2000
- 8001ee2:	683b      	ldr	r3, [r7, #0]
- 8001ee4:	619a      	str	r2, [r3, #24]
-  macconf->Speed = READ_BIT(heth->Instance->MACCR, ETH_MACCR_FES);
- 8001ee6:	687b      	ldr	r3, [r7, #4]
- 8001ee8:	681b      	ldr	r3, [r3, #0]
- 8001eea:	681b      	ldr	r3, [r3, #0]
- 8001eec:	f403 4280 	and.w	r2, r3, #16384	; 0x4000
- 8001ef0:	683b      	ldr	r3, [r7, #0]
- 8001ef2:	615a      	str	r2, [r3, #20]
-  macconf->JumboPacket = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_JE) >> 16) > 0U) ? ENABLE : DISABLE;
- 8001ef4:	687b      	ldr	r3, [r7, #4]
- 8001ef6:	681b      	ldr	r3, [r3, #0]
- 8001ef8:	681b      	ldr	r3, [r3, #0]
- 8001efa:	f403 3380 	and.w	r3, r3, #65536	; 0x10000
- 8001efe:	2b00      	cmp	r3, #0
- 8001f00:	bf14      	ite	ne
- 8001f02:	2301      	movne	r3, #1
- 8001f04:	2300      	moveq	r3, #0
- 8001f06:	b2db      	uxtb	r3, r3
- 8001f08:	461a      	mov	r2, r3
- 8001f0a:	683b      	ldr	r3, [r7, #0]
- 8001f0c:	749a      	strb	r2, [r3, #18]
-  macconf->Jabber = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_JD) >> 17) == 0U) ? ENABLE : DISABLE;
- 8001f0e:	687b      	ldr	r3, [r7, #4]
- 8001f10:	681b      	ldr	r3, [r3, #0]
- 8001f12:	681b      	ldr	r3, [r3, #0]
- 8001f14:	f403 3300 	and.w	r3, r3, #131072	; 0x20000
- 8001f18:	2b00      	cmp	r3, #0
- 8001f1a:	bf0c      	ite	eq
- 8001f1c:	2301      	moveq	r3, #1
- 8001f1e:	2300      	movne	r3, #0
- 8001f20:	b2db      	uxtb	r3, r3
- 8001f22:	461a      	mov	r2, r3
- 8001f24:	683b      	ldr	r3, [r7, #0]
- 8001f26:	745a      	strb	r2, [r3, #17]
-  macconf->Watchdog = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_WD) >> 19) == 0U) ? ENABLE : DISABLE;
- 8001f28:	687b      	ldr	r3, [r7, #4]
- 8001f2a:	681b      	ldr	r3, [r3, #0]
- 8001f2c:	681b      	ldr	r3, [r3, #0]
- 8001f2e:	f403 2300 	and.w	r3, r3, #524288	; 0x80000
- 8001f32:	2b00      	cmp	r3, #0
- 8001f34:	bf0c      	ite	eq
- 8001f36:	2301      	moveq	r3, #1
- 8001f38:	2300      	movne	r3, #0
- 8001f3a:	b2db      	uxtb	r3, r3
- 8001f3c:	461a      	mov	r2, r3
- 8001f3e:	683b      	ldr	r3, [r7, #0]
- 8001f40:	741a      	strb	r2, [r3, #16]
-  macconf->AutomaticPadCRCStrip = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_ACS) >> 20) > 0U) ? ENABLE : DISABLE;
- 8001f42:	687b      	ldr	r3, [r7, #4]
- 8001f44:	681b      	ldr	r3, [r3, #0]
- 8001f46:	681b      	ldr	r3, [r3, #0]
- 8001f48:	f403 1380 	and.w	r3, r3, #1048576	; 0x100000
- 8001f4c:	2b00      	cmp	r3, #0
- 8001f4e:	bf14      	ite	ne
- 8001f50:	2301      	movne	r3, #1
- 8001f52:	2300      	moveq	r3, #0
- 8001f54:	b2db      	uxtb	r3, r3
- 8001f56:	461a      	mov	r2, r3
- 8001f58:	683b      	ldr	r3, [r7, #0]
- 8001f5a:	73da      	strb	r2, [r3, #15]
-  macconf->CRCStripTypePacket = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_CST) >> 21) > 0U) ? ENABLE : DISABLE;
- 8001f5c:	687b      	ldr	r3, [r7, #4]
- 8001f5e:	681b      	ldr	r3, [r3, #0]
- 8001f60:	681b      	ldr	r3, [r3, #0]
- 8001f62:	f403 1300 	and.w	r3, r3, #2097152	; 0x200000
- 8001f66:	2b00      	cmp	r3, #0
- 8001f68:	bf14      	ite	ne
- 8001f6a:	2301      	movne	r3, #1
- 8001f6c:	2300      	moveq	r3, #0
- 8001f6e:	b2db      	uxtb	r3, r3
- 8001f70:	461a      	mov	r2, r3
- 8001f72:	683b      	ldr	r3, [r7, #0]
- 8001f74:	739a      	strb	r2, [r3, #14]
-  macconf->Support2KPacket = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_S2KP) >> 22) > 0U) ? ENABLE : DISABLE;
- 8001f76:	687b      	ldr	r3, [r7, #4]
- 8001f78:	681b      	ldr	r3, [r3, #0]
- 8001f7a:	681b      	ldr	r3, [r3, #0]
- 8001f7c:	f403 0380 	and.w	r3, r3, #4194304	; 0x400000
- 8001f80:	2b00      	cmp	r3, #0
- 8001f82:	bf14      	ite	ne
- 8001f84:	2301      	movne	r3, #1
- 8001f86:	2300      	moveq	r3, #0
- 8001f88:	b2db      	uxtb	r3, r3
- 8001f8a:	461a      	mov	r2, r3
- 8001f8c:	683b      	ldr	r3, [r7, #0]
- 8001f8e:	735a      	strb	r2, [r3, #13]
-  macconf->GiantPacketSizeLimitControl = ((READ_BIT(heth->Instance->MACCR,
- 8001f90:	687b      	ldr	r3, [r7, #4]
- 8001f92:	681b      	ldr	r3, [r3, #0]
- 8001f94:	681b      	ldr	r3, [r3, #0]
-                                                    ETH_MACCR_GPSLCE) >> 23) > 0U) ? ENABLE : DISABLE;
- 8001f96:	f403 0300 	and.w	r3, r3, #8388608	; 0x800000
- 8001f9a:	2b00      	cmp	r3, #0
- 8001f9c:	bf14      	ite	ne
- 8001f9e:	2301      	movne	r3, #1
- 8001fa0:	2300      	moveq	r3, #0
- 8001fa2:	b2db      	uxtb	r3, r3
- 8001fa4:	461a      	mov	r2, r3
-  macconf->GiantPacketSizeLimitControl = ((READ_BIT(heth->Instance->MACCR,
- 8001fa6:	683b      	ldr	r3, [r7, #0]
- 8001fa8:	731a      	strb	r2, [r3, #12]
-  macconf->InterPacketGapVal = READ_BIT(heth->Instance->MACCR, ETH_MACCR_IPG);
- 8001faa:	687b      	ldr	r3, [r7, #4]
- 8001fac:	681b      	ldr	r3, [r3, #0]
- 8001fae:	681b      	ldr	r3, [r3, #0]
- 8001fb0:	f003 62e0 	and.w	r2, r3, #117440512	; 0x7000000
- 8001fb4:	683b      	ldr	r3, [r7, #0]
- 8001fb6:	609a      	str	r2, [r3, #8]
-  macconf->ChecksumOffload = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_IPC) >> 27) > 0U) ? ENABLE : DISABLE;
- 8001fb8:	687b      	ldr	r3, [r7, #4]
- 8001fba:	681b      	ldr	r3, [r3, #0]
- 8001fbc:	681b      	ldr	r3, [r3, #0]
- 8001fbe:	f003 6300 	and.w	r3, r3, #134217728	; 0x8000000
- 8001fc2:	2b00      	cmp	r3, #0
- 8001fc4:	bf14      	ite	ne
- 8001fc6:	2301      	movne	r3, #1
- 8001fc8:	2300      	moveq	r3, #0
- 8001fca:	b2db      	uxtb	r3, r3
- 8001fcc:	461a      	mov	r2, r3
- 8001fce:	683b      	ldr	r3, [r7, #0]
- 8001fd0:	711a      	strb	r2, [r3, #4]
-  macconf->SourceAddrControl = READ_BIT(heth->Instance->MACCR, ETH_MACCR_SARC);
- 8001fd2:	687b      	ldr	r3, [r7, #4]
- 8001fd4:	681b      	ldr	r3, [r3, #0]
- 8001fd6:	681b      	ldr	r3, [r3, #0]
- 8001fd8:	f003 42e0 	and.w	r2, r3, #1879048192	; 0x70000000
- 8001fdc:	683b      	ldr	r3, [r7, #0]
- 8001fde:	601a      	str	r2, [r3, #0]
-
-  macconf->GiantPacketSizeLimit = READ_BIT(heth->Instance->MACECR, ETH_MACECR_GPSL);
- 8001fe0:	687b      	ldr	r3, [r7, #4]
- 8001fe2:	681b      	ldr	r3, [r3, #0]
- 8001fe4:	685b      	ldr	r3, [r3, #4]
- 8001fe6:	f3c3 020d 	ubfx	r2, r3, #0, #14
- 8001fea:	683b      	ldr	r3, [r7, #0]
- 8001fec:	635a      	str	r2, [r3, #52]	; 0x34
-  macconf->CRCCheckingRxPackets = ((READ_BIT(heth->Instance->MACECR, ETH_MACECR_DCRCC) >> 16) == 0U) ? ENABLE : DISABLE;
- 8001fee:	687b      	ldr	r3, [r7, #4]
- 8001ff0:	681b      	ldr	r3, [r3, #0]
- 8001ff2:	685b      	ldr	r3, [r3, #4]
- 8001ff4:	f403 3380 	and.w	r3, r3, #65536	; 0x10000
- 8001ff8:	2b00      	cmp	r3, #0
- 8001ffa:	bf0c      	ite	eq
- 8001ffc:	2301      	moveq	r3, #1
- 8001ffe:	2300      	movne	r3, #0
- 8002000:	b2db      	uxtb	r3, r3
- 8002002:	461a      	mov	r2, r3
- 8002004:	683b      	ldr	r3, [r7, #0]
- 8002006:	f883 2032 	strb.w	r2, [r3, #50]	; 0x32
-  macconf->SlowProtocolDetect = ((READ_BIT(heth->Instance->MACECR, ETH_MACECR_SPEN) >> 17) > 0U) ? ENABLE : DISABLE;
- 800200a:	687b      	ldr	r3, [r7, #4]
- 800200c:	681b      	ldr	r3, [r3, #0]
- 800200e:	685b      	ldr	r3, [r3, #4]
- 8002010:	f403 3300 	and.w	r3, r3, #131072	; 0x20000
- 8002014:	2b00      	cmp	r3, #0
- 8002016:	bf14      	ite	ne
- 8002018:	2301      	movne	r3, #1
- 800201a:	2300      	moveq	r3, #0
- 800201c:	b2db      	uxtb	r3, r3
- 800201e:	461a      	mov	r2, r3
- 8002020:	683b      	ldr	r3, [r7, #0]
- 8002022:	f883 2031 	strb.w	r2, [r3, #49]	; 0x31
-  macconf->UnicastSlowProtocolPacketDetect = ((READ_BIT(heth->Instance->MACECR,
- 8002026:	687b      	ldr	r3, [r7, #4]
- 8002028:	681b      	ldr	r3, [r3, #0]
- 800202a:	685b      	ldr	r3, [r3, #4]
-                                                        ETH_MACECR_USP) >> 18) > 0U) ? ENABLE : DISABLE;
- 800202c:	f403 2380 	and.w	r3, r3, #262144	; 0x40000
- 8002030:	2b00      	cmp	r3, #0
- 8002032:	bf14      	ite	ne
- 8002034:	2301      	movne	r3, #1
- 8002036:	2300      	moveq	r3, #0
- 8002038:	b2db      	uxtb	r3, r3
- 800203a:	461a      	mov	r2, r3
-  macconf->UnicastSlowProtocolPacketDetect = ((READ_BIT(heth->Instance->MACECR,
- 800203c:	683b      	ldr	r3, [r7, #0]
- 800203e:	f883 2030 	strb.w	r2, [r3, #48]	; 0x30
-  macconf->ExtendedInterPacketGap = ((READ_BIT(heth->Instance->MACECR, ETH_MACECR_EIPGEN) >> 24) > 0U)
- 8002042:	687b      	ldr	r3, [r7, #4]
- 8002044:	681b      	ldr	r3, [r3, #0]
- 8002046:	685b      	ldr	r3, [r3, #4]
- 8002048:	f003 7380 	and.w	r3, r3, #16777216	; 0x1000000
-                                    ? ENABLE : DISABLE;
- 800204c:	2b00      	cmp	r3, #0
- 800204e:	bf14      	ite	ne
- 8002050:	2301      	movne	r3, #1
- 8002052:	2300      	moveq	r3, #0
- 8002054:	b2db      	uxtb	r3, r3
- 8002056:	461a      	mov	r2, r3
-  macconf->ExtendedInterPacketGap = ((READ_BIT(heth->Instance->MACECR, ETH_MACECR_EIPGEN) >> 24) > 0U)
- 8002058:	683b      	ldr	r3, [r7, #0]
- 800205a:	f883 2038 	strb.w	r2, [r3, #56]	; 0x38
-  macconf->ExtendedInterPacketGapVal = READ_BIT(heth->Instance->MACECR, ETH_MACECR_EIPG) >> 25;
- 800205e:	687b      	ldr	r3, [r7, #4]
- 8002060:	681b      	ldr	r3, [r3, #0]
- 8002062:	685b      	ldr	r3, [r3, #4]
- 8002064:	0e5b      	lsrs	r3, r3, #25
- 8002066:	f003 021f 	and.w	r2, r3, #31
- 800206a:	683b      	ldr	r3, [r7, #0]
- 800206c:	63da      	str	r2, [r3, #60]	; 0x3c
-
-
-  macconf->ProgrammableWatchdog = ((READ_BIT(heth->Instance->MACWTR, ETH_MACWTR_PWE) >> 8) > 0U) ? ENABLE : DISABLE;
- 800206e:	687b      	ldr	r3, [r7, #4]
- 8002070:	681b      	ldr	r3, [r3, #0]
- 8002072:	68db      	ldr	r3, [r3, #12]
- 8002074:	f403 7380 	and.w	r3, r3, #256	; 0x100
- 8002078:	2b00      	cmp	r3, #0
- 800207a:	bf14      	ite	ne
- 800207c:	2301      	movne	r3, #1
- 800207e:	2300      	moveq	r3, #0
- 8002080:	b2db      	uxtb	r3, r3
- 8002082:	461a      	mov	r2, r3
- 8002084:	683b      	ldr	r3, [r7, #0]
- 8002086:	f883 2040 	strb.w	r2, [r3, #64]	; 0x40
-  macconf->WatchdogTimeout = READ_BIT(heth->Instance->MACWTR, ETH_MACWTR_WTO);
- 800208a:	687b      	ldr	r3, [r7, #4]
- 800208c:	681b      	ldr	r3, [r3, #0]
- 800208e:	68db      	ldr	r3, [r3, #12]
- 8002090:	f003 020f 	and.w	r2, r3, #15
- 8002094:	683b      	ldr	r3, [r7, #0]
- 8002096:	645a      	str	r2, [r3, #68]	; 0x44
-
-  macconf->TransmitFlowControl = ((READ_BIT(heth->Instance->MACTFCR, ETH_MACTFCR_TFE) >> 1) > 0U) ? ENABLE : DISABLE;
- 8002098:	687b      	ldr	r3, [r7, #4]
- 800209a:	681b      	ldr	r3, [r3, #0]
- 800209c:	6f1b      	ldr	r3, [r3, #112]	; 0x70
- 800209e:	f003 0302 	and.w	r3, r3, #2
- 80020a2:	2b00      	cmp	r3, #0
- 80020a4:	bf14      	ite	ne
- 80020a6:	2301      	movne	r3, #1
- 80020a8:	2300      	moveq	r3, #0
- 80020aa:	b2db      	uxtb	r3, r3
- 80020ac:	461a      	mov	r2, r3
- 80020ae:	683b      	ldr	r3, [r7, #0]
- 80020b0:	f883 2054 	strb.w	r2, [r3, #84]	; 0x54
-  macconf->ZeroQuantaPause = ((READ_BIT(heth->Instance->MACTFCR, ETH_MACTFCR_DZPQ) >> 7) == 0U) ? ENABLE : DISABLE;
- 80020b4:	687b      	ldr	r3, [r7, #4]
- 80020b6:	681b      	ldr	r3, [r3, #0]
- 80020b8:	6f1b      	ldr	r3, [r3, #112]	; 0x70
- 80020ba:	f003 0380 	and.w	r3, r3, #128	; 0x80
- 80020be:	2b00      	cmp	r3, #0
- 80020c0:	bf0c      	ite	eq
- 80020c2:	2301      	moveq	r3, #1
- 80020c4:	2300      	movne	r3, #0
- 80020c6:	b2db      	uxtb	r3, r3
- 80020c8:	461a      	mov	r2, r3
- 80020ca:	683b      	ldr	r3, [r7, #0]
- 80020cc:	f883 204c 	strb.w	r2, [r3, #76]	; 0x4c
-  macconf->PauseLowThreshold = READ_BIT(heth->Instance->MACTFCR, ETH_MACTFCR_PLT);
- 80020d0:	687b      	ldr	r3, [r7, #4]
- 80020d2:	681b      	ldr	r3, [r3, #0]
- 80020d4:	6f1b      	ldr	r3, [r3, #112]	; 0x70
- 80020d6:	f003 0270 	and.w	r2, r3, #112	; 0x70
- 80020da:	683b      	ldr	r3, [r7, #0]
- 80020dc:	651a      	str	r2, [r3, #80]	; 0x50
-  macconf->PauseTime = (READ_BIT(heth->Instance->MACTFCR, ETH_MACTFCR_PT) >> 16);
- 80020de:	687b      	ldr	r3, [r7, #4]
- 80020e0:	681b      	ldr	r3, [r3, #0]
- 80020e2:	6f1b      	ldr	r3, [r3, #112]	; 0x70
- 80020e4:	0c1b      	lsrs	r3, r3, #16
- 80020e6:	b29a      	uxth	r2, r3
- 80020e8:	683b      	ldr	r3, [r7, #0]
- 80020ea:	649a      	str	r2, [r3, #72]	; 0x48
-
-
-  macconf->ReceiveFlowControl = (READ_BIT(heth->Instance->MACRFCR, ETH_MACRFCR_RFE) > 0U) ? ENABLE : DISABLE;
- 80020ec:	687b      	ldr	r3, [r7, #4]
- 80020ee:	681b      	ldr	r3, [r3, #0]
- 80020f0:	f8d3 3090 	ldr.w	r3, [r3, #144]	; 0x90
- 80020f4:	f003 0301 	and.w	r3, r3, #1
- 80020f8:	2b00      	cmp	r3, #0
- 80020fa:	bf14      	ite	ne
- 80020fc:	2301      	movne	r3, #1
- 80020fe:	2300      	moveq	r3, #0
- 8002100:	b2db      	uxtb	r3, r3
- 8002102:	461a      	mov	r2, r3
- 8002104:	683b      	ldr	r3, [r7, #0]
- 8002106:	f883 2056 	strb.w	r2, [r3, #86]	; 0x56
-  macconf->UnicastPausePacketDetect = ((READ_BIT(heth->Instance->MACRFCR, ETH_MACRFCR_UP) >> 1) > 0U)
- 800210a:	687b      	ldr	r3, [r7, #4]
- 800210c:	681b      	ldr	r3, [r3, #0]
- 800210e:	f8d3 3090 	ldr.w	r3, [r3, #144]	; 0x90
- 8002112:	f003 0302 	and.w	r3, r3, #2
-                                      ? ENABLE : DISABLE;
- 8002116:	2b00      	cmp	r3, #0
- 8002118:	bf14      	ite	ne
- 800211a:	2301      	movne	r3, #1
- 800211c:	2300      	moveq	r3, #0
- 800211e:	b2db      	uxtb	r3, r3
- 8002120:	461a      	mov	r2, r3
-  macconf->UnicastPausePacketDetect = ((READ_BIT(heth->Instance->MACRFCR, ETH_MACRFCR_UP) >> 1) > 0U)
- 8002122:	683b      	ldr	r3, [r7, #0]
- 8002124:	f883 2055 	strb.w	r2, [r3, #85]	; 0x55
-
-  macconf->TransmitQueueMode = READ_BIT(heth->Instance->MTLTQOMR, (ETH_MTLTQOMR_TTC | ETH_MTLTQOMR_TSF));
- 8002128:	687b      	ldr	r3, [r7, #4]
- 800212a:	681b      	ldr	r3, [r3, #0]
- 800212c:	f8d3 3d00 	ldr.w	r3, [r3, #3328]	; 0xd00
- 8002130:	f003 0272 	and.w	r2, r3, #114	; 0x72
- 8002134:	683b      	ldr	r3, [r7, #0]
- 8002136:	659a      	str	r2, [r3, #88]	; 0x58
-
-  macconf->ReceiveQueueMode = READ_BIT(heth->Instance->MTLRQOMR, (ETH_MTLRQOMR_RTC | ETH_MTLRQOMR_RSF));
- 8002138:	687b      	ldr	r3, [r7, #4]
- 800213a:	681b      	ldr	r3, [r3, #0]
- 800213c:	f8d3 3d30 	ldr.w	r3, [r3, #3376]	; 0xd30
- 8002140:	f003 0223 	and.w	r2, r3, #35	; 0x23
- 8002144:	683b      	ldr	r3, [r7, #0]
- 8002146:	65da      	str	r2, [r3, #92]	; 0x5c
-  macconf->ForwardRxUndersizedGoodPacket = ((READ_BIT(heth->Instance->MTLRQOMR,
- 8002148:	687b      	ldr	r3, [r7, #4]
- 800214a:	681b      	ldr	r3, [r3, #0]
- 800214c:	f8d3 3d30 	ldr.w	r3, [r3, #3376]	; 0xd30
-                                                      ETH_MTLRQOMR_FUP) >> 3) > 0U) ? ENABLE : DISABLE;
- 8002150:	f003 0308 	and.w	r3, r3, #8
- 8002154:	2b00      	cmp	r3, #0
- 8002156:	bf14      	ite	ne
- 8002158:	2301      	movne	r3, #1
- 800215a:	2300      	moveq	r3, #0
- 800215c:	b2db      	uxtb	r3, r3
- 800215e:	461a      	mov	r2, r3
-  macconf->ForwardRxUndersizedGoodPacket = ((READ_BIT(heth->Instance->MTLRQOMR,
- 8002160:	683b      	ldr	r3, [r7, #0]
- 8002162:	f883 2062 	strb.w	r2, [r3, #98]	; 0x62
-  macconf->ForwardRxErrorPacket = ((READ_BIT(heth->Instance->MTLRQOMR, ETH_MTLRQOMR_FEP) >> 4) > 0U) ? ENABLE : DISABLE;
- 8002166:	687b      	ldr	r3, [r7, #4]
- 8002168:	681b      	ldr	r3, [r3, #0]
- 800216a:	f8d3 3d30 	ldr.w	r3, [r3, #3376]	; 0xd30
- 800216e:	f003 0310 	and.w	r3, r3, #16
- 8002172:	2b00      	cmp	r3, #0
- 8002174:	bf14      	ite	ne
- 8002176:	2301      	movne	r3, #1
- 8002178:	2300      	moveq	r3, #0
- 800217a:	b2db      	uxtb	r3, r3
- 800217c:	461a      	mov	r2, r3
- 800217e:	683b      	ldr	r3, [r7, #0]
- 8002180:	f883 2061 	strb.w	r2, [r3, #97]	; 0x61
-  macconf->DropTCPIPChecksumErrorPacket = ((READ_BIT(heth->Instance->MTLRQOMR,
- 8002184:	687b      	ldr	r3, [r7, #4]
- 8002186:	681b      	ldr	r3, [r3, #0]
- 8002188:	f8d3 3d30 	ldr.w	r3, [r3, #3376]	; 0xd30
-                                                     ETH_MTLRQOMR_DISTCPEF) >> 6) == 0U) ? ENABLE : DISABLE;
- 800218c:	f003 0340 	and.w	r3, r3, #64	; 0x40
- 8002190:	2b00      	cmp	r3, #0
- 8002192:	bf0c      	ite	eq
- 8002194:	2301      	moveq	r3, #1
- 8002196:	2300      	movne	r3, #0
- 8002198:	b2db      	uxtb	r3, r3
- 800219a:	461a      	mov	r2, r3
-  macconf->DropTCPIPChecksumErrorPacket = ((READ_BIT(heth->Instance->MTLRQOMR,
- 800219c:	683b      	ldr	r3, [r7, #0]
- 800219e:	f883 2060 	strb.w	r2, [r3, #96]	; 0x60
-
-  return HAL_OK;
- 80021a2:	2300      	movs	r3, #0
-}
- 80021a4:	4618      	mov	r0, r3
- 80021a6:	370c      	adds	r7, #12
- 80021a8:	46bd      	mov	sp, r7
- 80021aa:	f85d 7b04 	ldr.w	r7, [sp], #4
- 80021ae:	4770      	bx	lr
-
-080021b0 <HAL_ETH_SetMACConfig>:
-  * @param  macconf: pointer to a ETH_MACConfigTypeDef structure that contains
-  *         the configuration of the MAC.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_ETH_SetMACConfig(ETH_HandleTypeDef *heth,  ETH_MACConfigTypeDef *macconf)
-{
- 80021b0:	b580      	push	{r7, lr}
- 80021b2:	b082      	sub	sp, #8
- 80021b4:	af00      	add	r7, sp, #0
- 80021b6:	6078      	str	r0, [r7, #4]
- 80021b8:	6039      	str	r1, [r7, #0]
-  if (macconf == NULL)
- 80021ba:	683b      	ldr	r3, [r7, #0]
- 80021bc:	2b00      	cmp	r3, #0
- 80021be:	d101      	bne.n	80021c4 <HAL_ETH_SetMACConfig+0x14>
-  {
-    return HAL_ERROR;
- 80021c0:	2301      	movs	r3, #1
- 80021c2:	e00b      	b.n	80021dc <HAL_ETH_SetMACConfig+0x2c>
-  }
-
-  if (heth->gState == HAL_ETH_STATE_READY)
- 80021c4:	687b      	ldr	r3, [r7, #4]
- 80021c6:	f8d3 3084 	ldr.w	r3, [r3, #132]	; 0x84
- 80021ca:	2b10      	cmp	r3, #16
- 80021cc:	d105      	bne.n	80021da <HAL_ETH_SetMACConfig+0x2a>
-  {
-    ETH_SetMACConfig(heth, macconf);
- 80021ce:	6839      	ldr	r1, [r7, #0]
- 80021d0:	6878      	ldr	r0, [r7, #4]
- 80021d2:	f000 f85f 	bl	8002294 <ETH_SetMACConfig>
-
-    return HAL_OK;
- 80021d6:	2300      	movs	r3, #0
- 80021d8:	e000      	b.n	80021dc <HAL_ETH_SetMACConfig+0x2c>
-  }
-  else
-  {
-    return HAL_ERROR;
- 80021da:	2301      	movs	r3, #1
-  }
-}
- 80021dc:	4618      	mov	r0, r3
- 80021de:	3708      	adds	r7, #8
- 80021e0:	46bd      	mov	sp, r7
- 80021e2:	bd80      	pop	{r7, pc}
-
-080021e4 <HAL_ETH_SetMDIOClockRange>:
-  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
-  *         the configuration information for ETHERNET module
-  * @retval None
-  */
-void HAL_ETH_SetMDIOClockRange(ETH_HandleTypeDef *heth)
-{
- 80021e4:	b580      	push	{r7, lr}
- 80021e6:	b084      	sub	sp, #16
- 80021e8:	af00      	add	r7, sp, #0
- 80021ea:	6078      	str	r0, [r7, #4]
-  uint32_t hclk;
-  uint32_t tmpreg;
-
-  /* Get the ETHERNET MACMDIOAR value */
-  tmpreg = (heth->Instance)->MACMDIOAR;
- 80021ec:	687b      	ldr	r3, [r7, #4]
- 80021ee:	681b      	ldr	r3, [r3, #0]
- 80021f0:	f8d3 3200 	ldr.w	r3, [r3, #512]	; 0x200
- 80021f4:	60fb      	str	r3, [r7, #12]
-
-  /* Clear CSR Clock Range bits */
-  tmpreg &= ~ETH_MACMDIOAR_CR;
- 80021f6:	68fb      	ldr	r3, [r7, #12]
- 80021f8:	f423 6370 	bic.w	r3, r3, #3840	; 0xf00
- 80021fc:	60fb      	str	r3, [r7, #12]
-
-  /* Get hclk frequency value */
-  hclk = HAL_RCC_GetHCLKFreq();
- 80021fe:	f001 fea9 	bl	8003f54 <HAL_RCC_GetHCLKFreq>
- 8002202:	60b8      	str	r0, [r7, #8]
-
-  /* Set CR bits depending on hclk value */
-  if ((hclk >= 20000000U) && (hclk < 35000000U))
- 8002204:	68bb      	ldr	r3, [r7, #8]
- 8002206:	4a1e      	ldr	r2, [pc, #120]	; (8002280 <HAL_ETH_SetMDIOClockRange+0x9c>)
- 8002208:	4293      	cmp	r3, r2
- 800220a:	d908      	bls.n	800221e <HAL_ETH_SetMDIOClockRange+0x3a>
- 800220c:	68bb      	ldr	r3, [r7, #8]
- 800220e:	4a1d      	ldr	r2, [pc, #116]	; (8002284 <HAL_ETH_SetMDIOClockRange+0xa0>)
- 8002210:	4293      	cmp	r3, r2
- 8002212:	d804      	bhi.n	800221e <HAL_ETH_SetMDIOClockRange+0x3a>
-  {
-    /* CSR Clock Range between 20-35 MHz */
-    tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV16;
- 8002214:	68fb      	ldr	r3, [r7, #12]
- 8002216:	f443 7300 	orr.w	r3, r3, #512	; 0x200
- 800221a:	60fb      	str	r3, [r7, #12]
- 800221c:	e027      	b.n	800226e <HAL_ETH_SetMDIOClockRange+0x8a>
-  }
-  else if ((hclk >= 35000000U) && (hclk < 60000000U))
- 800221e:	68bb      	ldr	r3, [r7, #8]
- 8002220:	4a18      	ldr	r2, [pc, #96]	; (8002284 <HAL_ETH_SetMDIOClockRange+0xa0>)
- 8002222:	4293      	cmp	r3, r2
- 8002224:	d908      	bls.n	8002238 <HAL_ETH_SetMDIOClockRange+0x54>
- 8002226:	68bb      	ldr	r3, [r7, #8]
- 8002228:	4a17      	ldr	r2, [pc, #92]	; (8002288 <HAL_ETH_SetMDIOClockRange+0xa4>)
- 800222a:	4293      	cmp	r3, r2
- 800222c:	d204      	bcs.n	8002238 <HAL_ETH_SetMDIOClockRange+0x54>
-  {
-    /* CSR Clock Range between 35-60 MHz */
-    tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV26;
- 800222e:	68fb      	ldr	r3, [r7, #12]
- 8002230:	f443 7340 	orr.w	r3, r3, #768	; 0x300
- 8002234:	60fb      	str	r3, [r7, #12]
- 8002236:	e01a      	b.n	800226e <HAL_ETH_SetMDIOClockRange+0x8a>
-  }
-  else if ((hclk >= 60000000U) && (hclk < 100000000U))
- 8002238:	68bb      	ldr	r3, [r7, #8]
- 800223a:	4a13      	ldr	r2, [pc, #76]	; (8002288 <HAL_ETH_SetMDIOClockRange+0xa4>)
- 800223c:	4293      	cmp	r3, r2
- 800223e:	d303      	bcc.n	8002248 <HAL_ETH_SetMDIOClockRange+0x64>
- 8002240:	68bb      	ldr	r3, [r7, #8]
- 8002242:	4a12      	ldr	r2, [pc, #72]	; (800228c <HAL_ETH_SetMDIOClockRange+0xa8>)
- 8002244:	4293      	cmp	r3, r2
- 8002246:	d911      	bls.n	800226c <HAL_ETH_SetMDIOClockRange+0x88>
-  {
-    /* CSR Clock Range between 60-100 MHz */
-    tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV42;
-  }
-  else if ((hclk >= 100000000U) && (hclk < 150000000U))
- 8002248:	68bb      	ldr	r3, [r7, #8]
- 800224a:	4a10      	ldr	r2, [pc, #64]	; (800228c <HAL_ETH_SetMDIOClockRange+0xa8>)
- 800224c:	4293      	cmp	r3, r2
- 800224e:	d908      	bls.n	8002262 <HAL_ETH_SetMDIOClockRange+0x7e>
- 8002250:	68bb      	ldr	r3, [r7, #8]
- 8002252:	4a0f      	ldr	r2, [pc, #60]	; (8002290 <HAL_ETH_SetMDIOClockRange+0xac>)
- 8002254:	4293      	cmp	r3, r2
- 8002256:	d804      	bhi.n	8002262 <HAL_ETH_SetMDIOClockRange+0x7e>
-  {
-    /* CSR Clock Range between 100-150 MHz */
-    tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV62;
- 8002258:	68fb      	ldr	r3, [r7, #12]
- 800225a:	f443 7380 	orr.w	r3, r3, #256	; 0x100
- 800225e:	60fb      	str	r3, [r7, #12]
- 8002260:	e005      	b.n	800226e <HAL_ETH_SetMDIOClockRange+0x8a>
-  }
-  else /* (hclk >= 150000000)&&(hclk <= 200000000) */
-  {
-    /* CSR Clock Range between 150-200 MHz */
-    tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV102;
- 8002262:	68fb      	ldr	r3, [r7, #12]
- 8002264:	f443 6380 	orr.w	r3, r3, #1024	; 0x400
- 8002268:	60fb      	str	r3, [r7, #12]
- 800226a:	e000      	b.n	800226e <HAL_ETH_SetMDIOClockRange+0x8a>
-    tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV42;
- 800226c:	bf00      	nop
-  }
-
-  /* Configure the CSR Clock Range */
-  (heth->Instance)->MACMDIOAR = (uint32_t)tmpreg;
- 800226e:	687b      	ldr	r3, [r7, #4]
- 8002270:	681b      	ldr	r3, [r3, #0]
- 8002272:	68fa      	ldr	r2, [r7, #12]
- 8002274:	f8c3 2200 	str.w	r2, [r3, #512]	; 0x200
-}
- 8002278:	bf00      	nop
- 800227a:	3710      	adds	r7, #16
- 800227c:	46bd      	mov	sp, r7
- 800227e:	bd80      	pop	{r7, pc}
- 8002280:	01312cff 	.word	0x01312cff
- 8002284:	02160ebf 	.word	0x02160ebf
- 8002288:	03938700 	.word	0x03938700
- 800228c:	05f5e0ff 	.word	0x05f5e0ff
- 8002290:	08f0d17f 	.word	0x08f0d17f
-
-08002294 <ETH_SetMACConfig>:
-  * @{
-  */
-
-
-static void ETH_SetMACConfig(ETH_HandleTypeDef *heth,  ETH_MACConfigTypeDef *macconf)
-{
- 8002294:	b480      	push	{r7}
- 8002296:	b085      	sub	sp, #20
- 8002298:	af00      	add	r7, sp, #0
- 800229a:	6078      	str	r0, [r7, #4]
- 800229c:	6039      	str	r1, [r7, #0]
-  uint32_t macregval;
-
-  /*------------------------ MACCR Configuration --------------------*/
-  macregval = (macconf->InterPacketGapVal |
- 800229e:	683b      	ldr	r3, [r7, #0]
- 80022a0:	689a      	ldr	r2, [r3, #8]
-               macconf->SourceAddrControl |
- 80022a2:	683b      	ldr	r3, [r7, #0]
- 80022a4:	681b      	ldr	r3, [r3, #0]
-  macregval = (macconf->InterPacketGapVal |
- 80022a6:	431a      	orrs	r2, r3
-               ((uint32_t)macconf->ChecksumOffload << 27) |
- 80022a8:	683b      	ldr	r3, [r7, #0]
- 80022aa:	791b      	ldrb	r3, [r3, #4]
- 80022ac:	06db      	lsls	r3, r3, #27
-               macconf->SourceAddrControl |
- 80022ae:	431a      	orrs	r2, r3
-               ((uint32_t)macconf->GiantPacketSizeLimitControl << 23) |
- 80022b0:	683b      	ldr	r3, [r7, #0]
- 80022b2:	7b1b      	ldrb	r3, [r3, #12]
- 80022b4:	05db      	lsls	r3, r3, #23
-               ((uint32_t)macconf->ChecksumOffload << 27) |
- 80022b6:	431a      	orrs	r2, r3
-               ((uint32_t)macconf->Support2KPacket  << 22) |
- 80022b8:	683b      	ldr	r3, [r7, #0]
- 80022ba:	7b5b      	ldrb	r3, [r3, #13]
- 80022bc:	059b      	lsls	r3, r3, #22
-               ((uint32_t)macconf->GiantPacketSizeLimitControl << 23) |
- 80022be:	431a      	orrs	r2, r3
-               ((uint32_t)macconf->CRCStripTypePacket << 21) |
- 80022c0:	683b      	ldr	r3, [r7, #0]
- 80022c2:	7b9b      	ldrb	r3, [r3, #14]
- 80022c4:	055b      	lsls	r3, r3, #21
-               ((uint32_t)macconf->Support2KPacket  << 22) |
- 80022c6:	431a      	orrs	r2, r3
-               ((uint32_t)macconf->AutomaticPadCRCStrip << 20) |
- 80022c8:	683b      	ldr	r3, [r7, #0]
- 80022ca:	7bdb      	ldrb	r3, [r3, #15]
- 80022cc:	051b      	lsls	r3, r3, #20
-               ((uint32_t)macconf->CRCStripTypePacket << 21) |
- 80022ce:	4313      	orrs	r3, r2
-               ((uint32_t)((macconf->Watchdog == DISABLE) ? 1U : 0U) << 19) |
- 80022d0:	683a      	ldr	r2, [r7, #0]
- 80022d2:	7c12      	ldrb	r2, [r2, #16]
- 80022d4:	2a00      	cmp	r2, #0
- 80022d6:	d102      	bne.n	80022de <ETH_SetMACConfig+0x4a>
- 80022d8:	f44f 2200 	mov.w	r2, #524288	; 0x80000
- 80022dc:	e000      	b.n	80022e0 <ETH_SetMACConfig+0x4c>
- 80022de:	2200      	movs	r2, #0
-               ((uint32_t)macconf->AutomaticPadCRCStrip << 20) |
- 80022e0:	4313      	orrs	r3, r2
-               ((uint32_t)((macconf->Jabber == DISABLE) ? 1U : 0U) << 17) |
- 80022e2:	683a      	ldr	r2, [r7, #0]
- 80022e4:	7c52      	ldrb	r2, [r2, #17]
- 80022e6:	2a00      	cmp	r2, #0
- 80022e8:	d102      	bne.n	80022f0 <ETH_SetMACConfig+0x5c>
- 80022ea:	f44f 3200 	mov.w	r2, #131072	; 0x20000
- 80022ee:	e000      	b.n	80022f2 <ETH_SetMACConfig+0x5e>
- 80022f0:	2200      	movs	r2, #0
-               ((uint32_t)((macconf->Watchdog == DISABLE) ? 1U : 0U) << 19) |
- 80022f2:	431a      	orrs	r2, r3
-               ((uint32_t)macconf->JumboPacket << 16) |
- 80022f4:	683b      	ldr	r3, [r7, #0]
- 80022f6:	7c9b      	ldrb	r3, [r3, #18]
- 80022f8:	041b      	lsls	r3, r3, #16
-               ((uint32_t)((macconf->Jabber == DISABLE) ? 1U : 0U) << 17) |
- 80022fa:	431a      	orrs	r2, r3
-               macconf->Speed |
- 80022fc:	683b      	ldr	r3, [r7, #0]
- 80022fe:	695b      	ldr	r3, [r3, #20]
-               ((uint32_t)macconf->JumboPacket << 16) |
- 8002300:	431a      	orrs	r2, r3
-               macconf->DuplexMode |
- 8002302:	683b      	ldr	r3, [r7, #0]
- 8002304:	699b      	ldr	r3, [r3, #24]
-               macconf->Speed |
- 8002306:	431a      	orrs	r2, r3
-               ((uint32_t)macconf->LoopbackMode << 12) |
- 8002308:	683b      	ldr	r3, [r7, #0]
- 800230a:	7f1b      	ldrb	r3, [r3, #28]
- 800230c:	031b      	lsls	r3, r3, #12
-               macconf->DuplexMode |
- 800230e:	431a      	orrs	r2, r3
-               ((uint32_t)macconf->CarrierSenseBeforeTransmit << 11) |
- 8002310:	683b      	ldr	r3, [r7, #0]
- 8002312:	7f5b      	ldrb	r3, [r3, #29]
- 8002314:	02db      	lsls	r3, r3, #11
-               ((uint32_t)macconf->LoopbackMode << 12) |
- 8002316:	4313      	orrs	r3, r2
-               ((uint32_t)((macconf->ReceiveOwn == DISABLE) ? 1U : 0U) << 10) |
- 8002318:	683a      	ldr	r2, [r7, #0]
- 800231a:	7f92      	ldrb	r2, [r2, #30]
- 800231c:	2a00      	cmp	r2, #0
- 800231e:	d102      	bne.n	8002326 <ETH_SetMACConfig+0x92>
- 8002320:	f44f 6280 	mov.w	r2, #1024	; 0x400
- 8002324:	e000      	b.n	8002328 <ETH_SetMACConfig+0x94>
- 8002326:	2200      	movs	r2, #0
-               ((uint32_t)macconf->CarrierSenseBeforeTransmit << 11) |
- 8002328:	431a      	orrs	r2, r3
-               ((uint32_t)macconf->CarrierSenseDuringTransmit << 9) |
- 800232a:	683b      	ldr	r3, [r7, #0]
- 800232c:	7fdb      	ldrb	r3, [r3, #31]
- 800232e:	025b      	lsls	r3, r3, #9
-               ((uint32_t)((macconf->ReceiveOwn == DISABLE) ? 1U : 0U) << 10) |
- 8002330:	4313      	orrs	r3, r2
-               ((uint32_t)((macconf->RetryTransmission == DISABLE) ? 1U : 0U) << 8) |
- 8002332:	683a      	ldr	r2, [r7, #0]
- 8002334:	f892 2020 	ldrb.w	r2, [r2, #32]
- 8002338:	2a00      	cmp	r2, #0
- 800233a:	d102      	bne.n	8002342 <ETH_SetMACConfig+0xae>
- 800233c:	f44f 7280 	mov.w	r2, #256	; 0x100
- 8002340:	e000      	b.n	8002344 <ETH_SetMACConfig+0xb0>
- 8002342:	2200      	movs	r2, #0
-               ((uint32_t)macconf->CarrierSenseDuringTransmit << 9) |
- 8002344:	431a      	orrs	r2, r3
-               macconf->BackOffLimit |
- 8002346:	683b      	ldr	r3, [r7, #0]
- 8002348:	6a5b      	ldr	r3, [r3, #36]	; 0x24
-               ((uint32_t)((macconf->RetryTransmission == DISABLE) ? 1U : 0U) << 8) |
- 800234a:	431a      	orrs	r2, r3
-               ((uint32_t)macconf->DeferralCheck << 4) |
- 800234c:	683b      	ldr	r3, [r7, #0]
- 800234e:	f893 3028 	ldrb.w	r3, [r3, #40]	; 0x28
- 8002352:	011b      	lsls	r3, r3, #4
-               macconf->BackOffLimit |
- 8002354:	431a      	orrs	r2, r3
-               macconf->PreambleLength);
- 8002356:	683b      	ldr	r3, [r7, #0]
- 8002358:	6adb      	ldr	r3, [r3, #44]	; 0x2c
-  macregval = (macconf->InterPacketGapVal |
- 800235a:	4313      	orrs	r3, r2
- 800235c:	60fb      	str	r3, [r7, #12]
-
-  /* Write to MACCR */
-  MODIFY_REG(heth->Instance->MACCR, ETH_MACCR_MASK, macregval);
- 800235e:	687b      	ldr	r3, [r7, #4]
- 8002360:	681b      	ldr	r3, [r3, #0]
- 8002362:	681a      	ldr	r2, [r3, #0]
- 8002364:	4b56      	ldr	r3, [pc, #344]	; (80024c0 <ETH_SetMACConfig+0x22c>)
- 8002366:	4013      	ands	r3, r2
- 8002368:	687a      	ldr	r2, [r7, #4]
- 800236a:	6812      	ldr	r2, [r2, #0]
- 800236c:	68f9      	ldr	r1, [r7, #12]
- 800236e:	430b      	orrs	r3, r1
- 8002370:	6013      	str	r3, [r2, #0]
-
-  /*------------------------ MACECR Configuration --------------------*/
-  macregval = ((macconf->ExtendedInterPacketGapVal << 25) |
- 8002372:	683b      	ldr	r3, [r7, #0]
- 8002374:	6bdb      	ldr	r3, [r3, #60]	; 0x3c
- 8002376:	065a      	lsls	r2, r3, #25
-               ((uint32_t)macconf->ExtendedInterPacketGap << 24) |
- 8002378:	683b      	ldr	r3, [r7, #0]
- 800237a:	f893 3038 	ldrb.w	r3, [r3, #56]	; 0x38
- 800237e:	061b      	lsls	r3, r3, #24
-  macregval = ((macconf->ExtendedInterPacketGapVal << 25) |
- 8002380:	431a      	orrs	r2, r3
-               ((uint32_t)macconf->UnicastSlowProtocolPacketDetect << 18) |
- 8002382:	683b      	ldr	r3, [r7, #0]
- 8002384:	f893 3030 	ldrb.w	r3, [r3, #48]	; 0x30
- 8002388:	049b      	lsls	r3, r3, #18
-               ((uint32_t)macconf->ExtendedInterPacketGap << 24) |
- 800238a:	431a      	orrs	r2, r3
-               ((uint32_t)macconf->SlowProtocolDetect << 17) |
- 800238c:	683b      	ldr	r3, [r7, #0]
- 800238e:	f893 3031 	ldrb.w	r3, [r3, #49]	; 0x31
- 8002392:	045b      	lsls	r3, r3, #17
-               ((uint32_t)macconf->UnicastSlowProtocolPacketDetect << 18) |
- 8002394:	4313      	orrs	r3, r2
-               ((uint32_t)((macconf->CRCCheckingRxPackets == DISABLE) ? 1U : 0U) << 16) |
- 8002396:	683a      	ldr	r2, [r7, #0]
- 8002398:	f892 2032 	ldrb.w	r2, [r2, #50]	; 0x32
- 800239c:	2a00      	cmp	r2, #0
- 800239e:	d102      	bne.n	80023a6 <ETH_SetMACConfig+0x112>
- 80023a0:	f44f 3280 	mov.w	r2, #65536	; 0x10000
- 80023a4:	e000      	b.n	80023a8 <ETH_SetMACConfig+0x114>
- 80023a6:	2200      	movs	r2, #0
-               ((uint32_t)macconf->SlowProtocolDetect << 17) |
- 80023a8:	431a      	orrs	r2, r3
-               macconf->GiantPacketSizeLimit);
- 80023aa:	683b      	ldr	r3, [r7, #0]
- 80023ac:	6b5b      	ldr	r3, [r3, #52]	; 0x34
-  macregval = ((macconf->ExtendedInterPacketGapVal << 25) |
- 80023ae:	4313      	orrs	r3, r2
- 80023b0:	60fb      	str	r3, [r7, #12]
-
-  /* Write to MACECR */
-  MODIFY_REG(heth->Instance->MACECR, ETH_MACECR_MASK, macregval);
- 80023b2:	687b      	ldr	r3, [r7, #4]
- 80023b4:	681b      	ldr	r3, [r3, #0]
- 80023b6:	685a      	ldr	r2, [r3, #4]
- 80023b8:	4b42      	ldr	r3, [pc, #264]	; (80024c4 <ETH_SetMACConfig+0x230>)
- 80023ba:	4013      	ands	r3, r2
- 80023bc:	687a      	ldr	r2, [r7, #4]
- 80023be:	6812      	ldr	r2, [r2, #0]
- 80023c0:	68f9      	ldr	r1, [r7, #12]
- 80023c2:	430b      	orrs	r3, r1
- 80023c4:	6053      	str	r3, [r2, #4]
-
-  /*------------------------ MACWTR Configuration --------------------*/
-  macregval = (((uint32_t)macconf->ProgrammableWatchdog << 8) |
- 80023c6:	683b      	ldr	r3, [r7, #0]
- 80023c8:	f893 3040 	ldrb.w	r3, [r3, #64]	; 0x40
- 80023cc:	021a      	lsls	r2, r3, #8
-               macconf->WatchdogTimeout);
- 80023ce:	683b      	ldr	r3, [r7, #0]
- 80023d0:	6c5b      	ldr	r3, [r3, #68]	; 0x44
-  macregval = (((uint32_t)macconf->ProgrammableWatchdog << 8) |
- 80023d2:	4313      	orrs	r3, r2
- 80023d4:	60fb      	str	r3, [r7, #12]
-
-  /* Write to MACWTR */
-  MODIFY_REG(heth->Instance->MACWTR, ETH_MACWTR_MASK, macregval);
- 80023d6:	687b      	ldr	r3, [r7, #4]
- 80023d8:	681b      	ldr	r3, [r3, #0]
- 80023da:	68da      	ldr	r2, [r3, #12]
- 80023dc:	4b3a      	ldr	r3, [pc, #232]	; (80024c8 <ETH_SetMACConfig+0x234>)
- 80023de:	4013      	ands	r3, r2
- 80023e0:	687a      	ldr	r2, [r7, #4]
- 80023e2:	6812      	ldr	r2, [r2, #0]
- 80023e4:	68f9      	ldr	r1, [r7, #12]
- 80023e6:	430b      	orrs	r3, r1
- 80023e8:	60d3      	str	r3, [r2, #12]
-
-  /*------------------------ MACTFCR Configuration --------------------*/
-  macregval = (((uint32_t)macconf->TransmitFlowControl << 1) |
- 80023ea:	683b      	ldr	r3, [r7, #0]
- 80023ec:	f893 3054 	ldrb.w	r3, [r3, #84]	; 0x54
- 80023f0:	005a      	lsls	r2, r3, #1
-               macconf->PauseLowThreshold |
- 80023f2:	683b      	ldr	r3, [r7, #0]
- 80023f4:	6d1b      	ldr	r3, [r3, #80]	; 0x50
-  macregval = (((uint32_t)macconf->TransmitFlowControl << 1) |
- 80023f6:	4313      	orrs	r3, r2
-               ((uint32_t)((macconf->ZeroQuantaPause == DISABLE) ? 1U : 0U) << 7) |
- 80023f8:	683a      	ldr	r2, [r7, #0]
- 80023fa:	f892 204c 	ldrb.w	r2, [r2, #76]	; 0x4c
- 80023fe:	2a00      	cmp	r2, #0
- 8002400:	d101      	bne.n	8002406 <ETH_SetMACConfig+0x172>
- 8002402:	2280      	movs	r2, #128	; 0x80
- 8002404:	e000      	b.n	8002408 <ETH_SetMACConfig+0x174>
- 8002406:	2200      	movs	r2, #0
-               macconf->PauseLowThreshold |
- 8002408:	431a      	orrs	r2, r3
-               (macconf->PauseTime << 16));
- 800240a:	683b      	ldr	r3, [r7, #0]
- 800240c:	6c9b      	ldr	r3, [r3, #72]	; 0x48
- 800240e:	041b      	lsls	r3, r3, #16
-  macregval = (((uint32_t)macconf->TransmitFlowControl << 1) |
- 8002410:	4313      	orrs	r3, r2
- 8002412:	60fb      	str	r3, [r7, #12]
-
-  /* Write to MACTFCR */
-  MODIFY_REG(heth->Instance->MACTFCR, ETH_MACTFCR_MASK, macregval);
- 8002414:	687b      	ldr	r3, [r7, #4]
- 8002416:	681b      	ldr	r3, [r3, #0]
- 8002418:	6f1a      	ldr	r2, [r3, #112]	; 0x70
- 800241a:	f64f 730d 	movw	r3, #65293	; 0xff0d
- 800241e:	4013      	ands	r3, r2
- 8002420:	687a      	ldr	r2, [r7, #4]
- 8002422:	6812      	ldr	r2, [r2, #0]
- 8002424:	68f9      	ldr	r1, [r7, #12]
- 8002426:	430b      	orrs	r3, r1
- 8002428:	6713      	str	r3, [r2, #112]	; 0x70
-
-  /*------------------------ MACRFCR Configuration --------------------*/
-  macregval = ((uint32_t)macconf->ReceiveFlowControl |
- 800242a:	683b      	ldr	r3, [r7, #0]
- 800242c:	f893 3056 	ldrb.w	r3, [r3, #86]	; 0x56
- 8002430:	461a      	mov	r2, r3
-               ((uint32_t)macconf->UnicastPausePacketDetect << 1));
- 8002432:	683b      	ldr	r3, [r7, #0]
- 8002434:	f893 3055 	ldrb.w	r3, [r3, #85]	; 0x55
- 8002438:	005b      	lsls	r3, r3, #1
-  macregval = ((uint32_t)macconf->ReceiveFlowControl |
- 800243a:	4313      	orrs	r3, r2
- 800243c:	60fb      	str	r3, [r7, #12]
-
-  /* Write to MACRFCR */
-  MODIFY_REG(heth->Instance->MACRFCR, ETH_MACRFCR_MASK, macregval);
- 800243e:	687b      	ldr	r3, [r7, #4]
- 8002440:	681b      	ldr	r3, [r3, #0]
- 8002442:	f8d3 3090 	ldr.w	r3, [r3, #144]	; 0x90
- 8002446:	f023 0103 	bic.w	r1, r3, #3
- 800244a:	687b      	ldr	r3, [r7, #4]
- 800244c:	681b      	ldr	r3, [r3, #0]
- 800244e:	68fa      	ldr	r2, [r7, #12]
- 8002450:	430a      	orrs	r2, r1
- 8002452:	f8c3 2090 	str.w	r2, [r3, #144]	; 0x90
-
-  /*------------------------ MTLTQOMR Configuration --------------------*/
-  /* Write to MTLTQOMR */
-  MODIFY_REG(heth->Instance->MTLTQOMR, ETH_MTLTQOMR_MASK, macconf->TransmitQueueMode);
- 8002456:	687b      	ldr	r3, [r7, #4]
- 8002458:	681b      	ldr	r3, [r3, #0]
- 800245a:	f8d3 3d00 	ldr.w	r3, [r3, #3328]	; 0xd00
- 800245e:	f023 0172 	bic.w	r1, r3, #114	; 0x72
- 8002462:	683b      	ldr	r3, [r7, #0]
- 8002464:	6d9a      	ldr	r2, [r3, #88]	; 0x58
- 8002466:	687b      	ldr	r3, [r7, #4]
- 8002468:	681b      	ldr	r3, [r3, #0]
- 800246a:	430a      	orrs	r2, r1
- 800246c:	f8c3 2d00 	str.w	r2, [r3, #3328]	; 0xd00
-
-  /*------------------------ MTLRQOMR Configuration --------------------*/
-  macregval = (macconf->ReceiveQueueMode |
- 8002470:	683b      	ldr	r3, [r7, #0]
- 8002472:	6ddb      	ldr	r3, [r3, #92]	; 0x5c
-               ((uint32_t)((macconf->DropTCPIPChecksumErrorPacket == DISABLE) ? 1U : 0U) << 6) |
- 8002474:	683a      	ldr	r2, [r7, #0]
- 8002476:	f892 2060 	ldrb.w	r2, [r2, #96]	; 0x60
- 800247a:	2a00      	cmp	r2, #0
- 800247c:	d101      	bne.n	8002482 <ETH_SetMACConfig+0x1ee>
- 800247e:	2240      	movs	r2, #64	; 0x40
- 8002480:	e000      	b.n	8002484 <ETH_SetMACConfig+0x1f0>
- 8002482:	2200      	movs	r2, #0
-  macregval = (macconf->ReceiveQueueMode |
- 8002484:	431a      	orrs	r2, r3
-               ((uint32_t)macconf->ForwardRxErrorPacket << 4) |
- 8002486:	683b      	ldr	r3, [r7, #0]
- 8002488:	f893 3061 	ldrb.w	r3, [r3, #97]	; 0x61
- 800248c:	011b      	lsls	r3, r3, #4
-               ((uint32_t)((macconf->DropTCPIPChecksumErrorPacket == DISABLE) ? 1U : 0U) << 6) |
- 800248e:	431a      	orrs	r2, r3
-               ((uint32_t)macconf->ForwardRxUndersizedGoodPacket << 3));
- 8002490:	683b      	ldr	r3, [r7, #0]
- 8002492:	f893 3062 	ldrb.w	r3, [r3, #98]	; 0x62
- 8002496:	00db      	lsls	r3, r3, #3
-  macregval = (macconf->ReceiveQueueMode |
- 8002498:	4313      	orrs	r3, r2
- 800249a:	60fb      	str	r3, [r7, #12]
-
-  /* Write to MTLRQOMR */
-  MODIFY_REG(heth->Instance->MTLRQOMR, ETH_MTLRQOMR_MASK, macregval);
- 800249c:	687b      	ldr	r3, [r7, #4]
- 800249e:	681b      	ldr	r3, [r3, #0]
- 80024a0:	f8d3 3d30 	ldr.w	r3, [r3, #3376]	; 0xd30
- 80024a4:	f023 017b 	bic.w	r1, r3, #123	; 0x7b
- 80024a8:	687b      	ldr	r3, [r7, #4]
- 80024aa:	681b      	ldr	r3, [r3, #0]
- 80024ac:	68fa      	ldr	r2, [r7, #12]
- 80024ae:	430a      	orrs	r2, r1
- 80024b0:	f8c3 2d30 	str.w	r2, [r3, #3376]	; 0xd30
-}
- 80024b4:	bf00      	nop
- 80024b6:	3714      	adds	r7, #20
- 80024b8:	46bd      	mov	sp, r7
- 80024ba:	f85d 7b04 	ldr.w	r7, [sp], #4
- 80024be:	4770      	bx	lr
- 80024c0:	00048083 	.word	0x00048083
- 80024c4:	c0f88000 	.word	0xc0f88000
- 80024c8:	fffffef0 	.word	0xfffffef0
-
-080024cc <ETH_SetDMAConfig>:
-
-static void ETH_SetDMAConfig(ETH_HandleTypeDef *heth,  ETH_DMAConfigTypeDef *dmaconf)
-{
- 80024cc:	b480      	push	{r7}
- 80024ce:	b085      	sub	sp, #20
- 80024d0:	af00      	add	r7, sp, #0
- 80024d2:	6078      	str	r0, [r7, #4]
- 80024d4:	6039      	str	r1, [r7, #0]
-  uint32_t dmaregval;
-
-  /*------------------------ DMAMR Configuration --------------------*/
-  MODIFY_REG(heth->Instance->DMAMR, ETH_DMAMR_MASK, dmaconf->DMAArbitration);
- 80024d6:	687b      	ldr	r3, [r7, #4]
- 80024d8:	681b      	ldr	r3, [r3, #0]
- 80024da:	f503 5380 	add.w	r3, r3, #4096	; 0x1000
- 80024de:	681a      	ldr	r2, [r3, #0]
- 80024e0:	4b38      	ldr	r3, [pc, #224]	; (80025c4 <ETH_SetDMAConfig+0xf8>)
- 80024e2:	4013      	ands	r3, r2
- 80024e4:	683a      	ldr	r2, [r7, #0]
- 80024e6:	6811      	ldr	r1, [r2, #0]
- 80024e8:	687a      	ldr	r2, [r7, #4]
- 80024ea:	6812      	ldr	r2, [r2, #0]
- 80024ec:	430b      	orrs	r3, r1
- 80024ee:	f502 5280 	add.w	r2, r2, #4096	; 0x1000
- 80024f2:	6013      	str	r3, [r2, #0]
-
-  /*------------------------ DMASBMR Configuration --------------------*/
-  dmaregval = (((uint32_t)dmaconf->AddressAlignedBeats << 12) |
- 80024f4:	683b      	ldr	r3, [r7, #0]
- 80024f6:	791b      	ldrb	r3, [r3, #4]
- 80024f8:	031a      	lsls	r2, r3, #12
-               dmaconf->BurstMode |
- 80024fa:	683b      	ldr	r3, [r7, #0]
- 80024fc:	689b      	ldr	r3, [r3, #8]
-  dmaregval = (((uint32_t)dmaconf->AddressAlignedBeats << 12) |
- 80024fe:	431a      	orrs	r2, r3
-               ((uint32_t)dmaconf->RebuildINCRxBurst << 15));
- 8002500:	683b      	ldr	r3, [r7, #0]
- 8002502:	7b1b      	ldrb	r3, [r3, #12]
- 8002504:	03db      	lsls	r3, r3, #15
-  dmaregval = (((uint32_t)dmaconf->AddressAlignedBeats << 12) |
- 8002506:	4313      	orrs	r3, r2
- 8002508:	60fb      	str	r3, [r7, #12]
-
-  MODIFY_REG(heth->Instance->DMASBMR, ETH_DMASBMR_MASK, dmaregval);
- 800250a:	687b      	ldr	r3, [r7, #4]
- 800250c:	681b      	ldr	r3, [r3, #0]
- 800250e:	f503 5380 	add.w	r3, r3, #4096	; 0x1000
- 8002512:	685a      	ldr	r2, [r3, #4]
- 8002514:	4b2c      	ldr	r3, [pc, #176]	; (80025c8 <ETH_SetDMAConfig+0xfc>)
- 8002516:	4013      	ands	r3, r2
- 8002518:	687a      	ldr	r2, [r7, #4]
- 800251a:	6812      	ldr	r2, [r2, #0]
- 800251c:	68f9      	ldr	r1, [r7, #12]
- 800251e:	430b      	orrs	r3, r1
- 8002520:	f502 5280 	add.w	r2, r2, #4096	; 0x1000
- 8002524:	6053      	str	r3, [r2, #4]
-
-  /*------------------------ DMACCR Configuration --------------------*/
-  dmaregval = (((uint32_t)dmaconf->PBLx8Mode << 16) |
- 8002526:	683b      	ldr	r3, [r7, #0]
- 8002528:	7b5b      	ldrb	r3, [r3, #13]
- 800252a:	041a      	lsls	r2, r3, #16
-               dmaconf->MaximumSegmentSize);
- 800252c:	683b      	ldr	r3, [r7, #0]
- 800252e:	6a1b      	ldr	r3, [r3, #32]
-  dmaregval = (((uint32_t)dmaconf->PBLx8Mode << 16) |
- 8002530:	4313      	orrs	r3, r2
- 8002532:	60fb      	str	r3, [r7, #12]
-
-  MODIFY_REG(heth->Instance->DMACCR, ETH_DMACCR_MASK, dmaregval);
- 8002534:	687b      	ldr	r3, [r7, #4]
- 8002536:	681b      	ldr	r3, [r3, #0]
- 8002538:	f503 5380 	add.w	r3, r3, #4096	; 0x1000
- 800253c:	f8d3 2100 	ldr.w	r2, [r3, #256]	; 0x100
- 8002540:	4b22      	ldr	r3, [pc, #136]	; (80025cc <ETH_SetDMAConfig+0x100>)
- 8002542:	4013      	ands	r3, r2
- 8002544:	687a      	ldr	r2, [r7, #4]
- 8002546:	6812      	ldr	r2, [r2, #0]
- 8002548:	68f9      	ldr	r1, [r7, #12]
- 800254a:	430b      	orrs	r3, r1
- 800254c:	f502 5280 	add.w	r2, r2, #4096	; 0x1000
- 8002550:	f8c2 3100 	str.w	r3, [r2, #256]	; 0x100
-
-  /*------------------------ DMACTCR Configuration --------------------*/
-  dmaregval = (dmaconf->TxDMABurstLength |
- 8002554:	683b      	ldr	r3, [r7, #0]
- 8002556:	691a      	ldr	r2, [r3, #16]
-               ((uint32_t)dmaconf->SecondPacketOperate << 4) |
- 8002558:	683b      	ldr	r3, [r7, #0]
- 800255a:	7d1b      	ldrb	r3, [r3, #20]
- 800255c:	011b      	lsls	r3, r3, #4
-  dmaregval = (dmaconf->TxDMABurstLength |
- 800255e:	431a      	orrs	r2, r3
-               ((uint32_t)dmaconf->TCPSegmentation << 12));
- 8002560:	683b      	ldr	r3, [r7, #0]
- 8002562:	7f5b      	ldrb	r3, [r3, #29]
- 8002564:	031b      	lsls	r3, r3, #12
-  dmaregval = (dmaconf->TxDMABurstLength |
- 8002566:	4313      	orrs	r3, r2
- 8002568:	60fb      	str	r3, [r7, #12]
-
-  MODIFY_REG(heth->Instance->DMACTCR, ETH_DMACTCR_MASK, dmaregval);
- 800256a:	687b      	ldr	r3, [r7, #4]
- 800256c:	681b      	ldr	r3, [r3, #0]
- 800256e:	f503 5380 	add.w	r3, r3, #4096	; 0x1000
- 8002572:	f8d3 2104 	ldr.w	r2, [r3, #260]	; 0x104
- 8002576:	4b16      	ldr	r3, [pc, #88]	; (80025d0 <ETH_SetDMAConfig+0x104>)
- 8002578:	4013      	ands	r3, r2
- 800257a:	687a      	ldr	r2, [r7, #4]
- 800257c:	6812      	ldr	r2, [r2, #0]
- 800257e:	68f9      	ldr	r1, [r7, #12]
- 8002580:	430b      	orrs	r3, r1
- 8002582:	f502 5280 	add.w	r2, r2, #4096	; 0x1000
- 8002586:	f8c2 3104 	str.w	r3, [r2, #260]	; 0x104
-
-  /*------------------------ DMACRCR Configuration --------------------*/
-  dmaregval = (((uint32_t)dmaconf->FlushRxPacket  << 31) |
- 800258a:	683b      	ldr	r3, [r7, #0]
- 800258c:	7f1b      	ldrb	r3, [r3, #28]
- 800258e:	07da      	lsls	r2, r3, #31
-               dmaconf->RxDMABurstLength);
- 8002590:	683b      	ldr	r3, [r7, #0]
- 8002592:	699b      	ldr	r3, [r3, #24]
-  dmaregval = (((uint32_t)dmaconf->FlushRxPacket  << 31) |
- 8002594:	4313      	orrs	r3, r2
- 8002596:	60fb      	str	r3, [r7, #12]
-
-  /* Write to DMACRCR */
-  MODIFY_REG(heth->Instance->DMACRCR, ETH_DMACRCR_MASK, dmaregval);
- 8002598:	687b      	ldr	r3, [r7, #4]
- 800259a:	681b      	ldr	r3, [r3, #0]
- 800259c:	f503 5380 	add.w	r3, r3, #4096	; 0x1000
- 80025a0:	f8d3 2108 	ldr.w	r2, [r3, #264]	; 0x108
- 80025a4:	4b0b      	ldr	r3, [pc, #44]	; (80025d4 <ETH_SetDMAConfig+0x108>)
- 80025a6:	4013      	ands	r3, r2
- 80025a8:	687a      	ldr	r2, [r7, #4]
- 80025aa:	6812      	ldr	r2, [r2, #0]
- 80025ac:	68f9      	ldr	r1, [r7, #12]
- 80025ae:	430b      	orrs	r3, r1
- 80025b0:	f502 5280 	add.w	r2, r2, #4096	; 0x1000
- 80025b4:	f8c2 3108 	str.w	r3, [r2, #264]	; 0x108
-}
- 80025b8:	bf00      	nop
- 80025ba:	3714      	adds	r7, #20
- 80025bc:	46bd      	mov	sp, r7
- 80025be:	f85d 7b04 	ldr.w	r7, [sp], #4
- 80025c2:	4770      	bx	lr
- 80025c4:	ffff87fd 	.word	0xffff87fd
- 80025c8:	ffff2ffe 	.word	0xffff2ffe
- 80025cc:	fffec000 	.word	0xfffec000
- 80025d0:	ffc0efef 	.word	0xffc0efef
- 80025d4:	7fc0ffff 	.word	0x7fc0ffff
-
-080025d8 <ETH_MACDMAConfig>:
-  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
-  *         the configuration information for ETHERNET module
-  * @retval HAL status
-  */
-static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth)
-{
- 80025d8:	b580      	push	{r7, lr}
- 80025da:	b0a4      	sub	sp, #144	; 0x90
- 80025dc:	af00      	add	r7, sp, #0
- 80025de:	6078      	str	r0, [r7, #4]
-  ETH_MACConfigTypeDef macDefaultConf;
-  ETH_DMAConfigTypeDef dmaDefaultConf;
-
-  /*--------------- ETHERNET MAC registers default Configuration --------------*/
-  macDefaultConf.AutomaticPadCRCStrip = ENABLE;
- 80025e0:	2301      	movs	r3, #1
- 80025e2:	f887 303b 	strb.w	r3, [r7, #59]	; 0x3b
-  macDefaultConf.BackOffLimit = ETH_BACKOFFLIMIT_10;
- 80025e6:	2300      	movs	r3, #0
- 80025e8:	653b      	str	r3, [r7, #80]	; 0x50
-  macDefaultConf.CarrierSenseBeforeTransmit = DISABLE;
- 80025ea:	2300      	movs	r3, #0
- 80025ec:	f887 3049 	strb.w	r3, [r7, #73]	; 0x49
-  macDefaultConf.CarrierSenseDuringTransmit = DISABLE;
- 80025f0:	2300      	movs	r3, #0
- 80025f2:	f887 304b 	strb.w	r3, [r7, #75]	; 0x4b
-  macDefaultConf.ChecksumOffload = ENABLE;
- 80025f6:	2301      	movs	r3, #1
- 80025f8:	f887 3030 	strb.w	r3, [r7, #48]	; 0x30
-  macDefaultConf.CRCCheckingRxPackets = ENABLE;
- 80025fc:	2301      	movs	r3, #1
- 80025fe:	f887 305e 	strb.w	r3, [r7, #94]	; 0x5e
-  macDefaultConf.CRCStripTypePacket = ENABLE;
- 8002602:	2301      	movs	r3, #1
- 8002604:	f887 303a 	strb.w	r3, [r7, #58]	; 0x3a
-  macDefaultConf.DeferralCheck = DISABLE;
- 8002608:	2300      	movs	r3, #0
- 800260a:	f887 3054 	strb.w	r3, [r7, #84]	; 0x54
-  macDefaultConf.DropTCPIPChecksumErrorPacket = ENABLE;
- 800260e:	2301      	movs	r3, #1
- 8002610:	f887 308c 	strb.w	r3, [r7, #140]	; 0x8c
-  macDefaultConf.DuplexMode = ETH_FULLDUPLEX_MODE;
- 8002614:	f44f 5300 	mov.w	r3, #8192	; 0x2000
- 8002618:	647b      	str	r3, [r7, #68]	; 0x44
-  macDefaultConf.ExtendedInterPacketGap = DISABLE;
- 800261a:	2300      	movs	r3, #0
- 800261c:	f887 3064 	strb.w	r3, [r7, #100]	; 0x64
-  macDefaultConf.ExtendedInterPacketGapVal = 0x0;
- 8002620:	2300      	movs	r3, #0
- 8002622:	66bb      	str	r3, [r7, #104]	; 0x68
-  macDefaultConf.ForwardRxErrorPacket = DISABLE;
- 8002624:	2300      	movs	r3, #0
- 8002626:	f887 308d 	strb.w	r3, [r7, #141]	; 0x8d
-  macDefaultConf.ForwardRxUndersizedGoodPacket = DISABLE;
- 800262a:	2300      	movs	r3, #0
- 800262c:	f887 308e 	strb.w	r3, [r7, #142]	; 0x8e
-  macDefaultConf.GiantPacketSizeLimit = 0x618;
- 8002630:	f44f 63c3 	mov.w	r3, #1560	; 0x618
- 8002634:	663b      	str	r3, [r7, #96]	; 0x60
-  macDefaultConf.GiantPacketSizeLimitControl = DISABLE;
- 8002636:	2300      	movs	r3, #0
- 8002638:	f887 3038 	strb.w	r3, [r7, #56]	; 0x38
-  macDefaultConf.InterPacketGapVal = ETH_INTERPACKETGAP_96BIT;
- 800263c:	2300      	movs	r3, #0
- 800263e:	637b      	str	r3, [r7, #52]	; 0x34
-  macDefaultConf.Jabber = ENABLE;
- 8002640:	2301      	movs	r3, #1
- 8002642:	f887 303d 	strb.w	r3, [r7, #61]	; 0x3d
-  macDefaultConf.JumboPacket = DISABLE;
- 8002646:	2300      	movs	r3, #0
- 8002648:	f887 303e 	strb.w	r3, [r7, #62]	; 0x3e
-  macDefaultConf.LoopbackMode = DISABLE;
- 800264c:	2300      	movs	r3, #0
- 800264e:	f887 3048 	strb.w	r3, [r7, #72]	; 0x48
-  macDefaultConf.PauseLowThreshold = ETH_PAUSELOWTHRESHOLD_MINUS_4;
- 8002652:	2300      	movs	r3, #0
- 8002654:	67fb      	str	r3, [r7, #124]	; 0x7c
-  macDefaultConf.PauseTime = 0x0;
- 8002656:	2300      	movs	r3, #0
- 8002658:	677b      	str	r3, [r7, #116]	; 0x74
-  macDefaultConf.PreambleLength = ETH_PREAMBLELENGTH_7;
- 800265a:	2300      	movs	r3, #0
- 800265c:	65bb      	str	r3, [r7, #88]	; 0x58
-  macDefaultConf.ProgrammableWatchdog = DISABLE;
- 800265e:	2300      	movs	r3, #0
- 8002660:	f887 306c 	strb.w	r3, [r7, #108]	; 0x6c
-  macDefaultConf.ReceiveFlowControl = DISABLE;
- 8002664:	2300      	movs	r3, #0
- 8002666:	f887 3082 	strb.w	r3, [r7, #130]	; 0x82
-  macDefaultConf.ReceiveOwn = ENABLE;
- 800266a:	2301      	movs	r3, #1
- 800266c:	f887 304a 	strb.w	r3, [r7, #74]	; 0x4a
-  macDefaultConf.ReceiveQueueMode = ETH_RECEIVESTOREFORWARD;
- 8002670:	2320      	movs	r3, #32
- 8002672:	f8c7 3088 	str.w	r3, [r7, #136]	; 0x88
-  macDefaultConf.RetryTransmission = ENABLE;
- 8002676:	2301      	movs	r3, #1
- 8002678:	f887 304c 	strb.w	r3, [r7, #76]	; 0x4c
-  macDefaultConf.SlowProtocolDetect = DISABLE;
- 800267c:	2300      	movs	r3, #0
- 800267e:	f887 305d 	strb.w	r3, [r7, #93]	; 0x5d
-  macDefaultConf.SourceAddrControl = ETH_SOURCEADDRESS_REPLACE_ADDR0;
- 8002682:	f04f 5340 	mov.w	r3, #805306368	; 0x30000000
- 8002686:	62fb      	str	r3, [r7, #44]	; 0x2c
-  macDefaultConf.Speed = ETH_SPEED_100M;
- 8002688:	f44f 4380 	mov.w	r3, #16384	; 0x4000
- 800268c:	643b      	str	r3, [r7, #64]	; 0x40
-  macDefaultConf.Support2KPacket = DISABLE;
- 800268e:	2300      	movs	r3, #0
- 8002690:	f887 3039 	strb.w	r3, [r7, #57]	; 0x39
-  macDefaultConf.TransmitQueueMode = ETH_TRANSMITSTOREFORWARD;
- 8002694:	2302      	movs	r3, #2
- 8002696:	f8c7 3084 	str.w	r3, [r7, #132]	; 0x84
-  macDefaultConf.TransmitFlowControl = DISABLE;
- 800269a:	2300      	movs	r3, #0
- 800269c:	f887 3080 	strb.w	r3, [r7, #128]	; 0x80
-  macDefaultConf.UnicastPausePacketDetect = DISABLE;
- 80026a0:	2300      	movs	r3, #0
- 80026a2:	f887 3081 	strb.w	r3, [r7, #129]	; 0x81
-  macDefaultConf.UnicastSlowProtocolPacketDetect = DISABLE;
- 80026a6:	2300      	movs	r3, #0
- 80026a8:	f887 305c 	strb.w	r3, [r7, #92]	; 0x5c
-  macDefaultConf.Watchdog = ENABLE;
- 80026ac:	2301      	movs	r3, #1
- 80026ae:	f887 303c 	strb.w	r3, [r7, #60]	; 0x3c
-  macDefaultConf.WatchdogTimeout =  ETH_MACWTR_WTO_2KB;
- 80026b2:	2300      	movs	r3, #0
- 80026b4:	673b      	str	r3, [r7, #112]	; 0x70
-  macDefaultConf.ZeroQuantaPause = ENABLE;
- 80026b6:	2301      	movs	r3, #1
- 80026b8:	f887 3078 	strb.w	r3, [r7, #120]	; 0x78
-
-  /* MAC default configuration */
-  ETH_SetMACConfig(heth, &macDefaultConf);
- 80026bc:	f107 032c 	add.w	r3, r7, #44	; 0x2c
- 80026c0:	4619      	mov	r1, r3
- 80026c2:	6878      	ldr	r0, [r7, #4]
- 80026c4:	f7ff fde6 	bl	8002294 <ETH_SetMACConfig>
-
-  /*--------------- ETHERNET DMA registers default Configuration --------------*/
-  dmaDefaultConf.AddressAlignedBeats = ENABLE;
- 80026c8:	2301      	movs	r3, #1
- 80026ca:	733b      	strb	r3, [r7, #12]
-  dmaDefaultConf.BurstMode = ETH_BURSTLENGTH_FIXED;
- 80026cc:	2301      	movs	r3, #1
- 80026ce:	613b      	str	r3, [r7, #16]
-  dmaDefaultConf.DMAArbitration = ETH_DMAARBITRATION_RX1_TX1;
- 80026d0:	2300      	movs	r3, #0
- 80026d2:	60bb      	str	r3, [r7, #8]
-  dmaDefaultConf.FlushRxPacket = DISABLE;
- 80026d4:	2300      	movs	r3, #0
- 80026d6:	f887 3024 	strb.w	r3, [r7, #36]	; 0x24
-  dmaDefaultConf.PBLx8Mode = DISABLE;
- 80026da:	2300      	movs	r3, #0
- 80026dc:	757b      	strb	r3, [r7, #21]
-  dmaDefaultConf.RebuildINCRxBurst = DISABLE;
- 80026de:	2300      	movs	r3, #0
- 80026e0:	753b      	strb	r3, [r7, #20]
-  dmaDefaultConf.RxDMABurstLength = ETH_RXDMABURSTLENGTH_32BEAT;
- 80026e2:	f44f 1300 	mov.w	r3, #2097152	; 0x200000
- 80026e6:	623b      	str	r3, [r7, #32]
-  dmaDefaultConf.SecondPacketOperate = DISABLE;
- 80026e8:	2300      	movs	r3, #0
- 80026ea:	773b      	strb	r3, [r7, #28]
-  dmaDefaultConf.TxDMABurstLength = ETH_TXDMABURSTLENGTH_32BEAT;
- 80026ec:	f44f 1300 	mov.w	r3, #2097152	; 0x200000
- 80026f0:	61bb      	str	r3, [r7, #24]
-  dmaDefaultConf.TCPSegmentation = DISABLE;
- 80026f2:	2300      	movs	r3, #0
- 80026f4:	f887 3025 	strb.w	r3, [r7, #37]	; 0x25
-  dmaDefaultConf.MaximumSegmentSize = ETH_SEGMENT_SIZE_DEFAULT;
- 80026f8:	f44f 7306 	mov.w	r3, #536	; 0x218
- 80026fc:	62bb      	str	r3, [r7, #40]	; 0x28
-
-  /* DMA default configuration */
-  ETH_SetDMAConfig(heth, &dmaDefaultConf);
- 80026fe:	f107 0308 	add.w	r3, r7, #8
- 8002702:	4619      	mov	r1, r3
- 8002704:	6878      	ldr	r0, [r7, #4]
- 8002706:	f7ff fee1 	bl	80024cc <ETH_SetDMAConfig>
-}
- 800270a:	bf00      	nop
- 800270c:	3790      	adds	r7, #144	; 0x90
- 800270e:	46bd      	mov	sp, r7
- 8002710:	bd80      	pop	{r7, pc}
-
-08002712 <ETH_DMATxDescListInit>:
-  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
-  *         the configuration information for ETHERNET module
-  * @retval None
-  */
-static void ETH_DMATxDescListInit(ETH_HandleTypeDef *heth)
-{
- 8002712:	b480      	push	{r7}
- 8002714:	b085      	sub	sp, #20
- 8002716:	af00      	add	r7, sp, #0
- 8002718:	6078      	str	r0, [r7, #4]
-  ETH_DMADescTypeDef *dmatxdesc;
-  uint32_t i;
-
-  /* Fill each DMATxDesc descriptor with the right values */
-  for (i = 0; i < (uint32_t)ETH_TX_DESC_CNT; i++)
- 800271a:	2300      	movs	r3, #0
- 800271c:	60fb      	str	r3, [r7, #12]
- 800271e:	e01d      	b.n	800275c <ETH_DMATxDescListInit+0x4a>
-  {
-    dmatxdesc = heth->Init.TxDesc + i;
- 8002720:	687b      	ldr	r3, [r7, #4]
- 8002722:	68d9      	ldr	r1, [r3, #12]
- 8002724:	68fa      	ldr	r2, [r7, #12]
- 8002726:	4613      	mov	r3, r2
- 8002728:	005b      	lsls	r3, r3, #1
- 800272a:	4413      	add	r3, r2
- 800272c:	00db      	lsls	r3, r3, #3
- 800272e:	440b      	add	r3, r1
- 8002730:	60bb      	str	r3, [r7, #8]
-
-    WRITE_REG(dmatxdesc->DESC0, 0x0);
- 8002732:	68bb      	ldr	r3, [r7, #8]
- 8002734:	2200      	movs	r2, #0
- 8002736:	601a      	str	r2, [r3, #0]
-    WRITE_REG(dmatxdesc->DESC1, 0x0);
- 8002738:	68bb      	ldr	r3, [r7, #8]
- 800273a:	2200      	movs	r2, #0
- 800273c:	605a      	str	r2, [r3, #4]
-    WRITE_REG(dmatxdesc->DESC2, 0x0);
- 800273e:	68bb      	ldr	r3, [r7, #8]
- 8002740:	2200      	movs	r2, #0
- 8002742:	609a      	str	r2, [r3, #8]
-    WRITE_REG(dmatxdesc->DESC3, 0x0);
- 8002744:	68bb      	ldr	r3, [r7, #8]
- 8002746:	2200      	movs	r2, #0
- 8002748:	60da      	str	r2, [r3, #12]
-
-    WRITE_REG(heth->TxDescList.TxDesc[i], (uint32_t)dmatxdesc);
- 800274a:	68b9      	ldr	r1, [r7, #8]
- 800274c:	687b      	ldr	r3, [r7, #4]
- 800274e:	68fa      	ldr	r2, [r7, #12]
- 8002750:	3206      	adds	r2, #6
- 8002752:	f843 1022 	str.w	r1, [r3, r2, lsl #2]
-  for (i = 0; i < (uint32_t)ETH_TX_DESC_CNT; i++)
- 8002756:	68fb      	ldr	r3, [r7, #12]
- 8002758:	3301      	adds	r3, #1
- 800275a:	60fb      	str	r3, [r7, #12]
- 800275c:	68fb      	ldr	r3, [r7, #12]
- 800275e:	2b03      	cmp	r3, #3
- 8002760:	d9de      	bls.n	8002720 <ETH_DMATxDescListInit+0xe>
-
-  }
-
-  heth->TxDescList.CurTxDesc = 0;
- 8002762:	687b      	ldr	r3, [r7, #4]
- 8002764:	2200      	movs	r2, #0
- 8002766:	629a      	str	r2, [r3, #40]	; 0x28
-
-  /* Set Transmit Descriptor Ring Length */
-  WRITE_REG(heth->Instance->DMACTDRLR, (ETH_TX_DESC_CNT - 1U));
- 8002768:	687b      	ldr	r3, [r7, #4]
- 800276a:	681b      	ldr	r3, [r3, #0]
- 800276c:	f503 5380 	add.w	r3, r3, #4096	; 0x1000
- 8002770:	461a      	mov	r2, r3
- 8002772:	2303      	movs	r3, #3
- 8002774:	f8c2 312c 	str.w	r3, [r2, #300]	; 0x12c
-
-  /* Set Transmit Descriptor List Address */
-  WRITE_REG(heth->Instance->DMACTDLAR, (uint32_t) heth->Init.TxDesc);
- 8002778:	687b      	ldr	r3, [r7, #4]
- 800277a:	68da      	ldr	r2, [r3, #12]
- 800277c:	687b      	ldr	r3, [r7, #4]
- 800277e:	681b      	ldr	r3, [r3, #0]
- 8002780:	f503 5380 	add.w	r3, r3, #4096	; 0x1000
- 8002784:	f8c3 2114 	str.w	r2, [r3, #276]	; 0x114
-
-  /* Set Transmit Descriptor Tail pointer */
-  WRITE_REG(heth->Instance->DMACTDTPR, (uint32_t) heth->Init.TxDesc);
- 8002788:	687b      	ldr	r3, [r7, #4]
- 800278a:	68da      	ldr	r2, [r3, #12]
- 800278c:	687b      	ldr	r3, [r7, #4]
- 800278e:	681b      	ldr	r3, [r3, #0]
- 8002790:	f503 5380 	add.w	r3, r3, #4096	; 0x1000
- 8002794:	f8c3 2120 	str.w	r2, [r3, #288]	; 0x120
-}
- 8002798:	bf00      	nop
- 800279a:	3714      	adds	r7, #20
- 800279c:	46bd      	mov	sp, r7
- 800279e:	f85d 7b04 	ldr.w	r7, [sp], #4
- 80027a2:	4770      	bx	lr
-
-080027a4 <ETH_DMARxDescListInit>:
-  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
-  *         the configuration information for ETHERNET module
-  * @retval None
-  */
-static void ETH_DMARxDescListInit(ETH_HandleTypeDef *heth)
-{
- 80027a4:	b480      	push	{r7}
- 80027a6:	b085      	sub	sp, #20
- 80027a8:	af00      	add	r7, sp, #0
- 80027aa:	6078      	str	r0, [r7, #4]
-  ETH_DMADescTypeDef *dmarxdesc;
-  uint32_t i;
-
-  for (i = 0; i < (uint32_t)ETH_RX_DESC_CNT; i++)
- 80027ac:	2300      	movs	r3, #0
- 80027ae:	60fb      	str	r3, [r7, #12]
- 80027b0:	e023      	b.n	80027fa <ETH_DMARxDescListInit+0x56>
-  {
-    dmarxdesc =  heth->Init.RxDesc + i;
- 80027b2:	687b      	ldr	r3, [r7, #4]
- 80027b4:	6919      	ldr	r1, [r3, #16]
- 80027b6:	68fa      	ldr	r2, [r7, #12]
- 80027b8:	4613      	mov	r3, r2
- 80027ba:	005b      	lsls	r3, r3, #1
- 80027bc:	4413      	add	r3, r2
- 80027be:	00db      	lsls	r3, r3, #3
- 80027c0:	440b      	add	r3, r1
- 80027c2:	60bb      	str	r3, [r7, #8]
-
-    WRITE_REG(dmarxdesc->DESC0, 0x0);
- 80027c4:	68bb      	ldr	r3, [r7, #8]
- 80027c6:	2200      	movs	r2, #0
- 80027c8:	601a      	str	r2, [r3, #0]
-    WRITE_REG(dmarxdesc->DESC1, 0x0);
- 80027ca:	68bb      	ldr	r3, [r7, #8]
- 80027cc:	2200      	movs	r2, #0
- 80027ce:	605a      	str	r2, [r3, #4]
-    WRITE_REG(dmarxdesc->DESC2, 0x0);
- 80027d0:	68bb      	ldr	r3, [r7, #8]
- 80027d2:	2200      	movs	r2, #0
- 80027d4:	609a      	str	r2, [r3, #8]
-    WRITE_REG(dmarxdesc->DESC3, 0x0);
- 80027d6:	68bb      	ldr	r3, [r7, #8]
- 80027d8:	2200      	movs	r2, #0
- 80027da:	60da      	str	r2, [r3, #12]
-    WRITE_REG(dmarxdesc->BackupAddr0, 0x0);
- 80027dc:	68bb      	ldr	r3, [r7, #8]
- 80027de:	2200      	movs	r2, #0
- 80027e0:	611a      	str	r2, [r3, #16]
-    WRITE_REG(dmarxdesc->BackupAddr1, 0x0);
- 80027e2:	68bb      	ldr	r3, [r7, #8]
- 80027e4:	2200      	movs	r2, #0
- 80027e6:	615a      	str	r2, [r3, #20]
-
-
-    /* Set Rx descritors addresses */
-    WRITE_REG(heth->RxDescList.RxDesc[i], (uint32_t)dmarxdesc);
- 80027e8:	68b9      	ldr	r1, [r7, #8]
- 80027ea:	687b      	ldr	r3, [r7, #4]
- 80027ec:	68fa      	ldr	r2, [r7, #12]
- 80027ee:	3212      	adds	r2, #18
- 80027f0:	f843 1022 	str.w	r1, [r3, r2, lsl #2]
-  for (i = 0; i < (uint32_t)ETH_RX_DESC_CNT; i++)
- 80027f4:	68fb      	ldr	r3, [r7, #12]
- 80027f6:	3301      	adds	r3, #1
- 80027f8:	60fb      	str	r3, [r7, #12]
- 80027fa:	68fb      	ldr	r3, [r7, #12]
- 80027fc:	2b03      	cmp	r3, #3
- 80027fe:	d9d8      	bls.n	80027b2 <ETH_DMARxDescListInit+0xe>
-
-  }
-
-  WRITE_REG(heth->RxDescList.RxDescIdx, 0);
- 8002800:	687b      	ldr	r3, [r7, #4]
- 8002802:	2200      	movs	r2, #0
- 8002804:	65da      	str	r2, [r3, #92]	; 0x5c
-  WRITE_REG(heth->RxDescList.RxDescCnt, 0);
- 8002806:	687b      	ldr	r3, [r7, #4]
- 8002808:	2200      	movs	r2, #0
- 800280a:	661a      	str	r2, [r3, #96]	; 0x60
-  WRITE_REG(heth->RxDescList.RxBuildDescIdx, 0);
- 800280c:	687b      	ldr	r3, [r7, #4]
- 800280e:	2200      	movs	r2, #0
- 8002810:	669a      	str	r2, [r3, #104]	; 0x68
-  WRITE_REG(heth->RxDescList.RxBuildDescCnt, 0);
- 8002812:	687b      	ldr	r3, [r7, #4]
- 8002814:	2200      	movs	r2, #0
- 8002816:	66da      	str	r2, [r3, #108]	; 0x6c
-  WRITE_REG(heth->RxDescList.ItMode, 0);
- 8002818:	687b      	ldr	r3, [r7, #4]
- 800281a:	2200      	movs	r2, #0
- 800281c:	659a      	str	r2, [r3, #88]	; 0x58
-
-  /* Set Receive Descriptor Ring Length */
-  WRITE_REG(heth->Instance->DMACRDRLR, ((uint32_t)(ETH_RX_DESC_CNT - 1U)));
- 800281e:	687b      	ldr	r3, [r7, #4]
- 8002820:	681b      	ldr	r3, [r3, #0]
- 8002822:	f503 5380 	add.w	r3, r3, #4096	; 0x1000
- 8002826:	461a      	mov	r2, r3
- 8002828:	2303      	movs	r3, #3
- 800282a:	f8c2 3130 	str.w	r3, [r2, #304]	; 0x130
-
-  /* Set Receive Descriptor List Address */
-  WRITE_REG(heth->Instance->DMACRDLAR, (uint32_t) heth->Init.RxDesc);
- 800282e:	687b      	ldr	r3, [r7, #4]
- 8002830:	691a      	ldr	r2, [r3, #16]
- 8002832:	687b      	ldr	r3, [r7, #4]
- 8002834:	681b      	ldr	r3, [r3, #0]
- 8002836:	f503 5380 	add.w	r3, r3, #4096	; 0x1000
- 800283a:	f8c3 211c 	str.w	r2, [r3, #284]	; 0x11c
-
-  /* Set Receive Descriptor Tail pointer Address */
-  WRITE_REG(heth->Instance->DMACRDTPR, ((uint32_t)(heth->Init.RxDesc + (uint32_t)(ETH_RX_DESC_CNT - 1U))));
- 800283e:	687b      	ldr	r3, [r7, #4]
- 8002840:	691b      	ldr	r3, [r3, #16]
- 8002842:	f103 0248 	add.w	r2, r3, #72	; 0x48
- 8002846:	687b      	ldr	r3, [r7, #4]
- 8002848:	681b      	ldr	r3, [r3, #0]
- 800284a:	f503 5380 	add.w	r3, r3, #4096	; 0x1000
- 800284e:	f8c3 2128 	str.w	r2, [r3, #296]	; 0x128
-}
- 8002852:	bf00      	nop
- 8002854:	3714      	adds	r7, #20
- 8002856:	46bd      	mov	sp, r7
- 8002858:	f85d 7b04 	ldr.w	r7, [sp], #4
- 800285c:	4770      	bx	lr
-	...
-
-08002860 <ETH_Prepare_Tx_Descriptors>:
-  * @param  pTxConfig: Tx packet configuration
-  * @param  ItMode: Enable or disable Tx EOT interrept
-  * @retval Status
-  */
-static uint32_t ETH_Prepare_Tx_Descriptors(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig, uint32_t ItMode)
-{
- 8002860:	b480      	push	{r7}
- 8002862:	b08d      	sub	sp, #52	; 0x34
- 8002864:	af00      	add	r7, sp, #0
- 8002866:	60f8      	str	r0, [r7, #12]
- 8002868:	60b9      	str	r1, [r7, #8]
- 800286a:	607a      	str	r2, [r7, #4]
-  ETH_TxDescListTypeDef *dmatxdesclist = &heth->TxDescList;
- 800286c:	68fb      	ldr	r3, [r7, #12]
- 800286e:	3318      	adds	r3, #24
- 8002870:	617b      	str	r3, [r7, #20]
-  uint32_t descidx = dmatxdesclist->CurTxDesc;
- 8002872:	697b      	ldr	r3, [r7, #20]
- 8002874:	691b      	ldr	r3, [r3, #16]
- 8002876:	62fb      	str	r3, [r7, #44]	; 0x2c
-  uint32_t firstdescidx = dmatxdesclist->CurTxDesc;
- 8002878:	697b      	ldr	r3, [r7, #20]
- 800287a:	691b      	ldr	r3, [r3, #16]
- 800287c:	613b      	str	r3, [r7, #16]
-  uint32_t idx;
-  uint32_t descnbr = 0;
- 800287e:	2300      	movs	r3, #0
- 8002880:	627b      	str	r3, [r7, #36]	; 0x24
-  ETH_DMADescTypeDef *dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[descidx];
- 8002882:	697b      	ldr	r3, [r7, #20]
- 8002884:	6afa      	ldr	r2, [r7, #44]	; 0x2c
- 8002886:	f853 3022 	ldr.w	r3, [r3, r2, lsl #2]
- 800288a:	623b      	str	r3, [r7, #32]
-
-  ETH_BufferTypeDef  *txbuffer = pTxConfig->TxBuffer;
- 800288c:	68bb      	ldr	r3, [r7, #8]
- 800288e:	689b      	ldr	r3, [r3, #8]
- 8002890:	61fb      	str	r3, [r7, #28]
-  uint32_t           bd_count = 0;
- 8002892:	2300      	movs	r3, #0
- 8002894:	61bb      	str	r3, [r7, #24]
-
-  /* Current Tx Descriptor Owned by DMA: cannot be used by the application  */
-  if ((READ_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCWBF_OWN) == ETH_DMATXNDESCWBF_OWN)
- 8002896:	6a3b      	ldr	r3, [r7, #32]
- 8002898:	68db      	ldr	r3, [r3, #12]
- 800289a:	f003 4300 	and.w	r3, r3, #2147483648	; 0x80000000
- 800289e:	f1b3 4f00 	cmp.w	r3, #2147483648	; 0x80000000
- 80028a2:	d007      	beq.n	80028b4 <ETH_Prepare_Tx_Descriptors+0x54>
-      || (dmatxdesclist->PacketAddress[descidx] != NULL))
- 80028a4:	697a      	ldr	r2, [r7, #20]
- 80028a6:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 80028a8:	3304      	adds	r3, #4
- 80028aa:	009b      	lsls	r3, r3, #2
- 80028ac:	4413      	add	r3, r2
- 80028ae:	685b      	ldr	r3, [r3, #4]
- 80028b0:	2b00      	cmp	r3, #0
- 80028b2:	d001      	beq.n	80028b8 <ETH_Prepare_Tx_Descriptors+0x58>
-  {
-    return HAL_ETH_ERROR_BUSY;
- 80028b4:	2302      	movs	r3, #2
- 80028b6:	e259      	b.n	8002d6c <ETH_Prepare_Tx_Descriptors+0x50c>
-
-  /***************************************************************************/
-  /*****************    Context descriptor configuration (Optional) **********/
-  /***************************************************************************/
-  /* If VLAN tag is enabled for this packet */
-  if (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_VLANTAG) != (uint32_t)RESET)
- 80028b8:	68bb      	ldr	r3, [r7, #8]
- 80028ba:	681b      	ldr	r3, [r3, #0]
- 80028bc:	f003 0304 	and.w	r3, r3, #4
- 80028c0:	2b00      	cmp	r3, #0
- 80028c2:	d044      	beq.n	800294e <ETH_Prepare_Tx_Descriptors+0xee>
-  {
-    /* Set vlan tag value */
-    MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXCDESC_VT, pTxConfig->VlanTag);
- 80028c4:	6a3b      	ldr	r3, [r7, #32]
- 80028c6:	68da      	ldr	r2, [r3, #12]
- 80028c8:	4b75      	ldr	r3, [pc, #468]	; (8002aa0 <ETH_Prepare_Tx_Descriptors+0x240>)
- 80028ca:	4013      	ands	r3, r2
- 80028cc:	68ba      	ldr	r2, [r7, #8]
- 80028ce:	6a52      	ldr	r2, [r2, #36]	; 0x24
- 80028d0:	431a      	orrs	r2, r3
- 80028d2:	6a3b      	ldr	r3, [r7, #32]
- 80028d4:	60da      	str	r2, [r3, #12]
-    /* Set vlan tag valid bit */
-    SET_BIT(dmatxdesc->DESC3, ETH_DMATXCDESC_VLTV);
- 80028d6:	6a3b      	ldr	r3, [r7, #32]
- 80028d8:	68db      	ldr	r3, [r3, #12]
- 80028da:	f443 3280 	orr.w	r2, r3, #65536	; 0x10000
- 80028de:	6a3b      	ldr	r3, [r7, #32]
- 80028e0:	60da      	str	r2, [r3, #12]
-    /* Set the descriptor as the vlan input source */
-    SET_BIT(heth->Instance->MACVIR, ETH_MACVIR_VLTI);
- 80028e2:	68fb      	ldr	r3, [r7, #12]
- 80028e4:	681b      	ldr	r3, [r3, #0]
- 80028e6:	6e1a      	ldr	r2, [r3, #96]	; 0x60
- 80028e8:	68fb      	ldr	r3, [r7, #12]
- 80028ea:	681b      	ldr	r3, [r3, #0]
- 80028ec:	f442 1280 	orr.w	r2, r2, #1048576	; 0x100000
- 80028f0:	661a      	str	r2, [r3, #96]	; 0x60
-
-    /* if inner VLAN is enabled */
-    if (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_INNERVLANTAG) != (uint32_t)RESET)
- 80028f2:	68bb      	ldr	r3, [r7, #8]
- 80028f4:	681b      	ldr	r3, [r3, #0]
- 80028f6:	f003 0308 	and.w	r3, r3, #8
- 80028fa:	2b00      	cmp	r3, #0
- 80028fc:	d027      	beq.n	800294e <ETH_Prepare_Tx_Descriptors+0xee>
-    {
-      /* Set inner vlan tag value */
-      MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXCDESC_IVT, (pTxConfig->InnerVlanTag << 16));
- 80028fe:	6a3b      	ldr	r3, [r7, #32]
- 8002900:	689b      	ldr	r3, [r3, #8]
- 8002902:	b29a      	uxth	r2, r3
- 8002904:	68bb      	ldr	r3, [r7, #8]
- 8002906:	6adb      	ldr	r3, [r3, #44]	; 0x2c
- 8002908:	041b      	lsls	r3, r3, #16
- 800290a:	431a      	orrs	r2, r3
- 800290c:	6a3b      	ldr	r3, [r7, #32]
- 800290e:	609a      	str	r2, [r3, #8]
-      /* Set inner vlan tag valid bit */
-      SET_BIT(dmatxdesc->DESC3, ETH_DMATXCDESC_IVLTV);
- 8002910:	6a3b      	ldr	r3, [r7, #32]
- 8002912:	68db      	ldr	r3, [r3, #12]
- 8002914:	f443 3200 	orr.w	r2, r3, #131072	; 0x20000
- 8002918:	6a3b      	ldr	r3, [r7, #32]
- 800291a:	60da      	str	r2, [r3, #12]
-
-      /* Set Vlan Tag control */
-      MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXCDESC_IVTIR, pTxConfig->InnerVlanCtrl);
- 800291c:	6a3b      	ldr	r3, [r7, #32]
- 800291e:	68db      	ldr	r3, [r3, #12]
- 8002920:	f423 2240 	bic.w	r2, r3, #786432	; 0xc0000
- 8002924:	68bb      	ldr	r3, [r7, #8]
- 8002926:	6b1b      	ldr	r3, [r3, #48]	; 0x30
- 8002928:	431a      	orrs	r2, r3
- 800292a:	6a3b      	ldr	r3, [r7, #32]
- 800292c:	60da      	str	r2, [r3, #12]
-
-      /* Set the descriptor as the inner vlan input source */
-      SET_BIT(heth->Instance->MACIVIR, ETH_MACIVIR_VLTI);
- 800292e:	68fb      	ldr	r3, [r7, #12]
- 8002930:	681b      	ldr	r3, [r3, #0]
- 8002932:	6e5a      	ldr	r2, [r3, #100]	; 0x64
- 8002934:	68fb      	ldr	r3, [r7, #12]
- 8002936:	681b      	ldr	r3, [r3, #0]
- 8002938:	f442 1280 	orr.w	r2, r2, #1048576	; 0x100000
- 800293c:	665a      	str	r2, [r3, #100]	; 0x64
-      /* Enable double VLAN processing */
-      SET_BIT(heth->Instance->MACVTR, ETH_MACVTR_EDVLP);
- 800293e:	68fb      	ldr	r3, [r7, #12]
- 8002940:	681b      	ldr	r3, [r3, #0]
- 8002942:	6d1a      	ldr	r2, [r3, #80]	; 0x50
- 8002944:	68fb      	ldr	r3, [r7, #12]
- 8002946:	681b      	ldr	r3, [r3, #0]
- 8002948:	f042 6280 	orr.w	r2, r2, #67108864	; 0x4000000
- 800294c:	651a      	str	r2, [r3, #80]	; 0x50
-    }
-  }
-
-  /* if tcp segmentation is enabled for this packet */
-  if (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_TSO) != (uint32_t)RESET)
- 800294e:	68bb      	ldr	r3, [r7, #8]
- 8002950:	681b      	ldr	r3, [r3, #0]
- 8002952:	f003 0310 	and.w	r3, r3, #16
- 8002956:	2b00      	cmp	r3, #0
- 8002958:	d00e      	beq.n	8002978 <ETH_Prepare_Tx_Descriptors+0x118>
-  {
-    /* Set MSS value */
-    MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXCDESC_MSS, pTxConfig->MaxSegmentSize);
- 800295a:	6a3b      	ldr	r3, [r7, #32]
- 800295c:	689a      	ldr	r2, [r3, #8]
- 800295e:	4b51      	ldr	r3, [pc, #324]	; (8002aa4 <ETH_Prepare_Tx_Descriptors+0x244>)
- 8002960:	4013      	ands	r3, r2
- 8002962:	68ba      	ldr	r2, [r7, #8]
- 8002964:	6992      	ldr	r2, [r2, #24]
- 8002966:	431a      	orrs	r2, r3
- 8002968:	6a3b      	ldr	r3, [r7, #32]
- 800296a:	609a      	str	r2, [r3, #8]
-    /* Set MSS valid bit */
-    SET_BIT(dmatxdesc->DESC3, ETH_DMATXCDESC_TCMSSV);
- 800296c:	6a3b      	ldr	r3, [r7, #32]
- 800296e:	68db      	ldr	r3, [r3, #12]
- 8002970:	f043 6280 	orr.w	r2, r3, #67108864	; 0x4000000
- 8002974:	6a3b      	ldr	r3, [r7, #32]
- 8002976:	60da      	str	r2, [r3, #12]
-  }
-
-  if ((READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_VLANTAG) != (uint32_t)RESET)
- 8002978:	68bb      	ldr	r3, [r7, #8]
- 800297a:	681b      	ldr	r3, [r3, #0]
- 800297c:	f003 0304 	and.w	r3, r3, #4
- 8002980:	2b00      	cmp	r3, #0
- 8002982:	d105      	bne.n	8002990 <ETH_Prepare_Tx_Descriptors+0x130>
-      || (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_TSO) != (uint32_t)RESET))
- 8002984:	68bb      	ldr	r3, [r7, #8]
- 8002986:	681b      	ldr	r3, [r3, #0]
- 8002988:	f003 0310 	and.w	r3, r3, #16
- 800298c:	2b00      	cmp	r3, #0
- 800298e:	d036      	beq.n	80029fe <ETH_Prepare_Tx_Descriptors+0x19e>
-  {
-    /* Set as context descriptor */
-    SET_BIT(dmatxdesc->DESC3, ETH_DMATXCDESC_CTXT);
- 8002990:	6a3b      	ldr	r3, [r7, #32]
- 8002992:	68db      	ldr	r3, [r3, #12]
- 8002994:	f043 4280 	orr.w	r2, r3, #1073741824	; 0x40000000
- 8002998:	6a3b      	ldr	r3, [r7, #32]
- 800299a:	60da      	str	r2, [r3, #12]
-  __ASM volatile ("dmb 0xF":::"memory");
- 800299c:	f3bf 8f5f 	dmb	sy
-}
- 80029a0:	bf00      	nop
-    /* Ensure rest of descriptor is written to RAM before the OWN bit */
-    __DMB();
-    /* Set own bit */
-    SET_BIT(dmatxdesc->DESC3, ETH_DMATXCDESC_OWN);
- 80029a2:	6a3b      	ldr	r3, [r7, #32]
- 80029a4:	68db      	ldr	r3, [r3, #12]
- 80029a6:	f043 4200 	orr.w	r2, r3, #2147483648	; 0x80000000
- 80029aa:	6a3b      	ldr	r3, [r7, #32]
- 80029ac:	60da      	str	r2, [r3, #12]
-    /* Increment current tx descriptor index */
-    INCR_TX_DESC_INDEX(descidx, 1U);
- 80029ae:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 80029b0:	3301      	adds	r3, #1
- 80029b2:	62fb      	str	r3, [r7, #44]	; 0x2c
- 80029b4:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 80029b6:	2b03      	cmp	r3, #3
- 80029b8:	d902      	bls.n	80029c0 <ETH_Prepare_Tx_Descriptors+0x160>
- 80029ba:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 80029bc:	3b04      	subs	r3, #4
- 80029be:	62fb      	str	r3, [r7, #44]	; 0x2c
-    /* Get current descriptor address */
-    dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[descidx];
- 80029c0:	697b      	ldr	r3, [r7, #20]
- 80029c2:	6afa      	ldr	r2, [r7, #44]	; 0x2c
- 80029c4:	f853 3022 	ldr.w	r3, [r3, r2, lsl #2]
- 80029c8:	623b      	str	r3, [r7, #32]
-
-    descnbr += 1U;
- 80029ca:	6a7b      	ldr	r3, [r7, #36]	; 0x24
- 80029cc:	3301      	adds	r3, #1
- 80029ce:	627b      	str	r3, [r7, #36]	; 0x24
-
-    /* Current Tx Descriptor Owned by DMA: cannot be used by the application  */
-    if (READ_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCWBF_OWN) == ETH_DMATXNDESCWBF_OWN)
- 80029d0:	6a3b      	ldr	r3, [r7, #32]
- 80029d2:	68db      	ldr	r3, [r3, #12]
- 80029d4:	f003 4300 	and.w	r3, r3, #2147483648	; 0x80000000
- 80029d8:	f1b3 4f00 	cmp.w	r3, #2147483648	; 0x80000000
- 80029dc:	d10f      	bne.n	80029fe <ETH_Prepare_Tx_Descriptors+0x19e>
-    {
-      dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[firstdescidx];
- 80029de:	697b      	ldr	r3, [r7, #20]
- 80029e0:	693a      	ldr	r2, [r7, #16]
- 80029e2:	f853 3022 	ldr.w	r3, [r3, r2, lsl #2]
- 80029e6:	623b      	str	r3, [r7, #32]
-  __ASM volatile ("dmb 0xF":::"memory");
- 80029e8:	f3bf 8f5f 	dmb	sy
-}
- 80029ec:	bf00      	nop
-      /* Ensure rest of descriptor is written to RAM before the OWN bit */
-      __DMB();
-      /* Clear own bit */
-      CLEAR_BIT(dmatxdesc->DESC3, ETH_DMATXCDESC_OWN);
- 80029ee:	6a3b      	ldr	r3, [r7, #32]
- 80029f0:	68db      	ldr	r3, [r3, #12]
- 80029f2:	f023 4200 	bic.w	r2, r3, #2147483648	; 0x80000000
- 80029f6:	6a3b      	ldr	r3, [r7, #32]
- 80029f8:	60da      	str	r2, [r3, #12]
-
-      return HAL_ETH_ERROR_BUSY;
- 80029fa:	2302      	movs	r3, #2
- 80029fc:	e1b6      	b.n	8002d6c <ETH_Prepare_Tx_Descriptors+0x50c>
-
-  /***************************************************************************/
-  /*****************    Normal descriptors configuration     *****************/
-  /***************************************************************************/
-
-  descnbr += 1U;
- 80029fe:	6a7b      	ldr	r3, [r7, #36]	; 0x24
- 8002a00:	3301      	adds	r3, #1
- 8002a02:	627b      	str	r3, [r7, #36]	; 0x24
-
-  /* Set header or buffer 1 address */
-  WRITE_REG(dmatxdesc->DESC0, (uint32_t)txbuffer->buffer);
- 8002a04:	69fb      	ldr	r3, [r7, #28]
- 8002a06:	681b      	ldr	r3, [r3, #0]
- 8002a08:	461a      	mov	r2, r3
- 8002a0a:	6a3b      	ldr	r3, [r7, #32]
- 8002a0c:	601a      	str	r2, [r3, #0]
-  /* Set header or buffer 1 Length */
-  MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_B1L, txbuffer->len);
- 8002a0e:	6a3b      	ldr	r3, [r7, #32]
- 8002a10:	689a      	ldr	r2, [r3, #8]
- 8002a12:	4b24      	ldr	r3, [pc, #144]	; (8002aa4 <ETH_Prepare_Tx_Descriptors+0x244>)
- 8002a14:	4013      	ands	r3, r2
- 8002a16:	69fa      	ldr	r2, [r7, #28]
- 8002a18:	6852      	ldr	r2, [r2, #4]
- 8002a1a:	431a      	orrs	r2, r3
- 8002a1c:	6a3b      	ldr	r3, [r7, #32]
- 8002a1e:	609a      	str	r2, [r3, #8]
-
-  if (txbuffer->next != NULL)
- 8002a20:	69fb      	ldr	r3, [r7, #28]
- 8002a22:	689b      	ldr	r3, [r3, #8]
- 8002a24:	2b00      	cmp	r3, #0
- 8002a26:	d012      	beq.n	8002a4e <ETH_Prepare_Tx_Descriptors+0x1ee>
-  {
-    txbuffer = txbuffer->next;
- 8002a28:	69fb      	ldr	r3, [r7, #28]
- 8002a2a:	689b      	ldr	r3, [r3, #8]
- 8002a2c:	61fb      	str	r3, [r7, #28]
-    /* Set buffer 2 address */
-    WRITE_REG(dmatxdesc->DESC1, (uint32_t)txbuffer->buffer);
- 8002a2e:	69fb      	ldr	r3, [r7, #28]
- 8002a30:	681b      	ldr	r3, [r3, #0]
- 8002a32:	461a      	mov	r2, r3
- 8002a34:	6a3b      	ldr	r3, [r7, #32]
- 8002a36:	605a      	str	r2, [r3, #4]
-    /* Set buffer 2 Length */
-    MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_B2L, (txbuffer->len << 16));
- 8002a38:	6a3b      	ldr	r3, [r7, #32]
- 8002a3a:	689a      	ldr	r2, [r3, #8]
- 8002a3c:	4b1a      	ldr	r3, [pc, #104]	; (8002aa8 <ETH_Prepare_Tx_Descriptors+0x248>)
- 8002a3e:	4013      	ands	r3, r2
- 8002a40:	69fa      	ldr	r2, [r7, #28]
- 8002a42:	6852      	ldr	r2, [r2, #4]
- 8002a44:	0412      	lsls	r2, r2, #16
- 8002a46:	431a      	orrs	r2, r3
- 8002a48:	6a3b      	ldr	r3, [r7, #32]
- 8002a4a:	609a      	str	r2, [r3, #8]
- 8002a4c:	e008      	b.n	8002a60 <ETH_Prepare_Tx_Descriptors+0x200>
-  }
-  else
-  {
-    WRITE_REG(dmatxdesc->DESC1, 0x0);
- 8002a4e:	6a3b      	ldr	r3, [r7, #32]
- 8002a50:	2200      	movs	r2, #0
- 8002a52:	605a      	str	r2, [r3, #4]
-    /* Set buffer 2 Length */
-    MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_B2L, 0x0U);
- 8002a54:	6a3b      	ldr	r3, [r7, #32]
- 8002a56:	689a      	ldr	r2, [r3, #8]
- 8002a58:	4b13      	ldr	r3, [pc, #76]	; (8002aa8 <ETH_Prepare_Tx_Descriptors+0x248>)
- 8002a5a:	4013      	ands	r3, r2
- 8002a5c:	6a3a      	ldr	r2, [r7, #32]
- 8002a5e:	6093      	str	r3, [r2, #8]
-  }
-
-  if (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_TSO) != (uint32_t)RESET)
- 8002a60:	68bb      	ldr	r3, [r7, #8]
- 8002a62:	681b      	ldr	r3, [r3, #0]
- 8002a64:	f003 0310 	and.w	r3, r3, #16
- 8002a68:	2b00      	cmp	r3, #0
- 8002a6a:	d021      	beq.n	8002ab0 <ETH_Prepare_Tx_Descriptors+0x250>
-  {
-    /* Set TCP Header length */
-    MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_THL, (pTxConfig->TCPHeaderLen << 19));
- 8002a6c:	6a3b      	ldr	r3, [r7, #32]
- 8002a6e:	68db      	ldr	r3, [r3, #12]
- 8002a70:	f423 02f0 	bic.w	r2, r3, #7864320	; 0x780000
- 8002a74:	68bb      	ldr	r3, [r7, #8]
- 8002a76:	6a1b      	ldr	r3, [r3, #32]
- 8002a78:	04db      	lsls	r3, r3, #19
- 8002a7a:	431a      	orrs	r2, r3
- 8002a7c:	6a3b      	ldr	r3, [r7, #32]
- 8002a7e:	60da      	str	r2, [r3, #12]
-    /* Set TCP payload length */
-    MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_TPL, pTxConfig->PayloadLen);
- 8002a80:	6a3b      	ldr	r3, [r7, #32]
- 8002a82:	68da      	ldr	r2, [r3, #12]
- 8002a84:	4b09      	ldr	r3, [pc, #36]	; (8002aac <ETH_Prepare_Tx_Descriptors+0x24c>)
- 8002a86:	4013      	ands	r3, r2
- 8002a88:	68ba      	ldr	r2, [r7, #8]
- 8002a8a:	69d2      	ldr	r2, [r2, #28]
- 8002a8c:	431a      	orrs	r2, r3
- 8002a8e:	6a3b      	ldr	r3, [r7, #32]
- 8002a90:	60da      	str	r2, [r3, #12]
-    /* Set TCP Segmentation Enabled bit */
-    SET_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_TSE);
- 8002a92:	6a3b      	ldr	r3, [r7, #32]
- 8002a94:	68db      	ldr	r3, [r3, #12]
- 8002a96:	f443 2280 	orr.w	r2, r3, #262144	; 0x40000
- 8002a9a:	6a3b      	ldr	r3, [r7, #32]
- 8002a9c:	60da      	str	r2, [r3, #12]
- 8002a9e:	e02e      	b.n	8002afe <ETH_Prepare_Tx_Descriptors+0x29e>
- 8002aa0:	ffff0000 	.word	0xffff0000
- 8002aa4:	ffffc000 	.word	0xffffc000
- 8002aa8:	c000ffff 	.word	0xc000ffff
- 8002aac:	fffc0000 	.word	0xfffc0000
-  }
-  else
-  {
-    MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_FL, pTxConfig->Length);
- 8002ab0:	6a3b      	ldr	r3, [r7, #32]
- 8002ab2:	68da      	ldr	r2, [r3, #12]
- 8002ab4:	4b7b      	ldr	r3, [pc, #492]	; (8002ca4 <ETH_Prepare_Tx_Descriptors+0x444>)
- 8002ab6:	4013      	ands	r3, r2
- 8002ab8:	68ba      	ldr	r2, [r7, #8]
- 8002aba:	6852      	ldr	r2, [r2, #4]
- 8002abc:	431a      	orrs	r2, r3
- 8002abe:	6a3b      	ldr	r3, [r7, #32]
- 8002ac0:	60da      	str	r2, [r3, #12]
-
-    if (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_CSUM) != (uint32_t)RESET)
- 8002ac2:	68bb      	ldr	r3, [r7, #8]
- 8002ac4:	681b      	ldr	r3, [r3, #0]
- 8002ac6:	f003 0301 	and.w	r3, r3, #1
- 8002aca:	2b00      	cmp	r3, #0
- 8002acc:	d008      	beq.n	8002ae0 <ETH_Prepare_Tx_Descriptors+0x280>
-    {
-      MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_CIC, pTxConfig->ChecksumCtrl);
- 8002ace:	6a3b      	ldr	r3, [r7, #32]
- 8002ad0:	68db      	ldr	r3, [r3, #12]
- 8002ad2:	f423 3240 	bic.w	r2, r3, #196608	; 0x30000
- 8002ad6:	68bb      	ldr	r3, [r7, #8]
- 8002ad8:	695b      	ldr	r3, [r3, #20]
- 8002ada:	431a      	orrs	r2, r3
- 8002adc:	6a3b      	ldr	r3, [r7, #32]
- 8002ade:	60da      	str	r2, [r3, #12]
-    }
-
-    if (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_CRCPAD) != (uint32_t)RESET)
- 8002ae0:	68bb      	ldr	r3, [r7, #8]
- 8002ae2:	681b      	ldr	r3, [r3, #0]
- 8002ae4:	f003 0320 	and.w	r3, r3, #32
- 8002ae8:	2b00      	cmp	r3, #0
- 8002aea:	d008      	beq.n	8002afe <ETH_Prepare_Tx_Descriptors+0x29e>
-    {
-      MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_CPC, pTxConfig->CRCPadCtrl);
- 8002aec:	6a3b      	ldr	r3, [r7, #32]
- 8002aee:	68db      	ldr	r3, [r3, #12]
- 8002af0:	f023 6240 	bic.w	r2, r3, #201326592	; 0xc000000
- 8002af4:	68bb      	ldr	r3, [r7, #8]
- 8002af6:	691b      	ldr	r3, [r3, #16]
- 8002af8:	431a      	orrs	r2, r3
- 8002afa:	6a3b      	ldr	r3, [r7, #32]
- 8002afc:	60da      	str	r2, [r3, #12]
-    }
-  }
-
-  if (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_VLANTAG) != (uint32_t)RESET)
- 8002afe:	68bb      	ldr	r3, [r7, #8]
- 8002b00:	681b      	ldr	r3, [r3, #0]
- 8002b02:	f003 0304 	and.w	r3, r3, #4
- 8002b06:	2b00      	cmp	r3, #0
- 8002b08:	d008      	beq.n	8002b1c <ETH_Prepare_Tx_Descriptors+0x2bc>
-  {
-    /* Set Vlan Tag control */
-    MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_VTIR, pTxConfig->VlanCtrl);
- 8002b0a:	6a3b      	ldr	r3, [r7, #32]
- 8002b0c:	689b      	ldr	r3, [r3, #8]
- 8002b0e:	f423 4240 	bic.w	r2, r3, #49152	; 0xc000
- 8002b12:	68bb      	ldr	r3, [r7, #8]
- 8002b14:	6a9b      	ldr	r3, [r3, #40]	; 0x28
- 8002b16:	431a      	orrs	r2, r3
- 8002b18:	6a3b      	ldr	r3, [r7, #32]
- 8002b1a:	609a      	str	r2, [r3, #8]
-  }
-
-  /* Mark it as First Descriptor */
-  SET_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_FD);
- 8002b1c:	6a3b      	ldr	r3, [r7, #32]
- 8002b1e:	68db      	ldr	r3, [r3, #12]
- 8002b20:	f043 5200 	orr.w	r2, r3, #536870912	; 0x20000000
- 8002b24:	6a3b      	ldr	r3, [r7, #32]
- 8002b26:	60da      	str	r2, [r3, #12]
-  /* Mark it as NORMAL descriptor */
-  CLEAR_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_CTXT);
- 8002b28:	6a3b      	ldr	r3, [r7, #32]
- 8002b2a:	68db      	ldr	r3, [r3, #12]
- 8002b2c:	f023 4280 	bic.w	r2, r3, #1073741824	; 0x40000000
- 8002b30:	6a3b      	ldr	r3, [r7, #32]
- 8002b32:	60da      	str	r2, [r3, #12]
-  __ASM volatile ("dmb 0xF":::"memory");
- 8002b34:	f3bf 8f5f 	dmb	sy
-}
- 8002b38:	bf00      	nop
-  /* Ensure rest of descriptor is written to RAM before the OWN bit */
-  __DMB();
-  /* set OWN bit of FIRST descriptor */
-  SET_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_OWN);
- 8002b3a:	6a3b      	ldr	r3, [r7, #32]
- 8002b3c:	68db      	ldr	r3, [r3, #12]
- 8002b3e:	f043 4200 	orr.w	r2, r3, #2147483648	; 0x80000000
- 8002b42:	6a3b      	ldr	r3, [r7, #32]
- 8002b44:	60da      	str	r2, [r3, #12]
-
-  /* If source address insertion/replacement is enabled for this packet */
-  if (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_SAIC) != (uint32_t)RESET)
- 8002b46:	68bb      	ldr	r3, [r7, #8]
- 8002b48:	681b      	ldr	r3, [r3, #0]
- 8002b4a:	f003 0302 	and.w	r3, r3, #2
- 8002b4e:	2b00      	cmp	r3, #0
- 8002b50:	f000 80da 	beq.w	8002d08 <ETH_Prepare_Tx_Descriptors+0x4a8>
-  {
-    MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_SAIC, pTxConfig->SrcAddrCtrl);
- 8002b54:	6a3b      	ldr	r3, [r7, #32]
- 8002b56:	68db      	ldr	r3, [r3, #12]
- 8002b58:	f023 7260 	bic.w	r2, r3, #58720256	; 0x3800000
- 8002b5c:	68bb      	ldr	r3, [r7, #8]
- 8002b5e:	68db      	ldr	r3, [r3, #12]
- 8002b60:	431a      	orrs	r2, r3
- 8002b62:	6a3b      	ldr	r3, [r7, #32]
- 8002b64:	60da      	str	r2, [r3, #12]
-  }
-
-  /* only if the packet is split into more than one descriptors > 1 */
-  while (txbuffer->next != NULL)
- 8002b66:	e0cf      	b.n	8002d08 <ETH_Prepare_Tx_Descriptors+0x4a8>
-  {
-    /* Clear the LD bit of previous descriptor */
-    CLEAR_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_LD);
- 8002b68:	6a3b      	ldr	r3, [r7, #32]
- 8002b6a:	68db      	ldr	r3, [r3, #12]
- 8002b6c:	f023 5280 	bic.w	r2, r3, #268435456	; 0x10000000
- 8002b70:	6a3b      	ldr	r3, [r7, #32]
- 8002b72:	60da      	str	r2, [r3, #12]
-    /* Increment current tx descriptor index */
-    INCR_TX_DESC_INDEX(descidx, 1U);
- 8002b74:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 8002b76:	3301      	adds	r3, #1
- 8002b78:	62fb      	str	r3, [r7, #44]	; 0x2c
- 8002b7a:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 8002b7c:	2b03      	cmp	r3, #3
- 8002b7e:	d902      	bls.n	8002b86 <ETH_Prepare_Tx_Descriptors+0x326>
- 8002b80:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 8002b82:	3b04      	subs	r3, #4
- 8002b84:	62fb      	str	r3, [r7, #44]	; 0x2c
-    /* Get current descriptor address */
-    dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[descidx];
- 8002b86:	697b      	ldr	r3, [r7, #20]
- 8002b88:	6afa      	ldr	r2, [r7, #44]	; 0x2c
- 8002b8a:	f853 3022 	ldr.w	r3, [r3, r2, lsl #2]
- 8002b8e:	623b      	str	r3, [r7, #32]
-
-    /* Clear the FD bit of new Descriptor */
-    CLEAR_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_FD);
- 8002b90:	6a3b      	ldr	r3, [r7, #32]
- 8002b92:	68db      	ldr	r3, [r3, #12]
- 8002b94:	f023 5200 	bic.w	r2, r3, #536870912	; 0x20000000
- 8002b98:	6a3b      	ldr	r3, [r7, #32]
- 8002b9a:	60da      	str	r2, [r3, #12]
-
-    /* Current Tx Descriptor Owned by DMA: cannot be used by the application  */
-    if ((READ_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_OWN) == ETH_DMATXNDESCRF_OWN)
- 8002b9c:	6a3b      	ldr	r3, [r7, #32]
- 8002b9e:	68db      	ldr	r3, [r3, #12]
- 8002ba0:	f003 4300 	and.w	r3, r3, #2147483648	; 0x80000000
- 8002ba4:	f1b3 4f00 	cmp.w	r3, #2147483648	; 0x80000000
- 8002ba8:	d007      	beq.n	8002bba <ETH_Prepare_Tx_Descriptors+0x35a>
-        || (dmatxdesclist->PacketAddress[descidx] != NULL))
- 8002baa:	697a      	ldr	r2, [r7, #20]
- 8002bac:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 8002bae:	3304      	adds	r3, #4
- 8002bb0:	009b      	lsls	r3, r3, #2
- 8002bb2:	4413      	add	r3, r2
- 8002bb4:	685b      	ldr	r3, [r3, #4]
- 8002bb6:	2b00      	cmp	r3, #0
- 8002bb8:	d029      	beq.n	8002c0e <ETH_Prepare_Tx_Descriptors+0x3ae>
-    {
-      descidx = firstdescidx;
- 8002bba:	693b      	ldr	r3, [r7, #16]
- 8002bbc:	62fb      	str	r3, [r7, #44]	; 0x2c
-      dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[descidx];
- 8002bbe:	697b      	ldr	r3, [r7, #20]
- 8002bc0:	6afa      	ldr	r2, [r7, #44]	; 0x2c
- 8002bc2:	f853 3022 	ldr.w	r3, [r3, r2, lsl #2]
- 8002bc6:	623b      	str	r3, [r7, #32]
-
-      /* clear previous desc own bit */
-      for (idx = 0; idx < descnbr; idx ++)
- 8002bc8:	2300      	movs	r3, #0
- 8002bca:	62bb      	str	r3, [r7, #40]	; 0x28
- 8002bcc:	e019      	b.n	8002c02 <ETH_Prepare_Tx_Descriptors+0x3a2>
-  __ASM volatile ("dmb 0xF":::"memory");
- 8002bce:	f3bf 8f5f 	dmb	sy
-}
- 8002bd2:	bf00      	nop
-      {
-        /* Ensure rest of descriptor is written to RAM before the OWN bit */
-        __DMB();
-
-        CLEAR_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_OWN);
- 8002bd4:	6a3b      	ldr	r3, [r7, #32]
- 8002bd6:	68db      	ldr	r3, [r3, #12]
- 8002bd8:	f023 4200 	bic.w	r2, r3, #2147483648	; 0x80000000
- 8002bdc:	6a3b      	ldr	r3, [r7, #32]
- 8002bde:	60da      	str	r2, [r3, #12]
-
-        /* Increment current tx descriptor index */
-        INCR_TX_DESC_INDEX(descidx, 1U);
- 8002be0:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 8002be2:	3301      	adds	r3, #1
- 8002be4:	62fb      	str	r3, [r7, #44]	; 0x2c
- 8002be6:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 8002be8:	2b03      	cmp	r3, #3
- 8002bea:	d902      	bls.n	8002bf2 <ETH_Prepare_Tx_Descriptors+0x392>
- 8002bec:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 8002bee:	3b04      	subs	r3, #4
- 8002bf0:	62fb      	str	r3, [r7, #44]	; 0x2c
-        /* Get current descriptor address */
-        dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[descidx];
- 8002bf2:	697b      	ldr	r3, [r7, #20]
- 8002bf4:	6afa      	ldr	r2, [r7, #44]	; 0x2c
- 8002bf6:	f853 3022 	ldr.w	r3, [r3, r2, lsl #2]
- 8002bfa:	623b      	str	r3, [r7, #32]
-      for (idx = 0; idx < descnbr; idx ++)
- 8002bfc:	6abb      	ldr	r3, [r7, #40]	; 0x28
- 8002bfe:	3301      	adds	r3, #1
- 8002c00:	62bb      	str	r3, [r7, #40]	; 0x28
- 8002c02:	6aba      	ldr	r2, [r7, #40]	; 0x28
- 8002c04:	6a7b      	ldr	r3, [r7, #36]	; 0x24
- 8002c06:	429a      	cmp	r2, r3
- 8002c08:	d3e1      	bcc.n	8002bce <ETH_Prepare_Tx_Descriptors+0x36e>
-      }
-
-      return HAL_ETH_ERROR_BUSY;
- 8002c0a:	2302      	movs	r3, #2
- 8002c0c:	e0ae      	b.n	8002d6c <ETH_Prepare_Tx_Descriptors+0x50c>
-    }
-
-    descnbr += 1U;
- 8002c0e:	6a7b      	ldr	r3, [r7, #36]	; 0x24
- 8002c10:	3301      	adds	r3, #1
- 8002c12:	627b      	str	r3, [r7, #36]	; 0x24
-
-    /* Get the next Tx buffer in the list */
-    txbuffer = txbuffer->next;
- 8002c14:	69fb      	ldr	r3, [r7, #28]
- 8002c16:	689b      	ldr	r3, [r3, #8]
- 8002c18:	61fb      	str	r3, [r7, #28]
-
-    /* Set header or buffer 1 address */
-    WRITE_REG(dmatxdesc->DESC0, (uint32_t)txbuffer->buffer);
- 8002c1a:	69fb      	ldr	r3, [r7, #28]
- 8002c1c:	681b      	ldr	r3, [r3, #0]
- 8002c1e:	461a      	mov	r2, r3
- 8002c20:	6a3b      	ldr	r3, [r7, #32]
- 8002c22:	601a      	str	r2, [r3, #0]
-    /* Set header or buffer 1 Length */
-    MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_B1L, txbuffer->len);
- 8002c24:	6a3b      	ldr	r3, [r7, #32]
- 8002c26:	689a      	ldr	r2, [r3, #8]
- 8002c28:	4b1f      	ldr	r3, [pc, #124]	; (8002ca8 <ETH_Prepare_Tx_Descriptors+0x448>)
- 8002c2a:	4013      	ands	r3, r2
- 8002c2c:	69fa      	ldr	r2, [r7, #28]
- 8002c2e:	6852      	ldr	r2, [r2, #4]
- 8002c30:	431a      	orrs	r2, r3
- 8002c32:	6a3b      	ldr	r3, [r7, #32]
- 8002c34:	609a      	str	r2, [r3, #8]
-
-    if (txbuffer->next != NULL)
- 8002c36:	69fb      	ldr	r3, [r7, #28]
- 8002c38:	689b      	ldr	r3, [r3, #8]
- 8002c3a:	2b00      	cmp	r3, #0
- 8002c3c:	d012      	beq.n	8002c64 <ETH_Prepare_Tx_Descriptors+0x404>
-    {
-      /* Get the next Tx buffer in the list */
-      txbuffer = txbuffer->next;
- 8002c3e:	69fb      	ldr	r3, [r7, #28]
- 8002c40:	689b      	ldr	r3, [r3, #8]
- 8002c42:	61fb      	str	r3, [r7, #28]
-      /* Set buffer 2 address */
-      WRITE_REG(dmatxdesc->DESC1, (uint32_t)txbuffer->buffer);
- 8002c44:	69fb      	ldr	r3, [r7, #28]
- 8002c46:	681b      	ldr	r3, [r3, #0]
- 8002c48:	461a      	mov	r2, r3
- 8002c4a:	6a3b      	ldr	r3, [r7, #32]
- 8002c4c:	605a      	str	r2, [r3, #4]
-      /* Set buffer 2 Length */
-      MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_B2L, (txbuffer->len << 16));
- 8002c4e:	6a3b      	ldr	r3, [r7, #32]
- 8002c50:	689a      	ldr	r2, [r3, #8]
- 8002c52:	4b16      	ldr	r3, [pc, #88]	; (8002cac <ETH_Prepare_Tx_Descriptors+0x44c>)
- 8002c54:	4013      	ands	r3, r2
- 8002c56:	69fa      	ldr	r2, [r7, #28]
- 8002c58:	6852      	ldr	r2, [r2, #4]
- 8002c5a:	0412      	lsls	r2, r2, #16
- 8002c5c:	431a      	orrs	r2, r3
- 8002c5e:	6a3b      	ldr	r3, [r7, #32]
- 8002c60:	609a      	str	r2, [r3, #8]
- 8002c62:	e008      	b.n	8002c76 <ETH_Prepare_Tx_Descriptors+0x416>
-    }
-    else
-    {
-      WRITE_REG(dmatxdesc->DESC1, 0x0);
- 8002c64:	6a3b      	ldr	r3, [r7, #32]
- 8002c66:	2200      	movs	r2, #0
- 8002c68:	605a      	str	r2, [r3, #4]
-      /* Set buffer 2 Length */
-      MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_B2L, 0x0U);
- 8002c6a:	6a3b      	ldr	r3, [r7, #32]
- 8002c6c:	689a      	ldr	r2, [r3, #8]
- 8002c6e:	4b0f      	ldr	r3, [pc, #60]	; (8002cac <ETH_Prepare_Tx_Descriptors+0x44c>)
- 8002c70:	4013      	ands	r3, r2
- 8002c72:	6a3a      	ldr	r2, [r7, #32]
- 8002c74:	6093      	str	r3, [r2, #8]
-    }
-
-    if (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_TSO) != (uint32_t)RESET)
- 8002c76:	68bb      	ldr	r3, [r7, #8]
- 8002c78:	681b      	ldr	r3, [r3, #0]
- 8002c7a:	f003 0310 	and.w	r3, r3, #16
- 8002c7e:	2b00      	cmp	r3, #0
- 8002c80:	d018      	beq.n	8002cb4 <ETH_Prepare_Tx_Descriptors+0x454>
-    {
-      /* Set TCP payload length */
-      MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_TPL, pTxConfig->PayloadLen);
- 8002c82:	6a3b      	ldr	r3, [r7, #32]
- 8002c84:	68da      	ldr	r2, [r3, #12]
- 8002c86:	4b0a      	ldr	r3, [pc, #40]	; (8002cb0 <ETH_Prepare_Tx_Descriptors+0x450>)
- 8002c88:	4013      	ands	r3, r2
- 8002c8a:	68ba      	ldr	r2, [r7, #8]
- 8002c8c:	69d2      	ldr	r2, [r2, #28]
- 8002c8e:	431a      	orrs	r2, r3
- 8002c90:	6a3b      	ldr	r3, [r7, #32]
- 8002c92:	60da      	str	r2, [r3, #12]
-      /* Set TCP Segmentation Enabled bit */
-      SET_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_TSE);
- 8002c94:	6a3b      	ldr	r3, [r7, #32]
- 8002c96:	68db      	ldr	r3, [r3, #12]
- 8002c98:	f443 2280 	orr.w	r2, r3, #262144	; 0x40000
- 8002c9c:	6a3b      	ldr	r3, [r7, #32]
- 8002c9e:	60da      	str	r2, [r3, #12]
- 8002ca0:	e020      	b.n	8002ce4 <ETH_Prepare_Tx_Descriptors+0x484>
- 8002ca2:	bf00      	nop
- 8002ca4:	ffff8000 	.word	0xffff8000
- 8002ca8:	ffffc000 	.word	0xffffc000
- 8002cac:	c000ffff 	.word	0xc000ffff
- 8002cb0:	fffc0000 	.word	0xfffc0000
-    }
-    else
-    {
-      /* Set the packet length */
-      MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_FL, pTxConfig->Length);
- 8002cb4:	6a3b      	ldr	r3, [r7, #32]
- 8002cb6:	68da      	ldr	r2, [r3, #12]
- 8002cb8:	4b2f      	ldr	r3, [pc, #188]	; (8002d78 <ETH_Prepare_Tx_Descriptors+0x518>)
- 8002cba:	4013      	ands	r3, r2
- 8002cbc:	68ba      	ldr	r2, [r7, #8]
- 8002cbe:	6852      	ldr	r2, [r2, #4]
- 8002cc0:	431a      	orrs	r2, r3
- 8002cc2:	6a3b      	ldr	r3, [r7, #32]
- 8002cc4:	60da      	str	r2, [r3, #12]
-
-      if (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_CSUM) != (uint32_t)RESET)
- 8002cc6:	68bb      	ldr	r3, [r7, #8]
- 8002cc8:	681b      	ldr	r3, [r3, #0]
- 8002cca:	f003 0301 	and.w	r3, r3, #1
- 8002cce:	2b00      	cmp	r3, #0
- 8002cd0:	d008      	beq.n	8002ce4 <ETH_Prepare_Tx_Descriptors+0x484>
-      {
-        /* Checksum Insertion Control */
-        MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_CIC, pTxConfig->ChecksumCtrl);
- 8002cd2:	6a3b      	ldr	r3, [r7, #32]
- 8002cd4:	68db      	ldr	r3, [r3, #12]
- 8002cd6:	f423 3240 	bic.w	r2, r3, #196608	; 0x30000
- 8002cda:	68bb      	ldr	r3, [r7, #8]
- 8002cdc:	695b      	ldr	r3, [r3, #20]
- 8002cde:	431a      	orrs	r2, r3
- 8002ce0:	6a3b      	ldr	r3, [r7, #32]
- 8002ce2:	60da      	str	r2, [r3, #12]
-      }
-    }
-
-    bd_count += 1U;
- 8002ce4:	69bb      	ldr	r3, [r7, #24]
- 8002ce6:	3301      	adds	r3, #1
- 8002ce8:	61bb      	str	r3, [r7, #24]
-  __ASM volatile ("dmb 0xF":::"memory");
- 8002cea:	f3bf 8f5f 	dmb	sy
-}
- 8002cee:	bf00      	nop
-
-    /* Ensure rest of descriptor is written to RAM before the OWN bit */
-    __DMB();
-    /* Set Own bit */
-    SET_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_OWN);
- 8002cf0:	6a3b      	ldr	r3, [r7, #32]
- 8002cf2:	68db      	ldr	r3, [r3, #12]
- 8002cf4:	f043 4200 	orr.w	r2, r3, #2147483648	; 0x80000000
- 8002cf8:	6a3b      	ldr	r3, [r7, #32]
- 8002cfa:	60da      	str	r2, [r3, #12]
-    /* Mark it as NORMAL descriptor */
-    CLEAR_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_CTXT);
- 8002cfc:	6a3b      	ldr	r3, [r7, #32]
- 8002cfe:	68db      	ldr	r3, [r3, #12]
- 8002d00:	f023 4280 	bic.w	r2, r3, #1073741824	; 0x40000000
- 8002d04:	6a3b      	ldr	r3, [r7, #32]
- 8002d06:	60da      	str	r2, [r3, #12]
-  while (txbuffer->next != NULL)
- 8002d08:	69fb      	ldr	r3, [r7, #28]
- 8002d0a:	689b      	ldr	r3, [r3, #8]
- 8002d0c:	2b00      	cmp	r3, #0
- 8002d0e:	f47f af2b 	bne.w	8002b68 <ETH_Prepare_Tx_Descriptors+0x308>
-  }
-
-  if (ItMode != ((uint32_t)RESET))
- 8002d12:	687b      	ldr	r3, [r7, #4]
- 8002d14:	2b00      	cmp	r3, #0
- 8002d16:	d006      	beq.n	8002d26 <ETH_Prepare_Tx_Descriptors+0x4c6>
-  {
-    /* Set Interrupt on completion bit */
-    SET_BIT(dmatxdesc->DESC2, ETH_DMATXNDESCRF_IOC);
- 8002d18:	6a3b      	ldr	r3, [r7, #32]
- 8002d1a:	689b      	ldr	r3, [r3, #8]
- 8002d1c:	f043 4200 	orr.w	r2, r3, #2147483648	; 0x80000000
- 8002d20:	6a3b      	ldr	r3, [r7, #32]
- 8002d22:	609a      	str	r2, [r3, #8]
- 8002d24:	e005      	b.n	8002d32 <ETH_Prepare_Tx_Descriptors+0x4d2>
-  }
-  else
-  {
-    /* Clear Interrupt on completion bit */
-    CLEAR_BIT(dmatxdesc->DESC2, ETH_DMATXNDESCRF_IOC);
- 8002d26:	6a3b      	ldr	r3, [r7, #32]
- 8002d28:	689b      	ldr	r3, [r3, #8]
- 8002d2a:	f023 4200 	bic.w	r2, r3, #2147483648	; 0x80000000
- 8002d2e:	6a3b      	ldr	r3, [r7, #32]
- 8002d30:	609a      	str	r2, [r3, #8]
-  }
-
-  /* Mark it as LAST descriptor */
-  SET_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_LD);
- 8002d32:	6a3b      	ldr	r3, [r7, #32]
- 8002d34:	68db      	ldr	r3, [r3, #12]
- 8002d36:	f043 5280 	orr.w	r2, r3, #268435456	; 0x10000000
- 8002d3a:	6a3b      	ldr	r3, [r7, #32]
- 8002d3c:	60da      	str	r2, [r3, #12]
-  /* Save the current packet address to expose it to the application */
-  dmatxdesclist->PacketAddress[descidx] = dmatxdesclist->CurrentPacketAddress;
- 8002d3e:	697b      	ldr	r3, [r7, #20]
- 8002d40:	6a5a      	ldr	r2, [r3, #36]	; 0x24
- 8002d42:	6979      	ldr	r1, [r7, #20]
- 8002d44:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 8002d46:	3304      	adds	r3, #4
- 8002d48:	009b      	lsls	r3, r3, #2
- 8002d4a:	440b      	add	r3, r1
- 8002d4c:	605a      	str	r2, [r3, #4]
-
-  dmatxdesclist->CurTxDesc = descidx;
- 8002d4e:	697b      	ldr	r3, [r7, #20]
- 8002d50:	6afa      	ldr	r2, [r7, #44]	; 0x2c
- 8002d52:	611a      	str	r2, [r3, #16]
-  __ASM volatile ("cpsid i" : : : "memory");
- 8002d54:	b672      	cpsid	i
-}
- 8002d56:	bf00      	nop
-
-  /* disable the interrupt */
-  __disable_irq();
-
-  dmatxdesclist->BuffersInUse += bd_count + 1U;
- 8002d58:	697b      	ldr	r3, [r7, #20]
- 8002d5a:	6a9a      	ldr	r2, [r3, #40]	; 0x28
- 8002d5c:	69bb      	ldr	r3, [r7, #24]
- 8002d5e:	4413      	add	r3, r2
- 8002d60:	1c5a      	adds	r2, r3, #1
- 8002d62:	697b      	ldr	r3, [r7, #20]
- 8002d64:	629a      	str	r2, [r3, #40]	; 0x28
-  __ASM volatile ("cpsie i" : : : "memory");
- 8002d66:	b662      	cpsie	i
-}
- 8002d68:	bf00      	nop
-  /* Enable interrupts back */
-  __enable_irq();
-
-
-  /* Return function status */
-  return HAL_ETH_ERROR_NONE;
- 8002d6a:	2300      	movs	r3, #0
-}
- 8002d6c:	4618      	mov	r0, r3
- 8002d6e:	3734      	adds	r7, #52	; 0x34
- 8002d70:	46bd      	mov	sp, r7
- 8002d72:	f85d 7b04 	ldr.w	r7, [sp], #4
- 8002d76:	4770      	bx	lr
- 8002d78:	ffff8000 	.word	0xffff8000
-
-08002d7c <HAL_GPIO_Init>:
-  * @param  GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains
-  *         the configuration information for the specified GPIO peripheral.
-  * @retval None
-  */
-void HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init)
-{
- 8002d7c:	b480      	push	{r7}
- 8002d7e:	b089      	sub	sp, #36	; 0x24
- 8002d80:	af00      	add	r7, sp, #0
- 8002d82:	6078      	str	r0, [r7, #4]
- 8002d84:	6039      	str	r1, [r7, #0]
-  uint32_t position = 0x00U;
- 8002d86:	2300      	movs	r3, #0
- 8002d88:	61fb      	str	r3, [r7, #28]
-  EXTI_Core_TypeDef *EXTI_CurrentCPU;
-
-#if defined(DUAL_CORE) && defined(CORE_CM4)
-  EXTI_CurrentCPU = EXTI_D2; /* EXTI for CM4 CPU */
-#else
-  EXTI_CurrentCPU = EXTI_D1; /* EXTI for CM7 CPU */
- 8002d8a:	4b86      	ldr	r3, [pc, #536]	; (8002fa4 <HAL_GPIO_Init+0x228>)
- 8002d8c:	617b      	str	r3, [r7, #20]
-  assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
-  assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
-  assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
-
-  /* Configure the port pins */
-  while (((GPIO_Init->Pin) >> position) != 0x00U)
- 8002d8e:	e18c      	b.n	80030aa <HAL_GPIO_Init+0x32e>
-  {
-    /* Get current io position */
-    iocurrent = (GPIO_Init->Pin) & (1UL << position);
- 8002d90:	683b      	ldr	r3, [r7, #0]
- 8002d92:	681a      	ldr	r2, [r3, #0]
- 8002d94:	2101      	movs	r1, #1
- 8002d96:	69fb      	ldr	r3, [r7, #28]
- 8002d98:	fa01 f303 	lsl.w	r3, r1, r3
- 8002d9c:	4013      	ands	r3, r2
- 8002d9e:	613b      	str	r3, [r7, #16]
-
-    if (iocurrent != 0x00U)
- 8002da0:	693b      	ldr	r3, [r7, #16]
- 8002da2:	2b00      	cmp	r3, #0
- 8002da4:	f000 817e 	beq.w	80030a4 <HAL_GPIO_Init+0x328>
-    {
-      /*--------------------- GPIO Mode Configuration ------------------------*/
-      /* In case of Output or Alternate function mode selection */
-      if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF))
- 8002da8:	683b      	ldr	r3, [r7, #0]
- 8002daa:	685b      	ldr	r3, [r3, #4]
- 8002dac:	f003 0303 	and.w	r3, r3, #3
- 8002db0:	2b01      	cmp	r3, #1
- 8002db2:	d005      	beq.n	8002dc0 <HAL_GPIO_Init+0x44>
- 8002db4:	683b      	ldr	r3, [r7, #0]
- 8002db6:	685b      	ldr	r3, [r3, #4]
- 8002db8:	f003 0303 	and.w	r3, r3, #3
- 8002dbc:	2b02      	cmp	r3, #2
- 8002dbe:	d130      	bne.n	8002e22 <HAL_GPIO_Init+0xa6>
-      {
-        /* Check the Speed parameter */
-        assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
-
-        /* Configure the IO Speed */
-        temp = GPIOx->OSPEEDR;
- 8002dc0:	687b      	ldr	r3, [r7, #4]
- 8002dc2:	689b      	ldr	r3, [r3, #8]
- 8002dc4:	61bb      	str	r3, [r7, #24]
-        temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U));
- 8002dc6:	69fb      	ldr	r3, [r7, #28]
- 8002dc8:	005b      	lsls	r3, r3, #1
- 8002dca:	2203      	movs	r2, #3
- 8002dcc:	fa02 f303 	lsl.w	r3, r2, r3
- 8002dd0:	43db      	mvns	r3, r3
- 8002dd2:	69ba      	ldr	r2, [r7, #24]
- 8002dd4:	4013      	ands	r3, r2
- 8002dd6:	61bb      	str	r3, [r7, #24]
-        temp |= (GPIO_Init->Speed << (position * 2U));
- 8002dd8:	683b      	ldr	r3, [r7, #0]
- 8002dda:	68da      	ldr	r2, [r3, #12]
- 8002ddc:	69fb      	ldr	r3, [r7, #28]
- 8002dde:	005b      	lsls	r3, r3, #1
- 8002de0:	fa02 f303 	lsl.w	r3, r2, r3
- 8002de4:	69ba      	ldr	r2, [r7, #24]
- 8002de6:	4313      	orrs	r3, r2
- 8002de8:	61bb      	str	r3, [r7, #24]
-        GPIOx->OSPEEDR = temp;
- 8002dea:	687b      	ldr	r3, [r7, #4]
- 8002dec:	69ba      	ldr	r2, [r7, #24]
- 8002dee:	609a      	str	r2, [r3, #8]
-
-        /* Configure the IO Output Type */
-        temp = GPIOx->OTYPER;
- 8002df0:	687b      	ldr	r3, [r7, #4]
- 8002df2:	685b      	ldr	r3, [r3, #4]
- 8002df4:	61bb      	str	r3, [r7, #24]
-        temp &= ~(GPIO_OTYPER_OT0 << position) ;
- 8002df6:	2201      	movs	r2, #1
- 8002df8:	69fb      	ldr	r3, [r7, #28]
- 8002dfa:	fa02 f303 	lsl.w	r3, r2, r3
- 8002dfe:	43db      	mvns	r3, r3
- 8002e00:	69ba      	ldr	r2, [r7, #24]
- 8002e02:	4013      	ands	r3, r2
- 8002e04:	61bb      	str	r3, [r7, #24]
-        temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
- 8002e06:	683b      	ldr	r3, [r7, #0]
- 8002e08:	685b      	ldr	r3, [r3, #4]
- 8002e0a:	091b      	lsrs	r3, r3, #4
- 8002e0c:	f003 0201 	and.w	r2, r3, #1
- 8002e10:	69fb      	ldr	r3, [r7, #28]
- 8002e12:	fa02 f303 	lsl.w	r3, r2, r3
- 8002e16:	69ba      	ldr	r2, [r7, #24]
- 8002e18:	4313      	orrs	r3, r2
- 8002e1a:	61bb      	str	r3, [r7, #24]
-        GPIOx->OTYPER = temp;
- 8002e1c:	687b      	ldr	r3, [r7, #4]
- 8002e1e:	69ba      	ldr	r2, [r7, #24]
- 8002e20:	605a      	str	r2, [r3, #4]
-      }
-
-      if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG)
- 8002e22:	683b      	ldr	r3, [r7, #0]
- 8002e24:	685b      	ldr	r3, [r3, #4]
- 8002e26:	f003 0303 	and.w	r3, r3, #3
- 8002e2a:	2b03      	cmp	r3, #3
- 8002e2c:	d017      	beq.n	8002e5e <HAL_GPIO_Init+0xe2>
-      {
-       /* Check the Pull parameter */
-       assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
-
-      /* Activate the Pull-up or Pull down resistor for the current IO */
-      temp = GPIOx->PUPDR;
- 8002e2e:	687b      	ldr	r3, [r7, #4]
- 8002e30:	68db      	ldr	r3, [r3, #12]
- 8002e32:	61bb      	str	r3, [r7, #24]
-      temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U));
- 8002e34:	69fb      	ldr	r3, [r7, #28]
- 8002e36:	005b      	lsls	r3, r3, #1
- 8002e38:	2203      	movs	r2, #3
- 8002e3a:	fa02 f303 	lsl.w	r3, r2, r3
- 8002e3e:	43db      	mvns	r3, r3
- 8002e40:	69ba      	ldr	r2, [r7, #24]
- 8002e42:	4013      	ands	r3, r2
- 8002e44:	61bb      	str	r3, [r7, #24]
-      temp |= ((GPIO_Init->Pull) << (position * 2U));
- 8002e46:	683b      	ldr	r3, [r7, #0]
- 8002e48:	689a      	ldr	r2, [r3, #8]
- 8002e4a:	69fb      	ldr	r3, [r7, #28]
- 8002e4c:	005b      	lsls	r3, r3, #1
- 8002e4e:	fa02 f303 	lsl.w	r3, r2, r3
- 8002e52:	69ba      	ldr	r2, [r7, #24]
- 8002e54:	4313      	orrs	r3, r2
- 8002e56:	61bb      	str	r3, [r7, #24]
-      GPIOx->PUPDR = temp;
- 8002e58:	687b      	ldr	r3, [r7, #4]
- 8002e5a:	69ba      	ldr	r2, [r7, #24]
- 8002e5c:	60da      	str	r2, [r3, #12]
-      }
-
-      /* In case of Alternate function mode selection */
-      if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
- 8002e5e:	683b      	ldr	r3, [r7, #0]
- 8002e60:	685b      	ldr	r3, [r3, #4]
- 8002e62:	f003 0303 	and.w	r3, r3, #3
- 8002e66:	2b02      	cmp	r3, #2
- 8002e68:	d123      	bne.n	8002eb2 <HAL_GPIO_Init+0x136>
-        /* Check the Alternate function parameters */
-        assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
-        assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
-
-        /* Configure Alternate function mapped with the current IO */
-        temp = GPIOx->AFR[position >> 3U];
- 8002e6a:	69fb      	ldr	r3, [r7, #28]
- 8002e6c:	08da      	lsrs	r2, r3, #3
- 8002e6e:	687b      	ldr	r3, [r7, #4]
- 8002e70:	3208      	adds	r2, #8
- 8002e72:	f853 3022 	ldr.w	r3, [r3, r2, lsl #2]
- 8002e76:	61bb      	str	r3, [r7, #24]
-        temp &= ~(0xFU << ((position & 0x07U) * 4U));
- 8002e78:	69fb      	ldr	r3, [r7, #28]
- 8002e7a:	f003 0307 	and.w	r3, r3, #7
- 8002e7e:	009b      	lsls	r3, r3, #2
- 8002e80:	220f      	movs	r2, #15
- 8002e82:	fa02 f303 	lsl.w	r3, r2, r3
- 8002e86:	43db      	mvns	r3, r3
- 8002e88:	69ba      	ldr	r2, [r7, #24]
- 8002e8a:	4013      	ands	r3, r2
- 8002e8c:	61bb      	str	r3, [r7, #24]
-        temp |= ((GPIO_Init->Alternate) << ((position & 0x07U) * 4U));
- 8002e8e:	683b      	ldr	r3, [r7, #0]
- 8002e90:	691a      	ldr	r2, [r3, #16]
- 8002e92:	69fb      	ldr	r3, [r7, #28]
- 8002e94:	f003 0307 	and.w	r3, r3, #7
- 8002e98:	009b      	lsls	r3, r3, #2
- 8002e9a:	fa02 f303 	lsl.w	r3, r2, r3
- 8002e9e:	69ba      	ldr	r2, [r7, #24]
- 8002ea0:	4313      	orrs	r3, r2
- 8002ea2:	61bb      	str	r3, [r7, #24]
-        GPIOx->AFR[position >> 3U] = temp;
- 8002ea4:	69fb      	ldr	r3, [r7, #28]
- 8002ea6:	08da      	lsrs	r2, r3, #3
- 8002ea8:	687b      	ldr	r3, [r7, #4]
- 8002eaa:	3208      	adds	r2, #8
- 8002eac:	69b9      	ldr	r1, [r7, #24]
- 8002eae:	f843 1022 	str.w	r1, [r3, r2, lsl #2]
-      }
-
-      /* Configure IO Direction mode (Input, Output, Alternate or Analog) */
-      temp = GPIOx->MODER;
- 8002eb2:	687b      	ldr	r3, [r7, #4]
- 8002eb4:	681b      	ldr	r3, [r3, #0]
- 8002eb6:	61bb      	str	r3, [r7, #24]
-      temp &= ~(GPIO_MODER_MODE0 << (position * 2U));
- 8002eb8:	69fb      	ldr	r3, [r7, #28]
- 8002eba:	005b      	lsls	r3, r3, #1
- 8002ebc:	2203      	movs	r2, #3
- 8002ebe:	fa02 f303 	lsl.w	r3, r2, r3
- 8002ec2:	43db      	mvns	r3, r3
- 8002ec4:	69ba      	ldr	r2, [r7, #24]
- 8002ec6:	4013      	ands	r3, r2
- 8002ec8:	61bb      	str	r3, [r7, #24]
-      temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U));
- 8002eca:	683b      	ldr	r3, [r7, #0]
- 8002ecc:	685b      	ldr	r3, [r3, #4]
- 8002ece:	f003 0203 	and.w	r2, r3, #3
- 8002ed2:	69fb      	ldr	r3, [r7, #28]
- 8002ed4:	005b      	lsls	r3, r3, #1
- 8002ed6:	fa02 f303 	lsl.w	r3, r2, r3
- 8002eda:	69ba      	ldr	r2, [r7, #24]
- 8002edc:	4313      	orrs	r3, r2
- 8002ede:	61bb      	str	r3, [r7, #24]
-      GPIOx->MODER = temp;
- 8002ee0:	687b      	ldr	r3, [r7, #4]
- 8002ee2:	69ba      	ldr	r2, [r7, #24]
- 8002ee4:	601a      	str	r2, [r3, #0]
-
-      /*--------------------- EXTI Mode Configuration ------------------------*/
-      /* Configure the External Interrupt or event for the current IO */
-      if ((GPIO_Init->Mode & EXTI_MODE) != 0x00U)
- 8002ee6:	683b      	ldr	r3, [r7, #0]
- 8002ee8:	685b      	ldr	r3, [r3, #4]
- 8002eea:	f403 3340 	and.w	r3, r3, #196608	; 0x30000
- 8002eee:	2b00      	cmp	r3, #0
- 8002ef0:	f000 80d8 	beq.w	80030a4 <HAL_GPIO_Init+0x328>
-      {
-        /* Enable SYSCFG Clock */
-        __HAL_RCC_SYSCFG_CLK_ENABLE();
- 8002ef4:	4b2c      	ldr	r3, [pc, #176]	; (8002fa8 <HAL_GPIO_Init+0x22c>)
- 8002ef6:	f8d3 30f4 	ldr.w	r3, [r3, #244]	; 0xf4
- 8002efa:	4a2b      	ldr	r2, [pc, #172]	; (8002fa8 <HAL_GPIO_Init+0x22c>)
- 8002efc:	f043 0302 	orr.w	r3, r3, #2
- 8002f00:	f8c2 30f4 	str.w	r3, [r2, #244]	; 0xf4
- 8002f04:	4b28      	ldr	r3, [pc, #160]	; (8002fa8 <HAL_GPIO_Init+0x22c>)
- 8002f06:	f8d3 30f4 	ldr.w	r3, [r3, #244]	; 0xf4
- 8002f0a:	f003 0302 	and.w	r3, r3, #2
- 8002f0e:	60fb      	str	r3, [r7, #12]
- 8002f10:	68fb      	ldr	r3, [r7, #12]
-
-        temp = SYSCFG->EXTICR[position >> 2U];
- 8002f12:	4a26      	ldr	r2, [pc, #152]	; (8002fac <HAL_GPIO_Init+0x230>)
- 8002f14:	69fb      	ldr	r3, [r7, #28]
- 8002f16:	089b      	lsrs	r3, r3, #2
- 8002f18:	3302      	adds	r3, #2
- 8002f1a:	f852 3023 	ldr.w	r3, [r2, r3, lsl #2]
- 8002f1e:	61bb      	str	r3, [r7, #24]
-        temp &= ~(0x0FUL << (4U * (position & 0x03U)));
- 8002f20:	69fb      	ldr	r3, [r7, #28]
- 8002f22:	f003 0303 	and.w	r3, r3, #3
- 8002f26:	009b      	lsls	r3, r3, #2
- 8002f28:	220f      	movs	r2, #15
- 8002f2a:	fa02 f303 	lsl.w	r3, r2, r3
- 8002f2e:	43db      	mvns	r3, r3
- 8002f30:	69ba      	ldr	r2, [r7, #24]
- 8002f32:	4013      	ands	r3, r2
- 8002f34:	61bb      	str	r3, [r7, #24]
-        temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U)));
- 8002f36:	687b      	ldr	r3, [r7, #4]
- 8002f38:	4a1d      	ldr	r2, [pc, #116]	; (8002fb0 <HAL_GPIO_Init+0x234>)
- 8002f3a:	4293      	cmp	r3, r2
- 8002f3c:	d04a      	beq.n	8002fd4 <HAL_GPIO_Init+0x258>
- 8002f3e:	687b      	ldr	r3, [r7, #4]
- 8002f40:	4a1c      	ldr	r2, [pc, #112]	; (8002fb4 <HAL_GPIO_Init+0x238>)
- 8002f42:	4293      	cmp	r3, r2
- 8002f44:	d02b      	beq.n	8002f9e <HAL_GPIO_Init+0x222>
- 8002f46:	687b      	ldr	r3, [r7, #4]
- 8002f48:	4a1b      	ldr	r2, [pc, #108]	; (8002fb8 <HAL_GPIO_Init+0x23c>)
- 8002f4a:	4293      	cmp	r3, r2
- 8002f4c:	d025      	beq.n	8002f9a <HAL_GPIO_Init+0x21e>
- 8002f4e:	687b      	ldr	r3, [r7, #4]
- 8002f50:	4a1a      	ldr	r2, [pc, #104]	; (8002fbc <HAL_GPIO_Init+0x240>)
- 8002f52:	4293      	cmp	r3, r2
- 8002f54:	d01f      	beq.n	8002f96 <HAL_GPIO_Init+0x21a>
- 8002f56:	687b      	ldr	r3, [r7, #4]
- 8002f58:	4a19      	ldr	r2, [pc, #100]	; (8002fc0 <HAL_GPIO_Init+0x244>)
- 8002f5a:	4293      	cmp	r3, r2
- 8002f5c:	d019      	beq.n	8002f92 <HAL_GPIO_Init+0x216>
- 8002f5e:	687b      	ldr	r3, [r7, #4]
- 8002f60:	4a18      	ldr	r2, [pc, #96]	; (8002fc4 <HAL_GPIO_Init+0x248>)
- 8002f62:	4293      	cmp	r3, r2
- 8002f64:	d013      	beq.n	8002f8e <HAL_GPIO_Init+0x212>
- 8002f66:	687b      	ldr	r3, [r7, #4]
- 8002f68:	4a17      	ldr	r2, [pc, #92]	; (8002fc8 <HAL_GPIO_Init+0x24c>)
- 8002f6a:	4293      	cmp	r3, r2
- 8002f6c:	d00d      	beq.n	8002f8a <HAL_GPIO_Init+0x20e>
- 8002f6e:	687b      	ldr	r3, [r7, #4]
- 8002f70:	4a16      	ldr	r2, [pc, #88]	; (8002fcc <HAL_GPIO_Init+0x250>)
- 8002f72:	4293      	cmp	r3, r2
- 8002f74:	d007      	beq.n	8002f86 <HAL_GPIO_Init+0x20a>
- 8002f76:	687b      	ldr	r3, [r7, #4]
- 8002f78:	4a15      	ldr	r2, [pc, #84]	; (8002fd0 <HAL_GPIO_Init+0x254>)
- 8002f7a:	4293      	cmp	r3, r2
- 8002f7c:	d101      	bne.n	8002f82 <HAL_GPIO_Init+0x206>
- 8002f7e:	2309      	movs	r3, #9
- 8002f80:	e029      	b.n	8002fd6 <HAL_GPIO_Init+0x25a>
- 8002f82:	230a      	movs	r3, #10
- 8002f84:	e027      	b.n	8002fd6 <HAL_GPIO_Init+0x25a>
- 8002f86:	2307      	movs	r3, #7
- 8002f88:	e025      	b.n	8002fd6 <HAL_GPIO_Init+0x25a>
- 8002f8a:	2306      	movs	r3, #6
- 8002f8c:	e023      	b.n	8002fd6 <HAL_GPIO_Init+0x25a>
- 8002f8e:	2305      	movs	r3, #5
- 8002f90:	e021      	b.n	8002fd6 <HAL_GPIO_Init+0x25a>
- 8002f92:	2304      	movs	r3, #4
- 8002f94:	e01f      	b.n	8002fd6 <HAL_GPIO_Init+0x25a>
- 8002f96:	2303      	movs	r3, #3
- 8002f98:	e01d      	b.n	8002fd6 <HAL_GPIO_Init+0x25a>
- 8002f9a:	2302      	movs	r3, #2
- 8002f9c:	e01b      	b.n	8002fd6 <HAL_GPIO_Init+0x25a>
- 8002f9e:	2301      	movs	r3, #1
- 8002fa0:	e019      	b.n	8002fd6 <HAL_GPIO_Init+0x25a>
- 8002fa2:	bf00      	nop
- 8002fa4:	58000080 	.word	0x58000080
- 8002fa8:	58024400 	.word	0x58024400
- 8002fac:	58000400 	.word	0x58000400
- 8002fb0:	58020000 	.word	0x58020000
- 8002fb4:	58020400 	.word	0x58020400
- 8002fb8:	58020800 	.word	0x58020800
- 8002fbc:	58020c00 	.word	0x58020c00
- 8002fc0:	58021000 	.word	0x58021000
- 8002fc4:	58021400 	.word	0x58021400
- 8002fc8:	58021800 	.word	0x58021800
- 8002fcc:	58021c00 	.word	0x58021c00
- 8002fd0:	58022400 	.word	0x58022400
- 8002fd4:	2300      	movs	r3, #0
- 8002fd6:	69fa      	ldr	r2, [r7, #28]
- 8002fd8:	f002 0203 	and.w	r2, r2, #3
- 8002fdc:	0092      	lsls	r2, r2, #2
- 8002fde:	4093      	lsls	r3, r2
- 8002fe0:	69ba      	ldr	r2, [r7, #24]
- 8002fe2:	4313      	orrs	r3, r2
- 8002fe4:	61bb      	str	r3, [r7, #24]
-        SYSCFG->EXTICR[position >> 2U] = temp;
- 8002fe6:	4938      	ldr	r1, [pc, #224]	; (80030c8 <HAL_GPIO_Init+0x34c>)
- 8002fe8:	69fb      	ldr	r3, [r7, #28]
- 8002fea:	089b      	lsrs	r3, r3, #2
- 8002fec:	3302      	adds	r3, #2
- 8002fee:	69ba      	ldr	r2, [r7, #24]
- 8002ff0:	f841 2023 	str.w	r2, [r1, r3, lsl #2]
-
-        /* Clear Rising Falling edge configuration */
-        temp = EXTI->RTSR1;
- 8002ff4:	f04f 43b0 	mov.w	r3, #1476395008	; 0x58000000
- 8002ff8:	681b      	ldr	r3, [r3, #0]
- 8002ffa:	61bb      	str	r3, [r7, #24]
-        temp &= ~(iocurrent);
- 8002ffc:	693b      	ldr	r3, [r7, #16]
- 8002ffe:	43db      	mvns	r3, r3
- 8003000:	69ba      	ldr	r2, [r7, #24]
- 8003002:	4013      	ands	r3, r2
- 8003004:	61bb      	str	r3, [r7, #24]
-        if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U)
- 8003006:	683b      	ldr	r3, [r7, #0]
- 8003008:	685b      	ldr	r3, [r3, #4]
- 800300a:	f403 1380 	and.w	r3, r3, #1048576	; 0x100000
- 800300e:	2b00      	cmp	r3, #0
- 8003010:	d003      	beq.n	800301a <HAL_GPIO_Init+0x29e>
-        {
-          temp |= iocurrent;
- 8003012:	69ba      	ldr	r2, [r7, #24]
- 8003014:	693b      	ldr	r3, [r7, #16]
- 8003016:	4313      	orrs	r3, r2
- 8003018:	61bb      	str	r3, [r7, #24]
-        }
-        EXTI->RTSR1 = temp;
- 800301a:	f04f 42b0 	mov.w	r2, #1476395008	; 0x58000000
- 800301e:	69bb      	ldr	r3, [r7, #24]
- 8003020:	6013      	str	r3, [r2, #0]
-
-        temp = EXTI->FTSR1;
- 8003022:	f04f 43b0 	mov.w	r3, #1476395008	; 0x58000000
- 8003026:	685b      	ldr	r3, [r3, #4]
- 8003028:	61bb      	str	r3, [r7, #24]
-        temp &= ~(iocurrent);
- 800302a:	693b      	ldr	r3, [r7, #16]
- 800302c:	43db      	mvns	r3, r3
- 800302e:	69ba      	ldr	r2, [r7, #24]
- 8003030:	4013      	ands	r3, r2
- 8003032:	61bb      	str	r3, [r7, #24]
-        if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U)
- 8003034:	683b      	ldr	r3, [r7, #0]
- 8003036:	685b      	ldr	r3, [r3, #4]
- 8003038:	f403 1300 	and.w	r3, r3, #2097152	; 0x200000
- 800303c:	2b00      	cmp	r3, #0
- 800303e:	d003      	beq.n	8003048 <HAL_GPIO_Init+0x2cc>
-        {
-          temp |= iocurrent;
- 8003040:	69ba      	ldr	r2, [r7, #24]
- 8003042:	693b      	ldr	r3, [r7, #16]
- 8003044:	4313      	orrs	r3, r2
- 8003046:	61bb      	str	r3, [r7, #24]
-        }
-        EXTI->FTSR1 = temp;
- 8003048:	f04f 42b0 	mov.w	r2, #1476395008	; 0x58000000
- 800304c:	69bb      	ldr	r3, [r7, #24]
- 800304e:	6053      	str	r3, [r2, #4]
-
-        temp = EXTI_CurrentCPU->EMR1;
- 8003050:	697b      	ldr	r3, [r7, #20]
- 8003052:	685b      	ldr	r3, [r3, #4]
- 8003054:	61bb      	str	r3, [r7, #24]
-        temp &= ~(iocurrent);
- 8003056:	693b      	ldr	r3, [r7, #16]
- 8003058:	43db      	mvns	r3, r3
- 800305a:	69ba      	ldr	r2, [r7, #24]
- 800305c:	4013      	ands	r3, r2
- 800305e:	61bb      	str	r3, [r7, #24]
-        if ((GPIO_Init->Mode & EXTI_EVT) != 0x00U)
- 8003060:	683b      	ldr	r3, [r7, #0]
- 8003062:	685b      	ldr	r3, [r3, #4]
- 8003064:	f403 3300 	and.w	r3, r3, #131072	; 0x20000
- 8003068:	2b00      	cmp	r3, #0
- 800306a:	d003      	beq.n	8003074 <HAL_GPIO_Init+0x2f8>
-        {
-          temp |= iocurrent;
- 800306c:	69ba      	ldr	r2, [r7, #24]
- 800306e:	693b      	ldr	r3, [r7, #16]
- 8003070:	4313      	orrs	r3, r2
- 8003072:	61bb      	str	r3, [r7, #24]
-        }
-        EXTI_CurrentCPU->EMR1 = temp;
- 8003074:	697b      	ldr	r3, [r7, #20]
- 8003076:	69ba      	ldr	r2, [r7, #24]
- 8003078:	605a      	str	r2, [r3, #4]
-
-        /* Clear EXTI line configuration */
-        temp = EXTI_CurrentCPU->IMR1;
- 800307a:	697b      	ldr	r3, [r7, #20]
- 800307c:	681b      	ldr	r3, [r3, #0]
- 800307e:	61bb      	str	r3, [r7, #24]
-        temp &= ~(iocurrent);
- 8003080:	693b      	ldr	r3, [r7, #16]
- 8003082:	43db      	mvns	r3, r3
- 8003084:	69ba      	ldr	r2, [r7, #24]
- 8003086:	4013      	ands	r3, r2
- 8003088:	61bb      	str	r3, [r7, #24]
-        if ((GPIO_Init->Mode & EXTI_IT) != 0x00U)
- 800308a:	683b      	ldr	r3, [r7, #0]
- 800308c:	685b      	ldr	r3, [r3, #4]
- 800308e:	f403 3380 	and.w	r3, r3, #65536	; 0x10000
- 8003092:	2b00      	cmp	r3, #0
- 8003094:	d003      	beq.n	800309e <HAL_GPIO_Init+0x322>
-        {
-          temp |= iocurrent;
- 8003096:	69ba      	ldr	r2, [r7, #24]
- 8003098:	693b      	ldr	r3, [r7, #16]
- 800309a:	4313      	orrs	r3, r2
- 800309c:	61bb      	str	r3, [r7, #24]
-        }
-        EXTI_CurrentCPU->IMR1 = temp;
- 800309e:	697b      	ldr	r3, [r7, #20]
- 80030a0:	69ba      	ldr	r2, [r7, #24]
- 80030a2:	601a      	str	r2, [r3, #0]
-      }
-    }
-
-    position++;
- 80030a4:	69fb      	ldr	r3, [r7, #28]
- 80030a6:	3301      	adds	r3, #1
- 80030a8:	61fb      	str	r3, [r7, #28]
-  while (((GPIO_Init->Pin) >> position) != 0x00U)
- 80030aa:	683b      	ldr	r3, [r7, #0]
- 80030ac:	681a      	ldr	r2, [r3, #0]
- 80030ae:	69fb      	ldr	r3, [r7, #28]
- 80030b0:	fa22 f303 	lsr.w	r3, r2, r3
- 80030b4:	2b00      	cmp	r3, #0
- 80030b6:	f47f ae6b 	bne.w	8002d90 <HAL_GPIO_Init+0x14>
-  }
-}
- 80030ba:	bf00      	nop
- 80030bc:	bf00      	nop
- 80030be:	3724      	adds	r7, #36	; 0x24
- 80030c0:	46bd      	mov	sp, r7
- 80030c2:	f85d 7b04 	ldr.w	r7, [sp], #4
- 80030c6:	4770      	bx	lr
- 80030c8:	58000400 	.word	0x58000400
-
-080030cc <HAL_PWREx_ConfigSupply>:
-  *         PWR_SMPS_2V5_SUPPLIES_EXT are used only for lines that supports SMPS
-  *         regulator.
-  * @retval HAL status.
-  */
-HAL_StatusTypeDef HAL_PWREx_ConfigSupply (uint32_t SupplySource)
-{
- 80030cc:	b580      	push	{r7, lr}
- 80030ce:	b084      	sub	sp, #16
- 80030d0:	af00      	add	r7, sp, #0
- 80030d2:	6078      	str	r0, [r7, #4]
-  /* Check the parameters */
-  assert_param (IS_PWR_SUPPLY (SupplySource));
-
-  /* Check if supply source was configured */
-#if defined (PWR_FLAG_SCUEN)
-  if (__HAL_PWR_GET_FLAG (PWR_FLAG_SCUEN) == 0U)
- 80030d4:	4b19      	ldr	r3, [pc, #100]	; (800313c <HAL_PWREx_ConfigSupply+0x70>)
- 80030d6:	68db      	ldr	r3, [r3, #12]
- 80030d8:	f003 0304 	and.w	r3, r3, #4
- 80030dc:	2b04      	cmp	r3, #4
- 80030de:	d00a      	beq.n	80030f6 <HAL_PWREx_ConfigSupply+0x2a>
-#else
-  if ((PWR->CR3 & (PWR_CR3_SMPSEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS)) != (PWR_CR3_SMPSEN | PWR_CR3_LDOEN))
-#endif /* defined (PWR_FLAG_SCUEN) */
-  {
-    /* Check supply configuration */
-    if ((PWR->CR3 & PWR_SUPPLY_CONFIG_MASK) != SupplySource)
- 80030e0:	4b16      	ldr	r3, [pc, #88]	; (800313c <HAL_PWREx_ConfigSupply+0x70>)
- 80030e2:	68db      	ldr	r3, [r3, #12]
- 80030e4:	f003 0307 	and.w	r3, r3, #7
- 80030e8:	687a      	ldr	r2, [r7, #4]
- 80030ea:	429a      	cmp	r2, r3
- 80030ec:	d001      	beq.n	80030f2 <HAL_PWREx_ConfigSupply+0x26>
-    {
-      /* Supply configuration update locked, can't apply a new supply config */
-      return HAL_ERROR;
- 80030ee:	2301      	movs	r3, #1
- 80030f0:	e01f      	b.n	8003132 <HAL_PWREx_ConfigSupply+0x66>
-    else
-    {
-      /* Supply configuration update locked, but new supply configuration
-         matches with old supply configuration : nothing to do
-      */
-      return HAL_OK;
- 80030f2:	2300      	movs	r3, #0
- 80030f4:	e01d      	b.n	8003132 <HAL_PWREx_ConfigSupply+0x66>
-    }
-  }
-
-  /* Set the power supply configuration */
-  MODIFY_REG (PWR->CR3, PWR_SUPPLY_CONFIG_MASK, SupplySource);
- 80030f6:	4b11      	ldr	r3, [pc, #68]	; (800313c <HAL_PWREx_ConfigSupply+0x70>)
- 80030f8:	68db      	ldr	r3, [r3, #12]
- 80030fa:	f023 0207 	bic.w	r2, r3, #7
- 80030fe:	490f      	ldr	r1, [pc, #60]	; (800313c <HAL_PWREx_ConfigSupply+0x70>)
- 8003100:	687b      	ldr	r3, [r7, #4]
- 8003102:	4313      	orrs	r3, r2
- 8003104:	60cb      	str	r3, [r1, #12]
-
-  /* Get tick */
-  tickstart = HAL_GetTick ();
- 8003106:	f7fd ff81 	bl	800100c <HAL_GetTick>
- 800310a:	60f8      	str	r0, [r7, #12]
-
-  /* Wait till voltage level flag is set */
-  while (__HAL_PWR_GET_FLAG (PWR_FLAG_ACTVOSRDY) == 0U)
- 800310c:	e009      	b.n	8003122 <HAL_PWREx_ConfigSupply+0x56>
-  {
-    if ((HAL_GetTick () - tickstart) > PWR_FLAG_SETTING_DELAY)
- 800310e:	f7fd ff7d 	bl	800100c <HAL_GetTick>
- 8003112:	4602      	mov	r2, r0
- 8003114:	68fb      	ldr	r3, [r7, #12]
- 8003116:	1ad3      	subs	r3, r2, r3
- 8003118:	f5b3 7f7a 	cmp.w	r3, #1000	; 0x3e8
- 800311c:	d901      	bls.n	8003122 <HAL_PWREx_ConfigSupply+0x56>
-    {
-      return HAL_ERROR;
- 800311e:	2301      	movs	r3, #1
- 8003120:	e007      	b.n	8003132 <HAL_PWREx_ConfigSupply+0x66>
-  while (__HAL_PWR_GET_FLAG (PWR_FLAG_ACTVOSRDY) == 0U)
- 8003122:	4b06      	ldr	r3, [pc, #24]	; (800313c <HAL_PWREx_ConfigSupply+0x70>)
- 8003124:	685b      	ldr	r3, [r3, #4]
- 8003126:	f403 5300 	and.w	r3, r3, #8192	; 0x2000
- 800312a:	f5b3 5f00 	cmp.w	r3, #8192	; 0x2000
- 800312e:	d1ee      	bne.n	800310e <HAL_PWREx_ConfigSupply+0x42>
-      }
-    }
-  }
-#endif /* defined (SMPS) */
-
-  return HAL_OK;
- 8003130:	2300      	movs	r3, #0
-}
- 8003132:	4618      	mov	r0, r3
- 8003134:	3710      	adds	r7, #16
- 8003136:	46bd      	mov	sp, r7
- 8003138:	bd80      	pop	{r7, pc}
- 800313a:	bf00      	nop
- 800313c:	58024800 	.word	0x58024800
-
-08003140 <HAL_RCC_OscConfig>:
-  *         supported by this function. User should request a transition to HSE Off
-  *         first and then HSE On or HSE Bypass.
-  * @retval HAL status
-  */
-__weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
-{
- 8003140:	b580      	push	{r7, lr}
- 8003142:	b08c      	sub	sp, #48	; 0x30
- 8003144:	af00      	add	r7, sp, #0
- 8003146:	6078      	str	r0, [r7, #4]
-  uint32_t tickstart;
-  uint32_t temp1_pllckcfg, temp2_pllckcfg;
-
-  /* Check Null pointer */
-  if (RCC_OscInitStruct == NULL)
- 8003148:	687b      	ldr	r3, [r7, #4]
- 800314a:	2b00      	cmp	r3, #0
- 800314c:	d101      	bne.n	8003152 <HAL_RCC_OscConfig+0x12>
-  {
-    return HAL_ERROR;
- 800314e:	2301      	movs	r3, #1
- 8003150:	e3c8      	b.n	80038e4 <HAL_RCC_OscConfig+0x7a4>
-  }
-
-  /* Check the parameters */
-  assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
-  /*------------------------------- HSE Configuration ------------------------*/
-  if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
- 8003152:	687b      	ldr	r3, [r7, #4]
- 8003154:	681b      	ldr	r3, [r3, #0]
- 8003156:	f003 0301 	and.w	r3, r3, #1
- 800315a:	2b00      	cmp	r3, #0
- 800315c:	f000 8087 	beq.w	800326e <HAL_RCC_OscConfig+0x12e>
-  {
-    /* Check the parameters */
-    assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
-
-    const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();
- 8003160:	4b88      	ldr	r3, [pc, #544]	; (8003384 <HAL_RCC_OscConfig+0x244>)
- 8003162:	691b      	ldr	r3, [r3, #16]
- 8003164:	f003 0338 	and.w	r3, r3, #56	; 0x38
- 8003168:	62fb      	str	r3, [r7, #44]	; 0x2c
-    const uint32_t temp_pllckselr = RCC->PLLCKSELR;
- 800316a:	4b86      	ldr	r3, [pc, #536]	; (8003384 <HAL_RCC_OscConfig+0x244>)
- 800316c:	6a9b      	ldr	r3, [r3, #40]	; 0x28
- 800316e:	62bb      	str	r3, [r7, #40]	; 0x28
-    /* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */
-    if ((temp_sysclksrc == RCC_CFGR_SWS_HSE) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_HSE)))
- 8003170:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 8003172:	2b10      	cmp	r3, #16
- 8003174:	d007      	beq.n	8003186 <HAL_RCC_OscConfig+0x46>
- 8003176:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 8003178:	2b18      	cmp	r3, #24
- 800317a:	d110      	bne.n	800319e <HAL_RCC_OscConfig+0x5e>
- 800317c:	6abb      	ldr	r3, [r7, #40]	; 0x28
- 800317e:	f003 0303 	and.w	r3, r3, #3
- 8003182:	2b02      	cmp	r3, #2
- 8003184:	d10b      	bne.n	800319e <HAL_RCC_OscConfig+0x5e>
-    {
-      if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
- 8003186:	4b7f      	ldr	r3, [pc, #508]	; (8003384 <HAL_RCC_OscConfig+0x244>)
- 8003188:	681b      	ldr	r3, [r3, #0]
- 800318a:	f403 3300 	and.w	r3, r3, #131072	; 0x20000
- 800318e:	2b00      	cmp	r3, #0
- 8003190:	d06c      	beq.n	800326c <HAL_RCC_OscConfig+0x12c>
- 8003192:	687b      	ldr	r3, [r7, #4]
- 8003194:	685b      	ldr	r3, [r3, #4]
- 8003196:	2b00      	cmp	r3, #0
- 8003198:	d168      	bne.n	800326c <HAL_RCC_OscConfig+0x12c>
-      {
-        return HAL_ERROR;
- 800319a:	2301      	movs	r3, #1
- 800319c:	e3a2      	b.n	80038e4 <HAL_RCC_OscConfig+0x7a4>
-      }
-    }
-    else
-    {
-      /* Set the new HSE configuration ---------------------------------------*/
-      __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
- 800319e:	687b      	ldr	r3, [r7, #4]
- 80031a0:	685b      	ldr	r3, [r3, #4]
- 80031a2:	f5b3 3f80 	cmp.w	r3, #65536	; 0x10000
- 80031a6:	d106      	bne.n	80031b6 <HAL_RCC_OscConfig+0x76>
- 80031a8:	4b76      	ldr	r3, [pc, #472]	; (8003384 <HAL_RCC_OscConfig+0x244>)
- 80031aa:	681b      	ldr	r3, [r3, #0]
- 80031ac:	4a75      	ldr	r2, [pc, #468]	; (8003384 <HAL_RCC_OscConfig+0x244>)
- 80031ae:	f443 3380 	orr.w	r3, r3, #65536	; 0x10000
- 80031b2:	6013      	str	r3, [r2, #0]
- 80031b4:	e02e      	b.n	8003214 <HAL_RCC_OscConfig+0xd4>
- 80031b6:	687b      	ldr	r3, [r7, #4]
- 80031b8:	685b      	ldr	r3, [r3, #4]
- 80031ba:	2b00      	cmp	r3, #0
- 80031bc:	d10c      	bne.n	80031d8 <HAL_RCC_OscConfig+0x98>
- 80031be:	4b71      	ldr	r3, [pc, #452]	; (8003384 <HAL_RCC_OscConfig+0x244>)
- 80031c0:	681b      	ldr	r3, [r3, #0]
- 80031c2:	4a70      	ldr	r2, [pc, #448]	; (8003384 <HAL_RCC_OscConfig+0x244>)
- 80031c4:	f423 3380 	bic.w	r3, r3, #65536	; 0x10000
- 80031c8:	6013      	str	r3, [r2, #0]
- 80031ca:	4b6e      	ldr	r3, [pc, #440]	; (8003384 <HAL_RCC_OscConfig+0x244>)
- 80031cc:	681b      	ldr	r3, [r3, #0]
- 80031ce:	4a6d      	ldr	r2, [pc, #436]	; (8003384 <HAL_RCC_OscConfig+0x244>)
- 80031d0:	f423 2380 	bic.w	r3, r3, #262144	; 0x40000
- 80031d4:	6013      	str	r3, [r2, #0]
- 80031d6:	e01d      	b.n	8003214 <HAL_RCC_OscConfig+0xd4>
- 80031d8:	687b      	ldr	r3, [r7, #4]
- 80031da:	685b      	ldr	r3, [r3, #4]
- 80031dc:	f5b3 2fa0 	cmp.w	r3, #327680	; 0x50000
- 80031e0:	d10c      	bne.n	80031fc <HAL_RCC_OscConfig+0xbc>
- 80031e2:	4b68      	ldr	r3, [pc, #416]	; (8003384 <HAL_RCC_OscConfig+0x244>)
- 80031e4:	681b      	ldr	r3, [r3, #0]
- 80031e6:	4a67      	ldr	r2, [pc, #412]	; (8003384 <HAL_RCC_OscConfig+0x244>)
- 80031e8:	f443 2380 	orr.w	r3, r3, #262144	; 0x40000
- 80031ec:	6013      	str	r3, [r2, #0]
- 80031ee:	4b65      	ldr	r3, [pc, #404]	; (8003384 <HAL_RCC_OscConfig+0x244>)
- 80031f0:	681b      	ldr	r3, [r3, #0]
- 80031f2:	4a64      	ldr	r2, [pc, #400]	; (8003384 <HAL_RCC_OscConfig+0x244>)
- 80031f4:	f443 3380 	orr.w	r3, r3, #65536	; 0x10000
- 80031f8:	6013      	str	r3, [r2, #0]
- 80031fa:	e00b      	b.n	8003214 <HAL_RCC_OscConfig+0xd4>
- 80031fc:	4b61      	ldr	r3, [pc, #388]	; (8003384 <HAL_RCC_OscConfig+0x244>)
- 80031fe:	681b      	ldr	r3, [r3, #0]
- 8003200:	4a60      	ldr	r2, [pc, #384]	; (8003384 <HAL_RCC_OscConfig+0x244>)
- 8003202:	f423 3380 	bic.w	r3, r3, #65536	; 0x10000
- 8003206:	6013      	str	r3, [r2, #0]
- 8003208:	4b5e      	ldr	r3, [pc, #376]	; (8003384 <HAL_RCC_OscConfig+0x244>)
- 800320a:	681b      	ldr	r3, [r3, #0]
- 800320c:	4a5d      	ldr	r2, [pc, #372]	; (8003384 <HAL_RCC_OscConfig+0x244>)
- 800320e:	f423 2380 	bic.w	r3, r3, #262144	; 0x40000
- 8003212:	6013      	str	r3, [r2, #0]
-
-      /* Check the HSE State */
-      if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
- 8003214:	687b      	ldr	r3, [r7, #4]
- 8003216:	685b      	ldr	r3, [r3, #4]
- 8003218:	2b00      	cmp	r3, #0
- 800321a:	d013      	beq.n	8003244 <HAL_RCC_OscConfig+0x104>
-      {
-        /* Get Start Tick*/
-        tickstart = HAL_GetTick();
- 800321c:	f7fd fef6 	bl	800100c <HAL_GetTick>
- 8003220:	6278      	str	r0, [r7, #36]	; 0x24
-
-        /* Wait till HSE is ready */
-        while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U)
- 8003222:	e008      	b.n	8003236 <HAL_RCC_OscConfig+0xf6>
-        {
-          if ((uint32_t)(HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
- 8003224:	f7fd fef2 	bl	800100c <HAL_GetTick>
- 8003228:	4602      	mov	r2, r0
- 800322a:	6a7b      	ldr	r3, [r7, #36]	; 0x24
- 800322c:	1ad3      	subs	r3, r2, r3
- 800322e:	2b64      	cmp	r3, #100	; 0x64
- 8003230:	d901      	bls.n	8003236 <HAL_RCC_OscConfig+0xf6>
-          {
-            return HAL_TIMEOUT;
- 8003232:	2303      	movs	r3, #3
- 8003234:	e356      	b.n	80038e4 <HAL_RCC_OscConfig+0x7a4>
-        while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U)
- 8003236:	4b53      	ldr	r3, [pc, #332]	; (8003384 <HAL_RCC_OscConfig+0x244>)
- 8003238:	681b      	ldr	r3, [r3, #0]
- 800323a:	f403 3300 	and.w	r3, r3, #131072	; 0x20000
- 800323e:	2b00      	cmp	r3, #0
- 8003240:	d0f0      	beq.n	8003224 <HAL_RCC_OscConfig+0xe4>
- 8003242:	e014      	b.n	800326e <HAL_RCC_OscConfig+0x12e>
-        }
-      }
-      else
-      {
-        /* Get Start Tick*/
-        tickstart = HAL_GetTick();
- 8003244:	f7fd fee2 	bl	800100c <HAL_GetTick>
- 8003248:	6278      	str	r0, [r7, #36]	; 0x24
-
-        /* Wait till HSE is disabled */
-        while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U)
- 800324a:	e008      	b.n	800325e <HAL_RCC_OscConfig+0x11e>
-        {
-          if ((uint32_t)(HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
- 800324c:	f7fd fede 	bl	800100c <HAL_GetTick>
- 8003250:	4602      	mov	r2, r0
- 8003252:	6a7b      	ldr	r3, [r7, #36]	; 0x24
- 8003254:	1ad3      	subs	r3, r2, r3
- 8003256:	2b64      	cmp	r3, #100	; 0x64
- 8003258:	d901      	bls.n	800325e <HAL_RCC_OscConfig+0x11e>
-          {
-            return HAL_TIMEOUT;
- 800325a:	2303      	movs	r3, #3
- 800325c:	e342      	b.n	80038e4 <HAL_RCC_OscConfig+0x7a4>
-        while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U)
- 800325e:	4b49      	ldr	r3, [pc, #292]	; (8003384 <HAL_RCC_OscConfig+0x244>)
- 8003260:	681b      	ldr	r3, [r3, #0]
- 8003262:	f403 3300 	and.w	r3, r3, #131072	; 0x20000
- 8003266:	2b00      	cmp	r3, #0
- 8003268:	d1f0      	bne.n	800324c <HAL_RCC_OscConfig+0x10c>
- 800326a:	e000      	b.n	800326e <HAL_RCC_OscConfig+0x12e>
-      if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
- 800326c:	bf00      	nop
-        }
-      }
-    }
-  }
-  /*----------------------------- HSI Configuration --------------------------*/
-  if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
- 800326e:	687b      	ldr	r3, [r7, #4]
- 8003270:	681b      	ldr	r3, [r3, #0]
- 8003272:	f003 0302 	and.w	r3, r3, #2
- 8003276:	2b00      	cmp	r3, #0
- 8003278:	f000 808c 	beq.w	8003394 <HAL_RCC_OscConfig+0x254>
-    /* Check the parameters */
-    assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
-    assert_param(IS_RCC_HSICALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
-
-    /* When the HSI is used as system clock it will not be disabled */
-    const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();
- 800327c:	4b41      	ldr	r3, [pc, #260]	; (8003384 <HAL_RCC_OscConfig+0x244>)
- 800327e:	691b      	ldr	r3, [r3, #16]
- 8003280:	f003 0338 	and.w	r3, r3, #56	; 0x38
- 8003284:	623b      	str	r3, [r7, #32]
-    const uint32_t temp_pllckselr = RCC->PLLCKSELR;
- 8003286:	4b3f      	ldr	r3, [pc, #252]	; (8003384 <HAL_RCC_OscConfig+0x244>)
- 8003288:	6a9b      	ldr	r3, [r3, #40]	; 0x28
- 800328a:	61fb      	str	r3, [r7, #28]
-    if ((temp_sysclksrc == RCC_CFGR_SWS_HSI) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_HSI)))
- 800328c:	6a3b      	ldr	r3, [r7, #32]
- 800328e:	2b00      	cmp	r3, #0
- 8003290:	d007      	beq.n	80032a2 <HAL_RCC_OscConfig+0x162>
- 8003292:	6a3b      	ldr	r3, [r7, #32]
- 8003294:	2b18      	cmp	r3, #24
- 8003296:	d137      	bne.n	8003308 <HAL_RCC_OscConfig+0x1c8>
- 8003298:	69fb      	ldr	r3, [r7, #28]
- 800329a:	f003 0303 	and.w	r3, r3, #3
- 800329e:	2b00      	cmp	r3, #0
- 80032a0:	d132      	bne.n	8003308 <HAL_RCC_OscConfig+0x1c8>
-    {
-      /* When HSI is used as system clock it will not be disabled */
-      if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF))
- 80032a2:	4b38      	ldr	r3, [pc, #224]	; (8003384 <HAL_RCC_OscConfig+0x244>)
- 80032a4:	681b      	ldr	r3, [r3, #0]
- 80032a6:	f003 0304 	and.w	r3, r3, #4
- 80032aa:	2b00      	cmp	r3, #0
- 80032ac:	d005      	beq.n	80032ba <HAL_RCC_OscConfig+0x17a>
- 80032ae:	687b      	ldr	r3, [r7, #4]
- 80032b0:	68db      	ldr	r3, [r3, #12]
- 80032b2:	2b00      	cmp	r3, #0
- 80032b4:	d101      	bne.n	80032ba <HAL_RCC_OscConfig+0x17a>
-      {
-        return HAL_ERROR;
- 80032b6:	2301      	movs	r3, #1
- 80032b8:	e314      	b.n	80038e4 <HAL_RCC_OscConfig+0x7a4>
-      }
-      /* Otherwise, only HSI division and calibration are allowed */
-      else
-      {
-        /* Enable the Internal High Speed oscillator (HSI, HSIDIV2, HSIDIV4, or HSIDIV8) */
-        __HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIState);
- 80032ba:	4b32      	ldr	r3, [pc, #200]	; (8003384 <HAL_RCC_OscConfig+0x244>)
- 80032bc:	681b      	ldr	r3, [r3, #0]
- 80032be:	f023 0219 	bic.w	r2, r3, #25
- 80032c2:	687b      	ldr	r3, [r7, #4]
- 80032c4:	68db      	ldr	r3, [r3, #12]
- 80032c6:	492f      	ldr	r1, [pc, #188]	; (8003384 <HAL_RCC_OscConfig+0x244>)
- 80032c8:	4313      	orrs	r3, r2
- 80032ca:	600b      	str	r3, [r1, #0]
-
-        /* Get Start Tick*/
-        tickstart = HAL_GetTick();
- 80032cc:	f7fd fe9e 	bl	800100c <HAL_GetTick>
- 80032d0:	6278      	str	r0, [r7, #36]	; 0x24
-
-        /* Wait till HSI is ready */
-        while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U)
- 80032d2:	e008      	b.n	80032e6 <HAL_RCC_OscConfig+0x1a6>
-        {
-          if ((uint32_t)(HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
- 80032d4:	f7fd fe9a 	bl	800100c <HAL_GetTick>
- 80032d8:	4602      	mov	r2, r0
- 80032da:	6a7b      	ldr	r3, [r7, #36]	; 0x24
- 80032dc:	1ad3      	subs	r3, r2, r3
- 80032de:	2b02      	cmp	r3, #2
- 80032e0:	d901      	bls.n	80032e6 <HAL_RCC_OscConfig+0x1a6>
-          {
-            return HAL_TIMEOUT;
- 80032e2:	2303      	movs	r3, #3
- 80032e4:	e2fe      	b.n	80038e4 <HAL_RCC_OscConfig+0x7a4>
-        while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U)
- 80032e6:	4b27      	ldr	r3, [pc, #156]	; (8003384 <HAL_RCC_OscConfig+0x244>)
- 80032e8:	681b      	ldr	r3, [r3, #0]
- 80032ea:	f003 0304 	and.w	r3, r3, #4
- 80032ee:	2b00      	cmp	r3, #0
- 80032f0:	d0f0      	beq.n	80032d4 <HAL_RCC_OscConfig+0x194>
-          }
-        }
-        /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
-        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
- 80032f2:	4b24      	ldr	r3, [pc, #144]	; (8003384 <HAL_RCC_OscConfig+0x244>)
- 80032f4:	685b      	ldr	r3, [r3, #4]
- 80032f6:	f023 42fe 	bic.w	r2, r3, #2130706432	; 0x7f000000
- 80032fa:	687b      	ldr	r3, [r7, #4]
- 80032fc:	691b      	ldr	r3, [r3, #16]
- 80032fe:	061b      	lsls	r3, r3, #24
- 8003300:	4920      	ldr	r1, [pc, #128]	; (8003384 <HAL_RCC_OscConfig+0x244>)
- 8003302:	4313      	orrs	r3, r2
- 8003304:	604b      	str	r3, [r1, #4]
-      if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF))
- 8003306:	e045      	b.n	8003394 <HAL_RCC_OscConfig+0x254>
-    }
-
-    else
-    {
-      /* Check the HSI State */
-      if ((RCC_OscInitStruct->HSIState) != RCC_HSI_OFF)
- 8003308:	687b      	ldr	r3, [r7, #4]
- 800330a:	68db      	ldr	r3, [r3, #12]
- 800330c:	2b00      	cmp	r3, #0
- 800330e:	d026      	beq.n	800335e <HAL_RCC_OscConfig+0x21e>
-      {
-        /* Enable the Internal High Speed oscillator (HSI, HSIDIV2,HSIDIV4, or HSIDIV8) */
-        __HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIState);
- 8003310:	4b1c      	ldr	r3, [pc, #112]	; (8003384 <HAL_RCC_OscConfig+0x244>)
- 8003312:	681b      	ldr	r3, [r3, #0]
- 8003314:	f023 0219 	bic.w	r2, r3, #25
- 8003318:	687b      	ldr	r3, [r7, #4]
- 800331a:	68db      	ldr	r3, [r3, #12]
- 800331c:	4919      	ldr	r1, [pc, #100]	; (8003384 <HAL_RCC_OscConfig+0x244>)
- 800331e:	4313      	orrs	r3, r2
- 8003320:	600b      	str	r3, [r1, #0]
-
-        /* Get Start Tick*/
-        tickstart = HAL_GetTick();
- 8003322:	f7fd fe73 	bl	800100c <HAL_GetTick>
- 8003326:	6278      	str	r0, [r7, #36]	; 0x24
-
-        /* Wait till HSI is ready */
-        while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U)
- 8003328:	e008      	b.n	800333c <HAL_RCC_OscConfig+0x1fc>
-        {
-          if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
- 800332a:	f7fd fe6f 	bl	800100c <HAL_GetTick>
- 800332e:	4602      	mov	r2, r0
- 8003330:	6a7b      	ldr	r3, [r7, #36]	; 0x24
- 8003332:	1ad3      	subs	r3, r2, r3
- 8003334:	2b02      	cmp	r3, #2
- 8003336:	d901      	bls.n	800333c <HAL_RCC_OscConfig+0x1fc>
-          {
-            return HAL_TIMEOUT;
- 8003338:	2303      	movs	r3, #3
- 800333a:	e2d3      	b.n	80038e4 <HAL_RCC_OscConfig+0x7a4>
-        while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U)
- 800333c:	4b11      	ldr	r3, [pc, #68]	; (8003384 <HAL_RCC_OscConfig+0x244>)
- 800333e:	681b      	ldr	r3, [r3, #0]
- 8003340:	f003 0304 	and.w	r3, r3, #4
- 8003344:	2b00      	cmp	r3, #0
- 8003346:	d0f0      	beq.n	800332a <HAL_RCC_OscConfig+0x1ea>
-          }
-        }
-
-        /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
-        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
- 8003348:	4b0e      	ldr	r3, [pc, #56]	; (8003384 <HAL_RCC_OscConfig+0x244>)
- 800334a:	685b      	ldr	r3, [r3, #4]
- 800334c:	f023 42fe 	bic.w	r2, r3, #2130706432	; 0x7f000000
- 8003350:	687b      	ldr	r3, [r7, #4]
- 8003352:	691b      	ldr	r3, [r3, #16]
- 8003354:	061b      	lsls	r3, r3, #24
- 8003356:	490b      	ldr	r1, [pc, #44]	; (8003384 <HAL_RCC_OscConfig+0x244>)
- 8003358:	4313      	orrs	r3, r2
- 800335a:	604b      	str	r3, [r1, #4]
- 800335c:	e01a      	b.n	8003394 <HAL_RCC_OscConfig+0x254>
-      }
-      else
-      {
-        /* Disable the Internal High Speed oscillator (HSI). */
-        __HAL_RCC_HSI_DISABLE();
- 800335e:	4b09      	ldr	r3, [pc, #36]	; (8003384 <HAL_RCC_OscConfig+0x244>)
- 8003360:	681b      	ldr	r3, [r3, #0]
- 8003362:	4a08      	ldr	r2, [pc, #32]	; (8003384 <HAL_RCC_OscConfig+0x244>)
- 8003364:	f023 0301 	bic.w	r3, r3, #1
- 8003368:	6013      	str	r3, [r2, #0]
-
-        /* Get Start Tick*/
-        tickstart = HAL_GetTick();
- 800336a:	f7fd fe4f 	bl	800100c <HAL_GetTick>
- 800336e:	6278      	str	r0, [r7, #36]	; 0x24
-
-        /* Wait till HSI is disabled */
-        while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U)
- 8003370:	e00a      	b.n	8003388 <HAL_RCC_OscConfig+0x248>
-        {
-          if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
- 8003372:	f7fd fe4b 	bl	800100c <HAL_GetTick>
- 8003376:	4602      	mov	r2, r0
- 8003378:	6a7b      	ldr	r3, [r7, #36]	; 0x24
- 800337a:	1ad3      	subs	r3, r2, r3
- 800337c:	2b02      	cmp	r3, #2
- 800337e:	d903      	bls.n	8003388 <HAL_RCC_OscConfig+0x248>
-          {
-            return HAL_TIMEOUT;
- 8003380:	2303      	movs	r3, #3
- 8003382:	e2af      	b.n	80038e4 <HAL_RCC_OscConfig+0x7a4>
- 8003384:	58024400 	.word	0x58024400
-        while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U)
- 8003388:	4b96      	ldr	r3, [pc, #600]	; (80035e4 <HAL_RCC_OscConfig+0x4a4>)
- 800338a:	681b      	ldr	r3, [r3, #0]
- 800338c:	f003 0304 	and.w	r3, r3, #4
- 8003390:	2b00      	cmp	r3, #0
- 8003392:	d1ee      	bne.n	8003372 <HAL_RCC_OscConfig+0x232>
-        }
-      }
-    }
-  }
-  /*----------------------------- CSI Configuration --------------------------*/
-  if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_CSI) == RCC_OSCILLATORTYPE_CSI)
- 8003394:	687b      	ldr	r3, [r7, #4]
- 8003396:	681b      	ldr	r3, [r3, #0]
- 8003398:	f003 0310 	and.w	r3, r3, #16
- 800339c:	2b00      	cmp	r3, #0
- 800339e:	d06a      	beq.n	8003476 <HAL_RCC_OscConfig+0x336>
-    /* Check the parameters */
-    assert_param(IS_RCC_CSI(RCC_OscInitStruct->CSIState));
-    assert_param(IS_RCC_CSICALIBRATION_VALUE(RCC_OscInitStruct->CSICalibrationValue));
-
-    /* When the CSI is used as system clock it will not disabled */
-    const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();
- 80033a0:	4b90      	ldr	r3, [pc, #576]	; (80035e4 <HAL_RCC_OscConfig+0x4a4>)
- 80033a2:	691b      	ldr	r3, [r3, #16]
- 80033a4:	f003 0338 	and.w	r3, r3, #56	; 0x38
- 80033a8:	61bb      	str	r3, [r7, #24]
-    const uint32_t temp_pllckselr = RCC->PLLCKSELR;
- 80033aa:	4b8e      	ldr	r3, [pc, #568]	; (80035e4 <HAL_RCC_OscConfig+0x4a4>)
- 80033ac:	6a9b      	ldr	r3, [r3, #40]	; 0x28
- 80033ae:	617b      	str	r3, [r7, #20]
-    if ((temp_sysclksrc == RCC_CFGR_SWS_CSI) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_CSI)))
- 80033b0:	69bb      	ldr	r3, [r7, #24]
- 80033b2:	2b08      	cmp	r3, #8
- 80033b4:	d007      	beq.n	80033c6 <HAL_RCC_OscConfig+0x286>
- 80033b6:	69bb      	ldr	r3, [r7, #24]
- 80033b8:	2b18      	cmp	r3, #24
- 80033ba:	d11b      	bne.n	80033f4 <HAL_RCC_OscConfig+0x2b4>
- 80033bc:	697b      	ldr	r3, [r7, #20]
- 80033be:	f003 0303 	and.w	r3, r3, #3
- 80033c2:	2b01      	cmp	r3, #1
- 80033c4:	d116      	bne.n	80033f4 <HAL_RCC_OscConfig+0x2b4>
-    {
-      /* When CSI is used as system clock it will not disabled */
-      if ((__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) && (RCC_OscInitStruct->CSIState != RCC_CSI_ON))
- 80033c6:	4b87      	ldr	r3, [pc, #540]	; (80035e4 <HAL_RCC_OscConfig+0x4a4>)
- 80033c8:	681b      	ldr	r3, [r3, #0]
- 80033ca:	f403 7380 	and.w	r3, r3, #256	; 0x100
- 80033ce:	2b00      	cmp	r3, #0
- 80033d0:	d005      	beq.n	80033de <HAL_RCC_OscConfig+0x29e>
- 80033d2:	687b      	ldr	r3, [r7, #4]
- 80033d4:	69db      	ldr	r3, [r3, #28]
- 80033d6:	2b80      	cmp	r3, #128	; 0x80
- 80033d8:	d001      	beq.n	80033de <HAL_RCC_OscConfig+0x29e>
-      {
-        return HAL_ERROR;
- 80033da:	2301      	movs	r3, #1
- 80033dc:	e282      	b.n	80038e4 <HAL_RCC_OscConfig+0x7a4>
-      }
-      /* Otherwise, just the calibration is allowed */
-      else
-      {
-        /* Adjusts the Internal High Speed oscillator (CSI) calibration value.*/
-        __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->CSICalibrationValue);
- 80033de:	4b81      	ldr	r3, [pc, #516]	; (80035e4 <HAL_RCC_OscConfig+0x4a4>)
- 80033e0:	68db      	ldr	r3, [r3, #12]
- 80033e2:	f023 527c 	bic.w	r2, r3, #1056964608	; 0x3f000000
- 80033e6:	687b      	ldr	r3, [r7, #4]
- 80033e8:	6a1b      	ldr	r3, [r3, #32]
- 80033ea:	061b      	lsls	r3, r3, #24
- 80033ec:	497d      	ldr	r1, [pc, #500]	; (80035e4 <HAL_RCC_OscConfig+0x4a4>)
- 80033ee:	4313      	orrs	r3, r2
- 80033f0:	60cb      	str	r3, [r1, #12]
-      if ((__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) && (RCC_OscInitStruct->CSIState != RCC_CSI_ON))
- 80033f2:	e040      	b.n	8003476 <HAL_RCC_OscConfig+0x336>
-      }
-    }
-    else
-    {
-      /* Check the CSI State */
-      if ((RCC_OscInitStruct->CSIState) != RCC_CSI_OFF)
- 80033f4:	687b      	ldr	r3, [r7, #4]
- 80033f6:	69db      	ldr	r3, [r3, #28]
- 80033f8:	2b00      	cmp	r3, #0
- 80033fa:	d023      	beq.n	8003444 <HAL_RCC_OscConfig+0x304>
-      {
-        /* Enable the Internal High Speed oscillator (CSI). */
-        __HAL_RCC_CSI_ENABLE();
- 80033fc:	4b79      	ldr	r3, [pc, #484]	; (80035e4 <HAL_RCC_OscConfig+0x4a4>)
- 80033fe:	681b      	ldr	r3, [r3, #0]
- 8003400:	4a78      	ldr	r2, [pc, #480]	; (80035e4 <HAL_RCC_OscConfig+0x4a4>)
- 8003402:	f043 0380 	orr.w	r3, r3, #128	; 0x80
- 8003406:	6013      	str	r3, [r2, #0]
-
-        /* Get Start Tick*/
-        tickstart = HAL_GetTick();
- 8003408:	f7fd fe00 	bl	800100c <HAL_GetTick>
- 800340c:	6278      	str	r0, [r7, #36]	; 0x24
-
-        /* Wait till CSI is ready */
-        while (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) == 0U)
- 800340e:	e008      	b.n	8003422 <HAL_RCC_OscConfig+0x2e2>
-        {
-          if ((HAL_GetTick() - tickstart) > CSI_TIMEOUT_VALUE)
- 8003410:	f7fd fdfc 	bl	800100c <HAL_GetTick>
- 8003414:	4602      	mov	r2, r0
- 8003416:	6a7b      	ldr	r3, [r7, #36]	; 0x24
- 8003418:	1ad3      	subs	r3, r2, r3
- 800341a:	2b02      	cmp	r3, #2
- 800341c:	d901      	bls.n	8003422 <HAL_RCC_OscConfig+0x2e2>
-          {
-            return HAL_TIMEOUT;
- 800341e:	2303      	movs	r3, #3
- 8003420:	e260      	b.n	80038e4 <HAL_RCC_OscConfig+0x7a4>
-        while (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) == 0U)
- 8003422:	4b70      	ldr	r3, [pc, #448]	; (80035e4 <HAL_RCC_OscConfig+0x4a4>)
- 8003424:	681b      	ldr	r3, [r3, #0]
- 8003426:	f403 7380 	and.w	r3, r3, #256	; 0x100
- 800342a:	2b00      	cmp	r3, #0
- 800342c:	d0f0      	beq.n	8003410 <HAL_RCC_OscConfig+0x2d0>
-          }
-        }
-
-        /* Adjusts the Internal High Speed oscillator (CSI) calibration value.*/
-        __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->CSICalibrationValue);
- 800342e:	4b6d      	ldr	r3, [pc, #436]	; (80035e4 <HAL_RCC_OscConfig+0x4a4>)
- 8003430:	68db      	ldr	r3, [r3, #12]
- 8003432:	f023 527c 	bic.w	r2, r3, #1056964608	; 0x3f000000
- 8003436:	687b      	ldr	r3, [r7, #4]
- 8003438:	6a1b      	ldr	r3, [r3, #32]
- 800343a:	061b      	lsls	r3, r3, #24
- 800343c:	4969      	ldr	r1, [pc, #420]	; (80035e4 <HAL_RCC_OscConfig+0x4a4>)
- 800343e:	4313      	orrs	r3, r2
- 8003440:	60cb      	str	r3, [r1, #12]
- 8003442:	e018      	b.n	8003476 <HAL_RCC_OscConfig+0x336>
-      }
-      else
-      {
-        /* Disable the Internal High Speed oscillator (CSI). */
-        __HAL_RCC_CSI_DISABLE();
- 8003444:	4b67      	ldr	r3, [pc, #412]	; (80035e4 <HAL_RCC_OscConfig+0x4a4>)
- 8003446:	681b      	ldr	r3, [r3, #0]
- 8003448:	4a66      	ldr	r2, [pc, #408]	; (80035e4 <HAL_RCC_OscConfig+0x4a4>)
- 800344a:	f023 0380 	bic.w	r3, r3, #128	; 0x80
- 800344e:	6013      	str	r3, [r2, #0]
-
-        /* Get Start Tick*/
-        tickstart = HAL_GetTick();
- 8003450:	f7fd fddc 	bl	800100c <HAL_GetTick>
- 8003454:	6278      	str	r0, [r7, #36]	; 0x24
-
-        /* Wait till CSI is disabled */
-        while (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U)
- 8003456:	e008      	b.n	800346a <HAL_RCC_OscConfig+0x32a>
-        {
-          if ((HAL_GetTick() - tickstart) > CSI_TIMEOUT_VALUE)
- 8003458:	f7fd fdd8 	bl	800100c <HAL_GetTick>
- 800345c:	4602      	mov	r2, r0
- 800345e:	6a7b      	ldr	r3, [r7, #36]	; 0x24
- 8003460:	1ad3      	subs	r3, r2, r3
- 8003462:	2b02      	cmp	r3, #2
- 8003464:	d901      	bls.n	800346a <HAL_RCC_OscConfig+0x32a>
-          {
-            return HAL_TIMEOUT;
- 8003466:	2303      	movs	r3, #3
- 8003468:	e23c      	b.n	80038e4 <HAL_RCC_OscConfig+0x7a4>
-        while (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U)
- 800346a:	4b5e      	ldr	r3, [pc, #376]	; (80035e4 <HAL_RCC_OscConfig+0x4a4>)
- 800346c:	681b      	ldr	r3, [r3, #0]
- 800346e:	f403 7380 	and.w	r3, r3, #256	; 0x100
- 8003472:	2b00      	cmp	r3, #0
- 8003474:	d1f0      	bne.n	8003458 <HAL_RCC_OscConfig+0x318>
-        }
-      }
-    }
-  }
-  /*------------------------------ LSI Configuration -------------------------*/
-  if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
- 8003476:	687b      	ldr	r3, [r7, #4]
- 8003478:	681b      	ldr	r3, [r3, #0]
- 800347a:	f003 0308 	and.w	r3, r3, #8
- 800347e:	2b00      	cmp	r3, #0
- 8003480:	d036      	beq.n	80034f0 <HAL_RCC_OscConfig+0x3b0>
-  {
-    /* Check the parameters */
-    assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
-
-    /* Check the LSI State */
-    if ((RCC_OscInitStruct->LSIState) != RCC_LSI_OFF)
- 8003482:	687b      	ldr	r3, [r7, #4]
- 8003484:	695b      	ldr	r3, [r3, #20]
- 8003486:	2b00      	cmp	r3, #0
- 8003488:	d019      	beq.n	80034be <HAL_RCC_OscConfig+0x37e>
-    {
-      /* Enable the Internal Low Speed oscillator (LSI). */
-      __HAL_RCC_LSI_ENABLE();
- 800348a:	4b56      	ldr	r3, [pc, #344]	; (80035e4 <HAL_RCC_OscConfig+0x4a4>)
- 800348c:	6f5b      	ldr	r3, [r3, #116]	; 0x74
- 800348e:	4a55      	ldr	r2, [pc, #340]	; (80035e4 <HAL_RCC_OscConfig+0x4a4>)
- 8003490:	f043 0301 	orr.w	r3, r3, #1
- 8003494:	6753      	str	r3, [r2, #116]	; 0x74
-
-      /* Get Start Tick*/
-      tickstart = HAL_GetTick();
- 8003496:	f7fd fdb9 	bl	800100c <HAL_GetTick>
- 800349a:	6278      	str	r0, [r7, #36]	; 0x24
-
-      /* Wait till LSI is ready */
-      while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == 0U)
- 800349c:	e008      	b.n	80034b0 <HAL_RCC_OscConfig+0x370>
-      {
-        if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
- 800349e:	f7fd fdb5 	bl	800100c <HAL_GetTick>
- 80034a2:	4602      	mov	r2, r0
- 80034a4:	6a7b      	ldr	r3, [r7, #36]	; 0x24
- 80034a6:	1ad3      	subs	r3, r2, r3
- 80034a8:	2b02      	cmp	r3, #2
- 80034aa:	d901      	bls.n	80034b0 <HAL_RCC_OscConfig+0x370>
-        {
-          return HAL_TIMEOUT;
- 80034ac:	2303      	movs	r3, #3
- 80034ae:	e219      	b.n	80038e4 <HAL_RCC_OscConfig+0x7a4>
-      while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == 0U)
- 80034b0:	4b4c      	ldr	r3, [pc, #304]	; (80035e4 <HAL_RCC_OscConfig+0x4a4>)
- 80034b2:	6f5b      	ldr	r3, [r3, #116]	; 0x74
- 80034b4:	f003 0302 	and.w	r3, r3, #2
- 80034b8:	2b00      	cmp	r3, #0
- 80034ba:	d0f0      	beq.n	800349e <HAL_RCC_OscConfig+0x35e>
- 80034bc:	e018      	b.n	80034f0 <HAL_RCC_OscConfig+0x3b0>
-      }
-    }
-    else
-    {
-      /* Disable the Internal Low Speed oscillator (LSI). */
-      __HAL_RCC_LSI_DISABLE();
- 80034be:	4b49      	ldr	r3, [pc, #292]	; (80035e4 <HAL_RCC_OscConfig+0x4a4>)
- 80034c0:	6f5b      	ldr	r3, [r3, #116]	; 0x74
- 80034c2:	4a48      	ldr	r2, [pc, #288]	; (80035e4 <HAL_RCC_OscConfig+0x4a4>)
- 80034c4:	f023 0301 	bic.w	r3, r3, #1
- 80034c8:	6753      	str	r3, [r2, #116]	; 0x74
-
-      /* Get Start Tick*/
-      tickstart = HAL_GetTick();
- 80034ca:	f7fd fd9f 	bl	800100c <HAL_GetTick>
- 80034ce:	6278      	str	r0, [r7, #36]	; 0x24
-
-      /* Wait till LSI is ready */
-      while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != 0U)
- 80034d0:	e008      	b.n	80034e4 <HAL_RCC_OscConfig+0x3a4>
-      {
-        if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
- 80034d2:	f7fd fd9b 	bl	800100c <HAL_GetTick>
- 80034d6:	4602      	mov	r2, r0
- 80034d8:	6a7b      	ldr	r3, [r7, #36]	; 0x24
- 80034da:	1ad3      	subs	r3, r2, r3
- 80034dc:	2b02      	cmp	r3, #2
- 80034de:	d901      	bls.n	80034e4 <HAL_RCC_OscConfig+0x3a4>
-        {
-          return HAL_TIMEOUT;
- 80034e0:	2303      	movs	r3, #3
- 80034e2:	e1ff      	b.n	80038e4 <HAL_RCC_OscConfig+0x7a4>
-      while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != 0U)
- 80034e4:	4b3f      	ldr	r3, [pc, #252]	; (80035e4 <HAL_RCC_OscConfig+0x4a4>)
- 80034e6:	6f5b      	ldr	r3, [r3, #116]	; 0x74
- 80034e8:	f003 0302 	and.w	r3, r3, #2
- 80034ec:	2b00      	cmp	r3, #0
- 80034ee:	d1f0      	bne.n	80034d2 <HAL_RCC_OscConfig+0x392>
-      }
-    }
-  }
-
-  /*------------------------------ HSI48 Configuration -------------------------*/
-  if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48)
- 80034f0:	687b      	ldr	r3, [r7, #4]
- 80034f2:	681b      	ldr	r3, [r3, #0]
- 80034f4:	f003 0320 	and.w	r3, r3, #32
- 80034f8:	2b00      	cmp	r3, #0
- 80034fa:	d036      	beq.n	800356a <HAL_RCC_OscConfig+0x42a>
-  {
-    /* Check the parameters */
-    assert_param(IS_RCC_HSI48(RCC_OscInitStruct->HSI48State));
-
-    /* Check the HSI48 State */
-    if ((RCC_OscInitStruct->HSI48State) != RCC_HSI48_OFF)
- 80034fc:	687b      	ldr	r3, [r7, #4]
- 80034fe:	699b      	ldr	r3, [r3, #24]
- 8003500:	2b00      	cmp	r3, #0
- 8003502:	d019      	beq.n	8003538 <HAL_RCC_OscConfig+0x3f8>
-    {
-      /* Enable the Internal Low Speed oscillator (HSI48). */
-      __HAL_RCC_HSI48_ENABLE();
- 8003504:	4b37      	ldr	r3, [pc, #220]	; (80035e4 <HAL_RCC_OscConfig+0x4a4>)
- 8003506:	681b      	ldr	r3, [r3, #0]
- 8003508:	4a36      	ldr	r2, [pc, #216]	; (80035e4 <HAL_RCC_OscConfig+0x4a4>)
- 800350a:	f443 5380 	orr.w	r3, r3, #4096	; 0x1000
- 800350e:	6013      	str	r3, [r2, #0]
-
-      /* Get time-out */
-      tickstart = HAL_GetTick();
- 8003510:	f7fd fd7c 	bl	800100c <HAL_GetTick>
- 8003514:	6278      	str	r0, [r7, #36]	; 0x24
-
-      /* Wait till HSI48 is ready */
-      while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == 0U)
- 8003516:	e008      	b.n	800352a <HAL_RCC_OscConfig+0x3ea>
-      {
-        if ((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE)
- 8003518:	f7fd fd78 	bl	800100c <HAL_GetTick>
- 800351c:	4602      	mov	r2, r0
- 800351e:	6a7b      	ldr	r3, [r7, #36]	; 0x24
- 8003520:	1ad3      	subs	r3, r2, r3
- 8003522:	2b02      	cmp	r3, #2
- 8003524:	d901      	bls.n	800352a <HAL_RCC_OscConfig+0x3ea>
-        {
-          return HAL_TIMEOUT;
- 8003526:	2303      	movs	r3, #3
- 8003528:	e1dc      	b.n	80038e4 <HAL_RCC_OscConfig+0x7a4>
-      while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == 0U)
- 800352a:	4b2e      	ldr	r3, [pc, #184]	; (80035e4 <HAL_RCC_OscConfig+0x4a4>)
- 800352c:	681b      	ldr	r3, [r3, #0]
- 800352e:	f403 5300 	and.w	r3, r3, #8192	; 0x2000
- 8003532:	2b00      	cmp	r3, #0
- 8003534:	d0f0      	beq.n	8003518 <HAL_RCC_OscConfig+0x3d8>
- 8003536:	e018      	b.n	800356a <HAL_RCC_OscConfig+0x42a>
-      }
-    }
-    else
-    {
-      /* Disable the Internal Low Speed oscillator (HSI48). */
-      __HAL_RCC_HSI48_DISABLE();
- 8003538:	4b2a      	ldr	r3, [pc, #168]	; (80035e4 <HAL_RCC_OscConfig+0x4a4>)
- 800353a:	681b      	ldr	r3, [r3, #0]
- 800353c:	4a29      	ldr	r2, [pc, #164]	; (80035e4 <HAL_RCC_OscConfig+0x4a4>)
- 800353e:	f423 5380 	bic.w	r3, r3, #4096	; 0x1000
- 8003542:	6013      	str	r3, [r2, #0]
-
-      /* Get time-out */
-      tickstart = HAL_GetTick();
- 8003544:	f7fd fd62 	bl	800100c <HAL_GetTick>
- 8003548:	6278      	str	r0, [r7, #36]	; 0x24
-
-      /* Wait till HSI48 is ready */
-      while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != 0U)
- 800354a:	e008      	b.n	800355e <HAL_RCC_OscConfig+0x41e>
-      {
-        if ((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE)
- 800354c:	f7fd fd5e 	bl	800100c <HAL_GetTick>
- 8003550:	4602      	mov	r2, r0
- 8003552:	6a7b      	ldr	r3, [r7, #36]	; 0x24
- 8003554:	1ad3      	subs	r3, r2, r3
- 8003556:	2b02      	cmp	r3, #2
- 8003558:	d901      	bls.n	800355e <HAL_RCC_OscConfig+0x41e>
-        {
-          return HAL_TIMEOUT;
- 800355a:	2303      	movs	r3, #3
- 800355c:	e1c2      	b.n	80038e4 <HAL_RCC_OscConfig+0x7a4>
-      while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != 0U)
- 800355e:	4b21      	ldr	r3, [pc, #132]	; (80035e4 <HAL_RCC_OscConfig+0x4a4>)
- 8003560:	681b      	ldr	r3, [r3, #0]
- 8003562:	f403 5300 	and.w	r3, r3, #8192	; 0x2000
- 8003566:	2b00      	cmp	r3, #0
- 8003568:	d1f0      	bne.n	800354c <HAL_RCC_OscConfig+0x40c>
-        }
-      }
-    }
-  }
-  /*------------------------------ LSE Configuration -------------------------*/
-  if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
- 800356a:	687b      	ldr	r3, [r7, #4]
- 800356c:	681b      	ldr	r3, [r3, #0]
- 800356e:	f003 0304 	and.w	r3, r3, #4
- 8003572:	2b00      	cmp	r3, #0
- 8003574:	f000 8086 	beq.w	8003684 <HAL_RCC_OscConfig+0x544>
-  {
-    /* Check the parameters */
-    assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
-
-    /* Enable write access to Backup domain */
-    PWR->CR1 |= PWR_CR1_DBP;
- 8003578:	4b1b      	ldr	r3, [pc, #108]	; (80035e8 <HAL_RCC_OscConfig+0x4a8>)
- 800357a:	681b      	ldr	r3, [r3, #0]
- 800357c:	4a1a      	ldr	r2, [pc, #104]	; (80035e8 <HAL_RCC_OscConfig+0x4a8>)
- 800357e:	f443 7380 	orr.w	r3, r3, #256	; 0x100
- 8003582:	6013      	str	r3, [r2, #0]
-
-    /* Wait for Backup domain Write protection disable */
-    tickstart = HAL_GetTick();
- 8003584:	f7fd fd42 	bl	800100c <HAL_GetTick>
- 8003588:	6278      	str	r0, [r7, #36]	; 0x24
-
-    while ((PWR->CR1 & PWR_CR1_DBP) == 0U)
- 800358a:	e008      	b.n	800359e <HAL_RCC_OscConfig+0x45e>
-    {
-      if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
- 800358c:	f7fd fd3e 	bl	800100c <HAL_GetTick>
- 8003590:	4602      	mov	r2, r0
- 8003592:	6a7b      	ldr	r3, [r7, #36]	; 0x24
- 8003594:	1ad3      	subs	r3, r2, r3
- 8003596:	2b64      	cmp	r3, #100	; 0x64
- 8003598:	d901      	bls.n	800359e <HAL_RCC_OscConfig+0x45e>
-      {
-        return HAL_TIMEOUT;
- 800359a:	2303      	movs	r3, #3
- 800359c:	e1a2      	b.n	80038e4 <HAL_RCC_OscConfig+0x7a4>
-    while ((PWR->CR1 & PWR_CR1_DBP) == 0U)
- 800359e:	4b12      	ldr	r3, [pc, #72]	; (80035e8 <HAL_RCC_OscConfig+0x4a8>)
- 80035a0:	681b      	ldr	r3, [r3, #0]
- 80035a2:	f403 7380 	and.w	r3, r3, #256	; 0x100
- 80035a6:	2b00      	cmp	r3, #0
- 80035a8:	d0f0      	beq.n	800358c <HAL_RCC_OscConfig+0x44c>
-      }
-    }
-
-    /* Set the new LSE configuration -----------------------------------------*/
-    __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
- 80035aa:	687b      	ldr	r3, [r7, #4]
- 80035ac:	689b      	ldr	r3, [r3, #8]
- 80035ae:	2b01      	cmp	r3, #1
- 80035b0:	d106      	bne.n	80035c0 <HAL_RCC_OscConfig+0x480>
- 80035b2:	4b0c      	ldr	r3, [pc, #48]	; (80035e4 <HAL_RCC_OscConfig+0x4a4>)
- 80035b4:	6f1b      	ldr	r3, [r3, #112]	; 0x70
- 80035b6:	4a0b      	ldr	r2, [pc, #44]	; (80035e4 <HAL_RCC_OscConfig+0x4a4>)
- 80035b8:	f043 0301 	orr.w	r3, r3, #1
- 80035bc:	6713      	str	r3, [r2, #112]	; 0x70
- 80035be:	e032      	b.n	8003626 <HAL_RCC_OscConfig+0x4e6>
- 80035c0:	687b      	ldr	r3, [r7, #4]
- 80035c2:	689b      	ldr	r3, [r3, #8]
- 80035c4:	2b00      	cmp	r3, #0
- 80035c6:	d111      	bne.n	80035ec <HAL_RCC_OscConfig+0x4ac>
- 80035c8:	4b06      	ldr	r3, [pc, #24]	; (80035e4 <HAL_RCC_OscConfig+0x4a4>)
- 80035ca:	6f1b      	ldr	r3, [r3, #112]	; 0x70
- 80035cc:	4a05      	ldr	r2, [pc, #20]	; (80035e4 <HAL_RCC_OscConfig+0x4a4>)
- 80035ce:	f023 0301 	bic.w	r3, r3, #1
- 80035d2:	6713      	str	r3, [r2, #112]	; 0x70
- 80035d4:	4b03      	ldr	r3, [pc, #12]	; (80035e4 <HAL_RCC_OscConfig+0x4a4>)
- 80035d6:	6f1b      	ldr	r3, [r3, #112]	; 0x70
- 80035d8:	4a02      	ldr	r2, [pc, #8]	; (80035e4 <HAL_RCC_OscConfig+0x4a4>)
- 80035da:	f023 0304 	bic.w	r3, r3, #4
- 80035de:	6713      	str	r3, [r2, #112]	; 0x70
- 80035e0:	e021      	b.n	8003626 <HAL_RCC_OscConfig+0x4e6>
- 80035e2:	bf00      	nop
- 80035e4:	58024400 	.word	0x58024400
- 80035e8:	58024800 	.word	0x58024800
- 80035ec:	687b      	ldr	r3, [r7, #4]
- 80035ee:	689b      	ldr	r3, [r3, #8]
- 80035f0:	2b05      	cmp	r3, #5
- 80035f2:	d10c      	bne.n	800360e <HAL_RCC_OscConfig+0x4ce>
- 80035f4:	4b83      	ldr	r3, [pc, #524]	; (8003804 <HAL_RCC_OscConfig+0x6c4>)
- 80035f6:	6f1b      	ldr	r3, [r3, #112]	; 0x70
- 80035f8:	4a82      	ldr	r2, [pc, #520]	; (8003804 <HAL_RCC_OscConfig+0x6c4>)
- 80035fa:	f043 0304 	orr.w	r3, r3, #4
- 80035fe:	6713      	str	r3, [r2, #112]	; 0x70
- 8003600:	4b80      	ldr	r3, [pc, #512]	; (8003804 <HAL_RCC_OscConfig+0x6c4>)
- 8003602:	6f1b      	ldr	r3, [r3, #112]	; 0x70
- 8003604:	4a7f      	ldr	r2, [pc, #508]	; (8003804 <HAL_RCC_OscConfig+0x6c4>)
- 8003606:	f043 0301 	orr.w	r3, r3, #1
- 800360a:	6713      	str	r3, [r2, #112]	; 0x70
- 800360c:	e00b      	b.n	8003626 <HAL_RCC_OscConfig+0x4e6>
- 800360e:	4b7d      	ldr	r3, [pc, #500]	; (8003804 <HAL_RCC_OscConfig+0x6c4>)
- 8003610:	6f1b      	ldr	r3, [r3, #112]	; 0x70
- 8003612:	4a7c      	ldr	r2, [pc, #496]	; (8003804 <HAL_RCC_OscConfig+0x6c4>)
- 8003614:	f023 0301 	bic.w	r3, r3, #1
- 8003618:	6713      	str	r3, [r2, #112]	; 0x70
- 800361a:	4b7a      	ldr	r3, [pc, #488]	; (8003804 <HAL_RCC_OscConfig+0x6c4>)
- 800361c:	6f1b      	ldr	r3, [r3, #112]	; 0x70
- 800361e:	4a79      	ldr	r2, [pc, #484]	; (8003804 <HAL_RCC_OscConfig+0x6c4>)
- 8003620:	f023 0304 	bic.w	r3, r3, #4
- 8003624:	6713      	str	r3, [r2, #112]	; 0x70
-    /* Check the LSE State */
-    if ((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)
- 8003626:	687b      	ldr	r3, [r7, #4]
- 8003628:	689b      	ldr	r3, [r3, #8]
- 800362a:	2b00      	cmp	r3, #0
- 800362c:	d015      	beq.n	800365a <HAL_RCC_OscConfig+0x51a>
-    {
-      /* Get Start Tick*/
-      tickstart = HAL_GetTick();
- 800362e:	f7fd fced 	bl	800100c <HAL_GetTick>
- 8003632:	6278      	str	r0, [r7, #36]	; 0x24
-
-      /* Wait till LSE is ready */
-      while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U)
- 8003634:	e00a      	b.n	800364c <HAL_RCC_OscConfig+0x50c>
-      {
-        if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
- 8003636:	f7fd fce9 	bl	800100c <HAL_GetTick>
- 800363a:	4602      	mov	r2, r0
- 800363c:	6a7b      	ldr	r3, [r7, #36]	; 0x24
- 800363e:	1ad3      	subs	r3, r2, r3
- 8003640:	f241 3288 	movw	r2, #5000	; 0x1388
- 8003644:	4293      	cmp	r3, r2
- 8003646:	d901      	bls.n	800364c <HAL_RCC_OscConfig+0x50c>
-        {
-          return HAL_TIMEOUT;
- 8003648:	2303      	movs	r3, #3
- 800364a:	e14b      	b.n	80038e4 <HAL_RCC_OscConfig+0x7a4>
-      while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U)
- 800364c:	4b6d      	ldr	r3, [pc, #436]	; (8003804 <HAL_RCC_OscConfig+0x6c4>)
- 800364e:	6f1b      	ldr	r3, [r3, #112]	; 0x70
- 8003650:	f003 0302 	and.w	r3, r3, #2
- 8003654:	2b00      	cmp	r3, #0
- 8003656:	d0ee      	beq.n	8003636 <HAL_RCC_OscConfig+0x4f6>
- 8003658:	e014      	b.n	8003684 <HAL_RCC_OscConfig+0x544>
-      }
-    }
-    else
-    {
-      /* Get Start Tick*/
-      tickstart = HAL_GetTick();
- 800365a:	f7fd fcd7 	bl	800100c <HAL_GetTick>
- 800365e:	6278      	str	r0, [r7, #36]	; 0x24
-
-      /* Wait till LSE is disabled */
-      while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U)
- 8003660:	e00a      	b.n	8003678 <HAL_RCC_OscConfig+0x538>
-      {
-        if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
- 8003662:	f7fd fcd3 	bl	800100c <HAL_GetTick>
- 8003666:	4602      	mov	r2, r0
- 8003668:	6a7b      	ldr	r3, [r7, #36]	; 0x24
- 800366a:	1ad3      	subs	r3, r2, r3
- 800366c:	f241 3288 	movw	r2, #5000	; 0x1388
- 8003670:	4293      	cmp	r3, r2
- 8003672:	d901      	bls.n	8003678 <HAL_RCC_OscConfig+0x538>
-        {
-          return HAL_TIMEOUT;
- 8003674:	2303      	movs	r3, #3
- 8003676:	e135      	b.n	80038e4 <HAL_RCC_OscConfig+0x7a4>
-      while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U)
- 8003678:	4b62      	ldr	r3, [pc, #392]	; (8003804 <HAL_RCC_OscConfig+0x6c4>)
- 800367a:	6f1b      	ldr	r3, [r3, #112]	; 0x70
- 800367c:	f003 0302 	and.w	r3, r3, #2
- 8003680:	2b00      	cmp	r3, #0
- 8003682:	d1ee      	bne.n	8003662 <HAL_RCC_OscConfig+0x522>
-    }
-  }
-  /*-------------------------------- PLL Configuration -----------------------*/
-  /* Check the parameters */
-  assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
-  if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
- 8003684:	687b      	ldr	r3, [r7, #4]
- 8003686:	6a5b      	ldr	r3, [r3, #36]	; 0x24
- 8003688:	2b00      	cmp	r3, #0
- 800368a:	f000 812a 	beq.w	80038e2 <HAL_RCC_OscConfig+0x7a2>
-  {
-    /* Check if the PLL is used as system clock or not */
-    if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL1)
- 800368e:	4b5d      	ldr	r3, [pc, #372]	; (8003804 <HAL_RCC_OscConfig+0x6c4>)
- 8003690:	691b      	ldr	r3, [r3, #16]
- 8003692:	f003 0338 	and.w	r3, r3, #56	; 0x38
- 8003696:	2b18      	cmp	r3, #24
- 8003698:	f000 80ba 	beq.w	8003810 <HAL_RCC_OscConfig+0x6d0>
-    {
-      if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
- 800369c:	687b      	ldr	r3, [r7, #4]
- 800369e:	6a5b      	ldr	r3, [r3, #36]	; 0x24
- 80036a0:	2b02      	cmp	r3, #2
- 80036a2:	f040 8095 	bne.w	80037d0 <HAL_RCC_OscConfig+0x690>
-        assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
-        assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR));
-        assert_param(IS_RCC_PLLFRACN_VALUE(RCC_OscInitStruct->PLL.PLLFRACN));
-
-        /* Disable the main PLL. */
-        __HAL_RCC_PLL_DISABLE();
- 80036a6:	4b57      	ldr	r3, [pc, #348]	; (8003804 <HAL_RCC_OscConfig+0x6c4>)
- 80036a8:	681b      	ldr	r3, [r3, #0]
- 80036aa:	4a56      	ldr	r2, [pc, #344]	; (8003804 <HAL_RCC_OscConfig+0x6c4>)
- 80036ac:	f023 7380 	bic.w	r3, r3, #16777216	; 0x1000000
- 80036b0:	6013      	str	r3, [r2, #0]
-
-        /* Get Start Tick*/
-        tickstart = HAL_GetTick();
- 80036b2:	f7fd fcab 	bl	800100c <HAL_GetTick>
- 80036b6:	6278      	str	r0, [r7, #36]	; 0x24
-
-        /* Wait till PLL is disabled */
-        while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U)
- 80036b8:	e008      	b.n	80036cc <HAL_RCC_OscConfig+0x58c>
-        {
-          if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
- 80036ba:	f7fd fca7 	bl	800100c <HAL_GetTick>
- 80036be:	4602      	mov	r2, r0
- 80036c0:	6a7b      	ldr	r3, [r7, #36]	; 0x24
- 80036c2:	1ad3      	subs	r3, r2, r3
- 80036c4:	2b02      	cmp	r3, #2
- 80036c6:	d901      	bls.n	80036cc <HAL_RCC_OscConfig+0x58c>
-          {
-            return HAL_TIMEOUT;
- 80036c8:	2303      	movs	r3, #3
- 80036ca:	e10b      	b.n	80038e4 <HAL_RCC_OscConfig+0x7a4>
-        while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U)
- 80036cc:	4b4d      	ldr	r3, [pc, #308]	; (8003804 <HAL_RCC_OscConfig+0x6c4>)
- 80036ce:	681b      	ldr	r3, [r3, #0]
- 80036d0:	f003 7300 	and.w	r3, r3, #33554432	; 0x2000000
- 80036d4:	2b00      	cmp	r3, #0
- 80036d6:	d1f0      	bne.n	80036ba <HAL_RCC_OscConfig+0x57a>
-          }
-        }
-
-        /* Configure the main PLL clock source, multiplication and division factors. */
-        __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
- 80036d8:	4b4a      	ldr	r3, [pc, #296]	; (8003804 <HAL_RCC_OscConfig+0x6c4>)
- 80036da:	6a9a      	ldr	r2, [r3, #40]	; 0x28
- 80036dc:	4b4a      	ldr	r3, [pc, #296]	; (8003808 <HAL_RCC_OscConfig+0x6c8>)
- 80036de:	4013      	ands	r3, r2
- 80036e0:	687a      	ldr	r2, [r7, #4]
- 80036e2:	6a91      	ldr	r1, [r2, #40]	; 0x28
- 80036e4:	687a      	ldr	r2, [r7, #4]
- 80036e6:	6ad2      	ldr	r2, [r2, #44]	; 0x2c
- 80036e8:	0112      	lsls	r2, r2, #4
- 80036ea:	430a      	orrs	r2, r1
- 80036ec:	4945      	ldr	r1, [pc, #276]	; (8003804 <HAL_RCC_OscConfig+0x6c4>)
- 80036ee:	4313      	orrs	r3, r2
- 80036f0:	628b      	str	r3, [r1, #40]	; 0x28
- 80036f2:	687b      	ldr	r3, [r7, #4]
- 80036f4:	6b1b      	ldr	r3, [r3, #48]	; 0x30
- 80036f6:	3b01      	subs	r3, #1
- 80036f8:	f3c3 0208 	ubfx	r2, r3, #0, #9
- 80036fc:	687b      	ldr	r3, [r7, #4]
- 80036fe:	6b5b      	ldr	r3, [r3, #52]	; 0x34
- 8003700:	3b01      	subs	r3, #1
- 8003702:	025b      	lsls	r3, r3, #9
- 8003704:	b29b      	uxth	r3, r3
- 8003706:	431a      	orrs	r2, r3
- 8003708:	687b      	ldr	r3, [r7, #4]
- 800370a:	6b9b      	ldr	r3, [r3, #56]	; 0x38
- 800370c:	3b01      	subs	r3, #1
- 800370e:	041b      	lsls	r3, r3, #16
- 8003710:	f403 03fe 	and.w	r3, r3, #8323072	; 0x7f0000
- 8003714:	431a      	orrs	r2, r3
- 8003716:	687b      	ldr	r3, [r7, #4]
- 8003718:	6bdb      	ldr	r3, [r3, #60]	; 0x3c
- 800371a:	3b01      	subs	r3, #1
- 800371c:	061b      	lsls	r3, r3, #24
- 800371e:	f003 43fe 	and.w	r3, r3, #2130706432	; 0x7f000000
- 8003722:	4938      	ldr	r1, [pc, #224]	; (8003804 <HAL_RCC_OscConfig+0x6c4>)
- 8003724:	4313      	orrs	r3, r2
- 8003726:	630b      	str	r3, [r1, #48]	; 0x30
-                             RCC_OscInitStruct->PLL.PLLP,
-                             RCC_OscInitStruct->PLL.PLLQ,
-                             RCC_OscInitStruct->PLL.PLLR);
-
-        /* Disable PLLFRACN . */
-        __HAL_RCC_PLLFRACN_DISABLE();
- 8003728:	4b36      	ldr	r3, [pc, #216]	; (8003804 <HAL_RCC_OscConfig+0x6c4>)
- 800372a:	6adb      	ldr	r3, [r3, #44]	; 0x2c
- 800372c:	4a35      	ldr	r2, [pc, #212]	; (8003804 <HAL_RCC_OscConfig+0x6c4>)
- 800372e:	f023 0301 	bic.w	r3, r3, #1
- 8003732:	62d3      	str	r3, [r2, #44]	; 0x2c
-
-        /* Configure PLL PLL1FRACN */
-        __HAL_RCC_PLLFRACN_CONFIG(RCC_OscInitStruct->PLL.PLLFRACN);
- 8003734:	4b33      	ldr	r3, [pc, #204]	; (8003804 <HAL_RCC_OscConfig+0x6c4>)
- 8003736:	6b5a      	ldr	r2, [r3, #52]	; 0x34
- 8003738:	4b34      	ldr	r3, [pc, #208]	; (800380c <HAL_RCC_OscConfig+0x6cc>)
- 800373a:	4013      	ands	r3, r2
- 800373c:	687a      	ldr	r2, [r7, #4]
- 800373e:	6c92      	ldr	r2, [r2, #72]	; 0x48
- 8003740:	00d2      	lsls	r2, r2, #3
- 8003742:	4930      	ldr	r1, [pc, #192]	; (8003804 <HAL_RCC_OscConfig+0x6c4>)
- 8003744:	4313      	orrs	r3, r2
- 8003746:	634b      	str	r3, [r1, #52]	; 0x34
-
-        /* Select PLL1 input reference frequency range: VCI */
-        __HAL_RCC_PLL_VCIRANGE(RCC_OscInitStruct->PLL.PLLRGE) ;
- 8003748:	4b2e      	ldr	r3, [pc, #184]	; (8003804 <HAL_RCC_OscConfig+0x6c4>)
- 800374a:	6adb      	ldr	r3, [r3, #44]	; 0x2c
- 800374c:	f023 020c 	bic.w	r2, r3, #12
- 8003750:	687b      	ldr	r3, [r7, #4]
- 8003752:	6c1b      	ldr	r3, [r3, #64]	; 0x40
- 8003754:	492b      	ldr	r1, [pc, #172]	; (8003804 <HAL_RCC_OscConfig+0x6c4>)
- 8003756:	4313      	orrs	r3, r2
- 8003758:	62cb      	str	r3, [r1, #44]	; 0x2c
-
-        /* Select PLL1 output frequency range : VCO */
-        __HAL_RCC_PLL_VCORANGE(RCC_OscInitStruct->PLL.PLLVCOSEL) ;
- 800375a:	4b2a      	ldr	r3, [pc, #168]	; (8003804 <HAL_RCC_OscConfig+0x6c4>)
- 800375c:	6adb      	ldr	r3, [r3, #44]	; 0x2c
- 800375e:	f023 0202 	bic.w	r2, r3, #2
- 8003762:	687b      	ldr	r3, [r7, #4]
- 8003764:	6c5b      	ldr	r3, [r3, #68]	; 0x44
- 8003766:	4927      	ldr	r1, [pc, #156]	; (8003804 <HAL_RCC_OscConfig+0x6c4>)
- 8003768:	4313      	orrs	r3, r2
- 800376a:	62cb      	str	r3, [r1, #44]	; 0x2c
-
-        /* Enable PLL System Clock output. */
-        __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVP);
- 800376c:	4b25      	ldr	r3, [pc, #148]	; (8003804 <HAL_RCC_OscConfig+0x6c4>)
- 800376e:	6adb      	ldr	r3, [r3, #44]	; 0x2c
- 8003770:	4a24      	ldr	r2, [pc, #144]	; (8003804 <HAL_RCC_OscConfig+0x6c4>)
- 8003772:	f443 3380 	orr.w	r3, r3, #65536	; 0x10000
- 8003776:	62d3      	str	r3, [r2, #44]	; 0x2c
-
-        /* Enable PLL1Q Clock output. */
-        __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
- 8003778:	4b22      	ldr	r3, [pc, #136]	; (8003804 <HAL_RCC_OscConfig+0x6c4>)
- 800377a:	6adb      	ldr	r3, [r3, #44]	; 0x2c
- 800377c:	4a21      	ldr	r2, [pc, #132]	; (8003804 <HAL_RCC_OscConfig+0x6c4>)
- 800377e:	f443 3300 	orr.w	r3, r3, #131072	; 0x20000
- 8003782:	62d3      	str	r3, [r2, #44]	; 0x2c
-
-        /* Enable PLL1R  Clock output. */
-        __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVR);
- 8003784:	4b1f      	ldr	r3, [pc, #124]	; (8003804 <HAL_RCC_OscConfig+0x6c4>)
- 8003786:	6adb      	ldr	r3, [r3, #44]	; 0x2c
- 8003788:	4a1e      	ldr	r2, [pc, #120]	; (8003804 <HAL_RCC_OscConfig+0x6c4>)
- 800378a:	f443 2380 	orr.w	r3, r3, #262144	; 0x40000
- 800378e:	62d3      	str	r3, [r2, #44]	; 0x2c
-
-        /* Enable PLL1FRACN . */
-        __HAL_RCC_PLLFRACN_ENABLE();
- 8003790:	4b1c      	ldr	r3, [pc, #112]	; (8003804 <HAL_RCC_OscConfig+0x6c4>)
- 8003792:	6adb      	ldr	r3, [r3, #44]	; 0x2c
- 8003794:	4a1b      	ldr	r2, [pc, #108]	; (8003804 <HAL_RCC_OscConfig+0x6c4>)
- 8003796:	f043 0301 	orr.w	r3, r3, #1
- 800379a:	62d3      	str	r3, [r2, #44]	; 0x2c
-
-        /* Enable the main PLL. */
-        __HAL_RCC_PLL_ENABLE();
- 800379c:	4b19      	ldr	r3, [pc, #100]	; (8003804 <HAL_RCC_OscConfig+0x6c4>)
- 800379e:	681b      	ldr	r3, [r3, #0]
- 80037a0:	4a18      	ldr	r2, [pc, #96]	; (8003804 <HAL_RCC_OscConfig+0x6c4>)
- 80037a2:	f043 7380 	orr.w	r3, r3, #16777216	; 0x1000000
- 80037a6:	6013      	str	r3, [r2, #0]
-
-        /* Get Start Tick*/
-        tickstart = HAL_GetTick();
- 80037a8:	f7fd fc30 	bl	800100c <HAL_GetTick>
- 80037ac:	6278      	str	r0, [r7, #36]	; 0x24
-
-        /* Wait till PLL is ready */
-        while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U)
- 80037ae:	e008      	b.n	80037c2 <HAL_RCC_OscConfig+0x682>
-        {
-          if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
- 80037b0:	f7fd fc2c 	bl	800100c <HAL_GetTick>
- 80037b4:	4602      	mov	r2, r0
- 80037b6:	6a7b      	ldr	r3, [r7, #36]	; 0x24
- 80037b8:	1ad3      	subs	r3, r2, r3
- 80037ba:	2b02      	cmp	r3, #2
- 80037bc:	d901      	bls.n	80037c2 <HAL_RCC_OscConfig+0x682>
-          {
-            return HAL_TIMEOUT;
- 80037be:	2303      	movs	r3, #3
- 80037c0:	e090      	b.n	80038e4 <HAL_RCC_OscConfig+0x7a4>
-        while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U)
- 80037c2:	4b10      	ldr	r3, [pc, #64]	; (8003804 <HAL_RCC_OscConfig+0x6c4>)
- 80037c4:	681b      	ldr	r3, [r3, #0]
- 80037c6:	f003 7300 	and.w	r3, r3, #33554432	; 0x2000000
- 80037ca:	2b00      	cmp	r3, #0
- 80037cc:	d0f0      	beq.n	80037b0 <HAL_RCC_OscConfig+0x670>
- 80037ce:	e088      	b.n	80038e2 <HAL_RCC_OscConfig+0x7a2>
-        }
-      }
-      else
-      {
-        /* Disable the main PLL. */
-        __HAL_RCC_PLL_DISABLE();
- 80037d0:	4b0c      	ldr	r3, [pc, #48]	; (8003804 <HAL_RCC_OscConfig+0x6c4>)
- 80037d2:	681b      	ldr	r3, [r3, #0]
- 80037d4:	4a0b      	ldr	r2, [pc, #44]	; (8003804 <HAL_RCC_OscConfig+0x6c4>)
- 80037d6:	f023 7380 	bic.w	r3, r3, #16777216	; 0x1000000
- 80037da:	6013      	str	r3, [r2, #0]
-
-        /* Get Start Tick*/
-        tickstart = HAL_GetTick();
- 80037dc:	f7fd fc16 	bl	800100c <HAL_GetTick>
- 80037e0:	6278      	str	r0, [r7, #36]	; 0x24
-
-        /* Wait till PLL is disabled */
-        while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U)
- 80037e2:	e008      	b.n	80037f6 <HAL_RCC_OscConfig+0x6b6>
-        {
-          if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
- 80037e4:	f7fd fc12 	bl	800100c <HAL_GetTick>
- 80037e8:	4602      	mov	r2, r0
- 80037ea:	6a7b      	ldr	r3, [r7, #36]	; 0x24
- 80037ec:	1ad3      	subs	r3, r2, r3
- 80037ee:	2b02      	cmp	r3, #2
- 80037f0:	d901      	bls.n	80037f6 <HAL_RCC_OscConfig+0x6b6>
-          {
-            return HAL_TIMEOUT;
- 80037f2:	2303      	movs	r3, #3
- 80037f4:	e076      	b.n	80038e4 <HAL_RCC_OscConfig+0x7a4>
-        while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U)
- 80037f6:	4b03      	ldr	r3, [pc, #12]	; (8003804 <HAL_RCC_OscConfig+0x6c4>)
- 80037f8:	681b      	ldr	r3, [r3, #0]
- 80037fa:	f003 7300 	and.w	r3, r3, #33554432	; 0x2000000
- 80037fe:	2b00      	cmp	r3, #0
- 8003800:	d1f0      	bne.n	80037e4 <HAL_RCC_OscConfig+0x6a4>
- 8003802:	e06e      	b.n	80038e2 <HAL_RCC_OscConfig+0x7a2>
- 8003804:	58024400 	.word	0x58024400
- 8003808:	fffffc0c 	.word	0xfffffc0c
- 800380c:	ffff0007 	.word	0xffff0007
-      }
-    }
-    else
-    {
-      /* Do not return HAL_ERROR if request repeats the current configuration */
-      temp1_pllckcfg = RCC->PLLCKSELR;
- 8003810:	4b36      	ldr	r3, [pc, #216]	; (80038ec <HAL_RCC_OscConfig+0x7ac>)
- 8003812:	6a9b      	ldr	r3, [r3, #40]	; 0x28
- 8003814:	613b      	str	r3, [r7, #16]
-      temp2_pllckcfg = RCC->PLL1DIVR;
- 8003816:	4b35      	ldr	r3, [pc, #212]	; (80038ec <HAL_RCC_OscConfig+0x7ac>)
- 8003818:	6b1b      	ldr	r3, [r3, #48]	; 0x30
- 800381a:	60fb      	str	r3, [r7, #12]
-      if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
- 800381c:	687b      	ldr	r3, [r7, #4]
- 800381e:	6a5b      	ldr	r3, [r3, #36]	; 0x24
- 8003820:	2b01      	cmp	r3, #1
- 8003822:	d031      	beq.n	8003888 <HAL_RCC_OscConfig+0x748>
-          (READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
- 8003824:	693b      	ldr	r3, [r7, #16]
- 8003826:	f003 0203 	and.w	r2, r3, #3
- 800382a:	687b      	ldr	r3, [r7, #4]
- 800382c:	6a9b      	ldr	r3, [r3, #40]	; 0x28
-      if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
- 800382e:	429a      	cmp	r2, r3
- 8003830:	d12a      	bne.n	8003888 <HAL_RCC_OscConfig+0x748>
-          ((READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_DIVM1) >> RCC_PLLCKSELR_DIVM1_Pos) != RCC_OscInitStruct->PLL.PLLM) ||
- 8003832:	693b      	ldr	r3, [r7, #16]
- 8003834:	091b      	lsrs	r3, r3, #4
- 8003836:	f003 023f 	and.w	r2, r3, #63	; 0x3f
- 800383a:	687b      	ldr	r3, [r7, #4]
- 800383c:	6adb      	ldr	r3, [r3, #44]	; 0x2c
-          (READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
- 800383e:	429a      	cmp	r2, r3
- 8003840:	d122      	bne.n	8003888 <HAL_RCC_OscConfig+0x748>
-          (READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_N1) != (RCC_OscInitStruct->PLL.PLLN - 1U)) ||
- 8003842:	68fb      	ldr	r3, [r7, #12]
- 8003844:	f3c3 0208 	ubfx	r2, r3, #0, #9
- 8003848:	687b      	ldr	r3, [r7, #4]
- 800384a:	6b1b      	ldr	r3, [r3, #48]	; 0x30
- 800384c:	3b01      	subs	r3, #1
-          ((READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_DIVM1) >> RCC_PLLCKSELR_DIVM1_Pos) != RCC_OscInitStruct->PLL.PLLM) ||
- 800384e:	429a      	cmp	r2, r3
- 8003850:	d11a      	bne.n	8003888 <HAL_RCC_OscConfig+0x748>
-          ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_P1) >> RCC_PLL1DIVR_P1_Pos) != (RCC_OscInitStruct->PLL.PLLP - 1U)) ||
- 8003852:	68fb      	ldr	r3, [r7, #12]
- 8003854:	0a5b      	lsrs	r3, r3, #9
- 8003856:	f003 027f 	and.w	r2, r3, #127	; 0x7f
- 800385a:	687b      	ldr	r3, [r7, #4]
- 800385c:	6b5b      	ldr	r3, [r3, #52]	; 0x34
- 800385e:	3b01      	subs	r3, #1
-          (READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_N1) != (RCC_OscInitStruct->PLL.PLLN - 1U)) ||
- 8003860:	429a      	cmp	r2, r3
- 8003862:	d111      	bne.n	8003888 <HAL_RCC_OscConfig+0x748>
-          ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_Q1) >> RCC_PLL1DIVR_Q1_Pos) != (RCC_OscInitStruct->PLL.PLLQ - 1U)) ||
- 8003864:	68fb      	ldr	r3, [r7, #12]
- 8003866:	0c1b      	lsrs	r3, r3, #16
- 8003868:	f003 027f 	and.w	r2, r3, #127	; 0x7f
- 800386c:	687b      	ldr	r3, [r7, #4]
- 800386e:	6b9b      	ldr	r3, [r3, #56]	; 0x38
- 8003870:	3b01      	subs	r3, #1
-          ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_P1) >> RCC_PLL1DIVR_P1_Pos) != (RCC_OscInitStruct->PLL.PLLP - 1U)) ||
- 8003872:	429a      	cmp	r2, r3
- 8003874:	d108      	bne.n	8003888 <HAL_RCC_OscConfig+0x748>
-          ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_R1) >> RCC_PLL1DIVR_R1_Pos) != (RCC_OscInitStruct->PLL.PLLR - 1U)))
- 8003876:	68fb      	ldr	r3, [r7, #12]
- 8003878:	0e1b      	lsrs	r3, r3, #24
- 800387a:	f003 027f 	and.w	r2, r3, #127	; 0x7f
- 800387e:	687b      	ldr	r3, [r7, #4]
- 8003880:	6bdb      	ldr	r3, [r3, #60]	; 0x3c
- 8003882:	3b01      	subs	r3, #1
-          ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_Q1) >> RCC_PLL1DIVR_Q1_Pos) != (RCC_OscInitStruct->PLL.PLLQ - 1U)) ||
- 8003884:	429a      	cmp	r2, r3
- 8003886:	d001      	beq.n	800388c <HAL_RCC_OscConfig+0x74c>
-      {
-        return HAL_ERROR;
- 8003888:	2301      	movs	r3, #1
- 800388a:	e02b      	b.n	80038e4 <HAL_RCC_OscConfig+0x7a4>
-      }
-      else
-      {
-        /* Check if only fractional part needs to be updated  */
-        temp1_pllckcfg = ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> RCC_PLL1FRACR_FRACN1_Pos);
- 800388c:	4b17      	ldr	r3, [pc, #92]	; (80038ec <HAL_RCC_OscConfig+0x7ac>)
- 800388e:	6b5b      	ldr	r3, [r3, #52]	; 0x34
- 8003890:	08db      	lsrs	r3, r3, #3
- 8003892:	f3c3 030c 	ubfx	r3, r3, #0, #13
- 8003896:	613b      	str	r3, [r7, #16]
-        if (RCC_OscInitStruct->PLL.PLLFRACN != temp1_pllckcfg)
- 8003898:	687b      	ldr	r3, [r7, #4]
- 800389a:	6c9b      	ldr	r3, [r3, #72]	; 0x48
- 800389c:	693a      	ldr	r2, [r7, #16]
- 800389e:	429a      	cmp	r2, r3
- 80038a0:	d01f      	beq.n	80038e2 <HAL_RCC_OscConfig+0x7a2>
-        {
-          assert_param(IS_RCC_PLLFRACN_VALUE(RCC_OscInitStruct->PLL.PLLFRACN));
-          /* Disable PLL1FRACEN */
-          __HAL_RCC_PLLFRACN_DISABLE();
- 80038a2:	4b12      	ldr	r3, [pc, #72]	; (80038ec <HAL_RCC_OscConfig+0x7ac>)
- 80038a4:	6adb      	ldr	r3, [r3, #44]	; 0x2c
- 80038a6:	4a11      	ldr	r2, [pc, #68]	; (80038ec <HAL_RCC_OscConfig+0x7ac>)
- 80038a8:	f023 0301 	bic.w	r3, r3, #1
- 80038ac:	62d3      	str	r3, [r2, #44]	; 0x2c
-          /* Get Start Tick*/
-          tickstart = HAL_GetTick();
- 80038ae:	f7fd fbad 	bl	800100c <HAL_GetTick>
- 80038b2:	6278      	str	r0, [r7, #36]	; 0x24
-          /* Wait at least 2 CK_REF (PLL input source divided by M) period to make sure next latched value will be taken into account. */
-          while ((HAL_GetTick() - tickstart) < PLL_FRAC_TIMEOUT_VALUE)
- 80038b4:	bf00      	nop
- 80038b6:	f7fd fba9 	bl	800100c <HAL_GetTick>
- 80038ba:	4602      	mov	r2, r0
- 80038bc:	6a7b      	ldr	r3, [r7, #36]	; 0x24
- 80038be:	4293      	cmp	r3, r2
- 80038c0:	d0f9      	beq.n	80038b6 <HAL_RCC_OscConfig+0x776>
-          {
-          }
-          /* Configure PLL1 PLL1FRACN */
-          __HAL_RCC_PLLFRACN_CONFIG(RCC_OscInitStruct->PLL.PLLFRACN);
- 80038c2:	4b0a      	ldr	r3, [pc, #40]	; (80038ec <HAL_RCC_OscConfig+0x7ac>)
- 80038c4:	6b5a      	ldr	r2, [r3, #52]	; 0x34
- 80038c6:	4b0a      	ldr	r3, [pc, #40]	; (80038f0 <HAL_RCC_OscConfig+0x7b0>)
- 80038c8:	4013      	ands	r3, r2
- 80038ca:	687a      	ldr	r2, [r7, #4]
- 80038cc:	6c92      	ldr	r2, [r2, #72]	; 0x48
- 80038ce:	00d2      	lsls	r2, r2, #3
- 80038d0:	4906      	ldr	r1, [pc, #24]	; (80038ec <HAL_RCC_OscConfig+0x7ac>)
- 80038d2:	4313      	orrs	r3, r2
- 80038d4:	634b      	str	r3, [r1, #52]	; 0x34
-          /* Enable PLL1FRACEN to latch new value. */
-          __HAL_RCC_PLLFRACN_ENABLE();
- 80038d6:	4b05      	ldr	r3, [pc, #20]	; (80038ec <HAL_RCC_OscConfig+0x7ac>)
- 80038d8:	6adb      	ldr	r3, [r3, #44]	; 0x2c
- 80038da:	4a04      	ldr	r2, [pc, #16]	; (80038ec <HAL_RCC_OscConfig+0x7ac>)
- 80038dc:	f043 0301 	orr.w	r3, r3, #1
- 80038e0:	62d3      	str	r3, [r2, #44]	; 0x2c
-        }
-      }
-    }
-  }
-  return HAL_OK;
- 80038e2:	2300      	movs	r3, #0
-}
- 80038e4:	4618      	mov	r0, r3
- 80038e6:	3730      	adds	r7, #48	; 0x30
- 80038e8:	46bd      	mov	sp, r7
- 80038ea:	bd80      	pop	{r7, pc}
- 80038ec:	58024400 	.word	0x58024400
- 80038f0:	ffff0007 	.word	0xffff0007
-
-080038f4 <HAL_RCC_ClockConfig>:
-  *         D1CPRE[3:0] bits to ensure that  Domain1 core clock not exceed the maximum allowed frequency
-  *         (for more details refer to section above "Initialization/de-initialization functions")
-  * @retval None
-  */
-HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t FLatency)
-{
- 80038f4:	b580      	push	{r7, lr}
- 80038f6:	b086      	sub	sp, #24
- 80038f8:	af00      	add	r7, sp, #0
- 80038fa:	6078      	str	r0, [r7, #4]
- 80038fc:	6039      	str	r1, [r7, #0]
-  HAL_StatusTypeDef halstatus;
-  uint32_t tickstart;
-  uint32_t common_system_clock;
-
-  /* Check Null pointer */
-  if (RCC_ClkInitStruct == NULL)
- 80038fe:	687b      	ldr	r3, [r7, #4]
- 8003900:	2b00      	cmp	r3, #0
- 8003902:	d101      	bne.n	8003908 <HAL_RCC_ClockConfig+0x14>
-  {
-    return HAL_ERROR;
- 8003904:	2301      	movs	r3, #1
- 8003906:	e19c      	b.n	8003c42 <HAL_RCC_ClockConfig+0x34e>
-  /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
-    must be correctly programmed according to the frequency of the CPU clock
-    (HCLK) and the supply voltage of the device. */
-
-  /* Increasing the CPU frequency */
-  if (FLatency > __HAL_FLASH_GET_LATENCY())
- 8003908:	4b8a      	ldr	r3, [pc, #552]	; (8003b34 <HAL_RCC_ClockConfig+0x240>)
- 800390a:	681b      	ldr	r3, [r3, #0]
- 800390c:	f003 030f 	and.w	r3, r3, #15
- 8003910:	683a      	ldr	r2, [r7, #0]
- 8003912:	429a      	cmp	r2, r3
- 8003914:	d910      	bls.n	8003938 <HAL_RCC_ClockConfig+0x44>
-  {
-    /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
-    __HAL_FLASH_SET_LATENCY(FLatency);
- 8003916:	4b87      	ldr	r3, [pc, #540]	; (8003b34 <HAL_RCC_ClockConfig+0x240>)
- 8003918:	681b      	ldr	r3, [r3, #0]
- 800391a:	f023 020f 	bic.w	r2, r3, #15
- 800391e:	4985      	ldr	r1, [pc, #532]	; (8003b34 <HAL_RCC_ClockConfig+0x240>)
- 8003920:	683b      	ldr	r3, [r7, #0]
- 8003922:	4313      	orrs	r3, r2
- 8003924:	600b      	str	r3, [r1, #0]
-
-    /* Check that the new number of wait states is taken into account to access the Flash
-    memory by reading the FLASH_ACR register */
-    if (__HAL_FLASH_GET_LATENCY() != FLatency)
- 8003926:	4b83      	ldr	r3, [pc, #524]	; (8003b34 <HAL_RCC_ClockConfig+0x240>)
- 8003928:	681b      	ldr	r3, [r3, #0]
- 800392a:	f003 030f 	and.w	r3, r3, #15
- 800392e:	683a      	ldr	r2, [r7, #0]
- 8003930:	429a      	cmp	r2, r3
- 8003932:	d001      	beq.n	8003938 <HAL_RCC_ClockConfig+0x44>
-    {
-      return HAL_ERROR;
- 8003934:	2301      	movs	r3, #1
- 8003936:	e184      	b.n	8003c42 <HAL_RCC_ClockConfig+0x34e>
-
-  }
-
-  /* Increasing the BUS frequency divider */
-  /*-------------------------- D1PCLK1/CDPCLK1 Configuration ---------------------------*/
-  if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D1PCLK1) == RCC_CLOCKTYPE_D1PCLK1)
- 8003938:	687b      	ldr	r3, [r7, #4]
- 800393a:	681b      	ldr	r3, [r3, #0]
- 800393c:	f003 0304 	and.w	r3, r3, #4
- 8003940:	2b00      	cmp	r3, #0
- 8003942:	d010      	beq.n	8003966 <HAL_RCC_ClockConfig+0x72>
-  {
-#if defined (RCC_D1CFGR_D1PPRE)
-    if ((RCC_ClkInitStruct->APB3CLKDivider) > (RCC->D1CFGR & RCC_D1CFGR_D1PPRE))
- 8003944:	687b      	ldr	r3, [r7, #4]
- 8003946:	691a      	ldr	r2, [r3, #16]
- 8003948:	4b7b      	ldr	r3, [pc, #492]	; (8003b38 <HAL_RCC_ClockConfig+0x244>)
- 800394a:	699b      	ldr	r3, [r3, #24]
- 800394c:	f003 0370 	and.w	r3, r3, #112	; 0x70
- 8003950:	429a      	cmp	r2, r3
- 8003952:	d908      	bls.n	8003966 <HAL_RCC_ClockConfig+0x72>
-    {
-      assert_param(IS_RCC_D1PCLK1(RCC_ClkInitStruct->APB3CLKDivider));
-      MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1PPRE, RCC_ClkInitStruct->APB3CLKDivider);
- 8003954:	4b78      	ldr	r3, [pc, #480]	; (8003b38 <HAL_RCC_ClockConfig+0x244>)
- 8003956:	699b      	ldr	r3, [r3, #24]
- 8003958:	f023 0270 	bic.w	r2, r3, #112	; 0x70
- 800395c:	687b      	ldr	r3, [r7, #4]
- 800395e:	691b      	ldr	r3, [r3, #16]
- 8003960:	4975      	ldr	r1, [pc, #468]	; (8003b38 <HAL_RCC_ClockConfig+0x244>)
- 8003962:	4313      	orrs	r3, r2
- 8003964:	618b      	str	r3, [r1, #24]
-    }
-#endif
-  }
-
-  /*-------------------------- PCLK1 Configuration ---------------------------*/
-  if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
- 8003966:	687b      	ldr	r3, [r7, #4]
- 8003968:	681b      	ldr	r3, [r3, #0]
- 800396a:	f003 0308 	and.w	r3, r3, #8
- 800396e:	2b00      	cmp	r3, #0
- 8003970:	d010      	beq.n	8003994 <HAL_RCC_ClockConfig+0xa0>
-  {
-#if defined (RCC_D2CFGR_D2PPRE1)
-    if ((RCC_ClkInitStruct->APB1CLKDivider) > (RCC->D2CFGR & RCC_D2CFGR_D2PPRE1))
- 8003972:	687b      	ldr	r3, [r7, #4]
- 8003974:	695a      	ldr	r2, [r3, #20]
- 8003976:	4b70      	ldr	r3, [pc, #448]	; (8003b38 <HAL_RCC_ClockConfig+0x244>)
- 8003978:	69db      	ldr	r3, [r3, #28]
- 800397a:	f003 0370 	and.w	r3, r3, #112	; 0x70
- 800397e:	429a      	cmp	r2, r3
- 8003980:	d908      	bls.n	8003994 <HAL_RCC_ClockConfig+0xa0>
-    {
-      assert_param(IS_RCC_PCLK1(RCC_ClkInitStruct->APB1CLKDivider));
-      MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE1, (RCC_ClkInitStruct->APB1CLKDivider));
- 8003982:	4b6d      	ldr	r3, [pc, #436]	; (8003b38 <HAL_RCC_ClockConfig+0x244>)
- 8003984:	69db      	ldr	r3, [r3, #28]
- 8003986:	f023 0270 	bic.w	r2, r3, #112	; 0x70
- 800398a:	687b      	ldr	r3, [r7, #4]
- 800398c:	695b      	ldr	r3, [r3, #20]
- 800398e:	496a      	ldr	r1, [pc, #424]	; (8003b38 <HAL_RCC_ClockConfig+0x244>)
- 8003990:	4313      	orrs	r3, r2
- 8003992:	61cb      	str	r3, [r1, #28]
-      MODIFY_REG(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE1, (RCC_ClkInitStruct->APB1CLKDivider));
-    }
-#endif
-  }
-  /*-------------------------- PCLK2 Configuration ---------------------------*/
-  if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
- 8003994:	687b      	ldr	r3, [r7, #4]
- 8003996:	681b      	ldr	r3, [r3, #0]
- 8003998:	f003 0310 	and.w	r3, r3, #16
- 800399c:	2b00      	cmp	r3, #0
- 800399e:	d010      	beq.n	80039c2 <HAL_RCC_ClockConfig+0xce>
-  {
-#if defined(RCC_D2CFGR_D2PPRE2)
-    if ((RCC_ClkInitStruct->APB2CLKDivider) > (RCC->D2CFGR & RCC_D2CFGR_D2PPRE2))
- 80039a0:	687b      	ldr	r3, [r7, #4]
- 80039a2:	699a      	ldr	r2, [r3, #24]
- 80039a4:	4b64      	ldr	r3, [pc, #400]	; (8003b38 <HAL_RCC_ClockConfig+0x244>)
- 80039a6:	69db      	ldr	r3, [r3, #28]
- 80039a8:	f403 63e0 	and.w	r3, r3, #1792	; 0x700
- 80039ac:	429a      	cmp	r2, r3
- 80039ae:	d908      	bls.n	80039c2 <HAL_RCC_ClockConfig+0xce>
-    {
-      assert_param(IS_RCC_PCLK2(RCC_ClkInitStruct->APB2CLKDivider));
-      MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE2, (RCC_ClkInitStruct->APB2CLKDivider));
- 80039b0:	4b61      	ldr	r3, [pc, #388]	; (8003b38 <HAL_RCC_ClockConfig+0x244>)
- 80039b2:	69db      	ldr	r3, [r3, #28]
- 80039b4:	f423 62e0 	bic.w	r2, r3, #1792	; 0x700
- 80039b8:	687b      	ldr	r3, [r7, #4]
- 80039ba:	699b      	ldr	r3, [r3, #24]
- 80039bc:	495e      	ldr	r1, [pc, #376]	; (8003b38 <HAL_RCC_ClockConfig+0x244>)
- 80039be:	4313      	orrs	r3, r2
- 80039c0:	61cb      	str	r3, [r1, #28]
-    }
-#endif
-  }
-
-  /*-------------------------- D3PCLK1 Configuration ---------------------------*/
-  if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D3PCLK1) == RCC_CLOCKTYPE_D3PCLK1)
- 80039c2:	687b      	ldr	r3, [r7, #4]
- 80039c4:	681b      	ldr	r3, [r3, #0]
- 80039c6:	f003 0320 	and.w	r3, r3, #32
- 80039ca:	2b00      	cmp	r3, #0
- 80039cc:	d010      	beq.n	80039f0 <HAL_RCC_ClockConfig+0xfc>
-  {
-#if defined(RCC_D3CFGR_D3PPRE)
-    if ((RCC_ClkInitStruct->APB4CLKDivider) > (RCC->D3CFGR & RCC_D3CFGR_D3PPRE))
- 80039ce:	687b      	ldr	r3, [r7, #4]
- 80039d0:	69da      	ldr	r2, [r3, #28]
- 80039d2:	4b59      	ldr	r3, [pc, #356]	; (8003b38 <HAL_RCC_ClockConfig+0x244>)
- 80039d4:	6a1b      	ldr	r3, [r3, #32]
- 80039d6:	f003 0370 	and.w	r3, r3, #112	; 0x70
- 80039da:	429a      	cmp	r2, r3
- 80039dc:	d908      	bls.n	80039f0 <HAL_RCC_ClockConfig+0xfc>
-    {
-      assert_param(IS_RCC_D3PCLK1(RCC_ClkInitStruct->APB4CLKDivider));
-      MODIFY_REG(RCC->D3CFGR, RCC_D3CFGR_D3PPRE, (RCC_ClkInitStruct->APB4CLKDivider));
- 80039de:	4b56      	ldr	r3, [pc, #344]	; (8003b38 <HAL_RCC_ClockConfig+0x244>)
- 80039e0:	6a1b      	ldr	r3, [r3, #32]
- 80039e2:	f023 0270 	bic.w	r2, r3, #112	; 0x70
- 80039e6:	687b      	ldr	r3, [r7, #4]
- 80039e8:	69db      	ldr	r3, [r3, #28]
- 80039ea:	4953      	ldr	r1, [pc, #332]	; (8003b38 <HAL_RCC_ClockConfig+0x244>)
- 80039ec:	4313      	orrs	r3, r2
- 80039ee:	620b      	str	r3, [r1, #32]
-    }
-#endif
-  }
-
-  /*-------------------------- HCLK Configuration --------------------------*/
-  if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
- 80039f0:	687b      	ldr	r3, [r7, #4]
- 80039f2:	681b      	ldr	r3, [r3, #0]
- 80039f4:	f003 0302 	and.w	r3, r3, #2
- 80039f8:	2b00      	cmp	r3, #0
- 80039fa:	d010      	beq.n	8003a1e <HAL_RCC_ClockConfig+0x12a>
-  {
-#if defined (RCC_D1CFGR_HPRE)
-    if ((RCC_ClkInitStruct->AHBCLKDivider) > (RCC->D1CFGR & RCC_D1CFGR_HPRE))
- 80039fc:	687b      	ldr	r3, [r7, #4]
- 80039fe:	68da      	ldr	r2, [r3, #12]
- 8003a00:	4b4d      	ldr	r3, [pc, #308]	; (8003b38 <HAL_RCC_ClockConfig+0x244>)
- 8003a02:	699b      	ldr	r3, [r3, #24]
- 8003a04:	f003 030f 	and.w	r3, r3, #15
- 8003a08:	429a      	cmp	r2, r3
- 8003a0a:	d908      	bls.n	8003a1e <HAL_RCC_ClockConfig+0x12a>
-    {
-      /* Set the new HCLK clock divider */
-      assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
-      MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
- 8003a0c:	4b4a      	ldr	r3, [pc, #296]	; (8003b38 <HAL_RCC_ClockConfig+0x244>)
- 8003a0e:	699b      	ldr	r3, [r3, #24]
- 8003a10:	f023 020f 	bic.w	r2, r3, #15
- 8003a14:	687b      	ldr	r3, [r7, #4]
- 8003a16:	68db      	ldr	r3, [r3, #12]
- 8003a18:	4947      	ldr	r1, [pc, #284]	; (8003b38 <HAL_RCC_ClockConfig+0x244>)
- 8003a1a:	4313      	orrs	r3, r2
- 8003a1c:	618b      	str	r3, [r1, #24]
-    }
-#endif
-  }
-
-  /*------------------------- SYSCLK Configuration -------------------------*/
-  if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
- 8003a1e:	687b      	ldr	r3, [r7, #4]
- 8003a20:	681b      	ldr	r3, [r3, #0]
- 8003a22:	f003 0301 	and.w	r3, r3, #1
- 8003a26:	2b00      	cmp	r3, #0
- 8003a28:	d055      	beq.n	8003ad6 <HAL_RCC_ClockConfig+0x1e2>
-  {
-    assert_param(IS_RCC_SYSCLK(RCC_ClkInitStruct->SYSCLKDivider));
-    assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
-#if defined(RCC_D1CFGR_D1CPRE)
-    MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1CPRE, RCC_ClkInitStruct->SYSCLKDivider);
- 8003a2a:	4b43      	ldr	r3, [pc, #268]	; (8003b38 <HAL_RCC_ClockConfig+0x244>)
- 8003a2c:	699b      	ldr	r3, [r3, #24]
- 8003a2e:	f423 6270 	bic.w	r2, r3, #3840	; 0xf00
- 8003a32:	687b      	ldr	r3, [r7, #4]
- 8003a34:	689b      	ldr	r3, [r3, #8]
- 8003a36:	4940      	ldr	r1, [pc, #256]	; (8003b38 <HAL_RCC_ClockConfig+0x244>)
- 8003a38:	4313      	orrs	r3, r2
- 8003a3a:	618b      	str	r3, [r1, #24]
-#else
-    MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_CDCPRE, RCC_ClkInitStruct->SYSCLKDivider);
-#endif
-    /* HSE is selected as System Clock Source */
-    if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
- 8003a3c:	687b      	ldr	r3, [r7, #4]
- 8003a3e:	685b      	ldr	r3, [r3, #4]
- 8003a40:	2b02      	cmp	r3, #2
- 8003a42:	d107      	bne.n	8003a54 <HAL_RCC_ClockConfig+0x160>
-    {
-      /* Check the HSE ready flag */
-      if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U)
- 8003a44:	4b3c      	ldr	r3, [pc, #240]	; (8003b38 <HAL_RCC_ClockConfig+0x244>)
- 8003a46:	681b      	ldr	r3, [r3, #0]
- 8003a48:	f403 3300 	and.w	r3, r3, #131072	; 0x20000
- 8003a4c:	2b00      	cmp	r3, #0
- 8003a4e:	d121      	bne.n	8003a94 <HAL_RCC_ClockConfig+0x1a0>
-      {
-        return HAL_ERROR;
- 8003a50:	2301      	movs	r3, #1
- 8003a52:	e0f6      	b.n	8003c42 <HAL_RCC_ClockConfig+0x34e>
-      }
-    }
-    /* PLL is selected as System Clock Source */
-    else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
- 8003a54:	687b      	ldr	r3, [r7, #4]
- 8003a56:	685b      	ldr	r3, [r3, #4]
- 8003a58:	2b03      	cmp	r3, #3
- 8003a5a:	d107      	bne.n	8003a6c <HAL_RCC_ClockConfig+0x178>
-    {
-      /* Check the PLL ready flag */
-      if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U)
- 8003a5c:	4b36      	ldr	r3, [pc, #216]	; (8003b38 <HAL_RCC_ClockConfig+0x244>)
- 8003a5e:	681b      	ldr	r3, [r3, #0]
- 8003a60:	f003 7300 	and.w	r3, r3, #33554432	; 0x2000000
- 8003a64:	2b00      	cmp	r3, #0
- 8003a66:	d115      	bne.n	8003a94 <HAL_RCC_ClockConfig+0x1a0>
-      {
-        return HAL_ERROR;
- 8003a68:	2301      	movs	r3, #1
- 8003a6a:	e0ea      	b.n	8003c42 <HAL_RCC_ClockConfig+0x34e>
-      }
-    }
-    /* CSI is selected as System Clock Source */
-    else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_CSI)
- 8003a6c:	687b      	ldr	r3, [r7, #4]
- 8003a6e:	685b      	ldr	r3, [r3, #4]
- 8003a70:	2b01      	cmp	r3, #1
- 8003a72:	d107      	bne.n	8003a84 <HAL_RCC_ClockConfig+0x190>
-    {
-      /* Check the PLL ready flag */
-      if (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) == 0U)
- 8003a74:	4b30      	ldr	r3, [pc, #192]	; (8003b38 <HAL_RCC_ClockConfig+0x244>)
- 8003a76:	681b      	ldr	r3, [r3, #0]
- 8003a78:	f403 7380 	and.w	r3, r3, #256	; 0x100
- 8003a7c:	2b00      	cmp	r3, #0
- 8003a7e:	d109      	bne.n	8003a94 <HAL_RCC_ClockConfig+0x1a0>
-      {
-        return HAL_ERROR;
- 8003a80:	2301      	movs	r3, #1
- 8003a82:	e0de      	b.n	8003c42 <HAL_RCC_ClockConfig+0x34e>
-    }
-    /* HSI is selected as System Clock Source */
-    else
-    {
-      /* Check the HSI ready flag */
-      if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U)
- 8003a84:	4b2c      	ldr	r3, [pc, #176]	; (8003b38 <HAL_RCC_ClockConfig+0x244>)
- 8003a86:	681b      	ldr	r3, [r3, #0]
- 8003a88:	f003 0304 	and.w	r3, r3, #4
- 8003a8c:	2b00      	cmp	r3, #0
- 8003a8e:	d101      	bne.n	8003a94 <HAL_RCC_ClockConfig+0x1a0>
-      {
-        return HAL_ERROR;
- 8003a90:	2301      	movs	r3, #1
- 8003a92:	e0d6      	b.n	8003c42 <HAL_RCC_ClockConfig+0x34e>
-      }
-    }
-    MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);
- 8003a94:	4b28      	ldr	r3, [pc, #160]	; (8003b38 <HAL_RCC_ClockConfig+0x244>)
- 8003a96:	691b      	ldr	r3, [r3, #16]
- 8003a98:	f023 0207 	bic.w	r2, r3, #7
- 8003a9c:	687b      	ldr	r3, [r7, #4]
- 8003a9e:	685b      	ldr	r3, [r3, #4]
- 8003aa0:	4925      	ldr	r1, [pc, #148]	; (8003b38 <HAL_RCC_ClockConfig+0x244>)
- 8003aa2:	4313      	orrs	r3, r2
- 8003aa4:	610b      	str	r3, [r1, #16]
-
-    /* Get Start Tick*/
-    tickstart = HAL_GetTick();
- 8003aa6:	f7fd fab1 	bl	800100c <HAL_GetTick>
- 8003aaa:	6178      	str	r0, [r7, #20]
-
-    while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
- 8003aac:	e00a      	b.n	8003ac4 <HAL_RCC_ClockConfig+0x1d0>
-    {
-      if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
- 8003aae:	f7fd faad 	bl	800100c <HAL_GetTick>
- 8003ab2:	4602      	mov	r2, r0
- 8003ab4:	697b      	ldr	r3, [r7, #20]
- 8003ab6:	1ad3      	subs	r3, r2, r3
- 8003ab8:	f241 3288 	movw	r2, #5000	; 0x1388
- 8003abc:	4293      	cmp	r3, r2
- 8003abe:	d901      	bls.n	8003ac4 <HAL_RCC_ClockConfig+0x1d0>
-      {
-        return HAL_TIMEOUT;
- 8003ac0:	2303      	movs	r3, #3
- 8003ac2:	e0be      	b.n	8003c42 <HAL_RCC_ClockConfig+0x34e>
-    while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
- 8003ac4:	4b1c      	ldr	r3, [pc, #112]	; (8003b38 <HAL_RCC_ClockConfig+0x244>)
- 8003ac6:	691b      	ldr	r3, [r3, #16]
- 8003ac8:	f003 0238 	and.w	r2, r3, #56	; 0x38
- 8003acc:	687b      	ldr	r3, [r7, #4]
- 8003ace:	685b      	ldr	r3, [r3, #4]
- 8003ad0:	00db      	lsls	r3, r3, #3
- 8003ad2:	429a      	cmp	r2, r3
- 8003ad4:	d1eb      	bne.n	8003aae <HAL_RCC_ClockConfig+0x1ba>
-
-  }
-
-  /* Decreasing the BUS frequency divider */
-  /*-------------------------- HCLK Configuration --------------------------*/
-  if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
- 8003ad6:	687b      	ldr	r3, [r7, #4]
- 8003ad8:	681b      	ldr	r3, [r3, #0]
- 8003ada:	f003 0302 	and.w	r3, r3, #2
- 8003ade:	2b00      	cmp	r3, #0
- 8003ae0:	d010      	beq.n	8003b04 <HAL_RCC_ClockConfig+0x210>
-  {
-#if defined(RCC_D1CFGR_HPRE)
-    if ((RCC_ClkInitStruct->AHBCLKDivider) < (RCC->D1CFGR & RCC_D1CFGR_HPRE))
- 8003ae2:	687b      	ldr	r3, [r7, #4]
- 8003ae4:	68da      	ldr	r2, [r3, #12]
- 8003ae6:	4b14      	ldr	r3, [pc, #80]	; (8003b38 <HAL_RCC_ClockConfig+0x244>)
- 8003ae8:	699b      	ldr	r3, [r3, #24]
- 8003aea:	f003 030f 	and.w	r3, r3, #15
- 8003aee:	429a      	cmp	r2, r3
- 8003af0:	d208      	bcs.n	8003b04 <HAL_RCC_ClockConfig+0x210>
-    {
-      /* Set the new HCLK clock divider */
-      assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
-      MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
- 8003af2:	4b11      	ldr	r3, [pc, #68]	; (8003b38 <HAL_RCC_ClockConfig+0x244>)
- 8003af4:	699b      	ldr	r3, [r3, #24]
- 8003af6:	f023 020f 	bic.w	r2, r3, #15
- 8003afa:	687b      	ldr	r3, [r7, #4]
- 8003afc:	68db      	ldr	r3, [r3, #12]
- 8003afe:	490e      	ldr	r1, [pc, #56]	; (8003b38 <HAL_RCC_ClockConfig+0x244>)
- 8003b00:	4313      	orrs	r3, r2
- 8003b02:	618b      	str	r3, [r1, #24]
-    }
-#endif
-  }
-
-  /* Decreasing the number of wait states because of lower CPU frequency */
-  if (FLatency < __HAL_FLASH_GET_LATENCY())
- 8003b04:	4b0b      	ldr	r3, [pc, #44]	; (8003b34 <HAL_RCC_ClockConfig+0x240>)
- 8003b06:	681b      	ldr	r3, [r3, #0]
- 8003b08:	f003 030f 	and.w	r3, r3, #15
- 8003b0c:	683a      	ldr	r2, [r7, #0]
- 8003b0e:	429a      	cmp	r2, r3
- 8003b10:	d214      	bcs.n	8003b3c <HAL_RCC_ClockConfig+0x248>
-  {
-    /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
-    __HAL_FLASH_SET_LATENCY(FLatency);
- 8003b12:	4b08      	ldr	r3, [pc, #32]	; (8003b34 <HAL_RCC_ClockConfig+0x240>)
- 8003b14:	681b      	ldr	r3, [r3, #0]
- 8003b16:	f023 020f 	bic.w	r2, r3, #15
- 8003b1a:	4906      	ldr	r1, [pc, #24]	; (8003b34 <HAL_RCC_ClockConfig+0x240>)
- 8003b1c:	683b      	ldr	r3, [r7, #0]
- 8003b1e:	4313      	orrs	r3, r2
- 8003b20:	600b      	str	r3, [r1, #0]
-
-    /* Check that the new number of wait states is taken into account to access the Flash
-    memory by reading the FLASH_ACR register */
-    if (__HAL_FLASH_GET_LATENCY() != FLatency)
- 8003b22:	4b04      	ldr	r3, [pc, #16]	; (8003b34 <HAL_RCC_ClockConfig+0x240>)
- 8003b24:	681b      	ldr	r3, [r3, #0]
- 8003b26:	f003 030f 	and.w	r3, r3, #15
- 8003b2a:	683a      	ldr	r2, [r7, #0]
- 8003b2c:	429a      	cmp	r2, r3
- 8003b2e:	d005      	beq.n	8003b3c <HAL_RCC_ClockConfig+0x248>
-    {
-      return HAL_ERROR;
- 8003b30:	2301      	movs	r3, #1
- 8003b32:	e086      	b.n	8003c42 <HAL_RCC_ClockConfig+0x34e>
- 8003b34:	52002000 	.word	0x52002000
- 8003b38:	58024400 	.word	0x58024400
-    }
-  }
-
-  /*-------------------------- D1PCLK1/CDPCLK Configuration ---------------------------*/
-  if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D1PCLK1) == RCC_CLOCKTYPE_D1PCLK1)
- 8003b3c:	687b      	ldr	r3, [r7, #4]
- 8003b3e:	681b      	ldr	r3, [r3, #0]
- 8003b40:	f003 0304 	and.w	r3, r3, #4
- 8003b44:	2b00      	cmp	r3, #0
- 8003b46:	d010      	beq.n	8003b6a <HAL_RCC_ClockConfig+0x276>
-  {
-#if defined(RCC_D1CFGR_D1PPRE)
-    if ((RCC_ClkInitStruct->APB3CLKDivider) < (RCC->D1CFGR & RCC_D1CFGR_D1PPRE))
- 8003b48:	687b      	ldr	r3, [r7, #4]
- 8003b4a:	691a      	ldr	r2, [r3, #16]
- 8003b4c:	4b3f      	ldr	r3, [pc, #252]	; (8003c4c <HAL_RCC_ClockConfig+0x358>)
- 8003b4e:	699b      	ldr	r3, [r3, #24]
- 8003b50:	f003 0370 	and.w	r3, r3, #112	; 0x70
- 8003b54:	429a      	cmp	r2, r3
- 8003b56:	d208      	bcs.n	8003b6a <HAL_RCC_ClockConfig+0x276>
-    {
-      assert_param(IS_RCC_D1PCLK1(RCC_ClkInitStruct->APB3CLKDivider));
-      MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1PPRE, RCC_ClkInitStruct->APB3CLKDivider);
- 8003b58:	4b3c      	ldr	r3, [pc, #240]	; (8003c4c <HAL_RCC_ClockConfig+0x358>)
- 8003b5a:	699b      	ldr	r3, [r3, #24]
- 8003b5c:	f023 0270 	bic.w	r2, r3, #112	; 0x70
- 8003b60:	687b      	ldr	r3, [r7, #4]
- 8003b62:	691b      	ldr	r3, [r3, #16]
- 8003b64:	4939      	ldr	r1, [pc, #228]	; (8003c4c <HAL_RCC_ClockConfig+0x358>)
- 8003b66:	4313      	orrs	r3, r2
- 8003b68:	618b      	str	r3, [r1, #24]
-    }
-#endif
-  }
-
-  /*-------------------------- PCLK1 Configuration ---------------------------*/
-  if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
- 8003b6a:	687b      	ldr	r3, [r7, #4]
- 8003b6c:	681b      	ldr	r3, [r3, #0]
- 8003b6e:	f003 0308 	and.w	r3, r3, #8
- 8003b72:	2b00      	cmp	r3, #0
- 8003b74:	d010      	beq.n	8003b98 <HAL_RCC_ClockConfig+0x2a4>
-  {
-#if defined(RCC_D2CFGR_D2PPRE1)
-    if ((RCC_ClkInitStruct->APB1CLKDivider) < (RCC->D2CFGR & RCC_D2CFGR_D2PPRE1))
- 8003b76:	687b      	ldr	r3, [r7, #4]
- 8003b78:	695a      	ldr	r2, [r3, #20]
- 8003b7a:	4b34      	ldr	r3, [pc, #208]	; (8003c4c <HAL_RCC_ClockConfig+0x358>)
- 8003b7c:	69db      	ldr	r3, [r3, #28]
- 8003b7e:	f003 0370 	and.w	r3, r3, #112	; 0x70
- 8003b82:	429a      	cmp	r2, r3
- 8003b84:	d208      	bcs.n	8003b98 <HAL_RCC_ClockConfig+0x2a4>
-    {
-      assert_param(IS_RCC_PCLK1(RCC_ClkInitStruct->APB1CLKDivider));
-      MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE1, (RCC_ClkInitStruct->APB1CLKDivider));
- 8003b86:	4b31      	ldr	r3, [pc, #196]	; (8003c4c <HAL_RCC_ClockConfig+0x358>)
- 8003b88:	69db      	ldr	r3, [r3, #28]
- 8003b8a:	f023 0270 	bic.w	r2, r3, #112	; 0x70
- 8003b8e:	687b      	ldr	r3, [r7, #4]
- 8003b90:	695b      	ldr	r3, [r3, #20]
- 8003b92:	492e      	ldr	r1, [pc, #184]	; (8003c4c <HAL_RCC_ClockConfig+0x358>)
- 8003b94:	4313      	orrs	r3, r2
- 8003b96:	61cb      	str	r3, [r1, #28]
-    }
-#endif
-  }
-
-  /*-------------------------- PCLK2 Configuration ---------------------------*/
-  if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
- 8003b98:	687b      	ldr	r3, [r7, #4]
- 8003b9a:	681b      	ldr	r3, [r3, #0]
- 8003b9c:	f003 0310 	and.w	r3, r3, #16
- 8003ba0:	2b00      	cmp	r3, #0
- 8003ba2:	d010      	beq.n	8003bc6 <HAL_RCC_ClockConfig+0x2d2>
-  {
-#if defined (RCC_D2CFGR_D2PPRE2)
-    if ((RCC_ClkInitStruct->APB2CLKDivider) < (RCC->D2CFGR & RCC_D2CFGR_D2PPRE2))
- 8003ba4:	687b      	ldr	r3, [r7, #4]
- 8003ba6:	699a      	ldr	r2, [r3, #24]
- 8003ba8:	4b28      	ldr	r3, [pc, #160]	; (8003c4c <HAL_RCC_ClockConfig+0x358>)
- 8003baa:	69db      	ldr	r3, [r3, #28]
- 8003bac:	f403 63e0 	and.w	r3, r3, #1792	; 0x700
- 8003bb0:	429a      	cmp	r2, r3
- 8003bb2:	d208      	bcs.n	8003bc6 <HAL_RCC_ClockConfig+0x2d2>
-    {
-      assert_param(IS_RCC_PCLK2(RCC_ClkInitStruct->APB2CLKDivider));
-      MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE2, (RCC_ClkInitStruct->APB2CLKDivider));
- 8003bb4:	4b25      	ldr	r3, [pc, #148]	; (8003c4c <HAL_RCC_ClockConfig+0x358>)
- 8003bb6:	69db      	ldr	r3, [r3, #28]
- 8003bb8:	f423 62e0 	bic.w	r2, r3, #1792	; 0x700
- 8003bbc:	687b      	ldr	r3, [r7, #4]
- 8003bbe:	699b      	ldr	r3, [r3, #24]
- 8003bc0:	4922      	ldr	r1, [pc, #136]	; (8003c4c <HAL_RCC_ClockConfig+0x358>)
- 8003bc2:	4313      	orrs	r3, r2
- 8003bc4:	61cb      	str	r3, [r1, #28]
-    }
-#endif
-  }
-
-  /*-------------------------- D3PCLK1/SRDPCLK1 Configuration ---------------------------*/
-  if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D3PCLK1) == RCC_CLOCKTYPE_D3PCLK1)
- 8003bc6:	687b      	ldr	r3, [r7, #4]
- 8003bc8:	681b      	ldr	r3, [r3, #0]
- 8003bca:	f003 0320 	and.w	r3, r3, #32
- 8003bce:	2b00      	cmp	r3, #0
- 8003bd0:	d010      	beq.n	8003bf4 <HAL_RCC_ClockConfig+0x300>
-  {
-#if defined(RCC_D3CFGR_D3PPRE)
-    if ((RCC_ClkInitStruct->APB4CLKDivider) < (RCC->D3CFGR & RCC_D3CFGR_D3PPRE))
- 8003bd2:	687b      	ldr	r3, [r7, #4]
- 8003bd4:	69da      	ldr	r2, [r3, #28]
- 8003bd6:	4b1d      	ldr	r3, [pc, #116]	; (8003c4c <HAL_RCC_ClockConfig+0x358>)
- 8003bd8:	6a1b      	ldr	r3, [r3, #32]
- 8003bda:	f003 0370 	and.w	r3, r3, #112	; 0x70
- 8003bde:	429a      	cmp	r2, r3
- 8003be0:	d208      	bcs.n	8003bf4 <HAL_RCC_ClockConfig+0x300>
-    {
-      assert_param(IS_RCC_D3PCLK1(RCC_ClkInitStruct->APB4CLKDivider));
-      MODIFY_REG(RCC->D3CFGR, RCC_D3CFGR_D3PPRE, (RCC_ClkInitStruct->APB4CLKDivider));
- 8003be2:	4b1a      	ldr	r3, [pc, #104]	; (8003c4c <HAL_RCC_ClockConfig+0x358>)
- 8003be4:	6a1b      	ldr	r3, [r3, #32]
- 8003be6:	f023 0270 	bic.w	r2, r3, #112	; 0x70
- 8003bea:	687b      	ldr	r3, [r7, #4]
- 8003bec:	69db      	ldr	r3, [r3, #28]
- 8003bee:	4917      	ldr	r1, [pc, #92]	; (8003c4c <HAL_RCC_ClockConfig+0x358>)
- 8003bf0:	4313      	orrs	r3, r2
- 8003bf2:	620b      	str	r3, [r1, #32]
-#endif
-  }
-
-  /* Update the SystemCoreClock global variable */
-#if defined(RCC_D1CFGR_D1CPRE)
-  common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE) >> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU);
- 8003bf4:	f000 f834 	bl	8003c60 <HAL_RCC_GetSysClockFreq>
- 8003bf8:	4602      	mov	r2, r0
- 8003bfa:	4b14      	ldr	r3, [pc, #80]	; (8003c4c <HAL_RCC_ClockConfig+0x358>)
- 8003bfc:	699b      	ldr	r3, [r3, #24]
- 8003bfe:	0a1b      	lsrs	r3, r3, #8
- 8003c00:	f003 030f 	and.w	r3, r3, #15
- 8003c04:	4912      	ldr	r1, [pc, #72]	; (8003c50 <HAL_RCC_ClockConfig+0x35c>)
- 8003c06:	5ccb      	ldrb	r3, [r1, r3]
- 8003c08:	f003 031f 	and.w	r3, r3, #31
- 8003c0c:	fa22 f303 	lsr.w	r3, r2, r3
- 8003c10:	613b      	str	r3, [r7, #16]
-#else
-  common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE) >> RCC_CDCFGR1_CDCPRE_Pos]) & 0x1FU);
-#endif
-
-#if defined(RCC_D1CFGR_HPRE)
-  SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE) >> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
- 8003c12:	4b0e      	ldr	r3, [pc, #56]	; (8003c4c <HAL_RCC_ClockConfig+0x358>)
- 8003c14:	699b      	ldr	r3, [r3, #24]
- 8003c16:	f003 030f 	and.w	r3, r3, #15
- 8003c1a:	4a0d      	ldr	r2, [pc, #52]	; (8003c50 <HAL_RCC_ClockConfig+0x35c>)
- 8003c1c:	5cd3      	ldrb	r3, [r2, r3]
- 8003c1e:	f003 031f 	and.w	r3, r3, #31
- 8003c22:	693a      	ldr	r2, [r7, #16]
- 8003c24:	fa22 f303 	lsr.w	r3, r2, r3
- 8003c28:	4a0a      	ldr	r2, [pc, #40]	; (8003c54 <HAL_RCC_ClockConfig+0x360>)
- 8003c2a:	6013      	str	r3, [r2, #0]
-#endif
-
-#if defined(DUAL_CORE) && defined(CORE_CM4)
-  SystemCoreClock = SystemD2Clock;
-#else
-  SystemCoreClock = common_system_clock;
- 8003c2c:	4a0a      	ldr	r2, [pc, #40]	; (8003c58 <HAL_RCC_ClockConfig+0x364>)
- 8003c2e:	693b      	ldr	r3, [r7, #16]
- 8003c30:	6013      	str	r3, [r2, #0]
-#endif /* DUAL_CORE && CORE_CM4 */
-
-  /* Configure the source of time base considering new system clocks settings*/
-  halstatus = HAL_InitTick(uwTickPrio);
- 8003c32:	4b0a      	ldr	r3, [pc, #40]	; (8003c5c <HAL_RCC_ClockConfig+0x368>)
- 8003c34:	681b      	ldr	r3, [r3, #0]
- 8003c36:	4618      	mov	r0, r3
- 8003c38:	f7fd f99e 	bl	8000f78 <HAL_InitTick>
- 8003c3c:	4603      	mov	r3, r0
- 8003c3e:	73fb      	strb	r3, [r7, #15]
-
-  return halstatus;
- 8003c40:	7bfb      	ldrb	r3, [r7, #15]
-}
- 8003c42:	4618      	mov	r0, r3
- 8003c44:	3718      	adds	r7, #24
- 8003c46:	46bd      	mov	sp, r7
- 8003c48:	bd80      	pop	{r7, pc}
- 8003c4a:	bf00      	nop
- 8003c4c:	58024400 	.word	0x58024400
- 8003c50:	08014c80 	.word	0x08014c80
- 8003c54:	24000004 	.word	0x24000004
- 8003c58:	24000000 	.word	0x24000000
- 8003c5c:	24000008 	.word	0x24000008
-
-08003c60 <HAL_RCC_GetSysClockFreq>:
-  *
-  *
-  * @retval SYSCLK frequency
-  */
-uint32_t HAL_RCC_GetSysClockFreq(void)
-{
- 8003c60:	b480      	push	{r7}
- 8003c62:	b089      	sub	sp, #36	; 0x24
- 8003c64:	af00      	add	r7, sp, #0
-  float_t fracn1, pllvco;
-  uint32_t sysclockfreq;
-
-  /* Get SYSCLK source -------------------------------------------------------*/
-
-  switch (RCC->CFGR & RCC_CFGR_SWS)
- 8003c66:	4bb3      	ldr	r3, [pc, #716]	; (8003f34 <HAL_RCC_GetSysClockFreq+0x2d4>)
- 8003c68:	691b      	ldr	r3, [r3, #16]
- 8003c6a:	f003 0338 	and.w	r3, r3, #56	; 0x38
- 8003c6e:	2b18      	cmp	r3, #24
- 8003c70:	f200 8155 	bhi.w	8003f1e <HAL_RCC_GetSysClockFreq+0x2be>
- 8003c74:	a201      	add	r2, pc, #4	; (adr r2, 8003c7c <HAL_RCC_GetSysClockFreq+0x1c>)
- 8003c76:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
- 8003c7a:	bf00      	nop
- 8003c7c:	08003ce1 	.word	0x08003ce1
- 8003c80:	08003f1f 	.word	0x08003f1f
- 8003c84:	08003f1f 	.word	0x08003f1f
- 8003c88:	08003f1f 	.word	0x08003f1f
- 8003c8c:	08003f1f 	.word	0x08003f1f
- 8003c90:	08003f1f 	.word	0x08003f1f
- 8003c94:	08003f1f 	.word	0x08003f1f
- 8003c98:	08003f1f 	.word	0x08003f1f
- 8003c9c:	08003d07 	.word	0x08003d07
- 8003ca0:	08003f1f 	.word	0x08003f1f
- 8003ca4:	08003f1f 	.word	0x08003f1f
- 8003ca8:	08003f1f 	.word	0x08003f1f
- 8003cac:	08003f1f 	.word	0x08003f1f
- 8003cb0:	08003f1f 	.word	0x08003f1f
- 8003cb4:	08003f1f 	.word	0x08003f1f
- 8003cb8:	08003f1f 	.word	0x08003f1f
- 8003cbc:	08003d0d 	.word	0x08003d0d
- 8003cc0:	08003f1f 	.word	0x08003f1f
- 8003cc4:	08003f1f 	.word	0x08003f1f
- 8003cc8:	08003f1f 	.word	0x08003f1f
- 8003ccc:	08003f1f 	.word	0x08003f1f
- 8003cd0:	08003f1f 	.word	0x08003f1f
- 8003cd4:	08003f1f 	.word	0x08003f1f
- 8003cd8:	08003f1f 	.word	0x08003f1f
- 8003cdc:	08003d13 	.word	0x08003d13
-  {
-    case RCC_CFGR_SWS_HSI:  /* HSI used as system clock source */
-
-      if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
- 8003ce0:	4b94      	ldr	r3, [pc, #592]	; (8003f34 <HAL_RCC_GetSysClockFreq+0x2d4>)
- 8003ce2:	681b      	ldr	r3, [r3, #0]
- 8003ce4:	f003 0320 	and.w	r3, r3, #32
- 8003ce8:	2b00      	cmp	r3, #0
- 8003cea:	d009      	beq.n	8003d00 <HAL_RCC_GetSysClockFreq+0xa0>
-      {
-        sysclockfreq = (uint32_t)(HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
- 8003cec:	4b91      	ldr	r3, [pc, #580]	; (8003f34 <HAL_RCC_GetSysClockFreq+0x2d4>)
- 8003cee:	681b      	ldr	r3, [r3, #0]
- 8003cf0:	08db      	lsrs	r3, r3, #3
- 8003cf2:	f003 0303 	and.w	r3, r3, #3
- 8003cf6:	4a90      	ldr	r2, [pc, #576]	; (8003f38 <HAL_RCC_GetSysClockFreq+0x2d8>)
- 8003cf8:	fa22 f303 	lsr.w	r3, r2, r3
- 8003cfc:	61bb      	str	r3, [r7, #24]
-      else
-      {
-        sysclockfreq = (uint32_t) HSI_VALUE;
-      }
-
-      break;
- 8003cfe:	e111      	b.n	8003f24 <HAL_RCC_GetSysClockFreq+0x2c4>
-        sysclockfreq = (uint32_t) HSI_VALUE;
- 8003d00:	4b8d      	ldr	r3, [pc, #564]	; (8003f38 <HAL_RCC_GetSysClockFreq+0x2d8>)
- 8003d02:	61bb      	str	r3, [r7, #24]
-      break;
- 8003d04:	e10e      	b.n	8003f24 <HAL_RCC_GetSysClockFreq+0x2c4>
-
-    case RCC_CFGR_SWS_CSI:  /* CSI used as system clock  source */
-      sysclockfreq = CSI_VALUE;
- 8003d06:	4b8d      	ldr	r3, [pc, #564]	; (8003f3c <HAL_RCC_GetSysClockFreq+0x2dc>)
- 8003d08:	61bb      	str	r3, [r7, #24]
-      break;
- 8003d0a:	e10b      	b.n	8003f24 <HAL_RCC_GetSysClockFreq+0x2c4>
-
-    case RCC_CFGR_SWS_HSE:  /* HSE used as system clock  source */
-      sysclockfreq = HSE_VALUE;
- 8003d0c:	4b8c      	ldr	r3, [pc, #560]	; (8003f40 <HAL_RCC_GetSysClockFreq+0x2e0>)
- 8003d0e:	61bb      	str	r3, [r7, #24]
-      break;
- 8003d10:	e108      	b.n	8003f24 <HAL_RCC_GetSysClockFreq+0x2c4>
-    case RCC_CFGR_SWS_PLL1:  /* PLL1 used as system clock  source */
-
-      /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN
-      SYSCLK = PLL_VCO / PLLR
-      */
-      pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
- 8003d12:	4b88      	ldr	r3, [pc, #544]	; (8003f34 <HAL_RCC_GetSysClockFreq+0x2d4>)
- 8003d14:	6a9b      	ldr	r3, [r3, #40]	; 0x28
- 8003d16:	f003 0303 	and.w	r3, r3, #3
- 8003d1a:	617b      	str	r3, [r7, #20]
-      pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1) >> 4)  ;
- 8003d1c:	4b85      	ldr	r3, [pc, #532]	; (8003f34 <HAL_RCC_GetSysClockFreq+0x2d4>)
- 8003d1e:	6a9b      	ldr	r3, [r3, #40]	; 0x28
- 8003d20:	091b      	lsrs	r3, r3, #4
- 8003d22:	f003 033f 	and.w	r3, r3, #63	; 0x3f
- 8003d26:	613b      	str	r3, [r7, #16]
-      pllfracen = ((RCC-> PLLCFGR & RCC_PLLCFGR_PLL1FRACEN) >> RCC_PLLCFGR_PLL1FRACEN_Pos);
- 8003d28:	4b82      	ldr	r3, [pc, #520]	; (8003f34 <HAL_RCC_GetSysClockFreq+0x2d4>)
- 8003d2a:	6adb      	ldr	r3, [r3, #44]	; 0x2c
- 8003d2c:	f003 0301 	and.w	r3, r3, #1
- 8003d30:	60fb      	str	r3, [r7, #12]
-      fracn1 = (float_t)(uint32_t)(pllfracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> 3));
- 8003d32:	4b80      	ldr	r3, [pc, #512]	; (8003f34 <HAL_RCC_GetSysClockFreq+0x2d4>)
- 8003d34:	6b5b      	ldr	r3, [r3, #52]	; 0x34
- 8003d36:	08db      	lsrs	r3, r3, #3
- 8003d38:	f3c3 030c 	ubfx	r3, r3, #0, #13
- 8003d3c:	68fa      	ldr	r2, [r7, #12]
- 8003d3e:	fb02 f303 	mul.w	r3, r2, r3
- 8003d42:	ee07 3a90 	vmov	s15, r3
- 8003d46:	eef8 7a67 	vcvt.f32.u32	s15, s15
- 8003d4a:	edc7 7a02 	vstr	s15, [r7, #8]
-
-      if (pllm != 0U)
- 8003d4e:	693b      	ldr	r3, [r7, #16]
- 8003d50:	2b00      	cmp	r3, #0
- 8003d52:	f000 80e1 	beq.w	8003f18 <HAL_RCC_GetSysClockFreq+0x2b8>
- 8003d56:	697b      	ldr	r3, [r7, #20]
- 8003d58:	2b02      	cmp	r3, #2
- 8003d5a:	f000 8083 	beq.w	8003e64 <HAL_RCC_GetSysClockFreq+0x204>
- 8003d5e:	697b      	ldr	r3, [r7, #20]
- 8003d60:	2b02      	cmp	r3, #2
- 8003d62:	f200 80a1 	bhi.w	8003ea8 <HAL_RCC_GetSysClockFreq+0x248>
- 8003d66:	697b      	ldr	r3, [r7, #20]
- 8003d68:	2b00      	cmp	r3, #0
- 8003d6a:	d003      	beq.n	8003d74 <HAL_RCC_GetSysClockFreq+0x114>
- 8003d6c:	697b      	ldr	r3, [r7, #20]
- 8003d6e:	2b01      	cmp	r3, #1
- 8003d70:	d056      	beq.n	8003e20 <HAL_RCC_GetSysClockFreq+0x1c0>
- 8003d72:	e099      	b.n	8003ea8 <HAL_RCC_GetSysClockFreq+0x248>
-      {
-        switch (pllsource)
-        {
-          case RCC_PLLSOURCE_HSI:  /* HSI used as PLL clock source */
-
-            if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
- 8003d74:	4b6f      	ldr	r3, [pc, #444]	; (8003f34 <HAL_RCC_GetSysClockFreq+0x2d4>)
- 8003d76:	681b      	ldr	r3, [r3, #0]
- 8003d78:	f003 0320 	and.w	r3, r3, #32
- 8003d7c:	2b00      	cmp	r3, #0
- 8003d7e:	d02d      	beq.n	8003ddc <HAL_RCC_GetSysClockFreq+0x17c>
-            {
-              hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
- 8003d80:	4b6c      	ldr	r3, [pc, #432]	; (8003f34 <HAL_RCC_GetSysClockFreq+0x2d4>)
- 8003d82:	681b      	ldr	r3, [r3, #0]
- 8003d84:	08db      	lsrs	r3, r3, #3
- 8003d86:	f003 0303 	and.w	r3, r3, #3
- 8003d8a:	4a6b      	ldr	r2, [pc, #428]	; (8003f38 <HAL_RCC_GetSysClockFreq+0x2d8>)
- 8003d8c:	fa22 f303 	lsr.w	r3, r2, r3
- 8003d90:	607b      	str	r3, [r7, #4]
-              pllvco = ((float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
- 8003d92:	687b      	ldr	r3, [r7, #4]
- 8003d94:	ee07 3a90 	vmov	s15, r3
- 8003d98:	eef8 6a67 	vcvt.f32.u32	s13, s15
- 8003d9c:	693b      	ldr	r3, [r7, #16]
- 8003d9e:	ee07 3a90 	vmov	s15, r3
- 8003da2:	eef8 7a67 	vcvt.f32.u32	s15, s15
- 8003da6:	ee86 7aa7 	vdiv.f32	s14, s13, s15
- 8003daa:	4b62      	ldr	r3, [pc, #392]	; (8003f34 <HAL_RCC_GetSysClockFreq+0x2d4>)
- 8003dac:	6b1b      	ldr	r3, [r3, #48]	; 0x30
- 8003dae:	f3c3 0308 	ubfx	r3, r3, #0, #9
- 8003db2:	ee07 3a90 	vmov	s15, r3
- 8003db6:	eef8 6a67 	vcvt.f32.u32	s13, s15
- 8003dba:	ed97 6a02 	vldr	s12, [r7, #8]
- 8003dbe:	eddf 5a61 	vldr	s11, [pc, #388]	; 8003f44 <HAL_RCC_GetSysClockFreq+0x2e4>
- 8003dc2:	eec6 7a25 	vdiv.f32	s15, s12, s11
- 8003dc6:	ee76 7aa7 	vadd.f32	s15, s13, s15
- 8003dca:	eef7 6a00 	vmov.f32	s13, #112	; 0x3f800000  1.0
- 8003dce:	ee77 7aa6 	vadd.f32	s15, s15, s13
- 8003dd2:	ee67 7a27 	vmul.f32	s15, s14, s15
- 8003dd6:	edc7 7a07 	vstr	s15, [r7, #28]
-            }
-            else
-            {
-              pllvco = ((float_t)HSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
-            }
-            break;
- 8003dda:	e087      	b.n	8003eec <HAL_RCC_GetSysClockFreq+0x28c>
-              pllvco = ((float_t)HSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
- 8003ddc:	693b      	ldr	r3, [r7, #16]
- 8003dde:	ee07 3a90 	vmov	s15, r3
- 8003de2:	eef8 7a67 	vcvt.f32.u32	s15, s15
- 8003de6:	eddf 6a58 	vldr	s13, [pc, #352]	; 8003f48 <HAL_RCC_GetSysClockFreq+0x2e8>
- 8003dea:	ee86 7aa7 	vdiv.f32	s14, s13, s15
- 8003dee:	4b51      	ldr	r3, [pc, #324]	; (8003f34 <HAL_RCC_GetSysClockFreq+0x2d4>)
- 8003df0:	6b1b      	ldr	r3, [r3, #48]	; 0x30
- 8003df2:	f3c3 0308 	ubfx	r3, r3, #0, #9
- 8003df6:	ee07 3a90 	vmov	s15, r3
- 8003dfa:	eef8 6a67 	vcvt.f32.u32	s13, s15
- 8003dfe:	ed97 6a02 	vldr	s12, [r7, #8]
- 8003e02:	eddf 5a50 	vldr	s11, [pc, #320]	; 8003f44 <HAL_RCC_GetSysClockFreq+0x2e4>
- 8003e06:	eec6 7a25 	vdiv.f32	s15, s12, s11
- 8003e0a:	ee76 7aa7 	vadd.f32	s15, s13, s15
- 8003e0e:	eef7 6a00 	vmov.f32	s13, #112	; 0x3f800000  1.0
- 8003e12:	ee77 7aa6 	vadd.f32	s15, s15, s13
- 8003e16:	ee67 7a27 	vmul.f32	s15, s14, s15
- 8003e1a:	edc7 7a07 	vstr	s15, [r7, #28]
-            break;
- 8003e1e:	e065      	b.n	8003eec <HAL_RCC_GetSysClockFreq+0x28c>
-
-          case RCC_PLLSOURCE_CSI:  /* CSI used as PLL clock source */
-            pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
- 8003e20:	693b      	ldr	r3, [r7, #16]
- 8003e22:	ee07 3a90 	vmov	s15, r3
- 8003e26:	eef8 7a67 	vcvt.f32.u32	s15, s15
- 8003e2a:	eddf 6a48 	vldr	s13, [pc, #288]	; 8003f4c <HAL_RCC_GetSysClockFreq+0x2ec>
- 8003e2e:	ee86 7aa7 	vdiv.f32	s14, s13, s15
- 8003e32:	4b40      	ldr	r3, [pc, #256]	; (8003f34 <HAL_RCC_GetSysClockFreq+0x2d4>)
- 8003e34:	6b1b      	ldr	r3, [r3, #48]	; 0x30
- 8003e36:	f3c3 0308 	ubfx	r3, r3, #0, #9
- 8003e3a:	ee07 3a90 	vmov	s15, r3
- 8003e3e:	eef8 6a67 	vcvt.f32.u32	s13, s15
- 8003e42:	ed97 6a02 	vldr	s12, [r7, #8]
- 8003e46:	eddf 5a3f 	vldr	s11, [pc, #252]	; 8003f44 <HAL_RCC_GetSysClockFreq+0x2e4>
- 8003e4a:	eec6 7a25 	vdiv.f32	s15, s12, s11
- 8003e4e:	ee76 7aa7 	vadd.f32	s15, s13, s15
- 8003e52:	eef7 6a00 	vmov.f32	s13, #112	; 0x3f800000  1.0
- 8003e56:	ee77 7aa6 	vadd.f32	s15, s15, s13
- 8003e5a:	ee67 7a27 	vmul.f32	s15, s14, s15
- 8003e5e:	edc7 7a07 	vstr	s15, [r7, #28]
-            break;
- 8003e62:	e043      	b.n	8003eec <HAL_RCC_GetSysClockFreq+0x28c>
-
-          case RCC_PLLSOURCE_HSE:  /* HSE used as PLL clock source */
-            pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
- 8003e64:	693b      	ldr	r3, [r7, #16]
- 8003e66:	ee07 3a90 	vmov	s15, r3
- 8003e6a:	eef8 7a67 	vcvt.f32.u32	s15, s15
- 8003e6e:	eddf 6a38 	vldr	s13, [pc, #224]	; 8003f50 <HAL_RCC_GetSysClockFreq+0x2f0>
- 8003e72:	ee86 7aa7 	vdiv.f32	s14, s13, s15
- 8003e76:	4b2f      	ldr	r3, [pc, #188]	; (8003f34 <HAL_RCC_GetSysClockFreq+0x2d4>)
- 8003e78:	6b1b      	ldr	r3, [r3, #48]	; 0x30
- 8003e7a:	f3c3 0308 	ubfx	r3, r3, #0, #9
- 8003e7e:	ee07 3a90 	vmov	s15, r3
- 8003e82:	eef8 6a67 	vcvt.f32.u32	s13, s15
- 8003e86:	ed97 6a02 	vldr	s12, [r7, #8]
- 8003e8a:	eddf 5a2e 	vldr	s11, [pc, #184]	; 8003f44 <HAL_RCC_GetSysClockFreq+0x2e4>
- 8003e8e:	eec6 7a25 	vdiv.f32	s15, s12, s11
- 8003e92:	ee76 7aa7 	vadd.f32	s15, s13, s15
- 8003e96:	eef7 6a00 	vmov.f32	s13, #112	; 0x3f800000  1.0
- 8003e9a:	ee77 7aa6 	vadd.f32	s15, s15, s13
- 8003e9e:	ee67 7a27 	vmul.f32	s15, s14, s15
- 8003ea2:	edc7 7a07 	vstr	s15, [r7, #28]
-            break;
- 8003ea6:	e021      	b.n	8003eec <HAL_RCC_GetSysClockFreq+0x28c>
-
-          default:
-            pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
- 8003ea8:	693b      	ldr	r3, [r7, #16]
- 8003eaa:	ee07 3a90 	vmov	s15, r3
- 8003eae:	eef8 7a67 	vcvt.f32.u32	s15, s15
- 8003eb2:	eddf 6a26 	vldr	s13, [pc, #152]	; 8003f4c <HAL_RCC_GetSysClockFreq+0x2ec>
- 8003eb6:	ee86 7aa7 	vdiv.f32	s14, s13, s15
- 8003eba:	4b1e      	ldr	r3, [pc, #120]	; (8003f34 <HAL_RCC_GetSysClockFreq+0x2d4>)
- 8003ebc:	6b1b      	ldr	r3, [r3, #48]	; 0x30
- 8003ebe:	f3c3 0308 	ubfx	r3, r3, #0, #9
- 8003ec2:	ee07 3a90 	vmov	s15, r3
- 8003ec6:	eef8 6a67 	vcvt.f32.u32	s13, s15
- 8003eca:	ed97 6a02 	vldr	s12, [r7, #8]
- 8003ece:	eddf 5a1d 	vldr	s11, [pc, #116]	; 8003f44 <HAL_RCC_GetSysClockFreq+0x2e4>
- 8003ed2:	eec6 7a25 	vdiv.f32	s15, s12, s11
- 8003ed6:	ee76 7aa7 	vadd.f32	s15, s13, s15
- 8003eda:	eef7 6a00 	vmov.f32	s13, #112	; 0x3f800000  1.0
- 8003ede:	ee77 7aa6 	vadd.f32	s15, s15, s13
- 8003ee2:	ee67 7a27 	vmul.f32	s15, s14, s15
- 8003ee6:	edc7 7a07 	vstr	s15, [r7, #28]
-            break;
- 8003eea:	bf00      	nop
-        }
-        pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >> 9) + 1U) ;
- 8003eec:	4b11      	ldr	r3, [pc, #68]	; (8003f34 <HAL_RCC_GetSysClockFreq+0x2d4>)
- 8003eee:	6b1b      	ldr	r3, [r3, #48]	; 0x30
- 8003ef0:	0a5b      	lsrs	r3, r3, #9
- 8003ef2:	f003 037f 	and.w	r3, r3, #127	; 0x7f
- 8003ef6:	3301      	adds	r3, #1
- 8003ef8:	603b      	str	r3, [r7, #0]
-        sysclockfreq = (uint32_t)(float_t)(pllvco / (float_t)pllp);
- 8003efa:	683b      	ldr	r3, [r7, #0]
- 8003efc:	ee07 3a90 	vmov	s15, r3
- 8003f00:	eeb8 7a67 	vcvt.f32.u32	s14, s15
- 8003f04:	edd7 6a07 	vldr	s13, [r7, #28]
- 8003f08:	eec6 7a87 	vdiv.f32	s15, s13, s14
- 8003f0c:	eefc 7ae7 	vcvt.u32.f32	s15, s15
- 8003f10:	ee17 3a90 	vmov	r3, s15
- 8003f14:	61bb      	str	r3, [r7, #24]
-      }
-      else
-      {
-        sysclockfreq = 0U;
-      }
-      break;
- 8003f16:	e005      	b.n	8003f24 <HAL_RCC_GetSysClockFreq+0x2c4>
-        sysclockfreq = 0U;
- 8003f18:	2300      	movs	r3, #0
- 8003f1a:	61bb      	str	r3, [r7, #24]
-      break;
- 8003f1c:	e002      	b.n	8003f24 <HAL_RCC_GetSysClockFreq+0x2c4>
-
-    default:
-      sysclockfreq = CSI_VALUE;
- 8003f1e:	4b07      	ldr	r3, [pc, #28]	; (8003f3c <HAL_RCC_GetSysClockFreq+0x2dc>)
- 8003f20:	61bb      	str	r3, [r7, #24]
-      break;
- 8003f22:	bf00      	nop
-  }
-
-  return sysclockfreq;
- 8003f24:	69bb      	ldr	r3, [r7, #24]
-}
- 8003f26:	4618      	mov	r0, r3
- 8003f28:	3724      	adds	r7, #36	; 0x24
- 8003f2a:	46bd      	mov	sp, r7
- 8003f2c:	f85d 7b04 	ldr.w	r7, [sp], #4
- 8003f30:	4770      	bx	lr
- 8003f32:	bf00      	nop
- 8003f34:	58024400 	.word	0x58024400
- 8003f38:	03d09000 	.word	0x03d09000
- 8003f3c:	003d0900 	.word	0x003d0900
- 8003f40:	017d7840 	.word	0x017d7840
- 8003f44:	46000000 	.word	0x46000000
- 8003f48:	4c742400 	.word	0x4c742400
- 8003f4c:	4a742400 	.word	0x4a742400
- 8003f50:	4bbebc20 	.word	0x4bbebc20
-
-08003f54 <HAL_RCC_GetHCLKFreq>:
-  * @note   The SystemD2Clock CMSIS variable is used to store System domain2 Clock Frequency
-  *         and updated within this function
-  * @retval HCLK frequency
-  */
-uint32_t HAL_RCC_GetHCLKFreq(void)
-{
- 8003f54:	b580      	push	{r7, lr}
- 8003f56:	b082      	sub	sp, #8
- 8003f58:	af00      	add	r7, sp, #0
-  uint32_t common_system_clock;
-
-#if defined(RCC_D1CFGR_D1CPRE)
-  common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE) >> RCC_D1CFGR_D1CPRE_Pos] & 0x1FU);
- 8003f5a:	f7ff fe81 	bl	8003c60 <HAL_RCC_GetSysClockFreq>
- 8003f5e:	4602      	mov	r2, r0
- 8003f60:	4b10      	ldr	r3, [pc, #64]	; (8003fa4 <HAL_RCC_GetHCLKFreq+0x50>)
- 8003f62:	699b      	ldr	r3, [r3, #24]
- 8003f64:	0a1b      	lsrs	r3, r3, #8
- 8003f66:	f003 030f 	and.w	r3, r3, #15
- 8003f6a:	490f      	ldr	r1, [pc, #60]	; (8003fa8 <HAL_RCC_GetHCLKFreq+0x54>)
- 8003f6c:	5ccb      	ldrb	r3, [r1, r3]
- 8003f6e:	f003 031f 	and.w	r3, r3, #31
- 8003f72:	fa22 f303 	lsr.w	r3, r2, r3
- 8003f76:	607b      	str	r3, [r7, #4]
-#else
-  common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE) >> RCC_CDCFGR1_CDCPRE_Pos] & 0x1FU);
-#endif
-
-#if defined(RCC_D1CFGR_HPRE)
-  SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE) >> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
- 8003f78:	4b0a      	ldr	r3, [pc, #40]	; (8003fa4 <HAL_RCC_GetHCLKFreq+0x50>)
- 8003f7a:	699b      	ldr	r3, [r3, #24]
- 8003f7c:	f003 030f 	and.w	r3, r3, #15
- 8003f80:	4a09      	ldr	r2, [pc, #36]	; (8003fa8 <HAL_RCC_GetHCLKFreq+0x54>)
- 8003f82:	5cd3      	ldrb	r3, [r2, r3]
- 8003f84:	f003 031f 	and.w	r3, r3, #31
- 8003f88:	687a      	ldr	r2, [r7, #4]
- 8003f8a:	fa22 f303 	lsr.w	r3, r2, r3
- 8003f8e:	4a07      	ldr	r2, [pc, #28]	; (8003fac <HAL_RCC_GetHCLKFreq+0x58>)
- 8003f90:	6013      	str	r3, [r2, #0]
-#endif
-
-#if defined(DUAL_CORE) && defined(CORE_CM4)
-  SystemCoreClock = SystemD2Clock;
-#else
-  SystemCoreClock = common_system_clock;
- 8003f92:	4a07      	ldr	r2, [pc, #28]	; (8003fb0 <HAL_RCC_GetHCLKFreq+0x5c>)
- 8003f94:	687b      	ldr	r3, [r7, #4]
- 8003f96:	6013      	str	r3, [r2, #0]
-#endif /* DUAL_CORE && CORE_CM4 */
-
-  return SystemD2Clock;
- 8003f98:	4b04      	ldr	r3, [pc, #16]	; (8003fac <HAL_RCC_GetHCLKFreq+0x58>)
- 8003f9a:	681b      	ldr	r3, [r3, #0]
-}
- 8003f9c:	4618      	mov	r0, r3
- 8003f9e:	3708      	adds	r7, #8
- 8003fa0:	46bd      	mov	sp, r7
- 8003fa2:	bd80      	pop	{r7, pc}
- 8003fa4:	58024400 	.word	0x58024400
- 8003fa8:	08014c80 	.word	0x08014c80
- 8003fac:	24000004 	.word	0x24000004
- 8003fb0:	24000000 	.word	0x24000000
-
-08003fb4 <lwftp_pcb_close>:
-		struct pbuf *p);
-
-/** Close control or data pcb
- * @param pointer to lwftp session data
- */
-static err_t lwftp_pcb_close(struct tcp_pcb *tpcb) {
- 8003fb4:	b580      	push	{r7, lr}
- 8003fb6:	b084      	sub	sp, #16
- 8003fb8:	af00      	add	r7, sp, #0
- 8003fba:	6078      	str	r0, [r7, #4]
-	err_t error;
-
-	tcp_err(tpcb, NULL);
- 8003fbc:	2100      	movs	r1, #0
- 8003fbe:	6878      	ldr	r0, [r7, #4]
- 8003fc0:	f004 fe24 	bl	8008c0c <tcp_err>
-	tcp_recv(tpcb, NULL);
- 8003fc4:	2100      	movs	r1, #0
- 8003fc6:	6878      	ldr	r0, [r7, #4]
- 8003fc8:	f004 fddc 	bl	8008b84 <tcp_recv>
-	tcp_sent(tpcb, NULL);
- 8003fcc:	2100      	movs	r1, #0
- 8003fce:	6878      	ldr	r0, [r7, #4]
- 8003fd0:	f004 fdfa 	bl	8008bc8 <tcp_sent>
-	error = tcp_close(tpcb);
- 8003fd4:	6878      	ldr	r0, [r7, #4]
- 8003fd6:	f003 fc9b 	bl	8007910 <tcp_close>
- 8003fda:	4603      	mov	r3, r0
- 8003fdc:	73fb      	strb	r3, [r7, #15]
-	if (error != ERR_OK) {
- 8003fde:	f997 300f 	ldrsb.w	r3, [r7, #15]
- 8003fe2:	2b00      	cmp	r3, #0
- 8003fe4:	d002      	beq.n	8003fec <lwftp_pcb_close+0x38>
-		LWIP_DEBUGF(LWFTP_SEVERE, ("lwftp:pcb close failure, not implemented\n"));
- 8003fe6:	4804      	ldr	r0, [pc, #16]	; (8003ff8 <lwftp_pcb_close+0x44>)
- 8003fe8:	f00c fe5c 	bl	8010ca4 <puts>
-	}
-	return ERR_OK;
- 8003fec:	2300      	movs	r3, #0
-}
- 8003fee:	4618      	mov	r0, r3
- 8003ff0:	3710      	adds	r7, #16
- 8003ff2:	46bd      	mov	sp, r7
- 8003ff4:	bd80      	pop	{r7, pc}
- 8003ff6:	bf00      	nop
- 8003ff8:	0801167c 	.word	0x0801167c
-
-08003ffc <lwftp_send_next_data>:
-/** Send data
- * @param pointer to lwftp session data
- * @param pointer to PCB
- * @param number of bytes sent
- */
-static err_t lwftp_send_next_data(lwftp_session_t *s) {
- 8003ffc:	b580      	push	{r7, lr}
- 8003ffe:	b086      	sub	sp, #24
- 8004000:	af00      	add	r7, sp, #0
- 8004002:	6078      	str	r0, [r7, #4]
-	const char *data;
-	int len = 0;
- 8004004:	2300      	movs	r3, #0
- 8004006:	617b      	str	r3, [r7, #20]
-	err_t error = ERR_OK;
- 8004008:	2300      	movs	r3, #0
- 800400a:	74fb      	strb	r3, [r7, #19]
-
-	if (s->data_source) {
- 800400c:	687b      	ldr	r3, [r7, #4]
- 800400e:	699b      	ldr	r3, [r3, #24]
- 8004010:	2b00      	cmp	r3, #0
- 8004012:	d026      	beq.n	8004062 <lwftp_send_next_data+0x66>
-		len = s->data_source(s->handle, &data, s->data_pcb->mss);
- 8004014:	687b      	ldr	r3, [r7, #4]
- 8004016:	699b      	ldr	r3, [r3, #24]
- 8004018:	687a      	ldr	r2, [r7, #4]
- 800401a:	6950      	ldr	r0, [r2, #20]
- 800401c:	687a      	ldr	r2, [r7, #4]
- 800401e:	6b12      	ldr	r2, [r2, #48]	; 0x30
- 8004020:	8e52      	ldrh	r2, [r2, #50]	; 0x32
- 8004022:	f107 010c 	add.w	r1, r7, #12
- 8004026:	4798      	blx	r3
- 8004028:	4603      	mov	r3, r0
- 800402a:	617b      	str	r3, [r7, #20]
-		if (len) {
- 800402c:	697b      	ldr	r3, [r7, #20]
- 800402e:	2b00      	cmp	r3, #0
- 8004030:	d017      	beq.n	8004062 <lwftp_send_next_data+0x66>
-			error = tcp_write(s->data_pcb, data, len, 0);
- 8004032:	687b      	ldr	r3, [r7, #4]
- 8004034:	6b18      	ldr	r0, [r3, #48]	; 0x30
- 8004036:	68f9      	ldr	r1, [r7, #12]
- 8004038:	697b      	ldr	r3, [r7, #20]
- 800403a:	b29a      	uxth	r2, r3
- 800403c:	2300      	movs	r3, #0
- 800403e:	f007 fc91 	bl	800b964 <tcp_write>
- 8004042:	4603      	mov	r3, r0
- 8004044:	74fb      	strb	r3, [r7, #19]
-			if (error != ERR_OK) {
- 8004046:	f997 3013 	ldrsb.w	r3, [r7, #19]
- 800404a:	2b00      	cmp	r3, #0
- 800404c:	d009      	beq.n	8004062 <lwftp_send_next_data+0x66>
-				LWIP_DEBUGF(LWFTP_SEVERE, ("lwftp:write failure (%s), not implemented\n",lwip_strerr(error)));
- 800404e:	f997 3013 	ldrsb.w	r3, [r7, #19]
- 8004052:	4618      	mov	r0, r3
- 8004054:	f001 fa5a 	bl	800550c <lwip_strerr>
- 8004058:	4603      	mov	r3, r0
- 800405a:	4619      	mov	r1, r3
- 800405c:	480a      	ldr	r0, [pc, #40]	; (8004088 <lwftp_send_next_data+0x8c>)
- 800405e:	f00c fdb3 	bl	8010bc8 <iprintf>
-			}
-		}
-	}
-	if (!len) {
- 8004062:	697b      	ldr	r3, [r7, #20]
- 8004064:	2b00      	cmp	r3, #0
- 8004066:	d10a      	bne.n	800407e <lwftp_send_next_data+0x82>
-		LWIP_DEBUGF(LWFTP_STATE, ("lwftp:end of file\n"));
- 8004068:	4808      	ldr	r0, [pc, #32]	; (800408c <lwftp_send_next_data+0x90>)
- 800406a:	f00c fe1b 	bl	8010ca4 <puts>
-		lwftp_pcb_close(s->data_pcb);
- 800406e:	687b      	ldr	r3, [r7, #4]
- 8004070:	6b1b      	ldr	r3, [r3, #48]	; 0x30
- 8004072:	4618      	mov	r0, r3
- 8004074:	f7ff ff9e 	bl	8003fb4 <lwftp_pcb_close>
-		s->data_pcb = NULL;
- 8004078:	687b      	ldr	r3, [r7, #4]
- 800407a:	2200      	movs	r2, #0
- 800407c:	631a      	str	r2, [r3, #48]	; 0x30
-	}
-	return ERR_OK;
- 800407e:	2300      	movs	r3, #0
-}
- 8004080:	4618      	mov	r0, r3
- 8004082:	3718      	adds	r7, #24
- 8004084:	46bd      	mov	sp, r7
- 8004086:	bd80      	pop	{r7, pc}
- 8004088:	080116a8 	.word	0x080116a8
- 800408c:	080116d4 	.word	0x080116d4
-
-08004090 <lwftp_data_recv>:
- * @param pointer to PCB
- * @param pointer to incoming pbuf
- * @param state of incoming process
- */
-static err_t lwftp_data_recv(void *arg, struct tcp_pcb *tpcb, struct pbuf *p,
-		err_t err) {
- 8004090:	b580      	push	{r7, lr}
- 8004092:	b086      	sub	sp, #24
- 8004094:	af00      	add	r7, sp, #0
- 8004096:	60f8      	str	r0, [r7, #12]
- 8004098:	60b9      	str	r1, [r7, #8]
- 800409a:	607a      	str	r2, [r7, #4]
- 800409c:	70fb      	strb	r3, [r7, #3]
-	lwftp_session_t *s = (lwftp_session_t*) arg;
- 800409e:	68fb      	ldr	r3, [r7, #12]
- 80040a0:	613b      	str	r3, [r7, #16]
-	if (p) {
- 80040a2:	687b      	ldr	r3, [r7, #4]
- 80040a4:	2b00      	cmp	r3, #0
- 80040a6:	d026      	beq.n	80040f6 <lwftp_data_recv+0x66>
-		if (s->data_sink) {
- 80040a8:	693b      	ldr	r3, [r7, #16]
- 80040aa:	69db      	ldr	r3, [r3, #28]
- 80040ac:	2b00      	cmp	r3, #0
- 80040ae:	d012      	beq.n	80040d6 <lwftp_data_recv+0x46>
-			struct pbuf *q;
-			for (q = p; q; q = q->next) {
- 80040b0:	687b      	ldr	r3, [r7, #4]
- 80040b2:	617b      	str	r3, [r7, #20]
- 80040b4:	e00b      	b.n	80040ce <lwftp_data_recv+0x3e>
-				s->data_sink(s->handle, q->payload, q->len);
- 80040b6:	693b      	ldr	r3, [r7, #16]
- 80040b8:	69db      	ldr	r3, [r3, #28]
- 80040ba:	693a      	ldr	r2, [r7, #16]
- 80040bc:	6950      	ldr	r0, [r2, #20]
- 80040be:	697a      	ldr	r2, [r7, #20]
- 80040c0:	6851      	ldr	r1, [r2, #4]
- 80040c2:	697a      	ldr	r2, [r7, #20]
- 80040c4:	8952      	ldrh	r2, [r2, #10]
- 80040c6:	4798      	blx	r3
-			for (q = p; q; q = q->next) {
- 80040c8:	697b      	ldr	r3, [r7, #20]
- 80040ca:	681b      	ldr	r3, [r3, #0]
- 80040cc:	617b      	str	r3, [r7, #20]
- 80040ce:	697b      	ldr	r3, [r7, #20]
- 80040d0:	2b00      	cmp	r3, #0
- 80040d2:	d1f0      	bne.n	80040b6 <lwftp_data_recv+0x26>
- 80040d4:	e005      	b.n	80040e2 <lwftp_data_recv+0x52>
-			}
-		} else {
-			LWIP_DEBUGF(LWFTP_SEVERE, ("lwftp: sinking %d bytes\n",p->tot_len));
- 80040d6:	687b      	ldr	r3, [r7, #4]
- 80040d8:	891b      	ldrh	r3, [r3, #8]
- 80040da:	4619      	mov	r1, r3
- 80040dc:	480e      	ldr	r0, [pc, #56]	; (8004118 <lwftp_data_recv+0x88>)
- 80040de:	f00c fd73 	bl	8010bc8 <iprintf>
-		}
-		tcp_recved(tpcb, p->tot_len);
- 80040e2:	687b      	ldr	r3, [r7, #4]
- 80040e4:	891b      	ldrh	r3, [r3, #8]
- 80040e6:	4619      	mov	r1, r3
- 80040e8:	68b8      	ldr	r0, [r7, #8]
- 80040ea:	f003 fd61 	bl	8007bb0 <tcp_recved>
-		pbuf_free(p);
- 80040ee:	6878      	ldr	r0, [r7, #4]
- 80040f0:	f002 ff70 	bl	8006fd4 <pbuf_free>
- 80040f4:	e00a      	b.n	800410c <lwftp_data_recv+0x7c>
-	} else {
-		// NULL pbuf shall lead to close the pcb. Close is postponed after
-		// the session state machine updates. No need to close right here.
-		// Instead we kindly tell data sink we are done
-		if (s->data_sink) {
- 80040f6:	693b      	ldr	r3, [r7, #16]
- 80040f8:	69db      	ldr	r3, [r3, #28]
- 80040fa:	2b00      	cmp	r3, #0
- 80040fc:	d006      	beq.n	800410c <lwftp_data_recv+0x7c>
-			s->data_sink(s->handle, NULL, 0);
- 80040fe:	693b      	ldr	r3, [r7, #16]
- 8004100:	69db      	ldr	r3, [r3, #28]
- 8004102:	693a      	ldr	r2, [r7, #16]
- 8004104:	6950      	ldr	r0, [r2, #20]
- 8004106:	2200      	movs	r2, #0
- 8004108:	2100      	movs	r1, #0
- 800410a:	4798      	blx	r3
-		}
-	}
-	return ERR_OK;
- 800410c:	2300      	movs	r3, #0
-}
- 800410e:	4618      	mov	r0, r3
- 8004110:	3718      	adds	r7, #24
- 8004112:	46bd      	mov	sp, r7
- 8004114:	bd80      	pop	{r7, pc}
- 8004116:	bf00      	nop
- 8004118:	080116e8 	.word	0x080116e8
-
-0800411c <lwftp_data_sent>:
-/** Handle data connection acknowledge of sent data
- * @param pointer to lwftp session data
- * @param pointer to PCB
- * @param number of bytes sent
- */
-static err_t lwftp_data_sent(void *arg, struct tcp_pcb *tpcb, u16_t len) {
- 800411c:	b580      	push	{r7, lr}
- 800411e:	b086      	sub	sp, #24
- 8004120:	af00      	add	r7, sp, #0
- 8004122:	60f8      	str	r0, [r7, #12]
- 8004124:	60b9      	str	r1, [r7, #8]
- 8004126:	4613      	mov	r3, r2
- 8004128:	80fb      	strh	r3, [r7, #6]
-	lwftp_session_t *s = (lwftp_session_t*) arg;
- 800412a:	68fb      	ldr	r3, [r7, #12]
- 800412c:	617b      	str	r3, [r7, #20]
-
-	if (s->data_source) {
- 800412e:	697b      	ldr	r3, [r7, #20]
- 8004130:	699b      	ldr	r3, [r3, #24]
- 8004132:	2b00      	cmp	r3, #0
- 8004134:	d006      	beq.n	8004144 <lwftp_data_sent+0x28>
-		s->data_source(s->handle, NULL, len);
- 8004136:	697b      	ldr	r3, [r7, #20]
- 8004138:	699b      	ldr	r3, [r3, #24]
- 800413a:	697a      	ldr	r2, [r7, #20]
- 800413c:	6950      	ldr	r0, [r2, #20]
- 800413e:	88fa      	ldrh	r2, [r7, #6]
- 8004140:	2100      	movs	r1, #0
- 8004142:	4798      	blx	r3
-	}
-	return lwftp_send_next_data(s);
- 8004144:	6978      	ldr	r0, [r7, #20]
- 8004146:	f7ff ff59 	bl	8003ffc <lwftp_send_next_data>
- 800414a:	4603      	mov	r3, r0
-}
- 800414c:	4618      	mov	r0, r3
- 800414e:	3718      	adds	r7, #24
- 8004150:	46bd      	mov	sp, r7
- 8004152:	bd80      	pop	{r7, pc}
-
-08004154 <lwftp_data_err>:
-
-/** Handle data connection error
- * @param pointer to lwftp session data
- * @param state of connection
- */
-static void lwftp_data_err(void *arg, err_t err) {
- 8004154:	b580      	push	{r7, lr}
- 8004156:	b084      	sub	sp, #16
- 8004158:	af00      	add	r7, sp, #0
- 800415a:	6078      	str	r0, [r7, #4]
- 800415c:	460b      	mov	r3, r1
- 800415e:	70fb      	strb	r3, [r7, #3]
-	LWIP_UNUSED_ARG(err);
-	if (arg != NULL) {
- 8004160:	687b      	ldr	r3, [r7, #4]
- 8004162:	2b00      	cmp	r3, #0
- 8004164:	d01c      	beq.n	80041a0 <lwftp_data_err+0x4c>
-		lwftp_session_t *s = (lwftp_session_t*) arg;
- 8004166:	687b      	ldr	r3, [r7, #4]
- 8004168:	60fb      	str	r3, [r7, #12]
-		LWIP_DEBUGF(LWFTP_WARNING, ("lwftp:failed/error connecting for data to server (%s)\n",lwip_strerr(err)));
- 800416a:	f997 3003 	ldrsb.w	r3, [r7, #3]
- 800416e:	4618      	mov	r0, r3
- 8004170:	f001 f9cc 	bl	800550c <lwip_strerr>
- 8004174:	4603      	mov	r3, r0
- 8004176:	4619      	mov	r1, r3
- 8004178:	480b      	ldr	r0, [pc, #44]	; (80041a8 <lwftp_data_err+0x54>)
- 800417a:	f00c fd25 	bl	8010bc8 <iprintf>
-		s->data_pcb = NULL; // No need to de-allocate PCB
- 800417e:	68fb      	ldr	r3, [r7, #12]
- 8004180:	2200      	movs	r2, #0
- 8004182:	631a      	str	r2, [r3, #48]	; 0x30
-		if (s->control_state == LWFTP_XFERING) { // gracefully move control session ahead
- 8004184:	68fb      	ldr	r3, [r7, #12]
- 8004186:	f893 3028 	ldrb.w	r3, [r3, #40]	; 0x28
- 800418a:	2b09      	cmp	r3, #9
- 800418c:	d108      	bne.n	80041a0 <lwftp_data_err+0x4c>
-			s->control_state = LWFTP_DATAEND;
- 800418e:	68fb      	ldr	r3, [r7, #12]
- 8004190:	220a      	movs	r2, #10
- 8004192:	f883 2028 	strb.w	r2, [r3, #40]	; 0x28
-			lwftp_control_process(s, NULL, NULL);
- 8004196:	2200      	movs	r2, #0
- 8004198:	2100      	movs	r1, #0
- 800419a:	68f8      	ldr	r0, [r7, #12]
- 800419c:	f000 f97c 	bl	8004498 <lwftp_control_process>
-		}
-	}
-}
- 80041a0:	bf00      	nop
- 80041a2:	3710      	adds	r7, #16
- 80041a4:	46bd      	mov	sp, r7
- 80041a6:	bd80      	pop	{r7, pc}
- 80041a8:	08011704 	.word	0x08011704
-
-080041ac <lwftp_data_connected>:
-/** Process newly connected PCB
- * @param pointer to lwftp session data
- * @param pointer to PCB
- * @param state of connection
- */
-static err_t lwftp_data_connected(void *arg, struct tcp_pcb *tpcb, err_t err) {
- 80041ac:	b580      	push	{r7, lr}
- 80041ae:	b086      	sub	sp, #24
- 80041b0:	af00      	add	r7, sp, #0
- 80041b2:	60f8      	str	r0, [r7, #12]
- 80041b4:	60b9      	str	r1, [r7, #8]
- 80041b6:	4613      	mov	r3, r2
- 80041b8:	71fb      	strb	r3, [r7, #7]
-	lwftp_session_t *s = (lwftp_session_t*) arg;
- 80041ba:	68fb      	ldr	r3, [r7, #12]
- 80041bc:	617b      	str	r3, [r7, #20]
-
-	if (err == ERR_OK) {
- 80041be:	f997 3007 	ldrsb.w	r3, [r7, #7]
- 80041c2:	2b00      	cmp	r3, #0
- 80041c4:	d107      	bne.n	80041d6 <lwftp_data_connected+0x2a>
-		LWIP_DEBUGF(LWFTP_STATE, ("lwftp:connected for data to server\n"));
- 80041c6:	480c      	ldr	r0, [pc, #48]	; (80041f8 <lwftp_data_connected+0x4c>)
- 80041c8:	f00c fd6c 	bl	8010ca4 <puts>
-		s->data_state = LWFTP_CONNECTED;
- 80041cc:	697b      	ldr	r3, [r7, #20]
- 80041ce:	2201      	movs	r2, #1
- 80041d0:	f883 202a 	strb.w	r2, [r3, #42]	; 0x2a
- 80041d4:	e009      	b.n	80041ea <lwftp_data_connected+0x3e>
-	} else {
-		LWIP_DEBUGF(LWFTP_WARNING, ("lwftp:err in data_connected (%s)\n",lwip_strerr(err)));
- 80041d6:	f997 3007 	ldrsb.w	r3, [r7, #7]
- 80041da:	4618      	mov	r0, r3
- 80041dc:	f001 f996 	bl	800550c <lwip_strerr>
- 80041e0:	4603      	mov	r3, r0
- 80041e2:	4619      	mov	r1, r3
- 80041e4:	4805      	ldr	r0, [pc, #20]	; (80041fc <lwftp_data_connected+0x50>)
- 80041e6:	f00c fcef 	bl	8010bc8 <iprintf>
-	}
-	return err;
- 80041ea:	f997 3007 	ldrsb.w	r3, [r7, #7]
-}
- 80041ee:	4618      	mov	r0, r3
- 80041f0:	3718      	adds	r7, #24
- 80041f2:	46bd      	mov	sp, r7
- 80041f4:	bd80      	pop	{r7, pc}
- 80041f6:	bf00      	nop
- 80041f8:	0801173c 	.word	0x0801173c
- 80041fc:	08011760 	.word	0x08011760
-
-08004200 <lwftp_data_open>:
-
-/** Open data connection for passive transfer
- * @param pointer to lwftp session data
- * @param pointer to incoming PASV response
- */
-static err_t lwftp_data_open(lwftp_session_t *s, struct pbuf *p) {
- 8004200:	b580      	push	{r7, lr}
- 8004202:	b08a      	sub	sp, #40	; 0x28
- 8004204:	af00      	add	r7, sp, #0
- 8004206:	6078      	str	r0, [r7, #4]
- 8004208:	6039      	str	r1, [r7, #0]
-	char *ptr;
-	ip_addr_t data_server;
-	u16_t data_port;
-
-	// Find server connection parameter
-	ptr = strchr(p->payload, '(');
- 800420a:	683b      	ldr	r3, [r7, #0]
- 800420c:	685b      	ldr	r3, [r3, #4]
- 800420e:	2128      	movs	r1, #40	; 0x28
- 8004210:	4618      	mov	r0, r3
- 8004212:	f00c fe3f 	bl	8010e94 <strchr>
- 8004216:	4603      	mov	r3, r0
- 8004218:	613b      	str	r3, [r7, #16]
-	if (!ptr)
- 800421a:	693b      	ldr	r3, [r7, #16]
- 800421c:	2b00      	cmp	r3, #0
- 800421e:	d102      	bne.n	8004226 <lwftp_data_open+0x26>
-		return ERR_BUF;
- 8004220:	f06f 0301 	mvn.w	r3, #1
- 8004224:	e0ac      	b.n	8004380 <lwftp_data_open+0x180>
-	do {
-		unsigned int a = strtoul(ptr + 1, &ptr, 10);
- 8004226:	693b      	ldr	r3, [r7, #16]
- 8004228:	3301      	adds	r3, #1
- 800422a:	f107 0110 	add.w	r1, r7, #16
- 800422e:	220a      	movs	r2, #10
- 8004230:	4618      	mov	r0, r3
- 8004232:	f00c f8c5 	bl	80103c0 <strtoul>
- 8004236:	6278      	str	r0, [r7, #36]	; 0x24
-		unsigned int b = strtoul(ptr + 1, &ptr, 10);
- 8004238:	693b      	ldr	r3, [r7, #16]
- 800423a:	3301      	adds	r3, #1
- 800423c:	f107 0110 	add.w	r1, r7, #16
- 8004240:	220a      	movs	r2, #10
- 8004242:	4618      	mov	r0, r3
- 8004244:	f00c f8bc 	bl	80103c0 <strtoul>
- 8004248:	6238      	str	r0, [r7, #32]
-		unsigned int c = strtoul(ptr + 1, &ptr, 10);
- 800424a:	693b      	ldr	r3, [r7, #16]
- 800424c:	3301      	adds	r3, #1
- 800424e:	f107 0110 	add.w	r1, r7, #16
- 8004252:	220a      	movs	r2, #10
- 8004254:	4618      	mov	r0, r3
- 8004256:	f00c f8b3 	bl	80103c0 <strtoul>
- 800425a:	61f8      	str	r0, [r7, #28]
-		unsigned int d = strtoul(ptr + 1, &ptr, 10);
- 800425c:	693b      	ldr	r3, [r7, #16]
- 800425e:	3301      	adds	r3, #1
- 8004260:	f107 0110 	add.w	r1, r7, #16
- 8004264:	220a      	movs	r2, #10
- 8004266:	4618      	mov	r0, r3
- 8004268:	f00c f8aa 	bl	80103c0 <strtoul>
- 800426c:	61b8      	str	r0, [r7, #24]
-		IP4_ADDR(&data_server, a, b, c, d);
- 800426e:	6a7b      	ldr	r3, [r7, #36]	; 0x24
- 8004270:	061a      	lsls	r2, r3, #24
- 8004272:	6a3b      	ldr	r3, [r7, #32]
- 8004274:	041b      	lsls	r3, r3, #16
- 8004276:	f403 037f 	and.w	r3, r3, #16711680	; 0xff0000
- 800427a:	431a      	orrs	r2, r3
- 800427c:	69fb      	ldr	r3, [r7, #28]
- 800427e:	021b      	lsls	r3, r3, #8
- 8004280:	b29b      	uxth	r3, r3
- 8004282:	431a      	orrs	r2, r3
- 8004284:	69bb      	ldr	r3, [r7, #24]
- 8004286:	b2db      	uxtb	r3, r3
- 8004288:	4313      	orrs	r3, r2
- 800428a:	061a      	lsls	r2, r3, #24
- 800428c:	6a7b      	ldr	r3, [r7, #36]	; 0x24
- 800428e:	0619      	lsls	r1, r3, #24
- 8004290:	6a3b      	ldr	r3, [r7, #32]
- 8004292:	041b      	lsls	r3, r3, #16
- 8004294:	f403 037f 	and.w	r3, r3, #16711680	; 0xff0000
- 8004298:	4319      	orrs	r1, r3
- 800429a:	69fb      	ldr	r3, [r7, #28]
- 800429c:	021b      	lsls	r3, r3, #8
- 800429e:	b29b      	uxth	r3, r3
- 80042a0:	4319      	orrs	r1, r3
- 80042a2:	69bb      	ldr	r3, [r7, #24]
- 80042a4:	b2db      	uxtb	r3, r3
- 80042a6:	430b      	orrs	r3, r1
- 80042a8:	021b      	lsls	r3, r3, #8
- 80042aa:	f403 037f 	and.w	r3, r3, #16711680	; 0xff0000
- 80042ae:	431a      	orrs	r2, r3
- 80042b0:	6a7b      	ldr	r3, [r7, #36]	; 0x24
- 80042b2:	0619      	lsls	r1, r3, #24
- 80042b4:	6a3b      	ldr	r3, [r7, #32]
- 80042b6:	041b      	lsls	r3, r3, #16
- 80042b8:	f403 037f 	and.w	r3, r3, #16711680	; 0xff0000
- 80042bc:	4319      	orrs	r1, r3
- 80042be:	69fb      	ldr	r3, [r7, #28]
- 80042c0:	021b      	lsls	r3, r3, #8
- 80042c2:	b29b      	uxth	r3, r3
- 80042c4:	4319      	orrs	r1, r3
- 80042c6:	69bb      	ldr	r3, [r7, #24]
- 80042c8:	b2db      	uxtb	r3, r3
- 80042ca:	430b      	orrs	r3, r1
- 80042cc:	0a1b      	lsrs	r3, r3, #8
- 80042ce:	f403 437f 	and.w	r3, r3, #65280	; 0xff00
- 80042d2:	431a      	orrs	r2, r3
- 80042d4:	6a7b      	ldr	r3, [r7, #36]	; 0x24
- 80042d6:	0619      	lsls	r1, r3, #24
- 80042d8:	6a3b      	ldr	r3, [r7, #32]
- 80042da:	041b      	lsls	r3, r3, #16
- 80042dc:	f403 037f 	and.w	r3, r3, #16711680	; 0xff0000
- 80042e0:	4319      	orrs	r1, r3
- 80042e2:	69fb      	ldr	r3, [r7, #28]
- 80042e4:	021b      	lsls	r3, r3, #8
- 80042e6:	b29b      	uxth	r3, r3
- 80042e8:	4319      	orrs	r1, r3
- 80042ea:	69bb      	ldr	r3, [r7, #24]
- 80042ec:	b2db      	uxtb	r3, r3
- 80042ee:	430b      	orrs	r3, r1
- 80042f0:	0e1b      	lsrs	r3, r3, #24
- 80042f2:	4313      	orrs	r3, r2
- 80042f4:	60fb      	str	r3, [r7, #12]
-	} while (0);
-	data_port = strtoul(ptr + 1, &ptr, 10) << 8;
- 80042f6:	693b      	ldr	r3, [r7, #16]
- 80042f8:	3301      	adds	r3, #1
- 80042fa:	f107 0110 	add.w	r1, r7, #16
- 80042fe:	220a      	movs	r2, #10
- 8004300:	4618      	mov	r0, r3
- 8004302:	f00c f85d 	bl	80103c0 <strtoul>
- 8004306:	4603      	mov	r3, r0
- 8004308:	b29b      	uxth	r3, r3
- 800430a:	021b      	lsls	r3, r3, #8
- 800430c:	82fb      	strh	r3, [r7, #22]
-	data_port |= strtoul(ptr + 1, &ptr, 10) & 255;
- 800430e:	693b      	ldr	r3, [r7, #16]
- 8004310:	3301      	adds	r3, #1
- 8004312:	f107 0110 	add.w	r1, r7, #16
- 8004316:	220a      	movs	r2, #10
- 8004318:	4618      	mov	r0, r3
- 800431a:	f00c f851 	bl	80103c0 <strtoul>
- 800431e:	4603      	mov	r3, r0
- 8004320:	b2db      	uxtb	r3, r3
- 8004322:	b29a      	uxth	r2, r3
- 8004324:	8afb      	ldrh	r3, [r7, #22]
- 8004326:	4313      	orrs	r3, r2
- 8004328:	82fb      	strh	r3, [r7, #22]
-	if (*ptr != ')')
- 800432a:	693b      	ldr	r3, [r7, #16]
- 800432c:	781b      	ldrb	r3, [r3, #0]
- 800432e:	2b29      	cmp	r3, #41	; 0x29
- 8004330:	d002      	beq.n	8004338 <lwftp_data_open+0x138>
-		return ERR_BUF;
- 8004332:	f06f 0301 	mvn.w	r3, #1
- 8004336:	e023      	b.n	8004380 <lwftp_data_open+0x180>
-
-	// Open data session
-	tcp_arg(s->data_pcb, s);
- 8004338:	687b      	ldr	r3, [r7, #4]
- 800433a:	6b1b      	ldr	r3, [r3, #48]	; 0x30
- 800433c:	6879      	ldr	r1, [r7, #4]
- 800433e:	4618      	mov	r0, r3
- 8004340:	f004 fc0e 	bl	8008b60 <tcp_arg>
-	tcp_err(s->data_pcb, lwftp_data_err);
- 8004344:	687b      	ldr	r3, [r7, #4]
- 8004346:	6b1b      	ldr	r3, [r3, #48]	; 0x30
- 8004348:	490f      	ldr	r1, [pc, #60]	; (8004388 <lwftp_data_open+0x188>)
- 800434a:	4618      	mov	r0, r3
- 800434c:	f004 fc5e 	bl	8008c0c <tcp_err>
-	tcp_recv(s->data_pcb, lwftp_data_recv);
- 8004350:	687b      	ldr	r3, [r7, #4]
- 8004352:	6b1b      	ldr	r3, [r3, #48]	; 0x30
- 8004354:	490d      	ldr	r1, [pc, #52]	; (800438c <lwftp_data_open+0x18c>)
- 8004356:	4618      	mov	r0, r3
- 8004358:	f004 fc14 	bl	8008b84 <tcp_recv>
-	tcp_sent(s->data_pcb, lwftp_data_sent);
- 800435c:	687b      	ldr	r3, [r7, #4]
- 800435e:	6b1b      	ldr	r3, [r3, #48]	; 0x30
- 8004360:	490b      	ldr	r1, [pc, #44]	; (8004390 <lwftp_data_open+0x190>)
- 8004362:	4618      	mov	r0, r3
- 8004364:	f004 fc30 	bl	8008bc8 <tcp_sent>
-	error = tcp_connect(s->data_pcb, &data_server, data_port,
- 8004368:	687b      	ldr	r3, [r7, #4]
- 800436a:	6b18      	ldr	r0, [r3, #48]	; 0x30
- 800436c:	8afa      	ldrh	r2, [r7, #22]
- 800436e:	f107 010c 	add.w	r1, r7, #12
- 8004372:	4b08      	ldr	r3, [pc, #32]	; (8004394 <lwftp_data_open+0x194>)
- 8004374:	f003 fcb2 	bl	8007cdc <tcp_connect>
- 8004378:	4603      	mov	r3, r0
- 800437a:	757b      	strb	r3, [r7, #21]
-			lwftp_data_connected);
-	return error;
- 800437c:	f997 3015 	ldrsb.w	r3, [r7, #21]
-}
- 8004380:	4618      	mov	r0, r3
- 8004382:	3728      	adds	r7, #40	; 0x28
- 8004384:	46bd      	mov	sp, r7
- 8004386:	bd80      	pop	{r7, pc}
- 8004388:	08004155 	.word	0x08004155
- 800438c:	08004091 	.word	0x08004091
- 8004390:	0800411d 	.word	0x0800411d
- 8004394:	080041ad 	.word	0x080041ad
-
-08004398 <lwftp_send_msg>:
-
-/** Send a message to control connection
- * @param pointer to lwftp session data
- * @param pointer to message string
- */
-static err_t lwftp_send_msg(lwftp_session_t *s, const char *msg, size_t len) {
- 8004398:	b580      	push	{r7, lr}
- 800439a:	b086      	sub	sp, #24
- 800439c:	af00      	add	r7, sp, #0
- 800439e:	60f8      	str	r0, [r7, #12]
- 80043a0:	60b9      	str	r1, [r7, #8]
- 80043a2:	607a      	str	r2, [r7, #4]
-	err_t error;
-
-	LWIP_DEBUGF(LWFTP_TRACE,("lwftp:sending %s",msg));
- 80043a4:	68b9      	ldr	r1, [r7, #8]
- 80043a6:	4810      	ldr	r0, [pc, #64]	; (80043e8 <lwftp_send_msg+0x50>)
- 80043a8:	f00c fc0e 	bl	8010bc8 <iprintf>
-	error = tcp_write(s->control_pcb, msg, len, 0);
- 80043ac:	68fb      	ldr	r3, [r7, #12]
- 80043ae:	6ad8      	ldr	r0, [r3, #44]	; 0x2c
- 80043b0:	687b      	ldr	r3, [r7, #4]
- 80043b2:	b29a      	uxth	r2, r3
- 80043b4:	2300      	movs	r3, #0
- 80043b6:	68b9      	ldr	r1, [r7, #8]
- 80043b8:	f007 fad4 	bl	800b964 <tcp_write>
- 80043bc:	4603      	mov	r3, r0
- 80043be:	75fb      	strb	r3, [r7, #23]
-	if (error != ERR_OK) {
- 80043c0:	f997 3017 	ldrsb.w	r3, [r7, #23]
- 80043c4:	2b00      	cmp	r3, #0
- 80043c6:	d009      	beq.n	80043dc <lwftp_send_msg+0x44>
-		LWIP_DEBUGF(LWFTP_WARNING, ("lwftp:cannot write (%s)\n",lwip_strerr(error)));
- 80043c8:	f997 3017 	ldrsb.w	r3, [r7, #23]
- 80043cc:	4618      	mov	r0, r3
- 80043ce:	f001 f89d 	bl	800550c <lwip_strerr>
- 80043d2:	4603      	mov	r3, r0
- 80043d4:	4619      	mov	r1, r3
- 80043d6:	4805      	ldr	r0, [pc, #20]	; (80043ec <lwftp_send_msg+0x54>)
- 80043d8:	f00c fbf6 	bl	8010bc8 <iprintf>
-	}
-	return error;
- 80043dc:	f997 3017 	ldrsb.w	r3, [r7, #23]
-}
- 80043e0:	4618      	mov	r0, r3
- 80043e2:	3718      	adds	r7, #24
- 80043e4:	46bd      	mov	sp, r7
- 80043e6:	bd80      	pop	{r7, pc}
- 80043e8:	08011784 	.word	0x08011784
- 80043ec:	08011798 	.word	0x08011798
-
-080043f0 <lwftp_data_close>:
-
-/** Close data connection
- * @param pointer to lwftp session data
- * @param result to pass to callback fn (if called)
- */
-static void lwftp_data_close(lwftp_session_t *s, int result) {
- 80043f0:	b580      	push	{r7, lr}
- 80043f2:	b082      	sub	sp, #8
- 80043f4:	af00      	add	r7, sp, #0
- 80043f6:	6078      	str	r0, [r7, #4]
- 80043f8:	6039      	str	r1, [r7, #0]
-	if (s->data_pcb) {
- 80043fa:	687b      	ldr	r3, [r7, #4]
- 80043fc:	6b1b      	ldr	r3, [r3, #48]	; 0x30
- 80043fe:	2b00      	cmp	r3, #0
- 8004400:	d007      	beq.n	8004412 <lwftp_data_close+0x22>
-		lwftp_pcb_close(s->data_pcb);
- 8004402:	687b      	ldr	r3, [r7, #4]
- 8004404:	6b1b      	ldr	r3, [r3, #48]	; 0x30
- 8004406:	4618      	mov	r0, r3
- 8004408:	f7ff fdd4 	bl	8003fb4 <lwftp_pcb_close>
-		s->data_pcb = NULL;
- 800440c:	687b      	ldr	r3, [r7, #4]
- 800440e:	2200      	movs	r2, #0
- 8004410:	631a      	str	r2, [r3, #48]	; 0x30
-	}
-	if (s->done_fn) {
- 8004412:	687b      	ldr	r3, [r7, #4]
- 8004414:	6a1b      	ldr	r3, [r3, #32]
- 8004416:	2b00      	cmp	r3, #0
- 8004418:	d006      	beq.n	8004428 <lwftp_data_close+0x38>
-		s->done_fn(s->handle, result);
- 800441a:	687b      	ldr	r3, [r7, #4]
- 800441c:	6a1b      	ldr	r3, [r3, #32]
- 800441e:	687a      	ldr	r2, [r7, #4]
- 8004420:	6952      	ldr	r2, [r2, #20]
- 8004422:	6839      	ldr	r1, [r7, #0]
- 8004424:	4610      	mov	r0, r2
- 8004426:	4798      	blx	r3
-	}
-}
- 8004428:	bf00      	nop
- 800442a:	3708      	adds	r7, #8
- 800442c:	46bd      	mov	sp, r7
- 800442e:	bd80      	pop	{r7, pc}
-
-08004430 <lwftp_control_close>:
-
-/** Close control connection
- * @param pointer to lwftp session data
- * @param result to pass to callback fn (if called)
- */
-static void lwftp_control_close(lwftp_session_t *s, int result) {
- 8004430:	b580      	push	{r7, lr}
- 8004432:	b082      	sub	sp, #8
- 8004434:	af00      	add	r7, sp, #0
- 8004436:	6078      	str	r0, [r7, #4]
- 8004438:	6039      	str	r1, [r7, #0]
-	if (s->data_pcb) {
- 800443a:	687b      	ldr	r3, [r7, #4]
- 800443c:	6b1b      	ldr	r3, [r3, #48]	; 0x30
- 800443e:	2b00      	cmp	r3, #0
- 8004440:	d007      	beq.n	8004452 <lwftp_control_close+0x22>
-		lwftp_pcb_close(s->data_pcb);
- 8004442:	687b      	ldr	r3, [r7, #4]
- 8004444:	6b1b      	ldr	r3, [r3, #48]	; 0x30
- 8004446:	4618      	mov	r0, r3
- 8004448:	f7ff fdb4 	bl	8003fb4 <lwftp_pcb_close>
-		s->data_pcb = NULL;
- 800444c:	687b      	ldr	r3, [r7, #4]
- 800444e:	2200      	movs	r2, #0
- 8004450:	631a      	str	r2, [r3, #48]	; 0x30
-	}
-	if (s->control_pcb) {
- 8004452:	687b      	ldr	r3, [r7, #4]
- 8004454:	6adb      	ldr	r3, [r3, #44]	; 0x2c
- 8004456:	2b00      	cmp	r3, #0
- 8004458:	d007      	beq.n	800446a <lwftp_control_close+0x3a>
-		lwftp_pcb_close(s->control_pcb);
- 800445a:	687b      	ldr	r3, [r7, #4]
- 800445c:	6adb      	ldr	r3, [r3, #44]	; 0x2c
- 800445e:	4618      	mov	r0, r3
- 8004460:	f7ff fda8 	bl	8003fb4 <lwftp_pcb_close>
-		s->control_pcb = NULL;
- 8004464:	687b      	ldr	r3, [r7, #4]
- 8004466:	2200      	movs	r2, #0
- 8004468:	62da      	str	r2, [r3, #44]	; 0x2c
-	}
-	s->control_state = LWFTP_CLOSED;
- 800446a:	687b      	ldr	r3, [r7, #4]
- 800446c:	2200      	movs	r2, #0
- 800446e:	f883 2028 	strb.w	r2, [r3, #40]	; 0x28
-	if ((result >= 0) && s->done_fn) {
- 8004472:	683b      	ldr	r3, [r7, #0]
- 8004474:	2b00      	cmp	r3, #0
- 8004476:	db0a      	blt.n	800448e <lwftp_control_close+0x5e>
- 8004478:	687b      	ldr	r3, [r7, #4]
- 800447a:	6a1b      	ldr	r3, [r3, #32]
- 800447c:	2b00      	cmp	r3, #0
- 800447e:	d006      	beq.n	800448e <lwftp_control_close+0x5e>
-		s->done_fn(s->handle, result);
- 8004480:	687b      	ldr	r3, [r7, #4]
- 8004482:	6a1b      	ldr	r3, [r3, #32]
- 8004484:	687a      	ldr	r2, [r7, #4]
- 8004486:	6952      	ldr	r2, [r2, #20]
- 8004488:	6839      	ldr	r1, [r7, #0]
- 800448a:	4610      	mov	r0, r2
- 800448c:	4798      	blx	r3
-	}
-}
- 800448e:	bf00      	nop
- 8004490:	3708      	adds	r7, #8
- 8004492:	46bd      	mov	sp, r7
- 8004494:	bd80      	pop	{r7, pc}
-	...
-
-08004498 <lwftp_control_process>:
- * @param pointer to lwftp session data
- * @param pointer to PCB
- * @param pointer to incoming data
- */
-static void lwftp_control_process(lwftp_session_t *s, struct tcp_pcb *tpcb,
-		struct pbuf *p) {
- 8004498:	b590      	push	{r4, r7, lr}
- 800449a:	b087      	sub	sp, #28
- 800449c:	af00      	add	r7, sp, #0
- 800449e:	60f8      	str	r0, [r7, #12]
- 80044a0:	60b9      	str	r1, [r7, #8]
- 80044a2:	607a      	str	r2, [r7, #4]
-	uint response = 0;
- 80044a4:	2300      	movs	r3, #0
- 80044a6:	617b      	str	r3, [r7, #20]
-	int result = LWFTP_RESULT_ERR_SRVR_RESP;
- 80044a8:	230a      	movs	r3, #10
- 80044aa:	613b      	str	r3, [r7, #16]
-
-	// Try to get response number
-	if (p) {
- 80044ac:	687b      	ldr	r3, [r7, #4]
- 80044ae:	2b00      	cmp	r3, #0
- 80044b0:	d00b      	beq.n	80044ca <lwftp_control_process+0x32>
-		response = strtoul(p->payload, NULL, 10);
- 80044b2:	687b      	ldr	r3, [r7, #4]
- 80044b4:	685b      	ldr	r3, [r3, #4]
- 80044b6:	220a      	movs	r2, #10
- 80044b8:	2100      	movs	r1, #0
- 80044ba:	4618      	mov	r0, r3
- 80044bc:	f00b ff80 	bl	80103c0 <strtoul>
- 80044c0:	6178      	str	r0, [r7, #20]
-		LWIP_DEBUGF(LWFTP_TRACE, ("lwftp:got response %d\n",response));
- 80044c2:	6979      	ldr	r1, [r7, #20]
- 80044c4:	48a8      	ldr	r0, [pc, #672]	; (8004768 <lwftp_control_process+0x2d0>)
- 80044c6:	f00c fb7f 	bl	8010bc8 <iprintf>
-	}
-
-	switch (s->control_state) {
- 80044ca:	68fb      	ldr	r3, [r7, #12]
- 80044cc:	f893 3028 	ldrb.w	r3, [r3, #40]	; 0x28
- 80044d0:	3b01      	subs	r3, #1
- 80044d2:	2b0b      	cmp	r3, #11
- 80044d4:	f200 816d 	bhi.w	80047b2 <lwftp_control_process+0x31a>
- 80044d8:	a201      	add	r2, pc, #4	; (adr r2, 80044e0 <lwftp_control_process+0x48>)
- 80044da:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
- 80044de:	bf00      	nop
- 80044e0:	08004511 	.word	0x08004511
- 80044e4:	08004561 	.word	0x08004561
- 80044e8:	080045b5 	.word	0x080045b5
- 80044ec:	080047b3 	.word	0x080047b3
- 80044f0:	080045f5 	.word	0x080045f5
- 80044f4:	08004621 	.word	0x08004621
- 80044f8:	080046a7 	.word	0x080046a7
- 80044fc:	080046f5 	.word	0x080046f5
- 8004500:	08004727 	.word	0x08004727
- 8004504:	0800474f 	.word	0x0800474f
- 8004508:	080047b3 	.word	0x080047b3
- 800450c:	08004757 	.word	0x08004757
-	case LWFTP_CONNECTED:
-		if (response > 0) {
- 8004510:	697b      	ldr	r3, [r7, #20]
- 8004512:	2b00      	cmp	r3, #0
- 8004514:	f000 8155 	beq.w	80047c2 <lwftp_control_process+0x32a>
-			if (response == 220) {
- 8004518:	697b      	ldr	r3, [r7, #20]
- 800451a:	2bdc      	cmp	r3, #220	; 0xdc
- 800451c:	d11b      	bne.n	8004556 <lwftp_control_process+0xbe>
-				lwftp_send_msg(s, PTRNLEN("USER "));
- 800451e:	2205      	movs	r2, #5
- 8004520:	4992      	ldr	r1, [pc, #584]	; (800476c <lwftp_control_process+0x2d4>)
- 8004522:	68f8      	ldr	r0, [r7, #12]
- 8004524:	f7ff ff38 	bl	8004398 <lwftp_send_msg>
-				lwftp_send_msg(s, s->user, strlen(s->user));
- 8004528:	68fb      	ldr	r3, [r7, #12]
- 800452a:	68dc      	ldr	r4, [r3, #12]
- 800452c:	68fb      	ldr	r3, [r7, #12]
- 800452e:	68db      	ldr	r3, [r3, #12]
- 8004530:	4618      	mov	r0, r3
- 8004532:	f7fb ff3d 	bl	80003b0 <strlen>
- 8004536:	4603      	mov	r3, r0
- 8004538:	461a      	mov	r2, r3
- 800453a:	4621      	mov	r1, r4
- 800453c:	68f8      	ldr	r0, [r7, #12]
- 800453e:	f7ff ff2b 	bl	8004398 <lwftp_send_msg>
-				lwftp_send_msg(s, PTRNLEN("\r\n"));
- 8004542:	2202      	movs	r2, #2
- 8004544:	498a      	ldr	r1, [pc, #552]	; (8004770 <lwftp_control_process+0x2d8>)
- 8004546:	68f8      	ldr	r0, [r7, #12]
- 8004548:	f7ff ff26 	bl	8004398 <lwftp_send_msg>
-				s->control_state = LWFTP_USER_SENT;
- 800454c:	68fb      	ldr	r3, [r7, #12]
- 800454e:	2202      	movs	r2, #2
- 8004550:	f883 2028 	strb.w	r2, [r3, #40]	; 0x28
-			} else {
-				s->control_state = LWFTP_QUIT;
-			}
-		}
-		break;
- 8004554:	e135      	b.n	80047c2 <lwftp_control_process+0x32a>
-				s->control_state = LWFTP_QUIT;
- 8004556:	68fb      	ldr	r3, [r7, #12]
- 8004558:	220b      	movs	r2, #11
- 800455a:	f883 2028 	strb.w	r2, [r3, #40]	; 0x28
-		break;
- 800455e:	e130      	b.n	80047c2 <lwftp_control_process+0x32a>
-	case LWFTP_USER_SENT:
-		if (response > 0) {
- 8004560:	697b      	ldr	r3, [r7, #20]
- 8004562:	2b00      	cmp	r3, #0
- 8004564:	f000 812f 	beq.w	80047c6 <lwftp_control_process+0x32e>
-			if (response == 331) {
- 8004568:	697b      	ldr	r3, [r7, #20]
- 800456a:	f240 124b 	movw	r2, #331	; 0x14b
- 800456e:	4293      	cmp	r3, r2
- 8004570:	d11b      	bne.n	80045aa <lwftp_control_process+0x112>
-				lwftp_send_msg(s, PTRNLEN("PASS "));
- 8004572:	2205      	movs	r2, #5
- 8004574:	497f      	ldr	r1, [pc, #508]	; (8004774 <lwftp_control_process+0x2dc>)
- 8004576:	68f8      	ldr	r0, [r7, #12]
- 8004578:	f7ff ff0e 	bl	8004398 <lwftp_send_msg>
-				lwftp_send_msg(s, s->pass, strlen(s->pass));
- 800457c:	68fb      	ldr	r3, [r7, #12]
- 800457e:	691c      	ldr	r4, [r3, #16]
- 8004580:	68fb      	ldr	r3, [r7, #12]
- 8004582:	691b      	ldr	r3, [r3, #16]
- 8004584:	4618      	mov	r0, r3
- 8004586:	f7fb ff13 	bl	80003b0 <strlen>
- 800458a:	4603      	mov	r3, r0
- 800458c:	461a      	mov	r2, r3
- 800458e:	4621      	mov	r1, r4
- 8004590:	68f8      	ldr	r0, [r7, #12]
- 8004592:	f7ff ff01 	bl	8004398 <lwftp_send_msg>
-				lwftp_send_msg(s, PTRNLEN("\r\n"));
- 8004596:	2202      	movs	r2, #2
- 8004598:	4975      	ldr	r1, [pc, #468]	; (8004770 <lwftp_control_process+0x2d8>)
- 800459a:	68f8      	ldr	r0, [r7, #12]
- 800459c:	f7ff fefc 	bl	8004398 <lwftp_send_msg>
-				s->control_state = LWFTP_PASS_SENT;
- 80045a0:	68fb      	ldr	r3, [r7, #12]
- 80045a2:	2203      	movs	r2, #3
- 80045a4:	f883 2028 	strb.w	r2, [r3, #40]	; 0x28
-			} else {
-				s->control_state = LWFTP_QUIT;
-			}
-		}
-		break;
- 80045a8:	e10d      	b.n	80047c6 <lwftp_control_process+0x32e>
-				s->control_state = LWFTP_QUIT;
- 80045aa:	68fb      	ldr	r3, [r7, #12]
- 80045ac:	220b      	movs	r2, #11
- 80045ae:	f883 2028 	strb.w	r2, [r3, #40]	; 0x28
-		break;
- 80045b2:	e108      	b.n	80047c6 <lwftp_control_process+0x32e>
-	case LWFTP_PASS_SENT:
-		if (response > 0) {
- 80045b4:	697b      	ldr	r3, [r7, #20]
- 80045b6:	2b00      	cmp	r3, #0
- 80045b8:	f000 8107 	beq.w	80047ca <lwftp_control_process+0x332>
-			if (response == 230) {
- 80045bc:	697b      	ldr	r3, [r7, #20]
- 80045be:	2be6      	cmp	r3, #230	; 0xe6
- 80045c0:	d113      	bne.n	80045ea <lwftp_control_process+0x152>
-				s->control_state = LWFTP_LOGGED;
- 80045c2:	68fb      	ldr	r3, [r7, #12]
- 80045c4:	2204      	movs	r2, #4
- 80045c6:	f883 2028 	strb.w	r2, [r3, #40]	; 0x28
-				LWIP_DEBUGF(LWFTP_STATE, ("lwftp: now logged in\n"));
- 80045ca:	486b      	ldr	r0, [pc, #428]	; (8004778 <lwftp_control_process+0x2e0>)
- 80045cc:	f00c fb6a 	bl	8010ca4 <puts>
-				if (s->done_fn) {
- 80045d0:	68fb      	ldr	r3, [r7, #12]
- 80045d2:	6a1b      	ldr	r3, [r3, #32]
- 80045d4:	2b00      	cmp	r3, #0
- 80045d6:	f000 80f8 	beq.w	80047ca <lwftp_control_process+0x332>
-					s->done_fn(s->handle, LWFTP_RESULT_LOGGED);
- 80045da:	68fb      	ldr	r3, [r7, #12]
- 80045dc:	6a1b      	ldr	r3, [r3, #32]
- 80045de:	68fa      	ldr	r2, [r7, #12]
- 80045e0:	6952      	ldr	r2, [r2, #20]
- 80045e2:	2102      	movs	r1, #2
- 80045e4:	4610      	mov	r0, r2
- 80045e6:	4798      	blx	r3
-				}
-			} else {
-				s->control_state = LWFTP_QUIT;
-			}
-		}
-		break;
- 80045e8:	e0ef      	b.n	80047ca <lwftp_control_process+0x332>
-				s->control_state = LWFTP_QUIT;
- 80045ea:	68fb      	ldr	r3, [r7, #12]
- 80045ec:	220b      	movs	r2, #11
- 80045ee:	f883 2028 	strb.w	r2, [r3, #40]	; 0x28
-		break;
- 80045f2:	e0ea      	b.n	80047ca <lwftp_control_process+0x332>
-	case LWFTP_TYPE_SENT:
-		if (response > 0) {
- 80045f4:	697b      	ldr	r3, [r7, #20]
- 80045f6:	2b00      	cmp	r3, #0
- 80045f8:	f000 80e9 	beq.w	80047ce <lwftp_control_process+0x336>
-			if (response == 200) {
- 80045fc:	697b      	ldr	r3, [r7, #20]
- 80045fe:	2bc8      	cmp	r3, #200	; 0xc8
- 8004600:	d109      	bne.n	8004616 <lwftp_control_process+0x17e>
-				lwftp_send_msg(s, PTRNLEN("PASV\r\n"));
- 8004602:	2206      	movs	r2, #6
- 8004604:	495d      	ldr	r1, [pc, #372]	; (800477c <lwftp_control_process+0x2e4>)
- 8004606:	68f8      	ldr	r0, [r7, #12]
- 8004608:	f7ff fec6 	bl	8004398 <lwftp_send_msg>
-				s->control_state = LWFTP_PASV_SENT;
- 800460c:	68fb      	ldr	r3, [r7, #12]
- 800460e:	2206      	movs	r2, #6
- 8004610:	f883 2028 	strb.w	r2, [r3, #40]	; 0x28
-			} else {
-				s->control_state = LWFTP_QUIT;
-			}
-		}
-		break;
- 8004614:	e0db      	b.n	80047ce <lwftp_control_process+0x336>
-				s->control_state = LWFTP_QUIT;
- 8004616:	68fb      	ldr	r3, [r7, #12]
- 8004618:	220b      	movs	r2, #11
- 800461a:	f883 2028 	strb.w	r2, [r3, #40]	; 0x28
-		break;
- 800461e:	e0d6      	b.n	80047ce <lwftp_control_process+0x336>
-	case LWFTP_PASV_SENT:
-		if (response > 0) {
- 8004620:	697b      	ldr	r3, [r7, #20]
- 8004622:	2b00      	cmp	r3, #0
- 8004624:	f000 80d5 	beq.w	80047d2 <lwftp_control_process+0x33a>
-			if (response == 227) {
- 8004628:	697b      	ldr	r3, [r7, #20]
- 800462a:	2be3      	cmp	r3, #227	; 0xe3
- 800462c:	d136      	bne.n	800469c <lwftp_control_process+0x204>
-				lwftp_data_open(s, p);
- 800462e:	6879      	ldr	r1, [r7, #4]
- 8004630:	68f8      	ldr	r0, [r7, #12]
- 8004632:	f7ff fde5 	bl	8004200 <lwftp_data_open>
-				switch (s->target_state) {
- 8004636:	68fb      	ldr	r3, [r7, #12]
- 8004638:	f893 3029 	ldrb.w	r3, [r3, #41]	; 0x29
- 800463c:	2b07      	cmp	r3, #7
- 800463e:	d007      	beq.n	8004650 <lwftp_control_process+0x1b8>
- 8004640:	2b08      	cmp	r3, #8
- 8004642:	d10b      	bne.n	800465c <lwftp_control_process+0x1c4>
-				case LWFTP_STOR_SENT:
-					lwftp_send_msg(s, PTRNLEN("STOR "));
- 8004644:	2205      	movs	r2, #5
- 8004646:	494e      	ldr	r1, [pc, #312]	; (8004780 <lwftp_control_process+0x2e8>)
- 8004648:	68f8      	ldr	r0, [r7, #12]
- 800464a:	f7ff fea5 	bl	8004398 <lwftp_send_msg>
-					break;
- 800464e:	e00c      	b.n	800466a <lwftp_control_process+0x1d2>
-				case LWFTP_RETR_SENT:
-					lwftp_send_msg(s, PTRNLEN("RETR "));
- 8004650:	2205      	movs	r2, #5
- 8004652:	494c      	ldr	r1, [pc, #304]	; (8004784 <lwftp_control_process+0x2ec>)
- 8004654:	68f8      	ldr	r0, [r7, #12]
- 8004656:	f7ff fe9f 	bl	8004398 <lwftp_send_msg>
-					break;
- 800465a:	e006      	b.n	800466a <lwftp_control_process+0x1d2>
-				default:
-					LOG_ERROR("Unexpected internal state");
- 800465c:	484a      	ldr	r0, [pc, #296]	; (8004788 <lwftp_control_process+0x2f0>)
- 800465e:	f7fb fef3 	bl	8000448 <LOG_ERROR>
-					s->target_state = LWFTP_QUIT;
- 8004662:	68fb      	ldr	r3, [r7, #12]
- 8004664:	220b      	movs	r2, #11
- 8004666:	f883 2029 	strb.w	r2, [r3, #41]	; 0x29
-				}
-				lwftp_send_msg(s, s->remote_path, strlen(s->remote_path));
- 800466a:	68fb      	ldr	r3, [r7, #12]
- 800466c:	689c      	ldr	r4, [r3, #8]
- 800466e:	68fb      	ldr	r3, [r7, #12]
- 8004670:	689b      	ldr	r3, [r3, #8]
- 8004672:	4618      	mov	r0, r3
- 8004674:	f7fb fe9c 	bl	80003b0 <strlen>
- 8004678:	4603      	mov	r3, r0
- 800467a:	461a      	mov	r2, r3
- 800467c:	4621      	mov	r1, r4
- 800467e:	68f8      	ldr	r0, [r7, #12]
- 8004680:	f7ff fe8a 	bl	8004398 <lwftp_send_msg>
-				lwftp_send_msg(s, PTRNLEN("\r\n"));
- 8004684:	2202      	movs	r2, #2
- 8004686:	493a      	ldr	r1, [pc, #232]	; (8004770 <lwftp_control_process+0x2d8>)
- 8004688:	68f8      	ldr	r0, [r7, #12]
- 800468a:	f7ff fe85 	bl	8004398 <lwftp_send_msg>
-				s->control_state = s->target_state;
- 800468e:	68fb      	ldr	r3, [r7, #12]
- 8004690:	f893 2029 	ldrb.w	r2, [r3, #41]	; 0x29
- 8004694:	68fb      	ldr	r3, [r7, #12]
- 8004696:	f883 2028 	strb.w	r2, [r3, #40]	; 0x28
-			} else {
-				s->control_state = LWFTP_QUIT;
-			}
-		}
-		break;
- 800469a:	e09a      	b.n	80047d2 <lwftp_control_process+0x33a>
-				s->control_state = LWFTP_QUIT;
- 800469c:	68fb      	ldr	r3, [r7, #12]
- 800469e:	220b      	movs	r2, #11
- 80046a0:	f883 2028 	strb.w	r2, [r3, #40]	; 0x28
-		break;
- 80046a4:	e095      	b.n	80047d2 <lwftp_control_process+0x33a>
-	case LWFTP_RETR_SENT:
-		if (response > 0) {
- 80046a6:	697b      	ldr	r3, [r7, #20]
- 80046a8:	2b00      	cmp	r3, #0
- 80046aa:	f000 8094 	beq.w	80047d6 <lwftp_control_process+0x33e>
-			if (response == 150) {
- 80046ae:	697b      	ldr	r3, [r7, #20]
- 80046b0:	2b96      	cmp	r3, #150	; 0x96
- 80046b2:	d104      	bne.n	80046be <lwftp_control_process+0x226>
-				s->control_state = LWFTP_XFERING;
- 80046b4:	68fb      	ldr	r3, [r7, #12]
- 80046b6:	2209      	movs	r2, #9
- 80046b8:	f883 2028 	strb.w	r2, [r3, #40]	; 0x28
-			} else {
-				s->control_state = LWFTP_DATAEND;
-				LWIP_DEBUGF(LWFTP_WARNING, ("lwftp:expected 150, received %d\n",response));
-			}
-		}
-		break;
- 80046bc:	e08b      	b.n	80047d6 <lwftp_control_process+0x33e>
-			} else if (response == 550) {
- 80046be:	697b      	ldr	r3, [r7, #20]
- 80046c0:	f240 2226 	movw	r2, #550	; 0x226
- 80046c4:	4293      	cmp	r3, r2
- 80046c6:	d10c      	bne.n	80046e2 <lwftp_control_process+0x24a>
-				s->control_state = LWFTP_DATAEND;
- 80046c8:	68fb      	ldr	r3, [r7, #12]
- 80046ca:	220a      	movs	r2, #10
- 80046cc:	f883 2028 	strb.w	r2, [r3, #40]	; 0x28
-				result = LWFTP_RESULT_ERR_FILENAME;
- 80046d0:	230d      	movs	r3, #13
- 80046d2:	613b      	str	r3, [r7, #16]
-				LWIP_DEBUGF(LWFTP_WARNING, ("lwftp: Failed to open file '%s'\n", s->remote_path));
- 80046d4:	68fb      	ldr	r3, [r7, #12]
- 80046d6:	689b      	ldr	r3, [r3, #8]
- 80046d8:	4619      	mov	r1, r3
- 80046da:	482c      	ldr	r0, [pc, #176]	; (800478c <lwftp_control_process+0x2f4>)
- 80046dc:	f00c fa74 	bl	8010bc8 <iprintf>
-		break;
- 80046e0:	e079      	b.n	80047d6 <lwftp_control_process+0x33e>
-				s->control_state = LWFTP_DATAEND;
- 80046e2:	68fb      	ldr	r3, [r7, #12]
- 80046e4:	220a      	movs	r2, #10
- 80046e6:	f883 2028 	strb.w	r2, [r3, #40]	; 0x28
-				LWIP_DEBUGF(LWFTP_WARNING, ("lwftp:expected 150, received %d\n",response));
- 80046ea:	6979      	ldr	r1, [r7, #20]
- 80046ec:	4828      	ldr	r0, [pc, #160]	; (8004790 <lwftp_control_process+0x2f8>)
- 80046ee:	f00c fa6b 	bl	8010bc8 <iprintf>
-		break;
- 80046f2:	e070      	b.n	80047d6 <lwftp_control_process+0x33e>
-	case LWFTP_STOR_SENT:
-		if (response > 0) {
- 80046f4:	697b      	ldr	r3, [r7, #20]
- 80046f6:	2b00      	cmp	r3, #0
- 80046f8:	d06f      	beq.n	80047da <lwftp_control_process+0x342>
-			if (response == 150) {
- 80046fa:	697b      	ldr	r3, [r7, #20]
- 80046fc:	2b96      	cmp	r3, #150	; 0x96
- 80046fe:	d109      	bne.n	8004714 <lwftp_control_process+0x27c>
-				s->control_state = LWFTP_XFERING;
- 8004700:	68fb      	ldr	r3, [r7, #12]
- 8004702:	2209      	movs	r2, #9
- 8004704:	f883 2028 	strb.w	r2, [r3, #40]	; 0x28
-				lwftp_data_sent(s, NULL, 0);
- 8004708:	2200      	movs	r2, #0
- 800470a:	2100      	movs	r1, #0
- 800470c:	68f8      	ldr	r0, [r7, #12]
- 800470e:	f7ff fd05 	bl	800411c <lwftp_data_sent>
-			} else {
-				s->control_state = LWFTP_DATAEND;
-				LWIP_DEBUGF(LWFTP_WARNING, ("lwftp:expected 150, received %d\n",response));
-			}
-		}
-		break;
- 8004712:	e062      	b.n	80047da <lwftp_control_process+0x342>
-				s->control_state = LWFTP_DATAEND;
- 8004714:	68fb      	ldr	r3, [r7, #12]
- 8004716:	220a      	movs	r2, #10
- 8004718:	f883 2028 	strb.w	r2, [r3, #40]	; 0x28
-				LWIP_DEBUGF(LWFTP_WARNING, ("lwftp:expected 150, received %d\n",response));
- 800471c:	6979      	ldr	r1, [r7, #20]
- 800471e:	481c      	ldr	r0, [pc, #112]	; (8004790 <lwftp_control_process+0x2f8>)
- 8004720:	f00c fa52 	bl	8010bc8 <iprintf>
-		break;
- 8004724:	e059      	b.n	80047da <lwftp_control_process+0x342>
-	case LWFTP_XFERING:
-		if (response > 0) {
- 8004726:	697b      	ldr	r3, [r7, #20]
- 8004728:	2b00      	cmp	r3, #0
- 800472a:	d058      	beq.n	80047de <lwftp_control_process+0x346>
-			if (response == 226) {
- 800472c:	697b      	ldr	r3, [r7, #20]
- 800472e:	2be2      	cmp	r3, #226	; 0xe2
- 8004730:	d102      	bne.n	8004738 <lwftp_control_process+0x2a0>
-				result = LWFTP_RESULT_OK;
- 8004732:	2300      	movs	r3, #0
- 8004734:	613b      	str	r3, [r7, #16]
- 8004736:	e005      	b.n	8004744 <lwftp_control_process+0x2ac>
-			} else {
-				result = LWFTP_RESULT_ERR_CLOSED;
- 8004738:	2308      	movs	r3, #8
- 800473a:	613b      	str	r3, [r7, #16]
-				LWIP_DEBUGF(LWFTP_WARNING, ("lwftp:expected 226, received %d\n",response));
- 800473c:	6979      	ldr	r1, [r7, #20]
- 800473e:	4815      	ldr	r0, [pc, #84]	; (8004794 <lwftp_control_process+0x2fc>)
- 8004740:	f00c fa42 	bl	8010bc8 <iprintf>
-			}
-			s->control_state = LWFTP_DATAEND;
- 8004744:	68fb      	ldr	r3, [r7, #12]
- 8004746:	220a      	movs	r2, #10
- 8004748:	f883 2028 	strb.w	r2, [r3, #40]	; 0x28
-		}
-		break;
- 800474c:	e047      	b.n	80047de <lwftp_control_process+0x346>
-	case LWFTP_DATAEND:
-		LOG_TRACE("forced end of data session");
- 800474e:	4812      	ldr	r0, [pc, #72]	; (8004798 <lwftp_control_process+0x300>)
- 8004750:	f7fb fea6 	bl	80004a0 <LOG_TRACE>
-		break;
- 8004754:	e046      	b.n	80047e4 <lwftp_control_process+0x34c>
-	case LWFTP_QUIT_SENT:
-		if (response > 0) {
- 8004756:	697b      	ldr	r3, [r7, #20]
- 8004758:	2b00      	cmp	r3, #0
- 800475a:	d042      	beq.n	80047e2 <lwftp_control_process+0x34a>
-			if (response == 221) {
- 800475c:	697b      	ldr	r3, [r7, #20]
- 800475e:	2bdd      	cmp	r3, #221	; 0xdd
- 8004760:	d11c      	bne.n	800479c <lwftp_control_process+0x304>
-				result = LWFTP_RESULT_OK;
- 8004762:	2300      	movs	r3, #0
- 8004764:	613b      	str	r3, [r7, #16]
- 8004766:	e01f      	b.n	80047a8 <lwftp_control_process+0x310>
- 8004768:	080117b4 	.word	0x080117b4
- 800476c:	080117cc 	.word	0x080117cc
- 8004770:	080117d4 	.word	0x080117d4
- 8004774:	080117d8 	.word	0x080117d8
- 8004778:	080117e0 	.word	0x080117e0
- 800477c:	080117f8 	.word	0x080117f8
- 8004780:	08011800 	.word	0x08011800
- 8004784:	08011808 	.word	0x08011808
- 8004788:	08011810 	.word	0x08011810
- 800478c:	0801182c 	.word	0x0801182c
- 8004790:	08011850 	.word	0x08011850
- 8004794:	08011874 	.word	0x08011874
- 8004798:	08011898 	.word	0x08011898
-			} else {
-				result = LWFTP_RESULT_ERR_UNKNOWN;
- 800479c:	2303      	movs	r3, #3
- 800479e:	613b      	str	r3, [r7, #16]
-				LWIP_DEBUGF(LWFTP_WARNING, ("lwftp:expected 221, received %d\n",response));
- 80047a0:	6979      	ldr	r1, [r7, #20]
- 80047a2:	482a      	ldr	r0, [pc, #168]	; (800484c <lwftp_control_process+0x3b4>)
- 80047a4:	f00c fa10 	bl	8010bc8 <iprintf>
-			}
-			s->control_state = LWFTP_CLOSING;
- 80047a8:	68fb      	ldr	r3, [r7, #12]
- 80047aa:	220d      	movs	r2, #13
- 80047ac:	f883 2028 	strb.w	r2, [r3, #40]	; 0x28
-		}
-		break;
- 80047b0:	e017      	b.n	80047e2 <lwftp_control_process+0x34a>
-	default:
-		LWIP_DEBUGF(LWFTP_SEVERE, ("lwftp:unhandled state (%d)\n",s->control_state));
- 80047b2:	68fb      	ldr	r3, [r7, #12]
- 80047b4:	f893 3028 	ldrb.w	r3, [r3, #40]	; 0x28
- 80047b8:	4619      	mov	r1, r3
- 80047ba:	4825      	ldr	r0, [pc, #148]	; (8004850 <lwftp_control_process+0x3b8>)
- 80047bc:	f00c fa04 	bl	8010bc8 <iprintf>
- 80047c0:	e010      	b.n	80047e4 <lwftp_control_process+0x34c>
-		break;
- 80047c2:	bf00      	nop
- 80047c4:	e00e      	b.n	80047e4 <lwftp_control_process+0x34c>
-		break;
- 80047c6:	bf00      	nop
- 80047c8:	e00c      	b.n	80047e4 <lwftp_control_process+0x34c>
-		break;
- 80047ca:	bf00      	nop
- 80047cc:	e00a      	b.n	80047e4 <lwftp_control_process+0x34c>
-		break;
- 80047ce:	bf00      	nop
- 80047d0:	e008      	b.n	80047e4 <lwftp_control_process+0x34c>
-		break;
- 80047d2:	bf00      	nop
- 80047d4:	e006      	b.n	80047e4 <lwftp_control_process+0x34c>
-		break;
- 80047d6:	bf00      	nop
- 80047d8:	e004      	b.n	80047e4 <lwftp_control_process+0x34c>
-		break;
- 80047da:	bf00      	nop
- 80047dc:	e002      	b.n	80047e4 <lwftp_control_process+0x34c>
-		break;
- 80047de:	bf00      	nop
- 80047e0:	e000      	b.n	80047e4 <lwftp_control_process+0x34c>
-		break;
- 80047e2:	bf00      	nop
-	}
-
-	// Free receiving pbuf if any
-	if (p) {
- 80047e4:	687b      	ldr	r3, [r7, #4]
- 80047e6:	2b00      	cmp	r3, #0
- 80047e8:	d002      	beq.n	80047f0 <lwftp_control_process+0x358>
-		pbuf_free(p);
- 80047ea:	6878      	ldr	r0, [r7, #4]
- 80047ec:	f002 fbf2 	bl	8006fd4 <pbuf_free>
-	}
-
-	// Handle second step in state machine
-	switch (s->control_state) {
- 80047f0:	68fb      	ldr	r3, [r7, #12]
- 80047f2:	f893 3028 	ldrb.w	r3, [r3, #40]	; 0x28
- 80047f6:	2b0d      	cmp	r3, #13
- 80047f8:	d01e      	beq.n	8004838 <lwftp_control_process+0x3a0>
- 80047fa:	2b0d      	cmp	r3, #13
- 80047fc:	dc21      	bgt.n	8004842 <lwftp_control_process+0x3aa>
- 80047fe:	2b0a      	cmp	r3, #10
- 8004800:	d002      	beq.n	8004808 <lwftp_control_process+0x370>
- 8004802:	2b0b      	cmp	r3, #11
- 8004804:	d009      	beq.n	800481a <lwftp_control_process+0x382>
-		lwftp_control_close(s, result);
-		break;
-	default:
-		;
-	}
-}
- 8004806:	e01c      	b.n	8004842 <lwftp_control_process+0x3aa>
-		lwftp_data_close(s, result);
- 8004808:	6939      	ldr	r1, [r7, #16]
- 800480a:	68f8      	ldr	r0, [r7, #12]
- 800480c:	f7ff fdf0 	bl	80043f0 <lwftp_data_close>
-		s->control_state = LWFTP_LOGGED;
- 8004810:	68fb      	ldr	r3, [r7, #12]
- 8004812:	2204      	movs	r2, #4
- 8004814:	f883 2028 	strb.w	r2, [r3, #40]	; 0x28
-		break;
- 8004818:	e013      	b.n	8004842 <lwftp_control_process+0x3aa>
-		lwftp_send_msg(s, PTRNLEN("QUIT\r\n"));
- 800481a:	2206      	movs	r2, #6
- 800481c:	490d      	ldr	r1, [pc, #52]	; (8004854 <lwftp_control_process+0x3bc>)
- 800481e:	68f8      	ldr	r0, [r7, #12]
- 8004820:	f7ff fdba 	bl	8004398 <lwftp_send_msg>
-		tcp_output(s->control_pcb);
- 8004824:	68fb      	ldr	r3, [r7, #12]
- 8004826:	6adb      	ldr	r3, [r3, #44]	; 0x2c
- 8004828:	4618      	mov	r0, r3
- 800482a:	f007 fee3 	bl	800c5f4 <tcp_output>
-		s->control_state = LWFTP_QUIT_SENT;
- 800482e:	68fb      	ldr	r3, [r7, #12]
- 8004830:	220c      	movs	r2, #12
- 8004832:	f883 2028 	strb.w	r2, [r3, #40]	; 0x28
-		break;
- 8004836:	e004      	b.n	8004842 <lwftp_control_process+0x3aa>
-		lwftp_control_close(s, result);
- 8004838:	6939      	ldr	r1, [r7, #16]
- 800483a:	68f8      	ldr	r0, [r7, #12]
- 800483c:	f7ff fdf8 	bl	8004430 <lwftp_control_close>
-		break;
- 8004840:	bf00      	nop
-}
- 8004842:	bf00      	nop
- 8004844:	371c      	adds	r7, #28
- 8004846:	46bd      	mov	sp, r7
- 8004848:	bd90      	pop	{r4, r7, pc}
- 800484a:	bf00      	nop
- 800484c:	080118b4 	.word	0x080118b4
- 8004850:	080118d8 	.word	0x080118d8
- 8004854:	080118f4 	.word	0x080118f4
-
-08004858 <lwftp_control_recv>:
- * @param pointer to PCB
- * @param pointer to incoming pbuf
- * @param state of incoming process
- */
-static err_t lwftp_control_recv(void *arg, struct tcp_pcb *tpcb, struct pbuf *p,
-		err_t err) {
- 8004858:	b580      	push	{r7, lr}
- 800485a:	b086      	sub	sp, #24
- 800485c:	af00      	add	r7, sp, #0
- 800485e:	60f8      	str	r0, [r7, #12]
- 8004860:	60b9      	str	r1, [r7, #8]
- 8004862:	607a      	str	r2, [r7, #4]
- 8004864:	70fb      	strb	r3, [r7, #3]
-	lwftp_session_t *s = (lwftp_session_t*) arg;
- 8004866:	68fb      	ldr	r3, [r7, #12]
- 8004868:	617b      	str	r3, [r7, #20]
-
-	if (err == ERR_OK) {
- 800486a:	f997 3003 	ldrsb.w	r3, [r7, #3]
- 800486e:	2b00      	cmp	r3, #0
- 8004870:	d116      	bne.n	80048a0 <lwftp_control_recv+0x48>
-		if (p) {
- 8004872:	687b      	ldr	r3, [r7, #4]
- 8004874:	2b00      	cmp	r3, #0
- 8004876:	d00b      	beq.n	8004890 <lwftp_control_recv+0x38>
-			tcp_recved(tpcb, p->tot_len);
- 8004878:	687b      	ldr	r3, [r7, #4]
- 800487a:	891b      	ldrh	r3, [r3, #8]
- 800487c:	4619      	mov	r1, r3
- 800487e:	68b8      	ldr	r0, [r7, #8]
- 8004880:	f003 f996 	bl	8007bb0 <tcp_recved>
-			lwftp_control_process(s, tpcb, p);
- 8004884:	687a      	ldr	r2, [r7, #4]
- 8004886:	68b9      	ldr	r1, [r7, #8]
- 8004888:	6978      	ldr	r0, [r7, #20]
- 800488a:	f7ff fe05 	bl	8004498 <lwftp_control_process>
- 800488e:	e015      	b.n	80048bc <lwftp_control_recv+0x64>
-		} else {
-			LWIP_DEBUGF(LWFTP_WARNING, ("lwftp:connection closed by remote host\n"));
- 8004890:	480d      	ldr	r0, [pc, #52]	; (80048c8 <lwftp_control_recv+0x70>)
- 8004892:	f00c fa07 	bl	8010ca4 <puts>
-			lwftp_control_close(s, LWFTP_RESULT_ERR_CLOSED);
- 8004896:	2108      	movs	r1, #8
- 8004898:	6978      	ldr	r0, [r7, #20]
- 800489a:	f7ff fdc9 	bl	8004430 <lwftp_control_close>
- 800489e:	e00d      	b.n	80048bc <lwftp_control_recv+0x64>
-		}
-	} else {
-		LWIP_DEBUGF(LWFTP_SERIOUS, ("lwftp:failed to receive (%s)\n",lwip_strerr(err)));
- 80048a0:	f997 3003 	ldrsb.w	r3, [r7, #3]
- 80048a4:	4618      	mov	r0, r3
- 80048a6:	f000 fe31 	bl	800550c <lwip_strerr>
- 80048aa:	4603      	mov	r3, r0
- 80048ac:	4619      	mov	r1, r3
- 80048ae:	4807      	ldr	r0, [pc, #28]	; (80048cc <lwftp_control_recv+0x74>)
- 80048b0:	f00c f98a 	bl	8010bc8 <iprintf>
-		lwftp_control_close(s, LWFTP_RESULT_ERR_UNKNOWN);
- 80048b4:	2103      	movs	r1, #3
- 80048b6:	6978      	ldr	r0, [r7, #20]
- 80048b8:	f7ff fdba 	bl	8004430 <lwftp_control_close>
-	}
-	return err;
- 80048bc:	f997 3003 	ldrsb.w	r3, [r7, #3]
-}
- 80048c0:	4618      	mov	r0, r3
- 80048c2:	3718      	adds	r7, #24
- 80048c4:	46bd      	mov	sp, r7
- 80048c6:	bd80      	pop	{r7, pc}
- 80048c8:	08011920 	.word	0x08011920
- 80048cc:	08011948 	.word	0x08011948
-
-080048d0 <lwftp_control_sent>:
-/** Handle control connection acknowledge of sent data
- * @param pointer to lwftp session data
- * @param pointer to PCB
- * @param number of bytes sent
- */
-static err_t lwftp_control_sent(void *arg, struct tcp_pcb *tpcb, u16_t len) {
- 80048d0:	b580      	push	{r7, lr}
- 80048d2:	b084      	sub	sp, #16
- 80048d4:	af00      	add	r7, sp, #0
- 80048d6:	60f8      	str	r0, [r7, #12]
- 80048d8:	60b9      	str	r1, [r7, #8]
- 80048da:	4613      	mov	r3, r2
- 80048dc:	80fb      	strh	r3, [r7, #6]
-	LWIP_DEBUGF(LWFTP_TRACE, ("lwftp:successfully sent %d bytes\n",len));
- 80048de:	88fb      	ldrh	r3, [r7, #6]
- 80048e0:	4619      	mov	r1, r3
- 80048e2:	4804      	ldr	r0, [pc, #16]	; (80048f4 <lwftp_control_sent+0x24>)
- 80048e4:	f00c f970 	bl	8010bc8 <iprintf>
-	return ERR_OK;
- 80048e8:	2300      	movs	r3, #0
-}
- 80048ea:	4618      	mov	r0, r3
- 80048ec:	3710      	adds	r7, #16
- 80048ee:	46bd      	mov	sp, r7
- 80048f0:	bd80      	pop	{r7, pc}
- 80048f2:	bf00      	nop
- 80048f4:	08011968 	.word	0x08011968
-
-080048f8 <lwftp_control_err>:
-
-/** Handle control connection error
- * @param pointer to lwftp session data
- * @param state of connection
- */
-static void lwftp_control_err(void *arg, err_t err) {
- 80048f8:	b580      	push	{r7, lr}
- 80048fa:	b084      	sub	sp, #16
- 80048fc:	af00      	add	r7, sp, #0
- 80048fe:	6078      	str	r0, [r7, #4]
- 8004900:	460b      	mov	r3, r1
- 8004902:	70fb      	strb	r3, [r7, #3]
-	LWIP_UNUSED_ARG(err);
-	if (arg != NULL) {
- 8004904:	687b      	ldr	r3, [r7, #4]
- 8004906:	2b00      	cmp	r3, #0
- 8004908:	d01f      	beq.n	800494a <lwftp_control_err+0x52>
-		lwftp_session_t *s = (lwftp_session_t*) arg;
- 800490a:	687b      	ldr	r3, [r7, #4]
- 800490c:	60bb      	str	r3, [r7, #8]
-		int result;
-		if (s->control_state == LWFTP_CLOSED) {
- 800490e:	68bb      	ldr	r3, [r7, #8]
- 8004910:	f893 3028 	ldrb.w	r3, [r3, #40]	; 0x28
- 8004914:	2b00      	cmp	r3, #0
- 8004916:	d10c      	bne.n	8004932 <lwftp_control_err+0x3a>
-			LWIP_DEBUGF(LWFTP_WARNING, ("lwftp:failed to connect to server (%s)\n",lwip_strerr(err)));
- 8004918:	f997 3003 	ldrsb.w	r3, [r7, #3]
- 800491c:	4618      	mov	r0, r3
- 800491e:	f000 fdf5 	bl	800550c <lwip_strerr>
- 8004922:	4603      	mov	r3, r0
- 8004924:	4619      	mov	r1, r3
- 8004926:	480b      	ldr	r0, [pc, #44]	; (8004954 <lwftp_control_err+0x5c>)
- 8004928:	f00c f94e 	bl	8010bc8 <iprintf>
-			result = LWFTP_RESULT_ERR_CONNECT;
- 800492c:	2306      	movs	r3, #6
- 800492e:	60fb      	str	r3, [r7, #12]
- 8004930:	e004      	b.n	800493c <lwftp_control_err+0x44>
-		} else {
-			LWIP_DEBUGF(LWFTP_WARNING, ("lwftp:connection closed by remote host\n"));
- 8004932:	4809      	ldr	r0, [pc, #36]	; (8004958 <lwftp_control_err+0x60>)
- 8004934:	f00c f9b6 	bl	8010ca4 <puts>
-			result = LWFTP_RESULT_ERR_CLOSED;
- 8004938:	2308      	movs	r3, #8
- 800493a:	60fb      	str	r3, [r7, #12]
-		}
-		s->control_pcb = NULL; // No need to de-allocate PCB
- 800493c:	68bb      	ldr	r3, [r7, #8]
- 800493e:	2200      	movs	r2, #0
- 8004940:	62da      	str	r2, [r3, #44]	; 0x2c
-		lwftp_control_close(s, result);
- 8004942:	68f9      	ldr	r1, [r7, #12]
- 8004944:	68b8      	ldr	r0, [r7, #8]
- 8004946:	f7ff fd73 	bl	8004430 <lwftp_control_close>
-	}
-}
- 800494a:	bf00      	nop
- 800494c:	3710      	adds	r7, #16
- 800494e:	46bd      	mov	sp, r7
- 8004950:	bd80      	pop	{r7, pc}
- 8004952:	bf00      	nop
- 8004954:	0801198c 	.word	0x0801198c
- 8004958:	08011920 	.word	0x08011920
-
-0800495c <lwftp_control_connected>:
-/** Process newly connected PCB
- * @param pointer to lwftp session data
- * @param pointer to PCB
- * @param state of connection
- */
-static err_t lwftp_control_connected(void *arg, struct tcp_pcb *tpcb, err_t err) {
- 800495c:	b580      	push	{r7, lr}
- 800495e:	b086      	sub	sp, #24
- 8004960:	af00      	add	r7, sp, #0
- 8004962:	60f8      	str	r0, [r7, #12]
- 8004964:	60b9      	str	r1, [r7, #8]
- 8004966:	4613      	mov	r3, r2
- 8004968:	71fb      	strb	r3, [r7, #7]
-	lwftp_session_t *s = (lwftp_session_t*) arg;
- 800496a:	68fb      	ldr	r3, [r7, #12]
- 800496c:	617b      	str	r3, [r7, #20]
-
-	if (err == ERR_OK) {
- 800496e:	f997 3007 	ldrsb.w	r3, [r7, #7]
- 8004972:	2b00      	cmp	r3, #0
- 8004974:	d103      	bne.n	800497e <lwftp_control_connected+0x22>
-		LWIP_DEBUGF(LWFTP_STATE, ("lwftp:connected to server\n"));
- 8004976:	480f      	ldr	r0, [pc, #60]	; (80049b4 <lwftp_control_connected+0x58>)
- 8004978:	f00c f994 	bl	8010ca4 <puts>
- 800497c:	e014      	b.n	80049a8 <lwftp_control_connected+0x4c>
-	} else {
-		LWIP_DEBUGF(LWFTP_WARNING, ("lwftp:err in control_connected (%s)\n", lwip_strerr(err)));
- 800497e:	f997 3007 	ldrsb.w	r3, [r7, #7]
- 8004982:	4618      	mov	r0, r3
- 8004984:	f000 fdc2 	bl	800550c <lwip_strerr>
- 8004988:	4603      	mov	r3, r0
- 800498a:	4619      	mov	r1, r3
- 800498c:	480a      	ldr	r0, [pc, #40]	; (80049b8 <lwftp_control_connected+0x5c>)
- 800498e:	f00c f91b 	bl	8010bc8 <iprintf>
-		if (s->done_fn) {
- 8004992:	697b      	ldr	r3, [r7, #20]
- 8004994:	6a1b      	ldr	r3, [r3, #32]
- 8004996:	2b00      	cmp	r3, #0
- 8004998:	d006      	beq.n	80049a8 <lwftp_control_connected+0x4c>
-			s->done_fn(s->handle, LWFTP_RESULT_ERR_CONNECT); // 연결 실패 상태 전달
- 800499a:	697b      	ldr	r3, [r7, #20]
- 800499c:	6a1b      	ldr	r3, [r3, #32]
- 800499e:	697a      	ldr	r2, [r7, #20]
- 80049a0:	6952      	ldr	r2, [r2, #20]
- 80049a2:	2106      	movs	r1, #6
- 80049a4:	4610      	mov	r0, r2
- 80049a6:	4798      	blx	r3
-		}
-	}
-	return err;
- 80049a8:	f997 3007 	ldrsb.w	r3, [r7, #7]
-}
- 80049ac:	4618      	mov	r0, r3
- 80049ae:	3718      	adds	r7, #24
- 80049b0:	46bd      	mov	sp, r7
- 80049b2:	bd80      	pop	{r7, pc}
- 80049b4:	080119b4 	.word	0x080119b4
- 80049b8:	080119d0 	.word	0x080119d0
-
-080049bc <lwftp_connect>:
-
-/** Open a control session
- * @param Session structure
- */
-err_t lwftp_connect(lwftp_session_t *s) {
- 80049bc:	b580      	push	{r7, lr}
- 80049be:	b084      	sub	sp, #16
- 80049c0:	af00      	add	r7, sp, #0
- 80049c2:	6078      	str	r0, [r7, #4]
-	err_t error;
-	enum lwftp_results retval = LWFTP_RESULT_ERR_UNKNOWN;
- 80049c4:	2303      	movs	r3, #3
- 80049c6:	73fb      	strb	r3, [r7, #15]
-
-	// Check user supplied data
-	if ((s->control_state != LWFTP_CLOSED) || s->control_pcb || s->data_pcb
- 80049c8:	687b      	ldr	r3, [r7, #4]
- 80049ca:	f893 3028 	ldrb.w	r3, [r3, #40]	; 0x28
- 80049ce:	2b00      	cmp	r3, #0
- 80049d0:	d10f      	bne.n	80049f2 <lwftp_connect+0x36>
- 80049d2:	687b      	ldr	r3, [r7, #4]
- 80049d4:	6adb      	ldr	r3, [r3, #44]	; 0x2c
- 80049d6:	2b00      	cmp	r3, #0
- 80049d8:	d10b      	bne.n	80049f2 <lwftp_connect+0x36>
- 80049da:	687b      	ldr	r3, [r7, #4]
- 80049dc:	6b1b      	ldr	r3, [r3, #48]	; 0x30
- 80049de:	2b00      	cmp	r3, #0
- 80049e0:	d107      	bne.n	80049f2 <lwftp_connect+0x36>
-			|| !s->user || !s->pass) {
- 80049e2:	687b      	ldr	r3, [r7, #4]
- 80049e4:	68db      	ldr	r3, [r3, #12]
- 80049e6:	2b00      	cmp	r3, #0
- 80049e8:	d003      	beq.n	80049f2 <lwftp_connect+0x36>
- 80049ea:	687b      	ldr	r3, [r7, #4]
- 80049ec:	691b      	ldr	r3, [r3, #16]
- 80049ee:	2b00      	cmp	r3, #0
- 80049f0:	d105      	bne.n	80049fe <lwftp_connect+0x42>
-		LWIP_DEBUGF(LWFTP_WARNING, ("lwftp:invalid control session\n"));
- 80049f2:	482f      	ldr	r0, [pc, #188]	; (8004ab0 <lwftp_connect+0xf4>)
- 80049f4:	f00c f956 	bl	8010ca4 <puts>
-		retval = LWFTP_RESULT_ERR_ARGUMENT;
- 80049f8:	2304      	movs	r3, #4
- 80049fa:	73fb      	strb	r3, [r7, #15]
-		goto exit;
- 80049fc:	e046      	b.n	8004a8c <lwftp_connect+0xd0>
-	}
-	// Get sessions pcb
-	s->control_pcb = tcp_new();
- 80049fe:	f004 f8a7 	bl	8008b50 <tcp_new>
- 8004a02:	4602      	mov	r2, r0
- 8004a04:	687b      	ldr	r3, [r7, #4]
- 8004a06:	62da      	str	r2, [r3, #44]	; 0x2c
-	if (!s->control_pcb) {
- 8004a08:	687b      	ldr	r3, [r7, #4]
- 8004a0a:	6adb      	ldr	r3, [r3, #44]	; 0x2c
- 8004a0c:	2b00      	cmp	r3, #0
- 8004a0e:	d105      	bne.n	8004a1c <lwftp_connect+0x60>
-		LWIP_DEBUGF(LWFTP_SERIOUS, ("lwftp:cannot alloc control_pcb (low memory?)\n"));
- 8004a10:	4828      	ldr	r0, [pc, #160]	; (8004ab4 <lwftp_connect+0xf8>)
- 8004a12:	f00c f947 	bl	8010ca4 <puts>
-		retval = LWFTP_RESULT_ERR_MEMORY;
- 8004a16:	2305      	movs	r3, #5
- 8004a18:	73fb      	strb	r3, [r7, #15]
-		goto exit;
- 8004a1a:	e037      	b.n	8004a8c <lwftp_connect+0xd0>
-	}
-	// Open control session
-	tcp_arg(s->control_pcb, s);
- 8004a1c:	687b      	ldr	r3, [r7, #4]
- 8004a1e:	6adb      	ldr	r3, [r3, #44]	; 0x2c
- 8004a20:	6879      	ldr	r1, [r7, #4]
- 8004a22:	4618      	mov	r0, r3
- 8004a24:	f004 f89c 	bl	8008b60 <tcp_arg>
-	tcp_err(s->control_pcb, lwftp_control_err);
- 8004a28:	687b      	ldr	r3, [r7, #4]
- 8004a2a:	6adb      	ldr	r3, [r3, #44]	; 0x2c
- 8004a2c:	4922      	ldr	r1, [pc, #136]	; (8004ab8 <lwftp_connect+0xfc>)
- 8004a2e:	4618      	mov	r0, r3
- 8004a30:	f004 f8ec 	bl	8008c0c <tcp_err>
-	tcp_recv(s->control_pcb, lwftp_control_recv);
- 8004a34:	687b      	ldr	r3, [r7, #4]
- 8004a36:	6adb      	ldr	r3, [r3, #44]	; 0x2c
- 8004a38:	4920      	ldr	r1, [pc, #128]	; (8004abc <lwftp_connect+0x100>)
- 8004a3a:	4618      	mov	r0, r3
- 8004a3c:	f004 f8a2 	bl	8008b84 <tcp_recv>
-	tcp_sent(s->control_pcb, lwftp_control_sent);
- 8004a40:	687b      	ldr	r3, [r7, #4]
- 8004a42:	6adb      	ldr	r3, [r3, #44]	; 0x2c
- 8004a44:	491e      	ldr	r1, [pc, #120]	; (8004ac0 <lwftp_connect+0x104>)
- 8004a46:	4618      	mov	r0, r3
- 8004a48:	f004 f8be 	bl	8008bc8 <tcp_sent>
-	error = tcp_connect(s->control_pcb, &s->server_ip, s->server_port,
- 8004a4c:	687b      	ldr	r3, [r7, #4]
- 8004a4e:	6ad8      	ldr	r0, [r3, #44]	; 0x2c
- 8004a50:	6879      	ldr	r1, [r7, #4]
- 8004a52:	687b      	ldr	r3, [r7, #4]
- 8004a54:	889a      	ldrh	r2, [r3, #4]
- 8004a56:	4b1b      	ldr	r3, [pc, #108]	; (8004ac4 <lwftp_connect+0x108>)
- 8004a58:	f003 f940 	bl	8007cdc <tcp_connect>
- 8004a5c:	4603      	mov	r3, r0
- 8004a5e:	73bb      	strb	r3, [r7, #14]
-			lwftp_control_connected);
-	if (error == ERR_OK) {
- 8004a60:	f997 300e 	ldrsb.w	r3, [r7, #14]
- 8004a64:	2b00      	cmp	r3, #0
- 8004a66:	d102      	bne.n	8004a6e <lwftp_connect+0xb2>
-		retval = LWFTP_RESULT_INPROGRESS;
- 8004a68:	2301      	movs	r3, #1
- 8004a6a:	73fb      	strb	r3, [r7, #15]
-		goto exit;
- 8004a6c:	e00e      	b.n	8004a8c <lwftp_connect+0xd0>
-	}
-
-	// Release pcbs in case of failure
-	LWIP_DEBUGF(LWFTP_SERIOUS, ("lwftp:cannot connect control_pcb (%s)\n", lwip_strerr(error)));
- 8004a6e:	f997 300e 	ldrsb.w	r3, [r7, #14]
- 8004a72:	4618      	mov	r0, r3
- 8004a74:	f000 fd4a 	bl	800550c <lwip_strerr>
- 8004a78:	4603      	mov	r3, r0
- 8004a7a:	4619      	mov	r1, r3
- 8004a7c:	4812      	ldr	r0, [pc, #72]	; (8004ac8 <lwftp_connect+0x10c>)
- 8004a7e:	f00c f8a3 	bl	8010bc8 <iprintf>
-	lwftp_control_close(s, -1);
- 8004a82:	f04f 31ff 	mov.w	r1, #4294967295
- 8004a86:	6878      	ldr	r0, [r7, #4]
- 8004a88:	f7ff fcd2 	bl	8004430 <lwftp_control_close>
-
-	exit: if (s->done_fn)
- 8004a8c:	687b      	ldr	r3, [r7, #4]
- 8004a8e:	6a1b      	ldr	r3, [r3, #32]
- 8004a90:	2b00      	cmp	r3, #0
- 8004a92:	d006      	beq.n	8004aa2 <lwftp_connect+0xe6>
-		s->done_fn(s->handle, retval);
- 8004a94:	687b      	ldr	r3, [r7, #4]
- 8004a96:	6a1b      	ldr	r3, [r3, #32]
- 8004a98:	687a      	ldr	r2, [r7, #4]
- 8004a9a:	6952      	ldr	r2, [r2, #20]
- 8004a9c:	7bf9      	ldrb	r1, [r7, #15]
- 8004a9e:	4610      	mov	r0, r2
- 8004aa0:	4798      	blx	r3
-	return retval;
- 8004aa2:	f997 300f 	ldrsb.w	r3, [r7, #15]
-}
- 8004aa6:	4618      	mov	r0, r3
- 8004aa8:	3710      	adds	r7, #16
- 8004aaa:	46bd      	mov	sp, r7
- 8004aac:	bd80      	pop	{r7, pc}
- 8004aae:	bf00      	nop
- 8004ab0:	080119f8 	.word	0x080119f8
- 8004ab4:	08011a18 	.word	0x08011a18
- 8004ab8:	080048f9 	.word	0x080048f9
- 8004abc:	08004859 	.word	0x08004859
- 8004ac0:	080048d1 	.word	0x080048d1
- 8004ac4:	0800495d 	.word	0x0800495d
- 8004ac8:	08011a48 	.word	0x08011a48
-
-08004acc <MX_LWIP_Init>:
-
-/**
-  * LwIP initialization function
-  */
-void MX_LWIP_Init(void)
-{
- 8004acc:	b580      	push	{r7, lr}
- 8004ace:	b084      	sub	sp, #16
- 8004ad0:	af04      	add	r7, sp, #16
-  /* IP addresses initialization */
-  IP_ADDRESS[0] = 192;
- 8004ad2:	4b87      	ldr	r3, [pc, #540]	; (8004cf0 <MX_LWIP_Init+0x224>)
- 8004ad4:	22c0      	movs	r2, #192	; 0xc0
- 8004ad6:	701a      	strb	r2, [r3, #0]
-  IP_ADDRESS[1] = 168;
- 8004ad8:	4b85      	ldr	r3, [pc, #532]	; (8004cf0 <MX_LWIP_Init+0x224>)
- 8004ada:	22a8      	movs	r2, #168	; 0xa8
- 8004adc:	705a      	strb	r2, [r3, #1]
-  IP_ADDRESS[2] = 0;
- 8004ade:	4b84      	ldr	r3, [pc, #528]	; (8004cf0 <MX_LWIP_Init+0x224>)
- 8004ae0:	2200      	movs	r2, #0
- 8004ae2:	709a      	strb	r2, [r3, #2]
-  IP_ADDRESS[3] = 120;
- 8004ae4:	4b82      	ldr	r3, [pc, #520]	; (8004cf0 <MX_LWIP_Init+0x224>)
- 8004ae6:	2278      	movs	r2, #120	; 0x78
- 8004ae8:	70da      	strb	r2, [r3, #3]
-  NETMASK_ADDRESS[0] = 255;
- 8004aea:	4b82      	ldr	r3, [pc, #520]	; (8004cf4 <MX_LWIP_Init+0x228>)
- 8004aec:	22ff      	movs	r2, #255	; 0xff
- 8004aee:	701a      	strb	r2, [r3, #0]
-  NETMASK_ADDRESS[1] = 255;
- 8004af0:	4b80      	ldr	r3, [pc, #512]	; (8004cf4 <MX_LWIP_Init+0x228>)
- 8004af2:	22ff      	movs	r2, #255	; 0xff
- 8004af4:	705a      	strb	r2, [r3, #1]
-  NETMASK_ADDRESS[2] = 255;
- 8004af6:	4b7f      	ldr	r3, [pc, #508]	; (8004cf4 <MX_LWIP_Init+0x228>)
- 8004af8:	22ff      	movs	r2, #255	; 0xff
- 8004afa:	709a      	strb	r2, [r3, #2]
-  NETMASK_ADDRESS[3] = 0;
- 8004afc:	4b7d      	ldr	r3, [pc, #500]	; (8004cf4 <MX_LWIP_Init+0x228>)
- 8004afe:	2200      	movs	r2, #0
- 8004b00:	70da      	strb	r2, [r3, #3]
-  GATEWAY_ADDRESS[0] = 0;
- 8004b02:	4b7d      	ldr	r3, [pc, #500]	; (8004cf8 <MX_LWIP_Init+0x22c>)
- 8004b04:	2200      	movs	r2, #0
- 8004b06:	701a      	strb	r2, [r3, #0]
-  GATEWAY_ADDRESS[1] = 0;
- 8004b08:	4b7b      	ldr	r3, [pc, #492]	; (8004cf8 <MX_LWIP_Init+0x22c>)
- 8004b0a:	2200      	movs	r2, #0
- 8004b0c:	705a      	strb	r2, [r3, #1]
-  GATEWAY_ADDRESS[2] = 0;
- 8004b0e:	4b7a      	ldr	r3, [pc, #488]	; (8004cf8 <MX_LWIP_Init+0x22c>)
- 8004b10:	2200      	movs	r2, #0
- 8004b12:	709a      	strb	r2, [r3, #2]
-  GATEWAY_ADDRESS[3] = 0;
- 8004b14:	4b78      	ldr	r3, [pc, #480]	; (8004cf8 <MX_LWIP_Init+0x22c>)
- 8004b16:	2200      	movs	r2, #0
- 8004b18:	70da      	strb	r2, [r3, #3]
-
-/* USER CODE BEGIN IP_ADDRESSES */
-/* USER CODE END IP_ADDRESSES */
-
-  /* Initilialize the LwIP stack without RTOS */
-  lwip_init();
- 8004b1a:	f000 fe01 	bl	8005720 <lwip_init>
-
-  /* IP addresses initialization without DHCP (IPv4) */
-  IP4_ADDR(&ipaddr, IP_ADDRESS[0], IP_ADDRESS[1], IP_ADDRESS[2], IP_ADDRESS[3]);
- 8004b1e:	4b74      	ldr	r3, [pc, #464]	; (8004cf0 <MX_LWIP_Init+0x224>)
- 8004b20:	781b      	ldrb	r3, [r3, #0]
- 8004b22:	061a      	lsls	r2, r3, #24
- 8004b24:	4b72      	ldr	r3, [pc, #456]	; (8004cf0 <MX_LWIP_Init+0x224>)
- 8004b26:	785b      	ldrb	r3, [r3, #1]
- 8004b28:	041b      	lsls	r3, r3, #16
- 8004b2a:	431a      	orrs	r2, r3
- 8004b2c:	4b70      	ldr	r3, [pc, #448]	; (8004cf0 <MX_LWIP_Init+0x224>)
- 8004b2e:	789b      	ldrb	r3, [r3, #2]
- 8004b30:	021b      	lsls	r3, r3, #8
- 8004b32:	4313      	orrs	r3, r2
- 8004b34:	4a6e      	ldr	r2, [pc, #440]	; (8004cf0 <MX_LWIP_Init+0x224>)
- 8004b36:	78d2      	ldrb	r2, [r2, #3]
- 8004b38:	4313      	orrs	r3, r2
- 8004b3a:	061a      	lsls	r2, r3, #24
- 8004b3c:	4b6c      	ldr	r3, [pc, #432]	; (8004cf0 <MX_LWIP_Init+0x224>)
- 8004b3e:	781b      	ldrb	r3, [r3, #0]
- 8004b40:	0619      	lsls	r1, r3, #24
- 8004b42:	4b6b      	ldr	r3, [pc, #428]	; (8004cf0 <MX_LWIP_Init+0x224>)
- 8004b44:	785b      	ldrb	r3, [r3, #1]
- 8004b46:	041b      	lsls	r3, r3, #16
- 8004b48:	4319      	orrs	r1, r3
- 8004b4a:	4b69      	ldr	r3, [pc, #420]	; (8004cf0 <MX_LWIP_Init+0x224>)
- 8004b4c:	789b      	ldrb	r3, [r3, #2]
- 8004b4e:	021b      	lsls	r3, r3, #8
- 8004b50:	430b      	orrs	r3, r1
- 8004b52:	4967      	ldr	r1, [pc, #412]	; (8004cf0 <MX_LWIP_Init+0x224>)
- 8004b54:	78c9      	ldrb	r1, [r1, #3]
- 8004b56:	430b      	orrs	r3, r1
- 8004b58:	021b      	lsls	r3, r3, #8
- 8004b5a:	f403 037f 	and.w	r3, r3, #16711680	; 0xff0000
- 8004b5e:	431a      	orrs	r2, r3
- 8004b60:	4b63      	ldr	r3, [pc, #396]	; (8004cf0 <MX_LWIP_Init+0x224>)
- 8004b62:	781b      	ldrb	r3, [r3, #0]
- 8004b64:	0619      	lsls	r1, r3, #24
- 8004b66:	4b62      	ldr	r3, [pc, #392]	; (8004cf0 <MX_LWIP_Init+0x224>)
- 8004b68:	785b      	ldrb	r3, [r3, #1]
- 8004b6a:	041b      	lsls	r3, r3, #16
- 8004b6c:	4319      	orrs	r1, r3
- 8004b6e:	4b60      	ldr	r3, [pc, #384]	; (8004cf0 <MX_LWIP_Init+0x224>)
- 8004b70:	789b      	ldrb	r3, [r3, #2]
- 8004b72:	021b      	lsls	r3, r3, #8
- 8004b74:	430b      	orrs	r3, r1
- 8004b76:	495e      	ldr	r1, [pc, #376]	; (8004cf0 <MX_LWIP_Init+0x224>)
- 8004b78:	78c9      	ldrb	r1, [r1, #3]
- 8004b7a:	430b      	orrs	r3, r1
- 8004b7c:	0a1b      	lsrs	r3, r3, #8
- 8004b7e:	f403 437f 	and.w	r3, r3, #65280	; 0xff00
- 8004b82:	431a      	orrs	r2, r3
- 8004b84:	4b5a      	ldr	r3, [pc, #360]	; (8004cf0 <MX_LWIP_Init+0x224>)
- 8004b86:	781b      	ldrb	r3, [r3, #0]
- 8004b88:	0619      	lsls	r1, r3, #24
- 8004b8a:	4b59      	ldr	r3, [pc, #356]	; (8004cf0 <MX_LWIP_Init+0x224>)
- 8004b8c:	785b      	ldrb	r3, [r3, #1]
- 8004b8e:	041b      	lsls	r3, r3, #16
- 8004b90:	4319      	orrs	r1, r3
- 8004b92:	4b57      	ldr	r3, [pc, #348]	; (8004cf0 <MX_LWIP_Init+0x224>)
- 8004b94:	789b      	ldrb	r3, [r3, #2]
- 8004b96:	021b      	lsls	r3, r3, #8
- 8004b98:	430b      	orrs	r3, r1
- 8004b9a:	4955      	ldr	r1, [pc, #340]	; (8004cf0 <MX_LWIP_Init+0x224>)
- 8004b9c:	78c9      	ldrb	r1, [r1, #3]
- 8004b9e:	430b      	orrs	r3, r1
- 8004ba0:	0e1b      	lsrs	r3, r3, #24
- 8004ba2:	4313      	orrs	r3, r2
- 8004ba4:	4a55      	ldr	r2, [pc, #340]	; (8004cfc <MX_LWIP_Init+0x230>)
- 8004ba6:	6013      	str	r3, [r2, #0]
-  IP4_ADDR(&netmask, NETMASK_ADDRESS[0], NETMASK_ADDRESS[1] , NETMASK_ADDRESS[2], NETMASK_ADDRESS[3]);
- 8004ba8:	4b52      	ldr	r3, [pc, #328]	; (8004cf4 <MX_LWIP_Init+0x228>)
- 8004baa:	781b      	ldrb	r3, [r3, #0]
- 8004bac:	061a      	lsls	r2, r3, #24
- 8004bae:	4b51      	ldr	r3, [pc, #324]	; (8004cf4 <MX_LWIP_Init+0x228>)
- 8004bb0:	785b      	ldrb	r3, [r3, #1]
- 8004bb2:	041b      	lsls	r3, r3, #16
- 8004bb4:	431a      	orrs	r2, r3
- 8004bb6:	4b4f      	ldr	r3, [pc, #316]	; (8004cf4 <MX_LWIP_Init+0x228>)
- 8004bb8:	789b      	ldrb	r3, [r3, #2]
- 8004bba:	021b      	lsls	r3, r3, #8
- 8004bbc:	4313      	orrs	r3, r2
- 8004bbe:	4a4d      	ldr	r2, [pc, #308]	; (8004cf4 <MX_LWIP_Init+0x228>)
- 8004bc0:	78d2      	ldrb	r2, [r2, #3]
- 8004bc2:	4313      	orrs	r3, r2
- 8004bc4:	061a      	lsls	r2, r3, #24
- 8004bc6:	4b4b      	ldr	r3, [pc, #300]	; (8004cf4 <MX_LWIP_Init+0x228>)
- 8004bc8:	781b      	ldrb	r3, [r3, #0]
- 8004bca:	0619      	lsls	r1, r3, #24
- 8004bcc:	4b49      	ldr	r3, [pc, #292]	; (8004cf4 <MX_LWIP_Init+0x228>)
- 8004bce:	785b      	ldrb	r3, [r3, #1]
- 8004bd0:	041b      	lsls	r3, r3, #16
- 8004bd2:	4319      	orrs	r1, r3
- 8004bd4:	4b47      	ldr	r3, [pc, #284]	; (8004cf4 <MX_LWIP_Init+0x228>)
- 8004bd6:	789b      	ldrb	r3, [r3, #2]
- 8004bd8:	021b      	lsls	r3, r3, #8
- 8004bda:	430b      	orrs	r3, r1
- 8004bdc:	4945      	ldr	r1, [pc, #276]	; (8004cf4 <MX_LWIP_Init+0x228>)
- 8004bde:	78c9      	ldrb	r1, [r1, #3]
- 8004be0:	430b      	orrs	r3, r1
- 8004be2:	021b      	lsls	r3, r3, #8
- 8004be4:	f403 037f 	and.w	r3, r3, #16711680	; 0xff0000
- 8004be8:	431a      	orrs	r2, r3
- 8004bea:	4b42      	ldr	r3, [pc, #264]	; (8004cf4 <MX_LWIP_Init+0x228>)
- 8004bec:	781b      	ldrb	r3, [r3, #0]
- 8004bee:	0619      	lsls	r1, r3, #24
- 8004bf0:	4b40      	ldr	r3, [pc, #256]	; (8004cf4 <MX_LWIP_Init+0x228>)
- 8004bf2:	785b      	ldrb	r3, [r3, #1]
- 8004bf4:	041b      	lsls	r3, r3, #16
- 8004bf6:	4319      	orrs	r1, r3
- 8004bf8:	4b3e      	ldr	r3, [pc, #248]	; (8004cf4 <MX_LWIP_Init+0x228>)
- 8004bfa:	789b      	ldrb	r3, [r3, #2]
- 8004bfc:	021b      	lsls	r3, r3, #8
- 8004bfe:	430b      	orrs	r3, r1
- 8004c00:	493c      	ldr	r1, [pc, #240]	; (8004cf4 <MX_LWIP_Init+0x228>)
- 8004c02:	78c9      	ldrb	r1, [r1, #3]
- 8004c04:	430b      	orrs	r3, r1
- 8004c06:	0a1b      	lsrs	r3, r3, #8
- 8004c08:	f403 437f 	and.w	r3, r3, #65280	; 0xff00
- 8004c0c:	431a      	orrs	r2, r3
- 8004c0e:	4b39      	ldr	r3, [pc, #228]	; (8004cf4 <MX_LWIP_Init+0x228>)
- 8004c10:	781b      	ldrb	r3, [r3, #0]
- 8004c12:	0619      	lsls	r1, r3, #24
- 8004c14:	4b37      	ldr	r3, [pc, #220]	; (8004cf4 <MX_LWIP_Init+0x228>)
- 8004c16:	785b      	ldrb	r3, [r3, #1]
- 8004c18:	041b      	lsls	r3, r3, #16
- 8004c1a:	4319      	orrs	r1, r3
- 8004c1c:	4b35      	ldr	r3, [pc, #212]	; (8004cf4 <MX_LWIP_Init+0x228>)
- 8004c1e:	789b      	ldrb	r3, [r3, #2]
- 8004c20:	021b      	lsls	r3, r3, #8
- 8004c22:	430b      	orrs	r3, r1
- 8004c24:	4933      	ldr	r1, [pc, #204]	; (8004cf4 <MX_LWIP_Init+0x228>)
- 8004c26:	78c9      	ldrb	r1, [r1, #3]
- 8004c28:	430b      	orrs	r3, r1
- 8004c2a:	0e1b      	lsrs	r3, r3, #24
- 8004c2c:	4313      	orrs	r3, r2
- 8004c2e:	4a34      	ldr	r2, [pc, #208]	; (8004d00 <MX_LWIP_Init+0x234>)
- 8004c30:	6013      	str	r3, [r2, #0]
-  IP4_ADDR(&gw, GATEWAY_ADDRESS[0], GATEWAY_ADDRESS[1], GATEWAY_ADDRESS[2], GATEWAY_ADDRESS[3]);
- 8004c32:	4b31      	ldr	r3, [pc, #196]	; (8004cf8 <MX_LWIP_Init+0x22c>)
- 8004c34:	781b      	ldrb	r3, [r3, #0]
- 8004c36:	061a      	lsls	r2, r3, #24
- 8004c38:	4b2f      	ldr	r3, [pc, #188]	; (8004cf8 <MX_LWIP_Init+0x22c>)
- 8004c3a:	785b      	ldrb	r3, [r3, #1]
- 8004c3c:	041b      	lsls	r3, r3, #16
- 8004c3e:	431a      	orrs	r2, r3
- 8004c40:	4b2d      	ldr	r3, [pc, #180]	; (8004cf8 <MX_LWIP_Init+0x22c>)
- 8004c42:	789b      	ldrb	r3, [r3, #2]
- 8004c44:	021b      	lsls	r3, r3, #8
- 8004c46:	4313      	orrs	r3, r2
- 8004c48:	4a2b      	ldr	r2, [pc, #172]	; (8004cf8 <MX_LWIP_Init+0x22c>)
- 8004c4a:	78d2      	ldrb	r2, [r2, #3]
- 8004c4c:	4313      	orrs	r3, r2
- 8004c4e:	061a      	lsls	r2, r3, #24
- 8004c50:	4b29      	ldr	r3, [pc, #164]	; (8004cf8 <MX_LWIP_Init+0x22c>)
- 8004c52:	781b      	ldrb	r3, [r3, #0]
- 8004c54:	0619      	lsls	r1, r3, #24
- 8004c56:	4b28      	ldr	r3, [pc, #160]	; (8004cf8 <MX_LWIP_Init+0x22c>)
- 8004c58:	785b      	ldrb	r3, [r3, #1]
- 8004c5a:	041b      	lsls	r3, r3, #16
- 8004c5c:	4319      	orrs	r1, r3
- 8004c5e:	4b26      	ldr	r3, [pc, #152]	; (8004cf8 <MX_LWIP_Init+0x22c>)
- 8004c60:	789b      	ldrb	r3, [r3, #2]
- 8004c62:	021b      	lsls	r3, r3, #8
- 8004c64:	430b      	orrs	r3, r1
- 8004c66:	4924      	ldr	r1, [pc, #144]	; (8004cf8 <MX_LWIP_Init+0x22c>)
- 8004c68:	78c9      	ldrb	r1, [r1, #3]
- 8004c6a:	430b      	orrs	r3, r1
- 8004c6c:	021b      	lsls	r3, r3, #8
- 8004c6e:	f403 037f 	and.w	r3, r3, #16711680	; 0xff0000
- 8004c72:	431a      	orrs	r2, r3
- 8004c74:	4b20      	ldr	r3, [pc, #128]	; (8004cf8 <MX_LWIP_Init+0x22c>)
- 8004c76:	781b      	ldrb	r3, [r3, #0]
- 8004c78:	0619      	lsls	r1, r3, #24
- 8004c7a:	4b1f      	ldr	r3, [pc, #124]	; (8004cf8 <MX_LWIP_Init+0x22c>)
- 8004c7c:	785b      	ldrb	r3, [r3, #1]
- 8004c7e:	041b      	lsls	r3, r3, #16
- 8004c80:	4319      	orrs	r1, r3
- 8004c82:	4b1d      	ldr	r3, [pc, #116]	; (8004cf8 <MX_LWIP_Init+0x22c>)
- 8004c84:	789b      	ldrb	r3, [r3, #2]
- 8004c86:	021b      	lsls	r3, r3, #8
- 8004c88:	430b      	orrs	r3, r1
- 8004c8a:	491b      	ldr	r1, [pc, #108]	; (8004cf8 <MX_LWIP_Init+0x22c>)
- 8004c8c:	78c9      	ldrb	r1, [r1, #3]
- 8004c8e:	430b      	orrs	r3, r1
- 8004c90:	0a1b      	lsrs	r3, r3, #8
- 8004c92:	f403 437f 	and.w	r3, r3, #65280	; 0xff00
- 8004c96:	431a      	orrs	r2, r3
- 8004c98:	4b17      	ldr	r3, [pc, #92]	; (8004cf8 <MX_LWIP_Init+0x22c>)
- 8004c9a:	781b      	ldrb	r3, [r3, #0]
- 8004c9c:	0619      	lsls	r1, r3, #24
- 8004c9e:	4b16      	ldr	r3, [pc, #88]	; (8004cf8 <MX_LWIP_Init+0x22c>)
- 8004ca0:	785b      	ldrb	r3, [r3, #1]
- 8004ca2:	041b      	lsls	r3, r3, #16
- 8004ca4:	4319      	orrs	r1, r3
- 8004ca6:	4b14      	ldr	r3, [pc, #80]	; (8004cf8 <MX_LWIP_Init+0x22c>)
- 8004ca8:	789b      	ldrb	r3, [r3, #2]
- 8004caa:	021b      	lsls	r3, r3, #8
- 8004cac:	430b      	orrs	r3, r1
- 8004cae:	4912      	ldr	r1, [pc, #72]	; (8004cf8 <MX_LWIP_Init+0x22c>)
- 8004cb0:	78c9      	ldrb	r1, [r1, #3]
- 8004cb2:	430b      	orrs	r3, r1
- 8004cb4:	0e1b      	lsrs	r3, r3, #24
- 8004cb6:	4313      	orrs	r3, r2
- 8004cb8:	4a12      	ldr	r2, [pc, #72]	; (8004d04 <MX_LWIP_Init+0x238>)
- 8004cba:	6013      	str	r3, [r2, #0]
-
-  /* add the network interface (IPv4/IPv6) without RTOS */
-  netif_add(&gnetif, &ipaddr, &netmask, &gw, NULL, &ethernetif_init, &ethernet_input);
- 8004cbc:	4b12      	ldr	r3, [pc, #72]	; (8004d08 <MX_LWIP_Init+0x23c>)
- 8004cbe:	9302      	str	r3, [sp, #8]
- 8004cc0:	4b12      	ldr	r3, [pc, #72]	; (8004d0c <MX_LWIP_Init+0x240>)
- 8004cc2:	9301      	str	r3, [sp, #4]
- 8004cc4:	2300      	movs	r3, #0
- 8004cc6:	9300      	str	r3, [sp, #0]
- 8004cc8:	4b0e      	ldr	r3, [pc, #56]	; (8004d04 <MX_LWIP_Init+0x238>)
- 8004cca:	4a0d      	ldr	r2, [pc, #52]	; (8004d00 <MX_LWIP_Init+0x234>)
- 8004ccc:	490b      	ldr	r1, [pc, #44]	; (8004cfc <MX_LWIP_Init+0x230>)
- 8004cce:	4810      	ldr	r0, [pc, #64]	; (8004d10 <MX_LWIP_Init+0x244>)
- 8004cd0:	f001 fa46 	bl	8006160 <netif_add>
-
-  /* Registers the default network interface */
-  netif_set_default(&gnetif);
- 8004cd4:	480e      	ldr	r0, [pc, #56]	; (8004d10 <MX_LWIP_Init+0x244>)
- 8004cd6:	f001 fcd7 	bl	8006688 <netif_set_default>
-
-  /* We must always bring the network interface up connection or not... */
-  netif_set_up(&gnetif);
- 8004cda:	480d      	ldr	r0, [pc, #52]	; (8004d10 <MX_LWIP_Init+0x244>)
- 8004cdc:	f001 fcf8 	bl	80066d0 <netif_set_up>
-
-  /* Set the link callback function, this function is called on change of link status*/
-  netif_set_link_callback(&gnetif, ethernet_link_status_updated);
- 8004ce0:	490c      	ldr	r1, [pc, #48]	; (8004d14 <MX_LWIP_Init+0x248>)
- 8004ce2:	480b      	ldr	r0, [pc, #44]	; (8004d10 <MX_LWIP_Init+0x244>)
- 8004ce4:	f001 fdf6 	bl	80068d4 <netif_set_link_callback>
-  /* Create the Ethernet link handler thread */
-
-/* USER CODE BEGIN 3 */
-
-/* USER CODE END 3 */
-}
- 8004ce8:	bf00      	nop
- 8004cea:	46bd      	mov	sp, r7
- 8004cec:	bd80      	pop	{r7, pc}
- 8004cee:	bf00      	nop
- 8004cf0:	24000170 	.word	0x24000170
- 8004cf4:	24000174 	.word	0x24000174
- 8004cf8:	24000178 	.word	0x24000178
- 8004cfc:	24000164 	.word	0x24000164
- 8004d00:	24000168 	.word	0x24000168
- 8004d04:	2400016c 	.word	0x2400016c
- 8004d08:	080100b5 	.word	0x080100b5
- 8004d0c:	08005021 	.word	0x08005021
- 8004d10:	24000130 	.word	0x24000130
- 8004d14:	08004d69 	.word	0x08004d69
-
-08004d18 <Ethernet_Link_Periodic_Handle>:
-  * @brief  Ethernet Link periodic check
-  * @param  netif
-  * @retval None
-  */
-static void Ethernet_Link_Periodic_Handle(struct netif *netif)
-{
- 8004d18:	b580      	push	{r7, lr}
- 8004d1a:	b082      	sub	sp, #8
- 8004d1c:	af00      	add	r7, sp, #0
- 8004d1e:	6078      	str	r0, [r7, #4]
-/* USER CODE BEGIN 4_4_1 */
-/* USER CODE END 4_4_1 */
-
-  /* Ethernet Link every 100ms */
-  if (HAL_GetTick() - EthernetLinkTimer >= 100)
- 8004d20:	f7fc f974 	bl	800100c <HAL_GetTick>
- 8004d24:	4602      	mov	r2, r0
- 8004d26:	4b08      	ldr	r3, [pc, #32]	; (8004d48 <Ethernet_Link_Periodic_Handle+0x30>)
- 8004d28:	681b      	ldr	r3, [r3, #0]
- 8004d2a:	1ad3      	subs	r3, r2, r3
- 8004d2c:	2b63      	cmp	r3, #99	; 0x63
- 8004d2e:	d907      	bls.n	8004d40 <Ethernet_Link_Periodic_Handle+0x28>
-  {
-    EthernetLinkTimer = HAL_GetTick();
- 8004d30:	f7fc f96c 	bl	800100c <HAL_GetTick>
- 8004d34:	4603      	mov	r3, r0
- 8004d36:	4a04      	ldr	r2, [pc, #16]	; (8004d48 <Ethernet_Link_Periodic_Handle+0x30>)
- 8004d38:	6013      	str	r3, [r2, #0]
-    ethernet_link_check_state(netif);
- 8004d3a:	6878      	ldr	r0, [r7, #4]
- 8004d3c:	f000 fac2 	bl	80052c4 <ethernet_link_check_state>
-  }
-/* USER CODE BEGIN 4_4 */
-/* USER CODE END 4_4 */
-}
- 8004d40:	bf00      	nop
- 8004d42:	3708      	adds	r7, #8
- 8004d44:	46bd      	mov	sp, r7
- 8004d46:	bd80      	pop	{r7, pc}
- 8004d48:	2400012c 	.word	0x2400012c
-
-08004d4c <MX_LWIP_Process>:
- * Send it to the lwIP stack for handling
- * Handle timeouts if LWIP_TIMERS is set and without RTOS
- * Handle the llink status if LWIP_NETIF_LINK_CALLBACK is set and without RTOS
- */
-void MX_LWIP_Process(void)
-{
- 8004d4c:	b580      	push	{r7, lr}
- 8004d4e:	af00      	add	r7, sp, #0
-/* USER CODE BEGIN 4_1 */
-/* USER CODE END 4_1 */
-  ethernetif_input(&gnetif);
- 8004d50:	4804      	ldr	r0, [pc, #16]	; (8004d64 <MX_LWIP_Process+0x18>)
- 8004d52:	f000 f945 	bl	8004fe0 <ethernetif_input>
-
-/* USER CODE BEGIN 4_2 */
-/* USER CODE END 4_2 */
-  /* Handle timeouts */
-  sys_check_timeouts();
- 8004d56:	f008 fcd7 	bl	800d708 <sys_check_timeouts>
-
-  Ethernet_Link_Periodic_Handle(&gnetif);
- 8004d5a:	4802      	ldr	r0, [pc, #8]	; (8004d64 <MX_LWIP_Process+0x18>)
- 8004d5c:	f7ff ffdc 	bl	8004d18 <Ethernet_Link_Periodic_Handle>
-
-/* USER CODE BEGIN 4_3 */
-/* USER CODE END 4_3 */
-}
- 8004d60:	bf00      	nop
- 8004d62:	bd80      	pop	{r7, pc}
- 8004d64:	24000130 	.word	0x24000130
-
-08004d68 <ethernet_link_status_updated>:
-  * @brief  Notify the User about the network interface config status
-  * @param  netif: the network interface
-  * @retval None
-  */
-static void ethernet_link_status_updated(struct netif *netif)
-{
- 8004d68:	b480      	push	{r7}
- 8004d6a:	b083      	sub	sp, #12
- 8004d6c:	af00      	add	r7, sp, #0
- 8004d6e:	6078      	str	r0, [r7, #4]
-  else /* netif is down */
-  {
-/* USER CODE BEGIN 6 */
-/* USER CODE END 6 */
-  }
-}
- 8004d70:	bf00      	nop
- 8004d72:	370c      	adds	r7, #12
- 8004d74:	46bd      	mov	sp, r7
- 8004d76:	f85d 7b04 	ldr.w	r7, [sp], #4
- 8004d7a:	4770      	bx	lr
-
-08004d7c <low_level_init>:
- *
- * @param netif the already initialized lwip network interface structure
- *        for this ethernetif
- */
-static void low_level_init(struct netif *netif)
-{
- 8004d7c:	b580      	push	{r7, lr}
- 8004d7e:	b084      	sub	sp, #16
- 8004d80:	af00      	add	r7, sp, #0
- 8004d82:	6078      	str	r0, [r7, #4]
-  HAL_StatusTypeDef hal_eth_init_status = HAL_OK;
- 8004d84:	2300      	movs	r3, #0
- 8004d86:	73fb      	strb	r3, [r7, #15]
-  /* Start ETH HAL Init */
-
-   uint8_t MACAddr[6] ;
-  heth.Instance = ETH;
- 8004d88:	4b3f      	ldr	r3, [pc, #252]	; (8004e88 <low_level_init+0x10c>)
- 8004d8a:	4a40      	ldr	r2, [pc, #256]	; (8004e8c <low_level_init+0x110>)
- 8004d8c:	601a      	str	r2, [r3, #0]
-  MACAddr[0] = 0x00;
- 8004d8e:	2300      	movs	r3, #0
- 8004d90:	723b      	strb	r3, [r7, #8]
-  MACAddr[1] = 0x80;
- 8004d92:	2380      	movs	r3, #128	; 0x80
- 8004d94:	727b      	strb	r3, [r7, #9]
-  MACAddr[2] = 0xE1;
- 8004d96:	23e1      	movs	r3, #225	; 0xe1
- 8004d98:	72bb      	strb	r3, [r7, #10]
-  MACAddr[3] = 0x00;
- 8004d9a:	2300      	movs	r3, #0
- 8004d9c:	72fb      	strb	r3, [r7, #11]
-  MACAddr[4] = 0x00;
- 8004d9e:	2300      	movs	r3, #0
- 8004da0:	733b      	strb	r3, [r7, #12]
-  MACAddr[5] = 0x00;
- 8004da2:	2300      	movs	r3, #0
- 8004da4:	737b      	strb	r3, [r7, #13]
-  heth.Init.MACAddr = &MACAddr[0];
- 8004da6:	4a38      	ldr	r2, [pc, #224]	; (8004e88 <low_level_init+0x10c>)
- 8004da8:	f107 0308 	add.w	r3, r7, #8
- 8004dac:	6053      	str	r3, [r2, #4]
-  heth.Init.MediaInterface = HAL_ETH_RMII_MODE;
- 8004dae:	4b36      	ldr	r3, [pc, #216]	; (8004e88 <low_level_init+0x10c>)
- 8004db0:	2201      	movs	r2, #1
- 8004db2:	721a      	strb	r2, [r3, #8]
-  heth.Init.TxDesc = DMATxDscrTab;
- 8004db4:	4b34      	ldr	r3, [pc, #208]	; (8004e88 <low_level_init+0x10c>)
- 8004db6:	4a36      	ldr	r2, [pc, #216]	; (8004e90 <low_level_init+0x114>)
- 8004db8:	60da      	str	r2, [r3, #12]
-  heth.Init.RxDesc = DMARxDscrTab;
- 8004dba:	4b33      	ldr	r3, [pc, #204]	; (8004e88 <low_level_init+0x10c>)
- 8004dbc:	4a35      	ldr	r2, [pc, #212]	; (8004e94 <low_level_init+0x118>)
- 8004dbe:	611a      	str	r2, [r3, #16]
-  heth.Init.RxBuffLen = 1536;
- 8004dc0:	4b31      	ldr	r3, [pc, #196]	; (8004e88 <low_level_init+0x10c>)
- 8004dc2:	f44f 62c0 	mov.w	r2, #1536	; 0x600
- 8004dc6:	615a      	str	r2, [r3, #20]
-
-  /* USER CODE BEGIN MACADDRESS */
-
-  /* USER CODE END MACADDRESS */
-
-  hal_eth_init_status = HAL_ETH_Init(&heth);
- 8004dc8:	482f      	ldr	r0, [pc, #188]	; (8004e88 <low_level_init+0x10c>)
- 8004dca:	f7fc facb 	bl	8001364 <HAL_ETH_Init>
- 8004dce:	4603      	mov	r3, r0
- 8004dd0:	73fb      	strb	r3, [r7, #15]
-
-  memset(&TxConfig, 0 , sizeof(ETH_TxPacketConfig));
- 8004dd2:	2238      	movs	r2, #56	; 0x38
- 8004dd4:	2100      	movs	r1, #0
- 8004dd6:	4830      	ldr	r0, [pc, #192]	; (8004e98 <low_level_init+0x11c>)
- 8004dd8:	f00c f854 	bl	8010e84 <memset>
-  TxConfig.Attributes = ETH_TX_PACKETS_FEATURES_CSUM | ETH_TX_PACKETS_FEATURES_CRCPAD;
- 8004ddc:	4b2e      	ldr	r3, [pc, #184]	; (8004e98 <low_level_init+0x11c>)
- 8004dde:	2221      	movs	r2, #33	; 0x21
- 8004de0:	601a      	str	r2, [r3, #0]
-  TxConfig.ChecksumCtrl = ETH_CHECKSUM_IPHDR_PAYLOAD_INSERT_PHDR_CALC;
- 8004de2:	4b2d      	ldr	r3, [pc, #180]	; (8004e98 <low_level_init+0x11c>)
- 8004de4:	f44f 3240 	mov.w	r2, #196608	; 0x30000
- 8004de8:	615a      	str	r2, [r3, #20]
-  TxConfig.CRCPadCtrl = ETH_CRC_PAD_INSERT;
- 8004dea:	4b2b      	ldr	r3, [pc, #172]	; (8004e98 <low_level_init+0x11c>)
- 8004dec:	2200      	movs	r2, #0
- 8004dee:	611a      	str	r2, [r3, #16]
-
-  /* End ETH HAL Init */
-
-  /* Initialize the RX POOL */
-  LWIP_MEMPOOL_INIT(RX_POOL);
- 8004df0:	482a      	ldr	r0, [pc, #168]	; (8004e9c <low_level_init+0x120>)
- 8004df2:	f001 f875 	bl	8005ee0 <memp_init_pool>
-
-#if LWIP_ARP || LWIP_ETHERNET
-
-  /* set MAC hardware address length */
-  netif->hwaddr_len = ETH_HWADDR_LEN;
- 8004df6:	687b      	ldr	r3, [r7, #4]
- 8004df8:	2206      	movs	r2, #6
- 8004dfa:	f883 202c 	strb.w	r2, [r3, #44]	; 0x2c
-
-  /* set MAC hardware address */
-  netif->hwaddr[0] =  heth.Init.MACAddr[0];
- 8004dfe:	4b22      	ldr	r3, [pc, #136]	; (8004e88 <low_level_init+0x10c>)
- 8004e00:	685b      	ldr	r3, [r3, #4]
- 8004e02:	781a      	ldrb	r2, [r3, #0]
- 8004e04:	687b      	ldr	r3, [r7, #4]
- 8004e06:	f883 2026 	strb.w	r2, [r3, #38]	; 0x26
-  netif->hwaddr[1] =  heth.Init.MACAddr[1];
- 8004e0a:	4b1f      	ldr	r3, [pc, #124]	; (8004e88 <low_level_init+0x10c>)
- 8004e0c:	685b      	ldr	r3, [r3, #4]
- 8004e0e:	785a      	ldrb	r2, [r3, #1]
- 8004e10:	687b      	ldr	r3, [r7, #4]
- 8004e12:	f883 2027 	strb.w	r2, [r3, #39]	; 0x27
-  netif->hwaddr[2] =  heth.Init.MACAddr[2];
- 8004e16:	4b1c      	ldr	r3, [pc, #112]	; (8004e88 <low_level_init+0x10c>)
- 8004e18:	685b      	ldr	r3, [r3, #4]
- 8004e1a:	789a      	ldrb	r2, [r3, #2]
- 8004e1c:	687b      	ldr	r3, [r7, #4]
- 8004e1e:	f883 2028 	strb.w	r2, [r3, #40]	; 0x28
-  netif->hwaddr[3] =  heth.Init.MACAddr[3];
- 8004e22:	4b19      	ldr	r3, [pc, #100]	; (8004e88 <low_level_init+0x10c>)
- 8004e24:	685b      	ldr	r3, [r3, #4]
- 8004e26:	78da      	ldrb	r2, [r3, #3]
- 8004e28:	687b      	ldr	r3, [r7, #4]
- 8004e2a:	f883 2029 	strb.w	r2, [r3, #41]	; 0x29
-  netif->hwaddr[4] =  heth.Init.MACAddr[4];
- 8004e2e:	4b16      	ldr	r3, [pc, #88]	; (8004e88 <low_level_init+0x10c>)
- 8004e30:	685b      	ldr	r3, [r3, #4]
- 8004e32:	791a      	ldrb	r2, [r3, #4]
- 8004e34:	687b      	ldr	r3, [r7, #4]
- 8004e36:	f883 202a 	strb.w	r2, [r3, #42]	; 0x2a
-  netif->hwaddr[5] =  heth.Init.MACAddr[5];
- 8004e3a:	4b13      	ldr	r3, [pc, #76]	; (8004e88 <low_level_init+0x10c>)
- 8004e3c:	685b      	ldr	r3, [r3, #4]
- 8004e3e:	795a      	ldrb	r2, [r3, #5]
- 8004e40:	687b      	ldr	r3, [r7, #4]
- 8004e42:	f883 202b 	strb.w	r2, [r3, #43]	; 0x2b
-
-  /* maximum transfer unit */
-  netif->mtu = ETH_MAX_PAYLOAD;
- 8004e46:	687b      	ldr	r3, [r7, #4]
- 8004e48:	f240 52dc 	movw	r2, #1500	; 0x5dc
- 8004e4c:	849a      	strh	r2, [r3, #36]	; 0x24
-
-  /* Accept broadcast address and ARP traffic */
-  /* don't set NETIF_FLAG_ETHARP if this device is not an ethernet one */
-  #if LWIP_ARP
-    netif->flags |= NETIF_FLAG_BROADCAST | NETIF_FLAG_ETHARP;
- 8004e4e:	687b      	ldr	r3, [r7, #4]
- 8004e50:	f893 302d 	ldrb.w	r3, [r3, #45]	; 0x2d
- 8004e54:	f043 030a 	orr.w	r3, r3, #10
- 8004e58:	b2da      	uxtb	r2, r3
- 8004e5a:	687b      	ldr	r3, [r7, #4]
- 8004e5c:	f883 202d 	strb.w	r2, [r3, #45]	; 0x2d
-
-/* USER CODE BEGIN PHY_PRE_CONFIG */
-
-/* USER CODE END PHY_PRE_CONFIG */
-  /* Set PHY IO functions */
-  LAN8742_RegisterBusIO(&LAN8742, &LAN8742_IOCtx);
- 8004e60:	490f      	ldr	r1, [pc, #60]	; (8004ea0 <low_level_init+0x124>)
- 8004e62:	4810      	ldr	r0, [pc, #64]	; (8004ea4 <low_level_init+0x128>)
- 8004e64:	f7fb feeb 	bl	8000c3e <LAN8742_RegisterBusIO>
-
-  /* Initialize the LAN8742 ETH PHY */
-  LAN8742_Init(&LAN8742);
- 8004e68:	480e      	ldr	r0, [pc, #56]	; (8004ea4 <low_level_init+0x128>)
- 8004e6a:	f7fb ff1a 	bl	8000ca2 <LAN8742_Init>
-
-  if (hal_eth_init_status == HAL_OK)
- 8004e6e:	7bfb      	ldrb	r3, [r7, #15]
- 8004e70:	2b00      	cmp	r3, #0
- 8004e72:	d103      	bne.n	8004e7c <low_level_init+0x100>
-  {
-  /* Get link state */
-  ethernet_link_check_state(netif);
- 8004e74:	6878      	ldr	r0, [r7, #4]
- 8004e76:	f000 fa25 	bl	80052c4 <ethernet_link_check_state>
-#endif /* LWIP_ARP || LWIP_ETHERNET */
-
-/* USER CODE BEGIN LOW_LEVEL_INIT */
-
-/* USER CODE END LOW_LEVEL_INIT */
-}
- 8004e7a:	e001      	b.n	8004e80 <low_level_init+0x104>
-    Error_Handler();
- 8004e7c:	f7fb fd2d 	bl	80008da <Error_Handler>
-}
- 8004e80:	bf00      	nop
- 8004e82:	3710      	adds	r7, #16
- 8004e84:	46bd      	mov	sp, r7
- 8004e86:	bd80      	pop	{r7, pc}
- 8004e88:	24004b08 	.word	0x24004b08
- 8004e8c:	40028000 	.word	0x40028000
- 8004e90:	30000100 	.word	0x30000100
- 8004e94:	30000000 	.word	0x30000000
- 8004e98:	24004bb8 	.word	0x24004bb8
- 8004e9c:	08014c90 	.word	0x08014c90
- 8004ea0:	24000010 	.word	0x24000010
- 8004ea4:	24004bf0 	.word	0x24004bf0
-
-08004ea8 <low_level_output>:
- *       to become available since the stack doesn't retry to send a packet
- *       dropped because of memory failure (except for the TCP timers).
- */
-
-static err_t low_level_output(struct netif *netif, struct pbuf *p)
-{
- 8004ea8:	b580      	push	{r7, lr}
- 8004eaa:	b092      	sub	sp, #72	; 0x48
- 8004eac:	af00      	add	r7, sp, #0
- 8004eae:	6078      	str	r0, [r7, #4]
- 8004eb0:	6039      	str	r1, [r7, #0]
-  uint32_t i = 0U;
- 8004eb2:	2300      	movs	r3, #0
- 8004eb4:	647b      	str	r3, [r7, #68]	; 0x44
-  struct pbuf *q = NULL;
- 8004eb6:	2300      	movs	r3, #0
- 8004eb8:	643b      	str	r3, [r7, #64]	; 0x40
-  err_t errval = ERR_OK;
- 8004eba:	2300      	movs	r3, #0
- 8004ebc:	f887 303f 	strb.w	r3, [r7, #63]	; 0x3f
-  ETH_BufferTypeDef Txbuffer[ETH_TX_DESC_CNT] = {0};
- 8004ec0:	f107 030c 	add.w	r3, r7, #12
- 8004ec4:	2230      	movs	r2, #48	; 0x30
- 8004ec6:	2100      	movs	r1, #0
- 8004ec8:	4618      	mov	r0, r3
- 8004eca:	f00b ffdb 	bl	8010e84 <memset>
-
-  memset(Txbuffer, 0 , ETH_TX_DESC_CNT*sizeof(ETH_BufferTypeDef));
- 8004ece:	f107 030c 	add.w	r3, r7, #12
- 8004ed2:	2230      	movs	r2, #48	; 0x30
- 8004ed4:	2100      	movs	r1, #0
- 8004ed6:	4618      	mov	r0, r3
- 8004ed8:	f00b ffd4 	bl	8010e84 <memset>
-
-  for(q = p; q != NULL; q = q->next)
- 8004edc:	683b      	ldr	r3, [r7, #0]
- 8004ede:	643b      	str	r3, [r7, #64]	; 0x40
- 8004ee0:	e045      	b.n	8004f6e <low_level_output+0xc6>
-  {
-    if(i >= ETH_TX_DESC_CNT)
- 8004ee2:	6c7b      	ldr	r3, [r7, #68]	; 0x44
- 8004ee4:	2b03      	cmp	r3, #3
- 8004ee6:	d902      	bls.n	8004eee <low_level_output+0x46>
-      return ERR_IF;
- 8004ee8:	f06f 030b 	mvn.w	r3, #11
- 8004eec:	e055      	b.n	8004f9a <low_level_output+0xf2>
-
-    Txbuffer[i].buffer = q->payload;
- 8004eee:	6c3b      	ldr	r3, [r7, #64]	; 0x40
- 8004ef0:	6859      	ldr	r1, [r3, #4]
- 8004ef2:	6c7a      	ldr	r2, [r7, #68]	; 0x44
- 8004ef4:	4613      	mov	r3, r2
- 8004ef6:	005b      	lsls	r3, r3, #1
- 8004ef8:	4413      	add	r3, r2
- 8004efa:	009b      	lsls	r3, r3, #2
- 8004efc:	3348      	adds	r3, #72	; 0x48
- 8004efe:	443b      	add	r3, r7
- 8004f00:	3b3c      	subs	r3, #60	; 0x3c
- 8004f02:	6019      	str	r1, [r3, #0]
-    Txbuffer[i].len = q->len;
- 8004f04:	6c3b      	ldr	r3, [r7, #64]	; 0x40
- 8004f06:	895b      	ldrh	r3, [r3, #10]
- 8004f08:	4619      	mov	r1, r3
- 8004f0a:	6c7a      	ldr	r2, [r7, #68]	; 0x44
- 8004f0c:	4613      	mov	r3, r2
- 8004f0e:	005b      	lsls	r3, r3, #1
- 8004f10:	4413      	add	r3, r2
- 8004f12:	009b      	lsls	r3, r3, #2
- 8004f14:	3348      	adds	r3, #72	; 0x48
- 8004f16:	443b      	add	r3, r7
- 8004f18:	3b38      	subs	r3, #56	; 0x38
- 8004f1a:	6019      	str	r1, [r3, #0]
-
-    if(i>0)
- 8004f1c:	6c7b      	ldr	r3, [r7, #68]	; 0x44
- 8004f1e:	2b00      	cmp	r3, #0
- 8004f20:	d011      	beq.n	8004f46 <low_level_output+0x9e>
-    {
-      Txbuffer[i-1].next = &Txbuffer[i];
- 8004f22:	6c7b      	ldr	r3, [r7, #68]	; 0x44
- 8004f24:	1e5a      	subs	r2, r3, #1
- 8004f26:	f107 000c 	add.w	r0, r7, #12
- 8004f2a:	6c79      	ldr	r1, [r7, #68]	; 0x44
- 8004f2c:	460b      	mov	r3, r1
- 8004f2e:	005b      	lsls	r3, r3, #1
- 8004f30:	440b      	add	r3, r1
- 8004f32:	009b      	lsls	r3, r3, #2
- 8004f34:	18c1      	adds	r1, r0, r3
- 8004f36:	4613      	mov	r3, r2
- 8004f38:	005b      	lsls	r3, r3, #1
- 8004f3a:	4413      	add	r3, r2
- 8004f3c:	009b      	lsls	r3, r3, #2
- 8004f3e:	3348      	adds	r3, #72	; 0x48
- 8004f40:	443b      	add	r3, r7
- 8004f42:	3b34      	subs	r3, #52	; 0x34
- 8004f44:	6019      	str	r1, [r3, #0]
-    }
-
-    if(q->next == NULL)
- 8004f46:	6c3b      	ldr	r3, [r7, #64]	; 0x40
- 8004f48:	681b      	ldr	r3, [r3, #0]
- 8004f4a:	2b00      	cmp	r3, #0
- 8004f4c:	d109      	bne.n	8004f62 <low_level_output+0xba>
-    {
-      Txbuffer[i].next = NULL;
- 8004f4e:	6c7a      	ldr	r2, [r7, #68]	; 0x44
- 8004f50:	4613      	mov	r3, r2
- 8004f52:	005b      	lsls	r3, r3, #1
- 8004f54:	4413      	add	r3, r2
- 8004f56:	009b      	lsls	r3, r3, #2
- 8004f58:	3348      	adds	r3, #72	; 0x48
- 8004f5a:	443b      	add	r3, r7
- 8004f5c:	3b34      	subs	r3, #52	; 0x34
- 8004f5e:	2200      	movs	r2, #0
- 8004f60:	601a      	str	r2, [r3, #0]
-    }
-
-    i++;
- 8004f62:	6c7b      	ldr	r3, [r7, #68]	; 0x44
- 8004f64:	3301      	adds	r3, #1
- 8004f66:	647b      	str	r3, [r7, #68]	; 0x44
-  for(q = p; q != NULL; q = q->next)
- 8004f68:	6c3b      	ldr	r3, [r7, #64]	; 0x40
- 8004f6a:	681b      	ldr	r3, [r3, #0]
- 8004f6c:	643b      	str	r3, [r7, #64]	; 0x40
- 8004f6e:	6c3b      	ldr	r3, [r7, #64]	; 0x40
- 8004f70:	2b00      	cmp	r3, #0
- 8004f72:	d1b6      	bne.n	8004ee2 <low_level_output+0x3a>
-  }
-
-  TxConfig.Length = p->tot_len;
- 8004f74:	683b      	ldr	r3, [r7, #0]
- 8004f76:	891b      	ldrh	r3, [r3, #8]
- 8004f78:	461a      	mov	r2, r3
- 8004f7a:	4b0a      	ldr	r3, [pc, #40]	; (8004fa4 <low_level_output+0xfc>)
- 8004f7c:	605a      	str	r2, [r3, #4]
-  TxConfig.TxBuffer = Txbuffer;
- 8004f7e:	4a09      	ldr	r2, [pc, #36]	; (8004fa4 <low_level_output+0xfc>)
- 8004f80:	f107 030c 	add.w	r3, r7, #12
- 8004f84:	6093      	str	r3, [r2, #8]
-  TxConfig.pData = p;
- 8004f86:	4a07      	ldr	r2, [pc, #28]	; (8004fa4 <low_level_output+0xfc>)
- 8004f88:	683b      	ldr	r3, [r7, #0]
- 8004f8a:	6353      	str	r3, [r2, #52]	; 0x34
-
-  HAL_ETH_Transmit(&heth, &TxConfig, ETH_DMA_TRANSMIT_TIMEOUT);
- 8004f8c:	2214      	movs	r2, #20
- 8004f8e:	4905      	ldr	r1, [pc, #20]	; (8004fa4 <low_level_output+0xfc>)
- 8004f90:	4805      	ldr	r0, [pc, #20]	; (8004fa8 <low_level_output+0x100>)
- 8004f92:	f7fc fb7f 	bl	8001694 <HAL_ETH_Transmit>
-
-  return errval;
- 8004f96:	f997 303f 	ldrsb.w	r3, [r7, #63]	; 0x3f
-}
- 8004f9a:	4618      	mov	r0, r3
- 8004f9c:	3748      	adds	r7, #72	; 0x48
- 8004f9e:	46bd      	mov	sp, r7
- 8004fa0:	bd80      	pop	{r7, pc}
- 8004fa2:	bf00      	nop
- 8004fa4:	24004bb8 	.word	0x24004bb8
- 8004fa8:	24004b08 	.word	0x24004b08
-
-08004fac <low_level_input>:
- * @param netif the lwip network interface structure for this ethernetif
- * @return a pbuf filled with the received packet (including MAC header)
- *         NULL on memory error
-   */
-static struct pbuf * low_level_input(struct netif *netif)
-{
- 8004fac:	b580      	push	{r7, lr}
- 8004fae:	b084      	sub	sp, #16
- 8004fb0:	af00      	add	r7, sp, #0
- 8004fb2:	6078      	str	r0, [r7, #4]
-  struct pbuf *p = NULL;
- 8004fb4:	2300      	movs	r3, #0
- 8004fb6:	60fb      	str	r3, [r7, #12]
-
-  if(RxAllocStatus == RX_ALLOC_OK)
- 8004fb8:	4b07      	ldr	r3, [pc, #28]	; (8004fd8 <low_level_input+0x2c>)
- 8004fba:	781b      	ldrb	r3, [r3, #0]
- 8004fbc:	2b00      	cmp	r3, #0
- 8004fbe:	d105      	bne.n	8004fcc <low_level_input+0x20>
-  {
-    HAL_ETH_ReadData(&heth, (void **)&p);
- 8004fc0:	f107 030c 	add.w	r3, r7, #12
- 8004fc4:	4619      	mov	r1, r3
- 8004fc6:	4805      	ldr	r0, [pc, #20]	; (8004fdc <low_level_input+0x30>)
- 8004fc8:	f7fc fbfb 	bl	80017c2 <HAL_ETH_ReadData>
-  }
-
-  return p;
- 8004fcc:	68fb      	ldr	r3, [r7, #12]
-}
- 8004fce:	4618      	mov	r0, r3
- 8004fd0:	3710      	adds	r7, #16
- 8004fd2:	46bd      	mov	sp, r7
- 8004fd4:	bd80      	pop	{r7, pc}
- 8004fd6:	bf00      	nop
- 8004fd8:	24004b04 	.word	0x24004b04
- 8004fdc:	24004b08 	.word	0x24004b08
-
-08004fe0 <ethernetif_input>:
- * the appropriate input function is called.
- *
- * @param netif the lwip network interface structure for this ethernetif
- */
-void ethernetif_input(struct netif *netif)
-{
- 8004fe0:	b580      	push	{r7, lr}
- 8004fe2:	b084      	sub	sp, #16
- 8004fe4:	af00      	add	r7, sp, #0
- 8004fe6:	6078      	str	r0, [r7, #4]
-  struct pbuf *p = NULL;
- 8004fe8:	2300      	movs	r3, #0
- 8004fea:	60fb      	str	r3, [r7, #12]
-
-  do
-  {
-    p = low_level_input( netif );
- 8004fec:	6878      	ldr	r0, [r7, #4]
- 8004fee:	f7ff ffdd 	bl	8004fac <low_level_input>
- 8004ff2:	60f8      	str	r0, [r7, #12]
-    if (p != NULL)
- 8004ff4:	68fb      	ldr	r3, [r7, #12]
- 8004ff6:	2b00      	cmp	r3, #0
- 8004ff8:	d00a      	beq.n	8005010 <ethernetif_input+0x30>
-    {
-      if (netif->input( p, netif) != ERR_OK )
- 8004ffa:	687b      	ldr	r3, [r7, #4]
- 8004ffc:	691b      	ldr	r3, [r3, #16]
- 8004ffe:	6879      	ldr	r1, [r7, #4]
- 8005000:	68f8      	ldr	r0, [r7, #12]
- 8005002:	4798      	blx	r3
- 8005004:	4603      	mov	r3, r0
- 8005006:	2b00      	cmp	r3, #0
- 8005008:	d002      	beq.n	8005010 <ethernetif_input+0x30>
-      {
-        pbuf_free(p);
- 800500a:	68f8      	ldr	r0, [r7, #12]
- 800500c:	f001 ffe2 	bl	8006fd4 <pbuf_free>
-      }
-    }
-  } while(p!=NULL);
- 8005010:	68fb      	ldr	r3, [r7, #12]
- 8005012:	2b00      	cmp	r3, #0
- 8005014:	d1ea      	bne.n	8004fec <ethernetif_input+0xc>
-}
- 8005016:	bf00      	nop
- 8005018:	bf00      	nop
- 800501a:	3710      	adds	r7, #16
- 800501c:	46bd      	mov	sp, r7
- 800501e:	bd80      	pop	{r7, pc}
-
-08005020 <ethernetif_init>:
- * @return ERR_OK if the loopif is initialized
- *         ERR_MEM if private data couldn't be allocated
- *         any other err_t on error
- */
-err_t ethernetif_init(struct netif *netif)
-{
- 8005020:	b580      	push	{r7, lr}
- 8005022:	b082      	sub	sp, #8
- 8005024:	af00      	add	r7, sp, #0
- 8005026:	6078      	str	r0, [r7, #4]
-  LWIP_ASSERT("netif != NULL", (netif != NULL));
- 8005028:	687b      	ldr	r3, [r7, #4]
- 800502a:	2b00      	cmp	r3, #0
- 800502c:	d106      	bne.n	800503c <ethernetif_init+0x1c>
- 800502e:	4b0e      	ldr	r3, [pc, #56]	; (8005068 <ethernetif_init+0x48>)
- 8005030:	f240 127b 	movw	r2, #379	; 0x17b
- 8005034:	490d      	ldr	r1, [pc, #52]	; (800506c <ethernetif_init+0x4c>)
- 8005036:	480e      	ldr	r0, [pc, #56]	; (8005070 <ethernetif_init+0x50>)
- 8005038:	f00b fdc6 	bl	8010bc8 <iprintf>
-   * The last argument should be replaced with your link speed, in units
-   * of bits per second.
-   */
-  // MIB2_INIT_NETIF(netif, snmp_ifType_ethernet_csmacd, LINK_SPEED_OF_YOUR_NETIF_IN_BPS);
-
-  netif->name[0] = IFNAME0;
- 800503c:	687b      	ldr	r3, [r7, #4]
- 800503e:	2273      	movs	r2, #115	; 0x73
- 8005040:	f883 202e 	strb.w	r2, [r3, #46]	; 0x2e
-  netif->name[1] = IFNAME1;
- 8005044:	687b      	ldr	r3, [r7, #4]
- 8005046:	2274      	movs	r2, #116	; 0x74
- 8005048:	f883 202f 	strb.w	r2, [r3, #47]	; 0x2f
-   * is available...) */
-
-#if LWIP_IPV4
-#if LWIP_ARP || LWIP_ETHERNET
-#if LWIP_ARP
-  netif->output = etharp_output;
- 800504c:	687b      	ldr	r3, [r7, #4]
- 800504e:	4a09      	ldr	r2, [pc, #36]	; (8005074 <ethernetif_init+0x54>)
- 8005050:	615a      	str	r2, [r3, #20]
-
-#if LWIP_IPV6
-  netif->output_ip6 = ethip6_output;
-#endif /* LWIP_IPV6 */
-
-  netif->linkoutput = low_level_output;
- 8005052:	687b      	ldr	r3, [r7, #4]
- 8005054:	4a08      	ldr	r2, [pc, #32]	; (8005078 <ethernetif_init+0x58>)
- 8005056:	619a      	str	r2, [r3, #24]
-
-  /* initialize the hardware */
-  low_level_init(netif);
- 8005058:	6878      	ldr	r0, [r7, #4]
- 800505a:	f7ff fe8f 	bl	8004d7c <low_level_init>
-
-  return ERR_OK;
- 800505e:	2300      	movs	r3, #0
-}
- 8005060:	4618      	mov	r0, r3
- 8005062:	3708      	adds	r7, #8
- 8005064:	46bd      	mov	sp, r7
- 8005066:	bd80      	pop	{r7, pc}
- 8005068:	08011b00 	.word	0x08011b00
- 800506c:	08011b1c 	.word	0x08011b1c
- 8005070:	08011b2c 	.word	0x08011b2c
- 8005074:	0800e3f5 	.word	0x0800e3f5
- 8005078:	08004ea9 	.word	0x08004ea9
-
-0800507c <pbuf_free_custom>:
-  * @brief  Custom Rx pbuf free callback
-  * @param  pbuf: pbuf to be freed
-  * @retval None
-  */
-void pbuf_free_custom(struct pbuf *p)
-{
- 800507c:	b580      	push	{r7, lr}
- 800507e:	b084      	sub	sp, #16
- 8005080:	af00      	add	r7, sp, #0
- 8005082:	6078      	str	r0, [r7, #4]
-  struct pbuf_custom* custom_pbuf = (struct pbuf_custom*)p;
- 8005084:	687b      	ldr	r3, [r7, #4]
- 8005086:	60fb      	str	r3, [r7, #12]
-  LWIP_MEMPOOL_FREE(RX_POOL, custom_pbuf);
- 8005088:	68f9      	ldr	r1, [r7, #12]
- 800508a:	4807      	ldr	r0, [pc, #28]	; (80050a8 <pbuf_free_custom+0x2c>)
- 800508c:	f001 f812 	bl	80060b4 <memp_free_pool>
-
-  /* If the Rx Buffer Pool was exhausted, signal the ethernetif_input task to
-   * call HAL_ETH_GetRxDataBuffer to rebuild the Rx descriptors. */
-
-  if (RxAllocStatus == RX_ALLOC_ERROR)
- 8005090:	4b06      	ldr	r3, [pc, #24]	; (80050ac <pbuf_free_custom+0x30>)
- 8005092:	781b      	ldrb	r3, [r3, #0]
- 8005094:	2b01      	cmp	r3, #1
- 8005096:	d102      	bne.n	800509e <pbuf_free_custom+0x22>
-  {
-    RxAllocStatus = RX_ALLOC_OK;
- 8005098:	4b04      	ldr	r3, [pc, #16]	; (80050ac <pbuf_free_custom+0x30>)
- 800509a:	2200      	movs	r2, #0
- 800509c:	701a      	strb	r2, [r3, #0]
-  }
-}
- 800509e:	bf00      	nop
- 80050a0:	3710      	adds	r7, #16
- 80050a2:	46bd      	mov	sp, r7
- 80050a4:	bd80      	pop	{r7, pc}
- 80050a6:	bf00      	nop
- 80050a8:	08014c90 	.word	0x08014c90
- 80050ac:	24004b04 	.word	0x24004b04
-
-080050b0 <sys_now>:
-*         when LWIP_TIMERS == 1 and NO_SYS == 1
-* @param  None
-* @retval Current Time value
-*/
-u32_t sys_now(void)
-{
- 80050b0:	b580      	push	{r7, lr}
- 80050b2:	af00      	add	r7, sp, #0
-  return HAL_GetTick();
- 80050b4:	f7fb ffaa 	bl	800100c <HAL_GetTick>
- 80050b8:	4603      	mov	r3, r0
-}
- 80050ba:	4618      	mov	r0, r3
- 80050bc:	bd80      	pop	{r7, pc}
-	...
-
-080050c0 <HAL_ETH_MspInit>:
-  * @param  ethHandle: ETH handle
-  * @retval None
-  */
-
-void HAL_ETH_MspInit(ETH_HandleTypeDef* ethHandle)
-{
- 80050c0:	b580      	push	{r7, lr}
- 80050c2:	b08e      	sub	sp, #56	; 0x38
- 80050c4:	af00      	add	r7, sp, #0
- 80050c6:	6078      	str	r0, [r7, #4]
-  GPIO_InitTypeDef GPIO_InitStruct = {0};
- 80050c8:	f107 0324 	add.w	r3, r7, #36	; 0x24
- 80050cc:	2200      	movs	r2, #0
- 80050ce:	601a      	str	r2, [r3, #0]
- 80050d0:	605a      	str	r2, [r3, #4]
- 80050d2:	609a      	str	r2, [r3, #8]
- 80050d4:	60da      	str	r2, [r3, #12]
- 80050d6:	611a      	str	r2, [r3, #16]
-  if(ethHandle->Instance==ETH)
- 80050d8:	687b      	ldr	r3, [r7, #4]
- 80050da:	681b      	ldr	r3, [r3, #0]
- 80050dc:	4a4d      	ldr	r2, [pc, #308]	; (8005214 <HAL_ETH_MspInit+0x154>)
- 80050de:	4293      	cmp	r3, r2
- 80050e0:	f040 8093 	bne.w	800520a <HAL_ETH_MspInit+0x14a>
-  {
-  /* USER CODE BEGIN ETH_MspInit 0 */
-
-  /* USER CODE END ETH_MspInit 0 */
-    /* Enable Peripheral clock */
-    __HAL_RCC_ETH1MAC_CLK_ENABLE();
- 80050e4:	4b4c      	ldr	r3, [pc, #304]	; (8005218 <HAL_ETH_MspInit+0x158>)
- 80050e6:	f8d3 30d8 	ldr.w	r3, [r3, #216]	; 0xd8
- 80050ea:	4a4b      	ldr	r2, [pc, #300]	; (8005218 <HAL_ETH_MspInit+0x158>)
- 80050ec:	f443 4300 	orr.w	r3, r3, #32768	; 0x8000
- 80050f0:	f8c2 30d8 	str.w	r3, [r2, #216]	; 0xd8
- 80050f4:	4b48      	ldr	r3, [pc, #288]	; (8005218 <HAL_ETH_MspInit+0x158>)
- 80050f6:	f8d3 30d8 	ldr.w	r3, [r3, #216]	; 0xd8
- 80050fa:	f403 4300 	and.w	r3, r3, #32768	; 0x8000
- 80050fe:	623b      	str	r3, [r7, #32]
- 8005100:	6a3b      	ldr	r3, [r7, #32]
-    __HAL_RCC_ETH1TX_CLK_ENABLE();
- 8005102:	4b45      	ldr	r3, [pc, #276]	; (8005218 <HAL_ETH_MspInit+0x158>)
- 8005104:	f8d3 30d8 	ldr.w	r3, [r3, #216]	; 0xd8
- 8005108:	4a43      	ldr	r2, [pc, #268]	; (8005218 <HAL_ETH_MspInit+0x158>)
- 800510a:	f443 3380 	orr.w	r3, r3, #65536	; 0x10000
- 800510e:	f8c2 30d8 	str.w	r3, [r2, #216]	; 0xd8
- 8005112:	4b41      	ldr	r3, [pc, #260]	; (8005218 <HAL_ETH_MspInit+0x158>)
- 8005114:	f8d3 30d8 	ldr.w	r3, [r3, #216]	; 0xd8
- 8005118:	f403 3380 	and.w	r3, r3, #65536	; 0x10000
- 800511c:	61fb      	str	r3, [r7, #28]
- 800511e:	69fb      	ldr	r3, [r7, #28]
-    __HAL_RCC_ETH1RX_CLK_ENABLE();
- 8005120:	4b3d      	ldr	r3, [pc, #244]	; (8005218 <HAL_ETH_MspInit+0x158>)
- 8005122:	f8d3 30d8 	ldr.w	r3, [r3, #216]	; 0xd8
- 8005126:	4a3c      	ldr	r2, [pc, #240]	; (8005218 <HAL_ETH_MspInit+0x158>)
- 8005128:	f443 3300 	orr.w	r3, r3, #131072	; 0x20000
- 800512c:	f8c2 30d8 	str.w	r3, [r2, #216]	; 0xd8
- 8005130:	4b39      	ldr	r3, [pc, #228]	; (8005218 <HAL_ETH_MspInit+0x158>)
- 8005132:	f8d3 30d8 	ldr.w	r3, [r3, #216]	; 0xd8
- 8005136:	f403 3300 	and.w	r3, r3, #131072	; 0x20000
- 800513a:	61bb      	str	r3, [r7, #24]
- 800513c:	69bb      	ldr	r3, [r7, #24]
-
-    __HAL_RCC_GPIOC_CLK_ENABLE();
- 800513e:	4b36      	ldr	r3, [pc, #216]	; (8005218 <HAL_ETH_MspInit+0x158>)
- 8005140:	f8d3 30e0 	ldr.w	r3, [r3, #224]	; 0xe0
- 8005144:	4a34      	ldr	r2, [pc, #208]	; (8005218 <HAL_ETH_MspInit+0x158>)
- 8005146:	f043 0304 	orr.w	r3, r3, #4
- 800514a:	f8c2 30e0 	str.w	r3, [r2, #224]	; 0xe0
- 800514e:	4b32      	ldr	r3, [pc, #200]	; (8005218 <HAL_ETH_MspInit+0x158>)
- 8005150:	f8d3 30e0 	ldr.w	r3, [r3, #224]	; 0xe0
- 8005154:	f003 0304 	and.w	r3, r3, #4
- 8005158:	617b      	str	r3, [r7, #20]
- 800515a:	697b      	ldr	r3, [r7, #20]
-    __HAL_RCC_GPIOA_CLK_ENABLE();
- 800515c:	4b2e      	ldr	r3, [pc, #184]	; (8005218 <HAL_ETH_MspInit+0x158>)
- 800515e:	f8d3 30e0 	ldr.w	r3, [r3, #224]	; 0xe0
- 8005162:	4a2d      	ldr	r2, [pc, #180]	; (8005218 <HAL_ETH_MspInit+0x158>)
- 8005164:	f043 0301 	orr.w	r3, r3, #1
- 8005168:	f8c2 30e0 	str.w	r3, [r2, #224]	; 0xe0
- 800516c:	4b2a      	ldr	r3, [pc, #168]	; (8005218 <HAL_ETH_MspInit+0x158>)
- 800516e:	f8d3 30e0 	ldr.w	r3, [r3, #224]	; 0xe0
- 8005172:	f003 0301 	and.w	r3, r3, #1
- 8005176:	613b      	str	r3, [r7, #16]
- 8005178:	693b      	ldr	r3, [r7, #16]
-    __HAL_RCC_GPIOB_CLK_ENABLE();
- 800517a:	4b27      	ldr	r3, [pc, #156]	; (8005218 <HAL_ETH_MspInit+0x158>)
- 800517c:	f8d3 30e0 	ldr.w	r3, [r3, #224]	; 0xe0
- 8005180:	4a25      	ldr	r2, [pc, #148]	; (8005218 <HAL_ETH_MspInit+0x158>)
- 8005182:	f043 0302 	orr.w	r3, r3, #2
- 8005186:	f8c2 30e0 	str.w	r3, [r2, #224]	; 0xe0
- 800518a:	4b23      	ldr	r3, [pc, #140]	; (8005218 <HAL_ETH_MspInit+0x158>)
- 800518c:	f8d3 30e0 	ldr.w	r3, [r3, #224]	; 0xe0
- 8005190:	f003 0302 	and.w	r3, r3, #2
- 8005194:	60fb      	str	r3, [r7, #12]
- 8005196:	68fb      	ldr	r3, [r7, #12]
-    PB13     ------> ETH_TXD1
-    PA7     ------> ETH_CRS_DV
-    PB11     ------> ETH_TX_EN
-    PB12     ------> ETH_TXD0
-    */
-    GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_4|GPIO_PIN_5;
- 8005198:	2332      	movs	r3, #50	; 0x32
- 800519a:	627b      	str	r3, [r7, #36]	; 0x24
-    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
- 800519c:	2302      	movs	r3, #2
- 800519e:	62bb      	str	r3, [r7, #40]	; 0x28
-    GPIO_InitStruct.Pull = GPIO_NOPULL;
- 80051a0:	2300      	movs	r3, #0
- 80051a2:	62fb      	str	r3, [r7, #44]	; 0x2c
-    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
- 80051a4:	2303      	movs	r3, #3
- 80051a6:	633b      	str	r3, [r7, #48]	; 0x30
-    GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
- 80051a8:	230b      	movs	r3, #11
- 80051aa:	637b      	str	r3, [r7, #52]	; 0x34
-    HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
- 80051ac:	f107 0324 	add.w	r3, r7, #36	; 0x24
- 80051b0:	4619      	mov	r1, r3
- 80051b2:	481a      	ldr	r0, [pc, #104]	; (800521c <HAL_ETH_MspInit+0x15c>)
- 80051b4:	f7fd fde2 	bl	8002d7c <HAL_GPIO_Init>
-
-    GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_7;
- 80051b8:	2386      	movs	r3, #134	; 0x86
- 80051ba:	627b      	str	r3, [r7, #36]	; 0x24
-    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
- 80051bc:	2302      	movs	r3, #2
- 80051be:	62bb      	str	r3, [r7, #40]	; 0x28
-    GPIO_InitStruct.Pull = GPIO_NOPULL;
- 80051c0:	2300      	movs	r3, #0
- 80051c2:	62fb      	str	r3, [r7, #44]	; 0x2c
-    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
- 80051c4:	2303      	movs	r3, #3
- 80051c6:	633b      	str	r3, [r7, #48]	; 0x30
-    GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
- 80051c8:	230b      	movs	r3, #11
- 80051ca:	637b      	str	r3, [r7, #52]	; 0x34
-    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
- 80051cc:	f107 0324 	add.w	r3, r7, #36	; 0x24
- 80051d0:	4619      	mov	r1, r3
- 80051d2:	4813      	ldr	r0, [pc, #76]	; (8005220 <HAL_ETH_MspInit+0x160>)
- 80051d4:	f7fd fdd2 	bl	8002d7c <HAL_GPIO_Init>
-
-    GPIO_InitStruct.Pin = GPIO_PIN_13|GPIO_PIN_11|GPIO_PIN_12;
- 80051d8:	f44f 5360 	mov.w	r3, #14336	; 0x3800
- 80051dc:	627b      	str	r3, [r7, #36]	; 0x24
-    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
- 80051de:	2302      	movs	r3, #2
- 80051e0:	62bb      	str	r3, [r7, #40]	; 0x28
-    GPIO_InitStruct.Pull = GPIO_NOPULL;
- 80051e2:	2300      	movs	r3, #0
- 80051e4:	62fb      	str	r3, [r7, #44]	; 0x2c
-    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
- 80051e6:	2303      	movs	r3, #3
- 80051e8:	633b      	str	r3, [r7, #48]	; 0x30
-    GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
- 80051ea:	230b      	movs	r3, #11
- 80051ec:	637b      	str	r3, [r7, #52]	; 0x34
-    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
- 80051ee:	f107 0324 	add.w	r3, r7, #36	; 0x24
- 80051f2:	4619      	mov	r1, r3
- 80051f4:	480b      	ldr	r0, [pc, #44]	; (8005224 <HAL_ETH_MspInit+0x164>)
- 80051f6:	f7fd fdc1 	bl	8002d7c <HAL_GPIO_Init>
-
-    /* Peripheral interrupt init */
-    HAL_NVIC_SetPriority(ETH_IRQn, 0, 0);
- 80051fa:	2200      	movs	r2, #0
- 80051fc:	2100      	movs	r1, #0
- 80051fe:	203d      	movs	r0, #61	; 0x3d
- 8005200:	f7fb ffff 	bl	8001202 <HAL_NVIC_SetPriority>
-    HAL_NVIC_EnableIRQ(ETH_IRQn);
- 8005204:	203d      	movs	r0, #61	; 0x3d
- 8005206:	f7fc f816 	bl	8001236 <HAL_NVIC_EnableIRQ>
-  /* USER CODE BEGIN ETH_MspInit 1 */
-
-  /* USER CODE END ETH_MspInit 1 */
-  }
-}
- 800520a:	bf00      	nop
- 800520c:	3738      	adds	r7, #56	; 0x38
- 800520e:	46bd      	mov	sp, r7
- 8005210:	bd80      	pop	{r7, pc}
- 8005212:	bf00      	nop
- 8005214:	40028000 	.word	0x40028000
- 8005218:	58024400 	.word	0x58024400
- 800521c:	58020800 	.word	0x58020800
- 8005220:	58020000 	.word	0x58020000
- 8005224:	58020400 	.word	0x58020400
-
-08005228 <ETH_PHY_IO_Init>:
-  * @brief  Initializes the MDIO interface GPIO and clocks.
-  * @param  None
-  * @retval 0 if OK, -1 if ERROR
-  */
-int32_t ETH_PHY_IO_Init(void)
-{
- 8005228:	b580      	push	{r7, lr}
- 800522a:	af00      	add	r7, sp, #0
-  /* We assume that MDIO GPIO configuration is already done
-     in the ETH_MspInit() else it should be done here
-  */
-
-  /* Configure the MDIO Clock */
-  HAL_ETH_SetMDIOClockRange(&heth);
- 800522c:	4802      	ldr	r0, [pc, #8]	; (8005238 <ETH_PHY_IO_Init+0x10>)
- 800522e:	f7fc ffd9 	bl	80021e4 <HAL_ETH_SetMDIOClockRange>
-
-  return 0;
- 8005232:	2300      	movs	r3, #0
-}
- 8005234:	4618      	mov	r0, r3
- 8005236:	bd80      	pop	{r7, pc}
- 8005238:	24004b08 	.word	0x24004b08
-
-0800523c <ETH_PHY_IO_DeInit>:
-  * @brief  De-Initializes the MDIO interface .
-  * @param  None
-  * @retval 0 if OK, -1 if ERROR
-  */
-int32_t ETH_PHY_IO_DeInit (void)
-{
- 800523c:	b480      	push	{r7}
- 800523e:	af00      	add	r7, sp, #0
-  return 0;
- 8005240:	2300      	movs	r3, #0
-}
- 8005242:	4618      	mov	r0, r3
- 8005244:	46bd      	mov	sp, r7
- 8005246:	f85d 7b04 	ldr.w	r7, [sp], #4
- 800524a:	4770      	bx	lr
-
-0800524c <ETH_PHY_IO_ReadReg>:
-  * @param  RegAddr: PHY register address
-  * @param  pRegVal: pointer to hold the register value
-  * @retval 0 if OK -1 if Error
-  */
-int32_t ETH_PHY_IO_ReadReg(uint32_t DevAddr, uint32_t RegAddr, uint32_t *pRegVal)
-{
- 800524c:	b580      	push	{r7, lr}
- 800524e:	b084      	sub	sp, #16
- 8005250:	af00      	add	r7, sp, #0
- 8005252:	60f8      	str	r0, [r7, #12]
- 8005254:	60b9      	str	r1, [r7, #8]
- 8005256:	607a      	str	r2, [r7, #4]
-  if(HAL_ETH_ReadPHYRegister(&heth, DevAddr, RegAddr, pRegVal) != HAL_OK)
- 8005258:	687b      	ldr	r3, [r7, #4]
- 800525a:	68ba      	ldr	r2, [r7, #8]
- 800525c:	68f9      	ldr	r1, [r7, #12]
- 800525e:	4807      	ldr	r0, [pc, #28]	; (800527c <ETH_PHY_IO_ReadReg+0x30>)
- 8005260:	f7fc fd2a 	bl	8001cb8 <HAL_ETH_ReadPHYRegister>
- 8005264:	4603      	mov	r3, r0
- 8005266:	2b00      	cmp	r3, #0
- 8005268:	d002      	beq.n	8005270 <ETH_PHY_IO_ReadReg+0x24>
-  {
-    return -1;
- 800526a:	f04f 33ff 	mov.w	r3, #4294967295
- 800526e:	e000      	b.n	8005272 <ETH_PHY_IO_ReadReg+0x26>
-  }
-
-  return 0;
- 8005270:	2300      	movs	r3, #0
-}
- 8005272:	4618      	mov	r0, r3
- 8005274:	3710      	adds	r7, #16
- 8005276:	46bd      	mov	sp, r7
- 8005278:	bd80      	pop	{r7, pc}
- 800527a:	bf00      	nop
- 800527c:	24004b08 	.word	0x24004b08
-
-08005280 <ETH_PHY_IO_WriteReg>:
-  * @param  RegAddr: PHY register address
-  * @param  RegVal: Value to be written
-  * @retval 0 if OK -1 if Error
-  */
-int32_t ETH_PHY_IO_WriteReg(uint32_t DevAddr, uint32_t RegAddr, uint32_t RegVal)
-{
- 8005280:	b580      	push	{r7, lr}
- 8005282:	b084      	sub	sp, #16
- 8005284:	af00      	add	r7, sp, #0
- 8005286:	60f8      	str	r0, [r7, #12]
- 8005288:	60b9      	str	r1, [r7, #8]
- 800528a:	607a      	str	r2, [r7, #4]
-  if(HAL_ETH_WritePHYRegister(&heth, DevAddr, RegAddr, RegVal) != HAL_OK)
- 800528c:	687b      	ldr	r3, [r7, #4]
- 800528e:	68ba      	ldr	r2, [r7, #8]
- 8005290:	68f9      	ldr	r1, [r7, #12]
- 8005292:	4807      	ldr	r0, [pc, #28]	; (80052b0 <ETH_PHY_IO_WriteReg+0x30>)
- 8005294:	f7fc fd64 	bl	8001d60 <HAL_ETH_WritePHYRegister>
- 8005298:	4603      	mov	r3, r0
- 800529a:	2b00      	cmp	r3, #0
- 800529c:	d002      	beq.n	80052a4 <ETH_PHY_IO_WriteReg+0x24>
-  {
-    return -1;
- 800529e:	f04f 33ff 	mov.w	r3, #4294967295
- 80052a2:	e000      	b.n	80052a6 <ETH_PHY_IO_WriteReg+0x26>
-  }
-
-  return 0;
- 80052a4:	2300      	movs	r3, #0
-}
- 80052a6:	4618      	mov	r0, r3
- 80052a8:	3710      	adds	r7, #16
- 80052aa:	46bd      	mov	sp, r7
- 80052ac:	bd80      	pop	{r7, pc}
- 80052ae:	bf00      	nop
- 80052b0:	24004b08 	.word	0x24004b08
-
-080052b4 <ETH_PHY_IO_GetTick>:
-/**
-  * @brief  Get the time in millisecons used for internal PHY driver process.
-  * @retval Time value
-  */
-int32_t ETH_PHY_IO_GetTick(void)
-{
- 80052b4:	b580      	push	{r7, lr}
- 80052b6:	af00      	add	r7, sp, #0
-  return HAL_GetTick();
- 80052b8:	f7fb fea8 	bl	800100c <HAL_GetTick>
- 80052bc:	4603      	mov	r3, r0
-}
- 80052be:	4618      	mov	r0, r3
- 80052c0:	bd80      	pop	{r7, pc}
-	...
-
-080052c4 <ethernet_link_check_state>:
-/**
-  * @brief  Check the ETH link state then update ETH driver and netif link accordingly.
-  * @retval None
-  */
-void ethernet_link_check_state(struct netif *netif)
-{
- 80052c4:	b580      	push	{r7, lr}
- 80052c6:	b0a0      	sub	sp, #128	; 0x80
- 80052c8:	af00      	add	r7, sp, #0
- 80052ca:	6078      	str	r0, [r7, #4]
-  ETH_MACConfigTypeDef MACConf = {0};
- 80052cc:	f107 030c 	add.w	r3, r7, #12
- 80052d0:	2264      	movs	r2, #100	; 0x64
- 80052d2:	2100      	movs	r1, #0
- 80052d4:	4618      	mov	r0, r3
- 80052d6:	f00b fdd5 	bl	8010e84 <memset>
-  int32_t PHYLinkState = 0;
- 80052da:	2300      	movs	r3, #0
- 80052dc:	673b      	str	r3, [r7, #112]	; 0x70
-  uint32_t linkchanged = 0U, speed = 0U, duplex = 0U;
- 80052de:	2300      	movs	r3, #0
- 80052e0:	67fb      	str	r3, [r7, #124]	; 0x7c
- 80052e2:	2300      	movs	r3, #0
- 80052e4:	67bb      	str	r3, [r7, #120]	; 0x78
- 80052e6:	2300      	movs	r3, #0
- 80052e8:	677b      	str	r3, [r7, #116]	; 0x74
-
-  PHYLinkState = LAN8742_GetLinkState(&LAN8742);
- 80052ea:	483a      	ldr	r0, [pc, #232]	; (80053d4 <ethernet_link_check_state+0x110>)
- 80052ec:	f7fb fd81 	bl	8000df2 <LAN8742_GetLinkState>
- 80052f0:	6738      	str	r0, [r7, #112]	; 0x70
-
-  if(netif_is_link_up(netif) && (PHYLinkState <= LAN8742_STATUS_LINK_DOWN))
- 80052f2:	687b      	ldr	r3, [r7, #4]
- 80052f4:	f893 302d 	ldrb.w	r3, [r3, #45]	; 0x2d
- 80052f8:	089b      	lsrs	r3, r3, #2
- 80052fa:	f003 0301 	and.w	r3, r3, #1
- 80052fe:	b2db      	uxtb	r3, r3
- 8005300:	2b00      	cmp	r3, #0
- 8005302:	d00c      	beq.n	800531e <ethernet_link_check_state+0x5a>
- 8005304:	6f3b      	ldr	r3, [r7, #112]	; 0x70
- 8005306:	2b01      	cmp	r3, #1
- 8005308:	dc09      	bgt.n	800531e <ethernet_link_check_state+0x5a>
-  {
-    HAL_ETH_Stop(&heth);
- 800530a:	4833      	ldr	r0, [pc, #204]	; (80053d8 <ethernet_link_check_state+0x114>)
- 800530c:	f7fc f972 	bl	80015f4 <HAL_ETH_Stop>
-    netif_set_down(netif);
- 8005310:	6878      	ldr	r0, [r7, #4]
- 8005312:	f001 fa49 	bl	80067a8 <netif_set_down>
-    netif_set_link_down(netif);
- 8005316:	6878      	ldr	r0, [r7, #4]
- 8005318:	f001 faac 	bl	8006874 <netif_set_link_down>
-      netif_set_up(netif);
-      netif_set_link_up(netif);
-    }
-  }
-
-}
- 800531c:	e055      	b.n	80053ca <ethernet_link_check_state+0x106>
-  else if(!netif_is_link_up(netif) && (PHYLinkState > LAN8742_STATUS_LINK_DOWN))
- 800531e:	687b      	ldr	r3, [r7, #4]
- 8005320:	f893 302d 	ldrb.w	r3, [r3, #45]	; 0x2d
- 8005324:	f003 0304 	and.w	r3, r3, #4
- 8005328:	2b00      	cmp	r3, #0
- 800532a:	d14e      	bne.n	80053ca <ethernet_link_check_state+0x106>
- 800532c:	6f3b      	ldr	r3, [r7, #112]	; 0x70
- 800532e:	2b01      	cmp	r3, #1
- 8005330:	dd4b      	ble.n	80053ca <ethernet_link_check_state+0x106>
-    switch (PHYLinkState)
- 8005332:	6f3b      	ldr	r3, [r7, #112]	; 0x70
- 8005334:	3b02      	subs	r3, #2
- 8005336:	2b03      	cmp	r3, #3
- 8005338:	d82a      	bhi.n	8005390 <ethernet_link_check_state+0xcc>
- 800533a:	a201      	add	r2, pc, #4	; (adr r2, 8005340 <ethernet_link_check_state+0x7c>)
- 800533c:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
- 8005340:	08005351 	.word	0x08005351
- 8005344:	08005363 	.word	0x08005363
- 8005348:	08005373 	.word	0x08005373
- 800534c:	08005383 	.word	0x08005383
-      duplex = ETH_FULLDUPLEX_MODE;
- 8005350:	f44f 5300 	mov.w	r3, #8192	; 0x2000
- 8005354:	677b      	str	r3, [r7, #116]	; 0x74
-      speed = ETH_SPEED_100M;
- 8005356:	f44f 4380 	mov.w	r3, #16384	; 0x4000
- 800535a:	67bb      	str	r3, [r7, #120]	; 0x78
-      linkchanged = 1;
- 800535c:	2301      	movs	r3, #1
- 800535e:	67fb      	str	r3, [r7, #124]	; 0x7c
-      break;
- 8005360:	e017      	b.n	8005392 <ethernet_link_check_state+0xce>
-      duplex = ETH_HALFDUPLEX_MODE;
- 8005362:	2300      	movs	r3, #0
- 8005364:	677b      	str	r3, [r7, #116]	; 0x74
-      speed = ETH_SPEED_100M;
- 8005366:	f44f 4380 	mov.w	r3, #16384	; 0x4000
- 800536a:	67bb      	str	r3, [r7, #120]	; 0x78
-      linkchanged = 1;
- 800536c:	2301      	movs	r3, #1
- 800536e:	67fb      	str	r3, [r7, #124]	; 0x7c
-      break;
- 8005370:	e00f      	b.n	8005392 <ethernet_link_check_state+0xce>
-      duplex = ETH_FULLDUPLEX_MODE;
- 8005372:	f44f 5300 	mov.w	r3, #8192	; 0x2000
- 8005376:	677b      	str	r3, [r7, #116]	; 0x74
-      speed = ETH_SPEED_10M;
- 8005378:	2300      	movs	r3, #0
- 800537a:	67bb      	str	r3, [r7, #120]	; 0x78
-      linkchanged = 1;
- 800537c:	2301      	movs	r3, #1
- 800537e:	67fb      	str	r3, [r7, #124]	; 0x7c
-      break;
- 8005380:	e007      	b.n	8005392 <ethernet_link_check_state+0xce>
-      duplex = ETH_HALFDUPLEX_MODE;
- 8005382:	2300      	movs	r3, #0
- 8005384:	677b      	str	r3, [r7, #116]	; 0x74
-      speed = ETH_SPEED_10M;
- 8005386:	2300      	movs	r3, #0
- 8005388:	67bb      	str	r3, [r7, #120]	; 0x78
-      linkchanged = 1;
- 800538a:	2301      	movs	r3, #1
- 800538c:	67fb      	str	r3, [r7, #124]	; 0x7c
-      break;
- 800538e:	e000      	b.n	8005392 <ethernet_link_check_state+0xce>
-      break;
- 8005390:	bf00      	nop
-    if(linkchanged)
- 8005392:	6ffb      	ldr	r3, [r7, #124]	; 0x7c
- 8005394:	2b00      	cmp	r3, #0
- 8005396:	d018      	beq.n	80053ca <ethernet_link_check_state+0x106>
-      HAL_ETH_GetMACConfig(&heth, &MACConf);
- 8005398:	f107 030c 	add.w	r3, r7, #12
- 800539c:	4619      	mov	r1, r3
- 800539e:	480e      	ldr	r0, [pc, #56]	; (80053d8 <ethernet_link_check_state+0x114>)
- 80053a0:	f7fc fd32 	bl	8001e08 <HAL_ETH_GetMACConfig>
-      MACConf.DuplexMode = duplex;
- 80053a4:	6f7b      	ldr	r3, [r7, #116]	; 0x74
- 80053a6:	627b      	str	r3, [r7, #36]	; 0x24
-      MACConf.Speed = speed;
- 80053a8:	6fbb      	ldr	r3, [r7, #120]	; 0x78
- 80053aa:	623b      	str	r3, [r7, #32]
-      HAL_ETH_SetMACConfig(&heth, &MACConf);
- 80053ac:	f107 030c 	add.w	r3, r7, #12
- 80053b0:	4619      	mov	r1, r3
- 80053b2:	4809      	ldr	r0, [pc, #36]	; (80053d8 <ethernet_link_check_state+0x114>)
- 80053b4:	f7fc fefc 	bl	80021b0 <HAL_ETH_SetMACConfig>
-      HAL_ETH_Start(&heth);
- 80053b8:	4807      	ldr	r0, [pc, #28]	; (80053d8 <ethernet_link_check_state+0x114>)
- 80053ba:	f7fc f8b9 	bl	8001530 <HAL_ETH_Start>
-      netif_set_up(netif);
- 80053be:	6878      	ldr	r0, [r7, #4]
- 80053c0:	f001 f986 	bl	80066d0 <netif_set_up>
-      netif_set_link_up(netif);
- 80053c4:	6878      	ldr	r0, [r7, #4]
- 80053c6:	f001 fa21 	bl	800680c <netif_set_link_up>
-}
- 80053ca:	bf00      	nop
- 80053cc:	3780      	adds	r7, #128	; 0x80
- 80053ce:	46bd      	mov	sp, r7
- 80053d0:	bd80      	pop	{r7, pc}
- 80053d2:	bf00      	nop
- 80053d4:	24004bf0 	.word	0x24004bf0
- 80053d8:	24004b08 	.word	0x24004b08
-
-080053dc <HAL_ETH_RxAllocateCallback>:
-
-void HAL_ETH_RxAllocateCallback(uint8_t **buff)
-{
- 80053dc:	b580      	push	{r7, lr}
- 80053de:	b086      	sub	sp, #24
- 80053e0:	af02      	add	r7, sp, #8
- 80053e2:	6078      	str	r0, [r7, #4]
-/* USER CODE BEGIN HAL ETH RxAllocateCallback */
-  struct pbuf_custom *p = LWIP_MEMPOOL_ALLOC(RX_POOL);
- 80053e4:	4812      	ldr	r0, [pc, #72]	; (8005430 <HAL_ETH_RxAllocateCallback+0x54>)
- 80053e6:	f000 fdf7 	bl	8005fd8 <memp_malloc_pool>
- 80053ea:	60f8      	str	r0, [r7, #12]
-  if (p)
- 80053ec:	68fb      	ldr	r3, [r7, #12]
- 80053ee:	2b00      	cmp	r3, #0
- 80053f0:	d014      	beq.n	800541c <HAL_ETH_RxAllocateCallback+0x40>
-  {
-    /* Get the buff from the struct pbuf address. */
-    *buff = (uint8_t *)p + offsetof(RxBuff_t, buff);
- 80053f2:	68fb      	ldr	r3, [r7, #12]
- 80053f4:	f103 0220 	add.w	r2, r3, #32
- 80053f8:	687b      	ldr	r3, [r7, #4]
- 80053fa:	601a      	str	r2, [r3, #0]
-    p->custom_free_function = pbuf_free_custom;
- 80053fc:	68fb      	ldr	r3, [r7, #12]
- 80053fe:	4a0d      	ldr	r2, [pc, #52]	; (8005434 <HAL_ETH_RxAllocateCallback+0x58>)
- 8005400:	611a      	str	r2, [r3, #16]
-    /* Initialize the struct pbuf.
-    * This must be performed whenever a buffer's allocated because it may be
-    * changed by lwIP or the app, e.g., pbuf_free decrements ref. */
-    pbuf_alloced_custom(PBUF_RAW, 0, PBUF_REF, p, *buff, ETH_RX_BUFFER_SIZE);
- 8005402:	687b      	ldr	r3, [r7, #4]
- 8005404:	681b      	ldr	r3, [r3, #0]
- 8005406:	f44f 62c0 	mov.w	r2, #1536	; 0x600
- 800540a:	9201      	str	r2, [sp, #4]
- 800540c:	9300      	str	r3, [sp, #0]
- 800540e:	68fb      	ldr	r3, [r7, #12]
- 8005410:	2241      	movs	r2, #65	; 0x41
- 8005412:	2100      	movs	r1, #0
- 8005414:	2000      	movs	r0, #0
- 8005416:	f001 fc23 	bl	8006c60 <pbuf_alloced_custom>
-  {
-    RxAllocStatus = RX_ALLOC_ERROR;
-    *buff = NULL;
-  }
-/* USER CODE END HAL ETH RxAllocateCallback */
-}
- 800541a:	e005      	b.n	8005428 <HAL_ETH_RxAllocateCallback+0x4c>
-    RxAllocStatus = RX_ALLOC_ERROR;
- 800541c:	4b06      	ldr	r3, [pc, #24]	; (8005438 <HAL_ETH_RxAllocateCallback+0x5c>)
- 800541e:	2201      	movs	r2, #1
- 8005420:	701a      	strb	r2, [r3, #0]
-    *buff = NULL;
- 8005422:	687b      	ldr	r3, [r7, #4]
- 8005424:	2200      	movs	r2, #0
- 8005426:	601a      	str	r2, [r3, #0]
-}
- 8005428:	bf00      	nop
- 800542a:	3710      	adds	r7, #16
- 800542c:	46bd      	mov	sp, r7
- 800542e:	bd80      	pop	{r7, pc}
- 8005430:	08014c90 	.word	0x08014c90
- 8005434:	0800507d 	.word	0x0800507d
- 8005438:	24004b04 	.word	0x24004b04
-
-0800543c <HAL_ETH_RxLinkCallback>:
-
-void HAL_ETH_RxLinkCallback(void **pStart, void **pEnd, uint8_t *buff, uint16_t Length)
-{
- 800543c:	b480      	push	{r7}
- 800543e:	b08d      	sub	sp, #52	; 0x34
- 8005440:	af00      	add	r7, sp, #0
- 8005442:	60f8      	str	r0, [r7, #12]
- 8005444:	60b9      	str	r1, [r7, #8]
- 8005446:	607a      	str	r2, [r7, #4]
- 8005448:	807b      	strh	r3, [r7, #2]
-/* USER CODE BEGIN HAL ETH RxLinkCallback */
-
-  struct pbuf **ppStart = (struct pbuf **)pStart;
- 800544a:	68fb      	ldr	r3, [r7, #12]
- 800544c:	62bb      	str	r3, [r7, #40]	; 0x28
-  struct pbuf **ppEnd = (struct pbuf **)pEnd;
- 800544e:	68bb      	ldr	r3, [r7, #8]
- 8005450:	627b      	str	r3, [r7, #36]	; 0x24
-  struct pbuf *p = NULL;
- 8005452:	2300      	movs	r3, #0
- 8005454:	62fb      	str	r3, [r7, #44]	; 0x2c
-
-  /* Get the struct pbuf from the buff address. */
-  p = (struct pbuf *)(buff - offsetof(RxBuff_t, buff));
- 8005456:	687b      	ldr	r3, [r7, #4]
- 8005458:	3b20      	subs	r3, #32
- 800545a:	62fb      	str	r3, [r7, #44]	; 0x2c
-  p->next = NULL;
- 800545c:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 800545e:	2200      	movs	r2, #0
- 8005460:	601a      	str	r2, [r3, #0]
-  p->tot_len = 0;
- 8005462:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 8005464:	2200      	movs	r2, #0
- 8005466:	811a      	strh	r2, [r3, #8]
-  p->len = Length;
- 8005468:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 800546a:	887a      	ldrh	r2, [r7, #2]
- 800546c:	815a      	strh	r2, [r3, #10]
-
-  /* Chain the buffer. */
-  if (!*ppStart)
- 800546e:	6abb      	ldr	r3, [r7, #40]	; 0x28
- 8005470:	681b      	ldr	r3, [r3, #0]
- 8005472:	2b00      	cmp	r3, #0
- 8005474:	d103      	bne.n	800547e <HAL_ETH_RxLinkCallback+0x42>
-  {
-    /* The first buffer of the packet. */
-    *ppStart = p;
- 8005476:	6abb      	ldr	r3, [r7, #40]	; 0x28
- 8005478:	6afa      	ldr	r2, [r7, #44]	; 0x2c
- 800547a:	601a      	str	r2, [r3, #0]
- 800547c:	e003      	b.n	8005486 <HAL_ETH_RxLinkCallback+0x4a>
-  }
-  else
-  {
-    /* Chain the buffer to the end of the packet. */
-    (*ppEnd)->next = p;
- 800547e:	6a7b      	ldr	r3, [r7, #36]	; 0x24
- 8005480:	681b      	ldr	r3, [r3, #0]
- 8005482:	6afa      	ldr	r2, [r7, #44]	; 0x2c
- 8005484:	601a      	str	r2, [r3, #0]
-  }
-  *ppEnd  = p;
- 8005486:	6a7b      	ldr	r3, [r7, #36]	; 0x24
- 8005488:	6afa      	ldr	r2, [r7, #44]	; 0x2c
- 800548a:	601a      	str	r2, [r3, #0]
-
-  /* Update the total length of all the buffers of the chain. Each pbuf in the chain should have its tot_len
-   * set to its own length, plus the length of all the following pbufs in the chain. */
-  for (p = *ppStart; p != NULL; p = p->next)
- 800548c:	6abb      	ldr	r3, [r7, #40]	; 0x28
- 800548e:	681b      	ldr	r3, [r3, #0]
- 8005490:	62fb      	str	r3, [r7, #44]	; 0x2c
- 8005492:	e009      	b.n	80054a8 <HAL_ETH_RxLinkCallback+0x6c>
-  {
-    p->tot_len += Length;
- 8005494:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 8005496:	891a      	ldrh	r2, [r3, #8]
- 8005498:	887b      	ldrh	r3, [r7, #2]
- 800549a:	4413      	add	r3, r2
- 800549c:	b29a      	uxth	r2, r3
- 800549e:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 80054a0:	811a      	strh	r2, [r3, #8]
-  for (p = *ppStart; p != NULL; p = p->next)
- 80054a2:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 80054a4:	681b      	ldr	r3, [r3, #0]
- 80054a6:	62fb      	str	r3, [r7, #44]	; 0x2c
- 80054a8:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 80054aa:	2b00      	cmp	r3, #0
- 80054ac:	d1f2      	bne.n	8005494 <HAL_ETH_RxLinkCallback+0x58>
-  }
-
-  /* Invalidate data cache because Rx DMA's writing to physical memory makes it stale. */
-  SCB_InvalidateDCache_by_Addr((uint32_t *)buff, Length);
- 80054ae:	887b      	ldrh	r3, [r7, #2]
- 80054b0:	687a      	ldr	r2, [r7, #4]
- 80054b2:	623a      	str	r2, [r7, #32]
- 80054b4:	61fb      	str	r3, [r7, #28]
-    if ( dsize > 0 ) { 
- 80054b6:	69fb      	ldr	r3, [r7, #28]
- 80054b8:	2b00      	cmp	r3, #0
- 80054ba:	dd1d      	ble.n	80054f8 <HAL_ETH_RxLinkCallback+0xbc>
-       int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
- 80054bc:	6a3b      	ldr	r3, [r7, #32]
- 80054be:	f003 021f 	and.w	r2, r3, #31
- 80054c2:	69fb      	ldr	r3, [r7, #28]
- 80054c4:	4413      	add	r3, r2
- 80054c6:	61bb      	str	r3, [r7, #24]
-      uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
- 80054c8:	6a3b      	ldr	r3, [r7, #32]
- 80054ca:	617b      	str	r3, [r7, #20]
-  __ASM volatile ("dsb 0xF":::"memory");
- 80054cc:	f3bf 8f4f 	dsb	sy
-}
- 80054d0:	bf00      	nop
-        SCB->DCIMVAC = op_addr;             /* register accepts only 32byte aligned values, only bits 31..5 are valid */
- 80054d2:	4a0d      	ldr	r2, [pc, #52]	; (8005508 <HAL_ETH_RxLinkCallback+0xcc>)
- 80054d4:	697b      	ldr	r3, [r7, #20]
- 80054d6:	f8c2 325c 	str.w	r3, [r2, #604]	; 0x25c
-        op_addr += __SCB_DCACHE_LINE_SIZE;
- 80054da:	697b      	ldr	r3, [r7, #20]
- 80054dc:	3320      	adds	r3, #32
- 80054de:	617b      	str	r3, [r7, #20]
-        op_size -= __SCB_DCACHE_LINE_SIZE;
- 80054e0:	69bb      	ldr	r3, [r7, #24]
- 80054e2:	3b20      	subs	r3, #32
- 80054e4:	61bb      	str	r3, [r7, #24]
-      } while ( op_size > 0 );
- 80054e6:	69bb      	ldr	r3, [r7, #24]
- 80054e8:	2b00      	cmp	r3, #0
- 80054ea:	dcf2      	bgt.n	80054d2 <HAL_ETH_RxLinkCallback+0x96>
-  __ASM volatile ("dsb 0xF":::"memory");
- 80054ec:	f3bf 8f4f 	dsb	sy
-}
- 80054f0:	bf00      	nop
-  __ASM volatile ("isb 0xF":::"memory");
- 80054f2:	f3bf 8f6f 	isb	sy
-}
- 80054f6:	bf00      	nop
-}
- 80054f8:	bf00      	nop
-
-/* USER CODE END HAL ETH RxLinkCallback */
-}
- 80054fa:	bf00      	nop
- 80054fc:	3734      	adds	r7, #52	; 0x34
- 80054fe:	46bd      	mov	sp, r7
- 8005500:	f85d 7b04 	ldr.w	r7, [sp], #4
- 8005504:	4770      	bx	lr
- 8005506:	bf00      	nop
- 8005508:	e000ed00 	.word	0xe000ed00
-
-0800550c <lwip_strerr>:
- * @param err an lwip internal err_t
- * @return a string representation for err
- */
-const char *
-lwip_strerr(err_t err)
-{
- 800550c:	b480      	push	{r7}
- 800550e:	b083      	sub	sp, #12
- 8005510:	af00      	add	r7, sp, #0
- 8005512:	4603      	mov	r3, r0
- 8005514:	71fb      	strb	r3, [r7, #7]
-  if ((err > 0) || (-err >= (err_t)LWIP_ARRAYSIZE(err_strerr))) {
- 8005516:	f997 3007 	ldrsb.w	r3, [r7, #7]
- 800551a:	2b00      	cmp	r3, #0
- 800551c:	dc04      	bgt.n	8005528 <lwip_strerr+0x1c>
- 800551e:	f997 3007 	ldrsb.w	r3, [r7, #7]
- 8005522:	f113 0f10 	cmn.w	r3, #16
- 8005526:	da01      	bge.n	800552c <lwip_strerr+0x20>
-    return "Unknown error.";
- 8005528:	4b06      	ldr	r3, [pc, #24]	; (8005544 <lwip_strerr+0x38>)
- 800552a:	e005      	b.n	8005538 <lwip_strerr+0x2c>
-  }
-  return err_strerr[-err];
- 800552c:	f997 3007 	ldrsb.w	r3, [r7, #7]
- 8005530:	425b      	negs	r3, r3
- 8005532:	4a05      	ldr	r2, [pc, #20]	; (8005548 <lwip_strerr+0x3c>)
- 8005534:	f852 3023 	ldr.w	r3, [r2, r3, lsl #2]
-}
- 8005538:	4618      	mov	r0, r3
- 800553a:	370c      	adds	r7, #12
- 800553c:	46bd      	mov	sp, r7
- 800553e:	f85d 7b04 	ldr.w	r7, [sp], #4
- 8005542:	4770      	bx	lr
- 8005544:	08011c90 	.word	0x08011c90
- 8005548:	24000024 	.word	0x24000024
-
-0800554c <lwip_htons>:
- * @param n u16_t in host byte order
- * @return n in network byte order
- */
-u16_t
-lwip_htons(u16_t n)
-{
- 800554c:	b480      	push	{r7}
- 800554e:	b083      	sub	sp, #12
- 8005550:	af00      	add	r7, sp, #0
- 8005552:	4603      	mov	r3, r0
- 8005554:	80fb      	strh	r3, [r7, #6]
-  return PP_HTONS(n);
- 8005556:	88fb      	ldrh	r3, [r7, #6]
- 8005558:	021b      	lsls	r3, r3, #8
- 800555a:	b21a      	sxth	r2, r3
- 800555c:	88fb      	ldrh	r3, [r7, #6]
- 800555e:	0a1b      	lsrs	r3, r3, #8
- 8005560:	b29b      	uxth	r3, r3
- 8005562:	b21b      	sxth	r3, r3
- 8005564:	4313      	orrs	r3, r2
- 8005566:	b21b      	sxth	r3, r3
- 8005568:	b29b      	uxth	r3, r3
-}
- 800556a:	4618      	mov	r0, r3
- 800556c:	370c      	adds	r7, #12
- 800556e:	46bd      	mov	sp, r7
- 8005570:	f85d 7b04 	ldr.w	r7, [sp], #4
- 8005574:	4770      	bx	lr
-
-08005576 <lwip_htonl>:
- * @param n u32_t in host byte order
- * @return n in network byte order
- */
-u32_t
-lwip_htonl(u32_t n)
-{
- 8005576:	b480      	push	{r7}
- 8005578:	b083      	sub	sp, #12
- 800557a:	af00      	add	r7, sp, #0
- 800557c:	6078      	str	r0, [r7, #4]
-  return PP_HTONL(n);
- 800557e:	687b      	ldr	r3, [r7, #4]
- 8005580:	061a      	lsls	r2, r3, #24
- 8005582:	687b      	ldr	r3, [r7, #4]
- 8005584:	021b      	lsls	r3, r3, #8
- 8005586:	f403 037f 	and.w	r3, r3, #16711680	; 0xff0000
- 800558a:	431a      	orrs	r2, r3
- 800558c:	687b      	ldr	r3, [r7, #4]
- 800558e:	0a1b      	lsrs	r3, r3, #8
- 8005590:	f403 437f 	and.w	r3, r3, #65280	; 0xff00
- 8005594:	431a      	orrs	r2, r3
- 8005596:	687b      	ldr	r3, [r7, #4]
- 8005598:	0e1b      	lsrs	r3, r3, #24
- 800559a:	4313      	orrs	r3, r2
-}
- 800559c:	4618      	mov	r0, r3
- 800559e:	370c      	adds	r7, #12
- 80055a0:	46bd      	mov	sp, r7
- 80055a2:	f85d 7b04 	ldr.w	r7, [sp], #4
- 80055a6:	4770      	bx	lr
-
-080055a8 <lwip_standard_chksum>:
- * @param len length of data to be summed
- * @return host order (!) lwip checksum (non-inverted Internet sum)
- */
-u16_t
-lwip_standard_chksum(const void *dataptr, int len)
-{
- 80055a8:	b480      	push	{r7}
- 80055aa:	b089      	sub	sp, #36	; 0x24
- 80055ac:	af00      	add	r7, sp, #0
- 80055ae:	6078      	str	r0, [r7, #4]
- 80055b0:	6039      	str	r1, [r7, #0]
-  const u8_t *pb = (const u8_t *)dataptr;
- 80055b2:	687b      	ldr	r3, [r7, #4]
- 80055b4:	61fb      	str	r3, [r7, #28]
-  const u16_t *ps;
-  u16_t t = 0;
- 80055b6:	2300      	movs	r3, #0
- 80055b8:	81fb      	strh	r3, [r7, #14]
-  u32_t sum = 0;
- 80055ba:	2300      	movs	r3, #0
- 80055bc:	617b      	str	r3, [r7, #20]
-  int odd = ((mem_ptr_t)pb & 1);
- 80055be:	69fb      	ldr	r3, [r7, #28]
- 80055c0:	f003 0301 	and.w	r3, r3, #1
- 80055c4:	613b      	str	r3, [r7, #16]
-
-  /* Get aligned to u16_t */
-  if (odd && len > 0) {
- 80055c6:	693b      	ldr	r3, [r7, #16]
- 80055c8:	2b00      	cmp	r3, #0
- 80055ca:	d00d      	beq.n	80055e8 <lwip_standard_chksum+0x40>
- 80055cc:	683b      	ldr	r3, [r7, #0]
- 80055ce:	2b00      	cmp	r3, #0
- 80055d0:	dd0a      	ble.n	80055e8 <lwip_standard_chksum+0x40>
-    ((u8_t *)&t)[1] = *pb++;
- 80055d2:	69fa      	ldr	r2, [r7, #28]
- 80055d4:	1c53      	adds	r3, r2, #1
- 80055d6:	61fb      	str	r3, [r7, #28]
- 80055d8:	f107 030e 	add.w	r3, r7, #14
- 80055dc:	3301      	adds	r3, #1
- 80055de:	7812      	ldrb	r2, [r2, #0]
- 80055e0:	701a      	strb	r2, [r3, #0]
-    len--;
- 80055e2:	683b      	ldr	r3, [r7, #0]
- 80055e4:	3b01      	subs	r3, #1
- 80055e6:	603b      	str	r3, [r7, #0]
-  }
-
-  /* Add the bulk of the data */
-  ps = (const u16_t *)(const void *)pb;
- 80055e8:	69fb      	ldr	r3, [r7, #28]
- 80055ea:	61bb      	str	r3, [r7, #24]
-  while (len > 1) {
- 80055ec:	e00a      	b.n	8005604 <lwip_standard_chksum+0x5c>
-    sum += *ps++;
- 80055ee:	69bb      	ldr	r3, [r7, #24]
- 80055f0:	1c9a      	adds	r2, r3, #2
- 80055f2:	61ba      	str	r2, [r7, #24]
- 80055f4:	881b      	ldrh	r3, [r3, #0]
- 80055f6:	461a      	mov	r2, r3
- 80055f8:	697b      	ldr	r3, [r7, #20]
- 80055fa:	4413      	add	r3, r2
- 80055fc:	617b      	str	r3, [r7, #20]
-    len -= 2;
- 80055fe:	683b      	ldr	r3, [r7, #0]
- 8005600:	3b02      	subs	r3, #2
- 8005602:	603b      	str	r3, [r7, #0]
-  while (len > 1) {
- 8005604:	683b      	ldr	r3, [r7, #0]
- 8005606:	2b01      	cmp	r3, #1
- 8005608:	dcf1      	bgt.n	80055ee <lwip_standard_chksum+0x46>
-  }
-
-  /* Consume left-over byte, if any */
-  if (len > 0) {
- 800560a:	683b      	ldr	r3, [r7, #0]
- 800560c:	2b00      	cmp	r3, #0
- 800560e:	dd04      	ble.n	800561a <lwip_standard_chksum+0x72>
-    ((u8_t *)&t)[0] = *(const u8_t *)ps;
- 8005610:	f107 030e 	add.w	r3, r7, #14
- 8005614:	69ba      	ldr	r2, [r7, #24]
- 8005616:	7812      	ldrb	r2, [r2, #0]
- 8005618:	701a      	strb	r2, [r3, #0]
-  }
-
-  /* Add end bytes */
-  sum += t;
- 800561a:	89fb      	ldrh	r3, [r7, #14]
- 800561c:	461a      	mov	r2, r3
- 800561e:	697b      	ldr	r3, [r7, #20]
- 8005620:	4413      	add	r3, r2
- 8005622:	617b      	str	r3, [r7, #20]
-
-  /* Fold 32-bit sum to 16 bits
-     calling this twice is probably faster than if statements... */
-  sum = FOLD_U32T(sum);
- 8005624:	697b      	ldr	r3, [r7, #20]
- 8005626:	0c1a      	lsrs	r2, r3, #16
- 8005628:	697b      	ldr	r3, [r7, #20]
- 800562a:	b29b      	uxth	r3, r3
- 800562c:	4413      	add	r3, r2
- 800562e:	617b      	str	r3, [r7, #20]
-  sum = FOLD_U32T(sum);
- 8005630:	697b      	ldr	r3, [r7, #20]
- 8005632:	0c1a      	lsrs	r2, r3, #16
- 8005634:	697b      	ldr	r3, [r7, #20]
- 8005636:	b29b      	uxth	r3, r3
- 8005638:	4413      	add	r3, r2
- 800563a:	617b      	str	r3, [r7, #20]
-
-  /* Swap if alignment was odd */
-  if (odd) {
- 800563c:	693b      	ldr	r3, [r7, #16]
- 800563e:	2b00      	cmp	r3, #0
- 8005640:	d007      	beq.n	8005652 <lwip_standard_chksum+0xaa>
-    sum = SWAP_BYTES_IN_WORD(sum);
- 8005642:	697b      	ldr	r3, [r7, #20]
- 8005644:	021b      	lsls	r3, r3, #8
- 8005646:	b29a      	uxth	r2, r3
- 8005648:	697b      	ldr	r3, [r7, #20]
- 800564a:	0a1b      	lsrs	r3, r3, #8
- 800564c:	b2db      	uxtb	r3, r3
- 800564e:	4313      	orrs	r3, r2
- 8005650:	617b      	str	r3, [r7, #20]
-  }
-
-  return (u16_t)sum;
- 8005652:	697b      	ldr	r3, [r7, #20]
- 8005654:	b29b      	uxth	r3, r3
-}
- 8005656:	4618      	mov	r0, r3
- 8005658:	3724      	adds	r7, #36	; 0x24
- 800565a:	46bd      	mov	sp, r7
- 800565c:	f85d 7b04 	ldr.w	r7, [sp], #4
- 8005660:	4770      	bx	lr
-
-08005662 <inet_chksum>:
- * @return checksum (as u16_t) to be saved directly in the protocol header
- */
-
-u16_t
-inet_chksum(const void *dataptr, u16_t len)
-{
- 8005662:	b580      	push	{r7, lr}
- 8005664:	b082      	sub	sp, #8
- 8005666:	af00      	add	r7, sp, #0
- 8005668:	6078      	str	r0, [r7, #4]
- 800566a:	460b      	mov	r3, r1
- 800566c:	807b      	strh	r3, [r7, #2]
-  return (u16_t)~(unsigned int)LWIP_CHKSUM(dataptr, len);
- 800566e:	887b      	ldrh	r3, [r7, #2]
- 8005670:	4619      	mov	r1, r3
- 8005672:	6878      	ldr	r0, [r7, #4]
- 8005674:	f7ff ff98 	bl	80055a8 <lwip_standard_chksum>
- 8005678:	4603      	mov	r3, r0
- 800567a:	43db      	mvns	r3, r3
- 800567c:	b29b      	uxth	r3, r3
-}
- 800567e:	4618      	mov	r0, r3
- 8005680:	3708      	adds	r7, #8
- 8005682:	46bd      	mov	sp, r7
- 8005684:	bd80      	pop	{r7, pc}
-
-08005686 <inet_chksum_pbuf>:
- * @param p pbuf chain over that the checksum should be calculated
- * @return checksum (as u16_t) to be saved directly in the protocol header
- */
-u16_t
-inet_chksum_pbuf(struct pbuf *p)
-{
- 8005686:	b580      	push	{r7, lr}
- 8005688:	b086      	sub	sp, #24
- 800568a:	af00      	add	r7, sp, #0
- 800568c:	6078      	str	r0, [r7, #4]
-  u32_t acc;
-  struct pbuf *q;
-  int swapped = 0;
- 800568e:	2300      	movs	r3, #0
- 8005690:	60fb      	str	r3, [r7, #12]
-
-  acc = 0;
- 8005692:	2300      	movs	r3, #0
- 8005694:	617b      	str	r3, [r7, #20]
-  for (q = p; q != NULL; q = q->next) {
- 8005696:	687b      	ldr	r3, [r7, #4]
- 8005698:	613b      	str	r3, [r7, #16]
- 800569a:	e02b      	b.n	80056f4 <inet_chksum_pbuf+0x6e>
-    acc += LWIP_CHKSUM(q->payload, q->len);
- 800569c:	693b      	ldr	r3, [r7, #16]
- 800569e:	685a      	ldr	r2, [r3, #4]
- 80056a0:	693b      	ldr	r3, [r7, #16]
- 80056a2:	895b      	ldrh	r3, [r3, #10]
- 80056a4:	4619      	mov	r1, r3
- 80056a6:	4610      	mov	r0, r2
- 80056a8:	f7ff ff7e 	bl	80055a8 <lwip_standard_chksum>
- 80056ac:	4603      	mov	r3, r0
- 80056ae:	461a      	mov	r2, r3
- 80056b0:	697b      	ldr	r3, [r7, #20]
- 80056b2:	4413      	add	r3, r2
- 80056b4:	617b      	str	r3, [r7, #20]
-    acc = FOLD_U32T(acc);
- 80056b6:	697b      	ldr	r3, [r7, #20]
- 80056b8:	0c1a      	lsrs	r2, r3, #16
- 80056ba:	697b      	ldr	r3, [r7, #20]
- 80056bc:	b29b      	uxth	r3, r3
- 80056be:	4413      	add	r3, r2
- 80056c0:	617b      	str	r3, [r7, #20]
-    if (q->len % 2 != 0) {
- 80056c2:	693b      	ldr	r3, [r7, #16]
- 80056c4:	895b      	ldrh	r3, [r3, #10]
- 80056c6:	f003 0301 	and.w	r3, r3, #1
- 80056ca:	b29b      	uxth	r3, r3
- 80056cc:	2b00      	cmp	r3, #0
- 80056ce:	d00e      	beq.n	80056ee <inet_chksum_pbuf+0x68>
-      swapped = !swapped;
- 80056d0:	68fb      	ldr	r3, [r7, #12]
- 80056d2:	2b00      	cmp	r3, #0
- 80056d4:	bf0c      	ite	eq
- 80056d6:	2301      	moveq	r3, #1
- 80056d8:	2300      	movne	r3, #0
- 80056da:	b2db      	uxtb	r3, r3
- 80056dc:	60fb      	str	r3, [r7, #12]
-      acc = SWAP_BYTES_IN_WORD(acc);
- 80056de:	697b      	ldr	r3, [r7, #20]
- 80056e0:	021b      	lsls	r3, r3, #8
- 80056e2:	b29a      	uxth	r2, r3
- 80056e4:	697b      	ldr	r3, [r7, #20]
- 80056e6:	0a1b      	lsrs	r3, r3, #8
- 80056e8:	b2db      	uxtb	r3, r3
- 80056ea:	4313      	orrs	r3, r2
- 80056ec:	617b      	str	r3, [r7, #20]
-  for (q = p; q != NULL; q = q->next) {
- 80056ee:	693b      	ldr	r3, [r7, #16]
- 80056f0:	681b      	ldr	r3, [r3, #0]
- 80056f2:	613b      	str	r3, [r7, #16]
- 80056f4:	693b      	ldr	r3, [r7, #16]
- 80056f6:	2b00      	cmp	r3, #0
- 80056f8:	d1d0      	bne.n	800569c <inet_chksum_pbuf+0x16>
-    }
-  }
-
-  if (swapped) {
- 80056fa:	68fb      	ldr	r3, [r7, #12]
- 80056fc:	2b00      	cmp	r3, #0
- 80056fe:	d007      	beq.n	8005710 <inet_chksum_pbuf+0x8a>
-    acc = SWAP_BYTES_IN_WORD(acc);
- 8005700:	697b      	ldr	r3, [r7, #20]
- 8005702:	021b      	lsls	r3, r3, #8
- 8005704:	b29a      	uxth	r2, r3
- 8005706:	697b      	ldr	r3, [r7, #20]
- 8005708:	0a1b      	lsrs	r3, r3, #8
- 800570a:	b2db      	uxtb	r3, r3
- 800570c:	4313      	orrs	r3, r2
- 800570e:	617b      	str	r3, [r7, #20]
-  }
-  return (u16_t)~(acc & 0xffffUL);
- 8005710:	697b      	ldr	r3, [r7, #20]
- 8005712:	b29b      	uxth	r3, r3
- 8005714:	43db      	mvns	r3, r3
- 8005716:	b29b      	uxth	r3, r3
-}
- 8005718:	4618      	mov	r0, r3
- 800571a:	3718      	adds	r7, #24
- 800571c:	46bd      	mov	sp, r7
- 800571e:	bd80      	pop	{r7, pc}
-
-08005720 <lwip_init>:
- * Initialize all modules.
- * Use this in NO_SYS mode. Use tcpip_init() otherwise.
- */
-void
-lwip_init(void)
-{
- 8005720:	b580      	push	{r7, lr}
- 8005722:	b082      	sub	sp, #8
- 8005724:	af00      	add	r7, sp, #0
-#ifndef LWIP_SKIP_CONST_CHECK
-  int a = 0;
- 8005726:	2300      	movs	r3, #0
- 8005728:	607b      	str	r3, [r7, #4]
-  /* Modules initialization */
-  stats_init();
-#if !NO_SYS
-  sys_init();
-#endif /* !NO_SYS */
-  mem_init();
- 800572a:	f000 f8d9 	bl	80058e0 <mem_init>
-  memp_init();
- 800572e:	f000 fc07 	bl	8005f40 <memp_init>
-  pbuf_init();
-  netif_init();
- 8005732:	f000 fd0d 	bl	8006150 <netif_init>
-#endif /* LWIP_IPV4 */
-#if LWIP_RAW
-  raw_init();
-#endif /* LWIP_RAW */
-#if LWIP_UDP
-  udp_init();
- 8005736:	f008 f829 	bl	800d78c <udp_init>
-#endif /* LWIP_UDP */
-#if LWIP_TCP
-  tcp_init();
- 800573a:	f001 fed9 	bl	80074f0 <tcp_init>
-#if PPP_SUPPORT
-  ppp_init();
-#endif
-
-#if LWIP_TIMERS
-  sys_timeouts_init();
- 800573e:	f007 ff9b 	bl	800d678 <sys_timeouts_init>
-#endif /* LWIP_TIMERS */
-}
- 8005742:	bf00      	nop
- 8005744:	3708      	adds	r7, #8
- 8005746:	46bd      	mov	sp, r7
- 8005748:	bd80      	pop	{r7, pc}
-	...
-
-0800574c <ptr_to_mem>:
-#define mem_overflow_check_element(mem)
-#endif /* MEM_OVERFLOW_CHECK */
-
-static struct mem *
-ptr_to_mem(mem_size_t ptr)
-{
- 800574c:	b480      	push	{r7}
- 800574e:	b083      	sub	sp, #12
- 8005750:	af00      	add	r7, sp, #0
- 8005752:	4603      	mov	r3, r0
- 8005754:	80fb      	strh	r3, [r7, #6]
-  return (struct mem *)(void *)&ram[ptr];
- 8005756:	4b05      	ldr	r3, [pc, #20]	; (800576c <ptr_to_mem+0x20>)
- 8005758:	681a      	ldr	r2, [r3, #0]
- 800575a:	88fb      	ldrh	r3, [r7, #6]
- 800575c:	4413      	add	r3, r2
-}
- 800575e:	4618      	mov	r0, r3
- 8005760:	370c      	adds	r7, #12
- 8005762:	46bd      	mov	sp, r7
- 8005764:	f85d 7b04 	ldr.w	r7, [sp], #4
- 8005768:	4770      	bx	lr
- 800576a:	bf00      	nop
- 800576c:	24004c28 	.word	0x24004c28
-
-08005770 <mem_to_ptr>:
-
-static mem_size_t
-mem_to_ptr(void *mem)
-{
- 8005770:	b480      	push	{r7}
- 8005772:	b083      	sub	sp, #12
- 8005774:	af00      	add	r7, sp, #0
- 8005776:	6078      	str	r0, [r7, #4]
-  return (mem_size_t)((u8_t *)mem - ram);
- 8005778:	4b05      	ldr	r3, [pc, #20]	; (8005790 <mem_to_ptr+0x20>)
- 800577a:	681b      	ldr	r3, [r3, #0]
- 800577c:	687a      	ldr	r2, [r7, #4]
- 800577e:	1ad3      	subs	r3, r2, r3
- 8005780:	b29b      	uxth	r3, r3
-}
- 8005782:	4618      	mov	r0, r3
- 8005784:	370c      	adds	r7, #12
- 8005786:	46bd      	mov	sp, r7
- 8005788:	f85d 7b04 	ldr.w	r7, [sp], #4
- 800578c:	4770      	bx	lr
- 800578e:	bf00      	nop
- 8005790:	24004c28 	.word	0x24004c28
-
-08005794 <plug_holes>:
- * This assumes access to the heap is protected by the calling function
- * already.
- */
-static void
-plug_holes(struct mem *mem)
-{
- 8005794:	b590      	push	{r4, r7, lr}
- 8005796:	b085      	sub	sp, #20
- 8005798:	af00      	add	r7, sp, #0
- 800579a:	6078      	str	r0, [r7, #4]
-  struct mem *nmem;
-  struct mem *pmem;
-
-  LWIP_ASSERT("plug_holes: mem >= ram", (u8_t *)mem >= ram);
- 800579c:	4b47      	ldr	r3, [pc, #284]	; (80058bc <plug_holes+0x128>)
- 800579e:	681b      	ldr	r3, [r3, #0]
- 80057a0:	687a      	ldr	r2, [r7, #4]
- 80057a2:	429a      	cmp	r2, r3
- 80057a4:	d206      	bcs.n	80057b4 <plug_holes+0x20>
- 80057a6:	4b46      	ldr	r3, [pc, #280]	; (80058c0 <plug_holes+0x12c>)
- 80057a8:	f240 12df 	movw	r2, #479	; 0x1df
- 80057ac:	4945      	ldr	r1, [pc, #276]	; (80058c4 <plug_holes+0x130>)
- 80057ae:	4846      	ldr	r0, [pc, #280]	; (80058c8 <plug_holes+0x134>)
- 80057b0:	f00b fa0a 	bl	8010bc8 <iprintf>
-  LWIP_ASSERT("plug_holes: mem < ram_end", (u8_t *)mem < (u8_t *)ram_end);
- 80057b4:	4b45      	ldr	r3, [pc, #276]	; (80058cc <plug_holes+0x138>)
- 80057b6:	681b      	ldr	r3, [r3, #0]
- 80057b8:	687a      	ldr	r2, [r7, #4]
- 80057ba:	429a      	cmp	r2, r3
- 80057bc:	d306      	bcc.n	80057cc <plug_holes+0x38>
- 80057be:	4b40      	ldr	r3, [pc, #256]	; (80058c0 <plug_holes+0x12c>)
- 80057c0:	f44f 72f0 	mov.w	r2, #480	; 0x1e0
- 80057c4:	4942      	ldr	r1, [pc, #264]	; (80058d0 <plug_holes+0x13c>)
- 80057c6:	4840      	ldr	r0, [pc, #256]	; (80058c8 <plug_holes+0x134>)
- 80057c8:	f00b f9fe 	bl	8010bc8 <iprintf>
-  LWIP_ASSERT("plug_holes: mem->used == 0", mem->used == 0);
- 80057cc:	687b      	ldr	r3, [r7, #4]
- 80057ce:	791b      	ldrb	r3, [r3, #4]
- 80057d0:	2b00      	cmp	r3, #0
- 80057d2:	d006      	beq.n	80057e2 <plug_holes+0x4e>
- 80057d4:	4b3a      	ldr	r3, [pc, #232]	; (80058c0 <plug_holes+0x12c>)
- 80057d6:	f240 12e1 	movw	r2, #481	; 0x1e1
- 80057da:	493e      	ldr	r1, [pc, #248]	; (80058d4 <plug_holes+0x140>)
- 80057dc:	483a      	ldr	r0, [pc, #232]	; (80058c8 <plug_holes+0x134>)
- 80057de:	f00b f9f3 	bl	8010bc8 <iprintf>
-
-  /* plug hole forward */
-  LWIP_ASSERT("plug_holes: mem->next <= MEM_SIZE_ALIGNED", mem->next <= MEM_SIZE_ALIGNED);
- 80057e2:	687b      	ldr	r3, [r7, #4]
- 80057e4:	881b      	ldrh	r3, [r3, #0]
- 80057e6:	f647 52e8 	movw	r2, #32232	; 0x7de8
- 80057ea:	4293      	cmp	r3, r2
- 80057ec:	d906      	bls.n	80057fc <plug_holes+0x68>
- 80057ee:	4b34      	ldr	r3, [pc, #208]	; (80058c0 <plug_holes+0x12c>)
- 80057f0:	f44f 72f2 	mov.w	r2, #484	; 0x1e4
- 80057f4:	4938      	ldr	r1, [pc, #224]	; (80058d8 <plug_holes+0x144>)
- 80057f6:	4834      	ldr	r0, [pc, #208]	; (80058c8 <plug_holes+0x134>)
- 80057f8:	f00b f9e6 	bl	8010bc8 <iprintf>
-
-  nmem = ptr_to_mem(mem->next);
- 80057fc:	687b      	ldr	r3, [r7, #4]
- 80057fe:	881b      	ldrh	r3, [r3, #0]
- 8005800:	4618      	mov	r0, r3
- 8005802:	f7ff ffa3 	bl	800574c <ptr_to_mem>
- 8005806:	60f8      	str	r0, [r7, #12]
-  if (mem != nmem && nmem->used == 0 && (u8_t *)nmem != (u8_t *)ram_end) {
- 8005808:	687a      	ldr	r2, [r7, #4]
- 800580a:	68fb      	ldr	r3, [r7, #12]
- 800580c:	429a      	cmp	r2, r3
- 800580e:	d025      	beq.n	800585c <plug_holes+0xc8>
- 8005810:	68fb      	ldr	r3, [r7, #12]
- 8005812:	791b      	ldrb	r3, [r3, #4]
- 8005814:	2b00      	cmp	r3, #0
- 8005816:	d121      	bne.n	800585c <plug_holes+0xc8>
- 8005818:	4b2c      	ldr	r3, [pc, #176]	; (80058cc <plug_holes+0x138>)
- 800581a:	681b      	ldr	r3, [r3, #0]
- 800581c:	68fa      	ldr	r2, [r7, #12]
- 800581e:	429a      	cmp	r2, r3
- 8005820:	d01c      	beq.n	800585c <plug_holes+0xc8>
-    /* if mem->next is unused and not end of ram, combine mem and mem->next */
-    if (lfree == nmem) {
- 8005822:	4b2e      	ldr	r3, [pc, #184]	; (80058dc <plug_holes+0x148>)
- 8005824:	681b      	ldr	r3, [r3, #0]
- 8005826:	68fa      	ldr	r2, [r7, #12]
- 8005828:	429a      	cmp	r2, r3
- 800582a:	d102      	bne.n	8005832 <plug_holes+0x9e>
-      lfree = mem;
- 800582c:	4a2b      	ldr	r2, [pc, #172]	; (80058dc <plug_holes+0x148>)
- 800582e:	687b      	ldr	r3, [r7, #4]
- 8005830:	6013      	str	r3, [r2, #0]
-    }
-    mem->next = nmem->next;
- 8005832:	68fb      	ldr	r3, [r7, #12]
- 8005834:	881a      	ldrh	r2, [r3, #0]
- 8005836:	687b      	ldr	r3, [r7, #4]
- 8005838:	801a      	strh	r2, [r3, #0]
-    if (nmem->next != MEM_SIZE_ALIGNED) {
- 800583a:	68fb      	ldr	r3, [r7, #12]
- 800583c:	881b      	ldrh	r3, [r3, #0]
- 800583e:	f647 52e8 	movw	r2, #32232	; 0x7de8
- 8005842:	4293      	cmp	r3, r2
- 8005844:	d00a      	beq.n	800585c <plug_holes+0xc8>
-      ptr_to_mem(nmem->next)->prev = mem_to_ptr(mem);
- 8005846:	68fb      	ldr	r3, [r7, #12]
- 8005848:	881b      	ldrh	r3, [r3, #0]
- 800584a:	4618      	mov	r0, r3
- 800584c:	f7ff ff7e 	bl	800574c <ptr_to_mem>
- 8005850:	4604      	mov	r4, r0
- 8005852:	6878      	ldr	r0, [r7, #4]
- 8005854:	f7ff ff8c 	bl	8005770 <mem_to_ptr>
- 8005858:	4603      	mov	r3, r0
- 800585a:	8063      	strh	r3, [r4, #2]
-    }
-  }
-
-  /* plug hole backward */
-  pmem = ptr_to_mem(mem->prev);
- 800585c:	687b      	ldr	r3, [r7, #4]
- 800585e:	885b      	ldrh	r3, [r3, #2]
- 8005860:	4618      	mov	r0, r3
- 8005862:	f7ff ff73 	bl	800574c <ptr_to_mem>
- 8005866:	60b8      	str	r0, [r7, #8]
-  if (pmem != mem && pmem->used == 0) {
- 8005868:	68ba      	ldr	r2, [r7, #8]
- 800586a:	687b      	ldr	r3, [r7, #4]
- 800586c:	429a      	cmp	r2, r3
- 800586e:	d020      	beq.n	80058b2 <plug_holes+0x11e>
- 8005870:	68bb      	ldr	r3, [r7, #8]
- 8005872:	791b      	ldrb	r3, [r3, #4]
- 8005874:	2b00      	cmp	r3, #0
- 8005876:	d11c      	bne.n	80058b2 <plug_holes+0x11e>
-    /* if mem->prev is unused, combine mem and mem->prev */
-    if (lfree == mem) {
- 8005878:	4b18      	ldr	r3, [pc, #96]	; (80058dc <plug_holes+0x148>)
- 800587a:	681b      	ldr	r3, [r3, #0]
- 800587c:	687a      	ldr	r2, [r7, #4]
- 800587e:	429a      	cmp	r2, r3
- 8005880:	d102      	bne.n	8005888 <plug_holes+0xf4>
-      lfree = pmem;
- 8005882:	4a16      	ldr	r2, [pc, #88]	; (80058dc <plug_holes+0x148>)
- 8005884:	68bb      	ldr	r3, [r7, #8]
- 8005886:	6013      	str	r3, [r2, #0]
-    }
-    pmem->next = mem->next;
- 8005888:	687b      	ldr	r3, [r7, #4]
- 800588a:	881a      	ldrh	r2, [r3, #0]
- 800588c:	68bb      	ldr	r3, [r7, #8]
- 800588e:	801a      	strh	r2, [r3, #0]
-    if (mem->next != MEM_SIZE_ALIGNED) {
- 8005890:	687b      	ldr	r3, [r7, #4]
- 8005892:	881b      	ldrh	r3, [r3, #0]
- 8005894:	f647 52e8 	movw	r2, #32232	; 0x7de8
- 8005898:	4293      	cmp	r3, r2
- 800589a:	d00a      	beq.n	80058b2 <plug_holes+0x11e>
-      ptr_to_mem(mem->next)->prev = mem_to_ptr(pmem);
- 800589c:	687b      	ldr	r3, [r7, #4]
- 800589e:	881b      	ldrh	r3, [r3, #0]
- 80058a0:	4618      	mov	r0, r3
- 80058a2:	f7ff ff53 	bl	800574c <ptr_to_mem>
- 80058a6:	4604      	mov	r4, r0
- 80058a8:	68b8      	ldr	r0, [r7, #8]
- 80058aa:	f7ff ff61 	bl	8005770 <mem_to_ptr>
- 80058ae:	4603      	mov	r3, r0
- 80058b0:	8063      	strh	r3, [r4, #2]
-    }
-  }
-}
- 80058b2:	bf00      	nop
- 80058b4:	3714      	adds	r7, #20
- 80058b6:	46bd      	mov	sp, r7
- 80058b8:	bd90      	pop	{r4, r7, pc}
- 80058ba:	bf00      	nop
- 80058bc:	24004c28 	.word	0x24004c28
- 80058c0:	08011ca0 	.word	0x08011ca0
- 80058c4:	08011cd0 	.word	0x08011cd0
- 80058c8:	08011ce8 	.word	0x08011ce8
- 80058cc:	24004c2c 	.word	0x24004c2c
- 80058d0:	08011d10 	.word	0x08011d10
- 80058d4:	08011d2c 	.word	0x08011d2c
- 80058d8:	08011d48 	.word	0x08011d48
- 80058dc:	24004c30 	.word	0x24004c30
-
-080058e0 <mem_init>:
-/**
- * Zero the heap and initialize start, end and lowest-free
- */
-void
-mem_init(void)
-{
- 80058e0:	b580      	push	{r7, lr}
- 80058e2:	b082      	sub	sp, #8
- 80058e4:	af00      	add	r7, sp, #0
-
-  LWIP_ASSERT("Sanity check alignment",
-              (SIZEOF_STRUCT_MEM & (MEM_ALIGNMENT - 1)) == 0);
-
-  /* align the heap */
-  ram = (u8_t *)LWIP_MEM_ALIGN(LWIP_RAM_HEAP_POINTER);
- 80058e6:	4b16      	ldr	r3, [pc, #88]	; (8005940 <mem_init+0x60>)
- 80058e8:	4a16      	ldr	r2, [pc, #88]	; (8005944 <mem_init+0x64>)
- 80058ea:	601a      	str	r2, [r3, #0]
-  /* initialize the start of the heap */
-  mem = (struct mem *)(void *)ram;
- 80058ec:	4b14      	ldr	r3, [pc, #80]	; (8005940 <mem_init+0x60>)
- 80058ee:	681b      	ldr	r3, [r3, #0]
- 80058f0:	607b      	str	r3, [r7, #4]
-  mem->next = MEM_SIZE_ALIGNED;
- 80058f2:	687b      	ldr	r3, [r7, #4]
- 80058f4:	f647 52e8 	movw	r2, #32232	; 0x7de8
- 80058f8:	801a      	strh	r2, [r3, #0]
-  mem->prev = 0;
- 80058fa:	687b      	ldr	r3, [r7, #4]
- 80058fc:	2200      	movs	r2, #0
- 80058fe:	805a      	strh	r2, [r3, #2]
-  mem->used = 0;
- 8005900:	687b      	ldr	r3, [r7, #4]
- 8005902:	2200      	movs	r2, #0
- 8005904:	711a      	strb	r2, [r3, #4]
-  /* initialize the end of the heap */
-  ram_end = ptr_to_mem(MEM_SIZE_ALIGNED);
- 8005906:	f647 50e8 	movw	r0, #32232	; 0x7de8
- 800590a:	f7ff ff1f 	bl	800574c <ptr_to_mem>
- 800590e:	4603      	mov	r3, r0
- 8005910:	4a0d      	ldr	r2, [pc, #52]	; (8005948 <mem_init+0x68>)
- 8005912:	6013      	str	r3, [r2, #0]
-  ram_end->used = 1;
- 8005914:	4b0c      	ldr	r3, [pc, #48]	; (8005948 <mem_init+0x68>)
- 8005916:	681b      	ldr	r3, [r3, #0]
- 8005918:	2201      	movs	r2, #1
- 800591a:	711a      	strb	r2, [r3, #4]
-  ram_end->next = MEM_SIZE_ALIGNED;
- 800591c:	4b0a      	ldr	r3, [pc, #40]	; (8005948 <mem_init+0x68>)
- 800591e:	681b      	ldr	r3, [r3, #0]
- 8005920:	f647 52e8 	movw	r2, #32232	; 0x7de8
- 8005924:	801a      	strh	r2, [r3, #0]
-  ram_end->prev = MEM_SIZE_ALIGNED;
- 8005926:	4b08      	ldr	r3, [pc, #32]	; (8005948 <mem_init+0x68>)
- 8005928:	681b      	ldr	r3, [r3, #0]
- 800592a:	f647 52e8 	movw	r2, #32232	; 0x7de8
- 800592e:	805a      	strh	r2, [r3, #2]
-  MEM_SANITY();
-
-  /* initialize the lowest-free pointer to the start of the heap */
-  lfree = (struct mem *)(void *)ram;
- 8005930:	4b03      	ldr	r3, [pc, #12]	; (8005940 <mem_init+0x60>)
- 8005932:	681b      	ldr	r3, [r3, #0]
- 8005934:	4a05      	ldr	r2, [pc, #20]	; (800594c <mem_init+0x6c>)
- 8005936:	6013      	str	r3, [r2, #0]
-  MEM_STATS_AVAIL(avail, MEM_SIZE_ALIGNED);
-
-  if (sys_mutex_new(&mem_mutex) != ERR_OK) {
-    LWIP_ASSERT("failed to create mem_mutex", 0);
-  }
-}
- 8005938:	bf00      	nop
- 800593a:	3708      	adds	r7, #8
- 800593c:	46bd      	mov	sp, r7
- 800593e:	bd80      	pop	{r7, pc}
- 8005940:	24004c28 	.word	0x24004c28
- 8005944:	30000200 	.word	0x30000200
- 8005948:	24004c2c 	.word	0x24004c2c
- 800594c:	24004c30 	.word	0x24004c30
-
-08005950 <mem_link_valid>:
-/* Check if a struct mem is correctly linked.
- * If not, double-free is a possible reason.
- */
-static int
-mem_link_valid(struct mem *mem)
-{
- 8005950:	b580      	push	{r7, lr}
- 8005952:	b086      	sub	sp, #24
- 8005954:	af00      	add	r7, sp, #0
- 8005956:	6078      	str	r0, [r7, #4]
-  struct mem *nmem, *pmem;
-  mem_size_t rmem_idx;
-  rmem_idx = mem_to_ptr(mem);
- 8005958:	6878      	ldr	r0, [r7, #4]
- 800595a:	f7ff ff09 	bl	8005770 <mem_to_ptr>
- 800595e:	4603      	mov	r3, r0
- 8005960:	82fb      	strh	r3, [r7, #22]
-  nmem = ptr_to_mem(mem->next);
- 8005962:	687b      	ldr	r3, [r7, #4]
- 8005964:	881b      	ldrh	r3, [r3, #0]
- 8005966:	4618      	mov	r0, r3
- 8005968:	f7ff fef0 	bl	800574c <ptr_to_mem>
- 800596c:	6138      	str	r0, [r7, #16]
-  pmem = ptr_to_mem(mem->prev);
- 800596e:	687b      	ldr	r3, [r7, #4]
- 8005970:	885b      	ldrh	r3, [r3, #2]
- 8005972:	4618      	mov	r0, r3
- 8005974:	f7ff feea 	bl	800574c <ptr_to_mem>
- 8005978:	60f8      	str	r0, [r7, #12]
-  if ((mem->next > MEM_SIZE_ALIGNED) || (mem->prev > MEM_SIZE_ALIGNED) ||
- 800597a:	687b      	ldr	r3, [r7, #4]
- 800597c:	881b      	ldrh	r3, [r3, #0]
- 800597e:	f647 52e8 	movw	r2, #32232	; 0x7de8
- 8005982:	4293      	cmp	r3, r2
- 8005984:	d819      	bhi.n	80059ba <mem_link_valid+0x6a>
- 8005986:	687b      	ldr	r3, [r7, #4]
- 8005988:	885b      	ldrh	r3, [r3, #2]
- 800598a:	f647 52e8 	movw	r2, #32232	; 0x7de8
- 800598e:	4293      	cmp	r3, r2
- 8005990:	d813      	bhi.n	80059ba <mem_link_valid+0x6a>
-      ((mem->prev != rmem_idx) && (pmem->next != rmem_idx)) ||
- 8005992:	687b      	ldr	r3, [r7, #4]
- 8005994:	885b      	ldrh	r3, [r3, #2]
-  if ((mem->next > MEM_SIZE_ALIGNED) || (mem->prev > MEM_SIZE_ALIGNED) ||
- 8005996:	8afa      	ldrh	r2, [r7, #22]
- 8005998:	429a      	cmp	r2, r3
- 800599a:	d004      	beq.n	80059a6 <mem_link_valid+0x56>
-      ((mem->prev != rmem_idx) && (pmem->next != rmem_idx)) ||
- 800599c:	68fb      	ldr	r3, [r7, #12]
- 800599e:	881b      	ldrh	r3, [r3, #0]
- 80059a0:	8afa      	ldrh	r2, [r7, #22]
- 80059a2:	429a      	cmp	r2, r3
- 80059a4:	d109      	bne.n	80059ba <mem_link_valid+0x6a>
-      ((nmem != ram_end) && (nmem->prev != rmem_idx))) {
- 80059a6:	4b08      	ldr	r3, [pc, #32]	; (80059c8 <mem_link_valid+0x78>)
- 80059a8:	681b      	ldr	r3, [r3, #0]
-      ((mem->prev != rmem_idx) && (pmem->next != rmem_idx)) ||
- 80059aa:	693a      	ldr	r2, [r7, #16]
- 80059ac:	429a      	cmp	r2, r3
- 80059ae:	d006      	beq.n	80059be <mem_link_valid+0x6e>
-      ((nmem != ram_end) && (nmem->prev != rmem_idx))) {
- 80059b0:	693b      	ldr	r3, [r7, #16]
- 80059b2:	885b      	ldrh	r3, [r3, #2]
- 80059b4:	8afa      	ldrh	r2, [r7, #22]
- 80059b6:	429a      	cmp	r2, r3
- 80059b8:	d001      	beq.n	80059be <mem_link_valid+0x6e>
-    return 0;
- 80059ba:	2300      	movs	r3, #0
- 80059bc:	e000      	b.n	80059c0 <mem_link_valid+0x70>
-  }
-  return 1;
- 80059be:	2301      	movs	r3, #1
-}
- 80059c0:	4618      	mov	r0, r3
- 80059c2:	3718      	adds	r7, #24
- 80059c4:	46bd      	mov	sp, r7
- 80059c6:	bd80      	pop	{r7, pc}
- 80059c8:	24004c2c 	.word	0x24004c2c
-
-080059cc <mem_free>:
- * @param rmem is the data portion of a struct mem as returned by a previous
- *             call to mem_malloc()
- */
-void
-mem_free(void *rmem)
-{
- 80059cc:	b580      	push	{r7, lr}
- 80059ce:	b084      	sub	sp, #16
- 80059d0:	af00      	add	r7, sp, #0
- 80059d2:	6078      	str	r0, [r7, #4]
-  struct mem *mem;
-  LWIP_MEM_FREE_DECL_PROTECT();
-
-  if (rmem == NULL) {
- 80059d4:	687b      	ldr	r3, [r7, #4]
- 80059d6:	2b00      	cmp	r3, #0
- 80059d8:	d103      	bne.n	80059e2 <mem_free+0x16>
-    LWIP_DEBUGF(MEM_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, ("mem_free(p == NULL) was called.\n"));
- 80059da:	482f      	ldr	r0, [pc, #188]	; (8005a98 <mem_free+0xcc>)
- 80059dc:	f00b f962 	bl	8010ca4 <puts>
-    return;
- 80059e0:	e057      	b.n	8005a92 <mem_free+0xc6>
-  }
-  if ((((mem_ptr_t)rmem) & (MEM_ALIGNMENT - 1)) != 0) {
- 80059e2:	687b      	ldr	r3, [r7, #4]
- 80059e4:	f003 0303 	and.w	r3, r3, #3
- 80059e8:	2b00      	cmp	r3, #0
- 80059ea:	d00a      	beq.n	8005a02 <mem_free+0x36>
-    LWIP_MEM_ILLEGAL_FREE("mem_free: sanity check alignment");
- 80059ec:	4b2b      	ldr	r3, [pc, #172]	; (8005a9c <mem_free+0xd0>)
- 80059ee:	f240 2273 	movw	r2, #627	; 0x273
- 80059f2:	492b      	ldr	r1, [pc, #172]	; (8005aa0 <mem_free+0xd4>)
- 80059f4:	482b      	ldr	r0, [pc, #172]	; (8005aa4 <mem_free+0xd8>)
- 80059f6:	f00b f8e7 	bl	8010bc8 <iprintf>
-    LWIP_DEBUGF(MEM_DEBUG | LWIP_DBG_LEVEL_SEVERE, ("mem_free: sanity check alignment\n"));
- 80059fa:	4829      	ldr	r0, [pc, #164]	; (8005aa0 <mem_free+0xd4>)
- 80059fc:	f00b f952 	bl	8010ca4 <puts>
-    /* protect mem stats from concurrent access */
-    MEM_STATS_INC_LOCKED(illegal);
-    return;
- 8005a00:	e047      	b.n	8005a92 <mem_free+0xc6>
-  }
-
-  /* Get the corresponding struct mem: */
-  /* cast through void* to get rid of alignment warnings */
-  mem = (struct mem *)(void *)((u8_t *)rmem - (SIZEOF_STRUCT_MEM + MEM_SANITY_OFFSET));
- 8005a02:	687b      	ldr	r3, [r7, #4]
- 8005a04:	3b08      	subs	r3, #8
- 8005a06:	60fb      	str	r3, [r7, #12]
-
-  if ((u8_t *)mem < ram || (u8_t *)rmem + MIN_SIZE_ALIGNED > (u8_t *)ram_end) {
- 8005a08:	4b27      	ldr	r3, [pc, #156]	; (8005aa8 <mem_free+0xdc>)
- 8005a0a:	681b      	ldr	r3, [r3, #0]
- 8005a0c:	68fa      	ldr	r2, [r7, #12]
- 8005a0e:	429a      	cmp	r2, r3
- 8005a10:	d306      	bcc.n	8005a20 <mem_free+0x54>
- 8005a12:	687b      	ldr	r3, [r7, #4]
- 8005a14:	f103 020c 	add.w	r2, r3, #12
- 8005a18:	4b24      	ldr	r3, [pc, #144]	; (8005aac <mem_free+0xe0>)
- 8005a1a:	681b      	ldr	r3, [r3, #0]
- 8005a1c:	429a      	cmp	r2, r3
- 8005a1e:	d90a      	bls.n	8005a36 <mem_free+0x6a>
-    LWIP_MEM_ILLEGAL_FREE("mem_free: illegal memory");
- 8005a20:	4b1e      	ldr	r3, [pc, #120]	; (8005a9c <mem_free+0xd0>)
- 8005a22:	f240 227f 	movw	r2, #639	; 0x27f
- 8005a26:	4922      	ldr	r1, [pc, #136]	; (8005ab0 <mem_free+0xe4>)
- 8005a28:	481e      	ldr	r0, [pc, #120]	; (8005aa4 <mem_free+0xd8>)
- 8005a2a:	f00b f8cd 	bl	8010bc8 <iprintf>
-    LWIP_DEBUGF(MEM_DEBUG | LWIP_DBG_LEVEL_SEVERE, ("mem_free: illegal memory\n"));
- 8005a2e:	4820      	ldr	r0, [pc, #128]	; (8005ab0 <mem_free+0xe4>)
- 8005a30:	f00b f938 	bl	8010ca4 <puts>
-    /* protect mem stats from concurrent access */
-    MEM_STATS_INC_LOCKED(illegal);
-    return;
- 8005a34:	e02d      	b.n	8005a92 <mem_free+0xc6>
-  mem_overflow_check_element(mem);
-#endif
-  /* protect the heap from concurrent access */
-  LWIP_MEM_FREE_PROTECT();
-  /* mem has to be in a used state */
-  if (!mem->used) {
- 8005a36:	68fb      	ldr	r3, [r7, #12]
- 8005a38:	791b      	ldrb	r3, [r3, #4]
- 8005a3a:	2b00      	cmp	r3, #0
- 8005a3c:	d10a      	bne.n	8005a54 <mem_free+0x88>
-    LWIP_MEM_ILLEGAL_FREE("mem_free: illegal memory: double free");
- 8005a3e:	4b17      	ldr	r3, [pc, #92]	; (8005a9c <mem_free+0xd0>)
- 8005a40:	f44f 7223 	mov.w	r2, #652	; 0x28c
- 8005a44:	491b      	ldr	r1, [pc, #108]	; (8005ab4 <mem_free+0xe8>)
- 8005a46:	4817      	ldr	r0, [pc, #92]	; (8005aa4 <mem_free+0xd8>)
- 8005a48:	f00b f8be 	bl	8010bc8 <iprintf>
-    LWIP_MEM_FREE_UNPROTECT();
-    LWIP_DEBUGF(MEM_DEBUG | LWIP_DBG_LEVEL_SEVERE, ("mem_free: illegal memory: double free?\n"));
- 8005a4c:	481a      	ldr	r0, [pc, #104]	; (8005ab8 <mem_free+0xec>)
- 8005a4e:	f00b f929 	bl	8010ca4 <puts>
-    /* protect mem stats from concurrent access */
-    MEM_STATS_INC_LOCKED(illegal);
-    return;
- 8005a52:	e01e      	b.n	8005a92 <mem_free+0xc6>
-  }
-
-  if (!mem_link_valid(mem)) {
- 8005a54:	68f8      	ldr	r0, [r7, #12]
- 8005a56:	f7ff ff7b 	bl	8005950 <mem_link_valid>
- 8005a5a:	4603      	mov	r3, r0
- 8005a5c:	2b00      	cmp	r3, #0
- 8005a5e:	d10a      	bne.n	8005a76 <mem_free+0xaa>
-    LWIP_MEM_ILLEGAL_FREE("mem_free: illegal memory: non-linked: double free");
- 8005a60:	4b0e      	ldr	r3, [pc, #56]	; (8005a9c <mem_free+0xd0>)
- 8005a62:	f240 2295 	movw	r2, #661	; 0x295
- 8005a66:	4915      	ldr	r1, [pc, #84]	; (8005abc <mem_free+0xf0>)
- 8005a68:	480e      	ldr	r0, [pc, #56]	; (8005aa4 <mem_free+0xd8>)
- 8005a6a:	f00b f8ad 	bl	8010bc8 <iprintf>
-    LWIP_MEM_FREE_UNPROTECT();
-    LWIP_DEBUGF(MEM_DEBUG | LWIP_DBG_LEVEL_SEVERE, ("mem_free: illegal memory: non-linked: double free?\n"));
- 8005a6e:	4814      	ldr	r0, [pc, #80]	; (8005ac0 <mem_free+0xf4>)
- 8005a70:	f00b f918 	bl	8010ca4 <puts>
-    /* protect mem stats from concurrent access */
-    MEM_STATS_INC_LOCKED(illegal);
-    return;
- 8005a74:	e00d      	b.n	8005a92 <mem_free+0xc6>
-  }
-
-  /* mem is now unused. */
-  mem->used = 0;
- 8005a76:	68fb      	ldr	r3, [r7, #12]
- 8005a78:	2200      	movs	r2, #0
- 8005a7a:	711a      	strb	r2, [r3, #4]
-
-  if (mem < lfree) {
- 8005a7c:	4b11      	ldr	r3, [pc, #68]	; (8005ac4 <mem_free+0xf8>)
- 8005a7e:	681b      	ldr	r3, [r3, #0]
- 8005a80:	68fa      	ldr	r2, [r7, #12]
- 8005a82:	429a      	cmp	r2, r3
- 8005a84:	d202      	bcs.n	8005a8c <mem_free+0xc0>
-    /* the newly freed struct is now the lowest */
-    lfree = mem;
- 8005a86:	4a0f      	ldr	r2, [pc, #60]	; (8005ac4 <mem_free+0xf8>)
- 8005a88:	68fb      	ldr	r3, [r7, #12]
- 8005a8a:	6013      	str	r3, [r2, #0]
-  }
-
-  MEM_STATS_DEC_USED(used, mem->next - (mem_size_t)(((u8_t *)mem - ram)));
-
-  /* finally, see if prev or next are free also */
-  plug_holes(mem);
- 8005a8c:	68f8      	ldr	r0, [r7, #12]
- 8005a8e:	f7ff fe81 	bl	8005794 <plug_holes>
-  MEM_SANITY();
-#if LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT
-  mem_free_count = 1;
-#endif /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */
-  LWIP_MEM_FREE_UNPROTECT();
-}
- 8005a92:	3710      	adds	r7, #16
- 8005a94:	46bd      	mov	sp, r7
- 8005a96:	bd80      	pop	{r7, pc}
- 8005a98:	08011d74 	.word	0x08011d74
- 8005a9c:	08011ca0 	.word	0x08011ca0
- 8005aa0:	08011d94 	.word	0x08011d94
- 8005aa4:	08011ce8 	.word	0x08011ce8
- 8005aa8:	24004c28 	.word	0x24004c28
- 8005aac:	24004c2c 	.word	0x24004c2c
- 8005ab0:	08011db8 	.word	0x08011db8
- 8005ab4:	08011dd4 	.word	0x08011dd4
- 8005ab8:	08011dfc 	.word	0x08011dfc
- 8005abc:	08011e24 	.word	0x08011e24
- 8005ac0:	08011e58 	.word	0x08011e58
- 8005ac4:	24004c30 	.word	0x24004c30
-
-08005ac8 <mem_trim>:
- *         or NULL if newsize is > old size, in which case rmem is NOT touched
- *         or freed!
- */
-void *
-mem_trim(void *rmem, mem_size_t new_size)
-{
- 8005ac8:	b580      	push	{r7, lr}
- 8005aca:	b088      	sub	sp, #32
- 8005acc:	af00      	add	r7, sp, #0
- 8005ace:	6078      	str	r0, [r7, #4]
- 8005ad0:	460b      	mov	r3, r1
- 8005ad2:	807b      	strh	r3, [r7, #2]
-  /* use the FREE_PROTECT here: it protects with sem OR SYS_ARCH_PROTECT */
-  LWIP_MEM_FREE_DECL_PROTECT();
-
-  /* Expand the size of the allocated memory region so that we can
-     adjust for alignment. */
-  newsize = (mem_size_t)LWIP_MEM_ALIGN_SIZE(new_size);
- 8005ad4:	887b      	ldrh	r3, [r7, #2]
- 8005ad6:	3303      	adds	r3, #3
- 8005ad8:	b29b      	uxth	r3, r3
- 8005ada:	f023 0303 	bic.w	r3, r3, #3
- 8005ade:	83fb      	strh	r3, [r7, #30]
-  if (newsize < MIN_SIZE_ALIGNED) {
- 8005ae0:	8bfb      	ldrh	r3, [r7, #30]
- 8005ae2:	2b0b      	cmp	r3, #11
- 8005ae4:	d801      	bhi.n	8005aea <mem_trim+0x22>
-    /* every data block must be at least MIN_SIZE_ALIGNED long */
-    newsize = MIN_SIZE_ALIGNED;
- 8005ae6:	230c      	movs	r3, #12
- 8005ae8:	83fb      	strh	r3, [r7, #30]
-  }
-#if MEM_OVERFLOW_CHECK
-  newsize += MEM_SANITY_REGION_BEFORE_ALIGNED + MEM_SANITY_REGION_AFTER_ALIGNED;
-#endif
-  if ((newsize > MEM_SIZE_ALIGNED) || (newsize < new_size)) {
- 8005aea:	8bfb      	ldrh	r3, [r7, #30]
- 8005aec:	f647 52e8 	movw	r2, #32232	; 0x7de8
- 8005af0:	4293      	cmp	r3, r2
- 8005af2:	d803      	bhi.n	8005afc <mem_trim+0x34>
- 8005af4:	8bfa      	ldrh	r2, [r7, #30]
- 8005af6:	887b      	ldrh	r3, [r7, #2]
- 8005af8:	429a      	cmp	r2, r3
- 8005afa:	d201      	bcs.n	8005b00 <mem_trim+0x38>
-    return NULL;
- 8005afc:	2300      	movs	r3, #0
- 8005afe:	e0d3      	b.n	8005ca8 <mem_trim+0x1e0>
-  }
-
-  LWIP_ASSERT("mem_trim: legal memory", (u8_t *)rmem >= (u8_t *)ram &&
- 8005b00:	4b6b      	ldr	r3, [pc, #428]	; (8005cb0 <mem_trim+0x1e8>)
- 8005b02:	681b      	ldr	r3, [r3, #0]
- 8005b04:	687a      	ldr	r2, [r7, #4]
- 8005b06:	429a      	cmp	r2, r3
- 8005b08:	d304      	bcc.n	8005b14 <mem_trim+0x4c>
- 8005b0a:	4b6a      	ldr	r3, [pc, #424]	; (8005cb4 <mem_trim+0x1ec>)
- 8005b0c:	681b      	ldr	r3, [r3, #0]
- 8005b0e:	687a      	ldr	r2, [r7, #4]
- 8005b10:	429a      	cmp	r2, r3
- 8005b12:	d306      	bcc.n	8005b22 <mem_trim+0x5a>
- 8005b14:	4b68      	ldr	r3, [pc, #416]	; (8005cb8 <mem_trim+0x1f0>)
- 8005b16:	f240 22d1 	movw	r2, #721	; 0x2d1
- 8005b1a:	4968      	ldr	r1, [pc, #416]	; (8005cbc <mem_trim+0x1f4>)
- 8005b1c:	4868      	ldr	r0, [pc, #416]	; (8005cc0 <mem_trim+0x1f8>)
- 8005b1e:	f00b f853 	bl	8010bc8 <iprintf>
-              (u8_t *)rmem < (u8_t *)ram_end);
-
-  if ((u8_t *)rmem < (u8_t *)ram || (u8_t *)rmem >= (u8_t *)ram_end) {
- 8005b22:	4b63      	ldr	r3, [pc, #396]	; (8005cb0 <mem_trim+0x1e8>)
- 8005b24:	681b      	ldr	r3, [r3, #0]
- 8005b26:	687a      	ldr	r2, [r7, #4]
- 8005b28:	429a      	cmp	r2, r3
- 8005b2a:	d304      	bcc.n	8005b36 <mem_trim+0x6e>
- 8005b2c:	4b61      	ldr	r3, [pc, #388]	; (8005cb4 <mem_trim+0x1ec>)
- 8005b2e:	681b      	ldr	r3, [r3, #0]
- 8005b30:	687a      	ldr	r2, [r7, #4]
- 8005b32:	429a      	cmp	r2, r3
- 8005b34:	d304      	bcc.n	8005b40 <mem_trim+0x78>
-    LWIP_DEBUGF(MEM_DEBUG | LWIP_DBG_LEVEL_SEVERE, ("mem_trim: illegal memory\n"));
- 8005b36:	4863      	ldr	r0, [pc, #396]	; (8005cc4 <mem_trim+0x1fc>)
- 8005b38:	f00b f8b4 	bl	8010ca4 <puts>
-    /* protect mem stats from concurrent access */
-    MEM_STATS_INC_LOCKED(illegal);
-    return rmem;
- 8005b3c:	687b      	ldr	r3, [r7, #4]
- 8005b3e:	e0b3      	b.n	8005ca8 <mem_trim+0x1e0>
-  }
-  /* Get the corresponding struct mem ... */
-  /* cast through void* to get rid of alignment warnings */
-  mem = (struct mem *)(void *)((u8_t *)rmem - (SIZEOF_STRUCT_MEM + MEM_SANITY_OFFSET));
- 8005b40:	687b      	ldr	r3, [r7, #4]
- 8005b42:	3b08      	subs	r3, #8
- 8005b44:	61bb      	str	r3, [r7, #24]
-#if MEM_OVERFLOW_CHECK
-  mem_overflow_check_element(mem);
-#endif
-  /* ... and its offset pointer */
-  ptr = mem_to_ptr(mem);
- 8005b46:	69b8      	ldr	r0, [r7, #24]
- 8005b48:	f7ff fe12 	bl	8005770 <mem_to_ptr>
- 8005b4c:	4603      	mov	r3, r0
- 8005b4e:	82fb      	strh	r3, [r7, #22]
-
-  size = (mem_size_t)((mem_size_t)(mem->next - ptr) - (SIZEOF_STRUCT_MEM + MEM_SANITY_OVERHEAD));
- 8005b50:	69bb      	ldr	r3, [r7, #24]
- 8005b52:	881a      	ldrh	r2, [r3, #0]
- 8005b54:	8afb      	ldrh	r3, [r7, #22]
- 8005b56:	1ad3      	subs	r3, r2, r3
- 8005b58:	b29b      	uxth	r3, r3
- 8005b5a:	3b08      	subs	r3, #8
- 8005b5c:	82bb      	strh	r3, [r7, #20]
-  LWIP_ASSERT("mem_trim can only shrink memory", newsize <= size);
- 8005b5e:	8bfa      	ldrh	r2, [r7, #30]
- 8005b60:	8abb      	ldrh	r3, [r7, #20]
- 8005b62:	429a      	cmp	r2, r3
- 8005b64:	d906      	bls.n	8005b74 <mem_trim+0xac>
- 8005b66:	4b54      	ldr	r3, [pc, #336]	; (8005cb8 <mem_trim+0x1f0>)
- 8005b68:	f44f 7239 	mov.w	r2, #740	; 0x2e4
- 8005b6c:	4956      	ldr	r1, [pc, #344]	; (8005cc8 <mem_trim+0x200>)
- 8005b6e:	4854      	ldr	r0, [pc, #336]	; (8005cc0 <mem_trim+0x1f8>)
- 8005b70:	f00b f82a 	bl	8010bc8 <iprintf>
-  if (newsize > size) {
- 8005b74:	8bfa      	ldrh	r2, [r7, #30]
- 8005b76:	8abb      	ldrh	r3, [r7, #20]
- 8005b78:	429a      	cmp	r2, r3
- 8005b7a:	d901      	bls.n	8005b80 <mem_trim+0xb8>
-    /* not supported */
-    return NULL;
- 8005b7c:	2300      	movs	r3, #0
- 8005b7e:	e093      	b.n	8005ca8 <mem_trim+0x1e0>
-  }
-  if (newsize == size) {
- 8005b80:	8bfa      	ldrh	r2, [r7, #30]
- 8005b82:	8abb      	ldrh	r3, [r7, #20]
- 8005b84:	429a      	cmp	r2, r3
- 8005b86:	d101      	bne.n	8005b8c <mem_trim+0xc4>
-    /* No change in size, simply return */
-    return rmem;
- 8005b88:	687b      	ldr	r3, [r7, #4]
- 8005b8a:	e08d      	b.n	8005ca8 <mem_trim+0x1e0>
-  }
-
-  /* protect the heap from concurrent access */
-  LWIP_MEM_FREE_PROTECT();
-
-  mem2 = ptr_to_mem(mem->next);
- 8005b8c:	69bb      	ldr	r3, [r7, #24]
- 8005b8e:	881b      	ldrh	r3, [r3, #0]
- 8005b90:	4618      	mov	r0, r3
- 8005b92:	f7ff fddb 	bl	800574c <ptr_to_mem>
- 8005b96:	6138      	str	r0, [r7, #16]
-  if (mem2->used == 0) {
- 8005b98:	693b      	ldr	r3, [r7, #16]
- 8005b9a:	791b      	ldrb	r3, [r3, #4]
- 8005b9c:	2b00      	cmp	r3, #0
- 8005b9e:	d141      	bne.n	8005c24 <mem_trim+0x15c>
-    /* The next struct is unused, we can simply move it at little */
-    mem_size_t next;
-    LWIP_ASSERT("invalid next ptr", mem->next != MEM_SIZE_ALIGNED);
- 8005ba0:	69bb      	ldr	r3, [r7, #24]
- 8005ba2:	881b      	ldrh	r3, [r3, #0]
- 8005ba4:	f647 52e8 	movw	r2, #32232	; 0x7de8
- 8005ba8:	4293      	cmp	r3, r2
- 8005baa:	d106      	bne.n	8005bba <mem_trim+0xf2>
- 8005bac:	4b42      	ldr	r3, [pc, #264]	; (8005cb8 <mem_trim+0x1f0>)
- 8005bae:	f240 22f5 	movw	r2, #757	; 0x2f5
- 8005bb2:	4946      	ldr	r1, [pc, #280]	; (8005ccc <mem_trim+0x204>)
- 8005bb4:	4842      	ldr	r0, [pc, #264]	; (8005cc0 <mem_trim+0x1f8>)
- 8005bb6:	f00b f807 	bl	8010bc8 <iprintf>
-    /* remember the old next pointer */
-    next = mem2->next;
- 8005bba:	693b      	ldr	r3, [r7, #16]
- 8005bbc:	881b      	ldrh	r3, [r3, #0]
- 8005bbe:	81bb      	strh	r3, [r7, #12]
-    /* create new struct mem which is moved directly after the shrinked mem */
-    ptr2 = (mem_size_t)(ptr + SIZEOF_STRUCT_MEM + newsize);
- 8005bc0:	8afa      	ldrh	r2, [r7, #22]
- 8005bc2:	8bfb      	ldrh	r3, [r7, #30]
- 8005bc4:	4413      	add	r3, r2
- 8005bc6:	b29b      	uxth	r3, r3
- 8005bc8:	3308      	adds	r3, #8
- 8005bca:	81fb      	strh	r3, [r7, #14]
-    if (lfree == mem2) {
- 8005bcc:	4b40      	ldr	r3, [pc, #256]	; (8005cd0 <mem_trim+0x208>)
- 8005bce:	681b      	ldr	r3, [r3, #0]
- 8005bd0:	693a      	ldr	r2, [r7, #16]
- 8005bd2:	429a      	cmp	r2, r3
- 8005bd4:	d106      	bne.n	8005be4 <mem_trim+0x11c>
-      lfree = ptr_to_mem(ptr2);
- 8005bd6:	89fb      	ldrh	r3, [r7, #14]
- 8005bd8:	4618      	mov	r0, r3
- 8005bda:	f7ff fdb7 	bl	800574c <ptr_to_mem>
- 8005bde:	4603      	mov	r3, r0
- 8005be0:	4a3b      	ldr	r2, [pc, #236]	; (8005cd0 <mem_trim+0x208>)
- 8005be2:	6013      	str	r3, [r2, #0]
-    }
-    mem2 = ptr_to_mem(ptr2);
- 8005be4:	89fb      	ldrh	r3, [r7, #14]
- 8005be6:	4618      	mov	r0, r3
- 8005be8:	f7ff fdb0 	bl	800574c <ptr_to_mem>
- 8005bec:	6138      	str	r0, [r7, #16]
-    mem2->used = 0;
- 8005bee:	693b      	ldr	r3, [r7, #16]
- 8005bf0:	2200      	movs	r2, #0
- 8005bf2:	711a      	strb	r2, [r3, #4]
-    /* restore the next pointer */
-    mem2->next = next;
- 8005bf4:	693b      	ldr	r3, [r7, #16]
- 8005bf6:	89ba      	ldrh	r2, [r7, #12]
- 8005bf8:	801a      	strh	r2, [r3, #0]
-    /* link it back to mem */
-    mem2->prev = ptr;
- 8005bfa:	693b      	ldr	r3, [r7, #16]
- 8005bfc:	8afa      	ldrh	r2, [r7, #22]
- 8005bfe:	805a      	strh	r2, [r3, #2]
-    /* link mem to it */
-    mem->next = ptr2;
- 8005c00:	69bb      	ldr	r3, [r7, #24]
- 8005c02:	89fa      	ldrh	r2, [r7, #14]
- 8005c04:	801a      	strh	r2, [r3, #0]
-    /* last thing to restore linked list: as we have moved mem2,
-     * let 'mem2->next->prev' point to mem2 again. but only if mem2->next is not
-     * the end of the heap */
-    if (mem2->next != MEM_SIZE_ALIGNED) {
- 8005c06:	693b      	ldr	r3, [r7, #16]
- 8005c08:	881b      	ldrh	r3, [r3, #0]
- 8005c0a:	f647 52e8 	movw	r2, #32232	; 0x7de8
- 8005c0e:	4293      	cmp	r3, r2
- 8005c10:	d049      	beq.n	8005ca6 <mem_trim+0x1de>
-      ptr_to_mem(mem2->next)->prev = ptr2;
- 8005c12:	693b      	ldr	r3, [r7, #16]
- 8005c14:	881b      	ldrh	r3, [r3, #0]
- 8005c16:	4618      	mov	r0, r3
- 8005c18:	f7ff fd98 	bl	800574c <ptr_to_mem>
- 8005c1c:	4602      	mov	r2, r0
- 8005c1e:	89fb      	ldrh	r3, [r7, #14]
- 8005c20:	8053      	strh	r3, [r2, #2]
- 8005c22:	e040      	b.n	8005ca6 <mem_trim+0x1de>
-    }
-    MEM_STATS_DEC_USED(used, (size - newsize));
-    /* no need to plug holes, we've already done that */
-  } else if (newsize + SIZEOF_STRUCT_MEM + MIN_SIZE_ALIGNED <= size) {
- 8005c24:	8bfb      	ldrh	r3, [r7, #30]
- 8005c26:	f103 0214 	add.w	r2, r3, #20
- 8005c2a:	8abb      	ldrh	r3, [r7, #20]
- 8005c2c:	429a      	cmp	r2, r3
- 8005c2e:	d83a      	bhi.n	8005ca6 <mem_trim+0x1de>
-     * Old size ('size') must be big enough to contain at least 'newsize' plus a struct mem
-     * ('SIZEOF_STRUCT_MEM') with some data ('MIN_SIZE_ALIGNED').
-     * @todo we could leave out MIN_SIZE_ALIGNED. We would create an empty
-     *       region that couldn't hold data, but when mem->next gets freed,
-     *       the 2 regions would be combined, resulting in more free memory */
-    ptr2 = (mem_size_t)(ptr + SIZEOF_STRUCT_MEM + newsize);
- 8005c30:	8afa      	ldrh	r2, [r7, #22]
- 8005c32:	8bfb      	ldrh	r3, [r7, #30]
- 8005c34:	4413      	add	r3, r2
- 8005c36:	b29b      	uxth	r3, r3
- 8005c38:	3308      	adds	r3, #8
- 8005c3a:	81fb      	strh	r3, [r7, #14]
-    LWIP_ASSERT("invalid next ptr", mem->next != MEM_SIZE_ALIGNED);
- 8005c3c:	69bb      	ldr	r3, [r7, #24]
- 8005c3e:	881b      	ldrh	r3, [r3, #0]
- 8005c40:	f647 52e8 	movw	r2, #32232	; 0x7de8
- 8005c44:	4293      	cmp	r3, r2
- 8005c46:	d106      	bne.n	8005c56 <mem_trim+0x18e>
- 8005c48:	4b1b      	ldr	r3, [pc, #108]	; (8005cb8 <mem_trim+0x1f0>)
- 8005c4a:	f240 3216 	movw	r2, #790	; 0x316
- 8005c4e:	491f      	ldr	r1, [pc, #124]	; (8005ccc <mem_trim+0x204>)
- 8005c50:	481b      	ldr	r0, [pc, #108]	; (8005cc0 <mem_trim+0x1f8>)
- 8005c52:	f00a ffb9 	bl	8010bc8 <iprintf>
-    mem2 = ptr_to_mem(ptr2);
- 8005c56:	89fb      	ldrh	r3, [r7, #14]
- 8005c58:	4618      	mov	r0, r3
- 8005c5a:	f7ff fd77 	bl	800574c <ptr_to_mem>
- 8005c5e:	6138      	str	r0, [r7, #16]
-    if (mem2 < lfree) {
- 8005c60:	4b1b      	ldr	r3, [pc, #108]	; (8005cd0 <mem_trim+0x208>)
- 8005c62:	681b      	ldr	r3, [r3, #0]
- 8005c64:	693a      	ldr	r2, [r7, #16]
- 8005c66:	429a      	cmp	r2, r3
- 8005c68:	d202      	bcs.n	8005c70 <mem_trim+0x1a8>
-      lfree = mem2;
- 8005c6a:	4a19      	ldr	r2, [pc, #100]	; (8005cd0 <mem_trim+0x208>)
- 8005c6c:	693b      	ldr	r3, [r7, #16]
- 8005c6e:	6013      	str	r3, [r2, #0]
-    }
-    mem2->used = 0;
- 8005c70:	693b      	ldr	r3, [r7, #16]
- 8005c72:	2200      	movs	r2, #0
- 8005c74:	711a      	strb	r2, [r3, #4]
-    mem2->next = mem->next;
- 8005c76:	69bb      	ldr	r3, [r7, #24]
- 8005c78:	881a      	ldrh	r2, [r3, #0]
- 8005c7a:	693b      	ldr	r3, [r7, #16]
- 8005c7c:	801a      	strh	r2, [r3, #0]
-    mem2->prev = ptr;
- 8005c7e:	693b      	ldr	r3, [r7, #16]
- 8005c80:	8afa      	ldrh	r2, [r7, #22]
- 8005c82:	805a      	strh	r2, [r3, #2]
-    mem->next = ptr2;
- 8005c84:	69bb      	ldr	r3, [r7, #24]
- 8005c86:	89fa      	ldrh	r2, [r7, #14]
- 8005c88:	801a      	strh	r2, [r3, #0]
-    if (mem2->next != MEM_SIZE_ALIGNED) {
- 8005c8a:	693b      	ldr	r3, [r7, #16]
- 8005c8c:	881b      	ldrh	r3, [r3, #0]
- 8005c8e:	f647 52e8 	movw	r2, #32232	; 0x7de8
- 8005c92:	4293      	cmp	r3, r2
- 8005c94:	d007      	beq.n	8005ca6 <mem_trim+0x1de>
-      ptr_to_mem(mem2->next)->prev = ptr2;
- 8005c96:	693b      	ldr	r3, [r7, #16]
- 8005c98:	881b      	ldrh	r3, [r3, #0]
- 8005c9a:	4618      	mov	r0, r3
- 8005c9c:	f7ff fd56 	bl	800574c <ptr_to_mem>
- 8005ca0:	4602      	mov	r2, r0
- 8005ca2:	89fb      	ldrh	r3, [r7, #14]
- 8005ca4:	8053      	strh	r3, [r2, #2]
-  MEM_SANITY();
-#if LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT
-  mem_free_count = 1;
-#endif /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */
-  LWIP_MEM_FREE_UNPROTECT();
-  return rmem;
- 8005ca6:	687b      	ldr	r3, [r7, #4]
-}
- 8005ca8:	4618      	mov	r0, r3
- 8005caa:	3720      	adds	r7, #32
- 8005cac:	46bd      	mov	sp, r7
- 8005cae:	bd80      	pop	{r7, pc}
- 8005cb0:	24004c28 	.word	0x24004c28
- 8005cb4:	24004c2c 	.word	0x24004c2c
- 8005cb8:	08011ca0 	.word	0x08011ca0
- 8005cbc:	08011e8c 	.word	0x08011e8c
- 8005cc0:	08011ce8 	.word	0x08011ce8
- 8005cc4:	08011ea4 	.word	0x08011ea4
- 8005cc8:	08011ec0 	.word	0x08011ec0
- 8005ccc:	08011ee0 	.word	0x08011ee0
- 8005cd0:	24004c30 	.word	0x24004c30
-
-08005cd4 <mem_malloc>:
- *
- * Note that the returned value will always be aligned (as defined by MEM_ALIGNMENT).
- */
-void *
-mem_malloc(mem_size_t size_in)
-{
- 8005cd4:	b580      	push	{r7, lr}
- 8005cd6:	b088      	sub	sp, #32
- 8005cd8:	af00      	add	r7, sp, #0
- 8005cda:	4603      	mov	r3, r0
- 8005cdc:	80fb      	strh	r3, [r7, #6]
-#if LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT
-  u8_t local_mem_free_count = 0;
-#endif /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */
-  LWIP_MEM_ALLOC_DECL_PROTECT();
-
-  if (size_in == 0) {
- 8005cde:	88fb      	ldrh	r3, [r7, #6]
- 8005ce0:	2b00      	cmp	r3, #0
- 8005ce2:	d101      	bne.n	8005ce8 <mem_malloc+0x14>
-    return NULL;
- 8005ce4:	2300      	movs	r3, #0
- 8005ce6:	e0e3      	b.n	8005eb0 <mem_malloc+0x1dc>
-  }
-
-  /* Expand the size of the allocated memory region so that we can
-     adjust for alignment. */
-  size = (mem_size_t)LWIP_MEM_ALIGN_SIZE(size_in);
- 8005ce8:	88fb      	ldrh	r3, [r7, #6]
- 8005cea:	3303      	adds	r3, #3
- 8005cec:	b29b      	uxth	r3, r3
- 8005cee:	f023 0303 	bic.w	r3, r3, #3
- 8005cf2:	83bb      	strh	r3, [r7, #28]
-  if (size < MIN_SIZE_ALIGNED) {
- 8005cf4:	8bbb      	ldrh	r3, [r7, #28]
- 8005cf6:	2b0b      	cmp	r3, #11
- 8005cf8:	d801      	bhi.n	8005cfe <mem_malloc+0x2a>
-    /* every data block must be at least MIN_SIZE_ALIGNED long */
-    size = MIN_SIZE_ALIGNED;
- 8005cfa:	230c      	movs	r3, #12
- 8005cfc:	83bb      	strh	r3, [r7, #28]
-  }
-#if MEM_OVERFLOW_CHECK
-  size += MEM_SANITY_REGION_BEFORE_ALIGNED + MEM_SANITY_REGION_AFTER_ALIGNED;
-#endif
-  if ((size > MEM_SIZE_ALIGNED) || (size < size_in)) {
- 8005cfe:	8bbb      	ldrh	r3, [r7, #28]
- 8005d00:	f647 52e8 	movw	r2, #32232	; 0x7de8
- 8005d04:	4293      	cmp	r3, r2
- 8005d06:	d803      	bhi.n	8005d10 <mem_malloc+0x3c>
- 8005d08:	8bba      	ldrh	r2, [r7, #28]
- 8005d0a:	88fb      	ldrh	r3, [r7, #6]
- 8005d0c:	429a      	cmp	r2, r3
- 8005d0e:	d201      	bcs.n	8005d14 <mem_malloc+0x40>
-    return NULL;
- 8005d10:	2300      	movs	r3, #0
- 8005d12:	e0cd      	b.n	8005eb0 <mem_malloc+0x1dc>
-#endif /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */
-
-    /* Scan through the heap searching for a free block that is big enough,
-     * beginning with the lowest free block.
-     */
-    for (ptr = mem_to_ptr(lfree); ptr < MEM_SIZE_ALIGNED - size;
- 8005d14:	4b68      	ldr	r3, [pc, #416]	; (8005eb8 <mem_malloc+0x1e4>)
- 8005d16:	681b      	ldr	r3, [r3, #0]
- 8005d18:	4618      	mov	r0, r3
- 8005d1a:	f7ff fd29 	bl	8005770 <mem_to_ptr>
- 8005d1e:	4603      	mov	r3, r0
- 8005d20:	83fb      	strh	r3, [r7, #30]
- 8005d22:	e0b6      	b.n	8005e92 <mem_malloc+0x1be>
-         ptr = ptr_to_mem(ptr)->next) {
-      mem = ptr_to_mem(ptr);
- 8005d24:	8bfb      	ldrh	r3, [r7, #30]
- 8005d26:	4618      	mov	r0, r3
- 8005d28:	f7ff fd10 	bl	800574c <ptr_to_mem>
- 8005d2c:	6178      	str	r0, [r7, #20]
-        local_mem_free_count = 1;
-        break;
-      }
-#endif /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */
-
-      if ((!mem->used) &&
- 8005d2e:	697b      	ldr	r3, [r7, #20]
- 8005d30:	791b      	ldrb	r3, [r3, #4]
- 8005d32:	2b00      	cmp	r3, #0
- 8005d34:	f040 80a6 	bne.w	8005e84 <mem_malloc+0x1b0>
-          (mem->next - (ptr + SIZEOF_STRUCT_MEM)) >= size) {
- 8005d38:	697b      	ldr	r3, [r7, #20]
- 8005d3a:	881b      	ldrh	r3, [r3, #0]
- 8005d3c:	461a      	mov	r2, r3
- 8005d3e:	8bfb      	ldrh	r3, [r7, #30]
- 8005d40:	1ad3      	subs	r3, r2, r3
- 8005d42:	f1a3 0208 	sub.w	r2, r3, #8
- 8005d46:	8bbb      	ldrh	r3, [r7, #28]
-      if ((!mem->used) &&
- 8005d48:	429a      	cmp	r2, r3
- 8005d4a:	f0c0 809b 	bcc.w	8005e84 <mem_malloc+0x1b0>
-        /* mem is not used and at least perfect fit is possible:
-         * mem->next - (ptr + SIZEOF_STRUCT_MEM) gives us the 'user data size' of mem */
-
-        if (mem->next - (ptr + SIZEOF_STRUCT_MEM) >= (size + SIZEOF_STRUCT_MEM + MIN_SIZE_ALIGNED)) {
- 8005d4e:	697b      	ldr	r3, [r7, #20]
- 8005d50:	881b      	ldrh	r3, [r3, #0]
- 8005d52:	461a      	mov	r2, r3
- 8005d54:	8bfb      	ldrh	r3, [r7, #30]
- 8005d56:	1ad3      	subs	r3, r2, r3
- 8005d58:	f1a3 0208 	sub.w	r2, r3, #8
- 8005d5c:	8bbb      	ldrh	r3, [r7, #28]
- 8005d5e:	3314      	adds	r3, #20
- 8005d60:	429a      	cmp	r2, r3
- 8005d62:	d335      	bcc.n	8005dd0 <mem_malloc+0xfc>
-           * struct mem would fit in but no data between mem2 and mem2->next
-           * @todo we could leave out MIN_SIZE_ALIGNED. We would create an empty
-           *       region that couldn't hold data, but when mem->next gets freed,
-           *       the 2 regions would be combined, resulting in more free memory
-           */
-          ptr2 = (mem_size_t)(ptr + SIZEOF_STRUCT_MEM + size);
- 8005d64:	8bfa      	ldrh	r2, [r7, #30]
- 8005d66:	8bbb      	ldrh	r3, [r7, #28]
- 8005d68:	4413      	add	r3, r2
- 8005d6a:	b29b      	uxth	r3, r3
- 8005d6c:	3308      	adds	r3, #8
- 8005d6e:	827b      	strh	r3, [r7, #18]
-          LWIP_ASSERT("invalid next ptr",ptr2 != MEM_SIZE_ALIGNED);
- 8005d70:	8a7b      	ldrh	r3, [r7, #18]
- 8005d72:	f647 52e8 	movw	r2, #32232	; 0x7de8
- 8005d76:	4293      	cmp	r3, r2
- 8005d78:	d106      	bne.n	8005d88 <mem_malloc+0xb4>
- 8005d7a:	4b50      	ldr	r3, [pc, #320]	; (8005ebc <mem_malloc+0x1e8>)
- 8005d7c:	f240 3287 	movw	r2, #903	; 0x387
- 8005d80:	494f      	ldr	r1, [pc, #316]	; (8005ec0 <mem_malloc+0x1ec>)
- 8005d82:	4850      	ldr	r0, [pc, #320]	; (8005ec4 <mem_malloc+0x1f0>)
- 8005d84:	f00a ff20 	bl	8010bc8 <iprintf>
-          /* create mem2 struct */
-          mem2 = ptr_to_mem(ptr2);
- 8005d88:	8a7b      	ldrh	r3, [r7, #18]
- 8005d8a:	4618      	mov	r0, r3
- 8005d8c:	f7ff fcde 	bl	800574c <ptr_to_mem>
- 8005d90:	60f8      	str	r0, [r7, #12]
-          mem2->used = 0;
- 8005d92:	68fb      	ldr	r3, [r7, #12]
- 8005d94:	2200      	movs	r2, #0
- 8005d96:	711a      	strb	r2, [r3, #4]
-          mem2->next = mem->next;
- 8005d98:	697b      	ldr	r3, [r7, #20]
- 8005d9a:	881a      	ldrh	r2, [r3, #0]
- 8005d9c:	68fb      	ldr	r3, [r7, #12]
- 8005d9e:	801a      	strh	r2, [r3, #0]
-          mem2->prev = ptr;
- 8005da0:	68fb      	ldr	r3, [r7, #12]
- 8005da2:	8bfa      	ldrh	r2, [r7, #30]
- 8005da4:	805a      	strh	r2, [r3, #2]
-          /* and insert it between mem and mem->next */
-          mem->next = ptr2;
- 8005da6:	697b      	ldr	r3, [r7, #20]
- 8005da8:	8a7a      	ldrh	r2, [r7, #18]
- 8005daa:	801a      	strh	r2, [r3, #0]
-          mem->used = 1;
- 8005dac:	697b      	ldr	r3, [r7, #20]
- 8005dae:	2201      	movs	r2, #1
- 8005db0:	711a      	strb	r2, [r3, #4]
-
-          if (mem2->next != MEM_SIZE_ALIGNED) {
- 8005db2:	68fb      	ldr	r3, [r7, #12]
- 8005db4:	881b      	ldrh	r3, [r3, #0]
- 8005db6:	f647 52e8 	movw	r2, #32232	; 0x7de8
- 8005dba:	4293      	cmp	r3, r2
- 8005dbc:	d00b      	beq.n	8005dd6 <mem_malloc+0x102>
-            ptr_to_mem(mem2->next)->prev = ptr2;
- 8005dbe:	68fb      	ldr	r3, [r7, #12]
- 8005dc0:	881b      	ldrh	r3, [r3, #0]
- 8005dc2:	4618      	mov	r0, r3
- 8005dc4:	f7ff fcc2 	bl	800574c <ptr_to_mem>
- 8005dc8:	4602      	mov	r2, r0
- 8005dca:	8a7b      	ldrh	r3, [r7, #18]
- 8005dcc:	8053      	strh	r3, [r2, #2]
- 8005dce:	e002      	b.n	8005dd6 <mem_malloc+0x102>
-           * take care of this).
-           * -> near fit or exact fit: do not split, no mem2 creation
-           * also can't move mem->next directly behind mem, since mem->next
-           * will always be used at this point!
-           */
-          mem->used = 1;
- 8005dd0:	697b      	ldr	r3, [r7, #20]
- 8005dd2:	2201      	movs	r2, #1
- 8005dd4:	711a      	strb	r2, [r3, #4]
-          MEM_STATS_INC_USED(used, mem->next - mem_to_ptr(mem));
-        }
-#if LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT
-mem_malloc_adjust_lfree:
-#endif /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */
-        if (mem == lfree) {
- 8005dd6:	4b38      	ldr	r3, [pc, #224]	; (8005eb8 <mem_malloc+0x1e4>)
- 8005dd8:	681b      	ldr	r3, [r3, #0]
- 8005dda:	697a      	ldr	r2, [r7, #20]
- 8005ddc:	429a      	cmp	r2, r3
- 8005dde:	d127      	bne.n	8005e30 <mem_malloc+0x15c>
-          struct mem *cur = lfree;
- 8005de0:	4b35      	ldr	r3, [pc, #212]	; (8005eb8 <mem_malloc+0x1e4>)
- 8005de2:	681b      	ldr	r3, [r3, #0]
- 8005de4:	61bb      	str	r3, [r7, #24]
-          /* Find next free block after mem and update lowest free pointer */
-          while (cur->used && cur != ram_end) {
- 8005de6:	e005      	b.n	8005df4 <mem_malloc+0x120>
-              /* If mem_free or mem_trim have run, we have to restart since they
-                 could have altered our current struct mem or lfree. */
-              goto mem_malloc_adjust_lfree;
-            }
-#endif /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */
-            cur = ptr_to_mem(cur->next);
- 8005de8:	69bb      	ldr	r3, [r7, #24]
- 8005dea:	881b      	ldrh	r3, [r3, #0]
- 8005dec:	4618      	mov	r0, r3
- 8005dee:	f7ff fcad 	bl	800574c <ptr_to_mem>
- 8005df2:	61b8      	str	r0, [r7, #24]
-          while (cur->used && cur != ram_end) {
- 8005df4:	69bb      	ldr	r3, [r7, #24]
- 8005df6:	791b      	ldrb	r3, [r3, #4]
- 8005df8:	2b00      	cmp	r3, #0
- 8005dfa:	d004      	beq.n	8005e06 <mem_malloc+0x132>
- 8005dfc:	4b32      	ldr	r3, [pc, #200]	; (8005ec8 <mem_malloc+0x1f4>)
- 8005dfe:	681b      	ldr	r3, [r3, #0]
- 8005e00:	69ba      	ldr	r2, [r7, #24]
- 8005e02:	429a      	cmp	r2, r3
- 8005e04:	d1f0      	bne.n	8005de8 <mem_malloc+0x114>
-          }
-          lfree = cur;
- 8005e06:	4a2c      	ldr	r2, [pc, #176]	; (8005eb8 <mem_malloc+0x1e4>)
- 8005e08:	69bb      	ldr	r3, [r7, #24]
- 8005e0a:	6013      	str	r3, [r2, #0]
-          LWIP_ASSERT("mem_malloc: !lfree->used", ((lfree == ram_end) || (!lfree->used)));
- 8005e0c:	4b2a      	ldr	r3, [pc, #168]	; (8005eb8 <mem_malloc+0x1e4>)
- 8005e0e:	681a      	ldr	r2, [r3, #0]
- 8005e10:	4b2d      	ldr	r3, [pc, #180]	; (8005ec8 <mem_malloc+0x1f4>)
- 8005e12:	681b      	ldr	r3, [r3, #0]
- 8005e14:	429a      	cmp	r2, r3
- 8005e16:	d00b      	beq.n	8005e30 <mem_malloc+0x15c>
- 8005e18:	4b27      	ldr	r3, [pc, #156]	; (8005eb8 <mem_malloc+0x1e4>)
- 8005e1a:	681b      	ldr	r3, [r3, #0]
- 8005e1c:	791b      	ldrb	r3, [r3, #4]
- 8005e1e:	2b00      	cmp	r3, #0
- 8005e20:	d006      	beq.n	8005e30 <mem_malloc+0x15c>
- 8005e22:	4b26      	ldr	r3, [pc, #152]	; (8005ebc <mem_malloc+0x1e8>)
- 8005e24:	f240 32b5 	movw	r2, #949	; 0x3b5
- 8005e28:	4928      	ldr	r1, [pc, #160]	; (8005ecc <mem_malloc+0x1f8>)
- 8005e2a:	4826      	ldr	r0, [pc, #152]	; (8005ec4 <mem_malloc+0x1f0>)
- 8005e2c:	f00a fecc 	bl	8010bc8 <iprintf>
-        }
-        LWIP_MEM_ALLOC_UNPROTECT();
-        sys_mutex_unlock(&mem_mutex);
-        LWIP_ASSERT("mem_malloc: allocated memory not above ram_end.",
- 8005e30:	8bba      	ldrh	r2, [r7, #28]
- 8005e32:	697b      	ldr	r3, [r7, #20]
- 8005e34:	4413      	add	r3, r2
- 8005e36:	3308      	adds	r3, #8
- 8005e38:	4a23      	ldr	r2, [pc, #140]	; (8005ec8 <mem_malloc+0x1f4>)
- 8005e3a:	6812      	ldr	r2, [r2, #0]
- 8005e3c:	4293      	cmp	r3, r2
- 8005e3e:	d906      	bls.n	8005e4e <mem_malloc+0x17a>
- 8005e40:	4b1e      	ldr	r3, [pc, #120]	; (8005ebc <mem_malloc+0x1e8>)
- 8005e42:	f240 32b9 	movw	r2, #953	; 0x3b9
- 8005e46:	4922      	ldr	r1, [pc, #136]	; (8005ed0 <mem_malloc+0x1fc>)
- 8005e48:	481e      	ldr	r0, [pc, #120]	; (8005ec4 <mem_malloc+0x1f0>)
- 8005e4a:	f00a febd 	bl	8010bc8 <iprintf>
-                    (mem_ptr_t)mem + SIZEOF_STRUCT_MEM + size <= (mem_ptr_t)ram_end);
-        LWIP_ASSERT("mem_malloc: allocated memory properly aligned.",
- 8005e4e:	697b      	ldr	r3, [r7, #20]
- 8005e50:	f003 0303 	and.w	r3, r3, #3
- 8005e54:	2b00      	cmp	r3, #0
- 8005e56:	d006      	beq.n	8005e66 <mem_malloc+0x192>
- 8005e58:	4b18      	ldr	r3, [pc, #96]	; (8005ebc <mem_malloc+0x1e8>)
- 8005e5a:	f240 32bb 	movw	r2, #955	; 0x3bb
- 8005e5e:	491d      	ldr	r1, [pc, #116]	; (8005ed4 <mem_malloc+0x200>)
- 8005e60:	4818      	ldr	r0, [pc, #96]	; (8005ec4 <mem_malloc+0x1f0>)
- 8005e62:	f00a feb1 	bl	8010bc8 <iprintf>
-                    ((mem_ptr_t)mem + SIZEOF_STRUCT_MEM) % MEM_ALIGNMENT == 0);
-        LWIP_ASSERT("mem_malloc: sanity check alignment",
- 8005e66:	697b      	ldr	r3, [r7, #20]
- 8005e68:	f003 0303 	and.w	r3, r3, #3
- 8005e6c:	2b00      	cmp	r3, #0
- 8005e6e:	d006      	beq.n	8005e7e <mem_malloc+0x1aa>
- 8005e70:	4b12      	ldr	r3, [pc, #72]	; (8005ebc <mem_malloc+0x1e8>)
- 8005e72:	f240 32bd 	movw	r2, #957	; 0x3bd
- 8005e76:	4918      	ldr	r1, [pc, #96]	; (8005ed8 <mem_malloc+0x204>)
- 8005e78:	4812      	ldr	r0, [pc, #72]	; (8005ec4 <mem_malloc+0x1f0>)
- 8005e7a:	f00a fea5 	bl	8010bc8 <iprintf>
-
-#if MEM_OVERFLOW_CHECK
-        mem_overflow_init_element(mem, size_in);
-#endif
-        MEM_SANITY();
-        return (u8_t *)mem + SIZEOF_STRUCT_MEM + MEM_SANITY_OFFSET;
- 8005e7e:	697b      	ldr	r3, [r7, #20]
- 8005e80:	3308      	adds	r3, #8
- 8005e82:	e015      	b.n	8005eb0 <mem_malloc+0x1dc>
-         ptr = ptr_to_mem(ptr)->next) {
- 8005e84:	8bfb      	ldrh	r3, [r7, #30]
- 8005e86:	4618      	mov	r0, r3
- 8005e88:	f7ff fc60 	bl	800574c <ptr_to_mem>
- 8005e8c:	4603      	mov	r3, r0
- 8005e8e:	881b      	ldrh	r3, [r3, #0]
- 8005e90:	83fb      	strh	r3, [r7, #30]
-    for (ptr = mem_to_ptr(lfree); ptr < MEM_SIZE_ALIGNED - size;
- 8005e92:	8bfa      	ldrh	r2, [r7, #30]
- 8005e94:	8bb9      	ldrh	r1, [r7, #28]
- 8005e96:	f647 53e8 	movw	r3, #32232	; 0x7de8
- 8005e9a:	1a5b      	subs	r3, r3, r1
- 8005e9c:	429a      	cmp	r2, r3
- 8005e9e:	f4ff af41 	bcc.w	8005d24 <mem_malloc+0x50>
-  } while (local_mem_free_count != 0);
-#endif /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */
-  MEM_STATS_INC(err);
-  LWIP_MEM_ALLOC_UNPROTECT();
-  sys_mutex_unlock(&mem_mutex);
-  LWIP_DEBUGF(MEM_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("mem_malloc: could not allocate %"S16_F" bytes\n", (s16_t)size));
- 8005ea2:	f9b7 301c 	ldrsh.w	r3, [r7, #28]
- 8005ea6:	4619      	mov	r1, r3
- 8005ea8:	480c      	ldr	r0, [pc, #48]	; (8005edc <mem_malloc+0x208>)
- 8005eaa:	f00a fe8d 	bl	8010bc8 <iprintf>
-  return NULL;
- 8005eae:	2300      	movs	r3, #0
-}
- 8005eb0:	4618      	mov	r0, r3
- 8005eb2:	3720      	adds	r7, #32
- 8005eb4:	46bd      	mov	sp, r7
- 8005eb6:	bd80      	pop	{r7, pc}
- 8005eb8:	24004c30 	.word	0x24004c30
- 8005ebc:	08011ca0 	.word	0x08011ca0
- 8005ec0:	08011ee0 	.word	0x08011ee0
- 8005ec4:	08011ce8 	.word	0x08011ce8
- 8005ec8:	24004c2c 	.word	0x24004c2c
- 8005ecc:	08011ef4 	.word	0x08011ef4
- 8005ed0:	08011f10 	.word	0x08011f10
- 8005ed4:	08011f40 	.word	0x08011f40
- 8005ed8:	08011f70 	.word	0x08011f70
- 8005edc:	08011f94 	.word	0x08011f94
-
-08005ee0 <memp_init_pool>:
- *
- * @param desc pool to initialize
- */
-void
-memp_init_pool(const struct memp_desc *desc)
-{
- 8005ee0:	b480      	push	{r7}
- 8005ee2:	b085      	sub	sp, #20
- 8005ee4:	af00      	add	r7, sp, #0
- 8005ee6:	6078      	str	r0, [r7, #4]
-  LWIP_UNUSED_ARG(desc);
-#else
-  int i;
-  struct memp *memp;
-
-  *desc->tab = NULL;
- 8005ee8:	687b      	ldr	r3, [r7, #4]
- 8005eea:	68db      	ldr	r3, [r3, #12]
- 8005eec:	2200      	movs	r2, #0
- 8005eee:	601a      	str	r2, [r3, #0]
-  memp = (struct memp *)LWIP_MEM_ALIGN(desc->base);
- 8005ef0:	687b      	ldr	r3, [r7, #4]
- 8005ef2:	689b      	ldr	r3, [r3, #8]
- 8005ef4:	3303      	adds	r3, #3
- 8005ef6:	f023 0303 	bic.w	r3, r3, #3
- 8005efa:	60bb      	str	r3, [r7, #8]
-                                       + MEM_SANITY_REGION_AFTER_ALIGNED
-#endif
-                                      ));
-#endif
-  /* create a linked list of memp elements */
-  for (i = 0; i < desc->num; ++i) {
- 8005efc:	2300      	movs	r3, #0
- 8005efe:	60fb      	str	r3, [r7, #12]
- 8005f00:	e011      	b.n	8005f26 <memp_init_pool+0x46>
-    memp->next = *desc->tab;
- 8005f02:	687b      	ldr	r3, [r7, #4]
- 8005f04:	68db      	ldr	r3, [r3, #12]
- 8005f06:	681a      	ldr	r2, [r3, #0]
- 8005f08:	68bb      	ldr	r3, [r7, #8]
- 8005f0a:	601a      	str	r2, [r3, #0]
-    *desc->tab = memp;
- 8005f0c:	687b      	ldr	r3, [r7, #4]
- 8005f0e:	68db      	ldr	r3, [r3, #12]
- 8005f10:	68ba      	ldr	r2, [r7, #8]
- 8005f12:	601a      	str	r2, [r3, #0]
-#if MEMP_OVERFLOW_CHECK
-    memp_overflow_init_element(memp, desc);
-#endif /* MEMP_OVERFLOW_CHECK */
-    /* cast through void* to get rid of alignment warnings */
-    memp = (struct memp *)(void *)((u8_t *)memp + MEMP_SIZE + desc->size
- 8005f14:	687b      	ldr	r3, [r7, #4]
- 8005f16:	889b      	ldrh	r3, [r3, #4]
- 8005f18:	461a      	mov	r2, r3
- 8005f1a:	68bb      	ldr	r3, [r7, #8]
- 8005f1c:	4413      	add	r3, r2
- 8005f1e:	60bb      	str	r3, [r7, #8]
-  for (i = 0; i < desc->num; ++i) {
- 8005f20:	68fb      	ldr	r3, [r7, #12]
- 8005f22:	3301      	adds	r3, #1
- 8005f24:	60fb      	str	r3, [r7, #12]
- 8005f26:	687b      	ldr	r3, [r7, #4]
- 8005f28:	88db      	ldrh	r3, [r3, #6]
- 8005f2a:	461a      	mov	r2, r3
- 8005f2c:	68fb      	ldr	r3, [r7, #12]
- 8005f2e:	4293      	cmp	r3, r2
- 8005f30:	dbe7      	blt.n	8005f02 <memp_init_pool+0x22>
-#endif /* !MEMP_MEM_MALLOC */
-
-#if MEMP_STATS && (defined(LWIP_DEBUG) || LWIP_STATS_DISPLAY)
-  desc->stats->name  = desc->desc;
-#endif /* MEMP_STATS && (defined(LWIP_DEBUG) || LWIP_STATS_DISPLAY) */
-}
- 8005f32:	bf00      	nop
- 8005f34:	bf00      	nop
- 8005f36:	3714      	adds	r7, #20
- 8005f38:	46bd      	mov	sp, r7
- 8005f3a:	f85d 7b04 	ldr.w	r7, [sp], #4
- 8005f3e:	4770      	bx	lr
-
-08005f40 <memp_init>:
- *
- * Carves out memp_memory into linked lists for each pool-type.
- */
-void
-memp_init(void)
-{
- 8005f40:	b580      	push	{r7, lr}
- 8005f42:	b082      	sub	sp, #8
- 8005f44:	af00      	add	r7, sp, #0
-  u16_t i;
-
-  /* for every pool: */
-  for (i = 0; i < LWIP_ARRAYSIZE(memp_pools); i++) {
- 8005f46:	2300      	movs	r3, #0
- 8005f48:	80fb      	strh	r3, [r7, #6]
- 8005f4a:	e009      	b.n	8005f60 <memp_init+0x20>
-    memp_init_pool(memp_pools[i]);
- 8005f4c:	88fb      	ldrh	r3, [r7, #6]
- 8005f4e:	4a08      	ldr	r2, [pc, #32]	; (8005f70 <memp_init+0x30>)
- 8005f50:	f852 3023 	ldr.w	r3, [r2, r3, lsl #2]
- 8005f54:	4618      	mov	r0, r3
- 8005f56:	f7ff ffc3 	bl	8005ee0 <memp_init_pool>
-  for (i = 0; i < LWIP_ARRAYSIZE(memp_pools); i++) {
- 8005f5a:	88fb      	ldrh	r3, [r7, #6]
- 8005f5c:	3301      	adds	r3, #1
- 8005f5e:	80fb      	strh	r3, [r7, #6]
- 8005f60:	88fb      	ldrh	r3, [r7, #6]
- 8005f62:	2b08      	cmp	r3, #8
- 8005f64:	d9f2      	bls.n	8005f4c <memp_init+0xc>
-
-#if MEMP_OVERFLOW_CHECK >= 2
-  /* check everything a first time to see if it worked */
-  memp_overflow_check_all();
-#endif /* MEMP_OVERFLOW_CHECK >= 2 */
-}
- 8005f66:	bf00      	nop
- 8005f68:	bf00      	nop
- 8005f6a:	3708      	adds	r7, #8
- 8005f6c:	46bd      	mov	sp, r7
- 8005f6e:	bd80      	pop	{r7, pc}
- 8005f70:	08014d30 	.word	0x08014d30
-
-08005f74 <do_memp_malloc_pool>:
-#if !MEMP_OVERFLOW_CHECK
-do_memp_malloc_pool(const struct memp_desc *desc)
-#else
-do_memp_malloc_pool_fn(const struct memp_desc *desc, const char *file, const int line)
-#endif
-{
- 8005f74:	b580      	push	{r7, lr}
- 8005f76:	b084      	sub	sp, #16
- 8005f78:	af00      	add	r7, sp, #0
- 8005f7a:	6078      	str	r0, [r7, #4]
-  memp = (struct memp *)mem_malloc(MEMP_SIZE + MEMP_ALIGN_SIZE(desc->size));
-  SYS_ARCH_PROTECT(old_level);
-#else /* MEMP_MEM_MALLOC */
-  SYS_ARCH_PROTECT(old_level);
-
-  memp = *desc->tab;
- 8005f7c:	687b      	ldr	r3, [r7, #4]
- 8005f7e:	68db      	ldr	r3, [r3, #12]
- 8005f80:	681b      	ldr	r3, [r3, #0]
- 8005f82:	60fb      	str	r3, [r7, #12]
-#endif /* MEMP_MEM_MALLOC */
-
-  if (memp != NULL) {
- 8005f84:	68fb      	ldr	r3, [r7, #12]
- 8005f86:	2b00      	cmp	r3, #0
- 8005f88:	d012      	beq.n	8005fb0 <do_memp_malloc_pool+0x3c>
-#if !MEMP_MEM_MALLOC
-#if MEMP_OVERFLOW_CHECK == 1
-    memp_overflow_check_element(memp, desc);
-#endif /* MEMP_OVERFLOW_CHECK */
-
-    *desc->tab = memp->next;
- 8005f8a:	687b      	ldr	r3, [r7, #4]
- 8005f8c:	68db      	ldr	r3, [r3, #12]
- 8005f8e:	68fa      	ldr	r2, [r7, #12]
- 8005f90:	6812      	ldr	r2, [r2, #0]
- 8005f92:	601a      	str	r2, [r3, #0]
-    memp->line = line;
-#if MEMP_MEM_MALLOC
-    memp_overflow_init_element(memp, desc);
-#endif /* MEMP_MEM_MALLOC */
-#endif /* MEMP_OVERFLOW_CHECK */
-    LWIP_ASSERT("memp_malloc: memp properly aligned",
- 8005f94:	68fb      	ldr	r3, [r7, #12]
- 8005f96:	f003 0303 	and.w	r3, r3, #3
- 8005f9a:	2b00      	cmp	r3, #0
- 8005f9c:	d006      	beq.n	8005fac <do_memp_malloc_pool+0x38>
- 8005f9e:	4b0a      	ldr	r3, [pc, #40]	; (8005fc8 <do_memp_malloc_pool+0x54>)
- 8005fa0:	f44f 728c 	mov.w	r2, #280	; 0x118
- 8005fa4:	4909      	ldr	r1, [pc, #36]	; (8005fcc <do_memp_malloc_pool+0x58>)
- 8005fa6:	480a      	ldr	r0, [pc, #40]	; (8005fd0 <do_memp_malloc_pool+0x5c>)
- 8005fa8:	f00a fe0e 	bl	8010bc8 <iprintf>
-      desc->stats->max = desc->stats->used;
-    }
-#endif
-    SYS_ARCH_UNPROTECT(old_level);
-    /* cast through u8_t* to get rid of alignment warnings */
-    return ((u8_t *)memp + MEMP_SIZE);
- 8005fac:	68fb      	ldr	r3, [r7, #12]
- 8005fae:	e006      	b.n	8005fbe <do_memp_malloc_pool+0x4a>
-  } else {
-#if MEMP_STATS
-    desc->stats->err++;
-#endif
-    SYS_ARCH_UNPROTECT(old_level);
-    LWIP_DEBUGF(MEMP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("memp_malloc: out of memory in pool %s\n", desc->desc));
- 8005fb0:	687b      	ldr	r3, [r7, #4]
- 8005fb2:	681b      	ldr	r3, [r3, #0]
- 8005fb4:	4619      	mov	r1, r3
- 8005fb6:	4807      	ldr	r0, [pc, #28]	; (8005fd4 <do_memp_malloc_pool+0x60>)
- 8005fb8:	f00a fe06 	bl	8010bc8 <iprintf>
-  }
-
-  return NULL;
- 8005fbc:	2300      	movs	r3, #0
-}
- 8005fbe:	4618      	mov	r0, r3
- 8005fc0:	3710      	adds	r7, #16
- 8005fc2:	46bd      	mov	sp, r7
- 8005fc4:	bd80      	pop	{r7, pc}
- 8005fc6:	bf00      	nop
- 8005fc8:	08012054 	.word	0x08012054
- 8005fcc:	08012084 	.word	0x08012084
- 8005fd0:	080120a8 	.word	0x080120a8
- 8005fd4:	080120d0 	.word	0x080120d0
-
-08005fd8 <memp_malloc_pool>:
-#if !MEMP_OVERFLOW_CHECK
-memp_malloc_pool(const struct memp_desc *desc)
-#else
-memp_malloc_pool_fn(const struct memp_desc *desc, const char *file, const int line)
-#endif
-{
- 8005fd8:	b580      	push	{r7, lr}
- 8005fda:	b082      	sub	sp, #8
- 8005fdc:	af00      	add	r7, sp, #0
- 8005fde:	6078      	str	r0, [r7, #4]
-  LWIP_ASSERT("invalid pool desc", desc != NULL);
- 8005fe0:	687b      	ldr	r3, [r7, #4]
- 8005fe2:	2b00      	cmp	r3, #0
- 8005fe4:	d106      	bne.n	8005ff4 <memp_malloc_pool+0x1c>
- 8005fe6:	4b0a      	ldr	r3, [pc, #40]	; (8006010 <memp_malloc_pool+0x38>)
- 8005fe8:	f44f 729e 	mov.w	r2, #316	; 0x13c
- 8005fec:	4909      	ldr	r1, [pc, #36]	; (8006014 <memp_malloc_pool+0x3c>)
- 8005fee:	480a      	ldr	r0, [pc, #40]	; (8006018 <memp_malloc_pool+0x40>)
- 8005ff0:	f00a fdea 	bl	8010bc8 <iprintf>
-  if (desc == NULL) {
- 8005ff4:	687b      	ldr	r3, [r7, #4]
- 8005ff6:	2b00      	cmp	r3, #0
- 8005ff8:	d101      	bne.n	8005ffe <memp_malloc_pool+0x26>
-    return NULL;
- 8005ffa:	2300      	movs	r3, #0
- 8005ffc:	e003      	b.n	8006006 <memp_malloc_pool+0x2e>
-  }
-
-#if !MEMP_OVERFLOW_CHECK
-  return do_memp_malloc_pool(desc);
- 8005ffe:	6878      	ldr	r0, [r7, #4]
- 8006000:	f7ff ffb8 	bl	8005f74 <do_memp_malloc_pool>
- 8006004:	4603      	mov	r3, r0
-#else
-  return do_memp_malloc_pool_fn(desc, file, line);
-#endif
-}
- 8006006:	4618      	mov	r0, r3
- 8006008:	3708      	adds	r7, #8
- 800600a:	46bd      	mov	sp, r7
- 800600c:	bd80      	pop	{r7, pc}
- 800600e:	bf00      	nop
- 8006010:	08012054 	.word	0x08012054
- 8006014:	080120f8 	.word	0x080120f8
- 8006018:	080120a8 	.word	0x080120a8
-
-0800601c <memp_malloc>:
-#if !MEMP_OVERFLOW_CHECK
-memp_malloc(memp_t type)
-#else
-memp_malloc_fn(memp_t type, const char *file, const int line)
-#endif
-{
- 800601c:	b580      	push	{r7, lr}
- 800601e:	b084      	sub	sp, #16
- 8006020:	af00      	add	r7, sp, #0
- 8006022:	4603      	mov	r3, r0
- 8006024:	71fb      	strb	r3, [r7, #7]
-  void *memp;
-  LWIP_ERROR("memp_malloc: type < MEMP_MAX", (type < MEMP_MAX), return NULL;);
- 8006026:	79fb      	ldrb	r3, [r7, #7]
- 8006028:	2b08      	cmp	r3, #8
- 800602a:	d908      	bls.n	800603e <memp_malloc+0x22>
- 800602c:	4b0a      	ldr	r3, [pc, #40]	; (8006058 <memp_malloc+0x3c>)
- 800602e:	f240 1257 	movw	r2, #343	; 0x157
- 8006032:	490a      	ldr	r1, [pc, #40]	; (800605c <memp_malloc+0x40>)
- 8006034:	480a      	ldr	r0, [pc, #40]	; (8006060 <memp_malloc+0x44>)
- 8006036:	f00a fdc7 	bl	8010bc8 <iprintf>
- 800603a:	2300      	movs	r3, #0
- 800603c:	e008      	b.n	8006050 <memp_malloc+0x34>
-#if MEMP_OVERFLOW_CHECK >= 2
-  memp_overflow_check_all();
-#endif /* MEMP_OVERFLOW_CHECK >= 2 */
-
-#if !MEMP_OVERFLOW_CHECK
-  memp = do_memp_malloc_pool(memp_pools[type]);
- 800603e:	79fb      	ldrb	r3, [r7, #7]
- 8006040:	4a08      	ldr	r2, [pc, #32]	; (8006064 <memp_malloc+0x48>)
- 8006042:	f852 3023 	ldr.w	r3, [r2, r3, lsl #2]
- 8006046:	4618      	mov	r0, r3
- 8006048:	f7ff ff94 	bl	8005f74 <do_memp_malloc_pool>
- 800604c:	60f8      	str	r0, [r7, #12]
-#else
-  memp = do_memp_malloc_pool_fn(memp_pools[type], file, line);
-#endif
-
-  return memp;
- 800604e:	68fb      	ldr	r3, [r7, #12]
-}
- 8006050:	4618      	mov	r0, r3
- 8006052:	3710      	adds	r7, #16
- 8006054:	46bd      	mov	sp, r7
- 8006056:	bd80      	pop	{r7, pc}
- 8006058:	08012054 	.word	0x08012054
- 800605c:	0801210c 	.word	0x0801210c
- 8006060:	080120a8 	.word	0x080120a8
- 8006064:	08014d30 	.word	0x08014d30
-
-08006068 <do_memp_free_pool>:
-
-static void
-do_memp_free_pool(const struct memp_desc *desc, void *mem)
-{
- 8006068:	b580      	push	{r7, lr}
- 800606a:	b084      	sub	sp, #16
- 800606c:	af00      	add	r7, sp, #0
- 800606e:	6078      	str	r0, [r7, #4]
- 8006070:	6039      	str	r1, [r7, #0]
-  struct memp *memp;
-  SYS_ARCH_DECL_PROTECT(old_level);
-
-  LWIP_ASSERT("memp_free: mem properly aligned",
- 8006072:	683b      	ldr	r3, [r7, #0]
- 8006074:	f003 0303 	and.w	r3, r3, #3
- 8006078:	2b00      	cmp	r3, #0
- 800607a:	d006      	beq.n	800608a <do_memp_free_pool+0x22>
- 800607c:	4b0a      	ldr	r3, [pc, #40]	; (80060a8 <do_memp_free_pool+0x40>)
- 800607e:	f44f 72b6 	mov.w	r2, #364	; 0x16c
- 8006082:	490a      	ldr	r1, [pc, #40]	; (80060ac <do_memp_free_pool+0x44>)
- 8006084:	480a      	ldr	r0, [pc, #40]	; (80060b0 <do_memp_free_pool+0x48>)
- 8006086:	f00a fd9f 	bl	8010bc8 <iprintf>
-              ((mem_ptr_t)mem % MEM_ALIGNMENT) == 0);
-
-  /* cast through void* to get rid of alignment warnings */
-  memp = (struct memp *)(void *)((u8_t *)mem - MEMP_SIZE);
- 800608a:	683b      	ldr	r3, [r7, #0]
- 800608c:	60fb      	str	r3, [r7, #12]
-#if MEMP_MEM_MALLOC
-  LWIP_UNUSED_ARG(desc);
-  SYS_ARCH_UNPROTECT(old_level);
-  mem_free(memp);
-#else /* MEMP_MEM_MALLOC */
-  memp->next = *desc->tab;
- 800608e:	687b      	ldr	r3, [r7, #4]
- 8006090:	68db      	ldr	r3, [r3, #12]
- 8006092:	681a      	ldr	r2, [r3, #0]
- 8006094:	68fb      	ldr	r3, [r7, #12]
- 8006096:	601a      	str	r2, [r3, #0]
-  *desc->tab = memp;
- 8006098:	687b      	ldr	r3, [r7, #4]
- 800609a:	68db      	ldr	r3, [r3, #12]
- 800609c:	68fa      	ldr	r2, [r7, #12]
- 800609e:	601a      	str	r2, [r3, #0]
-  LWIP_ASSERT("memp sanity", memp_sanity(desc));
-#endif /* MEMP_SANITY_CHECK */
-
-  SYS_ARCH_UNPROTECT(old_level);
-#endif /* !MEMP_MEM_MALLOC */
-}
- 80060a0:	bf00      	nop
- 80060a2:	3710      	adds	r7, #16
- 80060a4:	46bd      	mov	sp, r7
- 80060a6:	bd80      	pop	{r7, pc}
- 80060a8:	08012054 	.word	0x08012054
- 80060ac:	0801212c 	.word	0x0801212c
- 80060b0:	080120a8 	.word	0x080120a8
-
-080060b4 <memp_free_pool>:
- * @param desc the pool where to put mem
- * @param mem the memp element to free
- */
-void
-memp_free_pool(const struct memp_desc *desc, void *mem)
-{
- 80060b4:	b580      	push	{r7, lr}
- 80060b6:	b082      	sub	sp, #8
- 80060b8:	af00      	add	r7, sp, #0
- 80060ba:	6078      	str	r0, [r7, #4]
- 80060bc:	6039      	str	r1, [r7, #0]
-  LWIP_ASSERT("invalid pool desc", desc != NULL);
- 80060be:	687b      	ldr	r3, [r7, #4]
- 80060c0:	2b00      	cmp	r3, #0
- 80060c2:	d106      	bne.n	80060d2 <memp_free_pool+0x1e>
- 80060c4:	4b0a      	ldr	r3, [pc, #40]	; (80060f0 <memp_free_pool+0x3c>)
- 80060c6:	f240 1295 	movw	r2, #405	; 0x195
- 80060ca:	490a      	ldr	r1, [pc, #40]	; (80060f4 <memp_free_pool+0x40>)
- 80060cc:	480a      	ldr	r0, [pc, #40]	; (80060f8 <memp_free_pool+0x44>)
- 80060ce:	f00a fd7b 	bl	8010bc8 <iprintf>
-  if ((desc == NULL) || (mem == NULL)) {
- 80060d2:	687b      	ldr	r3, [r7, #4]
- 80060d4:	2b00      	cmp	r3, #0
- 80060d6:	d007      	beq.n	80060e8 <memp_free_pool+0x34>
- 80060d8:	683b      	ldr	r3, [r7, #0]
- 80060da:	2b00      	cmp	r3, #0
- 80060dc:	d004      	beq.n	80060e8 <memp_free_pool+0x34>
-    return;
-  }
-
-  do_memp_free_pool(desc, mem);
- 80060de:	6839      	ldr	r1, [r7, #0]
- 80060e0:	6878      	ldr	r0, [r7, #4]
- 80060e2:	f7ff ffc1 	bl	8006068 <do_memp_free_pool>
- 80060e6:	e000      	b.n	80060ea <memp_free_pool+0x36>
-    return;
- 80060e8:	bf00      	nop
-}
- 80060ea:	3708      	adds	r7, #8
- 80060ec:	46bd      	mov	sp, r7
- 80060ee:	bd80      	pop	{r7, pc}
- 80060f0:	08012054 	.word	0x08012054
- 80060f4:	080120f8 	.word	0x080120f8
- 80060f8:	080120a8 	.word	0x080120a8
-
-080060fc <memp_free>:
- * @param type the pool where to put mem
- * @param mem the memp element to free
- */
-void
-memp_free(memp_t type, void *mem)
-{
- 80060fc:	b580      	push	{r7, lr}
- 80060fe:	b082      	sub	sp, #8
- 8006100:	af00      	add	r7, sp, #0
- 8006102:	4603      	mov	r3, r0
- 8006104:	6039      	str	r1, [r7, #0]
- 8006106:	71fb      	strb	r3, [r7, #7]
-#ifdef LWIP_HOOK_MEMP_AVAILABLE
-  struct memp *old_first;
-#endif
-
-  LWIP_ERROR("memp_free: type < MEMP_MAX", (type < MEMP_MAX), return;);
- 8006108:	79fb      	ldrb	r3, [r7, #7]
- 800610a:	2b08      	cmp	r3, #8
- 800610c:	d907      	bls.n	800611e <memp_free+0x22>
- 800610e:	4b0c      	ldr	r3, [pc, #48]	; (8006140 <memp_free+0x44>)
- 8006110:	f44f 72d5 	mov.w	r2, #426	; 0x1aa
- 8006114:	490b      	ldr	r1, [pc, #44]	; (8006144 <memp_free+0x48>)
- 8006116:	480c      	ldr	r0, [pc, #48]	; (8006148 <memp_free+0x4c>)
- 8006118:	f00a fd56 	bl	8010bc8 <iprintf>
- 800611c:	e00c      	b.n	8006138 <memp_free+0x3c>
-
-  if (mem == NULL) {
- 800611e:	683b      	ldr	r3, [r7, #0]
- 8006120:	2b00      	cmp	r3, #0
- 8006122:	d008      	beq.n	8006136 <memp_free+0x3a>
-
-#ifdef LWIP_HOOK_MEMP_AVAILABLE
-  old_first = *memp_pools[type]->tab;
-#endif
-
-  do_memp_free_pool(memp_pools[type], mem);
- 8006124:	79fb      	ldrb	r3, [r7, #7]
- 8006126:	4a09      	ldr	r2, [pc, #36]	; (800614c <memp_free+0x50>)
- 8006128:	f852 3023 	ldr.w	r3, [r2, r3, lsl #2]
- 800612c:	6839      	ldr	r1, [r7, #0]
- 800612e:	4618      	mov	r0, r3
- 8006130:	f7ff ff9a 	bl	8006068 <do_memp_free_pool>
- 8006134:	e000      	b.n	8006138 <memp_free+0x3c>
-    return;
- 8006136:	bf00      	nop
-#ifdef LWIP_HOOK_MEMP_AVAILABLE
-  if (old_first == NULL) {
-    LWIP_HOOK_MEMP_AVAILABLE(type);
-  }
-#endif
-}
- 8006138:	3708      	adds	r7, #8
- 800613a:	46bd      	mov	sp, r7
- 800613c:	bd80      	pop	{r7, pc}
- 800613e:	bf00      	nop
- 8006140:	08012054 	.word	0x08012054
- 8006144:	0801214c 	.word	0x0801214c
- 8006148:	080120a8 	.word	0x080120a8
- 800614c:	08014d30 	.word	0x08014d30
-
-08006150 <netif_init>:
-}
-#endif /* LWIP_HAVE_LOOPIF */
-
-void
-netif_init(void)
-{
- 8006150:	b480      	push	{r7}
- 8006152:	af00      	add	r7, sp, #0
-
-  netif_set_link_up(&loop_netif);
-  netif_set_up(&loop_netif);
-
-#endif /* LWIP_HAVE_LOOPIF */
-}
- 8006154:	bf00      	nop
- 8006156:	46bd      	mov	sp, r7
- 8006158:	f85d 7b04 	ldr.w	r7, [sp], #4
- 800615c:	4770      	bx	lr
-	...
-
-08006160 <netif_add>:
-netif_add(struct netif *netif,
-#if LWIP_IPV4
-          const ip4_addr_t *ipaddr, const ip4_addr_t *netmask, const ip4_addr_t *gw,
-#endif /* LWIP_IPV4 */
-          void *state, netif_init_fn init, netif_input_fn input)
-{
- 8006160:	b580      	push	{r7, lr}
- 8006162:	b088      	sub	sp, #32
- 8006164:	af02      	add	r7, sp, #8
- 8006166:	60f8      	str	r0, [r7, #12]
- 8006168:	60b9      	str	r1, [r7, #8]
- 800616a:	607a      	str	r2, [r7, #4]
- 800616c:	603b      	str	r3, [r7, #0]
-    LWIP_ASSERT("single netif already set", 0);
-    return NULL;
-  }
-#endif
-
-  LWIP_ERROR("netif_add: invalid netif", netif != NULL, return NULL);
- 800616e:	68fb      	ldr	r3, [r7, #12]
- 8006170:	2b00      	cmp	r3, #0
- 8006172:	d108      	bne.n	8006186 <netif_add+0x26>
- 8006174:	4b96      	ldr	r3, [pc, #600]	; (80063d0 <netif_add+0x270>)
- 8006176:	f240 1227 	movw	r2, #295	; 0x127
- 800617a:	4996      	ldr	r1, [pc, #600]	; (80063d4 <netif_add+0x274>)
- 800617c:	4896      	ldr	r0, [pc, #600]	; (80063d8 <netif_add+0x278>)
- 800617e:	f00a fd23 	bl	8010bc8 <iprintf>
- 8006182:	2300      	movs	r3, #0
- 8006184:	e14c      	b.n	8006420 <netif_add+0x2c0>
-  LWIP_ERROR("netif_add: No init function given", init != NULL, return NULL);
- 8006186:	6a7b      	ldr	r3, [r7, #36]	; 0x24
- 8006188:	2b00      	cmp	r3, #0
- 800618a:	d108      	bne.n	800619e <netif_add+0x3e>
- 800618c:	4b90      	ldr	r3, [pc, #576]	; (80063d0 <netif_add+0x270>)
- 800618e:	f44f 7294 	mov.w	r2, #296	; 0x128
- 8006192:	4992      	ldr	r1, [pc, #584]	; (80063dc <netif_add+0x27c>)
- 8006194:	4890      	ldr	r0, [pc, #576]	; (80063d8 <netif_add+0x278>)
- 8006196:	f00a fd17 	bl	8010bc8 <iprintf>
- 800619a:	2300      	movs	r3, #0
- 800619c:	e140      	b.n	8006420 <netif_add+0x2c0>
-
-#if LWIP_IPV4
-  if (ipaddr == NULL) {
- 800619e:	68bb      	ldr	r3, [r7, #8]
- 80061a0:	2b00      	cmp	r3, #0
- 80061a2:	d101      	bne.n	80061a8 <netif_add+0x48>
-    ipaddr = ip_2_ip4(IP4_ADDR_ANY);
- 80061a4:	4b8e      	ldr	r3, [pc, #568]	; (80063e0 <netif_add+0x280>)
- 80061a6:	60bb      	str	r3, [r7, #8]
-  }
-  if (netmask == NULL) {
- 80061a8:	687b      	ldr	r3, [r7, #4]
- 80061aa:	2b00      	cmp	r3, #0
- 80061ac:	d101      	bne.n	80061b2 <netif_add+0x52>
-    netmask = ip_2_ip4(IP4_ADDR_ANY);
- 80061ae:	4b8c      	ldr	r3, [pc, #560]	; (80063e0 <netif_add+0x280>)
- 80061b0:	607b      	str	r3, [r7, #4]
-  }
-  if (gw == NULL) {
- 80061b2:	683b      	ldr	r3, [r7, #0]
- 80061b4:	2b00      	cmp	r3, #0
- 80061b6:	d101      	bne.n	80061bc <netif_add+0x5c>
-    gw = ip_2_ip4(IP4_ADDR_ANY);
- 80061b8:	4b89      	ldr	r3, [pc, #548]	; (80063e0 <netif_add+0x280>)
- 80061ba:	603b      	str	r3, [r7, #0]
-  }
-
-  /* reset new interface configuration state */
-  ip_addr_set_zero_ip4(&netif->ip_addr);
- 80061bc:	68fb      	ldr	r3, [r7, #12]
- 80061be:	2200      	movs	r2, #0
- 80061c0:	605a      	str	r2, [r3, #4]
-  ip_addr_set_zero_ip4(&netif->netmask);
- 80061c2:	68fb      	ldr	r3, [r7, #12]
- 80061c4:	2200      	movs	r2, #0
- 80061c6:	609a      	str	r2, [r3, #8]
-  ip_addr_set_zero_ip4(&netif->gw);
- 80061c8:	68fb      	ldr	r3, [r7, #12]
- 80061ca:	2200      	movs	r2, #0
- 80061cc:	60da      	str	r2, [r3, #12]
-  netif->output = netif_null_output_ip4;
- 80061ce:	68fb      	ldr	r3, [r7, #12]
- 80061d0:	4a84      	ldr	r2, [pc, #528]	; (80063e4 <netif_add+0x284>)
- 80061d2:	615a      	str	r2, [r3, #20]
-#endif /* LWIP_IPV6_ADDRESS_LIFETIMES */
-  }
-  netif->output_ip6 = netif_null_output_ip6;
-#endif /* LWIP_IPV6 */
-  NETIF_SET_CHECKSUM_CTRL(netif, NETIF_CHECKSUM_ENABLE_ALL);
-  netif->mtu = 0;
- 80061d4:	68fb      	ldr	r3, [r7, #12]
- 80061d6:	2200      	movs	r2, #0
- 80061d8:	849a      	strh	r2, [r3, #36]	; 0x24
-  netif->flags = 0;
- 80061da:	68fb      	ldr	r3, [r7, #12]
- 80061dc:	2200      	movs	r2, #0
- 80061de:	f883 202d 	strb.w	r2, [r3, #45]	; 0x2d
-#endif /* LWIP_IPV6 */
-#if LWIP_NETIF_STATUS_CALLBACK
-  netif->status_callback = NULL;
-#endif /* LWIP_NETIF_STATUS_CALLBACK */
-#if LWIP_NETIF_LINK_CALLBACK
-  netif->link_callback = NULL;
- 80061e2:	68fb      	ldr	r3, [r7, #12]
- 80061e4:	2200      	movs	r2, #0
- 80061e6:	61da      	str	r2, [r3, #28]
-  netif->loop_first = NULL;
-  netif->loop_last = NULL;
-#endif /* ENABLE_LOOPBACK */
-
-  /* remember netif specific state information data */
-  netif->state = state;
- 80061e8:	68fb      	ldr	r3, [r7, #12]
- 80061ea:	6a3a      	ldr	r2, [r7, #32]
- 80061ec:	621a      	str	r2, [r3, #32]
-  netif->num = netif_num;
- 80061ee:	4b7e      	ldr	r3, [pc, #504]	; (80063e8 <netif_add+0x288>)
- 80061f0:	781a      	ldrb	r2, [r3, #0]
- 80061f2:	68fb      	ldr	r3, [r7, #12]
- 80061f4:	f883 2030 	strb.w	r2, [r3, #48]	; 0x30
-  netif->input = input;
- 80061f8:	68fb      	ldr	r3, [r7, #12]
- 80061fa:	6aba      	ldr	r2, [r7, #40]	; 0x28
- 80061fc:	611a      	str	r2, [r3, #16]
-#if ENABLE_LOOPBACK && LWIP_LOOPBACK_MAX_PBUFS
-  netif->loop_cnt_current = 0;
-#endif /* ENABLE_LOOPBACK && LWIP_LOOPBACK_MAX_PBUFS */
-
-#if LWIP_IPV4
-  netif_set_addr(netif, ipaddr, netmask, gw);
- 80061fe:	683b      	ldr	r3, [r7, #0]
- 8006200:	687a      	ldr	r2, [r7, #4]
- 8006202:	68b9      	ldr	r1, [r7, #8]
- 8006204:	68f8      	ldr	r0, [r7, #12]
- 8006206:	f000 f9f5 	bl	80065f4 <netif_set_addr>
-#endif /* LWIP_IPV4 */
-
-  /* call user specified initialization function for netif */
-  if (init(netif) != ERR_OK) {
- 800620a:	6a7b      	ldr	r3, [r7, #36]	; 0x24
- 800620c:	68f8      	ldr	r0, [r7, #12]
- 800620e:	4798      	blx	r3
- 8006210:	4603      	mov	r3, r0
- 8006212:	2b00      	cmp	r3, #0
- 8006214:	d001      	beq.n	800621a <netif_add+0xba>
-    return NULL;
- 8006216:	2300      	movs	r3, #0
- 8006218:	e102      	b.n	8006420 <netif_add+0x2c0>
-     */
-  {
-    struct netif *netif2;
-    int num_netifs;
-    do {
-      if (netif->num == 255) {
- 800621a:	68fb      	ldr	r3, [r7, #12]
- 800621c:	f893 3030 	ldrb.w	r3, [r3, #48]	; 0x30
- 8006220:	2bff      	cmp	r3, #255	; 0xff
- 8006222:	d103      	bne.n	800622c <netif_add+0xcc>
-        netif->num = 0;
- 8006224:	68fb      	ldr	r3, [r7, #12]
- 8006226:	2200      	movs	r2, #0
- 8006228:	f883 2030 	strb.w	r2, [r3, #48]	; 0x30
-      }
-      num_netifs = 0;
- 800622c:	2300      	movs	r3, #0
- 800622e:	613b      	str	r3, [r7, #16]
-      for (netif2 = netif_list; netif2 != NULL; netif2 = netif2->next) {
- 8006230:	4b6e      	ldr	r3, [pc, #440]	; (80063ec <netif_add+0x28c>)
- 8006232:	681b      	ldr	r3, [r3, #0]
- 8006234:	617b      	str	r3, [r7, #20]
- 8006236:	e02b      	b.n	8006290 <netif_add+0x130>
-        LWIP_ASSERT("netif already added", netif2 != netif);
- 8006238:	697a      	ldr	r2, [r7, #20]
- 800623a:	68fb      	ldr	r3, [r7, #12]
- 800623c:	429a      	cmp	r2, r3
- 800623e:	d106      	bne.n	800624e <netif_add+0xee>
- 8006240:	4b63      	ldr	r3, [pc, #396]	; (80063d0 <netif_add+0x270>)
- 8006242:	f240 128b 	movw	r2, #395	; 0x18b
- 8006246:	496a      	ldr	r1, [pc, #424]	; (80063f0 <netif_add+0x290>)
- 8006248:	4863      	ldr	r0, [pc, #396]	; (80063d8 <netif_add+0x278>)
- 800624a:	f00a fcbd 	bl	8010bc8 <iprintf>
-        num_netifs++;
- 800624e:	693b      	ldr	r3, [r7, #16]
- 8006250:	3301      	adds	r3, #1
- 8006252:	613b      	str	r3, [r7, #16]
-        LWIP_ASSERT("too many netifs, max. supported number is 255", num_netifs <= 255);
- 8006254:	693b      	ldr	r3, [r7, #16]
- 8006256:	2bff      	cmp	r3, #255	; 0xff
- 8006258:	dd06      	ble.n	8006268 <netif_add+0x108>
- 800625a:	4b5d      	ldr	r3, [pc, #372]	; (80063d0 <netif_add+0x270>)
- 800625c:	f240 128d 	movw	r2, #397	; 0x18d
- 8006260:	4964      	ldr	r1, [pc, #400]	; (80063f4 <netif_add+0x294>)
- 8006262:	485d      	ldr	r0, [pc, #372]	; (80063d8 <netif_add+0x278>)
- 8006264:	f00a fcb0 	bl	8010bc8 <iprintf>
-        if (netif2->num == netif->num) {
- 8006268:	697b      	ldr	r3, [r7, #20]
- 800626a:	f893 2030 	ldrb.w	r2, [r3, #48]	; 0x30
- 800626e:	68fb      	ldr	r3, [r7, #12]
- 8006270:	f893 3030 	ldrb.w	r3, [r3, #48]	; 0x30
- 8006274:	429a      	cmp	r2, r3
- 8006276:	d108      	bne.n	800628a <netif_add+0x12a>
-          netif->num++;
- 8006278:	68fb      	ldr	r3, [r7, #12]
- 800627a:	f893 3030 	ldrb.w	r3, [r3, #48]	; 0x30
- 800627e:	3301      	adds	r3, #1
- 8006280:	b2da      	uxtb	r2, r3
- 8006282:	68fb      	ldr	r3, [r7, #12]
- 8006284:	f883 2030 	strb.w	r2, [r3, #48]	; 0x30
-          break;
- 8006288:	e005      	b.n	8006296 <netif_add+0x136>
-      for (netif2 = netif_list; netif2 != NULL; netif2 = netif2->next) {
- 800628a:	697b      	ldr	r3, [r7, #20]
- 800628c:	681b      	ldr	r3, [r3, #0]
- 800628e:	617b      	str	r3, [r7, #20]
- 8006290:	697b      	ldr	r3, [r7, #20]
- 8006292:	2b00      	cmp	r3, #0
- 8006294:	d1d0      	bne.n	8006238 <netif_add+0xd8>
-        }
-      }
-    } while (netif2 != NULL);
- 8006296:	697b      	ldr	r3, [r7, #20]
- 8006298:	2b00      	cmp	r3, #0
- 800629a:	d1be      	bne.n	800621a <netif_add+0xba>
-  }
-  if (netif->num == 254) {
- 800629c:	68fb      	ldr	r3, [r7, #12]
- 800629e:	f893 3030 	ldrb.w	r3, [r3, #48]	; 0x30
- 80062a2:	2bfe      	cmp	r3, #254	; 0xfe
- 80062a4:	d103      	bne.n	80062ae <netif_add+0x14e>
-    netif_num = 0;
- 80062a6:	4b50      	ldr	r3, [pc, #320]	; (80063e8 <netif_add+0x288>)
- 80062a8:	2200      	movs	r2, #0
- 80062aa:	701a      	strb	r2, [r3, #0]
- 80062ac:	e006      	b.n	80062bc <netif_add+0x15c>
-  } else {
-    netif_num = (u8_t)(netif->num + 1);
- 80062ae:	68fb      	ldr	r3, [r7, #12]
- 80062b0:	f893 3030 	ldrb.w	r3, [r3, #48]	; 0x30
- 80062b4:	3301      	adds	r3, #1
- 80062b6:	b2da      	uxtb	r2, r3
- 80062b8:	4b4b      	ldr	r3, [pc, #300]	; (80063e8 <netif_add+0x288>)
- 80062ba:	701a      	strb	r2, [r3, #0]
-  }
-
-  /* add this netif to the list */
-  netif->next = netif_list;
- 80062bc:	4b4b      	ldr	r3, [pc, #300]	; (80063ec <netif_add+0x28c>)
- 80062be:	681a      	ldr	r2, [r3, #0]
- 80062c0:	68fb      	ldr	r3, [r7, #12]
- 80062c2:	601a      	str	r2, [r3, #0]
-  netif_list = netif;
- 80062c4:	4a49      	ldr	r2, [pc, #292]	; (80063ec <netif_add+0x28c>)
- 80062c6:	68fb      	ldr	r3, [r7, #12]
- 80062c8:	6013      	str	r3, [r2, #0]
-  if (netif->flags & NETIF_FLAG_IGMP) {
-    igmp_start(netif);
-  }
-#endif /* LWIP_IGMP */
-
-  LWIP_DEBUGF(NETIF_DEBUG, ("netif: added interface %c%c IP",
- 80062ca:	68fb      	ldr	r3, [r7, #12]
- 80062cc:	f893 302e 	ldrb.w	r3, [r3, #46]	; 0x2e
- 80062d0:	4619      	mov	r1, r3
- 80062d2:	68fb      	ldr	r3, [r7, #12]
- 80062d4:	f893 302f 	ldrb.w	r3, [r3, #47]	; 0x2f
- 80062d8:	461a      	mov	r2, r3
- 80062da:	4847      	ldr	r0, [pc, #284]	; (80063f8 <netif_add+0x298>)
- 80062dc:	f00a fc74 	bl	8010bc8 <iprintf>
-                            netif->name[0], netif->name[1]));
-#if LWIP_IPV4
-  LWIP_DEBUGF(NETIF_DEBUG, (" addr "));
- 80062e0:	4846      	ldr	r0, [pc, #280]	; (80063fc <netif_add+0x29c>)
- 80062e2:	f00a fc71 	bl	8010bc8 <iprintf>
-  ip4_addr_debug_print(NETIF_DEBUG, ipaddr);
- 80062e6:	68bb      	ldr	r3, [r7, #8]
- 80062e8:	2b00      	cmp	r3, #0
- 80062ea:	d003      	beq.n	80062f4 <netif_add+0x194>
- 80062ec:	68bb      	ldr	r3, [r7, #8]
- 80062ee:	781b      	ldrb	r3, [r3, #0]
- 80062f0:	4619      	mov	r1, r3
- 80062f2:	e000      	b.n	80062f6 <netif_add+0x196>
- 80062f4:	2100      	movs	r1, #0
- 80062f6:	68bb      	ldr	r3, [r7, #8]
- 80062f8:	2b00      	cmp	r3, #0
- 80062fa:	d004      	beq.n	8006306 <netif_add+0x1a6>
- 80062fc:	68bb      	ldr	r3, [r7, #8]
- 80062fe:	3301      	adds	r3, #1
- 8006300:	781b      	ldrb	r3, [r3, #0]
- 8006302:	461a      	mov	r2, r3
- 8006304:	e000      	b.n	8006308 <netif_add+0x1a8>
- 8006306:	2200      	movs	r2, #0
- 8006308:	68bb      	ldr	r3, [r7, #8]
- 800630a:	2b00      	cmp	r3, #0
- 800630c:	d004      	beq.n	8006318 <netif_add+0x1b8>
- 800630e:	68bb      	ldr	r3, [r7, #8]
- 8006310:	3302      	adds	r3, #2
- 8006312:	781b      	ldrb	r3, [r3, #0]
- 8006314:	4618      	mov	r0, r3
- 8006316:	e000      	b.n	800631a <netif_add+0x1ba>
- 8006318:	2000      	movs	r0, #0
- 800631a:	68bb      	ldr	r3, [r7, #8]
- 800631c:	2b00      	cmp	r3, #0
- 800631e:	d003      	beq.n	8006328 <netif_add+0x1c8>
- 8006320:	68bb      	ldr	r3, [r7, #8]
- 8006322:	3303      	adds	r3, #3
- 8006324:	781b      	ldrb	r3, [r3, #0]
- 8006326:	e000      	b.n	800632a <netif_add+0x1ca>
- 8006328:	2300      	movs	r3, #0
- 800632a:	9300      	str	r3, [sp, #0]
- 800632c:	4603      	mov	r3, r0
- 800632e:	4834      	ldr	r0, [pc, #208]	; (8006400 <netif_add+0x2a0>)
- 8006330:	f00a fc4a 	bl	8010bc8 <iprintf>
-  LWIP_DEBUGF(NETIF_DEBUG, (" netmask "));
- 8006334:	4833      	ldr	r0, [pc, #204]	; (8006404 <netif_add+0x2a4>)
- 8006336:	f00a fc47 	bl	8010bc8 <iprintf>
-  ip4_addr_debug_print(NETIF_DEBUG, netmask);
- 800633a:	687b      	ldr	r3, [r7, #4]
- 800633c:	2b00      	cmp	r3, #0
- 800633e:	d003      	beq.n	8006348 <netif_add+0x1e8>
- 8006340:	687b      	ldr	r3, [r7, #4]
- 8006342:	781b      	ldrb	r3, [r3, #0]
- 8006344:	4619      	mov	r1, r3
- 8006346:	e000      	b.n	800634a <netif_add+0x1ea>
- 8006348:	2100      	movs	r1, #0
- 800634a:	687b      	ldr	r3, [r7, #4]
- 800634c:	2b00      	cmp	r3, #0
- 800634e:	d004      	beq.n	800635a <netif_add+0x1fa>
- 8006350:	687b      	ldr	r3, [r7, #4]
- 8006352:	3301      	adds	r3, #1
- 8006354:	781b      	ldrb	r3, [r3, #0]
- 8006356:	461a      	mov	r2, r3
- 8006358:	e000      	b.n	800635c <netif_add+0x1fc>
- 800635a:	2200      	movs	r2, #0
- 800635c:	687b      	ldr	r3, [r7, #4]
- 800635e:	2b00      	cmp	r3, #0
- 8006360:	d004      	beq.n	800636c <netif_add+0x20c>
- 8006362:	687b      	ldr	r3, [r7, #4]
- 8006364:	3302      	adds	r3, #2
- 8006366:	781b      	ldrb	r3, [r3, #0]
- 8006368:	4618      	mov	r0, r3
- 800636a:	e000      	b.n	800636e <netif_add+0x20e>
- 800636c:	2000      	movs	r0, #0
- 800636e:	687b      	ldr	r3, [r7, #4]
- 8006370:	2b00      	cmp	r3, #0
- 8006372:	d003      	beq.n	800637c <netif_add+0x21c>
- 8006374:	687b      	ldr	r3, [r7, #4]
- 8006376:	3303      	adds	r3, #3
- 8006378:	781b      	ldrb	r3, [r3, #0]
- 800637a:	e000      	b.n	800637e <netif_add+0x21e>
- 800637c:	2300      	movs	r3, #0
- 800637e:	9300      	str	r3, [sp, #0]
- 8006380:	4603      	mov	r3, r0
- 8006382:	481f      	ldr	r0, [pc, #124]	; (8006400 <netif_add+0x2a0>)
- 8006384:	f00a fc20 	bl	8010bc8 <iprintf>
-  LWIP_DEBUGF(NETIF_DEBUG, (" gw "));
- 8006388:	481f      	ldr	r0, [pc, #124]	; (8006408 <netif_add+0x2a8>)
- 800638a:	f00a fc1d 	bl	8010bc8 <iprintf>
-  ip4_addr_debug_print(NETIF_DEBUG, gw);
- 800638e:	683b      	ldr	r3, [r7, #0]
- 8006390:	2b00      	cmp	r3, #0
- 8006392:	d003      	beq.n	800639c <netif_add+0x23c>
- 8006394:	683b      	ldr	r3, [r7, #0]
- 8006396:	781b      	ldrb	r3, [r3, #0]
- 8006398:	4619      	mov	r1, r3
- 800639a:	e000      	b.n	800639e <netif_add+0x23e>
- 800639c:	2100      	movs	r1, #0
- 800639e:	683b      	ldr	r3, [r7, #0]
- 80063a0:	2b00      	cmp	r3, #0
- 80063a2:	d004      	beq.n	80063ae <netif_add+0x24e>
- 80063a4:	683b      	ldr	r3, [r7, #0]
- 80063a6:	3301      	adds	r3, #1
- 80063a8:	781b      	ldrb	r3, [r3, #0]
- 80063aa:	461a      	mov	r2, r3
- 80063ac:	e000      	b.n	80063b0 <netif_add+0x250>
- 80063ae:	2200      	movs	r2, #0
- 80063b0:	683b      	ldr	r3, [r7, #0]
- 80063b2:	2b00      	cmp	r3, #0
- 80063b4:	d004      	beq.n	80063c0 <netif_add+0x260>
- 80063b6:	683b      	ldr	r3, [r7, #0]
- 80063b8:	3302      	adds	r3, #2
- 80063ba:	781b      	ldrb	r3, [r3, #0]
- 80063bc:	4618      	mov	r0, r3
- 80063be:	e000      	b.n	80063c2 <netif_add+0x262>
- 80063c0:	2000      	movs	r0, #0
- 80063c2:	683b      	ldr	r3, [r7, #0]
- 80063c4:	2b00      	cmp	r3, #0
- 80063c6:	d021      	beq.n	800640c <netif_add+0x2ac>
- 80063c8:	683b      	ldr	r3, [r7, #0]
- 80063ca:	3303      	adds	r3, #3
- 80063cc:	781b      	ldrb	r3, [r3, #0]
- 80063ce:	e01e      	b.n	800640e <netif_add+0x2ae>
- 80063d0:	08012168 	.word	0x08012168
- 80063d4:	080121fc 	.word	0x080121fc
- 80063d8:	080121b8 	.word	0x080121b8
- 80063dc:	08012218 	.word	0x08012218
- 80063e0:	08014d94 	.word	0x08014d94
- 80063e4:	080068f7 	.word	0x080068f7
- 80063e8:	24007b68 	.word	0x24007b68
- 80063ec:	24007b60 	.word	0x24007b60
- 80063f0:	0801223c 	.word	0x0801223c
- 80063f4:	08012250 	.word	0x08012250
- 80063f8:	08012280 	.word	0x08012280
- 80063fc:	080122a0 	.word	0x080122a0
- 8006400:	080122a8 	.word	0x080122a8
- 8006404:	080122b8 	.word	0x080122b8
- 8006408:	080122c4 	.word	0x080122c4
- 800640c:	2300      	movs	r3, #0
- 800640e:	9300      	str	r3, [sp, #0]
- 8006410:	4603      	mov	r3, r0
- 8006412:	4805      	ldr	r0, [pc, #20]	; (8006428 <netif_add+0x2c8>)
- 8006414:	f00a fbd8 	bl	8010bc8 <iprintf>
-#endif /* LWIP_IPV4 */
-  LWIP_DEBUGF(NETIF_DEBUG, ("\n"));
- 8006418:	200a      	movs	r0, #10
- 800641a:	f00a fbe7 	bl	8010bec <putchar>
-
-  netif_invoke_ext_callback(netif, LWIP_NSC_NETIF_ADDED, NULL);
-
-  return netif;
- 800641e:	68fb      	ldr	r3, [r7, #12]
-}
- 8006420:	4618      	mov	r0, r3
- 8006422:	3718      	adds	r7, #24
- 8006424:	46bd      	mov	sp, r7
- 8006426:	bd80      	pop	{r7, pc}
- 8006428:	080122a8 	.word	0x080122a8
-
-0800642c <netif_do_ip_addr_changed>:
-
-static void
-netif_do_ip_addr_changed(const ip_addr_t *old_addr, const ip_addr_t *new_addr)
-{
- 800642c:	b580      	push	{r7, lr}
- 800642e:	b082      	sub	sp, #8
- 8006430:	af00      	add	r7, sp, #0
- 8006432:	6078      	str	r0, [r7, #4]
- 8006434:	6039      	str	r1, [r7, #0]
-#if LWIP_TCP
-  tcp_netif_ip_addr_changed(old_addr, new_addr);
- 8006436:	6839      	ldr	r1, [r7, #0]
- 8006438:	6878      	ldr	r0, [r7, #4]
- 800643a:	f002 fd85 	bl	8008f48 <tcp_netif_ip_addr_changed>
-#endif /* LWIP_TCP */
-#if LWIP_UDP
-  udp_netif_ip_addr_changed(old_addr, new_addr);
- 800643e:	6839      	ldr	r1, [r7, #0]
- 8006440:	6878      	ldr	r0, [r7, #4]
- 8006442:	f007 fb2d 	bl	800daa0 <udp_netif_ip_addr_changed>
-#endif /* LWIP_UDP */
-#if LWIP_RAW
-  raw_netif_ip_addr_changed(old_addr, new_addr);
-#endif /* LWIP_RAW */
-}
- 8006446:	bf00      	nop
- 8006448:	3708      	adds	r7, #8
- 800644a:	46bd      	mov	sp, r7
- 800644c:	bd80      	pop	{r7, pc}
-	...
-
-08006450 <netif_do_set_ipaddr>:
-
-#if LWIP_IPV4
-static int
-netif_do_set_ipaddr(struct netif *netif, const ip4_addr_t *ipaddr, ip_addr_t *old_addr)
-{
- 8006450:	b580      	push	{r7, lr}
- 8006452:	b086      	sub	sp, #24
- 8006454:	af00      	add	r7, sp, #0
- 8006456:	60f8      	str	r0, [r7, #12]
- 8006458:	60b9      	str	r1, [r7, #8]
- 800645a:	607a      	str	r2, [r7, #4]
-  LWIP_ASSERT("invalid pointer", ipaddr != NULL);
- 800645c:	68bb      	ldr	r3, [r7, #8]
- 800645e:	2b00      	cmp	r3, #0
- 8006460:	d106      	bne.n	8006470 <netif_do_set_ipaddr+0x20>
- 8006462:	4b1e      	ldr	r3, [pc, #120]	; (80064dc <netif_do_set_ipaddr+0x8c>)
- 8006464:	f240 12cb 	movw	r2, #459	; 0x1cb
- 8006468:	491d      	ldr	r1, [pc, #116]	; (80064e0 <netif_do_set_ipaddr+0x90>)
- 800646a:	481e      	ldr	r0, [pc, #120]	; (80064e4 <netif_do_set_ipaddr+0x94>)
- 800646c:	f00a fbac 	bl	8010bc8 <iprintf>
-  LWIP_ASSERT("invalid pointer", old_addr != NULL);
- 8006470:	687b      	ldr	r3, [r7, #4]
- 8006472:	2b00      	cmp	r3, #0
- 8006474:	d106      	bne.n	8006484 <netif_do_set_ipaddr+0x34>
- 8006476:	4b19      	ldr	r3, [pc, #100]	; (80064dc <netif_do_set_ipaddr+0x8c>)
- 8006478:	f44f 72e6 	mov.w	r2, #460	; 0x1cc
- 800647c:	4918      	ldr	r1, [pc, #96]	; (80064e0 <netif_do_set_ipaddr+0x90>)
- 800647e:	4819      	ldr	r0, [pc, #100]	; (80064e4 <netif_do_set_ipaddr+0x94>)
- 8006480:	f00a fba2 	bl	8010bc8 <iprintf>
-
-  /* address is actually being changed? */
-  if (ip4_addr_cmp(ipaddr, netif_ip4_addr(netif)) == 0) {
- 8006484:	68bb      	ldr	r3, [r7, #8]
- 8006486:	681a      	ldr	r2, [r3, #0]
- 8006488:	68fb      	ldr	r3, [r7, #12]
- 800648a:	3304      	adds	r3, #4
- 800648c:	681b      	ldr	r3, [r3, #0]
- 800648e:	429a      	cmp	r2, r3
- 8006490:	d01f      	beq.n	80064d2 <netif_do_set_ipaddr+0x82>
-    ip_addr_t new_addr;
-    *ip_2_ip4(&new_addr) = *ipaddr;
- 8006492:	68bb      	ldr	r3, [r7, #8]
- 8006494:	681b      	ldr	r3, [r3, #0]
- 8006496:	617b      	str	r3, [r7, #20]
-    IP_SET_TYPE_VAL(new_addr, IPADDR_TYPE_V4);
-
-    ip_addr_copy(*old_addr, *netif_ip_addr4(netif));
- 8006498:	68fb      	ldr	r3, [r7, #12]
- 800649a:	3304      	adds	r3, #4
- 800649c:	681a      	ldr	r2, [r3, #0]
- 800649e:	687b      	ldr	r3, [r7, #4]
- 80064a0:	601a      	str	r2, [r3, #0]
-
-    LWIP_DEBUGF(NETIF_DEBUG | LWIP_DBG_STATE, ("netif_set_ipaddr: netif address being changed\n"));
- 80064a2:	4811      	ldr	r0, [pc, #68]	; (80064e8 <netif_do_set_ipaddr+0x98>)
- 80064a4:	f00a fbfe 	bl	8010ca4 <puts>
-    netif_do_ip_addr_changed(old_addr, &new_addr);
- 80064a8:	f107 0314 	add.w	r3, r7, #20
- 80064ac:	4619      	mov	r1, r3
- 80064ae:	6878      	ldr	r0, [r7, #4]
- 80064b0:	f7ff ffbc 	bl	800642c <netif_do_ip_addr_changed>
-
-    mib2_remove_ip4(netif);
-    mib2_remove_route_ip4(0, netif);
-    /* set new IP address to netif */
-    ip4_addr_set(ip_2_ip4(&netif->ip_addr), ipaddr);
- 80064b4:	68bb      	ldr	r3, [r7, #8]
- 80064b6:	2b00      	cmp	r3, #0
- 80064b8:	d002      	beq.n	80064c0 <netif_do_set_ipaddr+0x70>
- 80064ba:	68bb      	ldr	r3, [r7, #8]
- 80064bc:	681b      	ldr	r3, [r3, #0]
- 80064be:	e000      	b.n	80064c2 <netif_do_set_ipaddr+0x72>
- 80064c0:	2300      	movs	r3, #0
- 80064c2:	68fa      	ldr	r2, [r7, #12]
- 80064c4:	6053      	str	r3, [r2, #4]
-    IP_SET_TYPE_VAL(netif->ip_addr, IPADDR_TYPE_V4);
-    mib2_add_ip4(netif);
-    mib2_add_route_ip4(0, netif);
-
-    netif_issue_reports(netif, NETIF_REPORT_TYPE_IPV4);
- 80064c6:	2101      	movs	r1, #1
- 80064c8:	68f8      	ldr	r0, [r7, #12]
- 80064ca:	f000 f92d 	bl	8006728 <netif_issue_reports>
-
-    NETIF_STATUS_CALLBACK(netif);
-    return 1; /* address changed */
- 80064ce:	2301      	movs	r3, #1
- 80064d0:	e000      	b.n	80064d4 <netif_do_set_ipaddr+0x84>
-  }
-  return 0; /* address unchanged */
- 80064d2:	2300      	movs	r3, #0
-}
- 80064d4:	4618      	mov	r0, r3
- 80064d6:	3718      	adds	r7, #24
- 80064d8:	46bd      	mov	sp, r7
- 80064da:	bd80      	pop	{r7, pc}
- 80064dc:	08012168 	.word	0x08012168
- 80064e0:	080122cc 	.word	0x080122cc
- 80064e4:	080121b8 	.word	0x080121b8
- 80064e8:	080122dc 	.word	0x080122dc
-
-080064ec <netif_do_set_netmask>:
-  }
-}
-
-static int
-netif_do_set_netmask(struct netif *netif, const ip4_addr_t *netmask, ip_addr_t *old_nm)
-{
- 80064ec:	b5b0      	push	{r4, r5, r7, lr}
- 80064ee:	b088      	sub	sp, #32
- 80064f0:	af04      	add	r7, sp, #16
- 80064f2:	60f8      	str	r0, [r7, #12]
- 80064f4:	60b9      	str	r1, [r7, #8]
- 80064f6:	607a      	str	r2, [r7, #4]
-  /* address is actually being changed? */
-  if (ip4_addr_cmp(netmask, netif_ip4_netmask(netif)) == 0) {
- 80064f8:	68bb      	ldr	r3, [r7, #8]
- 80064fa:	681a      	ldr	r2, [r3, #0]
- 80064fc:	68fb      	ldr	r3, [r7, #12]
- 80064fe:	3308      	adds	r3, #8
- 8006500:	681b      	ldr	r3, [r3, #0]
- 8006502:	429a      	cmp	r2, r3
- 8006504:	d02d      	beq.n	8006562 <netif_do_set_netmask+0x76>
-#else
-    LWIP_UNUSED_ARG(old_nm);
-#endif
-    mib2_remove_route_ip4(0, netif);
-    /* set new netmask to netif */
-    ip4_addr_set(ip_2_ip4(&netif->netmask), netmask);
- 8006506:	68bb      	ldr	r3, [r7, #8]
- 8006508:	2b00      	cmp	r3, #0
- 800650a:	d002      	beq.n	8006512 <netif_do_set_netmask+0x26>
- 800650c:	68bb      	ldr	r3, [r7, #8]
- 800650e:	681b      	ldr	r3, [r3, #0]
- 8006510:	e000      	b.n	8006514 <netif_do_set_netmask+0x28>
- 8006512:	2300      	movs	r3, #0
- 8006514:	68fa      	ldr	r2, [r7, #12]
- 8006516:	6093      	str	r3, [r2, #8]
-    IP_SET_TYPE_VAL(netif->netmask, IPADDR_TYPE_V4);
-    mib2_add_route_ip4(0, netif);
-    LWIP_DEBUGF(NETIF_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("netif: netmask of interface %c%c set to %"U16_F".%"U16_F".%"U16_F".%"U16_F"\n",
- 8006518:	68fb      	ldr	r3, [r7, #12]
- 800651a:	f893 302e 	ldrb.w	r3, [r3, #46]	; 0x2e
- 800651e:	4618      	mov	r0, r3
- 8006520:	68fb      	ldr	r3, [r7, #12]
- 8006522:	f893 302f 	ldrb.w	r3, [r3, #47]	; 0x2f
- 8006526:	461c      	mov	r4, r3
- 8006528:	68fb      	ldr	r3, [r7, #12]
- 800652a:	3308      	adds	r3, #8
- 800652c:	781b      	ldrb	r3, [r3, #0]
- 800652e:	461d      	mov	r5, r3
- 8006530:	68fb      	ldr	r3, [r7, #12]
- 8006532:	3308      	adds	r3, #8
- 8006534:	3301      	adds	r3, #1
- 8006536:	781b      	ldrb	r3, [r3, #0]
- 8006538:	461a      	mov	r2, r3
- 800653a:	68fb      	ldr	r3, [r7, #12]
- 800653c:	3308      	adds	r3, #8
- 800653e:	3302      	adds	r3, #2
- 8006540:	781b      	ldrb	r3, [r3, #0]
- 8006542:	4619      	mov	r1, r3
- 8006544:	68fb      	ldr	r3, [r7, #12]
- 8006546:	3308      	adds	r3, #8
- 8006548:	3303      	adds	r3, #3
- 800654a:	781b      	ldrb	r3, [r3, #0]
- 800654c:	9302      	str	r3, [sp, #8]
- 800654e:	9101      	str	r1, [sp, #4]
- 8006550:	9200      	str	r2, [sp, #0]
- 8006552:	462b      	mov	r3, r5
- 8006554:	4622      	mov	r2, r4
- 8006556:	4601      	mov	r1, r0
- 8006558:	4804      	ldr	r0, [pc, #16]	; (800656c <netif_do_set_netmask+0x80>)
- 800655a:	f00a fb35 	bl	8010bc8 <iprintf>
-                netif->name[0], netif->name[1],
-                ip4_addr1_16(netif_ip4_netmask(netif)),
-                ip4_addr2_16(netif_ip4_netmask(netif)),
-                ip4_addr3_16(netif_ip4_netmask(netif)),
-                ip4_addr4_16(netif_ip4_netmask(netif))));
-    return 1; /* netmask changed */
- 800655e:	2301      	movs	r3, #1
- 8006560:	e000      	b.n	8006564 <netif_do_set_netmask+0x78>
-  }
-  return 0; /* netmask unchanged */
- 8006562:	2300      	movs	r3, #0
-}
- 8006564:	4618      	mov	r0, r3
- 8006566:	3710      	adds	r7, #16
- 8006568:	46bd      	mov	sp, r7
- 800656a:	bdb0      	pop	{r4, r5, r7, pc}
- 800656c:	0801232c 	.word	0x0801232c
-
-08006570 <netif_do_set_gw>:
-  }
-}
-
-static int
-netif_do_set_gw(struct netif *netif, const ip4_addr_t *gw, ip_addr_t *old_gw)
-{
- 8006570:	b5b0      	push	{r4, r5, r7, lr}
- 8006572:	b088      	sub	sp, #32
- 8006574:	af04      	add	r7, sp, #16
- 8006576:	60f8      	str	r0, [r7, #12]
- 8006578:	60b9      	str	r1, [r7, #8]
- 800657a:	607a      	str	r2, [r7, #4]
-  /* address is actually being changed? */
-  if (ip4_addr_cmp(gw, netif_ip4_gw(netif)) == 0) {
- 800657c:	68bb      	ldr	r3, [r7, #8]
- 800657e:	681a      	ldr	r2, [r3, #0]
- 8006580:	68fb      	ldr	r3, [r7, #12]
- 8006582:	330c      	adds	r3, #12
- 8006584:	681b      	ldr	r3, [r3, #0]
- 8006586:	429a      	cmp	r2, r3
- 8006588:	d02d      	beq.n	80065e6 <netif_do_set_gw+0x76>
-    ip_addr_copy(*old_gw, *netif_ip_gw4(netif));
-#else
-    LWIP_UNUSED_ARG(old_gw);
-#endif
-
-    ip4_addr_set(ip_2_ip4(&netif->gw), gw);
- 800658a:	68bb      	ldr	r3, [r7, #8]
- 800658c:	2b00      	cmp	r3, #0
- 800658e:	d002      	beq.n	8006596 <netif_do_set_gw+0x26>
- 8006590:	68bb      	ldr	r3, [r7, #8]
- 8006592:	681b      	ldr	r3, [r3, #0]
- 8006594:	e000      	b.n	8006598 <netif_do_set_gw+0x28>
- 8006596:	2300      	movs	r3, #0
- 8006598:	68fa      	ldr	r2, [r7, #12]
- 800659a:	60d3      	str	r3, [r2, #12]
-    IP_SET_TYPE_VAL(netif->gw, IPADDR_TYPE_V4);
-    LWIP_DEBUGF(NETIF_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("netif: GW address of interface %c%c set to %"U16_F".%"U16_F".%"U16_F".%"U16_F"\n",
- 800659c:	68fb      	ldr	r3, [r7, #12]
- 800659e:	f893 302e 	ldrb.w	r3, [r3, #46]	; 0x2e
- 80065a2:	4618      	mov	r0, r3
- 80065a4:	68fb      	ldr	r3, [r7, #12]
- 80065a6:	f893 302f 	ldrb.w	r3, [r3, #47]	; 0x2f
- 80065aa:	461c      	mov	r4, r3
- 80065ac:	68fb      	ldr	r3, [r7, #12]
- 80065ae:	330c      	adds	r3, #12
- 80065b0:	781b      	ldrb	r3, [r3, #0]
- 80065b2:	461d      	mov	r5, r3
- 80065b4:	68fb      	ldr	r3, [r7, #12]
- 80065b6:	330c      	adds	r3, #12
- 80065b8:	3301      	adds	r3, #1
- 80065ba:	781b      	ldrb	r3, [r3, #0]
- 80065bc:	461a      	mov	r2, r3
- 80065be:	68fb      	ldr	r3, [r7, #12]
- 80065c0:	330c      	adds	r3, #12
- 80065c2:	3302      	adds	r3, #2
- 80065c4:	781b      	ldrb	r3, [r3, #0]
- 80065c6:	4619      	mov	r1, r3
- 80065c8:	68fb      	ldr	r3, [r7, #12]
- 80065ca:	330c      	adds	r3, #12
- 80065cc:	3303      	adds	r3, #3
- 80065ce:	781b      	ldrb	r3, [r3, #0]
- 80065d0:	9302      	str	r3, [sp, #8]
- 80065d2:	9101      	str	r1, [sp, #4]
- 80065d4:	9200      	str	r2, [sp, #0]
- 80065d6:	462b      	mov	r3, r5
- 80065d8:	4622      	mov	r2, r4
- 80065da:	4601      	mov	r1, r0
- 80065dc:	4804      	ldr	r0, [pc, #16]	; (80065f0 <netif_do_set_gw+0x80>)
- 80065de:	f00a faf3 	bl	8010bc8 <iprintf>
-                netif->name[0], netif->name[1],
-                ip4_addr1_16(netif_ip4_gw(netif)),
-                ip4_addr2_16(netif_ip4_gw(netif)),
-                ip4_addr3_16(netif_ip4_gw(netif)),
-                ip4_addr4_16(netif_ip4_gw(netif))));
-    return 1; /* gateway changed */
- 80065e2:	2301      	movs	r3, #1
- 80065e4:	e000      	b.n	80065e8 <netif_do_set_gw+0x78>
-  }
-  return 0; /* gateway unchanged */
- 80065e6:	2300      	movs	r3, #0
-}
- 80065e8:	4618      	mov	r0, r3
- 80065ea:	3710      	adds	r7, #16
- 80065ec:	46bd      	mov	sp, r7
- 80065ee:	bdb0      	pop	{r4, r5, r7, pc}
- 80065f0:	0801238c 	.word	0x0801238c
-
-080065f4 <netif_set_addr>:
- * @param gw the new default gateway
- */
-void
-netif_set_addr(struct netif *netif, const ip4_addr_t *ipaddr, const ip4_addr_t *netmask,
-               const ip4_addr_t *gw)
-{
- 80065f4:	b580      	push	{r7, lr}
- 80065f6:	b088      	sub	sp, #32
- 80065f8:	af00      	add	r7, sp, #0
- 80065fa:	60f8      	str	r0, [r7, #12]
- 80065fc:	60b9      	str	r1, [r7, #8]
- 80065fe:	607a      	str	r2, [r7, #4]
- 8006600:	603b      	str	r3, [r7, #0]
-  ip_addr_t old_nm_val;
-  ip_addr_t old_gw_val;
-  ip_addr_t *old_nm = &old_nm_val;
-  ip_addr_t *old_gw = &old_gw_val;
-#else
-  ip_addr_t *old_nm = NULL;
- 8006602:	2300      	movs	r3, #0
- 8006604:	61fb      	str	r3, [r7, #28]
-  ip_addr_t *old_gw = NULL;
- 8006606:	2300      	movs	r3, #0
- 8006608:	61bb      	str	r3, [r7, #24]
-  int remove;
-
-  LWIP_ASSERT_CORE_LOCKED();
-
-  /* Don't propagate NULL pointer (IPv4 ANY) to subsequent functions */
-  if (ipaddr == NULL) {
- 800660a:	68bb      	ldr	r3, [r7, #8]
- 800660c:	2b00      	cmp	r3, #0
- 800660e:	d101      	bne.n	8006614 <netif_set_addr+0x20>
-    ipaddr = IP4_ADDR_ANY4;
- 8006610:	4b1c      	ldr	r3, [pc, #112]	; (8006684 <netif_set_addr+0x90>)
- 8006612:	60bb      	str	r3, [r7, #8]
-  }
-  if (netmask == NULL) {
- 8006614:	687b      	ldr	r3, [r7, #4]
- 8006616:	2b00      	cmp	r3, #0
- 8006618:	d101      	bne.n	800661e <netif_set_addr+0x2a>
-    netmask = IP4_ADDR_ANY4;
- 800661a:	4b1a      	ldr	r3, [pc, #104]	; (8006684 <netif_set_addr+0x90>)
- 800661c:	607b      	str	r3, [r7, #4]
-  }
-  if (gw == NULL) {
- 800661e:	683b      	ldr	r3, [r7, #0]
- 8006620:	2b00      	cmp	r3, #0
- 8006622:	d101      	bne.n	8006628 <netif_set_addr+0x34>
-    gw = IP4_ADDR_ANY4;
- 8006624:	4b17      	ldr	r3, [pc, #92]	; (8006684 <netif_set_addr+0x90>)
- 8006626:	603b      	str	r3, [r7, #0]
-  }
-
-  remove = ip4_addr_isany(ipaddr);
- 8006628:	68bb      	ldr	r3, [r7, #8]
- 800662a:	2b00      	cmp	r3, #0
- 800662c:	d003      	beq.n	8006636 <netif_set_addr+0x42>
- 800662e:	68bb      	ldr	r3, [r7, #8]
- 8006630:	681b      	ldr	r3, [r3, #0]
- 8006632:	2b00      	cmp	r3, #0
- 8006634:	d101      	bne.n	800663a <netif_set_addr+0x46>
- 8006636:	2301      	movs	r3, #1
- 8006638:	e000      	b.n	800663c <netif_set_addr+0x48>
- 800663a:	2300      	movs	r3, #0
- 800663c:	617b      	str	r3, [r7, #20]
-  if (remove) {
- 800663e:	697b      	ldr	r3, [r7, #20]
- 8006640:	2b00      	cmp	r3, #0
- 8006642:	d006      	beq.n	8006652 <netif_set_addr+0x5e>
-    /* when removing an address, we have to remove it *before* changing netmask/gw
-       to ensure that tcp RST segment can be sent correctly */
-    if (netif_do_set_ipaddr(netif, ipaddr, &old_addr)) {
- 8006644:	f107 0310 	add.w	r3, r7, #16
- 8006648:	461a      	mov	r2, r3
- 800664a:	68b9      	ldr	r1, [r7, #8]
- 800664c:	68f8      	ldr	r0, [r7, #12]
- 800664e:	f7ff feff 	bl	8006450 <netif_do_set_ipaddr>
-      change_reason |= LWIP_NSC_IPV4_ADDRESS_CHANGED;
-      cb_args.ipv4_changed.old_address = &old_addr;
-#endif
-    }
-  }
-  if (netif_do_set_netmask(netif, netmask, old_nm)) {
- 8006652:	69fa      	ldr	r2, [r7, #28]
- 8006654:	6879      	ldr	r1, [r7, #4]
- 8006656:	68f8      	ldr	r0, [r7, #12]
- 8006658:	f7ff ff48 	bl	80064ec <netif_do_set_netmask>
-#if LWIP_NETIF_EXT_STATUS_CALLBACK
-    change_reason |= LWIP_NSC_IPV4_NETMASK_CHANGED;
-    cb_args.ipv4_changed.old_netmask = old_nm;
-#endif
-  }
-  if (netif_do_set_gw(netif, gw, old_gw)) {
- 800665c:	69ba      	ldr	r2, [r7, #24]
- 800665e:	6839      	ldr	r1, [r7, #0]
- 8006660:	68f8      	ldr	r0, [r7, #12]
- 8006662:	f7ff ff85 	bl	8006570 <netif_do_set_gw>
-#if LWIP_NETIF_EXT_STATUS_CALLBACK
-    change_reason |= LWIP_NSC_IPV4_GATEWAY_CHANGED;
-    cb_args.ipv4_changed.old_gw = old_gw;
-#endif
-  }
-  if (!remove) {
- 8006666:	697b      	ldr	r3, [r7, #20]
- 8006668:	2b00      	cmp	r3, #0
- 800666a:	d106      	bne.n	800667a <netif_set_addr+0x86>
-    /* set ipaddr last to ensure netmask/gw have been set when status callback is called */
-    if (netif_do_set_ipaddr(netif, ipaddr, &old_addr)) {
- 800666c:	f107 0310 	add.w	r3, r7, #16
- 8006670:	461a      	mov	r2, r3
- 8006672:	68b9      	ldr	r1, [r7, #8]
- 8006674:	68f8      	ldr	r0, [r7, #12]
- 8006676:	f7ff feeb 	bl	8006450 <netif_do_set_ipaddr>
-  if (change_reason != LWIP_NSC_NONE) {
-    change_reason |= LWIP_NSC_IPV4_SETTINGS_CHANGED;
-    netif_invoke_ext_callback(netif, change_reason, &cb_args);
-  }
-#endif
-}
- 800667a:	bf00      	nop
- 800667c:	3720      	adds	r7, #32
- 800667e:	46bd      	mov	sp, r7
- 8006680:	bd80      	pop	{r7, pc}
- 8006682:	bf00      	nop
- 8006684:	08014d94 	.word	0x08014d94
-
-08006688 <netif_set_default>:
- *
- * @param netif the default network interface
- */
-void
-netif_set_default(struct netif *netif)
-{
- 8006688:	b580      	push	{r7, lr}
- 800668a:	b082      	sub	sp, #8
- 800668c:	af00      	add	r7, sp, #0
- 800668e:	6078      	str	r0, [r7, #4]
-    mib2_remove_route_ip4(1, netif);
-  } else {
-    /* install default route */
-    mib2_add_route_ip4(1, netif);
-  }
-  netif_default = netif;
- 8006690:	4a0d      	ldr	r2, [pc, #52]	; (80066c8 <netif_set_default+0x40>)
- 8006692:	687b      	ldr	r3, [r7, #4]
- 8006694:	6013      	str	r3, [r2, #0]
-  LWIP_DEBUGF(NETIF_DEBUG, ("netif: setting default interface %c%c\n",
- 8006696:	687b      	ldr	r3, [r7, #4]
- 8006698:	2b00      	cmp	r3, #0
- 800669a:	d004      	beq.n	80066a6 <netif_set_default+0x1e>
- 800669c:	687b      	ldr	r3, [r7, #4]
- 800669e:	f893 302e 	ldrb.w	r3, [r3, #46]	; 0x2e
- 80066a2:	4619      	mov	r1, r3
- 80066a4:	e000      	b.n	80066a8 <netif_set_default+0x20>
- 80066a6:	2127      	movs	r1, #39	; 0x27
- 80066a8:	687b      	ldr	r3, [r7, #4]
- 80066aa:	2b00      	cmp	r3, #0
- 80066ac:	d003      	beq.n	80066b6 <netif_set_default+0x2e>
- 80066ae:	687b      	ldr	r3, [r7, #4]
- 80066b0:	f893 302f 	ldrb.w	r3, [r3, #47]	; 0x2f
- 80066b4:	e000      	b.n	80066b8 <netif_set_default+0x30>
- 80066b6:	2327      	movs	r3, #39	; 0x27
- 80066b8:	461a      	mov	r2, r3
- 80066ba:	4804      	ldr	r0, [pc, #16]	; (80066cc <netif_set_default+0x44>)
- 80066bc:	f00a fa84 	bl	8010bc8 <iprintf>
-                            netif ? netif->name[0] : '\'', netif ? netif->name[1] : '\''));
-}
- 80066c0:	bf00      	nop
- 80066c2:	3708      	adds	r7, #8
- 80066c4:	46bd      	mov	sp, r7
- 80066c6:	bd80      	pop	{r7, pc}
- 80066c8:	24007b64 	.word	0x24007b64
- 80066cc:	08012400 	.word	0x08012400
-
-080066d0 <netif_set_up>:
- * Bring an interface up, available for processing
- * traffic.
- */
-void
-netif_set_up(struct netif *netif)
-{
- 80066d0:	b580      	push	{r7, lr}
- 80066d2:	b082      	sub	sp, #8
- 80066d4:	af00      	add	r7, sp, #0
- 80066d6:	6078      	str	r0, [r7, #4]
-  LWIP_ASSERT_CORE_LOCKED();
-
-  LWIP_ERROR("netif_set_up: invalid netif", netif != NULL, return);
- 80066d8:	687b      	ldr	r3, [r7, #4]
- 80066da:	2b00      	cmp	r3, #0
- 80066dc:	d107      	bne.n	80066ee <netif_set_up+0x1e>
- 80066de:	4b0f      	ldr	r3, [pc, #60]	; (800671c <netif_set_up+0x4c>)
- 80066e0:	f44f 7254 	mov.w	r2, #848	; 0x350
- 80066e4:	490e      	ldr	r1, [pc, #56]	; (8006720 <netif_set_up+0x50>)
- 80066e6:	480f      	ldr	r0, [pc, #60]	; (8006724 <netif_set_up+0x54>)
- 80066e8:	f00a fa6e 	bl	8010bc8 <iprintf>
- 80066ec:	e013      	b.n	8006716 <netif_set_up+0x46>
-
-  if (!(netif->flags & NETIF_FLAG_UP)) {
- 80066ee:	687b      	ldr	r3, [r7, #4]
- 80066f0:	f893 302d 	ldrb.w	r3, [r3, #45]	; 0x2d
- 80066f4:	f003 0301 	and.w	r3, r3, #1
- 80066f8:	2b00      	cmp	r3, #0
- 80066fa:	d10c      	bne.n	8006716 <netif_set_up+0x46>
-    netif_set_flags(netif, NETIF_FLAG_UP);
- 80066fc:	687b      	ldr	r3, [r7, #4]
- 80066fe:	f893 302d 	ldrb.w	r3, [r3, #45]	; 0x2d
- 8006702:	f043 0301 	orr.w	r3, r3, #1
- 8006706:	b2da      	uxtb	r2, r3
- 8006708:	687b      	ldr	r3, [r7, #4]
- 800670a:	f883 202d 	strb.w	r2, [r3, #45]	; 0x2d
-      args.status_changed.state = 1;
-      netif_invoke_ext_callback(netif, LWIP_NSC_STATUS_CHANGED, &args);
-    }
-#endif
-
-    netif_issue_reports(netif, NETIF_REPORT_TYPE_IPV4 | NETIF_REPORT_TYPE_IPV6);
- 800670e:	2103      	movs	r1, #3
- 8006710:	6878      	ldr	r0, [r7, #4]
- 8006712:	f000 f809 	bl	8006728 <netif_issue_reports>
-#if LWIP_IPV6
-    nd6_restart_netif(netif);
-#endif /* LWIP_IPV6 */
-  }
-}
- 8006716:	3708      	adds	r7, #8
- 8006718:	46bd      	mov	sp, r7
- 800671a:	bd80      	pop	{r7, pc}
- 800671c:	08012168 	.word	0x08012168
- 8006720:	08012428 	.word	0x08012428
- 8006724:	080121b8 	.word	0x080121b8
-
-08006728 <netif_issue_reports>:
-
-/** Send ARP/IGMP/MLD/RS events, e.g. on link-up/netif-up or addr-change
- */
-static void
-netif_issue_reports(struct netif *netif, u8_t report_type)
-{
- 8006728:	b580      	push	{r7, lr}
- 800672a:	b082      	sub	sp, #8
- 800672c:	af00      	add	r7, sp, #0
- 800672e:	6078      	str	r0, [r7, #4]
- 8006730:	460b      	mov	r3, r1
- 8006732:	70fb      	strb	r3, [r7, #3]
-  LWIP_ASSERT("netif_issue_reports: invalid netif", netif != NULL);
- 8006734:	687b      	ldr	r3, [r7, #4]
- 8006736:	2b00      	cmp	r3, #0
- 8006738:	d106      	bne.n	8006748 <netif_issue_reports+0x20>
- 800673a:	4b18      	ldr	r3, [pc, #96]	; (800679c <netif_issue_reports+0x74>)
- 800673c:	f240 326d 	movw	r2, #877	; 0x36d
- 8006740:	4917      	ldr	r1, [pc, #92]	; (80067a0 <netif_issue_reports+0x78>)
- 8006742:	4818      	ldr	r0, [pc, #96]	; (80067a4 <netif_issue_reports+0x7c>)
- 8006744:	f00a fa40 	bl	8010bc8 <iprintf>
-
-  /* Only send reports when both link and admin states are up */
-  if (!(netif->flags & NETIF_FLAG_LINK_UP) ||
- 8006748:	687b      	ldr	r3, [r7, #4]
- 800674a:	f893 302d 	ldrb.w	r3, [r3, #45]	; 0x2d
- 800674e:	f003 0304 	and.w	r3, r3, #4
- 8006752:	2b00      	cmp	r3, #0
- 8006754:	d01e      	beq.n	8006794 <netif_issue_reports+0x6c>
-      !(netif->flags & NETIF_FLAG_UP)) {
- 8006756:	687b      	ldr	r3, [r7, #4]
- 8006758:	f893 302d 	ldrb.w	r3, [r3, #45]	; 0x2d
- 800675c:	f003 0301 	and.w	r3, r3, #1
-  if (!(netif->flags & NETIF_FLAG_LINK_UP) ||
- 8006760:	2b00      	cmp	r3, #0
- 8006762:	d017      	beq.n	8006794 <netif_issue_reports+0x6c>
-    return;
-  }
-
-#if LWIP_IPV4
-  if ((report_type & NETIF_REPORT_TYPE_IPV4) &&
- 8006764:	78fb      	ldrb	r3, [r7, #3]
- 8006766:	f003 0301 	and.w	r3, r3, #1
- 800676a:	2b00      	cmp	r3, #0
- 800676c:	d013      	beq.n	8006796 <netif_issue_reports+0x6e>
-      !ip4_addr_isany_val(*netif_ip4_addr(netif))) {
- 800676e:	687b      	ldr	r3, [r7, #4]
- 8006770:	3304      	adds	r3, #4
- 8006772:	681b      	ldr	r3, [r3, #0]
-  if ((report_type & NETIF_REPORT_TYPE_IPV4) &&
- 8006774:	2b00      	cmp	r3, #0
- 8006776:	d00e      	beq.n	8006796 <netif_issue_reports+0x6e>
-#if LWIP_ARP
-    /* For Ethernet network interfaces, we would like to send a "gratuitous ARP" */
-    if (netif->flags & (NETIF_FLAG_ETHARP)) {
- 8006778:	687b      	ldr	r3, [r7, #4]
- 800677a:	f893 302d 	ldrb.w	r3, [r3, #45]	; 0x2d
- 800677e:	f003 0308 	and.w	r3, r3, #8
- 8006782:	2b00      	cmp	r3, #0
- 8006784:	d007      	beq.n	8006796 <netif_issue_reports+0x6e>
-      etharp_gratuitous(netif);
- 8006786:	687b      	ldr	r3, [r7, #4]
- 8006788:	3304      	adds	r3, #4
- 800678a:	4619      	mov	r1, r3
- 800678c:	6878      	ldr	r0, [r7, #4]
- 800678e:	f008 f91f 	bl	800e9d0 <etharp_request>
- 8006792:	e000      	b.n	8006796 <netif_issue_reports+0x6e>
-    return;
- 8006794:	bf00      	nop
-    /* send mld memberships */
-    mld6_report_groups(netif);
-#endif /* LWIP_IPV6_MLD */
-  }
-#endif /* LWIP_IPV6 */
-}
- 8006796:	3708      	adds	r7, #8
- 8006798:	46bd      	mov	sp, r7
- 800679a:	bd80      	pop	{r7, pc}
- 800679c:	08012168 	.word	0x08012168
- 80067a0:	08012444 	.word	0x08012444
- 80067a4:	080121b8 	.word	0x080121b8
-
-080067a8 <netif_set_down>:
- * @ingroup netif
- * Bring an interface down, disabling any traffic processing.
- */
-void
-netif_set_down(struct netif *netif)
-{
- 80067a8:	b580      	push	{r7, lr}
- 80067aa:	b082      	sub	sp, #8
- 80067ac:	af00      	add	r7, sp, #0
- 80067ae:	6078      	str	r0, [r7, #4]
-  LWIP_ASSERT_CORE_LOCKED();
-
-  LWIP_ERROR("netif_set_down: invalid netif", netif != NULL, return);
- 80067b0:	687b      	ldr	r3, [r7, #4]
- 80067b2:	2b00      	cmp	r3, #0
- 80067b4:	d107      	bne.n	80067c6 <netif_set_down+0x1e>
- 80067b6:	4b12      	ldr	r3, [pc, #72]	; (8006800 <netif_set_down+0x58>)
- 80067b8:	f240 329b 	movw	r2, #923	; 0x39b
- 80067bc:	4911      	ldr	r1, [pc, #68]	; (8006804 <netif_set_down+0x5c>)
- 80067be:	4812      	ldr	r0, [pc, #72]	; (8006808 <netif_set_down+0x60>)
- 80067c0:	f00a fa02 	bl	8010bc8 <iprintf>
- 80067c4:	e019      	b.n	80067fa <netif_set_down+0x52>
-
-  if (netif->flags & NETIF_FLAG_UP) {
- 80067c6:	687b      	ldr	r3, [r7, #4]
- 80067c8:	f893 302d 	ldrb.w	r3, [r3, #45]	; 0x2d
- 80067cc:	f003 0301 	and.w	r3, r3, #1
- 80067d0:	2b00      	cmp	r3, #0
- 80067d2:	d012      	beq.n	80067fa <netif_set_down+0x52>
-      args.status_changed.state = 0;
-      netif_invoke_ext_callback(netif, LWIP_NSC_STATUS_CHANGED, &args);
-    }
-#endif
-
-    netif_clear_flags(netif, NETIF_FLAG_UP);
- 80067d4:	687b      	ldr	r3, [r7, #4]
- 80067d6:	f893 302d 	ldrb.w	r3, [r3, #45]	; 0x2d
- 80067da:	f023 0301 	bic.w	r3, r3, #1
- 80067de:	b2da      	uxtb	r2, r3
- 80067e0:	687b      	ldr	r3, [r7, #4]
- 80067e2:	f883 202d 	strb.w	r2, [r3, #45]	; 0x2d
-    MIB2_COPY_SYSUPTIME_TO(&netif->ts);
-
-#if LWIP_IPV4 && LWIP_ARP
-    if (netif->flags & NETIF_FLAG_ETHARP) {
- 80067e6:	687b      	ldr	r3, [r7, #4]
- 80067e8:	f893 302d 	ldrb.w	r3, [r3, #45]	; 0x2d
- 80067ec:	f003 0308 	and.w	r3, r3, #8
- 80067f0:	2b00      	cmp	r3, #0
- 80067f2:	d002      	beq.n	80067fa <netif_set_down+0x52>
-      etharp_cleanup_netif(netif);
- 80067f4:	6878      	ldr	r0, [r7, #4]
- 80067f6:	f007 fca9 	bl	800e14c <etharp_cleanup_netif>
-    nd6_cleanup_netif(netif);
-#endif /* LWIP_IPV6 */
-
-    NETIF_STATUS_CALLBACK(netif);
-  }
-}
- 80067fa:	3708      	adds	r7, #8
- 80067fc:	46bd      	mov	sp, r7
- 80067fe:	bd80      	pop	{r7, pc}
- 8006800:	08012168 	.word	0x08012168
- 8006804:	08012468 	.word	0x08012468
- 8006808:	080121b8 	.word	0x080121b8
-
-0800680c <netif_set_link_up>:
- * @ingroup netif
- * Called by a driver when its link goes up
- */
-void
-netif_set_link_up(struct netif *netif)
-{
- 800680c:	b580      	push	{r7, lr}
- 800680e:	b082      	sub	sp, #8
- 8006810:	af00      	add	r7, sp, #0
- 8006812:	6078      	str	r0, [r7, #4]
-  LWIP_ASSERT_CORE_LOCKED();
-
-  LWIP_ERROR("netif_set_link_up: invalid netif", netif != NULL, return);
- 8006814:	687b      	ldr	r3, [r7, #4]
- 8006816:	2b00      	cmp	r3, #0
- 8006818:	d107      	bne.n	800682a <netif_set_link_up+0x1e>
- 800681a:	4b13      	ldr	r3, [pc, #76]	; (8006868 <netif_set_link_up+0x5c>)
- 800681c:	f44f 7278 	mov.w	r2, #992	; 0x3e0
- 8006820:	4912      	ldr	r1, [pc, #72]	; (800686c <netif_set_link_up+0x60>)
- 8006822:	4813      	ldr	r0, [pc, #76]	; (8006870 <netif_set_link_up+0x64>)
- 8006824:	f00a f9d0 	bl	8010bc8 <iprintf>
- 8006828:	e01b      	b.n	8006862 <netif_set_link_up+0x56>
-
-  if (!(netif->flags & NETIF_FLAG_LINK_UP)) {
- 800682a:	687b      	ldr	r3, [r7, #4]
- 800682c:	f893 302d 	ldrb.w	r3, [r3, #45]	; 0x2d
- 8006830:	f003 0304 	and.w	r3, r3, #4
- 8006834:	2b00      	cmp	r3, #0
- 8006836:	d114      	bne.n	8006862 <netif_set_link_up+0x56>
-    netif_set_flags(netif, NETIF_FLAG_LINK_UP);
- 8006838:	687b      	ldr	r3, [r7, #4]
- 800683a:	f893 302d 	ldrb.w	r3, [r3, #45]	; 0x2d
- 800683e:	f043 0304 	orr.w	r3, r3, #4
- 8006842:	b2da      	uxtb	r2, r3
- 8006844:	687b      	ldr	r3, [r7, #4]
- 8006846:	f883 202d 	strb.w	r2, [r3, #45]	; 0x2d
-
-#if LWIP_AUTOIP
-    autoip_network_changed(netif);
-#endif /* LWIP_AUTOIP */
-
-    netif_issue_reports(netif, NETIF_REPORT_TYPE_IPV4 | NETIF_REPORT_TYPE_IPV6);
- 800684a:	2103      	movs	r1, #3
- 800684c:	6878      	ldr	r0, [r7, #4]
- 800684e:	f7ff ff6b 	bl	8006728 <netif_issue_reports>
-#if LWIP_IPV6
-    nd6_restart_netif(netif);
-#endif /* LWIP_IPV6 */
-
-    NETIF_LINK_CALLBACK(netif);
- 8006852:	687b      	ldr	r3, [r7, #4]
- 8006854:	69db      	ldr	r3, [r3, #28]
- 8006856:	2b00      	cmp	r3, #0
- 8006858:	d003      	beq.n	8006862 <netif_set_link_up+0x56>
- 800685a:	687b      	ldr	r3, [r7, #4]
- 800685c:	69db      	ldr	r3, [r3, #28]
- 800685e:	6878      	ldr	r0, [r7, #4]
- 8006860:	4798      	blx	r3
-      args.link_changed.state = 1;
-      netif_invoke_ext_callback(netif, LWIP_NSC_LINK_CHANGED, &args);
-    }
-#endif
-  }
-}
- 8006862:	3708      	adds	r7, #8
- 8006864:	46bd      	mov	sp, r7
- 8006866:	bd80      	pop	{r7, pc}
- 8006868:	08012168 	.word	0x08012168
- 800686c:	08012488 	.word	0x08012488
- 8006870:	080121b8 	.word	0x080121b8
-
-08006874 <netif_set_link_down>:
- * @ingroup netif
- * Called by a driver when its link goes down
- */
-void
-netif_set_link_down(struct netif *netif)
-{
- 8006874:	b580      	push	{r7, lr}
- 8006876:	b082      	sub	sp, #8
- 8006878:	af00      	add	r7, sp, #0
- 800687a:	6078      	str	r0, [r7, #4]
-  LWIP_ASSERT_CORE_LOCKED();
-
-  LWIP_ERROR("netif_set_link_down: invalid netif", netif != NULL, return);
- 800687c:	687b      	ldr	r3, [r7, #4]
- 800687e:	2b00      	cmp	r3, #0
- 8006880:	d107      	bne.n	8006892 <netif_set_link_down+0x1e>
- 8006882:	4b11      	ldr	r3, [pc, #68]	; (80068c8 <netif_set_link_down+0x54>)
- 8006884:	f240 4206 	movw	r2, #1030	; 0x406
- 8006888:	4910      	ldr	r1, [pc, #64]	; (80068cc <netif_set_link_down+0x58>)
- 800688a:	4811      	ldr	r0, [pc, #68]	; (80068d0 <netif_set_link_down+0x5c>)
- 800688c:	f00a f99c 	bl	8010bc8 <iprintf>
- 8006890:	e017      	b.n	80068c2 <netif_set_link_down+0x4e>
-
-  if (netif->flags & NETIF_FLAG_LINK_UP) {
- 8006892:	687b      	ldr	r3, [r7, #4]
- 8006894:	f893 302d 	ldrb.w	r3, [r3, #45]	; 0x2d
- 8006898:	f003 0304 	and.w	r3, r3, #4
- 800689c:	2b00      	cmp	r3, #0
- 800689e:	d010      	beq.n	80068c2 <netif_set_link_down+0x4e>
-    netif_clear_flags(netif, NETIF_FLAG_LINK_UP);
- 80068a0:	687b      	ldr	r3, [r7, #4]
- 80068a2:	f893 302d 	ldrb.w	r3, [r3, #45]	; 0x2d
- 80068a6:	f023 0304 	bic.w	r3, r3, #4
- 80068aa:	b2da      	uxtb	r2, r3
- 80068ac:	687b      	ldr	r3, [r7, #4]
- 80068ae:	f883 202d 	strb.w	r2, [r3, #45]	; 0x2d
-    NETIF_LINK_CALLBACK(netif);
- 80068b2:	687b      	ldr	r3, [r7, #4]
- 80068b4:	69db      	ldr	r3, [r3, #28]
- 80068b6:	2b00      	cmp	r3, #0
- 80068b8:	d003      	beq.n	80068c2 <netif_set_link_down+0x4e>
- 80068ba:	687b      	ldr	r3, [r7, #4]
- 80068bc:	69db      	ldr	r3, [r3, #28]
- 80068be:	6878      	ldr	r0, [r7, #4]
- 80068c0:	4798      	blx	r3
-      args.link_changed.state = 0;
-      netif_invoke_ext_callback(netif, LWIP_NSC_LINK_CHANGED, &args);
-    }
-#endif
-  }
-}
- 80068c2:	3708      	adds	r7, #8
- 80068c4:	46bd      	mov	sp, r7
- 80068c6:	bd80      	pop	{r7, pc}
- 80068c8:	08012168 	.word	0x08012168
- 80068cc:	080124ac 	.word	0x080124ac
- 80068d0:	080121b8 	.word	0x080121b8
-
-080068d4 <netif_set_link_callback>:
- * @ingroup netif
- * Set callback to be called when link is brought up/down
- */
-void
-netif_set_link_callback(struct netif *netif, netif_status_callback_fn link_callback)
-{
- 80068d4:	b480      	push	{r7}
- 80068d6:	b083      	sub	sp, #12
- 80068d8:	af00      	add	r7, sp, #0
- 80068da:	6078      	str	r0, [r7, #4]
- 80068dc:	6039      	str	r1, [r7, #0]
-  LWIP_ASSERT_CORE_LOCKED();
-
-  if (netif) {
- 80068de:	687b      	ldr	r3, [r7, #4]
- 80068e0:	2b00      	cmp	r3, #0
- 80068e2:	d002      	beq.n	80068ea <netif_set_link_callback+0x16>
-    netif->link_callback = link_callback;
- 80068e4:	687b      	ldr	r3, [r7, #4]
- 80068e6:	683a      	ldr	r2, [r7, #0]
- 80068e8:	61da      	str	r2, [r3, #28]
-  }
-}
- 80068ea:	bf00      	nop
- 80068ec:	370c      	adds	r7, #12
- 80068ee:	46bd      	mov	sp, r7
- 80068f0:	f85d 7b04 	ldr.w	r7, [sp], #4
- 80068f4:	4770      	bx	lr
-
-080068f6 <netif_null_output_ip4>:
-#if LWIP_IPV4
-/** Dummy IPv4 output function for netifs not supporting IPv4
- */
-static err_t
-netif_null_output_ip4(struct netif *netif, struct pbuf *p, const ip4_addr_t *ipaddr)
-{
- 80068f6:	b480      	push	{r7}
- 80068f8:	b085      	sub	sp, #20
- 80068fa:	af00      	add	r7, sp, #0
- 80068fc:	60f8      	str	r0, [r7, #12]
- 80068fe:	60b9      	str	r1, [r7, #8]
- 8006900:	607a      	str	r2, [r7, #4]
-  LWIP_UNUSED_ARG(netif);
-  LWIP_UNUSED_ARG(p);
-  LWIP_UNUSED_ARG(ipaddr);
-
-  return ERR_IF;
- 8006902:	f06f 030b 	mvn.w	r3, #11
-}
- 8006906:	4618      	mov	r0, r3
- 8006908:	3714      	adds	r7, #20
- 800690a:	46bd      	mov	sp, r7
- 800690c:	f85d 7b04 	ldr.w	r7, [sp], #4
- 8006910:	4770      	bx	lr
-	...
-
-08006914 <netif_get_by_index>:
-*
-* @param idx index of netif to find
-*/
-struct netif *
-netif_get_by_index(u8_t idx)
-{
- 8006914:	b480      	push	{r7}
- 8006916:	b085      	sub	sp, #20
- 8006918:	af00      	add	r7, sp, #0
- 800691a:	4603      	mov	r3, r0
- 800691c:	71fb      	strb	r3, [r7, #7]
-  struct netif *netif;
-
-  LWIP_ASSERT_CORE_LOCKED();
-
-  if (idx != NETIF_NO_INDEX) {
- 800691e:	79fb      	ldrb	r3, [r7, #7]
- 8006920:	2b00      	cmp	r3, #0
- 8006922:	d013      	beq.n	800694c <netif_get_by_index+0x38>
-    NETIF_FOREACH(netif) {
- 8006924:	4b0d      	ldr	r3, [pc, #52]	; (800695c <netif_get_by_index+0x48>)
- 8006926:	681b      	ldr	r3, [r3, #0]
- 8006928:	60fb      	str	r3, [r7, #12]
- 800692a:	e00c      	b.n	8006946 <netif_get_by_index+0x32>
-      if (idx == netif_get_index(netif)) {
- 800692c:	68fb      	ldr	r3, [r7, #12]
- 800692e:	f893 3030 	ldrb.w	r3, [r3, #48]	; 0x30
- 8006932:	3301      	adds	r3, #1
- 8006934:	b2db      	uxtb	r3, r3
- 8006936:	79fa      	ldrb	r2, [r7, #7]
- 8006938:	429a      	cmp	r2, r3
- 800693a:	d101      	bne.n	8006940 <netif_get_by_index+0x2c>
-        return netif; /* found! */
- 800693c:	68fb      	ldr	r3, [r7, #12]
- 800693e:	e006      	b.n	800694e <netif_get_by_index+0x3a>
-    NETIF_FOREACH(netif) {
- 8006940:	68fb      	ldr	r3, [r7, #12]
- 8006942:	681b      	ldr	r3, [r3, #0]
- 8006944:	60fb      	str	r3, [r7, #12]
- 8006946:	68fb      	ldr	r3, [r7, #12]
- 8006948:	2b00      	cmp	r3, #0
- 800694a:	d1ef      	bne.n	800692c <netif_get_by_index+0x18>
-      }
-    }
-  }
-
-  return NULL;
- 800694c:	2300      	movs	r3, #0
-}
- 800694e:	4618      	mov	r0, r3
- 8006950:	3714      	adds	r7, #20
- 8006952:	46bd      	mov	sp, r7
- 8006954:	f85d 7b04 	ldr.w	r7, [sp], #4
- 8006958:	4770      	bx	lr
- 800695a:	bf00      	nop
- 800695c:	24007b60 	.word	0x24007b60
-
-08006960 <pbuf_free_ooseq>:
-#if !NO_SYS
-static
-#endif /* !NO_SYS */
-void
-pbuf_free_ooseq(void)
-{
- 8006960:	b580      	push	{r7, lr}
- 8006962:	b082      	sub	sp, #8
- 8006964:	af00      	add	r7, sp, #0
-  struct tcp_pcb *pcb;
-  SYS_ARCH_SET(pbuf_free_ooseq_pending, 0);
- 8006966:	4b0c      	ldr	r3, [pc, #48]	; (8006998 <pbuf_free_ooseq+0x38>)
- 8006968:	2200      	movs	r2, #0
- 800696a:	701a      	strb	r2, [r3, #0]
-
-  for (pcb = tcp_active_pcbs; NULL != pcb; pcb = pcb->next) {
- 800696c:	4b0b      	ldr	r3, [pc, #44]	; (800699c <pbuf_free_ooseq+0x3c>)
- 800696e:	681b      	ldr	r3, [r3, #0]
- 8006970:	607b      	str	r3, [r7, #4]
- 8006972:	e00a      	b.n	800698a <pbuf_free_ooseq+0x2a>
-    if (pcb->ooseq != NULL) {
- 8006974:	687b      	ldr	r3, [r7, #4]
- 8006976:	6f5b      	ldr	r3, [r3, #116]	; 0x74
- 8006978:	2b00      	cmp	r3, #0
- 800697a:	d003      	beq.n	8006984 <pbuf_free_ooseq+0x24>
-      /** Free the ooseq pbufs of one PCB only */
-      LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_free_ooseq: freeing out-of-sequence pbufs\n"));
-      tcp_free_ooseq(pcb);
- 800697c:	6878      	ldr	r0, [r7, #4]
- 800697e:	f002 fb21 	bl	8008fc4 <tcp_free_ooseq>
-      return;
- 8006982:	e005      	b.n	8006990 <pbuf_free_ooseq+0x30>
-  for (pcb = tcp_active_pcbs; NULL != pcb; pcb = pcb->next) {
- 8006984:	687b      	ldr	r3, [r7, #4]
- 8006986:	68db      	ldr	r3, [r3, #12]
- 8006988:	607b      	str	r3, [r7, #4]
- 800698a:	687b      	ldr	r3, [r7, #4]
- 800698c:	2b00      	cmp	r3, #0
- 800698e:	d1f1      	bne.n	8006974 <pbuf_free_ooseq+0x14>
-    }
-  }
-}
- 8006990:	3708      	adds	r7, #8
- 8006992:	46bd      	mov	sp, r7
- 8006994:	bd80      	pop	{r7, pc}
- 8006996:	bf00      	nop
- 8006998:	24007b69 	.word	0x24007b69
- 800699c:	24007b78 	.word	0x24007b78
-
-080069a0 <pbuf_pool_is_empty>:
-#endif /* !NO_SYS */
-
-/** Queue a call to pbuf_free_ooseq if not already queued. */
-static void
-pbuf_pool_is_empty(void)
-{
- 80069a0:	b480      	push	{r7}
- 80069a2:	af00      	add	r7, sp, #0
-#ifndef PBUF_POOL_FREE_OOSEQ_QUEUE_CALL
-  SYS_ARCH_SET(pbuf_free_ooseq_pending, 1);
- 80069a4:	4b03      	ldr	r3, [pc, #12]	; (80069b4 <pbuf_pool_is_empty+0x14>)
- 80069a6:	2201      	movs	r2, #1
- 80069a8:	701a      	strb	r2, [r3, #0]
-  if (!queued) {
-    /* queue a call to pbuf_free_ooseq if not already queued */
-    PBUF_POOL_FREE_OOSEQ_QUEUE_CALL();
-  }
-#endif /* PBUF_POOL_FREE_OOSEQ_QUEUE_CALL */
-}
- 80069aa:	bf00      	nop
- 80069ac:	46bd      	mov	sp, r7
- 80069ae:	f85d 7b04 	ldr.w	r7, [sp], #4
- 80069b2:	4770      	bx	lr
- 80069b4:	24007b69 	.word	0x24007b69
-
-080069b8 <pbuf_init_alloced_pbuf>:
-#endif /* !LWIP_TCP || !TCP_QUEUE_OOSEQ || !PBUF_POOL_FREE_OOSEQ */
-
-/* Initialize members of struct pbuf after allocation */
-static void
-pbuf_init_alloced_pbuf(struct pbuf *p, void *payload, u16_t tot_len, u16_t len, pbuf_type type, u8_t flags)
-{
- 80069b8:	b480      	push	{r7}
- 80069ba:	b085      	sub	sp, #20
- 80069bc:	af00      	add	r7, sp, #0
- 80069be:	60f8      	str	r0, [r7, #12]
- 80069c0:	60b9      	str	r1, [r7, #8]
- 80069c2:	4611      	mov	r1, r2
- 80069c4:	461a      	mov	r2, r3
- 80069c6:	460b      	mov	r3, r1
- 80069c8:	80fb      	strh	r3, [r7, #6]
- 80069ca:	4613      	mov	r3, r2
- 80069cc:	80bb      	strh	r3, [r7, #4]
-  p->next = NULL;
- 80069ce:	68fb      	ldr	r3, [r7, #12]
- 80069d0:	2200      	movs	r2, #0
- 80069d2:	601a      	str	r2, [r3, #0]
-  p->payload = payload;
- 80069d4:	68fb      	ldr	r3, [r7, #12]
- 80069d6:	68ba      	ldr	r2, [r7, #8]
- 80069d8:	605a      	str	r2, [r3, #4]
-  p->tot_len = tot_len;
- 80069da:	68fb      	ldr	r3, [r7, #12]
- 80069dc:	88fa      	ldrh	r2, [r7, #6]
- 80069de:	811a      	strh	r2, [r3, #8]
-  p->len = len;
- 80069e0:	68fb      	ldr	r3, [r7, #12]
- 80069e2:	88ba      	ldrh	r2, [r7, #4]
- 80069e4:	815a      	strh	r2, [r3, #10]
-  p->type_internal = (u8_t)type;
- 80069e6:	8b3b      	ldrh	r3, [r7, #24]
- 80069e8:	b2da      	uxtb	r2, r3
- 80069ea:	68fb      	ldr	r3, [r7, #12]
- 80069ec:	731a      	strb	r2, [r3, #12]
-  p->flags = flags;
- 80069ee:	68fb      	ldr	r3, [r7, #12]
- 80069f0:	7f3a      	ldrb	r2, [r7, #28]
- 80069f2:	735a      	strb	r2, [r3, #13]
-  p->ref = 1;
- 80069f4:	68fb      	ldr	r3, [r7, #12]
- 80069f6:	2201      	movs	r2, #1
- 80069f8:	739a      	strb	r2, [r3, #14]
-  p->if_idx = NETIF_NO_INDEX;
- 80069fa:	68fb      	ldr	r3, [r7, #12]
- 80069fc:	2200      	movs	r2, #0
- 80069fe:	73da      	strb	r2, [r3, #15]
-}
- 8006a00:	bf00      	nop
- 8006a02:	3714      	adds	r7, #20
- 8006a04:	46bd      	mov	sp, r7
- 8006a06:	f85d 7b04 	ldr.w	r7, [sp], #4
- 8006a0a:	4770      	bx	lr
-
-08006a0c <pbuf_alloc>:
- * @return the allocated pbuf. If multiple pbufs where allocated, this
- * is the first pbuf of a pbuf chain.
- */
-struct pbuf *
-pbuf_alloc(pbuf_layer layer, u16_t length, pbuf_type type)
-{
- 8006a0c:	b580      	push	{r7, lr}
- 8006a0e:	b08c      	sub	sp, #48	; 0x30
- 8006a10:	af02      	add	r7, sp, #8
- 8006a12:	4603      	mov	r3, r0
- 8006a14:	71fb      	strb	r3, [r7, #7]
- 8006a16:	460b      	mov	r3, r1
- 8006a18:	80bb      	strh	r3, [r7, #4]
- 8006a1a:	4613      	mov	r3, r2
- 8006a1c:	807b      	strh	r3, [r7, #2]
-  struct pbuf *p;
-  u16_t offset = (u16_t)layer;
- 8006a1e:	79fb      	ldrb	r3, [r7, #7]
- 8006a20:	847b      	strh	r3, [r7, #34]	; 0x22
-  LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_alloc(length=%"U16_F")\n", length));
-
-  switch (type) {
- 8006a22:	887b      	ldrh	r3, [r7, #2]
- 8006a24:	f5b3 7f20 	cmp.w	r3, #640	; 0x280
- 8006a28:	d07f      	beq.n	8006b2a <pbuf_alloc+0x11e>
- 8006a2a:	f5b3 7f20 	cmp.w	r3, #640	; 0x280
- 8006a2e:	f300 80c8 	bgt.w	8006bc2 <pbuf_alloc+0x1b6>
- 8006a32:	f5b3 7fc1 	cmp.w	r3, #386	; 0x182
- 8006a36:	d010      	beq.n	8006a5a <pbuf_alloc+0x4e>
- 8006a38:	f5b3 7fc1 	cmp.w	r3, #386	; 0x182
- 8006a3c:	f300 80c1 	bgt.w	8006bc2 <pbuf_alloc+0x1b6>
- 8006a40:	2b01      	cmp	r3, #1
- 8006a42:	d002      	beq.n	8006a4a <pbuf_alloc+0x3e>
- 8006a44:	2b41      	cmp	r3, #65	; 0x41
- 8006a46:	f040 80bc 	bne.w	8006bc2 <pbuf_alloc+0x1b6>
-    case PBUF_REF: /* fall through */
-    case PBUF_ROM:
-      p = pbuf_alloc_reference(NULL, length, type);
- 8006a4a:	887a      	ldrh	r2, [r7, #2]
- 8006a4c:	88bb      	ldrh	r3, [r7, #4]
- 8006a4e:	4619      	mov	r1, r3
- 8006a50:	2000      	movs	r0, #0
- 8006a52:	f000 f8d1 	bl	8006bf8 <pbuf_alloc_reference>
- 8006a56:	6278      	str	r0, [r7, #36]	; 0x24
-      break;
- 8006a58:	e0bd      	b.n	8006bd6 <pbuf_alloc+0x1ca>
-    case PBUF_POOL: {
-      struct pbuf *q, *last;
-      u16_t rem_len; /* remaining length */
-      p = NULL;
- 8006a5a:	2300      	movs	r3, #0
- 8006a5c:	627b      	str	r3, [r7, #36]	; 0x24
-      last = NULL;
- 8006a5e:	2300      	movs	r3, #0
- 8006a60:	61fb      	str	r3, [r7, #28]
-      rem_len = length;
- 8006a62:	88bb      	ldrh	r3, [r7, #4]
- 8006a64:	837b      	strh	r3, [r7, #26]
-      do {
-        u16_t qlen;
-        q = (struct pbuf *)memp_malloc(MEMP_PBUF_POOL);
- 8006a66:	2008      	movs	r0, #8
- 8006a68:	f7ff fad8 	bl	800601c <memp_malloc>
- 8006a6c:	6138      	str	r0, [r7, #16]
-        if (q == NULL) {
- 8006a6e:	693b      	ldr	r3, [r7, #16]
- 8006a70:	2b00      	cmp	r3, #0
- 8006a72:	d109      	bne.n	8006a88 <pbuf_alloc+0x7c>
-          PBUF_POOL_IS_EMPTY();
- 8006a74:	f7ff ff94 	bl	80069a0 <pbuf_pool_is_empty>
-          /* free chain so far allocated */
-          if (p) {
- 8006a78:	6a7b      	ldr	r3, [r7, #36]	; 0x24
- 8006a7a:	2b00      	cmp	r3, #0
- 8006a7c:	d002      	beq.n	8006a84 <pbuf_alloc+0x78>
-            pbuf_free(p);
- 8006a7e:	6a78      	ldr	r0, [r7, #36]	; 0x24
- 8006a80:	f000 faa8 	bl	8006fd4 <pbuf_free>
-          }
-          /* bail out unsuccessfully */
-          return NULL;
- 8006a84:	2300      	movs	r3, #0
- 8006a86:	e0a7      	b.n	8006bd8 <pbuf_alloc+0x1cc>
-        }
-        qlen = LWIP_MIN(rem_len, (u16_t)(PBUF_POOL_BUFSIZE_ALIGNED - LWIP_MEM_ALIGN_SIZE(offset)));
- 8006a88:	8c7b      	ldrh	r3, [r7, #34]	; 0x22
- 8006a8a:	3303      	adds	r3, #3
- 8006a8c:	b29b      	uxth	r3, r3
- 8006a8e:	f023 0303 	bic.w	r3, r3, #3
- 8006a92:	b29b      	uxth	r3, r3
- 8006a94:	f5c3 7314 	rsb	r3, r3, #592	; 0x250
- 8006a98:	b29b      	uxth	r3, r3
- 8006a9a:	8b7a      	ldrh	r2, [r7, #26]
- 8006a9c:	4293      	cmp	r3, r2
- 8006a9e:	bf28      	it	cs
- 8006aa0:	4613      	movcs	r3, r2
- 8006aa2:	81fb      	strh	r3, [r7, #14]
-        pbuf_init_alloced_pbuf(q, LWIP_MEM_ALIGN((void *)((u8_t *)q + SIZEOF_STRUCT_PBUF + offset)),
- 8006aa4:	8c7b      	ldrh	r3, [r7, #34]	; 0x22
- 8006aa6:	3310      	adds	r3, #16
- 8006aa8:	693a      	ldr	r2, [r7, #16]
- 8006aaa:	4413      	add	r3, r2
- 8006aac:	3303      	adds	r3, #3
- 8006aae:	f023 0303 	bic.w	r3, r3, #3
- 8006ab2:	4618      	mov	r0, r3
- 8006ab4:	89f9      	ldrh	r1, [r7, #14]
- 8006ab6:	8b7a      	ldrh	r2, [r7, #26]
- 8006ab8:	2300      	movs	r3, #0
- 8006aba:	9301      	str	r3, [sp, #4]
- 8006abc:	887b      	ldrh	r3, [r7, #2]
- 8006abe:	9300      	str	r3, [sp, #0]
- 8006ac0:	460b      	mov	r3, r1
- 8006ac2:	4601      	mov	r1, r0
- 8006ac4:	6938      	ldr	r0, [r7, #16]
- 8006ac6:	f7ff ff77 	bl	80069b8 <pbuf_init_alloced_pbuf>
-                               rem_len, qlen, type, 0);
-        LWIP_ASSERT("pbuf_alloc: pbuf q->payload properly aligned",
- 8006aca:	693b      	ldr	r3, [r7, #16]
- 8006acc:	685b      	ldr	r3, [r3, #4]
- 8006ace:	f003 0303 	and.w	r3, r3, #3
- 8006ad2:	2b00      	cmp	r3, #0
- 8006ad4:	d006      	beq.n	8006ae4 <pbuf_alloc+0xd8>
- 8006ad6:	4b42      	ldr	r3, [pc, #264]	; (8006be0 <pbuf_alloc+0x1d4>)
- 8006ad8:	f44f 7280 	mov.w	r2, #256	; 0x100
- 8006adc:	4941      	ldr	r1, [pc, #260]	; (8006be4 <pbuf_alloc+0x1d8>)
- 8006ade:	4842      	ldr	r0, [pc, #264]	; (8006be8 <pbuf_alloc+0x1dc>)
- 8006ae0:	f00a f872 	bl	8010bc8 <iprintf>
-                    ((mem_ptr_t)q->payload % MEM_ALIGNMENT) == 0);
-        LWIP_ASSERT("PBUF_POOL_BUFSIZE must be bigger than MEM_ALIGNMENT",
- 8006ae4:	8c7b      	ldrh	r3, [r7, #34]	; 0x22
- 8006ae6:	3303      	adds	r3, #3
- 8006ae8:	f023 0303 	bic.w	r3, r3, #3
- 8006aec:	f5b3 7f14 	cmp.w	r3, #592	; 0x250
- 8006af0:	d106      	bne.n	8006b00 <pbuf_alloc+0xf4>
- 8006af2:	4b3b      	ldr	r3, [pc, #236]	; (8006be0 <pbuf_alloc+0x1d4>)
- 8006af4:	f44f 7281 	mov.w	r2, #258	; 0x102
- 8006af8:	493c      	ldr	r1, [pc, #240]	; (8006bec <pbuf_alloc+0x1e0>)
- 8006afa:	483b      	ldr	r0, [pc, #236]	; (8006be8 <pbuf_alloc+0x1dc>)
- 8006afc:	f00a f864 	bl	8010bc8 <iprintf>
-                    (PBUF_POOL_BUFSIZE_ALIGNED - LWIP_MEM_ALIGN_SIZE(offset)) > 0 );
-        if (p == NULL) {
- 8006b00:	6a7b      	ldr	r3, [r7, #36]	; 0x24
- 8006b02:	2b00      	cmp	r3, #0
- 8006b04:	d102      	bne.n	8006b0c <pbuf_alloc+0x100>
-          /* allocated head of pbuf chain (into p) */
-          p = q;
- 8006b06:	693b      	ldr	r3, [r7, #16]
- 8006b08:	627b      	str	r3, [r7, #36]	; 0x24
- 8006b0a:	e002      	b.n	8006b12 <pbuf_alloc+0x106>
-        } else {
-          /* make previous pbuf point to this pbuf */
-          last->next = q;
- 8006b0c:	69fb      	ldr	r3, [r7, #28]
- 8006b0e:	693a      	ldr	r2, [r7, #16]
- 8006b10:	601a      	str	r2, [r3, #0]
-        }
-        last = q;
- 8006b12:	693b      	ldr	r3, [r7, #16]
- 8006b14:	61fb      	str	r3, [r7, #28]
-        rem_len = (u16_t)(rem_len - qlen);
- 8006b16:	8b7a      	ldrh	r2, [r7, #26]
- 8006b18:	89fb      	ldrh	r3, [r7, #14]
- 8006b1a:	1ad3      	subs	r3, r2, r3
- 8006b1c:	837b      	strh	r3, [r7, #26]
-        offset = 0;
- 8006b1e:	2300      	movs	r3, #0
- 8006b20:	847b      	strh	r3, [r7, #34]	; 0x22
-      } while (rem_len > 0);
- 8006b22:	8b7b      	ldrh	r3, [r7, #26]
- 8006b24:	2b00      	cmp	r3, #0
- 8006b26:	d19e      	bne.n	8006a66 <pbuf_alloc+0x5a>
-      break;
- 8006b28:	e055      	b.n	8006bd6 <pbuf_alloc+0x1ca>
-    }
-    case PBUF_RAM: {
-      u16_t payload_len = (u16_t)(LWIP_MEM_ALIGN_SIZE(offset) + LWIP_MEM_ALIGN_SIZE(length));
- 8006b2a:	8c7b      	ldrh	r3, [r7, #34]	; 0x22
- 8006b2c:	3303      	adds	r3, #3
- 8006b2e:	b29b      	uxth	r3, r3
- 8006b30:	f023 0303 	bic.w	r3, r3, #3
- 8006b34:	b29a      	uxth	r2, r3
- 8006b36:	88bb      	ldrh	r3, [r7, #4]
- 8006b38:	3303      	adds	r3, #3
- 8006b3a:	b29b      	uxth	r3, r3
- 8006b3c:	f023 0303 	bic.w	r3, r3, #3
- 8006b40:	b29b      	uxth	r3, r3
- 8006b42:	4413      	add	r3, r2
- 8006b44:	833b      	strh	r3, [r7, #24]
-      mem_size_t alloc_len = (mem_size_t)(LWIP_MEM_ALIGN_SIZE(SIZEOF_STRUCT_PBUF) + payload_len);
- 8006b46:	8b3b      	ldrh	r3, [r7, #24]
- 8006b48:	3310      	adds	r3, #16
- 8006b4a:	82fb      	strh	r3, [r7, #22]
-
-      /* bug #50040: Check for integer overflow when calculating alloc_len */
-      if ((payload_len < LWIP_MEM_ALIGN_SIZE(length)) ||
- 8006b4c:	8b3a      	ldrh	r2, [r7, #24]
- 8006b4e:	88bb      	ldrh	r3, [r7, #4]
- 8006b50:	3303      	adds	r3, #3
- 8006b52:	f023 0303 	bic.w	r3, r3, #3
- 8006b56:	429a      	cmp	r2, r3
- 8006b58:	d306      	bcc.n	8006b68 <pbuf_alloc+0x15c>
-          (alloc_len < LWIP_MEM_ALIGN_SIZE(length))) {
- 8006b5a:	8afa      	ldrh	r2, [r7, #22]
- 8006b5c:	88bb      	ldrh	r3, [r7, #4]
- 8006b5e:	3303      	adds	r3, #3
- 8006b60:	f023 0303 	bic.w	r3, r3, #3
-      if ((payload_len < LWIP_MEM_ALIGN_SIZE(length)) ||
- 8006b64:	429a      	cmp	r2, r3
- 8006b66:	d201      	bcs.n	8006b6c <pbuf_alloc+0x160>
-        return NULL;
- 8006b68:	2300      	movs	r3, #0
- 8006b6a:	e035      	b.n	8006bd8 <pbuf_alloc+0x1cc>
-      }
-
-      /* If pbuf is to be allocated in RAM, allocate memory for it. */
-      p = (struct pbuf *)mem_malloc(alloc_len);
- 8006b6c:	8afb      	ldrh	r3, [r7, #22]
- 8006b6e:	4618      	mov	r0, r3
- 8006b70:	f7ff f8b0 	bl	8005cd4 <mem_malloc>
- 8006b74:	6278      	str	r0, [r7, #36]	; 0x24
-      if (p == NULL) {
- 8006b76:	6a7b      	ldr	r3, [r7, #36]	; 0x24
- 8006b78:	2b00      	cmp	r3, #0
- 8006b7a:	d101      	bne.n	8006b80 <pbuf_alloc+0x174>
-        return NULL;
- 8006b7c:	2300      	movs	r3, #0
- 8006b7e:	e02b      	b.n	8006bd8 <pbuf_alloc+0x1cc>
-      }
-      pbuf_init_alloced_pbuf(p, LWIP_MEM_ALIGN((void *)((u8_t *)p + SIZEOF_STRUCT_PBUF + offset)),
- 8006b80:	8c7b      	ldrh	r3, [r7, #34]	; 0x22
- 8006b82:	3310      	adds	r3, #16
- 8006b84:	6a7a      	ldr	r2, [r7, #36]	; 0x24
- 8006b86:	4413      	add	r3, r2
- 8006b88:	3303      	adds	r3, #3
- 8006b8a:	f023 0303 	bic.w	r3, r3, #3
- 8006b8e:	4618      	mov	r0, r3
- 8006b90:	88b9      	ldrh	r1, [r7, #4]
- 8006b92:	88ba      	ldrh	r2, [r7, #4]
- 8006b94:	2300      	movs	r3, #0
- 8006b96:	9301      	str	r3, [sp, #4]
- 8006b98:	887b      	ldrh	r3, [r7, #2]
- 8006b9a:	9300      	str	r3, [sp, #0]
- 8006b9c:	460b      	mov	r3, r1
- 8006b9e:	4601      	mov	r1, r0
- 8006ba0:	6a78      	ldr	r0, [r7, #36]	; 0x24
- 8006ba2:	f7ff ff09 	bl	80069b8 <pbuf_init_alloced_pbuf>
-                             length, length, type, 0);
-      LWIP_ASSERT("pbuf_alloc: pbuf->payload properly aligned",
- 8006ba6:	6a7b      	ldr	r3, [r7, #36]	; 0x24
- 8006ba8:	685b      	ldr	r3, [r3, #4]
- 8006baa:	f003 0303 	and.w	r3, r3, #3
- 8006bae:	2b00      	cmp	r3, #0
- 8006bb0:	d010      	beq.n	8006bd4 <pbuf_alloc+0x1c8>
- 8006bb2:	4b0b      	ldr	r3, [pc, #44]	; (8006be0 <pbuf_alloc+0x1d4>)
- 8006bb4:	f44f 7291 	mov.w	r2, #290	; 0x122
- 8006bb8:	490d      	ldr	r1, [pc, #52]	; (8006bf0 <pbuf_alloc+0x1e4>)
- 8006bba:	480b      	ldr	r0, [pc, #44]	; (8006be8 <pbuf_alloc+0x1dc>)
- 8006bbc:	f00a f804 	bl	8010bc8 <iprintf>
-                  ((mem_ptr_t)p->payload % MEM_ALIGNMENT) == 0);
-      break;
- 8006bc0:	e008      	b.n	8006bd4 <pbuf_alloc+0x1c8>
-    }
-    default:
-      LWIP_ASSERT("pbuf_alloc: erroneous type", 0);
- 8006bc2:	4b07      	ldr	r3, [pc, #28]	; (8006be0 <pbuf_alloc+0x1d4>)
- 8006bc4:	f240 1227 	movw	r2, #295	; 0x127
- 8006bc8:	490a      	ldr	r1, [pc, #40]	; (8006bf4 <pbuf_alloc+0x1e8>)
- 8006bca:	4807      	ldr	r0, [pc, #28]	; (8006be8 <pbuf_alloc+0x1dc>)
- 8006bcc:	f009 fffc 	bl	8010bc8 <iprintf>
-      return NULL;
- 8006bd0:	2300      	movs	r3, #0
- 8006bd2:	e001      	b.n	8006bd8 <pbuf_alloc+0x1cc>
-      break;
- 8006bd4:	bf00      	nop
-  }
-  LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_alloc(length=%"U16_F") == %p\n", length, (void *)p));
-  return p;
- 8006bd6:	6a7b      	ldr	r3, [r7, #36]	; 0x24
-}
- 8006bd8:	4618      	mov	r0, r3
- 8006bda:	3728      	adds	r7, #40	; 0x28
- 8006bdc:	46bd      	mov	sp, r7
- 8006bde:	bd80      	pop	{r7, pc}
- 8006be0:	08012508 	.word	0x08012508
- 8006be4:	08012538 	.word	0x08012538
- 8006be8:	08012568 	.word	0x08012568
- 8006bec:	08012590 	.word	0x08012590
- 8006bf0:	080125c4 	.word	0x080125c4
- 8006bf4:	080125f0 	.word	0x080125f0
-
-08006bf8 <pbuf_alloc_reference>:
- *
- * @return the allocated pbuf.
- */
-struct pbuf *
-pbuf_alloc_reference(void *payload, u16_t length, pbuf_type type)
-{
- 8006bf8:	b580      	push	{r7, lr}
- 8006bfa:	b086      	sub	sp, #24
- 8006bfc:	af02      	add	r7, sp, #8
- 8006bfe:	6078      	str	r0, [r7, #4]
- 8006c00:	460b      	mov	r3, r1
- 8006c02:	807b      	strh	r3, [r7, #2]
- 8006c04:	4613      	mov	r3, r2
- 8006c06:	803b      	strh	r3, [r7, #0]
-  struct pbuf *p;
-  LWIP_ASSERT("invalid pbuf_type", (type == PBUF_REF) || (type == PBUF_ROM));
- 8006c08:	883b      	ldrh	r3, [r7, #0]
- 8006c0a:	2b41      	cmp	r3, #65	; 0x41
- 8006c0c:	d009      	beq.n	8006c22 <pbuf_alloc_reference+0x2a>
- 8006c0e:	883b      	ldrh	r3, [r7, #0]
- 8006c10:	2b01      	cmp	r3, #1
- 8006c12:	d006      	beq.n	8006c22 <pbuf_alloc_reference+0x2a>
- 8006c14:	4b0f      	ldr	r3, [pc, #60]	; (8006c54 <pbuf_alloc_reference+0x5c>)
- 8006c16:	f44f 72a5 	mov.w	r2, #330	; 0x14a
- 8006c1a:	490f      	ldr	r1, [pc, #60]	; (8006c58 <pbuf_alloc_reference+0x60>)
- 8006c1c:	480f      	ldr	r0, [pc, #60]	; (8006c5c <pbuf_alloc_reference+0x64>)
- 8006c1e:	f009 ffd3 	bl	8010bc8 <iprintf>
-  /* only allocate memory for the pbuf structure */
-  p = (struct pbuf *)memp_malloc(MEMP_PBUF);
- 8006c22:	2007      	movs	r0, #7
- 8006c24:	f7ff f9fa 	bl	800601c <memp_malloc>
- 8006c28:	60f8      	str	r0, [r7, #12]
-  if (p == NULL) {
- 8006c2a:	68fb      	ldr	r3, [r7, #12]
- 8006c2c:	2b00      	cmp	r3, #0
- 8006c2e:	d101      	bne.n	8006c34 <pbuf_alloc_reference+0x3c>
-    LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_LEVEL_SERIOUS,
-                ("pbuf_alloc_reference: Could not allocate MEMP_PBUF for PBUF_%s.\n",
-                 (type == PBUF_ROM) ? "ROM" : "REF"));
-    return NULL;
- 8006c30:	2300      	movs	r3, #0
- 8006c32:	e00b      	b.n	8006c4c <pbuf_alloc_reference+0x54>
-  }
-  pbuf_init_alloced_pbuf(p, payload, length, length, type, 0);
- 8006c34:	8879      	ldrh	r1, [r7, #2]
- 8006c36:	887a      	ldrh	r2, [r7, #2]
- 8006c38:	2300      	movs	r3, #0
- 8006c3a:	9301      	str	r3, [sp, #4]
- 8006c3c:	883b      	ldrh	r3, [r7, #0]
- 8006c3e:	9300      	str	r3, [sp, #0]
- 8006c40:	460b      	mov	r3, r1
- 8006c42:	6879      	ldr	r1, [r7, #4]
- 8006c44:	68f8      	ldr	r0, [r7, #12]
- 8006c46:	f7ff feb7 	bl	80069b8 <pbuf_init_alloced_pbuf>
-  return p;
- 8006c4a:	68fb      	ldr	r3, [r7, #12]
-}
- 8006c4c:	4618      	mov	r0, r3
- 8006c4e:	3710      	adds	r7, #16
- 8006c50:	46bd      	mov	sp, r7
- 8006c52:	bd80      	pop	{r7, pc}
- 8006c54:	08012508 	.word	0x08012508
- 8006c58:	0801260c 	.word	0x0801260c
- 8006c5c:	08012568 	.word	0x08012568
-
-08006c60 <pbuf_alloced_custom>:
- *        big enough to hold 'length' plus the header size
- */
-struct pbuf *
-pbuf_alloced_custom(pbuf_layer l, u16_t length, pbuf_type type, struct pbuf_custom *p,
-                    void *payload_mem, u16_t payload_mem_len)
-{
- 8006c60:	b580      	push	{r7, lr}
- 8006c62:	b088      	sub	sp, #32
- 8006c64:	af02      	add	r7, sp, #8
- 8006c66:	607b      	str	r3, [r7, #4]
- 8006c68:	4603      	mov	r3, r0
- 8006c6a:	73fb      	strb	r3, [r7, #15]
- 8006c6c:	460b      	mov	r3, r1
- 8006c6e:	81bb      	strh	r3, [r7, #12]
- 8006c70:	4613      	mov	r3, r2
- 8006c72:	817b      	strh	r3, [r7, #10]
-  u16_t offset = (u16_t)l;
- 8006c74:	7bfb      	ldrb	r3, [r7, #15]
- 8006c76:	827b      	strh	r3, [r7, #18]
-  void *payload;
-  LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_alloced_custom(length=%"U16_F")\n", length));
-
-  if (LWIP_MEM_ALIGN_SIZE(offset) + length > payload_mem_len) {
- 8006c78:	8a7b      	ldrh	r3, [r7, #18]
- 8006c7a:	3303      	adds	r3, #3
- 8006c7c:	f023 0203 	bic.w	r2, r3, #3
- 8006c80:	89bb      	ldrh	r3, [r7, #12]
- 8006c82:	441a      	add	r2, r3
- 8006c84:	8cbb      	ldrh	r3, [r7, #36]	; 0x24
- 8006c86:	429a      	cmp	r2, r3
- 8006c88:	d901      	bls.n	8006c8e <pbuf_alloced_custom+0x2e>
-    LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_LEVEL_WARNING, ("pbuf_alloced_custom(length=%"U16_F") buffer too short\n", length));
-    return NULL;
- 8006c8a:	2300      	movs	r3, #0
- 8006c8c:	e018      	b.n	8006cc0 <pbuf_alloced_custom+0x60>
-  }
-
-  if (payload_mem != NULL) {
- 8006c8e:	6a3b      	ldr	r3, [r7, #32]
- 8006c90:	2b00      	cmp	r3, #0
- 8006c92:	d007      	beq.n	8006ca4 <pbuf_alloced_custom+0x44>
-    payload = (u8_t *)payload_mem + LWIP_MEM_ALIGN_SIZE(offset);
- 8006c94:	8a7b      	ldrh	r3, [r7, #18]
- 8006c96:	3303      	adds	r3, #3
- 8006c98:	f023 0303 	bic.w	r3, r3, #3
- 8006c9c:	6a3a      	ldr	r2, [r7, #32]
- 8006c9e:	4413      	add	r3, r2
- 8006ca0:	617b      	str	r3, [r7, #20]
- 8006ca2:	e001      	b.n	8006ca8 <pbuf_alloced_custom+0x48>
-  } else {
-    payload = NULL;
- 8006ca4:	2300      	movs	r3, #0
- 8006ca6:	617b      	str	r3, [r7, #20]
-  }
-  pbuf_init_alloced_pbuf(&p->pbuf, payload, length, length, type, PBUF_FLAG_IS_CUSTOM);
- 8006ca8:	6878      	ldr	r0, [r7, #4]
- 8006caa:	89b9      	ldrh	r1, [r7, #12]
- 8006cac:	89ba      	ldrh	r2, [r7, #12]
- 8006cae:	2302      	movs	r3, #2
- 8006cb0:	9301      	str	r3, [sp, #4]
- 8006cb2:	897b      	ldrh	r3, [r7, #10]
- 8006cb4:	9300      	str	r3, [sp, #0]
- 8006cb6:	460b      	mov	r3, r1
- 8006cb8:	6979      	ldr	r1, [r7, #20]
- 8006cba:	f7ff fe7d 	bl	80069b8 <pbuf_init_alloced_pbuf>
-  return &p->pbuf;
- 8006cbe:	687b      	ldr	r3, [r7, #4]
-}
- 8006cc0:	4618      	mov	r0, r3
- 8006cc2:	3718      	adds	r7, #24
- 8006cc4:	46bd      	mov	sp, r7
- 8006cc6:	bd80      	pop	{r7, pc}
-
-08006cc8 <pbuf_realloc>:
- *
- * @note Despite its name, pbuf_realloc cannot grow the size of a pbuf (chain).
- */
-void
-pbuf_realloc(struct pbuf *p, u16_t new_len)
-{
- 8006cc8:	b580      	push	{r7, lr}
- 8006cca:	b084      	sub	sp, #16
- 8006ccc:	af00      	add	r7, sp, #0
- 8006cce:	6078      	str	r0, [r7, #4]
- 8006cd0:	460b      	mov	r3, r1
- 8006cd2:	807b      	strh	r3, [r7, #2]
-  struct pbuf *q;
-  u16_t rem_len; /* remaining length */
-  u16_t shrink;
-
-  LWIP_ASSERT("pbuf_realloc: p != NULL", p != NULL);
- 8006cd4:	687b      	ldr	r3, [r7, #4]
- 8006cd6:	2b00      	cmp	r3, #0
- 8006cd8:	d106      	bne.n	8006ce8 <pbuf_realloc+0x20>
- 8006cda:	4b3a      	ldr	r3, [pc, #232]	; (8006dc4 <pbuf_realloc+0xfc>)
- 8006cdc:	f44f 72cc 	mov.w	r2, #408	; 0x198
- 8006ce0:	4939      	ldr	r1, [pc, #228]	; (8006dc8 <pbuf_realloc+0x100>)
- 8006ce2:	483a      	ldr	r0, [pc, #232]	; (8006dcc <pbuf_realloc+0x104>)
- 8006ce4:	f009 ff70 	bl	8010bc8 <iprintf>
-
-  /* desired length larger than current length? */
-  if (new_len >= p->tot_len) {
- 8006ce8:	687b      	ldr	r3, [r7, #4]
- 8006cea:	891b      	ldrh	r3, [r3, #8]
- 8006cec:	887a      	ldrh	r2, [r7, #2]
- 8006cee:	429a      	cmp	r2, r3
- 8006cf0:	d263      	bcs.n	8006dba <pbuf_realloc+0xf2>
-    return;
-  }
-
-  /* the pbuf chain grows by (new_len - p->tot_len) bytes
-   * (which may be negative in case of shrinking) */
-  shrink = (u16_t)(p->tot_len - new_len);
- 8006cf2:	687b      	ldr	r3, [r7, #4]
- 8006cf4:	891a      	ldrh	r2, [r3, #8]
- 8006cf6:	887b      	ldrh	r3, [r7, #2]
- 8006cf8:	1ad3      	subs	r3, r2, r3
- 8006cfa:	813b      	strh	r3, [r7, #8]
-
-  /* first, step over any pbufs that should remain in the chain */
-  rem_len = new_len;
- 8006cfc:	887b      	ldrh	r3, [r7, #2]
- 8006cfe:	817b      	strh	r3, [r7, #10]
-  q = p;
- 8006d00:	687b      	ldr	r3, [r7, #4]
- 8006d02:	60fb      	str	r3, [r7, #12]
-  /* should this pbuf be kept? */
-  while (rem_len > q->len) {
- 8006d04:	e018      	b.n	8006d38 <pbuf_realloc+0x70>
-    /* decrease remaining length by pbuf length */
-    rem_len = (u16_t)(rem_len - q->len);
- 8006d06:	68fb      	ldr	r3, [r7, #12]
- 8006d08:	895b      	ldrh	r3, [r3, #10]
- 8006d0a:	897a      	ldrh	r2, [r7, #10]
- 8006d0c:	1ad3      	subs	r3, r2, r3
- 8006d0e:	817b      	strh	r3, [r7, #10]
-    /* decrease total length indicator */
-    q->tot_len = (u16_t)(q->tot_len - shrink);
- 8006d10:	68fb      	ldr	r3, [r7, #12]
- 8006d12:	891a      	ldrh	r2, [r3, #8]
- 8006d14:	893b      	ldrh	r3, [r7, #8]
- 8006d16:	1ad3      	subs	r3, r2, r3
- 8006d18:	b29a      	uxth	r2, r3
- 8006d1a:	68fb      	ldr	r3, [r7, #12]
- 8006d1c:	811a      	strh	r2, [r3, #8]
-    /* proceed to next pbuf in chain */
-    q = q->next;
- 8006d1e:	68fb      	ldr	r3, [r7, #12]
- 8006d20:	681b      	ldr	r3, [r3, #0]
- 8006d22:	60fb      	str	r3, [r7, #12]
-    LWIP_ASSERT("pbuf_realloc: q != NULL", q != NULL);
- 8006d24:	68fb      	ldr	r3, [r7, #12]
- 8006d26:	2b00      	cmp	r3, #0
- 8006d28:	d106      	bne.n	8006d38 <pbuf_realloc+0x70>
- 8006d2a:	4b26      	ldr	r3, [pc, #152]	; (8006dc4 <pbuf_realloc+0xfc>)
- 8006d2c:	f240 12af 	movw	r2, #431	; 0x1af
- 8006d30:	4927      	ldr	r1, [pc, #156]	; (8006dd0 <pbuf_realloc+0x108>)
- 8006d32:	4826      	ldr	r0, [pc, #152]	; (8006dcc <pbuf_realloc+0x104>)
- 8006d34:	f009 ff48 	bl	8010bc8 <iprintf>
-  while (rem_len > q->len) {
- 8006d38:	68fb      	ldr	r3, [r7, #12]
- 8006d3a:	895b      	ldrh	r3, [r3, #10]
- 8006d3c:	897a      	ldrh	r2, [r7, #10]
- 8006d3e:	429a      	cmp	r2, r3
- 8006d40:	d8e1      	bhi.n	8006d06 <pbuf_realloc+0x3e>
-  /* we have now reached the new last pbuf (in q) */
-  /* rem_len == desired length for pbuf q */
-
-  /* shrink allocated memory for PBUF_RAM */
-  /* (other types merely adjust their length fields */
-  if (pbuf_match_allocsrc(q, PBUF_TYPE_ALLOC_SRC_MASK_STD_HEAP) && (rem_len != q->len)
- 8006d42:	68fb      	ldr	r3, [r7, #12]
- 8006d44:	7b1b      	ldrb	r3, [r3, #12]
- 8006d46:	f003 030f 	and.w	r3, r3, #15
- 8006d4a:	2b00      	cmp	r3, #0
- 8006d4c:	d121      	bne.n	8006d92 <pbuf_realloc+0xca>
- 8006d4e:	68fb      	ldr	r3, [r7, #12]
- 8006d50:	895b      	ldrh	r3, [r3, #10]
- 8006d52:	897a      	ldrh	r2, [r7, #10]
- 8006d54:	429a      	cmp	r2, r3
- 8006d56:	d01c      	beq.n	8006d92 <pbuf_realloc+0xca>
-#if LWIP_SUPPORT_CUSTOM_PBUF
-      && ((q->flags & PBUF_FLAG_IS_CUSTOM) == 0)
- 8006d58:	68fb      	ldr	r3, [r7, #12]
- 8006d5a:	7b5b      	ldrb	r3, [r3, #13]
- 8006d5c:	f003 0302 	and.w	r3, r3, #2
- 8006d60:	2b00      	cmp	r3, #0
- 8006d62:	d116      	bne.n	8006d92 <pbuf_realloc+0xca>
-#endif /* LWIP_SUPPORT_CUSTOM_PBUF */
-     ) {
-    /* reallocate and adjust the length of the pbuf that will be split */
-    q = (struct pbuf *)mem_trim(q, (mem_size_t)(((u8_t *)q->payload - (u8_t *)q) + rem_len));
- 8006d64:	68fb      	ldr	r3, [r7, #12]
- 8006d66:	685a      	ldr	r2, [r3, #4]
- 8006d68:	68fb      	ldr	r3, [r7, #12]
- 8006d6a:	1ad3      	subs	r3, r2, r3
- 8006d6c:	b29a      	uxth	r2, r3
- 8006d6e:	897b      	ldrh	r3, [r7, #10]
- 8006d70:	4413      	add	r3, r2
- 8006d72:	b29b      	uxth	r3, r3
- 8006d74:	4619      	mov	r1, r3
- 8006d76:	68f8      	ldr	r0, [r7, #12]
- 8006d78:	f7fe fea6 	bl	8005ac8 <mem_trim>
- 8006d7c:	60f8      	str	r0, [r7, #12]
-    LWIP_ASSERT("mem_trim returned q == NULL", q != NULL);
- 8006d7e:	68fb      	ldr	r3, [r7, #12]
- 8006d80:	2b00      	cmp	r3, #0
- 8006d82:	d106      	bne.n	8006d92 <pbuf_realloc+0xca>
- 8006d84:	4b0f      	ldr	r3, [pc, #60]	; (8006dc4 <pbuf_realloc+0xfc>)
- 8006d86:	f240 12bd 	movw	r2, #445	; 0x1bd
- 8006d8a:	4912      	ldr	r1, [pc, #72]	; (8006dd4 <pbuf_realloc+0x10c>)
- 8006d8c:	480f      	ldr	r0, [pc, #60]	; (8006dcc <pbuf_realloc+0x104>)
- 8006d8e:	f009 ff1b 	bl	8010bc8 <iprintf>
-  }
-  /* adjust length fields for new last pbuf */
-  q->len = rem_len;
- 8006d92:	68fb      	ldr	r3, [r7, #12]
- 8006d94:	897a      	ldrh	r2, [r7, #10]
- 8006d96:	815a      	strh	r2, [r3, #10]
-  q->tot_len = q->len;
- 8006d98:	68fb      	ldr	r3, [r7, #12]
- 8006d9a:	895a      	ldrh	r2, [r3, #10]
- 8006d9c:	68fb      	ldr	r3, [r7, #12]
- 8006d9e:	811a      	strh	r2, [r3, #8]
-
-  /* any remaining pbufs in chain? */
-  if (q->next != NULL) {
- 8006da0:	68fb      	ldr	r3, [r7, #12]
- 8006da2:	681b      	ldr	r3, [r3, #0]
- 8006da4:	2b00      	cmp	r3, #0
- 8006da6:	d004      	beq.n	8006db2 <pbuf_realloc+0xea>
-    /* free remaining pbufs in chain */
-    pbuf_free(q->next);
- 8006da8:	68fb      	ldr	r3, [r7, #12]
- 8006daa:	681b      	ldr	r3, [r3, #0]
- 8006dac:	4618      	mov	r0, r3
- 8006dae:	f000 f911 	bl	8006fd4 <pbuf_free>
-  }
-  /* q is last packet in chain */
-  q->next = NULL;
- 8006db2:	68fb      	ldr	r3, [r7, #12]
- 8006db4:	2200      	movs	r2, #0
- 8006db6:	601a      	str	r2, [r3, #0]
- 8006db8:	e000      	b.n	8006dbc <pbuf_realloc+0xf4>
-    return;
- 8006dba:	bf00      	nop
-
-}
- 8006dbc:	3710      	adds	r7, #16
- 8006dbe:	46bd      	mov	sp, r7
- 8006dc0:	bd80      	pop	{r7, pc}
- 8006dc2:	bf00      	nop
- 8006dc4:	08012508 	.word	0x08012508
- 8006dc8:	08012620 	.word	0x08012620
- 8006dcc:	08012568 	.word	0x08012568
- 8006dd0:	08012638 	.word	0x08012638
- 8006dd4:	08012650 	.word	0x08012650
-
-08006dd8 <pbuf_add_header_impl>:
- * @return non-zero on failure, zero on success.
- *
- */
-static u8_t
-pbuf_add_header_impl(struct pbuf *p, size_t header_size_increment, u8_t force)
-{
- 8006dd8:	b580      	push	{r7, lr}
- 8006dda:	b086      	sub	sp, #24
- 8006ddc:	af00      	add	r7, sp, #0
- 8006dde:	60f8      	str	r0, [r7, #12]
- 8006de0:	60b9      	str	r1, [r7, #8]
- 8006de2:	4613      	mov	r3, r2
- 8006de4:	71fb      	strb	r3, [r7, #7]
-  u16_t type_internal;
-  void *payload;
-  u16_t increment_magnitude;
-
-  LWIP_ASSERT("p != NULL", p != NULL);
- 8006de6:	68fb      	ldr	r3, [r7, #12]
- 8006de8:	2b00      	cmp	r3, #0
- 8006dea:	d106      	bne.n	8006dfa <pbuf_add_header_impl+0x22>
- 8006dec:	4b2b      	ldr	r3, [pc, #172]	; (8006e9c <pbuf_add_header_impl+0xc4>)
- 8006dee:	f240 12df 	movw	r2, #479	; 0x1df
- 8006df2:	492b      	ldr	r1, [pc, #172]	; (8006ea0 <pbuf_add_header_impl+0xc8>)
- 8006df4:	482b      	ldr	r0, [pc, #172]	; (8006ea4 <pbuf_add_header_impl+0xcc>)
- 8006df6:	f009 fee7 	bl	8010bc8 <iprintf>
-  if ((p == NULL) || (header_size_increment > 0xFFFF)) {
- 8006dfa:	68fb      	ldr	r3, [r7, #12]
- 8006dfc:	2b00      	cmp	r3, #0
- 8006dfe:	d003      	beq.n	8006e08 <pbuf_add_header_impl+0x30>
- 8006e00:	68bb      	ldr	r3, [r7, #8]
- 8006e02:	f5b3 3f80 	cmp.w	r3, #65536	; 0x10000
- 8006e06:	d301      	bcc.n	8006e0c <pbuf_add_header_impl+0x34>
-    return 1;
- 8006e08:	2301      	movs	r3, #1
- 8006e0a:	e043      	b.n	8006e94 <pbuf_add_header_impl+0xbc>
-  }
-  if (header_size_increment == 0) {
- 8006e0c:	68bb      	ldr	r3, [r7, #8]
- 8006e0e:	2b00      	cmp	r3, #0
- 8006e10:	d101      	bne.n	8006e16 <pbuf_add_header_impl+0x3e>
-    return 0;
- 8006e12:	2300      	movs	r3, #0
- 8006e14:	e03e      	b.n	8006e94 <pbuf_add_header_impl+0xbc>
-  }
-
-  increment_magnitude = (u16_t)header_size_increment;
- 8006e16:	68bb      	ldr	r3, [r7, #8]
- 8006e18:	827b      	strh	r3, [r7, #18]
-  /* Do not allow tot_len to wrap as a result. */
-  if ((u16_t)(increment_magnitude + p->tot_len) < increment_magnitude) {
- 8006e1a:	68fb      	ldr	r3, [r7, #12]
- 8006e1c:	891a      	ldrh	r2, [r3, #8]
- 8006e1e:	8a7b      	ldrh	r3, [r7, #18]
- 8006e20:	4413      	add	r3, r2
- 8006e22:	b29b      	uxth	r3, r3
- 8006e24:	8a7a      	ldrh	r2, [r7, #18]
- 8006e26:	429a      	cmp	r2, r3
- 8006e28:	d901      	bls.n	8006e2e <pbuf_add_header_impl+0x56>
-    return 1;
- 8006e2a:	2301      	movs	r3, #1
- 8006e2c:	e032      	b.n	8006e94 <pbuf_add_header_impl+0xbc>
-  }
-
-  type_internal = p->type_internal;
- 8006e2e:	68fb      	ldr	r3, [r7, #12]
- 8006e30:	7b1b      	ldrb	r3, [r3, #12]
- 8006e32:	823b      	strh	r3, [r7, #16]
-
-  /* pbuf types containing payloads? */
-  if (type_internal & PBUF_TYPE_FLAG_STRUCT_DATA_CONTIGUOUS) {
- 8006e34:	8a3b      	ldrh	r3, [r7, #16]
- 8006e36:	f003 0380 	and.w	r3, r3, #128	; 0x80
- 8006e3a:	2b00      	cmp	r3, #0
- 8006e3c:	d00c      	beq.n	8006e58 <pbuf_add_header_impl+0x80>
-    /* set new payload pointer */
-    payload = (u8_t *)p->payload - header_size_increment;
- 8006e3e:	68fb      	ldr	r3, [r7, #12]
- 8006e40:	685a      	ldr	r2, [r3, #4]
- 8006e42:	68bb      	ldr	r3, [r7, #8]
- 8006e44:	425b      	negs	r3, r3
- 8006e46:	4413      	add	r3, r2
- 8006e48:	617b      	str	r3, [r7, #20]
-    /* boundary check fails? */
-    if ((u8_t *)payload < (u8_t *)p + SIZEOF_STRUCT_PBUF) {
- 8006e4a:	68fb      	ldr	r3, [r7, #12]
- 8006e4c:	3310      	adds	r3, #16
- 8006e4e:	697a      	ldr	r2, [r7, #20]
- 8006e50:	429a      	cmp	r2, r3
- 8006e52:	d20d      	bcs.n	8006e70 <pbuf_add_header_impl+0x98>
-      LWIP_DEBUGF( PBUF_DEBUG | LWIP_DBG_TRACE,
-                   ("pbuf_add_header: failed as %p < %p (not enough space for new header size)\n",
-                    (void *)payload, (void *)((u8_t *)p + SIZEOF_STRUCT_PBUF)));
-      /* bail out unsuccessfully */
-      return 1;
- 8006e54:	2301      	movs	r3, #1
- 8006e56:	e01d      	b.n	8006e94 <pbuf_add_header_impl+0xbc>
-    }
-    /* pbuf types referring to external payloads? */
-  } else {
-    /* hide a header in the payload? */
-    if (force) {
- 8006e58:	79fb      	ldrb	r3, [r7, #7]
- 8006e5a:	2b00      	cmp	r3, #0
- 8006e5c:	d006      	beq.n	8006e6c <pbuf_add_header_impl+0x94>
-      payload = (u8_t *)p->payload - header_size_increment;
- 8006e5e:	68fb      	ldr	r3, [r7, #12]
- 8006e60:	685a      	ldr	r2, [r3, #4]
- 8006e62:	68bb      	ldr	r3, [r7, #8]
- 8006e64:	425b      	negs	r3, r3
- 8006e66:	4413      	add	r3, r2
- 8006e68:	617b      	str	r3, [r7, #20]
- 8006e6a:	e001      	b.n	8006e70 <pbuf_add_header_impl+0x98>
-    } else {
-      /* cannot expand payload to front (yet!)
-       * bail out unsuccessfully */
-      return 1;
- 8006e6c:	2301      	movs	r3, #1
- 8006e6e:	e011      	b.n	8006e94 <pbuf_add_header_impl+0xbc>
-  }
-  LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_add_header: old %p new %p (%"U16_F")\n",
-              (void *)p->payload, (void *)payload, increment_magnitude));
-
-  /* modify pbuf fields */
-  p->payload = payload;
- 8006e70:	68fb      	ldr	r3, [r7, #12]
- 8006e72:	697a      	ldr	r2, [r7, #20]
- 8006e74:	605a      	str	r2, [r3, #4]
-  p->len = (u16_t)(p->len + increment_magnitude);
- 8006e76:	68fb      	ldr	r3, [r7, #12]
- 8006e78:	895a      	ldrh	r2, [r3, #10]
- 8006e7a:	8a7b      	ldrh	r3, [r7, #18]
- 8006e7c:	4413      	add	r3, r2
- 8006e7e:	b29a      	uxth	r2, r3
- 8006e80:	68fb      	ldr	r3, [r7, #12]
- 8006e82:	815a      	strh	r2, [r3, #10]
-  p->tot_len = (u16_t)(p->tot_len + increment_magnitude);
- 8006e84:	68fb      	ldr	r3, [r7, #12]
- 8006e86:	891a      	ldrh	r2, [r3, #8]
- 8006e88:	8a7b      	ldrh	r3, [r7, #18]
- 8006e8a:	4413      	add	r3, r2
- 8006e8c:	b29a      	uxth	r2, r3
- 8006e8e:	68fb      	ldr	r3, [r7, #12]
- 8006e90:	811a      	strh	r2, [r3, #8]
-
-
-  return 0;
- 8006e92:	2300      	movs	r3, #0
-}
- 8006e94:	4618      	mov	r0, r3
- 8006e96:	3718      	adds	r7, #24
- 8006e98:	46bd      	mov	sp, r7
- 8006e9a:	bd80      	pop	{r7, pc}
- 8006e9c:	08012508 	.word	0x08012508
- 8006ea0:	0801266c 	.word	0x0801266c
- 8006ea4:	08012568 	.word	0x08012568
-
-08006ea8 <pbuf_add_header>:
- * @return non-zero on failure, zero on success.
- *
- */
-u8_t
-pbuf_add_header(struct pbuf *p, size_t header_size_increment)
-{
- 8006ea8:	b580      	push	{r7, lr}
- 8006eaa:	b082      	sub	sp, #8
- 8006eac:	af00      	add	r7, sp, #0
- 8006eae:	6078      	str	r0, [r7, #4]
- 8006eb0:	6039      	str	r1, [r7, #0]
-  return pbuf_add_header_impl(p, header_size_increment, 0);
- 8006eb2:	2200      	movs	r2, #0
- 8006eb4:	6839      	ldr	r1, [r7, #0]
- 8006eb6:	6878      	ldr	r0, [r7, #4]
- 8006eb8:	f7ff ff8e 	bl	8006dd8 <pbuf_add_header_impl>
- 8006ebc:	4603      	mov	r3, r0
-}
- 8006ebe:	4618      	mov	r0, r3
- 8006ec0:	3708      	adds	r7, #8
- 8006ec2:	46bd      	mov	sp, r7
- 8006ec4:	bd80      	pop	{r7, pc}
-	...
-
-08006ec8 <pbuf_remove_header>:
- * @return non-zero on failure, zero on success.
- *
- */
-u8_t
-pbuf_remove_header(struct pbuf *p, size_t header_size_decrement)
-{
- 8006ec8:	b580      	push	{r7, lr}
- 8006eca:	b084      	sub	sp, #16
- 8006ecc:	af00      	add	r7, sp, #0
- 8006ece:	6078      	str	r0, [r7, #4]
- 8006ed0:	6039      	str	r1, [r7, #0]
-  void *payload;
-  u16_t increment_magnitude;
-
-  LWIP_ASSERT("p != NULL", p != NULL);
- 8006ed2:	687b      	ldr	r3, [r7, #4]
- 8006ed4:	2b00      	cmp	r3, #0
- 8006ed6:	d106      	bne.n	8006ee6 <pbuf_remove_header+0x1e>
- 8006ed8:	4b20      	ldr	r3, [pc, #128]	; (8006f5c <pbuf_remove_header+0x94>)
- 8006eda:	f240 224b 	movw	r2, #587	; 0x24b
- 8006ede:	4920      	ldr	r1, [pc, #128]	; (8006f60 <pbuf_remove_header+0x98>)
- 8006ee0:	4820      	ldr	r0, [pc, #128]	; (8006f64 <pbuf_remove_header+0x9c>)
- 8006ee2:	f009 fe71 	bl	8010bc8 <iprintf>
-  if ((p == NULL) || (header_size_decrement > 0xFFFF)) {
- 8006ee6:	687b      	ldr	r3, [r7, #4]
- 8006ee8:	2b00      	cmp	r3, #0
- 8006eea:	d003      	beq.n	8006ef4 <pbuf_remove_header+0x2c>
- 8006eec:	683b      	ldr	r3, [r7, #0]
- 8006eee:	f5b3 3f80 	cmp.w	r3, #65536	; 0x10000
- 8006ef2:	d301      	bcc.n	8006ef8 <pbuf_remove_header+0x30>
-    return 1;
- 8006ef4:	2301      	movs	r3, #1
- 8006ef6:	e02c      	b.n	8006f52 <pbuf_remove_header+0x8a>
-  }
-  if (header_size_decrement == 0) {
- 8006ef8:	683b      	ldr	r3, [r7, #0]
- 8006efa:	2b00      	cmp	r3, #0
- 8006efc:	d101      	bne.n	8006f02 <pbuf_remove_header+0x3a>
-    return 0;
- 8006efe:	2300      	movs	r3, #0
- 8006f00:	e027      	b.n	8006f52 <pbuf_remove_header+0x8a>
-  }
-
-  increment_magnitude = (u16_t)header_size_decrement;
- 8006f02:	683b      	ldr	r3, [r7, #0]
- 8006f04:	81fb      	strh	r3, [r7, #14]
-  /* Check that we aren't going to move off the end of the pbuf */
-  LWIP_ERROR("increment_magnitude <= p->len", (increment_magnitude <= p->len), return 1;);
- 8006f06:	687b      	ldr	r3, [r7, #4]
- 8006f08:	895b      	ldrh	r3, [r3, #10]
- 8006f0a:	89fa      	ldrh	r2, [r7, #14]
- 8006f0c:	429a      	cmp	r2, r3
- 8006f0e:	d908      	bls.n	8006f22 <pbuf_remove_header+0x5a>
- 8006f10:	4b12      	ldr	r3, [pc, #72]	; (8006f5c <pbuf_remove_header+0x94>)
- 8006f12:	f240 2255 	movw	r2, #597	; 0x255
- 8006f16:	4914      	ldr	r1, [pc, #80]	; (8006f68 <pbuf_remove_header+0xa0>)
- 8006f18:	4812      	ldr	r0, [pc, #72]	; (8006f64 <pbuf_remove_header+0x9c>)
- 8006f1a:	f009 fe55 	bl	8010bc8 <iprintf>
- 8006f1e:	2301      	movs	r3, #1
- 8006f20:	e017      	b.n	8006f52 <pbuf_remove_header+0x8a>
-
-  /* remember current payload pointer */
-  payload = p->payload;
- 8006f22:	687b      	ldr	r3, [r7, #4]
- 8006f24:	685b      	ldr	r3, [r3, #4]
- 8006f26:	60bb      	str	r3, [r7, #8]
-  LWIP_UNUSED_ARG(payload); /* only used in LWIP_DEBUGF below */
-
-  /* increase payload pointer (guarded by length check above) */
-  p->payload = (u8_t *)p->payload + header_size_decrement;
- 8006f28:	687b      	ldr	r3, [r7, #4]
- 8006f2a:	685a      	ldr	r2, [r3, #4]
- 8006f2c:	683b      	ldr	r3, [r7, #0]
- 8006f2e:	441a      	add	r2, r3
- 8006f30:	687b      	ldr	r3, [r7, #4]
- 8006f32:	605a      	str	r2, [r3, #4]
-  /* modify pbuf length fields */
-  p->len = (u16_t)(p->len - increment_magnitude);
- 8006f34:	687b      	ldr	r3, [r7, #4]
- 8006f36:	895a      	ldrh	r2, [r3, #10]
- 8006f38:	89fb      	ldrh	r3, [r7, #14]
- 8006f3a:	1ad3      	subs	r3, r2, r3
- 8006f3c:	b29a      	uxth	r2, r3
- 8006f3e:	687b      	ldr	r3, [r7, #4]
- 8006f40:	815a      	strh	r2, [r3, #10]
-  p->tot_len = (u16_t)(p->tot_len - increment_magnitude);
- 8006f42:	687b      	ldr	r3, [r7, #4]
- 8006f44:	891a      	ldrh	r2, [r3, #8]
- 8006f46:	89fb      	ldrh	r3, [r7, #14]
- 8006f48:	1ad3      	subs	r3, r2, r3
- 8006f4a:	b29a      	uxth	r2, r3
- 8006f4c:	687b      	ldr	r3, [r7, #4]
- 8006f4e:	811a      	strh	r2, [r3, #8]
-
-  LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_remove_header: old %p new %p (%"U16_F")\n",
-              (void *)payload, (void *)p->payload, increment_magnitude));
-
-  return 0;
- 8006f50:	2300      	movs	r3, #0
-}
- 8006f52:	4618      	mov	r0, r3
- 8006f54:	3710      	adds	r7, #16
- 8006f56:	46bd      	mov	sp, r7
- 8006f58:	bd80      	pop	{r7, pc}
- 8006f5a:	bf00      	nop
- 8006f5c:	08012508 	.word	0x08012508
- 8006f60:	0801266c 	.word	0x0801266c
- 8006f64:	08012568 	.word	0x08012568
- 8006f68:	08012678 	.word	0x08012678
-
-08006f6c <pbuf_header_impl>:
-
-static u8_t
-pbuf_header_impl(struct pbuf *p, s16_t header_size_increment, u8_t force)
-{
- 8006f6c:	b580      	push	{r7, lr}
- 8006f6e:	b082      	sub	sp, #8
- 8006f70:	af00      	add	r7, sp, #0
- 8006f72:	6078      	str	r0, [r7, #4]
- 8006f74:	460b      	mov	r3, r1
- 8006f76:	807b      	strh	r3, [r7, #2]
- 8006f78:	4613      	mov	r3, r2
- 8006f7a:	707b      	strb	r3, [r7, #1]
-  if (header_size_increment < 0) {
- 8006f7c:	f9b7 3002 	ldrsh.w	r3, [r7, #2]
- 8006f80:	2b00      	cmp	r3, #0
- 8006f82:	da08      	bge.n	8006f96 <pbuf_header_impl+0x2a>
-    return pbuf_remove_header(p, (size_t) - header_size_increment);
- 8006f84:	f9b7 3002 	ldrsh.w	r3, [r7, #2]
- 8006f88:	425b      	negs	r3, r3
- 8006f8a:	4619      	mov	r1, r3
- 8006f8c:	6878      	ldr	r0, [r7, #4]
- 8006f8e:	f7ff ff9b 	bl	8006ec8 <pbuf_remove_header>
- 8006f92:	4603      	mov	r3, r0
- 8006f94:	e007      	b.n	8006fa6 <pbuf_header_impl+0x3a>
-  } else {
-    return pbuf_add_header_impl(p, (size_t)header_size_increment, force);
- 8006f96:	f9b7 3002 	ldrsh.w	r3, [r7, #2]
- 8006f9a:	787a      	ldrb	r2, [r7, #1]
- 8006f9c:	4619      	mov	r1, r3
- 8006f9e:	6878      	ldr	r0, [r7, #4]
- 8006fa0:	f7ff ff1a 	bl	8006dd8 <pbuf_add_header_impl>
- 8006fa4:	4603      	mov	r3, r0
-  }
-}
- 8006fa6:	4618      	mov	r0, r3
- 8006fa8:	3708      	adds	r7, #8
- 8006faa:	46bd      	mov	sp, r7
- 8006fac:	bd80      	pop	{r7, pc}
-
-08006fae <pbuf_header_force>:
- * Same as pbuf_header but does not check if 'header_size > 0' is allowed.
- * This is used internally only, to allow PBUF_REF for RX.
- */
-u8_t
-pbuf_header_force(struct pbuf *p, s16_t header_size_increment)
-{
- 8006fae:	b580      	push	{r7, lr}
- 8006fb0:	b082      	sub	sp, #8
- 8006fb2:	af00      	add	r7, sp, #0
- 8006fb4:	6078      	str	r0, [r7, #4]
- 8006fb6:	460b      	mov	r3, r1
- 8006fb8:	807b      	strh	r3, [r7, #2]
-  return pbuf_header_impl(p, header_size_increment, 1);
- 8006fba:	f9b7 3002 	ldrsh.w	r3, [r7, #2]
- 8006fbe:	2201      	movs	r2, #1
- 8006fc0:	4619      	mov	r1, r3
- 8006fc2:	6878      	ldr	r0, [r7, #4]
- 8006fc4:	f7ff ffd2 	bl	8006f6c <pbuf_header_impl>
- 8006fc8:	4603      	mov	r3, r0
-}
- 8006fca:	4618      	mov	r0, r3
- 8006fcc:	3708      	adds	r7, #8
- 8006fce:	46bd      	mov	sp, r7
- 8006fd0:	bd80      	pop	{r7, pc}
-	...
-
-08006fd4 <pbuf_free>:
- * 1->1->1 becomes .......
- *
- */
-u8_t
-pbuf_free(struct pbuf *p)
-{
- 8006fd4:	b580      	push	{r7, lr}
- 8006fd6:	b086      	sub	sp, #24
- 8006fd8:	af00      	add	r7, sp, #0
- 8006fda:	6078      	str	r0, [r7, #4]
-  u8_t alloc_src;
-  struct pbuf *q;
-  u8_t count;
-
-  if (p == NULL) {
- 8006fdc:	687b      	ldr	r3, [r7, #4]
- 8006fde:	2b00      	cmp	r3, #0
- 8006fe0:	d10b      	bne.n	8006ffa <pbuf_free+0x26>
-    LWIP_ASSERT("p != NULL", p != NULL);
- 8006fe2:	687b      	ldr	r3, [r7, #4]
- 8006fe4:	2b00      	cmp	r3, #0
- 8006fe6:	d106      	bne.n	8006ff6 <pbuf_free+0x22>
- 8006fe8:	4b38      	ldr	r3, [pc, #224]	; (80070cc <pbuf_free+0xf8>)
- 8006fea:	f44f 7237 	mov.w	r2, #732	; 0x2dc
- 8006fee:	4938      	ldr	r1, [pc, #224]	; (80070d0 <pbuf_free+0xfc>)
- 8006ff0:	4838      	ldr	r0, [pc, #224]	; (80070d4 <pbuf_free+0x100>)
- 8006ff2:	f009 fde9 	bl	8010bc8 <iprintf>
-    /* if assertions are disabled, proceed with debug output */
-    LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_LEVEL_SERIOUS,
-                ("pbuf_free(p == NULL) was called.\n"));
-    return 0;
- 8006ff6:	2300      	movs	r3, #0
- 8006ff8:	e063      	b.n	80070c2 <pbuf_free+0xee>
-  }
-  LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_free(%p)\n", (void *)p));
-
-  PERF_START;
-
-  count = 0;
- 8006ffa:	2300      	movs	r3, #0
- 8006ffc:	75fb      	strb	r3, [r7, #23]
-  /* de-allocate all consecutive pbufs from the head of the chain that
-   * obtain a zero reference count after decrementing*/
-  while (p != NULL) {
- 8006ffe:	e05c      	b.n	80070ba <pbuf_free+0xe6>
-    /* Since decrementing ref cannot be guaranteed to be a single machine operation
-     * we must protect it. We put the new ref into a local variable to prevent
-     * further protection. */
-    SYS_ARCH_PROTECT(old_level);
-    /* all pbufs in a chain are referenced at least once */
-    LWIP_ASSERT("pbuf_free: p->ref > 0", p->ref > 0);
- 8007000:	687b      	ldr	r3, [r7, #4]
- 8007002:	7b9b      	ldrb	r3, [r3, #14]
- 8007004:	2b00      	cmp	r3, #0
- 8007006:	d106      	bne.n	8007016 <pbuf_free+0x42>
- 8007008:	4b30      	ldr	r3, [pc, #192]	; (80070cc <pbuf_free+0xf8>)
- 800700a:	f240 22f1 	movw	r2, #753	; 0x2f1
- 800700e:	4932      	ldr	r1, [pc, #200]	; (80070d8 <pbuf_free+0x104>)
- 8007010:	4830      	ldr	r0, [pc, #192]	; (80070d4 <pbuf_free+0x100>)
- 8007012:	f009 fdd9 	bl	8010bc8 <iprintf>
-    /* decrease reference count (number of pointers to pbuf) */
-    ref = --(p->ref);
- 8007016:	687b      	ldr	r3, [r7, #4]
- 8007018:	7b9b      	ldrb	r3, [r3, #14]
- 800701a:	3b01      	subs	r3, #1
- 800701c:	b2da      	uxtb	r2, r3
- 800701e:	687b      	ldr	r3, [r7, #4]
- 8007020:	739a      	strb	r2, [r3, #14]
- 8007022:	687b      	ldr	r3, [r7, #4]
- 8007024:	7b9b      	ldrb	r3, [r3, #14]
- 8007026:	75bb      	strb	r3, [r7, #22]
-    SYS_ARCH_UNPROTECT(old_level);
-    /* this pbuf is no longer referenced to? */
-    if (ref == 0) {
- 8007028:	7dbb      	ldrb	r3, [r7, #22]
- 800702a:	2b00      	cmp	r3, #0
- 800702c:	d143      	bne.n	80070b6 <pbuf_free+0xe2>
-      /* remember next pbuf in chain for next iteration */
-      q = p->next;
- 800702e:	687b      	ldr	r3, [r7, #4]
- 8007030:	681b      	ldr	r3, [r3, #0]
- 8007032:	613b      	str	r3, [r7, #16]
-      LWIP_DEBUGF( PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_free: deallocating %p\n", (void *)p));
-      alloc_src = pbuf_get_allocsrc(p);
- 8007034:	687b      	ldr	r3, [r7, #4]
- 8007036:	7b1b      	ldrb	r3, [r3, #12]
- 8007038:	f003 030f 	and.w	r3, r3, #15
- 800703c:	73fb      	strb	r3, [r7, #15]
-#if LWIP_SUPPORT_CUSTOM_PBUF
-      /* is this a custom pbuf? */
-      if ((p->flags & PBUF_FLAG_IS_CUSTOM) != 0) {
- 800703e:	687b      	ldr	r3, [r7, #4]
- 8007040:	7b5b      	ldrb	r3, [r3, #13]
- 8007042:	f003 0302 	and.w	r3, r3, #2
- 8007046:	2b00      	cmp	r3, #0
- 8007048:	d011      	beq.n	800706e <pbuf_free+0x9a>
-        struct pbuf_custom *pc = (struct pbuf_custom *)p;
- 800704a:	687b      	ldr	r3, [r7, #4]
- 800704c:	60bb      	str	r3, [r7, #8]
-        LWIP_ASSERT("pc->custom_free_function != NULL", pc->custom_free_function != NULL);
- 800704e:	68bb      	ldr	r3, [r7, #8]
- 8007050:	691b      	ldr	r3, [r3, #16]
- 8007052:	2b00      	cmp	r3, #0
- 8007054:	d106      	bne.n	8007064 <pbuf_free+0x90>
- 8007056:	4b1d      	ldr	r3, [pc, #116]	; (80070cc <pbuf_free+0xf8>)
- 8007058:	f240 22ff 	movw	r2, #767	; 0x2ff
- 800705c:	491f      	ldr	r1, [pc, #124]	; (80070dc <pbuf_free+0x108>)
- 800705e:	481d      	ldr	r0, [pc, #116]	; (80070d4 <pbuf_free+0x100>)
- 8007060:	f009 fdb2 	bl	8010bc8 <iprintf>
-        pc->custom_free_function(p);
- 8007064:	68bb      	ldr	r3, [r7, #8]
- 8007066:	691b      	ldr	r3, [r3, #16]
- 8007068:	6878      	ldr	r0, [r7, #4]
- 800706a:	4798      	blx	r3
- 800706c:	e01d      	b.n	80070aa <pbuf_free+0xd6>
-      } else
-#endif /* LWIP_SUPPORT_CUSTOM_PBUF */
-      {
-        /* is this a pbuf from the pool? */
-        if (alloc_src == PBUF_TYPE_ALLOC_SRC_MASK_STD_MEMP_PBUF_POOL) {
- 800706e:	7bfb      	ldrb	r3, [r7, #15]
- 8007070:	2b02      	cmp	r3, #2
- 8007072:	d104      	bne.n	800707e <pbuf_free+0xaa>
-          memp_free(MEMP_PBUF_POOL, p);
- 8007074:	6879      	ldr	r1, [r7, #4]
- 8007076:	2008      	movs	r0, #8
- 8007078:	f7ff f840 	bl	80060fc <memp_free>
- 800707c:	e015      	b.n	80070aa <pbuf_free+0xd6>
-          /* is this a ROM or RAM referencing pbuf? */
-        } else if (alloc_src == PBUF_TYPE_ALLOC_SRC_MASK_STD_MEMP_PBUF) {
- 800707e:	7bfb      	ldrb	r3, [r7, #15]
- 8007080:	2b01      	cmp	r3, #1
- 8007082:	d104      	bne.n	800708e <pbuf_free+0xba>
-          memp_free(MEMP_PBUF, p);
- 8007084:	6879      	ldr	r1, [r7, #4]
- 8007086:	2007      	movs	r0, #7
- 8007088:	f7ff f838 	bl	80060fc <memp_free>
- 800708c:	e00d      	b.n	80070aa <pbuf_free+0xd6>
-          /* type == PBUF_RAM */
-        } else if (alloc_src == PBUF_TYPE_ALLOC_SRC_MASK_STD_HEAP) {
- 800708e:	7bfb      	ldrb	r3, [r7, #15]
- 8007090:	2b00      	cmp	r3, #0
- 8007092:	d103      	bne.n	800709c <pbuf_free+0xc8>
-          mem_free(p);
- 8007094:	6878      	ldr	r0, [r7, #4]
- 8007096:	f7fe fc99 	bl	80059cc <mem_free>
- 800709a:	e006      	b.n	80070aa <pbuf_free+0xd6>
-        } else {
-          /* @todo: support freeing other types */
-          LWIP_ASSERT("invalid pbuf type", 0);
- 800709c:	4b0b      	ldr	r3, [pc, #44]	; (80070cc <pbuf_free+0xf8>)
- 800709e:	f240 320f 	movw	r2, #783	; 0x30f
- 80070a2:	490f      	ldr	r1, [pc, #60]	; (80070e0 <pbuf_free+0x10c>)
- 80070a4:	480b      	ldr	r0, [pc, #44]	; (80070d4 <pbuf_free+0x100>)
- 80070a6:	f009 fd8f 	bl	8010bc8 <iprintf>
-        }
-      }
-      count++;
- 80070aa:	7dfb      	ldrb	r3, [r7, #23]
- 80070ac:	3301      	adds	r3, #1
- 80070ae:	75fb      	strb	r3, [r7, #23]
-      /* proceed to next pbuf */
-      p = q;
- 80070b0:	693b      	ldr	r3, [r7, #16]
- 80070b2:	607b      	str	r3, [r7, #4]
- 80070b4:	e001      	b.n	80070ba <pbuf_free+0xe6>
-      /* p->ref > 0, this pbuf is still referenced to */
-      /* (and so the remaining pbufs in chain as well) */
-    } else {
-      LWIP_DEBUGF( PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_free: %p has ref %"U16_F", ending here.\n", (void *)p, (u16_t)ref));
-      /* stop walking through the chain */
-      p = NULL;
- 80070b6:	2300      	movs	r3, #0
- 80070b8:	607b      	str	r3, [r7, #4]
-  while (p != NULL) {
- 80070ba:	687b      	ldr	r3, [r7, #4]
- 80070bc:	2b00      	cmp	r3, #0
- 80070be:	d19f      	bne.n	8007000 <pbuf_free+0x2c>
-    }
-  }
-  PERF_STOP("pbuf_free");
-  /* return number of de-allocated pbufs */
-  return count;
- 80070c0:	7dfb      	ldrb	r3, [r7, #23]
-}
- 80070c2:	4618      	mov	r0, r3
- 80070c4:	3718      	adds	r7, #24
- 80070c6:	46bd      	mov	sp, r7
- 80070c8:	bd80      	pop	{r7, pc}
- 80070ca:	bf00      	nop
- 80070cc:	08012508 	.word	0x08012508
- 80070d0:	0801266c 	.word	0x0801266c
- 80070d4:	08012568 	.word	0x08012568
- 80070d8:	08012698 	.word	0x08012698
- 80070dc:	080126b0 	.word	0x080126b0
- 80070e0:	080126d4 	.word	0x080126d4
-
-080070e4 <pbuf_clen>:
- * @param p first pbuf of chain
- * @return the number of pbufs in a chain
- */
-u16_t
-pbuf_clen(const struct pbuf *p)
-{
- 80070e4:	b480      	push	{r7}
- 80070e6:	b085      	sub	sp, #20
- 80070e8:	af00      	add	r7, sp, #0
- 80070ea:	6078      	str	r0, [r7, #4]
-  u16_t len;
-
-  len = 0;
- 80070ec:	2300      	movs	r3, #0
- 80070ee:	81fb      	strh	r3, [r7, #14]
-  while (p != NULL) {
- 80070f0:	e005      	b.n	80070fe <pbuf_clen+0x1a>
-    ++len;
- 80070f2:	89fb      	ldrh	r3, [r7, #14]
- 80070f4:	3301      	adds	r3, #1
- 80070f6:	81fb      	strh	r3, [r7, #14]
-    p = p->next;
- 80070f8:	687b      	ldr	r3, [r7, #4]
- 80070fa:	681b      	ldr	r3, [r3, #0]
- 80070fc:	607b      	str	r3, [r7, #4]
-  while (p != NULL) {
- 80070fe:	687b      	ldr	r3, [r7, #4]
- 8007100:	2b00      	cmp	r3, #0
- 8007102:	d1f6      	bne.n	80070f2 <pbuf_clen+0xe>
-  }
-  return len;
- 8007104:	89fb      	ldrh	r3, [r7, #14]
-}
- 8007106:	4618      	mov	r0, r3
- 8007108:	3714      	adds	r7, #20
- 800710a:	46bd      	mov	sp, r7
- 800710c:	f85d 7b04 	ldr.w	r7, [sp], #4
- 8007110:	4770      	bx	lr
-	...
-
-08007114 <pbuf_ref>:
- * @param p pbuf to increase reference counter of
- *
- */
-void
-pbuf_ref(struct pbuf *p)
-{
- 8007114:	b580      	push	{r7, lr}
- 8007116:	b082      	sub	sp, #8
- 8007118:	af00      	add	r7, sp, #0
- 800711a:	6078      	str	r0, [r7, #4]
-  /* pbuf given? */
-  if (p != NULL) {
- 800711c:	687b      	ldr	r3, [r7, #4]
- 800711e:	2b00      	cmp	r3, #0
- 8007120:	d010      	beq.n	8007144 <pbuf_ref+0x30>
-    SYS_ARCH_SET(p->ref, (LWIP_PBUF_REF_T)(p->ref + 1));
- 8007122:	687b      	ldr	r3, [r7, #4]
- 8007124:	7b9b      	ldrb	r3, [r3, #14]
- 8007126:	3301      	adds	r3, #1
- 8007128:	b2da      	uxtb	r2, r3
- 800712a:	687b      	ldr	r3, [r7, #4]
- 800712c:	739a      	strb	r2, [r3, #14]
-    LWIP_ASSERT("pbuf ref overflow", p->ref > 0);
- 800712e:	687b      	ldr	r3, [r7, #4]
- 8007130:	7b9b      	ldrb	r3, [r3, #14]
- 8007132:	2b00      	cmp	r3, #0
- 8007134:	d106      	bne.n	8007144 <pbuf_ref+0x30>
- 8007136:	4b05      	ldr	r3, [pc, #20]	; (800714c <pbuf_ref+0x38>)
- 8007138:	f240 3242 	movw	r2, #834	; 0x342
- 800713c:	4904      	ldr	r1, [pc, #16]	; (8007150 <pbuf_ref+0x3c>)
- 800713e:	4805      	ldr	r0, [pc, #20]	; (8007154 <pbuf_ref+0x40>)
- 8007140:	f009 fd42 	bl	8010bc8 <iprintf>
-  }
-}
- 8007144:	bf00      	nop
- 8007146:	3708      	adds	r7, #8
- 8007148:	46bd      	mov	sp, r7
- 800714a:	bd80      	pop	{r7, pc}
- 800714c:	08012508 	.word	0x08012508
- 8007150:	080126e8 	.word	0x080126e8
- 8007154:	08012568 	.word	0x08012568
-
-08007158 <pbuf_cat>:
- *
- * @see pbuf_chain()
- */
-void
-pbuf_cat(struct pbuf *h, struct pbuf *t)
-{
- 8007158:	b580      	push	{r7, lr}
- 800715a:	b084      	sub	sp, #16
- 800715c:	af00      	add	r7, sp, #0
- 800715e:	6078      	str	r0, [r7, #4]
- 8007160:	6039      	str	r1, [r7, #0]
-  struct pbuf *p;
-
-  LWIP_ERROR("(h != NULL) && (t != NULL) (programmer violates API)",
- 8007162:	687b      	ldr	r3, [r7, #4]
- 8007164:	2b00      	cmp	r3, #0
- 8007166:	d002      	beq.n	800716e <pbuf_cat+0x16>
- 8007168:	683b      	ldr	r3, [r7, #0]
- 800716a:	2b00      	cmp	r3, #0
- 800716c:	d107      	bne.n	800717e <pbuf_cat+0x26>
- 800716e:	4b20      	ldr	r3, [pc, #128]	; (80071f0 <pbuf_cat+0x98>)
- 8007170:	f240 3259 	movw	r2, #857	; 0x359
- 8007174:	491f      	ldr	r1, [pc, #124]	; (80071f4 <pbuf_cat+0x9c>)
- 8007176:	4820      	ldr	r0, [pc, #128]	; (80071f8 <pbuf_cat+0xa0>)
- 8007178:	f009 fd26 	bl	8010bc8 <iprintf>
- 800717c:	e034      	b.n	80071e8 <pbuf_cat+0x90>
-             ((h != NULL) && (t != NULL)), return;);
-
-  /* proceed to last pbuf of chain */
-  for (p = h; p->next != NULL; p = p->next) {
- 800717e:	687b      	ldr	r3, [r7, #4]
- 8007180:	60fb      	str	r3, [r7, #12]
- 8007182:	e00a      	b.n	800719a <pbuf_cat+0x42>
-    /* add total length of second chain to all totals of first chain */
-    p->tot_len = (u16_t)(p->tot_len + t->tot_len);
- 8007184:	68fb      	ldr	r3, [r7, #12]
- 8007186:	891a      	ldrh	r2, [r3, #8]
- 8007188:	683b      	ldr	r3, [r7, #0]
- 800718a:	891b      	ldrh	r3, [r3, #8]
- 800718c:	4413      	add	r3, r2
- 800718e:	b29a      	uxth	r2, r3
- 8007190:	68fb      	ldr	r3, [r7, #12]
- 8007192:	811a      	strh	r2, [r3, #8]
-  for (p = h; p->next != NULL; p = p->next) {
- 8007194:	68fb      	ldr	r3, [r7, #12]
- 8007196:	681b      	ldr	r3, [r3, #0]
- 8007198:	60fb      	str	r3, [r7, #12]
- 800719a:	68fb      	ldr	r3, [r7, #12]
- 800719c:	681b      	ldr	r3, [r3, #0]
- 800719e:	2b00      	cmp	r3, #0
- 80071a0:	d1f0      	bne.n	8007184 <pbuf_cat+0x2c>
-  }
-  /* { p is last pbuf of first h chain, p->next == NULL } */
-  LWIP_ASSERT("p->tot_len == p->len (of last pbuf in chain)", p->tot_len == p->len);
- 80071a2:	68fb      	ldr	r3, [r7, #12]
- 80071a4:	891a      	ldrh	r2, [r3, #8]
- 80071a6:	68fb      	ldr	r3, [r7, #12]
- 80071a8:	895b      	ldrh	r3, [r3, #10]
- 80071aa:	429a      	cmp	r2, r3
- 80071ac:	d006      	beq.n	80071bc <pbuf_cat+0x64>
- 80071ae:	4b10      	ldr	r3, [pc, #64]	; (80071f0 <pbuf_cat+0x98>)
- 80071b0:	f240 3262 	movw	r2, #866	; 0x362
- 80071b4:	4911      	ldr	r1, [pc, #68]	; (80071fc <pbuf_cat+0xa4>)
- 80071b6:	4810      	ldr	r0, [pc, #64]	; (80071f8 <pbuf_cat+0xa0>)
- 80071b8:	f009 fd06 	bl	8010bc8 <iprintf>
-  LWIP_ASSERT("p->next == NULL", p->next == NULL);
- 80071bc:	68fb      	ldr	r3, [r7, #12]
- 80071be:	681b      	ldr	r3, [r3, #0]
- 80071c0:	2b00      	cmp	r3, #0
- 80071c2:	d006      	beq.n	80071d2 <pbuf_cat+0x7a>
- 80071c4:	4b0a      	ldr	r3, [pc, #40]	; (80071f0 <pbuf_cat+0x98>)
- 80071c6:	f240 3263 	movw	r2, #867	; 0x363
- 80071ca:	490d      	ldr	r1, [pc, #52]	; (8007200 <pbuf_cat+0xa8>)
- 80071cc:	480a      	ldr	r0, [pc, #40]	; (80071f8 <pbuf_cat+0xa0>)
- 80071ce:	f009 fcfb 	bl	8010bc8 <iprintf>
-  /* add total length of second chain to last pbuf total of first chain */
-  p->tot_len = (u16_t)(p->tot_len + t->tot_len);
- 80071d2:	68fb      	ldr	r3, [r7, #12]
- 80071d4:	891a      	ldrh	r2, [r3, #8]
- 80071d6:	683b      	ldr	r3, [r7, #0]
- 80071d8:	891b      	ldrh	r3, [r3, #8]
- 80071da:	4413      	add	r3, r2
- 80071dc:	b29a      	uxth	r2, r3
- 80071de:	68fb      	ldr	r3, [r7, #12]
- 80071e0:	811a      	strh	r2, [r3, #8]
-  /* chain last pbuf of head (p) with first of tail (t) */
-  p->next = t;
- 80071e2:	68fb      	ldr	r3, [r7, #12]
- 80071e4:	683a      	ldr	r2, [r7, #0]
- 80071e6:	601a      	str	r2, [r3, #0]
-  /* p->next now references t, but the caller will drop its reference to t,
-   * so netto there is no change to the reference count of t.
-   */
-}
- 80071e8:	3710      	adds	r7, #16
- 80071ea:	46bd      	mov	sp, r7
- 80071ec:	bd80      	pop	{r7, pc}
- 80071ee:	bf00      	nop
- 80071f0:	08012508 	.word	0x08012508
- 80071f4:	080126fc 	.word	0x080126fc
- 80071f8:	08012568 	.word	0x08012568
- 80071fc:	08012734 	.word	0x08012734
- 8007200:	08012764 	.word	0x08012764
-
-08007204 <pbuf_copy>:
- *         ERR_ARG if one of the pbufs is NULL or p_to is not big
- *                 enough to hold p_from
- */
-err_t
-pbuf_copy(struct pbuf *p_to, const struct pbuf *p_from)
-{
- 8007204:	b580      	push	{r7, lr}
- 8007206:	b086      	sub	sp, #24
- 8007208:	af00      	add	r7, sp, #0
- 800720a:	6078      	str	r0, [r7, #4]
- 800720c:	6039      	str	r1, [r7, #0]
-  size_t offset_to = 0, offset_from = 0, len;
- 800720e:	2300      	movs	r3, #0
- 8007210:	617b      	str	r3, [r7, #20]
- 8007212:	2300      	movs	r3, #0
- 8007214:	613b      	str	r3, [r7, #16]
-
-  LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_copy(%p, %p)\n",
-              (const void *)p_to, (const void *)p_from));
-
-  /* is the target big enough to hold the source? */
-  LWIP_ERROR("pbuf_copy: target not big enough to hold source", ((p_to != NULL) &&
- 8007216:	687b      	ldr	r3, [r7, #4]
- 8007218:	2b00      	cmp	r3, #0
- 800721a:	d008      	beq.n	800722e <pbuf_copy+0x2a>
- 800721c:	683b      	ldr	r3, [r7, #0]
- 800721e:	2b00      	cmp	r3, #0
- 8007220:	d005      	beq.n	800722e <pbuf_copy+0x2a>
- 8007222:	687b      	ldr	r3, [r7, #4]
- 8007224:	891a      	ldrh	r2, [r3, #8]
- 8007226:	683b      	ldr	r3, [r7, #0]
- 8007228:	891b      	ldrh	r3, [r3, #8]
- 800722a:	429a      	cmp	r2, r3
- 800722c:	d209      	bcs.n	8007242 <pbuf_copy+0x3e>
- 800722e:	4b57      	ldr	r3, [pc, #348]	; (800738c <pbuf_copy+0x188>)
- 8007230:	f240 32c9 	movw	r2, #969	; 0x3c9
- 8007234:	4956      	ldr	r1, [pc, #344]	; (8007390 <pbuf_copy+0x18c>)
- 8007236:	4857      	ldr	r0, [pc, #348]	; (8007394 <pbuf_copy+0x190>)
- 8007238:	f009 fcc6 	bl	8010bc8 <iprintf>
- 800723c:	f06f 030f 	mvn.w	r3, #15
- 8007240:	e09f      	b.n	8007382 <pbuf_copy+0x17e>
-             (p_from != NULL) && (p_to->tot_len >= p_from->tot_len)), return ERR_ARG;);
-
-  /* iterate through pbuf chain */
-  do {
-    /* copy one part of the original chain */
-    if ((p_to->len - offset_to) >= (p_from->len - offset_from)) {
- 8007242:	687b      	ldr	r3, [r7, #4]
- 8007244:	895b      	ldrh	r3, [r3, #10]
- 8007246:	461a      	mov	r2, r3
- 8007248:	697b      	ldr	r3, [r7, #20]
- 800724a:	1ad2      	subs	r2, r2, r3
- 800724c:	683b      	ldr	r3, [r7, #0]
- 800724e:	895b      	ldrh	r3, [r3, #10]
- 8007250:	4619      	mov	r1, r3
- 8007252:	693b      	ldr	r3, [r7, #16]
- 8007254:	1acb      	subs	r3, r1, r3
- 8007256:	429a      	cmp	r2, r3
- 8007258:	d306      	bcc.n	8007268 <pbuf_copy+0x64>
-      /* complete current p_from fits into current p_to */
-      len = p_from->len - offset_from;
- 800725a:	683b      	ldr	r3, [r7, #0]
- 800725c:	895b      	ldrh	r3, [r3, #10]
- 800725e:	461a      	mov	r2, r3
- 8007260:	693b      	ldr	r3, [r7, #16]
- 8007262:	1ad3      	subs	r3, r2, r3
- 8007264:	60fb      	str	r3, [r7, #12]
- 8007266:	e005      	b.n	8007274 <pbuf_copy+0x70>
-    } else {
-      /* current p_from does not fit into current p_to */
-      len = p_to->len - offset_to;
- 8007268:	687b      	ldr	r3, [r7, #4]
- 800726a:	895b      	ldrh	r3, [r3, #10]
- 800726c:	461a      	mov	r2, r3
- 800726e:	697b      	ldr	r3, [r7, #20]
- 8007270:	1ad3      	subs	r3, r2, r3
- 8007272:	60fb      	str	r3, [r7, #12]
-    }
-    MEMCPY((u8_t *)p_to->payload + offset_to, (u8_t *)p_from->payload + offset_from, len);
- 8007274:	687b      	ldr	r3, [r7, #4]
- 8007276:	685a      	ldr	r2, [r3, #4]
- 8007278:	697b      	ldr	r3, [r7, #20]
- 800727a:	18d0      	adds	r0, r2, r3
- 800727c:	683b      	ldr	r3, [r7, #0]
- 800727e:	685a      	ldr	r2, [r3, #4]
- 8007280:	693b      	ldr	r3, [r7, #16]
- 8007282:	4413      	add	r3, r2
- 8007284:	68fa      	ldr	r2, [r7, #12]
- 8007286:	4619      	mov	r1, r3
- 8007288:	f009 fe7f 	bl	8010f8a <memcpy>
-    offset_to += len;
- 800728c:	697a      	ldr	r2, [r7, #20]
- 800728e:	68fb      	ldr	r3, [r7, #12]
- 8007290:	4413      	add	r3, r2
- 8007292:	617b      	str	r3, [r7, #20]
-    offset_from += len;
- 8007294:	693a      	ldr	r2, [r7, #16]
- 8007296:	68fb      	ldr	r3, [r7, #12]
- 8007298:	4413      	add	r3, r2
- 800729a:	613b      	str	r3, [r7, #16]
-    LWIP_ASSERT("offset_to <= p_to->len", offset_to <= p_to->len);
- 800729c:	687b      	ldr	r3, [r7, #4]
- 800729e:	895b      	ldrh	r3, [r3, #10]
- 80072a0:	461a      	mov	r2, r3
- 80072a2:	697b      	ldr	r3, [r7, #20]
- 80072a4:	4293      	cmp	r3, r2
- 80072a6:	d906      	bls.n	80072b6 <pbuf_copy+0xb2>
- 80072a8:	4b38      	ldr	r3, [pc, #224]	; (800738c <pbuf_copy+0x188>)
- 80072aa:	f240 32d9 	movw	r2, #985	; 0x3d9
- 80072ae:	493a      	ldr	r1, [pc, #232]	; (8007398 <pbuf_copy+0x194>)
- 80072b0:	4838      	ldr	r0, [pc, #224]	; (8007394 <pbuf_copy+0x190>)
- 80072b2:	f009 fc89 	bl	8010bc8 <iprintf>
-    LWIP_ASSERT("offset_from <= p_from->len", offset_from <= p_from->len);
- 80072b6:	683b      	ldr	r3, [r7, #0]
- 80072b8:	895b      	ldrh	r3, [r3, #10]
- 80072ba:	461a      	mov	r2, r3
- 80072bc:	693b      	ldr	r3, [r7, #16]
- 80072be:	4293      	cmp	r3, r2
- 80072c0:	d906      	bls.n	80072d0 <pbuf_copy+0xcc>
- 80072c2:	4b32      	ldr	r3, [pc, #200]	; (800738c <pbuf_copy+0x188>)
- 80072c4:	f240 32da 	movw	r2, #986	; 0x3da
- 80072c8:	4934      	ldr	r1, [pc, #208]	; (800739c <pbuf_copy+0x198>)
- 80072ca:	4832      	ldr	r0, [pc, #200]	; (8007394 <pbuf_copy+0x190>)
- 80072cc:	f009 fc7c 	bl	8010bc8 <iprintf>
-    if (offset_from >= p_from->len) {
- 80072d0:	683b      	ldr	r3, [r7, #0]
- 80072d2:	895b      	ldrh	r3, [r3, #10]
- 80072d4:	461a      	mov	r2, r3
- 80072d6:	693b      	ldr	r3, [r7, #16]
- 80072d8:	4293      	cmp	r3, r2
- 80072da:	d304      	bcc.n	80072e6 <pbuf_copy+0xe2>
-      /* on to next p_from (if any) */
-      offset_from = 0;
- 80072dc:	2300      	movs	r3, #0
- 80072de:	613b      	str	r3, [r7, #16]
-      p_from = p_from->next;
- 80072e0:	683b      	ldr	r3, [r7, #0]
- 80072e2:	681b      	ldr	r3, [r3, #0]
- 80072e4:	603b      	str	r3, [r7, #0]
-    }
-    if (offset_to == p_to->len) {
- 80072e6:	687b      	ldr	r3, [r7, #4]
- 80072e8:	895b      	ldrh	r3, [r3, #10]
- 80072ea:	461a      	mov	r2, r3
- 80072ec:	697b      	ldr	r3, [r7, #20]
- 80072ee:	4293      	cmp	r3, r2
- 80072f0:	d114      	bne.n	800731c <pbuf_copy+0x118>
-      /* on to next p_to (if any) */
-      offset_to = 0;
- 80072f2:	2300      	movs	r3, #0
- 80072f4:	617b      	str	r3, [r7, #20]
-      p_to = p_to->next;
- 80072f6:	687b      	ldr	r3, [r7, #4]
- 80072f8:	681b      	ldr	r3, [r3, #0]
- 80072fa:	607b      	str	r3, [r7, #4]
-      LWIP_ERROR("p_to != NULL", (p_to != NULL) || (p_from == NULL), return ERR_ARG;);
- 80072fc:	687b      	ldr	r3, [r7, #4]
- 80072fe:	2b00      	cmp	r3, #0
- 8007300:	d10c      	bne.n	800731c <pbuf_copy+0x118>
- 8007302:	683b      	ldr	r3, [r7, #0]
- 8007304:	2b00      	cmp	r3, #0
- 8007306:	d009      	beq.n	800731c <pbuf_copy+0x118>
- 8007308:	4b20      	ldr	r3, [pc, #128]	; (800738c <pbuf_copy+0x188>)
- 800730a:	f44f 7279 	mov.w	r2, #996	; 0x3e4
- 800730e:	4924      	ldr	r1, [pc, #144]	; (80073a0 <pbuf_copy+0x19c>)
- 8007310:	4820      	ldr	r0, [pc, #128]	; (8007394 <pbuf_copy+0x190>)
- 8007312:	f009 fc59 	bl	8010bc8 <iprintf>
- 8007316:	f06f 030f 	mvn.w	r3, #15
- 800731a:	e032      	b.n	8007382 <pbuf_copy+0x17e>
-    }
-
-    if ((p_from != NULL) && (p_from->len == p_from->tot_len)) {
- 800731c:	683b      	ldr	r3, [r7, #0]
- 800731e:	2b00      	cmp	r3, #0
- 8007320:	d013      	beq.n	800734a <pbuf_copy+0x146>
- 8007322:	683b      	ldr	r3, [r7, #0]
- 8007324:	895a      	ldrh	r2, [r3, #10]
- 8007326:	683b      	ldr	r3, [r7, #0]
- 8007328:	891b      	ldrh	r3, [r3, #8]
- 800732a:	429a      	cmp	r2, r3
- 800732c:	d10d      	bne.n	800734a <pbuf_copy+0x146>
-      /* don't copy more than one packet! */
-      LWIP_ERROR("pbuf_copy() does not allow packet queues!",
- 800732e:	683b      	ldr	r3, [r7, #0]
- 8007330:	681b      	ldr	r3, [r3, #0]
- 8007332:	2b00      	cmp	r3, #0
- 8007334:	d009      	beq.n	800734a <pbuf_copy+0x146>
- 8007336:	4b15      	ldr	r3, [pc, #84]	; (800738c <pbuf_copy+0x188>)
- 8007338:	f240 32e9 	movw	r2, #1001	; 0x3e9
- 800733c:	4919      	ldr	r1, [pc, #100]	; (80073a4 <pbuf_copy+0x1a0>)
- 800733e:	4815      	ldr	r0, [pc, #84]	; (8007394 <pbuf_copy+0x190>)
- 8007340:	f009 fc42 	bl	8010bc8 <iprintf>
- 8007344:	f06f 0305 	mvn.w	r3, #5
- 8007348:	e01b      	b.n	8007382 <pbuf_copy+0x17e>
-                 (p_from->next == NULL), return ERR_VAL;);
-    }
-    if ((p_to != NULL) && (p_to->len == p_to->tot_len)) {
- 800734a:	687b      	ldr	r3, [r7, #4]
- 800734c:	2b00      	cmp	r3, #0
- 800734e:	d013      	beq.n	8007378 <pbuf_copy+0x174>
- 8007350:	687b      	ldr	r3, [r7, #4]
- 8007352:	895a      	ldrh	r2, [r3, #10]
- 8007354:	687b      	ldr	r3, [r7, #4]
- 8007356:	891b      	ldrh	r3, [r3, #8]
- 8007358:	429a      	cmp	r2, r3
- 800735a:	d10d      	bne.n	8007378 <pbuf_copy+0x174>
-      /* don't copy more than one packet! */
-      LWIP_ERROR("pbuf_copy() does not allow packet queues!",
- 800735c:	687b      	ldr	r3, [r7, #4]
- 800735e:	681b      	ldr	r3, [r3, #0]
- 8007360:	2b00      	cmp	r3, #0
- 8007362:	d009      	beq.n	8007378 <pbuf_copy+0x174>
- 8007364:	4b09      	ldr	r3, [pc, #36]	; (800738c <pbuf_copy+0x188>)
- 8007366:	f240 32ee 	movw	r2, #1006	; 0x3ee
- 800736a:	490e      	ldr	r1, [pc, #56]	; (80073a4 <pbuf_copy+0x1a0>)
- 800736c:	4809      	ldr	r0, [pc, #36]	; (8007394 <pbuf_copy+0x190>)
- 800736e:	f009 fc2b 	bl	8010bc8 <iprintf>
- 8007372:	f06f 0305 	mvn.w	r3, #5
- 8007376:	e004      	b.n	8007382 <pbuf_copy+0x17e>
-                 (p_to->next == NULL), return ERR_VAL;);
-    }
-  } while (p_from);
- 8007378:	683b      	ldr	r3, [r7, #0]
- 800737a:	2b00      	cmp	r3, #0
- 800737c:	f47f af61 	bne.w	8007242 <pbuf_copy+0x3e>
-  LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_copy: end of chain reached.\n"));
-  return ERR_OK;
- 8007380:	2300      	movs	r3, #0
-}
- 8007382:	4618      	mov	r0, r3
- 8007384:	3718      	adds	r7, #24
- 8007386:	46bd      	mov	sp, r7
- 8007388:	bd80      	pop	{r7, pc}
- 800738a:	bf00      	nop
- 800738c:	08012508 	.word	0x08012508
- 8007390:	080127b0 	.word	0x080127b0
- 8007394:	08012568 	.word	0x08012568
- 8007398:	080127e0 	.word	0x080127e0
- 800739c:	080127f8 	.word	0x080127f8
- 80073a0:	08012814 	.word	0x08012814
- 80073a4:	08012824 	.word	0x08012824
-
-080073a8 <pbuf_copy_partial>:
- * @param offset offset into the packet buffer from where to begin copying len bytes
- * @return the number of bytes copied, or 0 on failure
- */
-u16_t
-pbuf_copy_partial(const struct pbuf *buf, void *dataptr, u16_t len, u16_t offset)
-{
- 80073a8:	b580      	push	{r7, lr}
- 80073aa:	b088      	sub	sp, #32
- 80073ac:	af00      	add	r7, sp, #0
- 80073ae:	60f8      	str	r0, [r7, #12]
- 80073b0:	60b9      	str	r1, [r7, #8]
- 80073b2:	4611      	mov	r1, r2
- 80073b4:	461a      	mov	r2, r3
- 80073b6:	460b      	mov	r3, r1
- 80073b8:	80fb      	strh	r3, [r7, #6]
- 80073ba:	4613      	mov	r3, r2
- 80073bc:	80bb      	strh	r3, [r7, #4]
-  const struct pbuf *p;
-  u16_t left = 0;
- 80073be:	2300      	movs	r3, #0
- 80073c0:	837b      	strh	r3, [r7, #26]
-  u16_t buf_copy_len;
-  u16_t copied_total = 0;
- 80073c2:	2300      	movs	r3, #0
- 80073c4:	82fb      	strh	r3, [r7, #22]
-
-  LWIP_ERROR("pbuf_copy_partial: invalid buf", (buf != NULL), return 0;);
- 80073c6:	68fb      	ldr	r3, [r7, #12]
- 80073c8:	2b00      	cmp	r3, #0
- 80073ca:	d108      	bne.n	80073de <pbuf_copy_partial+0x36>
- 80073cc:	4b2b      	ldr	r3, [pc, #172]	; (800747c <pbuf_copy_partial+0xd4>)
- 80073ce:	f240 420a 	movw	r2, #1034	; 0x40a
- 80073d2:	492b      	ldr	r1, [pc, #172]	; (8007480 <pbuf_copy_partial+0xd8>)
- 80073d4:	482b      	ldr	r0, [pc, #172]	; (8007484 <pbuf_copy_partial+0xdc>)
- 80073d6:	f009 fbf7 	bl	8010bc8 <iprintf>
- 80073da:	2300      	movs	r3, #0
- 80073dc:	e04a      	b.n	8007474 <pbuf_copy_partial+0xcc>
-  LWIP_ERROR("pbuf_copy_partial: invalid dataptr", (dataptr != NULL), return 0;);
- 80073de:	68bb      	ldr	r3, [r7, #8]
- 80073e0:	2b00      	cmp	r3, #0
- 80073e2:	d108      	bne.n	80073f6 <pbuf_copy_partial+0x4e>
- 80073e4:	4b25      	ldr	r3, [pc, #148]	; (800747c <pbuf_copy_partial+0xd4>)
- 80073e6:	f240 420b 	movw	r2, #1035	; 0x40b
- 80073ea:	4927      	ldr	r1, [pc, #156]	; (8007488 <pbuf_copy_partial+0xe0>)
- 80073ec:	4825      	ldr	r0, [pc, #148]	; (8007484 <pbuf_copy_partial+0xdc>)
- 80073ee:	f009 fbeb 	bl	8010bc8 <iprintf>
- 80073f2:	2300      	movs	r3, #0
- 80073f4:	e03e      	b.n	8007474 <pbuf_copy_partial+0xcc>
-
-  /* Note some systems use byte copy if dataptr or one of the pbuf payload pointers are unaligned. */
-  for (p = buf; len != 0 && p != NULL; p = p->next) {
- 80073f6:	68fb      	ldr	r3, [r7, #12]
- 80073f8:	61fb      	str	r3, [r7, #28]
- 80073fa:	e034      	b.n	8007466 <pbuf_copy_partial+0xbe>
-    if ((offset != 0) && (offset >= p->len)) {
- 80073fc:	88bb      	ldrh	r3, [r7, #4]
- 80073fe:	2b00      	cmp	r3, #0
- 8007400:	d00a      	beq.n	8007418 <pbuf_copy_partial+0x70>
- 8007402:	69fb      	ldr	r3, [r7, #28]
- 8007404:	895b      	ldrh	r3, [r3, #10]
- 8007406:	88ba      	ldrh	r2, [r7, #4]
- 8007408:	429a      	cmp	r2, r3
- 800740a:	d305      	bcc.n	8007418 <pbuf_copy_partial+0x70>
-      /* don't copy from this buffer -> on to the next */
-      offset = (u16_t)(offset - p->len);
- 800740c:	69fb      	ldr	r3, [r7, #28]
- 800740e:	895b      	ldrh	r3, [r3, #10]
- 8007410:	88ba      	ldrh	r2, [r7, #4]
- 8007412:	1ad3      	subs	r3, r2, r3
- 8007414:	80bb      	strh	r3, [r7, #4]
- 8007416:	e023      	b.n	8007460 <pbuf_copy_partial+0xb8>
-    } else {
-      /* copy from this buffer. maybe only partially. */
-      buf_copy_len = (u16_t)(p->len - offset);
- 8007418:	69fb      	ldr	r3, [r7, #28]
- 800741a:	895a      	ldrh	r2, [r3, #10]
- 800741c:	88bb      	ldrh	r3, [r7, #4]
- 800741e:	1ad3      	subs	r3, r2, r3
- 8007420:	833b      	strh	r3, [r7, #24]
-      if (buf_copy_len > len) {
- 8007422:	8b3a      	ldrh	r2, [r7, #24]
- 8007424:	88fb      	ldrh	r3, [r7, #6]
- 8007426:	429a      	cmp	r2, r3
- 8007428:	d901      	bls.n	800742e <pbuf_copy_partial+0x86>
-        buf_copy_len = len;
- 800742a:	88fb      	ldrh	r3, [r7, #6]
- 800742c:	833b      	strh	r3, [r7, #24]
-      }
-      /* copy the necessary parts of the buffer */
-      MEMCPY(&((char *)dataptr)[left], &((char *)p->payload)[offset], buf_copy_len);
- 800742e:	8b7b      	ldrh	r3, [r7, #26]
- 8007430:	68ba      	ldr	r2, [r7, #8]
- 8007432:	18d0      	adds	r0, r2, r3
- 8007434:	69fb      	ldr	r3, [r7, #28]
- 8007436:	685a      	ldr	r2, [r3, #4]
- 8007438:	88bb      	ldrh	r3, [r7, #4]
- 800743a:	4413      	add	r3, r2
- 800743c:	8b3a      	ldrh	r2, [r7, #24]
- 800743e:	4619      	mov	r1, r3
- 8007440:	f009 fda3 	bl	8010f8a <memcpy>
-      copied_total = (u16_t)(copied_total + buf_copy_len);
- 8007444:	8afa      	ldrh	r2, [r7, #22]
- 8007446:	8b3b      	ldrh	r3, [r7, #24]
- 8007448:	4413      	add	r3, r2
- 800744a:	82fb      	strh	r3, [r7, #22]
-      left = (u16_t)(left + buf_copy_len);
- 800744c:	8b7a      	ldrh	r2, [r7, #26]
- 800744e:	8b3b      	ldrh	r3, [r7, #24]
- 8007450:	4413      	add	r3, r2
- 8007452:	837b      	strh	r3, [r7, #26]
-      len = (u16_t)(len - buf_copy_len);
- 8007454:	88fa      	ldrh	r2, [r7, #6]
- 8007456:	8b3b      	ldrh	r3, [r7, #24]
- 8007458:	1ad3      	subs	r3, r2, r3
- 800745a:	80fb      	strh	r3, [r7, #6]
-      offset = 0;
- 800745c:	2300      	movs	r3, #0
- 800745e:	80bb      	strh	r3, [r7, #4]
-  for (p = buf; len != 0 && p != NULL; p = p->next) {
- 8007460:	69fb      	ldr	r3, [r7, #28]
- 8007462:	681b      	ldr	r3, [r3, #0]
- 8007464:	61fb      	str	r3, [r7, #28]
- 8007466:	88fb      	ldrh	r3, [r7, #6]
- 8007468:	2b00      	cmp	r3, #0
- 800746a:	d002      	beq.n	8007472 <pbuf_copy_partial+0xca>
- 800746c:	69fb      	ldr	r3, [r7, #28]
- 800746e:	2b00      	cmp	r3, #0
- 8007470:	d1c4      	bne.n	80073fc <pbuf_copy_partial+0x54>
-    }
-  }
-  return copied_total;
- 8007472:	8afb      	ldrh	r3, [r7, #22]
-}
- 8007474:	4618      	mov	r0, r3
- 8007476:	3720      	adds	r7, #32
- 8007478:	46bd      	mov	sp, r7
- 800747a:	bd80      	pop	{r7, pc}
- 800747c:	08012508 	.word	0x08012508
- 8007480:	08012850 	.word	0x08012850
- 8007484:	08012568 	.word	0x08012568
- 8007488:	08012870 	.word	0x08012870
-
-0800748c <pbuf_clone>:
- *
- * @return a new pbuf or NULL if allocation fails
- */
-struct pbuf *
-pbuf_clone(pbuf_layer layer, pbuf_type type, struct pbuf *p)
-{
- 800748c:	b580      	push	{r7, lr}
- 800748e:	b084      	sub	sp, #16
- 8007490:	af00      	add	r7, sp, #0
- 8007492:	4603      	mov	r3, r0
- 8007494:	603a      	str	r2, [r7, #0]
- 8007496:	71fb      	strb	r3, [r7, #7]
- 8007498:	460b      	mov	r3, r1
- 800749a:	80bb      	strh	r3, [r7, #4]
-  struct pbuf *q;
-  err_t err;
-  q = pbuf_alloc(layer, p->tot_len, type);
- 800749c:	683b      	ldr	r3, [r7, #0]
- 800749e:	8919      	ldrh	r1, [r3, #8]
- 80074a0:	88ba      	ldrh	r2, [r7, #4]
- 80074a2:	79fb      	ldrb	r3, [r7, #7]
- 80074a4:	4618      	mov	r0, r3
- 80074a6:	f7ff fab1 	bl	8006a0c <pbuf_alloc>
- 80074aa:	60f8      	str	r0, [r7, #12]
-  if (q == NULL) {
- 80074ac:	68fb      	ldr	r3, [r7, #12]
- 80074ae:	2b00      	cmp	r3, #0
- 80074b0:	d101      	bne.n	80074b6 <pbuf_clone+0x2a>
-    return NULL;
- 80074b2:	2300      	movs	r3, #0
- 80074b4:	e011      	b.n	80074da <pbuf_clone+0x4e>
-  }
-  err = pbuf_copy(q, p);
- 80074b6:	6839      	ldr	r1, [r7, #0]
- 80074b8:	68f8      	ldr	r0, [r7, #12]
- 80074ba:	f7ff fea3 	bl	8007204 <pbuf_copy>
- 80074be:	4603      	mov	r3, r0
- 80074c0:	72fb      	strb	r3, [r7, #11]
-  LWIP_UNUSED_ARG(err); /* in case of LWIP_NOASSERT */
-  LWIP_ASSERT("pbuf_copy failed", err == ERR_OK);
- 80074c2:	f997 300b 	ldrsb.w	r3, [r7, #11]
- 80074c6:	2b00      	cmp	r3, #0
- 80074c8:	d006      	beq.n	80074d8 <pbuf_clone+0x4c>
- 80074ca:	4b06      	ldr	r3, [pc, #24]	; (80074e4 <pbuf_clone+0x58>)
- 80074cc:	f240 5224 	movw	r2, #1316	; 0x524
- 80074d0:	4905      	ldr	r1, [pc, #20]	; (80074e8 <pbuf_clone+0x5c>)
- 80074d2:	4806      	ldr	r0, [pc, #24]	; (80074ec <pbuf_clone+0x60>)
- 80074d4:	f009 fb78 	bl	8010bc8 <iprintf>
-  return q;
- 80074d8:	68fb      	ldr	r3, [r7, #12]
-}
- 80074da:	4618      	mov	r0, r3
- 80074dc:	3710      	adds	r7, #16
- 80074de:	46bd      	mov	sp, r7
- 80074e0:	bd80      	pop	{r7, pc}
- 80074e2:	bf00      	nop
- 80074e4:	08012508 	.word	0x08012508
- 80074e8:	0801297c 	.word	0x0801297c
- 80074ec:	08012568 	.word	0x08012568
-
-080074f0 <tcp_init>:
-/**
- * Initialize this module.
- */
-void
-tcp_init(void)
-{
- 80074f0:	b580      	push	{r7, lr}
- 80074f2:	af00      	add	r7, sp, #0
-#ifdef LWIP_RAND
-  tcp_port = TCP_ENSURE_LOCAL_PORT_RANGE(LWIP_RAND());
- 80074f4:	f008 feb4 	bl	8010260 <rand>
- 80074f8:	4603      	mov	r3, r0
- 80074fa:	b29b      	uxth	r3, r3
- 80074fc:	f3c3 030d 	ubfx	r3, r3, #0, #14
- 8007500:	b29b      	uxth	r3, r3
- 8007502:	f5a3 4380 	sub.w	r3, r3, #16384	; 0x4000
- 8007506:	b29a      	uxth	r2, r3
- 8007508:	4b01      	ldr	r3, [pc, #4]	; (8007510 <tcp_init+0x20>)
- 800750a:	801a      	strh	r2, [r3, #0]
-#endif /* LWIP_RAND */
-}
- 800750c:	bf00      	nop
- 800750e:	bd80      	pop	{r7, pc}
- 8007510:	24000068 	.word	0x24000068
-
-08007514 <tcp_free>:
-
-/** Free a tcp pcb */
-void
-tcp_free(struct tcp_pcb *pcb)
-{
- 8007514:	b580      	push	{r7, lr}
- 8007516:	b082      	sub	sp, #8
- 8007518:	af00      	add	r7, sp, #0
- 800751a:	6078      	str	r0, [r7, #4]
-  LWIP_ASSERT("tcp_free: LISTEN", pcb->state != LISTEN);
- 800751c:	687b      	ldr	r3, [r7, #4]
- 800751e:	7d1b      	ldrb	r3, [r3, #20]
- 8007520:	2b01      	cmp	r3, #1
- 8007522:	d105      	bne.n	8007530 <tcp_free+0x1c>
- 8007524:	4b06      	ldr	r3, [pc, #24]	; (8007540 <tcp_free+0x2c>)
- 8007526:	22d4      	movs	r2, #212	; 0xd4
- 8007528:	4906      	ldr	r1, [pc, #24]	; (8007544 <tcp_free+0x30>)
- 800752a:	4807      	ldr	r0, [pc, #28]	; (8007548 <tcp_free+0x34>)
- 800752c:	f009 fb4c 	bl	8010bc8 <iprintf>
-#if LWIP_TCP_PCB_NUM_EXT_ARGS
-  tcp_ext_arg_invoke_callbacks_destroyed(pcb->ext_args);
-#endif
-  memp_free(MEMP_TCP_PCB, pcb);
- 8007530:	6879      	ldr	r1, [r7, #4]
- 8007532:	2001      	movs	r0, #1
- 8007534:	f7fe fde2 	bl	80060fc <memp_free>
-}
- 8007538:	bf00      	nop
- 800753a:	3708      	adds	r7, #8
- 800753c:	46bd      	mov	sp, r7
- 800753e:	bd80      	pop	{r7, pc}
- 8007540:	08012a08 	.word	0x08012a08
- 8007544:	08012a38 	.word	0x08012a38
- 8007548:	08012a4c 	.word	0x08012a4c
-
-0800754c <tcp_free_listen>:
-
-/** Free a tcp listen pcb */
-static void
-tcp_free_listen(struct tcp_pcb *pcb)
-{
- 800754c:	b580      	push	{r7, lr}
- 800754e:	b082      	sub	sp, #8
- 8007550:	af00      	add	r7, sp, #0
- 8007552:	6078      	str	r0, [r7, #4]
-  LWIP_ASSERT("tcp_free_listen: !LISTEN", pcb->state != LISTEN);
- 8007554:	687b      	ldr	r3, [r7, #4]
- 8007556:	7d1b      	ldrb	r3, [r3, #20]
- 8007558:	2b01      	cmp	r3, #1
- 800755a:	d105      	bne.n	8007568 <tcp_free_listen+0x1c>
- 800755c:	4b06      	ldr	r3, [pc, #24]	; (8007578 <tcp_free_listen+0x2c>)
- 800755e:	22df      	movs	r2, #223	; 0xdf
- 8007560:	4906      	ldr	r1, [pc, #24]	; (800757c <tcp_free_listen+0x30>)
- 8007562:	4807      	ldr	r0, [pc, #28]	; (8007580 <tcp_free_listen+0x34>)
- 8007564:	f009 fb30 	bl	8010bc8 <iprintf>
-#if LWIP_TCP_PCB_NUM_EXT_ARGS
-  tcp_ext_arg_invoke_callbacks_destroyed(pcb->ext_args);
-#endif
-  memp_free(MEMP_TCP_PCB_LISTEN, pcb);
- 8007568:	6879      	ldr	r1, [r7, #4]
- 800756a:	2002      	movs	r0, #2
- 800756c:	f7fe fdc6 	bl	80060fc <memp_free>
-}
- 8007570:	bf00      	nop
- 8007572:	3708      	adds	r7, #8
- 8007574:	46bd      	mov	sp, r7
- 8007576:	bd80      	pop	{r7, pc}
- 8007578:	08012a08 	.word	0x08012a08
- 800757c:	08012a74 	.word	0x08012a74
- 8007580:	08012a4c 	.word	0x08012a4c
-
-08007584 <tcp_tmr>:
-/**
- * Called periodically to dispatch TCP timers.
- */
-void
-tcp_tmr(void)
-{
- 8007584:	b580      	push	{r7, lr}
- 8007586:	af00      	add	r7, sp, #0
-  /* Call tcp_fasttmr() every 250 ms */
-  tcp_fasttmr();
- 8007588:	f001 f800 	bl	800858c <tcp_fasttmr>
-
-  if (++tcp_timer & 1) {
- 800758c:	4b07      	ldr	r3, [pc, #28]	; (80075ac <tcp_tmr+0x28>)
- 800758e:	781b      	ldrb	r3, [r3, #0]
- 8007590:	3301      	adds	r3, #1
- 8007592:	b2da      	uxtb	r2, r3
- 8007594:	4b05      	ldr	r3, [pc, #20]	; (80075ac <tcp_tmr+0x28>)
- 8007596:	701a      	strb	r2, [r3, #0]
- 8007598:	4b04      	ldr	r3, [pc, #16]	; (80075ac <tcp_tmr+0x28>)
- 800759a:	781b      	ldrb	r3, [r3, #0]
- 800759c:	f003 0301 	and.w	r3, r3, #1
- 80075a0:	2b00      	cmp	r3, #0
- 80075a2:	d001      	beq.n	80075a8 <tcp_tmr+0x24>
-    /* Call tcp_slowtmr() every 500 ms, i.e., every other timer
-       tcp_tmr() is called. */
-    tcp_slowtmr();
- 80075a4:	f000 fcb2 	bl	8007f0c <tcp_slowtmr>
-  }
-}
- 80075a8:	bf00      	nop
- 80075aa:	bd80      	pop	{r7, pc}
- 80075ac:	24007b81 	.word	0x24007b81
-
-080075b0 <tcp_remove_listener>:
-/** Called when a listen pcb is closed. Iterates one pcb list and removes the
- * closed listener pcb from pcb->listener if matching.
- */
-static void
-tcp_remove_listener(struct tcp_pcb *list, struct tcp_pcb_listen *lpcb)
-{
- 80075b0:	b580      	push	{r7, lr}
- 80075b2:	b084      	sub	sp, #16
- 80075b4:	af00      	add	r7, sp, #0
- 80075b6:	6078      	str	r0, [r7, #4]
- 80075b8:	6039      	str	r1, [r7, #0]
-  struct tcp_pcb *pcb;
-
-  LWIP_ASSERT("tcp_remove_listener: invalid listener", lpcb != NULL);
- 80075ba:	683b      	ldr	r3, [r7, #0]
- 80075bc:	2b00      	cmp	r3, #0
- 80075be:	d105      	bne.n	80075cc <tcp_remove_listener+0x1c>
- 80075c0:	4b0d      	ldr	r3, [pc, #52]	; (80075f8 <tcp_remove_listener+0x48>)
- 80075c2:	22ff      	movs	r2, #255	; 0xff
- 80075c4:	490d      	ldr	r1, [pc, #52]	; (80075fc <tcp_remove_listener+0x4c>)
- 80075c6:	480e      	ldr	r0, [pc, #56]	; (8007600 <tcp_remove_listener+0x50>)
- 80075c8:	f009 fafe 	bl	8010bc8 <iprintf>
-
-  for (pcb = list; pcb != NULL; pcb = pcb->next) {
- 80075cc:	687b      	ldr	r3, [r7, #4]
- 80075ce:	60fb      	str	r3, [r7, #12]
- 80075d0:	e00a      	b.n	80075e8 <tcp_remove_listener+0x38>
-    if (pcb->listener == lpcb) {
- 80075d2:	68fb      	ldr	r3, [r7, #12]
- 80075d4:	6fdb      	ldr	r3, [r3, #124]	; 0x7c
- 80075d6:	683a      	ldr	r2, [r7, #0]
- 80075d8:	429a      	cmp	r2, r3
- 80075da:	d102      	bne.n	80075e2 <tcp_remove_listener+0x32>
-      pcb->listener = NULL;
- 80075dc:	68fb      	ldr	r3, [r7, #12]
- 80075de:	2200      	movs	r2, #0
- 80075e0:	67da      	str	r2, [r3, #124]	; 0x7c
-  for (pcb = list; pcb != NULL; pcb = pcb->next) {
- 80075e2:	68fb      	ldr	r3, [r7, #12]
- 80075e4:	68db      	ldr	r3, [r3, #12]
- 80075e6:	60fb      	str	r3, [r7, #12]
- 80075e8:	68fb      	ldr	r3, [r7, #12]
- 80075ea:	2b00      	cmp	r3, #0
- 80075ec:	d1f1      	bne.n	80075d2 <tcp_remove_listener+0x22>
-    }
-  }
-}
- 80075ee:	bf00      	nop
- 80075f0:	bf00      	nop
- 80075f2:	3710      	adds	r7, #16
- 80075f4:	46bd      	mov	sp, r7
- 80075f6:	bd80      	pop	{r7, pc}
- 80075f8:	08012a08 	.word	0x08012a08
- 80075fc:	08012a90 	.word	0x08012a90
- 8007600:	08012a4c 	.word	0x08012a4c
-
-08007604 <tcp_listen_closed>:
-/** Called when a listen pcb is closed. Iterates all pcb lists and removes the
- * closed listener pcb from pcb->listener if matching.
- */
-static void
-tcp_listen_closed(struct tcp_pcb *pcb)
-{
- 8007604:	b580      	push	{r7, lr}
- 8007606:	b084      	sub	sp, #16
- 8007608:	af00      	add	r7, sp, #0
- 800760a:	6078      	str	r0, [r7, #4]
-#if LWIP_CALLBACK_API || TCP_LISTEN_BACKLOG
-  size_t i;
-  LWIP_ASSERT("pcb != NULL", pcb != NULL);
- 800760c:	687b      	ldr	r3, [r7, #4]
- 800760e:	2b00      	cmp	r3, #0
- 8007610:	d106      	bne.n	8007620 <tcp_listen_closed+0x1c>
- 8007612:	4b14      	ldr	r3, [pc, #80]	; (8007664 <tcp_listen_closed+0x60>)
- 8007614:	f240 1211 	movw	r2, #273	; 0x111
- 8007618:	4913      	ldr	r1, [pc, #76]	; (8007668 <tcp_listen_closed+0x64>)
- 800761a:	4814      	ldr	r0, [pc, #80]	; (800766c <tcp_listen_closed+0x68>)
- 800761c:	f009 fad4 	bl	8010bc8 <iprintf>
-  LWIP_ASSERT("pcb->state == LISTEN", pcb->state == LISTEN);
- 8007620:	687b      	ldr	r3, [r7, #4]
- 8007622:	7d1b      	ldrb	r3, [r3, #20]
- 8007624:	2b01      	cmp	r3, #1
- 8007626:	d006      	beq.n	8007636 <tcp_listen_closed+0x32>
- 8007628:	4b0e      	ldr	r3, [pc, #56]	; (8007664 <tcp_listen_closed+0x60>)
- 800762a:	f44f 7289 	mov.w	r2, #274	; 0x112
- 800762e:	4910      	ldr	r1, [pc, #64]	; (8007670 <tcp_listen_closed+0x6c>)
- 8007630:	480e      	ldr	r0, [pc, #56]	; (800766c <tcp_listen_closed+0x68>)
- 8007632:	f009 fac9 	bl	8010bc8 <iprintf>
-  for (i = 1; i < LWIP_ARRAYSIZE(tcp_pcb_lists); i++) {
- 8007636:	2301      	movs	r3, #1
- 8007638:	60fb      	str	r3, [r7, #12]
- 800763a:	e00b      	b.n	8007654 <tcp_listen_closed+0x50>
-    tcp_remove_listener(*tcp_pcb_lists[i], (struct tcp_pcb_listen *)pcb);
- 800763c:	4a0d      	ldr	r2, [pc, #52]	; (8007674 <tcp_listen_closed+0x70>)
- 800763e:	68fb      	ldr	r3, [r7, #12]
- 8007640:	f852 3023 	ldr.w	r3, [r2, r3, lsl #2]
- 8007644:	681b      	ldr	r3, [r3, #0]
- 8007646:	6879      	ldr	r1, [r7, #4]
- 8007648:	4618      	mov	r0, r3
- 800764a:	f7ff ffb1 	bl	80075b0 <tcp_remove_listener>
-  for (i = 1; i < LWIP_ARRAYSIZE(tcp_pcb_lists); i++) {
- 800764e:	68fb      	ldr	r3, [r7, #12]
- 8007650:	3301      	adds	r3, #1
- 8007652:	60fb      	str	r3, [r7, #12]
- 8007654:	68fb      	ldr	r3, [r7, #12]
- 8007656:	2b03      	cmp	r3, #3
- 8007658:	d9f0      	bls.n	800763c <tcp_listen_closed+0x38>
-  }
-#endif
-  LWIP_UNUSED_ARG(pcb);
-}
- 800765a:	bf00      	nop
- 800765c:	bf00      	nop
- 800765e:	3710      	adds	r7, #16
- 8007660:	46bd      	mov	sp, r7
- 8007662:	bd80      	pop	{r7, pc}
- 8007664:	08012a08 	.word	0x08012a08
- 8007668:	08012ab8 	.word	0x08012ab8
- 800766c:	08012a4c 	.word	0x08012a4c
- 8007670:	08012ac4 	.word	0x08012ac4
- 8007674:	08014d6c 	.word	0x08014d6c
-
-08007678 <tcp_close_shutdown>:
- * @return ERR_OK if connection has been closed
- *         another err_t if closing failed and pcb is not freed
- */
-static err_t
-tcp_close_shutdown(struct tcp_pcb *pcb, u8_t rst_on_unacked_data)
-{
- 8007678:	b5b0      	push	{r4, r5, r7, lr}
- 800767a:	b088      	sub	sp, #32
- 800767c:	af04      	add	r7, sp, #16
- 800767e:	6078      	str	r0, [r7, #4]
- 8007680:	460b      	mov	r3, r1
- 8007682:	70fb      	strb	r3, [r7, #3]
-  LWIP_ASSERT("tcp_close_shutdown: invalid pcb", pcb != NULL);
- 8007684:	687b      	ldr	r3, [r7, #4]
- 8007686:	2b00      	cmp	r3, #0
- 8007688:	d106      	bne.n	8007698 <tcp_close_shutdown+0x20>
- 800768a:	4b63      	ldr	r3, [pc, #396]	; (8007818 <tcp_close_shutdown+0x1a0>)
- 800768c:	f44f 72af 	mov.w	r2, #350	; 0x15e
- 8007690:	4962      	ldr	r1, [pc, #392]	; (800781c <tcp_close_shutdown+0x1a4>)
- 8007692:	4863      	ldr	r0, [pc, #396]	; (8007820 <tcp_close_shutdown+0x1a8>)
- 8007694:	f009 fa98 	bl	8010bc8 <iprintf>
-
-  if (rst_on_unacked_data && ((pcb->state == ESTABLISHED) || (pcb->state == CLOSE_WAIT))) {
- 8007698:	78fb      	ldrb	r3, [r7, #3]
- 800769a:	2b00      	cmp	r3, #0
- 800769c:	d066      	beq.n	800776c <tcp_close_shutdown+0xf4>
- 800769e:	687b      	ldr	r3, [r7, #4]
- 80076a0:	7d1b      	ldrb	r3, [r3, #20]
- 80076a2:	2b04      	cmp	r3, #4
- 80076a4:	d003      	beq.n	80076ae <tcp_close_shutdown+0x36>
- 80076a6:	687b      	ldr	r3, [r7, #4]
- 80076a8:	7d1b      	ldrb	r3, [r3, #20]
- 80076aa:	2b07      	cmp	r3, #7
- 80076ac:	d15e      	bne.n	800776c <tcp_close_shutdown+0xf4>
-    if ((pcb->refused_data != NULL) || (pcb->rcv_wnd != TCP_WND_MAX(pcb))) {
- 80076ae:	687b      	ldr	r3, [r7, #4]
- 80076b0:	6f9b      	ldr	r3, [r3, #120]	; 0x78
- 80076b2:	2b00      	cmp	r3, #0
- 80076b4:	d104      	bne.n	80076c0 <tcp_close_shutdown+0x48>
- 80076b6:	687b      	ldr	r3, [r7, #4]
- 80076b8:	8d1b      	ldrh	r3, [r3, #40]	; 0x28
- 80076ba:	f5b3 6f06 	cmp.w	r3, #2144	; 0x860
- 80076be:	d055      	beq.n	800776c <tcp_close_shutdown+0xf4>
-      /* Not all data received by application, send RST to tell the remote
-         side about this. */
-      LWIP_ASSERT("pcb->flags & TF_RXCLOSED", pcb->flags & TF_RXCLOSED);
- 80076c0:	687b      	ldr	r3, [r7, #4]
- 80076c2:	8b5b      	ldrh	r3, [r3, #26]
- 80076c4:	f003 0310 	and.w	r3, r3, #16
- 80076c8:	2b00      	cmp	r3, #0
- 80076ca:	d106      	bne.n	80076da <tcp_close_shutdown+0x62>
- 80076cc:	4b52      	ldr	r3, [pc, #328]	; (8007818 <tcp_close_shutdown+0x1a0>)
- 80076ce:	f44f 72b2 	mov.w	r2, #356	; 0x164
- 80076d2:	4954      	ldr	r1, [pc, #336]	; (8007824 <tcp_close_shutdown+0x1ac>)
- 80076d4:	4852      	ldr	r0, [pc, #328]	; (8007820 <tcp_close_shutdown+0x1a8>)
- 80076d6:	f009 fa77 	bl	8010bc8 <iprintf>
-
-      /* don't call tcp_abort here: we must not deallocate the pcb since
-         that might not be expected when calling tcp_close */
-      tcp_rst(pcb, pcb->snd_nxt, pcb->rcv_nxt, &pcb->local_ip, &pcb->remote_ip,
- 80076da:	687b      	ldr	r3, [r7, #4]
- 80076dc:	6d18      	ldr	r0, [r3, #80]	; 0x50
- 80076de:	687b      	ldr	r3, [r7, #4]
- 80076e0:	6a5c      	ldr	r4, [r3, #36]	; 0x24
- 80076e2:	687d      	ldr	r5, [r7, #4]
- 80076e4:	687b      	ldr	r3, [r7, #4]
- 80076e6:	3304      	adds	r3, #4
- 80076e8:	687a      	ldr	r2, [r7, #4]
- 80076ea:	8ad2      	ldrh	r2, [r2, #22]
- 80076ec:	6879      	ldr	r1, [r7, #4]
- 80076ee:	8b09      	ldrh	r1, [r1, #24]
- 80076f0:	9102      	str	r1, [sp, #8]
- 80076f2:	9201      	str	r2, [sp, #4]
- 80076f4:	9300      	str	r3, [sp, #0]
- 80076f6:	462b      	mov	r3, r5
- 80076f8:	4622      	mov	r2, r4
- 80076fa:	4601      	mov	r1, r0
- 80076fc:	6878      	ldr	r0, [r7, #4]
- 80076fe:	f005 fd39 	bl	800d174 <tcp_rst>
-              pcb->local_port, pcb->remote_port);
-
-      tcp_pcb_purge(pcb);
- 8007702:	6878      	ldr	r0, [r7, #4]
- 8007704:	f001 faa4 	bl	8008c50 <tcp_pcb_purge>
-      TCP_RMV_ACTIVE(pcb);
- 8007708:	4b47      	ldr	r3, [pc, #284]	; (8007828 <tcp_close_shutdown+0x1b0>)
- 800770a:	681b      	ldr	r3, [r3, #0]
- 800770c:	687a      	ldr	r2, [r7, #4]
- 800770e:	429a      	cmp	r2, r3
- 8007710:	d105      	bne.n	800771e <tcp_close_shutdown+0xa6>
- 8007712:	4b45      	ldr	r3, [pc, #276]	; (8007828 <tcp_close_shutdown+0x1b0>)
- 8007714:	681b      	ldr	r3, [r3, #0]
- 8007716:	68db      	ldr	r3, [r3, #12]
- 8007718:	4a43      	ldr	r2, [pc, #268]	; (8007828 <tcp_close_shutdown+0x1b0>)
- 800771a:	6013      	str	r3, [r2, #0]
- 800771c:	e013      	b.n	8007746 <tcp_close_shutdown+0xce>
- 800771e:	4b42      	ldr	r3, [pc, #264]	; (8007828 <tcp_close_shutdown+0x1b0>)
- 8007720:	681b      	ldr	r3, [r3, #0]
- 8007722:	60fb      	str	r3, [r7, #12]
- 8007724:	e00c      	b.n	8007740 <tcp_close_shutdown+0xc8>
- 8007726:	68fb      	ldr	r3, [r7, #12]
- 8007728:	68db      	ldr	r3, [r3, #12]
- 800772a:	687a      	ldr	r2, [r7, #4]
- 800772c:	429a      	cmp	r2, r3
- 800772e:	d104      	bne.n	800773a <tcp_close_shutdown+0xc2>
- 8007730:	687b      	ldr	r3, [r7, #4]
- 8007732:	68da      	ldr	r2, [r3, #12]
- 8007734:	68fb      	ldr	r3, [r7, #12]
- 8007736:	60da      	str	r2, [r3, #12]
- 8007738:	e005      	b.n	8007746 <tcp_close_shutdown+0xce>
- 800773a:	68fb      	ldr	r3, [r7, #12]
- 800773c:	68db      	ldr	r3, [r3, #12]
- 800773e:	60fb      	str	r3, [r7, #12]
- 8007740:	68fb      	ldr	r3, [r7, #12]
- 8007742:	2b00      	cmp	r3, #0
- 8007744:	d1ef      	bne.n	8007726 <tcp_close_shutdown+0xae>
- 8007746:	687b      	ldr	r3, [r7, #4]
- 8007748:	2200      	movs	r2, #0
- 800774a:	60da      	str	r2, [r3, #12]
- 800774c:	4b37      	ldr	r3, [pc, #220]	; (800782c <tcp_close_shutdown+0x1b4>)
- 800774e:	2201      	movs	r2, #1
- 8007750:	701a      	strb	r2, [r3, #0]
-      /* Deallocate the pcb since we already sent a RST for it */
-      if (tcp_input_pcb == pcb) {
- 8007752:	4b37      	ldr	r3, [pc, #220]	; (8007830 <tcp_close_shutdown+0x1b8>)
- 8007754:	681b      	ldr	r3, [r3, #0]
- 8007756:	687a      	ldr	r2, [r7, #4]
- 8007758:	429a      	cmp	r2, r3
- 800775a:	d102      	bne.n	8007762 <tcp_close_shutdown+0xea>
-        /* prevent using a deallocated pcb: free it from tcp_input later */
-        tcp_trigger_input_pcb_close();
- 800775c:	f003 ff42 	bl	800b5e4 <tcp_trigger_input_pcb_close>
- 8007760:	e002      	b.n	8007768 <tcp_close_shutdown+0xf0>
-      } else {
-        tcp_free(pcb);
- 8007762:	6878      	ldr	r0, [r7, #4]
- 8007764:	f7ff fed6 	bl	8007514 <tcp_free>
-      }
-      return ERR_OK;
- 8007768:	2300      	movs	r3, #0
- 800776a:	e050      	b.n	800780e <tcp_close_shutdown+0x196>
-    }
-  }
-
-  /* - states which free the pcb are handled here,
-     - states which send FIN and change state are handled in tcp_close_shutdown_fin() */
-  switch (pcb->state) {
- 800776c:	687b      	ldr	r3, [r7, #4]
- 800776e:	7d1b      	ldrb	r3, [r3, #20]
- 8007770:	2b02      	cmp	r3, #2
- 8007772:	d03b      	beq.n	80077ec <tcp_close_shutdown+0x174>
- 8007774:	2b02      	cmp	r3, #2
- 8007776:	dc44      	bgt.n	8007802 <tcp_close_shutdown+0x18a>
- 8007778:	2b00      	cmp	r3, #0
- 800777a:	d002      	beq.n	8007782 <tcp_close_shutdown+0x10a>
- 800777c:	2b01      	cmp	r3, #1
- 800777e:	d02a      	beq.n	80077d6 <tcp_close_shutdown+0x15e>
- 8007780:	e03f      	b.n	8007802 <tcp_close_shutdown+0x18a>
-       * and the user needs some way to free it should the need arise.
-       * Calling tcp_close() with a pcb that has already been closed, (i.e. twice)
-       * or for a pcb that has been used and then entered the CLOSED state
-       * is erroneous, but this should never happen as the pcb has in those cases
-       * been freed, and so any remaining handles are bogus. */
-      if (pcb->local_port != 0) {
- 8007782:	687b      	ldr	r3, [r7, #4]
- 8007784:	8adb      	ldrh	r3, [r3, #22]
- 8007786:	2b00      	cmp	r3, #0
- 8007788:	d021      	beq.n	80077ce <tcp_close_shutdown+0x156>
-        TCP_RMV(&tcp_bound_pcbs, pcb);
- 800778a:	4b2a      	ldr	r3, [pc, #168]	; (8007834 <tcp_close_shutdown+0x1bc>)
- 800778c:	681b      	ldr	r3, [r3, #0]
- 800778e:	687a      	ldr	r2, [r7, #4]
- 8007790:	429a      	cmp	r2, r3
- 8007792:	d105      	bne.n	80077a0 <tcp_close_shutdown+0x128>
- 8007794:	4b27      	ldr	r3, [pc, #156]	; (8007834 <tcp_close_shutdown+0x1bc>)
- 8007796:	681b      	ldr	r3, [r3, #0]
- 8007798:	68db      	ldr	r3, [r3, #12]
- 800779a:	4a26      	ldr	r2, [pc, #152]	; (8007834 <tcp_close_shutdown+0x1bc>)
- 800779c:	6013      	str	r3, [r2, #0]
- 800779e:	e013      	b.n	80077c8 <tcp_close_shutdown+0x150>
- 80077a0:	4b24      	ldr	r3, [pc, #144]	; (8007834 <tcp_close_shutdown+0x1bc>)
- 80077a2:	681b      	ldr	r3, [r3, #0]
- 80077a4:	60bb      	str	r3, [r7, #8]
- 80077a6:	e00c      	b.n	80077c2 <tcp_close_shutdown+0x14a>
- 80077a8:	68bb      	ldr	r3, [r7, #8]
- 80077aa:	68db      	ldr	r3, [r3, #12]
- 80077ac:	687a      	ldr	r2, [r7, #4]
- 80077ae:	429a      	cmp	r2, r3
- 80077b0:	d104      	bne.n	80077bc <tcp_close_shutdown+0x144>
- 80077b2:	687b      	ldr	r3, [r7, #4]
- 80077b4:	68da      	ldr	r2, [r3, #12]
- 80077b6:	68bb      	ldr	r3, [r7, #8]
- 80077b8:	60da      	str	r2, [r3, #12]
- 80077ba:	e005      	b.n	80077c8 <tcp_close_shutdown+0x150>
- 80077bc:	68bb      	ldr	r3, [r7, #8]
- 80077be:	68db      	ldr	r3, [r3, #12]
- 80077c0:	60bb      	str	r3, [r7, #8]
- 80077c2:	68bb      	ldr	r3, [r7, #8]
- 80077c4:	2b00      	cmp	r3, #0
- 80077c6:	d1ef      	bne.n	80077a8 <tcp_close_shutdown+0x130>
- 80077c8:	687b      	ldr	r3, [r7, #4]
- 80077ca:	2200      	movs	r2, #0
- 80077cc:	60da      	str	r2, [r3, #12]
-      }
-      tcp_free(pcb);
- 80077ce:	6878      	ldr	r0, [r7, #4]
- 80077d0:	f7ff fea0 	bl	8007514 <tcp_free>
-      break;
- 80077d4:	e01a      	b.n	800780c <tcp_close_shutdown+0x194>
-    case LISTEN:
-      tcp_listen_closed(pcb);
- 80077d6:	6878      	ldr	r0, [r7, #4]
- 80077d8:	f7ff ff14 	bl	8007604 <tcp_listen_closed>
-      tcp_pcb_remove(&tcp_listen_pcbs.pcbs, pcb);
- 80077dc:	6879      	ldr	r1, [r7, #4]
- 80077de:	4816      	ldr	r0, [pc, #88]	; (8007838 <tcp_close_shutdown+0x1c0>)
- 80077e0:	f001 fa86 	bl	8008cf0 <tcp_pcb_remove>
-      tcp_free_listen(pcb);
- 80077e4:	6878      	ldr	r0, [r7, #4]
- 80077e6:	f7ff feb1 	bl	800754c <tcp_free_listen>
-      break;
- 80077ea:	e00f      	b.n	800780c <tcp_close_shutdown+0x194>
-    case SYN_SENT:
-      TCP_PCB_REMOVE_ACTIVE(pcb);
- 80077ec:	6879      	ldr	r1, [r7, #4]
- 80077ee:	480e      	ldr	r0, [pc, #56]	; (8007828 <tcp_close_shutdown+0x1b0>)
- 80077f0:	f001 fa7e 	bl	8008cf0 <tcp_pcb_remove>
- 80077f4:	4b0d      	ldr	r3, [pc, #52]	; (800782c <tcp_close_shutdown+0x1b4>)
- 80077f6:	2201      	movs	r2, #1
- 80077f8:	701a      	strb	r2, [r3, #0]
-      tcp_free(pcb);
- 80077fa:	6878      	ldr	r0, [r7, #4]
- 80077fc:	f7ff fe8a 	bl	8007514 <tcp_free>
-      MIB2_STATS_INC(mib2.tcpattemptfails);
-      break;
- 8007800:	e004      	b.n	800780c <tcp_close_shutdown+0x194>
-    default:
-      return tcp_close_shutdown_fin(pcb);
- 8007802:	6878      	ldr	r0, [r7, #4]
- 8007804:	f000 f81a 	bl	800783c <tcp_close_shutdown_fin>
- 8007808:	4603      	mov	r3, r0
- 800780a:	e000      	b.n	800780e <tcp_close_shutdown+0x196>
-  }
-  return ERR_OK;
- 800780c:	2300      	movs	r3, #0
-}
- 800780e:	4618      	mov	r0, r3
- 8007810:	3710      	adds	r7, #16
- 8007812:	46bd      	mov	sp, r7
- 8007814:	bdb0      	pop	{r4, r5, r7, pc}
- 8007816:	bf00      	nop
- 8007818:	08012a08 	.word	0x08012a08
- 800781c:	08012adc 	.word	0x08012adc
- 8007820:	08012a4c 	.word	0x08012a4c
- 8007824:	08012afc 	.word	0x08012afc
- 8007828:	24007b78 	.word	0x24007b78
- 800782c:	24007b80 	.word	0x24007b80
- 8007830:	24007bbc 	.word	0x24007bbc
- 8007834:	24007b70 	.word	0x24007b70
- 8007838:	24007b74 	.word	0x24007b74
-
-0800783c <tcp_close_shutdown_fin>:
-
-static err_t
-tcp_close_shutdown_fin(struct tcp_pcb *pcb)
-{
- 800783c:	b580      	push	{r7, lr}
- 800783e:	b084      	sub	sp, #16
- 8007840:	af00      	add	r7, sp, #0
- 8007842:	6078      	str	r0, [r7, #4]
-  err_t err;
-  LWIP_ASSERT("pcb != NULL", pcb != NULL);
- 8007844:	687b      	ldr	r3, [r7, #4]
- 8007846:	2b00      	cmp	r3, #0
- 8007848:	d106      	bne.n	8007858 <tcp_close_shutdown_fin+0x1c>
- 800784a:	4b2e      	ldr	r3, [pc, #184]	; (8007904 <tcp_close_shutdown_fin+0xc8>)
- 800784c:	f44f 72ce 	mov.w	r2, #412	; 0x19c
- 8007850:	492d      	ldr	r1, [pc, #180]	; (8007908 <tcp_close_shutdown_fin+0xcc>)
- 8007852:	482e      	ldr	r0, [pc, #184]	; (800790c <tcp_close_shutdown_fin+0xd0>)
- 8007854:	f009 f9b8 	bl	8010bc8 <iprintf>
-
-  switch (pcb->state) {
- 8007858:	687b      	ldr	r3, [r7, #4]
- 800785a:	7d1b      	ldrb	r3, [r3, #20]
- 800785c:	2b07      	cmp	r3, #7
- 800785e:	d020      	beq.n	80078a2 <tcp_close_shutdown_fin+0x66>
- 8007860:	2b07      	cmp	r3, #7
- 8007862:	dc2b      	bgt.n	80078bc <tcp_close_shutdown_fin+0x80>
- 8007864:	2b03      	cmp	r3, #3
- 8007866:	d002      	beq.n	800786e <tcp_close_shutdown_fin+0x32>
- 8007868:	2b04      	cmp	r3, #4
- 800786a:	d00d      	beq.n	8007888 <tcp_close_shutdown_fin+0x4c>
- 800786c:	e026      	b.n	80078bc <tcp_close_shutdown_fin+0x80>
-    case SYN_RCVD:
-      err = tcp_send_fin(pcb);
- 800786e:	6878      	ldr	r0, [r7, #4]
- 8007870:	f004 fd82 	bl	800c378 <tcp_send_fin>
- 8007874:	4603      	mov	r3, r0
- 8007876:	73fb      	strb	r3, [r7, #15]
-      if (err == ERR_OK) {
- 8007878:	f997 300f 	ldrsb.w	r3, [r7, #15]
- 800787c:	2b00      	cmp	r3, #0
- 800787e:	d11f      	bne.n	80078c0 <tcp_close_shutdown_fin+0x84>
-        tcp_backlog_accepted(pcb);
-        MIB2_STATS_INC(mib2.tcpattemptfails);
-        pcb->state = FIN_WAIT_1;
- 8007880:	687b      	ldr	r3, [r7, #4]
- 8007882:	2205      	movs	r2, #5
- 8007884:	751a      	strb	r2, [r3, #20]
-      }
-      break;
- 8007886:	e01b      	b.n	80078c0 <tcp_close_shutdown_fin+0x84>
-    case ESTABLISHED:
-      err = tcp_send_fin(pcb);
- 8007888:	6878      	ldr	r0, [r7, #4]
- 800788a:	f004 fd75 	bl	800c378 <tcp_send_fin>
- 800788e:	4603      	mov	r3, r0
- 8007890:	73fb      	strb	r3, [r7, #15]
-      if (err == ERR_OK) {
- 8007892:	f997 300f 	ldrsb.w	r3, [r7, #15]
- 8007896:	2b00      	cmp	r3, #0
- 8007898:	d114      	bne.n	80078c4 <tcp_close_shutdown_fin+0x88>
-        MIB2_STATS_INC(mib2.tcpestabresets);
-        pcb->state = FIN_WAIT_1;
- 800789a:	687b      	ldr	r3, [r7, #4]
- 800789c:	2205      	movs	r2, #5
- 800789e:	751a      	strb	r2, [r3, #20]
-      }
-      break;
- 80078a0:	e010      	b.n	80078c4 <tcp_close_shutdown_fin+0x88>
-    case CLOSE_WAIT:
-      err = tcp_send_fin(pcb);
- 80078a2:	6878      	ldr	r0, [r7, #4]
- 80078a4:	f004 fd68 	bl	800c378 <tcp_send_fin>
- 80078a8:	4603      	mov	r3, r0
- 80078aa:	73fb      	strb	r3, [r7, #15]
-      if (err == ERR_OK) {
- 80078ac:	f997 300f 	ldrsb.w	r3, [r7, #15]
- 80078b0:	2b00      	cmp	r3, #0
- 80078b2:	d109      	bne.n	80078c8 <tcp_close_shutdown_fin+0x8c>
-        MIB2_STATS_INC(mib2.tcpestabresets);
-        pcb->state = LAST_ACK;
- 80078b4:	687b      	ldr	r3, [r7, #4]
- 80078b6:	2209      	movs	r2, #9
- 80078b8:	751a      	strb	r2, [r3, #20]
-      }
-      break;
- 80078ba:	e005      	b.n	80078c8 <tcp_close_shutdown_fin+0x8c>
-    default:
-      /* Has already been closed, do nothing. */
-      return ERR_OK;
- 80078bc:	2300      	movs	r3, #0
- 80078be:	e01c      	b.n	80078fa <tcp_close_shutdown_fin+0xbe>
-      break;
- 80078c0:	bf00      	nop
- 80078c2:	e002      	b.n	80078ca <tcp_close_shutdown_fin+0x8e>
-      break;
- 80078c4:	bf00      	nop
- 80078c6:	e000      	b.n	80078ca <tcp_close_shutdown_fin+0x8e>
-      break;
- 80078c8:	bf00      	nop
-  }
-
-  if (err == ERR_OK) {
- 80078ca:	f997 300f 	ldrsb.w	r3, [r7, #15]
- 80078ce:	2b00      	cmp	r3, #0
- 80078d0:	d103      	bne.n	80078da <tcp_close_shutdown_fin+0x9e>
-    /* To ensure all data has been sent when tcp_close returns, we have
-       to make sure tcp_output doesn't fail.
-       Since we don't really have to ensure all data has been sent when tcp_close
-       returns (unsent data is sent from tcp timer functions, also), we don't care
-       for the return value of tcp_output for now. */
-    tcp_output(pcb);
- 80078d2:	6878      	ldr	r0, [r7, #4]
- 80078d4:	f004 fe8e 	bl	800c5f4 <tcp_output>
- 80078d8:	e00d      	b.n	80078f6 <tcp_close_shutdown_fin+0xba>
-  } else if (err == ERR_MEM) {
- 80078da:	f997 300f 	ldrsb.w	r3, [r7, #15]
- 80078de:	f1b3 3fff 	cmp.w	r3, #4294967295
- 80078e2:	d108      	bne.n	80078f6 <tcp_close_shutdown_fin+0xba>
-    /* Mark this pcb for closing. Closing is retried from tcp_tmr. */
-    tcp_set_flags(pcb, TF_CLOSEPEND);
- 80078e4:	687b      	ldr	r3, [r7, #4]
- 80078e6:	8b5b      	ldrh	r3, [r3, #26]
- 80078e8:	f043 0308 	orr.w	r3, r3, #8
- 80078ec:	b29a      	uxth	r2, r3
- 80078ee:	687b      	ldr	r3, [r7, #4]
- 80078f0:	835a      	strh	r2, [r3, #26]
-    /* We have to return ERR_OK from here to indicate to the callers that this
-       pcb should not be used any more as it will be freed soon via tcp_tmr.
-       This is OK here since sending FIN does not guarantee a time frime for
-       actually freeing the pcb, either (it is left in closure states for
-       remote ACK or timeout) */
-    return ERR_OK;
- 80078f2:	2300      	movs	r3, #0
- 80078f4:	e001      	b.n	80078fa <tcp_close_shutdown_fin+0xbe>
-  }
-  return err;
- 80078f6:	f997 300f 	ldrsb.w	r3, [r7, #15]
-}
- 80078fa:	4618      	mov	r0, r3
- 80078fc:	3710      	adds	r7, #16
- 80078fe:	46bd      	mov	sp, r7
- 8007900:	bd80      	pop	{r7, pc}
- 8007902:	bf00      	nop
- 8007904:	08012a08 	.word	0x08012a08
- 8007908:	08012ab8 	.word	0x08012ab8
- 800790c:	08012a4c 	.word	0x08012a4c
-
-08007910 <tcp_close>:
- * @return ERR_OK if connection has been closed
- *         another err_t if closing failed and pcb is not freed
- */
-err_t
-tcp_close(struct tcp_pcb *pcb)
-{
- 8007910:	b580      	push	{r7, lr}
- 8007912:	b082      	sub	sp, #8
- 8007914:	af00      	add	r7, sp, #0
- 8007916:	6078      	str	r0, [r7, #4]
-  LWIP_ASSERT_CORE_LOCKED();
-
-  LWIP_ERROR("tcp_close: invalid pcb", pcb != NULL, return ERR_ARG);
- 8007918:	687b      	ldr	r3, [r7, #4]
- 800791a:	2b00      	cmp	r3, #0
- 800791c:	d109      	bne.n	8007932 <tcp_close+0x22>
- 800791e:	4b0f      	ldr	r3, [pc, #60]	; (800795c <tcp_close+0x4c>)
- 8007920:	f44f 72f4 	mov.w	r2, #488	; 0x1e8
- 8007924:	490e      	ldr	r1, [pc, #56]	; (8007960 <tcp_close+0x50>)
- 8007926:	480f      	ldr	r0, [pc, #60]	; (8007964 <tcp_close+0x54>)
- 8007928:	f009 f94e 	bl	8010bc8 <iprintf>
- 800792c:	f06f 030f 	mvn.w	r3, #15
- 8007930:	e00f      	b.n	8007952 <tcp_close+0x42>
-  LWIP_DEBUGF(TCP_DEBUG, ("tcp_close: closing in "));
-
-  tcp_debug_print_state(pcb->state);
-
-  if (pcb->state != LISTEN) {
- 8007932:	687b      	ldr	r3, [r7, #4]
- 8007934:	7d1b      	ldrb	r3, [r3, #20]
- 8007936:	2b01      	cmp	r3, #1
- 8007938:	d006      	beq.n	8007948 <tcp_close+0x38>
-    /* Set a flag not to receive any more data... */
-    tcp_set_flags(pcb, TF_RXCLOSED);
- 800793a:	687b      	ldr	r3, [r7, #4]
- 800793c:	8b5b      	ldrh	r3, [r3, #26]
- 800793e:	f043 0310 	orr.w	r3, r3, #16
- 8007942:	b29a      	uxth	r2, r3
- 8007944:	687b      	ldr	r3, [r7, #4]
- 8007946:	835a      	strh	r2, [r3, #26]
-  }
-  /* ... and close */
-  return tcp_close_shutdown(pcb, 1);
- 8007948:	2101      	movs	r1, #1
- 800794a:	6878      	ldr	r0, [r7, #4]
- 800794c:	f7ff fe94 	bl	8007678 <tcp_close_shutdown>
- 8007950:	4603      	mov	r3, r0
-}
- 8007952:	4618      	mov	r0, r3
- 8007954:	3708      	adds	r7, #8
- 8007956:	46bd      	mov	sp, r7
- 8007958:	bd80      	pop	{r7, pc}
- 800795a:	bf00      	nop
- 800795c:	08012a08 	.word	0x08012a08
- 8007960:	08012b18 	.word	0x08012b18
- 8007964:	08012a4c 	.word	0x08012a4c
-
-08007968 <tcp_abandon>:
- * @param pcb the tcp_pcb to abort
- * @param reset boolean to indicate whether a reset should be sent
- */
-void
-tcp_abandon(struct tcp_pcb *pcb, int reset)
-{
- 8007968:	b580      	push	{r7, lr}
- 800796a:	b08e      	sub	sp, #56	; 0x38
- 800796c:	af04      	add	r7, sp, #16
- 800796e:	6078      	str	r0, [r7, #4]
- 8007970:	6039      	str	r1, [r7, #0]
-#endif /* LWIP_CALLBACK_API */
-  void *errf_arg;
-
-  LWIP_ASSERT_CORE_LOCKED();
-
-  LWIP_ERROR("tcp_abandon: invalid pcb", pcb != NULL, return);
- 8007972:	687b      	ldr	r3, [r7, #4]
- 8007974:	2b00      	cmp	r3, #0
- 8007976:	d107      	bne.n	8007988 <tcp_abandon+0x20>
- 8007978:	4b52      	ldr	r3, [pc, #328]	; (8007ac4 <tcp_abandon+0x15c>)
- 800797a:	f240 223d 	movw	r2, #573	; 0x23d
- 800797e:	4952      	ldr	r1, [pc, #328]	; (8007ac8 <tcp_abandon+0x160>)
- 8007980:	4852      	ldr	r0, [pc, #328]	; (8007acc <tcp_abandon+0x164>)
- 8007982:	f009 f921 	bl	8010bc8 <iprintf>
- 8007986:	e099      	b.n	8007abc <tcp_abandon+0x154>
-
-  /* pcb->state LISTEN not allowed here */
-  LWIP_ASSERT("don't call tcp_abort/tcp_abandon for listen-pcbs",
- 8007988:	687b      	ldr	r3, [r7, #4]
- 800798a:	7d1b      	ldrb	r3, [r3, #20]
- 800798c:	2b01      	cmp	r3, #1
- 800798e:	d106      	bne.n	800799e <tcp_abandon+0x36>
- 8007990:	4b4c      	ldr	r3, [pc, #304]	; (8007ac4 <tcp_abandon+0x15c>)
- 8007992:	f44f 7210 	mov.w	r2, #576	; 0x240
- 8007996:	494e      	ldr	r1, [pc, #312]	; (8007ad0 <tcp_abandon+0x168>)
- 8007998:	484c      	ldr	r0, [pc, #304]	; (8007acc <tcp_abandon+0x164>)
- 800799a:	f009 f915 	bl	8010bc8 <iprintf>
-              pcb->state != LISTEN);
-  /* Figure out on which TCP PCB list we are, and remove us. If we
-     are in an active state, call the receive function associated with
-     the PCB with a NULL argument, and send an RST to the remote end. */
-  if (pcb->state == TIME_WAIT) {
- 800799e:	687b      	ldr	r3, [r7, #4]
- 80079a0:	7d1b      	ldrb	r3, [r3, #20]
- 80079a2:	2b0a      	cmp	r3, #10
- 80079a4:	d107      	bne.n	80079b6 <tcp_abandon+0x4e>
-    tcp_pcb_remove(&tcp_tw_pcbs, pcb);
- 80079a6:	6879      	ldr	r1, [r7, #4]
- 80079a8:	484a      	ldr	r0, [pc, #296]	; (8007ad4 <tcp_abandon+0x16c>)
- 80079aa:	f001 f9a1 	bl	8008cf0 <tcp_pcb_remove>
-    tcp_free(pcb);
- 80079ae:	6878      	ldr	r0, [r7, #4]
- 80079b0:	f7ff fdb0 	bl	8007514 <tcp_free>
- 80079b4:	e082      	b.n	8007abc <tcp_abandon+0x154>
-  } else {
-    int send_rst = 0;
- 80079b6:	2300      	movs	r3, #0
- 80079b8:	627b      	str	r3, [r7, #36]	; 0x24
-    u16_t local_port = 0;
- 80079ba:	2300      	movs	r3, #0
- 80079bc:	847b      	strh	r3, [r7, #34]	; 0x22
-    enum tcp_state last_state;
-    seqno = pcb->snd_nxt;
- 80079be:	687b      	ldr	r3, [r7, #4]
- 80079c0:	6d1b      	ldr	r3, [r3, #80]	; 0x50
- 80079c2:	61bb      	str	r3, [r7, #24]
-    ackno = pcb->rcv_nxt;
- 80079c4:	687b      	ldr	r3, [r7, #4]
- 80079c6:	6a5b      	ldr	r3, [r3, #36]	; 0x24
- 80079c8:	617b      	str	r3, [r7, #20]
-#if LWIP_CALLBACK_API
-    errf = pcb->errf;
- 80079ca:	687b      	ldr	r3, [r7, #4]
- 80079cc:	f8d3 3090 	ldr.w	r3, [r3, #144]	; 0x90
- 80079d0:	613b      	str	r3, [r7, #16]
-#endif /* LWIP_CALLBACK_API */
-    errf_arg = pcb->callback_arg;
- 80079d2:	687b      	ldr	r3, [r7, #4]
- 80079d4:	691b      	ldr	r3, [r3, #16]
- 80079d6:	60fb      	str	r3, [r7, #12]
-    if (pcb->state == CLOSED) {
- 80079d8:	687b      	ldr	r3, [r7, #4]
- 80079da:	7d1b      	ldrb	r3, [r3, #20]
- 80079dc:	2b00      	cmp	r3, #0
- 80079de:	d126      	bne.n	8007a2e <tcp_abandon+0xc6>
-      if (pcb->local_port != 0) {
- 80079e0:	687b      	ldr	r3, [r7, #4]
- 80079e2:	8adb      	ldrh	r3, [r3, #22]
- 80079e4:	2b00      	cmp	r3, #0
- 80079e6:	d02e      	beq.n	8007a46 <tcp_abandon+0xde>
-        /* bound, not yet opened */
-        TCP_RMV(&tcp_bound_pcbs, pcb);
- 80079e8:	4b3b      	ldr	r3, [pc, #236]	; (8007ad8 <tcp_abandon+0x170>)
- 80079ea:	681b      	ldr	r3, [r3, #0]
- 80079ec:	687a      	ldr	r2, [r7, #4]
- 80079ee:	429a      	cmp	r2, r3
- 80079f0:	d105      	bne.n	80079fe <tcp_abandon+0x96>
- 80079f2:	4b39      	ldr	r3, [pc, #228]	; (8007ad8 <tcp_abandon+0x170>)
- 80079f4:	681b      	ldr	r3, [r3, #0]
- 80079f6:	68db      	ldr	r3, [r3, #12]
- 80079f8:	4a37      	ldr	r2, [pc, #220]	; (8007ad8 <tcp_abandon+0x170>)
- 80079fa:	6013      	str	r3, [r2, #0]
- 80079fc:	e013      	b.n	8007a26 <tcp_abandon+0xbe>
- 80079fe:	4b36      	ldr	r3, [pc, #216]	; (8007ad8 <tcp_abandon+0x170>)
- 8007a00:	681b      	ldr	r3, [r3, #0]
- 8007a02:	61fb      	str	r3, [r7, #28]
- 8007a04:	e00c      	b.n	8007a20 <tcp_abandon+0xb8>
- 8007a06:	69fb      	ldr	r3, [r7, #28]
- 8007a08:	68db      	ldr	r3, [r3, #12]
- 8007a0a:	687a      	ldr	r2, [r7, #4]
- 8007a0c:	429a      	cmp	r2, r3
- 8007a0e:	d104      	bne.n	8007a1a <tcp_abandon+0xb2>
- 8007a10:	687b      	ldr	r3, [r7, #4]
- 8007a12:	68da      	ldr	r2, [r3, #12]
- 8007a14:	69fb      	ldr	r3, [r7, #28]
- 8007a16:	60da      	str	r2, [r3, #12]
- 8007a18:	e005      	b.n	8007a26 <tcp_abandon+0xbe>
- 8007a1a:	69fb      	ldr	r3, [r7, #28]
- 8007a1c:	68db      	ldr	r3, [r3, #12]
- 8007a1e:	61fb      	str	r3, [r7, #28]
- 8007a20:	69fb      	ldr	r3, [r7, #28]
- 8007a22:	2b00      	cmp	r3, #0
- 8007a24:	d1ef      	bne.n	8007a06 <tcp_abandon+0x9e>
- 8007a26:	687b      	ldr	r3, [r7, #4]
- 8007a28:	2200      	movs	r2, #0
- 8007a2a:	60da      	str	r2, [r3, #12]
- 8007a2c:	e00b      	b.n	8007a46 <tcp_abandon+0xde>
-      }
-    } else {
-      send_rst = reset;
- 8007a2e:	683b      	ldr	r3, [r7, #0]
- 8007a30:	627b      	str	r3, [r7, #36]	; 0x24
-      local_port = pcb->local_port;
- 8007a32:	687b      	ldr	r3, [r7, #4]
- 8007a34:	8adb      	ldrh	r3, [r3, #22]
- 8007a36:	847b      	strh	r3, [r7, #34]	; 0x22
-      TCP_PCB_REMOVE_ACTIVE(pcb);
- 8007a38:	6879      	ldr	r1, [r7, #4]
- 8007a3a:	4828      	ldr	r0, [pc, #160]	; (8007adc <tcp_abandon+0x174>)
- 8007a3c:	f001 f958 	bl	8008cf0 <tcp_pcb_remove>
- 8007a40:	4b27      	ldr	r3, [pc, #156]	; (8007ae0 <tcp_abandon+0x178>)
- 8007a42:	2201      	movs	r2, #1
- 8007a44:	701a      	strb	r2, [r3, #0]
-    }
-    if (pcb->unacked != NULL) {
- 8007a46:	687b      	ldr	r3, [r7, #4]
- 8007a48:	6f1b      	ldr	r3, [r3, #112]	; 0x70
- 8007a4a:	2b00      	cmp	r3, #0
- 8007a4c:	d004      	beq.n	8007a58 <tcp_abandon+0xf0>
-      tcp_segs_free(pcb->unacked);
- 8007a4e:	687b      	ldr	r3, [r7, #4]
- 8007a50:	6f1b      	ldr	r3, [r3, #112]	; 0x70
- 8007a52:	4618      	mov	r0, r3
- 8007a54:	f000 fe7a 	bl	800874c <tcp_segs_free>
-    }
-    if (pcb->unsent != NULL) {
- 8007a58:	687b      	ldr	r3, [r7, #4]
- 8007a5a:	6edb      	ldr	r3, [r3, #108]	; 0x6c
- 8007a5c:	2b00      	cmp	r3, #0
- 8007a5e:	d004      	beq.n	8007a6a <tcp_abandon+0x102>
-      tcp_segs_free(pcb->unsent);
- 8007a60:	687b      	ldr	r3, [r7, #4]
- 8007a62:	6edb      	ldr	r3, [r3, #108]	; 0x6c
- 8007a64:	4618      	mov	r0, r3
- 8007a66:	f000 fe71 	bl	800874c <tcp_segs_free>
-    }
-#if TCP_QUEUE_OOSEQ
-    if (pcb->ooseq != NULL) {
- 8007a6a:	687b      	ldr	r3, [r7, #4]
- 8007a6c:	6f5b      	ldr	r3, [r3, #116]	; 0x74
- 8007a6e:	2b00      	cmp	r3, #0
- 8007a70:	d004      	beq.n	8007a7c <tcp_abandon+0x114>
-      tcp_segs_free(pcb->ooseq);
- 8007a72:	687b      	ldr	r3, [r7, #4]
- 8007a74:	6f5b      	ldr	r3, [r3, #116]	; 0x74
- 8007a76:	4618      	mov	r0, r3
- 8007a78:	f000 fe68 	bl	800874c <tcp_segs_free>
-    }
-#endif /* TCP_QUEUE_OOSEQ */
-    tcp_backlog_accepted(pcb);
-    if (send_rst) {
- 8007a7c:	6a7b      	ldr	r3, [r7, #36]	; 0x24
- 8007a7e:	2b00      	cmp	r3, #0
- 8007a80:	d00e      	beq.n	8007aa0 <tcp_abandon+0x138>
-      LWIP_DEBUGF(TCP_RST_DEBUG, ("tcp_abandon: sending RST\n"));
-      tcp_rst(pcb, seqno, ackno, &pcb->local_ip, &pcb->remote_ip, local_port, pcb->remote_port);
- 8007a82:	6879      	ldr	r1, [r7, #4]
- 8007a84:	687b      	ldr	r3, [r7, #4]
- 8007a86:	3304      	adds	r3, #4
- 8007a88:	687a      	ldr	r2, [r7, #4]
- 8007a8a:	8b12      	ldrh	r2, [r2, #24]
- 8007a8c:	9202      	str	r2, [sp, #8]
- 8007a8e:	8c7a      	ldrh	r2, [r7, #34]	; 0x22
- 8007a90:	9201      	str	r2, [sp, #4]
- 8007a92:	9300      	str	r3, [sp, #0]
- 8007a94:	460b      	mov	r3, r1
- 8007a96:	697a      	ldr	r2, [r7, #20]
- 8007a98:	69b9      	ldr	r1, [r7, #24]
- 8007a9a:	6878      	ldr	r0, [r7, #4]
- 8007a9c:	f005 fb6a 	bl	800d174 <tcp_rst>
-    }
-    last_state = pcb->state;
- 8007aa0:	687b      	ldr	r3, [r7, #4]
- 8007aa2:	7d1b      	ldrb	r3, [r3, #20]
- 8007aa4:	72fb      	strb	r3, [r7, #11]
-    tcp_free(pcb);
- 8007aa6:	6878      	ldr	r0, [r7, #4]
- 8007aa8:	f7ff fd34 	bl	8007514 <tcp_free>
-    TCP_EVENT_ERR(last_state, errf, errf_arg, ERR_ABRT);
- 8007aac:	693b      	ldr	r3, [r7, #16]
- 8007aae:	2b00      	cmp	r3, #0
- 8007ab0:	d004      	beq.n	8007abc <tcp_abandon+0x154>
- 8007ab2:	693b      	ldr	r3, [r7, #16]
- 8007ab4:	f06f 010c 	mvn.w	r1, #12
- 8007ab8:	68f8      	ldr	r0, [r7, #12]
- 8007aba:	4798      	blx	r3
-  }
-}
- 8007abc:	3728      	adds	r7, #40	; 0x28
- 8007abe:	46bd      	mov	sp, r7
- 8007ac0:	bd80      	pop	{r7, pc}
- 8007ac2:	bf00      	nop
- 8007ac4:	08012a08 	.word	0x08012a08
- 8007ac8:	08012b4c 	.word	0x08012b4c
- 8007acc:	08012a4c 	.word	0x08012a4c
- 8007ad0:	08012b68 	.word	0x08012b68
- 8007ad4:	24007b7c 	.word	0x24007b7c
- 8007ad8:	24007b70 	.word	0x24007b70
- 8007adc:	24007b78 	.word	0x24007b78
- 8007ae0:	24007b80 	.word	0x24007b80
-
-08007ae4 <tcp_abort>:
- *
- * @param pcb the tcp pcb to abort
- */
-void
-tcp_abort(struct tcp_pcb *pcb)
-{
- 8007ae4:	b580      	push	{r7, lr}
- 8007ae6:	b082      	sub	sp, #8
- 8007ae8:	af00      	add	r7, sp, #0
- 8007aea:	6078      	str	r0, [r7, #4]
-  tcp_abandon(pcb, 1);
- 8007aec:	2101      	movs	r1, #1
- 8007aee:	6878      	ldr	r0, [r7, #4]
- 8007af0:	f7ff ff3a 	bl	8007968 <tcp_abandon>
-}
- 8007af4:	bf00      	nop
- 8007af6:	3708      	adds	r7, #8
- 8007af8:	46bd      	mov	sp, r7
- 8007afa:	bd80      	pop	{r7, pc}
-
-08007afc <tcp_update_rcv_ann_wnd>:
- * Returns how much extra window would be advertised if we sent an
- * update now.
- */
-u32_t
-tcp_update_rcv_ann_wnd(struct tcp_pcb *pcb)
-{
- 8007afc:	b580      	push	{r7, lr}
- 8007afe:	b084      	sub	sp, #16
- 8007b00:	af00      	add	r7, sp, #0
- 8007b02:	6078      	str	r0, [r7, #4]
-  u32_t new_right_edge;
-
-  LWIP_ASSERT("tcp_update_rcv_ann_wnd: invalid pcb", pcb != NULL);
- 8007b04:	687b      	ldr	r3, [r7, #4]
- 8007b06:	2b00      	cmp	r3, #0
- 8007b08:	d106      	bne.n	8007b18 <tcp_update_rcv_ann_wnd+0x1c>
- 8007b0a:	4b25      	ldr	r3, [pc, #148]	; (8007ba0 <tcp_update_rcv_ann_wnd+0xa4>)
- 8007b0c:	f240 32a6 	movw	r2, #934	; 0x3a6
- 8007b10:	4924      	ldr	r1, [pc, #144]	; (8007ba4 <tcp_update_rcv_ann_wnd+0xa8>)
- 8007b12:	4825      	ldr	r0, [pc, #148]	; (8007ba8 <tcp_update_rcv_ann_wnd+0xac>)
- 8007b14:	f009 f858 	bl	8010bc8 <iprintf>
-  new_right_edge = pcb->rcv_nxt + pcb->rcv_wnd;
- 8007b18:	687b      	ldr	r3, [r7, #4]
- 8007b1a:	6a5b      	ldr	r3, [r3, #36]	; 0x24
- 8007b1c:	687a      	ldr	r2, [r7, #4]
- 8007b1e:	8d12      	ldrh	r2, [r2, #40]	; 0x28
- 8007b20:	4413      	add	r3, r2
- 8007b22:	60fb      	str	r3, [r7, #12]
-
-  if (TCP_SEQ_GEQ(new_right_edge, pcb->rcv_ann_right_edge + LWIP_MIN((TCP_WND / 2), pcb->mss))) {
- 8007b24:	687b      	ldr	r3, [r7, #4]
- 8007b26:	6adb      	ldr	r3, [r3, #44]	; 0x2c
- 8007b28:	687a      	ldr	r2, [r7, #4]
- 8007b2a:	8e52      	ldrh	r2, [r2, #50]	; 0x32
- 8007b2c:	f5b2 6f86 	cmp.w	r2, #1072	; 0x430
- 8007b30:	bf28      	it	cs
- 8007b32:	f44f 6286 	movcs.w	r2, #1072	; 0x430
- 8007b36:	b292      	uxth	r2, r2
- 8007b38:	4413      	add	r3, r2
- 8007b3a:	68fa      	ldr	r2, [r7, #12]
- 8007b3c:	1ad3      	subs	r3, r2, r3
- 8007b3e:	2b00      	cmp	r3, #0
- 8007b40:	db08      	blt.n	8007b54 <tcp_update_rcv_ann_wnd+0x58>
-    /* we can advertise more window */
-    pcb->rcv_ann_wnd = pcb->rcv_wnd;
- 8007b42:	687b      	ldr	r3, [r7, #4]
- 8007b44:	8d1a      	ldrh	r2, [r3, #40]	; 0x28
- 8007b46:	687b      	ldr	r3, [r7, #4]
- 8007b48:	855a      	strh	r2, [r3, #42]	; 0x2a
-    return new_right_edge - pcb->rcv_ann_right_edge;
- 8007b4a:	687b      	ldr	r3, [r7, #4]
- 8007b4c:	6adb      	ldr	r3, [r3, #44]	; 0x2c
- 8007b4e:	68fa      	ldr	r2, [r7, #12]
- 8007b50:	1ad3      	subs	r3, r2, r3
- 8007b52:	e020      	b.n	8007b96 <tcp_update_rcv_ann_wnd+0x9a>
-  } else {
-    if (TCP_SEQ_GT(pcb->rcv_nxt, pcb->rcv_ann_right_edge)) {
- 8007b54:	687b      	ldr	r3, [r7, #4]
- 8007b56:	6a5a      	ldr	r2, [r3, #36]	; 0x24
- 8007b58:	687b      	ldr	r3, [r7, #4]
- 8007b5a:	6adb      	ldr	r3, [r3, #44]	; 0x2c
- 8007b5c:	1ad3      	subs	r3, r2, r3
- 8007b5e:	2b00      	cmp	r3, #0
- 8007b60:	dd03      	ble.n	8007b6a <tcp_update_rcv_ann_wnd+0x6e>
-      /* Can happen due to other end sending out of advertised window,
-       * but within actual available (but not yet advertised) window */
-      pcb->rcv_ann_wnd = 0;
- 8007b62:	687b      	ldr	r3, [r7, #4]
- 8007b64:	2200      	movs	r2, #0
- 8007b66:	855a      	strh	r2, [r3, #42]	; 0x2a
- 8007b68:	e014      	b.n	8007b94 <tcp_update_rcv_ann_wnd+0x98>
-    } else {
-      /* keep the right edge of window constant */
-      u32_t new_rcv_ann_wnd = pcb->rcv_ann_right_edge - pcb->rcv_nxt;
- 8007b6a:	687b      	ldr	r3, [r7, #4]
- 8007b6c:	6ada      	ldr	r2, [r3, #44]	; 0x2c
- 8007b6e:	687b      	ldr	r3, [r7, #4]
- 8007b70:	6a5b      	ldr	r3, [r3, #36]	; 0x24
- 8007b72:	1ad3      	subs	r3, r2, r3
- 8007b74:	60bb      	str	r3, [r7, #8]
-#if !LWIP_WND_SCALE
-      LWIP_ASSERT("new_rcv_ann_wnd <= 0xffff", new_rcv_ann_wnd <= 0xffff);
- 8007b76:	68bb      	ldr	r3, [r7, #8]
- 8007b78:	f5b3 3f80 	cmp.w	r3, #65536	; 0x10000
- 8007b7c:	d306      	bcc.n	8007b8c <tcp_update_rcv_ann_wnd+0x90>
- 8007b7e:	4b08      	ldr	r3, [pc, #32]	; (8007ba0 <tcp_update_rcv_ann_wnd+0xa4>)
- 8007b80:	f240 32b6 	movw	r2, #950	; 0x3b6
- 8007b84:	4909      	ldr	r1, [pc, #36]	; (8007bac <tcp_update_rcv_ann_wnd+0xb0>)
- 8007b86:	4808      	ldr	r0, [pc, #32]	; (8007ba8 <tcp_update_rcv_ann_wnd+0xac>)
- 8007b88:	f009 f81e 	bl	8010bc8 <iprintf>
-#endif
-      pcb->rcv_ann_wnd = (tcpwnd_size_t)new_rcv_ann_wnd;
- 8007b8c:	68bb      	ldr	r3, [r7, #8]
- 8007b8e:	b29a      	uxth	r2, r3
- 8007b90:	687b      	ldr	r3, [r7, #4]
- 8007b92:	855a      	strh	r2, [r3, #42]	; 0x2a
-    }
-    return 0;
- 8007b94:	2300      	movs	r3, #0
-  }
-}
- 8007b96:	4618      	mov	r0, r3
- 8007b98:	3710      	adds	r7, #16
- 8007b9a:	46bd      	mov	sp, r7
- 8007b9c:	bd80      	pop	{r7, pc}
- 8007b9e:	bf00      	nop
- 8007ba0:	08012a08 	.word	0x08012a08
- 8007ba4:	08012c64 	.word	0x08012c64
- 8007ba8:	08012a4c 	.word	0x08012a4c
- 8007bac:	08012c88 	.word	0x08012c88
-
-08007bb0 <tcp_recved>:
- * @param pcb the tcp_pcb for which data is read
- * @param len the amount of bytes that have been read by the application
- */
-void
-tcp_recved(struct tcp_pcb *pcb, u16_t len)
-{
- 8007bb0:	b580      	push	{r7, lr}
- 8007bb2:	b084      	sub	sp, #16
- 8007bb4:	af00      	add	r7, sp, #0
- 8007bb6:	6078      	str	r0, [r7, #4]
- 8007bb8:	460b      	mov	r3, r1
- 8007bba:	807b      	strh	r3, [r7, #2]
-  u32_t wnd_inflation;
-  tcpwnd_size_t rcv_wnd;
-
-  LWIP_ASSERT_CORE_LOCKED();
-
-  LWIP_ERROR("tcp_recved: invalid pcb", pcb != NULL, return);
- 8007bbc:	687b      	ldr	r3, [r7, #4]
- 8007bbe:	2b00      	cmp	r3, #0
- 8007bc0:	d107      	bne.n	8007bd2 <tcp_recved+0x22>
- 8007bc2:	4b1f      	ldr	r3, [pc, #124]	; (8007c40 <tcp_recved+0x90>)
- 8007bc4:	f240 32cf 	movw	r2, #975	; 0x3cf
- 8007bc8:	491e      	ldr	r1, [pc, #120]	; (8007c44 <tcp_recved+0x94>)
- 8007bca:	481f      	ldr	r0, [pc, #124]	; (8007c48 <tcp_recved+0x98>)
- 8007bcc:	f008 fffc 	bl	8010bc8 <iprintf>
- 8007bd0:	e032      	b.n	8007c38 <tcp_recved+0x88>
-
-  /* pcb->state LISTEN not allowed here */
-  LWIP_ASSERT("don't call tcp_recved for listen-pcbs",
- 8007bd2:	687b      	ldr	r3, [r7, #4]
- 8007bd4:	7d1b      	ldrb	r3, [r3, #20]
- 8007bd6:	2b01      	cmp	r3, #1
- 8007bd8:	d106      	bne.n	8007be8 <tcp_recved+0x38>
- 8007bda:	4b19      	ldr	r3, [pc, #100]	; (8007c40 <tcp_recved+0x90>)
- 8007bdc:	f240 32d2 	movw	r2, #978	; 0x3d2
- 8007be0:	491a      	ldr	r1, [pc, #104]	; (8007c4c <tcp_recved+0x9c>)
- 8007be2:	4819      	ldr	r0, [pc, #100]	; (8007c48 <tcp_recved+0x98>)
- 8007be4:	f008 fff0 	bl	8010bc8 <iprintf>
-              pcb->state != LISTEN);
-
-  rcv_wnd = (tcpwnd_size_t)(pcb->rcv_wnd + len);
- 8007be8:	687b      	ldr	r3, [r7, #4]
- 8007bea:	8d1a      	ldrh	r2, [r3, #40]	; 0x28
- 8007bec:	887b      	ldrh	r3, [r7, #2]
- 8007bee:	4413      	add	r3, r2
- 8007bf0:	81fb      	strh	r3, [r7, #14]
-  if ((rcv_wnd > TCP_WND_MAX(pcb)) || (rcv_wnd < pcb->rcv_wnd)) {
- 8007bf2:	89fb      	ldrh	r3, [r7, #14]
- 8007bf4:	f5b3 6f06 	cmp.w	r3, #2144	; 0x860
- 8007bf8:	d804      	bhi.n	8007c04 <tcp_recved+0x54>
- 8007bfa:	687b      	ldr	r3, [r7, #4]
- 8007bfc:	8d1b      	ldrh	r3, [r3, #40]	; 0x28
- 8007bfe:	89fa      	ldrh	r2, [r7, #14]
- 8007c00:	429a      	cmp	r2, r3
- 8007c02:	d204      	bcs.n	8007c0e <tcp_recved+0x5e>
-    /* window got too big or tcpwnd_size_t overflow */
-    LWIP_DEBUGF(TCP_DEBUG, ("tcp_recved: window got too big or tcpwnd_size_t overflow\n"));
-    pcb->rcv_wnd = TCP_WND_MAX(pcb);
- 8007c04:	687b      	ldr	r3, [r7, #4]
- 8007c06:	f44f 6206 	mov.w	r2, #2144	; 0x860
- 8007c0a:	851a      	strh	r2, [r3, #40]	; 0x28
- 8007c0c:	e002      	b.n	8007c14 <tcp_recved+0x64>
-  } else  {
-    pcb->rcv_wnd = rcv_wnd;
- 8007c0e:	687b      	ldr	r3, [r7, #4]
- 8007c10:	89fa      	ldrh	r2, [r7, #14]
- 8007c12:	851a      	strh	r2, [r3, #40]	; 0x28
-  }
-
-  wnd_inflation = tcp_update_rcv_ann_wnd(pcb);
- 8007c14:	6878      	ldr	r0, [r7, #4]
- 8007c16:	f7ff ff71 	bl	8007afc <tcp_update_rcv_ann_wnd>
- 8007c1a:	60b8      	str	r0, [r7, #8]
-
-  /* If the change in the right edge of window is significant (default
-   * watermark is TCP_WND/4), then send an explicit update now.
-   * Otherwise wait for a packet to be sent in the normal course of
-   * events (or more window to be available later) */
-  if (wnd_inflation >= TCP_WND_UPDATE_THRESHOLD) {
- 8007c1c:	68bb      	ldr	r3, [r7, #8]
- 8007c1e:	f5b3 7f06 	cmp.w	r3, #536	; 0x218
- 8007c22:	d309      	bcc.n	8007c38 <tcp_recved+0x88>
-    tcp_ack_now(pcb);
- 8007c24:	687b      	ldr	r3, [r7, #4]
- 8007c26:	8b5b      	ldrh	r3, [r3, #26]
- 8007c28:	f043 0302 	orr.w	r3, r3, #2
- 8007c2c:	b29a      	uxth	r2, r3
- 8007c2e:	687b      	ldr	r3, [r7, #4]
- 8007c30:	835a      	strh	r2, [r3, #26]
-    tcp_output(pcb);
- 8007c32:	6878      	ldr	r0, [r7, #4]
- 8007c34:	f004 fcde 	bl	800c5f4 <tcp_output>
-  }
-
-  LWIP_DEBUGF(TCP_DEBUG, ("tcp_recved: received %"U16_F" bytes, wnd %"TCPWNDSIZE_F" (%"TCPWNDSIZE_F").\n",
-                          len, pcb->rcv_wnd, (u16_t)(TCP_WND_MAX(pcb) - pcb->rcv_wnd)));
-}
- 8007c38:	3710      	adds	r7, #16
- 8007c3a:	46bd      	mov	sp, r7
- 8007c3c:	bd80      	pop	{r7, pc}
- 8007c3e:	bf00      	nop
- 8007c40:	08012a08 	.word	0x08012a08
- 8007c44:	08012ca4 	.word	0x08012ca4
- 8007c48:	08012a4c 	.word	0x08012a4c
- 8007c4c:	08012cbc 	.word	0x08012cbc
-
-08007c50 <tcp_new_port>:
- *
- * @return a new (free) local TCP port number
- */
-static u16_t
-tcp_new_port(void)
-{
- 8007c50:	b480      	push	{r7}
- 8007c52:	b083      	sub	sp, #12
- 8007c54:	af00      	add	r7, sp, #0
-  u8_t i;
-  u16_t n = 0;
- 8007c56:	2300      	movs	r3, #0
- 8007c58:	80bb      	strh	r3, [r7, #4]
-  struct tcp_pcb *pcb;
-
-again:
-  tcp_port++;
- 8007c5a:	4b1e      	ldr	r3, [pc, #120]	; (8007cd4 <tcp_new_port+0x84>)
- 8007c5c:	881b      	ldrh	r3, [r3, #0]
- 8007c5e:	3301      	adds	r3, #1
- 8007c60:	b29a      	uxth	r2, r3
- 8007c62:	4b1c      	ldr	r3, [pc, #112]	; (8007cd4 <tcp_new_port+0x84>)
- 8007c64:	801a      	strh	r2, [r3, #0]
-  if (tcp_port == TCP_LOCAL_PORT_RANGE_END) {
- 8007c66:	4b1b      	ldr	r3, [pc, #108]	; (8007cd4 <tcp_new_port+0x84>)
- 8007c68:	881b      	ldrh	r3, [r3, #0]
- 8007c6a:	f64f 72ff 	movw	r2, #65535	; 0xffff
- 8007c6e:	4293      	cmp	r3, r2
- 8007c70:	d103      	bne.n	8007c7a <tcp_new_port+0x2a>
-    tcp_port = TCP_LOCAL_PORT_RANGE_START;
- 8007c72:	4b18      	ldr	r3, [pc, #96]	; (8007cd4 <tcp_new_port+0x84>)
- 8007c74:	f44f 4240 	mov.w	r2, #49152	; 0xc000
- 8007c78:	801a      	strh	r2, [r3, #0]
-  }
-  /* Check all PCB lists. */
-  for (i = 0; i < NUM_TCP_PCB_LISTS; i++) {
- 8007c7a:	2300      	movs	r3, #0
- 8007c7c:	71fb      	strb	r3, [r7, #7]
- 8007c7e:	e01e      	b.n	8007cbe <tcp_new_port+0x6e>
-    for (pcb = *tcp_pcb_lists[i]; pcb != NULL; pcb = pcb->next) {
- 8007c80:	79fb      	ldrb	r3, [r7, #7]
- 8007c82:	4a15      	ldr	r2, [pc, #84]	; (8007cd8 <tcp_new_port+0x88>)
- 8007c84:	f852 3023 	ldr.w	r3, [r2, r3, lsl #2]
- 8007c88:	681b      	ldr	r3, [r3, #0]
- 8007c8a:	603b      	str	r3, [r7, #0]
- 8007c8c:	e011      	b.n	8007cb2 <tcp_new_port+0x62>
-      if (pcb->local_port == tcp_port) {
- 8007c8e:	683b      	ldr	r3, [r7, #0]
- 8007c90:	8ada      	ldrh	r2, [r3, #22]
- 8007c92:	4b10      	ldr	r3, [pc, #64]	; (8007cd4 <tcp_new_port+0x84>)
- 8007c94:	881b      	ldrh	r3, [r3, #0]
- 8007c96:	429a      	cmp	r2, r3
- 8007c98:	d108      	bne.n	8007cac <tcp_new_port+0x5c>
-        n++;
- 8007c9a:	88bb      	ldrh	r3, [r7, #4]
- 8007c9c:	3301      	adds	r3, #1
- 8007c9e:	80bb      	strh	r3, [r7, #4]
-        if (n > (TCP_LOCAL_PORT_RANGE_END - TCP_LOCAL_PORT_RANGE_START)) {
- 8007ca0:	88bb      	ldrh	r3, [r7, #4]
- 8007ca2:	f5b3 4f80 	cmp.w	r3, #16384	; 0x4000
- 8007ca6:	d3d8      	bcc.n	8007c5a <tcp_new_port+0xa>
-          return 0;
- 8007ca8:	2300      	movs	r3, #0
- 8007caa:	e00d      	b.n	8007cc8 <tcp_new_port+0x78>
-    for (pcb = *tcp_pcb_lists[i]; pcb != NULL; pcb = pcb->next) {
- 8007cac:	683b      	ldr	r3, [r7, #0]
- 8007cae:	68db      	ldr	r3, [r3, #12]
- 8007cb0:	603b      	str	r3, [r7, #0]
- 8007cb2:	683b      	ldr	r3, [r7, #0]
- 8007cb4:	2b00      	cmp	r3, #0
- 8007cb6:	d1ea      	bne.n	8007c8e <tcp_new_port+0x3e>
-  for (i = 0; i < NUM_TCP_PCB_LISTS; i++) {
- 8007cb8:	79fb      	ldrb	r3, [r7, #7]
- 8007cba:	3301      	adds	r3, #1
- 8007cbc:	71fb      	strb	r3, [r7, #7]
- 8007cbe:	79fb      	ldrb	r3, [r7, #7]
- 8007cc0:	2b03      	cmp	r3, #3
- 8007cc2:	d9dd      	bls.n	8007c80 <tcp_new_port+0x30>
-        }
-        goto again;
-      }
-    }
-  }
-  return tcp_port;
- 8007cc4:	4b03      	ldr	r3, [pc, #12]	; (8007cd4 <tcp_new_port+0x84>)
- 8007cc6:	881b      	ldrh	r3, [r3, #0]
-}
- 8007cc8:	4618      	mov	r0, r3
- 8007cca:	370c      	adds	r7, #12
- 8007ccc:	46bd      	mov	sp, r7
- 8007cce:	f85d 7b04 	ldr.w	r7, [sp], #4
- 8007cd2:	4770      	bx	lr
- 8007cd4:	24000068 	.word	0x24000068
- 8007cd8:	08014d6c 	.word	0x08014d6c
-
-08007cdc <tcp_connect>:
- *         other err_t values if connect request couldn't be sent
- */
-err_t
-tcp_connect(struct tcp_pcb *pcb, const ip_addr_t *ipaddr, u16_t port,
-            tcp_connected_fn connected)
-{
- 8007cdc:	b580      	push	{r7, lr}
- 8007cde:	b08a      	sub	sp, #40	; 0x28
- 8007ce0:	af00      	add	r7, sp, #0
- 8007ce2:	60f8      	str	r0, [r7, #12]
- 8007ce4:	60b9      	str	r1, [r7, #8]
- 8007ce6:	603b      	str	r3, [r7, #0]
- 8007ce8:	4613      	mov	r3, r2
- 8007cea:	80fb      	strh	r3, [r7, #6]
-  struct netif *netif = NULL;
- 8007cec:	2300      	movs	r3, #0
- 8007cee:	627b      	str	r3, [r7, #36]	; 0x24
-  u32_t iss;
-  u16_t old_local_port;
-
-  LWIP_ASSERT_CORE_LOCKED();
-
-  LWIP_ERROR("tcp_connect: invalid pcb", pcb != NULL, return ERR_ARG);
- 8007cf0:	68fb      	ldr	r3, [r7, #12]
- 8007cf2:	2b00      	cmp	r3, #0
- 8007cf4:	d109      	bne.n	8007d0a <tcp_connect+0x2e>
- 8007cf6:	4b7d      	ldr	r3, [pc, #500]	; (8007eec <tcp_connect+0x210>)
- 8007cf8:	f240 4235 	movw	r2, #1077	; 0x435
- 8007cfc:	497c      	ldr	r1, [pc, #496]	; (8007ef0 <tcp_connect+0x214>)
- 8007cfe:	487d      	ldr	r0, [pc, #500]	; (8007ef4 <tcp_connect+0x218>)
- 8007d00:	f008 ff62 	bl	8010bc8 <iprintf>
- 8007d04:	f06f 030f 	mvn.w	r3, #15
- 8007d08:	e0ec      	b.n	8007ee4 <tcp_connect+0x208>
-  LWIP_ERROR("tcp_connect: invalid ipaddr", ipaddr != NULL, return ERR_ARG);
- 8007d0a:	68bb      	ldr	r3, [r7, #8]
- 8007d0c:	2b00      	cmp	r3, #0
- 8007d0e:	d109      	bne.n	8007d24 <tcp_connect+0x48>
- 8007d10:	4b76      	ldr	r3, [pc, #472]	; (8007eec <tcp_connect+0x210>)
- 8007d12:	f240 4236 	movw	r2, #1078	; 0x436
- 8007d16:	4978      	ldr	r1, [pc, #480]	; (8007ef8 <tcp_connect+0x21c>)
- 8007d18:	4876      	ldr	r0, [pc, #472]	; (8007ef4 <tcp_connect+0x218>)
- 8007d1a:	f008 ff55 	bl	8010bc8 <iprintf>
- 8007d1e:	f06f 030f 	mvn.w	r3, #15
- 8007d22:	e0df      	b.n	8007ee4 <tcp_connect+0x208>
-
-  LWIP_ERROR("tcp_connect: can only connect from state CLOSED", pcb->state == CLOSED, return ERR_ISCONN);
- 8007d24:	68fb      	ldr	r3, [r7, #12]
- 8007d26:	7d1b      	ldrb	r3, [r3, #20]
- 8007d28:	2b00      	cmp	r3, #0
- 8007d2a:	d009      	beq.n	8007d40 <tcp_connect+0x64>
- 8007d2c:	4b6f      	ldr	r3, [pc, #444]	; (8007eec <tcp_connect+0x210>)
- 8007d2e:	f44f 6287 	mov.w	r2, #1080	; 0x438
- 8007d32:	4972      	ldr	r1, [pc, #456]	; (8007efc <tcp_connect+0x220>)
- 8007d34:	486f      	ldr	r0, [pc, #444]	; (8007ef4 <tcp_connect+0x218>)
- 8007d36:	f008 ff47 	bl	8010bc8 <iprintf>
- 8007d3a:	f06f 0309 	mvn.w	r3, #9
- 8007d3e:	e0d1      	b.n	8007ee4 <tcp_connect+0x208>
-
-  LWIP_DEBUGF(TCP_DEBUG, ("tcp_connect to port %"U16_F"\n", port));
-  ip_addr_set(&pcb->remote_ip, ipaddr);
- 8007d40:	68bb      	ldr	r3, [r7, #8]
- 8007d42:	2b00      	cmp	r3, #0
- 8007d44:	d002      	beq.n	8007d4c <tcp_connect+0x70>
- 8007d46:	68bb      	ldr	r3, [r7, #8]
- 8007d48:	681b      	ldr	r3, [r3, #0]
- 8007d4a:	e000      	b.n	8007d4e <tcp_connect+0x72>
- 8007d4c:	2300      	movs	r3, #0
- 8007d4e:	68fa      	ldr	r2, [r7, #12]
- 8007d50:	6053      	str	r3, [r2, #4]
-  pcb->remote_port = port;
- 8007d52:	68fb      	ldr	r3, [r7, #12]
- 8007d54:	88fa      	ldrh	r2, [r7, #6]
- 8007d56:	831a      	strh	r2, [r3, #24]
-
-  if (pcb->netif_idx != NETIF_NO_INDEX) {
- 8007d58:	68fb      	ldr	r3, [r7, #12]
- 8007d5a:	7a1b      	ldrb	r3, [r3, #8]
- 8007d5c:	2b00      	cmp	r3, #0
- 8007d5e:	d006      	beq.n	8007d6e <tcp_connect+0x92>
-    netif = netif_get_by_index(pcb->netif_idx);
- 8007d60:	68fb      	ldr	r3, [r7, #12]
- 8007d62:	7a1b      	ldrb	r3, [r3, #8]
- 8007d64:	4618      	mov	r0, r3
- 8007d66:	f7fe fdd5 	bl	8006914 <netif_get_by_index>
- 8007d6a:	6278      	str	r0, [r7, #36]	; 0x24
- 8007d6c:	e005      	b.n	8007d7a <tcp_connect+0x9e>
-  } else {
-    /* check if we have a route to the remote host */
-    netif = ip_route(&pcb->local_ip, &pcb->remote_ip);
- 8007d6e:	68fb      	ldr	r3, [r7, #12]
- 8007d70:	3304      	adds	r3, #4
- 8007d72:	4618      	mov	r0, r3
- 8007d74:	f007 f888 	bl	800ee88 <ip4_route>
- 8007d78:	6278      	str	r0, [r7, #36]	; 0x24
-  }
-  if (netif == NULL) {
- 8007d7a:	6a7b      	ldr	r3, [r7, #36]	; 0x24
- 8007d7c:	2b00      	cmp	r3, #0
- 8007d7e:	d102      	bne.n	8007d86 <tcp_connect+0xaa>
-    /* Don't even try to send a SYN packet if we have no route since that will fail. */
-    return ERR_RTE;
- 8007d80:	f06f 0303 	mvn.w	r3, #3
- 8007d84:	e0ae      	b.n	8007ee4 <tcp_connect+0x208>
-  }
-
-  /* check if local IP has been assigned to pcb, if not, get one */
-  if (ip_addr_isany(&pcb->local_ip)) {
- 8007d86:	68fb      	ldr	r3, [r7, #12]
- 8007d88:	2b00      	cmp	r3, #0
- 8007d8a:	d003      	beq.n	8007d94 <tcp_connect+0xb8>
- 8007d8c:	68fb      	ldr	r3, [r7, #12]
- 8007d8e:	681b      	ldr	r3, [r3, #0]
- 8007d90:	2b00      	cmp	r3, #0
- 8007d92:	d111      	bne.n	8007db8 <tcp_connect+0xdc>
-    const ip_addr_t *local_ip = ip_netif_get_local_ip(netif, ipaddr);
- 8007d94:	6a7b      	ldr	r3, [r7, #36]	; 0x24
- 8007d96:	2b00      	cmp	r3, #0
- 8007d98:	d002      	beq.n	8007da0 <tcp_connect+0xc4>
- 8007d9a:	6a7b      	ldr	r3, [r7, #36]	; 0x24
- 8007d9c:	3304      	adds	r3, #4
- 8007d9e:	e000      	b.n	8007da2 <tcp_connect+0xc6>
- 8007da0:	2300      	movs	r3, #0
- 8007da2:	61fb      	str	r3, [r7, #28]
-    if (local_ip == NULL) {
- 8007da4:	69fb      	ldr	r3, [r7, #28]
- 8007da6:	2b00      	cmp	r3, #0
- 8007da8:	d102      	bne.n	8007db0 <tcp_connect+0xd4>
-      return ERR_RTE;
- 8007daa:	f06f 0303 	mvn.w	r3, #3
- 8007dae:	e099      	b.n	8007ee4 <tcp_connect+0x208>
-    }
-    ip_addr_copy(pcb->local_ip, *local_ip);
- 8007db0:	69fb      	ldr	r3, [r7, #28]
- 8007db2:	681a      	ldr	r2, [r3, #0]
- 8007db4:	68fb      	ldr	r3, [r7, #12]
- 8007db6:	601a      	str	r2, [r3, #0]
-      ip6_addr_lacks_zone(ip_2_ip6(&pcb->remote_ip), IP6_UNICAST)) {
-    ip6_addr_assign_zone(ip_2_ip6(&pcb->remote_ip), IP6_UNICAST, netif);
-  }
-#endif /* LWIP_IPV6 && LWIP_IPV6_SCOPES */
-
-  old_local_port = pcb->local_port;
- 8007db8:	68fb      	ldr	r3, [r7, #12]
- 8007dba:	8adb      	ldrh	r3, [r3, #22]
- 8007dbc:	837b      	strh	r3, [r7, #26]
-  if (pcb->local_port == 0) {
- 8007dbe:	68fb      	ldr	r3, [r7, #12]
- 8007dc0:	8adb      	ldrh	r3, [r3, #22]
- 8007dc2:	2b00      	cmp	r3, #0
- 8007dc4:	d10c      	bne.n	8007de0 <tcp_connect+0x104>
-    pcb->local_port = tcp_new_port();
- 8007dc6:	f7ff ff43 	bl	8007c50 <tcp_new_port>
- 8007dca:	4603      	mov	r3, r0
- 8007dcc:	461a      	mov	r2, r3
- 8007dce:	68fb      	ldr	r3, [r7, #12]
- 8007dd0:	82da      	strh	r2, [r3, #22]
-    if (pcb->local_port == 0) {
- 8007dd2:	68fb      	ldr	r3, [r7, #12]
- 8007dd4:	8adb      	ldrh	r3, [r3, #22]
- 8007dd6:	2b00      	cmp	r3, #0
- 8007dd8:	d102      	bne.n	8007de0 <tcp_connect+0x104>
-      return ERR_BUF;
- 8007dda:	f06f 0301 	mvn.w	r3, #1
- 8007dde:	e081      	b.n	8007ee4 <tcp_connect+0x208>
-      }
-    }
-#endif /* SO_REUSE */
-  }
-
-  iss = tcp_next_iss(pcb);
- 8007de0:	68f8      	ldr	r0, [r7, #12]
- 8007de2:	f001 f819 	bl	8008e18 <tcp_next_iss>
- 8007de6:	6178      	str	r0, [r7, #20]
-  pcb->rcv_nxt = 0;
- 8007de8:	68fb      	ldr	r3, [r7, #12]
- 8007dea:	2200      	movs	r2, #0
- 8007dec:	625a      	str	r2, [r3, #36]	; 0x24
-  pcb->snd_nxt = iss;
- 8007dee:	68fb      	ldr	r3, [r7, #12]
- 8007df0:	697a      	ldr	r2, [r7, #20]
- 8007df2:	651a      	str	r2, [r3, #80]	; 0x50
-  pcb->lastack = iss - 1;
- 8007df4:	697b      	ldr	r3, [r7, #20]
- 8007df6:	1e5a      	subs	r2, r3, #1
- 8007df8:	68fb      	ldr	r3, [r7, #12]
- 8007dfa:	645a      	str	r2, [r3, #68]	; 0x44
-  pcb->snd_wl2 = iss - 1;
- 8007dfc:	697b      	ldr	r3, [r7, #20]
- 8007dfe:	1e5a      	subs	r2, r3, #1
- 8007e00:	68fb      	ldr	r3, [r7, #12]
- 8007e02:	659a      	str	r2, [r3, #88]	; 0x58
-  pcb->snd_lbb = iss - 1;
- 8007e04:	697b      	ldr	r3, [r7, #20]
- 8007e06:	1e5a      	subs	r2, r3, #1
- 8007e08:	68fb      	ldr	r3, [r7, #12]
- 8007e0a:	65da      	str	r2, [r3, #92]	; 0x5c
-  /* Start with a window that does not need scaling. When window scaling is
-     enabled and used, the window is enlarged when both sides agree on scaling. */
-  pcb->rcv_wnd = pcb->rcv_ann_wnd = TCPWND_MIN16(TCP_WND);
- 8007e0c:	68fb      	ldr	r3, [r7, #12]
- 8007e0e:	f44f 6206 	mov.w	r2, #2144	; 0x860
- 8007e12:	855a      	strh	r2, [r3, #42]	; 0x2a
- 8007e14:	68fb      	ldr	r3, [r7, #12]
- 8007e16:	8d5a      	ldrh	r2, [r3, #42]	; 0x2a
- 8007e18:	68fb      	ldr	r3, [r7, #12]
- 8007e1a:	851a      	strh	r2, [r3, #40]	; 0x28
-  pcb->rcv_ann_right_edge = pcb->rcv_nxt;
- 8007e1c:	68fb      	ldr	r3, [r7, #12]
- 8007e1e:	6a5a      	ldr	r2, [r3, #36]	; 0x24
- 8007e20:	68fb      	ldr	r3, [r7, #12]
- 8007e22:	62da      	str	r2, [r3, #44]	; 0x2c
-  pcb->snd_wnd = TCP_WND;
- 8007e24:	68fb      	ldr	r3, [r7, #12]
- 8007e26:	f44f 6206 	mov.w	r2, #2144	; 0x860
- 8007e2a:	f8a3 2060 	strh.w	r2, [r3, #96]	; 0x60
-  /* As initial send MSS, we use TCP_MSS but limit it to 536.
-     The send MSS is updated when an MSS option is received. */
-  pcb->mss = INITIAL_MSS;
- 8007e2e:	68fb      	ldr	r3, [r7, #12]
- 8007e30:	f44f 7206 	mov.w	r2, #536	; 0x218
- 8007e34:	865a      	strh	r2, [r3, #50]	; 0x32
-#if TCP_CALCULATE_EFF_SEND_MSS
-  pcb->mss = tcp_eff_send_mss_netif(pcb->mss, netif, &pcb->remote_ip);
- 8007e36:	68fb      	ldr	r3, [r7, #12]
- 8007e38:	8e58      	ldrh	r0, [r3, #50]	; 0x32
- 8007e3a:	68fb      	ldr	r3, [r7, #12]
- 8007e3c:	3304      	adds	r3, #4
- 8007e3e:	461a      	mov	r2, r3
- 8007e40:	6a79      	ldr	r1, [r7, #36]	; 0x24
- 8007e42:	f001 f80f 	bl	8008e64 <tcp_eff_send_mss_netif>
- 8007e46:	4603      	mov	r3, r0
- 8007e48:	461a      	mov	r2, r3
- 8007e4a:	68fb      	ldr	r3, [r7, #12]
- 8007e4c:	865a      	strh	r2, [r3, #50]	; 0x32
-#endif /* TCP_CALCULATE_EFF_SEND_MSS */
-  pcb->cwnd = 1;
- 8007e4e:	68fb      	ldr	r3, [r7, #12]
- 8007e50:	2201      	movs	r2, #1
- 8007e52:	f8a3 2048 	strh.w	r2, [r3, #72]	; 0x48
-#if LWIP_CALLBACK_API
-  pcb->connected = connected;
- 8007e56:	68fb      	ldr	r3, [r7, #12]
- 8007e58:	683a      	ldr	r2, [r7, #0]
- 8007e5a:	f8c3 2088 	str.w	r2, [r3, #136]	; 0x88
-#else /* LWIP_CALLBACK_API */
-  LWIP_UNUSED_ARG(connected);
-#endif /* LWIP_CALLBACK_API */
-
-  /* Send a SYN together with the MSS option. */
-  ret = tcp_enqueue_flags(pcb, TCP_SYN);
- 8007e5e:	2102      	movs	r1, #2
- 8007e60:	68f8      	ldr	r0, [r7, #12]
- 8007e62:	f004 fad9 	bl	800c418 <tcp_enqueue_flags>
- 8007e66:	4603      	mov	r3, r0
- 8007e68:	74fb      	strb	r3, [r7, #19]
-  if (ret == ERR_OK) {
- 8007e6a:	f997 3013 	ldrsb.w	r3, [r7, #19]
- 8007e6e:	2b00      	cmp	r3, #0
- 8007e70:	d136      	bne.n	8007ee0 <tcp_connect+0x204>
-    /* SYN segment was enqueued, changed the pcbs state now */
-    pcb->state = SYN_SENT;
- 8007e72:	68fb      	ldr	r3, [r7, #12]
- 8007e74:	2202      	movs	r2, #2
- 8007e76:	751a      	strb	r2, [r3, #20]
-    if (old_local_port != 0) {
- 8007e78:	8b7b      	ldrh	r3, [r7, #26]
- 8007e7a:	2b00      	cmp	r3, #0
- 8007e7c:	d021      	beq.n	8007ec2 <tcp_connect+0x1e6>
-      TCP_RMV(&tcp_bound_pcbs, pcb);
- 8007e7e:	4b20      	ldr	r3, [pc, #128]	; (8007f00 <tcp_connect+0x224>)
- 8007e80:	681b      	ldr	r3, [r3, #0]
- 8007e82:	68fa      	ldr	r2, [r7, #12]
- 8007e84:	429a      	cmp	r2, r3
- 8007e86:	d105      	bne.n	8007e94 <tcp_connect+0x1b8>
- 8007e88:	4b1d      	ldr	r3, [pc, #116]	; (8007f00 <tcp_connect+0x224>)
- 8007e8a:	681b      	ldr	r3, [r3, #0]
- 8007e8c:	68db      	ldr	r3, [r3, #12]
- 8007e8e:	4a1c      	ldr	r2, [pc, #112]	; (8007f00 <tcp_connect+0x224>)
- 8007e90:	6013      	str	r3, [r2, #0]
- 8007e92:	e013      	b.n	8007ebc <tcp_connect+0x1e0>
- 8007e94:	4b1a      	ldr	r3, [pc, #104]	; (8007f00 <tcp_connect+0x224>)
- 8007e96:	681b      	ldr	r3, [r3, #0]
- 8007e98:	623b      	str	r3, [r7, #32]
- 8007e9a:	e00c      	b.n	8007eb6 <tcp_connect+0x1da>
- 8007e9c:	6a3b      	ldr	r3, [r7, #32]
- 8007e9e:	68db      	ldr	r3, [r3, #12]
- 8007ea0:	68fa      	ldr	r2, [r7, #12]
- 8007ea2:	429a      	cmp	r2, r3
- 8007ea4:	d104      	bne.n	8007eb0 <tcp_connect+0x1d4>
- 8007ea6:	68fb      	ldr	r3, [r7, #12]
- 8007ea8:	68da      	ldr	r2, [r3, #12]
- 8007eaa:	6a3b      	ldr	r3, [r7, #32]
- 8007eac:	60da      	str	r2, [r3, #12]
- 8007eae:	e005      	b.n	8007ebc <tcp_connect+0x1e0>
- 8007eb0:	6a3b      	ldr	r3, [r7, #32]
- 8007eb2:	68db      	ldr	r3, [r3, #12]
- 8007eb4:	623b      	str	r3, [r7, #32]
- 8007eb6:	6a3b      	ldr	r3, [r7, #32]
- 8007eb8:	2b00      	cmp	r3, #0
- 8007eba:	d1ef      	bne.n	8007e9c <tcp_connect+0x1c0>
- 8007ebc:	68fb      	ldr	r3, [r7, #12]
- 8007ebe:	2200      	movs	r2, #0
- 8007ec0:	60da      	str	r2, [r3, #12]
-    }
-    TCP_REG_ACTIVE(pcb);
- 8007ec2:	4b10      	ldr	r3, [pc, #64]	; (8007f04 <tcp_connect+0x228>)
- 8007ec4:	681a      	ldr	r2, [r3, #0]
- 8007ec6:	68fb      	ldr	r3, [r7, #12]
- 8007ec8:	60da      	str	r2, [r3, #12]
- 8007eca:	4a0e      	ldr	r2, [pc, #56]	; (8007f04 <tcp_connect+0x228>)
- 8007ecc:	68fb      	ldr	r3, [r7, #12]
- 8007ece:	6013      	str	r3, [r2, #0]
- 8007ed0:	f005 fb12 	bl	800d4f8 <tcp_timer_needed>
- 8007ed4:	4b0c      	ldr	r3, [pc, #48]	; (8007f08 <tcp_connect+0x22c>)
- 8007ed6:	2201      	movs	r2, #1
- 8007ed8:	701a      	strb	r2, [r3, #0]
-    MIB2_STATS_INC(mib2.tcpactiveopens);
-
-    tcp_output(pcb);
- 8007eda:	68f8      	ldr	r0, [r7, #12]
- 8007edc:	f004 fb8a 	bl	800c5f4 <tcp_output>
-  }
-  return ret;
- 8007ee0:	f997 3013 	ldrsb.w	r3, [r7, #19]
-}
- 8007ee4:	4618      	mov	r0, r3
- 8007ee6:	3728      	adds	r7, #40	; 0x28
- 8007ee8:	46bd      	mov	sp, r7
- 8007eea:	bd80      	pop	{r7, pc}
- 8007eec:	08012a08 	.word	0x08012a08
- 8007ef0:	08012ce4 	.word	0x08012ce4
- 8007ef4:	08012a4c 	.word	0x08012a4c
- 8007ef8:	08012d00 	.word	0x08012d00
- 8007efc:	08012d1c 	.word	0x08012d1c
- 8007f00:	24007b70 	.word	0x24007b70
- 8007f04:	24007b78 	.word	0x24007b78
- 8007f08:	24007b80 	.word	0x24007b80
-
-08007f0c <tcp_slowtmr>:
- *
- * Automatically called from tcp_tmr().
- */
-void
-tcp_slowtmr(void)
-{
- 8007f0c:	b5b0      	push	{r4, r5, r7, lr}
- 8007f0e:	b090      	sub	sp, #64	; 0x40
- 8007f10:	af04      	add	r7, sp, #16
-  tcpwnd_size_t eff_wnd;
-  u8_t pcb_remove;      /* flag if a PCB should be removed */
-  u8_t pcb_reset;       /* flag if a RST should be sent when removing */
-  err_t err;
-
-  err = ERR_OK;
- 8007f12:	2300      	movs	r3, #0
- 8007f14:	f887 3025 	strb.w	r3, [r7, #37]	; 0x25
-
-  ++tcp_ticks;
- 8007f18:	4b94      	ldr	r3, [pc, #592]	; (800816c <tcp_slowtmr+0x260>)
- 8007f1a:	681b      	ldr	r3, [r3, #0]
- 8007f1c:	3301      	adds	r3, #1
- 8007f1e:	4a93      	ldr	r2, [pc, #588]	; (800816c <tcp_slowtmr+0x260>)
- 8007f20:	6013      	str	r3, [r2, #0]
-  ++tcp_timer_ctr;
- 8007f22:	4b93      	ldr	r3, [pc, #588]	; (8008170 <tcp_slowtmr+0x264>)
- 8007f24:	781b      	ldrb	r3, [r3, #0]
- 8007f26:	3301      	adds	r3, #1
- 8007f28:	b2da      	uxtb	r2, r3
- 8007f2a:	4b91      	ldr	r3, [pc, #580]	; (8008170 <tcp_slowtmr+0x264>)
- 8007f2c:	701a      	strb	r2, [r3, #0]
-
-tcp_slowtmr_start:
-  /* Steps through all of the active PCBs. */
-  prev = NULL;
- 8007f2e:	2300      	movs	r3, #0
- 8007f30:	62bb      	str	r3, [r7, #40]	; 0x28
-  pcb = tcp_active_pcbs;
- 8007f32:	4b90      	ldr	r3, [pc, #576]	; (8008174 <tcp_slowtmr+0x268>)
- 8007f34:	681b      	ldr	r3, [r3, #0]
- 8007f36:	62fb      	str	r3, [r7, #44]	; 0x2c
-  if (pcb == NULL) {
-    LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: no active pcbs\n"));
-  }
-  while (pcb != NULL) {
- 8007f38:	e29d      	b.n	8008476 <tcp_slowtmr+0x56a>
-    LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: processing active pcb\n"));
-    LWIP_ASSERT("tcp_slowtmr: active pcb->state != CLOSED\n", pcb->state != CLOSED);
- 8007f3a:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 8007f3c:	7d1b      	ldrb	r3, [r3, #20]
- 8007f3e:	2b00      	cmp	r3, #0
- 8007f40:	d106      	bne.n	8007f50 <tcp_slowtmr+0x44>
- 8007f42:	4b8d      	ldr	r3, [pc, #564]	; (8008178 <tcp_slowtmr+0x26c>)
- 8007f44:	f240 42be 	movw	r2, #1214	; 0x4be
- 8007f48:	498c      	ldr	r1, [pc, #560]	; (800817c <tcp_slowtmr+0x270>)
- 8007f4a:	488d      	ldr	r0, [pc, #564]	; (8008180 <tcp_slowtmr+0x274>)
- 8007f4c:	f008 fe3c 	bl	8010bc8 <iprintf>
-    LWIP_ASSERT("tcp_slowtmr: active pcb->state != LISTEN\n", pcb->state != LISTEN);
- 8007f50:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 8007f52:	7d1b      	ldrb	r3, [r3, #20]
- 8007f54:	2b01      	cmp	r3, #1
- 8007f56:	d106      	bne.n	8007f66 <tcp_slowtmr+0x5a>
- 8007f58:	4b87      	ldr	r3, [pc, #540]	; (8008178 <tcp_slowtmr+0x26c>)
- 8007f5a:	f240 42bf 	movw	r2, #1215	; 0x4bf
- 8007f5e:	4989      	ldr	r1, [pc, #548]	; (8008184 <tcp_slowtmr+0x278>)
- 8007f60:	4887      	ldr	r0, [pc, #540]	; (8008180 <tcp_slowtmr+0x274>)
- 8007f62:	f008 fe31 	bl	8010bc8 <iprintf>
-    LWIP_ASSERT("tcp_slowtmr: active pcb->state != TIME-WAIT\n", pcb->state != TIME_WAIT);
- 8007f66:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 8007f68:	7d1b      	ldrb	r3, [r3, #20]
- 8007f6a:	2b0a      	cmp	r3, #10
- 8007f6c:	d106      	bne.n	8007f7c <tcp_slowtmr+0x70>
- 8007f6e:	4b82      	ldr	r3, [pc, #520]	; (8008178 <tcp_slowtmr+0x26c>)
- 8007f70:	f44f 6298 	mov.w	r2, #1216	; 0x4c0
- 8007f74:	4984      	ldr	r1, [pc, #528]	; (8008188 <tcp_slowtmr+0x27c>)
- 8007f76:	4882      	ldr	r0, [pc, #520]	; (8008180 <tcp_slowtmr+0x274>)
- 8007f78:	f008 fe26 	bl	8010bc8 <iprintf>
-    if (pcb->last_timer == tcp_timer_ctr) {
- 8007f7c:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 8007f7e:	7f9a      	ldrb	r2, [r3, #30]
- 8007f80:	4b7b      	ldr	r3, [pc, #492]	; (8008170 <tcp_slowtmr+0x264>)
- 8007f82:	781b      	ldrb	r3, [r3, #0]
- 8007f84:	429a      	cmp	r2, r3
- 8007f86:	d105      	bne.n	8007f94 <tcp_slowtmr+0x88>
-      /* skip this pcb, we have already processed it */
-      prev = pcb;
- 8007f88:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 8007f8a:	62bb      	str	r3, [r7, #40]	; 0x28
-      pcb = pcb->next;
- 8007f8c:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 8007f8e:	68db      	ldr	r3, [r3, #12]
- 8007f90:	62fb      	str	r3, [r7, #44]	; 0x2c
-      continue;
- 8007f92:	e270      	b.n	8008476 <tcp_slowtmr+0x56a>
-    }
-    pcb->last_timer = tcp_timer_ctr;
- 8007f94:	4b76      	ldr	r3, [pc, #472]	; (8008170 <tcp_slowtmr+0x264>)
- 8007f96:	781a      	ldrb	r2, [r3, #0]
- 8007f98:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 8007f9a:	779a      	strb	r2, [r3, #30]
-
-    pcb_remove = 0;
- 8007f9c:	2300      	movs	r3, #0
- 8007f9e:	f887 3027 	strb.w	r3, [r7, #39]	; 0x27
-    pcb_reset = 0;
- 8007fa2:	2300      	movs	r3, #0
- 8007fa4:	f887 3026 	strb.w	r3, [r7, #38]	; 0x26
-
-    if (pcb->state == SYN_SENT && pcb->nrtx >= TCP_SYNMAXRTX) {
- 8007fa8:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 8007faa:	7d1b      	ldrb	r3, [r3, #20]
- 8007fac:	2b02      	cmp	r3, #2
- 8007fae:	d10a      	bne.n	8007fc6 <tcp_slowtmr+0xba>
- 8007fb0:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 8007fb2:	f893 3042 	ldrb.w	r3, [r3, #66]	; 0x42
- 8007fb6:	2b05      	cmp	r3, #5
- 8007fb8:	d905      	bls.n	8007fc6 <tcp_slowtmr+0xba>
-      ++pcb_remove;
- 8007fba:	f897 3027 	ldrb.w	r3, [r7, #39]	; 0x27
- 8007fbe:	3301      	adds	r3, #1
- 8007fc0:	f887 3027 	strb.w	r3, [r7, #39]	; 0x27
-      LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: max SYN retries reached\n"));
- 8007fc4:	e11e      	b.n	8008204 <tcp_slowtmr+0x2f8>
-    } else if (pcb->nrtx >= TCP_MAXRTX) {
- 8007fc6:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 8007fc8:	f893 3042 	ldrb.w	r3, [r3, #66]	; 0x42
- 8007fcc:	2b0b      	cmp	r3, #11
- 8007fce:	d905      	bls.n	8007fdc <tcp_slowtmr+0xd0>
-      ++pcb_remove;
- 8007fd0:	f897 3027 	ldrb.w	r3, [r7, #39]	; 0x27
- 8007fd4:	3301      	adds	r3, #1
- 8007fd6:	f887 3027 	strb.w	r3, [r7, #39]	; 0x27
- 8007fda:	e113      	b.n	8008204 <tcp_slowtmr+0x2f8>
-      LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: max DATA retries reached\n"));
-    } else {
-      if (pcb->persist_backoff > 0) {
- 8007fdc:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 8007fde:	f893 3099 	ldrb.w	r3, [r3, #153]	; 0x99
- 8007fe2:	2b00      	cmp	r3, #0
- 8007fe4:	d075      	beq.n	80080d2 <tcp_slowtmr+0x1c6>
-        LWIP_ASSERT("tcp_slowtimr: persist ticking with in-flight data", pcb->unacked == NULL);
- 8007fe6:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 8007fe8:	6f1b      	ldr	r3, [r3, #112]	; 0x70
- 8007fea:	2b00      	cmp	r3, #0
- 8007fec:	d006      	beq.n	8007ffc <tcp_slowtmr+0xf0>
- 8007fee:	4b62      	ldr	r3, [pc, #392]	; (8008178 <tcp_slowtmr+0x26c>)
- 8007ff0:	f240 42d4 	movw	r2, #1236	; 0x4d4
- 8007ff4:	4965      	ldr	r1, [pc, #404]	; (800818c <tcp_slowtmr+0x280>)
- 8007ff6:	4862      	ldr	r0, [pc, #392]	; (8008180 <tcp_slowtmr+0x274>)
- 8007ff8:	f008 fde6 	bl	8010bc8 <iprintf>
-        LWIP_ASSERT("tcp_slowtimr: persist ticking with empty send buffer", pcb->unsent != NULL);
- 8007ffc:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 8007ffe:	6edb      	ldr	r3, [r3, #108]	; 0x6c
- 8008000:	2b00      	cmp	r3, #0
- 8008002:	d106      	bne.n	8008012 <tcp_slowtmr+0x106>
- 8008004:	4b5c      	ldr	r3, [pc, #368]	; (8008178 <tcp_slowtmr+0x26c>)
- 8008006:	f240 42d5 	movw	r2, #1237	; 0x4d5
- 800800a:	4961      	ldr	r1, [pc, #388]	; (8008190 <tcp_slowtmr+0x284>)
- 800800c:	485c      	ldr	r0, [pc, #368]	; (8008180 <tcp_slowtmr+0x274>)
- 800800e:	f008 fddb 	bl	8010bc8 <iprintf>
-        if (pcb->persist_probe >= TCP_MAXRTX) {
- 8008012:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 8008014:	f893 309a 	ldrb.w	r3, [r3, #154]	; 0x9a
- 8008018:	2b0b      	cmp	r3, #11
- 800801a:	d905      	bls.n	8008028 <tcp_slowtmr+0x11c>
-          ++pcb_remove; /* max probes reached */
- 800801c:	f897 3027 	ldrb.w	r3, [r7, #39]	; 0x27
- 8008020:	3301      	adds	r3, #1
- 8008022:	f887 3027 	strb.w	r3, [r7, #39]	; 0x27
- 8008026:	e0ed      	b.n	8008204 <tcp_slowtmr+0x2f8>
-        } else {
-          u8_t backoff_cnt = tcp_persist_backoff[pcb->persist_backoff - 1];
- 8008028:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 800802a:	f893 3099 	ldrb.w	r3, [r3, #153]	; 0x99
- 800802e:	3b01      	subs	r3, #1
- 8008030:	4a58      	ldr	r2, [pc, #352]	; (8008194 <tcp_slowtmr+0x288>)
- 8008032:	5cd3      	ldrb	r3, [r2, r3]
- 8008034:	747b      	strb	r3, [r7, #17]
-          if (pcb->persist_cnt < backoff_cnt) {
- 8008036:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 8008038:	f893 3098 	ldrb.w	r3, [r3, #152]	; 0x98
- 800803c:	7c7a      	ldrb	r2, [r7, #17]
- 800803e:	429a      	cmp	r2, r3
- 8008040:	d907      	bls.n	8008052 <tcp_slowtmr+0x146>
-            pcb->persist_cnt++;
- 8008042:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 8008044:	f893 3098 	ldrb.w	r3, [r3, #152]	; 0x98
- 8008048:	3301      	adds	r3, #1
- 800804a:	b2da      	uxtb	r2, r3
- 800804c:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 800804e:	f883 2098 	strb.w	r2, [r3, #152]	; 0x98
-          }
-          if (pcb->persist_cnt >= backoff_cnt) {
- 8008052:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 8008054:	f893 3098 	ldrb.w	r3, [r3, #152]	; 0x98
- 8008058:	7c7a      	ldrb	r2, [r7, #17]
- 800805a:	429a      	cmp	r2, r3
- 800805c:	f200 80d2 	bhi.w	8008204 <tcp_slowtmr+0x2f8>
-            int next_slot = 1; /* increment timer to next slot */
- 8008060:	2301      	movs	r3, #1
- 8008062:	623b      	str	r3, [r7, #32]
-            /* If snd_wnd is zero, send 1 byte probes */
-            if (pcb->snd_wnd == 0) {
- 8008064:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 8008066:	f8b3 3060 	ldrh.w	r3, [r3, #96]	; 0x60
- 800806a:	2b00      	cmp	r3, #0
- 800806c:	d108      	bne.n	8008080 <tcp_slowtmr+0x174>
-              if (tcp_zero_window_probe(pcb) != ERR_OK) {
- 800806e:	6af8      	ldr	r0, [r7, #44]	; 0x2c
- 8008070:	f005 f974 	bl	800d35c <tcp_zero_window_probe>
- 8008074:	4603      	mov	r3, r0
- 8008076:	2b00      	cmp	r3, #0
- 8008078:	d014      	beq.n	80080a4 <tcp_slowtmr+0x198>
-                next_slot = 0; /* try probe again with current slot */
- 800807a:	2300      	movs	r3, #0
- 800807c:	623b      	str	r3, [r7, #32]
- 800807e:	e011      	b.n	80080a4 <tcp_slowtmr+0x198>
-              }
-              /* snd_wnd not fully closed, split unsent head and fill window */
-            } else {
-              if (tcp_split_unsent_seg(pcb, (u16_t)pcb->snd_wnd) == ERR_OK) {
- 8008080:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 8008082:	f8b3 3060 	ldrh.w	r3, [r3, #96]	; 0x60
- 8008086:	4619      	mov	r1, r3
- 8008088:	6af8      	ldr	r0, [r7, #44]	; 0x2c
- 800808a:	f004 f829 	bl	800c0e0 <tcp_split_unsent_seg>
- 800808e:	4603      	mov	r3, r0
- 8008090:	2b00      	cmp	r3, #0
- 8008092:	d107      	bne.n	80080a4 <tcp_slowtmr+0x198>
-                if (tcp_output(pcb) == ERR_OK) {
- 8008094:	6af8      	ldr	r0, [r7, #44]	; 0x2c
- 8008096:	f004 faad 	bl	800c5f4 <tcp_output>
- 800809a:	4603      	mov	r3, r0
- 800809c:	2b00      	cmp	r3, #0
- 800809e:	d101      	bne.n	80080a4 <tcp_slowtmr+0x198>
-                  /* sending will cancel persist timer, else retry with current slot */
-                  next_slot = 0;
- 80080a0:	2300      	movs	r3, #0
- 80080a2:	623b      	str	r3, [r7, #32]
-                }
-              }
-            }
-            if (next_slot) {
- 80080a4:	6a3b      	ldr	r3, [r7, #32]
- 80080a6:	2b00      	cmp	r3, #0
- 80080a8:	f000 80ac 	beq.w	8008204 <tcp_slowtmr+0x2f8>
-              pcb->persist_cnt = 0;
- 80080ac:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 80080ae:	2200      	movs	r2, #0
- 80080b0:	f883 2098 	strb.w	r2, [r3, #152]	; 0x98
-              if (pcb->persist_backoff < sizeof(tcp_persist_backoff)) {
- 80080b4:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 80080b6:	f893 3099 	ldrb.w	r3, [r3, #153]	; 0x99
- 80080ba:	2b06      	cmp	r3, #6
- 80080bc:	f200 80a2 	bhi.w	8008204 <tcp_slowtmr+0x2f8>
-                pcb->persist_backoff++;
- 80080c0:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 80080c2:	f893 3099 	ldrb.w	r3, [r3, #153]	; 0x99
- 80080c6:	3301      	adds	r3, #1
- 80080c8:	b2da      	uxtb	r2, r3
- 80080ca:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 80080cc:	f883 2099 	strb.w	r2, [r3, #153]	; 0x99
- 80080d0:	e098      	b.n	8008204 <tcp_slowtmr+0x2f8>
-            }
-          }
-        }
-      } else {
-        /* Increase the retransmission timer if it is running */
-        if ((pcb->rtime >= 0) && (pcb->rtime < 0x7FFF)) {
- 80080d2:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 80080d4:	f9b3 3030 	ldrsh.w	r3, [r3, #48]	; 0x30
- 80080d8:	2b00      	cmp	r3, #0
- 80080da:	db0f      	blt.n	80080fc <tcp_slowtmr+0x1f0>
- 80080dc:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 80080de:	f9b3 3030 	ldrsh.w	r3, [r3, #48]	; 0x30
- 80080e2:	f647 72ff 	movw	r2, #32767	; 0x7fff
- 80080e6:	4293      	cmp	r3, r2
- 80080e8:	d008      	beq.n	80080fc <tcp_slowtmr+0x1f0>
-          ++pcb->rtime;
- 80080ea:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 80080ec:	f9b3 3030 	ldrsh.w	r3, [r3, #48]	; 0x30
- 80080f0:	b29b      	uxth	r3, r3
- 80080f2:	3301      	adds	r3, #1
- 80080f4:	b29b      	uxth	r3, r3
- 80080f6:	b21a      	sxth	r2, r3
- 80080f8:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 80080fa:	861a      	strh	r2, [r3, #48]	; 0x30
-        }
-
-        if (pcb->rtime >= pcb->rto) {
- 80080fc:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 80080fe:	f9b3 2030 	ldrsh.w	r2, [r3, #48]	; 0x30
- 8008102:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 8008104:	f9b3 3040 	ldrsh.w	r3, [r3, #64]	; 0x40
- 8008108:	429a      	cmp	r2, r3
- 800810a:	db7b      	blt.n	8008204 <tcp_slowtmr+0x2f8>
-                                      " pcb->rto %"S16_F"\n",
-                                      pcb->rtime, pcb->rto));
-          /* If prepare phase fails but we have unsent data but no unacked data,
-             still execute the backoff calculations below, as this means we somehow
-             failed to send segment. */
-          if ((tcp_rexmit_rto_prepare(pcb) == ERR_OK) || ((pcb->unacked == NULL) && (pcb->unsent != NULL))) {
- 800810c:	6af8      	ldr	r0, [r7, #44]	; 0x2c
- 800810e:	f004 fd67 	bl	800cbe0 <tcp_rexmit_rto_prepare>
- 8008112:	4603      	mov	r3, r0
- 8008114:	2b00      	cmp	r3, #0
- 8008116:	d007      	beq.n	8008128 <tcp_slowtmr+0x21c>
- 8008118:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 800811a:	6f1b      	ldr	r3, [r3, #112]	; 0x70
- 800811c:	2b00      	cmp	r3, #0
- 800811e:	d171      	bne.n	8008204 <tcp_slowtmr+0x2f8>
- 8008120:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 8008122:	6edb      	ldr	r3, [r3, #108]	; 0x6c
- 8008124:	2b00      	cmp	r3, #0
- 8008126:	d06d      	beq.n	8008204 <tcp_slowtmr+0x2f8>
-            /* Double retransmission time-out unless we are trying to
-             * connect to somebody (i.e., we are in SYN_SENT). */
-            if (pcb->state != SYN_SENT) {
- 8008128:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 800812a:	7d1b      	ldrb	r3, [r3, #20]
- 800812c:	2b02      	cmp	r3, #2
- 800812e:	d03a      	beq.n	80081a6 <tcp_slowtmr+0x29a>
-              u8_t backoff_idx = LWIP_MIN(pcb->nrtx, sizeof(tcp_backoff) - 1);
- 8008130:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 8008132:	f893 3042 	ldrb.w	r3, [r3, #66]	; 0x42
- 8008136:	2b0c      	cmp	r3, #12
- 8008138:	bf28      	it	cs
- 800813a:	230c      	movcs	r3, #12
- 800813c:	76fb      	strb	r3, [r7, #27]
-              int calc_rto = ((pcb->sa >> 3) + pcb->sv) << tcp_backoff[backoff_idx];
- 800813e:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 8008140:	f9b3 303c 	ldrsh.w	r3, [r3, #60]	; 0x3c
- 8008144:	10db      	asrs	r3, r3, #3
- 8008146:	b21b      	sxth	r3, r3
- 8008148:	461a      	mov	r2, r3
- 800814a:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 800814c:	f9b3 303e 	ldrsh.w	r3, [r3, #62]	; 0x3e
- 8008150:	4413      	add	r3, r2
- 8008152:	7efa      	ldrb	r2, [r7, #27]
- 8008154:	4910      	ldr	r1, [pc, #64]	; (8008198 <tcp_slowtmr+0x28c>)
- 8008156:	5c8a      	ldrb	r2, [r1, r2]
- 8008158:	4093      	lsls	r3, r2
- 800815a:	617b      	str	r3, [r7, #20]
-              pcb->rto = (s16_t)LWIP_MIN(calc_rto, 0x7FFF);
- 800815c:	697b      	ldr	r3, [r7, #20]
- 800815e:	f647 72fe 	movw	r2, #32766	; 0x7ffe
- 8008162:	4293      	cmp	r3, r2
- 8008164:	dc1a      	bgt.n	800819c <tcp_slowtmr+0x290>
- 8008166:	697b      	ldr	r3, [r7, #20]
- 8008168:	b21a      	sxth	r2, r3
- 800816a:	e019      	b.n	80081a0 <tcp_slowtmr+0x294>
- 800816c:	24007b6c 	.word	0x24007b6c
- 8008170:	24007b82 	.word	0x24007b82
- 8008174:	24007b78 	.word	0x24007b78
- 8008178:	08012a08 	.word	0x08012a08
- 800817c:	08012d4c 	.word	0x08012d4c
- 8008180:	08012a4c 	.word	0x08012a4c
- 8008184:	08012d78 	.word	0x08012d78
- 8008188:	08012da4 	.word	0x08012da4
- 800818c:	08012dd4 	.word	0x08012dd4
- 8008190:	08012e08 	.word	0x08012e08
- 8008194:	08014d64 	.word	0x08014d64
- 8008198:	08014d54 	.word	0x08014d54
- 800819c:	f647 72ff 	movw	r2, #32767	; 0x7fff
- 80081a0:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 80081a2:	f8a3 2040 	strh.w	r2, [r3, #64]	; 0x40
-            }
-
-            /* Reset the retransmission timer. */
-            pcb->rtime = 0;
- 80081a6:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 80081a8:	2200      	movs	r2, #0
- 80081aa:	861a      	strh	r2, [r3, #48]	; 0x30
-
-            /* Reduce congestion window and ssthresh. */
-            eff_wnd = LWIP_MIN(pcb->cwnd, pcb->snd_wnd);
- 80081ac:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 80081ae:	f8b3 2060 	ldrh.w	r2, [r3, #96]	; 0x60
- 80081b2:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 80081b4:	f8b3 3048 	ldrh.w	r3, [r3, #72]	; 0x48
- 80081b8:	4293      	cmp	r3, r2
- 80081ba:	bf28      	it	cs
- 80081bc:	4613      	movcs	r3, r2
- 80081be:	827b      	strh	r3, [r7, #18]
-            pcb->ssthresh = eff_wnd >> 1;
- 80081c0:	8a7b      	ldrh	r3, [r7, #18]
- 80081c2:	085b      	lsrs	r3, r3, #1
- 80081c4:	b29a      	uxth	r2, r3
- 80081c6:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 80081c8:	f8a3 204a 	strh.w	r2, [r3, #74]	; 0x4a
-            if (pcb->ssthresh < (tcpwnd_size_t)(pcb->mss << 1)) {
- 80081cc:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 80081ce:	f8b3 204a 	ldrh.w	r2, [r3, #74]	; 0x4a
- 80081d2:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 80081d4:	8e5b      	ldrh	r3, [r3, #50]	; 0x32
- 80081d6:	005b      	lsls	r3, r3, #1
- 80081d8:	b29b      	uxth	r3, r3
- 80081da:	429a      	cmp	r2, r3
- 80081dc:	d206      	bcs.n	80081ec <tcp_slowtmr+0x2e0>
-              pcb->ssthresh = (tcpwnd_size_t)(pcb->mss << 1);
- 80081de:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 80081e0:	8e5b      	ldrh	r3, [r3, #50]	; 0x32
- 80081e2:	005b      	lsls	r3, r3, #1
- 80081e4:	b29a      	uxth	r2, r3
- 80081e6:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 80081e8:	f8a3 204a 	strh.w	r2, [r3, #74]	; 0x4a
-            }
-            pcb->cwnd = pcb->mss;
- 80081ec:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 80081ee:	8e5a      	ldrh	r2, [r3, #50]	; 0x32
- 80081f0:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 80081f2:	f8a3 2048 	strh.w	r2, [r3, #72]	; 0x48
-            LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_slowtmr: cwnd %"TCPWNDSIZE_F
-                                         " ssthresh %"TCPWNDSIZE_F"\n",
-                                         pcb->cwnd, pcb->ssthresh));
-            pcb->bytes_acked = 0;
- 80081f6:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 80081f8:	2200      	movs	r2, #0
- 80081fa:	f8a3 206a 	strh.w	r2, [r3, #106]	; 0x6a
-
-            /* The following needs to be called AFTER cwnd is set to one
-               mss - STJ */
-            tcp_rexmit_rto_commit(pcb);
- 80081fe:	6af8      	ldr	r0, [r7, #44]	; 0x2c
- 8008200:	f004 fd68 	bl	800ccd4 <tcp_rexmit_rto_commit>
-          }
-        }
-      }
-    }
-    /* Check if this PCB has stayed too long in FIN-WAIT-2 */
-    if (pcb->state == FIN_WAIT_2) {
- 8008204:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 8008206:	7d1b      	ldrb	r3, [r3, #20]
- 8008208:	2b06      	cmp	r3, #6
- 800820a:	d111      	bne.n	8008230 <tcp_slowtmr+0x324>
-      /* If this PCB is in FIN_WAIT_2 because of SHUT_WR don't let it time out. */
-      if (pcb->flags & TF_RXCLOSED) {
- 800820c:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 800820e:	8b5b      	ldrh	r3, [r3, #26]
- 8008210:	f003 0310 	and.w	r3, r3, #16
- 8008214:	2b00      	cmp	r3, #0
- 8008216:	d00b      	beq.n	8008230 <tcp_slowtmr+0x324>
-        /* PCB was fully closed (either through close() or SHUT_RDWR):
-           normal FIN-WAIT timeout handling. */
-        if ((u32_t)(tcp_ticks - pcb->tmr) >
- 8008218:	4b9c      	ldr	r3, [pc, #624]	; (800848c <tcp_slowtmr+0x580>)
- 800821a:	681a      	ldr	r2, [r3, #0]
- 800821c:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 800821e:	6a1b      	ldr	r3, [r3, #32]
- 8008220:	1ad3      	subs	r3, r2, r3
- 8008222:	2b28      	cmp	r3, #40	; 0x28
- 8008224:	d904      	bls.n	8008230 <tcp_slowtmr+0x324>
-            TCP_FIN_WAIT_TIMEOUT / TCP_SLOW_INTERVAL) {
-          ++pcb_remove;
- 8008226:	f897 3027 	ldrb.w	r3, [r7, #39]	; 0x27
- 800822a:	3301      	adds	r3, #1
- 800822c:	f887 3027 	strb.w	r3, [r7, #39]	; 0x27
-        }
-      }
-    }
-
-    /* Check if KEEPALIVE should be sent */
-    if (ip_get_option(pcb, SOF_KEEPALIVE) &&
- 8008230:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 8008232:	7a5b      	ldrb	r3, [r3, #9]
- 8008234:	f003 0308 	and.w	r3, r3, #8
- 8008238:	2b00      	cmp	r3, #0
- 800823a:	d04a      	beq.n	80082d2 <tcp_slowtmr+0x3c6>
-        ((pcb->state == ESTABLISHED) ||
- 800823c:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 800823e:	7d1b      	ldrb	r3, [r3, #20]
-    if (ip_get_option(pcb, SOF_KEEPALIVE) &&
- 8008240:	2b04      	cmp	r3, #4
- 8008242:	d003      	beq.n	800824c <tcp_slowtmr+0x340>
-         (pcb->state == CLOSE_WAIT))) {
- 8008244:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 8008246:	7d1b      	ldrb	r3, [r3, #20]
-        ((pcb->state == ESTABLISHED) ||
- 8008248:	2b07      	cmp	r3, #7
- 800824a:	d142      	bne.n	80082d2 <tcp_slowtmr+0x3c6>
-      if ((u32_t)(tcp_ticks - pcb->tmr) >
- 800824c:	4b8f      	ldr	r3, [pc, #572]	; (800848c <tcp_slowtmr+0x580>)
- 800824e:	681a      	ldr	r2, [r3, #0]
- 8008250:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 8008252:	6a1b      	ldr	r3, [r3, #32]
- 8008254:	1ad2      	subs	r2, r2, r3
-          (pcb->keep_idle + TCP_KEEP_DUR(pcb)) / TCP_SLOW_INTERVAL) {
- 8008256:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 8008258:	f8d3 1094 	ldr.w	r1, [r3, #148]	; 0x94
- 800825c:	4b8c      	ldr	r3, [pc, #560]	; (8008490 <tcp_slowtmr+0x584>)
- 800825e:	440b      	add	r3, r1
- 8008260:	498c      	ldr	r1, [pc, #560]	; (8008494 <tcp_slowtmr+0x588>)
- 8008262:	fba1 1303 	umull	r1, r3, r1, r3
- 8008266:	095b      	lsrs	r3, r3, #5
-      if ((u32_t)(tcp_ticks - pcb->tmr) >
- 8008268:	429a      	cmp	r2, r3
- 800826a:	d90a      	bls.n	8008282 <tcp_slowtmr+0x376>
-        LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: KEEPALIVE timeout. Aborting connection to "));
-        ip_addr_debug_print_val(TCP_DEBUG, pcb->remote_ip);
-        LWIP_DEBUGF(TCP_DEBUG, ("\n"));
-
-        ++pcb_remove;
- 800826c:	f897 3027 	ldrb.w	r3, [r7, #39]	; 0x27
- 8008270:	3301      	adds	r3, #1
- 8008272:	f887 3027 	strb.w	r3, [r7, #39]	; 0x27
-        ++pcb_reset;
- 8008276:	f897 3026 	ldrb.w	r3, [r7, #38]	; 0x26
- 800827a:	3301      	adds	r3, #1
- 800827c:	f887 3026 	strb.w	r3, [r7, #38]	; 0x26
- 8008280:	e027      	b.n	80082d2 <tcp_slowtmr+0x3c6>
-      } else if ((u32_t)(tcp_ticks - pcb->tmr) >
- 8008282:	4b82      	ldr	r3, [pc, #520]	; (800848c <tcp_slowtmr+0x580>)
- 8008284:	681a      	ldr	r2, [r3, #0]
- 8008286:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 8008288:	6a1b      	ldr	r3, [r3, #32]
- 800828a:	1ad2      	subs	r2, r2, r3
-                 (pcb->keep_idle + pcb->keep_cnt_sent * TCP_KEEP_INTVL(pcb))
- 800828c:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 800828e:	f8d3 1094 	ldr.w	r1, [r3, #148]	; 0x94
- 8008292:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 8008294:	f893 309b 	ldrb.w	r3, [r3, #155]	; 0x9b
- 8008298:	4618      	mov	r0, r3
- 800829a:	4b7f      	ldr	r3, [pc, #508]	; (8008498 <tcp_slowtmr+0x58c>)
- 800829c:	fb00 f303 	mul.w	r3, r0, r3
- 80082a0:	440b      	add	r3, r1
-                 / TCP_SLOW_INTERVAL) {
- 80082a2:	497c      	ldr	r1, [pc, #496]	; (8008494 <tcp_slowtmr+0x588>)
- 80082a4:	fba1 1303 	umull	r1, r3, r1, r3
- 80082a8:	095b      	lsrs	r3, r3, #5
-      } else if ((u32_t)(tcp_ticks - pcb->tmr) >
- 80082aa:	429a      	cmp	r2, r3
- 80082ac:	d911      	bls.n	80082d2 <tcp_slowtmr+0x3c6>
-        err = tcp_keepalive(pcb);
- 80082ae:	6af8      	ldr	r0, [r7, #44]	; 0x2c
- 80082b0:	f005 f814 	bl	800d2dc <tcp_keepalive>
- 80082b4:	4603      	mov	r3, r0
- 80082b6:	f887 3025 	strb.w	r3, [r7, #37]	; 0x25
-        if (err == ERR_OK) {
- 80082ba:	f997 3025 	ldrsb.w	r3, [r7, #37]	; 0x25
- 80082be:	2b00      	cmp	r3, #0
- 80082c0:	d107      	bne.n	80082d2 <tcp_slowtmr+0x3c6>
-          pcb->keep_cnt_sent++;
- 80082c2:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 80082c4:	f893 309b 	ldrb.w	r3, [r3, #155]	; 0x9b
- 80082c8:	3301      	adds	r3, #1
- 80082ca:	b2da      	uxtb	r2, r3
- 80082cc:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 80082ce:	f883 209b 	strb.w	r2, [r3, #155]	; 0x9b
-
-    /* If this PCB has queued out of sequence data, but has been
-       inactive for too long, will drop the data (it will eventually
-       be retransmitted). */
-#if TCP_QUEUE_OOSEQ
-    if (pcb->ooseq != NULL &&
- 80082d2:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 80082d4:	6f5b      	ldr	r3, [r3, #116]	; 0x74
- 80082d6:	2b00      	cmp	r3, #0
- 80082d8:	d011      	beq.n	80082fe <tcp_slowtmr+0x3f2>
-        (tcp_ticks - pcb->tmr >= (u32_t)pcb->rto * TCP_OOSEQ_TIMEOUT)) {
- 80082da:	4b6c      	ldr	r3, [pc, #432]	; (800848c <tcp_slowtmr+0x580>)
- 80082dc:	681a      	ldr	r2, [r3, #0]
- 80082de:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 80082e0:	6a1b      	ldr	r3, [r3, #32]
- 80082e2:	1ad2      	subs	r2, r2, r3
- 80082e4:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 80082e6:	f9b3 3040 	ldrsh.w	r3, [r3, #64]	; 0x40
- 80082ea:	4619      	mov	r1, r3
- 80082ec:	460b      	mov	r3, r1
- 80082ee:	005b      	lsls	r3, r3, #1
- 80082f0:	440b      	add	r3, r1
- 80082f2:	005b      	lsls	r3, r3, #1
-    if (pcb->ooseq != NULL &&
- 80082f4:	429a      	cmp	r2, r3
- 80082f6:	d302      	bcc.n	80082fe <tcp_slowtmr+0x3f2>
-      LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_slowtmr: dropping OOSEQ queued data\n"));
-      tcp_free_ooseq(pcb);
- 80082f8:	6af8      	ldr	r0, [r7, #44]	; 0x2c
- 80082fa:	f000 fe63 	bl	8008fc4 <tcp_free_ooseq>
-    }
-#endif /* TCP_QUEUE_OOSEQ */
-
-    /* Check if this PCB has stayed too long in SYN-RCVD */
-    if (pcb->state == SYN_RCVD) {
- 80082fe:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 8008300:	7d1b      	ldrb	r3, [r3, #20]
- 8008302:	2b03      	cmp	r3, #3
- 8008304:	d10b      	bne.n	800831e <tcp_slowtmr+0x412>
-      if ((u32_t)(tcp_ticks - pcb->tmr) >
- 8008306:	4b61      	ldr	r3, [pc, #388]	; (800848c <tcp_slowtmr+0x580>)
- 8008308:	681a      	ldr	r2, [r3, #0]
- 800830a:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 800830c:	6a1b      	ldr	r3, [r3, #32]
- 800830e:	1ad3      	subs	r3, r2, r3
- 8008310:	2b28      	cmp	r3, #40	; 0x28
- 8008312:	d904      	bls.n	800831e <tcp_slowtmr+0x412>
-          TCP_SYN_RCVD_TIMEOUT / TCP_SLOW_INTERVAL) {
-        ++pcb_remove;
- 8008314:	f897 3027 	ldrb.w	r3, [r7, #39]	; 0x27
- 8008318:	3301      	adds	r3, #1
- 800831a:	f887 3027 	strb.w	r3, [r7, #39]	; 0x27
-        LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: removing pcb stuck in SYN-RCVD\n"));
-      }
-    }
-
-    /* Check if this PCB has stayed too long in LAST-ACK */
-    if (pcb->state == LAST_ACK) {
- 800831e:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 8008320:	7d1b      	ldrb	r3, [r3, #20]
- 8008322:	2b09      	cmp	r3, #9
- 8008324:	d10b      	bne.n	800833e <tcp_slowtmr+0x432>
-      if ((u32_t)(tcp_ticks - pcb->tmr) > 2 * TCP_MSL / TCP_SLOW_INTERVAL) {
- 8008326:	4b59      	ldr	r3, [pc, #356]	; (800848c <tcp_slowtmr+0x580>)
- 8008328:	681a      	ldr	r2, [r3, #0]
- 800832a:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 800832c:	6a1b      	ldr	r3, [r3, #32]
- 800832e:	1ad3      	subs	r3, r2, r3
- 8008330:	2bf0      	cmp	r3, #240	; 0xf0
- 8008332:	d904      	bls.n	800833e <tcp_slowtmr+0x432>
-        ++pcb_remove;
- 8008334:	f897 3027 	ldrb.w	r3, [r7, #39]	; 0x27
- 8008338:	3301      	adds	r3, #1
- 800833a:	f887 3027 	strb.w	r3, [r7, #39]	; 0x27
-        LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: removing pcb stuck in LAST-ACK\n"));
-      }
-    }
-
-    /* If the PCB should be removed, do it. */
-    if (pcb_remove) {
- 800833e:	f897 3027 	ldrb.w	r3, [r7, #39]	; 0x27
- 8008342:	2b00      	cmp	r3, #0
- 8008344:	d060      	beq.n	8008408 <tcp_slowtmr+0x4fc>
-      struct tcp_pcb *pcb2;
-#if LWIP_CALLBACK_API
-      tcp_err_fn err_fn = pcb->errf;
- 8008346:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 8008348:	f8d3 3090 	ldr.w	r3, [r3, #144]	; 0x90
- 800834c:	60fb      	str	r3, [r7, #12]
-#endif /* LWIP_CALLBACK_API */
-      void *err_arg;
-      enum tcp_state last_state;
-      tcp_pcb_purge(pcb);
- 800834e:	6af8      	ldr	r0, [r7, #44]	; 0x2c
- 8008350:	f000 fc7e 	bl	8008c50 <tcp_pcb_purge>
-      /* Remove PCB from tcp_active_pcbs list. */
-      if (prev != NULL) {
- 8008354:	6abb      	ldr	r3, [r7, #40]	; 0x28
- 8008356:	2b00      	cmp	r3, #0
- 8008358:	d010      	beq.n	800837c <tcp_slowtmr+0x470>
-        LWIP_ASSERT("tcp_slowtmr: middle tcp != tcp_active_pcbs", pcb != tcp_active_pcbs);
- 800835a:	4b50      	ldr	r3, [pc, #320]	; (800849c <tcp_slowtmr+0x590>)
- 800835c:	681b      	ldr	r3, [r3, #0]
- 800835e:	6afa      	ldr	r2, [r7, #44]	; 0x2c
- 8008360:	429a      	cmp	r2, r3
- 8008362:	d106      	bne.n	8008372 <tcp_slowtmr+0x466>
- 8008364:	4b4e      	ldr	r3, [pc, #312]	; (80084a0 <tcp_slowtmr+0x594>)
- 8008366:	f240 526d 	movw	r2, #1389	; 0x56d
- 800836a:	494e      	ldr	r1, [pc, #312]	; (80084a4 <tcp_slowtmr+0x598>)
- 800836c:	484e      	ldr	r0, [pc, #312]	; (80084a8 <tcp_slowtmr+0x59c>)
- 800836e:	f008 fc2b 	bl	8010bc8 <iprintf>
-        prev->next = pcb->next;
- 8008372:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 8008374:	68da      	ldr	r2, [r3, #12]
- 8008376:	6abb      	ldr	r3, [r7, #40]	; 0x28
- 8008378:	60da      	str	r2, [r3, #12]
- 800837a:	e00f      	b.n	800839c <tcp_slowtmr+0x490>
-      } else {
-        /* This PCB was the first. */
-        LWIP_ASSERT("tcp_slowtmr: first pcb == tcp_active_pcbs", tcp_active_pcbs == pcb);
- 800837c:	4b47      	ldr	r3, [pc, #284]	; (800849c <tcp_slowtmr+0x590>)
- 800837e:	681b      	ldr	r3, [r3, #0]
- 8008380:	6afa      	ldr	r2, [r7, #44]	; 0x2c
- 8008382:	429a      	cmp	r2, r3
- 8008384:	d006      	beq.n	8008394 <tcp_slowtmr+0x488>
- 8008386:	4b46      	ldr	r3, [pc, #280]	; (80084a0 <tcp_slowtmr+0x594>)
- 8008388:	f240 5271 	movw	r2, #1393	; 0x571
- 800838c:	4947      	ldr	r1, [pc, #284]	; (80084ac <tcp_slowtmr+0x5a0>)
- 800838e:	4846      	ldr	r0, [pc, #280]	; (80084a8 <tcp_slowtmr+0x59c>)
- 8008390:	f008 fc1a 	bl	8010bc8 <iprintf>
-        tcp_active_pcbs = pcb->next;
- 8008394:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 8008396:	68db      	ldr	r3, [r3, #12]
- 8008398:	4a40      	ldr	r2, [pc, #256]	; (800849c <tcp_slowtmr+0x590>)
- 800839a:	6013      	str	r3, [r2, #0]
-      }
-
-      if (pcb_reset) {
- 800839c:	f897 3026 	ldrb.w	r3, [r7, #38]	; 0x26
- 80083a0:	2b00      	cmp	r3, #0
- 80083a2:	d013      	beq.n	80083cc <tcp_slowtmr+0x4c0>
-        tcp_rst(pcb, pcb->snd_nxt, pcb->rcv_nxt, &pcb->local_ip, &pcb->remote_ip,
- 80083a4:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 80083a6:	6d18      	ldr	r0, [r3, #80]	; 0x50
- 80083a8:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 80083aa:	6a5c      	ldr	r4, [r3, #36]	; 0x24
- 80083ac:	6afd      	ldr	r5, [r7, #44]	; 0x2c
- 80083ae:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 80083b0:	3304      	adds	r3, #4
- 80083b2:	6afa      	ldr	r2, [r7, #44]	; 0x2c
- 80083b4:	8ad2      	ldrh	r2, [r2, #22]
- 80083b6:	6af9      	ldr	r1, [r7, #44]	; 0x2c
- 80083b8:	8b09      	ldrh	r1, [r1, #24]
- 80083ba:	9102      	str	r1, [sp, #8]
- 80083bc:	9201      	str	r2, [sp, #4]
- 80083be:	9300      	str	r3, [sp, #0]
- 80083c0:	462b      	mov	r3, r5
- 80083c2:	4622      	mov	r2, r4
- 80083c4:	4601      	mov	r1, r0
- 80083c6:	6af8      	ldr	r0, [r7, #44]	; 0x2c
- 80083c8:	f004 fed4 	bl	800d174 <tcp_rst>
-                pcb->local_port, pcb->remote_port);
-      }
-
-      err_arg = pcb->callback_arg;
- 80083cc:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 80083ce:	691b      	ldr	r3, [r3, #16]
- 80083d0:	60bb      	str	r3, [r7, #8]
-      last_state = pcb->state;
- 80083d2:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 80083d4:	7d1b      	ldrb	r3, [r3, #20]
- 80083d6:	71fb      	strb	r3, [r7, #7]
-      pcb2 = pcb;
- 80083d8:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 80083da:	603b      	str	r3, [r7, #0]
-      pcb = pcb->next;
- 80083dc:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 80083de:	68db      	ldr	r3, [r3, #12]
- 80083e0:	62fb      	str	r3, [r7, #44]	; 0x2c
-      tcp_free(pcb2);
- 80083e2:	6838      	ldr	r0, [r7, #0]
- 80083e4:	f7ff f896 	bl	8007514 <tcp_free>
-
-      tcp_active_pcbs_changed = 0;
- 80083e8:	4b31      	ldr	r3, [pc, #196]	; (80084b0 <tcp_slowtmr+0x5a4>)
- 80083ea:	2200      	movs	r2, #0
- 80083ec:	701a      	strb	r2, [r3, #0]
-      TCP_EVENT_ERR(last_state, err_fn, err_arg, ERR_ABRT);
- 80083ee:	68fb      	ldr	r3, [r7, #12]
- 80083f0:	2b00      	cmp	r3, #0
- 80083f2:	d004      	beq.n	80083fe <tcp_slowtmr+0x4f2>
- 80083f4:	68fb      	ldr	r3, [r7, #12]
- 80083f6:	f06f 010c 	mvn.w	r1, #12
- 80083fa:	68b8      	ldr	r0, [r7, #8]
- 80083fc:	4798      	blx	r3
-      if (tcp_active_pcbs_changed) {
- 80083fe:	4b2c      	ldr	r3, [pc, #176]	; (80084b0 <tcp_slowtmr+0x5a4>)
- 8008400:	781b      	ldrb	r3, [r3, #0]
- 8008402:	2b00      	cmp	r3, #0
- 8008404:	d037      	beq.n	8008476 <tcp_slowtmr+0x56a>
-        goto tcp_slowtmr_start;
- 8008406:	e592      	b.n	8007f2e <tcp_slowtmr+0x22>
-      }
-    } else {
-      /* get the 'next' element now and work with 'prev' below (in case of abort) */
-      prev = pcb;
- 8008408:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 800840a:	62bb      	str	r3, [r7, #40]	; 0x28
-      pcb = pcb->next;
- 800840c:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 800840e:	68db      	ldr	r3, [r3, #12]
- 8008410:	62fb      	str	r3, [r7, #44]	; 0x2c
-
-      /* We check if we should poll the connection. */
-      ++prev->polltmr;
- 8008412:	6abb      	ldr	r3, [r7, #40]	; 0x28
- 8008414:	7f1b      	ldrb	r3, [r3, #28]
- 8008416:	3301      	adds	r3, #1
- 8008418:	b2da      	uxtb	r2, r3
- 800841a:	6abb      	ldr	r3, [r7, #40]	; 0x28
- 800841c:	771a      	strb	r2, [r3, #28]
-      if (prev->polltmr >= prev->pollinterval) {
- 800841e:	6abb      	ldr	r3, [r7, #40]	; 0x28
- 8008420:	7f1a      	ldrb	r2, [r3, #28]
- 8008422:	6abb      	ldr	r3, [r7, #40]	; 0x28
- 8008424:	7f5b      	ldrb	r3, [r3, #29]
- 8008426:	429a      	cmp	r2, r3
- 8008428:	d325      	bcc.n	8008476 <tcp_slowtmr+0x56a>
-        prev->polltmr = 0;
- 800842a:	6abb      	ldr	r3, [r7, #40]	; 0x28
- 800842c:	2200      	movs	r2, #0
- 800842e:	771a      	strb	r2, [r3, #28]
-        LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: polling application\n"));
-        tcp_active_pcbs_changed = 0;
- 8008430:	4b1f      	ldr	r3, [pc, #124]	; (80084b0 <tcp_slowtmr+0x5a4>)
- 8008432:	2200      	movs	r2, #0
- 8008434:	701a      	strb	r2, [r3, #0]
-        TCP_EVENT_POLL(prev, err);
- 8008436:	6abb      	ldr	r3, [r7, #40]	; 0x28
- 8008438:	f8d3 308c 	ldr.w	r3, [r3, #140]	; 0x8c
- 800843c:	2b00      	cmp	r3, #0
- 800843e:	d00b      	beq.n	8008458 <tcp_slowtmr+0x54c>
- 8008440:	6abb      	ldr	r3, [r7, #40]	; 0x28
- 8008442:	f8d3 308c 	ldr.w	r3, [r3, #140]	; 0x8c
- 8008446:	6aba      	ldr	r2, [r7, #40]	; 0x28
- 8008448:	6912      	ldr	r2, [r2, #16]
- 800844a:	6ab9      	ldr	r1, [r7, #40]	; 0x28
- 800844c:	4610      	mov	r0, r2
- 800844e:	4798      	blx	r3
- 8008450:	4603      	mov	r3, r0
- 8008452:	f887 3025 	strb.w	r3, [r7, #37]	; 0x25
- 8008456:	e002      	b.n	800845e <tcp_slowtmr+0x552>
- 8008458:	2300      	movs	r3, #0
- 800845a:	f887 3025 	strb.w	r3, [r7, #37]	; 0x25
-        if (tcp_active_pcbs_changed) {
- 800845e:	4b14      	ldr	r3, [pc, #80]	; (80084b0 <tcp_slowtmr+0x5a4>)
- 8008460:	781b      	ldrb	r3, [r3, #0]
- 8008462:	2b00      	cmp	r3, #0
- 8008464:	d000      	beq.n	8008468 <tcp_slowtmr+0x55c>
-          goto tcp_slowtmr_start;
- 8008466:	e562      	b.n	8007f2e <tcp_slowtmr+0x22>
-        }
-        /* if err == ERR_ABRT, 'prev' is already deallocated */
-        if (err == ERR_OK) {
- 8008468:	f997 3025 	ldrsb.w	r3, [r7, #37]	; 0x25
- 800846c:	2b00      	cmp	r3, #0
- 800846e:	d102      	bne.n	8008476 <tcp_slowtmr+0x56a>
-          tcp_output(prev);
- 8008470:	6ab8      	ldr	r0, [r7, #40]	; 0x28
- 8008472:	f004 f8bf 	bl	800c5f4 <tcp_output>
-  while (pcb != NULL) {
- 8008476:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 8008478:	2b00      	cmp	r3, #0
- 800847a:	f47f ad5e 	bne.w	8007f3a <tcp_slowtmr+0x2e>
-    }
-  }
-
-
-  /* Steps through all of the TIME-WAIT PCBs. */
-  prev = NULL;
- 800847e:	2300      	movs	r3, #0
- 8008480:	62bb      	str	r3, [r7, #40]	; 0x28
-  pcb = tcp_tw_pcbs;
- 8008482:	4b0c      	ldr	r3, [pc, #48]	; (80084b4 <tcp_slowtmr+0x5a8>)
- 8008484:	681b      	ldr	r3, [r3, #0]
- 8008486:	62fb      	str	r3, [r7, #44]	; 0x2c
-  while (pcb != NULL) {
- 8008488:	e069      	b.n	800855e <tcp_slowtmr+0x652>
- 800848a:	bf00      	nop
- 800848c:	24007b6c 	.word	0x24007b6c
- 8008490:	000a4cb8 	.word	0x000a4cb8
- 8008494:	10624dd3 	.word	0x10624dd3
- 8008498:	000124f8 	.word	0x000124f8
- 800849c:	24007b78 	.word	0x24007b78
- 80084a0:	08012a08 	.word	0x08012a08
- 80084a4:	08012e40 	.word	0x08012e40
- 80084a8:	08012a4c 	.word	0x08012a4c
- 80084ac:	08012e6c 	.word	0x08012e6c
- 80084b0:	24007b80 	.word	0x24007b80
- 80084b4:	24007b7c 	.word	0x24007b7c
-    LWIP_ASSERT("tcp_slowtmr: TIME-WAIT pcb->state == TIME-WAIT", pcb->state == TIME_WAIT);
- 80084b8:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 80084ba:	7d1b      	ldrb	r3, [r3, #20]
- 80084bc:	2b0a      	cmp	r3, #10
- 80084be:	d006      	beq.n	80084ce <tcp_slowtmr+0x5c2>
- 80084c0:	4b2b      	ldr	r3, [pc, #172]	; (8008570 <tcp_slowtmr+0x664>)
- 80084c2:	f240 52a1 	movw	r2, #1441	; 0x5a1
- 80084c6:	492b      	ldr	r1, [pc, #172]	; (8008574 <tcp_slowtmr+0x668>)
- 80084c8:	482b      	ldr	r0, [pc, #172]	; (8008578 <tcp_slowtmr+0x66c>)
- 80084ca:	f008 fb7d 	bl	8010bc8 <iprintf>
-    pcb_remove = 0;
- 80084ce:	2300      	movs	r3, #0
- 80084d0:	f887 3027 	strb.w	r3, [r7, #39]	; 0x27
-
-    /* Check if this PCB has stayed long enough in TIME-WAIT */
-    if ((u32_t)(tcp_ticks - pcb->tmr) > 2 * TCP_MSL / TCP_SLOW_INTERVAL) {
- 80084d4:	4b29      	ldr	r3, [pc, #164]	; (800857c <tcp_slowtmr+0x670>)
- 80084d6:	681a      	ldr	r2, [r3, #0]
- 80084d8:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 80084da:	6a1b      	ldr	r3, [r3, #32]
- 80084dc:	1ad3      	subs	r3, r2, r3
- 80084de:	2bf0      	cmp	r3, #240	; 0xf0
- 80084e0:	d904      	bls.n	80084ec <tcp_slowtmr+0x5e0>
-      ++pcb_remove;
- 80084e2:	f897 3027 	ldrb.w	r3, [r7, #39]	; 0x27
- 80084e6:	3301      	adds	r3, #1
- 80084e8:	f887 3027 	strb.w	r3, [r7, #39]	; 0x27
-    }
-
-    /* If the PCB should be removed, do it. */
-    if (pcb_remove) {
- 80084ec:	f897 3027 	ldrb.w	r3, [r7, #39]	; 0x27
- 80084f0:	2b00      	cmp	r3, #0
- 80084f2:	d02f      	beq.n	8008554 <tcp_slowtmr+0x648>
-      struct tcp_pcb *pcb2;
-      tcp_pcb_purge(pcb);
- 80084f4:	6af8      	ldr	r0, [r7, #44]	; 0x2c
- 80084f6:	f000 fbab 	bl	8008c50 <tcp_pcb_purge>
-      /* Remove PCB from tcp_tw_pcbs list. */
-      if (prev != NULL) {
- 80084fa:	6abb      	ldr	r3, [r7, #40]	; 0x28
- 80084fc:	2b00      	cmp	r3, #0
- 80084fe:	d010      	beq.n	8008522 <tcp_slowtmr+0x616>
-        LWIP_ASSERT("tcp_slowtmr: middle tcp != tcp_tw_pcbs", pcb != tcp_tw_pcbs);
- 8008500:	4b1f      	ldr	r3, [pc, #124]	; (8008580 <tcp_slowtmr+0x674>)
- 8008502:	681b      	ldr	r3, [r3, #0]
- 8008504:	6afa      	ldr	r2, [r7, #44]	; 0x2c
- 8008506:	429a      	cmp	r2, r3
- 8008508:	d106      	bne.n	8008518 <tcp_slowtmr+0x60c>
- 800850a:	4b19      	ldr	r3, [pc, #100]	; (8008570 <tcp_slowtmr+0x664>)
- 800850c:	f240 52af 	movw	r2, #1455	; 0x5af
- 8008510:	491c      	ldr	r1, [pc, #112]	; (8008584 <tcp_slowtmr+0x678>)
- 8008512:	4819      	ldr	r0, [pc, #100]	; (8008578 <tcp_slowtmr+0x66c>)
- 8008514:	f008 fb58 	bl	8010bc8 <iprintf>
-        prev->next = pcb->next;
- 8008518:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 800851a:	68da      	ldr	r2, [r3, #12]
- 800851c:	6abb      	ldr	r3, [r7, #40]	; 0x28
- 800851e:	60da      	str	r2, [r3, #12]
- 8008520:	e00f      	b.n	8008542 <tcp_slowtmr+0x636>
-      } else {
-        /* This PCB was the first. */
-        LWIP_ASSERT("tcp_slowtmr: first pcb == tcp_tw_pcbs", tcp_tw_pcbs == pcb);
- 8008522:	4b17      	ldr	r3, [pc, #92]	; (8008580 <tcp_slowtmr+0x674>)
- 8008524:	681b      	ldr	r3, [r3, #0]
- 8008526:	6afa      	ldr	r2, [r7, #44]	; 0x2c
- 8008528:	429a      	cmp	r2, r3
- 800852a:	d006      	beq.n	800853a <tcp_slowtmr+0x62e>
- 800852c:	4b10      	ldr	r3, [pc, #64]	; (8008570 <tcp_slowtmr+0x664>)
- 800852e:	f240 52b3 	movw	r2, #1459	; 0x5b3
- 8008532:	4915      	ldr	r1, [pc, #84]	; (8008588 <tcp_slowtmr+0x67c>)
- 8008534:	4810      	ldr	r0, [pc, #64]	; (8008578 <tcp_slowtmr+0x66c>)
- 8008536:	f008 fb47 	bl	8010bc8 <iprintf>
-        tcp_tw_pcbs = pcb->next;
- 800853a:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 800853c:	68db      	ldr	r3, [r3, #12]
- 800853e:	4a10      	ldr	r2, [pc, #64]	; (8008580 <tcp_slowtmr+0x674>)
- 8008540:	6013      	str	r3, [r2, #0]
-      }
-      pcb2 = pcb;
- 8008542:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 8008544:	61fb      	str	r3, [r7, #28]
-      pcb = pcb->next;
- 8008546:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 8008548:	68db      	ldr	r3, [r3, #12]
- 800854a:	62fb      	str	r3, [r7, #44]	; 0x2c
-      tcp_free(pcb2);
- 800854c:	69f8      	ldr	r0, [r7, #28]
- 800854e:	f7fe ffe1 	bl	8007514 <tcp_free>
- 8008552:	e004      	b.n	800855e <tcp_slowtmr+0x652>
-    } else {
-      prev = pcb;
- 8008554:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 8008556:	62bb      	str	r3, [r7, #40]	; 0x28
-      pcb = pcb->next;
- 8008558:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 800855a:	68db      	ldr	r3, [r3, #12]
- 800855c:	62fb      	str	r3, [r7, #44]	; 0x2c
-  while (pcb != NULL) {
- 800855e:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 8008560:	2b00      	cmp	r3, #0
- 8008562:	d1a9      	bne.n	80084b8 <tcp_slowtmr+0x5ac>
-    }
-  }
-}
- 8008564:	bf00      	nop
- 8008566:	bf00      	nop
- 8008568:	3730      	adds	r7, #48	; 0x30
- 800856a:	46bd      	mov	sp, r7
- 800856c:	bdb0      	pop	{r4, r5, r7, pc}
- 800856e:	bf00      	nop
- 8008570:	08012a08 	.word	0x08012a08
- 8008574:	08012e98 	.word	0x08012e98
- 8008578:	08012a4c 	.word	0x08012a4c
- 800857c:	24007b6c 	.word	0x24007b6c
- 8008580:	24007b7c 	.word	0x24007b7c
- 8008584:	08012ec8 	.word	0x08012ec8
- 8008588:	08012ef0 	.word	0x08012ef0
-
-0800858c <tcp_fasttmr>:
- *
- * Automatically called from tcp_tmr().
- */
-void
-tcp_fasttmr(void)
-{
- 800858c:	b580      	push	{r7, lr}
- 800858e:	b082      	sub	sp, #8
- 8008590:	af00      	add	r7, sp, #0
-  struct tcp_pcb *pcb;
-
-  ++tcp_timer_ctr;
- 8008592:	4b2d      	ldr	r3, [pc, #180]	; (8008648 <tcp_fasttmr+0xbc>)
- 8008594:	781b      	ldrb	r3, [r3, #0]
- 8008596:	3301      	adds	r3, #1
- 8008598:	b2da      	uxtb	r2, r3
- 800859a:	4b2b      	ldr	r3, [pc, #172]	; (8008648 <tcp_fasttmr+0xbc>)
- 800859c:	701a      	strb	r2, [r3, #0]
-
-tcp_fasttmr_start:
-  pcb = tcp_active_pcbs;
- 800859e:	4b2b      	ldr	r3, [pc, #172]	; (800864c <tcp_fasttmr+0xc0>)
- 80085a0:	681b      	ldr	r3, [r3, #0]
- 80085a2:	607b      	str	r3, [r7, #4]
-
-  while (pcb != NULL) {
- 80085a4:	e048      	b.n	8008638 <tcp_fasttmr+0xac>
-    if (pcb->last_timer != tcp_timer_ctr) {
- 80085a6:	687b      	ldr	r3, [r7, #4]
- 80085a8:	7f9a      	ldrb	r2, [r3, #30]
- 80085aa:	4b27      	ldr	r3, [pc, #156]	; (8008648 <tcp_fasttmr+0xbc>)
- 80085ac:	781b      	ldrb	r3, [r3, #0]
- 80085ae:	429a      	cmp	r2, r3
- 80085b0:	d03f      	beq.n	8008632 <tcp_fasttmr+0xa6>
-      struct tcp_pcb *next;
-      pcb->last_timer = tcp_timer_ctr;
- 80085b2:	4b25      	ldr	r3, [pc, #148]	; (8008648 <tcp_fasttmr+0xbc>)
- 80085b4:	781a      	ldrb	r2, [r3, #0]
- 80085b6:	687b      	ldr	r3, [r7, #4]
- 80085b8:	779a      	strb	r2, [r3, #30]
-      /* send delayed ACKs */
-      if (pcb->flags & TF_ACK_DELAY) {
- 80085ba:	687b      	ldr	r3, [r7, #4]
- 80085bc:	8b5b      	ldrh	r3, [r3, #26]
- 80085be:	f003 0301 	and.w	r3, r3, #1
- 80085c2:	2b00      	cmp	r3, #0
- 80085c4:	d010      	beq.n	80085e8 <tcp_fasttmr+0x5c>
-        LWIP_DEBUGF(TCP_DEBUG, ("tcp_fasttmr: delayed ACK\n"));
-        tcp_ack_now(pcb);
- 80085c6:	687b      	ldr	r3, [r7, #4]
- 80085c8:	8b5b      	ldrh	r3, [r3, #26]
- 80085ca:	f043 0302 	orr.w	r3, r3, #2
- 80085ce:	b29a      	uxth	r2, r3
- 80085d0:	687b      	ldr	r3, [r7, #4]
- 80085d2:	835a      	strh	r2, [r3, #26]
-        tcp_output(pcb);
- 80085d4:	6878      	ldr	r0, [r7, #4]
- 80085d6:	f004 f80d 	bl	800c5f4 <tcp_output>
-        tcp_clear_flags(pcb, TF_ACK_DELAY | TF_ACK_NOW);
- 80085da:	687b      	ldr	r3, [r7, #4]
- 80085dc:	8b5b      	ldrh	r3, [r3, #26]
- 80085de:	f023 0303 	bic.w	r3, r3, #3
- 80085e2:	b29a      	uxth	r2, r3
- 80085e4:	687b      	ldr	r3, [r7, #4]
- 80085e6:	835a      	strh	r2, [r3, #26]
-      }
-      /* send pending FIN */
-      if (pcb->flags & TF_CLOSEPEND) {
- 80085e8:	687b      	ldr	r3, [r7, #4]
- 80085ea:	8b5b      	ldrh	r3, [r3, #26]
- 80085ec:	f003 0308 	and.w	r3, r3, #8
- 80085f0:	2b00      	cmp	r3, #0
- 80085f2:	d009      	beq.n	8008608 <tcp_fasttmr+0x7c>
-        LWIP_DEBUGF(TCP_DEBUG, ("tcp_fasttmr: pending FIN\n"));
-        tcp_clear_flags(pcb, TF_CLOSEPEND);
- 80085f4:	687b      	ldr	r3, [r7, #4]
- 80085f6:	8b5b      	ldrh	r3, [r3, #26]
- 80085f8:	f023 0308 	bic.w	r3, r3, #8
- 80085fc:	b29a      	uxth	r2, r3
- 80085fe:	687b      	ldr	r3, [r7, #4]
- 8008600:	835a      	strh	r2, [r3, #26]
-        tcp_close_shutdown_fin(pcb);
- 8008602:	6878      	ldr	r0, [r7, #4]
- 8008604:	f7ff f91a 	bl	800783c <tcp_close_shutdown_fin>
-      }
-
-      next = pcb->next;
- 8008608:	687b      	ldr	r3, [r7, #4]
- 800860a:	68db      	ldr	r3, [r3, #12]
- 800860c:	603b      	str	r3, [r7, #0]
-
-      /* If there is data which was previously "refused" by upper layer */
-      if (pcb->refused_data != NULL) {
- 800860e:	687b      	ldr	r3, [r7, #4]
- 8008610:	6f9b      	ldr	r3, [r3, #120]	; 0x78
- 8008612:	2b00      	cmp	r3, #0
- 8008614:	d00a      	beq.n	800862c <tcp_fasttmr+0xa0>
-        tcp_active_pcbs_changed = 0;
- 8008616:	4b0e      	ldr	r3, [pc, #56]	; (8008650 <tcp_fasttmr+0xc4>)
- 8008618:	2200      	movs	r2, #0
- 800861a:	701a      	strb	r2, [r3, #0]
-        tcp_process_refused_data(pcb);
- 800861c:	6878      	ldr	r0, [r7, #4]
- 800861e:	f000 f819 	bl	8008654 <tcp_process_refused_data>
-        if (tcp_active_pcbs_changed) {
- 8008622:	4b0b      	ldr	r3, [pc, #44]	; (8008650 <tcp_fasttmr+0xc4>)
- 8008624:	781b      	ldrb	r3, [r3, #0]
- 8008626:	2b00      	cmp	r3, #0
- 8008628:	d000      	beq.n	800862c <tcp_fasttmr+0xa0>
-          /* application callback has changed the pcb list: restart the loop */
-          goto tcp_fasttmr_start;
- 800862a:	e7b8      	b.n	800859e <tcp_fasttmr+0x12>
-        }
-      }
-      pcb = next;
- 800862c:	683b      	ldr	r3, [r7, #0]
- 800862e:	607b      	str	r3, [r7, #4]
- 8008630:	e002      	b.n	8008638 <tcp_fasttmr+0xac>
-    } else {
-      pcb = pcb->next;
- 8008632:	687b      	ldr	r3, [r7, #4]
- 8008634:	68db      	ldr	r3, [r3, #12]
- 8008636:	607b      	str	r3, [r7, #4]
-  while (pcb != NULL) {
- 8008638:	687b      	ldr	r3, [r7, #4]
- 800863a:	2b00      	cmp	r3, #0
- 800863c:	d1b3      	bne.n	80085a6 <tcp_fasttmr+0x1a>
-    }
-  }
-}
- 800863e:	bf00      	nop
- 8008640:	bf00      	nop
- 8008642:	3708      	adds	r7, #8
- 8008644:	46bd      	mov	sp, r7
- 8008646:	bd80      	pop	{r7, pc}
- 8008648:	24007b82 	.word	0x24007b82
- 800864c:	24007b78 	.word	0x24007b78
- 8008650:	24007b80 	.word	0x24007b80
-
-08008654 <tcp_process_refused_data>:
-}
-
-/** Pass pcb->refused_data to the recv callback */
-err_t
-tcp_process_refused_data(struct tcp_pcb *pcb)
-{
- 8008654:	b590      	push	{r4, r7, lr}
- 8008656:	b085      	sub	sp, #20
- 8008658:	af00      	add	r7, sp, #0
- 800865a:	6078      	str	r0, [r7, #4]
-#if TCP_QUEUE_OOSEQ && LWIP_WND_SCALE
-  struct pbuf *rest;
-#endif /* TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */
-
-  LWIP_ERROR("tcp_process_refused_data: invalid pcb", pcb != NULL, return ERR_ARG);
- 800865c:	687b      	ldr	r3, [r7, #4]
- 800865e:	2b00      	cmp	r3, #0
- 8008660:	d109      	bne.n	8008676 <tcp_process_refused_data+0x22>
- 8008662:	4b37      	ldr	r3, [pc, #220]	; (8008740 <tcp_process_refused_data+0xec>)
- 8008664:	f240 6209 	movw	r2, #1545	; 0x609
- 8008668:	4936      	ldr	r1, [pc, #216]	; (8008744 <tcp_process_refused_data+0xf0>)
- 800866a:	4837      	ldr	r0, [pc, #220]	; (8008748 <tcp_process_refused_data+0xf4>)
- 800866c:	f008 faac 	bl	8010bc8 <iprintf>
- 8008670:	f06f 030f 	mvn.w	r3, #15
- 8008674:	e060      	b.n	8008738 <tcp_process_refused_data+0xe4>
-#if TCP_QUEUE_OOSEQ && LWIP_WND_SCALE
-  while (pcb->refused_data != NULL)
-#endif /* TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */
-  {
-    err_t err;
-    u8_t refused_flags = pcb->refused_data->flags;
- 8008676:	687b      	ldr	r3, [r7, #4]
- 8008678:	6f9b      	ldr	r3, [r3, #120]	; 0x78
- 800867a:	7b5b      	ldrb	r3, [r3, #13]
- 800867c:	73bb      	strb	r3, [r7, #14]
-    /* set pcb->refused_data to NULL in case the callback frees it and then
-       closes the pcb */
-    struct pbuf *refused_data = pcb->refused_data;
- 800867e:	687b      	ldr	r3, [r7, #4]
- 8008680:	6f9b      	ldr	r3, [r3, #120]	; 0x78
- 8008682:	60bb      	str	r3, [r7, #8]
-#if TCP_QUEUE_OOSEQ && LWIP_WND_SCALE
-    pbuf_split_64k(refused_data, &rest);
-    pcb->refused_data = rest;
-#else /* TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */
-    pcb->refused_data = NULL;
- 8008684:	687b      	ldr	r3, [r7, #4]
- 8008686:	2200      	movs	r2, #0
- 8008688:	679a      	str	r2, [r3, #120]	; 0x78
-#endif /* TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */
-    /* Notify again application with data previously received. */
-    LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: notify kept packet\n"));
-    TCP_EVENT_RECV(pcb, refused_data, ERR_OK, err);
- 800868a:	687b      	ldr	r3, [r7, #4]
- 800868c:	f8d3 3084 	ldr.w	r3, [r3, #132]	; 0x84
- 8008690:	2b00      	cmp	r3, #0
- 8008692:	d00b      	beq.n	80086ac <tcp_process_refused_data+0x58>
- 8008694:	687b      	ldr	r3, [r7, #4]
- 8008696:	f8d3 4084 	ldr.w	r4, [r3, #132]	; 0x84
- 800869a:	687b      	ldr	r3, [r7, #4]
- 800869c:	6918      	ldr	r0, [r3, #16]
- 800869e:	2300      	movs	r3, #0
- 80086a0:	68ba      	ldr	r2, [r7, #8]
- 80086a2:	6879      	ldr	r1, [r7, #4]
- 80086a4:	47a0      	blx	r4
- 80086a6:	4603      	mov	r3, r0
- 80086a8:	73fb      	strb	r3, [r7, #15]
- 80086aa:	e007      	b.n	80086bc <tcp_process_refused_data+0x68>
- 80086ac:	2300      	movs	r3, #0
- 80086ae:	68ba      	ldr	r2, [r7, #8]
- 80086b0:	6879      	ldr	r1, [r7, #4]
- 80086b2:	2000      	movs	r0, #0
- 80086b4:	f000 f8a4 	bl	8008800 <tcp_recv_null>
- 80086b8:	4603      	mov	r3, r0
- 80086ba:	73fb      	strb	r3, [r7, #15]
-    if (err == ERR_OK) {
- 80086bc:	f997 300f 	ldrsb.w	r3, [r7, #15]
- 80086c0:	2b00      	cmp	r3, #0
- 80086c2:	d12a      	bne.n	800871a <tcp_process_refused_data+0xc6>
-      /* did refused_data include a FIN? */
-      if ((refused_flags & PBUF_FLAG_TCP_FIN)
- 80086c4:	7bbb      	ldrb	r3, [r7, #14]
- 80086c6:	f003 0320 	and.w	r3, r3, #32
- 80086ca:	2b00      	cmp	r3, #0
- 80086cc:	d033      	beq.n	8008736 <tcp_process_refused_data+0xe2>
-          && (rest == NULL)
-#endif /* TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */
-         ) {
-        /* correct rcv_wnd as the application won't call tcp_recved()
-           for the FIN's seqno */
-        if (pcb->rcv_wnd != TCP_WND_MAX(pcb)) {
- 80086ce:	687b      	ldr	r3, [r7, #4]
- 80086d0:	8d1b      	ldrh	r3, [r3, #40]	; 0x28
- 80086d2:	f5b3 6f06 	cmp.w	r3, #2144	; 0x860
- 80086d6:	d005      	beq.n	80086e4 <tcp_process_refused_data+0x90>
-          pcb->rcv_wnd++;
- 80086d8:	687b      	ldr	r3, [r7, #4]
- 80086da:	8d1b      	ldrh	r3, [r3, #40]	; 0x28
- 80086dc:	3301      	adds	r3, #1
- 80086de:	b29a      	uxth	r2, r3
- 80086e0:	687b      	ldr	r3, [r7, #4]
- 80086e2:	851a      	strh	r2, [r3, #40]	; 0x28
-        }
-        TCP_EVENT_CLOSED(pcb, err);
- 80086e4:	687b      	ldr	r3, [r7, #4]
- 80086e6:	f8d3 3084 	ldr.w	r3, [r3, #132]	; 0x84
- 80086ea:	2b00      	cmp	r3, #0
- 80086ec:	d00b      	beq.n	8008706 <tcp_process_refused_data+0xb2>
- 80086ee:	687b      	ldr	r3, [r7, #4]
- 80086f0:	f8d3 4084 	ldr.w	r4, [r3, #132]	; 0x84
- 80086f4:	687b      	ldr	r3, [r7, #4]
- 80086f6:	6918      	ldr	r0, [r3, #16]
- 80086f8:	2300      	movs	r3, #0
- 80086fa:	2200      	movs	r2, #0
- 80086fc:	6879      	ldr	r1, [r7, #4]
- 80086fe:	47a0      	blx	r4
- 8008700:	4603      	mov	r3, r0
- 8008702:	73fb      	strb	r3, [r7, #15]
- 8008704:	e001      	b.n	800870a <tcp_process_refused_data+0xb6>
- 8008706:	2300      	movs	r3, #0
- 8008708:	73fb      	strb	r3, [r7, #15]
-        if (err == ERR_ABRT) {
- 800870a:	f997 300f 	ldrsb.w	r3, [r7, #15]
- 800870e:	f113 0f0d 	cmn.w	r3, #13
- 8008712:	d110      	bne.n	8008736 <tcp_process_refused_data+0xe2>
-          return ERR_ABRT;
- 8008714:	f06f 030c 	mvn.w	r3, #12
- 8008718:	e00e      	b.n	8008738 <tcp_process_refused_data+0xe4>
-        }
-      }
-    } else if (err == ERR_ABRT) {
- 800871a:	f997 300f 	ldrsb.w	r3, [r7, #15]
- 800871e:	f113 0f0d 	cmn.w	r3, #13
- 8008722:	d102      	bne.n	800872a <tcp_process_refused_data+0xd6>
-      /* if err == ERR_ABRT, 'pcb' is already deallocated */
-      /* Drop incoming packets because pcb is "full" (only if the incoming
-         segment contains data). */
-      LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: drop incoming packets, because pcb is \"full\"\n"));
-      return ERR_ABRT;
- 8008724:	f06f 030c 	mvn.w	r3, #12
- 8008728:	e006      	b.n	8008738 <tcp_process_refused_data+0xe4>
-#if TCP_QUEUE_OOSEQ && LWIP_WND_SCALE
-      if (rest != NULL) {
-        pbuf_cat(refused_data, rest);
-      }
-#endif /* TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */
-      pcb->refused_data = refused_data;
- 800872a:	687b      	ldr	r3, [r7, #4]
- 800872c:	68ba      	ldr	r2, [r7, #8]
- 800872e:	679a      	str	r2, [r3, #120]	; 0x78
-      return ERR_INPROGRESS;
- 8008730:	f06f 0304 	mvn.w	r3, #4
- 8008734:	e000      	b.n	8008738 <tcp_process_refused_data+0xe4>
-    }
-  }
-  return ERR_OK;
- 8008736:	2300      	movs	r3, #0
-}
- 8008738:	4618      	mov	r0, r3
- 800873a:	3714      	adds	r7, #20
- 800873c:	46bd      	mov	sp, r7
- 800873e:	bd90      	pop	{r4, r7, pc}
- 8008740:	08012a08 	.word	0x08012a08
- 8008744:	08012f18 	.word	0x08012f18
- 8008748:	08012a4c 	.word	0x08012a4c
-
-0800874c <tcp_segs_free>:
- *
- * @param seg tcp_seg list of TCP segments to free
- */
-void
-tcp_segs_free(struct tcp_seg *seg)
-{
- 800874c:	b580      	push	{r7, lr}
- 800874e:	b084      	sub	sp, #16
- 8008750:	af00      	add	r7, sp, #0
- 8008752:	6078      	str	r0, [r7, #4]
-  while (seg != NULL) {
- 8008754:	e007      	b.n	8008766 <tcp_segs_free+0x1a>
-    struct tcp_seg *next = seg->next;
- 8008756:	687b      	ldr	r3, [r7, #4]
- 8008758:	681b      	ldr	r3, [r3, #0]
- 800875a:	60fb      	str	r3, [r7, #12]
-    tcp_seg_free(seg);
- 800875c:	6878      	ldr	r0, [r7, #4]
- 800875e:	f000 f80a 	bl	8008776 <tcp_seg_free>
-    seg = next;
- 8008762:	68fb      	ldr	r3, [r7, #12]
- 8008764:	607b      	str	r3, [r7, #4]
-  while (seg != NULL) {
- 8008766:	687b      	ldr	r3, [r7, #4]
- 8008768:	2b00      	cmp	r3, #0
- 800876a:	d1f4      	bne.n	8008756 <tcp_segs_free+0xa>
-  }
-}
- 800876c:	bf00      	nop
- 800876e:	bf00      	nop
- 8008770:	3710      	adds	r7, #16
- 8008772:	46bd      	mov	sp, r7
- 8008774:	bd80      	pop	{r7, pc}
-
-08008776 <tcp_seg_free>:
- *
- * @param seg single tcp_seg to free
- */
-void
-tcp_seg_free(struct tcp_seg *seg)
-{
- 8008776:	b580      	push	{r7, lr}
- 8008778:	b082      	sub	sp, #8
- 800877a:	af00      	add	r7, sp, #0
- 800877c:	6078      	str	r0, [r7, #4]
-  if (seg != NULL) {
- 800877e:	687b      	ldr	r3, [r7, #4]
- 8008780:	2b00      	cmp	r3, #0
- 8008782:	d00c      	beq.n	800879e <tcp_seg_free+0x28>
-    if (seg->p != NULL) {
- 8008784:	687b      	ldr	r3, [r7, #4]
- 8008786:	685b      	ldr	r3, [r3, #4]
- 8008788:	2b00      	cmp	r3, #0
- 800878a:	d004      	beq.n	8008796 <tcp_seg_free+0x20>
-      pbuf_free(seg->p);
- 800878c:	687b      	ldr	r3, [r7, #4]
- 800878e:	685b      	ldr	r3, [r3, #4]
- 8008790:	4618      	mov	r0, r3
- 8008792:	f7fe fc1f 	bl	8006fd4 <pbuf_free>
-#if TCP_DEBUG
-      seg->p = NULL;
-#endif /* TCP_DEBUG */
-    }
-    memp_free(MEMP_TCP_SEG, seg);
- 8008796:	6879      	ldr	r1, [r7, #4]
- 8008798:	2003      	movs	r0, #3
- 800879a:	f7fd fcaf 	bl	80060fc <memp_free>
-  }
-}
- 800879e:	bf00      	nop
- 80087a0:	3708      	adds	r7, #8
- 80087a2:	46bd      	mov	sp, r7
- 80087a4:	bd80      	pop	{r7, pc}
-	...
-
-080087a8 <tcp_seg_copy>:
- * @param seg the old tcp_seg
- * @return a copy of seg
- */
-struct tcp_seg *
-tcp_seg_copy(struct tcp_seg *seg)
-{
- 80087a8:	b580      	push	{r7, lr}
- 80087aa:	b084      	sub	sp, #16
- 80087ac:	af00      	add	r7, sp, #0
- 80087ae:	6078      	str	r0, [r7, #4]
-  struct tcp_seg *cseg;
-
-  LWIP_ASSERT("tcp_seg_copy: invalid seg", seg != NULL);
- 80087b0:	687b      	ldr	r3, [r7, #4]
- 80087b2:	2b00      	cmp	r3, #0
- 80087b4:	d106      	bne.n	80087c4 <tcp_seg_copy+0x1c>
- 80087b6:	4b0f      	ldr	r3, [pc, #60]	; (80087f4 <tcp_seg_copy+0x4c>)
- 80087b8:	f240 6282 	movw	r2, #1666	; 0x682
- 80087bc:	490e      	ldr	r1, [pc, #56]	; (80087f8 <tcp_seg_copy+0x50>)
- 80087be:	480f      	ldr	r0, [pc, #60]	; (80087fc <tcp_seg_copy+0x54>)
- 80087c0:	f008 fa02 	bl	8010bc8 <iprintf>
-
-  cseg = (struct tcp_seg *)memp_malloc(MEMP_TCP_SEG);
- 80087c4:	2003      	movs	r0, #3
- 80087c6:	f7fd fc29 	bl	800601c <memp_malloc>
- 80087ca:	60f8      	str	r0, [r7, #12]
-  if (cseg == NULL) {
- 80087cc:	68fb      	ldr	r3, [r7, #12]
- 80087ce:	2b00      	cmp	r3, #0
- 80087d0:	d101      	bne.n	80087d6 <tcp_seg_copy+0x2e>
-    return NULL;
- 80087d2:	2300      	movs	r3, #0
- 80087d4:	e00a      	b.n	80087ec <tcp_seg_copy+0x44>
-  }
-  SMEMCPY((u8_t *)cseg, (const u8_t *)seg, sizeof(struct tcp_seg));
- 80087d6:	2214      	movs	r2, #20
- 80087d8:	6879      	ldr	r1, [r7, #4]
- 80087da:	68f8      	ldr	r0, [r7, #12]
- 80087dc:	f008 fbd5 	bl	8010f8a <memcpy>
-  pbuf_ref(cseg->p);
- 80087e0:	68fb      	ldr	r3, [r7, #12]
- 80087e2:	685b      	ldr	r3, [r3, #4]
- 80087e4:	4618      	mov	r0, r3
- 80087e6:	f7fe fc95 	bl	8007114 <pbuf_ref>
-  return cseg;
- 80087ea:	68fb      	ldr	r3, [r7, #12]
-}
- 80087ec:	4618      	mov	r0, r3
- 80087ee:	3710      	adds	r7, #16
- 80087f0:	46bd      	mov	sp, r7
- 80087f2:	bd80      	pop	{r7, pc}
- 80087f4:	08012a08 	.word	0x08012a08
- 80087f8:	08012f5c 	.word	0x08012f5c
- 80087fc:	08012a4c 	.word	0x08012a4c
-
-08008800 <tcp_recv_null>:
- * Default receive callback that is called if the user didn't register
- * a recv callback for the pcb.
- */
-err_t
-tcp_recv_null(void *arg, struct tcp_pcb *pcb, struct pbuf *p, err_t err)
-{
- 8008800:	b580      	push	{r7, lr}
- 8008802:	b084      	sub	sp, #16
- 8008804:	af00      	add	r7, sp, #0
- 8008806:	60f8      	str	r0, [r7, #12]
- 8008808:	60b9      	str	r1, [r7, #8]
- 800880a:	607a      	str	r2, [r7, #4]
- 800880c:	70fb      	strb	r3, [r7, #3]
-  LWIP_UNUSED_ARG(arg);
-
-  LWIP_ERROR("tcp_recv_null: invalid pcb", pcb != NULL, return ERR_ARG);
- 800880e:	68bb      	ldr	r3, [r7, #8]
- 8008810:	2b00      	cmp	r3, #0
- 8008812:	d109      	bne.n	8008828 <tcp_recv_null+0x28>
- 8008814:	4b12      	ldr	r3, [pc, #72]	; (8008860 <tcp_recv_null+0x60>)
- 8008816:	f44f 62d3 	mov.w	r2, #1688	; 0x698
- 800881a:	4912      	ldr	r1, [pc, #72]	; (8008864 <tcp_recv_null+0x64>)
- 800881c:	4812      	ldr	r0, [pc, #72]	; (8008868 <tcp_recv_null+0x68>)
- 800881e:	f008 f9d3 	bl	8010bc8 <iprintf>
- 8008822:	f06f 030f 	mvn.w	r3, #15
- 8008826:	e016      	b.n	8008856 <tcp_recv_null+0x56>
-
-  if (p != NULL) {
- 8008828:	687b      	ldr	r3, [r7, #4]
- 800882a:	2b00      	cmp	r3, #0
- 800882c:	d009      	beq.n	8008842 <tcp_recv_null+0x42>
-    tcp_recved(pcb, p->tot_len);
- 800882e:	687b      	ldr	r3, [r7, #4]
- 8008830:	891b      	ldrh	r3, [r3, #8]
- 8008832:	4619      	mov	r1, r3
- 8008834:	68b8      	ldr	r0, [r7, #8]
- 8008836:	f7ff f9bb 	bl	8007bb0 <tcp_recved>
-    pbuf_free(p);
- 800883a:	6878      	ldr	r0, [r7, #4]
- 800883c:	f7fe fbca 	bl	8006fd4 <pbuf_free>
- 8008840:	e008      	b.n	8008854 <tcp_recv_null+0x54>
-  } else if (err == ERR_OK) {
- 8008842:	f997 3003 	ldrsb.w	r3, [r7, #3]
- 8008846:	2b00      	cmp	r3, #0
- 8008848:	d104      	bne.n	8008854 <tcp_recv_null+0x54>
-    return tcp_close(pcb);
- 800884a:	68b8      	ldr	r0, [r7, #8]
- 800884c:	f7ff f860 	bl	8007910 <tcp_close>
- 8008850:	4603      	mov	r3, r0
- 8008852:	e000      	b.n	8008856 <tcp_recv_null+0x56>
-  }
-  return ERR_OK;
- 8008854:	2300      	movs	r3, #0
-}
- 8008856:	4618      	mov	r0, r3
- 8008858:	3710      	adds	r7, #16
- 800885a:	46bd      	mov	sp, r7
- 800885c:	bd80      	pop	{r7, pc}
- 800885e:	bf00      	nop
- 8008860:	08012a08 	.word	0x08012a08
- 8008864:	08012f78 	.word	0x08012f78
- 8008868:	08012a4c 	.word	0x08012a4c
-
-0800886c <tcp_kill_prio>:
- *
- * @param prio minimum priority
- */
-static void
-tcp_kill_prio(u8_t prio)
-{
- 800886c:	b580      	push	{r7, lr}
- 800886e:	b086      	sub	sp, #24
- 8008870:	af00      	add	r7, sp, #0
- 8008872:	4603      	mov	r3, r0
- 8008874:	71fb      	strb	r3, [r7, #7]
-  struct tcp_pcb *pcb, *inactive;
-  u32_t inactivity;
-  u8_t mprio;
-
-  mprio = LWIP_MIN(TCP_PRIO_MAX, prio);
- 8008876:	f997 3007 	ldrsb.w	r3, [r7, #7]
- 800887a:	2b00      	cmp	r3, #0
- 800887c:	db01      	blt.n	8008882 <tcp_kill_prio+0x16>
- 800887e:	79fb      	ldrb	r3, [r7, #7]
- 8008880:	e000      	b.n	8008884 <tcp_kill_prio+0x18>
- 8008882:	237f      	movs	r3, #127	; 0x7f
- 8008884:	72fb      	strb	r3, [r7, #11]
-
-  /* We want to kill connections with a lower prio, so bail out if
-   * supplied prio is 0 - there can never be a lower prio
-   */
-  if (mprio == 0) {
- 8008886:	7afb      	ldrb	r3, [r7, #11]
- 8008888:	2b00      	cmp	r3, #0
- 800888a:	d034      	beq.n	80088f6 <tcp_kill_prio+0x8a>
-  /* We only want kill connections with a lower prio, so decrement prio by one
-   * and start searching for oldest connection with same or lower priority than mprio.
-   * We want to find the connections with the lowest possible prio, and among
-   * these the one with the longest inactivity time.
-   */
-  mprio--;
- 800888c:	7afb      	ldrb	r3, [r7, #11]
- 800888e:	3b01      	subs	r3, #1
- 8008890:	72fb      	strb	r3, [r7, #11]
-
-  inactivity = 0;
- 8008892:	2300      	movs	r3, #0
- 8008894:	60fb      	str	r3, [r7, #12]
-  inactive = NULL;
- 8008896:	2300      	movs	r3, #0
- 8008898:	613b      	str	r3, [r7, #16]
-  for (pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) {
- 800889a:	4b19      	ldr	r3, [pc, #100]	; (8008900 <tcp_kill_prio+0x94>)
- 800889c:	681b      	ldr	r3, [r3, #0]
- 800889e:	617b      	str	r3, [r7, #20]
- 80088a0:	e01f      	b.n	80088e2 <tcp_kill_prio+0x76>
-        /* lower prio is always a kill candidate */
-    if ((pcb->prio < mprio) ||
- 80088a2:	697b      	ldr	r3, [r7, #20]
- 80088a4:	7d5b      	ldrb	r3, [r3, #21]
- 80088a6:	7afa      	ldrb	r2, [r7, #11]
- 80088a8:	429a      	cmp	r2, r3
- 80088aa:	d80c      	bhi.n	80088c6 <tcp_kill_prio+0x5a>
-        /* longer inactivity is also a kill candidate */
-        ((pcb->prio == mprio) && ((u32_t)(tcp_ticks - pcb->tmr) >= inactivity))) {
- 80088ac:	697b      	ldr	r3, [r7, #20]
- 80088ae:	7d5b      	ldrb	r3, [r3, #21]
-    if ((pcb->prio < mprio) ||
- 80088b0:	7afa      	ldrb	r2, [r7, #11]
- 80088b2:	429a      	cmp	r2, r3
- 80088b4:	d112      	bne.n	80088dc <tcp_kill_prio+0x70>
-        ((pcb->prio == mprio) && ((u32_t)(tcp_ticks - pcb->tmr) >= inactivity))) {
- 80088b6:	4b13      	ldr	r3, [pc, #76]	; (8008904 <tcp_kill_prio+0x98>)
- 80088b8:	681a      	ldr	r2, [r3, #0]
- 80088ba:	697b      	ldr	r3, [r7, #20]
- 80088bc:	6a1b      	ldr	r3, [r3, #32]
- 80088be:	1ad3      	subs	r3, r2, r3
- 80088c0:	68fa      	ldr	r2, [r7, #12]
- 80088c2:	429a      	cmp	r2, r3
- 80088c4:	d80a      	bhi.n	80088dc <tcp_kill_prio+0x70>
-      inactivity = tcp_ticks - pcb->tmr;
- 80088c6:	4b0f      	ldr	r3, [pc, #60]	; (8008904 <tcp_kill_prio+0x98>)
- 80088c8:	681a      	ldr	r2, [r3, #0]
- 80088ca:	697b      	ldr	r3, [r7, #20]
- 80088cc:	6a1b      	ldr	r3, [r3, #32]
- 80088ce:	1ad3      	subs	r3, r2, r3
- 80088d0:	60fb      	str	r3, [r7, #12]
-      inactive   = pcb;
- 80088d2:	697b      	ldr	r3, [r7, #20]
- 80088d4:	613b      	str	r3, [r7, #16]
-      mprio      = pcb->prio;
- 80088d6:	697b      	ldr	r3, [r7, #20]
- 80088d8:	7d5b      	ldrb	r3, [r3, #21]
- 80088da:	72fb      	strb	r3, [r7, #11]
-  for (pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) {
- 80088dc:	697b      	ldr	r3, [r7, #20]
- 80088de:	68db      	ldr	r3, [r3, #12]
- 80088e0:	617b      	str	r3, [r7, #20]
- 80088e2:	697b      	ldr	r3, [r7, #20]
- 80088e4:	2b00      	cmp	r3, #0
- 80088e6:	d1dc      	bne.n	80088a2 <tcp_kill_prio+0x36>
-    }
-  }
-  if (inactive != NULL) {
- 80088e8:	693b      	ldr	r3, [r7, #16]
- 80088ea:	2b00      	cmp	r3, #0
- 80088ec:	d004      	beq.n	80088f8 <tcp_kill_prio+0x8c>
-    LWIP_DEBUGF(TCP_DEBUG, ("tcp_kill_prio: killing oldest PCB %p (%"S32_F")\n",
-                            (void *)inactive, inactivity));
-    tcp_abort(inactive);
- 80088ee:	6938      	ldr	r0, [r7, #16]
- 80088f0:	f7ff f8f8 	bl	8007ae4 <tcp_abort>
- 80088f4:	e000      	b.n	80088f8 <tcp_kill_prio+0x8c>
-    return;
- 80088f6:	bf00      	nop
-  }
-}
- 80088f8:	3718      	adds	r7, #24
- 80088fa:	46bd      	mov	sp, r7
- 80088fc:	bd80      	pop	{r7, pc}
- 80088fe:	bf00      	nop
- 8008900:	24007b78 	.word	0x24007b78
- 8008904:	24007b6c 	.word	0x24007b6c
-
-08008908 <tcp_kill_state>:
- * Kills the oldest connection that is in specific state.
- * Called from tcp_alloc() for LAST_ACK and CLOSING if no more connections are available.
- */
-static void
-tcp_kill_state(enum tcp_state state)
-{
- 8008908:	b580      	push	{r7, lr}
- 800890a:	b086      	sub	sp, #24
- 800890c:	af00      	add	r7, sp, #0
- 800890e:	4603      	mov	r3, r0
- 8008910:	71fb      	strb	r3, [r7, #7]
-  struct tcp_pcb *pcb, *inactive;
-  u32_t inactivity;
-
-  LWIP_ASSERT("invalid state", (state == CLOSING) || (state == LAST_ACK));
- 8008912:	79fb      	ldrb	r3, [r7, #7]
- 8008914:	2b08      	cmp	r3, #8
- 8008916:	d009      	beq.n	800892c <tcp_kill_state+0x24>
- 8008918:	79fb      	ldrb	r3, [r7, #7]
- 800891a:	2b09      	cmp	r3, #9
- 800891c:	d006      	beq.n	800892c <tcp_kill_state+0x24>
- 800891e:	4b1a      	ldr	r3, [pc, #104]	; (8008988 <tcp_kill_state+0x80>)
- 8008920:	f240 62dd 	movw	r2, #1757	; 0x6dd
- 8008924:	4919      	ldr	r1, [pc, #100]	; (800898c <tcp_kill_state+0x84>)
- 8008926:	481a      	ldr	r0, [pc, #104]	; (8008990 <tcp_kill_state+0x88>)
- 8008928:	f008 f94e 	bl	8010bc8 <iprintf>
-
-  inactivity = 0;
- 800892c:	2300      	movs	r3, #0
- 800892e:	60fb      	str	r3, [r7, #12]
-  inactive = NULL;
- 8008930:	2300      	movs	r3, #0
- 8008932:	613b      	str	r3, [r7, #16]
-  /* Go through the list of active pcbs and get the oldest pcb that is in state
-     CLOSING/LAST_ACK. */
-  for (pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) {
- 8008934:	4b17      	ldr	r3, [pc, #92]	; (8008994 <tcp_kill_state+0x8c>)
- 8008936:	681b      	ldr	r3, [r3, #0]
- 8008938:	617b      	str	r3, [r7, #20]
- 800893a:	e017      	b.n	800896c <tcp_kill_state+0x64>
-    if (pcb->state == state) {
- 800893c:	697b      	ldr	r3, [r7, #20]
- 800893e:	7d1b      	ldrb	r3, [r3, #20]
- 8008940:	79fa      	ldrb	r2, [r7, #7]
- 8008942:	429a      	cmp	r2, r3
- 8008944:	d10f      	bne.n	8008966 <tcp_kill_state+0x5e>
-      if ((u32_t)(tcp_ticks - pcb->tmr) >= inactivity) {
- 8008946:	4b14      	ldr	r3, [pc, #80]	; (8008998 <tcp_kill_state+0x90>)
- 8008948:	681a      	ldr	r2, [r3, #0]
- 800894a:	697b      	ldr	r3, [r7, #20]
- 800894c:	6a1b      	ldr	r3, [r3, #32]
- 800894e:	1ad3      	subs	r3, r2, r3
- 8008950:	68fa      	ldr	r2, [r7, #12]
- 8008952:	429a      	cmp	r2, r3
- 8008954:	d807      	bhi.n	8008966 <tcp_kill_state+0x5e>
-        inactivity = tcp_ticks - pcb->tmr;
- 8008956:	4b10      	ldr	r3, [pc, #64]	; (8008998 <tcp_kill_state+0x90>)
- 8008958:	681a      	ldr	r2, [r3, #0]
- 800895a:	697b      	ldr	r3, [r7, #20]
- 800895c:	6a1b      	ldr	r3, [r3, #32]
- 800895e:	1ad3      	subs	r3, r2, r3
- 8008960:	60fb      	str	r3, [r7, #12]
-        inactive = pcb;
- 8008962:	697b      	ldr	r3, [r7, #20]
- 8008964:	613b      	str	r3, [r7, #16]
-  for (pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) {
- 8008966:	697b      	ldr	r3, [r7, #20]
- 8008968:	68db      	ldr	r3, [r3, #12]
- 800896a:	617b      	str	r3, [r7, #20]
- 800896c:	697b      	ldr	r3, [r7, #20]
- 800896e:	2b00      	cmp	r3, #0
- 8008970:	d1e4      	bne.n	800893c <tcp_kill_state+0x34>
-      }
-    }
-  }
-  if (inactive != NULL) {
- 8008972:	693b      	ldr	r3, [r7, #16]
- 8008974:	2b00      	cmp	r3, #0
- 8008976:	d003      	beq.n	8008980 <tcp_kill_state+0x78>
-    LWIP_DEBUGF(TCP_DEBUG, ("tcp_kill_closing: killing oldest %s PCB %p (%"S32_F")\n",
-                            tcp_state_str[state], (void *)inactive, inactivity));
-    /* Don't send a RST, since no data is lost. */
-    tcp_abandon(inactive, 0);
- 8008978:	2100      	movs	r1, #0
- 800897a:	6938      	ldr	r0, [r7, #16]
- 800897c:	f7fe fff4 	bl	8007968 <tcp_abandon>
-  }
-}
- 8008980:	bf00      	nop
- 8008982:	3718      	adds	r7, #24
- 8008984:	46bd      	mov	sp, r7
- 8008986:	bd80      	pop	{r7, pc}
- 8008988:	08012a08 	.word	0x08012a08
- 800898c:	08012f94 	.word	0x08012f94
- 8008990:	08012a4c 	.word	0x08012a4c
- 8008994:	24007b78 	.word	0x24007b78
- 8008998:	24007b6c 	.word	0x24007b6c
-
-0800899c <tcp_kill_timewait>:
- * Kills the oldest connection that is in TIME_WAIT state.
- * Called from tcp_alloc() if no more connections are available.
- */
-static void
-tcp_kill_timewait(void)
-{
- 800899c:	b580      	push	{r7, lr}
- 800899e:	b084      	sub	sp, #16
- 80089a0:	af00      	add	r7, sp, #0
-  struct tcp_pcb *pcb, *inactive;
-  u32_t inactivity;
-
-  inactivity = 0;
- 80089a2:	2300      	movs	r3, #0
- 80089a4:	607b      	str	r3, [r7, #4]
-  inactive = NULL;
- 80089a6:	2300      	movs	r3, #0
- 80089a8:	60bb      	str	r3, [r7, #8]
-  /* Go through the list of TIME_WAIT pcbs and get the oldest pcb. */
-  for (pcb = tcp_tw_pcbs; pcb != NULL; pcb = pcb->next) {
- 80089aa:	4b12      	ldr	r3, [pc, #72]	; (80089f4 <tcp_kill_timewait+0x58>)
- 80089ac:	681b      	ldr	r3, [r3, #0]
- 80089ae:	60fb      	str	r3, [r7, #12]
- 80089b0:	e012      	b.n	80089d8 <tcp_kill_timewait+0x3c>
-    if ((u32_t)(tcp_ticks - pcb->tmr) >= inactivity) {
- 80089b2:	4b11      	ldr	r3, [pc, #68]	; (80089f8 <tcp_kill_timewait+0x5c>)
- 80089b4:	681a      	ldr	r2, [r3, #0]
- 80089b6:	68fb      	ldr	r3, [r7, #12]
- 80089b8:	6a1b      	ldr	r3, [r3, #32]
- 80089ba:	1ad3      	subs	r3, r2, r3
- 80089bc:	687a      	ldr	r2, [r7, #4]
- 80089be:	429a      	cmp	r2, r3
- 80089c0:	d807      	bhi.n	80089d2 <tcp_kill_timewait+0x36>
-      inactivity = tcp_ticks - pcb->tmr;
- 80089c2:	4b0d      	ldr	r3, [pc, #52]	; (80089f8 <tcp_kill_timewait+0x5c>)
- 80089c4:	681a      	ldr	r2, [r3, #0]
- 80089c6:	68fb      	ldr	r3, [r7, #12]
- 80089c8:	6a1b      	ldr	r3, [r3, #32]
- 80089ca:	1ad3      	subs	r3, r2, r3
- 80089cc:	607b      	str	r3, [r7, #4]
-      inactive = pcb;
- 80089ce:	68fb      	ldr	r3, [r7, #12]
- 80089d0:	60bb      	str	r3, [r7, #8]
-  for (pcb = tcp_tw_pcbs; pcb != NULL; pcb = pcb->next) {
- 80089d2:	68fb      	ldr	r3, [r7, #12]
- 80089d4:	68db      	ldr	r3, [r3, #12]
- 80089d6:	60fb      	str	r3, [r7, #12]
- 80089d8:	68fb      	ldr	r3, [r7, #12]
- 80089da:	2b00      	cmp	r3, #0
- 80089dc:	d1e9      	bne.n	80089b2 <tcp_kill_timewait+0x16>
-    }
-  }
-  if (inactive != NULL) {
- 80089de:	68bb      	ldr	r3, [r7, #8]
- 80089e0:	2b00      	cmp	r3, #0
- 80089e2:	d002      	beq.n	80089ea <tcp_kill_timewait+0x4e>
-    LWIP_DEBUGF(TCP_DEBUG, ("tcp_kill_timewait: killing oldest TIME-WAIT PCB %p (%"S32_F")\n",
-                            (void *)inactive, inactivity));
-    tcp_abort(inactive);
- 80089e4:	68b8      	ldr	r0, [r7, #8]
- 80089e6:	f7ff f87d 	bl	8007ae4 <tcp_abort>
-  }
-}
- 80089ea:	bf00      	nop
- 80089ec:	3710      	adds	r7, #16
- 80089ee:	46bd      	mov	sp, r7
- 80089f0:	bd80      	pop	{r7, pc}
- 80089f2:	bf00      	nop
- 80089f4:	24007b7c 	.word	0x24007b7c
- 80089f8:	24007b6c 	.word	0x24007b6c
-
-080089fc <tcp_handle_closepend>:
- * now send the FIN (which failed before), the pcb might be in a state that is
- * OK for us to now free it.
- */
-static void
-tcp_handle_closepend(void)
-{
- 80089fc:	b580      	push	{r7, lr}
- 80089fe:	b082      	sub	sp, #8
- 8008a00:	af00      	add	r7, sp, #0
-  struct tcp_pcb *pcb = tcp_active_pcbs;
- 8008a02:	4b10      	ldr	r3, [pc, #64]	; (8008a44 <tcp_handle_closepend+0x48>)
- 8008a04:	681b      	ldr	r3, [r3, #0]
- 8008a06:	607b      	str	r3, [r7, #4]
-
-  while (pcb != NULL) {
- 8008a08:	e014      	b.n	8008a34 <tcp_handle_closepend+0x38>
-    struct tcp_pcb *next = pcb->next;
- 8008a0a:	687b      	ldr	r3, [r7, #4]
- 8008a0c:	68db      	ldr	r3, [r3, #12]
- 8008a0e:	603b      	str	r3, [r7, #0]
-    /* send pending FIN */
-    if (pcb->flags & TF_CLOSEPEND) {
- 8008a10:	687b      	ldr	r3, [r7, #4]
- 8008a12:	8b5b      	ldrh	r3, [r3, #26]
- 8008a14:	f003 0308 	and.w	r3, r3, #8
- 8008a18:	2b00      	cmp	r3, #0
- 8008a1a:	d009      	beq.n	8008a30 <tcp_handle_closepend+0x34>
-      LWIP_DEBUGF(TCP_DEBUG, ("tcp_handle_closepend: pending FIN\n"));
-      tcp_clear_flags(pcb, TF_CLOSEPEND);
- 8008a1c:	687b      	ldr	r3, [r7, #4]
- 8008a1e:	8b5b      	ldrh	r3, [r3, #26]
- 8008a20:	f023 0308 	bic.w	r3, r3, #8
- 8008a24:	b29a      	uxth	r2, r3
- 8008a26:	687b      	ldr	r3, [r7, #4]
- 8008a28:	835a      	strh	r2, [r3, #26]
-      tcp_close_shutdown_fin(pcb);
- 8008a2a:	6878      	ldr	r0, [r7, #4]
- 8008a2c:	f7fe ff06 	bl	800783c <tcp_close_shutdown_fin>
-    }
-    pcb = next;
- 8008a30:	683b      	ldr	r3, [r7, #0]
- 8008a32:	607b      	str	r3, [r7, #4]
-  while (pcb != NULL) {
- 8008a34:	687b      	ldr	r3, [r7, #4]
- 8008a36:	2b00      	cmp	r3, #0
- 8008a38:	d1e7      	bne.n	8008a0a <tcp_handle_closepend+0xe>
-  }
-}
- 8008a3a:	bf00      	nop
- 8008a3c:	bf00      	nop
- 8008a3e:	3708      	adds	r7, #8
- 8008a40:	46bd      	mov	sp, r7
- 8008a42:	bd80      	pop	{r7, pc}
- 8008a44:	24007b78 	.word	0x24007b78
-
-08008a48 <tcp_alloc>:
- * @param prio priority for the new pcb
- * @return a new tcp_pcb that initially is in state CLOSED
- */
-struct tcp_pcb *
-tcp_alloc(u8_t prio)
-{
- 8008a48:	b580      	push	{r7, lr}
- 8008a4a:	b084      	sub	sp, #16
- 8008a4c:	af00      	add	r7, sp, #0
- 8008a4e:	4603      	mov	r3, r0
- 8008a50:	71fb      	strb	r3, [r7, #7]
-  struct tcp_pcb *pcb;
-
-  LWIP_ASSERT_CORE_LOCKED();
-
-  pcb = (struct tcp_pcb *)memp_malloc(MEMP_TCP_PCB);
- 8008a52:	2001      	movs	r0, #1
- 8008a54:	f7fd fae2 	bl	800601c <memp_malloc>
- 8008a58:	60f8      	str	r0, [r7, #12]
-  if (pcb == NULL) {
- 8008a5a:	68fb      	ldr	r3, [r7, #12]
- 8008a5c:	2b00      	cmp	r3, #0
- 8008a5e:	d126      	bne.n	8008aae <tcp_alloc+0x66>
-    /* Try to send FIN for all pcbs stuck in TF_CLOSEPEND first */
-    tcp_handle_closepend();
- 8008a60:	f7ff ffcc 	bl	80089fc <tcp_handle_closepend>
-
-    /* Try killing oldest connection in TIME-WAIT. */
-    LWIP_DEBUGF(TCP_DEBUG, ("tcp_alloc: killing off oldest TIME-WAIT connection\n"));
-    tcp_kill_timewait();
- 8008a64:	f7ff ff9a 	bl	800899c <tcp_kill_timewait>
-    /* Try to allocate a tcp_pcb again. */
-    pcb = (struct tcp_pcb *)memp_malloc(MEMP_TCP_PCB);
- 8008a68:	2001      	movs	r0, #1
- 8008a6a:	f7fd fad7 	bl	800601c <memp_malloc>
- 8008a6e:	60f8      	str	r0, [r7, #12]
-    if (pcb == NULL) {
- 8008a70:	68fb      	ldr	r3, [r7, #12]
- 8008a72:	2b00      	cmp	r3, #0
- 8008a74:	d11b      	bne.n	8008aae <tcp_alloc+0x66>
-      /* Try killing oldest connection in LAST-ACK (these wouldn't go to TIME-WAIT). */
-      LWIP_DEBUGF(TCP_DEBUG, ("tcp_alloc: killing off oldest LAST-ACK connection\n"));
-      tcp_kill_state(LAST_ACK);
- 8008a76:	2009      	movs	r0, #9
- 8008a78:	f7ff ff46 	bl	8008908 <tcp_kill_state>
-      /* Try to allocate a tcp_pcb again. */
-      pcb = (struct tcp_pcb *)memp_malloc(MEMP_TCP_PCB);
- 8008a7c:	2001      	movs	r0, #1
- 8008a7e:	f7fd facd 	bl	800601c <memp_malloc>
- 8008a82:	60f8      	str	r0, [r7, #12]
-      if (pcb == NULL) {
- 8008a84:	68fb      	ldr	r3, [r7, #12]
- 8008a86:	2b00      	cmp	r3, #0
- 8008a88:	d111      	bne.n	8008aae <tcp_alloc+0x66>
-        /* Try killing oldest connection in CLOSING. */
-        LWIP_DEBUGF(TCP_DEBUG, ("tcp_alloc: killing off oldest CLOSING connection\n"));
-        tcp_kill_state(CLOSING);
- 8008a8a:	2008      	movs	r0, #8
- 8008a8c:	f7ff ff3c 	bl	8008908 <tcp_kill_state>
-        /* Try to allocate a tcp_pcb again. */
-        pcb = (struct tcp_pcb *)memp_malloc(MEMP_TCP_PCB);
- 8008a90:	2001      	movs	r0, #1
- 8008a92:	f7fd fac3 	bl	800601c <memp_malloc>
- 8008a96:	60f8      	str	r0, [r7, #12]
-        if (pcb == NULL) {
- 8008a98:	68fb      	ldr	r3, [r7, #12]
- 8008a9a:	2b00      	cmp	r3, #0
- 8008a9c:	d107      	bne.n	8008aae <tcp_alloc+0x66>
-          /* Try killing oldest active connection with lower priority than the new one. */
-          LWIP_DEBUGF(TCP_DEBUG, ("tcp_alloc: killing oldest connection with prio lower than %d\n", prio));
-          tcp_kill_prio(prio);
- 8008a9e:	79fb      	ldrb	r3, [r7, #7]
- 8008aa0:	4618      	mov	r0, r3
- 8008aa2:	f7ff fee3 	bl	800886c <tcp_kill_prio>
-          /* Try to allocate a tcp_pcb again. */
-          pcb = (struct tcp_pcb *)memp_malloc(MEMP_TCP_PCB);
- 8008aa6:	2001      	movs	r0, #1
- 8008aa8:	f7fd fab8 	bl	800601c <memp_malloc>
- 8008aac:	60f8      	str	r0, [r7, #12]
-    if (pcb != NULL) {
-      /* adjust err stats: memp_malloc failed above */
-      MEMP_STATS_DEC(err, MEMP_TCP_PCB);
-    }
-  }
-  if (pcb != NULL) {
- 8008aae:	68fb      	ldr	r3, [r7, #12]
- 8008ab0:	2b00      	cmp	r3, #0
- 8008ab2:	d03f      	beq.n	8008b34 <tcp_alloc+0xec>
-    /* zero out the whole pcb, so there is no need to initialize members to zero */
-    memset(pcb, 0, sizeof(struct tcp_pcb));
- 8008ab4:	229c      	movs	r2, #156	; 0x9c
- 8008ab6:	2100      	movs	r1, #0
- 8008ab8:	68f8      	ldr	r0, [r7, #12]
- 8008aba:	f008 f9e3 	bl	8010e84 <memset>
-    pcb->prio = prio;
- 8008abe:	68fb      	ldr	r3, [r7, #12]
- 8008ac0:	79fa      	ldrb	r2, [r7, #7]
- 8008ac2:	755a      	strb	r2, [r3, #21]
-    pcb->snd_buf = TCP_SND_BUF;
- 8008ac4:	68fb      	ldr	r3, [r7, #12]
- 8008ac6:	f44f 6286 	mov.w	r2, #1072	; 0x430
- 8008aca:	f8a3 2064 	strh.w	r2, [r3, #100]	; 0x64
-    /* Start with a window that does not need scaling. When window scaling is
-       enabled and used, the window is enlarged when both sides agree on scaling. */
-    pcb->rcv_wnd = pcb->rcv_ann_wnd = TCPWND_MIN16(TCP_WND);
- 8008ace:	68fb      	ldr	r3, [r7, #12]
- 8008ad0:	f44f 6206 	mov.w	r2, #2144	; 0x860
- 8008ad4:	855a      	strh	r2, [r3, #42]	; 0x2a
- 8008ad6:	68fb      	ldr	r3, [r7, #12]
- 8008ad8:	8d5a      	ldrh	r2, [r3, #42]	; 0x2a
- 8008ada:	68fb      	ldr	r3, [r7, #12]
- 8008adc:	851a      	strh	r2, [r3, #40]	; 0x28
-    pcb->ttl = TCP_TTL;
- 8008ade:	68fb      	ldr	r3, [r7, #12]
- 8008ae0:	22ff      	movs	r2, #255	; 0xff
- 8008ae2:	72da      	strb	r2, [r3, #11]
-    /* As initial send MSS, we use TCP_MSS but limit it to 536.
-       The send MSS is updated when an MSS option is received. */
-    pcb->mss = INITIAL_MSS;
- 8008ae4:	68fb      	ldr	r3, [r7, #12]
- 8008ae6:	f44f 7206 	mov.w	r2, #536	; 0x218
- 8008aea:	865a      	strh	r2, [r3, #50]	; 0x32
-    pcb->rto = 3000 / TCP_SLOW_INTERVAL;
- 8008aec:	68fb      	ldr	r3, [r7, #12]
- 8008aee:	2206      	movs	r2, #6
- 8008af0:	f8a3 2040 	strh.w	r2, [r3, #64]	; 0x40
-    pcb->sv = 3000 / TCP_SLOW_INTERVAL;
- 8008af4:	68fb      	ldr	r3, [r7, #12]
- 8008af6:	2206      	movs	r2, #6
- 8008af8:	87da      	strh	r2, [r3, #62]	; 0x3e
-    pcb->rtime = -1;
- 8008afa:	68fb      	ldr	r3, [r7, #12]
- 8008afc:	f64f 72ff 	movw	r2, #65535	; 0xffff
- 8008b00:	861a      	strh	r2, [r3, #48]	; 0x30
-    pcb->cwnd = 1;
- 8008b02:	68fb      	ldr	r3, [r7, #12]
- 8008b04:	2201      	movs	r2, #1
- 8008b06:	f8a3 2048 	strh.w	r2, [r3, #72]	; 0x48
-    pcb->tmr = tcp_ticks;
- 8008b0a:	4b0d      	ldr	r3, [pc, #52]	; (8008b40 <tcp_alloc+0xf8>)
- 8008b0c:	681a      	ldr	r2, [r3, #0]
- 8008b0e:	68fb      	ldr	r3, [r7, #12]
- 8008b10:	621a      	str	r2, [r3, #32]
-    pcb->last_timer = tcp_timer_ctr;
- 8008b12:	4b0c      	ldr	r3, [pc, #48]	; (8008b44 <tcp_alloc+0xfc>)
- 8008b14:	781a      	ldrb	r2, [r3, #0]
- 8008b16:	68fb      	ldr	r3, [r7, #12]
- 8008b18:	779a      	strb	r2, [r3, #30]
-    of using the largest advertised receive window.  We've seen complications with
-    receiving TCPs that use window scaling and/or window auto-tuning where the
-    initial advertised window is very small and then grows rapidly once the
-    connection is established. To avoid these complications, we set ssthresh to the
-    largest effective cwnd (amount of in-flight data) that the sender can have. */
-    pcb->ssthresh = TCP_SND_BUF;
- 8008b1a:	68fb      	ldr	r3, [r7, #12]
- 8008b1c:	f44f 6286 	mov.w	r2, #1072	; 0x430
- 8008b20:	f8a3 204a 	strh.w	r2, [r3, #74]	; 0x4a
-
-#if LWIP_CALLBACK_API
-    pcb->recv = tcp_recv_null;
- 8008b24:	68fb      	ldr	r3, [r7, #12]
- 8008b26:	4a08      	ldr	r2, [pc, #32]	; (8008b48 <tcp_alloc+0x100>)
- 8008b28:	f8c3 2084 	str.w	r2, [r3, #132]	; 0x84
-#endif /* LWIP_CALLBACK_API */
-
-    /* Init KEEPALIVE timer */
-    pcb->keep_idle  = TCP_KEEPIDLE_DEFAULT;
- 8008b2c:	68fb      	ldr	r3, [r7, #12]
- 8008b2e:	4a07      	ldr	r2, [pc, #28]	; (8008b4c <tcp_alloc+0x104>)
- 8008b30:	f8c3 2094 	str.w	r2, [r3, #148]	; 0x94
-#if LWIP_TCP_KEEPALIVE
-    pcb->keep_intvl = TCP_KEEPINTVL_DEFAULT;
-    pcb->keep_cnt   = TCP_KEEPCNT_DEFAULT;
-#endif /* LWIP_TCP_KEEPALIVE */
-  }
-  return pcb;
- 8008b34:	68fb      	ldr	r3, [r7, #12]
-}
- 8008b36:	4618      	mov	r0, r3
- 8008b38:	3710      	adds	r7, #16
- 8008b3a:	46bd      	mov	sp, r7
- 8008b3c:	bd80      	pop	{r7, pc}
- 8008b3e:	bf00      	nop
- 8008b40:	24007b6c 	.word	0x24007b6c
- 8008b44:	24007b82 	.word	0x24007b82
- 8008b48:	08008801 	.word	0x08008801
- 8008b4c:	006ddd00 	.word	0x006ddd00
-
-08008b50 <tcp_new>:
- *
- * @return a new tcp_pcb that initially is in state CLOSED
- */
-struct tcp_pcb *
-tcp_new(void)
-{
- 8008b50:	b580      	push	{r7, lr}
- 8008b52:	af00      	add	r7, sp, #0
-  return tcp_alloc(TCP_PRIO_NORMAL);
- 8008b54:	2040      	movs	r0, #64	; 0x40
- 8008b56:	f7ff ff77 	bl	8008a48 <tcp_alloc>
- 8008b5a:	4603      	mov	r3, r0
-}
- 8008b5c:	4618      	mov	r0, r3
- 8008b5e:	bd80      	pop	{r7, pc}
-
-08008b60 <tcp_arg>:
- * @param pcb tcp_pcb to set the callback argument
- * @param arg void pointer argument to pass to callback functions
- */
-void
-tcp_arg(struct tcp_pcb *pcb, void *arg)
-{
- 8008b60:	b480      	push	{r7}
- 8008b62:	b083      	sub	sp, #12
- 8008b64:	af00      	add	r7, sp, #0
- 8008b66:	6078      	str	r0, [r7, #4]
- 8008b68:	6039      	str	r1, [r7, #0]
-  LWIP_ASSERT_CORE_LOCKED();
-  /* This function is allowed to be called for both listen pcbs and
-     connection pcbs. */
-  if (pcb != NULL) {
- 8008b6a:	687b      	ldr	r3, [r7, #4]
- 8008b6c:	2b00      	cmp	r3, #0
- 8008b6e:	d002      	beq.n	8008b76 <tcp_arg+0x16>
-    pcb->callback_arg = arg;
- 8008b70:	687b      	ldr	r3, [r7, #4]
- 8008b72:	683a      	ldr	r2, [r7, #0]
- 8008b74:	611a      	str	r2, [r3, #16]
-  }
-}
- 8008b76:	bf00      	nop
- 8008b78:	370c      	adds	r7, #12
- 8008b7a:	46bd      	mov	sp, r7
- 8008b7c:	f85d 7b04 	ldr.w	r7, [sp], #4
- 8008b80:	4770      	bx	lr
-	...
-
-08008b84 <tcp_recv>:
- * @param pcb tcp_pcb to set the recv callback
- * @param recv callback function to call for this pcb when data is received
- */
-void
-tcp_recv(struct tcp_pcb *pcb, tcp_recv_fn recv)
-{
- 8008b84:	b580      	push	{r7, lr}
- 8008b86:	b082      	sub	sp, #8
- 8008b88:	af00      	add	r7, sp, #0
- 8008b8a:	6078      	str	r0, [r7, #4]
- 8008b8c:	6039      	str	r1, [r7, #0]
-  LWIP_ASSERT_CORE_LOCKED();
-  if (pcb != NULL) {
- 8008b8e:	687b      	ldr	r3, [r7, #4]
- 8008b90:	2b00      	cmp	r3, #0
- 8008b92:	d00e      	beq.n	8008bb2 <tcp_recv+0x2e>
-    LWIP_ASSERT("invalid socket state for recv callback", pcb->state != LISTEN);
- 8008b94:	687b      	ldr	r3, [r7, #4]
- 8008b96:	7d1b      	ldrb	r3, [r3, #20]
- 8008b98:	2b01      	cmp	r3, #1
- 8008b9a:	d106      	bne.n	8008baa <tcp_recv+0x26>
- 8008b9c:	4b07      	ldr	r3, [pc, #28]	; (8008bbc <tcp_recv+0x38>)
- 8008b9e:	f240 72df 	movw	r2, #2015	; 0x7df
- 8008ba2:	4907      	ldr	r1, [pc, #28]	; (8008bc0 <tcp_recv+0x3c>)
- 8008ba4:	4807      	ldr	r0, [pc, #28]	; (8008bc4 <tcp_recv+0x40>)
- 8008ba6:	f008 f80f 	bl	8010bc8 <iprintf>
-    pcb->recv = recv;
- 8008baa:	687b      	ldr	r3, [r7, #4]
- 8008bac:	683a      	ldr	r2, [r7, #0]
- 8008bae:	f8c3 2084 	str.w	r2, [r3, #132]	; 0x84
-  }
-}
- 8008bb2:	bf00      	nop
- 8008bb4:	3708      	adds	r7, #8
- 8008bb6:	46bd      	mov	sp, r7
- 8008bb8:	bd80      	pop	{r7, pc}
- 8008bba:	bf00      	nop
- 8008bbc:	08012a08 	.word	0x08012a08
- 8008bc0:	08012fa4 	.word	0x08012fa4
- 8008bc4:	08012a4c 	.word	0x08012a4c
-
-08008bc8 <tcp_sent>:
- * @param pcb tcp_pcb to set the sent callback
- * @param sent callback function to call for this pcb when data is successfully sent
- */
-void
-tcp_sent(struct tcp_pcb *pcb, tcp_sent_fn sent)
-{
- 8008bc8:	b580      	push	{r7, lr}
- 8008bca:	b082      	sub	sp, #8
- 8008bcc:	af00      	add	r7, sp, #0
- 8008bce:	6078      	str	r0, [r7, #4]
- 8008bd0:	6039      	str	r1, [r7, #0]
-  LWIP_ASSERT_CORE_LOCKED();
-  if (pcb != NULL) {
- 8008bd2:	687b      	ldr	r3, [r7, #4]
- 8008bd4:	2b00      	cmp	r3, #0
- 8008bd6:	d00e      	beq.n	8008bf6 <tcp_sent+0x2e>
-    LWIP_ASSERT("invalid socket state for sent callback", pcb->state != LISTEN);
- 8008bd8:	687b      	ldr	r3, [r7, #4]
- 8008bda:	7d1b      	ldrb	r3, [r3, #20]
- 8008bdc:	2b01      	cmp	r3, #1
- 8008bde:	d106      	bne.n	8008bee <tcp_sent+0x26>
- 8008be0:	4b07      	ldr	r3, [pc, #28]	; (8008c00 <tcp_sent+0x38>)
- 8008be2:	f240 72f3 	movw	r2, #2035	; 0x7f3
- 8008be6:	4907      	ldr	r1, [pc, #28]	; (8008c04 <tcp_sent+0x3c>)
- 8008be8:	4807      	ldr	r0, [pc, #28]	; (8008c08 <tcp_sent+0x40>)
- 8008bea:	f007 ffed 	bl	8010bc8 <iprintf>
-    pcb->sent = sent;
- 8008bee:	687b      	ldr	r3, [r7, #4]
- 8008bf0:	683a      	ldr	r2, [r7, #0]
- 8008bf2:	f8c3 2080 	str.w	r2, [r3, #128]	; 0x80
-  }
-}
- 8008bf6:	bf00      	nop
- 8008bf8:	3708      	adds	r7, #8
- 8008bfa:	46bd      	mov	sp, r7
- 8008bfc:	bd80      	pop	{r7, pc}
- 8008bfe:	bf00      	nop
- 8008c00:	08012a08 	.word	0x08012a08
- 8008c04:	08012fcc 	.word	0x08012fcc
- 8008c08:	08012a4c 	.word	0x08012a4c
-
-08008c0c <tcp_err>:
- * @param err callback function to call for this pcb when a fatal error
- *        has occurred on the connection
- */
-void
-tcp_err(struct tcp_pcb *pcb, tcp_err_fn err)
-{
- 8008c0c:	b580      	push	{r7, lr}
- 8008c0e:	b082      	sub	sp, #8
- 8008c10:	af00      	add	r7, sp, #0
- 8008c12:	6078      	str	r0, [r7, #4]
- 8008c14:	6039      	str	r1, [r7, #0]
-  LWIP_ASSERT_CORE_LOCKED();
-  if (pcb != NULL) {
- 8008c16:	687b      	ldr	r3, [r7, #4]
- 8008c18:	2b00      	cmp	r3, #0
- 8008c1a:	d00e      	beq.n	8008c3a <tcp_err+0x2e>
-    LWIP_ASSERT("invalid socket state for err callback", pcb->state != LISTEN);
- 8008c1c:	687b      	ldr	r3, [r7, #4]
- 8008c1e:	7d1b      	ldrb	r3, [r3, #20]
- 8008c20:	2b01      	cmp	r3, #1
- 8008c22:	d106      	bne.n	8008c32 <tcp_err+0x26>
- 8008c24:	4b07      	ldr	r3, [pc, #28]	; (8008c44 <tcp_err+0x38>)
- 8008c26:	f640 020d 	movw	r2, #2061	; 0x80d
- 8008c2a:	4907      	ldr	r1, [pc, #28]	; (8008c48 <tcp_err+0x3c>)
- 8008c2c:	4807      	ldr	r0, [pc, #28]	; (8008c4c <tcp_err+0x40>)
- 8008c2e:	f007 ffcb 	bl	8010bc8 <iprintf>
-    pcb->errf = err;
- 8008c32:	687b      	ldr	r3, [r7, #4]
- 8008c34:	683a      	ldr	r2, [r7, #0]
- 8008c36:	f8c3 2090 	str.w	r2, [r3, #144]	; 0x90
-  }
-}
- 8008c3a:	bf00      	nop
- 8008c3c:	3708      	adds	r7, #8
- 8008c3e:	46bd      	mov	sp, r7
- 8008c40:	bd80      	pop	{r7, pc}
- 8008c42:	bf00      	nop
- 8008c44:	08012a08 	.word	0x08012a08
- 8008c48:	08012ff4 	.word	0x08012ff4
- 8008c4c:	08012a4c 	.word	0x08012a4c
-
-08008c50 <tcp_pcb_purge>:
- *
- * @param pcb tcp_pcb to purge. The pcb itself is not deallocated!
- */
-void
-tcp_pcb_purge(struct tcp_pcb *pcb)
-{
- 8008c50:	b580      	push	{r7, lr}
- 8008c52:	b082      	sub	sp, #8
- 8008c54:	af00      	add	r7, sp, #0
- 8008c56:	6078      	str	r0, [r7, #4]
-  LWIP_ERROR("tcp_pcb_purge: invalid pcb", pcb != NULL, return);
- 8008c58:	687b      	ldr	r3, [r7, #4]
- 8008c5a:	2b00      	cmp	r3, #0
- 8008c5c:	d107      	bne.n	8008c6e <tcp_pcb_purge+0x1e>
- 8008c5e:	4b21      	ldr	r3, [pc, #132]	; (8008ce4 <tcp_pcb_purge+0x94>)
- 8008c60:	f640 0251 	movw	r2, #2129	; 0x851
- 8008c64:	4920      	ldr	r1, [pc, #128]	; (8008ce8 <tcp_pcb_purge+0x98>)
- 8008c66:	4821      	ldr	r0, [pc, #132]	; (8008cec <tcp_pcb_purge+0x9c>)
- 8008c68:	f007 ffae 	bl	8010bc8 <iprintf>
- 8008c6c:	e037      	b.n	8008cde <tcp_pcb_purge+0x8e>
-
-  if (pcb->state != CLOSED &&
- 8008c6e:	687b      	ldr	r3, [r7, #4]
- 8008c70:	7d1b      	ldrb	r3, [r3, #20]
- 8008c72:	2b00      	cmp	r3, #0
- 8008c74:	d033      	beq.n	8008cde <tcp_pcb_purge+0x8e>
-      pcb->state != TIME_WAIT &&
- 8008c76:	687b      	ldr	r3, [r7, #4]
- 8008c78:	7d1b      	ldrb	r3, [r3, #20]
-  if (pcb->state != CLOSED &&
- 8008c7a:	2b0a      	cmp	r3, #10
- 8008c7c:	d02f      	beq.n	8008cde <tcp_pcb_purge+0x8e>
-      pcb->state != LISTEN) {
- 8008c7e:	687b      	ldr	r3, [r7, #4]
- 8008c80:	7d1b      	ldrb	r3, [r3, #20]
-      pcb->state != TIME_WAIT &&
- 8008c82:	2b01      	cmp	r3, #1
- 8008c84:	d02b      	beq.n	8008cde <tcp_pcb_purge+0x8e>
-
-    LWIP_DEBUGF(TCP_DEBUG, ("tcp_pcb_purge\n"));
-
-    tcp_backlog_accepted(pcb);
-
-    if (pcb->refused_data != NULL) {
- 8008c86:	687b      	ldr	r3, [r7, #4]
- 8008c88:	6f9b      	ldr	r3, [r3, #120]	; 0x78
- 8008c8a:	2b00      	cmp	r3, #0
- 8008c8c:	d007      	beq.n	8008c9e <tcp_pcb_purge+0x4e>
-      LWIP_DEBUGF(TCP_DEBUG, ("tcp_pcb_purge: data left on ->refused_data\n"));
-      pbuf_free(pcb->refused_data);
- 8008c8e:	687b      	ldr	r3, [r7, #4]
- 8008c90:	6f9b      	ldr	r3, [r3, #120]	; 0x78
- 8008c92:	4618      	mov	r0, r3
- 8008c94:	f7fe f99e 	bl	8006fd4 <pbuf_free>
-      pcb->refused_data = NULL;
- 8008c98:	687b      	ldr	r3, [r7, #4]
- 8008c9a:	2200      	movs	r2, #0
- 8008c9c:	679a      	str	r2, [r3, #120]	; 0x78
-    }
-    if (pcb->unacked != NULL) {
-      LWIP_DEBUGF(TCP_DEBUG, ("tcp_pcb_purge: data left on ->unacked\n"));
-    }
-#if TCP_QUEUE_OOSEQ
-    if (pcb->ooseq != NULL) {
- 8008c9e:	687b      	ldr	r3, [r7, #4]
- 8008ca0:	6f5b      	ldr	r3, [r3, #116]	; 0x74
- 8008ca2:	2b00      	cmp	r3, #0
- 8008ca4:	d002      	beq.n	8008cac <tcp_pcb_purge+0x5c>
-      LWIP_DEBUGF(TCP_DEBUG, ("tcp_pcb_purge: data left on ->ooseq\n"));
-      tcp_free_ooseq(pcb);
- 8008ca6:	6878      	ldr	r0, [r7, #4]
- 8008ca8:	f000 f98c 	bl	8008fc4 <tcp_free_ooseq>
-    }
-#endif /* TCP_QUEUE_OOSEQ */
-
-    /* Stop the retransmission timer as it will expect data on unacked
-       queue if it fires */
-    pcb->rtime = -1;
- 8008cac:	687b      	ldr	r3, [r7, #4]
- 8008cae:	f64f 72ff 	movw	r2, #65535	; 0xffff
- 8008cb2:	861a      	strh	r2, [r3, #48]	; 0x30
-
-    tcp_segs_free(pcb->unsent);
- 8008cb4:	687b      	ldr	r3, [r7, #4]
- 8008cb6:	6edb      	ldr	r3, [r3, #108]	; 0x6c
- 8008cb8:	4618      	mov	r0, r3
- 8008cba:	f7ff fd47 	bl	800874c <tcp_segs_free>
-    tcp_segs_free(pcb->unacked);
- 8008cbe:	687b      	ldr	r3, [r7, #4]
- 8008cc0:	6f1b      	ldr	r3, [r3, #112]	; 0x70
- 8008cc2:	4618      	mov	r0, r3
- 8008cc4:	f7ff fd42 	bl	800874c <tcp_segs_free>
-    pcb->unacked = pcb->unsent = NULL;
- 8008cc8:	687b      	ldr	r3, [r7, #4]
- 8008cca:	2200      	movs	r2, #0
- 8008ccc:	66da      	str	r2, [r3, #108]	; 0x6c
- 8008cce:	687b      	ldr	r3, [r7, #4]
- 8008cd0:	6eda      	ldr	r2, [r3, #108]	; 0x6c
- 8008cd2:	687b      	ldr	r3, [r7, #4]
- 8008cd4:	671a      	str	r2, [r3, #112]	; 0x70
-#if TCP_OVERSIZE
-    pcb->unsent_oversize = 0;
- 8008cd6:	687b      	ldr	r3, [r7, #4]
- 8008cd8:	2200      	movs	r2, #0
- 8008cda:	f8a3 2068 	strh.w	r2, [r3, #104]	; 0x68
-#endif /* TCP_OVERSIZE */
-  }
-}
- 8008cde:	3708      	adds	r7, #8
- 8008ce0:	46bd      	mov	sp, r7
- 8008ce2:	bd80      	pop	{r7, pc}
- 8008ce4:	08012a08 	.word	0x08012a08
- 8008ce8:	08013054 	.word	0x08013054
- 8008cec:	08012a4c 	.word	0x08012a4c
-
-08008cf0 <tcp_pcb_remove>:
- * @param pcblist PCB list to purge.
- * @param pcb tcp_pcb to purge. The pcb itself is NOT deallocated!
- */
-void
-tcp_pcb_remove(struct tcp_pcb **pcblist, struct tcp_pcb *pcb)
-{
- 8008cf0:	b580      	push	{r7, lr}
- 8008cf2:	b084      	sub	sp, #16
- 8008cf4:	af00      	add	r7, sp, #0
- 8008cf6:	6078      	str	r0, [r7, #4]
- 8008cf8:	6039      	str	r1, [r7, #0]
-  LWIP_ASSERT("tcp_pcb_remove: invalid pcb", pcb != NULL);
- 8008cfa:	683b      	ldr	r3, [r7, #0]
- 8008cfc:	2b00      	cmp	r3, #0
- 8008cfe:	d106      	bne.n	8008d0e <tcp_pcb_remove+0x1e>
- 8008d00:	4b3e      	ldr	r3, [pc, #248]	; (8008dfc <tcp_pcb_remove+0x10c>)
- 8008d02:	f640 0283 	movw	r2, #2179	; 0x883
- 8008d06:	493e      	ldr	r1, [pc, #248]	; (8008e00 <tcp_pcb_remove+0x110>)
- 8008d08:	483e      	ldr	r0, [pc, #248]	; (8008e04 <tcp_pcb_remove+0x114>)
- 8008d0a:	f007 ff5d 	bl	8010bc8 <iprintf>
-  LWIP_ASSERT("tcp_pcb_remove: invalid pcblist", pcblist != NULL);
- 8008d0e:	687b      	ldr	r3, [r7, #4]
- 8008d10:	2b00      	cmp	r3, #0
- 8008d12:	d106      	bne.n	8008d22 <tcp_pcb_remove+0x32>
- 8008d14:	4b39      	ldr	r3, [pc, #228]	; (8008dfc <tcp_pcb_remove+0x10c>)
- 8008d16:	f640 0284 	movw	r2, #2180	; 0x884
- 8008d1a:	493b      	ldr	r1, [pc, #236]	; (8008e08 <tcp_pcb_remove+0x118>)
- 8008d1c:	4839      	ldr	r0, [pc, #228]	; (8008e04 <tcp_pcb_remove+0x114>)
- 8008d1e:	f007 ff53 	bl	8010bc8 <iprintf>
-
-  TCP_RMV(pcblist, pcb);
- 8008d22:	687b      	ldr	r3, [r7, #4]
- 8008d24:	681b      	ldr	r3, [r3, #0]
- 8008d26:	683a      	ldr	r2, [r7, #0]
- 8008d28:	429a      	cmp	r2, r3
- 8008d2a:	d105      	bne.n	8008d38 <tcp_pcb_remove+0x48>
- 8008d2c:	687b      	ldr	r3, [r7, #4]
- 8008d2e:	681b      	ldr	r3, [r3, #0]
- 8008d30:	68da      	ldr	r2, [r3, #12]
- 8008d32:	687b      	ldr	r3, [r7, #4]
- 8008d34:	601a      	str	r2, [r3, #0]
- 8008d36:	e013      	b.n	8008d60 <tcp_pcb_remove+0x70>
- 8008d38:	687b      	ldr	r3, [r7, #4]
- 8008d3a:	681b      	ldr	r3, [r3, #0]
- 8008d3c:	60fb      	str	r3, [r7, #12]
- 8008d3e:	e00c      	b.n	8008d5a <tcp_pcb_remove+0x6a>
- 8008d40:	68fb      	ldr	r3, [r7, #12]
- 8008d42:	68db      	ldr	r3, [r3, #12]
- 8008d44:	683a      	ldr	r2, [r7, #0]
- 8008d46:	429a      	cmp	r2, r3
- 8008d48:	d104      	bne.n	8008d54 <tcp_pcb_remove+0x64>
- 8008d4a:	683b      	ldr	r3, [r7, #0]
- 8008d4c:	68da      	ldr	r2, [r3, #12]
- 8008d4e:	68fb      	ldr	r3, [r7, #12]
- 8008d50:	60da      	str	r2, [r3, #12]
- 8008d52:	e005      	b.n	8008d60 <tcp_pcb_remove+0x70>
- 8008d54:	68fb      	ldr	r3, [r7, #12]
- 8008d56:	68db      	ldr	r3, [r3, #12]
- 8008d58:	60fb      	str	r3, [r7, #12]
- 8008d5a:	68fb      	ldr	r3, [r7, #12]
- 8008d5c:	2b00      	cmp	r3, #0
- 8008d5e:	d1ef      	bne.n	8008d40 <tcp_pcb_remove+0x50>
- 8008d60:	683b      	ldr	r3, [r7, #0]
- 8008d62:	2200      	movs	r2, #0
- 8008d64:	60da      	str	r2, [r3, #12]
-
-  tcp_pcb_purge(pcb);
- 8008d66:	6838      	ldr	r0, [r7, #0]
- 8008d68:	f7ff ff72 	bl	8008c50 <tcp_pcb_purge>
-
-  /* if there is an outstanding delayed ACKs, send it */
-  if ((pcb->state != TIME_WAIT) &&
- 8008d6c:	683b      	ldr	r3, [r7, #0]
- 8008d6e:	7d1b      	ldrb	r3, [r3, #20]
- 8008d70:	2b0a      	cmp	r3, #10
- 8008d72:	d013      	beq.n	8008d9c <tcp_pcb_remove+0xac>
-      (pcb->state != LISTEN) &&
- 8008d74:	683b      	ldr	r3, [r7, #0]
- 8008d76:	7d1b      	ldrb	r3, [r3, #20]
-  if ((pcb->state != TIME_WAIT) &&
- 8008d78:	2b01      	cmp	r3, #1
- 8008d7a:	d00f      	beq.n	8008d9c <tcp_pcb_remove+0xac>
-      (pcb->flags & TF_ACK_DELAY)) {
- 8008d7c:	683b      	ldr	r3, [r7, #0]
- 8008d7e:	8b5b      	ldrh	r3, [r3, #26]
- 8008d80:	f003 0301 	and.w	r3, r3, #1
-      (pcb->state != LISTEN) &&
- 8008d84:	2b00      	cmp	r3, #0
- 8008d86:	d009      	beq.n	8008d9c <tcp_pcb_remove+0xac>
-    tcp_ack_now(pcb);
- 8008d88:	683b      	ldr	r3, [r7, #0]
- 8008d8a:	8b5b      	ldrh	r3, [r3, #26]
- 8008d8c:	f043 0302 	orr.w	r3, r3, #2
- 8008d90:	b29a      	uxth	r2, r3
- 8008d92:	683b      	ldr	r3, [r7, #0]
- 8008d94:	835a      	strh	r2, [r3, #26]
-    tcp_output(pcb);
- 8008d96:	6838      	ldr	r0, [r7, #0]
- 8008d98:	f003 fc2c 	bl	800c5f4 <tcp_output>
-  }
-
-  if (pcb->state != LISTEN) {
- 8008d9c:	683b      	ldr	r3, [r7, #0]
- 8008d9e:	7d1b      	ldrb	r3, [r3, #20]
- 8008da0:	2b01      	cmp	r3, #1
- 8008da2:	d020      	beq.n	8008de6 <tcp_pcb_remove+0xf6>
-    LWIP_ASSERT("unsent segments leaking", pcb->unsent == NULL);
- 8008da4:	683b      	ldr	r3, [r7, #0]
- 8008da6:	6edb      	ldr	r3, [r3, #108]	; 0x6c
- 8008da8:	2b00      	cmp	r3, #0
- 8008daa:	d006      	beq.n	8008dba <tcp_pcb_remove+0xca>
- 8008dac:	4b13      	ldr	r3, [pc, #76]	; (8008dfc <tcp_pcb_remove+0x10c>)
- 8008dae:	f640 0293 	movw	r2, #2195	; 0x893
- 8008db2:	4916      	ldr	r1, [pc, #88]	; (8008e0c <tcp_pcb_remove+0x11c>)
- 8008db4:	4813      	ldr	r0, [pc, #76]	; (8008e04 <tcp_pcb_remove+0x114>)
- 8008db6:	f007 ff07 	bl	8010bc8 <iprintf>
-    LWIP_ASSERT("unacked segments leaking", pcb->unacked == NULL);
- 8008dba:	683b      	ldr	r3, [r7, #0]
- 8008dbc:	6f1b      	ldr	r3, [r3, #112]	; 0x70
- 8008dbe:	2b00      	cmp	r3, #0
- 8008dc0:	d006      	beq.n	8008dd0 <tcp_pcb_remove+0xe0>
- 8008dc2:	4b0e      	ldr	r3, [pc, #56]	; (8008dfc <tcp_pcb_remove+0x10c>)
- 8008dc4:	f640 0294 	movw	r2, #2196	; 0x894
- 8008dc8:	4911      	ldr	r1, [pc, #68]	; (8008e10 <tcp_pcb_remove+0x120>)
- 8008dca:	480e      	ldr	r0, [pc, #56]	; (8008e04 <tcp_pcb_remove+0x114>)
- 8008dcc:	f007 fefc 	bl	8010bc8 <iprintf>
-#if TCP_QUEUE_OOSEQ
-    LWIP_ASSERT("ooseq segments leaking", pcb->ooseq == NULL);
- 8008dd0:	683b      	ldr	r3, [r7, #0]
- 8008dd2:	6f5b      	ldr	r3, [r3, #116]	; 0x74
- 8008dd4:	2b00      	cmp	r3, #0
- 8008dd6:	d006      	beq.n	8008de6 <tcp_pcb_remove+0xf6>
- 8008dd8:	4b08      	ldr	r3, [pc, #32]	; (8008dfc <tcp_pcb_remove+0x10c>)
- 8008dda:	f640 0296 	movw	r2, #2198	; 0x896
- 8008dde:	490d      	ldr	r1, [pc, #52]	; (8008e14 <tcp_pcb_remove+0x124>)
- 8008de0:	4808      	ldr	r0, [pc, #32]	; (8008e04 <tcp_pcb_remove+0x114>)
- 8008de2:	f007 fef1 	bl	8010bc8 <iprintf>
-#endif /* TCP_QUEUE_OOSEQ */
-  }
-
-  pcb->state = CLOSED;
- 8008de6:	683b      	ldr	r3, [r7, #0]
- 8008de8:	2200      	movs	r2, #0
- 8008dea:	751a      	strb	r2, [r3, #20]
-  /* reset the local port to prevent the pcb from being 'bound' */
-  pcb->local_port = 0;
- 8008dec:	683b      	ldr	r3, [r7, #0]
- 8008dee:	2200      	movs	r2, #0
- 8008df0:	82da      	strh	r2, [r3, #22]
-
-  LWIP_ASSERT("tcp_pcb_remove: tcp_pcbs_sane()", tcp_pcbs_sane());
-}
- 8008df2:	bf00      	nop
- 8008df4:	3710      	adds	r7, #16
- 8008df6:	46bd      	mov	sp, r7
- 8008df8:	bd80      	pop	{r7, pc}
- 8008dfa:	bf00      	nop
- 8008dfc:	08012a08 	.word	0x08012a08
- 8008e00:	08013070 	.word	0x08013070
- 8008e04:	08012a4c 	.word	0x08012a4c
- 8008e08:	0801308c 	.word	0x0801308c
- 8008e0c:	080130ac 	.word	0x080130ac
- 8008e10:	080130c4 	.word	0x080130c4
- 8008e14:	080130e0 	.word	0x080130e0
-
-08008e18 <tcp_next_iss>:
- *
- * @return u32_t pseudo random sequence number
- */
-u32_t
-tcp_next_iss(struct tcp_pcb *pcb)
-{
- 8008e18:	b580      	push	{r7, lr}
- 8008e1a:	b082      	sub	sp, #8
- 8008e1c:	af00      	add	r7, sp, #0
- 8008e1e:	6078      	str	r0, [r7, #4]
-  LWIP_ASSERT("tcp_next_iss: invalid pcb", pcb != NULL);
-  return LWIP_HOOK_TCP_ISN(&pcb->local_ip, pcb->local_port, &pcb->remote_ip, pcb->remote_port);
-#else /* LWIP_HOOK_TCP_ISN */
-  static u32_t iss = 6510;
-
-  LWIP_ASSERT("tcp_next_iss: invalid pcb", pcb != NULL);
- 8008e20:	687b      	ldr	r3, [r7, #4]
- 8008e22:	2b00      	cmp	r3, #0
- 8008e24:	d106      	bne.n	8008e34 <tcp_next_iss+0x1c>
- 8008e26:	4b0a      	ldr	r3, [pc, #40]	; (8008e50 <tcp_next_iss+0x38>)
- 8008e28:	f640 02af 	movw	r2, #2223	; 0x8af
- 8008e2c:	4909      	ldr	r1, [pc, #36]	; (8008e54 <tcp_next_iss+0x3c>)
- 8008e2e:	480a      	ldr	r0, [pc, #40]	; (8008e58 <tcp_next_iss+0x40>)
- 8008e30:	f007 feca 	bl	8010bc8 <iprintf>
-  LWIP_UNUSED_ARG(pcb);
-
-  iss += tcp_ticks;       /* XXX */
- 8008e34:	4b09      	ldr	r3, [pc, #36]	; (8008e5c <tcp_next_iss+0x44>)
- 8008e36:	681a      	ldr	r2, [r3, #0]
- 8008e38:	4b09      	ldr	r3, [pc, #36]	; (8008e60 <tcp_next_iss+0x48>)
- 8008e3a:	681b      	ldr	r3, [r3, #0]
- 8008e3c:	4413      	add	r3, r2
- 8008e3e:	4a07      	ldr	r2, [pc, #28]	; (8008e5c <tcp_next_iss+0x44>)
- 8008e40:	6013      	str	r3, [r2, #0]
-  return iss;
- 8008e42:	4b06      	ldr	r3, [pc, #24]	; (8008e5c <tcp_next_iss+0x44>)
- 8008e44:	681b      	ldr	r3, [r3, #0]
-#endif /* LWIP_HOOK_TCP_ISN */
-}
- 8008e46:	4618      	mov	r0, r3
- 8008e48:	3708      	adds	r7, #8
- 8008e4a:	46bd      	mov	sp, r7
- 8008e4c:	bd80      	pop	{r7, pc}
- 8008e4e:	bf00      	nop
- 8008e50:	08012a08 	.word	0x08012a08
- 8008e54:	080130f8 	.word	0x080130f8
- 8008e58:	08012a4c 	.word	0x08012a4c
- 8008e5c:	2400006c 	.word	0x2400006c
- 8008e60:	24007b6c 	.word	0x24007b6c
-
-08008e64 <tcp_eff_send_mss_netif>:
- * by calculating the minimum of TCP_MSS and the mtu (if set) of the target
- * netif (if not NULL).
- */
-u16_t
-tcp_eff_send_mss_netif(u16_t sendmss, struct netif *outif, const ip_addr_t *dest)
-{
- 8008e64:	b580      	push	{r7, lr}
- 8008e66:	b086      	sub	sp, #24
- 8008e68:	af00      	add	r7, sp, #0
- 8008e6a:	4603      	mov	r3, r0
- 8008e6c:	60b9      	str	r1, [r7, #8]
- 8008e6e:	607a      	str	r2, [r7, #4]
- 8008e70:	81fb      	strh	r3, [r7, #14]
-  u16_t mss_s;
-  u16_t mtu;
-
-  LWIP_UNUSED_ARG(dest); /* in case IPv6 is disabled */
-
-  LWIP_ASSERT("tcp_eff_send_mss_netif: invalid dst_ip", dest != NULL);
- 8008e72:	687b      	ldr	r3, [r7, #4]
- 8008e74:	2b00      	cmp	r3, #0
- 8008e76:	d106      	bne.n	8008e86 <tcp_eff_send_mss_netif+0x22>
- 8008e78:	4b14      	ldr	r3, [pc, #80]	; (8008ecc <tcp_eff_send_mss_netif+0x68>)
- 8008e7a:	f640 02c5 	movw	r2, #2245	; 0x8c5
- 8008e7e:	4914      	ldr	r1, [pc, #80]	; (8008ed0 <tcp_eff_send_mss_netif+0x6c>)
- 8008e80:	4814      	ldr	r0, [pc, #80]	; (8008ed4 <tcp_eff_send_mss_netif+0x70>)
- 8008e82:	f007 fea1 	bl	8010bc8 <iprintf>
-  else
-#endif /* LWIP_IPV4 */
-#endif /* LWIP_IPV6 */
-#if LWIP_IPV4
-  {
-    if (outif == NULL) {
- 8008e86:	68bb      	ldr	r3, [r7, #8]
- 8008e88:	2b00      	cmp	r3, #0
- 8008e8a:	d101      	bne.n	8008e90 <tcp_eff_send_mss_netif+0x2c>
-      return sendmss;
- 8008e8c:	89fb      	ldrh	r3, [r7, #14]
- 8008e8e:	e019      	b.n	8008ec4 <tcp_eff_send_mss_netif+0x60>
-    }
-    mtu = outif->mtu;
- 8008e90:	68bb      	ldr	r3, [r7, #8]
- 8008e92:	8c9b      	ldrh	r3, [r3, #36]	; 0x24
- 8008e94:	82fb      	strh	r3, [r7, #22]
-  }
-#endif /* LWIP_IPV4 */
-
-  if (mtu != 0) {
- 8008e96:	8afb      	ldrh	r3, [r7, #22]
- 8008e98:	2b00      	cmp	r3, #0
- 8008e9a:	d012      	beq.n	8008ec2 <tcp_eff_send_mss_netif+0x5e>
-    else
-#endif /* LWIP_IPV4 */
-#endif /* LWIP_IPV6 */
-#if LWIP_IPV4
-    {
-      offset = IP_HLEN + TCP_HLEN;
- 8008e9c:	2328      	movs	r3, #40	; 0x28
- 8008e9e:	82bb      	strh	r3, [r7, #20]
-    }
-#endif /* LWIP_IPV4 */
-    mss_s = (mtu > offset) ? (u16_t)(mtu - offset) : 0;
- 8008ea0:	8afa      	ldrh	r2, [r7, #22]
- 8008ea2:	8abb      	ldrh	r3, [r7, #20]
- 8008ea4:	429a      	cmp	r2, r3
- 8008ea6:	d904      	bls.n	8008eb2 <tcp_eff_send_mss_netif+0x4e>
- 8008ea8:	8afa      	ldrh	r2, [r7, #22]
- 8008eaa:	8abb      	ldrh	r3, [r7, #20]
- 8008eac:	1ad3      	subs	r3, r2, r3
- 8008eae:	b29b      	uxth	r3, r3
- 8008eb0:	e000      	b.n	8008eb4 <tcp_eff_send_mss_netif+0x50>
- 8008eb2:	2300      	movs	r3, #0
- 8008eb4:	827b      	strh	r3, [r7, #18]
-    /* RFC 1122, chap 4.2.2.6:
-     * Eff.snd.MSS = min(SendMSS+20, MMS_S) - TCPhdrsize - IPoptionsize
-     * We correct for TCP options in tcp_write(), and don't support IP options.
-     */
-    sendmss = LWIP_MIN(sendmss, mss_s);
- 8008eb6:	8a7a      	ldrh	r2, [r7, #18]
- 8008eb8:	89fb      	ldrh	r3, [r7, #14]
- 8008eba:	4293      	cmp	r3, r2
- 8008ebc:	bf28      	it	cs
- 8008ebe:	4613      	movcs	r3, r2
- 8008ec0:	81fb      	strh	r3, [r7, #14]
-  }
-  return sendmss;
- 8008ec2:	89fb      	ldrh	r3, [r7, #14]
-}
- 8008ec4:	4618      	mov	r0, r3
- 8008ec6:	3718      	adds	r7, #24
- 8008ec8:	46bd      	mov	sp, r7
- 8008eca:	bd80      	pop	{r7, pc}
- 8008ecc:	08012a08 	.word	0x08012a08
- 8008ed0:	08013114 	.word	0x08013114
- 8008ed4:	08012a4c 	.word	0x08012a4c
-
-08008ed8 <tcp_netif_ip_addr_changed_pcblist>:
-#endif /* TCP_CALCULATE_EFF_SEND_MSS */
-
-/** Helper function for tcp_netif_ip_addr_changed() that iterates a pcb list */
-static void
-tcp_netif_ip_addr_changed_pcblist(const ip_addr_t *old_addr, struct tcp_pcb *pcb_list)
-{
- 8008ed8:	b580      	push	{r7, lr}
- 8008eda:	b084      	sub	sp, #16
- 8008edc:	af00      	add	r7, sp, #0
- 8008ede:	6078      	str	r0, [r7, #4]
- 8008ee0:	6039      	str	r1, [r7, #0]
-  struct tcp_pcb *pcb;
-  pcb = pcb_list;
- 8008ee2:	683b      	ldr	r3, [r7, #0]
- 8008ee4:	60fb      	str	r3, [r7, #12]
-
-  LWIP_ASSERT("tcp_netif_ip_addr_changed_pcblist: invalid old_addr", old_addr != NULL);
- 8008ee6:	687b      	ldr	r3, [r7, #4]
- 8008ee8:	2b00      	cmp	r3, #0
- 8008eea:	d11d      	bne.n	8008f28 <tcp_netif_ip_addr_changed_pcblist+0x50>
- 8008eec:	4b12      	ldr	r3, [pc, #72]	; (8008f38 <tcp_netif_ip_addr_changed_pcblist+0x60>)
- 8008eee:	f44f 6210 	mov.w	r2, #2304	; 0x900
- 8008ef2:	4912      	ldr	r1, [pc, #72]	; (8008f3c <tcp_netif_ip_addr_changed_pcblist+0x64>)
- 8008ef4:	4812      	ldr	r0, [pc, #72]	; (8008f40 <tcp_netif_ip_addr_changed_pcblist+0x68>)
- 8008ef6:	f007 fe67 	bl	8010bc8 <iprintf>
-
-  while (pcb != NULL) {
- 8008efa:	e015      	b.n	8008f28 <tcp_netif_ip_addr_changed_pcblist+0x50>
-    /* PCB bound to current local interface address? */
-    if (ip_addr_cmp(&pcb->local_ip, old_addr)
- 8008efc:	68fb      	ldr	r3, [r7, #12]
- 8008efe:	681a      	ldr	r2, [r3, #0]
- 8008f00:	687b      	ldr	r3, [r7, #4]
- 8008f02:	681b      	ldr	r3, [r3, #0]
- 8008f04:	429a      	cmp	r2, r3
- 8008f06:	d10c      	bne.n	8008f22 <tcp_netif_ip_addr_changed_pcblist+0x4a>
-        /* connections to link-local addresses must persist (RFC3927 ch. 1.9) */
-        && (!IP_IS_V4_VAL(pcb->local_ip) || !ip4_addr_islinklocal(ip_2_ip4(&pcb->local_ip)))
-#endif /* LWIP_AUTOIP */
-       ) {
-      /* this connection must be aborted */
-      struct tcp_pcb *next = pcb->next;
- 8008f08:	68fb      	ldr	r3, [r7, #12]
- 8008f0a:	68db      	ldr	r3, [r3, #12]
- 8008f0c:	60bb      	str	r3, [r7, #8]
-      LWIP_DEBUGF(NETIF_DEBUG | LWIP_DBG_STATE, ("netif_set_ipaddr: aborting TCP pcb %p\n", (void *)pcb));
- 8008f0e:	68f9      	ldr	r1, [r7, #12]
- 8008f10:	480c      	ldr	r0, [pc, #48]	; (8008f44 <tcp_netif_ip_addr_changed_pcblist+0x6c>)
- 8008f12:	f007 fe59 	bl	8010bc8 <iprintf>
-      tcp_abort(pcb);
- 8008f16:	68f8      	ldr	r0, [r7, #12]
- 8008f18:	f7fe fde4 	bl	8007ae4 <tcp_abort>
-      pcb = next;
- 8008f1c:	68bb      	ldr	r3, [r7, #8]
- 8008f1e:	60fb      	str	r3, [r7, #12]
- 8008f20:	e002      	b.n	8008f28 <tcp_netif_ip_addr_changed_pcblist+0x50>
-    } else {
-      pcb = pcb->next;
- 8008f22:	68fb      	ldr	r3, [r7, #12]
- 8008f24:	68db      	ldr	r3, [r3, #12]
- 8008f26:	60fb      	str	r3, [r7, #12]
-  while (pcb != NULL) {
- 8008f28:	68fb      	ldr	r3, [r7, #12]
- 8008f2a:	2b00      	cmp	r3, #0
- 8008f2c:	d1e6      	bne.n	8008efc <tcp_netif_ip_addr_changed_pcblist+0x24>
-    }
-  }
-}
- 8008f2e:	bf00      	nop
- 8008f30:	bf00      	nop
- 8008f32:	3710      	adds	r7, #16
- 8008f34:	46bd      	mov	sp, r7
- 8008f36:	bd80      	pop	{r7, pc}
- 8008f38:	08012a08 	.word	0x08012a08
- 8008f3c:	0801313c 	.word	0x0801313c
- 8008f40:	08012a4c 	.word	0x08012a4c
- 8008f44:	08013170 	.word	0x08013170
-
-08008f48 <tcp_netif_ip_addr_changed>:
- * @param old_addr IP address of the netif before change
- * @param new_addr IP address of the netif after change or NULL if netif has been removed
- */
-void
-tcp_netif_ip_addr_changed(const ip_addr_t *old_addr, const ip_addr_t *new_addr)
-{
- 8008f48:	b580      	push	{r7, lr}
- 8008f4a:	b084      	sub	sp, #16
- 8008f4c:	af00      	add	r7, sp, #0
- 8008f4e:	6078      	str	r0, [r7, #4]
- 8008f50:	6039      	str	r1, [r7, #0]
-  struct tcp_pcb_listen *lpcb;
-
-  if (!ip_addr_isany(old_addr)) {
- 8008f52:	687b      	ldr	r3, [r7, #4]
- 8008f54:	2b00      	cmp	r3, #0
- 8008f56:	d02a      	beq.n	8008fae <tcp_netif_ip_addr_changed+0x66>
- 8008f58:	687b      	ldr	r3, [r7, #4]
- 8008f5a:	681b      	ldr	r3, [r3, #0]
- 8008f5c:	2b00      	cmp	r3, #0
- 8008f5e:	d026      	beq.n	8008fae <tcp_netif_ip_addr_changed+0x66>
-    tcp_netif_ip_addr_changed_pcblist(old_addr, tcp_active_pcbs);
- 8008f60:	4b15      	ldr	r3, [pc, #84]	; (8008fb8 <tcp_netif_ip_addr_changed+0x70>)
- 8008f62:	681b      	ldr	r3, [r3, #0]
- 8008f64:	4619      	mov	r1, r3
- 8008f66:	6878      	ldr	r0, [r7, #4]
- 8008f68:	f7ff ffb6 	bl	8008ed8 <tcp_netif_ip_addr_changed_pcblist>
-    tcp_netif_ip_addr_changed_pcblist(old_addr, tcp_bound_pcbs);
- 8008f6c:	4b13      	ldr	r3, [pc, #76]	; (8008fbc <tcp_netif_ip_addr_changed+0x74>)
- 8008f6e:	681b      	ldr	r3, [r3, #0]
- 8008f70:	4619      	mov	r1, r3
- 8008f72:	6878      	ldr	r0, [r7, #4]
- 8008f74:	f7ff ffb0 	bl	8008ed8 <tcp_netif_ip_addr_changed_pcblist>
-
-    if (!ip_addr_isany(new_addr)) {
- 8008f78:	683b      	ldr	r3, [r7, #0]
- 8008f7a:	2b00      	cmp	r3, #0
- 8008f7c:	d017      	beq.n	8008fae <tcp_netif_ip_addr_changed+0x66>
- 8008f7e:	683b      	ldr	r3, [r7, #0]
- 8008f80:	681b      	ldr	r3, [r3, #0]
- 8008f82:	2b00      	cmp	r3, #0
- 8008f84:	d013      	beq.n	8008fae <tcp_netif_ip_addr_changed+0x66>
-      /* PCB bound to current local interface address? */
-      for (lpcb = tcp_listen_pcbs.listen_pcbs; lpcb != NULL; lpcb = lpcb->next) {
- 8008f86:	4b0e      	ldr	r3, [pc, #56]	; (8008fc0 <tcp_netif_ip_addr_changed+0x78>)
- 8008f88:	681b      	ldr	r3, [r3, #0]
- 8008f8a:	60fb      	str	r3, [r7, #12]
- 8008f8c:	e00c      	b.n	8008fa8 <tcp_netif_ip_addr_changed+0x60>
-        /* PCB bound to current local interface address? */
-        if (ip_addr_cmp(&lpcb->local_ip, old_addr)) {
- 8008f8e:	68fb      	ldr	r3, [r7, #12]
- 8008f90:	681a      	ldr	r2, [r3, #0]
- 8008f92:	687b      	ldr	r3, [r7, #4]
- 8008f94:	681b      	ldr	r3, [r3, #0]
- 8008f96:	429a      	cmp	r2, r3
- 8008f98:	d103      	bne.n	8008fa2 <tcp_netif_ip_addr_changed+0x5a>
-          /* The PCB is listening to the old ipaddr and
-            * is set to listen to the new one instead */
-          ip_addr_copy(lpcb->local_ip, *new_addr);
- 8008f9a:	683b      	ldr	r3, [r7, #0]
- 8008f9c:	681a      	ldr	r2, [r3, #0]
- 8008f9e:	68fb      	ldr	r3, [r7, #12]
- 8008fa0:	601a      	str	r2, [r3, #0]
-      for (lpcb = tcp_listen_pcbs.listen_pcbs; lpcb != NULL; lpcb = lpcb->next) {
- 8008fa2:	68fb      	ldr	r3, [r7, #12]
- 8008fa4:	68db      	ldr	r3, [r3, #12]
- 8008fa6:	60fb      	str	r3, [r7, #12]
- 8008fa8:	68fb      	ldr	r3, [r7, #12]
- 8008faa:	2b00      	cmp	r3, #0
- 8008fac:	d1ef      	bne.n	8008f8e <tcp_netif_ip_addr_changed+0x46>
-        }
-      }
-    }
-  }
-}
- 8008fae:	bf00      	nop
- 8008fb0:	3710      	adds	r7, #16
- 8008fb2:	46bd      	mov	sp, r7
- 8008fb4:	bd80      	pop	{r7, pc}
- 8008fb6:	bf00      	nop
- 8008fb8:	24007b78 	.word	0x24007b78
- 8008fbc:	24007b70 	.word	0x24007b70
- 8008fc0:	24007b74 	.word	0x24007b74
-
-08008fc4 <tcp_free_ooseq>:
-
-#if TCP_QUEUE_OOSEQ
-/* Free all ooseq pbufs (and possibly reset SACK state) */
-void
-tcp_free_ooseq(struct tcp_pcb *pcb)
-{
- 8008fc4:	b580      	push	{r7, lr}
- 8008fc6:	b082      	sub	sp, #8
- 8008fc8:	af00      	add	r7, sp, #0
- 8008fca:	6078      	str	r0, [r7, #4]
-  if (pcb->ooseq) {
- 8008fcc:	687b      	ldr	r3, [r7, #4]
- 8008fce:	6f5b      	ldr	r3, [r3, #116]	; 0x74
- 8008fd0:	2b00      	cmp	r3, #0
- 8008fd2:	d007      	beq.n	8008fe4 <tcp_free_ooseq+0x20>
-    tcp_segs_free(pcb->ooseq);
- 8008fd4:	687b      	ldr	r3, [r7, #4]
- 8008fd6:	6f5b      	ldr	r3, [r3, #116]	; 0x74
- 8008fd8:	4618      	mov	r0, r3
- 8008fda:	f7ff fbb7 	bl	800874c <tcp_segs_free>
-    pcb->ooseq = NULL;
- 8008fde:	687b      	ldr	r3, [r7, #4]
- 8008fe0:	2200      	movs	r2, #0
- 8008fe2:	675a      	str	r2, [r3, #116]	; 0x74
-#if LWIP_TCP_SACK_OUT
-    memset(pcb->rcv_sacks, 0, sizeof(pcb->rcv_sacks));
-#endif /* LWIP_TCP_SACK_OUT */
-  }
-}
- 8008fe4:	bf00      	nop
- 8008fe6:	3708      	adds	r7, #8
- 8008fe8:	46bd      	mov	sp, r7
- 8008fea:	bd80      	pop	{r7, pc}
-
-08008fec <tcp_input>:
- * @param p received TCP segment to process (p->payload pointing to the TCP header)
- * @param inp network interface on which this segment was received
- */
-void
-tcp_input(struct pbuf *p, struct netif *inp)
-{
- 8008fec:	b590      	push	{r4, r7, lr}
- 8008fee:	b08d      	sub	sp, #52	; 0x34
- 8008ff0:	af04      	add	r7, sp, #16
- 8008ff2:	6078      	str	r0, [r7, #4]
- 8008ff4:	6039      	str	r1, [r7, #0]
-  u8_t hdrlen_bytes;
-  err_t err;
-
-  LWIP_UNUSED_ARG(inp);
-  LWIP_ASSERT_CORE_LOCKED();
-  LWIP_ASSERT("tcp_input: invalid pbuf", p != NULL);
- 8008ff6:	687b      	ldr	r3, [r7, #4]
- 8008ff8:	2b00      	cmp	r3, #0
- 8008ffa:	d105      	bne.n	8009008 <tcp_input+0x1c>
- 8008ffc:	4b9b      	ldr	r3, [pc, #620]	; (800926c <tcp_input+0x280>)
- 8008ffe:	2283      	movs	r2, #131	; 0x83
- 8009000:	499b      	ldr	r1, [pc, #620]	; (8009270 <tcp_input+0x284>)
- 8009002:	489c      	ldr	r0, [pc, #624]	; (8009274 <tcp_input+0x288>)
- 8009004:	f007 fde0 	bl	8010bc8 <iprintf>
-  PERF_START;
-
-  TCP_STATS_INC(tcp.recv);
-  MIB2_STATS_INC(mib2.tcpinsegs);
-
-  tcphdr = (struct tcp_hdr *)p->payload;
- 8009008:	687b      	ldr	r3, [r7, #4]
- 800900a:	685b      	ldr	r3, [r3, #4]
- 800900c:	4a9a      	ldr	r2, [pc, #616]	; (8009278 <tcp_input+0x28c>)
- 800900e:	6013      	str	r3, [r2, #0]
-#if TCP_INPUT_DEBUG
-  tcp_debug_print(tcphdr);
-#endif
-
-  /* Check that TCP header fits in payload */
-  if (p->len < TCP_HLEN) {
- 8009010:	687b      	ldr	r3, [r7, #4]
- 8009012:	895b      	ldrh	r3, [r3, #10]
- 8009014:	2b13      	cmp	r3, #19
- 8009016:	f240 83d1 	bls.w	80097bc <tcp_input+0x7d0>
-    TCP_STATS_INC(tcp.lenerr);
-    goto dropped;
-  }
-
-  /* Don't even process incoming broadcasts/multicasts. */
-  if (ip_addr_isbroadcast(ip_current_dest_addr(), ip_current_netif()) ||
- 800901a:	4b98      	ldr	r3, [pc, #608]	; (800927c <tcp_input+0x290>)
- 800901c:	695b      	ldr	r3, [r3, #20]
- 800901e:	4a97      	ldr	r2, [pc, #604]	; (800927c <tcp_input+0x290>)
- 8009020:	6812      	ldr	r2, [r2, #0]
- 8009022:	4611      	mov	r1, r2
- 8009024:	4618      	mov	r0, r3
- 8009026:	f006 f9c5 	bl	800f3b4 <ip4_addr_isbroadcast_u32>
- 800902a:	4603      	mov	r3, r0
- 800902c:	2b00      	cmp	r3, #0
- 800902e:	f040 83c7 	bne.w	80097c0 <tcp_input+0x7d4>
-      ip_addr_ismulticast(ip_current_dest_addr())) {
- 8009032:	4b92      	ldr	r3, [pc, #584]	; (800927c <tcp_input+0x290>)
- 8009034:	695b      	ldr	r3, [r3, #20]
- 8009036:	f003 03f0 	and.w	r3, r3, #240	; 0xf0
-  if (ip_addr_isbroadcast(ip_current_dest_addr(), ip_current_netif()) ||
- 800903a:	2be0      	cmp	r3, #224	; 0xe0
- 800903c:	f000 83c0 	beq.w	80097c0 <tcp_input+0x7d4>
-    }
-  }
-#endif /* CHECKSUM_CHECK_TCP */
-
-  /* sanity-check header length */
-  hdrlen_bytes = TCPH_HDRLEN_BYTES(tcphdr);
- 8009040:	4b8d      	ldr	r3, [pc, #564]	; (8009278 <tcp_input+0x28c>)
- 8009042:	681b      	ldr	r3, [r3, #0]
- 8009044:	899b      	ldrh	r3, [r3, #12]
- 8009046:	b29b      	uxth	r3, r3
- 8009048:	4618      	mov	r0, r3
- 800904a:	f7fc fa7f 	bl	800554c <lwip_htons>
- 800904e:	4603      	mov	r3, r0
- 8009050:	0b1b      	lsrs	r3, r3, #12
- 8009052:	b29b      	uxth	r3, r3
- 8009054:	b2db      	uxtb	r3, r3
- 8009056:	009b      	lsls	r3, r3, #2
- 8009058:	74bb      	strb	r3, [r7, #18]
-  if ((hdrlen_bytes < TCP_HLEN) || (hdrlen_bytes > p->tot_len)) {
- 800905a:	7cbb      	ldrb	r3, [r7, #18]
- 800905c:	2b13      	cmp	r3, #19
- 800905e:	f240 83b1 	bls.w	80097c4 <tcp_input+0x7d8>
- 8009062:	7cbb      	ldrb	r3, [r7, #18]
- 8009064:	b29a      	uxth	r2, r3
- 8009066:	687b      	ldr	r3, [r7, #4]
- 8009068:	891b      	ldrh	r3, [r3, #8]
- 800906a:	429a      	cmp	r2, r3
- 800906c:	f200 83aa 	bhi.w	80097c4 <tcp_input+0x7d8>
-    goto dropped;
-  }
-
-  /* Move the payload pointer in the pbuf so that it points to the
-     TCP data instead of the TCP header. */
-  tcphdr_optlen = (u16_t)(hdrlen_bytes - TCP_HLEN);
- 8009070:	7cbb      	ldrb	r3, [r7, #18]
- 8009072:	b29b      	uxth	r3, r3
- 8009074:	3b14      	subs	r3, #20
- 8009076:	b29a      	uxth	r2, r3
- 8009078:	4b81      	ldr	r3, [pc, #516]	; (8009280 <tcp_input+0x294>)
- 800907a:	801a      	strh	r2, [r3, #0]
-  tcphdr_opt2 = NULL;
- 800907c:	4b81      	ldr	r3, [pc, #516]	; (8009284 <tcp_input+0x298>)
- 800907e:	2200      	movs	r2, #0
- 8009080:	601a      	str	r2, [r3, #0]
-  if (p->len >= hdrlen_bytes) {
- 8009082:	687b      	ldr	r3, [r7, #4]
- 8009084:	895a      	ldrh	r2, [r3, #10]
- 8009086:	7cbb      	ldrb	r3, [r7, #18]
- 8009088:	b29b      	uxth	r3, r3
- 800908a:	429a      	cmp	r2, r3
- 800908c:	d309      	bcc.n	80090a2 <tcp_input+0xb6>
-    /* all options are in the first pbuf */
-    tcphdr_opt1len = tcphdr_optlen;
- 800908e:	4b7c      	ldr	r3, [pc, #496]	; (8009280 <tcp_input+0x294>)
- 8009090:	881a      	ldrh	r2, [r3, #0]
- 8009092:	4b7d      	ldr	r3, [pc, #500]	; (8009288 <tcp_input+0x29c>)
- 8009094:	801a      	strh	r2, [r3, #0]
-    pbuf_remove_header(p, hdrlen_bytes); /* cannot fail */
- 8009096:	7cbb      	ldrb	r3, [r7, #18]
- 8009098:	4619      	mov	r1, r3
- 800909a:	6878      	ldr	r0, [r7, #4]
- 800909c:	f7fd ff14 	bl	8006ec8 <pbuf_remove_header>
- 80090a0:	e04e      	b.n	8009140 <tcp_input+0x154>
-  } else {
-    u16_t opt2len;
-    /* TCP header fits into first pbuf, options don't - data is in the next pbuf */
-    /* there must be a next pbuf, due to hdrlen_bytes sanity check above */
-    LWIP_ASSERT("p->next != NULL", p->next != NULL);
- 80090a2:	687b      	ldr	r3, [r7, #4]
- 80090a4:	681b      	ldr	r3, [r3, #0]
- 80090a6:	2b00      	cmp	r3, #0
- 80090a8:	d105      	bne.n	80090b6 <tcp_input+0xca>
- 80090aa:	4b70      	ldr	r3, [pc, #448]	; (800926c <tcp_input+0x280>)
- 80090ac:	22c2      	movs	r2, #194	; 0xc2
- 80090ae:	4977      	ldr	r1, [pc, #476]	; (800928c <tcp_input+0x2a0>)
- 80090b0:	4870      	ldr	r0, [pc, #448]	; (8009274 <tcp_input+0x288>)
- 80090b2:	f007 fd89 	bl	8010bc8 <iprintf>
-
-    /* advance over the TCP header (cannot fail) */
-    pbuf_remove_header(p, TCP_HLEN);
- 80090b6:	2114      	movs	r1, #20
- 80090b8:	6878      	ldr	r0, [r7, #4]
- 80090ba:	f7fd ff05 	bl	8006ec8 <pbuf_remove_header>
-
-    /* determine how long the first and second parts of the options are */
-    tcphdr_opt1len = p->len;
- 80090be:	687b      	ldr	r3, [r7, #4]
- 80090c0:	895a      	ldrh	r2, [r3, #10]
- 80090c2:	4b71      	ldr	r3, [pc, #452]	; (8009288 <tcp_input+0x29c>)
- 80090c4:	801a      	strh	r2, [r3, #0]
-    opt2len = (u16_t)(tcphdr_optlen - tcphdr_opt1len);
- 80090c6:	4b6e      	ldr	r3, [pc, #440]	; (8009280 <tcp_input+0x294>)
- 80090c8:	881a      	ldrh	r2, [r3, #0]
- 80090ca:	4b6f      	ldr	r3, [pc, #444]	; (8009288 <tcp_input+0x29c>)
- 80090cc:	881b      	ldrh	r3, [r3, #0]
- 80090ce:	1ad3      	subs	r3, r2, r3
- 80090d0:	823b      	strh	r3, [r7, #16]
-
-    /* options continue in the next pbuf: set p to zero length and hide the
-        options in the next pbuf (adjusting p->tot_len) */
-    pbuf_remove_header(p, tcphdr_opt1len);
- 80090d2:	4b6d      	ldr	r3, [pc, #436]	; (8009288 <tcp_input+0x29c>)
- 80090d4:	881b      	ldrh	r3, [r3, #0]
- 80090d6:	4619      	mov	r1, r3
- 80090d8:	6878      	ldr	r0, [r7, #4]
- 80090da:	f7fd fef5 	bl	8006ec8 <pbuf_remove_header>
-
-    /* check that the options fit in the second pbuf */
-    if (opt2len > p->next->len) {
- 80090de:	687b      	ldr	r3, [r7, #4]
- 80090e0:	681b      	ldr	r3, [r3, #0]
- 80090e2:	895b      	ldrh	r3, [r3, #10]
- 80090e4:	8a3a      	ldrh	r2, [r7, #16]
- 80090e6:	429a      	cmp	r2, r3
- 80090e8:	f200 836e 	bhi.w	80097c8 <tcp_input+0x7dc>
-      TCP_STATS_INC(tcp.lenerr);
-      goto dropped;
-    }
-
-    /* remember the pointer to the second part of the options */
-    tcphdr_opt2 = (u8_t *)p->next->payload;
- 80090ec:	687b      	ldr	r3, [r7, #4]
- 80090ee:	681b      	ldr	r3, [r3, #0]
- 80090f0:	685b      	ldr	r3, [r3, #4]
- 80090f2:	4a64      	ldr	r2, [pc, #400]	; (8009284 <tcp_input+0x298>)
- 80090f4:	6013      	str	r3, [r2, #0]
-
-    /* advance p->next to point after the options, and manually
-        adjust p->tot_len to keep it consistent with the changed p->next */
-    pbuf_remove_header(p->next, opt2len);
- 80090f6:	687b      	ldr	r3, [r7, #4]
- 80090f8:	681b      	ldr	r3, [r3, #0]
- 80090fa:	8a3a      	ldrh	r2, [r7, #16]
- 80090fc:	4611      	mov	r1, r2
- 80090fe:	4618      	mov	r0, r3
- 8009100:	f7fd fee2 	bl	8006ec8 <pbuf_remove_header>
-    p->tot_len = (u16_t)(p->tot_len - opt2len);
- 8009104:	687b      	ldr	r3, [r7, #4]
- 8009106:	891a      	ldrh	r2, [r3, #8]
- 8009108:	8a3b      	ldrh	r3, [r7, #16]
- 800910a:	1ad3      	subs	r3, r2, r3
- 800910c:	b29a      	uxth	r2, r3
- 800910e:	687b      	ldr	r3, [r7, #4]
- 8009110:	811a      	strh	r2, [r3, #8]
-
-    LWIP_ASSERT("p->len == 0", p->len == 0);
- 8009112:	687b      	ldr	r3, [r7, #4]
- 8009114:	895b      	ldrh	r3, [r3, #10]
- 8009116:	2b00      	cmp	r3, #0
- 8009118:	d005      	beq.n	8009126 <tcp_input+0x13a>
- 800911a:	4b54      	ldr	r3, [pc, #336]	; (800926c <tcp_input+0x280>)
- 800911c:	22df      	movs	r2, #223	; 0xdf
- 800911e:	495c      	ldr	r1, [pc, #368]	; (8009290 <tcp_input+0x2a4>)
- 8009120:	4854      	ldr	r0, [pc, #336]	; (8009274 <tcp_input+0x288>)
- 8009122:	f007 fd51 	bl	8010bc8 <iprintf>
-    LWIP_ASSERT("p->tot_len == p->next->tot_len", p->tot_len == p->next->tot_len);
- 8009126:	687b      	ldr	r3, [r7, #4]
- 8009128:	891a      	ldrh	r2, [r3, #8]
- 800912a:	687b      	ldr	r3, [r7, #4]
- 800912c:	681b      	ldr	r3, [r3, #0]
- 800912e:	891b      	ldrh	r3, [r3, #8]
- 8009130:	429a      	cmp	r2, r3
- 8009132:	d005      	beq.n	8009140 <tcp_input+0x154>
- 8009134:	4b4d      	ldr	r3, [pc, #308]	; (800926c <tcp_input+0x280>)
- 8009136:	22e0      	movs	r2, #224	; 0xe0
- 8009138:	4956      	ldr	r1, [pc, #344]	; (8009294 <tcp_input+0x2a8>)
- 800913a:	484e      	ldr	r0, [pc, #312]	; (8009274 <tcp_input+0x288>)
- 800913c:	f007 fd44 	bl	8010bc8 <iprintf>
-  }
-
-  /* Convert fields in TCP header to host byte order. */
-  tcphdr->src = lwip_ntohs(tcphdr->src);
- 8009140:	4b4d      	ldr	r3, [pc, #308]	; (8009278 <tcp_input+0x28c>)
- 8009142:	681b      	ldr	r3, [r3, #0]
- 8009144:	881b      	ldrh	r3, [r3, #0]
- 8009146:	b29b      	uxth	r3, r3
- 8009148:	4a4b      	ldr	r2, [pc, #300]	; (8009278 <tcp_input+0x28c>)
- 800914a:	6814      	ldr	r4, [r2, #0]
- 800914c:	4618      	mov	r0, r3
- 800914e:	f7fc f9fd 	bl	800554c <lwip_htons>
- 8009152:	4603      	mov	r3, r0
- 8009154:	8023      	strh	r3, [r4, #0]
-  tcphdr->dest = lwip_ntohs(tcphdr->dest);
- 8009156:	4b48      	ldr	r3, [pc, #288]	; (8009278 <tcp_input+0x28c>)
- 8009158:	681b      	ldr	r3, [r3, #0]
- 800915a:	885b      	ldrh	r3, [r3, #2]
- 800915c:	b29b      	uxth	r3, r3
- 800915e:	4a46      	ldr	r2, [pc, #280]	; (8009278 <tcp_input+0x28c>)
- 8009160:	6814      	ldr	r4, [r2, #0]
- 8009162:	4618      	mov	r0, r3
- 8009164:	f7fc f9f2 	bl	800554c <lwip_htons>
- 8009168:	4603      	mov	r3, r0
- 800916a:	8063      	strh	r3, [r4, #2]
-  seqno = tcphdr->seqno = lwip_ntohl(tcphdr->seqno);
- 800916c:	4b42      	ldr	r3, [pc, #264]	; (8009278 <tcp_input+0x28c>)
- 800916e:	681b      	ldr	r3, [r3, #0]
- 8009170:	685b      	ldr	r3, [r3, #4]
- 8009172:	4a41      	ldr	r2, [pc, #260]	; (8009278 <tcp_input+0x28c>)
- 8009174:	6814      	ldr	r4, [r2, #0]
- 8009176:	4618      	mov	r0, r3
- 8009178:	f7fc f9fd 	bl	8005576 <lwip_htonl>
- 800917c:	4603      	mov	r3, r0
- 800917e:	6063      	str	r3, [r4, #4]
- 8009180:	6863      	ldr	r3, [r4, #4]
- 8009182:	4a45      	ldr	r2, [pc, #276]	; (8009298 <tcp_input+0x2ac>)
- 8009184:	6013      	str	r3, [r2, #0]
-  ackno = tcphdr->ackno = lwip_ntohl(tcphdr->ackno);
- 8009186:	4b3c      	ldr	r3, [pc, #240]	; (8009278 <tcp_input+0x28c>)
- 8009188:	681b      	ldr	r3, [r3, #0]
- 800918a:	689b      	ldr	r3, [r3, #8]
- 800918c:	4a3a      	ldr	r2, [pc, #232]	; (8009278 <tcp_input+0x28c>)
- 800918e:	6814      	ldr	r4, [r2, #0]
- 8009190:	4618      	mov	r0, r3
- 8009192:	f7fc f9f0 	bl	8005576 <lwip_htonl>
- 8009196:	4603      	mov	r3, r0
- 8009198:	60a3      	str	r3, [r4, #8]
- 800919a:	68a3      	ldr	r3, [r4, #8]
- 800919c:	4a3f      	ldr	r2, [pc, #252]	; (800929c <tcp_input+0x2b0>)
- 800919e:	6013      	str	r3, [r2, #0]
-  tcphdr->wnd = lwip_ntohs(tcphdr->wnd);
- 80091a0:	4b35      	ldr	r3, [pc, #212]	; (8009278 <tcp_input+0x28c>)
- 80091a2:	681b      	ldr	r3, [r3, #0]
- 80091a4:	89db      	ldrh	r3, [r3, #14]
- 80091a6:	b29b      	uxth	r3, r3
- 80091a8:	4a33      	ldr	r2, [pc, #204]	; (8009278 <tcp_input+0x28c>)
- 80091aa:	6814      	ldr	r4, [r2, #0]
- 80091ac:	4618      	mov	r0, r3
- 80091ae:	f7fc f9cd 	bl	800554c <lwip_htons>
- 80091b2:	4603      	mov	r3, r0
- 80091b4:	81e3      	strh	r3, [r4, #14]
-
-  flags = TCPH_FLAGS(tcphdr);
- 80091b6:	4b30      	ldr	r3, [pc, #192]	; (8009278 <tcp_input+0x28c>)
- 80091b8:	681b      	ldr	r3, [r3, #0]
- 80091ba:	899b      	ldrh	r3, [r3, #12]
- 80091bc:	b29b      	uxth	r3, r3
- 80091be:	4618      	mov	r0, r3
- 80091c0:	f7fc f9c4 	bl	800554c <lwip_htons>
- 80091c4:	4603      	mov	r3, r0
- 80091c6:	b2db      	uxtb	r3, r3
- 80091c8:	f003 033f 	and.w	r3, r3, #63	; 0x3f
- 80091cc:	b2da      	uxtb	r2, r3
- 80091ce:	4b34      	ldr	r3, [pc, #208]	; (80092a0 <tcp_input+0x2b4>)
- 80091d0:	701a      	strb	r2, [r3, #0]
-  tcplen = p->tot_len;
- 80091d2:	687b      	ldr	r3, [r7, #4]
- 80091d4:	891a      	ldrh	r2, [r3, #8]
- 80091d6:	4b33      	ldr	r3, [pc, #204]	; (80092a4 <tcp_input+0x2b8>)
- 80091d8:	801a      	strh	r2, [r3, #0]
-  if (flags & (TCP_FIN | TCP_SYN)) {
- 80091da:	4b31      	ldr	r3, [pc, #196]	; (80092a0 <tcp_input+0x2b4>)
- 80091dc:	781b      	ldrb	r3, [r3, #0]
- 80091de:	f003 0303 	and.w	r3, r3, #3
- 80091e2:	2b00      	cmp	r3, #0
- 80091e4:	d00c      	beq.n	8009200 <tcp_input+0x214>
-    tcplen++;
- 80091e6:	4b2f      	ldr	r3, [pc, #188]	; (80092a4 <tcp_input+0x2b8>)
- 80091e8:	881b      	ldrh	r3, [r3, #0]
- 80091ea:	3301      	adds	r3, #1
- 80091ec:	b29a      	uxth	r2, r3
- 80091ee:	4b2d      	ldr	r3, [pc, #180]	; (80092a4 <tcp_input+0x2b8>)
- 80091f0:	801a      	strh	r2, [r3, #0]
-    if (tcplen < p->tot_len) {
- 80091f2:	687b      	ldr	r3, [r7, #4]
- 80091f4:	891a      	ldrh	r2, [r3, #8]
- 80091f6:	4b2b      	ldr	r3, [pc, #172]	; (80092a4 <tcp_input+0x2b8>)
- 80091f8:	881b      	ldrh	r3, [r3, #0]
- 80091fa:	429a      	cmp	r2, r3
- 80091fc:	f200 82e6 	bhi.w	80097cc <tcp_input+0x7e0>
-    }
-  }
-
-  /* Demultiplex an incoming segment. First, we check if it is destined
-     for an active connection. */
-  prev = NULL;
- 8009200:	2300      	movs	r3, #0
- 8009202:	61fb      	str	r3, [r7, #28]
-
-  for (pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) {
- 8009204:	4b28      	ldr	r3, [pc, #160]	; (80092a8 <tcp_input+0x2bc>)
- 8009206:	681b      	ldr	r3, [r3, #0]
- 8009208:	61bb      	str	r3, [r7, #24]
- 800920a:	e09d      	b.n	8009348 <tcp_input+0x35c>
-    LWIP_ASSERT("tcp_input: active pcb->state != CLOSED", pcb->state != CLOSED);
- 800920c:	69bb      	ldr	r3, [r7, #24]
- 800920e:	7d1b      	ldrb	r3, [r3, #20]
- 8009210:	2b00      	cmp	r3, #0
- 8009212:	d105      	bne.n	8009220 <tcp_input+0x234>
- 8009214:	4b15      	ldr	r3, [pc, #84]	; (800926c <tcp_input+0x280>)
- 8009216:	22fb      	movs	r2, #251	; 0xfb
- 8009218:	4924      	ldr	r1, [pc, #144]	; (80092ac <tcp_input+0x2c0>)
- 800921a:	4816      	ldr	r0, [pc, #88]	; (8009274 <tcp_input+0x288>)
- 800921c:	f007 fcd4 	bl	8010bc8 <iprintf>
-    LWIP_ASSERT("tcp_input: active pcb->state != TIME-WAIT", pcb->state != TIME_WAIT);
- 8009220:	69bb      	ldr	r3, [r7, #24]
- 8009222:	7d1b      	ldrb	r3, [r3, #20]
- 8009224:	2b0a      	cmp	r3, #10
- 8009226:	d105      	bne.n	8009234 <tcp_input+0x248>
- 8009228:	4b10      	ldr	r3, [pc, #64]	; (800926c <tcp_input+0x280>)
- 800922a:	22fc      	movs	r2, #252	; 0xfc
- 800922c:	4920      	ldr	r1, [pc, #128]	; (80092b0 <tcp_input+0x2c4>)
- 800922e:	4811      	ldr	r0, [pc, #68]	; (8009274 <tcp_input+0x288>)
- 8009230:	f007 fcca 	bl	8010bc8 <iprintf>
-    LWIP_ASSERT("tcp_input: active pcb->state != LISTEN", pcb->state != LISTEN);
- 8009234:	69bb      	ldr	r3, [r7, #24]
- 8009236:	7d1b      	ldrb	r3, [r3, #20]
- 8009238:	2b01      	cmp	r3, #1
- 800923a:	d105      	bne.n	8009248 <tcp_input+0x25c>
- 800923c:	4b0b      	ldr	r3, [pc, #44]	; (800926c <tcp_input+0x280>)
- 800923e:	22fd      	movs	r2, #253	; 0xfd
- 8009240:	491c      	ldr	r1, [pc, #112]	; (80092b4 <tcp_input+0x2c8>)
- 8009242:	480c      	ldr	r0, [pc, #48]	; (8009274 <tcp_input+0x288>)
- 8009244:	f007 fcc0 	bl	8010bc8 <iprintf>
-
-    /* check if PCB is bound to specific netif */
-    if ((pcb->netif_idx != NETIF_NO_INDEX) &&
- 8009248:	69bb      	ldr	r3, [r7, #24]
- 800924a:	7a1b      	ldrb	r3, [r3, #8]
- 800924c:	2b00      	cmp	r3, #0
- 800924e:	d033      	beq.n	80092b8 <tcp_input+0x2cc>
-        (pcb->netif_idx != netif_get_index(ip_data.current_input_netif))) {
- 8009250:	69bb      	ldr	r3, [r7, #24]
- 8009252:	7a1a      	ldrb	r2, [r3, #8]
- 8009254:	4b09      	ldr	r3, [pc, #36]	; (800927c <tcp_input+0x290>)
- 8009256:	685b      	ldr	r3, [r3, #4]
- 8009258:	f893 3030 	ldrb.w	r3, [r3, #48]	; 0x30
- 800925c:	3301      	adds	r3, #1
- 800925e:	b2db      	uxtb	r3, r3
-    if ((pcb->netif_idx != NETIF_NO_INDEX) &&
- 8009260:	429a      	cmp	r2, r3
- 8009262:	d029      	beq.n	80092b8 <tcp_input+0x2cc>
-      prev = pcb;
- 8009264:	69bb      	ldr	r3, [r7, #24]
- 8009266:	61fb      	str	r3, [r7, #28]
-      continue;
- 8009268:	e06b      	b.n	8009342 <tcp_input+0x356>
- 800926a:	bf00      	nop
- 800926c:	08013198 	.word	0x08013198
- 8009270:	080131cc 	.word	0x080131cc
- 8009274:	080131e4 	.word	0x080131e4
- 8009278:	24007b98 	.word	0x24007b98
- 800927c:	24004c10 	.word	0x24004c10
- 8009280:	24007b9c 	.word	0x24007b9c
- 8009284:	24007ba0 	.word	0x24007ba0
- 8009288:	24007b9e 	.word	0x24007b9e
- 800928c:	0801320c 	.word	0x0801320c
- 8009290:	0801321c 	.word	0x0801321c
- 8009294:	08013228 	.word	0x08013228
- 8009298:	24007ba8 	.word	0x24007ba8
- 800929c:	24007bac 	.word	0x24007bac
- 80092a0:	24007bb4 	.word	0x24007bb4
- 80092a4:	24007bb2 	.word	0x24007bb2
- 80092a8:	24007b78 	.word	0x24007b78
- 80092ac:	08013248 	.word	0x08013248
- 80092b0:	08013270 	.word	0x08013270
- 80092b4:	0801329c 	.word	0x0801329c
-    }
-
-    if (pcb->remote_port == tcphdr->src &&
- 80092b8:	69bb      	ldr	r3, [r7, #24]
- 80092ba:	8b1a      	ldrh	r2, [r3, #24]
- 80092bc:	4b72      	ldr	r3, [pc, #456]	; (8009488 <tcp_input+0x49c>)
- 80092be:	681b      	ldr	r3, [r3, #0]
- 80092c0:	881b      	ldrh	r3, [r3, #0]
- 80092c2:	b29b      	uxth	r3, r3
- 80092c4:	429a      	cmp	r2, r3
- 80092c6:	d13a      	bne.n	800933e <tcp_input+0x352>
-        pcb->local_port == tcphdr->dest &&
- 80092c8:	69bb      	ldr	r3, [r7, #24]
- 80092ca:	8ada      	ldrh	r2, [r3, #22]
- 80092cc:	4b6e      	ldr	r3, [pc, #440]	; (8009488 <tcp_input+0x49c>)
- 80092ce:	681b      	ldr	r3, [r3, #0]
- 80092d0:	885b      	ldrh	r3, [r3, #2]
- 80092d2:	b29b      	uxth	r3, r3
-    if (pcb->remote_port == tcphdr->src &&
- 80092d4:	429a      	cmp	r2, r3
- 80092d6:	d132      	bne.n	800933e <tcp_input+0x352>
-        ip_addr_cmp(&pcb->remote_ip, ip_current_src_addr()) &&
- 80092d8:	69bb      	ldr	r3, [r7, #24]
- 80092da:	685a      	ldr	r2, [r3, #4]
- 80092dc:	4b6b      	ldr	r3, [pc, #428]	; (800948c <tcp_input+0x4a0>)
- 80092de:	691b      	ldr	r3, [r3, #16]
-        pcb->local_port == tcphdr->dest &&
- 80092e0:	429a      	cmp	r2, r3
- 80092e2:	d12c      	bne.n	800933e <tcp_input+0x352>
-        ip_addr_cmp(&pcb->local_ip, ip_current_dest_addr())) {
- 80092e4:	69bb      	ldr	r3, [r7, #24]
- 80092e6:	681a      	ldr	r2, [r3, #0]
- 80092e8:	4b68      	ldr	r3, [pc, #416]	; (800948c <tcp_input+0x4a0>)
- 80092ea:	695b      	ldr	r3, [r3, #20]
-        ip_addr_cmp(&pcb->remote_ip, ip_current_src_addr()) &&
- 80092ec:	429a      	cmp	r2, r3
- 80092ee:	d126      	bne.n	800933e <tcp_input+0x352>
-      /* Move this PCB to the front of the list so that subsequent
-         lookups will be faster (we exploit locality in TCP segment
-         arrivals). */
-      LWIP_ASSERT("tcp_input: pcb->next != pcb (before cache)", pcb->next != pcb);
- 80092f0:	69bb      	ldr	r3, [r7, #24]
- 80092f2:	68db      	ldr	r3, [r3, #12]
- 80092f4:	69ba      	ldr	r2, [r7, #24]
- 80092f6:	429a      	cmp	r2, r3
- 80092f8:	d106      	bne.n	8009308 <tcp_input+0x31c>
- 80092fa:	4b65      	ldr	r3, [pc, #404]	; (8009490 <tcp_input+0x4a4>)
- 80092fc:	f240 120d 	movw	r2, #269	; 0x10d
- 8009300:	4964      	ldr	r1, [pc, #400]	; (8009494 <tcp_input+0x4a8>)
- 8009302:	4865      	ldr	r0, [pc, #404]	; (8009498 <tcp_input+0x4ac>)
- 8009304:	f007 fc60 	bl	8010bc8 <iprintf>
-      if (prev != NULL) {
- 8009308:	69fb      	ldr	r3, [r7, #28]
- 800930a:	2b00      	cmp	r3, #0
- 800930c:	d00a      	beq.n	8009324 <tcp_input+0x338>
-        prev->next = pcb->next;
- 800930e:	69bb      	ldr	r3, [r7, #24]
- 8009310:	68da      	ldr	r2, [r3, #12]
- 8009312:	69fb      	ldr	r3, [r7, #28]
- 8009314:	60da      	str	r2, [r3, #12]
-        pcb->next = tcp_active_pcbs;
- 8009316:	4b61      	ldr	r3, [pc, #388]	; (800949c <tcp_input+0x4b0>)
- 8009318:	681a      	ldr	r2, [r3, #0]
- 800931a:	69bb      	ldr	r3, [r7, #24]
- 800931c:	60da      	str	r2, [r3, #12]
-        tcp_active_pcbs = pcb;
- 800931e:	4a5f      	ldr	r2, [pc, #380]	; (800949c <tcp_input+0x4b0>)
- 8009320:	69bb      	ldr	r3, [r7, #24]
- 8009322:	6013      	str	r3, [r2, #0]
-      } else {
-        TCP_STATS_INC(tcp.cachehit);
-      }
-      LWIP_ASSERT("tcp_input: pcb->next != pcb (after cache)", pcb->next != pcb);
- 8009324:	69bb      	ldr	r3, [r7, #24]
- 8009326:	68db      	ldr	r3, [r3, #12]
- 8009328:	69ba      	ldr	r2, [r7, #24]
- 800932a:	429a      	cmp	r2, r3
- 800932c:	d111      	bne.n	8009352 <tcp_input+0x366>
- 800932e:	4b58      	ldr	r3, [pc, #352]	; (8009490 <tcp_input+0x4a4>)
- 8009330:	f240 1215 	movw	r2, #277	; 0x115
- 8009334:	495a      	ldr	r1, [pc, #360]	; (80094a0 <tcp_input+0x4b4>)
- 8009336:	4858      	ldr	r0, [pc, #352]	; (8009498 <tcp_input+0x4ac>)
- 8009338:	f007 fc46 	bl	8010bc8 <iprintf>
-      break;
- 800933c:	e009      	b.n	8009352 <tcp_input+0x366>
-    }
-    prev = pcb;
- 800933e:	69bb      	ldr	r3, [r7, #24]
- 8009340:	61fb      	str	r3, [r7, #28]
-  for (pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) {
- 8009342:	69bb      	ldr	r3, [r7, #24]
- 8009344:	68db      	ldr	r3, [r3, #12]
- 8009346:	61bb      	str	r3, [r7, #24]
- 8009348:	69bb      	ldr	r3, [r7, #24]
- 800934a:	2b00      	cmp	r3, #0
- 800934c:	f47f af5e 	bne.w	800920c <tcp_input+0x220>
- 8009350:	e000      	b.n	8009354 <tcp_input+0x368>
-      break;
- 8009352:	bf00      	nop
-  }
-
-  if (pcb == NULL) {
- 8009354:	69bb      	ldr	r3, [r7, #24]
- 8009356:	2b00      	cmp	r3, #0
- 8009358:	f040 80aa 	bne.w	80094b0 <tcp_input+0x4c4>
-    /* If it did not go to an active connection, we check the connections
-       in the TIME-WAIT state. */
-    for (pcb = tcp_tw_pcbs; pcb != NULL; pcb = pcb->next) {
- 800935c:	4b51      	ldr	r3, [pc, #324]	; (80094a4 <tcp_input+0x4b8>)
- 800935e:	681b      	ldr	r3, [r3, #0]
- 8009360:	61bb      	str	r3, [r7, #24]
- 8009362:	e03f      	b.n	80093e4 <tcp_input+0x3f8>
-      LWIP_ASSERT("tcp_input: TIME-WAIT pcb->state == TIME-WAIT", pcb->state == TIME_WAIT);
- 8009364:	69bb      	ldr	r3, [r7, #24]
- 8009366:	7d1b      	ldrb	r3, [r3, #20]
- 8009368:	2b0a      	cmp	r3, #10
- 800936a:	d006      	beq.n	800937a <tcp_input+0x38e>
- 800936c:	4b48      	ldr	r3, [pc, #288]	; (8009490 <tcp_input+0x4a4>)
- 800936e:	f240 121f 	movw	r2, #287	; 0x11f
- 8009372:	494d      	ldr	r1, [pc, #308]	; (80094a8 <tcp_input+0x4bc>)
- 8009374:	4848      	ldr	r0, [pc, #288]	; (8009498 <tcp_input+0x4ac>)
- 8009376:	f007 fc27 	bl	8010bc8 <iprintf>
-
-      /* check if PCB is bound to specific netif */
-      if ((pcb->netif_idx != NETIF_NO_INDEX) &&
- 800937a:	69bb      	ldr	r3, [r7, #24]
- 800937c:	7a1b      	ldrb	r3, [r3, #8]
- 800937e:	2b00      	cmp	r3, #0
- 8009380:	d009      	beq.n	8009396 <tcp_input+0x3aa>
-          (pcb->netif_idx != netif_get_index(ip_data.current_input_netif))) {
- 8009382:	69bb      	ldr	r3, [r7, #24]
- 8009384:	7a1a      	ldrb	r2, [r3, #8]
- 8009386:	4b41      	ldr	r3, [pc, #260]	; (800948c <tcp_input+0x4a0>)
- 8009388:	685b      	ldr	r3, [r3, #4]
- 800938a:	f893 3030 	ldrb.w	r3, [r3, #48]	; 0x30
- 800938e:	3301      	adds	r3, #1
- 8009390:	b2db      	uxtb	r3, r3
-      if ((pcb->netif_idx != NETIF_NO_INDEX) &&
- 8009392:	429a      	cmp	r2, r3
- 8009394:	d122      	bne.n	80093dc <tcp_input+0x3f0>
-        continue;
-      }
-
-      if (pcb->remote_port == tcphdr->src &&
- 8009396:	69bb      	ldr	r3, [r7, #24]
- 8009398:	8b1a      	ldrh	r2, [r3, #24]
- 800939a:	4b3b      	ldr	r3, [pc, #236]	; (8009488 <tcp_input+0x49c>)
- 800939c:	681b      	ldr	r3, [r3, #0]
- 800939e:	881b      	ldrh	r3, [r3, #0]
- 80093a0:	b29b      	uxth	r3, r3
- 80093a2:	429a      	cmp	r2, r3
- 80093a4:	d11b      	bne.n	80093de <tcp_input+0x3f2>
-          pcb->local_port == tcphdr->dest &&
- 80093a6:	69bb      	ldr	r3, [r7, #24]
- 80093a8:	8ada      	ldrh	r2, [r3, #22]
- 80093aa:	4b37      	ldr	r3, [pc, #220]	; (8009488 <tcp_input+0x49c>)
- 80093ac:	681b      	ldr	r3, [r3, #0]
- 80093ae:	885b      	ldrh	r3, [r3, #2]
- 80093b0:	b29b      	uxth	r3, r3
-      if (pcb->remote_port == tcphdr->src &&
- 80093b2:	429a      	cmp	r2, r3
- 80093b4:	d113      	bne.n	80093de <tcp_input+0x3f2>
-          ip_addr_cmp(&pcb->remote_ip, ip_current_src_addr()) &&
- 80093b6:	69bb      	ldr	r3, [r7, #24]
- 80093b8:	685a      	ldr	r2, [r3, #4]
- 80093ba:	4b34      	ldr	r3, [pc, #208]	; (800948c <tcp_input+0x4a0>)
- 80093bc:	691b      	ldr	r3, [r3, #16]
-          pcb->local_port == tcphdr->dest &&
- 80093be:	429a      	cmp	r2, r3
- 80093c0:	d10d      	bne.n	80093de <tcp_input+0x3f2>
-          ip_addr_cmp(&pcb->local_ip, ip_current_dest_addr())) {
- 80093c2:	69bb      	ldr	r3, [r7, #24]
- 80093c4:	681a      	ldr	r2, [r3, #0]
- 80093c6:	4b31      	ldr	r3, [pc, #196]	; (800948c <tcp_input+0x4a0>)
- 80093c8:	695b      	ldr	r3, [r3, #20]
-          ip_addr_cmp(&pcb->remote_ip, ip_current_src_addr()) &&
- 80093ca:	429a      	cmp	r2, r3
- 80093cc:	d107      	bne.n	80093de <tcp_input+0x3f2>
-#ifdef LWIP_HOOK_TCP_INPACKET_PCB
-        if (LWIP_HOOK_TCP_INPACKET_PCB(pcb, tcphdr, tcphdr_optlen, tcphdr_opt1len,
-                                       tcphdr_opt2, p) == ERR_OK)
-#endif
-        {
-          tcp_timewait_input(pcb);
- 80093ce:	69b8      	ldr	r0, [r7, #24]
- 80093d0:	f000 fb56 	bl	8009a80 <tcp_timewait_input>
-        }
-        pbuf_free(p);
- 80093d4:	6878      	ldr	r0, [r7, #4]
- 80093d6:	f7fd fdfd 	bl	8006fd4 <pbuf_free>
-        return;
- 80093da:	e1fd      	b.n	80097d8 <tcp_input+0x7ec>
-        continue;
- 80093dc:	bf00      	nop
-    for (pcb = tcp_tw_pcbs; pcb != NULL; pcb = pcb->next) {
- 80093de:	69bb      	ldr	r3, [r7, #24]
- 80093e0:	68db      	ldr	r3, [r3, #12]
- 80093e2:	61bb      	str	r3, [r7, #24]
- 80093e4:	69bb      	ldr	r3, [r7, #24]
- 80093e6:	2b00      	cmp	r3, #0
- 80093e8:	d1bc      	bne.n	8009364 <tcp_input+0x378>
-      }
-    }
-
-    /* Finally, if we still did not get a match, we check all PCBs that
-       are LISTENing for incoming connections. */
-    prev = NULL;
- 80093ea:	2300      	movs	r3, #0
- 80093ec:	61fb      	str	r3, [r7, #28]
-    for (lpcb = tcp_listen_pcbs.listen_pcbs; lpcb != NULL; lpcb = lpcb->next) {
- 80093ee:	4b2f      	ldr	r3, [pc, #188]	; (80094ac <tcp_input+0x4c0>)
- 80093f0:	681b      	ldr	r3, [r3, #0]
- 80093f2:	617b      	str	r3, [r7, #20]
- 80093f4:	e02a      	b.n	800944c <tcp_input+0x460>
-      /* check if PCB is bound to specific netif */
-      if ((lpcb->netif_idx != NETIF_NO_INDEX) &&
- 80093f6:	697b      	ldr	r3, [r7, #20]
- 80093f8:	7a1b      	ldrb	r3, [r3, #8]
- 80093fa:	2b00      	cmp	r3, #0
- 80093fc:	d00c      	beq.n	8009418 <tcp_input+0x42c>
-          (lpcb->netif_idx != netif_get_index(ip_data.current_input_netif))) {
- 80093fe:	697b      	ldr	r3, [r7, #20]
- 8009400:	7a1a      	ldrb	r2, [r3, #8]
- 8009402:	4b22      	ldr	r3, [pc, #136]	; (800948c <tcp_input+0x4a0>)
- 8009404:	685b      	ldr	r3, [r3, #4]
- 8009406:	f893 3030 	ldrb.w	r3, [r3, #48]	; 0x30
- 800940a:	3301      	adds	r3, #1
- 800940c:	b2db      	uxtb	r3, r3
-      if ((lpcb->netif_idx != NETIF_NO_INDEX) &&
- 800940e:	429a      	cmp	r2, r3
- 8009410:	d002      	beq.n	8009418 <tcp_input+0x42c>
-        prev = (struct tcp_pcb *)lpcb;
- 8009412:	697b      	ldr	r3, [r7, #20]
- 8009414:	61fb      	str	r3, [r7, #28]
-        continue;
- 8009416:	e016      	b.n	8009446 <tcp_input+0x45a>
-      }
-
-      if (lpcb->local_port == tcphdr->dest) {
- 8009418:	697b      	ldr	r3, [r7, #20]
- 800941a:	8ada      	ldrh	r2, [r3, #22]
- 800941c:	4b1a      	ldr	r3, [pc, #104]	; (8009488 <tcp_input+0x49c>)
- 800941e:	681b      	ldr	r3, [r3, #0]
- 8009420:	885b      	ldrh	r3, [r3, #2]
- 8009422:	b29b      	uxth	r3, r3
- 8009424:	429a      	cmp	r2, r3
- 8009426:	d10c      	bne.n	8009442 <tcp_input+0x456>
-          lpcb_prev = prev;
-#else /* SO_REUSE */
-          break;
-#endif /* SO_REUSE */
-        } else if (IP_ADDR_PCB_VERSION_MATCH_EXACT(lpcb, ip_current_dest_addr())) {
-          if (ip_addr_cmp(&lpcb->local_ip, ip_current_dest_addr())) {
- 8009428:	697b      	ldr	r3, [r7, #20]
- 800942a:	681a      	ldr	r2, [r3, #0]
- 800942c:	4b17      	ldr	r3, [pc, #92]	; (800948c <tcp_input+0x4a0>)
- 800942e:	695b      	ldr	r3, [r3, #20]
- 8009430:	429a      	cmp	r2, r3
- 8009432:	d00f      	beq.n	8009454 <tcp_input+0x468>
-            /* found an exact match */
-            break;
-          } else if (ip_addr_isany(&lpcb->local_ip)) {
- 8009434:	697b      	ldr	r3, [r7, #20]
- 8009436:	2b00      	cmp	r3, #0
- 8009438:	d00d      	beq.n	8009456 <tcp_input+0x46a>
- 800943a:	697b      	ldr	r3, [r7, #20]
- 800943c:	681b      	ldr	r3, [r3, #0]
- 800943e:	2b00      	cmp	r3, #0
- 8009440:	d009      	beq.n	8009456 <tcp_input+0x46a>
-            break;
-#endif /* SO_REUSE */
-          }
-        }
-      }
-      prev = (struct tcp_pcb *)lpcb;
- 8009442:	697b      	ldr	r3, [r7, #20]
- 8009444:	61fb      	str	r3, [r7, #28]
-    for (lpcb = tcp_listen_pcbs.listen_pcbs; lpcb != NULL; lpcb = lpcb->next) {
- 8009446:	697b      	ldr	r3, [r7, #20]
- 8009448:	68db      	ldr	r3, [r3, #12]
- 800944a:	617b      	str	r3, [r7, #20]
- 800944c:	697b      	ldr	r3, [r7, #20]
- 800944e:	2b00      	cmp	r3, #0
- 8009450:	d1d1      	bne.n	80093f6 <tcp_input+0x40a>
- 8009452:	e000      	b.n	8009456 <tcp_input+0x46a>
-            break;
- 8009454:	bf00      	nop
-      /* only pass to ANY if no specific local IP has been found */
-      lpcb = lpcb_any;
-      prev = lpcb_prev;
-    }
-#endif /* SO_REUSE */
-    if (lpcb != NULL) {
- 8009456:	697b      	ldr	r3, [r7, #20]
- 8009458:	2b00      	cmp	r3, #0
- 800945a:	d029      	beq.n	80094b0 <tcp_input+0x4c4>
-      /* Move this PCB to the front of the list so that subsequent
-         lookups will be faster (we exploit locality in TCP segment
-         arrivals). */
-      if (prev != NULL) {
- 800945c:	69fb      	ldr	r3, [r7, #28]
- 800945e:	2b00      	cmp	r3, #0
- 8009460:	d00a      	beq.n	8009478 <tcp_input+0x48c>
-        ((struct tcp_pcb_listen *)prev)->next = lpcb->next;
- 8009462:	697b      	ldr	r3, [r7, #20]
- 8009464:	68da      	ldr	r2, [r3, #12]
- 8009466:	69fb      	ldr	r3, [r7, #28]
- 8009468:	60da      	str	r2, [r3, #12]
-        /* our successor is the remainder of the listening list */
-        lpcb->next = tcp_listen_pcbs.listen_pcbs;
- 800946a:	4b10      	ldr	r3, [pc, #64]	; (80094ac <tcp_input+0x4c0>)
- 800946c:	681a      	ldr	r2, [r3, #0]
- 800946e:	697b      	ldr	r3, [r7, #20]
- 8009470:	60da      	str	r2, [r3, #12]
-        /* put this listening pcb at the head of the listening list */
-        tcp_listen_pcbs.listen_pcbs = lpcb;
- 8009472:	4a0e      	ldr	r2, [pc, #56]	; (80094ac <tcp_input+0x4c0>)
- 8009474:	697b      	ldr	r3, [r7, #20]
- 8009476:	6013      	str	r3, [r2, #0]
-#ifdef LWIP_HOOK_TCP_INPACKET_PCB
-      if (LWIP_HOOK_TCP_INPACKET_PCB((struct tcp_pcb *)lpcb, tcphdr, tcphdr_optlen,
-                                     tcphdr_opt1len, tcphdr_opt2, p) == ERR_OK)
-#endif
-      {
-        tcp_listen_input(lpcb);
- 8009478:	6978      	ldr	r0, [r7, #20]
- 800947a:	f000 fa03 	bl	8009884 <tcp_listen_input>
-      }
-      pbuf_free(p);
- 800947e:	6878      	ldr	r0, [r7, #4]
- 8009480:	f7fd fda8 	bl	8006fd4 <pbuf_free>
-      return;
- 8009484:	e1a8      	b.n	80097d8 <tcp_input+0x7ec>
- 8009486:	bf00      	nop
- 8009488:	24007b98 	.word	0x24007b98
- 800948c:	24004c10 	.word	0x24004c10
- 8009490:	08013198 	.word	0x08013198
- 8009494:	080132c4 	.word	0x080132c4
- 8009498:	080131e4 	.word	0x080131e4
- 800949c:	24007b78 	.word	0x24007b78
- 80094a0:	080132f0 	.word	0x080132f0
- 80094a4:	24007b7c 	.word	0x24007b7c
- 80094a8:	0801331c 	.word	0x0801331c
- 80094ac:	24007b74 	.word	0x24007b74
-      tcphdr_opt1len, tcphdr_opt2, p) != ERR_OK) {
-    pbuf_free(p);
-    return;
-  }
-#endif
-  if (pcb != NULL) {
- 80094b0:	69bb      	ldr	r3, [r7, #24]
- 80094b2:	2b00      	cmp	r3, #0
- 80094b4:	f000 8158 	beq.w	8009768 <tcp_input+0x77c>
-#if TCP_INPUT_DEBUG
-    tcp_debug_print_state(pcb->state);
-#endif /* TCP_INPUT_DEBUG */
-
-    /* Set up a tcp_seg structure. */
-    inseg.next = NULL;
- 80094b8:	4b95      	ldr	r3, [pc, #596]	; (8009710 <tcp_input+0x724>)
- 80094ba:	2200      	movs	r2, #0
- 80094bc:	601a      	str	r2, [r3, #0]
-    inseg.len = p->tot_len;
- 80094be:	687b      	ldr	r3, [r7, #4]
- 80094c0:	891a      	ldrh	r2, [r3, #8]
- 80094c2:	4b93      	ldr	r3, [pc, #588]	; (8009710 <tcp_input+0x724>)
- 80094c4:	811a      	strh	r2, [r3, #8]
-    inseg.p = p;
- 80094c6:	4a92      	ldr	r2, [pc, #584]	; (8009710 <tcp_input+0x724>)
- 80094c8:	687b      	ldr	r3, [r7, #4]
- 80094ca:	6053      	str	r3, [r2, #4]
-    inseg.tcphdr = tcphdr;
- 80094cc:	4b91      	ldr	r3, [pc, #580]	; (8009714 <tcp_input+0x728>)
- 80094ce:	681b      	ldr	r3, [r3, #0]
- 80094d0:	4a8f      	ldr	r2, [pc, #572]	; (8009710 <tcp_input+0x724>)
- 80094d2:	6113      	str	r3, [r2, #16]
-
-    recv_data = NULL;
- 80094d4:	4b90      	ldr	r3, [pc, #576]	; (8009718 <tcp_input+0x72c>)
- 80094d6:	2200      	movs	r2, #0
- 80094d8:	601a      	str	r2, [r3, #0]
-    recv_flags = 0;
- 80094da:	4b90      	ldr	r3, [pc, #576]	; (800971c <tcp_input+0x730>)
- 80094dc:	2200      	movs	r2, #0
- 80094de:	701a      	strb	r2, [r3, #0]
-    recv_acked = 0;
- 80094e0:	4b8f      	ldr	r3, [pc, #572]	; (8009720 <tcp_input+0x734>)
- 80094e2:	2200      	movs	r2, #0
- 80094e4:	801a      	strh	r2, [r3, #0]
-
-    if (flags & TCP_PSH) {
- 80094e6:	4b8f      	ldr	r3, [pc, #572]	; (8009724 <tcp_input+0x738>)
- 80094e8:	781b      	ldrb	r3, [r3, #0]
- 80094ea:	f003 0308 	and.w	r3, r3, #8
- 80094ee:	2b00      	cmp	r3, #0
- 80094f0:	d006      	beq.n	8009500 <tcp_input+0x514>
-      p->flags |= PBUF_FLAG_PUSH;
- 80094f2:	687b      	ldr	r3, [r7, #4]
- 80094f4:	7b5b      	ldrb	r3, [r3, #13]
- 80094f6:	f043 0301 	orr.w	r3, r3, #1
- 80094fa:	b2da      	uxtb	r2, r3
- 80094fc:	687b      	ldr	r3, [r7, #4]
- 80094fe:	735a      	strb	r2, [r3, #13]
-    }
-
-    /* If there is data which was previously "refused" by upper layer */
-    if (pcb->refused_data != NULL) {
- 8009500:	69bb      	ldr	r3, [r7, #24]
- 8009502:	6f9b      	ldr	r3, [r3, #120]	; 0x78
- 8009504:	2b00      	cmp	r3, #0
- 8009506:	d017      	beq.n	8009538 <tcp_input+0x54c>
-      if ((tcp_process_refused_data(pcb) == ERR_ABRT) ||
- 8009508:	69b8      	ldr	r0, [r7, #24]
- 800950a:	f7ff f8a3 	bl	8008654 <tcp_process_refused_data>
- 800950e:	4603      	mov	r3, r0
- 8009510:	f113 0f0d 	cmn.w	r3, #13
- 8009514:	d007      	beq.n	8009526 <tcp_input+0x53a>
-          ((pcb->refused_data != NULL) && (tcplen > 0))) {
- 8009516:	69bb      	ldr	r3, [r7, #24]
- 8009518:	6f9b      	ldr	r3, [r3, #120]	; 0x78
-      if ((tcp_process_refused_data(pcb) == ERR_ABRT) ||
- 800951a:	2b00      	cmp	r3, #0
- 800951c:	d00c      	beq.n	8009538 <tcp_input+0x54c>
-          ((pcb->refused_data != NULL) && (tcplen > 0))) {
- 800951e:	4b82      	ldr	r3, [pc, #520]	; (8009728 <tcp_input+0x73c>)
- 8009520:	881b      	ldrh	r3, [r3, #0]
- 8009522:	2b00      	cmp	r3, #0
- 8009524:	d008      	beq.n	8009538 <tcp_input+0x54c>
-        /* pcb has been aborted or refused data is still refused and the new
-           segment contains data */
-        if (pcb->rcv_ann_wnd == 0) {
- 8009526:	69bb      	ldr	r3, [r7, #24]
- 8009528:	8d5b      	ldrh	r3, [r3, #42]	; 0x2a
- 800952a:	2b00      	cmp	r3, #0
- 800952c:	f040 80e3 	bne.w	80096f6 <tcp_input+0x70a>
-          /* this is a zero-window probe, we respond to it with current RCV.NXT
-          and drop the data segment */
-          tcp_send_empty_ack(pcb);
- 8009530:	69b8      	ldr	r0, [r7, #24]
- 8009532:	f003 fe71 	bl	800d218 <tcp_send_empty_ack>
-        }
-        TCP_STATS_INC(tcp.drop);
-        MIB2_STATS_INC(mib2.tcpinerrs);
-        goto aborted;
- 8009536:	e0de      	b.n	80096f6 <tcp_input+0x70a>
-      }
-    }
-    tcp_input_pcb = pcb;
- 8009538:	4a7c      	ldr	r2, [pc, #496]	; (800972c <tcp_input+0x740>)
- 800953a:	69bb      	ldr	r3, [r7, #24]
- 800953c:	6013      	str	r3, [r2, #0]
-    err = tcp_process(pcb);
- 800953e:	69b8      	ldr	r0, [r7, #24]
- 8009540:	f000 fb18 	bl	8009b74 <tcp_process>
- 8009544:	4603      	mov	r3, r0
- 8009546:	74fb      	strb	r3, [r7, #19]
-    /* A return value of ERR_ABRT means that tcp_abort() was called
-       and that the pcb has been freed. If so, we don't do anything. */
-    if (err != ERR_ABRT) {
- 8009548:	f997 3013 	ldrsb.w	r3, [r7, #19]
- 800954c:	f113 0f0d 	cmn.w	r3, #13
- 8009550:	f000 80d3 	beq.w	80096fa <tcp_input+0x70e>
-      if (recv_flags & TF_RESET) {
- 8009554:	4b71      	ldr	r3, [pc, #452]	; (800971c <tcp_input+0x730>)
- 8009556:	781b      	ldrb	r3, [r3, #0]
- 8009558:	f003 0308 	and.w	r3, r3, #8
- 800955c:	2b00      	cmp	r3, #0
- 800955e:	d015      	beq.n	800958c <tcp_input+0x5a0>
-        /* TF_RESET means that the connection was reset by the other
-           end. We then call the error callback to inform the
-           application that the connection is dead before we
-           deallocate the PCB. */
-        TCP_EVENT_ERR(pcb->state, pcb->errf, pcb->callback_arg, ERR_RST);
- 8009560:	69bb      	ldr	r3, [r7, #24]
- 8009562:	f8d3 3090 	ldr.w	r3, [r3, #144]	; 0x90
- 8009566:	2b00      	cmp	r3, #0
- 8009568:	d008      	beq.n	800957c <tcp_input+0x590>
- 800956a:	69bb      	ldr	r3, [r7, #24]
- 800956c:	f8d3 3090 	ldr.w	r3, [r3, #144]	; 0x90
- 8009570:	69ba      	ldr	r2, [r7, #24]
- 8009572:	6912      	ldr	r2, [r2, #16]
- 8009574:	f06f 010d 	mvn.w	r1, #13
- 8009578:	4610      	mov	r0, r2
- 800957a:	4798      	blx	r3
-        tcp_pcb_remove(&tcp_active_pcbs, pcb);
- 800957c:	69b9      	ldr	r1, [r7, #24]
- 800957e:	486c      	ldr	r0, [pc, #432]	; (8009730 <tcp_input+0x744>)
- 8009580:	f7ff fbb6 	bl	8008cf0 <tcp_pcb_remove>
-        tcp_free(pcb);
- 8009584:	69b8      	ldr	r0, [r7, #24]
- 8009586:	f7fd ffc5 	bl	8007514 <tcp_free>
- 800958a:	e0da      	b.n	8009742 <tcp_input+0x756>
-      } else {
-        err = ERR_OK;
- 800958c:	2300      	movs	r3, #0
- 800958e:	74fb      	strb	r3, [r7, #19]
-        /* If the application has registered a "sent" function to be
-           called when new send buffer space is available, we call it
-           now. */
-        if (recv_acked > 0) {
- 8009590:	4b63      	ldr	r3, [pc, #396]	; (8009720 <tcp_input+0x734>)
- 8009592:	881b      	ldrh	r3, [r3, #0]
- 8009594:	2b00      	cmp	r3, #0
- 8009596:	d01d      	beq.n	80095d4 <tcp_input+0x5e8>
-          while (acked > 0) {
-            acked16 = (u16_t)LWIP_MIN(acked, 0xffffu);
-            acked -= acked16;
-#else
-          {
-            acked16 = recv_acked;
- 8009598:	4b61      	ldr	r3, [pc, #388]	; (8009720 <tcp_input+0x734>)
- 800959a:	881b      	ldrh	r3, [r3, #0]
- 800959c:	81fb      	strh	r3, [r7, #14]
-#endif
-            TCP_EVENT_SENT(pcb, (u16_t)acked16, err);
- 800959e:	69bb      	ldr	r3, [r7, #24]
- 80095a0:	f8d3 3080 	ldr.w	r3, [r3, #128]	; 0x80
- 80095a4:	2b00      	cmp	r3, #0
- 80095a6:	d00a      	beq.n	80095be <tcp_input+0x5d2>
- 80095a8:	69bb      	ldr	r3, [r7, #24]
- 80095aa:	f8d3 3080 	ldr.w	r3, [r3, #128]	; 0x80
- 80095ae:	69ba      	ldr	r2, [r7, #24]
- 80095b0:	6910      	ldr	r0, [r2, #16]
- 80095b2:	89fa      	ldrh	r2, [r7, #14]
- 80095b4:	69b9      	ldr	r1, [r7, #24]
- 80095b6:	4798      	blx	r3
- 80095b8:	4603      	mov	r3, r0
- 80095ba:	74fb      	strb	r3, [r7, #19]
- 80095bc:	e001      	b.n	80095c2 <tcp_input+0x5d6>
- 80095be:	2300      	movs	r3, #0
- 80095c0:	74fb      	strb	r3, [r7, #19]
-            if (err == ERR_ABRT) {
- 80095c2:	f997 3013 	ldrsb.w	r3, [r7, #19]
- 80095c6:	f113 0f0d 	cmn.w	r3, #13
- 80095ca:	f000 8098 	beq.w	80096fe <tcp_input+0x712>
-              goto aborted;
-            }
-          }
-          recv_acked = 0;
- 80095ce:	4b54      	ldr	r3, [pc, #336]	; (8009720 <tcp_input+0x734>)
- 80095d0:	2200      	movs	r2, #0
- 80095d2:	801a      	strh	r2, [r3, #0]
-        }
-        if (tcp_input_delayed_close(pcb)) {
- 80095d4:	69b8      	ldr	r0, [r7, #24]
- 80095d6:	f000 f915 	bl	8009804 <tcp_input_delayed_close>
- 80095da:	4603      	mov	r3, r0
- 80095dc:	2b00      	cmp	r3, #0
- 80095de:	f040 8090 	bne.w	8009702 <tcp_input+0x716>
-#if TCP_QUEUE_OOSEQ && LWIP_WND_SCALE
-        while (recv_data != NULL) {
-          struct pbuf *rest = NULL;
-          pbuf_split_64k(recv_data, &rest);
-#else /* TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */
-        if (recv_data != NULL) {
- 80095e2:	4b4d      	ldr	r3, [pc, #308]	; (8009718 <tcp_input+0x72c>)
- 80095e4:	681b      	ldr	r3, [r3, #0]
- 80095e6:	2b00      	cmp	r3, #0
- 80095e8:	d041      	beq.n	800966e <tcp_input+0x682>
-#endif /* TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */
-
-          LWIP_ASSERT("pcb->refused_data == NULL", pcb->refused_data == NULL);
- 80095ea:	69bb      	ldr	r3, [r7, #24]
- 80095ec:	6f9b      	ldr	r3, [r3, #120]	; 0x78
- 80095ee:	2b00      	cmp	r3, #0
- 80095f0:	d006      	beq.n	8009600 <tcp_input+0x614>
- 80095f2:	4b50      	ldr	r3, [pc, #320]	; (8009734 <tcp_input+0x748>)
- 80095f4:	f44f 72f3 	mov.w	r2, #486	; 0x1e6
- 80095f8:	494f      	ldr	r1, [pc, #316]	; (8009738 <tcp_input+0x74c>)
- 80095fa:	4850      	ldr	r0, [pc, #320]	; (800973c <tcp_input+0x750>)
- 80095fc:	f007 fae4 	bl	8010bc8 <iprintf>
-          if (pcb->flags & TF_RXCLOSED) {
- 8009600:	69bb      	ldr	r3, [r7, #24]
- 8009602:	8b5b      	ldrh	r3, [r3, #26]
- 8009604:	f003 0310 	and.w	r3, r3, #16
- 8009608:	2b00      	cmp	r3, #0
- 800960a:	d008      	beq.n	800961e <tcp_input+0x632>
-            /* received data although already closed -> abort (send RST) to
-               notify the remote host that not all data has been processed */
-            pbuf_free(recv_data);
- 800960c:	4b42      	ldr	r3, [pc, #264]	; (8009718 <tcp_input+0x72c>)
- 800960e:	681b      	ldr	r3, [r3, #0]
- 8009610:	4618      	mov	r0, r3
- 8009612:	f7fd fcdf 	bl	8006fd4 <pbuf_free>
-#if TCP_QUEUE_OOSEQ && LWIP_WND_SCALE
-            if (rest != NULL) {
-              pbuf_free(rest);
-            }
-#endif /* TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */
-            tcp_abort(pcb);
- 8009616:	69b8      	ldr	r0, [r7, #24]
- 8009618:	f7fe fa64 	bl	8007ae4 <tcp_abort>
-            goto aborted;
- 800961c:	e091      	b.n	8009742 <tcp_input+0x756>
-          }
-
-          /* Notify application that data has been received. */
-          TCP_EVENT_RECV(pcb, recv_data, ERR_OK, err);
- 800961e:	69bb      	ldr	r3, [r7, #24]
- 8009620:	f8d3 3084 	ldr.w	r3, [r3, #132]	; 0x84
- 8009624:	2b00      	cmp	r3, #0
- 8009626:	d00c      	beq.n	8009642 <tcp_input+0x656>
- 8009628:	69bb      	ldr	r3, [r7, #24]
- 800962a:	f8d3 4084 	ldr.w	r4, [r3, #132]	; 0x84
- 800962e:	69bb      	ldr	r3, [r7, #24]
- 8009630:	6918      	ldr	r0, [r3, #16]
- 8009632:	4b39      	ldr	r3, [pc, #228]	; (8009718 <tcp_input+0x72c>)
- 8009634:	681a      	ldr	r2, [r3, #0]
- 8009636:	2300      	movs	r3, #0
- 8009638:	69b9      	ldr	r1, [r7, #24]
- 800963a:	47a0      	blx	r4
- 800963c:	4603      	mov	r3, r0
- 800963e:	74fb      	strb	r3, [r7, #19]
- 8009640:	e008      	b.n	8009654 <tcp_input+0x668>
- 8009642:	4b35      	ldr	r3, [pc, #212]	; (8009718 <tcp_input+0x72c>)
- 8009644:	681a      	ldr	r2, [r3, #0]
- 8009646:	2300      	movs	r3, #0
- 8009648:	69b9      	ldr	r1, [r7, #24]
- 800964a:	2000      	movs	r0, #0
- 800964c:	f7ff f8d8 	bl	8008800 <tcp_recv_null>
- 8009650:	4603      	mov	r3, r0
- 8009652:	74fb      	strb	r3, [r7, #19]
-          if (err == ERR_ABRT) {
- 8009654:	f997 3013 	ldrsb.w	r3, [r7, #19]
- 8009658:	f113 0f0d 	cmn.w	r3, #13
- 800965c:	d053      	beq.n	8009706 <tcp_input+0x71a>
-#endif /* TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */
-            goto aborted;
-          }
-
-          /* If the upper layer can't receive this data, store it */
-          if (err != ERR_OK) {
- 800965e:	f997 3013 	ldrsb.w	r3, [r7, #19]
- 8009662:	2b00      	cmp	r3, #0
- 8009664:	d003      	beq.n	800966e <tcp_input+0x682>
-#if TCP_QUEUE_OOSEQ && LWIP_WND_SCALE
-            if (rest != NULL) {
-              pbuf_cat(recv_data, rest);
-            }
-#endif /* TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */
-            pcb->refused_data = recv_data;
- 8009666:	4b2c      	ldr	r3, [pc, #176]	; (8009718 <tcp_input+0x72c>)
- 8009668:	681a      	ldr	r2, [r3, #0]
- 800966a:	69bb      	ldr	r3, [r7, #24]
- 800966c:	679a      	str	r2, [r3, #120]	; 0x78
-          }
-        }
-
-        /* If a FIN segment was received, we call the callback
-           function with a NULL buffer to indicate EOF. */
-        if (recv_flags & TF_GOT_FIN) {
- 800966e:	4b2b      	ldr	r3, [pc, #172]	; (800971c <tcp_input+0x730>)
- 8009670:	781b      	ldrb	r3, [r3, #0]
- 8009672:	f003 0320 	and.w	r3, r3, #32
- 8009676:	2b00      	cmp	r3, #0
- 8009678:	d030      	beq.n	80096dc <tcp_input+0x6f0>
-          if (pcb->refused_data != NULL) {
- 800967a:	69bb      	ldr	r3, [r7, #24]
- 800967c:	6f9b      	ldr	r3, [r3, #120]	; 0x78
- 800967e:	2b00      	cmp	r3, #0
- 8009680:	d009      	beq.n	8009696 <tcp_input+0x6aa>
-            /* Delay this if we have refused data. */
-            pcb->refused_data->flags |= PBUF_FLAG_TCP_FIN;
- 8009682:	69bb      	ldr	r3, [r7, #24]
- 8009684:	6f9b      	ldr	r3, [r3, #120]	; 0x78
- 8009686:	7b5a      	ldrb	r2, [r3, #13]
- 8009688:	69bb      	ldr	r3, [r7, #24]
- 800968a:	6f9b      	ldr	r3, [r3, #120]	; 0x78
- 800968c:	f042 0220 	orr.w	r2, r2, #32
- 8009690:	b2d2      	uxtb	r2, r2
- 8009692:	735a      	strb	r2, [r3, #13]
- 8009694:	e022      	b.n	80096dc <tcp_input+0x6f0>
-          } else {
-            /* correct rcv_wnd as the application won't call tcp_recved()
-               for the FIN's seqno */
-            if (pcb->rcv_wnd != TCP_WND_MAX(pcb)) {
- 8009696:	69bb      	ldr	r3, [r7, #24]
- 8009698:	8d1b      	ldrh	r3, [r3, #40]	; 0x28
- 800969a:	f5b3 6f06 	cmp.w	r3, #2144	; 0x860
- 800969e:	d005      	beq.n	80096ac <tcp_input+0x6c0>
-              pcb->rcv_wnd++;
- 80096a0:	69bb      	ldr	r3, [r7, #24]
- 80096a2:	8d1b      	ldrh	r3, [r3, #40]	; 0x28
- 80096a4:	3301      	adds	r3, #1
- 80096a6:	b29a      	uxth	r2, r3
- 80096a8:	69bb      	ldr	r3, [r7, #24]
- 80096aa:	851a      	strh	r2, [r3, #40]	; 0x28
-            }
-            TCP_EVENT_CLOSED(pcb, err);
- 80096ac:	69bb      	ldr	r3, [r7, #24]
- 80096ae:	f8d3 3084 	ldr.w	r3, [r3, #132]	; 0x84
- 80096b2:	2b00      	cmp	r3, #0
- 80096b4:	d00b      	beq.n	80096ce <tcp_input+0x6e2>
- 80096b6:	69bb      	ldr	r3, [r7, #24]
- 80096b8:	f8d3 4084 	ldr.w	r4, [r3, #132]	; 0x84
- 80096bc:	69bb      	ldr	r3, [r7, #24]
- 80096be:	6918      	ldr	r0, [r3, #16]
- 80096c0:	2300      	movs	r3, #0
- 80096c2:	2200      	movs	r2, #0
- 80096c4:	69b9      	ldr	r1, [r7, #24]
- 80096c6:	47a0      	blx	r4
- 80096c8:	4603      	mov	r3, r0
- 80096ca:	74fb      	strb	r3, [r7, #19]
- 80096cc:	e001      	b.n	80096d2 <tcp_input+0x6e6>
- 80096ce:	2300      	movs	r3, #0
- 80096d0:	74fb      	strb	r3, [r7, #19]
-            if (err == ERR_ABRT) {
- 80096d2:	f997 3013 	ldrsb.w	r3, [r7, #19]
- 80096d6:	f113 0f0d 	cmn.w	r3, #13
- 80096da:	d016      	beq.n	800970a <tcp_input+0x71e>
-              goto aborted;
-            }
-          }
-        }
-
-        tcp_input_pcb = NULL;
- 80096dc:	4b13      	ldr	r3, [pc, #76]	; (800972c <tcp_input+0x740>)
- 80096de:	2200      	movs	r2, #0
- 80096e0:	601a      	str	r2, [r3, #0]
-        if (tcp_input_delayed_close(pcb)) {
- 80096e2:	69b8      	ldr	r0, [r7, #24]
- 80096e4:	f000 f88e 	bl	8009804 <tcp_input_delayed_close>
- 80096e8:	4603      	mov	r3, r0
- 80096ea:	2b00      	cmp	r3, #0
- 80096ec:	d128      	bne.n	8009740 <tcp_input+0x754>
-          goto aborted;
-        }
-        /* Try to send something out. */
-        tcp_output(pcb);
- 80096ee:	69b8      	ldr	r0, [r7, #24]
- 80096f0:	f002 ff80 	bl	800c5f4 <tcp_output>
- 80096f4:	e025      	b.n	8009742 <tcp_input+0x756>
-        goto aborted;
- 80096f6:	bf00      	nop
- 80096f8:	e023      	b.n	8009742 <tcp_input+0x756>
-#endif /* TCP_INPUT_DEBUG */
-      }
-    }
-    /* Jump target if pcb has been aborted in a callback (by calling tcp_abort()).
-       Below this line, 'pcb' may not be dereferenced! */
-aborted:
- 80096fa:	bf00      	nop
- 80096fc:	e021      	b.n	8009742 <tcp_input+0x756>
-              goto aborted;
- 80096fe:	bf00      	nop
- 8009700:	e01f      	b.n	8009742 <tcp_input+0x756>
-          goto aborted;
- 8009702:	bf00      	nop
- 8009704:	e01d      	b.n	8009742 <tcp_input+0x756>
-            goto aborted;
- 8009706:	bf00      	nop
- 8009708:	e01b      	b.n	8009742 <tcp_input+0x756>
-              goto aborted;
- 800970a:	bf00      	nop
- 800970c:	e019      	b.n	8009742 <tcp_input+0x756>
- 800970e:	bf00      	nop
- 8009710:	24007b84 	.word	0x24007b84
- 8009714:	24007b98 	.word	0x24007b98
- 8009718:	24007bb8 	.word	0x24007bb8
- 800971c:	24007bb5 	.word	0x24007bb5
- 8009720:	24007bb0 	.word	0x24007bb0
- 8009724:	24007bb4 	.word	0x24007bb4
- 8009728:	24007bb2 	.word	0x24007bb2
- 800972c:	24007bbc 	.word	0x24007bbc
- 8009730:	24007b78 	.word	0x24007b78
- 8009734:	08013198 	.word	0x08013198
- 8009738:	0801334c 	.word	0x0801334c
- 800973c:	080131e4 	.word	0x080131e4
-          goto aborted;
- 8009740:	bf00      	nop
-    tcp_input_pcb = NULL;
- 8009742:	4b27      	ldr	r3, [pc, #156]	; (80097e0 <tcp_input+0x7f4>)
- 8009744:	2200      	movs	r2, #0
- 8009746:	601a      	str	r2, [r3, #0]
-    recv_data = NULL;
- 8009748:	4b26      	ldr	r3, [pc, #152]	; (80097e4 <tcp_input+0x7f8>)
- 800974a:	2200      	movs	r2, #0
- 800974c:	601a      	str	r2, [r3, #0]
-
-    /* give up our reference to inseg.p */
-    if (inseg.p != NULL) {
- 800974e:	4b26      	ldr	r3, [pc, #152]	; (80097e8 <tcp_input+0x7fc>)
- 8009750:	685b      	ldr	r3, [r3, #4]
- 8009752:	2b00      	cmp	r3, #0
- 8009754:	d03f      	beq.n	80097d6 <tcp_input+0x7ea>
-      pbuf_free(inseg.p);
- 8009756:	4b24      	ldr	r3, [pc, #144]	; (80097e8 <tcp_input+0x7fc>)
- 8009758:	685b      	ldr	r3, [r3, #4]
- 800975a:	4618      	mov	r0, r3
- 800975c:	f7fd fc3a 	bl	8006fd4 <pbuf_free>
-      inseg.p = NULL;
- 8009760:	4b21      	ldr	r3, [pc, #132]	; (80097e8 <tcp_input+0x7fc>)
- 8009762:	2200      	movs	r2, #0
- 8009764:	605a      	str	r2, [r3, #4]
-    pbuf_free(p);
-  }
-
-  LWIP_ASSERT("tcp_input: tcp_pcbs_sane()", tcp_pcbs_sane());
-  PERF_STOP("tcp_input");
-  return;
- 8009766:	e036      	b.n	80097d6 <tcp_input+0x7ea>
-    if (!(TCPH_FLAGS(tcphdr) & TCP_RST)) {
- 8009768:	4b20      	ldr	r3, [pc, #128]	; (80097ec <tcp_input+0x800>)
- 800976a:	681b      	ldr	r3, [r3, #0]
- 800976c:	899b      	ldrh	r3, [r3, #12]
- 800976e:	b29b      	uxth	r3, r3
- 8009770:	4618      	mov	r0, r3
- 8009772:	f7fb feeb 	bl	800554c <lwip_htons>
- 8009776:	4603      	mov	r3, r0
- 8009778:	b2db      	uxtb	r3, r3
- 800977a:	f003 0304 	and.w	r3, r3, #4
- 800977e:	2b00      	cmp	r3, #0
- 8009780:	d118      	bne.n	80097b4 <tcp_input+0x7c8>
-      tcp_rst(NULL, ackno, seqno + tcplen, ip_current_dest_addr(),
- 8009782:	4b1b      	ldr	r3, [pc, #108]	; (80097f0 <tcp_input+0x804>)
- 8009784:	6819      	ldr	r1, [r3, #0]
- 8009786:	4b1b      	ldr	r3, [pc, #108]	; (80097f4 <tcp_input+0x808>)
- 8009788:	881b      	ldrh	r3, [r3, #0]
- 800978a:	461a      	mov	r2, r3
- 800978c:	4b1a      	ldr	r3, [pc, #104]	; (80097f8 <tcp_input+0x80c>)
- 800978e:	681b      	ldr	r3, [r3, #0]
- 8009790:	18d0      	adds	r0, r2, r3
-              ip_current_src_addr(), tcphdr->dest, tcphdr->src);
- 8009792:	4b16      	ldr	r3, [pc, #88]	; (80097ec <tcp_input+0x800>)
- 8009794:	681b      	ldr	r3, [r3, #0]
-      tcp_rst(NULL, ackno, seqno + tcplen, ip_current_dest_addr(),
- 8009796:	885b      	ldrh	r3, [r3, #2]
- 8009798:	b29b      	uxth	r3, r3
-              ip_current_src_addr(), tcphdr->dest, tcphdr->src);
- 800979a:	4a14      	ldr	r2, [pc, #80]	; (80097ec <tcp_input+0x800>)
- 800979c:	6812      	ldr	r2, [r2, #0]
-      tcp_rst(NULL, ackno, seqno + tcplen, ip_current_dest_addr(),
- 800979e:	8812      	ldrh	r2, [r2, #0]
- 80097a0:	b292      	uxth	r2, r2
- 80097a2:	9202      	str	r2, [sp, #8]
- 80097a4:	9301      	str	r3, [sp, #4]
- 80097a6:	4b15      	ldr	r3, [pc, #84]	; (80097fc <tcp_input+0x810>)
- 80097a8:	9300      	str	r3, [sp, #0]
- 80097aa:	4b15      	ldr	r3, [pc, #84]	; (8009800 <tcp_input+0x814>)
- 80097ac:	4602      	mov	r2, r0
- 80097ae:	2000      	movs	r0, #0
- 80097b0:	f003 fce0 	bl	800d174 <tcp_rst>
-    pbuf_free(p);
- 80097b4:	6878      	ldr	r0, [r7, #4]
- 80097b6:	f7fd fc0d 	bl	8006fd4 <pbuf_free>
-  return;
- 80097ba:	e00c      	b.n	80097d6 <tcp_input+0x7ea>
-    goto dropped;
- 80097bc:	bf00      	nop
- 80097be:	e006      	b.n	80097ce <tcp_input+0x7e2>
-    goto dropped;
- 80097c0:	bf00      	nop
- 80097c2:	e004      	b.n	80097ce <tcp_input+0x7e2>
-    goto dropped;
- 80097c4:	bf00      	nop
- 80097c6:	e002      	b.n	80097ce <tcp_input+0x7e2>
-      goto dropped;
- 80097c8:	bf00      	nop
- 80097ca:	e000      	b.n	80097ce <tcp_input+0x7e2>
-      goto dropped;
- 80097cc:	bf00      	nop
-dropped:
-  TCP_STATS_INC(tcp.drop);
-  MIB2_STATS_INC(mib2.tcpinerrs);
-  pbuf_free(p);
- 80097ce:	6878      	ldr	r0, [r7, #4]
- 80097d0:	f7fd fc00 	bl	8006fd4 <pbuf_free>
- 80097d4:	e000      	b.n	80097d8 <tcp_input+0x7ec>
-  return;
- 80097d6:	bf00      	nop
-}
- 80097d8:	3724      	adds	r7, #36	; 0x24
- 80097da:	46bd      	mov	sp, r7
- 80097dc:	bd90      	pop	{r4, r7, pc}
- 80097de:	bf00      	nop
- 80097e0:	24007bbc 	.word	0x24007bbc
- 80097e4:	24007bb8 	.word	0x24007bb8
- 80097e8:	24007b84 	.word	0x24007b84
- 80097ec:	24007b98 	.word	0x24007b98
- 80097f0:	24007bac 	.word	0x24007bac
- 80097f4:	24007bb2 	.word	0x24007bb2
- 80097f8:	24007ba8 	.word	0x24007ba8
- 80097fc:	24004c20 	.word	0x24004c20
- 8009800:	24004c24 	.word	0x24004c24
-
-08009804 <tcp_input_delayed_close>:
- * any more.
- * @returns 1 if the pcb has been closed and deallocated, 0 otherwise
- */
-static int
-tcp_input_delayed_close(struct tcp_pcb *pcb)
-{
- 8009804:	b580      	push	{r7, lr}
- 8009806:	b082      	sub	sp, #8
- 8009808:	af00      	add	r7, sp, #0
- 800980a:	6078      	str	r0, [r7, #4]
-  LWIP_ASSERT("tcp_input_delayed_close: invalid pcb", pcb != NULL);
- 800980c:	687b      	ldr	r3, [r7, #4]
- 800980e:	2b00      	cmp	r3, #0
- 8009810:	d106      	bne.n	8009820 <tcp_input_delayed_close+0x1c>
- 8009812:	4b17      	ldr	r3, [pc, #92]	; (8009870 <tcp_input_delayed_close+0x6c>)
- 8009814:	f240 225a 	movw	r2, #602	; 0x25a
- 8009818:	4916      	ldr	r1, [pc, #88]	; (8009874 <tcp_input_delayed_close+0x70>)
- 800981a:	4817      	ldr	r0, [pc, #92]	; (8009878 <tcp_input_delayed_close+0x74>)
- 800981c:	f007 f9d4 	bl	8010bc8 <iprintf>
-
-  if (recv_flags & TF_CLOSED) {
- 8009820:	4b16      	ldr	r3, [pc, #88]	; (800987c <tcp_input_delayed_close+0x78>)
- 8009822:	781b      	ldrb	r3, [r3, #0]
- 8009824:	f003 0310 	and.w	r3, r3, #16
- 8009828:	2b00      	cmp	r3, #0
- 800982a:	d01c      	beq.n	8009866 <tcp_input_delayed_close+0x62>
-    /* The connection has been closed and we will deallocate the
-        PCB. */
-    if (!(pcb->flags & TF_RXCLOSED)) {
- 800982c:	687b      	ldr	r3, [r7, #4]
- 800982e:	8b5b      	ldrh	r3, [r3, #26]
- 8009830:	f003 0310 	and.w	r3, r3, #16
- 8009834:	2b00      	cmp	r3, #0
- 8009836:	d10d      	bne.n	8009854 <tcp_input_delayed_close+0x50>
-      /* Connection closed although the application has only shut down the
-          tx side: call the PCB's err callback and indicate the closure to
-          ensure the application doesn't continue using the PCB. */
-      TCP_EVENT_ERR(pcb->state, pcb->errf, pcb->callback_arg, ERR_CLSD);
- 8009838:	687b      	ldr	r3, [r7, #4]
- 800983a:	f8d3 3090 	ldr.w	r3, [r3, #144]	; 0x90
- 800983e:	2b00      	cmp	r3, #0
- 8009840:	d008      	beq.n	8009854 <tcp_input_delayed_close+0x50>
- 8009842:	687b      	ldr	r3, [r7, #4]
- 8009844:	f8d3 3090 	ldr.w	r3, [r3, #144]	; 0x90
- 8009848:	687a      	ldr	r2, [r7, #4]
- 800984a:	6912      	ldr	r2, [r2, #16]
- 800984c:	f06f 010e 	mvn.w	r1, #14
- 8009850:	4610      	mov	r0, r2
- 8009852:	4798      	blx	r3
-    }
-    tcp_pcb_remove(&tcp_active_pcbs, pcb);
- 8009854:	6879      	ldr	r1, [r7, #4]
- 8009856:	480a      	ldr	r0, [pc, #40]	; (8009880 <tcp_input_delayed_close+0x7c>)
- 8009858:	f7ff fa4a 	bl	8008cf0 <tcp_pcb_remove>
-    tcp_free(pcb);
- 800985c:	6878      	ldr	r0, [r7, #4]
- 800985e:	f7fd fe59 	bl	8007514 <tcp_free>
-    return 1;
- 8009862:	2301      	movs	r3, #1
- 8009864:	e000      	b.n	8009868 <tcp_input_delayed_close+0x64>
-  }
-  return 0;
- 8009866:	2300      	movs	r3, #0
-}
- 8009868:	4618      	mov	r0, r3
- 800986a:	3708      	adds	r7, #8
- 800986c:	46bd      	mov	sp, r7
- 800986e:	bd80      	pop	{r7, pc}
- 8009870:	08013198 	.word	0x08013198
- 8009874:	08013368 	.word	0x08013368
- 8009878:	080131e4 	.word	0x080131e4
- 800987c:	24007bb5 	.word	0x24007bb5
- 8009880:	24007b78 	.word	0x24007b78
-
-08009884 <tcp_listen_input>:
- * @note the segment which arrived is saved in global variables, therefore only the pcb
- *       involved is passed as a parameter to this function
- */
-static void
-tcp_listen_input(struct tcp_pcb_listen *pcb)
-{
- 8009884:	b590      	push	{r4, r7, lr}
- 8009886:	b08b      	sub	sp, #44	; 0x2c
- 8009888:	af04      	add	r7, sp, #16
- 800988a:	6078      	str	r0, [r7, #4]
-  struct tcp_pcb *npcb;
-  u32_t iss;
-  err_t rc;
-
-  if (flags & TCP_RST) {
- 800988c:	4b6f      	ldr	r3, [pc, #444]	; (8009a4c <tcp_listen_input+0x1c8>)
- 800988e:	781b      	ldrb	r3, [r3, #0]
- 8009890:	f003 0304 	and.w	r3, r3, #4
- 8009894:	2b00      	cmp	r3, #0
- 8009896:	f040 80d2 	bne.w	8009a3e <tcp_listen_input+0x1ba>
-    /* An incoming RST should be ignored. Return. */
-    return;
-  }
-
-  LWIP_ASSERT("tcp_listen_input: invalid pcb", pcb != NULL);
- 800989a:	687b      	ldr	r3, [r7, #4]
- 800989c:	2b00      	cmp	r3, #0
- 800989e:	d106      	bne.n	80098ae <tcp_listen_input+0x2a>
- 80098a0:	4b6b      	ldr	r3, [pc, #428]	; (8009a50 <tcp_listen_input+0x1cc>)
- 80098a2:	f240 2281 	movw	r2, #641	; 0x281
- 80098a6:	496b      	ldr	r1, [pc, #428]	; (8009a54 <tcp_listen_input+0x1d0>)
- 80098a8:	486b      	ldr	r0, [pc, #428]	; (8009a58 <tcp_listen_input+0x1d4>)
- 80098aa:	f007 f98d 	bl	8010bc8 <iprintf>
-
-  /* In the LISTEN state, we check for incoming SYN segments,
-     creates a new PCB, and responds with a SYN|ACK. */
-  if (flags & TCP_ACK) {
- 80098ae:	4b67      	ldr	r3, [pc, #412]	; (8009a4c <tcp_listen_input+0x1c8>)
- 80098b0:	781b      	ldrb	r3, [r3, #0]
- 80098b2:	f003 0310 	and.w	r3, r3, #16
- 80098b6:	2b00      	cmp	r3, #0
- 80098b8:	d019      	beq.n	80098ee <tcp_listen_input+0x6a>
-    /* For incoming segments with the ACK flag set, respond with a
-       RST. */
-    LWIP_DEBUGF(TCP_RST_DEBUG, ("tcp_listen_input: ACK in LISTEN, sending reset\n"));
-    tcp_rst((const struct tcp_pcb *)pcb, ackno, seqno + tcplen, ip_current_dest_addr(),
- 80098ba:	4b68      	ldr	r3, [pc, #416]	; (8009a5c <tcp_listen_input+0x1d8>)
- 80098bc:	6819      	ldr	r1, [r3, #0]
- 80098be:	4b68      	ldr	r3, [pc, #416]	; (8009a60 <tcp_listen_input+0x1dc>)
- 80098c0:	881b      	ldrh	r3, [r3, #0]
- 80098c2:	461a      	mov	r2, r3
- 80098c4:	4b67      	ldr	r3, [pc, #412]	; (8009a64 <tcp_listen_input+0x1e0>)
- 80098c6:	681b      	ldr	r3, [r3, #0]
- 80098c8:	18d0      	adds	r0, r2, r3
-            ip_current_src_addr(), tcphdr->dest, tcphdr->src);
- 80098ca:	4b67      	ldr	r3, [pc, #412]	; (8009a68 <tcp_listen_input+0x1e4>)
- 80098cc:	681b      	ldr	r3, [r3, #0]
-    tcp_rst((const struct tcp_pcb *)pcb, ackno, seqno + tcplen, ip_current_dest_addr(),
- 80098ce:	885b      	ldrh	r3, [r3, #2]
- 80098d0:	b29b      	uxth	r3, r3
-            ip_current_src_addr(), tcphdr->dest, tcphdr->src);
- 80098d2:	4a65      	ldr	r2, [pc, #404]	; (8009a68 <tcp_listen_input+0x1e4>)
- 80098d4:	6812      	ldr	r2, [r2, #0]
-    tcp_rst((const struct tcp_pcb *)pcb, ackno, seqno + tcplen, ip_current_dest_addr(),
- 80098d6:	8812      	ldrh	r2, [r2, #0]
- 80098d8:	b292      	uxth	r2, r2
- 80098da:	9202      	str	r2, [sp, #8]
- 80098dc:	9301      	str	r3, [sp, #4]
- 80098de:	4b63      	ldr	r3, [pc, #396]	; (8009a6c <tcp_listen_input+0x1e8>)
- 80098e0:	9300      	str	r3, [sp, #0]
- 80098e2:	4b63      	ldr	r3, [pc, #396]	; (8009a70 <tcp_listen_input+0x1ec>)
- 80098e4:	4602      	mov	r2, r0
- 80098e6:	6878      	ldr	r0, [r7, #4]
- 80098e8:	f003 fc44 	bl	800d174 <tcp_rst>
-      tcp_abandon(npcb, 0);
-      return;
-    }
-    tcp_output(npcb);
-  }
-  return;
- 80098ec:	e0a9      	b.n	8009a42 <tcp_listen_input+0x1be>
-  } else if (flags & TCP_SYN) {
- 80098ee:	4b57      	ldr	r3, [pc, #348]	; (8009a4c <tcp_listen_input+0x1c8>)
- 80098f0:	781b      	ldrb	r3, [r3, #0]
- 80098f2:	f003 0302 	and.w	r3, r3, #2
- 80098f6:	2b00      	cmp	r3, #0
- 80098f8:	f000 80a3 	beq.w	8009a42 <tcp_listen_input+0x1be>
-    npcb = tcp_alloc(pcb->prio);
- 80098fc:	687b      	ldr	r3, [r7, #4]
- 80098fe:	7d5b      	ldrb	r3, [r3, #21]
- 8009900:	4618      	mov	r0, r3
- 8009902:	f7ff f8a1 	bl	8008a48 <tcp_alloc>
- 8009906:	6178      	str	r0, [r7, #20]
-    if (npcb == NULL) {
- 8009908:	697b      	ldr	r3, [r7, #20]
- 800990a:	2b00      	cmp	r3, #0
- 800990c:	d111      	bne.n	8009932 <tcp_listen_input+0xae>
-      TCP_EVENT_ACCEPT(pcb, NULL, pcb->callback_arg, ERR_MEM, err);
- 800990e:	687b      	ldr	r3, [r7, #4]
- 8009910:	699b      	ldr	r3, [r3, #24]
- 8009912:	2b00      	cmp	r3, #0
- 8009914:	d00a      	beq.n	800992c <tcp_listen_input+0xa8>
- 8009916:	687b      	ldr	r3, [r7, #4]
- 8009918:	699b      	ldr	r3, [r3, #24]
- 800991a:	687a      	ldr	r2, [r7, #4]
- 800991c:	6910      	ldr	r0, [r2, #16]
- 800991e:	f04f 32ff 	mov.w	r2, #4294967295
- 8009922:	2100      	movs	r1, #0
- 8009924:	4798      	blx	r3
- 8009926:	4603      	mov	r3, r0
- 8009928:	73bb      	strb	r3, [r7, #14]
-      return;
- 800992a:	e08b      	b.n	8009a44 <tcp_listen_input+0x1c0>
-      TCP_EVENT_ACCEPT(pcb, NULL, pcb->callback_arg, ERR_MEM, err);
- 800992c:	23f0      	movs	r3, #240	; 0xf0
- 800992e:	73bb      	strb	r3, [r7, #14]
-      return;
- 8009930:	e088      	b.n	8009a44 <tcp_listen_input+0x1c0>
-    ip_addr_copy(npcb->local_ip, *ip_current_dest_addr());
- 8009932:	4b50      	ldr	r3, [pc, #320]	; (8009a74 <tcp_listen_input+0x1f0>)
- 8009934:	695a      	ldr	r2, [r3, #20]
- 8009936:	697b      	ldr	r3, [r7, #20]
- 8009938:	601a      	str	r2, [r3, #0]
-    ip_addr_copy(npcb->remote_ip, *ip_current_src_addr());
- 800993a:	4b4e      	ldr	r3, [pc, #312]	; (8009a74 <tcp_listen_input+0x1f0>)
- 800993c:	691a      	ldr	r2, [r3, #16]
- 800993e:	697b      	ldr	r3, [r7, #20]
- 8009940:	605a      	str	r2, [r3, #4]
-    npcb->local_port = pcb->local_port;
- 8009942:	687b      	ldr	r3, [r7, #4]
- 8009944:	8ada      	ldrh	r2, [r3, #22]
- 8009946:	697b      	ldr	r3, [r7, #20]
- 8009948:	82da      	strh	r2, [r3, #22]
-    npcb->remote_port = tcphdr->src;
- 800994a:	4b47      	ldr	r3, [pc, #284]	; (8009a68 <tcp_listen_input+0x1e4>)
- 800994c:	681b      	ldr	r3, [r3, #0]
- 800994e:	881b      	ldrh	r3, [r3, #0]
- 8009950:	b29a      	uxth	r2, r3
- 8009952:	697b      	ldr	r3, [r7, #20]
- 8009954:	831a      	strh	r2, [r3, #24]
-    npcb->state = SYN_RCVD;
- 8009956:	697b      	ldr	r3, [r7, #20]
- 8009958:	2203      	movs	r2, #3
- 800995a:	751a      	strb	r2, [r3, #20]
-    npcb->rcv_nxt = seqno + 1;
- 800995c:	4b41      	ldr	r3, [pc, #260]	; (8009a64 <tcp_listen_input+0x1e0>)
- 800995e:	681b      	ldr	r3, [r3, #0]
- 8009960:	1c5a      	adds	r2, r3, #1
- 8009962:	697b      	ldr	r3, [r7, #20]
- 8009964:	625a      	str	r2, [r3, #36]	; 0x24
-    npcb->rcv_ann_right_edge = npcb->rcv_nxt;
- 8009966:	697b      	ldr	r3, [r7, #20]
- 8009968:	6a5a      	ldr	r2, [r3, #36]	; 0x24
- 800996a:	697b      	ldr	r3, [r7, #20]
- 800996c:	62da      	str	r2, [r3, #44]	; 0x2c
-    iss = tcp_next_iss(npcb);
- 800996e:	6978      	ldr	r0, [r7, #20]
- 8009970:	f7ff fa52 	bl	8008e18 <tcp_next_iss>
- 8009974:	6138      	str	r0, [r7, #16]
-    npcb->snd_wl2 = iss;
- 8009976:	697b      	ldr	r3, [r7, #20]
- 8009978:	693a      	ldr	r2, [r7, #16]
- 800997a:	659a      	str	r2, [r3, #88]	; 0x58
-    npcb->snd_nxt = iss;
- 800997c:	697b      	ldr	r3, [r7, #20]
- 800997e:	693a      	ldr	r2, [r7, #16]
- 8009980:	651a      	str	r2, [r3, #80]	; 0x50
-    npcb->lastack = iss;
- 8009982:	697b      	ldr	r3, [r7, #20]
- 8009984:	693a      	ldr	r2, [r7, #16]
- 8009986:	645a      	str	r2, [r3, #68]	; 0x44
-    npcb->snd_lbb = iss;
- 8009988:	697b      	ldr	r3, [r7, #20]
- 800998a:	693a      	ldr	r2, [r7, #16]
- 800998c:	65da      	str	r2, [r3, #92]	; 0x5c
-    npcb->snd_wl1 = seqno - 1;/* initialise to seqno-1 to force window update */
- 800998e:	4b35      	ldr	r3, [pc, #212]	; (8009a64 <tcp_listen_input+0x1e0>)
- 8009990:	681b      	ldr	r3, [r3, #0]
- 8009992:	1e5a      	subs	r2, r3, #1
- 8009994:	697b      	ldr	r3, [r7, #20]
- 8009996:	655a      	str	r2, [r3, #84]	; 0x54
-    npcb->callback_arg = pcb->callback_arg;
- 8009998:	687b      	ldr	r3, [r7, #4]
- 800999a:	691a      	ldr	r2, [r3, #16]
- 800999c:	697b      	ldr	r3, [r7, #20]
- 800999e:	611a      	str	r2, [r3, #16]
-    npcb->listener = pcb;
- 80099a0:	697b      	ldr	r3, [r7, #20]
- 80099a2:	687a      	ldr	r2, [r7, #4]
- 80099a4:	67da      	str	r2, [r3, #124]	; 0x7c
-    npcb->so_options = pcb->so_options & SOF_INHERITED;
- 80099a6:	687b      	ldr	r3, [r7, #4]
- 80099a8:	7a5b      	ldrb	r3, [r3, #9]
- 80099aa:	f003 030c 	and.w	r3, r3, #12
- 80099ae:	b2da      	uxtb	r2, r3
- 80099b0:	697b      	ldr	r3, [r7, #20]
- 80099b2:	725a      	strb	r2, [r3, #9]
-    npcb->netif_idx = pcb->netif_idx;
- 80099b4:	687b      	ldr	r3, [r7, #4]
- 80099b6:	7a1a      	ldrb	r2, [r3, #8]
- 80099b8:	697b      	ldr	r3, [r7, #20]
- 80099ba:	721a      	strb	r2, [r3, #8]
-    TCP_REG_ACTIVE(npcb);
- 80099bc:	4b2e      	ldr	r3, [pc, #184]	; (8009a78 <tcp_listen_input+0x1f4>)
- 80099be:	681a      	ldr	r2, [r3, #0]
- 80099c0:	697b      	ldr	r3, [r7, #20]
- 80099c2:	60da      	str	r2, [r3, #12]
- 80099c4:	4a2c      	ldr	r2, [pc, #176]	; (8009a78 <tcp_listen_input+0x1f4>)
- 80099c6:	697b      	ldr	r3, [r7, #20]
- 80099c8:	6013      	str	r3, [r2, #0]
- 80099ca:	f003 fd95 	bl	800d4f8 <tcp_timer_needed>
- 80099ce:	4b2b      	ldr	r3, [pc, #172]	; (8009a7c <tcp_listen_input+0x1f8>)
- 80099d0:	2201      	movs	r2, #1
- 80099d2:	701a      	strb	r2, [r3, #0]
-    tcp_parseopt(npcb);
- 80099d4:	6978      	ldr	r0, [r7, #20]
- 80099d6:	f001 fd8f 	bl	800b4f8 <tcp_parseopt>
-    npcb->snd_wnd = tcphdr->wnd;
- 80099da:	4b23      	ldr	r3, [pc, #140]	; (8009a68 <tcp_listen_input+0x1e4>)
- 80099dc:	681b      	ldr	r3, [r3, #0]
- 80099de:	89db      	ldrh	r3, [r3, #14]
- 80099e0:	b29a      	uxth	r2, r3
- 80099e2:	697b      	ldr	r3, [r7, #20]
- 80099e4:	f8a3 2060 	strh.w	r2, [r3, #96]	; 0x60
-    npcb->snd_wnd_max = npcb->snd_wnd;
- 80099e8:	697b      	ldr	r3, [r7, #20]
- 80099ea:	f8b3 2060 	ldrh.w	r2, [r3, #96]	; 0x60
- 80099ee:	697b      	ldr	r3, [r7, #20]
- 80099f0:	f8a3 2062 	strh.w	r2, [r3, #98]	; 0x62
-    npcb->mss = tcp_eff_send_mss(npcb->mss, &npcb->local_ip, &npcb->remote_ip);
- 80099f4:	697b      	ldr	r3, [r7, #20]
- 80099f6:	8e5c      	ldrh	r4, [r3, #50]	; 0x32
- 80099f8:	697b      	ldr	r3, [r7, #20]
- 80099fa:	3304      	adds	r3, #4
- 80099fc:	4618      	mov	r0, r3
- 80099fe:	f005 fa43 	bl	800ee88 <ip4_route>
- 8009a02:	4601      	mov	r1, r0
- 8009a04:	697b      	ldr	r3, [r7, #20]
- 8009a06:	3304      	adds	r3, #4
- 8009a08:	461a      	mov	r2, r3
- 8009a0a:	4620      	mov	r0, r4
- 8009a0c:	f7ff fa2a 	bl	8008e64 <tcp_eff_send_mss_netif>
- 8009a10:	4603      	mov	r3, r0
- 8009a12:	461a      	mov	r2, r3
- 8009a14:	697b      	ldr	r3, [r7, #20]
- 8009a16:	865a      	strh	r2, [r3, #50]	; 0x32
-    rc = tcp_enqueue_flags(npcb, TCP_SYN | TCP_ACK);
- 8009a18:	2112      	movs	r1, #18
- 8009a1a:	6978      	ldr	r0, [r7, #20]
- 8009a1c:	f002 fcfc 	bl	800c418 <tcp_enqueue_flags>
- 8009a20:	4603      	mov	r3, r0
- 8009a22:	73fb      	strb	r3, [r7, #15]
-    if (rc != ERR_OK) {
- 8009a24:	f997 300f 	ldrsb.w	r3, [r7, #15]
- 8009a28:	2b00      	cmp	r3, #0
- 8009a2a:	d004      	beq.n	8009a36 <tcp_listen_input+0x1b2>
-      tcp_abandon(npcb, 0);
- 8009a2c:	2100      	movs	r1, #0
- 8009a2e:	6978      	ldr	r0, [r7, #20]
- 8009a30:	f7fd ff9a 	bl	8007968 <tcp_abandon>
-      return;
- 8009a34:	e006      	b.n	8009a44 <tcp_listen_input+0x1c0>
-    tcp_output(npcb);
- 8009a36:	6978      	ldr	r0, [r7, #20]
- 8009a38:	f002 fddc 	bl	800c5f4 <tcp_output>
-  return;
- 8009a3c:	e001      	b.n	8009a42 <tcp_listen_input+0x1be>
-    return;
- 8009a3e:	bf00      	nop
- 8009a40:	e000      	b.n	8009a44 <tcp_listen_input+0x1c0>
-  return;
- 8009a42:	bf00      	nop
-}
- 8009a44:	371c      	adds	r7, #28
- 8009a46:	46bd      	mov	sp, r7
- 8009a48:	bd90      	pop	{r4, r7, pc}
- 8009a4a:	bf00      	nop
- 8009a4c:	24007bb4 	.word	0x24007bb4
- 8009a50:	08013198 	.word	0x08013198
- 8009a54:	08013390 	.word	0x08013390
- 8009a58:	080131e4 	.word	0x080131e4
- 8009a5c:	24007bac 	.word	0x24007bac
- 8009a60:	24007bb2 	.word	0x24007bb2
- 8009a64:	24007ba8 	.word	0x24007ba8
- 8009a68:	24007b98 	.word	0x24007b98
- 8009a6c:	24004c20 	.word	0x24004c20
- 8009a70:	24004c24 	.word	0x24004c24
- 8009a74:	24004c10 	.word	0x24004c10
- 8009a78:	24007b78 	.word	0x24007b78
- 8009a7c:	24007b80 	.word	0x24007b80
-
-08009a80 <tcp_timewait_input>:
- * @note the segment which arrived is saved in global variables, therefore only the pcb
- *       involved is passed as a parameter to this function
- */
-static void
-tcp_timewait_input(struct tcp_pcb *pcb)
-{
- 8009a80:	b580      	push	{r7, lr}
- 8009a82:	b086      	sub	sp, #24
- 8009a84:	af04      	add	r7, sp, #16
- 8009a86:	6078      	str	r0, [r7, #4]
-  /* RFC 1337: in TIME_WAIT, ignore RST and ACK FINs + any 'acceptable' segments */
-  /* RFC 793 3.9 Event Processing - Segment Arrives:
-   * - first check sequence number - we skip that one in TIME_WAIT (always
-   *   acceptable since we only send ACKs)
-   * - second check the RST bit (... return) */
-  if (flags & TCP_RST) {
- 8009a88:	4b2f      	ldr	r3, [pc, #188]	; (8009b48 <tcp_timewait_input+0xc8>)
- 8009a8a:	781b      	ldrb	r3, [r3, #0]
- 8009a8c:	f003 0304 	and.w	r3, r3, #4
- 8009a90:	2b00      	cmp	r3, #0
- 8009a92:	d153      	bne.n	8009b3c <tcp_timewait_input+0xbc>
-    return;
-  }
-
-  LWIP_ASSERT("tcp_timewait_input: invalid pcb", pcb != NULL);
- 8009a94:	687b      	ldr	r3, [r7, #4]
- 8009a96:	2b00      	cmp	r3, #0
- 8009a98:	d106      	bne.n	8009aa8 <tcp_timewait_input+0x28>
- 8009a9a:	4b2c      	ldr	r3, [pc, #176]	; (8009b4c <tcp_timewait_input+0xcc>)
- 8009a9c:	f240 22ee 	movw	r2, #750	; 0x2ee
- 8009aa0:	492b      	ldr	r1, [pc, #172]	; (8009b50 <tcp_timewait_input+0xd0>)
- 8009aa2:	482c      	ldr	r0, [pc, #176]	; (8009b54 <tcp_timewait_input+0xd4>)
- 8009aa4:	f007 f890 	bl	8010bc8 <iprintf>
-
-  /* - fourth, check the SYN bit, */
-  if (flags & TCP_SYN) {
- 8009aa8:	4b27      	ldr	r3, [pc, #156]	; (8009b48 <tcp_timewait_input+0xc8>)
- 8009aaa:	781b      	ldrb	r3, [r3, #0]
- 8009aac:	f003 0302 	and.w	r3, r3, #2
- 8009ab0:	2b00      	cmp	r3, #0
- 8009ab2:	d02a      	beq.n	8009b0a <tcp_timewait_input+0x8a>
-    /* If an incoming segment is not acceptable, an acknowledgment
-       should be sent in reply */
-    if (TCP_SEQ_BETWEEN(seqno, pcb->rcv_nxt, pcb->rcv_nxt + pcb->rcv_wnd)) {
- 8009ab4:	4b28      	ldr	r3, [pc, #160]	; (8009b58 <tcp_timewait_input+0xd8>)
- 8009ab6:	681a      	ldr	r2, [r3, #0]
- 8009ab8:	687b      	ldr	r3, [r7, #4]
- 8009aba:	6a5b      	ldr	r3, [r3, #36]	; 0x24
- 8009abc:	1ad3      	subs	r3, r2, r3
- 8009abe:	2b00      	cmp	r3, #0
- 8009ac0:	db2d      	blt.n	8009b1e <tcp_timewait_input+0x9e>
- 8009ac2:	4b25      	ldr	r3, [pc, #148]	; (8009b58 <tcp_timewait_input+0xd8>)
- 8009ac4:	681a      	ldr	r2, [r3, #0]
- 8009ac6:	687b      	ldr	r3, [r7, #4]
- 8009ac8:	6a5b      	ldr	r3, [r3, #36]	; 0x24
- 8009aca:	6879      	ldr	r1, [r7, #4]
- 8009acc:	8d09      	ldrh	r1, [r1, #40]	; 0x28
- 8009ace:	440b      	add	r3, r1
- 8009ad0:	1ad3      	subs	r3, r2, r3
- 8009ad2:	2b00      	cmp	r3, #0
- 8009ad4:	dc23      	bgt.n	8009b1e <tcp_timewait_input+0x9e>
-      /* If the SYN is in the window it is an error, send a reset */
-      tcp_rst(pcb, ackno, seqno + tcplen, ip_current_dest_addr(),
- 8009ad6:	4b21      	ldr	r3, [pc, #132]	; (8009b5c <tcp_timewait_input+0xdc>)
- 8009ad8:	6819      	ldr	r1, [r3, #0]
- 8009ada:	4b21      	ldr	r3, [pc, #132]	; (8009b60 <tcp_timewait_input+0xe0>)
- 8009adc:	881b      	ldrh	r3, [r3, #0]
- 8009ade:	461a      	mov	r2, r3
- 8009ae0:	4b1d      	ldr	r3, [pc, #116]	; (8009b58 <tcp_timewait_input+0xd8>)
- 8009ae2:	681b      	ldr	r3, [r3, #0]
- 8009ae4:	18d0      	adds	r0, r2, r3
-              ip_current_src_addr(), tcphdr->dest, tcphdr->src);
- 8009ae6:	4b1f      	ldr	r3, [pc, #124]	; (8009b64 <tcp_timewait_input+0xe4>)
- 8009ae8:	681b      	ldr	r3, [r3, #0]
-      tcp_rst(pcb, ackno, seqno + tcplen, ip_current_dest_addr(),
- 8009aea:	885b      	ldrh	r3, [r3, #2]
- 8009aec:	b29b      	uxth	r3, r3
-              ip_current_src_addr(), tcphdr->dest, tcphdr->src);
- 8009aee:	4a1d      	ldr	r2, [pc, #116]	; (8009b64 <tcp_timewait_input+0xe4>)
- 8009af0:	6812      	ldr	r2, [r2, #0]
-      tcp_rst(pcb, ackno, seqno + tcplen, ip_current_dest_addr(),
- 8009af2:	8812      	ldrh	r2, [r2, #0]
- 8009af4:	b292      	uxth	r2, r2
- 8009af6:	9202      	str	r2, [sp, #8]
- 8009af8:	9301      	str	r3, [sp, #4]
- 8009afa:	4b1b      	ldr	r3, [pc, #108]	; (8009b68 <tcp_timewait_input+0xe8>)
- 8009afc:	9300      	str	r3, [sp, #0]
- 8009afe:	4b1b      	ldr	r3, [pc, #108]	; (8009b6c <tcp_timewait_input+0xec>)
- 8009b00:	4602      	mov	r2, r0
- 8009b02:	6878      	ldr	r0, [r7, #4]
- 8009b04:	f003 fb36 	bl	800d174 <tcp_rst>
-      return;
- 8009b08:	e01b      	b.n	8009b42 <tcp_timewait_input+0xc2>
-    }
-  } else if (flags & TCP_FIN) {
- 8009b0a:	4b0f      	ldr	r3, [pc, #60]	; (8009b48 <tcp_timewait_input+0xc8>)
- 8009b0c:	781b      	ldrb	r3, [r3, #0]
- 8009b0e:	f003 0301 	and.w	r3, r3, #1
- 8009b12:	2b00      	cmp	r3, #0
- 8009b14:	d003      	beq.n	8009b1e <tcp_timewait_input+0x9e>
-    /* - eighth, check the FIN bit: Remain in the TIME-WAIT state.
-         Restart the 2 MSL time-wait timeout.*/
-    pcb->tmr = tcp_ticks;
- 8009b16:	4b16      	ldr	r3, [pc, #88]	; (8009b70 <tcp_timewait_input+0xf0>)
- 8009b18:	681a      	ldr	r2, [r3, #0]
- 8009b1a:	687b      	ldr	r3, [r7, #4]
- 8009b1c:	621a      	str	r2, [r3, #32]
-  }
-
-  if ((tcplen > 0)) {
- 8009b1e:	4b10      	ldr	r3, [pc, #64]	; (8009b60 <tcp_timewait_input+0xe0>)
- 8009b20:	881b      	ldrh	r3, [r3, #0]
- 8009b22:	2b00      	cmp	r3, #0
- 8009b24:	d00c      	beq.n	8009b40 <tcp_timewait_input+0xc0>
-    /* Acknowledge data, FIN or out-of-window SYN */
-    tcp_ack_now(pcb);
- 8009b26:	687b      	ldr	r3, [r7, #4]
- 8009b28:	8b5b      	ldrh	r3, [r3, #26]
- 8009b2a:	f043 0302 	orr.w	r3, r3, #2
- 8009b2e:	b29a      	uxth	r2, r3
- 8009b30:	687b      	ldr	r3, [r7, #4]
- 8009b32:	835a      	strh	r2, [r3, #26]
-    tcp_output(pcb);
- 8009b34:	6878      	ldr	r0, [r7, #4]
- 8009b36:	f002 fd5d 	bl	800c5f4 <tcp_output>
-  }
-  return;
- 8009b3a:	e001      	b.n	8009b40 <tcp_timewait_input+0xc0>
-    return;
- 8009b3c:	bf00      	nop
- 8009b3e:	e000      	b.n	8009b42 <tcp_timewait_input+0xc2>
-  return;
- 8009b40:	bf00      	nop
-}
- 8009b42:	3708      	adds	r7, #8
- 8009b44:	46bd      	mov	sp, r7
- 8009b46:	bd80      	pop	{r7, pc}
- 8009b48:	24007bb4 	.word	0x24007bb4
- 8009b4c:	08013198 	.word	0x08013198
- 8009b50:	080133b0 	.word	0x080133b0
- 8009b54:	080131e4 	.word	0x080131e4
- 8009b58:	24007ba8 	.word	0x24007ba8
- 8009b5c:	24007bac 	.word	0x24007bac
- 8009b60:	24007bb2 	.word	0x24007bb2
- 8009b64:	24007b98 	.word	0x24007b98
- 8009b68:	24004c20 	.word	0x24004c20
- 8009b6c:	24004c24 	.word	0x24004c24
- 8009b70:	24007b6c 	.word	0x24007b6c
-
-08009b74 <tcp_process>:
- * @note the segment which arrived is saved in global variables, therefore only the pcb
- *       involved is passed as a parameter to this function
- */
-static err_t
-tcp_process(struct tcp_pcb *pcb)
-{
- 8009b74:	b590      	push	{r4, r7, lr}
- 8009b76:	b08d      	sub	sp, #52	; 0x34
- 8009b78:	af04      	add	r7, sp, #16
- 8009b7a:	6078      	str	r0, [r7, #4]
-  struct tcp_seg *rseg;
-  u8_t acceptable = 0;
- 8009b7c:	2300      	movs	r3, #0
- 8009b7e:	77fb      	strb	r3, [r7, #31]
-  err_t err;
-
-  err = ERR_OK;
- 8009b80:	2300      	movs	r3, #0
- 8009b82:	77bb      	strb	r3, [r7, #30]
-
-  LWIP_ASSERT("tcp_process: invalid pcb", pcb != NULL);
- 8009b84:	687b      	ldr	r3, [r7, #4]
- 8009b86:	2b00      	cmp	r3, #0
- 8009b88:	d106      	bne.n	8009b98 <tcp_process+0x24>
- 8009b8a:	4b9d      	ldr	r3, [pc, #628]	; (8009e00 <tcp_process+0x28c>)
- 8009b8c:	f44f 7247 	mov.w	r2, #796	; 0x31c
- 8009b90:	499c      	ldr	r1, [pc, #624]	; (8009e04 <tcp_process+0x290>)
- 8009b92:	489d      	ldr	r0, [pc, #628]	; (8009e08 <tcp_process+0x294>)
- 8009b94:	f007 f818 	bl	8010bc8 <iprintf>
-
-  /* Process incoming RST segments. */
-  if (flags & TCP_RST) {
- 8009b98:	4b9c      	ldr	r3, [pc, #624]	; (8009e0c <tcp_process+0x298>)
- 8009b9a:	781b      	ldrb	r3, [r3, #0]
- 8009b9c:	f003 0304 	and.w	r3, r3, #4
- 8009ba0:	2b00      	cmp	r3, #0
- 8009ba2:	d04e      	beq.n	8009c42 <tcp_process+0xce>
-    /* First, determine if the reset is acceptable. */
-    if (pcb->state == SYN_SENT) {
- 8009ba4:	687b      	ldr	r3, [r7, #4]
- 8009ba6:	7d1b      	ldrb	r3, [r3, #20]
- 8009ba8:	2b02      	cmp	r3, #2
- 8009baa:	d108      	bne.n	8009bbe <tcp_process+0x4a>
-      /* "In the SYN-SENT state (a RST received in response to an initial SYN),
-          the RST is acceptable if the ACK field acknowledges the SYN." */
-      if (ackno == pcb->snd_nxt) {
- 8009bac:	687b      	ldr	r3, [r7, #4]
- 8009bae:	6d1a      	ldr	r2, [r3, #80]	; 0x50
- 8009bb0:	4b97      	ldr	r3, [pc, #604]	; (8009e10 <tcp_process+0x29c>)
- 8009bb2:	681b      	ldr	r3, [r3, #0]
- 8009bb4:	429a      	cmp	r2, r3
- 8009bb6:	d123      	bne.n	8009c00 <tcp_process+0x8c>
-        acceptable = 1;
- 8009bb8:	2301      	movs	r3, #1
- 8009bba:	77fb      	strb	r3, [r7, #31]
- 8009bbc:	e020      	b.n	8009c00 <tcp_process+0x8c>
-      }
-    } else {
-      /* "In all states except SYN-SENT, all reset (RST) segments are validated
-          by checking their SEQ-fields." */
-      if (seqno == pcb->rcv_nxt) {
- 8009bbe:	687b      	ldr	r3, [r7, #4]
- 8009bc0:	6a5a      	ldr	r2, [r3, #36]	; 0x24
- 8009bc2:	4b94      	ldr	r3, [pc, #592]	; (8009e14 <tcp_process+0x2a0>)
- 8009bc4:	681b      	ldr	r3, [r3, #0]
- 8009bc6:	429a      	cmp	r2, r3
- 8009bc8:	d102      	bne.n	8009bd0 <tcp_process+0x5c>
-        acceptable = 1;
- 8009bca:	2301      	movs	r3, #1
- 8009bcc:	77fb      	strb	r3, [r7, #31]
- 8009bce:	e017      	b.n	8009c00 <tcp_process+0x8c>
-      } else  if (TCP_SEQ_BETWEEN(seqno, pcb->rcv_nxt,
- 8009bd0:	4b90      	ldr	r3, [pc, #576]	; (8009e14 <tcp_process+0x2a0>)
- 8009bd2:	681a      	ldr	r2, [r3, #0]
- 8009bd4:	687b      	ldr	r3, [r7, #4]
- 8009bd6:	6a5b      	ldr	r3, [r3, #36]	; 0x24
- 8009bd8:	1ad3      	subs	r3, r2, r3
- 8009bda:	2b00      	cmp	r3, #0
- 8009bdc:	db10      	blt.n	8009c00 <tcp_process+0x8c>
- 8009bde:	4b8d      	ldr	r3, [pc, #564]	; (8009e14 <tcp_process+0x2a0>)
- 8009be0:	681a      	ldr	r2, [r3, #0]
- 8009be2:	687b      	ldr	r3, [r7, #4]
- 8009be4:	6a5b      	ldr	r3, [r3, #36]	; 0x24
- 8009be6:	6879      	ldr	r1, [r7, #4]
- 8009be8:	8d09      	ldrh	r1, [r1, #40]	; 0x28
- 8009bea:	440b      	add	r3, r1
- 8009bec:	1ad3      	subs	r3, r2, r3
- 8009bee:	2b00      	cmp	r3, #0
- 8009bf0:	dc06      	bgt.n	8009c00 <tcp_process+0x8c>
-                                  pcb->rcv_nxt + pcb->rcv_wnd)) {
-        /* If the sequence number is inside the window, we send a challenge ACK
-           and wait for a re-send with matching sequence number.
-           This follows RFC 5961 section 3.2 and addresses CVE-2004-0230
-           (RST spoofing attack), which is present in RFC 793 RST handling. */
-        tcp_ack_now(pcb);
- 8009bf2:	687b      	ldr	r3, [r7, #4]
- 8009bf4:	8b5b      	ldrh	r3, [r3, #26]
- 8009bf6:	f043 0302 	orr.w	r3, r3, #2
- 8009bfa:	b29a      	uxth	r2, r3
- 8009bfc:	687b      	ldr	r3, [r7, #4]
- 8009bfe:	835a      	strh	r2, [r3, #26]
-      }
-    }
-
-    if (acceptable) {
- 8009c00:	7ffb      	ldrb	r3, [r7, #31]
- 8009c02:	2b00      	cmp	r3, #0
- 8009c04:	d01b      	beq.n	8009c3e <tcp_process+0xca>
-      LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_process: Connection RESET\n"));
-      LWIP_ASSERT("tcp_input: pcb->state != CLOSED", pcb->state != CLOSED);
- 8009c06:	687b      	ldr	r3, [r7, #4]
- 8009c08:	7d1b      	ldrb	r3, [r3, #20]
- 8009c0a:	2b00      	cmp	r3, #0
- 8009c0c:	d106      	bne.n	8009c1c <tcp_process+0xa8>
- 8009c0e:	4b7c      	ldr	r3, [pc, #496]	; (8009e00 <tcp_process+0x28c>)
- 8009c10:	f44f 724e 	mov.w	r2, #824	; 0x338
- 8009c14:	4980      	ldr	r1, [pc, #512]	; (8009e18 <tcp_process+0x2a4>)
- 8009c16:	487c      	ldr	r0, [pc, #496]	; (8009e08 <tcp_process+0x294>)
- 8009c18:	f006 ffd6 	bl	8010bc8 <iprintf>
-      recv_flags |= TF_RESET;
- 8009c1c:	4b7f      	ldr	r3, [pc, #508]	; (8009e1c <tcp_process+0x2a8>)
- 8009c1e:	781b      	ldrb	r3, [r3, #0]
- 8009c20:	f043 0308 	orr.w	r3, r3, #8
- 8009c24:	b2da      	uxtb	r2, r3
- 8009c26:	4b7d      	ldr	r3, [pc, #500]	; (8009e1c <tcp_process+0x2a8>)
- 8009c28:	701a      	strb	r2, [r3, #0]
-      tcp_clear_flags(pcb, TF_ACK_DELAY);
- 8009c2a:	687b      	ldr	r3, [r7, #4]
- 8009c2c:	8b5b      	ldrh	r3, [r3, #26]
- 8009c2e:	f023 0301 	bic.w	r3, r3, #1
- 8009c32:	b29a      	uxth	r2, r3
- 8009c34:	687b      	ldr	r3, [r7, #4]
- 8009c36:	835a      	strh	r2, [r3, #26]
-      return ERR_RST;
- 8009c38:	f06f 030d 	mvn.w	r3, #13
- 8009c3c:	e37a      	b.n	800a334 <tcp_process+0x7c0>
-    } else {
-      LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_process: unacceptable reset seqno %"U32_F" rcv_nxt %"U32_F"\n",
-                                    seqno, pcb->rcv_nxt));
-      LWIP_DEBUGF(TCP_DEBUG, ("tcp_process: unacceptable reset seqno %"U32_F" rcv_nxt %"U32_F"\n",
-                              seqno, pcb->rcv_nxt));
-      return ERR_OK;
- 8009c3e:	2300      	movs	r3, #0
- 8009c40:	e378      	b.n	800a334 <tcp_process+0x7c0>
-    }
-  }
-
-  if ((flags & TCP_SYN) && (pcb->state != SYN_SENT && pcb->state != SYN_RCVD)) {
- 8009c42:	4b72      	ldr	r3, [pc, #456]	; (8009e0c <tcp_process+0x298>)
- 8009c44:	781b      	ldrb	r3, [r3, #0]
- 8009c46:	f003 0302 	and.w	r3, r3, #2
- 8009c4a:	2b00      	cmp	r3, #0
- 8009c4c:	d010      	beq.n	8009c70 <tcp_process+0xfc>
- 8009c4e:	687b      	ldr	r3, [r7, #4]
- 8009c50:	7d1b      	ldrb	r3, [r3, #20]
- 8009c52:	2b02      	cmp	r3, #2
- 8009c54:	d00c      	beq.n	8009c70 <tcp_process+0xfc>
- 8009c56:	687b      	ldr	r3, [r7, #4]
- 8009c58:	7d1b      	ldrb	r3, [r3, #20]
- 8009c5a:	2b03      	cmp	r3, #3
- 8009c5c:	d008      	beq.n	8009c70 <tcp_process+0xfc>
-    /* Cope with new connection attempt after remote end crashed */
-    tcp_ack_now(pcb);
- 8009c5e:	687b      	ldr	r3, [r7, #4]
- 8009c60:	8b5b      	ldrh	r3, [r3, #26]
- 8009c62:	f043 0302 	orr.w	r3, r3, #2
- 8009c66:	b29a      	uxth	r2, r3
- 8009c68:	687b      	ldr	r3, [r7, #4]
- 8009c6a:	835a      	strh	r2, [r3, #26]
-    return ERR_OK;
- 8009c6c:	2300      	movs	r3, #0
- 8009c6e:	e361      	b.n	800a334 <tcp_process+0x7c0>
-  }
-
-  if ((pcb->flags & TF_RXCLOSED) == 0) {
- 8009c70:	687b      	ldr	r3, [r7, #4]
- 8009c72:	8b5b      	ldrh	r3, [r3, #26]
- 8009c74:	f003 0310 	and.w	r3, r3, #16
- 8009c78:	2b00      	cmp	r3, #0
- 8009c7a:	d103      	bne.n	8009c84 <tcp_process+0x110>
-    /* Update the PCB (in)activity timer unless rx is closed (see tcp_shutdown) */
-    pcb->tmr = tcp_ticks;
- 8009c7c:	4b68      	ldr	r3, [pc, #416]	; (8009e20 <tcp_process+0x2ac>)
- 8009c7e:	681a      	ldr	r2, [r3, #0]
- 8009c80:	687b      	ldr	r3, [r7, #4]
- 8009c82:	621a      	str	r2, [r3, #32]
-  }
-  pcb->keep_cnt_sent = 0;
- 8009c84:	687b      	ldr	r3, [r7, #4]
- 8009c86:	2200      	movs	r2, #0
- 8009c88:	f883 209b 	strb.w	r2, [r3, #155]	; 0x9b
-  pcb->persist_probe = 0;
- 8009c8c:	687b      	ldr	r3, [r7, #4]
- 8009c8e:	2200      	movs	r2, #0
- 8009c90:	f883 209a 	strb.w	r2, [r3, #154]	; 0x9a
-
-  tcp_parseopt(pcb);
- 8009c94:	6878      	ldr	r0, [r7, #4]
- 8009c96:	f001 fc2f 	bl	800b4f8 <tcp_parseopt>
-
-  /* Do different things depending on the TCP state. */
-  switch (pcb->state) {
- 8009c9a:	687b      	ldr	r3, [r7, #4]
- 8009c9c:	7d1b      	ldrb	r3, [r3, #20]
- 8009c9e:	3b02      	subs	r3, #2
- 8009ca0:	2b07      	cmp	r3, #7
- 8009ca2:	f200 8337 	bhi.w	800a314 <tcp_process+0x7a0>
- 8009ca6:	a201      	add	r2, pc, #4	; (adr r2, 8009cac <tcp_process+0x138>)
- 8009ca8:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
- 8009cac:	08009ccd 	.word	0x08009ccd
- 8009cb0:	08009efd 	.word	0x08009efd
- 8009cb4:	0800a075 	.word	0x0800a075
- 8009cb8:	0800a09f 	.word	0x0800a09f
- 8009cbc:	0800a1c3 	.word	0x0800a1c3
- 8009cc0:	0800a075 	.word	0x0800a075
- 8009cc4:	0800a24f 	.word	0x0800a24f
- 8009cc8:	0800a2df 	.word	0x0800a2df
-    case SYN_SENT:
-      LWIP_DEBUGF(TCP_INPUT_DEBUG, ("SYN-SENT: ackno %"U32_F" pcb->snd_nxt %"U32_F" unacked %"U32_F"\n", ackno,
-                                    pcb->snd_nxt, lwip_ntohl(pcb->unacked->tcphdr->seqno)));
-      /* received SYN ACK with expected sequence number? */
-      if ((flags & TCP_ACK) && (flags & TCP_SYN)
- 8009ccc:	4b4f      	ldr	r3, [pc, #316]	; (8009e0c <tcp_process+0x298>)
- 8009cce:	781b      	ldrb	r3, [r3, #0]
- 8009cd0:	f003 0310 	and.w	r3, r3, #16
- 8009cd4:	2b00      	cmp	r3, #0
- 8009cd6:	f000 80e4 	beq.w	8009ea2 <tcp_process+0x32e>
- 8009cda:	4b4c      	ldr	r3, [pc, #304]	; (8009e0c <tcp_process+0x298>)
- 8009cdc:	781b      	ldrb	r3, [r3, #0]
- 8009cde:	f003 0302 	and.w	r3, r3, #2
- 8009ce2:	2b00      	cmp	r3, #0
- 8009ce4:	f000 80dd 	beq.w	8009ea2 <tcp_process+0x32e>
-          && (ackno == pcb->lastack + 1)) {
- 8009ce8:	687b      	ldr	r3, [r7, #4]
- 8009cea:	6c5b      	ldr	r3, [r3, #68]	; 0x44
- 8009cec:	1c5a      	adds	r2, r3, #1
- 8009cee:	4b48      	ldr	r3, [pc, #288]	; (8009e10 <tcp_process+0x29c>)
- 8009cf0:	681b      	ldr	r3, [r3, #0]
- 8009cf2:	429a      	cmp	r2, r3
- 8009cf4:	f040 80d5 	bne.w	8009ea2 <tcp_process+0x32e>
-        pcb->rcv_nxt = seqno + 1;
- 8009cf8:	4b46      	ldr	r3, [pc, #280]	; (8009e14 <tcp_process+0x2a0>)
- 8009cfa:	681b      	ldr	r3, [r3, #0]
- 8009cfc:	1c5a      	adds	r2, r3, #1
- 8009cfe:	687b      	ldr	r3, [r7, #4]
- 8009d00:	625a      	str	r2, [r3, #36]	; 0x24
-        pcb->rcv_ann_right_edge = pcb->rcv_nxt;
- 8009d02:	687b      	ldr	r3, [r7, #4]
- 8009d04:	6a5a      	ldr	r2, [r3, #36]	; 0x24
- 8009d06:	687b      	ldr	r3, [r7, #4]
- 8009d08:	62da      	str	r2, [r3, #44]	; 0x2c
-        pcb->lastack = ackno;
- 8009d0a:	4b41      	ldr	r3, [pc, #260]	; (8009e10 <tcp_process+0x29c>)
- 8009d0c:	681a      	ldr	r2, [r3, #0]
- 8009d0e:	687b      	ldr	r3, [r7, #4]
- 8009d10:	645a      	str	r2, [r3, #68]	; 0x44
-        pcb->snd_wnd = tcphdr->wnd;
- 8009d12:	4b44      	ldr	r3, [pc, #272]	; (8009e24 <tcp_process+0x2b0>)
- 8009d14:	681b      	ldr	r3, [r3, #0]
- 8009d16:	89db      	ldrh	r3, [r3, #14]
- 8009d18:	b29a      	uxth	r2, r3
- 8009d1a:	687b      	ldr	r3, [r7, #4]
- 8009d1c:	f8a3 2060 	strh.w	r2, [r3, #96]	; 0x60
-        pcb->snd_wnd_max = pcb->snd_wnd;
- 8009d20:	687b      	ldr	r3, [r7, #4]
- 8009d22:	f8b3 2060 	ldrh.w	r2, [r3, #96]	; 0x60
- 8009d26:	687b      	ldr	r3, [r7, #4]
- 8009d28:	f8a3 2062 	strh.w	r2, [r3, #98]	; 0x62
-        pcb->snd_wl1 = seqno - 1; /* initialise to seqno - 1 to force window update */
- 8009d2c:	4b39      	ldr	r3, [pc, #228]	; (8009e14 <tcp_process+0x2a0>)
- 8009d2e:	681b      	ldr	r3, [r3, #0]
- 8009d30:	1e5a      	subs	r2, r3, #1
- 8009d32:	687b      	ldr	r3, [r7, #4]
- 8009d34:	655a      	str	r2, [r3, #84]	; 0x54
-        pcb->state = ESTABLISHED;
- 8009d36:	687b      	ldr	r3, [r7, #4]
- 8009d38:	2204      	movs	r2, #4
- 8009d3a:	751a      	strb	r2, [r3, #20]
-
-#if TCP_CALCULATE_EFF_SEND_MSS
-        pcb->mss = tcp_eff_send_mss(pcb->mss, &pcb->local_ip, &pcb->remote_ip);
- 8009d3c:	687b      	ldr	r3, [r7, #4]
- 8009d3e:	8e5c      	ldrh	r4, [r3, #50]	; 0x32
- 8009d40:	687b      	ldr	r3, [r7, #4]
- 8009d42:	3304      	adds	r3, #4
- 8009d44:	4618      	mov	r0, r3
- 8009d46:	f005 f89f 	bl	800ee88 <ip4_route>
- 8009d4a:	4601      	mov	r1, r0
- 8009d4c:	687b      	ldr	r3, [r7, #4]
- 8009d4e:	3304      	adds	r3, #4
- 8009d50:	461a      	mov	r2, r3
- 8009d52:	4620      	mov	r0, r4
- 8009d54:	f7ff f886 	bl	8008e64 <tcp_eff_send_mss_netif>
- 8009d58:	4603      	mov	r3, r0
- 8009d5a:	461a      	mov	r2, r3
- 8009d5c:	687b      	ldr	r3, [r7, #4]
- 8009d5e:	865a      	strh	r2, [r3, #50]	; 0x32
-#endif /* TCP_CALCULATE_EFF_SEND_MSS */
-
-        pcb->cwnd = LWIP_TCP_CALC_INITIAL_CWND(pcb->mss);
- 8009d60:	687b      	ldr	r3, [r7, #4]
- 8009d62:	8e5b      	ldrh	r3, [r3, #50]	; 0x32
- 8009d64:	009a      	lsls	r2, r3, #2
- 8009d66:	687b      	ldr	r3, [r7, #4]
- 8009d68:	8e5b      	ldrh	r3, [r3, #50]	; 0x32
- 8009d6a:	005b      	lsls	r3, r3, #1
- 8009d6c:	f241 111c 	movw	r1, #4380	; 0x111c
- 8009d70:	428b      	cmp	r3, r1
- 8009d72:	bf38      	it	cc
- 8009d74:	460b      	movcc	r3, r1
- 8009d76:	429a      	cmp	r2, r3
- 8009d78:	d204      	bcs.n	8009d84 <tcp_process+0x210>
- 8009d7a:	687b      	ldr	r3, [r7, #4]
- 8009d7c:	8e5b      	ldrh	r3, [r3, #50]	; 0x32
- 8009d7e:	009b      	lsls	r3, r3, #2
- 8009d80:	b29b      	uxth	r3, r3
- 8009d82:	e00d      	b.n	8009da0 <tcp_process+0x22c>
- 8009d84:	687b      	ldr	r3, [r7, #4]
- 8009d86:	8e5b      	ldrh	r3, [r3, #50]	; 0x32
- 8009d88:	005b      	lsls	r3, r3, #1
- 8009d8a:	f241 121c 	movw	r2, #4380	; 0x111c
- 8009d8e:	4293      	cmp	r3, r2
- 8009d90:	d904      	bls.n	8009d9c <tcp_process+0x228>
- 8009d92:	687b      	ldr	r3, [r7, #4]
- 8009d94:	8e5b      	ldrh	r3, [r3, #50]	; 0x32
- 8009d96:	005b      	lsls	r3, r3, #1
- 8009d98:	b29b      	uxth	r3, r3
- 8009d9a:	e001      	b.n	8009da0 <tcp_process+0x22c>
- 8009d9c:	f241 131c 	movw	r3, #4380	; 0x111c
- 8009da0:	687a      	ldr	r2, [r7, #4]
- 8009da2:	f8a2 3048 	strh.w	r3, [r2, #72]	; 0x48
-        LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_process (SENT): cwnd %"TCPWNDSIZE_F
-                                     " ssthresh %"TCPWNDSIZE_F"\n",
-                                     pcb->cwnd, pcb->ssthresh));
-        LWIP_ASSERT("pcb->snd_queuelen > 0", (pcb->snd_queuelen > 0));
- 8009da6:	687b      	ldr	r3, [r7, #4]
- 8009da8:	f8b3 3066 	ldrh.w	r3, [r3, #102]	; 0x66
- 8009dac:	2b00      	cmp	r3, #0
- 8009dae:	d106      	bne.n	8009dbe <tcp_process+0x24a>
- 8009db0:	4b13      	ldr	r3, [pc, #76]	; (8009e00 <tcp_process+0x28c>)
- 8009db2:	f44f 725b 	mov.w	r2, #876	; 0x36c
- 8009db6:	491c      	ldr	r1, [pc, #112]	; (8009e28 <tcp_process+0x2b4>)
- 8009db8:	4813      	ldr	r0, [pc, #76]	; (8009e08 <tcp_process+0x294>)
- 8009dba:	f006 ff05 	bl	8010bc8 <iprintf>
-        --pcb->snd_queuelen;
- 8009dbe:	687b      	ldr	r3, [r7, #4]
- 8009dc0:	f8b3 3066 	ldrh.w	r3, [r3, #102]	; 0x66
- 8009dc4:	3b01      	subs	r3, #1
- 8009dc6:	b29a      	uxth	r2, r3
- 8009dc8:	687b      	ldr	r3, [r7, #4]
- 8009dca:	f8a3 2066 	strh.w	r2, [r3, #102]	; 0x66
-        LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_process: SYN-SENT --queuelen %"TCPWNDSIZE_F"\n", (tcpwnd_size_t)pcb->snd_queuelen));
-        rseg = pcb->unacked;
- 8009dce:	687b      	ldr	r3, [r7, #4]
- 8009dd0:	6f1b      	ldr	r3, [r3, #112]	; 0x70
- 8009dd2:	617b      	str	r3, [r7, #20]
-        if (rseg == NULL) {
- 8009dd4:	697b      	ldr	r3, [r7, #20]
- 8009dd6:	2b00      	cmp	r3, #0
- 8009dd8:	d12a      	bne.n	8009e30 <tcp_process+0x2bc>
-          /* might happen if tcp_output fails in tcp_rexmit_rto()
-             in which case the segment is on the unsent list */
-          rseg = pcb->unsent;
- 8009dda:	687b      	ldr	r3, [r7, #4]
- 8009ddc:	6edb      	ldr	r3, [r3, #108]	; 0x6c
- 8009dde:	617b      	str	r3, [r7, #20]
-          LWIP_ASSERT("no segment to free", rseg != NULL);
- 8009de0:	697b      	ldr	r3, [r7, #20]
- 8009de2:	2b00      	cmp	r3, #0
- 8009de4:	d106      	bne.n	8009df4 <tcp_process+0x280>
- 8009de6:	4b06      	ldr	r3, [pc, #24]	; (8009e00 <tcp_process+0x28c>)
- 8009de8:	f44f 725d 	mov.w	r2, #884	; 0x374
- 8009dec:	490f      	ldr	r1, [pc, #60]	; (8009e2c <tcp_process+0x2b8>)
- 8009dee:	4806      	ldr	r0, [pc, #24]	; (8009e08 <tcp_process+0x294>)
- 8009df0:	f006 feea 	bl	8010bc8 <iprintf>
-          pcb->unsent = rseg->next;
- 8009df4:	697b      	ldr	r3, [r7, #20]
- 8009df6:	681a      	ldr	r2, [r3, #0]
- 8009df8:	687b      	ldr	r3, [r7, #4]
- 8009dfa:	66da      	str	r2, [r3, #108]	; 0x6c
- 8009dfc:	e01c      	b.n	8009e38 <tcp_process+0x2c4>
- 8009dfe:	bf00      	nop
- 8009e00:	08013198 	.word	0x08013198
- 8009e04:	080133d0 	.word	0x080133d0
- 8009e08:	080131e4 	.word	0x080131e4
- 8009e0c:	24007bb4 	.word	0x24007bb4
- 8009e10:	24007bac 	.word	0x24007bac
- 8009e14:	24007ba8 	.word	0x24007ba8
- 8009e18:	080133ec 	.word	0x080133ec
- 8009e1c:	24007bb5 	.word	0x24007bb5
- 8009e20:	24007b6c 	.word	0x24007b6c
- 8009e24:	24007b98 	.word	0x24007b98
- 8009e28:	0801340c 	.word	0x0801340c
- 8009e2c:	08013424 	.word	0x08013424
-        } else {
-          pcb->unacked = rseg->next;
- 8009e30:	697b      	ldr	r3, [r7, #20]
- 8009e32:	681a      	ldr	r2, [r3, #0]
- 8009e34:	687b      	ldr	r3, [r7, #4]
- 8009e36:	671a      	str	r2, [r3, #112]	; 0x70
-        }
-        tcp_seg_free(rseg);
- 8009e38:	6978      	ldr	r0, [r7, #20]
- 8009e3a:	f7fe fc9c 	bl	8008776 <tcp_seg_free>
-
-        /* If there's nothing left to acknowledge, stop the retransmit
-           timer, otherwise reset it to start again */
-        if (pcb->unacked == NULL) {
- 8009e3e:	687b      	ldr	r3, [r7, #4]
- 8009e40:	6f1b      	ldr	r3, [r3, #112]	; 0x70
- 8009e42:	2b00      	cmp	r3, #0
- 8009e44:	d104      	bne.n	8009e50 <tcp_process+0x2dc>
-          pcb->rtime = -1;
- 8009e46:	687b      	ldr	r3, [r7, #4]
- 8009e48:	f64f 72ff 	movw	r2, #65535	; 0xffff
- 8009e4c:	861a      	strh	r2, [r3, #48]	; 0x30
- 8009e4e:	e006      	b.n	8009e5e <tcp_process+0x2ea>
-        } else {
-          pcb->rtime = 0;
- 8009e50:	687b      	ldr	r3, [r7, #4]
- 8009e52:	2200      	movs	r2, #0
- 8009e54:	861a      	strh	r2, [r3, #48]	; 0x30
-          pcb->nrtx = 0;
- 8009e56:	687b      	ldr	r3, [r7, #4]
- 8009e58:	2200      	movs	r2, #0
- 8009e5a:	f883 2042 	strb.w	r2, [r3, #66]	; 0x42
-        }
-
-        /* Call the user specified function to call when successfully
-         * connected. */
-        TCP_EVENT_CONNECTED(pcb, ERR_OK, err);
- 8009e5e:	687b      	ldr	r3, [r7, #4]
- 8009e60:	f8d3 3088 	ldr.w	r3, [r3, #136]	; 0x88
- 8009e64:	2b00      	cmp	r3, #0
- 8009e66:	d00a      	beq.n	8009e7e <tcp_process+0x30a>
- 8009e68:	687b      	ldr	r3, [r7, #4]
- 8009e6a:	f8d3 3088 	ldr.w	r3, [r3, #136]	; 0x88
- 8009e6e:	687a      	ldr	r2, [r7, #4]
- 8009e70:	6910      	ldr	r0, [r2, #16]
- 8009e72:	2200      	movs	r2, #0
- 8009e74:	6879      	ldr	r1, [r7, #4]
- 8009e76:	4798      	blx	r3
- 8009e78:	4603      	mov	r3, r0
- 8009e7a:	77bb      	strb	r3, [r7, #30]
- 8009e7c:	e001      	b.n	8009e82 <tcp_process+0x30e>
- 8009e7e:	2300      	movs	r3, #0
- 8009e80:	77bb      	strb	r3, [r7, #30]
-        if (err == ERR_ABRT) {
- 8009e82:	f997 301e 	ldrsb.w	r3, [r7, #30]
- 8009e86:	f113 0f0d 	cmn.w	r3, #13
- 8009e8a:	d102      	bne.n	8009e92 <tcp_process+0x31e>
-          return ERR_ABRT;
- 8009e8c:	f06f 030c 	mvn.w	r3, #12
- 8009e90:	e250      	b.n	800a334 <tcp_process+0x7c0>
-        }
-        tcp_ack_now(pcb);
- 8009e92:	687b      	ldr	r3, [r7, #4]
- 8009e94:	8b5b      	ldrh	r3, [r3, #26]
- 8009e96:	f043 0302 	orr.w	r3, r3, #2
- 8009e9a:	b29a      	uxth	r2, r3
- 8009e9c:	687b      	ldr	r3, [r7, #4]
- 8009e9e:	835a      	strh	r2, [r3, #26]
-        if (pcb->nrtx < TCP_SYNMAXRTX) {
-          pcb->rtime = 0;
-          tcp_rexmit_rto(pcb);
-        }
-      }
-      break;
- 8009ea0:	e23a      	b.n	800a318 <tcp_process+0x7a4>
-      else if (flags & TCP_ACK) {
- 8009ea2:	4b98      	ldr	r3, [pc, #608]	; (800a104 <tcp_process+0x590>)
- 8009ea4:	781b      	ldrb	r3, [r3, #0]
- 8009ea6:	f003 0310 	and.w	r3, r3, #16
- 8009eaa:	2b00      	cmp	r3, #0
- 8009eac:	f000 8234 	beq.w	800a318 <tcp_process+0x7a4>
-        tcp_rst(pcb, ackno, seqno + tcplen, ip_current_dest_addr(),
- 8009eb0:	4b95      	ldr	r3, [pc, #596]	; (800a108 <tcp_process+0x594>)
- 8009eb2:	6819      	ldr	r1, [r3, #0]
- 8009eb4:	4b95      	ldr	r3, [pc, #596]	; (800a10c <tcp_process+0x598>)
- 8009eb6:	881b      	ldrh	r3, [r3, #0]
- 8009eb8:	461a      	mov	r2, r3
- 8009eba:	4b95      	ldr	r3, [pc, #596]	; (800a110 <tcp_process+0x59c>)
- 8009ebc:	681b      	ldr	r3, [r3, #0]
- 8009ebe:	18d0      	adds	r0, r2, r3
-                ip_current_src_addr(), tcphdr->dest, tcphdr->src);
- 8009ec0:	4b94      	ldr	r3, [pc, #592]	; (800a114 <tcp_process+0x5a0>)
- 8009ec2:	681b      	ldr	r3, [r3, #0]
-        tcp_rst(pcb, ackno, seqno + tcplen, ip_current_dest_addr(),
- 8009ec4:	885b      	ldrh	r3, [r3, #2]
- 8009ec6:	b29b      	uxth	r3, r3
-                ip_current_src_addr(), tcphdr->dest, tcphdr->src);
- 8009ec8:	4a92      	ldr	r2, [pc, #584]	; (800a114 <tcp_process+0x5a0>)
- 8009eca:	6812      	ldr	r2, [r2, #0]
-        tcp_rst(pcb, ackno, seqno + tcplen, ip_current_dest_addr(),
- 8009ecc:	8812      	ldrh	r2, [r2, #0]
- 8009ece:	b292      	uxth	r2, r2
- 8009ed0:	9202      	str	r2, [sp, #8]
- 8009ed2:	9301      	str	r3, [sp, #4]
- 8009ed4:	4b90      	ldr	r3, [pc, #576]	; (800a118 <tcp_process+0x5a4>)
- 8009ed6:	9300      	str	r3, [sp, #0]
- 8009ed8:	4b90      	ldr	r3, [pc, #576]	; (800a11c <tcp_process+0x5a8>)
- 8009eda:	4602      	mov	r2, r0
- 8009edc:	6878      	ldr	r0, [r7, #4]
- 8009ede:	f003 f949 	bl	800d174 <tcp_rst>
-        if (pcb->nrtx < TCP_SYNMAXRTX) {
- 8009ee2:	687b      	ldr	r3, [r7, #4]
- 8009ee4:	f893 3042 	ldrb.w	r3, [r3, #66]	; 0x42
- 8009ee8:	2b05      	cmp	r3, #5
- 8009eea:	f200 8215 	bhi.w	800a318 <tcp_process+0x7a4>
-          pcb->rtime = 0;
- 8009eee:	687b      	ldr	r3, [r7, #4]
- 8009ef0:	2200      	movs	r2, #0
- 8009ef2:	861a      	strh	r2, [r3, #48]	; 0x30
-          tcp_rexmit_rto(pcb);
- 8009ef4:	6878      	ldr	r0, [r7, #4]
- 8009ef6:	f002 ff15 	bl	800cd24 <tcp_rexmit_rto>
-      break;
- 8009efa:	e20d      	b.n	800a318 <tcp_process+0x7a4>
-    case SYN_RCVD:
-      if (flags & TCP_ACK) {
- 8009efc:	4b81      	ldr	r3, [pc, #516]	; (800a104 <tcp_process+0x590>)
- 8009efe:	781b      	ldrb	r3, [r3, #0]
- 8009f00:	f003 0310 	and.w	r3, r3, #16
- 8009f04:	2b00      	cmp	r3, #0
- 8009f06:	f000 80a1 	beq.w	800a04c <tcp_process+0x4d8>
-        /* expected ACK number? */
-        if (TCP_SEQ_BETWEEN(ackno, pcb->lastack + 1, pcb->snd_nxt)) {
- 8009f0a:	4b7f      	ldr	r3, [pc, #508]	; (800a108 <tcp_process+0x594>)
- 8009f0c:	681a      	ldr	r2, [r3, #0]
- 8009f0e:	687b      	ldr	r3, [r7, #4]
- 8009f10:	6c5b      	ldr	r3, [r3, #68]	; 0x44
- 8009f12:	1ad3      	subs	r3, r2, r3
- 8009f14:	3b01      	subs	r3, #1
- 8009f16:	2b00      	cmp	r3, #0
- 8009f18:	db7e      	blt.n	800a018 <tcp_process+0x4a4>
- 8009f1a:	4b7b      	ldr	r3, [pc, #492]	; (800a108 <tcp_process+0x594>)
- 8009f1c:	681a      	ldr	r2, [r3, #0]
- 8009f1e:	687b      	ldr	r3, [r7, #4]
- 8009f20:	6d1b      	ldr	r3, [r3, #80]	; 0x50
- 8009f22:	1ad3      	subs	r3, r2, r3
- 8009f24:	2b00      	cmp	r3, #0
- 8009f26:	dc77      	bgt.n	800a018 <tcp_process+0x4a4>
-          pcb->state = ESTABLISHED;
- 8009f28:	687b      	ldr	r3, [r7, #4]
- 8009f2a:	2204      	movs	r2, #4
- 8009f2c:	751a      	strb	r2, [r3, #20]
-          LWIP_DEBUGF(TCP_DEBUG, ("TCP connection established %"U16_F" -> %"U16_F".\n", inseg.tcphdr->src, inseg.tcphdr->dest));
-#if LWIP_CALLBACK_API || TCP_LISTEN_BACKLOG
-          if (pcb->listener == NULL) {
- 8009f2e:	687b      	ldr	r3, [r7, #4]
- 8009f30:	6fdb      	ldr	r3, [r3, #124]	; 0x7c
- 8009f32:	2b00      	cmp	r3, #0
- 8009f34:	d102      	bne.n	8009f3c <tcp_process+0x3c8>
-            /* listen pcb might be closed by now */
-            err = ERR_VAL;
- 8009f36:	23fa      	movs	r3, #250	; 0xfa
- 8009f38:	77bb      	strb	r3, [r7, #30]
- 8009f3a:	e01d      	b.n	8009f78 <tcp_process+0x404>
-          } else
-#endif /* LWIP_CALLBACK_API || TCP_LISTEN_BACKLOG */
-          {
-#if LWIP_CALLBACK_API
-            LWIP_ASSERT("pcb->listener->accept != NULL", pcb->listener->accept != NULL);
- 8009f3c:	687b      	ldr	r3, [r7, #4]
- 8009f3e:	6fdb      	ldr	r3, [r3, #124]	; 0x7c
- 8009f40:	699b      	ldr	r3, [r3, #24]
- 8009f42:	2b00      	cmp	r3, #0
- 8009f44:	d106      	bne.n	8009f54 <tcp_process+0x3e0>
- 8009f46:	4b76      	ldr	r3, [pc, #472]	; (800a120 <tcp_process+0x5ac>)
- 8009f48:	f44f 726a 	mov.w	r2, #936	; 0x3a8
- 8009f4c:	4975      	ldr	r1, [pc, #468]	; (800a124 <tcp_process+0x5b0>)
- 8009f4e:	4876      	ldr	r0, [pc, #472]	; (800a128 <tcp_process+0x5b4>)
- 8009f50:	f006 fe3a 	bl	8010bc8 <iprintf>
-#endif
-            tcp_backlog_accepted(pcb);
-            /* Call the accept function. */
-            TCP_EVENT_ACCEPT(pcb->listener, pcb, pcb->callback_arg, ERR_OK, err);
- 8009f54:	687b      	ldr	r3, [r7, #4]
- 8009f56:	6fdb      	ldr	r3, [r3, #124]	; 0x7c
- 8009f58:	699b      	ldr	r3, [r3, #24]
- 8009f5a:	2b00      	cmp	r3, #0
- 8009f5c:	d00a      	beq.n	8009f74 <tcp_process+0x400>
- 8009f5e:	687b      	ldr	r3, [r7, #4]
- 8009f60:	6fdb      	ldr	r3, [r3, #124]	; 0x7c
- 8009f62:	699b      	ldr	r3, [r3, #24]
- 8009f64:	687a      	ldr	r2, [r7, #4]
- 8009f66:	6910      	ldr	r0, [r2, #16]
- 8009f68:	2200      	movs	r2, #0
- 8009f6a:	6879      	ldr	r1, [r7, #4]
- 8009f6c:	4798      	blx	r3
- 8009f6e:	4603      	mov	r3, r0
- 8009f70:	77bb      	strb	r3, [r7, #30]
- 8009f72:	e001      	b.n	8009f78 <tcp_process+0x404>
- 8009f74:	23f0      	movs	r3, #240	; 0xf0
- 8009f76:	77bb      	strb	r3, [r7, #30]
-          }
-          if (err != ERR_OK) {
- 8009f78:	f997 301e 	ldrsb.w	r3, [r7, #30]
- 8009f7c:	2b00      	cmp	r3, #0
- 8009f7e:	d00a      	beq.n	8009f96 <tcp_process+0x422>
-            /* If the accept function returns with an error, we abort
-             * the connection. */
-            /* Already aborted? */
-            if (err != ERR_ABRT) {
- 8009f80:	f997 301e 	ldrsb.w	r3, [r7, #30]
- 8009f84:	f113 0f0d 	cmn.w	r3, #13
- 8009f88:	d002      	beq.n	8009f90 <tcp_process+0x41c>
-              tcp_abort(pcb);
- 8009f8a:	6878      	ldr	r0, [r7, #4]
- 8009f8c:	f7fd fdaa 	bl	8007ae4 <tcp_abort>
-            }
-            return ERR_ABRT;
- 8009f90:	f06f 030c 	mvn.w	r3, #12
- 8009f94:	e1ce      	b.n	800a334 <tcp_process+0x7c0>
-          }
-          /* If there was any data contained within this ACK,
-           * we'd better pass it on to the application as well. */
-          tcp_receive(pcb);
- 8009f96:	6878      	ldr	r0, [r7, #4]
- 8009f98:	f000 fae0 	bl	800a55c <tcp_receive>
-
-          /* Prevent ACK for SYN to generate a sent event */
-          if (recv_acked != 0) {
- 8009f9c:	4b63      	ldr	r3, [pc, #396]	; (800a12c <tcp_process+0x5b8>)
- 8009f9e:	881b      	ldrh	r3, [r3, #0]
- 8009fa0:	2b00      	cmp	r3, #0
- 8009fa2:	d005      	beq.n	8009fb0 <tcp_process+0x43c>
-            recv_acked--;
- 8009fa4:	4b61      	ldr	r3, [pc, #388]	; (800a12c <tcp_process+0x5b8>)
- 8009fa6:	881b      	ldrh	r3, [r3, #0]
- 8009fa8:	3b01      	subs	r3, #1
- 8009faa:	b29a      	uxth	r2, r3
- 8009fac:	4b5f      	ldr	r3, [pc, #380]	; (800a12c <tcp_process+0x5b8>)
- 8009fae:	801a      	strh	r2, [r3, #0]
-          }
-
-          pcb->cwnd = LWIP_TCP_CALC_INITIAL_CWND(pcb->mss);
- 8009fb0:	687b      	ldr	r3, [r7, #4]
- 8009fb2:	8e5b      	ldrh	r3, [r3, #50]	; 0x32
- 8009fb4:	009a      	lsls	r2, r3, #2
- 8009fb6:	687b      	ldr	r3, [r7, #4]
- 8009fb8:	8e5b      	ldrh	r3, [r3, #50]	; 0x32
- 8009fba:	005b      	lsls	r3, r3, #1
- 8009fbc:	f241 111c 	movw	r1, #4380	; 0x111c
- 8009fc0:	428b      	cmp	r3, r1
- 8009fc2:	bf38      	it	cc
- 8009fc4:	460b      	movcc	r3, r1
- 8009fc6:	429a      	cmp	r2, r3
- 8009fc8:	d204      	bcs.n	8009fd4 <tcp_process+0x460>
- 8009fca:	687b      	ldr	r3, [r7, #4]
- 8009fcc:	8e5b      	ldrh	r3, [r3, #50]	; 0x32
- 8009fce:	009b      	lsls	r3, r3, #2
- 8009fd0:	b29b      	uxth	r3, r3
- 8009fd2:	e00d      	b.n	8009ff0 <tcp_process+0x47c>
- 8009fd4:	687b      	ldr	r3, [r7, #4]
- 8009fd6:	8e5b      	ldrh	r3, [r3, #50]	; 0x32
- 8009fd8:	005b      	lsls	r3, r3, #1
- 8009fda:	f241 121c 	movw	r2, #4380	; 0x111c
- 8009fde:	4293      	cmp	r3, r2
- 8009fe0:	d904      	bls.n	8009fec <tcp_process+0x478>
- 8009fe2:	687b      	ldr	r3, [r7, #4]
- 8009fe4:	8e5b      	ldrh	r3, [r3, #50]	; 0x32
- 8009fe6:	005b      	lsls	r3, r3, #1
- 8009fe8:	b29b      	uxth	r3, r3
- 8009fea:	e001      	b.n	8009ff0 <tcp_process+0x47c>
- 8009fec:	f241 131c 	movw	r3, #4380	; 0x111c
- 8009ff0:	687a      	ldr	r2, [r7, #4]
- 8009ff2:	f8a2 3048 	strh.w	r3, [r2, #72]	; 0x48
-          LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_process (SYN_RCVD): cwnd %"TCPWNDSIZE_F
-                                       " ssthresh %"TCPWNDSIZE_F"\n",
-                                       pcb->cwnd, pcb->ssthresh));
-
-          if (recv_flags & TF_GOT_FIN) {
- 8009ff6:	4b4e      	ldr	r3, [pc, #312]	; (800a130 <tcp_process+0x5bc>)
- 8009ff8:	781b      	ldrb	r3, [r3, #0]
- 8009ffa:	f003 0320 	and.w	r3, r3, #32
- 8009ffe:	2b00      	cmp	r3, #0
- 800a000:	d037      	beq.n	800a072 <tcp_process+0x4fe>
-            tcp_ack_now(pcb);
- 800a002:	687b      	ldr	r3, [r7, #4]
- 800a004:	8b5b      	ldrh	r3, [r3, #26]
- 800a006:	f043 0302 	orr.w	r3, r3, #2
- 800a00a:	b29a      	uxth	r2, r3
- 800a00c:	687b      	ldr	r3, [r7, #4]
- 800a00e:	835a      	strh	r2, [r3, #26]
-            pcb->state = CLOSE_WAIT;
- 800a010:	687b      	ldr	r3, [r7, #4]
- 800a012:	2207      	movs	r2, #7
- 800a014:	751a      	strb	r2, [r3, #20]
-          if (recv_flags & TF_GOT_FIN) {
- 800a016:	e02c      	b.n	800a072 <tcp_process+0x4fe>
-          }
-        } else {
-          /* incorrect ACK number, send RST */
-          tcp_rst(pcb, ackno, seqno + tcplen, ip_current_dest_addr(),
- 800a018:	4b3b      	ldr	r3, [pc, #236]	; (800a108 <tcp_process+0x594>)
- 800a01a:	6819      	ldr	r1, [r3, #0]
- 800a01c:	4b3b      	ldr	r3, [pc, #236]	; (800a10c <tcp_process+0x598>)
- 800a01e:	881b      	ldrh	r3, [r3, #0]
- 800a020:	461a      	mov	r2, r3
- 800a022:	4b3b      	ldr	r3, [pc, #236]	; (800a110 <tcp_process+0x59c>)
- 800a024:	681b      	ldr	r3, [r3, #0]
- 800a026:	18d0      	adds	r0, r2, r3
-                  ip_current_src_addr(), tcphdr->dest, tcphdr->src);
- 800a028:	4b3a      	ldr	r3, [pc, #232]	; (800a114 <tcp_process+0x5a0>)
- 800a02a:	681b      	ldr	r3, [r3, #0]
-          tcp_rst(pcb, ackno, seqno + tcplen, ip_current_dest_addr(),
- 800a02c:	885b      	ldrh	r3, [r3, #2]
- 800a02e:	b29b      	uxth	r3, r3
-                  ip_current_src_addr(), tcphdr->dest, tcphdr->src);
- 800a030:	4a38      	ldr	r2, [pc, #224]	; (800a114 <tcp_process+0x5a0>)
- 800a032:	6812      	ldr	r2, [r2, #0]
-          tcp_rst(pcb, ackno, seqno + tcplen, ip_current_dest_addr(),
- 800a034:	8812      	ldrh	r2, [r2, #0]
- 800a036:	b292      	uxth	r2, r2
- 800a038:	9202      	str	r2, [sp, #8]
- 800a03a:	9301      	str	r3, [sp, #4]
- 800a03c:	4b36      	ldr	r3, [pc, #216]	; (800a118 <tcp_process+0x5a4>)
- 800a03e:	9300      	str	r3, [sp, #0]
- 800a040:	4b36      	ldr	r3, [pc, #216]	; (800a11c <tcp_process+0x5a8>)
- 800a042:	4602      	mov	r2, r0
- 800a044:	6878      	ldr	r0, [r7, #4]
- 800a046:	f003 f895 	bl	800d174 <tcp_rst>
-        }
-      } else if ((flags & TCP_SYN) && (seqno == pcb->rcv_nxt - 1)) {
-        /* Looks like another copy of the SYN - retransmit our SYN-ACK */
-        tcp_rexmit(pcb);
-      }
-      break;
- 800a04a:	e167      	b.n	800a31c <tcp_process+0x7a8>
-      } else if ((flags & TCP_SYN) && (seqno == pcb->rcv_nxt - 1)) {
- 800a04c:	4b2d      	ldr	r3, [pc, #180]	; (800a104 <tcp_process+0x590>)
- 800a04e:	781b      	ldrb	r3, [r3, #0]
- 800a050:	f003 0302 	and.w	r3, r3, #2
- 800a054:	2b00      	cmp	r3, #0
- 800a056:	f000 8161 	beq.w	800a31c <tcp_process+0x7a8>
- 800a05a:	687b      	ldr	r3, [r7, #4]
- 800a05c:	6a5b      	ldr	r3, [r3, #36]	; 0x24
- 800a05e:	1e5a      	subs	r2, r3, #1
- 800a060:	4b2b      	ldr	r3, [pc, #172]	; (800a110 <tcp_process+0x59c>)
- 800a062:	681b      	ldr	r3, [r3, #0]
- 800a064:	429a      	cmp	r2, r3
- 800a066:	f040 8159 	bne.w	800a31c <tcp_process+0x7a8>
-        tcp_rexmit(pcb);
- 800a06a:	6878      	ldr	r0, [r7, #4]
- 800a06c:	f002 fe7c 	bl	800cd68 <tcp_rexmit>
-      break;
- 800a070:	e154      	b.n	800a31c <tcp_process+0x7a8>
- 800a072:	e153      	b.n	800a31c <tcp_process+0x7a8>
-    case CLOSE_WAIT:
-    /* FALLTHROUGH */
-    case ESTABLISHED:
-      tcp_receive(pcb);
- 800a074:	6878      	ldr	r0, [r7, #4]
- 800a076:	f000 fa71 	bl	800a55c <tcp_receive>
-      if (recv_flags & TF_GOT_FIN) { /* passive close */
- 800a07a:	4b2d      	ldr	r3, [pc, #180]	; (800a130 <tcp_process+0x5bc>)
- 800a07c:	781b      	ldrb	r3, [r3, #0]
- 800a07e:	f003 0320 	and.w	r3, r3, #32
- 800a082:	2b00      	cmp	r3, #0
- 800a084:	f000 814c 	beq.w	800a320 <tcp_process+0x7ac>
-        tcp_ack_now(pcb);
- 800a088:	687b      	ldr	r3, [r7, #4]
- 800a08a:	8b5b      	ldrh	r3, [r3, #26]
- 800a08c:	f043 0302 	orr.w	r3, r3, #2
- 800a090:	b29a      	uxth	r2, r3
- 800a092:	687b      	ldr	r3, [r7, #4]
- 800a094:	835a      	strh	r2, [r3, #26]
-        pcb->state = CLOSE_WAIT;
- 800a096:	687b      	ldr	r3, [r7, #4]
- 800a098:	2207      	movs	r2, #7
- 800a09a:	751a      	strb	r2, [r3, #20]
-      }
-      break;
- 800a09c:	e140      	b.n	800a320 <tcp_process+0x7ac>
-    case FIN_WAIT_1:
-      tcp_receive(pcb);
- 800a09e:	6878      	ldr	r0, [r7, #4]
- 800a0a0:	f000 fa5c 	bl	800a55c <tcp_receive>
-      if (recv_flags & TF_GOT_FIN) {
- 800a0a4:	4b22      	ldr	r3, [pc, #136]	; (800a130 <tcp_process+0x5bc>)
- 800a0a6:	781b      	ldrb	r3, [r3, #0]
- 800a0a8:	f003 0320 	and.w	r3, r3, #32
- 800a0ac:	2b00      	cmp	r3, #0
- 800a0ae:	d071      	beq.n	800a194 <tcp_process+0x620>
-        if ((flags & TCP_ACK) && (ackno == pcb->snd_nxt) &&
- 800a0b0:	4b14      	ldr	r3, [pc, #80]	; (800a104 <tcp_process+0x590>)
- 800a0b2:	781b      	ldrb	r3, [r3, #0]
- 800a0b4:	f003 0310 	and.w	r3, r3, #16
- 800a0b8:	2b00      	cmp	r3, #0
- 800a0ba:	d060      	beq.n	800a17e <tcp_process+0x60a>
- 800a0bc:	687b      	ldr	r3, [r7, #4]
- 800a0be:	6d1a      	ldr	r2, [r3, #80]	; 0x50
- 800a0c0:	4b11      	ldr	r3, [pc, #68]	; (800a108 <tcp_process+0x594>)
- 800a0c2:	681b      	ldr	r3, [r3, #0]
- 800a0c4:	429a      	cmp	r2, r3
- 800a0c6:	d15a      	bne.n	800a17e <tcp_process+0x60a>
-            pcb->unsent == NULL) {
- 800a0c8:	687b      	ldr	r3, [r7, #4]
- 800a0ca:	6edb      	ldr	r3, [r3, #108]	; 0x6c
-        if ((flags & TCP_ACK) && (ackno == pcb->snd_nxt) &&
- 800a0cc:	2b00      	cmp	r3, #0
- 800a0ce:	d156      	bne.n	800a17e <tcp_process+0x60a>
-          LWIP_DEBUGF(TCP_DEBUG,
-                      ("TCP connection closed: FIN_WAIT_1 %"U16_F" -> %"U16_F".\n", inseg.tcphdr->src, inseg.tcphdr->dest));
-          tcp_ack_now(pcb);
- 800a0d0:	687b      	ldr	r3, [r7, #4]
- 800a0d2:	8b5b      	ldrh	r3, [r3, #26]
- 800a0d4:	f043 0302 	orr.w	r3, r3, #2
- 800a0d8:	b29a      	uxth	r2, r3
- 800a0da:	687b      	ldr	r3, [r7, #4]
- 800a0dc:	835a      	strh	r2, [r3, #26]
-          tcp_pcb_purge(pcb);
- 800a0de:	6878      	ldr	r0, [r7, #4]
- 800a0e0:	f7fe fdb6 	bl	8008c50 <tcp_pcb_purge>
-          TCP_RMV_ACTIVE(pcb);
- 800a0e4:	4b13      	ldr	r3, [pc, #76]	; (800a134 <tcp_process+0x5c0>)
- 800a0e6:	681b      	ldr	r3, [r3, #0]
- 800a0e8:	687a      	ldr	r2, [r7, #4]
- 800a0ea:	429a      	cmp	r2, r3
- 800a0ec:	d105      	bne.n	800a0fa <tcp_process+0x586>
- 800a0ee:	4b11      	ldr	r3, [pc, #68]	; (800a134 <tcp_process+0x5c0>)
- 800a0f0:	681b      	ldr	r3, [r3, #0]
- 800a0f2:	68db      	ldr	r3, [r3, #12]
- 800a0f4:	4a0f      	ldr	r2, [pc, #60]	; (800a134 <tcp_process+0x5c0>)
- 800a0f6:	6013      	str	r3, [r2, #0]
- 800a0f8:	e02e      	b.n	800a158 <tcp_process+0x5e4>
- 800a0fa:	4b0e      	ldr	r3, [pc, #56]	; (800a134 <tcp_process+0x5c0>)
- 800a0fc:	681b      	ldr	r3, [r3, #0]
- 800a0fe:	613b      	str	r3, [r7, #16]
- 800a100:	e027      	b.n	800a152 <tcp_process+0x5de>
- 800a102:	bf00      	nop
- 800a104:	24007bb4 	.word	0x24007bb4
- 800a108:	24007bac 	.word	0x24007bac
- 800a10c:	24007bb2 	.word	0x24007bb2
- 800a110:	24007ba8 	.word	0x24007ba8
- 800a114:	24007b98 	.word	0x24007b98
- 800a118:	24004c20 	.word	0x24004c20
- 800a11c:	24004c24 	.word	0x24004c24
- 800a120:	08013198 	.word	0x08013198
- 800a124:	08013438 	.word	0x08013438
- 800a128:	080131e4 	.word	0x080131e4
- 800a12c:	24007bb0 	.word	0x24007bb0
- 800a130:	24007bb5 	.word	0x24007bb5
- 800a134:	24007b78 	.word	0x24007b78
- 800a138:	693b      	ldr	r3, [r7, #16]
- 800a13a:	68db      	ldr	r3, [r3, #12]
- 800a13c:	687a      	ldr	r2, [r7, #4]
- 800a13e:	429a      	cmp	r2, r3
- 800a140:	d104      	bne.n	800a14c <tcp_process+0x5d8>
- 800a142:	687b      	ldr	r3, [r7, #4]
- 800a144:	68da      	ldr	r2, [r3, #12]
- 800a146:	693b      	ldr	r3, [r7, #16]
- 800a148:	60da      	str	r2, [r3, #12]
- 800a14a:	e005      	b.n	800a158 <tcp_process+0x5e4>
- 800a14c:	693b      	ldr	r3, [r7, #16]
- 800a14e:	68db      	ldr	r3, [r3, #12]
- 800a150:	613b      	str	r3, [r7, #16]
- 800a152:	693b      	ldr	r3, [r7, #16]
- 800a154:	2b00      	cmp	r3, #0
- 800a156:	d1ef      	bne.n	800a138 <tcp_process+0x5c4>
- 800a158:	687b      	ldr	r3, [r7, #4]
- 800a15a:	2200      	movs	r2, #0
- 800a15c:	60da      	str	r2, [r3, #12]
- 800a15e:	4b77      	ldr	r3, [pc, #476]	; (800a33c <tcp_process+0x7c8>)
- 800a160:	2201      	movs	r2, #1
- 800a162:	701a      	strb	r2, [r3, #0]
-          pcb->state = TIME_WAIT;
- 800a164:	687b      	ldr	r3, [r7, #4]
- 800a166:	220a      	movs	r2, #10
- 800a168:	751a      	strb	r2, [r3, #20]
-          TCP_REG(&tcp_tw_pcbs, pcb);
- 800a16a:	4b75      	ldr	r3, [pc, #468]	; (800a340 <tcp_process+0x7cc>)
- 800a16c:	681a      	ldr	r2, [r3, #0]
- 800a16e:	687b      	ldr	r3, [r7, #4]
- 800a170:	60da      	str	r2, [r3, #12]
- 800a172:	4a73      	ldr	r2, [pc, #460]	; (800a340 <tcp_process+0x7cc>)
- 800a174:	687b      	ldr	r3, [r7, #4]
- 800a176:	6013      	str	r3, [r2, #0]
- 800a178:	f003 f9be 	bl	800d4f8 <tcp_timer_needed>
-        }
-      } else if ((flags & TCP_ACK) && (ackno == pcb->snd_nxt) &&
-                 pcb->unsent == NULL) {
-        pcb->state = FIN_WAIT_2;
-      }
-      break;
- 800a17c:	e0d2      	b.n	800a324 <tcp_process+0x7b0>
-          tcp_ack_now(pcb);
- 800a17e:	687b      	ldr	r3, [r7, #4]
- 800a180:	8b5b      	ldrh	r3, [r3, #26]
- 800a182:	f043 0302 	orr.w	r3, r3, #2
- 800a186:	b29a      	uxth	r2, r3
- 800a188:	687b      	ldr	r3, [r7, #4]
- 800a18a:	835a      	strh	r2, [r3, #26]
-          pcb->state = CLOSING;
- 800a18c:	687b      	ldr	r3, [r7, #4]
- 800a18e:	2208      	movs	r2, #8
- 800a190:	751a      	strb	r2, [r3, #20]
-      break;
- 800a192:	e0c7      	b.n	800a324 <tcp_process+0x7b0>
-      } else if ((flags & TCP_ACK) && (ackno == pcb->snd_nxt) &&
- 800a194:	4b6b      	ldr	r3, [pc, #428]	; (800a344 <tcp_process+0x7d0>)
- 800a196:	781b      	ldrb	r3, [r3, #0]
- 800a198:	f003 0310 	and.w	r3, r3, #16
- 800a19c:	2b00      	cmp	r3, #0
- 800a19e:	f000 80c1 	beq.w	800a324 <tcp_process+0x7b0>
- 800a1a2:	687b      	ldr	r3, [r7, #4]
- 800a1a4:	6d1a      	ldr	r2, [r3, #80]	; 0x50
- 800a1a6:	4b68      	ldr	r3, [pc, #416]	; (800a348 <tcp_process+0x7d4>)
- 800a1a8:	681b      	ldr	r3, [r3, #0]
- 800a1aa:	429a      	cmp	r2, r3
- 800a1ac:	f040 80ba 	bne.w	800a324 <tcp_process+0x7b0>
-                 pcb->unsent == NULL) {
- 800a1b0:	687b      	ldr	r3, [r7, #4]
- 800a1b2:	6edb      	ldr	r3, [r3, #108]	; 0x6c
-      } else if ((flags & TCP_ACK) && (ackno == pcb->snd_nxt) &&
- 800a1b4:	2b00      	cmp	r3, #0
- 800a1b6:	f040 80b5 	bne.w	800a324 <tcp_process+0x7b0>
-        pcb->state = FIN_WAIT_2;
- 800a1ba:	687b      	ldr	r3, [r7, #4]
- 800a1bc:	2206      	movs	r2, #6
- 800a1be:	751a      	strb	r2, [r3, #20]
-      break;
- 800a1c0:	e0b0      	b.n	800a324 <tcp_process+0x7b0>
-    case FIN_WAIT_2:
-      tcp_receive(pcb);
- 800a1c2:	6878      	ldr	r0, [r7, #4]
- 800a1c4:	f000 f9ca 	bl	800a55c <tcp_receive>
-      if (recv_flags & TF_GOT_FIN) {
- 800a1c8:	4b60      	ldr	r3, [pc, #384]	; (800a34c <tcp_process+0x7d8>)
- 800a1ca:	781b      	ldrb	r3, [r3, #0]
- 800a1cc:	f003 0320 	and.w	r3, r3, #32
- 800a1d0:	2b00      	cmp	r3, #0
- 800a1d2:	f000 80a9 	beq.w	800a328 <tcp_process+0x7b4>
-        LWIP_DEBUGF(TCP_DEBUG, ("TCP connection closed: FIN_WAIT_2 %"U16_F" -> %"U16_F".\n", inseg.tcphdr->src, inseg.tcphdr->dest));
-        tcp_ack_now(pcb);
- 800a1d6:	687b      	ldr	r3, [r7, #4]
- 800a1d8:	8b5b      	ldrh	r3, [r3, #26]
- 800a1da:	f043 0302 	orr.w	r3, r3, #2
- 800a1de:	b29a      	uxth	r2, r3
- 800a1e0:	687b      	ldr	r3, [r7, #4]
- 800a1e2:	835a      	strh	r2, [r3, #26]
-        tcp_pcb_purge(pcb);
- 800a1e4:	6878      	ldr	r0, [r7, #4]
- 800a1e6:	f7fe fd33 	bl	8008c50 <tcp_pcb_purge>
-        TCP_RMV_ACTIVE(pcb);
- 800a1ea:	4b59      	ldr	r3, [pc, #356]	; (800a350 <tcp_process+0x7dc>)
- 800a1ec:	681b      	ldr	r3, [r3, #0]
- 800a1ee:	687a      	ldr	r2, [r7, #4]
- 800a1f0:	429a      	cmp	r2, r3
- 800a1f2:	d105      	bne.n	800a200 <tcp_process+0x68c>
- 800a1f4:	4b56      	ldr	r3, [pc, #344]	; (800a350 <tcp_process+0x7dc>)
- 800a1f6:	681b      	ldr	r3, [r3, #0]
- 800a1f8:	68db      	ldr	r3, [r3, #12]
- 800a1fa:	4a55      	ldr	r2, [pc, #340]	; (800a350 <tcp_process+0x7dc>)
- 800a1fc:	6013      	str	r3, [r2, #0]
- 800a1fe:	e013      	b.n	800a228 <tcp_process+0x6b4>
- 800a200:	4b53      	ldr	r3, [pc, #332]	; (800a350 <tcp_process+0x7dc>)
- 800a202:	681b      	ldr	r3, [r3, #0]
- 800a204:	60fb      	str	r3, [r7, #12]
- 800a206:	e00c      	b.n	800a222 <tcp_process+0x6ae>
- 800a208:	68fb      	ldr	r3, [r7, #12]
- 800a20a:	68db      	ldr	r3, [r3, #12]
- 800a20c:	687a      	ldr	r2, [r7, #4]
- 800a20e:	429a      	cmp	r2, r3
- 800a210:	d104      	bne.n	800a21c <tcp_process+0x6a8>
- 800a212:	687b      	ldr	r3, [r7, #4]
- 800a214:	68da      	ldr	r2, [r3, #12]
- 800a216:	68fb      	ldr	r3, [r7, #12]
- 800a218:	60da      	str	r2, [r3, #12]
- 800a21a:	e005      	b.n	800a228 <tcp_process+0x6b4>
- 800a21c:	68fb      	ldr	r3, [r7, #12]
- 800a21e:	68db      	ldr	r3, [r3, #12]
- 800a220:	60fb      	str	r3, [r7, #12]
- 800a222:	68fb      	ldr	r3, [r7, #12]
- 800a224:	2b00      	cmp	r3, #0
- 800a226:	d1ef      	bne.n	800a208 <tcp_process+0x694>
- 800a228:	687b      	ldr	r3, [r7, #4]
- 800a22a:	2200      	movs	r2, #0
- 800a22c:	60da      	str	r2, [r3, #12]
- 800a22e:	4b43      	ldr	r3, [pc, #268]	; (800a33c <tcp_process+0x7c8>)
- 800a230:	2201      	movs	r2, #1
- 800a232:	701a      	strb	r2, [r3, #0]
-        pcb->state = TIME_WAIT;
- 800a234:	687b      	ldr	r3, [r7, #4]
- 800a236:	220a      	movs	r2, #10
- 800a238:	751a      	strb	r2, [r3, #20]
-        TCP_REG(&tcp_tw_pcbs, pcb);
- 800a23a:	4b41      	ldr	r3, [pc, #260]	; (800a340 <tcp_process+0x7cc>)
- 800a23c:	681a      	ldr	r2, [r3, #0]
- 800a23e:	687b      	ldr	r3, [r7, #4]
- 800a240:	60da      	str	r2, [r3, #12]
- 800a242:	4a3f      	ldr	r2, [pc, #252]	; (800a340 <tcp_process+0x7cc>)
- 800a244:	687b      	ldr	r3, [r7, #4]
- 800a246:	6013      	str	r3, [r2, #0]
- 800a248:	f003 f956 	bl	800d4f8 <tcp_timer_needed>
-      }
-      break;
- 800a24c:	e06c      	b.n	800a328 <tcp_process+0x7b4>
-    case CLOSING:
-      tcp_receive(pcb);
- 800a24e:	6878      	ldr	r0, [r7, #4]
- 800a250:	f000 f984 	bl	800a55c <tcp_receive>
-      if ((flags & TCP_ACK) && ackno == pcb->snd_nxt && pcb->unsent == NULL) {
- 800a254:	4b3b      	ldr	r3, [pc, #236]	; (800a344 <tcp_process+0x7d0>)
- 800a256:	781b      	ldrb	r3, [r3, #0]
- 800a258:	f003 0310 	and.w	r3, r3, #16
- 800a25c:	2b00      	cmp	r3, #0
- 800a25e:	d065      	beq.n	800a32c <tcp_process+0x7b8>
- 800a260:	687b      	ldr	r3, [r7, #4]
- 800a262:	6d1a      	ldr	r2, [r3, #80]	; 0x50
- 800a264:	4b38      	ldr	r3, [pc, #224]	; (800a348 <tcp_process+0x7d4>)
- 800a266:	681b      	ldr	r3, [r3, #0]
- 800a268:	429a      	cmp	r2, r3
- 800a26a:	d15f      	bne.n	800a32c <tcp_process+0x7b8>
- 800a26c:	687b      	ldr	r3, [r7, #4]
- 800a26e:	6edb      	ldr	r3, [r3, #108]	; 0x6c
- 800a270:	2b00      	cmp	r3, #0
- 800a272:	d15b      	bne.n	800a32c <tcp_process+0x7b8>
-        LWIP_DEBUGF(TCP_DEBUG, ("TCP connection closed: CLOSING %"U16_F" -> %"U16_F".\n", inseg.tcphdr->src, inseg.tcphdr->dest));
-        tcp_pcb_purge(pcb);
- 800a274:	6878      	ldr	r0, [r7, #4]
- 800a276:	f7fe fceb 	bl	8008c50 <tcp_pcb_purge>
-        TCP_RMV_ACTIVE(pcb);
- 800a27a:	4b35      	ldr	r3, [pc, #212]	; (800a350 <tcp_process+0x7dc>)
- 800a27c:	681b      	ldr	r3, [r3, #0]
- 800a27e:	687a      	ldr	r2, [r7, #4]
- 800a280:	429a      	cmp	r2, r3
- 800a282:	d105      	bne.n	800a290 <tcp_process+0x71c>
- 800a284:	4b32      	ldr	r3, [pc, #200]	; (800a350 <tcp_process+0x7dc>)
- 800a286:	681b      	ldr	r3, [r3, #0]
- 800a288:	68db      	ldr	r3, [r3, #12]
- 800a28a:	4a31      	ldr	r2, [pc, #196]	; (800a350 <tcp_process+0x7dc>)
- 800a28c:	6013      	str	r3, [r2, #0]
- 800a28e:	e013      	b.n	800a2b8 <tcp_process+0x744>
- 800a290:	4b2f      	ldr	r3, [pc, #188]	; (800a350 <tcp_process+0x7dc>)
- 800a292:	681b      	ldr	r3, [r3, #0]
- 800a294:	61bb      	str	r3, [r7, #24]
- 800a296:	e00c      	b.n	800a2b2 <tcp_process+0x73e>
- 800a298:	69bb      	ldr	r3, [r7, #24]
- 800a29a:	68db      	ldr	r3, [r3, #12]
- 800a29c:	687a      	ldr	r2, [r7, #4]
- 800a29e:	429a      	cmp	r2, r3
- 800a2a0:	d104      	bne.n	800a2ac <tcp_process+0x738>
- 800a2a2:	687b      	ldr	r3, [r7, #4]
- 800a2a4:	68da      	ldr	r2, [r3, #12]
- 800a2a6:	69bb      	ldr	r3, [r7, #24]
- 800a2a8:	60da      	str	r2, [r3, #12]
- 800a2aa:	e005      	b.n	800a2b8 <tcp_process+0x744>
- 800a2ac:	69bb      	ldr	r3, [r7, #24]
- 800a2ae:	68db      	ldr	r3, [r3, #12]
- 800a2b0:	61bb      	str	r3, [r7, #24]
- 800a2b2:	69bb      	ldr	r3, [r7, #24]
- 800a2b4:	2b00      	cmp	r3, #0
- 800a2b6:	d1ef      	bne.n	800a298 <tcp_process+0x724>
- 800a2b8:	687b      	ldr	r3, [r7, #4]
- 800a2ba:	2200      	movs	r2, #0
- 800a2bc:	60da      	str	r2, [r3, #12]
- 800a2be:	4b1f      	ldr	r3, [pc, #124]	; (800a33c <tcp_process+0x7c8>)
- 800a2c0:	2201      	movs	r2, #1
- 800a2c2:	701a      	strb	r2, [r3, #0]
-        pcb->state = TIME_WAIT;
- 800a2c4:	687b      	ldr	r3, [r7, #4]
- 800a2c6:	220a      	movs	r2, #10
- 800a2c8:	751a      	strb	r2, [r3, #20]
-        TCP_REG(&tcp_tw_pcbs, pcb);
- 800a2ca:	4b1d      	ldr	r3, [pc, #116]	; (800a340 <tcp_process+0x7cc>)
- 800a2cc:	681a      	ldr	r2, [r3, #0]
- 800a2ce:	687b      	ldr	r3, [r7, #4]
- 800a2d0:	60da      	str	r2, [r3, #12]
- 800a2d2:	4a1b      	ldr	r2, [pc, #108]	; (800a340 <tcp_process+0x7cc>)
- 800a2d4:	687b      	ldr	r3, [r7, #4]
- 800a2d6:	6013      	str	r3, [r2, #0]
- 800a2d8:	f003 f90e 	bl	800d4f8 <tcp_timer_needed>
-      }
-      break;
- 800a2dc:	e026      	b.n	800a32c <tcp_process+0x7b8>
-    case LAST_ACK:
-      tcp_receive(pcb);
- 800a2de:	6878      	ldr	r0, [r7, #4]
- 800a2e0:	f000 f93c 	bl	800a55c <tcp_receive>
-      if ((flags & TCP_ACK) && ackno == pcb->snd_nxt && pcb->unsent == NULL) {
- 800a2e4:	4b17      	ldr	r3, [pc, #92]	; (800a344 <tcp_process+0x7d0>)
- 800a2e6:	781b      	ldrb	r3, [r3, #0]
- 800a2e8:	f003 0310 	and.w	r3, r3, #16
- 800a2ec:	2b00      	cmp	r3, #0
- 800a2ee:	d01f      	beq.n	800a330 <tcp_process+0x7bc>
- 800a2f0:	687b      	ldr	r3, [r7, #4]
- 800a2f2:	6d1a      	ldr	r2, [r3, #80]	; 0x50
- 800a2f4:	4b14      	ldr	r3, [pc, #80]	; (800a348 <tcp_process+0x7d4>)
- 800a2f6:	681b      	ldr	r3, [r3, #0]
- 800a2f8:	429a      	cmp	r2, r3
- 800a2fa:	d119      	bne.n	800a330 <tcp_process+0x7bc>
- 800a2fc:	687b      	ldr	r3, [r7, #4]
- 800a2fe:	6edb      	ldr	r3, [r3, #108]	; 0x6c
- 800a300:	2b00      	cmp	r3, #0
- 800a302:	d115      	bne.n	800a330 <tcp_process+0x7bc>
-        LWIP_DEBUGF(TCP_DEBUG, ("TCP connection closed: LAST_ACK %"U16_F" -> %"U16_F".\n", inseg.tcphdr->src, inseg.tcphdr->dest));
-        /* bugfix #21699: don't set pcb->state to CLOSED here or we risk leaking segments */
-        recv_flags |= TF_CLOSED;
- 800a304:	4b11      	ldr	r3, [pc, #68]	; (800a34c <tcp_process+0x7d8>)
- 800a306:	781b      	ldrb	r3, [r3, #0]
- 800a308:	f043 0310 	orr.w	r3, r3, #16
- 800a30c:	b2da      	uxtb	r2, r3
- 800a30e:	4b0f      	ldr	r3, [pc, #60]	; (800a34c <tcp_process+0x7d8>)
- 800a310:	701a      	strb	r2, [r3, #0]
-      }
-      break;
- 800a312:	e00d      	b.n	800a330 <tcp_process+0x7bc>
-    default:
-      break;
- 800a314:	bf00      	nop
- 800a316:	e00c      	b.n	800a332 <tcp_process+0x7be>
-      break;
- 800a318:	bf00      	nop
- 800a31a:	e00a      	b.n	800a332 <tcp_process+0x7be>
-      break;
- 800a31c:	bf00      	nop
- 800a31e:	e008      	b.n	800a332 <tcp_process+0x7be>
-      break;
- 800a320:	bf00      	nop
- 800a322:	e006      	b.n	800a332 <tcp_process+0x7be>
-      break;
- 800a324:	bf00      	nop
- 800a326:	e004      	b.n	800a332 <tcp_process+0x7be>
-      break;
- 800a328:	bf00      	nop
- 800a32a:	e002      	b.n	800a332 <tcp_process+0x7be>
-      break;
- 800a32c:	bf00      	nop
- 800a32e:	e000      	b.n	800a332 <tcp_process+0x7be>
-      break;
- 800a330:	bf00      	nop
-  }
-  return ERR_OK;
- 800a332:	2300      	movs	r3, #0
-}
- 800a334:	4618      	mov	r0, r3
- 800a336:	3724      	adds	r7, #36	; 0x24
- 800a338:	46bd      	mov	sp, r7
- 800a33a:	bd90      	pop	{r4, r7, pc}
- 800a33c:	24007b80 	.word	0x24007b80
- 800a340:	24007b7c 	.word	0x24007b7c
- 800a344:	24007bb4 	.word	0x24007bb4
- 800a348:	24007bac 	.word	0x24007bac
- 800a34c:	24007bb5 	.word	0x24007bb5
- 800a350:	24007b78 	.word	0x24007b78
-
-0800a354 <tcp_oos_insert_segment>:
- *
- * Called from tcp_receive()
- */
-static void
-tcp_oos_insert_segment(struct tcp_seg *cseg, struct tcp_seg *next)
-{
- 800a354:	b590      	push	{r4, r7, lr}
- 800a356:	b085      	sub	sp, #20
- 800a358:	af00      	add	r7, sp, #0
- 800a35a:	6078      	str	r0, [r7, #4]
- 800a35c:	6039      	str	r1, [r7, #0]
-  struct tcp_seg *old_seg;
-
-  LWIP_ASSERT("tcp_oos_insert_segment: invalid cseg", cseg != NULL);
- 800a35e:	687b      	ldr	r3, [r7, #4]
- 800a360:	2b00      	cmp	r3, #0
- 800a362:	d106      	bne.n	800a372 <tcp_oos_insert_segment+0x1e>
- 800a364:	4b3b      	ldr	r3, [pc, #236]	; (800a454 <tcp_oos_insert_segment+0x100>)
- 800a366:	f240 421f 	movw	r2, #1055	; 0x41f
- 800a36a:	493b      	ldr	r1, [pc, #236]	; (800a458 <tcp_oos_insert_segment+0x104>)
- 800a36c:	483b      	ldr	r0, [pc, #236]	; (800a45c <tcp_oos_insert_segment+0x108>)
- 800a36e:	f006 fc2b 	bl	8010bc8 <iprintf>
-
-  if (TCPH_FLAGS(cseg->tcphdr) & TCP_FIN) {
- 800a372:	687b      	ldr	r3, [r7, #4]
- 800a374:	691b      	ldr	r3, [r3, #16]
- 800a376:	899b      	ldrh	r3, [r3, #12]
- 800a378:	b29b      	uxth	r3, r3
- 800a37a:	4618      	mov	r0, r3
- 800a37c:	f7fb f8e6 	bl	800554c <lwip_htons>
- 800a380:	4603      	mov	r3, r0
- 800a382:	b2db      	uxtb	r3, r3
- 800a384:	f003 0301 	and.w	r3, r3, #1
- 800a388:	2b00      	cmp	r3, #0
- 800a38a:	d028      	beq.n	800a3de <tcp_oos_insert_segment+0x8a>
-    /* received segment overlaps all following segments */
-    tcp_segs_free(next);
- 800a38c:	6838      	ldr	r0, [r7, #0]
- 800a38e:	f7fe f9dd 	bl	800874c <tcp_segs_free>
-    next = NULL;
- 800a392:	2300      	movs	r3, #0
- 800a394:	603b      	str	r3, [r7, #0]
- 800a396:	e056      	b.n	800a446 <tcp_oos_insert_segment+0xf2>
-       oos queue may have segments with FIN flag */
-    while (next &&
-           TCP_SEQ_GEQ((seqno + cseg->len),
-                       (next->tcphdr->seqno + next->len))) {
-      /* cseg with FIN already processed */
-      if (TCPH_FLAGS(next->tcphdr) & TCP_FIN) {
- 800a398:	683b      	ldr	r3, [r7, #0]
- 800a39a:	691b      	ldr	r3, [r3, #16]
- 800a39c:	899b      	ldrh	r3, [r3, #12]
- 800a39e:	b29b      	uxth	r3, r3
- 800a3a0:	4618      	mov	r0, r3
- 800a3a2:	f7fb f8d3 	bl	800554c <lwip_htons>
- 800a3a6:	4603      	mov	r3, r0
- 800a3a8:	b2db      	uxtb	r3, r3
- 800a3aa:	f003 0301 	and.w	r3, r3, #1
- 800a3ae:	2b00      	cmp	r3, #0
- 800a3b0:	d00d      	beq.n	800a3ce <tcp_oos_insert_segment+0x7a>
-        TCPH_SET_FLAG(cseg->tcphdr, TCP_FIN);
- 800a3b2:	687b      	ldr	r3, [r7, #4]
- 800a3b4:	691b      	ldr	r3, [r3, #16]
- 800a3b6:	899b      	ldrh	r3, [r3, #12]
- 800a3b8:	b29c      	uxth	r4, r3
- 800a3ba:	2001      	movs	r0, #1
- 800a3bc:	f7fb f8c6 	bl	800554c <lwip_htons>
- 800a3c0:	4603      	mov	r3, r0
- 800a3c2:	461a      	mov	r2, r3
- 800a3c4:	687b      	ldr	r3, [r7, #4]
- 800a3c6:	691b      	ldr	r3, [r3, #16]
- 800a3c8:	4322      	orrs	r2, r4
- 800a3ca:	b292      	uxth	r2, r2
- 800a3cc:	819a      	strh	r2, [r3, #12]
-      }
-      old_seg = next;
- 800a3ce:	683b      	ldr	r3, [r7, #0]
- 800a3d0:	60fb      	str	r3, [r7, #12]
-      next = next->next;
- 800a3d2:	683b      	ldr	r3, [r7, #0]
- 800a3d4:	681b      	ldr	r3, [r3, #0]
- 800a3d6:	603b      	str	r3, [r7, #0]
-      tcp_seg_free(old_seg);
- 800a3d8:	68f8      	ldr	r0, [r7, #12]
- 800a3da:	f7fe f9cc 	bl	8008776 <tcp_seg_free>
-    while (next &&
- 800a3de:	683b      	ldr	r3, [r7, #0]
- 800a3e0:	2b00      	cmp	r3, #0
- 800a3e2:	d00e      	beq.n	800a402 <tcp_oos_insert_segment+0xae>
-           TCP_SEQ_GEQ((seqno + cseg->len),
- 800a3e4:	687b      	ldr	r3, [r7, #4]
- 800a3e6:	891b      	ldrh	r3, [r3, #8]
- 800a3e8:	461a      	mov	r2, r3
- 800a3ea:	4b1d      	ldr	r3, [pc, #116]	; (800a460 <tcp_oos_insert_segment+0x10c>)
- 800a3ec:	681b      	ldr	r3, [r3, #0]
- 800a3ee:	441a      	add	r2, r3
- 800a3f0:	683b      	ldr	r3, [r7, #0]
- 800a3f2:	691b      	ldr	r3, [r3, #16]
- 800a3f4:	685b      	ldr	r3, [r3, #4]
- 800a3f6:	6839      	ldr	r1, [r7, #0]
- 800a3f8:	8909      	ldrh	r1, [r1, #8]
- 800a3fa:	440b      	add	r3, r1
- 800a3fc:	1ad3      	subs	r3, r2, r3
-    while (next &&
- 800a3fe:	2b00      	cmp	r3, #0
- 800a400:	daca      	bge.n	800a398 <tcp_oos_insert_segment+0x44>
-    }
-    if (next &&
- 800a402:	683b      	ldr	r3, [r7, #0]
- 800a404:	2b00      	cmp	r3, #0
- 800a406:	d01e      	beq.n	800a446 <tcp_oos_insert_segment+0xf2>
-        TCP_SEQ_GT(seqno + cseg->len, next->tcphdr->seqno)) {
- 800a408:	687b      	ldr	r3, [r7, #4]
- 800a40a:	891b      	ldrh	r3, [r3, #8]
- 800a40c:	461a      	mov	r2, r3
- 800a40e:	4b14      	ldr	r3, [pc, #80]	; (800a460 <tcp_oos_insert_segment+0x10c>)
- 800a410:	681b      	ldr	r3, [r3, #0]
- 800a412:	441a      	add	r2, r3
- 800a414:	683b      	ldr	r3, [r7, #0]
- 800a416:	691b      	ldr	r3, [r3, #16]
- 800a418:	685b      	ldr	r3, [r3, #4]
- 800a41a:	1ad3      	subs	r3, r2, r3
-    if (next &&
- 800a41c:	2b00      	cmp	r3, #0
- 800a41e:	dd12      	ble.n	800a446 <tcp_oos_insert_segment+0xf2>
-      /* We need to trim the incoming segment. */
-      cseg->len = (u16_t)(next->tcphdr->seqno - seqno);
- 800a420:	683b      	ldr	r3, [r7, #0]
- 800a422:	691b      	ldr	r3, [r3, #16]
- 800a424:	685b      	ldr	r3, [r3, #4]
- 800a426:	b29a      	uxth	r2, r3
- 800a428:	4b0d      	ldr	r3, [pc, #52]	; (800a460 <tcp_oos_insert_segment+0x10c>)
- 800a42a:	681b      	ldr	r3, [r3, #0]
- 800a42c:	b29b      	uxth	r3, r3
- 800a42e:	1ad3      	subs	r3, r2, r3
- 800a430:	b29a      	uxth	r2, r3
- 800a432:	687b      	ldr	r3, [r7, #4]
- 800a434:	811a      	strh	r2, [r3, #8]
-      pbuf_realloc(cseg->p, cseg->len);
- 800a436:	687b      	ldr	r3, [r7, #4]
- 800a438:	685a      	ldr	r2, [r3, #4]
- 800a43a:	687b      	ldr	r3, [r7, #4]
- 800a43c:	891b      	ldrh	r3, [r3, #8]
- 800a43e:	4619      	mov	r1, r3
- 800a440:	4610      	mov	r0, r2
- 800a442:	f7fc fc41 	bl	8006cc8 <pbuf_realloc>
-    }
-  }
-  cseg->next = next;
- 800a446:	687b      	ldr	r3, [r7, #4]
- 800a448:	683a      	ldr	r2, [r7, #0]
- 800a44a:	601a      	str	r2, [r3, #0]
-}
- 800a44c:	bf00      	nop
- 800a44e:	3714      	adds	r7, #20
- 800a450:	46bd      	mov	sp, r7
- 800a452:	bd90      	pop	{r4, r7, pc}
- 800a454:	08013198 	.word	0x08013198
- 800a458:	08013458 	.word	0x08013458
- 800a45c:	080131e4 	.word	0x080131e4
- 800a460:	24007ba8 	.word	0x24007ba8
-
-0800a464 <tcp_free_acked_segments>:
-
-/** Remove segments from a list if the incoming ACK acknowledges them */
-static struct tcp_seg *
-tcp_free_acked_segments(struct tcp_pcb *pcb, struct tcp_seg *seg_list, const char *dbg_list_name,
-                        struct tcp_seg *dbg_other_seg_list)
-{
- 800a464:	b5b0      	push	{r4, r5, r7, lr}
- 800a466:	b086      	sub	sp, #24
- 800a468:	af00      	add	r7, sp, #0
- 800a46a:	60f8      	str	r0, [r7, #12]
- 800a46c:	60b9      	str	r1, [r7, #8]
- 800a46e:	607a      	str	r2, [r7, #4]
- 800a470:	603b      	str	r3, [r7, #0]
-  u16_t clen;
-
-  LWIP_UNUSED_ARG(dbg_list_name);
-  LWIP_UNUSED_ARG(dbg_other_seg_list);
-
-  while (seg_list != NULL &&
- 800a472:	e03e      	b.n	800a4f2 <tcp_free_acked_segments+0x8e>
-    LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: removing %"U32_F":%"U32_F" from pcb->%s\n",
-                                  lwip_ntohl(seg_list->tcphdr->seqno),
-                                  lwip_ntohl(seg_list->tcphdr->seqno) + TCP_TCPLEN(seg_list),
-                                  dbg_list_name));
-
-    next = seg_list;
- 800a474:	68bb      	ldr	r3, [r7, #8]
- 800a476:	617b      	str	r3, [r7, #20]
-    seg_list = seg_list->next;
- 800a478:	68bb      	ldr	r3, [r7, #8]
- 800a47a:	681b      	ldr	r3, [r3, #0]
- 800a47c:	60bb      	str	r3, [r7, #8]
-
-    clen = pbuf_clen(next->p);
- 800a47e:	697b      	ldr	r3, [r7, #20]
- 800a480:	685b      	ldr	r3, [r3, #4]
- 800a482:	4618      	mov	r0, r3
- 800a484:	f7fc fe2e 	bl	80070e4 <pbuf_clen>
- 800a488:	4603      	mov	r3, r0
- 800a48a:	827b      	strh	r3, [r7, #18]
-    LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_receive: queuelen %"TCPWNDSIZE_F" ... ",
-                                 (tcpwnd_size_t)pcb->snd_queuelen));
-    LWIP_ASSERT("pcb->snd_queuelen >= pbuf_clen(next->p)", (pcb->snd_queuelen >= clen));
- 800a48c:	68fb      	ldr	r3, [r7, #12]
- 800a48e:	f8b3 3066 	ldrh.w	r3, [r3, #102]	; 0x66
- 800a492:	8a7a      	ldrh	r2, [r7, #18]
- 800a494:	429a      	cmp	r2, r3
- 800a496:	d906      	bls.n	800a4a6 <tcp_free_acked_segments+0x42>
- 800a498:	4b2a      	ldr	r3, [pc, #168]	; (800a544 <tcp_free_acked_segments+0xe0>)
- 800a49a:	f240 4257 	movw	r2, #1111	; 0x457
- 800a49e:	492a      	ldr	r1, [pc, #168]	; (800a548 <tcp_free_acked_segments+0xe4>)
- 800a4a0:	482a      	ldr	r0, [pc, #168]	; (800a54c <tcp_free_acked_segments+0xe8>)
- 800a4a2:	f006 fb91 	bl	8010bc8 <iprintf>
-
-    pcb->snd_queuelen = (u16_t)(pcb->snd_queuelen - clen);
- 800a4a6:	68fb      	ldr	r3, [r7, #12]
- 800a4a8:	f8b3 2066 	ldrh.w	r2, [r3, #102]	; 0x66
- 800a4ac:	8a7b      	ldrh	r3, [r7, #18]
- 800a4ae:	1ad3      	subs	r3, r2, r3
- 800a4b0:	b29a      	uxth	r2, r3
- 800a4b2:	68fb      	ldr	r3, [r7, #12]
- 800a4b4:	f8a3 2066 	strh.w	r2, [r3, #102]	; 0x66
-    recv_acked = (tcpwnd_size_t)(recv_acked + next->len);
- 800a4b8:	697b      	ldr	r3, [r7, #20]
- 800a4ba:	891a      	ldrh	r2, [r3, #8]
- 800a4bc:	4b24      	ldr	r3, [pc, #144]	; (800a550 <tcp_free_acked_segments+0xec>)
- 800a4be:	881b      	ldrh	r3, [r3, #0]
- 800a4c0:	4413      	add	r3, r2
- 800a4c2:	b29a      	uxth	r2, r3
- 800a4c4:	4b22      	ldr	r3, [pc, #136]	; (800a550 <tcp_free_acked_segments+0xec>)
- 800a4c6:	801a      	strh	r2, [r3, #0]
-    tcp_seg_free(next);
- 800a4c8:	6978      	ldr	r0, [r7, #20]
- 800a4ca:	f7fe f954 	bl	8008776 <tcp_seg_free>
-
-    LWIP_DEBUGF(TCP_QLEN_DEBUG, ("%"TCPWNDSIZE_F" (after freeing %s)\n",
-                                 (tcpwnd_size_t)pcb->snd_queuelen,
-                                 dbg_list_name));
-    if (pcb->snd_queuelen != 0) {
- 800a4ce:	68fb      	ldr	r3, [r7, #12]
- 800a4d0:	f8b3 3066 	ldrh.w	r3, [r3, #102]	; 0x66
- 800a4d4:	2b00      	cmp	r3, #0
- 800a4d6:	d00c      	beq.n	800a4f2 <tcp_free_acked_segments+0x8e>
-      LWIP_ASSERT("tcp_receive: valid queue length",
- 800a4d8:	68bb      	ldr	r3, [r7, #8]
- 800a4da:	2b00      	cmp	r3, #0
- 800a4dc:	d109      	bne.n	800a4f2 <tcp_free_acked_segments+0x8e>
- 800a4de:	683b      	ldr	r3, [r7, #0]
- 800a4e0:	2b00      	cmp	r3, #0
- 800a4e2:	d106      	bne.n	800a4f2 <tcp_free_acked_segments+0x8e>
- 800a4e4:	4b17      	ldr	r3, [pc, #92]	; (800a544 <tcp_free_acked_segments+0xe0>)
- 800a4e6:	f240 4261 	movw	r2, #1121	; 0x461
- 800a4ea:	491a      	ldr	r1, [pc, #104]	; (800a554 <tcp_free_acked_segments+0xf0>)
- 800a4ec:	4817      	ldr	r0, [pc, #92]	; (800a54c <tcp_free_acked_segments+0xe8>)
- 800a4ee:	f006 fb6b 	bl	8010bc8 <iprintf>
-  while (seg_list != NULL &&
- 800a4f2:	68bb      	ldr	r3, [r7, #8]
- 800a4f4:	2b00      	cmp	r3, #0
- 800a4f6:	d020      	beq.n	800a53a <tcp_free_acked_segments+0xd6>
-         TCP_SEQ_LEQ(lwip_ntohl(seg_list->tcphdr->seqno) +
- 800a4f8:	68bb      	ldr	r3, [r7, #8]
- 800a4fa:	691b      	ldr	r3, [r3, #16]
- 800a4fc:	685b      	ldr	r3, [r3, #4]
- 800a4fe:	4618      	mov	r0, r3
- 800a500:	f7fb f839 	bl	8005576 <lwip_htonl>
- 800a504:	4604      	mov	r4, r0
- 800a506:	68bb      	ldr	r3, [r7, #8]
- 800a508:	891b      	ldrh	r3, [r3, #8]
- 800a50a:	461d      	mov	r5, r3
- 800a50c:	68bb      	ldr	r3, [r7, #8]
- 800a50e:	691b      	ldr	r3, [r3, #16]
- 800a510:	899b      	ldrh	r3, [r3, #12]
- 800a512:	b29b      	uxth	r3, r3
- 800a514:	4618      	mov	r0, r3
- 800a516:	f7fb f819 	bl	800554c <lwip_htons>
- 800a51a:	4603      	mov	r3, r0
- 800a51c:	b2db      	uxtb	r3, r3
- 800a51e:	f003 0303 	and.w	r3, r3, #3
- 800a522:	2b00      	cmp	r3, #0
- 800a524:	d001      	beq.n	800a52a <tcp_free_acked_segments+0xc6>
- 800a526:	2301      	movs	r3, #1
- 800a528:	e000      	b.n	800a52c <tcp_free_acked_segments+0xc8>
- 800a52a:	2300      	movs	r3, #0
- 800a52c:	442b      	add	r3, r5
- 800a52e:	18e2      	adds	r2, r4, r3
- 800a530:	4b09      	ldr	r3, [pc, #36]	; (800a558 <tcp_free_acked_segments+0xf4>)
- 800a532:	681b      	ldr	r3, [r3, #0]
- 800a534:	1ad3      	subs	r3, r2, r3
-  while (seg_list != NULL &&
- 800a536:	2b00      	cmp	r3, #0
- 800a538:	dd9c      	ble.n	800a474 <tcp_free_acked_segments+0x10>
-                  seg_list != NULL || dbg_other_seg_list != NULL);
-    }
-  }
-  return seg_list;
- 800a53a:	68bb      	ldr	r3, [r7, #8]
-}
- 800a53c:	4618      	mov	r0, r3
- 800a53e:	3718      	adds	r7, #24
- 800a540:	46bd      	mov	sp, r7
- 800a542:	bdb0      	pop	{r4, r5, r7, pc}
- 800a544:	08013198 	.word	0x08013198
- 800a548:	08013480 	.word	0x08013480
- 800a54c:	080131e4 	.word	0x080131e4
- 800a550:	24007bb0 	.word	0x24007bb0
- 800a554:	080134a8 	.word	0x080134a8
- 800a558:	24007bac 	.word	0x24007bac
-
-0800a55c <tcp_receive>:
- *
- * Called from tcp_process().
- */
-static void
-tcp_receive(struct tcp_pcb *pcb)
-{
- 800a55c:	b5b0      	push	{r4, r5, r7, lr}
- 800a55e:	b094      	sub	sp, #80	; 0x50
- 800a560:	af00      	add	r7, sp, #0
- 800a562:	6078      	str	r0, [r7, #4]
-  s16_t m;
-  u32_t right_wnd_edge;
-  int found_dupack = 0;
- 800a564:	2300      	movs	r3, #0
- 800a566:	64bb      	str	r3, [r7, #72]	; 0x48
-
-  LWIP_ASSERT("tcp_receive: invalid pcb", pcb != NULL);
- 800a568:	687b      	ldr	r3, [r7, #4]
- 800a56a:	2b00      	cmp	r3, #0
- 800a56c:	d106      	bne.n	800a57c <tcp_receive+0x20>
- 800a56e:	4b91      	ldr	r3, [pc, #580]	; (800a7b4 <tcp_receive+0x258>)
- 800a570:	f240 427b 	movw	r2, #1147	; 0x47b
- 800a574:	4990      	ldr	r1, [pc, #576]	; (800a7b8 <tcp_receive+0x25c>)
- 800a576:	4891      	ldr	r0, [pc, #580]	; (800a7bc <tcp_receive+0x260>)
- 800a578:	f006 fb26 	bl	8010bc8 <iprintf>
-  LWIP_ASSERT("tcp_receive: wrong state", pcb->state >= ESTABLISHED);
- 800a57c:	687b      	ldr	r3, [r7, #4]
- 800a57e:	7d1b      	ldrb	r3, [r3, #20]
- 800a580:	2b03      	cmp	r3, #3
- 800a582:	d806      	bhi.n	800a592 <tcp_receive+0x36>
- 800a584:	4b8b      	ldr	r3, [pc, #556]	; (800a7b4 <tcp_receive+0x258>)
- 800a586:	f240 427c 	movw	r2, #1148	; 0x47c
- 800a58a:	498d      	ldr	r1, [pc, #564]	; (800a7c0 <tcp_receive+0x264>)
- 800a58c:	488b      	ldr	r0, [pc, #556]	; (800a7bc <tcp_receive+0x260>)
- 800a58e:	f006 fb1b 	bl	8010bc8 <iprintf>
-
-  if (flags & TCP_ACK) {
- 800a592:	4b8c      	ldr	r3, [pc, #560]	; (800a7c4 <tcp_receive+0x268>)
- 800a594:	781b      	ldrb	r3, [r3, #0]
- 800a596:	f003 0310 	and.w	r3, r3, #16
- 800a59a:	2b00      	cmp	r3, #0
- 800a59c:	f000 8264 	beq.w	800aa68 <tcp_receive+0x50c>
-    right_wnd_edge = pcb->snd_wnd + pcb->snd_wl2;
- 800a5a0:	687b      	ldr	r3, [r7, #4]
- 800a5a2:	f8b3 3060 	ldrh.w	r3, [r3, #96]	; 0x60
- 800a5a6:	461a      	mov	r2, r3
- 800a5a8:	687b      	ldr	r3, [r7, #4]
- 800a5aa:	6d9b      	ldr	r3, [r3, #88]	; 0x58
- 800a5ac:	4413      	add	r3, r2
- 800a5ae:	633b      	str	r3, [r7, #48]	; 0x30
-
-    /* Update window. */
-    if (TCP_SEQ_LT(pcb->snd_wl1, seqno) ||
- 800a5b0:	687b      	ldr	r3, [r7, #4]
- 800a5b2:	6d5a      	ldr	r2, [r3, #84]	; 0x54
- 800a5b4:	4b84      	ldr	r3, [pc, #528]	; (800a7c8 <tcp_receive+0x26c>)
- 800a5b6:	681b      	ldr	r3, [r3, #0]
- 800a5b8:	1ad3      	subs	r3, r2, r3
- 800a5ba:	2b00      	cmp	r3, #0
- 800a5bc:	db1b      	blt.n	800a5f6 <tcp_receive+0x9a>
-        (pcb->snd_wl1 == seqno && TCP_SEQ_LT(pcb->snd_wl2, ackno)) ||
- 800a5be:	687b      	ldr	r3, [r7, #4]
- 800a5c0:	6d5a      	ldr	r2, [r3, #84]	; 0x54
- 800a5c2:	4b81      	ldr	r3, [pc, #516]	; (800a7c8 <tcp_receive+0x26c>)
- 800a5c4:	681b      	ldr	r3, [r3, #0]
-    if (TCP_SEQ_LT(pcb->snd_wl1, seqno) ||
- 800a5c6:	429a      	cmp	r2, r3
- 800a5c8:	d106      	bne.n	800a5d8 <tcp_receive+0x7c>
-        (pcb->snd_wl1 == seqno && TCP_SEQ_LT(pcb->snd_wl2, ackno)) ||
- 800a5ca:	687b      	ldr	r3, [r7, #4]
- 800a5cc:	6d9a      	ldr	r2, [r3, #88]	; 0x58
- 800a5ce:	4b7f      	ldr	r3, [pc, #508]	; (800a7cc <tcp_receive+0x270>)
- 800a5d0:	681b      	ldr	r3, [r3, #0]
- 800a5d2:	1ad3      	subs	r3, r2, r3
- 800a5d4:	2b00      	cmp	r3, #0
- 800a5d6:	db0e      	blt.n	800a5f6 <tcp_receive+0x9a>
-        (pcb->snd_wl2 == ackno && (u32_t)SND_WND_SCALE(pcb, tcphdr->wnd) > pcb->snd_wnd)) {
- 800a5d8:	687b      	ldr	r3, [r7, #4]
- 800a5da:	6d9a      	ldr	r2, [r3, #88]	; 0x58
- 800a5dc:	4b7b      	ldr	r3, [pc, #492]	; (800a7cc <tcp_receive+0x270>)
- 800a5de:	681b      	ldr	r3, [r3, #0]
-        (pcb->snd_wl1 == seqno && TCP_SEQ_LT(pcb->snd_wl2, ackno)) ||
- 800a5e0:	429a      	cmp	r2, r3
- 800a5e2:	d125      	bne.n	800a630 <tcp_receive+0xd4>
-        (pcb->snd_wl2 == ackno && (u32_t)SND_WND_SCALE(pcb, tcphdr->wnd) > pcb->snd_wnd)) {
- 800a5e4:	4b7a      	ldr	r3, [pc, #488]	; (800a7d0 <tcp_receive+0x274>)
- 800a5e6:	681b      	ldr	r3, [r3, #0]
- 800a5e8:	89db      	ldrh	r3, [r3, #14]
- 800a5ea:	b29a      	uxth	r2, r3
- 800a5ec:	687b      	ldr	r3, [r7, #4]
- 800a5ee:	f8b3 3060 	ldrh.w	r3, [r3, #96]	; 0x60
- 800a5f2:	429a      	cmp	r2, r3
- 800a5f4:	d91c      	bls.n	800a630 <tcp_receive+0xd4>
-      pcb->snd_wnd = SND_WND_SCALE(pcb, tcphdr->wnd);
- 800a5f6:	4b76      	ldr	r3, [pc, #472]	; (800a7d0 <tcp_receive+0x274>)
- 800a5f8:	681b      	ldr	r3, [r3, #0]
- 800a5fa:	89db      	ldrh	r3, [r3, #14]
- 800a5fc:	b29a      	uxth	r2, r3
- 800a5fe:	687b      	ldr	r3, [r7, #4]
- 800a600:	f8a3 2060 	strh.w	r2, [r3, #96]	; 0x60
-      /* keep track of the biggest window announced by the remote host to calculate
-         the maximum segment size */
-      if (pcb->snd_wnd_max < pcb->snd_wnd) {
- 800a604:	687b      	ldr	r3, [r7, #4]
- 800a606:	f8b3 2062 	ldrh.w	r2, [r3, #98]	; 0x62
- 800a60a:	687b      	ldr	r3, [r7, #4]
- 800a60c:	f8b3 3060 	ldrh.w	r3, [r3, #96]	; 0x60
- 800a610:	429a      	cmp	r2, r3
- 800a612:	d205      	bcs.n	800a620 <tcp_receive+0xc4>
-        pcb->snd_wnd_max = pcb->snd_wnd;
- 800a614:	687b      	ldr	r3, [r7, #4]
- 800a616:	f8b3 2060 	ldrh.w	r2, [r3, #96]	; 0x60
- 800a61a:	687b      	ldr	r3, [r7, #4]
- 800a61c:	f8a3 2062 	strh.w	r2, [r3, #98]	; 0x62
-      }
-      pcb->snd_wl1 = seqno;
- 800a620:	4b69      	ldr	r3, [pc, #420]	; (800a7c8 <tcp_receive+0x26c>)
- 800a622:	681a      	ldr	r2, [r3, #0]
- 800a624:	687b      	ldr	r3, [r7, #4]
- 800a626:	655a      	str	r2, [r3, #84]	; 0x54
-      pcb->snd_wl2 = ackno;
- 800a628:	4b68      	ldr	r3, [pc, #416]	; (800a7cc <tcp_receive+0x270>)
- 800a62a:	681a      	ldr	r2, [r3, #0]
- 800a62c:	687b      	ldr	r3, [r7, #4]
- 800a62e:	659a      	str	r2, [r3, #88]	; 0x58
-     * If it only passes 1, should reset dupack counter
-     *
-     */
-
-    /* Clause 1 */
-    if (TCP_SEQ_LEQ(ackno, pcb->lastack)) {
- 800a630:	4b66      	ldr	r3, [pc, #408]	; (800a7cc <tcp_receive+0x270>)
- 800a632:	681a      	ldr	r2, [r3, #0]
- 800a634:	687b      	ldr	r3, [r7, #4]
- 800a636:	6c5b      	ldr	r3, [r3, #68]	; 0x44
- 800a638:	1ad3      	subs	r3, r2, r3
- 800a63a:	2b00      	cmp	r3, #0
- 800a63c:	dc58      	bgt.n	800a6f0 <tcp_receive+0x194>
-      /* Clause 2 */
-      if (tcplen == 0) {
- 800a63e:	4b65      	ldr	r3, [pc, #404]	; (800a7d4 <tcp_receive+0x278>)
- 800a640:	881b      	ldrh	r3, [r3, #0]
- 800a642:	2b00      	cmp	r3, #0
- 800a644:	d14b      	bne.n	800a6de <tcp_receive+0x182>
-        /* Clause 3 */
-        if (pcb->snd_wl2 + pcb->snd_wnd == right_wnd_edge) {
- 800a646:	687b      	ldr	r3, [r7, #4]
- 800a648:	6d9b      	ldr	r3, [r3, #88]	; 0x58
- 800a64a:	687a      	ldr	r2, [r7, #4]
- 800a64c:	f8b2 2060 	ldrh.w	r2, [r2, #96]	; 0x60
- 800a650:	4413      	add	r3, r2
- 800a652:	6b3a      	ldr	r2, [r7, #48]	; 0x30
- 800a654:	429a      	cmp	r2, r3
- 800a656:	d142      	bne.n	800a6de <tcp_receive+0x182>
-          /* Clause 4 */
-          if (pcb->rtime >= 0) {
- 800a658:	687b      	ldr	r3, [r7, #4]
- 800a65a:	f9b3 3030 	ldrsh.w	r3, [r3, #48]	; 0x30
- 800a65e:	2b00      	cmp	r3, #0
- 800a660:	db3d      	blt.n	800a6de <tcp_receive+0x182>
-            /* Clause 5 */
-            if (pcb->lastack == ackno) {
- 800a662:	687b      	ldr	r3, [r7, #4]
- 800a664:	6c5a      	ldr	r2, [r3, #68]	; 0x44
- 800a666:	4b59      	ldr	r3, [pc, #356]	; (800a7cc <tcp_receive+0x270>)
- 800a668:	681b      	ldr	r3, [r3, #0]
- 800a66a:	429a      	cmp	r2, r3
- 800a66c:	d137      	bne.n	800a6de <tcp_receive+0x182>
-              found_dupack = 1;
- 800a66e:	2301      	movs	r3, #1
- 800a670:	64bb      	str	r3, [r7, #72]	; 0x48
-              if ((u8_t)(pcb->dupacks + 1) > pcb->dupacks) {
- 800a672:	687b      	ldr	r3, [r7, #4]
- 800a674:	f893 3043 	ldrb.w	r3, [r3, #67]	; 0x43
- 800a678:	2bff      	cmp	r3, #255	; 0xff
- 800a67a:	d007      	beq.n	800a68c <tcp_receive+0x130>
-                ++pcb->dupacks;
- 800a67c:	687b      	ldr	r3, [r7, #4]
- 800a67e:	f893 3043 	ldrb.w	r3, [r3, #67]	; 0x43
- 800a682:	3301      	adds	r3, #1
- 800a684:	b2da      	uxtb	r2, r3
- 800a686:	687b      	ldr	r3, [r7, #4]
- 800a688:	f883 2043 	strb.w	r2, [r3, #67]	; 0x43
-              }
-              if (pcb->dupacks > 3) {
- 800a68c:	687b      	ldr	r3, [r7, #4]
- 800a68e:	f893 3043 	ldrb.w	r3, [r3, #67]	; 0x43
- 800a692:	2b03      	cmp	r3, #3
- 800a694:	d91b      	bls.n	800a6ce <tcp_receive+0x172>
-                /* Inflate the congestion window */
-                TCP_WND_INC(pcb->cwnd, pcb->mss);
- 800a696:	687b      	ldr	r3, [r7, #4]
- 800a698:	f8b3 2048 	ldrh.w	r2, [r3, #72]	; 0x48
- 800a69c:	687b      	ldr	r3, [r7, #4]
- 800a69e:	8e5b      	ldrh	r3, [r3, #50]	; 0x32
- 800a6a0:	4413      	add	r3, r2
- 800a6a2:	b29a      	uxth	r2, r3
- 800a6a4:	687b      	ldr	r3, [r7, #4]
- 800a6a6:	f8b3 3048 	ldrh.w	r3, [r3, #72]	; 0x48
- 800a6aa:	429a      	cmp	r2, r3
- 800a6ac:	d30a      	bcc.n	800a6c4 <tcp_receive+0x168>
- 800a6ae:	687b      	ldr	r3, [r7, #4]
- 800a6b0:	f8b3 2048 	ldrh.w	r2, [r3, #72]	; 0x48
- 800a6b4:	687b      	ldr	r3, [r7, #4]
- 800a6b6:	8e5b      	ldrh	r3, [r3, #50]	; 0x32
- 800a6b8:	4413      	add	r3, r2
- 800a6ba:	b29a      	uxth	r2, r3
- 800a6bc:	687b      	ldr	r3, [r7, #4]
- 800a6be:	f8a3 2048 	strh.w	r2, [r3, #72]	; 0x48
- 800a6c2:	e004      	b.n	800a6ce <tcp_receive+0x172>
- 800a6c4:	687b      	ldr	r3, [r7, #4]
- 800a6c6:	f64f 72ff 	movw	r2, #65535	; 0xffff
- 800a6ca:	f8a3 2048 	strh.w	r2, [r3, #72]	; 0x48
-              }
-              if (pcb->dupacks >= 3) {
- 800a6ce:	687b      	ldr	r3, [r7, #4]
- 800a6d0:	f893 3043 	ldrb.w	r3, [r3, #67]	; 0x43
- 800a6d4:	2b02      	cmp	r3, #2
- 800a6d6:	d902      	bls.n	800a6de <tcp_receive+0x182>
-                /* Do fast retransmit (checked via TF_INFR, not via dupacks count) */
-                tcp_rexmit_fast(pcb);
- 800a6d8:	6878      	ldr	r0, [r7, #4]
- 800a6da:	f002 fbb1 	bl	800ce40 <tcp_rexmit_fast>
-          }
-        }
-      }
-      /* If Clause (1) or more is true, but not a duplicate ack, reset
-       * count of consecutive duplicate acks */
-      if (!found_dupack) {
- 800a6de:	6cbb      	ldr	r3, [r7, #72]	; 0x48
- 800a6e0:	2b00      	cmp	r3, #0
- 800a6e2:	f040 8161 	bne.w	800a9a8 <tcp_receive+0x44c>
-        pcb->dupacks = 0;
- 800a6e6:	687b      	ldr	r3, [r7, #4]
- 800a6e8:	2200      	movs	r2, #0
- 800a6ea:	f883 2043 	strb.w	r2, [r3, #67]	; 0x43
- 800a6ee:	e15b      	b.n	800a9a8 <tcp_receive+0x44c>
-      }
-    } else if (TCP_SEQ_BETWEEN(ackno, pcb->lastack + 1, pcb->snd_nxt)) {
- 800a6f0:	4b36      	ldr	r3, [pc, #216]	; (800a7cc <tcp_receive+0x270>)
- 800a6f2:	681a      	ldr	r2, [r3, #0]
- 800a6f4:	687b      	ldr	r3, [r7, #4]
- 800a6f6:	6c5b      	ldr	r3, [r3, #68]	; 0x44
- 800a6f8:	1ad3      	subs	r3, r2, r3
- 800a6fa:	3b01      	subs	r3, #1
- 800a6fc:	2b00      	cmp	r3, #0
- 800a6fe:	f2c0 814e 	blt.w	800a99e <tcp_receive+0x442>
- 800a702:	4b32      	ldr	r3, [pc, #200]	; (800a7cc <tcp_receive+0x270>)
- 800a704:	681a      	ldr	r2, [r3, #0]
- 800a706:	687b      	ldr	r3, [r7, #4]
- 800a708:	6d1b      	ldr	r3, [r3, #80]	; 0x50
- 800a70a:	1ad3      	subs	r3, r2, r3
- 800a70c:	2b00      	cmp	r3, #0
- 800a70e:	f300 8146 	bgt.w	800a99e <tcp_receive+0x442>
-      tcpwnd_size_t acked;
-
-      /* Reset the "IN Fast Retransmit" flag, since we are no longer
-         in fast retransmit. Also reset the congestion window to the
-         slow start threshold. */
-      if (pcb->flags & TF_INFR) {
- 800a712:	687b      	ldr	r3, [r7, #4]
- 800a714:	8b5b      	ldrh	r3, [r3, #26]
- 800a716:	f003 0304 	and.w	r3, r3, #4
- 800a71a:	2b00      	cmp	r3, #0
- 800a71c:	d010      	beq.n	800a740 <tcp_receive+0x1e4>
-        tcp_clear_flags(pcb, TF_INFR);
- 800a71e:	687b      	ldr	r3, [r7, #4]
- 800a720:	8b5b      	ldrh	r3, [r3, #26]
- 800a722:	f023 0304 	bic.w	r3, r3, #4
- 800a726:	b29a      	uxth	r2, r3
- 800a728:	687b      	ldr	r3, [r7, #4]
- 800a72a:	835a      	strh	r2, [r3, #26]
-        pcb->cwnd = pcb->ssthresh;
- 800a72c:	687b      	ldr	r3, [r7, #4]
- 800a72e:	f8b3 204a 	ldrh.w	r2, [r3, #74]	; 0x4a
- 800a732:	687b      	ldr	r3, [r7, #4]
- 800a734:	f8a3 2048 	strh.w	r2, [r3, #72]	; 0x48
-        pcb->bytes_acked = 0;
- 800a738:	687b      	ldr	r3, [r7, #4]
- 800a73a:	2200      	movs	r2, #0
- 800a73c:	f8a3 206a 	strh.w	r2, [r3, #106]	; 0x6a
-      }
-
-      /* Reset the number of retransmissions. */
-      pcb->nrtx = 0;
- 800a740:	687b      	ldr	r3, [r7, #4]
- 800a742:	2200      	movs	r2, #0
- 800a744:	f883 2042 	strb.w	r2, [r3, #66]	; 0x42
-
-      /* Reset the retransmission time-out. */
-      pcb->rto = (s16_t)((pcb->sa >> 3) + pcb->sv);
- 800a748:	687b      	ldr	r3, [r7, #4]
- 800a74a:	f9b3 303c 	ldrsh.w	r3, [r3, #60]	; 0x3c
- 800a74e:	10db      	asrs	r3, r3, #3
- 800a750:	b21b      	sxth	r3, r3
- 800a752:	b29a      	uxth	r2, r3
- 800a754:	687b      	ldr	r3, [r7, #4]
- 800a756:	f9b3 303e 	ldrsh.w	r3, [r3, #62]	; 0x3e
- 800a75a:	b29b      	uxth	r3, r3
- 800a75c:	4413      	add	r3, r2
- 800a75e:	b29b      	uxth	r3, r3
- 800a760:	b21a      	sxth	r2, r3
- 800a762:	687b      	ldr	r3, [r7, #4]
- 800a764:	f8a3 2040 	strh.w	r2, [r3, #64]	; 0x40
-
-      /* Record how much data this ACK acks */
-      acked = (tcpwnd_size_t)(ackno - pcb->lastack);
- 800a768:	4b18      	ldr	r3, [pc, #96]	; (800a7cc <tcp_receive+0x270>)
- 800a76a:	681b      	ldr	r3, [r3, #0]
- 800a76c:	b29a      	uxth	r2, r3
- 800a76e:	687b      	ldr	r3, [r7, #4]
- 800a770:	6c5b      	ldr	r3, [r3, #68]	; 0x44
- 800a772:	b29b      	uxth	r3, r3
- 800a774:	1ad3      	subs	r3, r2, r3
- 800a776:	85fb      	strh	r3, [r7, #46]	; 0x2e
-
-      /* Reset the fast retransmit variables. */
-      pcb->dupacks = 0;
- 800a778:	687b      	ldr	r3, [r7, #4]
- 800a77a:	2200      	movs	r2, #0
- 800a77c:	f883 2043 	strb.w	r2, [r3, #67]	; 0x43
-      pcb->lastack = ackno;
- 800a780:	4b12      	ldr	r3, [pc, #72]	; (800a7cc <tcp_receive+0x270>)
- 800a782:	681a      	ldr	r2, [r3, #0]
- 800a784:	687b      	ldr	r3, [r7, #4]
- 800a786:	645a      	str	r2, [r3, #68]	; 0x44
-
-      /* Update the congestion control variables (cwnd and
-         ssthresh). */
-      if (pcb->state >= ESTABLISHED) {
- 800a788:	687b      	ldr	r3, [r7, #4]
- 800a78a:	7d1b      	ldrb	r3, [r3, #20]
- 800a78c:	2b03      	cmp	r3, #3
- 800a78e:	f240 8097 	bls.w	800a8c0 <tcp_receive+0x364>
-        if (pcb->cwnd < pcb->ssthresh) {
- 800a792:	687b      	ldr	r3, [r7, #4]
- 800a794:	f8b3 2048 	ldrh.w	r2, [r3, #72]	; 0x48
- 800a798:	687b      	ldr	r3, [r7, #4]
- 800a79a:	f8b3 304a 	ldrh.w	r3, [r3, #74]	; 0x4a
- 800a79e:	429a      	cmp	r2, r3
- 800a7a0:	d245      	bcs.n	800a82e <tcp_receive+0x2d2>
-          tcpwnd_size_t increase;
-          /* limit to 1 SMSS segment during period following RTO */
-          u8_t num_seg = (pcb->flags & TF_RTO) ? 1 : 2;
- 800a7a2:	687b      	ldr	r3, [r7, #4]
- 800a7a4:	8b5b      	ldrh	r3, [r3, #26]
- 800a7a6:	f403 6300 	and.w	r3, r3, #2048	; 0x800
- 800a7aa:	2b00      	cmp	r3, #0
- 800a7ac:	d014      	beq.n	800a7d8 <tcp_receive+0x27c>
- 800a7ae:	2301      	movs	r3, #1
- 800a7b0:	e013      	b.n	800a7da <tcp_receive+0x27e>
- 800a7b2:	bf00      	nop
- 800a7b4:	08013198 	.word	0x08013198
- 800a7b8:	080134c8 	.word	0x080134c8
- 800a7bc:	080131e4 	.word	0x080131e4
- 800a7c0:	080134e4 	.word	0x080134e4
- 800a7c4:	24007bb4 	.word	0x24007bb4
- 800a7c8:	24007ba8 	.word	0x24007ba8
- 800a7cc:	24007bac 	.word	0x24007bac
- 800a7d0:	24007b98 	.word	0x24007b98
- 800a7d4:	24007bb2 	.word	0x24007bb2
- 800a7d8:	2302      	movs	r3, #2
- 800a7da:	f887 302d 	strb.w	r3, [r7, #45]	; 0x2d
-          /* RFC 3465, section 2.2 Slow Start */
-          increase = LWIP_MIN(acked, (tcpwnd_size_t)(num_seg * pcb->mss));
- 800a7de:	f897 302d 	ldrb.w	r3, [r7, #45]	; 0x2d
- 800a7e2:	b29a      	uxth	r2, r3
- 800a7e4:	687b      	ldr	r3, [r7, #4]
- 800a7e6:	8e5b      	ldrh	r3, [r3, #50]	; 0x32
- 800a7e8:	fb12 f303 	smulbb	r3, r2, r3
- 800a7ec:	b29b      	uxth	r3, r3
- 800a7ee:	8dfa      	ldrh	r2, [r7, #46]	; 0x2e
- 800a7f0:	4293      	cmp	r3, r2
- 800a7f2:	bf28      	it	cs
- 800a7f4:	4613      	movcs	r3, r2
- 800a7f6:	857b      	strh	r3, [r7, #42]	; 0x2a
-          TCP_WND_INC(pcb->cwnd, increase);
- 800a7f8:	687b      	ldr	r3, [r7, #4]
- 800a7fa:	f8b3 2048 	ldrh.w	r2, [r3, #72]	; 0x48
- 800a7fe:	8d7b      	ldrh	r3, [r7, #42]	; 0x2a
- 800a800:	4413      	add	r3, r2
- 800a802:	b29a      	uxth	r2, r3
- 800a804:	687b      	ldr	r3, [r7, #4]
- 800a806:	f8b3 3048 	ldrh.w	r3, [r3, #72]	; 0x48
- 800a80a:	429a      	cmp	r2, r3
- 800a80c:	d309      	bcc.n	800a822 <tcp_receive+0x2c6>
- 800a80e:	687b      	ldr	r3, [r7, #4]
- 800a810:	f8b3 2048 	ldrh.w	r2, [r3, #72]	; 0x48
- 800a814:	8d7b      	ldrh	r3, [r7, #42]	; 0x2a
- 800a816:	4413      	add	r3, r2
- 800a818:	b29a      	uxth	r2, r3
- 800a81a:	687b      	ldr	r3, [r7, #4]
- 800a81c:	f8a3 2048 	strh.w	r2, [r3, #72]	; 0x48
- 800a820:	e04e      	b.n	800a8c0 <tcp_receive+0x364>
- 800a822:	687b      	ldr	r3, [r7, #4]
- 800a824:	f64f 72ff 	movw	r2, #65535	; 0xffff
- 800a828:	f8a3 2048 	strh.w	r2, [r3, #72]	; 0x48
- 800a82c:	e048      	b.n	800a8c0 <tcp_receive+0x364>
-          LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_receive: slow start cwnd %"TCPWNDSIZE_F"\n", pcb->cwnd));
-        } else {
-          /* RFC 3465, section 2.1 Congestion Avoidance */
-          TCP_WND_INC(pcb->bytes_acked, acked);
- 800a82e:	687b      	ldr	r3, [r7, #4]
- 800a830:	f8b3 206a 	ldrh.w	r2, [r3, #106]	; 0x6a
- 800a834:	8dfb      	ldrh	r3, [r7, #46]	; 0x2e
- 800a836:	4413      	add	r3, r2
- 800a838:	b29a      	uxth	r2, r3
- 800a83a:	687b      	ldr	r3, [r7, #4]
- 800a83c:	f8b3 306a 	ldrh.w	r3, [r3, #106]	; 0x6a
- 800a840:	429a      	cmp	r2, r3
- 800a842:	d309      	bcc.n	800a858 <tcp_receive+0x2fc>
- 800a844:	687b      	ldr	r3, [r7, #4]
- 800a846:	f8b3 206a 	ldrh.w	r2, [r3, #106]	; 0x6a
- 800a84a:	8dfb      	ldrh	r3, [r7, #46]	; 0x2e
- 800a84c:	4413      	add	r3, r2
- 800a84e:	b29a      	uxth	r2, r3
- 800a850:	687b      	ldr	r3, [r7, #4]
- 800a852:	f8a3 206a 	strh.w	r2, [r3, #106]	; 0x6a
- 800a856:	e004      	b.n	800a862 <tcp_receive+0x306>
- 800a858:	687b      	ldr	r3, [r7, #4]
- 800a85a:	f64f 72ff 	movw	r2, #65535	; 0xffff
- 800a85e:	f8a3 206a 	strh.w	r2, [r3, #106]	; 0x6a
-          if (pcb->bytes_acked >= pcb->cwnd) {
- 800a862:	687b      	ldr	r3, [r7, #4]
- 800a864:	f8b3 206a 	ldrh.w	r2, [r3, #106]	; 0x6a
- 800a868:	687b      	ldr	r3, [r7, #4]
- 800a86a:	f8b3 3048 	ldrh.w	r3, [r3, #72]	; 0x48
- 800a86e:	429a      	cmp	r2, r3
- 800a870:	d326      	bcc.n	800a8c0 <tcp_receive+0x364>
-            pcb->bytes_acked = (tcpwnd_size_t)(pcb->bytes_acked - pcb->cwnd);
- 800a872:	687b      	ldr	r3, [r7, #4]
- 800a874:	f8b3 206a 	ldrh.w	r2, [r3, #106]	; 0x6a
- 800a878:	687b      	ldr	r3, [r7, #4]
- 800a87a:	f8b3 3048 	ldrh.w	r3, [r3, #72]	; 0x48
- 800a87e:	1ad3      	subs	r3, r2, r3
- 800a880:	b29a      	uxth	r2, r3
- 800a882:	687b      	ldr	r3, [r7, #4]
- 800a884:	f8a3 206a 	strh.w	r2, [r3, #106]	; 0x6a
-            TCP_WND_INC(pcb->cwnd, pcb->mss);
- 800a888:	687b      	ldr	r3, [r7, #4]
- 800a88a:	f8b3 2048 	ldrh.w	r2, [r3, #72]	; 0x48
- 800a88e:	687b      	ldr	r3, [r7, #4]
- 800a890:	8e5b      	ldrh	r3, [r3, #50]	; 0x32
- 800a892:	4413      	add	r3, r2
- 800a894:	b29a      	uxth	r2, r3
- 800a896:	687b      	ldr	r3, [r7, #4]
- 800a898:	f8b3 3048 	ldrh.w	r3, [r3, #72]	; 0x48
- 800a89c:	429a      	cmp	r2, r3
- 800a89e:	d30a      	bcc.n	800a8b6 <tcp_receive+0x35a>
- 800a8a0:	687b      	ldr	r3, [r7, #4]
- 800a8a2:	f8b3 2048 	ldrh.w	r2, [r3, #72]	; 0x48
- 800a8a6:	687b      	ldr	r3, [r7, #4]
- 800a8a8:	8e5b      	ldrh	r3, [r3, #50]	; 0x32
- 800a8aa:	4413      	add	r3, r2
- 800a8ac:	b29a      	uxth	r2, r3
- 800a8ae:	687b      	ldr	r3, [r7, #4]
- 800a8b0:	f8a3 2048 	strh.w	r2, [r3, #72]	; 0x48
- 800a8b4:	e004      	b.n	800a8c0 <tcp_receive+0x364>
- 800a8b6:	687b      	ldr	r3, [r7, #4]
- 800a8b8:	f64f 72ff 	movw	r2, #65535	; 0xffff
- 800a8bc:	f8a3 2048 	strh.w	r2, [r3, #72]	; 0x48
-                                    pcb->unacked != NULL ?
-                                    lwip_ntohl(pcb->unacked->tcphdr->seqno) + TCP_TCPLEN(pcb->unacked) : 0));
-
-      /* Remove segment from the unacknowledged list if the incoming
-         ACK acknowledges them. */
-      pcb->unacked = tcp_free_acked_segments(pcb, pcb->unacked, "unacked", pcb->unsent);
- 800a8c0:	687b      	ldr	r3, [r7, #4]
- 800a8c2:	6f19      	ldr	r1, [r3, #112]	; 0x70
- 800a8c4:	687b      	ldr	r3, [r7, #4]
- 800a8c6:	6edb      	ldr	r3, [r3, #108]	; 0x6c
- 800a8c8:	4a98      	ldr	r2, [pc, #608]	; (800ab2c <tcp_receive+0x5d0>)
- 800a8ca:	6878      	ldr	r0, [r7, #4]
- 800a8cc:	f7ff fdca 	bl	800a464 <tcp_free_acked_segments>
- 800a8d0:	4602      	mov	r2, r0
- 800a8d2:	687b      	ldr	r3, [r7, #4]
- 800a8d4:	671a      	str	r2, [r3, #112]	; 0x70
-         on the list are acknowledged by the ACK. This may seem
-         strange since an "unsent" segment shouldn't be acked. The
-         rationale is that lwIP puts all outstanding segments on the
-         ->unsent list after a retransmission, so these segments may
-         in fact have been sent once. */
-      pcb->unsent = tcp_free_acked_segments(pcb, pcb->unsent, "unsent", pcb->unacked);
- 800a8d6:	687b      	ldr	r3, [r7, #4]
- 800a8d8:	6ed9      	ldr	r1, [r3, #108]	; 0x6c
- 800a8da:	687b      	ldr	r3, [r7, #4]
- 800a8dc:	6f1b      	ldr	r3, [r3, #112]	; 0x70
- 800a8de:	4a94      	ldr	r2, [pc, #592]	; (800ab30 <tcp_receive+0x5d4>)
- 800a8e0:	6878      	ldr	r0, [r7, #4]
- 800a8e2:	f7ff fdbf 	bl	800a464 <tcp_free_acked_segments>
- 800a8e6:	4602      	mov	r2, r0
- 800a8e8:	687b      	ldr	r3, [r7, #4]
- 800a8ea:	66da      	str	r2, [r3, #108]	; 0x6c
-
-      /* If there's nothing left to acknowledge, stop the retransmit
-         timer, otherwise reset it to start again */
-      if (pcb->unacked == NULL) {
- 800a8ec:	687b      	ldr	r3, [r7, #4]
- 800a8ee:	6f1b      	ldr	r3, [r3, #112]	; 0x70
- 800a8f0:	2b00      	cmp	r3, #0
- 800a8f2:	d104      	bne.n	800a8fe <tcp_receive+0x3a2>
-        pcb->rtime = -1;
- 800a8f4:	687b      	ldr	r3, [r7, #4]
- 800a8f6:	f64f 72ff 	movw	r2, #65535	; 0xffff
- 800a8fa:	861a      	strh	r2, [r3, #48]	; 0x30
- 800a8fc:	e002      	b.n	800a904 <tcp_receive+0x3a8>
-      } else {
-        pcb->rtime = 0;
- 800a8fe:	687b      	ldr	r3, [r7, #4]
- 800a900:	2200      	movs	r2, #0
- 800a902:	861a      	strh	r2, [r3, #48]	; 0x30
-      }
-
-      pcb->polltmr = 0;
- 800a904:	687b      	ldr	r3, [r7, #4]
- 800a906:	2200      	movs	r2, #0
- 800a908:	771a      	strb	r2, [r3, #28]
-
-#if TCP_OVERSIZE
-      if (pcb->unsent == NULL) {
- 800a90a:	687b      	ldr	r3, [r7, #4]
- 800a90c:	6edb      	ldr	r3, [r3, #108]	; 0x6c
- 800a90e:	2b00      	cmp	r3, #0
- 800a910:	d103      	bne.n	800a91a <tcp_receive+0x3be>
-        pcb->unsent_oversize = 0;
- 800a912:	687b      	ldr	r3, [r7, #4]
- 800a914:	2200      	movs	r2, #0
- 800a916:	f8a3 2068 	strh.w	r2, [r3, #104]	; 0x68
-        /* Inform neighbor reachability of forward progress. */
-        nd6_reachability_hint(ip6_current_src_addr());
-      }
-#endif /* LWIP_IPV6 && LWIP_ND6_TCP_REACHABILITY_HINTS*/
-
-      pcb->snd_buf = (tcpwnd_size_t)(pcb->snd_buf + recv_acked);
- 800a91a:	687b      	ldr	r3, [r7, #4]
- 800a91c:	f8b3 2064 	ldrh.w	r2, [r3, #100]	; 0x64
- 800a920:	4b84      	ldr	r3, [pc, #528]	; (800ab34 <tcp_receive+0x5d8>)
- 800a922:	881b      	ldrh	r3, [r3, #0]
- 800a924:	4413      	add	r3, r2
- 800a926:	b29a      	uxth	r2, r3
- 800a928:	687b      	ldr	r3, [r7, #4]
- 800a92a:	f8a3 2064 	strh.w	r2, [r3, #100]	; 0x64
-      /* check if this ACK ends our retransmission of in-flight data */
-      if (pcb->flags & TF_RTO) {
- 800a92e:	687b      	ldr	r3, [r7, #4]
- 800a930:	8b5b      	ldrh	r3, [r3, #26]
- 800a932:	f403 6300 	and.w	r3, r3, #2048	; 0x800
- 800a936:	2b00      	cmp	r3, #0
- 800a938:	d035      	beq.n	800a9a6 <tcp_receive+0x44a>
-        /* RTO is done if
-            1) both queues are empty or
-            2) unacked is empty and unsent head contains data not part of RTO or
-            3) unacked head contains data not part of RTO */
-        if (pcb->unacked == NULL) {
- 800a93a:	687b      	ldr	r3, [r7, #4]
- 800a93c:	6f1b      	ldr	r3, [r3, #112]	; 0x70
- 800a93e:	2b00      	cmp	r3, #0
- 800a940:	d118      	bne.n	800a974 <tcp_receive+0x418>
-          if ((pcb->unsent == NULL) ||
- 800a942:	687b      	ldr	r3, [r7, #4]
- 800a944:	6edb      	ldr	r3, [r3, #108]	; 0x6c
- 800a946:	2b00      	cmp	r3, #0
- 800a948:	d00c      	beq.n	800a964 <tcp_receive+0x408>
-              (TCP_SEQ_LEQ(pcb->rto_end, lwip_ntohl(pcb->unsent->tcphdr->seqno)))) {
- 800a94a:	687b      	ldr	r3, [r7, #4]
- 800a94c:	6cdc      	ldr	r4, [r3, #76]	; 0x4c
- 800a94e:	687b      	ldr	r3, [r7, #4]
- 800a950:	6edb      	ldr	r3, [r3, #108]	; 0x6c
- 800a952:	691b      	ldr	r3, [r3, #16]
- 800a954:	685b      	ldr	r3, [r3, #4]
- 800a956:	4618      	mov	r0, r3
- 800a958:	f7fa fe0d 	bl	8005576 <lwip_htonl>
- 800a95c:	4603      	mov	r3, r0
- 800a95e:	1ae3      	subs	r3, r4, r3
-          if ((pcb->unsent == NULL) ||
- 800a960:	2b00      	cmp	r3, #0
- 800a962:	dc20      	bgt.n	800a9a6 <tcp_receive+0x44a>
-            tcp_clear_flags(pcb, TF_RTO);
- 800a964:	687b      	ldr	r3, [r7, #4]
- 800a966:	8b5b      	ldrh	r3, [r3, #26]
- 800a968:	f423 6300 	bic.w	r3, r3, #2048	; 0x800
- 800a96c:	b29a      	uxth	r2, r3
- 800a96e:	687b      	ldr	r3, [r7, #4]
- 800a970:	835a      	strh	r2, [r3, #26]
-    } else if (TCP_SEQ_BETWEEN(ackno, pcb->lastack + 1, pcb->snd_nxt)) {
- 800a972:	e018      	b.n	800a9a6 <tcp_receive+0x44a>
-          }
-        } else if (TCP_SEQ_LEQ(pcb->rto_end, lwip_ntohl(pcb->unacked->tcphdr->seqno))) {
- 800a974:	687b      	ldr	r3, [r7, #4]
- 800a976:	6cdc      	ldr	r4, [r3, #76]	; 0x4c
- 800a978:	687b      	ldr	r3, [r7, #4]
- 800a97a:	6f1b      	ldr	r3, [r3, #112]	; 0x70
- 800a97c:	691b      	ldr	r3, [r3, #16]
- 800a97e:	685b      	ldr	r3, [r3, #4]
- 800a980:	4618      	mov	r0, r3
- 800a982:	f7fa fdf8 	bl	8005576 <lwip_htonl>
- 800a986:	4603      	mov	r3, r0
- 800a988:	1ae3      	subs	r3, r4, r3
- 800a98a:	2b00      	cmp	r3, #0
- 800a98c:	dc0b      	bgt.n	800a9a6 <tcp_receive+0x44a>
-          tcp_clear_flags(pcb, TF_RTO);
- 800a98e:	687b      	ldr	r3, [r7, #4]
- 800a990:	8b5b      	ldrh	r3, [r3, #26]
- 800a992:	f423 6300 	bic.w	r3, r3, #2048	; 0x800
- 800a996:	b29a      	uxth	r2, r3
- 800a998:	687b      	ldr	r3, [r7, #4]
- 800a99a:	835a      	strh	r2, [r3, #26]
-    } else if (TCP_SEQ_BETWEEN(ackno, pcb->lastack + 1, pcb->snd_nxt)) {
- 800a99c:	e003      	b.n	800a9a6 <tcp_receive+0x44a>
-        }
-      }
-      /* End of ACK for new data processing. */
-    } else {
-      /* Out of sequence ACK, didn't really ack anything */
-      tcp_send_empty_ack(pcb);
- 800a99e:	6878      	ldr	r0, [r7, #4]
- 800a9a0:	f002 fc3a 	bl	800d218 <tcp_send_empty_ack>
- 800a9a4:	e000      	b.n	800a9a8 <tcp_receive+0x44c>
-    } else if (TCP_SEQ_BETWEEN(ackno, pcb->lastack + 1, pcb->snd_nxt)) {
- 800a9a6:	bf00      	nop
-                                pcb->rttest, pcb->rtseq, ackno));
-
-    /* RTT estimation calculations. This is done by checking if the
-       incoming segment acknowledges the segment we use to take a
-       round-trip time measurement. */
-    if (pcb->rttest && TCP_SEQ_LT(pcb->rtseq, ackno)) {
- 800a9a8:	687b      	ldr	r3, [r7, #4]
- 800a9aa:	6b5b      	ldr	r3, [r3, #52]	; 0x34
- 800a9ac:	2b00      	cmp	r3, #0
- 800a9ae:	d05b      	beq.n	800aa68 <tcp_receive+0x50c>
- 800a9b0:	687b      	ldr	r3, [r7, #4]
- 800a9b2:	6b9a      	ldr	r2, [r3, #56]	; 0x38
- 800a9b4:	4b60      	ldr	r3, [pc, #384]	; (800ab38 <tcp_receive+0x5dc>)
- 800a9b6:	681b      	ldr	r3, [r3, #0]
- 800a9b8:	1ad3      	subs	r3, r2, r3
- 800a9ba:	2b00      	cmp	r3, #0
- 800a9bc:	da54      	bge.n	800aa68 <tcp_receive+0x50c>
-      /* diff between this shouldn't exceed 32K since this are tcp timer ticks
-         and a round-trip shouldn't be that long... */
-      m = (s16_t)(tcp_ticks - pcb->rttest);
- 800a9be:	4b5f      	ldr	r3, [pc, #380]	; (800ab3c <tcp_receive+0x5e0>)
- 800a9c0:	681b      	ldr	r3, [r3, #0]
- 800a9c2:	b29a      	uxth	r2, r3
- 800a9c4:	687b      	ldr	r3, [r7, #4]
- 800a9c6:	6b5b      	ldr	r3, [r3, #52]	; 0x34
- 800a9c8:	b29b      	uxth	r3, r3
- 800a9ca:	1ad3      	subs	r3, r2, r3
- 800a9cc:	b29b      	uxth	r3, r3
- 800a9ce:	f8a7 304e 	strh.w	r3, [r7, #78]	; 0x4e
-
-      LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_receive: experienced rtt %"U16_F" ticks (%"U16_F" msec).\n",
-                                  m, (u16_t)(m * TCP_SLOW_INTERVAL)));
-
-      /* This is taken directly from VJs original code in his paper */
-      m = (s16_t)(m - (pcb->sa >> 3));
- 800a9d2:	f8b7 204e 	ldrh.w	r2, [r7, #78]	; 0x4e
- 800a9d6:	687b      	ldr	r3, [r7, #4]
- 800a9d8:	f9b3 303c 	ldrsh.w	r3, [r3, #60]	; 0x3c
- 800a9dc:	10db      	asrs	r3, r3, #3
- 800a9de:	b21b      	sxth	r3, r3
- 800a9e0:	b29b      	uxth	r3, r3
- 800a9e2:	1ad3      	subs	r3, r2, r3
- 800a9e4:	b29b      	uxth	r3, r3
- 800a9e6:	f8a7 304e 	strh.w	r3, [r7, #78]	; 0x4e
-      pcb->sa = (s16_t)(pcb->sa + m);
- 800a9ea:	687b      	ldr	r3, [r7, #4]
- 800a9ec:	f9b3 303c 	ldrsh.w	r3, [r3, #60]	; 0x3c
- 800a9f0:	b29a      	uxth	r2, r3
- 800a9f2:	f8b7 304e 	ldrh.w	r3, [r7, #78]	; 0x4e
- 800a9f6:	4413      	add	r3, r2
- 800a9f8:	b29b      	uxth	r3, r3
- 800a9fa:	b21a      	sxth	r2, r3
- 800a9fc:	687b      	ldr	r3, [r7, #4]
- 800a9fe:	879a      	strh	r2, [r3, #60]	; 0x3c
-      if (m < 0) {
- 800aa00:	f9b7 304e 	ldrsh.w	r3, [r7, #78]	; 0x4e
- 800aa04:	2b00      	cmp	r3, #0
- 800aa06:	da05      	bge.n	800aa14 <tcp_receive+0x4b8>
-        m = (s16_t) - m;
- 800aa08:	f8b7 304e 	ldrh.w	r3, [r7, #78]	; 0x4e
- 800aa0c:	425b      	negs	r3, r3
- 800aa0e:	b29b      	uxth	r3, r3
- 800aa10:	f8a7 304e 	strh.w	r3, [r7, #78]	; 0x4e
-      }
-      m = (s16_t)(m - (pcb->sv >> 2));
- 800aa14:	f8b7 204e 	ldrh.w	r2, [r7, #78]	; 0x4e
- 800aa18:	687b      	ldr	r3, [r7, #4]
- 800aa1a:	f9b3 303e 	ldrsh.w	r3, [r3, #62]	; 0x3e
- 800aa1e:	109b      	asrs	r3, r3, #2
- 800aa20:	b21b      	sxth	r3, r3
- 800aa22:	b29b      	uxth	r3, r3
- 800aa24:	1ad3      	subs	r3, r2, r3
- 800aa26:	b29b      	uxth	r3, r3
- 800aa28:	f8a7 304e 	strh.w	r3, [r7, #78]	; 0x4e
-      pcb->sv = (s16_t)(pcb->sv + m);
- 800aa2c:	687b      	ldr	r3, [r7, #4]
- 800aa2e:	f9b3 303e 	ldrsh.w	r3, [r3, #62]	; 0x3e
- 800aa32:	b29a      	uxth	r2, r3
- 800aa34:	f8b7 304e 	ldrh.w	r3, [r7, #78]	; 0x4e
- 800aa38:	4413      	add	r3, r2
- 800aa3a:	b29b      	uxth	r3, r3
- 800aa3c:	b21a      	sxth	r2, r3
- 800aa3e:	687b      	ldr	r3, [r7, #4]
- 800aa40:	87da      	strh	r2, [r3, #62]	; 0x3e
-      pcb->rto = (s16_t)((pcb->sa >> 3) + pcb->sv);
- 800aa42:	687b      	ldr	r3, [r7, #4]
- 800aa44:	f9b3 303c 	ldrsh.w	r3, [r3, #60]	; 0x3c
- 800aa48:	10db      	asrs	r3, r3, #3
- 800aa4a:	b21b      	sxth	r3, r3
- 800aa4c:	b29a      	uxth	r2, r3
- 800aa4e:	687b      	ldr	r3, [r7, #4]
- 800aa50:	f9b3 303e 	ldrsh.w	r3, [r3, #62]	; 0x3e
- 800aa54:	b29b      	uxth	r3, r3
- 800aa56:	4413      	add	r3, r2
- 800aa58:	b29b      	uxth	r3, r3
- 800aa5a:	b21a      	sxth	r2, r3
- 800aa5c:	687b      	ldr	r3, [r7, #4]
- 800aa5e:	f8a3 2040 	strh.w	r2, [r3, #64]	; 0x40
-
-      LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_receive: RTO %"U16_F" (%"U16_F" milliseconds)\n",
-                                  pcb->rto, (u16_t)(pcb->rto * TCP_SLOW_INTERVAL)));
-
-      pcb->rttest = 0;
- 800aa62:	687b      	ldr	r3, [r7, #4]
- 800aa64:	2200      	movs	r2, #0
- 800aa66:	635a      	str	r2, [r3, #52]	; 0x34
-
-  /* If the incoming segment contains data, we must process it
-     further unless the pcb already received a FIN.
-     (RFC 793, chapter 3.9, "SEGMENT ARRIVES" in states CLOSE-WAIT, CLOSING,
-     LAST-ACK and TIME-WAIT: "Ignore the segment text.") */
-  if ((tcplen > 0) && (pcb->state < CLOSE_WAIT)) {
- 800aa68:	4b35      	ldr	r3, [pc, #212]	; (800ab40 <tcp_receive+0x5e4>)
- 800aa6a:	881b      	ldrh	r3, [r3, #0]
- 800aa6c:	2b00      	cmp	r3, #0
- 800aa6e:	f000 84e2 	beq.w	800b436 <tcp_receive+0xeda>
- 800aa72:	687b      	ldr	r3, [r7, #4]
- 800aa74:	7d1b      	ldrb	r3, [r3, #20]
- 800aa76:	2b06      	cmp	r3, #6
- 800aa78:	f200 84dd 	bhi.w	800b436 <tcp_receive+0xeda>
-       this if the sequence number of the incoming segment is less
-       than rcv_nxt, and the sequence number plus the length of the
-       segment is larger than rcv_nxt. */
-    /*    if (TCP_SEQ_LT(seqno, pcb->rcv_nxt)) {
-          if (TCP_SEQ_LT(pcb->rcv_nxt, seqno + tcplen)) {*/
-    if (TCP_SEQ_BETWEEN(pcb->rcv_nxt, seqno + 1, seqno + tcplen - 1)) {
- 800aa7c:	687b      	ldr	r3, [r7, #4]
- 800aa7e:	6a5a      	ldr	r2, [r3, #36]	; 0x24
- 800aa80:	4b30      	ldr	r3, [pc, #192]	; (800ab44 <tcp_receive+0x5e8>)
- 800aa82:	681b      	ldr	r3, [r3, #0]
- 800aa84:	1ad3      	subs	r3, r2, r3
- 800aa86:	3b01      	subs	r3, #1
- 800aa88:	2b00      	cmp	r3, #0
- 800aa8a:	f2c0 808f 	blt.w	800abac <tcp_receive+0x650>
- 800aa8e:	687b      	ldr	r3, [r7, #4]
- 800aa90:	6a5a      	ldr	r2, [r3, #36]	; 0x24
- 800aa92:	4b2b      	ldr	r3, [pc, #172]	; (800ab40 <tcp_receive+0x5e4>)
- 800aa94:	881b      	ldrh	r3, [r3, #0]
- 800aa96:	4619      	mov	r1, r3
- 800aa98:	4b2a      	ldr	r3, [pc, #168]	; (800ab44 <tcp_receive+0x5e8>)
- 800aa9a:	681b      	ldr	r3, [r3, #0]
- 800aa9c:	440b      	add	r3, r1
- 800aa9e:	1ad3      	subs	r3, r2, r3
- 800aaa0:	3301      	adds	r3, #1
- 800aaa2:	2b00      	cmp	r3, #0
- 800aaa4:	f300 8082 	bgt.w	800abac <tcp_receive+0x650>
-
-         After we are done with adjusting the pbuf pointers we must
-         adjust the ->data pointer in the seg and the segment
-         length.*/
-
-      struct pbuf *p = inseg.p;
- 800aaa8:	4b27      	ldr	r3, [pc, #156]	; (800ab48 <tcp_receive+0x5ec>)
- 800aaaa:	685b      	ldr	r3, [r3, #4]
- 800aaac:	647b      	str	r3, [r7, #68]	; 0x44
-      u32_t off32 = pcb->rcv_nxt - seqno;
- 800aaae:	687b      	ldr	r3, [r7, #4]
- 800aab0:	6a5a      	ldr	r2, [r3, #36]	; 0x24
- 800aab2:	4b24      	ldr	r3, [pc, #144]	; (800ab44 <tcp_receive+0x5e8>)
- 800aab4:	681b      	ldr	r3, [r3, #0]
- 800aab6:	1ad3      	subs	r3, r2, r3
- 800aab8:	627b      	str	r3, [r7, #36]	; 0x24
-      u16_t new_tot_len, off;
-      LWIP_ASSERT("inseg.p != NULL", inseg.p);
- 800aaba:	4b23      	ldr	r3, [pc, #140]	; (800ab48 <tcp_receive+0x5ec>)
- 800aabc:	685b      	ldr	r3, [r3, #4]
- 800aabe:	2b00      	cmp	r3, #0
- 800aac0:	d106      	bne.n	800aad0 <tcp_receive+0x574>
- 800aac2:	4b22      	ldr	r3, [pc, #136]	; (800ab4c <tcp_receive+0x5f0>)
- 800aac4:	f240 5294 	movw	r2, #1428	; 0x594
- 800aac8:	4921      	ldr	r1, [pc, #132]	; (800ab50 <tcp_receive+0x5f4>)
- 800aaca:	4822      	ldr	r0, [pc, #136]	; (800ab54 <tcp_receive+0x5f8>)
- 800aacc:	f006 f87c 	bl	8010bc8 <iprintf>
-      LWIP_ASSERT("insane offset!", (off32 < 0xffff));
- 800aad0:	6a7b      	ldr	r3, [r7, #36]	; 0x24
- 800aad2:	f64f 72fe 	movw	r2, #65534	; 0xfffe
- 800aad6:	4293      	cmp	r3, r2
- 800aad8:	d906      	bls.n	800aae8 <tcp_receive+0x58c>
- 800aada:	4b1c      	ldr	r3, [pc, #112]	; (800ab4c <tcp_receive+0x5f0>)
- 800aadc:	f240 5295 	movw	r2, #1429	; 0x595
- 800aae0:	491d      	ldr	r1, [pc, #116]	; (800ab58 <tcp_receive+0x5fc>)
- 800aae2:	481c      	ldr	r0, [pc, #112]	; (800ab54 <tcp_receive+0x5f8>)
- 800aae4:	f006 f870 	bl	8010bc8 <iprintf>
-      off = (u16_t)off32;
- 800aae8:	6a7b      	ldr	r3, [r7, #36]	; 0x24
- 800aaea:	f8a7 3042 	strh.w	r3, [r7, #66]	; 0x42
-      LWIP_ASSERT("pbuf too short!", (((s32_t)inseg.p->tot_len) >= off));
- 800aaee:	4b16      	ldr	r3, [pc, #88]	; (800ab48 <tcp_receive+0x5ec>)
- 800aaf0:	685b      	ldr	r3, [r3, #4]
- 800aaf2:	891b      	ldrh	r3, [r3, #8]
- 800aaf4:	f8b7 2042 	ldrh.w	r2, [r7, #66]	; 0x42
- 800aaf8:	429a      	cmp	r2, r3
- 800aafa:	d906      	bls.n	800ab0a <tcp_receive+0x5ae>
- 800aafc:	4b13      	ldr	r3, [pc, #76]	; (800ab4c <tcp_receive+0x5f0>)
- 800aafe:	f240 5297 	movw	r2, #1431	; 0x597
- 800ab02:	4916      	ldr	r1, [pc, #88]	; (800ab5c <tcp_receive+0x600>)
- 800ab04:	4813      	ldr	r0, [pc, #76]	; (800ab54 <tcp_receive+0x5f8>)
- 800ab06:	f006 f85f 	bl	8010bc8 <iprintf>
-      inseg.len -= off;
- 800ab0a:	4b0f      	ldr	r3, [pc, #60]	; (800ab48 <tcp_receive+0x5ec>)
- 800ab0c:	891a      	ldrh	r2, [r3, #8]
- 800ab0e:	f8b7 3042 	ldrh.w	r3, [r7, #66]	; 0x42
- 800ab12:	1ad3      	subs	r3, r2, r3
- 800ab14:	b29a      	uxth	r2, r3
- 800ab16:	4b0c      	ldr	r3, [pc, #48]	; (800ab48 <tcp_receive+0x5ec>)
- 800ab18:	811a      	strh	r2, [r3, #8]
-      new_tot_len = (u16_t)(inseg.p->tot_len - off);
- 800ab1a:	4b0b      	ldr	r3, [pc, #44]	; (800ab48 <tcp_receive+0x5ec>)
- 800ab1c:	685b      	ldr	r3, [r3, #4]
- 800ab1e:	891a      	ldrh	r2, [r3, #8]
- 800ab20:	f8b7 3042 	ldrh.w	r3, [r7, #66]	; 0x42
- 800ab24:	1ad3      	subs	r3, r2, r3
- 800ab26:	847b      	strh	r3, [r7, #34]	; 0x22
-      while (p->len < off) {
- 800ab28:	e02a      	b.n	800ab80 <tcp_receive+0x624>
- 800ab2a:	bf00      	nop
- 800ab2c:	08013500 	.word	0x08013500
- 800ab30:	08013508 	.word	0x08013508
- 800ab34:	24007bb0 	.word	0x24007bb0
- 800ab38:	24007bac 	.word	0x24007bac
- 800ab3c:	24007b6c 	.word	0x24007b6c
- 800ab40:	24007bb2 	.word	0x24007bb2
- 800ab44:	24007ba8 	.word	0x24007ba8
- 800ab48:	24007b84 	.word	0x24007b84
- 800ab4c:	08013198 	.word	0x08013198
- 800ab50:	08013510 	.word	0x08013510
- 800ab54:	080131e4 	.word	0x080131e4
- 800ab58:	08013520 	.word	0x08013520
- 800ab5c:	08013530 	.word	0x08013530
-        off -= p->len;
- 800ab60:	6c7b      	ldr	r3, [r7, #68]	; 0x44
- 800ab62:	895b      	ldrh	r3, [r3, #10]
- 800ab64:	f8b7 2042 	ldrh.w	r2, [r7, #66]	; 0x42
- 800ab68:	1ad3      	subs	r3, r2, r3
- 800ab6a:	f8a7 3042 	strh.w	r3, [r7, #66]	; 0x42
-        /* all pbufs up to and including this one have len==0, so tot_len is equal */
-        p->tot_len = new_tot_len;
- 800ab6e:	6c7b      	ldr	r3, [r7, #68]	; 0x44
- 800ab70:	8c7a      	ldrh	r2, [r7, #34]	; 0x22
- 800ab72:	811a      	strh	r2, [r3, #8]
-        p->len = 0;
- 800ab74:	6c7b      	ldr	r3, [r7, #68]	; 0x44
- 800ab76:	2200      	movs	r2, #0
- 800ab78:	815a      	strh	r2, [r3, #10]
-        p = p->next;
- 800ab7a:	6c7b      	ldr	r3, [r7, #68]	; 0x44
- 800ab7c:	681b      	ldr	r3, [r3, #0]
- 800ab7e:	647b      	str	r3, [r7, #68]	; 0x44
-      while (p->len < off) {
- 800ab80:	6c7b      	ldr	r3, [r7, #68]	; 0x44
- 800ab82:	895b      	ldrh	r3, [r3, #10]
- 800ab84:	f8b7 2042 	ldrh.w	r2, [r7, #66]	; 0x42
- 800ab88:	429a      	cmp	r2, r3
- 800ab8a:	d8e9      	bhi.n	800ab60 <tcp_receive+0x604>
-      }
-      /* cannot fail... */
-      pbuf_remove_header(p, off);
- 800ab8c:	f8b7 3042 	ldrh.w	r3, [r7, #66]	; 0x42
- 800ab90:	4619      	mov	r1, r3
- 800ab92:	6c78      	ldr	r0, [r7, #68]	; 0x44
- 800ab94:	f7fc f998 	bl	8006ec8 <pbuf_remove_header>
-      inseg.tcphdr->seqno = seqno = pcb->rcv_nxt;
- 800ab98:	687b      	ldr	r3, [r7, #4]
- 800ab9a:	6a5b      	ldr	r3, [r3, #36]	; 0x24
- 800ab9c:	4a91      	ldr	r2, [pc, #580]	; (800ade4 <tcp_receive+0x888>)
- 800ab9e:	6013      	str	r3, [r2, #0]
- 800aba0:	4b91      	ldr	r3, [pc, #580]	; (800ade8 <tcp_receive+0x88c>)
- 800aba2:	691b      	ldr	r3, [r3, #16]
- 800aba4:	4a8f      	ldr	r2, [pc, #572]	; (800ade4 <tcp_receive+0x888>)
- 800aba6:	6812      	ldr	r2, [r2, #0]
- 800aba8:	605a      	str	r2, [r3, #4]
-    if (TCP_SEQ_BETWEEN(pcb->rcv_nxt, seqno + 1, seqno + tcplen - 1)) {
- 800abaa:	e00d      	b.n	800abc8 <tcp_receive+0x66c>
-    } else {
-      if (TCP_SEQ_LT(seqno, pcb->rcv_nxt)) {
- 800abac:	4b8d      	ldr	r3, [pc, #564]	; (800ade4 <tcp_receive+0x888>)
- 800abae:	681a      	ldr	r2, [r3, #0]
- 800abb0:	687b      	ldr	r3, [r7, #4]
- 800abb2:	6a5b      	ldr	r3, [r3, #36]	; 0x24
- 800abb4:	1ad3      	subs	r3, r2, r3
- 800abb6:	2b00      	cmp	r3, #0
- 800abb8:	da06      	bge.n	800abc8 <tcp_receive+0x66c>
-        /* the whole segment is < rcv_nxt */
-        /* must be a duplicate of a packet that has already been correctly handled */
-
-        LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: duplicate seqno %"U32_F"\n", seqno));
-        tcp_ack_now(pcb);
- 800abba:	687b      	ldr	r3, [r7, #4]
- 800abbc:	8b5b      	ldrh	r3, [r3, #26]
- 800abbe:	f043 0302 	orr.w	r3, r3, #2
- 800abc2:	b29a      	uxth	r2, r3
- 800abc4:	687b      	ldr	r3, [r7, #4]
- 800abc6:	835a      	strh	r2, [r3, #26]
-    }
-
-    /* The sequence number must be within the window (above rcv_nxt
-       and below rcv_nxt + rcv_wnd) in order to be further
-       processed. */
-    if (TCP_SEQ_BETWEEN(seqno, pcb->rcv_nxt,
- 800abc8:	4b86      	ldr	r3, [pc, #536]	; (800ade4 <tcp_receive+0x888>)
- 800abca:	681a      	ldr	r2, [r3, #0]
- 800abcc:	687b      	ldr	r3, [r7, #4]
- 800abce:	6a5b      	ldr	r3, [r3, #36]	; 0x24
- 800abd0:	1ad3      	subs	r3, r2, r3
- 800abd2:	2b00      	cmp	r3, #0
- 800abd4:	f2c0 842a 	blt.w	800b42c <tcp_receive+0xed0>
- 800abd8:	4b82      	ldr	r3, [pc, #520]	; (800ade4 <tcp_receive+0x888>)
- 800abda:	681a      	ldr	r2, [r3, #0]
- 800abdc:	687b      	ldr	r3, [r7, #4]
- 800abde:	6a5b      	ldr	r3, [r3, #36]	; 0x24
- 800abe0:	6879      	ldr	r1, [r7, #4]
- 800abe2:	8d09      	ldrh	r1, [r1, #40]	; 0x28
- 800abe4:	440b      	add	r3, r1
- 800abe6:	1ad3      	subs	r3, r2, r3
- 800abe8:	3301      	adds	r3, #1
- 800abea:	2b00      	cmp	r3, #0
- 800abec:	f300 841e 	bgt.w	800b42c <tcp_receive+0xed0>
-                        pcb->rcv_nxt + pcb->rcv_wnd - 1)) {
-      if (pcb->rcv_nxt == seqno) {
- 800abf0:	687b      	ldr	r3, [r7, #4]
- 800abf2:	6a5a      	ldr	r2, [r3, #36]	; 0x24
- 800abf4:	4b7b      	ldr	r3, [pc, #492]	; (800ade4 <tcp_receive+0x888>)
- 800abf6:	681b      	ldr	r3, [r3, #0]
- 800abf8:	429a      	cmp	r2, r3
- 800abfa:	f040 829a 	bne.w	800b132 <tcp_receive+0xbd6>
-        /* The incoming segment is the next in sequence. We check if
-           we have to trim the end of the segment and update rcv_nxt
-           and pass the data to the application. */
-        tcplen = TCP_TCPLEN(&inseg);
- 800abfe:	4b7a      	ldr	r3, [pc, #488]	; (800ade8 <tcp_receive+0x88c>)
- 800ac00:	891c      	ldrh	r4, [r3, #8]
- 800ac02:	4b79      	ldr	r3, [pc, #484]	; (800ade8 <tcp_receive+0x88c>)
- 800ac04:	691b      	ldr	r3, [r3, #16]
- 800ac06:	899b      	ldrh	r3, [r3, #12]
- 800ac08:	b29b      	uxth	r3, r3
- 800ac0a:	4618      	mov	r0, r3
- 800ac0c:	f7fa fc9e 	bl	800554c <lwip_htons>
- 800ac10:	4603      	mov	r3, r0
- 800ac12:	b2db      	uxtb	r3, r3
- 800ac14:	f003 0303 	and.w	r3, r3, #3
- 800ac18:	2b00      	cmp	r3, #0
- 800ac1a:	d001      	beq.n	800ac20 <tcp_receive+0x6c4>
- 800ac1c:	2301      	movs	r3, #1
- 800ac1e:	e000      	b.n	800ac22 <tcp_receive+0x6c6>
- 800ac20:	2300      	movs	r3, #0
- 800ac22:	4423      	add	r3, r4
- 800ac24:	b29a      	uxth	r2, r3
- 800ac26:	4b71      	ldr	r3, [pc, #452]	; (800adec <tcp_receive+0x890>)
- 800ac28:	801a      	strh	r2, [r3, #0]
-
-        if (tcplen > pcb->rcv_wnd) {
- 800ac2a:	687b      	ldr	r3, [r7, #4]
- 800ac2c:	8d1a      	ldrh	r2, [r3, #40]	; 0x28
- 800ac2e:	4b6f      	ldr	r3, [pc, #444]	; (800adec <tcp_receive+0x890>)
- 800ac30:	881b      	ldrh	r3, [r3, #0]
- 800ac32:	429a      	cmp	r2, r3
- 800ac34:	d275      	bcs.n	800ad22 <tcp_receive+0x7c6>
-          LWIP_DEBUGF(TCP_INPUT_DEBUG,
-                      ("tcp_receive: other end overran receive window"
-                       "seqno %"U32_F" len %"U16_F" right edge %"U32_F"\n",
-                       seqno, tcplen, pcb->rcv_nxt + pcb->rcv_wnd));
-          if (TCPH_FLAGS(inseg.tcphdr) & TCP_FIN) {
- 800ac36:	4b6c      	ldr	r3, [pc, #432]	; (800ade8 <tcp_receive+0x88c>)
- 800ac38:	691b      	ldr	r3, [r3, #16]
- 800ac3a:	899b      	ldrh	r3, [r3, #12]
- 800ac3c:	b29b      	uxth	r3, r3
- 800ac3e:	4618      	mov	r0, r3
- 800ac40:	f7fa fc84 	bl	800554c <lwip_htons>
- 800ac44:	4603      	mov	r3, r0
- 800ac46:	b2db      	uxtb	r3, r3
- 800ac48:	f003 0301 	and.w	r3, r3, #1
- 800ac4c:	2b00      	cmp	r3, #0
- 800ac4e:	d01f      	beq.n	800ac90 <tcp_receive+0x734>
-            /* Must remove the FIN from the header as we're trimming
-             * that byte of sequence-space from the packet */
-            TCPH_FLAGS_SET(inseg.tcphdr, TCPH_FLAGS(inseg.tcphdr) & ~(unsigned int)TCP_FIN);
- 800ac50:	4b65      	ldr	r3, [pc, #404]	; (800ade8 <tcp_receive+0x88c>)
- 800ac52:	691b      	ldr	r3, [r3, #16]
- 800ac54:	899b      	ldrh	r3, [r3, #12]
- 800ac56:	b29b      	uxth	r3, r3
- 800ac58:	b21b      	sxth	r3, r3
- 800ac5a:	f423 537c 	bic.w	r3, r3, #16128	; 0x3f00
- 800ac5e:	b21c      	sxth	r4, r3
- 800ac60:	4b61      	ldr	r3, [pc, #388]	; (800ade8 <tcp_receive+0x88c>)
- 800ac62:	691b      	ldr	r3, [r3, #16]
- 800ac64:	899b      	ldrh	r3, [r3, #12]
- 800ac66:	b29b      	uxth	r3, r3
- 800ac68:	4618      	mov	r0, r3
- 800ac6a:	f7fa fc6f 	bl	800554c <lwip_htons>
- 800ac6e:	4603      	mov	r3, r0
- 800ac70:	b2db      	uxtb	r3, r3
- 800ac72:	b29b      	uxth	r3, r3
- 800ac74:	f003 033e 	and.w	r3, r3, #62	; 0x3e
- 800ac78:	b29b      	uxth	r3, r3
- 800ac7a:	4618      	mov	r0, r3
- 800ac7c:	f7fa fc66 	bl	800554c <lwip_htons>
- 800ac80:	4603      	mov	r3, r0
- 800ac82:	b21b      	sxth	r3, r3
- 800ac84:	4323      	orrs	r3, r4
- 800ac86:	b21a      	sxth	r2, r3
- 800ac88:	4b57      	ldr	r3, [pc, #348]	; (800ade8 <tcp_receive+0x88c>)
- 800ac8a:	691b      	ldr	r3, [r3, #16]
- 800ac8c:	b292      	uxth	r2, r2
- 800ac8e:	819a      	strh	r2, [r3, #12]
-          }
-          /* Adjust length of segment to fit in the window. */
-          TCPWND_CHECK16(pcb->rcv_wnd);
-          inseg.len = (u16_t)pcb->rcv_wnd;
- 800ac90:	687b      	ldr	r3, [r7, #4]
- 800ac92:	8d1a      	ldrh	r2, [r3, #40]	; 0x28
- 800ac94:	4b54      	ldr	r3, [pc, #336]	; (800ade8 <tcp_receive+0x88c>)
- 800ac96:	811a      	strh	r2, [r3, #8]
-          if (TCPH_FLAGS(inseg.tcphdr) & TCP_SYN) {
- 800ac98:	4b53      	ldr	r3, [pc, #332]	; (800ade8 <tcp_receive+0x88c>)
- 800ac9a:	691b      	ldr	r3, [r3, #16]
- 800ac9c:	899b      	ldrh	r3, [r3, #12]
- 800ac9e:	b29b      	uxth	r3, r3
- 800aca0:	4618      	mov	r0, r3
- 800aca2:	f7fa fc53 	bl	800554c <lwip_htons>
- 800aca6:	4603      	mov	r3, r0
- 800aca8:	b2db      	uxtb	r3, r3
- 800acaa:	f003 0302 	and.w	r3, r3, #2
- 800acae:	2b00      	cmp	r3, #0
- 800acb0:	d005      	beq.n	800acbe <tcp_receive+0x762>
-            inseg.len -= 1;
- 800acb2:	4b4d      	ldr	r3, [pc, #308]	; (800ade8 <tcp_receive+0x88c>)
- 800acb4:	891b      	ldrh	r3, [r3, #8]
- 800acb6:	3b01      	subs	r3, #1
- 800acb8:	b29a      	uxth	r2, r3
- 800acba:	4b4b      	ldr	r3, [pc, #300]	; (800ade8 <tcp_receive+0x88c>)
- 800acbc:	811a      	strh	r2, [r3, #8]
-          }
-          pbuf_realloc(inseg.p, inseg.len);
- 800acbe:	4b4a      	ldr	r3, [pc, #296]	; (800ade8 <tcp_receive+0x88c>)
- 800acc0:	685b      	ldr	r3, [r3, #4]
- 800acc2:	4a49      	ldr	r2, [pc, #292]	; (800ade8 <tcp_receive+0x88c>)
- 800acc4:	8912      	ldrh	r2, [r2, #8]
- 800acc6:	4611      	mov	r1, r2
- 800acc8:	4618      	mov	r0, r3
- 800acca:	f7fb fffd 	bl	8006cc8 <pbuf_realloc>
-          tcplen = TCP_TCPLEN(&inseg);
- 800acce:	4b46      	ldr	r3, [pc, #280]	; (800ade8 <tcp_receive+0x88c>)
- 800acd0:	891c      	ldrh	r4, [r3, #8]
- 800acd2:	4b45      	ldr	r3, [pc, #276]	; (800ade8 <tcp_receive+0x88c>)
- 800acd4:	691b      	ldr	r3, [r3, #16]
- 800acd6:	899b      	ldrh	r3, [r3, #12]
- 800acd8:	b29b      	uxth	r3, r3
- 800acda:	4618      	mov	r0, r3
- 800acdc:	f7fa fc36 	bl	800554c <lwip_htons>
- 800ace0:	4603      	mov	r3, r0
- 800ace2:	b2db      	uxtb	r3, r3
- 800ace4:	f003 0303 	and.w	r3, r3, #3
- 800ace8:	2b00      	cmp	r3, #0
- 800acea:	d001      	beq.n	800acf0 <tcp_receive+0x794>
- 800acec:	2301      	movs	r3, #1
- 800acee:	e000      	b.n	800acf2 <tcp_receive+0x796>
- 800acf0:	2300      	movs	r3, #0
- 800acf2:	4423      	add	r3, r4
- 800acf4:	b29a      	uxth	r2, r3
- 800acf6:	4b3d      	ldr	r3, [pc, #244]	; (800adec <tcp_receive+0x890>)
- 800acf8:	801a      	strh	r2, [r3, #0]
-          LWIP_ASSERT("tcp_receive: segment not trimmed correctly to rcv_wnd\n",
- 800acfa:	4b3c      	ldr	r3, [pc, #240]	; (800adec <tcp_receive+0x890>)
- 800acfc:	881b      	ldrh	r3, [r3, #0]
- 800acfe:	461a      	mov	r2, r3
- 800ad00:	4b38      	ldr	r3, [pc, #224]	; (800ade4 <tcp_receive+0x888>)
- 800ad02:	681b      	ldr	r3, [r3, #0]
- 800ad04:	441a      	add	r2, r3
- 800ad06:	687b      	ldr	r3, [r7, #4]
- 800ad08:	6a5b      	ldr	r3, [r3, #36]	; 0x24
- 800ad0a:	6879      	ldr	r1, [r7, #4]
- 800ad0c:	8d09      	ldrh	r1, [r1, #40]	; 0x28
- 800ad0e:	440b      	add	r3, r1
- 800ad10:	429a      	cmp	r2, r3
- 800ad12:	d006      	beq.n	800ad22 <tcp_receive+0x7c6>
- 800ad14:	4b36      	ldr	r3, [pc, #216]	; (800adf0 <tcp_receive+0x894>)
- 800ad16:	f240 52cb 	movw	r2, #1483	; 0x5cb
- 800ad1a:	4936      	ldr	r1, [pc, #216]	; (800adf4 <tcp_receive+0x898>)
- 800ad1c:	4836      	ldr	r0, [pc, #216]	; (800adf8 <tcp_receive+0x89c>)
- 800ad1e:	f005 ff53 	bl	8010bc8 <iprintf>
-        }
-#if TCP_QUEUE_OOSEQ
-        /* Received in-sequence data, adjust ooseq data if:
-           - FIN has been received or
-           - inseq overlaps with ooseq */
-        if (pcb->ooseq != NULL) {
- 800ad22:	687b      	ldr	r3, [r7, #4]
- 800ad24:	6f5b      	ldr	r3, [r3, #116]	; 0x74
- 800ad26:	2b00      	cmp	r3, #0
- 800ad28:	f000 80e7 	beq.w	800aefa <tcp_receive+0x99e>
-          if (TCPH_FLAGS(inseg.tcphdr) & TCP_FIN) {
- 800ad2c:	4b2e      	ldr	r3, [pc, #184]	; (800ade8 <tcp_receive+0x88c>)
- 800ad2e:	691b      	ldr	r3, [r3, #16]
- 800ad30:	899b      	ldrh	r3, [r3, #12]
- 800ad32:	b29b      	uxth	r3, r3
- 800ad34:	4618      	mov	r0, r3
- 800ad36:	f7fa fc09 	bl	800554c <lwip_htons>
- 800ad3a:	4603      	mov	r3, r0
- 800ad3c:	b2db      	uxtb	r3, r3
- 800ad3e:	f003 0301 	and.w	r3, r3, #1
- 800ad42:	2b00      	cmp	r3, #0
- 800ad44:	d010      	beq.n	800ad68 <tcp_receive+0x80c>
-            LWIP_DEBUGF(TCP_INPUT_DEBUG,
-                        ("tcp_receive: received in-order FIN, binning ooseq queue\n"));
-            /* Received in-order FIN means anything that was received
-             * out of order must now have been received in-order, so
-             * bin the ooseq queue */
-            while (pcb->ooseq != NULL) {
- 800ad46:	e00a      	b.n	800ad5e <tcp_receive+0x802>
-              struct tcp_seg *old_ooseq = pcb->ooseq;
- 800ad48:	687b      	ldr	r3, [r7, #4]
- 800ad4a:	6f5b      	ldr	r3, [r3, #116]	; 0x74
- 800ad4c:	60fb      	str	r3, [r7, #12]
-              pcb->ooseq = pcb->ooseq->next;
- 800ad4e:	687b      	ldr	r3, [r7, #4]
- 800ad50:	6f5b      	ldr	r3, [r3, #116]	; 0x74
- 800ad52:	681a      	ldr	r2, [r3, #0]
- 800ad54:	687b      	ldr	r3, [r7, #4]
- 800ad56:	675a      	str	r2, [r3, #116]	; 0x74
-              tcp_seg_free(old_ooseq);
- 800ad58:	68f8      	ldr	r0, [r7, #12]
- 800ad5a:	f7fd fd0c 	bl	8008776 <tcp_seg_free>
-            while (pcb->ooseq != NULL) {
- 800ad5e:	687b      	ldr	r3, [r7, #4]
- 800ad60:	6f5b      	ldr	r3, [r3, #116]	; 0x74
- 800ad62:	2b00      	cmp	r3, #0
- 800ad64:	d1f0      	bne.n	800ad48 <tcp_receive+0x7ec>
- 800ad66:	e0c8      	b.n	800aefa <tcp_receive+0x99e>
-            }
-          } else {
-            struct tcp_seg *next = pcb->ooseq;
- 800ad68:	687b      	ldr	r3, [r7, #4]
- 800ad6a:	6f5b      	ldr	r3, [r3, #116]	; 0x74
- 800ad6c:	63fb      	str	r3, [r7, #60]	; 0x3c
-            /* Remove all segments on ooseq that are covered by inseg already.
-             * FIN is copied from ooseq to inseg if present. */
-            while (next &&
- 800ad6e:	e052      	b.n	800ae16 <tcp_receive+0x8ba>
-                   TCP_SEQ_GEQ(seqno + tcplen,
-                               next->tcphdr->seqno + next->len)) {
-              struct tcp_seg *tmp;
-              /* inseg cannot have FIN here (already processed above) */
-              if ((TCPH_FLAGS(next->tcphdr) & TCP_FIN) != 0 &&
- 800ad70:	6bfb      	ldr	r3, [r7, #60]	; 0x3c
- 800ad72:	691b      	ldr	r3, [r3, #16]
- 800ad74:	899b      	ldrh	r3, [r3, #12]
- 800ad76:	b29b      	uxth	r3, r3
- 800ad78:	4618      	mov	r0, r3
- 800ad7a:	f7fa fbe7 	bl	800554c <lwip_htons>
- 800ad7e:	4603      	mov	r3, r0
- 800ad80:	b2db      	uxtb	r3, r3
- 800ad82:	f003 0301 	and.w	r3, r3, #1
- 800ad86:	2b00      	cmp	r3, #0
- 800ad88:	d03d      	beq.n	800ae06 <tcp_receive+0x8aa>
-                  (TCPH_FLAGS(inseg.tcphdr) & TCP_SYN) == 0) {
- 800ad8a:	4b17      	ldr	r3, [pc, #92]	; (800ade8 <tcp_receive+0x88c>)
- 800ad8c:	691b      	ldr	r3, [r3, #16]
- 800ad8e:	899b      	ldrh	r3, [r3, #12]
- 800ad90:	b29b      	uxth	r3, r3
- 800ad92:	4618      	mov	r0, r3
- 800ad94:	f7fa fbda 	bl	800554c <lwip_htons>
- 800ad98:	4603      	mov	r3, r0
- 800ad9a:	b2db      	uxtb	r3, r3
- 800ad9c:	f003 0302 	and.w	r3, r3, #2
-              if ((TCPH_FLAGS(next->tcphdr) & TCP_FIN) != 0 &&
- 800ada0:	2b00      	cmp	r3, #0
- 800ada2:	d130      	bne.n	800ae06 <tcp_receive+0x8aa>
-                TCPH_SET_FLAG(inseg.tcphdr, TCP_FIN);
- 800ada4:	4b10      	ldr	r3, [pc, #64]	; (800ade8 <tcp_receive+0x88c>)
- 800ada6:	691b      	ldr	r3, [r3, #16]
- 800ada8:	899b      	ldrh	r3, [r3, #12]
- 800adaa:	b29c      	uxth	r4, r3
- 800adac:	2001      	movs	r0, #1
- 800adae:	f7fa fbcd 	bl	800554c <lwip_htons>
- 800adb2:	4603      	mov	r3, r0
- 800adb4:	461a      	mov	r2, r3
- 800adb6:	4b0c      	ldr	r3, [pc, #48]	; (800ade8 <tcp_receive+0x88c>)
- 800adb8:	691b      	ldr	r3, [r3, #16]
- 800adba:	4322      	orrs	r2, r4
- 800adbc:	b292      	uxth	r2, r2
- 800adbe:	819a      	strh	r2, [r3, #12]
-                tcplen = TCP_TCPLEN(&inseg);
- 800adc0:	4b09      	ldr	r3, [pc, #36]	; (800ade8 <tcp_receive+0x88c>)
- 800adc2:	891c      	ldrh	r4, [r3, #8]
- 800adc4:	4b08      	ldr	r3, [pc, #32]	; (800ade8 <tcp_receive+0x88c>)
- 800adc6:	691b      	ldr	r3, [r3, #16]
- 800adc8:	899b      	ldrh	r3, [r3, #12]
- 800adca:	b29b      	uxth	r3, r3
- 800adcc:	4618      	mov	r0, r3
- 800adce:	f7fa fbbd 	bl	800554c <lwip_htons>
- 800add2:	4603      	mov	r3, r0
- 800add4:	b2db      	uxtb	r3, r3
- 800add6:	f003 0303 	and.w	r3, r3, #3
- 800adda:	2b00      	cmp	r3, #0
- 800addc:	d00e      	beq.n	800adfc <tcp_receive+0x8a0>
- 800adde:	2301      	movs	r3, #1
- 800ade0:	e00d      	b.n	800adfe <tcp_receive+0x8a2>
- 800ade2:	bf00      	nop
- 800ade4:	24007ba8 	.word	0x24007ba8
- 800ade8:	24007b84 	.word	0x24007b84
- 800adec:	24007bb2 	.word	0x24007bb2
- 800adf0:	08013198 	.word	0x08013198
- 800adf4:	08013540 	.word	0x08013540
- 800adf8:	080131e4 	.word	0x080131e4
- 800adfc:	2300      	movs	r3, #0
- 800adfe:	4423      	add	r3, r4
- 800ae00:	b29a      	uxth	r2, r3
- 800ae02:	4b98      	ldr	r3, [pc, #608]	; (800b064 <tcp_receive+0xb08>)
- 800ae04:	801a      	strh	r2, [r3, #0]
-              }
-              tmp = next;
- 800ae06:	6bfb      	ldr	r3, [r7, #60]	; 0x3c
- 800ae08:	613b      	str	r3, [r7, #16]
-              next = next->next;
- 800ae0a:	6bfb      	ldr	r3, [r7, #60]	; 0x3c
- 800ae0c:	681b      	ldr	r3, [r3, #0]
- 800ae0e:	63fb      	str	r3, [r7, #60]	; 0x3c
-              tcp_seg_free(tmp);
- 800ae10:	6938      	ldr	r0, [r7, #16]
- 800ae12:	f7fd fcb0 	bl	8008776 <tcp_seg_free>
-            while (next &&
- 800ae16:	6bfb      	ldr	r3, [r7, #60]	; 0x3c
- 800ae18:	2b00      	cmp	r3, #0
- 800ae1a:	d00e      	beq.n	800ae3a <tcp_receive+0x8de>
-                   TCP_SEQ_GEQ(seqno + tcplen,
- 800ae1c:	4b91      	ldr	r3, [pc, #580]	; (800b064 <tcp_receive+0xb08>)
- 800ae1e:	881b      	ldrh	r3, [r3, #0]
- 800ae20:	461a      	mov	r2, r3
- 800ae22:	4b91      	ldr	r3, [pc, #580]	; (800b068 <tcp_receive+0xb0c>)
- 800ae24:	681b      	ldr	r3, [r3, #0]
- 800ae26:	441a      	add	r2, r3
- 800ae28:	6bfb      	ldr	r3, [r7, #60]	; 0x3c
- 800ae2a:	691b      	ldr	r3, [r3, #16]
- 800ae2c:	685b      	ldr	r3, [r3, #4]
- 800ae2e:	6bf9      	ldr	r1, [r7, #60]	; 0x3c
- 800ae30:	8909      	ldrh	r1, [r1, #8]
- 800ae32:	440b      	add	r3, r1
- 800ae34:	1ad3      	subs	r3, r2, r3
-            while (next &&
- 800ae36:	2b00      	cmp	r3, #0
- 800ae38:	da9a      	bge.n	800ad70 <tcp_receive+0x814>
-            }
-            /* Now trim right side of inseg if it overlaps with the first
-             * segment on ooseq */
-            if (next &&
- 800ae3a:	6bfb      	ldr	r3, [r7, #60]	; 0x3c
- 800ae3c:	2b00      	cmp	r3, #0
- 800ae3e:	d059      	beq.n	800aef4 <tcp_receive+0x998>
-                TCP_SEQ_GT(seqno + tcplen,
- 800ae40:	4b88      	ldr	r3, [pc, #544]	; (800b064 <tcp_receive+0xb08>)
- 800ae42:	881b      	ldrh	r3, [r3, #0]
- 800ae44:	461a      	mov	r2, r3
- 800ae46:	4b88      	ldr	r3, [pc, #544]	; (800b068 <tcp_receive+0xb0c>)
- 800ae48:	681b      	ldr	r3, [r3, #0]
- 800ae4a:	441a      	add	r2, r3
- 800ae4c:	6bfb      	ldr	r3, [r7, #60]	; 0x3c
- 800ae4e:	691b      	ldr	r3, [r3, #16]
- 800ae50:	685b      	ldr	r3, [r3, #4]
- 800ae52:	1ad3      	subs	r3, r2, r3
-            if (next &&
- 800ae54:	2b00      	cmp	r3, #0
- 800ae56:	dd4d      	ble.n	800aef4 <tcp_receive+0x998>
-                           next->tcphdr->seqno)) {
-              /* inseg cannot have FIN here (already processed above) */
-              inseg.len = (u16_t)(next->tcphdr->seqno - seqno);
- 800ae58:	6bfb      	ldr	r3, [r7, #60]	; 0x3c
- 800ae5a:	691b      	ldr	r3, [r3, #16]
- 800ae5c:	685b      	ldr	r3, [r3, #4]
- 800ae5e:	b29a      	uxth	r2, r3
- 800ae60:	4b81      	ldr	r3, [pc, #516]	; (800b068 <tcp_receive+0xb0c>)
- 800ae62:	681b      	ldr	r3, [r3, #0]
- 800ae64:	b29b      	uxth	r3, r3
- 800ae66:	1ad3      	subs	r3, r2, r3
- 800ae68:	b29a      	uxth	r2, r3
- 800ae6a:	4b80      	ldr	r3, [pc, #512]	; (800b06c <tcp_receive+0xb10>)
- 800ae6c:	811a      	strh	r2, [r3, #8]
-              if (TCPH_FLAGS(inseg.tcphdr) & TCP_SYN) {
- 800ae6e:	4b7f      	ldr	r3, [pc, #508]	; (800b06c <tcp_receive+0xb10>)
- 800ae70:	691b      	ldr	r3, [r3, #16]
- 800ae72:	899b      	ldrh	r3, [r3, #12]
- 800ae74:	b29b      	uxth	r3, r3
- 800ae76:	4618      	mov	r0, r3
- 800ae78:	f7fa fb68 	bl	800554c <lwip_htons>
- 800ae7c:	4603      	mov	r3, r0
- 800ae7e:	b2db      	uxtb	r3, r3
- 800ae80:	f003 0302 	and.w	r3, r3, #2
- 800ae84:	2b00      	cmp	r3, #0
- 800ae86:	d005      	beq.n	800ae94 <tcp_receive+0x938>
-                inseg.len -= 1;
- 800ae88:	4b78      	ldr	r3, [pc, #480]	; (800b06c <tcp_receive+0xb10>)
- 800ae8a:	891b      	ldrh	r3, [r3, #8]
- 800ae8c:	3b01      	subs	r3, #1
- 800ae8e:	b29a      	uxth	r2, r3
- 800ae90:	4b76      	ldr	r3, [pc, #472]	; (800b06c <tcp_receive+0xb10>)
- 800ae92:	811a      	strh	r2, [r3, #8]
-              }
-              pbuf_realloc(inseg.p, inseg.len);
- 800ae94:	4b75      	ldr	r3, [pc, #468]	; (800b06c <tcp_receive+0xb10>)
- 800ae96:	685b      	ldr	r3, [r3, #4]
- 800ae98:	4a74      	ldr	r2, [pc, #464]	; (800b06c <tcp_receive+0xb10>)
- 800ae9a:	8912      	ldrh	r2, [r2, #8]
- 800ae9c:	4611      	mov	r1, r2
- 800ae9e:	4618      	mov	r0, r3
- 800aea0:	f7fb ff12 	bl	8006cc8 <pbuf_realloc>
-              tcplen = TCP_TCPLEN(&inseg);
- 800aea4:	4b71      	ldr	r3, [pc, #452]	; (800b06c <tcp_receive+0xb10>)
- 800aea6:	891c      	ldrh	r4, [r3, #8]
- 800aea8:	4b70      	ldr	r3, [pc, #448]	; (800b06c <tcp_receive+0xb10>)
- 800aeaa:	691b      	ldr	r3, [r3, #16]
- 800aeac:	899b      	ldrh	r3, [r3, #12]
- 800aeae:	b29b      	uxth	r3, r3
- 800aeb0:	4618      	mov	r0, r3
- 800aeb2:	f7fa fb4b 	bl	800554c <lwip_htons>
- 800aeb6:	4603      	mov	r3, r0
- 800aeb8:	b2db      	uxtb	r3, r3
- 800aeba:	f003 0303 	and.w	r3, r3, #3
- 800aebe:	2b00      	cmp	r3, #0
- 800aec0:	d001      	beq.n	800aec6 <tcp_receive+0x96a>
- 800aec2:	2301      	movs	r3, #1
- 800aec4:	e000      	b.n	800aec8 <tcp_receive+0x96c>
- 800aec6:	2300      	movs	r3, #0
- 800aec8:	4423      	add	r3, r4
- 800aeca:	b29a      	uxth	r2, r3
- 800aecc:	4b65      	ldr	r3, [pc, #404]	; (800b064 <tcp_receive+0xb08>)
- 800aece:	801a      	strh	r2, [r3, #0]
-              LWIP_ASSERT("tcp_receive: segment not trimmed correctly to ooseq queue\n",
- 800aed0:	4b64      	ldr	r3, [pc, #400]	; (800b064 <tcp_receive+0xb08>)
- 800aed2:	881b      	ldrh	r3, [r3, #0]
- 800aed4:	461a      	mov	r2, r3
- 800aed6:	4b64      	ldr	r3, [pc, #400]	; (800b068 <tcp_receive+0xb0c>)
- 800aed8:	681b      	ldr	r3, [r3, #0]
- 800aeda:	441a      	add	r2, r3
- 800aedc:	6bfb      	ldr	r3, [r7, #60]	; 0x3c
- 800aede:	691b      	ldr	r3, [r3, #16]
- 800aee0:	685b      	ldr	r3, [r3, #4]
- 800aee2:	429a      	cmp	r2, r3
- 800aee4:	d006      	beq.n	800aef4 <tcp_receive+0x998>
- 800aee6:	4b62      	ldr	r3, [pc, #392]	; (800b070 <tcp_receive+0xb14>)
- 800aee8:	f240 52fc 	movw	r2, #1532	; 0x5fc
- 800aeec:	4961      	ldr	r1, [pc, #388]	; (800b074 <tcp_receive+0xb18>)
- 800aeee:	4862      	ldr	r0, [pc, #392]	; (800b078 <tcp_receive+0xb1c>)
- 800aef0:	f005 fe6a 	bl	8010bc8 <iprintf>
-                          (seqno + tcplen) == next->tcphdr->seqno);
-            }
-            pcb->ooseq = next;
- 800aef4:	687b      	ldr	r3, [r7, #4]
- 800aef6:	6bfa      	ldr	r2, [r7, #60]	; 0x3c
- 800aef8:	675a      	str	r2, [r3, #116]	; 0x74
-          }
-        }
-#endif /* TCP_QUEUE_OOSEQ */
-
-        pcb->rcv_nxt = seqno + tcplen;
- 800aefa:	4b5a      	ldr	r3, [pc, #360]	; (800b064 <tcp_receive+0xb08>)
- 800aefc:	881b      	ldrh	r3, [r3, #0]
- 800aefe:	461a      	mov	r2, r3
- 800af00:	4b59      	ldr	r3, [pc, #356]	; (800b068 <tcp_receive+0xb0c>)
- 800af02:	681b      	ldr	r3, [r3, #0]
- 800af04:	441a      	add	r2, r3
- 800af06:	687b      	ldr	r3, [r7, #4]
- 800af08:	625a      	str	r2, [r3, #36]	; 0x24
-
-        /* Update the receiver's (our) window. */
-        LWIP_ASSERT("tcp_receive: tcplen > rcv_wnd\n", pcb->rcv_wnd >= tcplen);
- 800af0a:	687b      	ldr	r3, [r7, #4]
- 800af0c:	8d1a      	ldrh	r2, [r3, #40]	; 0x28
- 800af0e:	4b55      	ldr	r3, [pc, #340]	; (800b064 <tcp_receive+0xb08>)
- 800af10:	881b      	ldrh	r3, [r3, #0]
- 800af12:	429a      	cmp	r2, r3
- 800af14:	d206      	bcs.n	800af24 <tcp_receive+0x9c8>
- 800af16:	4b56      	ldr	r3, [pc, #344]	; (800b070 <tcp_receive+0xb14>)
- 800af18:	f240 6207 	movw	r2, #1543	; 0x607
- 800af1c:	4957      	ldr	r1, [pc, #348]	; (800b07c <tcp_receive+0xb20>)
- 800af1e:	4856      	ldr	r0, [pc, #344]	; (800b078 <tcp_receive+0xb1c>)
- 800af20:	f005 fe52 	bl	8010bc8 <iprintf>
-        pcb->rcv_wnd -= tcplen;
- 800af24:	687b      	ldr	r3, [r7, #4]
- 800af26:	8d1a      	ldrh	r2, [r3, #40]	; 0x28
- 800af28:	4b4e      	ldr	r3, [pc, #312]	; (800b064 <tcp_receive+0xb08>)
- 800af2a:	881b      	ldrh	r3, [r3, #0]
- 800af2c:	1ad3      	subs	r3, r2, r3
- 800af2e:	b29a      	uxth	r2, r3
- 800af30:	687b      	ldr	r3, [r7, #4]
- 800af32:	851a      	strh	r2, [r3, #40]	; 0x28
-
-        tcp_update_rcv_ann_wnd(pcb);
- 800af34:	6878      	ldr	r0, [r7, #4]
- 800af36:	f7fc fde1 	bl	8007afc <tcp_update_rcv_ann_wnd>
-           chains its data on this pbuf as well.
-
-           If the segment was a FIN, we set the TF_GOT_FIN flag that will
-           be used to indicate to the application that the remote side has
-           closed its end of the connection. */
-        if (inseg.p->tot_len > 0) {
- 800af3a:	4b4c      	ldr	r3, [pc, #304]	; (800b06c <tcp_receive+0xb10>)
- 800af3c:	685b      	ldr	r3, [r3, #4]
- 800af3e:	891b      	ldrh	r3, [r3, #8]
- 800af40:	2b00      	cmp	r3, #0
- 800af42:	d006      	beq.n	800af52 <tcp_receive+0x9f6>
-          recv_data = inseg.p;
- 800af44:	4b49      	ldr	r3, [pc, #292]	; (800b06c <tcp_receive+0xb10>)
- 800af46:	685b      	ldr	r3, [r3, #4]
- 800af48:	4a4d      	ldr	r2, [pc, #308]	; (800b080 <tcp_receive+0xb24>)
- 800af4a:	6013      	str	r3, [r2, #0]
-          /* Since this pbuf now is the responsibility of the
-             application, we delete our reference to it so that we won't
-             (mistakingly) deallocate it. */
-          inseg.p = NULL;
- 800af4c:	4b47      	ldr	r3, [pc, #284]	; (800b06c <tcp_receive+0xb10>)
- 800af4e:	2200      	movs	r2, #0
- 800af50:	605a      	str	r2, [r3, #4]
-        }
-        if (TCPH_FLAGS(inseg.tcphdr) & TCP_FIN) {
- 800af52:	4b46      	ldr	r3, [pc, #280]	; (800b06c <tcp_receive+0xb10>)
- 800af54:	691b      	ldr	r3, [r3, #16]
- 800af56:	899b      	ldrh	r3, [r3, #12]
- 800af58:	b29b      	uxth	r3, r3
- 800af5a:	4618      	mov	r0, r3
- 800af5c:	f7fa faf6 	bl	800554c <lwip_htons>
- 800af60:	4603      	mov	r3, r0
- 800af62:	b2db      	uxtb	r3, r3
- 800af64:	f003 0301 	and.w	r3, r3, #1
- 800af68:	2b00      	cmp	r3, #0
- 800af6a:	f000 80b8 	beq.w	800b0de <tcp_receive+0xb82>
-          LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: received FIN.\n"));
-          recv_flags |= TF_GOT_FIN;
- 800af6e:	4b45      	ldr	r3, [pc, #276]	; (800b084 <tcp_receive+0xb28>)
- 800af70:	781b      	ldrb	r3, [r3, #0]
- 800af72:	f043 0320 	orr.w	r3, r3, #32
- 800af76:	b2da      	uxtb	r2, r3
- 800af78:	4b42      	ldr	r3, [pc, #264]	; (800b084 <tcp_receive+0xb28>)
- 800af7a:	701a      	strb	r2, [r3, #0]
-        }
-
-#if TCP_QUEUE_OOSEQ
-        /* We now check if we have segments on the ->ooseq queue that
-           are now in sequence. */
-        while (pcb->ooseq != NULL &&
- 800af7c:	e0af      	b.n	800b0de <tcp_receive+0xb82>
-               pcb->ooseq->tcphdr->seqno == pcb->rcv_nxt) {
-
-          struct tcp_seg *cseg = pcb->ooseq;
- 800af7e:	687b      	ldr	r3, [r7, #4]
- 800af80:	6f5b      	ldr	r3, [r3, #116]	; 0x74
- 800af82:	60bb      	str	r3, [r7, #8]
-          seqno = pcb->ooseq->tcphdr->seqno;
- 800af84:	687b      	ldr	r3, [r7, #4]
- 800af86:	6f5b      	ldr	r3, [r3, #116]	; 0x74
- 800af88:	691b      	ldr	r3, [r3, #16]
- 800af8a:	685b      	ldr	r3, [r3, #4]
- 800af8c:	4a36      	ldr	r2, [pc, #216]	; (800b068 <tcp_receive+0xb0c>)
- 800af8e:	6013      	str	r3, [r2, #0]
-
-          pcb->rcv_nxt += TCP_TCPLEN(cseg);
- 800af90:	68bb      	ldr	r3, [r7, #8]
- 800af92:	891b      	ldrh	r3, [r3, #8]
- 800af94:	461c      	mov	r4, r3
- 800af96:	68bb      	ldr	r3, [r7, #8]
- 800af98:	691b      	ldr	r3, [r3, #16]
- 800af9a:	899b      	ldrh	r3, [r3, #12]
- 800af9c:	b29b      	uxth	r3, r3
- 800af9e:	4618      	mov	r0, r3
- 800afa0:	f7fa fad4 	bl	800554c <lwip_htons>
- 800afa4:	4603      	mov	r3, r0
- 800afa6:	b2db      	uxtb	r3, r3
- 800afa8:	f003 0303 	and.w	r3, r3, #3
- 800afac:	2b00      	cmp	r3, #0
- 800afae:	d001      	beq.n	800afb4 <tcp_receive+0xa58>
- 800afb0:	2301      	movs	r3, #1
- 800afb2:	e000      	b.n	800afb6 <tcp_receive+0xa5a>
- 800afb4:	2300      	movs	r3, #0
- 800afb6:	191a      	adds	r2, r3, r4
- 800afb8:	687b      	ldr	r3, [r7, #4]
- 800afba:	6a5b      	ldr	r3, [r3, #36]	; 0x24
- 800afbc:	441a      	add	r2, r3
- 800afbe:	687b      	ldr	r3, [r7, #4]
- 800afc0:	625a      	str	r2, [r3, #36]	; 0x24
-          LWIP_ASSERT("tcp_receive: ooseq tcplen > rcv_wnd\n",
- 800afc2:	687b      	ldr	r3, [r7, #4]
- 800afc4:	8d1b      	ldrh	r3, [r3, #40]	; 0x28
- 800afc6:	461c      	mov	r4, r3
- 800afc8:	68bb      	ldr	r3, [r7, #8]
- 800afca:	891b      	ldrh	r3, [r3, #8]
- 800afcc:	461d      	mov	r5, r3
- 800afce:	68bb      	ldr	r3, [r7, #8]
- 800afd0:	691b      	ldr	r3, [r3, #16]
- 800afd2:	899b      	ldrh	r3, [r3, #12]
- 800afd4:	b29b      	uxth	r3, r3
- 800afd6:	4618      	mov	r0, r3
- 800afd8:	f7fa fab8 	bl	800554c <lwip_htons>
- 800afdc:	4603      	mov	r3, r0
- 800afde:	b2db      	uxtb	r3, r3
- 800afe0:	f003 0303 	and.w	r3, r3, #3
- 800afe4:	2b00      	cmp	r3, #0
- 800afe6:	d001      	beq.n	800afec <tcp_receive+0xa90>
- 800afe8:	2301      	movs	r3, #1
- 800afea:	e000      	b.n	800afee <tcp_receive+0xa92>
- 800afec:	2300      	movs	r3, #0
- 800afee:	442b      	add	r3, r5
- 800aff0:	429c      	cmp	r4, r3
- 800aff2:	d206      	bcs.n	800b002 <tcp_receive+0xaa6>
- 800aff4:	4b1e      	ldr	r3, [pc, #120]	; (800b070 <tcp_receive+0xb14>)
- 800aff6:	f240 622b 	movw	r2, #1579	; 0x62b
- 800affa:	4923      	ldr	r1, [pc, #140]	; (800b088 <tcp_receive+0xb2c>)
- 800affc:	481e      	ldr	r0, [pc, #120]	; (800b078 <tcp_receive+0xb1c>)
- 800affe:	f005 fde3 	bl	8010bc8 <iprintf>
-                      pcb->rcv_wnd >= TCP_TCPLEN(cseg));
-          pcb->rcv_wnd -= TCP_TCPLEN(cseg);
- 800b002:	68bb      	ldr	r3, [r7, #8]
- 800b004:	891b      	ldrh	r3, [r3, #8]
- 800b006:	461c      	mov	r4, r3
- 800b008:	68bb      	ldr	r3, [r7, #8]
- 800b00a:	691b      	ldr	r3, [r3, #16]
- 800b00c:	899b      	ldrh	r3, [r3, #12]
- 800b00e:	b29b      	uxth	r3, r3
- 800b010:	4618      	mov	r0, r3
- 800b012:	f7fa fa9b 	bl	800554c <lwip_htons>
- 800b016:	4603      	mov	r3, r0
- 800b018:	b2db      	uxtb	r3, r3
- 800b01a:	f003 0303 	and.w	r3, r3, #3
- 800b01e:	2b00      	cmp	r3, #0
- 800b020:	d001      	beq.n	800b026 <tcp_receive+0xaca>
- 800b022:	2301      	movs	r3, #1
- 800b024:	e000      	b.n	800b028 <tcp_receive+0xacc>
- 800b026:	2300      	movs	r3, #0
- 800b028:	1919      	adds	r1, r3, r4
- 800b02a:	687b      	ldr	r3, [r7, #4]
- 800b02c:	8d1a      	ldrh	r2, [r3, #40]	; 0x28
- 800b02e:	b28b      	uxth	r3, r1
- 800b030:	1ad3      	subs	r3, r2, r3
- 800b032:	b29a      	uxth	r2, r3
- 800b034:	687b      	ldr	r3, [r7, #4]
- 800b036:	851a      	strh	r2, [r3, #40]	; 0x28
-
-          tcp_update_rcv_ann_wnd(pcb);
- 800b038:	6878      	ldr	r0, [r7, #4]
- 800b03a:	f7fc fd5f 	bl	8007afc <tcp_update_rcv_ann_wnd>
-
-          if (cseg->p->tot_len > 0) {
- 800b03e:	68bb      	ldr	r3, [r7, #8]
- 800b040:	685b      	ldr	r3, [r3, #4]
- 800b042:	891b      	ldrh	r3, [r3, #8]
- 800b044:	2b00      	cmp	r3, #0
- 800b046:	d028      	beq.n	800b09a <tcp_receive+0xb3e>
-            /* Chain this pbuf onto the pbuf that we will pass to
-               the application. */
-            /* With window scaling, this can overflow recv_data->tot_len, but
-               that's not a problem since we explicitly fix that before passing
-               recv_data to the application. */
-            if (recv_data) {
- 800b048:	4b0d      	ldr	r3, [pc, #52]	; (800b080 <tcp_receive+0xb24>)
- 800b04a:	681b      	ldr	r3, [r3, #0]
- 800b04c:	2b00      	cmp	r3, #0
- 800b04e:	d01d      	beq.n	800b08c <tcp_receive+0xb30>
-              pbuf_cat(recv_data, cseg->p);
- 800b050:	4b0b      	ldr	r3, [pc, #44]	; (800b080 <tcp_receive+0xb24>)
- 800b052:	681a      	ldr	r2, [r3, #0]
- 800b054:	68bb      	ldr	r3, [r7, #8]
- 800b056:	685b      	ldr	r3, [r3, #4]
- 800b058:	4619      	mov	r1, r3
- 800b05a:	4610      	mov	r0, r2
- 800b05c:	f7fc f87c 	bl	8007158 <pbuf_cat>
- 800b060:	e018      	b.n	800b094 <tcp_receive+0xb38>
- 800b062:	bf00      	nop
- 800b064:	24007bb2 	.word	0x24007bb2
- 800b068:	24007ba8 	.word	0x24007ba8
- 800b06c:	24007b84 	.word	0x24007b84
- 800b070:	08013198 	.word	0x08013198
- 800b074:	08013578 	.word	0x08013578
- 800b078:	080131e4 	.word	0x080131e4
- 800b07c:	080135b4 	.word	0x080135b4
- 800b080:	24007bb8 	.word	0x24007bb8
- 800b084:	24007bb5 	.word	0x24007bb5
- 800b088:	080135d4 	.word	0x080135d4
-            } else {
-              recv_data = cseg->p;
- 800b08c:	68bb      	ldr	r3, [r7, #8]
- 800b08e:	685b      	ldr	r3, [r3, #4]
- 800b090:	4a70      	ldr	r2, [pc, #448]	; (800b254 <tcp_receive+0xcf8>)
- 800b092:	6013      	str	r3, [r2, #0]
-            }
-            cseg->p = NULL;
- 800b094:	68bb      	ldr	r3, [r7, #8]
- 800b096:	2200      	movs	r2, #0
- 800b098:	605a      	str	r2, [r3, #4]
-          }
-          if (TCPH_FLAGS(cseg->tcphdr) & TCP_FIN) {
- 800b09a:	68bb      	ldr	r3, [r7, #8]
- 800b09c:	691b      	ldr	r3, [r3, #16]
- 800b09e:	899b      	ldrh	r3, [r3, #12]
- 800b0a0:	b29b      	uxth	r3, r3
- 800b0a2:	4618      	mov	r0, r3
- 800b0a4:	f7fa fa52 	bl	800554c <lwip_htons>
- 800b0a8:	4603      	mov	r3, r0
- 800b0aa:	b2db      	uxtb	r3, r3
- 800b0ac:	f003 0301 	and.w	r3, r3, #1
- 800b0b0:	2b00      	cmp	r3, #0
- 800b0b2:	d00d      	beq.n	800b0d0 <tcp_receive+0xb74>
-            LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: dequeued FIN.\n"));
-            recv_flags |= TF_GOT_FIN;
- 800b0b4:	4b68      	ldr	r3, [pc, #416]	; (800b258 <tcp_receive+0xcfc>)
- 800b0b6:	781b      	ldrb	r3, [r3, #0]
- 800b0b8:	f043 0320 	orr.w	r3, r3, #32
- 800b0bc:	b2da      	uxtb	r2, r3
- 800b0be:	4b66      	ldr	r3, [pc, #408]	; (800b258 <tcp_receive+0xcfc>)
- 800b0c0:	701a      	strb	r2, [r3, #0]
-            if (pcb->state == ESTABLISHED) { /* force passive close or we can move to active close */
- 800b0c2:	687b      	ldr	r3, [r7, #4]
- 800b0c4:	7d1b      	ldrb	r3, [r3, #20]
- 800b0c6:	2b04      	cmp	r3, #4
- 800b0c8:	d102      	bne.n	800b0d0 <tcp_receive+0xb74>
-              pcb->state = CLOSE_WAIT;
- 800b0ca:	687b      	ldr	r3, [r7, #4]
- 800b0cc:	2207      	movs	r2, #7
- 800b0ce:	751a      	strb	r2, [r3, #20]
-            }
-          }
-
-          pcb->ooseq = cseg->next;
- 800b0d0:	68bb      	ldr	r3, [r7, #8]
- 800b0d2:	681a      	ldr	r2, [r3, #0]
- 800b0d4:	687b      	ldr	r3, [r7, #4]
- 800b0d6:	675a      	str	r2, [r3, #116]	; 0x74
-          tcp_seg_free(cseg);
- 800b0d8:	68b8      	ldr	r0, [r7, #8]
- 800b0da:	f7fd fb4c 	bl	8008776 <tcp_seg_free>
-        while (pcb->ooseq != NULL &&
- 800b0de:	687b      	ldr	r3, [r7, #4]
- 800b0e0:	6f5b      	ldr	r3, [r3, #116]	; 0x74
- 800b0e2:	2b00      	cmp	r3, #0
- 800b0e4:	d008      	beq.n	800b0f8 <tcp_receive+0xb9c>
-               pcb->ooseq->tcphdr->seqno == pcb->rcv_nxt) {
- 800b0e6:	687b      	ldr	r3, [r7, #4]
- 800b0e8:	6f5b      	ldr	r3, [r3, #116]	; 0x74
- 800b0ea:	691b      	ldr	r3, [r3, #16]
- 800b0ec:	685a      	ldr	r2, [r3, #4]
- 800b0ee:	687b      	ldr	r3, [r7, #4]
- 800b0f0:	6a5b      	ldr	r3, [r3, #36]	; 0x24
-        while (pcb->ooseq != NULL &&
- 800b0f2:	429a      	cmp	r2, r3
- 800b0f4:	f43f af43 	beq.w	800af7e <tcp_receive+0xa22>
-#endif /* LWIP_TCP_SACK_OUT */
-#endif /* TCP_QUEUE_OOSEQ */
-
-
-        /* Acknowledge the segment(s). */
-        tcp_ack(pcb);
- 800b0f8:	687b      	ldr	r3, [r7, #4]
- 800b0fa:	8b5b      	ldrh	r3, [r3, #26]
- 800b0fc:	f003 0301 	and.w	r3, r3, #1
- 800b100:	2b00      	cmp	r3, #0
- 800b102:	d00e      	beq.n	800b122 <tcp_receive+0xbc6>
- 800b104:	687b      	ldr	r3, [r7, #4]
- 800b106:	8b5b      	ldrh	r3, [r3, #26]
- 800b108:	f023 0301 	bic.w	r3, r3, #1
- 800b10c:	b29a      	uxth	r2, r3
- 800b10e:	687b      	ldr	r3, [r7, #4]
- 800b110:	835a      	strh	r2, [r3, #26]
- 800b112:	687b      	ldr	r3, [r7, #4]
- 800b114:	8b5b      	ldrh	r3, [r3, #26]
- 800b116:	f043 0302 	orr.w	r3, r3, #2
- 800b11a:	b29a      	uxth	r2, r3
- 800b11c:	687b      	ldr	r3, [r7, #4]
- 800b11e:	835a      	strh	r2, [r3, #26]
-      if (pcb->rcv_nxt == seqno) {
- 800b120:	e188      	b.n	800b434 <tcp_receive+0xed8>
-        tcp_ack(pcb);
- 800b122:	687b      	ldr	r3, [r7, #4]
- 800b124:	8b5b      	ldrh	r3, [r3, #26]
- 800b126:	f043 0301 	orr.w	r3, r3, #1
- 800b12a:	b29a      	uxth	r2, r3
- 800b12c:	687b      	ldr	r3, [r7, #4]
- 800b12e:	835a      	strh	r2, [r3, #26]
-      if (pcb->rcv_nxt == seqno) {
- 800b130:	e180      	b.n	800b434 <tcp_receive+0xed8>
-      } else {
-        /* We get here if the incoming segment is out-of-sequence. */
-
-#if TCP_QUEUE_OOSEQ
-        /* We queue the segment on the ->ooseq queue. */
-        if (pcb->ooseq == NULL) {
- 800b132:	687b      	ldr	r3, [r7, #4]
- 800b134:	6f5b      	ldr	r3, [r3, #116]	; 0x74
- 800b136:	2b00      	cmp	r3, #0
- 800b138:	d106      	bne.n	800b148 <tcp_receive+0xbec>
-          pcb->ooseq = tcp_seg_copy(&inseg);
- 800b13a:	4848      	ldr	r0, [pc, #288]	; (800b25c <tcp_receive+0xd00>)
- 800b13c:	f7fd fb34 	bl	80087a8 <tcp_seg_copy>
- 800b140:	4602      	mov	r2, r0
- 800b142:	687b      	ldr	r3, [r7, #4]
- 800b144:	675a      	str	r2, [r3, #116]	; 0x74
- 800b146:	e16d      	b.n	800b424 <tcp_receive+0xec8>
-#if LWIP_TCP_SACK_OUT
-          /* This is the left edge of the lowest possible SACK range.
-             It may start before the newly received segment (possibly adjusted below). */
-          u32_t sackbeg = TCP_SEQ_LT(seqno, pcb->ooseq->tcphdr->seqno) ? seqno : pcb->ooseq->tcphdr->seqno;
-#endif /* LWIP_TCP_SACK_OUT */
-          struct tcp_seg *next, *prev = NULL;
- 800b148:	2300      	movs	r3, #0
- 800b14a:	637b      	str	r3, [r7, #52]	; 0x34
-          for (next = pcb->ooseq; next != NULL; next = next->next) {
- 800b14c:	687b      	ldr	r3, [r7, #4]
- 800b14e:	6f5b      	ldr	r3, [r3, #116]	; 0x74
- 800b150:	63bb      	str	r3, [r7, #56]	; 0x38
- 800b152:	e157      	b.n	800b404 <tcp_receive+0xea8>
-            if (seqno == next->tcphdr->seqno) {
- 800b154:	6bbb      	ldr	r3, [r7, #56]	; 0x38
- 800b156:	691b      	ldr	r3, [r3, #16]
- 800b158:	685a      	ldr	r2, [r3, #4]
- 800b15a:	4b41      	ldr	r3, [pc, #260]	; (800b260 <tcp_receive+0xd04>)
- 800b15c:	681b      	ldr	r3, [r3, #0]
- 800b15e:	429a      	cmp	r2, r3
- 800b160:	d11d      	bne.n	800b19e <tcp_receive+0xc42>
-              /* The sequence number of the incoming segment is the
-                 same as the sequence number of the segment on
-                 ->ooseq. We check the lengths to see which one to
-                 discard. */
-              if (inseg.len > next->len) {
- 800b162:	4b3e      	ldr	r3, [pc, #248]	; (800b25c <tcp_receive+0xd00>)
- 800b164:	891a      	ldrh	r2, [r3, #8]
- 800b166:	6bbb      	ldr	r3, [r7, #56]	; 0x38
- 800b168:	891b      	ldrh	r3, [r3, #8]
- 800b16a:	429a      	cmp	r2, r3
- 800b16c:	f240 814f 	bls.w	800b40e <tcp_receive+0xeb2>
-                /* The incoming segment is larger than the old
-                   segment. We replace some segments with the new
-                   one. */
-                struct tcp_seg *cseg = tcp_seg_copy(&inseg);
- 800b170:	483a      	ldr	r0, [pc, #232]	; (800b25c <tcp_receive+0xd00>)
- 800b172:	f7fd fb19 	bl	80087a8 <tcp_seg_copy>
- 800b176:	6178      	str	r0, [r7, #20]
-                if (cseg != NULL) {
- 800b178:	697b      	ldr	r3, [r7, #20]
- 800b17a:	2b00      	cmp	r3, #0
- 800b17c:	f000 8149 	beq.w	800b412 <tcp_receive+0xeb6>
-                  if (prev != NULL) {
- 800b180:	6b7b      	ldr	r3, [r7, #52]	; 0x34
- 800b182:	2b00      	cmp	r3, #0
- 800b184:	d003      	beq.n	800b18e <tcp_receive+0xc32>
-                    prev->next = cseg;
- 800b186:	6b7b      	ldr	r3, [r7, #52]	; 0x34
- 800b188:	697a      	ldr	r2, [r7, #20]
- 800b18a:	601a      	str	r2, [r3, #0]
- 800b18c:	e002      	b.n	800b194 <tcp_receive+0xc38>
-                  } else {
-                    pcb->ooseq = cseg;
- 800b18e:	687b      	ldr	r3, [r7, #4]
- 800b190:	697a      	ldr	r2, [r7, #20]
- 800b192:	675a      	str	r2, [r3, #116]	; 0x74
-                  }
-                  tcp_oos_insert_segment(cseg, next);
- 800b194:	6bb9      	ldr	r1, [r7, #56]	; 0x38
- 800b196:	6978      	ldr	r0, [r7, #20]
- 800b198:	f7ff f8dc 	bl	800a354 <tcp_oos_insert_segment>
-                }
-                break;
- 800b19c:	e139      	b.n	800b412 <tcp_receive+0xeb6>
-                   segment was smaller than the old one; in either
-                   case, we ditch the incoming segment. */
-                break;
-              }
-            } else {
-              if (prev == NULL) {
- 800b19e:	6b7b      	ldr	r3, [r7, #52]	; 0x34
- 800b1a0:	2b00      	cmp	r3, #0
- 800b1a2:	d117      	bne.n	800b1d4 <tcp_receive+0xc78>
-                if (TCP_SEQ_LT(seqno, next->tcphdr->seqno)) {
- 800b1a4:	4b2e      	ldr	r3, [pc, #184]	; (800b260 <tcp_receive+0xd04>)
- 800b1a6:	681a      	ldr	r2, [r3, #0]
- 800b1a8:	6bbb      	ldr	r3, [r7, #56]	; 0x38
- 800b1aa:	691b      	ldr	r3, [r3, #16]
- 800b1ac:	685b      	ldr	r3, [r3, #4]
- 800b1ae:	1ad3      	subs	r3, r2, r3
- 800b1b0:	2b00      	cmp	r3, #0
- 800b1b2:	da57      	bge.n	800b264 <tcp_receive+0xd08>
-                  /* The sequence number of the incoming segment is lower
-                     than the sequence number of the first segment on the
-                     queue. We put the incoming segment first on the
-                     queue. */
-                  struct tcp_seg *cseg = tcp_seg_copy(&inseg);
- 800b1b4:	4829      	ldr	r0, [pc, #164]	; (800b25c <tcp_receive+0xd00>)
- 800b1b6:	f7fd faf7 	bl	80087a8 <tcp_seg_copy>
- 800b1ba:	61b8      	str	r0, [r7, #24]
-                  if (cseg != NULL) {
- 800b1bc:	69bb      	ldr	r3, [r7, #24]
- 800b1be:	2b00      	cmp	r3, #0
- 800b1c0:	f000 8129 	beq.w	800b416 <tcp_receive+0xeba>
-                    pcb->ooseq = cseg;
- 800b1c4:	687b      	ldr	r3, [r7, #4]
- 800b1c6:	69ba      	ldr	r2, [r7, #24]
- 800b1c8:	675a      	str	r2, [r3, #116]	; 0x74
-                    tcp_oos_insert_segment(cseg, next);
- 800b1ca:	6bb9      	ldr	r1, [r7, #56]	; 0x38
- 800b1cc:	69b8      	ldr	r0, [r7, #24]
- 800b1ce:	f7ff f8c1 	bl	800a354 <tcp_oos_insert_segment>
-                  }
-                  break;
- 800b1d2:	e120      	b.n	800b416 <tcp_receive+0xeba>
-                }
-              } else {
-                /*if (TCP_SEQ_LT(prev->tcphdr->seqno, seqno) &&
-                  TCP_SEQ_LT(seqno, next->tcphdr->seqno)) {*/
-                if (TCP_SEQ_BETWEEN(seqno, prev->tcphdr->seqno + 1, next->tcphdr->seqno - 1)) {
- 800b1d4:	4b22      	ldr	r3, [pc, #136]	; (800b260 <tcp_receive+0xd04>)
- 800b1d6:	681a      	ldr	r2, [r3, #0]
- 800b1d8:	6b7b      	ldr	r3, [r7, #52]	; 0x34
- 800b1da:	691b      	ldr	r3, [r3, #16]
- 800b1dc:	685b      	ldr	r3, [r3, #4]
- 800b1de:	1ad3      	subs	r3, r2, r3
- 800b1e0:	3b01      	subs	r3, #1
- 800b1e2:	2b00      	cmp	r3, #0
- 800b1e4:	db3e      	blt.n	800b264 <tcp_receive+0xd08>
- 800b1e6:	4b1e      	ldr	r3, [pc, #120]	; (800b260 <tcp_receive+0xd04>)
- 800b1e8:	681a      	ldr	r2, [r3, #0]
- 800b1ea:	6bbb      	ldr	r3, [r7, #56]	; 0x38
- 800b1ec:	691b      	ldr	r3, [r3, #16]
- 800b1ee:	685b      	ldr	r3, [r3, #4]
- 800b1f0:	1ad3      	subs	r3, r2, r3
- 800b1f2:	3301      	adds	r3, #1
- 800b1f4:	2b00      	cmp	r3, #0
- 800b1f6:	dc35      	bgt.n	800b264 <tcp_receive+0xd08>
-                  /* The sequence number of the incoming segment is in
-                     between the sequence numbers of the previous and
-                     the next segment on ->ooseq. We trim trim the previous
-                     segment, delete next segments that included in received segment
-                     and trim received, if needed. */
-                  struct tcp_seg *cseg = tcp_seg_copy(&inseg);
- 800b1f8:	4818      	ldr	r0, [pc, #96]	; (800b25c <tcp_receive+0xd00>)
- 800b1fa:	f7fd fad5 	bl	80087a8 <tcp_seg_copy>
- 800b1fe:	61f8      	str	r0, [r7, #28]
-                  if (cseg != NULL) {
- 800b200:	69fb      	ldr	r3, [r7, #28]
- 800b202:	2b00      	cmp	r3, #0
- 800b204:	f000 8109 	beq.w	800b41a <tcp_receive+0xebe>
-                    if (TCP_SEQ_GT(prev->tcphdr->seqno + prev->len, seqno)) {
- 800b208:	6b7b      	ldr	r3, [r7, #52]	; 0x34
- 800b20a:	691b      	ldr	r3, [r3, #16]
- 800b20c:	685b      	ldr	r3, [r3, #4]
- 800b20e:	6b7a      	ldr	r2, [r7, #52]	; 0x34
- 800b210:	8912      	ldrh	r2, [r2, #8]
- 800b212:	441a      	add	r2, r3
- 800b214:	4b12      	ldr	r3, [pc, #72]	; (800b260 <tcp_receive+0xd04>)
- 800b216:	681b      	ldr	r3, [r3, #0]
- 800b218:	1ad3      	subs	r3, r2, r3
- 800b21a:	2b00      	cmp	r3, #0
- 800b21c:	dd12      	ble.n	800b244 <tcp_receive+0xce8>
-                      /* We need to trim the prev segment. */
-                      prev->len = (u16_t)(seqno - prev->tcphdr->seqno);
- 800b21e:	4b10      	ldr	r3, [pc, #64]	; (800b260 <tcp_receive+0xd04>)
- 800b220:	681b      	ldr	r3, [r3, #0]
- 800b222:	b29a      	uxth	r2, r3
- 800b224:	6b7b      	ldr	r3, [r7, #52]	; 0x34
- 800b226:	691b      	ldr	r3, [r3, #16]
- 800b228:	685b      	ldr	r3, [r3, #4]
- 800b22a:	b29b      	uxth	r3, r3
- 800b22c:	1ad3      	subs	r3, r2, r3
- 800b22e:	b29a      	uxth	r2, r3
- 800b230:	6b7b      	ldr	r3, [r7, #52]	; 0x34
- 800b232:	811a      	strh	r2, [r3, #8]
-                      pbuf_realloc(prev->p, prev->len);
- 800b234:	6b7b      	ldr	r3, [r7, #52]	; 0x34
- 800b236:	685a      	ldr	r2, [r3, #4]
- 800b238:	6b7b      	ldr	r3, [r7, #52]	; 0x34
- 800b23a:	891b      	ldrh	r3, [r3, #8]
- 800b23c:	4619      	mov	r1, r3
- 800b23e:	4610      	mov	r0, r2
- 800b240:	f7fb fd42 	bl	8006cc8 <pbuf_realloc>
-                    }
-                    prev->next = cseg;
- 800b244:	6b7b      	ldr	r3, [r7, #52]	; 0x34
- 800b246:	69fa      	ldr	r2, [r7, #28]
- 800b248:	601a      	str	r2, [r3, #0]
-                    tcp_oos_insert_segment(cseg, next);
- 800b24a:	6bb9      	ldr	r1, [r7, #56]	; 0x38
- 800b24c:	69f8      	ldr	r0, [r7, #28]
- 800b24e:	f7ff f881 	bl	800a354 <tcp_oos_insert_segment>
-                  }
-                  break;
- 800b252:	e0e2      	b.n	800b41a <tcp_receive+0xebe>
- 800b254:	24007bb8 	.word	0x24007bb8
- 800b258:	24007bb5 	.word	0x24007bb5
- 800b25c:	24007b84 	.word	0x24007b84
- 800b260:	24007ba8 	.word	0x24007ba8
-#endif /* LWIP_TCP_SACK_OUT */
-
-              /* We don't use 'prev' below, so let's set it to current 'next'.
-                 This way even if we break the loop below, 'prev' will be pointing
-                 at the segment right in front of the newly added one. */
-              prev = next;
- 800b264:	6bbb      	ldr	r3, [r7, #56]	; 0x38
- 800b266:	637b      	str	r3, [r7, #52]	; 0x34
-
-              /* If the "next" segment is the last segment on the
-                 ooseq queue, we add the incoming segment to the end
-                 of the list. */
-              if (next->next == NULL &&
- 800b268:	6bbb      	ldr	r3, [r7, #56]	; 0x38
- 800b26a:	681b      	ldr	r3, [r3, #0]
- 800b26c:	2b00      	cmp	r3, #0
- 800b26e:	f040 80c6 	bne.w	800b3fe <tcp_receive+0xea2>
-                  TCP_SEQ_GT(seqno, next->tcphdr->seqno)) {
- 800b272:	4b80      	ldr	r3, [pc, #512]	; (800b474 <tcp_receive+0xf18>)
- 800b274:	681a      	ldr	r2, [r3, #0]
- 800b276:	6bbb      	ldr	r3, [r7, #56]	; 0x38
- 800b278:	691b      	ldr	r3, [r3, #16]
- 800b27a:	685b      	ldr	r3, [r3, #4]
- 800b27c:	1ad3      	subs	r3, r2, r3
-              if (next->next == NULL &&
- 800b27e:	2b00      	cmp	r3, #0
- 800b280:	f340 80bd 	ble.w	800b3fe <tcp_receive+0xea2>
-                if (TCPH_FLAGS(next->tcphdr) & TCP_FIN) {
- 800b284:	6bbb      	ldr	r3, [r7, #56]	; 0x38
- 800b286:	691b      	ldr	r3, [r3, #16]
- 800b288:	899b      	ldrh	r3, [r3, #12]
- 800b28a:	b29b      	uxth	r3, r3
- 800b28c:	4618      	mov	r0, r3
- 800b28e:	f7fa f95d 	bl	800554c <lwip_htons>
- 800b292:	4603      	mov	r3, r0
- 800b294:	b2db      	uxtb	r3, r3
- 800b296:	f003 0301 	and.w	r3, r3, #1
- 800b29a:	2b00      	cmp	r3, #0
- 800b29c:	f040 80bf 	bne.w	800b41e <tcp_receive+0xec2>
-                  /* segment "next" already contains all data */
-                  break;
-                }
-                next->next = tcp_seg_copy(&inseg);
- 800b2a0:	4875      	ldr	r0, [pc, #468]	; (800b478 <tcp_receive+0xf1c>)
- 800b2a2:	f7fd fa81 	bl	80087a8 <tcp_seg_copy>
- 800b2a6:	4602      	mov	r2, r0
- 800b2a8:	6bbb      	ldr	r3, [r7, #56]	; 0x38
- 800b2aa:	601a      	str	r2, [r3, #0]
-                if (next->next != NULL) {
- 800b2ac:	6bbb      	ldr	r3, [r7, #56]	; 0x38
- 800b2ae:	681b      	ldr	r3, [r3, #0]
- 800b2b0:	2b00      	cmp	r3, #0
- 800b2b2:	f000 80b6 	beq.w	800b422 <tcp_receive+0xec6>
-                  if (TCP_SEQ_GT(next->tcphdr->seqno + next->len, seqno)) {
- 800b2b6:	6bbb      	ldr	r3, [r7, #56]	; 0x38
- 800b2b8:	691b      	ldr	r3, [r3, #16]
- 800b2ba:	685b      	ldr	r3, [r3, #4]
- 800b2bc:	6bba      	ldr	r2, [r7, #56]	; 0x38
- 800b2be:	8912      	ldrh	r2, [r2, #8]
- 800b2c0:	441a      	add	r2, r3
- 800b2c2:	4b6c      	ldr	r3, [pc, #432]	; (800b474 <tcp_receive+0xf18>)
- 800b2c4:	681b      	ldr	r3, [r3, #0]
- 800b2c6:	1ad3      	subs	r3, r2, r3
- 800b2c8:	2b00      	cmp	r3, #0
- 800b2ca:	dd12      	ble.n	800b2f2 <tcp_receive+0xd96>
-                    /* We need to trim the last segment. */
-                    next->len = (u16_t)(seqno - next->tcphdr->seqno);
- 800b2cc:	4b69      	ldr	r3, [pc, #420]	; (800b474 <tcp_receive+0xf18>)
- 800b2ce:	681b      	ldr	r3, [r3, #0]
- 800b2d0:	b29a      	uxth	r2, r3
- 800b2d2:	6bbb      	ldr	r3, [r7, #56]	; 0x38
- 800b2d4:	691b      	ldr	r3, [r3, #16]
- 800b2d6:	685b      	ldr	r3, [r3, #4]
- 800b2d8:	b29b      	uxth	r3, r3
- 800b2da:	1ad3      	subs	r3, r2, r3
- 800b2dc:	b29a      	uxth	r2, r3
- 800b2de:	6bbb      	ldr	r3, [r7, #56]	; 0x38
- 800b2e0:	811a      	strh	r2, [r3, #8]
-                    pbuf_realloc(next->p, next->len);
- 800b2e2:	6bbb      	ldr	r3, [r7, #56]	; 0x38
- 800b2e4:	685a      	ldr	r2, [r3, #4]
- 800b2e6:	6bbb      	ldr	r3, [r7, #56]	; 0x38
- 800b2e8:	891b      	ldrh	r3, [r3, #8]
- 800b2ea:	4619      	mov	r1, r3
- 800b2ec:	4610      	mov	r0, r2
- 800b2ee:	f7fb fceb 	bl	8006cc8 <pbuf_realloc>
-                  }
-                  /* check if the remote side overruns our receive window */
-                  if (TCP_SEQ_GT((u32_t)tcplen + seqno, pcb->rcv_nxt + (u32_t)pcb->rcv_wnd)) {
- 800b2f2:	4b62      	ldr	r3, [pc, #392]	; (800b47c <tcp_receive+0xf20>)
- 800b2f4:	881b      	ldrh	r3, [r3, #0]
- 800b2f6:	461a      	mov	r2, r3
- 800b2f8:	4b5e      	ldr	r3, [pc, #376]	; (800b474 <tcp_receive+0xf18>)
- 800b2fa:	681b      	ldr	r3, [r3, #0]
- 800b2fc:	441a      	add	r2, r3
- 800b2fe:	687b      	ldr	r3, [r7, #4]
- 800b300:	6a5b      	ldr	r3, [r3, #36]	; 0x24
- 800b302:	6879      	ldr	r1, [r7, #4]
- 800b304:	8d09      	ldrh	r1, [r1, #40]	; 0x28
- 800b306:	440b      	add	r3, r1
- 800b308:	1ad3      	subs	r3, r2, r3
- 800b30a:	2b00      	cmp	r3, #0
- 800b30c:	f340 8089 	ble.w	800b422 <tcp_receive+0xec6>
-                    LWIP_DEBUGF(TCP_INPUT_DEBUG,
-                                ("tcp_receive: other end overran receive window"
-                                 "seqno %"U32_F" len %"U16_F" right edge %"U32_F"\n",
-                                 seqno, tcplen, pcb->rcv_nxt + pcb->rcv_wnd));
-                    if (TCPH_FLAGS(next->next->tcphdr) & TCP_FIN) {
- 800b310:	6bbb      	ldr	r3, [r7, #56]	; 0x38
- 800b312:	681b      	ldr	r3, [r3, #0]
- 800b314:	691b      	ldr	r3, [r3, #16]
- 800b316:	899b      	ldrh	r3, [r3, #12]
- 800b318:	b29b      	uxth	r3, r3
- 800b31a:	4618      	mov	r0, r3
- 800b31c:	f7fa f916 	bl	800554c <lwip_htons>
- 800b320:	4603      	mov	r3, r0
- 800b322:	b2db      	uxtb	r3, r3
- 800b324:	f003 0301 	and.w	r3, r3, #1
- 800b328:	2b00      	cmp	r3, #0
- 800b32a:	d022      	beq.n	800b372 <tcp_receive+0xe16>
-                      /* Must remove the FIN from the header as we're trimming
-                       * that byte of sequence-space from the packet */
-                      TCPH_FLAGS_SET(next->next->tcphdr, TCPH_FLAGS(next->next->tcphdr) & ~TCP_FIN);
- 800b32c:	6bbb      	ldr	r3, [r7, #56]	; 0x38
- 800b32e:	681b      	ldr	r3, [r3, #0]
- 800b330:	691b      	ldr	r3, [r3, #16]
- 800b332:	899b      	ldrh	r3, [r3, #12]
- 800b334:	b29b      	uxth	r3, r3
- 800b336:	b21b      	sxth	r3, r3
- 800b338:	f423 537c 	bic.w	r3, r3, #16128	; 0x3f00
- 800b33c:	b21c      	sxth	r4, r3
- 800b33e:	6bbb      	ldr	r3, [r7, #56]	; 0x38
- 800b340:	681b      	ldr	r3, [r3, #0]
- 800b342:	691b      	ldr	r3, [r3, #16]
- 800b344:	899b      	ldrh	r3, [r3, #12]
- 800b346:	b29b      	uxth	r3, r3
- 800b348:	4618      	mov	r0, r3
- 800b34a:	f7fa f8ff 	bl	800554c <lwip_htons>
- 800b34e:	4603      	mov	r3, r0
- 800b350:	b2db      	uxtb	r3, r3
- 800b352:	b29b      	uxth	r3, r3
- 800b354:	f003 033e 	and.w	r3, r3, #62	; 0x3e
- 800b358:	b29b      	uxth	r3, r3
- 800b35a:	4618      	mov	r0, r3
- 800b35c:	f7fa f8f6 	bl	800554c <lwip_htons>
- 800b360:	4603      	mov	r3, r0
- 800b362:	b21b      	sxth	r3, r3
- 800b364:	4323      	orrs	r3, r4
- 800b366:	b21a      	sxth	r2, r3
- 800b368:	6bbb      	ldr	r3, [r7, #56]	; 0x38
- 800b36a:	681b      	ldr	r3, [r3, #0]
- 800b36c:	691b      	ldr	r3, [r3, #16]
- 800b36e:	b292      	uxth	r2, r2
- 800b370:	819a      	strh	r2, [r3, #12]
-                    }
-                    /* Adjust length of segment to fit in the window. */
-                    next->next->len = (u16_t)(pcb->rcv_nxt + pcb->rcv_wnd - seqno);
- 800b372:	687b      	ldr	r3, [r7, #4]
- 800b374:	6a5b      	ldr	r3, [r3, #36]	; 0x24
- 800b376:	b29a      	uxth	r2, r3
- 800b378:	687b      	ldr	r3, [r7, #4]
- 800b37a:	8d1b      	ldrh	r3, [r3, #40]	; 0x28
- 800b37c:	4413      	add	r3, r2
- 800b37e:	b299      	uxth	r1, r3
- 800b380:	4b3c      	ldr	r3, [pc, #240]	; (800b474 <tcp_receive+0xf18>)
- 800b382:	681b      	ldr	r3, [r3, #0]
- 800b384:	b29a      	uxth	r2, r3
- 800b386:	6bbb      	ldr	r3, [r7, #56]	; 0x38
- 800b388:	681b      	ldr	r3, [r3, #0]
- 800b38a:	1a8a      	subs	r2, r1, r2
- 800b38c:	b292      	uxth	r2, r2
- 800b38e:	811a      	strh	r2, [r3, #8]
-                    pbuf_realloc(next->next->p, next->next->len);
- 800b390:	6bbb      	ldr	r3, [r7, #56]	; 0x38
- 800b392:	681b      	ldr	r3, [r3, #0]
- 800b394:	685a      	ldr	r2, [r3, #4]
- 800b396:	6bbb      	ldr	r3, [r7, #56]	; 0x38
- 800b398:	681b      	ldr	r3, [r3, #0]
- 800b39a:	891b      	ldrh	r3, [r3, #8]
- 800b39c:	4619      	mov	r1, r3
- 800b39e:	4610      	mov	r0, r2
- 800b3a0:	f7fb fc92 	bl	8006cc8 <pbuf_realloc>
-                    tcplen = TCP_TCPLEN(next->next);
- 800b3a4:	6bbb      	ldr	r3, [r7, #56]	; 0x38
- 800b3a6:	681b      	ldr	r3, [r3, #0]
- 800b3a8:	891c      	ldrh	r4, [r3, #8]
- 800b3aa:	6bbb      	ldr	r3, [r7, #56]	; 0x38
- 800b3ac:	681b      	ldr	r3, [r3, #0]
- 800b3ae:	691b      	ldr	r3, [r3, #16]
- 800b3b0:	899b      	ldrh	r3, [r3, #12]
- 800b3b2:	b29b      	uxth	r3, r3
- 800b3b4:	4618      	mov	r0, r3
- 800b3b6:	f7fa f8c9 	bl	800554c <lwip_htons>
- 800b3ba:	4603      	mov	r3, r0
- 800b3bc:	b2db      	uxtb	r3, r3
- 800b3be:	f003 0303 	and.w	r3, r3, #3
- 800b3c2:	2b00      	cmp	r3, #0
- 800b3c4:	d001      	beq.n	800b3ca <tcp_receive+0xe6e>
- 800b3c6:	2301      	movs	r3, #1
- 800b3c8:	e000      	b.n	800b3cc <tcp_receive+0xe70>
- 800b3ca:	2300      	movs	r3, #0
- 800b3cc:	4423      	add	r3, r4
- 800b3ce:	b29a      	uxth	r2, r3
- 800b3d0:	4b2a      	ldr	r3, [pc, #168]	; (800b47c <tcp_receive+0xf20>)
- 800b3d2:	801a      	strh	r2, [r3, #0]
-                    LWIP_ASSERT("tcp_receive: segment not trimmed correctly to rcv_wnd\n",
- 800b3d4:	4b29      	ldr	r3, [pc, #164]	; (800b47c <tcp_receive+0xf20>)
- 800b3d6:	881b      	ldrh	r3, [r3, #0]
- 800b3d8:	461a      	mov	r2, r3
- 800b3da:	4b26      	ldr	r3, [pc, #152]	; (800b474 <tcp_receive+0xf18>)
- 800b3dc:	681b      	ldr	r3, [r3, #0]
- 800b3de:	441a      	add	r2, r3
- 800b3e0:	687b      	ldr	r3, [r7, #4]
- 800b3e2:	6a5b      	ldr	r3, [r3, #36]	; 0x24
- 800b3e4:	6879      	ldr	r1, [r7, #4]
- 800b3e6:	8d09      	ldrh	r1, [r1, #40]	; 0x28
- 800b3e8:	440b      	add	r3, r1
- 800b3ea:	429a      	cmp	r2, r3
- 800b3ec:	d019      	beq.n	800b422 <tcp_receive+0xec6>
- 800b3ee:	4b24      	ldr	r3, [pc, #144]	; (800b480 <tcp_receive+0xf24>)
- 800b3f0:	f44f 62df 	mov.w	r2, #1784	; 0x6f8
- 800b3f4:	4923      	ldr	r1, [pc, #140]	; (800b484 <tcp_receive+0xf28>)
- 800b3f6:	4824      	ldr	r0, [pc, #144]	; (800b488 <tcp_receive+0xf2c>)
- 800b3f8:	f005 fbe6 	bl	8010bc8 <iprintf>
-                                (seqno + tcplen) == (pcb->rcv_nxt + pcb->rcv_wnd));
-                  }
-                }
-                break;
- 800b3fc:	e011      	b.n	800b422 <tcp_receive+0xec6>
-          for (next = pcb->ooseq; next != NULL; next = next->next) {
- 800b3fe:	6bbb      	ldr	r3, [r7, #56]	; 0x38
- 800b400:	681b      	ldr	r3, [r3, #0]
- 800b402:	63bb      	str	r3, [r7, #56]	; 0x38
- 800b404:	6bbb      	ldr	r3, [r7, #56]	; 0x38
- 800b406:	2b00      	cmp	r3, #0
- 800b408:	f47f aea4 	bne.w	800b154 <tcp_receive+0xbf8>
- 800b40c:	e00a      	b.n	800b424 <tcp_receive+0xec8>
-                break;
- 800b40e:	bf00      	nop
- 800b410:	e008      	b.n	800b424 <tcp_receive+0xec8>
-                break;
- 800b412:	bf00      	nop
- 800b414:	e006      	b.n	800b424 <tcp_receive+0xec8>
-                  break;
- 800b416:	bf00      	nop
- 800b418:	e004      	b.n	800b424 <tcp_receive+0xec8>
-                  break;
- 800b41a:	bf00      	nop
- 800b41c:	e002      	b.n	800b424 <tcp_receive+0xec8>
-                  break;
- 800b41e:	bf00      	nop
- 800b420:	e000      	b.n	800b424 <tcp_receive+0xec8>
-                break;
- 800b422:	bf00      	nop
-#endif /* TCP_OOSEQ_BYTES_LIMIT || TCP_OOSEQ_PBUFS_LIMIT */
-#endif /* TCP_QUEUE_OOSEQ */
-
-        /* We send the ACK packet after we've (potentially) dealt with SACKs,
-           so they can be included in the acknowledgment. */
-        tcp_send_empty_ack(pcb);
- 800b424:	6878      	ldr	r0, [r7, #4]
- 800b426:	f001 fef7 	bl	800d218 <tcp_send_empty_ack>
-      if (pcb->rcv_nxt == seqno) {
- 800b42a:	e003      	b.n	800b434 <tcp_receive+0xed8>
-      }
-    } else {
-      /* The incoming segment is not within the window. */
-      tcp_send_empty_ack(pcb);
- 800b42c:	6878      	ldr	r0, [r7, #4]
- 800b42e:	f001 fef3 	bl	800d218 <tcp_send_empty_ack>
-    if (TCP_SEQ_BETWEEN(seqno, pcb->rcv_nxt,
- 800b432:	e01a      	b.n	800b46a <tcp_receive+0xf0e>
- 800b434:	e019      	b.n	800b46a <tcp_receive+0xf0e>
-    }
-  } else {
-    /* Segments with length 0 is taken care of here. Segments that
-       fall out of the window are ACKed. */
-    if (!TCP_SEQ_BETWEEN(seqno, pcb->rcv_nxt, pcb->rcv_nxt + pcb->rcv_wnd - 1)) {
- 800b436:	4b0f      	ldr	r3, [pc, #60]	; (800b474 <tcp_receive+0xf18>)
- 800b438:	681a      	ldr	r2, [r3, #0]
- 800b43a:	687b      	ldr	r3, [r7, #4]
- 800b43c:	6a5b      	ldr	r3, [r3, #36]	; 0x24
- 800b43e:	1ad3      	subs	r3, r2, r3
- 800b440:	2b00      	cmp	r3, #0
- 800b442:	db0a      	blt.n	800b45a <tcp_receive+0xefe>
- 800b444:	4b0b      	ldr	r3, [pc, #44]	; (800b474 <tcp_receive+0xf18>)
- 800b446:	681a      	ldr	r2, [r3, #0]
- 800b448:	687b      	ldr	r3, [r7, #4]
- 800b44a:	6a5b      	ldr	r3, [r3, #36]	; 0x24
- 800b44c:	6879      	ldr	r1, [r7, #4]
- 800b44e:	8d09      	ldrh	r1, [r1, #40]	; 0x28
- 800b450:	440b      	add	r3, r1
- 800b452:	1ad3      	subs	r3, r2, r3
- 800b454:	3301      	adds	r3, #1
- 800b456:	2b00      	cmp	r3, #0
- 800b458:	dd07      	ble.n	800b46a <tcp_receive+0xf0e>
-      tcp_ack_now(pcb);
- 800b45a:	687b      	ldr	r3, [r7, #4]
- 800b45c:	8b5b      	ldrh	r3, [r3, #26]
- 800b45e:	f043 0302 	orr.w	r3, r3, #2
- 800b462:	b29a      	uxth	r2, r3
- 800b464:	687b      	ldr	r3, [r7, #4]
- 800b466:	835a      	strh	r2, [r3, #26]
-    }
-  }
-}
- 800b468:	e7ff      	b.n	800b46a <tcp_receive+0xf0e>
- 800b46a:	bf00      	nop
- 800b46c:	3750      	adds	r7, #80	; 0x50
- 800b46e:	46bd      	mov	sp, r7
- 800b470:	bdb0      	pop	{r4, r5, r7, pc}
- 800b472:	bf00      	nop
- 800b474:	24007ba8 	.word	0x24007ba8
- 800b478:	24007b84 	.word	0x24007b84
- 800b47c:	24007bb2 	.word	0x24007bb2
- 800b480:	08013198 	.word	0x08013198
- 800b484:	08013540 	.word	0x08013540
- 800b488:	080131e4 	.word	0x080131e4
-
-0800b48c <tcp_get_next_optbyte>:
-
-static u8_t
-tcp_get_next_optbyte(void)
-{
- 800b48c:	b480      	push	{r7}
- 800b48e:	b083      	sub	sp, #12
- 800b490:	af00      	add	r7, sp, #0
-  u16_t optidx = tcp_optidx++;
- 800b492:	4b15      	ldr	r3, [pc, #84]	; (800b4e8 <tcp_get_next_optbyte+0x5c>)
- 800b494:	881b      	ldrh	r3, [r3, #0]
- 800b496:	1c5a      	adds	r2, r3, #1
- 800b498:	b291      	uxth	r1, r2
- 800b49a:	4a13      	ldr	r2, [pc, #76]	; (800b4e8 <tcp_get_next_optbyte+0x5c>)
- 800b49c:	8011      	strh	r1, [r2, #0]
- 800b49e:	80fb      	strh	r3, [r7, #6]
-  if ((tcphdr_opt2 == NULL) || (optidx < tcphdr_opt1len)) {
- 800b4a0:	4b12      	ldr	r3, [pc, #72]	; (800b4ec <tcp_get_next_optbyte+0x60>)
- 800b4a2:	681b      	ldr	r3, [r3, #0]
- 800b4a4:	2b00      	cmp	r3, #0
- 800b4a6:	d004      	beq.n	800b4b2 <tcp_get_next_optbyte+0x26>
- 800b4a8:	4b11      	ldr	r3, [pc, #68]	; (800b4f0 <tcp_get_next_optbyte+0x64>)
- 800b4aa:	881b      	ldrh	r3, [r3, #0]
- 800b4ac:	88fa      	ldrh	r2, [r7, #6]
- 800b4ae:	429a      	cmp	r2, r3
- 800b4b0:	d208      	bcs.n	800b4c4 <tcp_get_next_optbyte+0x38>
-    u8_t *opts = (u8_t *)tcphdr + TCP_HLEN;
- 800b4b2:	4b10      	ldr	r3, [pc, #64]	; (800b4f4 <tcp_get_next_optbyte+0x68>)
- 800b4b4:	681b      	ldr	r3, [r3, #0]
- 800b4b6:	3314      	adds	r3, #20
- 800b4b8:	603b      	str	r3, [r7, #0]
-    return opts[optidx];
- 800b4ba:	88fb      	ldrh	r3, [r7, #6]
- 800b4bc:	683a      	ldr	r2, [r7, #0]
- 800b4be:	4413      	add	r3, r2
- 800b4c0:	781b      	ldrb	r3, [r3, #0]
- 800b4c2:	e00b      	b.n	800b4dc <tcp_get_next_optbyte+0x50>
-  } else {
-    u8_t idx = (u8_t)(optidx - tcphdr_opt1len);
- 800b4c4:	88fb      	ldrh	r3, [r7, #6]
- 800b4c6:	b2da      	uxtb	r2, r3
- 800b4c8:	4b09      	ldr	r3, [pc, #36]	; (800b4f0 <tcp_get_next_optbyte+0x64>)
- 800b4ca:	881b      	ldrh	r3, [r3, #0]
- 800b4cc:	b2db      	uxtb	r3, r3
- 800b4ce:	1ad3      	subs	r3, r2, r3
- 800b4d0:	717b      	strb	r3, [r7, #5]
-    return tcphdr_opt2[idx];
- 800b4d2:	4b06      	ldr	r3, [pc, #24]	; (800b4ec <tcp_get_next_optbyte+0x60>)
- 800b4d4:	681a      	ldr	r2, [r3, #0]
- 800b4d6:	797b      	ldrb	r3, [r7, #5]
- 800b4d8:	4413      	add	r3, r2
- 800b4da:	781b      	ldrb	r3, [r3, #0]
-  }
-}
- 800b4dc:	4618      	mov	r0, r3
- 800b4de:	370c      	adds	r7, #12
- 800b4e0:	46bd      	mov	sp, r7
- 800b4e2:	f85d 7b04 	ldr.w	r7, [sp], #4
- 800b4e6:	4770      	bx	lr
- 800b4e8:	24007ba4 	.word	0x24007ba4
- 800b4ec:	24007ba0 	.word	0x24007ba0
- 800b4f0:	24007b9e 	.word	0x24007b9e
- 800b4f4:	24007b98 	.word	0x24007b98
-
-0800b4f8 <tcp_parseopt>:
- *
- * @param pcb the tcp_pcb for which a segment arrived
- */
-static void
-tcp_parseopt(struct tcp_pcb *pcb)
-{
- 800b4f8:	b580      	push	{r7, lr}
- 800b4fa:	b084      	sub	sp, #16
- 800b4fc:	af00      	add	r7, sp, #0
- 800b4fe:	6078      	str	r0, [r7, #4]
-  u16_t mss;
-#if LWIP_TCP_TIMESTAMPS
-  u32_t tsval;
-#endif
-
-  LWIP_ASSERT("tcp_parseopt: invalid pcb", pcb != NULL);
- 800b500:	687b      	ldr	r3, [r7, #4]
- 800b502:	2b00      	cmp	r3, #0
- 800b504:	d106      	bne.n	800b514 <tcp_parseopt+0x1c>
- 800b506:	4b32      	ldr	r3, [pc, #200]	; (800b5d0 <tcp_parseopt+0xd8>)
- 800b508:	f240 727d 	movw	r2, #1917	; 0x77d
- 800b50c:	4931      	ldr	r1, [pc, #196]	; (800b5d4 <tcp_parseopt+0xdc>)
- 800b50e:	4832      	ldr	r0, [pc, #200]	; (800b5d8 <tcp_parseopt+0xe0>)
- 800b510:	f005 fb5a 	bl	8010bc8 <iprintf>
-
-  /* Parse the TCP MSS option, if present. */
-  if (tcphdr_optlen != 0) {
- 800b514:	4b31      	ldr	r3, [pc, #196]	; (800b5dc <tcp_parseopt+0xe4>)
- 800b516:	881b      	ldrh	r3, [r3, #0]
- 800b518:	2b00      	cmp	r3, #0
- 800b51a:	d055      	beq.n	800b5c8 <tcp_parseopt+0xd0>
-    for (tcp_optidx = 0; tcp_optidx < tcphdr_optlen; ) {
- 800b51c:	4b30      	ldr	r3, [pc, #192]	; (800b5e0 <tcp_parseopt+0xe8>)
- 800b51e:	2200      	movs	r2, #0
- 800b520:	801a      	strh	r2, [r3, #0]
- 800b522:	e045      	b.n	800b5b0 <tcp_parseopt+0xb8>
-      u8_t opt = tcp_get_next_optbyte();
- 800b524:	f7ff ffb2 	bl	800b48c <tcp_get_next_optbyte>
- 800b528:	4603      	mov	r3, r0
- 800b52a:	73fb      	strb	r3, [r7, #15]
-      switch (opt) {
- 800b52c:	7bfb      	ldrb	r3, [r7, #15]
- 800b52e:	2b02      	cmp	r3, #2
- 800b530:	d006      	beq.n	800b540 <tcp_parseopt+0x48>
- 800b532:	2b02      	cmp	r3, #2
- 800b534:	dc2b      	bgt.n	800b58e <tcp_parseopt+0x96>
- 800b536:	2b00      	cmp	r3, #0
- 800b538:	d041      	beq.n	800b5be <tcp_parseopt+0xc6>
- 800b53a:	2b01      	cmp	r3, #1
- 800b53c:	d127      	bne.n	800b58e <tcp_parseopt+0x96>
-          LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_parseopt: EOL\n"));
-          return;
-        case LWIP_TCP_OPT_NOP:
-          /* NOP option. */
-          LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_parseopt: NOP\n"));
-          break;
- 800b53e:	e037      	b.n	800b5b0 <tcp_parseopt+0xb8>
-        case LWIP_TCP_OPT_MSS:
-          LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_parseopt: MSS\n"));
-          if (tcp_get_next_optbyte() != LWIP_TCP_OPT_LEN_MSS || (tcp_optidx - 2 + LWIP_TCP_OPT_LEN_MSS) > tcphdr_optlen) {
- 800b540:	f7ff ffa4 	bl	800b48c <tcp_get_next_optbyte>
- 800b544:	4603      	mov	r3, r0
- 800b546:	2b04      	cmp	r3, #4
- 800b548:	d13b      	bne.n	800b5c2 <tcp_parseopt+0xca>
- 800b54a:	4b25      	ldr	r3, [pc, #148]	; (800b5e0 <tcp_parseopt+0xe8>)
- 800b54c:	881b      	ldrh	r3, [r3, #0]
- 800b54e:	3301      	adds	r3, #1
- 800b550:	4a22      	ldr	r2, [pc, #136]	; (800b5dc <tcp_parseopt+0xe4>)
- 800b552:	8812      	ldrh	r2, [r2, #0]
- 800b554:	4293      	cmp	r3, r2
- 800b556:	da34      	bge.n	800b5c2 <tcp_parseopt+0xca>
-            /* Bad length */
-            LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_parseopt: bad length\n"));
-            return;
-          }
-          /* An MSS option with the right option length. */
-          mss = (u16_t)(tcp_get_next_optbyte() << 8);
- 800b558:	f7ff ff98 	bl	800b48c <tcp_get_next_optbyte>
- 800b55c:	4603      	mov	r3, r0
- 800b55e:	b29b      	uxth	r3, r3
- 800b560:	021b      	lsls	r3, r3, #8
- 800b562:	81bb      	strh	r3, [r7, #12]
-          mss |= tcp_get_next_optbyte();
- 800b564:	f7ff ff92 	bl	800b48c <tcp_get_next_optbyte>
- 800b568:	4603      	mov	r3, r0
- 800b56a:	b29a      	uxth	r2, r3
- 800b56c:	89bb      	ldrh	r3, [r7, #12]
- 800b56e:	4313      	orrs	r3, r2
- 800b570:	81bb      	strh	r3, [r7, #12]
-          /* Limit the mss to the configured TCP_MSS and prevent division by zero */
-          pcb->mss = ((mss > TCP_MSS) || (mss == 0)) ? TCP_MSS : mss;
- 800b572:	89bb      	ldrh	r3, [r7, #12]
- 800b574:	f5b3 7f06 	cmp.w	r3, #536	; 0x218
- 800b578:	d804      	bhi.n	800b584 <tcp_parseopt+0x8c>
- 800b57a:	89bb      	ldrh	r3, [r7, #12]
- 800b57c:	2b00      	cmp	r3, #0
- 800b57e:	d001      	beq.n	800b584 <tcp_parseopt+0x8c>
- 800b580:	89ba      	ldrh	r2, [r7, #12]
- 800b582:	e001      	b.n	800b588 <tcp_parseopt+0x90>
- 800b584:	f44f 7206 	mov.w	r2, #536	; 0x218
- 800b588:	687b      	ldr	r3, [r7, #4]
- 800b58a:	865a      	strh	r2, [r3, #50]	; 0x32
-          break;
- 800b58c:	e010      	b.n	800b5b0 <tcp_parseopt+0xb8>
-          }
-          break;
-#endif /* LWIP_TCP_SACK_OUT */
-        default:
-          LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_parseopt: other\n"));
-          data = tcp_get_next_optbyte();
- 800b58e:	f7ff ff7d 	bl	800b48c <tcp_get_next_optbyte>
- 800b592:	4603      	mov	r3, r0
- 800b594:	72fb      	strb	r3, [r7, #11]
-          if (data < 2) {
- 800b596:	7afb      	ldrb	r3, [r7, #11]
- 800b598:	2b01      	cmp	r3, #1
- 800b59a:	d914      	bls.n	800b5c6 <tcp_parseopt+0xce>
-               and we don't process them further. */
-            return;
-          }
-          /* All other options have a length field, so that we easily
-             can skip past them. */
-          tcp_optidx += data - 2;
- 800b59c:	7afb      	ldrb	r3, [r7, #11]
- 800b59e:	b29a      	uxth	r2, r3
- 800b5a0:	4b0f      	ldr	r3, [pc, #60]	; (800b5e0 <tcp_parseopt+0xe8>)
- 800b5a2:	881b      	ldrh	r3, [r3, #0]
- 800b5a4:	4413      	add	r3, r2
- 800b5a6:	b29b      	uxth	r3, r3
- 800b5a8:	3b02      	subs	r3, #2
- 800b5aa:	b29a      	uxth	r2, r3
- 800b5ac:	4b0c      	ldr	r3, [pc, #48]	; (800b5e0 <tcp_parseopt+0xe8>)
- 800b5ae:	801a      	strh	r2, [r3, #0]
-    for (tcp_optidx = 0; tcp_optidx < tcphdr_optlen; ) {
- 800b5b0:	4b0b      	ldr	r3, [pc, #44]	; (800b5e0 <tcp_parseopt+0xe8>)
- 800b5b2:	881a      	ldrh	r2, [r3, #0]
- 800b5b4:	4b09      	ldr	r3, [pc, #36]	; (800b5dc <tcp_parseopt+0xe4>)
- 800b5b6:	881b      	ldrh	r3, [r3, #0]
- 800b5b8:	429a      	cmp	r2, r3
- 800b5ba:	d3b3      	bcc.n	800b524 <tcp_parseopt+0x2c>
- 800b5bc:	e004      	b.n	800b5c8 <tcp_parseopt+0xd0>
-          return;
- 800b5be:	bf00      	nop
- 800b5c0:	e002      	b.n	800b5c8 <tcp_parseopt+0xd0>
-            return;
- 800b5c2:	bf00      	nop
- 800b5c4:	e000      	b.n	800b5c8 <tcp_parseopt+0xd0>
-            return;
- 800b5c6:	bf00      	nop
-      }
-    }
-  }
-}
- 800b5c8:	3710      	adds	r7, #16
- 800b5ca:	46bd      	mov	sp, r7
- 800b5cc:	bd80      	pop	{r7, pc}
- 800b5ce:	bf00      	nop
- 800b5d0:	08013198 	.word	0x08013198
- 800b5d4:	080135fc 	.word	0x080135fc
- 800b5d8:	080131e4 	.word	0x080131e4
- 800b5dc:	24007b9c 	.word	0x24007b9c
- 800b5e0:	24007ba4 	.word	0x24007ba4
-
-0800b5e4 <tcp_trigger_input_pcb_close>:
-
-void
-tcp_trigger_input_pcb_close(void)
-{
- 800b5e4:	b480      	push	{r7}
- 800b5e6:	af00      	add	r7, sp, #0
-  recv_flags |= TF_CLOSED;
- 800b5e8:	4b05      	ldr	r3, [pc, #20]	; (800b600 <tcp_trigger_input_pcb_close+0x1c>)
- 800b5ea:	781b      	ldrb	r3, [r3, #0]
- 800b5ec:	f043 0310 	orr.w	r3, r3, #16
- 800b5f0:	b2da      	uxtb	r2, r3
- 800b5f2:	4b03      	ldr	r3, [pc, #12]	; (800b600 <tcp_trigger_input_pcb_close+0x1c>)
- 800b5f4:	701a      	strb	r2, [r3, #0]
-}
- 800b5f6:	bf00      	nop
- 800b5f8:	46bd      	mov	sp, r7
- 800b5fa:	f85d 7b04 	ldr.w	r7, [sp], #4
- 800b5fe:	4770      	bx	lr
- 800b600:	24007bb5 	.word	0x24007bb5
-
-0800b604 <tcp_route>:
-static err_t tcp_output_segment(struct tcp_seg *seg, struct tcp_pcb *pcb, struct netif *netif);
-
-/* tcp_route: common code that returns a fixed bound netif or calls ip_route */
-static struct netif *
-tcp_route(const struct tcp_pcb *pcb, const ip_addr_t *src, const ip_addr_t *dst)
-{
- 800b604:	b580      	push	{r7, lr}
- 800b606:	b084      	sub	sp, #16
- 800b608:	af00      	add	r7, sp, #0
- 800b60a:	60f8      	str	r0, [r7, #12]
- 800b60c:	60b9      	str	r1, [r7, #8]
- 800b60e:	607a      	str	r2, [r7, #4]
-  LWIP_UNUSED_ARG(src); /* in case IPv4-only and source-based routing is disabled */
-
-  if ((pcb != NULL) && (pcb->netif_idx != NETIF_NO_INDEX)) {
- 800b610:	68fb      	ldr	r3, [r7, #12]
- 800b612:	2b00      	cmp	r3, #0
- 800b614:	d00a      	beq.n	800b62c <tcp_route+0x28>
- 800b616:	68fb      	ldr	r3, [r7, #12]
- 800b618:	7a1b      	ldrb	r3, [r3, #8]
- 800b61a:	2b00      	cmp	r3, #0
- 800b61c:	d006      	beq.n	800b62c <tcp_route+0x28>
-    return netif_get_by_index(pcb->netif_idx);
- 800b61e:	68fb      	ldr	r3, [r7, #12]
- 800b620:	7a1b      	ldrb	r3, [r3, #8]
- 800b622:	4618      	mov	r0, r3
- 800b624:	f7fb f976 	bl	8006914 <netif_get_by_index>
- 800b628:	4603      	mov	r3, r0
- 800b62a:	e003      	b.n	800b634 <tcp_route+0x30>
-  } else {
-    return ip_route(src, dst);
- 800b62c:	6878      	ldr	r0, [r7, #4]
- 800b62e:	f003 fc2b 	bl	800ee88 <ip4_route>
- 800b632:	4603      	mov	r3, r0
-  }
-}
- 800b634:	4618      	mov	r0, r3
- 800b636:	3710      	adds	r7, #16
- 800b638:	46bd      	mov	sp, r7
- 800b63a:	bd80      	pop	{r7, pc}
-
-0800b63c <tcp_create_segment>:
- * The TCP header is filled in except ackno and wnd.
- * p is freed on failure.
- */
-static struct tcp_seg *
-tcp_create_segment(const struct tcp_pcb *pcb, struct pbuf *p, u8_t hdrflags, u32_t seqno, u8_t optflags)
-{
- 800b63c:	b590      	push	{r4, r7, lr}
- 800b63e:	b087      	sub	sp, #28
- 800b640:	af00      	add	r7, sp, #0
- 800b642:	60f8      	str	r0, [r7, #12]
- 800b644:	60b9      	str	r1, [r7, #8]
- 800b646:	603b      	str	r3, [r7, #0]
- 800b648:	4613      	mov	r3, r2
- 800b64a:	71fb      	strb	r3, [r7, #7]
-  struct tcp_seg *seg;
-  u8_t optlen;
-
-  LWIP_ASSERT("tcp_create_segment: invalid pcb", pcb != NULL);
- 800b64c:	68fb      	ldr	r3, [r7, #12]
- 800b64e:	2b00      	cmp	r3, #0
- 800b650:	d105      	bne.n	800b65e <tcp_create_segment+0x22>
- 800b652:	4b45      	ldr	r3, [pc, #276]	; (800b768 <tcp_create_segment+0x12c>)
- 800b654:	22a3      	movs	r2, #163	; 0xa3
- 800b656:	4945      	ldr	r1, [pc, #276]	; (800b76c <tcp_create_segment+0x130>)
- 800b658:	4845      	ldr	r0, [pc, #276]	; (800b770 <tcp_create_segment+0x134>)
- 800b65a:	f005 fab5 	bl	8010bc8 <iprintf>
-  LWIP_ASSERT("tcp_create_segment: invalid pbuf", p != NULL);
- 800b65e:	68bb      	ldr	r3, [r7, #8]
- 800b660:	2b00      	cmp	r3, #0
- 800b662:	d105      	bne.n	800b670 <tcp_create_segment+0x34>
- 800b664:	4b40      	ldr	r3, [pc, #256]	; (800b768 <tcp_create_segment+0x12c>)
- 800b666:	22a4      	movs	r2, #164	; 0xa4
- 800b668:	4942      	ldr	r1, [pc, #264]	; (800b774 <tcp_create_segment+0x138>)
- 800b66a:	4841      	ldr	r0, [pc, #260]	; (800b770 <tcp_create_segment+0x134>)
- 800b66c:	f005 faac 	bl	8010bc8 <iprintf>
-
-  optlen = LWIP_TCP_OPT_LENGTH_SEGMENT(optflags, pcb);
- 800b670:	f897 3028 	ldrb.w	r3, [r7, #40]	; 0x28
- 800b674:	009b      	lsls	r3, r3, #2
- 800b676:	b2db      	uxtb	r3, r3
- 800b678:	f003 0304 	and.w	r3, r3, #4
- 800b67c:	75fb      	strb	r3, [r7, #23]
-
-  if ((seg = (struct tcp_seg *)memp_malloc(MEMP_TCP_SEG)) == NULL) {
- 800b67e:	2003      	movs	r0, #3
- 800b680:	f7fa fccc 	bl	800601c <memp_malloc>
- 800b684:	6138      	str	r0, [r7, #16]
- 800b686:	693b      	ldr	r3, [r7, #16]
- 800b688:	2b00      	cmp	r3, #0
- 800b68a:	d104      	bne.n	800b696 <tcp_create_segment+0x5a>
-    LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("tcp_create_segment: no memory.\n"));
-    pbuf_free(p);
- 800b68c:	68b8      	ldr	r0, [r7, #8]
- 800b68e:	f7fb fca1 	bl	8006fd4 <pbuf_free>
-    return NULL;
- 800b692:	2300      	movs	r3, #0
- 800b694:	e064      	b.n	800b760 <tcp_create_segment+0x124>
-  }
-  seg->flags = optflags;
- 800b696:	693b      	ldr	r3, [r7, #16]
- 800b698:	f897 2028 	ldrb.w	r2, [r7, #40]	; 0x28
- 800b69c:	731a      	strb	r2, [r3, #12]
-  seg->next = NULL;
- 800b69e:	693b      	ldr	r3, [r7, #16]
- 800b6a0:	2200      	movs	r2, #0
- 800b6a2:	601a      	str	r2, [r3, #0]
-  seg->p = p;
- 800b6a4:	693b      	ldr	r3, [r7, #16]
- 800b6a6:	68ba      	ldr	r2, [r7, #8]
- 800b6a8:	605a      	str	r2, [r3, #4]
-  LWIP_ASSERT("p->tot_len >= optlen", p->tot_len >= optlen);
- 800b6aa:	68bb      	ldr	r3, [r7, #8]
- 800b6ac:	891a      	ldrh	r2, [r3, #8]
- 800b6ae:	7dfb      	ldrb	r3, [r7, #23]
- 800b6b0:	b29b      	uxth	r3, r3
- 800b6b2:	429a      	cmp	r2, r3
- 800b6b4:	d205      	bcs.n	800b6c2 <tcp_create_segment+0x86>
- 800b6b6:	4b2c      	ldr	r3, [pc, #176]	; (800b768 <tcp_create_segment+0x12c>)
- 800b6b8:	22b0      	movs	r2, #176	; 0xb0
- 800b6ba:	492f      	ldr	r1, [pc, #188]	; (800b778 <tcp_create_segment+0x13c>)
- 800b6bc:	482c      	ldr	r0, [pc, #176]	; (800b770 <tcp_create_segment+0x134>)
- 800b6be:	f005 fa83 	bl	8010bc8 <iprintf>
-  seg->len = p->tot_len - optlen;
- 800b6c2:	68bb      	ldr	r3, [r7, #8]
- 800b6c4:	891a      	ldrh	r2, [r3, #8]
- 800b6c6:	7dfb      	ldrb	r3, [r7, #23]
- 800b6c8:	b29b      	uxth	r3, r3
- 800b6ca:	1ad3      	subs	r3, r2, r3
- 800b6cc:	b29a      	uxth	r2, r3
- 800b6ce:	693b      	ldr	r3, [r7, #16]
- 800b6d0:	811a      	strh	r2, [r3, #8]
-#if TCP_OVERSIZE_DBGCHECK
-  seg->oversize_left = 0;
- 800b6d2:	693b      	ldr	r3, [r7, #16]
- 800b6d4:	2200      	movs	r2, #0
- 800b6d6:	815a      	strh	r2, [r3, #10]
-  LWIP_ASSERT("invalid optflags passed: TF_SEG_DATA_CHECKSUMMED",
-              (optflags & TF_SEG_DATA_CHECKSUMMED) == 0);
-#endif /* TCP_CHECKSUM_ON_COPY */
-
-  /* build TCP header */
-  if (pbuf_add_header(p, TCP_HLEN)) {
- 800b6d8:	2114      	movs	r1, #20
- 800b6da:	68b8      	ldr	r0, [r7, #8]
- 800b6dc:	f7fb fbe4 	bl	8006ea8 <pbuf_add_header>
- 800b6e0:	4603      	mov	r3, r0
- 800b6e2:	2b00      	cmp	r3, #0
- 800b6e4:	d004      	beq.n	800b6f0 <tcp_create_segment+0xb4>
-    LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("tcp_create_segment: no room for TCP header in pbuf.\n"));
-    TCP_STATS_INC(tcp.err);
-    tcp_seg_free(seg);
- 800b6e6:	6938      	ldr	r0, [r7, #16]
- 800b6e8:	f7fd f845 	bl	8008776 <tcp_seg_free>
-    return NULL;
- 800b6ec:	2300      	movs	r3, #0
- 800b6ee:	e037      	b.n	800b760 <tcp_create_segment+0x124>
-  }
-  seg->tcphdr = (struct tcp_hdr *)seg->p->payload;
- 800b6f0:	693b      	ldr	r3, [r7, #16]
- 800b6f2:	685b      	ldr	r3, [r3, #4]
- 800b6f4:	685a      	ldr	r2, [r3, #4]
- 800b6f6:	693b      	ldr	r3, [r7, #16]
- 800b6f8:	611a      	str	r2, [r3, #16]
-  seg->tcphdr->src = lwip_htons(pcb->local_port);
- 800b6fa:	68fb      	ldr	r3, [r7, #12]
- 800b6fc:	8ada      	ldrh	r2, [r3, #22]
- 800b6fe:	693b      	ldr	r3, [r7, #16]
- 800b700:	691c      	ldr	r4, [r3, #16]
- 800b702:	4610      	mov	r0, r2
- 800b704:	f7f9 ff22 	bl	800554c <lwip_htons>
- 800b708:	4603      	mov	r3, r0
- 800b70a:	8023      	strh	r3, [r4, #0]
-  seg->tcphdr->dest = lwip_htons(pcb->remote_port);
- 800b70c:	68fb      	ldr	r3, [r7, #12]
- 800b70e:	8b1a      	ldrh	r2, [r3, #24]
- 800b710:	693b      	ldr	r3, [r7, #16]
- 800b712:	691c      	ldr	r4, [r3, #16]
- 800b714:	4610      	mov	r0, r2
- 800b716:	f7f9 ff19 	bl	800554c <lwip_htons>
- 800b71a:	4603      	mov	r3, r0
- 800b71c:	8063      	strh	r3, [r4, #2]
-  seg->tcphdr->seqno = lwip_htonl(seqno);
- 800b71e:	693b      	ldr	r3, [r7, #16]
- 800b720:	691c      	ldr	r4, [r3, #16]
- 800b722:	6838      	ldr	r0, [r7, #0]
- 800b724:	f7f9 ff27 	bl	8005576 <lwip_htonl>
- 800b728:	4603      	mov	r3, r0
- 800b72a:	6063      	str	r3, [r4, #4]
-  /* ackno is set in tcp_output */
-  TCPH_HDRLEN_FLAGS_SET(seg->tcphdr, (5 + optlen / 4), hdrflags);
- 800b72c:	7dfb      	ldrb	r3, [r7, #23]
- 800b72e:	089b      	lsrs	r3, r3, #2
- 800b730:	b2db      	uxtb	r3, r3
- 800b732:	b29b      	uxth	r3, r3
- 800b734:	3305      	adds	r3, #5
- 800b736:	b29b      	uxth	r3, r3
- 800b738:	031b      	lsls	r3, r3, #12
- 800b73a:	b29a      	uxth	r2, r3
- 800b73c:	79fb      	ldrb	r3, [r7, #7]
- 800b73e:	b29b      	uxth	r3, r3
- 800b740:	4313      	orrs	r3, r2
- 800b742:	b29a      	uxth	r2, r3
- 800b744:	693b      	ldr	r3, [r7, #16]
- 800b746:	691c      	ldr	r4, [r3, #16]
- 800b748:	4610      	mov	r0, r2
- 800b74a:	f7f9 feff 	bl	800554c <lwip_htons>
- 800b74e:	4603      	mov	r3, r0
- 800b750:	81a3      	strh	r3, [r4, #12]
-  /* wnd and chksum are set in tcp_output */
-  seg->tcphdr->urgp = 0;
- 800b752:	693b      	ldr	r3, [r7, #16]
- 800b754:	691b      	ldr	r3, [r3, #16]
- 800b756:	2200      	movs	r2, #0
- 800b758:	749a      	strb	r2, [r3, #18]
- 800b75a:	2200      	movs	r2, #0
- 800b75c:	74da      	strb	r2, [r3, #19]
-  return seg;
- 800b75e:	693b      	ldr	r3, [r7, #16]
-}
- 800b760:	4618      	mov	r0, r3
- 800b762:	371c      	adds	r7, #28
- 800b764:	46bd      	mov	sp, r7
- 800b766:	bd90      	pop	{r4, r7, pc}
- 800b768:	08013618 	.word	0x08013618
- 800b76c:	0801364c 	.word	0x0801364c
- 800b770:	0801366c 	.word	0x0801366c
- 800b774:	08013694 	.word	0x08013694
- 800b778:	080136b8 	.word	0x080136b8
-
-0800b77c <tcp_pbuf_prealloc>:
-#if TCP_OVERSIZE
-static struct pbuf *
-tcp_pbuf_prealloc(pbuf_layer layer, u16_t length, u16_t max_length,
-                  u16_t *oversize, const struct tcp_pcb *pcb, u8_t apiflags,
-                  u8_t first_seg)
-{
- 800b77c:	b580      	push	{r7, lr}
- 800b77e:	b086      	sub	sp, #24
- 800b780:	af00      	add	r7, sp, #0
- 800b782:	607b      	str	r3, [r7, #4]
- 800b784:	4603      	mov	r3, r0
- 800b786:	73fb      	strb	r3, [r7, #15]
- 800b788:	460b      	mov	r3, r1
- 800b78a:	81bb      	strh	r3, [r7, #12]
- 800b78c:	4613      	mov	r3, r2
- 800b78e:	817b      	strh	r3, [r7, #10]
-  struct pbuf *p;
-  u16_t alloc = length;
- 800b790:	89bb      	ldrh	r3, [r7, #12]
- 800b792:	82fb      	strh	r3, [r7, #22]
-
-  LWIP_ASSERT("tcp_pbuf_prealloc: invalid oversize", oversize != NULL);
- 800b794:	687b      	ldr	r3, [r7, #4]
- 800b796:	2b00      	cmp	r3, #0
- 800b798:	d105      	bne.n	800b7a6 <tcp_pbuf_prealloc+0x2a>
- 800b79a:	4b30      	ldr	r3, [pc, #192]	; (800b85c <tcp_pbuf_prealloc+0xe0>)
- 800b79c:	22e8      	movs	r2, #232	; 0xe8
- 800b79e:	4930      	ldr	r1, [pc, #192]	; (800b860 <tcp_pbuf_prealloc+0xe4>)
- 800b7a0:	4830      	ldr	r0, [pc, #192]	; (800b864 <tcp_pbuf_prealloc+0xe8>)
- 800b7a2:	f005 fa11 	bl	8010bc8 <iprintf>
-  LWIP_ASSERT("tcp_pbuf_prealloc: invalid pcb", pcb != NULL);
- 800b7a6:	6a3b      	ldr	r3, [r7, #32]
- 800b7a8:	2b00      	cmp	r3, #0
- 800b7aa:	d105      	bne.n	800b7b8 <tcp_pbuf_prealloc+0x3c>
- 800b7ac:	4b2b      	ldr	r3, [pc, #172]	; (800b85c <tcp_pbuf_prealloc+0xe0>)
- 800b7ae:	22e9      	movs	r2, #233	; 0xe9
- 800b7b0:	492d      	ldr	r1, [pc, #180]	; (800b868 <tcp_pbuf_prealloc+0xec>)
- 800b7b2:	482c      	ldr	r0, [pc, #176]	; (800b864 <tcp_pbuf_prealloc+0xe8>)
- 800b7b4:	f005 fa08 	bl	8010bc8 <iprintf>
-  LWIP_UNUSED_ARG(pcb);
-  LWIP_UNUSED_ARG(apiflags);
-  LWIP_UNUSED_ARG(first_seg);
-  alloc = max_length;
-#else /* LWIP_NETIF_TX_SINGLE_PBUF */
-  if (length < max_length) {
- 800b7b8:	89ba      	ldrh	r2, [r7, #12]
- 800b7ba:	897b      	ldrh	r3, [r7, #10]
- 800b7bc:	429a      	cmp	r2, r3
- 800b7be:	d221      	bcs.n	800b804 <tcp_pbuf_prealloc+0x88>
-     *
-     * Did the user set TCP_WRITE_FLAG_MORE?
-     *
-     * Will the Nagle algorithm defer transmission of this segment?
-     */
-    if ((apiflags & TCP_WRITE_FLAG_MORE) ||
- 800b7c0:	f897 3024 	ldrb.w	r3, [r7, #36]	; 0x24
- 800b7c4:	f003 0302 	and.w	r3, r3, #2
- 800b7c8:	2b00      	cmp	r3, #0
- 800b7ca:	d111      	bne.n	800b7f0 <tcp_pbuf_prealloc+0x74>
-        (!(pcb->flags & TF_NODELAY) &&
- 800b7cc:	6a3b      	ldr	r3, [r7, #32]
- 800b7ce:	8b5b      	ldrh	r3, [r3, #26]
- 800b7d0:	f003 0340 	and.w	r3, r3, #64	; 0x40
-    if ((apiflags & TCP_WRITE_FLAG_MORE) ||
- 800b7d4:	2b00      	cmp	r3, #0
- 800b7d6:	d115      	bne.n	800b804 <tcp_pbuf_prealloc+0x88>
-        (!(pcb->flags & TF_NODELAY) &&
- 800b7d8:	f897 3028 	ldrb.w	r3, [r7, #40]	; 0x28
- 800b7dc:	2b00      	cmp	r3, #0
- 800b7de:	d007      	beq.n	800b7f0 <tcp_pbuf_prealloc+0x74>
-         (!first_seg ||
-          pcb->unsent != NULL ||
- 800b7e0:	6a3b      	ldr	r3, [r7, #32]
- 800b7e2:	6edb      	ldr	r3, [r3, #108]	; 0x6c
-         (!first_seg ||
- 800b7e4:	2b00      	cmp	r3, #0
- 800b7e6:	d103      	bne.n	800b7f0 <tcp_pbuf_prealloc+0x74>
-          pcb->unacked != NULL))) {
- 800b7e8:	6a3b      	ldr	r3, [r7, #32]
- 800b7ea:	6f1b      	ldr	r3, [r3, #112]	; 0x70
-          pcb->unsent != NULL ||
- 800b7ec:	2b00      	cmp	r3, #0
- 800b7ee:	d009      	beq.n	800b804 <tcp_pbuf_prealloc+0x88>
-      alloc = LWIP_MIN(max_length, LWIP_MEM_ALIGN_SIZE(TCP_OVERSIZE_CALC_LENGTH(length)));
- 800b7f0:	89bb      	ldrh	r3, [r7, #12]
- 800b7f2:	f203 231b 	addw	r3, r3, #539	; 0x21b
- 800b7f6:	f023 0203 	bic.w	r2, r3, #3
- 800b7fa:	897b      	ldrh	r3, [r7, #10]
- 800b7fc:	4293      	cmp	r3, r2
- 800b7fe:	bf28      	it	cs
- 800b800:	4613      	movcs	r3, r2
- 800b802:	82fb      	strh	r3, [r7, #22]
-    }
-  }
-#endif /* LWIP_NETIF_TX_SINGLE_PBUF */
-  p = pbuf_alloc(layer, alloc, PBUF_RAM);
- 800b804:	8af9      	ldrh	r1, [r7, #22]
- 800b806:	7bfb      	ldrb	r3, [r7, #15]
- 800b808:	f44f 7220 	mov.w	r2, #640	; 0x280
- 800b80c:	4618      	mov	r0, r3
- 800b80e:	f7fb f8fd 	bl	8006a0c <pbuf_alloc>
- 800b812:	6138      	str	r0, [r7, #16]
-  if (p == NULL) {
- 800b814:	693b      	ldr	r3, [r7, #16]
- 800b816:	2b00      	cmp	r3, #0
- 800b818:	d101      	bne.n	800b81e <tcp_pbuf_prealloc+0xa2>
-    return NULL;
- 800b81a:	2300      	movs	r3, #0
- 800b81c:	e019      	b.n	800b852 <tcp_pbuf_prealloc+0xd6>
-  }
-  LWIP_ASSERT("need unchained pbuf", p->next == NULL);
- 800b81e:	693b      	ldr	r3, [r7, #16]
- 800b820:	681b      	ldr	r3, [r3, #0]
- 800b822:	2b00      	cmp	r3, #0
- 800b824:	d006      	beq.n	800b834 <tcp_pbuf_prealloc+0xb8>
- 800b826:	4b0d      	ldr	r3, [pc, #52]	; (800b85c <tcp_pbuf_prealloc+0xe0>)
- 800b828:	f240 120b 	movw	r2, #267	; 0x10b
- 800b82c:	490f      	ldr	r1, [pc, #60]	; (800b86c <tcp_pbuf_prealloc+0xf0>)
- 800b82e:	480d      	ldr	r0, [pc, #52]	; (800b864 <tcp_pbuf_prealloc+0xe8>)
- 800b830:	f005 f9ca 	bl	8010bc8 <iprintf>
-  *oversize = p->len - length;
- 800b834:	693b      	ldr	r3, [r7, #16]
- 800b836:	895a      	ldrh	r2, [r3, #10]
- 800b838:	89bb      	ldrh	r3, [r7, #12]
- 800b83a:	1ad3      	subs	r3, r2, r3
- 800b83c:	b29a      	uxth	r2, r3
- 800b83e:	687b      	ldr	r3, [r7, #4]
- 800b840:	801a      	strh	r2, [r3, #0]
-  /* trim p->len to the currently used size */
-  p->len = p->tot_len = length;
- 800b842:	693b      	ldr	r3, [r7, #16]
- 800b844:	89ba      	ldrh	r2, [r7, #12]
- 800b846:	811a      	strh	r2, [r3, #8]
- 800b848:	693b      	ldr	r3, [r7, #16]
- 800b84a:	891a      	ldrh	r2, [r3, #8]
- 800b84c:	693b      	ldr	r3, [r7, #16]
- 800b84e:	815a      	strh	r2, [r3, #10]
-  return p;
- 800b850:	693b      	ldr	r3, [r7, #16]
-}
- 800b852:	4618      	mov	r0, r3
- 800b854:	3718      	adds	r7, #24
- 800b856:	46bd      	mov	sp, r7
- 800b858:	bd80      	pop	{r7, pc}
- 800b85a:	bf00      	nop
- 800b85c:	08013618 	.word	0x08013618
- 800b860:	080136d0 	.word	0x080136d0
- 800b864:	0801366c 	.word	0x0801366c
- 800b868:	080136f4 	.word	0x080136f4
- 800b86c:	08013714 	.word	0x08013714
-
-0800b870 <tcp_write_checks>:
- * @param len length of data to send (checked agains snd_buf)
- * @return ERR_OK if tcp_write is allowed to proceed, another err_t otherwise
- */
-static err_t
-tcp_write_checks(struct tcp_pcb *pcb, u16_t len)
-{
- 800b870:	b580      	push	{r7, lr}
- 800b872:	b082      	sub	sp, #8
- 800b874:	af00      	add	r7, sp, #0
- 800b876:	6078      	str	r0, [r7, #4]
- 800b878:	460b      	mov	r3, r1
- 800b87a:	807b      	strh	r3, [r7, #2]
-  LWIP_ASSERT("tcp_write_checks: invalid pcb", pcb != NULL);
- 800b87c:	687b      	ldr	r3, [r7, #4]
- 800b87e:	2b00      	cmp	r3, #0
- 800b880:	d106      	bne.n	800b890 <tcp_write_checks+0x20>
- 800b882:	4b33      	ldr	r3, [pc, #204]	; (800b950 <tcp_write_checks+0xe0>)
- 800b884:	f240 1233 	movw	r2, #307	; 0x133
- 800b888:	4932      	ldr	r1, [pc, #200]	; (800b954 <tcp_write_checks+0xe4>)
- 800b88a:	4833      	ldr	r0, [pc, #204]	; (800b958 <tcp_write_checks+0xe8>)
- 800b88c:	f005 f99c 	bl	8010bc8 <iprintf>
-
-  /* connection is in invalid state for data transmission? */
-  if ((pcb->state != ESTABLISHED) &&
- 800b890:	687b      	ldr	r3, [r7, #4]
- 800b892:	7d1b      	ldrb	r3, [r3, #20]
- 800b894:	2b04      	cmp	r3, #4
- 800b896:	d00e      	beq.n	800b8b6 <tcp_write_checks+0x46>
-      (pcb->state != CLOSE_WAIT) &&
- 800b898:	687b      	ldr	r3, [r7, #4]
- 800b89a:	7d1b      	ldrb	r3, [r3, #20]
-  if ((pcb->state != ESTABLISHED) &&
- 800b89c:	2b07      	cmp	r3, #7
- 800b89e:	d00a      	beq.n	800b8b6 <tcp_write_checks+0x46>
-      (pcb->state != SYN_SENT) &&
- 800b8a0:	687b      	ldr	r3, [r7, #4]
- 800b8a2:	7d1b      	ldrb	r3, [r3, #20]
-      (pcb->state != CLOSE_WAIT) &&
- 800b8a4:	2b02      	cmp	r3, #2
- 800b8a6:	d006      	beq.n	800b8b6 <tcp_write_checks+0x46>
-      (pcb->state != SYN_RCVD)) {
- 800b8a8:	687b      	ldr	r3, [r7, #4]
- 800b8aa:	7d1b      	ldrb	r3, [r3, #20]
-      (pcb->state != SYN_SENT) &&
- 800b8ac:	2b03      	cmp	r3, #3
- 800b8ae:	d002      	beq.n	800b8b6 <tcp_write_checks+0x46>
-    LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_STATE | LWIP_DBG_LEVEL_SEVERE, ("tcp_write() called in invalid state\n"));
-    return ERR_CONN;
- 800b8b0:	f06f 030a 	mvn.w	r3, #10
- 800b8b4:	e048      	b.n	800b948 <tcp_write_checks+0xd8>
-  } else if (len == 0) {
- 800b8b6:	887b      	ldrh	r3, [r7, #2]
- 800b8b8:	2b00      	cmp	r3, #0
- 800b8ba:	d101      	bne.n	800b8c0 <tcp_write_checks+0x50>
-    return ERR_OK;
- 800b8bc:	2300      	movs	r3, #0
- 800b8be:	e043      	b.n	800b948 <tcp_write_checks+0xd8>
-  }
-
-  /* fail on too much data */
-  if (len > pcb->snd_buf) {
- 800b8c0:	687b      	ldr	r3, [r7, #4]
- 800b8c2:	f8b3 3064 	ldrh.w	r3, [r3, #100]	; 0x64
- 800b8c6:	887a      	ldrh	r2, [r7, #2]
- 800b8c8:	429a      	cmp	r2, r3
- 800b8ca:	d909      	bls.n	800b8e0 <tcp_write_checks+0x70>
-    LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_LEVEL_SEVERE, ("tcp_write: too much data (len=%"U16_F" > snd_buf=%"TCPWNDSIZE_F")\n",
-                len, pcb->snd_buf));
-    tcp_set_flags(pcb, TF_NAGLEMEMERR);
- 800b8cc:	687b      	ldr	r3, [r7, #4]
- 800b8ce:	8b5b      	ldrh	r3, [r3, #26]
- 800b8d0:	f043 0380 	orr.w	r3, r3, #128	; 0x80
- 800b8d4:	b29a      	uxth	r2, r3
- 800b8d6:	687b      	ldr	r3, [r7, #4]
- 800b8d8:	835a      	strh	r2, [r3, #26]
-    return ERR_MEM;
- 800b8da:	f04f 33ff 	mov.w	r3, #4294967295
- 800b8de:	e033      	b.n	800b948 <tcp_write_checks+0xd8>
-  LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_write: queuelen: %"TCPWNDSIZE_F"\n", (tcpwnd_size_t)pcb->snd_queuelen));
-
-  /* If total number of pbufs on the unsent/unacked queues exceeds the
-   * configured maximum, return an error */
-  /* check for configured max queuelen and possible overflow */
-  if (pcb->snd_queuelen >= LWIP_MIN(TCP_SND_QUEUELEN, (TCP_SNDQUEUELEN_OVERFLOW + 1))) {
- 800b8e0:	687b      	ldr	r3, [r7, #4]
- 800b8e2:	f8b3 3066 	ldrh.w	r3, [r3, #102]	; 0x66
- 800b8e6:	2b08      	cmp	r3, #8
- 800b8e8:	d909      	bls.n	800b8fe <tcp_write_checks+0x8e>
-    LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_LEVEL_SEVERE, ("tcp_write: too long queue %"U16_F" (max %"U16_F")\n",
-                pcb->snd_queuelen, (u16_t)TCP_SND_QUEUELEN));
-    TCP_STATS_INC(tcp.memerr);
-    tcp_set_flags(pcb, TF_NAGLEMEMERR);
- 800b8ea:	687b      	ldr	r3, [r7, #4]
- 800b8ec:	8b5b      	ldrh	r3, [r3, #26]
- 800b8ee:	f043 0380 	orr.w	r3, r3, #128	; 0x80
- 800b8f2:	b29a      	uxth	r2, r3
- 800b8f4:	687b      	ldr	r3, [r7, #4]
- 800b8f6:	835a      	strh	r2, [r3, #26]
-    return ERR_MEM;
- 800b8f8:	f04f 33ff 	mov.w	r3, #4294967295
- 800b8fc:	e024      	b.n	800b948 <tcp_write_checks+0xd8>
-  }
-  if (pcb->snd_queuelen != 0) {
- 800b8fe:	687b      	ldr	r3, [r7, #4]
- 800b900:	f8b3 3066 	ldrh.w	r3, [r3, #102]	; 0x66
- 800b904:	2b00      	cmp	r3, #0
- 800b906:	d00f      	beq.n	800b928 <tcp_write_checks+0xb8>
-    LWIP_ASSERT("tcp_write: pbufs on queue => at least one queue non-empty",
- 800b908:	687b      	ldr	r3, [r7, #4]
- 800b90a:	6f1b      	ldr	r3, [r3, #112]	; 0x70
- 800b90c:	2b00      	cmp	r3, #0
- 800b90e:	d11a      	bne.n	800b946 <tcp_write_checks+0xd6>
- 800b910:	687b      	ldr	r3, [r7, #4]
- 800b912:	6edb      	ldr	r3, [r3, #108]	; 0x6c
- 800b914:	2b00      	cmp	r3, #0
- 800b916:	d116      	bne.n	800b946 <tcp_write_checks+0xd6>
- 800b918:	4b0d      	ldr	r3, [pc, #52]	; (800b950 <tcp_write_checks+0xe0>)
- 800b91a:	f240 1255 	movw	r2, #341	; 0x155
- 800b91e:	490f      	ldr	r1, [pc, #60]	; (800b95c <tcp_write_checks+0xec>)
- 800b920:	480d      	ldr	r0, [pc, #52]	; (800b958 <tcp_write_checks+0xe8>)
- 800b922:	f005 f951 	bl	8010bc8 <iprintf>
- 800b926:	e00e      	b.n	800b946 <tcp_write_checks+0xd6>
-                pcb->unacked != NULL || pcb->unsent != NULL);
-  } else {
-    LWIP_ASSERT("tcp_write: no pbufs on queue => both queues empty",
- 800b928:	687b      	ldr	r3, [r7, #4]
- 800b92a:	6f1b      	ldr	r3, [r3, #112]	; 0x70
- 800b92c:	2b00      	cmp	r3, #0
- 800b92e:	d103      	bne.n	800b938 <tcp_write_checks+0xc8>
- 800b930:	687b      	ldr	r3, [r7, #4]
- 800b932:	6edb      	ldr	r3, [r3, #108]	; 0x6c
- 800b934:	2b00      	cmp	r3, #0
- 800b936:	d006      	beq.n	800b946 <tcp_write_checks+0xd6>
- 800b938:	4b05      	ldr	r3, [pc, #20]	; (800b950 <tcp_write_checks+0xe0>)
- 800b93a:	f44f 72ac 	mov.w	r2, #344	; 0x158
- 800b93e:	4908      	ldr	r1, [pc, #32]	; (800b960 <tcp_write_checks+0xf0>)
- 800b940:	4805      	ldr	r0, [pc, #20]	; (800b958 <tcp_write_checks+0xe8>)
- 800b942:	f005 f941 	bl	8010bc8 <iprintf>
-                pcb->unacked == NULL && pcb->unsent == NULL);
-  }
-  return ERR_OK;
- 800b946:	2300      	movs	r3, #0
-}
- 800b948:	4618      	mov	r0, r3
- 800b94a:	3708      	adds	r7, #8
- 800b94c:	46bd      	mov	sp, r7
- 800b94e:	bd80      	pop	{r7, pc}
- 800b950:	08013618 	.word	0x08013618
- 800b954:	08013728 	.word	0x08013728
- 800b958:	0801366c 	.word	0x0801366c
- 800b95c:	08013748 	.word	0x08013748
- 800b960:	08013784 	.word	0x08013784
-
-0800b964 <tcp_write>:
- * - TCP_WRITE_FLAG_MORE (0x02) for TCP connection, PSH flag will not be set on last segment sent,
- * @return ERR_OK if enqueued, another err_t on error
- */
-err_t
-tcp_write(struct tcp_pcb *pcb, const void *arg, u16_t len, u8_t apiflags)
-{
- 800b964:	b590      	push	{r4, r7, lr}
- 800b966:	b09d      	sub	sp, #116	; 0x74
- 800b968:	af04      	add	r7, sp, #16
- 800b96a:	60f8      	str	r0, [r7, #12]
- 800b96c:	60b9      	str	r1, [r7, #8]
- 800b96e:	4611      	mov	r1, r2
- 800b970:	461a      	mov	r2, r3
- 800b972:	460b      	mov	r3, r1
- 800b974:	80fb      	strh	r3, [r7, #6]
- 800b976:	4613      	mov	r3, r2
- 800b978:	717b      	strb	r3, [r7, #5]
-  struct pbuf *concat_p = NULL;
- 800b97a:	2300      	movs	r3, #0
- 800b97c:	63fb      	str	r3, [r7, #60]	; 0x3c
-  struct tcp_seg *last_unsent = NULL, *seg = NULL, *prev_seg = NULL, *queue = NULL;
- 800b97e:	2300      	movs	r3, #0
- 800b980:	643b      	str	r3, [r7, #64]	; 0x40
- 800b982:	2300      	movs	r3, #0
- 800b984:	657b      	str	r3, [r7, #84]	; 0x54
- 800b986:	2300      	movs	r3, #0
- 800b988:	653b      	str	r3, [r7, #80]	; 0x50
- 800b98a:	2300      	movs	r3, #0
- 800b98c:	64fb      	str	r3, [r7, #76]	; 0x4c
-  u16_t pos = 0; /* position in 'arg' data */
- 800b98e:	2300      	movs	r3, #0
- 800b990:	f8a7 304a 	strh.w	r3, [r7, #74]	; 0x4a
-  u16_t queuelen;
-  u8_t optlen;
-  u8_t optflags = 0;
- 800b994:	2300      	movs	r3, #0
- 800b996:	f887 302b 	strb.w	r3, [r7, #43]	; 0x2b
-#if TCP_OVERSIZE
-  u16_t oversize = 0;
- 800b99a:	2300      	movs	r3, #0
- 800b99c:	82fb      	strh	r3, [r7, #22]
-  u16_t oversize_used = 0;
- 800b99e:	2300      	movs	r3, #0
- 800b9a0:	f8a7 3046 	strh.w	r3, [r7, #70]	; 0x46
-#if TCP_OVERSIZE_DBGCHECK
-  u16_t oversize_add = 0;
- 800b9a4:	2300      	movs	r3, #0
- 800b9a6:	f8a7 305a 	strh.w	r3, [r7, #90]	; 0x5a
-#endif /* TCP_OVERSIZE_DBGCHECK*/
-#endif /* TCP_OVERSIZE */
-  u16_t extendlen = 0;
- 800b9aa:	2300      	movs	r3, #0
- 800b9ac:	f8a7 305e 	strh.w	r3, [r7, #94]	; 0x5e
-  u16_t concat_chksummed = 0;
-#endif /* TCP_CHECKSUM_ON_COPY */
-  err_t err;
-  u16_t mss_local;
-
-  LWIP_ERROR("tcp_write: invalid pcb", pcb != NULL, return ERR_ARG);
- 800b9b0:	68fb      	ldr	r3, [r7, #12]
- 800b9b2:	2b00      	cmp	r3, #0
- 800b9b4:	d109      	bne.n	800b9ca <tcp_write+0x66>
- 800b9b6:	4b9c      	ldr	r3, [pc, #624]	; (800bc28 <tcp_write+0x2c4>)
- 800b9b8:	f44f 72cf 	mov.w	r2, #414	; 0x19e
- 800b9bc:	499b      	ldr	r1, [pc, #620]	; (800bc2c <tcp_write+0x2c8>)
- 800b9be:	489c      	ldr	r0, [pc, #624]	; (800bc30 <tcp_write+0x2cc>)
- 800b9c0:	f005 f902 	bl	8010bc8 <iprintf>
- 800b9c4:	f06f 030f 	mvn.w	r3, #15
- 800b9c8:	e379      	b.n	800c0be <tcp_write+0x75a>
-
-  /* don't allocate segments bigger than half the maximum window we ever received */
-  mss_local = LWIP_MIN(pcb->mss, TCPWND_MIN16(pcb->snd_wnd_max / 2));
- 800b9ca:	68fb      	ldr	r3, [r7, #12]
- 800b9cc:	f8b3 3062 	ldrh.w	r3, [r3, #98]	; 0x62
- 800b9d0:	085b      	lsrs	r3, r3, #1
- 800b9d2:	b29a      	uxth	r2, r3
- 800b9d4:	68fb      	ldr	r3, [r7, #12]
- 800b9d6:	8e5b      	ldrh	r3, [r3, #50]	; 0x32
- 800b9d8:	4293      	cmp	r3, r2
- 800b9da:	bf28      	it	cs
- 800b9dc:	4613      	movcs	r3, r2
- 800b9de:	853b      	strh	r3, [r7, #40]	; 0x28
-  mss_local = mss_local ? mss_local : pcb->mss;
- 800b9e0:	8d3b      	ldrh	r3, [r7, #40]	; 0x28
- 800b9e2:	2b00      	cmp	r3, #0
- 800b9e4:	d102      	bne.n	800b9ec <tcp_write+0x88>
- 800b9e6:	68fb      	ldr	r3, [r7, #12]
- 800b9e8:	8e5b      	ldrh	r3, [r3, #50]	; 0x32
- 800b9ea:	e000      	b.n	800b9ee <tcp_write+0x8a>
- 800b9ec:	8d3b      	ldrh	r3, [r7, #40]	; 0x28
- 800b9ee:	853b      	strh	r3, [r7, #40]	; 0x28
-  apiflags |= TCP_WRITE_FLAG_COPY;
-#endif /* LWIP_NETIF_TX_SINGLE_PBUF */
-
-  LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_write(pcb=%p, data=%p, len=%"U16_F", apiflags=%"U16_F")\n",
-                                 (void *)pcb, arg, len, (u16_t)apiflags));
-  LWIP_ERROR("tcp_write: arg == NULL (programmer violates API)",
- 800b9f0:	68bb      	ldr	r3, [r7, #8]
- 800b9f2:	2b00      	cmp	r3, #0
- 800b9f4:	d109      	bne.n	800ba0a <tcp_write+0xa6>
- 800b9f6:	4b8c      	ldr	r3, [pc, #560]	; (800bc28 <tcp_write+0x2c4>)
- 800b9f8:	f240 12ad 	movw	r2, #429	; 0x1ad
- 800b9fc:	498d      	ldr	r1, [pc, #564]	; (800bc34 <tcp_write+0x2d0>)
- 800b9fe:	488c      	ldr	r0, [pc, #560]	; (800bc30 <tcp_write+0x2cc>)
- 800ba00:	f005 f8e2 	bl	8010bc8 <iprintf>
- 800ba04:	f06f 030f 	mvn.w	r3, #15
- 800ba08:	e359      	b.n	800c0be <tcp_write+0x75a>
-             arg != NULL, return ERR_ARG;);
-
-  err = tcp_write_checks(pcb, len);
- 800ba0a:	88fb      	ldrh	r3, [r7, #6]
- 800ba0c:	4619      	mov	r1, r3
- 800ba0e:	68f8      	ldr	r0, [r7, #12]
- 800ba10:	f7ff ff2e 	bl	800b870 <tcp_write_checks>
- 800ba14:	4603      	mov	r3, r0
- 800ba16:	f887 3027 	strb.w	r3, [r7, #39]	; 0x27
-  if (err != ERR_OK) {
- 800ba1a:	f997 3027 	ldrsb.w	r3, [r7, #39]	; 0x27
- 800ba1e:	2b00      	cmp	r3, #0
- 800ba20:	d002      	beq.n	800ba28 <tcp_write+0xc4>
-    return err;
- 800ba22:	f997 3027 	ldrsb.w	r3, [r7, #39]	; 0x27
- 800ba26:	e34a      	b.n	800c0be <tcp_write+0x75a>
-  }
-  queuelen = pcb->snd_queuelen;
- 800ba28:	68fb      	ldr	r3, [r7, #12]
- 800ba2a:	f8b3 3066 	ldrh.w	r3, [r3, #102]	; 0x66
- 800ba2e:	f8a7 3048 	strh.w	r3, [r7, #72]	; 0x48
-    /* ensure that segments can hold at least one data byte... */
-    mss_local = LWIP_MAX(mss_local, LWIP_TCP_OPT_LEN_TS + 1);
-  } else
-#endif /* LWIP_TCP_TIMESTAMPS */
-  {
-    optlen = LWIP_TCP_OPT_LENGTH_SEGMENT(0, pcb);
- 800ba32:	2300      	movs	r3, #0
- 800ba34:	f887 3026 	strb.w	r3, [r7, #38]	; 0x26
-   *
-   * pos records progress as data is segmented.
-   */
-
-  /* Find the tail of the unsent queue. */
-  if (pcb->unsent != NULL) {
- 800ba38:	68fb      	ldr	r3, [r7, #12]
- 800ba3a:	6edb      	ldr	r3, [r3, #108]	; 0x6c
- 800ba3c:	2b00      	cmp	r3, #0
- 800ba3e:	f000 8127 	beq.w	800bc90 <tcp_write+0x32c>
-    u16_t space;
-    u16_t unsent_optlen;
-
-    /* @todo: this could be sped up by keeping last_unsent in the pcb */
-    for (last_unsent = pcb->unsent; last_unsent->next != NULL;
- 800ba42:	68fb      	ldr	r3, [r7, #12]
- 800ba44:	6edb      	ldr	r3, [r3, #108]	; 0x6c
- 800ba46:	643b      	str	r3, [r7, #64]	; 0x40
- 800ba48:	e002      	b.n	800ba50 <tcp_write+0xec>
-         last_unsent = last_unsent->next);
- 800ba4a:	6c3b      	ldr	r3, [r7, #64]	; 0x40
- 800ba4c:	681b      	ldr	r3, [r3, #0]
- 800ba4e:	643b      	str	r3, [r7, #64]	; 0x40
-    for (last_unsent = pcb->unsent; last_unsent->next != NULL;
- 800ba50:	6c3b      	ldr	r3, [r7, #64]	; 0x40
- 800ba52:	681b      	ldr	r3, [r3, #0]
- 800ba54:	2b00      	cmp	r3, #0
- 800ba56:	d1f8      	bne.n	800ba4a <tcp_write+0xe6>
-
-    /* Usable space at the end of the last unsent segment */
-    unsent_optlen = LWIP_TCP_OPT_LENGTH_SEGMENT(last_unsent->flags, pcb);
- 800ba58:	6c3b      	ldr	r3, [r7, #64]	; 0x40
- 800ba5a:	7b1b      	ldrb	r3, [r3, #12]
- 800ba5c:	009b      	lsls	r3, r3, #2
- 800ba5e:	b29b      	uxth	r3, r3
- 800ba60:	f003 0304 	and.w	r3, r3, #4
- 800ba64:	84bb      	strh	r3, [r7, #36]	; 0x24
-    LWIP_ASSERT("mss_local is too small", mss_local >= last_unsent->len + unsent_optlen);
- 800ba66:	8d3a      	ldrh	r2, [r7, #40]	; 0x28
- 800ba68:	6c3b      	ldr	r3, [r7, #64]	; 0x40
- 800ba6a:	891b      	ldrh	r3, [r3, #8]
- 800ba6c:	4619      	mov	r1, r3
- 800ba6e:	8cbb      	ldrh	r3, [r7, #36]	; 0x24
- 800ba70:	440b      	add	r3, r1
- 800ba72:	429a      	cmp	r2, r3
- 800ba74:	da06      	bge.n	800ba84 <tcp_write+0x120>
- 800ba76:	4b6c      	ldr	r3, [pc, #432]	; (800bc28 <tcp_write+0x2c4>)
- 800ba78:	f44f 72f3 	mov.w	r2, #486	; 0x1e6
- 800ba7c:	496e      	ldr	r1, [pc, #440]	; (800bc38 <tcp_write+0x2d4>)
- 800ba7e:	486c      	ldr	r0, [pc, #432]	; (800bc30 <tcp_write+0x2cc>)
- 800ba80:	f005 f8a2 	bl	8010bc8 <iprintf>
-    space = mss_local - (last_unsent->len + unsent_optlen);
- 800ba84:	6c3b      	ldr	r3, [r7, #64]	; 0x40
- 800ba86:	891a      	ldrh	r2, [r3, #8]
- 800ba88:	8cbb      	ldrh	r3, [r7, #36]	; 0x24
- 800ba8a:	4413      	add	r3, r2
- 800ba8c:	b29b      	uxth	r3, r3
- 800ba8e:	8d3a      	ldrh	r2, [r7, #40]	; 0x28
- 800ba90:	1ad3      	subs	r3, r2, r3
- 800ba92:	f8a7 305c 	strh.w	r3, [r7, #92]	; 0x5c
-     * function.
-     */
-#if TCP_OVERSIZE
-#if TCP_OVERSIZE_DBGCHECK
-    /* check that pcb->unsent_oversize matches last_unsent->oversize_left */
-    LWIP_ASSERT("unsent_oversize mismatch (pcb vs. last_unsent)",
- 800ba96:	68fb      	ldr	r3, [r7, #12]
- 800ba98:	f8b3 2068 	ldrh.w	r2, [r3, #104]	; 0x68
- 800ba9c:	6c3b      	ldr	r3, [r7, #64]	; 0x40
- 800ba9e:	895b      	ldrh	r3, [r3, #10]
- 800baa0:	429a      	cmp	r2, r3
- 800baa2:	d006      	beq.n	800bab2 <tcp_write+0x14e>
- 800baa4:	4b60      	ldr	r3, [pc, #384]	; (800bc28 <tcp_write+0x2c4>)
- 800baa6:	f240 12f3 	movw	r2, #499	; 0x1f3
- 800baaa:	4964      	ldr	r1, [pc, #400]	; (800bc3c <tcp_write+0x2d8>)
- 800baac:	4860      	ldr	r0, [pc, #384]	; (800bc30 <tcp_write+0x2cc>)
- 800baae:	f005 f88b 	bl	8010bc8 <iprintf>
-                pcb->unsent_oversize == last_unsent->oversize_left);
-#endif /* TCP_OVERSIZE_DBGCHECK */
-    oversize = pcb->unsent_oversize;
- 800bab2:	68fb      	ldr	r3, [r7, #12]
- 800bab4:	f8b3 3068 	ldrh.w	r3, [r3, #104]	; 0x68
- 800bab8:	82fb      	strh	r3, [r7, #22]
-    if (oversize > 0) {
- 800baba:	8afb      	ldrh	r3, [r7, #22]
- 800babc:	2b00      	cmp	r3, #0
- 800babe:	d02e      	beq.n	800bb1e <tcp_write+0x1ba>
-      LWIP_ASSERT("inconsistent oversize vs. space", oversize <= space);
- 800bac0:	8afb      	ldrh	r3, [r7, #22]
- 800bac2:	f8b7 205c 	ldrh.w	r2, [r7, #92]	; 0x5c
- 800bac6:	429a      	cmp	r2, r3
- 800bac8:	d206      	bcs.n	800bad8 <tcp_write+0x174>
- 800baca:	4b57      	ldr	r3, [pc, #348]	; (800bc28 <tcp_write+0x2c4>)
- 800bacc:	f44f 72fc 	mov.w	r2, #504	; 0x1f8
- 800bad0:	495b      	ldr	r1, [pc, #364]	; (800bc40 <tcp_write+0x2dc>)
- 800bad2:	4857      	ldr	r0, [pc, #348]	; (800bc30 <tcp_write+0x2cc>)
- 800bad4:	f005 f878 	bl	8010bc8 <iprintf>
-      seg = last_unsent;
- 800bad8:	6c3b      	ldr	r3, [r7, #64]	; 0x40
- 800bada:	657b      	str	r3, [r7, #84]	; 0x54
-      oversize_used = LWIP_MIN(space, LWIP_MIN(oversize, len));
- 800badc:	8afb      	ldrh	r3, [r7, #22]
- 800bade:	88fa      	ldrh	r2, [r7, #6]
- 800bae0:	4293      	cmp	r3, r2
- 800bae2:	bf28      	it	cs
- 800bae4:	4613      	movcs	r3, r2
- 800bae6:	b29b      	uxth	r3, r3
- 800bae8:	f8b7 205c 	ldrh.w	r2, [r7, #92]	; 0x5c
- 800baec:	4293      	cmp	r3, r2
- 800baee:	bf28      	it	cs
- 800baf0:	4613      	movcs	r3, r2
- 800baf2:	f8a7 3046 	strh.w	r3, [r7, #70]	; 0x46
-      pos += oversize_used;
- 800baf6:	f8b7 204a 	ldrh.w	r2, [r7, #74]	; 0x4a
- 800bafa:	f8b7 3046 	ldrh.w	r3, [r7, #70]	; 0x46
- 800bafe:	4413      	add	r3, r2
- 800bb00:	f8a7 304a 	strh.w	r3, [r7, #74]	; 0x4a
-      oversize -= oversize_used;
- 800bb04:	8afa      	ldrh	r2, [r7, #22]
- 800bb06:	f8b7 3046 	ldrh.w	r3, [r7, #70]	; 0x46
- 800bb0a:	1ad3      	subs	r3, r2, r3
- 800bb0c:	b29b      	uxth	r3, r3
- 800bb0e:	82fb      	strh	r3, [r7, #22]
-      space -= oversize_used;
- 800bb10:	f8b7 205c 	ldrh.w	r2, [r7, #92]	; 0x5c
- 800bb14:	f8b7 3046 	ldrh.w	r3, [r7, #70]	; 0x46
- 800bb18:	1ad3      	subs	r3, r2, r3
- 800bb1a:	f8a7 305c 	strh.w	r3, [r7, #92]	; 0x5c
-    }
-    /* now we are either finished or oversize is zero */
-    LWIP_ASSERT("inconsistent oversize vs. len", (oversize == 0) || (pos == len));
- 800bb1e:	8afb      	ldrh	r3, [r7, #22]
- 800bb20:	2b00      	cmp	r3, #0
- 800bb22:	d00b      	beq.n	800bb3c <tcp_write+0x1d8>
- 800bb24:	f8b7 204a 	ldrh.w	r2, [r7, #74]	; 0x4a
- 800bb28:	88fb      	ldrh	r3, [r7, #6]
- 800bb2a:	429a      	cmp	r2, r3
- 800bb2c:	d006      	beq.n	800bb3c <tcp_write+0x1d8>
- 800bb2e:	4b3e      	ldr	r3, [pc, #248]	; (800bc28 <tcp_write+0x2c4>)
- 800bb30:	f44f 7200 	mov.w	r2, #512	; 0x200
- 800bb34:	4943      	ldr	r1, [pc, #268]	; (800bc44 <tcp_write+0x2e0>)
- 800bb36:	483e      	ldr	r0, [pc, #248]	; (800bc30 <tcp_write+0x2cc>)
- 800bb38:	f005 f846 	bl	8010bc8 <iprintf>
-     *
-     * This phase is skipped for LWIP_NETIF_TX_SINGLE_PBUF as we could only execute
-     * it after rexmit puts a segment from unacked to unsent and at this point,
-     * oversize info is lost.
-     */
-    if ((pos < len) && (space > 0) && (last_unsent->len > 0)) {
- 800bb3c:	f8b7 204a 	ldrh.w	r2, [r7, #74]	; 0x4a
- 800bb40:	88fb      	ldrh	r3, [r7, #6]
- 800bb42:	429a      	cmp	r2, r3
- 800bb44:	f080 8172 	bcs.w	800be2c <tcp_write+0x4c8>
- 800bb48:	f8b7 305c 	ldrh.w	r3, [r7, #92]	; 0x5c
- 800bb4c:	2b00      	cmp	r3, #0
- 800bb4e:	f000 816d 	beq.w	800be2c <tcp_write+0x4c8>
- 800bb52:	6c3b      	ldr	r3, [r7, #64]	; 0x40
- 800bb54:	891b      	ldrh	r3, [r3, #8]
- 800bb56:	2b00      	cmp	r3, #0
- 800bb58:	f000 8168 	beq.w	800be2c <tcp_write+0x4c8>
-      u16_t seglen = LWIP_MIN(space, len - pos);
- 800bb5c:	88fa      	ldrh	r2, [r7, #6]
- 800bb5e:	f8b7 304a 	ldrh.w	r3, [r7, #74]	; 0x4a
- 800bb62:	1ad2      	subs	r2, r2, r3
- 800bb64:	f8b7 305c 	ldrh.w	r3, [r7, #92]	; 0x5c
- 800bb68:	4293      	cmp	r3, r2
- 800bb6a:	bfa8      	it	ge
- 800bb6c:	4613      	movge	r3, r2
- 800bb6e:	847b      	strh	r3, [r7, #34]	; 0x22
-      seg = last_unsent;
- 800bb70:	6c3b      	ldr	r3, [r7, #64]	; 0x40
- 800bb72:	657b      	str	r3, [r7, #84]	; 0x54
-
-      /* Create a pbuf with a copy or reference to seglen bytes. We
-       * can use PBUF_RAW here since the data appears in the middle of
-       * a segment. A header will never be prepended. */
-      if (apiflags & TCP_WRITE_FLAG_COPY) {
- 800bb74:	797b      	ldrb	r3, [r7, #5]
- 800bb76:	f003 0301 	and.w	r3, r3, #1
- 800bb7a:	2b00      	cmp	r3, #0
- 800bb7c:	d02b      	beq.n	800bbd6 <tcp_write+0x272>
-        /* Data is copied */
-        if ((concat_p = tcp_pbuf_prealloc(PBUF_RAW, seglen, space, &oversize, pcb, apiflags, 1)) == NULL) {
- 800bb7e:	f107 0016 	add.w	r0, r7, #22
- 800bb82:	f8b7 205c 	ldrh.w	r2, [r7, #92]	; 0x5c
- 800bb86:	8c79      	ldrh	r1, [r7, #34]	; 0x22
- 800bb88:	2301      	movs	r3, #1
- 800bb8a:	9302      	str	r3, [sp, #8]
- 800bb8c:	797b      	ldrb	r3, [r7, #5]
- 800bb8e:	9301      	str	r3, [sp, #4]
- 800bb90:	68fb      	ldr	r3, [r7, #12]
- 800bb92:	9300      	str	r3, [sp, #0]
- 800bb94:	4603      	mov	r3, r0
- 800bb96:	2000      	movs	r0, #0
- 800bb98:	f7ff fdf0 	bl	800b77c <tcp_pbuf_prealloc>
- 800bb9c:	63f8      	str	r0, [r7, #60]	; 0x3c
- 800bb9e:	6bfb      	ldr	r3, [r7, #60]	; 0x3c
- 800bba0:	2b00      	cmp	r3, #0
- 800bba2:	f000 825a 	beq.w	800c05a <tcp_write+0x6f6>
-                      ("tcp_write : could not allocate memory for pbuf copy size %"U16_F"\n",
-                       seglen));
-          goto memerr;
-        }
-#if TCP_OVERSIZE_DBGCHECK
-        oversize_add = oversize;
- 800bba6:	8afb      	ldrh	r3, [r7, #22]
- 800bba8:	f8a7 305a 	strh.w	r3, [r7, #90]	; 0x5a
-#endif /* TCP_OVERSIZE_DBGCHECK */
-        TCP_DATA_COPY2(concat_p->payload, (const u8_t *)arg + pos, seglen, &concat_chksum, &concat_chksum_swapped);
- 800bbac:	6bfb      	ldr	r3, [r7, #60]	; 0x3c
- 800bbae:	6858      	ldr	r0, [r3, #4]
- 800bbb0:	f8b7 304a 	ldrh.w	r3, [r7, #74]	; 0x4a
- 800bbb4:	68ba      	ldr	r2, [r7, #8]
- 800bbb6:	4413      	add	r3, r2
- 800bbb8:	8c7a      	ldrh	r2, [r7, #34]	; 0x22
- 800bbba:	4619      	mov	r1, r3
- 800bbbc:	f005 f9e5 	bl	8010f8a <memcpy>
-#if TCP_CHECKSUM_ON_COPY
-        concat_chksummed += seglen;
-#endif /* TCP_CHECKSUM_ON_COPY */
-        queuelen += pbuf_clen(concat_p);
- 800bbc0:	6bf8      	ldr	r0, [r7, #60]	; 0x3c
- 800bbc2:	f7fb fa8f 	bl	80070e4 <pbuf_clen>
- 800bbc6:	4603      	mov	r3, r0
- 800bbc8:	461a      	mov	r2, r3
- 800bbca:	f8b7 3048 	ldrh.w	r3, [r7, #72]	; 0x48
- 800bbce:	4413      	add	r3, r2
- 800bbd0:	f8a7 3048 	strh.w	r3, [r7, #72]	; 0x48
- 800bbd4:	e055      	b.n	800bc82 <tcp_write+0x31e>
-      } else {
-        /* Data is not copied */
-        /* If the last unsent pbuf is of type PBUF_ROM, try to extend it. */
-        struct pbuf *p;
-        for (p = last_unsent->p; p->next != NULL; p = p->next);
- 800bbd6:	6c3b      	ldr	r3, [r7, #64]	; 0x40
- 800bbd8:	685b      	ldr	r3, [r3, #4]
- 800bbda:	63bb      	str	r3, [r7, #56]	; 0x38
- 800bbdc:	e002      	b.n	800bbe4 <tcp_write+0x280>
- 800bbde:	6bbb      	ldr	r3, [r7, #56]	; 0x38
- 800bbe0:	681b      	ldr	r3, [r3, #0]
- 800bbe2:	63bb      	str	r3, [r7, #56]	; 0x38
- 800bbe4:	6bbb      	ldr	r3, [r7, #56]	; 0x38
- 800bbe6:	681b      	ldr	r3, [r3, #0]
- 800bbe8:	2b00      	cmp	r3, #0
- 800bbea:	d1f8      	bne.n	800bbde <tcp_write+0x27a>
-        if (((p->type_internal & (PBUF_TYPE_FLAG_STRUCT_DATA_CONTIGUOUS | PBUF_TYPE_FLAG_DATA_VOLATILE)) == 0) &&
- 800bbec:	6bbb      	ldr	r3, [r7, #56]	; 0x38
- 800bbee:	7b1b      	ldrb	r3, [r3, #12]
- 800bbf0:	f003 03c0 	and.w	r3, r3, #192	; 0xc0
- 800bbf4:	2b00      	cmp	r3, #0
- 800bbf6:	d129      	bne.n	800bc4c <tcp_write+0x2e8>
-            (const u8_t *)p->payload + p->len == (const u8_t *)arg) {
- 800bbf8:	6bbb      	ldr	r3, [r7, #56]	; 0x38
- 800bbfa:	685b      	ldr	r3, [r3, #4]
- 800bbfc:	6bba      	ldr	r2, [r7, #56]	; 0x38
- 800bbfe:	8952      	ldrh	r2, [r2, #10]
- 800bc00:	4413      	add	r3, r2
-        if (((p->type_internal & (PBUF_TYPE_FLAG_STRUCT_DATA_CONTIGUOUS | PBUF_TYPE_FLAG_DATA_VOLATILE)) == 0) &&
- 800bc02:	68ba      	ldr	r2, [r7, #8]
- 800bc04:	429a      	cmp	r2, r3
- 800bc06:	d121      	bne.n	800bc4c <tcp_write+0x2e8>
-          LWIP_ASSERT("tcp_write: ROM pbufs cannot be oversized", pos == 0);
- 800bc08:	f8b7 304a 	ldrh.w	r3, [r7, #74]	; 0x4a
- 800bc0c:	2b00      	cmp	r3, #0
- 800bc0e:	d006      	beq.n	800bc1e <tcp_write+0x2ba>
- 800bc10:	4b05      	ldr	r3, [pc, #20]	; (800bc28 <tcp_write+0x2c4>)
- 800bc12:	f240 2231 	movw	r2, #561	; 0x231
- 800bc16:	490c      	ldr	r1, [pc, #48]	; (800bc48 <tcp_write+0x2e4>)
- 800bc18:	4805      	ldr	r0, [pc, #20]	; (800bc30 <tcp_write+0x2cc>)
- 800bc1a:	f004 ffd5 	bl	8010bc8 <iprintf>
-          extendlen = seglen;
- 800bc1e:	8c7b      	ldrh	r3, [r7, #34]	; 0x22
- 800bc20:	f8a7 305e 	strh.w	r3, [r7, #94]	; 0x5e
- 800bc24:	e02d      	b.n	800bc82 <tcp_write+0x31e>
- 800bc26:	bf00      	nop
- 800bc28:	08013618 	.word	0x08013618
- 800bc2c:	080137b8 	.word	0x080137b8
- 800bc30:	0801366c 	.word	0x0801366c
- 800bc34:	080137d0 	.word	0x080137d0
- 800bc38:	08013804 	.word	0x08013804
- 800bc3c:	0801381c 	.word	0x0801381c
- 800bc40:	0801384c 	.word	0x0801384c
- 800bc44:	0801386c 	.word	0x0801386c
- 800bc48:	0801388c 	.word	0x0801388c
-        } else {
-          if ((concat_p = pbuf_alloc(PBUF_RAW, seglen, PBUF_ROM)) == NULL) {
- 800bc4c:	8c7b      	ldrh	r3, [r7, #34]	; 0x22
- 800bc4e:	2201      	movs	r2, #1
- 800bc50:	4619      	mov	r1, r3
- 800bc52:	2000      	movs	r0, #0
- 800bc54:	f7fa feda 	bl	8006a0c <pbuf_alloc>
- 800bc58:	63f8      	str	r0, [r7, #60]	; 0x3c
- 800bc5a:	6bfb      	ldr	r3, [r7, #60]	; 0x3c
- 800bc5c:	2b00      	cmp	r3, #0
- 800bc5e:	f000 81fe 	beq.w	800c05e <tcp_write+0x6fa>
-            LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_LEVEL_SERIOUS,
-                        ("tcp_write: could not allocate memory for zero-copy pbuf\n"));
-            goto memerr;
-          }
-          /* reference the non-volatile payload data */
-          ((struct pbuf_rom *)concat_p)->payload = (const u8_t *)arg + pos;
- 800bc62:	f8b7 304a 	ldrh.w	r3, [r7, #74]	; 0x4a
- 800bc66:	68ba      	ldr	r2, [r7, #8]
- 800bc68:	441a      	add	r2, r3
- 800bc6a:	6bfb      	ldr	r3, [r7, #60]	; 0x3c
- 800bc6c:	605a      	str	r2, [r3, #4]
-          queuelen += pbuf_clen(concat_p);
- 800bc6e:	6bf8      	ldr	r0, [r7, #60]	; 0x3c
- 800bc70:	f7fb fa38 	bl	80070e4 <pbuf_clen>
- 800bc74:	4603      	mov	r3, r0
- 800bc76:	461a      	mov	r2, r3
- 800bc78:	f8b7 3048 	ldrh.w	r3, [r7, #72]	; 0x48
- 800bc7c:	4413      	add	r3, r2
- 800bc7e:	f8a7 3048 	strh.w	r3, [r7, #72]	; 0x48
-                           &concat_chksum, &concat_chksum_swapped);
-        concat_chksummed += seglen;
-#endif /* TCP_CHECKSUM_ON_COPY */
-      }
-
-      pos += seglen;
- 800bc82:	f8b7 204a 	ldrh.w	r2, [r7, #74]	; 0x4a
- 800bc86:	8c7b      	ldrh	r3, [r7, #34]	; 0x22
- 800bc88:	4413      	add	r3, r2
- 800bc8a:	f8a7 304a 	strh.w	r3, [r7, #74]	; 0x4a
- 800bc8e:	e0cd      	b.n	800be2c <tcp_write+0x4c8>
-    }
-#endif /* !LWIP_NETIF_TX_SINGLE_PBUF */
-  } else {
-#if TCP_OVERSIZE
-    LWIP_ASSERT("unsent_oversize mismatch (pcb->unsent is NULL)",
- 800bc90:	68fb      	ldr	r3, [r7, #12]
- 800bc92:	f8b3 3068 	ldrh.w	r3, [r3, #104]	; 0x68
- 800bc96:	2b00      	cmp	r3, #0
- 800bc98:	f000 80c8 	beq.w	800be2c <tcp_write+0x4c8>
- 800bc9c:	4b72      	ldr	r3, [pc, #456]	; (800be68 <tcp_write+0x504>)
- 800bc9e:	f240 224a 	movw	r2, #586	; 0x24a
- 800bca2:	4972      	ldr	r1, [pc, #456]	; (800be6c <tcp_write+0x508>)
- 800bca4:	4872      	ldr	r0, [pc, #456]	; (800be70 <tcp_write+0x50c>)
- 800bca6:	f004 ff8f 	bl	8010bc8 <iprintf>
-   * Phase 3: Create new segments.
-   *
-   * The new segments are chained together in the local 'queue'
-   * variable, ready to be appended to pcb->unsent.
-   */
-  while (pos < len) {
- 800bcaa:	e0bf      	b.n	800be2c <tcp_write+0x4c8>
-    struct pbuf *p;
-    u16_t left = len - pos;
- 800bcac:	88fa      	ldrh	r2, [r7, #6]
- 800bcae:	f8b7 304a 	ldrh.w	r3, [r7, #74]	; 0x4a
- 800bcb2:	1ad3      	subs	r3, r2, r3
- 800bcb4:	843b      	strh	r3, [r7, #32]
-    u16_t max_len = mss_local - optlen;
- 800bcb6:	f897 3026 	ldrb.w	r3, [r7, #38]	; 0x26
- 800bcba:	b29b      	uxth	r3, r3
- 800bcbc:	8d3a      	ldrh	r2, [r7, #40]	; 0x28
- 800bcbe:	1ad3      	subs	r3, r2, r3
- 800bcc0:	83fb      	strh	r3, [r7, #30]
-    u16_t seglen = LWIP_MIN(left, max_len);
- 800bcc2:	8bfa      	ldrh	r2, [r7, #30]
- 800bcc4:	8c3b      	ldrh	r3, [r7, #32]
- 800bcc6:	4293      	cmp	r3, r2
- 800bcc8:	bf28      	it	cs
- 800bcca:	4613      	movcs	r3, r2
- 800bccc:	83bb      	strh	r3, [r7, #28]
-#if TCP_CHECKSUM_ON_COPY
-    u16_t chksum = 0;
-    u8_t chksum_swapped = 0;
-#endif /* TCP_CHECKSUM_ON_COPY */
-
-    if (apiflags & TCP_WRITE_FLAG_COPY) {
- 800bcce:	797b      	ldrb	r3, [r7, #5]
- 800bcd0:	f003 0301 	and.w	r3, r3, #1
- 800bcd4:	2b00      	cmp	r3, #0
- 800bcd6:	d036      	beq.n	800bd46 <tcp_write+0x3e2>
-      /* If copy is set, memory should be allocated and data copied
-       * into pbuf */
-      if ((p = tcp_pbuf_prealloc(PBUF_TRANSPORT, seglen + optlen, mss_local, &oversize, pcb, apiflags, queue == NULL)) == NULL) {
- 800bcd8:	f897 3026 	ldrb.w	r3, [r7, #38]	; 0x26
- 800bcdc:	b29a      	uxth	r2, r3
- 800bcde:	8bbb      	ldrh	r3, [r7, #28]
- 800bce0:	4413      	add	r3, r2
- 800bce2:	b299      	uxth	r1, r3
- 800bce4:	6cfb      	ldr	r3, [r7, #76]	; 0x4c
- 800bce6:	2b00      	cmp	r3, #0
- 800bce8:	bf0c      	ite	eq
- 800bcea:	2301      	moveq	r3, #1
- 800bcec:	2300      	movne	r3, #0
- 800bcee:	b2db      	uxtb	r3, r3
- 800bcf0:	f107 0016 	add.w	r0, r7, #22
- 800bcf4:	8d3a      	ldrh	r2, [r7, #40]	; 0x28
- 800bcf6:	9302      	str	r3, [sp, #8]
- 800bcf8:	797b      	ldrb	r3, [r7, #5]
- 800bcfa:	9301      	str	r3, [sp, #4]
- 800bcfc:	68fb      	ldr	r3, [r7, #12]
- 800bcfe:	9300      	str	r3, [sp, #0]
- 800bd00:	4603      	mov	r3, r0
- 800bd02:	2036      	movs	r0, #54	; 0x36
- 800bd04:	f7ff fd3a 	bl	800b77c <tcp_pbuf_prealloc>
- 800bd08:	6378      	str	r0, [r7, #52]	; 0x34
- 800bd0a:	6b7b      	ldr	r3, [r7, #52]	; 0x34
- 800bd0c:	2b00      	cmp	r3, #0
- 800bd0e:	f000 81a8 	beq.w	800c062 <tcp_write+0x6fe>
-        LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("tcp_write : could not allocate memory for pbuf copy size %"U16_F"\n", seglen));
-        goto memerr;
-      }
-      LWIP_ASSERT("tcp_write: check that first pbuf can hold the complete seglen",
- 800bd12:	6b7b      	ldr	r3, [r7, #52]	; 0x34
- 800bd14:	895b      	ldrh	r3, [r3, #10]
- 800bd16:	8bba      	ldrh	r2, [r7, #28]
- 800bd18:	429a      	cmp	r2, r3
- 800bd1a:	d906      	bls.n	800bd2a <tcp_write+0x3c6>
- 800bd1c:	4b52      	ldr	r3, [pc, #328]	; (800be68 <tcp_write+0x504>)
- 800bd1e:	f240 2266 	movw	r2, #614	; 0x266
- 800bd22:	4954      	ldr	r1, [pc, #336]	; (800be74 <tcp_write+0x510>)
- 800bd24:	4852      	ldr	r0, [pc, #328]	; (800be70 <tcp_write+0x50c>)
- 800bd26:	f004 ff4f 	bl	8010bc8 <iprintf>
-                  (p->len >= seglen));
-      TCP_DATA_COPY2((char *)p->payload + optlen, (const u8_t *)arg + pos, seglen, &chksum, &chksum_swapped);
- 800bd2a:	6b7b      	ldr	r3, [r7, #52]	; 0x34
- 800bd2c:	685a      	ldr	r2, [r3, #4]
- 800bd2e:	f897 3026 	ldrb.w	r3, [r7, #38]	; 0x26
- 800bd32:	18d0      	adds	r0, r2, r3
- 800bd34:	f8b7 304a 	ldrh.w	r3, [r7, #74]	; 0x4a
- 800bd38:	68ba      	ldr	r2, [r7, #8]
- 800bd3a:	4413      	add	r3, r2
- 800bd3c:	8bba      	ldrh	r2, [r7, #28]
- 800bd3e:	4619      	mov	r1, r3
- 800bd40:	f005 f923 	bl	8010f8a <memcpy>
- 800bd44:	e02f      	b.n	800bda6 <tcp_write+0x442>
-       * sent out on the link (as it has to be ACKed by the remote
-       * party) we can safely use PBUF_ROM instead of PBUF_REF here.
-       */
-      struct pbuf *p2;
-#if TCP_OVERSIZE
-      LWIP_ASSERT("oversize == 0", oversize == 0);
- 800bd46:	8afb      	ldrh	r3, [r7, #22]
- 800bd48:	2b00      	cmp	r3, #0
- 800bd4a:	d006      	beq.n	800bd5a <tcp_write+0x3f6>
- 800bd4c:	4b46      	ldr	r3, [pc, #280]	; (800be68 <tcp_write+0x504>)
- 800bd4e:	f240 2271 	movw	r2, #625	; 0x271
- 800bd52:	4949      	ldr	r1, [pc, #292]	; (800be78 <tcp_write+0x514>)
- 800bd54:	4846      	ldr	r0, [pc, #280]	; (800be70 <tcp_write+0x50c>)
- 800bd56:	f004 ff37 	bl	8010bc8 <iprintf>
-#endif /* TCP_OVERSIZE */
-      if ((p2 = pbuf_alloc(PBUF_TRANSPORT, seglen, PBUF_ROM)) == NULL) {
- 800bd5a:	8bbb      	ldrh	r3, [r7, #28]
- 800bd5c:	2201      	movs	r2, #1
- 800bd5e:	4619      	mov	r1, r3
- 800bd60:	2036      	movs	r0, #54	; 0x36
- 800bd62:	f7fa fe53 	bl	8006a0c <pbuf_alloc>
- 800bd66:	61b8      	str	r0, [r7, #24]
- 800bd68:	69bb      	ldr	r3, [r7, #24]
- 800bd6a:	2b00      	cmp	r3, #0
- 800bd6c:	f000 817b 	beq.w	800c066 <tcp_write+0x702>
-        chksum_swapped = 1;
-        chksum = SWAP_BYTES_IN_WORD(chksum);
-      }
-#endif /* TCP_CHECKSUM_ON_COPY */
-      /* reference the non-volatile payload data */
-      ((struct pbuf_rom *)p2)->payload = (const u8_t *)arg + pos;
- 800bd70:	f8b7 304a 	ldrh.w	r3, [r7, #74]	; 0x4a
- 800bd74:	68ba      	ldr	r2, [r7, #8]
- 800bd76:	441a      	add	r2, r3
- 800bd78:	69bb      	ldr	r3, [r7, #24]
- 800bd7a:	605a      	str	r2, [r3, #4]
-
-      /* Second, allocate a pbuf for the headers. */
-      if ((p = pbuf_alloc(PBUF_TRANSPORT, optlen, PBUF_RAM)) == NULL) {
- 800bd7c:	f897 3026 	ldrb.w	r3, [r7, #38]	; 0x26
- 800bd80:	b29b      	uxth	r3, r3
- 800bd82:	f44f 7220 	mov.w	r2, #640	; 0x280
- 800bd86:	4619      	mov	r1, r3
- 800bd88:	2036      	movs	r0, #54	; 0x36
- 800bd8a:	f7fa fe3f 	bl	8006a0c <pbuf_alloc>
- 800bd8e:	6378      	str	r0, [r7, #52]	; 0x34
- 800bd90:	6b7b      	ldr	r3, [r7, #52]	; 0x34
- 800bd92:	2b00      	cmp	r3, #0
- 800bd94:	d103      	bne.n	800bd9e <tcp_write+0x43a>
-        /* If allocation fails, we have to deallocate the data pbuf as
-         * well. */
-        pbuf_free(p2);
- 800bd96:	69b8      	ldr	r0, [r7, #24]
- 800bd98:	f7fb f91c 	bl	8006fd4 <pbuf_free>
-        LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("tcp_write: could not allocate memory for header pbuf\n"));
-        goto memerr;
- 800bd9c:	e166      	b.n	800c06c <tcp_write+0x708>
-      }
-      /* Concatenate the headers and data pbufs together. */
-      pbuf_cat(p/*header*/, p2/*data*/);
- 800bd9e:	69b9      	ldr	r1, [r7, #24]
- 800bda0:	6b78      	ldr	r0, [r7, #52]	; 0x34
- 800bda2:	f7fb f9d9 	bl	8007158 <pbuf_cat>
-    }
-
-    queuelen += pbuf_clen(p);
- 800bda6:	6b78      	ldr	r0, [r7, #52]	; 0x34
- 800bda8:	f7fb f99c 	bl	80070e4 <pbuf_clen>
- 800bdac:	4603      	mov	r3, r0
- 800bdae:	461a      	mov	r2, r3
- 800bdb0:	f8b7 3048 	ldrh.w	r3, [r7, #72]	; 0x48
- 800bdb4:	4413      	add	r3, r2
- 800bdb6:	f8a7 3048 	strh.w	r3, [r7, #72]	; 0x48
-
-    /* Now that there are more segments queued, we check again if the
-     * length of the queue exceeds the configured maximum or
-     * overflows. */
-    if (queuelen > LWIP_MIN(TCP_SND_QUEUELEN, TCP_SNDQUEUELEN_OVERFLOW)) {
- 800bdba:	f8b7 3048 	ldrh.w	r3, [r7, #72]	; 0x48
- 800bdbe:	2b09      	cmp	r3, #9
- 800bdc0:	d903      	bls.n	800bdca <tcp_write+0x466>
-      LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("tcp_write: queue too long %"U16_F" (%d)\n",
-                  queuelen, (int)TCP_SND_QUEUELEN));
-      pbuf_free(p);
- 800bdc2:	6b78      	ldr	r0, [r7, #52]	; 0x34
- 800bdc4:	f7fb f906 	bl	8006fd4 <pbuf_free>
-      goto memerr;
- 800bdc8:	e150      	b.n	800c06c <tcp_write+0x708>
-    }
-
-    if ((seg = tcp_create_segment(pcb, p, 0, pcb->snd_lbb + pos, optflags)) == NULL) {
- 800bdca:	68fb      	ldr	r3, [r7, #12]
- 800bdcc:	6dda      	ldr	r2, [r3, #92]	; 0x5c
- 800bdce:	f8b7 304a 	ldrh.w	r3, [r7, #74]	; 0x4a
- 800bdd2:	441a      	add	r2, r3
- 800bdd4:	f897 302b 	ldrb.w	r3, [r7, #43]	; 0x2b
- 800bdd8:	9300      	str	r3, [sp, #0]
- 800bdda:	4613      	mov	r3, r2
- 800bddc:	2200      	movs	r2, #0
- 800bdde:	6b79      	ldr	r1, [r7, #52]	; 0x34
- 800bde0:	68f8      	ldr	r0, [r7, #12]
- 800bde2:	f7ff fc2b 	bl	800b63c <tcp_create_segment>
- 800bde6:	6578      	str	r0, [r7, #84]	; 0x54
- 800bde8:	6d7b      	ldr	r3, [r7, #84]	; 0x54
- 800bdea:	2b00      	cmp	r3, #0
- 800bdec:	f000 813d 	beq.w	800c06a <tcp_write+0x706>
-      goto memerr;
-    }
-#if TCP_OVERSIZE_DBGCHECK
-    seg->oversize_left = oversize;
- 800bdf0:	8afa      	ldrh	r2, [r7, #22]
- 800bdf2:	6d7b      	ldr	r3, [r7, #84]	; 0x54
- 800bdf4:	815a      	strh	r2, [r3, #10]
-    seg->chksum_swapped = chksum_swapped;
-    seg->flags |= TF_SEG_DATA_CHECKSUMMED;
-#endif /* TCP_CHECKSUM_ON_COPY */
-
-    /* first segment of to-be-queued data? */
-    if (queue == NULL) {
- 800bdf6:	6cfb      	ldr	r3, [r7, #76]	; 0x4c
- 800bdf8:	2b00      	cmp	r3, #0
- 800bdfa:	d102      	bne.n	800be02 <tcp_write+0x49e>
-      queue = seg;
- 800bdfc:	6d7b      	ldr	r3, [r7, #84]	; 0x54
- 800bdfe:	64fb      	str	r3, [r7, #76]	; 0x4c
- 800be00:	e00c      	b.n	800be1c <tcp_write+0x4b8>
-    } else {
-      /* Attach the segment to the end of the queued segments */
-      LWIP_ASSERT("prev_seg != NULL", prev_seg != NULL);
- 800be02:	6d3b      	ldr	r3, [r7, #80]	; 0x50
- 800be04:	2b00      	cmp	r3, #0
- 800be06:	d106      	bne.n	800be16 <tcp_write+0x4b2>
- 800be08:	4b17      	ldr	r3, [pc, #92]	; (800be68 <tcp_write+0x504>)
- 800be0a:	f240 22ab 	movw	r2, #683	; 0x2ab
- 800be0e:	491b      	ldr	r1, [pc, #108]	; (800be7c <tcp_write+0x518>)
- 800be10:	4817      	ldr	r0, [pc, #92]	; (800be70 <tcp_write+0x50c>)
- 800be12:	f004 fed9 	bl	8010bc8 <iprintf>
-      prev_seg->next = seg;
- 800be16:	6d3b      	ldr	r3, [r7, #80]	; 0x50
- 800be18:	6d7a      	ldr	r2, [r7, #84]	; 0x54
- 800be1a:	601a      	str	r2, [r3, #0]
-    }
-    /* remember last segment of to-be-queued data for next iteration */
-    prev_seg = seg;
- 800be1c:	6d7b      	ldr	r3, [r7, #84]	; 0x54
- 800be1e:	653b      	str	r3, [r7, #80]	; 0x50
-
-    LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_TRACE, ("tcp_write: queueing %"U32_F":%"U32_F"\n",
-                lwip_ntohl(seg->tcphdr->seqno),
-                lwip_ntohl(seg->tcphdr->seqno) + TCP_TCPLEN(seg)));
-
-    pos += seglen;
- 800be20:	f8b7 204a 	ldrh.w	r2, [r7, #74]	; 0x4a
- 800be24:	8bbb      	ldrh	r3, [r7, #28]
- 800be26:	4413      	add	r3, r2
- 800be28:	f8a7 304a 	strh.w	r3, [r7, #74]	; 0x4a
-  while (pos < len) {
- 800be2c:	f8b7 204a 	ldrh.w	r2, [r7, #74]	; 0x4a
- 800be30:	88fb      	ldrh	r3, [r7, #6]
- 800be32:	429a      	cmp	r2, r3
- 800be34:	f4ff af3a 	bcc.w	800bcac <tcp_write+0x348>
-  /*
-   * All three segmentation phases were successful. We can commit the
-   * transaction.
-   */
-#if TCP_OVERSIZE_DBGCHECK
-  if ((last_unsent != NULL) && (oversize_add != 0)) {
- 800be38:	6c3b      	ldr	r3, [r7, #64]	; 0x40
- 800be3a:	2b00      	cmp	r3, #0
- 800be3c:	d00b      	beq.n	800be56 <tcp_write+0x4f2>
- 800be3e:	f8b7 305a 	ldrh.w	r3, [r7, #90]	; 0x5a
- 800be42:	2b00      	cmp	r3, #0
- 800be44:	d007      	beq.n	800be56 <tcp_write+0x4f2>
-    last_unsent->oversize_left += oversize_add;
- 800be46:	6c3b      	ldr	r3, [r7, #64]	; 0x40
- 800be48:	895a      	ldrh	r2, [r3, #10]
- 800be4a:	f8b7 305a 	ldrh.w	r3, [r7, #90]	; 0x5a
- 800be4e:	4413      	add	r3, r2
- 800be50:	b29a      	uxth	r2, r3
- 800be52:	6c3b      	ldr	r3, [r7, #64]	; 0x40
- 800be54:	815a      	strh	r2, [r3, #10]
-  /*
-   * Phase 1: If data has been added to the preallocated tail of
-   * last_unsent, we update the length fields of the pbuf chain.
-   */
-#if TCP_OVERSIZE
-  if (oversize_used > 0) {
- 800be56:	f8b7 3046 	ldrh.w	r3, [r7, #70]	; 0x46
- 800be5a:	2b00      	cmp	r3, #0
- 800be5c:	d052      	beq.n	800bf04 <tcp_write+0x5a0>
-    struct pbuf *p;
-    /* Bump tot_len of whole chain, len of tail */
-    for (p = last_unsent->p; p; p = p->next) {
- 800be5e:	6c3b      	ldr	r3, [r7, #64]	; 0x40
- 800be60:	685b      	ldr	r3, [r3, #4]
- 800be62:	633b      	str	r3, [r7, #48]	; 0x30
- 800be64:	e02e      	b.n	800bec4 <tcp_write+0x560>
- 800be66:	bf00      	nop
- 800be68:	08013618 	.word	0x08013618
- 800be6c:	080138b8 	.word	0x080138b8
- 800be70:	0801366c 	.word	0x0801366c
- 800be74:	080138e8 	.word	0x080138e8
- 800be78:	08013928 	.word	0x08013928
- 800be7c:	08013938 	.word	0x08013938
-      p->tot_len += oversize_used;
- 800be80:	6b3b      	ldr	r3, [r7, #48]	; 0x30
- 800be82:	891a      	ldrh	r2, [r3, #8]
- 800be84:	f8b7 3046 	ldrh.w	r3, [r7, #70]	; 0x46
- 800be88:	4413      	add	r3, r2
- 800be8a:	b29a      	uxth	r2, r3
- 800be8c:	6b3b      	ldr	r3, [r7, #48]	; 0x30
- 800be8e:	811a      	strh	r2, [r3, #8]
-      if (p->next == NULL) {
- 800be90:	6b3b      	ldr	r3, [r7, #48]	; 0x30
- 800be92:	681b      	ldr	r3, [r3, #0]
- 800be94:	2b00      	cmp	r3, #0
- 800be96:	d112      	bne.n	800bebe <tcp_write+0x55a>
-        TCP_DATA_COPY((char *)p->payload + p->len, arg, oversize_used, last_unsent);
- 800be98:	6b3b      	ldr	r3, [r7, #48]	; 0x30
- 800be9a:	685b      	ldr	r3, [r3, #4]
- 800be9c:	6b3a      	ldr	r2, [r7, #48]	; 0x30
- 800be9e:	8952      	ldrh	r2, [r2, #10]
- 800bea0:	4413      	add	r3, r2
- 800bea2:	f8b7 2046 	ldrh.w	r2, [r7, #70]	; 0x46
- 800bea6:	68b9      	ldr	r1, [r7, #8]
- 800bea8:	4618      	mov	r0, r3
- 800beaa:	f005 f86e 	bl	8010f8a <memcpy>
-        p->len += oversize_used;
- 800beae:	6b3b      	ldr	r3, [r7, #48]	; 0x30
- 800beb0:	895a      	ldrh	r2, [r3, #10]
- 800beb2:	f8b7 3046 	ldrh.w	r3, [r7, #70]	; 0x46
- 800beb6:	4413      	add	r3, r2
- 800beb8:	b29a      	uxth	r2, r3
- 800beba:	6b3b      	ldr	r3, [r7, #48]	; 0x30
- 800bebc:	815a      	strh	r2, [r3, #10]
-    for (p = last_unsent->p; p; p = p->next) {
- 800bebe:	6b3b      	ldr	r3, [r7, #48]	; 0x30
- 800bec0:	681b      	ldr	r3, [r3, #0]
- 800bec2:	633b      	str	r3, [r7, #48]	; 0x30
- 800bec4:	6b3b      	ldr	r3, [r7, #48]	; 0x30
- 800bec6:	2b00      	cmp	r3, #0
- 800bec8:	d1da      	bne.n	800be80 <tcp_write+0x51c>
-      }
-    }
-    last_unsent->len += oversize_used;
- 800beca:	6c3b      	ldr	r3, [r7, #64]	; 0x40
- 800becc:	891a      	ldrh	r2, [r3, #8]
- 800bece:	f8b7 3046 	ldrh.w	r3, [r7, #70]	; 0x46
- 800bed2:	4413      	add	r3, r2
- 800bed4:	b29a      	uxth	r2, r3
- 800bed6:	6c3b      	ldr	r3, [r7, #64]	; 0x40
- 800bed8:	811a      	strh	r2, [r3, #8]
-#if TCP_OVERSIZE_DBGCHECK
-    LWIP_ASSERT("last_unsent->oversize_left >= oversize_used",
- 800beda:	6c3b      	ldr	r3, [r7, #64]	; 0x40
- 800bedc:	895b      	ldrh	r3, [r3, #10]
- 800bede:	f8b7 2046 	ldrh.w	r2, [r7, #70]	; 0x46
- 800bee2:	429a      	cmp	r2, r3
- 800bee4:	d906      	bls.n	800bef4 <tcp_write+0x590>
- 800bee6:	4b78      	ldr	r3, [pc, #480]	; (800c0c8 <tcp_write+0x764>)
- 800bee8:	f240 22d3 	movw	r2, #723	; 0x2d3
- 800beec:	4977      	ldr	r1, [pc, #476]	; (800c0cc <tcp_write+0x768>)
- 800beee:	4878      	ldr	r0, [pc, #480]	; (800c0d0 <tcp_write+0x76c>)
- 800bef0:	f004 fe6a 	bl	8010bc8 <iprintf>
-                last_unsent->oversize_left >= oversize_used);
-    last_unsent->oversize_left -= oversize_used;
- 800bef4:	6c3b      	ldr	r3, [r7, #64]	; 0x40
- 800bef6:	895a      	ldrh	r2, [r3, #10]
- 800bef8:	f8b7 3046 	ldrh.w	r3, [r7, #70]	; 0x46
- 800befc:	1ad3      	subs	r3, r2, r3
- 800befe:	b29a      	uxth	r2, r3
- 800bf00:	6c3b      	ldr	r3, [r7, #64]	; 0x40
- 800bf02:	815a      	strh	r2, [r3, #10]
-#endif /* TCP_OVERSIZE_DBGCHECK */
-  }
-  pcb->unsent_oversize = oversize;
- 800bf04:	8afa      	ldrh	r2, [r7, #22]
- 800bf06:	68fb      	ldr	r3, [r7, #12]
- 800bf08:	f8a3 2068 	strh.w	r2, [r3, #104]	; 0x68
-
-  /*
-   * Phase 2: concat_p can be concatenated onto last_unsent->p, unless we
-   * determined that the last ROM pbuf can be extended to include the new data.
-   */
-  if (concat_p != NULL) {
- 800bf0c:	6bfb      	ldr	r3, [r7, #60]	; 0x3c
- 800bf0e:	2b00      	cmp	r3, #0
- 800bf10:	d018      	beq.n	800bf44 <tcp_write+0x5e0>
-    LWIP_ASSERT("tcp_write: cannot concatenate when pcb->unsent is empty",
- 800bf12:	6c3b      	ldr	r3, [r7, #64]	; 0x40
- 800bf14:	2b00      	cmp	r3, #0
- 800bf16:	d106      	bne.n	800bf26 <tcp_write+0x5c2>
- 800bf18:	4b6b      	ldr	r3, [pc, #428]	; (800c0c8 <tcp_write+0x764>)
- 800bf1a:	f44f 7238 	mov.w	r2, #736	; 0x2e0
- 800bf1e:	496d      	ldr	r1, [pc, #436]	; (800c0d4 <tcp_write+0x770>)
- 800bf20:	486b      	ldr	r0, [pc, #428]	; (800c0d0 <tcp_write+0x76c>)
- 800bf22:	f004 fe51 	bl	8010bc8 <iprintf>
-                (last_unsent != NULL));
-    pbuf_cat(last_unsent->p, concat_p);
- 800bf26:	6c3b      	ldr	r3, [r7, #64]	; 0x40
- 800bf28:	685b      	ldr	r3, [r3, #4]
- 800bf2a:	6bf9      	ldr	r1, [r7, #60]	; 0x3c
- 800bf2c:	4618      	mov	r0, r3
- 800bf2e:	f7fb f913 	bl	8007158 <pbuf_cat>
-    last_unsent->len += concat_p->tot_len;
- 800bf32:	6c3b      	ldr	r3, [r7, #64]	; 0x40
- 800bf34:	891a      	ldrh	r2, [r3, #8]
- 800bf36:	6bfb      	ldr	r3, [r7, #60]	; 0x3c
- 800bf38:	891b      	ldrh	r3, [r3, #8]
- 800bf3a:	4413      	add	r3, r2
- 800bf3c:	b29a      	uxth	r2, r3
- 800bf3e:	6c3b      	ldr	r3, [r7, #64]	; 0x40
- 800bf40:	811a      	strh	r2, [r3, #8]
- 800bf42:	e03c      	b.n	800bfbe <tcp_write+0x65a>
-  } else if (extendlen > 0) {
- 800bf44:	f8b7 305e 	ldrh.w	r3, [r7, #94]	; 0x5e
- 800bf48:	2b00      	cmp	r3, #0
- 800bf4a:	d038      	beq.n	800bfbe <tcp_write+0x65a>
-    struct pbuf *p;
-    LWIP_ASSERT("tcp_write: extension of reference requires reference",
- 800bf4c:	6c3b      	ldr	r3, [r7, #64]	; 0x40
- 800bf4e:	2b00      	cmp	r3, #0
- 800bf50:	d003      	beq.n	800bf5a <tcp_write+0x5f6>
- 800bf52:	6c3b      	ldr	r3, [r7, #64]	; 0x40
- 800bf54:	685b      	ldr	r3, [r3, #4]
- 800bf56:	2b00      	cmp	r3, #0
- 800bf58:	d106      	bne.n	800bf68 <tcp_write+0x604>
- 800bf5a:	4b5b      	ldr	r3, [pc, #364]	; (800c0c8 <tcp_write+0x764>)
- 800bf5c:	f240 22e6 	movw	r2, #742	; 0x2e6
- 800bf60:	495d      	ldr	r1, [pc, #372]	; (800c0d8 <tcp_write+0x774>)
- 800bf62:	485b      	ldr	r0, [pc, #364]	; (800c0d0 <tcp_write+0x76c>)
- 800bf64:	f004 fe30 	bl	8010bc8 <iprintf>
-                last_unsent != NULL && last_unsent->p != NULL);
-    for (p = last_unsent->p; p->next != NULL; p = p->next) {
- 800bf68:	6c3b      	ldr	r3, [r7, #64]	; 0x40
- 800bf6a:	685b      	ldr	r3, [r3, #4]
- 800bf6c:	62fb      	str	r3, [r7, #44]	; 0x2c
- 800bf6e:	e00a      	b.n	800bf86 <tcp_write+0x622>
-      p->tot_len += extendlen;
- 800bf70:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 800bf72:	891a      	ldrh	r2, [r3, #8]
- 800bf74:	f8b7 305e 	ldrh.w	r3, [r7, #94]	; 0x5e
- 800bf78:	4413      	add	r3, r2
- 800bf7a:	b29a      	uxth	r2, r3
- 800bf7c:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 800bf7e:	811a      	strh	r2, [r3, #8]
-    for (p = last_unsent->p; p->next != NULL; p = p->next) {
- 800bf80:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 800bf82:	681b      	ldr	r3, [r3, #0]
- 800bf84:	62fb      	str	r3, [r7, #44]	; 0x2c
- 800bf86:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 800bf88:	681b      	ldr	r3, [r3, #0]
- 800bf8a:	2b00      	cmp	r3, #0
- 800bf8c:	d1f0      	bne.n	800bf70 <tcp_write+0x60c>
-    }
-    p->tot_len += extendlen;
- 800bf8e:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 800bf90:	891a      	ldrh	r2, [r3, #8]
- 800bf92:	f8b7 305e 	ldrh.w	r3, [r7, #94]	; 0x5e
- 800bf96:	4413      	add	r3, r2
- 800bf98:	b29a      	uxth	r2, r3
- 800bf9a:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 800bf9c:	811a      	strh	r2, [r3, #8]
-    p->len += extendlen;
- 800bf9e:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 800bfa0:	895a      	ldrh	r2, [r3, #10]
- 800bfa2:	f8b7 305e 	ldrh.w	r3, [r7, #94]	; 0x5e
- 800bfa6:	4413      	add	r3, r2
- 800bfa8:	b29a      	uxth	r2, r3
- 800bfaa:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 800bfac:	815a      	strh	r2, [r3, #10]
-    last_unsent->len += extendlen;
- 800bfae:	6c3b      	ldr	r3, [r7, #64]	; 0x40
- 800bfb0:	891a      	ldrh	r2, [r3, #8]
- 800bfb2:	f8b7 305e 	ldrh.w	r3, [r7, #94]	; 0x5e
- 800bfb6:	4413      	add	r3, r2
- 800bfb8:	b29a      	uxth	r2, r3
- 800bfba:	6c3b      	ldr	r3, [r7, #64]	; 0x40
- 800bfbc:	811a      	strh	r2, [r3, #8]
-
-  /*
-   * Phase 3: Append queue to pcb->unsent. Queue may be NULL, but that
-   * is harmless
-   */
-  if (last_unsent == NULL) {
- 800bfbe:	6c3b      	ldr	r3, [r7, #64]	; 0x40
- 800bfc0:	2b00      	cmp	r3, #0
- 800bfc2:	d103      	bne.n	800bfcc <tcp_write+0x668>
-    pcb->unsent = queue;
- 800bfc4:	68fb      	ldr	r3, [r7, #12]
- 800bfc6:	6cfa      	ldr	r2, [r7, #76]	; 0x4c
- 800bfc8:	66da      	str	r2, [r3, #108]	; 0x6c
- 800bfca:	e002      	b.n	800bfd2 <tcp_write+0x66e>
-  } else {
-    last_unsent->next = queue;
- 800bfcc:	6c3b      	ldr	r3, [r7, #64]	; 0x40
- 800bfce:	6cfa      	ldr	r2, [r7, #76]	; 0x4c
- 800bfd0:	601a      	str	r2, [r3, #0]
-  }
-
-  /*
-   * Finally update the pcb state.
-   */
-  pcb->snd_lbb += len;
- 800bfd2:	68fb      	ldr	r3, [r7, #12]
- 800bfd4:	6dda      	ldr	r2, [r3, #92]	; 0x5c
- 800bfd6:	88fb      	ldrh	r3, [r7, #6]
- 800bfd8:	441a      	add	r2, r3
- 800bfda:	68fb      	ldr	r3, [r7, #12]
- 800bfdc:	65da      	str	r2, [r3, #92]	; 0x5c
-  pcb->snd_buf -= len;
- 800bfde:	68fb      	ldr	r3, [r7, #12]
- 800bfe0:	f8b3 2064 	ldrh.w	r2, [r3, #100]	; 0x64
- 800bfe4:	88fb      	ldrh	r3, [r7, #6]
- 800bfe6:	1ad3      	subs	r3, r2, r3
- 800bfe8:	b29a      	uxth	r2, r3
- 800bfea:	68fb      	ldr	r3, [r7, #12]
- 800bfec:	f8a3 2064 	strh.w	r2, [r3, #100]	; 0x64
-  pcb->snd_queuelen = queuelen;
- 800bff0:	68fb      	ldr	r3, [r7, #12]
- 800bff2:	f8b7 2048 	ldrh.w	r2, [r7, #72]	; 0x48
- 800bff6:	f8a3 2066 	strh.w	r2, [r3, #102]	; 0x66
-
-  LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_write: %"S16_F" (after enqueued)\n",
-                               pcb->snd_queuelen));
-  if (pcb->snd_queuelen != 0) {
- 800bffa:	68fb      	ldr	r3, [r7, #12]
- 800bffc:	f8b3 3066 	ldrh.w	r3, [r3, #102]	; 0x66
- 800c000:	2b00      	cmp	r3, #0
- 800c002:	d00e      	beq.n	800c022 <tcp_write+0x6be>
-    LWIP_ASSERT("tcp_write: valid queue length",
- 800c004:	68fb      	ldr	r3, [r7, #12]
- 800c006:	6f1b      	ldr	r3, [r3, #112]	; 0x70
- 800c008:	2b00      	cmp	r3, #0
- 800c00a:	d10a      	bne.n	800c022 <tcp_write+0x6be>
- 800c00c:	68fb      	ldr	r3, [r7, #12]
- 800c00e:	6edb      	ldr	r3, [r3, #108]	; 0x6c
- 800c010:	2b00      	cmp	r3, #0
- 800c012:	d106      	bne.n	800c022 <tcp_write+0x6be>
- 800c014:	4b2c      	ldr	r3, [pc, #176]	; (800c0c8 <tcp_write+0x764>)
- 800c016:	f240 3212 	movw	r2, #786	; 0x312
- 800c01a:	4930      	ldr	r1, [pc, #192]	; (800c0dc <tcp_write+0x778>)
- 800c01c:	482c      	ldr	r0, [pc, #176]	; (800c0d0 <tcp_write+0x76c>)
- 800c01e:	f004 fdd3 	bl	8010bc8 <iprintf>
-                pcb->unacked != NULL || pcb->unsent != NULL);
-  }
-
-  /* Set the PSH flag in the last segment that we enqueued. */
-  if (seg != NULL && seg->tcphdr != NULL && ((apiflags & TCP_WRITE_FLAG_MORE) == 0)) {
- 800c022:	6d7b      	ldr	r3, [r7, #84]	; 0x54
- 800c024:	2b00      	cmp	r3, #0
- 800c026:	d016      	beq.n	800c056 <tcp_write+0x6f2>
- 800c028:	6d7b      	ldr	r3, [r7, #84]	; 0x54
- 800c02a:	691b      	ldr	r3, [r3, #16]
- 800c02c:	2b00      	cmp	r3, #0
- 800c02e:	d012      	beq.n	800c056 <tcp_write+0x6f2>
- 800c030:	797b      	ldrb	r3, [r7, #5]
- 800c032:	f003 0302 	and.w	r3, r3, #2
- 800c036:	2b00      	cmp	r3, #0
- 800c038:	d10d      	bne.n	800c056 <tcp_write+0x6f2>
-    TCPH_SET_FLAG(seg->tcphdr, TCP_PSH);
- 800c03a:	6d7b      	ldr	r3, [r7, #84]	; 0x54
- 800c03c:	691b      	ldr	r3, [r3, #16]
- 800c03e:	899b      	ldrh	r3, [r3, #12]
- 800c040:	b29c      	uxth	r4, r3
- 800c042:	2008      	movs	r0, #8
- 800c044:	f7f9 fa82 	bl	800554c <lwip_htons>
- 800c048:	4603      	mov	r3, r0
- 800c04a:	461a      	mov	r2, r3
- 800c04c:	6d7b      	ldr	r3, [r7, #84]	; 0x54
- 800c04e:	691b      	ldr	r3, [r3, #16]
- 800c050:	4322      	orrs	r2, r4
- 800c052:	b292      	uxth	r2, r2
- 800c054:	819a      	strh	r2, [r3, #12]
-  }
-
-  return ERR_OK;
- 800c056:	2300      	movs	r3, #0
- 800c058:	e031      	b.n	800c0be <tcp_write+0x75a>
-          goto memerr;
- 800c05a:	bf00      	nop
- 800c05c:	e006      	b.n	800c06c <tcp_write+0x708>
-            goto memerr;
- 800c05e:	bf00      	nop
- 800c060:	e004      	b.n	800c06c <tcp_write+0x708>
-        goto memerr;
- 800c062:	bf00      	nop
- 800c064:	e002      	b.n	800c06c <tcp_write+0x708>
-        goto memerr;
- 800c066:	bf00      	nop
- 800c068:	e000      	b.n	800c06c <tcp_write+0x708>
-      goto memerr;
- 800c06a:	bf00      	nop
-memerr:
-  tcp_set_flags(pcb, TF_NAGLEMEMERR);
- 800c06c:	68fb      	ldr	r3, [r7, #12]
- 800c06e:	8b5b      	ldrh	r3, [r3, #26]
- 800c070:	f043 0380 	orr.w	r3, r3, #128	; 0x80
- 800c074:	b29a      	uxth	r2, r3
- 800c076:	68fb      	ldr	r3, [r7, #12]
- 800c078:	835a      	strh	r2, [r3, #26]
-  TCP_STATS_INC(tcp.memerr);
-
-  if (concat_p != NULL) {
- 800c07a:	6bfb      	ldr	r3, [r7, #60]	; 0x3c
- 800c07c:	2b00      	cmp	r3, #0
- 800c07e:	d002      	beq.n	800c086 <tcp_write+0x722>
-    pbuf_free(concat_p);
- 800c080:	6bf8      	ldr	r0, [r7, #60]	; 0x3c
- 800c082:	f7fa ffa7 	bl	8006fd4 <pbuf_free>
-  }
-  if (queue != NULL) {
- 800c086:	6cfb      	ldr	r3, [r7, #76]	; 0x4c
- 800c088:	2b00      	cmp	r3, #0
- 800c08a:	d002      	beq.n	800c092 <tcp_write+0x72e>
-    tcp_segs_free(queue);
- 800c08c:	6cf8      	ldr	r0, [r7, #76]	; 0x4c
- 800c08e:	f7fc fb5d 	bl	800874c <tcp_segs_free>
-  }
-  if (pcb->snd_queuelen != 0) {
- 800c092:	68fb      	ldr	r3, [r7, #12]
- 800c094:	f8b3 3066 	ldrh.w	r3, [r3, #102]	; 0x66
- 800c098:	2b00      	cmp	r3, #0
- 800c09a:	d00e      	beq.n	800c0ba <tcp_write+0x756>
-    LWIP_ASSERT("tcp_write: valid queue length", pcb->unacked != NULL ||
- 800c09c:	68fb      	ldr	r3, [r7, #12]
- 800c09e:	6f1b      	ldr	r3, [r3, #112]	; 0x70
- 800c0a0:	2b00      	cmp	r3, #0
- 800c0a2:	d10a      	bne.n	800c0ba <tcp_write+0x756>
- 800c0a4:	68fb      	ldr	r3, [r7, #12]
- 800c0a6:	6edb      	ldr	r3, [r3, #108]	; 0x6c
- 800c0a8:	2b00      	cmp	r3, #0
- 800c0aa:	d106      	bne.n	800c0ba <tcp_write+0x756>
- 800c0ac:	4b06      	ldr	r3, [pc, #24]	; (800c0c8 <tcp_write+0x764>)
- 800c0ae:	f240 3227 	movw	r2, #807	; 0x327
- 800c0b2:	490a      	ldr	r1, [pc, #40]	; (800c0dc <tcp_write+0x778>)
- 800c0b4:	4806      	ldr	r0, [pc, #24]	; (800c0d0 <tcp_write+0x76c>)
- 800c0b6:	f004 fd87 	bl	8010bc8 <iprintf>
-                pcb->unsent != NULL);
-  }
-  LWIP_DEBUGF(TCP_QLEN_DEBUG | LWIP_DBG_STATE, ("tcp_write: %"S16_F" (with mem err)\n", pcb->snd_queuelen));
-  return ERR_MEM;
- 800c0ba:	f04f 33ff 	mov.w	r3, #4294967295
-}
- 800c0be:	4618      	mov	r0, r3
- 800c0c0:	3764      	adds	r7, #100	; 0x64
- 800c0c2:	46bd      	mov	sp, r7
- 800c0c4:	bd90      	pop	{r4, r7, pc}
- 800c0c6:	bf00      	nop
- 800c0c8:	08013618 	.word	0x08013618
- 800c0cc:	0801394c 	.word	0x0801394c
- 800c0d0:	0801366c 	.word	0x0801366c
- 800c0d4:	08013978 	.word	0x08013978
- 800c0d8:	080139b0 	.word	0x080139b0
- 800c0dc:	080139e8 	.word	0x080139e8
-
-0800c0e0 <tcp_split_unsent_seg>:
- * @param pcb the tcp_pcb for which to split the unsent head
- * @param split the amount of payload to remain in the head
- */
-err_t
-tcp_split_unsent_seg(struct tcp_pcb *pcb, u16_t split)
-{
- 800c0e0:	b590      	push	{r4, r7, lr}
- 800c0e2:	b08b      	sub	sp, #44	; 0x2c
- 800c0e4:	af02      	add	r7, sp, #8
- 800c0e6:	6078      	str	r0, [r7, #4]
- 800c0e8:	460b      	mov	r3, r1
- 800c0ea:	807b      	strh	r3, [r7, #2]
-  struct tcp_seg *seg = NULL, *useg = NULL;
- 800c0ec:	2300      	movs	r3, #0
- 800c0ee:	61bb      	str	r3, [r7, #24]
- 800c0f0:	2300      	movs	r3, #0
- 800c0f2:	617b      	str	r3, [r7, #20]
-  struct pbuf *p = NULL;
- 800c0f4:	2300      	movs	r3, #0
- 800c0f6:	613b      	str	r3, [r7, #16]
-  u16_t chksum = 0;
-  u8_t chksum_swapped = 0;
-  struct pbuf *q;
-#endif /* TCP_CHECKSUM_ON_COPY */
-
-  LWIP_ASSERT("tcp_split_unsent_seg: invalid pcb", pcb != NULL);
- 800c0f8:	687b      	ldr	r3, [r7, #4]
- 800c0fa:	2b00      	cmp	r3, #0
- 800c0fc:	d106      	bne.n	800c10c <tcp_split_unsent_seg+0x2c>
- 800c0fe:	4b97      	ldr	r3, [pc, #604]	; (800c35c <tcp_split_unsent_seg+0x27c>)
- 800c100:	f240 324b 	movw	r2, #843	; 0x34b
- 800c104:	4996      	ldr	r1, [pc, #600]	; (800c360 <tcp_split_unsent_seg+0x280>)
- 800c106:	4897      	ldr	r0, [pc, #604]	; (800c364 <tcp_split_unsent_seg+0x284>)
- 800c108:	f004 fd5e 	bl	8010bc8 <iprintf>
-
-  useg = pcb->unsent;
- 800c10c:	687b      	ldr	r3, [r7, #4]
- 800c10e:	6edb      	ldr	r3, [r3, #108]	; 0x6c
- 800c110:	617b      	str	r3, [r7, #20]
-  if (useg == NULL) {
- 800c112:	697b      	ldr	r3, [r7, #20]
- 800c114:	2b00      	cmp	r3, #0
- 800c116:	d102      	bne.n	800c11e <tcp_split_unsent_seg+0x3e>
-    return ERR_MEM;
- 800c118:	f04f 33ff 	mov.w	r3, #4294967295
- 800c11c:	e119      	b.n	800c352 <tcp_split_unsent_seg+0x272>
-  }
-
-  if (split == 0) {
- 800c11e:	887b      	ldrh	r3, [r7, #2]
- 800c120:	2b00      	cmp	r3, #0
- 800c122:	d109      	bne.n	800c138 <tcp_split_unsent_seg+0x58>
-    LWIP_ASSERT("Can't split segment into length 0", 0);
- 800c124:	4b8d      	ldr	r3, [pc, #564]	; (800c35c <tcp_split_unsent_seg+0x27c>)
- 800c126:	f240 3253 	movw	r2, #851	; 0x353
- 800c12a:	498f      	ldr	r1, [pc, #572]	; (800c368 <tcp_split_unsent_seg+0x288>)
- 800c12c:	488d      	ldr	r0, [pc, #564]	; (800c364 <tcp_split_unsent_seg+0x284>)
- 800c12e:	f004 fd4b 	bl	8010bc8 <iprintf>
-    return ERR_VAL;
- 800c132:	f06f 0305 	mvn.w	r3, #5
- 800c136:	e10c      	b.n	800c352 <tcp_split_unsent_seg+0x272>
-  }
-
-  if (useg->len <= split) {
- 800c138:	697b      	ldr	r3, [r7, #20]
- 800c13a:	891b      	ldrh	r3, [r3, #8]
- 800c13c:	887a      	ldrh	r2, [r7, #2]
- 800c13e:	429a      	cmp	r2, r3
- 800c140:	d301      	bcc.n	800c146 <tcp_split_unsent_seg+0x66>
-    return ERR_OK;
- 800c142:	2300      	movs	r3, #0
- 800c144:	e105      	b.n	800c352 <tcp_split_unsent_seg+0x272>
-  }
-
-  LWIP_ASSERT("split <= mss", split <= pcb->mss);
- 800c146:	687b      	ldr	r3, [r7, #4]
- 800c148:	8e5b      	ldrh	r3, [r3, #50]	; 0x32
- 800c14a:	887a      	ldrh	r2, [r7, #2]
- 800c14c:	429a      	cmp	r2, r3
- 800c14e:	d906      	bls.n	800c15e <tcp_split_unsent_seg+0x7e>
- 800c150:	4b82      	ldr	r3, [pc, #520]	; (800c35c <tcp_split_unsent_seg+0x27c>)
- 800c152:	f240 325b 	movw	r2, #859	; 0x35b
- 800c156:	4985      	ldr	r1, [pc, #532]	; (800c36c <tcp_split_unsent_seg+0x28c>)
- 800c158:	4882      	ldr	r0, [pc, #520]	; (800c364 <tcp_split_unsent_seg+0x284>)
- 800c15a:	f004 fd35 	bl	8010bc8 <iprintf>
-  LWIP_ASSERT("useg->len > 0", useg->len > 0);
- 800c15e:	697b      	ldr	r3, [r7, #20]
- 800c160:	891b      	ldrh	r3, [r3, #8]
- 800c162:	2b00      	cmp	r3, #0
- 800c164:	d106      	bne.n	800c174 <tcp_split_unsent_seg+0x94>
- 800c166:	4b7d      	ldr	r3, [pc, #500]	; (800c35c <tcp_split_unsent_seg+0x27c>)
- 800c168:	f44f 7257 	mov.w	r2, #860	; 0x35c
- 800c16c:	4980      	ldr	r1, [pc, #512]	; (800c370 <tcp_split_unsent_seg+0x290>)
- 800c16e:	487d      	ldr	r0, [pc, #500]	; (800c364 <tcp_split_unsent_seg+0x284>)
- 800c170:	f004 fd2a 	bl	8010bc8 <iprintf>
-   * to split this packet so we may actually exceed the max value by
-   * one!
-   */
-  LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_enqueue: split_unsent_seg: %u\n", (unsigned int)pcb->snd_queuelen));
-
-  optflags = useg->flags;
- 800c174:	697b      	ldr	r3, [r7, #20]
- 800c176:	7b1b      	ldrb	r3, [r3, #12]
- 800c178:	73fb      	strb	r3, [r7, #15]
-#if TCP_CHECKSUM_ON_COPY
-  /* Remove since checksum is not stored until after tcp_create_segment() */
-  optflags &= ~TF_SEG_DATA_CHECKSUMMED;
-#endif /* TCP_CHECKSUM_ON_COPY */
-  optlen = LWIP_TCP_OPT_LENGTH(optflags);
- 800c17a:	7bfb      	ldrb	r3, [r7, #15]
- 800c17c:	009b      	lsls	r3, r3, #2
- 800c17e:	b2db      	uxtb	r3, r3
- 800c180:	f003 0304 	and.w	r3, r3, #4
- 800c184:	73bb      	strb	r3, [r7, #14]
-  remainder = useg->len - split;
- 800c186:	697b      	ldr	r3, [r7, #20]
- 800c188:	891a      	ldrh	r2, [r3, #8]
- 800c18a:	887b      	ldrh	r3, [r7, #2]
- 800c18c:	1ad3      	subs	r3, r2, r3
- 800c18e:	81bb      	strh	r3, [r7, #12]
-
-  /* Create new pbuf for the remainder of the split */
-  p = pbuf_alloc(PBUF_TRANSPORT, remainder + optlen, PBUF_RAM);
- 800c190:	7bbb      	ldrb	r3, [r7, #14]
- 800c192:	b29a      	uxth	r2, r3
- 800c194:	89bb      	ldrh	r3, [r7, #12]
- 800c196:	4413      	add	r3, r2
- 800c198:	b29b      	uxth	r3, r3
- 800c19a:	f44f 7220 	mov.w	r2, #640	; 0x280
- 800c19e:	4619      	mov	r1, r3
- 800c1a0:	2036      	movs	r0, #54	; 0x36
- 800c1a2:	f7fa fc33 	bl	8006a0c <pbuf_alloc>
- 800c1a6:	6138      	str	r0, [r7, #16]
-  if (p == NULL) {
- 800c1a8:	693b      	ldr	r3, [r7, #16]
- 800c1aa:	2b00      	cmp	r3, #0
- 800c1ac:	f000 80ba 	beq.w	800c324 <tcp_split_unsent_seg+0x244>
-                ("tcp_split_unsent_seg: could not allocate memory for pbuf remainder %u\n", remainder));
-    goto memerr;
-  }
-
-  /* Offset into the original pbuf is past TCP/IP headers, options, and split amount */
-  offset = useg->p->tot_len - useg->len + split;
- 800c1b0:	697b      	ldr	r3, [r7, #20]
- 800c1b2:	685b      	ldr	r3, [r3, #4]
- 800c1b4:	891a      	ldrh	r2, [r3, #8]
- 800c1b6:	697b      	ldr	r3, [r7, #20]
- 800c1b8:	891b      	ldrh	r3, [r3, #8]
- 800c1ba:	1ad3      	subs	r3, r2, r3
- 800c1bc:	b29a      	uxth	r2, r3
- 800c1be:	887b      	ldrh	r3, [r7, #2]
- 800c1c0:	4413      	add	r3, r2
- 800c1c2:	817b      	strh	r3, [r7, #10]
-  /* Copy remainder into new pbuf, headers and options will not be filled out */
-  if (pbuf_copy_partial(useg->p, (u8_t *)p->payload + optlen, remainder, offset ) != remainder) {
- 800c1c4:	697b      	ldr	r3, [r7, #20]
- 800c1c6:	6858      	ldr	r0, [r3, #4]
- 800c1c8:	693b      	ldr	r3, [r7, #16]
- 800c1ca:	685a      	ldr	r2, [r3, #4]
- 800c1cc:	7bbb      	ldrb	r3, [r7, #14]
- 800c1ce:	18d1      	adds	r1, r2, r3
- 800c1d0:	897b      	ldrh	r3, [r7, #10]
- 800c1d2:	89ba      	ldrh	r2, [r7, #12]
- 800c1d4:	f7fb f8e8 	bl	80073a8 <pbuf_copy_partial>
- 800c1d8:	4603      	mov	r3, r0
- 800c1da:	461a      	mov	r2, r3
- 800c1dc:	89bb      	ldrh	r3, [r7, #12]
- 800c1de:	4293      	cmp	r3, r2
- 800c1e0:	f040 80a2 	bne.w	800c328 <tcp_split_unsent_seg+0x248>
-#endif /* TCP_CHECKSUM_ON_COPY */
-
-  /* Options are created when calling tcp_output() */
-
-  /* Migrate flags from original segment */
-  split_flags = TCPH_FLAGS(useg->tcphdr);
- 800c1e4:	697b      	ldr	r3, [r7, #20]
- 800c1e6:	691b      	ldr	r3, [r3, #16]
- 800c1e8:	899b      	ldrh	r3, [r3, #12]
- 800c1ea:	b29b      	uxth	r3, r3
- 800c1ec:	4618      	mov	r0, r3
- 800c1ee:	f7f9 f9ad 	bl	800554c <lwip_htons>
- 800c1f2:	4603      	mov	r3, r0
- 800c1f4:	b2db      	uxtb	r3, r3
- 800c1f6:	f003 033f 	and.w	r3, r3, #63	; 0x3f
- 800c1fa:	77fb      	strb	r3, [r7, #31]
-  remainder_flags = 0; /* ACK added in tcp_output() */
- 800c1fc:	2300      	movs	r3, #0
- 800c1fe:	77bb      	strb	r3, [r7, #30]
-
-  if (split_flags & TCP_PSH) {
- 800c200:	7ffb      	ldrb	r3, [r7, #31]
- 800c202:	f003 0308 	and.w	r3, r3, #8
- 800c206:	2b00      	cmp	r3, #0
- 800c208:	d007      	beq.n	800c21a <tcp_split_unsent_seg+0x13a>
-    split_flags &= ~TCP_PSH;
- 800c20a:	7ffb      	ldrb	r3, [r7, #31]
- 800c20c:	f023 0308 	bic.w	r3, r3, #8
- 800c210:	77fb      	strb	r3, [r7, #31]
-    remainder_flags |= TCP_PSH;
- 800c212:	7fbb      	ldrb	r3, [r7, #30]
- 800c214:	f043 0308 	orr.w	r3, r3, #8
- 800c218:	77bb      	strb	r3, [r7, #30]
-  }
-  if (split_flags & TCP_FIN) {
- 800c21a:	7ffb      	ldrb	r3, [r7, #31]
- 800c21c:	f003 0301 	and.w	r3, r3, #1
- 800c220:	2b00      	cmp	r3, #0
- 800c222:	d007      	beq.n	800c234 <tcp_split_unsent_seg+0x154>
-    split_flags &= ~TCP_FIN;
- 800c224:	7ffb      	ldrb	r3, [r7, #31]
- 800c226:	f023 0301 	bic.w	r3, r3, #1
- 800c22a:	77fb      	strb	r3, [r7, #31]
-    remainder_flags |= TCP_FIN;
- 800c22c:	7fbb      	ldrb	r3, [r7, #30]
- 800c22e:	f043 0301 	orr.w	r3, r3, #1
- 800c232:	77bb      	strb	r3, [r7, #30]
-  }
-  /* SYN should be left on split, RST should not be present with data */
-
-  seg = tcp_create_segment(pcb, p, remainder_flags, lwip_ntohl(useg->tcphdr->seqno) + split, optflags);
- 800c234:	697b      	ldr	r3, [r7, #20]
- 800c236:	691b      	ldr	r3, [r3, #16]
- 800c238:	685b      	ldr	r3, [r3, #4]
- 800c23a:	4618      	mov	r0, r3
- 800c23c:	f7f9 f99b 	bl	8005576 <lwip_htonl>
- 800c240:	4602      	mov	r2, r0
- 800c242:	887b      	ldrh	r3, [r7, #2]
- 800c244:	18d1      	adds	r1, r2, r3
- 800c246:	7fba      	ldrb	r2, [r7, #30]
- 800c248:	7bfb      	ldrb	r3, [r7, #15]
- 800c24a:	9300      	str	r3, [sp, #0]
- 800c24c:	460b      	mov	r3, r1
- 800c24e:	6939      	ldr	r1, [r7, #16]
- 800c250:	6878      	ldr	r0, [r7, #4]
- 800c252:	f7ff f9f3 	bl	800b63c <tcp_create_segment>
- 800c256:	61b8      	str	r0, [r7, #24]
-  if (seg == NULL) {
- 800c258:	69bb      	ldr	r3, [r7, #24]
- 800c25a:	2b00      	cmp	r3, #0
- 800c25c:	d066      	beq.n	800c32c <tcp_split_unsent_seg+0x24c>
-  seg->chksum_swapped = chksum_swapped;
-  seg->flags |= TF_SEG_DATA_CHECKSUMMED;
-#endif /* TCP_CHECKSUM_ON_COPY */
-
-  /* Remove this segment from the queue since trimming it may free pbufs */
-  pcb->snd_queuelen -= pbuf_clen(useg->p);
- 800c25e:	697b      	ldr	r3, [r7, #20]
- 800c260:	685b      	ldr	r3, [r3, #4]
- 800c262:	4618      	mov	r0, r3
- 800c264:	f7fa ff3e 	bl	80070e4 <pbuf_clen>
- 800c268:	4603      	mov	r3, r0
- 800c26a:	461a      	mov	r2, r3
- 800c26c:	687b      	ldr	r3, [r7, #4]
- 800c26e:	f8b3 3066 	ldrh.w	r3, [r3, #102]	; 0x66
- 800c272:	1a9b      	subs	r3, r3, r2
- 800c274:	b29a      	uxth	r2, r3
- 800c276:	687b      	ldr	r3, [r7, #4]
- 800c278:	f8a3 2066 	strh.w	r2, [r3, #102]	; 0x66
-
-  /* Trim the original pbuf into our split size.  At this point our remainder segment must be setup
-  successfully because we are modifying the original segment */
-  pbuf_realloc(useg->p, useg->p->tot_len - remainder);
- 800c27c:	697b      	ldr	r3, [r7, #20]
- 800c27e:	6858      	ldr	r0, [r3, #4]
- 800c280:	697b      	ldr	r3, [r7, #20]
- 800c282:	685b      	ldr	r3, [r3, #4]
- 800c284:	891a      	ldrh	r2, [r3, #8]
- 800c286:	89bb      	ldrh	r3, [r7, #12]
- 800c288:	1ad3      	subs	r3, r2, r3
- 800c28a:	b29b      	uxth	r3, r3
- 800c28c:	4619      	mov	r1, r3
- 800c28e:	f7fa fd1b 	bl	8006cc8 <pbuf_realloc>
-  useg->len -= remainder;
- 800c292:	697b      	ldr	r3, [r7, #20]
- 800c294:	891a      	ldrh	r2, [r3, #8]
- 800c296:	89bb      	ldrh	r3, [r7, #12]
- 800c298:	1ad3      	subs	r3, r2, r3
- 800c29a:	b29a      	uxth	r2, r3
- 800c29c:	697b      	ldr	r3, [r7, #20]
- 800c29e:	811a      	strh	r2, [r3, #8]
-  TCPH_SET_FLAG(useg->tcphdr, split_flags);
- 800c2a0:	697b      	ldr	r3, [r7, #20]
- 800c2a2:	691b      	ldr	r3, [r3, #16]
- 800c2a4:	899b      	ldrh	r3, [r3, #12]
- 800c2a6:	b29c      	uxth	r4, r3
- 800c2a8:	7ffb      	ldrb	r3, [r7, #31]
- 800c2aa:	b29b      	uxth	r3, r3
- 800c2ac:	4618      	mov	r0, r3
- 800c2ae:	f7f9 f94d 	bl	800554c <lwip_htons>
- 800c2b2:	4603      	mov	r3, r0
- 800c2b4:	461a      	mov	r2, r3
- 800c2b6:	697b      	ldr	r3, [r7, #20]
- 800c2b8:	691b      	ldr	r3, [r3, #16]
- 800c2ba:	4322      	orrs	r2, r4
- 800c2bc:	b292      	uxth	r2, r2
- 800c2be:	819a      	strh	r2, [r3, #12]
-#if TCP_OVERSIZE_DBGCHECK
-  /* By trimming, realloc may have actually shrunk the pbuf, so clear oversize_left */
-  useg->oversize_left = 0;
- 800c2c0:	697b      	ldr	r3, [r7, #20]
- 800c2c2:	2200      	movs	r2, #0
- 800c2c4:	815a      	strh	r2, [r3, #10]
-#endif /* TCP_OVERSIZE_DBGCHECK */
-
-  /* Add back to the queue with new trimmed pbuf */
-  pcb->snd_queuelen += pbuf_clen(useg->p);
- 800c2c6:	697b      	ldr	r3, [r7, #20]
- 800c2c8:	685b      	ldr	r3, [r3, #4]
- 800c2ca:	4618      	mov	r0, r3
- 800c2cc:	f7fa ff0a 	bl	80070e4 <pbuf_clen>
- 800c2d0:	4603      	mov	r3, r0
- 800c2d2:	461a      	mov	r2, r3
- 800c2d4:	687b      	ldr	r3, [r7, #4]
- 800c2d6:	f8b3 3066 	ldrh.w	r3, [r3, #102]	; 0x66
- 800c2da:	4413      	add	r3, r2
- 800c2dc:	b29a      	uxth	r2, r3
- 800c2de:	687b      	ldr	r3, [r7, #4]
- 800c2e0:	f8a3 2066 	strh.w	r2, [r3, #102]	; 0x66
-#endif /* TCP_CHECKSUM_ON_COPY */
-
-  /* Update number of segments on the queues. Note that length now may
-   * exceed TCP_SND_QUEUELEN! We don't have to touch pcb->snd_buf
-   * because the total amount of data is constant when packet is split */
-  pcb->snd_queuelen += pbuf_clen(seg->p);
- 800c2e4:	69bb      	ldr	r3, [r7, #24]
- 800c2e6:	685b      	ldr	r3, [r3, #4]
- 800c2e8:	4618      	mov	r0, r3
- 800c2ea:	f7fa fefb 	bl	80070e4 <pbuf_clen>
- 800c2ee:	4603      	mov	r3, r0
- 800c2f0:	461a      	mov	r2, r3
- 800c2f2:	687b      	ldr	r3, [r7, #4]
- 800c2f4:	f8b3 3066 	ldrh.w	r3, [r3, #102]	; 0x66
- 800c2f8:	4413      	add	r3, r2
- 800c2fa:	b29a      	uxth	r2, r3
- 800c2fc:	687b      	ldr	r3, [r7, #4]
- 800c2fe:	f8a3 2066 	strh.w	r2, [r3, #102]	; 0x66
-
-  /* Finally insert remainder into queue after split (which stays head) */
-  seg->next = useg->next;
- 800c302:	697b      	ldr	r3, [r7, #20]
- 800c304:	681a      	ldr	r2, [r3, #0]
- 800c306:	69bb      	ldr	r3, [r7, #24]
- 800c308:	601a      	str	r2, [r3, #0]
-  useg->next = seg;
- 800c30a:	697b      	ldr	r3, [r7, #20]
- 800c30c:	69ba      	ldr	r2, [r7, #24]
- 800c30e:	601a      	str	r2, [r3, #0]
-
-#if TCP_OVERSIZE
-  /* If remainder is last segment on the unsent, ensure we clear the oversize amount
-   * because the remainder is always sized to the exact remaining amount */
-  if (seg->next == NULL) {
- 800c310:	69bb      	ldr	r3, [r7, #24]
- 800c312:	681b      	ldr	r3, [r3, #0]
- 800c314:	2b00      	cmp	r3, #0
- 800c316:	d103      	bne.n	800c320 <tcp_split_unsent_seg+0x240>
-    pcb->unsent_oversize = 0;
- 800c318:	687b      	ldr	r3, [r7, #4]
- 800c31a:	2200      	movs	r2, #0
- 800c31c:	f8a3 2068 	strh.w	r2, [r3, #104]	; 0x68
-  }
-#endif /* TCP_OVERSIZE */
-
-  return ERR_OK;
- 800c320:	2300      	movs	r3, #0
- 800c322:	e016      	b.n	800c352 <tcp_split_unsent_seg+0x272>
-    goto memerr;
- 800c324:	bf00      	nop
- 800c326:	e002      	b.n	800c32e <tcp_split_unsent_seg+0x24e>
-    goto memerr;
- 800c328:	bf00      	nop
- 800c32a:	e000      	b.n	800c32e <tcp_split_unsent_seg+0x24e>
-    goto memerr;
- 800c32c:	bf00      	nop
-memerr:
-  TCP_STATS_INC(tcp.memerr);
-
-  LWIP_ASSERT("seg == NULL", seg == NULL);
- 800c32e:	69bb      	ldr	r3, [r7, #24]
- 800c330:	2b00      	cmp	r3, #0
- 800c332:	d006      	beq.n	800c342 <tcp_split_unsent_seg+0x262>
- 800c334:	4b09      	ldr	r3, [pc, #36]	; (800c35c <tcp_split_unsent_seg+0x27c>)
- 800c336:	f44f 7276 	mov.w	r2, #984	; 0x3d8
- 800c33a:	490e      	ldr	r1, [pc, #56]	; (800c374 <tcp_split_unsent_seg+0x294>)
- 800c33c:	4809      	ldr	r0, [pc, #36]	; (800c364 <tcp_split_unsent_seg+0x284>)
- 800c33e:	f004 fc43 	bl	8010bc8 <iprintf>
-  if (p != NULL) {
- 800c342:	693b      	ldr	r3, [r7, #16]
- 800c344:	2b00      	cmp	r3, #0
- 800c346:	d002      	beq.n	800c34e <tcp_split_unsent_seg+0x26e>
-    pbuf_free(p);
- 800c348:	6938      	ldr	r0, [r7, #16]
- 800c34a:	f7fa fe43 	bl	8006fd4 <pbuf_free>
-  }
-
-  return ERR_MEM;
- 800c34e:	f04f 33ff 	mov.w	r3, #4294967295
-}
- 800c352:	4618      	mov	r0, r3
- 800c354:	3724      	adds	r7, #36	; 0x24
- 800c356:	46bd      	mov	sp, r7
- 800c358:	bd90      	pop	{r4, r7, pc}
- 800c35a:	bf00      	nop
- 800c35c:	08013618 	.word	0x08013618
- 800c360:	08013a08 	.word	0x08013a08
- 800c364:	0801366c 	.word	0x0801366c
- 800c368:	08013a2c 	.word	0x08013a2c
- 800c36c:	08013a50 	.word	0x08013a50
- 800c370:	08013a60 	.word	0x08013a60
- 800c374:	08013a70 	.word	0x08013a70
-
-0800c378 <tcp_send_fin>:
- * @param pcb the tcp_pcb over which to send a segment
- * @return ERR_OK if sent, another err_t otherwise
- */
-err_t
-tcp_send_fin(struct tcp_pcb *pcb)
-{
- 800c378:	b590      	push	{r4, r7, lr}
- 800c37a:	b085      	sub	sp, #20
- 800c37c:	af00      	add	r7, sp, #0
- 800c37e:	6078      	str	r0, [r7, #4]
-  LWIP_ASSERT("tcp_send_fin: invalid pcb", pcb != NULL);
- 800c380:	687b      	ldr	r3, [r7, #4]
- 800c382:	2b00      	cmp	r3, #0
- 800c384:	d106      	bne.n	800c394 <tcp_send_fin+0x1c>
- 800c386:	4b21      	ldr	r3, [pc, #132]	; (800c40c <tcp_send_fin+0x94>)
- 800c388:	f240 32eb 	movw	r2, #1003	; 0x3eb
- 800c38c:	4920      	ldr	r1, [pc, #128]	; (800c410 <tcp_send_fin+0x98>)
- 800c38e:	4821      	ldr	r0, [pc, #132]	; (800c414 <tcp_send_fin+0x9c>)
- 800c390:	f004 fc1a 	bl	8010bc8 <iprintf>
-
-  /* first, try to add the fin to the last unsent segment */
-  if (pcb->unsent != NULL) {
- 800c394:	687b      	ldr	r3, [r7, #4]
- 800c396:	6edb      	ldr	r3, [r3, #108]	; 0x6c
- 800c398:	2b00      	cmp	r3, #0
- 800c39a:	d02e      	beq.n	800c3fa <tcp_send_fin+0x82>
-    struct tcp_seg *last_unsent;
-    for (last_unsent = pcb->unsent; last_unsent->next != NULL;
- 800c39c:	687b      	ldr	r3, [r7, #4]
- 800c39e:	6edb      	ldr	r3, [r3, #108]	; 0x6c
- 800c3a0:	60fb      	str	r3, [r7, #12]
- 800c3a2:	e002      	b.n	800c3aa <tcp_send_fin+0x32>
-         last_unsent = last_unsent->next);
- 800c3a4:	68fb      	ldr	r3, [r7, #12]
- 800c3a6:	681b      	ldr	r3, [r3, #0]
- 800c3a8:	60fb      	str	r3, [r7, #12]
-    for (last_unsent = pcb->unsent; last_unsent->next != NULL;
- 800c3aa:	68fb      	ldr	r3, [r7, #12]
- 800c3ac:	681b      	ldr	r3, [r3, #0]
- 800c3ae:	2b00      	cmp	r3, #0
- 800c3b0:	d1f8      	bne.n	800c3a4 <tcp_send_fin+0x2c>
-
-    if ((TCPH_FLAGS(last_unsent->tcphdr) & (TCP_SYN | TCP_FIN | TCP_RST)) == 0) {
- 800c3b2:	68fb      	ldr	r3, [r7, #12]
- 800c3b4:	691b      	ldr	r3, [r3, #16]
- 800c3b6:	899b      	ldrh	r3, [r3, #12]
- 800c3b8:	b29b      	uxth	r3, r3
- 800c3ba:	4618      	mov	r0, r3
- 800c3bc:	f7f9 f8c6 	bl	800554c <lwip_htons>
- 800c3c0:	4603      	mov	r3, r0
- 800c3c2:	b2db      	uxtb	r3, r3
- 800c3c4:	f003 0307 	and.w	r3, r3, #7
- 800c3c8:	2b00      	cmp	r3, #0
- 800c3ca:	d116      	bne.n	800c3fa <tcp_send_fin+0x82>
-      /* no SYN/FIN/RST flag in the header, we can add the FIN flag */
-      TCPH_SET_FLAG(last_unsent->tcphdr, TCP_FIN);
- 800c3cc:	68fb      	ldr	r3, [r7, #12]
- 800c3ce:	691b      	ldr	r3, [r3, #16]
- 800c3d0:	899b      	ldrh	r3, [r3, #12]
- 800c3d2:	b29c      	uxth	r4, r3
- 800c3d4:	2001      	movs	r0, #1
- 800c3d6:	f7f9 f8b9 	bl	800554c <lwip_htons>
- 800c3da:	4603      	mov	r3, r0
- 800c3dc:	461a      	mov	r2, r3
- 800c3de:	68fb      	ldr	r3, [r7, #12]
- 800c3e0:	691b      	ldr	r3, [r3, #16]
- 800c3e2:	4322      	orrs	r2, r4
- 800c3e4:	b292      	uxth	r2, r2
- 800c3e6:	819a      	strh	r2, [r3, #12]
-      tcp_set_flags(pcb, TF_FIN);
- 800c3e8:	687b      	ldr	r3, [r7, #4]
- 800c3ea:	8b5b      	ldrh	r3, [r3, #26]
- 800c3ec:	f043 0320 	orr.w	r3, r3, #32
- 800c3f0:	b29a      	uxth	r2, r3
- 800c3f2:	687b      	ldr	r3, [r7, #4]
- 800c3f4:	835a      	strh	r2, [r3, #26]
-      return ERR_OK;
- 800c3f6:	2300      	movs	r3, #0
- 800c3f8:	e004      	b.n	800c404 <tcp_send_fin+0x8c>
-    }
-  }
-  /* no data, no length, flags, copy=1, no optdata */
-  return tcp_enqueue_flags(pcb, TCP_FIN);
- 800c3fa:	2101      	movs	r1, #1
- 800c3fc:	6878      	ldr	r0, [r7, #4]
- 800c3fe:	f000 f80b 	bl	800c418 <tcp_enqueue_flags>
- 800c402:	4603      	mov	r3, r0
-}
- 800c404:	4618      	mov	r0, r3
- 800c406:	3714      	adds	r7, #20
- 800c408:	46bd      	mov	sp, r7
- 800c40a:	bd90      	pop	{r4, r7, pc}
- 800c40c:	08013618 	.word	0x08013618
- 800c410:	08013a7c 	.word	0x08013a7c
- 800c414:	0801366c 	.word	0x0801366c
-
-0800c418 <tcp_enqueue_flags>:
- * @param pcb Protocol control block for the TCP connection.
- * @param flags TCP header flags to set in the outgoing segment.
- */
-err_t
-tcp_enqueue_flags(struct tcp_pcb *pcb, u8_t flags)
-{
- 800c418:	b580      	push	{r7, lr}
- 800c41a:	b088      	sub	sp, #32
- 800c41c:	af02      	add	r7, sp, #8
- 800c41e:	6078      	str	r0, [r7, #4]
- 800c420:	460b      	mov	r3, r1
- 800c422:	70fb      	strb	r3, [r7, #3]
-  struct pbuf *p;
-  struct tcp_seg *seg;
-  u8_t optflags = 0;
- 800c424:	2300      	movs	r3, #0
- 800c426:	75fb      	strb	r3, [r7, #23]
-  u8_t optlen = 0;
- 800c428:	2300      	movs	r3, #0
- 800c42a:	75bb      	strb	r3, [r7, #22]
-
-  LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_enqueue_flags: queuelen: %"U16_F"\n", (u16_t)pcb->snd_queuelen));
-
-  LWIP_ASSERT("tcp_enqueue_flags: need either TCP_SYN or TCP_FIN in flags (programmer violates API)",
- 800c42c:	78fb      	ldrb	r3, [r7, #3]
- 800c42e:	f003 0303 	and.w	r3, r3, #3
- 800c432:	2b00      	cmp	r3, #0
- 800c434:	d106      	bne.n	800c444 <tcp_enqueue_flags+0x2c>
- 800c436:	4b67      	ldr	r3, [pc, #412]	; (800c5d4 <tcp_enqueue_flags+0x1bc>)
- 800c438:	f240 4211 	movw	r2, #1041	; 0x411
- 800c43c:	4966      	ldr	r1, [pc, #408]	; (800c5d8 <tcp_enqueue_flags+0x1c0>)
- 800c43e:	4867      	ldr	r0, [pc, #412]	; (800c5dc <tcp_enqueue_flags+0x1c4>)
- 800c440:	f004 fbc2 	bl	8010bc8 <iprintf>
-              (flags & (TCP_SYN | TCP_FIN)) != 0);
-  LWIP_ASSERT("tcp_enqueue_flags: invalid pcb", pcb != NULL);
- 800c444:	687b      	ldr	r3, [r7, #4]
- 800c446:	2b00      	cmp	r3, #0
- 800c448:	d106      	bne.n	800c458 <tcp_enqueue_flags+0x40>
- 800c44a:	4b62      	ldr	r3, [pc, #392]	; (800c5d4 <tcp_enqueue_flags+0x1bc>)
- 800c44c:	f240 4213 	movw	r2, #1043	; 0x413
- 800c450:	4963      	ldr	r1, [pc, #396]	; (800c5e0 <tcp_enqueue_flags+0x1c8>)
- 800c452:	4862      	ldr	r0, [pc, #392]	; (800c5dc <tcp_enqueue_flags+0x1c4>)
- 800c454:	f004 fbb8 	bl	8010bc8 <iprintf>
-
-  /* No need to check pcb->snd_queuelen if only SYN or FIN are allowed! */
-
-  /* Get options for this segment. This is a special case since this is the
-     only place where a SYN can be sent. */
-  if (flags & TCP_SYN) {
- 800c458:	78fb      	ldrb	r3, [r7, #3]
- 800c45a:	f003 0302 	and.w	r3, r3, #2
- 800c45e:	2b00      	cmp	r3, #0
- 800c460:	d001      	beq.n	800c466 <tcp_enqueue_flags+0x4e>
-    optflags = TF_SEG_OPTS_MSS;
- 800c462:	2301      	movs	r3, #1
- 800c464:	75fb      	strb	r3, [r7, #23]
-    /* Make sure the timestamp option is only included in data segments if we
-       agreed about it with the remote host (and in active open SYN segments). */
-    optflags |= TF_SEG_OPTS_TS;
-  }
-#endif /* LWIP_TCP_TIMESTAMPS */
-  optlen = LWIP_TCP_OPT_LENGTH_SEGMENT(optflags, pcb);
- 800c466:	7dfb      	ldrb	r3, [r7, #23]
- 800c468:	009b      	lsls	r3, r3, #2
- 800c46a:	b2db      	uxtb	r3, r3
- 800c46c:	f003 0304 	and.w	r3, r3, #4
- 800c470:	75bb      	strb	r3, [r7, #22]
-
-  /* Allocate pbuf with room for TCP header + options */
-  if ((p = pbuf_alloc(PBUF_TRANSPORT, optlen, PBUF_RAM)) == NULL) {
- 800c472:	7dbb      	ldrb	r3, [r7, #22]
- 800c474:	b29b      	uxth	r3, r3
- 800c476:	f44f 7220 	mov.w	r2, #640	; 0x280
- 800c47a:	4619      	mov	r1, r3
- 800c47c:	2036      	movs	r0, #54	; 0x36
- 800c47e:	f7fa fac5 	bl	8006a0c <pbuf_alloc>
- 800c482:	60f8      	str	r0, [r7, #12]
- 800c484:	68fb      	ldr	r3, [r7, #12]
- 800c486:	2b00      	cmp	r3, #0
- 800c488:	d109      	bne.n	800c49e <tcp_enqueue_flags+0x86>
-    tcp_set_flags(pcb, TF_NAGLEMEMERR);
- 800c48a:	687b      	ldr	r3, [r7, #4]
- 800c48c:	8b5b      	ldrh	r3, [r3, #26]
- 800c48e:	f043 0380 	orr.w	r3, r3, #128	; 0x80
- 800c492:	b29a      	uxth	r2, r3
- 800c494:	687b      	ldr	r3, [r7, #4]
- 800c496:	835a      	strh	r2, [r3, #26]
-    TCP_STATS_INC(tcp.memerr);
-    return ERR_MEM;
- 800c498:	f04f 33ff 	mov.w	r3, #4294967295
- 800c49c:	e095      	b.n	800c5ca <tcp_enqueue_flags+0x1b2>
-  }
-  LWIP_ASSERT("tcp_enqueue_flags: check that first pbuf can hold optlen",
- 800c49e:	68fb      	ldr	r3, [r7, #12]
- 800c4a0:	895a      	ldrh	r2, [r3, #10]
- 800c4a2:	7dbb      	ldrb	r3, [r7, #22]
- 800c4a4:	b29b      	uxth	r3, r3
- 800c4a6:	429a      	cmp	r2, r3
- 800c4a8:	d206      	bcs.n	800c4b8 <tcp_enqueue_flags+0xa0>
- 800c4aa:	4b4a      	ldr	r3, [pc, #296]	; (800c5d4 <tcp_enqueue_flags+0x1bc>)
- 800c4ac:	f240 4239 	movw	r2, #1081	; 0x439
- 800c4b0:	494c      	ldr	r1, [pc, #304]	; (800c5e4 <tcp_enqueue_flags+0x1cc>)
- 800c4b2:	484a      	ldr	r0, [pc, #296]	; (800c5dc <tcp_enqueue_flags+0x1c4>)
- 800c4b4:	f004 fb88 	bl	8010bc8 <iprintf>
-              (p->len >= optlen));
-
-  /* Allocate memory for tcp_seg, and fill in fields. */
-  if ((seg = tcp_create_segment(pcb, p, flags, pcb->snd_lbb, optflags)) == NULL) {
- 800c4b8:	687b      	ldr	r3, [r7, #4]
- 800c4ba:	6dd9      	ldr	r1, [r3, #92]	; 0x5c
- 800c4bc:	78fa      	ldrb	r2, [r7, #3]
- 800c4be:	7dfb      	ldrb	r3, [r7, #23]
- 800c4c0:	9300      	str	r3, [sp, #0]
- 800c4c2:	460b      	mov	r3, r1
- 800c4c4:	68f9      	ldr	r1, [r7, #12]
- 800c4c6:	6878      	ldr	r0, [r7, #4]
- 800c4c8:	f7ff f8b8 	bl	800b63c <tcp_create_segment>
- 800c4cc:	60b8      	str	r0, [r7, #8]
- 800c4ce:	68bb      	ldr	r3, [r7, #8]
- 800c4d0:	2b00      	cmp	r3, #0
- 800c4d2:	d109      	bne.n	800c4e8 <tcp_enqueue_flags+0xd0>
-    tcp_set_flags(pcb, TF_NAGLEMEMERR);
- 800c4d4:	687b      	ldr	r3, [r7, #4]
- 800c4d6:	8b5b      	ldrh	r3, [r3, #26]
- 800c4d8:	f043 0380 	orr.w	r3, r3, #128	; 0x80
- 800c4dc:	b29a      	uxth	r2, r3
- 800c4de:	687b      	ldr	r3, [r7, #4]
- 800c4e0:	835a      	strh	r2, [r3, #26]
-    TCP_STATS_INC(tcp.memerr);
-    return ERR_MEM;
- 800c4e2:	f04f 33ff 	mov.w	r3, #4294967295
- 800c4e6:	e070      	b.n	800c5ca <tcp_enqueue_flags+0x1b2>
-  }
-  LWIP_ASSERT("seg->tcphdr not aligned", ((mem_ptr_t)seg->tcphdr % LWIP_MIN(MEM_ALIGNMENT, 4)) == 0);
- 800c4e8:	68bb      	ldr	r3, [r7, #8]
- 800c4ea:	691b      	ldr	r3, [r3, #16]
- 800c4ec:	f003 0303 	and.w	r3, r3, #3
- 800c4f0:	2b00      	cmp	r3, #0
- 800c4f2:	d006      	beq.n	800c502 <tcp_enqueue_flags+0xea>
- 800c4f4:	4b37      	ldr	r3, [pc, #220]	; (800c5d4 <tcp_enqueue_flags+0x1bc>)
- 800c4f6:	f240 4242 	movw	r2, #1090	; 0x442
- 800c4fa:	493b      	ldr	r1, [pc, #236]	; (800c5e8 <tcp_enqueue_flags+0x1d0>)
- 800c4fc:	4837      	ldr	r0, [pc, #220]	; (800c5dc <tcp_enqueue_flags+0x1c4>)
- 800c4fe:	f004 fb63 	bl	8010bc8 <iprintf>
-  LWIP_ASSERT("tcp_enqueue_flags: invalid segment length", seg->len == 0);
- 800c502:	68bb      	ldr	r3, [r7, #8]
- 800c504:	891b      	ldrh	r3, [r3, #8]
- 800c506:	2b00      	cmp	r3, #0
- 800c508:	d006      	beq.n	800c518 <tcp_enqueue_flags+0x100>
- 800c50a:	4b32      	ldr	r3, [pc, #200]	; (800c5d4 <tcp_enqueue_flags+0x1bc>)
- 800c50c:	f240 4243 	movw	r2, #1091	; 0x443
- 800c510:	4936      	ldr	r1, [pc, #216]	; (800c5ec <tcp_enqueue_flags+0x1d4>)
- 800c512:	4832      	ldr	r0, [pc, #200]	; (800c5dc <tcp_enqueue_flags+0x1c4>)
- 800c514:	f004 fb58 	bl	8010bc8 <iprintf>
-               lwip_ntohl(seg->tcphdr->seqno),
-               lwip_ntohl(seg->tcphdr->seqno) + TCP_TCPLEN(seg),
-               (u16_t)flags));
-
-  /* Now append seg to pcb->unsent queue */
-  if (pcb->unsent == NULL) {
- 800c518:	687b      	ldr	r3, [r7, #4]
- 800c51a:	6edb      	ldr	r3, [r3, #108]	; 0x6c
- 800c51c:	2b00      	cmp	r3, #0
- 800c51e:	d103      	bne.n	800c528 <tcp_enqueue_flags+0x110>
-    pcb->unsent = seg;
- 800c520:	687b      	ldr	r3, [r7, #4]
- 800c522:	68ba      	ldr	r2, [r7, #8]
- 800c524:	66da      	str	r2, [r3, #108]	; 0x6c
- 800c526:	e00d      	b.n	800c544 <tcp_enqueue_flags+0x12c>
-  } else {
-    struct tcp_seg *useg;
-    for (useg = pcb->unsent; useg->next != NULL; useg = useg->next);
- 800c528:	687b      	ldr	r3, [r7, #4]
- 800c52a:	6edb      	ldr	r3, [r3, #108]	; 0x6c
- 800c52c:	613b      	str	r3, [r7, #16]
- 800c52e:	e002      	b.n	800c536 <tcp_enqueue_flags+0x11e>
- 800c530:	693b      	ldr	r3, [r7, #16]
- 800c532:	681b      	ldr	r3, [r3, #0]
- 800c534:	613b      	str	r3, [r7, #16]
- 800c536:	693b      	ldr	r3, [r7, #16]
- 800c538:	681b      	ldr	r3, [r3, #0]
- 800c53a:	2b00      	cmp	r3, #0
- 800c53c:	d1f8      	bne.n	800c530 <tcp_enqueue_flags+0x118>
-    useg->next = seg;
- 800c53e:	693b      	ldr	r3, [r7, #16]
- 800c540:	68ba      	ldr	r2, [r7, #8]
- 800c542:	601a      	str	r2, [r3, #0]
-  }
-#if TCP_OVERSIZE
-  /* The new unsent tail has no space */
-  pcb->unsent_oversize = 0;
- 800c544:	687b      	ldr	r3, [r7, #4]
- 800c546:	2200      	movs	r2, #0
- 800c548:	f8a3 2068 	strh.w	r2, [r3, #104]	; 0x68
-#endif /* TCP_OVERSIZE */
-
-  /* SYN and FIN bump the sequence number */
-  if ((flags & TCP_SYN) || (flags & TCP_FIN)) {
- 800c54c:	78fb      	ldrb	r3, [r7, #3]
- 800c54e:	f003 0302 	and.w	r3, r3, #2
- 800c552:	2b00      	cmp	r3, #0
- 800c554:	d104      	bne.n	800c560 <tcp_enqueue_flags+0x148>
- 800c556:	78fb      	ldrb	r3, [r7, #3]
- 800c558:	f003 0301 	and.w	r3, r3, #1
- 800c55c:	2b00      	cmp	r3, #0
- 800c55e:	d004      	beq.n	800c56a <tcp_enqueue_flags+0x152>
-    pcb->snd_lbb++;
- 800c560:	687b      	ldr	r3, [r7, #4]
- 800c562:	6ddb      	ldr	r3, [r3, #92]	; 0x5c
- 800c564:	1c5a      	adds	r2, r3, #1
- 800c566:	687b      	ldr	r3, [r7, #4]
- 800c568:	65da      	str	r2, [r3, #92]	; 0x5c
-    /* optlen does not influence snd_buf */
-  }
-  if (flags & TCP_FIN) {
- 800c56a:	78fb      	ldrb	r3, [r7, #3]
- 800c56c:	f003 0301 	and.w	r3, r3, #1
- 800c570:	2b00      	cmp	r3, #0
- 800c572:	d006      	beq.n	800c582 <tcp_enqueue_flags+0x16a>
-    tcp_set_flags(pcb, TF_FIN);
- 800c574:	687b      	ldr	r3, [r7, #4]
- 800c576:	8b5b      	ldrh	r3, [r3, #26]
- 800c578:	f043 0320 	orr.w	r3, r3, #32
- 800c57c:	b29a      	uxth	r2, r3
- 800c57e:	687b      	ldr	r3, [r7, #4]
- 800c580:	835a      	strh	r2, [r3, #26]
-  }
-
-  /* update number of segments on the queues */
-  pcb->snd_queuelen += pbuf_clen(seg->p);
- 800c582:	68bb      	ldr	r3, [r7, #8]
- 800c584:	685b      	ldr	r3, [r3, #4]
- 800c586:	4618      	mov	r0, r3
- 800c588:	f7fa fdac 	bl	80070e4 <pbuf_clen>
- 800c58c:	4603      	mov	r3, r0
- 800c58e:	461a      	mov	r2, r3
- 800c590:	687b      	ldr	r3, [r7, #4]
- 800c592:	f8b3 3066 	ldrh.w	r3, [r3, #102]	; 0x66
- 800c596:	4413      	add	r3, r2
- 800c598:	b29a      	uxth	r2, r3
- 800c59a:	687b      	ldr	r3, [r7, #4]
- 800c59c:	f8a3 2066 	strh.w	r2, [r3, #102]	; 0x66
-  LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_enqueue_flags: %"S16_F" (after enqueued)\n", pcb->snd_queuelen));
-  if (pcb->snd_queuelen != 0) {
- 800c5a0:	687b      	ldr	r3, [r7, #4]
- 800c5a2:	f8b3 3066 	ldrh.w	r3, [r3, #102]	; 0x66
- 800c5a6:	2b00      	cmp	r3, #0
- 800c5a8:	d00e      	beq.n	800c5c8 <tcp_enqueue_flags+0x1b0>
-    LWIP_ASSERT("tcp_enqueue_flags: invalid queue length",
- 800c5aa:	687b      	ldr	r3, [r7, #4]
- 800c5ac:	6f1b      	ldr	r3, [r3, #112]	; 0x70
- 800c5ae:	2b00      	cmp	r3, #0
- 800c5b0:	d10a      	bne.n	800c5c8 <tcp_enqueue_flags+0x1b0>
- 800c5b2:	687b      	ldr	r3, [r7, #4]
- 800c5b4:	6edb      	ldr	r3, [r3, #108]	; 0x6c
- 800c5b6:	2b00      	cmp	r3, #0
- 800c5b8:	d106      	bne.n	800c5c8 <tcp_enqueue_flags+0x1b0>
- 800c5ba:	4b06      	ldr	r3, [pc, #24]	; (800c5d4 <tcp_enqueue_flags+0x1bc>)
- 800c5bc:	f240 4265 	movw	r2, #1125	; 0x465
- 800c5c0:	490b      	ldr	r1, [pc, #44]	; (800c5f0 <tcp_enqueue_flags+0x1d8>)
- 800c5c2:	4806      	ldr	r0, [pc, #24]	; (800c5dc <tcp_enqueue_flags+0x1c4>)
- 800c5c4:	f004 fb00 	bl	8010bc8 <iprintf>
-                pcb->unacked != NULL || pcb->unsent != NULL);
-  }
-
-  return ERR_OK;
- 800c5c8:	2300      	movs	r3, #0
-}
- 800c5ca:	4618      	mov	r0, r3
- 800c5cc:	3718      	adds	r7, #24
- 800c5ce:	46bd      	mov	sp, r7
- 800c5d0:	bd80      	pop	{r7, pc}
- 800c5d2:	bf00      	nop
- 800c5d4:	08013618 	.word	0x08013618
- 800c5d8:	08013a98 	.word	0x08013a98
- 800c5dc:	0801366c 	.word	0x0801366c
- 800c5e0:	08013af0 	.word	0x08013af0
- 800c5e4:	08013b10 	.word	0x08013b10
- 800c5e8:	08013b4c 	.word	0x08013b4c
- 800c5ec:	08013b64 	.word	0x08013b64
- 800c5f0:	08013b90 	.word	0x08013b90
-
-0800c5f4 <tcp_output>:
- * @return ERR_OK if data has been sent or nothing to send
- *         another err_t on error
- */
-err_t
-tcp_output(struct tcp_pcb *pcb)
-{
- 800c5f4:	b5b0      	push	{r4, r5, r7, lr}
- 800c5f6:	b08a      	sub	sp, #40	; 0x28
- 800c5f8:	af00      	add	r7, sp, #0
- 800c5fa:	6078      	str	r0, [r7, #4]
-  s16_t i = 0;
-#endif /* TCP_CWND_DEBUG */
-
-  LWIP_ASSERT_CORE_LOCKED();
-
-  LWIP_ASSERT("tcp_output: invalid pcb", pcb != NULL);
- 800c5fc:	687b      	ldr	r3, [r7, #4]
- 800c5fe:	2b00      	cmp	r3, #0
- 800c600:	d106      	bne.n	800c610 <tcp_output+0x1c>
- 800c602:	4b8a      	ldr	r3, [pc, #552]	; (800c82c <tcp_output+0x238>)
- 800c604:	f240 42e1 	movw	r2, #1249	; 0x4e1
- 800c608:	4989      	ldr	r1, [pc, #548]	; (800c830 <tcp_output+0x23c>)
- 800c60a:	488a      	ldr	r0, [pc, #552]	; (800c834 <tcp_output+0x240>)
- 800c60c:	f004 fadc 	bl	8010bc8 <iprintf>
-  /* pcb->state LISTEN not allowed here */
-  LWIP_ASSERT("don't call tcp_output for listen-pcbs",
- 800c610:	687b      	ldr	r3, [r7, #4]
- 800c612:	7d1b      	ldrb	r3, [r3, #20]
- 800c614:	2b01      	cmp	r3, #1
- 800c616:	d106      	bne.n	800c626 <tcp_output+0x32>
- 800c618:	4b84      	ldr	r3, [pc, #528]	; (800c82c <tcp_output+0x238>)
- 800c61a:	f240 42e3 	movw	r2, #1251	; 0x4e3
- 800c61e:	4986      	ldr	r1, [pc, #536]	; (800c838 <tcp_output+0x244>)
- 800c620:	4884      	ldr	r0, [pc, #528]	; (800c834 <tcp_output+0x240>)
- 800c622:	f004 fad1 	bl	8010bc8 <iprintf>
-
-  /* First, check if we are invoked by the TCP input processing
-     code. If so, we do not output anything. Instead, we rely on the
-     input processing code to call us when input processing is done
-     with. */
-  if (tcp_input_pcb == pcb) {
- 800c626:	4b85      	ldr	r3, [pc, #532]	; (800c83c <tcp_output+0x248>)
- 800c628:	681b      	ldr	r3, [r3, #0]
- 800c62a:	687a      	ldr	r2, [r7, #4]
- 800c62c:	429a      	cmp	r2, r3
- 800c62e:	d101      	bne.n	800c634 <tcp_output+0x40>
-    return ERR_OK;
- 800c630:	2300      	movs	r3, #0
- 800c632:	e1d1      	b.n	800c9d8 <tcp_output+0x3e4>
-  }
-
-  wnd = LWIP_MIN(pcb->snd_wnd, pcb->cwnd);
- 800c634:	687b      	ldr	r3, [r7, #4]
- 800c636:	f8b3 2048 	ldrh.w	r2, [r3, #72]	; 0x48
- 800c63a:	687b      	ldr	r3, [r7, #4]
- 800c63c:	f8b3 3060 	ldrh.w	r3, [r3, #96]	; 0x60
- 800c640:	4293      	cmp	r3, r2
- 800c642:	bf28      	it	cs
- 800c644:	4613      	movcs	r3, r2
- 800c646:	b29b      	uxth	r3, r3
- 800c648:	61bb      	str	r3, [r7, #24]
-
-  seg = pcb->unsent;
- 800c64a:	687b      	ldr	r3, [r7, #4]
- 800c64c:	6edb      	ldr	r3, [r3, #108]	; 0x6c
- 800c64e:	627b      	str	r3, [r7, #36]	; 0x24
-
-  if (seg == NULL) {
- 800c650:	6a7b      	ldr	r3, [r7, #36]	; 0x24
- 800c652:	2b00      	cmp	r3, #0
- 800c654:	d10b      	bne.n	800c66e <tcp_output+0x7a>
-                                 ", seg == NULL, ack %"U32_F"\n",
-                                 pcb->snd_wnd, pcb->cwnd, wnd, pcb->lastack));
-
-    /* If the TF_ACK_NOW flag is set and the ->unsent queue is empty, construct
-     * an empty ACK segment and send it. */
-    if (pcb->flags & TF_ACK_NOW) {
- 800c656:	687b      	ldr	r3, [r7, #4]
- 800c658:	8b5b      	ldrh	r3, [r3, #26]
- 800c65a:	f003 0302 	and.w	r3, r3, #2
- 800c65e:	2b00      	cmp	r3, #0
- 800c660:	f000 81ad 	beq.w	800c9be <tcp_output+0x3ca>
-      return tcp_send_empty_ack(pcb);
- 800c664:	6878      	ldr	r0, [r7, #4]
- 800c666:	f000 fdd7 	bl	800d218 <tcp_send_empty_ack>
- 800c66a:	4603      	mov	r3, r0
- 800c66c:	e1b4      	b.n	800c9d8 <tcp_output+0x3e4>
-                 pcb->snd_wnd, pcb->cwnd, wnd,
-                 lwip_ntohl(seg->tcphdr->seqno) - pcb->lastack + seg->len,
-                 lwip_ntohl(seg->tcphdr->seqno), pcb->lastack));
-  }
-
-  netif = tcp_route(pcb, &pcb->local_ip, &pcb->remote_ip);
- 800c66e:	6879      	ldr	r1, [r7, #4]
- 800c670:	687b      	ldr	r3, [r7, #4]
- 800c672:	3304      	adds	r3, #4
- 800c674:	461a      	mov	r2, r3
- 800c676:	6878      	ldr	r0, [r7, #4]
- 800c678:	f7fe ffc4 	bl	800b604 <tcp_route>
- 800c67c:	6178      	str	r0, [r7, #20]
-  if (netif == NULL) {
- 800c67e:	697b      	ldr	r3, [r7, #20]
- 800c680:	2b00      	cmp	r3, #0
- 800c682:	d102      	bne.n	800c68a <tcp_output+0x96>
-    return ERR_RTE;
- 800c684:	f06f 0303 	mvn.w	r3, #3
- 800c688:	e1a6      	b.n	800c9d8 <tcp_output+0x3e4>
-  }
-
-  /* If we don't have a local IP address, we get one from netif */
-  if (ip_addr_isany(&pcb->local_ip)) {
- 800c68a:	687b      	ldr	r3, [r7, #4]
- 800c68c:	2b00      	cmp	r3, #0
- 800c68e:	d003      	beq.n	800c698 <tcp_output+0xa4>
- 800c690:	687b      	ldr	r3, [r7, #4]
- 800c692:	681b      	ldr	r3, [r3, #0]
- 800c694:	2b00      	cmp	r3, #0
- 800c696:	d111      	bne.n	800c6bc <tcp_output+0xc8>
-    const ip_addr_t *local_ip = ip_netif_get_local_ip(netif, &pcb->remote_ip);
- 800c698:	697b      	ldr	r3, [r7, #20]
- 800c69a:	2b00      	cmp	r3, #0
- 800c69c:	d002      	beq.n	800c6a4 <tcp_output+0xb0>
- 800c69e:	697b      	ldr	r3, [r7, #20]
- 800c6a0:	3304      	adds	r3, #4
- 800c6a2:	e000      	b.n	800c6a6 <tcp_output+0xb2>
- 800c6a4:	2300      	movs	r3, #0
- 800c6a6:	613b      	str	r3, [r7, #16]
-    if (local_ip == NULL) {
- 800c6a8:	693b      	ldr	r3, [r7, #16]
- 800c6aa:	2b00      	cmp	r3, #0
- 800c6ac:	d102      	bne.n	800c6b4 <tcp_output+0xc0>
-      return ERR_RTE;
- 800c6ae:	f06f 0303 	mvn.w	r3, #3
- 800c6b2:	e191      	b.n	800c9d8 <tcp_output+0x3e4>
-    }
-    ip_addr_copy(pcb->local_ip, *local_ip);
- 800c6b4:	693b      	ldr	r3, [r7, #16]
- 800c6b6:	681a      	ldr	r2, [r3, #0]
- 800c6b8:	687b      	ldr	r3, [r7, #4]
- 800c6ba:	601a      	str	r2, [r3, #0]
-  }
-
-  /* Handle the current segment not fitting within the window */
-  if (lwip_ntohl(seg->tcphdr->seqno) - pcb->lastack + seg->len > wnd) {
- 800c6bc:	6a7b      	ldr	r3, [r7, #36]	; 0x24
- 800c6be:	691b      	ldr	r3, [r3, #16]
- 800c6c0:	685b      	ldr	r3, [r3, #4]
- 800c6c2:	4618      	mov	r0, r3
- 800c6c4:	f7f8 ff57 	bl	8005576 <lwip_htonl>
- 800c6c8:	4602      	mov	r2, r0
- 800c6ca:	687b      	ldr	r3, [r7, #4]
- 800c6cc:	6c5b      	ldr	r3, [r3, #68]	; 0x44
- 800c6ce:	1ad3      	subs	r3, r2, r3
- 800c6d0:	6a7a      	ldr	r2, [r7, #36]	; 0x24
- 800c6d2:	8912      	ldrh	r2, [r2, #8]
- 800c6d4:	4413      	add	r3, r2
- 800c6d6:	69ba      	ldr	r2, [r7, #24]
- 800c6d8:	429a      	cmp	r2, r3
- 800c6da:	d227      	bcs.n	800c72c <tcp_output+0x138>
-     * within the remaining (could be 0) send window and RTO timer is not running (we
-     * have no in-flight data). If window is still too small after persist timer fires,
-     * then we split the segment. We don't consider the congestion window since a cwnd
-     * smaller than 1 SMSS implies in-flight data
-     */
-    if (wnd == pcb->snd_wnd && pcb->unacked == NULL && pcb->persist_backoff == 0) {
- 800c6dc:	687b      	ldr	r3, [r7, #4]
- 800c6de:	f8b3 3060 	ldrh.w	r3, [r3, #96]	; 0x60
- 800c6e2:	461a      	mov	r2, r3
- 800c6e4:	69bb      	ldr	r3, [r7, #24]
- 800c6e6:	4293      	cmp	r3, r2
- 800c6e8:	d114      	bne.n	800c714 <tcp_output+0x120>
- 800c6ea:	687b      	ldr	r3, [r7, #4]
- 800c6ec:	6f1b      	ldr	r3, [r3, #112]	; 0x70
- 800c6ee:	2b00      	cmp	r3, #0
- 800c6f0:	d110      	bne.n	800c714 <tcp_output+0x120>
- 800c6f2:	687b      	ldr	r3, [r7, #4]
- 800c6f4:	f893 3099 	ldrb.w	r3, [r3, #153]	; 0x99
- 800c6f8:	2b00      	cmp	r3, #0
- 800c6fa:	d10b      	bne.n	800c714 <tcp_output+0x120>
-      pcb->persist_cnt = 0;
- 800c6fc:	687b      	ldr	r3, [r7, #4]
- 800c6fe:	2200      	movs	r2, #0
- 800c700:	f883 2098 	strb.w	r2, [r3, #152]	; 0x98
-      pcb->persist_backoff = 1;
- 800c704:	687b      	ldr	r3, [r7, #4]
- 800c706:	2201      	movs	r2, #1
- 800c708:	f883 2099 	strb.w	r2, [r3, #153]	; 0x99
-      pcb->persist_probe = 0;
- 800c70c:	687b      	ldr	r3, [r7, #4]
- 800c70e:	2200      	movs	r2, #0
- 800c710:	f883 209a 	strb.w	r2, [r3, #154]	; 0x9a
-    }
-    /* We need an ACK, but can't send data now, so send an empty ACK */
-    if (pcb->flags & TF_ACK_NOW) {
- 800c714:	687b      	ldr	r3, [r7, #4]
- 800c716:	8b5b      	ldrh	r3, [r3, #26]
- 800c718:	f003 0302 	and.w	r3, r3, #2
- 800c71c:	2b00      	cmp	r3, #0
- 800c71e:	f000 8150 	beq.w	800c9c2 <tcp_output+0x3ce>
-      return tcp_send_empty_ack(pcb);
- 800c722:	6878      	ldr	r0, [r7, #4]
- 800c724:	f000 fd78 	bl	800d218 <tcp_send_empty_ack>
- 800c728:	4603      	mov	r3, r0
- 800c72a:	e155      	b.n	800c9d8 <tcp_output+0x3e4>
-    }
-    goto output_done;
-  }
-  /* Stop persist timer, above conditions are not active */
-  pcb->persist_backoff = 0;
- 800c72c:	687b      	ldr	r3, [r7, #4]
- 800c72e:	2200      	movs	r2, #0
- 800c730:	f883 2099 	strb.w	r2, [r3, #153]	; 0x99
-
-  /* useg should point to last segment on unacked queue */
-  useg = pcb->unacked;
- 800c734:	687b      	ldr	r3, [r7, #4]
- 800c736:	6f1b      	ldr	r3, [r3, #112]	; 0x70
- 800c738:	623b      	str	r3, [r7, #32]
-  if (useg != NULL) {
- 800c73a:	6a3b      	ldr	r3, [r7, #32]
- 800c73c:	2b00      	cmp	r3, #0
- 800c73e:	f000 811f 	beq.w	800c980 <tcp_output+0x38c>
-    for (; useg->next != NULL; useg = useg->next);
- 800c742:	e002      	b.n	800c74a <tcp_output+0x156>
- 800c744:	6a3b      	ldr	r3, [r7, #32]
- 800c746:	681b      	ldr	r3, [r3, #0]
- 800c748:	623b      	str	r3, [r7, #32]
- 800c74a:	6a3b      	ldr	r3, [r7, #32]
- 800c74c:	681b      	ldr	r3, [r3, #0]
- 800c74e:	2b00      	cmp	r3, #0
- 800c750:	d1f8      	bne.n	800c744 <tcp_output+0x150>
-  }
-  /* data available and window allows it to be sent? */
-  while (seg != NULL &&
- 800c752:	e115      	b.n	800c980 <tcp_output+0x38c>
-         lwip_ntohl(seg->tcphdr->seqno) - pcb->lastack + seg->len <= wnd) {
-    LWIP_ASSERT("RST not expected here!",
- 800c754:	6a7b      	ldr	r3, [r7, #36]	; 0x24
- 800c756:	691b      	ldr	r3, [r3, #16]
- 800c758:	899b      	ldrh	r3, [r3, #12]
- 800c75a:	b29b      	uxth	r3, r3
- 800c75c:	4618      	mov	r0, r3
- 800c75e:	f7f8 fef5 	bl	800554c <lwip_htons>
- 800c762:	4603      	mov	r3, r0
- 800c764:	b2db      	uxtb	r3, r3
- 800c766:	f003 0304 	and.w	r3, r3, #4
- 800c76a:	2b00      	cmp	r3, #0
- 800c76c:	d006      	beq.n	800c77c <tcp_output+0x188>
- 800c76e:	4b2f      	ldr	r3, [pc, #188]	; (800c82c <tcp_output+0x238>)
- 800c770:	f240 5236 	movw	r2, #1334	; 0x536
- 800c774:	4932      	ldr	r1, [pc, #200]	; (800c840 <tcp_output+0x24c>)
- 800c776:	482f      	ldr	r0, [pc, #188]	; (800c834 <tcp_output+0x240>)
- 800c778:	f004 fa26 	bl	8010bc8 <iprintf>
-     * - if tcp_write had a memory error before (prevent delayed ACK timeout) or
-     * - if FIN was already enqueued for this PCB (SYN is always alone in a segment -
-     *   either seg->next != NULL or pcb->unacked == NULL;
-     *   RST is no sent using tcp_write/tcp_output.
-     */
-    if ((tcp_do_output_nagle(pcb) == 0) &&
- 800c77c:	687b      	ldr	r3, [r7, #4]
- 800c77e:	6f1b      	ldr	r3, [r3, #112]	; 0x70
- 800c780:	2b00      	cmp	r3, #0
- 800c782:	d01f      	beq.n	800c7c4 <tcp_output+0x1d0>
- 800c784:	687b      	ldr	r3, [r7, #4]
- 800c786:	8b5b      	ldrh	r3, [r3, #26]
- 800c788:	f003 0344 	and.w	r3, r3, #68	; 0x44
- 800c78c:	2b00      	cmp	r3, #0
- 800c78e:	d119      	bne.n	800c7c4 <tcp_output+0x1d0>
- 800c790:	687b      	ldr	r3, [r7, #4]
- 800c792:	6edb      	ldr	r3, [r3, #108]	; 0x6c
- 800c794:	2b00      	cmp	r3, #0
- 800c796:	d00b      	beq.n	800c7b0 <tcp_output+0x1bc>
- 800c798:	687b      	ldr	r3, [r7, #4]
- 800c79a:	6edb      	ldr	r3, [r3, #108]	; 0x6c
- 800c79c:	681b      	ldr	r3, [r3, #0]
- 800c79e:	2b00      	cmp	r3, #0
- 800c7a0:	d110      	bne.n	800c7c4 <tcp_output+0x1d0>
- 800c7a2:	687b      	ldr	r3, [r7, #4]
- 800c7a4:	6edb      	ldr	r3, [r3, #108]	; 0x6c
- 800c7a6:	891a      	ldrh	r2, [r3, #8]
- 800c7a8:	687b      	ldr	r3, [r7, #4]
- 800c7aa:	8e5b      	ldrh	r3, [r3, #50]	; 0x32
- 800c7ac:	429a      	cmp	r2, r3
- 800c7ae:	d209      	bcs.n	800c7c4 <tcp_output+0x1d0>
- 800c7b0:	687b      	ldr	r3, [r7, #4]
- 800c7b2:	f8b3 3064 	ldrh.w	r3, [r3, #100]	; 0x64
- 800c7b6:	2b00      	cmp	r3, #0
- 800c7b8:	d004      	beq.n	800c7c4 <tcp_output+0x1d0>
- 800c7ba:	687b      	ldr	r3, [r7, #4]
- 800c7bc:	f8b3 3066 	ldrh.w	r3, [r3, #102]	; 0x66
- 800c7c0:	2b08      	cmp	r3, #8
- 800c7c2:	d901      	bls.n	800c7c8 <tcp_output+0x1d4>
- 800c7c4:	2301      	movs	r3, #1
- 800c7c6:	e000      	b.n	800c7ca <tcp_output+0x1d6>
- 800c7c8:	2300      	movs	r3, #0
- 800c7ca:	2b00      	cmp	r3, #0
- 800c7cc:	d106      	bne.n	800c7dc <tcp_output+0x1e8>
-        ((pcb->flags & (TF_NAGLEMEMERR | TF_FIN)) == 0)) {
- 800c7ce:	687b      	ldr	r3, [r7, #4]
- 800c7d0:	8b5b      	ldrh	r3, [r3, #26]
- 800c7d2:	f003 03a0 	and.w	r3, r3, #160	; 0xa0
-    if ((tcp_do_output_nagle(pcb) == 0) &&
- 800c7d6:	2b00      	cmp	r3, #0
- 800c7d8:	f000 80e7 	beq.w	800c9aa <tcp_output+0x3b6>
-                                 pcb->lastack,
-                                 lwip_ntohl(seg->tcphdr->seqno), pcb->lastack, i));
-    ++i;
-#endif /* TCP_CWND_DEBUG */
-
-    if (pcb->state != SYN_SENT) {
- 800c7dc:	687b      	ldr	r3, [r7, #4]
- 800c7de:	7d1b      	ldrb	r3, [r3, #20]
- 800c7e0:	2b02      	cmp	r3, #2
- 800c7e2:	d00d      	beq.n	800c800 <tcp_output+0x20c>
-      TCPH_SET_FLAG(seg->tcphdr, TCP_ACK);
- 800c7e4:	6a7b      	ldr	r3, [r7, #36]	; 0x24
- 800c7e6:	691b      	ldr	r3, [r3, #16]
- 800c7e8:	899b      	ldrh	r3, [r3, #12]
- 800c7ea:	b29c      	uxth	r4, r3
- 800c7ec:	2010      	movs	r0, #16
- 800c7ee:	f7f8 fead 	bl	800554c <lwip_htons>
- 800c7f2:	4603      	mov	r3, r0
- 800c7f4:	461a      	mov	r2, r3
- 800c7f6:	6a7b      	ldr	r3, [r7, #36]	; 0x24
- 800c7f8:	691b      	ldr	r3, [r3, #16]
- 800c7fa:	4322      	orrs	r2, r4
- 800c7fc:	b292      	uxth	r2, r2
- 800c7fe:	819a      	strh	r2, [r3, #12]
-    }
-
-    err = tcp_output_segment(seg, pcb, netif);
- 800c800:	697a      	ldr	r2, [r7, #20]
- 800c802:	6879      	ldr	r1, [r7, #4]
- 800c804:	6a78      	ldr	r0, [r7, #36]	; 0x24
- 800c806:	f000 f90b 	bl	800ca20 <tcp_output_segment>
- 800c80a:	4603      	mov	r3, r0
- 800c80c:	73fb      	strb	r3, [r7, #15]
-    if (err != ERR_OK) {
- 800c80e:	f997 300f 	ldrsb.w	r3, [r7, #15]
- 800c812:	2b00      	cmp	r3, #0
- 800c814:	d016      	beq.n	800c844 <tcp_output+0x250>
-      /* segment could not be sent, for whatever reason */
-      tcp_set_flags(pcb, TF_NAGLEMEMERR);
- 800c816:	687b      	ldr	r3, [r7, #4]
- 800c818:	8b5b      	ldrh	r3, [r3, #26]
- 800c81a:	f043 0380 	orr.w	r3, r3, #128	; 0x80
- 800c81e:	b29a      	uxth	r2, r3
- 800c820:	687b      	ldr	r3, [r7, #4]
- 800c822:	835a      	strh	r2, [r3, #26]
-      return err;
- 800c824:	f997 300f 	ldrsb.w	r3, [r7, #15]
- 800c828:	e0d6      	b.n	800c9d8 <tcp_output+0x3e4>
- 800c82a:	bf00      	nop
- 800c82c:	08013618 	.word	0x08013618
- 800c830:	08013bb8 	.word	0x08013bb8
- 800c834:	0801366c 	.word	0x0801366c
- 800c838:	08013bd0 	.word	0x08013bd0
- 800c83c:	24007bbc 	.word	0x24007bbc
- 800c840:	08013bf8 	.word	0x08013bf8
-    }
-#if TCP_OVERSIZE_DBGCHECK
-    seg->oversize_left = 0;
- 800c844:	6a7b      	ldr	r3, [r7, #36]	; 0x24
- 800c846:	2200      	movs	r2, #0
- 800c848:	815a      	strh	r2, [r3, #10]
-#endif /* TCP_OVERSIZE_DBGCHECK */
-    pcb->unsent = seg->next;
- 800c84a:	6a7b      	ldr	r3, [r7, #36]	; 0x24
- 800c84c:	681a      	ldr	r2, [r3, #0]
- 800c84e:	687b      	ldr	r3, [r7, #4]
- 800c850:	66da      	str	r2, [r3, #108]	; 0x6c
-    if (pcb->state != SYN_SENT) {
- 800c852:	687b      	ldr	r3, [r7, #4]
- 800c854:	7d1b      	ldrb	r3, [r3, #20]
- 800c856:	2b02      	cmp	r3, #2
- 800c858:	d006      	beq.n	800c868 <tcp_output+0x274>
-      tcp_clear_flags(pcb, TF_ACK_DELAY | TF_ACK_NOW);
- 800c85a:	687b      	ldr	r3, [r7, #4]
- 800c85c:	8b5b      	ldrh	r3, [r3, #26]
- 800c85e:	f023 0303 	bic.w	r3, r3, #3
- 800c862:	b29a      	uxth	r2, r3
- 800c864:	687b      	ldr	r3, [r7, #4]
- 800c866:	835a      	strh	r2, [r3, #26]
-    }
-    snd_nxt = lwip_ntohl(seg->tcphdr->seqno) + TCP_TCPLEN(seg);
- 800c868:	6a7b      	ldr	r3, [r7, #36]	; 0x24
- 800c86a:	691b      	ldr	r3, [r3, #16]
- 800c86c:	685b      	ldr	r3, [r3, #4]
- 800c86e:	4618      	mov	r0, r3
- 800c870:	f7f8 fe81 	bl	8005576 <lwip_htonl>
- 800c874:	4604      	mov	r4, r0
- 800c876:	6a7b      	ldr	r3, [r7, #36]	; 0x24
- 800c878:	891b      	ldrh	r3, [r3, #8]
- 800c87a:	461d      	mov	r5, r3
- 800c87c:	6a7b      	ldr	r3, [r7, #36]	; 0x24
- 800c87e:	691b      	ldr	r3, [r3, #16]
- 800c880:	899b      	ldrh	r3, [r3, #12]
- 800c882:	b29b      	uxth	r3, r3
- 800c884:	4618      	mov	r0, r3
- 800c886:	f7f8 fe61 	bl	800554c <lwip_htons>
- 800c88a:	4603      	mov	r3, r0
- 800c88c:	b2db      	uxtb	r3, r3
- 800c88e:	f003 0303 	and.w	r3, r3, #3
- 800c892:	2b00      	cmp	r3, #0
- 800c894:	d001      	beq.n	800c89a <tcp_output+0x2a6>
- 800c896:	2301      	movs	r3, #1
- 800c898:	e000      	b.n	800c89c <tcp_output+0x2a8>
- 800c89a:	2300      	movs	r3, #0
- 800c89c:	442b      	add	r3, r5
- 800c89e:	4423      	add	r3, r4
- 800c8a0:	60bb      	str	r3, [r7, #8]
-    if (TCP_SEQ_LT(pcb->snd_nxt, snd_nxt)) {
- 800c8a2:	687b      	ldr	r3, [r7, #4]
- 800c8a4:	6d1a      	ldr	r2, [r3, #80]	; 0x50
- 800c8a6:	68bb      	ldr	r3, [r7, #8]
- 800c8a8:	1ad3      	subs	r3, r2, r3
- 800c8aa:	2b00      	cmp	r3, #0
- 800c8ac:	da02      	bge.n	800c8b4 <tcp_output+0x2c0>
-      pcb->snd_nxt = snd_nxt;
- 800c8ae:	687b      	ldr	r3, [r7, #4]
- 800c8b0:	68ba      	ldr	r2, [r7, #8]
- 800c8b2:	651a      	str	r2, [r3, #80]	; 0x50
-    }
-    /* put segment on unacknowledged list if length > 0 */
-    if (TCP_TCPLEN(seg) > 0) {
- 800c8b4:	6a7b      	ldr	r3, [r7, #36]	; 0x24
- 800c8b6:	891b      	ldrh	r3, [r3, #8]
- 800c8b8:	461c      	mov	r4, r3
- 800c8ba:	6a7b      	ldr	r3, [r7, #36]	; 0x24
- 800c8bc:	691b      	ldr	r3, [r3, #16]
- 800c8be:	899b      	ldrh	r3, [r3, #12]
- 800c8c0:	b29b      	uxth	r3, r3
- 800c8c2:	4618      	mov	r0, r3
- 800c8c4:	f7f8 fe42 	bl	800554c <lwip_htons>
- 800c8c8:	4603      	mov	r3, r0
- 800c8ca:	b2db      	uxtb	r3, r3
- 800c8cc:	f003 0303 	and.w	r3, r3, #3
- 800c8d0:	2b00      	cmp	r3, #0
- 800c8d2:	d001      	beq.n	800c8d8 <tcp_output+0x2e4>
- 800c8d4:	2301      	movs	r3, #1
- 800c8d6:	e000      	b.n	800c8da <tcp_output+0x2e6>
- 800c8d8:	2300      	movs	r3, #0
- 800c8da:	4423      	add	r3, r4
- 800c8dc:	2b00      	cmp	r3, #0
- 800c8de:	d049      	beq.n	800c974 <tcp_output+0x380>
-      seg->next = NULL;
- 800c8e0:	6a7b      	ldr	r3, [r7, #36]	; 0x24
- 800c8e2:	2200      	movs	r2, #0
- 800c8e4:	601a      	str	r2, [r3, #0]
-      /* unacked list is empty? */
-      if (pcb->unacked == NULL) {
- 800c8e6:	687b      	ldr	r3, [r7, #4]
- 800c8e8:	6f1b      	ldr	r3, [r3, #112]	; 0x70
- 800c8ea:	2b00      	cmp	r3, #0
- 800c8ec:	d105      	bne.n	800c8fa <tcp_output+0x306>
-        pcb->unacked = seg;
- 800c8ee:	687b      	ldr	r3, [r7, #4]
- 800c8f0:	6a7a      	ldr	r2, [r7, #36]	; 0x24
- 800c8f2:	671a      	str	r2, [r3, #112]	; 0x70
-        useg = seg;
- 800c8f4:	6a7b      	ldr	r3, [r7, #36]	; 0x24
- 800c8f6:	623b      	str	r3, [r7, #32]
- 800c8f8:	e03f      	b.n	800c97a <tcp_output+0x386>
-        /* unacked list is not empty? */
-      } else {
-        /* In the case of fast retransmit, the packet should not go to the tail
-         * of the unacked queue, but rather somewhere before it. We need to check for
-         * this case. -STJ Jul 27, 2004 */
-        if (TCP_SEQ_LT(lwip_ntohl(seg->tcphdr->seqno), lwip_ntohl(useg->tcphdr->seqno))) {
- 800c8fa:	6a7b      	ldr	r3, [r7, #36]	; 0x24
- 800c8fc:	691b      	ldr	r3, [r3, #16]
- 800c8fe:	685b      	ldr	r3, [r3, #4]
- 800c900:	4618      	mov	r0, r3
- 800c902:	f7f8 fe38 	bl	8005576 <lwip_htonl>
- 800c906:	4604      	mov	r4, r0
- 800c908:	6a3b      	ldr	r3, [r7, #32]
- 800c90a:	691b      	ldr	r3, [r3, #16]
- 800c90c:	685b      	ldr	r3, [r3, #4]
- 800c90e:	4618      	mov	r0, r3
- 800c910:	f7f8 fe31 	bl	8005576 <lwip_htonl>
- 800c914:	4603      	mov	r3, r0
- 800c916:	1ae3      	subs	r3, r4, r3
- 800c918:	2b00      	cmp	r3, #0
- 800c91a:	da24      	bge.n	800c966 <tcp_output+0x372>
-          /* add segment to before tail of unacked list, keeping the list sorted */
-          struct tcp_seg **cur_seg = &(pcb->unacked);
- 800c91c:	687b      	ldr	r3, [r7, #4]
- 800c91e:	3370      	adds	r3, #112	; 0x70
- 800c920:	61fb      	str	r3, [r7, #28]
-          while (*cur_seg &&
- 800c922:	e002      	b.n	800c92a <tcp_output+0x336>
-                 TCP_SEQ_LT(lwip_ntohl((*cur_seg)->tcphdr->seqno), lwip_ntohl(seg->tcphdr->seqno))) {
-            cur_seg = &((*cur_seg)->next );
- 800c924:	69fb      	ldr	r3, [r7, #28]
- 800c926:	681b      	ldr	r3, [r3, #0]
- 800c928:	61fb      	str	r3, [r7, #28]
-          while (*cur_seg &&
- 800c92a:	69fb      	ldr	r3, [r7, #28]
- 800c92c:	681b      	ldr	r3, [r3, #0]
- 800c92e:	2b00      	cmp	r3, #0
- 800c930:	d011      	beq.n	800c956 <tcp_output+0x362>
-                 TCP_SEQ_LT(lwip_ntohl((*cur_seg)->tcphdr->seqno), lwip_ntohl(seg->tcphdr->seqno))) {
- 800c932:	69fb      	ldr	r3, [r7, #28]
- 800c934:	681b      	ldr	r3, [r3, #0]
- 800c936:	691b      	ldr	r3, [r3, #16]
- 800c938:	685b      	ldr	r3, [r3, #4]
- 800c93a:	4618      	mov	r0, r3
- 800c93c:	f7f8 fe1b 	bl	8005576 <lwip_htonl>
- 800c940:	4604      	mov	r4, r0
- 800c942:	6a7b      	ldr	r3, [r7, #36]	; 0x24
- 800c944:	691b      	ldr	r3, [r3, #16]
- 800c946:	685b      	ldr	r3, [r3, #4]
- 800c948:	4618      	mov	r0, r3
- 800c94a:	f7f8 fe14 	bl	8005576 <lwip_htonl>
- 800c94e:	4603      	mov	r3, r0
- 800c950:	1ae3      	subs	r3, r4, r3
-          while (*cur_seg &&
- 800c952:	2b00      	cmp	r3, #0
- 800c954:	dbe6      	blt.n	800c924 <tcp_output+0x330>
-          }
-          seg->next = (*cur_seg);
- 800c956:	69fb      	ldr	r3, [r7, #28]
- 800c958:	681a      	ldr	r2, [r3, #0]
- 800c95a:	6a7b      	ldr	r3, [r7, #36]	; 0x24
- 800c95c:	601a      	str	r2, [r3, #0]
-          (*cur_seg) = seg;
- 800c95e:	69fb      	ldr	r3, [r7, #28]
- 800c960:	6a7a      	ldr	r2, [r7, #36]	; 0x24
- 800c962:	601a      	str	r2, [r3, #0]
- 800c964:	e009      	b.n	800c97a <tcp_output+0x386>
-        } else {
-          /* add segment to tail of unacked list */
-          useg->next = seg;
- 800c966:	6a3b      	ldr	r3, [r7, #32]
- 800c968:	6a7a      	ldr	r2, [r7, #36]	; 0x24
- 800c96a:	601a      	str	r2, [r3, #0]
-          useg = useg->next;
- 800c96c:	6a3b      	ldr	r3, [r7, #32]
- 800c96e:	681b      	ldr	r3, [r3, #0]
- 800c970:	623b      	str	r3, [r7, #32]
- 800c972:	e002      	b.n	800c97a <tcp_output+0x386>
-        }
-      }
-      /* do not queue empty segments on the unacked list */
-    } else {
-      tcp_seg_free(seg);
- 800c974:	6a78      	ldr	r0, [r7, #36]	; 0x24
- 800c976:	f7fb fefe 	bl	8008776 <tcp_seg_free>
-    }
-    seg = pcb->unsent;
- 800c97a:	687b      	ldr	r3, [r7, #4]
- 800c97c:	6edb      	ldr	r3, [r3, #108]	; 0x6c
- 800c97e:	627b      	str	r3, [r7, #36]	; 0x24
-  while (seg != NULL &&
- 800c980:	6a7b      	ldr	r3, [r7, #36]	; 0x24
- 800c982:	2b00      	cmp	r3, #0
- 800c984:	d012      	beq.n	800c9ac <tcp_output+0x3b8>
-         lwip_ntohl(seg->tcphdr->seqno) - pcb->lastack + seg->len <= wnd) {
- 800c986:	6a7b      	ldr	r3, [r7, #36]	; 0x24
- 800c988:	691b      	ldr	r3, [r3, #16]
- 800c98a:	685b      	ldr	r3, [r3, #4]
- 800c98c:	4618      	mov	r0, r3
- 800c98e:	f7f8 fdf2 	bl	8005576 <lwip_htonl>
- 800c992:	4602      	mov	r2, r0
- 800c994:	687b      	ldr	r3, [r7, #4]
- 800c996:	6c5b      	ldr	r3, [r3, #68]	; 0x44
- 800c998:	1ad3      	subs	r3, r2, r3
- 800c99a:	6a7a      	ldr	r2, [r7, #36]	; 0x24
- 800c99c:	8912      	ldrh	r2, [r2, #8]
- 800c99e:	4413      	add	r3, r2
-  while (seg != NULL &&
- 800c9a0:	69ba      	ldr	r2, [r7, #24]
- 800c9a2:	429a      	cmp	r2, r3
- 800c9a4:	f4bf aed6 	bcs.w	800c754 <tcp_output+0x160>
- 800c9a8:	e000      	b.n	800c9ac <tcp_output+0x3b8>
-      break;
- 800c9aa:	bf00      	nop
-  }
-#if TCP_OVERSIZE
-  if (pcb->unsent == NULL) {
- 800c9ac:	687b      	ldr	r3, [r7, #4]
- 800c9ae:	6edb      	ldr	r3, [r3, #108]	; 0x6c
- 800c9b0:	2b00      	cmp	r3, #0
- 800c9b2:	d108      	bne.n	800c9c6 <tcp_output+0x3d2>
-    /* last unsent has been removed, reset unsent_oversize */
-    pcb->unsent_oversize = 0;
- 800c9b4:	687b      	ldr	r3, [r7, #4]
- 800c9b6:	2200      	movs	r2, #0
- 800c9b8:	f8a3 2068 	strh.w	r2, [r3, #104]	; 0x68
- 800c9bc:	e004      	b.n	800c9c8 <tcp_output+0x3d4>
-    goto output_done;
- 800c9be:	bf00      	nop
- 800c9c0:	e002      	b.n	800c9c8 <tcp_output+0x3d4>
-    goto output_done;
- 800c9c2:	bf00      	nop
- 800c9c4:	e000      	b.n	800c9c8 <tcp_output+0x3d4>
-  }
-#endif /* TCP_OVERSIZE */
-
-output_done:
- 800c9c6:	bf00      	nop
-  tcp_clear_flags(pcb, TF_NAGLEMEMERR);
- 800c9c8:	687b      	ldr	r3, [r7, #4]
- 800c9ca:	8b5b      	ldrh	r3, [r3, #26]
- 800c9cc:	f023 0380 	bic.w	r3, r3, #128	; 0x80
- 800c9d0:	b29a      	uxth	r2, r3
- 800c9d2:	687b      	ldr	r3, [r7, #4]
- 800c9d4:	835a      	strh	r2, [r3, #26]
-  return ERR_OK;
- 800c9d6:	2300      	movs	r3, #0
-}
- 800c9d8:	4618      	mov	r0, r3
- 800c9da:	3728      	adds	r7, #40	; 0x28
- 800c9dc:	46bd      	mov	sp, r7
- 800c9de:	bdb0      	pop	{r4, r5, r7, pc}
-
-0800c9e0 <tcp_output_segment_busy>:
- * @arg seg the tcp segment to check
- * @return 1 if ref != 1, 0 if ref == 1
- */
-static int
-tcp_output_segment_busy(const struct tcp_seg *seg)
-{
- 800c9e0:	b580      	push	{r7, lr}
- 800c9e2:	b082      	sub	sp, #8
- 800c9e4:	af00      	add	r7, sp, #0
- 800c9e6:	6078      	str	r0, [r7, #4]
-  LWIP_ASSERT("tcp_output_segment_busy: invalid seg", seg != NULL);
- 800c9e8:	687b      	ldr	r3, [r7, #4]
- 800c9ea:	2b00      	cmp	r3, #0
- 800c9ec:	d106      	bne.n	800c9fc <tcp_output_segment_busy+0x1c>
- 800c9ee:	4b09      	ldr	r3, [pc, #36]	; (800ca14 <tcp_output_segment_busy+0x34>)
- 800c9f0:	f240 529a 	movw	r2, #1434	; 0x59a
- 800c9f4:	4908      	ldr	r1, [pc, #32]	; (800ca18 <tcp_output_segment_busy+0x38>)
- 800c9f6:	4809      	ldr	r0, [pc, #36]	; (800ca1c <tcp_output_segment_busy+0x3c>)
- 800c9f8:	f004 f8e6 	bl	8010bc8 <iprintf>
-
-  /* We only need to check the first pbuf here:
-     If a pbuf is queued for transmission, a driver calls pbuf_ref(),
-     which only changes the ref count of the first pbuf */
-  if (seg->p->ref != 1) {
- 800c9fc:	687b      	ldr	r3, [r7, #4]
- 800c9fe:	685b      	ldr	r3, [r3, #4]
- 800ca00:	7b9b      	ldrb	r3, [r3, #14]
- 800ca02:	2b01      	cmp	r3, #1
- 800ca04:	d001      	beq.n	800ca0a <tcp_output_segment_busy+0x2a>
-    /* other reference found */
-    return 1;
- 800ca06:	2301      	movs	r3, #1
- 800ca08:	e000      	b.n	800ca0c <tcp_output_segment_busy+0x2c>
-  }
-  /* no other references found */
-  return 0;
- 800ca0a:	2300      	movs	r3, #0
-}
- 800ca0c:	4618      	mov	r0, r3
- 800ca0e:	3708      	adds	r7, #8
- 800ca10:	46bd      	mov	sp, r7
- 800ca12:	bd80      	pop	{r7, pc}
- 800ca14:	08013618 	.word	0x08013618
- 800ca18:	08013c10 	.word	0x08013c10
- 800ca1c:	0801366c 	.word	0x0801366c
-
-0800ca20 <tcp_output_segment>:
- * @param pcb the tcp_pcb for the TCP connection used to send the segment
- * @param netif the netif used to send the segment
- */
-static err_t
-tcp_output_segment(struct tcp_seg *seg, struct tcp_pcb *pcb, struct netif *netif)
-{
- 800ca20:	b5b0      	push	{r4, r5, r7, lr}
- 800ca22:	b08c      	sub	sp, #48	; 0x30
- 800ca24:	af04      	add	r7, sp, #16
- 800ca26:	60f8      	str	r0, [r7, #12]
- 800ca28:	60b9      	str	r1, [r7, #8]
- 800ca2a:	607a      	str	r2, [r7, #4]
-  u32_t *opts;
-#if TCP_CHECKSUM_ON_COPY
-  int seg_chksum_was_swapped = 0;
-#endif
-
-  LWIP_ASSERT("tcp_output_segment: invalid seg", seg != NULL);
- 800ca2c:	68fb      	ldr	r3, [r7, #12]
- 800ca2e:	2b00      	cmp	r3, #0
- 800ca30:	d106      	bne.n	800ca40 <tcp_output_segment+0x20>
- 800ca32:	4b64      	ldr	r3, [pc, #400]	; (800cbc4 <tcp_output_segment+0x1a4>)
- 800ca34:	f44f 62b7 	mov.w	r2, #1464	; 0x5b8
- 800ca38:	4963      	ldr	r1, [pc, #396]	; (800cbc8 <tcp_output_segment+0x1a8>)
- 800ca3a:	4864      	ldr	r0, [pc, #400]	; (800cbcc <tcp_output_segment+0x1ac>)
- 800ca3c:	f004 f8c4 	bl	8010bc8 <iprintf>
-  LWIP_ASSERT("tcp_output_segment: invalid pcb", pcb != NULL);
- 800ca40:	68bb      	ldr	r3, [r7, #8]
- 800ca42:	2b00      	cmp	r3, #0
- 800ca44:	d106      	bne.n	800ca54 <tcp_output_segment+0x34>
- 800ca46:	4b5f      	ldr	r3, [pc, #380]	; (800cbc4 <tcp_output_segment+0x1a4>)
- 800ca48:	f240 52b9 	movw	r2, #1465	; 0x5b9
- 800ca4c:	4960      	ldr	r1, [pc, #384]	; (800cbd0 <tcp_output_segment+0x1b0>)
- 800ca4e:	485f      	ldr	r0, [pc, #380]	; (800cbcc <tcp_output_segment+0x1ac>)
- 800ca50:	f004 f8ba 	bl	8010bc8 <iprintf>
-  LWIP_ASSERT("tcp_output_segment: invalid netif", netif != NULL);
- 800ca54:	687b      	ldr	r3, [r7, #4]
- 800ca56:	2b00      	cmp	r3, #0
- 800ca58:	d106      	bne.n	800ca68 <tcp_output_segment+0x48>
- 800ca5a:	4b5a      	ldr	r3, [pc, #360]	; (800cbc4 <tcp_output_segment+0x1a4>)
- 800ca5c:	f240 52ba 	movw	r2, #1466	; 0x5ba
- 800ca60:	495c      	ldr	r1, [pc, #368]	; (800cbd4 <tcp_output_segment+0x1b4>)
- 800ca62:	485a      	ldr	r0, [pc, #360]	; (800cbcc <tcp_output_segment+0x1ac>)
- 800ca64:	f004 f8b0 	bl	8010bc8 <iprintf>
-
-  if (tcp_output_segment_busy(seg)) {
- 800ca68:	68f8      	ldr	r0, [r7, #12]
- 800ca6a:	f7ff ffb9 	bl	800c9e0 <tcp_output_segment_busy>
- 800ca6e:	4603      	mov	r3, r0
- 800ca70:	2b00      	cmp	r3, #0
- 800ca72:	d001      	beq.n	800ca78 <tcp_output_segment+0x58>
-    /* This should not happen: rexmit functions should have checked this.
-       However, since this function modifies p->len, we must not continue in this case. */
-    LWIP_DEBUGF(TCP_RTO_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("tcp_output_segment: segment busy\n"));
-    return ERR_OK;
- 800ca74:	2300      	movs	r3, #0
- 800ca76:	e0a1      	b.n	800cbbc <tcp_output_segment+0x19c>
-  }
-
-  /* The TCP header has already been constructed, but the ackno and
-   wnd fields remain. */
-  seg->tcphdr->ackno = lwip_htonl(pcb->rcv_nxt);
- 800ca78:	68bb      	ldr	r3, [r7, #8]
- 800ca7a:	6a5a      	ldr	r2, [r3, #36]	; 0x24
- 800ca7c:	68fb      	ldr	r3, [r7, #12]
- 800ca7e:	691c      	ldr	r4, [r3, #16]
- 800ca80:	4610      	mov	r0, r2
- 800ca82:	f7f8 fd78 	bl	8005576 <lwip_htonl>
- 800ca86:	4603      	mov	r3, r0
- 800ca88:	60a3      	str	r3, [r4, #8]
-       the window scale option) is never scaled. */
-    seg->tcphdr->wnd = lwip_htons(TCPWND_MIN16(pcb->rcv_ann_wnd));
-  } else
-#endif /* LWIP_WND_SCALE */
-  {
-    seg->tcphdr->wnd = lwip_htons(TCPWND_MIN16(RCV_WND_SCALE(pcb, pcb->rcv_ann_wnd)));
- 800ca8a:	68bb      	ldr	r3, [r7, #8]
- 800ca8c:	8d5a      	ldrh	r2, [r3, #42]	; 0x2a
- 800ca8e:	68fb      	ldr	r3, [r7, #12]
- 800ca90:	691c      	ldr	r4, [r3, #16]
- 800ca92:	4610      	mov	r0, r2
- 800ca94:	f7f8 fd5a 	bl	800554c <lwip_htons>
- 800ca98:	4603      	mov	r3, r0
- 800ca9a:	81e3      	strh	r3, [r4, #14]
-  }
-
-  pcb->rcv_ann_right_edge = pcb->rcv_nxt + pcb->rcv_ann_wnd;
- 800ca9c:	68bb      	ldr	r3, [r7, #8]
- 800ca9e:	6a5b      	ldr	r3, [r3, #36]	; 0x24
- 800caa0:	68ba      	ldr	r2, [r7, #8]
- 800caa2:	8d52      	ldrh	r2, [r2, #42]	; 0x2a
- 800caa4:	441a      	add	r2, r3
- 800caa6:	68bb      	ldr	r3, [r7, #8]
- 800caa8:	62da      	str	r2, [r3, #44]	; 0x2c
-
-  /* Add any requested options.  NB MSS option is only set on SYN
-     packets, so ignore it here */
-  /* cast through void* to get rid of alignment warnings */
-  opts = (u32_t *)(void *)(seg->tcphdr + 1);
- 800caaa:	68fb      	ldr	r3, [r7, #12]
- 800caac:	691b      	ldr	r3, [r3, #16]
- 800caae:	3314      	adds	r3, #20
- 800cab0:	61fb      	str	r3, [r7, #28]
-  if (seg->flags & TF_SEG_OPTS_MSS) {
- 800cab2:	68fb      	ldr	r3, [r7, #12]
- 800cab4:	7b1b      	ldrb	r3, [r3, #12]
- 800cab6:	f003 0301 	and.w	r3, r3, #1
- 800caba:	2b00      	cmp	r3, #0
- 800cabc:	d015      	beq.n	800caea <tcp_output_segment+0xca>
-    u16_t mss;
-#if TCP_CALCULATE_EFF_SEND_MSS
-    mss = tcp_eff_send_mss_netif(TCP_MSS, netif, &pcb->remote_ip);
- 800cabe:	68bb      	ldr	r3, [r7, #8]
- 800cac0:	3304      	adds	r3, #4
- 800cac2:	461a      	mov	r2, r3
- 800cac4:	6879      	ldr	r1, [r7, #4]
- 800cac6:	f44f 7006 	mov.w	r0, #536	; 0x218
- 800caca:	f7fc f9cb 	bl	8008e64 <tcp_eff_send_mss_netif>
- 800cace:	4603      	mov	r3, r0
- 800cad0:	837b      	strh	r3, [r7, #26]
-#else /* TCP_CALCULATE_EFF_SEND_MSS */
-    mss = TCP_MSS;
-#endif /* TCP_CALCULATE_EFF_SEND_MSS */
-    *opts = TCP_BUILD_MSS_OPTION(mss);
- 800cad2:	8b7b      	ldrh	r3, [r7, #26]
- 800cad4:	f043 7301 	orr.w	r3, r3, #33816576	; 0x2040000
- 800cad8:	4618      	mov	r0, r3
- 800cada:	f7f8 fd4c 	bl	8005576 <lwip_htonl>
- 800cade:	4602      	mov	r2, r0
- 800cae0:	69fb      	ldr	r3, [r7, #28]
- 800cae2:	601a      	str	r2, [r3, #0]
-    opts += 1;
- 800cae4:	69fb      	ldr	r3, [r7, #28]
- 800cae6:	3304      	adds	r3, #4
- 800cae8:	61fb      	str	r3, [r7, #28]
-  }
-#endif
-
-  /* Set retransmission timer running if it is not currently enabled
-     This must be set before checking the route. */
-  if (pcb->rtime < 0) {
- 800caea:	68bb      	ldr	r3, [r7, #8]
- 800caec:	f9b3 3030 	ldrsh.w	r3, [r3, #48]	; 0x30
- 800caf0:	2b00      	cmp	r3, #0
- 800caf2:	da02      	bge.n	800cafa <tcp_output_segment+0xda>
-    pcb->rtime = 0;
- 800caf4:	68bb      	ldr	r3, [r7, #8]
- 800caf6:	2200      	movs	r2, #0
- 800caf8:	861a      	strh	r2, [r3, #48]	; 0x30
-  }
-
-  if (pcb->rttest == 0) {
- 800cafa:	68bb      	ldr	r3, [r7, #8]
- 800cafc:	6b5b      	ldr	r3, [r3, #52]	; 0x34
- 800cafe:	2b00      	cmp	r3, #0
- 800cb00:	d10c      	bne.n	800cb1c <tcp_output_segment+0xfc>
-    pcb->rttest = tcp_ticks;
- 800cb02:	4b35      	ldr	r3, [pc, #212]	; (800cbd8 <tcp_output_segment+0x1b8>)
- 800cb04:	681a      	ldr	r2, [r3, #0]
- 800cb06:	68bb      	ldr	r3, [r7, #8]
- 800cb08:	635a      	str	r2, [r3, #52]	; 0x34
-    pcb->rtseq = lwip_ntohl(seg->tcphdr->seqno);
- 800cb0a:	68fb      	ldr	r3, [r7, #12]
- 800cb0c:	691b      	ldr	r3, [r3, #16]
- 800cb0e:	685b      	ldr	r3, [r3, #4]
- 800cb10:	4618      	mov	r0, r3
- 800cb12:	f7f8 fd30 	bl	8005576 <lwip_htonl>
- 800cb16:	4602      	mov	r2, r0
- 800cb18:	68bb      	ldr	r3, [r7, #8]
- 800cb1a:	639a      	str	r2, [r3, #56]	; 0x38
-  }
-  LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_output_segment: %"U32_F":%"U32_F"\n",
-                                 lwip_htonl(seg->tcphdr->seqno), lwip_htonl(seg->tcphdr->seqno) +
-                                 seg->len));
-
-  len = (u16_t)((u8_t *)seg->tcphdr - (u8_t *)seg->p->payload);
- 800cb1c:	68fb      	ldr	r3, [r7, #12]
- 800cb1e:	691a      	ldr	r2, [r3, #16]
- 800cb20:	68fb      	ldr	r3, [r7, #12]
- 800cb22:	685b      	ldr	r3, [r3, #4]
- 800cb24:	685b      	ldr	r3, [r3, #4]
- 800cb26:	1ad3      	subs	r3, r2, r3
- 800cb28:	833b      	strh	r3, [r7, #24]
-  if (len == 0) {
-    /** Exclude retransmitted segments from this count. */
-    MIB2_STATS_INC(mib2.tcpoutsegs);
-  }
-
-  seg->p->len -= len;
- 800cb2a:	68fb      	ldr	r3, [r7, #12]
- 800cb2c:	685b      	ldr	r3, [r3, #4]
- 800cb2e:	8959      	ldrh	r1, [r3, #10]
- 800cb30:	68fb      	ldr	r3, [r7, #12]
- 800cb32:	685b      	ldr	r3, [r3, #4]
- 800cb34:	8b3a      	ldrh	r2, [r7, #24]
- 800cb36:	1a8a      	subs	r2, r1, r2
- 800cb38:	b292      	uxth	r2, r2
- 800cb3a:	815a      	strh	r2, [r3, #10]
-  seg->p->tot_len -= len;
- 800cb3c:	68fb      	ldr	r3, [r7, #12]
- 800cb3e:	685b      	ldr	r3, [r3, #4]
- 800cb40:	8919      	ldrh	r1, [r3, #8]
- 800cb42:	68fb      	ldr	r3, [r7, #12]
- 800cb44:	685b      	ldr	r3, [r3, #4]
- 800cb46:	8b3a      	ldrh	r2, [r7, #24]
- 800cb48:	1a8a      	subs	r2, r1, r2
- 800cb4a:	b292      	uxth	r2, r2
- 800cb4c:	811a      	strh	r2, [r3, #8]
-
-  seg->p->payload = seg->tcphdr;
- 800cb4e:	68fb      	ldr	r3, [r7, #12]
- 800cb50:	685b      	ldr	r3, [r3, #4]
- 800cb52:	68fa      	ldr	r2, [r7, #12]
- 800cb54:	6912      	ldr	r2, [r2, #16]
- 800cb56:	605a      	str	r2, [r3, #4]
-
-  seg->tcphdr->chksum = 0;
- 800cb58:	68fb      	ldr	r3, [r7, #12]
- 800cb5a:	691b      	ldr	r3, [r3, #16]
- 800cb5c:	2200      	movs	r2, #0
- 800cb5e:	741a      	strb	r2, [r3, #16]
- 800cb60:	2200      	movs	r2, #0
- 800cb62:	745a      	strb	r2, [r3, #17]
-
-#ifdef LWIP_HOOK_TCP_OUT_ADD_TCPOPTS
-  opts = LWIP_HOOK_TCP_OUT_ADD_TCPOPTS(seg->p, seg->tcphdr, pcb, opts);
-#endif
-  LWIP_ASSERT("options not filled", (u8_t *)opts == ((u8_t *)(seg->tcphdr + 1)) + LWIP_TCP_OPT_LENGTH_SEGMENT(seg->flags, pcb));
- 800cb64:	68fb      	ldr	r3, [r7, #12]
- 800cb66:	691a      	ldr	r2, [r3, #16]
- 800cb68:	68fb      	ldr	r3, [r7, #12]
- 800cb6a:	7b1b      	ldrb	r3, [r3, #12]
- 800cb6c:	f003 0301 	and.w	r3, r3, #1
- 800cb70:	2b00      	cmp	r3, #0
- 800cb72:	d001      	beq.n	800cb78 <tcp_output_segment+0x158>
- 800cb74:	2318      	movs	r3, #24
- 800cb76:	e000      	b.n	800cb7a <tcp_output_segment+0x15a>
- 800cb78:	2314      	movs	r3, #20
- 800cb7a:	4413      	add	r3, r2
- 800cb7c:	69fa      	ldr	r2, [r7, #28]
- 800cb7e:	429a      	cmp	r2, r3
- 800cb80:	d006      	beq.n	800cb90 <tcp_output_segment+0x170>
- 800cb82:	4b10      	ldr	r3, [pc, #64]	; (800cbc4 <tcp_output_segment+0x1a4>)
- 800cb84:	f240 621c 	movw	r2, #1564	; 0x61c
- 800cb88:	4914      	ldr	r1, [pc, #80]	; (800cbdc <tcp_output_segment+0x1bc>)
- 800cb8a:	4810      	ldr	r0, [pc, #64]	; (800cbcc <tcp_output_segment+0x1ac>)
- 800cb8c:	f004 f81c 	bl	8010bc8 <iprintf>
-  }
-#endif /* CHECKSUM_GEN_TCP */
-  TCP_STATS_INC(tcp.xmit);
-
-  NETIF_SET_HINTS(netif, &(pcb->netif_hints));
-  err = ip_output_if(seg->p, &pcb->local_ip, &pcb->remote_ip, pcb->ttl,
- 800cb90:	68fb      	ldr	r3, [r7, #12]
- 800cb92:	6858      	ldr	r0, [r3, #4]
- 800cb94:	68b9      	ldr	r1, [r7, #8]
- 800cb96:	68bb      	ldr	r3, [r7, #8]
- 800cb98:	1d1c      	adds	r4, r3, #4
- 800cb9a:	68bb      	ldr	r3, [r7, #8]
- 800cb9c:	7add      	ldrb	r5, [r3, #11]
- 800cb9e:	68bb      	ldr	r3, [r7, #8]
- 800cba0:	7a9b      	ldrb	r3, [r3, #10]
- 800cba2:	687a      	ldr	r2, [r7, #4]
- 800cba4:	9202      	str	r2, [sp, #8]
- 800cba6:	2206      	movs	r2, #6
- 800cba8:	9201      	str	r2, [sp, #4]
- 800cbaa:	9300      	str	r3, [sp, #0]
- 800cbac:	462b      	mov	r3, r5
- 800cbae:	4622      	mov	r2, r4
- 800cbb0:	f002 fb28 	bl	800f204 <ip4_output_if>
- 800cbb4:	4603      	mov	r3, r0
- 800cbb6:	75fb      	strb	r3, [r7, #23]
-    seg->chksum = SWAP_BYTES_IN_WORD(seg->chksum);
-    seg->chksum_swapped = 1;
-  }
-#endif
-
-  return err;
- 800cbb8:	f997 3017 	ldrsb.w	r3, [r7, #23]
-}
- 800cbbc:	4618      	mov	r0, r3
- 800cbbe:	3720      	adds	r7, #32
- 800cbc0:	46bd      	mov	sp, r7
- 800cbc2:	bdb0      	pop	{r4, r5, r7, pc}
- 800cbc4:	08013618 	.word	0x08013618
- 800cbc8:	08013c38 	.word	0x08013c38
- 800cbcc:	0801366c 	.word	0x0801366c
- 800cbd0:	08013c58 	.word	0x08013c58
- 800cbd4:	08013c78 	.word	0x08013c78
- 800cbd8:	24007b6c 	.word	0x24007b6c
- 800cbdc:	08013c9c 	.word	0x08013c9c
-
-0800cbe0 <tcp_rexmit_rto_prepare>:
- *
- * @param pcb the tcp_pcb for which to re-enqueue all unacked segments
- */
-err_t
-tcp_rexmit_rto_prepare(struct tcp_pcb *pcb)
-{
- 800cbe0:	b5b0      	push	{r4, r5, r7, lr}
- 800cbe2:	b084      	sub	sp, #16
- 800cbe4:	af00      	add	r7, sp, #0
- 800cbe6:	6078      	str	r0, [r7, #4]
-  struct tcp_seg *seg;
-
-  LWIP_ASSERT("tcp_rexmit_rto_prepare: invalid pcb", pcb != NULL);
- 800cbe8:	687b      	ldr	r3, [r7, #4]
- 800cbea:	2b00      	cmp	r3, #0
- 800cbec:	d106      	bne.n	800cbfc <tcp_rexmit_rto_prepare+0x1c>
- 800cbee:	4b36      	ldr	r3, [pc, #216]	; (800ccc8 <tcp_rexmit_rto_prepare+0xe8>)
- 800cbf0:	f240 6263 	movw	r2, #1635	; 0x663
- 800cbf4:	4935      	ldr	r1, [pc, #212]	; (800cccc <tcp_rexmit_rto_prepare+0xec>)
- 800cbf6:	4836      	ldr	r0, [pc, #216]	; (800ccd0 <tcp_rexmit_rto_prepare+0xf0>)
- 800cbf8:	f003 ffe6 	bl	8010bc8 <iprintf>
-
-  if (pcb->unacked == NULL) {
- 800cbfc:	687b      	ldr	r3, [r7, #4]
- 800cbfe:	6f1b      	ldr	r3, [r3, #112]	; 0x70
- 800cc00:	2b00      	cmp	r3, #0
- 800cc02:	d102      	bne.n	800cc0a <tcp_rexmit_rto_prepare+0x2a>
-    return ERR_VAL;
- 800cc04:	f06f 0305 	mvn.w	r3, #5
- 800cc08:	e059      	b.n	800ccbe <tcp_rexmit_rto_prepare+0xde>
-
-  /* Move all unacked segments to the head of the unsent queue.
-     However, give up if any of the unsent pbufs are still referenced by the
-     netif driver due to deferred transmission. No point loading the link further
-     if it is struggling to flush its buffered writes. */
-  for (seg = pcb->unacked; seg->next != NULL; seg = seg->next) {
- 800cc0a:	687b      	ldr	r3, [r7, #4]
- 800cc0c:	6f1b      	ldr	r3, [r3, #112]	; 0x70
- 800cc0e:	60fb      	str	r3, [r7, #12]
- 800cc10:	e00b      	b.n	800cc2a <tcp_rexmit_rto_prepare+0x4a>
-    if (tcp_output_segment_busy(seg)) {
- 800cc12:	68f8      	ldr	r0, [r7, #12]
- 800cc14:	f7ff fee4 	bl	800c9e0 <tcp_output_segment_busy>
- 800cc18:	4603      	mov	r3, r0
- 800cc1a:	2b00      	cmp	r3, #0
- 800cc1c:	d002      	beq.n	800cc24 <tcp_rexmit_rto_prepare+0x44>
-      LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_rexmit_rto: segment busy\n"));
-      return ERR_VAL;
- 800cc1e:	f06f 0305 	mvn.w	r3, #5
- 800cc22:	e04c      	b.n	800ccbe <tcp_rexmit_rto_prepare+0xde>
-  for (seg = pcb->unacked; seg->next != NULL; seg = seg->next) {
- 800cc24:	68fb      	ldr	r3, [r7, #12]
- 800cc26:	681b      	ldr	r3, [r3, #0]
- 800cc28:	60fb      	str	r3, [r7, #12]
- 800cc2a:	68fb      	ldr	r3, [r7, #12]
- 800cc2c:	681b      	ldr	r3, [r3, #0]
- 800cc2e:	2b00      	cmp	r3, #0
- 800cc30:	d1ef      	bne.n	800cc12 <tcp_rexmit_rto_prepare+0x32>
-    }
-  }
-  if (tcp_output_segment_busy(seg)) {
- 800cc32:	68f8      	ldr	r0, [r7, #12]
- 800cc34:	f7ff fed4 	bl	800c9e0 <tcp_output_segment_busy>
- 800cc38:	4603      	mov	r3, r0
- 800cc3a:	2b00      	cmp	r3, #0
- 800cc3c:	d002      	beq.n	800cc44 <tcp_rexmit_rto_prepare+0x64>
-    LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_rexmit_rto: segment busy\n"));
-    return ERR_VAL;
- 800cc3e:	f06f 0305 	mvn.w	r3, #5
- 800cc42:	e03c      	b.n	800ccbe <tcp_rexmit_rto_prepare+0xde>
-  }
-  /* concatenate unsent queue after unacked queue */
-  seg->next = pcb->unsent;
- 800cc44:	687b      	ldr	r3, [r7, #4]
- 800cc46:	6eda      	ldr	r2, [r3, #108]	; 0x6c
- 800cc48:	68fb      	ldr	r3, [r7, #12]
- 800cc4a:	601a      	str	r2, [r3, #0]
-#if TCP_OVERSIZE_DBGCHECK
-  /* if last unsent changed, we need to update unsent_oversize */
-  if (pcb->unsent == NULL) {
- 800cc4c:	687b      	ldr	r3, [r7, #4]
- 800cc4e:	6edb      	ldr	r3, [r3, #108]	; 0x6c
- 800cc50:	2b00      	cmp	r3, #0
- 800cc52:	d104      	bne.n	800cc5e <tcp_rexmit_rto_prepare+0x7e>
-    pcb->unsent_oversize = seg->oversize_left;
- 800cc54:	68fb      	ldr	r3, [r7, #12]
- 800cc56:	895a      	ldrh	r2, [r3, #10]
- 800cc58:	687b      	ldr	r3, [r7, #4]
- 800cc5a:	f8a3 2068 	strh.w	r2, [r3, #104]	; 0x68
-  }
-#endif /* TCP_OVERSIZE_DBGCHECK */
-  /* unsent queue is the concatenated queue (of unacked, unsent) */
-  pcb->unsent = pcb->unacked;
- 800cc5e:	687b      	ldr	r3, [r7, #4]
- 800cc60:	6f1a      	ldr	r2, [r3, #112]	; 0x70
- 800cc62:	687b      	ldr	r3, [r7, #4]
- 800cc64:	66da      	str	r2, [r3, #108]	; 0x6c
-  /* unacked queue is now empty */
-  pcb->unacked = NULL;
- 800cc66:	687b      	ldr	r3, [r7, #4]
- 800cc68:	2200      	movs	r2, #0
- 800cc6a:	671a      	str	r2, [r3, #112]	; 0x70
-
-  /* Mark RTO in-progress */
-  tcp_set_flags(pcb, TF_RTO);
- 800cc6c:	687b      	ldr	r3, [r7, #4]
- 800cc6e:	8b5b      	ldrh	r3, [r3, #26]
- 800cc70:	f443 6300 	orr.w	r3, r3, #2048	; 0x800
- 800cc74:	b29a      	uxth	r2, r3
- 800cc76:	687b      	ldr	r3, [r7, #4]
- 800cc78:	835a      	strh	r2, [r3, #26]
-  /* Record the next byte following retransmit */
-  pcb->rto_end = lwip_ntohl(seg->tcphdr->seqno) + TCP_TCPLEN(seg);
- 800cc7a:	68fb      	ldr	r3, [r7, #12]
- 800cc7c:	691b      	ldr	r3, [r3, #16]
- 800cc7e:	685b      	ldr	r3, [r3, #4]
- 800cc80:	4618      	mov	r0, r3
- 800cc82:	f7f8 fc78 	bl	8005576 <lwip_htonl>
- 800cc86:	4604      	mov	r4, r0
- 800cc88:	68fb      	ldr	r3, [r7, #12]
- 800cc8a:	891b      	ldrh	r3, [r3, #8]
- 800cc8c:	461d      	mov	r5, r3
- 800cc8e:	68fb      	ldr	r3, [r7, #12]
- 800cc90:	691b      	ldr	r3, [r3, #16]
- 800cc92:	899b      	ldrh	r3, [r3, #12]
- 800cc94:	b29b      	uxth	r3, r3
- 800cc96:	4618      	mov	r0, r3
- 800cc98:	f7f8 fc58 	bl	800554c <lwip_htons>
- 800cc9c:	4603      	mov	r3, r0
- 800cc9e:	b2db      	uxtb	r3, r3
- 800cca0:	f003 0303 	and.w	r3, r3, #3
- 800cca4:	2b00      	cmp	r3, #0
- 800cca6:	d001      	beq.n	800ccac <tcp_rexmit_rto_prepare+0xcc>
- 800cca8:	2301      	movs	r3, #1
- 800ccaa:	e000      	b.n	800ccae <tcp_rexmit_rto_prepare+0xce>
- 800ccac:	2300      	movs	r3, #0
- 800ccae:	442b      	add	r3, r5
- 800ccb0:	18e2      	adds	r2, r4, r3
- 800ccb2:	687b      	ldr	r3, [r7, #4]
- 800ccb4:	64da      	str	r2, [r3, #76]	; 0x4c
-  /* Don't take any RTT measurements after retransmitting. */
-  pcb->rttest = 0;
- 800ccb6:	687b      	ldr	r3, [r7, #4]
- 800ccb8:	2200      	movs	r2, #0
- 800ccba:	635a      	str	r2, [r3, #52]	; 0x34
-
-  return ERR_OK;
- 800ccbc:	2300      	movs	r3, #0
-}
- 800ccbe:	4618      	mov	r0, r3
- 800ccc0:	3710      	adds	r7, #16
- 800ccc2:	46bd      	mov	sp, r7
- 800ccc4:	bdb0      	pop	{r4, r5, r7, pc}
- 800ccc6:	bf00      	nop
- 800ccc8:	08013618 	.word	0x08013618
- 800cccc:	08013cb0 	.word	0x08013cb0
- 800ccd0:	0801366c 	.word	0x0801366c
-
-0800ccd4 <tcp_rexmit_rto_commit>:
- *
- * @param pcb the tcp_pcb for which to re-enqueue all unacked segments
- */
-void
-tcp_rexmit_rto_commit(struct tcp_pcb *pcb)
-{
- 800ccd4:	b580      	push	{r7, lr}
- 800ccd6:	b082      	sub	sp, #8
- 800ccd8:	af00      	add	r7, sp, #0
- 800ccda:	6078      	str	r0, [r7, #4]
-  LWIP_ASSERT("tcp_rexmit_rto_commit: invalid pcb", pcb != NULL);
- 800ccdc:	687b      	ldr	r3, [r7, #4]
- 800ccde:	2b00      	cmp	r3, #0
- 800cce0:	d106      	bne.n	800ccf0 <tcp_rexmit_rto_commit+0x1c>
- 800cce2:	4b0d      	ldr	r3, [pc, #52]	; (800cd18 <tcp_rexmit_rto_commit+0x44>)
- 800cce4:	f44f 62d3 	mov.w	r2, #1688	; 0x698
- 800cce8:	490c      	ldr	r1, [pc, #48]	; (800cd1c <tcp_rexmit_rto_commit+0x48>)
- 800ccea:	480d      	ldr	r0, [pc, #52]	; (800cd20 <tcp_rexmit_rto_commit+0x4c>)
- 800ccec:	f003 ff6c 	bl	8010bc8 <iprintf>
-
-  /* increment number of retransmissions */
-  if (pcb->nrtx < 0xFF) {
- 800ccf0:	687b      	ldr	r3, [r7, #4]
- 800ccf2:	f893 3042 	ldrb.w	r3, [r3, #66]	; 0x42
- 800ccf6:	2bff      	cmp	r3, #255	; 0xff
- 800ccf8:	d007      	beq.n	800cd0a <tcp_rexmit_rto_commit+0x36>
-    ++pcb->nrtx;
- 800ccfa:	687b      	ldr	r3, [r7, #4]
- 800ccfc:	f893 3042 	ldrb.w	r3, [r3, #66]	; 0x42
- 800cd00:	3301      	adds	r3, #1
- 800cd02:	b2da      	uxtb	r2, r3
- 800cd04:	687b      	ldr	r3, [r7, #4]
- 800cd06:	f883 2042 	strb.w	r2, [r3, #66]	; 0x42
-  }
-  /* Do the actual retransmission */
-  tcp_output(pcb);
- 800cd0a:	6878      	ldr	r0, [r7, #4]
- 800cd0c:	f7ff fc72 	bl	800c5f4 <tcp_output>
-}
- 800cd10:	bf00      	nop
- 800cd12:	3708      	adds	r7, #8
- 800cd14:	46bd      	mov	sp, r7
- 800cd16:	bd80      	pop	{r7, pc}
- 800cd18:	08013618 	.word	0x08013618
- 800cd1c:	08013cd4 	.word	0x08013cd4
- 800cd20:	0801366c 	.word	0x0801366c
-
-0800cd24 <tcp_rexmit_rto>:
- *
- * @param pcb the tcp_pcb for which to re-enqueue all unacked segments
- */
-void
-tcp_rexmit_rto(struct tcp_pcb *pcb)
-{
- 800cd24:	b580      	push	{r7, lr}
- 800cd26:	b082      	sub	sp, #8
- 800cd28:	af00      	add	r7, sp, #0
- 800cd2a:	6078      	str	r0, [r7, #4]
-  LWIP_ASSERT("tcp_rexmit_rto: invalid pcb", pcb != NULL);
- 800cd2c:	687b      	ldr	r3, [r7, #4]
- 800cd2e:	2b00      	cmp	r3, #0
- 800cd30:	d106      	bne.n	800cd40 <tcp_rexmit_rto+0x1c>
- 800cd32:	4b0a      	ldr	r3, [pc, #40]	; (800cd5c <tcp_rexmit_rto+0x38>)
- 800cd34:	f240 62ad 	movw	r2, #1709	; 0x6ad
- 800cd38:	4909      	ldr	r1, [pc, #36]	; (800cd60 <tcp_rexmit_rto+0x3c>)
- 800cd3a:	480a      	ldr	r0, [pc, #40]	; (800cd64 <tcp_rexmit_rto+0x40>)
- 800cd3c:	f003 ff44 	bl	8010bc8 <iprintf>
-
-  if (tcp_rexmit_rto_prepare(pcb) == ERR_OK) {
- 800cd40:	6878      	ldr	r0, [r7, #4]
- 800cd42:	f7ff ff4d 	bl	800cbe0 <tcp_rexmit_rto_prepare>
- 800cd46:	4603      	mov	r3, r0
- 800cd48:	2b00      	cmp	r3, #0
- 800cd4a:	d102      	bne.n	800cd52 <tcp_rexmit_rto+0x2e>
-    tcp_rexmit_rto_commit(pcb);
- 800cd4c:	6878      	ldr	r0, [r7, #4]
- 800cd4e:	f7ff ffc1 	bl	800ccd4 <tcp_rexmit_rto_commit>
-  }
-}
- 800cd52:	bf00      	nop
- 800cd54:	3708      	adds	r7, #8
- 800cd56:	46bd      	mov	sp, r7
- 800cd58:	bd80      	pop	{r7, pc}
- 800cd5a:	bf00      	nop
- 800cd5c:	08013618 	.word	0x08013618
- 800cd60:	08013cf8 	.word	0x08013cf8
- 800cd64:	0801366c 	.word	0x0801366c
-
-0800cd68 <tcp_rexmit>:
- *
- * @param pcb the tcp_pcb for which to retransmit the first unacked segment
- */
-err_t
-tcp_rexmit(struct tcp_pcb *pcb)
-{
- 800cd68:	b590      	push	{r4, r7, lr}
- 800cd6a:	b085      	sub	sp, #20
- 800cd6c:	af00      	add	r7, sp, #0
- 800cd6e:	6078      	str	r0, [r7, #4]
-  struct tcp_seg *seg;
-  struct tcp_seg **cur_seg;
-
-  LWIP_ASSERT("tcp_rexmit: invalid pcb", pcb != NULL);
- 800cd70:	687b      	ldr	r3, [r7, #4]
- 800cd72:	2b00      	cmp	r3, #0
- 800cd74:	d106      	bne.n	800cd84 <tcp_rexmit+0x1c>
- 800cd76:	4b2f      	ldr	r3, [pc, #188]	; (800ce34 <tcp_rexmit+0xcc>)
- 800cd78:	f240 62c1 	movw	r2, #1729	; 0x6c1
- 800cd7c:	492e      	ldr	r1, [pc, #184]	; (800ce38 <tcp_rexmit+0xd0>)
- 800cd7e:	482f      	ldr	r0, [pc, #188]	; (800ce3c <tcp_rexmit+0xd4>)
- 800cd80:	f003 ff22 	bl	8010bc8 <iprintf>
-
-  if (pcb->unacked == NULL) {
- 800cd84:	687b      	ldr	r3, [r7, #4]
- 800cd86:	6f1b      	ldr	r3, [r3, #112]	; 0x70
- 800cd88:	2b00      	cmp	r3, #0
- 800cd8a:	d102      	bne.n	800cd92 <tcp_rexmit+0x2a>
-    return ERR_VAL;
- 800cd8c:	f06f 0305 	mvn.w	r3, #5
- 800cd90:	e04c      	b.n	800ce2c <tcp_rexmit+0xc4>
-  }
-
-  seg = pcb->unacked;
- 800cd92:	687b      	ldr	r3, [r7, #4]
- 800cd94:	6f1b      	ldr	r3, [r3, #112]	; 0x70
- 800cd96:	60bb      	str	r3, [r7, #8]
-
-  /* Give up if the segment is still referenced by the netif driver
-     due to deferred transmission. */
-  if (tcp_output_segment_busy(seg)) {
- 800cd98:	68b8      	ldr	r0, [r7, #8]
- 800cd9a:	f7ff fe21 	bl	800c9e0 <tcp_output_segment_busy>
- 800cd9e:	4603      	mov	r3, r0
- 800cda0:	2b00      	cmp	r3, #0
- 800cda2:	d002      	beq.n	800cdaa <tcp_rexmit+0x42>
-    LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_rexmit busy\n"));
-    return ERR_VAL;
- 800cda4:	f06f 0305 	mvn.w	r3, #5
- 800cda8:	e040      	b.n	800ce2c <tcp_rexmit+0xc4>
-  }
-
-  /* Move the first unacked segment to the unsent queue */
-  /* Keep the unsent queue sorted. */
-  pcb->unacked = seg->next;
- 800cdaa:	68bb      	ldr	r3, [r7, #8]
- 800cdac:	681a      	ldr	r2, [r3, #0]
- 800cdae:	687b      	ldr	r3, [r7, #4]
- 800cdb0:	671a      	str	r2, [r3, #112]	; 0x70
-
-  cur_seg = &(pcb->unsent);
- 800cdb2:	687b      	ldr	r3, [r7, #4]
- 800cdb4:	336c      	adds	r3, #108	; 0x6c
- 800cdb6:	60fb      	str	r3, [r7, #12]
-  while (*cur_seg &&
- 800cdb8:	e002      	b.n	800cdc0 <tcp_rexmit+0x58>
-         TCP_SEQ_LT(lwip_ntohl((*cur_seg)->tcphdr->seqno), lwip_ntohl(seg->tcphdr->seqno))) {
-    cur_seg = &((*cur_seg)->next );
- 800cdba:	68fb      	ldr	r3, [r7, #12]
- 800cdbc:	681b      	ldr	r3, [r3, #0]
- 800cdbe:	60fb      	str	r3, [r7, #12]
-  while (*cur_seg &&
- 800cdc0:	68fb      	ldr	r3, [r7, #12]
- 800cdc2:	681b      	ldr	r3, [r3, #0]
- 800cdc4:	2b00      	cmp	r3, #0
- 800cdc6:	d011      	beq.n	800cdec <tcp_rexmit+0x84>
-         TCP_SEQ_LT(lwip_ntohl((*cur_seg)->tcphdr->seqno), lwip_ntohl(seg->tcphdr->seqno))) {
- 800cdc8:	68fb      	ldr	r3, [r7, #12]
- 800cdca:	681b      	ldr	r3, [r3, #0]
- 800cdcc:	691b      	ldr	r3, [r3, #16]
- 800cdce:	685b      	ldr	r3, [r3, #4]
- 800cdd0:	4618      	mov	r0, r3
- 800cdd2:	f7f8 fbd0 	bl	8005576 <lwip_htonl>
- 800cdd6:	4604      	mov	r4, r0
- 800cdd8:	68bb      	ldr	r3, [r7, #8]
- 800cdda:	691b      	ldr	r3, [r3, #16]
- 800cddc:	685b      	ldr	r3, [r3, #4]
- 800cdde:	4618      	mov	r0, r3
- 800cde0:	f7f8 fbc9 	bl	8005576 <lwip_htonl>
- 800cde4:	4603      	mov	r3, r0
- 800cde6:	1ae3      	subs	r3, r4, r3
-  while (*cur_seg &&
- 800cde8:	2b00      	cmp	r3, #0
- 800cdea:	dbe6      	blt.n	800cdba <tcp_rexmit+0x52>
-  }
-  seg->next = *cur_seg;
- 800cdec:	68fb      	ldr	r3, [r7, #12]
- 800cdee:	681a      	ldr	r2, [r3, #0]
- 800cdf0:	68bb      	ldr	r3, [r7, #8]
- 800cdf2:	601a      	str	r2, [r3, #0]
-  *cur_seg = seg;
- 800cdf4:	68fb      	ldr	r3, [r7, #12]
- 800cdf6:	68ba      	ldr	r2, [r7, #8]
- 800cdf8:	601a      	str	r2, [r3, #0]
-#if TCP_OVERSIZE
-  if (seg->next == NULL) {
- 800cdfa:	68bb      	ldr	r3, [r7, #8]
- 800cdfc:	681b      	ldr	r3, [r3, #0]
- 800cdfe:	2b00      	cmp	r3, #0
- 800ce00:	d103      	bne.n	800ce0a <tcp_rexmit+0xa2>
-    /* the retransmitted segment is last in unsent, so reset unsent_oversize */
-    pcb->unsent_oversize = 0;
- 800ce02:	687b      	ldr	r3, [r7, #4]
- 800ce04:	2200      	movs	r2, #0
- 800ce06:	f8a3 2068 	strh.w	r2, [r3, #104]	; 0x68
-  }
-#endif /* TCP_OVERSIZE */
-
-  if (pcb->nrtx < 0xFF) {
- 800ce0a:	687b      	ldr	r3, [r7, #4]
- 800ce0c:	f893 3042 	ldrb.w	r3, [r3, #66]	; 0x42
- 800ce10:	2bff      	cmp	r3, #255	; 0xff
- 800ce12:	d007      	beq.n	800ce24 <tcp_rexmit+0xbc>
-    ++pcb->nrtx;
- 800ce14:	687b      	ldr	r3, [r7, #4]
- 800ce16:	f893 3042 	ldrb.w	r3, [r3, #66]	; 0x42
- 800ce1a:	3301      	adds	r3, #1
- 800ce1c:	b2da      	uxtb	r2, r3
- 800ce1e:	687b      	ldr	r3, [r7, #4]
- 800ce20:	f883 2042 	strb.w	r2, [r3, #66]	; 0x42
-  }
-
-  /* Don't take any rtt measurements after retransmitting. */
-  pcb->rttest = 0;
- 800ce24:	687b      	ldr	r3, [r7, #4]
- 800ce26:	2200      	movs	r2, #0
- 800ce28:	635a      	str	r2, [r3, #52]	; 0x34
-
-  /* Do the actual retransmission. */
-  MIB2_STATS_INC(mib2.tcpretranssegs);
-  /* No need to call tcp_output: we are always called from tcp_input()
-     and thus tcp_output directly returns. */
-  return ERR_OK;
- 800ce2a:	2300      	movs	r3, #0
-}
- 800ce2c:	4618      	mov	r0, r3
- 800ce2e:	3714      	adds	r7, #20
- 800ce30:	46bd      	mov	sp, r7
- 800ce32:	bd90      	pop	{r4, r7, pc}
- 800ce34:	08013618 	.word	0x08013618
- 800ce38:	08013d14 	.word	0x08013d14
- 800ce3c:	0801366c 	.word	0x0801366c
-
-0800ce40 <tcp_rexmit_fast>:
- *
- * @param pcb the tcp_pcb for which to retransmit the first unacked segment
- */
-void
-tcp_rexmit_fast(struct tcp_pcb *pcb)
-{
- 800ce40:	b580      	push	{r7, lr}
- 800ce42:	b082      	sub	sp, #8
- 800ce44:	af00      	add	r7, sp, #0
- 800ce46:	6078      	str	r0, [r7, #4]
-  LWIP_ASSERT("tcp_rexmit_fast: invalid pcb", pcb != NULL);
- 800ce48:	687b      	ldr	r3, [r7, #4]
- 800ce4a:	2b00      	cmp	r3, #0
- 800ce4c:	d106      	bne.n	800ce5c <tcp_rexmit_fast+0x1c>
- 800ce4e:	4b2a      	ldr	r3, [pc, #168]	; (800cef8 <tcp_rexmit_fast+0xb8>)
- 800ce50:	f240 62f9 	movw	r2, #1785	; 0x6f9
- 800ce54:	4929      	ldr	r1, [pc, #164]	; (800cefc <tcp_rexmit_fast+0xbc>)
- 800ce56:	482a      	ldr	r0, [pc, #168]	; (800cf00 <tcp_rexmit_fast+0xc0>)
- 800ce58:	f003 feb6 	bl	8010bc8 <iprintf>
-
-  if (pcb->unacked != NULL && !(pcb->flags & TF_INFR)) {
- 800ce5c:	687b      	ldr	r3, [r7, #4]
- 800ce5e:	6f1b      	ldr	r3, [r3, #112]	; 0x70
- 800ce60:	2b00      	cmp	r3, #0
- 800ce62:	d045      	beq.n	800cef0 <tcp_rexmit_fast+0xb0>
- 800ce64:	687b      	ldr	r3, [r7, #4]
- 800ce66:	8b5b      	ldrh	r3, [r3, #26]
- 800ce68:	f003 0304 	and.w	r3, r3, #4
- 800ce6c:	2b00      	cmp	r3, #0
- 800ce6e:	d13f      	bne.n	800cef0 <tcp_rexmit_fast+0xb0>
-    LWIP_DEBUGF(TCP_FR_DEBUG,
-                ("tcp_receive: dupacks %"U16_F" (%"U32_F
-                 "), fast retransmit %"U32_F"\n",
-                 (u16_t)pcb->dupacks, pcb->lastack,
-                 lwip_ntohl(pcb->unacked->tcphdr->seqno)));
-    if (tcp_rexmit(pcb) == ERR_OK) {
- 800ce70:	6878      	ldr	r0, [r7, #4]
- 800ce72:	f7ff ff79 	bl	800cd68 <tcp_rexmit>
- 800ce76:	4603      	mov	r3, r0
- 800ce78:	2b00      	cmp	r3, #0
- 800ce7a:	d139      	bne.n	800cef0 <tcp_rexmit_fast+0xb0>
-      /* Set ssthresh to half of the minimum of the current
-       * cwnd and the advertised window */
-      pcb->ssthresh = LWIP_MIN(pcb->cwnd, pcb->snd_wnd) / 2;
- 800ce7c:	687b      	ldr	r3, [r7, #4]
- 800ce7e:	f8b3 2060 	ldrh.w	r2, [r3, #96]	; 0x60
- 800ce82:	687b      	ldr	r3, [r7, #4]
- 800ce84:	f8b3 3048 	ldrh.w	r3, [r3, #72]	; 0x48
- 800ce88:	4293      	cmp	r3, r2
- 800ce8a:	bf28      	it	cs
- 800ce8c:	4613      	movcs	r3, r2
- 800ce8e:	b29b      	uxth	r3, r3
- 800ce90:	2b00      	cmp	r3, #0
- 800ce92:	da00      	bge.n	800ce96 <tcp_rexmit_fast+0x56>
- 800ce94:	3301      	adds	r3, #1
- 800ce96:	105b      	asrs	r3, r3, #1
- 800ce98:	b29a      	uxth	r2, r3
- 800ce9a:	687b      	ldr	r3, [r7, #4]
- 800ce9c:	f8a3 204a 	strh.w	r2, [r3, #74]	; 0x4a
-
-      /* The minimum value for ssthresh should be 2 MSS */
-      if (pcb->ssthresh < (2U * pcb->mss)) {
- 800cea0:	687b      	ldr	r3, [r7, #4]
- 800cea2:	f8b3 304a 	ldrh.w	r3, [r3, #74]	; 0x4a
- 800cea6:	461a      	mov	r2, r3
- 800cea8:	687b      	ldr	r3, [r7, #4]
- 800ceaa:	8e5b      	ldrh	r3, [r3, #50]	; 0x32
- 800ceac:	005b      	lsls	r3, r3, #1
- 800ceae:	429a      	cmp	r2, r3
- 800ceb0:	d206      	bcs.n	800cec0 <tcp_rexmit_fast+0x80>
-        LWIP_DEBUGF(TCP_FR_DEBUG,
-                    ("tcp_receive: The minimum value for ssthresh %"TCPWNDSIZE_F
-                     " should be min 2 mss %"U16_F"...\n",
-                     pcb->ssthresh, (u16_t)(2 * pcb->mss)));
-        pcb->ssthresh = 2 * pcb->mss;
- 800ceb2:	687b      	ldr	r3, [r7, #4]
- 800ceb4:	8e5b      	ldrh	r3, [r3, #50]	; 0x32
- 800ceb6:	005b      	lsls	r3, r3, #1
- 800ceb8:	b29a      	uxth	r2, r3
- 800ceba:	687b      	ldr	r3, [r7, #4]
- 800cebc:	f8a3 204a 	strh.w	r2, [r3, #74]	; 0x4a
-      }
-
-      pcb->cwnd = pcb->ssthresh + 3 * pcb->mss;
- 800cec0:	687b      	ldr	r3, [r7, #4]
- 800cec2:	f8b3 204a 	ldrh.w	r2, [r3, #74]	; 0x4a
- 800cec6:	687b      	ldr	r3, [r7, #4]
- 800cec8:	8e5b      	ldrh	r3, [r3, #50]	; 0x32
- 800ceca:	4619      	mov	r1, r3
- 800cecc:	0049      	lsls	r1, r1, #1
- 800cece:	440b      	add	r3, r1
- 800ced0:	b29b      	uxth	r3, r3
- 800ced2:	4413      	add	r3, r2
- 800ced4:	b29a      	uxth	r2, r3
- 800ced6:	687b      	ldr	r3, [r7, #4]
- 800ced8:	f8a3 2048 	strh.w	r2, [r3, #72]	; 0x48
-      tcp_set_flags(pcb, TF_INFR);
- 800cedc:	687b      	ldr	r3, [r7, #4]
- 800cede:	8b5b      	ldrh	r3, [r3, #26]
- 800cee0:	f043 0304 	orr.w	r3, r3, #4
- 800cee4:	b29a      	uxth	r2, r3
- 800cee6:	687b      	ldr	r3, [r7, #4]
- 800cee8:	835a      	strh	r2, [r3, #26]
-
-      /* Reset the retransmission timer to prevent immediate rto retransmissions */
-      pcb->rtime = 0;
- 800ceea:	687b      	ldr	r3, [r7, #4]
- 800ceec:	2200      	movs	r2, #0
- 800ceee:	861a      	strh	r2, [r3, #48]	; 0x30
-    }
-  }
-}
- 800cef0:	bf00      	nop
- 800cef2:	3708      	adds	r7, #8
- 800cef4:	46bd      	mov	sp, r7
- 800cef6:	bd80      	pop	{r7, pc}
- 800cef8:	08013618 	.word	0x08013618
- 800cefc:	08013d2c 	.word	0x08013d2c
- 800cf00:	0801366c 	.word	0x0801366c
-
-0800cf04 <tcp_output_alloc_header_common>:
-
-static struct pbuf *
-tcp_output_alloc_header_common(u32_t ackno, u16_t optlen, u16_t datalen,
-                        u32_t seqno_be /* already in network byte order */,
-                        u16_t src_port, u16_t dst_port, u8_t flags, u16_t wnd)
-{
- 800cf04:	b580      	push	{r7, lr}
- 800cf06:	b086      	sub	sp, #24
- 800cf08:	af00      	add	r7, sp, #0
- 800cf0a:	60f8      	str	r0, [r7, #12]
- 800cf0c:	607b      	str	r3, [r7, #4]
- 800cf0e:	460b      	mov	r3, r1
- 800cf10:	817b      	strh	r3, [r7, #10]
- 800cf12:	4613      	mov	r3, r2
- 800cf14:	813b      	strh	r3, [r7, #8]
-  struct tcp_hdr *tcphdr;
-  struct pbuf *p;
-
-  p = pbuf_alloc(PBUF_IP, TCP_HLEN + optlen + datalen, PBUF_RAM);
- 800cf16:	897a      	ldrh	r2, [r7, #10]
- 800cf18:	893b      	ldrh	r3, [r7, #8]
- 800cf1a:	4413      	add	r3, r2
- 800cf1c:	b29b      	uxth	r3, r3
- 800cf1e:	3314      	adds	r3, #20
- 800cf20:	b29b      	uxth	r3, r3
- 800cf22:	f44f 7220 	mov.w	r2, #640	; 0x280
- 800cf26:	4619      	mov	r1, r3
- 800cf28:	2022      	movs	r0, #34	; 0x22
- 800cf2a:	f7f9 fd6f 	bl	8006a0c <pbuf_alloc>
- 800cf2e:	6178      	str	r0, [r7, #20]
-  if (p != NULL) {
- 800cf30:	697b      	ldr	r3, [r7, #20]
- 800cf32:	2b00      	cmp	r3, #0
- 800cf34:	d04d      	beq.n	800cfd2 <tcp_output_alloc_header_common+0xce>
-    LWIP_ASSERT("check that first pbuf can hold struct tcp_hdr",
- 800cf36:	897b      	ldrh	r3, [r7, #10]
- 800cf38:	3313      	adds	r3, #19
- 800cf3a:	697a      	ldr	r2, [r7, #20]
- 800cf3c:	8952      	ldrh	r2, [r2, #10]
- 800cf3e:	4293      	cmp	r3, r2
- 800cf40:	db06      	blt.n	800cf50 <tcp_output_alloc_header_common+0x4c>
- 800cf42:	4b26      	ldr	r3, [pc, #152]	; (800cfdc <tcp_output_alloc_header_common+0xd8>)
- 800cf44:	f240 7223 	movw	r2, #1827	; 0x723
- 800cf48:	4925      	ldr	r1, [pc, #148]	; (800cfe0 <tcp_output_alloc_header_common+0xdc>)
- 800cf4a:	4826      	ldr	r0, [pc, #152]	; (800cfe4 <tcp_output_alloc_header_common+0xe0>)
- 800cf4c:	f003 fe3c 	bl	8010bc8 <iprintf>
-                (p->len >= TCP_HLEN + optlen));
-    tcphdr = (struct tcp_hdr *)p->payload;
- 800cf50:	697b      	ldr	r3, [r7, #20]
- 800cf52:	685b      	ldr	r3, [r3, #4]
- 800cf54:	613b      	str	r3, [r7, #16]
-    tcphdr->src = lwip_htons(src_port);
- 800cf56:	8c3b      	ldrh	r3, [r7, #32]
- 800cf58:	4618      	mov	r0, r3
- 800cf5a:	f7f8 faf7 	bl	800554c <lwip_htons>
- 800cf5e:	4603      	mov	r3, r0
- 800cf60:	461a      	mov	r2, r3
- 800cf62:	693b      	ldr	r3, [r7, #16]
- 800cf64:	801a      	strh	r2, [r3, #0]
-    tcphdr->dest = lwip_htons(dst_port);
- 800cf66:	8cbb      	ldrh	r3, [r7, #36]	; 0x24
- 800cf68:	4618      	mov	r0, r3
- 800cf6a:	f7f8 faef 	bl	800554c <lwip_htons>
- 800cf6e:	4603      	mov	r3, r0
- 800cf70:	461a      	mov	r2, r3
- 800cf72:	693b      	ldr	r3, [r7, #16]
- 800cf74:	805a      	strh	r2, [r3, #2]
-    tcphdr->seqno = seqno_be;
- 800cf76:	693b      	ldr	r3, [r7, #16]
- 800cf78:	687a      	ldr	r2, [r7, #4]
- 800cf7a:	605a      	str	r2, [r3, #4]
-    tcphdr->ackno = lwip_htonl(ackno);
- 800cf7c:	68f8      	ldr	r0, [r7, #12]
- 800cf7e:	f7f8 fafa 	bl	8005576 <lwip_htonl>
- 800cf82:	4602      	mov	r2, r0
- 800cf84:	693b      	ldr	r3, [r7, #16]
- 800cf86:	609a      	str	r2, [r3, #8]
-    TCPH_HDRLEN_FLAGS_SET(tcphdr, (5 + optlen / 4), flags);
- 800cf88:	897b      	ldrh	r3, [r7, #10]
- 800cf8a:	089b      	lsrs	r3, r3, #2
- 800cf8c:	b29b      	uxth	r3, r3
- 800cf8e:	3305      	adds	r3, #5
- 800cf90:	b29b      	uxth	r3, r3
- 800cf92:	031b      	lsls	r3, r3, #12
- 800cf94:	b29a      	uxth	r2, r3
- 800cf96:	f897 3028 	ldrb.w	r3, [r7, #40]	; 0x28
- 800cf9a:	b29b      	uxth	r3, r3
- 800cf9c:	4313      	orrs	r3, r2
- 800cf9e:	b29b      	uxth	r3, r3
- 800cfa0:	4618      	mov	r0, r3
- 800cfa2:	f7f8 fad3 	bl	800554c <lwip_htons>
- 800cfa6:	4603      	mov	r3, r0
- 800cfa8:	461a      	mov	r2, r3
- 800cfaa:	693b      	ldr	r3, [r7, #16]
- 800cfac:	819a      	strh	r2, [r3, #12]
-    tcphdr->wnd = lwip_htons(wnd);
- 800cfae:	8dbb      	ldrh	r3, [r7, #44]	; 0x2c
- 800cfb0:	4618      	mov	r0, r3
- 800cfb2:	f7f8 facb 	bl	800554c <lwip_htons>
- 800cfb6:	4603      	mov	r3, r0
- 800cfb8:	461a      	mov	r2, r3
- 800cfba:	693b      	ldr	r3, [r7, #16]
- 800cfbc:	81da      	strh	r2, [r3, #14]
-    tcphdr->chksum = 0;
- 800cfbe:	693b      	ldr	r3, [r7, #16]
- 800cfc0:	2200      	movs	r2, #0
- 800cfc2:	741a      	strb	r2, [r3, #16]
- 800cfc4:	2200      	movs	r2, #0
- 800cfc6:	745a      	strb	r2, [r3, #17]
-    tcphdr->urgp = 0;
- 800cfc8:	693b      	ldr	r3, [r7, #16]
- 800cfca:	2200      	movs	r2, #0
- 800cfcc:	749a      	strb	r2, [r3, #18]
- 800cfce:	2200      	movs	r2, #0
- 800cfd0:	74da      	strb	r2, [r3, #19]
-  }
-  return p;
- 800cfd2:	697b      	ldr	r3, [r7, #20]
-}
- 800cfd4:	4618      	mov	r0, r3
- 800cfd6:	3718      	adds	r7, #24
- 800cfd8:	46bd      	mov	sp, r7
- 800cfda:	bd80      	pop	{r7, pc}
- 800cfdc:	08013618 	.word	0x08013618
- 800cfe0:	08013d4c 	.word	0x08013d4c
- 800cfe4:	0801366c 	.word	0x0801366c
-
-0800cfe8 <tcp_output_alloc_header>:
- * @return pbuf with p->payload being the tcp_hdr
- */
-static struct pbuf *
-tcp_output_alloc_header(struct tcp_pcb *pcb, u16_t optlen, u16_t datalen,
-                        u32_t seqno_be /* already in network byte order */)
-{
- 800cfe8:	b5b0      	push	{r4, r5, r7, lr}
- 800cfea:	b08a      	sub	sp, #40	; 0x28
- 800cfec:	af04      	add	r7, sp, #16
- 800cfee:	60f8      	str	r0, [r7, #12]
- 800cff0:	607b      	str	r3, [r7, #4]
- 800cff2:	460b      	mov	r3, r1
- 800cff4:	817b      	strh	r3, [r7, #10]
- 800cff6:	4613      	mov	r3, r2
- 800cff8:	813b      	strh	r3, [r7, #8]
-  struct pbuf *p;
-
-  LWIP_ASSERT("tcp_output_alloc_header: invalid pcb", pcb != NULL);
- 800cffa:	68fb      	ldr	r3, [r7, #12]
- 800cffc:	2b00      	cmp	r3, #0
- 800cffe:	d106      	bne.n	800d00e <tcp_output_alloc_header+0x26>
- 800d000:	4b15      	ldr	r3, [pc, #84]	; (800d058 <tcp_output_alloc_header+0x70>)
- 800d002:	f240 7242 	movw	r2, #1858	; 0x742
- 800d006:	4915      	ldr	r1, [pc, #84]	; (800d05c <tcp_output_alloc_header+0x74>)
- 800d008:	4815      	ldr	r0, [pc, #84]	; (800d060 <tcp_output_alloc_header+0x78>)
- 800d00a:	f003 fddd 	bl	8010bc8 <iprintf>
-
-  p = tcp_output_alloc_header_common(pcb->rcv_nxt, optlen, datalen,
- 800d00e:	68fb      	ldr	r3, [r7, #12]
- 800d010:	6a58      	ldr	r0, [r3, #36]	; 0x24
- 800d012:	68fb      	ldr	r3, [r7, #12]
- 800d014:	8adb      	ldrh	r3, [r3, #22]
- 800d016:	68fa      	ldr	r2, [r7, #12]
- 800d018:	8b12      	ldrh	r2, [r2, #24]
- 800d01a:	68f9      	ldr	r1, [r7, #12]
- 800d01c:	8d49      	ldrh	r1, [r1, #42]	; 0x2a
- 800d01e:	893d      	ldrh	r5, [r7, #8]
- 800d020:	897c      	ldrh	r4, [r7, #10]
- 800d022:	9103      	str	r1, [sp, #12]
- 800d024:	2110      	movs	r1, #16
- 800d026:	9102      	str	r1, [sp, #8]
- 800d028:	9201      	str	r2, [sp, #4]
- 800d02a:	9300      	str	r3, [sp, #0]
- 800d02c:	687b      	ldr	r3, [r7, #4]
- 800d02e:	462a      	mov	r2, r5
- 800d030:	4621      	mov	r1, r4
- 800d032:	f7ff ff67 	bl	800cf04 <tcp_output_alloc_header_common>
- 800d036:	6178      	str	r0, [r7, #20]
-    seqno_be, pcb->local_port, pcb->remote_port, TCP_ACK,
-    TCPWND_MIN16(RCV_WND_SCALE(pcb, pcb->rcv_ann_wnd)));
-  if (p != NULL) {
- 800d038:	697b      	ldr	r3, [r7, #20]
- 800d03a:	2b00      	cmp	r3, #0
- 800d03c:	d006      	beq.n	800d04c <tcp_output_alloc_header+0x64>
-    /* If we're sending a packet, update the announced right window edge */
-    pcb->rcv_ann_right_edge = pcb->rcv_nxt + pcb->rcv_ann_wnd;
- 800d03e:	68fb      	ldr	r3, [r7, #12]
- 800d040:	6a5b      	ldr	r3, [r3, #36]	; 0x24
- 800d042:	68fa      	ldr	r2, [r7, #12]
- 800d044:	8d52      	ldrh	r2, [r2, #42]	; 0x2a
- 800d046:	441a      	add	r2, r3
- 800d048:	68fb      	ldr	r3, [r7, #12]
- 800d04a:	62da      	str	r2, [r3, #44]	; 0x2c
-  }
-  return p;
- 800d04c:	697b      	ldr	r3, [r7, #20]
-}
- 800d04e:	4618      	mov	r0, r3
- 800d050:	3718      	adds	r7, #24
- 800d052:	46bd      	mov	sp, r7
- 800d054:	bdb0      	pop	{r4, r5, r7, pc}
- 800d056:	bf00      	nop
- 800d058:	08013618 	.word	0x08013618
- 800d05c:	08013d7c 	.word	0x08013d7c
- 800d060:	0801366c 	.word	0x0801366c
-
-0800d064 <tcp_output_fill_options>:
-
-/* Fill in options for control segments */
-static void
-tcp_output_fill_options(const struct tcp_pcb *pcb, struct pbuf *p, u8_t optflags, u8_t num_sacks)
-{
- 800d064:	b580      	push	{r7, lr}
- 800d066:	b088      	sub	sp, #32
- 800d068:	af00      	add	r7, sp, #0
- 800d06a:	60f8      	str	r0, [r7, #12]
- 800d06c:	60b9      	str	r1, [r7, #8]
- 800d06e:	4611      	mov	r1, r2
- 800d070:	461a      	mov	r2, r3
- 800d072:	460b      	mov	r3, r1
- 800d074:	71fb      	strb	r3, [r7, #7]
- 800d076:	4613      	mov	r3, r2
- 800d078:	71bb      	strb	r3, [r7, #6]
-  struct tcp_hdr *tcphdr;
-  u32_t *opts;
-  u16_t sacks_len = 0;
- 800d07a:	2300      	movs	r3, #0
- 800d07c:	83fb      	strh	r3, [r7, #30]
-
-  LWIP_ASSERT("tcp_output_fill_options: invalid pbuf", p != NULL);
- 800d07e:	68bb      	ldr	r3, [r7, #8]
- 800d080:	2b00      	cmp	r3, #0
- 800d082:	d106      	bne.n	800d092 <tcp_output_fill_options+0x2e>
- 800d084:	4b12      	ldr	r3, [pc, #72]	; (800d0d0 <tcp_output_fill_options+0x6c>)
- 800d086:	f240 7256 	movw	r2, #1878	; 0x756
- 800d08a:	4912      	ldr	r1, [pc, #72]	; (800d0d4 <tcp_output_fill_options+0x70>)
- 800d08c:	4812      	ldr	r0, [pc, #72]	; (800d0d8 <tcp_output_fill_options+0x74>)
- 800d08e:	f003 fd9b 	bl	8010bc8 <iprintf>
-
-  tcphdr = (struct tcp_hdr *)p->payload;
- 800d092:	68bb      	ldr	r3, [r7, #8]
- 800d094:	685b      	ldr	r3, [r3, #4]
- 800d096:	61bb      	str	r3, [r7, #24]
-  opts = (u32_t *)(void *)(tcphdr + 1);
- 800d098:	69bb      	ldr	r3, [r7, #24]
- 800d09a:	3314      	adds	r3, #20
- 800d09c:	617b      	str	r3, [r7, #20]
-  opts = LWIP_HOOK_TCP_OUT_ADD_TCPOPTS(p, tcphdr, pcb, opts);
-#endif
-
-  LWIP_UNUSED_ARG(pcb);
-  LWIP_UNUSED_ARG(sacks_len);
-  LWIP_ASSERT("options not filled", (u8_t *)opts == ((u8_t *)(tcphdr + 1)) + sacks_len * 4 + LWIP_TCP_OPT_LENGTH_SEGMENT(optflags, pcb));
- 800d09e:	8bfb      	ldrh	r3, [r7, #30]
- 800d0a0:	009b      	lsls	r3, r3, #2
- 800d0a2:	461a      	mov	r2, r3
- 800d0a4:	79fb      	ldrb	r3, [r7, #7]
- 800d0a6:	009b      	lsls	r3, r3, #2
- 800d0a8:	f003 0304 	and.w	r3, r3, #4
- 800d0ac:	4413      	add	r3, r2
- 800d0ae:	3314      	adds	r3, #20
- 800d0b0:	69ba      	ldr	r2, [r7, #24]
- 800d0b2:	4413      	add	r3, r2
- 800d0b4:	697a      	ldr	r2, [r7, #20]
- 800d0b6:	429a      	cmp	r2, r3
- 800d0b8:	d006      	beq.n	800d0c8 <tcp_output_fill_options+0x64>
- 800d0ba:	4b05      	ldr	r3, [pc, #20]	; (800d0d0 <tcp_output_fill_options+0x6c>)
- 800d0bc:	f240 7275 	movw	r2, #1909	; 0x775
- 800d0c0:	4906      	ldr	r1, [pc, #24]	; (800d0dc <tcp_output_fill_options+0x78>)
- 800d0c2:	4805      	ldr	r0, [pc, #20]	; (800d0d8 <tcp_output_fill_options+0x74>)
- 800d0c4:	f003 fd80 	bl	8010bc8 <iprintf>
-  LWIP_UNUSED_ARG(optflags); /* for LWIP_NOASSERT */
-  LWIP_UNUSED_ARG(opts); /* for LWIP_NOASSERT */
-}
- 800d0c8:	bf00      	nop
- 800d0ca:	3720      	adds	r7, #32
- 800d0cc:	46bd      	mov	sp, r7
- 800d0ce:	bd80      	pop	{r7, pc}
- 800d0d0:	08013618 	.word	0x08013618
- 800d0d4:	08013da4 	.word	0x08013da4
- 800d0d8:	0801366c 	.word	0x0801366c
- 800d0dc:	08013c9c 	.word	0x08013c9c
-
-0800d0e0 <tcp_output_control_segment>:
- * header checksum and calling ip_output_if while handling netif hints and stats.
- */
-static err_t
-tcp_output_control_segment(const struct tcp_pcb *pcb, struct pbuf *p,
-                           const ip_addr_t *src, const ip_addr_t *dst)
-{
- 800d0e0:	b580      	push	{r7, lr}
- 800d0e2:	b08a      	sub	sp, #40	; 0x28
- 800d0e4:	af04      	add	r7, sp, #16
- 800d0e6:	60f8      	str	r0, [r7, #12]
- 800d0e8:	60b9      	str	r1, [r7, #8]
- 800d0ea:	607a      	str	r2, [r7, #4]
- 800d0ec:	603b      	str	r3, [r7, #0]
-  err_t err;
-  struct netif *netif;
-
-  LWIP_ASSERT("tcp_output_control_segment: invalid pbuf", p != NULL);
- 800d0ee:	68bb      	ldr	r3, [r7, #8]
- 800d0f0:	2b00      	cmp	r3, #0
- 800d0f2:	d106      	bne.n	800d102 <tcp_output_control_segment+0x22>
- 800d0f4:	4b1c      	ldr	r3, [pc, #112]	; (800d168 <tcp_output_control_segment+0x88>)
- 800d0f6:	f240 7287 	movw	r2, #1927	; 0x787
- 800d0fa:	491c      	ldr	r1, [pc, #112]	; (800d16c <tcp_output_control_segment+0x8c>)
- 800d0fc:	481c      	ldr	r0, [pc, #112]	; (800d170 <tcp_output_control_segment+0x90>)
- 800d0fe:	f003 fd63 	bl	8010bc8 <iprintf>
-
-  netif = tcp_route(pcb, src, dst);
- 800d102:	683a      	ldr	r2, [r7, #0]
- 800d104:	6879      	ldr	r1, [r7, #4]
- 800d106:	68f8      	ldr	r0, [r7, #12]
- 800d108:	f7fe fa7c 	bl	800b604 <tcp_route>
- 800d10c:	6138      	str	r0, [r7, #16]
-  if (netif == NULL) {
- 800d10e:	693b      	ldr	r3, [r7, #16]
- 800d110:	2b00      	cmp	r3, #0
- 800d112:	d102      	bne.n	800d11a <tcp_output_control_segment+0x3a>
-    err = ERR_RTE;
- 800d114:	23fc      	movs	r3, #252	; 0xfc
- 800d116:	75fb      	strb	r3, [r7, #23]
- 800d118:	e01c      	b.n	800d154 <tcp_output_control_segment+0x74>
-      struct tcp_hdr *tcphdr = (struct tcp_hdr *)p->payload;
-      tcphdr->chksum = ip_chksum_pseudo(p, IP_PROTO_TCP, p->tot_len,
-                                        src, dst);
-    }
-#endif
-    if (pcb != NULL) {
- 800d11a:	68fb      	ldr	r3, [r7, #12]
- 800d11c:	2b00      	cmp	r3, #0
- 800d11e:	d006      	beq.n	800d12e <tcp_output_control_segment+0x4e>
-      NETIF_SET_HINTS(netif, LWIP_CONST_CAST(struct netif_hint*, &(pcb->netif_hints)));
-      ttl = pcb->ttl;
- 800d120:	68fb      	ldr	r3, [r7, #12]
- 800d122:	7adb      	ldrb	r3, [r3, #11]
- 800d124:	75bb      	strb	r3, [r7, #22]
-      tos = pcb->tos;
- 800d126:	68fb      	ldr	r3, [r7, #12]
- 800d128:	7a9b      	ldrb	r3, [r3, #10]
- 800d12a:	757b      	strb	r3, [r7, #21]
- 800d12c:	e003      	b.n	800d136 <tcp_output_control_segment+0x56>
-    } else {
-      /* Send output with hardcoded TTL/HL since we have no access to the pcb */
-      ttl = TCP_TTL;
- 800d12e:	23ff      	movs	r3, #255	; 0xff
- 800d130:	75bb      	strb	r3, [r7, #22]
-      tos = 0;
- 800d132:	2300      	movs	r3, #0
- 800d134:	757b      	strb	r3, [r7, #21]
-    }
-    TCP_STATS_INC(tcp.xmit);
-    err = ip_output_if(p, src, dst, ttl, tos, IP_PROTO_TCP, netif);
- 800d136:	7dba      	ldrb	r2, [r7, #22]
- 800d138:	693b      	ldr	r3, [r7, #16]
- 800d13a:	9302      	str	r3, [sp, #8]
- 800d13c:	2306      	movs	r3, #6
- 800d13e:	9301      	str	r3, [sp, #4]
- 800d140:	7d7b      	ldrb	r3, [r7, #21]
- 800d142:	9300      	str	r3, [sp, #0]
- 800d144:	4613      	mov	r3, r2
- 800d146:	683a      	ldr	r2, [r7, #0]
- 800d148:	6879      	ldr	r1, [r7, #4]
- 800d14a:	68b8      	ldr	r0, [r7, #8]
- 800d14c:	f002 f85a 	bl	800f204 <ip4_output_if>
- 800d150:	4603      	mov	r3, r0
- 800d152:	75fb      	strb	r3, [r7, #23]
-    NETIF_RESET_HINTS(netif);
-  }
-  pbuf_free(p);
- 800d154:	68b8      	ldr	r0, [r7, #8]
- 800d156:	f7f9 ff3d 	bl	8006fd4 <pbuf_free>
-  return err;
- 800d15a:	f997 3017 	ldrsb.w	r3, [r7, #23]
-}
- 800d15e:	4618      	mov	r0, r3
- 800d160:	3718      	adds	r7, #24
- 800d162:	46bd      	mov	sp, r7
- 800d164:	bd80      	pop	{r7, pc}
- 800d166:	bf00      	nop
- 800d168:	08013618 	.word	0x08013618
- 800d16c:	08013dcc 	.word	0x08013dcc
- 800d170:	0801366c 	.word	0x0801366c
-
-0800d174 <tcp_rst>:
- */
-void
-tcp_rst(const struct tcp_pcb *pcb, u32_t seqno, u32_t ackno,
-        const ip_addr_t *local_ip, const ip_addr_t *remote_ip,
-        u16_t local_port, u16_t remote_port)
-{
- 800d174:	b590      	push	{r4, r7, lr}
- 800d176:	b08b      	sub	sp, #44	; 0x2c
- 800d178:	af04      	add	r7, sp, #16
- 800d17a:	60f8      	str	r0, [r7, #12]
- 800d17c:	60b9      	str	r1, [r7, #8]
- 800d17e:	607a      	str	r2, [r7, #4]
- 800d180:	603b      	str	r3, [r7, #0]
-  struct pbuf *p;
-  u16_t wnd;
-  u8_t optlen;
-
-  LWIP_ASSERT("tcp_rst: invalid local_ip", local_ip != NULL);
- 800d182:	683b      	ldr	r3, [r7, #0]
- 800d184:	2b00      	cmp	r3, #0
- 800d186:	d106      	bne.n	800d196 <tcp_rst+0x22>
- 800d188:	4b1f      	ldr	r3, [pc, #124]	; (800d208 <tcp_rst+0x94>)
- 800d18a:	f240 72c4 	movw	r2, #1988	; 0x7c4
- 800d18e:	491f      	ldr	r1, [pc, #124]	; (800d20c <tcp_rst+0x98>)
- 800d190:	481f      	ldr	r0, [pc, #124]	; (800d210 <tcp_rst+0x9c>)
- 800d192:	f003 fd19 	bl	8010bc8 <iprintf>
-  LWIP_ASSERT("tcp_rst: invalid remote_ip", remote_ip != NULL);
- 800d196:	6abb      	ldr	r3, [r7, #40]	; 0x28
- 800d198:	2b00      	cmp	r3, #0
- 800d19a:	d106      	bne.n	800d1aa <tcp_rst+0x36>
- 800d19c:	4b1a      	ldr	r3, [pc, #104]	; (800d208 <tcp_rst+0x94>)
- 800d19e:	f240 72c5 	movw	r2, #1989	; 0x7c5
- 800d1a2:	491c      	ldr	r1, [pc, #112]	; (800d214 <tcp_rst+0xa0>)
- 800d1a4:	481a      	ldr	r0, [pc, #104]	; (800d210 <tcp_rst+0x9c>)
- 800d1a6:	f003 fd0f 	bl	8010bc8 <iprintf>
-
-  optlen = LWIP_TCP_OPT_LENGTH_SEGMENT(0, pcb);
- 800d1aa:	2300      	movs	r3, #0
- 800d1ac:	75fb      	strb	r3, [r7, #23]
-
-#if LWIP_WND_SCALE
-  wnd = PP_HTONS(((TCP_WND >> TCP_RCV_SCALE) & 0xFFFF));
-#else
-  wnd = PP_HTONS(TCP_WND);
- 800d1ae:	f246 0308 	movw	r3, #24584	; 0x6008
- 800d1b2:	82bb      	strh	r3, [r7, #20]
-#endif
-
-  p = tcp_output_alloc_header_common(ackno, optlen, 0, lwip_htonl(seqno), local_port,
- 800d1b4:	7dfb      	ldrb	r3, [r7, #23]
- 800d1b6:	b29c      	uxth	r4, r3
- 800d1b8:	68b8      	ldr	r0, [r7, #8]
- 800d1ba:	f7f8 f9dc 	bl	8005576 <lwip_htonl>
- 800d1be:	4602      	mov	r2, r0
- 800d1c0:	8abb      	ldrh	r3, [r7, #20]
- 800d1c2:	9303      	str	r3, [sp, #12]
- 800d1c4:	2314      	movs	r3, #20
- 800d1c6:	9302      	str	r3, [sp, #8]
- 800d1c8:	8e3b      	ldrh	r3, [r7, #48]	; 0x30
- 800d1ca:	9301      	str	r3, [sp, #4]
- 800d1cc:	8dbb      	ldrh	r3, [r7, #44]	; 0x2c
- 800d1ce:	9300      	str	r3, [sp, #0]
- 800d1d0:	4613      	mov	r3, r2
- 800d1d2:	2200      	movs	r2, #0
- 800d1d4:	4621      	mov	r1, r4
- 800d1d6:	6878      	ldr	r0, [r7, #4]
- 800d1d8:	f7ff fe94 	bl	800cf04 <tcp_output_alloc_header_common>
- 800d1dc:	6138      	str	r0, [r7, #16]
-    remote_port, TCP_RST | TCP_ACK, wnd);
-  if (p == NULL) {
- 800d1de:	693b      	ldr	r3, [r7, #16]
- 800d1e0:	2b00      	cmp	r3, #0
- 800d1e2:	d00c      	beq.n	800d1fe <tcp_rst+0x8a>
-    LWIP_DEBUGF(TCP_DEBUG, ("tcp_rst: could not allocate memory for pbuf\n"));
-    return;
-  }
-  tcp_output_fill_options(pcb, p, 0, optlen);
- 800d1e4:	7dfb      	ldrb	r3, [r7, #23]
- 800d1e6:	2200      	movs	r2, #0
- 800d1e8:	6939      	ldr	r1, [r7, #16]
- 800d1ea:	68f8      	ldr	r0, [r7, #12]
- 800d1ec:	f7ff ff3a 	bl	800d064 <tcp_output_fill_options>
-
-  MIB2_STATS_INC(mib2.tcpoutrsts);
-
-  tcp_output_control_segment(pcb, p, local_ip, remote_ip);
- 800d1f0:	6abb      	ldr	r3, [r7, #40]	; 0x28
- 800d1f2:	683a      	ldr	r2, [r7, #0]
- 800d1f4:	6939      	ldr	r1, [r7, #16]
- 800d1f6:	68f8      	ldr	r0, [r7, #12]
- 800d1f8:	f7ff ff72 	bl	800d0e0 <tcp_output_control_segment>
- 800d1fc:	e000      	b.n	800d200 <tcp_rst+0x8c>
-    return;
- 800d1fe:	bf00      	nop
-  LWIP_DEBUGF(TCP_RST_DEBUG, ("tcp_rst: seqno %"U32_F" ackno %"U32_F".\n", seqno, ackno));
-}
- 800d200:	371c      	adds	r7, #28
- 800d202:	46bd      	mov	sp, r7
- 800d204:	bd90      	pop	{r4, r7, pc}
- 800d206:	bf00      	nop
- 800d208:	08013618 	.word	0x08013618
- 800d20c:	08013df8 	.word	0x08013df8
- 800d210:	0801366c 	.word	0x0801366c
- 800d214:	08013e14 	.word	0x08013e14
-
-0800d218 <tcp_send_empty_ack>:
- *
- * @param pcb Protocol control block for the TCP connection to send the ACK
- */
-err_t
-tcp_send_empty_ack(struct tcp_pcb *pcb)
-{
- 800d218:	b590      	push	{r4, r7, lr}
- 800d21a:	b087      	sub	sp, #28
- 800d21c:	af00      	add	r7, sp, #0
- 800d21e:	6078      	str	r0, [r7, #4]
-  err_t err;
-  struct pbuf *p;
-  u8_t optlen, optflags = 0;
- 800d220:	2300      	movs	r3, #0
- 800d222:	75fb      	strb	r3, [r7, #23]
-  u8_t num_sacks = 0;
- 800d224:	2300      	movs	r3, #0
- 800d226:	75bb      	strb	r3, [r7, #22]
-
-  LWIP_ASSERT("tcp_send_empty_ack: invalid pcb", pcb != NULL);
- 800d228:	687b      	ldr	r3, [r7, #4]
- 800d22a:	2b00      	cmp	r3, #0
- 800d22c:	d106      	bne.n	800d23c <tcp_send_empty_ack+0x24>
- 800d22e:	4b28      	ldr	r3, [pc, #160]	; (800d2d0 <tcp_send_empty_ack+0xb8>)
- 800d230:	f240 72ea 	movw	r2, #2026	; 0x7ea
- 800d234:	4927      	ldr	r1, [pc, #156]	; (800d2d4 <tcp_send_empty_ack+0xbc>)
- 800d236:	4828      	ldr	r0, [pc, #160]	; (800d2d8 <tcp_send_empty_ack+0xc0>)
- 800d238:	f003 fcc6 	bl	8010bc8 <iprintf>
-#if LWIP_TCP_TIMESTAMPS
-  if (pcb->flags & TF_TIMESTAMP) {
-    optflags = TF_SEG_OPTS_TS;
-  }
-#endif
-  optlen = LWIP_TCP_OPT_LENGTH_SEGMENT(optflags, pcb);
- 800d23c:	7dfb      	ldrb	r3, [r7, #23]
- 800d23e:	009b      	lsls	r3, r3, #2
- 800d240:	b2db      	uxtb	r3, r3
- 800d242:	f003 0304 	and.w	r3, r3, #4
- 800d246:	757b      	strb	r3, [r7, #21]
-  if ((num_sacks = tcp_get_num_sacks(pcb, optlen)) > 0) {
-    optlen += 4 + num_sacks * 8; /* 4 bytes for header (including 2*NOP), plus 8B for each SACK */
-  }
-#endif
-
-  p = tcp_output_alloc_header(pcb, optlen, 0, lwip_htonl(pcb->snd_nxt));
- 800d248:	7d7b      	ldrb	r3, [r7, #21]
- 800d24a:	b29c      	uxth	r4, r3
- 800d24c:	687b      	ldr	r3, [r7, #4]
- 800d24e:	6d1b      	ldr	r3, [r3, #80]	; 0x50
- 800d250:	4618      	mov	r0, r3
- 800d252:	f7f8 f990 	bl	8005576 <lwip_htonl>
- 800d256:	4603      	mov	r3, r0
- 800d258:	2200      	movs	r2, #0
- 800d25a:	4621      	mov	r1, r4
- 800d25c:	6878      	ldr	r0, [r7, #4]
- 800d25e:	f7ff fec3 	bl	800cfe8 <tcp_output_alloc_header>
- 800d262:	6138      	str	r0, [r7, #16]
-  if (p == NULL) {
- 800d264:	693b      	ldr	r3, [r7, #16]
- 800d266:	2b00      	cmp	r3, #0
- 800d268:	d109      	bne.n	800d27e <tcp_send_empty_ack+0x66>
-    /* let tcp_fasttmr retry sending this ACK */
-    tcp_set_flags(pcb, TF_ACK_DELAY | TF_ACK_NOW);
- 800d26a:	687b      	ldr	r3, [r7, #4]
- 800d26c:	8b5b      	ldrh	r3, [r3, #26]
- 800d26e:	f043 0303 	orr.w	r3, r3, #3
- 800d272:	b29a      	uxth	r2, r3
- 800d274:	687b      	ldr	r3, [r7, #4]
- 800d276:	835a      	strh	r2, [r3, #26]
-    LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_output: (ACK) could not allocate pbuf\n"));
-    return ERR_BUF;
- 800d278:	f06f 0301 	mvn.w	r3, #1
- 800d27c:	e023      	b.n	800d2c6 <tcp_send_empty_ack+0xae>
-  }
-  tcp_output_fill_options(pcb, p, optflags, num_sacks);
- 800d27e:	7dbb      	ldrb	r3, [r7, #22]
- 800d280:	7dfa      	ldrb	r2, [r7, #23]
- 800d282:	6939      	ldr	r1, [r7, #16]
- 800d284:	6878      	ldr	r0, [r7, #4]
- 800d286:	f7ff feed 	bl	800d064 <tcp_output_fill_options>
-  pcb->ts_lastacksent = pcb->rcv_nxt;
-#endif
-
-  LWIP_DEBUGF(TCP_OUTPUT_DEBUG,
-              ("tcp_output: sending ACK for %"U32_F"\n", pcb->rcv_nxt));
-  err = tcp_output_control_segment(pcb, p, &pcb->local_ip, &pcb->remote_ip);
- 800d28a:	687a      	ldr	r2, [r7, #4]
- 800d28c:	687b      	ldr	r3, [r7, #4]
- 800d28e:	3304      	adds	r3, #4
- 800d290:	6939      	ldr	r1, [r7, #16]
- 800d292:	6878      	ldr	r0, [r7, #4]
- 800d294:	f7ff ff24 	bl	800d0e0 <tcp_output_control_segment>
- 800d298:	4603      	mov	r3, r0
- 800d29a:	73fb      	strb	r3, [r7, #15]
-  if (err != ERR_OK) {
- 800d29c:	f997 300f 	ldrsb.w	r3, [r7, #15]
- 800d2a0:	2b00      	cmp	r3, #0
- 800d2a2:	d007      	beq.n	800d2b4 <tcp_send_empty_ack+0x9c>
-    /* let tcp_fasttmr retry sending this ACK */
-    tcp_set_flags(pcb, TF_ACK_DELAY | TF_ACK_NOW);
- 800d2a4:	687b      	ldr	r3, [r7, #4]
- 800d2a6:	8b5b      	ldrh	r3, [r3, #26]
- 800d2a8:	f043 0303 	orr.w	r3, r3, #3
- 800d2ac:	b29a      	uxth	r2, r3
- 800d2ae:	687b      	ldr	r3, [r7, #4]
- 800d2b0:	835a      	strh	r2, [r3, #26]
- 800d2b2:	e006      	b.n	800d2c2 <tcp_send_empty_ack+0xaa>
-  } else {
-    /* remove ACK flags from the PCB, as we sent an empty ACK now */
-    tcp_clear_flags(pcb, TF_ACK_DELAY | TF_ACK_NOW);
- 800d2b4:	687b      	ldr	r3, [r7, #4]
- 800d2b6:	8b5b      	ldrh	r3, [r3, #26]
- 800d2b8:	f023 0303 	bic.w	r3, r3, #3
- 800d2bc:	b29a      	uxth	r2, r3
- 800d2be:	687b      	ldr	r3, [r7, #4]
- 800d2c0:	835a      	strh	r2, [r3, #26]
-  }
-
-  return err;
- 800d2c2:	f997 300f 	ldrsb.w	r3, [r7, #15]
-}
- 800d2c6:	4618      	mov	r0, r3
- 800d2c8:	371c      	adds	r7, #28
- 800d2ca:	46bd      	mov	sp, r7
- 800d2cc:	bd90      	pop	{r4, r7, pc}
- 800d2ce:	bf00      	nop
- 800d2d0:	08013618 	.word	0x08013618
- 800d2d4:	08013e30 	.word	0x08013e30
- 800d2d8:	0801366c 	.word	0x0801366c
-
-0800d2dc <tcp_keepalive>:
- *
- * @param pcb the tcp_pcb for which to send a keepalive packet
- */
-err_t
-tcp_keepalive(struct tcp_pcb *pcb)
-{
- 800d2dc:	b590      	push	{r4, r7, lr}
- 800d2de:	b085      	sub	sp, #20
- 800d2e0:	af00      	add	r7, sp, #0
- 800d2e2:	6078      	str	r0, [r7, #4]
-  err_t err;
-  struct pbuf *p;
-  u8_t optlen = LWIP_TCP_OPT_LENGTH_SEGMENT(0, pcb);
- 800d2e4:	2300      	movs	r3, #0
- 800d2e6:	72bb      	strb	r3, [r7, #10]
-
-  LWIP_ASSERT("tcp_keepalive: invalid pcb", pcb != NULL);
- 800d2e8:	687b      	ldr	r3, [r7, #4]
- 800d2ea:	2b00      	cmp	r3, #0
- 800d2ec:	d106      	bne.n	800d2fc <tcp_keepalive+0x20>
- 800d2ee:	4b18      	ldr	r3, [pc, #96]	; (800d350 <tcp_keepalive+0x74>)
- 800d2f0:	f640 0224 	movw	r2, #2084	; 0x824
- 800d2f4:	4917      	ldr	r1, [pc, #92]	; (800d354 <tcp_keepalive+0x78>)
- 800d2f6:	4818      	ldr	r0, [pc, #96]	; (800d358 <tcp_keepalive+0x7c>)
- 800d2f8:	f003 fc66 	bl	8010bc8 <iprintf>
-  LWIP_DEBUGF(TCP_DEBUG, ("\n"));
-
-  LWIP_DEBUGF(TCP_DEBUG, ("tcp_keepalive: tcp_ticks %"U32_F"   pcb->tmr %"U32_F" pcb->keep_cnt_sent %"U16_F"\n",
-                          tcp_ticks, pcb->tmr, (u16_t)pcb->keep_cnt_sent));
-
-  p = tcp_output_alloc_header(pcb, optlen, 0, lwip_htonl(pcb->snd_nxt - 1));
- 800d2fc:	7abb      	ldrb	r3, [r7, #10]
- 800d2fe:	b29c      	uxth	r4, r3
- 800d300:	687b      	ldr	r3, [r7, #4]
- 800d302:	6d1b      	ldr	r3, [r3, #80]	; 0x50
- 800d304:	3b01      	subs	r3, #1
- 800d306:	4618      	mov	r0, r3
- 800d308:	f7f8 f935 	bl	8005576 <lwip_htonl>
- 800d30c:	4603      	mov	r3, r0
- 800d30e:	2200      	movs	r2, #0
- 800d310:	4621      	mov	r1, r4
- 800d312:	6878      	ldr	r0, [r7, #4]
- 800d314:	f7ff fe68 	bl	800cfe8 <tcp_output_alloc_header>
- 800d318:	60f8      	str	r0, [r7, #12]
-  if (p == NULL) {
- 800d31a:	68fb      	ldr	r3, [r7, #12]
- 800d31c:	2b00      	cmp	r3, #0
- 800d31e:	d102      	bne.n	800d326 <tcp_keepalive+0x4a>
-    LWIP_DEBUGF(TCP_DEBUG,
-                ("tcp_keepalive: could not allocate memory for pbuf\n"));
-    return ERR_MEM;
- 800d320:	f04f 33ff 	mov.w	r3, #4294967295
- 800d324:	e010      	b.n	800d348 <tcp_keepalive+0x6c>
-  }
-  tcp_output_fill_options(pcb, p, 0, optlen);
- 800d326:	7abb      	ldrb	r3, [r7, #10]
- 800d328:	2200      	movs	r2, #0
- 800d32a:	68f9      	ldr	r1, [r7, #12]
- 800d32c:	6878      	ldr	r0, [r7, #4]
- 800d32e:	f7ff fe99 	bl	800d064 <tcp_output_fill_options>
-  err = tcp_output_control_segment(pcb, p, &pcb->local_ip, &pcb->remote_ip);
- 800d332:	687a      	ldr	r2, [r7, #4]
- 800d334:	687b      	ldr	r3, [r7, #4]
- 800d336:	3304      	adds	r3, #4
- 800d338:	68f9      	ldr	r1, [r7, #12]
- 800d33a:	6878      	ldr	r0, [r7, #4]
- 800d33c:	f7ff fed0 	bl	800d0e0 <tcp_output_control_segment>
- 800d340:	4603      	mov	r3, r0
- 800d342:	72fb      	strb	r3, [r7, #11]
-
-  LWIP_DEBUGF(TCP_DEBUG, ("tcp_keepalive: seqno %"U32_F" ackno %"U32_F" err %d.\n",
-                          pcb->snd_nxt - 1, pcb->rcv_nxt, (int)err));
-  return err;
- 800d344:	f997 300b 	ldrsb.w	r3, [r7, #11]
-}
- 800d348:	4618      	mov	r0, r3
- 800d34a:	3714      	adds	r7, #20
- 800d34c:	46bd      	mov	sp, r7
- 800d34e:	bd90      	pop	{r4, r7, pc}
- 800d350:	08013618 	.word	0x08013618
- 800d354:	08013e50 	.word	0x08013e50
- 800d358:	0801366c 	.word	0x0801366c
-
-0800d35c <tcp_zero_window_probe>:
- *
- * @param pcb the tcp_pcb for which to send a zero-window probe packet
- */
-err_t
-tcp_zero_window_probe(struct tcp_pcb *pcb)
-{
- 800d35c:	b590      	push	{r4, r7, lr}
- 800d35e:	b08b      	sub	sp, #44	; 0x2c
- 800d360:	af00      	add	r7, sp, #0
- 800d362:	6078      	str	r0, [r7, #4]
-  struct tcp_hdr *tcphdr;
-  struct tcp_seg *seg;
-  u16_t len;
-  u8_t is_fin;
-  u32_t snd_nxt;
-  u8_t optlen = LWIP_TCP_OPT_LENGTH_SEGMENT(0, pcb);
- 800d364:	2300      	movs	r3, #0
- 800d366:	74fb      	strb	r3, [r7, #19]
-
-  LWIP_ASSERT("tcp_zero_window_probe: invalid pcb", pcb != NULL);
- 800d368:	687b      	ldr	r3, [r7, #4]
- 800d36a:	2b00      	cmp	r3, #0
- 800d36c:	d106      	bne.n	800d37c <tcp_zero_window_probe+0x20>
- 800d36e:	4b4d      	ldr	r3, [pc, #308]	; (800d4a4 <tcp_zero_window_probe+0x148>)
- 800d370:	f640 024f 	movw	r2, #2127	; 0x84f
- 800d374:	494c      	ldr	r1, [pc, #304]	; (800d4a8 <tcp_zero_window_probe+0x14c>)
- 800d376:	484d      	ldr	r0, [pc, #308]	; (800d4ac <tcp_zero_window_probe+0x150>)
- 800d378:	f003 fc26 	bl	8010bc8 <iprintf>
-              ("tcp_zero_window_probe: tcp_ticks %"U32_F
-               "   pcb->tmr %"U32_F" pcb->keep_cnt_sent %"U16_F"\n",
-               tcp_ticks, pcb->tmr, (u16_t)pcb->keep_cnt_sent));
-
-  /* Only consider unsent, persist timer should be off when there is data in-flight */
-  seg = pcb->unsent;
- 800d37c:	687b      	ldr	r3, [r7, #4]
- 800d37e:	6edb      	ldr	r3, [r3, #108]	; 0x6c
- 800d380:	627b      	str	r3, [r7, #36]	; 0x24
-  if (seg == NULL) {
- 800d382:	6a7b      	ldr	r3, [r7, #36]	; 0x24
- 800d384:	2b00      	cmp	r3, #0
- 800d386:	d101      	bne.n	800d38c <tcp_zero_window_probe+0x30>
-    /* Not expected, persist timer should be off when the send buffer is empty */
-    return ERR_OK;
- 800d388:	2300      	movs	r3, #0
- 800d38a:	e087      	b.n	800d49c <tcp_zero_window_probe+0x140>
-
-  /* increment probe count. NOTE: we record probe even if it fails
-     to actually transmit due to an error. This ensures memory exhaustion/
-     routing problem doesn't leave a zero-window pcb as an indefinite zombie.
-     RTO mechanism has similar behavior, see pcb->nrtx */
-  if (pcb->persist_probe < 0xFF) {
- 800d38c:	687b      	ldr	r3, [r7, #4]
- 800d38e:	f893 309a 	ldrb.w	r3, [r3, #154]	; 0x9a
- 800d392:	2bff      	cmp	r3, #255	; 0xff
- 800d394:	d007      	beq.n	800d3a6 <tcp_zero_window_probe+0x4a>
-    ++pcb->persist_probe;
- 800d396:	687b      	ldr	r3, [r7, #4]
- 800d398:	f893 309a 	ldrb.w	r3, [r3, #154]	; 0x9a
- 800d39c:	3301      	adds	r3, #1
- 800d39e:	b2da      	uxtb	r2, r3
- 800d3a0:	687b      	ldr	r3, [r7, #4]
- 800d3a2:	f883 209a 	strb.w	r2, [r3, #154]	; 0x9a
-  }
-
-  is_fin = ((TCPH_FLAGS(seg->tcphdr) & TCP_FIN) != 0) && (seg->len == 0);
- 800d3a6:	6a7b      	ldr	r3, [r7, #36]	; 0x24
- 800d3a8:	691b      	ldr	r3, [r3, #16]
- 800d3aa:	899b      	ldrh	r3, [r3, #12]
- 800d3ac:	b29b      	uxth	r3, r3
- 800d3ae:	4618      	mov	r0, r3
- 800d3b0:	f7f8 f8cc 	bl	800554c <lwip_htons>
- 800d3b4:	4603      	mov	r3, r0
- 800d3b6:	b2db      	uxtb	r3, r3
- 800d3b8:	f003 0301 	and.w	r3, r3, #1
- 800d3bc:	2b00      	cmp	r3, #0
- 800d3be:	d005      	beq.n	800d3cc <tcp_zero_window_probe+0x70>
- 800d3c0:	6a7b      	ldr	r3, [r7, #36]	; 0x24
- 800d3c2:	891b      	ldrh	r3, [r3, #8]
- 800d3c4:	2b00      	cmp	r3, #0
- 800d3c6:	d101      	bne.n	800d3cc <tcp_zero_window_probe+0x70>
- 800d3c8:	2301      	movs	r3, #1
- 800d3ca:	e000      	b.n	800d3ce <tcp_zero_window_probe+0x72>
- 800d3cc:	2300      	movs	r3, #0
- 800d3ce:	f887 3023 	strb.w	r3, [r7, #35]	; 0x23
-  /* we want to send one seqno: either FIN or data (no options) */
-  len = is_fin ? 0 : 1;
- 800d3d2:	f897 3023 	ldrb.w	r3, [r7, #35]	; 0x23
- 800d3d6:	2b00      	cmp	r3, #0
- 800d3d8:	bf0c      	ite	eq
- 800d3da:	2301      	moveq	r3, #1
- 800d3dc:	2300      	movne	r3, #0
- 800d3de:	b2db      	uxtb	r3, r3
- 800d3e0:	843b      	strh	r3, [r7, #32]
-
-  p = tcp_output_alloc_header(pcb, optlen, len, seg->tcphdr->seqno);
- 800d3e2:	7cfb      	ldrb	r3, [r7, #19]
- 800d3e4:	b299      	uxth	r1, r3
- 800d3e6:	6a7b      	ldr	r3, [r7, #36]	; 0x24
- 800d3e8:	691b      	ldr	r3, [r3, #16]
- 800d3ea:	685b      	ldr	r3, [r3, #4]
- 800d3ec:	8c3a      	ldrh	r2, [r7, #32]
- 800d3ee:	6878      	ldr	r0, [r7, #4]
- 800d3f0:	f7ff fdfa 	bl	800cfe8 <tcp_output_alloc_header>
- 800d3f4:	61f8      	str	r0, [r7, #28]
-  if (p == NULL) {
- 800d3f6:	69fb      	ldr	r3, [r7, #28]
- 800d3f8:	2b00      	cmp	r3, #0
- 800d3fa:	d102      	bne.n	800d402 <tcp_zero_window_probe+0xa6>
-    LWIP_DEBUGF(TCP_DEBUG, ("tcp_zero_window_probe: no memory for pbuf\n"));
-    return ERR_MEM;
- 800d3fc:	f04f 33ff 	mov.w	r3, #4294967295
- 800d400:	e04c      	b.n	800d49c <tcp_zero_window_probe+0x140>
-  }
-  tcphdr = (struct tcp_hdr *)p->payload;
- 800d402:	69fb      	ldr	r3, [r7, #28]
- 800d404:	685b      	ldr	r3, [r3, #4]
- 800d406:	61bb      	str	r3, [r7, #24]
-
-  if (is_fin) {
- 800d408:	f897 3023 	ldrb.w	r3, [r7, #35]	; 0x23
- 800d40c:	2b00      	cmp	r3, #0
- 800d40e:	d011      	beq.n	800d434 <tcp_zero_window_probe+0xd8>
-    /* FIN segment, no data */
-    TCPH_FLAGS_SET(tcphdr, TCP_ACK | TCP_FIN);
- 800d410:	69bb      	ldr	r3, [r7, #24]
- 800d412:	899b      	ldrh	r3, [r3, #12]
- 800d414:	b29b      	uxth	r3, r3
- 800d416:	b21b      	sxth	r3, r3
- 800d418:	f423 537c 	bic.w	r3, r3, #16128	; 0x3f00
- 800d41c:	b21c      	sxth	r4, r3
- 800d41e:	2011      	movs	r0, #17
- 800d420:	f7f8 f894 	bl	800554c <lwip_htons>
- 800d424:	4603      	mov	r3, r0
- 800d426:	b21b      	sxth	r3, r3
- 800d428:	4323      	orrs	r3, r4
- 800d42a:	b21b      	sxth	r3, r3
- 800d42c:	b29a      	uxth	r2, r3
- 800d42e:	69bb      	ldr	r3, [r7, #24]
- 800d430:	819a      	strh	r2, [r3, #12]
- 800d432:	e010      	b.n	800d456 <tcp_zero_window_probe+0xfa>
-  } else {
-    /* Data segment, copy in one byte from the head of the unacked queue */
-    char *d = ((char *)p->payload + TCP_HLEN);
- 800d434:	69fb      	ldr	r3, [r7, #28]
- 800d436:	685b      	ldr	r3, [r3, #4]
- 800d438:	3314      	adds	r3, #20
- 800d43a:	617b      	str	r3, [r7, #20]
-    /* Depending on whether the segment has already been sent (unacked) or not
-       (unsent), seg->p->payload points to the IP header or TCP header.
-       Ensure we copy the first TCP data byte: */
-    pbuf_copy_partial(seg->p, d, 1, seg->p->tot_len - seg->len);
- 800d43c:	6a7b      	ldr	r3, [r7, #36]	; 0x24
- 800d43e:	6858      	ldr	r0, [r3, #4]
- 800d440:	6a7b      	ldr	r3, [r7, #36]	; 0x24
- 800d442:	685b      	ldr	r3, [r3, #4]
- 800d444:	891a      	ldrh	r2, [r3, #8]
- 800d446:	6a7b      	ldr	r3, [r7, #36]	; 0x24
- 800d448:	891b      	ldrh	r3, [r3, #8]
- 800d44a:	1ad3      	subs	r3, r2, r3
- 800d44c:	b29b      	uxth	r3, r3
- 800d44e:	2201      	movs	r2, #1
- 800d450:	6979      	ldr	r1, [r7, #20]
- 800d452:	f7f9 ffa9 	bl	80073a8 <pbuf_copy_partial>
-  }
-
-  /* The byte may be acknowledged without the window being opened. */
-  snd_nxt = lwip_ntohl(seg->tcphdr->seqno) + 1;
- 800d456:	6a7b      	ldr	r3, [r7, #36]	; 0x24
- 800d458:	691b      	ldr	r3, [r3, #16]
- 800d45a:	685b      	ldr	r3, [r3, #4]
- 800d45c:	4618      	mov	r0, r3
- 800d45e:	f7f8 f88a 	bl	8005576 <lwip_htonl>
- 800d462:	4603      	mov	r3, r0
- 800d464:	3301      	adds	r3, #1
- 800d466:	60fb      	str	r3, [r7, #12]
-  if (TCP_SEQ_LT(pcb->snd_nxt, snd_nxt)) {
- 800d468:	687b      	ldr	r3, [r7, #4]
- 800d46a:	6d1a      	ldr	r2, [r3, #80]	; 0x50
- 800d46c:	68fb      	ldr	r3, [r7, #12]
- 800d46e:	1ad3      	subs	r3, r2, r3
- 800d470:	2b00      	cmp	r3, #0
- 800d472:	da02      	bge.n	800d47a <tcp_zero_window_probe+0x11e>
-    pcb->snd_nxt = snd_nxt;
- 800d474:	687b      	ldr	r3, [r7, #4]
- 800d476:	68fa      	ldr	r2, [r7, #12]
- 800d478:	651a      	str	r2, [r3, #80]	; 0x50
-  }
-  tcp_output_fill_options(pcb, p, 0, optlen);
- 800d47a:	7cfb      	ldrb	r3, [r7, #19]
- 800d47c:	2200      	movs	r2, #0
- 800d47e:	69f9      	ldr	r1, [r7, #28]
- 800d480:	6878      	ldr	r0, [r7, #4]
- 800d482:	f7ff fdef 	bl	800d064 <tcp_output_fill_options>
-
-  err = tcp_output_control_segment(pcb, p, &pcb->local_ip, &pcb->remote_ip);
- 800d486:	687a      	ldr	r2, [r7, #4]
- 800d488:	687b      	ldr	r3, [r7, #4]
- 800d48a:	3304      	adds	r3, #4
- 800d48c:	69f9      	ldr	r1, [r7, #28]
- 800d48e:	6878      	ldr	r0, [r7, #4]
- 800d490:	f7ff fe26 	bl	800d0e0 <tcp_output_control_segment>
- 800d494:	4603      	mov	r3, r0
- 800d496:	72fb      	strb	r3, [r7, #11]
-
-  LWIP_DEBUGF(TCP_DEBUG, ("tcp_zero_window_probe: seqno %"U32_F
-                          " ackno %"U32_F" err %d.\n",
-                          pcb->snd_nxt - 1, pcb->rcv_nxt, (int)err));
-  return err;
- 800d498:	f997 300b 	ldrsb.w	r3, [r7, #11]
-}
- 800d49c:	4618      	mov	r0, r3
- 800d49e:	372c      	adds	r7, #44	; 0x2c
- 800d4a0:	46bd      	mov	sp, r7
- 800d4a2:	bd90      	pop	{r4, r7, pc}
- 800d4a4:	08013618 	.word	0x08013618
- 800d4a8:	08013e6c 	.word	0x08013e6c
- 800d4ac:	0801366c 	.word	0x0801366c
-
-0800d4b0 <tcpip_tcp_timer>:
- *
- * @param arg unused argument
- */
-static void
-tcpip_tcp_timer(void *arg)
-{
- 800d4b0:	b580      	push	{r7, lr}
- 800d4b2:	b082      	sub	sp, #8
- 800d4b4:	af00      	add	r7, sp, #0
- 800d4b6:	6078      	str	r0, [r7, #4]
-  LWIP_UNUSED_ARG(arg);
-
-  /* call TCP timer handler */
-  tcp_tmr();
- 800d4b8:	f7fa f864 	bl	8007584 <tcp_tmr>
-  /* timer still needed? */
-  if (tcp_active_pcbs || tcp_tw_pcbs) {
- 800d4bc:	4b0a      	ldr	r3, [pc, #40]	; (800d4e8 <tcpip_tcp_timer+0x38>)
- 800d4be:	681b      	ldr	r3, [r3, #0]
- 800d4c0:	2b00      	cmp	r3, #0
- 800d4c2:	d103      	bne.n	800d4cc <tcpip_tcp_timer+0x1c>
- 800d4c4:	4b09      	ldr	r3, [pc, #36]	; (800d4ec <tcpip_tcp_timer+0x3c>)
- 800d4c6:	681b      	ldr	r3, [r3, #0]
- 800d4c8:	2b00      	cmp	r3, #0
- 800d4ca:	d005      	beq.n	800d4d8 <tcpip_tcp_timer+0x28>
-    /* restart timer */
-    sys_timeout(TCP_TMR_INTERVAL, tcpip_tcp_timer, NULL);
- 800d4cc:	2200      	movs	r2, #0
- 800d4ce:	4908      	ldr	r1, [pc, #32]	; (800d4f0 <tcpip_tcp_timer+0x40>)
- 800d4d0:	20fa      	movs	r0, #250	; 0xfa
- 800d4d2:	f000 f8f3 	bl	800d6bc <sys_timeout>
- 800d4d6:	e003      	b.n	800d4e0 <tcpip_tcp_timer+0x30>
-  } else {
-    /* disable timer */
-    tcpip_tcp_timer_active = 0;
- 800d4d8:	4b06      	ldr	r3, [pc, #24]	; (800d4f4 <tcpip_tcp_timer+0x44>)
- 800d4da:	2200      	movs	r2, #0
- 800d4dc:	601a      	str	r2, [r3, #0]
-  }
-}
- 800d4de:	bf00      	nop
- 800d4e0:	bf00      	nop
- 800d4e2:	3708      	adds	r7, #8
- 800d4e4:	46bd      	mov	sp, r7
- 800d4e6:	bd80      	pop	{r7, pc}
- 800d4e8:	24007b78 	.word	0x24007b78
- 800d4ec:	24007b7c 	.word	0x24007b7c
- 800d4f0:	0800d4b1 	.word	0x0800d4b1
- 800d4f4:	24007bc8 	.word	0x24007bc8
-
-0800d4f8 <tcp_timer_needed>:
- * the reason is to have the TCP timer only running when
- * there are active (or time-wait) PCBs.
- */
-void
-tcp_timer_needed(void)
-{
- 800d4f8:	b580      	push	{r7, lr}
- 800d4fa:	af00      	add	r7, sp, #0
-  LWIP_ASSERT_CORE_LOCKED();
-
-  /* timer is off but needed again? */
-  if (!tcpip_tcp_timer_active && (tcp_active_pcbs || tcp_tw_pcbs)) {
- 800d4fc:	4b0a      	ldr	r3, [pc, #40]	; (800d528 <tcp_timer_needed+0x30>)
- 800d4fe:	681b      	ldr	r3, [r3, #0]
- 800d500:	2b00      	cmp	r3, #0
- 800d502:	d10f      	bne.n	800d524 <tcp_timer_needed+0x2c>
- 800d504:	4b09      	ldr	r3, [pc, #36]	; (800d52c <tcp_timer_needed+0x34>)
- 800d506:	681b      	ldr	r3, [r3, #0]
- 800d508:	2b00      	cmp	r3, #0
- 800d50a:	d103      	bne.n	800d514 <tcp_timer_needed+0x1c>
- 800d50c:	4b08      	ldr	r3, [pc, #32]	; (800d530 <tcp_timer_needed+0x38>)
- 800d50e:	681b      	ldr	r3, [r3, #0]
- 800d510:	2b00      	cmp	r3, #0
- 800d512:	d007      	beq.n	800d524 <tcp_timer_needed+0x2c>
-    /* enable and start timer */
-    tcpip_tcp_timer_active = 1;
- 800d514:	4b04      	ldr	r3, [pc, #16]	; (800d528 <tcp_timer_needed+0x30>)
- 800d516:	2201      	movs	r2, #1
- 800d518:	601a      	str	r2, [r3, #0]
-    sys_timeout(TCP_TMR_INTERVAL, tcpip_tcp_timer, NULL);
- 800d51a:	2200      	movs	r2, #0
- 800d51c:	4905      	ldr	r1, [pc, #20]	; (800d534 <tcp_timer_needed+0x3c>)
- 800d51e:	20fa      	movs	r0, #250	; 0xfa
- 800d520:	f000 f8cc 	bl	800d6bc <sys_timeout>
-  }
-}
- 800d524:	bf00      	nop
- 800d526:	bd80      	pop	{r7, pc}
- 800d528:	24007bc8 	.word	0x24007bc8
- 800d52c:	24007b78 	.word	0x24007b78
- 800d530:	24007b7c 	.word	0x24007b7c
- 800d534:	0800d4b1 	.word	0x0800d4b1
-
-0800d538 <sys_timeout_abs>:
-#if LWIP_DEBUG_TIMERNAMES
-sys_timeout_abs(u32_t abs_time, sys_timeout_handler handler, void *arg, const char *handler_name)
-#else /* LWIP_DEBUG_TIMERNAMES */
-sys_timeout_abs(u32_t abs_time, sys_timeout_handler handler, void *arg)
-#endif
-{
- 800d538:	b580      	push	{r7, lr}
- 800d53a:	b086      	sub	sp, #24
- 800d53c:	af00      	add	r7, sp, #0
- 800d53e:	60f8      	str	r0, [r7, #12]
- 800d540:	60b9      	str	r1, [r7, #8]
- 800d542:	607a      	str	r2, [r7, #4]
-  struct sys_timeo *timeout, *t;
-
-  timeout = (struct sys_timeo *)memp_malloc(MEMP_SYS_TIMEOUT);
- 800d544:	2006      	movs	r0, #6
- 800d546:	f7f8 fd69 	bl	800601c <memp_malloc>
- 800d54a:	6138      	str	r0, [r7, #16]
-  if (timeout == NULL) {
- 800d54c:	693b      	ldr	r3, [r7, #16]
- 800d54e:	2b00      	cmp	r3, #0
- 800d550:	d109      	bne.n	800d566 <sys_timeout_abs+0x2e>
-    LWIP_ASSERT("sys_timeout: timeout != NULL, pool MEMP_SYS_TIMEOUT is empty", timeout != NULL);
- 800d552:	693b      	ldr	r3, [r7, #16]
- 800d554:	2b00      	cmp	r3, #0
- 800d556:	d151      	bne.n	800d5fc <sys_timeout_abs+0xc4>
- 800d558:	4b2a      	ldr	r3, [pc, #168]	; (800d604 <sys_timeout_abs+0xcc>)
- 800d55a:	22be      	movs	r2, #190	; 0xbe
- 800d55c:	492a      	ldr	r1, [pc, #168]	; (800d608 <sys_timeout_abs+0xd0>)
- 800d55e:	482b      	ldr	r0, [pc, #172]	; (800d60c <sys_timeout_abs+0xd4>)
- 800d560:	f003 fb32 	bl	8010bc8 <iprintf>
-    return;
- 800d564:	e04a      	b.n	800d5fc <sys_timeout_abs+0xc4>
-  }
-
-  timeout->next = NULL;
- 800d566:	693b      	ldr	r3, [r7, #16]
- 800d568:	2200      	movs	r2, #0
- 800d56a:	601a      	str	r2, [r3, #0]
-  timeout->h = handler;
- 800d56c:	693b      	ldr	r3, [r7, #16]
- 800d56e:	68ba      	ldr	r2, [r7, #8]
- 800d570:	609a      	str	r2, [r3, #8]
-  timeout->arg = arg;
- 800d572:	693b      	ldr	r3, [r7, #16]
- 800d574:	687a      	ldr	r2, [r7, #4]
- 800d576:	60da      	str	r2, [r3, #12]
-  timeout->time = abs_time;
- 800d578:	693b      	ldr	r3, [r7, #16]
- 800d57a:	68fa      	ldr	r2, [r7, #12]
- 800d57c:	605a      	str	r2, [r3, #4]
-  timeout->handler_name = handler_name;
-  LWIP_DEBUGF(TIMERS_DEBUG, ("sys_timeout: %p abs_time=%"U32_F" handler=%s arg=%p\n",
-                             (void *)timeout, abs_time, handler_name, (void *)arg));
-#endif /* LWIP_DEBUG_TIMERNAMES */
-
-  if (next_timeout == NULL) {
- 800d57e:	4b24      	ldr	r3, [pc, #144]	; (800d610 <sys_timeout_abs+0xd8>)
- 800d580:	681b      	ldr	r3, [r3, #0]
- 800d582:	2b00      	cmp	r3, #0
- 800d584:	d103      	bne.n	800d58e <sys_timeout_abs+0x56>
-    next_timeout = timeout;
- 800d586:	4a22      	ldr	r2, [pc, #136]	; (800d610 <sys_timeout_abs+0xd8>)
- 800d588:	693b      	ldr	r3, [r7, #16]
- 800d58a:	6013      	str	r3, [r2, #0]
-    return;
- 800d58c:	e037      	b.n	800d5fe <sys_timeout_abs+0xc6>
-  }
-  if (TIME_LESS_THAN(timeout->time, next_timeout->time)) {
- 800d58e:	693b      	ldr	r3, [r7, #16]
- 800d590:	685a      	ldr	r2, [r3, #4]
- 800d592:	4b1f      	ldr	r3, [pc, #124]	; (800d610 <sys_timeout_abs+0xd8>)
- 800d594:	681b      	ldr	r3, [r3, #0]
- 800d596:	685b      	ldr	r3, [r3, #4]
- 800d598:	1ad3      	subs	r3, r2, r3
- 800d59a:	0fdb      	lsrs	r3, r3, #31
- 800d59c:	f003 0301 	and.w	r3, r3, #1
- 800d5a0:	b2db      	uxtb	r3, r3
- 800d5a2:	2b00      	cmp	r3, #0
- 800d5a4:	d007      	beq.n	800d5b6 <sys_timeout_abs+0x7e>
-    timeout->next = next_timeout;
- 800d5a6:	4b1a      	ldr	r3, [pc, #104]	; (800d610 <sys_timeout_abs+0xd8>)
- 800d5a8:	681a      	ldr	r2, [r3, #0]
- 800d5aa:	693b      	ldr	r3, [r7, #16]
- 800d5ac:	601a      	str	r2, [r3, #0]
-    next_timeout = timeout;
- 800d5ae:	4a18      	ldr	r2, [pc, #96]	; (800d610 <sys_timeout_abs+0xd8>)
- 800d5b0:	693b      	ldr	r3, [r7, #16]
- 800d5b2:	6013      	str	r3, [r2, #0]
- 800d5b4:	e023      	b.n	800d5fe <sys_timeout_abs+0xc6>
-  } else {
-    for (t = next_timeout; t != NULL; t = t->next) {
- 800d5b6:	4b16      	ldr	r3, [pc, #88]	; (800d610 <sys_timeout_abs+0xd8>)
- 800d5b8:	681b      	ldr	r3, [r3, #0]
- 800d5ba:	617b      	str	r3, [r7, #20]
- 800d5bc:	e01a      	b.n	800d5f4 <sys_timeout_abs+0xbc>
-      if ((t->next == NULL) || TIME_LESS_THAN(timeout->time, t->next->time)) {
- 800d5be:	697b      	ldr	r3, [r7, #20]
- 800d5c0:	681b      	ldr	r3, [r3, #0]
- 800d5c2:	2b00      	cmp	r3, #0
- 800d5c4:	d00b      	beq.n	800d5de <sys_timeout_abs+0xa6>
- 800d5c6:	693b      	ldr	r3, [r7, #16]
- 800d5c8:	685a      	ldr	r2, [r3, #4]
- 800d5ca:	697b      	ldr	r3, [r7, #20]
- 800d5cc:	681b      	ldr	r3, [r3, #0]
- 800d5ce:	685b      	ldr	r3, [r3, #4]
- 800d5d0:	1ad3      	subs	r3, r2, r3
- 800d5d2:	0fdb      	lsrs	r3, r3, #31
- 800d5d4:	f003 0301 	and.w	r3, r3, #1
- 800d5d8:	b2db      	uxtb	r3, r3
- 800d5da:	2b00      	cmp	r3, #0
- 800d5dc:	d007      	beq.n	800d5ee <sys_timeout_abs+0xb6>
-        timeout->next = t->next;
- 800d5de:	697b      	ldr	r3, [r7, #20]
- 800d5e0:	681a      	ldr	r2, [r3, #0]
- 800d5e2:	693b      	ldr	r3, [r7, #16]
- 800d5e4:	601a      	str	r2, [r3, #0]
-        t->next = timeout;
- 800d5e6:	697b      	ldr	r3, [r7, #20]
- 800d5e8:	693a      	ldr	r2, [r7, #16]
- 800d5ea:	601a      	str	r2, [r3, #0]
-        break;
- 800d5ec:	e007      	b.n	800d5fe <sys_timeout_abs+0xc6>
-    for (t = next_timeout; t != NULL; t = t->next) {
- 800d5ee:	697b      	ldr	r3, [r7, #20]
- 800d5f0:	681b      	ldr	r3, [r3, #0]
- 800d5f2:	617b      	str	r3, [r7, #20]
- 800d5f4:	697b      	ldr	r3, [r7, #20]
- 800d5f6:	2b00      	cmp	r3, #0
- 800d5f8:	d1e1      	bne.n	800d5be <sys_timeout_abs+0x86>
- 800d5fa:	e000      	b.n	800d5fe <sys_timeout_abs+0xc6>
-    return;
- 800d5fc:	bf00      	nop
-      }
-    }
-  }
-}
- 800d5fe:	3718      	adds	r7, #24
- 800d600:	46bd      	mov	sp, r7
- 800d602:	bd80      	pop	{r7, pc}
- 800d604:	08013e90 	.word	0x08013e90
- 800d608:	08013ec4 	.word	0x08013ec4
- 800d60c:	08013f04 	.word	0x08013f04
- 800d610:	24007bc0 	.word	0x24007bc0
-
-0800d614 <lwip_cyclic_timer>:
-#if !LWIP_TESTMODE
-static
-#endif
-void
-lwip_cyclic_timer(void *arg)
-{
- 800d614:	b580      	push	{r7, lr}
- 800d616:	b086      	sub	sp, #24
- 800d618:	af00      	add	r7, sp, #0
- 800d61a:	6078      	str	r0, [r7, #4]
-  u32_t now;
-  u32_t next_timeout_time;
-  const struct lwip_cyclic_timer *cyclic = (const struct lwip_cyclic_timer *)arg;
- 800d61c:	687b      	ldr	r3, [r7, #4]
- 800d61e:	617b      	str	r3, [r7, #20]
-
-#if LWIP_DEBUG_TIMERNAMES
-  LWIP_DEBUGF(TIMERS_DEBUG, ("tcpip: %s()\n", cyclic->handler_name));
-#endif
-  cyclic->handler();
- 800d620:	697b      	ldr	r3, [r7, #20]
- 800d622:	685b      	ldr	r3, [r3, #4]
- 800d624:	4798      	blx	r3
-
-  now = sys_now();
- 800d626:	f7f7 fd43 	bl	80050b0 <sys_now>
- 800d62a:	6138      	str	r0, [r7, #16]
-  next_timeout_time = (u32_t)(current_timeout_due_time + cyclic->interval_ms);  /* overflow handled by TIME_LESS_THAN macro */ 
- 800d62c:	697b      	ldr	r3, [r7, #20]
- 800d62e:	681a      	ldr	r2, [r3, #0]
- 800d630:	4b0f      	ldr	r3, [pc, #60]	; (800d670 <lwip_cyclic_timer+0x5c>)
- 800d632:	681b      	ldr	r3, [r3, #0]
- 800d634:	4413      	add	r3, r2
- 800d636:	60fb      	str	r3, [r7, #12]
-  if (TIME_LESS_THAN(next_timeout_time, now)) {
- 800d638:	68fa      	ldr	r2, [r7, #12]
- 800d63a:	693b      	ldr	r3, [r7, #16]
- 800d63c:	1ad3      	subs	r3, r2, r3
- 800d63e:	0fdb      	lsrs	r3, r3, #31
- 800d640:	f003 0301 	and.w	r3, r3, #1
- 800d644:	b2db      	uxtb	r3, r3
- 800d646:	2b00      	cmp	r3, #0
- 800d648:	d009      	beq.n	800d65e <lwip_cyclic_timer+0x4a>
-    /* timer would immediately expire again -> "overload" -> restart without any correction */
-#if LWIP_DEBUG_TIMERNAMES
-    sys_timeout_abs((u32_t)(now + cyclic->interval_ms), lwip_cyclic_timer, arg, cyclic->handler_name);
-#else
-    sys_timeout_abs((u32_t)(now + cyclic->interval_ms), lwip_cyclic_timer, arg);
- 800d64a:	697b      	ldr	r3, [r7, #20]
- 800d64c:	681a      	ldr	r2, [r3, #0]
- 800d64e:	693b      	ldr	r3, [r7, #16]
- 800d650:	4413      	add	r3, r2
- 800d652:	687a      	ldr	r2, [r7, #4]
- 800d654:	4907      	ldr	r1, [pc, #28]	; (800d674 <lwip_cyclic_timer+0x60>)
- 800d656:	4618      	mov	r0, r3
- 800d658:	f7ff ff6e 	bl	800d538 <sys_timeout_abs>
-    sys_timeout_abs(next_timeout_time, lwip_cyclic_timer, arg, cyclic->handler_name);
-#else
-    sys_timeout_abs(next_timeout_time, lwip_cyclic_timer, arg);
-#endif
-  }
-}
- 800d65c:	e004      	b.n	800d668 <lwip_cyclic_timer+0x54>
-    sys_timeout_abs(next_timeout_time, lwip_cyclic_timer, arg);
- 800d65e:	687a      	ldr	r2, [r7, #4]
- 800d660:	4904      	ldr	r1, [pc, #16]	; (800d674 <lwip_cyclic_timer+0x60>)
- 800d662:	68f8      	ldr	r0, [r7, #12]
- 800d664:	f7ff ff68 	bl	800d538 <sys_timeout_abs>
-}
- 800d668:	bf00      	nop
- 800d66a:	3718      	adds	r7, #24
- 800d66c:	46bd      	mov	sp, r7
- 800d66e:	bd80      	pop	{r7, pc}
- 800d670:	24007bc4 	.word	0x24007bc4
- 800d674:	0800d615 	.word	0x0800d615
-
-0800d678 <sys_timeouts_init>:
-
-/** Initialize this module */
-void sys_timeouts_init(void)
-{
- 800d678:	b580      	push	{r7, lr}
- 800d67a:	b082      	sub	sp, #8
- 800d67c:	af00      	add	r7, sp, #0
-  size_t i;
-  /* tcp_tmr() at index 0 is started on demand */
-  for (i = (LWIP_TCP ? 1 : 0); i < LWIP_ARRAYSIZE(lwip_cyclic_timers); i++) {
- 800d67e:	2301      	movs	r3, #1
- 800d680:	607b      	str	r3, [r7, #4]
- 800d682:	e00e      	b.n	800d6a2 <sys_timeouts_init+0x2a>
-    /* we have to cast via size_t to get rid of const warning
-      (this is OK as cyclic_timer() casts back to const* */
-    sys_timeout(lwip_cyclic_timers[i].interval_ms, lwip_cyclic_timer, LWIP_CONST_CAST(void *, &lwip_cyclic_timers[i]));
- 800d684:	4a0b      	ldr	r2, [pc, #44]	; (800d6b4 <sys_timeouts_init+0x3c>)
- 800d686:	687b      	ldr	r3, [r7, #4]
- 800d688:	f852 0033 	ldr.w	r0, [r2, r3, lsl #3]
- 800d68c:	687b      	ldr	r3, [r7, #4]
- 800d68e:	00db      	lsls	r3, r3, #3
- 800d690:	4a08      	ldr	r2, [pc, #32]	; (800d6b4 <sys_timeouts_init+0x3c>)
- 800d692:	4413      	add	r3, r2
- 800d694:	461a      	mov	r2, r3
- 800d696:	4908      	ldr	r1, [pc, #32]	; (800d6b8 <sys_timeouts_init+0x40>)
- 800d698:	f000 f810 	bl	800d6bc <sys_timeout>
-  for (i = (LWIP_TCP ? 1 : 0); i < LWIP_ARRAYSIZE(lwip_cyclic_timers); i++) {
- 800d69c:	687b      	ldr	r3, [r7, #4]
- 800d69e:	3301      	adds	r3, #1
- 800d6a0:	607b      	str	r3, [r7, #4]
- 800d6a2:	687b      	ldr	r3, [r7, #4]
- 800d6a4:	2b02      	cmp	r3, #2
- 800d6a6:	d9ed      	bls.n	800d684 <sys_timeouts_init+0xc>
-  }
-}
- 800d6a8:	bf00      	nop
- 800d6aa:	bf00      	nop
- 800d6ac:	3708      	adds	r7, #8
- 800d6ae:	46bd      	mov	sp, r7
- 800d6b0:	bd80      	pop	{r7, pc}
- 800d6b2:	bf00      	nop
- 800d6b4:	08014d7c 	.word	0x08014d7c
- 800d6b8:	0800d615 	.word	0x0800d615
-
-0800d6bc <sys_timeout>:
-sys_timeout_debug(u32_t msecs, sys_timeout_handler handler, void *arg, const char *handler_name)
-#else /* LWIP_DEBUG_TIMERNAMES */
-void
-sys_timeout(u32_t msecs, sys_timeout_handler handler, void *arg)
-#endif /* LWIP_DEBUG_TIMERNAMES */
-{
- 800d6bc:	b580      	push	{r7, lr}
- 800d6be:	b086      	sub	sp, #24
- 800d6c0:	af00      	add	r7, sp, #0
- 800d6c2:	60f8      	str	r0, [r7, #12]
- 800d6c4:	60b9      	str	r1, [r7, #8]
- 800d6c6:	607a      	str	r2, [r7, #4]
-  u32_t next_timeout_time;
-
-  LWIP_ASSERT_CORE_LOCKED();
-
-  LWIP_ASSERT("Timeout time too long, max is LWIP_UINT32_MAX/4 msecs", msecs <= (LWIP_UINT32_MAX / 4));
- 800d6c8:	68fb      	ldr	r3, [r7, #12]
- 800d6ca:	f1b3 4f80 	cmp.w	r3, #1073741824	; 0x40000000
- 800d6ce:	d306      	bcc.n	800d6de <sys_timeout+0x22>
- 800d6d0:	4b0a      	ldr	r3, [pc, #40]	; (800d6fc <sys_timeout+0x40>)
- 800d6d2:	f240 1229 	movw	r2, #297	; 0x129
- 800d6d6:	490a      	ldr	r1, [pc, #40]	; (800d700 <sys_timeout+0x44>)
- 800d6d8:	480a      	ldr	r0, [pc, #40]	; (800d704 <sys_timeout+0x48>)
- 800d6da:	f003 fa75 	bl	8010bc8 <iprintf>
-
-  next_timeout_time = (u32_t)(sys_now() + msecs); /* overflow handled by TIME_LESS_THAN macro */ 
- 800d6de:	f7f7 fce7 	bl	80050b0 <sys_now>
- 800d6e2:	4602      	mov	r2, r0
- 800d6e4:	68fb      	ldr	r3, [r7, #12]
- 800d6e6:	4413      	add	r3, r2
- 800d6e8:	617b      	str	r3, [r7, #20]
-
-#if LWIP_DEBUG_TIMERNAMES
-  sys_timeout_abs(next_timeout_time, handler, arg, handler_name);
-#else
-  sys_timeout_abs(next_timeout_time, handler, arg);
- 800d6ea:	687a      	ldr	r2, [r7, #4]
- 800d6ec:	68b9      	ldr	r1, [r7, #8]
- 800d6ee:	6978      	ldr	r0, [r7, #20]
- 800d6f0:	f7ff ff22 	bl	800d538 <sys_timeout_abs>
-#endif
-}
- 800d6f4:	bf00      	nop
- 800d6f6:	3718      	adds	r7, #24
- 800d6f8:	46bd      	mov	sp, r7
- 800d6fa:	bd80      	pop	{r7, pc}
- 800d6fc:	08013e90 	.word	0x08013e90
- 800d700:	08013f2c 	.word	0x08013f2c
- 800d704:	08013f04 	.word	0x08013f04
-
-0800d708 <sys_check_timeouts>:
- *
- * Must be called periodically from your main loop.
- */
-void
-sys_check_timeouts(void)
-{
- 800d708:	b580      	push	{r7, lr}
- 800d70a:	b084      	sub	sp, #16
- 800d70c:	af00      	add	r7, sp, #0
-  u32_t now;
-
-  LWIP_ASSERT_CORE_LOCKED();
-
-  /* Process only timers expired at the start of the function. */
-  now = sys_now();
- 800d70e:	f7f7 fccf 	bl	80050b0 <sys_now>
- 800d712:	60f8      	str	r0, [r7, #12]
-  do {
-    struct sys_timeo *tmptimeout;
-    sys_timeout_handler handler;
-    void *arg;
-
-    PBUF_CHECK_FREE_OOSEQ();
- 800d714:	4b1a      	ldr	r3, [pc, #104]	; (800d780 <sys_check_timeouts+0x78>)
- 800d716:	781b      	ldrb	r3, [r3, #0]
- 800d718:	b2db      	uxtb	r3, r3
- 800d71a:	2b00      	cmp	r3, #0
- 800d71c:	d001      	beq.n	800d722 <sys_check_timeouts+0x1a>
- 800d71e:	f7f9 f91f 	bl	8006960 <pbuf_free_ooseq>
-
-    tmptimeout = next_timeout;
- 800d722:	4b18      	ldr	r3, [pc, #96]	; (800d784 <sys_check_timeouts+0x7c>)
- 800d724:	681b      	ldr	r3, [r3, #0]
- 800d726:	60bb      	str	r3, [r7, #8]
-    if (tmptimeout == NULL) {
- 800d728:	68bb      	ldr	r3, [r7, #8]
- 800d72a:	2b00      	cmp	r3, #0
- 800d72c:	d022      	beq.n	800d774 <sys_check_timeouts+0x6c>
-      return;
-    }
-
-    if (TIME_LESS_THAN(now, tmptimeout->time)) {
- 800d72e:	68bb      	ldr	r3, [r7, #8]
- 800d730:	685b      	ldr	r3, [r3, #4]
- 800d732:	68fa      	ldr	r2, [r7, #12]
- 800d734:	1ad3      	subs	r3, r2, r3
- 800d736:	0fdb      	lsrs	r3, r3, #31
- 800d738:	f003 0301 	and.w	r3, r3, #1
- 800d73c:	b2db      	uxtb	r3, r3
- 800d73e:	2b00      	cmp	r3, #0
- 800d740:	d11a      	bne.n	800d778 <sys_check_timeouts+0x70>
-      return;
-    }
-
-    /* Timeout has expired */
-    next_timeout = tmptimeout->next;
- 800d742:	68bb      	ldr	r3, [r7, #8]
- 800d744:	681b      	ldr	r3, [r3, #0]
- 800d746:	4a0f      	ldr	r2, [pc, #60]	; (800d784 <sys_check_timeouts+0x7c>)
- 800d748:	6013      	str	r3, [r2, #0]
-    handler = tmptimeout->h;
- 800d74a:	68bb      	ldr	r3, [r7, #8]
- 800d74c:	689b      	ldr	r3, [r3, #8]
- 800d74e:	607b      	str	r3, [r7, #4]
-    arg = tmptimeout->arg;
- 800d750:	68bb      	ldr	r3, [r7, #8]
- 800d752:	68db      	ldr	r3, [r3, #12]
- 800d754:	603b      	str	r3, [r7, #0]
-    current_timeout_due_time = tmptimeout->time;
- 800d756:	68bb      	ldr	r3, [r7, #8]
- 800d758:	685b      	ldr	r3, [r3, #4]
- 800d75a:	4a0b      	ldr	r2, [pc, #44]	; (800d788 <sys_check_timeouts+0x80>)
- 800d75c:	6013      	str	r3, [r2, #0]
-    if (handler != NULL) {
-      LWIP_DEBUGF(TIMERS_DEBUG, ("sct calling h=%s t=%"U32_F" arg=%p\n",
-                                 tmptimeout->handler_name, sys_now() - tmptimeout->time, arg));
-    }
-#endif /* LWIP_DEBUG_TIMERNAMES */
-    memp_free(MEMP_SYS_TIMEOUT, tmptimeout);
- 800d75e:	68b9      	ldr	r1, [r7, #8]
- 800d760:	2006      	movs	r0, #6
- 800d762:	f7f8 fccb 	bl	80060fc <memp_free>
-    if (handler != NULL) {
- 800d766:	687b      	ldr	r3, [r7, #4]
- 800d768:	2b00      	cmp	r3, #0
- 800d76a:	d0d3      	beq.n	800d714 <sys_check_timeouts+0xc>
-      handler(arg);
- 800d76c:	687b      	ldr	r3, [r7, #4]
- 800d76e:	6838      	ldr	r0, [r7, #0]
- 800d770:	4798      	blx	r3
-  do {
- 800d772:	e7cf      	b.n	800d714 <sys_check_timeouts+0xc>
-      return;
- 800d774:	bf00      	nop
- 800d776:	e000      	b.n	800d77a <sys_check_timeouts+0x72>
-      return;
- 800d778:	bf00      	nop
-    }
-    LWIP_TCPIP_THREAD_ALIVE();
-
-    /* Repeat until all expired timers have been called */
-  } while (1);
-}
- 800d77a:	3710      	adds	r7, #16
- 800d77c:	46bd      	mov	sp, r7
- 800d77e:	bd80      	pop	{r7, pc}
- 800d780:	24007b69 	.word	0x24007b69
- 800d784:	24007bc0 	.word	0x24007bc0
- 800d788:	24007bc4 	.word	0x24007bc4
-
-0800d78c <udp_init>:
-/**
- * Initialize this module.
- */
-void
-udp_init(void)
-{
- 800d78c:	b580      	push	{r7, lr}
- 800d78e:	af00      	add	r7, sp, #0
-#ifdef LWIP_RAND
-  udp_port = UDP_ENSURE_LOCAL_PORT_RANGE(LWIP_RAND());
- 800d790:	f002 fd66 	bl	8010260 <rand>
- 800d794:	4603      	mov	r3, r0
- 800d796:	b29b      	uxth	r3, r3
- 800d798:	f3c3 030d 	ubfx	r3, r3, #0, #14
- 800d79c:	b29b      	uxth	r3, r3
- 800d79e:	f5a3 4380 	sub.w	r3, r3, #16384	; 0x4000
- 800d7a2:	b29a      	uxth	r2, r3
- 800d7a4:	4b01      	ldr	r3, [pc, #4]	; (800d7ac <udp_init+0x20>)
- 800d7a6:	801a      	strh	r2, [r3, #0]
-#endif /* LWIP_RAND */
-}
- 800d7a8:	bf00      	nop
- 800d7aa:	bd80      	pop	{r7, pc}
- 800d7ac:	24000070 	.word	0x24000070
-
-0800d7b0 <udp_input_local_match>:
- * @param broadcast 1 if his is an IPv4 broadcast (global or subnet-only), 0 otherwise (only used for IPv4)
- * @return 1 on match, 0 otherwise
- */
-static u8_t
-udp_input_local_match(struct udp_pcb *pcb, struct netif *inp, u8_t broadcast)
-{
- 800d7b0:	b580      	push	{r7, lr}
- 800d7b2:	b084      	sub	sp, #16
- 800d7b4:	af00      	add	r7, sp, #0
- 800d7b6:	60f8      	str	r0, [r7, #12]
- 800d7b8:	60b9      	str	r1, [r7, #8]
- 800d7ba:	4613      	mov	r3, r2
- 800d7bc:	71fb      	strb	r3, [r7, #7]
-  LWIP_UNUSED_ARG(inp);       /* in IPv6 only case */
-  LWIP_UNUSED_ARG(broadcast); /* in IPv6 only case */
-
-  LWIP_ASSERT("udp_input_local_match: invalid pcb", pcb != NULL);
- 800d7be:	68fb      	ldr	r3, [r7, #12]
- 800d7c0:	2b00      	cmp	r3, #0
- 800d7c2:	d105      	bne.n	800d7d0 <udp_input_local_match+0x20>
- 800d7c4:	4b27      	ldr	r3, [pc, #156]	; (800d864 <udp_input_local_match+0xb4>)
- 800d7c6:	2287      	movs	r2, #135	; 0x87
- 800d7c8:	4927      	ldr	r1, [pc, #156]	; (800d868 <udp_input_local_match+0xb8>)
- 800d7ca:	4828      	ldr	r0, [pc, #160]	; (800d86c <udp_input_local_match+0xbc>)
- 800d7cc:	f003 f9fc 	bl	8010bc8 <iprintf>
-  LWIP_ASSERT("udp_input_local_match: invalid netif", inp != NULL);
- 800d7d0:	68bb      	ldr	r3, [r7, #8]
- 800d7d2:	2b00      	cmp	r3, #0
- 800d7d4:	d105      	bne.n	800d7e2 <udp_input_local_match+0x32>
- 800d7d6:	4b23      	ldr	r3, [pc, #140]	; (800d864 <udp_input_local_match+0xb4>)
- 800d7d8:	2288      	movs	r2, #136	; 0x88
- 800d7da:	4925      	ldr	r1, [pc, #148]	; (800d870 <udp_input_local_match+0xc0>)
- 800d7dc:	4823      	ldr	r0, [pc, #140]	; (800d86c <udp_input_local_match+0xbc>)
- 800d7de:	f003 f9f3 	bl	8010bc8 <iprintf>
-
-  /* check if PCB is bound to specific netif */
-  if ((pcb->netif_idx != NETIF_NO_INDEX) &&
- 800d7e2:	68fb      	ldr	r3, [r7, #12]
- 800d7e4:	7a1b      	ldrb	r3, [r3, #8]
- 800d7e6:	2b00      	cmp	r3, #0
- 800d7e8:	d00b      	beq.n	800d802 <udp_input_local_match+0x52>
-      (pcb->netif_idx != netif_get_index(ip_data.current_input_netif))) {
- 800d7ea:	68fb      	ldr	r3, [r7, #12]
- 800d7ec:	7a1a      	ldrb	r2, [r3, #8]
- 800d7ee:	4b21      	ldr	r3, [pc, #132]	; (800d874 <udp_input_local_match+0xc4>)
- 800d7f0:	685b      	ldr	r3, [r3, #4]
- 800d7f2:	f893 3030 	ldrb.w	r3, [r3, #48]	; 0x30
- 800d7f6:	3301      	adds	r3, #1
- 800d7f8:	b2db      	uxtb	r3, r3
-  if ((pcb->netif_idx != NETIF_NO_INDEX) &&
- 800d7fa:	429a      	cmp	r2, r3
- 800d7fc:	d001      	beq.n	800d802 <udp_input_local_match+0x52>
-    return 0;
- 800d7fe:	2300      	movs	r3, #0
- 800d800:	e02b      	b.n	800d85a <udp_input_local_match+0xaa>
-  /* Only need to check PCB if incoming IP version matches PCB IP version */
-  if (IP_ADDR_PCB_VERSION_MATCH_EXACT(pcb, ip_current_dest_addr())) {
-#if LWIP_IPV4
-    /* Special case: IPv4 broadcast: all or broadcasts in my subnet
-     * Note: broadcast variable can only be 1 if it is an IPv4 broadcast */
-    if (broadcast != 0) {
- 800d802:	79fb      	ldrb	r3, [r7, #7]
- 800d804:	2b00      	cmp	r3, #0
- 800d806:	d018      	beq.n	800d83a <udp_input_local_match+0x8a>
-#if IP_SOF_BROADCAST_RECV
-      if (ip_get_option(pcb, SOF_BROADCAST))
-#endif /* IP_SOF_BROADCAST_RECV */
-      {
-        if (ip4_addr_isany(ip_2_ip4(&pcb->local_ip)) ||
- 800d808:	68fb      	ldr	r3, [r7, #12]
- 800d80a:	2b00      	cmp	r3, #0
- 800d80c:	d013      	beq.n	800d836 <udp_input_local_match+0x86>
- 800d80e:	68fb      	ldr	r3, [r7, #12]
- 800d810:	681b      	ldr	r3, [r3, #0]
- 800d812:	2b00      	cmp	r3, #0
- 800d814:	d00f      	beq.n	800d836 <udp_input_local_match+0x86>
-            ((ip4_current_dest_addr()->addr == IPADDR_BROADCAST)) ||
- 800d816:	4b17      	ldr	r3, [pc, #92]	; (800d874 <udp_input_local_match+0xc4>)
- 800d818:	695b      	ldr	r3, [r3, #20]
-        if (ip4_addr_isany(ip_2_ip4(&pcb->local_ip)) ||
- 800d81a:	f1b3 3fff 	cmp.w	r3, #4294967295
- 800d81e:	d00a      	beq.n	800d836 <udp_input_local_match+0x86>
-            ip4_addr_netcmp(ip_2_ip4(&pcb->local_ip), ip4_current_dest_addr(), netif_ip4_netmask(inp))) {
- 800d820:	68fb      	ldr	r3, [r7, #12]
- 800d822:	681a      	ldr	r2, [r3, #0]
- 800d824:	4b13      	ldr	r3, [pc, #76]	; (800d874 <udp_input_local_match+0xc4>)
- 800d826:	695b      	ldr	r3, [r3, #20]
- 800d828:	405a      	eors	r2, r3
- 800d82a:	68bb      	ldr	r3, [r7, #8]
- 800d82c:	3308      	adds	r3, #8
- 800d82e:	681b      	ldr	r3, [r3, #0]
- 800d830:	4013      	ands	r3, r2
-            ((ip4_current_dest_addr()->addr == IPADDR_BROADCAST)) ||
- 800d832:	2b00      	cmp	r3, #0
- 800d834:	d110      	bne.n	800d858 <udp_input_local_match+0xa8>
-          return 1;
- 800d836:	2301      	movs	r3, #1
- 800d838:	e00f      	b.n	800d85a <udp_input_local_match+0xaa>
-        }
-      }
-    } else
-#endif /* LWIP_IPV4 */
-      /* Handle IPv4 and IPv6: all or exact match */
-      if (ip_addr_isany(&pcb->local_ip) || ip_addr_cmp(&pcb->local_ip, ip_current_dest_addr())) {
- 800d83a:	68fb      	ldr	r3, [r7, #12]
- 800d83c:	2b00      	cmp	r3, #0
- 800d83e:	d009      	beq.n	800d854 <udp_input_local_match+0xa4>
- 800d840:	68fb      	ldr	r3, [r7, #12]
- 800d842:	681b      	ldr	r3, [r3, #0]
- 800d844:	2b00      	cmp	r3, #0
- 800d846:	d005      	beq.n	800d854 <udp_input_local_match+0xa4>
- 800d848:	68fb      	ldr	r3, [r7, #12]
- 800d84a:	681a      	ldr	r2, [r3, #0]
- 800d84c:	4b09      	ldr	r3, [pc, #36]	; (800d874 <udp_input_local_match+0xc4>)
- 800d84e:	695b      	ldr	r3, [r3, #20]
- 800d850:	429a      	cmp	r2, r3
- 800d852:	d101      	bne.n	800d858 <udp_input_local_match+0xa8>
-        return 1;
- 800d854:	2301      	movs	r3, #1
- 800d856:	e000      	b.n	800d85a <udp_input_local_match+0xaa>
-      }
-  }
-
-  return 0;
- 800d858:	2300      	movs	r3, #0
-}
- 800d85a:	4618      	mov	r0, r3
- 800d85c:	3710      	adds	r7, #16
- 800d85e:	46bd      	mov	sp, r7
- 800d860:	bd80      	pop	{r7, pc}
- 800d862:	bf00      	nop
- 800d864:	08013f78 	.word	0x08013f78
- 800d868:	08013fa8 	.word	0x08013fa8
- 800d86c:	08013fcc 	.word	0x08013fcc
- 800d870:	08013ff4 	.word	0x08013ff4
- 800d874:	24004c10 	.word	0x24004c10
-
-0800d878 <udp_input>:
- * @param inp network interface on which the datagram was received.
- *
- */
-void
-udp_input(struct pbuf *p, struct netif *inp)
-{
- 800d878:	b590      	push	{r4, r7, lr}
- 800d87a:	b08d      	sub	sp, #52	; 0x34
- 800d87c:	af02      	add	r7, sp, #8
- 800d87e:	6078      	str	r0, [r7, #4]
- 800d880:	6039      	str	r1, [r7, #0]
-  struct udp_hdr *udphdr;
-  struct udp_pcb *pcb, *prev;
-  struct udp_pcb *uncon_pcb;
-  u16_t src, dest;
-  u8_t broadcast;
-  u8_t for_us = 0;
- 800d882:	2300      	movs	r3, #0
- 800d884:	77fb      	strb	r3, [r7, #31]
-
-  LWIP_UNUSED_ARG(inp);
-
-  LWIP_ASSERT_CORE_LOCKED();
-
-  LWIP_ASSERT("udp_input: invalid pbuf", p != NULL);
- 800d886:	687b      	ldr	r3, [r7, #4]
- 800d888:	2b00      	cmp	r3, #0
- 800d88a:	d105      	bne.n	800d898 <udp_input+0x20>
- 800d88c:	4b7c      	ldr	r3, [pc, #496]	; (800da80 <udp_input+0x208>)
- 800d88e:	22cf      	movs	r2, #207	; 0xcf
- 800d890:	497c      	ldr	r1, [pc, #496]	; (800da84 <udp_input+0x20c>)
- 800d892:	487d      	ldr	r0, [pc, #500]	; (800da88 <udp_input+0x210>)
- 800d894:	f003 f998 	bl	8010bc8 <iprintf>
-  LWIP_ASSERT("udp_input: invalid netif", inp != NULL);
- 800d898:	683b      	ldr	r3, [r7, #0]
- 800d89a:	2b00      	cmp	r3, #0
- 800d89c:	d105      	bne.n	800d8aa <udp_input+0x32>
- 800d89e:	4b78      	ldr	r3, [pc, #480]	; (800da80 <udp_input+0x208>)
- 800d8a0:	22d0      	movs	r2, #208	; 0xd0
- 800d8a2:	497a      	ldr	r1, [pc, #488]	; (800da8c <udp_input+0x214>)
- 800d8a4:	4878      	ldr	r0, [pc, #480]	; (800da88 <udp_input+0x210>)
- 800d8a6:	f003 f98f 	bl	8010bc8 <iprintf>
-  PERF_START;
-
-  UDP_STATS_INC(udp.recv);
-
-  /* Check minimum length (UDP header) */
-  if (p->len < UDP_HLEN) {
- 800d8aa:	687b      	ldr	r3, [r7, #4]
- 800d8ac:	895b      	ldrh	r3, [r3, #10]
- 800d8ae:	2b07      	cmp	r3, #7
- 800d8b0:	d803      	bhi.n	800d8ba <udp_input+0x42>
-    LWIP_DEBUGF(UDP_DEBUG,
-                ("udp_input: short UDP datagram (%"U16_F" bytes) discarded\n", p->tot_len));
-    UDP_STATS_INC(udp.lenerr);
-    UDP_STATS_INC(udp.drop);
-    MIB2_STATS_INC(mib2.udpinerrors);
-    pbuf_free(p);
- 800d8b2:	6878      	ldr	r0, [r7, #4]
- 800d8b4:	f7f9 fb8e 	bl	8006fd4 <pbuf_free>
-    goto end;
- 800d8b8:	e0de      	b.n	800da78 <udp_input+0x200>
-  }
-
-  udphdr = (struct udp_hdr *)p->payload;
- 800d8ba:	687b      	ldr	r3, [r7, #4]
- 800d8bc:	685b      	ldr	r3, [r3, #4]
- 800d8be:	617b      	str	r3, [r7, #20]
-
-  /* is broadcast packet ? */
-  broadcast = ip_addr_isbroadcast(ip_current_dest_addr(), ip_current_netif());
- 800d8c0:	4b73      	ldr	r3, [pc, #460]	; (800da90 <udp_input+0x218>)
- 800d8c2:	695b      	ldr	r3, [r3, #20]
- 800d8c4:	4a72      	ldr	r2, [pc, #456]	; (800da90 <udp_input+0x218>)
- 800d8c6:	6812      	ldr	r2, [r2, #0]
- 800d8c8:	4611      	mov	r1, r2
- 800d8ca:	4618      	mov	r0, r3
- 800d8cc:	f001 fd72 	bl	800f3b4 <ip4_addr_isbroadcast_u32>
- 800d8d0:	4603      	mov	r3, r0
- 800d8d2:	74fb      	strb	r3, [r7, #19]
-
-  LWIP_DEBUGF(UDP_DEBUG, ("udp_input: received datagram of length %"U16_F"\n", p->tot_len));
-
-  /* convert src and dest ports to host byte order */
-  src = lwip_ntohs(udphdr->src);
- 800d8d4:	697b      	ldr	r3, [r7, #20]
- 800d8d6:	881b      	ldrh	r3, [r3, #0]
- 800d8d8:	b29b      	uxth	r3, r3
- 800d8da:	4618      	mov	r0, r3
- 800d8dc:	f7f7 fe36 	bl	800554c <lwip_htons>
- 800d8e0:	4603      	mov	r3, r0
- 800d8e2:	823b      	strh	r3, [r7, #16]
-  dest = lwip_ntohs(udphdr->dest);
- 800d8e4:	697b      	ldr	r3, [r7, #20]
- 800d8e6:	885b      	ldrh	r3, [r3, #2]
- 800d8e8:	b29b      	uxth	r3, r3
- 800d8ea:	4618      	mov	r0, r3
- 800d8ec:	f7f7 fe2e 	bl	800554c <lwip_htons>
- 800d8f0:	4603      	mov	r3, r0
- 800d8f2:	81fb      	strh	r3, [r7, #14]
-  ip_addr_debug_print_val(UDP_DEBUG, *ip_current_dest_addr());
-  LWIP_DEBUGF(UDP_DEBUG, (", %"U16_F") <-- (", lwip_ntohs(udphdr->dest)));
-  ip_addr_debug_print_val(UDP_DEBUG, *ip_current_src_addr());
-  LWIP_DEBUGF(UDP_DEBUG, (", %"U16_F")\n", lwip_ntohs(udphdr->src)));
-
-  pcb = NULL;
- 800d8f4:	2300      	movs	r3, #0
- 800d8f6:	623b      	str	r3, [r7, #32]
-  prev = NULL;
- 800d8f8:	2300      	movs	r3, #0
- 800d8fa:	627b      	str	r3, [r7, #36]	; 0x24
-  uncon_pcb = NULL;
- 800d8fc:	2300      	movs	r3, #0
- 800d8fe:	61bb      	str	r3, [r7, #24]
-  /* Iterate through the UDP pcb list for a matching pcb.
-   * 'Perfect match' pcbs (connected to the remote port & ip address) are
-   * preferred. If no perfect match is found, the first unconnected pcb that
-   * matches the local port and ip address gets the datagram. */
-  for (pcb = udp_pcbs; pcb != NULL; pcb = pcb->next) {
- 800d900:	4b64      	ldr	r3, [pc, #400]	; (800da94 <udp_input+0x21c>)
- 800d902:	681b      	ldr	r3, [r3, #0]
- 800d904:	623b      	str	r3, [r7, #32]
- 800d906:	e054      	b.n	800d9b2 <udp_input+0x13a>
-    LWIP_DEBUGF(UDP_DEBUG, (", %"U16_F") <-- (", pcb->local_port));
-    ip_addr_debug_print_val(UDP_DEBUG, pcb->remote_ip);
-    LWIP_DEBUGF(UDP_DEBUG, (", %"U16_F")\n", pcb->remote_port));
-
-    /* compare PCB local addr+port to UDP destination addr+port */
-    if ((pcb->local_port == dest) &&
- 800d908:	6a3b      	ldr	r3, [r7, #32]
- 800d90a:	8a5b      	ldrh	r3, [r3, #18]
- 800d90c:	89fa      	ldrh	r2, [r7, #14]
- 800d90e:	429a      	cmp	r2, r3
- 800d910:	d14a      	bne.n	800d9a8 <udp_input+0x130>
-        (udp_input_local_match(pcb, inp, broadcast) != 0)) {
- 800d912:	7cfb      	ldrb	r3, [r7, #19]
- 800d914:	461a      	mov	r2, r3
- 800d916:	6839      	ldr	r1, [r7, #0]
- 800d918:	6a38      	ldr	r0, [r7, #32]
- 800d91a:	f7ff ff49 	bl	800d7b0 <udp_input_local_match>
- 800d91e:	4603      	mov	r3, r0
-    if ((pcb->local_port == dest) &&
- 800d920:	2b00      	cmp	r3, #0
- 800d922:	d041      	beq.n	800d9a8 <udp_input+0x130>
-      if ((pcb->flags & UDP_FLAGS_CONNECTED) == 0) {
- 800d924:	6a3b      	ldr	r3, [r7, #32]
- 800d926:	7c1b      	ldrb	r3, [r3, #16]
- 800d928:	f003 0304 	and.w	r3, r3, #4
- 800d92c:	2b00      	cmp	r3, #0
- 800d92e:	d11d      	bne.n	800d96c <udp_input+0xf4>
-        if (uncon_pcb == NULL) {
- 800d930:	69bb      	ldr	r3, [r7, #24]
- 800d932:	2b00      	cmp	r3, #0
- 800d934:	d102      	bne.n	800d93c <udp_input+0xc4>
-          /* the first unconnected matching PCB */
-          uncon_pcb = pcb;
- 800d936:	6a3b      	ldr	r3, [r7, #32]
- 800d938:	61bb      	str	r3, [r7, #24]
- 800d93a:	e017      	b.n	800d96c <udp_input+0xf4>
-#if LWIP_IPV4
-        } else if (broadcast && ip4_current_dest_addr()->addr == IPADDR_BROADCAST) {
- 800d93c:	7cfb      	ldrb	r3, [r7, #19]
- 800d93e:	2b00      	cmp	r3, #0
- 800d940:	d014      	beq.n	800d96c <udp_input+0xf4>
- 800d942:	4b53      	ldr	r3, [pc, #332]	; (800da90 <udp_input+0x218>)
- 800d944:	695b      	ldr	r3, [r3, #20]
- 800d946:	f1b3 3fff 	cmp.w	r3, #4294967295
- 800d94a:	d10f      	bne.n	800d96c <udp_input+0xf4>
-          /* global broadcast address (only valid for IPv4; match was checked before) */
-          if (!IP_IS_V4_VAL(uncon_pcb->local_ip) || !ip4_addr_cmp(ip_2_ip4(&uncon_pcb->local_ip), netif_ip4_addr(inp))) {
- 800d94c:	69bb      	ldr	r3, [r7, #24]
- 800d94e:	681a      	ldr	r2, [r3, #0]
- 800d950:	683b      	ldr	r3, [r7, #0]
- 800d952:	3304      	adds	r3, #4
- 800d954:	681b      	ldr	r3, [r3, #0]
- 800d956:	429a      	cmp	r2, r3
- 800d958:	d008      	beq.n	800d96c <udp_input+0xf4>
-            /* uncon_pcb does not match the input netif, check this pcb */
-            if (IP_IS_V4_VAL(pcb->local_ip) && ip4_addr_cmp(ip_2_ip4(&pcb->local_ip), netif_ip4_addr(inp))) {
- 800d95a:	6a3b      	ldr	r3, [r7, #32]
- 800d95c:	681a      	ldr	r2, [r3, #0]
- 800d95e:	683b      	ldr	r3, [r7, #0]
- 800d960:	3304      	adds	r3, #4
- 800d962:	681b      	ldr	r3, [r3, #0]
- 800d964:	429a      	cmp	r2, r3
- 800d966:	d101      	bne.n	800d96c <udp_input+0xf4>
-              /* better match */
-              uncon_pcb = pcb;
- 800d968:	6a3b      	ldr	r3, [r7, #32]
- 800d96a:	61bb      	str	r3, [r7, #24]
-        }
-#endif /* SO_REUSE */
-      }
-
-      /* compare PCB remote addr+port to UDP source addr+port */
-      if ((pcb->remote_port == src) &&
- 800d96c:	6a3b      	ldr	r3, [r7, #32]
- 800d96e:	8a9b      	ldrh	r3, [r3, #20]
- 800d970:	8a3a      	ldrh	r2, [r7, #16]
- 800d972:	429a      	cmp	r2, r3
- 800d974:	d118      	bne.n	800d9a8 <udp_input+0x130>
-          (ip_addr_isany_val(pcb->remote_ip) ||
- 800d976:	6a3b      	ldr	r3, [r7, #32]
- 800d978:	685b      	ldr	r3, [r3, #4]
-      if ((pcb->remote_port == src) &&
- 800d97a:	2b00      	cmp	r3, #0
- 800d97c:	d005      	beq.n	800d98a <udp_input+0x112>
-           ip_addr_cmp(&pcb->remote_ip, ip_current_src_addr()))) {
- 800d97e:	6a3b      	ldr	r3, [r7, #32]
- 800d980:	685a      	ldr	r2, [r3, #4]
- 800d982:	4b43      	ldr	r3, [pc, #268]	; (800da90 <udp_input+0x218>)
- 800d984:	691b      	ldr	r3, [r3, #16]
-          (ip_addr_isany_val(pcb->remote_ip) ||
- 800d986:	429a      	cmp	r2, r3
- 800d988:	d10e      	bne.n	800d9a8 <udp_input+0x130>
-        /* the first fully matching PCB */
-        if (prev != NULL) {
- 800d98a:	6a7b      	ldr	r3, [r7, #36]	; 0x24
- 800d98c:	2b00      	cmp	r3, #0
- 800d98e:	d014      	beq.n	800d9ba <udp_input+0x142>
-          /* move the pcb to the front of udp_pcbs so that is
-             found faster next time */
-          prev->next = pcb->next;
- 800d990:	6a3b      	ldr	r3, [r7, #32]
- 800d992:	68da      	ldr	r2, [r3, #12]
- 800d994:	6a7b      	ldr	r3, [r7, #36]	; 0x24
- 800d996:	60da      	str	r2, [r3, #12]
-          pcb->next = udp_pcbs;
- 800d998:	4b3e      	ldr	r3, [pc, #248]	; (800da94 <udp_input+0x21c>)
- 800d99a:	681a      	ldr	r2, [r3, #0]
- 800d99c:	6a3b      	ldr	r3, [r7, #32]
- 800d99e:	60da      	str	r2, [r3, #12]
-          udp_pcbs = pcb;
- 800d9a0:	4a3c      	ldr	r2, [pc, #240]	; (800da94 <udp_input+0x21c>)
- 800d9a2:	6a3b      	ldr	r3, [r7, #32]
- 800d9a4:	6013      	str	r3, [r2, #0]
-        } else {
-          UDP_STATS_INC(udp.cachehit);
-        }
-        break;
- 800d9a6:	e008      	b.n	800d9ba <udp_input+0x142>
-      }
-    }
-
-    prev = pcb;
- 800d9a8:	6a3b      	ldr	r3, [r7, #32]
- 800d9aa:	627b      	str	r3, [r7, #36]	; 0x24
-  for (pcb = udp_pcbs; pcb != NULL; pcb = pcb->next) {
- 800d9ac:	6a3b      	ldr	r3, [r7, #32]
- 800d9ae:	68db      	ldr	r3, [r3, #12]
- 800d9b0:	623b      	str	r3, [r7, #32]
- 800d9b2:	6a3b      	ldr	r3, [r7, #32]
- 800d9b4:	2b00      	cmp	r3, #0
- 800d9b6:	d1a7      	bne.n	800d908 <udp_input+0x90>
- 800d9b8:	e000      	b.n	800d9bc <udp_input+0x144>
-        break;
- 800d9ba:	bf00      	nop
-  }
-  /* no fully matching pcb found? then look for an unconnected pcb */
-  if (pcb == NULL) {
- 800d9bc:	6a3b      	ldr	r3, [r7, #32]
- 800d9be:	2b00      	cmp	r3, #0
- 800d9c0:	d101      	bne.n	800d9c6 <udp_input+0x14e>
-    pcb = uncon_pcb;
- 800d9c2:	69bb      	ldr	r3, [r7, #24]
- 800d9c4:	623b      	str	r3, [r7, #32]
-  }
-
-  /* Check checksum if this is a match or if it was directed at us. */
-  if (pcb != NULL) {
- 800d9c6:	6a3b      	ldr	r3, [r7, #32]
- 800d9c8:	2b00      	cmp	r3, #0
- 800d9ca:	d002      	beq.n	800d9d2 <udp_input+0x15a>
-    for_us = 1;
- 800d9cc:	2301      	movs	r3, #1
- 800d9ce:	77fb      	strb	r3, [r7, #31]
- 800d9d0:	e00a      	b.n	800d9e8 <udp_input+0x170>
-      for_us = netif_get_ip6_addr_match(inp, ip6_current_dest_addr()) >= 0;
-    }
-#endif /* LWIP_IPV6 */
-#if LWIP_IPV4
-    if (!ip_current_is_v6()) {
-      for_us = ip4_addr_cmp(netif_ip4_addr(inp), ip4_current_dest_addr());
- 800d9d2:	683b      	ldr	r3, [r7, #0]
- 800d9d4:	3304      	adds	r3, #4
- 800d9d6:	681a      	ldr	r2, [r3, #0]
- 800d9d8:	4b2d      	ldr	r3, [pc, #180]	; (800da90 <udp_input+0x218>)
- 800d9da:	695b      	ldr	r3, [r3, #20]
- 800d9dc:	429a      	cmp	r2, r3
- 800d9de:	bf0c      	ite	eq
- 800d9e0:	2301      	moveq	r3, #1
- 800d9e2:	2300      	movne	r3, #0
- 800d9e4:	b2db      	uxtb	r3, r3
- 800d9e6:	77fb      	strb	r3, [r7, #31]
-    }
-#endif /* LWIP_IPV4 */
-  }
-
-  if (for_us) {
- 800d9e8:	7ffb      	ldrb	r3, [r7, #31]
- 800d9ea:	2b00      	cmp	r3, #0
- 800d9ec:	d041      	beq.n	800da72 <udp_input+0x1fa>
-          }
-        }
-      }
-    }
-#endif /* CHECKSUM_CHECK_UDP */
-    if (pbuf_remove_header(p, UDP_HLEN)) {
- 800d9ee:	2108      	movs	r1, #8
- 800d9f0:	6878      	ldr	r0, [r7, #4]
- 800d9f2:	f7f9 fa69 	bl	8006ec8 <pbuf_remove_header>
- 800d9f6:	4603      	mov	r3, r0
- 800d9f8:	2b00      	cmp	r3, #0
- 800d9fa:	d00a      	beq.n	800da12 <udp_input+0x19a>
-      /* Can we cope with this failing? Just assert for now */
-      LWIP_ASSERT("pbuf_remove_header failed\n", 0);
- 800d9fc:	4b20      	ldr	r3, [pc, #128]	; (800da80 <udp_input+0x208>)
- 800d9fe:	f44f 72b8 	mov.w	r2, #368	; 0x170
- 800da02:	4925      	ldr	r1, [pc, #148]	; (800da98 <udp_input+0x220>)
- 800da04:	4820      	ldr	r0, [pc, #128]	; (800da88 <udp_input+0x210>)
- 800da06:	f003 f8df 	bl	8010bc8 <iprintf>
-      UDP_STATS_INC(udp.drop);
-      MIB2_STATS_INC(mib2.udpinerrors);
-      pbuf_free(p);
- 800da0a:	6878      	ldr	r0, [r7, #4]
- 800da0c:	f7f9 fae2 	bl	8006fd4 <pbuf_free>
-      goto end;
- 800da10:	e032      	b.n	800da78 <udp_input+0x200>
-    }
-
-    if (pcb != NULL) {
- 800da12:	6a3b      	ldr	r3, [r7, #32]
- 800da14:	2b00      	cmp	r3, #0
- 800da16:	d012      	beq.n	800da3e <udp_input+0x1c6>
-          }
-        }
-      }
-#endif /* SO_REUSE && SO_REUSE_RXTOALL */
-      /* callback */
-      if (pcb->recv != NULL) {
- 800da18:	6a3b      	ldr	r3, [r7, #32]
- 800da1a:	699b      	ldr	r3, [r3, #24]
- 800da1c:	2b00      	cmp	r3, #0
- 800da1e:	d00a      	beq.n	800da36 <udp_input+0x1be>
-        /* now the recv function is responsible for freeing p */
-        pcb->recv(pcb->recv_arg, pcb, p, ip_current_src_addr(), src);
- 800da20:	6a3b      	ldr	r3, [r7, #32]
- 800da22:	699c      	ldr	r4, [r3, #24]
- 800da24:	6a3b      	ldr	r3, [r7, #32]
- 800da26:	69d8      	ldr	r0, [r3, #28]
- 800da28:	8a3b      	ldrh	r3, [r7, #16]
- 800da2a:	9300      	str	r3, [sp, #0]
- 800da2c:	4b1b      	ldr	r3, [pc, #108]	; (800da9c <udp_input+0x224>)
- 800da2e:	687a      	ldr	r2, [r7, #4]
- 800da30:	6a39      	ldr	r1, [r7, #32]
- 800da32:	47a0      	blx	r4
-  } else {
-    pbuf_free(p);
-  }
-end:
-  PERF_STOP("udp_input");
-  return;
- 800da34:	e021      	b.n	800da7a <udp_input+0x202>
-        pbuf_free(p);
- 800da36:	6878      	ldr	r0, [r7, #4]
- 800da38:	f7f9 facc 	bl	8006fd4 <pbuf_free>
-        goto end;
- 800da3c:	e01c      	b.n	800da78 <udp_input+0x200>
-      if (!broadcast && !ip_addr_ismulticast(ip_current_dest_addr())) {
- 800da3e:	7cfb      	ldrb	r3, [r7, #19]
- 800da40:	2b00      	cmp	r3, #0
- 800da42:	d112      	bne.n	800da6a <udp_input+0x1f2>
- 800da44:	4b12      	ldr	r3, [pc, #72]	; (800da90 <udp_input+0x218>)
- 800da46:	695b      	ldr	r3, [r3, #20]
- 800da48:	f003 03f0 	and.w	r3, r3, #240	; 0xf0
- 800da4c:	2be0      	cmp	r3, #224	; 0xe0
- 800da4e:	d00c      	beq.n	800da6a <udp_input+0x1f2>
-        pbuf_header_force(p, (s16_t)(ip_current_header_tot_len() + UDP_HLEN));
- 800da50:	4b0f      	ldr	r3, [pc, #60]	; (800da90 <udp_input+0x218>)
- 800da52:	899b      	ldrh	r3, [r3, #12]
- 800da54:	3308      	adds	r3, #8
- 800da56:	b29b      	uxth	r3, r3
- 800da58:	b21b      	sxth	r3, r3
- 800da5a:	4619      	mov	r1, r3
- 800da5c:	6878      	ldr	r0, [r7, #4]
- 800da5e:	f7f9 faa6 	bl	8006fae <pbuf_header_force>
-        icmp_port_unreach(ip_current_is_v6(), p);
- 800da62:	2103      	movs	r1, #3
- 800da64:	6878      	ldr	r0, [r7, #4]
- 800da66:	f001 f93b 	bl	800ece0 <icmp_dest_unreach>
-      pbuf_free(p);
- 800da6a:	6878      	ldr	r0, [r7, #4]
- 800da6c:	f7f9 fab2 	bl	8006fd4 <pbuf_free>
-  return;
- 800da70:	e003      	b.n	800da7a <udp_input+0x202>
-    pbuf_free(p);
- 800da72:	6878      	ldr	r0, [r7, #4]
- 800da74:	f7f9 faae 	bl	8006fd4 <pbuf_free>
-  return;
- 800da78:	bf00      	nop
-  UDP_STATS_INC(udp.drop);
-  MIB2_STATS_INC(mib2.udpinerrors);
-  pbuf_free(p);
-  PERF_STOP("udp_input");
-#endif /* CHECKSUM_CHECK_UDP */
-}
- 800da7a:	372c      	adds	r7, #44	; 0x2c
- 800da7c:	46bd      	mov	sp, r7
- 800da7e:	bd90      	pop	{r4, r7, pc}
- 800da80:	08013f78 	.word	0x08013f78
- 800da84:	0801401c 	.word	0x0801401c
- 800da88:	08013fcc 	.word	0x08013fcc
- 800da8c:	08014034 	.word	0x08014034
- 800da90:	24004c10 	.word	0x24004c10
- 800da94:	24007bcc 	.word	0x24007bcc
- 800da98:	08014050 	.word	0x08014050
- 800da9c:	24004c20 	.word	0x24004c20
-
-0800daa0 <udp_netif_ip_addr_changed>:
- *
- * @param old_addr IP address of the netif before change
- * @param new_addr IP address of the netif after change
- */
-void udp_netif_ip_addr_changed(const ip_addr_t *old_addr, const ip_addr_t *new_addr)
-{
- 800daa0:	b480      	push	{r7}
- 800daa2:	b085      	sub	sp, #20
- 800daa4:	af00      	add	r7, sp, #0
- 800daa6:	6078      	str	r0, [r7, #4]
- 800daa8:	6039      	str	r1, [r7, #0]
-  struct udp_pcb *upcb;
-
-  if (!ip_addr_isany(old_addr) && !ip_addr_isany(new_addr)) {
- 800daaa:	687b      	ldr	r3, [r7, #4]
- 800daac:	2b00      	cmp	r3, #0
- 800daae:	d01e      	beq.n	800daee <udp_netif_ip_addr_changed+0x4e>
- 800dab0:	687b      	ldr	r3, [r7, #4]
- 800dab2:	681b      	ldr	r3, [r3, #0]
- 800dab4:	2b00      	cmp	r3, #0
- 800dab6:	d01a      	beq.n	800daee <udp_netif_ip_addr_changed+0x4e>
- 800dab8:	683b      	ldr	r3, [r7, #0]
- 800daba:	2b00      	cmp	r3, #0
- 800dabc:	d017      	beq.n	800daee <udp_netif_ip_addr_changed+0x4e>
- 800dabe:	683b      	ldr	r3, [r7, #0]
- 800dac0:	681b      	ldr	r3, [r3, #0]
- 800dac2:	2b00      	cmp	r3, #0
- 800dac4:	d013      	beq.n	800daee <udp_netif_ip_addr_changed+0x4e>
-    for (upcb = udp_pcbs; upcb != NULL; upcb = upcb->next) {
- 800dac6:	4b0d      	ldr	r3, [pc, #52]	; (800dafc <udp_netif_ip_addr_changed+0x5c>)
- 800dac8:	681b      	ldr	r3, [r3, #0]
- 800daca:	60fb      	str	r3, [r7, #12]
- 800dacc:	e00c      	b.n	800dae8 <udp_netif_ip_addr_changed+0x48>
-      /* PCB bound to current local interface address? */
-      if (ip_addr_cmp(&upcb->local_ip, old_addr)) {
- 800dace:	68fb      	ldr	r3, [r7, #12]
- 800dad0:	681a      	ldr	r2, [r3, #0]
- 800dad2:	687b      	ldr	r3, [r7, #4]
- 800dad4:	681b      	ldr	r3, [r3, #0]
- 800dad6:	429a      	cmp	r2, r3
- 800dad8:	d103      	bne.n	800dae2 <udp_netif_ip_addr_changed+0x42>
-        /* The PCB is bound to the old ipaddr and
-         * is set to bound to the new one instead */
-        ip_addr_copy(upcb->local_ip, *new_addr);
- 800dada:	683b      	ldr	r3, [r7, #0]
- 800dadc:	681a      	ldr	r2, [r3, #0]
- 800dade:	68fb      	ldr	r3, [r7, #12]
- 800dae0:	601a      	str	r2, [r3, #0]
-    for (upcb = udp_pcbs; upcb != NULL; upcb = upcb->next) {
- 800dae2:	68fb      	ldr	r3, [r7, #12]
- 800dae4:	68db      	ldr	r3, [r3, #12]
- 800dae6:	60fb      	str	r3, [r7, #12]
- 800dae8:	68fb      	ldr	r3, [r7, #12]
- 800daea:	2b00      	cmp	r3, #0
- 800daec:	d1ef      	bne.n	800dace <udp_netif_ip_addr_changed+0x2e>
-      }
-    }
-  }
-}
- 800daee:	bf00      	nop
- 800daf0:	3714      	adds	r7, #20
- 800daf2:	46bd      	mov	sp, r7
- 800daf4:	f85d 7b04 	ldr.w	r7, [sp], #4
- 800daf8:	4770      	bx	lr
- 800dafa:	bf00      	nop
- 800dafc:	24007bcc 	.word	0x24007bcc
-
-0800db00 <etharp_free_entry>:
-#endif /* ARP_QUEUEING */
-
-/** Clean up ARP table entries */
-static void
-etharp_free_entry(int i)
-{
- 800db00:	b580      	push	{r7, lr}
- 800db02:	b082      	sub	sp, #8
- 800db04:	af00      	add	r7, sp, #0
- 800db06:	6078      	str	r0, [r7, #4]
-  /* remove from SNMP ARP index tree */
-  mib2_remove_arp_entry(arp_table[i].netif, &arp_table[i].ipaddr);
-  /* and empty packet queue */
-  if (arp_table[i].q != NULL) {
- 800db08:	492b      	ldr	r1, [pc, #172]	; (800dbb8 <etharp_free_entry+0xb8>)
- 800db0a:	687a      	ldr	r2, [r7, #4]
- 800db0c:	4613      	mov	r3, r2
- 800db0e:	005b      	lsls	r3, r3, #1
- 800db10:	4413      	add	r3, r2
- 800db12:	00db      	lsls	r3, r3, #3
- 800db14:	440b      	add	r3, r1
- 800db16:	681b      	ldr	r3, [r3, #0]
- 800db18:	2b00      	cmp	r3, #0
- 800db1a:	d013      	beq.n	800db44 <etharp_free_entry+0x44>
-    /* remove all queued packets */
-    LWIP_DEBUGF(ETHARP_DEBUG, ("etharp_free_entry: freeing entry %"U16_F", packet queue %p.\n", (u16_t)i, (void *)(arp_table[i].q)));
-    free_etharp_q(arp_table[i].q);
- 800db1c:	4926      	ldr	r1, [pc, #152]	; (800dbb8 <etharp_free_entry+0xb8>)
- 800db1e:	687a      	ldr	r2, [r7, #4]
- 800db20:	4613      	mov	r3, r2
- 800db22:	005b      	lsls	r3, r3, #1
- 800db24:	4413      	add	r3, r2
- 800db26:	00db      	lsls	r3, r3, #3
- 800db28:	440b      	add	r3, r1
- 800db2a:	681b      	ldr	r3, [r3, #0]
- 800db2c:	4618      	mov	r0, r3
- 800db2e:	f7f9 fa51 	bl	8006fd4 <pbuf_free>
-    arp_table[i].q = NULL;
- 800db32:	4921      	ldr	r1, [pc, #132]	; (800dbb8 <etharp_free_entry+0xb8>)
- 800db34:	687a      	ldr	r2, [r7, #4]
- 800db36:	4613      	mov	r3, r2
- 800db38:	005b      	lsls	r3, r3, #1
- 800db3a:	4413      	add	r3, r2
- 800db3c:	00db      	lsls	r3, r3, #3
- 800db3e:	440b      	add	r3, r1
- 800db40:	2200      	movs	r2, #0
- 800db42:	601a      	str	r2, [r3, #0]
-  }
-  /* recycle entry for re-use */
-  arp_table[i].state = ETHARP_STATE_EMPTY;
- 800db44:	491c      	ldr	r1, [pc, #112]	; (800dbb8 <etharp_free_entry+0xb8>)
- 800db46:	687a      	ldr	r2, [r7, #4]
- 800db48:	4613      	mov	r3, r2
- 800db4a:	005b      	lsls	r3, r3, #1
- 800db4c:	4413      	add	r3, r2
- 800db4e:	00db      	lsls	r3, r3, #3
- 800db50:	440b      	add	r3, r1
- 800db52:	3314      	adds	r3, #20
- 800db54:	2200      	movs	r2, #0
- 800db56:	701a      	strb	r2, [r3, #0]
-#ifdef LWIP_DEBUG
-  /* for debugging, clean out the complete entry */
-  arp_table[i].ctime = 0;
- 800db58:	4917      	ldr	r1, [pc, #92]	; (800dbb8 <etharp_free_entry+0xb8>)
- 800db5a:	687a      	ldr	r2, [r7, #4]
- 800db5c:	4613      	mov	r3, r2
- 800db5e:	005b      	lsls	r3, r3, #1
- 800db60:	4413      	add	r3, r2
- 800db62:	00db      	lsls	r3, r3, #3
- 800db64:	440b      	add	r3, r1
- 800db66:	3312      	adds	r3, #18
- 800db68:	2200      	movs	r2, #0
- 800db6a:	801a      	strh	r2, [r3, #0]
-  arp_table[i].netif = NULL;
- 800db6c:	4912      	ldr	r1, [pc, #72]	; (800dbb8 <etharp_free_entry+0xb8>)
- 800db6e:	687a      	ldr	r2, [r7, #4]
- 800db70:	4613      	mov	r3, r2
- 800db72:	005b      	lsls	r3, r3, #1
- 800db74:	4413      	add	r3, r2
- 800db76:	00db      	lsls	r3, r3, #3
- 800db78:	440b      	add	r3, r1
- 800db7a:	3308      	adds	r3, #8
- 800db7c:	2200      	movs	r2, #0
- 800db7e:	601a      	str	r2, [r3, #0]
-  ip4_addr_set_zero(&arp_table[i].ipaddr);
- 800db80:	490d      	ldr	r1, [pc, #52]	; (800dbb8 <etharp_free_entry+0xb8>)
- 800db82:	687a      	ldr	r2, [r7, #4]
- 800db84:	4613      	mov	r3, r2
- 800db86:	005b      	lsls	r3, r3, #1
- 800db88:	4413      	add	r3, r2
- 800db8a:	00db      	lsls	r3, r3, #3
- 800db8c:	440b      	add	r3, r1
- 800db8e:	3304      	adds	r3, #4
- 800db90:	2200      	movs	r2, #0
- 800db92:	601a      	str	r2, [r3, #0]
-  arp_table[i].ethaddr = ethzero;
- 800db94:	4908      	ldr	r1, [pc, #32]	; (800dbb8 <etharp_free_entry+0xb8>)
- 800db96:	687a      	ldr	r2, [r7, #4]
- 800db98:	4613      	mov	r3, r2
- 800db9a:	005b      	lsls	r3, r3, #1
- 800db9c:	4413      	add	r3, r2
- 800db9e:	00db      	lsls	r3, r3, #3
- 800dba0:	440b      	add	r3, r1
- 800dba2:	3308      	adds	r3, #8
- 800dba4:	4a05      	ldr	r2, [pc, #20]	; (800dbbc <etharp_free_entry+0xbc>)
- 800dba6:	3304      	adds	r3, #4
- 800dba8:	6810      	ldr	r0, [r2, #0]
- 800dbaa:	6018      	str	r0, [r3, #0]
- 800dbac:	8892      	ldrh	r2, [r2, #4]
- 800dbae:	809a      	strh	r2, [r3, #4]
-#endif /* LWIP_DEBUG */
-}
- 800dbb0:	bf00      	nop
- 800dbb2:	3708      	adds	r7, #8
- 800dbb4:	46bd      	mov	sp, r7
- 800dbb6:	bd80      	pop	{r7, pc}
- 800dbb8:	24007bd0 	.word	0x24007bd0
- 800dbbc:	08014da0 	.word	0x08014da0
-
-0800dbc0 <etharp_tmr>:
- * This function should be called every ARP_TMR_INTERVAL milliseconds (1 second),
- * in order to expire entries in the ARP table.
- */
-void
-etharp_tmr(void)
-{
- 800dbc0:	b580      	push	{r7, lr}
- 800dbc2:	b082      	sub	sp, #8
- 800dbc4:	af00      	add	r7, sp, #0
-  int i;
-
-  LWIP_DEBUGF(ETHARP_DEBUG, ("etharp_timer\n"));
-  /* remove expired entries from the ARP table */
-  for (i = 0; i < ARP_TABLE_SIZE; ++i) {
- 800dbc6:	2300      	movs	r3, #0
- 800dbc8:	607b      	str	r3, [r7, #4]
- 800dbca:	e096      	b.n	800dcfa <etharp_tmr+0x13a>
-    u8_t state = arp_table[i].state;
- 800dbcc:	494f      	ldr	r1, [pc, #316]	; (800dd0c <etharp_tmr+0x14c>)
- 800dbce:	687a      	ldr	r2, [r7, #4]
- 800dbd0:	4613      	mov	r3, r2
- 800dbd2:	005b      	lsls	r3, r3, #1
- 800dbd4:	4413      	add	r3, r2
- 800dbd6:	00db      	lsls	r3, r3, #3
- 800dbd8:	440b      	add	r3, r1
- 800dbda:	3314      	adds	r3, #20
- 800dbdc:	781b      	ldrb	r3, [r3, #0]
- 800dbde:	70fb      	strb	r3, [r7, #3]
-    if (state != ETHARP_STATE_EMPTY
- 800dbe0:	78fb      	ldrb	r3, [r7, #3]
- 800dbe2:	2b00      	cmp	r3, #0
- 800dbe4:	f000 8086 	beq.w	800dcf4 <etharp_tmr+0x134>
-#if ETHARP_SUPPORT_STATIC_ENTRIES
-        && (state != ETHARP_STATE_STATIC)
-#endif /* ETHARP_SUPPORT_STATIC_ENTRIES */
-       ) {
-      arp_table[i].ctime++;
- 800dbe8:	4948      	ldr	r1, [pc, #288]	; (800dd0c <etharp_tmr+0x14c>)
- 800dbea:	687a      	ldr	r2, [r7, #4]
- 800dbec:	4613      	mov	r3, r2
- 800dbee:	005b      	lsls	r3, r3, #1
- 800dbf0:	4413      	add	r3, r2
- 800dbf2:	00db      	lsls	r3, r3, #3
- 800dbf4:	440b      	add	r3, r1
- 800dbf6:	3312      	adds	r3, #18
- 800dbf8:	881b      	ldrh	r3, [r3, #0]
- 800dbfa:	3301      	adds	r3, #1
- 800dbfc:	b298      	uxth	r0, r3
- 800dbfe:	4943      	ldr	r1, [pc, #268]	; (800dd0c <etharp_tmr+0x14c>)
- 800dc00:	687a      	ldr	r2, [r7, #4]
- 800dc02:	4613      	mov	r3, r2
- 800dc04:	005b      	lsls	r3, r3, #1
- 800dc06:	4413      	add	r3, r2
- 800dc08:	00db      	lsls	r3, r3, #3
- 800dc0a:	440b      	add	r3, r1
- 800dc0c:	3312      	adds	r3, #18
- 800dc0e:	4602      	mov	r2, r0
- 800dc10:	801a      	strh	r2, [r3, #0]
-      if ((arp_table[i].ctime >= ARP_MAXAGE) ||
- 800dc12:	493e      	ldr	r1, [pc, #248]	; (800dd0c <etharp_tmr+0x14c>)
- 800dc14:	687a      	ldr	r2, [r7, #4]
- 800dc16:	4613      	mov	r3, r2
- 800dc18:	005b      	lsls	r3, r3, #1
- 800dc1a:	4413      	add	r3, r2
- 800dc1c:	00db      	lsls	r3, r3, #3
- 800dc1e:	440b      	add	r3, r1
- 800dc20:	3312      	adds	r3, #18
- 800dc22:	881b      	ldrh	r3, [r3, #0]
- 800dc24:	f5b3 7f96 	cmp.w	r3, #300	; 0x12c
- 800dc28:	d215      	bcs.n	800dc56 <etharp_tmr+0x96>
-          ((arp_table[i].state == ETHARP_STATE_PENDING)  &&
- 800dc2a:	4938      	ldr	r1, [pc, #224]	; (800dd0c <etharp_tmr+0x14c>)
- 800dc2c:	687a      	ldr	r2, [r7, #4]
- 800dc2e:	4613      	mov	r3, r2
- 800dc30:	005b      	lsls	r3, r3, #1
- 800dc32:	4413      	add	r3, r2
- 800dc34:	00db      	lsls	r3, r3, #3
- 800dc36:	440b      	add	r3, r1
- 800dc38:	3314      	adds	r3, #20
- 800dc3a:	781b      	ldrb	r3, [r3, #0]
-      if ((arp_table[i].ctime >= ARP_MAXAGE) ||
- 800dc3c:	2b01      	cmp	r3, #1
- 800dc3e:	d10e      	bne.n	800dc5e <etharp_tmr+0x9e>
-           (arp_table[i].ctime >= ARP_MAXPENDING))) {
- 800dc40:	4932      	ldr	r1, [pc, #200]	; (800dd0c <etharp_tmr+0x14c>)
- 800dc42:	687a      	ldr	r2, [r7, #4]
- 800dc44:	4613      	mov	r3, r2
- 800dc46:	005b      	lsls	r3, r3, #1
- 800dc48:	4413      	add	r3, r2
- 800dc4a:	00db      	lsls	r3, r3, #3
- 800dc4c:	440b      	add	r3, r1
- 800dc4e:	3312      	adds	r3, #18
- 800dc50:	881b      	ldrh	r3, [r3, #0]
-          ((arp_table[i].state == ETHARP_STATE_PENDING)  &&
- 800dc52:	2b04      	cmp	r3, #4
- 800dc54:	d903      	bls.n	800dc5e <etharp_tmr+0x9e>
-        /* pending or stable entry has become old! */
-        LWIP_DEBUGF(ETHARP_DEBUG, ("etharp_timer: expired %s entry %d.\n",
-                                   arp_table[i].state >= ETHARP_STATE_STABLE ? "stable" : "pending", i));
-        /* clean up entries that have just been expired */
-        etharp_free_entry(i);
- 800dc56:	6878      	ldr	r0, [r7, #4]
- 800dc58:	f7ff ff52 	bl	800db00 <etharp_free_entry>
- 800dc5c:	e04a      	b.n	800dcf4 <etharp_tmr+0x134>
-      } else if (arp_table[i].state == ETHARP_STATE_STABLE_REREQUESTING_1) {
- 800dc5e:	492b      	ldr	r1, [pc, #172]	; (800dd0c <etharp_tmr+0x14c>)
- 800dc60:	687a      	ldr	r2, [r7, #4]
- 800dc62:	4613      	mov	r3, r2
- 800dc64:	005b      	lsls	r3, r3, #1
- 800dc66:	4413      	add	r3, r2
- 800dc68:	00db      	lsls	r3, r3, #3
- 800dc6a:	440b      	add	r3, r1
- 800dc6c:	3314      	adds	r3, #20
- 800dc6e:	781b      	ldrb	r3, [r3, #0]
- 800dc70:	2b03      	cmp	r3, #3
- 800dc72:	d10a      	bne.n	800dc8a <etharp_tmr+0xca>
-        /* Don't send more than one request every 2 seconds. */
-        arp_table[i].state = ETHARP_STATE_STABLE_REREQUESTING_2;
- 800dc74:	4925      	ldr	r1, [pc, #148]	; (800dd0c <etharp_tmr+0x14c>)
- 800dc76:	687a      	ldr	r2, [r7, #4]
- 800dc78:	4613      	mov	r3, r2
- 800dc7a:	005b      	lsls	r3, r3, #1
- 800dc7c:	4413      	add	r3, r2
- 800dc7e:	00db      	lsls	r3, r3, #3
- 800dc80:	440b      	add	r3, r1
- 800dc82:	3314      	adds	r3, #20
- 800dc84:	2204      	movs	r2, #4
- 800dc86:	701a      	strb	r2, [r3, #0]
- 800dc88:	e034      	b.n	800dcf4 <etharp_tmr+0x134>
-      } else if (arp_table[i].state == ETHARP_STATE_STABLE_REREQUESTING_2) {
- 800dc8a:	4920      	ldr	r1, [pc, #128]	; (800dd0c <etharp_tmr+0x14c>)
- 800dc8c:	687a      	ldr	r2, [r7, #4]
- 800dc8e:	4613      	mov	r3, r2
- 800dc90:	005b      	lsls	r3, r3, #1
- 800dc92:	4413      	add	r3, r2
- 800dc94:	00db      	lsls	r3, r3, #3
- 800dc96:	440b      	add	r3, r1
- 800dc98:	3314      	adds	r3, #20
- 800dc9a:	781b      	ldrb	r3, [r3, #0]
- 800dc9c:	2b04      	cmp	r3, #4
- 800dc9e:	d10a      	bne.n	800dcb6 <etharp_tmr+0xf6>
-        /* Reset state to stable, so that the next transmitted packet will
-           re-send an ARP request. */
-        arp_table[i].state = ETHARP_STATE_STABLE;
- 800dca0:	491a      	ldr	r1, [pc, #104]	; (800dd0c <etharp_tmr+0x14c>)
- 800dca2:	687a      	ldr	r2, [r7, #4]
- 800dca4:	4613      	mov	r3, r2
- 800dca6:	005b      	lsls	r3, r3, #1
- 800dca8:	4413      	add	r3, r2
- 800dcaa:	00db      	lsls	r3, r3, #3
- 800dcac:	440b      	add	r3, r1
- 800dcae:	3314      	adds	r3, #20
- 800dcb0:	2202      	movs	r2, #2
- 800dcb2:	701a      	strb	r2, [r3, #0]
- 800dcb4:	e01e      	b.n	800dcf4 <etharp_tmr+0x134>
-      } else if (arp_table[i].state == ETHARP_STATE_PENDING) {
- 800dcb6:	4915      	ldr	r1, [pc, #84]	; (800dd0c <etharp_tmr+0x14c>)
- 800dcb8:	687a      	ldr	r2, [r7, #4]
- 800dcba:	4613      	mov	r3, r2
- 800dcbc:	005b      	lsls	r3, r3, #1
- 800dcbe:	4413      	add	r3, r2
- 800dcc0:	00db      	lsls	r3, r3, #3
- 800dcc2:	440b      	add	r3, r1
- 800dcc4:	3314      	adds	r3, #20
- 800dcc6:	781b      	ldrb	r3, [r3, #0]
- 800dcc8:	2b01      	cmp	r3, #1
- 800dcca:	d113      	bne.n	800dcf4 <etharp_tmr+0x134>
-        /* still pending, resend an ARP query */
-        etharp_request(arp_table[i].netif, &arp_table[i].ipaddr);
- 800dccc:	490f      	ldr	r1, [pc, #60]	; (800dd0c <etharp_tmr+0x14c>)
- 800dcce:	687a      	ldr	r2, [r7, #4]
- 800dcd0:	4613      	mov	r3, r2
- 800dcd2:	005b      	lsls	r3, r3, #1
- 800dcd4:	4413      	add	r3, r2
- 800dcd6:	00db      	lsls	r3, r3, #3
- 800dcd8:	440b      	add	r3, r1
- 800dcda:	3308      	adds	r3, #8
- 800dcdc:	6818      	ldr	r0, [r3, #0]
- 800dcde:	687a      	ldr	r2, [r7, #4]
- 800dce0:	4613      	mov	r3, r2
- 800dce2:	005b      	lsls	r3, r3, #1
- 800dce4:	4413      	add	r3, r2
- 800dce6:	00db      	lsls	r3, r3, #3
- 800dce8:	4a08      	ldr	r2, [pc, #32]	; (800dd0c <etharp_tmr+0x14c>)
- 800dcea:	4413      	add	r3, r2
- 800dcec:	3304      	adds	r3, #4
- 800dcee:	4619      	mov	r1, r3
- 800dcf0:	f000 fe6e 	bl	800e9d0 <etharp_request>
-  for (i = 0; i < ARP_TABLE_SIZE; ++i) {
- 800dcf4:	687b      	ldr	r3, [r7, #4]
- 800dcf6:	3301      	adds	r3, #1
- 800dcf8:	607b      	str	r3, [r7, #4]
- 800dcfa:	687b      	ldr	r3, [r7, #4]
- 800dcfc:	2b09      	cmp	r3, #9
- 800dcfe:	f77f af65 	ble.w	800dbcc <etharp_tmr+0xc>
-      }
-    }
-  }
-}
- 800dd02:	bf00      	nop
- 800dd04:	bf00      	nop
- 800dd06:	3708      	adds	r7, #8
- 800dd08:	46bd      	mov	sp, r7
- 800dd0a:	bd80      	pop	{r7, pc}
- 800dd0c:	24007bd0 	.word	0x24007bd0
-
-0800dd10 <etharp_find_entry>:
- * @return The ARP entry index that matched or is created, ERR_MEM if no
- * entry is found or could be recycled.
- */
-static s16_t
-etharp_find_entry(const ip4_addr_t *ipaddr, u8_t flags, struct netif *netif)
-{
- 800dd10:	b580      	push	{r7, lr}
- 800dd12:	b08a      	sub	sp, #40	; 0x28
- 800dd14:	af00      	add	r7, sp, #0
- 800dd16:	60f8      	str	r0, [r7, #12]
- 800dd18:	460b      	mov	r3, r1
- 800dd1a:	607a      	str	r2, [r7, #4]
- 800dd1c:	72fb      	strb	r3, [r7, #11]
-  s16_t old_pending = ARP_TABLE_SIZE, old_stable = ARP_TABLE_SIZE;
- 800dd1e:	230a      	movs	r3, #10
- 800dd20:	843b      	strh	r3, [r7, #32]
- 800dd22:	230a      	movs	r3, #10
- 800dd24:	847b      	strh	r3, [r7, #34]	; 0x22
-  s16_t empty = ARP_TABLE_SIZE;
- 800dd26:	230a      	movs	r3, #10
- 800dd28:	84bb      	strh	r3, [r7, #36]	; 0x24
-  s16_t i = 0;
- 800dd2a:	2300      	movs	r3, #0
- 800dd2c:	84fb      	strh	r3, [r7, #38]	; 0x26
-  /* oldest entry with packets on queue */
-  s16_t old_queue = ARP_TABLE_SIZE;
- 800dd2e:	230a      	movs	r3, #10
- 800dd30:	83fb      	strh	r3, [r7, #30]
-  /* its age */
-  u16_t age_queue = 0, age_pending = 0, age_stable = 0;
- 800dd32:	2300      	movs	r3, #0
- 800dd34:	83bb      	strh	r3, [r7, #28]
- 800dd36:	2300      	movs	r3, #0
- 800dd38:	837b      	strh	r3, [r7, #26]
- 800dd3a:	2300      	movs	r3, #0
- 800dd3c:	833b      	strh	r3, [r7, #24]
-   * 4) remember the oldest pending entry with queued packets (if any)
-   * 5) search for a matching IP entry, either pending or stable
-   *    until 5 matches, or all entries are searched for.
-   */
-
-  for (i = 0; i < ARP_TABLE_SIZE; ++i) {
- 800dd3e:	2300      	movs	r3, #0
- 800dd40:	84fb      	strh	r3, [r7, #38]	; 0x26
- 800dd42:	e0ae      	b.n	800dea2 <etharp_find_entry+0x192>
-    u8_t state = arp_table[i].state;
- 800dd44:	f9b7 2026 	ldrsh.w	r2, [r7, #38]	; 0x26
- 800dd48:	49a6      	ldr	r1, [pc, #664]	; (800dfe4 <etharp_find_entry+0x2d4>)
- 800dd4a:	4613      	mov	r3, r2
- 800dd4c:	005b      	lsls	r3, r3, #1
- 800dd4e:	4413      	add	r3, r2
- 800dd50:	00db      	lsls	r3, r3, #3
- 800dd52:	440b      	add	r3, r1
- 800dd54:	3314      	adds	r3, #20
- 800dd56:	781b      	ldrb	r3, [r3, #0]
- 800dd58:	75fb      	strb	r3, [r7, #23]
-    /* no empty entry found yet and now we do find one? */
-    if ((empty == ARP_TABLE_SIZE) && (state == ETHARP_STATE_EMPTY)) {
- 800dd5a:	f9b7 3024 	ldrsh.w	r3, [r7, #36]	; 0x24
- 800dd5e:	2b0a      	cmp	r3, #10
- 800dd60:	d105      	bne.n	800dd6e <etharp_find_entry+0x5e>
- 800dd62:	7dfb      	ldrb	r3, [r7, #23]
- 800dd64:	2b00      	cmp	r3, #0
- 800dd66:	d102      	bne.n	800dd6e <etharp_find_entry+0x5e>
-      LWIP_DEBUGF(ETHARP_DEBUG, ("etharp_find_entry: found empty entry %d\n", (int)i));
-      /* remember first empty entry */
-      empty = i;
- 800dd68:	8cfb      	ldrh	r3, [r7, #38]	; 0x26
- 800dd6a:	84bb      	strh	r3, [r7, #36]	; 0x24
- 800dd6c:	e095      	b.n	800de9a <etharp_find_entry+0x18a>
-    } else if (state != ETHARP_STATE_EMPTY) {
- 800dd6e:	7dfb      	ldrb	r3, [r7, #23]
- 800dd70:	2b00      	cmp	r3, #0
- 800dd72:	f000 8092 	beq.w	800de9a <etharp_find_entry+0x18a>
-      LWIP_ASSERT("state == ETHARP_STATE_PENDING || state >= ETHARP_STATE_STABLE",
- 800dd76:	7dfb      	ldrb	r3, [r7, #23]
- 800dd78:	2b01      	cmp	r3, #1
- 800dd7a:	d009      	beq.n	800dd90 <etharp_find_entry+0x80>
- 800dd7c:	7dfb      	ldrb	r3, [r7, #23]
- 800dd7e:	2b01      	cmp	r3, #1
- 800dd80:	d806      	bhi.n	800dd90 <etharp_find_entry+0x80>
- 800dd82:	4b99      	ldr	r3, [pc, #612]	; (800dfe8 <etharp_find_entry+0x2d8>)
- 800dd84:	f240 1223 	movw	r2, #291	; 0x123
- 800dd88:	4998      	ldr	r1, [pc, #608]	; (800dfec <etharp_find_entry+0x2dc>)
- 800dd8a:	4899      	ldr	r0, [pc, #612]	; (800dff0 <etharp_find_entry+0x2e0>)
- 800dd8c:	f002 ff1c 	bl	8010bc8 <iprintf>
-                  state == ETHARP_STATE_PENDING || state >= ETHARP_STATE_STABLE);
-      /* if given, does IP address match IP address in ARP entry? */
-      if (ipaddr && ip4_addr_cmp(ipaddr, &arp_table[i].ipaddr)
- 800dd90:	68fb      	ldr	r3, [r7, #12]
- 800dd92:	2b00      	cmp	r3, #0
- 800dd94:	d020      	beq.n	800ddd8 <etharp_find_entry+0xc8>
- 800dd96:	68fb      	ldr	r3, [r7, #12]
- 800dd98:	6819      	ldr	r1, [r3, #0]
- 800dd9a:	f9b7 2026 	ldrsh.w	r2, [r7, #38]	; 0x26
- 800dd9e:	4891      	ldr	r0, [pc, #580]	; (800dfe4 <etharp_find_entry+0x2d4>)
- 800dda0:	4613      	mov	r3, r2
- 800dda2:	005b      	lsls	r3, r3, #1
- 800dda4:	4413      	add	r3, r2
- 800dda6:	00db      	lsls	r3, r3, #3
- 800dda8:	4403      	add	r3, r0
- 800ddaa:	3304      	adds	r3, #4
- 800ddac:	681b      	ldr	r3, [r3, #0]
- 800ddae:	4299      	cmp	r1, r3
- 800ddb0:	d112      	bne.n	800ddd8 <etharp_find_entry+0xc8>
-#if ETHARP_TABLE_MATCH_NETIF
-          && ((netif == NULL) || (netif == arp_table[i].netif))
- 800ddb2:	687b      	ldr	r3, [r7, #4]
- 800ddb4:	2b00      	cmp	r3, #0
- 800ddb6:	d00c      	beq.n	800ddd2 <etharp_find_entry+0xc2>
- 800ddb8:	f9b7 2026 	ldrsh.w	r2, [r7, #38]	; 0x26
- 800ddbc:	4989      	ldr	r1, [pc, #548]	; (800dfe4 <etharp_find_entry+0x2d4>)
- 800ddbe:	4613      	mov	r3, r2
- 800ddc0:	005b      	lsls	r3, r3, #1
- 800ddc2:	4413      	add	r3, r2
- 800ddc4:	00db      	lsls	r3, r3, #3
- 800ddc6:	440b      	add	r3, r1
- 800ddc8:	3308      	adds	r3, #8
- 800ddca:	681b      	ldr	r3, [r3, #0]
- 800ddcc:	687a      	ldr	r2, [r7, #4]
- 800ddce:	429a      	cmp	r2, r3
- 800ddd0:	d102      	bne.n	800ddd8 <etharp_find_entry+0xc8>
-#endif /* ETHARP_TABLE_MATCH_NETIF */
-         ) {
-        LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_find_entry: found matching entry %d\n", (int)i));
-        /* found exact IP address match, simply bail out */
-        return i;
- 800ddd2:	f9b7 3026 	ldrsh.w	r3, [r7, #38]	; 0x26
- 800ddd6:	e100      	b.n	800dfda <etharp_find_entry+0x2ca>
-      }
-      /* pending entry? */
-      if (state == ETHARP_STATE_PENDING) {
- 800ddd8:	7dfb      	ldrb	r3, [r7, #23]
- 800ddda:	2b01      	cmp	r3, #1
- 800dddc:	d140      	bne.n	800de60 <etharp_find_entry+0x150>
-        /* pending with queued packets? */
-        if (arp_table[i].q != NULL) {
- 800ddde:	f9b7 2026 	ldrsh.w	r2, [r7, #38]	; 0x26
- 800dde2:	4980      	ldr	r1, [pc, #512]	; (800dfe4 <etharp_find_entry+0x2d4>)
- 800dde4:	4613      	mov	r3, r2
- 800dde6:	005b      	lsls	r3, r3, #1
- 800dde8:	4413      	add	r3, r2
- 800ddea:	00db      	lsls	r3, r3, #3
- 800ddec:	440b      	add	r3, r1
- 800ddee:	681b      	ldr	r3, [r3, #0]
- 800ddf0:	2b00      	cmp	r3, #0
- 800ddf2:	d01a      	beq.n	800de2a <etharp_find_entry+0x11a>
-          if (arp_table[i].ctime >= age_queue) {
- 800ddf4:	f9b7 2026 	ldrsh.w	r2, [r7, #38]	; 0x26
- 800ddf8:	497a      	ldr	r1, [pc, #488]	; (800dfe4 <etharp_find_entry+0x2d4>)
- 800ddfa:	4613      	mov	r3, r2
- 800ddfc:	005b      	lsls	r3, r3, #1
- 800ddfe:	4413      	add	r3, r2
- 800de00:	00db      	lsls	r3, r3, #3
- 800de02:	440b      	add	r3, r1
- 800de04:	3312      	adds	r3, #18
- 800de06:	881b      	ldrh	r3, [r3, #0]
- 800de08:	8bba      	ldrh	r2, [r7, #28]
- 800de0a:	429a      	cmp	r2, r3
- 800de0c:	d845      	bhi.n	800de9a <etharp_find_entry+0x18a>
-            old_queue = i;
- 800de0e:	8cfb      	ldrh	r3, [r7, #38]	; 0x26
- 800de10:	83fb      	strh	r3, [r7, #30]
-            age_queue = arp_table[i].ctime;
- 800de12:	f9b7 2026 	ldrsh.w	r2, [r7, #38]	; 0x26
- 800de16:	4973      	ldr	r1, [pc, #460]	; (800dfe4 <etharp_find_entry+0x2d4>)
- 800de18:	4613      	mov	r3, r2
- 800de1a:	005b      	lsls	r3, r3, #1
- 800de1c:	4413      	add	r3, r2
- 800de1e:	00db      	lsls	r3, r3, #3
- 800de20:	440b      	add	r3, r1
- 800de22:	3312      	adds	r3, #18
- 800de24:	881b      	ldrh	r3, [r3, #0]
- 800de26:	83bb      	strh	r3, [r7, #28]
- 800de28:	e037      	b.n	800de9a <etharp_find_entry+0x18a>
-          }
-        } else
-          /* pending without queued packets? */
-        {
-          if (arp_table[i].ctime >= age_pending) {
- 800de2a:	f9b7 2026 	ldrsh.w	r2, [r7, #38]	; 0x26
- 800de2e:	496d      	ldr	r1, [pc, #436]	; (800dfe4 <etharp_find_entry+0x2d4>)
- 800de30:	4613      	mov	r3, r2
- 800de32:	005b      	lsls	r3, r3, #1
- 800de34:	4413      	add	r3, r2
- 800de36:	00db      	lsls	r3, r3, #3
- 800de38:	440b      	add	r3, r1
- 800de3a:	3312      	adds	r3, #18
- 800de3c:	881b      	ldrh	r3, [r3, #0]
- 800de3e:	8b7a      	ldrh	r2, [r7, #26]
- 800de40:	429a      	cmp	r2, r3
- 800de42:	d82a      	bhi.n	800de9a <etharp_find_entry+0x18a>
-            old_pending = i;
- 800de44:	8cfb      	ldrh	r3, [r7, #38]	; 0x26
- 800de46:	843b      	strh	r3, [r7, #32]
-            age_pending = arp_table[i].ctime;
- 800de48:	f9b7 2026 	ldrsh.w	r2, [r7, #38]	; 0x26
- 800de4c:	4965      	ldr	r1, [pc, #404]	; (800dfe4 <etharp_find_entry+0x2d4>)
- 800de4e:	4613      	mov	r3, r2
- 800de50:	005b      	lsls	r3, r3, #1
- 800de52:	4413      	add	r3, r2
- 800de54:	00db      	lsls	r3, r3, #3
- 800de56:	440b      	add	r3, r1
- 800de58:	3312      	adds	r3, #18
- 800de5a:	881b      	ldrh	r3, [r3, #0]
- 800de5c:	837b      	strh	r3, [r7, #26]
- 800de5e:	e01c      	b.n	800de9a <etharp_find_entry+0x18a>
-          }
-        }
-        /* stable entry? */
-      } else if (state >= ETHARP_STATE_STABLE) {
- 800de60:	7dfb      	ldrb	r3, [r7, #23]
- 800de62:	2b01      	cmp	r3, #1
- 800de64:	d919      	bls.n	800de9a <etharp_find_entry+0x18a>
-        /* don't record old_stable for static entries since they never expire */
-        if (state < ETHARP_STATE_STATIC)
-#endif /* ETHARP_SUPPORT_STATIC_ENTRIES */
-        {
-          /* remember entry with oldest stable entry in oldest, its age in maxtime */
-          if (arp_table[i].ctime >= age_stable) {
- 800de66:	f9b7 2026 	ldrsh.w	r2, [r7, #38]	; 0x26
- 800de6a:	495e      	ldr	r1, [pc, #376]	; (800dfe4 <etharp_find_entry+0x2d4>)
- 800de6c:	4613      	mov	r3, r2
- 800de6e:	005b      	lsls	r3, r3, #1
- 800de70:	4413      	add	r3, r2
- 800de72:	00db      	lsls	r3, r3, #3
- 800de74:	440b      	add	r3, r1
- 800de76:	3312      	adds	r3, #18
- 800de78:	881b      	ldrh	r3, [r3, #0]
- 800de7a:	8b3a      	ldrh	r2, [r7, #24]
- 800de7c:	429a      	cmp	r2, r3
- 800de7e:	d80c      	bhi.n	800de9a <etharp_find_entry+0x18a>
-            old_stable = i;
- 800de80:	8cfb      	ldrh	r3, [r7, #38]	; 0x26
- 800de82:	847b      	strh	r3, [r7, #34]	; 0x22
-            age_stable = arp_table[i].ctime;
- 800de84:	f9b7 2026 	ldrsh.w	r2, [r7, #38]	; 0x26
- 800de88:	4956      	ldr	r1, [pc, #344]	; (800dfe4 <etharp_find_entry+0x2d4>)
- 800de8a:	4613      	mov	r3, r2
- 800de8c:	005b      	lsls	r3, r3, #1
- 800de8e:	4413      	add	r3, r2
- 800de90:	00db      	lsls	r3, r3, #3
- 800de92:	440b      	add	r3, r1
- 800de94:	3312      	adds	r3, #18
- 800de96:	881b      	ldrh	r3, [r3, #0]
- 800de98:	833b      	strh	r3, [r7, #24]
-  for (i = 0; i < ARP_TABLE_SIZE; ++i) {
- 800de9a:	8cfb      	ldrh	r3, [r7, #38]	; 0x26
- 800de9c:	3301      	adds	r3, #1
- 800de9e:	b29b      	uxth	r3, r3
- 800dea0:	84fb      	strh	r3, [r7, #38]	; 0x26
- 800dea2:	f9b7 3026 	ldrsh.w	r3, [r7, #38]	; 0x26
- 800dea6:	2b09      	cmp	r3, #9
- 800dea8:	f77f af4c 	ble.w	800dd44 <etharp_find_entry+0x34>
-    }
-  }
-  /* { we have no match } => try to create a new entry */
-
-  /* don't create new entry, only search? */
-  if (((flags & ETHARP_FLAG_FIND_ONLY) != 0) ||
- 800deac:	7afb      	ldrb	r3, [r7, #11]
- 800deae:	f003 0302 	and.w	r3, r3, #2
- 800deb2:	2b00      	cmp	r3, #0
- 800deb4:	d108      	bne.n	800dec8 <etharp_find_entry+0x1b8>
- 800deb6:	f9b7 3024 	ldrsh.w	r3, [r7, #36]	; 0x24
- 800deba:	2b0a      	cmp	r3, #10
- 800debc:	d107      	bne.n	800dece <etharp_find_entry+0x1be>
-      /* or no empty entry found and not allowed to recycle? */
-      ((empty == ARP_TABLE_SIZE) && ((flags & ETHARP_FLAG_TRY_HARD) == 0))) {
- 800debe:	7afb      	ldrb	r3, [r7, #11]
- 800dec0:	f003 0301 	and.w	r3, r3, #1
- 800dec4:	2b00      	cmp	r3, #0
- 800dec6:	d102      	bne.n	800dece <etharp_find_entry+0x1be>
-    LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_find_entry: no empty entry found and not allowed to recycle\n"));
-    return (s16_t)ERR_MEM;
- 800dec8:	f04f 33ff 	mov.w	r3, #4294967295
- 800decc:	e085      	b.n	800dfda <etharp_find_entry+0x2ca>
-   *
-   * { ETHARP_FLAG_TRY_HARD is set at this point }
-   */
-
-  /* 1) empty entry available? */
-  if (empty < ARP_TABLE_SIZE) {
- 800dece:	f9b7 3024 	ldrsh.w	r3, [r7, #36]	; 0x24
- 800ded2:	2b09      	cmp	r3, #9
- 800ded4:	dc02      	bgt.n	800dedc <etharp_find_entry+0x1cc>
-    i = empty;
- 800ded6:	8cbb      	ldrh	r3, [r7, #36]	; 0x24
- 800ded8:	84fb      	strh	r3, [r7, #38]	; 0x26
- 800deda:	e039      	b.n	800df50 <etharp_find_entry+0x240>
-    LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_find_entry: selecting empty entry %d\n", (int)i));
-  } else {
-    /* 2) found recyclable stable entry? */
-    if (old_stable < ARP_TABLE_SIZE) {
- 800dedc:	f9b7 3022 	ldrsh.w	r3, [r7, #34]	; 0x22
- 800dee0:	2b09      	cmp	r3, #9
- 800dee2:	dc14      	bgt.n	800df0e <etharp_find_entry+0x1fe>
-      /* recycle oldest stable*/
-      i = old_stable;
- 800dee4:	8c7b      	ldrh	r3, [r7, #34]	; 0x22
- 800dee6:	84fb      	strh	r3, [r7, #38]	; 0x26
-      LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_find_entry: selecting oldest stable entry %d\n", (int)i));
-      /* no queued packets should exist on stable entries */
-      LWIP_ASSERT("arp_table[i].q == NULL", arp_table[i].q == NULL);
- 800dee8:	f9b7 2026 	ldrsh.w	r2, [r7, #38]	; 0x26
- 800deec:	493d      	ldr	r1, [pc, #244]	; (800dfe4 <etharp_find_entry+0x2d4>)
- 800deee:	4613      	mov	r3, r2
- 800def0:	005b      	lsls	r3, r3, #1
- 800def2:	4413      	add	r3, r2
- 800def4:	00db      	lsls	r3, r3, #3
- 800def6:	440b      	add	r3, r1
- 800def8:	681b      	ldr	r3, [r3, #0]
- 800defa:	2b00      	cmp	r3, #0
- 800defc:	d018      	beq.n	800df30 <etharp_find_entry+0x220>
- 800defe:	4b3a      	ldr	r3, [pc, #232]	; (800dfe8 <etharp_find_entry+0x2d8>)
- 800df00:	f240 126d 	movw	r2, #365	; 0x16d
- 800df04:	493b      	ldr	r1, [pc, #236]	; (800dff4 <etharp_find_entry+0x2e4>)
- 800df06:	483a      	ldr	r0, [pc, #232]	; (800dff0 <etharp_find_entry+0x2e0>)
- 800df08:	f002 fe5e 	bl	8010bc8 <iprintf>
- 800df0c:	e010      	b.n	800df30 <etharp_find_entry+0x220>
-      /* 3) found recyclable pending entry without queued packets? */
-    } else if (old_pending < ARP_TABLE_SIZE) {
- 800df0e:	f9b7 3020 	ldrsh.w	r3, [r7, #32]
- 800df12:	2b09      	cmp	r3, #9
- 800df14:	dc02      	bgt.n	800df1c <etharp_find_entry+0x20c>
-      /* recycle oldest pending */
-      i = old_pending;
- 800df16:	8c3b      	ldrh	r3, [r7, #32]
- 800df18:	84fb      	strh	r3, [r7, #38]	; 0x26
- 800df1a:	e009      	b.n	800df30 <etharp_find_entry+0x220>
-      LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_find_entry: selecting oldest pending entry %d (without queue)\n", (int)i));
-      /* 4) found recyclable pending entry with queued packets? */
-    } else if (old_queue < ARP_TABLE_SIZE) {
- 800df1c:	f9b7 301e 	ldrsh.w	r3, [r7, #30]
- 800df20:	2b09      	cmp	r3, #9
- 800df22:	dc02      	bgt.n	800df2a <etharp_find_entry+0x21a>
-      /* recycle oldest pending (queued packets are free in etharp_free_entry) */
-      i = old_queue;
- 800df24:	8bfb      	ldrh	r3, [r7, #30]
- 800df26:	84fb      	strh	r3, [r7, #38]	; 0x26
- 800df28:	e002      	b.n	800df30 <etharp_find_entry+0x220>
-      LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_find_entry: selecting oldest pending entry %d, freeing packet queue %p\n", (int)i, (void *)(arp_table[i].q)));
-      /* no empty or recyclable entries found */
-    } else {
-      LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_find_entry: no empty or recyclable entries found\n"));
-      return (s16_t)ERR_MEM;
- 800df2a:	f04f 33ff 	mov.w	r3, #4294967295
- 800df2e:	e054      	b.n	800dfda <etharp_find_entry+0x2ca>
-    }
-
-    /* { empty or recyclable entry found } */
-    LWIP_ASSERT("i < ARP_TABLE_SIZE", i < ARP_TABLE_SIZE);
- 800df30:	f9b7 3026 	ldrsh.w	r3, [r7, #38]	; 0x26
- 800df34:	2b09      	cmp	r3, #9
- 800df36:	dd06      	ble.n	800df46 <etharp_find_entry+0x236>
- 800df38:	4b2b      	ldr	r3, [pc, #172]	; (800dfe8 <etharp_find_entry+0x2d8>)
- 800df3a:	f240 127f 	movw	r2, #383	; 0x17f
- 800df3e:	492e      	ldr	r1, [pc, #184]	; (800dff8 <etharp_find_entry+0x2e8>)
- 800df40:	482b      	ldr	r0, [pc, #172]	; (800dff0 <etharp_find_entry+0x2e0>)
- 800df42:	f002 fe41 	bl	8010bc8 <iprintf>
-    etharp_free_entry(i);
- 800df46:	f9b7 3026 	ldrsh.w	r3, [r7, #38]	; 0x26
- 800df4a:	4618      	mov	r0, r3
- 800df4c:	f7ff fdd8 	bl	800db00 <etharp_free_entry>
-  }
-
-  LWIP_ASSERT("i < ARP_TABLE_SIZE", i < ARP_TABLE_SIZE);
- 800df50:	f9b7 3026 	ldrsh.w	r3, [r7, #38]	; 0x26
- 800df54:	2b09      	cmp	r3, #9
- 800df56:	dd06      	ble.n	800df66 <etharp_find_entry+0x256>
- 800df58:	4b23      	ldr	r3, [pc, #140]	; (800dfe8 <etharp_find_entry+0x2d8>)
- 800df5a:	f240 1283 	movw	r2, #387	; 0x183
- 800df5e:	4926      	ldr	r1, [pc, #152]	; (800dff8 <etharp_find_entry+0x2e8>)
- 800df60:	4823      	ldr	r0, [pc, #140]	; (800dff0 <etharp_find_entry+0x2e0>)
- 800df62:	f002 fe31 	bl	8010bc8 <iprintf>
-  LWIP_ASSERT("arp_table[i].state == ETHARP_STATE_EMPTY",
- 800df66:	f9b7 2026 	ldrsh.w	r2, [r7, #38]	; 0x26
- 800df6a:	491e      	ldr	r1, [pc, #120]	; (800dfe4 <etharp_find_entry+0x2d4>)
- 800df6c:	4613      	mov	r3, r2
- 800df6e:	005b      	lsls	r3, r3, #1
- 800df70:	4413      	add	r3, r2
- 800df72:	00db      	lsls	r3, r3, #3
- 800df74:	440b      	add	r3, r1
- 800df76:	3314      	adds	r3, #20
- 800df78:	781b      	ldrb	r3, [r3, #0]
- 800df7a:	2b00      	cmp	r3, #0
- 800df7c:	d006      	beq.n	800df8c <etharp_find_entry+0x27c>
- 800df7e:	4b1a      	ldr	r3, [pc, #104]	; (800dfe8 <etharp_find_entry+0x2d8>)
- 800df80:	f44f 72c2 	mov.w	r2, #388	; 0x184
- 800df84:	491d      	ldr	r1, [pc, #116]	; (800dffc <etharp_find_entry+0x2ec>)
- 800df86:	481a      	ldr	r0, [pc, #104]	; (800dff0 <etharp_find_entry+0x2e0>)
- 800df88:	f002 fe1e 	bl	8010bc8 <iprintf>
-              arp_table[i].state == ETHARP_STATE_EMPTY);
-
-  /* IP address given? */
-  if (ipaddr != NULL) {
- 800df8c:	68fb      	ldr	r3, [r7, #12]
- 800df8e:	2b00      	cmp	r3, #0
- 800df90:	d00b      	beq.n	800dfaa <etharp_find_entry+0x29a>
-    /* set IP address */
-    ip4_addr_copy(arp_table[i].ipaddr, *ipaddr);
- 800df92:	f9b7 2026 	ldrsh.w	r2, [r7, #38]	; 0x26
- 800df96:	68fb      	ldr	r3, [r7, #12]
- 800df98:	6819      	ldr	r1, [r3, #0]
- 800df9a:	4812      	ldr	r0, [pc, #72]	; (800dfe4 <etharp_find_entry+0x2d4>)
- 800df9c:	4613      	mov	r3, r2
- 800df9e:	005b      	lsls	r3, r3, #1
- 800dfa0:	4413      	add	r3, r2
- 800dfa2:	00db      	lsls	r3, r3, #3
- 800dfa4:	4403      	add	r3, r0
- 800dfa6:	3304      	adds	r3, #4
- 800dfa8:	6019      	str	r1, [r3, #0]
-  }
-  arp_table[i].ctime = 0;
- 800dfaa:	f9b7 2026 	ldrsh.w	r2, [r7, #38]	; 0x26
- 800dfae:	490d      	ldr	r1, [pc, #52]	; (800dfe4 <etharp_find_entry+0x2d4>)
- 800dfb0:	4613      	mov	r3, r2
- 800dfb2:	005b      	lsls	r3, r3, #1
- 800dfb4:	4413      	add	r3, r2
- 800dfb6:	00db      	lsls	r3, r3, #3
- 800dfb8:	440b      	add	r3, r1
- 800dfba:	3312      	adds	r3, #18
- 800dfbc:	2200      	movs	r2, #0
- 800dfbe:	801a      	strh	r2, [r3, #0]
-#if ETHARP_TABLE_MATCH_NETIF
-  arp_table[i].netif = netif;
- 800dfc0:	f9b7 2026 	ldrsh.w	r2, [r7, #38]	; 0x26
- 800dfc4:	4907      	ldr	r1, [pc, #28]	; (800dfe4 <etharp_find_entry+0x2d4>)
- 800dfc6:	4613      	mov	r3, r2
- 800dfc8:	005b      	lsls	r3, r3, #1
- 800dfca:	4413      	add	r3, r2
- 800dfcc:	00db      	lsls	r3, r3, #3
- 800dfce:	440b      	add	r3, r1
- 800dfd0:	3308      	adds	r3, #8
- 800dfd2:	687a      	ldr	r2, [r7, #4]
- 800dfd4:	601a      	str	r2, [r3, #0]
-#endif /* ETHARP_TABLE_MATCH_NETIF */
-  return (s16_t)i;
- 800dfd6:	f9b7 3026 	ldrsh.w	r3, [r7, #38]	; 0x26
-}
- 800dfda:	4618      	mov	r0, r3
- 800dfdc:	3728      	adds	r7, #40	; 0x28
- 800dfde:	46bd      	mov	sp, r7
- 800dfe0:	bd80      	pop	{r7, pc}
- 800dfe2:	bf00      	nop
- 800dfe4:	24007bd0 	.word	0x24007bd0
- 800dfe8:	080142dc 	.word	0x080142dc
- 800dfec:	08014314 	.word	0x08014314
- 800dff0:	08014354 	.word	0x08014354
- 800dff4:	0801437c 	.word	0x0801437c
- 800dff8:	08014394 	.word	0x08014394
- 800dffc:	080143a8 	.word	0x080143a8
-
-0800e000 <etharp_update_arp_entry>:
- *
- * @see pbuf_free()
- */
-static err_t
-etharp_update_arp_entry(struct netif *netif, const ip4_addr_t *ipaddr, struct eth_addr *ethaddr, u8_t flags)
-{
- 800e000:	b580      	push	{r7, lr}
- 800e002:	b088      	sub	sp, #32
- 800e004:	af02      	add	r7, sp, #8
- 800e006:	60f8      	str	r0, [r7, #12]
- 800e008:	60b9      	str	r1, [r7, #8]
- 800e00a:	607a      	str	r2, [r7, #4]
- 800e00c:	70fb      	strb	r3, [r7, #3]
-  s16_t i;
-  LWIP_ASSERT("netif->hwaddr_len == ETH_HWADDR_LEN", netif->hwaddr_len == ETH_HWADDR_LEN);
- 800e00e:	68fb      	ldr	r3, [r7, #12]
- 800e010:	f893 302c 	ldrb.w	r3, [r3, #44]	; 0x2c
- 800e014:	2b06      	cmp	r3, #6
- 800e016:	d006      	beq.n	800e026 <etharp_update_arp_entry+0x26>
- 800e018:	4b48      	ldr	r3, [pc, #288]	; (800e13c <etharp_update_arp_entry+0x13c>)
- 800e01a:	f240 12a9 	movw	r2, #425	; 0x1a9
- 800e01e:	4948      	ldr	r1, [pc, #288]	; (800e140 <etharp_update_arp_entry+0x140>)
- 800e020:	4848      	ldr	r0, [pc, #288]	; (800e144 <etharp_update_arp_entry+0x144>)
- 800e022:	f002 fdd1 	bl	8010bc8 <iprintf>
-  LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_update_arp_entry: %"U16_F".%"U16_F".%"U16_F".%"U16_F" - %02"X16_F":%02"X16_F":%02"X16_F":%02"X16_F":%02"X16_F":%02"X16_F"\n",
-              ip4_addr1_16(ipaddr), ip4_addr2_16(ipaddr), ip4_addr3_16(ipaddr), ip4_addr4_16(ipaddr),
-              (u16_t)ethaddr->addr[0], (u16_t)ethaddr->addr[1], (u16_t)ethaddr->addr[2],
-              (u16_t)ethaddr->addr[3], (u16_t)ethaddr->addr[4], (u16_t)ethaddr->addr[5]));
-  /* non-unicast address? */
-  if (ip4_addr_isany(ipaddr) ||
- 800e026:	68bb      	ldr	r3, [r7, #8]
- 800e028:	2b00      	cmp	r3, #0
- 800e02a:	d012      	beq.n	800e052 <etharp_update_arp_entry+0x52>
- 800e02c:	68bb      	ldr	r3, [r7, #8]
- 800e02e:	681b      	ldr	r3, [r3, #0]
- 800e030:	2b00      	cmp	r3, #0
- 800e032:	d00e      	beq.n	800e052 <etharp_update_arp_entry+0x52>
-      ip4_addr_isbroadcast(ipaddr, netif) ||
- 800e034:	68bb      	ldr	r3, [r7, #8]
- 800e036:	681b      	ldr	r3, [r3, #0]
- 800e038:	68f9      	ldr	r1, [r7, #12]
- 800e03a:	4618      	mov	r0, r3
- 800e03c:	f001 f9ba 	bl	800f3b4 <ip4_addr_isbroadcast_u32>
- 800e040:	4603      	mov	r3, r0
-  if (ip4_addr_isany(ipaddr) ||
- 800e042:	2b00      	cmp	r3, #0
- 800e044:	d105      	bne.n	800e052 <etharp_update_arp_entry+0x52>
-      ip4_addr_ismulticast(ipaddr)) {
- 800e046:	68bb      	ldr	r3, [r7, #8]
- 800e048:	681b      	ldr	r3, [r3, #0]
- 800e04a:	f003 03f0 	and.w	r3, r3, #240	; 0xf0
-      ip4_addr_isbroadcast(ipaddr, netif) ||
- 800e04e:	2be0      	cmp	r3, #224	; 0xe0
- 800e050:	d102      	bne.n	800e058 <etharp_update_arp_entry+0x58>
-    LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_update_arp_entry: will not add non-unicast IP address to ARP cache\n"));
-    return ERR_ARG;
- 800e052:	f06f 030f 	mvn.w	r3, #15
- 800e056:	e06c      	b.n	800e132 <etharp_update_arp_entry+0x132>
-  }
-  /* find or create ARP entry */
-  i = etharp_find_entry(ipaddr, flags, netif);
- 800e058:	78fb      	ldrb	r3, [r7, #3]
- 800e05a:	68fa      	ldr	r2, [r7, #12]
- 800e05c:	4619      	mov	r1, r3
- 800e05e:	68b8      	ldr	r0, [r7, #8]
- 800e060:	f7ff fe56 	bl	800dd10 <etharp_find_entry>
- 800e064:	4603      	mov	r3, r0
- 800e066:	82fb      	strh	r3, [r7, #22]
-  /* bail out if no entry could be found */
-  if (i < 0) {
- 800e068:	f9b7 3016 	ldrsh.w	r3, [r7, #22]
- 800e06c:	2b00      	cmp	r3, #0
- 800e06e:	da02      	bge.n	800e076 <etharp_update_arp_entry+0x76>
-    return (err_t)i;
- 800e070:	8afb      	ldrh	r3, [r7, #22]
- 800e072:	b25b      	sxtb	r3, r3
- 800e074:	e05d      	b.n	800e132 <etharp_update_arp_entry+0x132>
-    return ERR_VAL;
-  } else
-#endif /* ETHARP_SUPPORT_STATIC_ENTRIES */
-  {
-    /* mark it stable */
-    arp_table[i].state = ETHARP_STATE_STABLE;
- 800e076:	f9b7 2016 	ldrsh.w	r2, [r7, #22]
- 800e07a:	4933      	ldr	r1, [pc, #204]	; (800e148 <etharp_update_arp_entry+0x148>)
- 800e07c:	4613      	mov	r3, r2
- 800e07e:	005b      	lsls	r3, r3, #1
- 800e080:	4413      	add	r3, r2
- 800e082:	00db      	lsls	r3, r3, #3
- 800e084:	440b      	add	r3, r1
- 800e086:	3314      	adds	r3, #20
- 800e088:	2202      	movs	r2, #2
- 800e08a:	701a      	strb	r2, [r3, #0]
-  }
-
-  /* record network interface */
-  arp_table[i].netif = netif;
- 800e08c:	f9b7 2016 	ldrsh.w	r2, [r7, #22]
- 800e090:	492d      	ldr	r1, [pc, #180]	; (800e148 <etharp_update_arp_entry+0x148>)
- 800e092:	4613      	mov	r3, r2
- 800e094:	005b      	lsls	r3, r3, #1
- 800e096:	4413      	add	r3, r2
- 800e098:	00db      	lsls	r3, r3, #3
- 800e09a:	440b      	add	r3, r1
- 800e09c:	3308      	adds	r3, #8
- 800e09e:	68fa      	ldr	r2, [r7, #12]
- 800e0a0:	601a      	str	r2, [r3, #0]
-  /* insert in SNMP ARP index tree */
-  mib2_add_arp_entry(netif, &arp_table[i].ipaddr);
-
-  LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_update_arp_entry: updating stable entry %"S16_F"\n", i));
-  /* update address */
-  SMEMCPY(&arp_table[i].ethaddr, ethaddr, ETH_HWADDR_LEN);
- 800e0a2:	f9b7 2016 	ldrsh.w	r2, [r7, #22]
- 800e0a6:	4613      	mov	r3, r2
- 800e0a8:	005b      	lsls	r3, r3, #1
- 800e0aa:	4413      	add	r3, r2
- 800e0ac:	00db      	lsls	r3, r3, #3
- 800e0ae:	3308      	adds	r3, #8
- 800e0b0:	4a25      	ldr	r2, [pc, #148]	; (800e148 <etharp_update_arp_entry+0x148>)
- 800e0b2:	4413      	add	r3, r2
- 800e0b4:	3304      	adds	r3, #4
- 800e0b6:	2206      	movs	r2, #6
- 800e0b8:	6879      	ldr	r1, [r7, #4]
- 800e0ba:	4618      	mov	r0, r3
- 800e0bc:	f002 ff65 	bl	8010f8a <memcpy>
-  /* reset time stamp */
-  arp_table[i].ctime = 0;
- 800e0c0:	f9b7 2016 	ldrsh.w	r2, [r7, #22]
- 800e0c4:	4920      	ldr	r1, [pc, #128]	; (800e148 <etharp_update_arp_entry+0x148>)
- 800e0c6:	4613      	mov	r3, r2
- 800e0c8:	005b      	lsls	r3, r3, #1
- 800e0ca:	4413      	add	r3, r2
- 800e0cc:	00db      	lsls	r3, r3, #3
- 800e0ce:	440b      	add	r3, r1
- 800e0d0:	3312      	adds	r3, #18
- 800e0d2:	2200      	movs	r2, #0
- 800e0d4:	801a      	strh	r2, [r3, #0]
-    /* get the packet pointer */
-    p = q->p;
-    /* now queue entry can be freed */
-    memp_free(MEMP_ARP_QUEUE, q);
-#else /* ARP_QUEUEING */
-  if (arp_table[i].q != NULL) {
- 800e0d6:	f9b7 2016 	ldrsh.w	r2, [r7, #22]
- 800e0da:	491b      	ldr	r1, [pc, #108]	; (800e148 <etharp_update_arp_entry+0x148>)
- 800e0dc:	4613      	mov	r3, r2
- 800e0de:	005b      	lsls	r3, r3, #1
- 800e0e0:	4413      	add	r3, r2
- 800e0e2:	00db      	lsls	r3, r3, #3
- 800e0e4:	440b      	add	r3, r1
- 800e0e6:	681b      	ldr	r3, [r3, #0]
- 800e0e8:	2b00      	cmp	r3, #0
- 800e0ea:	d021      	beq.n	800e130 <etharp_update_arp_entry+0x130>
-    struct pbuf *p = arp_table[i].q;
- 800e0ec:	f9b7 2016 	ldrsh.w	r2, [r7, #22]
- 800e0f0:	4915      	ldr	r1, [pc, #84]	; (800e148 <etharp_update_arp_entry+0x148>)
- 800e0f2:	4613      	mov	r3, r2
- 800e0f4:	005b      	lsls	r3, r3, #1
- 800e0f6:	4413      	add	r3, r2
- 800e0f8:	00db      	lsls	r3, r3, #3
- 800e0fa:	440b      	add	r3, r1
- 800e0fc:	681b      	ldr	r3, [r3, #0]
- 800e0fe:	613b      	str	r3, [r7, #16]
-    arp_table[i].q = NULL;
- 800e100:	f9b7 2016 	ldrsh.w	r2, [r7, #22]
- 800e104:	4910      	ldr	r1, [pc, #64]	; (800e148 <etharp_update_arp_entry+0x148>)
- 800e106:	4613      	mov	r3, r2
- 800e108:	005b      	lsls	r3, r3, #1
- 800e10a:	4413      	add	r3, r2
- 800e10c:	00db      	lsls	r3, r3, #3
- 800e10e:	440b      	add	r3, r1
- 800e110:	2200      	movs	r2, #0
- 800e112:	601a      	str	r2, [r3, #0]
-#endif /* ARP_QUEUEING */
-    /* send the queued IP packet */
-    ethernet_output(netif, p, (struct eth_addr *)(netif->hwaddr), ethaddr, ETHTYPE_IP);
- 800e114:	68fb      	ldr	r3, [r7, #12]
- 800e116:	f103 0226 	add.w	r2, r3, #38	; 0x26
- 800e11a:	f44f 6300 	mov.w	r3, #2048	; 0x800
- 800e11e:	9300      	str	r3, [sp, #0]
- 800e120:	687b      	ldr	r3, [r7, #4]
- 800e122:	6939      	ldr	r1, [r7, #16]
- 800e124:	68f8      	ldr	r0, [r7, #12]
- 800e126:	f002 f853 	bl	80101d0 <ethernet_output>
-    /* free the queued IP packet */
-    pbuf_free(p);
- 800e12a:	6938      	ldr	r0, [r7, #16]
- 800e12c:	f7f8 ff52 	bl	8006fd4 <pbuf_free>
-  }
-  return ERR_OK;
- 800e130:	2300      	movs	r3, #0
-}
- 800e132:	4618      	mov	r0, r3
- 800e134:	3718      	adds	r7, #24
- 800e136:	46bd      	mov	sp, r7
- 800e138:	bd80      	pop	{r7, pc}
- 800e13a:	bf00      	nop
- 800e13c:	080142dc 	.word	0x080142dc
- 800e140:	080143d4 	.word	0x080143d4
- 800e144:	08014354 	.word	0x08014354
- 800e148:	24007bd0 	.word	0x24007bd0
-
-0800e14c <etharp_cleanup_netif>:
- *
- * @param netif points to a network interface
- */
-void
-etharp_cleanup_netif(struct netif *netif)
-{
- 800e14c:	b580      	push	{r7, lr}
- 800e14e:	b084      	sub	sp, #16
- 800e150:	af00      	add	r7, sp, #0
- 800e152:	6078      	str	r0, [r7, #4]
-  int i;
-
-  for (i = 0; i < ARP_TABLE_SIZE; ++i) {
- 800e154:	2300      	movs	r3, #0
- 800e156:	60fb      	str	r3, [r7, #12]
- 800e158:	e01e      	b.n	800e198 <etharp_cleanup_netif+0x4c>
-    u8_t state = arp_table[i].state;
- 800e15a:	4913      	ldr	r1, [pc, #76]	; (800e1a8 <etharp_cleanup_netif+0x5c>)
- 800e15c:	68fa      	ldr	r2, [r7, #12]
- 800e15e:	4613      	mov	r3, r2
- 800e160:	005b      	lsls	r3, r3, #1
- 800e162:	4413      	add	r3, r2
- 800e164:	00db      	lsls	r3, r3, #3
- 800e166:	440b      	add	r3, r1
- 800e168:	3314      	adds	r3, #20
- 800e16a:	781b      	ldrb	r3, [r3, #0]
- 800e16c:	72fb      	strb	r3, [r7, #11]
-    if ((state != ETHARP_STATE_EMPTY) && (arp_table[i].netif == netif)) {
- 800e16e:	7afb      	ldrb	r3, [r7, #11]
- 800e170:	2b00      	cmp	r3, #0
- 800e172:	d00e      	beq.n	800e192 <etharp_cleanup_netif+0x46>
- 800e174:	490c      	ldr	r1, [pc, #48]	; (800e1a8 <etharp_cleanup_netif+0x5c>)
- 800e176:	68fa      	ldr	r2, [r7, #12]
- 800e178:	4613      	mov	r3, r2
- 800e17a:	005b      	lsls	r3, r3, #1
- 800e17c:	4413      	add	r3, r2
- 800e17e:	00db      	lsls	r3, r3, #3
- 800e180:	440b      	add	r3, r1
- 800e182:	3308      	adds	r3, #8
- 800e184:	681b      	ldr	r3, [r3, #0]
- 800e186:	687a      	ldr	r2, [r7, #4]
- 800e188:	429a      	cmp	r2, r3
- 800e18a:	d102      	bne.n	800e192 <etharp_cleanup_netif+0x46>
-      etharp_free_entry(i);
- 800e18c:	68f8      	ldr	r0, [r7, #12]
- 800e18e:	f7ff fcb7 	bl	800db00 <etharp_free_entry>
-  for (i = 0; i < ARP_TABLE_SIZE; ++i) {
- 800e192:	68fb      	ldr	r3, [r7, #12]
- 800e194:	3301      	adds	r3, #1
- 800e196:	60fb      	str	r3, [r7, #12]
- 800e198:	68fb      	ldr	r3, [r7, #12]
- 800e19a:	2b09      	cmp	r3, #9
- 800e19c:	dddd      	ble.n	800e15a <etharp_cleanup_netif+0xe>
-    }
-  }
-}
- 800e19e:	bf00      	nop
- 800e1a0:	bf00      	nop
- 800e1a2:	3710      	adds	r7, #16
- 800e1a4:	46bd      	mov	sp, r7
- 800e1a6:	bd80      	pop	{r7, pc}
- 800e1a8:	24007bd0 	.word	0x24007bd0
-
-0800e1ac <etharp_input>:
- *
- * @see pbuf_free()
- */
-void
-etharp_input(struct pbuf *p, struct netif *netif)
-{
- 800e1ac:	b5b0      	push	{r4, r5, r7, lr}
- 800e1ae:	b08a      	sub	sp, #40	; 0x28
- 800e1b0:	af04      	add	r7, sp, #16
- 800e1b2:	6078      	str	r0, [r7, #4]
- 800e1b4:	6039      	str	r1, [r7, #0]
-  ip4_addr_t sipaddr, dipaddr;
-  u8_t for_us;
-
-  LWIP_ASSERT_CORE_LOCKED();
-
-  LWIP_ERROR("netif != NULL", (netif != NULL), return;);
- 800e1b6:	683b      	ldr	r3, [r7, #0]
- 800e1b8:	2b00      	cmp	r3, #0
- 800e1ba:	d107      	bne.n	800e1cc <etharp_input+0x20>
- 800e1bc:	4b3d      	ldr	r3, [pc, #244]	; (800e2b4 <etharp_input+0x108>)
- 800e1be:	f240 228a 	movw	r2, #650	; 0x28a
- 800e1c2:	493d      	ldr	r1, [pc, #244]	; (800e2b8 <etharp_input+0x10c>)
- 800e1c4:	483d      	ldr	r0, [pc, #244]	; (800e2bc <etharp_input+0x110>)
- 800e1c6:	f002 fcff 	bl	8010bc8 <iprintf>
- 800e1ca:	e06f      	b.n	800e2ac <etharp_input+0x100>
-
-  hdr = (struct etharp_hdr *)p->payload;
- 800e1cc:	687b      	ldr	r3, [r7, #4]
- 800e1ce:	685b      	ldr	r3, [r3, #4]
- 800e1d0:	617b      	str	r3, [r7, #20]
-
-  /* RFC 826 "Packet Reception": */
-  if ((hdr->hwtype != PP_HTONS(LWIP_IANA_HWTYPE_ETHERNET)) ||
- 800e1d2:	697b      	ldr	r3, [r7, #20]
- 800e1d4:	881b      	ldrh	r3, [r3, #0]
- 800e1d6:	b29b      	uxth	r3, r3
- 800e1d8:	f5b3 7f80 	cmp.w	r3, #256	; 0x100
- 800e1dc:	d10c      	bne.n	800e1f8 <etharp_input+0x4c>
-      (hdr->hwlen != ETH_HWADDR_LEN) ||
- 800e1de:	697b      	ldr	r3, [r7, #20]
- 800e1e0:	791b      	ldrb	r3, [r3, #4]
-  if ((hdr->hwtype != PP_HTONS(LWIP_IANA_HWTYPE_ETHERNET)) ||
- 800e1e2:	2b06      	cmp	r3, #6
- 800e1e4:	d108      	bne.n	800e1f8 <etharp_input+0x4c>
-      (hdr->protolen != sizeof(ip4_addr_t)) ||
- 800e1e6:	697b      	ldr	r3, [r7, #20]
- 800e1e8:	795b      	ldrb	r3, [r3, #5]
-      (hdr->hwlen != ETH_HWADDR_LEN) ||
- 800e1ea:	2b04      	cmp	r3, #4
- 800e1ec:	d104      	bne.n	800e1f8 <etharp_input+0x4c>
-      (hdr->proto != PP_HTONS(ETHTYPE_IP)))  {
- 800e1ee:	697b      	ldr	r3, [r7, #20]
- 800e1f0:	885b      	ldrh	r3, [r3, #2]
- 800e1f2:	b29b      	uxth	r3, r3
-      (hdr->protolen != sizeof(ip4_addr_t)) ||
- 800e1f4:	2b08      	cmp	r3, #8
- 800e1f6:	d003      	beq.n	800e200 <etharp_input+0x54>
-    LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_WARNING,
-                ("etharp_input: packet dropped, wrong hw type, hwlen, proto, protolen or ethernet type (%"U16_F"/%"U16_F"/%"U16_F"/%"U16_F")\n",
-                 hdr->hwtype, (u16_t)hdr->hwlen, hdr->proto, (u16_t)hdr->protolen));
-    ETHARP_STATS_INC(etharp.proterr);
-    ETHARP_STATS_INC(etharp.drop);
-    pbuf_free(p);
- 800e1f8:	6878      	ldr	r0, [r7, #4]
- 800e1fa:	f7f8 feeb 	bl	8006fd4 <pbuf_free>
-    return;
- 800e1fe:	e055      	b.n	800e2ac <etharp_input+0x100>
-  autoip_arp_reply(netif, hdr);
-#endif /* LWIP_AUTOIP */
-
-  /* Copy struct ip4_addr_wordaligned to aligned ip4_addr, to support compilers without
-   * structure packing (not using structure copy which breaks strict-aliasing rules). */
-  IPADDR_WORDALIGNED_COPY_TO_IP4_ADDR_T(&sipaddr, &hdr->sipaddr);
- 800e200:	697b      	ldr	r3, [r7, #20]
- 800e202:	330e      	adds	r3, #14
- 800e204:	681b      	ldr	r3, [r3, #0]
- 800e206:	60fb      	str	r3, [r7, #12]
-  IPADDR_WORDALIGNED_COPY_TO_IP4_ADDR_T(&dipaddr, &hdr->dipaddr);
- 800e208:	697b      	ldr	r3, [r7, #20]
- 800e20a:	3318      	adds	r3, #24
- 800e20c:	681b      	ldr	r3, [r3, #0]
- 800e20e:	60bb      	str	r3, [r7, #8]
-
-  /* this interface is not configured? */
-  if (ip4_addr_isany_val(*netif_ip4_addr(netif))) {
- 800e210:	683b      	ldr	r3, [r7, #0]
- 800e212:	3304      	adds	r3, #4
- 800e214:	681b      	ldr	r3, [r3, #0]
- 800e216:	2b00      	cmp	r3, #0
- 800e218:	d102      	bne.n	800e220 <etharp_input+0x74>
-    for_us = 0;
- 800e21a:	2300      	movs	r3, #0
- 800e21c:	74fb      	strb	r3, [r7, #19]
- 800e21e:	e009      	b.n	800e234 <etharp_input+0x88>
-  } else {
-    /* ARP packet directed to us? */
-    for_us = (u8_t)ip4_addr_cmp(&dipaddr, netif_ip4_addr(netif));
- 800e220:	68ba      	ldr	r2, [r7, #8]
- 800e222:	683b      	ldr	r3, [r7, #0]
- 800e224:	3304      	adds	r3, #4
- 800e226:	681b      	ldr	r3, [r3, #0]
- 800e228:	429a      	cmp	r2, r3
- 800e22a:	bf0c      	ite	eq
- 800e22c:	2301      	moveq	r3, #1
- 800e22e:	2300      	movne	r3, #0
- 800e230:	b2db      	uxtb	r3, r3
- 800e232:	74fb      	strb	r3, [r7, #19]
-  /* ARP message directed to us?
-      -> add IP address in ARP cache; assume requester wants to talk to us,
-         can result in directly sending the queued packets for this host.
-     ARP message not directed to us?
-      ->  update the source IP address in the cache, if present */
-  etharp_update_arp_entry(netif, &sipaddr, &(hdr->shwaddr),
- 800e234:	697b      	ldr	r3, [r7, #20]
- 800e236:	f103 0208 	add.w	r2, r3, #8
- 800e23a:	7cfb      	ldrb	r3, [r7, #19]
- 800e23c:	2b00      	cmp	r3, #0
- 800e23e:	d001      	beq.n	800e244 <etharp_input+0x98>
- 800e240:	2301      	movs	r3, #1
- 800e242:	e000      	b.n	800e246 <etharp_input+0x9a>
- 800e244:	2302      	movs	r3, #2
- 800e246:	f107 010c 	add.w	r1, r7, #12
- 800e24a:	6838      	ldr	r0, [r7, #0]
- 800e24c:	f7ff fed8 	bl	800e000 <etharp_update_arp_entry>
-                          for_us ? ETHARP_FLAG_TRY_HARD : ETHARP_FLAG_FIND_ONLY);
-
-  /* now act on the message itself */
-  switch (hdr->opcode) {
- 800e250:	697b      	ldr	r3, [r7, #20]
- 800e252:	88db      	ldrh	r3, [r3, #6]
- 800e254:	b29b      	uxth	r3, r3
- 800e256:	f5b3 7f80 	cmp.w	r3, #256	; 0x100
- 800e25a:	d003      	beq.n	800e264 <etharp_input+0xb8>
- 800e25c:	f5b3 7f00 	cmp.w	r3, #512	; 0x200
- 800e260:	d01e      	beq.n	800e2a0 <etharp_input+0xf4>
-#endif /* (LWIP_DHCP && DHCP_DOES_ARP_CHECK) */
-      break;
-    default:
-      LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_input: ARP unknown opcode type %"S16_F"\n", lwip_htons(hdr->opcode)));
-      ETHARP_STATS_INC(etharp.err);
-      break;
- 800e262:	e020      	b.n	800e2a6 <etharp_input+0xfa>
-      if (for_us) {
- 800e264:	7cfb      	ldrb	r3, [r7, #19]
- 800e266:	2b00      	cmp	r3, #0
- 800e268:	d01c      	beq.n	800e2a4 <etharp_input+0xf8>
-                   (struct eth_addr *)netif->hwaddr, &hdr->shwaddr,
- 800e26a:	683b      	ldr	r3, [r7, #0]
- 800e26c:	f103 0026 	add.w	r0, r3, #38	; 0x26
- 800e270:	697b      	ldr	r3, [r7, #20]
- 800e272:	f103 0408 	add.w	r4, r3, #8
-                   (struct eth_addr *)netif->hwaddr, netif_ip4_addr(netif),
- 800e276:	683b      	ldr	r3, [r7, #0]
- 800e278:	f103 0526 	add.w	r5, r3, #38	; 0x26
- 800e27c:	683b      	ldr	r3, [r7, #0]
- 800e27e:	3304      	adds	r3, #4
-                   &hdr->shwaddr, &sipaddr,
- 800e280:	697a      	ldr	r2, [r7, #20]
- 800e282:	3208      	adds	r2, #8
-        etharp_raw(netif,
- 800e284:	2102      	movs	r1, #2
- 800e286:	9103      	str	r1, [sp, #12]
- 800e288:	f107 010c 	add.w	r1, r7, #12
- 800e28c:	9102      	str	r1, [sp, #8]
- 800e28e:	9201      	str	r2, [sp, #4]
- 800e290:	9300      	str	r3, [sp, #0]
- 800e292:	462b      	mov	r3, r5
- 800e294:	4622      	mov	r2, r4
- 800e296:	4601      	mov	r1, r0
- 800e298:	6838      	ldr	r0, [r7, #0]
- 800e29a:	f000 faeb 	bl	800e874 <etharp_raw>
-      break;
- 800e29e:	e001      	b.n	800e2a4 <etharp_input+0xf8>
-      break;
- 800e2a0:	bf00      	nop
- 800e2a2:	e000      	b.n	800e2a6 <etharp_input+0xfa>
-      break;
- 800e2a4:	bf00      	nop
-  }
-  /* free ARP packet */
-  pbuf_free(p);
- 800e2a6:	6878      	ldr	r0, [r7, #4]
- 800e2a8:	f7f8 fe94 	bl	8006fd4 <pbuf_free>
-}
- 800e2ac:	3718      	adds	r7, #24
- 800e2ae:	46bd      	mov	sp, r7
- 800e2b0:	bdb0      	pop	{r4, r5, r7, pc}
- 800e2b2:	bf00      	nop
- 800e2b4:	080142dc 	.word	0x080142dc
- 800e2b8:	0801442c 	.word	0x0801442c
- 800e2bc:	08014354 	.word	0x08014354
-
-0800e2c0 <etharp_output_to_arp_index>:
-/** Just a small helper function that sends a pbuf to an ethernet address
- * in the arp_table specified by the index 'arp_idx'.
- */
-static err_t
-etharp_output_to_arp_index(struct netif *netif, struct pbuf *q, netif_addr_idx_t arp_idx)
-{
- 800e2c0:	b580      	push	{r7, lr}
- 800e2c2:	b086      	sub	sp, #24
- 800e2c4:	af02      	add	r7, sp, #8
- 800e2c6:	60f8      	str	r0, [r7, #12]
- 800e2c8:	60b9      	str	r1, [r7, #8]
- 800e2ca:	4613      	mov	r3, r2
- 800e2cc:	71fb      	strb	r3, [r7, #7]
-  LWIP_ASSERT("arp_table[arp_idx].state >= ETHARP_STATE_STABLE",
- 800e2ce:	79fa      	ldrb	r2, [r7, #7]
- 800e2d0:	4944      	ldr	r1, [pc, #272]	; (800e3e4 <etharp_output_to_arp_index+0x124>)
- 800e2d2:	4613      	mov	r3, r2
- 800e2d4:	005b      	lsls	r3, r3, #1
- 800e2d6:	4413      	add	r3, r2
- 800e2d8:	00db      	lsls	r3, r3, #3
- 800e2da:	440b      	add	r3, r1
- 800e2dc:	3314      	adds	r3, #20
- 800e2de:	781b      	ldrb	r3, [r3, #0]
- 800e2e0:	2b01      	cmp	r3, #1
- 800e2e2:	d806      	bhi.n	800e2f2 <etharp_output_to_arp_index+0x32>
- 800e2e4:	4b40      	ldr	r3, [pc, #256]	; (800e3e8 <etharp_output_to_arp_index+0x128>)
- 800e2e6:	f240 22ee 	movw	r2, #750	; 0x2ee
- 800e2ea:	4940      	ldr	r1, [pc, #256]	; (800e3ec <etharp_output_to_arp_index+0x12c>)
- 800e2ec:	4840      	ldr	r0, [pc, #256]	; (800e3f0 <etharp_output_to_arp_index+0x130>)
- 800e2ee:	f002 fc6b 	bl	8010bc8 <iprintf>
-              arp_table[arp_idx].state >= ETHARP_STATE_STABLE);
-  /* if arp table entry is about to expire: re-request it,
-     but only if its state is ETHARP_STATE_STABLE to prevent flooding the
-     network with ARP requests if this address is used frequently. */
-  if (arp_table[arp_idx].state == ETHARP_STATE_STABLE) {
- 800e2f2:	79fa      	ldrb	r2, [r7, #7]
- 800e2f4:	493b      	ldr	r1, [pc, #236]	; (800e3e4 <etharp_output_to_arp_index+0x124>)
- 800e2f6:	4613      	mov	r3, r2
- 800e2f8:	005b      	lsls	r3, r3, #1
- 800e2fa:	4413      	add	r3, r2
- 800e2fc:	00db      	lsls	r3, r3, #3
- 800e2fe:	440b      	add	r3, r1
- 800e300:	3314      	adds	r3, #20
- 800e302:	781b      	ldrb	r3, [r3, #0]
- 800e304:	2b02      	cmp	r3, #2
- 800e306:	d153      	bne.n	800e3b0 <etharp_output_to_arp_index+0xf0>
-    if (arp_table[arp_idx].ctime >= ARP_AGE_REREQUEST_USED_BROADCAST) {
- 800e308:	79fa      	ldrb	r2, [r7, #7]
- 800e30a:	4936      	ldr	r1, [pc, #216]	; (800e3e4 <etharp_output_to_arp_index+0x124>)
- 800e30c:	4613      	mov	r3, r2
- 800e30e:	005b      	lsls	r3, r3, #1
- 800e310:	4413      	add	r3, r2
- 800e312:	00db      	lsls	r3, r3, #3
- 800e314:	440b      	add	r3, r1
- 800e316:	3312      	adds	r3, #18
- 800e318:	881b      	ldrh	r3, [r3, #0]
- 800e31a:	f5b3 7f8e 	cmp.w	r3, #284	; 0x11c
- 800e31e:	d919      	bls.n	800e354 <etharp_output_to_arp_index+0x94>
-      /* issue a standard request using broadcast */
-      if (etharp_request(netif, &arp_table[arp_idx].ipaddr) == ERR_OK) {
- 800e320:	79fa      	ldrb	r2, [r7, #7]
- 800e322:	4613      	mov	r3, r2
- 800e324:	005b      	lsls	r3, r3, #1
- 800e326:	4413      	add	r3, r2
- 800e328:	00db      	lsls	r3, r3, #3
- 800e32a:	4a2e      	ldr	r2, [pc, #184]	; (800e3e4 <etharp_output_to_arp_index+0x124>)
- 800e32c:	4413      	add	r3, r2
- 800e32e:	3304      	adds	r3, #4
- 800e330:	4619      	mov	r1, r3
- 800e332:	68f8      	ldr	r0, [r7, #12]
- 800e334:	f000 fb4c 	bl	800e9d0 <etharp_request>
- 800e338:	4603      	mov	r3, r0
- 800e33a:	2b00      	cmp	r3, #0
- 800e33c:	d138      	bne.n	800e3b0 <etharp_output_to_arp_index+0xf0>
-        arp_table[arp_idx].state = ETHARP_STATE_STABLE_REREQUESTING_1;
- 800e33e:	79fa      	ldrb	r2, [r7, #7]
- 800e340:	4928      	ldr	r1, [pc, #160]	; (800e3e4 <etharp_output_to_arp_index+0x124>)
- 800e342:	4613      	mov	r3, r2
- 800e344:	005b      	lsls	r3, r3, #1
- 800e346:	4413      	add	r3, r2
- 800e348:	00db      	lsls	r3, r3, #3
- 800e34a:	440b      	add	r3, r1
- 800e34c:	3314      	adds	r3, #20
- 800e34e:	2203      	movs	r2, #3
- 800e350:	701a      	strb	r2, [r3, #0]
- 800e352:	e02d      	b.n	800e3b0 <etharp_output_to_arp_index+0xf0>
-      }
-    } else if (arp_table[arp_idx].ctime >= ARP_AGE_REREQUEST_USED_UNICAST) {
- 800e354:	79fa      	ldrb	r2, [r7, #7]
- 800e356:	4923      	ldr	r1, [pc, #140]	; (800e3e4 <etharp_output_to_arp_index+0x124>)
- 800e358:	4613      	mov	r3, r2
- 800e35a:	005b      	lsls	r3, r3, #1
- 800e35c:	4413      	add	r3, r2
- 800e35e:	00db      	lsls	r3, r3, #3
- 800e360:	440b      	add	r3, r1
- 800e362:	3312      	adds	r3, #18
- 800e364:	881b      	ldrh	r3, [r3, #0]
- 800e366:	f5b3 7f87 	cmp.w	r3, #270	; 0x10e
- 800e36a:	d321      	bcc.n	800e3b0 <etharp_output_to_arp_index+0xf0>
-      /* issue a unicast request (for 15 seconds) to prevent unnecessary broadcast */
-      if (etharp_request_dst(netif, &arp_table[arp_idx].ipaddr, &arp_table[arp_idx].ethaddr) == ERR_OK) {
- 800e36c:	79fa      	ldrb	r2, [r7, #7]
- 800e36e:	4613      	mov	r3, r2
- 800e370:	005b      	lsls	r3, r3, #1
- 800e372:	4413      	add	r3, r2
- 800e374:	00db      	lsls	r3, r3, #3
- 800e376:	4a1b      	ldr	r2, [pc, #108]	; (800e3e4 <etharp_output_to_arp_index+0x124>)
- 800e378:	4413      	add	r3, r2
- 800e37a:	1d19      	adds	r1, r3, #4
- 800e37c:	79fa      	ldrb	r2, [r7, #7]
- 800e37e:	4613      	mov	r3, r2
- 800e380:	005b      	lsls	r3, r3, #1
- 800e382:	4413      	add	r3, r2
- 800e384:	00db      	lsls	r3, r3, #3
- 800e386:	3308      	adds	r3, #8
- 800e388:	4a16      	ldr	r2, [pc, #88]	; (800e3e4 <etharp_output_to_arp_index+0x124>)
- 800e38a:	4413      	add	r3, r2
- 800e38c:	3304      	adds	r3, #4
- 800e38e:	461a      	mov	r2, r3
- 800e390:	68f8      	ldr	r0, [r7, #12]
- 800e392:	f000 fafb 	bl	800e98c <etharp_request_dst>
- 800e396:	4603      	mov	r3, r0
- 800e398:	2b00      	cmp	r3, #0
- 800e39a:	d109      	bne.n	800e3b0 <etharp_output_to_arp_index+0xf0>
-        arp_table[arp_idx].state = ETHARP_STATE_STABLE_REREQUESTING_1;
- 800e39c:	79fa      	ldrb	r2, [r7, #7]
- 800e39e:	4911      	ldr	r1, [pc, #68]	; (800e3e4 <etharp_output_to_arp_index+0x124>)
- 800e3a0:	4613      	mov	r3, r2
- 800e3a2:	005b      	lsls	r3, r3, #1
- 800e3a4:	4413      	add	r3, r2
- 800e3a6:	00db      	lsls	r3, r3, #3
- 800e3a8:	440b      	add	r3, r1
- 800e3aa:	3314      	adds	r3, #20
- 800e3ac:	2203      	movs	r2, #3
- 800e3ae:	701a      	strb	r2, [r3, #0]
-      }
-    }
-  }
-
-  return ethernet_output(netif, q, (struct eth_addr *)(netif->hwaddr), &arp_table[arp_idx].ethaddr, ETHTYPE_IP);
- 800e3b0:	68fb      	ldr	r3, [r7, #12]
- 800e3b2:	f103 0126 	add.w	r1, r3, #38	; 0x26
- 800e3b6:	79fa      	ldrb	r2, [r7, #7]
- 800e3b8:	4613      	mov	r3, r2
- 800e3ba:	005b      	lsls	r3, r3, #1
- 800e3bc:	4413      	add	r3, r2
- 800e3be:	00db      	lsls	r3, r3, #3
- 800e3c0:	3308      	adds	r3, #8
- 800e3c2:	4a08      	ldr	r2, [pc, #32]	; (800e3e4 <etharp_output_to_arp_index+0x124>)
- 800e3c4:	4413      	add	r3, r2
- 800e3c6:	3304      	adds	r3, #4
- 800e3c8:	f44f 6200 	mov.w	r2, #2048	; 0x800
- 800e3cc:	9200      	str	r2, [sp, #0]
- 800e3ce:	460a      	mov	r2, r1
- 800e3d0:	68b9      	ldr	r1, [r7, #8]
- 800e3d2:	68f8      	ldr	r0, [r7, #12]
- 800e3d4:	f001 fefc 	bl	80101d0 <ethernet_output>
- 800e3d8:	4603      	mov	r3, r0
-}
- 800e3da:	4618      	mov	r0, r3
- 800e3dc:	3710      	adds	r7, #16
- 800e3de:	46bd      	mov	sp, r7
- 800e3e0:	bd80      	pop	{r7, pc}
- 800e3e2:	bf00      	nop
- 800e3e4:	24007bd0 	.word	0x24007bd0
- 800e3e8:	080142dc 	.word	0x080142dc
- 800e3ec:	0801444c 	.word	0x0801444c
- 800e3f0:	08014354 	.word	0x08014354
-
-0800e3f4 <etharp_output>:
- * - ERR_RTE No route to destination (no gateway to external networks),
- * or the return type of either etharp_query() or ethernet_output().
- */
-err_t
-etharp_output(struct netif *netif, struct pbuf *q, const ip4_addr_t *ipaddr)
-{
- 800e3f4:	b580      	push	{r7, lr}
- 800e3f6:	b08a      	sub	sp, #40	; 0x28
- 800e3f8:	af02      	add	r7, sp, #8
- 800e3fa:	60f8      	str	r0, [r7, #12]
- 800e3fc:	60b9      	str	r1, [r7, #8]
- 800e3fe:	607a      	str	r2, [r7, #4]
-  const struct eth_addr *dest;
-  struct eth_addr mcastaddr;
-  const ip4_addr_t *dst_addr = ipaddr;
- 800e400:	687b      	ldr	r3, [r7, #4]
- 800e402:	61bb      	str	r3, [r7, #24]
-
-  LWIP_ASSERT_CORE_LOCKED();
-  LWIP_ASSERT("netif != NULL", netif != NULL);
- 800e404:	68fb      	ldr	r3, [r7, #12]
- 800e406:	2b00      	cmp	r3, #0
- 800e408:	d106      	bne.n	800e418 <etharp_output+0x24>
- 800e40a:	4b73      	ldr	r3, [pc, #460]	; (800e5d8 <etharp_output+0x1e4>)
- 800e40c:	f240 321e 	movw	r2, #798	; 0x31e
- 800e410:	4972      	ldr	r1, [pc, #456]	; (800e5dc <etharp_output+0x1e8>)
- 800e412:	4873      	ldr	r0, [pc, #460]	; (800e5e0 <etharp_output+0x1ec>)
- 800e414:	f002 fbd8 	bl	8010bc8 <iprintf>
-  LWIP_ASSERT("q != NULL", q != NULL);
- 800e418:	68bb      	ldr	r3, [r7, #8]
- 800e41a:	2b00      	cmp	r3, #0
- 800e41c:	d106      	bne.n	800e42c <etharp_output+0x38>
- 800e41e:	4b6e      	ldr	r3, [pc, #440]	; (800e5d8 <etharp_output+0x1e4>)
- 800e420:	f240 321f 	movw	r2, #799	; 0x31f
- 800e424:	496f      	ldr	r1, [pc, #444]	; (800e5e4 <etharp_output+0x1f0>)
- 800e426:	486e      	ldr	r0, [pc, #440]	; (800e5e0 <etharp_output+0x1ec>)
- 800e428:	f002 fbce 	bl	8010bc8 <iprintf>
-  LWIP_ASSERT("ipaddr != NULL", ipaddr != NULL);
- 800e42c:	687b      	ldr	r3, [r7, #4]
- 800e42e:	2b00      	cmp	r3, #0
- 800e430:	d106      	bne.n	800e440 <etharp_output+0x4c>
- 800e432:	4b69      	ldr	r3, [pc, #420]	; (800e5d8 <etharp_output+0x1e4>)
- 800e434:	f44f 7248 	mov.w	r2, #800	; 0x320
- 800e438:	496b      	ldr	r1, [pc, #428]	; (800e5e8 <etharp_output+0x1f4>)
- 800e43a:	4869      	ldr	r0, [pc, #420]	; (800e5e0 <etharp_output+0x1ec>)
- 800e43c:	f002 fbc4 	bl	8010bc8 <iprintf>
-
-  /* Determine on destination hardware address. Broadcasts and multicasts
-   * are special, other IP addresses are looked up in the ARP table. */
-
-  /* broadcast destination IP address? */
-  if (ip4_addr_isbroadcast(ipaddr, netif)) {
- 800e440:	687b      	ldr	r3, [r7, #4]
- 800e442:	681b      	ldr	r3, [r3, #0]
- 800e444:	68f9      	ldr	r1, [r7, #12]
- 800e446:	4618      	mov	r0, r3
- 800e448:	f000 ffb4 	bl	800f3b4 <ip4_addr_isbroadcast_u32>
- 800e44c:	4603      	mov	r3, r0
- 800e44e:	2b00      	cmp	r3, #0
- 800e450:	d002      	beq.n	800e458 <etharp_output+0x64>
-    /* broadcast on Ethernet also */
-    dest = (const struct eth_addr *)&ethbroadcast;
- 800e452:	4b66      	ldr	r3, [pc, #408]	; (800e5ec <etharp_output+0x1f8>)
- 800e454:	61fb      	str	r3, [r7, #28]
- 800e456:	e0af      	b.n	800e5b8 <etharp_output+0x1c4>
-    /* multicast destination IP address? */
-  } else if (ip4_addr_ismulticast(ipaddr)) {
- 800e458:	687b      	ldr	r3, [r7, #4]
- 800e45a:	681b      	ldr	r3, [r3, #0]
- 800e45c:	f003 03f0 	and.w	r3, r3, #240	; 0xf0
- 800e460:	2be0      	cmp	r3, #224	; 0xe0
- 800e462:	d118      	bne.n	800e496 <etharp_output+0xa2>
-    /* Hash IP multicast address to MAC address.*/
-    mcastaddr.addr[0] = LL_IP4_MULTICAST_ADDR_0;
- 800e464:	2301      	movs	r3, #1
- 800e466:	743b      	strb	r3, [r7, #16]
-    mcastaddr.addr[1] = LL_IP4_MULTICAST_ADDR_1;
- 800e468:	2300      	movs	r3, #0
- 800e46a:	747b      	strb	r3, [r7, #17]
-    mcastaddr.addr[2] = LL_IP4_MULTICAST_ADDR_2;
- 800e46c:	235e      	movs	r3, #94	; 0x5e
- 800e46e:	74bb      	strb	r3, [r7, #18]
-    mcastaddr.addr[3] = ip4_addr2(ipaddr) & 0x7f;
- 800e470:	687b      	ldr	r3, [r7, #4]
- 800e472:	3301      	adds	r3, #1
- 800e474:	781b      	ldrb	r3, [r3, #0]
- 800e476:	f003 037f 	and.w	r3, r3, #127	; 0x7f
- 800e47a:	b2db      	uxtb	r3, r3
- 800e47c:	74fb      	strb	r3, [r7, #19]
-    mcastaddr.addr[4] = ip4_addr3(ipaddr);
- 800e47e:	687b      	ldr	r3, [r7, #4]
- 800e480:	3302      	adds	r3, #2
- 800e482:	781b      	ldrb	r3, [r3, #0]
- 800e484:	753b      	strb	r3, [r7, #20]
-    mcastaddr.addr[5] = ip4_addr4(ipaddr);
- 800e486:	687b      	ldr	r3, [r7, #4]
- 800e488:	3303      	adds	r3, #3
- 800e48a:	781b      	ldrb	r3, [r3, #0]
- 800e48c:	757b      	strb	r3, [r7, #21]
-    /* destination Ethernet address is multicast */
-    dest = &mcastaddr;
- 800e48e:	f107 0310 	add.w	r3, r7, #16
- 800e492:	61fb      	str	r3, [r7, #28]
- 800e494:	e090      	b.n	800e5b8 <etharp_output+0x1c4>
-    /* unicast destination IP address? */
-  } else {
-    netif_addr_idx_t i;
-    /* outside local network? if so, this can neither be a global broadcast nor
-       a subnet broadcast. */
-    if (!ip4_addr_netcmp(ipaddr, netif_ip4_addr(netif), netif_ip4_netmask(netif)) &&
- 800e496:	687b      	ldr	r3, [r7, #4]
- 800e498:	681a      	ldr	r2, [r3, #0]
- 800e49a:	68fb      	ldr	r3, [r7, #12]
- 800e49c:	3304      	adds	r3, #4
- 800e49e:	681b      	ldr	r3, [r3, #0]
- 800e4a0:	405a      	eors	r2, r3
- 800e4a2:	68fb      	ldr	r3, [r7, #12]
- 800e4a4:	3308      	adds	r3, #8
- 800e4a6:	681b      	ldr	r3, [r3, #0]
- 800e4a8:	4013      	ands	r3, r2
- 800e4aa:	2b00      	cmp	r3, #0
- 800e4ac:	d012      	beq.n	800e4d4 <etharp_output+0xe0>
-        !ip4_addr_islinklocal(ipaddr)) {
- 800e4ae:	687b      	ldr	r3, [r7, #4]
- 800e4b0:	681b      	ldr	r3, [r3, #0]
- 800e4b2:	b29b      	uxth	r3, r3
-    if (!ip4_addr_netcmp(ipaddr, netif_ip4_addr(netif), netif_ip4_netmask(netif)) &&
- 800e4b4:	f64f 62a9 	movw	r2, #65193	; 0xfea9
- 800e4b8:	4293      	cmp	r3, r2
- 800e4ba:	d00b      	beq.n	800e4d4 <etharp_output+0xe0>
-        dst_addr = LWIP_HOOK_ETHARP_GET_GW(netif, ipaddr);
-        if (dst_addr == NULL)
-#endif /* LWIP_HOOK_ETHARP_GET_GW */
-        {
-          /* interface has default gateway? */
-          if (!ip4_addr_isany_val(*netif_ip4_gw(netif))) {
- 800e4bc:	68fb      	ldr	r3, [r7, #12]
- 800e4be:	330c      	adds	r3, #12
- 800e4c0:	681b      	ldr	r3, [r3, #0]
- 800e4c2:	2b00      	cmp	r3, #0
- 800e4c4:	d003      	beq.n	800e4ce <etharp_output+0xda>
-            /* send to hardware address of default gateway IP address */
-            dst_addr = netif_ip4_gw(netif);
- 800e4c6:	68fb      	ldr	r3, [r7, #12]
- 800e4c8:	330c      	adds	r3, #12
- 800e4ca:	61bb      	str	r3, [r7, #24]
- 800e4cc:	e002      	b.n	800e4d4 <etharp_output+0xe0>
-            /* no default gateway available */
-          } else {
-            /* no route to destination error (default gateway missing) */
-            return ERR_RTE;
- 800e4ce:	f06f 0303 	mvn.w	r3, #3
- 800e4d2:	e07d      	b.n	800e5d0 <etharp_output+0x1dc>
-    if (netif->hints != NULL) {
-      /* per-pcb cached entry was given */
-      netif_addr_idx_t etharp_cached_entry = netif->hints->addr_hint;
-      if (etharp_cached_entry < ARP_TABLE_SIZE) {
-#endif /* LWIP_NETIF_HWADDRHINT */
-        if ((arp_table[etharp_cached_entry].state >= ETHARP_STATE_STABLE) &&
- 800e4d4:	4b46      	ldr	r3, [pc, #280]	; (800e5f0 <etharp_output+0x1fc>)
- 800e4d6:	781b      	ldrb	r3, [r3, #0]
- 800e4d8:	4619      	mov	r1, r3
- 800e4da:	4a46      	ldr	r2, [pc, #280]	; (800e5f4 <etharp_output+0x200>)
- 800e4dc:	460b      	mov	r3, r1
- 800e4de:	005b      	lsls	r3, r3, #1
- 800e4e0:	440b      	add	r3, r1
- 800e4e2:	00db      	lsls	r3, r3, #3
- 800e4e4:	4413      	add	r3, r2
- 800e4e6:	3314      	adds	r3, #20
- 800e4e8:	781b      	ldrb	r3, [r3, #0]
- 800e4ea:	2b01      	cmp	r3, #1
- 800e4ec:	d925      	bls.n	800e53a <etharp_output+0x146>
-#if ETHARP_TABLE_MATCH_NETIF
-            (arp_table[etharp_cached_entry].netif == netif) &&
- 800e4ee:	4b40      	ldr	r3, [pc, #256]	; (800e5f0 <etharp_output+0x1fc>)
- 800e4f0:	781b      	ldrb	r3, [r3, #0]
- 800e4f2:	4619      	mov	r1, r3
- 800e4f4:	4a3f      	ldr	r2, [pc, #252]	; (800e5f4 <etharp_output+0x200>)
- 800e4f6:	460b      	mov	r3, r1
- 800e4f8:	005b      	lsls	r3, r3, #1
- 800e4fa:	440b      	add	r3, r1
- 800e4fc:	00db      	lsls	r3, r3, #3
- 800e4fe:	4413      	add	r3, r2
- 800e500:	3308      	adds	r3, #8
- 800e502:	681b      	ldr	r3, [r3, #0]
-        if ((arp_table[etharp_cached_entry].state >= ETHARP_STATE_STABLE) &&
- 800e504:	68fa      	ldr	r2, [r7, #12]
- 800e506:	429a      	cmp	r2, r3
- 800e508:	d117      	bne.n	800e53a <etharp_output+0x146>
-#endif
-            (ip4_addr_cmp(dst_addr, &arp_table[etharp_cached_entry].ipaddr))) {
- 800e50a:	69bb      	ldr	r3, [r7, #24]
- 800e50c:	681a      	ldr	r2, [r3, #0]
- 800e50e:	4b38      	ldr	r3, [pc, #224]	; (800e5f0 <etharp_output+0x1fc>)
- 800e510:	781b      	ldrb	r3, [r3, #0]
- 800e512:	4618      	mov	r0, r3
- 800e514:	4937      	ldr	r1, [pc, #220]	; (800e5f4 <etharp_output+0x200>)
- 800e516:	4603      	mov	r3, r0
- 800e518:	005b      	lsls	r3, r3, #1
- 800e51a:	4403      	add	r3, r0
- 800e51c:	00db      	lsls	r3, r3, #3
- 800e51e:	440b      	add	r3, r1
- 800e520:	3304      	adds	r3, #4
- 800e522:	681b      	ldr	r3, [r3, #0]
-            (arp_table[etharp_cached_entry].netif == netif) &&
- 800e524:	429a      	cmp	r2, r3
- 800e526:	d108      	bne.n	800e53a <etharp_output+0x146>
-          /* the per-pcb-cached entry is stable and the right one! */
-          ETHARP_STATS_INC(etharp.cachehit);
-          return etharp_output_to_arp_index(netif, q, etharp_cached_entry);
- 800e528:	4b31      	ldr	r3, [pc, #196]	; (800e5f0 <etharp_output+0x1fc>)
- 800e52a:	781b      	ldrb	r3, [r3, #0]
- 800e52c:	461a      	mov	r2, r3
- 800e52e:	68b9      	ldr	r1, [r7, #8]
- 800e530:	68f8      	ldr	r0, [r7, #12]
- 800e532:	f7ff fec5 	bl	800e2c0 <etharp_output_to_arp_index>
- 800e536:	4603      	mov	r3, r0
- 800e538:	e04a      	b.n	800e5d0 <etharp_output+0x1dc>
-    }
-#endif /* LWIP_NETIF_HWADDRHINT */
-
-    /* find stable entry: do this here since this is a critical path for
-       throughput and etharp_find_entry() is kind of slow */
-    for (i = 0; i < ARP_TABLE_SIZE; i++) {
- 800e53a:	2300      	movs	r3, #0
- 800e53c:	75fb      	strb	r3, [r7, #23]
- 800e53e:	e031      	b.n	800e5a4 <etharp_output+0x1b0>
-      if ((arp_table[i].state >= ETHARP_STATE_STABLE) &&
- 800e540:	7dfa      	ldrb	r2, [r7, #23]
- 800e542:	492c      	ldr	r1, [pc, #176]	; (800e5f4 <etharp_output+0x200>)
- 800e544:	4613      	mov	r3, r2
- 800e546:	005b      	lsls	r3, r3, #1
- 800e548:	4413      	add	r3, r2
- 800e54a:	00db      	lsls	r3, r3, #3
- 800e54c:	440b      	add	r3, r1
- 800e54e:	3314      	adds	r3, #20
- 800e550:	781b      	ldrb	r3, [r3, #0]
- 800e552:	2b01      	cmp	r3, #1
- 800e554:	d923      	bls.n	800e59e <etharp_output+0x1aa>
-#if ETHARP_TABLE_MATCH_NETIF
-          (arp_table[i].netif == netif) &&
- 800e556:	7dfa      	ldrb	r2, [r7, #23]
- 800e558:	4926      	ldr	r1, [pc, #152]	; (800e5f4 <etharp_output+0x200>)
- 800e55a:	4613      	mov	r3, r2
- 800e55c:	005b      	lsls	r3, r3, #1
- 800e55e:	4413      	add	r3, r2
- 800e560:	00db      	lsls	r3, r3, #3
- 800e562:	440b      	add	r3, r1
- 800e564:	3308      	adds	r3, #8
- 800e566:	681b      	ldr	r3, [r3, #0]
-      if ((arp_table[i].state >= ETHARP_STATE_STABLE) &&
- 800e568:	68fa      	ldr	r2, [r7, #12]
- 800e56a:	429a      	cmp	r2, r3
- 800e56c:	d117      	bne.n	800e59e <etharp_output+0x1aa>
-#endif
-          (ip4_addr_cmp(dst_addr, &arp_table[i].ipaddr))) {
- 800e56e:	69bb      	ldr	r3, [r7, #24]
- 800e570:	6819      	ldr	r1, [r3, #0]
- 800e572:	7dfa      	ldrb	r2, [r7, #23]
- 800e574:	481f      	ldr	r0, [pc, #124]	; (800e5f4 <etharp_output+0x200>)
- 800e576:	4613      	mov	r3, r2
- 800e578:	005b      	lsls	r3, r3, #1
- 800e57a:	4413      	add	r3, r2
- 800e57c:	00db      	lsls	r3, r3, #3
- 800e57e:	4403      	add	r3, r0
- 800e580:	3304      	adds	r3, #4
- 800e582:	681b      	ldr	r3, [r3, #0]
-          (arp_table[i].netif == netif) &&
- 800e584:	4299      	cmp	r1, r3
- 800e586:	d10a      	bne.n	800e59e <etharp_output+0x1aa>
-        /* found an existing, stable entry */
-        ETHARP_SET_ADDRHINT(netif, i);
- 800e588:	4a19      	ldr	r2, [pc, #100]	; (800e5f0 <etharp_output+0x1fc>)
- 800e58a:	7dfb      	ldrb	r3, [r7, #23]
- 800e58c:	7013      	strb	r3, [r2, #0]
-        return etharp_output_to_arp_index(netif, q, i);
- 800e58e:	7dfb      	ldrb	r3, [r7, #23]
- 800e590:	461a      	mov	r2, r3
- 800e592:	68b9      	ldr	r1, [r7, #8]
- 800e594:	68f8      	ldr	r0, [r7, #12]
- 800e596:	f7ff fe93 	bl	800e2c0 <etharp_output_to_arp_index>
- 800e59a:	4603      	mov	r3, r0
- 800e59c:	e018      	b.n	800e5d0 <etharp_output+0x1dc>
-    for (i = 0; i < ARP_TABLE_SIZE; i++) {
- 800e59e:	7dfb      	ldrb	r3, [r7, #23]
- 800e5a0:	3301      	adds	r3, #1
- 800e5a2:	75fb      	strb	r3, [r7, #23]
- 800e5a4:	7dfb      	ldrb	r3, [r7, #23]
- 800e5a6:	2b09      	cmp	r3, #9
- 800e5a8:	d9ca      	bls.n	800e540 <etharp_output+0x14c>
-      }
-    }
-    /* no stable entry found, use the (slower) query function:
-       queue on destination Ethernet address belonging to ipaddr */
-    return etharp_query(netif, dst_addr, q);
- 800e5aa:	68ba      	ldr	r2, [r7, #8]
- 800e5ac:	69b9      	ldr	r1, [r7, #24]
- 800e5ae:	68f8      	ldr	r0, [r7, #12]
- 800e5b0:	f000 f822 	bl	800e5f8 <etharp_query>
- 800e5b4:	4603      	mov	r3, r0
- 800e5b6:	e00b      	b.n	800e5d0 <etharp_output+0x1dc>
-  }
-
-  /* continuation for multicast/broadcast destinations */
-  /* obtain source Ethernet address of the given interface */
-  /* send packet directly on the link */
-  return ethernet_output(netif, q, (struct eth_addr *)(netif->hwaddr), dest, ETHTYPE_IP);
- 800e5b8:	68fb      	ldr	r3, [r7, #12]
- 800e5ba:	f103 0226 	add.w	r2, r3, #38	; 0x26
- 800e5be:	f44f 6300 	mov.w	r3, #2048	; 0x800
- 800e5c2:	9300      	str	r3, [sp, #0]
- 800e5c4:	69fb      	ldr	r3, [r7, #28]
- 800e5c6:	68b9      	ldr	r1, [r7, #8]
- 800e5c8:	68f8      	ldr	r0, [r7, #12]
- 800e5ca:	f001 fe01 	bl	80101d0 <ethernet_output>
- 800e5ce:	4603      	mov	r3, r0
-}
- 800e5d0:	4618      	mov	r0, r3
- 800e5d2:	3720      	adds	r7, #32
- 800e5d4:	46bd      	mov	sp, r7
- 800e5d6:	bd80      	pop	{r7, pc}
- 800e5d8:	080142dc 	.word	0x080142dc
- 800e5dc:	0801442c 	.word	0x0801442c
- 800e5e0:	08014354 	.word	0x08014354
- 800e5e4:	0801447c 	.word	0x0801447c
- 800e5e8:	0801441c 	.word	0x0801441c
- 800e5ec:	08014d98 	.word	0x08014d98
- 800e5f0:	24007cc0 	.word	0x24007cc0
- 800e5f4:	24007bd0 	.word	0x24007bd0
-
-0800e5f8 <etharp_query>:
- * - ERR_ARG Non-unicast address given, those will not appear in ARP cache.
- *
- */
-err_t
-etharp_query(struct netif *netif, const ip4_addr_t *ipaddr, struct pbuf *q)
-{
- 800e5f8:	b580      	push	{r7, lr}
- 800e5fa:	b08c      	sub	sp, #48	; 0x30
- 800e5fc:	af02      	add	r7, sp, #8
- 800e5fe:	60f8      	str	r0, [r7, #12]
- 800e600:	60b9      	str	r1, [r7, #8]
- 800e602:	607a      	str	r2, [r7, #4]
-  struct eth_addr *srcaddr = (struct eth_addr *)netif->hwaddr;
- 800e604:	68fb      	ldr	r3, [r7, #12]
- 800e606:	3326      	adds	r3, #38	; 0x26
- 800e608:	617b      	str	r3, [r7, #20]
-  err_t result = ERR_MEM;
- 800e60a:	23ff      	movs	r3, #255	; 0xff
- 800e60c:	f887 3027 	strb.w	r3, [r7, #39]	; 0x27
-  int is_new_entry = 0;
- 800e610:	2300      	movs	r3, #0
- 800e612:	623b      	str	r3, [r7, #32]
-  s16_t i_err;
-  netif_addr_idx_t i;
-
-  /* non-unicast address? */
-  if (ip4_addr_isbroadcast(ipaddr, netif) ||
- 800e614:	68bb      	ldr	r3, [r7, #8]
- 800e616:	681b      	ldr	r3, [r3, #0]
- 800e618:	68f9      	ldr	r1, [r7, #12]
- 800e61a:	4618      	mov	r0, r3
- 800e61c:	f000 feca 	bl	800f3b4 <ip4_addr_isbroadcast_u32>
- 800e620:	4603      	mov	r3, r0
- 800e622:	2b00      	cmp	r3, #0
- 800e624:	d10c      	bne.n	800e640 <etharp_query+0x48>
-      ip4_addr_ismulticast(ipaddr) ||
- 800e626:	68bb      	ldr	r3, [r7, #8]
- 800e628:	681b      	ldr	r3, [r3, #0]
- 800e62a:	f003 03f0 	and.w	r3, r3, #240	; 0xf0
-  if (ip4_addr_isbroadcast(ipaddr, netif) ||
- 800e62e:	2be0      	cmp	r3, #224	; 0xe0
- 800e630:	d006      	beq.n	800e640 <etharp_query+0x48>
-      ip4_addr_ismulticast(ipaddr) ||
- 800e632:	68bb      	ldr	r3, [r7, #8]
- 800e634:	2b00      	cmp	r3, #0
- 800e636:	d003      	beq.n	800e640 <etharp_query+0x48>
-      ip4_addr_isany(ipaddr)) {
- 800e638:	68bb      	ldr	r3, [r7, #8]
- 800e63a:	681b      	ldr	r3, [r3, #0]
- 800e63c:	2b00      	cmp	r3, #0
- 800e63e:	d102      	bne.n	800e646 <etharp_query+0x4e>
-    LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_query: will not add non-unicast IP address to ARP cache\n"));
-    return ERR_ARG;
- 800e640:	f06f 030f 	mvn.w	r3, #15
- 800e644:	e101      	b.n	800e84a <etharp_query+0x252>
-  }
-
-  /* find entry in ARP cache, ask to create entry if queueing packet */
-  i_err = etharp_find_entry(ipaddr, ETHARP_FLAG_TRY_HARD, netif);
- 800e646:	68fa      	ldr	r2, [r7, #12]
- 800e648:	2101      	movs	r1, #1
- 800e64a:	68b8      	ldr	r0, [r7, #8]
- 800e64c:	f7ff fb60 	bl	800dd10 <etharp_find_entry>
- 800e650:	4603      	mov	r3, r0
- 800e652:	827b      	strh	r3, [r7, #18]
-
-  /* could not find or create entry? */
-  if (i_err < 0) {
- 800e654:	f9b7 3012 	ldrsh.w	r3, [r7, #18]
- 800e658:	2b00      	cmp	r3, #0
- 800e65a:	da02      	bge.n	800e662 <etharp_query+0x6a>
-    LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_query: could not create ARP entry\n"));
-    if (q) {
-      LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_query: packet dropped\n"));
-      ETHARP_STATS_INC(etharp.memerr);
-    }
-    return (err_t)i_err;
- 800e65c:	8a7b      	ldrh	r3, [r7, #18]
- 800e65e:	b25b      	sxtb	r3, r3
- 800e660:	e0f3      	b.n	800e84a <etharp_query+0x252>
-  }
-  LWIP_ASSERT("type overflow", (size_t)i_err < NETIF_ADDR_IDX_MAX);
- 800e662:	8a7b      	ldrh	r3, [r7, #18]
- 800e664:	2b7e      	cmp	r3, #126	; 0x7e
- 800e666:	d906      	bls.n	800e676 <etharp_query+0x7e>
- 800e668:	4b7a      	ldr	r3, [pc, #488]	; (800e854 <etharp_query+0x25c>)
- 800e66a:	f240 32c1 	movw	r2, #961	; 0x3c1
- 800e66e:	497a      	ldr	r1, [pc, #488]	; (800e858 <etharp_query+0x260>)
- 800e670:	487a      	ldr	r0, [pc, #488]	; (800e85c <etharp_query+0x264>)
- 800e672:	f002 faa9 	bl	8010bc8 <iprintf>
-  i = (netif_addr_idx_t)i_err;
- 800e676:	8a7b      	ldrh	r3, [r7, #18]
- 800e678:	747b      	strb	r3, [r7, #17]
-
-  /* mark a fresh entry as pending (we just sent a request) */
-  if (arp_table[i].state == ETHARP_STATE_EMPTY) {
- 800e67a:	7c7a      	ldrb	r2, [r7, #17]
- 800e67c:	4978      	ldr	r1, [pc, #480]	; (800e860 <etharp_query+0x268>)
- 800e67e:	4613      	mov	r3, r2
- 800e680:	005b      	lsls	r3, r3, #1
- 800e682:	4413      	add	r3, r2
- 800e684:	00db      	lsls	r3, r3, #3
- 800e686:	440b      	add	r3, r1
- 800e688:	3314      	adds	r3, #20
- 800e68a:	781b      	ldrb	r3, [r3, #0]
- 800e68c:	2b00      	cmp	r3, #0
- 800e68e:	d115      	bne.n	800e6bc <etharp_query+0xc4>
-    is_new_entry = 1;
- 800e690:	2301      	movs	r3, #1
- 800e692:	623b      	str	r3, [r7, #32]
-    arp_table[i].state = ETHARP_STATE_PENDING;
- 800e694:	7c7a      	ldrb	r2, [r7, #17]
- 800e696:	4972      	ldr	r1, [pc, #456]	; (800e860 <etharp_query+0x268>)
- 800e698:	4613      	mov	r3, r2
- 800e69a:	005b      	lsls	r3, r3, #1
- 800e69c:	4413      	add	r3, r2
- 800e69e:	00db      	lsls	r3, r3, #3
- 800e6a0:	440b      	add	r3, r1
- 800e6a2:	3314      	adds	r3, #20
- 800e6a4:	2201      	movs	r2, #1
- 800e6a6:	701a      	strb	r2, [r3, #0]
-    /* record network interface for re-sending arp request in etharp_tmr */
-    arp_table[i].netif = netif;
- 800e6a8:	7c7a      	ldrb	r2, [r7, #17]
- 800e6aa:	496d      	ldr	r1, [pc, #436]	; (800e860 <etharp_query+0x268>)
- 800e6ac:	4613      	mov	r3, r2
- 800e6ae:	005b      	lsls	r3, r3, #1
- 800e6b0:	4413      	add	r3, r2
- 800e6b2:	00db      	lsls	r3, r3, #3
- 800e6b4:	440b      	add	r3, r1
- 800e6b6:	3308      	adds	r3, #8
- 800e6b8:	68fa      	ldr	r2, [r7, #12]
- 800e6ba:	601a      	str	r2, [r3, #0]
-  }
-
-  /* { i is either a STABLE or (new or existing) PENDING entry } */
-  LWIP_ASSERT("arp_table[i].state == PENDING or STABLE",
- 800e6bc:	7c7a      	ldrb	r2, [r7, #17]
- 800e6be:	4968      	ldr	r1, [pc, #416]	; (800e860 <etharp_query+0x268>)
- 800e6c0:	4613      	mov	r3, r2
- 800e6c2:	005b      	lsls	r3, r3, #1
- 800e6c4:	4413      	add	r3, r2
- 800e6c6:	00db      	lsls	r3, r3, #3
- 800e6c8:	440b      	add	r3, r1
- 800e6ca:	3314      	adds	r3, #20
- 800e6cc:	781b      	ldrb	r3, [r3, #0]
- 800e6ce:	2b01      	cmp	r3, #1
- 800e6d0:	d011      	beq.n	800e6f6 <etharp_query+0xfe>
- 800e6d2:	7c7a      	ldrb	r2, [r7, #17]
- 800e6d4:	4962      	ldr	r1, [pc, #392]	; (800e860 <etharp_query+0x268>)
- 800e6d6:	4613      	mov	r3, r2
- 800e6d8:	005b      	lsls	r3, r3, #1
- 800e6da:	4413      	add	r3, r2
- 800e6dc:	00db      	lsls	r3, r3, #3
- 800e6de:	440b      	add	r3, r1
- 800e6e0:	3314      	adds	r3, #20
- 800e6e2:	781b      	ldrb	r3, [r3, #0]
- 800e6e4:	2b01      	cmp	r3, #1
- 800e6e6:	d806      	bhi.n	800e6f6 <etharp_query+0xfe>
- 800e6e8:	4b5a      	ldr	r3, [pc, #360]	; (800e854 <etharp_query+0x25c>)
- 800e6ea:	f240 32cd 	movw	r2, #973	; 0x3cd
- 800e6ee:	495d      	ldr	r1, [pc, #372]	; (800e864 <etharp_query+0x26c>)
- 800e6f0:	485a      	ldr	r0, [pc, #360]	; (800e85c <etharp_query+0x264>)
- 800e6f2:	f002 fa69 	bl	8010bc8 <iprintf>
-              ((arp_table[i].state == ETHARP_STATE_PENDING) ||
-               (arp_table[i].state >= ETHARP_STATE_STABLE)));
-
-  /* do we have a new entry? or an implicit query request? */
-  if (is_new_entry || (q == NULL)) {
- 800e6f6:	6a3b      	ldr	r3, [r7, #32]
- 800e6f8:	2b00      	cmp	r3, #0
- 800e6fa:	d102      	bne.n	800e702 <etharp_query+0x10a>
- 800e6fc:	687b      	ldr	r3, [r7, #4]
- 800e6fe:	2b00      	cmp	r3, #0
- 800e700:	d10c      	bne.n	800e71c <etharp_query+0x124>
-    /* try to resolve it; send out ARP request */
-    result = etharp_request(netif, ipaddr);
- 800e702:	68b9      	ldr	r1, [r7, #8]
- 800e704:	68f8      	ldr	r0, [r7, #12]
- 800e706:	f000 f963 	bl	800e9d0 <etharp_request>
- 800e70a:	4603      	mov	r3, r0
- 800e70c:	f887 3027 	strb.w	r3, [r7, #39]	; 0x27
-      /* ARP request couldn't be sent */
-      /* We don't re-send arp request in etharp_tmr, but we still queue packets,
-         since this failure could be temporary, and the next packet calling
-         etharp_query again could lead to sending the queued packets. */
-    }
-    if (q == NULL) {
- 800e710:	687b      	ldr	r3, [r7, #4]
- 800e712:	2b00      	cmp	r3, #0
- 800e714:	d102      	bne.n	800e71c <etharp_query+0x124>
-      return result;
- 800e716:	f997 3027 	ldrsb.w	r3, [r7, #39]	; 0x27
- 800e71a:	e096      	b.n	800e84a <etharp_query+0x252>
-    }
-  }
-
-  /* packet given? */
-  LWIP_ASSERT("q != NULL", q != NULL);
- 800e71c:	687b      	ldr	r3, [r7, #4]
- 800e71e:	2b00      	cmp	r3, #0
- 800e720:	d106      	bne.n	800e730 <etharp_query+0x138>
- 800e722:	4b4c      	ldr	r3, [pc, #304]	; (800e854 <etharp_query+0x25c>)
- 800e724:	f240 32e1 	movw	r2, #993	; 0x3e1
- 800e728:	494f      	ldr	r1, [pc, #316]	; (800e868 <etharp_query+0x270>)
- 800e72a:	484c      	ldr	r0, [pc, #304]	; (800e85c <etharp_query+0x264>)
- 800e72c:	f002 fa4c 	bl	8010bc8 <iprintf>
-  /* stable entry? */
-  if (arp_table[i].state >= ETHARP_STATE_STABLE) {
- 800e730:	7c7a      	ldrb	r2, [r7, #17]
- 800e732:	494b      	ldr	r1, [pc, #300]	; (800e860 <etharp_query+0x268>)
- 800e734:	4613      	mov	r3, r2
- 800e736:	005b      	lsls	r3, r3, #1
- 800e738:	4413      	add	r3, r2
- 800e73a:	00db      	lsls	r3, r3, #3
- 800e73c:	440b      	add	r3, r1
- 800e73e:	3314      	adds	r3, #20
- 800e740:	781b      	ldrb	r3, [r3, #0]
- 800e742:	2b01      	cmp	r3, #1
- 800e744:	d917      	bls.n	800e776 <etharp_query+0x17e>
-    /* we have a valid IP->Ethernet address mapping */
-    ETHARP_SET_ADDRHINT(netif, i);
- 800e746:	4a49      	ldr	r2, [pc, #292]	; (800e86c <etharp_query+0x274>)
- 800e748:	7c7b      	ldrb	r3, [r7, #17]
- 800e74a:	7013      	strb	r3, [r2, #0]
-    /* send the packet */
-    result = ethernet_output(netif, q, srcaddr, &(arp_table[i].ethaddr), ETHTYPE_IP);
- 800e74c:	7c7a      	ldrb	r2, [r7, #17]
- 800e74e:	4613      	mov	r3, r2
- 800e750:	005b      	lsls	r3, r3, #1
- 800e752:	4413      	add	r3, r2
- 800e754:	00db      	lsls	r3, r3, #3
- 800e756:	3308      	adds	r3, #8
- 800e758:	4a41      	ldr	r2, [pc, #260]	; (800e860 <etharp_query+0x268>)
- 800e75a:	4413      	add	r3, r2
- 800e75c:	3304      	adds	r3, #4
- 800e75e:	f44f 6200 	mov.w	r2, #2048	; 0x800
- 800e762:	9200      	str	r2, [sp, #0]
- 800e764:	697a      	ldr	r2, [r7, #20]
- 800e766:	6879      	ldr	r1, [r7, #4]
- 800e768:	68f8      	ldr	r0, [r7, #12]
- 800e76a:	f001 fd31 	bl	80101d0 <ethernet_output>
- 800e76e:	4603      	mov	r3, r0
- 800e770:	f887 3027 	strb.w	r3, [r7, #39]	; 0x27
- 800e774:	e067      	b.n	800e846 <etharp_query+0x24e>
-    /* pending entry? (either just created or already pending */
-  } else if (arp_table[i].state == ETHARP_STATE_PENDING) {
- 800e776:	7c7a      	ldrb	r2, [r7, #17]
- 800e778:	4939      	ldr	r1, [pc, #228]	; (800e860 <etharp_query+0x268>)
- 800e77a:	4613      	mov	r3, r2
- 800e77c:	005b      	lsls	r3, r3, #1
- 800e77e:	4413      	add	r3, r2
- 800e780:	00db      	lsls	r3, r3, #3
- 800e782:	440b      	add	r3, r1
- 800e784:	3314      	adds	r3, #20
- 800e786:	781b      	ldrb	r3, [r3, #0]
- 800e788:	2b01      	cmp	r3, #1
- 800e78a:	d15c      	bne.n	800e846 <etharp_query+0x24e>
-    /* entry is still pending, queue the given packet 'q' */
-    struct pbuf *p;
-    int copy_needed = 0;
- 800e78c:	2300      	movs	r3, #0
- 800e78e:	61bb      	str	r3, [r7, #24]
-    /* IF q includes a pbuf that must be copied, copy the whole chain into a
-     * new PBUF_RAM. See the definition of PBUF_NEEDS_COPY for details. */
-    p = q;
- 800e790:	687b      	ldr	r3, [r7, #4]
- 800e792:	61fb      	str	r3, [r7, #28]
-    while (p) {
- 800e794:	e01c      	b.n	800e7d0 <etharp_query+0x1d8>
-      LWIP_ASSERT("no packet queues allowed!", (p->len != p->tot_len) || (p->next == 0));
- 800e796:	69fb      	ldr	r3, [r7, #28]
- 800e798:	895a      	ldrh	r2, [r3, #10]
- 800e79a:	69fb      	ldr	r3, [r7, #28]
- 800e79c:	891b      	ldrh	r3, [r3, #8]
- 800e79e:	429a      	cmp	r2, r3
- 800e7a0:	d10a      	bne.n	800e7b8 <etharp_query+0x1c0>
- 800e7a2:	69fb      	ldr	r3, [r7, #28]
- 800e7a4:	681b      	ldr	r3, [r3, #0]
- 800e7a6:	2b00      	cmp	r3, #0
- 800e7a8:	d006      	beq.n	800e7b8 <etharp_query+0x1c0>
- 800e7aa:	4b2a      	ldr	r3, [pc, #168]	; (800e854 <etharp_query+0x25c>)
- 800e7ac:	f240 32f1 	movw	r2, #1009	; 0x3f1
- 800e7b0:	492f      	ldr	r1, [pc, #188]	; (800e870 <etharp_query+0x278>)
- 800e7b2:	482a      	ldr	r0, [pc, #168]	; (800e85c <etharp_query+0x264>)
- 800e7b4:	f002 fa08 	bl	8010bc8 <iprintf>
-      if (PBUF_NEEDS_COPY(p)) {
- 800e7b8:	69fb      	ldr	r3, [r7, #28]
- 800e7ba:	7b1b      	ldrb	r3, [r3, #12]
- 800e7bc:	f003 0340 	and.w	r3, r3, #64	; 0x40
- 800e7c0:	2b00      	cmp	r3, #0
- 800e7c2:	d002      	beq.n	800e7ca <etharp_query+0x1d2>
-        copy_needed = 1;
- 800e7c4:	2301      	movs	r3, #1
- 800e7c6:	61bb      	str	r3, [r7, #24]
-        break;
- 800e7c8:	e005      	b.n	800e7d6 <etharp_query+0x1de>
-      }
-      p = p->next;
- 800e7ca:	69fb      	ldr	r3, [r7, #28]
- 800e7cc:	681b      	ldr	r3, [r3, #0]
- 800e7ce:	61fb      	str	r3, [r7, #28]
-    while (p) {
- 800e7d0:	69fb      	ldr	r3, [r7, #28]
- 800e7d2:	2b00      	cmp	r3, #0
- 800e7d4:	d1df      	bne.n	800e796 <etharp_query+0x19e>
-    }
-    if (copy_needed) {
- 800e7d6:	69bb      	ldr	r3, [r7, #24]
- 800e7d8:	2b00      	cmp	r3, #0
- 800e7da:	d007      	beq.n	800e7ec <etharp_query+0x1f4>
-      /* copy the whole packet into new pbufs */
-      p = pbuf_clone(PBUF_LINK, PBUF_RAM, q);
- 800e7dc:	687a      	ldr	r2, [r7, #4]
- 800e7de:	f44f 7120 	mov.w	r1, #640	; 0x280
- 800e7e2:	200e      	movs	r0, #14
- 800e7e4:	f7f8 fe52 	bl	800748c <pbuf_clone>
- 800e7e8:	61f8      	str	r0, [r7, #28]
- 800e7ea:	e004      	b.n	800e7f6 <etharp_query+0x1fe>
-    } else {
-      /* referencing the old pbuf is enough */
-      p = q;
- 800e7ec:	687b      	ldr	r3, [r7, #4]
- 800e7ee:	61fb      	str	r3, [r7, #28]
-      pbuf_ref(p);
- 800e7f0:	69f8      	ldr	r0, [r7, #28]
- 800e7f2:	f7f8 fc8f 	bl	8007114 <pbuf_ref>
-    }
-    /* packet could be taken over? */
-    if (p != NULL) {
- 800e7f6:	69fb      	ldr	r3, [r7, #28]
- 800e7f8:	2b00      	cmp	r3, #0
- 800e7fa:	d021      	beq.n	800e840 <etharp_query+0x248>
-        LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_query: could not queue a copy of PBUF_REF packet %p (out of memory)\n", (void *)q));
-        result = ERR_MEM;
-      }
-#else /* ARP_QUEUEING */
-      /* always queue one packet per ARP request only, freeing a previously queued packet */
-      if (arp_table[i].q != NULL) {
- 800e7fc:	7c7a      	ldrb	r2, [r7, #17]
- 800e7fe:	4918      	ldr	r1, [pc, #96]	; (800e860 <etharp_query+0x268>)
- 800e800:	4613      	mov	r3, r2
- 800e802:	005b      	lsls	r3, r3, #1
- 800e804:	4413      	add	r3, r2
- 800e806:	00db      	lsls	r3, r3, #3
- 800e808:	440b      	add	r3, r1
- 800e80a:	681b      	ldr	r3, [r3, #0]
- 800e80c:	2b00      	cmp	r3, #0
- 800e80e:	d00a      	beq.n	800e826 <etharp_query+0x22e>
-        LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_query: dropped previously queued packet %p for ARP entry %"U16_F"\n", (void *)q, (u16_t)i));
-        pbuf_free(arp_table[i].q);
- 800e810:	7c7a      	ldrb	r2, [r7, #17]
- 800e812:	4913      	ldr	r1, [pc, #76]	; (800e860 <etharp_query+0x268>)
- 800e814:	4613      	mov	r3, r2
- 800e816:	005b      	lsls	r3, r3, #1
- 800e818:	4413      	add	r3, r2
- 800e81a:	00db      	lsls	r3, r3, #3
- 800e81c:	440b      	add	r3, r1
- 800e81e:	681b      	ldr	r3, [r3, #0]
- 800e820:	4618      	mov	r0, r3
- 800e822:	f7f8 fbd7 	bl	8006fd4 <pbuf_free>
-      }
-      arp_table[i].q = p;
- 800e826:	7c7a      	ldrb	r2, [r7, #17]
- 800e828:	490d      	ldr	r1, [pc, #52]	; (800e860 <etharp_query+0x268>)
- 800e82a:	4613      	mov	r3, r2
- 800e82c:	005b      	lsls	r3, r3, #1
- 800e82e:	4413      	add	r3, r2
- 800e830:	00db      	lsls	r3, r3, #3
- 800e832:	440b      	add	r3, r1
- 800e834:	69fa      	ldr	r2, [r7, #28]
- 800e836:	601a      	str	r2, [r3, #0]
-      result = ERR_OK;
- 800e838:	2300      	movs	r3, #0
- 800e83a:	f887 3027 	strb.w	r3, [r7, #39]	; 0x27
- 800e83e:	e002      	b.n	800e846 <etharp_query+0x24e>
-      LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_query: queued packet %p on ARP entry %"U16_F"\n", (void *)q, (u16_t)i));
-#endif /* ARP_QUEUEING */
-    } else {
-      ETHARP_STATS_INC(etharp.memerr);
-      LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_query: could not queue a copy of PBUF_REF packet %p (out of memory)\n", (void *)q));
-      result = ERR_MEM;
- 800e840:	23ff      	movs	r3, #255	; 0xff
- 800e842:	f887 3027 	strb.w	r3, [r7, #39]	; 0x27
-    }
-  }
-  return result;
- 800e846:	f997 3027 	ldrsb.w	r3, [r7, #39]	; 0x27
-}
- 800e84a:	4618      	mov	r0, r3
- 800e84c:	3728      	adds	r7, #40	; 0x28
- 800e84e:	46bd      	mov	sp, r7
- 800e850:	bd80      	pop	{r7, pc}
- 800e852:	bf00      	nop
- 800e854:	080142dc 	.word	0x080142dc
- 800e858:	08014488 	.word	0x08014488
- 800e85c:	08014354 	.word	0x08014354
- 800e860:	24007bd0 	.word	0x24007bd0
- 800e864:	08014498 	.word	0x08014498
- 800e868:	0801447c 	.word	0x0801447c
- 800e86c:	24007cc0 	.word	0x24007cc0
- 800e870:	080144c0 	.word	0x080144c0
-
-0800e874 <etharp_raw>:
-etharp_raw(struct netif *netif, const struct eth_addr *ethsrc_addr,
-           const struct eth_addr *ethdst_addr,
-           const struct eth_addr *hwsrc_addr, const ip4_addr_t *ipsrc_addr,
-           const struct eth_addr *hwdst_addr, const ip4_addr_t *ipdst_addr,
-           const u16_t opcode)
-{
- 800e874:	b580      	push	{r7, lr}
- 800e876:	b08a      	sub	sp, #40	; 0x28
- 800e878:	af02      	add	r7, sp, #8
- 800e87a:	60f8      	str	r0, [r7, #12]
- 800e87c:	60b9      	str	r1, [r7, #8]
- 800e87e:	607a      	str	r2, [r7, #4]
- 800e880:	603b      	str	r3, [r7, #0]
-  struct pbuf *p;
-  err_t result = ERR_OK;
- 800e882:	2300      	movs	r3, #0
- 800e884:	77fb      	strb	r3, [r7, #31]
-  struct etharp_hdr *hdr;
-
-  LWIP_ASSERT("netif != NULL", netif != NULL);
- 800e886:	68fb      	ldr	r3, [r7, #12]
- 800e888:	2b00      	cmp	r3, #0
- 800e88a:	d106      	bne.n	800e89a <etharp_raw+0x26>
- 800e88c:	4b3a      	ldr	r3, [pc, #232]	; (800e978 <etharp_raw+0x104>)
- 800e88e:	f240 4257 	movw	r2, #1111	; 0x457
- 800e892:	493a      	ldr	r1, [pc, #232]	; (800e97c <etharp_raw+0x108>)
- 800e894:	483a      	ldr	r0, [pc, #232]	; (800e980 <etharp_raw+0x10c>)
- 800e896:	f002 f997 	bl	8010bc8 <iprintf>
-
-  /* allocate a pbuf for the outgoing ARP request packet */
-  p = pbuf_alloc(PBUF_LINK, SIZEOF_ETHARP_HDR, PBUF_RAM);
- 800e89a:	f44f 7220 	mov.w	r2, #640	; 0x280
- 800e89e:	211c      	movs	r1, #28
- 800e8a0:	200e      	movs	r0, #14
- 800e8a2:	f7f8 f8b3 	bl	8006a0c <pbuf_alloc>
- 800e8a6:	61b8      	str	r0, [r7, #24]
-  /* could allocate a pbuf for an ARP request? */
-  if (p == NULL) {
- 800e8a8:	69bb      	ldr	r3, [r7, #24]
- 800e8aa:	2b00      	cmp	r3, #0
- 800e8ac:	d102      	bne.n	800e8b4 <etharp_raw+0x40>
-    LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS,
-                ("etharp_raw: could not allocate pbuf for ARP request.\n"));
-    ETHARP_STATS_INC(etharp.memerr);
-    return ERR_MEM;
- 800e8ae:	f04f 33ff 	mov.w	r3, #4294967295
- 800e8b2:	e05d      	b.n	800e970 <etharp_raw+0xfc>
-  }
-  LWIP_ASSERT("check that first pbuf can hold struct etharp_hdr",
- 800e8b4:	69bb      	ldr	r3, [r7, #24]
- 800e8b6:	895b      	ldrh	r3, [r3, #10]
- 800e8b8:	2b1b      	cmp	r3, #27
- 800e8ba:	d806      	bhi.n	800e8ca <etharp_raw+0x56>
- 800e8bc:	4b2e      	ldr	r3, [pc, #184]	; (800e978 <etharp_raw+0x104>)
- 800e8be:	f240 4262 	movw	r2, #1122	; 0x462
- 800e8c2:	4930      	ldr	r1, [pc, #192]	; (800e984 <etharp_raw+0x110>)
- 800e8c4:	482e      	ldr	r0, [pc, #184]	; (800e980 <etharp_raw+0x10c>)
- 800e8c6:	f002 f97f 	bl	8010bc8 <iprintf>
-              (p->len >= SIZEOF_ETHARP_HDR));
-
-  hdr = (struct etharp_hdr *)p->payload;
- 800e8ca:	69bb      	ldr	r3, [r7, #24]
- 800e8cc:	685b      	ldr	r3, [r3, #4]
- 800e8ce:	617b      	str	r3, [r7, #20]
-  LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_raw: sending raw ARP packet.\n"));
-  hdr->opcode = lwip_htons(opcode);
- 800e8d0:	8ebb      	ldrh	r3, [r7, #52]	; 0x34
- 800e8d2:	4618      	mov	r0, r3
- 800e8d4:	f7f6 fe3a 	bl	800554c <lwip_htons>
- 800e8d8:	4603      	mov	r3, r0
- 800e8da:	461a      	mov	r2, r3
- 800e8dc:	697b      	ldr	r3, [r7, #20]
- 800e8de:	80da      	strh	r2, [r3, #6]
-
-  LWIP_ASSERT("netif->hwaddr_len must be the same as ETH_HWADDR_LEN for etharp!",
- 800e8e0:	68fb      	ldr	r3, [r7, #12]
- 800e8e2:	f893 302c 	ldrb.w	r3, [r3, #44]	; 0x2c
- 800e8e6:	2b06      	cmp	r3, #6
- 800e8e8:	d006      	beq.n	800e8f8 <etharp_raw+0x84>
- 800e8ea:	4b23      	ldr	r3, [pc, #140]	; (800e978 <etharp_raw+0x104>)
- 800e8ec:	f240 4269 	movw	r2, #1129	; 0x469
- 800e8f0:	4925      	ldr	r1, [pc, #148]	; (800e988 <etharp_raw+0x114>)
- 800e8f2:	4823      	ldr	r0, [pc, #140]	; (800e980 <etharp_raw+0x10c>)
- 800e8f4:	f002 f968 	bl	8010bc8 <iprintf>
-              (netif->hwaddr_len == ETH_HWADDR_LEN));
-
-  /* Write the ARP MAC-Addresses */
-  SMEMCPY(&hdr->shwaddr, hwsrc_addr, ETH_HWADDR_LEN);
- 800e8f8:	697b      	ldr	r3, [r7, #20]
- 800e8fa:	3308      	adds	r3, #8
- 800e8fc:	2206      	movs	r2, #6
- 800e8fe:	6839      	ldr	r1, [r7, #0]
- 800e900:	4618      	mov	r0, r3
- 800e902:	f002 fb42 	bl	8010f8a <memcpy>
-  SMEMCPY(&hdr->dhwaddr, hwdst_addr, ETH_HWADDR_LEN);
- 800e906:	697b      	ldr	r3, [r7, #20]
- 800e908:	3312      	adds	r3, #18
- 800e90a:	2206      	movs	r2, #6
- 800e90c:	6af9      	ldr	r1, [r7, #44]	; 0x2c
- 800e90e:	4618      	mov	r0, r3
- 800e910:	f002 fb3b 	bl	8010f8a <memcpy>
-  /* Copy struct ip4_addr_wordaligned to aligned ip4_addr, to support compilers without
-   * structure packing. */
-  IPADDR_WORDALIGNED_COPY_FROM_IP4_ADDR_T(&hdr->sipaddr, ipsrc_addr);
- 800e914:	697b      	ldr	r3, [r7, #20]
- 800e916:	330e      	adds	r3, #14
- 800e918:	6aba      	ldr	r2, [r7, #40]	; 0x28
- 800e91a:	6812      	ldr	r2, [r2, #0]
- 800e91c:	601a      	str	r2, [r3, #0]
-  IPADDR_WORDALIGNED_COPY_FROM_IP4_ADDR_T(&hdr->dipaddr, ipdst_addr);
- 800e91e:	697b      	ldr	r3, [r7, #20]
- 800e920:	3318      	adds	r3, #24
- 800e922:	6b3a      	ldr	r2, [r7, #48]	; 0x30
- 800e924:	6812      	ldr	r2, [r2, #0]
- 800e926:	601a      	str	r2, [r3, #0]
-
-  hdr->hwtype = PP_HTONS(LWIP_IANA_HWTYPE_ETHERNET);
- 800e928:	697b      	ldr	r3, [r7, #20]
- 800e92a:	2200      	movs	r2, #0
- 800e92c:	701a      	strb	r2, [r3, #0]
- 800e92e:	2200      	movs	r2, #0
- 800e930:	f042 0201 	orr.w	r2, r2, #1
- 800e934:	705a      	strb	r2, [r3, #1]
-  hdr->proto = PP_HTONS(ETHTYPE_IP);
- 800e936:	697b      	ldr	r3, [r7, #20]
- 800e938:	2200      	movs	r2, #0
- 800e93a:	f042 0208 	orr.w	r2, r2, #8
- 800e93e:	709a      	strb	r2, [r3, #2]
- 800e940:	2200      	movs	r2, #0
- 800e942:	70da      	strb	r2, [r3, #3]
-  /* set hwlen and protolen */
-  hdr->hwlen = ETH_HWADDR_LEN;
- 800e944:	697b      	ldr	r3, [r7, #20]
- 800e946:	2206      	movs	r2, #6
- 800e948:	711a      	strb	r2, [r3, #4]
-  hdr->protolen = sizeof(ip4_addr_t);
- 800e94a:	697b      	ldr	r3, [r7, #20]
- 800e94c:	2204      	movs	r2, #4
- 800e94e:	715a      	strb	r2, [r3, #5]
-  if (ip4_addr_islinklocal(ipsrc_addr)) {
-    ethernet_output(netif, p, ethsrc_addr, &ethbroadcast, ETHTYPE_ARP);
-  } else
-#endif /* LWIP_AUTOIP */
-  {
-    ethernet_output(netif, p, ethsrc_addr, ethdst_addr, ETHTYPE_ARP);
- 800e950:	f640 0306 	movw	r3, #2054	; 0x806
- 800e954:	9300      	str	r3, [sp, #0]
- 800e956:	687b      	ldr	r3, [r7, #4]
- 800e958:	68ba      	ldr	r2, [r7, #8]
- 800e95a:	69b9      	ldr	r1, [r7, #24]
- 800e95c:	68f8      	ldr	r0, [r7, #12]
- 800e95e:	f001 fc37 	bl	80101d0 <ethernet_output>
-  }
-
-  ETHARP_STATS_INC(etharp.xmit);
-  /* free ARP query packet */
-  pbuf_free(p);
- 800e962:	69b8      	ldr	r0, [r7, #24]
- 800e964:	f7f8 fb36 	bl	8006fd4 <pbuf_free>
-  p = NULL;
- 800e968:	2300      	movs	r3, #0
- 800e96a:	61bb      	str	r3, [r7, #24]
-  /* could not allocate pbuf for ARP request */
-
-  return result;
- 800e96c:	f997 301f 	ldrsb.w	r3, [r7, #31]
-}
- 800e970:	4618      	mov	r0, r3
- 800e972:	3720      	adds	r7, #32
- 800e974:	46bd      	mov	sp, r7
- 800e976:	bd80      	pop	{r7, pc}
- 800e978:	080142dc 	.word	0x080142dc
- 800e97c:	0801442c 	.word	0x0801442c
- 800e980:	08014354 	.word	0x08014354
- 800e984:	080144dc 	.word	0x080144dc
- 800e988:	08014510 	.word	0x08014510
-
-0800e98c <etharp_request_dst>:
- *         ERR_MEM if the ARP packet couldn't be allocated
- *         any other err_t on failure
- */
-static err_t
-etharp_request_dst(struct netif *netif, const ip4_addr_t *ipaddr, const struct eth_addr *hw_dst_addr)
-{
- 800e98c:	b580      	push	{r7, lr}
- 800e98e:	b088      	sub	sp, #32
- 800e990:	af04      	add	r7, sp, #16
- 800e992:	60f8      	str	r0, [r7, #12]
- 800e994:	60b9      	str	r1, [r7, #8]
- 800e996:	607a      	str	r2, [r7, #4]
-  return etharp_raw(netif, (struct eth_addr *)netif->hwaddr, hw_dst_addr,
- 800e998:	68fb      	ldr	r3, [r7, #12]
- 800e99a:	f103 0126 	add.w	r1, r3, #38	; 0x26
-                    (struct eth_addr *)netif->hwaddr, netif_ip4_addr(netif), &ethzero,
- 800e99e:	68fb      	ldr	r3, [r7, #12]
- 800e9a0:	f103 0026 	add.w	r0, r3, #38	; 0x26
- 800e9a4:	68fb      	ldr	r3, [r7, #12]
- 800e9a6:	3304      	adds	r3, #4
-  return etharp_raw(netif, (struct eth_addr *)netif->hwaddr, hw_dst_addr,
- 800e9a8:	2201      	movs	r2, #1
- 800e9aa:	9203      	str	r2, [sp, #12]
- 800e9ac:	68ba      	ldr	r2, [r7, #8]
- 800e9ae:	9202      	str	r2, [sp, #8]
- 800e9b0:	4a06      	ldr	r2, [pc, #24]	; (800e9cc <etharp_request_dst+0x40>)
- 800e9b2:	9201      	str	r2, [sp, #4]
- 800e9b4:	9300      	str	r3, [sp, #0]
- 800e9b6:	4603      	mov	r3, r0
- 800e9b8:	687a      	ldr	r2, [r7, #4]
- 800e9ba:	68f8      	ldr	r0, [r7, #12]
- 800e9bc:	f7ff ff5a 	bl	800e874 <etharp_raw>
- 800e9c0:	4603      	mov	r3, r0
-                    ipaddr, ARP_REQUEST);
-}
- 800e9c2:	4618      	mov	r0, r3
- 800e9c4:	3710      	adds	r7, #16
- 800e9c6:	46bd      	mov	sp, r7
- 800e9c8:	bd80      	pop	{r7, pc}
- 800e9ca:	bf00      	nop
- 800e9cc:	08014da0 	.word	0x08014da0
-
-0800e9d0 <etharp_request>:
- *         ERR_MEM if the ARP packet couldn't be allocated
- *         any other err_t on failure
- */
-err_t
-etharp_request(struct netif *netif, const ip4_addr_t *ipaddr)
-{
- 800e9d0:	b580      	push	{r7, lr}
- 800e9d2:	b082      	sub	sp, #8
- 800e9d4:	af00      	add	r7, sp, #0
- 800e9d6:	6078      	str	r0, [r7, #4]
- 800e9d8:	6039      	str	r1, [r7, #0]
-  LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_request: sending ARP request.\n"));
-  return etharp_request_dst(netif, ipaddr, &ethbroadcast);
- 800e9da:	4a05      	ldr	r2, [pc, #20]	; (800e9f0 <etharp_request+0x20>)
- 800e9dc:	6839      	ldr	r1, [r7, #0]
- 800e9de:	6878      	ldr	r0, [r7, #4]
- 800e9e0:	f7ff ffd4 	bl	800e98c <etharp_request_dst>
- 800e9e4:	4603      	mov	r3, r0
-}
- 800e9e6:	4618      	mov	r0, r3
- 800e9e8:	3708      	adds	r7, #8
- 800e9ea:	46bd      	mov	sp, r7
- 800e9ec:	bd80      	pop	{r7, pc}
- 800e9ee:	bf00      	nop
- 800e9f0:	08014d98 	.word	0x08014d98
-
-0800e9f4 <icmp_input>:
- * @param p the icmp echo request packet, p->payload pointing to the icmp header
- * @param inp the netif on which this packet was received
- */
-void
-icmp_input(struct pbuf *p, struct netif *inp)
-{
- 800e9f4:	b580      	push	{r7, lr}
- 800e9f6:	b08e      	sub	sp, #56	; 0x38
- 800e9f8:	af04      	add	r7, sp, #16
- 800e9fa:	6078      	str	r0, [r7, #4]
- 800e9fc:	6039      	str	r1, [r7, #0]
-  const ip4_addr_t *src;
-
-  ICMP_STATS_INC(icmp.recv);
-  MIB2_STATS_INC(mib2.icmpinmsgs);
-
-  iphdr_in = ip4_current_header();
- 800e9fe:	4ba4      	ldr	r3, [pc, #656]	; (800ec90 <icmp_input+0x29c>)
- 800ea00:	689b      	ldr	r3, [r3, #8]
- 800ea02:	627b      	str	r3, [r7, #36]	; 0x24
-  hlen = IPH_HL_BYTES(iphdr_in);
- 800ea04:	6a7b      	ldr	r3, [r7, #36]	; 0x24
- 800ea06:	781b      	ldrb	r3, [r3, #0]
- 800ea08:	f003 030f 	and.w	r3, r3, #15
- 800ea0c:	b2db      	uxtb	r3, r3
- 800ea0e:	009b      	lsls	r3, r3, #2
- 800ea10:	b2db      	uxtb	r3, r3
- 800ea12:	847b      	strh	r3, [r7, #34]	; 0x22
-  if (hlen < IP_HLEN) {
- 800ea14:	8c7b      	ldrh	r3, [r7, #34]	; 0x22
- 800ea16:	2b13      	cmp	r3, #19
- 800ea18:	d805      	bhi.n	800ea26 <icmp_input+0x32>
-    LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: short IP header (%"S16_F" bytes) received\n", hlen));
- 800ea1a:	8c7b      	ldrh	r3, [r7, #34]	; 0x22
- 800ea1c:	4619      	mov	r1, r3
- 800ea1e:	489d      	ldr	r0, [pc, #628]	; (800ec94 <icmp_input+0x2a0>)
- 800ea20:	f002 f8d2 	bl	8010bc8 <iprintf>
-    goto lenerr;
- 800ea24:	e128      	b.n	800ec78 <icmp_input+0x284>
-  }
-  if (p->len < sizeof(u16_t) * 2) {
- 800ea26:	687b      	ldr	r3, [r7, #4]
- 800ea28:	895b      	ldrh	r3, [r3, #10]
- 800ea2a:	2b03      	cmp	r3, #3
- 800ea2c:	d806      	bhi.n	800ea3c <icmp_input+0x48>
-    LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: short ICMP (%"U16_F" bytes) received\n", p->tot_len));
- 800ea2e:	687b      	ldr	r3, [r7, #4]
- 800ea30:	891b      	ldrh	r3, [r3, #8]
- 800ea32:	4619      	mov	r1, r3
- 800ea34:	4898      	ldr	r0, [pc, #608]	; (800ec98 <icmp_input+0x2a4>)
- 800ea36:	f002 f8c7 	bl	8010bc8 <iprintf>
-    goto lenerr;
- 800ea3a:	e11d      	b.n	800ec78 <icmp_input+0x284>
-  }
-
-  type = *((u8_t *)p->payload);
- 800ea3c:	687b      	ldr	r3, [r7, #4]
- 800ea3e:	685b      	ldr	r3, [r3, #4]
- 800ea40:	781b      	ldrb	r3, [r3, #0]
- 800ea42:	f887 3021 	strb.w	r3, [r7, #33]	; 0x21
-#ifdef LWIP_DEBUG
-  code = *(((u8_t *)p->payload) + 1);
- 800ea46:	687b      	ldr	r3, [r7, #4]
- 800ea48:	685b      	ldr	r3, [r3, #4]
- 800ea4a:	785b      	ldrb	r3, [r3, #1]
- 800ea4c:	f887 3020 	strb.w	r3, [r7, #32]
-  /* if debug is enabled but debug statement below is somehow disabled: */
-  LWIP_UNUSED_ARG(code);
-#endif /* LWIP_DEBUG */
-  switch (type) {
- 800ea50:	f897 3021 	ldrb.w	r3, [r7, #33]	; 0x21
- 800ea54:	2b00      	cmp	r3, #0
- 800ea56:	f000 8108 	beq.w	800ec6a <icmp_input+0x276>
- 800ea5a:	2b08      	cmp	r3, #8
- 800ea5c:	f040 80fc 	bne.w	800ec58 <icmp_input+0x264>
-         (as obviously, an echo request has been sent, too). */
-      MIB2_STATS_INC(mib2.icmpinechoreps);
-      break;
-    case ICMP_ECHO:
-      MIB2_STATS_INC(mib2.icmpinechos);
-      src = ip4_current_dest_addr();
- 800ea60:	4b8e      	ldr	r3, [pc, #568]	; (800ec9c <icmp_input+0x2a8>)
- 800ea62:	61fb      	str	r3, [r7, #28]
-      /* multicast destination address? */
-      if (ip4_addr_ismulticast(ip4_current_dest_addr())) {
- 800ea64:	4b8a      	ldr	r3, [pc, #552]	; (800ec90 <icmp_input+0x29c>)
- 800ea66:	695b      	ldr	r3, [r3, #20]
- 800ea68:	f003 03f0 	and.w	r3, r3, #240	; 0xf0
- 800ea6c:	2be0      	cmp	r3, #224	; 0xe0
- 800ea6e:	d103      	bne.n	800ea78 <icmp_input+0x84>
-#if LWIP_MULTICAST_PING
-        /* For multicast, use address of receiving interface as source address */
-        src = netif_ip4_addr(inp);
-#else /* LWIP_MULTICAST_PING */
-        LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: Not echoing to multicast pings\n"));
- 800ea70:	488b      	ldr	r0, [pc, #556]	; (800eca0 <icmp_input+0x2ac>)
- 800ea72:	f002 f917 	bl	8010ca4 <puts>
-        goto icmperr;
- 800ea76:	e103      	b.n	800ec80 <icmp_input+0x28c>
-#endif /* LWIP_MULTICAST_PING */
-      }
-      /* broadcast destination address? */
-      if (ip4_addr_isbroadcast(ip4_current_dest_addr(), ip_current_netif())) {
- 800ea78:	4b85      	ldr	r3, [pc, #532]	; (800ec90 <icmp_input+0x29c>)
- 800ea7a:	695b      	ldr	r3, [r3, #20]
- 800ea7c:	4a84      	ldr	r2, [pc, #528]	; (800ec90 <icmp_input+0x29c>)
- 800ea7e:	6812      	ldr	r2, [r2, #0]
- 800ea80:	4611      	mov	r1, r2
- 800ea82:	4618      	mov	r0, r3
- 800ea84:	f000 fc96 	bl	800f3b4 <ip4_addr_isbroadcast_u32>
- 800ea88:	4603      	mov	r3, r0
- 800ea8a:	2b00      	cmp	r3, #0
- 800ea8c:	d003      	beq.n	800ea96 <icmp_input+0xa2>
-#if LWIP_BROADCAST_PING
-        /* For broadcast, use address of receiving interface as source address */
-        src = netif_ip4_addr(inp);
-#else /* LWIP_BROADCAST_PING */
-        LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: Not echoing to broadcast pings\n"));
- 800ea8e:	4885      	ldr	r0, [pc, #532]	; (800eca4 <icmp_input+0x2b0>)
- 800ea90:	f002 f908 	bl	8010ca4 <puts>
-        goto icmperr;
- 800ea94:	e0f4      	b.n	800ec80 <icmp_input+0x28c>
-#endif /* LWIP_BROADCAST_PING */
-      }
-      LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: ping\n"));
- 800ea96:	4884      	ldr	r0, [pc, #528]	; (800eca8 <icmp_input+0x2b4>)
- 800ea98:	f002 f904 	bl	8010ca4 <puts>
-      if (p->tot_len < sizeof(struct icmp_echo_hdr)) {
- 800ea9c:	687b      	ldr	r3, [r7, #4]
- 800ea9e:	891b      	ldrh	r3, [r3, #8]
- 800eaa0:	2b07      	cmp	r3, #7
- 800eaa2:	d803      	bhi.n	800eaac <icmp_input+0xb8>
-        LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: bad ICMP echo received\n"));
- 800eaa4:	4881      	ldr	r0, [pc, #516]	; (800ecac <icmp_input+0x2b8>)
- 800eaa6:	f002 f8fd 	bl	8010ca4 <puts>
-        goto lenerr;
- 800eaaa:	e0e5      	b.n	800ec78 <icmp_input+0x284>
-      }
-#if CHECKSUM_CHECK_ICMP
-      IF__NETIF_CHECKSUM_ENABLED(inp, NETIF_CHECKSUM_CHECK_ICMP) {
-        if (inet_chksum_pbuf(p) != 0) {
- 800eaac:	6878      	ldr	r0, [r7, #4]
- 800eaae:	f7f6 fdea 	bl	8005686 <inet_chksum_pbuf>
- 800eab2:	4603      	mov	r3, r0
- 800eab4:	2b00      	cmp	r3, #0
- 800eab6:	d006      	beq.n	800eac6 <icmp_input+0xd2>
-          LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: checksum failed for received ICMP echo\n"));
- 800eab8:	487d      	ldr	r0, [pc, #500]	; (800ecb0 <icmp_input+0x2bc>)
- 800eaba:	f002 f8f3 	bl	8010ca4 <puts>
-          pbuf_free(p);
- 800eabe:	6878      	ldr	r0, [r7, #4]
- 800eac0:	f7f8 fa88 	bl	8006fd4 <pbuf_free>
-          ICMP_STATS_INC(icmp.chkerr);
-          MIB2_STATS_INC(mib2.icmpinerrors);
-          return;
- 800eac4:	e0e0      	b.n	800ec88 <icmp_input+0x294>
-        }
-      }
-#endif
-#if LWIP_ICMP_ECHO_CHECK_INPUT_PBUF_LEN
-      if (pbuf_add_header(p, hlen + PBUF_LINK_HLEN + PBUF_LINK_ENCAPSULATION_HLEN)) {
- 800eac6:	8c7b      	ldrh	r3, [r7, #34]	; 0x22
- 800eac8:	330e      	adds	r3, #14
- 800eaca:	4619      	mov	r1, r3
- 800eacc:	6878      	ldr	r0, [r7, #4]
- 800eace:	f7f8 f9eb 	bl	8006ea8 <pbuf_add_header>
- 800ead2:	4603      	mov	r3, r0
- 800ead4:	2b00      	cmp	r3, #0
- 800ead6:	d057      	beq.n	800eb88 <icmp_input+0x194>
-        /* p is not big enough to contain link headers
-         * allocate a new one and copy p into it
-         */
-        struct pbuf *r;
-        u16_t alloc_len = (u16_t)(p->tot_len + hlen);
- 800ead8:	687b      	ldr	r3, [r7, #4]
- 800eada:	891a      	ldrh	r2, [r3, #8]
- 800eadc:	8c7b      	ldrh	r3, [r7, #34]	; 0x22
- 800eade:	4413      	add	r3, r2
- 800eae0:	837b      	strh	r3, [r7, #26]
-        if (alloc_len < p->tot_len) {
- 800eae2:	687b      	ldr	r3, [r7, #4]
- 800eae4:	891b      	ldrh	r3, [r3, #8]
- 800eae6:	8b7a      	ldrh	r2, [r7, #26]
- 800eae8:	429a      	cmp	r2, r3
- 800eaea:	d203      	bcs.n	800eaf4 <icmp_input+0x100>
-          LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: allocating new pbuf failed (tot_len overflow)\n"));
- 800eaec:	4871      	ldr	r0, [pc, #452]	; (800ecb4 <icmp_input+0x2c0>)
- 800eaee:	f002 f8d9 	bl	8010ca4 <puts>
-          goto icmperr;
- 800eaf2:	e0c5      	b.n	800ec80 <icmp_input+0x28c>
-        }
-        /* allocate new packet buffer with space for link headers */
-        r = pbuf_alloc(PBUF_LINK, alloc_len, PBUF_RAM);
- 800eaf4:	8b7b      	ldrh	r3, [r7, #26]
- 800eaf6:	f44f 7220 	mov.w	r2, #640	; 0x280
- 800eafa:	4619      	mov	r1, r3
- 800eafc:	200e      	movs	r0, #14
- 800eafe:	f7f7 ff85 	bl	8006a0c <pbuf_alloc>
- 800eb02:	6178      	str	r0, [r7, #20]
-        if (r == NULL) {
- 800eb04:	697b      	ldr	r3, [r7, #20]
- 800eb06:	2b00      	cmp	r3, #0
- 800eb08:	d103      	bne.n	800eb12 <icmp_input+0x11e>
-          LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: allocating new pbuf failed\n"));
- 800eb0a:	486b      	ldr	r0, [pc, #428]	; (800ecb8 <icmp_input+0x2c4>)
- 800eb0c:	f002 f8ca 	bl	8010ca4 <puts>
-          goto icmperr;
- 800eb10:	e0b6      	b.n	800ec80 <icmp_input+0x28c>
-        }
-        if (r->len < hlen + sizeof(struct icmp_echo_hdr)) {
- 800eb12:	697b      	ldr	r3, [r7, #20]
- 800eb14:	895b      	ldrh	r3, [r3, #10]
- 800eb16:	461a      	mov	r2, r3
- 800eb18:	8c7b      	ldrh	r3, [r7, #34]	; 0x22
- 800eb1a:	3308      	adds	r3, #8
- 800eb1c:	429a      	cmp	r2, r3
- 800eb1e:	d206      	bcs.n	800eb2e <icmp_input+0x13a>
-          LWIP_DEBUGF(ICMP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("first pbuf cannot hold the ICMP header"));
- 800eb20:	4866      	ldr	r0, [pc, #408]	; (800ecbc <icmp_input+0x2c8>)
- 800eb22:	f002 f851 	bl	8010bc8 <iprintf>
-          pbuf_free(r);
- 800eb26:	6978      	ldr	r0, [r7, #20]
- 800eb28:	f7f8 fa54 	bl	8006fd4 <pbuf_free>
-          goto icmperr;
- 800eb2c:	e0a8      	b.n	800ec80 <icmp_input+0x28c>
-        }
-        /* copy the ip header */
-        MEMCPY(r->payload, iphdr_in, hlen);
- 800eb2e:	697b      	ldr	r3, [r7, #20]
- 800eb30:	685b      	ldr	r3, [r3, #4]
- 800eb32:	8c7a      	ldrh	r2, [r7, #34]	; 0x22
- 800eb34:	6a79      	ldr	r1, [r7, #36]	; 0x24
- 800eb36:	4618      	mov	r0, r3
- 800eb38:	f002 fa27 	bl	8010f8a <memcpy>
-        /* switch r->payload back to icmp header (cannot fail) */
-        if (pbuf_remove_header(r, hlen)) {
- 800eb3c:	8c7b      	ldrh	r3, [r7, #34]	; 0x22
- 800eb3e:	4619      	mov	r1, r3
- 800eb40:	6978      	ldr	r0, [r7, #20]
- 800eb42:	f7f8 f9c1 	bl	8006ec8 <pbuf_remove_header>
- 800eb46:	4603      	mov	r3, r0
- 800eb48:	2b00      	cmp	r3, #0
- 800eb4a:	d009      	beq.n	800eb60 <icmp_input+0x16c>
-          LWIP_ASSERT("icmp_input: moving r->payload to icmp header failed\n", 0);
- 800eb4c:	4b5c      	ldr	r3, [pc, #368]	; (800ecc0 <icmp_input+0x2cc>)
- 800eb4e:	22b6      	movs	r2, #182	; 0xb6
- 800eb50:	495c      	ldr	r1, [pc, #368]	; (800ecc4 <icmp_input+0x2d0>)
- 800eb52:	485d      	ldr	r0, [pc, #372]	; (800ecc8 <icmp_input+0x2d4>)
- 800eb54:	f002 f838 	bl	8010bc8 <iprintf>
-          pbuf_free(r);
- 800eb58:	6978      	ldr	r0, [r7, #20]
- 800eb5a:	f7f8 fa3b 	bl	8006fd4 <pbuf_free>
-          goto icmperr;
- 800eb5e:	e08f      	b.n	800ec80 <icmp_input+0x28c>
-        }
-        /* copy the rest of the packet without ip header */
-        if (pbuf_copy(r, p) != ERR_OK) {
- 800eb60:	6879      	ldr	r1, [r7, #4]
- 800eb62:	6978      	ldr	r0, [r7, #20]
- 800eb64:	f7f8 fb4e 	bl	8007204 <pbuf_copy>
- 800eb68:	4603      	mov	r3, r0
- 800eb6a:	2b00      	cmp	r3, #0
- 800eb6c:	d006      	beq.n	800eb7c <icmp_input+0x188>
-          LWIP_DEBUGF(ICMP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("icmp_input: copying to new pbuf failed"));
- 800eb6e:	4857      	ldr	r0, [pc, #348]	; (800eccc <icmp_input+0x2d8>)
- 800eb70:	f002 f82a 	bl	8010bc8 <iprintf>
-          pbuf_free(r);
- 800eb74:	6978      	ldr	r0, [r7, #20]
- 800eb76:	f7f8 fa2d 	bl	8006fd4 <pbuf_free>
-          goto icmperr;
- 800eb7a:	e081      	b.n	800ec80 <icmp_input+0x28c>
-        }
-        /* free the original p */
-        pbuf_free(p);
- 800eb7c:	6878      	ldr	r0, [r7, #4]
- 800eb7e:	f7f8 fa29 	bl	8006fd4 <pbuf_free>
-        /* we now have an identical copy of p that has room for link headers */
-        p = r;
- 800eb82:	697b      	ldr	r3, [r7, #20]
- 800eb84:	607b      	str	r3, [r7, #4]
- 800eb86:	e00f      	b.n	800eba8 <icmp_input+0x1b4>
-      } else {
-        /* restore p->payload to point to icmp header (cannot fail) */
-        if (pbuf_remove_header(p, hlen + PBUF_LINK_HLEN + PBUF_LINK_ENCAPSULATION_HLEN)) {
- 800eb88:	8c7b      	ldrh	r3, [r7, #34]	; 0x22
- 800eb8a:	330e      	adds	r3, #14
- 800eb8c:	4619      	mov	r1, r3
- 800eb8e:	6878      	ldr	r0, [r7, #4]
- 800eb90:	f7f8 f99a 	bl	8006ec8 <pbuf_remove_header>
- 800eb94:	4603      	mov	r3, r0
- 800eb96:	2b00      	cmp	r3, #0
- 800eb98:	d006      	beq.n	800eba8 <icmp_input+0x1b4>
-          LWIP_ASSERT("icmp_input: restoring original p->payload failed\n", 0);
- 800eb9a:	4b49      	ldr	r3, [pc, #292]	; (800ecc0 <icmp_input+0x2cc>)
- 800eb9c:	22c7      	movs	r2, #199	; 0xc7
- 800eb9e:	494c      	ldr	r1, [pc, #304]	; (800ecd0 <icmp_input+0x2dc>)
- 800eba0:	4849      	ldr	r0, [pc, #292]	; (800ecc8 <icmp_input+0x2d4>)
- 800eba2:	f002 f811 	bl	8010bc8 <iprintf>
-          goto icmperr;
- 800eba6:	e06b      	b.n	800ec80 <icmp_input+0x28c>
-      }
-#endif /* LWIP_ICMP_ECHO_CHECK_INPUT_PBUF_LEN */
-      /* At this point, all checks are OK. */
-      /* We generate an answer by switching the dest and src ip addresses,
-       * setting the icmp type to ECHO_RESPONSE and updating the checksum. */
-      iecho = (struct icmp_echo_hdr *)p->payload;
- 800eba8:	687b      	ldr	r3, [r7, #4]
- 800ebaa:	685b      	ldr	r3, [r3, #4]
- 800ebac:	613b      	str	r3, [r7, #16]
-      if (pbuf_add_header(p, hlen)) {
- 800ebae:	8c7b      	ldrh	r3, [r7, #34]	; 0x22
- 800ebb0:	4619      	mov	r1, r3
- 800ebb2:	6878      	ldr	r0, [r7, #4]
- 800ebb4:	f7f8 f978 	bl	8006ea8 <pbuf_add_header>
- 800ebb8:	4603      	mov	r3, r0
- 800ebba:	2b00      	cmp	r3, #0
- 800ebbc:	d003      	beq.n	800ebc6 <icmp_input+0x1d2>
-        LWIP_DEBUGF(ICMP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("Can't move over header in packet"));
- 800ebbe:	4845      	ldr	r0, [pc, #276]	; (800ecd4 <icmp_input+0x2e0>)
- 800ebc0:	f002 f802 	bl	8010bc8 <iprintf>
-                            ICMP_TTL, 0, IP_PROTO_ICMP, inp);
-        if (ret != ERR_OK) {
-          LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: ip_output_if returned an error: %s\n", lwip_strerr(ret)));
-        }
-      }
-      break;
- 800ebc4:	e053      	b.n	800ec6e <icmp_input+0x27a>
-        struct ip_hdr *iphdr = (struct ip_hdr *)p->payload;
- 800ebc6:	687b      	ldr	r3, [r7, #4]
- 800ebc8:	685b      	ldr	r3, [r3, #4]
- 800ebca:	60fb      	str	r3, [r7, #12]
-        ip4_addr_copy(iphdr->src, *src);
- 800ebcc:	69fb      	ldr	r3, [r7, #28]
- 800ebce:	681a      	ldr	r2, [r3, #0]
- 800ebd0:	68fb      	ldr	r3, [r7, #12]
- 800ebd2:	60da      	str	r2, [r3, #12]
-        ip4_addr_copy(iphdr->dest, *ip4_current_src_addr());
- 800ebd4:	4b2e      	ldr	r3, [pc, #184]	; (800ec90 <icmp_input+0x29c>)
- 800ebd6:	691a      	ldr	r2, [r3, #16]
- 800ebd8:	68fb      	ldr	r3, [r7, #12]
- 800ebda:	611a      	str	r2, [r3, #16]
-        ICMPH_TYPE_SET(iecho, ICMP_ER);
- 800ebdc:	693b      	ldr	r3, [r7, #16]
- 800ebde:	2200      	movs	r2, #0
- 800ebe0:	701a      	strb	r2, [r3, #0]
-          if (iecho->chksum > PP_HTONS(0xffffU - (ICMP_ECHO << 8))) {
- 800ebe2:	693b      	ldr	r3, [r7, #16]
- 800ebe4:	885b      	ldrh	r3, [r3, #2]
- 800ebe6:	b29b      	uxth	r3, r3
- 800ebe8:	f64f 72f7 	movw	r2, #65527	; 0xfff7
- 800ebec:	4293      	cmp	r3, r2
- 800ebee:	d907      	bls.n	800ec00 <icmp_input+0x20c>
-            iecho->chksum = (u16_t)(iecho->chksum + PP_HTONS((u16_t)(ICMP_ECHO << 8)) + 1);
- 800ebf0:	693b      	ldr	r3, [r7, #16]
- 800ebf2:	885b      	ldrh	r3, [r3, #2]
- 800ebf4:	b29b      	uxth	r3, r3
- 800ebf6:	3309      	adds	r3, #9
- 800ebf8:	b29a      	uxth	r2, r3
- 800ebfa:	693b      	ldr	r3, [r7, #16]
- 800ebfc:	805a      	strh	r2, [r3, #2]
- 800ebfe:	e006      	b.n	800ec0e <icmp_input+0x21a>
-            iecho->chksum = (u16_t)(iecho->chksum + PP_HTONS(ICMP_ECHO << 8));
- 800ec00:	693b      	ldr	r3, [r7, #16]
- 800ec02:	885b      	ldrh	r3, [r3, #2]
- 800ec04:	b29b      	uxth	r3, r3
- 800ec06:	3308      	adds	r3, #8
- 800ec08:	b29a      	uxth	r2, r3
- 800ec0a:	693b      	ldr	r3, [r7, #16]
- 800ec0c:	805a      	strh	r2, [r3, #2]
-        IPH_TTL_SET(iphdr, ICMP_TTL);
- 800ec0e:	68fb      	ldr	r3, [r7, #12]
- 800ec10:	22ff      	movs	r2, #255	; 0xff
- 800ec12:	721a      	strb	r2, [r3, #8]
-        IPH_CHKSUM_SET(iphdr, 0);
- 800ec14:	68fb      	ldr	r3, [r7, #12]
- 800ec16:	2200      	movs	r2, #0
- 800ec18:	729a      	strb	r2, [r3, #10]
- 800ec1a:	2200      	movs	r2, #0
- 800ec1c:	72da      	strb	r2, [r3, #11]
-        ret = ip4_output_if(p, src, LWIP_IP_HDRINCL,
- 800ec1e:	683b      	ldr	r3, [r7, #0]
- 800ec20:	9302      	str	r3, [sp, #8]
- 800ec22:	2301      	movs	r3, #1
- 800ec24:	9301      	str	r3, [sp, #4]
- 800ec26:	2300      	movs	r3, #0
- 800ec28:	9300      	str	r3, [sp, #0]
- 800ec2a:	23ff      	movs	r3, #255	; 0xff
- 800ec2c:	2200      	movs	r2, #0
- 800ec2e:	69f9      	ldr	r1, [r7, #28]
- 800ec30:	6878      	ldr	r0, [r7, #4]
- 800ec32:	f000 fae7 	bl	800f204 <ip4_output_if>
- 800ec36:	4603      	mov	r3, r0
- 800ec38:	72fb      	strb	r3, [r7, #11]
-        if (ret != ERR_OK) {
- 800ec3a:	f997 300b 	ldrsb.w	r3, [r7, #11]
- 800ec3e:	2b00      	cmp	r3, #0
- 800ec40:	d015      	beq.n	800ec6e <icmp_input+0x27a>
-          LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: ip_output_if returned an error: %s\n", lwip_strerr(ret)));
- 800ec42:	f997 300b 	ldrsb.w	r3, [r7, #11]
- 800ec46:	4618      	mov	r0, r3
- 800ec48:	f7f6 fc60 	bl	800550c <lwip_strerr>
- 800ec4c:	4603      	mov	r3, r0
- 800ec4e:	4619      	mov	r1, r3
- 800ec50:	4821      	ldr	r0, [pc, #132]	; (800ecd8 <icmp_input+0x2e4>)
- 800ec52:	f001 ffb9 	bl	8010bc8 <iprintf>
-      break;
- 800ec56:	e00a      	b.n	800ec6e <icmp_input+0x27a>
-      } else if (type == ICMP_AM) {
-        MIB2_STATS_INC(mib2.icmpinaddrmasks);
-      } else if (type == ICMP_AMR) {
-        MIB2_STATS_INC(mib2.icmpinaddrmaskreps);
-      }
-      LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: ICMP type %"S16_F" code %"S16_F" not supported.\n",
- 800ec58:	f897 3021 	ldrb.w	r3, [r7, #33]	; 0x21
- 800ec5c:	f897 2020 	ldrb.w	r2, [r7, #32]
- 800ec60:	4619      	mov	r1, r3
- 800ec62:	481e      	ldr	r0, [pc, #120]	; (800ecdc <icmp_input+0x2e8>)
- 800ec64:	f001 ffb0 	bl	8010bc8 <iprintf>
- 800ec68:	e002      	b.n	800ec70 <icmp_input+0x27c>
-      break;
- 800ec6a:	bf00      	nop
- 800ec6c:	e000      	b.n	800ec70 <icmp_input+0x27c>
-      break;
- 800ec6e:	bf00      	nop
-                               (s16_t)type, (s16_t)code));
-      ICMP_STATS_INC(icmp.proterr);
-      ICMP_STATS_INC(icmp.drop);
-  }
-  pbuf_free(p);
- 800ec70:	6878      	ldr	r0, [r7, #4]
- 800ec72:	f7f8 f9af 	bl	8006fd4 <pbuf_free>
-  return;
- 800ec76:	e007      	b.n	800ec88 <icmp_input+0x294>
-lenerr:
-  pbuf_free(p);
- 800ec78:	6878      	ldr	r0, [r7, #4]
- 800ec7a:	f7f8 f9ab 	bl	8006fd4 <pbuf_free>
-  ICMP_STATS_INC(icmp.lenerr);
-  MIB2_STATS_INC(mib2.icmpinerrors);
-  return;
- 800ec7e:	e003      	b.n	800ec88 <icmp_input+0x294>
-#if LWIP_ICMP_ECHO_CHECK_INPUT_PBUF_LEN || !LWIP_MULTICAST_PING || !LWIP_BROADCAST_PING
-icmperr:
-  pbuf_free(p);
- 800ec80:	6878      	ldr	r0, [r7, #4]
- 800ec82:	f7f8 f9a7 	bl	8006fd4 <pbuf_free>
-  ICMP_STATS_INC(icmp.err);
-  MIB2_STATS_INC(mib2.icmpinerrors);
-  return;
- 800ec86:	bf00      	nop
-#endif /* LWIP_ICMP_ECHO_CHECK_INPUT_PBUF_LEN || !LWIP_MULTICAST_PING || !LWIP_BROADCAST_PING */
-}
- 800ec88:	3728      	adds	r7, #40	; 0x28
- 800ec8a:	46bd      	mov	sp, r7
- 800ec8c:	bd80      	pop	{r7, pc}
- 800ec8e:	bf00      	nop
- 800ec90:	24004c10 	.word	0x24004c10
- 800ec94:	08014554 	.word	0x08014554
- 800ec98:	08014588 	.word	0x08014588
- 800ec9c:	24004c24 	.word	0x24004c24
- 800eca0:	080145b8 	.word	0x080145b8
- 800eca4:	080145e4 	.word	0x080145e4
- 800eca8:	08014610 	.word	0x08014610
- 800ecac:	08014624 	.word	0x08014624
- 800ecb0:	08014648 	.word	0x08014648
- 800ecb4:	0801467c 	.word	0x0801467c
- 800ecb8:	080146b8 	.word	0x080146b8
- 800ecbc:	080146e0 	.word	0x080146e0
- 800ecc0:	08014708 	.word	0x08014708
- 800ecc4:	08014740 	.word	0x08014740
- 800ecc8:	08014778 	.word	0x08014778
- 800eccc:	080147a0 	.word	0x080147a0
- 800ecd0:	080147c8 	.word	0x080147c8
- 800ecd4:	080147fc 	.word	0x080147fc
- 800ecd8:	08014820 	.word	0x08014820
- 800ecdc:	08014850 	.word	0x08014850
-
-0800ece0 <icmp_dest_unreach>:
- *          p->payload pointing to the IP header
- * @param t type of the 'unreachable' packet
- */
-void
-icmp_dest_unreach(struct pbuf *p, enum icmp_dur_type t)
-{
- 800ece0:	b580      	push	{r7, lr}
- 800ece2:	b082      	sub	sp, #8
- 800ece4:	af00      	add	r7, sp, #0
- 800ece6:	6078      	str	r0, [r7, #4]
- 800ece8:	460b      	mov	r3, r1
- 800ecea:	70fb      	strb	r3, [r7, #3]
-  MIB2_STATS_INC(mib2.icmpoutdestunreachs);
-  icmp_send_response(p, ICMP_DUR, t);
- 800ecec:	78fb      	ldrb	r3, [r7, #3]
- 800ecee:	461a      	mov	r2, r3
- 800ecf0:	2103      	movs	r1, #3
- 800ecf2:	6878      	ldr	r0, [r7, #4]
- 800ecf4:	f000 f814 	bl	800ed20 <icmp_send_response>
-}
- 800ecf8:	bf00      	nop
- 800ecfa:	3708      	adds	r7, #8
- 800ecfc:	46bd      	mov	sp, r7
- 800ecfe:	bd80      	pop	{r7, pc}
-
-0800ed00 <icmp_time_exceeded>:
- *          p->payload pointing to the IP header
- * @param t type of the 'time exceeded' packet
- */
-void
-icmp_time_exceeded(struct pbuf *p, enum icmp_te_type t)
-{
- 800ed00:	b580      	push	{r7, lr}
- 800ed02:	b082      	sub	sp, #8
- 800ed04:	af00      	add	r7, sp, #0
- 800ed06:	6078      	str	r0, [r7, #4]
- 800ed08:	460b      	mov	r3, r1
- 800ed0a:	70fb      	strb	r3, [r7, #3]
-  MIB2_STATS_INC(mib2.icmpouttimeexcds);
-  icmp_send_response(p, ICMP_TE, t);
- 800ed0c:	78fb      	ldrb	r3, [r7, #3]
- 800ed0e:	461a      	mov	r2, r3
- 800ed10:	210b      	movs	r1, #11
- 800ed12:	6878      	ldr	r0, [r7, #4]
- 800ed14:	f000 f804 	bl	800ed20 <icmp_send_response>
-}
- 800ed18:	bf00      	nop
- 800ed1a:	3708      	adds	r7, #8
- 800ed1c:	46bd      	mov	sp, r7
- 800ed1e:	bd80      	pop	{r7, pc}
-
-0800ed20 <icmp_send_response>:
- * @param type Type of the ICMP header
- * @param code Code of the ICMP header
- */
-static void
-icmp_send_response(struct pbuf *p, u8_t type, u8_t code)
-{
- 800ed20:	b580      	push	{r7, lr}
- 800ed22:	b08c      	sub	sp, #48	; 0x30
- 800ed24:	af04      	add	r7, sp, #16
- 800ed26:	6078      	str	r0, [r7, #4]
- 800ed28:	460b      	mov	r3, r1
- 800ed2a:	70fb      	strb	r3, [r7, #3]
- 800ed2c:	4613      	mov	r3, r2
- 800ed2e:	70bb      	strb	r3, [r7, #2]
-
-  /* increase number of messages attempted to send */
-  MIB2_STATS_INC(mib2.icmpoutmsgs);
-
-  /* ICMP header + IP header + 8 bytes of data */
-  q = pbuf_alloc(PBUF_IP, sizeof(struct icmp_echo_hdr) + IP_HLEN + ICMP_DEST_UNREACH_DATASIZE,
- 800ed30:	f44f 7220 	mov.w	r2, #640	; 0x280
- 800ed34:	2124      	movs	r1, #36	; 0x24
- 800ed36:	2022      	movs	r0, #34	; 0x22
- 800ed38:	f7f7 fe68 	bl	8006a0c <pbuf_alloc>
- 800ed3c:	61f8      	str	r0, [r7, #28]
-                 PBUF_RAM);
-  if (q == NULL) {
- 800ed3e:	69fb      	ldr	r3, [r7, #28]
- 800ed40:	2b00      	cmp	r3, #0
- 800ed42:	d103      	bne.n	800ed4c <icmp_send_response+0x2c>
-    LWIP_DEBUGF(ICMP_DEBUG, ("icmp_time_exceeded: failed to allocate pbuf for ICMP packet.\n"));
- 800ed44:	4849      	ldr	r0, [pc, #292]	; (800ee6c <icmp_send_response+0x14c>)
- 800ed46:	f001 ffad 	bl	8010ca4 <puts>
- 800ed4a:	e08c      	b.n	800ee66 <icmp_send_response+0x146>
-    MIB2_STATS_INC(mib2.icmpouterrors);
-    return;
-  }
-  LWIP_ASSERT("check that first pbuf can hold icmp message",
- 800ed4c:	69fb      	ldr	r3, [r7, #28]
- 800ed4e:	895b      	ldrh	r3, [r3, #10]
- 800ed50:	2b23      	cmp	r3, #35	; 0x23
- 800ed52:	d806      	bhi.n	800ed62 <icmp_send_response+0x42>
- 800ed54:	4b46      	ldr	r3, [pc, #280]	; (800ee70 <icmp_send_response+0x150>)
- 800ed56:	f44f 72b4 	mov.w	r2, #360	; 0x168
- 800ed5a:	4946      	ldr	r1, [pc, #280]	; (800ee74 <icmp_send_response+0x154>)
- 800ed5c:	4846      	ldr	r0, [pc, #280]	; (800ee78 <icmp_send_response+0x158>)
- 800ed5e:	f001 ff33 	bl	8010bc8 <iprintf>
-              (q->len >= (sizeof(struct icmp_echo_hdr) + IP_HLEN + ICMP_DEST_UNREACH_DATASIZE)));
-
-  iphdr = (struct ip_hdr *)p->payload;
- 800ed62:	687b      	ldr	r3, [r7, #4]
- 800ed64:	685b      	ldr	r3, [r3, #4]
- 800ed66:	61bb      	str	r3, [r7, #24]
-  LWIP_DEBUGF(ICMP_DEBUG, ("icmp_time_exceeded from "));
- 800ed68:	4844      	ldr	r0, [pc, #272]	; (800ee7c <icmp_send_response+0x15c>)
- 800ed6a:	f001 ff2d 	bl	8010bc8 <iprintf>
-  ip4_addr_debug_print_val(ICMP_DEBUG, iphdr->src);
- 800ed6e:	69bb      	ldr	r3, [r7, #24]
- 800ed70:	68db      	ldr	r3, [r3, #12]
- 800ed72:	b2db      	uxtb	r3, r3
- 800ed74:	4619      	mov	r1, r3
- 800ed76:	69bb      	ldr	r3, [r7, #24]
- 800ed78:	68db      	ldr	r3, [r3, #12]
- 800ed7a:	0a1b      	lsrs	r3, r3, #8
- 800ed7c:	b2db      	uxtb	r3, r3
- 800ed7e:	461a      	mov	r2, r3
- 800ed80:	69bb      	ldr	r3, [r7, #24]
- 800ed82:	68db      	ldr	r3, [r3, #12]
- 800ed84:	0c1b      	lsrs	r3, r3, #16
- 800ed86:	b2db      	uxtb	r3, r3
- 800ed88:	4618      	mov	r0, r3
- 800ed8a:	69bb      	ldr	r3, [r7, #24]
- 800ed8c:	68db      	ldr	r3, [r3, #12]
- 800ed8e:	0e1b      	lsrs	r3, r3, #24
- 800ed90:	b2db      	uxtb	r3, r3
- 800ed92:	9300      	str	r3, [sp, #0]
- 800ed94:	4603      	mov	r3, r0
- 800ed96:	483a      	ldr	r0, [pc, #232]	; (800ee80 <icmp_send_response+0x160>)
- 800ed98:	f001 ff16 	bl	8010bc8 <iprintf>
-  LWIP_DEBUGF(ICMP_DEBUG, (" to "));
- 800ed9c:	4839      	ldr	r0, [pc, #228]	; (800ee84 <icmp_send_response+0x164>)
- 800ed9e:	f001 ff13 	bl	8010bc8 <iprintf>
-  ip4_addr_debug_print_val(ICMP_DEBUG, iphdr->dest);
- 800eda2:	69bb      	ldr	r3, [r7, #24]
- 800eda4:	691b      	ldr	r3, [r3, #16]
- 800eda6:	b2db      	uxtb	r3, r3
- 800eda8:	4619      	mov	r1, r3
- 800edaa:	69bb      	ldr	r3, [r7, #24]
- 800edac:	691b      	ldr	r3, [r3, #16]
- 800edae:	0a1b      	lsrs	r3, r3, #8
- 800edb0:	b2db      	uxtb	r3, r3
- 800edb2:	461a      	mov	r2, r3
- 800edb4:	69bb      	ldr	r3, [r7, #24]
- 800edb6:	691b      	ldr	r3, [r3, #16]
- 800edb8:	0c1b      	lsrs	r3, r3, #16
- 800edba:	b2db      	uxtb	r3, r3
- 800edbc:	4618      	mov	r0, r3
- 800edbe:	69bb      	ldr	r3, [r7, #24]
- 800edc0:	691b      	ldr	r3, [r3, #16]
- 800edc2:	0e1b      	lsrs	r3, r3, #24
- 800edc4:	b2db      	uxtb	r3, r3
- 800edc6:	9300      	str	r3, [sp, #0]
- 800edc8:	4603      	mov	r3, r0
- 800edca:	482d      	ldr	r0, [pc, #180]	; (800ee80 <icmp_send_response+0x160>)
- 800edcc:	f001 fefc 	bl	8010bc8 <iprintf>
-  LWIP_DEBUGF(ICMP_DEBUG, ("\n"));
- 800edd0:	200a      	movs	r0, #10
- 800edd2:	f001 ff0b 	bl	8010bec <putchar>
-
-  icmphdr = (struct icmp_echo_hdr *)q->payload;
- 800edd6:	69fb      	ldr	r3, [r7, #28]
- 800edd8:	685b      	ldr	r3, [r3, #4]
- 800edda:	617b      	str	r3, [r7, #20]
-  icmphdr->type = type;
- 800eddc:	697b      	ldr	r3, [r7, #20]
- 800edde:	78fa      	ldrb	r2, [r7, #3]
- 800ede0:	701a      	strb	r2, [r3, #0]
-  icmphdr->code = code;
- 800ede2:	697b      	ldr	r3, [r7, #20]
- 800ede4:	78ba      	ldrb	r2, [r7, #2]
- 800ede6:	705a      	strb	r2, [r3, #1]
-  icmphdr->id = 0;
- 800ede8:	697b      	ldr	r3, [r7, #20]
- 800edea:	2200      	movs	r2, #0
- 800edec:	711a      	strb	r2, [r3, #4]
- 800edee:	2200      	movs	r2, #0
- 800edf0:	715a      	strb	r2, [r3, #5]
-  icmphdr->seqno = 0;
- 800edf2:	697b      	ldr	r3, [r7, #20]
- 800edf4:	2200      	movs	r2, #0
- 800edf6:	719a      	strb	r2, [r3, #6]
- 800edf8:	2200      	movs	r2, #0
- 800edfa:	71da      	strb	r2, [r3, #7]
-
-  /* copy fields from original packet */
-  SMEMCPY((u8_t *)q->payload + sizeof(struct icmp_echo_hdr), (u8_t *)p->payload,
- 800edfc:	69fb      	ldr	r3, [r7, #28]
- 800edfe:	685b      	ldr	r3, [r3, #4]
- 800ee00:	f103 0008 	add.w	r0, r3, #8
- 800ee04:	687b      	ldr	r3, [r7, #4]
- 800ee06:	685b      	ldr	r3, [r3, #4]
- 800ee08:	221c      	movs	r2, #28
- 800ee0a:	4619      	mov	r1, r3
- 800ee0c:	f002 f8bd 	bl	8010f8a <memcpy>
-          IP_HLEN + ICMP_DEST_UNREACH_DATASIZE);
-
-  ip4_addr_copy(iphdr_src, iphdr->src);
- 800ee10:	69bb      	ldr	r3, [r7, #24]
- 800ee12:	68db      	ldr	r3, [r3, #12]
- 800ee14:	60fb      	str	r3, [r7, #12]
-    ip4_addr_t iphdr_dst;
-    ip4_addr_copy(iphdr_dst, iphdr->dest);
-    netif = ip4_route_src(&iphdr_dst, &iphdr_src);
-  }
-#else
-  netif = ip4_route(&iphdr_src);
- 800ee16:	f107 030c 	add.w	r3, r7, #12
- 800ee1a:	4618      	mov	r0, r3
- 800ee1c:	f000 f834 	bl	800ee88 <ip4_route>
- 800ee20:	6138      	str	r0, [r7, #16]
-#endif
-  if (netif != NULL) {
- 800ee22:	693b      	ldr	r3, [r7, #16]
- 800ee24:	2b00      	cmp	r3, #0
- 800ee26:	d01b      	beq.n	800ee60 <icmp_send_response+0x140>
-    /* calculate checksum */
-    icmphdr->chksum = 0;
- 800ee28:	697b      	ldr	r3, [r7, #20]
- 800ee2a:	2200      	movs	r2, #0
- 800ee2c:	709a      	strb	r2, [r3, #2]
- 800ee2e:	2200      	movs	r2, #0
- 800ee30:	70da      	strb	r2, [r3, #3]
-#if CHECKSUM_GEN_ICMP
-    IF__NETIF_CHECKSUM_ENABLED(netif, NETIF_CHECKSUM_GEN_ICMP) {
-      icmphdr->chksum = inet_chksum(icmphdr, q->len);
- 800ee32:	69fb      	ldr	r3, [r7, #28]
- 800ee34:	895b      	ldrh	r3, [r3, #10]
- 800ee36:	4619      	mov	r1, r3
- 800ee38:	6978      	ldr	r0, [r7, #20]
- 800ee3a:	f7f6 fc12 	bl	8005662 <inet_chksum>
- 800ee3e:	4603      	mov	r3, r0
- 800ee40:	461a      	mov	r2, r3
- 800ee42:	697b      	ldr	r3, [r7, #20]
- 800ee44:	805a      	strh	r2, [r3, #2]
-    }
-#endif
-    ICMP_STATS_INC(icmp.xmit);
-    ip4_output_if(q, NULL, &iphdr_src, ICMP_TTL, 0, IP_PROTO_ICMP, netif);
- 800ee46:	f107 020c 	add.w	r2, r7, #12
- 800ee4a:	693b      	ldr	r3, [r7, #16]
- 800ee4c:	9302      	str	r3, [sp, #8]
- 800ee4e:	2301      	movs	r3, #1
- 800ee50:	9301      	str	r3, [sp, #4]
- 800ee52:	2300      	movs	r3, #0
- 800ee54:	9300      	str	r3, [sp, #0]
- 800ee56:	23ff      	movs	r3, #255	; 0xff
- 800ee58:	2100      	movs	r1, #0
- 800ee5a:	69f8      	ldr	r0, [r7, #28]
- 800ee5c:	f000 f9d2 	bl	800f204 <ip4_output_if>
-  }
-  pbuf_free(q);
- 800ee60:	69f8      	ldr	r0, [r7, #28]
- 800ee62:	f7f8 f8b7 	bl	8006fd4 <pbuf_free>
-}
- 800ee66:	3720      	adds	r7, #32
- 800ee68:	46bd      	mov	sp, r7
- 800ee6a:	bd80      	pop	{r7, pc}
- 800ee6c:	08014884 	.word	0x08014884
- 800ee70:	08014708 	.word	0x08014708
- 800ee74:	080148c4 	.word	0x080148c4
- 800ee78:	08014778 	.word	0x08014778
- 800ee7c:	080148f0 	.word	0x080148f0
- 800ee80:	0801490c 	.word	0x0801490c
- 800ee84:	0801491c 	.word	0x0801491c
-
-0800ee88 <ip4_route>:
- * @param dest the destination IP address for which to find the route
- * @return the netif on which to send to reach dest
- */
-struct netif *
-ip4_route(const ip4_addr_t *dest)
-{
- 800ee88:	b480      	push	{r7}
- 800ee8a:	b085      	sub	sp, #20
- 800ee8c:	af00      	add	r7, sp, #0
- 800ee8e:	6078      	str	r0, [r7, #4]
-
-  /* bug #54569: in case LWIP_SINGLE_NETIF=1 and LWIP_DEBUGF() disabled, the following loop is optimized away */
-  LWIP_UNUSED_ARG(dest);
-
-  /* iterate through netifs */
-  NETIF_FOREACH(netif) {
- 800ee90:	4b33      	ldr	r3, [pc, #204]	; (800ef60 <ip4_route+0xd8>)
- 800ee92:	681b      	ldr	r3, [r3, #0]
- 800ee94:	60fb      	str	r3, [r7, #12]
- 800ee96:	e036      	b.n	800ef06 <ip4_route+0x7e>
-    /* is the netif up, does it have a link and a valid address? */
-    if (netif_is_up(netif) && netif_is_link_up(netif) && !ip4_addr_isany_val(*netif_ip4_addr(netif))) {
- 800ee98:	68fb      	ldr	r3, [r7, #12]
- 800ee9a:	f893 302d 	ldrb.w	r3, [r3, #45]	; 0x2d
- 800ee9e:	f003 0301 	and.w	r3, r3, #1
- 800eea2:	b2db      	uxtb	r3, r3
- 800eea4:	2b00      	cmp	r3, #0
- 800eea6:	d02b      	beq.n	800ef00 <ip4_route+0x78>
- 800eea8:	68fb      	ldr	r3, [r7, #12]
- 800eeaa:	f893 302d 	ldrb.w	r3, [r3, #45]	; 0x2d
- 800eeae:	089b      	lsrs	r3, r3, #2
- 800eeb0:	f003 0301 	and.w	r3, r3, #1
- 800eeb4:	b2db      	uxtb	r3, r3
- 800eeb6:	2b00      	cmp	r3, #0
- 800eeb8:	d022      	beq.n	800ef00 <ip4_route+0x78>
- 800eeba:	68fb      	ldr	r3, [r7, #12]
- 800eebc:	3304      	adds	r3, #4
- 800eebe:	681b      	ldr	r3, [r3, #0]
- 800eec0:	2b00      	cmp	r3, #0
- 800eec2:	d01d      	beq.n	800ef00 <ip4_route+0x78>
-      /* network mask matches? */
-      if (ip4_addr_netcmp(dest, netif_ip4_addr(netif), netif_ip4_netmask(netif))) {
- 800eec4:	687b      	ldr	r3, [r7, #4]
- 800eec6:	681a      	ldr	r2, [r3, #0]
- 800eec8:	68fb      	ldr	r3, [r7, #12]
- 800eeca:	3304      	adds	r3, #4
- 800eecc:	681b      	ldr	r3, [r3, #0]
- 800eece:	405a      	eors	r2, r3
- 800eed0:	68fb      	ldr	r3, [r7, #12]
- 800eed2:	3308      	adds	r3, #8
- 800eed4:	681b      	ldr	r3, [r3, #0]
- 800eed6:	4013      	ands	r3, r2
- 800eed8:	2b00      	cmp	r3, #0
- 800eeda:	d101      	bne.n	800eee0 <ip4_route+0x58>
-        /* return netif on which to forward IP packet */
-        return netif;
- 800eedc:	68fb      	ldr	r3, [r7, #12]
- 800eede:	e038      	b.n	800ef52 <ip4_route+0xca>
-      }
-      /* gateway matches on a non broadcast interface? (i.e. peer in a point to point interface) */
-      if (((netif->flags & NETIF_FLAG_BROADCAST) == 0) && ip4_addr_cmp(dest, netif_ip4_gw(netif))) {
- 800eee0:	68fb      	ldr	r3, [r7, #12]
- 800eee2:	f893 302d 	ldrb.w	r3, [r3, #45]	; 0x2d
- 800eee6:	f003 0302 	and.w	r3, r3, #2
- 800eeea:	2b00      	cmp	r3, #0
- 800eeec:	d108      	bne.n	800ef00 <ip4_route+0x78>
- 800eeee:	687b      	ldr	r3, [r7, #4]
- 800eef0:	681a      	ldr	r2, [r3, #0]
- 800eef2:	68fb      	ldr	r3, [r7, #12]
- 800eef4:	330c      	adds	r3, #12
- 800eef6:	681b      	ldr	r3, [r3, #0]
- 800eef8:	429a      	cmp	r2, r3
- 800eefa:	d101      	bne.n	800ef00 <ip4_route+0x78>
-        /* return netif on which to forward IP packet */
-        return netif;
- 800eefc:	68fb      	ldr	r3, [r7, #12]
- 800eefe:	e028      	b.n	800ef52 <ip4_route+0xca>
-  NETIF_FOREACH(netif) {
- 800ef00:	68fb      	ldr	r3, [r7, #12]
- 800ef02:	681b      	ldr	r3, [r3, #0]
- 800ef04:	60fb      	str	r3, [r7, #12]
- 800ef06:	68fb      	ldr	r3, [r7, #12]
- 800ef08:	2b00      	cmp	r3, #0
- 800ef0a:	d1c5      	bne.n	800ee98 <ip4_route+0x10>
-    return netif;
-  }
-#endif
-#endif /* !LWIP_SINGLE_NETIF */
-
-  if ((netif_default == NULL) || !netif_is_up(netif_default) || !netif_is_link_up(netif_default) ||
- 800ef0c:	4b15      	ldr	r3, [pc, #84]	; (800ef64 <ip4_route+0xdc>)
- 800ef0e:	681b      	ldr	r3, [r3, #0]
- 800ef10:	2b00      	cmp	r3, #0
- 800ef12:	d01a      	beq.n	800ef4a <ip4_route+0xc2>
- 800ef14:	4b13      	ldr	r3, [pc, #76]	; (800ef64 <ip4_route+0xdc>)
- 800ef16:	681b      	ldr	r3, [r3, #0]
- 800ef18:	f893 302d 	ldrb.w	r3, [r3, #45]	; 0x2d
- 800ef1c:	f003 0301 	and.w	r3, r3, #1
- 800ef20:	2b00      	cmp	r3, #0
- 800ef22:	d012      	beq.n	800ef4a <ip4_route+0xc2>
- 800ef24:	4b0f      	ldr	r3, [pc, #60]	; (800ef64 <ip4_route+0xdc>)
- 800ef26:	681b      	ldr	r3, [r3, #0]
- 800ef28:	f893 302d 	ldrb.w	r3, [r3, #45]	; 0x2d
- 800ef2c:	f003 0304 	and.w	r3, r3, #4
- 800ef30:	2b00      	cmp	r3, #0
- 800ef32:	d00a      	beq.n	800ef4a <ip4_route+0xc2>
-      ip4_addr_isany_val(*netif_ip4_addr(netif_default)) || ip4_addr_isloopback(dest)) {
- 800ef34:	4b0b      	ldr	r3, [pc, #44]	; (800ef64 <ip4_route+0xdc>)
- 800ef36:	681b      	ldr	r3, [r3, #0]
- 800ef38:	3304      	adds	r3, #4
- 800ef3a:	681b      	ldr	r3, [r3, #0]
-  if ((netif_default == NULL) || !netif_is_up(netif_default) || !netif_is_link_up(netif_default) ||
- 800ef3c:	2b00      	cmp	r3, #0
- 800ef3e:	d004      	beq.n	800ef4a <ip4_route+0xc2>
-      ip4_addr_isany_val(*netif_ip4_addr(netif_default)) || ip4_addr_isloopback(dest)) {
- 800ef40:	687b      	ldr	r3, [r7, #4]
- 800ef42:	681b      	ldr	r3, [r3, #0]
- 800ef44:	b2db      	uxtb	r3, r3
- 800ef46:	2b7f      	cmp	r3, #127	; 0x7f
- 800ef48:	d101      	bne.n	800ef4e <ip4_route+0xc6>
-       If this is not good enough for you, use LWIP_HOOK_IP4_ROUTE() */
-    LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("ip4_route: No route to %"U16_F".%"U16_F".%"U16_F".%"U16_F"\n",
-                ip4_addr1_16(dest), ip4_addr2_16(dest), ip4_addr3_16(dest), ip4_addr4_16(dest)));
-    IP_STATS_INC(ip.rterr);
-    MIB2_STATS_INC(mib2.ipoutnoroutes);
-    return NULL;
- 800ef4a:	2300      	movs	r3, #0
- 800ef4c:	e001      	b.n	800ef52 <ip4_route+0xca>
-  }
-
-  return netif_default;
- 800ef4e:	4b05      	ldr	r3, [pc, #20]	; (800ef64 <ip4_route+0xdc>)
- 800ef50:	681b      	ldr	r3, [r3, #0]
-}
- 800ef52:	4618      	mov	r0, r3
- 800ef54:	3714      	adds	r7, #20
- 800ef56:	46bd      	mov	sp, r7
- 800ef58:	f85d 7b04 	ldr.w	r7, [sp], #4
- 800ef5c:	4770      	bx	lr
- 800ef5e:	bf00      	nop
- 800ef60:	24007b60 	.word	0x24007b60
- 800ef64:	24007b64 	.word	0x24007b64
-
-0800ef68 <ip4_input_accept>:
-#endif /* IP_FORWARD */
-
-/** Return true if the current input packet should be accepted on this netif */
-static int
-ip4_input_accept(struct netif *netif)
-{
- 800ef68:	b580      	push	{r7, lr}
- 800ef6a:	b082      	sub	sp, #8
- 800ef6c:	af00      	add	r7, sp, #0
- 800ef6e:	6078      	str	r0, [r7, #4]
-                         ip4_addr_get_u32(ip4_current_dest_addr()) & ip4_addr_get_u32(netif_ip4_netmask(netif)),
-                         ip4_addr_get_u32(netif_ip4_addr(netif)) & ip4_addr_get_u32(netif_ip4_netmask(netif)),
-                         ip4_addr_get_u32(ip4_current_dest_addr()) & ~ip4_addr_get_u32(netif_ip4_netmask(netif))));
-
-  /* interface is up and configured? */
-  if ((netif_is_up(netif)) && (!ip4_addr_isany_val(*netif_ip4_addr(netif)))) {
- 800ef70:	687b      	ldr	r3, [r7, #4]
- 800ef72:	f893 302d 	ldrb.w	r3, [r3, #45]	; 0x2d
- 800ef76:	f003 0301 	and.w	r3, r3, #1
- 800ef7a:	b2db      	uxtb	r3, r3
- 800ef7c:	2b00      	cmp	r3, #0
- 800ef7e:	d016      	beq.n	800efae <ip4_input_accept+0x46>
- 800ef80:	687b      	ldr	r3, [r7, #4]
- 800ef82:	3304      	adds	r3, #4
- 800ef84:	681b      	ldr	r3, [r3, #0]
- 800ef86:	2b00      	cmp	r3, #0
- 800ef88:	d011      	beq.n	800efae <ip4_input_accept+0x46>
-    /* unicast to this interface address? */
-    if (ip4_addr_cmp(ip4_current_dest_addr(), netif_ip4_addr(netif)) ||
- 800ef8a:	4b0b      	ldr	r3, [pc, #44]	; (800efb8 <ip4_input_accept+0x50>)
- 800ef8c:	695a      	ldr	r2, [r3, #20]
- 800ef8e:	687b      	ldr	r3, [r7, #4]
- 800ef90:	3304      	adds	r3, #4
- 800ef92:	681b      	ldr	r3, [r3, #0]
- 800ef94:	429a      	cmp	r2, r3
- 800ef96:	d008      	beq.n	800efaa <ip4_input_accept+0x42>
-        /* or broadcast on this interface network address? */
-        ip4_addr_isbroadcast(ip4_current_dest_addr(), netif)
- 800ef98:	4b07      	ldr	r3, [pc, #28]	; (800efb8 <ip4_input_accept+0x50>)
- 800ef9a:	695b      	ldr	r3, [r3, #20]
- 800ef9c:	6879      	ldr	r1, [r7, #4]
- 800ef9e:	4618      	mov	r0, r3
- 800efa0:	f000 fa08 	bl	800f3b4 <ip4_addr_isbroadcast_u32>
- 800efa4:	4603      	mov	r3, r0
-    if (ip4_addr_cmp(ip4_current_dest_addr(), netif_ip4_addr(netif)) ||
- 800efa6:	2b00      	cmp	r3, #0
- 800efa8:	d001      	beq.n	800efae <ip4_input_accept+0x46>
-#endif /* LWIP_NETIF_LOOPBACK && !LWIP_HAVE_LOOPIF */
-       ) {
-      LWIP_DEBUGF(IP_DEBUG, ("ip4_input: packet accepted on interface %c%c\n",
-                             netif->name[0], netif->name[1]));
-      /* accept on this netif */
-      return 1;
- 800efaa:	2301      	movs	r3, #1
- 800efac:	e000      	b.n	800efb0 <ip4_input_accept+0x48>
-      /* accept on this netif */
-      return 1;
-    }
-#endif /* LWIP_AUTOIP */
-  }
-  return 0;
- 800efae:	2300      	movs	r3, #0
-}
- 800efb0:	4618      	mov	r0, r3
- 800efb2:	3708      	adds	r7, #8
- 800efb4:	46bd      	mov	sp, r7
- 800efb6:	bd80      	pop	{r7, pc}
- 800efb8:	24004c10 	.word	0x24004c10
-
-0800efbc <ip4_input>:
- * @return ERR_OK if the packet was processed (could return ERR_* if it wasn't
- *         processed, but currently always returns ERR_OK)
- */
-err_t
-ip4_input(struct pbuf *p, struct netif *inp)
-{
- 800efbc:	b580      	push	{r7, lr}
- 800efbe:	b086      	sub	sp, #24
- 800efc0:	af00      	add	r7, sp, #0
- 800efc2:	6078      	str	r0, [r7, #4]
- 800efc4:	6039      	str	r1, [r7, #0]
-
-  IP_STATS_INC(ip.recv);
-  MIB2_STATS_INC(mib2.ipinreceives);
-
-  /* identify the IP header */
-  iphdr = (struct ip_hdr *)p->payload;
- 800efc6:	687b      	ldr	r3, [r7, #4]
- 800efc8:	685b      	ldr	r3, [r3, #4]
- 800efca:	613b      	str	r3, [r7, #16]
-  if (IPH_V(iphdr) != 4) {
- 800efcc:	693b      	ldr	r3, [r7, #16]
- 800efce:	781b      	ldrb	r3, [r3, #0]
- 800efd0:	091b      	lsrs	r3, r3, #4
- 800efd2:	b2db      	uxtb	r3, r3
- 800efd4:	2b04      	cmp	r3, #4
- 800efd6:	d004      	beq.n	800efe2 <ip4_input+0x26>
-    LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_LEVEL_WARNING, ("IP packet dropped due to bad version number %"U16_F"\n", (u16_t)IPH_V(iphdr)));
-    ip4_debug_print(p);
-    pbuf_free(p);
- 800efd8:	6878      	ldr	r0, [r7, #4]
- 800efda:	f7f7 fffb 	bl	8006fd4 <pbuf_free>
-    IP_STATS_INC(ip.err);
-    IP_STATS_INC(ip.drop);
-    MIB2_STATS_INC(mib2.ipinhdrerrors);
-    return ERR_OK;
- 800efde:	2300      	movs	r3, #0
- 800efe0:	e107      	b.n	800f1f2 <ip4_input+0x236>
-    return ERR_OK;
-  }
-#endif
-
-  /* obtain IP header length in bytes */
-  iphdr_hlen = IPH_HL_BYTES(iphdr);
- 800efe2:	693b      	ldr	r3, [r7, #16]
- 800efe4:	781b      	ldrb	r3, [r3, #0]
- 800efe6:	f003 030f 	and.w	r3, r3, #15
- 800efea:	b2db      	uxtb	r3, r3
- 800efec:	009b      	lsls	r3, r3, #2
- 800efee:	b2db      	uxtb	r3, r3
- 800eff0:	81fb      	strh	r3, [r7, #14]
-  /* obtain ip length in bytes */
-  iphdr_len = lwip_ntohs(IPH_LEN(iphdr));
- 800eff2:	693b      	ldr	r3, [r7, #16]
- 800eff4:	885b      	ldrh	r3, [r3, #2]
- 800eff6:	b29b      	uxth	r3, r3
- 800eff8:	4618      	mov	r0, r3
- 800effa:	f7f6 faa7 	bl	800554c <lwip_htons>
- 800effe:	4603      	mov	r3, r0
- 800f000:	81bb      	strh	r3, [r7, #12]
-
-  /* Trim pbuf. This is especially required for packets < 60 bytes. */
-  if (iphdr_len < p->tot_len) {
- 800f002:	687b      	ldr	r3, [r7, #4]
- 800f004:	891b      	ldrh	r3, [r3, #8]
- 800f006:	89ba      	ldrh	r2, [r7, #12]
- 800f008:	429a      	cmp	r2, r3
- 800f00a:	d204      	bcs.n	800f016 <ip4_input+0x5a>
-    pbuf_realloc(p, iphdr_len);
- 800f00c:	89bb      	ldrh	r3, [r7, #12]
- 800f00e:	4619      	mov	r1, r3
- 800f010:	6878      	ldr	r0, [r7, #4]
- 800f012:	f7f7 fe59 	bl	8006cc8 <pbuf_realloc>
-  }
-
-  /* header length exceeds first pbuf length, or ip length exceeds total pbuf length? */
-  if ((iphdr_hlen > p->len) || (iphdr_len > p->tot_len) || (iphdr_hlen < IP_HLEN)) {
- 800f016:	687b      	ldr	r3, [r7, #4]
- 800f018:	895b      	ldrh	r3, [r3, #10]
- 800f01a:	89fa      	ldrh	r2, [r7, #14]
- 800f01c:	429a      	cmp	r2, r3
- 800f01e:	d807      	bhi.n	800f030 <ip4_input+0x74>
- 800f020:	687b      	ldr	r3, [r7, #4]
- 800f022:	891b      	ldrh	r3, [r3, #8]
- 800f024:	89ba      	ldrh	r2, [r7, #12]
- 800f026:	429a      	cmp	r2, r3
- 800f028:	d802      	bhi.n	800f030 <ip4_input+0x74>
- 800f02a:	89fb      	ldrh	r3, [r7, #14]
- 800f02c:	2b13      	cmp	r3, #19
- 800f02e:	d804      	bhi.n	800f03a <ip4_input+0x7e>
-      LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_LEVEL_SERIOUS,
-                  ("IP (len %"U16_F") is longer than pbuf (len %"U16_F"), IP packet dropped.\n",
-                   iphdr_len, p->tot_len));
-    }
-    /* free (drop) packet pbufs */
-    pbuf_free(p);
- 800f030:	6878      	ldr	r0, [r7, #4]
- 800f032:	f7f7 ffcf 	bl	8006fd4 <pbuf_free>
-    IP_STATS_INC(ip.lenerr);
-    IP_STATS_INC(ip.drop);
-    MIB2_STATS_INC(mib2.ipindiscards);
-    return ERR_OK;
- 800f036:	2300      	movs	r3, #0
- 800f038:	e0db      	b.n	800f1f2 <ip4_input+0x236>
-    }
-  }
-#endif
-
-  /* copy IP addresses to aligned ip_addr_t */
-  ip_addr_copy_from_ip4(ip_data.current_iphdr_dest, iphdr->dest);
- 800f03a:	693b      	ldr	r3, [r7, #16]
- 800f03c:	691b      	ldr	r3, [r3, #16]
- 800f03e:	4a6f      	ldr	r2, [pc, #444]	; (800f1fc <ip4_input+0x240>)
- 800f040:	6153      	str	r3, [r2, #20]
-  ip_addr_copy_from_ip4(ip_data.current_iphdr_src, iphdr->src);
- 800f042:	693b      	ldr	r3, [r7, #16]
- 800f044:	68db      	ldr	r3, [r3, #12]
- 800f046:	4a6d      	ldr	r2, [pc, #436]	; (800f1fc <ip4_input+0x240>)
- 800f048:	6113      	str	r3, [r2, #16]
-
-  /* match packet against an interface, i.e. is this packet for us? */
-  if (ip4_addr_ismulticast(ip4_current_dest_addr())) {
- 800f04a:	4b6c      	ldr	r3, [pc, #432]	; (800f1fc <ip4_input+0x240>)
- 800f04c:	695b      	ldr	r3, [r3, #20]
- 800f04e:	f003 03f0 	and.w	r3, r3, #240	; 0xf0
- 800f052:	2be0      	cmp	r3, #224	; 0xe0
- 800f054:	d112      	bne.n	800f07c <ip4_input+0xc0>
-      netif = inp;
-    } else {
-      netif = NULL;
-    }
-#else /* LWIP_IGMP */
-    if ((netif_is_up(inp)) && (!ip4_addr_isany_val(*netif_ip4_addr(inp)))) {
- 800f056:	683b      	ldr	r3, [r7, #0]
- 800f058:	f893 302d 	ldrb.w	r3, [r3, #45]	; 0x2d
- 800f05c:	f003 0301 	and.w	r3, r3, #1
- 800f060:	b2db      	uxtb	r3, r3
- 800f062:	2b00      	cmp	r3, #0
- 800f064:	d007      	beq.n	800f076 <ip4_input+0xba>
- 800f066:	683b      	ldr	r3, [r7, #0]
- 800f068:	3304      	adds	r3, #4
- 800f06a:	681b      	ldr	r3, [r3, #0]
- 800f06c:	2b00      	cmp	r3, #0
- 800f06e:	d002      	beq.n	800f076 <ip4_input+0xba>
-      netif = inp;
- 800f070:	683b      	ldr	r3, [r7, #0]
- 800f072:	617b      	str	r3, [r7, #20]
- 800f074:	e02a      	b.n	800f0cc <ip4_input+0x110>
-    } else {
-      netif = NULL;
- 800f076:	2300      	movs	r3, #0
- 800f078:	617b      	str	r3, [r7, #20]
- 800f07a:	e027      	b.n	800f0cc <ip4_input+0x110>
-    }
-#endif /* LWIP_IGMP */
-  } else {
-    /* start trying with inp. if that's not acceptable, start walking the
-       list of configured netifs. */
-    if (ip4_input_accept(inp)) {
- 800f07c:	6838      	ldr	r0, [r7, #0]
- 800f07e:	f7ff ff73 	bl	800ef68 <ip4_input_accept>
- 800f082:	4603      	mov	r3, r0
- 800f084:	2b00      	cmp	r3, #0
- 800f086:	d002      	beq.n	800f08e <ip4_input+0xd2>
-      netif = inp;
- 800f088:	683b      	ldr	r3, [r7, #0]
- 800f08a:	617b      	str	r3, [r7, #20]
- 800f08c:	e01e      	b.n	800f0cc <ip4_input+0x110>
-    } else {
-      netif = NULL;
- 800f08e:	2300      	movs	r3, #0
- 800f090:	617b      	str	r3, [r7, #20]
-#if !LWIP_NETIF_LOOPBACK || LWIP_HAVE_LOOPIF
-      /* Packets sent to the loopback address must not be accepted on an
-       * interface that does not have the loopback address assigned to it,
-       * unless a non-loopback interface is used for loopback traffic. */
-      if (!ip4_addr_isloopback(ip4_current_dest_addr()))
- 800f092:	4b5a      	ldr	r3, [pc, #360]	; (800f1fc <ip4_input+0x240>)
- 800f094:	695b      	ldr	r3, [r3, #20]
- 800f096:	b2db      	uxtb	r3, r3
- 800f098:	2b7f      	cmp	r3, #127	; 0x7f
- 800f09a:	d017      	beq.n	800f0cc <ip4_input+0x110>
-#endif /* !LWIP_NETIF_LOOPBACK || LWIP_HAVE_LOOPIF */
-      {
-#if !LWIP_SINGLE_NETIF
-        NETIF_FOREACH(netif) {
- 800f09c:	4b58      	ldr	r3, [pc, #352]	; (800f200 <ip4_input+0x244>)
- 800f09e:	681b      	ldr	r3, [r3, #0]
- 800f0a0:	617b      	str	r3, [r7, #20]
- 800f0a2:	e00e      	b.n	800f0c2 <ip4_input+0x106>
-          if (netif == inp) {
- 800f0a4:	697a      	ldr	r2, [r7, #20]
- 800f0a6:	683b      	ldr	r3, [r7, #0]
- 800f0a8:	429a      	cmp	r2, r3
- 800f0aa:	d006      	beq.n	800f0ba <ip4_input+0xfe>
-            /* we checked that before already */
-            continue;
-          }
-          if (ip4_input_accept(netif)) {
- 800f0ac:	6978      	ldr	r0, [r7, #20]
- 800f0ae:	f7ff ff5b 	bl	800ef68 <ip4_input_accept>
- 800f0b2:	4603      	mov	r3, r0
- 800f0b4:	2b00      	cmp	r3, #0
- 800f0b6:	d108      	bne.n	800f0ca <ip4_input+0x10e>
- 800f0b8:	e000      	b.n	800f0bc <ip4_input+0x100>
-            continue;
- 800f0ba:	bf00      	nop
-        NETIF_FOREACH(netif) {
- 800f0bc:	697b      	ldr	r3, [r7, #20]
- 800f0be:	681b      	ldr	r3, [r3, #0]
- 800f0c0:	617b      	str	r3, [r7, #20]
- 800f0c2:	697b      	ldr	r3, [r7, #20]
- 800f0c4:	2b00      	cmp	r3, #0
- 800f0c6:	d1ed      	bne.n	800f0a4 <ip4_input+0xe8>
- 800f0c8:	e000      	b.n	800f0cc <ip4_input+0x110>
-            break;
- 800f0ca:	bf00      	nop
-      && !ip4_addr_isany_val(*ip4_current_src_addr())
-#endif /* IP_ACCEPT_LINK_LAYER_ADDRESSING */
-     )
-#endif /* LWIP_IGMP || IP_ACCEPT_LINK_LAYER_ADDRESSING */
-  {
-    if ((ip4_addr_isbroadcast(ip4_current_src_addr(), inp)) ||
- 800f0cc:	4b4b      	ldr	r3, [pc, #300]	; (800f1fc <ip4_input+0x240>)
- 800f0ce:	691b      	ldr	r3, [r3, #16]
- 800f0d0:	6839      	ldr	r1, [r7, #0]
- 800f0d2:	4618      	mov	r0, r3
- 800f0d4:	f000 f96e 	bl	800f3b4 <ip4_addr_isbroadcast_u32>
- 800f0d8:	4603      	mov	r3, r0
- 800f0da:	2b00      	cmp	r3, #0
- 800f0dc:	d105      	bne.n	800f0ea <ip4_input+0x12e>
-        (ip4_addr_ismulticast(ip4_current_src_addr()))) {
- 800f0de:	4b47      	ldr	r3, [pc, #284]	; (800f1fc <ip4_input+0x240>)
- 800f0e0:	691b      	ldr	r3, [r3, #16]
- 800f0e2:	f003 03f0 	and.w	r3, r3, #240	; 0xf0
-    if ((ip4_addr_isbroadcast(ip4_current_src_addr(), inp)) ||
- 800f0e6:	2be0      	cmp	r3, #224	; 0xe0
- 800f0e8:	d104      	bne.n	800f0f4 <ip4_input+0x138>
-      /* packet source is not valid */
-      LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_WARNING, ("ip4_input: packet source is not valid.\n"));
-      /* free (drop) packet pbufs */
-      pbuf_free(p);
- 800f0ea:	6878      	ldr	r0, [r7, #4]
- 800f0ec:	f7f7 ff72 	bl	8006fd4 <pbuf_free>
-      IP_STATS_INC(ip.drop);
-      MIB2_STATS_INC(mib2.ipinaddrerrors);
-      MIB2_STATS_INC(mib2.ipindiscards);
-      return ERR_OK;
- 800f0f0:	2300      	movs	r3, #0
- 800f0f2:	e07e      	b.n	800f1f2 <ip4_input+0x236>
-    }
-  }
-
-  /* packet not for us? */
-  if (netif == NULL) {
- 800f0f4:	697b      	ldr	r3, [r7, #20]
- 800f0f6:	2b00      	cmp	r3, #0
- 800f0f8:	d104      	bne.n	800f104 <ip4_input+0x148>
-    {
-      IP_STATS_INC(ip.drop);
-      MIB2_STATS_INC(mib2.ipinaddrerrors);
-      MIB2_STATS_INC(mib2.ipindiscards);
-    }
-    pbuf_free(p);
- 800f0fa:	6878      	ldr	r0, [r7, #4]
- 800f0fc:	f7f7 ff6a 	bl	8006fd4 <pbuf_free>
-    return ERR_OK;
- 800f100:	2300      	movs	r3, #0
- 800f102:	e076      	b.n	800f1f2 <ip4_input+0x236>
-  }
-  /* packet consists of multiple fragments? */
-  if ((IPH_OFFSET(iphdr) & PP_HTONS(IP_OFFMASK | IP_MF)) != 0) {
- 800f104:	693b      	ldr	r3, [r7, #16]
- 800f106:	88db      	ldrh	r3, [r3, #6]
- 800f108:	b29b      	uxth	r3, r3
- 800f10a:	461a      	mov	r2, r3
- 800f10c:	f64f 733f 	movw	r3, #65343	; 0xff3f
- 800f110:	4013      	ands	r3, r2
- 800f112:	2b00      	cmp	r3, #0
- 800f114:	d00b      	beq.n	800f12e <ip4_input+0x172>
-#if IP_REASSEMBLY /* packet fragment reassembly code present? */
-    LWIP_DEBUGF(IP_DEBUG, ("IP packet is a fragment (id=0x%04"X16_F" tot_len=%"U16_F" len=%"U16_F" MF=%"U16_F" offset=%"U16_F"), calling ip4_reass()\n",
-                           lwip_ntohs(IPH_ID(iphdr)), p->tot_len, lwip_ntohs(IPH_LEN(iphdr)), (u16_t)!!(IPH_OFFSET(iphdr) & PP_HTONS(IP_MF)), (u16_t)((lwip_ntohs(IPH_OFFSET(iphdr)) & IP_OFFMASK) * 8)));
-    /* reassemble the packet*/
-    p = ip4_reass(p);
- 800f116:	6878      	ldr	r0, [r7, #4]
- 800f118:	f000 fc92 	bl	800fa40 <ip4_reass>
- 800f11c:	6078      	str	r0, [r7, #4]
-    /* packet not fully reassembled yet? */
-    if (p == NULL) {
- 800f11e:	687b      	ldr	r3, [r7, #4]
- 800f120:	2b00      	cmp	r3, #0
- 800f122:	d101      	bne.n	800f128 <ip4_input+0x16c>
-      return ERR_OK;
- 800f124:	2300      	movs	r3, #0
- 800f126:	e064      	b.n	800f1f2 <ip4_input+0x236>
-    }
-    iphdr = (const struct ip_hdr *)p->payload;
- 800f128:	687b      	ldr	r3, [r7, #4]
- 800f12a:	685b      	ldr	r3, [r3, #4]
- 800f12c:	613b      	str	r3, [r7, #16]
-  /* send to upper layers */
-  LWIP_DEBUGF(IP_DEBUG, ("ip4_input: \n"));
-  ip4_debug_print(p);
-  LWIP_DEBUGF(IP_DEBUG, ("ip4_input: p->len %"U16_F" p->tot_len %"U16_F"\n", p->len, p->tot_len));
-
-  ip_data.current_netif = netif;
- 800f12e:	4a33      	ldr	r2, [pc, #204]	; (800f1fc <ip4_input+0x240>)
- 800f130:	697b      	ldr	r3, [r7, #20]
- 800f132:	6013      	str	r3, [r2, #0]
-  ip_data.current_input_netif = inp;
- 800f134:	4a31      	ldr	r2, [pc, #196]	; (800f1fc <ip4_input+0x240>)
- 800f136:	683b      	ldr	r3, [r7, #0]
- 800f138:	6053      	str	r3, [r2, #4]
-  ip_data.current_ip4_header = iphdr;
- 800f13a:	4a30      	ldr	r2, [pc, #192]	; (800f1fc <ip4_input+0x240>)
- 800f13c:	693b      	ldr	r3, [r7, #16]
- 800f13e:	6093      	str	r3, [r2, #8]
-  ip_data.current_ip_header_tot_len = IPH_HL_BYTES(iphdr);
- 800f140:	693b      	ldr	r3, [r7, #16]
- 800f142:	781b      	ldrb	r3, [r3, #0]
- 800f144:	f003 030f 	and.w	r3, r3, #15
- 800f148:	b2db      	uxtb	r3, r3
- 800f14a:	009b      	lsls	r3, r3, #2
- 800f14c:	b2db      	uxtb	r3, r3
- 800f14e:	b29a      	uxth	r2, r3
- 800f150:	4b2a      	ldr	r3, [pc, #168]	; (800f1fc <ip4_input+0x240>)
- 800f152:	819a      	strh	r2, [r3, #12]
-  /* raw input did not eat the packet? */
-  raw_status = raw_input(p, inp);
-  if (raw_status != RAW_INPUT_EATEN)
-#endif /* LWIP_RAW */
-  {
-    pbuf_remove_header(p, iphdr_hlen); /* Move to payload, no check necessary. */
- 800f154:	89fb      	ldrh	r3, [r7, #14]
- 800f156:	4619      	mov	r1, r3
- 800f158:	6878      	ldr	r0, [r7, #4]
- 800f15a:	f7f7 feb5 	bl	8006ec8 <pbuf_remove_header>
-
-    switch (IPH_PROTO(iphdr)) {
- 800f15e:	693b      	ldr	r3, [r7, #16]
- 800f160:	7a5b      	ldrb	r3, [r3, #9]
- 800f162:	2b11      	cmp	r3, #17
- 800f164:	d006      	beq.n	800f174 <ip4_input+0x1b8>
- 800f166:	2b11      	cmp	r3, #17
- 800f168:	dc13      	bgt.n	800f192 <ip4_input+0x1d6>
- 800f16a:	2b01      	cmp	r3, #1
- 800f16c:	d00c      	beq.n	800f188 <ip4_input+0x1cc>
- 800f16e:	2b06      	cmp	r3, #6
- 800f170:	d005      	beq.n	800f17e <ip4_input+0x1c2>
- 800f172:	e00e      	b.n	800f192 <ip4_input+0x1d6>
-      case IP_PROTO_UDP:
-#if LWIP_UDPLITE
-      case IP_PROTO_UDPLITE:
-#endif /* LWIP_UDPLITE */
-        MIB2_STATS_INC(mib2.ipindelivers);
-        udp_input(p, inp);
- 800f174:	6839      	ldr	r1, [r7, #0]
- 800f176:	6878      	ldr	r0, [r7, #4]
- 800f178:	f7fe fb7e 	bl	800d878 <udp_input>
-        break;
- 800f17c:	e026      	b.n	800f1cc <ip4_input+0x210>
-#endif /* LWIP_UDP */
-#if LWIP_TCP
-      case IP_PROTO_TCP:
-        MIB2_STATS_INC(mib2.ipindelivers);
-        tcp_input(p, inp);
- 800f17e:	6839      	ldr	r1, [r7, #0]
- 800f180:	6878      	ldr	r0, [r7, #4]
- 800f182:	f7f9 ff33 	bl	8008fec <tcp_input>
-        break;
- 800f186:	e021      	b.n	800f1cc <ip4_input+0x210>
-#endif /* LWIP_TCP */
-#if LWIP_ICMP
-      case IP_PROTO_ICMP:
-        MIB2_STATS_INC(mib2.ipindelivers);
-        icmp_input(p, inp);
- 800f188:	6839      	ldr	r1, [r7, #0]
- 800f18a:	6878      	ldr	r0, [r7, #4]
- 800f18c:	f7ff fc32 	bl	800e9f4 <icmp_input>
-        break;
- 800f190:	e01c      	b.n	800f1cc <ip4_input+0x210>
-        } else
-#endif /* LWIP_RAW */
-        {
-#if LWIP_ICMP
-          /* send ICMP destination protocol unreachable unless is was a broadcast */
-          if (!ip4_addr_isbroadcast(ip4_current_dest_addr(), netif) &&
- 800f192:	4b1a      	ldr	r3, [pc, #104]	; (800f1fc <ip4_input+0x240>)
- 800f194:	695b      	ldr	r3, [r3, #20]
- 800f196:	6979      	ldr	r1, [r7, #20]
- 800f198:	4618      	mov	r0, r3
- 800f19a:	f000 f90b 	bl	800f3b4 <ip4_addr_isbroadcast_u32>
- 800f19e:	4603      	mov	r3, r0
- 800f1a0:	2b00      	cmp	r3, #0
- 800f1a2:	d10f      	bne.n	800f1c4 <ip4_input+0x208>
-              !ip4_addr_ismulticast(ip4_current_dest_addr())) {
- 800f1a4:	4b15      	ldr	r3, [pc, #84]	; (800f1fc <ip4_input+0x240>)
- 800f1a6:	695b      	ldr	r3, [r3, #20]
- 800f1a8:	f003 03f0 	and.w	r3, r3, #240	; 0xf0
-          if (!ip4_addr_isbroadcast(ip4_current_dest_addr(), netif) &&
- 800f1ac:	2be0      	cmp	r3, #224	; 0xe0
- 800f1ae:	d009      	beq.n	800f1c4 <ip4_input+0x208>
-            pbuf_header_force(p, (s16_t)iphdr_hlen); /* Move to ip header, no check necessary. */
- 800f1b0:	f9b7 300e 	ldrsh.w	r3, [r7, #14]
- 800f1b4:	4619      	mov	r1, r3
- 800f1b6:	6878      	ldr	r0, [r7, #4]
- 800f1b8:	f7f7 fef9 	bl	8006fae <pbuf_header_force>
-            icmp_dest_unreach(p, ICMP_DUR_PROTO);
- 800f1bc:	2102      	movs	r1, #2
- 800f1be:	6878      	ldr	r0, [r7, #4]
- 800f1c0:	f7ff fd8e 	bl	800ece0 <icmp_dest_unreach>
-
-          IP_STATS_INC(ip.proterr);
-          IP_STATS_INC(ip.drop);
-          MIB2_STATS_INC(mib2.ipinunknownprotos);
-        }
-        pbuf_free(p);
- 800f1c4:	6878      	ldr	r0, [r7, #4]
- 800f1c6:	f7f7 ff05 	bl	8006fd4 <pbuf_free>
-        break;
- 800f1ca:	bf00      	nop
-    }
-  }
-
-  /* @todo: this is not really necessary... */
-  ip_data.current_netif = NULL;
- 800f1cc:	4b0b      	ldr	r3, [pc, #44]	; (800f1fc <ip4_input+0x240>)
- 800f1ce:	2200      	movs	r2, #0
- 800f1d0:	601a      	str	r2, [r3, #0]
-  ip_data.current_input_netif = NULL;
- 800f1d2:	4b0a      	ldr	r3, [pc, #40]	; (800f1fc <ip4_input+0x240>)
- 800f1d4:	2200      	movs	r2, #0
- 800f1d6:	605a      	str	r2, [r3, #4]
-  ip_data.current_ip4_header = NULL;
- 800f1d8:	4b08      	ldr	r3, [pc, #32]	; (800f1fc <ip4_input+0x240>)
- 800f1da:	2200      	movs	r2, #0
- 800f1dc:	609a      	str	r2, [r3, #8]
-  ip_data.current_ip_header_tot_len = 0;
- 800f1de:	4b07      	ldr	r3, [pc, #28]	; (800f1fc <ip4_input+0x240>)
- 800f1e0:	2200      	movs	r2, #0
- 800f1e2:	819a      	strh	r2, [r3, #12]
-  ip4_addr_set_any(ip4_current_src_addr());
- 800f1e4:	4b05      	ldr	r3, [pc, #20]	; (800f1fc <ip4_input+0x240>)
- 800f1e6:	2200      	movs	r2, #0
- 800f1e8:	611a      	str	r2, [r3, #16]
-  ip4_addr_set_any(ip4_current_dest_addr());
- 800f1ea:	4b04      	ldr	r3, [pc, #16]	; (800f1fc <ip4_input+0x240>)
- 800f1ec:	2200      	movs	r2, #0
- 800f1ee:	615a      	str	r2, [r3, #20]
-
-  return ERR_OK;
- 800f1f0:	2300      	movs	r3, #0
-}
- 800f1f2:	4618      	mov	r0, r3
- 800f1f4:	3718      	adds	r7, #24
- 800f1f6:	46bd      	mov	sp, r7
- 800f1f8:	bd80      	pop	{r7, pc}
- 800f1fa:	bf00      	nop
- 800f1fc:	24004c10 	.word	0x24004c10
- 800f200:	24007b60 	.word	0x24007b60
-
-0800f204 <ip4_output_if>:
- */
-err_t
-ip4_output_if(struct pbuf *p, const ip4_addr_t *src, const ip4_addr_t *dest,
-              u8_t ttl, u8_t tos,
-              u8_t proto, struct netif *netif)
-{
- 800f204:	b580      	push	{r7, lr}
- 800f206:	b08a      	sub	sp, #40	; 0x28
- 800f208:	af04      	add	r7, sp, #16
- 800f20a:	60f8      	str	r0, [r7, #12]
- 800f20c:	60b9      	str	r1, [r7, #8]
- 800f20e:	607a      	str	r2, [r7, #4]
- 800f210:	70fb      	strb	r3, [r7, #3]
-ip4_output_if_opt(struct pbuf *p, const ip4_addr_t *src, const ip4_addr_t *dest,
-                  u8_t ttl, u8_t tos, u8_t proto, struct netif *netif, void *ip_options,
-                  u16_t optlen)
-{
-#endif /* IP_OPTIONS_SEND */
-  const ip4_addr_t *src_used = src;
- 800f212:	68bb      	ldr	r3, [r7, #8]
- 800f214:	617b      	str	r3, [r7, #20]
-  if (dest != LWIP_IP_HDRINCL) {
- 800f216:	687b      	ldr	r3, [r7, #4]
- 800f218:	2b00      	cmp	r3, #0
- 800f21a:	d009      	beq.n	800f230 <ip4_output_if+0x2c>
-    if (ip4_addr_isany(src)) {
- 800f21c:	68bb      	ldr	r3, [r7, #8]
- 800f21e:	2b00      	cmp	r3, #0
- 800f220:	d003      	beq.n	800f22a <ip4_output_if+0x26>
- 800f222:	68bb      	ldr	r3, [r7, #8]
- 800f224:	681b      	ldr	r3, [r3, #0]
- 800f226:	2b00      	cmp	r3, #0
- 800f228:	d102      	bne.n	800f230 <ip4_output_if+0x2c>
-      src_used = netif_ip4_addr(netif);
- 800f22a:	6abb      	ldr	r3, [r7, #40]	; 0x28
- 800f22c:	3304      	adds	r3, #4
- 800f22e:	617b      	str	r3, [r7, #20]
-
-#if IP_OPTIONS_SEND
-  return ip4_output_if_opt_src(p, src_used, dest, ttl, tos, proto, netif,
-                               ip_options, optlen);
-#else /* IP_OPTIONS_SEND */
-  return ip4_output_if_src(p, src_used, dest, ttl, tos, proto, netif);
- 800f230:	78fa      	ldrb	r2, [r7, #3]
- 800f232:	6abb      	ldr	r3, [r7, #40]	; 0x28
- 800f234:	9302      	str	r3, [sp, #8]
- 800f236:	f897 3024 	ldrb.w	r3, [r7, #36]	; 0x24
- 800f23a:	9301      	str	r3, [sp, #4]
- 800f23c:	f897 3020 	ldrb.w	r3, [r7, #32]
- 800f240:	9300      	str	r3, [sp, #0]
- 800f242:	4613      	mov	r3, r2
- 800f244:	687a      	ldr	r2, [r7, #4]
- 800f246:	6979      	ldr	r1, [r7, #20]
- 800f248:	68f8      	ldr	r0, [r7, #12]
- 800f24a:	f000 f805 	bl	800f258 <ip4_output_if_src>
- 800f24e:	4603      	mov	r3, r0
-#endif /* IP_OPTIONS_SEND */
-}
- 800f250:	4618      	mov	r0, r3
- 800f252:	3718      	adds	r7, #24
- 800f254:	46bd      	mov	sp, r7
- 800f256:	bd80      	pop	{r7, pc}
-
-0800f258 <ip4_output_if_src>:
- */
-err_t
-ip4_output_if_src(struct pbuf *p, const ip4_addr_t *src, const ip4_addr_t *dest,
-                  u8_t ttl, u8_t tos,
-                  u8_t proto, struct netif *netif)
-{
- 800f258:	b580      	push	{r7, lr}
- 800f25a:	b088      	sub	sp, #32
- 800f25c:	af00      	add	r7, sp, #0
- 800f25e:	60f8      	str	r0, [r7, #12]
- 800f260:	60b9      	str	r1, [r7, #8]
- 800f262:	607a      	str	r2, [r7, #4]
- 800f264:	70fb      	strb	r3, [r7, #3]
-#if CHECKSUM_GEN_IP_INLINE
-  u32_t chk_sum = 0;
-#endif /* CHECKSUM_GEN_IP_INLINE */
-
-  LWIP_ASSERT_CORE_LOCKED();
-  LWIP_IP_CHECK_PBUF_REF_COUNT_FOR_TX(p);
- 800f266:	68fb      	ldr	r3, [r7, #12]
- 800f268:	7b9b      	ldrb	r3, [r3, #14]
- 800f26a:	2b01      	cmp	r3, #1
- 800f26c:	d006      	beq.n	800f27c <ip4_output_if_src+0x24>
- 800f26e:	4b4b      	ldr	r3, [pc, #300]	; (800f39c <ip4_output_if_src+0x144>)
- 800f270:	f44f 7255 	mov.w	r2, #852	; 0x354
- 800f274:	494a      	ldr	r1, [pc, #296]	; (800f3a0 <ip4_output_if_src+0x148>)
- 800f276:	484b      	ldr	r0, [pc, #300]	; (800f3a4 <ip4_output_if_src+0x14c>)
- 800f278:	f001 fca6 	bl	8010bc8 <iprintf>
-
-  MIB2_STATS_INC(mib2.ipoutrequests);
-
-  /* Should the IP header be generated or is it already included in p? */
-  if (dest != LWIP_IP_HDRINCL) {
- 800f27c:	687b      	ldr	r3, [r7, #4]
- 800f27e:	2b00      	cmp	r3, #0
- 800f280:	d060      	beq.n	800f344 <ip4_output_if_src+0xec>
-    u16_t ip_hlen = IP_HLEN;
- 800f282:	2314      	movs	r3, #20
- 800f284:	837b      	strh	r3, [r7, #26]
-      }
-#endif /* CHECKSUM_GEN_IP_INLINE */
-    }
-#endif /* IP_OPTIONS_SEND */
-    /* generate IP header */
-    if (pbuf_add_header(p, IP_HLEN)) {
- 800f286:	2114      	movs	r1, #20
- 800f288:	68f8      	ldr	r0, [r7, #12]
- 800f28a:	f7f7 fe0d 	bl	8006ea8 <pbuf_add_header>
- 800f28e:	4603      	mov	r3, r0
- 800f290:	2b00      	cmp	r3, #0
- 800f292:	d002      	beq.n	800f29a <ip4_output_if_src+0x42>
-      LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("ip4_output: not enough room for IP header in pbuf\n"));
-
-      IP_STATS_INC(ip.err);
-      MIB2_STATS_INC(mib2.ipoutdiscards);
-      return ERR_BUF;
- 800f294:	f06f 0301 	mvn.w	r3, #1
- 800f298:	e07c      	b.n	800f394 <ip4_output_if_src+0x13c>
-    }
-
-    iphdr = (struct ip_hdr *)p->payload;
- 800f29a:	68fb      	ldr	r3, [r7, #12]
- 800f29c:	685b      	ldr	r3, [r3, #4]
- 800f29e:	61fb      	str	r3, [r7, #28]
-    LWIP_ASSERT("check that first pbuf can hold struct ip_hdr",
- 800f2a0:	68fb      	ldr	r3, [r7, #12]
- 800f2a2:	895b      	ldrh	r3, [r3, #10]
- 800f2a4:	2b13      	cmp	r3, #19
- 800f2a6:	d806      	bhi.n	800f2b6 <ip4_output_if_src+0x5e>
- 800f2a8:	4b3c      	ldr	r3, [pc, #240]	; (800f39c <ip4_output_if_src+0x144>)
- 800f2aa:	f44f 7262 	mov.w	r2, #904	; 0x388
- 800f2ae:	493e      	ldr	r1, [pc, #248]	; (800f3a8 <ip4_output_if_src+0x150>)
- 800f2b0:	483c      	ldr	r0, [pc, #240]	; (800f3a4 <ip4_output_if_src+0x14c>)
- 800f2b2:	f001 fc89 	bl	8010bc8 <iprintf>
-                (p->len >= sizeof(struct ip_hdr)));
-
-    IPH_TTL_SET(iphdr, ttl);
- 800f2b6:	69fb      	ldr	r3, [r7, #28]
- 800f2b8:	78fa      	ldrb	r2, [r7, #3]
- 800f2ba:	721a      	strb	r2, [r3, #8]
-    IPH_PROTO_SET(iphdr, proto);
- 800f2bc:	69fb      	ldr	r3, [r7, #28]
- 800f2be:	f897 202c 	ldrb.w	r2, [r7, #44]	; 0x2c
- 800f2c2:	725a      	strb	r2, [r3, #9]
-#if CHECKSUM_GEN_IP_INLINE
-    chk_sum += PP_NTOHS(proto | (ttl << 8));
-#endif /* CHECKSUM_GEN_IP_INLINE */
-
-    /* dest cannot be NULL here */
-    ip4_addr_copy(iphdr->dest, *dest);
- 800f2c4:	687b      	ldr	r3, [r7, #4]
- 800f2c6:	681a      	ldr	r2, [r3, #0]
- 800f2c8:	69fb      	ldr	r3, [r7, #28]
- 800f2ca:	611a      	str	r2, [r3, #16]
-#if CHECKSUM_GEN_IP_INLINE
-    chk_sum += ip4_addr_get_u32(&iphdr->dest) & 0xFFFF;
-    chk_sum += ip4_addr_get_u32(&iphdr->dest) >> 16;
-#endif /* CHECKSUM_GEN_IP_INLINE */
-
-    IPH_VHL_SET(iphdr, 4, ip_hlen / 4);
- 800f2cc:	8b7b      	ldrh	r3, [r7, #26]
- 800f2ce:	089b      	lsrs	r3, r3, #2
- 800f2d0:	b29b      	uxth	r3, r3
- 800f2d2:	b2db      	uxtb	r3, r3
- 800f2d4:	f043 0340 	orr.w	r3, r3, #64	; 0x40
- 800f2d8:	b2da      	uxtb	r2, r3
- 800f2da:	69fb      	ldr	r3, [r7, #28]
- 800f2dc:	701a      	strb	r2, [r3, #0]
-    IPH_TOS_SET(iphdr, tos);
- 800f2de:	69fb      	ldr	r3, [r7, #28]
- 800f2e0:	f897 2028 	ldrb.w	r2, [r7, #40]	; 0x28
- 800f2e4:	705a      	strb	r2, [r3, #1]
-#if CHECKSUM_GEN_IP_INLINE
-    chk_sum += PP_NTOHS(tos | (iphdr->_v_hl << 8));
-#endif /* CHECKSUM_GEN_IP_INLINE */
-    IPH_LEN_SET(iphdr, lwip_htons(p->tot_len));
- 800f2e6:	68fb      	ldr	r3, [r7, #12]
- 800f2e8:	891b      	ldrh	r3, [r3, #8]
- 800f2ea:	4618      	mov	r0, r3
- 800f2ec:	f7f6 f92e 	bl	800554c <lwip_htons>
- 800f2f0:	4603      	mov	r3, r0
- 800f2f2:	461a      	mov	r2, r3
- 800f2f4:	69fb      	ldr	r3, [r7, #28]
- 800f2f6:	805a      	strh	r2, [r3, #2]
-#if CHECKSUM_GEN_IP_INLINE
-    chk_sum += iphdr->_len;
-#endif /* CHECKSUM_GEN_IP_INLINE */
-    IPH_OFFSET_SET(iphdr, 0);
- 800f2f8:	69fb      	ldr	r3, [r7, #28]
- 800f2fa:	2200      	movs	r2, #0
- 800f2fc:	719a      	strb	r2, [r3, #6]
- 800f2fe:	2200      	movs	r2, #0
- 800f300:	71da      	strb	r2, [r3, #7]
-    IPH_ID_SET(iphdr, lwip_htons(ip_id));
- 800f302:	4b2a      	ldr	r3, [pc, #168]	; (800f3ac <ip4_output_if_src+0x154>)
- 800f304:	881b      	ldrh	r3, [r3, #0]
- 800f306:	4618      	mov	r0, r3
- 800f308:	f7f6 f920 	bl	800554c <lwip_htons>
- 800f30c:	4603      	mov	r3, r0
- 800f30e:	461a      	mov	r2, r3
- 800f310:	69fb      	ldr	r3, [r7, #28]
- 800f312:	809a      	strh	r2, [r3, #4]
-#if CHECKSUM_GEN_IP_INLINE
-    chk_sum += iphdr->_id;
-#endif /* CHECKSUM_GEN_IP_INLINE */
-    ++ip_id;
- 800f314:	4b25      	ldr	r3, [pc, #148]	; (800f3ac <ip4_output_if_src+0x154>)
- 800f316:	881b      	ldrh	r3, [r3, #0]
- 800f318:	3301      	adds	r3, #1
- 800f31a:	b29a      	uxth	r2, r3
- 800f31c:	4b23      	ldr	r3, [pc, #140]	; (800f3ac <ip4_output_if_src+0x154>)
- 800f31e:	801a      	strh	r2, [r3, #0]
-
-    if (src == NULL) {
- 800f320:	68bb      	ldr	r3, [r7, #8]
- 800f322:	2b00      	cmp	r3, #0
- 800f324:	d104      	bne.n	800f330 <ip4_output_if_src+0xd8>
-      ip4_addr_copy(iphdr->src, *IP4_ADDR_ANY4);
- 800f326:	4b22      	ldr	r3, [pc, #136]	; (800f3b0 <ip4_output_if_src+0x158>)
- 800f328:	681a      	ldr	r2, [r3, #0]
- 800f32a:	69fb      	ldr	r3, [r7, #28]
- 800f32c:	60da      	str	r2, [r3, #12]
- 800f32e:	e003      	b.n	800f338 <ip4_output_if_src+0xe0>
-    } else {
-      /* src cannot be NULL here */
-      ip4_addr_copy(iphdr->src, *src);
- 800f330:	68bb      	ldr	r3, [r7, #8]
- 800f332:	681a      	ldr	r2, [r3, #0]
- 800f334:	69fb      	ldr	r3, [r7, #28]
- 800f336:	60da      	str	r2, [r3, #12]
-    else {
-      IPH_CHKSUM_SET(iphdr, 0);
-    }
-#endif /* LWIP_CHECKSUM_CTRL_PER_NETIF*/
-#else /* CHECKSUM_GEN_IP_INLINE */
-    IPH_CHKSUM_SET(iphdr, 0);
- 800f338:	69fb      	ldr	r3, [r7, #28]
- 800f33a:	2200      	movs	r2, #0
- 800f33c:	729a      	strb	r2, [r3, #10]
- 800f33e:	2200      	movs	r2, #0
- 800f340:	72da      	strb	r2, [r3, #11]
- 800f342:	e00f      	b.n	800f364 <ip4_output_if_src+0x10c>
-    }
-#endif /* CHECKSUM_GEN_IP */
-#endif /* CHECKSUM_GEN_IP_INLINE */
-  } else {
-    /* IP header already included in p */
-    if (p->len < IP_HLEN) {
- 800f344:	68fb      	ldr	r3, [r7, #12]
- 800f346:	895b      	ldrh	r3, [r3, #10]
- 800f348:	2b13      	cmp	r3, #19
- 800f34a:	d802      	bhi.n	800f352 <ip4_output_if_src+0xfa>
-      LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("ip4_output: LWIP_IP_HDRINCL but pbuf is too short\n"));
-      IP_STATS_INC(ip.err);
-      MIB2_STATS_INC(mib2.ipoutdiscards);
-      return ERR_BUF;
- 800f34c:	f06f 0301 	mvn.w	r3, #1
- 800f350:	e020      	b.n	800f394 <ip4_output_if_src+0x13c>
-    }
-    iphdr = (struct ip_hdr *)p->payload;
- 800f352:	68fb      	ldr	r3, [r7, #12]
- 800f354:	685b      	ldr	r3, [r3, #4]
- 800f356:	61fb      	str	r3, [r7, #28]
-    ip4_addr_copy(dest_addr, iphdr->dest);
- 800f358:	69fb      	ldr	r3, [r7, #28]
- 800f35a:	691b      	ldr	r3, [r3, #16]
- 800f35c:	617b      	str	r3, [r7, #20]
-    dest = &dest_addr;
- 800f35e:	f107 0314 	add.w	r3, r7, #20
- 800f362:	607b      	str	r3, [r7, #4]
-  }
-#endif /* LWIP_MULTICAST_TX_OPTIONS */
-#endif /* ENABLE_LOOPBACK */
-#if IP_FRAG
-  /* don't fragment if interface has mtu set to 0 [loopif] */
-  if (netif->mtu && (p->tot_len > netif->mtu)) {
- 800f364:	6b3b      	ldr	r3, [r7, #48]	; 0x30
- 800f366:	8c9b      	ldrh	r3, [r3, #36]	; 0x24
- 800f368:	2b00      	cmp	r3, #0
- 800f36a:	d00c      	beq.n	800f386 <ip4_output_if_src+0x12e>
- 800f36c:	68fb      	ldr	r3, [r7, #12]
- 800f36e:	891a      	ldrh	r2, [r3, #8]
- 800f370:	6b3b      	ldr	r3, [r7, #48]	; 0x30
- 800f372:	8c9b      	ldrh	r3, [r3, #36]	; 0x24
- 800f374:	429a      	cmp	r2, r3
- 800f376:	d906      	bls.n	800f386 <ip4_output_if_src+0x12e>
-    return ip4_frag(p, netif, dest);
- 800f378:	687a      	ldr	r2, [r7, #4]
- 800f37a:	6b39      	ldr	r1, [r7, #48]	; 0x30
- 800f37c:	68f8      	ldr	r0, [r7, #12]
- 800f37e:	f000 fd53 	bl	800fe28 <ip4_frag>
- 800f382:	4603      	mov	r3, r0
- 800f384:	e006      	b.n	800f394 <ip4_output_if_src+0x13c>
-  }
-#endif /* IP_FRAG */
-
-  LWIP_DEBUGF(IP_DEBUG, ("ip4_output_if: call netif->output()\n"));
-  return netif->output(netif, p, dest);
- 800f386:	6b3b      	ldr	r3, [r7, #48]	; 0x30
- 800f388:	695b      	ldr	r3, [r3, #20]
- 800f38a:	687a      	ldr	r2, [r7, #4]
- 800f38c:	68f9      	ldr	r1, [r7, #12]
- 800f38e:	6b38      	ldr	r0, [r7, #48]	; 0x30
- 800f390:	4798      	blx	r3
- 800f392:	4603      	mov	r3, r0
-}
- 800f394:	4618      	mov	r0, r3
- 800f396:	3720      	adds	r7, #32
- 800f398:	46bd      	mov	sp, r7
- 800f39a:	bd80      	pop	{r7, pc}
- 800f39c:	08014924 	.word	0x08014924
- 800f3a0:	08014958 	.word	0x08014958
- 800f3a4:	08014964 	.word	0x08014964
- 800f3a8:	0801498c 	.word	0x0801498c
- 800f3ac:	24007cc2 	.word	0x24007cc2
- 800f3b0:	08014d94 	.word	0x08014d94
-
-0800f3b4 <ip4_addr_isbroadcast_u32>:
- * @param netif the network interface against which the address is checked
- * @return returns non-zero if the address is a broadcast address
- */
-u8_t
-ip4_addr_isbroadcast_u32(u32_t addr, const struct netif *netif)
-{
- 800f3b4:	b480      	push	{r7}
- 800f3b6:	b085      	sub	sp, #20
- 800f3b8:	af00      	add	r7, sp, #0
- 800f3ba:	6078      	str	r0, [r7, #4]
- 800f3bc:	6039      	str	r1, [r7, #0]
-  ip4_addr_t ipaddr;
-  ip4_addr_set_u32(&ipaddr, addr);
- 800f3be:	687b      	ldr	r3, [r7, #4]
- 800f3c0:	60fb      	str	r3, [r7, #12]
-
-  /* all ones (broadcast) or all zeroes (old skool broadcast) */
-  if ((~addr == IPADDR_ANY) ||
- 800f3c2:	687b      	ldr	r3, [r7, #4]
- 800f3c4:	f1b3 3fff 	cmp.w	r3, #4294967295
- 800f3c8:	d002      	beq.n	800f3d0 <ip4_addr_isbroadcast_u32+0x1c>
- 800f3ca:	687b      	ldr	r3, [r7, #4]
- 800f3cc:	2b00      	cmp	r3, #0
- 800f3ce:	d101      	bne.n	800f3d4 <ip4_addr_isbroadcast_u32+0x20>
-      (addr == IPADDR_ANY)) {
-    return 1;
- 800f3d0:	2301      	movs	r3, #1
- 800f3d2:	e02a      	b.n	800f42a <ip4_addr_isbroadcast_u32+0x76>
-    /* no broadcast support on this network interface? */
-  } else if ((netif->flags & NETIF_FLAG_BROADCAST) == 0) {
- 800f3d4:	683b      	ldr	r3, [r7, #0]
- 800f3d6:	f893 302d 	ldrb.w	r3, [r3, #45]	; 0x2d
- 800f3da:	f003 0302 	and.w	r3, r3, #2
- 800f3de:	2b00      	cmp	r3, #0
- 800f3e0:	d101      	bne.n	800f3e6 <ip4_addr_isbroadcast_u32+0x32>
-    /* the given address cannot be a broadcast address
-     * nor can we check against any broadcast addresses */
-    return 0;
- 800f3e2:	2300      	movs	r3, #0
- 800f3e4:	e021      	b.n	800f42a <ip4_addr_isbroadcast_u32+0x76>
-    /* address matches network interface address exactly? => no broadcast */
-  } else if (addr == ip4_addr_get_u32(netif_ip4_addr(netif))) {
- 800f3e6:	683b      	ldr	r3, [r7, #0]
- 800f3e8:	3304      	adds	r3, #4
- 800f3ea:	681b      	ldr	r3, [r3, #0]
- 800f3ec:	687a      	ldr	r2, [r7, #4]
- 800f3ee:	429a      	cmp	r2, r3
- 800f3f0:	d101      	bne.n	800f3f6 <ip4_addr_isbroadcast_u32+0x42>
-    return 0;
- 800f3f2:	2300      	movs	r3, #0
- 800f3f4:	e019      	b.n	800f42a <ip4_addr_isbroadcast_u32+0x76>
-    /*  on the same (sub) network... */
-  } else if (ip4_addr_netcmp(&ipaddr, netif_ip4_addr(netif), netif_ip4_netmask(netif))
- 800f3f6:	68fa      	ldr	r2, [r7, #12]
- 800f3f8:	683b      	ldr	r3, [r7, #0]
- 800f3fa:	3304      	adds	r3, #4
- 800f3fc:	681b      	ldr	r3, [r3, #0]
- 800f3fe:	405a      	eors	r2, r3
- 800f400:	683b      	ldr	r3, [r7, #0]
- 800f402:	3308      	adds	r3, #8
- 800f404:	681b      	ldr	r3, [r3, #0]
- 800f406:	4013      	ands	r3, r2
- 800f408:	2b00      	cmp	r3, #0
- 800f40a:	d10d      	bne.n	800f428 <ip4_addr_isbroadcast_u32+0x74>
-             /* ...and host identifier bits are all ones? =>... */
-             && ((addr & ~ip4_addr_get_u32(netif_ip4_netmask(netif))) ==
- 800f40c:	683b      	ldr	r3, [r7, #0]
- 800f40e:	3308      	adds	r3, #8
- 800f410:	681b      	ldr	r3, [r3, #0]
- 800f412:	43da      	mvns	r2, r3
- 800f414:	687b      	ldr	r3, [r7, #4]
- 800f416:	401a      	ands	r2, r3
-                 (IPADDR_BROADCAST & ~ip4_addr_get_u32(netif_ip4_netmask(netif))))) {
- 800f418:	683b      	ldr	r3, [r7, #0]
- 800f41a:	3308      	adds	r3, #8
- 800f41c:	681b      	ldr	r3, [r3, #0]
- 800f41e:	43db      	mvns	r3, r3
-             && ((addr & ~ip4_addr_get_u32(netif_ip4_netmask(netif))) ==
- 800f420:	429a      	cmp	r2, r3
- 800f422:	d101      	bne.n	800f428 <ip4_addr_isbroadcast_u32+0x74>
-    /* => network broadcast address */
-    return 1;
- 800f424:	2301      	movs	r3, #1
- 800f426:	e000      	b.n	800f42a <ip4_addr_isbroadcast_u32+0x76>
-  } else {
-    return 0;
- 800f428:	2300      	movs	r3, #0
-  }
-}
- 800f42a:	4618      	mov	r0, r3
- 800f42c:	3714      	adds	r7, #20
- 800f42e:	46bd      	mov	sp, r7
- 800f430:	f85d 7b04 	ldr.w	r7, [sp], #4
- 800f434:	4770      	bx	lr
-	...
-
-0800f438 <ip_reass_tmr>:
- *
- * Should be called every 1000 msec (defined by IP_TMR_INTERVAL).
- */
-void
-ip_reass_tmr(void)
-{
- 800f438:	b580      	push	{r7, lr}
- 800f43a:	b084      	sub	sp, #16
- 800f43c:	af00      	add	r7, sp, #0
-  struct ip_reassdata *r, *prev = NULL;
- 800f43e:	2300      	movs	r3, #0
- 800f440:	60bb      	str	r3, [r7, #8]
-
-  r = reassdatagrams;
- 800f442:	4b12      	ldr	r3, [pc, #72]	; (800f48c <ip_reass_tmr+0x54>)
- 800f444:	681b      	ldr	r3, [r3, #0]
- 800f446:	60fb      	str	r3, [r7, #12]
-  while (r != NULL) {
- 800f448:	e018      	b.n	800f47c <ip_reass_tmr+0x44>
-    /* Decrement the timer. Once it reaches 0,
-     * clean up the incomplete fragment assembly */
-    if (r->timer > 0) {
- 800f44a:	68fb      	ldr	r3, [r7, #12]
- 800f44c:	7fdb      	ldrb	r3, [r3, #31]
- 800f44e:	2b00      	cmp	r3, #0
- 800f450:	d00b      	beq.n	800f46a <ip_reass_tmr+0x32>
-      r->timer--;
- 800f452:	68fb      	ldr	r3, [r7, #12]
- 800f454:	7fdb      	ldrb	r3, [r3, #31]
- 800f456:	3b01      	subs	r3, #1
- 800f458:	b2da      	uxtb	r2, r3
- 800f45a:	68fb      	ldr	r3, [r7, #12]
- 800f45c:	77da      	strb	r2, [r3, #31]
-      LWIP_DEBUGF(IP_REASS_DEBUG, ("ip_reass_tmr: timer dec %"U16_F"\n", (u16_t)r->timer));
-      prev = r;
- 800f45e:	68fb      	ldr	r3, [r7, #12]
- 800f460:	60bb      	str	r3, [r7, #8]
-      r = r->next;
- 800f462:	68fb      	ldr	r3, [r7, #12]
- 800f464:	681b      	ldr	r3, [r3, #0]
- 800f466:	60fb      	str	r3, [r7, #12]
- 800f468:	e008      	b.n	800f47c <ip_reass_tmr+0x44>
-    } else {
-      /* reassembly timed out */
-      struct ip_reassdata *tmp;
-      LWIP_DEBUGF(IP_REASS_DEBUG, ("ip_reass_tmr: timer timed out\n"));
-      tmp = r;
- 800f46a:	68fb      	ldr	r3, [r7, #12]
- 800f46c:	607b      	str	r3, [r7, #4]
-      /* get the next pointer before freeing */
-      r = r->next;
- 800f46e:	68fb      	ldr	r3, [r7, #12]
- 800f470:	681b      	ldr	r3, [r3, #0]
- 800f472:	60fb      	str	r3, [r7, #12]
-      /* free the helper struct and all enqueued pbufs */
-      ip_reass_free_complete_datagram(tmp, prev);
- 800f474:	68b9      	ldr	r1, [r7, #8]
- 800f476:	6878      	ldr	r0, [r7, #4]
- 800f478:	f000 f80a 	bl	800f490 <ip_reass_free_complete_datagram>
-  while (r != NULL) {
- 800f47c:	68fb      	ldr	r3, [r7, #12]
- 800f47e:	2b00      	cmp	r3, #0
- 800f480:	d1e3      	bne.n	800f44a <ip_reass_tmr+0x12>
-    }
-  }
-}
- 800f482:	bf00      	nop
- 800f484:	bf00      	nop
- 800f486:	3710      	adds	r7, #16
- 800f488:	46bd      	mov	sp, r7
- 800f48a:	bd80      	pop	{r7, pc}
- 800f48c:	24007cc4 	.word	0x24007cc4
-
-0800f490 <ip_reass_free_complete_datagram>:
- * @param prev the previous datagram in the linked list
- * @return the number of pbufs freed
- */
-static int
-ip_reass_free_complete_datagram(struct ip_reassdata *ipr, struct ip_reassdata *prev)
-{
- 800f490:	b580      	push	{r7, lr}
- 800f492:	b088      	sub	sp, #32
- 800f494:	af00      	add	r7, sp, #0
- 800f496:	6078      	str	r0, [r7, #4]
- 800f498:	6039      	str	r1, [r7, #0]
-  u16_t pbufs_freed = 0;
- 800f49a:	2300      	movs	r3, #0
- 800f49c:	83fb      	strh	r3, [r7, #30]
-  u16_t clen;
-  struct pbuf *p;
-  struct ip_reass_helper *iprh;
-
-  LWIP_ASSERT("prev != ipr", prev != ipr);
- 800f49e:	683a      	ldr	r2, [r7, #0]
- 800f4a0:	687b      	ldr	r3, [r7, #4]
- 800f4a2:	429a      	cmp	r2, r3
- 800f4a4:	d105      	bne.n	800f4b2 <ip_reass_free_complete_datagram+0x22>
- 800f4a6:	4b45      	ldr	r3, [pc, #276]	; (800f5bc <ip_reass_free_complete_datagram+0x12c>)
- 800f4a8:	22ab      	movs	r2, #171	; 0xab
- 800f4aa:	4945      	ldr	r1, [pc, #276]	; (800f5c0 <ip_reass_free_complete_datagram+0x130>)
- 800f4ac:	4845      	ldr	r0, [pc, #276]	; (800f5c4 <ip_reass_free_complete_datagram+0x134>)
- 800f4ae:	f001 fb8b 	bl	8010bc8 <iprintf>
-  if (prev != NULL) {
- 800f4b2:	683b      	ldr	r3, [r7, #0]
- 800f4b4:	2b00      	cmp	r3, #0
- 800f4b6:	d00a      	beq.n	800f4ce <ip_reass_free_complete_datagram+0x3e>
-    LWIP_ASSERT("prev->next == ipr", prev->next == ipr);
- 800f4b8:	683b      	ldr	r3, [r7, #0]
- 800f4ba:	681b      	ldr	r3, [r3, #0]
- 800f4bc:	687a      	ldr	r2, [r7, #4]
- 800f4be:	429a      	cmp	r2, r3
- 800f4c0:	d005      	beq.n	800f4ce <ip_reass_free_complete_datagram+0x3e>
- 800f4c2:	4b3e      	ldr	r3, [pc, #248]	; (800f5bc <ip_reass_free_complete_datagram+0x12c>)
- 800f4c4:	22ad      	movs	r2, #173	; 0xad
- 800f4c6:	4940      	ldr	r1, [pc, #256]	; (800f5c8 <ip_reass_free_complete_datagram+0x138>)
- 800f4c8:	483e      	ldr	r0, [pc, #248]	; (800f5c4 <ip_reass_free_complete_datagram+0x134>)
- 800f4ca:	f001 fb7d 	bl	8010bc8 <iprintf>
-  }
-
-  MIB2_STATS_INC(mib2.ipreasmfails);
-#if LWIP_ICMP
-  iprh = (struct ip_reass_helper *)ipr->p->payload;
- 800f4ce:	687b      	ldr	r3, [r7, #4]
- 800f4d0:	685b      	ldr	r3, [r3, #4]
- 800f4d2:	685b      	ldr	r3, [r3, #4]
- 800f4d4:	617b      	str	r3, [r7, #20]
-  if (iprh->start == 0) {
- 800f4d6:	697b      	ldr	r3, [r7, #20]
- 800f4d8:	889b      	ldrh	r3, [r3, #4]
- 800f4da:	b29b      	uxth	r3, r3
- 800f4dc:	2b00      	cmp	r3, #0
- 800f4de:	d12a      	bne.n	800f536 <ip_reass_free_complete_datagram+0xa6>
-    /* The first fragment was received, send ICMP time exceeded. */
-    /* First, de-queue the first pbuf from r->p. */
-    p = ipr->p;
- 800f4e0:	687b      	ldr	r3, [r7, #4]
- 800f4e2:	685b      	ldr	r3, [r3, #4]
- 800f4e4:	61bb      	str	r3, [r7, #24]
-    ipr->p = iprh->next_pbuf;
- 800f4e6:	697b      	ldr	r3, [r7, #20]
- 800f4e8:	681a      	ldr	r2, [r3, #0]
- 800f4ea:	687b      	ldr	r3, [r7, #4]
- 800f4ec:	605a      	str	r2, [r3, #4]
-    /* Then, copy the original header into it. */
-    SMEMCPY(p->payload, &ipr->iphdr, IP_HLEN);
- 800f4ee:	69bb      	ldr	r3, [r7, #24]
- 800f4f0:	6858      	ldr	r0, [r3, #4]
- 800f4f2:	687b      	ldr	r3, [r7, #4]
- 800f4f4:	3308      	adds	r3, #8
- 800f4f6:	2214      	movs	r2, #20
- 800f4f8:	4619      	mov	r1, r3
- 800f4fa:	f001 fd46 	bl	8010f8a <memcpy>
-    icmp_time_exceeded(p, ICMP_TE_FRAG);
- 800f4fe:	2101      	movs	r1, #1
- 800f500:	69b8      	ldr	r0, [r7, #24]
- 800f502:	f7ff fbfd 	bl	800ed00 <icmp_time_exceeded>
-    clen = pbuf_clen(p);
- 800f506:	69b8      	ldr	r0, [r7, #24]
- 800f508:	f7f7 fdec 	bl	80070e4 <pbuf_clen>
- 800f50c:	4603      	mov	r3, r0
- 800f50e:	827b      	strh	r3, [r7, #18]
-    LWIP_ASSERT("pbufs_freed + clen <= 0xffff", pbufs_freed + clen <= 0xffff);
- 800f510:	8bfa      	ldrh	r2, [r7, #30]
- 800f512:	8a7b      	ldrh	r3, [r7, #18]
- 800f514:	4413      	add	r3, r2
- 800f516:	f5b3 3f80 	cmp.w	r3, #65536	; 0x10000
- 800f51a:	db05      	blt.n	800f528 <ip_reass_free_complete_datagram+0x98>
- 800f51c:	4b27      	ldr	r3, [pc, #156]	; (800f5bc <ip_reass_free_complete_datagram+0x12c>)
- 800f51e:	22bc      	movs	r2, #188	; 0xbc
- 800f520:	492a      	ldr	r1, [pc, #168]	; (800f5cc <ip_reass_free_complete_datagram+0x13c>)
- 800f522:	4828      	ldr	r0, [pc, #160]	; (800f5c4 <ip_reass_free_complete_datagram+0x134>)
- 800f524:	f001 fb50 	bl	8010bc8 <iprintf>
-    pbufs_freed = (u16_t)(pbufs_freed + clen);
- 800f528:	8bfa      	ldrh	r2, [r7, #30]
- 800f52a:	8a7b      	ldrh	r3, [r7, #18]
- 800f52c:	4413      	add	r3, r2
- 800f52e:	83fb      	strh	r3, [r7, #30]
-    pbuf_free(p);
- 800f530:	69b8      	ldr	r0, [r7, #24]
- 800f532:	f7f7 fd4f 	bl	8006fd4 <pbuf_free>
-  }
-#endif /* LWIP_ICMP */
-
-  /* First, free all received pbufs.  The individual pbufs need to be released
-     separately as they have not yet been chained */
-  p = ipr->p;
- 800f536:	687b      	ldr	r3, [r7, #4]
- 800f538:	685b      	ldr	r3, [r3, #4]
- 800f53a:	61bb      	str	r3, [r7, #24]
-  while (p != NULL) {
- 800f53c:	e01f      	b.n	800f57e <ip_reass_free_complete_datagram+0xee>
-    struct pbuf *pcur;
-    iprh = (struct ip_reass_helper *)p->payload;
- 800f53e:	69bb      	ldr	r3, [r7, #24]
- 800f540:	685b      	ldr	r3, [r3, #4]
- 800f542:	617b      	str	r3, [r7, #20]
-    pcur = p;
- 800f544:	69bb      	ldr	r3, [r7, #24]
- 800f546:	60fb      	str	r3, [r7, #12]
-    /* get the next pointer before freeing */
-    p = iprh->next_pbuf;
- 800f548:	697b      	ldr	r3, [r7, #20]
- 800f54a:	681b      	ldr	r3, [r3, #0]
- 800f54c:	61bb      	str	r3, [r7, #24]
-    clen = pbuf_clen(pcur);
- 800f54e:	68f8      	ldr	r0, [r7, #12]
- 800f550:	f7f7 fdc8 	bl	80070e4 <pbuf_clen>
- 800f554:	4603      	mov	r3, r0
- 800f556:	827b      	strh	r3, [r7, #18]
-    LWIP_ASSERT("pbufs_freed + clen <= 0xffff", pbufs_freed + clen <= 0xffff);
- 800f558:	8bfa      	ldrh	r2, [r7, #30]
- 800f55a:	8a7b      	ldrh	r3, [r7, #18]
- 800f55c:	4413      	add	r3, r2
- 800f55e:	f5b3 3f80 	cmp.w	r3, #65536	; 0x10000
- 800f562:	db05      	blt.n	800f570 <ip_reass_free_complete_datagram+0xe0>
- 800f564:	4b15      	ldr	r3, [pc, #84]	; (800f5bc <ip_reass_free_complete_datagram+0x12c>)
- 800f566:	22cc      	movs	r2, #204	; 0xcc
- 800f568:	4918      	ldr	r1, [pc, #96]	; (800f5cc <ip_reass_free_complete_datagram+0x13c>)
- 800f56a:	4816      	ldr	r0, [pc, #88]	; (800f5c4 <ip_reass_free_complete_datagram+0x134>)
- 800f56c:	f001 fb2c 	bl	8010bc8 <iprintf>
-    pbufs_freed = (u16_t)(pbufs_freed + clen);
- 800f570:	8bfa      	ldrh	r2, [r7, #30]
- 800f572:	8a7b      	ldrh	r3, [r7, #18]
- 800f574:	4413      	add	r3, r2
- 800f576:	83fb      	strh	r3, [r7, #30]
-    pbuf_free(pcur);
- 800f578:	68f8      	ldr	r0, [r7, #12]
- 800f57a:	f7f7 fd2b 	bl	8006fd4 <pbuf_free>
-  while (p != NULL) {
- 800f57e:	69bb      	ldr	r3, [r7, #24]
- 800f580:	2b00      	cmp	r3, #0
- 800f582:	d1dc      	bne.n	800f53e <ip_reass_free_complete_datagram+0xae>
-  }
-  /* Then, unchain the struct ip_reassdata from the list and free it. */
-  ip_reass_dequeue_datagram(ipr, prev);
- 800f584:	6839      	ldr	r1, [r7, #0]
- 800f586:	6878      	ldr	r0, [r7, #4]
- 800f588:	f000 f8c2 	bl	800f710 <ip_reass_dequeue_datagram>
-  LWIP_ASSERT("ip_reass_pbufcount >= pbufs_freed", ip_reass_pbufcount >= pbufs_freed);
- 800f58c:	4b10      	ldr	r3, [pc, #64]	; (800f5d0 <ip_reass_free_complete_datagram+0x140>)
- 800f58e:	881b      	ldrh	r3, [r3, #0]
- 800f590:	8bfa      	ldrh	r2, [r7, #30]
- 800f592:	429a      	cmp	r2, r3
- 800f594:	d905      	bls.n	800f5a2 <ip_reass_free_complete_datagram+0x112>
- 800f596:	4b09      	ldr	r3, [pc, #36]	; (800f5bc <ip_reass_free_complete_datagram+0x12c>)
- 800f598:	22d2      	movs	r2, #210	; 0xd2
- 800f59a:	490e      	ldr	r1, [pc, #56]	; (800f5d4 <ip_reass_free_complete_datagram+0x144>)
- 800f59c:	4809      	ldr	r0, [pc, #36]	; (800f5c4 <ip_reass_free_complete_datagram+0x134>)
- 800f59e:	f001 fb13 	bl	8010bc8 <iprintf>
-  ip_reass_pbufcount = (u16_t)(ip_reass_pbufcount - pbufs_freed);
- 800f5a2:	4b0b      	ldr	r3, [pc, #44]	; (800f5d0 <ip_reass_free_complete_datagram+0x140>)
- 800f5a4:	881a      	ldrh	r2, [r3, #0]
- 800f5a6:	8bfb      	ldrh	r3, [r7, #30]
- 800f5a8:	1ad3      	subs	r3, r2, r3
- 800f5aa:	b29a      	uxth	r2, r3
- 800f5ac:	4b08      	ldr	r3, [pc, #32]	; (800f5d0 <ip_reass_free_complete_datagram+0x140>)
- 800f5ae:	801a      	strh	r2, [r3, #0]
-
-  return pbufs_freed;
- 800f5b0:	8bfb      	ldrh	r3, [r7, #30]
-}
- 800f5b2:	4618      	mov	r0, r3
- 800f5b4:	3720      	adds	r7, #32
- 800f5b6:	46bd      	mov	sp, r7
- 800f5b8:	bd80      	pop	{r7, pc}
- 800f5ba:	bf00      	nop
- 800f5bc:	080149bc 	.word	0x080149bc
- 800f5c0:	080149f8 	.word	0x080149f8
- 800f5c4:	08014a04 	.word	0x08014a04
- 800f5c8:	08014a2c 	.word	0x08014a2c
- 800f5cc:	08014a40 	.word	0x08014a40
- 800f5d0:	24007cc8 	.word	0x24007cc8
- 800f5d4:	08014a60 	.word	0x08014a60
-
-0800f5d8 <ip_reass_remove_oldest_datagram>:
- *        (used for freeing other datagrams if not enough space)
- * @return the number of pbufs freed
- */
-static int
-ip_reass_remove_oldest_datagram(struct ip_hdr *fraghdr, int pbufs_needed)
-{
- 800f5d8:	b580      	push	{r7, lr}
- 800f5da:	b08a      	sub	sp, #40	; 0x28
- 800f5dc:	af00      	add	r7, sp, #0
- 800f5de:	6078      	str	r0, [r7, #4]
- 800f5e0:	6039      	str	r1, [r7, #0]
-  /* @todo Can't we simply remove the last datagram in the
-   *       linked list behind reassdatagrams?
-   */
-  struct ip_reassdata *r, *oldest, *prev, *oldest_prev;
-  int pbufs_freed = 0, pbufs_freed_current;
- 800f5e2:	2300      	movs	r3, #0
- 800f5e4:	617b      	str	r3, [r7, #20]
-  int other_datagrams;
-
-  /* Free datagrams until being allowed to enqueue 'pbufs_needed' pbufs,
-   * but don't free the datagram that 'fraghdr' belongs to! */
-  do {
-    oldest = NULL;
- 800f5e6:	2300      	movs	r3, #0
- 800f5e8:	623b      	str	r3, [r7, #32]
-    prev = NULL;
- 800f5ea:	2300      	movs	r3, #0
- 800f5ec:	61fb      	str	r3, [r7, #28]
-    oldest_prev = NULL;
- 800f5ee:	2300      	movs	r3, #0
- 800f5f0:	61bb      	str	r3, [r7, #24]
-    other_datagrams = 0;
- 800f5f2:	2300      	movs	r3, #0
- 800f5f4:	613b      	str	r3, [r7, #16]
-    r = reassdatagrams;
- 800f5f6:	4b28      	ldr	r3, [pc, #160]	; (800f698 <ip_reass_remove_oldest_datagram+0xc0>)
- 800f5f8:	681b      	ldr	r3, [r3, #0]
- 800f5fa:	627b      	str	r3, [r7, #36]	; 0x24
-    while (r != NULL) {
- 800f5fc:	e030      	b.n	800f660 <ip_reass_remove_oldest_datagram+0x88>
-      if (!IP_ADDRESSES_AND_ID_MATCH(&r->iphdr, fraghdr)) {
- 800f5fe:	6a7b      	ldr	r3, [r7, #36]	; 0x24
- 800f600:	695a      	ldr	r2, [r3, #20]
- 800f602:	687b      	ldr	r3, [r7, #4]
- 800f604:	68db      	ldr	r3, [r3, #12]
- 800f606:	429a      	cmp	r2, r3
- 800f608:	d10c      	bne.n	800f624 <ip_reass_remove_oldest_datagram+0x4c>
- 800f60a:	6a7b      	ldr	r3, [r7, #36]	; 0x24
- 800f60c:	699a      	ldr	r2, [r3, #24]
- 800f60e:	687b      	ldr	r3, [r7, #4]
- 800f610:	691b      	ldr	r3, [r3, #16]
- 800f612:	429a      	cmp	r2, r3
- 800f614:	d106      	bne.n	800f624 <ip_reass_remove_oldest_datagram+0x4c>
- 800f616:	6a7b      	ldr	r3, [r7, #36]	; 0x24
- 800f618:	899a      	ldrh	r2, [r3, #12]
- 800f61a:	687b      	ldr	r3, [r7, #4]
- 800f61c:	889b      	ldrh	r3, [r3, #4]
- 800f61e:	b29b      	uxth	r3, r3
- 800f620:	429a      	cmp	r2, r3
- 800f622:	d014      	beq.n	800f64e <ip_reass_remove_oldest_datagram+0x76>
-        /* Not the same datagram as fraghdr */
-        other_datagrams++;
- 800f624:	693b      	ldr	r3, [r7, #16]
- 800f626:	3301      	adds	r3, #1
- 800f628:	613b      	str	r3, [r7, #16]
-        if (oldest == NULL) {
- 800f62a:	6a3b      	ldr	r3, [r7, #32]
- 800f62c:	2b00      	cmp	r3, #0
- 800f62e:	d104      	bne.n	800f63a <ip_reass_remove_oldest_datagram+0x62>
-          oldest = r;
- 800f630:	6a7b      	ldr	r3, [r7, #36]	; 0x24
- 800f632:	623b      	str	r3, [r7, #32]
-          oldest_prev = prev;
- 800f634:	69fb      	ldr	r3, [r7, #28]
- 800f636:	61bb      	str	r3, [r7, #24]
- 800f638:	e009      	b.n	800f64e <ip_reass_remove_oldest_datagram+0x76>
-        } else if (r->timer <= oldest->timer) {
- 800f63a:	6a7b      	ldr	r3, [r7, #36]	; 0x24
- 800f63c:	7fda      	ldrb	r2, [r3, #31]
- 800f63e:	6a3b      	ldr	r3, [r7, #32]
- 800f640:	7fdb      	ldrb	r3, [r3, #31]
- 800f642:	429a      	cmp	r2, r3
- 800f644:	d803      	bhi.n	800f64e <ip_reass_remove_oldest_datagram+0x76>
-          /* older than the previous oldest */
-          oldest = r;
- 800f646:	6a7b      	ldr	r3, [r7, #36]	; 0x24
- 800f648:	623b      	str	r3, [r7, #32]
-          oldest_prev = prev;
- 800f64a:	69fb      	ldr	r3, [r7, #28]
- 800f64c:	61bb      	str	r3, [r7, #24]
-        }
-      }
-      if (r->next != NULL) {
- 800f64e:	6a7b      	ldr	r3, [r7, #36]	; 0x24
- 800f650:	681b      	ldr	r3, [r3, #0]
- 800f652:	2b00      	cmp	r3, #0
- 800f654:	d001      	beq.n	800f65a <ip_reass_remove_oldest_datagram+0x82>
-        prev = r;
- 800f656:	6a7b      	ldr	r3, [r7, #36]	; 0x24
- 800f658:	61fb      	str	r3, [r7, #28]
-      }
-      r = r->next;
- 800f65a:	6a7b      	ldr	r3, [r7, #36]	; 0x24
- 800f65c:	681b      	ldr	r3, [r3, #0]
- 800f65e:	627b      	str	r3, [r7, #36]	; 0x24
-    while (r != NULL) {
- 800f660:	6a7b      	ldr	r3, [r7, #36]	; 0x24
- 800f662:	2b00      	cmp	r3, #0
- 800f664:	d1cb      	bne.n	800f5fe <ip_reass_remove_oldest_datagram+0x26>
-    }
-    if (oldest != NULL) {
- 800f666:	6a3b      	ldr	r3, [r7, #32]
- 800f668:	2b00      	cmp	r3, #0
- 800f66a:	d008      	beq.n	800f67e <ip_reass_remove_oldest_datagram+0xa6>
-      pbufs_freed_current = ip_reass_free_complete_datagram(oldest, oldest_prev);
- 800f66c:	69b9      	ldr	r1, [r7, #24]
- 800f66e:	6a38      	ldr	r0, [r7, #32]
- 800f670:	f7ff ff0e 	bl	800f490 <ip_reass_free_complete_datagram>
- 800f674:	60f8      	str	r0, [r7, #12]
-      pbufs_freed += pbufs_freed_current;
- 800f676:	697a      	ldr	r2, [r7, #20]
- 800f678:	68fb      	ldr	r3, [r7, #12]
- 800f67a:	4413      	add	r3, r2
- 800f67c:	617b      	str	r3, [r7, #20]
-    }
-  } while ((pbufs_freed < pbufs_needed) && (other_datagrams > 1));
- 800f67e:	697a      	ldr	r2, [r7, #20]
- 800f680:	683b      	ldr	r3, [r7, #0]
- 800f682:	429a      	cmp	r2, r3
- 800f684:	da02      	bge.n	800f68c <ip_reass_remove_oldest_datagram+0xb4>
- 800f686:	693b      	ldr	r3, [r7, #16]
- 800f688:	2b01      	cmp	r3, #1
- 800f68a:	dcac      	bgt.n	800f5e6 <ip_reass_remove_oldest_datagram+0xe>
-  return pbufs_freed;
- 800f68c:	697b      	ldr	r3, [r7, #20]
-}
- 800f68e:	4618      	mov	r0, r3
- 800f690:	3728      	adds	r7, #40	; 0x28
- 800f692:	46bd      	mov	sp, r7
- 800f694:	bd80      	pop	{r7, pc}
- 800f696:	bf00      	nop
- 800f698:	24007cc4 	.word	0x24007cc4
-
-0800f69c <ip_reass_enqueue_new_datagram>:
- * @param clen number of pbufs needed to enqueue (used for freeing other datagrams if not enough space)
- * @return A pointer to the queue location into which the fragment was enqueued
- */
-static struct ip_reassdata *
-ip_reass_enqueue_new_datagram(struct ip_hdr *fraghdr, int clen)
-{
- 800f69c:	b580      	push	{r7, lr}
- 800f69e:	b084      	sub	sp, #16
- 800f6a0:	af00      	add	r7, sp, #0
- 800f6a2:	6078      	str	r0, [r7, #4]
- 800f6a4:	6039      	str	r1, [r7, #0]
-#if ! IP_REASS_FREE_OLDEST
-  LWIP_UNUSED_ARG(clen);
-#endif
-
-  /* No matching previous fragment found, allocate a new reassdata struct */
-  ipr = (struct ip_reassdata *)memp_malloc(MEMP_REASSDATA);
- 800f6a6:	2004      	movs	r0, #4
- 800f6a8:	f7f6 fcb8 	bl	800601c <memp_malloc>
- 800f6ac:	60f8      	str	r0, [r7, #12]
-  if (ipr == NULL) {
- 800f6ae:	68fb      	ldr	r3, [r7, #12]
- 800f6b0:	2b00      	cmp	r3, #0
- 800f6b2:	d110      	bne.n	800f6d6 <ip_reass_enqueue_new_datagram+0x3a>
-#if IP_REASS_FREE_OLDEST
-    if (ip_reass_remove_oldest_datagram(fraghdr, clen) >= clen) {
- 800f6b4:	6839      	ldr	r1, [r7, #0]
- 800f6b6:	6878      	ldr	r0, [r7, #4]
- 800f6b8:	f7ff ff8e 	bl	800f5d8 <ip_reass_remove_oldest_datagram>
- 800f6bc:	4602      	mov	r2, r0
- 800f6be:	683b      	ldr	r3, [r7, #0]
- 800f6c0:	4293      	cmp	r3, r2
- 800f6c2:	dc03      	bgt.n	800f6cc <ip_reass_enqueue_new_datagram+0x30>
-      ipr = (struct ip_reassdata *)memp_malloc(MEMP_REASSDATA);
- 800f6c4:	2004      	movs	r0, #4
- 800f6c6:	f7f6 fca9 	bl	800601c <memp_malloc>
- 800f6ca:	60f8      	str	r0, [r7, #12]
-    }
-    if (ipr == NULL)
- 800f6cc:	68fb      	ldr	r3, [r7, #12]
- 800f6ce:	2b00      	cmp	r3, #0
- 800f6d0:	d101      	bne.n	800f6d6 <ip_reass_enqueue_new_datagram+0x3a>
-#endif /* IP_REASS_FREE_OLDEST */
-    {
-      IPFRAG_STATS_INC(ip_frag.memerr);
-      LWIP_DEBUGF(IP_REASS_DEBUG, ("Failed to alloc reassdata struct\n"));
-      return NULL;
- 800f6d2:	2300      	movs	r3, #0
- 800f6d4:	e016      	b.n	800f704 <ip_reass_enqueue_new_datagram+0x68>
-    }
-  }
-  memset(ipr, 0, sizeof(struct ip_reassdata));
- 800f6d6:	2220      	movs	r2, #32
- 800f6d8:	2100      	movs	r1, #0
- 800f6da:	68f8      	ldr	r0, [r7, #12]
- 800f6dc:	f001 fbd2 	bl	8010e84 <memset>
-  ipr->timer = IP_REASS_MAXAGE;
- 800f6e0:	68fb      	ldr	r3, [r7, #12]
- 800f6e2:	220f      	movs	r2, #15
- 800f6e4:	77da      	strb	r2, [r3, #31]
-
-  /* enqueue the new structure to the front of the list */
-  ipr->next = reassdatagrams;
- 800f6e6:	4b09      	ldr	r3, [pc, #36]	; (800f70c <ip_reass_enqueue_new_datagram+0x70>)
- 800f6e8:	681a      	ldr	r2, [r3, #0]
- 800f6ea:	68fb      	ldr	r3, [r7, #12]
- 800f6ec:	601a      	str	r2, [r3, #0]
-  reassdatagrams = ipr;
- 800f6ee:	4a07      	ldr	r2, [pc, #28]	; (800f70c <ip_reass_enqueue_new_datagram+0x70>)
- 800f6f0:	68fb      	ldr	r3, [r7, #12]
- 800f6f2:	6013      	str	r3, [r2, #0]
-  /* copy the ip header for later tests and input */
-  /* @todo: no ip options supported? */
-  SMEMCPY(&(ipr->iphdr), fraghdr, IP_HLEN);
- 800f6f4:	68fb      	ldr	r3, [r7, #12]
- 800f6f6:	3308      	adds	r3, #8
- 800f6f8:	2214      	movs	r2, #20
- 800f6fa:	6879      	ldr	r1, [r7, #4]
- 800f6fc:	4618      	mov	r0, r3
- 800f6fe:	f001 fc44 	bl	8010f8a <memcpy>
-  return ipr;
- 800f702:	68fb      	ldr	r3, [r7, #12]
-}
- 800f704:	4618      	mov	r0, r3
- 800f706:	3710      	adds	r7, #16
- 800f708:	46bd      	mov	sp, r7
- 800f70a:	bd80      	pop	{r7, pc}
- 800f70c:	24007cc4 	.word	0x24007cc4
-
-0800f710 <ip_reass_dequeue_datagram>:
- * Dequeues a datagram from the datagram queue. Doesn't deallocate the pbufs.
- * @param ipr points to the queue entry to dequeue
- */
-static void
-ip_reass_dequeue_datagram(struct ip_reassdata *ipr, struct ip_reassdata *prev)
-{
- 800f710:	b580      	push	{r7, lr}
- 800f712:	b082      	sub	sp, #8
- 800f714:	af00      	add	r7, sp, #0
- 800f716:	6078      	str	r0, [r7, #4]
- 800f718:	6039      	str	r1, [r7, #0]
-  /* dequeue the reass struct  */
-  if (reassdatagrams == ipr) {
- 800f71a:	4b10      	ldr	r3, [pc, #64]	; (800f75c <ip_reass_dequeue_datagram+0x4c>)
- 800f71c:	681b      	ldr	r3, [r3, #0]
- 800f71e:	687a      	ldr	r2, [r7, #4]
- 800f720:	429a      	cmp	r2, r3
- 800f722:	d104      	bne.n	800f72e <ip_reass_dequeue_datagram+0x1e>
-    /* it was the first in the list */
-    reassdatagrams = ipr->next;
- 800f724:	687b      	ldr	r3, [r7, #4]
- 800f726:	681b      	ldr	r3, [r3, #0]
- 800f728:	4a0c      	ldr	r2, [pc, #48]	; (800f75c <ip_reass_dequeue_datagram+0x4c>)
- 800f72a:	6013      	str	r3, [r2, #0]
- 800f72c:	e00d      	b.n	800f74a <ip_reass_dequeue_datagram+0x3a>
-  } else {
-    /* it wasn't the first, so it must have a valid 'prev' */
-    LWIP_ASSERT("sanity check linked list", prev != NULL);
- 800f72e:	683b      	ldr	r3, [r7, #0]
- 800f730:	2b00      	cmp	r3, #0
- 800f732:	d106      	bne.n	800f742 <ip_reass_dequeue_datagram+0x32>
- 800f734:	4b0a      	ldr	r3, [pc, #40]	; (800f760 <ip_reass_dequeue_datagram+0x50>)
- 800f736:	f240 1245 	movw	r2, #325	; 0x145
- 800f73a:	490a      	ldr	r1, [pc, #40]	; (800f764 <ip_reass_dequeue_datagram+0x54>)
- 800f73c:	480a      	ldr	r0, [pc, #40]	; (800f768 <ip_reass_dequeue_datagram+0x58>)
- 800f73e:	f001 fa43 	bl	8010bc8 <iprintf>
-    prev->next = ipr->next;
- 800f742:	687b      	ldr	r3, [r7, #4]
- 800f744:	681a      	ldr	r2, [r3, #0]
- 800f746:	683b      	ldr	r3, [r7, #0]
- 800f748:	601a      	str	r2, [r3, #0]
-  }
-
-  /* now we can free the ip_reassdata struct */
-  memp_free(MEMP_REASSDATA, ipr);
- 800f74a:	6879      	ldr	r1, [r7, #4]
- 800f74c:	2004      	movs	r0, #4
- 800f74e:	f7f6 fcd5 	bl	80060fc <memp_free>
-}
- 800f752:	bf00      	nop
- 800f754:	3708      	adds	r7, #8
- 800f756:	46bd      	mov	sp, r7
- 800f758:	bd80      	pop	{r7, pc}
- 800f75a:	bf00      	nop
- 800f75c:	24007cc4 	.word	0x24007cc4
- 800f760:	080149bc 	.word	0x080149bc
- 800f764:	08014a84 	.word	0x08014a84
- 800f768:	08014a04 	.word	0x08014a04
-
-0800f76c <ip_reass_chain_frag_into_datagram_and_validate>:
- * @param is_last is 1 if this pbuf has MF==0 (ipr->flags not updated yet)
- * @return see IP_REASS_VALIDATE_* defines
- */
-static int
-ip_reass_chain_frag_into_datagram_and_validate(struct ip_reassdata *ipr, struct pbuf *new_p, int is_last)
-{
- 800f76c:	b580      	push	{r7, lr}
- 800f76e:	b08c      	sub	sp, #48	; 0x30
- 800f770:	af00      	add	r7, sp, #0
- 800f772:	60f8      	str	r0, [r7, #12]
- 800f774:	60b9      	str	r1, [r7, #8]
- 800f776:	607a      	str	r2, [r7, #4]
-  struct ip_reass_helper *iprh, *iprh_tmp, *iprh_prev = NULL;
- 800f778:	2300      	movs	r3, #0
- 800f77a:	62bb      	str	r3, [r7, #40]	; 0x28
-  struct pbuf *q;
-  u16_t offset, len;
-  u8_t hlen;
-  struct ip_hdr *fraghdr;
-  int valid = 1;
- 800f77c:	2301      	movs	r3, #1
- 800f77e:	623b      	str	r3, [r7, #32]
-
-  /* Extract length and fragment offset from current fragment */
-  fraghdr = (struct ip_hdr *)new_p->payload;
- 800f780:	68bb      	ldr	r3, [r7, #8]
- 800f782:	685b      	ldr	r3, [r3, #4]
- 800f784:	61fb      	str	r3, [r7, #28]
-  len = lwip_ntohs(IPH_LEN(fraghdr));
- 800f786:	69fb      	ldr	r3, [r7, #28]
- 800f788:	885b      	ldrh	r3, [r3, #2]
- 800f78a:	b29b      	uxth	r3, r3
- 800f78c:	4618      	mov	r0, r3
- 800f78e:	f7f5 fedd 	bl	800554c <lwip_htons>
- 800f792:	4603      	mov	r3, r0
- 800f794:	837b      	strh	r3, [r7, #26]
-  hlen = IPH_HL_BYTES(fraghdr);
- 800f796:	69fb      	ldr	r3, [r7, #28]
- 800f798:	781b      	ldrb	r3, [r3, #0]
- 800f79a:	f003 030f 	and.w	r3, r3, #15
- 800f79e:	b2db      	uxtb	r3, r3
- 800f7a0:	009b      	lsls	r3, r3, #2
- 800f7a2:	767b      	strb	r3, [r7, #25]
-  if (hlen > len) {
- 800f7a4:	7e7b      	ldrb	r3, [r7, #25]
- 800f7a6:	b29b      	uxth	r3, r3
- 800f7a8:	8b7a      	ldrh	r2, [r7, #26]
- 800f7aa:	429a      	cmp	r2, r3
- 800f7ac:	d202      	bcs.n	800f7b4 <ip_reass_chain_frag_into_datagram_and_validate+0x48>
-    /* invalid datagram */
-    return IP_REASS_VALIDATE_PBUF_DROPPED;
- 800f7ae:	f04f 33ff 	mov.w	r3, #4294967295
- 800f7b2:	e135      	b.n	800fa20 <ip_reass_chain_frag_into_datagram_and_validate+0x2b4>
-  }
-  len = (u16_t)(len - hlen);
- 800f7b4:	7e7b      	ldrb	r3, [r7, #25]
- 800f7b6:	b29b      	uxth	r3, r3
- 800f7b8:	8b7a      	ldrh	r2, [r7, #26]
- 800f7ba:	1ad3      	subs	r3, r2, r3
- 800f7bc:	837b      	strh	r3, [r7, #26]
-  offset = IPH_OFFSET_BYTES(fraghdr);
- 800f7be:	69fb      	ldr	r3, [r7, #28]
- 800f7c0:	88db      	ldrh	r3, [r3, #6]
- 800f7c2:	b29b      	uxth	r3, r3
- 800f7c4:	4618      	mov	r0, r3
- 800f7c6:	f7f5 fec1 	bl	800554c <lwip_htons>
- 800f7ca:	4603      	mov	r3, r0
- 800f7cc:	f3c3 030c 	ubfx	r3, r3, #0, #13
- 800f7d0:	b29b      	uxth	r3, r3
- 800f7d2:	00db      	lsls	r3, r3, #3
- 800f7d4:	82fb      	strh	r3, [r7, #22]
-  /* overwrite the fragment's ip header from the pbuf with our helper struct,
-   * and setup the embedded helper structure. */
-  /* make sure the struct ip_reass_helper fits into the IP header */
-  LWIP_ASSERT("sizeof(struct ip_reass_helper) <= IP_HLEN",
-              sizeof(struct ip_reass_helper) <= IP_HLEN);
-  iprh = (struct ip_reass_helper *)new_p->payload;
- 800f7d6:	68bb      	ldr	r3, [r7, #8]
- 800f7d8:	685b      	ldr	r3, [r3, #4]
- 800f7da:	62fb      	str	r3, [r7, #44]	; 0x2c
-  iprh->next_pbuf = NULL;
- 800f7dc:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 800f7de:	2200      	movs	r2, #0
- 800f7e0:	701a      	strb	r2, [r3, #0]
- 800f7e2:	2200      	movs	r2, #0
- 800f7e4:	705a      	strb	r2, [r3, #1]
- 800f7e6:	2200      	movs	r2, #0
- 800f7e8:	709a      	strb	r2, [r3, #2]
- 800f7ea:	2200      	movs	r2, #0
- 800f7ec:	70da      	strb	r2, [r3, #3]
-  iprh->start = offset;
- 800f7ee:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 800f7f0:	8afa      	ldrh	r2, [r7, #22]
- 800f7f2:	809a      	strh	r2, [r3, #4]
-  iprh->end = (u16_t)(offset + len);
- 800f7f4:	8afa      	ldrh	r2, [r7, #22]
- 800f7f6:	8b7b      	ldrh	r3, [r7, #26]
- 800f7f8:	4413      	add	r3, r2
- 800f7fa:	b29a      	uxth	r2, r3
- 800f7fc:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 800f7fe:	80da      	strh	r2, [r3, #6]
-  if (iprh->end < offset) {
- 800f800:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 800f802:	88db      	ldrh	r3, [r3, #6]
- 800f804:	b29b      	uxth	r3, r3
- 800f806:	8afa      	ldrh	r2, [r7, #22]
- 800f808:	429a      	cmp	r2, r3
- 800f80a:	d902      	bls.n	800f812 <ip_reass_chain_frag_into_datagram_and_validate+0xa6>
-    /* u16_t overflow, cannot handle this */
-    return IP_REASS_VALIDATE_PBUF_DROPPED;
- 800f80c:	f04f 33ff 	mov.w	r3, #4294967295
- 800f810:	e106      	b.n	800fa20 <ip_reass_chain_frag_into_datagram_and_validate+0x2b4>
-  }
-
-  /* Iterate through until we either get to the end of the list (append),
-   * or we find one with a larger offset (insert). */
-  for (q = ipr->p; q != NULL;) {
- 800f812:	68fb      	ldr	r3, [r7, #12]
- 800f814:	685b      	ldr	r3, [r3, #4]
- 800f816:	627b      	str	r3, [r7, #36]	; 0x24
- 800f818:	e068      	b.n	800f8ec <ip_reass_chain_frag_into_datagram_and_validate+0x180>
-    iprh_tmp = (struct ip_reass_helper *)q->payload;
- 800f81a:	6a7b      	ldr	r3, [r7, #36]	; 0x24
- 800f81c:	685b      	ldr	r3, [r3, #4]
- 800f81e:	613b      	str	r3, [r7, #16]
-    if (iprh->start < iprh_tmp->start) {
- 800f820:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 800f822:	889b      	ldrh	r3, [r3, #4]
- 800f824:	b29a      	uxth	r2, r3
- 800f826:	693b      	ldr	r3, [r7, #16]
- 800f828:	889b      	ldrh	r3, [r3, #4]
- 800f82a:	b29b      	uxth	r3, r3
- 800f82c:	429a      	cmp	r2, r3
- 800f82e:	d235      	bcs.n	800f89c <ip_reass_chain_frag_into_datagram_and_validate+0x130>
-      /* the new pbuf should be inserted before this */
-      iprh->next_pbuf = q;
- 800f830:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 800f832:	6a7a      	ldr	r2, [r7, #36]	; 0x24
- 800f834:	601a      	str	r2, [r3, #0]
-      if (iprh_prev != NULL) {
- 800f836:	6abb      	ldr	r3, [r7, #40]	; 0x28
- 800f838:	2b00      	cmp	r3, #0
- 800f83a:	d020      	beq.n	800f87e <ip_reass_chain_frag_into_datagram_and_validate+0x112>
-        /* not the fragment with the lowest offset */
-#if IP_REASS_CHECK_OVERLAP
-        if ((iprh->start < iprh_prev->end) || (iprh->end > iprh_tmp->start)) {
- 800f83c:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 800f83e:	889b      	ldrh	r3, [r3, #4]
- 800f840:	b29a      	uxth	r2, r3
- 800f842:	6abb      	ldr	r3, [r7, #40]	; 0x28
- 800f844:	88db      	ldrh	r3, [r3, #6]
- 800f846:	b29b      	uxth	r3, r3
- 800f848:	429a      	cmp	r2, r3
- 800f84a:	d307      	bcc.n	800f85c <ip_reass_chain_frag_into_datagram_and_validate+0xf0>
- 800f84c:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 800f84e:	88db      	ldrh	r3, [r3, #6]
- 800f850:	b29a      	uxth	r2, r3
- 800f852:	693b      	ldr	r3, [r7, #16]
- 800f854:	889b      	ldrh	r3, [r3, #4]
- 800f856:	b29b      	uxth	r3, r3
- 800f858:	429a      	cmp	r2, r3
- 800f85a:	d902      	bls.n	800f862 <ip_reass_chain_frag_into_datagram_and_validate+0xf6>
-          /* fragment overlaps with previous or following, throw away */
-          return IP_REASS_VALIDATE_PBUF_DROPPED;
- 800f85c:	f04f 33ff 	mov.w	r3, #4294967295
- 800f860:	e0de      	b.n	800fa20 <ip_reass_chain_frag_into_datagram_and_validate+0x2b4>
-        }
-#endif /* IP_REASS_CHECK_OVERLAP */
-        iprh_prev->next_pbuf = new_p;
- 800f862:	6abb      	ldr	r3, [r7, #40]	; 0x28
- 800f864:	68ba      	ldr	r2, [r7, #8]
- 800f866:	601a      	str	r2, [r3, #0]
-        if (iprh_prev->end != iprh->start) {
- 800f868:	6abb      	ldr	r3, [r7, #40]	; 0x28
- 800f86a:	88db      	ldrh	r3, [r3, #6]
- 800f86c:	b29a      	uxth	r2, r3
- 800f86e:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 800f870:	889b      	ldrh	r3, [r3, #4]
- 800f872:	b29b      	uxth	r3, r3
- 800f874:	429a      	cmp	r2, r3
- 800f876:	d03d      	beq.n	800f8f4 <ip_reass_chain_frag_into_datagram_and_validate+0x188>
-          /* There is a fragment missing between the current
-           * and the previous fragment */
-          valid = 0;
- 800f878:	2300      	movs	r3, #0
- 800f87a:	623b      	str	r3, [r7, #32]
-        }
-#endif /* IP_REASS_CHECK_OVERLAP */
-        /* fragment with the lowest offset */
-        ipr->p = new_p;
-      }
-      break;
- 800f87c:	e03a      	b.n	800f8f4 <ip_reass_chain_frag_into_datagram_and_validate+0x188>
-        if (iprh->end > iprh_tmp->start) {
- 800f87e:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 800f880:	88db      	ldrh	r3, [r3, #6]
- 800f882:	b29a      	uxth	r2, r3
- 800f884:	693b      	ldr	r3, [r7, #16]
- 800f886:	889b      	ldrh	r3, [r3, #4]
- 800f888:	b29b      	uxth	r3, r3
- 800f88a:	429a      	cmp	r2, r3
- 800f88c:	d902      	bls.n	800f894 <ip_reass_chain_frag_into_datagram_and_validate+0x128>
-          return IP_REASS_VALIDATE_PBUF_DROPPED;
- 800f88e:	f04f 33ff 	mov.w	r3, #4294967295
- 800f892:	e0c5      	b.n	800fa20 <ip_reass_chain_frag_into_datagram_and_validate+0x2b4>
-        ipr->p = new_p;
- 800f894:	68fb      	ldr	r3, [r7, #12]
- 800f896:	68ba      	ldr	r2, [r7, #8]
- 800f898:	605a      	str	r2, [r3, #4]
-      break;
- 800f89a:	e02b      	b.n	800f8f4 <ip_reass_chain_frag_into_datagram_and_validate+0x188>
-    } else if (iprh->start == iprh_tmp->start) {
- 800f89c:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 800f89e:	889b      	ldrh	r3, [r3, #4]
- 800f8a0:	b29a      	uxth	r2, r3
- 800f8a2:	693b      	ldr	r3, [r7, #16]
- 800f8a4:	889b      	ldrh	r3, [r3, #4]
- 800f8a6:	b29b      	uxth	r3, r3
- 800f8a8:	429a      	cmp	r2, r3
- 800f8aa:	d102      	bne.n	800f8b2 <ip_reass_chain_frag_into_datagram_and_validate+0x146>
-      /* received the same datagram twice: no need to keep the datagram */
-      return IP_REASS_VALIDATE_PBUF_DROPPED;
- 800f8ac:	f04f 33ff 	mov.w	r3, #4294967295
- 800f8b0:	e0b6      	b.n	800fa20 <ip_reass_chain_frag_into_datagram_and_validate+0x2b4>
-#if IP_REASS_CHECK_OVERLAP
-    } else if (iprh->start < iprh_tmp->end) {
- 800f8b2:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 800f8b4:	889b      	ldrh	r3, [r3, #4]
- 800f8b6:	b29a      	uxth	r2, r3
- 800f8b8:	693b      	ldr	r3, [r7, #16]
- 800f8ba:	88db      	ldrh	r3, [r3, #6]
- 800f8bc:	b29b      	uxth	r3, r3
- 800f8be:	429a      	cmp	r2, r3
- 800f8c0:	d202      	bcs.n	800f8c8 <ip_reass_chain_frag_into_datagram_and_validate+0x15c>
-      /* overlap: no need to keep the new datagram */
-      return IP_REASS_VALIDATE_PBUF_DROPPED;
- 800f8c2:	f04f 33ff 	mov.w	r3, #4294967295
- 800f8c6:	e0ab      	b.n	800fa20 <ip_reass_chain_frag_into_datagram_and_validate+0x2b4>
-#endif /* IP_REASS_CHECK_OVERLAP */
-    } else {
-      /* Check if the fragments received so far have no holes. */
-      if (iprh_prev != NULL) {
- 800f8c8:	6abb      	ldr	r3, [r7, #40]	; 0x28
- 800f8ca:	2b00      	cmp	r3, #0
- 800f8cc:	d009      	beq.n	800f8e2 <ip_reass_chain_frag_into_datagram_and_validate+0x176>
-        if (iprh_prev->end != iprh_tmp->start) {
- 800f8ce:	6abb      	ldr	r3, [r7, #40]	; 0x28
- 800f8d0:	88db      	ldrh	r3, [r3, #6]
- 800f8d2:	b29a      	uxth	r2, r3
- 800f8d4:	693b      	ldr	r3, [r7, #16]
- 800f8d6:	889b      	ldrh	r3, [r3, #4]
- 800f8d8:	b29b      	uxth	r3, r3
- 800f8da:	429a      	cmp	r2, r3
- 800f8dc:	d001      	beq.n	800f8e2 <ip_reass_chain_frag_into_datagram_and_validate+0x176>
-          /* There is a fragment missing between the current
-           * and the previous fragment */
-          valid = 0;
- 800f8de:	2300      	movs	r3, #0
- 800f8e0:	623b      	str	r3, [r7, #32]
-        }
-      }
-    }
-    q = iprh_tmp->next_pbuf;
- 800f8e2:	693b      	ldr	r3, [r7, #16]
- 800f8e4:	681b      	ldr	r3, [r3, #0]
- 800f8e6:	627b      	str	r3, [r7, #36]	; 0x24
-    iprh_prev = iprh_tmp;
- 800f8e8:	693b      	ldr	r3, [r7, #16]
- 800f8ea:	62bb      	str	r3, [r7, #40]	; 0x28
-  for (q = ipr->p; q != NULL;) {
- 800f8ec:	6a7b      	ldr	r3, [r7, #36]	; 0x24
- 800f8ee:	2b00      	cmp	r3, #0
- 800f8f0:	d193      	bne.n	800f81a <ip_reass_chain_frag_into_datagram_and_validate+0xae>
- 800f8f2:	e000      	b.n	800f8f6 <ip_reass_chain_frag_into_datagram_and_validate+0x18a>
-      break;
- 800f8f4:	bf00      	nop
-  }
-
-  /* If q is NULL, then we made it to the end of the list. Determine what to do now */
-  if (q == NULL) {
- 800f8f6:	6a7b      	ldr	r3, [r7, #36]	; 0x24
- 800f8f8:	2b00      	cmp	r3, #0
- 800f8fa:	d12d      	bne.n	800f958 <ip_reass_chain_frag_into_datagram_and_validate+0x1ec>
-    if (iprh_prev != NULL) {
- 800f8fc:	6abb      	ldr	r3, [r7, #40]	; 0x28
- 800f8fe:	2b00      	cmp	r3, #0
- 800f900:	d01c      	beq.n	800f93c <ip_reass_chain_frag_into_datagram_and_validate+0x1d0>
-      /* this is (for now), the fragment with the highest offset:
-       * chain it to the last fragment */
-#if IP_REASS_CHECK_OVERLAP
-      LWIP_ASSERT("check fragments don't overlap", iprh_prev->end <= iprh->start);
- 800f902:	6abb      	ldr	r3, [r7, #40]	; 0x28
- 800f904:	88db      	ldrh	r3, [r3, #6]
- 800f906:	b29a      	uxth	r2, r3
- 800f908:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 800f90a:	889b      	ldrh	r3, [r3, #4]
- 800f90c:	b29b      	uxth	r3, r3
- 800f90e:	429a      	cmp	r2, r3
- 800f910:	d906      	bls.n	800f920 <ip_reass_chain_frag_into_datagram_and_validate+0x1b4>
- 800f912:	4b45      	ldr	r3, [pc, #276]	; (800fa28 <ip_reass_chain_frag_into_datagram_and_validate+0x2bc>)
- 800f914:	f44f 72db 	mov.w	r2, #438	; 0x1b6
- 800f918:	4944      	ldr	r1, [pc, #272]	; (800fa2c <ip_reass_chain_frag_into_datagram_and_validate+0x2c0>)
- 800f91a:	4845      	ldr	r0, [pc, #276]	; (800fa30 <ip_reass_chain_frag_into_datagram_and_validate+0x2c4>)
- 800f91c:	f001 f954 	bl	8010bc8 <iprintf>
-#endif /* IP_REASS_CHECK_OVERLAP */
-      iprh_prev->next_pbuf = new_p;
- 800f920:	6abb      	ldr	r3, [r7, #40]	; 0x28
- 800f922:	68ba      	ldr	r2, [r7, #8]
- 800f924:	601a      	str	r2, [r3, #0]
-      if (iprh_prev->end != iprh->start) {
- 800f926:	6abb      	ldr	r3, [r7, #40]	; 0x28
- 800f928:	88db      	ldrh	r3, [r3, #6]
- 800f92a:	b29a      	uxth	r2, r3
- 800f92c:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 800f92e:	889b      	ldrh	r3, [r3, #4]
- 800f930:	b29b      	uxth	r3, r3
- 800f932:	429a      	cmp	r2, r3
- 800f934:	d010      	beq.n	800f958 <ip_reass_chain_frag_into_datagram_and_validate+0x1ec>
-        valid = 0;
- 800f936:	2300      	movs	r3, #0
- 800f938:	623b      	str	r3, [r7, #32]
- 800f93a:	e00d      	b.n	800f958 <ip_reass_chain_frag_into_datagram_and_validate+0x1ec>
-      }
-    } else {
-#if IP_REASS_CHECK_OVERLAP
-      LWIP_ASSERT("no previous fragment, this must be the first fragment!",
- 800f93c:	68fb      	ldr	r3, [r7, #12]
- 800f93e:	685b      	ldr	r3, [r3, #4]
- 800f940:	2b00      	cmp	r3, #0
- 800f942:	d006      	beq.n	800f952 <ip_reass_chain_frag_into_datagram_and_validate+0x1e6>
- 800f944:	4b38      	ldr	r3, [pc, #224]	; (800fa28 <ip_reass_chain_frag_into_datagram_and_validate+0x2bc>)
- 800f946:	f44f 72df 	mov.w	r2, #446	; 0x1be
- 800f94a:	493a      	ldr	r1, [pc, #232]	; (800fa34 <ip_reass_chain_frag_into_datagram_and_validate+0x2c8>)
- 800f94c:	4838      	ldr	r0, [pc, #224]	; (800fa30 <ip_reass_chain_frag_into_datagram_and_validate+0x2c4>)
- 800f94e:	f001 f93b 	bl	8010bc8 <iprintf>
-                  ipr->p == NULL);
-#endif /* IP_REASS_CHECK_OVERLAP */
-      /* this is the first fragment we ever received for this ip datagram */
-      ipr->p = new_p;
- 800f952:	68fb      	ldr	r3, [r7, #12]
- 800f954:	68ba      	ldr	r2, [r7, #8]
- 800f956:	605a      	str	r2, [r3, #4]
-    }
-  }
-
-  /* At this point, the validation part begins: */
-  /* If we already received the last fragment */
-  if (is_last || ((ipr->flags & IP_REASS_FLAG_LASTFRAG) != 0)) {
- 800f958:	687b      	ldr	r3, [r7, #4]
- 800f95a:	2b00      	cmp	r3, #0
- 800f95c:	d105      	bne.n	800f96a <ip_reass_chain_frag_into_datagram_and_validate+0x1fe>
- 800f95e:	68fb      	ldr	r3, [r7, #12]
- 800f960:	7f9b      	ldrb	r3, [r3, #30]
- 800f962:	f003 0301 	and.w	r3, r3, #1
- 800f966:	2b00      	cmp	r3, #0
- 800f968:	d059      	beq.n	800fa1e <ip_reass_chain_frag_into_datagram_and_validate+0x2b2>
-    /* and had no holes so far */
-    if (valid) {
- 800f96a:	6a3b      	ldr	r3, [r7, #32]
- 800f96c:	2b00      	cmp	r3, #0
- 800f96e:	d04f      	beq.n	800fa10 <ip_reass_chain_frag_into_datagram_and_validate+0x2a4>
-      /* then check if the rest of the fragments is here */
-      /* Check if the queue starts with the first datagram */
-      if ((ipr->p == NULL) || (((struct ip_reass_helper *)ipr->p->payload)->start != 0)) {
- 800f970:	68fb      	ldr	r3, [r7, #12]
- 800f972:	685b      	ldr	r3, [r3, #4]
- 800f974:	2b00      	cmp	r3, #0
- 800f976:	d006      	beq.n	800f986 <ip_reass_chain_frag_into_datagram_and_validate+0x21a>
- 800f978:	68fb      	ldr	r3, [r7, #12]
- 800f97a:	685b      	ldr	r3, [r3, #4]
- 800f97c:	685b      	ldr	r3, [r3, #4]
- 800f97e:	889b      	ldrh	r3, [r3, #4]
- 800f980:	b29b      	uxth	r3, r3
- 800f982:	2b00      	cmp	r3, #0
- 800f984:	d002      	beq.n	800f98c <ip_reass_chain_frag_into_datagram_and_validate+0x220>
-        valid = 0;
- 800f986:	2300      	movs	r3, #0
- 800f988:	623b      	str	r3, [r7, #32]
- 800f98a:	e041      	b.n	800fa10 <ip_reass_chain_frag_into_datagram_and_validate+0x2a4>
-      } else {
-        /* and check that there are no holes after this datagram */
-        iprh_prev = iprh;
- 800f98c:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 800f98e:	62bb      	str	r3, [r7, #40]	; 0x28
-        q = iprh->next_pbuf;
- 800f990:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 800f992:	681b      	ldr	r3, [r3, #0]
- 800f994:	627b      	str	r3, [r7, #36]	; 0x24
-        while (q != NULL) {
- 800f996:	e012      	b.n	800f9be <ip_reass_chain_frag_into_datagram_and_validate+0x252>
-          iprh = (struct ip_reass_helper *)q->payload;
- 800f998:	6a7b      	ldr	r3, [r7, #36]	; 0x24
- 800f99a:	685b      	ldr	r3, [r3, #4]
- 800f99c:	62fb      	str	r3, [r7, #44]	; 0x2c
-          if (iprh_prev->end != iprh->start) {
- 800f99e:	6abb      	ldr	r3, [r7, #40]	; 0x28
- 800f9a0:	88db      	ldrh	r3, [r3, #6]
- 800f9a2:	b29a      	uxth	r2, r3
- 800f9a4:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 800f9a6:	889b      	ldrh	r3, [r3, #4]
- 800f9a8:	b29b      	uxth	r3, r3
- 800f9aa:	429a      	cmp	r2, r3
- 800f9ac:	d002      	beq.n	800f9b4 <ip_reass_chain_frag_into_datagram_and_validate+0x248>
-            valid = 0;
- 800f9ae:	2300      	movs	r3, #0
- 800f9b0:	623b      	str	r3, [r7, #32]
-            break;
- 800f9b2:	e007      	b.n	800f9c4 <ip_reass_chain_frag_into_datagram_and_validate+0x258>
-          }
-          iprh_prev = iprh;
- 800f9b4:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 800f9b6:	62bb      	str	r3, [r7, #40]	; 0x28
-          q = iprh->next_pbuf;
- 800f9b8:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 800f9ba:	681b      	ldr	r3, [r3, #0]
- 800f9bc:	627b      	str	r3, [r7, #36]	; 0x24
-        while (q != NULL) {
- 800f9be:	6a7b      	ldr	r3, [r7, #36]	; 0x24
- 800f9c0:	2b00      	cmp	r3, #0
- 800f9c2:	d1e9      	bne.n	800f998 <ip_reass_chain_frag_into_datagram_and_validate+0x22c>
-        }
-        /* if still valid, all fragments are received
-         * (because to the MF==0 already arrived */
-        if (valid) {
- 800f9c4:	6a3b      	ldr	r3, [r7, #32]
- 800f9c6:	2b00      	cmp	r3, #0
- 800f9c8:	d022      	beq.n	800fa10 <ip_reass_chain_frag_into_datagram_and_validate+0x2a4>
-          LWIP_ASSERT("sanity check", ipr->p != NULL);
- 800f9ca:	68fb      	ldr	r3, [r7, #12]
- 800f9cc:	685b      	ldr	r3, [r3, #4]
- 800f9ce:	2b00      	cmp	r3, #0
- 800f9d0:	d106      	bne.n	800f9e0 <ip_reass_chain_frag_into_datagram_and_validate+0x274>
- 800f9d2:	4b15      	ldr	r3, [pc, #84]	; (800fa28 <ip_reass_chain_frag_into_datagram_and_validate+0x2bc>)
- 800f9d4:	f240 12df 	movw	r2, #479	; 0x1df
- 800f9d8:	4917      	ldr	r1, [pc, #92]	; (800fa38 <ip_reass_chain_frag_into_datagram_and_validate+0x2cc>)
- 800f9da:	4815      	ldr	r0, [pc, #84]	; (800fa30 <ip_reass_chain_frag_into_datagram_and_validate+0x2c4>)
- 800f9dc:	f001 f8f4 	bl	8010bc8 <iprintf>
-          LWIP_ASSERT("sanity check",
- 800f9e0:	68fb      	ldr	r3, [r7, #12]
- 800f9e2:	685b      	ldr	r3, [r3, #4]
- 800f9e4:	685b      	ldr	r3, [r3, #4]
- 800f9e6:	6afa      	ldr	r2, [r7, #44]	; 0x2c
- 800f9e8:	429a      	cmp	r2, r3
- 800f9ea:	d106      	bne.n	800f9fa <ip_reass_chain_frag_into_datagram_and_validate+0x28e>
- 800f9ec:	4b0e      	ldr	r3, [pc, #56]	; (800fa28 <ip_reass_chain_frag_into_datagram_and_validate+0x2bc>)
- 800f9ee:	f44f 72f0 	mov.w	r2, #480	; 0x1e0
- 800f9f2:	4911      	ldr	r1, [pc, #68]	; (800fa38 <ip_reass_chain_frag_into_datagram_and_validate+0x2cc>)
- 800f9f4:	480e      	ldr	r0, [pc, #56]	; (800fa30 <ip_reass_chain_frag_into_datagram_and_validate+0x2c4>)
- 800f9f6:	f001 f8e7 	bl	8010bc8 <iprintf>
-                      ((struct ip_reass_helper *)ipr->p->payload) != iprh);
-          LWIP_ASSERT("validate_datagram:next_pbuf!=NULL",
- 800f9fa:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 800f9fc:	681b      	ldr	r3, [r3, #0]
- 800f9fe:	2b00      	cmp	r3, #0
- 800fa00:	d006      	beq.n	800fa10 <ip_reass_chain_frag_into_datagram_and_validate+0x2a4>
- 800fa02:	4b09      	ldr	r3, [pc, #36]	; (800fa28 <ip_reass_chain_frag_into_datagram_and_validate+0x2bc>)
- 800fa04:	f44f 72f1 	mov.w	r2, #482	; 0x1e2
- 800fa08:	490c      	ldr	r1, [pc, #48]	; (800fa3c <ip_reass_chain_frag_into_datagram_and_validate+0x2d0>)
- 800fa0a:	4809      	ldr	r0, [pc, #36]	; (800fa30 <ip_reass_chain_frag_into_datagram_and_validate+0x2c4>)
- 800fa0c:	f001 f8dc 	bl	8010bc8 <iprintf>
-      }
-    }
-    /* If valid is 0 here, there are some fragments missing in the middle
-     * (since MF == 0 has already arrived). Such datagrams simply time out if
-     * no more fragments are received... */
-    return valid ? IP_REASS_VALIDATE_TELEGRAM_FINISHED : IP_REASS_VALIDATE_PBUF_QUEUED;
- 800fa10:	6a3b      	ldr	r3, [r7, #32]
- 800fa12:	2b00      	cmp	r3, #0
- 800fa14:	bf14      	ite	ne
- 800fa16:	2301      	movne	r3, #1
- 800fa18:	2300      	moveq	r3, #0
- 800fa1a:	b2db      	uxtb	r3, r3
- 800fa1c:	e000      	b.n	800fa20 <ip_reass_chain_frag_into_datagram_and_validate+0x2b4>
-  }
-  /* If we come here, not all fragments were received, yet! */
-  return IP_REASS_VALIDATE_PBUF_QUEUED; /* not yet valid! */
- 800fa1e:	2300      	movs	r3, #0
-}
- 800fa20:	4618      	mov	r0, r3
- 800fa22:	3730      	adds	r7, #48	; 0x30
- 800fa24:	46bd      	mov	sp, r7
- 800fa26:	bd80      	pop	{r7, pc}
- 800fa28:	080149bc 	.word	0x080149bc
- 800fa2c:	08014aa0 	.word	0x08014aa0
- 800fa30:	08014a04 	.word	0x08014a04
- 800fa34:	08014ac0 	.word	0x08014ac0
- 800fa38:	08014af8 	.word	0x08014af8
- 800fa3c:	08014b08 	.word	0x08014b08
-
-0800fa40 <ip4_reass>:
- * @param p points to a pbuf chain of the fragment
- * @return NULL if reassembly is incomplete, ? otherwise
- */
-struct pbuf *
-ip4_reass(struct pbuf *p)
-{
- 800fa40:	b580      	push	{r7, lr}
- 800fa42:	b08e      	sub	sp, #56	; 0x38
- 800fa44:	af00      	add	r7, sp, #0
- 800fa46:	6078      	str	r0, [r7, #4]
-  int is_last;
-
-  IPFRAG_STATS_INC(ip_frag.recv);
-  MIB2_STATS_INC(mib2.ipreasmreqds);
-
-  fraghdr = (struct ip_hdr *)p->payload;
- 800fa48:	687b      	ldr	r3, [r7, #4]
- 800fa4a:	685b      	ldr	r3, [r3, #4]
- 800fa4c:	62bb      	str	r3, [r7, #40]	; 0x28
-
-  if (IPH_HL_BYTES(fraghdr) != IP_HLEN) {
- 800fa4e:	6abb      	ldr	r3, [r7, #40]	; 0x28
- 800fa50:	781b      	ldrb	r3, [r3, #0]
- 800fa52:	f003 030f 	and.w	r3, r3, #15
- 800fa56:	b2db      	uxtb	r3, r3
- 800fa58:	009b      	lsls	r3, r3, #2
- 800fa5a:	b2db      	uxtb	r3, r3
- 800fa5c:	2b14      	cmp	r3, #20
- 800fa5e:	f040 8171 	bne.w	800fd44 <ip4_reass+0x304>
-    LWIP_DEBUGF(IP_REASS_DEBUG, ("ip4_reass: IP options currently not supported!\n"));
-    IPFRAG_STATS_INC(ip_frag.err);
-    goto nullreturn;
-  }
-
-  offset = IPH_OFFSET_BYTES(fraghdr);
- 800fa62:	6abb      	ldr	r3, [r7, #40]	; 0x28
- 800fa64:	88db      	ldrh	r3, [r3, #6]
- 800fa66:	b29b      	uxth	r3, r3
- 800fa68:	4618      	mov	r0, r3
- 800fa6a:	f7f5 fd6f 	bl	800554c <lwip_htons>
- 800fa6e:	4603      	mov	r3, r0
- 800fa70:	f3c3 030c 	ubfx	r3, r3, #0, #13
- 800fa74:	b29b      	uxth	r3, r3
- 800fa76:	00db      	lsls	r3, r3, #3
- 800fa78:	84fb      	strh	r3, [r7, #38]	; 0x26
-  len = lwip_ntohs(IPH_LEN(fraghdr));
- 800fa7a:	6abb      	ldr	r3, [r7, #40]	; 0x28
- 800fa7c:	885b      	ldrh	r3, [r3, #2]
- 800fa7e:	b29b      	uxth	r3, r3
- 800fa80:	4618      	mov	r0, r3
- 800fa82:	f7f5 fd63 	bl	800554c <lwip_htons>
- 800fa86:	4603      	mov	r3, r0
- 800fa88:	84bb      	strh	r3, [r7, #36]	; 0x24
-  hlen = IPH_HL_BYTES(fraghdr);
- 800fa8a:	6abb      	ldr	r3, [r7, #40]	; 0x28
- 800fa8c:	781b      	ldrb	r3, [r3, #0]
- 800fa8e:	f003 030f 	and.w	r3, r3, #15
- 800fa92:	b2db      	uxtb	r3, r3
- 800fa94:	009b      	lsls	r3, r3, #2
- 800fa96:	f887 3023 	strb.w	r3, [r7, #35]	; 0x23
-  if (hlen > len) {
- 800fa9a:	f897 3023 	ldrb.w	r3, [r7, #35]	; 0x23
- 800fa9e:	b29b      	uxth	r3, r3
- 800faa0:	8cba      	ldrh	r2, [r7, #36]	; 0x24
- 800faa2:	429a      	cmp	r2, r3
- 800faa4:	f0c0 8150 	bcc.w	800fd48 <ip4_reass+0x308>
-    /* invalid datagram */
-    goto nullreturn;
-  }
-  len = (u16_t)(len - hlen);
- 800faa8:	f897 3023 	ldrb.w	r3, [r7, #35]	; 0x23
- 800faac:	b29b      	uxth	r3, r3
- 800faae:	8cba      	ldrh	r2, [r7, #36]	; 0x24
- 800fab0:	1ad3      	subs	r3, r2, r3
- 800fab2:	84bb      	strh	r3, [r7, #36]	; 0x24
-
-  /* Check if we are allowed to enqueue more datagrams. */
-  clen = pbuf_clen(p);
- 800fab4:	6878      	ldr	r0, [r7, #4]
- 800fab6:	f7f7 fb15 	bl	80070e4 <pbuf_clen>
- 800faba:	4603      	mov	r3, r0
- 800fabc:	843b      	strh	r3, [r7, #32]
-  if ((ip_reass_pbufcount + clen) > IP_REASS_MAX_PBUFS) {
- 800fabe:	4b8c      	ldr	r3, [pc, #560]	; (800fcf0 <ip4_reass+0x2b0>)
- 800fac0:	881b      	ldrh	r3, [r3, #0]
- 800fac2:	461a      	mov	r2, r3
- 800fac4:	8c3b      	ldrh	r3, [r7, #32]
- 800fac6:	4413      	add	r3, r2
- 800fac8:	2b0a      	cmp	r3, #10
- 800faca:	dd10      	ble.n	800faee <ip4_reass+0xae>
-#if IP_REASS_FREE_OLDEST
-    if (!ip_reass_remove_oldest_datagram(fraghdr, clen) ||
- 800facc:	8c3b      	ldrh	r3, [r7, #32]
- 800face:	4619      	mov	r1, r3
- 800fad0:	6ab8      	ldr	r0, [r7, #40]	; 0x28
- 800fad2:	f7ff fd81 	bl	800f5d8 <ip_reass_remove_oldest_datagram>
- 800fad6:	4603      	mov	r3, r0
- 800fad8:	2b00      	cmp	r3, #0
- 800fada:	f000 8137 	beq.w	800fd4c <ip4_reass+0x30c>
-        ((ip_reass_pbufcount + clen) > IP_REASS_MAX_PBUFS))
- 800fade:	4b84      	ldr	r3, [pc, #528]	; (800fcf0 <ip4_reass+0x2b0>)
- 800fae0:	881b      	ldrh	r3, [r3, #0]
- 800fae2:	461a      	mov	r2, r3
- 800fae4:	8c3b      	ldrh	r3, [r7, #32]
- 800fae6:	4413      	add	r3, r2
-    if (!ip_reass_remove_oldest_datagram(fraghdr, clen) ||
- 800fae8:	2b0a      	cmp	r3, #10
- 800faea:	f300 812f 	bgt.w	800fd4c <ip4_reass+0x30c>
-    }
-  }
-
-  /* Look for the datagram the fragment belongs to in the current datagram queue,
-   * remembering the previous in the queue for later dequeueing. */
-  for (ipr = reassdatagrams; ipr != NULL; ipr = ipr->next) {
- 800faee:	4b81      	ldr	r3, [pc, #516]	; (800fcf4 <ip4_reass+0x2b4>)
- 800faf0:	681b      	ldr	r3, [r3, #0]
- 800faf2:	633b      	str	r3, [r7, #48]	; 0x30
- 800faf4:	e015      	b.n	800fb22 <ip4_reass+0xe2>
-    /* Check if the incoming fragment matches the one currently present
-       in the reassembly buffer. If so, we proceed with copying the
-       fragment into the buffer. */
-    if (IP_ADDRESSES_AND_ID_MATCH(&ipr->iphdr, fraghdr)) {
- 800faf6:	6b3b      	ldr	r3, [r7, #48]	; 0x30
- 800faf8:	695a      	ldr	r2, [r3, #20]
- 800fafa:	6abb      	ldr	r3, [r7, #40]	; 0x28
- 800fafc:	68db      	ldr	r3, [r3, #12]
- 800fafe:	429a      	cmp	r2, r3
- 800fb00:	d10c      	bne.n	800fb1c <ip4_reass+0xdc>
- 800fb02:	6b3b      	ldr	r3, [r7, #48]	; 0x30
- 800fb04:	699a      	ldr	r2, [r3, #24]
- 800fb06:	6abb      	ldr	r3, [r7, #40]	; 0x28
- 800fb08:	691b      	ldr	r3, [r3, #16]
- 800fb0a:	429a      	cmp	r2, r3
- 800fb0c:	d106      	bne.n	800fb1c <ip4_reass+0xdc>
- 800fb0e:	6b3b      	ldr	r3, [r7, #48]	; 0x30
- 800fb10:	899a      	ldrh	r2, [r3, #12]
- 800fb12:	6abb      	ldr	r3, [r7, #40]	; 0x28
- 800fb14:	889b      	ldrh	r3, [r3, #4]
- 800fb16:	b29b      	uxth	r3, r3
- 800fb18:	429a      	cmp	r2, r3
- 800fb1a:	d006      	beq.n	800fb2a <ip4_reass+0xea>
-  for (ipr = reassdatagrams; ipr != NULL; ipr = ipr->next) {
- 800fb1c:	6b3b      	ldr	r3, [r7, #48]	; 0x30
- 800fb1e:	681b      	ldr	r3, [r3, #0]
- 800fb20:	633b      	str	r3, [r7, #48]	; 0x30
- 800fb22:	6b3b      	ldr	r3, [r7, #48]	; 0x30
- 800fb24:	2b00      	cmp	r3, #0
- 800fb26:	d1e6      	bne.n	800faf6 <ip4_reass+0xb6>
- 800fb28:	e000      	b.n	800fb2c <ip4_reass+0xec>
-      LWIP_DEBUGF(IP_REASS_DEBUG, ("ip4_reass: matching previous fragment ID=%"X16_F"\n",
-                                   lwip_ntohs(IPH_ID(fraghdr))));
-      IPFRAG_STATS_INC(ip_frag.cachehit);
-      break;
- 800fb2a:	bf00      	nop
-    }
-  }
-
-  if (ipr == NULL) {
- 800fb2c:	6b3b      	ldr	r3, [r7, #48]	; 0x30
- 800fb2e:	2b00      	cmp	r3, #0
- 800fb30:	d109      	bne.n	800fb46 <ip4_reass+0x106>
-    /* Enqueue a new datagram into the datagram queue */
-    ipr = ip_reass_enqueue_new_datagram(fraghdr, clen);
- 800fb32:	8c3b      	ldrh	r3, [r7, #32]
- 800fb34:	4619      	mov	r1, r3
- 800fb36:	6ab8      	ldr	r0, [r7, #40]	; 0x28
- 800fb38:	f7ff fdb0 	bl	800f69c <ip_reass_enqueue_new_datagram>
- 800fb3c:	6338      	str	r0, [r7, #48]	; 0x30
-    /* Bail if unable to enqueue */
-    if (ipr == NULL) {
- 800fb3e:	6b3b      	ldr	r3, [r7, #48]	; 0x30
- 800fb40:	2b00      	cmp	r3, #0
- 800fb42:	d11c      	bne.n	800fb7e <ip4_reass+0x13e>
-      goto nullreturn;
- 800fb44:	e105      	b.n	800fd52 <ip4_reass+0x312>
-    }
-  } else {
-    if (((lwip_ntohs(IPH_OFFSET(fraghdr)) & IP_OFFMASK) == 0) &&
- 800fb46:	6abb      	ldr	r3, [r7, #40]	; 0x28
- 800fb48:	88db      	ldrh	r3, [r3, #6]
- 800fb4a:	b29b      	uxth	r3, r3
- 800fb4c:	4618      	mov	r0, r3
- 800fb4e:	f7f5 fcfd 	bl	800554c <lwip_htons>
- 800fb52:	4603      	mov	r3, r0
- 800fb54:	f3c3 030c 	ubfx	r3, r3, #0, #13
- 800fb58:	2b00      	cmp	r3, #0
- 800fb5a:	d110      	bne.n	800fb7e <ip4_reass+0x13e>
-        ((lwip_ntohs(IPH_OFFSET(&ipr->iphdr)) & IP_OFFMASK) != 0)) {
- 800fb5c:	6b3b      	ldr	r3, [r7, #48]	; 0x30
- 800fb5e:	89db      	ldrh	r3, [r3, #14]
- 800fb60:	4618      	mov	r0, r3
- 800fb62:	f7f5 fcf3 	bl	800554c <lwip_htons>
- 800fb66:	4603      	mov	r3, r0
- 800fb68:	f3c3 030c 	ubfx	r3, r3, #0, #13
-    if (((lwip_ntohs(IPH_OFFSET(fraghdr)) & IP_OFFMASK) == 0) &&
- 800fb6c:	2b00      	cmp	r3, #0
- 800fb6e:	d006      	beq.n	800fb7e <ip4_reass+0x13e>
-      /* ipr->iphdr is not the header from the first fragment, but fraghdr is
-       * -> copy fraghdr into ipr->iphdr since we want to have the header
-       * of the first fragment (for ICMP time exceeded and later, for copying
-       * all options, if supported)*/
-      SMEMCPY(&ipr->iphdr, fraghdr, IP_HLEN);
- 800fb70:	6b3b      	ldr	r3, [r7, #48]	; 0x30
- 800fb72:	3308      	adds	r3, #8
- 800fb74:	2214      	movs	r2, #20
- 800fb76:	6ab9      	ldr	r1, [r7, #40]	; 0x28
- 800fb78:	4618      	mov	r0, r3
- 800fb7a:	f001 fa06 	bl	8010f8a <memcpy>
-
-  /* At this point, we have either created a new entry or pointing
-   * to an existing one */
-
-  /* check for 'no more fragments', and update queue entry*/
-  is_last = (IPH_OFFSET(fraghdr) & PP_NTOHS(IP_MF)) == 0;
- 800fb7e:	6abb      	ldr	r3, [r7, #40]	; 0x28
- 800fb80:	88db      	ldrh	r3, [r3, #6]
- 800fb82:	b29b      	uxth	r3, r3
- 800fb84:	f003 0320 	and.w	r3, r3, #32
- 800fb88:	2b00      	cmp	r3, #0
- 800fb8a:	bf0c      	ite	eq
- 800fb8c:	2301      	moveq	r3, #1
- 800fb8e:	2300      	movne	r3, #0
- 800fb90:	b2db      	uxtb	r3, r3
- 800fb92:	61fb      	str	r3, [r7, #28]
-  if (is_last) {
- 800fb94:	69fb      	ldr	r3, [r7, #28]
- 800fb96:	2b00      	cmp	r3, #0
- 800fb98:	d00e      	beq.n	800fbb8 <ip4_reass+0x178>
-    u16_t datagram_len = (u16_t)(offset + len);
- 800fb9a:	8cfa      	ldrh	r2, [r7, #38]	; 0x26
- 800fb9c:	8cbb      	ldrh	r3, [r7, #36]	; 0x24
- 800fb9e:	4413      	add	r3, r2
- 800fba0:	837b      	strh	r3, [r7, #26]
-    if ((datagram_len < offset) || (datagram_len > (0xFFFF - IP_HLEN))) {
- 800fba2:	8b7a      	ldrh	r2, [r7, #26]
- 800fba4:	8cfb      	ldrh	r3, [r7, #38]	; 0x26
- 800fba6:	429a      	cmp	r2, r3
- 800fba8:	f0c0 80a0 	bcc.w	800fcec <ip4_reass+0x2ac>
- 800fbac:	8b7b      	ldrh	r3, [r7, #26]
- 800fbae:	f64f 72eb 	movw	r2, #65515	; 0xffeb
- 800fbb2:	4293      	cmp	r3, r2
- 800fbb4:	f200 809a 	bhi.w	800fcec <ip4_reass+0x2ac>
-      goto nullreturn_ipr;
-    }
-  }
-  /* find the right place to insert this pbuf */
-  /* @todo: trim pbufs if fragments are overlapping */
-  valid = ip_reass_chain_frag_into_datagram_and_validate(ipr, p, is_last);
- 800fbb8:	69fa      	ldr	r2, [r7, #28]
- 800fbba:	6879      	ldr	r1, [r7, #4]
- 800fbbc:	6b38      	ldr	r0, [r7, #48]	; 0x30
- 800fbbe:	f7ff fdd5 	bl	800f76c <ip_reass_chain_frag_into_datagram_and_validate>
- 800fbc2:	6178      	str	r0, [r7, #20]
-  if (valid == IP_REASS_VALIDATE_PBUF_DROPPED) {
- 800fbc4:	697b      	ldr	r3, [r7, #20]
- 800fbc6:	f1b3 3fff 	cmp.w	r3, #4294967295
- 800fbca:	f000 809b 	beq.w	800fd04 <ip4_reass+0x2c4>
-  /* if we come here, the pbuf has been enqueued */
-
-  /* Track the current number of pbufs current 'in-flight', in order to limit
-     the number of fragments that may be enqueued at any one time
-     (overflow checked by testing against IP_REASS_MAX_PBUFS) */
-  ip_reass_pbufcount = (u16_t)(ip_reass_pbufcount + clen);
- 800fbce:	4b48      	ldr	r3, [pc, #288]	; (800fcf0 <ip4_reass+0x2b0>)
- 800fbd0:	881a      	ldrh	r2, [r3, #0]
- 800fbd2:	8c3b      	ldrh	r3, [r7, #32]
- 800fbd4:	4413      	add	r3, r2
- 800fbd6:	b29a      	uxth	r2, r3
- 800fbd8:	4b45      	ldr	r3, [pc, #276]	; (800fcf0 <ip4_reass+0x2b0>)
- 800fbda:	801a      	strh	r2, [r3, #0]
-  if (is_last) {
- 800fbdc:	69fb      	ldr	r3, [r7, #28]
- 800fbde:	2b00      	cmp	r3, #0
- 800fbe0:	d00d      	beq.n	800fbfe <ip4_reass+0x1be>
-    u16_t datagram_len = (u16_t)(offset + len);
- 800fbe2:	8cfa      	ldrh	r2, [r7, #38]	; 0x26
- 800fbe4:	8cbb      	ldrh	r3, [r7, #36]	; 0x24
- 800fbe6:	4413      	add	r3, r2
- 800fbe8:	827b      	strh	r3, [r7, #18]
-    ipr->datagram_len = datagram_len;
- 800fbea:	6b3b      	ldr	r3, [r7, #48]	; 0x30
- 800fbec:	8a7a      	ldrh	r2, [r7, #18]
- 800fbee:	839a      	strh	r2, [r3, #28]
-    ipr->flags |= IP_REASS_FLAG_LASTFRAG;
- 800fbf0:	6b3b      	ldr	r3, [r7, #48]	; 0x30
- 800fbf2:	7f9b      	ldrb	r3, [r3, #30]
- 800fbf4:	f043 0301 	orr.w	r3, r3, #1
- 800fbf8:	b2da      	uxtb	r2, r3
- 800fbfa:	6b3b      	ldr	r3, [r7, #48]	; 0x30
- 800fbfc:	779a      	strb	r2, [r3, #30]
-    LWIP_DEBUGF(IP_REASS_DEBUG,
-                ("ip4_reass: last fragment seen, total len %"S16_F"\n",
-                 ipr->datagram_len));
-  }
-
-  if (valid == IP_REASS_VALIDATE_TELEGRAM_FINISHED) {
- 800fbfe:	697b      	ldr	r3, [r7, #20]
- 800fc00:	2b01      	cmp	r3, #1
- 800fc02:	d171      	bne.n	800fce8 <ip4_reass+0x2a8>
-    struct ip_reassdata *ipr_prev;
-    /* the totally last fragment (flag more fragments = 0) was received at least
-     * once AND all fragments are received */
-    u16_t datagram_len = (u16_t)(ipr->datagram_len + IP_HLEN);
- 800fc04:	6b3b      	ldr	r3, [r7, #48]	; 0x30
- 800fc06:	8b9b      	ldrh	r3, [r3, #28]
- 800fc08:	3314      	adds	r3, #20
- 800fc0a:	823b      	strh	r3, [r7, #16]
-
-    /* save the second pbuf before copying the header over the pointer */
-    r = ((struct ip_reass_helper *)ipr->p->payload)->next_pbuf;
- 800fc0c:	6b3b      	ldr	r3, [r7, #48]	; 0x30
- 800fc0e:	685b      	ldr	r3, [r3, #4]
- 800fc10:	685b      	ldr	r3, [r3, #4]
- 800fc12:	681b      	ldr	r3, [r3, #0]
- 800fc14:	62fb      	str	r3, [r7, #44]	; 0x2c
-
-    /* copy the original ip header back to the first pbuf */
-    fraghdr = (struct ip_hdr *)(ipr->p->payload);
- 800fc16:	6b3b      	ldr	r3, [r7, #48]	; 0x30
- 800fc18:	685b      	ldr	r3, [r3, #4]
- 800fc1a:	685b      	ldr	r3, [r3, #4]
- 800fc1c:	62bb      	str	r3, [r7, #40]	; 0x28
-    SMEMCPY(fraghdr, &ipr->iphdr, IP_HLEN);
- 800fc1e:	6b3b      	ldr	r3, [r7, #48]	; 0x30
- 800fc20:	3308      	adds	r3, #8
- 800fc22:	2214      	movs	r2, #20
- 800fc24:	4619      	mov	r1, r3
- 800fc26:	6ab8      	ldr	r0, [r7, #40]	; 0x28
- 800fc28:	f001 f9af 	bl	8010f8a <memcpy>
-    IPH_LEN_SET(fraghdr, lwip_htons(datagram_len));
- 800fc2c:	8a3b      	ldrh	r3, [r7, #16]
- 800fc2e:	4618      	mov	r0, r3
- 800fc30:	f7f5 fc8c 	bl	800554c <lwip_htons>
- 800fc34:	4603      	mov	r3, r0
- 800fc36:	461a      	mov	r2, r3
- 800fc38:	6abb      	ldr	r3, [r7, #40]	; 0x28
- 800fc3a:	805a      	strh	r2, [r3, #2]
-    IPH_OFFSET_SET(fraghdr, 0);
- 800fc3c:	6abb      	ldr	r3, [r7, #40]	; 0x28
- 800fc3e:	2200      	movs	r2, #0
- 800fc40:	719a      	strb	r2, [r3, #6]
- 800fc42:	2200      	movs	r2, #0
- 800fc44:	71da      	strb	r2, [r3, #7]
-    IPH_CHKSUM_SET(fraghdr, 0);
- 800fc46:	6abb      	ldr	r3, [r7, #40]	; 0x28
- 800fc48:	2200      	movs	r2, #0
- 800fc4a:	729a      	strb	r2, [r3, #10]
- 800fc4c:	2200      	movs	r2, #0
- 800fc4e:	72da      	strb	r2, [r3, #11]
-    IF__NETIF_CHECKSUM_ENABLED(ip_current_input_netif(), NETIF_CHECKSUM_GEN_IP) {
-      IPH_CHKSUM_SET(fraghdr, inet_chksum(fraghdr, IP_HLEN));
-    }
-#endif /* CHECKSUM_GEN_IP */
-
-    p = ipr->p;
- 800fc50:	6b3b      	ldr	r3, [r7, #48]	; 0x30
- 800fc52:	685b      	ldr	r3, [r3, #4]
- 800fc54:	607b      	str	r3, [r7, #4]
-
-    /* chain together the pbufs contained within the reass_data list. */
-    while (r != NULL) {
- 800fc56:	e00d      	b.n	800fc74 <ip4_reass+0x234>
-      iprh = (struct ip_reass_helper *)r->payload;
- 800fc58:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 800fc5a:	685b      	ldr	r3, [r3, #4]
- 800fc5c:	60fb      	str	r3, [r7, #12]
-
-      /* hide the ip header for every succeeding fragment */
-      pbuf_remove_header(r, IP_HLEN);
- 800fc5e:	2114      	movs	r1, #20
- 800fc60:	6af8      	ldr	r0, [r7, #44]	; 0x2c
- 800fc62:	f7f7 f931 	bl	8006ec8 <pbuf_remove_header>
-      pbuf_cat(p, r);
- 800fc66:	6af9      	ldr	r1, [r7, #44]	; 0x2c
- 800fc68:	6878      	ldr	r0, [r7, #4]
- 800fc6a:	f7f7 fa75 	bl	8007158 <pbuf_cat>
-      r = iprh->next_pbuf;
- 800fc6e:	68fb      	ldr	r3, [r7, #12]
- 800fc70:	681b      	ldr	r3, [r3, #0]
- 800fc72:	62fb      	str	r3, [r7, #44]	; 0x2c
-    while (r != NULL) {
- 800fc74:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 800fc76:	2b00      	cmp	r3, #0
- 800fc78:	d1ee      	bne.n	800fc58 <ip4_reass+0x218>
-    }
-
-    /* find the previous entry in the linked list */
-    if (ipr == reassdatagrams) {
- 800fc7a:	4b1e      	ldr	r3, [pc, #120]	; (800fcf4 <ip4_reass+0x2b4>)
- 800fc7c:	681b      	ldr	r3, [r3, #0]
- 800fc7e:	6b3a      	ldr	r2, [r7, #48]	; 0x30
- 800fc80:	429a      	cmp	r2, r3
- 800fc82:	d102      	bne.n	800fc8a <ip4_reass+0x24a>
-      ipr_prev = NULL;
- 800fc84:	2300      	movs	r3, #0
- 800fc86:	637b      	str	r3, [r7, #52]	; 0x34
- 800fc88:	e010      	b.n	800fcac <ip4_reass+0x26c>
-    } else {
-      for (ipr_prev = reassdatagrams; ipr_prev != NULL; ipr_prev = ipr_prev->next) {
- 800fc8a:	4b1a      	ldr	r3, [pc, #104]	; (800fcf4 <ip4_reass+0x2b4>)
- 800fc8c:	681b      	ldr	r3, [r3, #0]
- 800fc8e:	637b      	str	r3, [r7, #52]	; 0x34
- 800fc90:	e007      	b.n	800fca2 <ip4_reass+0x262>
-        if (ipr_prev->next == ipr) {
- 800fc92:	6b7b      	ldr	r3, [r7, #52]	; 0x34
- 800fc94:	681b      	ldr	r3, [r3, #0]
- 800fc96:	6b3a      	ldr	r2, [r7, #48]	; 0x30
- 800fc98:	429a      	cmp	r2, r3
- 800fc9a:	d006      	beq.n	800fcaa <ip4_reass+0x26a>
-      for (ipr_prev = reassdatagrams; ipr_prev != NULL; ipr_prev = ipr_prev->next) {
- 800fc9c:	6b7b      	ldr	r3, [r7, #52]	; 0x34
- 800fc9e:	681b      	ldr	r3, [r3, #0]
- 800fca0:	637b      	str	r3, [r7, #52]	; 0x34
- 800fca2:	6b7b      	ldr	r3, [r7, #52]	; 0x34
- 800fca4:	2b00      	cmp	r3, #0
- 800fca6:	d1f4      	bne.n	800fc92 <ip4_reass+0x252>
- 800fca8:	e000      	b.n	800fcac <ip4_reass+0x26c>
-          break;
- 800fcaa:	bf00      	nop
-        }
-      }
-    }
-
-    /* release the sources allocate for the fragment queue entry */
-    ip_reass_dequeue_datagram(ipr, ipr_prev);
- 800fcac:	6b79      	ldr	r1, [r7, #52]	; 0x34
- 800fcae:	6b38      	ldr	r0, [r7, #48]	; 0x30
- 800fcb0:	f7ff fd2e 	bl	800f710 <ip_reass_dequeue_datagram>
-
-    /* and adjust the number of pbufs currently queued for reassembly. */
-    clen = pbuf_clen(p);
- 800fcb4:	6878      	ldr	r0, [r7, #4]
- 800fcb6:	f7f7 fa15 	bl	80070e4 <pbuf_clen>
- 800fcba:	4603      	mov	r3, r0
- 800fcbc:	843b      	strh	r3, [r7, #32]
-    LWIP_ASSERT("ip_reass_pbufcount >= clen", ip_reass_pbufcount >= clen);
- 800fcbe:	4b0c      	ldr	r3, [pc, #48]	; (800fcf0 <ip4_reass+0x2b0>)
- 800fcc0:	881b      	ldrh	r3, [r3, #0]
- 800fcc2:	8c3a      	ldrh	r2, [r7, #32]
- 800fcc4:	429a      	cmp	r2, r3
- 800fcc6:	d906      	bls.n	800fcd6 <ip4_reass+0x296>
- 800fcc8:	4b0b      	ldr	r3, [pc, #44]	; (800fcf8 <ip4_reass+0x2b8>)
- 800fcca:	f240 229b 	movw	r2, #667	; 0x29b
- 800fcce:	490b      	ldr	r1, [pc, #44]	; (800fcfc <ip4_reass+0x2bc>)
- 800fcd0:	480b      	ldr	r0, [pc, #44]	; (800fd00 <ip4_reass+0x2c0>)
- 800fcd2:	f000 ff79 	bl	8010bc8 <iprintf>
-    ip_reass_pbufcount = (u16_t)(ip_reass_pbufcount - clen);
- 800fcd6:	4b06      	ldr	r3, [pc, #24]	; (800fcf0 <ip4_reass+0x2b0>)
- 800fcd8:	881a      	ldrh	r2, [r3, #0]
- 800fcda:	8c3b      	ldrh	r3, [r7, #32]
- 800fcdc:	1ad3      	subs	r3, r2, r3
- 800fcde:	b29a      	uxth	r2, r3
- 800fce0:	4b03      	ldr	r3, [pc, #12]	; (800fcf0 <ip4_reass+0x2b0>)
- 800fce2:	801a      	strh	r2, [r3, #0]
-
-    MIB2_STATS_INC(mib2.ipreasmoks);
-
-    /* Return the pbuf chain */
-    return p;
- 800fce4:	687b      	ldr	r3, [r7, #4]
- 800fce6:	e038      	b.n	800fd5a <ip4_reass+0x31a>
-  }
-  /* the datagram is not (yet?) reassembled completely */
-  LWIP_DEBUGF(IP_REASS_DEBUG, ("ip_reass_pbufcount: %d out\n", ip_reass_pbufcount));
-  return NULL;
- 800fce8:	2300      	movs	r3, #0
- 800fcea:	e036      	b.n	800fd5a <ip4_reass+0x31a>
-      goto nullreturn_ipr;
- 800fcec:	bf00      	nop
- 800fcee:	e00a      	b.n	800fd06 <ip4_reass+0x2c6>
- 800fcf0:	24007cc8 	.word	0x24007cc8
- 800fcf4:	24007cc4 	.word	0x24007cc4
- 800fcf8:	080149bc 	.word	0x080149bc
- 800fcfc:	08014b2c 	.word	0x08014b2c
- 800fd00:	08014a04 	.word	0x08014a04
-    goto nullreturn_ipr;
- 800fd04:	bf00      	nop
-
-nullreturn_ipr:
-  LWIP_ASSERT("ipr != NULL", ipr != NULL);
- 800fd06:	6b3b      	ldr	r3, [r7, #48]	; 0x30
- 800fd08:	2b00      	cmp	r3, #0
- 800fd0a:	d106      	bne.n	800fd1a <ip4_reass+0x2da>
- 800fd0c:	4b15      	ldr	r3, [pc, #84]	; (800fd64 <ip4_reass+0x324>)
- 800fd0e:	f44f 722a 	mov.w	r2, #680	; 0x2a8
- 800fd12:	4915      	ldr	r1, [pc, #84]	; (800fd68 <ip4_reass+0x328>)
- 800fd14:	4815      	ldr	r0, [pc, #84]	; (800fd6c <ip4_reass+0x32c>)
- 800fd16:	f000 ff57 	bl	8010bc8 <iprintf>
-  if (ipr->p == NULL) {
- 800fd1a:	6b3b      	ldr	r3, [r7, #48]	; 0x30
- 800fd1c:	685b      	ldr	r3, [r3, #4]
- 800fd1e:	2b00      	cmp	r3, #0
- 800fd20:	d116      	bne.n	800fd50 <ip4_reass+0x310>
-    /* dropped pbuf after creating a new datagram entry: remove the entry, too */
-    LWIP_ASSERT("not firstalthough just enqueued", ipr == reassdatagrams);
- 800fd22:	4b13      	ldr	r3, [pc, #76]	; (800fd70 <ip4_reass+0x330>)
- 800fd24:	681b      	ldr	r3, [r3, #0]
- 800fd26:	6b3a      	ldr	r2, [r7, #48]	; 0x30
- 800fd28:	429a      	cmp	r2, r3
- 800fd2a:	d006      	beq.n	800fd3a <ip4_reass+0x2fa>
- 800fd2c:	4b0d      	ldr	r3, [pc, #52]	; (800fd64 <ip4_reass+0x324>)
- 800fd2e:	f240 22ab 	movw	r2, #683	; 0x2ab
- 800fd32:	4910      	ldr	r1, [pc, #64]	; (800fd74 <ip4_reass+0x334>)
- 800fd34:	480d      	ldr	r0, [pc, #52]	; (800fd6c <ip4_reass+0x32c>)
- 800fd36:	f000 ff47 	bl	8010bc8 <iprintf>
-    ip_reass_dequeue_datagram(ipr, NULL);
- 800fd3a:	2100      	movs	r1, #0
- 800fd3c:	6b38      	ldr	r0, [r7, #48]	; 0x30
- 800fd3e:	f7ff fce7 	bl	800f710 <ip_reass_dequeue_datagram>
- 800fd42:	e006      	b.n	800fd52 <ip4_reass+0x312>
-    goto nullreturn;
- 800fd44:	bf00      	nop
- 800fd46:	e004      	b.n	800fd52 <ip4_reass+0x312>
-    goto nullreturn;
- 800fd48:	bf00      	nop
- 800fd4a:	e002      	b.n	800fd52 <ip4_reass+0x312>
-      goto nullreturn;
- 800fd4c:	bf00      	nop
- 800fd4e:	e000      	b.n	800fd52 <ip4_reass+0x312>
-  }
-
-nullreturn:
- 800fd50:	bf00      	nop
-  LWIP_DEBUGF(IP_REASS_DEBUG, ("ip4_reass: nullreturn\n"));
-  IPFRAG_STATS_INC(ip_frag.drop);
-  pbuf_free(p);
- 800fd52:	6878      	ldr	r0, [r7, #4]
- 800fd54:	f7f7 f93e 	bl	8006fd4 <pbuf_free>
-  return NULL;
- 800fd58:	2300      	movs	r3, #0
-}
- 800fd5a:	4618      	mov	r0, r3
- 800fd5c:	3738      	adds	r7, #56	; 0x38
- 800fd5e:	46bd      	mov	sp, r7
- 800fd60:	bd80      	pop	{r7, pc}
- 800fd62:	bf00      	nop
- 800fd64:	080149bc 	.word	0x080149bc
- 800fd68:	08014b48 	.word	0x08014b48
- 800fd6c:	08014a04 	.word	0x08014a04
- 800fd70:	24007cc4 	.word	0x24007cc4
- 800fd74:	08014b54 	.word	0x08014b54
-
-0800fd78 <ip_frag_alloc_pbuf_custom_ref>:
-#if IP_FRAG
-#if !LWIP_NETIF_TX_SINGLE_PBUF
-/** Allocate a new struct pbuf_custom_ref */
-static struct pbuf_custom_ref *
-ip_frag_alloc_pbuf_custom_ref(void)
-{
- 800fd78:	b580      	push	{r7, lr}
- 800fd7a:	af00      	add	r7, sp, #0
-  return (struct pbuf_custom_ref *)memp_malloc(MEMP_FRAG_PBUF);
- 800fd7c:	2005      	movs	r0, #5
- 800fd7e:	f7f6 f94d 	bl	800601c <memp_malloc>
- 800fd82:	4603      	mov	r3, r0
-}
- 800fd84:	4618      	mov	r0, r3
- 800fd86:	bd80      	pop	{r7, pc}
-
-0800fd88 <ip_frag_free_pbuf_custom_ref>:
-
-/** Free a struct pbuf_custom_ref */
-static void
-ip_frag_free_pbuf_custom_ref(struct pbuf_custom_ref *p)
-{
- 800fd88:	b580      	push	{r7, lr}
- 800fd8a:	b082      	sub	sp, #8
- 800fd8c:	af00      	add	r7, sp, #0
- 800fd8e:	6078      	str	r0, [r7, #4]
-  LWIP_ASSERT("p != NULL", p != NULL);
- 800fd90:	687b      	ldr	r3, [r7, #4]
- 800fd92:	2b00      	cmp	r3, #0
- 800fd94:	d106      	bne.n	800fda4 <ip_frag_free_pbuf_custom_ref+0x1c>
- 800fd96:	4b07      	ldr	r3, [pc, #28]	; (800fdb4 <ip_frag_free_pbuf_custom_ref+0x2c>)
- 800fd98:	f44f 7231 	mov.w	r2, #708	; 0x2c4
- 800fd9c:	4906      	ldr	r1, [pc, #24]	; (800fdb8 <ip_frag_free_pbuf_custom_ref+0x30>)
- 800fd9e:	4807      	ldr	r0, [pc, #28]	; (800fdbc <ip_frag_free_pbuf_custom_ref+0x34>)
- 800fda0:	f000 ff12 	bl	8010bc8 <iprintf>
-  memp_free(MEMP_FRAG_PBUF, p);
- 800fda4:	6879      	ldr	r1, [r7, #4]
- 800fda6:	2005      	movs	r0, #5
- 800fda8:	f7f6 f9a8 	bl	80060fc <memp_free>
-}
- 800fdac:	bf00      	nop
- 800fdae:	3708      	adds	r7, #8
- 800fdb0:	46bd      	mov	sp, r7
- 800fdb2:	bd80      	pop	{r7, pc}
- 800fdb4:	080149bc 	.word	0x080149bc
- 800fdb8:	08014b74 	.word	0x08014b74
- 800fdbc:	08014a04 	.word	0x08014a04
-
-0800fdc0 <ipfrag_free_pbuf_custom>:
-
-/** Free-callback function to free a 'struct pbuf_custom_ref', called by
- * pbuf_free. */
-static void
-ipfrag_free_pbuf_custom(struct pbuf *p)
-{
- 800fdc0:	b580      	push	{r7, lr}
- 800fdc2:	b084      	sub	sp, #16
- 800fdc4:	af00      	add	r7, sp, #0
- 800fdc6:	6078      	str	r0, [r7, #4]
-  struct pbuf_custom_ref *pcr = (struct pbuf_custom_ref *)p;
- 800fdc8:	687b      	ldr	r3, [r7, #4]
- 800fdca:	60fb      	str	r3, [r7, #12]
-  LWIP_ASSERT("pcr != NULL", pcr != NULL);
- 800fdcc:	68fb      	ldr	r3, [r7, #12]
- 800fdce:	2b00      	cmp	r3, #0
- 800fdd0:	d106      	bne.n	800fde0 <ipfrag_free_pbuf_custom+0x20>
- 800fdd2:	4b11      	ldr	r3, [pc, #68]	; (800fe18 <ipfrag_free_pbuf_custom+0x58>)
- 800fdd4:	f240 22ce 	movw	r2, #718	; 0x2ce
- 800fdd8:	4910      	ldr	r1, [pc, #64]	; (800fe1c <ipfrag_free_pbuf_custom+0x5c>)
- 800fdda:	4811      	ldr	r0, [pc, #68]	; (800fe20 <ipfrag_free_pbuf_custom+0x60>)
- 800fddc:	f000 fef4 	bl	8010bc8 <iprintf>
-  LWIP_ASSERT("pcr == p", (void *)pcr == (void *)p);
- 800fde0:	68fa      	ldr	r2, [r7, #12]
- 800fde2:	687b      	ldr	r3, [r7, #4]
- 800fde4:	429a      	cmp	r2, r3
- 800fde6:	d006      	beq.n	800fdf6 <ipfrag_free_pbuf_custom+0x36>
- 800fde8:	4b0b      	ldr	r3, [pc, #44]	; (800fe18 <ipfrag_free_pbuf_custom+0x58>)
- 800fdea:	f240 22cf 	movw	r2, #719	; 0x2cf
- 800fdee:	490d      	ldr	r1, [pc, #52]	; (800fe24 <ipfrag_free_pbuf_custom+0x64>)
- 800fdf0:	480b      	ldr	r0, [pc, #44]	; (800fe20 <ipfrag_free_pbuf_custom+0x60>)
- 800fdf2:	f000 fee9 	bl	8010bc8 <iprintf>
-  if (pcr->original != NULL) {
- 800fdf6:	68fb      	ldr	r3, [r7, #12]
- 800fdf8:	695b      	ldr	r3, [r3, #20]
- 800fdfa:	2b00      	cmp	r3, #0
- 800fdfc:	d004      	beq.n	800fe08 <ipfrag_free_pbuf_custom+0x48>
-    pbuf_free(pcr->original);
- 800fdfe:	68fb      	ldr	r3, [r7, #12]
- 800fe00:	695b      	ldr	r3, [r3, #20]
- 800fe02:	4618      	mov	r0, r3
- 800fe04:	f7f7 f8e6 	bl	8006fd4 <pbuf_free>
-  }
-  ip_frag_free_pbuf_custom_ref(pcr);
- 800fe08:	68f8      	ldr	r0, [r7, #12]
- 800fe0a:	f7ff ffbd 	bl	800fd88 <ip_frag_free_pbuf_custom_ref>
-}
- 800fe0e:	bf00      	nop
- 800fe10:	3710      	adds	r7, #16
- 800fe12:	46bd      	mov	sp, r7
- 800fe14:	bd80      	pop	{r7, pc}
- 800fe16:	bf00      	nop
- 800fe18:	080149bc 	.word	0x080149bc
- 800fe1c:	08014b80 	.word	0x08014b80
- 800fe20:	08014a04 	.word	0x08014a04
- 800fe24:	08014b8c 	.word	0x08014b8c
-
-0800fe28 <ip4_frag>:
- *
- * @return ERR_OK if sent successfully, err_t otherwise
- */
-err_t
-ip4_frag(struct pbuf *p, struct netif *netif, const ip4_addr_t *dest)
-{
- 800fe28:	b580      	push	{r7, lr}
- 800fe2a:	b094      	sub	sp, #80	; 0x50
- 800fe2c:	af02      	add	r7, sp, #8
- 800fe2e:	60f8      	str	r0, [r7, #12]
- 800fe30:	60b9      	str	r1, [r7, #8]
- 800fe32:	607a      	str	r2, [r7, #4]
-  struct pbuf *rambuf;
-#if !LWIP_NETIF_TX_SINGLE_PBUF
-  struct pbuf *newpbuf;
-  u16_t newpbuflen = 0;
- 800fe34:	2300      	movs	r3, #0
- 800fe36:	f8a7 3046 	strh.w	r3, [r7, #70]	; 0x46
-  u16_t left_to_copy;
-#endif
-  struct ip_hdr *original_iphdr;
-  struct ip_hdr *iphdr;
-  const u16_t nfb = (u16_t)((netif->mtu - IP_HLEN) / 8);
- 800fe3a:	68bb      	ldr	r3, [r7, #8]
- 800fe3c:	8c9b      	ldrh	r3, [r3, #36]	; 0x24
- 800fe3e:	3b14      	subs	r3, #20
- 800fe40:	2b00      	cmp	r3, #0
- 800fe42:	da00      	bge.n	800fe46 <ip4_frag+0x1e>
- 800fe44:	3307      	adds	r3, #7
- 800fe46:	10db      	asrs	r3, r3, #3
- 800fe48:	877b      	strh	r3, [r7, #58]	; 0x3a
-  u16_t left, fragsize;
-  u16_t ofo;
-  int last;
-  u16_t poff = IP_HLEN;
- 800fe4a:	2314      	movs	r3, #20
- 800fe4c:	87fb      	strh	r3, [r7, #62]	; 0x3e
-  u16_t tmp;
-  int mf_set;
-
-  original_iphdr = (struct ip_hdr *)p->payload;
- 800fe4e:	68fb      	ldr	r3, [r7, #12]
- 800fe50:	685b      	ldr	r3, [r3, #4]
- 800fe52:	637b      	str	r3, [r7, #52]	; 0x34
-  iphdr = original_iphdr;
- 800fe54:	6b7b      	ldr	r3, [r7, #52]	; 0x34
- 800fe56:	633b      	str	r3, [r7, #48]	; 0x30
-  if (IPH_HL_BYTES(iphdr) != IP_HLEN) {
- 800fe58:	6b3b      	ldr	r3, [r7, #48]	; 0x30
- 800fe5a:	781b      	ldrb	r3, [r3, #0]
- 800fe5c:	f003 030f 	and.w	r3, r3, #15
- 800fe60:	b2db      	uxtb	r3, r3
- 800fe62:	009b      	lsls	r3, r3, #2
- 800fe64:	b2db      	uxtb	r3, r3
- 800fe66:	2b14      	cmp	r3, #20
- 800fe68:	d002      	beq.n	800fe70 <ip4_frag+0x48>
-    /* ip4_frag() does not support IP options */
-    return ERR_VAL;
- 800fe6a:	f06f 0305 	mvn.w	r3, #5
- 800fe6e:	e110      	b.n	8010092 <ip4_frag+0x26a>
-  }
-  LWIP_ERROR("ip4_frag(): pbuf too short", p->len >= IP_HLEN, return ERR_VAL);
- 800fe70:	68fb      	ldr	r3, [r7, #12]
- 800fe72:	895b      	ldrh	r3, [r3, #10]
- 800fe74:	2b13      	cmp	r3, #19
- 800fe76:	d809      	bhi.n	800fe8c <ip4_frag+0x64>
- 800fe78:	4b88      	ldr	r3, [pc, #544]	; (801009c <ip4_frag+0x274>)
- 800fe7a:	f44f 723f 	mov.w	r2, #764	; 0x2fc
- 800fe7e:	4988      	ldr	r1, [pc, #544]	; (80100a0 <ip4_frag+0x278>)
- 800fe80:	4888      	ldr	r0, [pc, #544]	; (80100a4 <ip4_frag+0x27c>)
- 800fe82:	f000 fea1 	bl	8010bc8 <iprintf>
- 800fe86:	f06f 0305 	mvn.w	r3, #5
- 800fe8a:	e102      	b.n	8010092 <ip4_frag+0x26a>
-
-  /* Save original offset */
-  tmp = lwip_ntohs(IPH_OFFSET(iphdr));
- 800fe8c:	6b3b      	ldr	r3, [r7, #48]	; 0x30
- 800fe8e:	88db      	ldrh	r3, [r3, #6]
- 800fe90:	b29b      	uxth	r3, r3
- 800fe92:	4618      	mov	r0, r3
- 800fe94:	f7f5 fb5a 	bl	800554c <lwip_htons>
- 800fe98:	4603      	mov	r3, r0
- 800fe9a:	87bb      	strh	r3, [r7, #60]	; 0x3c
-  ofo = tmp & IP_OFFMASK;
- 800fe9c:	8fbb      	ldrh	r3, [r7, #60]	; 0x3c
- 800fe9e:	f3c3 030c 	ubfx	r3, r3, #0, #13
- 800fea2:	f8a7 3040 	strh.w	r3, [r7, #64]	; 0x40
-  /* already fragmented? if so, the last fragment we create must have MF, too */
-  mf_set = tmp & IP_MF;
- 800fea6:	8fbb      	ldrh	r3, [r7, #60]	; 0x3c
- 800fea8:	f403 5300 	and.w	r3, r3, #8192	; 0x2000
- 800feac:	62fb      	str	r3, [r7, #44]	; 0x2c
-
-  left = (u16_t)(p->tot_len - IP_HLEN);
- 800feae:	68fb      	ldr	r3, [r7, #12]
- 800feb0:	891b      	ldrh	r3, [r3, #8]
- 800feb2:	3b14      	subs	r3, #20
- 800feb4:	f8a7 3042 	strh.w	r3, [r7, #66]	; 0x42
-
-  while (left) {
- 800feb8:	e0e1      	b.n	801007e <ip4_frag+0x256>
-    /* Fill this fragment */
-    fragsize = LWIP_MIN(left, (u16_t)(nfb * 8));
- 800feba:	8f7b      	ldrh	r3, [r7, #58]	; 0x3a
- 800febc:	00db      	lsls	r3, r3, #3
- 800febe:	b29b      	uxth	r3, r3
- 800fec0:	f8b7 2042 	ldrh.w	r2, [r7, #66]	; 0x42
- 800fec4:	4293      	cmp	r3, r2
- 800fec6:	bf28      	it	cs
- 800fec8:	4613      	movcs	r3, r2
- 800feca:	857b      	strh	r3, [r7, #42]	; 0x2a
-    /* When not using a static buffer, create a chain of pbufs.
-     * The first will be a PBUF_RAM holding the link and IP header.
-     * The rest will be PBUF_REFs mirroring the pbuf chain to be fragged,
-     * but limited to the size of an mtu.
-     */
-    rambuf = pbuf_alloc(PBUF_LINK, IP_HLEN, PBUF_RAM);
- 800fecc:	f44f 7220 	mov.w	r2, #640	; 0x280
- 800fed0:	2114      	movs	r1, #20
- 800fed2:	200e      	movs	r0, #14
- 800fed4:	f7f6 fd9a 	bl	8006a0c <pbuf_alloc>
- 800fed8:	6278      	str	r0, [r7, #36]	; 0x24
-    if (rambuf == NULL) {
- 800feda:	6a7b      	ldr	r3, [r7, #36]	; 0x24
- 800fedc:	2b00      	cmp	r3, #0
- 800fede:	f000 80d5 	beq.w	801008c <ip4_frag+0x264>
-      goto memerr;
-    }
-    LWIP_ASSERT("this needs a pbuf in one piece!",
- 800fee2:	6a7b      	ldr	r3, [r7, #36]	; 0x24
- 800fee4:	895b      	ldrh	r3, [r3, #10]
- 800fee6:	2b13      	cmp	r3, #19
- 800fee8:	d806      	bhi.n	800fef8 <ip4_frag+0xd0>
- 800feea:	4b6c      	ldr	r3, [pc, #432]	; (801009c <ip4_frag+0x274>)
- 800feec:	f44f 7249 	mov.w	r2, #804	; 0x324
- 800fef0:	496d      	ldr	r1, [pc, #436]	; (80100a8 <ip4_frag+0x280>)
- 800fef2:	486c      	ldr	r0, [pc, #432]	; (80100a4 <ip4_frag+0x27c>)
- 800fef4:	f000 fe68 	bl	8010bc8 <iprintf>
-                (rambuf->len >= (IP_HLEN)));
-    SMEMCPY(rambuf->payload, original_iphdr, IP_HLEN);
- 800fef8:	6a7b      	ldr	r3, [r7, #36]	; 0x24
- 800fefa:	685b      	ldr	r3, [r3, #4]
- 800fefc:	2214      	movs	r2, #20
- 800fefe:	6b79      	ldr	r1, [r7, #52]	; 0x34
- 800ff00:	4618      	mov	r0, r3
- 800ff02:	f001 f842 	bl	8010f8a <memcpy>
-    iphdr = (struct ip_hdr *)rambuf->payload;
- 800ff06:	6a7b      	ldr	r3, [r7, #36]	; 0x24
- 800ff08:	685b      	ldr	r3, [r3, #4]
- 800ff0a:	633b      	str	r3, [r7, #48]	; 0x30
-
-    left_to_copy = fragsize;
- 800ff0c:	8d7b      	ldrh	r3, [r7, #42]	; 0x2a
- 800ff0e:	f8a7 3044 	strh.w	r3, [r7, #68]	; 0x44
-    while (left_to_copy) {
- 800ff12:	e064      	b.n	800ffde <ip4_frag+0x1b6>
-      struct pbuf_custom_ref *pcr;
-      u16_t plen = (u16_t)(p->len - poff);
- 800ff14:	68fb      	ldr	r3, [r7, #12]
- 800ff16:	895a      	ldrh	r2, [r3, #10]
- 800ff18:	8ffb      	ldrh	r3, [r7, #62]	; 0x3e
- 800ff1a:	1ad3      	subs	r3, r2, r3
- 800ff1c:	83fb      	strh	r3, [r7, #30]
-      LWIP_ASSERT("p->len >= poff", p->len >= poff);
- 800ff1e:	68fb      	ldr	r3, [r7, #12]
- 800ff20:	895b      	ldrh	r3, [r3, #10]
- 800ff22:	8ffa      	ldrh	r2, [r7, #62]	; 0x3e
- 800ff24:	429a      	cmp	r2, r3
- 800ff26:	d906      	bls.n	800ff36 <ip4_frag+0x10e>
- 800ff28:	4b5c      	ldr	r3, [pc, #368]	; (801009c <ip4_frag+0x274>)
- 800ff2a:	f240 322d 	movw	r2, #813	; 0x32d
- 800ff2e:	495f      	ldr	r1, [pc, #380]	; (80100ac <ip4_frag+0x284>)
- 800ff30:	485c      	ldr	r0, [pc, #368]	; (80100a4 <ip4_frag+0x27c>)
- 800ff32:	f000 fe49 	bl	8010bc8 <iprintf>
-      newpbuflen = LWIP_MIN(left_to_copy, plen);
- 800ff36:	8bfa      	ldrh	r2, [r7, #30]
- 800ff38:	f8b7 3044 	ldrh.w	r3, [r7, #68]	; 0x44
- 800ff3c:	4293      	cmp	r3, r2
- 800ff3e:	bf28      	it	cs
- 800ff40:	4613      	movcs	r3, r2
- 800ff42:	f8a7 3046 	strh.w	r3, [r7, #70]	; 0x46
-      /* Is this pbuf already empty? */
-      if (!newpbuflen) {
- 800ff46:	f8b7 3046 	ldrh.w	r3, [r7, #70]	; 0x46
- 800ff4a:	2b00      	cmp	r3, #0
- 800ff4c:	d105      	bne.n	800ff5a <ip4_frag+0x132>
-        poff = 0;
- 800ff4e:	2300      	movs	r3, #0
- 800ff50:	87fb      	strh	r3, [r7, #62]	; 0x3e
-        p = p->next;
- 800ff52:	68fb      	ldr	r3, [r7, #12]
- 800ff54:	681b      	ldr	r3, [r3, #0]
- 800ff56:	60fb      	str	r3, [r7, #12]
-        continue;
- 800ff58:	e041      	b.n	800ffde <ip4_frag+0x1b6>
-      }
-      pcr = ip_frag_alloc_pbuf_custom_ref();
- 800ff5a:	f7ff ff0d 	bl	800fd78 <ip_frag_alloc_pbuf_custom_ref>
- 800ff5e:	61b8      	str	r0, [r7, #24]
-      if (pcr == NULL) {
- 800ff60:	69bb      	ldr	r3, [r7, #24]
- 800ff62:	2b00      	cmp	r3, #0
- 800ff64:	d103      	bne.n	800ff6e <ip4_frag+0x146>
-        pbuf_free(rambuf);
- 800ff66:	6a78      	ldr	r0, [r7, #36]	; 0x24
- 800ff68:	f7f7 f834 	bl	8006fd4 <pbuf_free>
-        goto memerr;
- 800ff6c:	e08f      	b.n	801008e <ip4_frag+0x266>
-      }
-      /* Mirror this pbuf, although we might not need all of it. */
-      newpbuf = pbuf_alloced_custom(PBUF_RAW, newpbuflen, PBUF_REF, &pcr->pc,
- 800ff6e:	69b8      	ldr	r0, [r7, #24]
-                                    (u8_t *)p->payload + poff, newpbuflen);
- 800ff70:	68fb      	ldr	r3, [r7, #12]
- 800ff72:	685a      	ldr	r2, [r3, #4]
-      newpbuf = pbuf_alloced_custom(PBUF_RAW, newpbuflen, PBUF_REF, &pcr->pc,
- 800ff74:	8ffb      	ldrh	r3, [r7, #62]	; 0x3e
- 800ff76:	4413      	add	r3, r2
- 800ff78:	f8b7 1046 	ldrh.w	r1, [r7, #70]	; 0x46
- 800ff7c:	f8b7 2046 	ldrh.w	r2, [r7, #70]	; 0x46
- 800ff80:	9201      	str	r2, [sp, #4]
- 800ff82:	9300      	str	r3, [sp, #0]
- 800ff84:	4603      	mov	r3, r0
- 800ff86:	2241      	movs	r2, #65	; 0x41
- 800ff88:	2000      	movs	r0, #0
- 800ff8a:	f7f6 fe69 	bl	8006c60 <pbuf_alloced_custom>
- 800ff8e:	6178      	str	r0, [r7, #20]
-      if (newpbuf == NULL) {
- 800ff90:	697b      	ldr	r3, [r7, #20]
- 800ff92:	2b00      	cmp	r3, #0
- 800ff94:	d106      	bne.n	800ffa4 <ip4_frag+0x17c>
-        ip_frag_free_pbuf_custom_ref(pcr);
- 800ff96:	69b8      	ldr	r0, [r7, #24]
- 800ff98:	f7ff fef6 	bl	800fd88 <ip_frag_free_pbuf_custom_ref>
-        pbuf_free(rambuf);
- 800ff9c:	6a78      	ldr	r0, [r7, #36]	; 0x24
- 800ff9e:	f7f7 f819 	bl	8006fd4 <pbuf_free>
-        goto memerr;
- 800ffa2:	e074      	b.n	801008e <ip4_frag+0x266>
-      }
-      pbuf_ref(p);
- 800ffa4:	68f8      	ldr	r0, [r7, #12]
- 800ffa6:	f7f7 f8b5 	bl	8007114 <pbuf_ref>
-      pcr->original = p;
- 800ffaa:	69bb      	ldr	r3, [r7, #24]
- 800ffac:	68fa      	ldr	r2, [r7, #12]
- 800ffae:	615a      	str	r2, [r3, #20]
-      pcr->pc.custom_free_function = ipfrag_free_pbuf_custom;
- 800ffb0:	69bb      	ldr	r3, [r7, #24]
- 800ffb2:	4a3f      	ldr	r2, [pc, #252]	; (80100b0 <ip4_frag+0x288>)
- 800ffb4:	611a      	str	r2, [r3, #16]
-
-      /* Add it to end of rambuf's chain, but using pbuf_cat, not pbuf_chain
-       * so that it is removed when pbuf_dechain is later called on rambuf.
-       */
-      pbuf_cat(rambuf, newpbuf);
- 800ffb6:	6979      	ldr	r1, [r7, #20]
- 800ffb8:	6a78      	ldr	r0, [r7, #36]	; 0x24
- 800ffba:	f7f7 f8cd 	bl	8007158 <pbuf_cat>
-      left_to_copy = (u16_t)(left_to_copy - newpbuflen);
- 800ffbe:	f8b7 2044 	ldrh.w	r2, [r7, #68]	; 0x44
- 800ffc2:	f8b7 3046 	ldrh.w	r3, [r7, #70]	; 0x46
- 800ffc6:	1ad3      	subs	r3, r2, r3
- 800ffc8:	f8a7 3044 	strh.w	r3, [r7, #68]	; 0x44
-      if (left_to_copy) {
- 800ffcc:	f8b7 3044 	ldrh.w	r3, [r7, #68]	; 0x44
- 800ffd0:	2b00      	cmp	r3, #0
- 800ffd2:	d004      	beq.n	800ffde <ip4_frag+0x1b6>
-        poff = 0;
- 800ffd4:	2300      	movs	r3, #0
- 800ffd6:	87fb      	strh	r3, [r7, #62]	; 0x3e
-        p = p->next;
- 800ffd8:	68fb      	ldr	r3, [r7, #12]
- 800ffda:	681b      	ldr	r3, [r3, #0]
- 800ffdc:	60fb      	str	r3, [r7, #12]
-    while (left_to_copy) {
- 800ffde:	f8b7 3044 	ldrh.w	r3, [r7, #68]	; 0x44
- 800ffe2:	2b00      	cmp	r3, #0
- 800ffe4:	d196      	bne.n	800ff14 <ip4_frag+0xec>
-      }
-    }
-    poff = (u16_t)(poff + newpbuflen);
- 800ffe6:	8ffa      	ldrh	r2, [r7, #62]	; 0x3e
- 800ffe8:	f8b7 3046 	ldrh.w	r3, [r7, #70]	; 0x46
- 800ffec:	4413      	add	r3, r2
- 800ffee:	87fb      	strh	r3, [r7, #62]	; 0x3e
-#endif /* LWIP_NETIF_TX_SINGLE_PBUF */
-
-    /* Correct header */
-    last = (left <= netif->mtu - IP_HLEN);
- 800fff0:	68bb      	ldr	r3, [r7, #8]
- 800fff2:	8c9b      	ldrh	r3, [r3, #36]	; 0x24
- 800fff4:	f1a3 0213 	sub.w	r2, r3, #19
- 800fff8:	f8b7 3042 	ldrh.w	r3, [r7, #66]	; 0x42
- 800fffc:	429a      	cmp	r2, r3
- 800fffe:	bfcc      	ite	gt
- 8010000:	2301      	movgt	r3, #1
- 8010002:	2300      	movle	r3, #0
- 8010004:	b2db      	uxtb	r3, r3
- 8010006:	623b      	str	r3, [r7, #32]
-
-    /* Set new offset and MF flag */
-    tmp = (IP_OFFMASK & (ofo));
- 8010008:	f8b7 3040 	ldrh.w	r3, [r7, #64]	; 0x40
- 801000c:	f3c3 030c 	ubfx	r3, r3, #0, #13
- 8010010:	87bb      	strh	r3, [r7, #60]	; 0x3c
-    if (!last || mf_set) {
- 8010012:	6a3b      	ldr	r3, [r7, #32]
- 8010014:	2b00      	cmp	r3, #0
- 8010016:	d002      	beq.n	801001e <ip4_frag+0x1f6>
- 8010018:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 801001a:	2b00      	cmp	r3, #0
- 801001c:	d003      	beq.n	8010026 <ip4_frag+0x1fe>
-      /* the last fragment has MF set if the input frame had it */
-      tmp = tmp | IP_MF;
- 801001e:	8fbb      	ldrh	r3, [r7, #60]	; 0x3c
- 8010020:	f443 5300 	orr.w	r3, r3, #8192	; 0x2000
- 8010024:	87bb      	strh	r3, [r7, #60]	; 0x3c
-    }
-    IPH_OFFSET_SET(iphdr, lwip_htons(tmp));
- 8010026:	8fbb      	ldrh	r3, [r7, #60]	; 0x3c
- 8010028:	4618      	mov	r0, r3
- 801002a:	f7f5 fa8f 	bl	800554c <lwip_htons>
- 801002e:	4603      	mov	r3, r0
- 8010030:	461a      	mov	r2, r3
- 8010032:	6b3b      	ldr	r3, [r7, #48]	; 0x30
- 8010034:	80da      	strh	r2, [r3, #6]
-    IPH_LEN_SET(iphdr, lwip_htons((u16_t)(fragsize + IP_HLEN)));
- 8010036:	8d7b      	ldrh	r3, [r7, #42]	; 0x2a
- 8010038:	3314      	adds	r3, #20
- 801003a:	b29b      	uxth	r3, r3
- 801003c:	4618      	mov	r0, r3
- 801003e:	f7f5 fa85 	bl	800554c <lwip_htons>
- 8010042:	4603      	mov	r3, r0
- 8010044:	461a      	mov	r2, r3
- 8010046:	6b3b      	ldr	r3, [r7, #48]	; 0x30
- 8010048:	805a      	strh	r2, [r3, #2]
-    IPH_CHKSUM_SET(iphdr, 0);
- 801004a:	6b3b      	ldr	r3, [r7, #48]	; 0x30
- 801004c:	2200      	movs	r2, #0
- 801004e:	729a      	strb	r2, [r3, #10]
- 8010050:	2200      	movs	r2, #0
- 8010052:	72da      	strb	r2, [r3, #11]
-#endif /* CHECKSUM_GEN_IP */
-
-    /* No need for separate header pbuf - we allowed room for it in rambuf
-     * when allocated.
-     */
-    netif->output(netif, rambuf, dest);
- 8010054:	68bb      	ldr	r3, [r7, #8]
- 8010056:	695b      	ldr	r3, [r3, #20]
- 8010058:	687a      	ldr	r2, [r7, #4]
- 801005a:	6a79      	ldr	r1, [r7, #36]	; 0x24
- 801005c:	68b8      	ldr	r0, [r7, #8]
- 801005e:	4798      	blx	r3
-     * recreate it next time round the loop. If we're lucky the hardware
-     * will have already sent the packet, the free will really free, and
-     * there will be zero memory penalty.
-     */
-
-    pbuf_free(rambuf);
- 8010060:	6a78      	ldr	r0, [r7, #36]	; 0x24
- 8010062:	f7f6 ffb7 	bl	8006fd4 <pbuf_free>
-    left = (u16_t)(left - fragsize);
- 8010066:	f8b7 2042 	ldrh.w	r2, [r7, #66]	; 0x42
- 801006a:	8d7b      	ldrh	r3, [r7, #42]	; 0x2a
- 801006c:	1ad3      	subs	r3, r2, r3
- 801006e:	f8a7 3042 	strh.w	r3, [r7, #66]	; 0x42
-    ofo = (u16_t)(ofo + nfb);
- 8010072:	f8b7 2040 	ldrh.w	r2, [r7, #64]	; 0x40
- 8010076:	8f7b      	ldrh	r3, [r7, #58]	; 0x3a
- 8010078:	4413      	add	r3, r2
- 801007a:	f8a7 3040 	strh.w	r3, [r7, #64]	; 0x40
-  while (left) {
- 801007e:	f8b7 3042 	ldrh.w	r3, [r7, #66]	; 0x42
- 8010082:	2b00      	cmp	r3, #0
- 8010084:	f47f af19 	bne.w	800feba <ip4_frag+0x92>
-  }
-  MIB2_STATS_INC(mib2.ipfragoks);
-  return ERR_OK;
- 8010088:	2300      	movs	r3, #0
- 801008a:	e002      	b.n	8010092 <ip4_frag+0x26a>
-      goto memerr;
- 801008c:	bf00      	nop
-memerr:
-  MIB2_STATS_INC(mib2.ipfragfails);
-  return ERR_MEM;
- 801008e:	f04f 33ff 	mov.w	r3, #4294967295
-}
- 8010092:	4618      	mov	r0, r3
- 8010094:	3748      	adds	r7, #72	; 0x48
- 8010096:	46bd      	mov	sp, r7
- 8010098:	bd80      	pop	{r7, pc}
- 801009a:	bf00      	nop
- 801009c:	080149bc 	.word	0x080149bc
- 80100a0:	08014b98 	.word	0x08014b98
- 80100a4:	08014a04 	.word	0x08014a04
- 80100a8:	08014bb4 	.word	0x08014bb4
- 80100ac:	08014bd4 	.word	0x08014bd4
- 80100b0:	0800fdc1 	.word	0x0800fdc1
-
-080100b4 <ethernet_input>:
- * @see ETHARP_SUPPORT_VLAN
- * @see LWIP_HOOK_VLAN_CHECK
- */
-err_t
-ethernet_input(struct pbuf *p, struct netif *netif)
-{
- 80100b4:	b580      	push	{r7, lr}
- 80100b6:	b086      	sub	sp, #24
- 80100b8:	af00      	add	r7, sp, #0
- 80100ba:	6078      	str	r0, [r7, #4]
- 80100bc:	6039      	str	r1, [r7, #0]
-  struct eth_hdr *ethhdr;
-  u16_t type;
-#if LWIP_ARP || ETHARP_SUPPORT_VLAN || LWIP_IPV6
-  u16_t next_hdr_offset = SIZEOF_ETH_HDR;
- 80100be:	230e      	movs	r3, #14
- 80100c0:	82fb      	strh	r3, [r7, #22]
-#endif /* LWIP_ARP || ETHARP_SUPPORT_VLAN */
-
-  LWIP_ASSERT_CORE_LOCKED();
-
-  if (p->len <= SIZEOF_ETH_HDR) {
- 80100c2:	687b      	ldr	r3, [r7, #4]
- 80100c4:	895b      	ldrh	r3, [r3, #10]
- 80100c6:	2b0e      	cmp	r3, #14
- 80100c8:	d96e      	bls.n	80101a8 <ethernet_input+0xf4>
-    ETHARP_STATS_INC(etharp.drop);
-    MIB2_STATS_NETIF_INC(netif, ifinerrors);
-    goto free_and_return;
-  }
-
-  if (p->if_idx == NETIF_NO_INDEX) {
- 80100ca:	687b      	ldr	r3, [r7, #4]
- 80100cc:	7bdb      	ldrb	r3, [r3, #15]
- 80100ce:	2b00      	cmp	r3, #0
- 80100d0:	d106      	bne.n	80100e0 <ethernet_input+0x2c>
-    p->if_idx = netif_get_index(netif);
- 80100d2:	683b      	ldr	r3, [r7, #0]
- 80100d4:	f893 3030 	ldrb.w	r3, [r3, #48]	; 0x30
- 80100d8:	3301      	adds	r3, #1
- 80100da:	b2da      	uxtb	r2, r3
- 80100dc:	687b      	ldr	r3, [r7, #4]
- 80100de:	73da      	strb	r2, [r3, #15]
-  }
-
-  /* points to packet payload, which starts with an Ethernet header */
-  ethhdr = (struct eth_hdr *)p->payload;
- 80100e0:	687b      	ldr	r3, [r7, #4]
- 80100e2:	685b      	ldr	r3, [r3, #4]
- 80100e4:	613b      	str	r3, [r7, #16]
-               (unsigned char)ethhdr->dest.addr[3], (unsigned char)ethhdr->dest.addr[4], (unsigned char)ethhdr->dest.addr[5],
-               (unsigned char)ethhdr->src.addr[0],  (unsigned char)ethhdr->src.addr[1],  (unsigned char)ethhdr->src.addr[2],
-               (unsigned char)ethhdr->src.addr[3],  (unsigned char)ethhdr->src.addr[4],  (unsigned char)ethhdr->src.addr[5],
-               lwip_htons(ethhdr->type)));
-
-  type = ethhdr->type;
- 80100e6:	693b      	ldr	r3, [r7, #16]
- 80100e8:	7b1a      	ldrb	r2, [r3, #12]
- 80100ea:	7b5b      	ldrb	r3, [r3, #13]
- 80100ec:	021b      	lsls	r3, r3, #8
- 80100ee:	4313      	orrs	r3, r2
- 80100f0:	81fb      	strh	r3, [r7, #14]
-
-#if LWIP_ARP_FILTER_NETIF
-  netif = LWIP_ARP_FILTER_NETIF_FN(p, netif, lwip_htons(type));
-#endif /* LWIP_ARP_FILTER_NETIF*/
-
-  if (ethhdr->dest.addr[0] & 1) {
- 80100f2:	693b      	ldr	r3, [r7, #16]
- 80100f4:	781b      	ldrb	r3, [r3, #0]
- 80100f6:	f003 0301 	and.w	r3, r3, #1
- 80100fa:	2b00      	cmp	r3, #0
- 80100fc:	d023      	beq.n	8010146 <ethernet_input+0x92>
-    /* this might be a multicast or broadcast packet */
-    if (ethhdr->dest.addr[0] == LL_IP4_MULTICAST_ADDR_0) {
- 80100fe:	693b      	ldr	r3, [r7, #16]
- 8010100:	781b      	ldrb	r3, [r3, #0]
- 8010102:	2b01      	cmp	r3, #1
- 8010104:	d10f      	bne.n	8010126 <ethernet_input+0x72>
-#if LWIP_IPV4
-      if ((ethhdr->dest.addr[1] == LL_IP4_MULTICAST_ADDR_1) &&
- 8010106:	693b      	ldr	r3, [r7, #16]
- 8010108:	785b      	ldrb	r3, [r3, #1]
- 801010a:	2b00      	cmp	r3, #0
- 801010c:	d11b      	bne.n	8010146 <ethernet_input+0x92>
-          (ethhdr->dest.addr[2] == LL_IP4_MULTICAST_ADDR_2)) {
- 801010e:	693b      	ldr	r3, [r7, #16]
- 8010110:	789b      	ldrb	r3, [r3, #2]
-      if ((ethhdr->dest.addr[1] == LL_IP4_MULTICAST_ADDR_1) &&
- 8010112:	2b5e      	cmp	r3, #94	; 0x5e
- 8010114:	d117      	bne.n	8010146 <ethernet_input+0x92>
-        /* mark the pbuf as link-layer multicast */
-        p->flags |= PBUF_FLAG_LLMCAST;
- 8010116:	687b      	ldr	r3, [r7, #4]
- 8010118:	7b5b      	ldrb	r3, [r3, #13]
- 801011a:	f043 0310 	orr.w	r3, r3, #16
- 801011e:	b2da      	uxtb	r2, r3
- 8010120:	687b      	ldr	r3, [r7, #4]
- 8010122:	735a      	strb	r2, [r3, #13]
- 8010124:	e00f      	b.n	8010146 <ethernet_input+0x92>
-             (ethhdr->dest.addr[1] == LL_IP6_MULTICAST_ADDR_1)) {
-      /* mark the pbuf as link-layer multicast */
-      p->flags |= PBUF_FLAG_LLMCAST;
-    }
-#endif /* LWIP_IPV6 */
-    else if (eth_addr_cmp(&ethhdr->dest, &ethbroadcast)) {
- 8010126:	693b      	ldr	r3, [r7, #16]
- 8010128:	2206      	movs	r2, #6
- 801012a:	4928      	ldr	r1, [pc, #160]	; (80101cc <ethernet_input+0x118>)
- 801012c:	4618      	mov	r0, r3
- 801012e:	f000 fe99 	bl	8010e64 <memcmp>
- 8010132:	4603      	mov	r3, r0
- 8010134:	2b00      	cmp	r3, #0
- 8010136:	d106      	bne.n	8010146 <ethernet_input+0x92>
-      /* mark the pbuf as link-layer broadcast */
-      p->flags |= PBUF_FLAG_LLBCAST;
- 8010138:	687b      	ldr	r3, [r7, #4]
- 801013a:	7b5b      	ldrb	r3, [r3, #13]
- 801013c:	f043 0308 	orr.w	r3, r3, #8
- 8010140:	b2da      	uxtb	r2, r3
- 8010142:	687b      	ldr	r3, [r7, #4]
- 8010144:	735a      	strb	r2, [r3, #13]
-    }
-  }
-
-  switch (type) {
- 8010146:	89fb      	ldrh	r3, [r7, #14]
- 8010148:	2b08      	cmp	r3, #8
- 801014a:	d003      	beq.n	8010154 <ethernet_input+0xa0>
- 801014c:	f5b3 6fc1 	cmp.w	r3, #1544	; 0x608
- 8010150:	d014      	beq.n	801017c <ethernet_input+0xc8>
-      }
-#endif
-      ETHARP_STATS_INC(etharp.proterr);
-      ETHARP_STATS_INC(etharp.drop);
-      MIB2_STATS_NETIF_INC(netif, ifinunknownprotos);
-      goto free_and_return;
- 8010152:	e032      	b.n	80101ba <ethernet_input+0x106>
-      if (!(netif->flags & NETIF_FLAG_ETHARP)) {
- 8010154:	683b      	ldr	r3, [r7, #0]
- 8010156:	f893 302d 	ldrb.w	r3, [r3, #45]	; 0x2d
- 801015a:	f003 0308 	and.w	r3, r3, #8
- 801015e:	2b00      	cmp	r3, #0
- 8010160:	d024      	beq.n	80101ac <ethernet_input+0xf8>
-      if (pbuf_remove_header(p, next_hdr_offset)) {
- 8010162:	8afb      	ldrh	r3, [r7, #22]
- 8010164:	4619      	mov	r1, r3
- 8010166:	6878      	ldr	r0, [r7, #4]
- 8010168:	f7f6 feae 	bl	8006ec8 <pbuf_remove_header>
- 801016c:	4603      	mov	r3, r0
- 801016e:	2b00      	cmp	r3, #0
- 8010170:	d11e      	bne.n	80101b0 <ethernet_input+0xfc>
-        ip4_input(p, netif);
- 8010172:	6839      	ldr	r1, [r7, #0]
- 8010174:	6878      	ldr	r0, [r7, #4]
- 8010176:	f7fe ff21 	bl	800efbc <ip4_input>
-      break;
- 801017a:	e013      	b.n	80101a4 <ethernet_input+0xf0>
-      if (!(netif->flags & NETIF_FLAG_ETHARP)) {
- 801017c:	683b      	ldr	r3, [r7, #0]
- 801017e:	f893 302d 	ldrb.w	r3, [r3, #45]	; 0x2d
- 8010182:	f003 0308 	and.w	r3, r3, #8
- 8010186:	2b00      	cmp	r3, #0
- 8010188:	d014      	beq.n	80101b4 <ethernet_input+0x100>
-      if (pbuf_remove_header(p, next_hdr_offset)) {
- 801018a:	8afb      	ldrh	r3, [r7, #22]
- 801018c:	4619      	mov	r1, r3
- 801018e:	6878      	ldr	r0, [r7, #4]
- 8010190:	f7f6 fe9a 	bl	8006ec8 <pbuf_remove_header>
- 8010194:	4603      	mov	r3, r0
- 8010196:	2b00      	cmp	r3, #0
- 8010198:	d10e      	bne.n	80101b8 <ethernet_input+0x104>
-        etharp_input(p, netif);
- 801019a:	6839      	ldr	r1, [r7, #0]
- 801019c:	6878      	ldr	r0, [r7, #4]
- 801019e:	f7fe f805 	bl	800e1ac <etharp_input>
-      break;
- 80101a2:	bf00      	nop
-  }
-
-  /* This means the pbuf is freed or consumed,
-     so the caller doesn't have to free it again */
-  return ERR_OK;
- 80101a4:	2300      	movs	r3, #0
- 80101a6:	e00c      	b.n	80101c2 <ethernet_input+0x10e>
-    goto free_and_return;
- 80101a8:	bf00      	nop
- 80101aa:	e006      	b.n	80101ba <ethernet_input+0x106>
-        goto free_and_return;
- 80101ac:	bf00      	nop
- 80101ae:	e004      	b.n	80101ba <ethernet_input+0x106>
-        goto free_and_return;
- 80101b0:	bf00      	nop
- 80101b2:	e002      	b.n	80101ba <ethernet_input+0x106>
-        goto free_and_return;
- 80101b4:	bf00      	nop
- 80101b6:	e000      	b.n	80101ba <ethernet_input+0x106>
-        goto free_and_return;
- 80101b8:	bf00      	nop
-
-free_and_return:
-  pbuf_free(p);
- 80101ba:	6878      	ldr	r0, [r7, #4]
- 80101bc:	f7f6 ff0a 	bl	8006fd4 <pbuf_free>
-  return ERR_OK;
- 80101c0:	2300      	movs	r3, #0
-}
- 80101c2:	4618      	mov	r0, r3
- 80101c4:	3718      	adds	r7, #24
- 80101c6:	46bd      	mov	sp, r7
- 80101c8:	bd80      	pop	{r7, pc}
- 80101ca:	bf00      	nop
- 80101cc:	08014d98 	.word	0x08014d98
-
-080101d0 <ethernet_output>:
- * @return ERR_OK if the packet was sent, any other err_t on failure
- */
-err_t
-ethernet_output(struct netif * netif, struct pbuf * p,
-                const struct eth_addr * src, const struct eth_addr * dst,
-                u16_t eth_type) {
- 80101d0:	b580      	push	{r7, lr}
- 80101d2:	b086      	sub	sp, #24
- 80101d4:	af00      	add	r7, sp, #0
- 80101d6:	60f8      	str	r0, [r7, #12]
- 80101d8:	60b9      	str	r1, [r7, #8]
- 80101da:	607a      	str	r2, [r7, #4]
- 80101dc:	603b      	str	r3, [r7, #0]
-  struct eth_hdr *ethhdr;
-  u16_t eth_type_be = lwip_htons(eth_type);
- 80101de:	8c3b      	ldrh	r3, [r7, #32]
- 80101e0:	4618      	mov	r0, r3
- 80101e2:	f7f5 f9b3 	bl	800554c <lwip_htons>
- 80101e6:	4603      	mov	r3, r0
- 80101e8:	82fb      	strh	r3, [r7, #22]
-
-    eth_type_be = PP_HTONS(ETHTYPE_VLAN);
-  } else
-#endif /* ETHARP_SUPPORT_VLAN && defined(LWIP_HOOK_VLAN_SET) */
-  {
-    if (pbuf_add_header(p, SIZEOF_ETH_HDR) != 0) {
- 80101ea:	210e      	movs	r1, #14
- 80101ec:	68b8      	ldr	r0, [r7, #8]
- 80101ee:	f7f6 fe5b 	bl	8006ea8 <pbuf_add_header>
- 80101f2:	4603      	mov	r3, r0
- 80101f4:	2b00      	cmp	r3, #0
- 80101f6:	d125      	bne.n	8010244 <ethernet_output+0x74>
-    }
-  }
-
-  LWIP_ASSERT_CORE_LOCKED();
-
-  ethhdr = (struct eth_hdr *)p->payload;
- 80101f8:	68bb      	ldr	r3, [r7, #8]
- 80101fa:	685b      	ldr	r3, [r3, #4]
- 80101fc:	613b      	str	r3, [r7, #16]
-  ethhdr->type = eth_type_be;
- 80101fe:	693b      	ldr	r3, [r7, #16]
- 8010200:	8afa      	ldrh	r2, [r7, #22]
- 8010202:	819a      	strh	r2, [r3, #12]
-  SMEMCPY(&ethhdr->dest, dst, ETH_HWADDR_LEN);
- 8010204:	693b      	ldr	r3, [r7, #16]
- 8010206:	2206      	movs	r2, #6
- 8010208:	6839      	ldr	r1, [r7, #0]
- 801020a:	4618      	mov	r0, r3
- 801020c:	f000 febd 	bl	8010f8a <memcpy>
-  SMEMCPY(&ethhdr->src,  src, ETH_HWADDR_LEN);
- 8010210:	693b      	ldr	r3, [r7, #16]
- 8010212:	3306      	adds	r3, #6
- 8010214:	2206      	movs	r2, #6
- 8010216:	6879      	ldr	r1, [r7, #4]
- 8010218:	4618      	mov	r0, r3
- 801021a:	f000 feb6 	bl	8010f8a <memcpy>
-
-  LWIP_ASSERT("netif->hwaddr_len must be 6 for ethernet_output!",
- 801021e:	68fb      	ldr	r3, [r7, #12]
- 8010220:	f893 302c 	ldrb.w	r3, [r3, #44]	; 0x2c
- 8010224:	2b06      	cmp	r3, #6
- 8010226:	d006      	beq.n	8010236 <ethernet_output+0x66>
- 8010228:	4b0a      	ldr	r3, [pc, #40]	; (8010254 <ethernet_output+0x84>)
- 801022a:	f44f 7299 	mov.w	r2, #306	; 0x132
- 801022e:	490a      	ldr	r1, [pc, #40]	; (8010258 <ethernet_output+0x88>)
- 8010230:	480a      	ldr	r0, [pc, #40]	; (801025c <ethernet_output+0x8c>)
- 8010232:	f000 fcc9 	bl	8010bc8 <iprintf>
-              (netif->hwaddr_len == ETH_HWADDR_LEN));
-  LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE,
-              ("ethernet_output: sending packet %p\n", (void *)p));
-
-  /* send the packet */
-  return netif->linkoutput(netif, p);
- 8010236:	68fb      	ldr	r3, [r7, #12]
- 8010238:	699b      	ldr	r3, [r3, #24]
- 801023a:	68b9      	ldr	r1, [r7, #8]
- 801023c:	68f8      	ldr	r0, [r7, #12]
- 801023e:	4798      	blx	r3
- 8010240:	4603      	mov	r3, r0
- 8010242:	e002      	b.n	801024a <ethernet_output+0x7a>
-      goto pbuf_header_failed;
- 8010244:	bf00      	nop
-
-pbuf_header_failed:
-  LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS,
-              ("ethernet_output: could not allocate room for header.\n"));
-  LINK_STATS_INC(link.lenerr);
-  return ERR_BUF;
- 8010246:	f06f 0301 	mvn.w	r3, #1
-}
- 801024a:	4618      	mov	r0, r3
- 801024c:	3718      	adds	r7, #24
- 801024e:	46bd      	mov	sp, r7
- 8010250:	bd80      	pop	{r7, pc}
- 8010252:	bf00      	nop
- 8010254:	08014be4 	.word	0x08014be4
- 8010258:	08014c1c 	.word	0x08014c1c
- 801025c:	08014c50 	.word	0x08014c50
-
-08010260 <rand>:
- 8010260:	4b16      	ldr	r3, [pc, #88]	; (80102bc <rand+0x5c>)
- 8010262:	b510      	push	{r4, lr}
- 8010264:	681c      	ldr	r4, [r3, #0]
- 8010266:	6b23      	ldr	r3, [r4, #48]	; 0x30
- 8010268:	b9b3      	cbnz	r3, 8010298 <rand+0x38>
- 801026a:	2018      	movs	r0, #24
- 801026c:	f000 ff06 	bl	801107c <malloc>
- 8010270:	4602      	mov	r2, r0
- 8010272:	6320      	str	r0, [r4, #48]	; 0x30
- 8010274:	b920      	cbnz	r0, 8010280 <rand+0x20>
- 8010276:	4b12      	ldr	r3, [pc, #72]	; (80102c0 <rand+0x60>)
- 8010278:	4812      	ldr	r0, [pc, #72]	; (80102c4 <rand+0x64>)
- 801027a:	2152      	movs	r1, #82	; 0x52
- 801027c:	f000 fe94 	bl	8010fa8 <__assert_func>
- 8010280:	4911      	ldr	r1, [pc, #68]	; (80102c8 <rand+0x68>)
- 8010282:	4b12      	ldr	r3, [pc, #72]	; (80102cc <rand+0x6c>)
- 8010284:	e9c0 1300 	strd	r1, r3, [r0]
- 8010288:	4b11      	ldr	r3, [pc, #68]	; (80102d0 <rand+0x70>)
- 801028a:	6083      	str	r3, [r0, #8]
- 801028c:	230b      	movs	r3, #11
- 801028e:	8183      	strh	r3, [r0, #12]
- 8010290:	2100      	movs	r1, #0
- 8010292:	2001      	movs	r0, #1
- 8010294:	e9c2 0104 	strd	r0, r1, [r2, #16]
- 8010298:	6b21      	ldr	r1, [r4, #48]	; 0x30
- 801029a:	480e      	ldr	r0, [pc, #56]	; (80102d4 <rand+0x74>)
- 801029c:	690b      	ldr	r3, [r1, #16]
- 801029e:	694c      	ldr	r4, [r1, #20]
- 80102a0:	4a0d      	ldr	r2, [pc, #52]	; (80102d8 <rand+0x78>)
- 80102a2:	4358      	muls	r0, r3
- 80102a4:	fb02 0004 	mla	r0, r2, r4, r0
- 80102a8:	fba3 3202 	umull	r3, r2, r3, r2
- 80102ac:	3301      	adds	r3, #1
- 80102ae:	eb40 0002 	adc.w	r0, r0, r2
- 80102b2:	e9c1 3004 	strd	r3, r0, [r1, #16]
- 80102b6:	f020 4000 	bic.w	r0, r0, #2147483648	; 0x80000000
- 80102ba:	bd10      	pop	{r4, pc}
- 80102bc:	240000cc 	.word	0x240000cc
- 80102c0:	08014da6 	.word	0x08014da6
- 80102c4:	08014dbd 	.word	0x08014dbd
- 80102c8:	abcd330e 	.word	0xabcd330e
- 80102cc:	e66d1234 	.word	0xe66d1234
- 80102d0:	0005deec 	.word	0x0005deec
- 80102d4:	5851f42d 	.word	0x5851f42d
- 80102d8:	4c957f2d 	.word	0x4c957f2d
-
-080102dc <_strtoul_l.constprop.0>:
- 80102dc:	e92d 43f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, lr}
- 80102e0:	4f36      	ldr	r7, [pc, #216]	; (80103bc <_strtoul_l.constprop.0+0xe0>)
- 80102e2:	4686      	mov	lr, r0
- 80102e4:	460d      	mov	r5, r1
- 80102e6:	4628      	mov	r0, r5
- 80102e8:	f815 4b01 	ldrb.w	r4, [r5], #1
- 80102ec:	5d3e      	ldrb	r6, [r7, r4]
- 80102ee:	f016 0608 	ands.w	r6, r6, #8
- 80102f2:	d1f8      	bne.n	80102e6 <_strtoul_l.constprop.0+0xa>
- 80102f4:	2c2d      	cmp	r4, #45	; 0x2d
- 80102f6:	d130      	bne.n	801035a <_strtoul_l.constprop.0+0x7e>
- 80102f8:	782c      	ldrb	r4, [r5, #0]
- 80102fa:	2601      	movs	r6, #1
- 80102fc:	1c85      	adds	r5, r0, #2
- 80102fe:	2b00      	cmp	r3, #0
- 8010300:	d057      	beq.n	80103b2 <_strtoul_l.constprop.0+0xd6>
- 8010302:	2b10      	cmp	r3, #16
- 8010304:	d109      	bne.n	801031a <_strtoul_l.constprop.0+0x3e>
- 8010306:	2c30      	cmp	r4, #48	; 0x30
- 8010308:	d107      	bne.n	801031a <_strtoul_l.constprop.0+0x3e>
- 801030a:	7828      	ldrb	r0, [r5, #0]
- 801030c:	f000 00df 	and.w	r0, r0, #223	; 0xdf
- 8010310:	2858      	cmp	r0, #88	; 0x58
- 8010312:	d149      	bne.n	80103a8 <_strtoul_l.constprop.0+0xcc>
- 8010314:	786c      	ldrb	r4, [r5, #1]
- 8010316:	2310      	movs	r3, #16
- 8010318:	3502      	adds	r5, #2
- 801031a:	f04f 38ff 	mov.w	r8, #4294967295
- 801031e:	2700      	movs	r7, #0
- 8010320:	fbb8 f8f3 	udiv	r8, r8, r3
- 8010324:	fb03 f908 	mul.w	r9, r3, r8
- 8010328:	ea6f 0909 	mvn.w	r9, r9
- 801032c:	4638      	mov	r0, r7
- 801032e:	f1a4 0c30 	sub.w	ip, r4, #48	; 0x30
- 8010332:	f1bc 0f09 	cmp.w	ip, #9
- 8010336:	d815      	bhi.n	8010364 <_strtoul_l.constprop.0+0x88>
- 8010338:	4664      	mov	r4, ip
- 801033a:	42a3      	cmp	r3, r4
- 801033c:	dd23      	ble.n	8010386 <_strtoul_l.constprop.0+0xaa>
- 801033e:	f1b7 3fff 	cmp.w	r7, #4294967295
- 8010342:	d007      	beq.n	8010354 <_strtoul_l.constprop.0+0x78>
- 8010344:	4580      	cmp	r8, r0
- 8010346:	d31b      	bcc.n	8010380 <_strtoul_l.constprop.0+0xa4>
- 8010348:	d101      	bne.n	801034e <_strtoul_l.constprop.0+0x72>
- 801034a:	45a1      	cmp	r9, r4
- 801034c:	db18      	blt.n	8010380 <_strtoul_l.constprop.0+0xa4>
- 801034e:	fb00 4003 	mla	r0, r0, r3, r4
- 8010352:	2701      	movs	r7, #1
- 8010354:	f815 4b01 	ldrb.w	r4, [r5], #1
- 8010358:	e7e9      	b.n	801032e <_strtoul_l.constprop.0+0x52>
- 801035a:	2c2b      	cmp	r4, #43	; 0x2b
- 801035c:	bf04      	itt	eq
- 801035e:	782c      	ldrbeq	r4, [r5, #0]
- 8010360:	1c85      	addeq	r5, r0, #2
- 8010362:	e7cc      	b.n	80102fe <_strtoul_l.constprop.0+0x22>
- 8010364:	f1a4 0c41 	sub.w	ip, r4, #65	; 0x41
- 8010368:	f1bc 0f19 	cmp.w	ip, #25
- 801036c:	d801      	bhi.n	8010372 <_strtoul_l.constprop.0+0x96>
- 801036e:	3c37      	subs	r4, #55	; 0x37
- 8010370:	e7e3      	b.n	801033a <_strtoul_l.constprop.0+0x5e>
- 8010372:	f1a4 0c61 	sub.w	ip, r4, #97	; 0x61
- 8010376:	f1bc 0f19 	cmp.w	ip, #25
- 801037a:	d804      	bhi.n	8010386 <_strtoul_l.constprop.0+0xaa>
- 801037c:	3c57      	subs	r4, #87	; 0x57
- 801037e:	e7dc      	b.n	801033a <_strtoul_l.constprop.0+0x5e>
- 8010380:	f04f 37ff 	mov.w	r7, #4294967295
- 8010384:	e7e6      	b.n	8010354 <_strtoul_l.constprop.0+0x78>
- 8010386:	1c7b      	adds	r3, r7, #1
- 8010388:	d106      	bne.n	8010398 <_strtoul_l.constprop.0+0xbc>
- 801038a:	2322      	movs	r3, #34	; 0x22
- 801038c:	f8ce 3000 	str.w	r3, [lr]
- 8010390:	4638      	mov	r0, r7
- 8010392:	b932      	cbnz	r2, 80103a2 <_strtoul_l.constprop.0+0xc6>
- 8010394:	e8bd 83f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, pc}
- 8010398:	b106      	cbz	r6, 801039c <_strtoul_l.constprop.0+0xc0>
- 801039a:	4240      	negs	r0, r0
- 801039c:	2a00      	cmp	r2, #0
- 801039e:	d0f9      	beq.n	8010394 <_strtoul_l.constprop.0+0xb8>
- 80103a0:	b107      	cbz	r7, 80103a4 <_strtoul_l.constprop.0+0xc8>
- 80103a2:	1e69      	subs	r1, r5, #1
- 80103a4:	6011      	str	r1, [r2, #0]
- 80103a6:	e7f5      	b.n	8010394 <_strtoul_l.constprop.0+0xb8>
- 80103a8:	2430      	movs	r4, #48	; 0x30
- 80103aa:	2b00      	cmp	r3, #0
- 80103ac:	d1b5      	bne.n	801031a <_strtoul_l.constprop.0+0x3e>
- 80103ae:	2308      	movs	r3, #8
- 80103b0:	e7b3      	b.n	801031a <_strtoul_l.constprop.0+0x3e>
- 80103b2:	2c30      	cmp	r4, #48	; 0x30
- 80103b4:	d0a9      	beq.n	801030a <_strtoul_l.constprop.0+0x2e>
- 80103b6:	230a      	movs	r3, #10
- 80103b8:	e7af      	b.n	801031a <_strtoul_l.constprop.0+0x3e>
- 80103ba:	bf00      	nop
- 80103bc:	08014e16 	.word	0x08014e16
-
-080103c0 <strtoul>:
- 80103c0:	4613      	mov	r3, r2
- 80103c2:	460a      	mov	r2, r1
- 80103c4:	4601      	mov	r1, r0
- 80103c6:	4802      	ldr	r0, [pc, #8]	; (80103d0 <strtoul+0x10>)
- 80103c8:	6800      	ldr	r0, [r0, #0]
- 80103ca:	f7ff bf87 	b.w	80102dc <_strtoul_l.constprop.0>
- 80103ce:	bf00      	nop
- 80103d0:	240000cc 	.word	0x240000cc
-
-080103d4 <__sfputc_r>:
- 80103d4:	6893      	ldr	r3, [r2, #8]
- 80103d6:	3b01      	subs	r3, #1
- 80103d8:	2b00      	cmp	r3, #0
- 80103da:	b410      	push	{r4}
- 80103dc:	6093      	str	r3, [r2, #8]
- 80103de:	da08      	bge.n	80103f2 <__sfputc_r+0x1e>
- 80103e0:	6994      	ldr	r4, [r2, #24]
- 80103e2:	42a3      	cmp	r3, r4
- 80103e4:	db01      	blt.n	80103ea <__sfputc_r+0x16>
- 80103e6:	290a      	cmp	r1, #10
- 80103e8:	d103      	bne.n	80103f2 <__sfputc_r+0x1e>
- 80103ea:	f85d 4b04 	ldr.w	r4, [sp], #4
- 80103ee:	f000 bca4 	b.w	8010d3a <__swbuf_r>
- 80103f2:	6813      	ldr	r3, [r2, #0]
- 80103f4:	1c58      	adds	r0, r3, #1
- 80103f6:	6010      	str	r0, [r2, #0]
- 80103f8:	7019      	strb	r1, [r3, #0]
- 80103fa:	4608      	mov	r0, r1
- 80103fc:	f85d 4b04 	ldr.w	r4, [sp], #4
- 8010400:	4770      	bx	lr
-
-08010402 <__sfputs_r>:
- 8010402:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
- 8010404:	4606      	mov	r6, r0
- 8010406:	460f      	mov	r7, r1
- 8010408:	4614      	mov	r4, r2
- 801040a:	18d5      	adds	r5, r2, r3
- 801040c:	42ac      	cmp	r4, r5
- 801040e:	d101      	bne.n	8010414 <__sfputs_r+0x12>
- 8010410:	2000      	movs	r0, #0
- 8010412:	e007      	b.n	8010424 <__sfputs_r+0x22>
- 8010414:	f814 1b01 	ldrb.w	r1, [r4], #1
- 8010418:	463a      	mov	r2, r7
- 801041a:	4630      	mov	r0, r6
- 801041c:	f7ff ffda 	bl	80103d4 <__sfputc_r>
- 8010420:	1c43      	adds	r3, r0, #1
- 8010422:	d1f3      	bne.n	801040c <__sfputs_r+0xa>
- 8010424:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
-	...
-
-08010428 <_vfiprintf_r>:
- 8010428:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
- 801042c:	460d      	mov	r5, r1
- 801042e:	b09d      	sub	sp, #116	; 0x74
- 8010430:	4614      	mov	r4, r2
- 8010432:	4698      	mov	r8, r3
- 8010434:	4606      	mov	r6, r0
- 8010436:	b118      	cbz	r0, 8010440 <_vfiprintf_r+0x18>
- 8010438:	6a03      	ldr	r3, [r0, #32]
- 801043a:	b90b      	cbnz	r3, 8010440 <_vfiprintf_r+0x18>
- 801043c:	f000 fb34 	bl	8010aa8 <__sinit>
- 8010440:	6e6b      	ldr	r3, [r5, #100]	; 0x64
- 8010442:	07d9      	lsls	r1, r3, #31
- 8010444:	d405      	bmi.n	8010452 <_vfiprintf_r+0x2a>
- 8010446:	89ab      	ldrh	r3, [r5, #12]
- 8010448:	059a      	lsls	r2, r3, #22
- 801044a:	d402      	bmi.n	8010452 <_vfiprintf_r+0x2a>
- 801044c:	6da8      	ldr	r0, [r5, #88]	; 0x58
- 801044e:	f000 fd9a 	bl	8010f86 <__retarget_lock_acquire_recursive>
- 8010452:	89ab      	ldrh	r3, [r5, #12]
- 8010454:	071b      	lsls	r3, r3, #28
- 8010456:	d501      	bpl.n	801045c <_vfiprintf_r+0x34>
- 8010458:	692b      	ldr	r3, [r5, #16]
- 801045a:	b99b      	cbnz	r3, 8010484 <_vfiprintf_r+0x5c>
- 801045c:	4629      	mov	r1, r5
- 801045e:	4630      	mov	r0, r6
- 8010460:	f000 fca8 	bl	8010db4 <__swsetup_r>
- 8010464:	b170      	cbz	r0, 8010484 <_vfiprintf_r+0x5c>
- 8010466:	6e6b      	ldr	r3, [r5, #100]	; 0x64
- 8010468:	07dc      	lsls	r4, r3, #31
- 801046a:	d504      	bpl.n	8010476 <_vfiprintf_r+0x4e>
- 801046c:	f04f 30ff 	mov.w	r0, #4294967295
- 8010470:	b01d      	add	sp, #116	; 0x74
- 8010472:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
- 8010476:	89ab      	ldrh	r3, [r5, #12]
- 8010478:	0598      	lsls	r0, r3, #22
- 801047a:	d4f7      	bmi.n	801046c <_vfiprintf_r+0x44>
- 801047c:	6da8      	ldr	r0, [r5, #88]	; 0x58
- 801047e:	f000 fd83 	bl	8010f88 <__retarget_lock_release_recursive>
- 8010482:	e7f3      	b.n	801046c <_vfiprintf_r+0x44>
- 8010484:	2300      	movs	r3, #0
- 8010486:	9309      	str	r3, [sp, #36]	; 0x24
- 8010488:	2320      	movs	r3, #32
- 801048a:	f88d 3029 	strb.w	r3, [sp, #41]	; 0x29
- 801048e:	f8cd 800c 	str.w	r8, [sp, #12]
- 8010492:	2330      	movs	r3, #48	; 0x30
- 8010494:	f8df 81b0 	ldr.w	r8, [pc, #432]	; 8010648 <_vfiprintf_r+0x220>
- 8010498:	f88d 302a 	strb.w	r3, [sp, #42]	; 0x2a
- 801049c:	f04f 0901 	mov.w	r9, #1
- 80104a0:	4623      	mov	r3, r4
- 80104a2:	469a      	mov	sl, r3
- 80104a4:	f813 2b01 	ldrb.w	r2, [r3], #1
- 80104a8:	b10a      	cbz	r2, 80104ae <_vfiprintf_r+0x86>
- 80104aa:	2a25      	cmp	r2, #37	; 0x25
- 80104ac:	d1f9      	bne.n	80104a2 <_vfiprintf_r+0x7a>
- 80104ae:	ebba 0b04 	subs.w	fp, sl, r4
- 80104b2:	d00b      	beq.n	80104cc <_vfiprintf_r+0xa4>
- 80104b4:	465b      	mov	r3, fp
- 80104b6:	4622      	mov	r2, r4
- 80104b8:	4629      	mov	r1, r5
- 80104ba:	4630      	mov	r0, r6
- 80104bc:	f7ff ffa1 	bl	8010402 <__sfputs_r>
- 80104c0:	3001      	adds	r0, #1
- 80104c2:	f000 80a9 	beq.w	8010618 <_vfiprintf_r+0x1f0>
- 80104c6:	9a09      	ldr	r2, [sp, #36]	; 0x24
- 80104c8:	445a      	add	r2, fp
- 80104ca:	9209      	str	r2, [sp, #36]	; 0x24
- 80104cc:	f89a 3000 	ldrb.w	r3, [sl]
- 80104d0:	2b00      	cmp	r3, #0
- 80104d2:	f000 80a1 	beq.w	8010618 <_vfiprintf_r+0x1f0>
- 80104d6:	2300      	movs	r3, #0
- 80104d8:	f04f 32ff 	mov.w	r2, #4294967295
- 80104dc:	e9cd 2305 	strd	r2, r3, [sp, #20]
- 80104e0:	f10a 0a01 	add.w	sl, sl, #1
- 80104e4:	9304      	str	r3, [sp, #16]
- 80104e6:	9307      	str	r3, [sp, #28]
- 80104e8:	f88d 3053 	strb.w	r3, [sp, #83]	; 0x53
- 80104ec:	931a      	str	r3, [sp, #104]	; 0x68
- 80104ee:	4654      	mov	r4, sl
- 80104f0:	2205      	movs	r2, #5
- 80104f2:	f814 1b01 	ldrb.w	r1, [r4], #1
- 80104f6:	4854      	ldr	r0, [pc, #336]	; (8010648 <_vfiprintf_r+0x220>)
- 80104f8:	f7ef ff0a 	bl	8000310 <memchr>
- 80104fc:	9a04      	ldr	r2, [sp, #16]
- 80104fe:	b9d8      	cbnz	r0, 8010538 <_vfiprintf_r+0x110>
- 8010500:	06d1      	lsls	r1, r2, #27
- 8010502:	bf44      	itt	mi
- 8010504:	2320      	movmi	r3, #32
- 8010506:	f88d 3053 	strbmi.w	r3, [sp, #83]	; 0x53
- 801050a:	0713      	lsls	r3, r2, #28
- 801050c:	bf44      	itt	mi
- 801050e:	232b      	movmi	r3, #43	; 0x2b
- 8010510:	f88d 3053 	strbmi.w	r3, [sp, #83]	; 0x53
- 8010514:	f89a 3000 	ldrb.w	r3, [sl]
- 8010518:	2b2a      	cmp	r3, #42	; 0x2a
- 801051a:	d015      	beq.n	8010548 <_vfiprintf_r+0x120>
- 801051c:	9a07      	ldr	r2, [sp, #28]
- 801051e:	4654      	mov	r4, sl
- 8010520:	2000      	movs	r0, #0
- 8010522:	f04f 0c0a 	mov.w	ip, #10
- 8010526:	4621      	mov	r1, r4
- 8010528:	f811 3b01 	ldrb.w	r3, [r1], #1
- 801052c:	3b30      	subs	r3, #48	; 0x30
- 801052e:	2b09      	cmp	r3, #9
- 8010530:	d94d      	bls.n	80105ce <_vfiprintf_r+0x1a6>
- 8010532:	b1b0      	cbz	r0, 8010562 <_vfiprintf_r+0x13a>
- 8010534:	9207      	str	r2, [sp, #28]
- 8010536:	e014      	b.n	8010562 <_vfiprintf_r+0x13a>
- 8010538:	eba0 0308 	sub.w	r3, r0, r8
- 801053c:	fa09 f303 	lsl.w	r3, r9, r3
- 8010540:	4313      	orrs	r3, r2
- 8010542:	9304      	str	r3, [sp, #16]
- 8010544:	46a2      	mov	sl, r4
- 8010546:	e7d2      	b.n	80104ee <_vfiprintf_r+0xc6>
- 8010548:	9b03      	ldr	r3, [sp, #12]
- 801054a:	1d19      	adds	r1, r3, #4
- 801054c:	681b      	ldr	r3, [r3, #0]
- 801054e:	9103      	str	r1, [sp, #12]
- 8010550:	2b00      	cmp	r3, #0
- 8010552:	bfbb      	ittet	lt
- 8010554:	425b      	neglt	r3, r3
- 8010556:	f042 0202 	orrlt.w	r2, r2, #2
- 801055a:	9307      	strge	r3, [sp, #28]
- 801055c:	9307      	strlt	r3, [sp, #28]
- 801055e:	bfb8      	it	lt
- 8010560:	9204      	strlt	r2, [sp, #16]
- 8010562:	7823      	ldrb	r3, [r4, #0]
- 8010564:	2b2e      	cmp	r3, #46	; 0x2e
- 8010566:	d10c      	bne.n	8010582 <_vfiprintf_r+0x15a>
- 8010568:	7863      	ldrb	r3, [r4, #1]
- 801056a:	2b2a      	cmp	r3, #42	; 0x2a
- 801056c:	d134      	bne.n	80105d8 <_vfiprintf_r+0x1b0>
- 801056e:	9b03      	ldr	r3, [sp, #12]
- 8010570:	1d1a      	adds	r2, r3, #4
- 8010572:	681b      	ldr	r3, [r3, #0]
- 8010574:	9203      	str	r2, [sp, #12]
- 8010576:	2b00      	cmp	r3, #0
- 8010578:	bfb8      	it	lt
- 801057a:	f04f 33ff 	movlt.w	r3, #4294967295
- 801057e:	3402      	adds	r4, #2
- 8010580:	9305      	str	r3, [sp, #20]
- 8010582:	f8df a0d4 	ldr.w	sl, [pc, #212]	; 8010658 <_vfiprintf_r+0x230>
- 8010586:	7821      	ldrb	r1, [r4, #0]
- 8010588:	2203      	movs	r2, #3
- 801058a:	4650      	mov	r0, sl
- 801058c:	f7ef fec0 	bl	8000310 <memchr>
- 8010590:	b138      	cbz	r0, 80105a2 <_vfiprintf_r+0x17a>
- 8010592:	9b04      	ldr	r3, [sp, #16]
- 8010594:	eba0 000a 	sub.w	r0, r0, sl
- 8010598:	2240      	movs	r2, #64	; 0x40
- 801059a:	4082      	lsls	r2, r0
- 801059c:	4313      	orrs	r3, r2
- 801059e:	3401      	adds	r4, #1
- 80105a0:	9304      	str	r3, [sp, #16]
- 80105a2:	f814 1b01 	ldrb.w	r1, [r4], #1
- 80105a6:	4829      	ldr	r0, [pc, #164]	; (801064c <_vfiprintf_r+0x224>)
- 80105a8:	f88d 1028 	strb.w	r1, [sp, #40]	; 0x28
- 80105ac:	2206      	movs	r2, #6
- 80105ae:	f7ef feaf 	bl	8000310 <memchr>
- 80105b2:	2800      	cmp	r0, #0
- 80105b4:	d03f      	beq.n	8010636 <_vfiprintf_r+0x20e>
- 80105b6:	4b26      	ldr	r3, [pc, #152]	; (8010650 <_vfiprintf_r+0x228>)
- 80105b8:	bb1b      	cbnz	r3, 8010602 <_vfiprintf_r+0x1da>
- 80105ba:	9b03      	ldr	r3, [sp, #12]
- 80105bc:	3307      	adds	r3, #7
- 80105be:	f023 0307 	bic.w	r3, r3, #7
- 80105c2:	3308      	adds	r3, #8
- 80105c4:	9303      	str	r3, [sp, #12]
- 80105c6:	9b09      	ldr	r3, [sp, #36]	; 0x24
- 80105c8:	443b      	add	r3, r7
- 80105ca:	9309      	str	r3, [sp, #36]	; 0x24
- 80105cc:	e768      	b.n	80104a0 <_vfiprintf_r+0x78>
- 80105ce:	fb0c 3202 	mla	r2, ip, r2, r3
- 80105d2:	460c      	mov	r4, r1
- 80105d4:	2001      	movs	r0, #1
- 80105d6:	e7a6      	b.n	8010526 <_vfiprintf_r+0xfe>
- 80105d8:	2300      	movs	r3, #0
- 80105da:	3401      	adds	r4, #1
- 80105dc:	9305      	str	r3, [sp, #20]
- 80105de:	4619      	mov	r1, r3
- 80105e0:	f04f 0c0a 	mov.w	ip, #10
- 80105e4:	4620      	mov	r0, r4
- 80105e6:	f810 2b01 	ldrb.w	r2, [r0], #1
- 80105ea:	3a30      	subs	r2, #48	; 0x30
- 80105ec:	2a09      	cmp	r2, #9
- 80105ee:	d903      	bls.n	80105f8 <_vfiprintf_r+0x1d0>
- 80105f0:	2b00      	cmp	r3, #0
- 80105f2:	d0c6      	beq.n	8010582 <_vfiprintf_r+0x15a>
- 80105f4:	9105      	str	r1, [sp, #20]
- 80105f6:	e7c4      	b.n	8010582 <_vfiprintf_r+0x15a>
- 80105f8:	fb0c 2101 	mla	r1, ip, r1, r2
- 80105fc:	4604      	mov	r4, r0
- 80105fe:	2301      	movs	r3, #1
- 8010600:	e7f0      	b.n	80105e4 <_vfiprintf_r+0x1bc>
- 8010602:	ab03      	add	r3, sp, #12
- 8010604:	9300      	str	r3, [sp, #0]
- 8010606:	462a      	mov	r2, r5
- 8010608:	4b12      	ldr	r3, [pc, #72]	; (8010654 <_vfiprintf_r+0x22c>)
- 801060a:	a904      	add	r1, sp, #16
- 801060c:	4630      	mov	r0, r6
- 801060e:	f3af 8000 	nop.w
- 8010612:	4607      	mov	r7, r0
- 8010614:	1c78      	adds	r0, r7, #1
- 8010616:	d1d6      	bne.n	80105c6 <_vfiprintf_r+0x19e>
- 8010618:	6e6b      	ldr	r3, [r5, #100]	; 0x64
- 801061a:	07d9      	lsls	r1, r3, #31
- 801061c:	d405      	bmi.n	801062a <_vfiprintf_r+0x202>
- 801061e:	89ab      	ldrh	r3, [r5, #12]
- 8010620:	059a      	lsls	r2, r3, #22
- 8010622:	d402      	bmi.n	801062a <_vfiprintf_r+0x202>
- 8010624:	6da8      	ldr	r0, [r5, #88]	; 0x58
- 8010626:	f000 fcaf 	bl	8010f88 <__retarget_lock_release_recursive>
- 801062a:	89ab      	ldrh	r3, [r5, #12]
- 801062c:	065b      	lsls	r3, r3, #25
- 801062e:	f53f af1d 	bmi.w	801046c <_vfiprintf_r+0x44>
- 8010632:	9809      	ldr	r0, [sp, #36]	; 0x24
- 8010634:	e71c      	b.n	8010470 <_vfiprintf_r+0x48>
- 8010636:	ab03      	add	r3, sp, #12
- 8010638:	9300      	str	r3, [sp, #0]
- 801063a:	462a      	mov	r2, r5
- 801063c:	4b05      	ldr	r3, [pc, #20]	; (8010654 <_vfiprintf_r+0x22c>)
- 801063e:	a904      	add	r1, sp, #16
- 8010640:	4630      	mov	r0, r6
- 8010642:	f000 f883 	bl	801074c <_printf_i>
- 8010646:	e7e4      	b.n	8010612 <_vfiprintf_r+0x1ea>
- 8010648:	08014f16 	.word	0x08014f16
- 801064c:	08014f20 	.word	0x08014f20
- 8010650:	00000000 	.word	0x00000000
- 8010654:	08010403 	.word	0x08010403
- 8010658:	08014f1c 	.word	0x08014f1c
-
-0801065c <vfiprintf>:
- 801065c:	4613      	mov	r3, r2
- 801065e:	460a      	mov	r2, r1
- 8010660:	4601      	mov	r1, r0
- 8010662:	4802      	ldr	r0, [pc, #8]	; (801066c <vfiprintf+0x10>)
- 8010664:	6800      	ldr	r0, [r0, #0]
- 8010666:	f7ff bedf 	b.w	8010428 <_vfiprintf_r>
- 801066a:	bf00      	nop
- 801066c:	240000cc 	.word	0x240000cc
-
-08010670 <_printf_common>:
- 8010670:	e92d 47f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
- 8010674:	4616      	mov	r6, r2
- 8010676:	4699      	mov	r9, r3
- 8010678:	688a      	ldr	r2, [r1, #8]
- 801067a:	690b      	ldr	r3, [r1, #16]
- 801067c:	f8dd 8020 	ldr.w	r8, [sp, #32]
- 8010680:	4293      	cmp	r3, r2
- 8010682:	bfb8      	it	lt
- 8010684:	4613      	movlt	r3, r2
- 8010686:	6033      	str	r3, [r6, #0]
- 8010688:	f891 2043 	ldrb.w	r2, [r1, #67]	; 0x43
- 801068c:	4607      	mov	r7, r0
- 801068e:	460c      	mov	r4, r1
- 8010690:	b10a      	cbz	r2, 8010696 <_printf_common+0x26>
- 8010692:	3301      	adds	r3, #1
- 8010694:	6033      	str	r3, [r6, #0]
- 8010696:	6823      	ldr	r3, [r4, #0]
- 8010698:	0699      	lsls	r1, r3, #26
- 801069a:	bf42      	ittt	mi
- 801069c:	6833      	ldrmi	r3, [r6, #0]
- 801069e:	3302      	addmi	r3, #2
- 80106a0:	6033      	strmi	r3, [r6, #0]
- 80106a2:	6825      	ldr	r5, [r4, #0]
- 80106a4:	f015 0506 	ands.w	r5, r5, #6
- 80106a8:	d106      	bne.n	80106b8 <_printf_common+0x48>
- 80106aa:	f104 0a19 	add.w	sl, r4, #25
- 80106ae:	68e3      	ldr	r3, [r4, #12]
- 80106b0:	6832      	ldr	r2, [r6, #0]
- 80106b2:	1a9b      	subs	r3, r3, r2
- 80106b4:	42ab      	cmp	r3, r5
- 80106b6:	dc26      	bgt.n	8010706 <_printf_common+0x96>
- 80106b8:	f894 2043 	ldrb.w	r2, [r4, #67]	; 0x43
- 80106bc:	1e13      	subs	r3, r2, #0
- 80106be:	6822      	ldr	r2, [r4, #0]
- 80106c0:	bf18      	it	ne
- 80106c2:	2301      	movne	r3, #1
- 80106c4:	0692      	lsls	r2, r2, #26
- 80106c6:	d42b      	bmi.n	8010720 <_printf_common+0xb0>
- 80106c8:	f104 0243 	add.w	r2, r4, #67	; 0x43
- 80106cc:	4649      	mov	r1, r9
- 80106ce:	4638      	mov	r0, r7
- 80106d0:	47c0      	blx	r8
- 80106d2:	3001      	adds	r0, #1
- 80106d4:	d01e      	beq.n	8010714 <_printf_common+0xa4>
- 80106d6:	6823      	ldr	r3, [r4, #0]
- 80106d8:	6922      	ldr	r2, [r4, #16]
- 80106da:	f003 0306 	and.w	r3, r3, #6
- 80106de:	2b04      	cmp	r3, #4
- 80106e0:	bf02      	ittt	eq
- 80106e2:	68e5      	ldreq	r5, [r4, #12]
- 80106e4:	6833      	ldreq	r3, [r6, #0]
- 80106e6:	1aed      	subeq	r5, r5, r3
- 80106e8:	68a3      	ldr	r3, [r4, #8]
- 80106ea:	bf0c      	ite	eq
- 80106ec:	ea25 75e5 	biceq.w	r5, r5, r5, asr #31
- 80106f0:	2500      	movne	r5, #0
- 80106f2:	4293      	cmp	r3, r2
- 80106f4:	bfc4      	itt	gt
- 80106f6:	1a9b      	subgt	r3, r3, r2
- 80106f8:	18ed      	addgt	r5, r5, r3
- 80106fa:	2600      	movs	r6, #0
- 80106fc:	341a      	adds	r4, #26
- 80106fe:	42b5      	cmp	r5, r6
- 8010700:	d11a      	bne.n	8010738 <_printf_common+0xc8>
- 8010702:	2000      	movs	r0, #0
- 8010704:	e008      	b.n	8010718 <_printf_common+0xa8>
- 8010706:	2301      	movs	r3, #1
- 8010708:	4652      	mov	r2, sl
- 801070a:	4649      	mov	r1, r9
- 801070c:	4638      	mov	r0, r7
- 801070e:	47c0      	blx	r8
- 8010710:	3001      	adds	r0, #1
- 8010712:	d103      	bne.n	801071c <_printf_common+0xac>
- 8010714:	f04f 30ff 	mov.w	r0, #4294967295
- 8010718:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
- 801071c:	3501      	adds	r5, #1
- 801071e:	e7c6      	b.n	80106ae <_printf_common+0x3e>
- 8010720:	18e1      	adds	r1, r4, r3
- 8010722:	1c5a      	adds	r2, r3, #1
- 8010724:	2030      	movs	r0, #48	; 0x30
- 8010726:	f881 0043 	strb.w	r0, [r1, #67]	; 0x43
- 801072a:	4422      	add	r2, r4
- 801072c:	f894 1045 	ldrb.w	r1, [r4, #69]	; 0x45
- 8010730:	f882 1043 	strb.w	r1, [r2, #67]	; 0x43
- 8010734:	3302      	adds	r3, #2
- 8010736:	e7c7      	b.n	80106c8 <_printf_common+0x58>
- 8010738:	2301      	movs	r3, #1
- 801073a:	4622      	mov	r2, r4
- 801073c:	4649      	mov	r1, r9
- 801073e:	4638      	mov	r0, r7
- 8010740:	47c0      	blx	r8
- 8010742:	3001      	adds	r0, #1
- 8010744:	d0e6      	beq.n	8010714 <_printf_common+0xa4>
- 8010746:	3601      	adds	r6, #1
- 8010748:	e7d9      	b.n	80106fe <_printf_common+0x8e>
-	...
-
-0801074c <_printf_i>:
- 801074c:	e92d 47ff 	stmdb	sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, lr}
- 8010750:	7e0f      	ldrb	r7, [r1, #24]
- 8010752:	9d0c      	ldr	r5, [sp, #48]	; 0x30
- 8010754:	2f78      	cmp	r7, #120	; 0x78
- 8010756:	4691      	mov	r9, r2
- 8010758:	4680      	mov	r8, r0
- 801075a:	460c      	mov	r4, r1
- 801075c:	469a      	mov	sl, r3
- 801075e:	f101 0243 	add.w	r2, r1, #67	; 0x43
- 8010762:	d807      	bhi.n	8010774 <_printf_i+0x28>
- 8010764:	2f62      	cmp	r7, #98	; 0x62
- 8010766:	d80a      	bhi.n	801077e <_printf_i+0x32>
- 8010768:	2f00      	cmp	r7, #0
- 801076a:	f000 80d4 	beq.w	8010916 <_printf_i+0x1ca>
- 801076e:	2f58      	cmp	r7, #88	; 0x58
- 8010770:	f000 80c0 	beq.w	80108f4 <_printf_i+0x1a8>
- 8010774:	f104 0542 	add.w	r5, r4, #66	; 0x42
- 8010778:	f884 7042 	strb.w	r7, [r4, #66]	; 0x42
- 801077c:	e03a      	b.n	80107f4 <_printf_i+0xa8>
- 801077e:	f1a7 0363 	sub.w	r3, r7, #99	; 0x63
- 8010782:	2b15      	cmp	r3, #21
- 8010784:	d8f6      	bhi.n	8010774 <_printf_i+0x28>
- 8010786:	a101      	add	r1, pc, #4	; (adr r1, 801078c <_printf_i+0x40>)
- 8010788:	f851 f023 	ldr.w	pc, [r1, r3, lsl #2]
- 801078c:	080107e5 	.word	0x080107e5
- 8010790:	080107f9 	.word	0x080107f9
- 8010794:	08010775 	.word	0x08010775
- 8010798:	08010775 	.word	0x08010775
- 801079c:	08010775 	.word	0x08010775
- 80107a0:	08010775 	.word	0x08010775
- 80107a4:	080107f9 	.word	0x080107f9
- 80107a8:	08010775 	.word	0x08010775
- 80107ac:	08010775 	.word	0x08010775
- 80107b0:	08010775 	.word	0x08010775
- 80107b4:	08010775 	.word	0x08010775
- 80107b8:	080108fd 	.word	0x080108fd
- 80107bc:	08010825 	.word	0x08010825
- 80107c0:	080108b7 	.word	0x080108b7
- 80107c4:	08010775 	.word	0x08010775
- 80107c8:	08010775 	.word	0x08010775
- 80107cc:	0801091f 	.word	0x0801091f
- 80107d0:	08010775 	.word	0x08010775
- 80107d4:	08010825 	.word	0x08010825
- 80107d8:	08010775 	.word	0x08010775
- 80107dc:	08010775 	.word	0x08010775
- 80107e0:	080108bf 	.word	0x080108bf
- 80107e4:	682b      	ldr	r3, [r5, #0]
- 80107e6:	1d1a      	adds	r2, r3, #4
- 80107e8:	681b      	ldr	r3, [r3, #0]
- 80107ea:	602a      	str	r2, [r5, #0]
- 80107ec:	f104 0542 	add.w	r5, r4, #66	; 0x42
- 80107f0:	f884 3042 	strb.w	r3, [r4, #66]	; 0x42
- 80107f4:	2301      	movs	r3, #1
- 80107f6:	e09f      	b.n	8010938 <_printf_i+0x1ec>
- 80107f8:	6820      	ldr	r0, [r4, #0]
- 80107fa:	682b      	ldr	r3, [r5, #0]
- 80107fc:	0607      	lsls	r7, r0, #24
- 80107fe:	f103 0104 	add.w	r1, r3, #4
- 8010802:	6029      	str	r1, [r5, #0]
- 8010804:	d501      	bpl.n	801080a <_printf_i+0xbe>
- 8010806:	681e      	ldr	r6, [r3, #0]
- 8010808:	e003      	b.n	8010812 <_printf_i+0xc6>
- 801080a:	0646      	lsls	r6, r0, #25
- 801080c:	d5fb      	bpl.n	8010806 <_printf_i+0xba>
- 801080e:	f9b3 6000 	ldrsh.w	r6, [r3]
- 8010812:	2e00      	cmp	r6, #0
- 8010814:	da03      	bge.n	801081e <_printf_i+0xd2>
- 8010816:	232d      	movs	r3, #45	; 0x2d
- 8010818:	4276      	negs	r6, r6
- 801081a:	f884 3043 	strb.w	r3, [r4, #67]	; 0x43
- 801081e:	485a      	ldr	r0, [pc, #360]	; (8010988 <_printf_i+0x23c>)
- 8010820:	230a      	movs	r3, #10
- 8010822:	e012      	b.n	801084a <_printf_i+0xfe>
- 8010824:	682b      	ldr	r3, [r5, #0]
- 8010826:	6820      	ldr	r0, [r4, #0]
- 8010828:	1d19      	adds	r1, r3, #4
- 801082a:	6029      	str	r1, [r5, #0]
- 801082c:	0605      	lsls	r5, r0, #24
- 801082e:	d501      	bpl.n	8010834 <_printf_i+0xe8>
- 8010830:	681e      	ldr	r6, [r3, #0]
- 8010832:	e002      	b.n	801083a <_printf_i+0xee>
- 8010834:	0641      	lsls	r1, r0, #25
- 8010836:	d5fb      	bpl.n	8010830 <_printf_i+0xe4>
- 8010838:	881e      	ldrh	r6, [r3, #0]
- 801083a:	4853      	ldr	r0, [pc, #332]	; (8010988 <_printf_i+0x23c>)
- 801083c:	2f6f      	cmp	r7, #111	; 0x6f
- 801083e:	bf0c      	ite	eq
- 8010840:	2308      	moveq	r3, #8
- 8010842:	230a      	movne	r3, #10
- 8010844:	2100      	movs	r1, #0
- 8010846:	f884 1043 	strb.w	r1, [r4, #67]	; 0x43
- 801084a:	6865      	ldr	r5, [r4, #4]
- 801084c:	60a5      	str	r5, [r4, #8]
- 801084e:	2d00      	cmp	r5, #0
- 8010850:	bfa2      	ittt	ge
- 8010852:	6821      	ldrge	r1, [r4, #0]
- 8010854:	f021 0104 	bicge.w	r1, r1, #4
- 8010858:	6021      	strge	r1, [r4, #0]
- 801085a:	b90e      	cbnz	r6, 8010860 <_printf_i+0x114>
- 801085c:	2d00      	cmp	r5, #0
- 801085e:	d04b      	beq.n	80108f8 <_printf_i+0x1ac>
- 8010860:	4615      	mov	r5, r2
- 8010862:	fbb6 f1f3 	udiv	r1, r6, r3
- 8010866:	fb03 6711 	mls	r7, r3, r1, r6
- 801086a:	5dc7      	ldrb	r7, [r0, r7]
- 801086c:	f805 7d01 	strb.w	r7, [r5, #-1]!
- 8010870:	4637      	mov	r7, r6
- 8010872:	42bb      	cmp	r3, r7
- 8010874:	460e      	mov	r6, r1
- 8010876:	d9f4      	bls.n	8010862 <_printf_i+0x116>
- 8010878:	2b08      	cmp	r3, #8
- 801087a:	d10b      	bne.n	8010894 <_printf_i+0x148>
- 801087c:	6823      	ldr	r3, [r4, #0]
- 801087e:	07de      	lsls	r6, r3, #31
- 8010880:	d508      	bpl.n	8010894 <_printf_i+0x148>
- 8010882:	6923      	ldr	r3, [r4, #16]
- 8010884:	6861      	ldr	r1, [r4, #4]
- 8010886:	4299      	cmp	r1, r3
- 8010888:	bfde      	ittt	le
- 801088a:	2330      	movle	r3, #48	; 0x30
- 801088c:	f805 3c01 	strble.w	r3, [r5, #-1]
- 8010890:	f105 35ff 	addle.w	r5, r5, #4294967295
- 8010894:	1b52      	subs	r2, r2, r5
- 8010896:	6122      	str	r2, [r4, #16]
- 8010898:	f8cd a000 	str.w	sl, [sp]
- 801089c:	464b      	mov	r3, r9
- 801089e:	aa03      	add	r2, sp, #12
- 80108a0:	4621      	mov	r1, r4
- 80108a2:	4640      	mov	r0, r8
- 80108a4:	f7ff fee4 	bl	8010670 <_printf_common>
- 80108a8:	3001      	adds	r0, #1
- 80108aa:	d14a      	bne.n	8010942 <_printf_i+0x1f6>
- 80108ac:	f04f 30ff 	mov.w	r0, #4294967295
- 80108b0:	b004      	add	sp, #16
- 80108b2:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
- 80108b6:	6823      	ldr	r3, [r4, #0]
- 80108b8:	f043 0320 	orr.w	r3, r3, #32
- 80108bc:	6023      	str	r3, [r4, #0]
- 80108be:	4833      	ldr	r0, [pc, #204]	; (801098c <_printf_i+0x240>)
- 80108c0:	2778      	movs	r7, #120	; 0x78
- 80108c2:	f884 7045 	strb.w	r7, [r4, #69]	; 0x45
- 80108c6:	6823      	ldr	r3, [r4, #0]
- 80108c8:	6829      	ldr	r1, [r5, #0]
- 80108ca:	061f      	lsls	r7, r3, #24
- 80108cc:	f851 6b04 	ldr.w	r6, [r1], #4
- 80108d0:	d402      	bmi.n	80108d8 <_printf_i+0x18c>
- 80108d2:	065f      	lsls	r7, r3, #25
- 80108d4:	bf48      	it	mi
- 80108d6:	b2b6      	uxthmi	r6, r6
- 80108d8:	07df      	lsls	r7, r3, #31
- 80108da:	bf48      	it	mi
- 80108dc:	f043 0320 	orrmi.w	r3, r3, #32
- 80108e0:	6029      	str	r1, [r5, #0]
- 80108e2:	bf48      	it	mi
- 80108e4:	6023      	strmi	r3, [r4, #0]
- 80108e6:	b91e      	cbnz	r6, 80108f0 <_printf_i+0x1a4>
- 80108e8:	6823      	ldr	r3, [r4, #0]
- 80108ea:	f023 0320 	bic.w	r3, r3, #32
- 80108ee:	6023      	str	r3, [r4, #0]
- 80108f0:	2310      	movs	r3, #16
- 80108f2:	e7a7      	b.n	8010844 <_printf_i+0xf8>
- 80108f4:	4824      	ldr	r0, [pc, #144]	; (8010988 <_printf_i+0x23c>)
- 80108f6:	e7e4      	b.n	80108c2 <_printf_i+0x176>
- 80108f8:	4615      	mov	r5, r2
- 80108fa:	e7bd      	b.n	8010878 <_printf_i+0x12c>
- 80108fc:	682b      	ldr	r3, [r5, #0]
- 80108fe:	6826      	ldr	r6, [r4, #0]
- 8010900:	6961      	ldr	r1, [r4, #20]
- 8010902:	1d18      	adds	r0, r3, #4
- 8010904:	6028      	str	r0, [r5, #0]
- 8010906:	0635      	lsls	r5, r6, #24
- 8010908:	681b      	ldr	r3, [r3, #0]
- 801090a:	d501      	bpl.n	8010910 <_printf_i+0x1c4>
- 801090c:	6019      	str	r1, [r3, #0]
- 801090e:	e002      	b.n	8010916 <_printf_i+0x1ca>
- 8010910:	0670      	lsls	r0, r6, #25
- 8010912:	d5fb      	bpl.n	801090c <_printf_i+0x1c0>
- 8010914:	8019      	strh	r1, [r3, #0]
- 8010916:	2300      	movs	r3, #0
- 8010918:	6123      	str	r3, [r4, #16]
- 801091a:	4615      	mov	r5, r2
- 801091c:	e7bc      	b.n	8010898 <_printf_i+0x14c>
- 801091e:	682b      	ldr	r3, [r5, #0]
- 8010920:	1d1a      	adds	r2, r3, #4
- 8010922:	602a      	str	r2, [r5, #0]
- 8010924:	681d      	ldr	r5, [r3, #0]
- 8010926:	6862      	ldr	r2, [r4, #4]
- 8010928:	2100      	movs	r1, #0
- 801092a:	4628      	mov	r0, r5
- 801092c:	f7ef fcf0 	bl	8000310 <memchr>
- 8010930:	b108      	cbz	r0, 8010936 <_printf_i+0x1ea>
- 8010932:	1b40      	subs	r0, r0, r5
- 8010934:	6060      	str	r0, [r4, #4]
- 8010936:	6863      	ldr	r3, [r4, #4]
- 8010938:	6123      	str	r3, [r4, #16]
- 801093a:	2300      	movs	r3, #0
- 801093c:	f884 3043 	strb.w	r3, [r4, #67]	; 0x43
- 8010940:	e7aa      	b.n	8010898 <_printf_i+0x14c>
- 8010942:	6923      	ldr	r3, [r4, #16]
- 8010944:	462a      	mov	r2, r5
- 8010946:	4649      	mov	r1, r9
- 8010948:	4640      	mov	r0, r8
- 801094a:	47d0      	blx	sl
- 801094c:	3001      	adds	r0, #1
- 801094e:	d0ad      	beq.n	80108ac <_printf_i+0x160>
- 8010950:	6823      	ldr	r3, [r4, #0]
- 8010952:	079b      	lsls	r3, r3, #30
- 8010954:	d413      	bmi.n	801097e <_printf_i+0x232>
- 8010956:	68e0      	ldr	r0, [r4, #12]
- 8010958:	9b03      	ldr	r3, [sp, #12]
- 801095a:	4298      	cmp	r0, r3
- 801095c:	bfb8      	it	lt
- 801095e:	4618      	movlt	r0, r3
- 8010960:	e7a6      	b.n	80108b0 <_printf_i+0x164>
- 8010962:	2301      	movs	r3, #1
- 8010964:	4632      	mov	r2, r6
- 8010966:	4649      	mov	r1, r9
- 8010968:	4640      	mov	r0, r8
- 801096a:	47d0      	blx	sl
- 801096c:	3001      	adds	r0, #1
- 801096e:	d09d      	beq.n	80108ac <_printf_i+0x160>
- 8010970:	3501      	adds	r5, #1
- 8010972:	68e3      	ldr	r3, [r4, #12]
- 8010974:	9903      	ldr	r1, [sp, #12]
- 8010976:	1a5b      	subs	r3, r3, r1
- 8010978:	42ab      	cmp	r3, r5
- 801097a:	dcf2      	bgt.n	8010962 <_printf_i+0x216>
- 801097c:	e7eb      	b.n	8010956 <_printf_i+0x20a>
- 801097e:	2500      	movs	r5, #0
- 8010980:	f104 0619 	add.w	r6, r4, #25
- 8010984:	e7f5      	b.n	8010972 <_printf_i+0x226>
- 8010986:	bf00      	nop
- 8010988:	08014f27 	.word	0x08014f27
- 801098c:	08014f38 	.word	0x08014f38
-
-08010990 <std>:
- 8010990:	2300      	movs	r3, #0
- 8010992:	b510      	push	{r4, lr}
- 8010994:	4604      	mov	r4, r0
- 8010996:	e9c0 3300 	strd	r3, r3, [r0]
- 801099a:	e9c0 3304 	strd	r3, r3, [r0, #16]
- 801099e:	6083      	str	r3, [r0, #8]
- 80109a0:	8181      	strh	r1, [r0, #12]
- 80109a2:	6643      	str	r3, [r0, #100]	; 0x64
- 80109a4:	81c2      	strh	r2, [r0, #14]
- 80109a6:	6183      	str	r3, [r0, #24]
- 80109a8:	4619      	mov	r1, r3
- 80109aa:	2208      	movs	r2, #8
- 80109ac:	305c      	adds	r0, #92	; 0x5c
- 80109ae:	f000 fa69 	bl	8010e84 <memset>
- 80109b2:	4b0d      	ldr	r3, [pc, #52]	; (80109e8 <std+0x58>)
- 80109b4:	6263      	str	r3, [r4, #36]	; 0x24
- 80109b6:	4b0d      	ldr	r3, [pc, #52]	; (80109ec <std+0x5c>)
- 80109b8:	62a3      	str	r3, [r4, #40]	; 0x28
- 80109ba:	4b0d      	ldr	r3, [pc, #52]	; (80109f0 <std+0x60>)
- 80109bc:	62e3      	str	r3, [r4, #44]	; 0x2c
- 80109be:	4b0d      	ldr	r3, [pc, #52]	; (80109f4 <std+0x64>)
- 80109c0:	6323      	str	r3, [r4, #48]	; 0x30
- 80109c2:	4b0d      	ldr	r3, [pc, #52]	; (80109f8 <std+0x68>)
- 80109c4:	6224      	str	r4, [r4, #32]
- 80109c6:	429c      	cmp	r4, r3
- 80109c8:	d006      	beq.n	80109d8 <std+0x48>
- 80109ca:	f103 0268 	add.w	r2, r3, #104	; 0x68
- 80109ce:	4294      	cmp	r4, r2
- 80109d0:	d002      	beq.n	80109d8 <std+0x48>
- 80109d2:	33d0      	adds	r3, #208	; 0xd0
- 80109d4:	429c      	cmp	r4, r3
- 80109d6:	d105      	bne.n	80109e4 <std+0x54>
- 80109d8:	f104 0058 	add.w	r0, r4, #88	; 0x58
- 80109dc:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
- 80109e0:	f000 bad0 	b.w	8010f84 <__retarget_lock_init_recursive>
- 80109e4:	bd10      	pop	{r4, pc}
- 80109e6:	bf00      	nop
- 80109e8:	08010cb5 	.word	0x08010cb5
- 80109ec:	08010cd7 	.word	0x08010cd7
- 80109f0:	08010d0f 	.word	0x08010d0f
- 80109f4:	08010d33 	.word	0x08010d33
- 80109f8:	24007ccc 	.word	0x24007ccc
-
-080109fc <stdio_exit_handler>:
- 80109fc:	4a02      	ldr	r2, [pc, #8]	; (8010a08 <stdio_exit_handler+0xc>)
- 80109fe:	4903      	ldr	r1, [pc, #12]	; (8010a0c <stdio_exit_handler+0x10>)
- 8010a00:	4803      	ldr	r0, [pc, #12]	; (8010a10 <stdio_exit_handler+0x14>)
- 8010a02:	f000 b869 	b.w	8010ad8 <_fwalk_sglue>
- 8010a06:	bf00      	nop
- 8010a08:	24000074 	.word	0x24000074
- 8010a0c:	080112f1 	.word	0x080112f1
- 8010a10:	24000080 	.word	0x24000080
-
-08010a14 <cleanup_stdio>:
- 8010a14:	6841      	ldr	r1, [r0, #4]
- 8010a16:	4b0c      	ldr	r3, [pc, #48]	; (8010a48 <cleanup_stdio+0x34>)
- 8010a18:	4299      	cmp	r1, r3
- 8010a1a:	b510      	push	{r4, lr}
- 8010a1c:	4604      	mov	r4, r0
- 8010a1e:	d001      	beq.n	8010a24 <cleanup_stdio+0x10>
- 8010a20:	f000 fc66 	bl	80112f0 <_fflush_r>
- 8010a24:	68a1      	ldr	r1, [r4, #8]
- 8010a26:	4b09      	ldr	r3, [pc, #36]	; (8010a4c <cleanup_stdio+0x38>)
- 8010a28:	4299      	cmp	r1, r3
- 8010a2a:	d002      	beq.n	8010a32 <cleanup_stdio+0x1e>
- 8010a2c:	4620      	mov	r0, r4
- 8010a2e:	f000 fc5f 	bl	80112f0 <_fflush_r>
- 8010a32:	68e1      	ldr	r1, [r4, #12]
- 8010a34:	4b06      	ldr	r3, [pc, #24]	; (8010a50 <cleanup_stdio+0x3c>)
- 8010a36:	4299      	cmp	r1, r3
- 8010a38:	d004      	beq.n	8010a44 <cleanup_stdio+0x30>
- 8010a3a:	4620      	mov	r0, r4
- 8010a3c:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
- 8010a40:	f000 bc56 	b.w	80112f0 <_fflush_r>
- 8010a44:	bd10      	pop	{r4, pc}
- 8010a46:	bf00      	nop
- 8010a48:	24007ccc 	.word	0x24007ccc
- 8010a4c:	24007d34 	.word	0x24007d34
- 8010a50:	24007d9c 	.word	0x24007d9c
-
-08010a54 <global_stdio_init.part.0>:
- 8010a54:	b510      	push	{r4, lr}
- 8010a56:	4b0b      	ldr	r3, [pc, #44]	; (8010a84 <global_stdio_init.part.0+0x30>)
- 8010a58:	4c0b      	ldr	r4, [pc, #44]	; (8010a88 <global_stdio_init.part.0+0x34>)
- 8010a5a:	4a0c      	ldr	r2, [pc, #48]	; (8010a8c <global_stdio_init.part.0+0x38>)
- 8010a5c:	601a      	str	r2, [r3, #0]
- 8010a5e:	4620      	mov	r0, r4
- 8010a60:	2200      	movs	r2, #0
- 8010a62:	2104      	movs	r1, #4
- 8010a64:	f7ff ff94 	bl	8010990 <std>
- 8010a68:	f104 0068 	add.w	r0, r4, #104	; 0x68
- 8010a6c:	2201      	movs	r2, #1
- 8010a6e:	2109      	movs	r1, #9
- 8010a70:	f7ff ff8e 	bl	8010990 <std>
- 8010a74:	f104 00d0 	add.w	r0, r4, #208	; 0xd0
- 8010a78:	2202      	movs	r2, #2
- 8010a7a:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
- 8010a7e:	2112      	movs	r1, #18
- 8010a80:	f7ff bf86 	b.w	8010990 <std>
- 8010a84:	24007e04 	.word	0x24007e04
- 8010a88:	24007ccc 	.word	0x24007ccc
- 8010a8c:	080109fd 	.word	0x080109fd
-
-08010a90 <__sfp_lock_acquire>:
- 8010a90:	4801      	ldr	r0, [pc, #4]	; (8010a98 <__sfp_lock_acquire+0x8>)
- 8010a92:	f000 ba78 	b.w	8010f86 <__retarget_lock_acquire_recursive>
- 8010a96:	bf00      	nop
- 8010a98:	24007e0d 	.word	0x24007e0d
-
-08010a9c <__sfp_lock_release>:
- 8010a9c:	4801      	ldr	r0, [pc, #4]	; (8010aa4 <__sfp_lock_release+0x8>)
- 8010a9e:	f000 ba73 	b.w	8010f88 <__retarget_lock_release_recursive>
- 8010aa2:	bf00      	nop
- 8010aa4:	24007e0d 	.word	0x24007e0d
-
-08010aa8 <__sinit>:
- 8010aa8:	b510      	push	{r4, lr}
- 8010aaa:	4604      	mov	r4, r0
- 8010aac:	f7ff fff0 	bl	8010a90 <__sfp_lock_acquire>
- 8010ab0:	6a23      	ldr	r3, [r4, #32]
- 8010ab2:	b11b      	cbz	r3, 8010abc <__sinit+0x14>
- 8010ab4:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
- 8010ab8:	f7ff bff0 	b.w	8010a9c <__sfp_lock_release>
- 8010abc:	4b04      	ldr	r3, [pc, #16]	; (8010ad0 <__sinit+0x28>)
- 8010abe:	6223      	str	r3, [r4, #32]
- 8010ac0:	4b04      	ldr	r3, [pc, #16]	; (8010ad4 <__sinit+0x2c>)
- 8010ac2:	681b      	ldr	r3, [r3, #0]
- 8010ac4:	2b00      	cmp	r3, #0
- 8010ac6:	d1f5      	bne.n	8010ab4 <__sinit+0xc>
- 8010ac8:	f7ff ffc4 	bl	8010a54 <global_stdio_init.part.0>
- 8010acc:	e7f2      	b.n	8010ab4 <__sinit+0xc>
- 8010ace:	bf00      	nop
- 8010ad0:	08010a15 	.word	0x08010a15
- 8010ad4:	24007e04 	.word	0x24007e04
-
-08010ad8 <_fwalk_sglue>:
- 8010ad8:	e92d 43f8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
- 8010adc:	4607      	mov	r7, r0
- 8010ade:	4688      	mov	r8, r1
- 8010ae0:	4614      	mov	r4, r2
- 8010ae2:	2600      	movs	r6, #0
- 8010ae4:	e9d4 9501 	ldrd	r9, r5, [r4, #4]
- 8010ae8:	f1b9 0901 	subs.w	r9, r9, #1
- 8010aec:	d505      	bpl.n	8010afa <_fwalk_sglue+0x22>
- 8010aee:	6824      	ldr	r4, [r4, #0]
- 8010af0:	2c00      	cmp	r4, #0
- 8010af2:	d1f7      	bne.n	8010ae4 <_fwalk_sglue+0xc>
- 8010af4:	4630      	mov	r0, r6
- 8010af6:	e8bd 83f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
- 8010afa:	89ab      	ldrh	r3, [r5, #12]
- 8010afc:	2b01      	cmp	r3, #1
- 8010afe:	d907      	bls.n	8010b10 <_fwalk_sglue+0x38>
- 8010b00:	f9b5 300e 	ldrsh.w	r3, [r5, #14]
- 8010b04:	3301      	adds	r3, #1
- 8010b06:	d003      	beq.n	8010b10 <_fwalk_sglue+0x38>
- 8010b08:	4629      	mov	r1, r5
- 8010b0a:	4638      	mov	r0, r7
- 8010b0c:	47c0      	blx	r8
- 8010b0e:	4306      	orrs	r6, r0
- 8010b10:	3568      	adds	r5, #104	; 0x68
- 8010b12:	e7e9      	b.n	8010ae8 <_fwalk_sglue+0x10>
-
-08010b14 <_fwrite_r>:
- 8010b14:	e92d 47f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
- 8010b18:	9c08      	ldr	r4, [sp, #32]
- 8010b1a:	468a      	mov	sl, r1
- 8010b1c:	4690      	mov	r8, r2
- 8010b1e:	fb02 f903 	mul.w	r9, r2, r3
- 8010b22:	4606      	mov	r6, r0
- 8010b24:	b118      	cbz	r0, 8010b2e <_fwrite_r+0x1a>
- 8010b26:	6a03      	ldr	r3, [r0, #32]
- 8010b28:	b90b      	cbnz	r3, 8010b2e <_fwrite_r+0x1a>
- 8010b2a:	f7ff ffbd 	bl	8010aa8 <__sinit>
- 8010b2e:	6e63      	ldr	r3, [r4, #100]	; 0x64
- 8010b30:	07dd      	lsls	r5, r3, #31
- 8010b32:	d405      	bmi.n	8010b40 <_fwrite_r+0x2c>
- 8010b34:	89a3      	ldrh	r3, [r4, #12]
- 8010b36:	0598      	lsls	r0, r3, #22
- 8010b38:	d402      	bmi.n	8010b40 <_fwrite_r+0x2c>
- 8010b3a:	6da0      	ldr	r0, [r4, #88]	; 0x58
- 8010b3c:	f000 fa23 	bl	8010f86 <__retarget_lock_acquire_recursive>
- 8010b40:	89a3      	ldrh	r3, [r4, #12]
- 8010b42:	0719      	lsls	r1, r3, #28
- 8010b44:	d516      	bpl.n	8010b74 <_fwrite_r+0x60>
- 8010b46:	6923      	ldr	r3, [r4, #16]
- 8010b48:	b1a3      	cbz	r3, 8010b74 <_fwrite_r+0x60>
- 8010b4a:	2500      	movs	r5, #0
- 8010b4c:	454d      	cmp	r5, r9
- 8010b4e:	d01f      	beq.n	8010b90 <_fwrite_r+0x7c>
- 8010b50:	68a7      	ldr	r7, [r4, #8]
- 8010b52:	f81a 1005 	ldrb.w	r1, [sl, r5]
- 8010b56:	3f01      	subs	r7, #1
- 8010b58:	2f00      	cmp	r7, #0
- 8010b5a:	60a7      	str	r7, [r4, #8]
- 8010b5c:	da04      	bge.n	8010b68 <_fwrite_r+0x54>
- 8010b5e:	69a3      	ldr	r3, [r4, #24]
- 8010b60:	429f      	cmp	r7, r3
- 8010b62:	db0f      	blt.n	8010b84 <_fwrite_r+0x70>
- 8010b64:	290a      	cmp	r1, #10
- 8010b66:	d00d      	beq.n	8010b84 <_fwrite_r+0x70>
- 8010b68:	6823      	ldr	r3, [r4, #0]
- 8010b6a:	1c5a      	adds	r2, r3, #1
- 8010b6c:	6022      	str	r2, [r4, #0]
- 8010b6e:	7019      	strb	r1, [r3, #0]
- 8010b70:	3501      	adds	r5, #1
- 8010b72:	e7eb      	b.n	8010b4c <_fwrite_r+0x38>
- 8010b74:	4621      	mov	r1, r4
- 8010b76:	4630      	mov	r0, r6
- 8010b78:	f000 f91c 	bl	8010db4 <__swsetup_r>
- 8010b7c:	2800      	cmp	r0, #0
- 8010b7e:	d0e4      	beq.n	8010b4a <_fwrite_r+0x36>
- 8010b80:	2500      	movs	r5, #0
- 8010b82:	e005      	b.n	8010b90 <_fwrite_r+0x7c>
- 8010b84:	4622      	mov	r2, r4
- 8010b86:	4630      	mov	r0, r6
- 8010b88:	f000 f8d7 	bl	8010d3a <__swbuf_r>
- 8010b8c:	3001      	adds	r0, #1
- 8010b8e:	d1ef      	bne.n	8010b70 <_fwrite_r+0x5c>
- 8010b90:	6e63      	ldr	r3, [r4, #100]	; 0x64
- 8010b92:	07da      	lsls	r2, r3, #31
- 8010b94:	d405      	bmi.n	8010ba2 <_fwrite_r+0x8e>
- 8010b96:	89a3      	ldrh	r3, [r4, #12]
- 8010b98:	059b      	lsls	r3, r3, #22
- 8010b9a:	d402      	bmi.n	8010ba2 <_fwrite_r+0x8e>
- 8010b9c:	6da0      	ldr	r0, [r4, #88]	; 0x58
- 8010b9e:	f000 f9f3 	bl	8010f88 <__retarget_lock_release_recursive>
- 8010ba2:	fbb5 f0f8 	udiv	r0, r5, r8
- 8010ba6:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
-	...
-
-08010bac <fwrite>:
- 8010bac:	b507      	push	{r0, r1, r2, lr}
- 8010bae:	9300      	str	r3, [sp, #0]
- 8010bb0:	4613      	mov	r3, r2
- 8010bb2:	460a      	mov	r2, r1
- 8010bb4:	4601      	mov	r1, r0
- 8010bb6:	4803      	ldr	r0, [pc, #12]	; (8010bc4 <fwrite+0x18>)
- 8010bb8:	6800      	ldr	r0, [r0, #0]
- 8010bba:	f7ff ffab 	bl	8010b14 <_fwrite_r>
- 8010bbe:	b003      	add	sp, #12
- 8010bc0:	f85d fb04 	ldr.w	pc, [sp], #4
- 8010bc4:	240000cc 	.word	0x240000cc
-
-08010bc8 <iprintf>:
- 8010bc8:	b40f      	push	{r0, r1, r2, r3}
- 8010bca:	b507      	push	{r0, r1, r2, lr}
- 8010bcc:	4906      	ldr	r1, [pc, #24]	; (8010be8 <iprintf+0x20>)
- 8010bce:	ab04      	add	r3, sp, #16
- 8010bd0:	6808      	ldr	r0, [r1, #0]
- 8010bd2:	f853 2b04 	ldr.w	r2, [r3], #4
- 8010bd6:	6881      	ldr	r1, [r0, #8]
- 8010bd8:	9301      	str	r3, [sp, #4]
- 8010bda:	f7ff fc25 	bl	8010428 <_vfiprintf_r>
- 8010bde:	b003      	add	sp, #12
- 8010be0:	f85d eb04 	ldr.w	lr, [sp], #4
- 8010be4:	b004      	add	sp, #16
- 8010be6:	4770      	bx	lr
- 8010be8:	240000cc 	.word	0x240000cc
-
-08010bec <putchar>:
- 8010bec:	4b02      	ldr	r3, [pc, #8]	; (8010bf8 <putchar+0xc>)
- 8010bee:	4601      	mov	r1, r0
- 8010bf0:	6818      	ldr	r0, [r3, #0]
- 8010bf2:	6882      	ldr	r2, [r0, #8]
- 8010bf4:	f000 bc18 	b.w	8011428 <_putc_r>
- 8010bf8:	240000cc 	.word	0x240000cc
-
-08010bfc <_puts_r>:
- 8010bfc:	6a03      	ldr	r3, [r0, #32]
- 8010bfe:	b570      	push	{r4, r5, r6, lr}
- 8010c00:	6884      	ldr	r4, [r0, #8]
- 8010c02:	4605      	mov	r5, r0
- 8010c04:	460e      	mov	r6, r1
- 8010c06:	b90b      	cbnz	r3, 8010c0c <_puts_r+0x10>
- 8010c08:	f7ff ff4e 	bl	8010aa8 <__sinit>
- 8010c0c:	6e63      	ldr	r3, [r4, #100]	; 0x64
- 8010c0e:	07db      	lsls	r3, r3, #31
- 8010c10:	d405      	bmi.n	8010c1e <_puts_r+0x22>
- 8010c12:	89a3      	ldrh	r3, [r4, #12]
- 8010c14:	0598      	lsls	r0, r3, #22
- 8010c16:	d402      	bmi.n	8010c1e <_puts_r+0x22>
- 8010c18:	6da0      	ldr	r0, [r4, #88]	; 0x58
- 8010c1a:	f000 f9b4 	bl	8010f86 <__retarget_lock_acquire_recursive>
- 8010c1e:	89a3      	ldrh	r3, [r4, #12]
- 8010c20:	0719      	lsls	r1, r3, #28
- 8010c22:	d513      	bpl.n	8010c4c <_puts_r+0x50>
- 8010c24:	6923      	ldr	r3, [r4, #16]
- 8010c26:	b18b      	cbz	r3, 8010c4c <_puts_r+0x50>
- 8010c28:	3e01      	subs	r6, #1
- 8010c2a:	68a3      	ldr	r3, [r4, #8]
- 8010c2c:	f816 1f01 	ldrb.w	r1, [r6, #1]!
- 8010c30:	3b01      	subs	r3, #1
- 8010c32:	60a3      	str	r3, [r4, #8]
- 8010c34:	b9e9      	cbnz	r1, 8010c72 <_puts_r+0x76>
- 8010c36:	2b00      	cmp	r3, #0
- 8010c38:	da2e      	bge.n	8010c98 <_puts_r+0x9c>
- 8010c3a:	4622      	mov	r2, r4
- 8010c3c:	210a      	movs	r1, #10
- 8010c3e:	4628      	mov	r0, r5
- 8010c40:	f000 f87b 	bl	8010d3a <__swbuf_r>
- 8010c44:	3001      	adds	r0, #1
- 8010c46:	d007      	beq.n	8010c58 <_puts_r+0x5c>
- 8010c48:	250a      	movs	r5, #10
- 8010c4a:	e007      	b.n	8010c5c <_puts_r+0x60>
- 8010c4c:	4621      	mov	r1, r4
- 8010c4e:	4628      	mov	r0, r5
- 8010c50:	f000 f8b0 	bl	8010db4 <__swsetup_r>
- 8010c54:	2800      	cmp	r0, #0
- 8010c56:	d0e7      	beq.n	8010c28 <_puts_r+0x2c>
- 8010c58:	f04f 35ff 	mov.w	r5, #4294967295
- 8010c5c:	6e63      	ldr	r3, [r4, #100]	; 0x64
- 8010c5e:	07da      	lsls	r2, r3, #31
- 8010c60:	d405      	bmi.n	8010c6e <_puts_r+0x72>
- 8010c62:	89a3      	ldrh	r3, [r4, #12]
- 8010c64:	059b      	lsls	r3, r3, #22
- 8010c66:	d402      	bmi.n	8010c6e <_puts_r+0x72>
- 8010c68:	6da0      	ldr	r0, [r4, #88]	; 0x58
- 8010c6a:	f000 f98d 	bl	8010f88 <__retarget_lock_release_recursive>
- 8010c6e:	4628      	mov	r0, r5
- 8010c70:	bd70      	pop	{r4, r5, r6, pc}
- 8010c72:	2b00      	cmp	r3, #0
- 8010c74:	da04      	bge.n	8010c80 <_puts_r+0x84>
- 8010c76:	69a2      	ldr	r2, [r4, #24]
- 8010c78:	429a      	cmp	r2, r3
- 8010c7a:	dc06      	bgt.n	8010c8a <_puts_r+0x8e>
- 8010c7c:	290a      	cmp	r1, #10
- 8010c7e:	d004      	beq.n	8010c8a <_puts_r+0x8e>
- 8010c80:	6823      	ldr	r3, [r4, #0]
- 8010c82:	1c5a      	adds	r2, r3, #1
- 8010c84:	6022      	str	r2, [r4, #0]
- 8010c86:	7019      	strb	r1, [r3, #0]
- 8010c88:	e7cf      	b.n	8010c2a <_puts_r+0x2e>
- 8010c8a:	4622      	mov	r2, r4
- 8010c8c:	4628      	mov	r0, r5
- 8010c8e:	f000 f854 	bl	8010d3a <__swbuf_r>
- 8010c92:	3001      	adds	r0, #1
- 8010c94:	d1c9      	bne.n	8010c2a <_puts_r+0x2e>
- 8010c96:	e7df      	b.n	8010c58 <_puts_r+0x5c>
- 8010c98:	6823      	ldr	r3, [r4, #0]
- 8010c9a:	250a      	movs	r5, #10
- 8010c9c:	1c5a      	adds	r2, r3, #1
- 8010c9e:	6022      	str	r2, [r4, #0]
- 8010ca0:	701d      	strb	r5, [r3, #0]
- 8010ca2:	e7db      	b.n	8010c5c <_puts_r+0x60>
-
-08010ca4 <puts>:
- 8010ca4:	4b02      	ldr	r3, [pc, #8]	; (8010cb0 <puts+0xc>)
- 8010ca6:	4601      	mov	r1, r0
- 8010ca8:	6818      	ldr	r0, [r3, #0]
- 8010caa:	f7ff bfa7 	b.w	8010bfc <_puts_r>
- 8010cae:	bf00      	nop
- 8010cb0:	240000cc 	.word	0x240000cc
-
-08010cb4 <__sread>:
- 8010cb4:	b510      	push	{r4, lr}
- 8010cb6:	460c      	mov	r4, r1
- 8010cb8:	f9b1 100e 	ldrsh.w	r1, [r1, #14]
- 8010cbc:	f000 f91a 	bl	8010ef4 <_read_r>
- 8010cc0:	2800      	cmp	r0, #0
- 8010cc2:	bfab      	itete	ge
- 8010cc4:	6d63      	ldrge	r3, [r4, #84]	; 0x54
- 8010cc6:	89a3      	ldrhlt	r3, [r4, #12]
- 8010cc8:	181b      	addge	r3, r3, r0
- 8010cca:	f423 5380 	biclt.w	r3, r3, #4096	; 0x1000
- 8010cce:	bfac      	ite	ge
- 8010cd0:	6563      	strge	r3, [r4, #84]	; 0x54
- 8010cd2:	81a3      	strhlt	r3, [r4, #12]
- 8010cd4:	bd10      	pop	{r4, pc}
-
-08010cd6 <__swrite>:
- 8010cd6:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
- 8010cda:	461f      	mov	r7, r3
- 8010cdc:	898b      	ldrh	r3, [r1, #12]
- 8010cde:	05db      	lsls	r3, r3, #23
- 8010ce0:	4605      	mov	r5, r0
- 8010ce2:	460c      	mov	r4, r1
- 8010ce4:	4616      	mov	r6, r2
- 8010ce6:	d505      	bpl.n	8010cf4 <__swrite+0x1e>
- 8010ce8:	f9b1 100e 	ldrsh.w	r1, [r1, #14]
- 8010cec:	2302      	movs	r3, #2
- 8010cee:	2200      	movs	r2, #0
- 8010cf0:	f000 f8ee 	bl	8010ed0 <_lseek_r>
- 8010cf4:	89a3      	ldrh	r3, [r4, #12]
- 8010cf6:	f9b4 100e 	ldrsh.w	r1, [r4, #14]
- 8010cfa:	f423 5380 	bic.w	r3, r3, #4096	; 0x1000
- 8010cfe:	81a3      	strh	r3, [r4, #12]
- 8010d00:	4632      	mov	r2, r6
- 8010d02:	463b      	mov	r3, r7
- 8010d04:	4628      	mov	r0, r5
- 8010d06:	e8bd 41f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, lr}
- 8010d0a:	f000 b905 	b.w	8010f18 <_write_r>
-
-08010d0e <__sseek>:
- 8010d0e:	b510      	push	{r4, lr}
- 8010d10:	460c      	mov	r4, r1
- 8010d12:	f9b1 100e 	ldrsh.w	r1, [r1, #14]
- 8010d16:	f000 f8db 	bl	8010ed0 <_lseek_r>
- 8010d1a:	1c43      	adds	r3, r0, #1
- 8010d1c:	89a3      	ldrh	r3, [r4, #12]
- 8010d1e:	bf15      	itete	ne
- 8010d20:	6560      	strne	r0, [r4, #84]	; 0x54
- 8010d22:	f423 5380 	biceq.w	r3, r3, #4096	; 0x1000
- 8010d26:	f443 5380 	orrne.w	r3, r3, #4096	; 0x1000
- 8010d2a:	81a3      	strheq	r3, [r4, #12]
- 8010d2c:	bf18      	it	ne
- 8010d2e:	81a3      	strhne	r3, [r4, #12]
- 8010d30:	bd10      	pop	{r4, pc}
-
-08010d32 <__sclose>:
- 8010d32:	f9b1 100e 	ldrsh.w	r1, [r1, #14]
- 8010d36:	f000 b8bb 	b.w	8010eb0 <_close_r>
-
-08010d3a <__swbuf_r>:
- 8010d3a:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
- 8010d3c:	460e      	mov	r6, r1
- 8010d3e:	4614      	mov	r4, r2
- 8010d40:	4605      	mov	r5, r0
- 8010d42:	b118      	cbz	r0, 8010d4c <__swbuf_r+0x12>
- 8010d44:	6a03      	ldr	r3, [r0, #32]
- 8010d46:	b90b      	cbnz	r3, 8010d4c <__swbuf_r+0x12>
- 8010d48:	f7ff feae 	bl	8010aa8 <__sinit>
- 8010d4c:	69a3      	ldr	r3, [r4, #24]
- 8010d4e:	60a3      	str	r3, [r4, #8]
- 8010d50:	89a3      	ldrh	r3, [r4, #12]
- 8010d52:	071a      	lsls	r2, r3, #28
- 8010d54:	d525      	bpl.n	8010da2 <__swbuf_r+0x68>
- 8010d56:	6923      	ldr	r3, [r4, #16]
- 8010d58:	b31b      	cbz	r3, 8010da2 <__swbuf_r+0x68>
- 8010d5a:	6823      	ldr	r3, [r4, #0]
- 8010d5c:	6922      	ldr	r2, [r4, #16]
- 8010d5e:	1a98      	subs	r0, r3, r2
- 8010d60:	6963      	ldr	r3, [r4, #20]
- 8010d62:	b2f6      	uxtb	r6, r6
- 8010d64:	4283      	cmp	r3, r0
- 8010d66:	4637      	mov	r7, r6
- 8010d68:	dc04      	bgt.n	8010d74 <__swbuf_r+0x3a>
- 8010d6a:	4621      	mov	r1, r4
- 8010d6c:	4628      	mov	r0, r5
- 8010d6e:	f000 fabf 	bl	80112f0 <_fflush_r>
- 8010d72:	b9e0      	cbnz	r0, 8010dae <__swbuf_r+0x74>
- 8010d74:	68a3      	ldr	r3, [r4, #8]
- 8010d76:	3b01      	subs	r3, #1
- 8010d78:	60a3      	str	r3, [r4, #8]
- 8010d7a:	6823      	ldr	r3, [r4, #0]
- 8010d7c:	1c5a      	adds	r2, r3, #1
- 8010d7e:	6022      	str	r2, [r4, #0]
- 8010d80:	701e      	strb	r6, [r3, #0]
- 8010d82:	6962      	ldr	r2, [r4, #20]
- 8010d84:	1c43      	adds	r3, r0, #1
- 8010d86:	429a      	cmp	r2, r3
- 8010d88:	d004      	beq.n	8010d94 <__swbuf_r+0x5a>
- 8010d8a:	89a3      	ldrh	r3, [r4, #12]
- 8010d8c:	07db      	lsls	r3, r3, #31
- 8010d8e:	d506      	bpl.n	8010d9e <__swbuf_r+0x64>
- 8010d90:	2e0a      	cmp	r6, #10
- 8010d92:	d104      	bne.n	8010d9e <__swbuf_r+0x64>
- 8010d94:	4621      	mov	r1, r4
- 8010d96:	4628      	mov	r0, r5
- 8010d98:	f000 faaa 	bl	80112f0 <_fflush_r>
- 8010d9c:	b938      	cbnz	r0, 8010dae <__swbuf_r+0x74>
- 8010d9e:	4638      	mov	r0, r7
- 8010da0:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
- 8010da2:	4621      	mov	r1, r4
- 8010da4:	4628      	mov	r0, r5
- 8010da6:	f000 f805 	bl	8010db4 <__swsetup_r>
- 8010daa:	2800      	cmp	r0, #0
- 8010dac:	d0d5      	beq.n	8010d5a <__swbuf_r+0x20>
- 8010dae:	f04f 37ff 	mov.w	r7, #4294967295
- 8010db2:	e7f4      	b.n	8010d9e <__swbuf_r+0x64>
-
-08010db4 <__swsetup_r>:
- 8010db4:	b538      	push	{r3, r4, r5, lr}
- 8010db6:	4b2a      	ldr	r3, [pc, #168]	; (8010e60 <__swsetup_r+0xac>)
- 8010db8:	4605      	mov	r5, r0
- 8010dba:	6818      	ldr	r0, [r3, #0]
- 8010dbc:	460c      	mov	r4, r1
- 8010dbe:	b118      	cbz	r0, 8010dc8 <__swsetup_r+0x14>
- 8010dc0:	6a03      	ldr	r3, [r0, #32]
- 8010dc2:	b90b      	cbnz	r3, 8010dc8 <__swsetup_r+0x14>
- 8010dc4:	f7ff fe70 	bl	8010aa8 <__sinit>
- 8010dc8:	89a3      	ldrh	r3, [r4, #12]
- 8010dca:	f9b4 200c 	ldrsh.w	r2, [r4, #12]
- 8010dce:	0718      	lsls	r0, r3, #28
- 8010dd0:	d422      	bmi.n	8010e18 <__swsetup_r+0x64>
- 8010dd2:	06d9      	lsls	r1, r3, #27
- 8010dd4:	d407      	bmi.n	8010de6 <__swsetup_r+0x32>
- 8010dd6:	2309      	movs	r3, #9
- 8010dd8:	602b      	str	r3, [r5, #0]
- 8010dda:	f042 0340 	orr.w	r3, r2, #64	; 0x40
- 8010dde:	81a3      	strh	r3, [r4, #12]
- 8010de0:	f04f 30ff 	mov.w	r0, #4294967295
- 8010de4:	e034      	b.n	8010e50 <__swsetup_r+0x9c>
- 8010de6:	0758      	lsls	r0, r3, #29
- 8010de8:	d512      	bpl.n	8010e10 <__swsetup_r+0x5c>
- 8010dea:	6b61      	ldr	r1, [r4, #52]	; 0x34
- 8010dec:	b141      	cbz	r1, 8010e00 <__swsetup_r+0x4c>
- 8010dee:	f104 0344 	add.w	r3, r4, #68	; 0x44
- 8010df2:	4299      	cmp	r1, r3
- 8010df4:	d002      	beq.n	8010dfc <__swsetup_r+0x48>
- 8010df6:	4628      	mov	r0, r5
- 8010df8:	f000 f8f4 	bl	8010fe4 <_free_r>
- 8010dfc:	2300      	movs	r3, #0
- 8010dfe:	6363      	str	r3, [r4, #52]	; 0x34
- 8010e00:	89a3      	ldrh	r3, [r4, #12]
- 8010e02:	f023 0324 	bic.w	r3, r3, #36	; 0x24
- 8010e06:	81a3      	strh	r3, [r4, #12]
- 8010e08:	2300      	movs	r3, #0
- 8010e0a:	6063      	str	r3, [r4, #4]
- 8010e0c:	6923      	ldr	r3, [r4, #16]
- 8010e0e:	6023      	str	r3, [r4, #0]
- 8010e10:	89a3      	ldrh	r3, [r4, #12]
- 8010e12:	f043 0308 	orr.w	r3, r3, #8
- 8010e16:	81a3      	strh	r3, [r4, #12]
- 8010e18:	6923      	ldr	r3, [r4, #16]
- 8010e1a:	b94b      	cbnz	r3, 8010e30 <__swsetup_r+0x7c>
- 8010e1c:	89a3      	ldrh	r3, [r4, #12]
- 8010e1e:	f403 7320 	and.w	r3, r3, #640	; 0x280
- 8010e22:	f5b3 7f00 	cmp.w	r3, #512	; 0x200
- 8010e26:	d003      	beq.n	8010e30 <__swsetup_r+0x7c>
- 8010e28:	4621      	mov	r1, r4
- 8010e2a:	4628      	mov	r0, r5
- 8010e2c:	f000 fac0 	bl	80113b0 <__smakebuf_r>
- 8010e30:	89a0      	ldrh	r0, [r4, #12]
- 8010e32:	f9b4 200c 	ldrsh.w	r2, [r4, #12]
- 8010e36:	f010 0301 	ands.w	r3, r0, #1
- 8010e3a:	d00a      	beq.n	8010e52 <__swsetup_r+0x9e>
- 8010e3c:	2300      	movs	r3, #0
- 8010e3e:	60a3      	str	r3, [r4, #8]
- 8010e40:	6963      	ldr	r3, [r4, #20]
- 8010e42:	425b      	negs	r3, r3
- 8010e44:	61a3      	str	r3, [r4, #24]
- 8010e46:	6923      	ldr	r3, [r4, #16]
- 8010e48:	b943      	cbnz	r3, 8010e5c <__swsetup_r+0xa8>
- 8010e4a:	f010 0080 	ands.w	r0, r0, #128	; 0x80
- 8010e4e:	d1c4      	bne.n	8010dda <__swsetup_r+0x26>
- 8010e50:	bd38      	pop	{r3, r4, r5, pc}
- 8010e52:	0781      	lsls	r1, r0, #30
- 8010e54:	bf58      	it	pl
- 8010e56:	6963      	ldrpl	r3, [r4, #20]
- 8010e58:	60a3      	str	r3, [r4, #8]
- 8010e5a:	e7f4      	b.n	8010e46 <__swsetup_r+0x92>
- 8010e5c:	2000      	movs	r0, #0
- 8010e5e:	e7f7      	b.n	8010e50 <__swsetup_r+0x9c>
- 8010e60:	240000cc 	.word	0x240000cc
-
-08010e64 <memcmp>:
- 8010e64:	b510      	push	{r4, lr}
- 8010e66:	3901      	subs	r1, #1
- 8010e68:	4402      	add	r2, r0
- 8010e6a:	4290      	cmp	r0, r2
- 8010e6c:	d101      	bne.n	8010e72 <memcmp+0xe>
- 8010e6e:	2000      	movs	r0, #0
- 8010e70:	e005      	b.n	8010e7e <memcmp+0x1a>
- 8010e72:	7803      	ldrb	r3, [r0, #0]
- 8010e74:	f811 4f01 	ldrb.w	r4, [r1, #1]!
- 8010e78:	42a3      	cmp	r3, r4
- 8010e7a:	d001      	beq.n	8010e80 <memcmp+0x1c>
- 8010e7c:	1b18      	subs	r0, r3, r4
- 8010e7e:	bd10      	pop	{r4, pc}
- 8010e80:	3001      	adds	r0, #1
- 8010e82:	e7f2      	b.n	8010e6a <memcmp+0x6>
-
-08010e84 <memset>:
- 8010e84:	4402      	add	r2, r0
- 8010e86:	4603      	mov	r3, r0
- 8010e88:	4293      	cmp	r3, r2
- 8010e8a:	d100      	bne.n	8010e8e <memset+0xa>
- 8010e8c:	4770      	bx	lr
- 8010e8e:	f803 1b01 	strb.w	r1, [r3], #1
- 8010e92:	e7f9      	b.n	8010e88 <memset+0x4>
-
-08010e94 <strchr>:
- 8010e94:	b2c9      	uxtb	r1, r1
- 8010e96:	4603      	mov	r3, r0
- 8010e98:	f810 2b01 	ldrb.w	r2, [r0], #1
- 8010e9c:	b11a      	cbz	r2, 8010ea6 <strchr+0x12>
- 8010e9e:	428a      	cmp	r2, r1
- 8010ea0:	d1f9      	bne.n	8010e96 <strchr+0x2>
- 8010ea2:	4618      	mov	r0, r3
- 8010ea4:	4770      	bx	lr
- 8010ea6:	2900      	cmp	r1, #0
- 8010ea8:	bf18      	it	ne
- 8010eaa:	2300      	movne	r3, #0
- 8010eac:	e7f9      	b.n	8010ea2 <strchr+0xe>
-	...
-
-08010eb0 <_close_r>:
- 8010eb0:	b538      	push	{r3, r4, r5, lr}
- 8010eb2:	4d06      	ldr	r5, [pc, #24]	; (8010ecc <_close_r+0x1c>)
- 8010eb4:	2300      	movs	r3, #0
- 8010eb6:	4604      	mov	r4, r0
- 8010eb8:	4608      	mov	r0, r1
- 8010eba:	602b      	str	r3, [r5, #0]
- 8010ebc:	f7ef fda1 	bl	8000a02 <_close>
- 8010ec0:	1c43      	adds	r3, r0, #1
- 8010ec2:	d102      	bne.n	8010eca <_close_r+0x1a>
- 8010ec4:	682b      	ldr	r3, [r5, #0]
- 8010ec6:	b103      	cbz	r3, 8010eca <_close_r+0x1a>
- 8010ec8:	6023      	str	r3, [r4, #0]
- 8010eca:	bd38      	pop	{r3, r4, r5, pc}
- 8010ecc:	24007e08 	.word	0x24007e08
-
-08010ed0 <_lseek_r>:
- 8010ed0:	b538      	push	{r3, r4, r5, lr}
- 8010ed2:	4d07      	ldr	r5, [pc, #28]	; (8010ef0 <_lseek_r+0x20>)
- 8010ed4:	4604      	mov	r4, r0
- 8010ed6:	4608      	mov	r0, r1
- 8010ed8:	4611      	mov	r1, r2
- 8010eda:	2200      	movs	r2, #0
- 8010edc:	602a      	str	r2, [r5, #0]
- 8010ede:	461a      	mov	r2, r3
- 8010ee0:	f7ef fdb6 	bl	8000a50 <_lseek>
- 8010ee4:	1c43      	adds	r3, r0, #1
- 8010ee6:	d102      	bne.n	8010eee <_lseek_r+0x1e>
- 8010ee8:	682b      	ldr	r3, [r5, #0]
- 8010eea:	b103      	cbz	r3, 8010eee <_lseek_r+0x1e>
- 8010eec:	6023      	str	r3, [r4, #0]
- 8010eee:	bd38      	pop	{r3, r4, r5, pc}
- 8010ef0:	24007e08 	.word	0x24007e08
-
-08010ef4 <_read_r>:
- 8010ef4:	b538      	push	{r3, r4, r5, lr}
- 8010ef6:	4d07      	ldr	r5, [pc, #28]	; (8010f14 <_read_r+0x20>)
- 8010ef8:	4604      	mov	r4, r0
- 8010efa:	4608      	mov	r0, r1
- 8010efc:	4611      	mov	r1, r2
- 8010efe:	2200      	movs	r2, #0
- 8010f00:	602a      	str	r2, [r5, #0]
- 8010f02:	461a      	mov	r2, r3
- 8010f04:	f7ef fd60 	bl	80009c8 <_read>
- 8010f08:	1c43      	adds	r3, r0, #1
- 8010f0a:	d102      	bne.n	8010f12 <_read_r+0x1e>
- 8010f0c:	682b      	ldr	r3, [r5, #0]
- 8010f0e:	b103      	cbz	r3, 8010f12 <_read_r+0x1e>
- 8010f10:	6023      	str	r3, [r4, #0]
- 8010f12:	bd38      	pop	{r3, r4, r5, pc}
- 8010f14:	24007e08 	.word	0x24007e08
-
-08010f18 <_write_r>:
- 8010f18:	b538      	push	{r3, r4, r5, lr}
- 8010f1a:	4d07      	ldr	r5, [pc, #28]	; (8010f38 <_write_r+0x20>)
- 8010f1c:	4604      	mov	r4, r0
- 8010f1e:	4608      	mov	r0, r1
- 8010f20:	4611      	mov	r1, r2
- 8010f22:	2200      	movs	r2, #0
- 8010f24:	602a      	str	r2, [r5, #0]
- 8010f26:	461a      	mov	r2, r3
- 8010f28:	f7ef fa71 	bl	800040e <_write>
- 8010f2c:	1c43      	adds	r3, r0, #1
- 8010f2e:	d102      	bne.n	8010f36 <_write_r+0x1e>
- 8010f30:	682b      	ldr	r3, [r5, #0]
- 8010f32:	b103      	cbz	r3, 8010f36 <_write_r+0x1e>
- 8010f34:	6023      	str	r3, [r4, #0]
- 8010f36:	bd38      	pop	{r3, r4, r5, pc}
- 8010f38:	24007e08 	.word	0x24007e08
-
-08010f3c <__libc_init_array>:
- 8010f3c:	b570      	push	{r4, r5, r6, lr}
- 8010f3e:	4d0d      	ldr	r5, [pc, #52]	; (8010f74 <__libc_init_array+0x38>)
- 8010f40:	4c0d      	ldr	r4, [pc, #52]	; (8010f78 <__libc_init_array+0x3c>)
- 8010f42:	1b64      	subs	r4, r4, r5
- 8010f44:	10a4      	asrs	r4, r4, #2
- 8010f46:	2600      	movs	r6, #0
- 8010f48:	42a6      	cmp	r6, r4
- 8010f4a:	d109      	bne.n	8010f60 <__libc_init_array+0x24>
- 8010f4c:	4d0b      	ldr	r5, [pc, #44]	; (8010f7c <__libc_init_array+0x40>)
- 8010f4e:	4c0c      	ldr	r4, [pc, #48]	; (8010f80 <__libc_init_array+0x44>)
- 8010f50:	f000 fb1c 	bl	801158c <_init>
- 8010f54:	1b64      	subs	r4, r4, r5
- 8010f56:	10a4      	asrs	r4, r4, #2
- 8010f58:	2600      	movs	r6, #0
- 8010f5a:	42a6      	cmp	r6, r4
- 8010f5c:	d105      	bne.n	8010f6a <__libc_init_array+0x2e>
- 8010f5e:	bd70      	pop	{r4, r5, r6, pc}
- 8010f60:	f855 3b04 	ldr.w	r3, [r5], #4
- 8010f64:	4798      	blx	r3
- 8010f66:	3601      	adds	r6, #1
- 8010f68:	e7ee      	b.n	8010f48 <__libc_init_array+0xc>
- 8010f6a:	f855 3b04 	ldr.w	r3, [r5], #4
- 8010f6e:	4798      	blx	r3
- 8010f70:	3601      	adds	r6, #1
- 8010f72:	e7f2      	b.n	8010f5a <__libc_init_array+0x1e>
- 8010f74:	08014f88 	.word	0x08014f88
- 8010f78:	08014f88 	.word	0x08014f88
- 8010f7c:	08014f88 	.word	0x08014f88
- 8010f80:	08014f8c 	.word	0x08014f8c
-
-08010f84 <__retarget_lock_init_recursive>:
- 8010f84:	4770      	bx	lr
-
-08010f86 <__retarget_lock_acquire_recursive>:
- 8010f86:	4770      	bx	lr
-
-08010f88 <__retarget_lock_release_recursive>:
- 8010f88:	4770      	bx	lr
-
-08010f8a <memcpy>:
- 8010f8a:	440a      	add	r2, r1
- 8010f8c:	4291      	cmp	r1, r2
- 8010f8e:	f100 33ff 	add.w	r3, r0, #4294967295
- 8010f92:	d100      	bne.n	8010f96 <memcpy+0xc>
- 8010f94:	4770      	bx	lr
- 8010f96:	b510      	push	{r4, lr}
- 8010f98:	f811 4b01 	ldrb.w	r4, [r1], #1
- 8010f9c:	f803 4f01 	strb.w	r4, [r3, #1]!
- 8010fa0:	4291      	cmp	r1, r2
- 8010fa2:	d1f9      	bne.n	8010f98 <memcpy+0xe>
- 8010fa4:	bd10      	pop	{r4, pc}
-	...
-
-08010fa8 <__assert_func>:
- 8010fa8:	b51f      	push	{r0, r1, r2, r3, r4, lr}
- 8010faa:	4614      	mov	r4, r2
- 8010fac:	461a      	mov	r2, r3
- 8010fae:	4b09      	ldr	r3, [pc, #36]	; (8010fd4 <__assert_func+0x2c>)
- 8010fb0:	681b      	ldr	r3, [r3, #0]
- 8010fb2:	4605      	mov	r5, r0
- 8010fb4:	68d8      	ldr	r0, [r3, #12]
- 8010fb6:	b14c      	cbz	r4, 8010fcc <__assert_func+0x24>
- 8010fb8:	4b07      	ldr	r3, [pc, #28]	; (8010fd8 <__assert_func+0x30>)
- 8010fba:	9100      	str	r1, [sp, #0]
- 8010fbc:	e9cd 3401 	strd	r3, r4, [sp, #4]
- 8010fc0:	4906      	ldr	r1, [pc, #24]	; (8010fdc <__assert_func+0x34>)
- 8010fc2:	462b      	mov	r3, r5
- 8010fc4:	f000 f9bc 	bl	8011340 <fiprintf>
- 8010fc8:	f000 fa94 	bl	80114f4 <abort>
- 8010fcc:	4b04      	ldr	r3, [pc, #16]	; (8010fe0 <__assert_func+0x38>)
- 8010fce:	461c      	mov	r4, r3
- 8010fd0:	e7f3      	b.n	8010fba <__assert_func+0x12>
- 8010fd2:	bf00      	nop
- 8010fd4:	240000cc 	.word	0x240000cc
- 8010fd8:	08014f49 	.word	0x08014f49
- 8010fdc:	08014f56 	.word	0x08014f56
- 8010fe0:	08014f84 	.word	0x08014f84
-
-08010fe4 <_free_r>:
- 8010fe4:	b537      	push	{r0, r1, r2, r4, r5, lr}
- 8010fe6:	2900      	cmp	r1, #0
- 8010fe8:	d044      	beq.n	8011074 <_free_r+0x90>
- 8010fea:	f851 3c04 	ldr.w	r3, [r1, #-4]
- 8010fee:	9001      	str	r0, [sp, #4]
- 8010ff0:	2b00      	cmp	r3, #0
- 8010ff2:	f1a1 0404 	sub.w	r4, r1, #4
- 8010ff6:	bfb8      	it	lt
- 8010ff8:	18e4      	addlt	r4, r4, r3
- 8010ffa:	f000 f8e7 	bl	80111cc <__malloc_lock>
- 8010ffe:	4a1e      	ldr	r2, [pc, #120]	; (8011078 <_free_r+0x94>)
- 8011000:	9801      	ldr	r0, [sp, #4]
- 8011002:	6813      	ldr	r3, [r2, #0]
- 8011004:	b933      	cbnz	r3, 8011014 <_free_r+0x30>
- 8011006:	6063      	str	r3, [r4, #4]
- 8011008:	6014      	str	r4, [r2, #0]
- 801100a:	b003      	add	sp, #12
- 801100c:	e8bd 4030 	ldmia.w	sp!, {r4, r5, lr}
- 8011010:	f000 b8e2 	b.w	80111d8 <__malloc_unlock>
- 8011014:	42a3      	cmp	r3, r4
- 8011016:	d908      	bls.n	801102a <_free_r+0x46>
- 8011018:	6825      	ldr	r5, [r4, #0]
- 801101a:	1961      	adds	r1, r4, r5
- 801101c:	428b      	cmp	r3, r1
- 801101e:	bf01      	itttt	eq
- 8011020:	6819      	ldreq	r1, [r3, #0]
- 8011022:	685b      	ldreq	r3, [r3, #4]
- 8011024:	1949      	addeq	r1, r1, r5
- 8011026:	6021      	streq	r1, [r4, #0]
- 8011028:	e7ed      	b.n	8011006 <_free_r+0x22>
- 801102a:	461a      	mov	r2, r3
- 801102c:	685b      	ldr	r3, [r3, #4]
- 801102e:	b10b      	cbz	r3, 8011034 <_free_r+0x50>
- 8011030:	42a3      	cmp	r3, r4
- 8011032:	d9fa      	bls.n	801102a <_free_r+0x46>
- 8011034:	6811      	ldr	r1, [r2, #0]
- 8011036:	1855      	adds	r5, r2, r1
- 8011038:	42a5      	cmp	r5, r4
- 801103a:	d10b      	bne.n	8011054 <_free_r+0x70>
- 801103c:	6824      	ldr	r4, [r4, #0]
- 801103e:	4421      	add	r1, r4
- 8011040:	1854      	adds	r4, r2, r1
- 8011042:	42a3      	cmp	r3, r4
- 8011044:	6011      	str	r1, [r2, #0]
- 8011046:	d1e0      	bne.n	801100a <_free_r+0x26>
- 8011048:	681c      	ldr	r4, [r3, #0]
- 801104a:	685b      	ldr	r3, [r3, #4]
- 801104c:	6053      	str	r3, [r2, #4]
- 801104e:	440c      	add	r4, r1
- 8011050:	6014      	str	r4, [r2, #0]
- 8011052:	e7da      	b.n	801100a <_free_r+0x26>
- 8011054:	d902      	bls.n	801105c <_free_r+0x78>
- 8011056:	230c      	movs	r3, #12
- 8011058:	6003      	str	r3, [r0, #0]
- 801105a:	e7d6      	b.n	801100a <_free_r+0x26>
- 801105c:	6825      	ldr	r5, [r4, #0]
- 801105e:	1961      	adds	r1, r4, r5
- 8011060:	428b      	cmp	r3, r1
- 8011062:	bf04      	itt	eq
- 8011064:	6819      	ldreq	r1, [r3, #0]
- 8011066:	685b      	ldreq	r3, [r3, #4]
- 8011068:	6063      	str	r3, [r4, #4]
- 801106a:	bf04      	itt	eq
- 801106c:	1949      	addeq	r1, r1, r5
- 801106e:	6021      	streq	r1, [r4, #0]
- 8011070:	6054      	str	r4, [r2, #4]
- 8011072:	e7ca      	b.n	801100a <_free_r+0x26>
- 8011074:	b003      	add	sp, #12
- 8011076:	bd30      	pop	{r4, r5, pc}
- 8011078:	24007e10 	.word	0x24007e10
-
-0801107c <malloc>:
- 801107c:	4b02      	ldr	r3, [pc, #8]	; (8011088 <malloc+0xc>)
- 801107e:	4601      	mov	r1, r0
- 8011080:	6818      	ldr	r0, [r3, #0]
- 8011082:	f000 b823 	b.w	80110cc <_malloc_r>
- 8011086:	bf00      	nop
- 8011088:	240000cc 	.word	0x240000cc
-
-0801108c <sbrk_aligned>:
- 801108c:	b570      	push	{r4, r5, r6, lr}
- 801108e:	4e0e      	ldr	r6, [pc, #56]	; (80110c8 <sbrk_aligned+0x3c>)
- 8011090:	460c      	mov	r4, r1
- 8011092:	6831      	ldr	r1, [r6, #0]
- 8011094:	4605      	mov	r5, r0
- 8011096:	b911      	cbnz	r1, 801109e <sbrk_aligned+0x12>
- 8011098:	f000 fa1c 	bl	80114d4 <_sbrk_r>
- 801109c:	6030      	str	r0, [r6, #0]
- 801109e:	4621      	mov	r1, r4
- 80110a0:	4628      	mov	r0, r5
- 80110a2:	f000 fa17 	bl	80114d4 <_sbrk_r>
- 80110a6:	1c43      	adds	r3, r0, #1
- 80110a8:	d00a      	beq.n	80110c0 <sbrk_aligned+0x34>
- 80110aa:	1cc4      	adds	r4, r0, #3
- 80110ac:	f024 0403 	bic.w	r4, r4, #3
- 80110b0:	42a0      	cmp	r0, r4
- 80110b2:	d007      	beq.n	80110c4 <sbrk_aligned+0x38>
- 80110b4:	1a21      	subs	r1, r4, r0
- 80110b6:	4628      	mov	r0, r5
- 80110b8:	f000 fa0c 	bl	80114d4 <_sbrk_r>
- 80110bc:	3001      	adds	r0, #1
- 80110be:	d101      	bne.n	80110c4 <sbrk_aligned+0x38>
- 80110c0:	f04f 34ff 	mov.w	r4, #4294967295
- 80110c4:	4620      	mov	r0, r4
- 80110c6:	bd70      	pop	{r4, r5, r6, pc}
- 80110c8:	24007e14 	.word	0x24007e14
-
-080110cc <_malloc_r>:
- 80110cc:	e92d 43f8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
- 80110d0:	1ccd      	adds	r5, r1, #3
- 80110d2:	f025 0503 	bic.w	r5, r5, #3
- 80110d6:	3508      	adds	r5, #8
- 80110d8:	2d0c      	cmp	r5, #12
- 80110da:	bf38      	it	cc
- 80110dc:	250c      	movcc	r5, #12
- 80110de:	2d00      	cmp	r5, #0
- 80110e0:	4607      	mov	r7, r0
- 80110e2:	db01      	blt.n	80110e8 <_malloc_r+0x1c>
- 80110e4:	42a9      	cmp	r1, r5
- 80110e6:	d905      	bls.n	80110f4 <_malloc_r+0x28>
- 80110e8:	230c      	movs	r3, #12
- 80110ea:	603b      	str	r3, [r7, #0]
- 80110ec:	2600      	movs	r6, #0
- 80110ee:	4630      	mov	r0, r6
- 80110f0:	e8bd 83f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
- 80110f4:	f8df 80d0 	ldr.w	r8, [pc, #208]	; 80111c8 <_malloc_r+0xfc>
- 80110f8:	f000 f868 	bl	80111cc <__malloc_lock>
- 80110fc:	f8d8 3000 	ldr.w	r3, [r8]
- 8011100:	461c      	mov	r4, r3
- 8011102:	bb5c      	cbnz	r4, 801115c <_malloc_r+0x90>
- 8011104:	4629      	mov	r1, r5
- 8011106:	4638      	mov	r0, r7
- 8011108:	f7ff ffc0 	bl	801108c <sbrk_aligned>
- 801110c:	1c43      	adds	r3, r0, #1
- 801110e:	4604      	mov	r4, r0
- 8011110:	d155      	bne.n	80111be <_malloc_r+0xf2>
- 8011112:	f8d8 4000 	ldr.w	r4, [r8]
- 8011116:	4626      	mov	r6, r4
- 8011118:	2e00      	cmp	r6, #0
- 801111a:	d145      	bne.n	80111a8 <_malloc_r+0xdc>
- 801111c:	2c00      	cmp	r4, #0
- 801111e:	d048      	beq.n	80111b2 <_malloc_r+0xe6>
- 8011120:	6823      	ldr	r3, [r4, #0]
- 8011122:	4631      	mov	r1, r6
- 8011124:	4638      	mov	r0, r7
- 8011126:	eb04 0903 	add.w	r9, r4, r3
- 801112a:	f000 f9d3 	bl	80114d4 <_sbrk_r>
- 801112e:	4581      	cmp	r9, r0
- 8011130:	d13f      	bne.n	80111b2 <_malloc_r+0xe6>
- 8011132:	6821      	ldr	r1, [r4, #0]
- 8011134:	1a6d      	subs	r5, r5, r1
- 8011136:	4629      	mov	r1, r5
- 8011138:	4638      	mov	r0, r7
- 801113a:	f7ff ffa7 	bl	801108c <sbrk_aligned>
- 801113e:	3001      	adds	r0, #1
- 8011140:	d037      	beq.n	80111b2 <_malloc_r+0xe6>
- 8011142:	6823      	ldr	r3, [r4, #0]
- 8011144:	442b      	add	r3, r5
- 8011146:	6023      	str	r3, [r4, #0]
- 8011148:	f8d8 3000 	ldr.w	r3, [r8]
- 801114c:	2b00      	cmp	r3, #0
- 801114e:	d038      	beq.n	80111c2 <_malloc_r+0xf6>
- 8011150:	685a      	ldr	r2, [r3, #4]
- 8011152:	42a2      	cmp	r2, r4
- 8011154:	d12b      	bne.n	80111ae <_malloc_r+0xe2>
- 8011156:	2200      	movs	r2, #0
- 8011158:	605a      	str	r2, [r3, #4]
- 801115a:	e00f      	b.n	801117c <_malloc_r+0xb0>
- 801115c:	6822      	ldr	r2, [r4, #0]
- 801115e:	1b52      	subs	r2, r2, r5
- 8011160:	d41f      	bmi.n	80111a2 <_malloc_r+0xd6>
- 8011162:	2a0b      	cmp	r2, #11
- 8011164:	d917      	bls.n	8011196 <_malloc_r+0xca>
- 8011166:	1961      	adds	r1, r4, r5
- 8011168:	42a3      	cmp	r3, r4
- 801116a:	6025      	str	r5, [r4, #0]
- 801116c:	bf18      	it	ne
- 801116e:	6059      	strne	r1, [r3, #4]
- 8011170:	6863      	ldr	r3, [r4, #4]
- 8011172:	bf08      	it	eq
- 8011174:	f8c8 1000 	streq.w	r1, [r8]
- 8011178:	5162      	str	r2, [r4, r5]
- 801117a:	604b      	str	r3, [r1, #4]
- 801117c:	4638      	mov	r0, r7
- 801117e:	f104 060b 	add.w	r6, r4, #11
- 8011182:	f000 f829 	bl	80111d8 <__malloc_unlock>
- 8011186:	f026 0607 	bic.w	r6, r6, #7
- 801118a:	1d23      	adds	r3, r4, #4
- 801118c:	1af2      	subs	r2, r6, r3
- 801118e:	d0ae      	beq.n	80110ee <_malloc_r+0x22>
- 8011190:	1b9b      	subs	r3, r3, r6
- 8011192:	50a3      	str	r3, [r4, r2]
- 8011194:	e7ab      	b.n	80110ee <_malloc_r+0x22>
- 8011196:	42a3      	cmp	r3, r4
- 8011198:	6862      	ldr	r2, [r4, #4]
- 801119a:	d1dd      	bne.n	8011158 <_malloc_r+0x8c>
- 801119c:	f8c8 2000 	str.w	r2, [r8]
- 80111a0:	e7ec      	b.n	801117c <_malloc_r+0xb0>
- 80111a2:	4623      	mov	r3, r4
- 80111a4:	6864      	ldr	r4, [r4, #4]
- 80111a6:	e7ac      	b.n	8011102 <_malloc_r+0x36>
- 80111a8:	4634      	mov	r4, r6
- 80111aa:	6876      	ldr	r6, [r6, #4]
- 80111ac:	e7b4      	b.n	8011118 <_malloc_r+0x4c>
- 80111ae:	4613      	mov	r3, r2
- 80111b0:	e7cc      	b.n	801114c <_malloc_r+0x80>
- 80111b2:	230c      	movs	r3, #12
- 80111b4:	603b      	str	r3, [r7, #0]
- 80111b6:	4638      	mov	r0, r7
- 80111b8:	f000 f80e 	bl	80111d8 <__malloc_unlock>
- 80111bc:	e797      	b.n	80110ee <_malloc_r+0x22>
- 80111be:	6025      	str	r5, [r4, #0]
- 80111c0:	e7dc      	b.n	801117c <_malloc_r+0xb0>
- 80111c2:	605b      	str	r3, [r3, #4]
- 80111c4:	deff      	udf	#255	; 0xff
- 80111c6:	bf00      	nop
- 80111c8:	24007e10 	.word	0x24007e10
-
-080111cc <__malloc_lock>:
- 80111cc:	4801      	ldr	r0, [pc, #4]	; (80111d4 <__malloc_lock+0x8>)
- 80111ce:	f7ff beda 	b.w	8010f86 <__retarget_lock_acquire_recursive>
- 80111d2:	bf00      	nop
- 80111d4:	24007e0c 	.word	0x24007e0c
-
-080111d8 <__malloc_unlock>:
- 80111d8:	4801      	ldr	r0, [pc, #4]	; (80111e0 <__malloc_unlock+0x8>)
- 80111da:	f7ff bed5 	b.w	8010f88 <__retarget_lock_release_recursive>
- 80111de:	bf00      	nop
- 80111e0:	24007e0c 	.word	0x24007e0c
-
-080111e4 <__sflush_r>:
- 80111e4:	898a      	ldrh	r2, [r1, #12]
- 80111e6:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
- 80111ea:	4605      	mov	r5, r0
- 80111ec:	0710      	lsls	r0, r2, #28
- 80111ee:	460c      	mov	r4, r1
- 80111f0:	d458      	bmi.n	80112a4 <__sflush_r+0xc0>
- 80111f2:	684b      	ldr	r3, [r1, #4]
- 80111f4:	2b00      	cmp	r3, #0
- 80111f6:	dc05      	bgt.n	8011204 <__sflush_r+0x20>
- 80111f8:	6c0b      	ldr	r3, [r1, #64]	; 0x40
- 80111fa:	2b00      	cmp	r3, #0
- 80111fc:	dc02      	bgt.n	8011204 <__sflush_r+0x20>
- 80111fe:	2000      	movs	r0, #0
- 8011200:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
- 8011204:	6ae6      	ldr	r6, [r4, #44]	; 0x2c
- 8011206:	2e00      	cmp	r6, #0
- 8011208:	d0f9      	beq.n	80111fe <__sflush_r+0x1a>
- 801120a:	2300      	movs	r3, #0
- 801120c:	f412 5280 	ands.w	r2, r2, #4096	; 0x1000
- 8011210:	682f      	ldr	r7, [r5, #0]
- 8011212:	6a21      	ldr	r1, [r4, #32]
- 8011214:	602b      	str	r3, [r5, #0]
- 8011216:	d032      	beq.n	801127e <__sflush_r+0x9a>
- 8011218:	6d60      	ldr	r0, [r4, #84]	; 0x54
- 801121a:	89a3      	ldrh	r3, [r4, #12]
- 801121c:	075a      	lsls	r2, r3, #29
- 801121e:	d505      	bpl.n	801122c <__sflush_r+0x48>
- 8011220:	6863      	ldr	r3, [r4, #4]
- 8011222:	1ac0      	subs	r0, r0, r3
- 8011224:	6b63      	ldr	r3, [r4, #52]	; 0x34
- 8011226:	b10b      	cbz	r3, 801122c <__sflush_r+0x48>
- 8011228:	6c23      	ldr	r3, [r4, #64]	; 0x40
- 801122a:	1ac0      	subs	r0, r0, r3
- 801122c:	2300      	movs	r3, #0
- 801122e:	4602      	mov	r2, r0
- 8011230:	6ae6      	ldr	r6, [r4, #44]	; 0x2c
- 8011232:	6a21      	ldr	r1, [r4, #32]
- 8011234:	4628      	mov	r0, r5
- 8011236:	47b0      	blx	r6
- 8011238:	1c43      	adds	r3, r0, #1
- 801123a:	89a3      	ldrh	r3, [r4, #12]
- 801123c:	d106      	bne.n	801124c <__sflush_r+0x68>
- 801123e:	6829      	ldr	r1, [r5, #0]
- 8011240:	291d      	cmp	r1, #29
- 8011242:	d82b      	bhi.n	801129c <__sflush_r+0xb8>
- 8011244:	4a29      	ldr	r2, [pc, #164]	; (80112ec <__sflush_r+0x108>)
- 8011246:	410a      	asrs	r2, r1
- 8011248:	07d6      	lsls	r6, r2, #31
- 801124a:	d427      	bmi.n	801129c <__sflush_r+0xb8>
- 801124c:	2200      	movs	r2, #0
- 801124e:	6062      	str	r2, [r4, #4]
- 8011250:	04d9      	lsls	r1, r3, #19
- 8011252:	6922      	ldr	r2, [r4, #16]
- 8011254:	6022      	str	r2, [r4, #0]
- 8011256:	d504      	bpl.n	8011262 <__sflush_r+0x7e>
- 8011258:	1c42      	adds	r2, r0, #1
- 801125a:	d101      	bne.n	8011260 <__sflush_r+0x7c>
- 801125c:	682b      	ldr	r3, [r5, #0]
- 801125e:	b903      	cbnz	r3, 8011262 <__sflush_r+0x7e>
- 8011260:	6560      	str	r0, [r4, #84]	; 0x54
- 8011262:	6b61      	ldr	r1, [r4, #52]	; 0x34
- 8011264:	602f      	str	r7, [r5, #0]
- 8011266:	2900      	cmp	r1, #0
- 8011268:	d0c9      	beq.n	80111fe <__sflush_r+0x1a>
- 801126a:	f104 0344 	add.w	r3, r4, #68	; 0x44
- 801126e:	4299      	cmp	r1, r3
- 8011270:	d002      	beq.n	8011278 <__sflush_r+0x94>
- 8011272:	4628      	mov	r0, r5
- 8011274:	f7ff feb6 	bl	8010fe4 <_free_r>
- 8011278:	2000      	movs	r0, #0
- 801127a:	6360      	str	r0, [r4, #52]	; 0x34
- 801127c:	e7c0      	b.n	8011200 <__sflush_r+0x1c>
- 801127e:	2301      	movs	r3, #1
- 8011280:	4628      	mov	r0, r5
- 8011282:	47b0      	blx	r6
- 8011284:	1c41      	adds	r1, r0, #1
- 8011286:	d1c8      	bne.n	801121a <__sflush_r+0x36>
- 8011288:	682b      	ldr	r3, [r5, #0]
- 801128a:	2b00      	cmp	r3, #0
- 801128c:	d0c5      	beq.n	801121a <__sflush_r+0x36>
- 801128e:	2b1d      	cmp	r3, #29
- 8011290:	d001      	beq.n	8011296 <__sflush_r+0xb2>
- 8011292:	2b16      	cmp	r3, #22
- 8011294:	d101      	bne.n	801129a <__sflush_r+0xb6>
- 8011296:	602f      	str	r7, [r5, #0]
- 8011298:	e7b1      	b.n	80111fe <__sflush_r+0x1a>
- 801129a:	89a3      	ldrh	r3, [r4, #12]
- 801129c:	f043 0340 	orr.w	r3, r3, #64	; 0x40
- 80112a0:	81a3      	strh	r3, [r4, #12]
- 80112a2:	e7ad      	b.n	8011200 <__sflush_r+0x1c>
- 80112a4:	690f      	ldr	r7, [r1, #16]
- 80112a6:	2f00      	cmp	r7, #0
- 80112a8:	d0a9      	beq.n	80111fe <__sflush_r+0x1a>
- 80112aa:	0793      	lsls	r3, r2, #30
- 80112ac:	680e      	ldr	r6, [r1, #0]
- 80112ae:	bf08      	it	eq
- 80112b0:	694b      	ldreq	r3, [r1, #20]
- 80112b2:	600f      	str	r7, [r1, #0]
- 80112b4:	bf18      	it	ne
- 80112b6:	2300      	movne	r3, #0
- 80112b8:	eba6 0807 	sub.w	r8, r6, r7
- 80112bc:	608b      	str	r3, [r1, #8]
- 80112be:	f1b8 0f00 	cmp.w	r8, #0
- 80112c2:	dd9c      	ble.n	80111fe <__sflush_r+0x1a>
- 80112c4:	6a21      	ldr	r1, [r4, #32]
- 80112c6:	6aa6      	ldr	r6, [r4, #40]	; 0x28
- 80112c8:	4643      	mov	r3, r8
- 80112ca:	463a      	mov	r2, r7
- 80112cc:	4628      	mov	r0, r5
- 80112ce:	47b0      	blx	r6
- 80112d0:	2800      	cmp	r0, #0
- 80112d2:	dc06      	bgt.n	80112e2 <__sflush_r+0xfe>
- 80112d4:	89a3      	ldrh	r3, [r4, #12]
- 80112d6:	f043 0340 	orr.w	r3, r3, #64	; 0x40
- 80112da:	81a3      	strh	r3, [r4, #12]
- 80112dc:	f04f 30ff 	mov.w	r0, #4294967295
- 80112e0:	e78e      	b.n	8011200 <__sflush_r+0x1c>
- 80112e2:	4407      	add	r7, r0
- 80112e4:	eba8 0800 	sub.w	r8, r8, r0
- 80112e8:	e7e9      	b.n	80112be <__sflush_r+0xda>
- 80112ea:	bf00      	nop
- 80112ec:	dfbffffe 	.word	0xdfbffffe
-
-080112f0 <_fflush_r>:
- 80112f0:	b538      	push	{r3, r4, r5, lr}
- 80112f2:	690b      	ldr	r3, [r1, #16]
- 80112f4:	4605      	mov	r5, r0
- 80112f6:	460c      	mov	r4, r1
- 80112f8:	b913      	cbnz	r3, 8011300 <_fflush_r+0x10>
- 80112fa:	2500      	movs	r5, #0
- 80112fc:	4628      	mov	r0, r5
- 80112fe:	bd38      	pop	{r3, r4, r5, pc}
- 8011300:	b118      	cbz	r0, 801130a <_fflush_r+0x1a>
- 8011302:	6a03      	ldr	r3, [r0, #32]
- 8011304:	b90b      	cbnz	r3, 801130a <_fflush_r+0x1a>
- 8011306:	f7ff fbcf 	bl	8010aa8 <__sinit>
- 801130a:	f9b4 300c 	ldrsh.w	r3, [r4, #12]
- 801130e:	2b00      	cmp	r3, #0
- 8011310:	d0f3      	beq.n	80112fa <_fflush_r+0xa>
- 8011312:	6e62      	ldr	r2, [r4, #100]	; 0x64
- 8011314:	07d0      	lsls	r0, r2, #31
- 8011316:	d404      	bmi.n	8011322 <_fflush_r+0x32>
- 8011318:	0599      	lsls	r1, r3, #22
- 801131a:	d402      	bmi.n	8011322 <_fflush_r+0x32>
- 801131c:	6da0      	ldr	r0, [r4, #88]	; 0x58
- 801131e:	f7ff fe32 	bl	8010f86 <__retarget_lock_acquire_recursive>
- 8011322:	4628      	mov	r0, r5
- 8011324:	4621      	mov	r1, r4
- 8011326:	f7ff ff5d 	bl	80111e4 <__sflush_r>
- 801132a:	6e63      	ldr	r3, [r4, #100]	; 0x64
- 801132c:	07da      	lsls	r2, r3, #31
- 801132e:	4605      	mov	r5, r0
- 8011330:	d4e4      	bmi.n	80112fc <_fflush_r+0xc>
- 8011332:	89a3      	ldrh	r3, [r4, #12]
- 8011334:	059b      	lsls	r3, r3, #22
- 8011336:	d4e1      	bmi.n	80112fc <_fflush_r+0xc>
- 8011338:	6da0      	ldr	r0, [r4, #88]	; 0x58
- 801133a:	f7ff fe25 	bl	8010f88 <__retarget_lock_release_recursive>
- 801133e:	e7dd      	b.n	80112fc <_fflush_r+0xc>
-
-08011340 <fiprintf>:
- 8011340:	b40e      	push	{r1, r2, r3}
- 8011342:	b503      	push	{r0, r1, lr}
- 8011344:	4601      	mov	r1, r0
- 8011346:	ab03      	add	r3, sp, #12
- 8011348:	4805      	ldr	r0, [pc, #20]	; (8011360 <fiprintf+0x20>)
- 801134a:	f853 2b04 	ldr.w	r2, [r3], #4
- 801134e:	6800      	ldr	r0, [r0, #0]
- 8011350:	9301      	str	r3, [sp, #4]
- 8011352:	f7ff f869 	bl	8010428 <_vfiprintf_r>
- 8011356:	b002      	add	sp, #8
- 8011358:	f85d eb04 	ldr.w	lr, [sp], #4
- 801135c:	b003      	add	sp, #12
- 801135e:	4770      	bx	lr
- 8011360:	240000cc 	.word	0x240000cc
-
-08011364 <__swhatbuf_r>:
- 8011364:	b570      	push	{r4, r5, r6, lr}
- 8011366:	460c      	mov	r4, r1
- 8011368:	f9b1 100e 	ldrsh.w	r1, [r1, #14]
- 801136c:	2900      	cmp	r1, #0
- 801136e:	b096      	sub	sp, #88	; 0x58
- 8011370:	4615      	mov	r5, r2
- 8011372:	461e      	mov	r6, r3
- 8011374:	da0d      	bge.n	8011392 <__swhatbuf_r+0x2e>
- 8011376:	89a3      	ldrh	r3, [r4, #12]
- 8011378:	f013 0f80 	tst.w	r3, #128	; 0x80
- 801137c:	f04f 0100 	mov.w	r1, #0
- 8011380:	bf0c      	ite	eq
- 8011382:	f44f 6380 	moveq.w	r3, #1024	; 0x400
- 8011386:	2340      	movne	r3, #64	; 0x40
- 8011388:	2000      	movs	r0, #0
- 801138a:	6031      	str	r1, [r6, #0]
- 801138c:	602b      	str	r3, [r5, #0]
- 801138e:	b016      	add	sp, #88	; 0x58
- 8011390:	bd70      	pop	{r4, r5, r6, pc}
- 8011392:	466a      	mov	r2, sp
- 8011394:	f000 f87c 	bl	8011490 <_fstat_r>
- 8011398:	2800      	cmp	r0, #0
- 801139a:	dbec      	blt.n	8011376 <__swhatbuf_r+0x12>
- 801139c:	9901      	ldr	r1, [sp, #4]
- 801139e:	f401 4170 	and.w	r1, r1, #61440	; 0xf000
- 80113a2:	f5a1 5300 	sub.w	r3, r1, #8192	; 0x2000
- 80113a6:	4259      	negs	r1, r3
- 80113a8:	4159      	adcs	r1, r3
- 80113aa:	f44f 6380 	mov.w	r3, #1024	; 0x400
- 80113ae:	e7eb      	b.n	8011388 <__swhatbuf_r+0x24>
-
-080113b0 <__smakebuf_r>:
- 80113b0:	898b      	ldrh	r3, [r1, #12]
- 80113b2:	b573      	push	{r0, r1, r4, r5, r6, lr}
- 80113b4:	079d      	lsls	r5, r3, #30
- 80113b6:	4606      	mov	r6, r0
- 80113b8:	460c      	mov	r4, r1
- 80113ba:	d507      	bpl.n	80113cc <__smakebuf_r+0x1c>
- 80113bc:	f104 0347 	add.w	r3, r4, #71	; 0x47
- 80113c0:	6023      	str	r3, [r4, #0]
- 80113c2:	6123      	str	r3, [r4, #16]
- 80113c4:	2301      	movs	r3, #1
- 80113c6:	6163      	str	r3, [r4, #20]
- 80113c8:	b002      	add	sp, #8
- 80113ca:	bd70      	pop	{r4, r5, r6, pc}
- 80113cc:	ab01      	add	r3, sp, #4
- 80113ce:	466a      	mov	r2, sp
- 80113d0:	f7ff ffc8 	bl	8011364 <__swhatbuf_r>
- 80113d4:	9900      	ldr	r1, [sp, #0]
- 80113d6:	4605      	mov	r5, r0
- 80113d8:	4630      	mov	r0, r6
- 80113da:	f7ff fe77 	bl	80110cc <_malloc_r>
- 80113de:	b948      	cbnz	r0, 80113f4 <__smakebuf_r+0x44>
- 80113e0:	f9b4 300c 	ldrsh.w	r3, [r4, #12]
- 80113e4:	059a      	lsls	r2, r3, #22
- 80113e6:	d4ef      	bmi.n	80113c8 <__smakebuf_r+0x18>
- 80113e8:	f023 0303 	bic.w	r3, r3, #3
- 80113ec:	f043 0302 	orr.w	r3, r3, #2
- 80113f0:	81a3      	strh	r3, [r4, #12]
- 80113f2:	e7e3      	b.n	80113bc <__smakebuf_r+0xc>
- 80113f4:	89a3      	ldrh	r3, [r4, #12]
- 80113f6:	6020      	str	r0, [r4, #0]
- 80113f8:	f043 0380 	orr.w	r3, r3, #128	; 0x80
- 80113fc:	81a3      	strh	r3, [r4, #12]
- 80113fe:	9b00      	ldr	r3, [sp, #0]
- 8011400:	6163      	str	r3, [r4, #20]
- 8011402:	9b01      	ldr	r3, [sp, #4]
- 8011404:	6120      	str	r0, [r4, #16]
- 8011406:	b15b      	cbz	r3, 8011420 <__smakebuf_r+0x70>
- 8011408:	f9b4 100e 	ldrsh.w	r1, [r4, #14]
- 801140c:	4630      	mov	r0, r6
- 801140e:	f000 f851 	bl	80114b4 <_isatty_r>
- 8011412:	b128      	cbz	r0, 8011420 <__smakebuf_r+0x70>
- 8011414:	89a3      	ldrh	r3, [r4, #12]
- 8011416:	f023 0303 	bic.w	r3, r3, #3
- 801141a:	f043 0301 	orr.w	r3, r3, #1
- 801141e:	81a3      	strh	r3, [r4, #12]
- 8011420:	89a3      	ldrh	r3, [r4, #12]
- 8011422:	431d      	orrs	r5, r3
- 8011424:	81a5      	strh	r5, [r4, #12]
- 8011426:	e7cf      	b.n	80113c8 <__smakebuf_r+0x18>
-
-08011428 <_putc_r>:
- 8011428:	b570      	push	{r4, r5, r6, lr}
- 801142a:	460d      	mov	r5, r1
- 801142c:	4614      	mov	r4, r2
- 801142e:	4606      	mov	r6, r0
- 8011430:	b118      	cbz	r0, 801143a <_putc_r+0x12>
- 8011432:	6a03      	ldr	r3, [r0, #32]
- 8011434:	b90b      	cbnz	r3, 801143a <_putc_r+0x12>
- 8011436:	f7ff fb37 	bl	8010aa8 <__sinit>
- 801143a:	6e63      	ldr	r3, [r4, #100]	; 0x64
- 801143c:	07d8      	lsls	r0, r3, #31
- 801143e:	d405      	bmi.n	801144c <_putc_r+0x24>
- 8011440:	89a3      	ldrh	r3, [r4, #12]
- 8011442:	0599      	lsls	r1, r3, #22
- 8011444:	d402      	bmi.n	801144c <_putc_r+0x24>
- 8011446:	6da0      	ldr	r0, [r4, #88]	; 0x58
- 8011448:	f7ff fd9d 	bl	8010f86 <__retarget_lock_acquire_recursive>
- 801144c:	68a3      	ldr	r3, [r4, #8]
- 801144e:	3b01      	subs	r3, #1
- 8011450:	2b00      	cmp	r3, #0
- 8011452:	60a3      	str	r3, [r4, #8]
- 8011454:	da05      	bge.n	8011462 <_putc_r+0x3a>
- 8011456:	69a2      	ldr	r2, [r4, #24]
- 8011458:	4293      	cmp	r3, r2
- 801145a:	db12      	blt.n	8011482 <_putc_r+0x5a>
- 801145c:	b2eb      	uxtb	r3, r5
- 801145e:	2b0a      	cmp	r3, #10
- 8011460:	d00f      	beq.n	8011482 <_putc_r+0x5a>
- 8011462:	6823      	ldr	r3, [r4, #0]
- 8011464:	1c5a      	adds	r2, r3, #1
- 8011466:	6022      	str	r2, [r4, #0]
- 8011468:	701d      	strb	r5, [r3, #0]
- 801146a:	b2ed      	uxtb	r5, r5
- 801146c:	6e63      	ldr	r3, [r4, #100]	; 0x64
- 801146e:	07da      	lsls	r2, r3, #31
- 8011470:	d405      	bmi.n	801147e <_putc_r+0x56>
- 8011472:	89a3      	ldrh	r3, [r4, #12]
- 8011474:	059b      	lsls	r3, r3, #22
- 8011476:	d402      	bmi.n	801147e <_putc_r+0x56>
- 8011478:	6da0      	ldr	r0, [r4, #88]	; 0x58
- 801147a:	f7ff fd85 	bl	8010f88 <__retarget_lock_release_recursive>
- 801147e:	4628      	mov	r0, r5
- 8011480:	bd70      	pop	{r4, r5, r6, pc}
- 8011482:	4629      	mov	r1, r5
- 8011484:	4622      	mov	r2, r4
- 8011486:	4630      	mov	r0, r6
- 8011488:	f7ff fc57 	bl	8010d3a <__swbuf_r>
- 801148c:	4605      	mov	r5, r0
- 801148e:	e7ed      	b.n	801146c <_putc_r+0x44>
-
-08011490 <_fstat_r>:
- 8011490:	b538      	push	{r3, r4, r5, lr}
- 8011492:	4d07      	ldr	r5, [pc, #28]	; (80114b0 <_fstat_r+0x20>)
- 8011494:	2300      	movs	r3, #0
- 8011496:	4604      	mov	r4, r0
- 8011498:	4608      	mov	r0, r1
- 801149a:	4611      	mov	r1, r2
- 801149c:	602b      	str	r3, [r5, #0]
- 801149e:	f7ef fabc 	bl	8000a1a <_fstat>
- 80114a2:	1c43      	adds	r3, r0, #1
- 80114a4:	d102      	bne.n	80114ac <_fstat_r+0x1c>
- 80114a6:	682b      	ldr	r3, [r5, #0]
- 80114a8:	b103      	cbz	r3, 80114ac <_fstat_r+0x1c>
- 80114aa:	6023      	str	r3, [r4, #0]
- 80114ac:	bd38      	pop	{r3, r4, r5, pc}
- 80114ae:	bf00      	nop
- 80114b0:	24007e08 	.word	0x24007e08
-
-080114b4 <_isatty_r>:
- 80114b4:	b538      	push	{r3, r4, r5, lr}
- 80114b6:	4d06      	ldr	r5, [pc, #24]	; (80114d0 <_isatty_r+0x1c>)
- 80114b8:	2300      	movs	r3, #0
- 80114ba:	4604      	mov	r4, r0
- 80114bc:	4608      	mov	r0, r1
- 80114be:	602b      	str	r3, [r5, #0]
- 80114c0:	f7ef fabb 	bl	8000a3a <_isatty>
- 80114c4:	1c43      	adds	r3, r0, #1
- 80114c6:	d102      	bne.n	80114ce <_isatty_r+0x1a>
- 80114c8:	682b      	ldr	r3, [r5, #0]
- 80114ca:	b103      	cbz	r3, 80114ce <_isatty_r+0x1a>
- 80114cc:	6023      	str	r3, [r4, #0]
- 80114ce:	bd38      	pop	{r3, r4, r5, pc}
- 80114d0:	24007e08 	.word	0x24007e08
-
-080114d4 <_sbrk_r>:
- 80114d4:	b538      	push	{r3, r4, r5, lr}
- 80114d6:	4d06      	ldr	r5, [pc, #24]	; (80114f0 <_sbrk_r+0x1c>)
- 80114d8:	2300      	movs	r3, #0
- 80114da:	4604      	mov	r4, r0
- 80114dc:	4608      	mov	r0, r1
- 80114de:	602b      	str	r3, [r5, #0]
- 80114e0:	f7ef fac4 	bl	8000a6c <_sbrk>
- 80114e4:	1c43      	adds	r3, r0, #1
- 80114e6:	d102      	bne.n	80114ee <_sbrk_r+0x1a>
- 80114e8:	682b      	ldr	r3, [r5, #0]
- 80114ea:	b103      	cbz	r3, 80114ee <_sbrk_r+0x1a>
- 80114ec:	6023      	str	r3, [r4, #0]
- 80114ee:	bd38      	pop	{r3, r4, r5, pc}
- 80114f0:	24007e08 	.word	0x24007e08
-
-080114f4 <abort>:
- 80114f4:	b508      	push	{r3, lr}
- 80114f6:	2006      	movs	r0, #6
- 80114f8:	f000 f82c 	bl	8011554 <raise>
- 80114fc:	2001      	movs	r0, #1
- 80114fe:	f7ef fa59 	bl	80009b4 <_exit>
-
-08011502 <_raise_r>:
- 8011502:	291f      	cmp	r1, #31
- 8011504:	b538      	push	{r3, r4, r5, lr}
- 8011506:	4604      	mov	r4, r0
- 8011508:	460d      	mov	r5, r1
- 801150a:	d904      	bls.n	8011516 <_raise_r+0x14>
- 801150c:	2316      	movs	r3, #22
- 801150e:	6003      	str	r3, [r0, #0]
- 8011510:	f04f 30ff 	mov.w	r0, #4294967295
- 8011514:	bd38      	pop	{r3, r4, r5, pc}
- 8011516:	6bc2      	ldr	r2, [r0, #60]	; 0x3c
- 8011518:	b112      	cbz	r2, 8011520 <_raise_r+0x1e>
- 801151a:	f852 3021 	ldr.w	r3, [r2, r1, lsl #2]
- 801151e:	b94b      	cbnz	r3, 8011534 <_raise_r+0x32>
- 8011520:	4620      	mov	r0, r4
- 8011522:	f000 f831 	bl	8011588 <_getpid_r>
- 8011526:	462a      	mov	r2, r5
- 8011528:	4601      	mov	r1, r0
- 801152a:	4620      	mov	r0, r4
- 801152c:	e8bd 4038 	ldmia.w	sp!, {r3, r4, r5, lr}
- 8011530:	f000 b818 	b.w	8011564 <_kill_r>
- 8011534:	2b01      	cmp	r3, #1
- 8011536:	d00a      	beq.n	801154e <_raise_r+0x4c>
- 8011538:	1c59      	adds	r1, r3, #1
- 801153a:	d103      	bne.n	8011544 <_raise_r+0x42>
- 801153c:	2316      	movs	r3, #22
- 801153e:	6003      	str	r3, [r0, #0]
- 8011540:	2001      	movs	r0, #1
- 8011542:	e7e7      	b.n	8011514 <_raise_r+0x12>
- 8011544:	2400      	movs	r4, #0
- 8011546:	f842 4025 	str.w	r4, [r2, r5, lsl #2]
- 801154a:	4628      	mov	r0, r5
- 801154c:	4798      	blx	r3
- 801154e:	2000      	movs	r0, #0
- 8011550:	e7e0      	b.n	8011514 <_raise_r+0x12>
-	...
-
-08011554 <raise>:
- 8011554:	4b02      	ldr	r3, [pc, #8]	; (8011560 <raise+0xc>)
- 8011556:	4601      	mov	r1, r0
- 8011558:	6818      	ldr	r0, [r3, #0]
- 801155a:	f7ff bfd2 	b.w	8011502 <_raise_r>
- 801155e:	bf00      	nop
- 8011560:	240000cc 	.word	0x240000cc
-
-08011564 <_kill_r>:
- 8011564:	b538      	push	{r3, r4, r5, lr}
- 8011566:	4d07      	ldr	r5, [pc, #28]	; (8011584 <_kill_r+0x20>)
- 8011568:	2300      	movs	r3, #0
- 801156a:	4604      	mov	r4, r0
- 801156c:	4608      	mov	r0, r1
- 801156e:	4611      	mov	r1, r2
- 8011570:	602b      	str	r3, [r5, #0]
- 8011572:	f7ef fa0d 	bl	8000990 <_kill>
- 8011576:	1c43      	adds	r3, r0, #1
- 8011578:	d102      	bne.n	8011580 <_kill_r+0x1c>
- 801157a:	682b      	ldr	r3, [r5, #0]
- 801157c:	b103      	cbz	r3, 8011580 <_kill_r+0x1c>
- 801157e:	6023      	str	r3, [r4, #0]
- 8011580:	bd38      	pop	{r3, r4, r5, pc}
- 8011582:	bf00      	nop
- 8011584:	24007e08 	.word	0x24007e08
-
-08011588 <_getpid_r>:
- 8011588:	f7ef b9fa 	b.w	8000980 <_getpid>
-
-0801158c <_init>:
- 801158c:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
- 801158e:	bf00      	nop
- 8011590:	bcf8      	pop	{r3, r4, r5, r6, r7}
- 8011592:	bc08      	pop	{r3}
- 8011594:	469e      	mov	lr, r3
- 8011596:	4770      	bx	lr
-
-08011598 <_fini>:
- 8011598:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
- 801159a:	bf00      	nop
- 801159c:	bcf8      	pop	{r3, r4, r5, r6, r7}
- 801159e:	bc08      	pop	{r3}
- 80115a0:	469e      	mov	lr, r3
- 80115a2:	4770      	bx	lr
diff --git a/Debug/makefile b/Debug/makefile
index e78f415..cca620f 100644
--- a/Debug/makefile
+++ b/Debug/makefile
@@ -9,6 +9,7 @@ RM := rm -rf
 
 # All of the sources participating in the build are defined here
 -include sources.mk
+-include Middlewares/Third_Party/LwIP/system/OS/subdir.mk
 -include Middlewares/Third_Party/LwIP/src/netif/ppp/subdir.mk
 -include Middlewares/Third_Party/LwIP/src/netif/subdir.mk
 -include Middlewares/Third_Party/LwIP/src/core/ipv6/subdir.mk
@@ -16,9 +17,17 @@ RM := rm -rf
 -include Middlewares/Third_Party/LwIP/src/core/subdir.mk
 -include Middlewares/Third_Party/LwIP/src/apps/mqtt/subdir.mk
 -include Middlewares/Third_Party/LwIP/src/api/subdir.mk
+-include Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/subdir.mk
+-include Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/subdir.mk
+-include Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/subdir.mk
+-include Middlewares/Third_Party/FreeRTOS/Source/subdir.mk
+-include Middlewares/Third_Party/FatFs/src/option/subdir.mk
+-include Middlewares/Third_Party/FatFs/src/subdir.mk
 -include LWIP/Target/subdir.mk
 -include LWIP/App/subdir.mk
--include LWFTP/subdir.mk
+-include LWFTPC/subdir.mk
+-include FATFS/Target/subdir.mk
+-include FATFS/App/subdir.mk
 -include Drivers/STM32H7xx_HAL_Driver/Src/subdir.mk
 -include Drivers/BSP/Components/lan8742/subdir.mk
 -include Core/Startup/subdir.mk
@@ -45,34 +54,34 @@ $(wildcard ../makefile.init) \
 $(wildcard ../makefile.targets) \
 
 
-BUILD_ARTIFACT_NAME := lwip_test
+BUILD_ARTIFACT_NAME := TBD_TaxiBoard
 BUILD_ARTIFACT_EXTENSION := elf
 BUILD_ARTIFACT_PREFIX :=
 BUILD_ARTIFACT := $(BUILD_ARTIFACT_PREFIX)$(BUILD_ARTIFACT_NAME)$(if $(BUILD_ARTIFACT_EXTENSION),.$(BUILD_ARTIFACT_EXTENSION),)
 
 # Add inputs and outputs from these tool invocations to the build variables 
 EXECUTABLES += \
-lwip_test.elf \
+TBD_TaxiBoard.elf \
 
 MAP_FILES += \
-lwip_test.map \
+TBD_TaxiBoard.map \
 
 SIZE_OUTPUT += \
 default.size.stdout \
 
 OBJDUMP_LIST += \
-lwip_test.list \
+TBD_TaxiBoard.list \
 
 
 # All Target
 all: main-build
 
 # Main-build Target
-main-build: lwip_test.elf secondary-outputs
+main-build: TBD_TaxiBoard.elf secondary-outputs
 
 # Tool invocations
-lwip_test.elf lwip_test.map: $(OBJS) $(USER_OBJS) C:\_NoSleep\STM32\lwip_test\STM32H723VGHX_FLASH.ld makefile objects.list $(OPTIONAL_TOOL_DEPS)
-	arm-none-eabi-gcc -o "lwip_test.elf" @"objects.list" $(USER_OBJS) $(LIBS) -mcpu=cortex-m7 -T"C:\_NoSleep\STM32\lwip_test\STM32H723VGHX_FLASH.ld" --specs=nosys.specs -Wl,-Map="lwip_test.map" -Wl,--gc-sections -static --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -Wl,--start-group -lc -lm -Wl,--end-group
+TBD_TaxiBoard.elf TBD_TaxiBoard.map: $(OBJS) $(USER_OBJS) C:\_NoSleep\STM32\TBD_TaxiBoard\STM32H723VGHX_FLASH.ld makefile objects.list $(OPTIONAL_TOOL_DEPS)
+	arm-none-eabi-gcc -o "TBD_TaxiBoard.elf" @"objects.list" $(USER_OBJS) $(LIBS) -mcpu=cortex-m7 -T"C:\_NoSleep\STM32\TBD_TaxiBoard\STM32H723VGHX_FLASH.ld" --specs=nosys.specs -Wl,-Map="TBD_TaxiBoard.map" -Wl,--gc-sections -static --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -Wl,--start-group -lc -lm -Wl,--end-group
 	@echo 'Finished building target: $@'
 	@echo ' '
 
@@ -81,14 +90,14 @@ default.size.stdout: $(EXECUTABLES) makefile objects.list $(OPTIONAL_TOOL_DEPS)
 	@echo 'Finished building: $@'
 	@echo ' '
 
-lwip_test.list: $(EXECUTABLES) makefile objects.list $(OPTIONAL_TOOL_DEPS)
-	arm-none-eabi-objdump -h -S $(EXECUTABLES) > "lwip_test.list"
+TBD_TaxiBoard.list: $(EXECUTABLES) makefile objects.list $(OPTIONAL_TOOL_DEPS)
+	arm-none-eabi-objdump -h -S $(EXECUTABLES) > "TBD_TaxiBoard.list"
 	@echo 'Finished building: $@'
 	@echo ' '
 
 # Other Targets
 clean:
-	-$(RM) default.size.stdout lwip_test.elf lwip_test.list lwip_test.map
+	-$(RM) TBD_TaxiBoard.elf TBD_TaxiBoard.list TBD_TaxiBoard.map default.size.stdout
 	-@echo ' '
 
 secondary-outputs: $(SIZE_OUTPUT) $(OBJDUMP_LIST)
diff --git a/Debug/objects.list b/Debug/objects.list
index bae596b..a0660f3 100644
--- a/Debug/objects.list
+++ b/Debug/objects.list
@@ -1,5 +1,7 @@
+"./Core/Src/freertos.o"
 "./Core/Src/main.o"
 "./Core/Src/stm32h7xx_hal_msp.o"
+"./Core/Src/stm32h7xx_hal_timebase_tim.o"
 "./Core/Src/stm32h7xx_it.o"
 "./Core/Src/syscalls.o"
 "./Core/Src/sysmem.o"
@@ -13,6 +15,7 @@
 "./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o"
 "./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.o"
 "./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.o"
+"./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o"
 "./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.o"
 "./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.o"
 "./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.o"
@@ -24,12 +27,36 @@
 "./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.o"
 "./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.o"
 "./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.o"
+"./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.o"
+"./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd_ex.o"
 "./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.o"
 "./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.o"
-"./LWFTP/lwftp.o"
-"./LWFTP/lwftp_mod.o"
+"./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.o"
+"./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.o"
+"./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_delayblock.o"
+"./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.o"
+"./FATFS/App/fatfs.o"
+"./FATFS/Target/bsp_driver_sd.o"
+"./FATFS/Target/fatfs_platform.o"
+"./FATFS/Target/sd_diskio.o"
+"./LWFTPC/lwftpc.o"
 "./LWIP/App/lwip.o"
 "./LWIP/Target/ethernetif.o"
+"./Middlewares/Third_Party/FatFs/src/diskio.o"
+"./Middlewares/Third_Party/FatFs/src/ff.o"
+"./Middlewares/Third_Party/FatFs/src/ff_gen_drv.o"
+"./Middlewares/Third_Party/FatFs/src/option/ccsbcs.o"
+"./Middlewares/Third_Party/FatFs/src/option/syscall.o"
+"./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o"
+"./Middlewares/Third_Party/FreeRTOS/Source/croutine.o"
+"./Middlewares/Third_Party/FreeRTOS/Source/event_groups.o"
+"./Middlewares/Third_Party/FreeRTOS/Source/list.o"
+"./Middlewares/Third_Party/FreeRTOS/Source/queue.o"
+"./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o"
+"./Middlewares/Third_Party/FreeRTOS/Source/tasks.o"
+"./Middlewares/Third_Party/FreeRTOS/Source/timers.o"
+"./Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.o"
+"./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o"
 "./Middlewares/Third_Party/LwIP/src/api/api_lib.o"
 "./Middlewares/Third_Party/LwIP/src/api/api_msg.o"
 "./Middlewares/Third_Party/LwIP/src/api/err.o"
@@ -110,3 +137,4 @@
 "./Middlewares/Third_Party/LwIP/src/netif/ppp/upap.o"
 "./Middlewares/Third_Party/LwIP/src/netif/ppp/utils.o"
 "./Middlewares/Third_Party/LwIP/src/netif/ppp/vj.o"
+"./Middlewares/Third_Party/LwIP/system/OS/sys_arch.o"
diff --git a/Debug/sources.mk b/Debug/sources.mk
index 5035afa..2d46f72 100644
--- a/Debug/sources.mk
+++ b/Debug/sources.mk
@@ -26,9 +26,17 @@ Core/Src \
 Core/Startup \
 Drivers/BSP/Components/lan8742 \
 Drivers/STM32H7xx_HAL_Driver/Src \
-LWFTP \
+FATFS/App \
+FATFS/Target \
+LWFTPC \
 LWIP/App \
 LWIP/Target \
+Middlewares/Third_Party/FatFs/src \
+Middlewares/Third_Party/FatFs/src/option \
+Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS \
+Middlewares/Third_Party/FreeRTOS/Source \
+Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F \
+Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang \
 Middlewares/Third_Party/LwIP/src/api \
 Middlewares/Third_Party/LwIP/src/apps/mqtt \
 Middlewares/Third_Party/LwIP/src/core \
@@ -36,4 +44,5 @@ Middlewares/Third_Party/LwIP/src/core/ipv4 \
 Middlewares/Third_Party/LwIP/src/core/ipv6 \
 Middlewares/Third_Party/LwIP/src/netif \
 Middlewares/Third_Party/LwIP/src/netif/ppp \
+Middlewares/Third_Party/LwIP/system/OS \
 
diff --git a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h
new file mode 100644
index 0000000..47f1fac
--- /dev/null
+++ b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h
@@ -0,0 +1,2422 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_fdcan.h
+  * @author  MCD Application Team
+  * @brief   Header file of FDCAN HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_HAL_FDCAN_H
+#define STM32H7xx_HAL_FDCAN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal_def.h"
+
+#if defined(FDCAN1)
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup FDCAN
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup FDCAN_Exported_Types FDCAN Exported Types
+  * @{
+  */
+
+/**
+  * @brief HAL State structures definition
+  */
+typedef enum
+{
+  HAL_FDCAN_STATE_RESET      = 0x00U, /*!< FDCAN not yet initialized or disabled */
+  HAL_FDCAN_STATE_READY      = 0x01U, /*!< FDCAN initialized and ready for use   */
+  HAL_FDCAN_STATE_BUSY       = 0x02U, /*!< FDCAN process is ongoing              */
+  HAL_FDCAN_STATE_ERROR      = 0x03U  /*!< FDCAN error state                     */
+} HAL_FDCAN_StateTypeDef;
+
+/**
+  * @brief FDCAN Init structure definition
+  */
+typedef struct
+{
+  uint32_t FrameFormat;                  /*!< Specifies the FDCAN frame format.
+                                              This parameter can be a value of @ref FDCAN_frame_format     */
+
+  uint32_t Mode;                         /*!< Specifies the FDCAN mode.
+                                              This parameter can be a value of @ref FDCAN_operating_mode   */
+
+  FunctionalState AutoRetransmission;    /*!< Enable or disable the automatic retransmission mode.
+                                              This parameter can be set to ENABLE or DISABLE               */
+
+  FunctionalState TransmitPause;         /*!< Enable or disable the Transmit Pause feature.
+                                              This parameter can be set to ENABLE or DISABLE               */
+
+  FunctionalState ProtocolException;      /*!< Enable or disable the Protocol Exception Handling.
+                                              This parameter can be set to ENABLE or DISABLE               */
+
+  uint32_t NominalPrescaler;             /*!< Specifies the value by which the oscillator frequency is
+                                              divided for generating the nominal bit time quanta.
+                                              This parameter must be a number between 1 and 512            */
+
+  uint32_t NominalSyncJumpWidth;         /*!< Specifies the maximum number of time quanta the FDCAN
+                                              hardware is allowed to lengthen or shorten a bit to perform
+                                              resynchronization.
+                                              This parameter must be a number between 1 and 128            */
+
+  uint32_t NominalTimeSeg1;              /*!< Specifies the number of time quanta in Bit Segment 1.
+                                              This parameter must be a number between 2 and 256            */
+
+  uint32_t NominalTimeSeg2;              /*!< Specifies the number of time quanta in Bit Segment 2.
+                                              This parameter must be a number between 2 and 128            */
+
+  uint32_t DataPrescaler;                /*!< Specifies the value by which the oscillator frequency is
+                                              divided for generating the data bit time quanta.
+                                              This parameter must be a number between 1 and 32             */
+
+  uint32_t DataSyncJumpWidth;            /*!< Specifies the maximum number of time quanta the FDCAN
+                                              hardware is allowed to lengthen or shorten a data bit to
+                                              perform resynchronization.
+                                              This parameter must be a number between 1 and 16             */
+
+  uint32_t DataTimeSeg1;                 /*!< Specifies the number of time quanta in Data Bit Segment 1.
+                                              This parameter must be a number between 1 and 32             */
+
+  uint32_t DataTimeSeg2;                 /*!< Specifies the number of time quanta in Data Bit Segment 2.
+                                              This parameter must be a number between 1 and 16             */
+
+  uint32_t MessageRAMOffset;             /*!< Specifies the message RAM start address.
+                                              This parameter must be a number between 0 and 2560           */
+
+  uint32_t StdFiltersNbr;                /*!< Specifies the number of standard Message ID filters.
+                                              This parameter must be a number between 0 and 128            */
+
+  uint32_t ExtFiltersNbr;                /*!< Specifies the number of extended Message ID filters.
+                                              This parameter must be a number between 0 and 64             */
+
+  uint32_t RxFifo0ElmtsNbr;              /*!< Specifies the number of Rx FIFO0 Elements.
+                                              This parameter must be a number between 0 and 64             */
+
+  uint32_t RxFifo0ElmtSize;              /*!< Specifies the Data Field Size in an Rx FIFO 0 element.
+                                              This parameter can be a value of @ref FDCAN_data_field_size  */
+
+  uint32_t RxFifo1ElmtsNbr;              /*!< Specifies the number of Rx FIFO 1 Elements.
+                                              This parameter must be a number between 0 and 64             */
+
+  uint32_t RxFifo1ElmtSize;              /*!< Specifies the Data Field Size in an Rx FIFO 1 element.
+                                              This parameter can be a value of @ref FDCAN_data_field_size  */
+
+  uint32_t RxBuffersNbr;                 /*!< Specifies the number of Dedicated Rx Buffer elements.
+                                              This parameter must be a number between 0 and 64             */
+
+  uint32_t RxBufferSize;                 /*!< Specifies the Data Field Size in an Rx Buffer element.
+                                              This parameter can be a value of @ref FDCAN_data_field_size  */
+
+  uint32_t TxEventsNbr;                  /*!< Specifies the number of Tx Event FIFO elements.
+                                              This parameter must be a number between 0 and 32             */
+
+  uint32_t TxBuffersNbr;                 /*!< Specifies the number of Dedicated Tx Buffers.
+                                              This parameter must be a number between 0 and 32             */
+
+  uint32_t TxFifoQueueElmtsNbr;          /*!< Specifies the number of Tx Buffers used for Tx FIFO/Queue.
+                                              This parameter must be a number between 0 and 32             */
+
+  uint32_t TxFifoQueueMode;              /*!< Tx FIFO/Queue Mode selection.
+                                              This parameter can be a value of @ref FDCAN_txFifoQueue_Mode */
+
+  uint32_t TxElmtSize;                   /*!< Specifies the Data Field Size in a Tx Element.
+                                              This parameter can be a value of @ref FDCAN_data_field_size  */
+
+} FDCAN_InitTypeDef;
+
+/**
+  * @brief  FDCAN clock calibration unit structure definition
+  */
+typedef struct
+{
+  uint32_t ClockCalibration;     /*!< Enable or disable the clock calibration.
+                                      This parameter can be a value of @ref FDCAN_clock_calibration.       */
+
+  uint32_t ClockDivider;         /*!< Specifies the FDCAN kernel clock divider when the clock calibration
+                                      is bypassed.
+                                      This parameter can be a value of @ref FDCAN_clock_divider            */
+
+  uint32_t MinOscClkPeriods;     /*!< Configures the minimum number of periods in two CAN bit times. The
+                                      actual configured number of periods is MinOscClkPeriods x 32.
+                                      This parameter must be a number between 0x00 and 0xFF                */
+
+  uint32_t CalFieldLength;       /*!< Specifies the calibration field length.
+                                      This parameter can be a value of @ref FDCAN_calibration_field_length */
+
+  uint32_t TimeQuantaPerBitTime; /*!< Configures the number of time quanta per bit time.
+                                      This parameter must be a number between 4 and 25                     */
+
+  uint32_t WatchdogStartValue;   /*!< Start value of the Calibration Watchdog Counter.
+                                      If set to zero the counter is disabled.
+                                      This parameter must be a number between 0x0000 and 0xFFFF            */
+
+} FDCAN_ClkCalUnitTypeDef;
+
+/**
+  * @brief  FDCAN filter structure definition
+  */
+typedef struct
+{
+  uint32_t IdType;           /*!< Specifies the identifier type.
+                                  This parameter can be a value of @ref FDCAN_id_type       */
+
+  uint32_t FilterIndex;      /*!< Specifies the filter which will be initialized.
+                                  This parameter must be a number between:
+                                   - 0 and 127, if IdType is FDCAN_STANDARD_ID
+                                   - 0 and 63, if IdType is FDCAN_EXTENDED_ID               */
+
+  uint32_t FilterType;       /*!< Specifies the filter type.
+                                  This parameter can be a value of @ref FDCAN_filter_type.
+                                  The value FDCAN_EXT_FILTER_RANGE_NO_EIDM is permitted
+                                  only when IdType is FDCAN_EXTENDED_ID.
+                                  This parameter is ignored if FilterConfig is set to
+                                  FDCAN_FILTER_TO_RXBUFFER                                  */
+
+  uint32_t FilterConfig;     /*!< Specifies the filter configuration.
+                                  This parameter can be a value of @ref FDCAN_filter_config */
+
+  uint32_t FilterID1;        /*!< Specifies the filter identification 1.
+                                  This parameter must be a number between:
+                                   - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID
+                                   - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID       */
+
+  uint32_t FilterID2;        /*!< Specifies the filter identification 2.
+                                  This parameter is ignored if FilterConfig is set to
+                                  FDCAN_FILTER_TO_RXBUFFER.
+                                  This parameter must be a number between:
+                                   - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID
+                                   - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID       */
+
+  uint32_t RxBufferIndex;    /*!< Contains the index of the Rx buffer in which the
+                                  matching message will be stored.
+                                  This parameter must be a number between 0 and 63.
+                                  This parameter is ignored if FilterConfig is different
+                                  from FDCAN_FILTER_TO_RXBUFFER                             */
+
+  uint32_t IsCalibrationMsg; /*!< Specifies whether the filter is configured for
+                                  calibration messages.
+                                  This parameter is ignored if FilterConfig is different
+                                  from FDCAN_FILTER_TO_RXBUFFER.
+                                  This parameter can be:
+                                   - 0 : ordinary message
+                                   - 1 : calibration message                                */
+
+} FDCAN_FilterTypeDef;
+
+/**
+  * @brief  FDCAN Tx header structure definition
+  */
+typedef struct
+{
+  uint32_t Identifier;          /*!< Specifies the identifier.
+                                     This parameter must be a number between:
+                                      - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID
+                                      - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID               */
+
+  uint32_t IdType;              /*!< Specifies the identifier type for the message that will be
+                                     transmitted.
+                                     This parameter can be a value of @ref FDCAN_id_type               */
+
+  uint32_t TxFrameType;         /*!< Specifies the frame type of the message that will be transmitted.
+                                     This parameter can be a value of @ref FDCAN_frame_type            */
+
+  uint32_t DataLength;          /*!< Specifies the length of the frame that will be transmitted.
+                                      This parameter can be a value of @ref FDCAN_data_length_code     */
+
+  uint32_t ErrorStateIndicator; /*!< Specifies the error state indicator.
+                                     This parameter can be a value of @ref FDCAN_error_state_indicator */
+
+  uint32_t BitRateSwitch;       /*!< Specifies whether the Tx frame will be transmitted with or without
+                                     bit rate switching.
+                                     This parameter can be a value of @ref FDCAN_bit_rate_switching    */
+
+  uint32_t FDFormat;            /*!< Specifies whether the Tx frame will be transmitted in classic or
+                                     FD format.
+                                     This parameter can be a value of @ref FDCAN_format                */
+
+  uint32_t TxEventFifoControl;  /*!< Specifies the event FIFO control.
+                                     This parameter can be a value of @ref FDCAN_EFC                   */
+
+  uint32_t MessageMarker;       /*!< Specifies the message marker to be copied into Tx Event FIFO
+                                     element for identification of Tx message status.
+                                     This parameter must be a number between 0 and 0xFF                */
+
+} FDCAN_TxHeaderTypeDef;
+
+/**
+  * @brief  FDCAN Rx header structure definition
+  */
+typedef struct
+{
+  uint32_t Identifier;            /*!< Specifies the identifier.
+                                       This parameter must be a number between:
+                                        - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID
+                                        - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID               */
+
+  uint32_t IdType;                /*!< Specifies the identifier type of the received message.
+                                       This parameter can be a value of @ref FDCAN_id_type               */
+
+  uint32_t RxFrameType;           /*!< Specifies the the received message frame type.
+                                       This parameter can be a value of @ref FDCAN_frame_type            */
+
+  uint32_t DataLength;            /*!< Specifies the received frame length.
+                                        This parameter can be a value of @ref FDCAN_data_length_code     */
+
+  uint32_t ErrorStateIndicator;   /*!< Specifies the error state indicator.
+                                       This parameter can be a value of @ref FDCAN_error_state_indicator */
+
+  uint32_t BitRateSwitch;         /*!< Specifies whether the Rx frame is received with or without bit
+                                       rate switching.
+                                       This parameter can be a value of @ref FDCAN_bit_rate_switching    */
+
+  uint32_t FDFormat;              /*!< Specifies whether the Rx frame is received in classic or FD
+                                       format.
+                                       This parameter can be a value of @ref FDCAN_format                */
+
+  uint32_t RxTimestamp;           /*!< Specifies the timestamp counter value captured on start of frame
+                                       reception.
+                                       This parameter must be a number between 0 and 0xFFFF              */
+
+  uint32_t FilterIndex;           /*!< Specifies the index of matching Rx acceptance filter element.
+                                       This parameter must be a number between:
+                                        - 0 and 127, if IdType is FDCAN_STANDARD_ID
+                                        - 0 and 63, if IdType is FDCAN_EXTENDED_ID
+                                       When the frame is a Non-Filter matching frame, this parameter
+                                       is unused.                                                        */
+
+  uint32_t IsFilterMatchingFrame; /*!< Specifies whether the accepted frame did not match any Rx filter.
+                                       Acceptance of non-matching frames may be enabled via
+                                       HAL_FDCAN_ConfigGlobalFilter().
+                                       This parameter takes 0 if the frame matched an Rx filter or
+                                       1 if it did not match any Rx filter                               */
+
+} FDCAN_RxHeaderTypeDef;
+
+/**
+  * @brief  FDCAN Tx event FIFO structure definition
+  */
+typedef struct
+{
+  uint32_t Identifier;          /*!< Specifies the identifier.
+                                     This parameter must be a number between:
+                                      - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID
+                                      - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID               */
+
+  uint32_t IdType;              /*!< Specifies the identifier type for the transmitted message.
+                                     This parameter can be a value of @ref FDCAN_id_type               */
+
+  uint32_t TxFrameType;         /*!< Specifies the frame type of the transmitted message.
+                                     This parameter can be a value of @ref FDCAN_frame_type            */
+
+  uint32_t DataLength;          /*!< Specifies the length of the transmitted frame.
+                                     This parameter can be a value of @ref FDCAN_data_length_code      */
+
+  uint32_t ErrorStateIndicator; /*!< Specifies the error state indicator.
+                                     This parameter can be a value of @ref FDCAN_error_state_indicator */
+
+  uint32_t BitRateSwitch;       /*!< Specifies whether the Tx frame is transmitted with or without bit
+                                     rate switching.
+                                     This parameter can be a value of @ref FDCAN_bit_rate_switching    */
+
+  uint32_t FDFormat;            /*!< Specifies whether the Tx frame is transmitted in classic or FD
+                                     format.
+                                     This parameter can be a value of @ref FDCAN_format                */
+
+  uint32_t TxTimestamp;         /*!< Specifies the timestamp counter value captured on start of frame
+                                     transmission.
+                                     This parameter must be a number between 0 and 0xFFFF              */
+
+  uint32_t MessageMarker;       /*!< Specifies the message marker copied into Tx Event FIFO element
+                                     for identification of Tx message status.
+                                     This parameter must be a number between 0 and 0xFF                */
+
+  uint32_t EventType;           /*!< Specifies the event type.
+                                     This parameter can be a value of @ref FDCAN_event_type            */
+
+} FDCAN_TxEventFifoTypeDef;
+
+/**
+  * @brief  FDCAN High Priority Message Status structure definition
+  */
+typedef struct
+{
+  uint32_t FilterList;     /*!< Specifies the filter list of the matching filter element.
+                                This parameter can be:
+                                 - 0 : Standard Filter List
+                                 - 1 : Extended Filter List                                */
+
+  uint32_t FilterIndex;    /*!< Specifies the index of matching filter element.
+                                This parameter can be a number between:
+                                - 0 and 127, if FilterList is 0 (Standard)
+                                - 0 and 63, if FilterList is 1 (Extended)                  */
+
+  uint32_t MessageStorage; /*!< Specifies the HP Message Storage.
+                                This parameter can be a value of @ref FDCAN_hp_msg_storage */
+
+  uint32_t MessageIndex;   /*!< Specifies the Index of Rx FIFO element to which the
+                                message was stored.
+                                This parameter is valid only when MessageStorage is:
+                                  FDCAN_HP_STORAGE_RXFIFO0
+                                 or
+                                  FDCAN_HP_STORAGE_RXFIFO1                                 */
+
+} FDCAN_HpMsgStatusTypeDef;
+
+/**
+  * @brief FDCAN Protocol Status structure definition
+  */
+typedef struct
+{
+  uint32_t LastErrorCode;     /*!< Specifies the type of the last error that occurred on the FDCAN bus.
+                                   This parameter can be a value of @ref FDCAN_protocol_error_code                           */
+
+  uint32_t DataLastErrorCode; /*!< Specifies the type of the last error that occurred in the data phase of a CAN FD format
+                                   frame with its BRS flag set.
+                                   This parameter can be a value of @ref FDCAN_protocol_error_code                           */
+
+  uint32_t Activity;          /*!< Specifies the FDCAN module communication state.
+                                   This parameter can be a value of @ref FDCAN_communication_state                           */
+
+  uint32_t ErrorPassive;      /*!< Specifies the FDCAN module error status.
+                                   This parameter can be:
+                                    - 0 : The FDCAN is in Error_Active state
+                                    - 1 : The FDCAN is in Error_Passive state                                                */
+
+  uint32_t Warning;           /*!< Specifies the FDCAN module warning status.
+                                   This parameter can be:
+                                    - 0 : error counters (RxErrorCnt and TxErrorCnt) are below the Error_Warning limit of 96
+                                    - 1 : at least one of error counters has reached the Error_Warning limit of 96           */
+
+  uint32_t BusOff;            /*!< Specifies the FDCAN module Bus_Off status.
+                                   This parameter can be:
+                                    - 0 : The FDCAN is not in Bus_Off state
+                                    - 1 : The FDCAN is in Bus_Off state                                                      */
+
+  uint32_t RxESIflag;         /*!< Specifies ESI flag of last received CAN FD message.
+                                   This parameter can be:
+                                    - 0 : Last received CAN FD message did not have its ESI flag set
+                                    - 1 : Last received CAN FD message had its ESI flag set                                  */
+
+  uint32_t RxBRSflag;         /*!< Specifies BRS flag of last received CAN FD message.
+                                   This parameter can be:
+                                    - 0 : Last received CAN FD message did not have its BRS flag set
+                                    - 1 : Last received CAN FD message had its BRS flag set                                  */
+
+  uint32_t RxFDFflag;         /*!< Specifies if CAN FD message (FDF flag set) has been received since last protocol status.
+                                   This parameter can be:
+                                    - 0 : no CAN FD message received
+                                    - 1 : CAN FD message received                                                            */
+
+  uint32_t ProtocolException; /*!< Specifies the FDCAN module Protocol Exception status.
+                                   This parameter can be:
+                                    - 0 : No protocol exception event occurred since last read access
+                                    - 1 : Protocol exception event occurred                                                  */
+
+  uint32_t TDCvalue;          /*!< Specifies the Transmitter Delay Compensation Value.
+                                   This parameter can be a number between 0 and 127                                          */
+
+} FDCAN_ProtocolStatusTypeDef;
+
+/**
+  * @brief FDCAN Error Counters structure definition
+  */
+typedef struct
+{
+  uint32_t TxErrorCnt;     /*!< Specifies the Transmit Error Counter Value.
+                                This parameter can be a number between 0 and 255                                         */
+
+  uint32_t RxErrorCnt;     /*!< Specifies the Receive Error Counter Value.
+                                This parameter can be a number between 0 and 127                                         */
+
+  uint32_t RxErrorPassive; /*!< Specifies the Receive Error Passive status.
+                                This parameter can be:
+                                 - 0 : The Receive Error Counter (RxErrorCnt) is below the error passive level of 128
+                                 - 1 : The Receive Error Counter (RxErrorCnt) has reached the error passive level of 128 */
+
+  uint32_t ErrorLogging;   /*!< Specifies the Transmit/Receive error logging counter value.
+                                This parameter can be a number between 0 and 255.
+                                This counter is incremented each time when a FDCAN protocol error causes the TxErrorCnt
+                                or the RxErrorCnt to be incremented. The counter stops at 255; the next increment of
+                                TxErrorCnt or RxErrorCnt sets interrupt flag FDCAN_FLAG_ERROR_LOGGING_OVERFLOW           */
+
+} FDCAN_ErrorCountersTypeDef;
+
+/**
+  * @brief FDCAN TT Init structure definition
+  */
+typedef struct
+{
+  uint32_t OperationMode;     /*!< Specifies the FDCAN Operation Mode.
+                                   This parameter can be a value of @ref FDCAN_operation_mode               */
+
+  uint32_t GapEnable;         /*!< Specifies the FDCAN TT Operation.
+                                   This parameter can be a value of @ref FDCAN_TT_operation.
+                                   This parameter is ignored if OperationMode is set to
+                                   FDCAN_TT_COMMUNICATION_LEVEL0                                            */
+
+  uint32_t TimeMaster;        /*!< Specifies whether the instance is a slave or a potential master.
+                                   This parameter can be a value of @ref FDCAN_TT_time_master               */
+
+  uint32_t SyncDevLimit;      /*!< Specifies the Synchronization Deviation Limit SDL of the TUR
+                                   numerator : TUR = (Numerator +/- SDL) / Denominator.
+                                   With : SDL = 2^(SyncDevLimit+5).
+                                   This parameter must be a number between 0 and 7                          */
+
+  uint32_t InitRefTrigOffset; /*!< Specifies the Initial Reference Trigger Offset.
+                                   This parameter must be a number between 0 and 127                        */
+
+  uint32_t ExternalClkSync;   /*!< Enable or disable External Clock Synchronization.
+                                   This parameter can be a value of @ref FDCAN_TT_external_clk_sync.
+                                   This parameter is ignored if OperationMode is set to
+                                   FDCAN_TT_COMMUNICATION_LEVEL1                                            */
+
+  uint32_t AppWdgLimit;       /*!< Specifies the Application Watchdog Limit : maximum time after
+                                   which the application has to serve the application watchdog.
+                                   The application watchdog is incremented once each 256 NTUs.
+                                   The application watchdog can be disabled by setting AppWdgLimit to 0.
+                                   This parameter must be a number between 0 and 255.
+                                   This parameter is ignored if OperationMode is set to
+                                   FDCAN_TT_COMMUNICATION_LEVEL0                                            */
+
+  uint32_t GlobalTimeFilter;  /*!< Enable or disable Global Time Filtering.
+                                   This parameter can be a value of @ref FDCAN_TT_global_time_filtering.
+                                   This parameter is ignored if OperationMode is set to
+                                   FDCAN_TT_COMMUNICATION_LEVEL1                                            */
+
+  uint32_t ClockCalibration;  /*!< Enable or disable Automatic Clock Calibration.
+                                   This parameter can be a value of @ref FDCAN_TT_auto_clk_calibration.
+                                   This parameter is ignored if OperationMode is set to
+                                   FDCAN_TT_COMMUNICATION_LEVEL1                                            */
+
+  uint32_t EvtTrigPolarity;   /*!< Specifies the Event Trigger Polarity.
+                                   This parameter can be a value of @ref FDCAN_TT_event_trig_polarity.
+                                   This parameter is ignored if OperationMode is set to
+                                   FDCAN_TT_COMMUNICATION_LEVEL0                                            */
+
+  uint32_t BasicCyclesNbr;    /*!< Specifies the number of basic cycles in the system matrix.
+                                   This parameter can be a value of @ref FDCAN_TT_basic_cycle_number        */
+
+  uint32_t CycleStartSync;    /*!< Enable or disable synchronization pulse output at pin fdcan1_soc.
+                                   This parameter can be a value of @ref FDCAN_TT_cycle_start_sync          */
+
+  uint32_t TxEnableWindow;    /*!< Specifies the length of Tx enable window in NTUs.
+                                   This parameter must be a number between 1 and 16                         */
+
+  uint32_t ExpTxTrigNbr;      /*!< Specifies the number of expected Tx_Triggers in the system matrix.
+                                   This is the sum of Tx_Triggers for exclusive, single arbitrating and
+                                   merged arbitrating windows.
+                                   This parameter must be a number between 0 and 4095                       */
+
+  uint32_t TURNumerator;      /*!< Specifies the TUR (Time Unit Ratio) numerator.
+                                   It is advised to set this parameter to the largest applicable value.
+                                   This parameter must be a number between 0x10000 and 0x1FFFF              */
+
+  uint32_t TURDenominator;    /*!< Specifies the TUR (Time Unit Ratio) denominator.
+                                   This parameter must be a number between 0x0001 and 0x3FFF                */
+
+  uint32_t TriggerMemoryNbr;  /*!< Specifies the number of trigger memory elements.
+                                   This parameter must be a number between 0 and 64                         */
+
+  uint32_t StopWatchTrigSel;  /*!< Specifies the input to be used as stop watch trigger.
+                                   This parameter can be a value of @ref FDCAN_TT_stop_watch_trig_selection */
+
+  uint32_t EventTrigSel;      /*!< Specifies the input to be used as event trigger.
+                                   This parameter can be a value of @ref FDCAN_TT_event_trig_selection      */
+
+} FDCAN_TT_ConfigTypeDef;
+
+/**
+  * @brief  FDCAN Trigger structure definition
+  */
+typedef struct
+{
+  uint32_t TriggerIndex;  /*!< Specifies the trigger which will be configured.
+                               This parameter must be a number between 0 and 63                                 */
+
+  uint32_t TimeMark;      /*!< Specifies the cycle time for which the trigger becomes active.
+                               This parameter must be a number between 0 and 0xFFFF                             */
+
+  uint32_t RepeatFactor;  /*!< Specifies the trigger repeat factor.
+                               This parameter can be a value of @ref FDCAN_TT_Repeat_Factor                     */
+
+  uint32_t StartCycle;    /*!< Specifies the index of the first cycle in which the trigger becomes active.
+                               This parameter is ignored if RepeatFactor is set to FDCAN_TT_REPEAT_EVERY_CYCLE.
+                               This parameter must be a number between 0 and RepeatFactor                       */
+
+  uint32_t TmEventInt;    /*!< Enable or disable the internal time mark event.
+                               If enabled, FDCAN_TT_FLAG_TRIG_TIME_MARK flag is set when trigger memory element
+                               becomes active.
+                               This parameter can be a value of @ref FDCAN_TT_Time_Mark_Event_Internal          */
+
+  uint32_t TmEventExt;    /*!< Enable or disable the external time mark event.
+                               If enabled, and if TTOCN.TTIE is set, a pulse is generated at fdcan1_tmp when
+                               trigger memory element becomes active.
+                               This parameter can be a value of @ref FDCAN_TT_Time_Mark_Event_External          */
+
+  uint32_t TriggerType;   /*!< Specifies the trigger type.
+                               This parameter can be a value of @ref FDCAN_TT_Trigger_Type                      */
+
+  uint32_t FilterType;    /*!< Specifies the filter identifier type.
+                               This parameter can be a value of @ref FDCAN_id_type                              */
+
+  uint32_t TxBufferIndex; /*!< Specifies the index of the Tx buffer for which the trigger is valid.
+                               This parameter can be a value of @ref FDCAN_Tx_location.
+                               This parameter is taken in consideration only if the trigger is configured for
+                               transmission.                                                                    */
+
+  uint32_t FilterIndex;   /*!< Specifies the filter for which the trigger is valid.
+                               This parameter is taken in consideration only if the trigger is configured for
+                               reception.
+                               This parameter must be a number between:
+                                - 0 and 127, if FilterType is FDCAN_STANDARD_ID
+                                - 0 and 63, if FilterType is FDCAN_EXTENDED_ID                                  */
+
+} FDCAN_TriggerTypeDef;
+
+/**
+  * @brief  FDCAN TT Operation Status structure definition
+  */
+typedef struct
+{
+  uint32_t ErrorLevel;       /*!< Specifies the type of the TT operation error level.
+                                  This parameter can be a value of @ref FDCAN_TT_error_level                    */
+
+  uint32_t MasterState;      /*!< Specifies the type of the TT master state.
+                                  This parameter can be a value of @ref FDCAN_TT_master_state                   */
+
+  uint32_t SyncState;        /*!< Specifies the type of the TT synchronization state.
+                                  This parameter can be a value of @ref FDCAN_TT_sync_state                     */
+
+  uint32_t GTimeQuality;     /*!< Specifies the Quality of Global Time Phase.
+                                  This parameter is only relevant in Level 0 and Level 2, otherwise fixed to 0.
+                                  This parameter can be:
+                                   - 0 : Global time not valid
+                                   - 1 : Global time in phase with Time Master                                  */
+
+  uint32_t ClockQuality;     /*!< Specifies the Quality of Clock Speed.
+                                  This parameter is only relevant in Level 0 and Level 2, otherwise fixed to 1.
+                                  This parameter can be:
+                                   - 0 : Local clock speed not synchronized to Time Master clock speed
+                                   - 1 : Synchronization Deviation = SDL                                        */
+
+  uint32_t RefTrigOffset;    /*!< Specifies the Actual Reference Trigger Offset Value.
+                                  This parameter can be a number between 0 and 0xFF                             */
+
+  uint32_t GTimeDiscPending; /*!< Specifies the Global Time Discontinuity State.
+                                  This parameter can be:
+                                   - 0 : No global time preset pending
+                                   - 1 : Node waits for the global time preset to take effect                   */
+
+  uint32_t GapFinished;      /*!< Specifies whether a Gap is finished.
+                                  This parameter can be:
+                                   - 0 : Reset at the end of each reference message
+                                   - 1 : Gap finished                                                           */
+
+  uint32_t MasterPriority;   /*!< Specifies the Priority of actual Time Master.
+                                  This parameter can be a number between 0 and 0x7                              */
+
+  uint32_t GapStarted;       /*!< Specifies whether a Gap is started.
+                                  This parameter can be:
+                                   - 0 : No Gap in schedule
+                                   - 1 : Gap time after Basic Cycle has started                                 */
+
+  uint32_t WaitForEvt;       /*!< Specifies whether a Gap is announced.
+                                  This parameter can be:
+                                   - 0 : No Gap announced, reset by a reference message with Next_is_Gap = 0
+                                   - 1 : Reference message with Next_is_Gap = 1 received                        */
+
+  uint32_t AppWdgEvt;        /*!< Specifies the Application Watchdog State.
+                                  This parameter can be:
+                                   - 0 : Application Watchdog served in time
+                                   - 1 : Failed to serve Application Watchdog in time                           */
+
+  uint32_t ECSPending;       /*!< Specifies the External Clock Synchronization State.
+                                  This parameter can be:
+                                   - 0 : No external clock synchronization pending
+                                   - 1 : Node waits for external clock synchronization to take effect           */
+
+  uint32_t PhaseLock;        /*!< Specifies the Phase Lock State.
+                                  This parameter can be:
+                                   - 0 : Phase outside range
+                                   - 1 : Phase inside range                                                     */
+
+} FDCAN_TTOperationStatusTypeDef;
+
+/**
+  * @brief  FDCAN Message RAM blocks
+  */
+typedef struct
+{
+  uint32_t StandardFilterSA; /*!< Specifies the Standard Filter List Start Address.
+                                  This parameter must be a 32-bit word address      */
+
+  uint32_t ExtendedFilterSA; /*!< Specifies the Extended Filter List Start Address.
+                                  This parameter must be a 32-bit word address      */
+
+  uint32_t RxFIFO0SA;        /*!< Specifies the Rx FIFO 0 Start Address.
+                                  This parameter must be a 32-bit word address      */
+
+  uint32_t RxFIFO1SA;        /*!< Specifies the Rx FIFO 1 Start Address.
+                                  This parameter must be a 32-bit word address      */
+
+  uint32_t RxBufferSA;       /*!< Specifies the Rx Buffer Start Address.
+                                  This parameter must be a 32-bit word address      */
+
+  uint32_t TxEventFIFOSA;    /*!< Specifies the Tx Event FIFO Start Address.
+                                  This parameter must be a 32-bit word address      */
+
+  uint32_t TxBufferSA;       /*!< Specifies the Tx Buffers Start Address.
+                                  This parameter must be a 32-bit word address      */
+
+  uint32_t TxFIFOQSA;        /*!< Specifies the Tx FIFO/Queue Start Address.
+                                  This parameter must be a 32-bit word address      */
+
+  uint32_t TTMemorySA;       /*!< Specifies the Trigger Memory Start Address.
+                                  This parameter must be a 32-bit word address      */
+
+  uint32_t EndAddress;       /*!< Specifies the End Address of the allocated RAM.
+                                  This parameter must be a 32-bit word address      */
+
+} FDCAN_MsgRamAddressTypeDef;
+
+/**
+  * @brief  FDCAN handle structure definition
+  */
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+typedef struct __FDCAN_HandleTypeDef
+#else
+typedef struct
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+{
+  FDCAN_GlobalTypeDef         *Instance;        /*!< Register base address     */
+
+  TTCAN_TypeDef               *ttcan;           /*!< TT register base address  */
+
+  FDCAN_InitTypeDef           Init;             /*!< FDCAN required parameters */
+
+  FDCAN_MsgRamAddressTypeDef  msgRam;           /*!< FDCAN Message RAM blocks  */
+
+  uint32_t                    LatestTxFifoQRequest; /*!< FDCAN Tx buffer index
+                                               of latest Tx FIFO/Queue request */
+
+  __IO HAL_FDCAN_StateTypeDef State;            /*!< FDCAN communication state */
+
+  HAL_LockTypeDef             Lock;             /*!< FDCAN locking object      */
+
+  __IO uint32_t               ErrorCode;        /*!< FDCAN Error code          */
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+  void (* ClockCalibrationCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t ClkCalibrationITs);         /*!< FDCAN Clock Calibration callback          */
+  void (* TxEventFifoCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t TxEventFifoITs);                 /*!< FDCAN Tx Event Fifo callback              */
+  void (* RxFifo0Callback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs);                         /*!< FDCAN Rx Fifo 0 callback                  */
+  void (* RxFifo1Callback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo1ITs);                         /*!< FDCAN Rx Fifo 1 callback                  */
+  void (* TxFifoEmptyCallback)(struct __FDCAN_HandleTypeDef *hfdcan);                                          /*!< FDCAN Tx Fifo Empty callback              */
+  void (* TxBufferCompleteCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes);             /*!< FDCAN Tx Buffer complete callback         */
+  void (* TxBufferAbortCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes);                /*!< FDCAN Tx Buffer abort callback            */
+  void (* RxBufferNewMessageCallback)(struct __FDCAN_HandleTypeDef *hfdcan);                                   /*!< FDCAN Rx Buffer New Message callback      */
+  void (* HighPriorityMessageCallback)(struct __FDCAN_HandleTypeDef *hfdcan);                                  /*!< FDCAN High priority message callback      */
+  void (* TimestampWraparoundCallback)(struct __FDCAN_HandleTypeDef *hfdcan);                                  /*!< FDCAN Timestamp wraparound callback       */
+  void (* TimeoutOccurredCallback)(struct __FDCAN_HandleTypeDef *hfdcan);                                      /*!< FDCAN Timeout occurred callback           */
+  void (* ErrorCallback)(struct __FDCAN_HandleTypeDef *hfdcan);                                                /*!< FDCAN Error callback                      */
+  void (* ErrorStatusCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t ErrorStatusITs);                 /*!< FDCAN Error status callback               */
+  void (* TT_ScheduleSyncCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t TTSchedSyncITs);             /*!< FDCAN T Schedule Synchronization callback */
+  void (* TT_TimeMarkCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t TTTimeMarkITs);                  /*!< FDCAN TT Time Mark callback               */
+  void (* TT_StopWatchCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t SWTime, uint32_t SWCycleCount); /*!< FDCAN TT Stop Watch callback              */
+  void (* TT_GlobalTimeCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t TTGlobTimeITs);                /*!< FDCAN TT Global Time callback             */
+
+  void (* MspInitCallback)(struct __FDCAN_HandleTypeDef *hfdcan);                                              /*!< FDCAN Msp Init callback                   */
+  void (* MspDeInitCallback)(struct __FDCAN_HandleTypeDef *hfdcan);                                            /*!< FDCAN Msp DeInit callback                 */
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+
+} FDCAN_HandleTypeDef;
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+/**
+  * @brief  HAL FDCAN common Callback ID enumeration definition
+  */
+typedef enum
+{
+  HAL_FDCAN_TX_FIFO_EMPTY_CB_ID        = 0x00U, /*!< FDCAN Tx Fifo Empty callback ID         */
+  HAL_FDCAN_RX_BUFFER_NEW_MSG_CB_ID    = 0x01U, /*!< FDCAN Rx buffer new message callback ID */
+  HAL_FDCAN_HIGH_PRIO_MESSAGE_CB_ID    = 0x02U, /*!< FDCAN High priority message callback ID */
+  HAL_FDCAN_TIMESTAMP_WRAPAROUND_CB_ID = 0x03U, /*!< FDCAN Timestamp wraparound callback ID  */
+  HAL_FDCAN_TIMEOUT_OCCURRED_CB_ID     = 0x04U, /*!< FDCAN Timeout occurred callback ID      */
+  HAL_FDCAN_ERROR_CALLBACK_CB_ID       = 0x05U, /*!< FDCAN Error callback ID                 */
+
+  HAL_FDCAN_MSPINIT_CB_ID              = 0x06U, /*!< FDCAN MspInit callback ID               */
+  HAL_FDCAN_MSPDEINIT_CB_ID            = 0x07U, /*!< FDCAN MspDeInit callback ID             */
+
+} HAL_FDCAN_CallbackIDTypeDef;
+
+/**
+  * @brief  HAL FDCAN Callback pointer definition
+  */
+typedef  void (*pFDCAN_CallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan);                                                     /*!< pointer to a common FDCAN callback function                    */
+typedef  void (*pFDCAN_ClockCalibrationCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t ClkCalibrationITs);         /*!< pointer to Clock Calibration FDCAN callback function           */
+typedef  void (*pFDCAN_TxEventFifoCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t TxEventFifoITs);                 /*!< pointer to Tx event Fifo FDCAN callback function               */
+typedef  void (*pFDCAN_RxFifo0CallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs);                         /*!< pointer to Rx Fifo 0 FDCAN callback function                   */
+typedef  void (*pFDCAN_RxFifo1CallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo1ITs);                         /*!< pointer to Rx Fifo 1 FDCAN callback function                   */
+typedef  void (*pFDCAN_TxBufferCompleteCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes);             /*!< pointer to Tx Buffer complete FDCAN callback function          */
+typedef  void (*pFDCAN_TxBufferAbortCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes);                /*!< pointer to Tx Buffer abort FDCAN callback function             */
+typedef  void (*pFDCAN_ErrorStatusCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t ErrorStatusITs);                 /*!< pointer to Error Status callback function                      */
+typedef  void (*pFDCAN_TT_ScheduleSyncCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t TTSchedSyncITs);             /*!< pointer to TT Schedule Synchronization FDCAN callback function */
+typedef  void (*pFDCAN_TT_TimeMarkCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t TTTimeMarkITs);                  /*!< pointer to TT Time Mark FDCAN callback function                */
+typedef  void (*pFDCAN_TT_StopWatchCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t SWTime, uint32_t SWCycleCount); /*!< pointer to TT Stop Watch FDCAN callback function               */
+typedef  void (*pFDCAN_TT_GlobalTimeCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t TTGlobTimeITs);                /*!< pointer to TT Global Time FDCAN callback function              */
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup FDCAN_Exported_Constants FDCAN Exported Constants
+  * @{
+  */
+
+/** @defgroup HAL_FDCAN_Error_Code HAL FDCAN Error Code
+  * @{
+  */
+#define HAL_FDCAN_ERROR_NONE            ((uint32_t)0x00000000U) /*!< No error                                                               */
+#define HAL_FDCAN_ERROR_TIMEOUT         ((uint32_t)0x00000001U) /*!< Timeout error                                                          */
+#define HAL_FDCAN_ERROR_NOT_INITIALIZED ((uint32_t)0x00000002U) /*!< Peripheral not initialized                                             */
+#define HAL_FDCAN_ERROR_NOT_READY       ((uint32_t)0x00000004U) /*!< Peripheral not ready                                                   */
+#define HAL_FDCAN_ERROR_NOT_STARTED     ((uint32_t)0x00000008U) /*!< Peripheral not started                                                 */
+#define HAL_FDCAN_ERROR_NOT_SUPPORTED   ((uint32_t)0x00000010U) /*!< Mode not supported                                                     */
+#define HAL_FDCAN_ERROR_PARAM           ((uint32_t)0x00000020U) /*!< Parameter error                                                        */
+#define HAL_FDCAN_ERROR_PENDING         ((uint32_t)0x00000040U) /*!< Pending operation                                                      */
+#define HAL_FDCAN_ERROR_RAM_ACCESS      ((uint32_t)0x00000080U) /*!< Message RAM Access Failure                                             */
+#define HAL_FDCAN_ERROR_FIFO_EMPTY      ((uint32_t)0x00000100U) /*!< Put element in full FIFO                                               */
+#define HAL_FDCAN_ERROR_FIFO_FULL       ((uint32_t)0x00000200U) /*!< Get element from empty FIFO                                            */
+#define HAL_FDCAN_ERROR_LOG_OVERFLOW    FDCAN_IR_ELO            /*!< Overflow of CAN Error Logging Counter                                  */
+#define HAL_FDCAN_ERROR_RAM_WDG         FDCAN_IR_WDI            /*!< Message RAM Watchdog event occurred                                    */
+#define HAL_FDCAN_ERROR_PROTOCOL_ARBT   FDCAN_IR_PEA            /*!< Protocol Error in Arbitration Phase (Nominal Bit Time is used)         */
+#define HAL_FDCAN_ERROR_PROTOCOL_DATA   FDCAN_IR_PED            /*!< Protocol Error in Data Phase (Data Bit Time is used)                   */
+#define HAL_FDCAN_ERROR_RESERVED_AREA   FDCAN_IR_ARA            /*!< Access to Reserved Address                                             */
+#define HAL_FDCAN_ERROR_TT_GLOBAL_TIME  FDCAN_TTIR_GTE          /*!< Global Time Error : Synchronization deviation exceeded limit           */
+#define HAL_FDCAN_ERROR_TT_TX_UNDERFLOW FDCAN_TTIR_TXU          /*!< Tx Count Underflow : Less Tx trigger than expected in one matrix cycle */
+#define HAL_FDCAN_ERROR_TT_TX_OVERFLOW  FDCAN_TTIR_TXO          /*!< Tx Count Overflow : More Tx trigger than expected in one matrix cycle  */
+#define HAL_FDCAN_ERROR_TT_SCHEDULE1    FDCAN_TTIR_SE1          /*!< Scheduling error 1                                                     */
+#define HAL_FDCAN_ERROR_TT_SCHEDULE2    FDCAN_TTIR_SE2          /*!< Scheduling error 2                                                     */
+#define HAL_FDCAN_ERROR_TT_NO_INIT_REF  FDCAN_TTIR_IWT          /*!< No system startup due to missing reference message                     */
+#define HAL_FDCAN_ERROR_TT_NO_REF       FDCAN_TTIR_WT           /*!< Missing reference message                                              */
+#define HAL_FDCAN_ERROR_TT_APPL_WDG     FDCAN_TTIR_AW           /*!< Application watchdog not served in time                                */
+#define HAL_FDCAN_ERROR_TT_CONFIG       FDCAN_TTIR_CER          /*!< Error found in trigger list                                            */
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+#define HAL_FDCAN_ERROR_INVALID_CALLBACK ((uint32_t)0x00000100U) /*!< Invalid Callback error                                                */
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_frame_format FDCAN Frame Format
+  * @{
+  */
+#define FDCAN_FRAME_CLASSIC   ((uint32_t)0x00000000U)                         /*!< Classic mode                      */
+#define FDCAN_FRAME_FD_NO_BRS ((uint32_t)FDCAN_CCCR_FDOE)                     /*!< FD mode without BitRate Switching */
+#define FDCAN_FRAME_FD_BRS    ((uint32_t)(FDCAN_CCCR_FDOE | FDCAN_CCCR_BRSE)) /*!< FD mode with BitRate Switching    */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_operating_mode FDCAN Operating Mode
+  * @{
+  */
+#define FDCAN_MODE_NORMAL               ((uint32_t)0x00000000U) /*!< Normal mode               */
+#define FDCAN_MODE_RESTRICTED_OPERATION ((uint32_t)0x00000001U) /*!< Restricted Operation mode */
+#define FDCAN_MODE_BUS_MONITORING       ((uint32_t)0x00000002U) /*!< Bus Monitoring mode       */
+#define FDCAN_MODE_INTERNAL_LOOPBACK    ((uint32_t)0x00000003U) /*!< Internal LoopBack mode    */
+#define FDCAN_MODE_EXTERNAL_LOOPBACK    ((uint32_t)0x00000004U) /*!< External LoopBack mode    */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_clock_calibration FDCAN Clock Calibration
+  * @{
+  */
+#define FDCAN_CLOCK_CALIBRATION_DISABLE ((uint32_t)0x00000000U) /*!< Disable Clock Calibration */
+#define FDCAN_CLOCK_CALIBRATION_ENABLE  ((uint32_t)0x00000001U) /*!< Enable Clock Calibration  */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_clock_divider FDCAN Clock Divider
+  * @{
+  */
+#define FDCAN_CLOCK_DIV1  ((uint32_t)0x00000000U) /*!< Divide kernel clock by 1  */
+#define FDCAN_CLOCK_DIV2  ((uint32_t)0x00010000U) /*!< Divide kernel clock by 2  */
+#define FDCAN_CLOCK_DIV4  ((uint32_t)0x00020000U) /*!< Divide kernel clock by 4  */
+#define FDCAN_CLOCK_DIV6  ((uint32_t)0x00030000U) /*!< Divide kernel clock by 6  */
+#define FDCAN_CLOCK_DIV8  ((uint32_t)0x00040000U) /*!< Divide kernel clock by 8  */
+#define FDCAN_CLOCK_DIV10 ((uint32_t)0x00050000U) /*!< Divide kernel clock by 10 */
+#define FDCAN_CLOCK_DIV12 ((uint32_t)0x00060000U) /*!< Divide kernel clock by 12 */
+#define FDCAN_CLOCK_DIV14 ((uint32_t)0x00070000U) /*!< Divide kernel clock by 14 */
+#define FDCAN_CLOCK_DIV16 ((uint32_t)0x00080000U) /*!< Divide kernel clock by 16 */
+#define FDCAN_CLOCK_DIV18 ((uint32_t)0x00090000U) /*!< Divide kernel clock by 18 */
+#define FDCAN_CLOCK_DIV20 ((uint32_t)0x000A0000U) /*!< Divide kernel clock by 20 */
+#define FDCAN_CLOCK_DIV22 ((uint32_t)0x000B0000U) /*!< Divide kernel clock by 22 */
+#define FDCAN_CLOCK_DIV24 ((uint32_t)0x000C0000U) /*!< Divide kernel clock by 24 */
+#define FDCAN_CLOCK_DIV26 ((uint32_t)0x000D0000U) /*!< Divide kernel clock by 26 */
+#define FDCAN_CLOCK_DIV28 ((uint32_t)0x000E0000U) /*!< Divide kernel clock by 28 */
+#define FDCAN_CLOCK_DIV30 ((uint32_t)0x000F0000U) /*!< Divide kernel clock by 30 */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_calibration_field_length FDCAN Calibration Field Length
+  * @{
+  */
+#define FDCAN_CALIB_FIELD_LENGTH_32 ((uint32_t)0x00000000U)       /*!< Calibration field length is 32 bits */
+#define FDCAN_CALIB_FIELD_LENGTH_64 ((uint32_t)FDCANCCU_CCFG_CFL) /*!< Calibration field length is 64 bits */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_calibration_state FDCAN Calibration State
+  * @{
+  */
+#define FDCAN_CLOCK_NOT_CALIBRATED       ((uint32_t)0x00000000U) /*!< Clock not calibrated       */
+#define FDCAN_CLOCK_BASIC_CALIBRATED     ((uint32_t)0x40000000U) /*!< Clock basic calibrated     */
+#define FDCAN_CLOCK_PRECISION_CALIBRATED ((uint32_t)0x80000000U) /*!< Clock precision calibrated */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_calibration_counter FDCAN Calibration Counter
+  * @{
+  */
+#define FDCAN_CALIB_TIME_QUANTA_COUNTER  ((uint32_t)0x00000000U) /*!< Time Quanta Counter             */
+#define FDCAN_CALIB_CLOCK_PERIOD_COUNTER ((uint32_t)0x00000001U) /*!< Oscillator Clock Period Counter */
+#define FDCAN_CALIB_WATCHDOG_COUNTER     ((uint32_t)0x00000002U) /*!< Calibration Watchdog Counter    */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_data_field_size FDCAN Data Field Size
+  * @{
+  */
+#define FDCAN_DATA_BYTES_8  ((uint32_t)0x00000004U) /*!< 8 bytes data field  */
+#define FDCAN_DATA_BYTES_12 ((uint32_t)0x00000005U) /*!< 12 bytes data field */
+#define FDCAN_DATA_BYTES_16 ((uint32_t)0x00000006U) /*!< 16 bytes data field */
+#define FDCAN_DATA_BYTES_20 ((uint32_t)0x00000007U) /*!< 20 bytes data field */
+#define FDCAN_DATA_BYTES_24 ((uint32_t)0x00000008U) /*!< 24 bytes data field */
+#define FDCAN_DATA_BYTES_32 ((uint32_t)0x0000000AU) /*!< 32 bytes data field */
+#define FDCAN_DATA_BYTES_48 ((uint32_t)0x0000000EU) /*!< 48 bytes data field */
+#define FDCAN_DATA_BYTES_64 ((uint32_t)0x00000012U) /*!< 64 bytes data field */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_txFifoQueue_Mode FDCAN Tx FIFO/Queue Mode
+  * @{
+  */
+#define FDCAN_TX_FIFO_OPERATION  ((uint32_t)0x00000000U)     /*!< FIFO mode  */
+#define FDCAN_TX_QUEUE_OPERATION ((uint32_t)FDCAN_TXBC_TFQM) /*!< Queue mode */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_id_type FDCAN ID Type
+  * @{
+  */
+#define FDCAN_STANDARD_ID ((uint32_t)0x00000000U) /*!< Standard ID element */
+#define FDCAN_EXTENDED_ID ((uint32_t)0x40000000U) /*!< Extended ID element */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_frame_type FDCAN Frame Type
+  * @{
+  */
+#define FDCAN_DATA_FRAME   ((uint32_t)0x00000000U)  /*!< Data frame   */
+#define FDCAN_REMOTE_FRAME ((uint32_t)0x20000000U)  /*!< Remote frame */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_data_length_code FDCAN Data Length Code
+  * @{
+  */
+#define FDCAN_DLC_BYTES_0  ((uint32_t)0x00000000U) /*!< 0 bytes data field  */
+#define FDCAN_DLC_BYTES_1  ((uint32_t)0x00010000U) /*!< 1 bytes data field  */
+#define FDCAN_DLC_BYTES_2  ((uint32_t)0x00020000U) /*!< 2 bytes data field  */
+#define FDCAN_DLC_BYTES_3  ((uint32_t)0x00030000U) /*!< 3 bytes data field  */
+#define FDCAN_DLC_BYTES_4  ((uint32_t)0x00040000U) /*!< 4 bytes data field  */
+#define FDCAN_DLC_BYTES_5  ((uint32_t)0x00050000U) /*!< 5 bytes data field  */
+#define FDCAN_DLC_BYTES_6  ((uint32_t)0x00060000U) /*!< 6 bytes data field  */
+#define FDCAN_DLC_BYTES_7  ((uint32_t)0x00070000U) /*!< 7 bytes data field  */
+#define FDCAN_DLC_BYTES_8  ((uint32_t)0x00080000U) /*!< 8 bytes data field  */
+#define FDCAN_DLC_BYTES_12 ((uint32_t)0x00090000U) /*!< 12 bytes data field */
+#define FDCAN_DLC_BYTES_16 ((uint32_t)0x000A0000U) /*!< 16 bytes data field */
+#define FDCAN_DLC_BYTES_20 ((uint32_t)0x000B0000U) /*!< 20 bytes data field */
+#define FDCAN_DLC_BYTES_24 ((uint32_t)0x000C0000U) /*!< 24 bytes data field */
+#define FDCAN_DLC_BYTES_32 ((uint32_t)0x000D0000U) /*!< 32 bytes data field */
+#define FDCAN_DLC_BYTES_48 ((uint32_t)0x000E0000U) /*!< 48 bytes data field */
+#define FDCAN_DLC_BYTES_64 ((uint32_t)0x000F0000U) /*!< 64 bytes data field */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_error_state_indicator FDCAN Error State Indicator
+  * @{
+  */
+#define FDCAN_ESI_ACTIVE  ((uint32_t)0x00000000U) /*!< Transmitting node is error active  */
+#define FDCAN_ESI_PASSIVE ((uint32_t)0x80000000U) /*!< Transmitting node is error passive */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_bit_rate_switching FDCAN Bit Rate Switching
+  * @{
+  */
+#define FDCAN_BRS_OFF ((uint32_t)0x00000000U) /*!< FDCAN frames transmitted/received without bit rate switching */
+#define FDCAN_BRS_ON  ((uint32_t)0x00100000U) /*!< FDCAN frames transmitted/received with bit rate switching    */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_format FDCAN format
+  * @{
+  */
+#define FDCAN_CLASSIC_CAN ((uint32_t)0x00000000U) /*!< Frame transmitted/received in Classic CAN format */
+#define FDCAN_FD_CAN      ((uint32_t)0x00200000U) /*!< Frame transmitted/received in FDCAN format       */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_EFC FDCAN Event FIFO control
+  * @{
+  */
+#define FDCAN_NO_TX_EVENTS    ((uint32_t)0x00000000U) /*!< Do not store Tx events */
+#define FDCAN_STORE_TX_EVENTS ((uint32_t)0x00800000U) /*!< Store Tx events        */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_filter_type FDCAN Filter Type
+  * @{
+  */
+#define FDCAN_FILTER_RANGE         ((uint32_t)0x00000000U) /*!< Range filter from FilterID1 to FilterID2                        */
+#define FDCAN_FILTER_DUAL          ((uint32_t)0x00000001U) /*!< Dual ID filter for FilterID1 or FilterID2                       */
+#define FDCAN_FILTER_MASK          ((uint32_t)0x00000002U) /*!< Classic filter: FilterID1 = filter, FilterID2 = mask            */
+#define FDCAN_FILTER_RANGE_NO_EIDM ((uint32_t)0x00000003U) /*!< Range filter from FilterID1 to FilterID2, EIDM mask not applied */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_filter_config FDCAN Filter Configuration
+  * @{
+  */
+#define FDCAN_FILTER_DISABLE       ((uint32_t)0x00000000U) /*!< Disable filter element                                    */
+#define FDCAN_FILTER_TO_RXFIFO0    ((uint32_t)0x00000001U) /*!< Store in Rx FIFO 0 if filter matches                      */
+#define FDCAN_FILTER_TO_RXFIFO1    ((uint32_t)0x00000002U) /*!< Store in Rx FIFO 1 if filter matches                      */
+#define FDCAN_FILTER_REJECT        ((uint32_t)0x00000003U) /*!< Reject ID if filter matches                               */
+#define FDCAN_FILTER_HP            ((uint32_t)0x00000004U) /*!< Set high priority if filter matches                       */
+#define FDCAN_FILTER_TO_RXFIFO0_HP ((uint32_t)0x00000005U) /*!< Set high priority and store in FIFO 0 if filter matches   */
+#define FDCAN_FILTER_TO_RXFIFO1_HP ((uint32_t)0x00000006U) /*!< Set high priority and store in FIFO 1 if filter matches   */
+#define FDCAN_FILTER_TO_RXBUFFER   ((uint32_t)0x00000007U) /*!< Store into Rx Buffer, configuration of FilterType ignored */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Tx_location FDCAN Tx Location
+  * @{
+  */
+#define FDCAN_TX_BUFFER0  ((uint32_t)0x00000001U) /*!< Add message to Tx Buffer 0  */
+#define FDCAN_TX_BUFFER1  ((uint32_t)0x00000002U) /*!< Add message to Tx Buffer 1  */
+#define FDCAN_TX_BUFFER2  ((uint32_t)0x00000004U) /*!< Add message to Tx Buffer 2  */
+#define FDCAN_TX_BUFFER3  ((uint32_t)0x00000008U) /*!< Add message to Tx Buffer 3  */
+#define FDCAN_TX_BUFFER4  ((uint32_t)0x00000010U) /*!< Add message to Tx Buffer 4  */
+#define FDCAN_TX_BUFFER5  ((uint32_t)0x00000020U) /*!< Add message to Tx Buffer 5  */
+#define FDCAN_TX_BUFFER6  ((uint32_t)0x00000040U) /*!< Add message to Tx Buffer 6  */
+#define FDCAN_TX_BUFFER7  ((uint32_t)0x00000080U) /*!< Add message to Tx Buffer 7  */
+#define FDCAN_TX_BUFFER8  ((uint32_t)0x00000100U) /*!< Add message to Tx Buffer 8  */
+#define FDCAN_TX_BUFFER9  ((uint32_t)0x00000200U) /*!< Add message to Tx Buffer 9  */
+#define FDCAN_TX_BUFFER10 ((uint32_t)0x00000400U) /*!< Add message to Tx Buffer 10 */
+#define FDCAN_TX_BUFFER11 ((uint32_t)0x00000800U) /*!< Add message to Tx Buffer 11 */
+#define FDCAN_TX_BUFFER12 ((uint32_t)0x00001000U) /*!< Add message to Tx Buffer 12 */
+#define FDCAN_TX_BUFFER13 ((uint32_t)0x00002000U) /*!< Add message to Tx Buffer 13 */
+#define FDCAN_TX_BUFFER14 ((uint32_t)0x00004000U) /*!< Add message to Tx Buffer 14 */
+#define FDCAN_TX_BUFFER15 ((uint32_t)0x00008000U) /*!< Add message to Tx Buffer 15 */
+#define FDCAN_TX_BUFFER16 ((uint32_t)0x00010000U) /*!< Add message to Tx Buffer 16 */
+#define FDCAN_TX_BUFFER17 ((uint32_t)0x00020000U) /*!< Add message to Tx Buffer 17 */
+#define FDCAN_TX_BUFFER18 ((uint32_t)0x00040000U) /*!< Add message to Tx Buffer 18 */
+#define FDCAN_TX_BUFFER19 ((uint32_t)0x00080000U) /*!< Add message to Tx Buffer 19 */
+#define FDCAN_TX_BUFFER20 ((uint32_t)0x00100000U) /*!< Add message to Tx Buffer 20 */
+#define FDCAN_TX_BUFFER21 ((uint32_t)0x00200000U) /*!< Add message to Tx Buffer 21 */
+#define FDCAN_TX_BUFFER22 ((uint32_t)0x00400000U) /*!< Add message to Tx Buffer 22 */
+#define FDCAN_TX_BUFFER23 ((uint32_t)0x00800000U) /*!< Add message to Tx Buffer 23 */
+#define FDCAN_TX_BUFFER24 ((uint32_t)0x01000000U) /*!< Add message to Tx Buffer 24 */
+#define FDCAN_TX_BUFFER25 ((uint32_t)0x02000000U) /*!< Add message to Tx Buffer 25 */
+#define FDCAN_TX_BUFFER26 ((uint32_t)0x04000000U) /*!< Add message to Tx Buffer 26 */
+#define FDCAN_TX_BUFFER27 ((uint32_t)0x08000000U) /*!< Add message to Tx Buffer 27 */
+#define FDCAN_TX_BUFFER28 ((uint32_t)0x10000000U) /*!< Add message to Tx Buffer 28 */
+#define FDCAN_TX_BUFFER29 ((uint32_t)0x20000000U) /*!< Add message to Tx Buffer 29 */
+#define FDCAN_TX_BUFFER30 ((uint32_t)0x40000000U) /*!< Add message to Tx Buffer 30 */
+#define FDCAN_TX_BUFFER31 ((uint32_t)0x80000000U) /*!< Add message to Tx Buffer 31 */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Rx_location FDCAN Rx Location
+  * @{
+  */
+#define FDCAN_RX_FIFO0    ((uint32_t)0x00000040U) /*!< Get received message from Rx FIFO 0    */
+#define FDCAN_RX_FIFO1    ((uint32_t)0x00000041U) /*!< Get received message from Rx FIFO 1    */
+#define FDCAN_RX_BUFFER0  ((uint32_t)0x00000000U) /*!< Get received message from Rx Buffer 0  */
+#define FDCAN_RX_BUFFER1  ((uint32_t)0x00000001U) /*!< Get received message from Rx Buffer 1  */
+#define FDCAN_RX_BUFFER2  ((uint32_t)0x00000002U) /*!< Get received message from Rx Buffer 2  */
+#define FDCAN_RX_BUFFER3  ((uint32_t)0x00000003U) /*!< Get received message from Rx Buffer 3  */
+#define FDCAN_RX_BUFFER4  ((uint32_t)0x00000004U) /*!< Get received message from Rx Buffer 4  */
+#define FDCAN_RX_BUFFER5  ((uint32_t)0x00000005U) /*!< Get received message from Rx Buffer 5  */
+#define FDCAN_RX_BUFFER6  ((uint32_t)0x00000006U) /*!< Get received message from Rx Buffer 6  */
+#define FDCAN_RX_BUFFER7  ((uint32_t)0x00000007U) /*!< Get received message from Rx Buffer 7  */
+#define FDCAN_RX_BUFFER8  ((uint32_t)0x00000008U) /*!< Get received message from Rx Buffer 8  */
+#define FDCAN_RX_BUFFER9  ((uint32_t)0x00000009U) /*!< Get received message from Rx Buffer 9  */
+#define FDCAN_RX_BUFFER10 ((uint32_t)0x0000000AU) /*!< Get received message from Rx Buffer 10 */
+#define FDCAN_RX_BUFFER11 ((uint32_t)0x0000000BU) /*!< Get received message from Rx Buffer 11 */
+#define FDCAN_RX_BUFFER12 ((uint32_t)0x0000000CU) /*!< Get received message from Rx Buffer 12 */
+#define FDCAN_RX_BUFFER13 ((uint32_t)0x0000000DU) /*!< Get received message from Rx Buffer 13 */
+#define FDCAN_RX_BUFFER14 ((uint32_t)0x0000000EU) /*!< Get received message from Rx Buffer 14 */
+#define FDCAN_RX_BUFFER15 ((uint32_t)0x0000000FU) /*!< Get received message from Rx Buffer 15 */
+#define FDCAN_RX_BUFFER16 ((uint32_t)0x00000010U) /*!< Get received message from Rx Buffer 16 */
+#define FDCAN_RX_BUFFER17 ((uint32_t)0x00000011U) /*!< Get received message from Rx Buffer 17 */
+#define FDCAN_RX_BUFFER18 ((uint32_t)0x00000012U) /*!< Get received message from Rx Buffer 18 */
+#define FDCAN_RX_BUFFER19 ((uint32_t)0x00000013U) /*!< Get received message from Rx Buffer 19 */
+#define FDCAN_RX_BUFFER20 ((uint32_t)0x00000014U) /*!< Get received message from Rx Buffer 20 */
+#define FDCAN_RX_BUFFER21 ((uint32_t)0x00000015U) /*!< Get received message from Rx Buffer 21 */
+#define FDCAN_RX_BUFFER22 ((uint32_t)0x00000016U) /*!< Get received message from Rx Buffer 22 */
+#define FDCAN_RX_BUFFER23 ((uint32_t)0x00000017U) /*!< Get received message from Rx Buffer 23 */
+#define FDCAN_RX_BUFFER24 ((uint32_t)0x00000018U) /*!< Get received message from Rx Buffer 24 */
+#define FDCAN_RX_BUFFER25 ((uint32_t)0x00000019U) /*!< Get received message from Rx Buffer 25 */
+#define FDCAN_RX_BUFFER26 ((uint32_t)0x0000001AU) /*!< Get received message from Rx Buffer 26 */
+#define FDCAN_RX_BUFFER27 ((uint32_t)0x0000001BU) /*!< Get received message from Rx Buffer 27 */
+#define FDCAN_RX_BUFFER28 ((uint32_t)0x0000001CU) /*!< Get received message from Rx Buffer 28 */
+#define FDCAN_RX_BUFFER29 ((uint32_t)0x0000001DU) /*!< Get received message from Rx Buffer 29 */
+#define FDCAN_RX_BUFFER30 ((uint32_t)0x0000001EU) /*!< Get received message from Rx Buffer 30 */
+#define FDCAN_RX_BUFFER31 ((uint32_t)0x0000001FU) /*!< Get received message from Rx Buffer 31 */
+#define FDCAN_RX_BUFFER32 ((uint32_t)0x00000020U) /*!< Get received message from Rx Buffer 32 */
+#define FDCAN_RX_BUFFER33 ((uint32_t)0x00000021U) /*!< Get received message from Rx Buffer 33 */
+#define FDCAN_RX_BUFFER34 ((uint32_t)0x00000022U) /*!< Get received message from Rx Buffer 34 */
+#define FDCAN_RX_BUFFER35 ((uint32_t)0x00000023U) /*!< Get received message from Rx Buffer 35 */
+#define FDCAN_RX_BUFFER36 ((uint32_t)0x00000024U) /*!< Get received message from Rx Buffer 36 */
+#define FDCAN_RX_BUFFER37 ((uint32_t)0x00000025U) /*!< Get received message from Rx Buffer 37 */
+#define FDCAN_RX_BUFFER38 ((uint32_t)0x00000026U) /*!< Get received message from Rx Buffer 38 */
+#define FDCAN_RX_BUFFER39 ((uint32_t)0x00000027U) /*!< Get received message from Rx Buffer 39 */
+#define FDCAN_RX_BUFFER40 ((uint32_t)0x00000028U) /*!< Get received message from Rx Buffer 40 */
+#define FDCAN_RX_BUFFER41 ((uint32_t)0x00000029U) /*!< Get received message from Rx Buffer 41 */
+#define FDCAN_RX_BUFFER42 ((uint32_t)0x0000002AU) /*!< Get received message from Rx Buffer 42 */
+#define FDCAN_RX_BUFFER43 ((uint32_t)0x0000002BU) /*!< Get received message from Rx Buffer 43 */
+#define FDCAN_RX_BUFFER44 ((uint32_t)0x0000002CU) /*!< Get received message from Rx Buffer 44 */
+#define FDCAN_RX_BUFFER45 ((uint32_t)0x0000002DU) /*!< Get received message from Rx Buffer 45 */
+#define FDCAN_RX_BUFFER46 ((uint32_t)0x0000002EU) /*!< Get received message from Rx Buffer 46 */
+#define FDCAN_RX_BUFFER47 ((uint32_t)0x0000002FU) /*!< Get received message from Rx Buffer 47 */
+#define FDCAN_RX_BUFFER48 ((uint32_t)0x00000030U) /*!< Get received message from Rx Buffer 48 */
+#define FDCAN_RX_BUFFER49 ((uint32_t)0x00000031U) /*!< Get received message from Rx Buffer 49 */
+#define FDCAN_RX_BUFFER50 ((uint32_t)0x00000032U) /*!< Get received message from Rx Buffer 50 */
+#define FDCAN_RX_BUFFER51 ((uint32_t)0x00000033U) /*!< Get received message from Rx Buffer 51 */
+#define FDCAN_RX_BUFFER52 ((uint32_t)0x00000034U) /*!< Get received message from Rx Buffer 52 */
+#define FDCAN_RX_BUFFER53 ((uint32_t)0x00000035U) /*!< Get received message from Rx Buffer 53 */
+#define FDCAN_RX_BUFFER54 ((uint32_t)0x00000036U) /*!< Get received message from Rx Buffer 54 */
+#define FDCAN_RX_BUFFER55 ((uint32_t)0x00000037U) /*!< Get received message from Rx Buffer 55 */
+#define FDCAN_RX_BUFFER56 ((uint32_t)0x00000038U) /*!< Get received message from Rx Buffer 56 */
+#define FDCAN_RX_BUFFER57 ((uint32_t)0x00000039U) /*!< Get received message from Rx Buffer 57 */
+#define FDCAN_RX_BUFFER58 ((uint32_t)0x0000003AU) /*!< Get received message from Rx Buffer 58 */
+#define FDCAN_RX_BUFFER59 ((uint32_t)0x0000003BU) /*!< Get received message from Rx Buffer 59 */
+#define FDCAN_RX_BUFFER60 ((uint32_t)0x0000003CU) /*!< Get received message from Rx Buffer 60 */
+#define FDCAN_RX_BUFFER61 ((uint32_t)0x0000003DU) /*!< Get received message from Rx Buffer 61 */
+#define FDCAN_RX_BUFFER62 ((uint32_t)0x0000003EU) /*!< Get received message from Rx Buffer 62 */
+#define FDCAN_RX_BUFFER63 ((uint32_t)0x0000003FU) /*!< Get received message from Rx Buffer 63 */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_event_type FDCAN Event Type
+  * @{
+  */
+#define FDCAN_TX_EVENT             ((uint32_t)0x00400000U) /*!< Tx event                              */
+#define FDCAN_TX_IN_SPITE_OF_ABORT ((uint32_t)0x00800000U) /*!< Transmission in spite of cancellation */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_hp_msg_storage FDCAN High Priority Message Storage
+  * @{
+  */
+#define FDCAN_HP_STORAGE_NO_FIFO  ((uint32_t)0x00000000U) /*!< No FIFO selected         */
+#define FDCAN_HP_STORAGE_MSG_LOST ((uint32_t)0x00000040U) /*!< FIFO message lost        */
+#define FDCAN_HP_STORAGE_RXFIFO0  ((uint32_t)0x00000080U) /*!< Message stored in FIFO 0 */
+#define FDCAN_HP_STORAGE_RXFIFO1  ((uint32_t)0x000000C0U) /*!< Message stored in FIFO 1 */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_protocol_error_code FDCAN protocol error code
+  * @{
+  */
+#define FDCAN_PROTOCOL_ERROR_NONE      ((uint32_t)0x00000000U) /*!< No error occurred         */
+#define FDCAN_PROTOCOL_ERROR_STUFF     ((uint32_t)0x00000001U) /*!< Stuff error               */
+#define FDCAN_PROTOCOL_ERROR_FORM      ((uint32_t)0x00000002U) /*!< Form error                */
+#define FDCAN_PROTOCOL_ERROR_ACK       ((uint32_t)0x00000003U) /*!< Acknowledge error         */
+#define FDCAN_PROTOCOL_ERROR_BIT1      ((uint32_t)0x00000004U) /*!< Bit 1 (recessive) error   */
+#define FDCAN_PROTOCOL_ERROR_BIT0      ((uint32_t)0x00000005U) /*!< Bit 0 (dominant) error    */
+#define FDCAN_PROTOCOL_ERROR_CRC       ((uint32_t)0x00000006U) /*!< CRC check sum error       */
+#define FDCAN_PROTOCOL_ERROR_NO_CHANGE ((uint32_t)0x00000007U) /*!< No change since last read */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_communication_state FDCAN communication state
+  * @{
+  */
+#define FDCAN_COM_STATE_SYNC ((uint32_t)0x00000000U) /*!< Node is synchronizing on CAN communication */
+#define FDCAN_COM_STATE_IDLE ((uint32_t)0x00000008U) /*!< Node is neither receiver nor transmitter   */
+#define FDCAN_COM_STATE_RX   ((uint32_t)0x00000010U) /*!< Node is operating as receiver              */
+#define FDCAN_COM_STATE_TX   ((uint32_t)0x00000018U) /*!< Node is operating as transmitter           */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_FIFO_watermark FDCAN FIFO watermark
+  * @{
+  */
+#define FDCAN_CFG_TX_EVENT_FIFO ((uint32_t)0x00000000U) /*!< Tx event FIFO */
+#define FDCAN_CFG_RX_FIFO0      ((uint32_t)0x00000001U) /*!< Rx FIFO0      */
+#define FDCAN_CFG_RX_FIFO1      ((uint32_t)0x00000002U) /*!< Rx FIFO1      */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Rx_FIFO_operation_mode FDCAN FIFO operation mode
+  * @{
+  */
+#define FDCAN_RX_FIFO_BLOCKING  ((uint32_t)0x00000000U) /*!< Rx FIFO blocking mode  */
+#define FDCAN_RX_FIFO_OVERWRITE ((uint32_t)0x80000000U) /*!< Rx FIFO overwrite mode */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Non_Matching_Frames FDCAN non-matching frames
+  * @{
+  */
+#define FDCAN_ACCEPT_IN_RX_FIFO0 ((uint32_t)0x00000000U) /*!< Accept in Rx FIFO 0 */
+#define FDCAN_ACCEPT_IN_RX_FIFO1 ((uint32_t)0x00000001U) /*!< Accept in Rx FIFO 1 */
+#define FDCAN_REJECT             ((uint32_t)0x00000002U) /*!< Reject              */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Reject_Remote_Frames FDCAN reject remote frames
+  * @{
+  */
+#define FDCAN_FILTER_REMOTE ((uint32_t)0x00000000U) /*!< Filter remote frames */
+#define FDCAN_REJECT_REMOTE ((uint32_t)0x00000001U) /*!< Reject all remote frames */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Interrupt_Line FDCAN interrupt line
+  * @{
+  */
+#define FDCAN_INTERRUPT_LINE0 ((uint32_t)0x00000001U) /*!< Interrupt Line 0 */
+#define FDCAN_INTERRUPT_LINE1 ((uint32_t)0x00000002U) /*!< Interrupt Line 1 */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Timestamp FDCAN timestamp
+  * @{
+  */
+#define FDCAN_TIMESTAMP_INTERNAL ((uint32_t)0x00000001U) /*!< Timestamp counter value incremented according to TCP */
+#define FDCAN_TIMESTAMP_EXTERNAL ((uint32_t)0x00000002U) /*!< External timestamp counter value used                */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Timestamp_Prescaler FDCAN timestamp prescaler
+  * @{
+  */
+#define FDCAN_TIMESTAMP_PRESC_1  ((uint32_t)0x00000000U) /*!< Timestamp counter time unit in equal to CAN bit time                 */
+#define FDCAN_TIMESTAMP_PRESC_2  ((uint32_t)0x00010000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 2  */
+#define FDCAN_TIMESTAMP_PRESC_3  ((uint32_t)0x00020000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 3  */
+#define FDCAN_TIMESTAMP_PRESC_4  ((uint32_t)0x00030000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 4  */
+#define FDCAN_TIMESTAMP_PRESC_5  ((uint32_t)0x00040000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 5  */
+#define FDCAN_TIMESTAMP_PRESC_6  ((uint32_t)0x00050000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 6  */
+#define FDCAN_TIMESTAMP_PRESC_7  ((uint32_t)0x00060000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 7  */
+#define FDCAN_TIMESTAMP_PRESC_8  ((uint32_t)0x00070000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 8  */
+#define FDCAN_TIMESTAMP_PRESC_9  ((uint32_t)0x00080000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 9  */
+#define FDCAN_TIMESTAMP_PRESC_10 ((uint32_t)0x00090000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 10 */
+#define FDCAN_TIMESTAMP_PRESC_11 ((uint32_t)0x000A0000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 11 */
+#define FDCAN_TIMESTAMP_PRESC_12 ((uint32_t)0x000B0000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 12 */
+#define FDCAN_TIMESTAMP_PRESC_13 ((uint32_t)0x000C0000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 13 */
+#define FDCAN_TIMESTAMP_PRESC_14 ((uint32_t)0x000D0000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 14 */
+#define FDCAN_TIMESTAMP_PRESC_15 ((uint32_t)0x000E0000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 15 */
+#define FDCAN_TIMESTAMP_PRESC_16 ((uint32_t)0x000F0000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 16 */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Timeout_Operation FDCAN timeout operation
+  * @{
+  */
+#define FDCAN_TIMEOUT_CONTINUOUS    ((uint32_t)0x00000000U) /*!< Timeout continuous operation        */
+#define FDCAN_TIMEOUT_TX_EVENT_FIFO ((uint32_t)0x00000002U) /*!< Timeout controlled by Tx Event FIFO */
+#define FDCAN_TIMEOUT_RX_FIFO0      ((uint32_t)0x00000004U) /*!< Timeout controlled by Rx FIFO 0     */
+#define FDCAN_TIMEOUT_RX_FIFO1      ((uint32_t)0x00000006U) /*!< Timeout controlled by Rx FIFO 1     */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TT_Reference_Message_Payload FDCAN TT reference message payload
+  * @{
+  */
+#define FDCAN_TT_REF_MESSAGE_NO_PAYLOAD  ((uint32_t)0x00000000U)      /*!< Reference message has no additional payload  */
+#define FDCAN_TT_REF_MESSAGE_ADD_PAYLOAD ((uint32_t)FDCAN_TTRMC_RMPS) /*!< Additional payload is taken from Tx Buffer 0 */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TT_Repeat_Factor FDCAN TT repeat factor
+  * @{
+  */
+#define FDCAN_TT_REPEAT_EVERY_CYCLE      ((uint32_t)0x00000000U) /*!< Trigger valid for all cycles   */
+#define FDCAN_TT_REPEAT_EVERY_2ND_CYCLE  ((uint32_t)0x00000002U) /*!< Trigger valid every 2dn cycle  */
+#define FDCAN_TT_REPEAT_EVERY_4TH_CYCLE  ((uint32_t)0x00000004U) /*!< Trigger valid every 4th cycle  */
+#define FDCAN_TT_REPEAT_EVERY_8TH_CYCLE  ((uint32_t)0x00000008U) /*!< Trigger valid every 8th cycle  */
+#define FDCAN_TT_REPEAT_EVERY_16TH_CYCLE ((uint32_t)0x00000010U) /*!< Trigger valid every 16th cycle */
+#define FDCAN_TT_REPEAT_EVERY_32ND_CYCLE ((uint32_t)0x00000020U) /*!< Trigger valid every 32nd cycle */
+#define FDCAN_TT_REPEAT_EVERY_64TH_CYCLE ((uint32_t)0x00000040U) /*!< Trigger valid every 64th cycle */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TT_Trigger_Type FDCAN TT trigger type
+  * @{
+  */
+#define FDCAN_TT_TX_REF_TRIGGER         ((uint32_t)0x00000000U) /*!< Transmit reference message in strictly time-triggered operation                                                     */
+#define FDCAN_TT_TX_REF_TRIGGER_GAP     ((uint32_t)0x00000001U) /*!< Transmit reference message in external event-synchronized time-triggered operation                                  */
+#define FDCAN_TT_TX_TRIGGER_SINGLE      ((uint32_t)0x00000002U) /*!< Start a single transmission in an exclusive time window                                                             */
+#define FDCAN_TT_TX_TRIGGER_CONTINUOUS  ((uint32_t)0x00000003U) /*!< Start a continuous transmission in an exclusive time window                                                         */
+#define FDCAN_TT_TX_TRIGGER_ARBITRATION ((uint32_t)0x00000004U) /*!< Start a transmission in an arbitration time window                                                                  */
+#define FDCAN_TT_TX_TRIGGER_MERGED      ((uint32_t)0x00000005U) /*!< Start a merged arbitration window                                                                                   */
+#define FDCAN_TT_WATCH_TRIGGER          ((uint32_t)0x00000006U) /*!< Check for missing reference messages in strictly time-triggered operation                                           */
+#define FDCAN_TT_WATCH_TRIGGER_GAP      ((uint32_t)0x00000007U) /*!< Check for missing reference messages in external event-synchronized time-triggered operation                        */
+#define FDCAN_TT_RX_TRIGGER             ((uint32_t)0x00000008U) /*!< Check for the reception of periodic messages in exclusive time windows                                              */
+#define FDCAN_TT_TIME_BASE_TRIGGER      ((uint32_t)0x00000009U) /*!< Generate internal/external events depending on TmEventInt/TmEventExt configuration                                  */
+#define FDCAN_TT_END_OF_LIST            ((uint32_t)0x0000000AU) /*!< Illegal trigger, to be assigned to the unused triggers after a FDCAN_TT_WATCH_TRIGGER or FDCAN_TT_WATCH_TRIGGER_GAP */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TT_Time_Mark_Event_Internal FDCAN TT time mark event internal
+  * @{
+  */
+#define FDCAN_TT_TM_NO_INTERNAL_EVENT  ((uint32_t)0x00000000U) /*!< No action                                               */
+#define FDCAN_TT_TM_GEN_INTERNAL_EVENT ((uint32_t)0x00000020U) /*!< Internal event is generated when trigger becomes active */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TT_Time_Mark_Event_External FDCAN TT time mark event external
+  * @{
+  */
+#define FDCAN_TT_TM_NO_EXTERNAL_EVENT  ((uint32_t)0x00000000U) /*!< No action                                                       */
+#define FDCAN_TT_TM_GEN_EXTERNAL_EVENT ((uint32_t)0x00000010U) /*!< External event (pulse) is generated when trigger becomes active */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_operation_mode FDCAN Operation Mode
+  * @{
+  */
+#define FDCAN_TT_COMMUNICATION_LEVEL1    ((uint32_t)0x00000001U) /*!< Time triggered communication, level 1 */
+#define FDCAN_TT_COMMUNICATION_LEVEL2    ((uint32_t)0x00000002U) /*!< Time triggered communication, level 2 */
+#define FDCAN_TT_COMMUNICATION_LEVEL0    ((uint32_t)0x00000003U) /*!< Time triggered communication, level 0 */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TT_operation FDCAN TT Operation
+  * @{
+  */
+#define FDCAN_STRICTLY_TT_OPERATION     ((uint32_t)0x00000000U)     /*!< Strictly time-triggered operation                    */
+#define FDCAN_EXT_EVT_SYNC_TT_OPERATION ((uint32_t)FDCAN_TTOCF_GEN) /*!< External event-synchronized time-triggered operation */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TT_time_master FDCAN TT Time Master
+  * @{
+  */
+#define FDCAN_TT_SLAVE            ((uint32_t)0x00000000U)    /*!< Time slave            */
+#define FDCAN_TT_POTENTIAL_MASTER ((uint32_t)FDCAN_TTOCF_TM) /*!< Potential time master */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TT_external_clk_sync FDCAN TT External Clock Synchronization
+  * @{
+  */
+#define FDCAN_TT_EXT_CLK_SYNC_DISABLE ((uint32_t)0x00000000U)      /*!< External clock synchronization in Level 0,2 disabled */
+#define FDCAN_TT_EXT_CLK_SYNC_ENABLE  ((uint32_t)FDCAN_TTOCF_EECS) /*!< External clock synchronization in Level 0,2 enabled  */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TT_global_time_filtering FDCAN TT Global Time Filtering
+  * @{
+  */
+#define FDCAN_TT_GLOB_TIME_FILT_DISABLE ((uint32_t)0x00000000U)      /*!< Global time filtering in Level 0,2 disabled */
+#define FDCAN_TT_GLOB_TIME_FILT_ENABLE  ((uint32_t)FDCAN_TTOCF_EGTF) /*!< Global time filtering in Level 0,2 enabled  */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TT_auto_clk_calibration FDCAN TT Automatic Clock Calibration
+  * @{
+  */
+#define FDCAN_TT_AUTO_CLK_CALIB_DISABLE ((uint32_t)0x00000000U)     /*!< Automatic clock calibration in Level 0,2 disabled */
+#define FDCAN_TT_AUTO_CLK_CALIB_ENABLE  ((uint32_t)FDCAN_TTOCF_ECC) /*!< Automatic clock calibration in Level 0,2 enabled  */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TT_event_trig_polarity FDCAN TT Event Trigger Polarity
+  * @{
+  */
+#define FDCAN_TT_EVT_TRIG_POL_RISING  ((uint32_t)0x00000000U)      /*!< Rising edge trigger  */
+#define FDCAN_TT_EVT_TRIG_POL_FALLING ((uint32_t)FDCAN_TTOCF_EVTP) /*!< Falling edge trigger */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TT_basic_cycle_number FDCAN TT Basic Cycle Number
+  * @{
+  */
+#define FDCAN_TT_CYCLES_PER_MATRIX_1  ((uint32_t)0x00000000U) /*!< 1 Basic Cycle per Matrix   */
+#define FDCAN_TT_CYCLES_PER_MATRIX_2  ((uint32_t)0x00000001U) /*!< 2 Basic Cycles per Matrix  */
+#define FDCAN_TT_CYCLES_PER_MATRIX_4  ((uint32_t)0x00000003U) /*!< 4 Basic Cycles per Matrix  */
+#define FDCAN_TT_CYCLES_PER_MATRIX_8  ((uint32_t)0x00000007U) /*!< 8 Basic Cycles per Matrix  */
+#define FDCAN_TT_CYCLES_PER_MATRIX_16 ((uint32_t)0x0000000FU) /*!< 16 Basic Cycles per Matrix */
+#define FDCAN_TT_CYCLES_PER_MATRIX_32 ((uint32_t)0x0000001FU) /*!< 32 Basic Cycles per Matrix */
+#define FDCAN_TT_CYCLES_PER_MATRIX_64 ((uint32_t)0x0000003FU) /*!< 64 Basic Cycles per Matrix */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TT_cycle_start_sync FDCAN TT Cycle Start Sync
+  * @{
+  */
+#define FDCAN_TT_NO_SYNC_PULSE          ((uint32_t)0x00000000U) /*!< No sync pulse                      */
+#define FDCAN_TT_SYNC_BASIC_CYCLE_START ((uint32_t)0x00000040U) /*!< Sync pulse at start of basic cycle */
+#define FDCAN_TT_SYNC_MATRIX_START      ((uint32_t)0x00000080U) /*!< Sync pulse at start of matrix      */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TT_stop_watch_trig_selection FDCAN TT Stop Watch Trigger Selection
+  * @{
+  */
+#define FDCAN_TT_STOP_WATCH_TRIGGER_0 ((uint32_t)0x00000000U) /*!< TIM2 selected as stop watch trigger  */
+#define FDCAN_TT_STOP_WATCH_TRIGGER_1 ((uint32_t)0x00000001U) /*!< TIM3 selected as stop watch trigger  */
+#define FDCAN_TT_STOP_WATCH_TRIGGER_2 ((uint32_t)0x00000002U) /*!< ETH selected as stop watch trigger   */
+#define FDCAN_TT_STOP_WATCH_TRIGGER_3 ((uint32_t)0x00000003U) /*!< HRTIM selected as stop watch trigger */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TT_event_trig_selection FDCAN TT Event Trigger Selection
+  * @{
+  */
+#define FDCAN_TT_EVENT_TRIGGER_0 ((uint32_t)0x00000000U) /*!< TIM2 selected as event trigger  */
+#define FDCAN_TT_EVENT_TRIGGER_1 ((uint32_t)0x00000010U) /*!< TIM3 selected as event trigger  */
+#define FDCAN_TT_EVENT_TRIGGER_2 ((uint32_t)0x00000020U) /*!< ETH selected as event trigger   */
+#define FDCAN_TT_EVENT_TRIGGER_3 ((uint32_t)0x00000030U) /*!< HRTIM selected as event trigger */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TT_stop_watch_source FDCAN TT Stop Watch Source
+  * @{
+  */
+#define FDCAN_TT_STOP_WATCH_DISABLED    ((uint32_t)0x00000000U) /*!< Stop Watch disabled                                                        */
+#define FDCAN_TT_STOP_WATCH_CYCLE_TIME  ((uint32_t)0x00000008U) /*!< Actual value of cycle time is copied to Capture Time register (TTCPT.SWV)  */
+#define FDCAN_TT_STOP_WATCH_LOCAL_TIME  ((uint32_t)0x00000010U) /*!< Actual value of local time is copied to Capture Time register (TTCPT.SWV)  */
+#define FDCAN_TT_STOP_WATCH_GLOBAL_TIME ((uint32_t)0x00000018U) /*!< Actual value of global time is copied to Capture Time register (TTCPT.SWV) */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TT_stop_watch_polarity FDCAN TT Stop Watch Polarity
+  * @{
+  */
+#define FDCAN_TT_STOP_WATCH_RISING  ((uint32_t)0x00000000U) /*!< Selected stop watch source is captured at rising edge of fdcan1_swt  */
+#define FDCAN_TT_STOP_WATCH_FALLING ((uint32_t)0x00000004U) /*!< Selected stop watch source is captured at falling edge of fdcan1_swt */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TT_time_mark_source FDCAN TT Time Mark Source
+  * @{
+  */
+#define FDCAN_TT_REG_TIMEMARK_DIABLED  ((uint32_t)0x00000000U) /*!< No Register Time Mark Interrupt generated               */
+#define FDCAN_TT_REG_TIMEMARK_CYC_TIME ((uint32_t)0x00000040U) /*!< Register Time Mark Interrupt if Time Mark = cycle time  */
+#define FDCAN_TT_REG_TIMEMARK_LOC_TIME ((uint32_t)0x00000080U) /*!< Register Time Mark Interrupt if Time Mark = local time  */
+#define FDCAN_TT_REG_TIMEMARK_GLO_TIME ((uint32_t)0x000000C0U) /*!< Register Time Mark Interrupt if Time Mark = global time */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TT_error_level FDCAN TT Error Level
+  * @{
+  */
+#define FDCAN_TT_NO_ERROR     ((uint32_t)0x00000000U) /*!< Severity 0 - No Error     */
+#define FDCAN_TT_WARNING      ((uint32_t)0x00000001U) /*!< Severity 1 - Warning      */
+#define FDCAN_TT_ERROR        ((uint32_t)0x00000002U) /*!< Severity 2 - Error        */
+#define FDCAN_TT_SEVERE_ERROR ((uint32_t)0x00000003U) /*!< Severity 3 - Severe Error */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TT_master_state FDCAN TT Master State
+  * @{
+  */
+#define FDCAN_TT_MASTER_OFF          ((uint32_t)0x00000000U) /*!< Master_Off, no master properties relevant */
+#define FDCAN_TT_TIME_SLAVE          ((uint32_t)0x00000004U) /*!< Operating as Time Slave                   */
+#define FDCAN_TT_BACKUP_TIME_MASTER  ((uint32_t)0x00000008U) /*!< Operating as Backup Time Master           */
+#define FDCAN_TT_CURRENT_TIME_MASTER ((uint32_t)0x0000000CU) /*!< Operating as current Time Master          */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TT_sync_state FDCAN TT Synchronization State
+  * @{
+  */
+#define FDCAN_TT_OUT_OF_SYNC   ((uint32_t)0x00000000U) /*!< Out of Synchronization         */
+#define FDCAN_TT_SYNCHRONIZING ((uint32_t)0x00000010U) /*!< Synchronizing to communication */
+#define FDCAN_TT_IN_GAP        ((uint32_t)0x00000020U) /*!< Schedule suspended by Gap      */
+#define FDCAN_TT_IN_SCHEDULE   ((uint32_t)0x00000030U) /*!< Synchronized to schedule       */
+/**
+  * @}
+  */
+
+/** @defgroup Interrupt_Masks Interrupt masks
+  * @{
+  */
+#define FDCAN_IR_MASK ((uint32_t)0x3FCFFFFFU) /*!< FDCAN interrupts mask */
+#define CCU_IR_MASK   ((uint32_t)0xC0000000U) /*!< CCU interrupts mask   */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_flags FDCAN Flags
+  * @{
+  */
+#define FDCAN_FLAG_TX_COMPLETE             FDCAN_IR_TC             /*!< Transmission Completed                                */
+#define FDCAN_FLAG_TX_ABORT_COMPLETE       FDCAN_IR_TCF            /*!< Transmission Cancellation Finished                    */
+#define FDCAN_FLAG_TX_FIFO_EMPTY           FDCAN_IR_TFE            /*!< Tx FIFO Empty                                         */
+#define FDCAN_FLAG_RX_HIGH_PRIORITY_MSG    FDCAN_IR_HPM            /*!< High priority message received                        */
+#define FDCAN_FLAG_RX_BUFFER_NEW_MESSAGE   FDCAN_IR_DRX            /*!< At least one received message stored into a Rx Buffer */
+#define FDCAN_FLAG_TX_EVT_FIFO_ELT_LOST    FDCAN_IR_TEFL           /*!< Tx Event FIFO element lost                            */
+#define FDCAN_FLAG_TX_EVT_FIFO_FULL        FDCAN_IR_TEFF           /*!< Tx Event FIFO full                                    */
+#define FDCAN_FLAG_TX_EVT_FIFO_WATERMARK   FDCAN_IR_TEFW           /*!< Tx Event FIFO fill level reached watermark            */
+#define FDCAN_FLAG_TX_EVT_FIFO_NEW_DATA    FDCAN_IR_TEFN           /*!< Tx Handler wrote Tx Event FIFO element                */
+#define FDCAN_FLAG_RX_FIFO0_MESSAGE_LOST   FDCAN_IR_RF0L           /*!< Rx FIFO 0 message lost                                */
+#define FDCAN_FLAG_RX_FIFO0_FULL           FDCAN_IR_RF0F           /*!< Rx FIFO 0 full                                        */
+#define FDCAN_FLAG_RX_FIFO0_WATERMARK      FDCAN_IR_RF0W           /*!< Rx FIFO 0 fill level reached watermark                */
+#define FDCAN_FLAG_RX_FIFO0_NEW_MESSAGE    FDCAN_IR_RF0N           /*!< New message written to Rx FIFO 0                      */
+#define FDCAN_FLAG_RX_FIFO1_MESSAGE_LOST   FDCAN_IR_RF1L           /*!< Rx FIFO 1 message lost                                */
+#define FDCAN_FLAG_RX_FIFO1_FULL           FDCAN_IR_RF1F           /*!< Rx FIFO 1 full                                        */
+#define FDCAN_FLAG_RX_FIFO1_WATERMARK      FDCAN_IR_RF1W           /*!< Rx FIFO 1 fill level reached watermark                */
+#define FDCAN_FLAG_RX_FIFO1_NEW_MESSAGE    FDCAN_IR_RF1N           /*!< New message written to Rx FIFO 1                      */
+#define FDCAN_FLAG_RAM_ACCESS_FAILURE      FDCAN_IR_MRAF           /*!< Message RAM access failure occurred                   */
+#define FDCAN_FLAG_ERROR_LOGGING_OVERFLOW  FDCAN_IR_ELO            /*!< Overflow of FDCAN Error Logging Counter occurred      */
+#define FDCAN_FLAG_ERROR_PASSIVE           FDCAN_IR_EP             /*!< Error_Passive status changed                          */
+#define FDCAN_FLAG_ERROR_WARNING           FDCAN_IR_EW             /*!< Error_Warning status changed                          */
+#define FDCAN_FLAG_BUS_OFF                 FDCAN_IR_BO             /*!< Bus_Off status changed                                */
+#define FDCAN_FLAG_RAM_WATCHDOG            FDCAN_IR_WDI            /*!< Message RAM Watchdog event due to missing READY       */
+#define FDCAN_FLAG_ARB_PROTOCOL_ERROR      FDCAN_IR_PEA            /*!< Protocol error in arbitration phase detected          */
+#define FDCAN_FLAG_DATA_PROTOCOL_ERROR     FDCAN_IR_PED            /*!< Protocol error in data phase detected                 */
+#define FDCAN_FLAG_RESERVED_ADDRESS_ACCESS FDCAN_IR_ARA            /*!< Access to reserved address occurred                   */
+#define FDCAN_FLAG_TIMESTAMP_WRAPAROUND    FDCAN_IR_TSW            /*!< Timestamp counter wrapped around                      */
+#define FDCAN_FLAG_TIMEOUT_OCCURRED        FDCAN_IR_TOO            /*!< Timeout reached                                       */
+#define FDCAN_FLAG_CALIB_STATE_CHANGED     (FDCANCCU_IR_CSC << 30) /*!< Clock calibration state changed                       */
+#define FDCAN_FLAG_CALIB_WATCHDOG_EVENT    (FDCANCCU_IR_CWE << 30) /*!< Clock calibration watchdog event occurred             */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Interrupts FDCAN Interrupts
+  * @{
+  */
+
+/** @defgroup FDCAN_Tx_Interrupts FDCAN Tx Interrupts
+  * @{
+  */
+#define FDCAN_IT_TX_COMPLETE           FDCAN_IE_TCE   /*!< Transmission Completed                                */
+#define FDCAN_IT_TX_ABORT_COMPLETE     FDCAN_IE_TCFE  /*!< Transmission Cancellation Finished                    */
+#define FDCAN_IT_TX_FIFO_EMPTY         FDCAN_IE_TFEE  /*!< Tx FIFO Empty                                         */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Rx_Interrupts FDCAN Rx Interrupts
+  * @{
+  */
+#define FDCAN_IT_RX_HIGH_PRIORITY_MSG  FDCAN_IE_HPME  /*!< High priority message received                        */
+#define FDCAN_IT_RX_BUFFER_NEW_MESSAGE FDCAN_IE_DRXE  /*!< At least one received message stored into a Rx Buffer */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Counter_Interrupts FDCAN Counter Interrupts
+  * @{
+  */
+#define FDCAN_IT_TIMESTAMP_WRAPAROUND  FDCAN_IE_TSWE  /*!< Timestamp counter wrapped around                      */
+#define FDCAN_IT_TIMEOUT_OCCURRED      FDCAN_IE_TOOE  /*!< Timeout reached                                       */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Clock_Calibration_Interrupts Clock Calibration Interrupts
+  * @{
+  */
+#define FDCAN_IT_CALIB_STATE_CHANGED  (FDCANCCU_IE_CSCE << 30) /*!< Clock calibration state changed           */
+#define FDCAN_IT_CALIB_WATCHDOG_EVENT (FDCANCCU_IE_CWEE << 30) /*!< Clock calibration watchdog event occurred */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Tx_Event_Fifo_Interrupts FDCAN Tx Event FIFO Interrupts
+  * @{
+  */
+#define FDCAN_IT_TX_EVT_FIFO_ELT_LOST  FDCAN_IE_TEFLE /*!< Tx Event FIFO element lost                 */
+#define FDCAN_IT_TX_EVT_FIFO_FULL      FDCAN_IE_TEFFE /*!< Tx Event FIFO full                         */
+#define FDCAN_IT_TX_EVT_FIFO_WATERMARK FDCAN_IE_TEFWE /*!< Tx Event FIFO fill level reached watermark */
+#define FDCAN_IT_TX_EVT_FIFO_NEW_DATA  FDCAN_IE_TEFNE /*!< Tx Handler wrote Tx Event FIFO element     */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Rx_Fifo0_Interrupts FDCAN Rx FIFO 0 Interrupts
+  * @{
+  */
+#define FDCAN_IT_RX_FIFO0_MESSAGE_LOST FDCAN_IE_RF0LE /*!< Rx FIFO 0 message lost                 */
+#define FDCAN_IT_RX_FIFO0_FULL         FDCAN_IE_RF0FE /*!< Rx FIFO 0 full                         */
+#define FDCAN_IT_RX_FIFO0_WATERMARK    FDCAN_IE_RF0WE /*!< Rx FIFO 0 fill level reached watermark */
+#define FDCAN_IT_RX_FIFO0_NEW_MESSAGE  FDCAN_IE_RF0NE /*!< New message written to Rx FIFO 0       */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Rx_Fifo1_Interrupts FDCAN Rx FIFO 1 Interrupts
+  * @{
+  */
+#define FDCAN_IT_RX_FIFO1_MESSAGE_LOST FDCAN_IE_RF1LE /*!< Rx FIFO 1 message lost                 */
+#define FDCAN_IT_RX_FIFO1_FULL         FDCAN_IE_RF1FE /*!< Rx FIFO 1 full                         */
+#define FDCAN_IT_RX_FIFO1_WATERMARK    FDCAN_IE_RF1WE /*!< Rx FIFO 1 fill level reached watermark */
+#define FDCAN_IT_RX_FIFO1_NEW_MESSAGE  FDCAN_IE_RF1NE /*!< New message written to Rx FIFO 1       */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Error_Interrupts FDCAN Error Interrupts
+  * @{
+  */
+#define FDCAN_IT_RAM_ACCESS_FAILURE      FDCAN_IE_MRAFE /*!< Message RAM access failure occurred              */
+#define FDCAN_IT_ERROR_LOGGING_OVERFLOW  FDCAN_IE_ELOE  /*!< Overflow of FDCAN Error Logging Counter occurred */
+#define FDCAN_IT_RAM_WATCHDOG            FDCAN_IE_WDIE  /*!< Message RAM Watchdog event due to missing READY  */
+#define FDCAN_IT_ARB_PROTOCOL_ERROR      FDCAN_IE_PEAE  /*!< Protocol error in arbitration phase detected     */
+#define FDCAN_IT_DATA_PROTOCOL_ERROR     FDCAN_IE_PEDE  /*!< Protocol error in data phase detected            */
+#define FDCAN_IT_RESERVED_ADDRESS_ACCESS FDCAN_IE_ARAE  /*!< Access to reserved address occurred              */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Error_Status_Interrupts FDCAN Error Status Interrupts
+  * @{
+  */
+#define FDCAN_IT_ERROR_PASSIVE FDCAN_IE_EPE /*!< Error_Passive status changed */
+#define FDCAN_IT_ERROR_WARNING FDCAN_IE_EWE /*!< Error_Warning status changed */
+#define FDCAN_IT_BUS_OFF       FDCAN_IE_BOE /*!< Bus_Off status changed       */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TTflags FDCAN TT Flags
+  * @{
+  */
+#define FDCAN_TT_FLAG_BASIC_CYCLE_START    FDCAN_TTIR_SBC  /*!< Start of Basic Cycle             */
+#define FDCAN_TT_FLAG_MATRIX_CYCLE_START   FDCAN_TTIR_SMC  /*!< Start of Matrix Cycle            */
+#define FDCAN_TT_FLAG_SYNC_MODE_CHANGE     FDCAN_TTIR_CSM  /*!< Change of Synchronization Mode   */
+#define FDCAN_TT_FLAG_START_OF_GAP         FDCAN_TTIR_SOG  /*!< Start of Gap                     */
+#define FDCAN_TT_FLAG_REG_TIME_MARK        FDCAN_TTIR_RTMI /*!< Register Time Mark Interrupt     */
+#define FDCAN_TT_FLAG_TRIG_TIME_MARK       FDCAN_TTIR_TTMI /*!< Trigger Time Mark Event Internal */
+#define FDCAN_TT_FLAG_STOP_WATCH           FDCAN_TTIR_SWE  /*!< Stop Watch Event                 */
+#define FDCAN_TT_FLAG_GLOBAL_TIME_WRAP     FDCAN_TTIR_GTW  /*!< Global Time Wrap                 */
+#define FDCAN_TT_FLAG_GLOBAL_TIME_DISC     FDCAN_TTIR_GTD  /*!< Global Time Discontinuity        */
+#define FDCAN_TT_FLAG_GLOBAL_TIME_ERROR    FDCAN_TTIR_GTE  /*!< Global Time Error                */
+#define FDCAN_TT_FLAG_TX_COUNT_UNDERFLOW   FDCAN_TTIR_TXU  /*!< Tx Count Underflow               */
+#define FDCAN_TT_FLAG_TX_COUNT_OVERFLOW    FDCAN_TTIR_TXO  /*!< Tx Count Overflow                */
+#define FDCAN_TT_FLAG_SCHEDULING_ERROR_1   FDCAN_TTIR_SE1  /*!< Scheduling Error 1               */
+#define FDCAN_TT_FLAG_SCHEDULING_ERROR_2   FDCAN_TTIR_SE2  /*!< Scheduling Error 2               */
+#define FDCAN_TT_FLAG_ERROR_LEVEL_CHANGE   FDCAN_TTIR_ELC  /*!< Error Level Changed              */
+#define FDCAN_TT_FLAG_INIT_WATCH_TRIGGER   FDCAN_TTIR_IWT  /*!< Initialization Watch Trigger     */
+#define FDCAN_TT_FLAG_WATCH_TRIGGER        FDCAN_TTIR_WT   /*!< Watch Trigger                    */
+#define FDCAN_TT_FLAG_APPLICATION_WATCHDOG FDCAN_TTIR_AW   /*!< Application Watchdog             */
+#define FDCAN_TT_FLAG_CONFIG_ERROR         FDCAN_TTIR_CER  /*!< Configuration Error              */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TTInterrupts FDCAN TT Interrupts
+  * @{
+  */
+
+/** @defgroup FDCAN_TTScheduleSynchronization_Interrupts FDCAN TT Schedule Synchronization Interrupts
+  * @{
+  */
+#define FDCAN_TT_IT_BASIC_CYCLE_START  FDCAN_TTIE_SBCE /*!< Start of Basic Cycle           */
+#define FDCAN_TT_IT_MATRIX_CYCLE_START FDCAN_TTIE_SMCE /*!< Start of Matrix Cycle          */
+#define FDCAN_TT_IT_SYNC_MODE_CHANGE   FDCAN_TTIE_CSME /*!< Change of Synchronization Mode */
+#define FDCAN_TT_IT_START_OF_GAP       FDCAN_TTIE_SOGE /*!< Start of Gap                   */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TTTimeMark_Interrupts FDCAN TT Time Mark Interrupts
+  * @{
+  */
+#define FDCAN_TT_IT_REG_TIME_MARK  FDCAN_TTIE_RTMIE /*!< Register Time Mark Interrupt     */
+#define FDCAN_TT_IT_TRIG_TIME_MARK FDCAN_TTIE_TTMIE /*!< Trigger Time Mark Event Internal */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TTStopWatch_Interrupt FDCAN TT Stop Watch Interrupt
+  * @{
+  */
+#define FDCAN_TT_IT_STOP_WATCH FDCAN_TTIE_SWEE /*!< Stop Watch Event */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TTGlobalTime_Interrupts FDCAN TT Global Time Interrupts
+  * @{
+  */
+#define FDCAN_TT_IT_GLOBAL_TIME_WRAP FDCAN_TTIE_GTWE  /*!< Global Time Wrap          */
+#define FDCAN_TT_IT_GLOBAL_TIME_DISC FDCAN_TTIE_GTDE  /*!< Global Time Discontinuity */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TTDisturbingError_Interrupts FDCAN TT Disturbing Error Interrupts
+  * @{
+  */
+#define FDCAN_TT_IT_GLOBAL_TIME_ERROR  FDCAN_TTIE_GTEE /*!< Global Time Error   */
+#define FDCAN_TT_IT_TX_COUNT_UNDERFLOW FDCAN_TTIE_TXUE /*!< Tx Count Underflow  */
+#define FDCAN_TT_IT_TX_COUNT_OVERFLOW  FDCAN_TTIE_TXOE /*!< Tx Count Overflow   */
+#define FDCAN_TT_IT_SCHEDULING_ERROR_1 FDCAN_TTIE_SE1E /*!< Scheduling Error 1  */
+#define FDCAN_TT_IT_SCHEDULING_ERROR_2 FDCAN_TTIE_SE2E /*!< Scheduling Error 2  */
+#define FDCAN_TT_IT_ERROR_LEVEL_CHANGE FDCAN_TTIE_ELCE /*!< Error Level Changed */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TTFatalError_Interrupts FDCAN TT Fatal Error Interrupts
+  * @{
+  */
+#define FDCAN_TT_IT_INIT_WATCH_TRIGGER   FDCAN_TTIE_IWTE /*!< Initialization Watch Trigger */
+#define FDCAN_TT_IT_WATCH_TRIGGER        FDCAN_TTIE_WTE  /*!< Watch Trigger                */
+#define FDCAN_TT_IT_APPLICATION_WATCHDOG FDCAN_TTIE_AWE  /*!< Application Watchdog         */
+#define FDCAN_TT_IT_CONFIG_ERROR         FDCAN_TTIE_CERE /*!< Configuration Error          */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup FDCAN_Exported_Macros FDCAN Exported Macros
+  * @{
+  */
+
+/** @brief  Reset FDCAN handle state.
+  * @param  __HANDLE__ FDCAN handle.
+  * @retval None
+  */
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+#define __HAL_FDCAN_RESET_HANDLE_STATE(__HANDLE__) do{                                                \
+                                                      (__HANDLE__)->State = HAL_FDCAN_STATE_RESET;    \
+                                                      (__HANDLE__)->MspInitCallback = NULL;           \
+                                                      (__HANDLE__)->MspDeInitCallback = NULL;         \
+                                                     } while(0)
+#else
+#define __HAL_FDCAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_FDCAN_STATE_RESET)
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+
+/**
+  * @brief  Enable the specified FDCAN interrupts.
+  * @param  __HANDLE__ FDCAN handle.
+  * @param  __INTERRUPT__ FDCAN interrupt.
+  *         This parameter can be any combination of @arg FDCAN_Interrupts
+  * @retval None
+  */
+#define __HAL_FDCAN_ENABLE_IT(__HANDLE__, __INTERRUPT__)             \
+  do{                                                                \
+    (__HANDLE__)->Instance->IE |= ((__INTERRUPT__) & FDCAN_IR_MASK); \
+    FDCAN_CCU->IE |= (((__INTERRUPT__) & CCU_IR_MASK) >> 30);        \
+  }while(0)
+
+
+/**
+  * @brief  Disable the specified FDCAN interrupts.
+  * @param  __HANDLE__ FDCAN handle.
+  * @param  __INTERRUPT__ FDCAN interrupt.
+  *         This parameter can be any combination of @arg FDCAN_Interrupts
+  * @retval None
+  */
+#define __HAL_FDCAN_DISABLE_IT(__HANDLE__, __INTERRUPT__)               \
+  do{                                                                   \
+    ((__HANDLE__)->Instance->IE) &= ~((__INTERRUPT__) & FDCAN_IR_MASK); \
+    FDCAN_CCU->IE &= ~(((__INTERRUPT__) & CCU_IR_MASK) >> 30);          \
+  }while(0)
+
+/**
+  * @brief  Check whether the specified FDCAN interrupt is set or not.
+  * @param  __HANDLE__ FDCAN handle.
+  * @param  __INTERRUPT__ FDCAN interrupt.
+  *         This parameter can be one of @arg FDCAN_Interrupts
+  * @retval ITStatus
+  */
+#define __HAL_FDCAN_GET_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) < FDCAN_IT_CALIB_WATCHDOG_EVENT) ? ((__HANDLE__)->Instance->IR & (__INTERRUPT__)) : ((FDCAN_CCU->IR << 30) & (__INTERRUPT__)))
+
+/**
+  * @brief  Clear the specified FDCAN interrupts.
+  * @param  __HANDLE__ FDCAN handle.
+  * @param  __INTERRUPT__ specifies the interrupts to clear.
+  *         This parameter can be any combination of @arg FDCAN_Interrupts
+  * @retval None
+  */
+#define __HAL_FDCAN_CLEAR_IT(__HANDLE__, __INTERRUPT__)               \
+do{                                                                   \
+    ((__HANDLE__)->Instance->IR) = ((__INTERRUPT__) & FDCAN_IR_MASK); \
+    FDCAN_CCU->IR = (((__INTERRUPT__) & CCU_IR_MASK) >> 30);          \
+  }while(0)
+
+/**
+  * @brief  Check whether the specified FDCAN flag is set or not.
+  * @param  __HANDLE__ FDCAN handle.
+  * @param  __FLAG__ FDCAN flag.
+  *         This parameter can be one of @arg FDCAN_flags
+  * @retval FlagStatus
+  */
+#define __HAL_FDCAN_GET_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) < FDCAN_FLAG_CALIB_WATCHDOG_EVENT) ? ((__HANDLE__)->Instance->IR & (__FLAG__)) : ((FDCAN_CCU->IR << 30) & (__FLAG__)))
+
+/**
+  * @brief  Clear the specified FDCAN flags.
+  * @param  __HANDLE__ FDCAN handle.
+  * @param  __FLAG__ specifies the flags to clear.
+  *         This parameter can be any combination of @arg FDCAN_flags
+  * @retval None
+  */
+#define __HAL_FDCAN_CLEAR_FLAG(__HANDLE__, __FLAG__)             \
+do{                                                              \
+    ((__HANDLE__)->Instance->IR) = ((__FLAG__) & FDCAN_IR_MASK); \
+    FDCAN_CCU->IR = (((__FLAG__) & CCU_IR_MASK) >> 30);          \
+  }while(0)
+
+/** @brief  Check if the specified FDCAN interrupt source is enabled or disabled.
+  * @param  __HANDLE__ FDCAN handle.
+  * @param  __INTERRUPT__ specifies the FDCAN interrupt source to check.
+  *         This parameter can be a value of @arg FDCAN_Interrupts
+  * @retval ITStatus
+  */
+#define __HAL_FDCAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) < FDCAN_IT_CALIB_WATCHDOG_EVENT) ? ((__HANDLE__)->Instance->IE & (__INTERRUPT__)) : ((FDCAN_CCU->IE << 30) & (__INTERRUPT__)))
+
+/**
+  * @brief  Enable the specified FDCAN TT interrupts.
+  * @param  __HANDLE__ FDCAN handle.
+  * @param  __INTERRUPT__ FDCAN TT interrupt.
+  *         This parameter can be any combination of @arg FDCAN_TTInterrupts
+  * @retval None
+  */
+#define __HAL_FDCAN_TT_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->ttcan->TTIE) |= (__INTERRUPT__))
+
+/**
+  * @brief  Disable the specified FDCAN TT interrupts.
+  * @param  __HANDLE__ FDCAN handle.
+  * @param  __INTERRUPT__ FDCAN TT interrupt.
+  *         This parameter can be any combination of @arg FDCAN_TTInterrupts
+  * @retval None
+  */
+#define __HAL_FDCAN_TT_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->ttcan->TTIE) &= ~(__INTERRUPT__))
+
+/**
+  * @brief  Check whether the specified FDCAN TT interrupt is set or not.
+  * @param  __HANDLE__ FDCAN handle.
+  * @param  __INTERRUPT__ FDCAN TT interrupt.
+  *         This parameter can be one of @arg FDCAN_TTInterrupts
+  * @retval ITStatus
+  */
+#define __HAL_FDCAN_TT_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->ttcan->TTIR) & (__INTERRUPT__))
+
+/**
+  * @brief  Clear the specified FDCAN TT interrupts.
+  * @param  __HANDLE__ FDCAN handle.
+  * @param  __INTERRUPT__ specifies the TT interrupts to clear.
+  *         This parameter can be any combination of @arg FDCAN_TTInterrupts
+  * @retval None
+  */
+#define __HAL_FDCAN_TT_CLEAR_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->ttcan->TTIR) = (__INTERRUPT__))
+
+/**
+  * @brief  Check whether the specified FDCAN TT flag is set or not.
+  * @param  __HANDLE__ FDCAN handle.
+  * @param  __FLAG__ FDCAN TT flag.
+  *         This parameter can be one of @arg FDCAN_TTflags
+  * @retval FlagStatus
+  */
+#define __HAL_FDCAN_TT_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->ttcan->TTIR) & (__FLAG__))
+
+/**
+  * @brief  Clear the specified FDCAN TT flags.
+  * @param  __HANDLE__ FDCAN handle.
+  * @param  __FLAG__ specifies the TT flags to clear.
+  *         This parameter can be any combination of @arg FDCAN_TTflags
+  * @retval None
+  */
+#define __HAL_FDCAN_TT_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->ttcan->TTIR) = (__FLAG__))
+
+/** @brief  Check if the specified FDCAN TT interrupt source is enabled or disabled.
+  * @param  __HANDLE__ FDCAN handle.
+  * @param  __INTERRUPT__ specifies the FDCAN TT interrupt source to check.
+  *         This parameter can be a value of @arg FDCAN_TTInterrupts
+  * @retval ITStatus
+  */
+#define __HAL_FDCAN_TT_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->ttcan->TTIE) & (__INTERRUPT__))
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup FDCAN_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup FDCAN_Exported_Functions_Group1
+  * @{
+  */
+/* Initialization and de-initialization functions *****************************/
+HAL_StatusTypeDef HAL_FDCAN_Init(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_DeInit(FDCAN_HandleTypeDef *hfdcan);
+void              HAL_FDCAN_MspInit(FDCAN_HandleTypeDef *hfdcan);
+void              HAL_FDCAN_MspDeInit(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_EnterPowerDownMode(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_ExitPowerDownMode(FDCAN_HandleTypeDef *hfdcan);
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+/* Callbacks Register/UnRegister functions  ***********************************/
+HAL_StatusTypeDef HAL_FDCAN_RegisterCallback(FDCAN_HandleTypeDef *hfdcan, HAL_FDCAN_CallbackIDTypeDef CallbackID, pFDCAN_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterCallback(FDCAN_HandleTypeDef *hfdcan, HAL_FDCAN_CallbackIDTypeDef CallbackID);
+HAL_StatusTypeDef HAL_FDCAN_RegisterClockCalibrationCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_ClockCalibrationCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterClockCalibrationCallback(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_RegisterTxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TxEventFifoCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_RegisterRxFifo0Callback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_RxFifo0CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterRxFifo0Callback(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_RegisterRxFifo1Callback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_RxFifo1CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterRxFifo1Callback(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_RegisterTxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TxBufferCompleteCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_RegisterTxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TxBufferAbortCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_RegisterErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_ErrorStatusCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_RegisterTTScheduleSyncCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TT_ScheduleSyncCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterTTScheduleSyncCallback(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_RegisterTTTimeMarkCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TT_TimeMarkCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterTTTimeMarkCallback(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_RegisterTTStopWatchCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TT_StopWatchCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterTTStopWatchCallback(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_RegisterTTGlobalTimeCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TT_GlobalTimeCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterTTGlobalTimeCallback(FDCAN_HandleTypeDef *hfdcan);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
+
+/** @addtogroup FDCAN_Exported_Functions_Group2
+  * @{
+  */
+/* Configuration functions ****************************************************/
+HAL_StatusTypeDef HAL_FDCAN_ConfigClockCalibration(FDCAN_HandleTypeDef *hfdcan, FDCAN_ClkCalUnitTypeDef *sCcuConfig);
+uint32_t          HAL_FDCAN_GetClockCalibrationState(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_ResetClockCalibrationState(FDCAN_HandleTypeDef *hfdcan);
+uint32_t          HAL_FDCAN_GetClockCalibrationCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t Counter);
+HAL_StatusTypeDef HAL_FDCAN_ConfigFilter(FDCAN_HandleTypeDef *hfdcan, FDCAN_FilterTypeDef *sFilterConfig);
+HAL_StatusTypeDef HAL_FDCAN_ConfigGlobalFilter(FDCAN_HandleTypeDef *hfdcan, uint32_t NonMatchingStd, uint32_t NonMatchingExt, uint32_t RejectRemoteStd, uint32_t RejectRemoteExt);
+HAL_StatusTypeDef HAL_FDCAN_ConfigExtendedIdMask(FDCAN_HandleTypeDef *hfdcan, uint32_t Mask);
+HAL_StatusTypeDef HAL_FDCAN_ConfigRxFifoOverwrite(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo, uint32_t OperationMode);
+HAL_StatusTypeDef HAL_FDCAN_ConfigFifoWatermark(FDCAN_HandleTypeDef *hfdcan, uint32_t FIFO, uint32_t Watermark);
+HAL_StatusTypeDef HAL_FDCAN_ConfigRamWatchdog(FDCAN_HandleTypeDef *hfdcan, uint32_t CounterStartValue);
+HAL_StatusTypeDef HAL_FDCAN_ConfigTimestampCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampPrescaler);
+HAL_StatusTypeDef HAL_FDCAN_EnableTimestampCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampOperation);
+HAL_StatusTypeDef HAL_FDCAN_DisableTimestampCounter(FDCAN_HandleTypeDef *hfdcan);
+uint16_t          HAL_FDCAN_GetTimestampCounter(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_ResetTimestampCounter(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_ConfigTimeoutCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimeoutOperation, uint32_t TimeoutPeriod);
+HAL_StatusTypeDef HAL_FDCAN_EnableTimeoutCounter(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_DisableTimeoutCounter(FDCAN_HandleTypeDef *hfdcan);
+uint16_t          HAL_FDCAN_GetTimeoutCounter(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_ResetTimeoutCounter(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_ConfigTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan, uint32_t TdcOffset, uint32_t TdcFilter);
+HAL_StatusTypeDef HAL_FDCAN_EnableTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_DisableTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_EnableISOMode(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_DisableISOMode(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_EnableEdgeFiltering(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_DisableEdgeFiltering(FDCAN_HandleTypeDef *hfdcan);
+/**
+  * @}
+  */
+
+/** @addtogroup FDCAN_Exported_Functions_Group3
+  * @{
+  */
+/* Control functions **********************************************************/
+HAL_StatusTypeDef HAL_FDCAN_Start(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_Stop(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxFifoQ(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData);
+HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxBuffer(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData, uint32_t BufferIndex);
+HAL_StatusTypeDef HAL_FDCAN_EnableTxBufferRequest(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndex);
+uint32_t HAL_FDCAN_GetLatestTxFifoQRequestBuffer(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_AbortTxRequest(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndex);
+HAL_StatusTypeDef HAL_FDCAN_GetRxMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t RxLocation, FDCAN_RxHeaderTypeDef *pRxHeader, uint8_t *pRxData);
+HAL_StatusTypeDef HAL_FDCAN_GetTxEvent(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxEventFifoTypeDef *pTxEvent);
+HAL_StatusTypeDef HAL_FDCAN_GetHighPriorityMessageStatus(FDCAN_HandleTypeDef *hfdcan, FDCAN_HpMsgStatusTypeDef *HpMsgStatus);
+HAL_StatusTypeDef HAL_FDCAN_GetProtocolStatus(FDCAN_HandleTypeDef *hfdcan, FDCAN_ProtocolStatusTypeDef *ProtocolStatus);
+HAL_StatusTypeDef HAL_FDCAN_GetErrorCounters(FDCAN_HandleTypeDef *hfdcan, FDCAN_ErrorCountersTypeDef *ErrorCounters);
+uint32_t HAL_FDCAN_IsRxBufferMessageAvailable(FDCAN_HandleTypeDef *hfdcan, uint32_t RxBufferIndex);
+uint32_t HAL_FDCAN_IsTxBufferMessagePending(FDCAN_HandleTypeDef *hfdcan, uint32_t TxBufferIndex);
+uint32_t HAL_FDCAN_GetRxFifoFillLevel(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo);
+uint32_t HAL_FDCAN_GetTxFifoFreeLevel(FDCAN_HandleTypeDef *hfdcan);
+uint32_t HAL_FDCAN_IsRestrictedOperationMode(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_ExitRestrictedOperationMode(FDCAN_HandleTypeDef *hfdcan);
+/**
+  * @}
+  */
+
+/** @addtogroup FDCAN_Exported_Functions_Group4
+  * @{
+  */
+/* TT Configuration and control functions**************************************/
+HAL_StatusTypeDef HAL_FDCAN_TT_ConfigOperation(FDCAN_HandleTypeDef *hfdcan, FDCAN_TT_ConfigTypeDef *pTTParams);
+HAL_StatusTypeDef HAL_FDCAN_TT_ConfigReferenceMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t IdType, uint32_t Identifier, uint32_t Payload);
+HAL_StatusTypeDef HAL_FDCAN_TT_ConfigTrigger(FDCAN_HandleTypeDef *hfdcan, FDCAN_TriggerTypeDef *sTriggerConfig);
+HAL_StatusTypeDef HAL_FDCAN_TT_SetGlobalTime(FDCAN_HandleTypeDef *hfdcan, uint32_t TimePreset);
+HAL_StatusTypeDef HAL_FDCAN_TT_SetClockSynchronization(FDCAN_HandleTypeDef *hfdcan, uint32_t NewTURNumerator);
+HAL_StatusTypeDef HAL_FDCAN_TT_ConfigStopWatch(FDCAN_HandleTypeDef *hfdcan, uint32_t Source, uint32_t Polarity);
+HAL_StatusTypeDef HAL_FDCAN_TT_ConfigRegisterTimeMark(FDCAN_HandleTypeDef *hfdcan, uint32_t TimeMarkSource, uint32_t TimeMarkValue, uint32_t RepeatFactor, uint32_t StartCycle);
+HAL_StatusTypeDef HAL_FDCAN_TT_EnableRegisterTimeMarkPulse(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_TT_DisableRegisterTimeMarkPulse(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_TT_EnableTriggerTimeMarkPulse(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_TT_DisableTriggerTimeMarkPulse(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_TT_EnableHardwareGapControl(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_TT_DisableHardwareGapControl(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_TT_EnableTimeMarkGapControl(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_TT_DisableTimeMarkGapControl(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_TT_SetNextIsGap(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_TT_SetEndOfGap(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_TT_ConfigExternalSyncPhase(FDCAN_HandleTypeDef *hfdcan, uint32_t TargetPhase);
+HAL_StatusTypeDef HAL_FDCAN_TT_EnableExternalSynchronization(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_TT_DisableExternalSynchronization(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_TT_GetOperationStatus(FDCAN_HandleTypeDef *hfdcan, FDCAN_TTOperationStatusTypeDef *TTOpStatus);
+/**
+  * @}
+  */
+
+/** @addtogroup FDCAN_Exported_Functions_Group5
+  * @{
+  */
+/* Interrupts management ******************************************************/
+HAL_StatusTypeDef HAL_FDCAN_ConfigInterruptLines(FDCAN_HandleTypeDef *hfdcan, uint32_t ITList, uint32_t InterruptLine);
+HAL_StatusTypeDef HAL_FDCAN_TT_ConfigInterruptLines(FDCAN_HandleTypeDef *hfdcan, uint32_t TTITList, uint32_t InterruptLine);
+HAL_StatusTypeDef HAL_FDCAN_ActivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t ActiveITs, uint32_t BufferIndexes);
+HAL_StatusTypeDef HAL_FDCAN_DeactivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t InactiveITs);
+HAL_StatusTypeDef HAL_FDCAN_TT_ActivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t ActiveTTITs);
+HAL_StatusTypeDef HAL_FDCAN_TT_DeactivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t InactiveTTITs);
+void              HAL_FDCAN_IRQHandler(FDCAN_HandleTypeDef *hfdcan);
+/**
+  * @}
+  */
+
+/** @addtogroup FDCAN_Exported_Functions_Group6
+  * @{
+  */
+/* Callback functions *********************************************************/
+void HAL_FDCAN_ClockCalibrationCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t ClkCalibrationITs);
+void HAL_FDCAN_TxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TxEventFifoITs);
+void HAL_FDCAN_RxFifo0Callback(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs);
+void HAL_FDCAN_RxFifo1Callback(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo1ITs);
+void HAL_FDCAN_TxFifoEmptyCallback(FDCAN_HandleTypeDef *hfdcan);
+void HAL_FDCAN_TxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes);
+void HAL_FDCAN_TxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes);
+void HAL_FDCAN_RxBufferNewMessageCallback(FDCAN_HandleTypeDef *hfdcan);
+void HAL_FDCAN_HighPriorityMessageCallback(FDCAN_HandleTypeDef *hfdcan);
+void HAL_FDCAN_TimestampWraparoundCallback(FDCAN_HandleTypeDef *hfdcan);
+void HAL_FDCAN_TimeoutOccurredCallback(FDCAN_HandleTypeDef *hfdcan);
+void HAL_FDCAN_ErrorCallback(FDCAN_HandleTypeDef *hfdcan);
+void HAL_FDCAN_ErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t ErrorStatusITs);
+void HAL_FDCAN_TT_ScheduleSyncCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TTSchedSyncITs);
+void HAL_FDCAN_TT_TimeMarkCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TTTimeMarkITs);
+void HAL_FDCAN_TT_StopWatchCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t SWTime, uint32_t SWCycleCount);
+void HAL_FDCAN_TT_GlobalTimeCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TTGlobTimeITs);
+/**
+  * @}
+  */
+
+/** @addtogroup FDCAN_Exported_Functions_Group7
+  * @{
+  */
+/* Peripheral State functions *************************************************/
+uint32_t HAL_FDCAN_GetError(FDCAN_HandleTypeDef *hfdcan);
+HAL_FDCAN_StateTypeDef HAL_FDCAN_GetState(FDCAN_HandleTypeDef *hfdcan);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private types -------------------------------------------------------------*/
+/** @defgroup FDCAN_Private_Types FDCAN Private Types
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup FDCAN_Private_Variables FDCAN Private Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup FDCAN_Private_Constants FDCAN Private Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup FDCAN_Private_Macros FDCAN Private Macros
+  * @{
+  */
+#define IS_FDCAN_FRAME_FORMAT(FORMAT) (((FORMAT) == FDCAN_FRAME_CLASSIC  ) || \
+                                       ((FORMAT) == FDCAN_FRAME_FD_NO_BRS) || \
+                                       ((FORMAT) == FDCAN_FRAME_FD_BRS   ))
+#define IS_FDCAN_MODE(MODE) (((MODE) == FDCAN_MODE_NORMAL              ) || \
+                             ((MODE) == FDCAN_MODE_RESTRICTED_OPERATION) || \
+                             ((MODE) == FDCAN_MODE_BUS_MONITORING      ) || \
+                             ((MODE) == FDCAN_MODE_INTERNAL_LOOPBACK   ) || \
+                             ((MODE) == FDCAN_MODE_EXTERNAL_LOOPBACK   ))
+
+#define IS_FDCAN_CLOCK_CALIBRATION(CALIBRATION) (((CALIBRATION) == FDCAN_CLOCK_CALIBRATION_DISABLE) || \
+                                                 ((CALIBRATION) == FDCAN_CLOCK_CALIBRATION_ENABLE ))
+
+#define IS_FDCAN_CKDIV(CKDIV) (((CKDIV) == FDCAN_CLOCK_DIV1 ) || \
+                               ((CKDIV) == FDCAN_CLOCK_DIV2 ) || \
+                               ((CKDIV) == FDCAN_CLOCK_DIV4 ) || \
+                               ((CKDIV) == FDCAN_CLOCK_DIV6 ) || \
+                               ((CKDIV) == FDCAN_CLOCK_DIV8 ) || \
+                               ((CKDIV) == FDCAN_CLOCK_DIV10) || \
+                               ((CKDIV) == FDCAN_CLOCK_DIV12) || \
+                               ((CKDIV) == FDCAN_CLOCK_DIV14) || \
+                               ((CKDIV) == FDCAN_CLOCK_DIV16) || \
+                               ((CKDIV) == FDCAN_CLOCK_DIV18) || \
+                               ((CKDIV) == FDCAN_CLOCK_DIV20) || \
+                               ((CKDIV) == FDCAN_CLOCK_DIV22) || \
+                               ((CKDIV) == FDCAN_CLOCK_DIV24) || \
+                               ((CKDIV) == FDCAN_CLOCK_DIV26) || \
+                               ((CKDIV) == FDCAN_CLOCK_DIV28) || \
+                               ((CKDIV) == FDCAN_CLOCK_DIV30))
+#define IS_FDCAN_NOMINAL_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 512U))
+#define IS_FDCAN_NOMINAL_SJW(SJW) (((SJW) >= 1U) && ((SJW) <= 128U))
+#define IS_FDCAN_NOMINAL_TSEG1(TSEG1) (((TSEG1) >= 1U) && ((TSEG1) <= 256U))
+#define IS_FDCAN_NOMINAL_TSEG2(TSEG2) (((TSEG2) >= 1U) && ((TSEG2) <= 128U))
+#define IS_FDCAN_DATA_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 32U))
+#define IS_FDCAN_DATA_SJW(SJW) (((SJW) >= 1U) && ((SJW) <= 16U))
+#define IS_FDCAN_DATA_TSEG1(TSEG1) (((TSEG1) >= 1U) && ((TSEG1) <= 32U))
+#define IS_FDCAN_DATA_TSEG2(TSEG2) (((TSEG2) >= 1U) && ((TSEG2) <= 16U))
+#define IS_FDCAN_MAX_VALUE(VALUE, MAX) ((VALUE) <= (MAX))
+#define IS_FDCAN_MIN_VALUE(VALUE, MIN) ((VALUE) >= (MIN))
+#define IS_FDCAN_DATA_SIZE(SIZE) (((SIZE) == FDCAN_DATA_BYTES_8 ) || \
+                                  ((SIZE) == FDCAN_DATA_BYTES_12) || \
+                                  ((SIZE) == FDCAN_DATA_BYTES_16) || \
+                                  ((SIZE) == FDCAN_DATA_BYTES_20) || \
+                                  ((SIZE) == FDCAN_DATA_BYTES_24) || \
+                                  ((SIZE) == FDCAN_DATA_BYTES_32) || \
+                                  ((SIZE) == FDCAN_DATA_BYTES_48) || \
+                                  ((SIZE) == FDCAN_DATA_BYTES_64))
+#define IS_FDCAN_TX_FIFO_QUEUE_MODE(MODE) (((MODE) == FDCAN_TX_FIFO_OPERATION ) || \
+                                           ((MODE) == FDCAN_TX_QUEUE_OPERATION))
+#define IS_FDCAN_ID_TYPE(ID_TYPE) (((ID_TYPE) == FDCAN_STANDARD_ID) || \
+                                   ((ID_TYPE) == FDCAN_EXTENDED_ID))
+#define IS_FDCAN_FILTER_CFG(CONFIG) (((CONFIG) == FDCAN_FILTER_DISABLE      ) || \
+                                     ((CONFIG) == FDCAN_FILTER_TO_RXFIFO0   ) || \
+                                     ((CONFIG) == FDCAN_FILTER_TO_RXFIFO1   ) || \
+                                     ((CONFIG) == FDCAN_FILTER_REJECT       ) || \
+                                     ((CONFIG) == FDCAN_FILTER_HP           ) || \
+                                     ((CONFIG) == FDCAN_FILTER_TO_RXFIFO0_HP) || \
+                                     ((CONFIG) == FDCAN_FILTER_TO_RXFIFO1_HP) || \
+                                     ((CONFIG) == FDCAN_FILTER_TO_RXBUFFER  ))
+#define IS_FDCAN_TX_LOCATION(LOCATION) (((LOCATION) == FDCAN_TX_BUFFER0 ) || ((LOCATION) == FDCAN_TX_BUFFER1 ) || \
+                                        ((LOCATION) == FDCAN_TX_BUFFER2 ) || ((LOCATION) == FDCAN_TX_BUFFER3 ) || \
+                                        ((LOCATION) == FDCAN_TX_BUFFER4 ) || ((LOCATION) == FDCAN_TX_BUFFER5 ) || \
+                                        ((LOCATION) == FDCAN_TX_BUFFER6 ) || ((LOCATION) == FDCAN_TX_BUFFER7 ) || \
+                                        ((LOCATION) == FDCAN_TX_BUFFER8 ) || ((LOCATION) == FDCAN_TX_BUFFER9 ) || \
+                                        ((LOCATION) == FDCAN_TX_BUFFER10) || ((LOCATION) == FDCAN_TX_BUFFER11) || \
+                                        ((LOCATION) == FDCAN_TX_BUFFER12) || ((LOCATION) == FDCAN_TX_BUFFER13) || \
+                                        ((LOCATION) == FDCAN_TX_BUFFER14) || ((LOCATION) == FDCAN_TX_BUFFER15) || \
+                                        ((LOCATION) == FDCAN_TX_BUFFER16) || ((LOCATION) == FDCAN_TX_BUFFER17) || \
+                                        ((LOCATION) == FDCAN_TX_BUFFER18) || ((LOCATION) == FDCAN_TX_BUFFER19) || \
+                                        ((LOCATION) == FDCAN_TX_BUFFER20) || ((LOCATION) == FDCAN_TX_BUFFER21) || \
+                                        ((LOCATION) == FDCAN_TX_BUFFER22) || ((LOCATION) == FDCAN_TX_BUFFER23) || \
+                                        ((LOCATION) == FDCAN_TX_BUFFER24) || ((LOCATION) == FDCAN_TX_BUFFER25) || \
+                                        ((LOCATION) == FDCAN_TX_BUFFER26) || ((LOCATION) == FDCAN_TX_BUFFER27) || \
+                                        ((LOCATION) == FDCAN_TX_BUFFER28) || ((LOCATION) == FDCAN_TX_BUFFER29) || \
+                                        ((LOCATION) == FDCAN_TX_BUFFER30) || ((LOCATION) == FDCAN_TX_BUFFER31))
+#define IS_FDCAN_RX_FIFO(FIFO) (((FIFO) == FDCAN_RX_FIFO0) || \
+                                ((FIFO) == FDCAN_RX_FIFO1))
+#define IS_FDCAN_RX_FIFO_MODE(MODE) (((MODE) == FDCAN_RX_FIFO_BLOCKING ) || \
+                                     ((MODE) == FDCAN_RX_FIFO_OVERWRITE))
+#define IS_FDCAN_STD_FILTER_TYPE(TYPE) (((TYPE) == FDCAN_FILTER_RANGE) || \
+                                        ((TYPE) == FDCAN_FILTER_DUAL ) || \
+                                        ((TYPE) == FDCAN_FILTER_MASK ))
+#define IS_FDCAN_EXT_FILTER_TYPE(TYPE) (((TYPE) == FDCAN_FILTER_RANGE        ) || \
+                                        ((TYPE) == FDCAN_FILTER_DUAL         ) || \
+                                        ((TYPE) == FDCAN_FILTER_MASK         ) || \
+                                        ((TYPE) == FDCAN_FILTER_RANGE_NO_EIDM))
+#define IS_FDCAN_FRAME_TYPE(TYPE) (((TYPE) == FDCAN_DATA_FRAME  ) || \
+                                   ((TYPE) == FDCAN_REMOTE_FRAME))
+#define IS_FDCAN_DLC(DLC) (((DLC) == FDCAN_DLC_BYTES_0 ) || \
+                           ((DLC) == FDCAN_DLC_BYTES_1 ) || \
+                           ((DLC) == FDCAN_DLC_BYTES_2 ) || \
+                           ((DLC) == FDCAN_DLC_BYTES_3 ) || \
+                           ((DLC) == FDCAN_DLC_BYTES_4 ) || \
+                           ((DLC) == FDCAN_DLC_BYTES_5 ) || \
+                           ((DLC) == FDCAN_DLC_BYTES_6 ) || \
+                           ((DLC) == FDCAN_DLC_BYTES_7 ) || \
+                           ((DLC) == FDCAN_DLC_BYTES_8 ) || \
+                           ((DLC) == FDCAN_DLC_BYTES_12) || \
+                           ((DLC) == FDCAN_DLC_BYTES_16) || \
+                           ((DLC) == FDCAN_DLC_BYTES_20) || \
+                           ((DLC) == FDCAN_DLC_BYTES_24) || \
+                           ((DLC) == FDCAN_DLC_BYTES_32) || \
+                           ((DLC) == FDCAN_DLC_BYTES_48) || \
+                           ((DLC) == FDCAN_DLC_BYTES_64))
+#define IS_FDCAN_ESI(ESI) (((ESI) == FDCAN_ESI_ACTIVE ) || \
+                           ((ESI) == FDCAN_ESI_PASSIVE))
+#define IS_FDCAN_BRS(BRS) (((BRS) == FDCAN_BRS_OFF) || \
+                           ((BRS) == FDCAN_BRS_ON ))
+#define IS_FDCAN_FDF(FDF) (((FDF) == FDCAN_CLASSIC_CAN) || \
+                           ((FDF) == FDCAN_FD_CAN     ))
+#define IS_FDCAN_EFC(EFC) (((EFC) == FDCAN_NO_TX_EVENTS   ) || \
+                           ((EFC) == FDCAN_STORE_TX_EVENTS))
+#define IS_FDCAN_IT(IT) (((IT) & ~(FDCAN_IR_MASK | CCU_IR_MASK)) == 0U)
+#define IS_FDCAN_TT_IT(IT) (((IT) & 0xFFF80000U) == 0U)
+#define IS_FDCAN_FIFO_WATERMARK(FIFO) (((FIFO) == FDCAN_CFG_TX_EVENT_FIFO) || \
+                                       ((FIFO) == FDCAN_CFG_RX_FIFO0     ) || \
+                                       ((FIFO) == FDCAN_CFG_RX_FIFO1     ))
+#define IS_FDCAN_NON_MATCHING(DESTINATION) (((DESTINATION) == FDCAN_ACCEPT_IN_RX_FIFO0) || \
+                                            ((DESTINATION) == FDCAN_ACCEPT_IN_RX_FIFO1) || \
+                                            ((DESTINATION) == FDCAN_REJECT            ))
+#define IS_FDCAN_REJECT_REMOTE(DESTINATION) (((DESTINATION) == FDCAN_FILTER_REMOTE) || \
+                                             ((DESTINATION) == FDCAN_REJECT_REMOTE))
+#define IS_FDCAN_IT_LINE(IT_LINE) (((IT_LINE) == FDCAN_INTERRUPT_LINE0) || \
+                                   ((IT_LINE) == FDCAN_INTERRUPT_LINE1))
+#define IS_FDCAN_TIMESTAMP(OPERATION) (((OPERATION) == FDCAN_TIMESTAMP_INTERNAL) || \
+                                       ((OPERATION) == FDCAN_TIMESTAMP_EXTERNAL))
+#define IS_FDCAN_TIMESTAMP_PRESCALER(PRESCALER) (((PRESCALER) == FDCAN_TIMESTAMP_PRESC_1 ) || \
+                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_2 ) || \
+                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_3 ) || \
+                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_4 ) || \
+                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_5 ) || \
+                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_6 ) || \
+                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_7 ) || \
+                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_8 ) || \
+                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_9 ) || \
+                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_10) || \
+                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_11) || \
+                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_12) || \
+                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_13) || \
+                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_14) || \
+                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_15) || \
+                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_16))
+#define IS_FDCAN_TIMEOUT(OPERATION) (((OPERATION) == FDCAN_TIMEOUT_CONTINUOUS   ) || \
+                                     ((OPERATION) == FDCAN_TIMEOUT_TX_EVENT_FIFO) || \
+                                     ((OPERATION) == FDCAN_TIMEOUT_RX_FIFO0     ) || \
+                                     ((OPERATION) == FDCAN_TIMEOUT_RX_FIFO1     ))
+#define IS_FDCAN_CALIBRATION_FIELD_LENGTH(LENGTH) (((LENGTH) == FDCAN_CALIB_FIELD_LENGTH_32) || \
+                                                   ((LENGTH) == FDCAN_CALIB_FIELD_LENGTH_64))
+#define IS_FDCAN_CALIBRATION_COUNTER(COUNTER) (((COUNTER) == FDCAN_CALIB_TIME_QUANTA_COUNTER ) || \
+                                               ((COUNTER) == FDCAN_CALIB_CLOCK_PERIOD_COUNTER) || \
+                                               ((COUNTER) == FDCAN_CALIB_WATCHDOG_COUNTER    ))
+#define IS_FDCAN_TT_REFERENCE_MESSAGE_PAYLOAD(PAYLOAD) (((PAYLOAD) == FDCAN_TT_REF_MESSAGE_NO_PAYLOAD ) || \
+                                                        ((PAYLOAD) == FDCAN_TT_REF_MESSAGE_ADD_PAYLOAD))
+#define IS_FDCAN_TT_REPEAT_FACTOR(FACTOR) (((FACTOR) == FDCAN_TT_REPEAT_EVERY_CYCLE     ) || \
+                                           ((FACTOR) == FDCAN_TT_REPEAT_EVERY_2ND_CYCLE ) || \
+                                           ((FACTOR) == FDCAN_TT_REPEAT_EVERY_4TH_CYCLE ) || \
+                                           ((FACTOR) == FDCAN_TT_REPEAT_EVERY_8TH_CYCLE ) || \
+                                           ((FACTOR) == FDCAN_TT_REPEAT_EVERY_16TH_CYCLE) || \
+                                           ((FACTOR) == FDCAN_TT_REPEAT_EVERY_32ND_CYCLE) || \
+                                           ((FACTOR) == FDCAN_TT_REPEAT_EVERY_64TH_CYCLE))
+#define IS_FDCAN_TT_TRIGGER_TYPE(TYPE) (((TYPE) == FDCAN_TT_TX_REF_TRIGGER        ) || \
+                                        ((TYPE) == FDCAN_TT_TX_REF_TRIGGER_GAP    ) || \
+                                        ((TYPE) == FDCAN_TT_TX_TRIGGER_SINGLE     ) || \
+                                        ((TYPE) == FDCAN_TT_TX_TRIGGER_CONTINUOUS ) || \
+                                        ((TYPE) == FDCAN_TT_TX_TRIGGER_ARBITRATION) || \
+                                        ((TYPE) == FDCAN_TT_TX_TRIGGER_MERGED     ) || \
+                                        ((TYPE) == FDCAN_TT_WATCH_TRIGGER         ) || \
+                                        ((TYPE) == FDCAN_TT_WATCH_TRIGGER_GAP     ) || \
+                                        ((TYPE) == FDCAN_TT_RX_TRIGGER            ) || \
+                                        ((TYPE) == FDCAN_TT_TIME_BASE_TRIGGER     ) || \
+                                        ((TYPE) == FDCAN_TT_END_OF_LIST           ))
+#define IS_FDCAN_TT_TM_EVENT_INTERNAL(EVENT) (((EVENT) == FDCAN_TT_TM_NO_INTERNAL_EVENT ) || \
+                                              ((EVENT) == FDCAN_TT_TM_GEN_INTERNAL_EVENT))
+#define IS_FDCAN_TT_TM_EVENT_EXTERNAL(EVENT) (((EVENT) == FDCAN_TT_TM_NO_EXTERNAL_EVENT ) || \
+                                              ((EVENT) == FDCAN_TT_TM_GEN_EXTERNAL_EVENT))
+#define IS_FDCAN_OPERATION_MODE(MODE) (((MODE) == FDCAN_TT_COMMUNICATION_LEVEL1 ) || \
+                                       ((MODE) == FDCAN_TT_COMMUNICATION_LEVEL2 ) || \
+                                       ((MODE) == FDCAN_TT_COMMUNICATION_LEVEL0 ))
+#define IS_FDCAN_TT_OPERATION(OPERATION) (((OPERATION) == FDCAN_STRICTLY_TT_OPERATION      ) || \
+                                          ((OPERATION) == FDCAN_EXT_EVT_SYNC_TT_OPERATION))
+#define IS_FDCAN_TT_TIME_MASTER(FUNCTION) (((FUNCTION) == FDCAN_TT_SLAVE           ) || \
+                                           ((FUNCTION) == FDCAN_TT_POTENTIAL_MASTER))
+#define IS_FDCAN_TT_EXTERNAL_CLK_SYNC(SYNC) (((SYNC) == FDCAN_TT_EXT_CLK_SYNC_DISABLE) || \
+                                             ((SYNC) == FDCAN_TT_EXT_CLK_SYNC_ENABLE ))
+#define IS_FDCAN_TT_GLOBAL_TIME_FILTERING(FILTERING) (((FILTERING) == FDCAN_TT_GLOB_TIME_FILT_DISABLE) || \
+                                                      ((FILTERING) == FDCAN_TT_GLOB_TIME_FILT_ENABLE ))
+#define IS_FDCAN_TT_AUTO_CLK_CALIBRATION(CALIBRATION) (((CALIBRATION) == FDCAN_TT_AUTO_CLK_CALIB_DISABLE) || \
+                                                       ((CALIBRATION) == FDCAN_TT_AUTO_CLK_CALIB_ENABLE ))
+#define IS_FDCAN_TT_EVENT_TRIGGER_POLARITY(POLARITY) (((POLARITY) == FDCAN_TT_EVT_TRIG_POL_RISING ) || \
+                                                      ((POLARITY) == FDCAN_TT_EVT_TRIG_POL_FALLING))
+#define IS_FDCAN_TT_BASIC_CYCLES_NUMBER(NUMBER) (((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_1 ) || \
+                                                 ((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_2 ) || \
+                                                 ((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_4 ) || \
+                                                 ((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_8 ) || \
+                                                 ((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_16) || \
+                                                 ((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_32) || \
+                                                 ((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_64))
+#define IS_FDCAN_TT_CYCLE_START_SYNC(SYNC) (((SYNC) == FDCAN_TT_NO_SYNC_PULSE         ) || \
+                                            ((SYNC) == FDCAN_TT_SYNC_BASIC_CYCLE_START) || \
+                                            ((SYNC) == FDCAN_TT_SYNC_MATRIX_START     ))
+#define IS_FDCAN_TT_TX_ENABLE_WINDOW(NTU) (((NTU) >= 1U) && ((NTU) <= 16U))
+#define IS_FDCAN_TT_TUR_NUMERATOR(NUMERATOR) (((NUMERATOR) >= 0x10000U) && ((NUMERATOR) <= 0x1FFFFU))
+#define IS_FDCAN_TT_TUR_DENOMINATOR(DENOMINATOR) (((DENOMINATOR) >= 0x0001U) && ((DENOMINATOR) <= 0x3FFFU))
+#define IS_FDCAN_TT_TUR_LEVEL_1(NC,DC) ((NC) >= (4U * (DC)))
+#define IS_FDCAN_TT_TUR_LEVEL_0_2(NC,DC) ((NC) >= (8U * (DC)))
+#define IS_FDCAN_TT_STOP_WATCH_TRIGGER(TRIGGER) (((TRIGGER) == FDCAN_TT_STOP_WATCH_TRIGGER_0) || \
+                                                 ((TRIGGER) == FDCAN_TT_STOP_WATCH_TRIGGER_1) || \
+                                                 ((TRIGGER) == FDCAN_TT_STOP_WATCH_TRIGGER_2) || \
+                                                 ((TRIGGER) == FDCAN_TT_STOP_WATCH_TRIGGER_3))
+#define IS_FDCAN_TT_EVENT_TRIGGER(TRIGGER) (((TRIGGER) == FDCAN_TT_EVENT_TRIGGER_0) || \
+                                            ((TRIGGER) == FDCAN_TT_EVENT_TRIGGER_1) || \
+                                            ((TRIGGER) == FDCAN_TT_EVENT_TRIGGER_2) || \
+                                            ((TRIGGER) == FDCAN_TT_EVENT_TRIGGER_3))
+#define IS_FDCAN_TT_TIME_PRESET(TIME) (((TIME) <= 0xFFFFU) && ((TIME) != 0x8000U))
+#define IS_FDCAN_TT_STOP_WATCH_SOURCE(SOURCE) (((SOURCE) == FDCAN_TT_STOP_WATCH_DISABLED   ) || \
+                                               ((SOURCE) == FDCAN_TT_STOP_WATCH_CYCLE_TIME ) || \
+                                               ((SOURCE) == FDCAN_TT_STOP_WATCH_LOCAL_TIME ) || \
+                                               ((SOURCE) == FDCAN_TT_STOP_WATCH_GLOBAL_TIME))
+#define IS_FDCAN_TT_STOP_WATCH_POLARITY(POLARITY) (((POLARITY) == FDCAN_TT_STOP_WATCH_RISING ) || \
+                                                   ((POLARITY) == FDCAN_TT_STOP_WATCH_FALLING))
+#define IS_FDCAN_TT_REGISTER_TIME_MARK_SOURCE(SOURCE) (((SOURCE) == FDCAN_TT_REG_TIMEMARK_DIABLED ) || \
+                                                       ((SOURCE) == FDCAN_TT_REG_TIMEMARK_CYC_TIME) || \
+                                                       ((SOURCE) == FDCAN_TT_REG_TIMEMARK_LOC_TIME) || \
+                                                       ((SOURCE) == FDCAN_TT_REG_TIMEMARK_GLO_TIME))
+
+#define FDCAN_CHECK_IT_SOURCE(__IE__, __IT__)  ((((__IE__) & (__IT__)) == (__IT__)) ? SET : RESET)
+
+#define FDCAN_CHECK_FLAG(__IR__, __FLAG__) ((((__IR__) & (__FLAG__)) == (__FLAG__)) ? SET : RESET)
+/**
+  * @}
+  */
+
+/* Private functions prototypes ----------------------------------------------*/
+/** @defgroup FDCAN_Private_Functions_Prototypes FDCAN Private Functions Prototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup FDCAN_Private_Functions FDCAN Private Functions
+  * @{
+  */
+
+/**
+  * @}
+  */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+#endif /* FDCAN1 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32H7xx_HAL_FDCAN_H */
+
+
diff --git a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h
new file mode 100644
index 0000000..83fa74f
--- /dev/null
+++ b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h
@@ -0,0 +1,800 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_sd.h
+  * @author  MCD Application Team
+  * @brief   Header file of SD HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_HAL_SD_H
+#define STM32H7xx_HAL_SD_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_ll_sdmmc.h"
+#if defined (DLYB_SDMMC1) || defined (DLYB_SDMMC2) || defined (DLYB_SDMMC3)
+#include "stm32h7xx_ll_delayblock.h"
+#endif /* (DLYB_SDMMC1) || (DLYB_SDMMC2) */
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup SD SD
+  * @brief SD HAL module driver
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup SD_Exported_Types SD Exported Types
+  * @{
+  */
+
+/** @defgroup SD_Exported_Types_Group1 SD State enumeration structure
+  * @{
+  */
+typedef enum
+{
+  HAL_SD_STATE_RESET                  = ((uint32_t)0x00000000U),  /*!< SD not yet initialized or disabled  */
+  HAL_SD_STATE_READY                  = ((uint32_t)0x00000001U),  /*!< SD initialized and ready for use    */
+  HAL_SD_STATE_TIMEOUT                = ((uint32_t)0x00000002U),  /*!< SD Timeout state                    */
+  HAL_SD_STATE_BUSY                   = ((uint32_t)0x00000003U),  /*!< SD process ongoing                  */
+  HAL_SD_STATE_PROGRAMMING            = ((uint32_t)0x00000004U),  /*!< SD Programming State                */
+  HAL_SD_STATE_RECEIVING              = ((uint32_t)0x00000005U),  /*!< SD Receiving State                  */
+  HAL_SD_STATE_TRANSFER               = ((uint32_t)0x00000006U),  /*!< SD Transfer State                   */
+  HAL_SD_STATE_ERROR                  = ((uint32_t)0x0000000FU)   /*!< SD is in error state                */
+} HAL_SD_StateTypeDef;
+/**
+  * @}
+  */
+
+/** @defgroup SD_Exported_Types_Group2 SD Card State enumeration structure
+  * @{
+  */
+typedef uint32_t HAL_SD_CardStateTypeDef;
+
+#define HAL_SD_CARD_READY          0x00000001U  /*!< Card state is ready                     */
+#define HAL_SD_CARD_IDENTIFICATION 0x00000002U  /*!< Card is in identification state         */
+#define HAL_SD_CARD_STANDBY        0x00000003U  /*!< Card is in standby state                */
+#define HAL_SD_CARD_TRANSFER       0x00000004U  /*!< Card is in transfer state               */
+#define HAL_SD_CARD_SENDING        0x00000005U  /*!< Card is sending an operation            */
+#define HAL_SD_CARD_RECEIVING      0x00000006U  /*!< Card is receiving operation information */
+#define HAL_SD_CARD_PROGRAMMING    0x00000007U  /*!< Card is in programming state            */
+#define HAL_SD_CARD_DISCONNECTED   0x00000008U  /*!< Card is disconnected                    */
+#define HAL_SD_CARD_ERROR          0x000000FFU  /*!< Card response Error                     */
+/**
+  * @}
+  */
+
+/** @defgroup SD_Exported_Types_Group3 SD Handle Structure definition
+  * @{
+  */
+#define SD_InitTypeDef      SDMMC_InitTypeDef
+#define SD_TypeDef          SDMMC_TypeDef
+
+/**
+  * @brief  SD Card Information Structure definition
+  */
+typedef struct
+{
+  uint32_t CardType;                     /*!< Specifies the card Type                         */
+
+  uint32_t CardVersion;                  /*!< Specifies the card version                      */
+
+  uint32_t Class;                        /*!< Specifies the class of the card class           */
+
+  uint32_t RelCardAdd;                   /*!< Specifies the Relative Card Address             */
+
+  uint32_t BlockNbr;                     /*!< Specifies the Card Capacity in blocks           */
+
+  uint32_t BlockSize;                    /*!< Specifies one block size in bytes               */
+
+  uint32_t LogBlockNbr;                  /*!< Specifies the Card logical Capacity in blocks   */
+
+  uint32_t LogBlockSize;                 /*!< Specifies logical block size in bytes           */
+
+  uint32_t CardSpeed;                    /*!< Specifies the card Speed                        */
+
+} HAL_SD_CardInfoTypeDef;
+
+/**
+  * @brief  SD handle Structure definition
+  */
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+typedef struct __SD_HandleTypeDef
+#else
+typedef struct
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+{
+  SD_TypeDef                   *Instance;        /*!< SD registers base address           */
+
+  SD_InitTypeDef               Init;             /*!< SD required parameters              */
+
+  HAL_LockTypeDef              Lock;             /*!< SD locking object                   */
+
+  const uint8_t                *pTxBuffPtr;      /*!< Pointer to SD Tx transfer Buffer    */
+
+  uint32_t                     TxXferSize;       /*!< SD Tx Transfer size                 */
+
+  uint8_t                      *pRxBuffPtr;      /*!< Pointer to SD Rx transfer Buffer    */
+
+  uint32_t                     RxXferSize;       /*!< SD Rx Transfer size                 */
+
+  __IO uint32_t                Context;          /*!< SD transfer context                 */
+
+  __IO HAL_SD_StateTypeDef     State;            /*!< SD card State                       */
+
+  __IO uint32_t                ErrorCode;        /*!< SD Card Error codes                 */
+
+  HAL_SD_CardInfoTypeDef       SdCard;           /*!< SD Card information                 */
+
+  uint32_t                     CSD[4];           /*!< SD card specific data table         */
+
+  uint32_t                     CID[4];           /*!< SD card identification number table */
+
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+  void (* TxCpltCallback)(struct __SD_HandleTypeDef *hsd);
+  void (* RxCpltCallback)(struct __SD_HandleTypeDef *hsd);
+  void (* ErrorCallback)(struct __SD_HandleTypeDef *hsd);
+  void (* AbortCpltCallback)(struct __SD_HandleTypeDef *hsd);
+  void (* Read_DMADblBuf0CpltCallback)(struct __SD_HandleTypeDef *hsd);
+  void (* Read_DMADblBuf1CpltCallback)(struct __SD_HandleTypeDef *hsd);
+  void (* Write_DMADblBuf0CpltCallback)(struct __SD_HandleTypeDef *hsd);
+  void (* Write_DMADblBuf1CpltCallback)(struct __SD_HandleTypeDef *hsd);
+#if (USE_SD_TRANSCEIVER != 0U)
+  void (* DriveTransceiver_1_8V_Callback)(FlagStatus status);
+#endif /* USE_SD_TRANSCEIVER */
+
+  void (* MspInitCallback)(struct __SD_HandleTypeDef *hsd);
+  void (* MspDeInitCallback)(struct __SD_HandleTypeDef *hsd);
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+} SD_HandleTypeDef;
+
+/**
+  * @}
+  */
+
+/** @defgroup SD_Exported_Types_Group4 Card Specific Data: CSD Register
+  * @{
+  */
+typedef struct
+{
+  __IO uint8_t  CSDStruct;            /*!< CSD structure                         */
+  __IO uint8_t  SysSpecVersion;       /*!< System specification version          */
+  __IO uint8_t  Reserved1;            /*!< Reserved                              */
+  __IO uint8_t  TAAC;                 /*!< Data read access time 1               */
+  __IO uint8_t  NSAC;                 /*!< Data read access time 2 in CLK cycles */
+  __IO uint8_t  MaxBusClkFrec;        /*!< Max. bus clock frequency              */
+  __IO uint16_t CardComdClasses;      /*!< Card command classes                  */
+  __IO uint8_t  RdBlockLen;           /*!< Max. read data block length           */
+  __IO uint8_t  PartBlockRead;        /*!< Partial blocks for read allowed       */
+  __IO uint8_t  WrBlockMisalign;      /*!< Write block misalignment              */
+  __IO uint8_t  RdBlockMisalign;      /*!< Read block misalignment               */
+  __IO uint8_t  DSRImpl;              /*!< DSR implemented                       */
+  __IO uint8_t  Reserved2;            /*!< Reserved                              */
+  __IO uint32_t DeviceSize;           /*!< Device Size                           */
+  __IO uint8_t  MaxRdCurrentVDDMin;   /*!< Max. read current @ VDD min           */
+  __IO uint8_t  MaxRdCurrentVDDMax;   /*!< Max. read current @ VDD max           */
+  __IO uint8_t  MaxWrCurrentVDDMin;   /*!< Max. write current @ VDD min          */
+  __IO uint8_t  MaxWrCurrentVDDMax;   /*!< Max. write current @ VDD max          */
+  __IO uint8_t  DeviceSizeMul;        /*!< Device size multiplier                */
+  __IO uint8_t  EraseGrSize;          /*!< Erase group size                      */
+  __IO uint8_t  EraseGrMul;           /*!< Erase group size multiplier           */
+  __IO uint8_t  WrProtectGrSize;      /*!< Write protect group size              */
+  __IO uint8_t  WrProtectGrEnable;    /*!< Write protect group enable            */
+  __IO uint8_t  ManDeflECC;           /*!< Manufacturer default ECC              */
+  __IO uint8_t  WrSpeedFact;          /*!< Write speed factor                    */
+  __IO uint8_t  MaxWrBlockLen;        /*!< Max. write data block length          */
+  __IO uint8_t  WriteBlockPaPartial;  /*!< Partial blocks for write allowed      */
+  __IO uint8_t  Reserved3;            /*!< Reserved                              */
+  __IO uint8_t  ContentProtectAppli;  /*!< Content protection application        */
+  __IO uint8_t  FileFormatGroup;      /*!< File format group                     */
+  __IO uint8_t  CopyFlag;             /*!< Copy flag (OTP)                       */
+  __IO uint8_t  PermWrProtect;        /*!< Permanent write protection            */
+  __IO uint8_t  TempWrProtect;        /*!< Temporary write protection            */
+  __IO uint8_t  FileFormat;           /*!< File format                           */
+  __IO uint8_t  ECC;                  /*!< ECC code                              */
+  __IO uint8_t  CSD_CRC;              /*!< CSD CRC                               */
+  __IO uint8_t  Reserved4;            /*!< Always 1                              */
+} HAL_SD_CardCSDTypeDef;
+/**
+  * @}
+  */
+
+/** @defgroup SD_Exported_Types_Group5 Card Identification Data: CID Register
+  * @{
+  */
+typedef struct
+{
+  __IO uint8_t  ManufacturerID;  /*!< Manufacturer ID       */
+  __IO uint16_t OEM_AppliID;     /*!< OEM/Application ID    */
+  __IO uint32_t ProdName1;       /*!< Product Name part1    */
+  __IO uint8_t  ProdName2;       /*!< Product Name part2    */
+  __IO uint8_t  ProdRev;         /*!< Product Revision      */
+  __IO uint32_t ProdSN;          /*!< Product Serial Number */
+  __IO uint8_t  Reserved1;       /*!< Reserved1             */
+  __IO uint16_t ManufactDate;    /*!< Manufacturing Date    */
+  __IO uint8_t  CID_CRC;         /*!< CID CRC               */
+  __IO uint8_t  Reserved2;       /*!< Always 1              */
+
+} HAL_SD_CardCIDTypeDef;
+/**
+  * @}
+  */
+
+/** @defgroup SD_Exported_Types_Group6 SD Card Status returned by ACMD13
+  * @{
+  */
+typedef struct
+{
+  __IO uint8_t  DataBusWidth;           /*!< Shows the currently defined data bus width                 */
+  __IO uint8_t  SecuredMode;            /*!< Card is in secured mode of operation                       */
+  __IO uint16_t CardType;               /*!< Carries information about card type                        */
+  __IO uint32_t ProtectedAreaSize;      /*!< Carries information about the capacity of protected area   */
+  __IO uint8_t  SpeedClass;             /*!< Carries information about the speed class of the card      */
+  __IO uint8_t  PerformanceMove;        /*!< Carries information about the card's performance move      */
+  __IO uint8_t  AllocationUnitSize;     /*!< Carries information about the card's allocation unit size  */
+  __IO uint16_t EraseSize;              /*!< Determines the number of AUs to be erased in one operation */
+  __IO uint8_t  EraseTimeout;           /*!< Determines the timeout for any number of AU erase          */
+  __IO uint8_t  EraseOffset;            /*!< Carries information about the erase offset                 */
+  __IO uint8_t  UhsSpeedGrade;          /*!< Carries information about the speed grade of UHS card      */
+  __IO uint8_t  UhsAllocationUnitSize;  /*!< Carries information about the UHS card's allocation unit size  */
+  __IO uint8_t  VideoSpeedClass;        /*!< Carries information about the Video Speed Class of UHS card    */
+} HAL_SD_CardStatusTypeDef;
+/**
+  * @}
+  */
+
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+/** @defgroup SD_Exported_Types_Group7 SD Callback ID enumeration definition
+  * @{
+  */
+typedef enum
+{
+  HAL_SD_TX_CPLT_CB_ID                 = 0x00U,  /*!< SD Tx Complete Callback ID                     */
+  HAL_SD_RX_CPLT_CB_ID                 = 0x01U,  /*!< SD Rx Complete Callback ID                     */
+  HAL_SD_ERROR_CB_ID                   = 0x02U,  /*!< SD Error Callback ID                           */
+  HAL_SD_ABORT_CB_ID                   = 0x03U,  /*!< SD Abort Callback ID                           */
+  HAL_SD_READ_DMA_DBL_BUF0_CPLT_CB_ID  = 0x04U,  /*!< SD Rx DMA Double Buffer 0 Complete Callback ID */
+  HAL_SD_READ_DMA_DBL_BUF1_CPLT_CB_ID  = 0x05U,  /*!< SD Rx DMA Double Buffer 1 Complete Callback ID */
+  HAL_SD_WRITE_DMA_DBL_BUF0_CPLT_CB_ID = 0x06U,  /*!< SD Tx DMA Double Buffer 0 Complete Callback ID */
+  HAL_SD_WRITE_DMA_DBL_BUF1_CPLT_CB_ID = 0x07U,  /*!< SD Tx DMA Double Buffer 1 Complete Callback ID */
+
+  HAL_SD_MSP_INIT_CB_ID                = 0x10U,  /*!< SD MspInit Callback ID                         */
+  HAL_SD_MSP_DEINIT_CB_ID              = 0x11U   /*!< SD MspDeInit Callback ID                       */
+} HAL_SD_CallbackIDTypeDef;
+/**
+  * @}
+  */
+
+/** @defgroup SD_Exported_Types_Group8 SD Callback pointer definition
+  * @{
+  */
+typedef void (*pSD_CallbackTypeDef)(SD_HandleTypeDef *hsd);
+#if (USE_SD_TRANSCEIVER != 0U)
+typedef void (*pSD_TransceiverCallbackTypeDef)(FlagStatus status);
+#endif /* USE_SD_TRANSCEIVER */
+/**
+  * @}
+  */
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup SD_Exported_Constants SD Exported Constants
+  * @{
+  */
+
+#define BLOCKSIZE   ((uint32_t)512U) /*!< Block size is 512 bytes */
+
+/** @defgroup SD_Exported_Constansts_Group1 SD Error status enumeration Structure definition
+  * @{
+  */
+#define HAL_SD_ERROR_NONE                     SDMMC_ERROR_NONE                        /*!< No error                                                     */
+#define HAL_SD_ERROR_CMD_CRC_FAIL             SDMMC_ERROR_CMD_CRC_FAIL                /*!< Command response received (but CRC check failed)             */
+#define HAL_SD_ERROR_DATA_CRC_FAIL            SDMMC_ERROR_DATA_CRC_FAIL               /*!< Data block sent/received (CRC check failed)                  */
+#define HAL_SD_ERROR_CMD_RSP_TIMEOUT          SDMMC_ERROR_CMD_RSP_TIMEOUT             /*!< Command response timeout                                     */
+#define HAL_SD_ERROR_DATA_TIMEOUT             SDMMC_ERROR_DATA_TIMEOUT                /*!< Data timeout                                                 */
+#define HAL_SD_ERROR_TX_UNDERRUN              SDMMC_ERROR_TX_UNDERRUN                 /*!< Transmit FIFO underrun                                       */
+#define HAL_SD_ERROR_RX_OVERRUN               SDMMC_ERROR_RX_OVERRUN                  /*!< Receive FIFO overrun                                         */
+#define HAL_SD_ERROR_ADDR_MISALIGNED          SDMMC_ERROR_ADDR_MISALIGNED             /*!< Misaligned address                                           */
+#define HAL_SD_ERROR_BLOCK_LEN_ERR            SDMMC_ERROR_BLOCK_LEN_ERR               /*!< Transferred block length is not allowed for the card or the  */
+                                                                                      /*!< number of transferred bytes does not match the block length  */
+#define HAL_SD_ERROR_ERASE_SEQ_ERR            SDMMC_ERROR_ERASE_SEQ_ERR               /*!< An error in the sequence of erase command occurs             */
+#define HAL_SD_ERROR_BAD_ERASE_PARAM          SDMMC_ERROR_BAD_ERASE_PARAM             /*!< An invalid selection for erase groups                        */
+#define HAL_SD_ERROR_WRITE_PROT_VIOLATION     SDMMC_ERROR_WRITE_PROT_VIOLATION        /*!< Attempt to program a write protect block                     */
+#define HAL_SD_ERROR_LOCK_UNLOCK_FAILED       SDMMC_ERROR_LOCK_UNLOCK_FAILED          /*!< Sequence or password error has been detected in unlock       */
+                                                                                      /*!< command or if there was an attempt to access a locked card   */
+#define HAL_SD_ERROR_COM_CRC_FAILED           SDMMC_ERROR_COM_CRC_FAILED              /*!< CRC check of the previous command failed                     */
+#define HAL_SD_ERROR_ILLEGAL_CMD              SDMMC_ERROR_ILLEGAL_CMD                 /*!< Command is not legal for the card state                      */
+#define HAL_SD_ERROR_CARD_ECC_FAILED          SDMMC_ERROR_CARD_ECC_FAILED             /*!< Card internal ECC was applied but failed to correct the data */
+#define HAL_SD_ERROR_CC_ERR                   SDMMC_ERROR_CC_ERR                      /*!< Internal card controller error                               */
+#define HAL_SD_ERROR_GENERAL_UNKNOWN_ERR      SDMMC_ERROR_GENERAL_UNKNOWN_ERR         /*!< General or unknown error                                     */
+#define HAL_SD_ERROR_STREAM_READ_UNDERRUN     SDMMC_ERROR_STREAM_READ_UNDERRUN        /*!< The card could not sustain data reading in stream rmode      */
+#define HAL_SD_ERROR_STREAM_WRITE_OVERRUN     SDMMC_ERROR_STREAM_WRITE_OVERRUN        /*!< The card could not sustain data programming in stream mode   */
+#define HAL_SD_ERROR_CID_CSD_OVERWRITE        SDMMC_ERROR_CID_CSD_OVERWRITE           /*!< CID/CSD overwrite error                                      */
+#define HAL_SD_ERROR_WP_ERASE_SKIP            SDMMC_ERROR_WP_ERASE_SKIP               /*!< Only partial address space was erased                        */
+#define HAL_SD_ERROR_CARD_ECC_DISABLED        SDMMC_ERROR_CARD_ECC_DISABLED           /*!< Command has been executed without using internal ECC         */
+#define HAL_SD_ERROR_ERASE_RESET              SDMMC_ERROR_ERASE_RESET                 /*!< Erase sequence was cleared before executing because an out   */
+                                                                                      /*!< of erase sequence command was received                       */
+#define HAL_SD_ERROR_AKE_SEQ_ERR              SDMMC_ERROR_AKE_SEQ_ERR                 /*!< Error in sequence of authentication                          */
+#define HAL_SD_ERROR_INVALID_VOLTRANGE        SDMMC_ERROR_INVALID_VOLTRANGE           /*!< Error in case of invalid voltage range                       */
+#define HAL_SD_ERROR_ADDR_OUT_OF_RANGE        SDMMC_ERROR_ADDR_OUT_OF_RANGE           /*!< Error when addressed block is out of range                   */
+#define HAL_SD_ERROR_REQUEST_NOT_APPLICABLE   SDMMC_ERROR_REQUEST_NOT_APPLICABLE      /*!< Error when command request is not applicable                 */
+#define HAL_SD_ERROR_PARAM                    SDMMC_ERROR_INVALID_PARAMETER           /*!< the used parameter is not valid                              */
+#define HAL_SD_ERROR_UNSUPPORTED_FEATURE      SDMMC_ERROR_UNSUPPORTED_FEATURE         /*!< Error when feature is not insupported                        */
+#define HAL_SD_ERROR_BUSY                     SDMMC_ERROR_BUSY                        /*!< Error when transfer process is busy                          */
+#define HAL_SD_ERROR_DMA                      SDMMC_ERROR_DMA                         /*!< Error while DMA transfer                                     */
+#define HAL_SD_ERROR_TIMEOUT                  SDMMC_ERROR_TIMEOUT                     /*!< Timeout error                                                */
+
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+#define HAL_SD_ERROR_INVALID_CALLBACK         SDMMC_ERROR_INVALID_PARAMETER       /*!< Invalid callback error                                        */
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
+
+/** @defgroup SD_Exported_Constansts_Group2 SD context enumeration
+  * @{
+  */
+#define   SD_CONTEXT_NONE                 ((uint32_t)0x00000000U)  /*!< None                             */
+#define   SD_CONTEXT_READ_SINGLE_BLOCK    ((uint32_t)0x00000001U)  /*!< Read single block operation      */
+#define   SD_CONTEXT_READ_MULTIPLE_BLOCK  ((uint32_t)0x00000002U)  /*!< Read multiple blocks operation   */
+#define   SD_CONTEXT_WRITE_SINGLE_BLOCK   ((uint32_t)0x00000010U)  /*!< Write single block operation     */
+#define   SD_CONTEXT_WRITE_MULTIPLE_BLOCK ((uint32_t)0x00000020U)  /*!< Write multiple blocks operation  */
+#define   SD_CONTEXT_IT                   ((uint32_t)0x00000008U)  /*!< Process in Interrupt mode        */
+#define   SD_CONTEXT_DMA                  ((uint32_t)0x00000080U)  /*!< Process in DMA mode              */
+
+/**
+  * @}
+  */
+
+/** @defgroup SD_Exported_Constansts_Group3 SD Supported Memory Cards
+  * @{
+  */
+#define CARD_NORMAL_SPEED        ((uint32_t)0x00000000U)    /*!< Normal Speed Card <12.5Mo/s , Spec Version 1.01    */
+#define CARD_HIGH_SPEED          ((uint32_t)0x00000100U)    /*!< High Speed Card <25Mo/s , Spec version 2.00        */
+#define CARD_ULTRA_HIGH_SPEED    ((uint32_t)0x00000200U)    /*!< UHS-I SD Card <50Mo/s for SDR50, DDR5 Cards
+                                                                 and <104Mo/s for SDR104, Spec version 3.01          */
+
+#define CARD_SDSC                  ((uint32_t)0x00000000U)  /*!< SD Standard Capacity <2Go                          */
+#define CARD_SDHC_SDXC             ((uint32_t)0x00000001U)  /*!< SD High Capacity <32Go, SD Extended Capacity <2To  */
+#define CARD_SECURED               ((uint32_t)0x00000003U)
+
+/**
+  * @}
+  */
+
+/** @defgroup SD_Exported_Constansts_Group4 SD Supported Version
+  * @{
+  */
+#define CARD_V1_X                  ((uint32_t)0x00000000U)
+#define CARD_V2_X                  ((uint32_t)0x00000001U)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup SD_Exported_macros SD Exported Macros
+  *  @brief macros to handle interrupts and specific clock configurations
+  * @{
+  */
+/** @brief Reset SD handle state.
+  * @param  __HANDLE__ SD Handle.
+  * @retval None
+  */
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+#define __HAL_SD_RESET_HANDLE_STATE(__HANDLE__)           do {                                              \
+                                                               (__HANDLE__)->State = HAL_SD_STATE_RESET; \
+                                                               (__HANDLE__)->MspInitCallback = NULL;       \
+                                                               (__HANDLE__)->MspDeInitCallback = NULL;     \
+                                                             } while(0)
+#else
+#define __HAL_SD_RESET_HANDLE_STATE(__HANDLE__)           ((__HANDLE__)->State = HAL_SD_STATE_RESET)
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+
+/**
+  * @brief  Enable the SD device interrupt.
+  * @param  __HANDLE__ SD Handle.
+  * @param  __INTERRUPT__ specifies the SDMMC interrupt sources to be enabled.
+  *         This parameter can be one or a combination of the following values:
+  *            @arg SDMMC_IT_CCRCFAIL:   Command response received (CRC check failed) interrupt
+  *            @arg SDMMC_IT_DCRCFAIL:   Data block sent/received (CRC check failed) interrupt
+  *            @arg SDMMC_IT_CTIMEOUT:   Command response timeout interrupt
+  *            @arg SDMMC_IT_DTIMEOUT:   Data timeout interrupt
+  *            @arg SDMMC_IT_TXUNDERR:   Transmit FIFO underrun error interrupt
+  *            @arg SDMMC_IT_RXOVERR:    Received FIFO overrun error interrupt
+  *            @arg SDMMC_IT_CMDREND:    Command response received (CRC check passed) interrupt
+  *            @arg SDMMC_IT_CMDSENT:    Command sent (no response required) interrupt
+  *            @arg SDMMC_IT_DATAEND:    Data end (data counter, DATACOUNT, is zero) interrupt
+  *            @arg SDMMC_IT_DHOLD:      Data transfer Hold interrupt
+  *            @arg SDMMC_IT_DBCKEND:    Data block sent/received (CRC check passed) interrupt
+  *            @arg SDMMC_IT_DABORT:     Data transfer aborted by CMD12 interrupt
+  *            @arg SDMMC_IT_TXFIFOHE:   Transmit FIFO Half Empty interrupt
+  *            @arg SDMMC_IT_RXFIFOHF:   Receive FIFO Half Full interrupt
+  *            @arg SDMMC_IT_RXFIFOF:    Receive FIFO full interrupt
+  *            @arg SDMMC_IT_TXFIFOE:    Transmit FIFO empty interrupt
+  *            @arg SDMMC_IT_BUSYD0END:  End of SDMMC_D0 Busy following a CMD response detected interrupt
+  *            @arg SDMMC_IT_SDIOIT:     SDIO interrupt received interrupt
+  *            @arg SDMMC_IT_ACKFAIL:    Boot Acknowledgment received interrupt
+  *            @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt
+  *            @arg SDMMC_IT_VSWEND:     Voltage switch critical timing section completion interrupt
+  *            @arg SDMMC_IT_CKSTOP:     SDMMC_CK stopped in Voltage switch procedure interrupt
+  *            @arg SDMMC_IT_IDMABTC:    IDMA buffer transfer complete interrupt
+  * @retval None
+  */
+#define __HAL_SD_ENABLE_IT(__HANDLE__, __INTERRUPT__) __SDMMC_ENABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
+
+/**
+  * @brief  Disable the SD device interrupt.
+  * @param  __HANDLE__ SD Handle.
+  * @param  __INTERRUPT__ specifies the SDMMC interrupt sources to be disabled.
+  *          This parameter can be one or a combination of the following values:
+  *            @arg SDMMC_IT_CCRCFAIL:   Command response received (CRC check failed) interrupt
+  *            @arg SDMMC_IT_DCRCFAIL:   Data block sent/received (CRC check failed) interrupt
+  *            @arg SDMMC_IT_CTIMEOUT:   Command response timeout interrupt
+  *            @arg SDMMC_IT_DTIMEOUT:   Data timeout interrupt
+  *            @arg SDMMC_IT_TXUNDERR:   Transmit FIFO underrun error interrupt
+  *            @arg SDMMC_IT_RXOVERR:    Received FIFO overrun error interrupt
+  *            @arg SDMMC_IT_CMDREND:    Command response received (CRC check passed) interrupt
+  *            @arg SDMMC_IT_CMDSENT:    Command sent (no response required) interrupt
+  *            @arg SDMMC_IT_DATAEND:    Data end (data counter, DATACOUNT, is zero) interrupt
+  *            @arg SDMMC_IT_DHOLD:      Data transfer Hold interrupt
+  *            @arg SDMMC_IT_DBCKEND:    Data block sent/received (CRC check passed) interrupt
+  *            @arg SDMMC_IT_DABORT:     Data transfer aborted by CMD12 interrupt
+  *            @arg SDMMC_IT_TXFIFOHE:   Transmit FIFO Half Empty interrupt
+  *            @arg SDMMC_IT_RXFIFOHF:   Receive FIFO Half Full interrupt
+  *            @arg SDMMC_IT_RXFIFOF:    Receive FIFO full interrupt
+  *            @arg SDMMC_IT_TXFIFOE:    Transmit FIFO empty interrupt
+  *            @arg SDMMC_IT_BUSYD0END:  End of SDMMC_D0 Busy following a CMD response detected interrupt
+  *            @arg SDMMC_IT_SDIOIT:     SDIO interrupt received interrupt
+  *            @arg SDMMC_IT_ACKFAIL:    Boot Acknowledgment received interrupt
+  *            @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt
+  *            @arg SDMMC_IT_VSWEND:     Voltage switch critical timing section completion interrupt
+  *            @arg SDMMC_IT_CKSTOP:     SDMMC_CK stopped in Voltage switch procedure interrupt
+  *            @arg SDMMC_IT_IDMABTC:    IDMA buffer transfer complete interrupt
+  * @retval None
+  */
+#define __HAL_SD_DISABLE_IT(__HANDLE__, __INTERRUPT__) __SDMMC_DISABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
+
+/**
+  * @brief  Check whether the specified SD flag is set or not.
+  * @param  __HANDLE__ SD Handle.
+  * @param  __FLAG__ specifies the flag to check.
+  *          This parameter can be one of the following values:
+  *            @arg SDMMC_FLAG_CCRCFAIL:   Command response received (CRC check failed)
+  *            @arg SDMMC_FLAG_DCRCFAIL:   Data block sent/received (CRC check failed)
+  *            @arg SDMMC_FLAG_CTIMEOUT:   Command response timeout
+  *            @arg SDMMC_FLAG_DTIMEOUT:   Data timeout
+  *            @arg SDMMC_FLAG_TXUNDERR:   Transmit FIFO underrun error
+  *            @arg SDMMC_FLAG_RXOVERR:    Received FIFO overrun error
+  *            @arg SDMMC_FLAG_CMDREND:    Command response received (CRC check passed)
+  *            @arg SDMMC_FLAG_CMDSENT:    Command sent (no response required)
+  *            @arg SDMMC_FLAG_DATAEND:    Data end (data counter, DATACOUNT, is zero)
+  *            @arg SDMMC_FLAG_DHOLD:      Data transfer Hold
+  *            @arg SDMMC_FLAG_DBCKEND:    Data block sent/received (CRC check passed)
+  *            @arg SDMMC_FLAG_DABORT:     Data transfer aborted by CMD12
+  *            @arg SDMMC_FLAG_DPSMACT:    Data path state machine active
+  *            @arg SDMMC_FLAG_CPSMACT:    Command path state machine active
+  *            @arg SDMMC_FLAG_TXFIFOHE:   Transmit FIFO Half Empty
+  *            @arg SDMMC_FLAG_RXFIFOHF:   Receive FIFO Half Full
+  *            @arg SDMMC_FLAG_TXFIFOF:    Transmit FIFO full
+  *            @arg SDMMC_FLAG_RXFIFOF:    Receive FIFO full
+  *            @arg SDMMC_FLAG_TXFIFOE:    Transmit FIFO empty
+  *            @arg SDMMC_FLAG_RXFIFOE:    Receive FIFO empty
+  *            @arg SDMMC_FLAG_BUSYD0:     Inverted value of SDMMC_D0 line (Busy)
+  *            @arg SDMMC_FLAG_BUSYD0END:  End of SDMMC_D0 Busy following a CMD response detected
+  *            @arg SDMMC_FLAG_SDIOIT:     SDIO interrupt received
+  *            @arg SDMMC_FLAG_ACKFAIL:    Boot Acknowledgment received
+  *            @arg SDMMC_FLAG_ACKTIMEOUT: Boot Acknowledgment timeout
+  *            @arg SDMMC_FLAG_VSWEND:     Voltage switch critical timing section completion
+  *            @arg SDMMC_FLAG_CKSTOP:     SDMMC_CK stopped in Voltage switch procedure
+  *            @arg SDMMC_FLAG_IDMATE:     IDMA transfer error
+  *            @arg SDMMC_FLAG_IDMABTC:    IDMA buffer transfer complete
+  * @retval The new state of SD FLAG (SET or RESET).
+  */
+#define __HAL_SD_GET_FLAG(__HANDLE__, __FLAG__) __SDMMC_GET_FLAG((__HANDLE__)->Instance, (__FLAG__))
+
+/**
+  * @brief  Clear the SD's pending flags.
+  * @param  __HANDLE__ SD Handle.
+  * @param  __FLAG__ specifies the flag to clear.
+  *          This parameter can be one or a combination of the following values:
+  *            @arg SDMMC_FLAG_CCRCFAIL:   Command response received (CRC check failed)
+  *            @arg SDMMC_FLAG_DCRCFAIL:   Data block sent/received (CRC check failed)
+  *            @arg SDMMC_FLAG_CTIMEOUT:   Command response timeout
+  *            @arg SDMMC_FLAG_DTIMEOUT:   Data timeout
+  *            @arg SDMMC_FLAG_TXUNDERR:   Transmit FIFO underrun error
+  *            @arg SDMMC_FLAG_RXOVERR:    Received FIFO overrun error
+  *            @arg SDMMC_FLAG_CMDREND:    Command response received (CRC check passed)
+  *            @arg SDMMC_FLAG_CMDSENT:    Command sent (no response required)
+  *            @arg SDMMC_FLAG_DATAEND:    Data end (data counter, DATACOUNT, is zero)
+  *            @arg SDMMC_FLAG_DHOLD:      Data transfer Hold
+  *            @arg SDMMC_FLAG_DBCKEND:    Data block sent/received (CRC check passed)
+  *            @arg SDMMC_FLAG_DABORT:     Data transfer aborted by CMD12
+  *            @arg SDMMC_FLAG_BUSYD0END:  End of SDMMC_D0 Busy following a CMD response detected
+  *            @arg SDMMC_FLAG_SDIOIT:     SDIO interrupt received
+  *            @arg SDMMC_FLAG_ACKFAIL:    Boot Acknowledgment received
+  *            @arg SDMMC_FLAG_ACKTIMEOUT: Boot Acknowledgment timeout
+  *            @arg SDMMC_FLAG_VSWEND:     Voltage switch critical timing section completion
+  *            @arg SDMMC_FLAG_CKSTOP:     SDMMC_CK stopped in Voltage switch procedure
+  *            @arg SDMMC_FLAG_IDMATE:     IDMA transfer error
+  *            @arg SDMMC_FLAG_IDMABTC:    IDMA buffer transfer complete
+  * @retval None
+  */
+#define __HAL_SD_CLEAR_FLAG(__HANDLE__, __FLAG__) __SDMMC_CLEAR_FLAG((__HANDLE__)->Instance, (__FLAG__))
+
+/**
+  * @brief  Check whether the specified SD interrupt has occurred or not.
+  * @param  __HANDLE__ SD Handle.
+  * @param  __INTERRUPT__ specifies the SDMMC interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg SDMMC_IT_CCRCFAIL:   Command response received (CRC check failed) interrupt
+  *            @arg SDMMC_IT_DCRCFAIL:   Data block sent/received (CRC check failed) interrupt
+  *            @arg SDMMC_IT_CTIMEOUT:   Command response timeout interrupt
+  *            @arg SDMMC_IT_DTIMEOUT:   Data timeout interrupt
+  *            @arg SDMMC_IT_TXUNDERR:   Transmit FIFO underrun error interrupt
+  *            @arg SDMMC_IT_RXOVERR:    Received FIFO overrun error interrupt
+  *            @arg SDMMC_IT_CMDREND:    Command response received (CRC check passed) interrupt
+  *            @arg SDMMC_IT_CMDSENT:    Command sent (no response required) interrupt
+  *            @arg SDMMC_IT_DATAEND:    Data end (data counter, DATACOUNT, is zero) interrupt
+  *            @arg SDMMC_IT_DHOLD:      Data transfer Hold interrupt
+  *            @arg SDMMC_IT_DBCKEND:    Data block sent/received (CRC check passed) interrupt
+  *            @arg SDMMC_IT_DABORT:     Data transfer aborted by CMD12 interrupt
+  *            @arg SDMMC_IT_TXFIFOHE:   Transmit FIFO Half Empty interrupt
+  *            @arg SDMMC_IT_RXFIFOHF:   Receive FIFO Half Full interrupt
+  *            @arg SDMMC_IT_RXFIFOF:    Receive FIFO full interrupt
+  *            @arg SDMMC_IT_TXFIFOE:    Transmit FIFO empty interrupt
+  *            @arg SDMMC_IT_BUSYD0END:  End of SDMMC_D0 Busy following a CMD response detected interrupt
+  *            @arg SDMMC_IT_SDIOIT:     SDIO interrupt received interrupt
+  *            @arg SDMMC_IT_ACKFAIL:    Boot Acknowledgment received interrupt
+  *            @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt
+  *            @arg SDMMC_IT_VSWEND:     Voltage switch critical timing section completion interrupt
+  *            @arg SDMMC_IT_CKSTOP:     SDMMC_CK stopped in Voltage switch procedure interrupt
+  *            @arg SDMMC_IT_IDMABTC:    IDMA buffer transfer complete interrupt
+  * @retval The new state of SD IT (SET or RESET).
+  */
+#define __HAL_SD_GET_IT(__HANDLE__, __INTERRUPT__) __SDMMC_GET_IT((__HANDLE__)->Instance, (__INTERRUPT__))
+
+/**
+  * @brief  Clear the SD's interrupt pending bits.
+  * @param  __HANDLE__ SD Handle.
+  * @param  __INTERRUPT__ specifies the interrupt pending bit to clear.
+  *          This parameter can be one or a combination of the following values:
+  *            @arg SDMMC_IT_CCRCFAIL:   Command response received (CRC check failed) interrupt
+  *            @arg SDMMC_IT_DCRCFAIL:   Data block sent/received (CRC check failed) interrupt
+  *            @arg SDMMC_IT_CTIMEOUT:   Command response timeout interrupt
+  *            @arg SDMMC_IT_DTIMEOUT:   Data timeout interrupt
+  *            @arg SDMMC_IT_TXUNDERR:   Transmit FIFO underrun error interrupt
+  *            @arg SDMMC_IT_RXOVERR:    Received FIFO overrun error interrupt
+  *            @arg SDMMC_IT_CMDREND:    Command response received (CRC check passed) interrupt
+  *            @arg SDMMC_IT_CMDSENT:    Command sent (no response required) interrupt
+  *            @arg SDMMC_IT_DATAEND:    Data end (data counter, DATACOUNT, is zero) interrupt
+  *            @arg SDMMC_IT_DHOLD:      Data transfer Hold interrupt
+  *            @arg SDMMC_IT_DBCKEND:    Data block sent/received (CRC check passed) interrupt
+  *            @arg SDMMC_IT_DABORT:     Data transfer aborted by CMD12 interrupt
+  *            @arg SDMMC_IT_BUSYD0END:  End of SDMMC_D0 Busy following a CMD response detected interrupt
+  *            @arg SDMMC_IT_SDIOIT:     SDIO interrupt received interrupt
+  *            @arg SDMMC_IT_ACKFAIL:    Boot Acknowledgment received interrupt
+  *            @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt
+  *            @arg SDMMC_IT_VSWEND:     Voltage switch critical timing section completion interrupt
+  *            @arg SDMMC_IT_CKSTOP:     SDMMC_CK stopped in Voltage switch procedure interrupt
+  *            @arg SDMMC_IT_IDMABTC:    IDMA buffer transfer complete interrupt
+  * @retval None
+  */
+#define __HAL_SD_CLEAR_IT(__HANDLE__, __INTERRUPT__) __SDMMC_CLEAR_IT((__HANDLE__)->Instance, (__INTERRUPT__))
+
+/**
+  * @}
+  */
+
+/* Include SD HAL Extension module */
+#include "stm32h7xx_hal_sd_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup SD_Exported_Functions SD Exported Functions
+  * @{
+  */
+
+/** @defgroup SD_Exported_Functions_Group1 Initialization and de-initialization functions
+  * @{
+  */
+HAL_StatusTypeDef HAL_SD_Init(SD_HandleTypeDef *hsd);
+HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd);
+HAL_StatusTypeDef HAL_SD_DeInit(SD_HandleTypeDef *hsd);
+void              HAL_SD_MspInit(SD_HandleTypeDef *hsd);
+void              HAL_SD_MspDeInit(SD_HandleTypeDef *hsd);
+/**
+  * @}
+  */
+
+/** @defgroup SD_Exported_Functions_Group2 Input and Output operation functions
+  * @{
+  */
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks,
+                                    uint32_t Timeout);
+HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, const uint8_t *pData, uint32_t BlockAdd,
+                                     uint32_t NumberOfBlocks, uint32_t Timeout);
+HAL_StatusTypeDef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint32_t BlockStartAdd, uint32_t BlockEndAdd);
+/* Non-Blocking mode: IT */
+HAL_StatusTypeDef HAL_SD_ReadBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd,
+                                       uint32_t NumberOfBlocks);
+HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, const uint8_t *pData, uint32_t BlockAdd,
+                                        uint32_t NumberOfBlocks);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd,
+                                        uint32_t NumberOfBlocks);
+HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, const uint8_t *pData, uint32_t BlockAdd,
+                                         uint32_t NumberOfBlocks);
+
+void              HAL_SD_IRQHandler(SD_HandleTypeDef *hsd);
+
+/* Callback in non blocking modes (DMA) */
+void              HAL_SD_TxCpltCallback(SD_HandleTypeDef *hsd);
+void              HAL_SD_RxCpltCallback(SD_HandleTypeDef *hsd);
+void              HAL_SD_ErrorCallback(SD_HandleTypeDef *hsd);
+void              HAL_SD_AbortCallback(SD_HandleTypeDef *hsd);
+
+#if (USE_SD_TRANSCEIVER != 0U)
+/* Callback to switch in 1.8V mode */
+void              HAL_SD_DriveTransceiver_1_8V_Callback(FlagStatus status);
+#endif /* USE_SD_TRANSCEIVER */
+
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+/* SD callback registering/unregistering */
+HAL_StatusTypeDef HAL_SD_RegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef CallbackID,
+                                          pSD_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_SD_UnRegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef CallbackID);
+
+#if (USE_SD_TRANSCEIVER != 0U)
+HAL_StatusTypeDef HAL_SD_RegisterTransceiverCallback(SD_HandleTypeDef *hsd, pSD_TransceiverCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_SD_UnRegisterTransceiverCallback(SD_HandleTypeDef *hsd);
+#endif /* USE_SD_TRANSCEIVER */
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/** @defgroup SD_Exported_Functions_Group3 Peripheral Control functions
+  * @{
+  */
+HAL_StatusTypeDef HAL_SD_ConfigWideBusOperation(SD_HandleTypeDef *hsd, uint32_t WideMode);
+HAL_StatusTypeDef HAL_SD_ConfigSpeedBusOperation(SD_HandleTypeDef *hsd, uint32_t SpeedMode);
+/**
+  * @}
+  */
+
+/** @defgroup SD_Exported_Functions_Group4 SD card related functions
+  * @{
+  */
+HAL_SD_CardStateTypeDef HAL_SD_GetCardState(SD_HandleTypeDef *hsd);
+HAL_StatusTypeDef       HAL_SD_GetCardCID(SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypeDef *pCID);
+HAL_StatusTypeDef       HAL_SD_GetCardCSD(SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypeDef *pCSD);
+HAL_StatusTypeDef       HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypeDef *pStatus);
+HAL_StatusTypeDef       HAL_SD_GetCardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypeDef *pCardInfo);
+/**
+  * @}
+  */
+
+/** @defgroup SD_Exported_Functions_Group5 Peripheral State and Errors functions
+  * @{
+  */
+HAL_SD_StateTypeDef HAL_SD_GetState(SD_HandleTypeDef *hsd);
+uint32_t            HAL_SD_GetError(SD_HandleTypeDef *hsd);
+/**
+  * @}
+  */
+
+/** @defgroup SD_Exported_Functions_Group6 Perioheral Abort management
+  * @{
+  */
+HAL_StatusTypeDef HAL_SD_Abort(SD_HandleTypeDef *hsd);
+HAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd);
+/**
+  * @}
+  */
+
+/* Private types -------------------------------------------------------------*/
+/** @defgroup SD_Private_Types SD Private Types
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private defines -----------------------------------------------------------*/
+/** @defgroup SD_Private_Defines SD Private Defines
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup SD_Private_Variables SD Private Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup SD_Private_Constants SD Private Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup SD_Private_Macros SD Private Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private functions prototypes ----------------------------------------------*/
+/** @defgroup SD_Private_Functions_Prototypes SD Private Functions Prototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup SD_Private_Functions SD Private Functions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* STM32H7xx_HAL_SD_H */
diff --git a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h
new file mode 100644
index 0000000..450e7df
--- /dev/null
+++ b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h
@@ -0,0 +1,110 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_sd_ex.h
+  * @author  MCD Application Team
+  * @brief   Header file of SD HAL extended module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_HAL_SD_EX_H
+#define STM32H7xx_HAL_SD_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal_def.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup SDEx
+  * @brief SD HAL extended module driver
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup SDEx_Exported_Types SDEx Exported Types
+  * @{
+  */
+
+/** @defgroup SDEx_Exported_Types_Group1 SD Card Internal DMA Buffer structure
+  * @{
+  */
+typedef enum
+{
+  SD_DMA_BUFFER0      = 0x00U,    /*!< selects SD internal DMA Buffer 0     */
+  SD_DMA_BUFFER1      = 0x01U,    /*!< selects SD internal DMA Buffer 1     */
+
+} HAL_SDEx_DMABuffer_MemoryTypeDef;
+
+/**
+  * @}
+  */
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup SDEx_Exported_Functions SDEx Exported Functions
+  * @{
+  */
+
+/** @defgroup SDEx_Exported_Functions_Group1 MultiBuffer functions
+  * @{
+  */
+
+HAL_StatusTypeDef HAL_SDEx_ConfigDMAMultiBuffer(SD_HandleTypeDef *hsd, uint32_t *pDataBuffer0, uint32_t *pDataBuffer1,
+                                                uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SDEx_ReadBlocksDMAMultiBuffer(SD_HandleTypeDef *hsd, uint32_t BlockAdd, uint32_t NumberOfBlocks);
+HAL_StatusTypeDef HAL_SDEx_WriteBlocksDMAMultiBuffer(SD_HandleTypeDef *hsd, uint32_t BlockAdd, uint32_t NumberOfBlocks);
+HAL_StatusTypeDef HAL_SDEx_ChangeDMABuffer(SD_HandleTypeDef *hsd, HAL_SDEx_DMABuffer_MemoryTypeDef Buffer,
+                                           uint32_t *pDataBuffer);
+
+void HAL_SDEx_Read_DMADoubleBuf0CpltCallback(SD_HandleTypeDef *hsd);
+void HAL_SDEx_Read_DMADoubleBuf1CpltCallback(SD_HandleTypeDef *hsd);
+void HAL_SDEx_Write_DMADoubleBuf0CpltCallback(SD_HandleTypeDef *hsd);
+void HAL_SDEx_Write_DMADoubleBuf1CpltCallback(SD_HandleTypeDef *hsd);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private defines -----------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private functions prototypes ----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* stm32h7xx_HAL_SD_EX_H */
diff --git a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h
new file mode 100644
index 0000000..c6fced0
--- /dev/null
+++ b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h
@@ -0,0 +1,1749 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_uart.h
+  * @author  MCD Application Team
+  * @brief   Header file of UART HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_HAL_UART_H
+#define STM32H7xx_HAL_UART_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal_def.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup UART
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup UART_Exported_Types UART Exported Types
+  * @{
+  */
+
+/**
+  * @brief UART Init Structure definition
+  */
+typedef struct
+{
+  uint32_t BaudRate;                /*!< This member configures the UART communication baud rate.
+                                         The baud rate register is computed using the following formula:
+                                         LPUART:
+                                         =======
+                                         Baud Rate Register = ((256 * lpuart_ker_ckpres) / ((huart->Init.BaudRate)))
+                                         where lpuart_ker_ck_pres is the UART input clock divided by a prescaler
+                                         UART:
+                                         =====
+                                         - If oversampling is 16 or in LIN mode,
+                                            Baud Rate Register = ((uart_ker_ckpres) / ((huart->Init.BaudRate)))
+                                         - If oversampling is 8,
+                                            Baud Rate Register[15:4] = ((2 * uart_ker_ckpres) /
+                                            ((huart->Init.BaudRate)))[15:4]
+                                            Baud Rate Register[3] =  0
+                                            Baud Rate Register[2:0] =  (((2 * uart_ker_ckpres) /
+                                            ((huart->Init.BaudRate)))[3:0]) >> 1
+                                         where uart_ker_ck_pres is the UART input clock divided by a prescaler */
+
+  uint32_t WordLength;              /*!< Specifies the number of data bits transmitted or received in a frame.
+                                         This parameter can be a value of @ref UARTEx_Word_Length. */
+
+  uint32_t StopBits;                /*!< Specifies the number of stop bits transmitted.
+                                         This parameter can be a value of @ref UART_Stop_Bits. */
+
+  uint32_t Parity;                  /*!< Specifies the parity mode.
+                                         This parameter can be a value of @ref UART_Parity
+                                         @note When parity is enabled, the computed parity is inserted
+                                               at the MSB position of the transmitted data (9th bit when
+                                               the word length is set to 9 data bits; 8th bit when the
+                                               word length is set to 8 data bits). */
+
+  uint32_t Mode;                    /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
+                                         This parameter can be a value of @ref UART_Mode. */
+
+  uint32_t HwFlowCtl;               /*!< Specifies whether the hardware flow control mode is enabled
+                                         or disabled.
+                                         This parameter can be a value of @ref UART_Hardware_Flow_Control. */
+
+  uint32_t OverSampling;            /*!< Specifies whether the Over sampling 8 is enabled or disabled,
+                                         to achieve higher speed (up to f_PCLK/8).
+                                         This parameter can be a value of @ref UART_Over_Sampling. */
+
+  uint32_t OneBitSampling;          /*!< Specifies whether a single sample or three samples' majority vote is selected.
+                                         Selecting the single sample method increases the receiver tolerance to clock
+                                         deviations. This parameter can be a value of @ref UART_OneBit_Sampling. */
+
+  uint32_t ClockPrescaler;          /*!< Specifies the prescaler value used to divide the UART clock source.
+                                         This parameter can be a value of @ref UART_ClockPrescaler. */
+
+} UART_InitTypeDef;
+
+/**
+  * @brief  UART Advanced Features initialization structure definition
+  */
+typedef struct
+{
+  uint32_t AdvFeatureInit;        /*!< Specifies which advanced UART features is initialized. Several
+                                       Advanced Features may be initialized at the same time .
+                                       This parameter can be a value of
+                                       @ref UART_Advanced_Features_Initialization_Type. */
+
+  uint32_t TxPinLevelInvert;      /*!< Specifies whether the TX pin active level is inverted.
+                                       This parameter can be a value of @ref UART_Tx_Inv. */
+
+  uint32_t RxPinLevelInvert;      /*!< Specifies whether the RX pin active level is inverted.
+                                       This parameter can be a value of @ref UART_Rx_Inv. */
+
+  uint32_t DataInvert;            /*!< Specifies whether data are inverted (positive/direct logic
+                                       vs negative/inverted logic).
+                                       This parameter can be a value of @ref UART_Data_Inv. */
+
+  uint32_t Swap;                  /*!< Specifies whether TX and RX pins are swapped.
+                                       This parameter can be a value of @ref UART_Rx_Tx_Swap. */
+
+  uint32_t OverrunDisable;        /*!< Specifies whether the reception overrun detection is disabled.
+                                       This parameter can be a value of @ref UART_Overrun_Disable. */
+
+  uint32_t DMADisableonRxError;   /*!< Specifies whether the DMA is disabled in case of reception error.
+                                       This parameter can be a value of @ref UART_DMA_Disable_on_Rx_Error. */
+
+  uint32_t AutoBaudRateEnable;    /*!< Specifies whether auto Baud rate detection is enabled.
+                                       This parameter can be a value of @ref UART_AutoBaudRate_Enable. */
+
+  uint32_t AutoBaudRateMode;      /*!< If auto Baud rate detection is enabled, specifies how the rate
+                                       detection is carried out.
+                                       This parameter can be a value of @ref UART_AutoBaud_Rate_Mode. */
+
+  uint32_t MSBFirst;              /*!< Specifies whether MSB is sent first on UART line.
+                                       This parameter can be a value of @ref UART_MSB_First. */
+} UART_AdvFeatureInitTypeDef;
+
+/**
+  * @brief HAL UART State definition
+  * @note  HAL UART State value is a combination of 2 different substates:
+  *        gState and RxState (see @ref UART_State_Definition).
+  *        - gState contains UART state information related to global Handle management
+  *          and also information related to Tx operations.
+  *          gState value coding follow below described bitmap :
+  *          b7-b6  Error information
+  *             00 : No Error
+  *             01 : (Not Used)
+  *             10 : Timeout
+  *             11 : Error
+  *          b5     Peripheral initialization status
+  *             0  : Reset (Peripheral not initialized)
+  *             1  : Init done (Peripheral initialized. HAL UART Init function already called)
+  *          b4-b3  (not used)
+  *             xx : Should be set to 00
+  *          b2     Intrinsic process state
+  *             0  : Ready
+  *             1  : Busy (Peripheral busy with some configuration or internal operations)
+  *          b1     (not used)
+  *             x  : Should be set to 0
+  *          b0     Tx state
+  *             0  : Ready (no Tx operation ongoing)
+  *             1  : Busy (Tx operation ongoing)
+  *        - RxState contains information related to Rx operations.
+  *          RxState value coding follow below described bitmap :
+  *          b7-b6  (not used)
+  *             xx : Should be set to 00
+  *          b5     Peripheral initialization status
+  *             0  : Reset (Peripheral not initialized)
+  *             1  : Init done (Peripheral initialized)
+  *          b4-b2  (not used)
+  *            xxx : Should be set to 000
+  *          b1     Rx state
+  *             0  : Ready (no Rx operation ongoing)
+  *             1  : Busy (Rx operation ongoing)
+  *          b0     (not used)
+  *             x  : Should be set to 0.
+  */
+typedef uint32_t HAL_UART_StateTypeDef;
+
+/**
+  * @brief UART clock sources definition
+  */
+typedef enum
+{
+  UART_CLOCKSOURCE_D2PCLK1    = 0x00U,    /*!< Domain2 PCLK1 clock source */
+  UART_CLOCKSOURCE_D2PCLK2    = 0x01U,    /*!< Domain2 PCLK2 clock source */
+  UART_CLOCKSOURCE_D3PCLK1    = 0x02U,    /*!< Domain3 PCLK1 clock source */
+  UART_CLOCKSOURCE_PLL2       = 0x04U,    /*!< PLL2Q clock source         */
+  UART_CLOCKSOURCE_PLL3       = 0x08U,    /*!< PLL3Q clock source         */
+  UART_CLOCKSOURCE_HSI        = 0x10U,    /*!< HSI clock source           */
+  UART_CLOCKSOURCE_CSI        = 0x20U,    /*!< CSI clock source           */
+  UART_CLOCKSOURCE_LSE        = 0x40U,    /*!< LSE clock source           */
+  UART_CLOCKSOURCE_UNDEFINED  = 0x80U     /*!< Undefined clock source     */
+} UART_ClockSourceTypeDef;
+
+/**
+  * @brief HAL UART Reception type definition
+  * @note  HAL UART Reception type value aims to identify which type of Reception is ongoing.
+  *        This parameter can be a value of @ref UART_Reception_Type_Values :
+  *           HAL_UART_RECEPTION_STANDARD         = 0x00U,
+  *           HAL_UART_RECEPTION_TOIDLE           = 0x01U,
+  *           HAL_UART_RECEPTION_TORTO            = 0x02U,
+  *           HAL_UART_RECEPTION_TOCHARMATCH      = 0x03U,
+  */
+typedef uint32_t HAL_UART_RxTypeTypeDef;
+
+/**
+  * @brief HAL UART Rx Event type definition
+  * @note  HAL UART Rx Event type value aims to identify which type of Event has occurred
+  *        leading to call of the RxEvent callback.
+  *        This parameter can be a value of @ref UART_RxEvent_Type_Values :
+  *           HAL_UART_RXEVENT_TC                 = 0x00U,
+  *           HAL_UART_RXEVENT_HT                 = 0x01U,
+  *           HAL_UART_RXEVENT_IDLE               = 0x02U,
+  */
+typedef uint32_t HAL_UART_RxEventTypeTypeDef;
+
+/**
+  * @brief  UART handle Structure definition
+  */
+typedef struct __UART_HandleTypeDef
+{
+  USART_TypeDef            *Instance;                /*!< UART registers base address        */
+
+  UART_InitTypeDef         Init;                     /*!< UART communication parameters      */
+
+  UART_AdvFeatureInitTypeDef AdvancedInit;           /*!< UART Advanced Features initialization parameters */
+
+  const uint8_t            *pTxBuffPtr;              /*!< Pointer to UART Tx transfer Buffer */
+
+  uint16_t                 TxXferSize;               /*!< UART Tx Transfer size              */
+
+  __IO uint16_t            TxXferCount;              /*!< UART Tx Transfer Counter           */
+
+  uint8_t                  *pRxBuffPtr;              /*!< Pointer to UART Rx transfer Buffer */
+
+  uint16_t                 RxXferSize;               /*!< UART Rx Transfer size              */
+
+  __IO uint16_t            RxXferCount;              /*!< UART Rx Transfer Counter           */
+
+  uint16_t                 Mask;                     /*!< UART Rx RDR register mask          */
+
+  uint32_t                 FifoMode;                 /*!< Specifies if the FIFO mode is being used.
+                                                          This parameter can be a value of @ref UARTEx_FIFO_mode. */
+
+  uint16_t                 NbRxDataToProcess;        /*!< Number of data to process during RX ISR execution */
+
+  uint16_t                 NbTxDataToProcess;        /*!< Number of data to process during TX ISR execution */
+
+  __IO HAL_UART_RxTypeTypeDef ReceptionType;         /*!< Type of ongoing reception          */
+
+  __IO HAL_UART_RxEventTypeTypeDef RxEventType;      /*!< Type of Rx Event                   */
+
+  void (*RxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Rx IRQ handler */
+
+  void (*TxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Tx IRQ handler */
+
+  DMA_HandleTypeDef        *hdmatx;                  /*!< UART Tx DMA Handle parameters      */
+
+  DMA_HandleTypeDef        *hdmarx;                  /*!< UART Rx DMA Handle parameters      */
+
+  HAL_LockTypeDef           Lock;                    /*!< Locking object                     */
+
+  __IO HAL_UART_StateTypeDef    gState;              /*!< UART state information related to global Handle management
+                                                          and also related to Tx operations. This parameter
+                                                          can be a value of @ref HAL_UART_StateTypeDef */
+
+  __IO HAL_UART_StateTypeDef    RxState;             /*!< UART state information related to Rx operations. This
+                                                          parameter can be a value of @ref HAL_UART_StateTypeDef */
+
+  __IO uint32_t                 ErrorCode;           /*!< UART Error code                    */
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+  void (* TxHalfCpltCallback)(struct __UART_HandleTypeDef *huart);        /*!< UART Tx Half Complete Callback        */
+  void (* TxCpltCallback)(struct __UART_HandleTypeDef *huart);            /*!< UART Tx Complete Callback             */
+  void (* RxHalfCpltCallback)(struct __UART_HandleTypeDef *huart);        /*!< UART Rx Half Complete Callback        */
+  void (* RxCpltCallback)(struct __UART_HandleTypeDef *huart);            /*!< UART Rx Complete Callback             */
+  void (* ErrorCallback)(struct __UART_HandleTypeDef *huart);             /*!< UART Error Callback                   */
+  void (* AbortCpltCallback)(struct __UART_HandleTypeDef *huart);         /*!< UART Abort Complete Callback          */
+  void (* AbortTransmitCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Transmit Complete Callback */
+  void (* AbortReceiveCpltCallback)(struct __UART_HandleTypeDef *huart);  /*!< UART Abort Receive Complete Callback  */
+  void (* WakeupCallback)(struct __UART_HandleTypeDef *huart);            /*!< UART Wakeup Callback                  */
+  void (* RxFifoFullCallback)(struct __UART_HandleTypeDef *huart);        /*!< UART Rx Fifo Full Callback            */
+  void (* TxFifoEmptyCallback)(struct __UART_HandleTypeDef *huart);       /*!< UART Tx Fifo Empty Callback           */
+  void (* RxEventCallback)(struct __UART_HandleTypeDef *huart, uint16_t Pos); /*!< UART Reception Event Callback     */
+
+  void (* MspInitCallback)(struct __UART_HandleTypeDef *huart);           /*!< UART Msp Init callback                */
+  void (* MspDeInitCallback)(struct __UART_HandleTypeDef *huart);         /*!< UART Msp DeInit callback              */
+#endif  /* USE_HAL_UART_REGISTER_CALLBACKS */
+
+} UART_HandleTypeDef;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  HAL UART Callback ID enumeration definition
+  */
+typedef enum
+{
+  HAL_UART_TX_HALFCOMPLETE_CB_ID         = 0x00U,    /*!< UART Tx Half Complete Callback ID        */
+  HAL_UART_TX_COMPLETE_CB_ID             = 0x01U,    /*!< UART Tx Complete Callback ID             */
+  HAL_UART_RX_HALFCOMPLETE_CB_ID         = 0x02U,    /*!< UART Rx Half Complete Callback ID        */
+  HAL_UART_RX_COMPLETE_CB_ID             = 0x03U,    /*!< UART Rx Complete Callback ID             */
+  HAL_UART_ERROR_CB_ID                   = 0x04U,    /*!< UART Error Callback ID                   */
+  HAL_UART_ABORT_COMPLETE_CB_ID          = 0x05U,    /*!< UART Abort Complete Callback ID          */
+  HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x06U,    /*!< UART Abort Transmit Complete Callback ID */
+  HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID  = 0x07U,    /*!< UART Abort Receive Complete Callback ID  */
+  HAL_UART_WAKEUP_CB_ID                  = 0x08U,    /*!< UART Wakeup Callback ID                  */
+  HAL_UART_RX_FIFO_FULL_CB_ID            = 0x09U,    /*!< UART Rx Fifo Full Callback ID            */
+  HAL_UART_TX_FIFO_EMPTY_CB_ID           = 0x0AU,    /*!< UART Tx Fifo Empty Callback ID           */
+
+  HAL_UART_MSPINIT_CB_ID                 = 0x0BU,    /*!< UART MspInit callback ID                 */
+  HAL_UART_MSPDEINIT_CB_ID               = 0x0CU     /*!< UART MspDeInit callback ID               */
+
+} HAL_UART_CallbackIDTypeDef;
+
+/**
+  * @brief  HAL UART Callback pointer definition
+  */
+typedef  void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer to an UART callback function */
+typedef  void (*pUART_RxEventCallbackTypeDef)
+(struct __UART_HandleTypeDef *huart, uint16_t Pos); /*!< pointer to a UART Rx Event specific callback function */
+
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup UART_Exported_Constants UART Exported Constants
+  * @{
+  */
+
+/** @defgroup UART_State_Definition UART State Code Definition
+  * @{
+  */
+#define  HAL_UART_STATE_RESET         0x00000000U    /*!< Peripheral is not initialized
+                                                          Value is allowed for gState and RxState */
+#define  HAL_UART_STATE_READY         0x00000020U    /*!< Peripheral Initialized and ready for use
+                                                          Value is allowed for gState and RxState */
+#define  HAL_UART_STATE_BUSY          0x00000024U    /*!< an internal process is ongoing
+                                                          Value is allowed for gState only */
+#define  HAL_UART_STATE_BUSY_TX       0x00000021U    /*!< Data Transmission process is ongoing
+                                                          Value is allowed for gState only */
+#define  HAL_UART_STATE_BUSY_RX       0x00000022U    /*!< Data Reception process is ongoing
+                                                          Value is allowed for RxState only */
+#define  HAL_UART_STATE_BUSY_TX_RX    0x00000023U    /*!< Data Transmission and Reception process is ongoing
+                                                          Not to be used for neither gState nor RxState.Value is result
+                                                          of combination (Or) between gState and RxState values */
+#define  HAL_UART_STATE_TIMEOUT       0x000000A0U    /*!< Timeout state
+                                                          Value is allowed for gState only */
+#define  HAL_UART_STATE_ERROR         0x000000E0U    /*!< Error
+                                                          Value is allowed for gState only */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Error_Definition   UART Error Definition
+  * @{
+  */
+#define  HAL_UART_ERROR_NONE             (0x00000000U)    /*!< No error                */
+#define  HAL_UART_ERROR_PE               (0x00000001U)    /*!< Parity error            */
+#define  HAL_UART_ERROR_NE               (0x00000002U)    /*!< Noise error             */
+#define  HAL_UART_ERROR_FE               (0x00000004U)    /*!< Frame error             */
+#define  HAL_UART_ERROR_ORE              (0x00000008U)    /*!< Overrun error           */
+#define  HAL_UART_ERROR_DMA              (0x00000010U)    /*!< DMA transfer error      */
+#define  HAL_UART_ERROR_RTO              (0x00000020U)    /*!< Receiver Timeout error  */
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+#define  HAL_UART_ERROR_INVALID_CALLBACK (0x00000040U)    /*!< Invalid Callback error  */
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Stop_Bits   UART Number of Stop Bits
+  * @{
+  */
+#define UART_STOPBITS_0_5                    USART_CR2_STOP_0                     /*!< UART frame with 0.5 stop bit  */
+#define UART_STOPBITS_1                     0x00000000U                           /*!< UART frame with 1 stop bit    */
+#define UART_STOPBITS_1_5                   (USART_CR2_STOP_0 | USART_CR2_STOP_1) /*!< UART frame with 1.5 stop bits */
+#define UART_STOPBITS_2                      USART_CR2_STOP_1                     /*!< UART frame with 2 stop bits   */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Parity  UART Parity
+  * @{
+  */
+#define UART_PARITY_NONE                    0x00000000U                        /*!< No parity   */
+#define UART_PARITY_EVEN                    USART_CR1_PCE                      /*!< Even parity */
+#define UART_PARITY_ODD                     (USART_CR1_PCE | USART_CR1_PS)     /*!< Odd parity  */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Hardware_Flow_Control UART Hardware Flow Control
+  * @{
+  */
+#define UART_HWCONTROL_NONE                  0x00000000U                          /*!< No hardware control       */
+#define UART_HWCONTROL_RTS                   USART_CR3_RTSE                       /*!< Request To Send           */
+#define UART_HWCONTROL_CTS                   USART_CR3_CTSE                       /*!< Clear To Send             */
+#define UART_HWCONTROL_RTS_CTS               (USART_CR3_RTSE | USART_CR3_CTSE)    /*!< Request and Clear To Send */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Mode UART Transfer Mode
+  * @{
+  */
+#define UART_MODE_RX                        USART_CR1_RE                    /*!< RX mode        */
+#define UART_MODE_TX                        USART_CR1_TE                    /*!< TX mode        */
+#define UART_MODE_TX_RX                     (USART_CR1_TE |USART_CR1_RE)    /*!< RX and TX mode */
+/**
+  * @}
+  */
+
+/** @defgroup UART_State  UART State
+  * @{
+  */
+#define UART_STATE_DISABLE                  0x00000000U         /*!< UART disabled  */
+#define UART_STATE_ENABLE                   USART_CR1_UE        /*!< UART enabled   */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Over_Sampling UART Over Sampling
+  * @{
+  */
+#define UART_OVERSAMPLING_16                0x00000000U         /*!< Oversampling by 16 */
+#define UART_OVERSAMPLING_8                 USART_CR1_OVER8     /*!< Oversampling by 8  */
+/**
+  * @}
+  */
+
+/** @defgroup UART_OneBit_Sampling UART One Bit Sampling Method
+  * @{
+  */
+#define UART_ONE_BIT_SAMPLE_DISABLE         0x00000000U         /*!< One-bit sampling disable */
+#define UART_ONE_BIT_SAMPLE_ENABLE          USART_CR3_ONEBIT    /*!< One-bit sampling enable  */
+/**
+  * @}
+  */
+
+/** @defgroup UART_ClockPrescaler  UART Clock Prescaler
+  * @{
+  */
+#define UART_PRESCALER_DIV1    0x00000000U  /*!< fclk_pres = fclk     */
+#define UART_PRESCALER_DIV2    0x00000001U  /*!< fclk_pres = fclk/2   */
+#define UART_PRESCALER_DIV4    0x00000002U  /*!< fclk_pres = fclk/4   */
+#define UART_PRESCALER_DIV6    0x00000003U  /*!< fclk_pres = fclk/6   */
+#define UART_PRESCALER_DIV8    0x00000004U  /*!< fclk_pres = fclk/8   */
+#define UART_PRESCALER_DIV10   0x00000005U  /*!< fclk_pres = fclk/10  */
+#define UART_PRESCALER_DIV12   0x00000006U  /*!< fclk_pres = fclk/12  */
+#define UART_PRESCALER_DIV16   0x00000007U  /*!< fclk_pres = fclk/16  */
+#define UART_PRESCALER_DIV32   0x00000008U  /*!< fclk_pres = fclk/32  */
+#define UART_PRESCALER_DIV64   0x00000009U  /*!< fclk_pres = fclk/64  */
+#define UART_PRESCALER_DIV128  0x0000000AU  /*!< fclk_pres = fclk/128 */
+#define UART_PRESCALER_DIV256  0x0000000BU  /*!< fclk_pres = fclk/256 */
+/**
+  * @}
+  */
+
+/** @defgroup UART_AutoBaud_Rate_Mode    UART Advanced Feature AutoBaud Rate Mode
+  * @{
+  */
+#define UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT    0x00000000U           /*!< Auto Baud rate detection
+                                                                              on start bit              */
+#define UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE USART_CR2_ABRMODE_0   /*!< Auto Baud rate detection
+                                                                              on falling edge           */
+#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME   USART_CR2_ABRMODE_1   /*!< Auto Baud rate detection
+                                                                              on 0x7F frame detection   */
+#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME   USART_CR2_ABRMODE     /*!< Auto Baud rate detection
+                                                                              on 0x55 frame detection   */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Receiver_Timeout UART Receiver Timeout
+  * @{
+  */
+#define UART_RECEIVER_TIMEOUT_DISABLE       0x00000000U                /*!< UART Receiver Timeout disable */
+#define UART_RECEIVER_TIMEOUT_ENABLE        USART_CR2_RTOEN            /*!< UART Receiver Timeout enable  */
+/**
+  * @}
+  */
+
+/** @defgroup UART_LIN    UART Local Interconnection Network mode
+  * @{
+  */
+#define UART_LIN_DISABLE                    0x00000000U                /*!< Local Interconnect Network disable */
+#define UART_LIN_ENABLE                     USART_CR2_LINEN            /*!< Local Interconnect Network enable  */
+/**
+  * @}
+  */
+
+/** @defgroup UART_LIN_Break_Detection  UART LIN Break Detection
+  * @{
+  */
+#define UART_LINBREAKDETECTLENGTH_10B       0x00000000U                /*!< LIN 10-bit break detection length */
+#define UART_LINBREAKDETECTLENGTH_11B       USART_CR2_LBDL             /*!< LIN 11-bit break detection length  */
+/**
+  * @}
+  */
+
+/** @defgroup UART_DMA_Tx    UART DMA Tx
+  * @{
+  */
+#define UART_DMA_TX_DISABLE                 0x00000000U                /*!< UART DMA TX disabled */
+#define UART_DMA_TX_ENABLE                  USART_CR3_DMAT             /*!< UART DMA TX enabled  */
+/**
+  * @}
+  */
+
+/** @defgroup UART_DMA_Rx   UART DMA Rx
+  * @{
+  */
+#define UART_DMA_RX_DISABLE                 0x00000000U                 /*!< UART DMA RX disabled */
+#define UART_DMA_RX_ENABLE                  USART_CR3_DMAR              /*!< UART DMA RX enabled  */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Half_Duplex_Selection  UART Half Duplex Selection
+  * @{
+  */
+#define UART_HALF_DUPLEX_DISABLE            0x00000000U                 /*!< UART half-duplex disabled */
+#define UART_HALF_DUPLEX_ENABLE             USART_CR3_HDSEL             /*!< UART half-duplex enabled  */
+/**
+  * @}
+  */
+
+/** @defgroup UART_WakeUp_Methods   UART WakeUp Methods
+  * @{
+  */
+#define UART_WAKEUPMETHOD_IDLELINE          0x00000000U                 /*!< UART wake-up on idle line    */
+#define UART_WAKEUPMETHOD_ADDRESSMARK       USART_CR1_WAKE              /*!< UART wake-up on address mark */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Request_Parameters UART Request Parameters
+  * @{
+  */
+#define UART_AUTOBAUD_REQUEST               USART_RQR_ABRRQ        /*!< Auto-Baud Rate Request      */
+#define UART_SENDBREAK_REQUEST              USART_RQR_SBKRQ        /*!< Send Break Request          */
+#define UART_MUTE_MODE_REQUEST              USART_RQR_MMRQ         /*!< Mute Mode Request           */
+#define UART_RXDATA_FLUSH_REQUEST           USART_RQR_RXFRQ        /*!< Receive Data flush Request  */
+#define UART_TXDATA_FLUSH_REQUEST           USART_RQR_TXFRQ        /*!< Transmit data flush Request */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Advanced_Features_Initialization_Type  UART Advanced Feature Initialization Type
+  * @{
+  */
+#define UART_ADVFEATURE_NO_INIT                 0x00000000U          /*!< No advanced feature initialization       */
+#define UART_ADVFEATURE_TXINVERT_INIT           0x00000001U          /*!< TX pin active level inversion            */
+#define UART_ADVFEATURE_RXINVERT_INIT           0x00000002U          /*!< RX pin active level inversion            */
+#define UART_ADVFEATURE_DATAINVERT_INIT         0x00000004U          /*!< Binary data inversion                    */
+#define UART_ADVFEATURE_SWAP_INIT               0x00000008U          /*!< TX/RX pins swap                          */
+#define UART_ADVFEATURE_RXOVERRUNDISABLE_INIT   0x00000010U          /*!< RX overrun disable                       */
+#define UART_ADVFEATURE_DMADISABLEONERROR_INIT  0x00000020U          /*!< DMA disable on Reception Error           */
+#define UART_ADVFEATURE_AUTOBAUDRATE_INIT       0x00000040U          /*!< Auto Baud rate detection initialization  */
+#define UART_ADVFEATURE_MSBFIRST_INIT           0x00000080U          /*!< Most significant bit sent/received first */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Tx_Inv UART Advanced Feature TX Pin Active Level Inversion
+  * @{
+  */
+#define UART_ADVFEATURE_TXINV_DISABLE       0x00000000U             /*!< TX pin active level inversion disable */
+#define UART_ADVFEATURE_TXINV_ENABLE        USART_CR2_TXINV         /*!< TX pin active level inversion enable  */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Rx_Inv UART Advanced Feature RX Pin Active Level Inversion
+  * @{
+  */
+#define UART_ADVFEATURE_RXINV_DISABLE       0x00000000U             /*!< RX pin active level inversion disable */
+#define UART_ADVFEATURE_RXINV_ENABLE        USART_CR2_RXINV         /*!< RX pin active level inversion enable  */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Data_Inv  UART Advanced Feature Binary Data Inversion
+  * @{
+  */
+#define UART_ADVFEATURE_DATAINV_DISABLE     0x00000000U             /*!< Binary data inversion disable */
+#define UART_ADVFEATURE_DATAINV_ENABLE      USART_CR2_DATAINV       /*!< Binary data inversion enable  */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Rx_Tx_Swap UART Advanced Feature RX TX Pins Swap
+  * @{
+  */
+#define UART_ADVFEATURE_SWAP_DISABLE        0x00000000U             /*!< TX/RX pins swap disable */
+#define UART_ADVFEATURE_SWAP_ENABLE         USART_CR2_SWAP          /*!< TX/RX pins swap enable  */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Overrun_Disable  UART Advanced Feature Overrun Disable
+  * @{
+  */
+#define UART_ADVFEATURE_OVERRUN_ENABLE      0x00000000U             /*!< RX overrun enable  */
+#define UART_ADVFEATURE_OVERRUN_DISABLE     USART_CR3_OVRDIS        /*!< RX overrun disable */
+/**
+  * @}
+  */
+
+/** @defgroup UART_AutoBaudRate_Enable  UART Advanced Feature Auto BaudRate Enable
+  * @{
+  */
+#define UART_ADVFEATURE_AUTOBAUDRATE_DISABLE   0x00000000U          /*!< RX Auto Baud rate detection enable  */
+#define UART_ADVFEATURE_AUTOBAUDRATE_ENABLE    USART_CR2_ABREN      /*!< RX Auto Baud rate detection disable */
+/**
+  * @}
+  */
+
+/** @defgroup UART_DMA_Disable_on_Rx_Error   UART Advanced Feature DMA Disable On Rx Error
+  * @{
+  */
+#define UART_ADVFEATURE_DMA_ENABLEONRXERROR    0x00000000U          /*!< DMA enable on Reception Error  */
+#define UART_ADVFEATURE_DMA_DISABLEONRXERROR   USART_CR3_DDRE       /*!< DMA disable on Reception Error */
+/**
+  * @}
+  */
+
+/** @defgroup UART_MSB_First   UART Advanced Feature MSB First
+  * @{
+  */
+#define UART_ADVFEATURE_MSBFIRST_DISABLE    0x00000000U             /*!< Most significant bit sent/received
+                                                                         first disable                      */
+#define UART_ADVFEATURE_MSBFIRST_ENABLE     USART_CR2_MSBFIRST      /*!< Most significant bit sent/received
+                                                                         first enable                       */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Stop_Mode_Enable   UART Advanced Feature Stop Mode Enable
+  * @{
+  */
+#define UART_ADVFEATURE_STOPMODE_DISABLE    0x00000000U             /*!< UART stop mode disable */
+#define UART_ADVFEATURE_STOPMODE_ENABLE     USART_CR1_UESM          /*!< UART stop mode enable  */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Mute_Mode   UART Advanced Feature Mute Mode Enable
+  * @{
+  */
+#define UART_ADVFEATURE_MUTEMODE_DISABLE    0x00000000U             /*!< UART mute mode disable */
+#define UART_ADVFEATURE_MUTEMODE_ENABLE     USART_CR1_MME           /*!< UART mute mode enable  */
+/**
+  * @}
+  */
+
+/** @defgroup UART_CR2_ADDRESS_LSB_POS    UART Address-matching LSB Position In CR2 Register
+  * @{
+  */
+#define UART_CR2_ADDRESS_LSB_POS             24U             /*!< UART address-matching LSB position in CR2 register */
+/**
+  * @}
+  */
+
+/** @defgroup UART_WakeUp_from_Stop_Selection   UART WakeUp From Stop Selection
+  * @{
+  */
+#define UART_WAKEUP_ON_ADDRESS              0x00000000U             /*!< UART wake-up on address                     */
+#define UART_WAKEUP_ON_STARTBIT             USART_CR3_WUS_1         /*!< UART wake-up on start bit                   */
+#define UART_WAKEUP_ON_READDATA_NONEMPTY    USART_CR3_WUS           /*!< UART wake-up on receive data register
+                                                                         not empty or RXFIFO is not empty            */
+/**
+  * @}
+  */
+
+/** @defgroup UART_DriverEnable_Polarity      UART DriverEnable Polarity
+  * @{
+  */
+#define UART_DE_POLARITY_HIGH               0x00000000U             /*!< Driver enable signal is active high */
+#define UART_DE_POLARITY_LOW                USART_CR3_DEP           /*!< Driver enable signal is active low  */
+/**
+  * @}
+  */
+
+/** @defgroup UART_CR1_DEAT_ADDRESS_LSB_POS    UART Driver Enable Assertion Time LSB Position In CR1 Register
+  * @{
+  */
+#define UART_CR1_DEAT_ADDRESS_LSB_POS       21U      /*!< UART Driver Enable assertion time LSB
+                                                          position in CR1 register */
+/**
+  * @}
+  */
+
+/** @defgroup UART_CR1_DEDT_ADDRESS_LSB_POS    UART Driver Enable DeAssertion Time LSB Position In CR1 Register
+  * @{
+  */
+#define UART_CR1_DEDT_ADDRESS_LSB_POS       16U      /*!< UART Driver Enable de-assertion time LSB
+                                                          position in CR1 register */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Interruption_Mask    UART Interruptions Flag Mask
+  * @{
+  */
+#define UART_IT_MASK                        0x001FU  /*!< UART interruptions flags mask */
+/**
+  * @}
+  */
+
+/** @defgroup UART_TimeOut_Value    UART polling-based communications time-out value
+  * @{
+  */
+#define HAL_UART_TIMEOUT_VALUE              0x1FFFFFFU  /*!< UART polling-based communications time-out value */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Flags     UART Status Flags
+  *        Elements values convention: 0xXXXX
+  *           - 0xXXXX  : Flag mask in the ISR register
+  * @{
+  */
+#define UART_FLAG_TXFT                      USART_ISR_TXFT          /*!< UART TXFIFO threshold flag                */
+#define UART_FLAG_RXFT                      USART_ISR_RXFT          /*!< UART RXFIFO threshold flag                */
+#define UART_FLAG_RXFF                      USART_ISR_RXFF          /*!< UART RXFIFO Full flag                     */
+#define UART_FLAG_TXFE                      USART_ISR_TXFE          /*!< UART TXFIFO Empty flag                    */
+#define UART_FLAG_REACK                     USART_ISR_REACK         /*!< UART receive enable acknowledge flag      */
+#define UART_FLAG_TEACK                     USART_ISR_TEACK         /*!< UART transmit enable acknowledge flag     */
+#define UART_FLAG_WUF                       USART_ISR_WUF           /*!< UART wake-up from stop mode flag          */
+#define UART_FLAG_RWU                       USART_ISR_RWU           /*!< UART receiver wake-up from mute mode flag */
+#define UART_FLAG_SBKF                      USART_ISR_SBKF          /*!< UART send break flag                      */
+#define UART_FLAG_CMF                       USART_ISR_CMF           /*!< UART character match flag                 */
+#define UART_FLAG_BUSY                      USART_ISR_BUSY          /*!< UART busy flag                            */
+#define UART_FLAG_ABRF                      USART_ISR_ABRF          /*!< UART auto Baud rate flag                  */
+#define UART_FLAG_ABRE                      USART_ISR_ABRE          /*!< UART auto Baud rate error                 */
+#define UART_FLAG_RTOF                      USART_ISR_RTOF          /*!< UART receiver timeout flag                */
+#define UART_FLAG_CTS                       USART_ISR_CTS           /*!< UART clear to send flag                   */
+#define UART_FLAG_CTSIF                     USART_ISR_CTSIF         /*!< UART clear to send interrupt flag         */
+#define UART_FLAG_LBDF                      USART_ISR_LBDF          /*!< UART LIN break detection flag             */
+#define UART_FLAG_TXE                       USART_ISR_TXE_TXFNF     /*!< UART transmit data register empty         */
+#define UART_FLAG_TXFNF                     USART_ISR_TXE_TXFNF     /*!< UART TXFIFO not full                      */
+#define UART_FLAG_TC                        USART_ISR_TC            /*!< UART transmission complete                */
+#define UART_FLAG_RXNE                      USART_ISR_RXNE_RXFNE    /*!< UART read data register not empty         */
+#define UART_FLAG_RXFNE                     USART_ISR_RXNE_RXFNE    /*!< UART RXFIFO not empty                     */
+#define UART_FLAG_IDLE                      USART_ISR_IDLE          /*!< UART idle flag                            */
+#define UART_FLAG_ORE                       USART_ISR_ORE           /*!< UART overrun error                        */
+#define UART_FLAG_NE                        USART_ISR_NE            /*!< UART noise error                          */
+#define UART_FLAG_FE                        USART_ISR_FE            /*!< UART frame error                          */
+#define UART_FLAG_PE                        USART_ISR_PE            /*!< UART parity error                         */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Interrupt_definition   UART Interrupts Definition
+  *        Elements values convention: 000ZZZZZ0XXYYYYYb
+  *           - YYYYY  : Interrupt source position in the XX register (5bits)
+  *           - XX  : Interrupt source register (2bits)
+  *                 - 01: CR1 register
+  *                 - 10: CR2 register
+  *                 - 11: CR3 register
+  *           - ZZZZZ  : Flag position in the ISR register(5bits)
+  *        Elements values convention: 000000000XXYYYYYb
+  *           - YYYYY  : Interrupt source position in the XX register (5bits)
+  *           - XX  : Interrupt source register (2bits)
+  *                 - 01: CR1 register
+  *                 - 10: CR2 register
+  *                 - 11: CR3 register
+  *        Elements values convention: 0000ZZZZ00000000b
+  *           - ZZZZ  : Flag position in the ISR register(4bits)
+  * @{
+  */
+#define UART_IT_PE                          0x0028U              /*!< UART parity error interruption                 */
+#define UART_IT_TXE                         0x0727U              /*!< UART transmit data register empty interruption */
+#define UART_IT_TXFNF                       0x0727U              /*!< UART TX FIFO not full interruption             */
+#define UART_IT_TC                          0x0626U              /*!< UART transmission complete interruption        */
+#define UART_IT_RXNE                        0x0525U              /*!< UART read data register not empty interruption */
+#define UART_IT_RXFNE                       0x0525U              /*!< UART RXFIFO not empty interruption             */
+#define UART_IT_IDLE                        0x0424U              /*!< UART idle interruption                         */
+#define UART_IT_LBD                         0x0846U              /*!< UART LIN break detection interruption          */
+#define UART_IT_CTS                         0x096AU              /*!< UART CTS interruption                          */
+#define UART_IT_CM                          0x112EU              /*!< UART character match interruption              */
+#define UART_IT_WUF                         0x1476U              /*!< UART wake-up from stop mode interruption       */
+#define UART_IT_RXFF                        0x183FU              /*!< UART RXFIFO full interruption                  */
+#define UART_IT_TXFE                        0x173EU              /*!< UART TXFIFO empty interruption                 */
+#define UART_IT_RXFT                        0x1A7CU              /*!< UART RXFIFO threshold reached interruption     */
+#define UART_IT_TXFT                        0x1B77U              /*!< UART TXFIFO threshold reached interruption     */
+#define UART_IT_RTO                         0x0B3AU              /*!< UART receiver timeout interruption             */
+
+#define UART_IT_ERR                         0x0060U              /*!< UART error interruption                        */
+
+#define UART_IT_ORE                         0x0300U              /*!< UART overrun error interruption                */
+#define UART_IT_NE                          0x0200U              /*!< UART noise error interruption                  */
+#define UART_IT_FE                          0x0100U              /*!< UART frame error interruption                  */
+/**
+  * @}
+  */
+
+/** @defgroup UART_IT_CLEAR_Flags  UART Interruption Clear Flags
+  * @{
+  */
+#define UART_CLEAR_PEF                       USART_ICR_PECF            /*!< Parity Error Clear Flag           */
+#define UART_CLEAR_FEF                       USART_ICR_FECF            /*!< Framing Error Clear Flag          */
+#define UART_CLEAR_NEF                       USART_ICR_NECF            /*!< Noise Error detected Clear Flag   */
+#define UART_CLEAR_OREF                      USART_ICR_ORECF           /*!< Overrun Error Clear Flag          */
+#define UART_CLEAR_IDLEF                     USART_ICR_IDLECF          /*!< IDLE line detected Clear Flag     */
+#define UART_CLEAR_TXFECF                    USART_ICR_TXFECF          /*!< TXFIFO empty clear flag           */
+#define UART_CLEAR_TCF                       USART_ICR_TCCF            /*!< Transmission Complete Clear Flag  */
+#define UART_CLEAR_LBDF                      USART_ICR_LBDCF           /*!< LIN Break Detection Clear Flag    */
+#define UART_CLEAR_CTSF                      USART_ICR_CTSCF           /*!< CTS Interrupt Clear Flag          */
+#define UART_CLEAR_CMF                       USART_ICR_CMCF            /*!< Character Match Clear Flag        */
+#define UART_CLEAR_WUF                       USART_ICR_WUCF            /*!< Wake Up from stop mode Clear Flag */
+#define UART_CLEAR_RTOF                      USART_ICR_RTOCF           /*!< UART receiver timeout clear flag  */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Reception_Type_Values  UART Reception type values
+  * @{
+  */
+#define HAL_UART_RECEPTION_STANDARD          (0x00000000U)             /*!< Standard reception                       */
+#define HAL_UART_RECEPTION_TOIDLE            (0x00000001U)             /*!< Reception till completion or IDLE event  */
+#define HAL_UART_RECEPTION_TORTO             (0x00000002U)             /*!< Reception till completion or RTO event   */
+#define HAL_UART_RECEPTION_TOCHARMATCH       (0x00000003U)             /*!< Reception till completion or CM event    */
+/**
+  * @}
+  */
+
+/** @defgroup UART_RxEvent_Type_Values  UART RxEvent type values
+  * @{
+  */
+#define HAL_UART_RXEVENT_TC                  (0x00000000U)             /*!< RxEvent linked to Transfer Complete event */
+#define HAL_UART_RXEVENT_HT                  (0x00000001U)             /*!< RxEvent linked to Half Transfer event     */
+#define HAL_UART_RXEVENT_IDLE                (0x00000002U)             /*!< RxEvent linked to IDLE event              */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup UART_Exported_Macros UART Exported Macros
+  * @{
+  */
+
+/** @brief  Reset UART handle states.
+  * @param  __HANDLE__ UART handle.
+  * @retval None
+  */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__)  do{                                                   \
+                                                       (__HANDLE__)->gState = HAL_UART_STATE_RESET;      \
+                                                       (__HANDLE__)->RxState = HAL_UART_STATE_RESET;     \
+                                                       (__HANDLE__)->MspInitCallback = NULL;             \
+                                                       (__HANDLE__)->MspDeInitCallback = NULL;           \
+                                                     } while(0U)
+#else
+#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__)  do{                                                   \
+                                                       (__HANDLE__)->gState = HAL_UART_STATE_RESET;      \
+                                                       (__HANDLE__)->RxState = HAL_UART_STATE_RESET;     \
+                                                     } while(0U)
+#endif /*USE_HAL_UART_REGISTER_CALLBACKS */
+
+/** @brief  Flush the UART Data registers.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @retval None
+  */
+#define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__)  \
+  do{                \
+    SET_BIT((__HANDLE__)->Instance->RQR, UART_RXDATA_FLUSH_REQUEST); \
+    SET_BIT((__HANDLE__)->Instance->RQR, UART_TXDATA_FLUSH_REQUEST); \
+  }  while(0U)
+
+/** @brief  Clear the specified UART pending flag.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @param  __FLAG__ specifies the flag to check.
+  *          This parameter can be any combination of the following values:
+  *            @arg @ref UART_CLEAR_PEF      Parity Error Clear Flag
+  *            @arg @ref UART_CLEAR_FEF      Framing Error Clear Flag
+  *            @arg @ref UART_CLEAR_NEF      Noise detected Clear Flag
+  *            @arg @ref UART_CLEAR_OREF     Overrun Error Clear Flag
+  *            @arg @ref UART_CLEAR_IDLEF    IDLE line detected Clear Flag
+  *            @arg @ref UART_CLEAR_TXFECF   TXFIFO empty clear Flag
+  *            @arg @ref UART_CLEAR_TCF      Transmission Complete Clear Flag
+  *            @arg @ref UART_CLEAR_RTOF     Receiver Timeout clear flag
+  *            @arg @ref UART_CLEAR_LBDF     LIN Break Detection Clear Flag
+  *            @arg @ref UART_CLEAR_CTSF     CTS Interrupt Clear Flag
+  *            @arg @ref UART_CLEAR_CMF      Character Match Clear Flag
+  *            @arg @ref UART_CLEAR_WUF      Wake Up from stop mode Clear Flag
+  * @retval None
+  */
+#define __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
+
+/** @brief  Clear the UART PE pending flag.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @retval None
+  */
+#define __HAL_UART_CLEAR_PEFLAG(__HANDLE__)   __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_PEF)
+
+/** @brief  Clear the UART FE pending flag.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @retval None
+  */
+#define __HAL_UART_CLEAR_FEFLAG(__HANDLE__)   __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_FEF)
+
+/** @brief  Clear the UART NE pending flag.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @retval None
+  */
+#define __HAL_UART_CLEAR_NEFLAG(__HANDLE__)  __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_NEF)
+
+/** @brief  Clear the UART ORE pending flag.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @retval None
+  */
+#define __HAL_UART_CLEAR_OREFLAG(__HANDLE__)   __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_OREF)
+
+/** @brief  Clear the UART IDLE pending flag.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @retval None
+  */
+#define __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__)   __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_IDLEF)
+
+/** @brief  Clear the UART TX FIFO empty clear flag.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @retval None
+  */
+#define __HAL_UART_CLEAR_TXFECF(__HANDLE__)   __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_TXFECF)
+
+/** @brief  Check whether the specified UART flag is set or not.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @param  __FLAG__ specifies the flag to check.
+  *        This parameter can be one of the following values:
+  *            @arg @ref UART_FLAG_TXFT  TXFIFO threshold flag
+  *            @arg @ref UART_FLAG_RXFT  RXFIFO threshold flag
+  *            @arg @ref UART_FLAG_RXFF  RXFIFO Full flag
+  *            @arg @ref UART_FLAG_TXFE  TXFIFO Empty flag
+  *            @arg @ref UART_FLAG_REACK Receive enable acknowledge flag
+  *            @arg @ref UART_FLAG_TEACK Transmit enable acknowledge flag
+  *            @arg @ref UART_FLAG_WUF   Wake up from stop mode flag
+  *            @arg @ref UART_FLAG_RWU   Receiver wake up flag (if the UART in mute mode)
+  *            @arg @ref UART_FLAG_SBKF  Send Break flag
+  *            @arg @ref UART_FLAG_CMF   Character match flag
+  *            @arg @ref UART_FLAG_BUSY  Busy flag
+  *            @arg @ref UART_FLAG_ABRF  Auto Baud rate detection flag
+  *            @arg @ref UART_FLAG_ABRE  Auto Baud rate detection error flag
+  *            @arg @ref UART_FLAG_CTS   CTS Change flag
+  *            @arg @ref UART_FLAG_LBDF  LIN Break detection flag
+  *            @arg @ref UART_FLAG_TXE   Transmit data register empty flag
+  *            @arg @ref UART_FLAG_TXFNF UART TXFIFO not full flag
+  *            @arg @ref UART_FLAG_TC    Transmission Complete flag
+  *            @arg @ref UART_FLAG_RXNE  Receive data register not empty flag
+  *            @arg @ref UART_FLAG_RXFNE UART RXFIFO not empty flag
+  *            @arg @ref UART_FLAG_RTOF  Receiver Timeout flag
+  *            @arg @ref UART_FLAG_IDLE  Idle Line detection flag
+  *            @arg @ref UART_FLAG_ORE   Overrun Error flag
+  *            @arg @ref UART_FLAG_NE    Noise Error flag
+  *            @arg @ref UART_FLAG_FE    Framing Error flag
+  *            @arg @ref UART_FLAG_PE    Parity Error flag
+  * @retval The new state of __FLAG__ (TRUE or FALSE).
+  */
+#define __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
+
+/** @brief  Enable the specified UART interrupt.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @param  __INTERRUPT__ specifies the UART interrupt source to enable.
+  *          This parameter can be one of the following values:
+  *            @arg @ref UART_IT_RXFF  RXFIFO Full interrupt
+  *            @arg @ref UART_IT_TXFE  TXFIFO Empty interrupt
+  *            @arg @ref UART_IT_RXFT  RXFIFO threshold interrupt
+  *            @arg @ref UART_IT_TXFT  TXFIFO threshold interrupt
+  *            @arg @ref UART_IT_WUF   Wakeup from stop mode interrupt
+  *            @arg @ref UART_IT_CM    Character match interrupt
+  *            @arg @ref UART_IT_CTS   CTS change interrupt
+  *            @arg @ref UART_IT_LBD   LIN Break detection interrupt
+  *            @arg @ref UART_IT_TXE   Transmit Data Register empty interrupt
+  *            @arg @ref UART_IT_TXFNF TX FIFO not full interrupt
+  *            @arg @ref UART_IT_TC    Transmission complete interrupt
+  *            @arg @ref UART_IT_RXNE  Receive Data register not empty interrupt
+  *            @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt
+  *            @arg @ref UART_IT_RTO   Receive Timeout interrupt
+  *            @arg @ref UART_IT_IDLE  Idle line detection interrupt
+  *            @arg @ref UART_IT_PE    Parity Error interrupt
+  *            @arg @ref UART_IT_ERR   Error interrupt (frame error, noise error, overrun error)
+  * @retval None
+  */
+#define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__)   (\
+                                                           ((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)?\
+                                                           ((__HANDLE__)->Instance->CR1 |= (1U <<\
+                                                               ((__INTERRUPT__) & UART_IT_MASK))): \
+                                                           ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)?\
+                                                           ((__HANDLE__)->Instance->CR2 |= (1U <<\
+                                                               ((__INTERRUPT__) & UART_IT_MASK))): \
+                                                           ((__HANDLE__)->Instance->CR3 |= (1U <<\
+                                                               ((__INTERRUPT__) & UART_IT_MASK))))
+
+/** @brief  Disable the specified UART interrupt.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @param  __INTERRUPT__ specifies the UART interrupt source to disable.
+  *          This parameter can be one of the following values:
+  *            @arg @ref UART_IT_RXFF  RXFIFO Full interrupt
+  *            @arg @ref UART_IT_TXFE  TXFIFO Empty interrupt
+  *            @arg @ref UART_IT_RXFT  RXFIFO threshold interrupt
+  *            @arg @ref UART_IT_TXFT  TXFIFO threshold interrupt
+  *            @arg @ref UART_IT_WUF   Wakeup from stop mode interrupt
+  *            @arg @ref UART_IT_CM    Character match interrupt
+  *            @arg @ref UART_IT_CTS   CTS change interrupt
+  *            @arg @ref UART_IT_LBD   LIN Break detection interrupt
+  *            @arg @ref UART_IT_TXE   Transmit Data Register empty interrupt
+  *            @arg @ref UART_IT_TXFNF TX FIFO not full interrupt
+  *            @arg @ref UART_IT_TC    Transmission complete interrupt
+  *            @arg @ref UART_IT_RXNE  Receive Data register not empty interrupt
+  *            @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt
+  *            @arg @ref UART_IT_RTO   Receive Timeout interrupt
+  *            @arg @ref UART_IT_IDLE  Idle line detection interrupt
+  *            @arg @ref UART_IT_PE    Parity Error interrupt
+  *            @arg @ref UART_IT_ERR   Error interrupt (Frame error, noise error, overrun error)
+  * @retval None
+  */
+#define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__)  (\
+                                                           ((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)?\
+                                                           ((__HANDLE__)->Instance->CR1 &= ~ (1U <<\
+                                                               ((__INTERRUPT__) & UART_IT_MASK))): \
+                                                           ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)?\
+                                                           ((__HANDLE__)->Instance->CR2 &= ~ (1U <<\
+                                                               ((__INTERRUPT__) & UART_IT_MASK))): \
+                                                           ((__HANDLE__)->Instance->CR3 &= ~ (1U <<\
+                                                               ((__INTERRUPT__) & UART_IT_MASK))))
+
+/** @brief  Check whether the specified UART interrupt has occurred or not.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @param  __INTERRUPT__ specifies the UART interrupt to check.
+  *          This parameter can be one of the following values:
+  *            @arg @ref UART_IT_RXFF  RXFIFO Full interrupt
+  *            @arg @ref UART_IT_TXFE  TXFIFO Empty interrupt
+  *            @arg @ref UART_IT_RXFT  RXFIFO threshold interrupt
+  *            @arg @ref UART_IT_TXFT  TXFIFO threshold interrupt
+  *            @arg @ref UART_IT_WUF   Wakeup from stop mode interrupt
+  *            @arg @ref UART_IT_CM    Character match interrupt
+  *            @arg @ref UART_IT_CTS   CTS change interrupt
+  *            @arg @ref UART_IT_LBD   LIN Break detection interrupt
+  *            @arg @ref UART_IT_TXE   Transmit Data Register empty interrupt
+  *            @arg @ref UART_IT_TXFNF TX FIFO not full interrupt
+  *            @arg @ref UART_IT_TC    Transmission complete interrupt
+  *            @arg @ref UART_IT_RXNE  Receive Data register not empty interrupt
+  *            @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt
+  *            @arg @ref UART_IT_RTO   Receive Timeout interrupt
+  *            @arg @ref UART_IT_IDLE  Idle line detection interrupt
+  *            @arg @ref UART_IT_PE    Parity Error interrupt
+  *            @arg @ref UART_IT_ERR   Error interrupt (Frame error, noise error, overrun error)
+  * @retval The new state of __INTERRUPT__ (SET or RESET).
+  */
+#define __HAL_UART_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\
+                                                        & (1U << ((__INTERRUPT__)>> 8U))) != RESET) ? SET : RESET)
+
+/** @brief  Check whether the specified UART interrupt source is enabled or not.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @param  __INTERRUPT__ specifies the UART interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg @ref UART_IT_RXFF  RXFIFO Full interrupt
+  *            @arg @ref UART_IT_TXFE  TXFIFO Empty interrupt
+  *            @arg @ref UART_IT_RXFT  RXFIFO threshold interrupt
+  *            @arg @ref UART_IT_TXFT  TXFIFO threshold interrupt
+  *            @arg @ref UART_IT_WUF   Wakeup from stop mode interrupt
+  *            @arg @ref UART_IT_CM    Character match interrupt
+  *            @arg @ref UART_IT_CTS   CTS change interrupt
+  *            @arg @ref UART_IT_LBD   LIN Break detection interrupt
+  *            @arg @ref UART_IT_TXE   Transmit Data Register empty interrupt
+  *            @arg @ref UART_IT_TXFNF TX FIFO not full interrupt
+  *            @arg @ref UART_IT_TC    Transmission complete interrupt
+  *            @arg @ref UART_IT_RXNE  Receive Data register not empty interrupt
+  *            @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt
+  *            @arg @ref UART_IT_RTO   Receive Timeout interrupt
+  *            @arg @ref UART_IT_IDLE  Idle line detection interrupt
+  *            @arg @ref UART_IT_PE    Parity Error interrupt
+  *            @arg @ref UART_IT_ERR   Error interrupt (Frame error, noise error, overrun error)
+  * @retval The new state of __INTERRUPT__ (SET or RESET).
+  */
+#define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U) ?\
+                                                                (__HANDLE__)->Instance->CR1 : \
+                                                                (((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U) ?\
+                                                                 (__HANDLE__)->Instance->CR2 : \
+                                                                 (__HANDLE__)->Instance->CR3)) & (1U <<\
+                                                                     (((uint16_t)(__INTERRUPT__)) &\
+                                                                      UART_IT_MASK)))  != RESET) ? SET : RESET)
+
+/** @brief  Clear the specified UART ISR flag, in setting the proper ICR register flag.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @param  __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set
+  *                       to clear the corresponding interrupt
+  *          This parameter can be one of the following values:
+  *            @arg @ref UART_CLEAR_PEF    Parity Error Clear Flag
+  *            @arg @ref UART_CLEAR_FEF    Framing Error Clear Flag
+  *            @arg @ref UART_CLEAR_NEF    Noise detected Clear Flag
+  *            @arg @ref UART_CLEAR_OREF   Overrun Error Clear Flag
+  *            @arg @ref UART_CLEAR_IDLEF  IDLE line detected Clear Flag
+  *            @arg @ref UART_CLEAR_RTOF   Receiver timeout clear flag
+  *            @arg @ref UART_CLEAR_TXFECF TXFIFO empty Clear Flag
+  *            @arg @ref UART_CLEAR_TCF    Transmission Complete Clear Flag
+  *            @arg @ref UART_CLEAR_LBDF   LIN Break Detection Clear Flag
+  *            @arg @ref UART_CLEAR_CTSF   CTS Interrupt Clear Flag
+  *            @arg @ref UART_CLEAR_CMF    Character Match Clear Flag
+  *            @arg @ref UART_CLEAR_WUF    Wake Up from stop mode Clear Flag
+  * @retval None
+  */
+#define __HAL_UART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
+
+/** @brief  Set a specific UART request flag.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @param  __REQ__ specifies the request flag to set
+  *          This parameter can be one of the following values:
+  *            @arg @ref UART_AUTOBAUD_REQUEST Auto-Baud Rate Request
+  *            @arg @ref UART_SENDBREAK_REQUEST Send Break Request
+  *            @arg @ref UART_MUTE_MODE_REQUEST Mute Mode Request
+  *            @arg @ref UART_RXDATA_FLUSH_REQUEST Receive Data flush Request
+  *            @arg @ref UART_TXDATA_FLUSH_REQUEST Transmit data flush Request
+  * @retval None
+  */
+#define __HAL_UART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
+
+/** @brief  Enable the UART one bit sample method.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @retval None
+  */
+#define __HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
+
+/** @brief  Disable the UART one bit sample method.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @retval None
+  */
+#define __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= ~USART_CR3_ONEBIT)
+
+/** @brief  Enable UART.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @retval None
+  */
+#define __HAL_UART_ENABLE(__HANDLE__)                   ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
+
+/** @brief  Disable UART.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @retval None
+  */
+#define __HAL_UART_DISABLE(__HANDLE__)                  ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
+
+/** @brief  Enable CTS flow control.
+  * @note   This macro allows to enable CTS hardware flow control for a given UART instance,
+  *         without need to call HAL_UART_Init() function.
+  *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
+  * @note   As macro is expected to be used for modifying CTS Hw flow control feature activation, without need
+  *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
+  *           - UART instance should have already been initialised (through call of HAL_UART_Init() )
+  *           - macro could only be called when corresponding UART instance is disabled
+  *             (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable
+  *              macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @retval None
+  */
+#define __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__)               \
+  do{                                                             \
+    ATOMIC_SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE);  \
+    (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_CTSE;               \
+  } while(0U)
+
+/** @brief  Disable CTS flow control.
+  * @note   This macro allows to disable CTS hardware flow control for a given UART instance,
+  *         without need to call HAL_UART_Init() function.
+  *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
+  * @note   As macro is expected to be used for modifying CTS Hw flow control feature activation, without need
+  *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
+  *           - UART instance should have already been initialised (through call of HAL_UART_Init() )
+  *           - macro could only be called when corresponding UART instance is disabled
+  *             (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable
+  *              macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @retval None
+  */
+#define __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__)               \
+  do{                                                              \
+    ATOMIC_CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \
+    (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE);             \
+  } while(0U)
+
+/** @brief  Enable RTS flow control.
+  * @note   This macro allows to enable RTS hardware flow control for a given UART instance,
+  *         without need to call HAL_UART_Init() function.
+  *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
+  * @note   As macro is expected to be used for modifying RTS Hw flow control feature activation, without need
+  *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
+  *           - UART instance should have already been initialised (through call of HAL_UART_Init() )
+  *           - macro could only be called when corresponding UART instance is disabled
+  *             (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable
+  *              macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @retval None
+  */
+#define __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__)              \
+  do{                                                            \
+    ATOMIC_SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \
+    (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_RTSE;              \
+  } while(0U)
+
+/** @brief  Disable RTS flow control.
+  * @note   This macro allows to disable RTS hardware flow control for a given UART instance,
+  *         without need to call HAL_UART_Init() function.
+  *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
+  * @note   As macro is expected to be used for modifying RTS Hw flow control feature activation, without need
+  *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
+  *           - UART instance should have already been initialised (through call of HAL_UART_Init() )
+  *           - macro could only be called when corresponding UART instance is disabled
+  *             (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable
+  *              macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @retval None
+  */
+#define __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__)              \
+  do{                                                             \
+    ATOMIC_CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\
+    (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE);            \
+  } while(0U)
+/**
+  * @}
+  */
+
+/* Private macros --------------------------------------------------------*/
+/** @defgroup UART_Private_Macros   UART Private Macros
+  * @{
+  */
+/** @brief  Get UART clok division factor from clock prescaler value.
+  * @param  __CLOCKPRESCALER__ UART prescaler value.
+  * @retval UART clock division factor
+  */
+#define UART_GET_DIV_FACTOR(__CLOCKPRESCALER__) \
+  (((__CLOCKPRESCALER__) == UART_PRESCALER_DIV1)   ? 1U :       \
+   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV2)   ? 2U :       \
+   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV4)   ? 4U :       \
+   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV6)   ? 6U :       \
+   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV8)   ? 8U :       \
+   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV10)  ? 10U :      \
+   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV12)  ? 12U :      \
+   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV16)  ? 16U :      \
+   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV32)  ? 32U :      \
+   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV64)  ? 64U :      \
+   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV128) ? 128U :     \
+   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV256) ? 256U : 1U)
+
+/** @brief  BRR division operation to set BRR register with LPUART.
+  * @param  __PCLK__ LPUART clock.
+  * @param  __BAUD__ Baud rate set by the user.
+  * @param  __CLOCKPRESCALER__ UART prescaler value.
+  * @retval Division result
+  */
+#define UART_DIV_LPUART(__PCLK__, __BAUD__, __CLOCKPRESCALER__)                        \
+  ((uint32_t)((((((uint64_t)(__PCLK__))/(UARTPrescTable[(__CLOCKPRESCALER__)]))*256U)+ \
+               (uint32_t)((__BAUD__)/2U)) / (__BAUD__))                                \
+  )
+
+/** @brief  BRR division operation to set BRR register in 8-bit oversampling mode.
+  * @param  __PCLK__ UART clock.
+  * @param  __BAUD__ Baud rate set by the user.
+  * @param  __CLOCKPRESCALER__ UART prescaler value.
+  * @retval Division result
+  */
+#define UART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__)                        \
+  (((((__PCLK__)/UARTPrescTable[(__CLOCKPRESCALER__)])*2U) + ((__BAUD__)/2U)) / (__BAUD__))
+
+/** @brief  BRR division operation to set BRR register in 16-bit oversampling mode.
+  * @param  __PCLK__ UART clock.
+  * @param  __BAUD__ Baud rate set by the user.
+  * @param  __CLOCKPRESCALER__ UART prescaler value.
+  * @retval Division result
+  */
+#define UART_DIV_SAMPLING16(__PCLK__, __BAUD__, __CLOCKPRESCALER__)                       \
+  ((((__PCLK__)/UARTPrescTable[(__CLOCKPRESCALER__)]) + ((__BAUD__)/2U)) / (__BAUD__))
+
+/** @brief  Check whether or not UART instance is Low Power UART.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @retval SET (instance is LPUART) or RESET (instance isn't LPUART)
+  */
+#define UART_INSTANCE_LOWPOWER(__HANDLE__) (IS_LPUART_INSTANCE((__HANDLE__)->Instance))
+
+/** @brief  Check UART Baud rate.
+  * @param  __BAUDRATE__ Baudrate specified by the user.
+  *         The maximum Baud Rate is derived from the maximum clock on H7 (i.e. 100 MHz)
+  *         divided by the smallest oversampling used on the USART (i.e. 8)
+  * @retval SET (__BAUDRATE__ is valid) or RESET (__BAUDRATE__ is invalid)
+  */
+#define IS_UART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 12500001U)
+
+/** @brief  Check UART assertion time.
+  * @param  __TIME__ 5-bit value assertion time.
+  * @retval Test result (TRUE or FALSE).
+  */
+#define IS_UART_ASSERTIONTIME(__TIME__)    ((__TIME__) <= 0x1FU)
+
+/** @brief  Check UART deassertion time.
+  * @param  __TIME__ 5-bit value deassertion time.
+  * @retval Test result (TRUE or FALSE).
+  */
+#define IS_UART_DEASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1FU)
+
+/**
+  * @brief Ensure that UART frame number of stop bits is valid.
+  * @param __STOPBITS__ UART frame number of stop bits.
+  * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)
+  */
+#define IS_UART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == UART_STOPBITS_0_5) || \
+                                        ((__STOPBITS__) == UART_STOPBITS_1)   || \
+                                        ((__STOPBITS__) == UART_STOPBITS_1_5) || \
+                                        ((__STOPBITS__) == UART_STOPBITS_2))
+
+/**
+  * @brief Ensure that LPUART frame number of stop bits is valid.
+  * @param __STOPBITS__ LPUART frame number of stop bits.
+  * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)
+  */
+#define IS_LPUART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == UART_STOPBITS_1) || \
+                                          ((__STOPBITS__) == UART_STOPBITS_2))
+
+/**
+  * @brief Ensure that UART frame parity is valid.
+  * @param __PARITY__ UART frame parity.
+  * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)
+  */
+#define IS_UART_PARITY(__PARITY__) (((__PARITY__) == UART_PARITY_NONE) || \
+                                    ((__PARITY__) == UART_PARITY_EVEN) || \
+                                    ((__PARITY__) == UART_PARITY_ODD))
+
+/**
+  * @brief Ensure that UART hardware flow control is valid.
+  * @param __CONTROL__ UART hardware flow control.
+  * @retval SET (__CONTROL__ is valid) or RESET (__CONTROL__ is invalid)
+  */
+#define IS_UART_HARDWARE_FLOW_CONTROL(__CONTROL__)\
+  (((__CONTROL__) == UART_HWCONTROL_NONE) || \
+   ((__CONTROL__) == UART_HWCONTROL_RTS)  || \
+   ((__CONTROL__) == UART_HWCONTROL_CTS)  || \
+   ((__CONTROL__) == UART_HWCONTROL_RTS_CTS))
+
+/**
+  * @brief Ensure that UART communication mode is valid.
+  * @param __MODE__ UART communication mode.
+  * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
+  */
+#define IS_UART_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(UART_MODE_TX_RX)))) == 0x00U) && ((__MODE__) != 0x00U))
+
+/**
+  * @brief Ensure that UART state is valid.
+  * @param __STATE__ UART state.
+  * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid)
+  */
+#define IS_UART_STATE(__STATE__) (((__STATE__) == UART_STATE_DISABLE) || \
+                                  ((__STATE__) == UART_STATE_ENABLE))
+
+/**
+  * @brief Ensure that UART oversampling is valid.
+  * @param __SAMPLING__ UART oversampling.
+  * @retval SET (__SAMPLING__ is valid) or RESET (__SAMPLING__ is invalid)
+  */
+#define IS_UART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == UART_OVERSAMPLING_16) || \
+                                            ((__SAMPLING__) == UART_OVERSAMPLING_8))
+
+/**
+  * @brief Ensure that UART frame sampling is valid.
+  * @param __ONEBIT__ UART frame sampling.
+  * @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid)
+  */
+#define IS_UART_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == UART_ONE_BIT_SAMPLE_DISABLE) || \
+                                            ((__ONEBIT__) == UART_ONE_BIT_SAMPLE_ENABLE))
+
+/**
+  * @brief Ensure that UART auto Baud rate detection mode is valid.
+  * @param __MODE__ UART auto Baud rate detection mode.
+  * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
+  */
+#define IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(__MODE__)  (((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT)    || \
+                                                        ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE) || \
+                                                        ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME)   || \
+                                                        ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME))
+
+/**
+  * @brief Ensure that UART receiver timeout setting is valid.
+  * @param __TIMEOUT__ UART receiver timeout setting.
+  * @retval SET (__TIMEOUT__ is valid) or RESET (__TIMEOUT__ is invalid)
+  */
+#define IS_UART_RECEIVER_TIMEOUT(__TIMEOUT__)  (((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_DISABLE) || \
+                                                ((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_ENABLE))
+
+/** @brief  Check the receiver timeout value.
+  * @note   The maximum UART receiver timeout value is 0xFFFFFF.
+  * @param  __TIMEOUTVALUE__ receiver timeout value.
+  * @retval Test result (TRUE or FALSE)
+  */
+#define IS_UART_RECEIVER_TIMEOUT_VALUE(__TIMEOUTVALUE__)  ((__TIMEOUTVALUE__) <= 0xFFFFFFU)
+
+/**
+  * @brief Ensure that UART LIN state is valid.
+  * @param __LIN__ UART LIN state.
+  * @retval SET (__LIN__ is valid) or RESET (__LIN__ is invalid)
+  */
+#define IS_UART_LIN(__LIN__)        (((__LIN__) == UART_LIN_DISABLE) || \
+                                     ((__LIN__) == UART_LIN_ENABLE))
+
+/**
+  * @brief Ensure that UART LIN break detection length is valid.
+  * @param __LENGTH__ UART LIN break detection length.
+  * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
+  */
+#define IS_UART_LIN_BREAK_DETECT_LENGTH(__LENGTH__) (((__LENGTH__) == UART_LINBREAKDETECTLENGTH_10B) || \
+                                                     ((__LENGTH__) == UART_LINBREAKDETECTLENGTH_11B))
+
+/**
+  * @brief Ensure that UART DMA TX state is valid.
+  * @param __DMATX__ UART DMA TX state.
+  * @retval SET (__DMATX__ is valid) or RESET (__DMATX__ is invalid)
+  */
+#define IS_UART_DMA_TX(__DMATX__)     (((__DMATX__) == UART_DMA_TX_DISABLE) || \
+                                       ((__DMATX__) == UART_DMA_TX_ENABLE))
+
+/**
+  * @brief Ensure that UART DMA RX state is valid.
+  * @param __DMARX__ UART DMA RX state.
+  * @retval SET (__DMARX__ is valid) or RESET (__DMARX__ is invalid)
+  */
+#define IS_UART_DMA_RX(__DMARX__)     (((__DMARX__) == UART_DMA_RX_DISABLE) || \
+                                       ((__DMARX__) == UART_DMA_RX_ENABLE))
+
+/**
+  * @brief Ensure that UART half-duplex state is valid.
+  * @param __HDSEL__ UART half-duplex state.
+  * @retval SET (__HDSEL__ is valid) or RESET (__HDSEL__ is invalid)
+  */
+#define IS_UART_HALF_DUPLEX(__HDSEL__)     (((__HDSEL__) == UART_HALF_DUPLEX_DISABLE) || \
+                                            ((__HDSEL__) == UART_HALF_DUPLEX_ENABLE))
+
+/**
+  * @brief Ensure that UART wake-up method is valid.
+  * @param __WAKEUP__ UART wake-up method .
+  * @retval SET (__WAKEUP__ is valid) or RESET (__WAKEUP__ is invalid)
+  */
+#define IS_UART_WAKEUPMETHOD(__WAKEUP__) (((__WAKEUP__) == UART_WAKEUPMETHOD_IDLELINE) || \
+                                          ((__WAKEUP__) == UART_WAKEUPMETHOD_ADDRESSMARK))
+
+/**
+  * @brief Ensure that UART request parameter is valid.
+  * @param __PARAM__ UART request parameter.
+  * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)
+  */
+#define IS_UART_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == UART_AUTOBAUD_REQUEST)     || \
+                                              ((__PARAM__) == UART_SENDBREAK_REQUEST)    || \
+                                              ((__PARAM__) == UART_MUTE_MODE_REQUEST)    || \
+                                              ((__PARAM__) == UART_RXDATA_FLUSH_REQUEST) || \
+                                              ((__PARAM__) == UART_TXDATA_FLUSH_REQUEST))
+
+/**
+  * @brief Ensure that UART advanced features initialization is valid.
+  * @param __INIT__ UART advanced features initialization.
+  * @retval SET (__INIT__ is valid) or RESET (__INIT__ is invalid)
+  */
+#define IS_UART_ADVFEATURE_INIT(__INIT__)   ((__INIT__) <= (UART_ADVFEATURE_NO_INIT                | \
+                                                            UART_ADVFEATURE_TXINVERT_INIT          | \
+                                                            UART_ADVFEATURE_RXINVERT_INIT          | \
+                                                            UART_ADVFEATURE_DATAINVERT_INIT        | \
+                                                            UART_ADVFEATURE_SWAP_INIT              | \
+                                                            UART_ADVFEATURE_RXOVERRUNDISABLE_INIT  | \
+                                                            UART_ADVFEATURE_DMADISABLEONERROR_INIT | \
+                                                            UART_ADVFEATURE_AUTOBAUDRATE_INIT      | \
+                                                            UART_ADVFEATURE_MSBFIRST_INIT))
+
+/**
+  * @brief Ensure that UART frame TX inversion setting is valid.
+  * @param __TXINV__ UART frame TX inversion setting.
+  * @retval SET (__TXINV__ is valid) or RESET (__TXINV__ is invalid)
+  */
+#define IS_UART_ADVFEATURE_TXINV(__TXINV__) (((__TXINV__) == UART_ADVFEATURE_TXINV_DISABLE) || \
+                                             ((__TXINV__) == UART_ADVFEATURE_TXINV_ENABLE))
+
+/**
+  * @brief Ensure that UART frame RX inversion setting is valid.
+  * @param __RXINV__ UART frame RX inversion setting.
+  * @retval SET (__RXINV__ is valid) or RESET (__RXINV__ is invalid)
+  */
+#define IS_UART_ADVFEATURE_RXINV(__RXINV__) (((__RXINV__) == UART_ADVFEATURE_RXINV_DISABLE) || \
+                                             ((__RXINV__) == UART_ADVFEATURE_RXINV_ENABLE))
+
+/**
+  * @brief Ensure that UART frame data inversion setting is valid.
+  * @param __DATAINV__ UART frame data inversion setting.
+  * @retval SET (__DATAINV__ is valid) or RESET (__DATAINV__ is invalid)
+  */
+#define IS_UART_ADVFEATURE_DATAINV(__DATAINV__) (((__DATAINV__) == UART_ADVFEATURE_DATAINV_DISABLE) || \
+                                                 ((__DATAINV__) == UART_ADVFEATURE_DATAINV_ENABLE))
+
+/**
+  * @brief Ensure that UART frame RX/TX pins swap setting is valid.
+  * @param __SWAP__ UART frame RX/TX pins swap setting.
+  * @retval SET (__SWAP__ is valid) or RESET (__SWAP__ is invalid)
+  */
+#define IS_UART_ADVFEATURE_SWAP(__SWAP__) (((__SWAP__) == UART_ADVFEATURE_SWAP_DISABLE) || \
+                                           ((__SWAP__) == UART_ADVFEATURE_SWAP_ENABLE))
+
+/**
+  * @brief Ensure that UART frame overrun setting is valid.
+  * @param __OVERRUN__ UART frame overrun setting.
+  * @retval SET (__OVERRUN__ is valid) or RESET (__OVERRUN__ is invalid)
+  */
+#define IS_UART_OVERRUN(__OVERRUN__)     (((__OVERRUN__) == UART_ADVFEATURE_OVERRUN_ENABLE) || \
+                                          ((__OVERRUN__) == UART_ADVFEATURE_OVERRUN_DISABLE))
+
+/**
+  * @brief Ensure that UART auto Baud rate state is valid.
+  * @param __AUTOBAUDRATE__ UART auto Baud rate state.
+  * @retval SET (__AUTOBAUDRATE__ is valid) or RESET (__AUTOBAUDRATE__ is invalid)
+  */
+#define IS_UART_ADVFEATURE_AUTOBAUDRATE(__AUTOBAUDRATE__) (((__AUTOBAUDRATE__) == \
+                                                            UART_ADVFEATURE_AUTOBAUDRATE_DISABLE) || \
+                                                           ((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE))
+
+/**
+  * @brief Ensure that UART DMA enabling or disabling on error setting is valid.
+  * @param __DMA__ UART DMA enabling or disabling on error setting.
+  * @retval SET (__DMA__ is valid) or RESET (__DMA__ is invalid)
+  */
+#define IS_UART_ADVFEATURE_DMAONRXERROR(__DMA__)  (((__DMA__) == UART_ADVFEATURE_DMA_ENABLEONRXERROR) || \
+                                                   ((__DMA__) == UART_ADVFEATURE_DMA_DISABLEONRXERROR))
+
+/**
+  * @brief Ensure that UART frame MSB first setting is valid.
+  * @param __MSBFIRST__ UART frame MSB first setting.
+  * @retval SET (__MSBFIRST__ is valid) or RESET (__MSBFIRST__ is invalid)
+  */
+#define IS_UART_ADVFEATURE_MSBFIRST(__MSBFIRST__) (((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_DISABLE) || \
+                                                   ((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_ENABLE))
+
+/**
+  * @brief Ensure that UART stop mode state is valid.
+  * @param __STOPMODE__ UART stop mode state.
+  * @retval SET (__STOPMODE__ is valid) or RESET (__STOPMODE__ is invalid)
+  */
+#define IS_UART_ADVFEATURE_STOPMODE(__STOPMODE__) (((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_DISABLE) || \
+                                                   ((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_ENABLE))
+
+/**
+  * @brief Ensure that UART mute mode state is valid.
+  * @param __MUTE__ UART mute mode state.
+  * @retval SET (__MUTE__ is valid) or RESET (__MUTE__ is invalid)
+  */
+#define IS_UART_MUTE_MODE(__MUTE__)       (((__MUTE__) == UART_ADVFEATURE_MUTEMODE_DISABLE) || \
+                                           ((__MUTE__) == UART_ADVFEATURE_MUTEMODE_ENABLE))
+
+/**
+  * @brief Ensure that UART wake-up selection is valid.
+  * @param __WAKE__ UART wake-up selection.
+  * @retval SET (__WAKE__ is valid) or RESET (__WAKE__ is invalid)
+  */
+#define IS_UART_WAKEUP_SELECTION(__WAKE__) (((__WAKE__) == UART_WAKEUP_ON_ADDRESS)           || \
+                                            ((__WAKE__) == UART_WAKEUP_ON_STARTBIT)          || \
+                                            ((__WAKE__) == UART_WAKEUP_ON_READDATA_NONEMPTY))
+
+/**
+  * @brief Ensure that UART driver enable polarity is valid.
+  * @param __POLARITY__ UART driver enable polarity.
+  * @retval SET (__POLARITY__ is valid) or RESET (__POLARITY__ is invalid)
+  */
+#define IS_UART_DE_POLARITY(__POLARITY__)    (((__POLARITY__) == UART_DE_POLARITY_HIGH) || \
+                                              ((__POLARITY__) == UART_DE_POLARITY_LOW))
+
+/**
+  * @brief Ensure that UART Prescaler is valid.
+  * @param __CLOCKPRESCALER__ UART Prescaler value.
+  * @retval SET (__CLOCKPRESCALER__ is valid) or RESET (__CLOCKPRESCALER__ is invalid)
+  */
+#define IS_UART_PRESCALER(__CLOCKPRESCALER__) (((__CLOCKPRESCALER__) == UART_PRESCALER_DIV1)   || \
+                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV2)   || \
+                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV4)   || \
+                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV6)   || \
+                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV8)   || \
+                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV10)  || \
+                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV12)  || \
+                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV16)  || \
+                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV32)  || \
+                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV64)  || \
+                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV128) || \
+                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV256))
+
+/**
+  * @}
+  */
+
+/* Include UART HAL Extended module */
+#include "stm32h7xx_hal_uart_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup UART_Exported_Functions UART Exported Functions
+  * @{
+  */
+
+/** @addtogroup UART_Exported_Functions_Group1 Initialization and de-initialization functions
+  * @{
+  */
+
+/* Initialization and de-initialization functions  ****************************/
+HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength);
+HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod);
+HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart);
+void HAL_UART_MspInit(UART_HandleTypeDef *huart);
+void HAL_UART_MspDeInit(UART_HandleTypeDef *huart);
+
+/* Callbacks Register/UnRegister functions  ***********************************/
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID,
+                                            pUART_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID);
+
+HAL_StatusTypeDef HAL_UART_RegisterRxEventCallback(UART_HandleTypeDef *huart, pUART_RxEventCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/** @addtogroup UART_Exported_Functions_Group2 IO operation functions
+  * @{
+  */
+
+/* IO operation functions *****************************************************/
+HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart);
+/* Transfer Abort functions */
+HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart);
+
+void HAL_UART_IRQHandler(UART_HandleTypeDef *huart);
+void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart);
+void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart);
+void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart);
+void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart);
+void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart);
+void HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart);
+void HAL_UART_AbortTransmitCpltCallback(UART_HandleTypeDef *huart);
+void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart);
+
+void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size);
+
+/**
+  * @}
+  */
+
+/** @addtogroup UART_Exported_Functions_Group3 Peripheral Control functions
+  * @{
+  */
+
+/* Peripheral Control functions  ************************************************/
+void HAL_UART_ReceiverTimeout_Config(UART_HandleTypeDef *huart, uint32_t TimeoutValue);
+HAL_StatusTypeDef HAL_UART_EnableReceiverTimeout(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_DisableReceiverTimeout(UART_HandleTypeDef *huart);
+
+HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart);
+void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart);
+
+/**
+  * @}
+  */
+
+/** @addtogroup UART_Exported_Functions_Group4 Peripheral State and Error functions
+  * @{
+  */
+
+/* Peripheral State and Errors functions  **************************************************/
+HAL_UART_StateTypeDef HAL_UART_GetState(const UART_HandleTypeDef *huart);
+uint32_t              HAL_UART_GetError(const UART_HandleTypeDef *huart);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private functions -----------------------------------------------------------*/
+/** @addtogroup UART_Private_Functions UART Private Functions
+  * @{
+  */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+void              UART_InitCallbacksToDefault(UART_HandleTypeDef *huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status,
+                                              uint32_t Tickstart, uint32_t Timeout);
+void              UART_AdvFeatureConfig(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
+
+/**
+  * @}
+  */
+
+/* Private variables -----------------------------------------------------------*/
+/** @defgroup UART_Private_variables UART Private variables
+  * @{
+  */
+/* Prescaler Table used in BRR computation macros.
+   Declared as extern here to allow use of private UART macros, outside of HAL UART functions */
+extern const uint16_t UARTPrescTable[12];
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32H7xx_HAL_UART_H */
+
diff --git a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h
new file mode 100644
index 0000000..a9415bc
--- /dev/null
+++ b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h
@@ -0,0 +1,870 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_uart_ex.h
+  * @author  MCD Application Team
+  * @brief   Header file of UART HAL Extended module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_HAL_UART_EX_H
+#define STM32H7xx_HAL_UART_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal_def.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup UARTEx
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup UARTEx_Exported_Types UARTEx Exported Types
+  * @{
+  */
+
+/**
+  * @brief  UART wake up from stop mode parameters
+  */
+typedef struct
+{
+  uint32_t WakeUpEvent;        /*!< Specifies which event will activate the Wakeup from Stop mode flag (WUF).
+                                    This parameter can be a value of @ref UART_WakeUp_from_Stop_Selection.
+                                    If set to UART_WAKEUP_ON_ADDRESS, the two other fields below must
+                                    be filled up. */
+
+  uint16_t AddressLength;      /*!< Specifies whether the address is 4 or 7-bit long.
+                                    This parameter can be a value of @ref UARTEx_WakeUp_Address_Length.  */
+
+  uint8_t Address;             /*!< UART/USART node address (7-bit long max). */
+} UART_WakeUpTypeDef;
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup UARTEx_Exported_Constants UARTEx Exported Constants
+  * @{
+  */
+
+/** @defgroup UARTEx_Word_Length UARTEx Word Length
+  * @{
+  */
+#define UART_WORDLENGTH_7B          USART_CR1_M1   /*!< 7-bit long UART frame */
+#define UART_WORDLENGTH_8B          0x00000000U    /*!< 8-bit long UART frame */
+#define UART_WORDLENGTH_9B          USART_CR1_M0   /*!< 9-bit long UART frame */
+/**
+  * @}
+  */
+
+/** @defgroup UARTEx_WakeUp_Address_Length UARTEx WakeUp Address Length
+  * @{
+  */
+#define UART_ADDRESS_DETECT_4B      0x00000000U      /*!< 4-bit long wake-up address */
+#define UART_ADDRESS_DETECT_7B      USART_CR2_ADDM7  /*!< 7-bit long wake-up address */
+/**
+  * @}
+  */
+
+/** @defgroup UARTEx_FIFO_mode UARTEx FIFO mode
+  * @brief    UART FIFO mode
+  * @{
+  */
+#define UART_FIFOMODE_DISABLE       0x00000000U       /*!< FIFO mode disable */
+#define UART_FIFOMODE_ENABLE        USART_CR1_FIFOEN  /*!< FIFO mode enable  */
+/**
+  * @}
+  */
+
+/** @defgroup UARTEx_TXFIFO_threshold_level UARTEx TXFIFO threshold level
+  * @brief    UART TXFIFO threshold level
+  * @{
+  */
+#define UART_TXFIFO_THRESHOLD_1_8   0x00000000U                               /*!< TX FIFO reaches 1/8 of its depth */
+#define UART_TXFIFO_THRESHOLD_1_4   USART_CR3_TXFTCFG_0                       /*!< TX FIFO reaches 1/4 of its depth */
+#define UART_TXFIFO_THRESHOLD_1_2   USART_CR3_TXFTCFG_1                       /*!< TX FIFO reaches 1/2 of its depth */
+#define UART_TXFIFO_THRESHOLD_3_4   (USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1) /*!< TX FIFO reaches 3/4 of its depth */
+#define UART_TXFIFO_THRESHOLD_7_8   USART_CR3_TXFTCFG_2                       /*!< TX FIFO reaches 7/8 of its depth */
+#define UART_TXFIFO_THRESHOLD_8_8   (USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0) /*!< TX FIFO becomes empty            */
+/**
+  * @}
+  */
+
+/** @defgroup UARTEx_RXFIFO_threshold_level UARTEx RXFIFO threshold level
+  * @brief    UART RXFIFO threshold level
+  * @{
+  */
+#define UART_RXFIFO_THRESHOLD_1_8   0x00000000U                               /*!< RX FIFO reaches 1/8 of its depth */
+#define UART_RXFIFO_THRESHOLD_1_4   USART_CR3_RXFTCFG_0                       /*!< RX FIFO reaches 1/4 of its depth */
+#define UART_RXFIFO_THRESHOLD_1_2   USART_CR3_RXFTCFG_1                       /*!< RX FIFO reaches 1/2 of its depth */
+#define UART_RXFIFO_THRESHOLD_3_4   (USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1) /*!< RX FIFO reaches 3/4 of its depth */
+#define UART_RXFIFO_THRESHOLD_7_8   USART_CR3_RXFTCFG_2                       /*!< RX FIFO reaches 7/8 of its depth */
+#define UART_RXFIFO_THRESHOLD_8_8   (USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0) /*!< RX FIFO becomes full             */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup UARTEx_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup UARTEx_Exported_Functions_Group1
+  * @{
+  */
+
+/* Initialization and de-initialization functions  ****************************/
+HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime,
+                                   uint32_t DeassertionTime);
+
+/**
+  * @}
+  */
+
+/** @addtogroup UARTEx_Exported_Functions_Group2
+  * @{
+  */
+
+void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart);
+
+void HAL_UARTEx_RxFifoFullCallback(UART_HandleTypeDef *huart);
+void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart);
+
+/**
+  * @}
+  */
+
+/** @addtogroup UARTEx_Exported_Functions_Group3
+  * @{
+  */
+
+/* Peripheral Control functions  **********************************************/
+HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection);
+HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart);
+
+HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength);
+
+HAL_StatusTypeDef HAL_UARTEx_EnableFifoMode(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold);
+HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold);
+
+HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen,
+                                           uint32_t Timeout);
+HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
+
+HAL_UART_RxEventTypeTypeDef HAL_UARTEx_GetRxEventType(UART_HandleTypeDef *huart);
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup UARTEx_Private_Macros UARTEx Private Macros
+  * @{
+  */
+
+/** @brief  Report the UART clock source.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @param  __CLOCKSOURCE__ output variable.
+  * @retval UART clocking source, written in __CLOCKSOURCE__.
+  */
+#if defined(UART9) && defined(USART10)
+#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)       \
+  do {                                                        \
+    if((__HANDLE__)->Instance == USART1)                      \
+    {                                                         \
+      switch(__HAL_RCC_GET_USART1_SOURCE())                   \
+      {                                                       \
+        case RCC_USART1CLKSOURCE_D2PCLK2:                     \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK2;       \
+          break;                                              \
+        case RCC_USART1CLKSOURCE_PLL2:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2;          \
+          break;                                              \
+        case RCC_USART1CLKSOURCE_PLL3:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3;          \
+          break;                                              \
+        case RCC_USART1CLKSOURCE_HSI:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_USART1CLKSOURCE_CSI:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI;           \
+          break;                                              \
+        case RCC_USART1CLKSOURCE_LSE:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
+    else if((__HANDLE__)->Instance == USART2)                 \
+    {                                                         \
+      switch(__HAL_RCC_GET_USART2_SOURCE())                   \
+      {                                                       \
+        case RCC_USART2CLKSOURCE_D2PCLK1:                     \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK1;       \
+          break;                                              \
+        case RCC_USART2CLKSOURCE_PLL2:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2;          \
+          break;                                              \
+        case RCC_USART2CLKSOURCE_PLL3:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3;          \
+          break;                                              \
+        case RCC_USART2CLKSOURCE_HSI:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_USART2CLKSOURCE_CSI:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI;           \
+          break;                                              \
+        case RCC_USART2CLKSOURCE_LSE:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
+    else if((__HANDLE__)->Instance == USART3)                 \
+    {                                                         \
+      switch(__HAL_RCC_GET_USART3_SOURCE())                   \
+      {                                                       \
+        case RCC_USART3CLKSOURCE_D2PCLK1:                     \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK1;       \
+          break;                                              \
+        case RCC_USART3CLKSOURCE_PLL2:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2;          \
+          break;                                              \
+        case RCC_USART3CLKSOURCE_PLL3:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3;          \
+          break;                                              \
+        case RCC_USART3CLKSOURCE_HSI:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_USART3CLKSOURCE_CSI:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI;           \
+          break;                                              \
+        case RCC_USART3CLKSOURCE_LSE:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
+    else if((__HANDLE__)->Instance == UART4)                  \
+    {                                                         \
+      switch(__HAL_RCC_GET_UART4_SOURCE())                    \
+      {                                                       \
+        case RCC_UART4CLKSOURCE_D2PCLK1:                      \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK1;       \
+          break;                                              \
+        case RCC_UART4CLKSOURCE_PLL2:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2;          \
+          break;                                              \
+        case RCC_UART4CLKSOURCE_PLL3:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3;          \
+          break;                                              \
+        case RCC_UART4CLKSOURCE_HSI:                          \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_UART4CLKSOURCE_CSI:                          \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI;           \
+          break;                                              \
+        case RCC_UART4CLKSOURCE_LSE:                          \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
+    else if ((__HANDLE__)->Instance == UART5)                 \
+    {                                                         \
+      switch(__HAL_RCC_GET_UART5_SOURCE())                    \
+      {                                                       \
+        case RCC_UART5CLKSOURCE_D2PCLK1:                      \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK1;       \
+          break;                                              \
+        case RCC_UART5CLKSOURCE_PLL2:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2;          \
+          break;                                              \
+        case RCC_UART5CLKSOURCE_PLL3:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3;          \
+          break;                                              \
+        case RCC_UART5CLKSOURCE_HSI:                          \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_UART5CLKSOURCE_CSI:                          \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI;           \
+          break;                                              \
+        case RCC_UART5CLKSOURCE_LSE:                          \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
+    else if((__HANDLE__)->Instance == USART6)                 \
+    {                                                         \
+      switch(__HAL_RCC_GET_USART6_SOURCE())                   \
+      {                                                       \
+        case RCC_USART6CLKSOURCE_D2PCLK2:                     \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK2;       \
+          break;                                              \
+        case RCC_USART6CLKSOURCE_PLL2:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2;          \
+          break;                                              \
+        case RCC_USART6CLKSOURCE_PLL3:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3;          \
+          break;                                              \
+        case RCC_USART6CLKSOURCE_HSI:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_USART6CLKSOURCE_CSI:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI;           \
+          break;                                              \
+        case RCC_USART6CLKSOURCE_LSE:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
+    else if((__HANDLE__)->Instance == UART7)                  \
+    {                                                         \
+      switch(__HAL_RCC_GET_UART7_SOURCE())                    \
+      {                                                       \
+        case RCC_UART7CLKSOURCE_D2PCLK1:                      \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK1;       \
+          break;                                              \
+        case RCC_UART7CLKSOURCE_PLL2:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2;          \
+          break;                                              \
+        case RCC_UART7CLKSOURCE_PLL3:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3;          \
+          break;                                              \
+        case RCC_UART7CLKSOURCE_HSI:                          \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_UART7CLKSOURCE_CSI:                          \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI;           \
+          break;                                              \
+        case RCC_UART7CLKSOURCE_LSE:                          \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
+    else if((__HANDLE__)->Instance == UART8)                  \
+    {                                                         \
+      switch(__HAL_RCC_GET_UART8_SOURCE())                    \
+      {                                                       \
+        case RCC_UART8CLKSOURCE_D2PCLK1:                      \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK1;       \
+          break;                                              \
+        case RCC_UART8CLKSOURCE_PLL2:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2;          \
+          break;                                              \
+        case RCC_UART8CLKSOURCE_PLL3:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3;          \
+          break;                                              \
+        case RCC_UART8CLKSOURCE_HSI:                          \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_UART8CLKSOURCE_CSI:                          \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI;           \
+          break;                                              \
+        case RCC_UART8CLKSOURCE_LSE:                          \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
+    else if((__HANDLE__)->Instance == UART9)                  \
+    {                                                         \
+      switch(__HAL_RCC_GET_UART9_SOURCE())                    \
+      {                                                       \
+        case RCC_UART9CLKSOURCE_D2PCLK2:                      \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK2;       \
+          break;                                              \
+        case RCC_UART9CLKSOURCE_PLL2:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2;          \
+          break;                                              \
+        case RCC_UART9CLKSOURCE_PLL3:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3;          \
+          break;                                              \
+        case RCC_UART9CLKSOURCE_HSI:                          \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_UART9CLKSOURCE_CSI:                          \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI;           \
+          break;                                              \
+        case RCC_UART9CLKSOURCE_LSE:                          \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
+    else if((__HANDLE__)->Instance == USART10)                \
+    {                                                         \
+      switch(__HAL_RCC_GET_USART10_SOURCE())                  \
+      {                                                       \
+        case RCC_USART10CLKSOURCE_D2PCLK2:                    \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK2;       \
+          break;                                              \
+        case RCC_USART10CLKSOURCE_PLL2:                       \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2;          \
+          break;                                              \
+        case RCC_USART10CLKSOURCE_PLL3:                       \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3;          \
+          break;                                              \
+        case RCC_USART10CLKSOURCE_HSI:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_USART10CLKSOURCE_CSI:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI;           \
+          break;                                              \
+        case RCC_USART10CLKSOURCE_LSE:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
+    else if((__HANDLE__)->Instance == LPUART1)                \
+    {                                                         \
+      switch(__HAL_RCC_GET_LPUART1_SOURCE())                  \
+      {                                                       \
+        case RCC_LPUART1CLKSOURCE_D3PCLK1:                    \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D3PCLK1;       \
+          break;                                              \
+        case RCC_LPUART1CLKSOURCE_PLL2:                       \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2;          \
+          break;                                              \
+        case RCC_LPUART1CLKSOURCE_PLL3:                       \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3;          \
+          break;                                              \
+        case RCC_LPUART1CLKSOURCE_HSI:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_LPUART1CLKSOURCE_CSI:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI;           \
+          break;                                              \
+        case RCC_LPUART1CLKSOURCE_LSE:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
+    else                                                      \
+    {                                                         \
+      (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;         \
+    }                                                         \
+  } while(0U)
+#else
+#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)       \
+  do {                                                        \
+    if((__HANDLE__)->Instance == USART1)                      \
+    {                                                         \
+      switch(__HAL_RCC_GET_USART1_SOURCE())                   \
+      {                                                       \
+        case RCC_USART1CLKSOURCE_D2PCLK2:                     \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK2;       \
+          break;                                              \
+        case RCC_USART1CLKSOURCE_PLL2:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2;          \
+          break;                                              \
+        case RCC_USART1CLKSOURCE_PLL3:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3;          \
+          break;                                              \
+        case RCC_USART1CLKSOURCE_HSI:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_USART1CLKSOURCE_CSI:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI;           \
+          break;                                              \
+        case RCC_USART1CLKSOURCE_LSE:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
+    else if((__HANDLE__)->Instance == USART2)                 \
+    {                                                         \
+      switch(__HAL_RCC_GET_USART2_SOURCE())                   \
+      {                                                       \
+        case RCC_USART2CLKSOURCE_D2PCLK1:                     \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK1;       \
+          break;                                              \
+        case RCC_USART2CLKSOURCE_PLL2:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2;          \
+          break;                                              \
+        case RCC_USART2CLKSOURCE_PLL3:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3;          \
+          break;                                              \
+        case RCC_USART2CLKSOURCE_HSI:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_USART2CLKSOURCE_CSI:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI;           \
+          break;                                              \
+        case RCC_USART2CLKSOURCE_LSE:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
+    else if((__HANDLE__)->Instance == USART3)                 \
+    {                                                         \
+      switch(__HAL_RCC_GET_USART3_SOURCE())                   \
+      {                                                       \
+        case RCC_USART3CLKSOURCE_D2PCLK1:                     \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK1;       \
+          break;                                              \
+        case RCC_USART3CLKSOURCE_PLL2:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2;          \
+          break;                                              \
+        case RCC_USART3CLKSOURCE_PLL3:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3;          \
+          break;                                              \
+        case RCC_USART3CLKSOURCE_HSI:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_USART3CLKSOURCE_CSI:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI;           \
+          break;                                              \
+        case RCC_USART3CLKSOURCE_LSE:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
+    else if((__HANDLE__)->Instance == UART4)                  \
+    {                                                         \
+      switch(__HAL_RCC_GET_UART4_SOURCE())                    \
+      {                                                       \
+        case RCC_UART4CLKSOURCE_D2PCLK1:                      \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK1;       \
+          break;                                              \
+        case RCC_UART4CLKSOURCE_PLL2:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2;          \
+          break;                                              \
+        case RCC_UART4CLKSOURCE_PLL3:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3;          \
+          break;                                              \
+        case RCC_UART4CLKSOURCE_HSI:                          \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_UART4CLKSOURCE_CSI:                          \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI;           \
+          break;                                              \
+        case RCC_UART4CLKSOURCE_LSE:                          \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
+    else if ((__HANDLE__)->Instance == UART5)                 \
+    {                                                         \
+      switch(__HAL_RCC_GET_UART5_SOURCE())                    \
+      {                                                       \
+        case RCC_UART5CLKSOURCE_D2PCLK1:                      \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK1;       \
+          break;                                              \
+        case RCC_UART5CLKSOURCE_PLL2:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2;          \
+          break;                                              \
+        case RCC_UART5CLKSOURCE_PLL3:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3;          \
+          break;                                              \
+        case RCC_UART5CLKSOURCE_HSI:                          \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_UART5CLKSOURCE_CSI:                          \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI;           \
+          break;                                              \
+        case RCC_UART5CLKSOURCE_LSE:                          \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
+    else if((__HANDLE__)->Instance == USART6)                 \
+    {                                                         \
+      switch(__HAL_RCC_GET_USART6_SOURCE())                   \
+      {                                                       \
+        case RCC_USART6CLKSOURCE_D2PCLK2:                     \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK2;       \
+          break;                                              \
+        case RCC_USART6CLKSOURCE_PLL2:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2;          \
+          break;                                              \
+        case RCC_USART6CLKSOURCE_PLL3:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3;          \
+          break;                                              \
+        case RCC_USART6CLKSOURCE_HSI:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_USART6CLKSOURCE_CSI:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI;           \
+          break;                                              \
+        case RCC_USART6CLKSOURCE_LSE:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
+    else if((__HANDLE__)->Instance == UART7)                  \
+    {                                                         \
+      switch(__HAL_RCC_GET_UART7_SOURCE())                    \
+      {                                                       \
+        case RCC_UART7CLKSOURCE_D2PCLK1:                      \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK1;       \
+          break;                                              \
+        case RCC_UART7CLKSOURCE_PLL2:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2;          \
+          break;                                              \
+        case RCC_UART7CLKSOURCE_PLL3:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3;          \
+          break;                                              \
+        case RCC_UART7CLKSOURCE_HSI:                          \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_UART7CLKSOURCE_CSI:                          \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI;           \
+          break;                                              \
+        case RCC_UART7CLKSOURCE_LSE:                          \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
+    else if((__HANDLE__)->Instance == UART8)                  \
+    {                                                         \
+      switch(__HAL_RCC_GET_UART8_SOURCE())                    \
+      {                                                       \
+        case RCC_UART8CLKSOURCE_D2PCLK1:                      \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK1;       \
+          break;                                              \
+        case RCC_UART8CLKSOURCE_PLL2:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2;          \
+          break;                                              \
+        case RCC_UART8CLKSOURCE_PLL3:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3;          \
+          break;                                              \
+        case RCC_UART8CLKSOURCE_HSI:                          \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_UART8CLKSOURCE_CSI:                          \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI;           \
+          break;                                              \
+        case RCC_UART8CLKSOURCE_LSE:                          \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
+    else if((__HANDLE__)->Instance == LPUART1)                \
+    {                                                         \
+      switch(__HAL_RCC_GET_LPUART1_SOURCE())                  \
+      {                                                       \
+        case RCC_LPUART1CLKSOURCE_D3PCLK1:                    \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D3PCLK1;       \
+          break;                                              \
+        case RCC_LPUART1CLKSOURCE_PLL2:                       \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2;          \
+          break;                                              \
+        case RCC_LPUART1CLKSOURCE_PLL3:                       \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3;          \
+          break;                                              \
+        case RCC_LPUART1CLKSOURCE_HSI:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_LPUART1CLKSOURCE_CSI:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI;           \
+          break;                                              \
+        case RCC_LPUART1CLKSOURCE_LSE:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
+    else                                                      \
+    {                                                         \
+      (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;         \
+    }                                                         \
+  } while(0U)
+#endif  /* UART9 && USART10 */
+
+/** @brief  Report the UART mask to apply to retrieve the received data
+  *         according to the word length and to the parity bits activation.
+  * @note   If PCE = 1, the parity bit is not included in the data extracted
+  *         by the reception API().
+  *         This masking operation is not carried out in the case of
+  *         DMA transfers.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @retval None, the mask to apply to UART RDR register is stored in (__HANDLE__)->Mask field.
+  */
+#define UART_MASK_COMPUTATION(__HANDLE__)                             \
+  do {                                                                \
+    if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_9B)          \
+    {                                                                 \
+      if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE)              \
+      {                                                               \
+        (__HANDLE__)->Mask = 0x01FFU ;                                \
+      }                                                               \
+      else                                                            \
+      {                                                               \
+        (__HANDLE__)->Mask = 0x00FFU ;                                \
+      }                                                               \
+    }                                                                 \
+    else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_8B)     \
+    {                                                                 \
+      if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE)              \
+      {                                                               \
+        (__HANDLE__)->Mask = 0x00FFU ;                                \
+      }                                                               \
+      else                                                            \
+      {                                                               \
+        (__HANDLE__)->Mask = 0x007FU ;                                \
+      }                                                               \
+    }                                                                 \
+    else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_7B)     \
+    {                                                                 \
+      if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE)              \
+      {                                                               \
+        (__HANDLE__)->Mask = 0x007FU ;                                \
+      }                                                               \
+      else                                                            \
+      {                                                               \
+        (__HANDLE__)->Mask = 0x003FU ;                                \
+      }                                                               \
+    }                                                                 \
+    else                                                              \
+    {                                                                 \
+      (__HANDLE__)->Mask = 0x0000U;                                   \
+    }                                                                 \
+  } while(0U)
+
+/**
+  * @brief Ensure that UART frame length is valid.
+  * @param __LENGTH__ UART frame length.
+  * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
+  */
+#define IS_UART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == UART_WORDLENGTH_7B) || \
+                                         ((__LENGTH__) == UART_WORDLENGTH_8B) || \
+                                         ((__LENGTH__) == UART_WORDLENGTH_9B))
+
+/**
+  * @brief Ensure that UART wake-up address length is valid.
+  * @param __ADDRESS__ UART wake-up address length.
+  * @retval SET (__ADDRESS__ is valid) or RESET (__ADDRESS__ is invalid)
+  */
+#define IS_UART_ADDRESSLENGTH_DETECT(__ADDRESS__) (((__ADDRESS__) == UART_ADDRESS_DETECT_4B) || \
+                                                   ((__ADDRESS__) == UART_ADDRESS_DETECT_7B))
+
+/**
+  * @brief Ensure that UART TXFIFO threshold level is valid.
+  * @param __THRESHOLD__ UART TXFIFO threshold level.
+  * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)
+  */
+#define IS_UART_TXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_8) || \
+                                                 ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_4) || \
+                                                 ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_2) || \
+                                                 ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_3_4) || \
+                                                 ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_7_8) || \
+                                                 ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_8_8))
+
+/**
+  * @brief Ensure that UART RXFIFO threshold level is valid.
+  * @param __THRESHOLD__ UART RXFIFO threshold level.
+  * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)
+  */
+#define IS_UART_RXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_8) || \
+                                                 ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_4) || \
+                                                 ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_2) || \
+                                                 ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_3_4) || \
+                                                 ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_7_8) || \
+                                                 ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_8_8))
+
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32H7xx_HAL_UART_EX_H */
+
diff --git a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h
new file mode 100644
index 0000000..4733bc7
--- /dev/null
+++ b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h
@@ -0,0 +1,93 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_ll_delayblock.h
+  * @author  MCD Application Team
+  * @brief   Header file of Delay Block module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_LL_DLYB_H
+#define STM32H7xx_LL_DLYB_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal_def.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup DELAYBLOCK_LL
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/ 
+/** @defgroup DELAYBLOCK_LL_Exported_Types DELAYBLOCK_LL Exported Types
+  * @{
+  */
+  
+
+/**
+  * @}
+  */
+  
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup DLYB_Exported_Constants Delay Block Exported Constants
+  * @{
+  */
+
+
+#define DLYB_MAX_UNIT   ((uint32_t)0x00000080U) /*!< Max UNIT value (128)  */
+#define DLYB_MAX_SELECT ((uint32_t)0x0000000CU) /*!< Max SELECT value (12)  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup DelayBlock_LL_Exported_Functions
+  * @{
+  */
+ 
+/* Peripheral Control functions  ************************************************/
+/** @addtogroup HAL_DELAY_LL_Group1
+  * @{
+  */
+HAL_StatusTypeDef DelayBlock_Enable(DLYB_TypeDef *DLYBx);
+HAL_StatusTypeDef DelayBlock_Disable(DLYB_TypeDef *DLYBx);
+HAL_StatusTypeDef DelayBlock_Configure(DLYB_TypeDef *DLYBx, uint32_t PhaseSel, uint32_t Units);
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */
+   
+/**
+  * @}
+  */
+
+  /**
+  * @}
+  */
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32H7xx_LL_DLYB_H */
+
diff --git a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_lpuart.h b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_lpuart.h
new file mode 100644
index 0000000..fe66bec
--- /dev/null
+++ b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_lpuart.h
@@ -0,0 +1,2643 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_ll_lpuart.h
+  * @author  MCD Application Team
+  * @brief   Header file of LPUART LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_LL_LPUART_H
+#define STM32H7xx_LL_LPUART_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx.h"
+
+/** @addtogroup STM32H7xx_LL_Driver
+  * @{
+  */
+
+#if defined (LPUART1)
+
+/** @defgroup LPUART_LL LPUART
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup LPUART_LL_Private_Variables LPUART Private Variables
+  * @{
+  */
+/* Array used to get the LPUART prescaler division decimal values versus @ref LPUART_LL_EC_PRESCALER values */
+static const uint16_t LPUART_PRESCALER_TAB[] =
+{
+  (uint16_t)1,
+  (uint16_t)2,
+  (uint16_t)4,
+  (uint16_t)6,
+  (uint16_t)8,
+  (uint16_t)10,
+  (uint16_t)12,
+  (uint16_t)16,
+  (uint16_t)32,
+  (uint16_t)64,
+  (uint16_t)128,
+  (uint16_t)256
+};
+/**
+  * @}
+  */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup LPUART_LL_Private_Constants LPUART Private Constants
+  * @{
+  */
+/* Defines used in Baud Rate related macros and corresponding register setting computation */
+#define LPUART_LPUARTDIV_FREQ_MUL     256U
+#define LPUART_BRR_MASK               0x000FFFFFU
+#define LPUART_BRR_MIN_VALUE          0x00000300U
+/**
+  * @}
+  */
+
+
+/* Private macros ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup LPUART_LL_Private_Macros LPUART Private Macros
+  * @{
+  */
+/**
+  * @}
+  */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup LPUART_LL_ES_INIT LPUART Exported Init structures
+  * @{
+  */
+
+/**
+  * @brief LL LPUART Init Structure definition
+  */
+typedef struct
+{
+  uint32_t PrescalerValue;            /*!< Specifies the Prescaler to compute the communication baud rate.
+                                           This parameter can be a value of @ref LPUART_LL_EC_PRESCALER.
+
+                                           This feature can be modified afterwards using unitary
+                                           function @ref LL_LPUART_SetPrescaler().*/
+
+  uint32_t BaudRate;                  /*!< This field defines expected LPUART communication baud rate.
+
+                                           This feature can be modified afterwards using unitary
+                                           function @ref LL_LPUART_SetBaudRate().*/
+
+  uint32_t DataWidth;                 /*!< Specifies the number of data bits transmitted or received in a frame.
+                                           This parameter can be a value of @ref LPUART_LL_EC_DATAWIDTH.
+
+                                           This feature can be modified afterwards using unitary
+                                           function @ref LL_LPUART_SetDataWidth().*/
+
+  uint32_t StopBits;                  /*!< Specifies the number of stop bits transmitted.
+                                           This parameter can be a value of @ref LPUART_LL_EC_STOPBITS.
+
+                                           This feature can be modified afterwards using unitary
+                                           function @ref LL_LPUART_SetStopBitsLength().*/
+
+  uint32_t Parity;                    /*!< Specifies the parity mode.
+                                           This parameter can be a value of @ref LPUART_LL_EC_PARITY.
+
+                                           This feature can be modified afterwards using unitary
+                                           function @ref LL_LPUART_SetParity().*/
+
+  uint32_t TransferDirection;         /*!< Specifies whether the Receive and/or Transmit mode is enabled or disabled.
+                                           This parameter can be a value of @ref LPUART_LL_EC_DIRECTION.
+
+                                           This feature can be modified afterwards using unitary
+                                           function @ref LL_LPUART_SetTransferDirection().*/
+
+  uint32_t HardwareFlowControl;       /*!< Specifies whether the hardware flow control mode is enabled or disabled.
+                                           This parameter can be a value of @ref LPUART_LL_EC_HWCONTROL.
+
+                                           This feature can be modified afterwards using unitary
+                                           function @ref LL_LPUART_SetHWFlowCtrl().*/
+
+} LL_LPUART_InitTypeDef;
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup LPUART_LL_Exported_Constants LPUART Exported Constants
+  * @{
+  */
+
+/** @defgroup LPUART_LL_EC_CLEAR_FLAG Clear Flags Defines
+  * @brief    Flags defines which can be used with LL_LPUART_WriteReg function
+  * @{
+  */
+#define LL_LPUART_ICR_PECF                 USART_ICR_PECF                /*!< Parity error clear flag */
+#define LL_LPUART_ICR_FECF                 USART_ICR_FECF                /*!< Framing error clear flag */
+#define LL_LPUART_ICR_NCF                  USART_ICR_NECF                /*!< Noise error detected clear flag */
+#define LL_LPUART_ICR_ORECF                USART_ICR_ORECF               /*!< Overrun error clear flag */
+#define LL_LPUART_ICR_IDLECF               USART_ICR_IDLECF              /*!< Idle line detected clear flag */
+#define LL_LPUART_ICR_TCCF                 USART_ICR_TCCF                /*!< Transmission complete clear flag */
+#define LL_LPUART_ICR_CTSCF                USART_ICR_CTSCF               /*!< CTS clear flag */
+#define LL_LPUART_ICR_CMCF                 USART_ICR_CMCF                /*!< Character match clear flag */
+#define LL_LPUART_ICR_WUCF                 USART_ICR_WUCF                /*!< Wakeup from Stop mode clear flag */
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EC_GET_FLAG Get Flags Defines
+  * @brief    Flags defines which can be used with LL_LPUART_ReadReg function
+  * @{
+  */
+#define LL_LPUART_ISR_PE               USART_ISR_PE         /*!< Parity error flag */
+#define LL_LPUART_ISR_FE               USART_ISR_FE         /*!< Framing error flag */
+#define LL_LPUART_ISR_NE               USART_ISR_NE         /*!< Noise detected flag */
+#define LL_LPUART_ISR_ORE              USART_ISR_ORE        /*!< Overrun error flag */
+#define LL_LPUART_ISR_IDLE             USART_ISR_IDLE       /*!< Idle line detected flag */
+#define LL_LPUART_ISR_RXNE_RXFNE       USART_ISR_RXNE_RXFNE /*!< Read data register or RX FIFO not empty flag */
+#define LL_LPUART_ISR_TC               USART_ISR_TC         /*!< Transmission complete flag */
+#define LL_LPUART_ISR_TXE_TXFNF        USART_ISR_TXE_TXFNF  /*!< Transmit data register empty or TX FIFO Not Full flag*/
+#define LL_LPUART_ISR_CTSIF            USART_ISR_CTSIF      /*!< CTS interrupt flag */
+#define LL_LPUART_ISR_CTS              USART_ISR_CTS        /*!< CTS flag */
+#define LL_LPUART_ISR_BUSY             USART_ISR_BUSY       /*!< Busy flag */
+#define LL_LPUART_ISR_CMF              USART_ISR_CMF        /*!< Character match flag */
+#define LL_LPUART_ISR_SBKF             USART_ISR_SBKF       /*!< Send break flag */
+#define LL_LPUART_ISR_RWU              USART_ISR_RWU        /*!< Receiver wakeup from Mute mode flag */
+#define LL_LPUART_ISR_WUF              USART_ISR_WUF        /*!< Wakeup from Stop mode flag */
+#define LL_LPUART_ISR_TEACK            USART_ISR_TEACK      /*!< Transmit enable acknowledge flag */
+#define LL_LPUART_ISR_REACK            USART_ISR_REACK      /*!< Receive enable acknowledge flag */
+#define LL_LPUART_ISR_TXFE             USART_ISR_TXFE       /*!< TX FIFO empty flag */
+#define LL_LPUART_ISR_RXFF             USART_ISR_RXFF       /*!< RX FIFO full flag */
+#define LL_LPUART_ISR_RXFT             USART_ISR_RXFT       /*!< RX FIFO threshold flag */
+#define LL_LPUART_ISR_TXFT             USART_ISR_TXFT       /*!< TX FIFO threshold flag */
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EC_IT IT Defines
+  * @brief    IT defines which can be used with LL_LPUART_ReadReg and  LL_LPUART_WriteReg functions
+  * @{
+  */
+#define LL_LPUART_CR1_IDLEIE         USART_CR1_IDLEIE         /*!< IDLE interrupt enable */
+#define LL_LPUART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_RXFNEIE /*!< Read data register and RXFIFO not empty
+                                                                   interrupt enable */
+#define LL_LPUART_CR1_TCIE           USART_CR1_TCIE           /*!< Transmission complete interrupt enable */
+#define LL_LPUART_CR1_TXEIE_TXFNFIE  USART_CR1_TXEIE_TXFNFIE  /*!< Transmit data register empty and TX FIFO
+                                                                   not full interrupt enable */
+#define LL_LPUART_CR1_PEIE           USART_CR1_PEIE           /*!< Parity error */
+#define LL_LPUART_CR1_CMIE           USART_CR1_CMIE           /*!< Character match interrupt enable */
+#define LL_LPUART_CR1_TXFEIE         USART_CR1_TXFEIE         /*!< TX FIFO empty interrupt enable */
+#define LL_LPUART_CR1_RXFFIE         USART_CR1_RXFFIE         /*!< RX FIFO full interrupt enable */
+#define LL_LPUART_CR3_EIE            USART_CR3_EIE            /*!< Error interrupt enable */
+#define LL_LPUART_CR3_CTSIE          USART_CR3_CTSIE          /*!< CTS interrupt enable */
+#define LL_LPUART_CR3_WUFIE          USART_CR3_WUFIE          /*!< Wakeup from Stop mode interrupt enable */
+#define LL_LPUART_CR3_TXFTIE         USART_CR3_TXFTIE         /*!< TX FIFO threshold interrupt enable */
+#define LL_LPUART_CR3_RXFTIE         USART_CR3_RXFTIE         /*!< RX FIFO threshold interrupt enable */
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EC_FIFOTHRESHOLD FIFO Threshold
+  * @{
+  */
+#define LL_LPUART_FIFOTHRESHOLD_1_8        0x00000000U /*!< FIFO reaches 1/8 of its depth */
+#define LL_LPUART_FIFOTHRESHOLD_1_4        0x00000001U /*!< FIFO reaches 1/4 of its depth */
+#define LL_LPUART_FIFOTHRESHOLD_1_2        0x00000002U /*!< FIFO reaches 1/2 of its depth */
+#define LL_LPUART_FIFOTHRESHOLD_3_4        0x00000003U /*!< FIFO reaches 3/4 of its depth */
+#define LL_LPUART_FIFOTHRESHOLD_7_8        0x00000004U /*!< FIFO reaches 7/8 of its depth */
+#define LL_LPUART_FIFOTHRESHOLD_8_8        0x00000005U /*!< FIFO becomes empty for TX and full for RX */
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EC_DIRECTION Direction
+  * @{
+  */
+#define LL_LPUART_DIRECTION_NONE  0x00000000U                  /*!< Transmitter and Receiver are disabled           */
+#define LL_LPUART_DIRECTION_RX    USART_CR1_RE                 /*!< Transmitter is disabled and Receiver is enabled */
+#define LL_LPUART_DIRECTION_TX    USART_CR1_TE                 /*!< Transmitter is enabled and Receiver is disabled */
+#define LL_LPUART_DIRECTION_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< Transmitter and Receiver are enabled            */
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EC_PARITY Parity Control
+  * @{
+  */
+#define LL_LPUART_PARITY_NONE 0x00000000U                    /*!< Parity control disabled                            */
+#define LL_LPUART_PARITY_EVEN USART_CR1_PCE                  /*!< Parity control enabled and Even Parity is selected */
+#define LL_LPUART_PARITY_ODD  (USART_CR1_PCE | USART_CR1_PS) /*!< Parity control enabled and Odd Parity is selected  */
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EC_WAKEUP Wakeup
+  * @{
+  */
+#define LL_LPUART_WAKEUP_IDLELINE    0x00000000U    /*!<  LPUART wake up from Mute mode on Idle Line    */
+#define LL_LPUART_WAKEUP_ADDRESSMARK USART_CR1_WAKE /*!<  LPUART wake up from Mute mode on Address Mark */
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EC_DATAWIDTH Datawidth
+  * @{
+  */
+#define LL_LPUART_DATAWIDTH_7B USART_CR1_M1 /*!< 7 bits word length : Start bit, 7 data bits, n stop bits */
+#define LL_LPUART_DATAWIDTH_8B 0x00000000U  /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */
+#define LL_LPUART_DATAWIDTH_9B USART_CR1_M0 /*!< 9 bits word length : Start bit, 9 data bits, n stop bits */
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EC_PRESCALER Clock Source Prescaler
+  * @{
+  */
+#define LL_LPUART_PRESCALER_DIV1   0x00000000U                    /*!< Input clock not divided   */
+#define LL_LPUART_PRESCALER_DIV2   (USART_PRESC_PRESCALER_0)      /*!< Input clock divided by 2  */
+#define LL_LPUART_PRESCALER_DIV4   (USART_PRESC_PRESCALER_1)      /*!< Input clock divided by 4  */
+#define LL_LPUART_PRESCALER_DIV6   (USART_PRESC_PRESCALER_1 |\
+                                    USART_PRESC_PRESCALER_0)      /*!< Input clock divided by 6  */
+#define LL_LPUART_PRESCALER_DIV8   (USART_PRESC_PRESCALER_2)      /*!< Input clock divided by 8  */
+#define LL_LPUART_PRESCALER_DIV10  (USART_PRESC_PRESCALER_2 |\
+                                    USART_PRESC_PRESCALER_0)      /*!< Input clock divided by 10 */
+#define LL_LPUART_PRESCALER_DIV12  (USART_PRESC_PRESCALER_2 |\
+                                    USART_PRESC_PRESCALER_1)      /*!< Input clock divided by 12 */
+#define LL_LPUART_PRESCALER_DIV16  (USART_PRESC_PRESCALER_2 |\
+                                    USART_PRESC_PRESCALER_1 |\
+                                    USART_PRESC_PRESCALER_0)      /*!< Input clock divided by 16 */
+#define LL_LPUART_PRESCALER_DIV32  (USART_PRESC_PRESCALER_3)      /*!< Input clock divided by 32 */
+#define LL_LPUART_PRESCALER_DIV64  (USART_PRESC_PRESCALER_3 |\
+                                    USART_PRESC_PRESCALER_0)      /*!< Input clock divided by 64 */
+#define LL_LPUART_PRESCALER_DIV128 (USART_PRESC_PRESCALER_3 |\
+                                    USART_PRESC_PRESCALER_1)      /*!< Input clock divided by 128 */
+#define LL_LPUART_PRESCALER_DIV256 (USART_PRESC_PRESCALER_3 |\
+                                    USART_PRESC_PRESCALER_1 |\
+                                    USART_PRESC_PRESCALER_0)      /*!< Input clock divided by 256 */
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EC_STOPBITS Stop Bits
+  * @{
+  */
+#define LL_LPUART_STOPBITS_1         0x00000000U             /*!< 1 stop bit */
+#define LL_LPUART_STOPBITS_2         USART_CR2_STOP_1        /*!< 2 stop bits */
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EC_TXRX TX RX Pins Swap
+  * @{
+  */
+#define LL_LPUART_TXRX_STANDARD      0x00000000U        /*!< TX/RX pins are used as defined in standard pinout */
+#define LL_LPUART_TXRX_SWAPPED       (USART_CR2_SWAP)   /*!< TX and RX pins functions are swapped.             */
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EC_RXPIN_LEVEL RX Pin Active Level Inversion
+  * @{
+  */
+#define LL_LPUART_RXPIN_LEVEL_STANDARD   0x00000000U       /*!< RX pin signal works using the standard logic levels */
+#define LL_LPUART_RXPIN_LEVEL_INVERTED   (USART_CR2_RXINV) /*!< RX pin signal values are inverted.                  */
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EC_TXPIN_LEVEL TX Pin Active Level Inversion
+  * @{
+  */
+#define LL_LPUART_TXPIN_LEVEL_STANDARD  0x00000000U       /*!< TX pin signal works using the standard logic levels */
+#define LL_LPUART_TXPIN_LEVEL_INVERTED  (USART_CR2_TXINV) /*!< TX pin signal values are inverted.                  */
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EC_BINARY_LOGIC Binary Data Inversion
+  * @{
+  */
+#define LL_LPUART_BINARY_LOGIC_POSITIVE 0x00000000U       /*!< Logical data from the data register are send/received
+                                                               in positive/direct logic. (1=H, 0=L)                  */
+#define LL_LPUART_BINARY_LOGIC_NEGATIVE USART_CR2_DATAINV /*!< Logical data from the data register are send/received
+                                                               in negative/inverse logic. (1=L, 0=H).
+                                                               The parity bit is also inverted.                      */
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EC_BITORDER Bit Order
+  * @{
+  */
+#define LL_LPUART_BITORDER_LSBFIRST 0x00000000U        /*!< data is transmitted/received with data bit 0 first,
+                                                            following the start bit */
+#define LL_LPUART_BITORDER_MSBFIRST USART_CR2_MSBFIRST /*!< data is transmitted/received with the MSB first,
+                                                            following the start bit */
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EC_ADDRESS_DETECT Address Length Detection
+  * @{
+  */
+#define LL_LPUART_ADDRESS_DETECT_4B 0x00000000U     /*!< 4-bit address detection method selected */
+#define LL_LPUART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /*!< 7-bit address detection (in 8-bit data mode) method selected */
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EC_HWCONTROL Hardware Control
+  * @{
+  */
+#define LL_LPUART_HWCONTROL_NONE    0x00000000U                       /*!< CTS and RTS hardware flow control disabled */
+#define LL_LPUART_HWCONTROL_RTS     USART_CR3_RTSE                    /*!< RTS output enabled, data is only requested
+                                                                           when there is space in the receive buffer  */
+#define LL_LPUART_HWCONTROL_CTS     USART_CR3_CTSE                    /*!< CTS mode enabled, data is only transmitted
+                                                                           when the nCTS input is asserted (tied to 0)*/
+#define LL_LPUART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) /*!< CTS and RTS hardware flow control enabled  */
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EC_WAKEUP_ON Wakeup Activation
+  * @{
+  */
+#define LL_LPUART_WAKEUP_ON_ADDRESS   0x00000000U                          /*!< Wake up active on address match */
+#define LL_LPUART_WAKEUP_ON_STARTBIT  USART_CR3_WUS_1                      /*!< Wake up active on Start bit detection */
+#define LL_LPUART_WAKEUP_ON_RXNE      (USART_CR3_WUS_0 | USART_CR3_WUS_1)  /*!< Wake up active on RXNE */
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EC_DE_POLARITY Driver Enable Polarity
+  * @{
+  */
+#define LL_LPUART_DE_POLARITY_HIGH         0x00000000U    /*!< DE signal is active high */
+#define LL_LPUART_DE_POLARITY_LOW          USART_CR3_DEP  /*!< DE signal is active low */
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EC_DMA_REG_DATA DMA Register Data
+  * @{
+  */
+#define LL_LPUART_DMA_REG_DATA_TRANSMIT    0x00000000U    /*!< Get address of data register used for transmission */
+#define LL_LPUART_DMA_REG_DATA_RECEIVE     0x00000001U    /*!< Get address of data register used for reception */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup LPUART_LL_Exported_Macros LPUART Exported Macros
+  * @{
+  */
+
+/** @defgroup LPUART_LL_EM_WRITE_READ Common Write and read registers Macros
+  * @{
+  */
+
+/**
+  * @brief  Write a value in LPUART register
+  * @param  __INSTANCE__ LPUART Instance
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_LPUART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in LPUART register
+  * @param  __INSTANCE__ LPUART Instance
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_LPUART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EM_Exported_Macros_Helper Helper Macros
+  * @{
+  */
+
+/**
+  * @brief  Compute LPUARTDIV value according to Peripheral Clock and
+  *         expected Baud Rate (20-bit value of LPUARTDIV is returned)
+  * @param  __PERIPHCLK__ Peripheral Clock frequency used for LPUART Instance
+  * @param  __PRESCALER__ This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_PRESCALER_DIV1
+  *         @arg @ref LL_LPUART_PRESCALER_DIV2
+  *         @arg @ref LL_LPUART_PRESCALER_DIV4
+  *         @arg @ref LL_LPUART_PRESCALER_DIV6
+  *         @arg @ref LL_LPUART_PRESCALER_DIV8
+  *         @arg @ref LL_LPUART_PRESCALER_DIV10
+  *         @arg @ref LL_LPUART_PRESCALER_DIV12
+  *         @arg @ref LL_LPUART_PRESCALER_DIV16
+  *         @arg @ref LL_LPUART_PRESCALER_DIV32
+  *         @arg @ref LL_LPUART_PRESCALER_DIV64
+  *         @arg @ref LL_LPUART_PRESCALER_DIV128
+  *         @arg @ref LL_LPUART_PRESCALER_DIV256
+  * @param  __BAUDRATE__ Baud Rate value to achieve
+  * @retval LPUARTDIV value to be used for BRR register filling
+  */
+#define __LL_LPUART_DIV(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) (uint32_t)\
+  ((((((uint64_t)(__PERIPHCLK__)/(uint64_t)(LPUART_PRESCALER_TAB[(uint16_t)(__PRESCALER__)]))\
+      * LPUART_LPUARTDIV_FREQ_MUL) + (uint32_t)((__BAUDRATE__)/2U))/(__BAUDRATE__)) & LPUART_BRR_MASK)
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup LPUART_LL_Exported_Functions LPUART Exported Functions
+  * @{
+  */
+
+/** @defgroup LPUART_LL_EF_Configuration Configuration functions
+  * @{
+  */
+
+/**
+  * @brief  LPUART Enable
+  * @rmtoll CR1          UE            LL_LPUART_Enable
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_Enable(USART_TypeDef *LPUARTx)
+{
+  SET_BIT(LPUARTx->CR1, USART_CR1_UE);
+}
+
+/**
+  * @brief  LPUART Disable
+  * @note   When LPUART is disabled, LPUART prescalers and outputs are stopped immediately,
+  *         and current operations are discarded. The configuration of the LPUART is kept, but all the status
+  *         flags, in the LPUARTx_ISR are set to their default values.
+  * @note   In order to go into low-power mode without generating errors on the line,
+  *         the TE bit must be reset before and the software must wait
+  *         for the TC bit in the LPUART_ISR to be set before resetting the UE bit.
+  *         The DMA requests are also reset when UE = 0 so the DMA channel must
+  *         be disabled before resetting the UE bit.
+  * @rmtoll CR1          UE            LL_LPUART_Disable
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_Disable(USART_TypeDef *LPUARTx)
+{
+  CLEAR_BIT(LPUARTx->CR1, USART_CR1_UE);
+}
+
+/**
+  * @brief  Indicate if LPUART is enabled
+  * @rmtoll CR1          UE            LL_LPUART_IsEnabled
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabled(const USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->CR1, USART_CR1_UE) == (USART_CR1_UE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  FIFO Mode Enable
+  * @rmtoll CR1          FIFOEN        LL_LPUART_EnableFIFO
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableFIFO(USART_TypeDef *LPUARTx)
+{
+  SET_BIT(LPUARTx->CR1, USART_CR1_FIFOEN);
+}
+
+/**
+  * @brief  FIFO Mode Disable
+  * @rmtoll CR1          FIFOEN        LL_LPUART_DisableFIFO
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableFIFO(USART_TypeDef *LPUARTx)
+{
+  CLEAR_BIT(LPUARTx->CR1, USART_CR1_FIFOEN);
+}
+
+/**
+  * @brief  Indicate if FIFO Mode is enabled
+  * @rmtoll CR1          FIFOEN        LL_LPUART_IsEnabledFIFO
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledFIFO(const USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->CR1, USART_CR1_FIFOEN) == (USART_CR1_FIFOEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Configure TX FIFO Threshold
+  * @rmtoll CR3          TXFTCFG       LL_LPUART_SetTXFIFOThreshold
+  * @param  LPUARTx LPUART Instance
+  * @param  Threshold This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_SetTXFIFOThreshold(USART_TypeDef *LPUARTx, uint32_t Threshold)
+{
+  ATOMIC_MODIFY_REG(LPUARTx->CR3, USART_CR3_TXFTCFG, Threshold << USART_CR3_TXFTCFG_Pos);
+}
+
+/**
+  * @brief  Return TX FIFO Threshold Configuration
+  * @rmtoll CR3          TXFTCFG       LL_LPUART_GetTXFIFOThreshold
+  * @param  LPUARTx LPUART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetTXFIFOThreshold(const USART_TypeDef *LPUARTx)
+{
+  return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos);
+}
+
+/**
+  * @brief  Configure RX FIFO Threshold
+  * @rmtoll CR3          RXFTCFG       LL_LPUART_SetRXFIFOThreshold
+  * @param  LPUARTx LPUART Instance
+  * @param  Threshold This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_SetRXFIFOThreshold(USART_TypeDef *LPUARTx, uint32_t Threshold)
+{
+  ATOMIC_MODIFY_REG(LPUARTx->CR3, USART_CR3_RXFTCFG, Threshold << USART_CR3_RXFTCFG_Pos);
+}
+
+/**
+  * @brief  Return RX FIFO Threshold Configuration
+  * @rmtoll CR3          RXFTCFG       LL_LPUART_GetRXFIFOThreshold
+  * @param  LPUARTx LPUART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetRXFIFOThreshold(const USART_TypeDef *LPUARTx)
+{
+  return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos);
+}
+
+/**
+  * @brief  Configure TX and RX FIFOs Threshold
+  * @rmtoll CR3          TXFTCFG       LL_LPUART_ConfigFIFOsThreshold\n
+  *         CR3          RXFTCFG       LL_LPUART_ConfigFIFOsThreshold
+  * @param  LPUARTx LPUART Instance
+  * @param  TXThreshold This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
+  * @param  RXThreshold This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_ConfigFIFOsThreshold(USART_TypeDef *LPUARTx, uint32_t TXThreshold, uint32_t RXThreshold)
+{
+  ATOMIC_MODIFY_REG(LPUARTx->CR3, USART_CR3_TXFTCFG | USART_CR3_RXFTCFG, (TXThreshold << USART_CR3_TXFTCFG_Pos) | \
+                    (RXThreshold << USART_CR3_RXFTCFG_Pos));
+}
+
+/**
+  * @brief  LPUART enabled in STOP Mode
+  * @note   When this function is enabled, LPUART is able to wake up the MCU from Stop mode, provided that
+  *         LPUART clock selection is HSI or LSE in RCC.
+  * @rmtoll CR1          UESM          LL_LPUART_EnableInStopMode
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableInStopMode(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_UESM);
+}
+
+/**
+  * @brief  LPUART disabled in STOP Mode
+  * @note   When this function is disabled, LPUART is not able to wake up the MCU from Stop mode
+  * @rmtoll CR1          UESM          LL_LPUART_DisableInStopMode
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableInStopMode(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_UESM);
+}
+
+/**
+  * @brief  Indicate if LPUART is enabled in STOP Mode
+  *         (able to wake up MCU from Stop mode or not)
+  * @rmtoll CR1          UESM          LL_LPUART_IsEnabledInStopMode
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledInStopMode(const USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->CR1, USART_CR1_UESM) == (USART_CR1_UESM)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Receiver Enable (Receiver is enabled and begins searching for a start bit)
+  * @rmtoll CR1          RE            LL_LPUART_EnableDirectionRx
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableDirectionRx(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_RE);
+}
+
+/**
+  * @brief  Receiver Disable
+  * @rmtoll CR1          RE            LL_LPUART_DisableDirectionRx
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableDirectionRx(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_RE);
+}
+
+/**
+  * @brief  Transmitter Enable
+  * @rmtoll CR1          TE            LL_LPUART_EnableDirectionTx
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableDirectionTx(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TE);
+}
+
+/**
+  * @brief  Transmitter Disable
+  * @rmtoll CR1          TE            LL_LPUART_DisableDirectionTx
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableDirectionTx(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TE);
+}
+
+/**
+  * @brief  Configure simultaneously enabled/disabled states
+  *         of Transmitter and Receiver
+  * @rmtoll CR1          RE            LL_LPUART_SetTransferDirection\n
+  *         CR1          TE            LL_LPUART_SetTransferDirection
+  * @param  LPUARTx LPUART Instance
+  * @param  TransferDirection This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_DIRECTION_NONE
+  *         @arg @ref LL_LPUART_DIRECTION_RX
+  *         @arg @ref LL_LPUART_DIRECTION_TX
+  *         @arg @ref LL_LPUART_DIRECTION_TX_RX
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_SetTransferDirection(USART_TypeDef *LPUARTx, uint32_t TransferDirection)
+{
+  ATOMIC_MODIFY_REG(LPUARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection);
+}
+
+/**
+  * @brief  Return enabled/disabled states of Transmitter and Receiver
+  * @rmtoll CR1          RE            LL_LPUART_GetTransferDirection\n
+  *         CR1          TE            LL_LPUART_GetTransferDirection
+  * @param  LPUARTx LPUART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPUART_DIRECTION_NONE
+  *         @arg @ref LL_LPUART_DIRECTION_RX
+  *         @arg @ref LL_LPUART_DIRECTION_TX
+  *         @arg @ref LL_LPUART_DIRECTION_TX_RX
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetTransferDirection(const USART_TypeDef *LPUARTx)
+{
+  return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_RE | USART_CR1_TE));
+}
+
+/**
+  * @brief  Configure Parity (enabled/disabled and parity mode if enabled)
+  * @note   This function selects if hardware parity control (generation and detection) is enabled or disabled.
+  *         When the parity control is enabled (Odd or Even), computed parity bit is inserted at the MSB position
+  *         (depending on data width) and parity is checked on the received data.
+  * @rmtoll CR1          PS            LL_LPUART_SetParity\n
+  *         CR1          PCE           LL_LPUART_SetParity
+  * @param  LPUARTx LPUART Instance
+  * @param  Parity This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_PARITY_NONE
+  *         @arg @ref LL_LPUART_PARITY_EVEN
+  *         @arg @ref LL_LPUART_PARITY_ODD
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_SetParity(USART_TypeDef *LPUARTx, uint32_t Parity)
+{
+  MODIFY_REG(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE, Parity);
+}
+
+/**
+  * @brief  Return Parity configuration (enabled/disabled and parity mode if enabled)
+  * @rmtoll CR1          PS            LL_LPUART_GetParity\n
+  *         CR1          PCE           LL_LPUART_GetParity
+  * @param  LPUARTx LPUART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPUART_PARITY_NONE
+  *         @arg @ref LL_LPUART_PARITY_EVEN
+  *         @arg @ref LL_LPUART_PARITY_ODD
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetParity(const USART_TypeDef *LPUARTx)
+{
+  return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE));
+}
+
+/**
+  * @brief  Set Receiver Wake Up method from Mute mode.
+  * @rmtoll CR1          WAKE          LL_LPUART_SetWakeUpMethod
+  * @param  LPUARTx LPUART Instance
+  * @param  Method This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_WAKEUP_IDLELINE
+  *         @arg @ref LL_LPUART_WAKEUP_ADDRESSMARK
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_SetWakeUpMethod(USART_TypeDef *LPUARTx, uint32_t Method)
+{
+  MODIFY_REG(LPUARTx->CR1, USART_CR1_WAKE, Method);
+}
+
+/**
+  * @brief  Return Receiver Wake Up method from Mute mode
+  * @rmtoll CR1          WAKE          LL_LPUART_GetWakeUpMethod
+  * @param  LPUARTx LPUART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPUART_WAKEUP_IDLELINE
+  *         @arg @ref LL_LPUART_WAKEUP_ADDRESSMARK
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetWakeUpMethod(const USART_TypeDef *LPUARTx)
+{
+  return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_WAKE));
+}
+
+/**
+  * @brief  Set Word length (nb of data bits, excluding start and stop bits)
+  * @rmtoll CR1          M             LL_LPUART_SetDataWidth
+  * @param  LPUARTx LPUART Instance
+  * @param  DataWidth This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_DATAWIDTH_7B
+  *         @arg @ref LL_LPUART_DATAWIDTH_8B
+  *         @arg @ref LL_LPUART_DATAWIDTH_9B
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_SetDataWidth(USART_TypeDef *LPUARTx, uint32_t DataWidth)
+{
+  MODIFY_REG(LPUARTx->CR1, USART_CR1_M, DataWidth);
+}
+
+/**
+  * @brief  Return Word length (i.e. nb of data bits, excluding start and stop bits)
+  * @rmtoll CR1          M             LL_LPUART_GetDataWidth
+  * @param  LPUARTx LPUART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPUART_DATAWIDTH_7B
+  *         @arg @ref LL_LPUART_DATAWIDTH_8B
+  *         @arg @ref LL_LPUART_DATAWIDTH_9B
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetDataWidth(const USART_TypeDef *LPUARTx)
+{
+  return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_M));
+}
+
+/**
+  * @brief  Allow switch between Mute Mode and Active mode
+  * @rmtoll CR1          MME           LL_LPUART_EnableMuteMode
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableMuteMode(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_MME);
+}
+
+/**
+  * @brief  Prevent Mute Mode use. Set Receiver in active mode permanently.
+  * @rmtoll CR1          MME           LL_LPUART_DisableMuteMode
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableMuteMode(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_MME);
+}
+
+/**
+  * @brief  Indicate if switch between Mute Mode and Active mode is allowed
+  * @rmtoll CR1          MME           LL_LPUART_IsEnabledMuteMode
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledMuteMode(const USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->CR1, USART_CR1_MME) == (USART_CR1_MME)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Configure Clock source prescaler for baudrate generator and oversampling
+  * @rmtoll PRESC        PRESCALER     LL_LPUART_SetPrescaler
+  * @param  LPUARTx LPUART Instance
+  * @param  PrescalerValue This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_PRESCALER_DIV1
+  *         @arg @ref LL_LPUART_PRESCALER_DIV2
+  *         @arg @ref LL_LPUART_PRESCALER_DIV4
+  *         @arg @ref LL_LPUART_PRESCALER_DIV6
+  *         @arg @ref LL_LPUART_PRESCALER_DIV8
+  *         @arg @ref LL_LPUART_PRESCALER_DIV10
+  *         @arg @ref LL_LPUART_PRESCALER_DIV12
+  *         @arg @ref LL_LPUART_PRESCALER_DIV16
+  *         @arg @ref LL_LPUART_PRESCALER_DIV32
+  *         @arg @ref LL_LPUART_PRESCALER_DIV64
+  *         @arg @ref LL_LPUART_PRESCALER_DIV128
+  *         @arg @ref LL_LPUART_PRESCALER_DIV256
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_SetPrescaler(USART_TypeDef *LPUARTx, uint32_t PrescalerValue)
+{
+  MODIFY_REG(LPUARTx->PRESC, USART_PRESC_PRESCALER, (uint16_t)PrescalerValue);
+}
+
+/**
+  * @brief  Retrieve the Clock source prescaler for baudrate generator and oversampling
+  * @rmtoll PRESC        PRESCALER     LL_LPUART_GetPrescaler
+  * @param  LPUARTx LPUART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPUART_PRESCALER_DIV1
+  *         @arg @ref LL_LPUART_PRESCALER_DIV2
+  *         @arg @ref LL_LPUART_PRESCALER_DIV4
+  *         @arg @ref LL_LPUART_PRESCALER_DIV6
+  *         @arg @ref LL_LPUART_PRESCALER_DIV8
+  *         @arg @ref LL_LPUART_PRESCALER_DIV10
+  *         @arg @ref LL_LPUART_PRESCALER_DIV12
+  *         @arg @ref LL_LPUART_PRESCALER_DIV16
+  *         @arg @ref LL_LPUART_PRESCALER_DIV32
+  *         @arg @ref LL_LPUART_PRESCALER_DIV64
+  *         @arg @ref LL_LPUART_PRESCALER_DIV128
+  *         @arg @ref LL_LPUART_PRESCALER_DIV256
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetPrescaler(const USART_TypeDef *LPUARTx)
+{
+  return (uint32_t)(READ_BIT(LPUARTx->PRESC, USART_PRESC_PRESCALER));
+}
+
+/**
+  * @brief  Set the length of the stop bits
+  * @rmtoll CR2          STOP          LL_LPUART_SetStopBitsLength
+  * @param  LPUARTx LPUART Instance
+  * @param  StopBits This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_STOPBITS_1
+  *         @arg @ref LL_LPUART_STOPBITS_2
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_SetStopBitsLength(USART_TypeDef *LPUARTx, uint32_t StopBits)
+{
+  MODIFY_REG(LPUARTx->CR2, USART_CR2_STOP, StopBits);
+}
+
+/**
+  * @brief  Retrieve the length of the stop bits
+  * @rmtoll CR2          STOP          LL_LPUART_GetStopBitsLength
+  * @param  LPUARTx LPUART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPUART_STOPBITS_1
+  *         @arg @ref LL_LPUART_STOPBITS_2
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetStopBitsLength(const USART_TypeDef *LPUARTx)
+{
+  return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_STOP));
+}
+
+/**
+  * @brief  Configure Character frame format (Datawidth, Parity control, Stop Bits)
+  * @note   Call of this function is equivalent to following function call sequence :
+  *         - Data Width configuration using @ref LL_LPUART_SetDataWidth() function
+  *         - Parity Control and mode configuration using @ref LL_LPUART_SetParity() function
+  *         - Stop bits configuration using @ref LL_LPUART_SetStopBitsLength() function
+  * @rmtoll CR1          PS            LL_LPUART_ConfigCharacter\n
+  *         CR1          PCE           LL_LPUART_ConfigCharacter\n
+  *         CR1          M             LL_LPUART_ConfigCharacter\n
+  *         CR2          STOP          LL_LPUART_ConfigCharacter
+  * @param  LPUARTx LPUART Instance
+  * @param  DataWidth This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_DATAWIDTH_7B
+  *         @arg @ref LL_LPUART_DATAWIDTH_8B
+  *         @arg @ref LL_LPUART_DATAWIDTH_9B
+  * @param  Parity This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_PARITY_NONE
+  *         @arg @ref LL_LPUART_PARITY_EVEN
+  *         @arg @ref LL_LPUART_PARITY_ODD
+  * @param  StopBits This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_STOPBITS_1
+  *         @arg @ref LL_LPUART_STOPBITS_2
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_ConfigCharacter(USART_TypeDef *LPUARTx, uint32_t DataWidth, uint32_t Parity,
+                                               uint32_t StopBits)
+{
+  MODIFY_REG(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE | USART_CR1_M, Parity | DataWidth);
+  MODIFY_REG(LPUARTx->CR2, USART_CR2_STOP, StopBits);
+}
+
+/**
+  * @brief  Configure TX/RX pins swapping setting.
+  * @rmtoll CR2          SWAP          LL_LPUART_SetTXRXSwap
+  * @param  LPUARTx LPUART Instance
+  * @param  SwapConfig This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_TXRX_STANDARD
+  *         @arg @ref LL_LPUART_TXRX_SWAPPED
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_SetTXRXSwap(USART_TypeDef *LPUARTx, uint32_t SwapConfig)
+{
+  MODIFY_REG(LPUARTx->CR2, USART_CR2_SWAP, SwapConfig);
+}
+
+/**
+  * @brief  Retrieve TX/RX pins swapping configuration.
+  * @rmtoll CR2          SWAP          LL_LPUART_GetTXRXSwap
+  * @param  LPUARTx LPUART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPUART_TXRX_STANDARD
+  *         @arg @ref LL_LPUART_TXRX_SWAPPED
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetTXRXSwap(const USART_TypeDef *LPUARTx)
+{
+  return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_SWAP));
+}
+
+/**
+  * @brief  Configure RX pin active level logic
+  * @rmtoll CR2          RXINV         LL_LPUART_SetRXPinLevel
+  * @param  LPUARTx LPUART Instance
+  * @param  PinInvMethod This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_RXPIN_LEVEL_STANDARD
+  *         @arg @ref LL_LPUART_RXPIN_LEVEL_INVERTED
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_SetRXPinLevel(USART_TypeDef *LPUARTx, uint32_t PinInvMethod)
+{
+  MODIFY_REG(LPUARTx->CR2, USART_CR2_RXINV, PinInvMethod);
+}
+
+/**
+  * @brief  Retrieve RX pin active level logic configuration
+  * @rmtoll CR2          RXINV         LL_LPUART_GetRXPinLevel
+  * @param  LPUARTx LPUART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPUART_RXPIN_LEVEL_STANDARD
+  *         @arg @ref LL_LPUART_RXPIN_LEVEL_INVERTED
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetRXPinLevel(const USART_TypeDef *LPUARTx)
+{
+  return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_RXINV));
+}
+
+/**
+  * @brief  Configure TX pin active level logic
+  * @rmtoll CR2          TXINV         LL_LPUART_SetTXPinLevel
+  * @param  LPUARTx LPUART Instance
+  * @param  PinInvMethod This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_TXPIN_LEVEL_STANDARD
+  *         @arg @ref LL_LPUART_TXPIN_LEVEL_INVERTED
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_SetTXPinLevel(USART_TypeDef *LPUARTx, uint32_t PinInvMethod)
+{
+  MODIFY_REG(LPUARTx->CR2, USART_CR2_TXINV, PinInvMethod);
+}
+
+/**
+  * @brief  Retrieve TX pin active level logic configuration
+  * @rmtoll CR2          TXINV         LL_LPUART_GetTXPinLevel
+  * @param  LPUARTx LPUART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPUART_TXPIN_LEVEL_STANDARD
+  *         @arg @ref LL_LPUART_TXPIN_LEVEL_INVERTED
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetTXPinLevel(const USART_TypeDef *LPUARTx)
+{
+  return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_TXINV));
+}
+
+/**
+  * @brief  Configure Binary data logic.
+  *
+  * @note   Allow to define how Logical data from the data register are send/received :
+  *         either in positive/direct logic (1=H, 0=L) or in negative/inverse logic (1=L, 0=H)
+  * @rmtoll CR2          DATAINV       LL_LPUART_SetBinaryDataLogic
+  * @param  LPUARTx LPUART Instance
+  * @param  DataLogic This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_BINARY_LOGIC_POSITIVE
+  *         @arg @ref LL_LPUART_BINARY_LOGIC_NEGATIVE
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_SetBinaryDataLogic(USART_TypeDef *LPUARTx, uint32_t DataLogic)
+{
+  MODIFY_REG(LPUARTx->CR2, USART_CR2_DATAINV, DataLogic);
+}
+
+/**
+  * @brief  Retrieve Binary data configuration
+  * @rmtoll CR2          DATAINV       LL_LPUART_GetBinaryDataLogic
+  * @param  LPUARTx LPUART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPUART_BINARY_LOGIC_POSITIVE
+  *         @arg @ref LL_LPUART_BINARY_LOGIC_NEGATIVE
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetBinaryDataLogic(const USART_TypeDef *LPUARTx)
+{
+  return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_DATAINV));
+}
+
+/**
+  * @brief  Configure transfer bit order (either Less or Most Significant Bit First)
+  * @note   MSB First means data is transmitted/received with the MSB first, following the start bit.
+  *         LSB First means data is transmitted/received with data bit 0 first, following the start bit.
+  * @rmtoll CR2          MSBFIRST      LL_LPUART_SetTransferBitOrder
+  * @param  LPUARTx LPUART Instance
+  * @param  BitOrder This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_BITORDER_LSBFIRST
+  *         @arg @ref LL_LPUART_BITORDER_MSBFIRST
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_SetTransferBitOrder(USART_TypeDef *LPUARTx, uint32_t BitOrder)
+{
+  MODIFY_REG(LPUARTx->CR2, USART_CR2_MSBFIRST, BitOrder);
+}
+
+/**
+  * @brief  Return transfer bit order (either Less or Most Significant Bit First)
+  * @note   MSB First means data is transmitted/received with the MSB first, following the start bit.
+  *         LSB First means data is transmitted/received with data bit 0 first, following the start bit.
+  * @rmtoll CR2          MSBFIRST      LL_LPUART_GetTransferBitOrder
+  * @param  LPUARTx LPUART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPUART_BITORDER_LSBFIRST
+  *         @arg @ref LL_LPUART_BITORDER_MSBFIRST
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetTransferBitOrder(const USART_TypeDef *LPUARTx)
+{
+  return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_MSBFIRST));
+}
+
+/**
+  * @brief  Set Address of the LPUART node.
+  * @note   This is used in multiprocessor communication during Mute mode or Stop mode,
+  *         for wake up with address mark detection.
+  * @note   4bits address node is used when 4-bit Address Detection is selected in ADDM7.
+  *         (b7-b4 should be set to 0)
+  *         8bits address node is used when 7-bit Address Detection is selected in ADDM7.
+  *         (This is used in multiprocessor communication during Mute mode or Stop mode,
+  *         for wake up with 7-bit address mark detection.
+  *         The MSB of the character sent by the transmitter should be equal to 1.
+  *         It may also be used for character detection during normal reception,
+  *         Mute mode inactive (for example, end of block detection in ModBus protocol).
+  *         In this case, the whole received character (8-bit) is compared to the ADD[7:0]
+  *         value and CMF flag is set on match)
+  * @rmtoll CR2          ADD           LL_LPUART_ConfigNodeAddress\n
+  *         CR2          ADDM7         LL_LPUART_ConfigNodeAddress
+  * @param  LPUARTx LPUART Instance
+  * @param  AddressLen This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_ADDRESS_DETECT_4B
+  *         @arg @ref LL_LPUART_ADDRESS_DETECT_7B
+  * @param  NodeAddress 4 or 7 bit Address of the LPUART node.
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_ConfigNodeAddress(USART_TypeDef *LPUARTx, uint32_t AddressLen, uint32_t NodeAddress)
+{
+  MODIFY_REG(LPUARTx->CR2, USART_CR2_ADD | USART_CR2_ADDM7,
+             (uint32_t)(AddressLen | (NodeAddress << USART_CR2_ADD_Pos)));
+}
+
+/**
+  * @brief  Return 8 bit Address of the LPUART node as set in ADD field of CR2.
+  * @note   If 4-bit Address Detection is selected in ADDM7,
+  *         only 4bits (b3-b0) of returned value are relevant (b31-b4 are not relevant)
+  *         If 7-bit Address Detection is selected in ADDM7,
+  *         only 8bits (b7-b0) of returned value are relevant (b31-b8 are not relevant)
+  * @rmtoll CR2          ADD           LL_LPUART_GetNodeAddress
+  * @param  LPUARTx LPUART Instance
+  * @retval Address of the LPUART node (Value between Min_Data=0 and Max_Data=255)
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetNodeAddress(const USART_TypeDef *LPUARTx)
+{
+  return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_ADD) >> USART_CR2_ADD_Pos);
+}
+
+/**
+  * @brief  Return Length of Node Address used in Address Detection mode (7-bit or 4-bit)
+  * @rmtoll CR2          ADDM7         LL_LPUART_GetNodeAddressLen
+  * @param  LPUARTx LPUART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPUART_ADDRESS_DETECT_4B
+  *         @arg @ref LL_LPUART_ADDRESS_DETECT_7B
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetNodeAddressLen(const USART_TypeDef *LPUARTx)
+{
+  return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_ADDM7));
+}
+
+/**
+  * @brief  Enable RTS HW Flow Control
+  * @rmtoll CR3          RTSE          LL_LPUART_EnableRTSHWFlowCtrl
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableRTSHWFlowCtrl(USART_TypeDef *LPUARTx)
+{
+  SET_BIT(LPUARTx->CR3, USART_CR3_RTSE);
+}
+
+/**
+  * @brief  Disable RTS HW Flow Control
+  * @rmtoll CR3          RTSE          LL_LPUART_DisableRTSHWFlowCtrl
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableRTSHWFlowCtrl(USART_TypeDef *LPUARTx)
+{
+  CLEAR_BIT(LPUARTx->CR3, USART_CR3_RTSE);
+}
+
+/**
+  * @brief  Enable CTS HW Flow Control
+  * @rmtoll CR3          CTSE          LL_LPUART_EnableCTSHWFlowCtrl
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableCTSHWFlowCtrl(USART_TypeDef *LPUARTx)
+{
+  SET_BIT(LPUARTx->CR3, USART_CR3_CTSE);
+}
+
+/**
+  * @brief  Disable CTS HW Flow Control
+  * @rmtoll CR3          CTSE          LL_LPUART_DisableCTSHWFlowCtrl
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableCTSHWFlowCtrl(USART_TypeDef *LPUARTx)
+{
+  CLEAR_BIT(LPUARTx->CR3, USART_CR3_CTSE);
+}
+
+/**
+  * @brief  Configure HW Flow Control mode (both CTS and RTS)
+  * @rmtoll CR3          RTSE          LL_LPUART_SetHWFlowCtrl\n
+  *         CR3          CTSE          LL_LPUART_SetHWFlowCtrl
+  * @param  LPUARTx LPUART Instance
+  * @param  HardwareFlowControl This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_HWCONTROL_NONE
+  *         @arg @ref LL_LPUART_HWCONTROL_RTS
+  *         @arg @ref LL_LPUART_HWCONTROL_CTS
+  *         @arg @ref LL_LPUART_HWCONTROL_RTS_CTS
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_SetHWFlowCtrl(USART_TypeDef *LPUARTx, uint32_t HardwareFlowControl)
+{
+  MODIFY_REG(LPUARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE, HardwareFlowControl);
+}
+
+/**
+  * @brief  Return HW Flow Control configuration (both CTS and RTS)
+  * @rmtoll CR3          RTSE          LL_LPUART_GetHWFlowCtrl\n
+  *         CR3          CTSE          LL_LPUART_GetHWFlowCtrl
+  * @param  LPUARTx LPUART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPUART_HWCONTROL_NONE
+  *         @arg @ref LL_LPUART_HWCONTROL_RTS
+  *         @arg @ref LL_LPUART_HWCONTROL_CTS
+  *         @arg @ref LL_LPUART_HWCONTROL_RTS_CTS
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetHWFlowCtrl(const USART_TypeDef *LPUARTx)
+{
+  return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE));
+}
+
+/**
+  * @brief  Enable Overrun detection
+  * @rmtoll CR3          OVRDIS        LL_LPUART_EnableOverrunDetect
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableOverrunDetect(USART_TypeDef *LPUARTx)
+{
+  CLEAR_BIT(LPUARTx->CR3, USART_CR3_OVRDIS);
+}
+
+/**
+  * @brief  Disable Overrun detection
+  * @rmtoll CR3          OVRDIS        LL_LPUART_DisableOverrunDetect
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableOverrunDetect(USART_TypeDef *LPUARTx)
+{
+  SET_BIT(LPUARTx->CR3, USART_CR3_OVRDIS);
+}
+
+/**
+  * @brief  Indicate if Overrun detection is enabled
+  * @rmtoll CR3          OVRDIS        LL_LPUART_IsEnabledOverrunDetect
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledOverrunDetect(const USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->CR3, USART_CR3_OVRDIS) != USART_CR3_OVRDIS) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Select event type for Wake UP Interrupt Flag (WUS[1:0] bits)
+  * @rmtoll CR3          WUS           LL_LPUART_SetWKUPType
+  * @param  LPUARTx LPUART Instance
+  * @param  Type This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_WAKEUP_ON_ADDRESS
+  *         @arg @ref LL_LPUART_WAKEUP_ON_STARTBIT
+  *         @arg @ref LL_LPUART_WAKEUP_ON_RXNE
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_SetWKUPType(USART_TypeDef *LPUARTx, uint32_t Type)
+{
+  MODIFY_REG(LPUARTx->CR3, USART_CR3_WUS, Type);
+}
+
+/**
+  * @brief  Return event type for Wake UP Interrupt Flag (WUS[1:0] bits)
+  * @rmtoll CR3          WUS           LL_LPUART_GetWKUPType
+  * @param  LPUARTx LPUART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPUART_WAKEUP_ON_ADDRESS
+  *         @arg @ref LL_LPUART_WAKEUP_ON_STARTBIT
+  *         @arg @ref LL_LPUART_WAKEUP_ON_RXNE
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetWKUPType(const USART_TypeDef *LPUARTx)
+{
+  return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_WUS));
+}
+
+/**
+  * @brief  Configure LPUART BRR register for achieving expected Baud Rate value.
+  *
+  * @note   Compute and set LPUARTDIV value in BRR Register (full BRR content)
+  *         according to used Peripheral Clock and expected Baud Rate values
+  * @note   Peripheral clock and Baud Rate values provided as function parameters should be valid
+  *         (Baud rate value != 0).
+  * @note   Provided that LPUARTx_BRR must be > = 0x300 and LPUART_BRR is 20-bit,
+  *         a care should be taken when generating high baud rates using high PeriphClk
+  *         values. PeriphClk must be in the range [3 x BaudRate, 4096 x BaudRate].
+  * @rmtoll BRR          BRR           LL_LPUART_SetBaudRate
+  * @param  LPUARTx LPUART Instance
+  * @param  PeriphClk Peripheral Clock
+  * @param  PrescalerValue This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_PRESCALER_DIV1
+  *         @arg @ref LL_LPUART_PRESCALER_DIV2
+  *         @arg @ref LL_LPUART_PRESCALER_DIV4
+  *         @arg @ref LL_LPUART_PRESCALER_DIV6
+  *         @arg @ref LL_LPUART_PRESCALER_DIV8
+  *         @arg @ref LL_LPUART_PRESCALER_DIV10
+  *         @arg @ref LL_LPUART_PRESCALER_DIV12
+  *         @arg @ref LL_LPUART_PRESCALER_DIV16
+  *         @arg @ref LL_LPUART_PRESCALER_DIV32
+  *         @arg @ref LL_LPUART_PRESCALER_DIV64
+  *         @arg @ref LL_LPUART_PRESCALER_DIV128
+  *         @arg @ref LL_LPUART_PRESCALER_DIV256
+  * @param  BaudRate Baud Rate
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_SetBaudRate(USART_TypeDef *LPUARTx, uint32_t PeriphClk, uint32_t PrescalerValue,
+                                           uint32_t BaudRate)
+{
+  if (BaudRate != 0U)
+  {
+    LPUARTx->BRR = __LL_LPUART_DIV(PeriphClk, PrescalerValue, BaudRate);
+  }
+}
+
+/**
+  * @brief  Return current Baud Rate value, according to LPUARTDIV present in BRR register
+  *         (full BRR content), and to used Peripheral Clock values
+  * @note   In case of non-initialized or invalid value stored in BRR register, value 0 will be returned.
+  * @rmtoll BRR          BRR           LL_LPUART_GetBaudRate
+  * @param  LPUARTx LPUART Instance
+  * @param  PeriphClk Peripheral Clock
+  * @param  PrescalerValue This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_PRESCALER_DIV1
+  *         @arg @ref LL_LPUART_PRESCALER_DIV2
+  *         @arg @ref LL_LPUART_PRESCALER_DIV4
+  *         @arg @ref LL_LPUART_PRESCALER_DIV6
+  *         @arg @ref LL_LPUART_PRESCALER_DIV8
+  *         @arg @ref LL_LPUART_PRESCALER_DIV10
+  *         @arg @ref LL_LPUART_PRESCALER_DIV12
+  *         @arg @ref LL_LPUART_PRESCALER_DIV16
+  *         @arg @ref LL_LPUART_PRESCALER_DIV32
+  *         @arg @ref LL_LPUART_PRESCALER_DIV64
+  *         @arg @ref LL_LPUART_PRESCALER_DIV128
+  *         @arg @ref LL_LPUART_PRESCALER_DIV256
+  * @retval Baud Rate
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetBaudRate(const USART_TypeDef *LPUARTx, uint32_t PeriphClk,
+                                               uint32_t PrescalerValue)
+{
+  uint32_t lpuartdiv;
+  uint32_t brrresult;
+  uint32_t periphclkpresc = (uint32_t)(PeriphClk / (LPUART_PRESCALER_TAB[(uint16_t)PrescalerValue]));
+
+  lpuartdiv = LPUARTx->BRR & LPUART_BRR_MASK;
+
+  if (lpuartdiv >= LPUART_BRR_MIN_VALUE)
+  {
+    brrresult = (uint32_t)(((uint64_t)(periphclkpresc) * LPUART_LPUARTDIV_FREQ_MUL) / lpuartdiv);
+  }
+  else
+  {
+    brrresult = 0x0UL;
+  }
+
+  return (brrresult);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EF_Configuration_HalfDuplex Configuration functions related to Half Duplex feature
+  * @{
+  */
+
+/**
+  * @brief  Enable Single Wire Half-Duplex mode
+  * @rmtoll CR3          HDSEL         LL_LPUART_EnableHalfDuplex
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableHalfDuplex(USART_TypeDef *LPUARTx)
+{
+  SET_BIT(LPUARTx->CR3, USART_CR3_HDSEL);
+}
+
+/**
+  * @brief  Disable Single Wire Half-Duplex mode
+  * @rmtoll CR3          HDSEL         LL_LPUART_DisableHalfDuplex
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableHalfDuplex(USART_TypeDef *LPUARTx)
+{
+  CLEAR_BIT(LPUARTx->CR3, USART_CR3_HDSEL);
+}
+
+/**
+  * @brief  Indicate if Single Wire Half-Duplex mode is enabled
+  * @rmtoll CR3          HDSEL         LL_LPUART_IsEnabledHalfDuplex
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledHalfDuplex(const USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EF_Configuration_DE Configuration functions related to Driver Enable feature
+  * @{
+  */
+
+/**
+  * @brief  Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits).
+  * @rmtoll CR1          DEDT          LL_LPUART_SetDEDeassertionTime
+  * @param  LPUARTx LPUART Instance
+  * @param  Time Value between Min_Data=0 and Max_Data=31
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_SetDEDeassertionTime(USART_TypeDef *LPUARTx, uint32_t Time)
+{
+  MODIFY_REG(LPUARTx->CR1, USART_CR1_DEDT, Time << USART_CR1_DEDT_Pos);
+}
+
+/**
+  * @brief  Return DEDT (Driver Enable De-Assertion Time)
+  * @rmtoll CR1          DEDT          LL_LPUART_GetDEDeassertionTime
+  * @param  LPUARTx LPUART Instance
+  * @retval Time value expressed on 5 bits ([4:0] bits) : c
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetDEDeassertionTime(const USART_TypeDef *LPUARTx)
+{
+  return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_DEDT) >> USART_CR1_DEDT_Pos);
+}
+
+/**
+  * @brief  Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits).
+  * @rmtoll CR1          DEAT          LL_LPUART_SetDEAssertionTime
+  * @param  LPUARTx LPUART Instance
+  * @param  Time Value between Min_Data=0 and Max_Data=31
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_SetDEAssertionTime(USART_TypeDef *LPUARTx, uint32_t Time)
+{
+  MODIFY_REG(LPUARTx->CR1, USART_CR1_DEAT, Time << USART_CR1_DEAT_Pos);
+}
+
+/**
+  * @brief  Return DEAT (Driver Enable Assertion Time)
+  * @rmtoll CR1          DEAT          LL_LPUART_GetDEAssertionTime
+  * @param  LPUARTx LPUART Instance
+  * @retval Time value expressed on 5 bits ([4:0] bits) : Time Value between Min_Data=0 and Max_Data=31
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetDEAssertionTime(const USART_TypeDef *LPUARTx)
+{
+  return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_DEAT) >> USART_CR1_DEAT_Pos);
+}
+
+/**
+  * @brief  Enable Driver Enable (DE) Mode
+  * @rmtoll CR3          DEM           LL_LPUART_EnableDEMode
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableDEMode(USART_TypeDef *LPUARTx)
+{
+  SET_BIT(LPUARTx->CR3, USART_CR3_DEM);
+}
+
+/**
+  * @brief  Disable Driver Enable (DE) Mode
+  * @rmtoll CR3          DEM           LL_LPUART_DisableDEMode
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableDEMode(USART_TypeDef *LPUARTx)
+{
+  CLEAR_BIT(LPUARTx->CR3, USART_CR3_DEM);
+}
+
+/**
+  * @brief  Indicate if Driver Enable (DE) Mode is enabled
+  * @rmtoll CR3          DEM           LL_LPUART_IsEnabledDEMode
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDEMode(const USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->CR3, USART_CR3_DEM) == (USART_CR3_DEM)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Select Driver Enable Polarity
+  * @rmtoll CR3          DEP           LL_LPUART_SetDESignalPolarity
+  * @param  LPUARTx LPUART Instance
+  * @param  Polarity This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_DE_POLARITY_HIGH
+  *         @arg @ref LL_LPUART_DE_POLARITY_LOW
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_SetDESignalPolarity(USART_TypeDef *LPUARTx, uint32_t Polarity)
+{
+  MODIFY_REG(LPUARTx->CR3, USART_CR3_DEP, Polarity);
+}
+
+/**
+  * @brief  Return Driver Enable Polarity
+  * @rmtoll CR3          DEP           LL_LPUART_GetDESignalPolarity
+  * @param  LPUARTx LPUART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPUART_DE_POLARITY_HIGH
+  *         @arg @ref LL_LPUART_DE_POLARITY_LOW
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetDESignalPolarity(const USART_TypeDef *LPUARTx)
+{
+  return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_DEP));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EF_FLAG_Management FLAG_Management
+  * @{
+  */
+
+/**
+  * @brief  Check if the LPUART Parity Error Flag is set or not
+  * @rmtoll ISR          PE            LL_LPUART_IsActiveFlag_PE
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_PE(const USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->ISR, USART_ISR_PE) == (USART_ISR_PE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the LPUART Framing Error Flag is set or not
+  * @rmtoll ISR          FE            LL_LPUART_IsActiveFlag_FE
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_FE(const USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->ISR, USART_ISR_FE) == (USART_ISR_FE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the LPUART Noise error detected Flag is set or not
+  * @rmtoll ISR          NE            LL_LPUART_IsActiveFlag_NE
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_NE(const USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->ISR, USART_ISR_NE) == (USART_ISR_NE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the LPUART OverRun Error Flag is set or not
+  * @rmtoll ISR          ORE           LL_LPUART_IsActiveFlag_ORE
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_ORE(const USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->ISR, USART_ISR_ORE) == (USART_ISR_ORE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the LPUART IDLE line detected Flag is set or not
+  * @rmtoll ISR          IDLE          LL_LPUART_IsActiveFlag_IDLE
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_IDLE(const USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE)) ? 1UL : 0UL);
+}
+
+#define LL_LPUART_IsActiveFlag_RXNE  LL_LPUART_IsActiveFlag_RXNE_RXFNE /* Redefinition for legacy purpose */
+
+/**
+  * @brief  Check if the LPUART Read Data Register or LPUART RX FIFO Not Empty Flag is set or not
+  * @rmtoll ISR          RXNE_RXFNE    LL_LPUART_IsActiveFlag_RXNE_RXFNE
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXNE_RXFNE(const USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->ISR, USART_ISR_RXNE_RXFNE) == (USART_ISR_RXNE_RXFNE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the LPUART Transmission Complete Flag is set or not
+  * @rmtoll ISR          TC            LL_LPUART_IsActiveFlag_TC
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TC(const USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->ISR, USART_ISR_TC) == (USART_ISR_TC)) ? 1UL : 0UL);
+}
+
+#define LL_LPUART_IsActiveFlag_TXE  LL_LPUART_IsActiveFlag_TXE_TXFNF /* Redefinition for legacy purpose */
+
+/**
+  * @brief  Check if the LPUART Transmit Data Register Empty or LPUART TX FIFO Not Full Flag is set or not
+  * @rmtoll ISR          TXE_TXFNF     LL_LPUART_IsActiveFlag_TXE_TXFNF
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXE_TXFNF(const USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->ISR, USART_ISR_TXE_TXFNF) == (USART_ISR_TXE_TXFNF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the LPUART CTS interrupt Flag is set or not
+  * @rmtoll ISR          CTSIF         LL_LPUART_IsActiveFlag_nCTS
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_nCTS(const USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->ISR, USART_ISR_CTSIF) == (USART_ISR_CTSIF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the LPUART CTS Flag is set or not
+  * @rmtoll ISR          CTS           LL_LPUART_IsActiveFlag_CTS
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CTS(const USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->ISR, USART_ISR_CTS) == (USART_ISR_CTS)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the LPUART Busy Flag is set or not
+  * @rmtoll ISR          BUSY          LL_LPUART_IsActiveFlag_BUSY
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_BUSY(const USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->ISR, USART_ISR_BUSY) == (USART_ISR_BUSY)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the LPUART Character Match Flag is set or not
+  * @rmtoll ISR          CMF           LL_LPUART_IsActiveFlag_CM
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CM(const USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->ISR, USART_ISR_CMF) == (USART_ISR_CMF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the LPUART Send Break Flag is set or not
+  * @rmtoll ISR          SBKF          LL_LPUART_IsActiveFlag_SBK
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_SBK(const USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->ISR, USART_ISR_SBKF) == (USART_ISR_SBKF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the LPUART Receive Wake Up from mute mode Flag is set or not
+  * @rmtoll ISR          RWU           LL_LPUART_IsActiveFlag_RWU
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RWU(const USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->ISR, USART_ISR_RWU) == (USART_ISR_RWU)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the LPUART Wake Up from stop mode Flag is set or not
+  * @rmtoll ISR          WUF           LL_LPUART_IsActiveFlag_WKUP
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_WKUP(const USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->ISR, USART_ISR_WUF) == (USART_ISR_WUF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the LPUART Transmit Enable Acknowledge Flag is set or not
+  * @rmtoll ISR          TEACK         LL_LPUART_IsActiveFlag_TEACK
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TEACK(const USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->ISR, USART_ISR_TEACK) == (USART_ISR_TEACK)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the LPUART Receive Enable Acknowledge Flag is set or not
+  * @rmtoll ISR          REACK         LL_LPUART_IsActiveFlag_REACK
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_REACK(const USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->ISR, USART_ISR_REACK) == (USART_ISR_REACK)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the LPUART TX FIFO Empty Flag is set or not
+  * @rmtoll ISR          TXFE          LL_LPUART_IsActiveFlag_TXFE
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXFE(const USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->ISR, USART_ISR_TXFE) == (USART_ISR_TXFE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the LPUART RX FIFO Full Flag is set or not
+  * @rmtoll ISR          RXFF          LL_LPUART_IsActiveFlag_RXFF
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXFF(const USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->ISR, USART_ISR_RXFF) == (USART_ISR_RXFF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the LPUART TX FIFO Threshold Flag is set or not
+  * @rmtoll ISR          TXFT          LL_LPUART_IsActiveFlag_TXFT
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXFT(const USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->ISR, USART_ISR_TXFT) == (USART_ISR_TXFT)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the LPUART RX FIFO Threshold Flag is set or not
+  * @rmtoll ISR          RXFT          LL_LPUART_IsActiveFlag_RXFT
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXFT(const USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->ISR, USART_ISR_RXFT) == (USART_ISR_RXFT)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear Parity Error Flag
+  * @rmtoll ICR          PECF          LL_LPUART_ClearFlag_PE
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_ClearFlag_PE(USART_TypeDef *LPUARTx)
+{
+  WRITE_REG(LPUARTx->ICR, USART_ICR_PECF);
+}
+
+/**
+  * @brief  Clear Framing Error Flag
+  * @rmtoll ICR          FECF          LL_LPUART_ClearFlag_FE
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_ClearFlag_FE(USART_TypeDef *LPUARTx)
+{
+  WRITE_REG(LPUARTx->ICR, USART_ICR_FECF);
+}
+
+/**
+  * @brief  Clear Noise detected Flag
+  * @rmtoll ICR          NECF          LL_LPUART_ClearFlag_NE
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_ClearFlag_NE(USART_TypeDef *LPUARTx)
+{
+  WRITE_REG(LPUARTx->ICR, USART_ICR_NECF);
+}
+
+/**
+  * @brief  Clear OverRun Error Flag
+  * @rmtoll ICR          ORECF         LL_LPUART_ClearFlag_ORE
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_ClearFlag_ORE(USART_TypeDef *LPUARTx)
+{
+  WRITE_REG(LPUARTx->ICR, USART_ICR_ORECF);
+}
+
+/**
+  * @brief  Clear IDLE line detected Flag
+  * @rmtoll ICR          IDLECF        LL_LPUART_ClearFlag_IDLE
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_ClearFlag_IDLE(USART_TypeDef *LPUARTx)
+{
+  WRITE_REG(LPUARTx->ICR, USART_ICR_IDLECF);
+}
+
+/**
+  * @brief  Clear Transmission Complete Flag
+  * @rmtoll ICR          TCCF          LL_LPUART_ClearFlag_TC
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_ClearFlag_TC(USART_TypeDef *LPUARTx)
+{
+  WRITE_REG(LPUARTx->ICR, USART_ICR_TCCF);
+}
+
+/**
+  * @brief  Clear CTS Interrupt Flag
+  * @rmtoll ICR          CTSCF         LL_LPUART_ClearFlag_nCTS
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_ClearFlag_nCTS(USART_TypeDef *LPUARTx)
+{
+  WRITE_REG(LPUARTx->ICR, USART_ICR_CTSCF);
+}
+
+/**
+  * @brief  Clear Character Match Flag
+  * @rmtoll ICR          CMCF          LL_LPUART_ClearFlag_CM
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_ClearFlag_CM(USART_TypeDef *LPUARTx)
+{
+  WRITE_REG(LPUARTx->ICR, USART_ICR_CMCF);
+}
+
+/**
+  * @brief  Clear Wake Up from stop mode Flag
+  * @rmtoll ICR          WUCF          LL_LPUART_ClearFlag_WKUP
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_ClearFlag_WKUP(USART_TypeDef *LPUARTx)
+{
+  WRITE_REG(LPUARTx->ICR, USART_ICR_WUCF);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EF_IT_Management IT_Management
+  * @{
+  */
+
+/**
+  * @brief  Enable IDLE Interrupt
+  * @rmtoll CR1          IDLEIE        LL_LPUART_EnableIT_IDLE
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableIT_IDLE(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_IDLEIE);
+}
+
+#define LL_LPUART_EnableIT_RXNE  LL_LPUART_EnableIT_RXNE_RXFNE /* Redefinition for legacy purpose */
+
+/**
+  * @brief  Enable RX Not Empty and RX FIFO Not Empty Interrupt
+  * @rmtoll CR1        RXNEIE_RXFNEIE  LL_LPUART_EnableIT_RXNE_RXFNE
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableIT_RXNE_RXFNE(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE);
+}
+
+/**
+  * @brief  Enable Transmission Complete Interrupt
+  * @rmtoll CR1          TCIE          LL_LPUART_EnableIT_TC
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableIT_TC(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TCIE);
+}
+
+#define LL_LPUART_EnableIT_TXE  LL_LPUART_EnableIT_TXE_TXFNF /* Redefinition for legacy purpose */
+
+/**
+  * @brief  Enable TX Empty and TX FIFO Not Full Interrupt
+  * @rmtoll CR1         TXEIE_TXFNFIE  LL_LPUART_EnableIT_TXE_TXFNF
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableIT_TXE_TXFNF(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE);
+}
+
+/**
+  * @brief  Enable Parity Error Interrupt
+  * @rmtoll CR1          PEIE          LL_LPUART_EnableIT_PE
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableIT_PE(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_PEIE);
+}
+
+/**
+  * @brief  Enable Character Match Interrupt
+  * @rmtoll CR1          CMIE          LL_LPUART_EnableIT_CM
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableIT_CM(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_CMIE);
+}
+
+/**
+  * @brief  Enable TX FIFO Empty Interrupt
+  * @rmtoll CR1          TXFEIE        LL_LPUART_EnableIT_TXFE
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableIT_TXFE(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TXFEIE);
+}
+
+/**
+  * @brief  Enable RX FIFO Full Interrupt
+  * @rmtoll CR1          RXFFIE        LL_LPUART_EnableIT_RXFF
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableIT_RXFF(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_RXFFIE);
+}
+
+/**
+  * @brief  Enable Error Interrupt
+  * @note   When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
+  *         error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register).
+  *         - 0: Interrupt is inhibited
+  *         - 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register.
+  * @rmtoll CR3          EIE           LL_LPUART_EnableIT_ERROR
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableIT_ERROR(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_EIE);
+}
+
+/**
+  * @brief  Enable CTS Interrupt
+  * @rmtoll CR3          CTSIE         LL_LPUART_EnableIT_CTS
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableIT_CTS(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_CTSIE);
+}
+
+/**
+  * @brief  Enable Wake Up from Stop Mode Interrupt
+  * @rmtoll CR3          WUFIE         LL_LPUART_EnableIT_WKUP
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableIT_WKUP(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_WUFIE);
+}
+
+/**
+  * @brief  Enable TX FIFO Threshold Interrupt
+  * @rmtoll CR3          TXFTIE        LL_LPUART_EnableIT_TXFT
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableIT_TXFT(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_TXFTIE);
+}
+
+/**
+  * @brief  Enable RX FIFO Threshold Interrupt
+  * @rmtoll CR3          RXFTIE        LL_LPUART_EnableIT_RXFT
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableIT_RXFT(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_RXFTIE);
+}
+
+/**
+  * @brief  Disable IDLE Interrupt
+  * @rmtoll CR1          IDLEIE        LL_LPUART_DisableIT_IDLE
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableIT_IDLE(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_IDLEIE);
+}
+
+#define LL_LPUART_DisableIT_RXNE  LL_LPUART_DisableIT_RXNE_RXFNE /* Redefinition for legacy purpose */
+
+/**
+  * @brief  Disable RX Not Empty and RX FIFO Not Empty Interrupt
+  * @rmtoll CR1        RXNEIE_RXFNEIE  LL_LPUART_DisableIT_RXNE_RXFNE
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableIT_RXNE_RXFNE(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE);
+}
+
+/**
+  * @brief  Disable Transmission Complete Interrupt
+  * @rmtoll CR1          TCIE          LL_LPUART_DisableIT_TC
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableIT_TC(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TCIE);
+}
+
+#define LL_LPUART_DisableIT_TXE  LL_LPUART_DisableIT_TXE_TXFNF /* Redefinition for legacy purpose */
+
+/**
+  * @brief  Disable TX Empty and TX FIFO Not Full Interrupt
+  * @rmtoll CR1        TXEIE_TXFNFIE  LL_LPUART_DisableIT_TXE_TXFNF
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableIT_TXE_TXFNF(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE);
+}
+
+/**
+  * @brief  Disable Parity Error Interrupt
+  * @rmtoll CR1          PEIE          LL_LPUART_DisableIT_PE
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableIT_PE(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_PEIE);
+}
+
+/**
+  * @brief  Disable Character Match Interrupt
+  * @rmtoll CR1          CMIE          LL_LPUART_DisableIT_CM
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableIT_CM(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_CMIE);
+}
+
+/**
+  * @brief  Disable TX FIFO Empty Interrupt
+  * @rmtoll CR1          TXFEIE        LL_LPUART_DisableIT_TXFE
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableIT_TXFE(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TXFEIE);
+}
+
+/**
+  * @brief  Disable RX FIFO Full Interrupt
+  * @rmtoll CR1          RXFFIE        LL_LPUART_DisableIT_RXFF
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableIT_RXFF(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_RXFFIE);
+}
+
+/**
+  * @brief  Disable Error Interrupt
+  * @note   When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
+  *         error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register).
+  *         - 0: Interrupt is inhibited
+  *         - 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register.
+  * @rmtoll CR3          EIE           LL_LPUART_DisableIT_ERROR
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableIT_ERROR(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_EIE);
+}
+
+/**
+  * @brief  Disable CTS Interrupt
+  * @rmtoll CR3          CTSIE         LL_LPUART_DisableIT_CTS
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableIT_CTS(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_CTSIE);
+}
+
+/**
+  * @brief  Disable Wake Up from Stop Mode Interrupt
+  * @rmtoll CR3          WUFIE         LL_LPUART_DisableIT_WKUP
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableIT_WKUP(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_WUFIE);
+}
+
+/**
+  * @brief  Disable TX FIFO Threshold Interrupt
+  * @rmtoll CR3          TXFTIE        LL_LPUART_DisableIT_TXFT
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableIT_TXFT(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_TXFTIE);
+}
+
+/**
+  * @brief  Disable RX FIFO Threshold Interrupt
+  * @rmtoll CR3          RXFTIE        LL_LPUART_DisableIT_RXFT
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableIT_RXFT(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_RXFTIE);
+}
+
+/**
+  * @brief  Check if the LPUART IDLE Interrupt  source is enabled or disabled.
+  * @rmtoll CR1          IDLEIE        LL_LPUART_IsEnabledIT_IDLE
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_IDLE(const USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE)) ? 1UL : 0UL);
+}
+
+#define LL_LPUART_IsEnabledIT_RXNE  LL_LPUART_IsEnabledIT_RXNE_RXFNE /* Redefinition for legacy purpose */
+
+/**
+  * @brief  Check if the LPUART RX Not Empty and LPUART RX FIFO Not Empty Interrupt is enabled or disabled.
+  * @rmtoll CR1        RXNEIE_RXFNEIE  LL_LPUART_IsEnabledIT_RXNE_RXFNE
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXNE_RXFNE(const USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE) == (USART_CR1_RXNEIE_RXFNEIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the LPUART Transmission Complete Interrupt is enabled or disabled.
+  * @rmtoll CR1          TCIE          LL_LPUART_IsEnabledIT_TC
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TC(const USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE)) ? 1UL : 0UL);
+}
+
+#define LL_LPUART_IsEnabledIT_TXE  LL_LPUART_IsEnabledIT_TXE_TXFNF /* Redefinition for legacy purpose */
+
+/**
+  * @brief  Check if the LPUART TX Empty and LPUART TX FIFO Not Full Interrupt is enabled or disabled
+  * @rmtoll CR1         TXEIE_TXFNFIE  LL_LPUART_IsEnabledIT_TXE_TXFNF
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXE_TXFNF(const USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE) == (USART_CR1_TXEIE_TXFNFIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the LPUART Parity Error Interrupt is enabled or disabled.
+  * @rmtoll CR1          PEIE          LL_LPUART_IsEnabledIT_PE
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_PE(const USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the LPUART Character Match Interrupt is enabled or disabled.
+  * @rmtoll CR1          CMIE          LL_LPUART_IsEnabledIT_CM
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CM(const USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->CR1, USART_CR1_CMIE) == (USART_CR1_CMIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the LPUART TX FIFO Empty Interrupt is enabled or disabled
+  * @rmtoll CR1          TXFEIE        LL_LPUART_IsEnabledIT_TXFE
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXFE(const USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->CR1, USART_CR1_TXFEIE) == (USART_CR1_TXFEIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the LPUART RX FIFO Full Interrupt is enabled or disabled
+  * @rmtoll CR1          RXFFIE        LL_LPUART_IsEnabledIT_RXFF
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXFF(const USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->CR1, USART_CR1_RXFFIE) == (USART_CR1_RXFFIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the LPUART Error Interrupt is enabled or disabled.
+  * @rmtoll CR3          EIE           LL_LPUART_IsEnabledIT_ERROR
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_ERROR(const USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the LPUART CTS Interrupt is enabled or disabled.
+  * @rmtoll CR3          CTSIE         LL_LPUART_IsEnabledIT_CTS
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CTS(const USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the LPUART Wake Up from Stop Mode Interrupt is enabled or disabled.
+  * @rmtoll CR3          WUFIE         LL_LPUART_IsEnabledIT_WKUP
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_WKUP(const USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->CR3, USART_CR3_WUFIE) == (USART_CR3_WUFIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if LPUART TX FIFO Threshold Interrupt is enabled or disabled
+  * @rmtoll CR3          TXFTIE        LL_LPUART_IsEnabledIT_TXFT
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXFT(const USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->CR3, USART_CR3_TXFTIE) == (USART_CR3_TXFTIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if LPUART RX FIFO Threshold Interrupt is enabled or disabled
+  * @rmtoll CR3          RXFTIE        LL_LPUART_IsEnabledIT_RXFT
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXFT(const USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->CR3, USART_CR3_RXFTIE) == (USART_CR3_RXFTIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EF_DMA_Management DMA_Management
+  * @{
+  */
+
+/**
+  * @brief  Enable DMA Mode for reception
+  * @rmtoll CR3          DMAR          LL_LPUART_EnableDMAReq_RX
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableDMAReq_RX(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_DMAR);
+}
+
+/**
+  * @brief  Disable DMA Mode for reception
+  * @rmtoll CR3          DMAR          LL_LPUART_DisableDMAReq_RX
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableDMAReq_RX(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_DMAR);
+}
+
+/**
+  * @brief  Check if DMA Mode is enabled for reception
+  * @rmtoll CR3          DMAR          LL_LPUART_IsEnabledDMAReq_RX
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_RX(const USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable DMA Mode for transmission
+  * @rmtoll CR3          DMAT          LL_LPUART_EnableDMAReq_TX
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableDMAReq_TX(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_DMAT);
+}
+
+/**
+  * @brief  Disable DMA Mode for transmission
+  * @rmtoll CR3          DMAT          LL_LPUART_DisableDMAReq_TX
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableDMAReq_TX(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_DMAT);
+}
+
+/**
+  * @brief  Check if DMA Mode is enabled for transmission
+  * @rmtoll CR3          DMAT          LL_LPUART_IsEnabledDMAReq_TX
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_TX(const USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable DMA Disabling on Reception Error
+  * @rmtoll CR3          DDRE          LL_LPUART_EnableDMADeactOnRxErr
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableDMADeactOnRxErr(USART_TypeDef *LPUARTx)
+{
+  SET_BIT(LPUARTx->CR3, USART_CR3_DDRE);
+}
+
+/**
+  * @brief  Disable DMA Disabling on Reception Error
+  * @rmtoll CR3          DDRE          LL_LPUART_DisableDMADeactOnRxErr
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableDMADeactOnRxErr(USART_TypeDef *LPUARTx)
+{
+  CLEAR_BIT(LPUARTx->CR3, USART_CR3_DDRE);
+}
+
+/**
+  * @brief  Indicate if DMA Disabling on Reception Error is disabled
+  * @rmtoll CR3          DDRE          LL_LPUART_IsEnabledDMADeactOnRxErr
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMADeactOnRxErr(const USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->CR3, USART_CR3_DDRE) == (USART_CR3_DDRE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get the LPUART data register address used for DMA transfer
+  * @rmtoll RDR          RDR           LL_LPUART_DMA_GetRegAddr\n
+  * @rmtoll TDR          TDR           LL_LPUART_DMA_GetRegAddr
+  * @param  LPUARTx LPUART Instance
+  * @param  Direction This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_DMA_REG_DATA_TRANSMIT
+  *         @arg @ref LL_LPUART_DMA_REG_DATA_RECEIVE
+  * @retval Address of data register
+  */
+__STATIC_INLINE uint32_t LL_LPUART_DMA_GetRegAddr(const USART_TypeDef *LPUARTx, uint32_t Direction)
+{
+  uint32_t data_reg_addr;
+
+  if (Direction == LL_LPUART_DMA_REG_DATA_TRANSMIT)
+  {
+    /* return address of TDR register */
+    data_reg_addr = (uint32_t) &(LPUARTx->TDR);
+  }
+  else
+  {
+    /* return address of RDR register */
+    data_reg_addr = (uint32_t) &(LPUARTx->RDR);
+  }
+
+  return data_reg_addr;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EF_Data_Management Data_Management
+  * @{
+  */
+
+/**
+  * @brief  Read Receiver Data register (Receive Data value, 8 bits)
+  * @rmtoll RDR          RDR           LL_LPUART_ReceiveData8
+  * @param  LPUARTx LPUART Instance
+  * @retval Time Value between Min_Data=0x00 and Max_Data=0xFF
+  */
+__STATIC_INLINE uint8_t LL_LPUART_ReceiveData8(const USART_TypeDef *LPUARTx)
+{
+  return (uint8_t)(READ_BIT(LPUARTx->RDR, USART_RDR_RDR) & 0xFFU);
+}
+
+/**
+  * @brief  Read Receiver Data register (Receive Data value, 9 bits)
+  * @rmtoll RDR          RDR           LL_LPUART_ReceiveData9
+  * @param  LPUARTx LPUART Instance
+  * @retval Time Value between Min_Data=0x00 and Max_Data=0x1FF
+  */
+__STATIC_INLINE uint16_t LL_LPUART_ReceiveData9(const USART_TypeDef *LPUARTx)
+{
+  return (uint16_t)(READ_BIT(LPUARTx->RDR, USART_RDR_RDR));
+}
+
+/**
+  * @brief  Write in Transmitter Data Register (Transmit Data value, 8 bits)
+  * @rmtoll TDR          TDR           LL_LPUART_TransmitData8
+  * @param  LPUARTx LPUART Instance
+  * @param  Value between Min_Data=0x00 and Max_Data=0xFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_TransmitData8(USART_TypeDef *LPUARTx, uint8_t Value)
+{
+  LPUARTx->TDR = Value;
+}
+
+/**
+  * @brief  Write in Transmitter Data Register (Transmit Data value, 9 bits)
+  * @rmtoll TDR          TDR           LL_LPUART_TransmitData9
+  * @param  LPUARTx LPUART Instance
+  * @param  Value between Min_Data=0x00 and Max_Data=0x1FF
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_TransmitData9(USART_TypeDef *LPUARTx, uint16_t Value)
+{
+  LPUARTx->TDR = Value & 0x1FFUL;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EF_Execution Execution
+  * @{
+  */
+
+/**
+  * @brief  Request Break sending
+  * @rmtoll RQR          SBKRQ         LL_LPUART_RequestBreakSending
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_RequestBreakSending(USART_TypeDef *LPUARTx)
+{
+  SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_SBKRQ);
+}
+
+/**
+  * @brief  Put LPUART in mute mode and set the RWU flag
+  * @rmtoll RQR          MMRQ          LL_LPUART_RequestEnterMuteMode
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_RequestEnterMuteMode(USART_TypeDef *LPUARTx)
+{
+  SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_MMRQ);
+}
+
+/**
+  * @brief  Request a Receive Data and FIFO flush
+  * @note   Allows to discard the received data without reading them, and avoid an overrun
+  *         condition.
+  * @rmtoll RQR          RXFRQ         LL_LPUART_RequestRxDataFlush
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_RequestRxDataFlush(USART_TypeDef *LPUARTx)
+{
+  SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_RXFRQ);
+}
+
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup LPUART_LL_EF_Init Initialization and de-initialization functions
+  * @{
+  */
+ErrorStatus LL_LPUART_DeInit(const USART_TypeDef *LPUARTx);
+ErrorStatus LL_LPUART_Init(USART_TypeDef *LPUARTx, const LL_LPUART_InitTypeDef *LPUART_InitStruct);
+void        LL_LPUART_StructInit(LL_LPUART_InitTypeDef *LPUART_InitStruct);
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* LPUART1 */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32H7xx_LL_LPUART_H */
+
diff --git a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h
new file mode 100644
index 0000000..6e12084
--- /dev/null
+++ b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h
@@ -0,0 +1,1117 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_ll_sdmmc.h
+  * @author  MCD Application Team
+  * @brief   Header file of SDMMC HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_LL_SDMMC_H
+#define STM32H7xx_LL_SDMMC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal_def.h"
+
+/** @addtogroup STM32H7xx_Driver
+  * @{
+  */
+
+/** @addtogroup SDMMC_LL
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup SDMMC_LL_Exported_Types SDMMC_LL Exported Types
+  * @{
+  */
+
+/**
+  * @brief  SDMMC Configuration Structure definition
+  */
+typedef struct
+{
+  uint32_t ClockEdge;            /*!< Specifies the SDMMC_CCK clock transition on which Data and Command change.
+                                      This parameter can be a value of @ref SDMMC_LL_Clock_Edge                 */
+
+  uint32_t ClockPowerSave;       /*!< Specifies whether SDMMC Clock output is enabled or
+                                      disabled when the bus is idle.
+                                      This parameter can be a value of @ref SDMMC_LL_Clock_Power_Save           */
+
+  uint32_t BusWide;              /*!< Specifies the SDMMC bus width.
+                                      This parameter can be a value of @ref SDMMC_LL_Bus_Wide                   */
+
+  uint32_t HardwareFlowControl;  /*!< Specifies whether the SDMMC hardware flow control is enabled or disabled.
+                                      This parameter can be a value of @ref SDMMC_LL_Hardware_Flow_Control      */
+
+  uint32_t ClockDiv;             /*!< Specifies the clock frequency of the SDMMC controller.
+                                      This parameter can be a value between Min_Data = 0 and Max_Data = 1023   */
+
+#if (USE_SD_TRANSCEIVER != 0U)
+  uint32_t TranceiverPresent;    /*!< Specifies if there is a 1V8 Transceiver/Switcher.
+                                      This parameter can be a value of @ref SDMMC_LL_TRANSCEIVER_PRESENT       */
+#endif /* USE_SD_TRANSCEIVER */
+} SDMMC_InitTypeDef;
+
+
+/**
+  * @brief  SDMMC Command Control structure
+  */
+typedef struct
+{
+  uint32_t Argument;            /*!< Specifies the SDMMC command argument which is sent
+                                     to a card as part of a command message. If a command
+                                     contains an argument, it must be loaded into this register
+                                     before writing the command to the command register.              */
+
+  uint32_t CmdIndex;            /*!< Specifies the SDMMC command index. It must be Min_Data = 0 and
+                                     Max_Data = 64                                                    */
+
+  uint32_t Response;            /*!< Specifies the SDMMC response type.
+                                     This parameter can be a value of @ref SDMMC_LL_Response_Type         */
+
+  uint32_t WaitForInterrupt;    /*!< Specifies whether SDMMC wait for interrupt request is
+                                     enabled or disabled.
+                                     This parameter can be a value of @ref SDMMC_LL_Wait_Interrupt_State  */
+
+  uint32_t CPSM;                /*!< Specifies whether SDMMC Command path state machine (CPSM)
+                                     is enabled or disabled.
+                                     This parameter can be a value of @ref SDMMC_LL_CPSM_State            */
+} SDMMC_CmdInitTypeDef;
+
+
+/**
+  * @brief  SDMMC Data Control structure
+  */
+typedef struct
+{
+  uint32_t DataTimeOut;         /*!< Specifies the data timeout period in card bus clock periods.  */
+
+  uint32_t DataLength;          /*!< Specifies the number of data bytes to be transferred.         */
+
+  uint32_t DataBlockSize;       /*!< Specifies the data block size for block transfer.
+                                     This parameter can be a value of @ref SDMMC_LL_Data_Block_Size    */
+
+  uint32_t TransferDir;         /*!< Specifies the data transfer direction, whether the transfer
+                                     is a read or write.
+                                     This parameter can be a value of @ref SDMMC_LL_Transfer_Direction */
+
+  uint32_t TransferMode;        /*!< Specifies whether data transfer is in stream or block mode.
+                                     This parameter can be a value of @ref SDMMC_LL_Transfer_Type      */
+
+  uint32_t DPSM;                /*!< Specifies whether SDMMC Data path state machine (DPSM)
+                                     is enabled or disabled.
+                                     This parameter can be a value of @ref SDMMC_LL_DPSM_State         */
+} SDMMC_DataInitTypeDef;
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup SDMMC_LL_Exported_Constants SDMMC_LL Exported Constants
+  * @{
+  */
+#define SDMMC_ERROR_NONE                     ((uint32_t)0x00000000U)   /*!< No error                                                      */
+#define SDMMC_ERROR_CMD_CRC_FAIL             ((uint32_t)0x00000001U)   /*!< Command response received (but CRC check failed)              */
+#define SDMMC_ERROR_DATA_CRC_FAIL            ((uint32_t)0x00000002U)   /*!< Data block sent/received (CRC check failed)                   */
+#define SDMMC_ERROR_CMD_RSP_TIMEOUT          ((uint32_t)0x00000004U)   /*!< Command response timeout                                      */
+#define SDMMC_ERROR_DATA_TIMEOUT             ((uint32_t)0x00000008U)   /*!< Data timeout                                                  */
+#define SDMMC_ERROR_TX_UNDERRUN              ((uint32_t)0x00000010U)   /*!< Transmit FIFO underrun                                        */
+#define SDMMC_ERROR_RX_OVERRUN               ((uint32_t)0x00000020U)   /*!< Receive FIFO overrun                                          */
+#define SDMMC_ERROR_ADDR_MISALIGNED          ((uint32_t)0x00000040U)   /*!< Misaligned address                                            */
+#define SDMMC_ERROR_BLOCK_LEN_ERR            ((uint32_t)0x00000080U)   /*!< Transferred block length is not allowed for the card or the number of transferred bytes does not match the block length   */
+#define SDMMC_ERROR_ERASE_SEQ_ERR            ((uint32_t)0x00000100U)   /*!< An error in the sequence of erase command occurs              */
+#define SDMMC_ERROR_BAD_ERASE_PARAM          ((uint32_t)0x00000200U)   /*!< An invalid selection for erase groups                         */
+#define SDMMC_ERROR_WRITE_PROT_VIOLATION     ((uint32_t)0x00000400U)   /*!< Attempt to program a write protect block                      */
+#define SDMMC_ERROR_LOCK_UNLOCK_FAILED       ((uint32_t)0x00000800U)   /*!< Sequence or password error has been detected in unlock command or if there was an attempt to access a locked card    */
+#define SDMMC_ERROR_COM_CRC_FAILED           ((uint32_t)0x00001000U)   /*!< CRC check of the previous command failed                      */
+#define SDMMC_ERROR_ILLEGAL_CMD              ((uint32_t)0x00002000U)   /*!< Command is not legal for the card state                       */
+#define SDMMC_ERROR_CARD_ECC_FAILED          ((uint32_t)0x00004000U)   /*!< Card internal ECC was applied but failed to correct the data  */
+#define SDMMC_ERROR_CC_ERR                   ((uint32_t)0x00008000U)   /*!< Internal card controller error                                */
+#define SDMMC_ERROR_GENERAL_UNKNOWN_ERR      ((uint32_t)0x00010000U)   /*!< General or unknown error                                      */
+#define SDMMC_ERROR_STREAM_READ_UNDERRUN     ((uint32_t)0x00020000U)   /*!< The card could not sustain data reading in stream rmode       */
+#define SDMMC_ERROR_STREAM_WRITE_OVERRUN     ((uint32_t)0x00040000U)   /*!< The card could not sustain data programming in stream mode    */
+#define SDMMC_ERROR_CID_CSD_OVERWRITE        ((uint32_t)0x00080000U)   /*!< CID/CSD overwrite error                                       */
+#define SDMMC_ERROR_WP_ERASE_SKIP            ((uint32_t)0x00100000U)   /*!< Only partial address space was erased                         */
+#define SDMMC_ERROR_CARD_ECC_DISABLED        ((uint32_t)0x00200000U)   /*!< Command has been executed without using internal ECC          */
+#define SDMMC_ERROR_ERASE_RESET              ((uint32_t)0x00400000U)   /*!< Erase sequence was cleared before executing because an out of erase sequence command was received                        */
+#define SDMMC_ERROR_AKE_SEQ_ERR              ((uint32_t)0x00800000U)   /*!< Error in sequence of authentication                           */
+#define SDMMC_ERROR_INVALID_VOLTRANGE        ((uint32_t)0x01000000U)   /*!< Error in case of invalid voltage range                        */
+#define SDMMC_ERROR_ADDR_OUT_OF_RANGE        ((uint32_t)0x02000000U)   /*!< Error when addressed block is out of range                    */
+#define SDMMC_ERROR_REQUEST_NOT_APPLICABLE   ((uint32_t)0x04000000U)   /*!< Error when command request is not applicable                  */
+#define SDMMC_ERROR_INVALID_PARAMETER        ((uint32_t)0x08000000U)   /*!< the used parameter is not valid                               */
+#define SDMMC_ERROR_UNSUPPORTED_FEATURE      ((uint32_t)0x10000000U)   /*!< Error when feature is not insupported                         */
+#define SDMMC_ERROR_BUSY                     ((uint32_t)0x20000000U)   /*!< Error when transfer process is busy                           */
+#define SDMMC_ERROR_DMA                      ((uint32_t)0x40000000U)   /*!< Error while DMA transfer                                      */
+#define SDMMC_ERROR_TIMEOUT                  ((uint32_t)0x80000000U)   /*!< Timeout error                                                 */
+
+/**
+  * @brief SDMMC Commands Index
+  */
+#define SDMMC_CMD_GO_IDLE_STATE                       ((uint8_t)0U)   /*!< Resets the SD memory card.                                                               */
+#define SDMMC_CMD_SEND_OP_COND                        ((uint8_t)1U)   /*!< Sends host capacity support information and activates the card's initialization process. */
+#define SDMMC_CMD_ALL_SEND_CID                        ((uint8_t)2U)   /*!< Asks any card connected to the host to send the CID numbers on the CMD line.             */
+#define SDMMC_CMD_SET_REL_ADDR                        ((uint8_t)3U)   /*!< Asks the card to publish a new relative address (RCA).                                   */
+#define SDMMC_CMD_SET_DSR                             ((uint8_t)4U)   /*!< Programs the DSR of all cards.                                                           */
+#define SDMMC_CMD_SDMMC_SEN_OP_COND                   ((uint8_t)5U)   /*!< Sends host capacity support information (HCS) and asks the accessed card to send its operating condition register (OCR) content in the response on the CMD line.*/
+#define SDMMC_CMD_HS_SWITCH                           ((uint8_t)6U)   /*!< Checks switchable function (mode 0) and switch card function (mode 1).                   */
+#define SDMMC_CMD_SEL_DESEL_CARD                      ((uint8_t)7U)   /*!< Selects the card by its own relative address and gets deselected by any other address    */
+#define SDMMC_CMD_HS_SEND_EXT_CSD                     ((uint8_t)8U)   /*!< Sends SD Memory Card interface condition, which includes host supply voltage information  and asks the card whether card supports voltage.                      */
+#define SDMMC_CMD_SEND_CSD                            ((uint8_t)9U)   /*!< Addressed card sends its card specific data (CSD) on the CMD line.                       */
+#define SDMMC_CMD_SEND_CID                            ((uint8_t)10U)  /*!< Addressed card sends its card identification (CID) on the CMD line.                      */
+#define SDMMC_CMD_VOLTAGE_SWITCH                      ((uint8_t)11U)  /*!< SD card Voltage switch to 1.8V mode.                                                     */
+#define SDMMC_CMD_STOP_TRANSMISSION                   ((uint8_t)12U)  /*!< Forces the card to stop transmission.                                                    */
+#define SDMMC_CMD_SEND_STATUS                         ((uint8_t)13U)  /*!< Addressed card sends its status register.                                                */
+#define SDMMC_CMD_HS_BUSTEST_READ                     ((uint8_t)14U)  /*!< Reserved                                                                                 */
+#define SDMMC_CMD_GO_INACTIVE_STATE                   ((uint8_t)15U)  /*!< Sends an addressed card into the inactive state.                                         */
+#define SDMMC_CMD_SET_BLOCKLEN                        ((uint8_t)16U)  /*!< Sets the block length (in bytes for SDSC) for all following block commands (read, write, lock). Default block length is fixed to 512 Bytes. Not effective        */
+/*!< for SDHS and SDXC.                                                                       */
+#define SDMMC_CMD_READ_SINGLE_BLOCK                   ((uint8_t)17U)  /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of fixed 512 bytes in case of SDHC and SDXC.                                    */
+#define SDMMC_CMD_READ_MULT_BLOCK                     ((uint8_t)18U)  /*!< Continuously transfers data blocks from card to host until interrupted by  STOP_TRANSMISSION command.                                                            */
+#define SDMMC_CMD_HS_BUSTEST_WRITE                    ((uint8_t)19U)  /*!< 64 bytes tuning pattern is sent for SDR50 and SDR104.                                    */
+#define SDMMC_CMD_WRITE_DAT_UNTIL_STOP                ((uint8_t)20U)  /*!< Speed class control command.                                                             */
+#define SDMMC_CMD_SET_BLOCK_COUNT                     ((uint8_t)23U)  /*!< Specify block count for CMD18 and CMD25.                                                 */
+#define SDMMC_CMD_WRITE_SINGLE_BLOCK                  ((uint8_t)24U)  /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of fixed 512 bytes in case of SDHC and SDXC.                                   */
+#define SDMMC_CMD_WRITE_MULT_BLOCK                    ((uint8_t)25U)  /*!< Continuously writes blocks of data until a STOP_TRANSMISSION follows.                    */
+#define SDMMC_CMD_PROG_CID                            ((uint8_t)26U)  /*!< Reserved for manufacturers.                                                              */
+#define SDMMC_CMD_PROG_CSD                            ((uint8_t)27U)  /*!< Programming of the programmable bits of the CSD.                                         */
+#define SDMMC_CMD_SET_WRITE_PROT                      ((uint8_t)28U)  /*!< Sets the write protection bit of the addressed group.                                    */
+#define SDMMC_CMD_CLR_WRITE_PROT                      ((uint8_t)29U)  /*!< Clears the write protection bit of the addressed group.                                  */
+#define SDMMC_CMD_SEND_WRITE_PROT                     ((uint8_t)30U)  /*!< Asks the card to send the status of the write protection bits.                           */
+#define SDMMC_CMD_SD_ERASE_GRP_START                  ((uint8_t)32U)  /*!< Sets the address of the first write block to be erased. (For SD card only).              */
+#define SDMMC_CMD_SD_ERASE_GRP_END                    ((uint8_t)33U)  /*!< Sets the address of the last write block of the continuous range to be erased.           */
+#define SDMMC_CMD_ERASE_GRP_START                     ((uint8_t)35U)  /*!< Sets the address of the first write block to be erased. Reserved for each command system set by switch function command (CMD6).                                  */
+#define SDMMC_CMD_ERASE_GRP_END                       ((uint8_t)36U)  /*!< Sets the address of the last write block of the continuous range to be erased. Reserved for each command system set by switch function command (CMD6).           */
+#define SDMMC_CMD_ERASE                               ((uint8_t)38U)  /*!< Reserved for SD security applications.                                                   */
+#define SDMMC_CMD_FAST_IO                             ((uint8_t)39U)  /*!< SD card doesn't support it (Reserved).                                                   */
+#define SDMMC_CMD_GO_IRQ_STATE                        ((uint8_t)40U)  /*!< SD card doesn't support it (Reserved).                                                   */
+#define SDMMC_CMD_LOCK_UNLOCK                         ((uint8_t)42U)  /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by the SET_BLOCK_LEN command.                                                */
+#define SDMMC_CMD_APP_CMD                             ((uint8_t)55U)  /*!< Indicates to the card that the next command is an application specific command rather than a standard command.                                                   */
+#define SDMMC_CMD_GEN_CMD                             ((uint8_t)56U)  /*!< Used either to transfer a data block to the card or to get a data block from the card for general purpose/application specific commands.                         */
+#define SDMMC_CMD_NO_CMD                              ((uint8_t)64U)  /*!< No command                                                                               */
+
+/**
+  * @brief Following commands are SD Card Specific commands.
+  *        SDMMC_APP_CMD should be sent before sending these commands.
+  */
+#define SDMMC_CMD_APP_SD_SET_BUSWIDTH                 ((uint8_t)6U)   /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus widths are given in SCR register.                                                   */
+#define SDMMC_CMD_SD_APP_STATUS                       ((uint8_t)13U)  /*!< (ACMD13) Sends the SD status.                                                            */
+#define SDMMC_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS        ((uint8_t)22U)  /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with 32bit+CRC data block.                                                               */
+#define SDMMC_CMD_SD_APP_OP_COND                      ((uint8_t)41U)  /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to send its operating condition register (OCR) content in the response on the CMD line. */
+#define SDMMC_CMD_SD_APP_SET_CLR_CARD_DETECT          ((uint8_t)42U)  /*!< (ACMD42) Connect/Disconnect the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card  */
+#define SDMMC_CMD_SD_APP_SEND_SCR                     ((uint8_t)51U)  /*!< Reads the SD Configuration Register (SCR).                                               */
+#define SDMMC_CMD_SDMMC_RW_DIRECT                     ((uint8_t)52U)  /*!< For SD I/O card only, reserved for security specification.                               */
+#define SDMMC_CMD_SDMMC_RW_EXTENDED                   ((uint8_t)53U)  /*!< For SD I/O card only, reserved for security specification.                               */
+
+/**
+  * @brief Following commands are MMC Specific commands.
+  */
+#define SDMMC_CMD_MMC_SLEEP_AWAKE                     ((uint8_t)5U)   /*!< Toggle the device between Sleep state and Standby state.                                 */
+
+/**
+  * @brief Following commands are SD Card Specific security commands.
+  *        SDMMC_CMD_APP_CMD should be sent before sending these commands.
+  */
+#define SDMMC_CMD_SD_APP_GET_MKB                      ((uint8_t)43U)
+#define SDMMC_CMD_SD_APP_GET_MID                      ((uint8_t)44U)
+#define SDMMC_CMD_SD_APP_SET_CER_RN1                  ((uint8_t)45U)
+#define SDMMC_CMD_SD_APP_GET_CER_RN2                  ((uint8_t)46U)
+#define SDMMC_CMD_SD_APP_SET_CER_RES2                 ((uint8_t)47U)
+#define SDMMC_CMD_SD_APP_GET_CER_RES1                 ((uint8_t)48U)
+#define SDMMC_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK   ((uint8_t)18U)
+#define SDMMC_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK  ((uint8_t)25U)
+#define SDMMC_CMD_SD_APP_SECURE_ERASE                 ((uint8_t)38U)
+#define SDMMC_CMD_SD_APP_CHANGE_SECURE_AREA           ((uint8_t)49U)
+#define SDMMC_CMD_SD_APP_SECURE_WRITE_MKB             ((uint8_t)48U)
+
+/**
+  * @brief  Masks for errors Card Status R1 (OCR Register)
+  */
+#define SDMMC_OCR_ADDR_OUT_OF_RANGE        ((uint32_t)0x80000000U)
+#define SDMMC_OCR_ADDR_MISALIGNED          ((uint32_t)0x40000000U)
+#define SDMMC_OCR_BLOCK_LEN_ERR            ((uint32_t)0x20000000U)
+#define SDMMC_OCR_ERASE_SEQ_ERR            ((uint32_t)0x10000000U)
+#define SDMMC_OCR_BAD_ERASE_PARAM          ((uint32_t)0x08000000U)
+#define SDMMC_OCR_WRITE_PROT_VIOLATION     ((uint32_t)0x04000000U)
+#define SDMMC_OCR_LOCK_UNLOCK_FAILED       ((uint32_t)0x01000000U)
+#define SDMMC_OCR_COM_CRC_FAILED           ((uint32_t)0x00800000U)
+#define SDMMC_OCR_ILLEGAL_CMD              ((uint32_t)0x00400000U)
+#define SDMMC_OCR_CARD_ECC_FAILED          ((uint32_t)0x00200000U)
+#define SDMMC_OCR_CC_ERROR                 ((uint32_t)0x00100000U)
+#define SDMMC_OCR_GENERAL_UNKNOWN_ERROR    ((uint32_t)0x00080000U)
+#define SDMMC_OCR_STREAM_READ_UNDERRUN     ((uint32_t)0x00040000U)
+#define SDMMC_OCR_STREAM_WRITE_OVERRUN     ((uint32_t)0x00020000U)
+#define SDMMC_OCR_CID_CSD_OVERWRITE        ((uint32_t)0x00010000U)
+#define SDMMC_OCR_WP_ERASE_SKIP            ((uint32_t)0x00008000U)
+#define SDMMC_OCR_CARD_ECC_DISABLED        ((uint32_t)0x00004000U)
+#define SDMMC_OCR_ERASE_RESET              ((uint32_t)0x00002000U)
+#define SDMMC_OCR_AKE_SEQ_ERROR            ((uint32_t)0x00000008U)
+#define SDMMC_OCR_ERRORBITS                ((uint32_t)0xFDFFE008U)
+
+/**
+  * @brief  Masks for R6 Response
+  */
+#define SDMMC_R6_GENERAL_UNKNOWN_ERROR     ((uint32_t)0x00002000U)
+#define SDMMC_R6_ILLEGAL_CMD               ((uint32_t)0x00004000U)
+#define SDMMC_R6_COM_CRC_FAILED            ((uint32_t)0x00008000U)
+
+#define SDMMC_VOLTAGE_WINDOW_SD            ((uint32_t)0x80100000U)
+#define SDMMC_HIGH_CAPACITY                ((uint32_t)0x40000000U)
+#define SDMMC_STD_CAPACITY                 ((uint32_t)0x00000000U)
+#define SDMMC_CHECK_PATTERN                ((uint32_t)0x000001AAU)
+#define SD_SWITCH_1_8V_CAPACITY            ((uint32_t)0x01000000U)
+#define SDMMC_DDR50_SWITCH_PATTERN         ((uint32_t)0x80FFFF04U)
+#define SDMMC_SDR104_SWITCH_PATTERN        ((uint32_t)0x80FF1F03U)
+#define SDMMC_SDR50_SWITCH_PATTERN         ((uint32_t)0x80FF1F02U)
+#define SDMMC_SDR25_SWITCH_PATTERN         ((uint32_t)0x80FFFF01U)
+#define SDMMC_SDR12_SWITCH_PATTERN         ((uint32_t)0x80FFFF00U)
+
+#define SDMMC_MAX_VOLT_TRIAL               ((uint32_t)0x0000FFFFU)
+
+#define SDMMC_MAX_TRIAL                    ((uint32_t)0x0000FFFFU)
+
+#define SDMMC_ALLZERO                      ((uint32_t)0x00000000U)
+
+#define SDMMC_WIDE_BUS_SUPPORT             ((uint32_t)0x00040000U)
+#define SDMMC_SINGLE_BUS_SUPPORT           ((uint32_t)0x00010000U)
+#define SDMMC_CARD_LOCKED                  ((uint32_t)0x02000000U)
+
+#ifndef SDMMC_DATATIMEOUT
+#define SDMMC_DATATIMEOUT                  ((uint32_t)0xFFFFFFFFU)
+#endif /* SDMMC_DATATIMEOUT */
+#define SDMMC_0TO7BITS                     ((uint32_t)0x000000FFU)
+#define SDMMC_8TO15BITS                    ((uint32_t)0x0000FF00U)
+#define SDMMC_16TO23BITS                   ((uint32_t)0x00FF0000U)
+#define SDMMC_24TO31BITS                   ((uint32_t)0xFF000000U)
+#define SDMMC_MAX_DATA_LENGTH              ((uint32_t)0x01FFFFFFU)
+
+#define SDMMC_HALFFIFO                     ((uint32_t)0x00000008U)
+#define SDMMC_HALFFIFOBYTES                ((uint32_t)0x00000020U)
+
+/**
+  * @brief  Command Class supported
+  */
+#define SDMMC_CCCC_ERASE                   ((uint32_t)0x00000020U)
+
+#define SDMMC_CMDTIMEOUT                   ((uint32_t)5000U)        /* Command send and response timeout     */
+#define SDMMC_MAXERASETIMEOUT              ((uint32_t)63000U)       /* Max erase Timeout 63 s                */
+#define SDMMC_STOPTRANSFERTIMEOUT          ((uint32_t)100000000U)   /* Timeout for STOP TRANSMISSION command */
+
+/** @defgroup SDMMC_LL_Clock_Edge Clock Edge
+  * @{
+  */
+#define SDMMC_CLOCK_EDGE_RISING               ((uint32_t)0x00000000U)
+#define SDMMC_CLOCK_EDGE_FALLING              SDMMC_CLKCR_NEGEDGE
+
+#define IS_SDMMC_CLOCK_EDGE(EDGE) (((EDGE) == SDMMC_CLOCK_EDGE_RISING) || \
+                                   ((EDGE) == SDMMC_CLOCK_EDGE_FALLING))
+/**
+  * @}
+  */
+
+/** @defgroup SDMMC_LL_Clock_Power_Save Clock Power Saving
+  * @{
+  */
+#define SDMMC_CLOCK_POWER_SAVE_DISABLE         ((uint32_t)0x00000000U)
+#define SDMMC_CLOCK_POWER_SAVE_ENABLE          SDMMC_CLKCR_PWRSAV
+
+#define IS_SDMMC_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDMMC_CLOCK_POWER_SAVE_DISABLE) || \
+                                         ((SAVE) == SDMMC_CLOCK_POWER_SAVE_ENABLE))
+/**
+  * @}
+  */
+
+/** @defgroup SDMMC_LL_Bus_Wide Bus Width
+  * @{
+  */
+#define SDMMC_BUS_WIDE_1B                      ((uint32_t)0x00000000U)
+#define SDMMC_BUS_WIDE_4B                      SDMMC_CLKCR_WIDBUS_0
+#define SDMMC_BUS_WIDE_8B                      SDMMC_CLKCR_WIDBUS_1
+
+#define IS_SDMMC_BUS_WIDE(WIDE) (((WIDE) == SDMMC_BUS_WIDE_1B) || \
+                                 ((WIDE) == SDMMC_BUS_WIDE_4B) || \
+                                 ((WIDE) == SDMMC_BUS_WIDE_8B))
+/**
+  * @}
+  */
+
+/** @defgroup SDMMC_LL_Speed_Mode
+  * @{
+  */
+#define SDMMC_SPEED_MODE_AUTO                  ((uint32_t)0x00000000U)
+#define SDMMC_SPEED_MODE_DEFAULT               ((uint32_t)0x00000001U)
+#define SDMMC_SPEED_MODE_HIGH                  ((uint32_t)0x00000002U)
+#define SDMMC_SPEED_MODE_ULTRA                 ((uint32_t)0x00000003U)
+#define SDMMC_SPEED_MODE_ULTRA_SDR104          SDMMC_SPEED_MODE_ULTRA
+#define SDMMC_SPEED_MODE_DDR                   ((uint32_t)0x00000004U)
+#define SDMMC_SPEED_MODE_ULTRA_SDR50           ((uint32_t)0x00000005U)
+
+#define IS_SDMMC_SPEED_MODE(MODE) (((MODE) == SDMMC_SPEED_MODE_AUTO)         || \
+                                   ((MODE) == SDMMC_SPEED_MODE_DEFAULT)      || \
+                                   ((MODE) == SDMMC_SPEED_MODE_HIGH)         || \
+                                   ((MODE) == SDMMC_SPEED_MODE_ULTRA)        || \
+                                   ((MODE) == SDMMC_SPEED_MODE_ULTRA_SDR50)  || \
+                                   ((MODE) == SDMMC_SPEED_MODE_DDR))
+
+/**
+  * @}
+  */
+
+/** @defgroup SDMMC_LL_Hardware_Flow_Control Hardware Flow Control
+  * @{
+  */
+#define SDMMC_HARDWARE_FLOW_CONTROL_DISABLE    ((uint32_t)0x00000000U)
+#define SDMMC_HARDWARE_FLOW_CONTROL_ENABLE     SDMMC_CLKCR_HWFC_EN
+
+#define IS_SDMMC_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDMMC_HARDWARE_FLOW_CONTROL_DISABLE) || \
+                                                 ((CONTROL) == SDMMC_HARDWARE_FLOW_CONTROL_ENABLE))
+/**
+  * @}
+  */
+
+/** @defgroup SDMMC_LL_Clock_Division Clock Division
+  * @{
+  */
+/* SDMMC_CK frequency = SDMMCCLK / [2 * CLKDIV] */
+#define IS_SDMMC_CLKDIV(DIV)   ((DIV) < 0x400U)
+/**
+  * @}
+  */
+
+/** @defgroup SDMMC_LL_TRANSCEIVER_PRESENT Transceiver Present
+  * @{
+  */
+#define SDMMC_TRANSCEIVER_UNKNOWN             ((uint32_t)0x00000000U)
+#define SDMMC_TRANSCEIVER_NOT_PRESENT         ((uint32_t)0x00000001U)
+#define SDMMC_TRANSCEIVER_PRESENT             ((uint32_t)0x00000002U)
+
+/**
+  * @}
+  */
+
+/** @defgroup SDMMC_LL_Command_Index Command Index
+  * @{
+  */
+#define IS_SDMMC_CMD_INDEX(INDEX)            ((INDEX) < 0x40U)
+/**
+  * @}
+  */
+
+/** @defgroup SDMMC_LL_Response_Type Response Type
+  * @{
+  */
+#define SDMMC_RESPONSE_NO                    ((uint32_t)0x00000000U)
+#define SDMMC_RESPONSE_SHORT                 SDMMC_CMD_WAITRESP_0
+#define SDMMC_RESPONSE_LONG                  SDMMC_CMD_WAITRESP
+
+#define IS_SDMMC_RESPONSE(RESPONSE) (((RESPONSE) == SDMMC_RESPONSE_NO)    || \
+                                     ((RESPONSE) == SDMMC_RESPONSE_SHORT) || \
+                                     ((RESPONSE) == SDMMC_RESPONSE_LONG))
+/**
+  * @}
+  */
+
+/** @defgroup SDMMC_LL_Wait_Interrupt_State Wait Interrupt
+  * @{
+  */
+#define SDMMC_WAIT_NO                        ((uint32_t)0x00000000U)
+#define SDMMC_WAIT_IT                        SDMMC_CMD_WAITINT
+#define SDMMC_WAIT_PEND                      SDMMC_CMD_WAITPEND
+
+#define IS_SDMMC_WAIT(WAIT) (((WAIT) == SDMMC_WAIT_NO) || \
+                             ((WAIT) == SDMMC_WAIT_IT) || \
+                             ((WAIT) == SDMMC_WAIT_PEND))
+/**
+  * @}
+  */
+
+/** @defgroup SDMMC_LL_CPSM_State CPSM State
+  * @{
+  */
+#define SDMMC_CPSM_DISABLE                   ((uint32_t)0x00000000U)
+#define SDMMC_CPSM_ENABLE                    SDMMC_CMD_CPSMEN
+
+#define IS_SDMMC_CPSM(CPSM) (((CPSM) == SDMMC_CPSM_DISABLE) || \
+                             ((CPSM) == SDMMC_CPSM_ENABLE))
+/**
+  * @}
+  */
+
+/** @defgroup SDMMC_LL_Response_Registers Response Register
+  * @{
+  */
+#define SDMMC_RESP1                          ((uint32_t)0x00000000U)
+#define SDMMC_RESP2                          ((uint32_t)0x00000004U)
+#define SDMMC_RESP3                          ((uint32_t)0x00000008U)
+#define SDMMC_RESP4                          ((uint32_t)0x0000000CU)
+
+#define IS_SDMMC_RESP(RESP) (((RESP) == SDMMC_RESP1) || \
+                             ((RESP) == SDMMC_RESP2) || \
+                             ((RESP) == SDMMC_RESP3) || \
+                             ((RESP) == SDMMC_RESP4))
+
+/** @defgroup SDMMC_Internal_DMA_Mode  SDMMC Internal DMA Mode
+  * @{
+  */
+#define SDMMC_DISABLE_IDMA              ((uint32_t)0x00000000)
+#define SDMMC_ENABLE_IDMA_SINGLE_BUFF   (SDMMC_IDMA_IDMAEN)
+#define SDMMC_ENABLE_IDMA_DOUBLE_BUFF0  (SDMMC_IDMA_IDMAEN | SDMMC_IDMA_IDMABMODE)
+#define SDMMC_ENABLE_IDMA_DOUBLE_BUFF1  (SDMMC_IDMA_IDMAEN | SDMMC_IDMA_IDMABMODE | SDMMC_IDMA_IDMABACT)
+
+/**
+  * @}
+  */
+
+/** @defgroup SDMMC_LL_Data_Length Data Length
+  * @{
+  */
+#define IS_SDMMC_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFFU)
+/**
+  * @}
+  */
+
+/** @defgroup SDMMC_LL_Data_Block_Size  Data Block Size
+  * @{
+  */
+#define SDMMC_DATABLOCK_SIZE_1B               ((uint32_t)0x00000000U)
+#define SDMMC_DATABLOCK_SIZE_2B               SDMMC_DCTRL_DBLOCKSIZE_0
+#define SDMMC_DATABLOCK_SIZE_4B               SDMMC_DCTRL_DBLOCKSIZE_1
+#define SDMMC_DATABLOCK_SIZE_8B               (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_1)
+#define SDMMC_DATABLOCK_SIZE_16B              SDMMC_DCTRL_DBLOCKSIZE_2
+#define SDMMC_DATABLOCK_SIZE_32B              (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_2)
+#define SDMMC_DATABLOCK_SIZE_64B              (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2)
+#define SDMMC_DATABLOCK_SIZE_128B             (SDMMC_DCTRL_DBLOCKSIZE_0| \
+                                               SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2)
+#define SDMMC_DATABLOCK_SIZE_256B             SDMMC_DCTRL_DBLOCKSIZE_3
+#define SDMMC_DATABLOCK_SIZE_512B             (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_3)
+#define SDMMC_DATABLOCK_SIZE_1024B            (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_3)
+#define SDMMC_DATABLOCK_SIZE_2048B            (SDMMC_DCTRL_DBLOCKSIZE_0| \
+                                               SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_3)
+#define SDMMC_DATABLOCK_SIZE_4096B            (SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3)
+#define SDMMC_DATABLOCK_SIZE_8192B            (SDMMC_DCTRL_DBLOCKSIZE_0| \
+                                               SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3)
+#define SDMMC_DATABLOCK_SIZE_16384B           (SDMMC_DCTRL_DBLOCKSIZE_1| \
+                                               SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3)
+
+#define IS_SDMMC_BLOCK_SIZE(SIZE) (((SIZE) == SDMMC_DATABLOCK_SIZE_1B)    || \
+                                   ((SIZE) == SDMMC_DATABLOCK_SIZE_2B)    || \
+                                   ((SIZE) == SDMMC_DATABLOCK_SIZE_4B)    || \
+                                   ((SIZE) == SDMMC_DATABLOCK_SIZE_8B)    || \
+                                   ((SIZE) == SDMMC_DATABLOCK_SIZE_16B)   || \
+                                   ((SIZE) == SDMMC_DATABLOCK_SIZE_32B)   || \
+                                   ((SIZE) == SDMMC_DATABLOCK_SIZE_64B)   || \
+                                   ((SIZE) == SDMMC_DATABLOCK_SIZE_128B)  || \
+                                   ((SIZE) == SDMMC_DATABLOCK_SIZE_256B)  || \
+                                   ((SIZE) == SDMMC_DATABLOCK_SIZE_512B)  || \
+                                   ((SIZE) == SDMMC_DATABLOCK_SIZE_1024B) || \
+                                   ((SIZE) == SDMMC_DATABLOCK_SIZE_2048B) || \
+                                   ((SIZE) == SDMMC_DATABLOCK_SIZE_4096B) || \
+                                   ((SIZE) == SDMMC_DATABLOCK_SIZE_8192B) || \
+                                   ((SIZE) == SDMMC_DATABLOCK_SIZE_16384B))
+/**
+  * @}
+  */
+
+/** @defgroup SDMMC_LL_Transfer_Direction Transfer Direction
+  * @{
+  */
+#define SDMMC_TRANSFER_DIR_TO_CARD            ((uint32_t)0x00000000U)
+#define SDMMC_TRANSFER_DIR_TO_SDMMC            SDMMC_DCTRL_DTDIR
+
+#define IS_SDMMC_TRANSFER_DIR(DIR) (((DIR) == SDMMC_TRANSFER_DIR_TO_CARD) || \
+                                    ((DIR) == SDMMC_TRANSFER_DIR_TO_SDMMC))
+/**
+  * @}
+  */
+
+/** @defgroup SDMMC_LL_Transfer_Type Transfer Type
+  * @{
+  */
+#define SDMMC_TRANSFER_MODE_BLOCK             ((uint32_t)0x00000000U)
+#define SDMMC_TRANSFER_MODE_STREAM            SDMMC_DCTRL_DTMODE_1
+
+#define IS_SDMMC_TRANSFER_MODE(MODE) (((MODE) == SDMMC_TRANSFER_MODE_BLOCK) || \
+                                      ((MODE) == SDMMC_TRANSFER_MODE_STREAM))
+/**
+  * @}
+  */
+
+/** @defgroup SDMMC_LL_DPSM_State DPSM State
+  * @{
+  */
+#define SDMMC_DPSM_DISABLE                    ((uint32_t)0x00000000U)
+#define SDMMC_DPSM_ENABLE                     SDMMC_DCTRL_DTEN
+
+#define IS_SDMMC_DPSM(DPSM) (((DPSM) == SDMMC_DPSM_DISABLE) ||\
+                             ((DPSM) == SDMMC_DPSM_ENABLE))
+/**
+  * @}
+  */
+
+/** @defgroup SDMMC_LL_Read_Wait_Mode Read Wait Mode
+  * @{
+  */
+#define SDMMC_READ_WAIT_MODE_DATA2                ((uint32_t)0x00000000U)
+#define SDMMC_READ_WAIT_MODE_CLK                  (SDMMC_DCTRL_RWMOD)
+
+#define IS_SDMMC_READWAIT_MODE(MODE) (((MODE) == SDMMC_READ_WAIT_MODE_CLK) || \
+                                      ((MODE) == SDMMC_READ_WAIT_MODE_DATA2))
+/**
+  * @}
+  */
+
+/** @defgroup SDMMC_LL_Interrupt_sources Interrupt Sources
+  * @{
+  */
+#define SDMMC_IT_CCRCFAIL                  SDMMC_MASK_CCRCFAILIE
+#define SDMMC_IT_DCRCFAIL                  SDMMC_MASK_DCRCFAILIE
+#define SDMMC_IT_CTIMEOUT                  SDMMC_MASK_CTIMEOUTIE
+#define SDMMC_IT_DTIMEOUT                  SDMMC_MASK_DTIMEOUTIE
+#define SDMMC_IT_TXUNDERR                  SDMMC_MASK_TXUNDERRIE
+#define SDMMC_IT_RXOVERR                   SDMMC_MASK_RXOVERRIE
+#define SDMMC_IT_CMDREND                   SDMMC_MASK_CMDRENDIE
+#define SDMMC_IT_CMDSENT                   SDMMC_MASK_CMDSENTIE
+#define SDMMC_IT_DATAEND                   SDMMC_MASK_DATAENDIE
+#define SDMMC_IT_DHOLD                     SDMMC_MASK_DHOLDIE
+#define SDMMC_IT_DBCKEND                   SDMMC_MASK_DBCKENDIE
+#define SDMMC_IT_DABORT                    SDMMC_MASK_DABORTIE
+#define SDMMC_IT_TXFIFOHE                  SDMMC_MASK_TXFIFOHEIE
+#define SDMMC_IT_RXFIFOHF                  SDMMC_MASK_RXFIFOHFIE
+#define SDMMC_IT_RXFIFOF                   SDMMC_MASK_RXFIFOFIE
+#define SDMMC_IT_TXFIFOE                   SDMMC_MASK_TXFIFOEIE
+#define SDMMC_IT_BUSYD0END                 SDMMC_MASK_BUSYD0ENDIE
+#define SDMMC_IT_SDIOIT                    SDMMC_MASK_SDIOITIE
+#define SDMMC_IT_ACKFAIL                   SDMMC_MASK_ACKFAILIE
+#define SDMMC_IT_ACKTIMEOUT                SDMMC_MASK_ACKTIMEOUTIE
+#define SDMMC_IT_VSWEND                    SDMMC_MASK_VSWENDIE
+#define SDMMC_IT_CKSTOP                    SDMMC_MASK_CKSTOPIE
+#define SDMMC_IT_IDMABTC                   SDMMC_MASK_IDMABTCIE
+/**
+  * @}
+  */
+
+/** @defgroup SDMMC_LL_Flags Flags
+  * @{
+  */
+#define SDMMC_FLAG_CCRCFAIL                  SDMMC_STA_CCRCFAIL
+#define SDMMC_FLAG_DCRCFAIL                  SDMMC_STA_DCRCFAIL
+#define SDMMC_FLAG_CTIMEOUT                  SDMMC_STA_CTIMEOUT
+#define SDMMC_FLAG_DTIMEOUT                  SDMMC_STA_DTIMEOUT
+#define SDMMC_FLAG_TXUNDERR                  SDMMC_STA_TXUNDERR
+#define SDMMC_FLAG_RXOVERR                   SDMMC_STA_RXOVERR
+#define SDMMC_FLAG_CMDREND                   SDMMC_STA_CMDREND
+#define SDMMC_FLAG_CMDSENT                   SDMMC_STA_CMDSENT
+#define SDMMC_FLAG_DATAEND                   SDMMC_STA_DATAEND
+#define SDMMC_FLAG_DHOLD                     SDMMC_STA_DHOLD
+#define SDMMC_FLAG_DBCKEND                   SDMMC_STA_DBCKEND
+#define SDMMC_FLAG_DABORT                    SDMMC_STA_DABORT
+#define SDMMC_FLAG_DPSMACT                   SDMMC_STA_DPSMACT
+#define SDMMC_FLAG_CMDACT                    SDMMC_STA_CPSMACT
+#define SDMMC_FLAG_TXFIFOHE                  SDMMC_STA_TXFIFOHE
+#define SDMMC_FLAG_RXFIFOHF                  SDMMC_STA_RXFIFOHF
+#define SDMMC_FLAG_TXFIFOF                   SDMMC_STA_TXFIFOF
+#define SDMMC_FLAG_RXFIFOF                   SDMMC_STA_RXFIFOF
+#define SDMMC_FLAG_TXFIFOE                   SDMMC_STA_TXFIFOE
+#define SDMMC_FLAG_RXFIFOE                   SDMMC_STA_RXFIFOE
+#define SDMMC_FLAG_BUSYD0                    SDMMC_STA_BUSYD0
+#define SDMMC_FLAG_BUSYD0END                 SDMMC_STA_BUSYD0END
+#define SDMMC_FLAG_SDIOIT                    SDMMC_STA_SDIOIT
+#define SDMMC_FLAG_ACKFAIL                   SDMMC_STA_ACKFAIL
+#define SDMMC_FLAG_ACKTIMEOUT                SDMMC_STA_ACKTIMEOUT
+#define SDMMC_FLAG_VSWEND                    SDMMC_STA_VSWEND
+#define SDMMC_FLAG_CKSTOP                    SDMMC_STA_CKSTOP
+#define SDMMC_FLAG_IDMATE                    SDMMC_STA_IDMATE
+#define SDMMC_FLAG_IDMABTC                   SDMMC_STA_IDMABTC
+
+#define SDMMC_STATIC_FLAGS             ((uint32_t)(SDMMC_FLAG_CCRCFAIL   | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_CTIMEOUT |\
+                                                   SDMMC_FLAG_DTIMEOUT   | SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_RXOVERR  |\
+                                                   SDMMC_FLAG_CMDREND    | SDMMC_FLAG_CMDSENT  | SDMMC_FLAG_DATAEND  |\
+                                                   SDMMC_FLAG_DHOLD      | SDMMC_FLAG_DBCKEND  | SDMMC_FLAG_DABORT   |\
+                                                   SDMMC_FLAG_BUSYD0END  | SDMMC_FLAG_SDIOIT   | SDMMC_FLAG_ACKFAIL  |\
+                                                   SDMMC_FLAG_ACKTIMEOUT | SDMMC_FLAG_VSWEND   | SDMMC_FLAG_CKSTOP   |\
+                                                   SDMMC_FLAG_IDMATE     | SDMMC_FLAG_IDMABTC))
+
+#define SDMMC_STATIC_CMD_FLAGS         ((uint32_t)(SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CTIMEOUT  | SDMMC_FLAG_CMDREND   |\
+                                                   SDMMC_FLAG_CMDSENT  | SDMMC_FLAG_BUSYD0END))
+
+#define SDMMC_STATIC_DATA_FLAGS        ((uint32_t)(SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_TXUNDERR   |\
+                                                   SDMMC_FLAG_RXOVERR  | SDMMC_FLAG_DATAEND  | SDMMC_FLAG_DHOLD      |\
+                                                   SDMMC_FLAG_DBCKEND  | SDMMC_FLAG_DABORT   | SDMMC_FLAG_IDMATE     |\
+                                                   SDMMC_FLAG_IDMABTC))
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup SDMMC_LL_Exported_macros SDMMC_LL Exported Macros
+  * @{
+  */
+
+/** @defgroup SDMMC_LL_Register Bits And Addresses Definitions
+  * @brief SDMMC_LL registers bit address in the alias region
+  * @{
+  */
+/* ---------------------- SDMMC registers bit mask --------------------------- */
+/* --- CLKCR Register ---*/
+/* CLKCR register clear mask */
+#define CLKCR_CLEAR_MASK         ((uint32_t)(SDMMC_CLKCR_CLKDIV  | SDMMC_CLKCR_PWRSAV |\
+                                             SDMMC_CLKCR_WIDBUS |\
+                                             SDMMC_CLKCR_NEGEDGE | SDMMC_CLKCR_HWFC_EN |\
+                                             SDMMC_CLKCR_DDR | SDMMC_CLKCR_BUSSPEED |\
+                                             SDMMC_CLKCR_SELCLKRX))
+
+/* --- DCTRL Register ---*/
+/* SDMMC DCTRL Clear Mask */
+#define DCTRL_CLEAR_MASK         ((uint32_t)(SDMMC_DCTRL_DTEN    | SDMMC_DCTRL_DTDIR |\
+                                             SDMMC_DCTRL_DTMODE  | SDMMC_DCTRL_DBLOCKSIZE))
+
+/* --- CMD Register ---*/
+/* CMD Register clear mask */
+#define CMD_CLEAR_MASK           ((uint32_t)(SDMMC_CMD_CMDINDEX | SDMMC_CMD_WAITRESP |\
+                                             SDMMC_CMD_WAITINT  | SDMMC_CMD_WAITPEND |\
+                                             SDMMC_CMD_CPSMEN   | SDMMC_CMD_CMDSUSPEND))
+
+/* SDMMC Initialization Frequency (400KHz max) for Peripheral CLK 200MHz*/
+#define SDMMC_INIT_CLK_DIV ((uint8_t)0xFA)
+
+/* SDMMC Default Speed Frequency (25Mhz max) for Peripheral CLK 200MHz*/
+#define SDMMC_NSPEED_CLK_DIV ((uint8_t)0x4)
+
+/* SDMMC High Speed Frequency (50Mhz max) for Peripheral CLK 200MHz*/
+#define SDMMC_HSPEED_CLK_DIV ((uint8_t)0x2)
+/**
+  * @}
+  */
+
+/** @defgroup SDMMC_LL_Interrupt_Clock Interrupt And Clock Configuration
+  *  @brief macros to handle interrupts and specific clock configurations
+  * @{
+  */
+
+/**
+  * @brief  Enable the SDMMC device interrupt.
+  * @param  __INSTANCE__ Pointer to SDMMC register base
+  * @param  __INTERRUPT__ specifies the SDMMC interrupt sources to be enabled.
+  *         This parameter can be one or a combination of the following values:
+  *            @arg SDMMC_IT_CCRCFAIL:   Command response received (CRC check failed) interrupt
+  *            @arg SDMMC_IT_DCRCFAIL:   Data block sent/received (CRC check failed) interrupt
+  *            @arg SDMMC_IT_CTIMEOUT:   Command response timeout interrupt
+  *            @arg SDMMC_IT_DTIMEOUT:   Data timeout interrupt
+  *            @arg SDMMC_IT_TXUNDERR:   Transmit FIFO underrun error interrupt
+  *            @arg SDMMC_IT_RXOVERR:    Received FIFO overrun error interrupt
+  *            @arg SDMMC_IT_CMDREND:    Command response received (CRC check passed) interrupt
+  *            @arg SDMMC_IT_CMDSENT:    Command sent (no response required) interrupt
+  *            @arg SDMMC_IT_DATAEND:    Data end (data counter, DATACOUNT, is zero) interrupt
+  *            @arg SDMMC_IT_DHOLD:      Data transfer Hold interrupt
+  *            @arg SDMMC_IT_DBCKEND:    Data block sent/received (CRC check passed) interrupt
+  *            @arg SDMMC_IT_DABORT:     Data transfer aborted by CMD12 interrupt
+  *            @arg SDMMC_IT_TXFIFOHE:   Transmit FIFO Half Empty interrupt
+  *            @arg SDMMC_IT_RXFIFOHF:   Receive FIFO Half Full interrupt
+  *            @arg SDMMC_IT_RXFIFOF:    Receive FIFO full interrupt
+  *            @arg SDMMC_IT_TXFIFOE:    Transmit FIFO empty interrupt
+  *            @arg SDMMC_IT_BUSYD0END:  End of SDMMC_D0 Busy following a CMD response detected interrupt
+  *            @arg SDMMC_IT_SDIOIT:     SDIO interrupt received interrupt
+  *            @arg SDMMC_IT_ACKFAIL:    Boot Acknowledgment received interrupt
+  *            @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt
+  *            @arg SDMMC_IT_VSWEND:     Voltage switch critical timing section completion interrupt
+  *            @arg SDMMC_IT_CKSTOP:     SDMMC_CK stopped in Voltage switch procedure interrupt
+  *            @arg SDMMC_IT_IDMABTC:    IDMA buffer transfer complete interrupt
+  * @retval None
+  */
+#define __SDMMC_ENABLE_IT(__INSTANCE__, __INTERRUPT__)  ((__INSTANCE__)->MASK |= (__INTERRUPT__))
+
+/**
+  * @brief  Disable the SDMMC device interrupt.
+  * @param  __INSTANCE__ Pointer to SDMMC register base
+  * @param  __INTERRUPT__ specifies the SDMMC interrupt sources to be disabled.
+  *          This parameter can be one or a combination of the following values:
+  *            @arg SDMMC_IT_CCRCFAIL:   Command response received (CRC check failed) interrupt
+  *            @arg SDMMC_IT_DCRCFAIL:   Data block sent/received (CRC check failed) interrupt
+  *            @arg SDMMC_IT_CTIMEOUT:   Command response timeout interrupt
+  *            @arg SDMMC_IT_DTIMEOUT:   Data timeout interrupt
+  *            @arg SDMMC_IT_TXUNDERR:   Transmit FIFO underrun error interrupt
+  *            @arg SDMMC_IT_RXOVERR:    Received FIFO overrun error interrupt
+  *            @arg SDMMC_IT_CMDREND:    Command response received (CRC check passed) interrupt
+  *            @arg SDMMC_IT_CMDSENT:    Command sent (no response required) interrupt
+  *            @arg SDMMC_IT_DATAEND:    Data end (data counter, DATACOUNT, is zero) interrupt
+  *            @arg SDMMC_IT_DHOLD:      Data transfer Hold interrupt
+  *            @arg SDMMC_IT_DBCKEND:    Data block sent/received (CRC check passed) interrupt
+  *            @arg SDMMC_IT_DABORT:     Data transfer aborted by CMD12 interrupt
+  *            @arg SDMMC_IT_TXFIFOHE:   Transmit FIFO Half Empty interrupt
+  *            @arg SDMMC_IT_RXFIFOHF:   Receive FIFO Half Full interrupt
+  *            @arg SDMMC_IT_RXFIFOF:    Receive FIFO full interrupt
+  *            @arg SDMMC_IT_TXFIFOE:    Transmit FIFO empty interrupt
+  *            @arg SDMMC_IT_BUSYD0END:  End of SDMMC_D0 Busy following a CMD response detected interrupt
+  *            @arg SDMMC_IT_SDIOIT:     SDIO interrupt received interrupt
+  *            @arg SDMMC_IT_ACKFAIL:    Boot Acknowledgment received interrupt
+  *            @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt
+  *            @arg SDMMC_IT_VSWEND:     Voltage switch critical timing section completion interrupt
+  *            @arg SDMMC_IT_CKSTOP:     SDMMC_CK stopped in Voltage switch procedure interrupt
+  *            @arg SDMMC_IT_IDMABTC:    IDMA buffer transfer complete interrupt
+  * @retval None
+  */
+#define __SDMMC_DISABLE_IT(__INSTANCE__, __INTERRUPT__)  ((__INSTANCE__)->MASK &= ~(__INTERRUPT__))
+
+/**
+  * @brief  Checks whether the specified SDMMC flag is set or not.
+  * @param  __INSTANCE__ Pointer to SDMMC register base
+  * @param  __FLAG__ specifies the flag to check.
+  *          This parameter can be one of the following values:
+  *            @arg SDMMC_FLAG_CCRCFAIL:   Command response received (CRC check failed)
+  *            @arg SDMMC_FLAG_DCRCFAIL:   Data block sent/received (CRC check failed)
+  *            @arg SDMMC_FLAG_CTIMEOUT:   Command response timeout
+  *            @arg SDMMC_FLAG_DTIMEOUT:   Data timeout
+  *            @arg SDMMC_FLAG_TXUNDERR:   Transmit FIFO underrun error
+  *            @arg SDMMC_FLAG_RXOVERR:    Received FIFO overrun error
+  *            @arg SDMMC_FLAG_CMDREND:    Command response received (CRC check passed)
+  *            @arg SDMMC_FLAG_CMDSENT:    Command sent (no response required)
+  *            @arg SDMMC_FLAG_DATAEND:    Data end (data counter, DATACOUNT, is zero)
+  *            @arg SDMMC_FLAG_DHOLD:      Data transfer Hold
+  *            @arg SDMMC_FLAG_DBCKEND:    Data block sent/received (CRC check passed)
+  *            @arg SDMMC_FLAG_DABORT:     Data transfer aborted by CMD12
+  *            @arg SDMMC_FLAG_DPSMACT:    Data path state machine active
+  *            @arg SDMMC_FLAG_CPSMACT:    Command path state machine active
+  *            @arg SDMMC_FLAG_TXFIFOHE:   Transmit FIFO Half Empty
+  *            @arg SDMMC_FLAG_RXFIFOHF:   Receive FIFO Half Full
+  *            @arg SDMMC_FLAG_TXFIFOF:    Transmit FIFO full
+  *            @arg SDMMC_FLAG_RXFIFOF:    Receive FIFO full
+  *            @arg SDMMC_FLAG_TXFIFOE:    Transmit FIFO empty
+  *            @arg SDMMC_FLAG_RXFIFOE:    Receive FIFO empty
+  *            @arg SDMMC_FLAG_BUSYD0:     Inverted value of SDMMC_D0 line (Busy)
+  *            @arg SDMMC_FLAG_BUSYD0END:  End of SDMMC_D0 Busy following a CMD response detected
+  *            @arg SDMMC_FLAG_SDIOIT:     SDIO interrupt received
+  *            @arg SDMMC_FLAG_ACKFAIL:    Boot Acknowledgment received
+  *            @arg SDMMC_FLAG_ACKTIMEOUT: Boot Acknowledgment timeout
+  *            @arg SDMMC_FLAG_VSWEND:     Voltage switch critical timing section completion
+  *            @arg SDMMC_FLAG_CKSTOP:     SDMMC_CK stopped in Voltage switch procedure
+  *            @arg SDMMC_FLAG_IDMATE:     IDMA transfer error
+  *            @arg SDMMC_FLAG_IDMABTC:    IDMA buffer transfer complete
+  * @retval The new state of SDMMC_FLAG (SET or RESET).
+  */
+#define __SDMMC_GET_FLAG(__INSTANCE__, __FLAG__)  (((__INSTANCE__)->STA &(__FLAG__)) != 0U)
+
+
+/**
+  * @brief  Clears the SDMMC pending flags.
+  * @param  __INSTANCE__ Pointer to SDMMC register base
+  * @param  __FLAG__ specifies the flag to clear.
+  *          This parameter can be one or a combination of the following values:
+  *            @arg SDMMC_FLAG_CCRCFAIL:   Command response received (CRC check failed)
+  *            @arg SDMMC_FLAG_DCRCFAIL:   Data block sent/received (CRC check failed)
+  *            @arg SDMMC_FLAG_CTIMEOUT:   Command response timeout
+  *            @arg SDMMC_FLAG_DTIMEOUT:   Data timeout
+  *            @arg SDMMC_FLAG_TXUNDERR:   Transmit FIFO underrun error
+  *            @arg SDMMC_FLAG_RXOVERR:    Received FIFO overrun error
+  *            @arg SDMMC_FLAG_CMDREND:    Command response received (CRC check passed)
+  *            @arg SDMMC_FLAG_CMDSENT:    Command sent (no response required)
+  *            @arg SDMMC_FLAG_DATAEND:    Data end (data counter, DATACOUNT, is zero)
+  *            @arg SDMMC_FLAG_DHOLD:      Data transfer Hold
+  *            @arg SDMMC_FLAG_DBCKEND:    Data block sent/received (CRC check passed)
+  *            @arg SDMMC_FLAG_DABORT:     Data transfer aborted by CMD12
+  *            @arg SDMMC_FLAG_BUSYD0END:  End of SDMMC_D0 Busy following a CMD response detected
+  *            @arg SDMMC_FLAG_SDIOIT:     SDIO interrupt received
+  *            @arg SDMMC_FLAG_ACKFAIL:    Boot Acknowledgment received
+  *            @arg SDMMC_FLAG_ACKTIMEOUT: Boot Acknowledgment timeout
+  *            @arg SDMMC_FLAG_VSWEND:     Voltage switch critical timing section completion
+  *            @arg SDMMC_FLAG_CKSTOP:     SDMMC_CK stopped in Voltage switch procedure
+  *            @arg SDMMC_FLAG_IDMATE:     IDMA transfer error
+  *            @arg SDMMC_FLAG_IDMABTC:    IDMA buffer transfer complete
+  * @retval None
+  */
+#define __SDMMC_CLEAR_FLAG(__INSTANCE__, __FLAG__)  ((__INSTANCE__)->ICR = (__FLAG__))
+
+/**
+  * @brief  Checks whether the specified SDMMC interrupt has occurred or not.
+  * @param  __INSTANCE__ Pointer to SDMMC register base
+  * @param  __INTERRUPT__ specifies the SDMMC interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg SDMMC_IT_CCRCFAIL:   Command response received (CRC check failed) interrupt
+  *            @arg SDMMC_IT_DCRCFAIL:   Data block sent/received (CRC check failed) interrupt
+  *            @arg SDMMC_IT_CTIMEOUT:   Command response timeout interrupt
+  *            @arg SDMMC_IT_DTIMEOUT:   Data timeout interrupt
+  *            @arg SDMMC_IT_TXUNDERR:   Transmit FIFO underrun error interrupt
+  *            @arg SDMMC_IT_RXOVERR:    Received FIFO overrun error interrupt
+  *            @arg SDMMC_IT_CMDREND:    Command response received (CRC check passed) interrupt
+  *            @arg SDMMC_IT_CMDSENT:    Command sent (no response required) interrupt
+  *            @arg SDMMC_IT_DATAEND:    Data end (data counter, DATACOUNT, is zero) interrupt
+  *            @arg SDMMC_IT_DHOLD:      Data transfer Hold interrupt
+  *            @arg SDMMC_IT_DBCKEND:    Data block sent/received (CRC check passed) interrupt
+  *            @arg SDMMC_IT_DABORT:     Data transfer aborted by CMD12 interrupt
+  *            @arg SDMMC_IT_TXFIFOHE:   Transmit FIFO Half Empty interrupt
+  *            @arg SDMMC_IT_RXFIFOHF:   Receive FIFO Half Full interrupt
+  *            @arg SDMMC_IT_RXFIFOF:    Receive FIFO full interrupt
+  *            @arg SDMMC_IT_TXFIFOE:    Transmit FIFO empty interrupt
+  *            @arg SDMMC_IT_BUSYD0END:  End of SDMMC_D0 Busy following a CMD response detected interrupt
+  *            @arg SDMMC_IT_SDIOIT:     SDIO interrupt received interrupt
+  *            @arg SDMMC_IT_ACKFAIL:    Boot Acknowledgment received interrupt
+  *            @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt
+  *            @arg SDMMC_IT_VSWEND:     Voltage switch critical timing section completion interrupt
+  *            @arg SDMMC_IT_CKSTOP:     SDMMC_CK stopped in Voltage switch procedure interrupt
+  *            @arg SDMMC_IT_IDMABTC:    IDMA buffer transfer complete interrupt
+  * @retval The new state of SDMMC_IT (SET or RESET).
+  */
+#define __SDMMC_GET_IT(__INSTANCE__, __INTERRUPT__)  (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__INTERRUPT__))
+
+/**
+  * @brief  Clears the SDMMC's interrupt pending bits.
+  * @param  __INSTANCE__ Pointer to SDMMC register base
+  * @param  __INTERRUPT__ specifies the interrupt pending bit to clear.
+  *          This parameter can be one or a combination of the following values:
+  *            @arg SDMMC_IT_CCRCFAIL:   Command response received (CRC check failed) interrupt
+  *            @arg SDMMC_IT_DCRCFAIL:   Data block sent/received (CRC check failed) interrupt
+  *            @arg SDMMC_IT_CTIMEOUT:   Command response timeout interrupt
+  *            @arg SDMMC_IT_DTIMEOUT:   Data timeout interrupt
+  *            @arg SDMMC_IT_TXUNDERR:   Transmit FIFO underrun error interrupt
+  *            @arg SDMMC_IT_RXOVERR:    Received FIFO overrun error interrupt
+  *            @arg SDMMC_IT_CMDREND:    Command response received (CRC check passed) interrupt
+  *            @arg SDMMC_IT_CMDSENT:    Command sent (no response required) interrupt
+  *            @arg SDMMC_IT_DATAEND:    Data end (data counter, DATACOUNT, is zero) interrupt
+  *            @arg SDMMC_IT_DHOLD:      Data transfer Hold interrupt
+  *            @arg SDMMC_IT_DBCKEND:    Data block sent/received (CRC check passed) interrupt
+  *            @arg SDMMC_IT_DABORT:     Data transfer aborted by CMD12 interrupt
+  *            @arg SDMMC_IT_BUSYD0END:  End of SDMMC_D0 Busy following a CMD response detected interrupt
+  *            @arg SDMMC_IT_SDIOIT:     SDIO interrupt received interrupt
+  *            @arg SDMMC_IT_ACKFAIL:    Boot Acknowledgment received interrupt
+  *            @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt
+  *            @arg SDMMC_IT_VSWEND:     Voltage switch critical timing section completion interrupt
+  *            @arg SDMMC_IT_CKSTOP:     SDMMC_CK stopped in Voltage switch procedure interrupt
+  *            @arg SDMMC_IT_IDMABTC:    IDMA buffer transfer complete interrupt
+  * @retval None
+  */
+#define __SDMMC_CLEAR_IT(__INSTANCE__, __INTERRUPT__)  ((__INSTANCE__)->ICR = (__INTERRUPT__))
+
+/**
+  * @brief  Enable Start the SD I/O Read Wait operation.
+  * @param  __INSTANCE__ Pointer to SDMMC register base
+  * @retval None
+  */
+#define __SDMMC_START_READWAIT_ENABLE(__INSTANCE__)  ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_RWSTART)
+
+/**
+  * @brief  Disable Start the SD I/O Read Wait operations.
+  * @param  __INSTANCE__ Pointer to SDMMC register base
+  * @retval None
+  */
+#define __SDMMC_START_READWAIT_DISABLE(__INSTANCE__)  ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_RWSTART)
+
+/**
+  * @brief  Enable Start the SD I/O Read Wait operation.
+  * @param  __INSTANCE__ Pointer to SDMMC register base
+  * @retval None
+  */
+#define __SDMMC_STOP_READWAIT_ENABLE(__INSTANCE__)  ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_RWSTOP)
+
+/**
+  * @brief  Disable Stop the SD I/O Read Wait operations.
+  * @param  __INSTANCE__ Pointer to SDMMC register base
+  * @retval None
+  */
+#define __SDMMC_STOP_READWAIT_DISABLE(__INSTANCE__)  ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_RWSTOP)
+
+/**
+  * @brief  Enable the SD I/O Mode Operation.
+  * @param  __INSTANCE__ Pointer to SDMMC register base
+  * @retval None
+  */
+#define __SDMMC_OPERATION_ENABLE(__INSTANCE__)  ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_SDIOEN)
+
+/**
+  * @brief  Disable the SD I/O Mode Operation.
+  * @param  __INSTANCE__ Pointer to SDMMC register base
+  * @retval None
+  */
+#define __SDMMC_OPERATION_DISABLE(__INSTANCE__)  ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_SDIOEN)
+
+/**
+  * @brief  Enable the SD I/O Suspend command sending.
+  * @param  __INSTANCE__ Pointer to SDMMC register base
+  * @retval None
+  */
+#define __SDMMC_SUSPEND_CMD_ENABLE(__INSTANCE__)  ((__INSTANCE__)->CMD |= SDMMC_CMD_CMDSUSPEND)
+
+/**
+  * @brief  Disable the SD I/O Suspend command sending.
+  * @param  __INSTANCE__ Pointer to SDMMC register base
+  * @retval None
+  */
+#define __SDMMC_SUSPEND_CMD_DISABLE(__INSTANCE__)  ((__INSTANCE__)->CMD &= ~SDMMC_CMD_CMDSUSPEND)
+
+/**
+  * @brief  Enable the CMDTRANS mode.
+  * @param  __INSTANCE__ Pointer to SDMMC register base
+  * @retval None
+  */
+#define __SDMMC_CMDTRANS_ENABLE(__INSTANCE__)  ((__INSTANCE__)->CMD |= SDMMC_CMD_CMDTRANS)
+
+/**
+  * @brief  Disable the CMDTRANS mode.
+  * @param  __INSTANCE__ Pointer to SDMMC register base
+  * @retval None
+  */
+#define __SDMMC_CMDTRANS_DISABLE(__INSTANCE__)  ((__INSTANCE__)->CMD &= ~SDMMC_CMD_CMDTRANS)
+
+/**
+  * @brief  Enable the CMDSTOP mode.
+  * @param  __INSTANCE__ Pointer to SDMMC register base
+  * @retval None
+  */
+#define __SDMMC_CMDSTOP_ENABLE(__INSTANCE__)  ((__INSTANCE__)->CMD |= SDMMC_CMD_CMDSTOP)
+
+/**
+  * @brief  Disable the CMDSTOP mode.
+  * @param  __INSTANCE__ Pointer to SDMMC register base
+  * @retval None
+  */
+#define __SDMMC_CMDSTOP_DISABLE(__INSTANCE__)  ((__INSTANCE__)->CMD &= ~SDMMC_CMD_CMDSTOP)
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup SDMMC_LL_Exported_Functions
+  * @{
+  */
+
+/* Initialization/de-initialization functions  **********************************/
+/** @addtogroup HAL_SDMMC_LL_Group1
+  * @{
+  */
+HAL_StatusTypeDef SDMMC_Init(SDMMC_TypeDef *SDMMCx, SDMMC_InitTypeDef Init);
+/**
+  * @}
+  */
+
+/* I/O operation functions  *****************************************************/
+/** @addtogroup HAL_SDMMC_LL_Group2
+  * @{
+  */
+uint32_t          SDMMC_ReadFIFO(SDMMC_TypeDef *SDMMCx);
+HAL_StatusTypeDef SDMMC_WriteFIFO(SDMMC_TypeDef *SDMMCx, uint32_t *pWriteData);
+/**
+  * @}
+  */
+
+/* Peripheral Control functions  ************************************************/
+/** @addtogroup HAL_SDMMC_LL_Group3
+  * @{
+  */
+HAL_StatusTypeDef SDMMC_PowerState_ON(SDMMC_TypeDef *SDMMCx);
+HAL_StatusTypeDef SDMMC_PowerState_Cycle(SDMMC_TypeDef *SDMMCx);
+HAL_StatusTypeDef SDMMC_PowerState_OFF(SDMMC_TypeDef *SDMMCx);
+uint32_t          SDMMC_GetPowerState(SDMMC_TypeDef *SDMMCx);
+
+/* Command path state machine (CPSM) management functions */
+HAL_StatusTypeDef SDMMC_SendCommand(SDMMC_TypeDef *SDMMCx, SDMMC_CmdInitTypeDef *Command);
+uint8_t           SDMMC_GetCommandResponse(SDMMC_TypeDef *SDMMCx);
+uint32_t          SDMMC_GetResponse(SDMMC_TypeDef *SDMMCx, uint32_t Response);
+
+/* Data path state machine (DPSM) management functions */
+HAL_StatusTypeDef SDMMC_ConfigData(SDMMC_TypeDef *SDMMCx, SDMMC_DataInitTypeDef *Data);
+uint32_t          SDMMC_GetDataCounter(SDMMC_TypeDef *SDMMCx);
+uint32_t          SDMMC_GetFIFOCount(SDMMC_TypeDef *SDMMCx);
+
+/* SDMMC Cards mode management functions */
+HAL_StatusTypeDef SDMMC_SetSDMMCReadWaitMode(SDMMC_TypeDef *SDMMCx, uint32_t SDMMC_ReadWaitMode);
+/**
+  * @}
+  */
+
+/* SDMMC Commands management functions ******************************************/
+/** @addtogroup HAL_SDMMC_LL_Group4
+  * @{
+  */
+uint32_t SDMMC_CmdBlockLength(SDMMC_TypeDef *SDMMCx, uint32_t BlockSize);
+uint32_t SDMMC_CmdReadSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd);
+uint32_t SDMMC_CmdReadMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd);
+uint32_t SDMMC_CmdWriteSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd);
+uint32_t SDMMC_CmdWriteMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd);
+uint32_t SDMMC_CmdEraseStartAdd(SDMMC_TypeDef *SDMMCx, uint32_t StartAdd);
+uint32_t SDMMC_CmdSDEraseStartAdd(SDMMC_TypeDef *SDMMCx, uint32_t StartAdd);
+uint32_t SDMMC_CmdEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd);
+uint32_t SDMMC_CmdSDEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd);
+uint32_t SDMMC_CmdErase(SDMMC_TypeDef *SDMMCx, uint32_t EraseType);
+uint32_t SDMMC_CmdStopTransfer(SDMMC_TypeDef *SDMMCx);
+uint32_t SDMMC_CmdSelDesel(SDMMC_TypeDef *SDMMCx, uint32_t Addr);
+uint32_t SDMMC_CmdGoIdleState(SDMMC_TypeDef *SDMMCx);
+uint32_t SDMMC_CmdOperCond(SDMMC_TypeDef *SDMMCx);
+uint32_t SDMMC_CmdAppCommand(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
+uint32_t SDMMC_CmdAppOperCommand(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
+uint32_t SDMMC_CmdBusWidth(SDMMC_TypeDef *SDMMCx, uint32_t BusWidth);
+uint32_t SDMMC_CmdSendSCR(SDMMC_TypeDef *SDMMCx);
+uint32_t SDMMC_CmdSendCID(SDMMC_TypeDef *SDMMCx);
+uint32_t SDMMC_CmdSendCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
+uint32_t SDMMC_CmdSetRelAdd(SDMMC_TypeDef *SDMMCx, uint16_t *pRCA);
+uint32_t SDMMC_CmdSetRelAddMmc(SDMMC_TypeDef *SDMMCx, uint16_t RCA);
+uint32_t SDMMC_CmdSleepMmc(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
+uint32_t SDMMC_CmdSendStatus(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
+uint32_t SDMMC_CmdStatusRegister(SDMMC_TypeDef *SDMMCx);
+uint32_t SDMMC_CmdVoltageSwitch(SDMMC_TypeDef *SDMMCx);
+uint32_t SDMMC_CmdOpCondition(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
+uint32_t SDMMC_CmdSwitch(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
+uint32_t SDMMC_CmdSendEXTCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
+/**
+  * @}
+  */
+
+/* SDMMC Responses management functions *****************************************/
+/** @addtogroup HAL_SDMMC_LL_Group5
+  * @{
+  */
+uint32_t SDMMC_GetCmdResp1(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint32_t Timeout);
+uint32_t SDMMC_GetCmdResp2(SDMMC_TypeDef *SDMMCx);
+uint32_t SDMMC_GetCmdResp3(SDMMC_TypeDef *SDMMCx);
+uint32_t SDMMC_GetCmdResp6(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint16_t *pRCA);
+uint32_t SDMMC_GetCmdResp7(SDMMC_TypeDef *SDMMCx);
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32H7xx_LL_SDMMC_H */
diff --git a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_tim.h b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_tim.h
new file mode 100644
index 0000000..f68a4e0
--- /dev/null
+++ b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_tim.h
@@ -0,0 +1,5209 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_ll_tim.h
+  * @author  MCD Application Team
+  * @brief   Header file of TIM LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32H7xx_LL_TIM_H
+#define __STM32H7xx_LL_TIM_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx.h"
+
+/** @addtogroup STM32H7xx_LL_Driver
+  * @{
+  */
+
+#if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM6) || defined (TIM7) || defined (TIM8) || defined (TIM12) || defined (TIM13) || defined (TIM14) || defined (TIM15) || defined (TIM16) || defined (TIM17) || defined (TIM23) || defined (TIM24)
+
+/** @defgroup TIM_LL TIM
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup TIM_LL_Private_Variables TIM Private Variables
+  * @{
+  */
+static const uint8_t OFFSET_TAB_CCMRx[] =
+{
+  0x00U,   /* 0: TIMx_CH1  */
+  0x00U,   /* 1: TIMx_CH1N */
+  0x00U,   /* 2: TIMx_CH2  */
+  0x00U,   /* 3: TIMx_CH2N */
+  0x04U,   /* 4: TIMx_CH3  */
+  0x04U,   /* 5: TIMx_CH3N */
+  0x04U,   /* 6: TIMx_CH4  */
+  0x3CU,   /* 7: TIMx_CH5  */
+  0x3CU    /* 8: TIMx_CH6  */
+};
+
+static const uint8_t SHIFT_TAB_OCxx[] =
+{
+  0U,            /* 0: OC1M, OC1FE, OC1PE */
+  0U,            /* 1: - NA */
+  8U,            /* 2: OC2M, OC2FE, OC2PE */
+  0U,            /* 3: - NA */
+  0U,            /* 4: OC3M, OC3FE, OC3PE */
+  0U,            /* 5: - NA */
+  8U,            /* 6: OC4M, OC4FE, OC4PE */
+  0U,            /* 7: OC5M, OC5FE, OC5PE */
+  8U             /* 8: OC6M, OC6FE, OC6PE */
+};
+
+static const uint8_t SHIFT_TAB_ICxx[] =
+{
+  0U,            /* 0: CC1S, IC1PSC, IC1F */
+  0U,            /* 1: - NA */
+  8U,            /* 2: CC2S, IC2PSC, IC2F */
+  0U,            /* 3: - NA */
+  0U,            /* 4: CC3S, IC3PSC, IC3F */
+  0U,            /* 5: - NA */
+  8U,            /* 6: CC4S, IC4PSC, IC4F */
+  0U,            /* 7: - NA */
+  0U             /* 8: - NA */
+};
+
+static const uint8_t SHIFT_TAB_CCxP[] =
+{
+  0U,            /* 0: CC1P */
+  2U,            /* 1: CC1NP */
+  4U,            /* 2: CC2P */
+  6U,            /* 3: CC2NP */
+  8U,            /* 4: CC3P */
+  10U,           /* 5: CC3NP */
+  12U,           /* 6: CC4P */
+  16U,           /* 7: CC5P */
+  20U            /* 8: CC6P */
+};
+
+static const uint8_t SHIFT_TAB_OISx[] =
+{
+  0U,            /* 0: OIS1 */
+  1U,            /* 1: OIS1N */
+  2U,            /* 2: OIS2 */
+  3U,            /* 3: OIS2N */
+  4U,            /* 4: OIS3 */
+  5U,            /* 5: OIS3N */
+  6U,            /* 6: OIS4 */
+  8U,            /* 7: OIS5 */
+  10U            /* 8: OIS6 */
+};
+/**
+  * @}
+  */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup TIM_LL_Private_Constants TIM Private Constants
+  * @{
+  */
+
+#if   defined(TIM_BREAK_INPUT_SUPPORT)
+/* Defines used for the bit position in the register and perform offsets */
+#define TIM_POSITION_BRK_SOURCE            (POSITION_VAL(Source) & 0x1FUL)
+
+/* Generic bit definitions for TIMx_AF1 register */
+#define TIMx_AF1_BKINP     TIM1_AF1_BKINP     /*!< BRK BKIN input polarity */
+#define TIMx_AF1_ETRSEL    TIM1_AF1_ETRSEL    /*!< TIMx ETR source selection */
+#endif /* TIM_BREAK_INPUT_SUPPORT */
+
+
+/* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */
+#define DT_DELAY_1 ((uint8_t)0x7F)
+#define DT_DELAY_2 ((uint8_t)0x3F)
+#define DT_DELAY_3 ((uint8_t)0x1F)
+#define DT_DELAY_4 ((uint8_t)0x1F)
+
+/* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */
+#define DT_RANGE_1 ((uint8_t)0x00)
+#define DT_RANGE_2 ((uint8_t)0x80)
+#define DT_RANGE_3 ((uint8_t)0xC0)
+#define DT_RANGE_4 ((uint8_t)0xE0)
+
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup TIM_LL_Private_Macros TIM Private Macros
+  * @{
+  */
+/** @brief  Convert channel id into channel index.
+  * @param  __CHANNEL__ This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH1N
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH2N
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH3N
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @retval none
+  */
+#define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \
+  (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
+   ((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\
+   ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
+   ((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\
+   ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\
+   ((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U :\
+   ((__CHANNEL__) == LL_TIM_CHANNEL_CH4) ? 6U :\
+   ((__CHANNEL__) == LL_TIM_CHANNEL_CH5) ? 7U : 8U)
+
+/** @brief  Calculate the deadtime sampling period(in ps).
+  * @param  __TIMCLK__ timer input clock frequency (in Hz).
+  * @param  __CKD__ This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV1
+  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV2
+  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV4
+  * @retval none
+  */
+#define TIM_CALC_DTS(__TIMCLK__, __CKD__)                                                        \
+  (((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__))         : \
+   ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \
+   ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U)))
+/**
+  * @}
+  */
+
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup TIM_LL_ES_INIT TIM Exported Init structure
+  * @{
+  */
+
+/**
+  * @brief  TIM Time Base configuration structure definition.
+  */
+typedef struct
+{
+  uint16_t Prescaler;         /*!< Specifies the prescaler value used to divide the TIM clock.
+                                   This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
+
+                                   This feature can be modified afterwards using unitary function
+                                   @ref LL_TIM_SetPrescaler().*/
+
+  uint32_t CounterMode;       /*!< Specifies the counter mode.
+                                   This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE.
+
+                                   This feature can be modified afterwards using unitary function
+                                   @ref LL_TIM_SetCounterMode().*/
+
+  uint32_t Autoreload;        /*!< Specifies the auto reload value to be loaded into the active
+                                   Auto-Reload Register at the next update event.
+                                   This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
+                                   Some timer instances may support 32 bits counters. In that case this parameter must
+                                   be a number between 0x0000 and 0xFFFFFFFF.
+
+                                   This feature can be modified afterwards using unitary function
+                                   @ref LL_TIM_SetAutoReload().*/
+
+  uint32_t ClockDivision;     /*!< Specifies the clock division.
+                                   This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION.
+
+                                   This feature can be modified afterwards using unitary function
+                                   @ref LL_TIM_SetClockDivision().*/
+
+  uint32_t RepetitionCounter;  /*!< Specifies the repetition counter value. Each time the RCR downcounter
+                                   reaches zero, an update event is generated and counting restarts
+                                   from the RCR value (N).
+                                   This means in PWM mode that (N+1) corresponds to:
+                                      - the number of PWM periods in edge-aligned mode
+                                      - the number of half PWM period in center-aligned mode
+                                   GP timers: this parameter must be a number between Min_Data = 0x00 and
+                                   Max_Data = 0xFF.
+                                   Advanced timers: this parameter must be a number between Min_Data = 0x0000 and
+                                   Max_Data = 0xFFFF.
+
+                                   This feature can be modified afterwards using unitary function
+                                   @ref LL_TIM_SetRepetitionCounter().*/
+} LL_TIM_InitTypeDef;
+
+/**
+  * @brief  TIM Output Compare configuration structure definition.
+  */
+typedef struct
+{
+  uint32_t OCMode;        /*!< Specifies the output mode.
+                               This parameter can be a value of @ref TIM_LL_EC_OCMODE.
+
+                               This feature can be modified afterwards using unitary function
+                               @ref LL_TIM_OC_SetMode().*/
+
+  uint32_t OCState;       /*!< Specifies the TIM Output Compare state.
+                               This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
+
+                               This feature can be modified afterwards using unitary functions
+                               @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
+
+  uint32_t OCNState;      /*!< Specifies the TIM complementary Output Compare state.
+                               This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
+
+                               This feature can be modified afterwards using unitary functions
+                               @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
+
+  uint32_t CompareValue;  /*!< Specifies the Compare value to be loaded into the Capture Compare Register.
+                               This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
+
+                               This feature can be modified afterwards using unitary function
+                               LL_TIM_OC_SetCompareCHx (x=1..6).*/
+
+  uint32_t OCPolarity;    /*!< Specifies the output polarity.
+                               This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
+
+                               This feature can be modified afterwards using unitary function
+                               @ref LL_TIM_OC_SetPolarity().*/
+
+  uint32_t OCNPolarity;   /*!< Specifies the complementary output polarity.
+                               This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
+
+                               This feature can be modified afterwards using unitary function
+                               @ref LL_TIM_OC_SetPolarity().*/
+
+
+  uint32_t OCIdleState;   /*!< Specifies the TIM Output Compare pin state during Idle state.
+                               This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
+
+                               This feature can be modified afterwards using unitary function
+                               @ref LL_TIM_OC_SetIdleState().*/
+
+  uint32_t OCNIdleState;  /*!< Specifies the TIM Output Compare pin state during Idle state.
+                               This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
+
+                               This feature can be modified afterwards using unitary function
+                               @ref LL_TIM_OC_SetIdleState().*/
+} LL_TIM_OC_InitTypeDef;
+
+/**
+  * @brief  TIM Input Capture configuration structure definition.
+  */
+
+typedef struct
+{
+
+  uint32_t ICPolarity;    /*!< Specifies the active edge of the input signal.
+                               This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
+
+                               This feature can be modified afterwards using unitary function
+                               @ref LL_TIM_IC_SetPolarity().*/
+
+  uint32_t ICActiveInput; /*!< Specifies the input.
+                               This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
+
+                               This feature can be modified afterwards using unitary function
+                               @ref LL_TIM_IC_SetActiveInput().*/
+
+  uint32_t ICPrescaler;   /*!< Specifies the Input Capture Prescaler.
+                               This parameter can be a value of @ref TIM_LL_EC_ICPSC.
+
+                               This feature can be modified afterwards using unitary function
+                               @ref LL_TIM_IC_SetPrescaler().*/
+
+  uint32_t ICFilter;      /*!< Specifies the input capture filter.
+                               This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
+
+                               This feature can be modified afterwards using unitary function
+                               @ref LL_TIM_IC_SetFilter().*/
+} LL_TIM_IC_InitTypeDef;
+
+
+/**
+  * @brief  TIM Encoder interface configuration structure definition.
+  */
+typedef struct
+{
+  uint32_t EncoderMode;     /*!< Specifies the encoder resolution (x2 or x4).
+                                 This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE.
+
+                                 This feature can be modified afterwards using unitary function
+                                 @ref LL_TIM_SetEncoderMode().*/
+
+  uint32_t IC1Polarity;     /*!< Specifies the active edge of TI1 input.
+                                 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
+
+                                 This feature can be modified afterwards using unitary function
+                                 @ref LL_TIM_IC_SetPolarity().*/
+
+  uint32_t IC1ActiveInput;  /*!< Specifies the TI1 input source
+                                 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
+
+                                 This feature can be modified afterwards using unitary function
+                                 @ref LL_TIM_IC_SetActiveInput().*/
+
+  uint32_t IC1Prescaler;    /*!< Specifies the TI1 input prescaler value.
+                                 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
+
+                                 This feature can be modified afterwards using unitary function
+                                 @ref LL_TIM_IC_SetPrescaler().*/
+
+  uint32_t IC1Filter;       /*!< Specifies the TI1 input filter.
+                                 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
+
+                                 This feature can be modified afterwards using unitary function
+                                 @ref LL_TIM_IC_SetFilter().*/
+
+  uint32_t IC2Polarity;      /*!< Specifies the active edge of TI2 input.
+                                 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
+
+                                 This feature can be modified afterwards using unitary function
+                                 @ref LL_TIM_IC_SetPolarity().*/
+
+  uint32_t IC2ActiveInput;  /*!< Specifies the TI2 input source
+                                 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
+
+                                 This feature can be modified afterwards using unitary function
+                                 @ref LL_TIM_IC_SetActiveInput().*/
+
+  uint32_t IC2Prescaler;    /*!< Specifies the TI2 input prescaler value.
+                                 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
+
+                                 This feature can be modified afterwards using unitary function
+                                 @ref LL_TIM_IC_SetPrescaler().*/
+
+  uint32_t IC2Filter;       /*!< Specifies the TI2 input filter.
+                                 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
+
+                                 This feature can be modified afterwards using unitary function
+                                 @ref LL_TIM_IC_SetFilter().*/
+
+} LL_TIM_ENCODER_InitTypeDef;
+
+/**
+  * @brief  TIM Hall sensor interface configuration structure definition.
+  */
+typedef struct
+{
+
+  uint32_t IC1Polarity;        /*!< Specifies the active edge of TI1 input.
+                                    This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
+
+                                    This feature can be modified afterwards using unitary function
+                                    @ref LL_TIM_IC_SetPolarity().*/
+
+  uint32_t IC1Prescaler;       /*!< Specifies the TI1 input prescaler value.
+                                    Prescaler must be set to get a maximum counter period longer than the
+                                    time interval between 2 consecutive changes on the Hall inputs.
+                                    This parameter can be a value of @ref TIM_LL_EC_ICPSC.
+
+                                    This feature can be modified afterwards using unitary function
+                                    @ref LL_TIM_IC_SetPrescaler().*/
+
+  uint32_t IC1Filter;          /*!< Specifies the TI1 input filter.
+                                    This parameter can be a value of
+                                    @ref TIM_LL_EC_IC_FILTER.
+
+                                    This feature can be modified afterwards using unitary function
+                                    @ref LL_TIM_IC_SetFilter().*/
+
+  uint32_t CommutationDelay;   /*!< Specifies the compare value to be loaded into the Capture Compare Register.
+                                    A positive pulse (TRGO event) is generated with a programmable delay every time
+                                    a change occurs on the Hall inputs.
+                                    This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
+
+                                    This feature can be modified afterwards using unitary function
+                                    @ref LL_TIM_OC_SetCompareCH2().*/
+} LL_TIM_HALLSENSOR_InitTypeDef;
+
+/**
+  * @brief  BDTR (Break and Dead Time) structure definition
+  */
+typedef struct
+{
+  uint32_t OSSRState;            /*!< Specifies the Off-State selection used in Run mode.
+                                      This parameter can be a value of @ref TIM_LL_EC_OSSR
+
+                                      This feature can be modified afterwards using unitary function
+                                      @ref LL_TIM_SetOffStates()
+
+                                      @note This bit-field cannot be modified as long as LOCK level 2 has been
+                                       programmed. */
+
+  uint32_t OSSIState;            /*!< Specifies the Off-State used in Idle state.
+                                      This parameter can be a value of @ref TIM_LL_EC_OSSI
+
+                                      This feature can be modified afterwards using unitary function
+                                      @ref LL_TIM_SetOffStates()
+
+                                      @note This bit-field cannot be modified as long as LOCK level 2 has been
+                                      programmed. */
+
+  uint32_t LockLevel;            /*!< Specifies the LOCK level parameters.
+                                      This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL
+
+                                      @note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR
+                                      register has been written, their content is frozen until the next reset.*/
+
+  uint8_t DeadTime;              /*!< Specifies the delay time between the switching-off and the
+                                      switching-on of the outputs.
+                                      This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF.
+
+                                      This feature can be modified afterwards using unitary function
+                                      @ref LL_TIM_OC_SetDeadTime()
+
+                                      @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been
+                                       programmed. */
+
+  uint16_t BreakState;           /*!< Specifies whether the TIM Break input is enabled or not.
+                                      This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE
+
+                                      This feature can be modified afterwards using unitary functions
+                                      @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK()
+
+                                      @note This bit-field can not be modified as long as LOCK level 1 has been
+                                      programmed. */
+
+  uint32_t BreakPolarity;        /*!< Specifies the TIM Break Input pin polarity.
+                                      This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY
+
+                                      This feature can be modified afterwards using unitary function
+                                      @ref LL_TIM_ConfigBRK()
+
+                                      @note This bit-field can not be modified as long as LOCK level 1 has been
+                                      programmed. */
+
+  uint32_t BreakFilter;          /*!< Specifies the TIM Break Filter.
+                                      This parameter can be a value of @ref TIM_LL_EC_BREAK_FILTER
+
+                                      This feature can be modified afterwards using unitary function
+                                      @ref LL_TIM_ConfigBRK()
+
+                                      @note This bit-field can not be modified as long as LOCK level 1 has been
+                                      programmed. */
+
+#if defined(TIM_BDTR_BKBID)
+  uint32_t BreakAFMode;           /*!< Specifies the alternate function mode of the break input.
+                                      This parameter can be a value of @ref TIM_LL_EC_BREAK_AFMODE
+
+                                      This feature can be modified afterwards using unitary functions
+                                      @ref LL_TIM_ConfigBRK()
+
+                                      @note Bidirectional break input is only supported by advanced timers instances.
+
+                                      @note This bit-field can not be modified as long as LOCK level 1 has been
+                                      programmed. */
+
+#endif /*TIM_BDTR_BKBID */
+  uint32_t Break2State;          /*!< Specifies whether the TIM Break2 input is enabled or not.
+                                      This parameter can be a value of @ref TIM_LL_EC_BREAK2_ENABLE
+
+                                      This feature can be modified afterwards using unitary functions
+                                      @ref LL_TIM_EnableBRK2() or @ref LL_TIM_DisableBRK2()
+
+                                      @note This bit-field can not be modified as long as LOCK level 1 has been
+                                      programmed. */
+
+  uint32_t Break2Polarity;        /*!< Specifies the TIM Break2 Input pin polarity.
+                                      This parameter can be a value of @ref TIM_LL_EC_BREAK2_POLARITY
+
+                                      This feature can be modified afterwards using unitary function
+                                      @ref LL_TIM_ConfigBRK2()
+
+                                      @note This bit-field can not be modified as long as LOCK level 1 has been
+                                      programmed. */
+
+  uint32_t Break2Filter;          /*!< Specifies the TIM Break2 Filter.
+                                      This parameter can be a value of @ref TIM_LL_EC_BREAK2_FILTER
+
+                                      This feature can be modified afterwards using unitary function
+                                      @ref LL_TIM_ConfigBRK2()
+
+                                      @note This bit-field can not be modified as long as LOCK level 1 has been
+                                      programmed. */
+
+#if defined(TIM_BDTR_BKBID)
+  uint32_t Break2AFMode;          /*!< Specifies the alternate function mode of the break2 input.
+                                      This parameter can be a value of @ref TIM_LL_EC_BREAK2_AFMODE
+
+                                      This feature can be modified afterwards using unitary functions
+                                      @ref LL_TIM_ConfigBRK2()
+
+                                      @note Bidirectional break input is only supported by advanced timers instances.
+
+                                      @note This bit-field can not be modified as long as LOCK level 1 has been
+                                      programmed. */
+
+#endif /*TIM_BDTR_BKBID */
+  uint32_t AutomaticOutput;      /*!< Specifies whether the TIM Automatic Output feature is enabled or not.
+                                      This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE
+
+                                      This feature can be modified afterwards using unitary functions
+                                      @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput()
+
+                                      @note This bit-field can not be modified as long as LOCK level 1 has been
+                                      programmed. */
+} LL_TIM_BDTR_InitTypeDef;
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup TIM_LL_Exported_Constants TIM Exported Constants
+  * @{
+  */
+
+/** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines
+  * @brief    Flags defines which can be used with LL_TIM_ReadReg function.
+  * @{
+  */
+#define LL_TIM_SR_UIF                          TIM_SR_UIF           /*!< Update interrupt flag */
+#define LL_TIM_SR_CC1IF                        TIM_SR_CC1IF         /*!< Capture/compare 1 interrupt flag */
+#define LL_TIM_SR_CC2IF                        TIM_SR_CC2IF         /*!< Capture/compare 2 interrupt flag */
+#define LL_TIM_SR_CC3IF                        TIM_SR_CC3IF         /*!< Capture/compare 3 interrupt flag */
+#define LL_TIM_SR_CC4IF                        TIM_SR_CC4IF         /*!< Capture/compare 4 interrupt flag */
+#define LL_TIM_SR_CC5IF                        TIM_SR_CC5IF         /*!< Capture/compare 5 interrupt flag */
+#define LL_TIM_SR_CC6IF                        TIM_SR_CC6IF         /*!< Capture/compare 6 interrupt flag */
+#define LL_TIM_SR_COMIF                        TIM_SR_COMIF         /*!< COM interrupt flag */
+#define LL_TIM_SR_TIF                          TIM_SR_TIF           /*!< Trigger interrupt flag */
+#define LL_TIM_SR_BIF                          TIM_SR_BIF           /*!< Break interrupt flag */
+#define LL_TIM_SR_B2IF                         TIM_SR_B2IF          /*!< Second break interrupt flag */
+#define LL_TIM_SR_CC1OF                        TIM_SR_CC1OF         /*!< Capture/Compare 1 overcapture flag */
+#define LL_TIM_SR_CC2OF                        TIM_SR_CC2OF         /*!< Capture/Compare 2 overcapture flag */
+#define LL_TIM_SR_CC3OF                        TIM_SR_CC3OF         /*!< Capture/Compare 3 overcapture flag */
+#define LL_TIM_SR_CC4OF                        TIM_SR_CC4OF         /*!< Capture/Compare 4 overcapture flag */
+#define LL_TIM_SR_SBIF                         TIM_SR_SBIF          /*!< System Break interrupt flag  */
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable
+  * @{
+  */
+#define LL_TIM_BREAK_DISABLE            0x00000000U             /*!< Break function disabled */
+#define LL_TIM_BREAK_ENABLE             TIM_BDTR_BKE            /*!< Break function enabled */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_BREAK2_ENABLE Break2 Enable
+  * @{
+  */
+#define LL_TIM_BREAK2_DISABLE            0x00000000U              /*!< Break2 function disabled */
+#define LL_TIM_BREAK2_ENABLE             TIM_BDTR_BK2E            /*!< Break2 function enabled */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable
+  * @{
+  */
+#define LL_TIM_AUTOMATICOUTPUT_DISABLE         0x00000000U             /*!< MOE can be set only by software */
+#define LL_TIM_AUTOMATICOUTPUT_ENABLE          TIM_BDTR_AOE            /*!< MOE can be set by software or automatically at the next update event */
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/** @defgroup TIM_LL_EC_IT IT Defines
+  * @brief    IT defines which can be used with LL_TIM_ReadReg and  LL_TIM_WriteReg functions.
+  * @{
+  */
+#define LL_TIM_DIER_UIE                        TIM_DIER_UIE         /*!< Update interrupt enable */
+#define LL_TIM_DIER_CC1IE                      TIM_DIER_CC1IE       /*!< Capture/compare 1 interrupt enable */
+#define LL_TIM_DIER_CC2IE                      TIM_DIER_CC2IE       /*!< Capture/compare 2 interrupt enable */
+#define LL_TIM_DIER_CC3IE                      TIM_DIER_CC3IE       /*!< Capture/compare 3 interrupt enable */
+#define LL_TIM_DIER_CC4IE                      TIM_DIER_CC4IE       /*!< Capture/compare 4 interrupt enable */
+#define LL_TIM_DIER_COMIE                      TIM_DIER_COMIE       /*!< COM interrupt enable */
+#define LL_TIM_DIER_TIE                        TIM_DIER_TIE         /*!< Trigger interrupt enable */
+#define LL_TIM_DIER_BIE                        TIM_DIER_BIE         /*!< Break interrupt enable */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_UPDATESOURCE Update Source
+  * @{
+  */
+#define LL_TIM_UPDATESOURCE_REGULAR            0x00000000U          /*!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request */
+#define LL_TIM_UPDATESOURCE_COUNTER            TIM_CR1_URS          /*!< Only counter overflow/underflow generates an update request */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode
+  * @{
+  */
+#define LL_TIM_ONEPULSEMODE_SINGLE             TIM_CR1_OPM          /*!< Counter stops counting at the next update event */
+#define LL_TIM_ONEPULSEMODE_REPETITIVE         0x00000000U          /*!< Counter is not stopped at update event */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode
+  * @{
+  */
+#define LL_TIM_COUNTERMODE_UP                  0x00000000U          /*!<Counter used as upcounter */
+#define LL_TIM_COUNTERMODE_DOWN                TIM_CR1_DIR          /*!< Counter used as downcounter */
+#define LL_TIM_COUNTERMODE_CENTER_DOWN         TIM_CR1_CMS_0        /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels  are set only when the counter is counting down. */
+#define LL_TIM_COUNTERMODE_CENTER_UP           TIM_CR1_CMS_1        /*!<The counter counts up and down alternatively. Output compare interrupt flags of output channels  are set only when the counter is counting up */
+#define LL_TIM_COUNTERMODE_CENTER_UP_DOWN      TIM_CR1_CMS          /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels  are set only when the counter is counting up or down. */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division
+  * @{
+  */
+#define LL_TIM_CLOCKDIVISION_DIV1              0x00000000U          /*!< tDTS=tCK_INT */
+#define LL_TIM_CLOCKDIVISION_DIV2              TIM_CR1_CKD_0        /*!< tDTS=2*tCK_INT */
+#define LL_TIM_CLOCKDIVISION_DIV4              TIM_CR1_CKD_1        /*!< tDTS=4*tCK_INT */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction
+  * @{
+  */
+#define LL_TIM_COUNTERDIRECTION_UP             0x00000000U          /*!< Timer counter counts up */
+#define LL_TIM_COUNTERDIRECTION_DOWN           TIM_CR1_DIR          /*!< Timer counter counts down */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_CCUPDATESOURCE Capture Compare  Update Source
+  * @{
+  */
+#define LL_TIM_CCUPDATESOURCE_COMG_ONLY        0x00000000U          /*!< Capture/compare control bits are updated by setting the COMG bit only */
+#define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI    TIM_CR2_CCUS         /*!< Capture/compare control bits are updated by setting the COMG bit or when a rising edge occurs on trigger input (TRGI) */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request
+  * @{
+  */
+#define LL_TIM_CCDMAREQUEST_CC                 0x00000000U          /*!< CCx DMA request sent when CCx event occurs */
+#define LL_TIM_CCDMAREQUEST_UPDATE             TIM_CR2_CCDS         /*!< CCx DMA requests sent when update event occurs */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_LOCKLEVEL Lock Level
+  * @{
+  */
+#define LL_TIM_LOCKLEVEL_OFF                   0x00000000U          /*!< LOCK OFF - No bit is write protected */
+#define LL_TIM_LOCKLEVEL_1                     TIM_BDTR_LOCK_0      /*!< LOCK Level 1 */
+#define LL_TIM_LOCKLEVEL_2                     TIM_BDTR_LOCK_1      /*!< LOCK Level 2 */
+#define LL_TIM_LOCKLEVEL_3                     TIM_BDTR_LOCK        /*!< LOCK Level 3 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_CHANNEL Channel
+  * @{
+  */
+#define LL_TIM_CHANNEL_CH1                     TIM_CCER_CC1E     /*!< Timer input/output channel 1 */
+#define LL_TIM_CHANNEL_CH1N                    TIM_CCER_CC1NE    /*!< Timer complementary output channel 1 */
+#define LL_TIM_CHANNEL_CH2                     TIM_CCER_CC2E     /*!< Timer input/output channel 2 */
+#define LL_TIM_CHANNEL_CH2N                    TIM_CCER_CC2NE    /*!< Timer complementary output channel 2 */
+#define LL_TIM_CHANNEL_CH3                     TIM_CCER_CC3E     /*!< Timer input/output channel 3 */
+#define LL_TIM_CHANNEL_CH3N                    TIM_CCER_CC3NE    /*!< Timer complementary output channel 3 */
+#define LL_TIM_CHANNEL_CH4                     TIM_CCER_CC4E     /*!< Timer input/output channel 4 */
+#define LL_TIM_CHANNEL_CH5                     TIM_CCER_CC5E     /*!< Timer output channel 5 */
+#define LL_TIM_CHANNEL_CH6                     TIM_CCER_CC6E     /*!< Timer output channel 6 */
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup TIM_LL_EC_OCSTATE Output Configuration State
+  * @{
+  */
+#define LL_TIM_OCSTATE_DISABLE                 0x00000000U             /*!< OCx is not active */
+#define LL_TIM_OCSTATE_ENABLE                  TIM_CCER_CC1E           /*!< OCx signal is output on the corresponding output pin */
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode
+  * @{
+  */
+#define LL_TIM_OCMODE_FROZEN                   0x00000000U                                              /*!<The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the output channel level */
+#define LL_TIM_OCMODE_ACTIVE                   TIM_CCMR1_OC1M_0                                         /*!<OCyREF is forced high on compare match*/
+#define LL_TIM_OCMODE_INACTIVE                 TIM_CCMR1_OC1M_1                                         /*!<OCyREF is forced low on compare match*/
+#define LL_TIM_OCMODE_TOGGLE                   (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)                    /*!<OCyREF toggles on compare match*/
+#define LL_TIM_OCMODE_FORCED_INACTIVE          TIM_CCMR1_OC1M_2                                         /*!<OCyREF is forced low*/
+#define LL_TIM_OCMODE_FORCED_ACTIVE            (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)                    /*!<OCyREF is forced high*/
+#define LL_TIM_OCMODE_PWM1                     (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)                    /*!<In upcounting, channel y is active as long as TIMx_CNT<TIMx_CCRy else inactive.  In downcounting, channel y is inactive as long as TIMx_CNT>TIMx_CCRy else active.*/
+#define LL_TIM_OCMODE_PWM2                     (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<In upcounting, channel y is inactive as long as TIMx_CNT<TIMx_CCRy else active.  In downcounting, channel y is active as long as TIMx_CNT>TIMx_CCRy else inactive*/
+#define LL_TIM_OCMODE_RETRIG_OPM1              TIM_CCMR1_OC1M_3                                         /*!<Retrigerrable OPM mode 1*/
+#define LL_TIM_OCMODE_RETRIG_OPM2              (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0)                    /*!<Retrigerrable OPM mode 2*/
+#define LL_TIM_OCMODE_COMBINED_PWM1            (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2)                    /*!<Combined PWM mode 1*/
+#define LL_TIM_OCMODE_COMBINED_PWM2            (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!<Combined PWM mode 2*/
+#define LL_TIM_OCMODE_ASSYMETRIC_PWM1          (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!<Asymmetric PWM mode 1*/
+#define LL_TIM_OCMODE_ASSYMETRIC_PWM2          (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M)                      /*!<Asymmetric PWM mode 2*/
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity
+  * @{
+  */
+#define LL_TIM_OCPOLARITY_HIGH                 0x00000000U                 /*!< OCxactive high*/
+#define LL_TIM_OCPOLARITY_LOW                  TIM_CCER_CC1P               /*!< OCxactive low*/
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_OCIDLESTATE Output Configuration Idle State
+  * @{
+  */
+#define LL_TIM_OCIDLESTATE_LOW                 0x00000000U             /*!<OCx=0 (after a dead-time if OC is implemented) when MOE=0*/
+#define LL_TIM_OCIDLESTATE_HIGH                TIM_CR2_OIS1            /*!<OCx=1 (after a dead-time if OC is implemented) when MOE=0*/
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_GROUPCH5 GROUPCH5
+  * @{
+  */
+#define LL_TIM_GROUPCH5_NONE                   0x00000000U           /*!< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */
+#define LL_TIM_GROUPCH5_OC1REFC                TIM_CCR5_GC5C1        /*!< OC1REFC is the logical AND of OC1REFC and OC5REF */
+#define LL_TIM_GROUPCH5_OC2REFC                TIM_CCR5_GC5C2        /*!< OC2REFC is the logical AND of OC2REFC and OC5REF */
+#define LL_TIM_GROUPCH5_OC3REFC                TIM_CCR5_GC5C3        /*!< OC3REFC is the logical AND of OC3REFC and OC5REF */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_ACTIVEINPUT Active Input Selection
+  * @{
+  */
+#define LL_TIM_ACTIVEINPUT_DIRECTTI            (TIM_CCMR1_CC1S_0 << 16U) /*!< ICx is mapped on TIx */
+#define LL_TIM_ACTIVEINPUT_INDIRECTTI          (TIM_CCMR1_CC1S_1 << 16U) /*!< ICx is mapped on TIy */
+#define LL_TIM_ACTIVEINPUT_TRC                 (TIM_CCMR1_CC1S << 16U)   /*!< ICx is mapped on TRC */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_ICPSC Input Configuration Prescaler
+  * @{
+  */
+#define LL_TIM_ICPSC_DIV1                      0x00000000U                    /*!< No prescaler, capture is done each time an edge is detected on the capture input */
+#define LL_TIM_ICPSC_DIV2                      (TIM_CCMR1_IC1PSC_0 << 16U)    /*!< Capture is done once every 2 events */
+#define LL_TIM_ICPSC_DIV4                      (TIM_CCMR1_IC1PSC_1 << 16U)    /*!< Capture is done once every 4 events */
+#define LL_TIM_ICPSC_DIV8                      (TIM_CCMR1_IC1PSC << 16U)      /*!< Capture is done once every 8 events */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_IC_FILTER Input Configuration Filter
+  * @{
+  */
+#define LL_TIM_IC_FILTER_FDIV1                 0x00000000U                                                        /*!< No filter, sampling is done at fDTS */
+#define LL_TIM_IC_FILTER_FDIV1_N2              (TIM_CCMR1_IC1F_0 << 16U)                                          /*!< fSAMPLING=fCK_INT, N=2 */
+#define LL_TIM_IC_FILTER_FDIV1_N4              (TIM_CCMR1_IC1F_1 << 16U)                                          /*!< fSAMPLING=fCK_INT, N=4 */
+#define LL_TIM_IC_FILTER_FDIV1_N8              ((TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)                     /*!< fSAMPLING=fCK_INT, N=8 */
+#define LL_TIM_IC_FILTER_FDIV2_N6              (TIM_CCMR1_IC1F_2 << 16U)                                          /*!< fSAMPLING=fDTS/2, N=6 */
+#define LL_TIM_IC_FILTER_FDIV2_N8              ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U)                     /*!< fSAMPLING=fDTS/2, N=8 */
+#define LL_TIM_IC_FILTER_FDIV4_N6              ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U)                     /*!< fSAMPLING=fDTS/4, N=6 */
+#define LL_TIM_IC_FILTER_FDIV4_N8              ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)  /*!< fSAMPLING=fDTS/4, N=8 */
+#define LL_TIM_IC_FILTER_FDIV8_N6              (TIM_CCMR1_IC1F_3 << 16U)                                          /*!< fSAMPLING=fDTS/8, N=6 */
+#define LL_TIM_IC_FILTER_FDIV8_N8              ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_0) << 16U)                     /*!< fSAMPLING=fDTS/8, N=8 */
+#define LL_TIM_IC_FILTER_FDIV16_N5             ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1) << 16U)                     /*!< fSAMPLING=fDTS/16, N=5 */
+#define LL_TIM_IC_FILTER_FDIV16_N6             ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)  /*!< fSAMPLING=fDTS/16, N=6 */
+#define LL_TIM_IC_FILTER_FDIV16_N8             ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2) << 16U)                     /*!< fSAMPLING=fDTS/16, N=8 */
+#define LL_TIM_IC_FILTER_FDIV32_N5             ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U)  /*!< fSAMPLING=fDTS/32, N=5 */
+#define LL_TIM_IC_FILTER_FDIV32_N6             ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U)  /*!< fSAMPLING=fDTS/32, N=6 */
+#define LL_TIM_IC_FILTER_FDIV32_N8             (TIM_CCMR1_IC1F << 16U)                                            /*!< fSAMPLING=fDTS/32, N=8 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_IC_POLARITY Input Configuration Polarity
+  * @{
+  */
+#define LL_TIM_IC_POLARITY_RISING              0x00000000U                      /*!< The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is not inverted */
+#define LL_TIM_IC_POLARITY_FALLING             TIM_CCER_CC1P                    /*!< The circuit is sensitive to TIxFP1 falling edge, TIxFP1 is inverted */
+#define LL_TIM_IC_POLARITY_BOTHEDGE            (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< The circuit is sensitive to both TIxFP1 rising and falling edges, TIxFP1 is not inverted */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_CLOCKSOURCE Clock Source
+  * @{
+  */
+#define LL_TIM_CLOCKSOURCE_INTERNAL            0x00000000U                                          /*!< The timer is clocked by the internal clock provided from the RCC */
+#define LL_TIM_CLOCKSOURCE_EXT_MODE1           (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)   /*!< Counter counts at each rising or falling edge on a selected input*/
+#define LL_TIM_CLOCKSOURCE_EXT_MODE2           TIM_SMCR_ECE                                         /*!< Counter counts at each rising or falling edge on the external trigger input ETR */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_ENCODERMODE Encoder Mode
+  * @{
+  */
+#define LL_TIM_ENCODERMODE_X2_TI1                     TIM_SMCR_SMS_0                                                     /*!< Quadrature encoder mode 1, x2 mode - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level */
+#define LL_TIM_ENCODERMODE_X2_TI2                     TIM_SMCR_SMS_1                                                     /*!< Quadrature encoder mode 2, x2 mode - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level */
+#define LL_TIM_ENCODERMODE_X4_TI12                   (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)                                   /*!< Quadrature encoder mode 3, x4 mode - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_TRGO Trigger Output
+  * @{
+  */
+#define LL_TIM_TRGO_RESET                      0x00000000U                                     /*!< UG bit from the TIMx_EGR register is used as trigger output */
+#define LL_TIM_TRGO_ENABLE                     TIM_CR2_MMS_0                                   /*!< Counter Enable signal (CNT_EN) is used as trigger output */
+#define LL_TIM_TRGO_UPDATE                     TIM_CR2_MMS_1                                   /*!< Update event is used as trigger output */
+#define LL_TIM_TRGO_CC1IF                      (TIM_CR2_MMS_1 | TIM_CR2_MMS_0)                 /*!< CC1 capture or a compare match is used as trigger output */
+#define LL_TIM_TRGO_OC1REF                     TIM_CR2_MMS_2                                   /*!< OC1REF signal is used as trigger output */
+#define LL_TIM_TRGO_OC2REF                     (TIM_CR2_MMS_2 | TIM_CR2_MMS_0)                 /*!< OC2REF signal is used as trigger output */
+#define LL_TIM_TRGO_OC3REF                     (TIM_CR2_MMS_2 | TIM_CR2_MMS_1)                 /*!< OC3REF signal is used as trigger output */
+#define LL_TIM_TRGO_OC4REF                     (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_TRGO2 Trigger Output 2
+  * @{
+  */
+#define LL_TIM_TRGO2_RESET                     0x00000000U                                                         /*!< UG bit from the TIMx_EGR register is used as trigger output 2 */
+#define LL_TIM_TRGO2_ENABLE                    TIM_CR2_MMS2_0                                                      /*!< Counter Enable signal (CNT_EN) is used as trigger output 2 */
+#define LL_TIM_TRGO2_UPDATE                    TIM_CR2_MMS2_1                                                      /*!< Update event is used as trigger output 2 */
+#define LL_TIM_TRGO2_CC1F                      (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)                                   /*!< CC1 capture or a compare match is used as trigger output 2 */
+#define LL_TIM_TRGO2_OC1                       TIM_CR2_MMS2_2                                                      /*!< OC1REF signal is used as trigger output 2 */
+#define LL_TIM_TRGO2_OC2                       (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)                                   /*!< OC2REF signal is used as trigger output 2 */
+#define LL_TIM_TRGO2_OC3                       (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1)                                   /*!< OC3REF signal is used as trigger output 2 */
+#define LL_TIM_TRGO2_OC4                       (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)                  /*!< OC4REF signal is used as trigger output 2 */
+#define LL_TIM_TRGO2_OC5                       TIM_CR2_MMS2_3                                                      /*!< OC5REF signal is used as trigger output 2 */
+#define LL_TIM_TRGO2_OC6                       (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0)                                   /*!< OC6REF signal is used as trigger output 2 */
+#define LL_TIM_TRGO2_OC4_RISINGFALLING         (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1)                                   /*!< OC4REF rising or falling edges are used as trigger output 2 */
+#define LL_TIM_TRGO2_OC6_RISINGFALLING         (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)                  /*!< OC6REF rising or falling edges are used as trigger output 2 */
+#define LL_TIM_TRGO2_OC4_RISING_OC6_RISING     (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2)                                   /*!< OC4REF or OC6REF rising edges are used as trigger output 2 */
+#define LL_TIM_TRGO2_OC4_RISING_OC6_FALLING    (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)                  /*!< OC4REF rising or OC6REF falling edges are used as trigger output 2 */
+#define LL_TIM_TRGO2_OC5_RISING_OC6_RISING     (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1)                   /*!< OC5REF or OC6REF rising edges are used as trigger output 2 */
+#define LL_TIM_TRGO2_OC5_RISING_OC6_FALLING    (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC5REF rising or OC6REF falling edges are used as trigger output 2 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_SLAVEMODE Slave Mode
+  * @{
+  */
+#define LL_TIM_SLAVEMODE_DISABLED              0x00000000U                         /*!< Slave mode disabled */
+#define LL_TIM_SLAVEMODE_RESET                 TIM_SMCR_SMS_2                      /*!< Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter */
+#define LL_TIM_SLAVEMODE_GATED                 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0)   /*!< Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high */
+#define LL_TIM_SLAVEMODE_TRIGGER               (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1)   /*!< Trigger Mode - The counter starts at a rising edge of the trigger TRGI */
+#define LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3                      /*!< Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI)  reinitializes the counter, generates an update of the registers and starts the counter */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_TS Trigger Selection
+  * @{
+  */
+#define LL_TIM_TS_ITR0                         0x00000000U                                                     /*!< Internal Trigger 0 (ITR0) is used as trigger input */
+#define LL_TIM_TS_ITR1                         TIM_SMCR_TS_0                                                   /*!< Internal Trigger 1 (ITR1) is used as trigger input */
+#define LL_TIM_TS_ITR2                         TIM_SMCR_TS_1                                                   /*!< Internal Trigger 2 (ITR2) is used as trigger input */
+#define LL_TIM_TS_ITR3                         (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)                                 /*!< Internal Trigger 3 (ITR3) is used as trigger input */
+#define LL_TIM_TS_ITR4                         (TIM_SMCR_TS_3)                                                 /*!< Internal Trigger 4 (ITR4) is used as trigger input */
+#define LL_TIM_TS_ITR5                         (TIM_SMCR_TS_0 | TIM_SMCR_TS_3)                                 /*!< Internal Trigger 5 (ITR5) is used as trigger input */
+#define LL_TIM_TS_ITR6                         (TIM_SMCR_TS_1 | TIM_SMCR_TS_3)                                 /*!< Internal Trigger 6 (ITR6) is used as trigger input */
+#define LL_TIM_TS_ITR7                         (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_3)                 /*!< Internal Trigger 7 (ITR7) is used as trigger input */
+#define LL_TIM_TS_ITR8                         (TIM_SMCR_TS_2 | TIM_SMCR_TS_3)                                 /*!< Internal Trigger 8 (ITR8) is used as trigger input */
+#define LL_TIM_TS_ITR9                         (TIM_SMCR_TS_0 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3)                 /*!< Internal Trigger 9 (ITR9) is used as trigger input */
+#define LL_TIM_TS_ITR10                        (TIM_SMCR_TS_1 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3)                 /*!< Internal Trigger 10 (ITR10) is used as trigger input */
+#define LL_TIM_TS_ITR11                        (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3) /*!< Internal Trigger 11 (ITR11) is used as trigger input */
+#define LL_TIM_TS_ITR12                        (TIM_SMCR_TS_4)                                                 /*!< Internal Trigger 12 (ITR12) is used as trigger input */
+#define LL_TIM_TS_ITR13                        (TIM_SMCR_TS_0 | TIM_SMCR_TS_4)                                 /*!< Internal Trigger 13 (ITR13) is used as trigger input */
+#define LL_TIM_TS_TI1F_ED                      TIM_SMCR_TS_2                                                   /*!< TI1 Edge Detector (TI1F_ED) is used as trigger input */
+#define LL_TIM_TS_TI1FP1                       (TIM_SMCR_TS_2 | TIM_SMCR_TS_0)                                 /*!< Filtered Timer Input 1 (TI1FP1) is used as trigger input */
+#define LL_TIM_TS_TI2FP2                       (TIM_SMCR_TS_2 | TIM_SMCR_TS_1)                                 /*!< Filtered Timer Input 2 (TI12P2) is used as trigger input */
+#define LL_TIM_TS_ETRF                         (TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0)                 /*!< Filtered external Trigger (ETRF) is used as trigger input */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_ETR_POLARITY External Trigger Polarity
+  * @{
+  */
+#define LL_TIM_ETR_POLARITY_NONINVERTED        0x00000000U             /*!< ETR is non-inverted, active at high level or rising edge */
+#define LL_TIM_ETR_POLARITY_INVERTED           TIM_SMCR_ETP            /*!< ETR is inverted, active at low level or falling edge */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_ETR_PRESCALER External Trigger Prescaler
+  * @{
+  */
+#define LL_TIM_ETR_PRESCALER_DIV1              0x00000000U             /*!< ETR prescaler OFF */
+#define LL_TIM_ETR_PRESCALER_DIV2              TIM_SMCR_ETPS_0         /*!< ETR frequency is divided by 2 */
+#define LL_TIM_ETR_PRESCALER_DIV4              TIM_SMCR_ETPS_1         /*!< ETR frequency is divided by 4 */
+#define LL_TIM_ETR_PRESCALER_DIV8              TIM_SMCR_ETPS           /*!< ETR frequency is divided by 8 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_ETR_FILTER External Trigger Filter
+  * @{
+  */
+#define LL_TIM_ETR_FILTER_FDIV1                0x00000000U                                          /*!< No filter, sampling is done at fDTS */
+#define LL_TIM_ETR_FILTER_FDIV1_N2             TIM_SMCR_ETF_0                                       /*!< fSAMPLING=fCK_INT, N=2 */
+#define LL_TIM_ETR_FILTER_FDIV1_N4             TIM_SMCR_ETF_1                                       /*!< fSAMPLING=fCK_INT, N=4 */
+#define LL_TIM_ETR_FILTER_FDIV1_N8             (TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)                    /*!< fSAMPLING=fCK_INT, N=8 */
+#define LL_TIM_ETR_FILTER_FDIV2_N6             TIM_SMCR_ETF_2                                       /*!< fSAMPLING=fDTS/2, N=6 */
+#define LL_TIM_ETR_FILTER_FDIV2_N8             (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0)                    /*!< fSAMPLING=fDTS/2, N=8 */
+#define LL_TIM_ETR_FILTER_FDIV4_N6             (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1)                    /*!< fSAMPLING=fDTS/4, N=6 */
+#define LL_TIM_ETR_FILTER_FDIV4_N8             (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)   /*!< fSAMPLING=fDTS/4, N=8 */
+#define LL_TIM_ETR_FILTER_FDIV8_N6             TIM_SMCR_ETF_3                                       /*!< fSAMPLING=fDTS/8, N=8 */
+#define LL_TIM_ETR_FILTER_FDIV8_N8             (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0)                    /*!< fSAMPLING=fDTS/16, N=5 */
+#define LL_TIM_ETR_FILTER_FDIV16_N5            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1)                    /*!< fSAMPLING=fDTS/16, N=6 */
+#define LL_TIM_ETR_FILTER_FDIV16_N6            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)   /*!< fSAMPLING=fDTS/16, N=8 */
+#define LL_TIM_ETR_FILTER_FDIV16_N8            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2)                    /*!< fSAMPLING=fDTS/16, N=5 */
+#define LL_TIM_ETR_FILTER_FDIV32_N5            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0)   /*!< fSAMPLING=fDTS/32, N=5 */
+#define LL_TIM_ETR_FILTER_FDIV32_N6            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1)   /*!< fSAMPLING=fDTS/32, N=6 */
+#define LL_TIM_ETR_FILTER_FDIV32_N8            TIM_SMCR_ETF                                         /*!< fSAMPLING=fDTS/32, N=8 */
+/**
+  * @}
+  */
+
+#define LL_TIM_TIM1_ETRSOURCE_GPIO        0x00000000U                                                 /*!< TIM1_ETR is connected to GPIO */
+#define LL_TIM_TIM1_ETRSOURCE_COMP1       TIM1_AF1_ETRSEL_0                                           /*!< TIM1_ETR is connected to COMP1 OUT */
+#define LL_TIM_TIM1_ETRSOURCE_COMP2       TIM1_AF1_ETRSEL_1                                           /*!< TIM1_ETR is connected to COMP2 OUT */
+#define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD1   (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0)                     /*!< TIM1_ETR is connected to ADC1 AWD1 */
+#define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD2   (TIM1_AF1_ETRSEL_2)                                         /*!< TIM1_ETR is connected to ADC1 AWD2 */
+#define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD3   (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0)                     /*!< TIM1_ETR is connected to ADC1 AWD3 */
+#define LL_TIM_TIM1_ETRSOURCE_ADC3_AWD1   (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1)                     /*!< TIM1_ETR is connected to ADC3 AWD1 */
+#define LL_TIM_TIM1_ETRSOURCE_ADC3_AWD2   (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< TIM1_ETR is connected to ADC3 AWD2 */
+#define LL_TIM_TIM1_ETRSOURCE_ADC3_AWD3   TIM1_AF1_ETRSEL_3                                           /*!< TIM1_ETR is connected to ADC3 AWD3 */
+
+#define LL_TIM_TIM8_ETRSOURCE_GPIO        0x00000000U                                                 /*!< TIM8_ETR is connected to GPIO */
+#define LL_TIM_TIM8_ETRSOURCE_COMP1       TIM8_AF1_ETRSEL_0                                           /*!< TIM8_ETR is connected to COMP1 OUT */
+#define LL_TIM_TIM8_ETRSOURCE_COMP2       TIM8_AF1_ETRSEL_1                                           /*!< TIM8_ETR is connected to COMP2 OUT */
+#define LL_TIM_TIM8_ETRSOURCE_ADC2_AWD1   (TIM8_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0)                     /*!< TIM8_ETR is connected to ADC2 AWD1 */
+#define LL_TIM_TIM8_ETRSOURCE_ADC2_AWD2   (TIM8_AF1_ETRSEL_2)                                         /*!< TIM8_ETR is connected to ADC2 AWD2 */
+#define LL_TIM_TIM8_ETRSOURCE_ADC2_AWD3   (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_0)                     /*!< TIM8_ETR is connected to ADC2 AWD3 */
+#define LL_TIM_TIM8_ETRSOURCE_ADC3_AWD1   (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_1)                     /*!< TIM8_ETR is connected to ADC3 AWD1 */
+#define LL_TIM_TIM8_ETRSOURCE_ADC3_AWD2   (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /*!< TIM8_ETR is connected to ADC3 AWD2 */
+#define LL_TIM_TIM8_ETRSOURCE_ADC3_AWD3   TIM8_AF1_ETRSEL_3                                           /*!< TIM8_ETR is connected to ADC3 AWD3 */
+
+#define LL_TIM_TIM2_ETRSOURCE_GPIO        0x00000000U                                                 /*!< TIM2_ETR is connected to GPIO */
+#define LL_TIM_TIM2_ETRSOURCE_COMP1       (TIM2_AF1_ETRSEL_0)                                         /*!< TIM2_ETR is connected to COMP1 OUT */
+#define LL_TIM_TIM2_ETRSOURCE_COMP2       (TIM2_AF1_ETRSEL_1)                                         /*!< TIM2_ETR is connected to COMP2 OUT */
+#define LL_TIM_TIM2_ETRSOURCE_RCC_LSE     (TIM2_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0)                     /*!< TIM2_ETR is connected to RCC LSE */
+#define LL_TIM_TIM2_ETRSOURCE_SAI1_FSA    TIM2_AF1_ETRSEL_2                                           /*!< TIM2_ETR is connected to SAI1 FS_A */
+#define LL_TIM_TIM2_ETRSOURCE_SAI1_FSB    (TIM2_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_0)                     /*!< TIM2_ETR is connected to SAI1 FS_B */
+
+#define LL_TIM_TIM3_ETRSOURCE_GPIO        0x00000000U                                                 /*!< TIM3_ETR is connected to GPIO */
+#define LL_TIM_TIM3_ETRSOURCE_COMP1       TIM3_AF1_ETRSEL_0                                           /*!< TIM3_ETR is connected to COMP1 OUT */
+
+#define LL_TIM_TIM5_ETRSOURCE_GPIO        0x00000000U                                                 /*!< TIM5_ETR is connected to GPIO */
+#define LL_TIM_TIM5_ETRSOURCE_SAI2_FSA    TIM5_AF1_ETRSEL_0                                           /*!< TIM5_ETR is connected to SAI2 FS_A */
+#define LL_TIM_TIM5_ETRSOURCE_SAI2_FSB    TIM5_AF1_ETRSEL_1                                           /*!< TIM5_ETR is connected to SAI2 FS_B */
+#define LL_TIM_TIM5_ETRSOURCE_SAI4_FSA    TIM5_AF1_ETRSEL_0                                           /*!< TIM5_ETR is connected to SAI4 FS_A */
+#define LL_TIM_TIM5_ETRSOURCE_SAI4_FSB    TIM5_AF1_ETRSEL_1                                           /*!< TIM5_ETR is connected to SAI4 FS_B */
+
+#define LL_TIM_TIM23_ETRSOURCE_GPIO       0x00000000U                                                 /*!< TIM23_ETR is connected to GPIO */
+#define LL_TIM_TIM23_ETRSOURCE_COMP1      (TIM2_AF1_ETRSEL_0)                                         /*!< TIM23_ETR is connected to COMP1 OUT */
+#define LL_TIM_TIM23_ETRSOURCE_COMP2      (TIM2_AF1_ETRSEL_1)                                         /*!< TIM23_ETR is connected to COMP2 OUT */
+
+#define LL_TIM_TIM24_ETRSOURCE_GPIO        0x00000000U                                                /*!< TIM24_ETR is connected to GPIO */
+#define LL_TIM_TIM24_ETRSOURCE_SAI4_FSA    TIM5_AF1_ETRSEL_0                                          /*!< TIM24_ETR is connected to SAI4 FS_A */
+#define LL_TIM_TIM24_ETRSOURCE_SAI4_FSB    TIM5_AF1_ETRSEL_1                                          /*!< TIM24_ETR is connected to SAI4 FS_B */
+#define LL_TIM_TIM24_ETRSOURCE_SAI1_FSA    (TIM2_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0)                    /*!< TIM24_ETR is connected to SAI1 FS_A */
+#define LL_TIM_TIM24_ETRSOURCE_SAI1_FSB    TIM2_AF1_ETRSEL_2                                          /*!< TIM24_ETR is connected to SAI1 FS_B */
+
+/** @defgroup TIM_LL_EC_BREAK_POLARITY break polarity
+  * @{
+  */
+#define LL_TIM_BREAK_POLARITY_LOW              0x00000000U               /*!< Break input BRK is active low */
+#define LL_TIM_BREAK_POLARITY_HIGH             TIM_BDTR_BKP              /*!< Break input BRK is active high */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_BREAK_FILTER break filter
+  * @{
+  */
+#define LL_TIM_BREAK_FILTER_FDIV1              0x00000000U   /*!< No filter, BRK acts asynchronously */
+#define LL_TIM_BREAK_FILTER_FDIV1_N2           0x00010000U   /*!< fSAMPLING=fCK_INT, N=2 */
+#define LL_TIM_BREAK_FILTER_FDIV1_N4           0x00020000U   /*!< fSAMPLING=fCK_INT, N=4 */
+#define LL_TIM_BREAK_FILTER_FDIV1_N8           0x00030000U   /*!< fSAMPLING=fCK_INT, N=8 */
+#define LL_TIM_BREAK_FILTER_FDIV2_N6           0x00040000U   /*!< fSAMPLING=fDTS/2, N=6 */
+#define LL_TIM_BREAK_FILTER_FDIV2_N8           0x00050000U   /*!< fSAMPLING=fDTS/2, N=8 */
+#define LL_TIM_BREAK_FILTER_FDIV4_N6           0x00060000U   /*!< fSAMPLING=fDTS/4, N=6 */
+#define LL_TIM_BREAK_FILTER_FDIV4_N8           0x00070000U   /*!< fSAMPLING=fDTS/4, N=8 */
+#define LL_TIM_BREAK_FILTER_FDIV8_N6           0x00080000U   /*!< fSAMPLING=fDTS/8, N=6 */
+#define LL_TIM_BREAK_FILTER_FDIV8_N8           0x00090000U   /*!< fSAMPLING=fDTS/8, N=8 */
+#define LL_TIM_BREAK_FILTER_FDIV16_N5          0x000A0000U   /*!< fSAMPLING=fDTS/16, N=5 */
+#define LL_TIM_BREAK_FILTER_FDIV16_N6          0x000B0000U   /*!< fSAMPLING=fDTS/16, N=6 */
+#define LL_TIM_BREAK_FILTER_FDIV16_N8          0x000C0000U   /*!< fSAMPLING=fDTS/16, N=8 */
+#define LL_TIM_BREAK_FILTER_FDIV32_N5          0x000D0000U   /*!< fSAMPLING=fDTS/32, N=5 */
+#define LL_TIM_BREAK_FILTER_FDIV32_N6          0x000E0000U   /*!< fSAMPLING=fDTS/32, N=6 */
+#define LL_TIM_BREAK_FILTER_FDIV32_N8          0x000F0000U   /*!< fSAMPLING=fDTS/32, N=8 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_BREAK2_POLARITY BREAK2 POLARITY
+  * @{
+  */
+#define LL_TIM_BREAK2_POLARITY_LOW             0x00000000U             /*!< Break input BRK2 is active low */
+#define LL_TIM_BREAK2_POLARITY_HIGH            TIM_BDTR_BK2P           /*!< Break input BRK2 is active high */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_BREAK2_FILTER BREAK2 FILTER
+  * @{
+  */
+#define LL_TIM_BREAK2_FILTER_FDIV1             0x00000000U   /*!< No filter, BRK acts asynchronously */
+#define LL_TIM_BREAK2_FILTER_FDIV1_N2          0x00100000U   /*!< fSAMPLING=fCK_INT, N=2 */
+#define LL_TIM_BREAK2_FILTER_FDIV1_N4          0x00200000U   /*!< fSAMPLING=fCK_INT, N=4 */
+#define LL_TIM_BREAK2_FILTER_FDIV1_N8          0x00300000U   /*!< fSAMPLING=fCK_INT, N=8 */
+#define LL_TIM_BREAK2_FILTER_FDIV2_N6          0x00400000U   /*!< fSAMPLING=fDTS/2, N=6 */
+#define LL_TIM_BREAK2_FILTER_FDIV2_N8          0x00500000U   /*!< fSAMPLING=fDTS/2, N=8 */
+#define LL_TIM_BREAK2_FILTER_FDIV4_N6          0x00600000U   /*!< fSAMPLING=fDTS/4, N=6 */
+#define LL_TIM_BREAK2_FILTER_FDIV4_N8          0x00700000U   /*!< fSAMPLING=fDTS/4, N=8 */
+#define LL_TIM_BREAK2_FILTER_FDIV8_N6          0x00800000U   /*!< fSAMPLING=fDTS/8, N=6 */
+#define LL_TIM_BREAK2_FILTER_FDIV8_N8          0x00900000U   /*!< fSAMPLING=fDTS/8, N=8 */
+#define LL_TIM_BREAK2_FILTER_FDIV16_N5         0x00A00000U   /*!< fSAMPLING=fDTS/16, N=5 */
+#define LL_TIM_BREAK2_FILTER_FDIV16_N6         0x00B00000U   /*!< fSAMPLING=fDTS/16, N=6 */
+#define LL_TIM_BREAK2_FILTER_FDIV16_N8         0x00C00000U   /*!< fSAMPLING=fDTS/16, N=8 */
+#define LL_TIM_BREAK2_FILTER_FDIV32_N5         0x00D00000U   /*!< fSAMPLING=fDTS/32, N=5 */
+#define LL_TIM_BREAK2_FILTER_FDIV32_N6         0x00E00000U   /*!< fSAMPLING=fDTS/32, N=6 */
+#define LL_TIM_BREAK2_FILTER_FDIV32_N8         0x00F00000U   /*!< fSAMPLING=fDTS/32, N=8 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_OSSI OSSI
+  * @{
+  */
+#define LL_TIM_OSSI_DISABLE                    0x00000000U             /*!< When inactive, OCx/OCxN outputs are disabled */
+#define LL_TIM_OSSI_ENABLE                     TIM_BDTR_OSSI           /*!< When inactive, OxC/OCxN outputs are first forced with their inactive level then forced to their idle level after the deadtime */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_OSSR OSSR
+  * @{
+  */
+#define LL_TIM_OSSR_DISABLE                    0x00000000U             /*!< When inactive, OCx/OCxN outputs are disabled */
+#define LL_TIM_OSSR_ENABLE                     TIM_BDTR_OSSR           /*!< When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 */
+/**
+  * @}
+  */
+
+#if   defined(TIM_BREAK_INPUT_SUPPORT)
+/** @defgroup TIM_LL_EC_BREAK_INPUT BREAK INPUT
+  * @{
+  */
+#define LL_TIM_BREAK_INPUT_BKIN                0x00000000U  /*!< TIMx_BKIN input */
+#define LL_TIM_BREAK_INPUT_BKIN2               0x00000004U  /*!< TIMx_BKIN2 input */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_BKIN_SOURCE BKIN SOURCE
+  * @{
+  */
+#define LL_TIM_BKIN_SOURCE_BKIN                TIM1_AF1_BKINE      /*!< BKIN input from AF controller */
+#define LL_TIM_BKIN_SOURCE_BKCOMP1             TIM1_AF1_BKCMP1E    /*!< internal signal: COMP1 output */
+#define LL_TIM_BKIN_SOURCE_BKCOMP2             TIM1_AF1_BKCMP2E    /*!< internal signal: COMP2 output */
+#define LL_TIM_BKIN_SOURCE_DF1BK               TIM1_AF1_BKDF1BK0E  /*!< internal signal: DFSDM1 break output */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_BKIN_POLARITY BKIN POLARITY
+  * @{
+  */
+#define LL_TIM_BKIN_POLARITY_LOW               TIM1_AF1_BKINP           /*!< BRK BKIN input is active low */
+#define LL_TIM_BKIN_POLARITY_HIGH              0x00000000U              /*!< BRK BKIN input is active high */
+/**
+  * @}
+  */
+#endif /* TIM_BREAK_INPUT_SUPPORT */
+
+#if defined(TIM_BDTR_BKBID)
+/** @defgroup TIM_LL_EC_BREAK_AFMODE BREAK AF MODE
+  * @{
+  */
+#define LL_TIM_BREAK_AFMODE_INPUT              0x00000000U              /*!< Break input BRK in input mode */
+#define LL_TIM_BREAK_AFMODE_BIDIRECTIONAL      TIM_BDTR_BKBID           /*!< Break input BRK in bidirectional mode */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_BREAK2_AFMODE BREAK2 AF MODE
+  * @{
+  */
+#define LL_TIM_BREAK2_AFMODE_INPUT             0x00000000U             /*!< Break2 input BRK2 in input mode */
+#define LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL     TIM_BDTR_BK2BID         /*!< Break2 input BRK2 in bidirectional mode */
+/**
+  * @}
+  */
+
+#endif /*TIM_BDTR_BKBID */
+/** @defgroup TIM_LL_EC_DMABURST_BASEADDR DMA Burst Base Address
+  * @{
+  */
+#define LL_TIM_DMABURST_BASEADDR_CR1           0x00000000U                                                      /*!< TIMx_CR1 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CR2           TIM_DCR_DBA_0                                                    /*!< TIMx_CR2 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_SMCR          TIM_DCR_DBA_1                                                    /*!< TIMx_SMCR register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_DIER          (TIM_DCR_DBA_1 |  TIM_DCR_DBA_0)                                 /*!< TIMx_DIER register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_SR            TIM_DCR_DBA_2                                                    /*!< TIMx_SR register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_EGR           (TIM_DCR_DBA_2 | TIM_DCR_DBA_0)                                  /*!< TIMx_EGR register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CCMR1         (TIM_DCR_DBA_2 | TIM_DCR_DBA_1)                                  /*!< TIMx_CCMR1 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CCMR2         (TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)                  /*!< TIMx_CCMR2 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CCER          TIM_DCR_DBA_3                                                    /*!< TIMx_CCER register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CNT           (TIM_DCR_DBA_3 | TIM_DCR_DBA_0)                                  /*!< TIMx_CNT register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_PSC           (TIM_DCR_DBA_3 | TIM_DCR_DBA_1)                                  /*!< TIMx_PSC register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_ARR           (TIM_DCR_DBA_3 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)                  /*!< TIMx_ARR register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_RCR           (TIM_DCR_DBA_3 | TIM_DCR_DBA_2)                                  /*!< TIMx_RCR register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CCR1          (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0)                  /*!< TIMx_CCR1 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CCR2          (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1)                  /*!< TIMx_CCR2 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CCR3          (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)  /*!< TIMx_CCR3 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CCR4          TIM_DCR_DBA_4                                                    /*!< TIMx_CCR4 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_BDTR          (TIM_DCR_DBA_4 | TIM_DCR_DBA_0)                                  /*!< TIMx_BDTR register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CCMR3         (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0)                  /*!< TIMx_CCMR3 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CCR5          (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1)                  /*!< TIMx_CCR5 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CCR6          (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)  /*!< TIMx_CCR6 register is the DMA base address for DMA burst */
+#if defined(TIM1_AF1_BKINE)&&defined(TIM1_AF2_BKINE)
+#define LL_TIM_DMABURST_BASEADDR_AF1           (TIM_DCR_DBA_4 | TIM_DCR_DBA_3)                                  /*!< TIMx_AF1 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_AF2           (TIM_DCR_DBA_4 | TIM_DCR_DBA_3 | TIM_DCR_DBA_0)                  /*!< TIMx_AF2 register is the DMA base address for DMA burst */
+#endif /* TIM1_AF1_BKINE && TIM1_AF2_BKINE */
+#define LL_TIM_DMABURST_BASEADDR_TISEL         (TIM_DCR_DBA_4 | TIM_DCR_DBA_3 | TIM_DCR_DBA_1)                  /*!< TIMx_TISEL register is the DMA base address for DMA burst */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_DMABURST_LENGTH DMA Burst Length
+  * @{
+  */
+#define LL_TIM_DMABURST_LENGTH_1TRANSFER       0x00000000U                                                     /*!< Transfer is done to 1 register starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_2TRANSFERS      TIM_DCR_DBL_0                                                   /*!< Transfer is done to 2 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_3TRANSFERS      TIM_DCR_DBL_1                                                   /*!< Transfer is done to 3 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_4TRANSFERS      (TIM_DCR_DBL_1 |  TIM_DCR_DBL_0)                                /*!< Transfer is done to 4 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_5TRANSFERS      TIM_DCR_DBL_2                                                   /*!< Transfer is done to 5 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_6TRANSFERS      (TIM_DCR_DBL_2 | TIM_DCR_DBL_0)                                 /*!< Transfer is done to 6 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_7TRANSFERS      (TIM_DCR_DBL_2 | TIM_DCR_DBL_1)                                 /*!< Transfer is done to 7 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_8TRANSFERS      (TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0)                 /*!< Transfer is done to 1 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_9TRANSFERS      TIM_DCR_DBL_3                                                   /*!< Transfer is done to 9 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_10TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_0)                                 /*!< Transfer is done to 10 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_11TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_1)                                 /*!< Transfer is done to 11 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_12TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0)                 /*!< Transfer is done to 12 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_13TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_2)                                 /*!< Transfer is done to 13 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_14TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0)                 /*!< Transfer is done to 14 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_15TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1)                 /*!< Transfer is done to 15 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_16TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 16 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_17TRANSFERS     TIM_DCR_DBL_4                                                   /*!< Transfer is done to 17 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_18TRANSFERS     (TIM_DCR_DBL_4 |  TIM_DCR_DBL_0)                                /*!< Transfer is done to 18 registers starting from the DMA burst base address */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_TIM1_TI1_RMP  TIM1 Timer Input Ch1 Remap
+  * @{
+  */
+#define LL_TIM_TIM1_TI1_RMP_GPIO                          0x00000000U                               /*!< TIM1 input 1 is connected to GPIO */
+#define LL_TIM_TIM1_TI1_RMP_COMP1                         TIM_TISEL_TI1SEL_0                        /*!< TIM1 input 1 is connected to COMP1 OUT */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_TIM8_TI1_RMP  TIM8 Timer Input Ch1 Remap
+  * @{
+  */
+#define LL_TIM_TIM8_TI1_RMP_GPIO                          0x00000000U                               /*!< TIM8 input 1 is connected to GPIO */
+#define LL_TIM_TIM8_TI1_RMP_COMP2                         TIM_TISEL_TI1SEL_0                        /*!< TIM8 input 1 is connected to COMP2 OUT */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_TIM2_TI4_RMP  TIM2 Timer Input Ch4 Remap
+  * @{
+  */
+#define LL_TIM_TIM2_TI4_RMP_GPIO                          0x00000000U                               /*!< TIM2 input 4 is connected to GPIO */
+#define LL_TIM_TIM2_TI4_RMP_COMP1                         TIM_TISEL_TI4SEL_0                        /*!< TIM2 input 4 is connected to COMP1 OUT */
+#define LL_TIM_TIM2_TI4_RMP_COMP2                         TIM_TISEL_TI4SEL_1                        /*!< TIM2 input 4 is connected to COMP2 OUT */
+#define LL_TIM_TIM2_TI4_RMP_COMP1_COMP2                   (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1) /*!< TIM2 input 4 is connected to COMP2 OUT OR COMP2 OUT */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_TIM3_TI1_RMP  TIM3 Timer Input Ch1 Remap
+  * @{
+  */
+#define LL_TIM_TIM3_TI1_RMP_GPIO                          0x00000000U                               /*!< TIM3 input 1 is connected to GPIO */
+#define LL_TIM_TIM3_TI1_RMP_COMP1                         TIM_TISEL_TI1SEL_0                        /*!< TIM3 input 1 is connected to COMP1 OUT */
+#define LL_TIM_TIM3_TI1_RMP_COMP2                         TIM_TISEL_TI1SEL_1                        /*!< TIM3 input 1 is connected to COMP2 OUT */
+#define LL_TIM_TIM3_TI1_RMP_COMP1_COMP2                   (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /*!< TIM3 input 1 is connected to COMP1 OUT or COMP2 OUT */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_TIM5_TI1_RMP  TIM5 Timer Input Ch1 Remap
+  * @{
+  */
+#define LL_TIM_TIM5_TI1_RMP_GPIO                          0x00000000U                               /*!< TIM5 input 1 is connected to GPIO */
+#define LL_TIM_TIM5_TI1_RMP_CAN_TMP                       TIM_TISEL_TI1SEL_0                        /*!< TIM5 input 1 is connected to CAN TMP */
+#define LL_TIM_TIM5_TI1_RMP_CAN_RTP                       TIM_TISEL_TI1SEL_1                        /*!< TIM5 input 1 is connected to CAN RTP */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_TIM12_TI1_RMP  TIM12 Timer Input Ch1 Remap
+  * @{
+  */
+#define LL_TIM_TIM12_TI1_RMP_GPIO                         0x00000000U                               /*!< TIM12 input 1 is connected to GPIO */
+#define LL_TIM_TIM12_TI1_RMP_SPDIF_FS                     TIM_TISEL_TI1SEL_0                        /*!< TIM12 input 1 is connected to SPDIF FS */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_TIM15_TI1_RMP  TIM15 Timer Input Ch1 Remap
+  * @{
+  */
+#define LL_TIM_TIM15_TI1_RMP_GPIO                         0x00000000U                               /*!< TIM15 input 1 is connected to GPIO */
+#define LL_TIM_TIM15_TI1_RMP_TIM2_CH1                     TIM_TISEL_TI1SEL_0                        /*!< TIM15 input 1 is connected to TIM2 CH1 */
+#define LL_TIM_TIM15_TI1_RMP_TIM3_CH1                     TIM_TISEL_TI1SEL_1                        /*!< TIM15 input 1 is connected to TIM3 CH1 */
+#define LL_TIM_TIM15_TI1_RMP_TIM4_CH1                     (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /*!< TIM15 input 1 is connected to TIM4 CH1 */
+#define LL_TIM_TIM15_TI1_RMP_RCC_LSE                      (TIM_TISEL_TI1SEL_2)                      /*!< TIM15 input 1 is connected to RCC LSE  */
+#define LL_TIM_TIM15_TI1_RMP_RCC_CSI                      (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0) /*!< TIM15 input 1 is connected to RCC CSI  */
+#define LL_TIM_TIM15_TI1_RMP_RCC_MCO2                     (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1) /*!< TIM15 input 1 is connected to RCC MCO2 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_TIM15_TI2_RMP  TIM15 Timer Input Ch2 Remap
+  * @{
+  */
+#define LL_TIM_TIM15_TI2_RMP_GPIO                         0x00000000U                               /*!< TIM15 input 2 is connected to GPIO */
+#define LL_TIM_TIM15_TI2_RMP_TIM2_CH2                     (TIM_TISEL_TI2SEL_0)                      /*!< TIM15 input 2 is connected to TIM2 CH2 */
+#define LL_TIM_TIM15_TI2_RMP_TIM3_CH2                     (TIM_TISEL_TI2SEL_1)                      /*!< TIM15 input 2 is connected to TIM3 CH2 */
+#define LL_TIM_TIM15_TI2_RMP_TIM4_CH2                     (TIM_TISEL_TI2SEL_0 | TIM_TISEL_TI2SEL_1) /*!< TIM15 input 2 is connected to TIM4 CH2 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_TIM16_TI1_RMP  TIM16 Timer Input Ch1 Remap
+  * @{
+  */
+#define LL_TIM_TIM16_TI1_RMP_GPIO                         0x00000000U                               /*!< TIM16 input 1 is connected to GPIO */
+#define LL_TIM_TIM16_TI1_RMP_RCC_LSI                      TIM_TISEL_TI1SEL_0                        /*!< TIM16 input 1 is connected to RCC LSI */
+#define LL_TIM_TIM16_TI1_RMP_RCC_LSE                      TIM_TISEL_TI1SEL_1                        /*!< TIM16 input 1 is connected to RCC LSE */
+#define LL_TIM_TIM16_TI1_RMP_WKUP_IT                      (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /*!< TIM16 input 1 is connected to WKUP_IT */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_TIM17_TI1_RMP  TIM17 Timer Input Ch1 Remap
+  * @{
+  */
+#define LL_TIM_TIM17_TI1_RMP_GPIO                         0x00000000U                               /*!< TIM17 input 1 is connected to GPIO */
+#define LL_TIM_TIM17_TI1_RMP_SPDIF_FS                     TIM_TISEL_TI1SEL_0                        /*!< TIM17 input 1 is connected to SPDIF FS */
+#define LL_TIM_TIM17_TI1_RMP_RCC_HSE1MHZ                  TIM_TISEL_TI1SEL_1                        /*!< TIM17 input 1 is connected to RCC HSE 1Mhz */
+#define LL_TIM_TIM17_TI1_RMP_RCC_MCO1                     (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /*!< TIM17 input 1 is connected to RCC MCO1 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_TIM23_TI4_RMP  TIM23 Timer Input Ch4 Remap
+  * @{
+  */
+#define LL_TIM_TIM23_TI4_RMP_GPIO                         0x00000000U                               /*!< TIM23 input 4 is connected to GPIO */
+#define LL_TIM_TIM23_TI4_RMP_COMP1                        TIM_TISEL_TI4SEL_0                        /*!< TIM23 input 4 is connected to COMP1 OUT */
+#define LL_TIM_TIM23_TI4_RMP_COMP2                        TIM_TISEL_TI4SEL_1                        /*!< TIM23 input 4 is connected to COMP2 OUT */
+#define LL_TIM_TIM23_TI4_RMP_COMP1_COMP2                  (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1) /*!< TIM23 input 4 is connected to COMP1 OUT or COMP2 OUT */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_TIM24_TI1_RMP  TIM24 Timer Input Ch1 Remap
+  * @{
+  */
+#define LL_TIM_TIM24_TI1_RMP_GPIO                         0x00000000U                               /*!< TIM24 input 1 is connected to GPIO */
+#define LL_TIM_TIM24_TI1_RMP_CAN_TMP                      TIM_TISEL_TI1SEL_0                        /*!< TIM24 input 1 is connected to CAN TMP  */
+#define LL_TIM_TIM24_TI1_RMP_CAN_RTP                      TIM_TISEL_TI1SEL_1                        /*!< TIM24 input 1 is connected to CAN RTP  */
+#define LL_TIM_TIM24_TI1_RMP_CAN_SOC                      (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1) /*!< TIM24 input 1 is connected to CAN SOC */
+
+#if defined(TIM_BREAK_INPUT_SUPPORT)
+/** Legacy definitions for compatibility purpose
+@cond 0
+  */
+#define LL_TIM_BKIN_SOURCE_DFBK  LL_TIM_BKIN_SOURCE_DF1BK
+/**
+@endcond
+  */
+#endif /* TIM_BREAK_INPUT_SUPPORT */
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup TIM_LL_Exported_Macros TIM Exported Macros
+  * @{
+  */
+
+/** @defgroup TIM_LL_EM_WRITE_READ Common Write and read registers Macros
+  * @{
+  */
+/**
+  * @brief  Write a value in TIM register.
+  * @param  __INSTANCE__ TIM Instance
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in TIM register.
+  * @param  __INSTANCE__ TIM Instance
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
+/**
+  * @}
+  */
+
+/**
+  * @brief  HELPER macro retrieving the UIFCPY flag from the counter value.
+  * @note ex: @ref __LL_TIM_GETFLAG_UIFCPY (@ref LL_TIM_GetCounter ());
+  * @note  Relevant only if UIF flag remapping has been enabled  (UIF status bit is copied
+  *        to TIMx_CNT register bit 31)
+  * @param  __CNT__ Counter value
+  * @retval UIF status bit
+  */
+#define __LL_TIM_GETFLAG_UIFCPY(__CNT__)  \
+  (READ_BIT((__CNT__), TIM_CNT_UIFCPY) >> TIM_CNT_UIFCPY_Pos)
+
+/**
+  * @brief  HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration.
+  * @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120);
+  * @param  __TIMCLK__ timer input clock frequency (in Hz)
+  * @param  __CKD__ This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV1
+  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV2
+  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV4
+  * @param  __DT__ deadtime duration (in ns)
+  * @retval DTG[0:7]
+  */
+#define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__)  \
+  ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__))))    ?  \
+    (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__)))  & DT_DELAY_1) :      \
+    (((uint64_t)((__DT__)*1000U)) < ((64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))))  ?  \
+    (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__),   \
+                                                 (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\
+    (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))))  ?  \
+    (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__),  \
+                                                 (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\
+    (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ?  \
+    (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__),  \
+                                                 (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\
+    0U)
+
+/**
+  * @brief  HELPER macro calculating the prescaler value to achieve the required counter clock frequency.
+  * @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000);
+  * @param  __TIMCLK__ timer input clock frequency (in Hz)
+  * @param  __CNTCLK__ counter clock frequency (in Hz)
+  * @retval Prescaler value  (between Min_Data=0 and Max_Data=65535)
+  */
+#define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__)   \
+  (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((((__TIMCLK__) + (__CNTCLK__)/2U)/(__CNTCLK__)) - 1U) : 0U)
+
+/**
+  * @brief  HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
+  * @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000);
+  * @param  __TIMCLK__ timer input clock frequency (in Hz)
+  * @param  __PSC__ prescaler
+  * @param  __FREQ__ output signal frequency (in Hz)
+  * @retval  Auto-reload value  (between Min_Data=0 and Max_Data=65535)
+  */
+#define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \
+  ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U)
+
+/**
+  * @brief  HELPER macro calculating the compare value required to achieve the required timer output compare
+  *         active/inactive delay.
+  * @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10);
+  * @param  __TIMCLK__ timer input clock frequency (in Hz)
+  * @param  __PSC__ prescaler
+  * @param  __DELAY__ timer output compare active/inactive delay (in us)
+  * @retval Compare value  (between Min_Data=0 and Max_Data=65535)
+  */
+#define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__)  \
+  ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \
+              / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
+
+/**
+  * @brief  HELPER macro calculating the auto-reload value to achieve the required pulse duration
+  *         (when the timer operates in one pulse mode).
+  * @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20);
+  * @param  __TIMCLK__ timer input clock frequency (in Hz)
+  * @param  __PSC__ prescaler
+  * @param  __DELAY__ timer output compare active/inactive delay (in us)
+  * @param  __PULSE__ pulse duration (in us)
+  * @retval Auto-reload value  (between Min_Data=0 and Max_Data=65535)
+  */
+#define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__)  \
+  ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \
+              + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__))))
+
+/**
+  * @brief  HELPER macro retrieving the ratio of the input capture prescaler
+  * @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ());
+  * @param  __ICPSC__ This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_ICPSC_DIV1
+  *         @arg @ref LL_TIM_ICPSC_DIV2
+  *         @arg @ref LL_TIM_ICPSC_DIV4
+  *         @arg @ref LL_TIM_ICPSC_DIV8
+  * @retval Input capture prescaler ratio (1, 2, 4 or 8)
+  */
+#define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__)  \
+  ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
+
+
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup TIM_LL_Exported_Functions TIM Exported Functions
+  * @{
+  */
+
+/** @defgroup TIM_LL_EF_Time_Base Time Base configuration
+  * @{
+  */
+/**
+  * @brief  Enable timer counter.
+  * @rmtoll CR1          CEN           LL_TIM_EnableCounter
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->CR1, TIM_CR1_CEN);
+}
+
+/**
+  * @brief  Disable timer counter.
+  * @rmtoll CR1          CEN           LL_TIM_DisableCounter
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN);
+}
+
+/**
+  * @brief  Indicates whether the timer counter is enabled.
+  * @rmtoll CR1          CEN           LL_TIM_IsEnabledCounter
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable update event generation.
+  * @rmtoll CR1          UDIS          LL_TIM_EnableUpdateEvent
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS);
+}
+
+/**
+  * @brief  Disable update event generation.
+  * @rmtoll CR1          UDIS          LL_TIM_DisableUpdateEvent
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->CR1, TIM_CR1_UDIS);
+}
+
+/**
+  * @brief  Indicates whether update event generation is enabled.
+  * @rmtoll CR1          UDIS          LL_TIM_IsEnabledUpdateEvent
+  * @param  TIMx Timer instance
+  * @retval Inverted state of bit (0 or 1).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (uint32_t)RESET) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set update event source
+  * @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events
+  *       generate an update interrupt or DMA request if enabled:
+  *        - Counter overflow/underflow
+  *        - Setting the UG bit
+  *        - Update generation through the slave mode controller
+  * @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter
+  *       overflow/underflow generates an update interrupt or DMA request if enabled.
+  * @rmtoll CR1          URS           LL_TIM_SetUpdateSource
+  * @param  TIMx Timer instance
+  * @param  UpdateSource This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_UPDATESOURCE_REGULAR
+  *         @arg @ref LL_TIM_UPDATESOURCE_COUNTER
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource)
+{
+  MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource);
+}
+
+/**
+  * @brief  Get actual event update source
+  * @rmtoll CR1          URS           LL_TIM_GetUpdateSource
+  * @param  TIMx Timer instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_UPDATESOURCE_REGULAR
+  *         @arg @ref LL_TIM_UPDATESOURCE_COUNTER
+  */
+__STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(const TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS));
+}
+
+/**
+  * @brief  Set one pulse mode (one shot v.s. repetitive).
+  * @rmtoll CR1          OPM           LL_TIM_SetOnePulseMode
+  * @param  TIMx Timer instance
+  * @param  OnePulseMode This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
+  *         @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode)
+{
+  MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode);
+}
+
+/**
+  * @brief  Get actual one pulse mode.
+  * @rmtoll CR1          OPM           LL_TIM_GetOnePulseMode
+  * @param  TIMx Timer instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
+  *         @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
+  */
+__STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(const TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM));
+}
+
+/**
+  * @brief  Set the timer counter counting mode.
+  * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
+  *       check whether or not the counter mode selection feature is supported
+  *       by a timer instance.
+  * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+  *       requires a timer reset to avoid unexpected direction
+  *       due to DIR bit readonly in center aligned mode.
+  * @rmtoll CR1          DIR           LL_TIM_SetCounterMode\n
+  *         CR1          CMS           LL_TIM_SetCounterMode
+  * @param  TIMx Timer instance
+  * @param  CounterMode This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_COUNTERMODE_UP
+  *         @arg @ref LL_TIM_COUNTERMODE_DOWN
+  *         @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
+  *         @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
+  *         @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode)
+{
+  MODIFY_REG(TIMx->CR1, (TIM_CR1_DIR | TIM_CR1_CMS), CounterMode);
+}
+
+/**
+  * @brief  Get actual counter mode.
+  * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
+  *       check whether or not the counter mode selection feature is supported
+  *       by a timer instance.
+  * @rmtoll CR1          DIR           LL_TIM_GetCounterMode\n
+  *         CR1          CMS           LL_TIM_GetCounterMode
+  * @param  TIMx Timer instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_COUNTERMODE_UP
+  *         @arg @ref LL_TIM_COUNTERMODE_DOWN
+  *         @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
+  *         @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
+  *         @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
+  */
+__STATIC_INLINE uint32_t LL_TIM_GetCounterMode(const TIM_TypeDef *TIMx)
+{
+  uint32_t counter_mode;
+
+  counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CMS));
+
+  if (counter_mode == 0U)
+  {
+    counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
+  }
+
+  return counter_mode;
+}
+
+/**
+  * @brief  Enable auto-reload (ARR) preload.
+  * @rmtoll CR1          ARPE          LL_TIM_EnableARRPreload
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->CR1, TIM_CR1_ARPE);
+}
+
+/**
+  * @brief  Disable auto-reload (ARR) preload.
+  * @rmtoll CR1          ARPE          LL_TIM_DisableARRPreload
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE);
+}
+
+/**
+  * @brief  Indicates whether auto-reload (ARR) preload is enabled.
+  * @rmtoll CR1          ARPE          LL_TIM_IsEnabledARRPreload
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set the division ratio between the timer clock  and the sampling clock used by the dead-time generators
+  *         (when supported) and the digital filters.
+  * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
+  *       whether or not the clock division feature is supported by the timer
+  *       instance.
+  * @rmtoll CR1          CKD           LL_TIM_SetClockDivision
+  * @param  TIMx Timer instance
+  * @param  ClockDivision This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV1
+  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV2
+  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV4
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision)
+{
+  MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision);
+}
+
+/**
+  * @brief  Get the actual division ratio between the timer clock  and the sampling clock used by the dead-time
+  *         generators (when supported) and the digital filters.
+  * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
+  *       whether or not the clock division feature is supported by the timer
+  *       instance.
+  * @rmtoll CR1          CKD           LL_TIM_GetClockDivision
+  * @param  TIMx Timer instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV1
+  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV2
+  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV4
+  */
+__STATIC_INLINE uint32_t LL_TIM_GetClockDivision(const TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD));
+}
+
+/**
+  * @brief  Set the counter value.
+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @rmtoll CNT          CNT           LL_TIM_SetCounter
+  * @param  TIMx Timer instance
+  * @param  Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter)
+{
+  WRITE_REG(TIMx->CNT, Counter);
+}
+
+/**
+  * @brief  Get the counter value.
+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @rmtoll CNT          CNT           LL_TIM_GetCounter
+  * @param  TIMx Timer instance
+  * @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
+  */
+__STATIC_INLINE uint32_t LL_TIM_GetCounter(const TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->CNT));
+}
+
+/**
+  * @brief  Get the current direction of the counter
+  * @rmtoll CR1          DIR           LL_TIM_GetDirection
+  * @param  TIMx Timer instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_COUNTERDIRECTION_UP
+  *         @arg @ref LL_TIM_COUNTERDIRECTION_DOWN
+  */
+__STATIC_INLINE uint32_t LL_TIM_GetDirection(const TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
+}
+
+/**
+  * @brief  Set the prescaler value.
+  * @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
+  * @note The prescaler can be changed on the fly as this control register is buffered. The new
+  *       prescaler ratio is taken into account at the next update event.
+  * @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter
+  * @rmtoll PSC          PSC           LL_TIM_SetPrescaler
+  * @param  TIMx Timer instance
+  * @param  Prescaler between Min_Data=0 and Max_Data=65535
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler)
+{
+  WRITE_REG(TIMx->PSC, Prescaler);
+}
+
+/**
+  * @brief  Get the prescaler value.
+  * @rmtoll PSC          PSC           LL_TIM_GetPrescaler
+  * @param  TIMx Timer instance
+  * @retval  Prescaler value between Min_Data=0 and Max_Data=65535
+  */
+__STATIC_INLINE uint32_t LL_TIM_GetPrescaler(const TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->PSC));
+}
+
+/**
+  * @brief  Set the auto-reload value.
+  * @note The counter is blocked while the auto-reload value is null.
+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter
+  * @rmtoll ARR          ARR           LL_TIM_SetAutoReload
+  * @param  TIMx Timer instance
+  * @param  AutoReload between Min_Data=0 and Max_Data=65535
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload)
+{
+  WRITE_REG(TIMx->ARR, AutoReload);
+}
+
+/**
+  * @brief  Get the auto-reload value.
+  * @rmtoll ARR          ARR           LL_TIM_GetAutoReload
+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @param  TIMx Timer instance
+  * @retval Auto-reload value
+  */
+__STATIC_INLINE uint32_t LL_TIM_GetAutoReload(const TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->ARR));
+}
+
+/**
+  * @brief  Set the repetition counter value.
+  * @note For advanced timer instances RepetitionCounter can be up to 65535.
+  * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a repetition counter.
+  * @rmtoll RCR          REP           LL_TIM_SetRepetitionCounter
+  * @param  TIMx Timer instance
+  * @param  RepetitionCounter between Min_Data=0 and Max_Data=255 or 65535 for advanced timer.
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter)
+{
+  WRITE_REG(TIMx->RCR, RepetitionCounter);
+}
+
+/**
+  * @brief  Get the repetition counter value.
+  * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a repetition counter.
+  * @rmtoll RCR          REP           LL_TIM_GetRepetitionCounter
+  * @param  TIMx Timer instance
+  * @retval Repetition counter value
+  */
+__STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(const TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->RCR));
+}
+
+/**
+  * @brief  Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31).
+  * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read
+  *       in an atomic way.
+  * @rmtoll CR1          UIFREMAP      LL_TIM_EnableUIFRemap
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableUIFRemap(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
+}
+
+/**
+  * @brief  Disable update interrupt flag (UIF) remapping.
+  * @rmtoll CR1          UIFREMAP      LL_TIM_DisableUIFRemap
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableUIFRemap(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
+}
+
+/**
+  * @brief  Indicate whether update interrupt flag (UIF) copy is set.
+  * @param  Counter Counter value
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveUIFCPY(const uint32_t Counter)
+{
+  return (((Counter & TIM_CNT_UIFCPY) == (TIM_CNT_UIFCPY)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration
+  * @{
+  */
+/**
+  * @brief  Enable  the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
+  * @note CCxE, CCxNE and OCxM bits are preloaded, after having been written,
+  *       they are updated only when a commutation event (COM) occurs.
+  * @note Only on channels that have a complementary output.
+  * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance is able to generate a commutation event.
+  * @rmtoll CR2          CCPC          LL_TIM_CC_EnablePreload
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->CR2, TIM_CR2_CCPC);
+}
+
+/**
+  * @brief  Disable  the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
+  * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance is able to generate a commutation event.
+  * @rmtoll CR2          CCPC          LL_TIM_CC_DisablePreload
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC);
+}
+
+/**
+  * @brief  Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
+  * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance is able to generate a commutation event.
+  * @rmtoll CR2          CCUS          LL_TIM_CC_SetUpdate
+  * @param  TIMx Timer instance
+  * @param  CCUpdateSource This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY
+  *         @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource)
+{
+  MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource);
+}
+
+/**
+  * @brief  Set the trigger of the capture/compare DMA request.
+  * @rmtoll CR2          CCDS          LL_TIM_CC_SetDMAReqTrigger
+  * @param  TIMx Timer instance
+  * @param  DMAReqTrigger This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CCDMAREQUEST_CC
+  *         @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger)
+{
+  MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger);
+}
+
+/**
+  * @brief  Get actual trigger of the capture/compare DMA request.
+  * @rmtoll CR2          CCDS          LL_TIM_CC_GetDMAReqTrigger
+  * @param  TIMx Timer instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_CCDMAREQUEST_CC
+  *         @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
+  */
+__STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(const TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS));
+}
+
+/**
+  * @brief  Set the lock level to freeze the
+  *         configuration of several capture/compare parameters.
+  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+  *       the lock mechanism is supported by a timer instance.
+  * @rmtoll BDTR         LOCK          LL_TIM_CC_SetLockLevel
+  * @param  TIMx Timer instance
+  * @param  LockLevel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_LOCKLEVEL_OFF
+  *         @arg @ref LL_TIM_LOCKLEVEL_1
+  *         @arg @ref LL_TIM_LOCKLEVEL_2
+  *         @arg @ref LL_TIM_LOCKLEVEL_3
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel)
+{
+  MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel);
+}
+
+/**
+  * @brief  Enable capture/compare channels.
+  * @rmtoll CCER         CC1E          LL_TIM_CC_EnableChannel\n
+  *         CCER         CC1NE         LL_TIM_CC_EnableChannel\n
+  *         CCER         CC2E          LL_TIM_CC_EnableChannel\n
+  *         CCER         CC2NE         LL_TIM_CC_EnableChannel\n
+  *         CCER         CC3E          LL_TIM_CC_EnableChannel\n
+  *         CCER         CC3NE         LL_TIM_CC_EnableChannel\n
+  *         CCER         CC4E          LL_TIM_CC_EnableChannel\n
+  *         CCER         CC5E          LL_TIM_CC_EnableChannel\n
+  *         CCER         CC6E          LL_TIM_CC_EnableChannel
+  * @param  TIMx Timer instance
+  * @param  Channels This parameter can be a combination of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH1N
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH2N
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH3N
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
+{
+  SET_BIT(TIMx->CCER, Channels);
+}
+
+/**
+  * @brief  Disable capture/compare channels.
+  * @rmtoll CCER         CC1E          LL_TIM_CC_DisableChannel\n
+  *         CCER         CC1NE         LL_TIM_CC_DisableChannel\n
+  *         CCER         CC2E          LL_TIM_CC_DisableChannel\n
+  *         CCER         CC2NE         LL_TIM_CC_DisableChannel\n
+  *         CCER         CC3E          LL_TIM_CC_DisableChannel\n
+  *         CCER         CC3NE         LL_TIM_CC_DisableChannel\n
+  *         CCER         CC4E          LL_TIM_CC_DisableChannel\n
+  *         CCER         CC5E          LL_TIM_CC_DisableChannel\n
+  *         CCER         CC6E          LL_TIM_CC_DisableChannel
+  * @param  TIMx Timer instance
+  * @param  Channels This parameter can be a combination of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH1N
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH2N
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH3N
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
+{
+  CLEAR_BIT(TIMx->CCER, Channels);
+}
+
+/**
+  * @brief  Indicate whether channel(s) is(are) enabled.
+  * @rmtoll CCER         CC1E          LL_TIM_CC_IsEnabledChannel\n
+  *         CCER         CC1NE         LL_TIM_CC_IsEnabledChannel\n
+  *         CCER         CC2E          LL_TIM_CC_IsEnabledChannel\n
+  *         CCER         CC2NE         LL_TIM_CC_IsEnabledChannel\n
+  *         CCER         CC3E          LL_TIM_CC_IsEnabledChannel\n
+  *         CCER         CC3NE         LL_TIM_CC_IsEnabledChannel\n
+  *         CCER         CC4E          LL_TIM_CC_IsEnabledChannel\n
+  *         CCER         CC5E          LL_TIM_CC_IsEnabledChannel\n
+  *         CCER         CC6E          LL_TIM_CC_IsEnabledChannel
+  * @param  TIMx Timer instance
+  * @param  Channels This parameter can be a combination of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH1N
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH2N
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH3N
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(TIM_TypeDef *TIMx, uint32_t Channels)
+{
+  return ((READ_BIT(TIMx->CCER, Channels) == (Channels)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EF_Output_Channel Output channel configuration
+  * @{
+  */
+/**
+  * @brief  Configure an output channel.
+  * @rmtoll CCMR1        CC1S          LL_TIM_OC_ConfigOutput\n
+  *         CCMR1        CC2S          LL_TIM_OC_ConfigOutput\n
+  *         CCMR2        CC3S          LL_TIM_OC_ConfigOutput\n
+  *         CCMR2        CC4S          LL_TIM_OC_ConfigOutput\n
+  *         CCMR3        CC5S          LL_TIM_OC_ConfigOutput\n
+  *         CCMR3        CC6S          LL_TIM_OC_ConfigOutput\n
+  *         CCER         CC1P          LL_TIM_OC_ConfigOutput\n
+  *         CCER         CC2P          LL_TIM_OC_ConfigOutput\n
+  *         CCER         CC3P          LL_TIM_OC_ConfigOutput\n
+  *         CCER         CC4P          LL_TIM_OC_ConfigOutput\n
+  *         CCER         CC5P          LL_TIM_OC_ConfigOutput\n
+  *         CCER         CC6P          LL_TIM_OC_ConfigOutput\n
+  *         CR2          OIS1          LL_TIM_OC_ConfigOutput\n
+  *         CR2          OIS2          LL_TIM_OC_ConfigOutput\n
+  *         CR2          OIS3          LL_TIM_OC_ConfigOutput\n
+  *         CR2          OIS4          LL_TIM_OC_ConfigOutput\n
+  *         CR2          OIS5          LL_TIM_OC_ConfigOutput\n
+  *         CR2          OIS6          LL_TIM_OC_ConfigOutput
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @param  Configuration This parameter must be a combination of all the following values:
+  *         @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW
+  *         @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel]));
+  MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),
+             (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]);
+  MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]),
+             (Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]);
+}
+
+/**
+  * @brief  Define the behavior of the output reference signal OCxREF from which
+  *         OCx and OCxN (when relevant) are derived.
+  * @rmtoll CCMR1        OC1M          LL_TIM_OC_SetMode\n
+  *         CCMR1        OC2M          LL_TIM_OC_SetMode\n
+  *         CCMR2        OC3M          LL_TIM_OC_SetMode\n
+  *         CCMR2        OC4M          LL_TIM_OC_SetMode\n
+  *         CCMR3        OC5M          LL_TIM_OC_SetMode\n
+  *         CCMR3        OC6M          LL_TIM_OC_SetMode
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @param  Mode This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_OCMODE_FROZEN
+  *         @arg @ref LL_TIM_OCMODE_ACTIVE
+  *         @arg @ref LL_TIM_OCMODE_INACTIVE
+  *         @arg @ref LL_TIM_OCMODE_TOGGLE
+  *         @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
+  *         @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
+  *         @arg @ref LL_TIM_OCMODE_PWM1
+  *         @arg @ref LL_TIM_OCMODE_PWM2
+  *         @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
+  *         @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
+  *         @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
+  *         @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
+  *         @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1
+  *         @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M  | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]);
+}
+
+/**
+  * @brief  Get the output compare mode of an output channel.
+  * @rmtoll CCMR1        OC1M          LL_TIM_OC_GetMode\n
+  *         CCMR1        OC2M          LL_TIM_OC_GetMode\n
+  *         CCMR2        OC3M          LL_TIM_OC_GetMode\n
+  *         CCMR2        OC4M          LL_TIM_OC_GetMode\n
+  *         CCMR3        OC5M          LL_TIM_OC_GetMode\n
+  *         CCMR3        OC6M          LL_TIM_OC_GetMode
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_OCMODE_FROZEN
+  *         @arg @ref LL_TIM_OCMODE_ACTIVE
+  *         @arg @ref LL_TIM_OCMODE_INACTIVE
+  *         @arg @ref LL_TIM_OCMODE_TOGGLE
+  *         @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
+  *         @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
+  *         @arg @ref LL_TIM_OCMODE_PWM1
+  *         @arg @ref LL_TIM_OCMODE_PWM2
+  *         @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
+  *         @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
+  *         @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
+  *         @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
+  *         @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1
+  *         @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2
+  */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetMode(const TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]);
+}
+
+/**
+  * @brief  Set the polarity of an output channel.
+  * @rmtoll CCER         CC1P          LL_TIM_OC_SetPolarity\n
+  *         CCER         CC1NP         LL_TIM_OC_SetPolarity\n
+  *         CCER         CC2P          LL_TIM_OC_SetPolarity\n
+  *         CCER         CC2NP         LL_TIM_OC_SetPolarity\n
+  *         CCER         CC3P          LL_TIM_OC_SetPolarity\n
+  *         CCER         CC3NP         LL_TIM_OC_SetPolarity\n
+  *         CCER         CC4P          LL_TIM_OC_SetPolarity\n
+  *         CCER         CC5P          LL_TIM_OC_SetPolarity\n
+  *         CCER         CC6P          LL_TIM_OC_SetPolarity
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH1N
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH2N
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH3N
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @param  Polarity This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_OCPOLARITY_HIGH
+  *         @arg @ref LL_TIM_OCPOLARITY_LOW
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),  Polarity << SHIFT_TAB_CCxP[iChannel]);
+}
+
+/**
+  * @brief  Get the polarity of an output channel.
+  * @rmtoll CCER         CC1P          LL_TIM_OC_GetPolarity\n
+  *         CCER         CC1NP         LL_TIM_OC_GetPolarity\n
+  *         CCER         CC2P          LL_TIM_OC_GetPolarity\n
+  *         CCER         CC2NP         LL_TIM_OC_GetPolarity\n
+  *         CCER         CC3P          LL_TIM_OC_GetPolarity\n
+  *         CCER         CC3NP         LL_TIM_OC_GetPolarity\n
+  *         CCER         CC4P          LL_TIM_OC_GetPolarity\n
+  *         CCER         CC5P          LL_TIM_OC_GetPolarity\n
+  *         CCER         CC6P          LL_TIM_OC_GetPolarity
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH1N
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH2N
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH3N
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_OCPOLARITY_HIGH
+  *         @arg @ref LL_TIM_OCPOLARITY_LOW
+  */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]);
+}
+
+/**
+  * @brief  Set the IDLE state of an output channel
+  * @note This function is significant only for the timer instances
+  *       supporting the break feature. Macro IS_TIM_BREAK_INSTANCE(TIMx)
+  *       can be used to check whether or not a timer instance provides
+  *       a break input.
+  * @rmtoll CR2         OIS1          LL_TIM_OC_SetIdleState\n
+  *         CR2         OIS2N         LL_TIM_OC_SetIdleState\n
+  *         CR2         OIS2          LL_TIM_OC_SetIdleState\n
+  *         CR2         OIS2N         LL_TIM_OC_SetIdleState\n
+  *         CR2         OIS3          LL_TIM_OC_SetIdleState\n
+  *         CR2         OIS3N         LL_TIM_OC_SetIdleState\n
+  *         CR2         OIS4          LL_TIM_OC_SetIdleState\n
+  *         CR2         OIS5          LL_TIM_OC_SetIdleState\n
+  *         CR2         OIS6          LL_TIM_OC_SetIdleState
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH1N
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH2N
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH3N
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @param  IdleState This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_OCIDLESTATE_LOW
+  *         @arg @ref LL_TIM_OCIDLESTATE_HIGH
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]),  IdleState << SHIFT_TAB_OISx[iChannel]);
+}
+
+/**
+  * @brief  Get the IDLE state of an output channel
+  * @rmtoll CR2         OIS1          LL_TIM_OC_GetIdleState\n
+  *         CR2         OIS2N         LL_TIM_OC_GetIdleState\n
+  *         CR2         OIS2          LL_TIM_OC_GetIdleState\n
+  *         CR2         OIS2N         LL_TIM_OC_GetIdleState\n
+  *         CR2         OIS3          LL_TIM_OC_GetIdleState\n
+  *         CR2         OIS3N         LL_TIM_OC_GetIdleState\n
+  *         CR2         OIS4          LL_TIM_OC_GetIdleState\n
+  *         CR2         OIS5          LL_TIM_OC_GetIdleState\n
+  *         CR2         OIS6          LL_TIM_OC_GetIdleState
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH1N
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH2N
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH3N
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_OCIDLESTATE_LOW
+  *         @arg @ref LL_TIM_OCIDLESTATE_HIGH
+  */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(const TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]);
+}
+
+/**
+  * @brief  Enable fast mode for the output channel.
+  * @note Acts only if the channel is configured in PWM1 or PWM2 mode.
+  * @rmtoll CCMR1        OC1FE          LL_TIM_OC_EnableFast\n
+  *         CCMR1        OC2FE          LL_TIM_OC_EnableFast\n
+  *         CCMR2        OC3FE          LL_TIM_OC_EnableFast\n
+  *         CCMR2        OC4FE          LL_TIM_OC_EnableFast\n
+  *         CCMR3        OC5FE          LL_TIM_OC_EnableFast\n
+  *         CCMR3        OC6FE          LL_TIM_OC_EnableFast
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
+
+}
+
+/**
+  * @brief  Disable fast mode for the output channel.
+  * @rmtoll CCMR1        OC1FE          LL_TIM_OC_DisableFast\n
+  *         CCMR1        OC2FE          LL_TIM_OC_DisableFast\n
+  *         CCMR2        OC3FE          LL_TIM_OC_DisableFast\n
+  *         CCMR2        OC4FE          LL_TIM_OC_DisableFast\n
+  *         CCMR3        OC5FE          LL_TIM_OC_DisableFast\n
+  *         CCMR3        OC6FE          LL_TIM_OC_DisableFast
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
+
+}
+
+/**
+  * @brief  Indicates whether fast mode is enabled for the output channel.
+  * @rmtoll CCMR1        OC1FE          LL_TIM_OC_IsEnabledFast\n
+  *         CCMR1        OC2FE          LL_TIM_OC_IsEnabledFast\n
+  *         CCMR2        OC3FE          LL_TIM_OC_IsEnabledFast\n
+  *         CCMR2        OC4FE          LL_TIM_OC_IsEnabledFast\n
+  *         CCMR3        OC5FE          LL_TIM_OC_IsEnabledFast\n
+  *         CCMR3        OC6FE          LL_TIM_OC_IsEnabledFast
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
+  return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable compare register (TIMx_CCRx) preload for the output channel.
+  * @rmtoll CCMR1        OC1PE          LL_TIM_OC_EnablePreload\n
+  *         CCMR1        OC2PE          LL_TIM_OC_EnablePreload\n
+  *         CCMR2        OC3PE          LL_TIM_OC_EnablePreload\n
+  *         CCMR2        OC4PE          LL_TIM_OC_EnablePreload\n
+  *         CCMR3        OC5PE          LL_TIM_OC_EnablePreload\n
+  *         CCMR3        OC6PE          LL_TIM_OC_EnablePreload
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
+}
+
+/**
+  * @brief  Disable compare register (TIMx_CCRx) preload for the output channel.
+  * @rmtoll CCMR1        OC1PE          LL_TIM_OC_DisablePreload\n
+  *         CCMR1        OC2PE          LL_TIM_OC_DisablePreload\n
+  *         CCMR2        OC3PE          LL_TIM_OC_DisablePreload\n
+  *         CCMR2        OC4PE          LL_TIM_OC_DisablePreload\n
+  *         CCMR3        OC5PE          LL_TIM_OC_DisablePreload\n
+  *         CCMR3        OC6PE          LL_TIM_OC_DisablePreload
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
+}
+
+/**
+  * @brief  Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel.
+  * @rmtoll CCMR1        OC1PE          LL_TIM_OC_IsEnabledPreload\n
+  *         CCMR1        OC2PE          LL_TIM_OC_IsEnabledPreload\n
+  *         CCMR2        OC3PE          LL_TIM_OC_IsEnabledPreload\n
+  *         CCMR2        OC4PE          LL_TIM_OC_IsEnabledPreload\n
+  *         CCMR3        OC5PE          LL_TIM_OC_IsEnabledPreload\n
+  *         CCMR3        OC6PE          LL_TIM_OC_IsEnabledPreload
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
+  return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable clearing the output channel on an external event.
+  * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
+  * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
+  *       or not a timer instance can clear the OCxREF signal on an external event.
+  * @rmtoll CCMR1        OC1CE          LL_TIM_OC_EnableClear\n
+  *         CCMR1        OC2CE          LL_TIM_OC_EnableClear\n
+  *         CCMR2        OC3CE          LL_TIM_OC_EnableClear\n
+  *         CCMR2        OC4CE          LL_TIM_OC_EnableClear\n
+  *         CCMR3        OC5CE          LL_TIM_OC_EnableClear\n
+  *         CCMR3        OC6CE          LL_TIM_OC_EnableClear
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
+}
+
+/**
+  * @brief  Disable clearing the output channel on an external event.
+  * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
+  *       or not a timer instance can clear the OCxREF signal on an external event.
+  * @rmtoll CCMR1        OC1CE          LL_TIM_OC_DisableClear\n
+  *         CCMR1        OC2CE          LL_TIM_OC_DisableClear\n
+  *         CCMR2        OC3CE          LL_TIM_OC_DisableClear\n
+  *         CCMR2        OC4CE          LL_TIM_OC_DisableClear\n
+  *         CCMR3        OC5CE          LL_TIM_OC_DisableClear\n
+  *         CCMR3        OC6CE          LL_TIM_OC_DisableClear
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
+}
+
+/**
+  * @brief  Indicates clearing the output channel on an external event is enabled for the output channel.
+  * @note This function enables clearing the output channel on an external event.
+  * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
+  * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
+  *       or not a timer instance can clear the OCxREF signal on an external event.
+  * @rmtoll CCMR1        OC1CE          LL_TIM_OC_IsEnabledClear\n
+  *         CCMR1        OC2CE          LL_TIM_OC_IsEnabledClear\n
+  *         CCMR2        OC3CE          LL_TIM_OC_IsEnabledClear\n
+  *         CCMR2        OC4CE          LL_TIM_OC_IsEnabledClear\n
+  *         CCMR3        OC5CE          LL_TIM_OC_IsEnabledClear\n
+  *         CCMR3        OC6CE          LL_TIM_OC_IsEnabledClear
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
+  return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of
+  *         the Ocx and OCxN signals).
+  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+  *       dead-time insertion feature is supported by a timer instance.
+  * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
+  * @rmtoll BDTR         DTG           LL_TIM_OC_SetDeadTime
+  * @param  TIMx Timer instance
+  * @param  DeadTime between Min_Data=0 and Max_Data=255
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime)
+{
+  MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime);
+}
+
+/**
+  * @brief  Set compare value for output channel 1 (TIMx_CCR1).
+  * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
+  *       output channel 1 is supported by a timer instance.
+  * @rmtoll CCR1         CCR1          LL_TIM_OC_SetCompareCH1
+  * @param  TIMx Timer instance
+  * @param  CompareValue between Min_Data=0 and Max_Data=65535
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue)
+{
+  WRITE_REG(TIMx->CCR1, CompareValue);
+}
+
+/**
+  * @brief  Set compare value for output channel 2 (TIMx_CCR2).
+  * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
+  *       output channel 2 is supported by a timer instance.
+  * @rmtoll CCR2         CCR2          LL_TIM_OC_SetCompareCH2
+  * @param  TIMx Timer instance
+  * @param  CompareValue between Min_Data=0 and Max_Data=65535
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue)
+{
+  WRITE_REG(TIMx->CCR2, CompareValue);
+}
+
+/**
+  * @brief  Set compare value for output channel 3 (TIMx_CCR3).
+  * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
+  *       output channel is supported by a timer instance.
+  * @rmtoll CCR3         CCR3          LL_TIM_OC_SetCompareCH3
+  * @param  TIMx Timer instance
+  * @param  CompareValue between Min_Data=0 and Max_Data=65535
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue)
+{
+  WRITE_REG(TIMx->CCR3, CompareValue);
+}
+
+/**
+  * @brief  Set compare value for output channel 4 (TIMx_CCR4).
+  * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
+  *       output channel 4 is supported by a timer instance.
+  * @rmtoll CCR4         CCR4          LL_TIM_OC_SetCompareCH4
+  * @param  TIMx Timer instance
+  * @param  CompareValue between Min_Data=0 and Max_Data=65535
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue)
+{
+  WRITE_REG(TIMx->CCR4, CompareValue);
+}
+
+/**
+  * @brief  Set compare value for output channel 5 (TIMx_CCR5).
+  * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
+  *       output channel 5 is supported by a timer instance.
+  * @rmtoll CCR5         CCR5          LL_TIM_OC_SetCompareCH5
+  * @param  TIMx Timer instance
+  * @param  CompareValue between Min_Data=0 and Max_Data=65535
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_SetCompareCH5(TIM_TypeDef *TIMx, uint32_t CompareValue)
+{
+  MODIFY_REG(TIMx->CCR5, TIM_CCR5_CCR5, CompareValue);
+}
+
+/**
+  * @brief  Set compare value for output channel 6 (TIMx_CCR6).
+  * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
+  *       output channel 6 is supported by a timer instance.
+  * @rmtoll CCR6         CCR6          LL_TIM_OC_SetCompareCH6
+  * @param  TIMx Timer instance
+  * @param  CompareValue between Min_Data=0 and Max_Data=65535
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_SetCompareCH6(TIM_TypeDef *TIMx, uint32_t CompareValue)
+{
+  WRITE_REG(TIMx->CCR6, CompareValue);
+}
+
+/**
+  * @brief  Get compare value (TIMx_CCR1) set for  output channel 1.
+  * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
+  *       output channel 1 is supported by a timer instance.
+  * @rmtoll CCR1         CCR1          LL_TIM_OC_GetCompareCH1
+  * @param  TIMx Timer instance
+  * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
+  */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(const TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->CCR1));
+}
+
+/**
+  * @brief  Get compare value (TIMx_CCR2) set for  output channel 2.
+  * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
+  *       output channel 2 is supported by a timer instance.
+  * @rmtoll CCR2         CCR2          LL_TIM_OC_GetCompareCH2
+  * @param  TIMx Timer instance
+  * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
+  */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(const TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->CCR2));
+}
+
+/**
+  * @brief  Get compare value (TIMx_CCR3) set for  output channel 3.
+  * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
+  *       output channel 3 is supported by a timer instance.
+  * @rmtoll CCR3         CCR3          LL_TIM_OC_GetCompareCH3
+  * @param  TIMx Timer instance
+  * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
+  */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(const TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->CCR3));
+}
+
+/**
+  * @brief  Get compare value (TIMx_CCR4) set for  output channel 4.
+  * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
+  *       output channel 4 is supported by a timer instance.
+  * @rmtoll CCR4         CCR4          LL_TIM_OC_GetCompareCH4
+  * @param  TIMx Timer instance
+  * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
+  */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(const TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->CCR4));
+}
+
+/**
+  * @brief  Get compare value (TIMx_CCR5) set for  output channel 5.
+  * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
+  *       output channel 5 is supported by a timer instance.
+  * @rmtoll CCR5         CCR5          LL_TIM_OC_GetCompareCH5
+  * @param  TIMx Timer instance
+  * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
+  */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5(const TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_BIT(TIMx->CCR5, TIM_CCR5_CCR5));
+}
+
+/**
+  * @brief  Get compare value (TIMx_CCR6) set for  output channel 6.
+  * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
+  *       output channel 6 is supported by a timer instance.
+  * @rmtoll CCR6         CCR6          LL_TIM_OC_GetCompareCH6
+  * @param  TIMx Timer instance
+  * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
+  */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH6(const TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->CCR6));
+}
+
+/**
+  * @brief  Select on which reference signal the OC5REF is combined to.
+  * @note Macro IS_TIM_COMBINED3PHASEPWM_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports the combined 3-phase PWM mode.
+  * @rmtoll CCR5         GC5C3          LL_TIM_SetCH5CombinedChannels\n
+  *         CCR5         GC5C2          LL_TIM_SetCH5CombinedChannels\n
+  *         CCR5         GC5C1          LL_TIM_SetCH5CombinedChannels
+  * @param  TIMx Timer instance
+  * @param  GroupCH5 This parameter can be a combination of the following values:
+  *         @arg @ref LL_TIM_GROUPCH5_NONE
+  *         @arg @ref LL_TIM_GROUPCH5_OC1REFC
+  *         @arg @ref LL_TIM_GROUPCH5_OC2REFC
+  *         @arg @ref LL_TIM_GROUPCH5_OC3REFC
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetCH5CombinedChannels(TIM_TypeDef *TIMx, uint32_t GroupCH5)
+{
+  MODIFY_REG(TIMx->CCR5, (TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1), GroupCH5);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EF_Input_Channel Input channel configuration
+  * @{
+  */
+/**
+  * @brief  Configure input channel.
+  * @rmtoll CCMR1        CC1S          LL_TIM_IC_Config\n
+  *         CCMR1        IC1PSC        LL_TIM_IC_Config\n
+  *         CCMR1        IC1F          LL_TIM_IC_Config\n
+  *         CCMR1        CC2S          LL_TIM_IC_Config\n
+  *         CCMR1        IC2PSC        LL_TIM_IC_Config\n
+  *         CCMR1        IC2F          LL_TIM_IC_Config\n
+  *         CCMR2        CC3S          LL_TIM_IC_Config\n
+  *         CCMR2        IC3PSC        LL_TIM_IC_Config\n
+  *         CCMR2        IC3F          LL_TIM_IC_Config\n
+  *         CCMR2        CC4S          LL_TIM_IC_Config\n
+  *         CCMR2        IC4PSC        LL_TIM_IC_Config\n
+  *         CCMR2        IC4F          LL_TIM_IC_Config\n
+  *         CCER         CC1P          LL_TIM_IC_Config\n
+  *         CCER         CC1NP         LL_TIM_IC_Config\n
+  *         CCER         CC2P          LL_TIM_IC_Config\n
+  *         CCER         CC2NP         LL_TIM_IC_Config\n
+  *         CCER         CC3P          LL_TIM_IC_Config\n
+  *         CCER         CC3NP         LL_TIM_IC_Config\n
+  *         CCER         CC4P          LL_TIM_IC_Config\n
+  *         CCER         CC4NP         LL_TIM_IC_Config
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @param  Configuration This parameter must be a combination of all the following values:
+  *         @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC
+  *         @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8
+  *         @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_IC_POLARITY_BOTHEDGE
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]),
+             ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S))                \
+             << SHIFT_TAB_ICxx[iChannel]);
+  MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
+             (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]);
+}
+
+/**
+  * @brief  Set the active input.
+  * @rmtoll CCMR1        CC1S          LL_TIM_IC_SetActiveInput\n
+  *         CCMR1        CC2S          LL_TIM_IC_SetActiveInput\n
+  *         CCMR2        CC3S          LL_TIM_IC_SetActiveInput\n
+  *         CCMR2        CC4S          LL_TIM_IC_SetActiveInput
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @param  ICActiveInput This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
+  *         @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
+  *         @arg @ref LL_TIM_ACTIVEINPUT_TRC
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]);
+}
+
+/**
+  * @brief  Get the current active input.
+  * @rmtoll CCMR1        CC1S          LL_TIM_IC_GetActiveInput\n
+  *         CCMR1        CC2S          LL_TIM_IC_GetActiveInput\n
+  *         CCMR2        CC3S          LL_TIM_IC_GetActiveInput\n
+  *         CCMR2        CC4S          LL_TIM_IC_GetActiveInput
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
+  *         @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
+  *         @arg @ref LL_TIM_ACTIVEINPUT_TRC
+  */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(const TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
+}
+
+/**
+  * @brief  Set the prescaler of input channel.
+  * @rmtoll CCMR1        IC1PSC        LL_TIM_IC_SetPrescaler\n
+  *         CCMR1        IC2PSC        LL_TIM_IC_SetPrescaler\n
+  *         CCMR2        IC3PSC        LL_TIM_IC_SetPrescaler\n
+  *         CCMR2        IC4PSC        LL_TIM_IC_SetPrescaler
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @param  ICPrescaler This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_ICPSC_DIV1
+  *         @arg @ref LL_TIM_ICPSC_DIV2
+  *         @arg @ref LL_TIM_ICPSC_DIV4
+  *         @arg @ref LL_TIM_ICPSC_DIV8
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]);
+}
+
+/**
+  * @brief  Get the current prescaler value acting on an  input channel.
+  * @rmtoll CCMR1        IC1PSC        LL_TIM_IC_GetPrescaler\n
+  *         CCMR1        IC2PSC        LL_TIM_IC_GetPrescaler\n
+  *         CCMR2        IC3PSC        LL_TIM_IC_GetPrescaler\n
+  *         CCMR2        IC4PSC        LL_TIM_IC_GetPrescaler
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_ICPSC_DIV1
+  *         @arg @ref LL_TIM_ICPSC_DIV2
+  *         @arg @ref LL_TIM_ICPSC_DIV4
+  *         @arg @ref LL_TIM_ICPSC_DIV8
+  */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(const TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
+}
+
+/**
+  * @brief  Set the input filter duration.
+  * @rmtoll CCMR1        IC1F          LL_TIM_IC_SetFilter\n
+  *         CCMR1        IC2F          LL_TIM_IC_SetFilter\n
+  *         CCMR2        IC3F          LL_TIM_IC_SetFilter\n
+  *         CCMR2        IC4F          LL_TIM_IC_SetFilter
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @param  ICFilter This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV1
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]);
+}
+
+/**
+  * @brief  Get the input filter duration.
+  * @rmtoll CCMR1        IC1F          LL_TIM_IC_GetFilter\n
+  *         CCMR1        IC2F          LL_TIM_IC_GetFilter\n
+  *         CCMR2        IC3F          LL_TIM_IC_GetFilter\n
+  *         CCMR2        IC4F          LL_TIM_IC_GetFilter
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV1
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
+  */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(const TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
+}
+
+/**
+  * @brief  Set the input channel polarity.
+  * @rmtoll CCER         CC1P          LL_TIM_IC_SetPolarity\n
+  *         CCER         CC1NP         LL_TIM_IC_SetPolarity\n
+  *         CCER         CC2P          LL_TIM_IC_SetPolarity\n
+  *         CCER         CC2NP         LL_TIM_IC_SetPolarity\n
+  *         CCER         CC3P          LL_TIM_IC_SetPolarity\n
+  *         CCER         CC3NP         LL_TIM_IC_SetPolarity\n
+  *         CCER         CC4P          LL_TIM_IC_SetPolarity\n
+  *         CCER         CC4NP         LL_TIM_IC_SetPolarity
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @param  ICPolarity This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_IC_POLARITY_RISING
+  *         @arg @ref LL_TIM_IC_POLARITY_FALLING
+  *         @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
+             ICPolarity << SHIFT_TAB_CCxP[iChannel]);
+}
+
+/**
+  * @brief  Get the current input channel polarity.
+  * @rmtoll CCER         CC1P          LL_TIM_IC_GetPolarity\n
+  *         CCER         CC1NP         LL_TIM_IC_GetPolarity\n
+  *         CCER         CC2P          LL_TIM_IC_GetPolarity\n
+  *         CCER         CC2NP         LL_TIM_IC_GetPolarity\n
+  *         CCER         CC3P          LL_TIM_IC_GetPolarity\n
+  *         CCER         CC3NP         LL_TIM_IC_GetPolarity\n
+  *         CCER         CC4P          LL_TIM_IC_GetPolarity\n
+  *         CCER         CC4NP         LL_TIM_IC_GetPolarity
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_IC_POLARITY_RISING
+  *         @arg @ref LL_TIM_IC_POLARITY_FALLING
+  *         @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
+  */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >>
+          SHIFT_TAB_CCxP[iChannel]);
+}
+
+/**
+  * @brief  Connect the TIMx_CH1, CH2 and CH3 pins  to the TI1 input (XOR combination).
+  * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides an XOR input.
+  * @rmtoll CR2          TI1S          LL_TIM_IC_EnableXORCombination
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->CR2, TIM_CR2_TI1S);
+}
+
+/**
+  * @brief  Disconnect the TIMx_CH1, CH2 and CH3 pins  from the TI1 input.
+  * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides an XOR input.
+  * @rmtoll CR2          TI1S          LL_TIM_IC_DisableXORCombination
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S);
+}
+
+/**
+  * @brief  Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.
+  * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
+  * a timer instance provides an XOR input.
+  * @rmtoll CR2          TI1S          LL_TIM_IC_IsEnabledXORCombination
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get captured value for input channel 1.
+  * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
+  *       input channel 1 is supported by a timer instance.
+  * @rmtoll CCR1         CCR1          LL_TIM_IC_GetCaptureCH1
+  * @param  TIMx Timer instance
+  * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
+  */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(const TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->CCR1));
+}
+
+/**
+  * @brief  Get captured value for input channel 2.
+  * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
+  *       input channel 2 is supported by a timer instance.
+  * @rmtoll CCR2         CCR2          LL_TIM_IC_GetCaptureCH2
+  * @param  TIMx Timer instance
+  * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
+  */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(const TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->CCR2));
+}
+
+/**
+  * @brief  Get captured value for input channel 3.
+  * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
+  *       input channel 3 is supported by a timer instance.
+  * @rmtoll CCR3         CCR3          LL_TIM_IC_GetCaptureCH3
+  * @param  TIMx Timer instance
+  * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
+  */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(const TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->CCR3));
+}
+
+/**
+  * @brief  Get captured value for input channel 4.
+  * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
+  *       input channel 4 is supported by a timer instance.
+  * @rmtoll CCR4         CCR4          LL_TIM_IC_GetCaptureCH4
+  * @param  TIMx Timer instance
+  * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
+  */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(const TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->CCR4));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection
+  * @{
+  */
+/**
+  * @brief  Enable external clock mode 2.
+  * @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal.
+  * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports external clock mode2.
+  * @rmtoll SMCR         ECE           LL_TIM_EnableExternalClock
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->SMCR, TIM_SMCR_ECE);
+}
+
+/**
+  * @brief  Disable external clock mode 2.
+  * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports external clock mode2.
+  * @rmtoll SMCR         ECE           LL_TIM_DisableExternalClock
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE);
+}
+
+/**
+  * @brief  Indicate whether external clock mode 2 is enabled.
+  * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports external clock mode2.
+  * @rmtoll SMCR         ECE           LL_TIM_IsEnabledExternalClock
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set the clock source of the counter clock.
+  * @note when selected clock source is external clock mode 1, the timer input
+  *       the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput()
+  *       function. This timer input must be configured by calling
+  *       the @ref LL_TIM_IC_Config() function.
+  * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports external clock mode1.
+  * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports external clock mode2.
+  * @rmtoll SMCR         SMS           LL_TIM_SetClockSource\n
+  *         SMCR         ECE           LL_TIM_SetClockSource
+  * @param  TIMx Timer instance
+  * @param  ClockSource This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL
+  *         @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1
+  *         @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource)
+{
+  MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS | TIM_SMCR_ECE, ClockSource);
+}
+
+/**
+  * @brief  Set the encoder interface mode.
+  * @note Macro IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports the encoder mode.
+  * @rmtoll SMCR         SMS           LL_TIM_SetEncoderMode
+  * @param  TIMx Timer instance
+  * @param  EncoderMode This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_ENCODERMODE_X2_TI1
+  *         @arg @ref LL_TIM_ENCODERMODE_X2_TI2
+  *         @arg @ref LL_TIM_ENCODERMODE_X4_TI12
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode)
+{
+  MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration
+  * @{
+  */
+/**
+  * @brief  Set the trigger output (TRGO) used for timer synchronization .
+  * @note Macro IS_TIM_MASTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance can operate as a master timer.
+  * @rmtoll CR2          MMS           LL_TIM_SetTriggerOutput
+  * @param  TIMx Timer instance
+  * @param  TimerSynchronization This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_TRGO_RESET
+  *         @arg @ref LL_TIM_TRGO_ENABLE
+  *         @arg @ref LL_TIM_TRGO_UPDATE
+  *         @arg @ref LL_TIM_TRGO_CC1IF
+  *         @arg @ref LL_TIM_TRGO_OC1REF
+  *         @arg @ref LL_TIM_TRGO_OC2REF
+  *         @arg @ref LL_TIM_TRGO_OC3REF
+  *         @arg @ref LL_TIM_TRGO_OC4REF
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization)
+{
+  MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization);
+}
+
+/**
+  * @brief  Set the trigger output 2 (TRGO2) used for ADC synchronization .
+  * @note Macro IS_TIM_TRGO2_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance can be used for ADC synchronization.
+  * @rmtoll CR2          MMS2          LL_TIM_SetTriggerOutput2
+  * @param  TIMx Timer Instance
+  * @param  ADCSynchronization This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_TRGO2_RESET
+  *         @arg @ref LL_TIM_TRGO2_ENABLE
+  *         @arg @ref LL_TIM_TRGO2_UPDATE
+  *         @arg @ref LL_TIM_TRGO2_CC1F
+  *         @arg @ref LL_TIM_TRGO2_OC1
+  *         @arg @ref LL_TIM_TRGO2_OC2
+  *         @arg @ref LL_TIM_TRGO2_OC3
+  *         @arg @ref LL_TIM_TRGO2_OC4
+  *         @arg @ref LL_TIM_TRGO2_OC5
+  *         @arg @ref LL_TIM_TRGO2_OC6
+  *         @arg @ref LL_TIM_TRGO2_OC4_RISINGFALLING
+  *         @arg @ref LL_TIM_TRGO2_OC6_RISINGFALLING
+  *         @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_RISING
+  *         @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_FALLING
+  *         @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_RISING
+  *         @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_FALLING
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetTriggerOutput2(TIM_TypeDef *TIMx, uint32_t ADCSynchronization)
+{
+  MODIFY_REG(TIMx->CR2, TIM_CR2_MMS2, ADCSynchronization);
+}
+
+/**
+  * @brief  Set the synchronization mode of a slave timer.
+  * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance can operate as a slave timer.
+  * @rmtoll SMCR         SMS           LL_TIM_SetSlaveMode
+  * @param  TIMx Timer instance
+  * @param  SlaveMode This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_SLAVEMODE_DISABLED
+  *         @arg @ref LL_TIM_SLAVEMODE_RESET
+  *         @arg @ref LL_TIM_SLAVEMODE_GATED
+  *         @arg @ref LL_TIM_SLAVEMODE_TRIGGER
+  *         @arg @ref LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode)
+{
+  MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode);
+}
+
+/**
+  * @brief  Set the selects the trigger input to be used to synchronize the counter.
+  * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance can operate as a slave timer.
+  * @rmtoll SMCR         TS            LL_TIM_SetTriggerInput
+  * @param  TIMx Timer instance
+  * @param  TriggerInput This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_TS_ITR0
+  *         @arg @ref LL_TIM_TS_ITR1
+  *         @arg @ref LL_TIM_TS_ITR2
+  *         @arg @ref LL_TIM_TS_ITR3
+  *         @arg @ref LL_TIM_TS_ITR4
+  *         @arg @ref LL_TIM_TS_ITR5
+  *         @arg @ref LL_TIM_TS_ITR6
+  *         @arg @ref LL_TIM_TS_ITR7
+  *         @arg @ref LL_TIM_TS_ITR8 (*)
+  *         @arg @ref LL_TIM_TS_ITR9 (*)
+  *         @arg @ref LL_TIM_TS_ITR10 (*)
+  *         @arg @ref LL_TIM_TS_ITR11 (*)
+  *         @arg @ref LL_TIM_TS_ITR12 (*)
+  *         @arg @ref LL_TIM_TS_ITR13 (*)
+  *         @arg @ref LL_TIM_TS_TI1F_ED
+  *         @arg @ref LL_TIM_TS_TI1FP1
+  *         @arg @ref LL_TIM_TS_TI2FP2
+  *         @arg @ref LL_TIM_TS_ETRF
+  *
+  *      (*)  Value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput)
+{
+  MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput);
+}
+
+/**
+  * @brief  Enable the Master/Slave mode.
+  * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance can operate as a slave timer.
+  * @rmtoll SMCR         MSM           LL_TIM_EnableMasterSlaveMode
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->SMCR, TIM_SMCR_MSM);
+}
+
+/**
+  * @brief  Disable the Master/Slave mode.
+  * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance can operate as a slave timer.
+  * @rmtoll SMCR         MSM           LL_TIM_DisableMasterSlaveMode
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM);
+}
+
+/**
+  * @brief Indicates whether the Master/Slave mode is enabled.
+  * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
+  * a timer instance can operate as a slave timer.
+  * @rmtoll SMCR         MSM           LL_TIM_IsEnabledMasterSlaveMode
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Configure the external trigger (ETR) input.
+  * @note Macro IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides an external trigger input.
+  * @rmtoll SMCR         ETP           LL_TIM_ConfigETR\n
+  *         SMCR         ETPS          LL_TIM_ConfigETR\n
+  *         SMCR         ETF           LL_TIM_ConfigETR
+  * @param  TIMx Timer instance
+  * @param  ETRPolarity This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED
+  *         @arg @ref LL_TIM_ETR_POLARITY_INVERTED
+  * @param  ETRPrescaler This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_ETR_PRESCALER_DIV1
+  *         @arg @ref LL_TIM_ETR_PRESCALER_DIV2
+  *         @arg @ref LL_TIM_ETR_PRESCALER_DIV4
+  *         @arg @ref LL_TIM_ETR_PRESCALER_DIV8
+  * @param  ETRFilter This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV1
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler,
+                                      uint32_t ETRFilter)
+{
+  MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP | TIM_SMCR_ETPS | TIM_SMCR_ETF, ETRPolarity | ETRPrescaler | ETRFilter);
+}
+
+/**
+  * @brief  Select the external trigger (ETR) input source.
+  * @note Macro IS_TIM_ETRSEL_INSTANCE(TIMx) can be used to check whether or
+  *       not a timer instance supports ETR source selection.
+  * @rmtoll AF1          ETRSEL        LL_TIM_SetETRSource
+  * @param  TIMx Timer instance
+  * @param  ETRSource This parameter can be one of the following values:
+  *      For TIM1, the parameter is one of the following values:
+  *         @arg LL_TIM_TIM1_ETRSOURCE_GPIO:               TIM1_ETR is connected to GPIO
+  *         @arg LL_TIM_TIM1_ETRSOURCE_COMP1:              TIM1_ETR is connected to COMP1 output
+  *         @arg LL_TIM_TIM1_ETRSOURCE_COMP2:              TIM1_ETR is connected to COMP2 output
+  *         @arg LL_TIM_TIM1_ETRSOURCE_ADC1_AWD1:          TIM1_ETR is connected to ADC1 AWD1
+  *         @arg LL_TIM_TIM1_ETRSOURCE_ADC1_AWD2:          TIM1_ETR is connected to ADC1 AWD2
+  *         @arg LL_TIM_TIM1_ETRSOURCE_ADC1_AWD3:          TIM1_ETR is connected to ADC1 AWD3
+  *         @arg LL_TIM_TIM1_ETRSOURCE_ADC3_AWD1:          TIM1_ETR is connected to ADC3 AWD1
+  *         @arg LL_TIM_TIM1_ETRSOURCE_ADC3_AWD2:          TIM1_ETR is connected to ADC3 AWD2
+  *         @arg LL_TIM_TIM1_ETRSOURCE_ADC3_AWD3:          TIM1_ETR is connected to ADC3 AWD3
+  *
+  *      For TIM2, the parameter is one of the following values:
+  *         @arg LL_TIM_TIM2_ETRSOURCE_GPIO:               TIM2_ETR is connected to GPIO
+  *         @arg LL_TIM_TIM2_ETRSOURCE_COMP1:              TIM2_ETR is connected to COMP1 output
+  *         @arg LL_TIM_TIM2_ETRSOURCE_COMP2:              TIM2_ETR is connected to COMP2 output
+  *         @arg LL_TIM_TIM2_ETRSOURCE_LSE:                TIM2_ETR is connected to LSE
+  *         @arg LL_TIM_TIM2_ETRSOURCE_SAI1_FSA:           TIM2_ETR is connected to SAI1 FS_A
+  *         @arg LL_TIM_TIM2_ETRSOURCE_SAI1_FSB:           TIM2_ETR is connected to SAI1 FS_B
+  *
+  *      For TIM3, the parameter is one of the following values:
+  *         @arg LL_TIM_TIM3_ETRSOURCE_GPIO:               TIM3_ETR is connected to GPIO
+  *         @arg LL_TIM_TIM3_ETRSOURCE_COMP1:              TIM3_ETR is connected to COMP1 output
+  *
+  *      For TIM5, the parameter is one of the following values:
+  *         @arg LL_TIM_TIM5_ETRSOURCE_GPIO:               TIM5_ETR is connected to GPIO
+  *         @arg LL_TIM_TIM5_ETRSOURCE_SAI2_FSA:           TIM5_ETR is connected to SAI2 FS_A (*)
+  *         @arg LL_TIM_TIM5_ETRSOURCE_SAI2_FSB:           TIM5_ETR is connected to SAI2 FS_B (*)
+  *         @arg LL_TIM_TIM5_ETRSOURCE_SAI4_FSA:           TIM5_ETR is connected to SAI2 FS_A (*)
+  *         @arg LL_TIM_TIM5_ETRSOURCE_SAI4_FSB:           TIM5_ETR is connected to SAI2 FS_B (*)
+  *
+  *      For TIM8, the parameter is one of the following values:
+  *         @arg LL_TIM_TIM8_ETRSOURCE_GPIO:               TIM8_ETR is connected to GPIO
+  *         @arg LL_TIM_TIM8_ETRSOURCE_COMP1:              TIM8_ETR is connected to COMP1 output
+  *         @arg LL_TIM_TIM8_ETRSOURCE_COMP2:              TIM8_ETR is connected to COMP2 output
+  *         @arg LL_TIM_TIM8_ETRSOURCE_ADC2_AWD1:          TIM8_ETR is connected to ADC2 AWD1
+  *         @arg LL_TIM_TIM8_ETRSOURCE_ADC2_AWD2:          TIM8_ETR is connected to ADC2 AWD2
+  *         @arg LL_TIM_TIM8_ETRSOURCE_ADC2_AWD3:          TIM8_ETR is connected to ADC2 AWD3
+  *         @arg LL_TIM_TIM8_ETRSOURCE_ADC3_AWD1:          TIM8_ETR is connected to ADC3 AWD1
+  *         @arg LL_TIM_TIM8_ETRSOURCE_ADC3_AWD2:          TIM8_ETR is connected to ADC3 AWD2
+  *         @arg LL_TIM_TIM8_ETRSOURCE_ADC3_AWD3:          TIM8_ETR is connected to ADC3 AWD3
+  *
+  *      For TIM23, the parameter is one of the following values: (*)
+  *         @arg LL_TIM_TIM23_ETRSOURCE_GPIO               TIM23_ETR is connected to GPIO
+  *         @arg LL_TIM_TIM23_ETRSOURCE_COMP1              TIM23_ETR is connected to COMP1 output
+  *         @arg LL_TIM_TIM23_ETRSOURCE_COMP2              TIM23_ETR is connected to COMP2 output
+  *
+  *      For TIM24, the parameter is one of the following values: (*)
+  *        @arg LL_TIM_TIM24_ETRSOURCE_GPIO                TIM24_ETR is connected to GPIO
+  *        @arg LL_TIM_TIM24_ETRSOURCE_SAI4_FSA            TIM24_ETR is connected to SAI4 FS_A
+  *        @arg LL_TIM_TIM24_ETRSOURCE_SAI4_FSB            TIM24_ETR is connected to SAI4 FS_B
+  *        @arg LL_TIM_TIM24_ETRSOURCE_SAI1_FSA            TIM24_ETR is connected to SAI1 FS_A
+  *        @arg LL_TIM_TIM24_ETRSOURCE_SAI1_FSB            TIM24_ETR is connected to SAI1 FS_B
+  *
+  *      (*)  Value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetETRSource(TIM_TypeDef *TIMx, uint32_t ETRSource)
+{
+  MODIFY_REG(TIMx->AF1, TIMx_AF1_ETRSEL, ETRSource);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EF_Break_Function Break function configuration
+  * @{
+  */
+/**
+  * @brief  Enable the break function.
+  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides a break input.
+  * @rmtoll BDTR         BKE           LL_TIM_EnableBRK
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->BDTR, TIM_BDTR_BKE);
+}
+
+/**
+  * @brief  Disable the break function.
+  * @rmtoll BDTR         BKE           LL_TIM_DisableBRK
+  * @param  TIMx Timer instance
+  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides a break input.
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE);
+}
+
+#if defined(TIM_BDTR_BKBID)
+/**
+  * @brief  Configure the break input.
+  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides a break input.
+  * @note Bidirectional mode is only supported by advanced timer instances.
+  *       Macro IS_TIM_ADVANCED_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance is an advanced-control timer.
+  * @note In bidirectional mode (BKBID bit set), the Break input is configured both
+  *        in input mode and in open drain output mode. Any active Break event will
+  *        assert a low logic level on the Break input to indicate an internal break
+  *        event to external devices.
+  * @note When bidirectional mode isn't supported, BreakAFMode must be set to
+  *       LL_TIM_BREAK_AFMODE_INPUT.
+  * @rmtoll BDTR         BKP           LL_TIM_ConfigBRK\n
+  *         BDTR         BKF           LL_TIM_ConfigBRK\n
+  *         BDTR         BKBID         LL_TIM_ConfigBRK
+  * @param  TIMx Timer instance
+  * @param  BreakPolarity This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_BREAK_POLARITY_LOW
+  *         @arg @ref LL_TIM_BREAK_POLARITY_HIGH
+  * @param  BreakFilter This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV1
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N2
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N4
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N8
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N6
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N8
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N6
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N8
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N6
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N8
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N5
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N6
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N8
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N5
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N6
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N8
+  * @param  BreakAFMode This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_BREAK_AFMODE_INPUT
+  *         @arg @ref LL_TIM_BREAK_AFMODE_BIDIRECTIONAL
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity, uint32_t BreakFilter,
+                                      uint32_t BreakAFMode)
+{
+  MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP | TIM_BDTR_BKF | TIM_BDTR_BKBID, BreakPolarity | BreakFilter | BreakAFMode);
+}
+
+#else
+/**
+  * @brief  Configure the break input.
+  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides a break input.
+  * @rmtoll BDTR         BKP           LL_TIM_ConfigBRK\n
+  *         BDTR         BKF           LL_TIM_ConfigBRK
+  * @param  TIMx Timer instance
+  * @param  BreakPolarity This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_BREAK_POLARITY_LOW
+  *         @arg @ref LL_TIM_BREAK_POLARITY_HIGH
+  * @param  BreakFilter This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV1
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N2
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N4
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N8
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N6
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N8
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N6
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N8
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N6
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N8
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N5
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N6
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N8
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N5
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N6
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N8
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity,
+                                      uint32_t BreakFilter)
+{
+  MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP | TIM_BDTR_BKF, BreakPolarity | BreakFilter);
+}
+
+#endif /* TIM_BDTR_BKBID */
+#if defined(TIM_BDTR_BKBID)
+/**
+  * @brief  Disarm the break input (when it operates in bidirectional mode).
+  * @note  The break input can be disarmed only when it is configured in
+  *        bidirectional mode and when when MOE is reset.
+  * @note  Purpose is to be able to have the input voltage back to high-state,
+  *        whatever the time constant on the output .
+  * @rmtoll BDTR         BKDSRM        LL_TIM_DisarmBRK
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisarmBRK(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->BDTR, TIM_BDTR_BKDSRM);
+}
+
+/**
+  * @brief  Re-arm the break input (when it operates in bidirectional mode).
+  * @note  The Break input is automatically armed as soon as MOE bit is set.
+  * @rmtoll BDTR         BKDSRM        LL_TIM_ReArmBRK
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ReArmBRK(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKDSRM);
+}
+
+#endif /*TIM_BDTR_BKBID */
+/**
+  * @brief  Enable the break 2 function.
+  * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides a second break input.
+  * @rmtoll BDTR         BK2E          LL_TIM_EnableBRK2
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableBRK2(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
+}
+
+/**
+  * @brief  Disable the break  2 function.
+  * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides a second break input.
+  * @rmtoll BDTR         BK2E          LL_TIM_DisableBRK2
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableBRK2(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
+}
+
+#if defined(TIM_BDTR_BKBID)
+/**
+  * @brief  Configure the break 2 input.
+  * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides a second break input.
+  * @note Bidirectional mode is only supported by advanced timer instances.
+  *       Macro IS_TIM_ADVANCED_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance is an advanced-control timer.
+  * @note In bidirectional mode (BK2BID bit set), the Break 2 input is configured both
+  *        in input mode and in open drain output mode. Any active Break event will
+  *        assert a low logic level on the Break 2 input to indicate an internal break
+  *        event to external devices.
+  * @note When bidirectional mode isn't supported, Break2AFMode must be set to
+  *       LL_TIM_BREAK2_AFMODE_INPUT.
+  * @rmtoll BDTR         BK2P          LL_TIM_ConfigBRK2\n
+  *         BDTR         BK2F          LL_TIM_ConfigBRK2\n
+  *         BDTR         BK2BID        LL_TIM_ConfigBRK2
+  * @param  TIMx Timer instance
+  * @param  Break2Polarity This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_BREAK2_POLARITY_LOW
+  *         @arg @ref LL_TIM_BREAK2_POLARITY_HIGH
+  * @param  Break2Filter This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV1
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N2
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N4
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N8
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N6
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N8
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N6
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N8
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N6
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N8
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N5
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N6
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N8
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N5
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N6
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N8
+  * @param  Break2AFMode This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_BREAK2_AFMODE_INPUT
+  *         @arg @ref LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ConfigBRK2(TIM_TypeDef *TIMx, uint32_t Break2Polarity, uint32_t Break2Filter,
+                                       uint32_t Break2AFMode)
+{
+  MODIFY_REG(TIMx->BDTR, TIM_BDTR_BK2P | TIM_BDTR_BK2F | TIM_BDTR_BK2BID, Break2Polarity | Break2Filter | Break2AFMode);
+}
+
+#else
+/**
+  * @brief  Configure the break 2 input.
+  * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides a second break input.
+  * @rmtoll BDTR         BK2P          LL_TIM_ConfigBRK2\n
+  *         BDTR         BK2F          LL_TIM_ConfigBRK2
+  * @param  TIMx Timer instance
+  * @param  Break2Polarity This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_BREAK2_POLARITY_LOW
+  *         @arg @ref LL_TIM_BREAK2_POLARITY_HIGH
+  * @param  Break2Filter This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV1
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N2
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N4
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N8
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N6
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N8
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N6
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N8
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N6
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N8
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N5
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N6
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N8
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N5
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N6
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N8
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ConfigBRK2(TIM_TypeDef *TIMx, uint32_t Break2Polarity, uint32_t Break2Filter)
+{
+  MODIFY_REG(TIMx->BDTR, TIM_BDTR_BK2P | TIM_BDTR_BK2F, Break2Polarity | Break2Filter);
+}
+
+#endif /*TIM_BDTR_BKBID */
+#if defined(TIM_BDTR_BKBID)
+/**
+  * @brief  Disarm the break 2 input (when it operates in bidirectional mode).
+  * @note  The break 2 input can be disarmed only when it is configured in
+  *        bidirectional mode and when when MOE is reset.
+  * @note  Purpose is to be able to have the input voltage back to high-state,
+  *        whatever the time constant on the output.
+  * @rmtoll BDTR         BK2DSRM       LL_TIM_DisarmBRK2
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisarmBRK2(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->BDTR, TIM_BDTR_BK2DSRM);
+}
+
+/**
+  * @brief  Re-arm the break 2 input (when it operates in bidirectional mode).
+  * @note  The Break 2 input is automatically armed as soon as MOE bit is set.
+  * @rmtoll BDTR         BK2DSRM       LL_TIM_ReArmBRK2
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ReArmBRK2(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2DSRM);
+}
+
+#endif /*TIM_BDTR_BKBID */
+/**
+  * @brief  Select the outputs off state (enabled v.s. disabled) in Idle and Run modes.
+  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides a break input.
+  * @rmtoll BDTR         OSSI          LL_TIM_SetOffStates\n
+  *         BDTR         OSSR          LL_TIM_SetOffStates
+  * @param  TIMx Timer instance
+  * @param  OffStateIdle This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_OSSI_DISABLE
+  *         @arg @ref LL_TIM_OSSI_ENABLE
+  * @param  OffStateRun This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_OSSR_DISABLE
+  *         @arg @ref LL_TIM_OSSR_ENABLE
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun)
+{
+  MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI | TIM_BDTR_OSSR, OffStateIdle | OffStateRun);
+}
+
+/**
+  * @brief  Enable automatic output (MOE can be set by software or automatically when a break input is active).
+  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides a break input.
+  * @rmtoll BDTR         AOE           LL_TIM_EnableAutomaticOutput
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->BDTR, TIM_BDTR_AOE);
+}
+
+/**
+  * @brief  Disable automatic output (MOE can be set only by software).
+  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides a break input.
+  * @rmtoll BDTR         AOE           LL_TIM_DisableAutomaticOutput
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE);
+}
+
+/**
+  * @brief  Indicate whether automatic output is enabled.
+  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides a break input.
+  * @rmtoll BDTR         AOE           LL_TIM_IsEnabledAutomaticOutput
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable the outputs (set the MOE bit in TIMx_BDTR register).
+  * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
+  *       software and is reset in case of break or break2 event
+  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides a break input.
+  * @rmtoll BDTR         MOE           LL_TIM_EnableAllOutputs
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->BDTR, TIM_BDTR_MOE);
+}
+
+/**
+  * @brief  Disable the outputs (reset the MOE bit in TIMx_BDTR register).
+  * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
+  *       software and is reset in case of break or break2 event.
+  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides a break input.
+  * @rmtoll BDTR         MOE           LL_TIM_DisableAllOutputs
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE);
+}
+
+/**
+  * @brief  Indicates whether outputs are enabled.
+  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides a break input.
+  * @rmtoll BDTR         MOE           LL_TIM_IsEnabledAllOutputs
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE)) ? 1UL : 0UL);
+}
+
+#if defined(TIM_BREAK_INPUT_SUPPORT)
+/**
+  * @brief  Enable the signals connected to the designated timer break input.
+  * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
+  *       or not a timer instance allows for break input selection.
+  * @rmtoll AF1          BKINE         LL_TIM_EnableBreakInputSource\n
+  *         AF1          BKCMP1E       LL_TIM_EnableBreakInputSource\n
+  *         AF1          BKCMP2E       LL_TIM_EnableBreakInputSource\n
+  *         AF1          BKDF1BK0E     LL_TIM_EnableBreakInputSource\n
+  *         AF2          BK2INE        LL_TIM_EnableBreakInputSource\n
+  *         AF2          BK2CMP1E      LL_TIM_EnableBreakInputSource\n
+  *         AF2          BK2CMP2E      LL_TIM_EnableBreakInputSource\n
+  *         AF2          BK2DF1BK1E    LL_TIM_EnableBreakInputSource
+  * @param  TIMx Timer instance
+  * @param  BreakInput This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_BREAK_INPUT_BKIN
+  *         @arg @ref LL_TIM_BREAK_INPUT_BKIN2
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_BKIN_SOURCE_BKIN
+  *         @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1
+  *         @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2
+  *         @arg @ref LL_TIM_BKIN_SOURCE_DF1BK
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
+{
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
+  SET_BIT(*pReg, Source);
+}
+
+/**
+  * @brief  Disable the signals connected to the designated timer break input.
+  * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
+  *       or not a timer instance allows for break input selection.
+  * @rmtoll AF1          BKINE         LL_TIM_DisableBreakInputSource\n
+  *         AF1          BKCMP1E       LL_TIM_DisableBreakInputSource\n
+  *         AF1          BKCMP2E       LL_TIM_DisableBreakInputSource\n
+  *         AF1          BKDF1BK0E     LL_TIM_DisableBreakInputSource\n
+  *         AF2          BK2INE        LL_TIM_DisableBreakInputSource\n
+  *         AF2          BK2CMP1E      LL_TIM_DisableBreakInputSource\n
+  *         AF2          BK2CMP2E      LL_TIM_DisableBreakInputSource\n
+  *         AF2          BK2DF1BK1E    LL_TIM_DisableBreakInputSource
+  * @param  TIMx Timer instance
+  * @param  BreakInput This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_BREAK_INPUT_BKIN
+  *         @arg @ref LL_TIM_BREAK_INPUT_BKIN2
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_BKIN_SOURCE_BKIN
+  *         @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1
+  *         @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2
+  *         @arg @ref LL_TIM_BKIN_SOURCE_DF1BK
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
+{
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
+  CLEAR_BIT(*pReg, Source);
+}
+
+/**
+  * @brief  Set the polarity of the break signal for the timer break input.
+  * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
+  *       or not a timer instance allows for break input selection.
+  * @rmtoll AF1          BKINP         LL_TIM_SetBreakInputSourcePolarity\n
+  *         AF1          BKCMP1P       LL_TIM_SetBreakInputSourcePolarity\n
+  *         AF1          BKCMP2P       LL_TIM_SetBreakInputSourcePolarity\n
+  *         AF2          BK2INP        LL_TIM_SetBreakInputSourcePolarity\n
+  *         AF2          BK2CMP1P      LL_TIM_SetBreakInputSourcePolarity\n
+  *         AF2          BK2CMP2P      LL_TIM_SetBreakInputSourcePolarity
+  * @param  TIMx Timer instance
+  * @param  BreakInput This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_BREAK_INPUT_BKIN
+  *         @arg @ref LL_TIM_BREAK_INPUT_BKIN2
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_BKIN_SOURCE_BKIN
+  *         @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1
+  *         @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2
+  * @param  Polarity This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_BKIN_POLARITY_LOW
+  *         @arg @ref LL_TIM_BKIN_POLARITY_HIGH
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source,
+                                                        uint32_t Polarity)
+{
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
+  MODIFY_REG(*pReg, (TIMx_AF1_BKINP << TIM_POSITION_BRK_SOURCE), (Polarity << TIM_POSITION_BRK_SOURCE));
+}
+#endif /* TIM_BREAK_INPUT_SUPPORT */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration
+  * @{
+  */
+/**
+  * @brief  Configures the timer DMA burst feature.
+  * @note Macro IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or
+  *       not a timer instance supports the DMA burst mode.
+  * @rmtoll DCR          DBL           LL_TIM_ConfigDMABurst\n
+  *         DCR          DBA           LL_TIM_ConfigDMABurst
+  * @param  TIMx Timer instance
+  * @param  DMABurstBaseAddress This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CR1
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CR2
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_DIER
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_SR
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_EGR
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCER
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CNT
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_PSC
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_ARR
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_RCR
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR3
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR5
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR6
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_AF1
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_AF2
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_TISEL
+  *
+  * @param  DMABurstLength This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength)
+{
+  MODIFY_REG(TIMx->DCR, (TIM_DCR_DBL | TIM_DCR_DBA), (DMABurstBaseAddress | DMABurstLength));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping
+  * @{
+  */
+/**
+  * @brief  Remap TIM inputs (input channel, internal/external triggers).
+  * @note Macro IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not
+  *       a some timer inputs can be remapped.
+  *         TIM1: one of the following values:
+  *            @arg LL_TIM_TIM1_TI1_RMP_GPIO:                TIM1 TI1 is connected to GPIO
+  *            @arg LL_TIM_TIM1_TI1_RMP_COMP1:               TIM1 TI1 is connected to COMP1 output
+  *
+  *         TIM2: one of the following values:
+  *            @arg LL_TIM_TIM2_TI4_RMP_GPIO:                TIM2 TI4 is connected to GPIO
+  *            @arg LL_TIM_TIM2_TI4_RMP_COMP1:               TIM2 TI4 is connected to COMP1 output
+  *            @arg LL_TIM_TIM2_TI4_RMP_COMP2:               TIM2 TI4 is connected to COMP2 output
+  *            @arg LL_TIM_TIM2_TI4_RMP_COMP1_COMP2:         TIM2 TI4 is connected to logical OR between COMP1 and COMP2 output
+  *
+  *         TIM3: one of the following values:
+  *            @arg LL_TIM_TIM3_TI1_RMP_GPIO:                TIM3 TI1 is connected to GPIO
+  *            @arg LL_TIM_TIM3_TI1_RMP_COMP1:               TIM3 TI1 is connected to COMP1 output
+  *            @arg LL_TIM_TIM3_TI1_RMP_COMP2:               TIM3 TI1 is connected to COMP2 output
+  *            @arg LL_TIM_TIM3_TI1_RMP_COMP1_COMP2:         TIM3 TI1 is connected to logical OR between COMP1 and COMP2 output
+  *
+  *         TIM5: one of the following values:
+  *            @arg LL_TIM_TIM5_TI1_RMP_GPIO:                TIM5 TI1 is connected to GPIO
+  *            @arg LL_TIM_TIM5_TI1_RMP_CAN_TMP:             TIM5 TI1 is connected to CAN TMP
+  *            @arg LL_TIM_TIM5_TI1_RMP_CAN_RTP:             TIM5 TI1 is connected to CAN RTP
+  *
+  *         TIM8: one of the following values:
+  *            @arg LL_TIM_TIM8_TI1_RMP_GPIO:               TIM8 TI1 is connected to GPIO
+  *            @arg LL_TIM_TIM8_TI1_RMP_COMP2:              TIM8 TI1 is connected to COMP2 output
+  *
+  *         TIM12: one of the following values: (*)
+  *            @arg LL_TIM_TIM12_TI1_RMP_GPIO:              TIM12 TI1 is connected to GPIO
+  *            @arg LL_TIM_TIM12_TI1_RMP_SPDIF_FS:          TIM12 TI1 is connected to SPDIF FS
+  *
+  *         TIM15: one of the following values:
+  *            @arg LL_TIM_TIM15_TI1_RMP_GPIO:              TIM15 TI1 is connected to GPIO
+  *            @arg LL_TIM_TIM15_TI1_RMP_TIM2:              TIM15 TI1 is connected to TIM2 CH1
+  *            @arg LL_TIM_TIM15_TI1_RMP_TIM3:              TIM15 TI1 is connected to TIM3 CH1
+  *            @arg LL_TIM_TIM15_TI1_RMP_TIM4:              TIM15 TI1 is connected to TIM4 CH1
+  *            @arg LL_TIM_TIM15_TI1_RMP_LSE:               TIM15 TI1 is connected to LSE
+  *            @arg LL_TIM_TIM15_TI1_RMP_CSI:               TIM15 TI1 is connected to CSI
+  *            @arg LL_TIM_TIM15_TI1_RMP_MCO2:              TIM15 TI1 is connected to MCO2
+  *            @arg LL_TIM_TIM15_TI2_RMP_GPIO:              TIM15 TI2 is connected to GPIO
+  *            @arg LL_TIM_TIM15_TI2_RMP_TIM2:              TIM15 TI2 is connected to TIM2 CH2
+  *            @arg LL_TIM_TIM15_TI2_RMP_TIM3:              TIM15 TI2 is connected to TIM3 CH2
+  *            @arg LL_TIM_TIM15_TI2_RMP_TIM4:              TIM15 TI2 is connected to TIM4 CH2
+  *
+  *         TIM16: one of the following values:
+  *            @arg LL_TIM_TIM16_TI1_RMP_GPIO:              TIM16 TI1 is connected to GPIO
+  *            @arg LL_TIM_TIM16_TI1_RMP_LSI:               TIM16 TI1 is connected to LSI
+  *            @arg LL_TIM_TIM16_TI1_RMP_LSE:               TIM16 TI1 is connected to LSE
+  *            @arg LL_TIM_TIM16_TI1_RMP_RTC:               TIM16 TI1 is connected to RTC wakeup interrupt
+  *
+  *         TIM17: one of the following values:
+  *            @arg LL_TIM_TIM17_TI1_RMP_GPIO:              TIM17 TI1 is connected to GPIO
+  *            @arg LL_TIM_TIM17_TI1_RMP_SPDIF_FS:          TIM17 TI1 is connected to SPDIF FS (*)
+  *            @arg LL_TIM_TIM17_TI1_RMP_HSE_1MHZ:          TIM17 TI1 is connected to HSE 1MHz
+  *            @arg LL_TIM_TIM17_TI1_RMP_MCO1:              TIM17 TI1 is connected to MCO1
+  *
+  *         TIM23: one of the following values: (*)
+  *            @arg LL_TIM_TIM23_TI4_RMP_GPIO               TIM23_TI4 is connected to GPIO
+  *            @arg LL_TIM_TIM23_TI4_RMP_COMP1              TIM23_TI4 is connected to COMP1 output
+  *            @arg LL_TIM_TIM23_TI4_RMP_COMP2              TIM23_TI4 is connected to COMP2 output
+  *            @arg LL_TIM_TIM23_TI4_RMP_COMP1_COMP2        TIM23_TI4 is connected to COMP2 output
+  *
+  *         TIM24: one of the following values: (*)
+  *            @arg LL_TIM_TIM24_TI1_RMP_GPIO               TIM24_TI1 is connected to GPIO
+  *            @arg LL_TIM_TIM24_TI1_RMP_CAN_TMP            TIM24_TI1 is connected to CAN_TMP
+  *            @arg LL_TIM_TIM24_TI1_RMP_CAN_RTP            TIM24_TI1 is connected to CAN_RTP
+  *            @arg LL_TIM_TIM24_TI1_RMP_CAN_SOC            TIM24_TI1 is connected to CAN_SOC
+  *
+  *         (*)  Value not defined in all devices. \n
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap)
+{
+  MODIFY_REG(TIMx->TISEL, (TIM_TISEL_TI1SEL | TIM_TISEL_TI2SEL | TIM_TISEL_TI3SEL | TIM_TISEL_TI4SEL), Remap);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management
+  * @{
+  */
+/**
+  * @brief  Clear the update interrupt flag (UIF).
+  * @rmtoll SR           UIF           LL_TIM_ClearFlag_UPDATE
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_UIF));
+}
+
+/**
+  * @brief  Indicate whether update interrupt flag (UIF) is set (update interrupt is pending).
+  * @rmtoll SR           UIF           LL_TIM_IsActiveFlag_UPDATE
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the Capture/Compare 1 interrupt flag (CC1F).
+  * @rmtoll SR           CC1IF         LL_TIM_ClearFlag_CC1
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF));
+}
+
+/**
+  * @brief  Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending).
+  * @rmtoll SR           CC1IF         LL_TIM_IsActiveFlag_CC1
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the Capture/Compare 2 interrupt flag (CC2F).
+  * @rmtoll SR           CC2IF         LL_TIM_ClearFlag_CC2
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF));
+}
+
+/**
+  * @brief  Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending).
+  * @rmtoll SR           CC2IF         LL_TIM_IsActiveFlag_CC2
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the Capture/Compare 3 interrupt flag (CC3F).
+  * @rmtoll SR           CC3IF         LL_TIM_ClearFlag_CC3
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF));
+}
+
+/**
+  * @brief  Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending).
+  * @rmtoll SR           CC3IF         LL_TIM_IsActiveFlag_CC3
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the Capture/Compare 4 interrupt flag (CC4F).
+  * @rmtoll SR           CC4IF         LL_TIM_ClearFlag_CC4
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF));
+}
+
+/**
+  * @brief  Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending).
+  * @rmtoll SR           CC4IF         LL_TIM_IsActiveFlag_CC4
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the Capture/Compare 5 interrupt flag (CC5F).
+  * @rmtoll SR           CC5IF         LL_TIM_ClearFlag_CC5
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC5(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_CC5IF));
+}
+
+/**
+  * @brief  Indicate whether Capture/Compare 5 interrupt flag (CC5F) is set (Capture/Compare 5 interrupt is pending).
+  * @rmtoll SR           CC5IF         LL_TIM_IsActiveFlag_CC5
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC5(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_CC5IF) == (TIM_SR_CC5IF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the Capture/Compare 6 interrupt flag (CC6F).
+  * @rmtoll SR           CC6IF         LL_TIM_ClearFlag_CC6
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC6(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_CC6IF));
+}
+
+/**
+  * @brief  Indicate whether Capture/Compare 6 interrupt flag (CC6F) is set (Capture/Compare 6 interrupt is pending).
+  * @rmtoll SR           CC6IF         LL_TIM_IsActiveFlag_CC6
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC6(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_CC6IF) == (TIM_SR_CC6IF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the commutation interrupt flag (COMIF).
+  * @rmtoll SR           COMIF         LL_TIM_ClearFlag_COM
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF));
+}
+
+/**
+  * @brief  Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending).
+  * @rmtoll SR           COMIF         LL_TIM_IsActiveFlag_COM
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the trigger interrupt flag (TIF).
+  * @rmtoll SR           TIF           LL_TIM_ClearFlag_TRIG
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_TIF));
+}
+
+/**
+  * @brief  Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending).
+  * @rmtoll SR           TIF           LL_TIM_IsActiveFlag_TRIG
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the break interrupt flag (BIF).
+  * @rmtoll SR           BIF           LL_TIM_ClearFlag_BRK
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_BIF));
+}
+
+/**
+  * @brief  Indicate whether break interrupt flag (BIF) is set (break interrupt is pending).
+  * @rmtoll SR           BIF           LL_TIM_IsActiveFlag_BRK
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the break 2 interrupt flag (B2IF).
+  * @rmtoll SR           B2IF          LL_TIM_ClearFlag_BRK2
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_BRK2(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_B2IF));
+}
+
+/**
+  * @brief  Indicate whether break 2 interrupt flag (B2IF) is set (break 2 interrupt is pending).
+  * @rmtoll SR           B2IF          LL_TIM_IsActiveFlag_BRK2
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK2(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_B2IF) == (TIM_SR_B2IF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).
+  * @rmtoll SR           CC1OF         LL_TIM_ClearFlag_CC1OVR
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF));
+}
+
+/**
+  * @brief  Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set
+  *         (Capture/Compare 1 interrupt is pending).
+  * @rmtoll SR           CC1OF         LL_TIM_IsActiveFlag_CC1OVR
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).
+  * @rmtoll SR           CC2OF         LL_TIM_ClearFlag_CC2OVR
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF));
+}
+
+/**
+  * @brief  Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set
+  *         (Capture/Compare 2 over-capture interrupt is pending).
+  * @rmtoll SR           CC2OF         LL_TIM_IsActiveFlag_CC2OVR
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).
+  * @rmtoll SR           CC3OF         LL_TIM_ClearFlag_CC3OVR
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF));
+}
+
+/**
+  * @brief  Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set
+  *         (Capture/Compare 3 over-capture interrupt is pending).
+  * @rmtoll SR           CC3OF         LL_TIM_IsActiveFlag_CC3OVR
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).
+  * @rmtoll SR           CC4OF         LL_TIM_ClearFlag_CC4OVR
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF));
+}
+
+/**
+  * @brief  Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set
+  *         (Capture/Compare 4 over-capture interrupt is pending).
+  * @rmtoll SR           CC4OF         LL_TIM_IsActiveFlag_CC4OVR
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the system break interrupt flag (SBIF).
+  * @rmtoll SR           SBIF          LL_TIM_ClearFlag_SYSBRK
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_SYSBRK(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_SBIF));
+}
+
+/**
+  * @brief  Indicate whether system break interrupt flag (SBIF) is set (system break interrupt is pending).
+  * @rmtoll SR           SBIF          LL_TIM_IsActiveFlag_SYSBRK
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_SYSBRK(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_SBIF) == (TIM_SR_SBIF)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EF_IT_Management IT-Management
+  * @{
+  */
+/**
+  * @brief  Enable update interrupt (UIE).
+  * @rmtoll DIER         UIE           LL_TIM_EnableIT_UPDATE
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_UIE);
+}
+
+/**
+  * @brief  Disable update interrupt (UIE).
+  * @rmtoll DIER         UIE           LL_TIM_DisableIT_UPDATE
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE);
+}
+
+/**
+  * @brief  Indicates whether the update interrupt (UIE) is enabled.
+  * @rmtoll DIER         UIE           LL_TIM_IsEnabledIT_UPDATE
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable capture/compare 1 interrupt (CC1IE).
+  * @rmtoll DIER         CC1IE         LL_TIM_EnableIT_CC1
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_CC1IE);
+}
+
+/**
+  * @brief  Disable capture/compare 1  interrupt (CC1IE).
+  * @rmtoll DIER         CC1IE         LL_TIM_DisableIT_CC1
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE);
+}
+
+/**
+  * @brief  Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
+  * @rmtoll DIER         CC1IE         LL_TIM_IsEnabledIT_CC1
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable capture/compare 2 interrupt (CC2IE).
+  * @rmtoll DIER         CC2IE         LL_TIM_EnableIT_CC2
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_CC2IE);
+}
+
+/**
+  * @brief  Disable capture/compare 2  interrupt (CC2IE).
+  * @rmtoll DIER         CC2IE         LL_TIM_DisableIT_CC2
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE);
+}
+
+/**
+  * @brief  Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
+  * @rmtoll DIER         CC2IE         LL_TIM_IsEnabledIT_CC2
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable capture/compare 3 interrupt (CC3IE).
+  * @rmtoll DIER         CC3IE         LL_TIM_EnableIT_CC3
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_CC3IE);
+}
+
+/**
+  * @brief  Disable capture/compare 3  interrupt (CC3IE).
+  * @rmtoll DIER         CC3IE         LL_TIM_DisableIT_CC3
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE);
+}
+
+/**
+  * @brief  Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.
+  * @rmtoll DIER         CC3IE         LL_TIM_IsEnabledIT_CC3
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable capture/compare 4 interrupt (CC4IE).
+  * @rmtoll DIER         CC4IE         LL_TIM_EnableIT_CC4
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_CC4IE);
+}
+
+/**
+  * @brief  Disable capture/compare 4  interrupt (CC4IE).
+  * @rmtoll DIER         CC4IE         LL_TIM_DisableIT_CC4
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE);
+}
+
+/**
+  * @brief  Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.
+  * @rmtoll DIER         CC4IE         LL_TIM_IsEnabledIT_CC4
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable commutation interrupt (COMIE).
+  * @rmtoll DIER         COMIE         LL_TIM_EnableIT_COM
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableIT_COM(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_COMIE);
+}
+
+/**
+  * @brief  Disable commutation interrupt (COMIE).
+  * @rmtoll DIER         COMIE         LL_TIM_DisableIT_COM
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_COMIE);
+}
+
+/**
+  * @brief  Indicates whether the commutation interrupt (COMIE) is enabled.
+  * @rmtoll DIER         COMIE         LL_TIM_IsEnabledIT_COM
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable trigger interrupt (TIE).
+  * @rmtoll DIER         TIE           LL_TIM_EnableIT_TRIG
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_TIE);
+}
+
+/**
+  * @brief  Disable trigger interrupt (TIE).
+  * @rmtoll DIER         TIE           LL_TIM_DisableIT_TRIG
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE);
+}
+
+/**
+  * @brief  Indicates whether the trigger interrupt (TIE) is enabled.
+  * @rmtoll DIER         TIE           LL_TIM_IsEnabledIT_TRIG
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable break interrupt (BIE).
+  * @rmtoll DIER         BIE           LL_TIM_EnableIT_BRK
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableIT_BRK(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_BIE);
+}
+
+/**
+  * @brief  Disable break interrupt (BIE).
+  * @rmtoll DIER         BIE           LL_TIM_DisableIT_BRK
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_BIE);
+}
+
+/**
+  * @brief  Indicates whether the break interrupt (BIE) is enabled.
+  * @rmtoll DIER         BIE           LL_TIM_IsEnabledIT_BRK
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EF_DMA_Management DMA Management
+  * @{
+  */
+/**
+  * @brief  Enable update DMA request (UDE).
+  * @rmtoll DIER         UDE           LL_TIM_EnableDMAReq_UPDATE
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_UDE);
+}
+
+/**
+  * @brief  Disable update DMA request (UDE).
+  * @rmtoll DIER         UDE           LL_TIM_DisableDMAReq_UPDATE
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE);
+}
+
+/**
+  * @brief  Indicates whether the update DMA request  (UDE) is enabled.
+  * @rmtoll DIER         UDE           LL_TIM_IsEnabledDMAReq_UPDATE
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable capture/compare 1 DMA request (CC1DE).
+  * @rmtoll DIER         CC1DE         LL_TIM_EnableDMAReq_CC1
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_CC1DE);
+}
+
+/**
+  * @brief  Disable capture/compare 1  DMA request (CC1DE).
+  * @rmtoll DIER         CC1DE         LL_TIM_DisableDMAReq_CC1
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE);
+}
+
+/**
+  * @brief  Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
+  * @rmtoll DIER         CC1DE         LL_TIM_IsEnabledDMAReq_CC1
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable capture/compare 2 DMA request (CC2DE).
+  * @rmtoll DIER         CC2DE         LL_TIM_EnableDMAReq_CC2
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_CC2DE);
+}
+
+/**
+  * @brief  Disable capture/compare 2  DMA request (CC2DE).
+  * @rmtoll DIER         CC2DE         LL_TIM_DisableDMAReq_CC2
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE);
+}
+
+/**
+  * @brief  Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
+  * @rmtoll DIER         CC2DE         LL_TIM_IsEnabledDMAReq_CC2
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable capture/compare 3 DMA request (CC3DE).
+  * @rmtoll DIER         CC3DE         LL_TIM_EnableDMAReq_CC3
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_CC3DE);
+}
+
+/**
+  * @brief  Disable capture/compare 3  DMA request (CC3DE).
+  * @rmtoll DIER         CC3DE         LL_TIM_DisableDMAReq_CC3
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE);
+}
+
+/**
+  * @brief  Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled.
+  * @rmtoll DIER         CC3DE         LL_TIM_IsEnabledDMAReq_CC3
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable capture/compare 4 DMA request (CC4DE).
+  * @rmtoll DIER         CC4DE         LL_TIM_EnableDMAReq_CC4
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_CC4DE);
+}
+
+/**
+  * @brief  Disable capture/compare 4  DMA request (CC4DE).
+  * @rmtoll DIER         CC4DE         LL_TIM_DisableDMAReq_CC4
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE);
+}
+
+/**
+  * @brief  Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled.
+  * @rmtoll DIER         CC4DE         LL_TIM_IsEnabledDMAReq_CC4
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable commutation DMA request (COMDE).
+  * @rmtoll DIER         COMDE         LL_TIM_EnableDMAReq_COM
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableDMAReq_COM(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_COMDE);
+}
+
+/**
+  * @brief  Disable commutation DMA request (COMDE).
+  * @rmtoll DIER         COMDE         LL_TIM_DisableDMAReq_COM
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_COMDE);
+}
+
+/**
+  * @brief  Indicates whether the commutation DMA request (COMDE) is enabled.
+  * @rmtoll DIER         COMDE         LL_TIM_IsEnabledDMAReq_COM
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable trigger interrupt (TDE).
+  * @rmtoll DIER         TDE           LL_TIM_EnableDMAReq_TRIG
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_TDE);
+}
+
+/**
+  * @brief  Disable trigger interrupt (TDE).
+  * @rmtoll DIER         TDE           LL_TIM_DisableDMAReq_TRIG
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE);
+}
+
+/**
+  * @brief  Indicates whether the trigger interrupt (TDE) is enabled.
+  * @rmtoll DIER         TDE           LL_TIM_IsEnabledDMAReq_TRIG
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management
+  * @{
+  */
+/**
+  * @brief  Generate an update event.
+  * @rmtoll EGR          UG            LL_TIM_GenerateEvent_UPDATE
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->EGR, TIM_EGR_UG);
+}
+
+/**
+  * @brief  Generate Capture/Compare 1 event.
+  * @rmtoll EGR          CC1G          LL_TIM_GenerateEvent_CC1
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->EGR, TIM_EGR_CC1G);
+}
+
+/**
+  * @brief  Generate Capture/Compare 2 event.
+  * @rmtoll EGR          CC2G          LL_TIM_GenerateEvent_CC2
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->EGR, TIM_EGR_CC2G);
+}
+
+/**
+  * @brief  Generate Capture/Compare 3 event.
+  * @rmtoll EGR          CC3G          LL_TIM_GenerateEvent_CC3
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->EGR, TIM_EGR_CC3G);
+}
+
+/**
+  * @brief  Generate Capture/Compare 4 event.
+  * @rmtoll EGR          CC4G          LL_TIM_GenerateEvent_CC4
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->EGR, TIM_EGR_CC4G);
+}
+
+/**
+  * @brief  Generate commutation event.
+  * @rmtoll EGR          COMG          LL_TIM_GenerateEvent_COM
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_GenerateEvent_COM(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->EGR, TIM_EGR_COMG);
+}
+
+/**
+  * @brief  Generate trigger event.
+  * @rmtoll EGR          TG            LL_TIM_GenerateEvent_TRIG
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->EGR, TIM_EGR_TG);
+}
+
+/**
+  * @brief  Generate break event.
+  * @rmtoll EGR          BG            LL_TIM_GenerateEvent_BRK
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->EGR, TIM_EGR_BG);
+}
+
+/**
+  * @brief  Generate break 2 event.
+  * @rmtoll EGR          B2G           LL_TIM_GenerateEvent_BRK2
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_GenerateEvent_BRK2(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->EGR, TIM_EGR_B2G);
+}
+
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions
+  * @{
+  */
+
+ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx);
+void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct);
+ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, const LL_TIM_InitTypeDef *TIM_InitStruct);
+void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
+ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
+void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
+ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct);
+void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
+ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, const LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
+void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
+ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, const LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
+void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
+ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM5 || TIM6 || TIM7 || TIM8 || TIM12 || TIM13 ||TIM14 || TIM15 || TIM16 || TIM17  || TIM23  || TIM24 */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32H7xx_LL_TIM_H */
diff --git a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usart.h b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usart.h
new file mode 100644
index 0000000..8494c35
--- /dev/null
+++ b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usart.h
@@ -0,0 +1,4400 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_ll_usart.h
+  * @author  MCD Application Team
+  * @brief   Header file of USART LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_LL_USART_H
+#define STM32H7xx_LL_USART_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx.h"
+
+/** @addtogroup STM32H7xx_LL_Driver
+  * @{
+  */
+
+#if defined(USART1) || defined(USART2) || defined(USART3) || defined(USART6) \
+ || defined(UART4) || defined(UART5) || defined(UART7) || defined(UART8) || defined(UART9) || defined(USART10)
+
+/** @defgroup USART_LL USART
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup USART_LL_Private_Variables USART Private Variables
+  * @{
+  */
+/* Array used to get the USART prescaler division decimal values versus @ref USART_LL_EC_PRESCALER values */
+static const uint32_t USART_PRESCALER_TAB[] =
+{
+  1UL,
+  2UL,
+  4UL,
+  6UL,
+  8UL,
+  10UL,
+  12UL,
+  16UL,
+  32UL,
+  64UL,
+  128UL,
+  256UL
+};
+/**
+  * @}
+  */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup USART_LL_Private_Constants USART Private Constants
+  * @{
+  */
+/**
+  * @}
+  */
+/* Private macros ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup USART_LL_Private_Macros USART Private Macros
+  * @{
+  */
+/**
+  * @}
+  */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup USART_LL_ES_INIT USART Exported Init structures
+  * @{
+  */
+
+/**
+  * @brief LL USART Init Structure definition
+  */
+typedef struct
+{
+  uint32_t PrescalerValue;            /*!< Specifies the Prescaler to compute the communication baud rate.
+                                           This parameter can be a value of @ref USART_LL_EC_PRESCALER.
+
+                                           This feature can be modified afterwards using unitary
+                                           function @ref LL_USART_SetPrescaler().*/
+
+  uint32_t BaudRate;                  /*!< This field defines expected Usart communication baud rate.
+
+                                           This feature can be modified afterwards using unitary
+                                           function @ref LL_USART_SetBaudRate().*/
+
+  uint32_t DataWidth;                 /*!< Specifies the number of data bits transmitted or received in a frame.
+                                           This parameter can be a value of @ref USART_LL_EC_DATAWIDTH.
+
+                                           This feature can be modified afterwards using unitary
+                                           function @ref LL_USART_SetDataWidth().*/
+
+  uint32_t StopBits;                  /*!< Specifies the number of stop bits transmitted.
+                                           This parameter can be a value of @ref USART_LL_EC_STOPBITS.
+
+                                           This feature can be modified afterwards using unitary
+                                           function @ref LL_USART_SetStopBitsLength().*/
+
+  uint32_t Parity;                    /*!< Specifies the parity mode.
+                                           This parameter can be a value of @ref USART_LL_EC_PARITY.
+
+                                           This feature can be modified afterwards using unitary
+                                           function @ref LL_USART_SetParity().*/
+
+  uint32_t TransferDirection;         /*!< Specifies whether the Receive and/or Transmit mode is enabled or disabled.
+                                           This parameter can be a value of @ref USART_LL_EC_DIRECTION.
+
+                                           This feature can be modified afterwards using unitary
+                                           function @ref LL_USART_SetTransferDirection().*/
+
+  uint32_t HardwareFlowControl;       /*!< Specifies whether the hardware flow control mode is enabled or disabled.
+                                           This parameter can be a value of @ref USART_LL_EC_HWCONTROL.
+
+                                           This feature can be modified afterwards using unitary
+                                           function @ref LL_USART_SetHWFlowCtrl().*/
+
+  uint32_t OverSampling;              /*!< Specifies whether USART oversampling mode is 16 or 8.
+                                           This parameter can be a value of @ref USART_LL_EC_OVERSAMPLING.
+
+                                           This feature can be modified afterwards using unitary
+                                           function @ref LL_USART_SetOverSampling().*/
+
+} LL_USART_InitTypeDef;
+
+/**
+  * @brief LL USART Clock Init Structure definition
+  */
+typedef struct
+{
+  uint32_t ClockOutput;               /*!< Specifies whether the USART clock is enabled or disabled.
+                                           This parameter can be a value of @ref USART_LL_EC_CLOCK.
+
+                                           USART HW configuration can be modified afterwards using unitary functions
+                                           @ref LL_USART_EnableSCLKOutput() or @ref LL_USART_DisableSCLKOutput().
+                                           For more details, refer to description of this function. */
+
+  uint32_t ClockPolarity;             /*!< Specifies the steady state of the serial clock.
+                                           This parameter can be a value of @ref USART_LL_EC_POLARITY.
+
+                                           USART HW configuration can be modified afterwards using unitary
+                                           functions @ref LL_USART_SetClockPolarity().
+                                           For more details, refer to description of this function. */
+
+  uint32_t ClockPhase;                /*!< Specifies the clock transition on which the bit capture is made.
+                                           This parameter can be a value of @ref USART_LL_EC_PHASE.
+
+                                           USART HW configuration can be modified afterwards using unitary
+                                           functions @ref LL_USART_SetClockPhase().
+                                           For more details, refer to description of this function. */
+
+  uint32_t LastBitClockPulse;         /*!< Specifies whether the clock pulse corresponding to the last transmitted
+                                           data bit (MSB) has to be output on the SCLK pin in synchronous mode.
+                                           This parameter can be a value of @ref USART_LL_EC_LASTCLKPULSE.
+
+                                           USART HW configuration can be modified afterwards using unitary
+                                           functions @ref LL_USART_SetLastClkPulseOutput().
+                                           For more details, refer to description of this function. */
+
+} LL_USART_ClockInitTypeDef;
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup USART_LL_Exported_Constants USART Exported Constants
+  * @{
+  */
+
+/** @defgroup USART_LL_EC_CLEAR_FLAG Clear Flags Defines
+  * @brief    Flags defines which can be used with LL_USART_WriteReg function
+  * @{
+  */
+#define LL_USART_ICR_PECF                       USART_ICR_PECF                /*!< Parity error clear flag */
+#define LL_USART_ICR_FECF                       USART_ICR_FECF                /*!< Framing error clear flag */
+#define LL_USART_ICR_NECF                       USART_ICR_NECF                /*!< Noise error detected clear flag */
+#define LL_USART_ICR_ORECF                      USART_ICR_ORECF               /*!< Overrun error clear flag */
+#define LL_USART_ICR_IDLECF                     USART_ICR_IDLECF              /*!< Idle line detected clear flag */
+#define LL_USART_ICR_TXFECF                     USART_ICR_TXFECF              /*!< TX FIFO Empty clear flag */
+#define LL_USART_ICR_TCCF                       USART_ICR_TCCF                /*!< Transmission complete clear flag */
+#define LL_USART_ICR_TCBGTCF                    USART_ICR_TCBGTCF             /*!< Transmission completed before guard time clear flag */
+#define LL_USART_ICR_LBDCF                      USART_ICR_LBDCF               /*!< LIN break detection clear flag */
+#define LL_USART_ICR_CTSCF                      USART_ICR_CTSCF               /*!< CTS clear flag */
+#define LL_USART_ICR_RTOCF                      USART_ICR_RTOCF               /*!< Receiver timeout clear flag */
+#define LL_USART_ICR_EOBCF                      USART_ICR_EOBCF               /*!< End of block clear flag */
+#define LL_USART_ICR_UDRCF                      USART_ICR_UDRCF               /*!< SPI Slave Underrun clear flag */
+#define LL_USART_ICR_CMCF                       USART_ICR_CMCF                /*!< Character match clear flag */
+#define LL_USART_ICR_WUCF                       USART_ICR_WUCF                /*!< Wakeup from Stop mode clear flag */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_GET_FLAG Get Flags Defines
+  * @brief    Flags defines which can be used with LL_USART_ReadReg function
+  * @{
+  */
+#define LL_USART_ISR_PE                         USART_ISR_PE                  /*!< Parity error flag */
+#define LL_USART_ISR_FE                         USART_ISR_FE                  /*!< Framing error flag */
+#define LL_USART_ISR_NE                         USART_ISR_NE                  /*!< Noise detected flag */
+#define LL_USART_ISR_ORE                        USART_ISR_ORE                 /*!< Overrun error flag */
+#define LL_USART_ISR_IDLE                       USART_ISR_IDLE                /*!< Idle line detected flag */
+#define LL_USART_ISR_RXNE_RXFNE                 USART_ISR_RXNE_RXFNE          /*!< Read data register or RX FIFO not empty flag */
+#define LL_USART_ISR_TC                         USART_ISR_TC                  /*!< Transmission complete flag */
+#define LL_USART_ISR_TXE_TXFNF                  USART_ISR_TXE_TXFNF           /*!< Transmit data register empty or TX FIFO Not Full flag*/
+#define LL_USART_ISR_LBDF                       USART_ISR_LBDF                /*!< LIN break detection flag */
+#define LL_USART_ISR_CTSIF                      USART_ISR_CTSIF               /*!< CTS interrupt flag */
+#define LL_USART_ISR_CTS                        USART_ISR_CTS                 /*!< CTS flag */
+#define LL_USART_ISR_RTOF                       USART_ISR_RTOF                /*!< Receiver timeout flag */
+#define LL_USART_ISR_EOBF                       USART_ISR_EOBF                /*!< End of block flag */
+#define LL_USART_ISR_UDR                        USART_ISR_UDR                 /*!< SPI Slave underrun error flag */
+#define LL_USART_ISR_ABRE                       USART_ISR_ABRE                /*!< Auto baud rate error flag */
+#define LL_USART_ISR_ABRF                       USART_ISR_ABRF                /*!< Auto baud rate flag */
+#define LL_USART_ISR_BUSY                       USART_ISR_BUSY                /*!< Busy flag */
+#define LL_USART_ISR_CMF                        USART_ISR_CMF                 /*!< Character match flag */
+#define LL_USART_ISR_SBKF                       USART_ISR_SBKF                /*!< Send break flag */
+#define LL_USART_ISR_RWU                        USART_ISR_RWU                 /*!< Receiver wakeup from Mute mode flag */
+#define LL_USART_ISR_WUF                        USART_ISR_WUF                 /*!< Wakeup from Stop mode flag */
+#define LL_USART_ISR_TEACK                      USART_ISR_TEACK               /*!< Transmit enable acknowledge flag */
+#define LL_USART_ISR_REACK                      USART_ISR_REACK               /*!< Receive enable acknowledge flag */
+#define LL_USART_ISR_TXFE                       USART_ISR_TXFE                /*!< TX FIFO empty flag */
+#define LL_USART_ISR_RXFF                       USART_ISR_RXFF                /*!< RX FIFO full flag */
+#define LL_USART_ISR_TCBGT                      USART_ISR_TCBGT               /*!< Transmission complete before guard time completion flag */
+#define LL_USART_ISR_RXFT                       USART_ISR_RXFT                /*!< RX FIFO threshold flag */
+#define LL_USART_ISR_TXFT                       USART_ISR_TXFT                /*!< TX FIFO threshold flag */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_IT IT Defines
+  * @brief    IT defines which can be used with LL_USART_ReadReg and  LL_USART_WriteReg functions
+  * @{
+  */
+#define LL_USART_CR1_IDLEIE                     USART_CR1_IDLEIE              /*!< IDLE interrupt enable */
+#define LL_USART_CR1_RXNEIE_RXFNEIE             USART_CR1_RXNEIE_RXFNEIE      /*!< Read data register and RXFIFO not empty interrupt enable */
+#define LL_USART_CR1_TCIE                       USART_CR1_TCIE                /*!< Transmission complete interrupt enable */
+#define LL_USART_CR1_TXEIE_TXFNFIE              USART_CR1_TXEIE_TXFNFIE       /*!< Transmit data register empty and TX FIFO not full interrupt enable */
+#define LL_USART_CR1_PEIE                       USART_CR1_PEIE                /*!< Parity error */
+#define LL_USART_CR1_CMIE                       USART_CR1_CMIE                /*!< Character match interrupt enable */
+#define LL_USART_CR1_RTOIE                      USART_CR1_RTOIE               /*!< Receiver timeout interrupt enable */
+#define LL_USART_CR1_EOBIE                      USART_CR1_EOBIE               /*!< End of Block interrupt enable */
+#define LL_USART_CR1_TXFEIE                     USART_CR1_TXFEIE              /*!< TX FIFO empty interrupt enable */
+#define LL_USART_CR1_RXFFIE                     USART_CR1_RXFFIE              /*!< RX FIFO full interrupt enable */
+#define LL_USART_CR2_LBDIE                      USART_CR2_LBDIE               /*!< LIN break detection interrupt enable */
+#define LL_USART_CR3_EIE                        USART_CR3_EIE                 /*!< Error interrupt enable */
+#define LL_USART_CR3_CTSIE                      USART_CR3_CTSIE               /*!< CTS interrupt enable */
+#define LL_USART_CR3_WUFIE                      USART_CR3_WUFIE               /*!< Wakeup from Stop mode interrupt enable */
+#define LL_USART_CR3_TXFTIE                     USART_CR3_TXFTIE              /*!< TX FIFO threshold interrupt enable */
+#define LL_USART_CR3_TCBGTIE                    USART_CR3_TCBGTIE             /*!< Transmission complete before guard time interrupt enable */
+#define LL_USART_CR3_RXFTIE                     USART_CR3_RXFTIE              /*!< RX FIFO threshold interrupt enable */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_FIFOTHRESHOLD FIFO Threshold
+  * @{
+  */
+#define LL_USART_FIFOTHRESHOLD_1_8              0x00000000U /*!< FIFO reaches 1/8 of its depth */
+#define LL_USART_FIFOTHRESHOLD_1_4              0x00000001U /*!< FIFO reaches 1/4 of its depth */
+#define LL_USART_FIFOTHRESHOLD_1_2              0x00000002U /*!< FIFO reaches 1/2 of its depth */
+#define LL_USART_FIFOTHRESHOLD_3_4              0x00000003U /*!< FIFO reaches 3/4 of its depth */
+#define LL_USART_FIFOTHRESHOLD_7_8              0x00000004U /*!< FIFO reaches 7/8 of its depth */
+#define LL_USART_FIFOTHRESHOLD_8_8              0x00000005U /*!< FIFO becomes empty for TX and full for RX */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_DIRECTION Communication Direction
+  * @{
+  */
+#define LL_USART_DIRECTION_NONE                 0x00000000U                        /*!< Transmitter and Receiver are disabled */
+#define LL_USART_DIRECTION_RX                   USART_CR1_RE                       /*!< Transmitter is disabled and Receiver is enabled */
+#define LL_USART_DIRECTION_TX                   USART_CR1_TE                       /*!< Transmitter is enabled and Receiver is disabled */
+#define LL_USART_DIRECTION_TX_RX                (USART_CR1_TE |USART_CR1_RE)       /*!< Transmitter and Receiver are enabled */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_PARITY Parity Control
+  * @{
+  */
+#define LL_USART_PARITY_NONE                    0x00000000U                          /*!< Parity control disabled */
+#define LL_USART_PARITY_EVEN                    USART_CR1_PCE                        /*!< Parity control enabled and Even Parity is selected */
+#define LL_USART_PARITY_ODD                     (USART_CR1_PCE | USART_CR1_PS)       /*!< Parity control enabled and Odd Parity is selected */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_WAKEUP Wakeup
+  * @{
+  */
+#define LL_USART_WAKEUP_IDLELINE                0x00000000U           /*!<  USART wake up from Mute mode on Idle Line */
+#define LL_USART_WAKEUP_ADDRESSMARK             USART_CR1_WAKE        /*!<  USART wake up from Mute mode on Address Mark */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_DATAWIDTH Datawidth
+  * @{
+  */
+#define LL_USART_DATAWIDTH_7B                   USART_CR1_M1            /*!< 7 bits word length : Start bit, 7 data bits, n stop bits */
+#define LL_USART_DATAWIDTH_8B                   0x00000000U             /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */
+#define LL_USART_DATAWIDTH_9B                   USART_CR1_M0            /*!< 9 bits word length : Start bit, 9 data bits, n stop bits */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_OVERSAMPLING Oversampling
+  * @{
+  */
+#define LL_USART_OVERSAMPLING_16                0x00000000U            /*!< Oversampling by 16 */
+#define LL_USART_OVERSAMPLING_8                 USART_CR1_OVER8        /*!< Oversampling by 8 */
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup USART_LL_EC_CLOCK Clock Signal
+  * @{
+  */
+
+#define LL_USART_CLOCK_DISABLE                  0x00000000U            /*!< Clock signal not provided */
+#define LL_USART_CLOCK_ENABLE                   USART_CR2_CLKEN        /*!< Clock signal provided */
+/**
+  * @}
+  */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/** @defgroup USART_LL_EC_LASTCLKPULSE Last Clock Pulse
+  * @{
+  */
+#define LL_USART_LASTCLKPULSE_NO_OUTPUT         0x00000000U           /*!< The clock pulse of the last data bit is not output to the SCLK pin */
+#define LL_USART_LASTCLKPULSE_OUTPUT            USART_CR2_LBCL        /*!< The clock pulse of the last data bit is output to the SCLK pin */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_PHASE Clock Phase
+  * @{
+  */
+#define LL_USART_PHASE_1EDGE                    0x00000000U           /*!< The first clock transition is the first data capture edge */
+#define LL_USART_PHASE_2EDGE                    USART_CR2_CPHA        /*!< The second clock transition is the first data capture edge */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_POLARITY Clock Polarity
+  * @{
+  */
+#define LL_USART_POLARITY_LOW                   0x00000000U           /*!< Steady low value on SCLK pin outside transmission window*/
+#define LL_USART_POLARITY_HIGH                  USART_CR2_CPOL        /*!< Steady high value on SCLK pin outside transmission window */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_PRESCALER Clock Source Prescaler
+  * @{
+  */
+#define LL_USART_PRESCALER_DIV1                 0x00000000U                                                                   /*!< Input clock not divided   */
+#define LL_USART_PRESCALER_DIV2                 (USART_PRESC_PRESCALER_0)                                                     /*!< Input clock divided by 2  */
+#define LL_USART_PRESCALER_DIV4                 (USART_PRESC_PRESCALER_1)                                                     /*!< Input clock divided by 4  */
+#define LL_USART_PRESCALER_DIV6                 (USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0)                           /*!< Input clock divided by 6  */
+#define LL_USART_PRESCALER_DIV8                 (USART_PRESC_PRESCALER_2)                                                     /*!< Input clock divided by 8  */
+#define LL_USART_PRESCALER_DIV10                (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_0)                           /*!< Input clock divided by 10 */
+#define LL_USART_PRESCALER_DIV12                (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1)                           /*!< Input clock divided by 12 */
+#define LL_USART_PRESCALER_DIV16                (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 16 */
+#define LL_USART_PRESCALER_DIV32                (USART_PRESC_PRESCALER_3)                                                     /*!< Input clock divided by 32 */
+#define LL_USART_PRESCALER_DIV64                (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_0)                           /*!< Input clock divided by 64 */
+#define LL_USART_PRESCALER_DIV128               (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1)                           /*!< Input clock divided by 128 */
+#define LL_USART_PRESCALER_DIV256               (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 256 */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_STOPBITS Stop Bits
+  * @{
+  */
+#define LL_USART_STOPBITS_0_5                   USART_CR2_STOP_0                           /*!< 0.5 stop bit */
+#define LL_USART_STOPBITS_1                     0x00000000U                                /*!< 1 stop bit */
+#define LL_USART_STOPBITS_1_5                   (USART_CR2_STOP_0 | USART_CR2_STOP_1)      /*!< 1.5 stop bits */
+#define LL_USART_STOPBITS_2                     USART_CR2_STOP_1                           /*!< 2 stop bits */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_TXRX TX RX Pins Swap
+  * @{
+  */
+#define LL_USART_TXRX_STANDARD                  0x00000000U           /*!< TX/RX pins are used as defined in standard pinout */
+#define LL_USART_TXRX_SWAPPED                   (USART_CR2_SWAP)      /*!< TX and RX pins functions are swapped.             */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_RXPIN_LEVEL RX Pin Active Level Inversion
+  * @{
+  */
+#define LL_USART_RXPIN_LEVEL_STANDARD           0x00000000U           /*!< RX pin signal works using the standard logic levels */
+#define LL_USART_RXPIN_LEVEL_INVERTED           (USART_CR2_RXINV)     /*!< RX pin signal values are inverted.                  */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_TXPIN_LEVEL TX Pin Active Level Inversion
+  * @{
+  */
+#define LL_USART_TXPIN_LEVEL_STANDARD           0x00000000U           /*!< TX pin signal works using the standard logic levels */
+#define LL_USART_TXPIN_LEVEL_INVERTED           (USART_CR2_TXINV)     /*!< TX pin signal values are inverted.                  */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_BINARY_LOGIC Binary Data Inversion
+  * @{
+  */
+#define LL_USART_BINARY_LOGIC_POSITIVE          0x00000000U           /*!< Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L) */
+#define LL_USART_BINARY_LOGIC_NEGATIVE          USART_CR2_DATAINV     /*!< Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The parity bit is also inverted. */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_BITORDER Bit Order
+  * @{
+  */
+#define LL_USART_BITORDER_LSBFIRST              0x00000000U           /*!< data is transmitted/received with data bit 0 first, following the start bit */
+#define LL_USART_BITORDER_MSBFIRST              USART_CR2_MSBFIRST    /*!< data is transmitted/received with the MSB first, following the start bit */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_AUTOBAUD_DETECT_ON Autobaud Detection
+  * @{
+  */
+#define LL_USART_AUTOBAUD_DETECT_ON_STARTBIT    0x00000000U                                 /*!< Measurement of the start bit is used to detect the baud rate */
+#define LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE USART_CR2_ABRMODE_0                         /*!< Falling edge to falling edge measurement. Received frame must start with a single bit = 1 -> Frame = Start10xxxxxx */
+#define LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME    USART_CR2_ABRMODE_1                         /*!< 0x7F frame detection */
+#define LL_USART_AUTOBAUD_DETECT_ON_55_FRAME    (USART_CR2_ABRMODE_1 | USART_CR2_ABRMODE_0) /*!< 0x55 frame detection */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_ADDRESS_DETECT Address Length Detection
+  * @{
+  */
+#define LL_USART_ADDRESS_DETECT_4B              0x00000000U           /*!< 4-bit address detection method selected */
+#define LL_USART_ADDRESS_DETECT_7B              USART_CR2_ADDM7       /*!< 7-bit address detection (in 8-bit data mode) method selected */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_HWCONTROL Hardware Control
+  * @{
+  */
+#define LL_USART_HWCONTROL_NONE                 0x00000000U                          /*!< CTS and RTS hardware flow control disabled */
+#define LL_USART_HWCONTROL_RTS                  USART_CR3_RTSE                       /*!< RTS output enabled, data is only requested when there is space in the receive buffer */
+#define LL_USART_HWCONTROL_CTS                  USART_CR3_CTSE                       /*!< CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0) */
+#define LL_USART_HWCONTROL_RTS_CTS              (USART_CR3_RTSE | USART_CR3_CTSE)    /*!< CTS and RTS hardware flow control enabled */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_WAKEUP_ON Wakeup Activation
+  * @{
+  */
+#define LL_USART_WAKEUP_ON_ADDRESS              0x00000000U                             /*!< Wake up active on address match */
+#define LL_USART_WAKEUP_ON_STARTBIT             USART_CR3_WUS_1                         /*!< Wake up active on Start bit detection */
+#define LL_USART_WAKEUP_ON_RXNE                 (USART_CR3_WUS_0 | USART_CR3_WUS_1)     /*!< Wake up active on RXNE */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_IRDA_POWER IrDA Power
+  * @{
+  */
+#define LL_USART_IRDA_POWER_NORMAL              0x00000000U           /*!< IrDA normal power mode */
+#define LL_USART_IRDA_POWER_LOW                 USART_CR3_IRLP        /*!< IrDA low power mode */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_LINBREAK_DETECT LIN Break Detection Length
+  * @{
+  */
+#define LL_USART_LINBREAK_DETECT_10B            0x00000000U           /*!< 10-bit break detection method selected */
+#define LL_USART_LINBREAK_DETECT_11B            USART_CR2_LBDL        /*!< 11-bit break detection method selected */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_DE_POLARITY Driver Enable Polarity
+  * @{
+  */
+#define LL_USART_DE_POLARITY_HIGH               0x00000000U           /*!< DE signal is active high */
+#define LL_USART_DE_POLARITY_LOW                USART_CR3_DEP         /*!< DE signal is active low */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_DMA_REG_DATA DMA Register Data
+  * @{
+  */
+#define LL_USART_DMA_REG_DATA_TRANSMIT          0x00000000U          /*!< Get address of data register used for transmission */
+#define LL_USART_DMA_REG_DATA_RECEIVE           0x00000001U          /*!< Get address of data register used for reception */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup USART_LL_Exported_Macros USART Exported Macros
+  * @{
+  */
+
+/** @defgroup USART_LL_EM_WRITE_READ Common Write and read registers Macros
+  * @{
+  */
+
+/**
+  * @brief  Write a value in USART register
+  * @param  __INSTANCE__ USART Instance
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_USART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in USART register
+  * @param  __INSTANCE__ USART Instance
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_USART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EM_Exported_Macros_Helper Exported_Macros_Helper
+  * @{
+  */
+
+/**
+  * @brief  Compute USARTDIV value according to Peripheral Clock and
+  *         expected Baud Rate in 8 bits sampling mode (32 bits value of USARTDIV is returned)
+  * @param  __PERIPHCLK__ Peripheral Clock frequency used for USART instance
+  * @param  __PRESCALER__ This parameter can be one of the following values:
+  *         @arg @ref LL_USART_PRESCALER_DIV1
+  *         @arg @ref LL_USART_PRESCALER_DIV2
+  *         @arg @ref LL_USART_PRESCALER_DIV4
+  *         @arg @ref LL_USART_PRESCALER_DIV6
+  *         @arg @ref LL_USART_PRESCALER_DIV8
+  *         @arg @ref LL_USART_PRESCALER_DIV10
+  *         @arg @ref LL_USART_PRESCALER_DIV12
+  *         @arg @ref LL_USART_PRESCALER_DIV16
+  *         @arg @ref LL_USART_PRESCALER_DIV32
+  *         @arg @ref LL_USART_PRESCALER_DIV64
+  *         @arg @ref LL_USART_PRESCALER_DIV128
+  *         @arg @ref LL_USART_PRESCALER_DIV256
+  * @param  __BAUDRATE__ Baud rate value to achieve
+  * @retval USARTDIV value to be used for BRR register filling in OverSampling_8 case
+  */
+#define __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) \
+  (((((__PERIPHCLK__)/(USART_PRESCALER_TAB[(__PRESCALER__)]))*2U)\
+    + ((__BAUDRATE__)/2U))/(__BAUDRATE__))
+
+/**
+  * @brief  Compute USARTDIV value according to Peripheral Clock and
+  *         expected Baud Rate in 16 bits sampling mode (32 bits value of USARTDIV is returned)
+  * @param  __PERIPHCLK__ Peripheral Clock frequency used for USART instance
+  * @param  __PRESCALER__ This parameter can be one of the following values:
+  *         @arg @ref LL_USART_PRESCALER_DIV1
+  *         @arg @ref LL_USART_PRESCALER_DIV2
+  *         @arg @ref LL_USART_PRESCALER_DIV4
+  *         @arg @ref LL_USART_PRESCALER_DIV6
+  *         @arg @ref LL_USART_PRESCALER_DIV8
+  *         @arg @ref LL_USART_PRESCALER_DIV10
+  *         @arg @ref LL_USART_PRESCALER_DIV12
+  *         @arg @ref LL_USART_PRESCALER_DIV16
+  *         @arg @ref LL_USART_PRESCALER_DIV32
+  *         @arg @ref LL_USART_PRESCALER_DIV64
+  *         @arg @ref LL_USART_PRESCALER_DIV128
+  *         @arg @ref LL_USART_PRESCALER_DIV256
+  * @param  __BAUDRATE__ Baud rate value to achieve
+  * @retval USARTDIV value to be used for BRR register filling in OverSampling_16 case
+  */
+#define __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) \
+  ((((__PERIPHCLK__)/(USART_PRESCALER_TAB[(__PRESCALER__)]))\
+    + ((__BAUDRATE__)/2U))/(__BAUDRATE__))
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup USART_LL_Exported_Functions USART Exported Functions
+  * @{
+  */
+
+/** @defgroup USART_LL_EF_Configuration Configuration functions
+  * @{
+  */
+
+/**
+  * @brief  USART Enable
+  * @rmtoll CR1          UE            LL_USART_Enable
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_Enable(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR1, USART_CR1_UE);
+}
+
+/**
+  * @brief  USART Disable (all USART prescalers and outputs are disabled)
+  * @note   When USART is disabled, USART prescalers and outputs are stopped immediately,
+  *         and current operations are discarded. The configuration of the USART is kept, but all the status
+  *         flags, in the USARTx_ISR are set to their default values.
+  * @rmtoll CR1          UE            LL_USART_Disable
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_Disable(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR1, USART_CR1_UE);
+}
+
+/**
+  * @brief  Indicate if USART is enabled
+  * @rmtoll CR1          UE            LL_USART_IsEnabled
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabled(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR1, USART_CR1_UE) == (USART_CR1_UE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  FIFO Mode Enable
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR1          FIFOEN        LL_USART_EnableFIFO
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableFIFO(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR1, USART_CR1_FIFOEN);
+}
+
+/**
+  * @brief  FIFO Mode Disable
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR1          FIFOEN        LL_USART_DisableFIFO
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableFIFO(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR1, USART_CR1_FIFOEN);
+}
+
+/**
+  * @brief  Indicate if FIFO Mode is enabled
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR1          FIFOEN        LL_USART_IsEnabledFIFO
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledFIFO(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR1, USART_CR1_FIFOEN) == (USART_CR1_FIFOEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Configure TX FIFO Threshold
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR3          TXFTCFG       LL_USART_SetTXFIFOThreshold
+  * @param  USARTx USART Instance
+  * @param  Threshold This parameter can be one of the following values:
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_8
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_4
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_2
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_3_4
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_7_8
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_8_8
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetTXFIFOThreshold(USART_TypeDef *USARTx, uint32_t Threshold)
+{
+  ATOMIC_MODIFY_REG(USARTx->CR3, USART_CR3_TXFTCFG, Threshold << USART_CR3_TXFTCFG_Pos);
+}
+
+/**
+  * @brief  Return TX FIFO Threshold Configuration
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR3          TXFTCFG       LL_USART_GetTXFIFOThreshold
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_8
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_4
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_2
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_3_4
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_7_8
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_8_8
+  */
+__STATIC_INLINE uint32_t LL_USART_GetTXFIFOThreshold(const USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos);
+}
+
+/**
+  * @brief  Configure RX FIFO Threshold
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR3          RXFTCFG       LL_USART_SetRXFIFOThreshold
+  * @param  USARTx USART Instance
+  * @param  Threshold This parameter can be one of the following values:
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_8
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_4
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_2
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_3_4
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_7_8
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_8_8
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetRXFIFOThreshold(USART_TypeDef *USARTx, uint32_t Threshold)
+{
+  ATOMIC_MODIFY_REG(USARTx->CR3, USART_CR3_RXFTCFG, Threshold << USART_CR3_RXFTCFG_Pos);
+}
+
+/**
+  * @brief  Return RX FIFO Threshold Configuration
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR3          RXFTCFG       LL_USART_GetRXFIFOThreshold
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_8
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_4
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_2
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_3_4
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_7_8
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_8_8
+  */
+__STATIC_INLINE uint32_t LL_USART_GetRXFIFOThreshold(const USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos);
+}
+
+/**
+  * @brief  Configure TX and RX FIFOs Threshold
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR3          TXFTCFG       LL_USART_ConfigFIFOsThreshold\n
+  *         CR3          RXFTCFG       LL_USART_ConfigFIFOsThreshold
+  * @param  USARTx USART Instance
+  * @param  TXThreshold This parameter can be one of the following values:
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_8
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_4
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_2
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_3_4
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_7_8
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_8_8
+  * @param  RXThreshold This parameter can be one of the following values:
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_8
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_4
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_2
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_3_4
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_7_8
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_8_8
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ConfigFIFOsThreshold(USART_TypeDef *USARTx, uint32_t TXThreshold, uint32_t RXThreshold)
+{
+  ATOMIC_MODIFY_REG(USARTx->CR3, USART_CR3_TXFTCFG | USART_CR3_RXFTCFG, (TXThreshold << USART_CR3_TXFTCFG_Pos) |
+                    (RXThreshold << USART_CR3_RXFTCFG_Pos));
+}
+
+/**
+  * @brief  USART enabled in STOP Mode.
+  * @note   When this function is enabled, USART is able to wake up the MCU from Stop mode, provided that
+  *         USART clock selection is HSI or LSE in RCC.
+  * @note   Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+  *         Wake-up from Stop mode feature is supported by the USARTx instance.
+  * @rmtoll CR1          UESM          LL_USART_EnableInStopMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableInStopMode(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_UESM);
+}
+
+/**
+  * @brief  USART disabled in STOP Mode.
+  * @note   When this function is disabled, USART is not able to wake up the MCU from Stop mode
+  * @note   Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+  *         Wake-up from Stop mode feature is supported by the USARTx instance.
+  * @rmtoll CR1          UESM          LL_USART_DisableInStopMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableInStopMode(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_UESM);
+}
+
+/**
+  * @brief  Indicate if USART is enabled in STOP Mode (able to wake up MCU from Stop mode or not)
+  * @note   Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+  *         Wake-up from Stop mode feature is supported by the USARTx instance.
+  * @rmtoll CR1          UESM          LL_USART_IsEnabledInStopMode
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledInStopMode(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR1, USART_CR1_UESM) == (USART_CR1_UESM)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Receiver Enable (Receiver is enabled and begins searching for a start bit)
+  * @rmtoll CR1          RE            LL_USART_EnableDirectionRx
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableDirectionRx(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RE);
+}
+
+/**
+  * @brief  Receiver Disable
+  * @rmtoll CR1          RE            LL_USART_DisableDirectionRx
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableDirectionRx(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RE);
+}
+
+/**
+  * @brief  Transmitter Enable
+  * @rmtoll CR1          TE            LL_USART_EnableDirectionTx
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableDirectionTx(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TE);
+}
+
+/**
+  * @brief  Transmitter Disable
+  * @rmtoll CR1          TE            LL_USART_DisableDirectionTx
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableDirectionTx(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TE);
+}
+
+/**
+  * @brief  Configure simultaneously enabled/disabled states
+  *         of Transmitter and Receiver
+  * @rmtoll CR1          RE            LL_USART_SetTransferDirection\n
+  *         CR1          TE            LL_USART_SetTransferDirection
+  * @param  USARTx USART Instance
+  * @param  TransferDirection This parameter can be one of the following values:
+  *         @arg @ref LL_USART_DIRECTION_NONE
+  *         @arg @ref LL_USART_DIRECTION_RX
+  *         @arg @ref LL_USART_DIRECTION_TX
+  *         @arg @ref LL_USART_DIRECTION_TX_RX
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetTransferDirection(USART_TypeDef *USARTx, uint32_t TransferDirection)
+{
+  ATOMIC_MODIFY_REG(USARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection);
+}
+
+/**
+  * @brief  Return enabled/disabled states of Transmitter and Receiver
+  * @rmtoll CR1          RE            LL_USART_GetTransferDirection\n
+  *         CR1          TE            LL_USART_GetTransferDirection
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_DIRECTION_NONE
+  *         @arg @ref LL_USART_DIRECTION_RX
+  *         @arg @ref LL_USART_DIRECTION_TX
+  *         @arg @ref LL_USART_DIRECTION_TX_RX
+  */
+__STATIC_INLINE uint32_t LL_USART_GetTransferDirection(const USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_RE | USART_CR1_TE));
+}
+
+/**
+  * @brief  Configure Parity (enabled/disabled and parity mode if enabled).
+  * @note   This function selects if hardware parity control (generation and detection) is enabled or disabled.
+  *         When the parity control is enabled (Odd or Even), computed parity bit is inserted at the MSB position
+  *         (9th or 8th bit depending on data width) and parity is checked on the received data.
+  * @rmtoll CR1          PS            LL_USART_SetParity\n
+  *         CR1          PCE           LL_USART_SetParity
+  * @param  USARTx USART Instance
+  * @param  Parity This parameter can be one of the following values:
+  *         @arg @ref LL_USART_PARITY_NONE
+  *         @arg @ref LL_USART_PARITY_EVEN
+  *         @arg @ref LL_USART_PARITY_ODD
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetParity(USART_TypeDef *USARTx, uint32_t Parity)
+{
+  MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE, Parity);
+}
+
+/**
+  * @brief  Return Parity configuration (enabled/disabled and parity mode if enabled)
+  * @rmtoll CR1          PS            LL_USART_GetParity\n
+  *         CR1          PCE           LL_USART_GetParity
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_PARITY_NONE
+  *         @arg @ref LL_USART_PARITY_EVEN
+  *         @arg @ref LL_USART_PARITY_ODD
+  */
+__STATIC_INLINE uint32_t LL_USART_GetParity(const USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE));
+}
+
+/**
+  * @brief  Set Receiver Wake Up method from Mute mode.
+  * @rmtoll CR1          WAKE          LL_USART_SetWakeUpMethod
+  * @param  USARTx USART Instance
+  * @param  Method This parameter can be one of the following values:
+  *         @arg @ref LL_USART_WAKEUP_IDLELINE
+  *         @arg @ref LL_USART_WAKEUP_ADDRESSMARK
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetWakeUpMethod(USART_TypeDef *USARTx, uint32_t Method)
+{
+  MODIFY_REG(USARTx->CR1, USART_CR1_WAKE, Method);
+}
+
+/**
+  * @brief  Return Receiver Wake Up method from Mute mode
+  * @rmtoll CR1          WAKE          LL_USART_GetWakeUpMethod
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_WAKEUP_IDLELINE
+  *         @arg @ref LL_USART_WAKEUP_ADDRESSMARK
+  */
+__STATIC_INLINE uint32_t LL_USART_GetWakeUpMethod(const USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_WAKE));
+}
+
+/**
+  * @brief  Set Word length (i.e. nb of data bits, excluding start and stop bits)
+  * @rmtoll CR1          M0            LL_USART_SetDataWidth\n
+  *         CR1          M1            LL_USART_SetDataWidth
+  * @param  USARTx USART Instance
+  * @param  DataWidth This parameter can be one of the following values:
+  *         @arg @ref LL_USART_DATAWIDTH_7B
+  *         @arg @ref LL_USART_DATAWIDTH_8B
+  *         @arg @ref LL_USART_DATAWIDTH_9B
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetDataWidth(USART_TypeDef *USARTx, uint32_t DataWidth)
+{
+  MODIFY_REG(USARTx->CR1, USART_CR1_M, DataWidth);
+}
+
+/**
+  * @brief  Return Word length (i.e. nb of data bits, excluding start and stop bits)
+  * @rmtoll CR1          M0            LL_USART_GetDataWidth\n
+  *         CR1          M1            LL_USART_GetDataWidth
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_DATAWIDTH_7B
+  *         @arg @ref LL_USART_DATAWIDTH_8B
+  *         @arg @ref LL_USART_DATAWIDTH_9B
+  */
+__STATIC_INLINE uint32_t LL_USART_GetDataWidth(const USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_M));
+}
+
+/**
+  * @brief  Allow switch between Mute Mode and Active mode
+  * @rmtoll CR1          MME           LL_USART_EnableMuteMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableMuteMode(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_MME);
+}
+
+/**
+  * @brief  Prevent Mute Mode use. Set Receiver in active mode permanently.
+  * @rmtoll CR1          MME           LL_USART_DisableMuteMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableMuteMode(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_MME);
+}
+
+/**
+  * @brief  Indicate if switch between Mute Mode and Active mode is allowed
+  * @rmtoll CR1          MME           LL_USART_IsEnabledMuteMode
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledMuteMode(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR1, USART_CR1_MME) == (USART_CR1_MME)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set Oversampling to 8-bit or 16-bit mode
+  * @rmtoll CR1          OVER8         LL_USART_SetOverSampling
+  * @param  USARTx USART Instance
+  * @param  OverSampling This parameter can be one of the following values:
+  *         @arg @ref LL_USART_OVERSAMPLING_16
+  *         @arg @ref LL_USART_OVERSAMPLING_8
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetOverSampling(USART_TypeDef *USARTx, uint32_t OverSampling)
+{
+  MODIFY_REG(USARTx->CR1, USART_CR1_OVER8, OverSampling);
+}
+
+/**
+  * @brief  Return Oversampling mode
+  * @rmtoll CR1          OVER8         LL_USART_GetOverSampling
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_OVERSAMPLING_16
+  *         @arg @ref LL_USART_OVERSAMPLING_8
+  */
+__STATIC_INLINE uint32_t LL_USART_GetOverSampling(const USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_OVER8));
+}
+
+/**
+  * @brief  Configure if Clock pulse of the last data bit is output to the SCLK pin or not
+  * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
+  *         Synchronous mode is supported by the USARTx instance.
+  * @rmtoll CR2          LBCL          LL_USART_SetLastClkPulseOutput
+  * @param  USARTx USART Instance
+  * @param  LastBitClockPulse This parameter can be one of the following values:
+  *         @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT
+  *         @arg @ref LL_USART_LASTCLKPULSE_OUTPUT
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetLastClkPulseOutput(USART_TypeDef *USARTx, uint32_t LastBitClockPulse)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_LBCL, LastBitClockPulse);
+}
+
+/**
+  * @brief  Retrieve Clock pulse of the last data bit output configuration
+  *         (Last bit Clock pulse output to the SCLK pin or not)
+  * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
+  *         Synchronous mode is supported by the USARTx instance.
+  * @rmtoll CR2          LBCL          LL_USART_GetLastClkPulseOutput
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT
+  *         @arg @ref LL_USART_LASTCLKPULSE_OUTPUT
+  */
+__STATIC_INLINE uint32_t LL_USART_GetLastClkPulseOutput(const USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBCL));
+}
+
+/**
+  * @brief  Select the phase of the clock output on the SCLK pin in synchronous mode
+  * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
+  *         Synchronous mode is supported by the USARTx instance.
+  * @rmtoll CR2          CPHA          LL_USART_SetClockPhase
+  * @param  USARTx USART Instance
+  * @param  ClockPhase This parameter can be one of the following values:
+  *         @arg @ref LL_USART_PHASE_1EDGE
+  *         @arg @ref LL_USART_PHASE_2EDGE
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetClockPhase(USART_TypeDef *USARTx, uint32_t ClockPhase)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_CPHA, ClockPhase);
+}
+
+/**
+  * @brief  Return phase of the clock output on the SCLK pin in synchronous mode
+  * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
+  *         Synchronous mode is supported by the USARTx instance.
+  * @rmtoll CR2          CPHA          LL_USART_GetClockPhase
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_PHASE_1EDGE
+  *         @arg @ref LL_USART_PHASE_2EDGE
+  */
+__STATIC_INLINE uint32_t LL_USART_GetClockPhase(const USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPHA));
+}
+
+/**
+  * @brief  Select the polarity of the clock output on the SCLK pin in synchronous mode
+  * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
+  *         Synchronous mode is supported by the USARTx instance.
+  * @rmtoll CR2          CPOL          LL_USART_SetClockPolarity
+  * @param  USARTx USART Instance
+  * @param  ClockPolarity This parameter can be one of the following values:
+  *         @arg @ref LL_USART_POLARITY_LOW
+  *         @arg @ref LL_USART_POLARITY_HIGH
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetClockPolarity(USART_TypeDef *USARTx, uint32_t ClockPolarity)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_CPOL, ClockPolarity);
+}
+
+/**
+  * @brief  Return polarity of the clock output on the SCLK pin in synchronous mode
+  * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
+  *         Synchronous mode is supported by the USARTx instance.
+  * @rmtoll CR2          CPOL          LL_USART_GetClockPolarity
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_POLARITY_LOW
+  *         @arg @ref LL_USART_POLARITY_HIGH
+  */
+__STATIC_INLINE uint32_t LL_USART_GetClockPolarity(const USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPOL));
+}
+
+/**
+  * @brief  Configure Clock signal format (Phase Polarity and choice about output of last bit clock pulse)
+  * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
+  *         Synchronous mode is supported by the USARTx instance.
+  * @note   Call of this function is equivalent to following function call sequence :
+  *         - Clock Phase configuration using @ref LL_USART_SetClockPhase() function
+  *         - Clock Polarity configuration using @ref LL_USART_SetClockPolarity() function
+  *         - Output of Last bit Clock pulse configuration using @ref LL_USART_SetLastClkPulseOutput() function
+  * @rmtoll CR2          CPHA          LL_USART_ConfigClock\n
+  *         CR2          CPOL          LL_USART_ConfigClock\n
+  *         CR2          LBCL          LL_USART_ConfigClock
+  * @param  USARTx USART Instance
+  * @param  Phase This parameter can be one of the following values:
+  *         @arg @ref LL_USART_PHASE_1EDGE
+  *         @arg @ref LL_USART_PHASE_2EDGE
+  * @param  Polarity This parameter can be one of the following values:
+  *         @arg @ref LL_USART_POLARITY_LOW
+  *         @arg @ref LL_USART_POLARITY_HIGH
+  * @param  LBCPOutput This parameter can be one of the following values:
+  *         @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT
+  *         @arg @ref LL_USART_LASTCLKPULSE_OUTPUT
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ConfigClock(USART_TypeDef *USARTx, uint32_t Phase, uint32_t Polarity, uint32_t LBCPOutput)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL, Phase | Polarity | LBCPOutput);
+}
+
+/**
+  * @brief  Configure Clock source prescaler for baudrate generator and oversampling
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll PRESC        PRESCALER     LL_USART_SetPrescaler
+  * @param  USARTx USART Instance
+  * @param  PrescalerValue This parameter can be one of the following values:
+  *         @arg @ref LL_USART_PRESCALER_DIV1
+  *         @arg @ref LL_USART_PRESCALER_DIV2
+  *         @arg @ref LL_USART_PRESCALER_DIV4
+  *         @arg @ref LL_USART_PRESCALER_DIV6
+  *         @arg @ref LL_USART_PRESCALER_DIV8
+  *         @arg @ref LL_USART_PRESCALER_DIV10
+  *         @arg @ref LL_USART_PRESCALER_DIV12
+  *         @arg @ref LL_USART_PRESCALER_DIV16
+  *         @arg @ref LL_USART_PRESCALER_DIV32
+  *         @arg @ref LL_USART_PRESCALER_DIV64
+  *         @arg @ref LL_USART_PRESCALER_DIV128
+  *         @arg @ref LL_USART_PRESCALER_DIV256
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue)
+{
+  MODIFY_REG(USARTx->PRESC, USART_PRESC_PRESCALER, (uint16_t)PrescalerValue);
+}
+
+/**
+  * @brief  Retrieve the Clock source prescaler for baudrate generator and oversampling
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll PRESC        PRESCALER     LL_USART_GetPrescaler
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_PRESCALER_DIV1
+  *         @arg @ref LL_USART_PRESCALER_DIV2
+  *         @arg @ref LL_USART_PRESCALER_DIV4
+  *         @arg @ref LL_USART_PRESCALER_DIV6
+  *         @arg @ref LL_USART_PRESCALER_DIV8
+  *         @arg @ref LL_USART_PRESCALER_DIV10
+  *         @arg @ref LL_USART_PRESCALER_DIV12
+  *         @arg @ref LL_USART_PRESCALER_DIV16
+  *         @arg @ref LL_USART_PRESCALER_DIV32
+  *         @arg @ref LL_USART_PRESCALER_DIV64
+  *         @arg @ref LL_USART_PRESCALER_DIV128
+  *         @arg @ref LL_USART_PRESCALER_DIV256
+  */
+__STATIC_INLINE uint32_t LL_USART_GetPrescaler(const USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->PRESC, USART_PRESC_PRESCALER));
+}
+
+/**
+  * @brief  Enable Clock output on SCLK pin
+  * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
+  *         Synchronous mode is supported by the USARTx instance.
+  * @rmtoll CR2          CLKEN         LL_USART_EnableSCLKOutput
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableSCLKOutput(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR2, USART_CR2_CLKEN);
+}
+
+/**
+  * @brief  Disable Clock output on SCLK pin
+  * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
+  *         Synchronous mode is supported by the USARTx instance.
+  * @rmtoll CR2          CLKEN         LL_USART_DisableSCLKOutput
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableSCLKOutput(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR2, USART_CR2_CLKEN);
+}
+
+/**
+  * @brief  Indicate if Clock output on SCLK pin is enabled
+  * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
+  *         Synchronous mode is supported by the USARTx instance.
+  * @rmtoll CR2          CLKEN         LL_USART_IsEnabledSCLKOutput
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledSCLKOutput(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR2, USART_CR2_CLKEN) == (USART_CR2_CLKEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set the length of the stop bits
+  * @rmtoll CR2          STOP          LL_USART_SetStopBitsLength
+  * @param  USARTx USART Instance
+  * @param  StopBits This parameter can be one of the following values:
+  *         @arg @ref LL_USART_STOPBITS_0_5
+  *         @arg @ref LL_USART_STOPBITS_1
+  *         @arg @ref LL_USART_STOPBITS_1_5
+  *         @arg @ref LL_USART_STOPBITS_2
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetStopBitsLength(USART_TypeDef *USARTx, uint32_t StopBits)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits);
+}
+
+/**
+  * @brief  Retrieve the length of the stop bits
+  * @rmtoll CR2          STOP          LL_USART_GetStopBitsLength
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_STOPBITS_0_5
+  *         @arg @ref LL_USART_STOPBITS_1
+  *         @arg @ref LL_USART_STOPBITS_1_5
+  *         @arg @ref LL_USART_STOPBITS_2
+  */
+__STATIC_INLINE uint32_t LL_USART_GetStopBitsLength(const USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_STOP));
+}
+
+/**
+  * @brief  Configure Character frame format (Datawidth, Parity control, Stop Bits)
+  * @note   Call of this function is equivalent to following function call sequence :
+  *         - Data Width configuration using @ref LL_USART_SetDataWidth() function
+  *         - Parity Control and mode configuration using @ref LL_USART_SetParity() function
+  *         - Stop bits configuration using @ref LL_USART_SetStopBitsLength() function
+  * @rmtoll CR1          PS            LL_USART_ConfigCharacter\n
+  *         CR1          PCE           LL_USART_ConfigCharacter\n
+  *         CR1          M0            LL_USART_ConfigCharacter\n
+  *         CR1          M1            LL_USART_ConfigCharacter\n
+  *         CR2          STOP          LL_USART_ConfigCharacter
+  * @param  USARTx USART Instance
+  * @param  DataWidth This parameter can be one of the following values:
+  *         @arg @ref LL_USART_DATAWIDTH_7B
+  *         @arg @ref LL_USART_DATAWIDTH_8B
+  *         @arg @ref LL_USART_DATAWIDTH_9B
+  * @param  Parity This parameter can be one of the following values:
+  *         @arg @ref LL_USART_PARITY_NONE
+  *         @arg @ref LL_USART_PARITY_EVEN
+  *         @arg @ref LL_USART_PARITY_ODD
+  * @param  StopBits This parameter can be one of the following values:
+  *         @arg @ref LL_USART_STOPBITS_0_5
+  *         @arg @ref LL_USART_STOPBITS_1
+  *         @arg @ref LL_USART_STOPBITS_1_5
+  *         @arg @ref LL_USART_STOPBITS_2
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ConfigCharacter(USART_TypeDef *USARTx, uint32_t DataWidth, uint32_t Parity,
+                                              uint32_t StopBits)
+{
+  MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE | USART_CR1_M, Parity | DataWidth);
+  MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits);
+}
+
+/**
+  * @brief  Configure TX/RX pins swapping setting.
+  * @rmtoll CR2          SWAP          LL_USART_SetTXRXSwap
+  * @param  USARTx USART Instance
+  * @param  SwapConfig This parameter can be one of the following values:
+  *         @arg @ref LL_USART_TXRX_STANDARD
+  *         @arg @ref LL_USART_TXRX_SWAPPED
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetTXRXSwap(USART_TypeDef *USARTx, uint32_t SwapConfig)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_SWAP, SwapConfig);
+}
+
+/**
+  * @brief  Retrieve TX/RX pins swapping configuration.
+  * @rmtoll CR2          SWAP          LL_USART_GetTXRXSwap
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_TXRX_STANDARD
+  *         @arg @ref LL_USART_TXRX_SWAPPED
+  */
+__STATIC_INLINE uint32_t LL_USART_GetTXRXSwap(const USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_SWAP));
+}
+
+/**
+  * @brief  Configure RX pin active level logic
+  * @rmtoll CR2          RXINV         LL_USART_SetRXPinLevel
+  * @param  USARTx USART Instance
+  * @param  PinInvMethod This parameter can be one of the following values:
+  *         @arg @ref LL_USART_RXPIN_LEVEL_STANDARD
+  *         @arg @ref LL_USART_RXPIN_LEVEL_INVERTED
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetRXPinLevel(USART_TypeDef *USARTx, uint32_t PinInvMethod)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_RXINV, PinInvMethod);
+}
+
+/**
+  * @brief  Retrieve RX pin active level logic configuration
+  * @rmtoll CR2          RXINV         LL_USART_GetRXPinLevel
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_RXPIN_LEVEL_STANDARD
+  *         @arg @ref LL_USART_RXPIN_LEVEL_INVERTED
+  */
+__STATIC_INLINE uint32_t LL_USART_GetRXPinLevel(const USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_RXINV));
+}
+
+/**
+  * @brief  Configure TX pin active level logic
+  * @rmtoll CR2          TXINV         LL_USART_SetTXPinLevel
+  * @param  USARTx USART Instance
+  * @param  PinInvMethod This parameter can be one of the following values:
+  *         @arg @ref LL_USART_TXPIN_LEVEL_STANDARD
+  *         @arg @ref LL_USART_TXPIN_LEVEL_INVERTED
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetTXPinLevel(USART_TypeDef *USARTx, uint32_t PinInvMethod)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_TXINV, PinInvMethod);
+}
+
+/**
+  * @brief  Retrieve TX pin active level logic configuration
+  * @rmtoll CR2          TXINV         LL_USART_GetTXPinLevel
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_TXPIN_LEVEL_STANDARD
+  *         @arg @ref LL_USART_TXPIN_LEVEL_INVERTED
+  */
+__STATIC_INLINE uint32_t LL_USART_GetTXPinLevel(const USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_TXINV));
+}
+
+/**
+  * @brief  Configure Binary data logic.
+  * @note   Allow to define how Logical data from the data register are send/received :
+  *         either in positive/direct logic (1=H, 0=L) or in negative/inverse logic (1=L, 0=H)
+  * @rmtoll CR2          DATAINV       LL_USART_SetBinaryDataLogic
+  * @param  USARTx USART Instance
+  * @param  DataLogic This parameter can be one of the following values:
+  *         @arg @ref LL_USART_BINARY_LOGIC_POSITIVE
+  *         @arg @ref LL_USART_BINARY_LOGIC_NEGATIVE
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetBinaryDataLogic(USART_TypeDef *USARTx, uint32_t DataLogic)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_DATAINV, DataLogic);
+}
+
+/**
+  * @brief  Retrieve Binary data configuration
+  * @rmtoll CR2          DATAINV       LL_USART_GetBinaryDataLogic
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_BINARY_LOGIC_POSITIVE
+  *         @arg @ref LL_USART_BINARY_LOGIC_NEGATIVE
+  */
+__STATIC_INLINE uint32_t LL_USART_GetBinaryDataLogic(const USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_DATAINV));
+}
+
+/**
+  * @brief  Configure transfer bit order (either Less or Most Significant Bit First)
+  * @note   MSB First means data is transmitted/received with the MSB first, following the start bit.
+  *         LSB First means data is transmitted/received with data bit 0 first, following the start bit.
+  * @rmtoll CR2          MSBFIRST      LL_USART_SetTransferBitOrder
+  * @param  USARTx USART Instance
+  * @param  BitOrder This parameter can be one of the following values:
+  *         @arg @ref LL_USART_BITORDER_LSBFIRST
+  *         @arg @ref LL_USART_BITORDER_MSBFIRST
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetTransferBitOrder(USART_TypeDef *USARTx, uint32_t BitOrder)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_MSBFIRST, BitOrder);
+}
+
+/**
+  * @brief  Return transfer bit order (either Less or Most Significant Bit First)
+  * @note   MSB First means data is transmitted/received with the MSB first, following the start bit.
+  *         LSB First means data is transmitted/received with data bit 0 first, following the start bit.
+  * @rmtoll CR2          MSBFIRST      LL_USART_GetTransferBitOrder
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_BITORDER_LSBFIRST
+  *         @arg @ref LL_USART_BITORDER_MSBFIRST
+  */
+__STATIC_INLINE uint32_t LL_USART_GetTransferBitOrder(const USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_MSBFIRST));
+}
+
+/**
+  * @brief  Enable Auto Baud-Rate Detection
+  * @note   Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
+  *         Auto Baud Rate detection feature is supported by the USARTx instance.
+  * @rmtoll CR2          ABREN         LL_USART_EnableAutoBaudRate
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableAutoBaudRate(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR2, USART_CR2_ABREN);
+}
+
+/**
+  * @brief  Disable Auto Baud-Rate Detection
+  * @note   Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
+  *         Auto Baud Rate detection feature is supported by the USARTx instance.
+  * @rmtoll CR2          ABREN         LL_USART_DisableAutoBaudRate
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableAutoBaudRate(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR2, USART_CR2_ABREN);
+}
+
+/**
+  * @brief  Indicate if Auto Baud-Rate Detection mechanism is enabled
+  * @note   Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
+  *         Auto Baud Rate detection feature is supported by the USARTx instance.
+  * @rmtoll CR2          ABREN         LL_USART_IsEnabledAutoBaud
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledAutoBaud(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR2, USART_CR2_ABREN) == (USART_CR2_ABREN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set Auto Baud-Rate mode bits
+  * @note   Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
+  *         Auto Baud Rate detection feature is supported by the USARTx instance.
+  * @rmtoll CR2          ABRMODE       LL_USART_SetAutoBaudRateMode
+  * @param  USARTx USART Instance
+  * @param  AutoBaudRateMode This parameter can be one of the following values:
+  *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_STARTBIT
+  *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE
+  *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME
+  *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_55_FRAME
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetAutoBaudRateMode(USART_TypeDef *USARTx, uint32_t AutoBaudRateMode)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_ABRMODE, AutoBaudRateMode);
+}
+
+/**
+  * @brief  Return Auto Baud-Rate mode
+  * @note   Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
+  *         Auto Baud Rate detection feature is supported by the USARTx instance.
+  * @rmtoll CR2          ABRMODE       LL_USART_GetAutoBaudRateMode
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_STARTBIT
+  *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE
+  *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME
+  *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_55_FRAME
+  */
+__STATIC_INLINE uint32_t LL_USART_GetAutoBaudRateMode(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ABRMODE));
+}
+
+/**
+  * @brief  Enable Receiver Timeout
+  * @rmtoll CR2          RTOEN         LL_USART_EnableRxTimeout
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableRxTimeout(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR2, USART_CR2_RTOEN);
+}
+
+/**
+  * @brief  Disable Receiver Timeout
+  * @rmtoll CR2          RTOEN         LL_USART_DisableRxTimeout
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableRxTimeout(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR2, USART_CR2_RTOEN);
+}
+
+/**
+  * @brief  Indicate if Receiver Timeout feature is enabled
+  * @rmtoll CR2          RTOEN         LL_USART_IsEnabledRxTimeout
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledRxTimeout(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR2, USART_CR2_RTOEN) == (USART_CR2_RTOEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set Address of the USART node.
+  * @note   This is used in multiprocessor communication during Mute mode or Stop mode,
+  *         for wake up with address mark detection.
+  * @note   4bits address node is used when 4-bit Address Detection is selected in ADDM7.
+  *         (b7-b4 should be set to 0)
+  *         8bits address node is used when 7-bit Address Detection is selected in ADDM7.
+  *         (This is used in multiprocessor communication during Mute mode or Stop mode,
+  *         for wake up with 7-bit address mark detection.
+  *         The MSB of the character sent by the transmitter should be equal to 1.
+  *         It may also be used for character detection during normal reception,
+  *         Mute mode inactive (for example, end of block detection in ModBus protocol).
+  *         In this case, the whole received character (8-bit) is compared to the ADD[7:0]
+  *         value and CMF flag is set on match)
+  * @rmtoll CR2          ADD           LL_USART_ConfigNodeAddress\n
+  *         CR2          ADDM7         LL_USART_ConfigNodeAddress
+  * @param  USARTx USART Instance
+  * @param  AddressLen This parameter can be one of the following values:
+  *         @arg @ref LL_USART_ADDRESS_DETECT_4B
+  *         @arg @ref LL_USART_ADDRESS_DETECT_7B
+  * @param  NodeAddress 4 or 7 bit Address of the USART node.
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ConfigNodeAddress(USART_TypeDef *USARTx, uint32_t AddressLen, uint32_t NodeAddress)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_ADD | USART_CR2_ADDM7,
+             (uint32_t)(AddressLen | (NodeAddress << USART_CR2_ADD_Pos)));
+}
+
+/**
+  * @brief  Return 8 bit Address of the USART node as set in ADD field of CR2.
+  * @note   If 4-bit Address Detection is selected in ADDM7,
+  *         only 4bits (b3-b0) of returned value are relevant (b31-b4 are not relevant)
+  *         If 7-bit Address Detection is selected in ADDM7,
+  *         only 8bits (b7-b0) of returned value are relevant (b31-b8 are not relevant)
+  * @rmtoll CR2          ADD           LL_USART_GetNodeAddress
+  * @param  USARTx USART Instance
+  * @retval Address of the USART node (Value between Min_Data=0 and Max_Data=255)
+  */
+__STATIC_INLINE uint32_t LL_USART_GetNodeAddress(const USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADD) >> USART_CR2_ADD_Pos);
+}
+
+/**
+  * @brief  Return Length of Node Address used in Address Detection mode (7-bit or 4-bit)
+  * @rmtoll CR2          ADDM7         LL_USART_GetNodeAddressLen
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_ADDRESS_DETECT_4B
+  *         @arg @ref LL_USART_ADDRESS_DETECT_7B
+  */
+__STATIC_INLINE uint32_t LL_USART_GetNodeAddressLen(const USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADDM7));
+}
+
+/**
+  * @brief  Enable RTS HW Flow Control
+  * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll CR3          RTSE          LL_USART_EnableRTSHWFlowCtrl
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableRTSHWFlowCtrl(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_RTSE);
+}
+
+/**
+  * @brief  Disable RTS HW Flow Control
+  * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll CR3          RTSE          LL_USART_DisableRTSHWFlowCtrl
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableRTSHWFlowCtrl(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_RTSE);
+}
+
+/**
+  * @brief  Enable CTS HW Flow Control
+  * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll CR3          CTSE          LL_USART_EnableCTSHWFlowCtrl
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableCTSHWFlowCtrl(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_CTSE);
+}
+
+/**
+  * @brief  Disable CTS HW Flow Control
+  * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll CR3          CTSE          LL_USART_DisableCTSHWFlowCtrl
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableCTSHWFlowCtrl(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_CTSE);
+}
+
+/**
+  * @brief  Configure HW Flow Control mode (both CTS and RTS)
+  * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll CR3          RTSE          LL_USART_SetHWFlowCtrl\n
+  *         CR3          CTSE          LL_USART_SetHWFlowCtrl
+  * @param  USARTx USART Instance
+  * @param  HardwareFlowControl This parameter can be one of the following values:
+  *         @arg @ref LL_USART_HWCONTROL_NONE
+  *         @arg @ref LL_USART_HWCONTROL_RTS
+  *         @arg @ref LL_USART_HWCONTROL_CTS
+  *         @arg @ref LL_USART_HWCONTROL_RTS_CTS
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetHWFlowCtrl(USART_TypeDef *USARTx, uint32_t HardwareFlowControl)
+{
+  MODIFY_REG(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE, HardwareFlowControl);
+}
+
+/**
+  * @brief  Return HW Flow Control configuration (both CTS and RTS)
+  * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll CR3          RTSE          LL_USART_GetHWFlowCtrl\n
+  *         CR3          CTSE          LL_USART_GetHWFlowCtrl
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_HWCONTROL_NONE
+  *         @arg @ref LL_USART_HWCONTROL_RTS
+  *         @arg @ref LL_USART_HWCONTROL_CTS
+  *         @arg @ref LL_USART_HWCONTROL_RTS_CTS
+  */
+__STATIC_INLINE uint32_t LL_USART_GetHWFlowCtrl(const USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE));
+}
+
+/**
+  * @brief  Enable One bit sampling method
+  * @rmtoll CR3          ONEBIT        LL_USART_EnableOneBitSamp
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableOneBitSamp(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_ONEBIT);
+}
+
+/**
+  * @brief  Disable One bit sampling method
+  * @rmtoll CR3          ONEBIT        LL_USART_DisableOneBitSamp
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableOneBitSamp(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_ONEBIT);
+}
+
+/**
+  * @brief  Indicate if One bit sampling method is enabled
+  * @rmtoll CR3          ONEBIT        LL_USART_IsEnabledOneBitSamp
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledOneBitSamp(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR3, USART_CR3_ONEBIT) == (USART_CR3_ONEBIT)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable Overrun detection
+  * @rmtoll CR3          OVRDIS        LL_USART_EnableOverrunDetect
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableOverrunDetect(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_OVRDIS);
+}
+
+/**
+  * @brief  Disable Overrun detection
+  * @rmtoll CR3          OVRDIS        LL_USART_DisableOverrunDetect
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableOverrunDetect(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_OVRDIS);
+}
+
+/**
+  * @brief  Indicate if Overrun detection is enabled
+  * @rmtoll CR3          OVRDIS        LL_USART_IsEnabledOverrunDetect
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledOverrunDetect(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR3, USART_CR3_OVRDIS) != USART_CR3_OVRDIS) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Select event type for Wake UP Interrupt Flag (WUS[1:0] bits)
+  * @note   Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+  *         Wake-up from Stop mode feature is supported by the USARTx instance.
+  * @rmtoll CR3          WUS           LL_USART_SetWKUPType
+  * @param  USARTx USART Instance
+  * @param  Type This parameter can be one of the following values:
+  *         @arg @ref LL_USART_WAKEUP_ON_ADDRESS
+  *         @arg @ref LL_USART_WAKEUP_ON_STARTBIT
+  *         @arg @ref LL_USART_WAKEUP_ON_RXNE
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetWKUPType(USART_TypeDef *USARTx, uint32_t Type)
+{
+  MODIFY_REG(USARTx->CR3, USART_CR3_WUS, Type);
+}
+
+/**
+  * @brief  Return event type for Wake UP Interrupt Flag (WUS[1:0] bits)
+  * @note   Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+  *         Wake-up from Stop mode feature is supported by the USARTx instance.
+  * @rmtoll CR3          WUS           LL_USART_GetWKUPType
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_WAKEUP_ON_ADDRESS
+  *         @arg @ref LL_USART_WAKEUP_ON_STARTBIT
+  *         @arg @ref LL_USART_WAKEUP_ON_RXNE
+  */
+__STATIC_INLINE uint32_t LL_USART_GetWKUPType(const USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_WUS));
+}
+
+/**
+  * @brief  Configure USART BRR register for achieving expected Baud Rate value.
+  * @note   Compute and set USARTDIV value in BRR Register (full BRR content)
+  *         according to used Peripheral Clock, Oversampling mode, and expected Baud Rate values
+  * @note   Peripheral clock and Baud rate values provided as function parameters should be valid
+  *         (Baud rate value != 0)
+  * @note   In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d.
+  * @rmtoll BRR          BRR           LL_USART_SetBaudRate
+  * @param  USARTx USART Instance
+  * @param  PeriphClk Peripheral Clock
+  * @param  PrescalerValue This parameter can be one of the following values:
+  *         @arg @ref LL_USART_PRESCALER_DIV1
+  *         @arg @ref LL_USART_PRESCALER_DIV2
+  *         @arg @ref LL_USART_PRESCALER_DIV4
+  *         @arg @ref LL_USART_PRESCALER_DIV6
+  *         @arg @ref LL_USART_PRESCALER_DIV8
+  *         @arg @ref LL_USART_PRESCALER_DIV10
+  *         @arg @ref LL_USART_PRESCALER_DIV12
+  *         @arg @ref LL_USART_PRESCALER_DIV16
+  *         @arg @ref LL_USART_PRESCALER_DIV32
+  *         @arg @ref LL_USART_PRESCALER_DIV64
+  *         @arg @ref LL_USART_PRESCALER_DIV128
+  *         @arg @ref LL_USART_PRESCALER_DIV256
+  * @param  OverSampling This parameter can be one of the following values:
+  *         @arg @ref LL_USART_OVERSAMPLING_16
+  *         @arg @ref LL_USART_OVERSAMPLING_8
+  * @param  BaudRate Baud Rate
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t PrescalerValue,
+                                          uint32_t OverSampling,
+                                          uint32_t BaudRate)
+{
+  uint32_t usartdiv;
+  uint32_t brrtemp;
+
+  if (PrescalerValue > LL_USART_PRESCALER_DIV256)
+  {
+    /* Do not overstep the size of USART_PRESCALER_TAB */
+  }
+  else if (BaudRate == 0U)
+  {
+    /* Can Not divide per 0 */
+  }
+  else if (OverSampling == LL_USART_OVERSAMPLING_8)
+  {
+    usartdiv = (uint16_t)(__LL_USART_DIV_SAMPLING8(PeriphClk, (uint8_t)PrescalerValue, BaudRate));
+    brrtemp = usartdiv & 0xFFF0U;
+    brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
+    USARTx->BRR = brrtemp;
+  }
+  else
+  {
+    USARTx->BRR = (uint16_t)(__LL_USART_DIV_SAMPLING16(PeriphClk, (uint8_t)PrescalerValue, BaudRate));
+  }
+}
+
+/**
+  * @brief  Return current Baud Rate value, according to USARTDIV present in BRR register
+  *         (full BRR content), and to used Peripheral Clock and Oversampling mode values
+  * @note   In case of non-initialized or invalid value stored in BRR register, value 0 will be returned.
+  * @note   In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d.
+  * @rmtoll BRR          BRR           LL_USART_GetBaudRate
+  * @param  USARTx USART Instance
+  * @param  PeriphClk Peripheral Clock
+  * @param  PrescalerValue This parameter can be one of the following values:
+  *         @arg @ref LL_USART_PRESCALER_DIV1
+  *         @arg @ref LL_USART_PRESCALER_DIV2
+  *         @arg @ref LL_USART_PRESCALER_DIV4
+  *         @arg @ref LL_USART_PRESCALER_DIV6
+  *         @arg @ref LL_USART_PRESCALER_DIV8
+  *         @arg @ref LL_USART_PRESCALER_DIV10
+  *         @arg @ref LL_USART_PRESCALER_DIV12
+  *         @arg @ref LL_USART_PRESCALER_DIV16
+  *         @arg @ref LL_USART_PRESCALER_DIV32
+  *         @arg @ref LL_USART_PRESCALER_DIV64
+  *         @arg @ref LL_USART_PRESCALER_DIV128
+  *         @arg @ref LL_USART_PRESCALER_DIV256
+  * @param  OverSampling This parameter can be one of the following values:
+  *         @arg @ref LL_USART_OVERSAMPLING_16
+  *         @arg @ref LL_USART_OVERSAMPLING_8
+  * @retval Baud Rate
+  */
+__STATIC_INLINE uint32_t LL_USART_GetBaudRate(const USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t PrescalerValue,
+                                              uint32_t OverSampling)
+{
+  uint32_t usartdiv;
+  uint32_t brrresult = 0x0U;
+  uint32_t periphclkpresc = (uint32_t)(PeriphClk / (USART_PRESCALER_TAB[(uint8_t)PrescalerValue]));
+
+  usartdiv = USARTx->BRR;
+
+  if (usartdiv == 0U)
+  {
+    /* Do not perform a division by 0 */
+  }
+  else if (OverSampling == LL_USART_OVERSAMPLING_8)
+  {
+    usartdiv = (uint16_t)((usartdiv & 0xFFF0U) | ((usartdiv & 0x0007U) << 1U)) ;
+    if (usartdiv != 0U)
+    {
+      brrresult = (periphclkpresc * 2U) / usartdiv;
+    }
+  }
+  else
+  {
+    if ((usartdiv & 0xFFFFU) != 0U)
+    {
+      brrresult = periphclkpresc / usartdiv;
+    }
+  }
+  return (brrresult);
+}
+
+/**
+  * @brief  Set Receiver Time Out Value (expressed in nb of bits duration)
+  * @rmtoll RTOR         RTO           LL_USART_SetRxTimeout
+  * @param  USARTx USART Instance
+  * @param  Timeout Value between Min_Data=0x00 and Max_Data=0x00FFFFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetRxTimeout(USART_TypeDef *USARTx, uint32_t Timeout)
+{
+  MODIFY_REG(USARTx->RTOR, USART_RTOR_RTO, Timeout);
+}
+
+/**
+  * @brief  Get Receiver Time Out Value (expressed in nb of bits duration)
+  * @rmtoll RTOR         RTO           LL_USART_GetRxTimeout
+  * @param  USARTx USART Instance
+  * @retval Value between Min_Data=0x00 and Max_Data=0x00FFFFFF
+  */
+__STATIC_INLINE uint32_t LL_USART_GetRxTimeout(const USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->RTOR, USART_RTOR_RTO));
+}
+
+/**
+  * @brief  Set Block Length value in reception
+  * @rmtoll RTOR         BLEN          LL_USART_SetBlockLength
+  * @param  USARTx USART Instance
+  * @param  BlockLength Value between Min_Data=0x00 and Max_Data=0xFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetBlockLength(USART_TypeDef *USARTx, uint32_t BlockLength)
+{
+  MODIFY_REG(USARTx->RTOR, USART_RTOR_BLEN, BlockLength << USART_RTOR_BLEN_Pos);
+}
+
+/**
+  * @brief  Get Block Length value in reception
+  * @rmtoll RTOR         BLEN          LL_USART_GetBlockLength
+  * @param  USARTx USART Instance
+  * @retval Value between Min_Data=0x00 and Max_Data=0xFF
+  */
+__STATIC_INLINE uint32_t LL_USART_GetBlockLength(const USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->RTOR, USART_RTOR_BLEN) >> USART_RTOR_BLEN_Pos);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EF_Configuration_IRDA Configuration functions related to Irda feature
+  * @{
+  */
+
+/**
+  * @brief  Enable IrDA mode
+  * @note   Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+  *         IrDA feature is supported by the USARTx instance.
+  * @rmtoll CR3          IREN          LL_USART_EnableIrda
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIrda(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_IREN);
+}
+
+/**
+  * @brief  Disable IrDA mode
+  * @note   Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+  *         IrDA feature is supported by the USARTx instance.
+  * @rmtoll CR3          IREN          LL_USART_DisableIrda
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIrda(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_IREN);
+}
+
+/**
+  * @brief  Indicate if IrDA mode is enabled
+  * @note   Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+  *         IrDA feature is supported by the USARTx instance.
+  * @rmtoll CR3          IREN          LL_USART_IsEnabledIrda
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIrda(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR3, USART_CR3_IREN) == (USART_CR3_IREN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Configure IrDA Power Mode (Normal or Low Power)
+  * @note   Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+  *         IrDA feature is supported by the USARTx instance.
+  * @rmtoll CR3          IRLP          LL_USART_SetIrdaPowerMode
+  * @param  USARTx USART Instance
+  * @param  PowerMode This parameter can be one of the following values:
+  *         @arg @ref LL_USART_IRDA_POWER_NORMAL
+  *         @arg @ref LL_USART_IRDA_POWER_LOW
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetIrdaPowerMode(USART_TypeDef *USARTx, uint32_t PowerMode)
+{
+  MODIFY_REG(USARTx->CR3, USART_CR3_IRLP, PowerMode);
+}
+
+/**
+  * @brief  Retrieve IrDA Power Mode configuration (Normal or Low Power)
+  * @note   Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+  *         IrDA feature is supported by the USARTx instance.
+  * @rmtoll CR3          IRLP          LL_USART_GetIrdaPowerMode
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_IRDA_POWER_NORMAL
+  *         @arg @ref LL_USART_PHASE_2EDGE
+  */
+__STATIC_INLINE uint32_t LL_USART_GetIrdaPowerMode(const USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_IRLP));
+}
+
+/**
+  * @brief  Set Irda prescaler value, used for dividing the USART clock source
+  *         to achieve the Irda Low Power frequency (8 bits value)
+  * @note   Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+  *         IrDA feature is supported by the USARTx instance.
+  * @rmtoll GTPR         PSC           LL_USART_SetIrdaPrescaler
+  * @param  USARTx USART Instance
+  * @param  PrescalerValue Value between Min_Data=0x00 and Max_Data=0xFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetIrdaPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue)
+{
+  MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, (uint16_t)PrescalerValue);
+}
+
+/**
+  * @brief  Return Irda prescaler value, used for dividing the USART clock source
+  *         to achieve the Irda Low Power frequency (8 bits value)
+  * @note   Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+  *         IrDA feature is supported by the USARTx instance.
+  * @rmtoll GTPR         PSC           LL_USART_GetIrdaPrescaler
+  * @param  USARTx USART Instance
+  * @retval Irda prescaler value (Value between Min_Data=0x00 and Max_Data=0xFF)
+  */
+__STATIC_INLINE uint32_t LL_USART_GetIrdaPrescaler(const USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EF_Configuration_Smartcard Configuration functions related to Smartcard feature
+  * @{
+  */
+
+/**
+  * @brief  Enable Smartcard NACK transmission
+  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR3          NACK          LL_USART_EnableSmartcardNACK
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableSmartcardNACK(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_NACK);
+}
+
+/**
+  * @brief  Disable Smartcard NACK transmission
+  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR3          NACK          LL_USART_DisableSmartcardNACK
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableSmartcardNACK(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_NACK);
+}
+
+/**
+  * @brief  Indicate if Smartcard NACK transmission is enabled
+  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR3          NACK          LL_USART_IsEnabledSmartcardNACK
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcardNACK(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR3, USART_CR3_NACK) == (USART_CR3_NACK)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable Smartcard mode
+  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR3          SCEN          LL_USART_EnableSmartcard
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableSmartcard(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_SCEN);
+}
+
+/**
+  * @brief  Disable Smartcard mode
+  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR3          SCEN          LL_USART_DisableSmartcard
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableSmartcard(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_SCEN);
+}
+
+/**
+  * @brief  Indicate if Smartcard mode is enabled
+  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR3          SCEN          LL_USART_IsEnabledSmartcard
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcard(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR3, USART_CR3_SCEN) == (USART_CR3_SCEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set Smartcard Auto-Retry Count value (SCARCNT[2:0] bits)
+  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @note   This bit-field specifies the number of retries in transmit and receive, in Smartcard mode.
+  *         In transmission mode, it specifies the number of automatic retransmission retries, before
+  *         generating a transmission error (FE bit set).
+  *         In reception mode, it specifies the number or erroneous reception trials, before generating a
+  *         reception error (RXNE and PE bits set)
+  * @rmtoll CR3          SCARCNT       LL_USART_SetSmartcardAutoRetryCount
+  * @param  USARTx USART Instance
+  * @param  AutoRetryCount Value between Min_Data=0 and Max_Data=7
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetSmartcardAutoRetryCount(USART_TypeDef *USARTx, uint32_t AutoRetryCount)
+{
+  MODIFY_REG(USARTx->CR3, USART_CR3_SCARCNT, AutoRetryCount << USART_CR3_SCARCNT_Pos);
+}
+
+/**
+  * @brief  Return Smartcard Auto-Retry Count value (SCARCNT[2:0] bits)
+  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR3          SCARCNT       LL_USART_GetSmartcardAutoRetryCount
+  * @param  USARTx USART Instance
+  * @retval Smartcard Auto-Retry Count value (Value between Min_Data=0 and Max_Data=7)
+  */
+__STATIC_INLINE uint32_t LL_USART_GetSmartcardAutoRetryCount(const USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_SCARCNT) >> USART_CR3_SCARCNT_Pos);
+}
+
+/**
+  * @brief  Set Smartcard prescaler value, used for dividing the USART clock
+  *         source to provide the SMARTCARD Clock (5 bits value)
+  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll GTPR         PSC           LL_USART_SetSmartcardPrescaler
+  * @param  USARTx USART Instance
+  * @param  PrescalerValue Value between Min_Data=0 and Max_Data=31
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetSmartcardPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue)
+{
+  MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, (uint16_t)PrescalerValue);
+}
+
+/**
+  * @brief  Return Smartcard prescaler value, used for dividing the USART clock
+  *         source to provide the SMARTCARD Clock (5 bits value)
+  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll GTPR         PSC           LL_USART_GetSmartcardPrescaler
+  * @param  USARTx USART Instance
+  * @retval Smartcard prescaler value (Value between Min_Data=0 and Max_Data=31)
+  */
+__STATIC_INLINE uint32_t LL_USART_GetSmartcardPrescaler(const USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC));
+}
+
+/**
+  * @brief  Set Smartcard Guard time value, expressed in nb of baud clocks periods
+  *         (GT[7:0] bits : Guard time value)
+  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll GTPR         GT            LL_USART_SetSmartcardGuardTime
+  * @param  USARTx USART Instance
+  * @param  GuardTime Value between Min_Data=0x00 and Max_Data=0xFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetSmartcardGuardTime(USART_TypeDef *USARTx, uint32_t GuardTime)
+{
+  MODIFY_REG(USARTx->GTPR, USART_GTPR_GT, (uint16_t)(GuardTime << USART_GTPR_GT_Pos));
+}
+
+/**
+  * @brief  Return Smartcard Guard time value, expressed in nb of baud clocks periods
+  *         (GT[7:0] bits : Guard time value)
+  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll GTPR         GT            LL_USART_GetSmartcardGuardTime
+  * @param  USARTx USART Instance
+  * @retval Smartcard Guard time value (Value between Min_Data=0x00 and Max_Data=0xFF)
+  */
+__STATIC_INLINE uint32_t LL_USART_GetSmartcardGuardTime(const USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_GT) >> USART_GTPR_GT_Pos);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EF_Configuration_HalfDuplex Configuration functions related to Half Duplex feature
+  * @{
+  */
+
+/**
+  * @brief  Enable Single Wire Half-Duplex mode
+  * @note   Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
+  *         Half-Duplex mode is supported by the USARTx instance.
+  * @rmtoll CR3          HDSEL         LL_USART_EnableHalfDuplex
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableHalfDuplex(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_HDSEL);
+}
+
+/**
+  * @brief  Disable Single Wire Half-Duplex mode
+  * @note   Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
+  *         Half-Duplex mode is supported by the USARTx instance.
+  * @rmtoll CR3          HDSEL         LL_USART_DisableHalfDuplex
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableHalfDuplex(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_HDSEL);
+}
+
+/**
+  * @brief  Indicate if Single Wire Half-Duplex mode is enabled
+  * @note   Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
+  *         Half-Duplex mode is supported by the USARTx instance.
+  * @rmtoll CR3          HDSEL         LL_USART_IsEnabledHalfDuplex
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledHalfDuplex(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EF_Configuration_SPI_SLAVE Configuration functions related to SPI Slave feature
+  * @{
+  */
+/**
+  * @brief  Enable SPI Synchronous Slave mode
+  * @note   Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
+  *         SPI Slave mode feature is supported by the USARTx instance.
+  * @rmtoll CR2          SLVEN         LL_USART_EnableSPISlave
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableSPISlave(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR2, USART_CR2_SLVEN);
+}
+
+/**
+  * @brief  Disable SPI Synchronous Slave mode
+  * @note   Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
+  *         SPI Slave mode feature is supported by the USARTx instance.
+  * @rmtoll CR2          SLVEN         LL_USART_DisableSPISlave
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableSPISlave(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR2, USART_CR2_SLVEN);
+}
+
+/**
+  * @brief  Indicate if  SPI Synchronous Slave mode is enabled
+  * @note   Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
+  *         SPI Slave mode feature is supported by the USARTx instance.
+  * @rmtoll CR2          SLVEN         LL_USART_IsEnabledSPISlave
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledSPISlave(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR2, USART_CR2_SLVEN) == (USART_CR2_SLVEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable SPI Slave Selection using NSS input pin
+  * @note   Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
+  *         SPI Slave mode feature is supported by the USARTx instance.
+  * @note   SPI Slave Selection depends on NSS input pin
+  *         (The slave is selected when NSS is low and deselected when NSS is high).
+  * @rmtoll CR2          DIS_NSS       LL_USART_EnableSPISlaveSelect
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableSPISlaveSelect(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR2, USART_CR2_DIS_NSS);
+}
+
+/**
+  * @brief  Disable SPI Slave Selection using NSS input pin
+  * @note   Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
+  *         SPI Slave mode feature is supported by the USARTx instance.
+  * @note   SPI Slave will be always selected and NSS input pin will be ignored.
+  * @rmtoll CR2          DIS_NSS       LL_USART_DisableSPISlaveSelect
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableSPISlaveSelect(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR2, USART_CR2_DIS_NSS);
+}
+
+/**
+  * @brief  Indicate if  SPI Slave Selection depends on NSS input pin
+  * @note   Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
+  *         SPI Slave mode feature is supported by the USARTx instance.
+  * @rmtoll CR2          DIS_NSS       LL_USART_IsEnabledSPISlaveSelect
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledSPISlaveSelect(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR2, USART_CR2_DIS_NSS) != (USART_CR2_DIS_NSS)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EF_Configuration_LIN Configuration functions related to LIN feature
+  * @{
+  */
+
+/**
+  * @brief  Set LIN Break Detection Length
+  * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+  *         LIN feature is supported by the USARTx instance.
+  * @rmtoll CR2          LBDL          LL_USART_SetLINBrkDetectionLen
+  * @param  USARTx USART Instance
+  * @param  LINBDLength This parameter can be one of the following values:
+  *         @arg @ref LL_USART_LINBREAK_DETECT_10B
+  *         @arg @ref LL_USART_LINBREAK_DETECT_11B
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetLINBrkDetectionLen(USART_TypeDef *USARTx, uint32_t LINBDLength)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_LBDL, LINBDLength);
+}
+
+/**
+  * @brief  Return LIN Break Detection Length
+  * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+  *         LIN feature is supported by the USARTx instance.
+  * @rmtoll CR2          LBDL          LL_USART_GetLINBrkDetectionLen
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_LINBREAK_DETECT_10B
+  *         @arg @ref LL_USART_LINBREAK_DETECT_11B
+  */
+__STATIC_INLINE uint32_t LL_USART_GetLINBrkDetectionLen(const USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBDL));
+}
+
+/**
+  * @brief  Enable LIN mode
+  * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+  *         LIN feature is supported by the USARTx instance.
+  * @rmtoll CR2          LINEN         LL_USART_EnableLIN
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableLIN(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR2, USART_CR2_LINEN);
+}
+
+/**
+  * @brief  Disable LIN mode
+  * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+  *         LIN feature is supported by the USARTx instance.
+  * @rmtoll CR2          LINEN         LL_USART_DisableLIN
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableLIN(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR2, USART_CR2_LINEN);
+}
+
+/**
+  * @brief  Indicate if LIN mode is enabled
+  * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+  *         LIN feature is supported by the USARTx instance.
+  * @rmtoll CR2          LINEN         LL_USART_IsEnabledLIN
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledLIN(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR2, USART_CR2_LINEN) == (USART_CR2_LINEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EF_Configuration_DE Configuration functions related to Driver Enable feature
+  * @{
+  */
+
+/**
+  * @brief  Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits).
+  * @note   Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+  *         Driver Enable feature is supported by the USARTx instance.
+  * @rmtoll CR1          DEDT          LL_USART_SetDEDeassertionTime
+  * @param  USARTx USART Instance
+  * @param  Time Value between Min_Data=0 and Max_Data=31
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetDEDeassertionTime(USART_TypeDef *USARTx, uint32_t Time)
+{
+  MODIFY_REG(USARTx->CR1, USART_CR1_DEDT, Time << USART_CR1_DEDT_Pos);
+}
+
+/**
+  * @brief  Return DEDT (Driver Enable De-Assertion Time)
+  * @note   Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+  *         Driver Enable feature is supported by the USARTx instance.
+  * @rmtoll CR1          DEDT          LL_USART_GetDEDeassertionTime
+  * @param  USARTx USART Instance
+  * @retval Time value expressed on 5 bits ([4:0] bits) : Value between Min_Data=0 and Max_Data=31
+  */
+__STATIC_INLINE uint32_t LL_USART_GetDEDeassertionTime(const USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_DEDT) >> USART_CR1_DEDT_Pos);
+}
+
+/**
+  * @brief  Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits).
+  * @note   Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+  *         Driver Enable feature is supported by the USARTx instance.
+  * @rmtoll CR1          DEAT          LL_USART_SetDEAssertionTime
+  * @param  USARTx USART Instance
+  * @param  Time Value between Min_Data=0 and Max_Data=31
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetDEAssertionTime(USART_TypeDef *USARTx, uint32_t Time)
+{
+  MODIFY_REG(USARTx->CR1, USART_CR1_DEAT, Time << USART_CR1_DEAT_Pos);
+}
+
+/**
+  * @brief  Return DEAT (Driver Enable Assertion Time)
+  * @note   Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+  *         Driver Enable feature is supported by the USARTx instance.
+  * @rmtoll CR1          DEAT          LL_USART_GetDEAssertionTime
+  * @param  USARTx USART Instance
+  * @retval Time value expressed on 5 bits ([4:0] bits) : Value between Min_Data=0 and Max_Data=31
+  */
+__STATIC_INLINE uint32_t LL_USART_GetDEAssertionTime(const USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_DEAT) >> USART_CR1_DEAT_Pos);
+}
+
+/**
+  * @brief  Enable Driver Enable (DE) Mode
+  * @note   Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+  *         Driver Enable feature is supported by the USARTx instance.
+  * @rmtoll CR3          DEM           LL_USART_EnableDEMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableDEMode(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_DEM);
+}
+
+/**
+  * @brief  Disable Driver Enable (DE) Mode
+  * @note   Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+  *         Driver Enable feature is supported by the USARTx instance.
+  * @rmtoll CR3          DEM           LL_USART_DisableDEMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableDEMode(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_DEM);
+}
+
+/**
+  * @brief  Indicate if Driver Enable (DE) Mode is enabled
+  * @note   Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+  *         Driver Enable feature is supported by the USARTx instance.
+  * @rmtoll CR3          DEM           LL_USART_IsEnabledDEMode
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledDEMode(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR3, USART_CR3_DEM) == (USART_CR3_DEM)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Select Driver Enable Polarity
+  * @note   Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+  *         Driver Enable feature is supported by the USARTx instance.
+  * @rmtoll CR3          DEP           LL_USART_SetDESignalPolarity
+  * @param  USARTx USART Instance
+  * @param  Polarity This parameter can be one of the following values:
+  *         @arg @ref LL_USART_DE_POLARITY_HIGH
+  *         @arg @ref LL_USART_DE_POLARITY_LOW
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetDESignalPolarity(USART_TypeDef *USARTx, uint32_t Polarity)
+{
+  MODIFY_REG(USARTx->CR3, USART_CR3_DEP, Polarity);
+}
+
+/**
+  * @brief  Return Driver Enable Polarity
+  * @note   Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+  *         Driver Enable feature is supported by the USARTx instance.
+  * @rmtoll CR3          DEP           LL_USART_GetDESignalPolarity
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_DE_POLARITY_HIGH
+  *         @arg @ref LL_USART_DE_POLARITY_LOW
+  */
+__STATIC_INLINE uint32_t LL_USART_GetDESignalPolarity(const USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_DEP));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EF_AdvancedConfiguration Advanced Configurations services
+  * @{
+  */
+
+/**
+  * @brief  Perform basic configuration of USART for enabling use in Asynchronous Mode (UART)
+  * @note   In UART mode, the following bits must be kept cleared:
+  *           - LINEN bit in the USART_CR2 register,
+  *           - CLKEN bit in the USART_CR2 register,
+  *           - SCEN bit in the USART_CR3 register,
+  *           - IREN bit in the USART_CR3 register,
+  *           - HDSEL bit in the USART_CR3 register.
+  * @note   Call of this function is equivalent to following function call sequence :
+  *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
+  *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
+  *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
+  *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
+  *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
+  * @note   Other remaining configurations items related to Asynchronous Mode
+  *         (as Baud Rate, Word length, Parity, ...) should be set using
+  *         dedicated functions
+  * @rmtoll CR2          LINEN         LL_USART_ConfigAsyncMode\n
+  *         CR2          CLKEN         LL_USART_ConfigAsyncMode\n
+  *         CR3          SCEN          LL_USART_ConfigAsyncMode\n
+  *         CR3          IREN          LL_USART_ConfigAsyncMode\n
+  *         CR3          HDSEL         LL_USART_ConfigAsyncMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ConfigAsyncMode(USART_TypeDef *USARTx)
+{
+  /* In Asynchronous mode, the following bits must be kept cleared:
+  - LINEN, CLKEN bits in the USART_CR2 register,
+  - SCEN, IREN and HDSEL bits in the USART_CR3 register.
+  */
+  CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+  CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL));
+}
+
+/**
+  * @brief  Perform basic configuration of USART for enabling use in Synchronous Mode
+  * @note   In Synchronous mode, the following bits must be kept cleared:
+  *           - LINEN bit in the USART_CR2 register,
+  *           - SCEN bit in the USART_CR3 register,
+  *           - IREN bit in the USART_CR3 register,
+  *           - HDSEL bit in the USART_CR3 register.
+  *         This function also sets the USART in Synchronous mode.
+  * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
+  *         Synchronous mode is supported by the USARTx instance.
+  * @note   Call of this function is equivalent to following function call sequence :
+  *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
+  *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
+  *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
+  *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
+  *         - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function
+  * @note   Other remaining configurations items related to Synchronous Mode
+  *         (as Baud Rate, Word length, Parity, Clock Polarity, ...) should be set using
+  *         dedicated functions
+  * @rmtoll CR2          LINEN         LL_USART_ConfigSyncMode\n
+  *         CR2          CLKEN         LL_USART_ConfigSyncMode\n
+  *         CR3          SCEN          LL_USART_ConfigSyncMode\n
+  *         CR3          IREN          LL_USART_ConfigSyncMode\n
+  *         CR3          HDSEL         LL_USART_ConfigSyncMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ConfigSyncMode(USART_TypeDef *USARTx)
+{
+  /* In Synchronous mode, the following bits must be kept cleared:
+  - LINEN bit in the USART_CR2 register,
+  - SCEN, IREN and HDSEL bits in the USART_CR3 register.
+  */
+  CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN));
+  CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL));
+  /* set the UART/USART in Synchronous mode */
+  SET_BIT(USARTx->CR2, USART_CR2_CLKEN);
+}
+
+/**
+  * @brief  Perform basic configuration of USART for enabling use in LIN Mode
+  * @note   In LIN mode, the following bits must be kept cleared:
+  *           - STOP and CLKEN bits in the USART_CR2 register,
+  *           - SCEN bit in the USART_CR3 register,
+  *           - IREN bit in the USART_CR3 register,
+  *           - HDSEL bit in the USART_CR3 register.
+  *         This function also set the UART/USART in LIN mode.
+  * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+  *         LIN feature is supported by the USARTx instance.
+  * @note   Call of this function is equivalent to following function call sequence :
+  *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
+  *         - Clear STOP in CR2 using @ref LL_USART_SetStopBitsLength() function
+  *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
+  *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
+  *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
+  *         - Set LINEN in CR2 using @ref LL_USART_EnableLIN() function
+  * @note   Other remaining configurations items related to LIN Mode
+  *         (as Baud Rate, Word length, LIN Break Detection Length, ...) should be set using
+  *         dedicated functions
+  * @rmtoll CR2          CLKEN         LL_USART_ConfigLINMode\n
+  *         CR2          STOP          LL_USART_ConfigLINMode\n
+  *         CR2          LINEN         LL_USART_ConfigLINMode\n
+  *         CR3          IREN          LL_USART_ConfigLINMode\n
+  *         CR3          SCEN          LL_USART_ConfigLINMode\n
+  *         CR3          HDSEL         LL_USART_ConfigLINMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ConfigLINMode(USART_TypeDef *USARTx)
+{
+  /* In LIN mode, the following bits must be kept cleared:
+  - STOP and CLKEN bits in the USART_CR2 register,
+  - IREN, SCEN and HDSEL bits in the USART_CR3 register.
+  */
+  CLEAR_BIT(USARTx->CR2, (USART_CR2_CLKEN | USART_CR2_STOP));
+  CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_SCEN | USART_CR3_HDSEL));
+  /* Set the UART/USART in LIN mode */
+  SET_BIT(USARTx->CR2, USART_CR2_LINEN);
+}
+
+/**
+  * @brief  Perform basic configuration of USART for enabling use in Half Duplex Mode
+  * @note   In Half Duplex mode, the following bits must be kept cleared:
+  *           - LINEN bit in the USART_CR2 register,
+  *           - CLKEN bit in the USART_CR2 register,
+  *           - SCEN bit in the USART_CR3 register,
+  *           - IREN bit in the USART_CR3 register,
+  *         This function also sets the UART/USART in Half Duplex mode.
+  * @note   Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
+  *         Half-Duplex mode is supported by the USARTx instance.
+  * @note   Call of this function is equivalent to following function call sequence :
+  *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
+  *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
+  *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
+  *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
+  *         - Set HDSEL in CR3 using @ref LL_USART_EnableHalfDuplex() function
+  * @note   Other remaining configurations items related to Half Duplex Mode
+  *         (as Baud Rate, Word length, Parity, ...) should be set using
+  *         dedicated functions
+  * @rmtoll CR2          LINEN         LL_USART_ConfigHalfDuplexMode\n
+  *         CR2          CLKEN         LL_USART_ConfigHalfDuplexMode\n
+  *         CR3          HDSEL         LL_USART_ConfigHalfDuplexMode\n
+  *         CR3          SCEN          LL_USART_ConfigHalfDuplexMode\n
+  *         CR3          IREN          LL_USART_ConfigHalfDuplexMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ConfigHalfDuplexMode(USART_TypeDef *USARTx)
+{
+  /* In Half Duplex mode, the following bits must be kept cleared:
+  - LINEN and CLKEN bits in the USART_CR2 register,
+  - SCEN and IREN bits in the USART_CR3 register.
+  */
+  CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+  CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN));
+  /* set the UART/USART in Half Duplex mode */
+  SET_BIT(USARTx->CR3, USART_CR3_HDSEL);
+}
+
+/**
+  * @brief  Perform basic configuration of USART for enabling use in Smartcard Mode
+  * @note   In Smartcard mode, the following bits must be kept cleared:
+  *           - LINEN bit in the USART_CR2 register,
+  *           - IREN bit in the USART_CR3 register,
+  *           - HDSEL bit in the USART_CR3 register.
+  *         This function also configures Stop bits to 1.5 bits and
+  *         sets the USART in Smartcard mode (SCEN bit).
+  *         Clock Output is also enabled (CLKEN).
+  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @note   Call of this function is equivalent to following function call sequence :
+  *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
+  *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
+  *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
+  *         - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength() function
+  *         - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function
+  *         - Set SCEN in CR3 using @ref LL_USART_EnableSmartcard() function
+  * @note   Other remaining configurations items related to Smartcard Mode
+  *         (as Baud Rate, Word length, Parity, ...) should be set using
+  *         dedicated functions
+  * @rmtoll CR2          LINEN         LL_USART_ConfigSmartcardMode\n
+  *         CR2          STOP          LL_USART_ConfigSmartcardMode\n
+  *         CR2          CLKEN         LL_USART_ConfigSmartcardMode\n
+  *         CR3          HDSEL         LL_USART_ConfigSmartcardMode\n
+  *         CR3          SCEN          LL_USART_ConfigSmartcardMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ConfigSmartcardMode(USART_TypeDef *USARTx)
+{
+  /* In Smartcard mode, the following bits must be kept cleared:
+  - LINEN bit in the USART_CR2 register,
+  - IREN and HDSEL bits in the USART_CR3 register.
+  */
+  CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN));
+  CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_HDSEL));
+  /* Configure Stop bits to 1.5 bits */
+  /* Synchronous mode is activated by default */
+  SET_BIT(USARTx->CR2, (USART_CR2_STOP_0 | USART_CR2_STOP_1 | USART_CR2_CLKEN));
+  /* set the UART/USART in Smartcard mode */
+  SET_BIT(USARTx->CR3, USART_CR3_SCEN);
+}
+
+/**
+  * @brief  Perform basic configuration of USART for enabling use in Irda Mode
+  * @note   In IRDA mode, the following bits must be kept cleared:
+  *           - LINEN bit in the USART_CR2 register,
+  *           - STOP and CLKEN bits in the USART_CR2 register,
+  *           - SCEN bit in the USART_CR3 register,
+  *           - HDSEL bit in the USART_CR3 register.
+  *         This function also sets the UART/USART in IRDA mode (IREN bit).
+  * @note   Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+  *         IrDA feature is supported by the USARTx instance.
+  * @note   Call of this function is equivalent to following function call sequence :
+  *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
+  *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
+  *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
+  *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
+  *         - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength() function
+  *         - Set IREN in CR3 using @ref LL_USART_EnableIrda() function
+  * @note   Other remaining configurations items related to Irda Mode
+  *         (as Baud Rate, Word length, Power mode, ...) should be set using
+  *         dedicated functions
+  * @rmtoll CR2          LINEN         LL_USART_ConfigIrdaMode\n
+  *         CR2          CLKEN         LL_USART_ConfigIrdaMode\n
+  *         CR2          STOP          LL_USART_ConfigIrdaMode\n
+  *         CR3          SCEN          LL_USART_ConfigIrdaMode\n
+  *         CR3          HDSEL         LL_USART_ConfigIrdaMode\n
+  *         CR3          IREN          LL_USART_ConfigIrdaMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ConfigIrdaMode(USART_TypeDef *USARTx)
+{
+  /* In IRDA mode, the following bits must be kept cleared:
+  - LINEN, STOP and CLKEN bits in the USART_CR2 register,
+  - SCEN and HDSEL bits in the USART_CR3 register.
+  */
+  CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP));
+  CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL));
+  /* set the UART/USART in IRDA mode */
+  SET_BIT(USARTx->CR3, USART_CR3_IREN);
+}
+
+/**
+  * @brief  Perform basic configuration of USART for enabling use in Multi processor Mode
+  *         (several USARTs connected in a network, one of the USARTs can be the master,
+  *         its TX output connected to the RX inputs of the other slaves USARTs).
+  * @note   In MultiProcessor mode, the following bits must be kept cleared:
+  *           - LINEN bit in the USART_CR2 register,
+  *           - CLKEN bit in the USART_CR2 register,
+  *           - SCEN bit in the USART_CR3 register,
+  *           - IREN bit in the USART_CR3 register,
+  *           - HDSEL bit in the USART_CR3 register.
+  * @note   Call of this function is equivalent to following function call sequence :
+  *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
+  *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
+  *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
+  *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
+  *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
+  * @note   Other remaining configurations items related to Multi processor Mode
+  *         (as Baud Rate, Wake Up Method, Node address, ...) should be set using
+  *         dedicated functions
+  * @rmtoll CR2          LINEN         LL_USART_ConfigMultiProcessMode\n
+  *         CR2          CLKEN         LL_USART_ConfigMultiProcessMode\n
+  *         CR3          SCEN          LL_USART_ConfigMultiProcessMode\n
+  *         CR3          HDSEL         LL_USART_ConfigMultiProcessMode\n
+  *         CR3          IREN          LL_USART_ConfigMultiProcessMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ConfigMultiProcessMode(USART_TypeDef *USARTx)
+{
+  /* In Multi Processor mode, the following bits must be kept cleared:
+  - LINEN and CLKEN bits in the USART_CR2 register,
+  - IREN, SCEN and HDSEL bits in the USART_CR3 register.
+  */
+  CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+  CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EF_FLAG_Management FLAG_Management
+  * @{
+  */
+
+/**
+  * @brief  Check if the USART Parity Error Flag is set or not
+  * @rmtoll ISR          PE            LL_USART_IsActiveFlag_PE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_PE(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_PE) == (USART_ISR_PE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Framing Error Flag is set or not
+  * @rmtoll ISR          FE            LL_USART_IsActiveFlag_FE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_FE(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_FE) == (USART_ISR_FE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Noise error detected Flag is set or not
+  * @rmtoll ISR          NE            LL_USART_IsActiveFlag_NE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_NE(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_NE) == (USART_ISR_NE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART OverRun Error Flag is set or not
+  * @rmtoll ISR          ORE           LL_USART_IsActiveFlag_ORE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ORE(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_ORE) == (USART_ISR_ORE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART IDLE line detected Flag is set or not
+  * @rmtoll ISR          IDLE          LL_USART_IsActiveFlag_IDLE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_IDLE(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE)) ? 1UL : 0UL);
+}
+
+#define LL_USART_IsActiveFlag_RXNE  LL_USART_IsActiveFlag_RXNE_RXFNE /* Redefinition for legacy purpose */
+
+/**
+  * @brief  Check if the USART Read Data Register or USART RX FIFO Not Empty Flag is set or not
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll ISR          RXNE_RXFNE    LL_USART_IsActiveFlag_RXNE_RXFNE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXNE_RXFNE(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_RXNE_RXFNE) == (USART_ISR_RXNE_RXFNE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Transmission Complete Flag is set or not
+  * @rmtoll ISR          TC            LL_USART_IsActiveFlag_TC
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TC(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_TC) == (USART_ISR_TC)) ? 1UL : 0UL);
+}
+
+#define LL_USART_IsActiveFlag_TXE  LL_USART_IsActiveFlag_TXE_TXFNF /* Redefinition for legacy purpose */
+
+/**
+  * @brief  Check if the USART Transmit Data Register Empty or USART TX FIFO Not Full Flag is set or not
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll ISR          TXE_TXFNF     LL_USART_IsActiveFlag_TXE_TXFNF
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXE_TXFNF(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_TXE_TXFNF) == (USART_ISR_TXE_TXFNF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART LIN Break Detection Flag is set or not
+  * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+  *         LIN feature is supported by the USARTx instance.
+  * @rmtoll ISR          LBDF          LL_USART_IsActiveFlag_LBD
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_LBD(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_LBDF) == (USART_ISR_LBDF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART CTS interrupt Flag is set or not
+  * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll ISR          CTSIF         LL_USART_IsActiveFlag_nCTS
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_nCTS(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_CTSIF) == (USART_ISR_CTSIF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART CTS Flag is set or not
+  * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll ISR          CTS           LL_USART_IsActiveFlag_CTS
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CTS(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_CTS) == (USART_ISR_CTS)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Receiver Time Out Flag is set or not
+  * @rmtoll ISR          RTOF          LL_USART_IsActiveFlag_RTO
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RTO(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_RTOF) == (USART_ISR_RTOF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART End Of Block Flag is set or not
+  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll ISR          EOBF          LL_USART_IsActiveFlag_EOB
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_EOB(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_EOBF) == (USART_ISR_EOBF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the SPI Slave Underrun error flag is set or not
+  * @note   Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
+  *         SPI Slave mode feature is supported by the USARTx instance.
+  * @rmtoll ISR          UDR           LL_USART_IsActiveFlag_UDR
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_UDR(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_UDR) == (USART_ISR_UDR)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Auto-Baud Rate Error Flag is set or not
+  * @note   Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
+  *         Auto Baud Rate detection feature is supported by the USARTx instance.
+  * @rmtoll ISR          ABRE          LL_USART_IsActiveFlag_ABRE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABRE(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_ABRE) == (USART_ISR_ABRE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Auto-Baud Rate Flag is set or not
+  * @note   Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
+  *         Auto Baud Rate detection feature is supported by the USARTx instance.
+  * @rmtoll ISR          ABRF          LL_USART_IsActiveFlag_ABR
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABR(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_ABRF) == (USART_ISR_ABRF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Busy Flag is set or not
+  * @rmtoll ISR          BUSY          LL_USART_IsActiveFlag_BUSY
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_BUSY(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_BUSY) == (USART_ISR_BUSY)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Character Match Flag is set or not
+  * @rmtoll ISR          CMF           LL_USART_IsActiveFlag_CM
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CM(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_CMF) == (USART_ISR_CMF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Send Break Flag is set or not
+  * @rmtoll ISR          SBKF          LL_USART_IsActiveFlag_SBK
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_SBK(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_SBKF) == (USART_ISR_SBKF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Receive Wake Up from mute mode Flag is set or not
+  * @rmtoll ISR          RWU           LL_USART_IsActiveFlag_RWU
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RWU(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_RWU) == (USART_ISR_RWU)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Wake Up from stop mode Flag is set or not
+  * @note   Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+  *         Wake-up from Stop mode feature is supported by the USARTx instance.
+  * @rmtoll ISR          WUF           LL_USART_IsActiveFlag_WKUP
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_WKUP(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_WUF) == (USART_ISR_WUF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Transmit Enable Acknowledge Flag is set or not
+  * @rmtoll ISR          TEACK         LL_USART_IsActiveFlag_TEACK
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TEACK(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_TEACK) == (USART_ISR_TEACK)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Receive Enable Acknowledge Flag is set or not
+  * @rmtoll ISR          REACK         LL_USART_IsActiveFlag_REACK
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_REACK(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_REACK) == (USART_ISR_REACK)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART TX FIFO Empty Flag is set or not
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll ISR          TXFE          LL_USART_IsActiveFlag_TXFE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXFE(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_TXFE) == (USART_ISR_TXFE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART RX FIFO Full Flag is set or not
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll ISR          RXFF          LL_USART_IsActiveFlag_RXFF
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXFF(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_RXFF) == (USART_ISR_RXFF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the Smartcard Transmission Complete Before Guard Time Flag is set or not
+  * @rmtoll ISR          TCBGT         LL_USART_IsActiveFlag_TCBGT
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TCBGT(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_TCBGT) == (USART_ISR_TCBGT)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART TX FIFO Threshold Flag is set or not
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll ISR          TXFT          LL_USART_IsActiveFlag_TXFT
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXFT(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_TXFT) == (USART_ISR_TXFT)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART RX FIFO Threshold Flag is set or not
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll ISR          RXFT          LL_USART_IsActiveFlag_RXFT
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXFT(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_RXFT) == (USART_ISR_RXFT)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear Parity Error Flag
+  * @rmtoll ICR          PECF          LL_USART_ClearFlag_PE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_PE(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_PECF);
+}
+
+/**
+  * @brief  Clear Framing Error Flag
+  * @rmtoll ICR          FECF          LL_USART_ClearFlag_FE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_FE(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_FECF);
+}
+
+/**
+  * @brief  Clear Noise Error detected Flag
+  * @rmtoll ICR          NECF          LL_USART_ClearFlag_NE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_NE(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_NECF);
+}
+
+/**
+  * @brief  Clear OverRun Error Flag
+  * @rmtoll ICR          ORECF         LL_USART_ClearFlag_ORE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_ORE(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_ORECF);
+}
+
+/**
+  * @brief  Clear IDLE line detected Flag
+  * @rmtoll ICR          IDLECF        LL_USART_ClearFlag_IDLE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_IDLE(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_IDLECF);
+}
+
+/**
+  * @brief  Clear TX FIFO Empty Flag
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll ICR          TXFECF        LL_USART_ClearFlag_TXFE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_TXFE(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_TXFECF);
+}
+
+/**
+  * @brief  Clear Transmission Complete Flag
+  * @rmtoll ICR          TCCF          LL_USART_ClearFlag_TC
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_TC(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_TCCF);
+}
+
+/**
+  * @brief  Clear Smartcard Transmission Complete Before Guard Time Flag
+  * @rmtoll ICR          TCBGTCF       LL_USART_ClearFlag_TCBGT
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_TCBGT(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_TCBGTCF);
+}
+
+/**
+  * @brief  Clear LIN Break Detection Flag
+  * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+  *         LIN feature is supported by the USARTx instance.
+  * @rmtoll ICR          LBDCF         LL_USART_ClearFlag_LBD
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_LBD(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_LBDCF);
+}
+
+/**
+  * @brief  Clear CTS Interrupt Flag
+  * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll ICR          CTSCF         LL_USART_ClearFlag_nCTS
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_nCTS(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_CTSCF);
+}
+
+/**
+  * @brief  Clear Receiver Time Out Flag
+  * @rmtoll ICR          RTOCF         LL_USART_ClearFlag_RTO
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_RTO(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_RTOCF);
+}
+
+/**
+  * @brief  Clear End Of Block Flag
+  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll ICR          EOBCF         LL_USART_ClearFlag_EOB
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_EOB(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_EOBCF);
+}
+
+/**
+  * @brief  Clear SPI Slave Underrun Flag
+  * @note   Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
+  *         SPI Slave mode feature is supported by the USARTx instance.
+  * @rmtoll ICR          UDRCF         LL_USART_ClearFlag_UDR
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_UDR(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_UDRCF);
+}
+
+/**
+  * @brief  Clear Character Match Flag
+  * @rmtoll ICR          CMCF          LL_USART_ClearFlag_CM
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_CM(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_CMCF);
+}
+
+/**
+  * @brief  Clear Wake Up from stop mode Flag
+  * @note   Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+  *         Wake-up from Stop mode feature is supported by the USARTx instance.
+  * @rmtoll ICR          WUCF          LL_USART_ClearFlag_WKUP
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_WKUP(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_WUCF);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EF_IT_Management IT_Management
+  * @{
+  */
+
+/**
+  * @brief  Enable IDLE Interrupt
+  * @rmtoll CR1          IDLEIE        LL_USART_EnableIT_IDLE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_IDLE(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_IDLEIE);
+}
+
+#define LL_USART_EnableIT_RXNE  LL_USART_EnableIT_RXNE_RXFNE /* Redefinition for legacy purpose */
+
+/**
+  * @brief  Enable RX Not Empty and RX FIFO Not Empty Interrupt
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR1        RXNEIE_RXFNEIE  LL_USART_EnableIT_RXNE_RXFNE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_RXNE_RXFNE(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RXNEIE_RXFNEIE);
+}
+
+/**
+  * @brief  Enable Transmission Complete Interrupt
+  * @rmtoll CR1          TCIE          LL_USART_EnableIT_TC
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_TC(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TCIE);
+}
+
+#define LL_USART_EnableIT_TXE  LL_USART_EnableIT_TXE_TXFNF /* Redefinition for legacy purpose */
+
+/**
+  * @brief  Enable TX Empty and TX FIFO Not Full Interrupt
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR1         TXEIE_TXFNFIE  LL_USART_EnableIT_TXE_TXFNF
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_TXE_TXFNF(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TXEIE_TXFNFIE);
+}
+
+/**
+  * @brief  Enable Parity Error Interrupt
+  * @rmtoll CR1          PEIE          LL_USART_EnableIT_PE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_PE(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_PEIE);
+}
+
+/**
+  * @brief  Enable Character Match Interrupt
+  * @rmtoll CR1          CMIE          LL_USART_EnableIT_CM
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_CM(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_CMIE);
+}
+
+/**
+  * @brief  Enable Receiver Timeout Interrupt
+  * @rmtoll CR1          RTOIE         LL_USART_EnableIT_RTO
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_RTO(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RTOIE);
+}
+
+/**
+  * @brief  Enable End Of Block Interrupt
+  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR1          EOBIE         LL_USART_EnableIT_EOB
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_EOB(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_EOBIE);
+}
+
+/**
+  * @brief  Enable TX FIFO Empty Interrupt
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR1          TXFEIE        LL_USART_EnableIT_TXFE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_TXFE(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TXFEIE);
+}
+
+/**
+  * @brief  Enable RX FIFO Full Interrupt
+  * @rmtoll CR1          RXFFIE        LL_USART_EnableIT_RXFF
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_RXFF(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RXFFIE);
+}
+
+/**
+  * @brief  Enable LIN Break Detection Interrupt
+  * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+  *         LIN feature is supported by the USARTx instance.
+  * @rmtoll CR2          LBDIE         LL_USART_EnableIT_LBD
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_LBD(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR2, USART_CR2_LBDIE);
+}
+
+/**
+  * @brief  Enable Error Interrupt
+  * @note   When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
+  *         error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_ISR register).
+  *           0: Interrupt is inhibited
+  *           1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_ISR register.
+  * @rmtoll CR3          EIE           LL_USART_EnableIT_ERROR
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_ERROR(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_EIE);
+}
+
+/**
+  * @brief  Enable CTS Interrupt
+  * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll CR3          CTSIE         LL_USART_EnableIT_CTS
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_CTS(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_CTSIE);
+}
+
+/**
+  * @brief  Enable Wake Up from Stop Mode Interrupt
+  * @note   Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+  *         Wake-up from Stop mode feature is supported by the USARTx instance.
+  * @rmtoll CR3          WUFIE         LL_USART_EnableIT_WKUP
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_WKUP(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_WUFIE);
+}
+
+/**
+  * @brief  Enable TX FIFO Threshold Interrupt
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR3          TXFTIE        LL_USART_EnableIT_TXFT
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_TXFT(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_TXFTIE);
+}
+
+/**
+  * @brief  Enable Smartcard Transmission Complete Before Guard Time Interrupt
+  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR3          TCBGTIE       LL_USART_EnableIT_TCBGT
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_TCBGT(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_TCBGTIE);
+}
+
+/**
+  * @brief  Enable RX FIFO Threshold Interrupt
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR3          RXFTIE        LL_USART_EnableIT_RXFT
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_RXFT(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_RXFTIE);
+}
+
+/**
+  * @brief  Disable IDLE Interrupt
+  * @rmtoll CR1          IDLEIE        LL_USART_DisableIT_IDLE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_IDLE(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_IDLEIE);
+}
+
+#define LL_USART_DisableIT_RXNE  LL_USART_DisableIT_RXNE_RXFNE /* Redefinition for legacy purpose */
+
+/**
+  * @brief  Disable RX Not Empty and RX FIFO Not Empty Interrupt
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR1        RXNEIE_RXFNEIE  LL_USART_DisableIT_RXNE_RXFNE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_RXNE_RXFNE(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RXNEIE_RXFNEIE);
+}
+
+/**
+  * @brief  Disable Transmission Complete Interrupt
+  * @rmtoll CR1          TCIE          LL_USART_DisableIT_TC
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_TC(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TCIE);
+}
+
+#define LL_USART_DisableIT_TXE  LL_USART_DisableIT_TXE_TXFNF /* Redefinition for legacy purpose */
+
+/**
+  * @brief  Disable TX Empty and TX FIFO Not Full Interrupt
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR1        TXEIE_TXFNFIE  LL_USART_DisableIT_TXE_TXFNF
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_TXE_TXFNF(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TXEIE_TXFNFIE);
+}
+
+/**
+  * @brief  Disable Parity Error Interrupt
+  * @rmtoll CR1          PEIE          LL_USART_DisableIT_PE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_PE(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_PEIE);
+}
+
+/**
+  * @brief  Disable Character Match Interrupt
+  * @rmtoll CR1          CMIE          LL_USART_DisableIT_CM
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_CM(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_CMIE);
+}
+
+/**
+  * @brief  Disable Receiver Timeout Interrupt
+  * @rmtoll CR1          RTOIE         LL_USART_DisableIT_RTO
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_RTO(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RTOIE);
+}
+
+/**
+  * @brief  Disable End Of Block Interrupt
+  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR1          EOBIE         LL_USART_DisableIT_EOB
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_EOB(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_EOBIE);
+}
+
+/**
+  * @brief  Disable TX FIFO Empty Interrupt
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR1          TXFEIE        LL_USART_DisableIT_TXFE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_TXFE(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TXFEIE);
+}
+
+/**
+  * @brief  Disable RX FIFO Full Interrupt
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR1          RXFFIE        LL_USART_DisableIT_RXFF
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_RXFF(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RXFFIE);
+}
+
+/**
+  * @brief  Disable LIN Break Detection Interrupt
+  * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+  *         LIN feature is supported by the USARTx instance.
+  * @rmtoll CR2          LBDIE         LL_USART_DisableIT_LBD
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_LBD(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR2, USART_CR2_LBDIE);
+}
+
+/**
+  * @brief  Disable Error Interrupt
+  * @note   When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
+  *         error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_ISR register).
+  *           0: Interrupt is inhibited
+  *           1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_ISR register.
+  * @rmtoll CR3          EIE           LL_USART_DisableIT_ERROR
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_ERROR(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_EIE);
+}
+
+/**
+  * @brief  Disable CTS Interrupt
+  * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll CR3          CTSIE         LL_USART_DisableIT_CTS
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_CTS(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_CTSIE);
+}
+
+/**
+  * @brief  Disable Wake Up from Stop Mode Interrupt
+  * @note   Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+  *         Wake-up from Stop mode feature is supported by the USARTx instance.
+  * @rmtoll CR3          WUFIE         LL_USART_DisableIT_WKUP
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_WKUP(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_WUFIE);
+}
+
+/**
+  * @brief  Disable TX FIFO Threshold Interrupt
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR3          TXFTIE        LL_USART_DisableIT_TXFT
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_TXFT(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_TXFTIE);
+}
+
+/**
+  * @brief  Disable Smartcard Transmission Complete Before Guard Time Interrupt
+  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR3          TCBGTIE       LL_USART_DisableIT_TCBGT
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_TCBGT(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_TCBGTIE);
+}
+
+/**
+  * @brief  Disable RX FIFO Threshold Interrupt
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR3          RXFTIE        LL_USART_DisableIT_RXFT
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_RXFT(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_RXFTIE);
+}
+
+/**
+  * @brief  Check if the USART IDLE Interrupt  source is enabled or disabled.
+  * @rmtoll CR1          IDLEIE        LL_USART_IsEnabledIT_IDLE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_IDLE(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE)) ? 1UL : 0UL);
+}
+
+#define LL_USART_IsEnabledIT_RXNE  LL_USART_IsEnabledIT_RXNE_RXFNE /* Redefinition for legacy purpose */
+
+/**
+  * @brief  Check if the USART RX Not Empty and USART RX FIFO Not Empty Interrupt is enabled or disabled.
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR1        RXNEIE_RXFNEIE  LL_USART_IsEnabledIT_RXNE_RXFNE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXNE_RXFNE(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR1, USART_CR1_RXNEIE_RXFNEIE) == (USART_CR1_RXNEIE_RXFNEIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Transmission Complete Interrupt is enabled or disabled.
+  * @rmtoll CR1          TCIE          LL_USART_IsEnabledIT_TC
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TC(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE)) ? 1UL : 0UL);
+}
+
+#define LL_USART_IsEnabledIT_TXE  LL_USART_IsEnabledIT_TXE_TXFNF /* Redefinition for legacy purpose */
+
+/**
+  * @brief  Check if the USART TX Empty and USART TX FIFO Not Full Interrupt is enabled or disabled
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR1         TXEIE_TXFNFIE  LL_USART_IsEnabledIT_TXE_TXFNF
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXE_TXFNF(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR1, USART_CR1_TXEIE_TXFNFIE) == (USART_CR1_TXEIE_TXFNFIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Parity Error Interrupt is enabled or disabled.
+  * @rmtoll CR1          PEIE          LL_USART_IsEnabledIT_PE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_PE(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Character Match Interrupt is enabled or disabled.
+  * @rmtoll CR1          CMIE          LL_USART_IsEnabledIT_CM
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CM(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR1, USART_CR1_CMIE) == (USART_CR1_CMIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Receiver Timeout Interrupt is enabled or disabled.
+  * @rmtoll CR1          RTOIE         LL_USART_IsEnabledIT_RTO
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RTO(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR1, USART_CR1_RTOIE) == (USART_CR1_RTOIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART End Of Block Interrupt is enabled or disabled.
+  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR1          EOBIE         LL_USART_IsEnabledIT_EOB
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_EOB(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR1, USART_CR1_EOBIE) == (USART_CR1_EOBIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART TX FIFO Empty Interrupt is enabled or disabled
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR1          TXFEIE        LL_USART_IsEnabledIT_TXFE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXFE(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR1, USART_CR1_TXFEIE) == (USART_CR1_TXFEIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART RX FIFO Full Interrupt is enabled or disabled
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR1          RXFFIE        LL_USART_IsEnabledIT_RXFF
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXFF(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR1, USART_CR1_RXFFIE) == (USART_CR1_RXFFIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART LIN Break Detection Interrupt is enabled or disabled.
+  * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+  *         LIN feature is supported by the USARTx instance.
+  * @rmtoll CR2          LBDIE         LL_USART_IsEnabledIT_LBD
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_LBD(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR2, USART_CR2_LBDIE) == (USART_CR2_LBDIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Error Interrupt is enabled or disabled.
+  * @rmtoll CR3          EIE           LL_USART_IsEnabledIT_ERROR
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_ERROR(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART CTS Interrupt is enabled or disabled.
+  * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll CR3          CTSIE         LL_USART_IsEnabledIT_CTS
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CTS(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Wake Up from Stop Mode Interrupt is enabled or disabled.
+  * @note   Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+  *         Wake-up from Stop mode feature is supported by the USARTx instance.
+  * @rmtoll CR3          WUFIE         LL_USART_IsEnabledIT_WKUP
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_WKUP(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR3, USART_CR3_WUFIE) == (USART_CR3_WUFIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if USART TX FIFO Threshold Interrupt is enabled or disabled
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR3          TXFTIE        LL_USART_IsEnabledIT_TXFT
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXFT(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR3, USART_CR3_TXFTIE) == (USART_CR3_TXFTIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the Smartcard Transmission Complete Before Guard Time Interrupt is enabled or disabled.
+  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR3          TCBGTIE       LL_USART_IsEnabledIT_TCBGT
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TCBGT(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR3, USART_CR3_TCBGTIE) == (USART_CR3_TCBGTIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if USART RX FIFO Threshold Interrupt is enabled or disabled
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR3          RXFTIE        LL_USART_IsEnabledIT_RXFT
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXFT(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR3, USART_CR3_RXFTIE) == (USART_CR3_RXFTIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EF_DMA_Management DMA_Management
+  * @{
+  */
+
+/**
+  * @brief  Enable DMA Mode for reception
+  * @rmtoll CR3          DMAR          LL_USART_EnableDMAReq_RX
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableDMAReq_RX(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_DMAR);
+}
+
+/**
+  * @brief  Disable DMA Mode for reception
+  * @rmtoll CR3          DMAR          LL_USART_DisableDMAReq_RX
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableDMAReq_RX(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_DMAR);
+}
+
+/**
+  * @brief  Check if DMA Mode is enabled for reception
+  * @rmtoll CR3          DMAR          LL_USART_IsEnabledDMAReq_RX
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_RX(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable DMA Mode for transmission
+  * @rmtoll CR3          DMAT          LL_USART_EnableDMAReq_TX
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableDMAReq_TX(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_DMAT);
+}
+
+/**
+  * @brief  Disable DMA Mode for transmission
+  * @rmtoll CR3          DMAT          LL_USART_DisableDMAReq_TX
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableDMAReq_TX(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_DMAT);
+}
+
+/**
+  * @brief  Check if DMA Mode is enabled for transmission
+  * @rmtoll CR3          DMAT          LL_USART_IsEnabledDMAReq_TX
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_TX(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable DMA Disabling on Reception Error
+  * @rmtoll CR3          DDRE          LL_USART_EnableDMADeactOnRxErr
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableDMADeactOnRxErr(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_DDRE);
+}
+
+/**
+  * @brief  Disable DMA Disabling on Reception Error
+  * @rmtoll CR3          DDRE          LL_USART_DisableDMADeactOnRxErr
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableDMADeactOnRxErr(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_DDRE);
+}
+
+/**
+  * @brief  Indicate if DMA Disabling on Reception Error is disabled
+  * @rmtoll CR3          DDRE          LL_USART_IsEnabledDMADeactOnRxErr
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledDMADeactOnRxErr(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR3, USART_CR3_DDRE) == (USART_CR3_DDRE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get the data register address used for DMA transfer
+  * @rmtoll RDR          RDR           LL_USART_DMA_GetRegAddr\n
+  * @rmtoll TDR          TDR           LL_USART_DMA_GetRegAddr
+  * @param  USARTx USART Instance
+  * @param  Direction This parameter can be one of the following values:
+  *         @arg @ref LL_USART_DMA_REG_DATA_TRANSMIT
+  *         @arg @ref LL_USART_DMA_REG_DATA_RECEIVE
+  * @retval Address of data register
+  */
+__STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr(const USART_TypeDef *USARTx, uint32_t Direction)
+{
+  uint32_t data_reg_addr;
+
+  if (Direction == LL_USART_DMA_REG_DATA_TRANSMIT)
+  {
+    /* return address of TDR register */
+    data_reg_addr = (uint32_t) &(USARTx->TDR);
+  }
+  else
+  {
+    /* return address of RDR register */
+    data_reg_addr = (uint32_t) &(USARTx->RDR);
+  }
+
+  return data_reg_addr;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EF_Data_Management Data_Management
+  * @{
+  */
+
+/**
+  * @brief  Read Receiver Data register (Receive Data value, 8 bits)
+  * @rmtoll RDR          RDR           LL_USART_ReceiveData8
+  * @param  USARTx USART Instance
+  * @retval Value between Min_Data=0x00 and Max_Data=0xFF
+  */
+__STATIC_INLINE uint8_t LL_USART_ReceiveData8(const USART_TypeDef *USARTx)
+{
+  return (uint8_t)(READ_BIT(USARTx->RDR, USART_RDR_RDR) & 0xFFU);
+}
+
+/**
+  * @brief  Read Receiver Data register (Receive Data value, 9 bits)
+  * @rmtoll RDR          RDR           LL_USART_ReceiveData9
+  * @param  USARTx USART Instance
+  * @retval Value between Min_Data=0x00 and Max_Data=0x1FF
+  */
+__STATIC_INLINE uint16_t LL_USART_ReceiveData9(const USART_TypeDef *USARTx)
+{
+  return (uint16_t)(READ_BIT(USARTx->RDR, USART_RDR_RDR));
+}
+
+/**
+  * @brief  Write in Transmitter Data Register (Transmit Data value, 8 bits)
+  * @rmtoll TDR          TDR           LL_USART_TransmitData8
+  * @param  USARTx USART Instance
+  * @param  Value between Min_Data=0x00 and Max_Data=0xFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_TransmitData8(USART_TypeDef *USARTx, uint8_t Value)
+{
+  USARTx->TDR = Value;
+}
+
+/**
+  * @brief  Write in Transmitter Data Register (Transmit Data value, 9 bits)
+  * @rmtoll TDR          TDR           LL_USART_TransmitData9
+  * @param  USARTx USART Instance
+  * @param  Value between Min_Data=0x00 and Max_Data=0x1FF
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_TransmitData9(USART_TypeDef *USARTx, uint16_t Value)
+{
+  USARTx->TDR = (uint16_t)(Value & 0x1FFUL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EF_Execution Execution
+  * @{
+  */
+
+/**
+  * @brief  Request an Automatic Baud Rate measurement on next received data frame
+  * @note   Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
+  *         Auto Baud Rate detection feature is supported by the USARTx instance.
+  * @rmtoll RQR          ABRRQ         LL_USART_RequestAutoBaudRate
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_RequestAutoBaudRate(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_ABRRQ);
+}
+
+/**
+  * @brief  Request Break sending
+  * @rmtoll RQR          SBKRQ         LL_USART_RequestBreakSending
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_RequestBreakSending(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_SBKRQ);
+}
+
+/**
+  * @brief  Put USART in mute mode and set the RWU flag
+  * @rmtoll RQR          MMRQ          LL_USART_RequestEnterMuteMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_RequestEnterMuteMode(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_MMRQ);
+}
+
+/**
+  * @brief  Request a Receive Data and FIFO flush
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @note   Allows to discard the received data without reading them, and avoid an overrun
+  *         condition.
+  * @rmtoll RQR          RXFRQ         LL_USART_RequestRxDataFlush
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_RequestRxDataFlush(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_RXFRQ);
+}
+
+/**
+  * @brief  Request a Transmit data and FIFO flush
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll RQR          TXFRQ         LL_USART_RequestTxDataFlush
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_RequestTxDataFlush(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_TXFRQ);
+}
+
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup USART_LL_EF_Init Initialization and de-initialization functions
+  * @{
+  */
+ErrorStatus LL_USART_DeInit(const USART_TypeDef *USARTx);
+ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, const LL_USART_InitTypeDef *USART_InitStruct);
+void        LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct);
+ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, const LL_USART_ClockInitTypeDef *USART_ClockInitStruct);
+void        LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct);
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* USART1 || USART2 || USART3 || USART6 || UART4 || UART5 || UART7 || UART8 || UART9 || USART10 */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32H7xx_LL_USART_H */
+
diff --git a/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c b/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c
new file mode 100644
index 0000000..950ea15
--- /dev/null
+++ b/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c
@@ -0,0 +1,6204 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_fdcan.c
+  * @author  MCD Application Team
+  * @brief   FDCAN HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Flexible DataRate Controller Area Network
+  *          (FDCAN) peripheral:
+  *           + Initialization and de-initialization functions
+  *           + IO operation functions
+  *           + Peripheral Configuration and Control functions
+  *           + Peripheral State and Error functions
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+                        ##### How to use this driver #####
+  ==============================================================================
+    [..]
+      (#) Initialize the FDCAN peripheral using HAL_FDCAN_Init function.
+
+      (#) If needed , configure the reception filters and optional features using
+          the following configuration functions:
+            (++) HAL_FDCAN_ConfigClockCalibration
+            (++) HAL_FDCAN_ConfigFilter
+            (++) HAL_FDCAN_ConfigGlobalFilter
+            (++) HAL_FDCAN_ConfigExtendedIdMask
+            (++) HAL_FDCAN_ConfigRxFifoOverwrite
+            (++) HAL_FDCAN_ConfigFifoWatermark
+            (++) HAL_FDCAN_ConfigRamWatchdog
+            (++) HAL_FDCAN_ConfigTimestampCounter
+            (++) HAL_FDCAN_EnableTimestampCounter
+            (++) HAL_FDCAN_DisableTimestampCounter
+            (++) HAL_FDCAN_ConfigTimeoutCounter
+            (++) HAL_FDCAN_EnableTimeoutCounter
+            (++) HAL_FDCAN_DisableTimeoutCounter
+            (++) HAL_FDCAN_ConfigTxDelayCompensation
+            (++) HAL_FDCAN_EnableTxDelayCompensation
+            (++) HAL_FDCAN_DisableTxDelayCompensation
+            (++) HAL_FDCAN_EnableISOMode
+            (++) HAL_FDCAN_DisableISOMode
+            (++) HAL_FDCAN_EnableEdgeFiltering
+            (++) HAL_FDCAN_DisableEdgeFiltering
+            (++) HAL_FDCAN_TT_ConfigOperation
+            (++) HAL_FDCAN_TT_ConfigReferenceMessage
+            (++) HAL_FDCAN_TT_ConfigTrigger
+
+      (#) Start the FDCAN module using HAL_FDCAN_Start function. At this level
+          the node is active on the bus: it can send and receive messages.
+
+      (#) The following Tx control functions can only be called when the FDCAN
+          module is started:
+            (++) HAL_FDCAN_AddMessageToTxFifoQ
+            (++) HAL_FDCAN_EnableTxBufferRequest
+            (++) HAL_FDCAN_AbortTxRequest
+
+      (#) After having submitted a Tx request in Tx Fifo or Queue, it is possible to
+          get Tx buffer location used to place the Tx request thanks to
+          HAL_FDCAN_GetLatestTxFifoQRequestBuffer API.
+          It is then possible to abort later on the corresponding Tx Request using
+          HAL_FDCAN_AbortTxRequest API.
+
+      (#) When a message is received into the FDCAN message RAM, it can be
+          retrieved using the HAL_FDCAN_GetRxMessage function.
+
+      (#) Calling the HAL_FDCAN_Stop function stops the FDCAN module by entering
+          it to initialization mode and re-enabling access to configuration
+          registers through the configuration functions listed here above.
+
+      (#) All other control functions can be called any time after initialization
+          phase, no matter if the FDCAN module is started or stopped.
+
+      *** Polling mode operation ***
+      ==============================
+
+    [..]
+        (#) Reception and transmission states can be monitored via the following
+            functions:
+              (++) HAL_FDCAN_IsRxBufferMessageAvailable
+              (++) HAL_FDCAN_IsTxBufferMessagePending
+              (++) HAL_FDCAN_GetRxFifoFillLevel
+              (++) HAL_FDCAN_GetTxFifoFreeLevel
+
+      *** Interrupt mode operation ***
+      ================================
+      [..]
+        (#) There are two interrupt lines: line 0 and 1.
+            By default, all interrupts are assigned to line 0. Interrupt lines
+            can be configured using HAL_FDCAN_ConfigInterruptLines function.
+
+        (#) Notifications are activated using HAL_FDCAN_ActivateNotification
+            function. Then, the process can be controlled through one of the
+            available user callbacks: HAL_FDCAN_xxxCallback.
+
+  *** Callback registration ***
+  =============================================
+
+  The compilation define USE_HAL_FDCAN_REGISTER_CALLBACKS when set to 1
+  allows the user to configure dynamically the driver callbacks.
+  Use Function HAL_FDCAN_RegisterCallback() or HAL_FDCAN_RegisterXXXCallback()
+  to register an interrupt callback.
+
+  Function HAL_FDCAN_RegisterCallback() allows to register following callbacks:
+    (+) TxFifoEmptyCallback          : Tx Fifo Empty Callback.
+    (+) RxBufferNewMessageCallback   : Rx Buffer New Message Callback.
+    (+) HighPriorityMessageCallback  : High Priority Message Callback.
+    (+) TimestampWraparoundCallback  : Timestamp Wraparound Callback.
+    (+) TimeoutOccurredCallback      : Timeout Occurred Callback.
+    (+) ErrorCallback                : Error Callback.
+    (+) MspInitCallback              : FDCAN MspInit.
+    (+) MspDeInitCallback            : FDCAN MspDeInit.
+  This function takes as parameters the HAL peripheral handle, the Callback ID
+  and a pointer to the user callback function.
+
+  For specific callbacks ClockCalibrationCallback, TxEventFifoCallback, RxFifo0Callback, RxFifo1Callback,
+  TxBufferCompleteCallback, TxBufferAbortCallback, ErrorStatusCallback, TT_ScheduleSyncCallback, TT_TimeMarkCallback,
+  TT_StopWatchCallback and TT_GlobalTimeCallback, use dedicated register callbacks :
+  respectively HAL_FDCAN_RegisterClockCalibrationCallback(), HAL_FDCAN_RegisterTxEventFifoCallback(),
+  HAL_FDCAN_RegisterRxFifo0Callback(), HAL_FDCAN_RegisterRxFifo1Callback(),
+  HAL_FDCAN_RegisterTxBufferCompleCallback(), HAL_FDCAN_RegisterTxBufferAbortCallback(),
+  HAL_FDCAN_RegisterErrorStatusCallback(), HAL_FDCAN_TT_RegisterScheduleSyncCallback(),
+  HAL_FDCAN_TT_RegisterTimeMarkCallback(), HAL_FDCAN_TT_RegisterStopWatchCallback() and
+  HAL_FDCAN_TT_RegisterGlobalTimeCallback().
+
+  Use function HAL_FDCAN_UnRegisterCallback() to reset a callback to the default
+  weak function.
+  HAL_FDCAN_UnRegisterCallback takes as parameters the HAL peripheral handle,
+  and the Callback ID.
+  This function allows to reset following callbacks:
+    (+) TxFifoEmptyCallback          : Tx Fifo Empty Callback.
+    (+) RxBufferNewMessageCallback   : Rx Buffer New Message Callback.
+    (+) HighPriorityMessageCallback  : High Priority Message Callback.
+    (+) TimestampWraparoundCallback  : Timestamp Wraparound Callback.
+    (+) TimeoutOccurredCallback      : Timeout Occurred Callback.
+    (+) ErrorCallback                : Error Callback.
+    (+) MspInitCallback              : FDCAN MspInit.
+    (+) MspDeInitCallback            : FDCAN MspDeInit.
+
+  For specific callbacks ClockCalibrationCallback, TxEventFifoCallback, RxFifo0Callback,
+  RxFifo1Callback, TxBufferCompleteCallback, TxBufferAbortCallback, TT_ScheduleSyncCallback,
+  TT_TimeMarkCallback, TT_StopWatchCallback and TT_GlobalTimeCallback, use dedicated
+  register callbacks : respectively HAL_FDCAN_UnRegisterClockCalibrationCallback(),
+  HAL_FDCAN_UnRegisterTxEventFifoCallback(), HAL_FDCAN_UnRegisterRxFifo0Callback(),
+  HAL_FDCAN_UnRegisterRxFifo1Callback(), HAL_FDCAN_UnRegisterTxBufferCompleCallback(),
+  HAL_FDCAN_UnRegisterTxBufferAbortCallback(), HAL_FDCAN_UnRegisterErrorStatusCallback(),
+  HAL_FDCAN_TT_UnRegisterScheduleSyncCallback(), HAL_FDCAN_TT_UnRegisterTimeMarkCallback(),
+  HAL_FDCAN_TT_UnRegisterStopWatchCallback() and HAL_FDCAN_TT_UnRegisterGlobalTimeCallback().
+
+  By default, after the HAL_FDCAN_Init() and when the state is HAL_FDCAN_STATE_RESET,
+  all callbacks are set to the corresponding weak functions:
+  examples HAL_FDCAN_ErrorCallback().
+  Exception done for MspInit and MspDeInit functions that are
+  reset to the legacy weak function in the HAL_FDCAN_Init()/ HAL_FDCAN_DeInit() only when
+  these callbacks are null (not registered beforehand).
+  if not, MspInit or MspDeInit are not null, the HAL_FDCAN_Init()/ HAL_FDCAN_DeInit()
+  keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
+
+  Callbacks can be registered/unregistered in HAL_FDCAN_STATE_READY state only.
+  Exception done MspInit/MspDeInit that can be registered/unregistered
+  in HAL_FDCAN_STATE_READY or HAL_FDCAN_STATE_RESET state,
+  thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
+  In that case first register the MspInit/MspDeInit user callbacks
+  using HAL_FDCAN_RegisterCallback() before calling HAL_FDCAN_DeInit()
+  or HAL_FDCAN_Init() function.
+
+  When The compilation define USE_HAL_FDCAN_REGISTER_CALLBACKS is set to 0 or
+  not defined, the callback registration feature is not available and all callbacks
+  are set to the corresponding weak functions.
+
+  @endverbatim
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal.h"
+
+#if defined(FDCAN1)
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup FDCAN FDCAN
+  * @brief FDCAN HAL module driver
+  * @{
+  */
+
+#ifdef HAL_FDCAN_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @addtogroup FDCAN_Private_Constants
+  * @{
+  */
+#define FDCAN_TIMEOUT_VALUE 10U
+#define FDCAN_TIMEOUT_COUNT 50U
+
+#define FDCAN_TX_EVENT_FIFO_MASK (FDCAN_IR_TEFL | FDCAN_IR_TEFF | FDCAN_IR_TEFW | FDCAN_IR_TEFN)
+#define FDCAN_RX_FIFO0_MASK (FDCAN_IR_RF0L | FDCAN_IR_RF0F | FDCAN_IR_RF0W | FDCAN_IR_RF0N)
+#define FDCAN_RX_FIFO1_MASK (FDCAN_IR_RF1L | FDCAN_IR_RF1F | FDCAN_IR_RF1W | FDCAN_IR_RF1N)
+#define FDCAN_ERROR_MASK (FDCAN_IR_ELO | FDCAN_IR_WDI | FDCAN_IR_PEA | FDCAN_IR_PED | FDCAN_IR_ARA)
+#define FDCAN_ERROR_STATUS_MASK (FDCAN_IR_EP | FDCAN_IR_EW | FDCAN_IR_BO)
+#define FDCAN_TT_SCHEDULE_SYNC_MASK (FDCAN_TTIR_SBC | FDCAN_TTIR_SMC | FDCAN_TTIR_CSM | FDCAN_TTIR_SOG)
+#define FDCAN_TT_TIME_MARK_MASK (FDCAN_TTIR_RTMI | FDCAN_TTIR_TTMI)
+#define FDCAN_TT_GLOBAL_TIME_MASK (FDCAN_TTIR_GTW | FDCAN_TTIR_GTD)
+#define FDCAN_TT_DISTURBING_ERROR_MASK (FDCAN_TTIR_GTE | FDCAN_TTIR_TXU | FDCAN_TTIR_TXO | \
+                                        FDCAN_TTIR_SE1 | FDCAN_TTIR_SE2 | FDCAN_TTIR_ELC)
+#define FDCAN_TT_FATAL_ERROR_MASK (FDCAN_TTIR_IWT | FDCAN_TTIR_WT | FDCAN_TTIR_AW | FDCAN_TTIR_CER)
+
+#define FDCAN_ELEMENT_MASK_STDID ((uint32_t)0x1FFC0000U) /* Standard Identifier         */
+#define FDCAN_ELEMENT_MASK_EXTID ((uint32_t)0x1FFFFFFFU) /* Extended Identifier         */
+#define FDCAN_ELEMENT_MASK_RTR   ((uint32_t)0x20000000U) /* Remote Transmission Request */
+#define FDCAN_ELEMENT_MASK_XTD   ((uint32_t)0x40000000U) /* Extended Identifier         */
+#define FDCAN_ELEMENT_MASK_ESI   ((uint32_t)0x80000000U) /* Error State Indicator       */
+#define FDCAN_ELEMENT_MASK_TS    ((uint32_t)0x0000FFFFU) /* Timestamp                   */
+#define FDCAN_ELEMENT_MASK_DLC   ((uint32_t)0x000F0000U) /* Data Length Code            */
+#define FDCAN_ELEMENT_MASK_BRS   ((uint32_t)0x00100000U) /* Bit Rate Switch             */
+#define FDCAN_ELEMENT_MASK_FDF   ((uint32_t)0x00200000U) /* FD Format                   */
+#define FDCAN_ELEMENT_MASK_EFC   ((uint32_t)0x00800000U) /* Event FIFO Control          */
+#define FDCAN_ELEMENT_MASK_MM    ((uint32_t)0xFF000000U) /* Message Marker              */
+#define FDCAN_ELEMENT_MASK_FIDX  ((uint32_t)0x7F000000U) /* Filter Index                */
+#define FDCAN_ELEMENT_MASK_ANMF  ((uint32_t)0x80000000U) /* Accepted Non-matching Frame */
+#define FDCAN_ELEMENT_MASK_ET    ((uint32_t)0x00C00000U) /* Event type                  */
+
+#define FDCAN_MESSAGE_RAM_SIZE 0x2800U
+#define FDCAN_MESSAGE_RAM_END_ADDRESS (SRAMCAN_BASE + FDCAN_MESSAGE_RAM_SIZE - 0x4U) /* The Message RAM has a width of 4 Bytes */
+
+/**
+  * @}
+  */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+static const uint8_t DLCtoBytes[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 12, 16, 20, 24, 32, 48, 64};
+
+/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup FDCAN_Private_Functions_Prototypes
+  * @{
+  */
+static HAL_StatusTypeDef FDCAN_CalcultateRamBlockAddresses(FDCAN_HandleTypeDef *hfdcan);
+static void FDCAN_CopyMessageToRAM(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData, uint32_t BufferIndex);
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup FDCAN_Exported_Functions FDCAN Exported Functions
+  * @{
+  */
+
+/** @defgroup FDCAN_Exported_Functions_Group1 Initialization and de-initialization functions
+ *  @brief    Initialization and Configuration functions
+ *
+@verbatim
+  ==============================================================================
+              ##### Initialization and de-initialization functions #####
+  ==============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Initialize and configure the FDCAN.
+      (+) De-initialize the FDCAN.
+      (+) Enter FDCAN peripheral in power down mode.
+      (+) Exit power down mode.
+      (+) Register callbacks.
+      (+) Unregister callbacks.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the FDCAN peripheral according to the specified
+  *         parameters in the FDCAN_InitTypeDef structure.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_Init(FDCAN_HandleTypeDef *hfdcan)
+{
+  uint32_t tickstart;
+  HAL_StatusTypeDef status;
+  const uint32_t CvtEltSize[] = {0, 0, 0, 0, 0, 1, 2, 3, 4, 0, 5, 0, 0, 0, 6, 0, 0, 0, 7};
+
+  /* Check FDCAN handle */
+  if (hfdcan == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check FDCAN instance */
+  if (hfdcan->Instance == FDCAN1)
+  {
+    hfdcan->ttcan = (TTCAN_TypeDef *)((uint32_t)hfdcan->Instance + 0x100U);
+  }
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_ALL_INSTANCE(hfdcan->Instance));
+  assert_param(IS_FDCAN_FRAME_FORMAT(hfdcan->Init.FrameFormat));
+  assert_param(IS_FDCAN_MODE(hfdcan->Init.Mode));
+  assert_param(IS_FUNCTIONAL_STATE(hfdcan->Init.AutoRetransmission));
+  assert_param(IS_FUNCTIONAL_STATE(hfdcan->Init.TransmitPause));
+  assert_param(IS_FUNCTIONAL_STATE(hfdcan->Init.ProtocolException));
+  assert_param(IS_FDCAN_NOMINAL_PRESCALER(hfdcan->Init.NominalPrescaler));
+  assert_param(IS_FDCAN_NOMINAL_SJW(hfdcan->Init.NominalSyncJumpWidth));
+  assert_param(IS_FDCAN_NOMINAL_TSEG1(hfdcan->Init.NominalTimeSeg1));
+  assert_param(IS_FDCAN_NOMINAL_TSEG2(hfdcan->Init.NominalTimeSeg2));
+  if (hfdcan->Init.FrameFormat == FDCAN_FRAME_FD_BRS)
+  {
+    assert_param(IS_FDCAN_DATA_PRESCALER(hfdcan->Init.DataPrescaler));
+    assert_param(IS_FDCAN_DATA_SJW(hfdcan->Init.DataSyncJumpWidth));
+    assert_param(IS_FDCAN_DATA_TSEG1(hfdcan->Init.DataTimeSeg1));
+    assert_param(IS_FDCAN_DATA_TSEG2(hfdcan->Init.DataTimeSeg2));
+  }
+  assert_param(IS_FDCAN_MAX_VALUE(hfdcan->Init.StdFiltersNbr, 128U));
+  assert_param(IS_FDCAN_MAX_VALUE(hfdcan->Init.ExtFiltersNbr, 64U));
+  assert_param(IS_FDCAN_MAX_VALUE(hfdcan->Init.RxFifo0ElmtsNbr, 64U));
+  if (hfdcan->Init.RxFifo0ElmtsNbr > 0U)
+  {
+    assert_param(IS_FDCAN_DATA_SIZE(hfdcan->Init.RxFifo0ElmtSize));
+  }
+  assert_param(IS_FDCAN_MAX_VALUE(hfdcan->Init.RxFifo1ElmtsNbr, 64U));
+  if (hfdcan->Init.RxFifo1ElmtsNbr > 0U)
+  {
+    assert_param(IS_FDCAN_DATA_SIZE(hfdcan->Init.RxFifo1ElmtSize));
+  }
+  assert_param(IS_FDCAN_MAX_VALUE(hfdcan->Init.RxBuffersNbr, 64U));
+  if (hfdcan->Init.RxBuffersNbr > 0U)
+  {
+    assert_param(IS_FDCAN_DATA_SIZE(hfdcan->Init.RxBufferSize));
+  }
+  assert_param(IS_FDCAN_MAX_VALUE(hfdcan->Init.TxEventsNbr, 32U));
+  assert_param(IS_FDCAN_MAX_VALUE((hfdcan->Init.TxBuffersNbr + hfdcan->Init.TxFifoQueueElmtsNbr), 32U));
+  if (hfdcan->Init.TxFifoQueueElmtsNbr > 0U)
+  {
+    assert_param(IS_FDCAN_TX_FIFO_QUEUE_MODE(hfdcan->Init.TxFifoQueueMode));
+  }
+  if ((hfdcan->Init.TxBuffersNbr + hfdcan->Init.TxFifoQueueElmtsNbr) > 0U)
+  {
+    assert_param(IS_FDCAN_DATA_SIZE(hfdcan->Init.TxElmtSize));
+  }
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+  if (hfdcan->State == HAL_FDCAN_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    hfdcan->Lock = HAL_UNLOCKED;
+
+    /* Reset callbacks to legacy functions */
+    hfdcan->ClockCalibrationCallback    = HAL_FDCAN_ClockCalibrationCallback;    /* Legacy weak ClockCalibrationCallback    */
+    hfdcan->TxEventFifoCallback         = HAL_FDCAN_TxEventFifoCallback;         /* Legacy weak TxEventFifoCallback         */
+    hfdcan->RxFifo0Callback             = HAL_FDCAN_RxFifo0Callback;             /* Legacy weak RxFifo0Callback             */
+    hfdcan->RxFifo1Callback             = HAL_FDCAN_RxFifo1Callback;             /* Legacy weak RxFifo1Callback             */
+    hfdcan->TxFifoEmptyCallback         = HAL_FDCAN_TxFifoEmptyCallback;         /* Legacy weak TxFifoEmptyCallback         */
+    hfdcan->TxBufferCompleteCallback    = HAL_FDCAN_TxBufferCompleteCallback;    /* Legacy weak TxBufferCompleteCallback    */
+    hfdcan->TxBufferAbortCallback       = HAL_FDCAN_TxBufferAbortCallback;       /* Legacy weak TxBufferAbortCallback       */
+    hfdcan->RxBufferNewMessageCallback  = HAL_FDCAN_RxBufferNewMessageCallback;  /* Legacy weak RxBufferNewMessageCallback  */
+    hfdcan->HighPriorityMessageCallback = HAL_FDCAN_HighPriorityMessageCallback; /* Legacy weak HighPriorityMessageCallback */
+    hfdcan->TimestampWraparoundCallback = HAL_FDCAN_TimestampWraparoundCallback; /* Legacy weak TimestampWraparoundCallback */
+    hfdcan->TimeoutOccurredCallback     = HAL_FDCAN_TimeoutOccurredCallback;     /* Legacy weak TimeoutOccurredCallback     */
+    hfdcan->ErrorCallback               = HAL_FDCAN_ErrorCallback;               /* Legacy weak ErrorCallback               */
+    hfdcan->ErrorStatusCallback         = HAL_FDCAN_ErrorStatusCallback;         /* Legacy weak ErrorStatusCallback         */
+    hfdcan->TT_ScheduleSyncCallback     = HAL_FDCAN_TT_ScheduleSyncCallback;     /* Legacy weak TT_ScheduleSyncCallback     */
+    hfdcan->TT_TimeMarkCallback         = HAL_FDCAN_TT_TimeMarkCallback;         /* Legacy weak TT_TimeMarkCallback         */
+    hfdcan->TT_StopWatchCallback        = HAL_FDCAN_TT_StopWatchCallback;        /* Legacy weak TT_StopWatchCallback        */
+    hfdcan->TT_GlobalTimeCallback       = HAL_FDCAN_TT_GlobalTimeCallback;       /* Legacy weak TT_GlobalTimeCallback       */
+
+    if (hfdcan->MspInitCallback == NULL)
+    {
+      hfdcan->MspInitCallback = HAL_FDCAN_MspInit;  /* Legacy weak MspInit */
+    }
+
+    /* Init the low level hardware: CLOCK, NVIC */
+    hfdcan->MspInitCallback(hfdcan);
+  }
+#else
+  if (hfdcan->State == HAL_FDCAN_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    hfdcan->Lock = HAL_UNLOCKED;
+
+    /* Init the low level hardware: CLOCK, NVIC */
+    HAL_FDCAN_MspInit(hfdcan);
+  }
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+
+  /* Exit from Sleep mode */
+  CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_CSR);
+
+  /* Get tick */
+  tickstart = HAL_GetTick();
+
+  /* Check Sleep mode acknowledge */
+  while ((hfdcan->Instance->CCCR & FDCAN_CCCR_CSA) == FDCAN_CCCR_CSA)
+  {
+    if ((HAL_GetTick() - tickstart) > FDCAN_TIMEOUT_VALUE)
+    {
+      /* Update error code */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+      /* Change FDCAN state */
+      hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+      return HAL_ERROR;
+    }
+  }
+
+  /* Request initialisation */
+  SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_INIT);
+
+  /* Get tick */
+  tickstart = HAL_GetTick();
+
+  /* Wait until the INIT bit into CCCR register is set */
+  while ((hfdcan->Instance->CCCR & FDCAN_CCCR_INIT) == 0U)
+  {
+    /* Check for the Timeout */
+    if ((HAL_GetTick() - tickstart) > FDCAN_TIMEOUT_VALUE)
+    {
+      /* Update error code */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+      /* Change FDCAN state */
+      hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+      return HAL_ERROR;
+    }
+  }
+
+  /* Enable configuration change */
+  SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_CCE);
+
+  /* Set the no automatic retransmission */
+  if (hfdcan->Init.AutoRetransmission == ENABLE)
+  {
+    CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_DAR);
+  }
+  else
+  {
+    SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_DAR);
+  }
+
+  /* Set the transmit pause feature */
+  if (hfdcan->Init.TransmitPause == ENABLE)
+  {
+    SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_TXP);
+  }
+  else
+  {
+    CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_TXP);
+  }
+
+  /* Set the Protocol Exception Handling */
+  if (hfdcan->Init.ProtocolException == ENABLE)
+  {
+    CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_PXHD);
+  }
+  else
+  {
+    SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_PXHD);
+  }
+
+  /* Set FDCAN Frame Format */
+  MODIFY_REG(hfdcan->Instance->CCCR, FDCAN_FRAME_FD_BRS, hfdcan->Init.FrameFormat);
+
+  /* Reset FDCAN Operation Mode */
+  CLEAR_BIT(hfdcan->Instance->CCCR, (FDCAN_CCCR_TEST | FDCAN_CCCR_MON | FDCAN_CCCR_ASM));
+  CLEAR_BIT(hfdcan->Instance->TEST, FDCAN_TEST_LBCK);
+
+  /* Set FDCAN Operating Mode:
+               | Normal | Restricted |    Bus     | Internal | External
+               |        | Operation  | Monitoring | LoopBack | LoopBack
+     CCCR.TEST |   0    |     0      |     0      |    1     |    1
+     CCCR.MON  |   0    |     0      |     1      |    1     |    0
+     TEST.LBCK |   0    |     0      |     0      |    1     |    1
+     CCCR.ASM  |   0    |     1      |     0      |    0     |    0
+  */
+  if (hfdcan->Init.Mode == FDCAN_MODE_RESTRICTED_OPERATION)
+  {
+    /* Enable Restricted Operation mode */
+    SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_ASM);
+  }
+  else if (hfdcan->Init.Mode != FDCAN_MODE_NORMAL)
+  {
+    if (hfdcan->Init.Mode != FDCAN_MODE_BUS_MONITORING)
+    {
+      /* Enable write access to TEST register */
+      SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_TEST);
+
+      /* Enable LoopBack mode */
+      SET_BIT(hfdcan->Instance->TEST, FDCAN_TEST_LBCK);
+
+      if (hfdcan->Init.Mode == FDCAN_MODE_INTERNAL_LOOPBACK)
+      {
+        SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_MON);
+      }
+    }
+    else
+    {
+      /* Enable bus monitoring mode */
+      SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_MON);
+    }
+  }
+  else
+  {
+    /* Nothing to do: normal mode */
+  }
+
+  /* Set the nominal bit timing register */
+  hfdcan->Instance->NBTP = ((((uint32_t)hfdcan->Init.NominalSyncJumpWidth - 1U) << FDCAN_NBTP_NSJW_Pos) | \
+                            (((uint32_t)hfdcan->Init.NominalTimeSeg1 - 1U) << FDCAN_NBTP_NTSEG1_Pos)    | \
+                            (((uint32_t)hfdcan->Init.NominalTimeSeg2 - 1U) << FDCAN_NBTP_NTSEG2_Pos)    | \
+                            (((uint32_t)hfdcan->Init.NominalPrescaler - 1U) << FDCAN_NBTP_NBRP_Pos));
+
+  /* If FD operation with BRS is selected, set the data bit timing register */
+  if (hfdcan->Init.FrameFormat == FDCAN_FRAME_FD_BRS)
+  {
+    hfdcan->Instance->DBTP = ((((uint32_t)hfdcan->Init.DataSyncJumpWidth - 1U) << FDCAN_DBTP_DSJW_Pos) | \
+                              (((uint32_t)hfdcan->Init.DataTimeSeg1 - 1U) << FDCAN_DBTP_DTSEG1_Pos)    | \
+                              (((uint32_t)hfdcan->Init.DataTimeSeg2 - 1U) << FDCAN_DBTP_DTSEG2_Pos)    | \
+                              (((uint32_t)hfdcan->Init.DataPrescaler - 1U) << FDCAN_DBTP_DBRP_Pos));
+  }
+
+  if (hfdcan->Init.TxFifoQueueElmtsNbr > 0U)
+  {
+    /* Select between Tx FIFO and Tx Queue operation modes */
+    SET_BIT(hfdcan->Instance->TXBC, hfdcan->Init.TxFifoQueueMode);
+  }
+
+  /* Configure Tx element size */
+  if ((hfdcan->Init.TxBuffersNbr + hfdcan->Init.TxFifoQueueElmtsNbr) > 0U)
+  {
+    MODIFY_REG(hfdcan->Instance->TXESC, FDCAN_TXESC_TBDS, CvtEltSize[hfdcan->Init.TxElmtSize]);
+  }
+
+  /* Configure Rx FIFO 0 element size */
+  if (hfdcan->Init.RxFifo0ElmtsNbr > 0U)
+  {
+    MODIFY_REG(hfdcan->Instance->RXESC, FDCAN_RXESC_F0DS, (CvtEltSize[hfdcan->Init.RxFifo0ElmtSize] << FDCAN_RXESC_F0DS_Pos));
+  }
+
+  /* Configure Rx FIFO 1 element size */
+  if (hfdcan->Init.RxFifo1ElmtsNbr > 0U)
+  {
+    MODIFY_REG(hfdcan->Instance->RXESC, FDCAN_RXESC_F1DS, (CvtEltSize[hfdcan->Init.RxFifo1ElmtSize] << FDCAN_RXESC_F1DS_Pos));
+  }
+
+  /* Configure Rx buffer element size */
+  if (hfdcan->Init.RxBuffersNbr > 0U)
+  {
+    MODIFY_REG(hfdcan->Instance->RXESC, FDCAN_RXESC_RBDS, (CvtEltSize[hfdcan->Init.RxBufferSize] << FDCAN_RXESC_RBDS_Pos));
+  }
+
+  /* By default operation mode is set to Event-driven communication.
+     If Time-triggered communication is needed, user should call the
+     HAL_FDCAN_TT_ConfigOperation function just after the HAL_FDCAN_Init */
+  if (hfdcan->Instance == FDCAN1)
+  {
+    CLEAR_BIT(hfdcan->ttcan->TTOCF, FDCAN_TTOCF_OM);
+  }
+
+  /* Initialize the Latest Tx FIFO/Queue request buffer index */
+  hfdcan->LatestTxFifoQRequest = 0U;
+
+  /* Initialize the error code */
+  hfdcan->ErrorCode = HAL_FDCAN_ERROR_NONE;
+
+  /* Initialize the FDCAN state */
+  hfdcan->State = HAL_FDCAN_STATE_READY;
+
+  /* Calculate each RAM block address */
+  status = FDCAN_CalcultateRamBlockAddresses(hfdcan);
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Deinitializes the FDCAN peripheral registers to their default reset values.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_DeInit(FDCAN_HandleTypeDef *hfdcan)
+{
+  /* Check FDCAN handle */
+  if (hfdcan == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_ALL_INSTANCE(hfdcan->Instance));
+
+  /* Stop the FDCAN module: return value is voluntary ignored */
+  (void)HAL_FDCAN_Stop(hfdcan);
+
+  /* Disable Interrupt lines */
+  CLEAR_BIT(hfdcan->Instance->ILE, (FDCAN_INTERRUPT_LINE0 | FDCAN_INTERRUPT_LINE1));
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+  if (hfdcan->MspDeInitCallback == NULL)
+  {
+    hfdcan->MspDeInitCallback = HAL_FDCAN_MspDeInit; /* Legacy weak MspDeInit */
+  }
+
+  /* DeInit the low level hardware: CLOCK, NVIC */
+  hfdcan->MspDeInitCallback(hfdcan);
+#else
+  /* DeInit the low level hardware: CLOCK, NVIC */
+  HAL_FDCAN_MspDeInit(hfdcan);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+
+  /* Reset the FDCAN ErrorCode */
+  hfdcan->ErrorCode = HAL_FDCAN_ERROR_NONE;
+
+  /* Change FDCAN state */
+  hfdcan->State = HAL_FDCAN_STATE_RESET;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the FDCAN MSP.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval None
+  */
+__weak void HAL_FDCAN_MspInit(FDCAN_HandleTypeDef *hfdcan)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hfdcan);
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitializes the FDCAN MSP.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval None
+  */
+__weak void HAL_FDCAN_MspDeInit(FDCAN_HandleTypeDef *hfdcan)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hfdcan);
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_MspDeInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Enter FDCAN peripheral in sleep mode.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_EnterPowerDownMode(FDCAN_HandleTypeDef *hfdcan)
+{
+  uint32_t tickstart;
+
+  /* Request clock stop */
+  SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_CSR);
+
+  /* Get tick */
+  tickstart = HAL_GetTick();
+
+  /* Wait until FDCAN is ready for power down */
+  while ((hfdcan->Instance->CCCR & FDCAN_CCCR_CSA) == 0U)
+  {
+    if ((HAL_GetTick() - tickstart) > FDCAN_TIMEOUT_VALUE)
+    {
+      /* Update error code */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+      /* Change FDCAN state */
+      hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+      return HAL_ERROR;
+    }
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Exit power down mode.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_ExitPowerDownMode(FDCAN_HandleTypeDef *hfdcan)
+{
+  uint32_t tickstart;
+
+  /* Reset clock stop request */
+  CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_CSR);
+
+  /* Get tick */
+  tickstart = HAL_GetTick();
+
+  /* Wait until FDCAN exits sleep mode */
+  while ((hfdcan->Instance->CCCR & FDCAN_CCCR_CSA) == FDCAN_CCCR_CSA)
+  {
+    if ((HAL_GetTick() - tickstart) > FDCAN_TIMEOUT_VALUE)
+    {
+      /* Update error code */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+      /* Change FDCAN state */
+      hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+      return HAL_ERROR;
+    }
+  }
+
+  /* Enter normal operation */
+  CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_INIT);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+/**
+  * @brief  Register a FDCAN CallBack.
+  *         To be used instead of the weak predefined callback
+  * @param  hfdcan pointer to a FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for FDCAN module
+  * @param  CallbackID ID of the callback to be registered
+  *         This parameter can be one of the following values:
+  *           @arg @ref HAL_FDCAN_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty callback ID
+  *           @arg @ref HAL_FDCAN_RX_BUFFER_NEW_MSG_CB_ID Rx buffer new message callback ID
+  *           @arg @ref HAL_FDCAN_HIGH_PRIO_MESSAGE_CB_ID High priority message callback ID
+  *           @arg @ref HAL_FDCAN_TIMESTAMP_WRAPAROUND_CB_ID Timestamp wraparound callback ID
+  *           @arg @ref HAL_FDCAN_TIMEOUT_OCCURRED_CB_ID Timeout occurred callback ID
+  *           @arg @ref HAL_FDCAN_ERROR_CALLBACK_CB_ID Error callback ID
+  *           @arg @ref HAL_FDCAN_MSPINIT_CB_ID MspInit callback ID
+  *           @arg @ref HAL_FDCAN_MSPDEINIT_CB_ID MspDeInit callback ID
+  * @param  pCallback pointer to the Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_RegisterCallback(FDCAN_HandleTypeDef *hfdcan, HAL_FDCAN_CallbackIDTypeDef CallbackID, void (* pCallback)(FDCAN_HandleTypeDef *_hFDCAN))
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    return HAL_ERROR;
+  }
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    switch (CallbackID)
+    {
+      case HAL_FDCAN_TX_FIFO_EMPTY_CB_ID :
+        hfdcan->TxFifoEmptyCallback = pCallback;
+        break;
+
+      case HAL_FDCAN_RX_BUFFER_NEW_MSG_CB_ID :
+        hfdcan->RxBufferNewMessageCallback = pCallback;
+        break;
+
+      case HAL_FDCAN_HIGH_PRIO_MESSAGE_CB_ID :
+        hfdcan->HighPriorityMessageCallback = pCallback;
+        break;
+
+      case HAL_FDCAN_TIMESTAMP_WRAPAROUND_CB_ID :
+        hfdcan->TimestampWraparoundCallback = pCallback;
+        break;
+
+      case HAL_FDCAN_TIMEOUT_OCCURRED_CB_ID :
+        hfdcan->TimeoutOccurredCallback = pCallback;
+        break;
+
+      case HAL_FDCAN_ERROR_CALLBACK_CB_ID :
+        hfdcan->ErrorCallback = pCallback;
+        break;
+
+      case HAL_FDCAN_MSPINIT_CB_ID :
+        hfdcan->MspInitCallback = pCallback;
+        break;
+
+      case HAL_FDCAN_MSPDEINIT_CB_ID :
+        hfdcan->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Update the error code */
+        hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (hfdcan->State == HAL_FDCAN_STATE_RESET)
+  {
+    switch (CallbackID)
+    {
+      case HAL_FDCAN_MSPINIT_CB_ID :
+        hfdcan->MspInitCallback = pCallback;
+        break;
+
+      case HAL_FDCAN_MSPDEINIT_CB_ID :
+        hfdcan->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Update the error code */
+        hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Unregister a FDCAN CallBack.
+  *         FDCAN callback is redirected to the weak predefined callback
+  * @param  hfdcan pointer to a FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for FDCAN module
+  * @param  CallbackID ID of the callback to be unregistered
+  *         This parameter can be one of the following values:
+  *           @arg @ref HAL_FDCAN_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty callback ID
+  *           @arg @ref HAL_FDCAN_RX_BUFFER_NEW_MSG_CB_ID Rx buffer new message callback ID
+  *           @arg @ref HAL_FDCAN_HIGH_PRIO_MESSAGE_CB_ID High priority message callback ID
+  *           @arg @ref HAL_FDCAN_TIMESTAMP_WRAPAROUND_CB_ID Timestamp wraparound callback ID
+  *           @arg @ref HAL_FDCAN_TIMEOUT_OCCURRED_CB_ID Timeout occurred callback ID
+  *           @arg @ref HAL_FDCAN_ERROR_CALLBACK_CB_ID Error callback ID
+  *           @arg @ref HAL_FDCAN_MSPINIT_CB_ID MspInit callback ID
+  *           @arg @ref HAL_FDCAN_MSPDEINIT_CB_ID MspDeInit callback ID
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterCallback(FDCAN_HandleTypeDef *hfdcan, HAL_FDCAN_CallbackIDTypeDef CallbackID)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    switch (CallbackID)
+    {
+      case HAL_FDCAN_TX_FIFO_EMPTY_CB_ID :
+        hfdcan->TxFifoEmptyCallback = HAL_FDCAN_TxFifoEmptyCallback;
+        break;
+
+      case HAL_FDCAN_RX_BUFFER_NEW_MSG_CB_ID :
+        hfdcan->RxBufferNewMessageCallback = HAL_FDCAN_RxBufferNewMessageCallback;
+        break;
+
+      case HAL_FDCAN_HIGH_PRIO_MESSAGE_CB_ID :
+        hfdcan->HighPriorityMessageCallback = HAL_FDCAN_HighPriorityMessageCallback;
+        break;
+
+      case HAL_FDCAN_TIMESTAMP_WRAPAROUND_CB_ID :
+        hfdcan->TimestampWraparoundCallback = HAL_FDCAN_TimestampWraparoundCallback;
+        break;
+
+      case HAL_FDCAN_TIMEOUT_OCCURRED_CB_ID :
+        hfdcan->TimeoutOccurredCallback = HAL_FDCAN_TimeoutOccurredCallback;
+        break;
+
+      case HAL_FDCAN_ERROR_CALLBACK_CB_ID :
+        hfdcan->ErrorCallback = HAL_FDCAN_ErrorCallback;
+        break;
+
+      case HAL_FDCAN_MSPINIT_CB_ID :
+        hfdcan->MspInitCallback = HAL_FDCAN_MspInit;
+        break;
+
+      case HAL_FDCAN_MSPDEINIT_CB_ID :
+        hfdcan->MspDeInitCallback = HAL_FDCAN_MspDeInit;
+        break;
+
+      default :
+        /* Update the error code */
+        hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (hfdcan->State == HAL_FDCAN_STATE_RESET)
+  {
+    switch (CallbackID)
+    {
+      case HAL_FDCAN_MSPINIT_CB_ID :
+        hfdcan->MspInitCallback = HAL_FDCAN_MspInit;
+        break;
+
+      case HAL_FDCAN_MSPDEINIT_CB_ID :
+        hfdcan->MspDeInitCallback = HAL_FDCAN_MspDeInit;
+        break;
+
+      default :
+        /* Update the error code */
+        hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Register Clock Calibration FDCAN Callback
+  *         To be used instead of the weak HAL_FDCAN_ClockCalibrationCallback() predefined callback
+  * @param  hfdcan FDCAN handle
+  * @param  pCallback pointer to the Clock Calibration Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_RegisterClockCalibrationCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_ClockCalibrationCallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+    return HAL_ERROR;
+  }
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    hfdcan->ClockCalibrationCallback = pCallback;
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  UnRegister the Clock Calibration FDCAN Callback
+  *         Clock Calibration FDCAN Callback is redirected to the weak HAL_FDCAN_ClockCalibrationCallback() predefined callback
+  * @param  hfdcan FDCAN handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterClockCalibrationCallback(FDCAN_HandleTypeDef *hfdcan)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    hfdcan->ClockCalibrationCallback = HAL_FDCAN_ClockCalibrationCallback; /* Legacy weak ClockCalibrationCallback  */
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Register Tx Event Fifo FDCAN Callback
+  *         To be used instead of the weak HAL_FDCAN_TxEventFifoCallback() predefined callback
+  * @param  hfdcan FDCAN handle
+  * @param  pCallback pointer to the Tx Event Fifo Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_RegisterTxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TxEventFifoCallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+    return HAL_ERROR;
+  }
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    hfdcan->TxEventFifoCallback = pCallback;
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  UnRegister the Tx Event Fifo FDCAN Callback
+  *         Tx Event Fifo FDCAN Callback is redirected to the weak HAL_FDCAN_TxEventFifoCallback() predefined callback
+  * @param  hfdcan FDCAN handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    hfdcan->TxEventFifoCallback = HAL_FDCAN_TxEventFifoCallback; /* Legacy weak TxEventFifoCallback  */
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Register Rx Fifo 0 FDCAN Callback
+  *         To be used instead of the weak HAL_FDCAN_RxFifo0Callback() predefined callback
+  * @param  hfdcan FDCAN handle
+  * @param  pCallback pointer to the Rx Fifo 0 Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_RegisterRxFifo0Callback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_RxFifo0CallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+    return HAL_ERROR;
+  }
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    hfdcan->RxFifo0Callback = pCallback;
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  UnRegister the Rx Fifo 0 FDCAN Callback
+  *         Rx Fifo 0 FDCAN Callback is redirected to the weak HAL_FDCAN_RxFifo0Callback() predefined callback
+  * @param  hfdcan FDCAN handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterRxFifo0Callback(FDCAN_HandleTypeDef *hfdcan)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    hfdcan->RxFifo0Callback = HAL_FDCAN_RxFifo0Callback; /* Legacy weak RxFifo0Callback  */
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Register Rx Fifo 1 FDCAN Callback
+  *         To be used instead of the weak HAL_FDCAN_RxFifo1Callback() predefined callback
+  * @param  hfdcan FDCAN handle
+  * @param  pCallback pointer to the Rx Fifo 1 Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_RegisterRxFifo1Callback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_RxFifo1CallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+    return HAL_ERROR;
+  }
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    hfdcan->RxFifo1Callback = pCallback;
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  UnRegister the Rx Fifo 1 FDCAN Callback
+  *         Rx Fifo 1 FDCAN Callback is redirected to the weak HAL_FDCAN_RxFifo1Callback() predefined callback
+  * @param  hfdcan FDCAN handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterRxFifo1Callback(FDCAN_HandleTypeDef *hfdcan)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    hfdcan->RxFifo1Callback = HAL_FDCAN_RxFifo1Callback; /* Legacy weak RxFifo1Callback  */
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Register Tx Buffer Complete FDCAN Callback
+  *         To be used instead of the weak HAL_FDCAN_TxBufferCompleteCallback() predefined callback
+  * @param  hfdcan FDCAN handle
+  * @param  pCallback pointer to the Tx Buffer Complete Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_RegisterTxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TxBufferCompleteCallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+    return HAL_ERROR;
+  }
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    hfdcan->TxBufferCompleteCallback = pCallback;
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  UnRegister the Tx Buffer Complete FDCAN Callback
+  *         Tx Buffer Complete FDCAN Callback is redirected to the weak HAL_FDCAN_TxBufferCompleteCallback() predefined callback
+  * @param  hfdcan FDCAN handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    hfdcan->TxBufferCompleteCallback = HAL_FDCAN_TxBufferCompleteCallback; /* Legacy weak TxBufferCompleteCallback  */
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Register Tx Buffer Abort FDCAN Callback
+  *         To be used instead of the weak HAL_FDCAN_TxBufferAbortCallback() predefined callback
+  * @param  hfdcan FDCAN handle
+  * @param  pCallback pointer to the Tx Buffer Abort Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_RegisterTxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TxBufferAbortCallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+    return HAL_ERROR;
+  }
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    hfdcan->TxBufferAbortCallback = pCallback;
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  UnRegister the Tx Buffer Abort FDCAN Callback
+  *         Tx Buffer Abort FDCAN Callback is redirected to the weak HAL_FDCAN_TxBufferAbortCallback() predefined callback
+  * @param  hfdcan FDCAN handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    hfdcan->TxBufferAbortCallback = HAL_FDCAN_TxBufferAbortCallback; /* Legacy weak TxBufferAbortCallback  */
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Register Error Status FDCAN Callback
+  *         To be used instead of the weak HAL_FDCAN_ErrorStatusCallback() predefined callback
+  * @param  hfdcan FDCAN handle
+  * @param  pCallback pointer to the Error Status Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_RegisterErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_ErrorStatusCallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+    return HAL_ERROR;
+  }
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    hfdcan->ErrorStatusCallback = pCallback;
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  UnRegister the Error Status FDCAN Callback
+  *         Error Status FDCAN Callback is redirected to the weak HAL_FDCAN_ErrorStatusCallback() predefined callback
+  * @param  hfdcan FDCAN handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    hfdcan->ErrorStatusCallback = HAL_FDCAN_ErrorStatusCallback; /* Legacy weak ErrorStatusCallback  */
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Register TT Schedule Synchronization FDCAN Callback
+  *         To be used instead of the weak HAL_FDCAN_TT_ScheduleSyncCallback() predefined callback
+  * @param  hfdcan FDCAN handle
+  * @param  pCallback pointer to the TT Schedule Synchronization Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_RegisterTTScheduleSyncCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TT_ScheduleSyncCallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+    return HAL_ERROR;
+  }
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    hfdcan->TT_ScheduleSyncCallback = pCallback;
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  UnRegister the TT Schedule Synchronization FDCAN Callback
+  *         TT Schedule Synchronization Callback is redirected to the weak HAL_FDCAN_TT_ScheduleSyncCallback() predefined callback
+  * @param  hfdcan FDCAN handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterTTScheduleSyncCallback(FDCAN_HandleTypeDef *hfdcan)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    hfdcan->TT_ScheduleSyncCallback = HAL_FDCAN_TT_ScheduleSyncCallback; /* Legacy weak TT_ScheduleSyncCallback  */
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Register TT Time Mark FDCAN Callback
+  *         To be used instead of the weak HAL_FDCAN_TT_TimeMarkCallback() predefined callback
+  * @param  hfdcan FDCAN handle
+  * @param  pCallback pointer to the TT Time Mark Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_RegisterTTTimeMarkCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TT_TimeMarkCallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+    return HAL_ERROR;
+  }
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    hfdcan->TT_TimeMarkCallback = pCallback;
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  UnRegister the TT Time Mark FDCAN Callback
+  *         TT Time Mark Callback is redirected to the weak HAL_FDCAN_TT_TimeMarkCallback() predefined callback
+  * @param  hfdcan FDCAN handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterTTTimeMarkCallback(FDCAN_HandleTypeDef *hfdcan)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    hfdcan->TT_TimeMarkCallback = HAL_FDCAN_TT_TimeMarkCallback; /* Legacy weak TT_TimeMarkCallback  */
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Register TT Stop Watch FDCAN Callback
+  *         To be used instead of the weak HAL_FDCAN_TT_StopWatchCallback() predefined callback
+  * @param  hfdcan FDCAN handle
+  * @param  pCallback pointer to the TT Stop Watch Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_RegisterTTStopWatchCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TT_StopWatchCallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+    return HAL_ERROR;
+  }
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    hfdcan->TT_StopWatchCallback = pCallback;
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  UnRegister the TT Stop Watch FDCAN Callback
+  *         TT Stop Watch Callback is redirected to the weak HAL_FDCAN_TT_StopWatchCallback() predefined callback
+  * @param  hfdcan FDCAN handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterTTStopWatchCallback(FDCAN_HandleTypeDef *hfdcan)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    hfdcan->TT_StopWatchCallback = HAL_FDCAN_TT_StopWatchCallback; /* Legacy weak TT_StopWatchCallback  */
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Register TT Global Time FDCAN Callback
+  *         To be used instead of the weak HAL_FDCAN_TT_GlobalTimeCallback() predefined callback
+  * @param  hfdcan FDCAN handle
+  * @param  pCallback pointer to the TT Global Time Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_RegisterTTGlobalTimeCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TT_GlobalTimeCallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+    return HAL_ERROR;
+  }
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    hfdcan->TT_GlobalTimeCallback = pCallback;
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  UnRegister the TT Global Time FDCAN Callback
+  *         TT Global Time Callback is redirected to the weak HAL_FDCAN_TT_GlobalTimeCallback() predefined callback
+  * @param  hfdcan FDCAN handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterTTGlobalTimeCallback(FDCAN_HandleTypeDef *hfdcan)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    hfdcan->TT_GlobalTimeCallback = HAL_FDCAN_TT_GlobalTimeCallback; /* Legacy weak TT_GlobalTimeCallback  */
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Exported_Functions_Group2 Configuration functions
+ *  @brief    FDCAN Configuration functions.
+ *
+@verbatim
+  ==============================================================================
+              ##### Configuration functions #####
+  ==============================================================================
+    [..]  This section provides functions allowing to:
+      (+) HAL_FDCAN_ConfigClockCalibration        : Configure the FDCAN clock calibration unit
+        (+) HAL_FDCAN_GetClockCalibrationState      : Get the clock calibration state
+        (+) HAL_FDCAN_ResetClockCalibrationState    : Reset the clock calibration state
+        (+) HAL_FDCAN_GetClockCalibrationCounter    : Get the clock calibration counters values
+      (+) HAL_FDCAN_ConfigFilter                  : Configure the FDCAN reception filters
+      (+) HAL_FDCAN_ConfigGlobalFilter            : Configure the FDCAN global filter
+      (+) HAL_FDCAN_ConfigExtendedIdMask          : Configure the extended ID mask
+      (+) HAL_FDCAN_ConfigRxFifoOverwrite         : Configure the Rx FIFO operation mode
+      (+) HAL_FDCAN_ConfigFifoWatermark           : Configure the FIFO watermark
+      (+) HAL_FDCAN_ConfigRamWatchdog             : Configure the RAM watchdog
+      (+) HAL_FDCAN_ConfigTimestampCounter        : Configure the timestamp counter
+        (+) HAL_FDCAN_EnableTimestampCounter        : Enable the timestamp counter
+        (+) HAL_FDCAN_DisableTimestampCounter       : Disable the timestamp counter
+        (+) HAL_FDCAN_GetTimestampCounter           : Get the timestamp counter value
+        (+) HAL_FDCAN_ResetTimestampCounter         : Reset the timestamp counter to zero
+      (+) HAL_FDCAN_ConfigTimeoutCounter          : Configure the timeout counter
+        (+) HAL_FDCAN_EnableTimeoutCounter          : Enable the timeout counter
+        (+) HAL_FDCAN_DisableTimeoutCounter         : Disable the timeout counter
+        (+) HAL_FDCAN_GetTimeoutCounter             : Get the timeout counter value
+        (+) HAL_FDCAN_ResetTimeoutCounter           : Reset the timeout counter to its start value
+      (+) HAL_FDCAN_ConfigTxDelayCompensation     : Configure the transmitter delay compensation
+        (+) HAL_FDCAN_EnableTxDelayCompensation     : Enable the transmitter delay compensation
+        (+) HAL_FDCAN_DisableTxDelayCompensation    : Disable the transmitter delay compensation
+      (+) HAL_FDCAN_EnableISOMode                 : Enable ISO 11898-1 protocol mode
+      (+) HAL_FDCAN_DisableISOMode                : Disable ISO 11898-1 protocol mode
+      (+) HAL_FDCAN_EnableEdgeFiltering           : Enable edge filtering during bus integration
+      (+) HAL_FDCAN_DisableEdgeFiltering          : Disable edge filtering during bus integration
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configure the FDCAN clock calibration unit according to the specified
+  *         parameters in the FDCAN_ClkCalUnitTypeDef structure.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  sCcuConfig pointer to an FDCAN_ClkCalUnitTypeDef structure that
+  *         contains the clock calibration information
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_ConfigClockCalibration(FDCAN_HandleTypeDef *hfdcan, FDCAN_ClkCalUnitTypeDef *sCcuConfig)
+{
+  /* Check function parameters */
+  assert_param(IS_FDCAN_CLOCK_CALIBRATION(sCcuConfig->ClockCalibration));
+  if (sCcuConfig->ClockCalibration == FDCAN_CLOCK_CALIBRATION_DISABLE)
+  {
+    assert_param(IS_FDCAN_CKDIV(sCcuConfig->ClockDivider));
+  }
+  else
+  {
+    assert_param(IS_FDCAN_MAX_VALUE(sCcuConfig->MinOscClkPeriods, 0xFFU));
+    assert_param(IS_FDCAN_CALIBRATION_FIELD_LENGTH(sCcuConfig->CalFieldLength));
+    assert_param(IS_FDCAN_MIN_VALUE(sCcuConfig->TimeQuantaPerBitTime, 4U));
+    assert_param(IS_FDCAN_MAX_VALUE(sCcuConfig->TimeQuantaPerBitTime, 0x25U));
+    assert_param(IS_FDCAN_MAX_VALUE(sCcuConfig->WatchdogStartValue, 0xFFFFU));
+  }
+
+  /* FDCAN1 should be initialized in order to use clock calibration */
+  if (hfdcan->Instance != FDCAN1)
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM;
+
+    return HAL_ERROR;
+  }
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    if (sCcuConfig->ClockCalibration == FDCAN_CLOCK_CALIBRATION_DISABLE)
+    {
+      /* Bypass clock calibration */
+      SET_BIT(FDCAN_CCU->CCFG, FDCANCCU_CCFG_BCC);
+
+      /* Configure clock divider */
+      MODIFY_REG(FDCAN_CCU->CCFG, FDCANCCU_CCFG_CDIV, sCcuConfig->ClockDivider);
+    }
+    else /* sCcuConfig->ClockCalibration == ENABLE */
+    {
+      /* Clock calibration unit generates time quanta clock */
+      CLEAR_BIT(FDCAN_CCU->CCFG, FDCANCCU_CCFG_BCC);
+
+      /* Configure clock calibration unit */
+      MODIFY_REG(FDCAN_CCU->CCFG,
+                 (FDCANCCU_CCFG_TQBT | FDCANCCU_CCFG_CFL | FDCANCCU_CCFG_OCPM),
+                 ((sCcuConfig->TimeQuantaPerBitTime << FDCANCCU_CCFG_TQBT_Pos) | sCcuConfig->CalFieldLength | (sCcuConfig->MinOscClkPeriods << FDCANCCU_CCFG_OCPM_Pos)));
+
+      /* Configure the start value of the calibration watchdog counter */
+      MODIFY_REG(FDCAN_CCU->CWD, FDCANCCU_CWD_WDC, sCcuConfig->WatchdogStartValue);
+    }
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Get the clock calibration state.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval State clock calibration state (can be a value of @arg FDCAN_calibration_state)
+  */
+uint32_t HAL_FDCAN_GetClockCalibrationState(FDCAN_HandleTypeDef *hfdcan)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hfdcan);
+
+  return (FDCAN_CCU->CSTAT & FDCANCCU_CSTAT_CALS);
+}
+
+/**
+  * @brief  Reset the clock calibration state.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_ResetClockCalibrationState(FDCAN_HandleTypeDef *hfdcan)
+{
+  /* FDCAN1 should be initialized in order to use clock calibration */
+  if (hfdcan->Instance != FDCAN1)
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM;
+
+    return HAL_ERROR;
+  }
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    /* Calibration software reset */
+    SET_BIT(FDCAN_CCU->CCFG, FDCANCCU_CCFG_SWR);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Get the clock calibration counter value.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  Counter clock calibration counter.
+  *         This parameter can be a value of @arg FDCAN_calibration_counter.
+  * @retval Value clock calibration counter value
+  */
+uint32_t HAL_FDCAN_GetClockCalibrationCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t Counter)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hfdcan);
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_CALIBRATION_COUNTER(Counter));
+
+  if (Counter == FDCAN_CALIB_TIME_QUANTA_COUNTER)
+  {
+    return ((FDCAN_CCU->CSTAT & FDCANCCU_CSTAT_TQC) >> FDCANCCU_CSTAT_TQC_Pos);
+  }
+  else if (Counter == FDCAN_CALIB_CLOCK_PERIOD_COUNTER)
+  {
+    return (FDCAN_CCU->CSTAT & FDCANCCU_CSTAT_OCPC);
+  }
+  else /* Counter == FDCAN_CALIB_WATCHDOG_COUNTER */
+  {
+    return ((FDCAN_CCU->CWD & FDCANCCU_CWD_WDV) >> FDCANCCU_CWD_WDV_Pos);
+  }
+}
+
+/**
+  * @brief  Configure the FDCAN reception filter according to the specified
+  *         parameters in the FDCAN_FilterTypeDef structure.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  sFilterConfig pointer to an FDCAN_FilterTypeDef structure that
+  *         contains the filter configuration information
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_ConfigFilter(FDCAN_HandleTypeDef *hfdcan, FDCAN_FilterTypeDef *sFilterConfig)
+{
+  uint32_t FilterElementW1;
+  uint32_t FilterElementW2;
+  uint32_t *FilterAddress;
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    /* Check function parameters */
+    assert_param(IS_FDCAN_ID_TYPE(sFilterConfig->IdType));
+    assert_param(IS_FDCAN_FILTER_CFG(sFilterConfig->FilterConfig));
+    if (sFilterConfig->FilterConfig == FDCAN_FILTER_TO_RXBUFFER)
+    {
+      assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->RxBufferIndex, 63U));
+      assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->IsCalibrationMsg, 1U));
+    }
+
+    if (sFilterConfig->IdType == FDCAN_STANDARD_ID)
+    {
+      /* Check function parameters */
+      assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterIndex, (hfdcan->Init.StdFiltersNbr - 1U)));
+      assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterID1, 0x7FFU));
+      if (sFilterConfig->FilterConfig != FDCAN_FILTER_TO_RXBUFFER)
+      {
+        assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterID2, 0x7FFU));
+        assert_param(IS_FDCAN_STD_FILTER_TYPE(sFilterConfig->FilterType));
+      }
+
+      /* Build filter element */
+      if (sFilterConfig->FilterConfig == FDCAN_FILTER_TO_RXBUFFER)
+      {
+        FilterElementW1 = ((FDCAN_FILTER_TO_RXBUFFER << 27U)       |
+                           (sFilterConfig->FilterID1 << 16U)       |
+                           (sFilterConfig->IsCalibrationMsg << 8U) |
+                           sFilterConfig->RxBufferIndex);
+      }
+      else
+      {
+        FilterElementW1 = ((sFilterConfig->FilterType << 30U)   |
+                           (sFilterConfig->FilterConfig << 27U) |
+                           (sFilterConfig->FilterID1 << 16U)    |
+                           sFilterConfig->FilterID2);
+      }
+
+      /* Calculate filter address */
+      FilterAddress = (uint32_t *)(hfdcan->msgRam.StandardFilterSA + (sFilterConfig->FilterIndex * 4U));
+
+      /* Write filter element to the message RAM */
+      *FilterAddress = FilterElementW1;
+    }
+    else /* sFilterConfig->IdType == FDCAN_EXTENDED_ID */
+    {
+      /* Check function parameters */
+      assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterIndex, (hfdcan->Init.ExtFiltersNbr - 1U)));
+      assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterID1, 0x1FFFFFFFU));
+      if (sFilterConfig->FilterConfig != FDCAN_FILTER_TO_RXBUFFER)
+      {
+        assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterID2, 0x1FFFFFFFU));
+        assert_param(IS_FDCAN_EXT_FILTER_TYPE(sFilterConfig->FilterType));
+      }
+
+      /* Build first word of filter element */
+      FilterElementW1 = ((sFilterConfig->FilterConfig << 29U) | sFilterConfig->FilterID1);
+
+      /* Build second word of filter element */
+      if (sFilterConfig->FilterConfig == FDCAN_FILTER_TO_RXBUFFER)
+      {
+        FilterElementW2 = sFilterConfig->RxBufferIndex;
+      }
+      else
+      {
+        FilterElementW2 = ((sFilterConfig->FilterType << 30U) | sFilterConfig->FilterID2);
+      }
+
+      /* Calculate filter address */
+      FilterAddress = (uint32_t *)(hfdcan->msgRam.ExtendedFilterSA + (sFilterConfig->FilterIndex * 4U * 2U));
+
+      /* Write filter element to the message RAM */
+      *FilterAddress = FilterElementW1;
+      FilterAddress++;
+      *FilterAddress = FilterElementW2;
+    }
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Configure the FDCAN global filter.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  NonMatchingStd Defines how received messages with 11-bit IDs that
+  *         do not match any element of the filter list are treated.
+  *         This parameter can be a value of @arg FDCAN_Non_Matching_Frames.
+  * @param  NonMatchingExt Defines how received messages with 29-bit IDs that
+  *         do not match any element of the filter list are treated.
+  *         This parameter can be a value of @arg FDCAN_Non_Matching_Frames.
+  * @param  RejectRemoteStd Filter or reject all the remote 11-bit IDs frames.
+  *         This parameter can be a value of @arg FDCAN_Reject_Remote_Frames.
+  * @param  RejectRemoteExt Filter or reject all the remote 29-bit IDs frames.
+  *         This parameter can be a value of @arg FDCAN_Reject_Remote_Frames.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_ConfigGlobalFilter(FDCAN_HandleTypeDef *hfdcan,
+                                               uint32_t NonMatchingStd,
+                                               uint32_t NonMatchingExt,
+                                               uint32_t RejectRemoteStd,
+                                               uint32_t RejectRemoteExt)
+{
+  /* Check function parameters */
+  assert_param(IS_FDCAN_NON_MATCHING(NonMatchingStd));
+  assert_param(IS_FDCAN_NON_MATCHING(NonMatchingExt));
+  assert_param(IS_FDCAN_REJECT_REMOTE(RejectRemoteStd));
+  assert_param(IS_FDCAN_REJECT_REMOTE(RejectRemoteExt));
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    /* Configure global filter */
+    hfdcan->Instance->GFC = ((NonMatchingStd << FDCAN_GFC_ANFS_Pos)  |
+                             (NonMatchingExt << FDCAN_GFC_ANFE_Pos)  |
+                             (RejectRemoteStd << FDCAN_GFC_RRFS_Pos) |
+                             (RejectRemoteExt << FDCAN_GFC_RRFE_Pos));
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Configure the extended ID mask.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  Mask Extended ID Mask.
+  *         This parameter must be a number between 0 and 0x1FFFFFFF
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_ConfigExtendedIdMask(FDCAN_HandleTypeDef *hfdcan, uint32_t Mask)
+{
+  /* Check function parameters */
+  assert_param(IS_FDCAN_MAX_VALUE(Mask, 0x1FFFFFFFU));
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    /* Configure the extended ID mask */
+    hfdcan->Instance->XIDAM = Mask;
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Configure the Rx FIFO operation mode.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  RxFifo Rx FIFO.
+  *         This parameter can be one of the following values:
+  *           @arg FDCAN_RX_FIFO0: Rx FIFO 0
+  *           @arg FDCAN_RX_FIFO1: Rx FIFO 1
+  * @param  OperationMode operation mode.
+  *         This parameter can be a value of @arg FDCAN_Rx_FIFO_operation_mode.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_ConfigRxFifoOverwrite(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo, uint32_t OperationMode)
+{
+  /* Check function parameters */
+  assert_param(IS_FDCAN_RX_FIFO(RxFifo));
+  assert_param(IS_FDCAN_RX_FIFO_MODE(OperationMode));
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    if (RxFifo == FDCAN_RX_FIFO0)
+    {
+      /* Select FIFO 0 Operation Mode */
+      MODIFY_REG(hfdcan->Instance->RXF0C, FDCAN_RXF0C_F0OM, OperationMode);
+    }
+    else /* RxFifo == FDCAN_RX_FIFO1 */
+    {
+      /* Select FIFO 1 Operation Mode */
+      MODIFY_REG(hfdcan->Instance->RXF1C, FDCAN_RXF1C_F1OM, OperationMode);
+    }
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Configure the FIFO watermark.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  FIFO select the FIFO to be configured.
+  *         This parameter can be a value of @arg FDCAN_FIFO_watermark.
+  * @param  Watermark level for FIFO watermark interrupt.
+  *         This parameter must be a number between:
+  *           - 0 and 32, if FIFO is FDCAN_CFG_TX_EVENT_FIFO
+  *           - 0 and 64, if FIFO is FDCAN_CFG_RX_FIFO0 or FDCAN_CFG_RX_FIFO1
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_ConfigFifoWatermark(FDCAN_HandleTypeDef *hfdcan, uint32_t FIFO, uint32_t Watermark)
+{
+  /* Check function parameters */
+  assert_param(IS_FDCAN_FIFO_WATERMARK(FIFO));
+  if (FIFO == FDCAN_CFG_TX_EVENT_FIFO)
+  {
+    assert_param(IS_FDCAN_MAX_VALUE(Watermark, 32U));
+  }
+  else /* (FIFO == FDCAN_CFG_RX_FIFO0) || (FIFO == FDCAN_CFG_RX_FIFO1) */
+  {
+    assert_param(IS_FDCAN_MAX_VALUE(Watermark, 64U));
+  }
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    /* Set the level for FIFO watermark interrupt */
+    if (FIFO == FDCAN_CFG_TX_EVENT_FIFO)
+    {
+      MODIFY_REG(hfdcan->Instance->TXEFC, FDCAN_TXEFC_EFWM, (Watermark << FDCAN_TXEFC_EFWM_Pos));
+    }
+    else if (FIFO == FDCAN_CFG_RX_FIFO0)
+    {
+      MODIFY_REG(hfdcan->Instance->RXF0C, FDCAN_RXF0C_F0WM, (Watermark << FDCAN_RXF0C_F0WM_Pos));
+    }
+    else /* FIFO == FDCAN_CFG_RX_FIFO1 */
+    {
+      MODIFY_REG(hfdcan->Instance->RXF1C, FDCAN_RXF1C_F1WM, (Watermark << FDCAN_RXF1C_F1WM_Pos));
+    }
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Configure the RAM watchdog.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  CounterStartValue Start value of the Message RAM Watchdog Counter,
+  *         This parameter must be a number between 0x00 and 0xFF,
+  *         with the reset value of 0x00 the counter is disabled.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_ConfigRamWatchdog(FDCAN_HandleTypeDef *hfdcan, uint32_t CounterStartValue)
+{
+  /* Check function parameters */
+  assert_param(IS_FDCAN_MAX_VALUE(CounterStartValue, 0xFFU));
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    /* Configure the RAM watchdog counter start value */
+    MODIFY_REG(hfdcan->Instance->RWD, FDCAN_RWD_WDC, CounterStartValue);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Configure the timestamp counter.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  TimestampPrescaler Timestamp Counter Prescaler.
+  *         This parameter can be a value of @arg FDCAN_Timestamp_Prescaler.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_ConfigTimestampCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampPrescaler)
+{
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TIMESTAMP_PRESCALER(TimestampPrescaler));
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    /* Configure prescaler */
+    MODIFY_REG(hfdcan->Instance->TSCC, FDCAN_TSCC_TCP, TimestampPrescaler);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Enable the timestamp counter.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  TimestampOperation Timestamp counter operation.
+  *         This parameter can be a value of @arg FDCAN_Timestamp.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_EnableTimestampCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampOperation)
+{
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TIMESTAMP(TimestampOperation));
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    /* Enable timestamp counter */
+    MODIFY_REG(hfdcan->Instance->TSCC, FDCAN_TSCC_TSS, TimestampOperation);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Disable the timestamp counter.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_DisableTimestampCounter(FDCAN_HandleTypeDef *hfdcan)
+{
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    /* Disable timestamp counter */
+    CLEAR_BIT(hfdcan->Instance->TSCC, FDCAN_TSCC_TSS);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Get the timestamp counter value.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval Value Timestamp counter value
+  */
+uint16_t HAL_FDCAN_GetTimestampCounter(FDCAN_HandleTypeDef *hfdcan)
+{
+  return (uint16_t)(hfdcan->Instance->TSCV);
+}
+
+/**
+  * @brief  Reset the timestamp counter to zero.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_ResetTimestampCounter(FDCAN_HandleTypeDef *hfdcan)
+{
+  if ((hfdcan->Instance->TSCC & FDCAN_TSCC_TSS) != FDCAN_TIMESTAMP_EXTERNAL)
+  {
+    /* Reset timestamp counter.
+       Actually any write operation to TSCV clears the counter */
+    CLEAR_REG(hfdcan->Instance->TSCV);
+  }
+  else
+  {
+    /* Update error code.
+       Unable to reset external counter */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
+
+    return HAL_ERROR;
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configure the timeout counter.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  TimeoutOperation Timeout counter operation.
+  *         This parameter can be a value of @arg FDCAN_Timeout_Operation.
+  * @param  TimeoutPeriod Start value of the timeout down-counter.
+  *         This parameter must be a number between 0x0000 and 0xFFFF
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_ConfigTimeoutCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimeoutOperation, uint32_t TimeoutPeriod)
+{
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TIMEOUT(TimeoutOperation));
+  assert_param(IS_FDCAN_MAX_VALUE(TimeoutPeriod, 0xFFFFU));
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    /* Select timeout operation and configure period */
+    MODIFY_REG(hfdcan->Instance->TOCC, (FDCAN_TOCC_TOS | FDCAN_TOCC_TOP), (TimeoutOperation | (TimeoutPeriod << FDCAN_TOCC_TOP_Pos)));
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Enable the timeout counter.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_EnableTimeoutCounter(FDCAN_HandleTypeDef *hfdcan)
+{
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    /* Enable timeout counter */
+    SET_BIT(hfdcan->Instance->TOCC, FDCAN_TOCC_ETOC);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Disable the timeout counter.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_DisableTimeoutCounter(FDCAN_HandleTypeDef *hfdcan)
+{
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    /* Disable timeout counter */
+    CLEAR_BIT(hfdcan->Instance->TOCC, FDCAN_TOCC_ETOC);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Get the timeout counter value.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval Value Timeout counter value
+  */
+uint16_t HAL_FDCAN_GetTimeoutCounter(FDCAN_HandleTypeDef *hfdcan)
+{
+  return (uint16_t)(hfdcan->Instance->TOCV);
+}
+
+/**
+  * @brief  Reset the timeout counter to its start value.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_ResetTimeoutCounter(FDCAN_HandleTypeDef *hfdcan)
+{
+  if ((hfdcan->Instance->TOCC & FDCAN_TOCC_TOS) == FDCAN_TIMEOUT_CONTINUOUS)
+  {
+    /* Reset timeout counter to start value */
+    CLEAR_REG(hfdcan->Instance->TOCV);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code.
+       Unable to reset counter: controlled only by FIFO empty state */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Configure the transmitter delay compensation.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  TdcOffset Transmitter Delay Compensation Offset.
+  *         This parameter must be a number between 0x00 and 0x7F.
+  * @param  TdcFilter Transmitter Delay Compensation Filter Window Length.
+  *         This parameter must be a number between 0x00 and 0x7F.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_ConfigTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan, uint32_t TdcOffset, uint32_t TdcFilter)
+{
+  /* Check function parameters */
+  assert_param(IS_FDCAN_MAX_VALUE(TdcOffset, 0x7FU));
+  assert_param(IS_FDCAN_MAX_VALUE(TdcFilter, 0x7FU));
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    /* Configure TDC offset and filter window */
+    hfdcan->Instance->TDCR = ((TdcFilter << FDCAN_TDCR_TDCF_Pos) | (TdcOffset << FDCAN_TDCR_TDCO_Pos));
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Enable the transmitter delay compensation.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_EnableTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan)
+{
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    /* Enable transmitter delay compensation */
+    SET_BIT(hfdcan->Instance->DBTP, FDCAN_DBTP_TDC);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Disable the transmitter delay compensation.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_DisableTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan)
+{
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    /* Disable transmitter delay compensation */
+    CLEAR_BIT(hfdcan->Instance->DBTP, FDCAN_DBTP_TDC);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Enable ISO 11898-1 protocol mode.
+  *         CAN FD frame format is according to ISO 11898-1 standard.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_EnableISOMode(FDCAN_HandleTypeDef *hfdcan)
+{
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    /* Disable Non ISO protocol mode */
+    CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_NISO);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Disable ISO 11898-1 protocol mode.
+  *         CAN FD frame format is according to Bosch CAN FD specification V1.0.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_DisableISOMode(FDCAN_HandleTypeDef *hfdcan)
+{
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    /* Enable Non ISO protocol mode */
+    SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_NISO);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Enable edge filtering during bus integration.
+  *         Two consecutive dominant tq are required to detect an edge for hard synchronization.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_EnableEdgeFiltering(FDCAN_HandleTypeDef *hfdcan)
+{
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    /* Enable edge filtering */
+    SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_EFBI);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Disable edge filtering during bus integration.
+  *         One dominant tq is required to detect an edge for hard synchronization.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_DisableEdgeFiltering(FDCAN_HandleTypeDef *hfdcan)
+{
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    /* Disable edge filtering */
+    CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_EFBI);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Exported_Functions_Group3 Control functions
+ *  @brief    Control functions
+ *
+@verbatim
+  ==============================================================================
+                          ##### Control functions #####
+  ==============================================================================
+    [..]  This section provides functions allowing to:
+      (+) HAL_FDCAN_Start                         : Start the FDCAN module
+      (+) HAL_FDCAN_Stop                          : Stop the FDCAN module and enable access to configuration registers
+      (+) HAL_FDCAN_AddMessageToTxFifoQ           : Add a message to the Tx FIFO/Queue and activate the corresponding transmission request
+      (+) HAL_FDCAN_AddMessageToTxBuffer          : Add a message to a dedicated Tx buffer
+      (+) HAL_FDCAN_EnableTxBufferRequest         : Enable transmission request
+      (+) HAL_FDCAN_GetLatestTxFifoQRequestBuffer : Get Tx buffer index of latest Tx FIFO/Queue request
+      (+) HAL_FDCAN_AbortTxRequest                : Abort transmission request
+      (+) HAL_FDCAN_GetRxMessage                  : Get an FDCAN frame from the Rx Buffer/FIFO zone into the message RAM
+      (+) HAL_FDCAN_GetTxEvent                    : Get an FDCAN Tx event from the Tx Event FIFO zone into the message RAM
+      (+) HAL_FDCAN_GetHighPriorityMessageStatus  : Get high priority message status
+      (+) HAL_FDCAN_GetProtocolStatus             : Get protocol status
+      (+) HAL_FDCAN_GetErrorCounters              : Get error counter values
+      (+) HAL_FDCAN_IsRxBufferMessageAvailable    : Check if a new message is received in the selected Rx buffer
+      (+) HAL_FDCAN_IsTxBufferMessagePending      : Check if a transmission request is pending on the selected Tx buffer
+      (+) HAL_FDCAN_GetRxFifoFillLevel            : Return Rx FIFO fill level
+      (+) HAL_FDCAN_GetTxFifoFreeLevel            : Return Tx FIFO free level
+      (+) HAL_FDCAN_IsRestrictedOperationMode     : Check if the FDCAN peripheral entered Restricted Operation Mode
+      (+) HAL_FDCAN_ExitRestrictedOperationMode   : Exit Restricted Operation Mode
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Start the FDCAN module.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_Start(FDCAN_HandleTypeDef *hfdcan)
+{
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    /* Change FDCAN peripheral state */
+    hfdcan->State = HAL_FDCAN_STATE_BUSY;
+
+    /* Request leave initialisation */
+    CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_INIT);
+
+    /* Reset the FDCAN ErrorCode */
+    hfdcan->ErrorCode = HAL_FDCAN_ERROR_NONE;
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Stop the FDCAN module and enable access to configuration registers.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_Stop(FDCAN_HandleTypeDef *hfdcan)
+{
+  uint32_t Counter = 0U;
+
+  if (hfdcan->State == HAL_FDCAN_STATE_BUSY)
+  {
+    /* Request initialisation */
+    SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_INIT);
+
+    /* Wait until the INIT bit into CCCR register is set */
+    while ((hfdcan->Instance->CCCR & FDCAN_CCCR_INIT) == 0U)
+    {
+      /* Check for the Timeout */
+      if (Counter > FDCAN_TIMEOUT_COUNT)
+      {
+        /* Update error code */
+        hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+        /* Change FDCAN state */
+        hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+        return HAL_ERROR;
+      }
+
+      /* Increment counter */
+      Counter++;
+    }
+
+    /* Reset counter */
+    Counter = 0U;
+
+    /* Exit from Sleep mode */
+    CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_CSR);
+
+    /* Wait until FDCAN exits sleep mode */
+    while ((hfdcan->Instance->CCCR & FDCAN_CCCR_CSA) == FDCAN_CCCR_CSA)
+    {
+      /* Check for the Timeout */
+      if (Counter > FDCAN_TIMEOUT_COUNT)
+      {
+        /* Update error code */
+        hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+        /* Change FDCAN state */
+        hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+        return HAL_ERROR;
+      }
+
+      /* Increment counter */
+      Counter++;
+    }
+
+    /* Enable configuration change */
+    SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_CCE);
+
+    /* Reset Latest Tx FIFO/Queue Request Buffer Index */
+    hfdcan->LatestTxFifoQRequest = 0U;
+
+    /* Change FDCAN peripheral state */
+    hfdcan->State = HAL_FDCAN_STATE_READY;
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_STARTED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Add a message to the Tx FIFO/Queue and activate the corresponding transmission request
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  pTxHeader pointer to a FDCAN_TxHeaderTypeDef structure.
+  * @param  pTxData pointer to a buffer containing the payload of the Tx frame.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxFifoQ(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData)
+{
+  uint32_t PutIndex;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_ID_TYPE(pTxHeader->IdType));
+  if (pTxHeader->IdType == FDCAN_STANDARD_ID)
+  {
+    assert_param(IS_FDCAN_MAX_VALUE(pTxHeader->Identifier, 0x7FFU));
+  }
+  else /* pTxHeader->IdType == FDCAN_EXTENDED_ID */
+  {
+    assert_param(IS_FDCAN_MAX_VALUE(pTxHeader->Identifier, 0x1FFFFFFFU));
+  }
+  assert_param(IS_FDCAN_FRAME_TYPE(pTxHeader->TxFrameType));
+  assert_param(IS_FDCAN_DLC(pTxHeader->DataLength));
+  assert_param(IS_FDCAN_ESI(pTxHeader->ErrorStateIndicator));
+  assert_param(IS_FDCAN_BRS(pTxHeader->BitRateSwitch));
+  assert_param(IS_FDCAN_FDF(pTxHeader->FDFormat));
+  assert_param(IS_FDCAN_EFC(pTxHeader->TxEventFifoControl));
+  assert_param(IS_FDCAN_MAX_VALUE(pTxHeader->MessageMarker, 0xFFU));
+
+  if (hfdcan->State == HAL_FDCAN_STATE_BUSY)
+  {
+    /* Check that the Tx FIFO/Queue has an allocated area into the RAM */
+    if ((hfdcan->Instance->TXBC & FDCAN_TXBC_TFQS) == 0U)
+    {
+      /* Update error code */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM;
+
+      return HAL_ERROR;
+    }
+
+    /* Check that the Tx FIFO/Queue is not full */
+    if ((hfdcan->Instance->TXFQS & FDCAN_TXFQS_TFQF) != 0U)
+    {
+      /* Update error code */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_FIFO_FULL;
+
+      return HAL_ERROR;
+    }
+    else
+    {
+      /* Retrieve the Tx FIFO PutIndex */
+      PutIndex = ((hfdcan->Instance->TXFQS & FDCAN_TXFQS_TFQPI) >> FDCAN_TXFQS_TFQPI_Pos);
+
+      /* Add the message to the Tx FIFO/Queue */
+      FDCAN_CopyMessageToRAM(hfdcan, pTxHeader, pTxData, PutIndex);
+
+      /* Activate the corresponding transmission request */
+      hfdcan->Instance->TXBAR = ((uint32_t)1 << PutIndex);
+
+      /* Store the Latest Tx FIFO/Queue Request Buffer Index */
+      hfdcan->LatestTxFifoQRequest = ((uint32_t)1 << PutIndex);
+    }
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_STARTED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Add a message to a dedicated Tx buffer
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  pTxHeader pointer to a FDCAN_TxHeaderTypeDef structure.
+  * @param  pTxData pointer to a buffer containing the payload of the Tx frame.
+  * @param  BufferIndex index of the buffer to be configured.
+  *         This parameter can be a value of @arg FDCAN_Tx_location.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxBuffer(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData, uint32_t BufferIndex)
+{
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_ID_TYPE(pTxHeader->IdType));
+  if (pTxHeader->IdType == FDCAN_STANDARD_ID)
+  {
+    assert_param(IS_FDCAN_MAX_VALUE(pTxHeader->Identifier, 0x7FFU));
+  }
+  else /* pTxHeader->IdType == FDCAN_EXTENDED_ID */
+  {
+    assert_param(IS_FDCAN_MAX_VALUE(pTxHeader->Identifier, 0x1FFFFFFFU));
+  }
+  assert_param(IS_FDCAN_FRAME_TYPE(pTxHeader->TxFrameType));
+  assert_param(IS_FDCAN_DLC(pTxHeader->DataLength));
+  assert_param(IS_FDCAN_ESI(pTxHeader->ErrorStateIndicator));
+  assert_param(IS_FDCAN_BRS(pTxHeader->BitRateSwitch));
+  assert_param(IS_FDCAN_FDF(pTxHeader->FDFormat));
+  assert_param(IS_FDCAN_EFC(pTxHeader->TxEventFifoControl));
+  assert_param(IS_FDCAN_MAX_VALUE(pTxHeader->MessageMarker, 0xFFU));
+  assert_param(IS_FDCAN_TX_LOCATION(BufferIndex));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    /* Check that the selected buffer has an allocated area into the RAM */
+    if (POSITION_VAL(BufferIndex) >= ((hfdcan->Instance->TXBC & FDCAN_TXBC_NDTB) >> FDCAN_TXBC_NDTB_Pos))
+    {
+      /* Update error code */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM;
+
+      return HAL_ERROR;
+    }
+
+    /* Check that there is no transmission request pending for the selected buffer */
+    if ((hfdcan->Instance->TXBRP & BufferIndex) != 0U)
+    {
+      /* Update error code */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PENDING;
+
+      return HAL_ERROR;
+    }
+    else
+    {
+      /* Add the message to the Tx buffer */
+      FDCAN_CopyMessageToRAM(hfdcan, pTxHeader, pTxData, POSITION_VAL(BufferIndex));
+    }
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Enable transmission request.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  BufferIndex buffer index.
+  *         This parameter can be any combination of @arg FDCAN_Tx_location.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_EnableTxBufferRequest(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndex)
+{
+  if (hfdcan->State == HAL_FDCAN_STATE_BUSY)
+  {
+    /* Add transmission request */
+    hfdcan->Instance->TXBAR = BufferIndex;
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_STARTED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Get Tx buffer index of latest Tx FIFO/Queue request
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval Tx buffer index of last Tx FIFO/Queue request
+  *          - Any value of @arg FDCAN_Tx_location if Tx request has been submitted.
+  *          - 0 if no Tx FIFO/Queue request have been submitted.
+  */
+uint32_t HAL_FDCAN_GetLatestTxFifoQRequestBuffer(FDCAN_HandleTypeDef *hfdcan)
+{
+  /* Return Last Tx FIFO/Queue Request Buffer */
+  return hfdcan->LatestTxFifoQRequest;
+}
+
+/**
+  * @brief  Abort transmission request
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  BufferIndex buffer index.
+  *         This parameter can be any combination of @arg FDCAN_Tx_location.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_AbortTxRequest(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndex)
+{
+  if (hfdcan->State == HAL_FDCAN_STATE_BUSY)
+  {
+    /* Add cancellation request */
+    hfdcan->Instance->TXBCR = BufferIndex;
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_STARTED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Get an FDCAN frame from the Rx Buffer/FIFO zone into the message RAM.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  RxLocation Location of the received message to be read.
+  *         This parameter can be a value of @arg FDCAN_Rx_location.
+  * @param  pRxHeader pointer to a FDCAN_RxHeaderTypeDef structure.
+  * @param  pRxData pointer to a buffer where the payload of the Rx frame will be stored.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_GetRxMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t RxLocation, FDCAN_RxHeaderTypeDef *pRxHeader, uint8_t *pRxData)
+{
+  uint32_t *RxAddress;
+  uint8_t  *pData;
+  uint32_t ByteCounter;
+  uint32_t GetIndex = 0;
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  if (state == HAL_FDCAN_STATE_BUSY)
+  {
+    if (RxLocation == FDCAN_RX_FIFO0) /* Rx element is assigned to the Rx FIFO 0 */
+    {
+      /* Check that the Rx FIFO 0 has an allocated area into the RAM */
+      if ((hfdcan->Instance->RXF0C & FDCAN_RXF0C_F0S) == 0U)
+      {
+        /* Update error code */
+        hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM;
+
+        return HAL_ERROR;
+      }
+
+      /* Check that the Rx FIFO 0 is not empty */
+      if ((hfdcan->Instance->RXF0S & FDCAN_RXF0S_F0FL) == 0U)
+      {
+        /* Update error code */
+        hfdcan->ErrorCode |= HAL_FDCAN_ERROR_FIFO_EMPTY;
+
+        return HAL_ERROR;
+      }
+      else
+      {
+        /* Check that the Rx FIFO 0 is full & overwrite mode is on*/
+        if(((hfdcan->Instance->RXF0S & FDCAN_RXF0S_F0F) >> FDCAN_RXF0S_F0F_Pos) == 1U)
+        {
+          if(((hfdcan->Instance->RXF0C & FDCAN_RXF0C_F0OM) >> FDCAN_RXF0C_F0OM_Pos) == FDCAN_RX_FIFO_OVERWRITE)
+          {
+            /* When overwrite status is on discard first message in FIFO */
+            GetIndex = 1U;
+          }
+        }
+
+        /* Calculate Rx FIFO 0 element index*/
+        GetIndex += ((hfdcan->Instance->RXF0S & FDCAN_RXF0S_F0GI) >> FDCAN_RXF0S_F0GI_Pos);
+
+        /* Calculate Rx FIFO 0 element address */
+        RxAddress = (uint32_t *)(hfdcan->msgRam.RxFIFO0SA + (GetIndex * hfdcan->Init.RxFifo0ElmtSize * 4U));
+      }
+    }
+    else if (RxLocation == FDCAN_RX_FIFO1) /* Rx element is assigned to the Rx FIFO 1 */
+    {
+      /* Check that the Rx FIFO 1 has an allocated area into the RAM */
+      if ((hfdcan->Instance->RXF1C & FDCAN_RXF1C_F1S) == 0U)
+      {
+        /* Update error code */
+        hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM;
+
+        return HAL_ERROR;
+      }
+
+      /* Check that the Rx FIFO 0 is not empty */
+      if ((hfdcan->Instance->RXF1S & FDCAN_RXF1S_F1FL) == 0U)
+      {
+        /* Update error code */
+        hfdcan->ErrorCode |= HAL_FDCAN_ERROR_FIFO_EMPTY;
+
+        return HAL_ERROR;
+      }
+      else
+      {
+        /* Check that the Rx FIFO 1 is full & overwrite mode is on*/
+        if(((hfdcan->Instance->RXF1S & FDCAN_RXF1S_F1F) >> FDCAN_RXF1S_F1F_Pos) == 1U)
+        {
+          if(((hfdcan->Instance->RXF1C & FDCAN_RXF1C_F1OM) >> FDCAN_RXF1C_F1OM_Pos) == FDCAN_RX_FIFO_OVERWRITE)
+          {
+            /* When overwrite status is on discard first message in FIFO */
+            GetIndex = 1U;
+          }
+        }
+
+        /* Calculate Rx FIFO 1 element index*/
+        GetIndex += ((hfdcan->Instance->RXF1S & FDCAN_RXF1S_F1GI) >> FDCAN_RXF1S_F1GI_Pos);
+
+        /* Calculate Rx FIFO 1 element address */
+        RxAddress = (uint32_t *)(hfdcan->msgRam.RxFIFO1SA + (GetIndex * hfdcan->Init.RxFifo1ElmtSize * 4U));
+      }
+    }
+    else /* Rx element is assigned to a dedicated Rx buffer */
+    {
+      /* Check that the selected buffer has an allocated area into the RAM */
+      if (RxLocation >= hfdcan->Init.RxBuffersNbr)
+      {
+        /* Update error code */
+        hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM;
+
+        return HAL_ERROR;
+      }
+      else
+      {
+        /* Calculate Rx buffer address */
+        RxAddress = (uint32_t *)(hfdcan->msgRam.RxBufferSA + (RxLocation * hfdcan->Init.RxBufferSize * 4U));
+      }
+    }
+
+    /* Retrieve IdType */
+    pRxHeader->IdType = *RxAddress & FDCAN_ELEMENT_MASK_XTD;
+
+    /* Retrieve Identifier */
+    if (pRxHeader->IdType == FDCAN_STANDARD_ID) /* Standard ID element */
+    {
+      pRxHeader->Identifier = ((*RxAddress & FDCAN_ELEMENT_MASK_STDID) >> 18);
+    }
+    else /* Extended ID element */
+    {
+      pRxHeader->Identifier = (*RxAddress & FDCAN_ELEMENT_MASK_EXTID);
+    }
+
+    /* Retrieve RxFrameType */
+    pRxHeader->RxFrameType = (*RxAddress & FDCAN_ELEMENT_MASK_RTR);
+
+    /* Retrieve ErrorStateIndicator */
+    pRxHeader->ErrorStateIndicator = (*RxAddress & FDCAN_ELEMENT_MASK_ESI);
+
+    /* Increment RxAddress pointer to second word of Rx FIFO element */
+    RxAddress++;
+
+    /* Retrieve RxTimestamp */
+    pRxHeader->RxTimestamp = (*RxAddress & FDCAN_ELEMENT_MASK_TS);
+
+    /* Retrieve DataLength */
+    pRxHeader->DataLength = (*RxAddress & FDCAN_ELEMENT_MASK_DLC);
+
+    /* Retrieve BitRateSwitch */
+    pRxHeader->BitRateSwitch = (*RxAddress & FDCAN_ELEMENT_MASK_BRS);
+
+    /* Retrieve FDFormat */
+    pRxHeader->FDFormat = (*RxAddress & FDCAN_ELEMENT_MASK_FDF);
+
+    /* Retrieve FilterIndex */
+    pRxHeader->FilterIndex = ((*RxAddress & FDCAN_ELEMENT_MASK_FIDX) >> 24);
+
+    /* Retrieve NonMatchingFrame */
+    pRxHeader->IsFilterMatchingFrame = ((*RxAddress & FDCAN_ELEMENT_MASK_ANMF) >> 31);
+
+    /* Increment RxAddress pointer to payload of Rx FIFO element */
+    RxAddress++;
+
+    /* Retrieve Rx payload */
+    pData = (uint8_t *)RxAddress;
+    for (ByteCounter = 0; ByteCounter < DLCtoBytes[pRxHeader->DataLength >> 16]; ByteCounter++)
+    {
+      pRxData[ByteCounter] = pData[ByteCounter];
+    }
+
+    if (RxLocation == FDCAN_RX_FIFO0) /* Rx element is assigned to the Rx FIFO 0 */
+    {
+      /* Acknowledge the Rx FIFO 0 that the oldest element is read so that it increments the GetIndex */
+      hfdcan->Instance->RXF0A = GetIndex;
+    }
+    else if (RxLocation == FDCAN_RX_FIFO1) /* Rx element is assigned to the Rx FIFO 1 */
+    {
+      /* Acknowledge the Rx FIFO 1 that the oldest element is read so that it increments the GetIndex */
+      hfdcan->Instance->RXF1A = GetIndex;
+    }
+    else /* Rx element is assigned to a dedicated Rx buffer */
+    {
+      /* Clear the New Data flag of the current Rx buffer */
+      if (RxLocation < FDCAN_RX_BUFFER32)
+      {
+        hfdcan->Instance->NDAT1 = ((uint32_t)1 << RxLocation);
+      }
+      else /* FDCAN_RX_BUFFER32 <= RxLocation <= FDCAN_RX_BUFFER63 */
+      {
+        hfdcan->Instance->NDAT2 = ((uint32_t)1 << (RxLocation & 0x1FU));
+      }
+    }
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_STARTED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Get an FDCAN Tx event from the Tx Event FIFO zone into the message RAM.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  pTxEvent pointer to a FDCAN_TxEventFifoTypeDef structure.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_GetTxEvent(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxEventFifoTypeDef *pTxEvent)
+{
+  uint32_t *TxEventAddress;
+  uint32_t GetIndex;
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_MIN_VALUE(hfdcan->Init.TxEventsNbr, 1U));
+
+  if (state == HAL_FDCAN_STATE_BUSY)
+  {
+    /* Check that the Tx Event FIFO has an allocated area into the RAM */
+    if ((hfdcan->Instance->TXEFC & FDCAN_TXEFC_EFS) == 0U)
+    {
+      /* Update error code */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM;
+
+      return HAL_ERROR;
+    }
+
+    /* Check that the Tx event FIFO is not empty */
+    if ((hfdcan->Instance->TXEFS & FDCAN_TXEFS_EFFL) == 0U)
+    {
+      /* Update error code */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_FIFO_EMPTY;
+
+      return HAL_ERROR;
+    }
+
+    /* Calculate Tx event FIFO element address */
+    GetIndex = ((hfdcan->Instance->TXEFS & FDCAN_TXEFS_EFGI) >> FDCAN_TXEFS_EFGI_Pos);
+    TxEventAddress = (uint32_t *)(hfdcan->msgRam.TxEventFIFOSA + (GetIndex * 2U * 4U));
+
+    /* Retrieve IdType */
+    pTxEvent->IdType = *TxEventAddress & FDCAN_ELEMENT_MASK_XTD;
+
+    /* Retrieve Identifier */
+    if (pTxEvent->IdType == FDCAN_STANDARD_ID) /* Standard ID element */
+    {
+      pTxEvent->Identifier = ((*TxEventAddress & FDCAN_ELEMENT_MASK_STDID) >> 18U);
+    }
+    else /* Extended ID element */
+    {
+      pTxEvent->Identifier = (*TxEventAddress & FDCAN_ELEMENT_MASK_EXTID);
+    }
+
+    /* Retrieve TxFrameType */
+    pTxEvent->TxFrameType = (*TxEventAddress & FDCAN_ELEMENT_MASK_RTR);
+
+    /* Retrieve ErrorStateIndicator */
+    pTxEvent->ErrorStateIndicator = (*TxEventAddress & FDCAN_ELEMENT_MASK_ESI);
+
+    /* Increment TxEventAddress pointer to second word of Tx Event FIFO element */
+    TxEventAddress++;
+
+    /* Retrieve TxTimestamp */
+    pTxEvent->TxTimestamp = (*TxEventAddress & FDCAN_ELEMENT_MASK_TS);
+
+    /* Retrieve DataLength */
+    pTxEvent->DataLength = (*TxEventAddress & FDCAN_ELEMENT_MASK_DLC);
+
+    /* Retrieve BitRateSwitch */
+    pTxEvent->BitRateSwitch = (*TxEventAddress & FDCAN_ELEMENT_MASK_BRS);
+
+    /* Retrieve FDFormat */
+    pTxEvent->FDFormat = (*TxEventAddress & FDCAN_ELEMENT_MASK_FDF);
+
+    /* Retrieve EventType */
+    pTxEvent->EventType = (*TxEventAddress & FDCAN_ELEMENT_MASK_ET);
+
+    /* Retrieve MessageMarker */
+    pTxEvent->MessageMarker = ((*TxEventAddress & FDCAN_ELEMENT_MASK_MM) >> 24);
+
+    /* Acknowledge the Tx Event FIFO that the oldest element is read so that it increments the GetIndex */
+    hfdcan->Instance->TXEFA = GetIndex;
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_STARTED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Get high priority message status.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  HpMsgStatus pointer to an FDCAN_HpMsgStatusTypeDef structure.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_GetHighPriorityMessageStatus(FDCAN_HandleTypeDef *hfdcan, FDCAN_HpMsgStatusTypeDef *HpMsgStatus)
+{
+  HpMsgStatus->FilterList = ((hfdcan->Instance->HPMS & FDCAN_HPMS_FLST) >> FDCAN_HPMS_FLST_Pos);
+  HpMsgStatus->FilterIndex = ((hfdcan->Instance->HPMS & FDCAN_HPMS_FIDX) >> FDCAN_HPMS_FIDX_Pos);
+  HpMsgStatus->MessageStorage = (hfdcan->Instance->HPMS & FDCAN_HPMS_MSI);
+  HpMsgStatus->MessageIndex = (hfdcan->Instance->HPMS & FDCAN_HPMS_BIDX);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Get protocol status.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  ProtocolStatus pointer to an FDCAN_ProtocolStatusTypeDef structure.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_GetProtocolStatus(FDCAN_HandleTypeDef *hfdcan, FDCAN_ProtocolStatusTypeDef *ProtocolStatus)
+{
+  uint32_t StatusReg;
+
+  /* Read the protocol status register */
+  StatusReg = READ_REG(hfdcan->Instance->PSR);
+
+  /* Fill the protocol status structure */
+  ProtocolStatus->LastErrorCode = (StatusReg & FDCAN_PSR_LEC);
+  ProtocolStatus->DataLastErrorCode = ((StatusReg & FDCAN_PSR_DLEC) >> FDCAN_PSR_DLEC_Pos);
+  ProtocolStatus->Activity = (StatusReg & FDCAN_PSR_ACT);
+  ProtocolStatus->ErrorPassive = ((StatusReg & FDCAN_PSR_EP) >> FDCAN_PSR_EP_Pos);
+  ProtocolStatus->Warning = ((StatusReg & FDCAN_PSR_EW) >> FDCAN_PSR_EW_Pos);
+  ProtocolStatus->BusOff = ((StatusReg & FDCAN_PSR_BO) >> FDCAN_PSR_BO_Pos);
+  ProtocolStatus->RxESIflag = ((StatusReg & FDCAN_PSR_RESI) >> FDCAN_PSR_RESI_Pos);
+  ProtocolStatus->RxBRSflag = ((StatusReg & FDCAN_PSR_RBRS) >> FDCAN_PSR_RBRS_Pos);
+  ProtocolStatus->RxFDFflag = ((StatusReg & FDCAN_PSR_REDL) >> FDCAN_PSR_REDL_Pos);
+  ProtocolStatus->ProtocolException = ((StatusReg & FDCAN_PSR_PXE) >> FDCAN_PSR_PXE_Pos);
+  ProtocolStatus->TDCvalue = ((StatusReg & FDCAN_PSR_TDCV) >> FDCAN_PSR_TDCV_Pos);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Get error counter values.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  ErrorCounters pointer to an FDCAN_ErrorCountersTypeDef structure.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_GetErrorCounters(FDCAN_HandleTypeDef *hfdcan, FDCAN_ErrorCountersTypeDef *ErrorCounters)
+{
+  uint32_t CountersReg;
+
+  /* Read the error counters register */
+  CountersReg = READ_REG(hfdcan->Instance->ECR);
+
+  /* Fill the error counters structure */
+  ErrorCounters->TxErrorCnt = ((CountersReg & FDCAN_ECR_TEC) >> FDCAN_ECR_TEC_Pos);
+  ErrorCounters->RxErrorCnt = ((CountersReg & FDCAN_ECR_REC) >> FDCAN_ECR_REC_Pos);
+  ErrorCounters->RxErrorPassive = ((CountersReg & FDCAN_ECR_RP) >> FDCAN_ECR_RP_Pos);
+  ErrorCounters->ErrorLogging = ((CountersReg & FDCAN_ECR_CEL) >> FDCAN_ECR_CEL_Pos);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Check if a new message is received in the selected Rx buffer.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  RxBufferIndex Rx buffer index.
+  *         This parameter must be a number between 0 and 63.
+  * @retval Status
+  *          - 0 : No new message on RxBufferIndex.
+  *          - 1 : New message received on RxBufferIndex.
+  */
+uint32_t HAL_FDCAN_IsRxBufferMessageAvailable(FDCAN_HandleTypeDef *hfdcan, uint32_t RxBufferIndex)
+{
+  /* Check function parameters */
+  assert_param(IS_FDCAN_MAX_VALUE(RxBufferIndex, 63U));
+  uint32_t NewData1 = hfdcan->Instance->NDAT1;
+  uint32_t NewData2 = hfdcan->Instance->NDAT2;
+
+  /* Check new message reception on the selected buffer */
+  if (((RxBufferIndex < 32U) && ((NewData1 & (uint32_t)((uint32_t)1 << RxBufferIndex)) == 0U)) ||
+      ((RxBufferIndex >= 32U) && ((NewData2 & (uint32_t)((uint32_t)1 << (RxBufferIndex & 0x1FU))) == 0U)))
+  {
+    return 0;
+  }
+
+  /* Clear the New Data flag of the current Rx buffer */
+  if (RxBufferIndex < 32U)
+  {
+    hfdcan->Instance->NDAT1 = ((uint32_t)1 << RxBufferIndex);
+  }
+  else /* 32 <= RxBufferIndex <= 63 */
+  {
+    hfdcan->Instance->NDAT2 = ((uint32_t)1 << (RxBufferIndex & 0x1FU));
+  }
+
+  return 1;
+}
+
+/**
+  * @brief  Check if a transmission request is pending on the selected Tx buffer.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  TxBufferIndex Tx buffer index.
+  *         This parameter can be any combination of @arg FDCAN_Tx_location.
+  * @retval Status
+  *          - 0 : No pending transmission request on TxBufferIndex.
+  *          - 1 : Pending transmission request on TxBufferIndex.
+  */
+uint32_t HAL_FDCAN_IsTxBufferMessagePending(FDCAN_HandleTypeDef *hfdcan, uint32_t TxBufferIndex)
+{
+  /* Check pending transmission request on the selected buffer */
+  if ((hfdcan->Instance->TXBRP & TxBufferIndex) == 0U)
+  {
+    return 0;
+  }
+  return 1;
+}
+
+/**
+  * @brief  Return Rx FIFO fill level.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  RxFifo Rx FIFO.
+  *         This parameter can be one of the following values:
+  *           @arg FDCAN_RX_FIFO0: Rx FIFO 0
+  *           @arg FDCAN_RX_FIFO1: Rx FIFO 1
+  * @retval Level Rx FIFO fill level.
+  */
+uint32_t HAL_FDCAN_GetRxFifoFillLevel(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo)
+{
+  uint32_t FillLevel;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_RX_FIFO(RxFifo));
+
+  if (RxFifo == FDCAN_RX_FIFO0)
+  {
+    FillLevel = hfdcan->Instance->RXF0S & FDCAN_RXF0S_F0FL;
+  }
+  else /* RxFifo == FDCAN_RX_FIFO1 */
+  {
+    FillLevel = hfdcan->Instance->RXF1S & FDCAN_RXF1S_F1FL;
+  }
+
+  /* Return Rx FIFO fill level */
+  return FillLevel;
+}
+
+/**
+  * @brief  Return Tx FIFO free level: number of consecutive free Tx FIFO
+  *         elements starting from Tx FIFO GetIndex.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval Level Tx FIFO free level.
+  */
+uint32_t HAL_FDCAN_GetTxFifoFreeLevel(FDCAN_HandleTypeDef *hfdcan)
+{
+  uint32_t FreeLevel;
+
+  FreeLevel = hfdcan->Instance->TXFQS & FDCAN_TXFQS_TFFL;
+
+  /* Return Tx FIFO free level */
+  return FreeLevel;
+}
+
+/**
+  * @brief  Check if the FDCAN peripheral entered Restricted Operation Mode.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval Status
+  *          - 0 : Normal FDCAN operation.
+  *          - 1 : Restricted Operation Mode active.
+  */
+uint32_t HAL_FDCAN_IsRestrictedOperationMode(FDCAN_HandleTypeDef *hfdcan)
+{
+  uint32_t OperationMode;
+
+  /* Get Operation Mode */
+  OperationMode = ((hfdcan->Instance->CCCR & FDCAN_CCCR_ASM) >> FDCAN_CCCR_ASM_Pos);
+
+  return OperationMode;
+}
+
+/**
+  * @brief  Exit Restricted Operation Mode.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_ExitRestrictedOperationMode(FDCAN_HandleTypeDef *hfdcan)
+{
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    /* Exit Restricted Operation mode */
+    CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_ASM);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Exported_Functions_Group4 TT Configuration and control functions
+ *  @brief    TT Configuration and control functions
+ *
+@verbatim
+  ==============================================================================
+              ##### TT Configuration and control functions #####
+  ==============================================================================
+    [..]  This section provides functions allowing to:
+      (+) HAL_FDCAN_TT_ConfigOperation                  : Initialize TT operation parameters
+      (+) HAL_FDCAN_TT_ConfigReferenceMessage           : Configure the reference message
+      (+) HAL_FDCAN_TT_ConfigTrigger                    : Configure the FDCAN trigger
+      (+) HAL_FDCAN_TT_SetGlobalTime                    : Schedule global time adjustment
+      (+) HAL_FDCAN_TT_SetClockSynchronization          : Schedule TUR numerator update
+      (+) HAL_FDCAN_TT_ConfigStopWatch                  : Configure stop watch source and polarity
+      (+) HAL_FDCAN_TT_ConfigRegisterTimeMark           : Configure register time mark pulse generation
+        (+) HAL_FDCAN_TT_EnableRegisterTimeMarkPulse      : Enable register time mark pulse generation
+        (+) HAL_FDCAN_TT_DisableRegisterTimeMarkPulse     : Disable register time mark pulse generation
+      (+) HAL_FDCAN_TT_EnableTriggerTimeMarkPulse       : Enable trigger time mark pulse generation
+      (+) HAL_FDCAN_TT_DisableTriggerTimeMarkPulse      : Disable trigger time mark pulse generation
+      (+) HAL_FDCAN_TT_EnableHardwareGapControl         : Enable gap control by input pin fdcan1_evt
+      (+) HAL_FDCAN_TT_DisableHardwareGapControl        : Disable gap control by input pin fdcan1_evt
+      (+) HAL_FDCAN_TT_EnableTimeMarkGapControl         : Enable gap control (finish only) by register time mark interrupt
+      (+) HAL_FDCAN_TT_DisableTimeMarkGapControl        : Disable gap control by register time mark interrupt
+      (+) HAL_FDCAN_TT_SetNextIsGap                     : Transmit next reference message with Next_is_Gap = "1"
+      (+) HAL_FDCAN_TT_SetEndOfGap                      : Finish a Gap by requesting start of reference message
+      (+) HAL_FDCAN_TT_ConfigExternalSyncPhase          : Configure target phase used for external synchronization
+        (+) HAL_FDCAN_TT_EnableExternalSynchronization    : Synchronize the phase of the FDCAN schedule to an external schedule
+        (+) HAL_FDCAN_TT_DisableExternalSynchronization   : Disable external schedule synchronization
+      (+) HAL_FDCAN_TT_GetOperationStatus               : Get TT operation status
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initialize TT operation parameters.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  pTTParams pointer to a FDCAN_TT_ConfigTypeDef structure.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_ConfigOperation(FDCAN_HandleTypeDef *hfdcan, FDCAN_TT_ConfigTypeDef *pTTParams)
+{
+  uint32_t tickstart;
+  uint32_t RAMcounter;
+  uint32_t StartAddress;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+  assert_param(IS_FDCAN_TT_TUR_NUMERATOR(pTTParams->TURNumerator));
+  assert_param(IS_FDCAN_TT_TUR_DENOMINATOR(pTTParams->TURDenominator));
+  assert_param(IS_FDCAN_TT_TIME_MASTER(pTTParams->TimeMaster));
+  assert_param(IS_FDCAN_MAX_VALUE(pTTParams->SyncDevLimit, 7U));
+  assert_param(IS_FDCAN_MAX_VALUE(pTTParams->InitRefTrigOffset, 127U));
+  assert_param(IS_FDCAN_MAX_VALUE(pTTParams->TriggerMemoryNbr, 64U));
+  assert_param(IS_FDCAN_TT_CYCLE_START_SYNC(pTTParams->CycleStartSync));
+  assert_param(IS_FDCAN_TT_STOP_WATCH_TRIGGER(pTTParams->StopWatchTrigSel));
+  assert_param(IS_FDCAN_TT_EVENT_TRIGGER(pTTParams->EventTrigSel));
+  if (pTTParams->TimeMaster == FDCAN_TT_POTENTIAL_MASTER)
+  {
+    assert_param(IS_FDCAN_TT_BASIC_CYCLES_NUMBER(pTTParams->BasicCyclesNbr));
+  }
+  if (pTTParams->OperationMode != FDCAN_TT_COMMUNICATION_LEVEL0)
+  {
+    assert_param(IS_FDCAN_TT_OPERATION(pTTParams->GapEnable));
+    assert_param(IS_FDCAN_MAX_VALUE(pTTParams->AppWdgLimit, 255U));
+    assert_param(IS_FDCAN_TT_EVENT_TRIGGER_POLARITY(pTTParams->EvtTrigPolarity));
+    assert_param(IS_FDCAN_TT_TX_ENABLE_WINDOW(pTTParams->TxEnableWindow));
+    assert_param(IS_FDCAN_MAX_VALUE(pTTParams->ExpTxTrigNbr, 4095U));
+  }
+  if (pTTParams->OperationMode != FDCAN_TT_COMMUNICATION_LEVEL1)
+  {
+    assert_param(IS_FDCAN_TT_TUR_LEVEL_0_2(pTTParams->TURNumerator, pTTParams->TURDenominator));
+    assert_param(IS_FDCAN_TT_EXTERNAL_CLK_SYNC(pTTParams->ExternalClkSync));
+    assert_param(IS_FDCAN_TT_GLOBAL_TIME_FILTERING(pTTParams->GlobalTimeFilter));
+    assert_param(IS_FDCAN_TT_AUTO_CLK_CALIBRATION(pTTParams->ClockCalibration));
+  }
+  else
+  {
+    assert_param(IS_FDCAN_TT_TUR_LEVEL_1(pTTParams->TURNumerator, pTTParams->TURDenominator));
+  }
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    /* Stop local time in order to enable write access to the other bits of TURCF register */
+    CLEAR_BIT(hfdcan->ttcan->TURCF, FDCAN_TURCF_ELT);
+
+    /* Get tick */
+    tickstart = HAL_GetTick();
+
+    /* Wait until the ELT bit into TURCF register is reset */
+    while ((hfdcan->ttcan->TURCF & FDCAN_TURCF_ELT) != 0U)
+    {
+      /* Check for the Timeout */
+      if ((HAL_GetTick() - tickstart) > FDCAN_TIMEOUT_VALUE)
+      {
+        /* Update error code */
+        hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+        /* Change FDCAN state */
+        hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+        return HAL_ERROR;
+      }
+    }
+
+    /* Configure TUR (Time Unit Ratio) */
+    MODIFY_REG(hfdcan->ttcan->TURCF,
+               (FDCAN_TURCF_NCL | FDCAN_TURCF_DC),
+               (((pTTParams->TURNumerator - 0x10000U) << FDCAN_TURCF_NCL_Pos) | (pTTParams->TURDenominator << FDCAN_TURCF_DC_Pos)));
+
+    /* Enable local time */
+    SET_BIT(hfdcan->ttcan->TURCF, FDCAN_TURCF_ELT);
+
+    /* Configure TT operation */
+    MODIFY_REG(hfdcan->ttcan->TTOCF,
+               (FDCAN_TTOCF_OM | FDCAN_TTOCF_TM | FDCAN_TTOCF_LDSDL | FDCAN_TTOCF_IRTO),
+               (pTTParams->OperationMode                           | \
+                pTTParams->TimeMaster                              | \
+                (pTTParams->SyncDevLimit << FDCAN_TTOCF_LDSDL_Pos) | \
+                (pTTParams->InitRefTrigOffset << FDCAN_TTOCF_IRTO_Pos)));
+    if (pTTParams->OperationMode != FDCAN_TT_COMMUNICATION_LEVEL0)
+    {
+      MODIFY_REG(hfdcan->ttcan->TTOCF,
+                 (FDCAN_TTOCF_GEN | FDCAN_TTOCF_AWL | FDCAN_TTOCF_EVTP),
+                 (pTTParams->GapEnable                            | \
+                  (pTTParams->AppWdgLimit << FDCAN_TTOCF_AWL_Pos) | \
+                  pTTParams->EvtTrigPolarity));
+    }
+    if (pTTParams->OperationMode != FDCAN_TT_COMMUNICATION_LEVEL1)
+    {
+      MODIFY_REG(hfdcan->ttcan->TTOCF,
+                 (FDCAN_TTOCF_EECS | FDCAN_TTOCF_EGTF | FDCAN_TTOCF_ECC),
+                 (pTTParams->ExternalClkSync  | \
+                  pTTParams->GlobalTimeFilter | \
+                  pTTParams->ClockCalibration));
+    }
+
+    /* Configure system matrix limits */
+    MODIFY_REG(hfdcan->ttcan->TTMLM, FDCAN_TTMLM_CSS, pTTParams->CycleStartSync);
+    if (pTTParams->OperationMode != FDCAN_TT_COMMUNICATION_LEVEL0)
+    {
+      MODIFY_REG(hfdcan->ttcan->TTMLM,
+                 (FDCAN_TTMLM_TXEW | FDCAN_TTMLM_ENTT),
+                 (((pTTParams->TxEnableWindow - 1U) << FDCAN_TTMLM_TXEW_Pos) | (pTTParams->ExpTxTrigNbr << FDCAN_TTMLM_ENTT_Pos)));
+    }
+    if (pTTParams->TimeMaster == FDCAN_TT_POTENTIAL_MASTER)
+    {
+      MODIFY_REG(hfdcan->ttcan->TTMLM, FDCAN_TTMLM_CCM, pTTParams->BasicCyclesNbr);
+    }
+
+    /* Configure input triggers: Stop watch and Event */
+    MODIFY_REG(hfdcan->ttcan->TTTS,
+               (FDCAN_TTTS_SWTSEL | FDCAN_TTTS_EVTSEL),
+               (pTTParams->StopWatchTrigSel | pTTParams->EventTrigSel));
+
+    /* Configure trigger memory start address */
+    StartAddress = (hfdcan->msgRam.EndAddress - SRAMCAN_BASE) / 4U;
+    MODIFY_REG(hfdcan->ttcan->TTTMC, FDCAN_TTTMC_TMSA, (StartAddress << FDCAN_TTTMC_TMSA_Pos));
+
+    /* Trigger memory elements number */
+    MODIFY_REG(hfdcan->ttcan->TTTMC, FDCAN_TTTMC_TME, (pTTParams->TriggerMemoryNbr << FDCAN_TTTMC_TME_Pos));
+
+    /* Recalculate End Address */
+    hfdcan->msgRam.TTMemorySA = hfdcan->msgRam.EndAddress;
+    hfdcan->msgRam.EndAddress = hfdcan->msgRam.TTMemorySA + (pTTParams->TriggerMemoryNbr * 2U * 4U);
+
+    if (hfdcan->msgRam.EndAddress > FDCAN_MESSAGE_RAM_END_ADDRESS) /* Last address of the Message RAM */
+    {
+      /* Update error code.
+         Message RAM overflow */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM;
+
+      return HAL_ERROR;
+    }
+    else
+    {
+      /* Flush the allocated Message RAM area */
+      for (RAMcounter = hfdcan->msgRam.TTMemorySA; RAMcounter < hfdcan->msgRam.EndAddress; RAMcounter += 4U)
+      {
+        *(uint32_t *)(RAMcounter) = 0x00000000;
+      }
+    }
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Configure the reference message.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  IdType Identifier Type.
+  *         This parameter can be a value of @arg FDCAN_id_type.
+  * @param  Identifier Reference Identifier.
+  *         This parameter must be a number between:
+  *           - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID
+  *           - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID
+  * @param  Payload Enable or disable the additional payload.
+  *         This parameter can be a value of @arg FDCAN_TT_Reference_Message_Payload.
+  *         This parameter is ignored in case of time slaves.
+  *         If this parameter is set to FDCAN_TT_REF_MESSAGE_ADD_PAYLOAD, the
+  *         following elements are taken from Tx Buffer 0:
+  *          - MessageMarker
+  *          - TxEventFifoControl
+  *          - DataLength
+  *          - Data Bytes (payload):
+  *             - bytes 2-8, for Level 1
+  *             - bytes 5-8, for Level 0 and Level 2
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_ConfigReferenceMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t IdType, uint32_t Identifier, uint32_t Payload)
+{
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+  assert_param(IS_FDCAN_ID_TYPE(IdType));
+  if (IdType == FDCAN_STANDARD_ID)
+  {
+    assert_param(IS_FDCAN_MAX_VALUE(Identifier, 0x7FFU));
+  }
+  else /* IdType == FDCAN_EXTENDED_ID */
+  {
+    assert_param(IS_FDCAN_MAX_VALUE(Identifier, 0x1FFFFFFFU));
+  }
+  assert_param(IS_FDCAN_TT_REFERENCE_MESSAGE_PAYLOAD(Payload));
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    /* Configure reference message identifier type, identifier and payload */
+    if (IdType == FDCAN_EXTENDED_ID)
+    {
+      MODIFY_REG(hfdcan->ttcan->TTRMC, (FDCAN_TTRMC_RID | FDCAN_TTRMC_XTD | FDCAN_TTRMC_RMPS), (Payload | IdType | Identifier));
+    }
+    else /* IdType == FDCAN_STANDARD_ID */
+    {
+      MODIFY_REG(hfdcan->ttcan->TTRMC, (FDCAN_TTRMC_RID | FDCAN_TTRMC_XTD | FDCAN_TTRMC_RMPS), (Payload | IdType | (Identifier << 18)));
+    }
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Configure the FDCAN trigger according to the specified
+  *         parameters in the FDCAN_TriggerTypeDef structure.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  sTriggerConfig pointer to an FDCAN_TriggerTypeDef structure that
+  *         contains the trigger configuration information
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_ConfigTrigger(FDCAN_HandleTypeDef *hfdcan, FDCAN_TriggerTypeDef *sTriggerConfig)
+{
+  uint32_t CycleCode;
+  uint32_t MessageNumber;
+  uint32_t TriggerElementW1;
+  uint32_t TriggerElementW2;
+  uint32_t *TriggerAddress;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+  assert_param(IS_FDCAN_MAX_VALUE(sTriggerConfig->TriggerIndex, 63U));
+  assert_param(IS_FDCAN_MAX_VALUE(sTriggerConfig->TimeMark, 0xFFFFU));
+  assert_param(IS_FDCAN_TT_REPEAT_FACTOR(sTriggerConfig->RepeatFactor));
+  if (sTriggerConfig->RepeatFactor != FDCAN_TT_REPEAT_EVERY_CYCLE)
+  {
+    assert_param(IS_FDCAN_MAX_VALUE(sTriggerConfig->StartCycle, (sTriggerConfig->RepeatFactor - 1U)));
+  }
+  assert_param(IS_FDCAN_TT_TM_EVENT_INTERNAL(sTriggerConfig->TmEventInt));
+  assert_param(IS_FDCAN_TT_TM_EVENT_EXTERNAL(sTriggerConfig->TmEventExt));
+  assert_param(IS_FDCAN_TT_TRIGGER_TYPE(sTriggerConfig->TriggerType));
+  assert_param(IS_FDCAN_ID_TYPE(sTriggerConfig->FilterType));
+  if ((sTriggerConfig->TriggerType == FDCAN_TT_TX_TRIGGER_SINGLE) ||
+      (sTriggerConfig->TriggerType == FDCAN_TT_TX_TRIGGER_CONTINUOUS) ||
+      (sTriggerConfig->TriggerType == FDCAN_TT_TX_TRIGGER_ARBITRATION) ||
+      (sTriggerConfig->TriggerType == FDCAN_TT_TX_TRIGGER_MERGED))
+  {
+    assert_param(IS_FDCAN_TX_LOCATION(sTriggerConfig->TxBufferIndex));
+  }
+  if (sTriggerConfig->TriggerType == FDCAN_TT_RX_TRIGGER)
+  {
+    if (sTriggerConfig->FilterType == FDCAN_STANDARD_ID)
+    {
+      assert_param(IS_FDCAN_MAX_VALUE(sTriggerConfig->FilterIndex, 63U));
+    }
+    else /* sTriggerConfig->FilterType == FDCAN_EXTENDED_ID */
+    {
+      assert_param(IS_FDCAN_MAX_VALUE(sTriggerConfig->FilterIndex, 127U));
+    }
+  }
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    /* Calculate cycle code */
+    if (sTriggerConfig->RepeatFactor == FDCAN_TT_REPEAT_EVERY_CYCLE)
+    {
+      CycleCode = FDCAN_TT_REPEAT_EVERY_CYCLE;
+    }
+    else /* sTriggerConfig->RepeatFactor != FDCAN_TT_REPEAT_EVERY_CYCLE */
+    {
+      CycleCode = sTriggerConfig->RepeatFactor + sTriggerConfig->StartCycle;
+    }
+
+    /* Build first word of trigger element */
+    TriggerElementW1 = ((sTriggerConfig->TimeMark << 16) | \
+                        (CycleCode << 8)                 | \
+                        sTriggerConfig->TmEventInt       | \
+                        sTriggerConfig->TmEventExt       | \
+                        sTriggerConfig->TriggerType);
+
+    /* Select message number depending on trigger type (transmission or reception) */
+    if (sTriggerConfig->TriggerType == FDCAN_TT_RX_TRIGGER)
+    {
+      MessageNumber = sTriggerConfig->FilterIndex;
+    }
+    else if ((sTriggerConfig->TriggerType == FDCAN_TT_TX_TRIGGER_SINGLE) ||
+             (sTriggerConfig->TriggerType == FDCAN_TT_TX_TRIGGER_CONTINUOUS) ||
+             (sTriggerConfig->TriggerType == FDCAN_TT_TX_TRIGGER_ARBITRATION) ||
+             (sTriggerConfig->TriggerType == FDCAN_TT_TX_TRIGGER_MERGED))
+    {
+      MessageNumber = POSITION_VAL(sTriggerConfig->TxBufferIndex);
+    }
+    else
+    {
+      MessageNumber = 0U;
+    }
+
+    /* Build second word of trigger element */
+    TriggerElementW2 = ((sTriggerConfig->FilterType >> 7) | (MessageNumber << 16));
+
+    /* Calculate trigger address */
+    TriggerAddress = (uint32_t *)(hfdcan->msgRam.TTMemorySA + (sTriggerConfig->TriggerIndex * 4U * 2U));
+
+    /* Write trigger element to the message RAM */
+    *TriggerAddress = TriggerElementW1;
+    TriggerAddress++;
+    *TriggerAddress = TriggerElementW2;
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Schedule global time adjustment for the next reference message.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  TimePreset time preset value.
+  *         This parameter must be a number between:
+  *           - 0x0000 and 0x7FFF, Next_Master_Ref_Mark = Current_Master_Ref_Mark + TimePreset
+  *           or
+  *           - 0x8001 and 0xFFFF, Next_Master_Ref_Mark = Current_Master_Ref_Mark - (0x10000 - TimePreset)
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_SetGlobalTime(FDCAN_HandleTypeDef *hfdcan, uint32_t TimePreset)
+{
+  uint32_t Counter = 0U;
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+  assert_param(IS_FDCAN_TT_TIME_PRESET(TimePreset));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    /* Check that the external clock synchronization is enabled */
+    if ((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_EECS) != FDCAN_TTOCF_EECS)
+    {
+      /* Update error code */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
+
+      return HAL_ERROR;
+    }
+
+    /* Check that no global time preset is pending */
+    if ((hfdcan->ttcan->TTOST & FDCAN_TTOST_WGTD) == FDCAN_TTOST_WGTD)
+    {
+      /* Update error code */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PENDING;
+
+      return HAL_ERROR;
+    }
+
+    /* Configure time preset */
+    MODIFY_REG(hfdcan->ttcan->TTGTP, FDCAN_TTGTP_TP, (TimePreset << FDCAN_TTGTP_TP_Pos));
+
+    /* Wait until the LCKC bit into TTOCN register is reset */
+    while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
+    {
+      /* Check for the Timeout */
+      if (Counter > FDCAN_TIMEOUT_COUNT)
+      {
+        /* Update error code */
+        hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+        /* Change FDCAN state */
+        hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+        return HAL_ERROR;
+      }
+
+      /* Increment counter */
+      Counter++;
+    }
+
+    /* Schedule time preset to take effect by the next reference message */
+    SET_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_SGT);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Schedule TUR numerator update for the next reference message.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  NewTURNumerator new value of the TUR numerator.
+  *         This parameter must be a number between 0x10000 and 0x1FFFF.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_SetClockSynchronization(FDCAN_HandleTypeDef *hfdcan, uint32_t NewTURNumerator)
+{
+  uint32_t Counter = 0U;
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+  assert_param(IS_FDCAN_TT_TUR_NUMERATOR(NewTURNumerator));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    /* Check that the external clock synchronization is enabled */
+    if ((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_EECS) != FDCAN_TTOCF_EECS)
+    {
+      /* Update error code */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
+
+      return HAL_ERROR;
+    }
+
+    /* Check that no external clock synchronization is pending */
+    if ((hfdcan->ttcan->TTOST & FDCAN_TTOST_WECS) == FDCAN_TTOST_WECS)
+    {
+      /* Update error code */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PENDING;
+
+      return HAL_ERROR;
+    }
+
+    /* Configure new TUR numerator */
+    MODIFY_REG(hfdcan->ttcan->TURCF, FDCAN_TURCF_NCL, (NewTURNumerator - 0x10000U));
+
+    /* Wait until the LCKC bit into TTOCN register is reset */
+    while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
+    {
+      /* Check for the Timeout */
+      if (Counter > FDCAN_TIMEOUT_COUNT)
+      {
+        /* Update error code */
+        hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+        /* Change FDCAN state */
+        hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+        return HAL_ERROR;
+      }
+
+      /* Increment counter */
+      Counter++;
+    }
+
+    /* Schedule TUR numerator update by the next reference message */
+    SET_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_ECS);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Configure stop watch source and polarity.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  Source stop watch source.
+  *         This parameter can be a value of @arg FDCAN_TT_stop_watch_source.
+  * @param  Polarity stop watch polarity.
+  *         This parameter can be a value of @arg FDCAN_TT_stop_watch_polarity.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_ConfigStopWatch(FDCAN_HandleTypeDef *hfdcan, uint32_t Source, uint32_t Polarity)
+{
+  uint32_t Counter = 0U;
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+  assert_param(IS_FDCAN_TT_STOP_WATCH_SOURCE(Source));
+  assert_param(IS_FDCAN_TT_STOP_WATCH_POLARITY(Polarity));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    /* Wait until the LCKC bit into TTOCN register is reset */
+    while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
+    {
+      /* Check for the Timeout */
+      if (Counter > FDCAN_TIMEOUT_COUNT)
+      {
+        /* Update error code */
+        hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+        /* Change FDCAN state */
+        hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+        return HAL_ERROR;
+      }
+
+      /* Increment counter */
+      Counter++;
+    }
+
+    /* Select stop watch source and polarity */
+    MODIFY_REG(hfdcan->ttcan->TTOCN, (FDCAN_TTOCN_SWS | FDCAN_TTOCN_SWP), (Source | Polarity));
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Configure register time mark pulse generation.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  TimeMarkSource time mark source.
+  *         This parameter can be a value of @arg FDCAN_TT_time_mark_source.
+  * @param  TimeMarkValue time mark value (reference).
+  *         This parameter must be a number between 0 and 0xFFFF.
+  * @param  RepeatFactor repeat factor of the cycle for which the time mark is valid.
+  *         This parameter can be a value of @arg FDCAN_TT_Repeat_Factor.
+  * @param  StartCycle index of the first cycle in which the time mark becomes valid.
+  *         This parameter is ignored if RepeatFactor is set to FDCAN_TT_REPEAT_EVERY_CYCLE.
+  *         This parameter must be a number between 0 and RepeatFactor.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_ConfigRegisterTimeMark(FDCAN_HandleTypeDef *hfdcan,
+                                                      uint32_t TimeMarkSource, uint32_t TimeMarkValue,
+                                                      uint32_t RepeatFactor, uint32_t StartCycle)
+{
+  uint32_t Counter = 0U;
+  uint32_t CycleCode;
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+  assert_param(IS_FDCAN_TT_REGISTER_TIME_MARK_SOURCE(TimeMarkSource));
+  assert_param(IS_FDCAN_MAX_VALUE(TimeMarkValue, 0xFFFFU));
+  assert_param(IS_FDCAN_TT_REPEAT_FACTOR(RepeatFactor));
+  if (RepeatFactor != FDCAN_TT_REPEAT_EVERY_CYCLE)
+  {
+    assert_param(IS_FDCAN_MAX_VALUE(StartCycle, (RepeatFactor - 1U)));
+  }
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    /* Wait until the LCKC bit into TTOCN register is reset */
+    while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
+    {
+      /* Check for the Timeout */
+      if (Counter > FDCAN_TIMEOUT_COUNT)
+      {
+        /* Update error code */
+        hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+        /* Change FDCAN state */
+        hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+        return HAL_ERROR;
+      }
+
+      /* Increment counter */
+      Counter++;
+    }
+
+    /* Disable the time mark compare function */
+    CLEAR_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_TMC);
+
+    if (TimeMarkSource != FDCAN_TT_REG_TIMEMARK_DIABLED)
+    {
+      /* Calculate cycle code */
+      if (RepeatFactor == FDCAN_TT_REPEAT_EVERY_CYCLE)
+      {
+        CycleCode = FDCAN_TT_REPEAT_EVERY_CYCLE;
+      }
+      else /* RepeatFactor != FDCAN_TT_REPEAT_EVERY_CYCLE */
+      {
+        CycleCode = RepeatFactor + StartCycle;
+      }
+
+      Counter = 0U;
+
+      /* Wait until the LCKM bit into TTTMK register is reset */
+      while ((hfdcan->ttcan->TTTMK & FDCAN_TTTMK_LCKM) != 0U)
+      {
+        /* Check for the Timeout */
+        if (Counter > FDCAN_TIMEOUT_COUNT)
+        {
+          /* Update error code */
+          hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+          /* Change FDCAN state */
+          hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+          return HAL_ERROR;
+        }
+
+        /* Increment counter */
+        Counter++;
+      }
+
+      /* Configure time mark value and cycle code */
+      hfdcan->ttcan->TTTMK = ((TimeMarkValue << FDCAN_TTTMK_TM_Pos) | (CycleCode << FDCAN_TTTMK_TICC_Pos));
+
+      Counter = 0U;
+
+      /* Wait until the LCKC bit into TTOCN register is reset */
+      while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
+      {
+        /* Check for the Timeout */
+        if (Counter > FDCAN_TIMEOUT_COUNT)
+        {
+          /* Update error code */
+          hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+          /* Change FDCAN state */
+          hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+          return HAL_ERROR;
+        }
+
+        /* Increment counter */
+        Counter++;
+      }
+
+      /* Update the register time mark compare source */
+      MODIFY_REG(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_TMC, TimeMarkSource);
+    }
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Enable register time mark pulse generation.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_EnableRegisterTimeMarkPulse(FDCAN_HandleTypeDef *hfdcan)
+{
+  uint32_t Counter = 0U;
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    /* Wait until the LCKC bit into TTOCN register is reset */
+    while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
+    {
+      /* Check for the Timeout */
+      if (Counter > FDCAN_TIMEOUT_COUNT)
+      {
+        /* Update error code */
+        hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+        /* Change FDCAN state */
+        hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+        return HAL_ERROR;
+      }
+
+      /* Increment counter */
+      Counter++;
+    }
+
+    /* Enable Register Time Mark Interrupt output on fdcan1_rtp */
+    SET_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_RTIE);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Disable register time mark pulse generation.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_DisableRegisterTimeMarkPulse(FDCAN_HandleTypeDef *hfdcan)
+{
+  uint32_t Counter = 0U;
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    /* Wait until the LCKC bit into TTOCN register is reset */
+    while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
+    {
+      /* Check for the Timeout */
+      if (Counter > FDCAN_TIMEOUT_COUNT)
+      {
+        /* Update error code */
+        hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+        /* Change FDCAN state */
+        hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+        return HAL_ERROR;
+      }
+
+      /* Increment counter */
+      Counter++;
+    }
+
+    /* Disable Register Time Mark Interrupt output on fdcan1_rtp */
+    CLEAR_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_RTIE);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Enable trigger time mark pulse generation.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_EnableTriggerTimeMarkPulse(FDCAN_HandleTypeDef *hfdcan)
+{
+  uint32_t Counter = 0U;
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    if ((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_OM) != FDCAN_TT_COMMUNICATION_LEVEL0)
+    {
+      /* Wait until the LCKC bit into TTOCN register is reset */
+      while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
+      {
+        /* Check for the Timeout */
+        if (Counter > FDCAN_TIMEOUT_COUNT)
+        {
+          /* Update error code */
+          hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+          /* Change FDCAN state */
+          hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+          return HAL_ERROR;
+        }
+
+        /* Increment counter */
+        Counter++;
+      }
+
+      /* Enable Trigger Time Mark Interrupt output on fdcan1_tmp */
+      SET_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_TTIE);
+
+      /* Return function status */
+      return HAL_OK;
+    }
+    else
+    {
+      /* Update error code.
+         Feature not supported for TT Level 0 */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
+
+      return HAL_ERROR;
+    }
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Disable trigger time mark pulse generation.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_DisableTriggerTimeMarkPulse(FDCAN_HandleTypeDef *hfdcan)
+{
+  uint32_t Counter = 0U;
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    if ((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_OM) != FDCAN_TT_COMMUNICATION_LEVEL0)
+    {
+      /* Wait until the LCKC bit into TTOCN register is reset */
+      while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
+      {
+        /* Check for the Timeout */
+        if (Counter > FDCAN_TIMEOUT_COUNT)
+        {
+          /* Update error code */
+          hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+          /* Change FDCAN state */
+          hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+          return HAL_ERROR;
+        }
+
+        /* Increment counter */
+        Counter++;
+      }
+
+      /* Disable Trigger Time Mark Interrupt output on fdcan1_rtp */
+      CLEAR_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_TTIE);
+
+      /* Return function status */
+      return HAL_OK;
+    }
+    else
+    {
+      /* Update error code.
+         Feature not supported for TT Level 0 */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
+
+      return HAL_ERROR;
+    }
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Enable gap control by input pin fdcan1_evt.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_EnableHardwareGapControl(FDCAN_HandleTypeDef *hfdcan)
+{
+  uint32_t Counter = 0U;
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    if ((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_OM) != FDCAN_TT_COMMUNICATION_LEVEL0)
+    {
+      /* Wait until the LCKC bit into TTOCN register is reset */
+      while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
+      {
+        /* Check for the Timeout */
+        if (Counter > FDCAN_TIMEOUT_COUNT)
+        {
+          /* Update error code */
+          hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+          /* Change FDCAN state */
+          hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+          return HAL_ERROR;
+        }
+
+        /* Increment counter */
+        Counter++;
+      }
+
+      /* Enable gap control by pin fdcan1_evt */
+      SET_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_GCS);
+
+      /* Return function status */
+      return HAL_OK;
+    }
+    else
+    {
+      /* Update error code.
+         Feature not supported for TT Level 0 */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
+
+      return HAL_ERROR;
+    }
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Disable gap control by input pin fdcan1_evt.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_DisableHardwareGapControl(FDCAN_HandleTypeDef *hfdcan)
+{
+  uint32_t Counter = 0U;
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    if ((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_OM) != FDCAN_TT_COMMUNICATION_LEVEL0)
+    {
+      /* Wait until the LCKC bit into TTOCN register is reset */
+      while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
+      {
+        /* Check for the Timeout */
+        if (Counter > FDCAN_TIMEOUT_COUNT)
+        {
+          /* Update error code */
+          hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+          /* Change FDCAN state */
+          hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+          return HAL_ERROR;
+        }
+
+        /* Increment counter */
+        Counter++;
+      }
+
+      /* Disable gap control by pin fdcan1_evt */
+      CLEAR_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_GCS);
+
+      /* Return function status */
+      return HAL_OK;
+    }
+    else
+    {
+      /* Update error code.
+         Feature not supported for TT Level 0 */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
+
+      return HAL_ERROR;
+    }
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Enable gap control (finish only) by register time mark interrupt.
+  *         The next register time mark interrupt (TTIR.RTMI = "1") will finish
+  *         the Gap and start the reference message.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_EnableTimeMarkGapControl(FDCAN_HandleTypeDef *hfdcan)
+{
+  uint32_t Counter = 0U;
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    if ((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_OM) != FDCAN_TT_COMMUNICATION_LEVEL0)
+    {
+      /* Wait until the LCKC bit into TTOCN register is reset */
+      while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
+      {
+        /* Check for the Timeout */
+        if (Counter > FDCAN_TIMEOUT_COUNT)
+        {
+          /* Update error code */
+          hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+          /* Change FDCAN state */
+          hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+          return HAL_ERROR;
+        }
+
+        /* Increment counter */
+        Counter++;
+      }
+
+      /* Enable gap control by register time mark interrupt */
+      SET_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_TMG);
+
+      /* Return function status */
+      return HAL_OK;
+    }
+    else
+    {
+      /* Update error code.
+         Feature not supported for TT Level 0 */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
+
+      return HAL_ERROR;
+    }
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Disable gap control by register time mark interrupt.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_DisableTimeMarkGapControl(FDCAN_HandleTypeDef *hfdcan)
+{
+  uint32_t Counter = 0U;
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    if ((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_OM) != FDCAN_TT_COMMUNICATION_LEVEL0)
+    {
+      /* Wait until the LCKC bit into TTOCN register is reset */
+      while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
+      {
+        /* Check for the Timeout */
+        if (Counter > FDCAN_TIMEOUT_COUNT)
+        {
+          /* Update error code */
+          hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+          /* Change FDCAN state */
+          hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+          return HAL_ERROR;
+        }
+
+        /* Increment counter */
+        Counter++;
+      }
+
+      /* Disable gap control by register time mark interrupt */
+      CLEAR_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_TMG);
+
+      /* Return function status */
+      return HAL_OK;
+    }
+    else
+    {
+      /* Update error code.
+         Feature not supported for TT Level 0 */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
+
+      return HAL_ERROR;
+    }
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Transmit next reference message with Next_is_Gap = "1".
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_SetNextIsGap(FDCAN_HandleTypeDef *hfdcan)
+{
+  uint32_t Counter = 0U;
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    /* Check that the node is configured for external event-synchronized TT operation */
+    if ((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_GEN) != FDCAN_TTOCF_GEN)
+    {
+      /* Update error code */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
+
+      return HAL_ERROR;
+    }
+
+    if ((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_OM) != FDCAN_TT_COMMUNICATION_LEVEL0)
+    {
+      /* Wait until the LCKC bit into TTOCN register is reset */
+      while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
+      {
+        /* Check for the Timeout */
+        if (Counter > FDCAN_TIMEOUT_COUNT)
+        {
+          /* Update error code */
+          hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+          /* Change FDCAN state */
+          hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+          return HAL_ERROR;
+        }
+
+        /* Increment counter */
+        Counter++;
+      }
+
+      /* Set Next is Gap */
+      SET_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_NIG);
+
+      /* Return function status */
+      return HAL_OK;
+    }
+    else
+    {
+      /* Update error code.
+         Feature not supported for TT Level 0 */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
+
+      return HAL_ERROR;
+    }
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Finish a Gap by requesting start of reference message.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_SetEndOfGap(FDCAN_HandleTypeDef *hfdcan)
+{
+  uint32_t Counter = 0U;
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    /* Check that the node is configured for external event-synchronized TT operation */
+    if ((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_GEN) != FDCAN_TTOCF_GEN)
+    {
+      /* Update error code */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
+
+      return HAL_ERROR;
+    }
+
+    if ((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_OM) != FDCAN_TT_COMMUNICATION_LEVEL0)
+    {
+      /* Wait until the LCKC bit into TTOCN register is reset */
+      while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
+      {
+        /* Check for the Timeout */
+        if (Counter > FDCAN_TIMEOUT_COUNT)
+        {
+          /* Update error code */
+          hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+          /* Change FDCAN state */
+          hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+          return HAL_ERROR;
+        }
+
+        /* Increment counter */
+        Counter++;
+      }
+
+      /* Set Finish Gap */
+      SET_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_FGP);
+
+      /* Return function status */
+      return HAL_OK;
+    }
+    else
+    {
+      /* Update error code.
+         Feature not supported for TT Level 0 */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
+
+      return HAL_ERROR;
+    }
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Configure target phase used for external synchronization by event
+  *         trigger input pin fdcan1_evt.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  TargetPhase defines target value of cycle time when a rising edge
+  *         of fdcan1_evt is expected.
+  *         This parameter must be a number between 0 and 0xFFFF.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_ConfigExternalSyncPhase(FDCAN_HandleTypeDef *hfdcan, uint32_t TargetPhase)
+{
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+  assert_param(IS_FDCAN_MAX_VALUE(TargetPhase, 0xFFFFU));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    /* Check that no external schedule synchronization is pending */
+    if ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_ESCN) == FDCAN_TTOCN_ESCN)
+    {
+      /* Update error code */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PENDING;
+
+      return HAL_ERROR;
+    }
+
+    /* Configure cycle time target phase */
+    MODIFY_REG(hfdcan->ttcan->TTGTP, FDCAN_TTGTP_CTP, (TargetPhase << FDCAN_TTGTP_CTP_Pos));
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Synchronize the phase of the FDCAN schedule to an external schedule
+  *         using event trigger input pin fdcan1_evt.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_EnableExternalSynchronization(FDCAN_HandleTypeDef *hfdcan)
+{
+  uint32_t Counter = 0U;
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    /* Wait until the LCKC bit into TTOCN register is reset */
+    while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
+    {
+      /* Check for the Timeout */
+      if (Counter > FDCAN_TIMEOUT_COUNT)
+      {
+        /* Update error code */
+        hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+        /* Change FDCAN state */
+        hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+        return HAL_ERROR;
+      }
+
+      /* Increment counter */
+      Counter++;
+    }
+
+    /* Enable external synchronization */
+    SET_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_ESCN);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Disable external schedule synchronization.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_DisableExternalSynchronization(FDCAN_HandleTypeDef *hfdcan)
+{
+  uint32_t Counter = 0U;
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    /* Wait until the LCKC bit into TTOCN register is reset */
+    while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
+    {
+      /* Check for the Timeout */
+      if (Counter > FDCAN_TIMEOUT_COUNT)
+      {
+        /* Update error code */
+        hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+        /* Change FDCAN state */
+        hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+        return HAL_ERROR;
+      }
+
+      /* Increment counter */
+      Counter++;
+    }
+
+    /* Disable external synchronization */
+    CLEAR_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_ESCN);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Get TT operation status.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  TTOpStatus pointer to an FDCAN_TTOperationStatusTypeDef structure.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_GetOperationStatus(FDCAN_HandleTypeDef *hfdcan, FDCAN_TTOperationStatusTypeDef *TTOpStatus)
+{
+  uint32_t TTStatusReg;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+
+  /* Read the TT operation status register */
+  TTStatusReg = READ_REG(hfdcan->ttcan->TTOST);
+
+  /* Fill the TT operation status structure */
+  TTOpStatus->ErrorLevel = (TTStatusReg & FDCAN_TTOST_EL);
+  TTOpStatus->MasterState = (TTStatusReg & FDCAN_TTOST_MS);
+  TTOpStatus->SyncState = (TTStatusReg & FDCAN_TTOST_SYS);
+  TTOpStatus->GTimeQuality = ((TTStatusReg & FDCAN_TTOST_QGTP) >> FDCAN_TTOST_QGTP_Pos);
+  TTOpStatus->ClockQuality = ((TTStatusReg & FDCAN_TTOST_QCS) >> FDCAN_TTOST_QCS_Pos);
+  TTOpStatus->RefTrigOffset = ((TTStatusReg & FDCAN_TTOST_RTO) >> FDCAN_TTOST_RTO_Pos);
+  TTOpStatus->GTimeDiscPending = ((TTStatusReg & FDCAN_TTOST_WGTD) >> FDCAN_TTOST_WGTD_Pos);
+  TTOpStatus->GapFinished = ((TTStatusReg & FDCAN_TTOST_GFI) >> FDCAN_TTOST_GFI_Pos);
+  TTOpStatus->MasterPriority = ((TTStatusReg & FDCAN_TTOST_TMP) >> FDCAN_TTOST_TMP_Pos);
+  TTOpStatus->GapStarted = ((TTStatusReg & FDCAN_TTOST_GSI) >> FDCAN_TTOST_GSI_Pos);
+  TTOpStatus->WaitForEvt = ((TTStatusReg & FDCAN_TTOST_WFE) >> FDCAN_TTOST_WFE_Pos);
+  TTOpStatus->AppWdgEvt = ((TTStatusReg & FDCAN_TTOST_AWE) >> FDCAN_TTOST_AWE_Pos);
+  TTOpStatus->ECSPending = ((TTStatusReg & FDCAN_TTOST_WECS) >> FDCAN_TTOST_WECS_Pos);
+  TTOpStatus->PhaseLock = ((TTStatusReg & FDCAN_TTOST_SPL) >> FDCAN_TTOST_SPL_Pos);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Exported_Functions_Group5 Interrupts management
+ *  @brief    Interrupts management
+ *
+@verbatim
+  ==============================================================================
+                       ##### Interrupts management #####
+  ==============================================================================
+    [..]  This section provides functions allowing to:
+      (+) HAL_FDCAN_ConfigInterruptLines      : Assign interrupts to either Interrupt line 0 or 1
+      (+) HAL_FDCAN_TT_ConfigInterruptLines   : Assign TT interrupts to either Interrupt line 0 or 1
+      (+) HAL_FDCAN_ActivateNotification      : Enable interrupts
+      (+) HAL_FDCAN_DeactivateNotification    : Disable interrupts
+      (+) HAL_FDCAN_TT_ActivateNotification   : Enable TT interrupts
+      (+) HAL_FDCAN_TT_DeactivateNotification : Disable TT interrupts
+      (+) HAL_FDCAN_IRQHandler                : Handles FDCAN interrupt request
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Assign interrupts to either Interrupt line 0 or 1.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  ITList indicates which interrupts will be assigned to the selected interrupt line.
+  *         This parameter can be any combination of @arg FDCAN_Interrupts.
+  * @param  InterruptLine Interrupt line.
+  *         This parameter can be a value of @arg FDCAN_Interrupt_Line.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_ConfigInterruptLines(FDCAN_HandleTypeDef *hfdcan, uint32_t ITList, uint32_t InterruptLine)
+{
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_IT(ITList));
+  assert_param(IS_FDCAN_IT_LINE(InterruptLine));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    /* Assign list of interrupts to the selected line */
+    if (InterruptLine == FDCAN_INTERRUPT_LINE0)
+    {
+      CLEAR_BIT(hfdcan->Instance->ILS, ITList);
+    }
+    else /* InterruptLine == FDCAN_INTERRUPT_LINE1 */
+    {
+      SET_BIT(hfdcan->Instance->ILS, ITList);
+    }
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Assign TT interrupts to either Interrupt line 0 or 1.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  TTITList indicates which interrupts will be assigned to the selected interrupt line.
+  *         This parameter can be any combination of @arg FDCAN_TTInterrupts.
+  * @param  InterruptLine Interrupt line.
+  *         This parameter can be a value of @arg FDCAN_Interrupt_Line.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_ConfigInterruptLines(FDCAN_HandleTypeDef *hfdcan, uint32_t TTITList, uint32_t InterruptLine)
+{
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+  assert_param(IS_FDCAN_TT_IT(TTITList));
+  assert_param(IS_FDCAN_IT_LINE(InterruptLine));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    /* Assign list of interrupts to the selected line */
+    if (InterruptLine == FDCAN_INTERRUPT_LINE0)
+    {
+      CLEAR_BIT(hfdcan->ttcan->TTILS, TTITList);
+    }
+    else /* InterruptLine == FDCAN_INTERRUPT_LINE1 */
+    {
+      SET_BIT(hfdcan->ttcan->TTILS, TTITList);
+    }
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Enable interrupts.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  ActiveITs indicates which interrupts will be enabled.
+  *         This parameter can be any combination of @arg FDCAN_Interrupts.
+  * @param  BufferIndexes Tx Buffer Indexes.
+  *         This parameter can be any combination of @arg FDCAN_Tx_location.
+  *         This parameter is ignored if ActiveITs does not include one of the following:
+  *           - FDCAN_IT_TX_COMPLETE
+  *           - FDCAN_IT_TX_ABORT_COMPLETE
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_ActivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t ActiveITs, uint32_t BufferIndexes)
+{
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_IT(ActiveITs));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    /* Enable Interrupt lines */
+    if ((ActiveITs & hfdcan->Instance->ILS) == 0U)
+    {
+      /* Enable Interrupt line 0 */
+      SET_BIT(hfdcan->Instance->ILE, FDCAN_INTERRUPT_LINE0);
+    }
+    else if ((ActiveITs & hfdcan->Instance->ILS) == ActiveITs)
+    {
+      /* Enable Interrupt line 1 */
+      SET_BIT(hfdcan->Instance->ILE, FDCAN_INTERRUPT_LINE1);
+    }
+    else
+    {
+      /* Enable Interrupt lines 0 and 1 */
+      hfdcan->Instance->ILE = (FDCAN_INTERRUPT_LINE0 | FDCAN_INTERRUPT_LINE1);
+    }
+
+    if ((ActiveITs & FDCAN_IT_TX_COMPLETE) != 0U)
+    {
+      /* Enable Tx Buffer Transmission Interrupt to set TC flag in IR register,
+         but interrupt will only occur if TC is enabled in IE register */
+      SET_BIT(hfdcan->Instance->TXBTIE, BufferIndexes);
+    }
+
+    if ((ActiveITs & FDCAN_IT_TX_ABORT_COMPLETE) != 0U)
+    {
+      /* Enable Tx Buffer Cancellation Finished Interrupt to set TCF flag in IR register,
+         but interrupt will only occur if TCF is enabled in IE register */
+      SET_BIT(hfdcan->Instance->TXBCIE, BufferIndexes);
+    }
+
+    /* Enable the selected interrupts */
+    __HAL_FDCAN_ENABLE_IT(hfdcan, ActiveITs);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Disable interrupts.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  InactiveITs indicates which interrupts will be disabled.
+  *         This parameter can be any combination of @arg FDCAN_Interrupts.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_DeactivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t InactiveITs)
+{
+  uint32_t ITLineSelection;
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_IT(InactiveITs));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    /* Disable the selected interrupts */
+    __HAL_FDCAN_DISABLE_IT(hfdcan, InactiveITs);
+
+    if ((InactiveITs & FDCAN_IT_TX_COMPLETE) != 0U)
+    {
+      /* Disable Tx Buffer Transmission Interrupts */
+      CLEAR_REG(hfdcan->Instance->TXBTIE);
+    }
+
+    if ((InactiveITs & FDCAN_IT_TX_ABORT_COMPLETE) != 0U)
+    {
+      /* Disable Tx Buffer Cancellation Finished Interrupt */
+      CLEAR_REG(hfdcan->Instance->TXBCIE);
+    }
+
+    ITLineSelection = hfdcan->Instance->ILS;
+
+    if ((hfdcan->Instance->IE | ITLineSelection) == ITLineSelection)
+    {
+      /* Disable Interrupt line 0 */
+      CLEAR_BIT(hfdcan->Instance->ILE, FDCAN_INTERRUPT_LINE0);
+    }
+
+    if ((hfdcan->Instance->IE & ITLineSelection) == 0U)
+    {
+      /* Disable Interrupt line 1 */
+      CLEAR_BIT(hfdcan->Instance->ILE, FDCAN_INTERRUPT_LINE1);
+    }
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Enable TT interrupts.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  ActiveTTITs indicates which TT interrupts will be enabled.
+  *         This parameter can be any combination of @arg FDCAN_TTInterrupts.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_ActivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t ActiveTTITs)
+{
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+  assert_param(IS_FDCAN_TT_IT(ActiveTTITs));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    /* Enable Interrupt lines */
+    if ((ActiveTTITs & hfdcan->ttcan->TTILS) == 0U)
+    {
+      /* Enable Interrupt line 0 */
+      SET_BIT(hfdcan->Instance->ILE, FDCAN_INTERRUPT_LINE0);
+    }
+    else if ((ActiveTTITs & hfdcan->ttcan->TTILS) == ActiveTTITs)
+    {
+      /* Enable Interrupt line 1 */
+      SET_BIT(hfdcan->Instance->ILE, FDCAN_INTERRUPT_LINE1);
+    }
+    else
+    {
+      /* Enable Interrupt lines 0 and 1 */
+      hfdcan->Instance->ILE = (FDCAN_INTERRUPT_LINE0 | FDCAN_INTERRUPT_LINE1);
+    }
+
+    /* Enable the selected TT interrupts */
+    __HAL_FDCAN_TT_ENABLE_IT(hfdcan, ActiveTTITs);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Disable TT interrupts.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  InactiveTTITs indicates which TT interrupts will be disabled.
+  *         This parameter can be any combination of @arg FDCAN_TTInterrupts.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_DeactivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t InactiveTTITs)
+{
+  uint32_t ITLineSelection;
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+  assert_param(IS_FDCAN_TT_IT(InactiveTTITs));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    /* Disable the selected TT interrupts */
+    __HAL_FDCAN_TT_DISABLE_IT(hfdcan, InactiveTTITs);
+
+    ITLineSelection = hfdcan->ttcan->TTILS;
+
+    if ((hfdcan->ttcan->TTIE | ITLineSelection) == ITLineSelection)
+    {
+      /* Disable Interrupt line 0 */
+      CLEAR_BIT(hfdcan->Instance->ILE, FDCAN_INTERRUPT_LINE0);
+    }
+
+    if ((hfdcan->ttcan->TTIE & ITLineSelection) == 0U)
+    {
+      /* Disable Interrupt line 1 */
+      CLEAR_BIT(hfdcan->Instance->ILE, FDCAN_INTERRUPT_LINE1);
+    }
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Handles FDCAN interrupt request.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+void HAL_FDCAN_IRQHandler(FDCAN_HandleTypeDef *hfdcan)
+{
+  uint32_t ClkCalibrationITs;
+  uint32_t TxEventFifoITs;
+  uint32_t RxFifo0ITs;
+  uint32_t RxFifo1ITs;
+  uint32_t Errors;
+  uint32_t ErrorStatusITs;
+  uint32_t TransmittedBuffers;
+  uint32_t AbortedBuffers;
+  uint32_t TTSchedSyncITs;
+  uint32_t TTTimeMarkITs;
+  uint32_t TTGlobTimeITs;
+  uint32_t TTDistErrors;
+  uint32_t TTFatalErrors;
+  uint32_t SWTime;
+  uint32_t SWCycleCount;
+  uint32_t itsourceIE;
+  uint32_t itsourceTTIE;
+  uint32_t itflagIR;
+  uint32_t itflagTTIR;
+
+  ClkCalibrationITs = (FDCAN_CCU->IR << 30);
+  ClkCalibrationITs &= (FDCAN_CCU->IE << 30);
+  TxEventFifoITs = hfdcan->Instance->IR & FDCAN_TX_EVENT_FIFO_MASK;
+  TxEventFifoITs &= hfdcan->Instance->IE;
+  RxFifo0ITs = hfdcan->Instance->IR & FDCAN_RX_FIFO0_MASK;
+  RxFifo0ITs &= hfdcan->Instance->IE;
+  RxFifo1ITs = hfdcan->Instance->IR & FDCAN_RX_FIFO1_MASK;
+  RxFifo1ITs &= hfdcan->Instance->IE;
+  Errors = hfdcan->Instance->IR & FDCAN_ERROR_MASK;
+  Errors &= hfdcan->Instance->IE;
+  ErrorStatusITs = hfdcan->Instance->IR & FDCAN_ERROR_STATUS_MASK;
+  ErrorStatusITs &= hfdcan->Instance->IE;
+  itsourceIE = hfdcan->Instance->IE;
+  itflagIR = hfdcan->Instance->IR;
+
+  /* High Priority Message interrupt management *******************************/
+  if (FDCAN_CHECK_IT_SOURCE(itsourceIE, FDCAN_IT_RX_HIGH_PRIORITY_MSG) != RESET)
+  {
+    if (FDCAN_CHECK_FLAG(itflagIR, FDCAN_FLAG_RX_HIGH_PRIORITY_MSG) != RESET)
+    {
+      /* Clear the High Priority Message flag */
+      __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_RX_HIGH_PRIORITY_MSG);
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+      /* Call registered callback*/
+      hfdcan->HighPriorityMessageCallback(hfdcan);
+#else
+      /* High Priority Message Callback */
+      HAL_FDCAN_HighPriorityMessageCallback(hfdcan);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+    }
+  }
+
+  /* Transmission Abort interrupt management **********************************/
+  if (FDCAN_CHECK_IT_SOURCE(itsourceIE, FDCAN_IT_TX_ABORT_COMPLETE) != RESET)
+  {
+    if (FDCAN_CHECK_FLAG(itflagIR, FDCAN_FLAG_TX_ABORT_COMPLETE) != RESET)
+    {
+      /* List of aborted monitored buffers */
+      AbortedBuffers = hfdcan->Instance->TXBCF;
+      AbortedBuffers &= hfdcan->Instance->TXBCIE;
+
+      /* Clear the Transmission Cancellation flag */
+      __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TX_ABORT_COMPLETE);
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+      /* Call registered callback*/
+      hfdcan->TxBufferAbortCallback(hfdcan, AbortedBuffers);
+#else
+      /* Transmission Cancellation Callback */
+      HAL_FDCAN_TxBufferAbortCallback(hfdcan, AbortedBuffers);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+    }
+  }
+
+  /* Clock calibration unit interrupts management *****************************/
+  if (ClkCalibrationITs != 0U)
+  {
+    /* Clear the Clock Calibration flags */
+    __HAL_FDCAN_CLEAR_FLAG(hfdcan, ClkCalibrationITs);
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+    /* Call registered callback*/
+    hfdcan->ClockCalibrationCallback(hfdcan, ClkCalibrationITs);
+#else
+    /* Clock Calibration Callback */
+    HAL_FDCAN_ClockCalibrationCallback(hfdcan, ClkCalibrationITs);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+  }
+
+  /* Tx event FIFO interrupts management **************************************/
+  if (TxEventFifoITs != 0U)
+  {
+    /* Clear the Tx Event FIFO flags */
+    __HAL_FDCAN_CLEAR_FLAG(hfdcan, TxEventFifoITs);
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+    /* Call registered callback*/
+    hfdcan->TxEventFifoCallback(hfdcan, TxEventFifoITs);
+#else
+    /* Tx Event FIFO Callback */
+    HAL_FDCAN_TxEventFifoCallback(hfdcan, TxEventFifoITs);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+  }
+
+  /* Rx FIFO 0 interrupts management ******************************************/
+  if (RxFifo0ITs != 0U)
+  {
+    /* Clear the Rx FIFO 0 flags */
+    __HAL_FDCAN_CLEAR_FLAG(hfdcan, RxFifo0ITs);
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+    /* Call registered callback*/
+    hfdcan->RxFifo0Callback(hfdcan, RxFifo0ITs);
+#else
+    /* Rx FIFO 0 Callback */
+    HAL_FDCAN_RxFifo0Callback(hfdcan, RxFifo0ITs);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+  }
+
+  /* Rx FIFO 1 interrupts management ******************************************/
+  if (RxFifo1ITs != 0U)
+  {
+    /* Clear the Rx FIFO 1 flags */
+    __HAL_FDCAN_CLEAR_FLAG(hfdcan, RxFifo1ITs);
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+    /* Call registered callback*/
+    hfdcan->RxFifo1Callback(hfdcan, RxFifo1ITs);
+#else
+    /* Rx FIFO 1 Callback */
+    HAL_FDCAN_RxFifo1Callback(hfdcan, RxFifo1ITs);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+  }
+
+  /* Tx FIFO empty interrupt management ***************************************/
+  if (FDCAN_CHECK_IT_SOURCE(itsourceIE, FDCAN_IT_TX_FIFO_EMPTY) != RESET)
+  {
+    if (FDCAN_CHECK_FLAG(itflagIR, FDCAN_FLAG_TX_FIFO_EMPTY) != RESET)
+    {
+      /* Clear the Tx FIFO empty flag */
+      __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TX_FIFO_EMPTY);
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+      /* Call registered callback*/
+      hfdcan->TxFifoEmptyCallback(hfdcan);
+#else
+      /* Tx FIFO empty Callback */
+      HAL_FDCAN_TxFifoEmptyCallback(hfdcan);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+    }
+  }
+
+  /* Transmission Complete interrupt management *******************************/
+  if (FDCAN_CHECK_IT_SOURCE(itsourceIE, FDCAN_IT_TX_COMPLETE) != RESET)
+  {
+    if (FDCAN_CHECK_FLAG(itflagIR, FDCAN_FLAG_TX_COMPLETE) != RESET)
+    {
+      /* List of transmitted monitored buffers */
+      TransmittedBuffers = hfdcan->Instance->TXBTO;
+      TransmittedBuffers &= hfdcan->Instance->TXBTIE;
+
+      /* Clear the Transmission Complete flag */
+      __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TX_COMPLETE);
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+      /* Call registered callback*/
+      hfdcan->TxBufferCompleteCallback(hfdcan, TransmittedBuffers);
+#else
+      /* Transmission Complete Callback */
+      HAL_FDCAN_TxBufferCompleteCallback(hfdcan, TransmittedBuffers);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+    }
+  }
+
+  /* Rx Buffer New Message interrupt management *******************************/
+  if (FDCAN_CHECK_IT_SOURCE(itsourceIE, FDCAN_IT_RX_BUFFER_NEW_MESSAGE) != RESET)
+  {
+    if (FDCAN_CHECK_FLAG(itflagIR, FDCAN_FLAG_RX_BUFFER_NEW_MESSAGE) != RESET)
+    {
+      /* Clear the Rx Buffer New Message flag */
+      __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_RX_BUFFER_NEW_MESSAGE);
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+      /* Call registered callback*/
+      hfdcan->RxBufferNewMessageCallback(hfdcan);
+#else
+      /* Rx Buffer New Message Callback */
+      HAL_FDCAN_RxBufferNewMessageCallback(hfdcan);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+    }
+  }
+
+  /* Timestamp Wraparound interrupt management ********************************/
+  if (FDCAN_CHECK_IT_SOURCE(itsourceIE, FDCAN_IT_TIMESTAMP_WRAPAROUND) != RESET)
+  {
+    if (FDCAN_CHECK_FLAG(itflagIR, FDCAN_FLAG_TIMESTAMP_WRAPAROUND) != RESET)
+    {
+      /* Clear the Timestamp Wraparound flag */
+      __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TIMESTAMP_WRAPAROUND);
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+      /* Call registered callback*/
+      hfdcan->TimestampWraparoundCallback(hfdcan);
+#else
+      /* Timestamp Wraparound Callback */
+      HAL_FDCAN_TimestampWraparoundCallback(hfdcan);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+    }
+  }
+
+  /* Timeout Occurred interrupt management ************************************/
+  if (FDCAN_CHECK_IT_SOURCE(itsourceIE, FDCAN_IT_TIMEOUT_OCCURRED) != RESET)
+  {
+    if (FDCAN_CHECK_FLAG(itflagIR, FDCAN_FLAG_TIMEOUT_OCCURRED) != RESET)
+    {
+      /* Clear the Timeout Occurred flag */
+      __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TIMEOUT_OCCURRED);
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+      /* Call registered callback*/
+      hfdcan->TimeoutOccurredCallback(hfdcan);
+#else
+      /* Timeout Occurred Callback */
+      HAL_FDCAN_TimeoutOccurredCallback(hfdcan);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+    }
+  }
+
+  /* Message RAM access failure interrupt management **************************/
+  if (FDCAN_CHECK_IT_SOURCE(itsourceIE, FDCAN_IT_RAM_ACCESS_FAILURE) != RESET)
+  {
+    if (FDCAN_CHECK_FLAG(itflagIR, FDCAN_FLAG_RAM_ACCESS_FAILURE) != RESET)
+    {
+      /* Clear the Message RAM access failure flag */
+      __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_RAM_ACCESS_FAILURE);
+
+      /* Update error code */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_RAM_ACCESS;
+    }
+  }
+
+  /* Error Status interrupts management ***************************************/
+  if (ErrorStatusITs != 0U)
+  {
+    /* Clear the Error flags */
+    __HAL_FDCAN_CLEAR_FLAG(hfdcan, ErrorStatusITs);
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+    /* Call registered callback*/
+    hfdcan->ErrorStatusCallback(hfdcan, ErrorStatusITs);
+#else
+    /* Error Status Callback */
+    HAL_FDCAN_ErrorStatusCallback(hfdcan, ErrorStatusITs);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+  }
+
+  /* Error interrupts management **********************************************/
+  if (Errors != 0U)
+  {
+    /* Clear the Error flags */
+    __HAL_FDCAN_CLEAR_FLAG(hfdcan, Errors);
+
+    /* Update error code */
+    hfdcan->ErrorCode |= Errors;
+  }
+
+  if (hfdcan->Instance == FDCAN1)
+  {
+    if ((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_OM) != 0U)
+    {
+      TTSchedSyncITs = hfdcan->ttcan->TTIR & FDCAN_TT_SCHEDULE_SYNC_MASK;
+      TTSchedSyncITs &= hfdcan->ttcan->TTIE;
+      TTTimeMarkITs = hfdcan->ttcan->TTIR & FDCAN_TT_TIME_MARK_MASK;
+      TTTimeMarkITs &= hfdcan->ttcan->TTIE;
+      TTGlobTimeITs = hfdcan->ttcan->TTIR & FDCAN_TT_GLOBAL_TIME_MASK;
+      TTGlobTimeITs &= hfdcan->ttcan->TTIE;
+      TTDistErrors = hfdcan->ttcan->TTIR & FDCAN_TT_DISTURBING_ERROR_MASK;
+      TTDistErrors &= hfdcan->ttcan->TTIE;
+      TTFatalErrors = hfdcan->ttcan->TTIR & FDCAN_TT_FATAL_ERROR_MASK;
+      TTFatalErrors &= hfdcan->ttcan->TTIE;
+      itsourceTTIE = hfdcan->ttcan->TTIE;
+      itflagTTIR = hfdcan->ttcan->TTIR;
+
+      /* TT Schedule Synchronization interrupts management **********************/
+      if (TTSchedSyncITs != 0U)
+      {
+        /* Clear the TT Schedule Synchronization flags */
+        __HAL_FDCAN_TT_CLEAR_FLAG(hfdcan, TTSchedSyncITs);
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+        /* Call registered callback*/
+        hfdcan->TT_ScheduleSyncCallback(hfdcan, TTSchedSyncITs);
+#else
+        /* TT Schedule Synchronization Callback */
+        HAL_FDCAN_TT_ScheduleSyncCallback(hfdcan, TTSchedSyncITs);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+      }
+
+      /* TT Time Mark interrupts management *************************************/
+      if (TTTimeMarkITs != 0U)
+      {
+        /* Clear the TT Time Mark flags */
+        __HAL_FDCAN_TT_CLEAR_FLAG(hfdcan, TTTimeMarkITs);
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+        /* Call registered callback*/
+        hfdcan->TT_TimeMarkCallback(hfdcan, TTTimeMarkITs);
+#else
+        /* TT Time Mark Callback */
+        HAL_FDCAN_TT_TimeMarkCallback(hfdcan, TTTimeMarkITs);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+      }
+
+      /* TT Stop Watch interrupt management *************************************/
+      if (FDCAN_CHECK_IT_SOURCE(itsourceTTIE, FDCAN_TT_IT_STOP_WATCH) != RESET)
+      {
+        if (FDCAN_CHECK_FLAG(itflagTTIR, FDCAN_TT_FLAG_STOP_WATCH) != RESET)
+        {
+          /* Retrieve Stop watch Time and Cycle count */
+          SWTime = ((hfdcan->ttcan->TTCPT & FDCAN_TTCPT_SWV) >> FDCAN_TTCPT_SWV_Pos);
+          SWCycleCount = ((hfdcan->ttcan->TTCPT & FDCAN_TTCPT_CCV) >> FDCAN_TTCPT_CCV_Pos);
+
+          /* Clear the TT Stop Watch flag */
+          __HAL_FDCAN_TT_CLEAR_FLAG(hfdcan, FDCAN_TT_FLAG_STOP_WATCH);
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+          /* Call registered callback*/
+          hfdcan->TT_StopWatchCallback(hfdcan, SWTime, SWCycleCount);
+#else
+          /* TT Stop Watch Callback */
+          HAL_FDCAN_TT_StopWatchCallback(hfdcan, SWTime, SWCycleCount);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+        }
+      }
+
+      /* TT Global Time interrupts management ***********************************/
+      if (TTGlobTimeITs != 0U)
+      {
+        /* Clear the TT Global Time flags */
+        __HAL_FDCAN_TT_CLEAR_FLAG(hfdcan, TTGlobTimeITs);
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+        /* Call registered callback*/
+        hfdcan->TT_GlobalTimeCallback(hfdcan, TTGlobTimeITs);
+#else
+        /* TT Global Time Callback */
+        HAL_FDCAN_TT_GlobalTimeCallback(hfdcan, TTGlobTimeITs);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+      }
+
+      /* TT Disturbing Error interrupts management ******************************/
+      if (TTDistErrors != 0U)
+      {
+        /* Clear the TT Disturbing Error flags */
+        __HAL_FDCAN_TT_CLEAR_FLAG(hfdcan, TTDistErrors);
+
+        /* Update error code */
+        hfdcan->ErrorCode |= TTDistErrors;
+      }
+
+      /* TT Fatal Error interrupts management ***********************************/
+      if (TTFatalErrors != 0U)
+      {
+        /* Clear the TT Fatal Error flags */
+        __HAL_FDCAN_TT_CLEAR_FLAG(hfdcan, TTFatalErrors);
+
+        /* Update error code */
+        hfdcan->ErrorCode |= TTFatalErrors;
+      }
+    }
+  }
+
+  if (hfdcan->ErrorCode != HAL_FDCAN_ERROR_NONE)
+  {
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+    /* Call registered callback*/
+    hfdcan->ErrorCallback(hfdcan);
+#else
+    /* Error Callback */
+    HAL_FDCAN_ErrorCallback(hfdcan);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Exported_Functions_Group6 Callback functions
+ *  @brief   FDCAN Callback functions
+ *
+@verbatim
+  ==============================================================================
+                          ##### Callback functions #####
+  ==============================================================================
+    [..]
+    This subsection provides the following callback functions:
+      (+) HAL_FDCAN_ClockCalibrationCallback
+      (+) HAL_FDCAN_TxEventFifoCallback
+      (+) HAL_FDCAN_RxFifo0Callback
+      (+) HAL_FDCAN_RxFifo1Callback
+      (+) HAL_FDCAN_TxFifoEmptyCallback
+      (+) HAL_FDCAN_TxBufferCompleteCallback
+      (+) HAL_FDCAN_TxBufferAbortCallback
+      (+) HAL_FDCAN_RxBufferNewMessageCallback
+      (+) HAL_FDCAN_HighPriorityMessageCallback
+      (+) HAL_FDCAN_TimestampWraparoundCallback
+      (+) HAL_FDCAN_TimeoutOccurredCallback
+      (+) HAL_FDCAN_ErrorCallback
+      (+) HAL_FDCAN_ErrorStatusCallback
+      (+) HAL_FDCAN_TT_ScheduleSyncCallback
+      (+) HAL_FDCAN_TT_TimeMarkCallback
+      (+) HAL_FDCAN_TT_StopWatchCallback
+      (+) HAL_FDCAN_TT_GlobalTimeCallback
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Clock Calibration callback.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  ClkCalibrationITs indicates which Clock Calibration interrupts are signaled.
+  *         This parameter can be any combination of @arg FDCAN_Clock_Calibration_Interrupts.
+  * @retval None
+  */
+__weak void HAL_FDCAN_ClockCalibrationCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t ClkCalibrationITs)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hfdcan);
+  UNUSED(ClkCalibrationITs);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_ClockCalibrationCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Tx Event callback.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  TxEventFifoITs indicates which Tx Event FIFO interrupts are signaled.
+  *         This parameter can be any combination of @arg FDCAN_Tx_Event_Fifo_Interrupts.
+  * @retval None
+  */
+__weak void HAL_FDCAN_TxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TxEventFifoITs)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hfdcan);
+  UNUSED(TxEventFifoITs);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_TxEventFifoCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Rx FIFO 0 callback.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  RxFifo0ITs indicates which Rx FIFO 0 interrupts are signaled.
+  *         This parameter can be any combination of @arg FDCAN_Rx_Fifo0_Interrupts.
+  * @retval None
+  */
+__weak void HAL_FDCAN_RxFifo0Callback(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hfdcan);
+  UNUSED(RxFifo0ITs);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_RxFifo0Callback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Rx FIFO 1 callback.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  RxFifo1ITs indicates which Rx FIFO 1 interrupts are signaled.
+  *         This parameter can be any combination of @arg FDCAN_Rx_Fifo1_Interrupts.
+  * @retval None
+  */
+__weak void HAL_FDCAN_RxFifo1Callback(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo1ITs)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hfdcan);
+  UNUSED(RxFifo1ITs);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_RxFifo1Callback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Tx FIFO Empty callback.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval None
+  */
+__weak void HAL_FDCAN_TxFifoEmptyCallback(FDCAN_HandleTypeDef *hfdcan)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hfdcan);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_TxFifoEmptyCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Transmission Complete callback.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  BufferIndexes Indexes of the transmitted buffers.
+  *         This parameter can be any combination of @arg FDCAN_Tx_location.
+  * @retval None
+  */
+__weak void HAL_FDCAN_TxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hfdcan);
+  UNUSED(BufferIndexes);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_TxBufferCompleteCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Transmission Cancellation callback.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  BufferIndexes Indexes of the aborted buffers.
+  *         This parameter can be any combination of @arg FDCAN_Tx_location.
+  * @retval None
+  */
+__weak void HAL_FDCAN_TxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hfdcan);
+  UNUSED(BufferIndexes);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_TxBufferAbortCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Rx Buffer New Message callback.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval None
+  */
+__weak void HAL_FDCAN_RxBufferNewMessageCallback(FDCAN_HandleTypeDef *hfdcan)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hfdcan);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_RxBufferNewMessageCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Timestamp Wraparound callback.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval None
+  */
+__weak void HAL_FDCAN_TimestampWraparoundCallback(FDCAN_HandleTypeDef *hfdcan)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hfdcan);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_TimestampWraparoundCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Timeout Occurred callback.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval None
+  */
+__weak void HAL_FDCAN_TimeoutOccurredCallback(FDCAN_HandleTypeDef *hfdcan)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hfdcan);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_TimeoutOccurredCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  High Priority Message callback.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval None
+  */
+__weak void HAL_FDCAN_HighPriorityMessageCallback(FDCAN_HandleTypeDef *hfdcan)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hfdcan);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_HighPriorityMessageCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Error callback.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval None
+  */
+__weak void HAL_FDCAN_ErrorCallback(FDCAN_HandleTypeDef *hfdcan)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hfdcan);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_ErrorCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Error status callback.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  ErrorStatusITs indicates which Error Status interrupts are signaled.
+  *         This parameter can be any combination of @arg FDCAN_Error_Status_Interrupts.
+  * @retval None
+  */
+__weak void HAL_FDCAN_ErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t ErrorStatusITs)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hfdcan);
+  UNUSED(ErrorStatusITs);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_ErrorStatusCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  TT Schedule Synchronization callback.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  TTSchedSyncITs indicates which TT Schedule Synchronization interrupts are signaled.
+  *         This parameter can be any combination of @arg FDCAN_TTScheduleSynchronization_Interrupts.
+  * @retval None
+  */
+__weak void HAL_FDCAN_TT_ScheduleSyncCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TTSchedSyncITs)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hfdcan);
+  UNUSED(TTSchedSyncITs);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_TT_ScheduleSyncCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  TT Time Mark callback.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  TTTimeMarkITs indicates which TT Schedule Synchronization interrupts are signaled.
+  *         This parameter can be any combination of @arg FDCAN_TTTimeMark_Interrupts.
+  * @retval None
+  */
+__weak void HAL_FDCAN_TT_TimeMarkCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TTTimeMarkITs)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hfdcan);
+  UNUSED(TTTimeMarkITs);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_TT_TimeMarkCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  TT Stop Watch callback.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  SWTime Time Value captured at the Stop Watch Trigger pin (fdcan1_swt) falling/rising
+  *         edge (as configured via HAL_FDCAN_TTConfigStopWatch).
+  *         This parameter is a number between 0 and 0xFFFF.
+  * @param  SWCycleCount Cycle count value captured together with SWTime.
+  *         This parameter is a number between 0 and 0x3F.
+  * @retval None
+  */
+__weak void HAL_FDCAN_TT_StopWatchCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t SWTime, uint32_t SWCycleCount)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hfdcan);
+  UNUSED(SWTime);
+  UNUSED(SWCycleCount);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_TT_StopWatchCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  TT Global Time callback.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  TTGlobTimeITs indicates which TT Global Time interrupts are signaled.
+  *         This parameter can be any combination of @arg FDCAN_TTGlobalTime_Interrupts.
+  * @retval None
+  */
+__weak void HAL_FDCAN_TT_GlobalTimeCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TTGlobTimeITs)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hfdcan);
+  UNUSED(TTGlobTimeITs);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_TT_GlobalTimeCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Exported_Functions_Group7 Peripheral State functions
+ *  @brief   FDCAN Peripheral State functions
+ *
+@verbatim
+  ==============================================================================
+                      ##### Peripheral State functions #####
+  ==============================================================================
+    [..]
+    This subsection provides functions allowing to :
+      (+) HAL_FDCAN_GetState()  : Return the FDCAN state.
+      (+) HAL_FDCAN_GetError()  : Return the FDCAN error code if any.
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Return the FDCAN state
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL state
+  */
+HAL_FDCAN_StateTypeDef HAL_FDCAN_GetState(FDCAN_HandleTypeDef *hfdcan)
+{
+  /* Return FDCAN state */
+  return hfdcan->State;
+}
+
+/**
+  * @brief  Return the FDCAN error code
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval FDCAN Error Code
+  */
+uint32_t HAL_FDCAN_GetError(FDCAN_HandleTypeDef *hfdcan)
+{
+  /* Return FDCAN error code */
+  return hfdcan->ErrorCode;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup FDCAN_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Calculate each RAM block start address and size
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+ */
+static HAL_StatusTypeDef FDCAN_CalcultateRamBlockAddresses(FDCAN_HandleTypeDef *hfdcan)
+{
+  uint32_t RAMcounter;
+  uint32_t StartAddress;
+
+  StartAddress = hfdcan->Init.MessageRAMOffset;
+
+  /* Standard filter list start address */
+  MODIFY_REG(hfdcan->Instance->SIDFC, FDCAN_SIDFC_FLSSA, (StartAddress << FDCAN_SIDFC_FLSSA_Pos));
+
+  /* Standard filter elements number */
+  MODIFY_REG(hfdcan->Instance->SIDFC, FDCAN_SIDFC_LSS, (hfdcan->Init.StdFiltersNbr << FDCAN_SIDFC_LSS_Pos));
+
+  /* Extended filter list start address */
+  StartAddress += hfdcan->Init.StdFiltersNbr;
+  MODIFY_REG(hfdcan->Instance->XIDFC, FDCAN_XIDFC_FLESA, (StartAddress << FDCAN_XIDFC_FLESA_Pos));
+
+  /* Extended filter elements number */
+  MODIFY_REG(hfdcan->Instance->XIDFC, FDCAN_XIDFC_LSE, (hfdcan->Init.ExtFiltersNbr << FDCAN_XIDFC_LSE_Pos));
+
+  /* Rx FIFO 0 start address */
+  StartAddress += (hfdcan->Init.ExtFiltersNbr * 2U);
+  MODIFY_REG(hfdcan->Instance->RXF0C, FDCAN_RXF0C_F0SA, (StartAddress << FDCAN_RXF0C_F0SA_Pos));
+
+  /* Rx FIFO 0 elements number */
+  MODIFY_REG(hfdcan->Instance->RXF0C, FDCAN_RXF0C_F0S, (hfdcan->Init.RxFifo0ElmtsNbr << FDCAN_RXF0C_F0S_Pos));
+
+  /* Rx FIFO 1 start address */
+  StartAddress += (hfdcan->Init.RxFifo0ElmtsNbr * hfdcan->Init.RxFifo0ElmtSize);
+  MODIFY_REG(hfdcan->Instance->RXF1C, FDCAN_RXF1C_F1SA, (StartAddress << FDCAN_RXF1C_F1SA_Pos));
+
+  /* Rx FIFO 1 elements number */
+  MODIFY_REG(hfdcan->Instance->RXF1C, FDCAN_RXF1C_F1S, (hfdcan->Init.RxFifo1ElmtsNbr << FDCAN_RXF1C_F1S_Pos));
+
+  /* Rx buffer list start address */
+  StartAddress += (hfdcan->Init.RxFifo1ElmtsNbr * hfdcan->Init.RxFifo1ElmtSize);
+  MODIFY_REG(hfdcan->Instance->RXBC, FDCAN_RXBC_RBSA, (StartAddress << FDCAN_RXBC_RBSA_Pos));
+
+  /* Tx event FIFO start address */
+  StartAddress += (hfdcan->Init.RxBuffersNbr * hfdcan->Init.RxBufferSize);
+  MODIFY_REG(hfdcan->Instance->TXEFC, FDCAN_TXEFC_EFSA, (StartAddress << FDCAN_TXEFC_EFSA_Pos));
+
+  /* Tx event FIFO elements number */
+  MODIFY_REG(hfdcan->Instance->TXEFC, FDCAN_TXEFC_EFS, (hfdcan->Init.TxEventsNbr << FDCAN_TXEFC_EFS_Pos));
+
+  /* Tx buffer list start address */
+  StartAddress += (hfdcan->Init.TxEventsNbr * 2U);
+  MODIFY_REG(hfdcan->Instance->TXBC, FDCAN_TXBC_TBSA, (StartAddress << FDCAN_TXBC_TBSA_Pos));
+
+  /* Dedicated Tx buffers number */
+  MODIFY_REG(hfdcan->Instance->TXBC, FDCAN_TXBC_NDTB, (hfdcan->Init.TxBuffersNbr << FDCAN_TXBC_NDTB_Pos));
+
+  /* Tx FIFO/queue elements number */
+  MODIFY_REG(hfdcan->Instance->TXBC, FDCAN_TXBC_TFQS, (hfdcan->Init.TxFifoQueueElmtsNbr << FDCAN_TXBC_TFQS_Pos));
+
+  hfdcan->msgRam.StandardFilterSA = SRAMCAN_BASE + (hfdcan->Init.MessageRAMOffset * 4U);
+  hfdcan->msgRam.ExtendedFilterSA = hfdcan->msgRam.StandardFilterSA + (hfdcan->Init.StdFiltersNbr * 4U);
+  hfdcan->msgRam.RxFIFO0SA = hfdcan->msgRam.ExtendedFilterSA + (hfdcan->Init.ExtFiltersNbr * 2U * 4U);
+  hfdcan->msgRam.RxFIFO1SA = hfdcan->msgRam.RxFIFO0SA + (hfdcan->Init.RxFifo0ElmtsNbr * hfdcan->Init.RxFifo0ElmtSize * 4U);
+  hfdcan->msgRam.RxBufferSA = hfdcan->msgRam.RxFIFO1SA + (hfdcan->Init.RxFifo1ElmtsNbr * hfdcan->Init.RxFifo1ElmtSize * 4U);
+  hfdcan->msgRam.TxEventFIFOSA = hfdcan->msgRam.RxBufferSA + (hfdcan->Init.RxBuffersNbr * hfdcan->Init.RxBufferSize * 4U);
+  hfdcan->msgRam.TxBufferSA = hfdcan->msgRam.TxEventFIFOSA + (hfdcan->Init.TxEventsNbr * 2U * 4U);
+  hfdcan->msgRam.TxFIFOQSA = hfdcan->msgRam.TxBufferSA + (hfdcan->Init.TxBuffersNbr * hfdcan->Init.TxElmtSize * 4U);
+
+  hfdcan->msgRam.EndAddress = hfdcan->msgRam.TxFIFOQSA + (hfdcan->Init.TxFifoQueueElmtsNbr * hfdcan->Init.TxElmtSize * 4U);
+
+  if (hfdcan->msgRam.EndAddress > FDCAN_MESSAGE_RAM_END_ADDRESS) /* Last address of the Message RAM */
+  {
+    /* Update error code.
+       Message RAM overflow */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM;
+
+    /* Change FDCAN state */
+    hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+    return HAL_ERROR;
+  }
+  else
+  {
+    /* Flush the allocated Message RAM area */
+    for (RAMcounter = hfdcan->msgRam.StandardFilterSA; RAMcounter < hfdcan->msgRam.EndAddress; RAMcounter += 4U)
+    {
+      *(uint32_t *)(RAMcounter) = 0x00000000;
+    }
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Copy Tx message to the message RAM.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  pTxHeader pointer to a FDCAN_TxHeaderTypeDef structure.
+  * @param  pTxData pointer to a buffer containing the payload of the Tx frame.
+  * @param  BufferIndex index of the buffer to be configured.
+  * @retval HAL status
+ */
+static void FDCAN_CopyMessageToRAM(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData, uint32_t BufferIndex)
+{
+  uint32_t TxElementW1;
+  uint32_t TxElementW2;
+  uint32_t *TxAddress;
+  uint32_t ByteCounter;
+
+  /* Build first word of Tx header element */
+  if (pTxHeader->IdType == FDCAN_STANDARD_ID)
+  {
+    TxElementW1 = (pTxHeader->ErrorStateIndicator |
+                   FDCAN_STANDARD_ID |
+                   pTxHeader->TxFrameType |
+                   (pTxHeader->Identifier << 18));
+  }
+  else /* pTxHeader->IdType == FDCAN_EXTENDED_ID */
+  {
+    TxElementW1 = (pTxHeader->ErrorStateIndicator |
+                   FDCAN_EXTENDED_ID |
+                   pTxHeader->TxFrameType |
+                   pTxHeader->Identifier);
+  }
+
+  /* Build second word of Tx header element */
+  TxElementW2 = ((pTxHeader->MessageMarker << 24) |
+                 pTxHeader->TxEventFifoControl |
+                 pTxHeader->FDFormat |
+                 pTxHeader->BitRateSwitch |
+                 pTxHeader->DataLength);
+
+  /* Calculate Tx element address */
+  TxAddress = (uint32_t *)(hfdcan->msgRam.TxBufferSA + (BufferIndex * hfdcan->Init.TxElmtSize * 4U));
+
+  /* Write Tx element header to the message RAM */
+  *TxAddress = TxElementW1;
+  TxAddress++;
+  *TxAddress = TxElementW2;
+  TxAddress++;
+
+  /* Write Tx payload to the message RAM */
+  for (ByteCounter = 0; ByteCounter < DLCtoBytes[pTxHeader->DataLength >> 16]; ByteCounter += 4U)
+  {
+    *TxAddress = (((uint32_t)pTxData[ByteCounter + 3U] << 24) |
+                  ((uint32_t)pTxData[ByteCounter + 2U] << 16) |
+                  ((uint32_t)pTxData[ByteCounter + 1U] << 8) |
+                  (uint32_t)pTxData[ByteCounter]);
+    TxAddress++;
+  }
+}
+
+/**
+  * @}
+  */
+#endif /* HAL_FDCAN_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* FDCAN1 */
+
diff --git a/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.c b/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.c
new file mode 100644
index 0000000..704d1ba
--- /dev/null
+++ b/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.c
@@ -0,0 +1,4158 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_sd.c
+  * @author  MCD Application Team
+  * @brief   SD card HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Secure Digital (SD) peripheral:
+  *           + Initialization and de-initialization functions
+  *           + IO operation functions
+  *           + Peripheral Control functions
+  *           + Peripheral State functions
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+                        ##### How to use this driver #####
+  ==============================================================================
+  [..]
+    This driver implements a high level communication layer for read and write from/to
+    this memory. The needed STM32 hardware resources (SDMMC and GPIO) are performed by
+    the user in HAL_SD_MspInit() function (MSP layer).
+    Basically, the MSP layer configuration should be the same as we provide in the
+    examples.
+    You can easily tailor this configuration according to hardware resources.
+
+  [..]
+    This driver is a generic layered driver for SDMMC memories which uses the HAL
+    SDMMC driver functions to interface with SD and uSD cards devices.
+    It is used as follows:
+
+    (#)Initialize the SDMMC low level resources by implementing the HAL_SD_MspInit() API:
+        (##) Enable the SDMMC interface clock using __HAL_RCC_SDMMC_CLK_ENABLE();
+        (##) SDMMC pins configuration for SD card
+            (+++) Enable the clock for the SDMMC GPIOs using the functions __HAL_RCC_GPIOx_CLK_ENABLE();
+            (+++) Configure these SDMMC pins as alternate function pull-up using HAL_GPIO_Init()
+                  and according to your pin assignment;
+        (##) NVIC configuration if you need to use interrupt process (HAL_SD_ReadBlocks_IT()
+             and HAL_SD_WriteBlocks_IT() APIs).
+            (+++) Configure the SDMMC interrupt priorities using function HAL_NVIC_SetPriority();
+            (+++) Enable the NVIC SDMMC IRQs using function HAL_NVIC_EnableIRQ()
+            (+++) SDMMC interrupts are managed using the macros __HAL_SD_ENABLE_IT()
+                  and __HAL_SD_DISABLE_IT() inside the communication process.
+            (+++) SDMMC interrupts pending bits are managed using the macros __HAL_SD_GET_IT()
+                  and __HAL_SD_CLEAR_IT()
+        (##) No general propose DMA Configuration is needed, an Internal DMA for SDMMC Peripheral are used.
+
+    (#) At this stage, you can perform SD read/write/erase operations after SD card initialization
+
+
+  *** SD Card Initialization and configuration ***
+  ================================================
+  [..]
+    To initialize the SD Card, use the HAL_SD_Init() function. It Initializes
+    SDMMC Peripheral(STM32 side) and the SD Card, and put it into StandBy State (Ready for data transfer).
+    This function provide the following operations:
+
+    (#) Apply the SD Card initialization process at 400KHz and check the SD Card
+        type (Standard Capacity or High Capacity). You can change or adapt this
+        frequency by adjusting the "ClockDiv" field.
+        The SD Card frequency (SDMMC_CK) is computed as follows:
+
+           SDMMC_CK = SDMMCCLK / (2 * ClockDiv)
+
+        In initialization mode and according to the SD Card standard,
+        make sure that the SDMMC_CK frequency doesn't exceed 400KHz.
+
+        This phase of initialization is done through SDMMC_Init() and
+        SDMMC_PowerState_ON() SDMMC low level APIs.
+
+    (#) Initialize the SD card. The API used is HAL_SD_InitCard().
+        This phase allows the card initialization and identification
+        and check the SD Card type (Standard Capacity or High Capacity)
+        The initialization flow is compatible with SD standard.
+
+        This API (HAL_SD_InitCard()) could be used also to reinitialize the card in case
+        of plug-off plug-in.
+
+    (#) Configure the SD Card Data transfer frequency. You can change or adapt this
+        frequency by adjusting the "ClockDiv" field.
+        In transfer mode and according to the SD Card standard, make sure that the
+        SDMMC_CK frequency doesn't exceed 25MHz and 100MHz in High-speed mode switch.
+
+    (#) Select the corresponding SD Card according to the address read with the step 2.
+
+    (#) Configure the SD Card in wide bus mode: 4-bits data.
+
+  *** SD Card Read operation ***
+  ==============================
+  [..]
+    (+) You can read from SD card in polling mode by using function HAL_SD_ReadBlocks().
+        This function support only 512-bytes block length (the block size should be
+        chosen as 512 bytes).
+        You can choose either one block read operation or multiple block read operation
+        by adjusting the "NumberOfBlocks" parameter.
+        After this, you have to ensure that the transfer is done correctly. The check is done
+        through HAL_SD_GetCardState() function for SD card state.
+
+    (+) You can read from SD card in DMA mode by using function HAL_SD_ReadBlocks_DMA().
+        This function support only 512-bytes block length (the block size should be
+        chosen as 512 bytes).
+        You can choose either one block read operation or multiple block read operation
+        by adjusting the "NumberOfBlocks" parameter.
+        After this, you have to ensure that the transfer is done correctly. The check is done
+        through HAL_SD_GetCardState() function for SD card state.
+        You could also check the DMA transfer process through the SD Rx interrupt event.
+
+    (+) You can read from SD card in Interrupt mode by using function HAL_SD_ReadBlocks_IT().
+        This function support only 512-bytes block length (the block size should be
+        chosen as 512 bytes).
+        You can choose either one block read operation or multiple block read operation
+        by adjusting the "NumberOfBlocks" parameter.
+        After this, you have to ensure that the transfer is done correctly. The check is done
+        through HAL_SD_GetCardState() function for SD card state.
+        You could also check the IT transfer process through the SD Rx interrupt event.
+
+  *** SD Card Write operation ***
+  ===============================
+  [..]
+    (+) You can write to SD card in polling mode by using function HAL_SD_WriteBlocks().
+        This function support only 512-bytes block length (the block size should be
+        chosen as 512 bytes).
+        You can choose either one block read operation or multiple block read operation
+        by adjusting the "NumberOfBlocks" parameter.
+        After this, you have to ensure that the transfer is done correctly. The check is done
+        through HAL_SD_GetCardState() function for SD card state.
+
+    (+) You can write to SD card in DMA mode by using function HAL_SD_WriteBlocks_DMA().
+        This function support only 512-bytes block length (the block size should be
+        chosen as 512 bytes).
+        You can choose either one block read operation or multiple block read operation
+        by adjusting the "NumberOfBlocks" parameter.
+        After this, you have to ensure that the transfer is done correctly. The check is done
+        through HAL_SD_GetCardState() function for SD card state.
+        You could also check the DMA transfer process through the SD Tx interrupt event.
+
+    (+) You can write to SD card in Interrupt mode by using function HAL_SD_WriteBlocks_IT().
+        This function support only 512-bytes block length (the block size should be
+        chosen as 512 bytes).
+        You can choose either one block read operation or multiple block read operation
+        by adjusting the "NumberOfBlocks" parameter.
+        After this, you have to ensure that the transfer is done correctly. The check is done
+        through HAL_SD_GetCardState() function for SD card state.
+        You could also check the IT transfer process through the SD Tx interrupt event.
+
+  *** SD card status ***
+  ======================
+  [..]
+    (+) The SD Status contains status bits that are related to the SD Memory
+        Card proprietary features. To get SD card status use the HAL_SD_GetCardStatus().
+
+  *** SD card information ***
+  ===========================
+  [..]
+    (+) To get SD card information, you can use the function HAL_SD_GetCardInfo().
+        It returns useful information about the SD card such as block size, card type,
+        block number ...
+
+  *** SD card CSD register ***
+  ============================
+    (+) The HAL_SD_GetCardCSD() API allows to get the parameters of the CSD register.
+        Some of the CSD parameters are useful for card initialization and identification.
+
+  *** SD card CID register ***
+  ============================
+    (+) The HAL_SD_GetCardCID() API allows to get the parameters of the CID register.
+        Some of the CSD parameters are useful for card initialization and identification.
+
+  *** SD HAL driver macros list ***
+  ==================================
+  [..]
+    Below the list of most used macros in SD HAL driver.
+
+    (+) __HAL_SD_ENABLE_IT: Enable the SD device interrupt
+    (+) __HAL_SD_DISABLE_IT: Disable the SD device interrupt
+    (+) __HAL_SD_GET_FLAG:Check whether the specified SD flag is set or not
+    (+) __HAL_SD_CLEAR_FLAG: Clear the SD's pending flags
+
+    (@) You can refer to the SD HAL driver header file for more useful macros
+
+  *** Callback registration ***
+  =============================================
+  [..]
+    The compilation define USE_HAL_SD_REGISTER_CALLBACKS when set to 1
+    allows the user to configure dynamically the driver callbacks.
+
+    Use Functions HAL_SD_RegisterCallback() to register a user callback,
+    it allows to register following callbacks:
+      (+) TxCpltCallback : callback when a transmission transfer is completed.
+      (+) RxCpltCallback : callback when a reception transfer is completed.
+      (+) ErrorCallback : callback when error occurs.
+      (+) AbortCpltCallback : callback when abort is completed.
+      (+) Read_DMADblBuf0CpltCallback : callback when the DMA reception of first buffer is completed.
+      (+) Read_DMADblBuf1CpltCallback : callback when the DMA reception of second buffer is completed.
+      (+) Write_DMADblBuf0CpltCallback : callback when the DMA transmission of first buffer is completed.
+      (+) Write_DMADblBuf1CpltCallback : callback when the DMA transmission of second buffer is completed.
+      (+) MspInitCallback    : SD MspInit.
+      (+) MspDeInitCallback  : SD MspDeInit.
+    This function takes as parameters the HAL peripheral handle, the Callback ID
+    and a pointer to the user callback function.
+    For specific callbacks TransceiverCallback use dedicated register callbacks:
+    respectively HAL_SD_RegisterTransceiverCallback().
+
+    Use function HAL_SD_UnRegisterCallback() to reset a callback to the default
+    weak (surcharged) function. It allows to reset following callbacks:
+      (+) TxCpltCallback : callback when a transmission transfer is completed.
+      (+) RxCpltCallback : callback when a reception transfer is completed.
+      (+) ErrorCallback : callback when error occurs.
+      (+) AbortCpltCallback : callback when abort is completed.
+      (+) Read_DMADblBuf0CpltCallback : callback when the DMA reception of first buffer is completed.
+      (+) Read_DMADblBuf1CpltCallback : callback when the DMA reception of second buffer is completed.
+      (+) Write_DMADblBuf0CpltCallback : callback when the DMA transmission of first buffer is completed.
+      (+) Write_DMADblBuf1CpltCallback : callback when the DMA transmission of second buffer is completed.
+      (+) MspInitCallback    : SD MspInit.
+      (+) MspDeInitCallback  : SD MspDeInit.
+    This function) takes as parameters the HAL peripheral handle and the Callback ID.
+    For specific callbacks TransceiverCallback use dedicated unregister callbacks:
+    respectively HAL_SD_UnRegisterTransceiverCallback().
+
+    By default, after the HAL_SD_Init and if the state is HAL_SD_STATE_RESET
+    all callbacks are reset to the corresponding legacy weak (surcharged) functions.
+    Exception done for MspInit and MspDeInit callbacks that are respectively
+    reset to the legacy weak (surcharged) functions in the HAL_SD_Init
+    and HAL_SD_DeInit only when these callbacks are null (not registered beforehand).
+    If not, MspInit or MspDeInit are not null, the HAL_SD_Init and HAL_SD_DeInit
+    keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
+
+    Callbacks can be registered/unregistered in READY state only.
+    Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
+    in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
+    during the Init/DeInit.
+    In that case first register the MspInit/MspDeInit user callbacks
+    using HAL_SD_RegisterCallback before calling HAL_SD_DeInit
+    or HAL_SD_Init function.
+
+    When The compilation define USE_HAL_SD_REGISTER_CALLBACKS is set to 0 or
+    not defined, the callback registering feature is not available
+    and weak (surcharged) callbacks are used.
+
+  @endverbatim
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup SD
+  * @{
+  */
+
+#ifdef HAL_SD_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @addtogroup SD_Private_Defines
+  * @{
+  */
+/* Frequencies used in the driver for clock divider calculation */
+#define SD_INIT_FREQ                   400000U   /* Initialization phase : 400 kHz max */
+#define SD_NORMAL_SPEED_FREQ           25000000U /* Normal speed phase : 25 MHz max */
+#define SD_HIGH_SPEED_FREQ             50000000U /* High speed phase : 50 MHz max */
+/* Private macro -------------------------------------------------------------*/
+#if defined (DLYB_SDMMC1) && defined (DLYB_SDMMC2)
+#define SD_GET_DLYB_INSTANCE(SDMMC_INSTANCE) (((SDMMC_INSTANCE) == SDMMC1)?  \
+                                              DLYB_SDMMC1 : DLYB_SDMMC2 )
+#elif defined (DLYB_SDMMC1)
+#define SD_GET_DLYB_INSTANCE(SDMMC_INSTANCE) ( DLYB_SDMMC1 )
+#endif /* (DLYB_SDMMC1) && defined (DLYB_SDMMC2) */
+
+/**
+  * @}
+  */
+
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup SD_Private_Functions SD Private Functions
+  * @{
+  */
+static uint32_t SD_InitCard(SD_HandleTypeDef *hsd);
+static uint32_t SD_PowerON(SD_HandleTypeDef *hsd);
+static uint32_t SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus);
+static uint32_t SD_SendStatus(SD_HandleTypeDef *hsd, uint32_t *pCardStatus);
+static uint32_t SD_WideBus_Enable(SD_HandleTypeDef *hsd);
+static uint32_t SD_WideBus_Disable(SD_HandleTypeDef *hsd);
+static uint32_t SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR);
+static void     SD_PowerOFF(SD_HandleTypeDef *hsd);
+static void     SD_Write_IT(SD_HandleTypeDef *hsd);
+static void     SD_Read_IT(SD_HandleTypeDef *hsd);
+static uint32_t SD_SwitchSpeed(SD_HandleTypeDef *hsd, uint32_t SwitchSpeedMode);
+#if (USE_SD_TRANSCEIVER != 0U)
+static uint32_t SD_UltraHighSpeed(SD_HandleTypeDef *hsd, uint32_t UltraHighSpeedMode);
+static uint32_t SD_DDR_Mode(SD_HandleTypeDef *hsd);
+#endif /* USE_SD_TRANSCEIVER */
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup SD_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup SD_Exported_Functions_Group1
+  *  @brief   Initialization and de-initialization functions
+  *
+@verbatim
+  ==============================================================================
+          ##### Initialization and de-initialization functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to initialize/de-initialize the SD
+    card device to be ready for use.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the SD according to the specified parameters in the
+            SD_HandleTypeDef and create the associated handle.
+  * @param  hsd: Pointer to the SD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SD_Init(SD_HandleTypeDef *hsd)
+{
+  HAL_SD_CardStatusTypeDef CardStatus;
+  uint32_t speedgrade;
+  uint32_t unitsize;
+  uint32_t tickstart;
+
+  /* Check the SD handle allocation */
+  if (hsd == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_SDMMC_ALL_INSTANCE(hsd->Instance));
+  assert_param(IS_SDMMC_CLOCK_EDGE(hsd->Init.ClockEdge));
+  assert_param(IS_SDMMC_CLOCK_POWER_SAVE(hsd->Init.ClockPowerSave));
+  assert_param(IS_SDMMC_BUS_WIDE(hsd->Init.BusWide));
+  assert_param(IS_SDMMC_HARDWARE_FLOW_CONTROL(hsd->Init.HardwareFlowControl));
+  assert_param(IS_SDMMC_CLKDIV(hsd->Init.ClockDiv));
+
+  if (hsd->State == HAL_SD_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    hsd->Lock = HAL_UNLOCKED;
+
+#if (USE_SD_TRANSCEIVER != 0U)
+    /* Force  SDMMC_TRANSCEIVER_PRESENT for Legacy usage */
+    if (hsd->Init.TranceiverPresent == SDMMC_TRANSCEIVER_UNKNOWN)
+    {
+      hsd->Init.TranceiverPresent = SDMMC_TRANSCEIVER_PRESENT;
+    }
+#endif /*USE_SD_TRANSCEIVER */
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+    /* Reset Callback pointers in HAL_SD_STATE_RESET only */
+    hsd->TxCpltCallback    = HAL_SD_TxCpltCallback;
+    hsd->RxCpltCallback    = HAL_SD_RxCpltCallback;
+    hsd->ErrorCallback     = HAL_SD_ErrorCallback;
+    hsd->AbortCpltCallback = HAL_SD_AbortCallback;
+    hsd->Read_DMADblBuf0CpltCallback = HAL_SDEx_Read_DMADoubleBuf0CpltCallback;
+    hsd->Read_DMADblBuf1CpltCallback = HAL_SDEx_Read_DMADoubleBuf1CpltCallback;
+    hsd->Write_DMADblBuf0CpltCallback = HAL_SDEx_Write_DMADoubleBuf0CpltCallback;
+    hsd->Write_DMADblBuf1CpltCallback = HAL_SDEx_Write_DMADoubleBuf1CpltCallback;
+#if (USE_SD_TRANSCEIVER != 0U)
+    if (hsd->Init.TranceiverPresent == SDMMC_TRANSCEIVER_PRESENT)
+    {
+      hsd->DriveTransceiver_1_8V_Callback = HAL_SD_DriveTransceiver_1_8V_Callback;
+    }
+#endif /* USE_SD_TRANSCEIVER */
+
+    if (hsd->MspInitCallback == NULL)
+    {
+      hsd->MspInitCallback = HAL_SD_MspInit;
+    }
+
+    /* Init the low level hardware */
+    hsd->MspInitCallback(hsd);
+#else
+    /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
+    HAL_SD_MspInit(hsd);
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+  }
+
+  hsd->State = HAL_SD_STATE_PROGRAMMING;
+
+  /* Initialize the Card parameters */
+  if (HAL_SD_InitCard(hsd) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+
+  if (HAL_SD_GetCardStatus(hsd, &CardStatus) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+  /* Get Initial Card Speed from Card Status*/
+  speedgrade = CardStatus.UhsSpeedGrade;
+  unitsize = CardStatus.UhsAllocationUnitSize;
+  if ((hsd->SdCard.CardType == CARD_SDHC_SDXC) && ((speedgrade != 0U) || (unitsize != 0U)))
+  {
+    hsd->SdCard.CardSpeed = CARD_ULTRA_HIGH_SPEED;
+  }
+  else
+  {
+    if (hsd->SdCard.CardType == CARD_SDHC_SDXC)
+    {
+      hsd->SdCard.CardSpeed  = CARD_HIGH_SPEED;
+    }
+    else
+    {
+      hsd->SdCard.CardSpeed  = CARD_NORMAL_SPEED;
+    }
+
+  }
+  /* Configure the bus wide */
+  if (HAL_SD_ConfigWideBusOperation(hsd, hsd->Init.BusWide) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Verify that SD card is ready to use after Initialization */
+  tickstart = HAL_GetTick();
+  while ((HAL_SD_GetCardState(hsd) != HAL_SD_CARD_TRANSFER))
+  {
+    if ((HAL_GetTick() - tickstart) >=  SDMMC_DATATIMEOUT)
+    {
+      hsd->ErrorCode = HAL_SD_ERROR_TIMEOUT;
+      hsd->State = HAL_SD_STATE_READY;
+      return HAL_TIMEOUT;
+    }
+  }
+
+  /* Initialize the error code */
+  hsd->ErrorCode = HAL_SD_ERROR_NONE;
+
+  /* Initialize the SD operation */
+  hsd->Context = SD_CONTEXT_NONE;
+
+  /* Initialize the SD state */
+  hsd->State = HAL_SD_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the SD Card.
+  * @param  hsd: Pointer to SD handle
+  * @note   This function initializes the SD card. It could be used when a card
+            re-initialization is needed.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd)
+{
+  uint32_t errorstate;
+  SD_InitTypeDef Init;
+  uint32_t sdmmc_clk;
+
+  /* Default SDMMC peripheral configuration for SD card initialization */
+  Init.ClockEdge           = SDMMC_CLOCK_EDGE_RISING;
+  Init.ClockPowerSave      = SDMMC_CLOCK_POWER_SAVE_DISABLE;
+  Init.BusWide             = SDMMC_BUS_WIDE_1B;
+  Init.HardwareFlowControl = SDMMC_HARDWARE_FLOW_CONTROL_DISABLE;
+
+  /* Init Clock should be less or equal to 400Khz*/
+  sdmmc_clk     = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SDMMC);
+  if (sdmmc_clk == 0U)
+  {
+    hsd->State = HAL_SD_STATE_READY;
+    hsd->ErrorCode = SDMMC_ERROR_INVALID_PARAMETER;
+    return HAL_ERROR;
+  }
+  Init.ClockDiv = sdmmc_clk / (2U * SD_INIT_FREQ);
+
+#if (USE_SD_TRANSCEIVER != 0U)
+  Init.TranceiverPresent = hsd->Init.TranceiverPresent;
+
+  if (hsd->Init.TranceiverPresent == SDMMC_TRANSCEIVER_PRESENT)
+  {
+    /* Set Transceiver polarity */
+    hsd->Instance->POWER |= SDMMC_POWER_DIRPOL;
+  }
+#elif defined (USE_SD_DIRPOL)
+  /* Set Transceiver polarity */
+  hsd->Instance->POWER |= SDMMC_POWER_DIRPOL;
+#endif /* USE_SD_TRANSCEIVER  */
+
+  /* Initialize SDMMC peripheral interface with default configuration */
+  (void)SDMMC_Init(hsd->Instance, Init);
+
+  /* Set Power State to ON */
+  (void)SDMMC_PowerState_ON(hsd->Instance);
+
+  /* wait 74 Cycles: required power up waiting time before starting
+     the SD initialization sequence */
+  if (Init.ClockDiv != 0U)
+  {
+    sdmmc_clk = sdmmc_clk / (2U * Init.ClockDiv);
+  }
+
+  if (sdmmc_clk != 0U)
+  {
+    HAL_Delay(1U + (74U * 1000U / (sdmmc_clk)));
+  }
+
+  /* Identify card operating voltage */
+  errorstate = SD_PowerON(hsd);
+  if (errorstate != HAL_SD_ERROR_NONE)
+  {
+    hsd->State = HAL_SD_STATE_READY;
+    hsd->ErrorCode |= errorstate;
+    return HAL_ERROR;
+  }
+
+  /* Card initialization */
+  errorstate = SD_InitCard(hsd);
+  if (errorstate != HAL_SD_ERROR_NONE)
+  {
+    hsd->State = HAL_SD_STATE_READY;
+    hsd->ErrorCode |= errorstate;
+    return HAL_ERROR;
+  }
+
+  /* Set Block Size for Card */
+  errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
+  if (errorstate != HAL_SD_ERROR_NONE)
+  {
+    /* Clear all the static flags */
+    __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+    hsd->ErrorCode |= errorstate;
+    hsd->State = HAL_SD_STATE_READY;
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  De-Initializes the SD card.
+  * @param  hsd: Pointer to SD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SD_DeInit(SD_HandleTypeDef *hsd)
+{
+  /* Check the SD handle allocation */
+  if (hsd == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_SDMMC_ALL_INSTANCE(hsd->Instance));
+
+  hsd->State = HAL_SD_STATE_BUSY;
+
+#if (USE_SD_TRANSCEIVER != 0U)
+  /* Deactivate the 1.8V Mode */
+  if (hsd->Init.TranceiverPresent == SDMMC_TRANSCEIVER_PRESENT)
+  {
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+    if (hsd->DriveTransceiver_1_8V_Callback == NULL)
+    {
+      hsd->DriveTransceiver_1_8V_Callback = HAL_SD_DriveTransceiver_1_8V_Callback;
+    }
+    hsd->DriveTransceiver_1_8V_Callback(RESET);
+#else
+    HAL_SD_DriveTransceiver_1_8V_Callback(RESET);
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+  }
+#endif /* USE_SD_TRANSCEIVER   */
+
+  /* Set SD power state to off */
+  SD_PowerOFF(hsd);
+
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+  if (hsd->MspDeInitCallback == NULL)
+  {
+    hsd->MspDeInitCallback = HAL_SD_MspDeInit;
+  }
+
+  /* DeInit the low level hardware */
+  hsd->MspDeInitCallback(hsd);
+#else
+  /* De-Initialize the MSP layer */
+  HAL_SD_MspDeInit(hsd);
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+
+  hsd->ErrorCode = HAL_SD_ERROR_NONE;
+  hsd->State = HAL_SD_STATE_RESET;
+
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  Initializes the SD MSP.
+  * @param  hsd: Pointer to SD handle
+  * @retval None
+  */
+__weak void HAL_SD_MspInit(SD_HandleTypeDef *hsd)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsd);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SD_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  De-Initialize SD MSP.
+  * @param  hsd: Pointer to SD handle
+  * @retval None
+  */
+__weak void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsd);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SD_MspDeInit could be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @addtogroup SD_Exported_Functions_Group2
+  *  @brief   Data transfer functions
+  *
+@verbatim
+  ==============================================================================
+                        ##### IO operation functions #####
+  ==============================================================================
+  [..]
+    This subsection provides a set of functions allowing to manage the data
+    transfer from/to SD card.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Reads block(s) from a specified address in a card. The Data transfer
+  *         is managed by polling mode.
+  * @note   This API should be followed by a check on the card state through
+  *         HAL_SD_GetCardState().
+  * @param  hsd: Pointer to SD handle
+  * @param  pData: pointer to the buffer that will contain the received data
+  * @param  BlockAdd: Block Address from where data is to be read
+  * @param  NumberOfBlocks: Number of SD blocks to read
+  * @param  Timeout: Specify timeout value
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks,
+                                    uint32_t Timeout)
+{
+  SDMMC_DataInitTypeDef config;
+  uint32_t errorstate;
+  uint32_t tickstart = HAL_GetTick();
+  uint32_t count;
+  uint32_t data;
+  uint32_t dataremaining;
+  uint32_t add = BlockAdd;
+  uint8_t *tempbuff = pData;
+
+  if (NULL == pData)
+  {
+    hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
+    return HAL_ERROR;
+  }
+
+  if (hsd->State == HAL_SD_STATE_READY)
+  {
+    hsd->ErrorCode = HAL_SD_ERROR_NONE;
+
+    if ((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
+    {
+      hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
+      return HAL_ERROR;
+    }
+
+    hsd->State = HAL_SD_STATE_BUSY;
+
+    /* Initialize data control register */
+    hsd->Instance->DCTRL = 0U;
+
+    if (hsd->SdCard.CardType != CARD_SDHC_SDXC)
+    {
+      add *= 512U;
+    }
+
+    /* Configure the SD DPSM (Data Path State Machine) */
+    config.DataTimeOut   = SDMMC_DATATIMEOUT;
+    config.DataLength    = NumberOfBlocks * BLOCKSIZE;
+    config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
+    config.TransferDir   = SDMMC_TRANSFER_DIR_TO_SDMMC;
+    config.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
+    config.DPSM          = SDMMC_DPSM_DISABLE;
+    (void)SDMMC_ConfigData(hsd->Instance, &config);
+    __SDMMC_CMDTRANS_ENABLE(hsd->Instance);
+
+    /* Read block(s) in polling mode */
+    if (NumberOfBlocks > 1U)
+    {
+      hsd->Context = SD_CONTEXT_READ_MULTIPLE_BLOCK;
+
+      /* Read Multi Block command */
+      errorstate = SDMMC_CmdReadMultiBlock(hsd->Instance, add);
+    }
+    else
+    {
+      hsd->Context = SD_CONTEXT_READ_SINGLE_BLOCK;
+
+      /* Read Single Block command */
+      errorstate = SDMMC_CmdReadSingleBlock(hsd->Instance, add);
+    }
+    if (errorstate != HAL_SD_ERROR_NONE)
+    {
+      /* Clear all the static flags */
+      __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+      hsd->ErrorCode |= errorstate;
+      hsd->State = HAL_SD_STATE_READY;
+      hsd->Context = SD_CONTEXT_NONE;
+      return HAL_ERROR;
+    }
+
+    /* Poll on SDMMC flags */
+    dataremaining = config.DataLength;
+    while (!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND))
+    {
+      if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF) && (dataremaining >= 32U))
+      {
+        /* Read data from SDMMC Rx FIFO */
+        for (count = 0U; count < 8U; count++)
+        {
+          data = SDMMC_ReadFIFO(hsd->Instance);
+          *tempbuff = (uint8_t)(data & 0xFFU);
+          tempbuff++;
+          *tempbuff = (uint8_t)((data >> 8U) & 0xFFU);
+          tempbuff++;
+          *tempbuff = (uint8_t)((data >> 16U) & 0xFFU);
+          tempbuff++;
+          *tempbuff = (uint8_t)((data >> 24U) & 0xFFU);
+          tempbuff++;
+        }
+        dataremaining -= 32U;
+      }
+
+      if (((HAL_GetTick() - tickstart) >=  Timeout) || (Timeout == 0U))
+      {
+        /* Clear all the static flags */
+        __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+        hsd->ErrorCode |= HAL_SD_ERROR_TIMEOUT;
+        hsd->State = HAL_SD_STATE_READY;
+        hsd->Context = SD_CONTEXT_NONE;
+        return HAL_TIMEOUT;
+      }
+    }
+    __SDMMC_CMDTRANS_DISABLE(hsd->Instance);
+
+    /* Send stop transmission command in case of multiblock read */
+    if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DATAEND) && (NumberOfBlocks > 1U))
+    {
+      if (hsd->SdCard.CardType != CARD_SECURED)
+      {
+        /* Send stop transmission command */
+        errorstate = SDMMC_CmdStopTransfer(hsd->Instance);
+        if (errorstate != HAL_SD_ERROR_NONE)
+        {
+          /* Clear all the static flags */
+          __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+          hsd->ErrorCode |= errorstate;
+          hsd->State = HAL_SD_STATE_READY;
+          hsd->Context = SD_CONTEXT_NONE;
+          return HAL_ERROR;
+        }
+      }
+    }
+
+    /* Get error state */
+    if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT))
+    {
+      /* Clear all the static flags */
+      __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+      hsd->ErrorCode |= HAL_SD_ERROR_DATA_TIMEOUT;
+      hsd->State = HAL_SD_STATE_READY;
+      hsd->Context = SD_CONTEXT_NONE;
+      return HAL_ERROR;
+    }
+    else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL))
+    {
+      /* Clear all the static flags */
+      __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+      hsd->ErrorCode |= HAL_SD_ERROR_DATA_CRC_FAIL;
+      hsd->State = HAL_SD_STATE_READY;
+      hsd->Context = SD_CONTEXT_NONE;
+      return HAL_ERROR;
+    }
+    else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR))
+    {
+      /* Clear all the static flags */
+      __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+      hsd->ErrorCode |= HAL_SD_ERROR_RX_OVERRUN;
+      hsd->State = HAL_SD_STATE_READY;
+      hsd->Context = SD_CONTEXT_NONE;
+      return HAL_ERROR;
+    }
+    else
+    {
+      /* Nothing to do */
+    }
+
+    /* Clear all the static flags */
+    __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS);
+
+    hsd->State = HAL_SD_STATE_READY;
+
+    return HAL_OK;
+  }
+  else
+  {
+    hsd->ErrorCode |= HAL_SD_ERROR_BUSY;
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Allows to write block(s) to a specified address in a card. The Data
+  *         transfer is managed by polling mode.
+  * @note   This API should be followed by a check on the card state through
+  *         HAL_SD_GetCardState().
+  * @param  hsd: Pointer to SD handle
+  * @param  pData: pointer to the buffer that will contain the data to transmit
+  * @param  BlockAdd: Block Address where data will be written
+  * @param  NumberOfBlocks: Number of SD blocks to write
+  * @param  Timeout: Specify timeout value
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, const uint8_t *pData, uint32_t BlockAdd,
+                                     uint32_t NumberOfBlocks, uint32_t Timeout)
+{
+  SDMMC_DataInitTypeDef config;
+  uint32_t errorstate;
+  uint32_t tickstart = HAL_GetTick();
+  uint32_t count;
+  uint32_t data;
+  uint32_t dataremaining;
+  uint32_t add = BlockAdd;
+  const uint8_t *tempbuff = pData;
+
+  if (NULL == pData)
+  {
+    hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
+    return HAL_ERROR;
+  }
+
+  if (hsd->State == HAL_SD_STATE_READY)
+  {
+    hsd->ErrorCode = HAL_SD_ERROR_NONE;
+
+    if ((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
+    {
+      hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
+      return HAL_ERROR;
+    }
+
+    hsd->State = HAL_SD_STATE_BUSY;
+
+    /* Initialize data control register */
+    hsd->Instance->DCTRL = 0U;
+
+    if (hsd->SdCard.CardType != CARD_SDHC_SDXC)
+    {
+      add *= 512U;
+    }
+
+    /* Configure the SD DPSM (Data Path State Machine) */
+    config.DataTimeOut   = SDMMC_DATATIMEOUT;
+    config.DataLength    = NumberOfBlocks * BLOCKSIZE;
+    config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
+    config.TransferDir   = SDMMC_TRANSFER_DIR_TO_CARD;
+    config.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
+    config.DPSM          = SDMMC_DPSM_DISABLE;
+    (void)SDMMC_ConfigData(hsd->Instance, &config);
+    __SDMMC_CMDTRANS_ENABLE(hsd->Instance);
+
+    /* Write Blocks in Polling mode */
+    if (NumberOfBlocks > 1U)
+    {
+      hsd->Context = SD_CONTEXT_WRITE_MULTIPLE_BLOCK;
+
+      /* Write Multi Block command */
+      errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, add);
+    }
+    else
+    {
+      hsd->Context = SD_CONTEXT_WRITE_SINGLE_BLOCK;
+
+      /* Write Single Block command */
+      errorstate = SDMMC_CmdWriteSingleBlock(hsd->Instance, add);
+    }
+    if (errorstate != HAL_SD_ERROR_NONE)
+    {
+      /* Clear all the static flags */
+      __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+      hsd->ErrorCode |= errorstate;
+      hsd->State = HAL_SD_STATE_READY;
+      hsd->Context = SD_CONTEXT_NONE;
+      return HAL_ERROR;
+    }
+
+    /* Write block(s) in polling mode */
+    dataremaining = config.DataLength;
+    while (!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT |
+                              SDMMC_FLAG_DATAEND))
+    {
+      if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXFIFOHE) && (dataremaining >= 32U))
+      {
+        /* Write data to SDMMC Tx FIFO */
+        for (count = 0U; count < 8U; count++)
+        {
+          data = (uint32_t)(*tempbuff);
+          tempbuff++;
+          data |= ((uint32_t)(*tempbuff) << 8U);
+          tempbuff++;
+          data |= ((uint32_t)(*tempbuff) << 16U);
+          tempbuff++;
+          data |= ((uint32_t)(*tempbuff) << 24U);
+          tempbuff++;
+          (void)SDMMC_WriteFIFO(hsd->Instance, &data);
+        }
+        dataremaining -= 32U;
+      }
+
+      if (((HAL_GetTick() - tickstart) >=  Timeout) || (Timeout == 0U))
+      {
+        /* Clear all the static flags */
+        __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+        hsd->ErrorCode |= errorstate;
+        hsd->State = HAL_SD_STATE_READY;
+        hsd->Context = SD_CONTEXT_NONE;
+        return HAL_TIMEOUT;
+      }
+    }
+    __SDMMC_CMDTRANS_DISABLE(hsd->Instance);
+
+    /* Send stop transmission command in case of multiblock write */
+    if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DATAEND) && (NumberOfBlocks > 1U))
+    {
+      if (hsd->SdCard.CardType != CARD_SECURED)
+      {
+        /* Send stop transmission command */
+        errorstate = SDMMC_CmdStopTransfer(hsd->Instance);
+        if (errorstate != HAL_SD_ERROR_NONE)
+        {
+          /* Clear all the static flags */
+          __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+          hsd->ErrorCode |= errorstate;
+          hsd->State = HAL_SD_STATE_READY;
+          hsd->Context = SD_CONTEXT_NONE;
+          return HAL_ERROR;
+        }
+      }
+    }
+
+    /* Get error state */
+    if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT))
+    {
+      /* Clear all the static flags */
+      __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+      hsd->ErrorCode |= HAL_SD_ERROR_DATA_TIMEOUT;
+      hsd->State = HAL_SD_STATE_READY;
+      hsd->Context = SD_CONTEXT_NONE;
+      return HAL_ERROR;
+    }
+    else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL))
+    {
+      /* Clear all the static flags */
+      __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+      hsd->ErrorCode |= HAL_SD_ERROR_DATA_CRC_FAIL;
+      hsd->State = HAL_SD_STATE_READY;
+      hsd->Context = SD_CONTEXT_NONE;
+      return HAL_ERROR;
+    }
+    else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXUNDERR))
+    {
+      /* Clear all the static flags */
+      __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+      hsd->ErrorCode |= HAL_SD_ERROR_TX_UNDERRUN;
+      hsd->State = HAL_SD_STATE_READY;
+      hsd->Context = SD_CONTEXT_NONE;
+      return HAL_ERROR;
+    }
+    else
+    {
+      /* Nothing to do */
+    }
+
+    /* Clear all the static flags */
+    __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS);
+
+    hsd->State = HAL_SD_STATE_READY;
+
+    return HAL_OK;
+  }
+  else
+  {
+    hsd->ErrorCode |= HAL_SD_ERROR_BUSY;
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Reads block(s) from a specified address in a card. The Data transfer
+  *         is managed in interrupt mode.
+  * @note   This API should be followed by a check on the card state through
+  *         HAL_SD_GetCardState().
+  * @note   You could also check the IT transfer process through the SD Rx
+  *         interrupt event.
+  * @param  hsd: Pointer to SD handle
+  * @param  pData: Pointer to the buffer that will contain the received data
+  * @param  BlockAdd: Block Address from where data is to be read
+  * @param  NumberOfBlocks: Number of blocks to read.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SD_ReadBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd,
+                                       uint32_t NumberOfBlocks)
+{
+  SDMMC_DataInitTypeDef config;
+  uint32_t errorstate;
+  uint32_t add = BlockAdd;
+
+  if (NULL == pData)
+  {
+    hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
+    return HAL_ERROR;
+  }
+
+  if (hsd->State == HAL_SD_STATE_READY)
+  {
+    hsd->ErrorCode = HAL_SD_ERROR_NONE;
+
+    if ((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
+    {
+      hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
+      return HAL_ERROR;
+    }
+
+    hsd->State = HAL_SD_STATE_BUSY;
+
+    /* Initialize data control register */
+    hsd->Instance->DCTRL = 0U;
+
+    hsd->pRxBuffPtr = pData;
+    hsd->RxXferSize = BLOCKSIZE * NumberOfBlocks;
+
+    if (hsd->SdCard.CardType != CARD_SDHC_SDXC)
+    {
+      add *= 512U;
+    }
+
+    /* Configure the SD DPSM (Data Path State Machine) */
+    config.DataTimeOut   = SDMMC_DATATIMEOUT;
+    config.DataLength    = BLOCKSIZE * NumberOfBlocks;
+    config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
+    config.TransferDir   = SDMMC_TRANSFER_DIR_TO_SDMMC;
+    config.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
+    config.DPSM          = SDMMC_DPSM_DISABLE;
+    (void)SDMMC_ConfigData(hsd->Instance, &config);
+    __SDMMC_CMDTRANS_ENABLE(hsd->Instance);
+
+    /* Read Blocks in IT mode */
+    if (NumberOfBlocks > 1U)
+    {
+      hsd->Context = (SD_CONTEXT_READ_MULTIPLE_BLOCK | SD_CONTEXT_IT);
+
+      /* Read Multi Block command */
+      errorstate = SDMMC_CmdReadMultiBlock(hsd->Instance, add);
+    }
+    else
+    {
+      hsd->Context = (SD_CONTEXT_READ_SINGLE_BLOCK | SD_CONTEXT_IT);
+
+      /* Read Single Block command */
+      errorstate = SDMMC_CmdReadSingleBlock(hsd->Instance, add);
+    }
+    if (errorstate != HAL_SD_ERROR_NONE)
+    {
+      /* Clear all the static flags */
+      __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+      hsd->ErrorCode |= errorstate;
+      hsd->State = HAL_SD_STATE_READY;
+      hsd->Context = SD_CONTEXT_NONE;
+      return HAL_ERROR;
+    }
+
+    __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND |
+                             SDMMC_FLAG_RXFIFOHF));
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Writes block(s) to a specified address in a card. The Data transfer
+  *         is managed in interrupt mode.
+  * @note   This API should be followed by a check on the card state through
+  *         HAL_SD_GetCardState().
+  * @note   You could also check the IT transfer process through the SD Tx
+  *         interrupt event.
+  * @param  hsd: Pointer to SD handle
+  * @param  pData: Pointer to the buffer that will contain the data to transmit
+  * @param  BlockAdd: Block Address where data will be written
+  * @param  NumberOfBlocks: Number of blocks to write
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, const uint8_t *pData, uint32_t BlockAdd,
+                                        uint32_t NumberOfBlocks)
+{
+  SDMMC_DataInitTypeDef config;
+  uint32_t errorstate;
+  uint32_t add = BlockAdd;
+
+  if (NULL == pData)
+  {
+    hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
+    return HAL_ERROR;
+  }
+
+  if (hsd->State == HAL_SD_STATE_READY)
+  {
+    hsd->ErrorCode = HAL_SD_ERROR_NONE;
+
+    if ((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
+    {
+      hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
+      return HAL_ERROR;
+    }
+
+    hsd->State = HAL_SD_STATE_BUSY;
+
+    /* Initialize data control register */
+    hsd->Instance->DCTRL = 0U;
+
+    hsd->pTxBuffPtr = pData;
+    hsd->TxXferSize = BLOCKSIZE * NumberOfBlocks;
+
+    if (hsd->SdCard.CardType != CARD_SDHC_SDXC)
+    {
+      add *= 512U;
+    }
+
+    /* Configure the SD DPSM (Data Path State Machine) */
+    config.DataTimeOut   = SDMMC_DATATIMEOUT;
+    config.DataLength    = BLOCKSIZE * NumberOfBlocks;
+    config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
+    config.TransferDir   = SDMMC_TRANSFER_DIR_TO_CARD;
+    config.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
+    config.DPSM          = SDMMC_DPSM_DISABLE;
+    (void)SDMMC_ConfigData(hsd->Instance, &config);
+
+    __SDMMC_CMDTRANS_ENABLE(hsd->Instance);
+
+    /* Write Blocks in Polling mode */
+    if (NumberOfBlocks > 1U)
+    {
+      hsd->Context = (SD_CONTEXT_WRITE_MULTIPLE_BLOCK | SD_CONTEXT_IT);
+
+      /* Write Multi Block command */
+      errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, add);
+    }
+    else
+    {
+      hsd->Context = (SD_CONTEXT_WRITE_SINGLE_BLOCK | SD_CONTEXT_IT);
+
+      /* Write Single Block command */
+      errorstate = SDMMC_CmdWriteSingleBlock(hsd->Instance, add);
+    }
+    if (errorstate != HAL_SD_ERROR_NONE)
+    {
+      /* Clear all the static flags */
+      __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+      hsd->ErrorCode |= errorstate;
+      hsd->State = HAL_SD_STATE_READY;
+      hsd->Context = SD_CONTEXT_NONE;
+      return HAL_ERROR;
+    }
+
+    /* Enable transfer interrupts */
+    __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND |
+                             SDMMC_FLAG_TXFIFOHE));
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Reads block(s) from a specified address in a card. The Data transfer
+  *         is managed by DMA mode.
+  * @note   This API should be followed by a check on the card state through
+  *         HAL_SD_GetCardState().
+  * @note   You could also check the DMA transfer process through the SD Rx
+  *         interrupt event.
+  * @param  hsd: Pointer SD handle
+  * @param  pData: Pointer to the buffer that will contain the received data
+  * @param  BlockAdd: Block Address from where data is to be read
+  * @param  NumberOfBlocks: Number of blocks to read.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd,
+                                        uint32_t NumberOfBlocks)
+{
+  SDMMC_DataInitTypeDef config;
+  uint32_t errorstate;
+  uint32_t add = BlockAdd;
+
+  if (NULL == pData)
+  {
+    hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
+    return HAL_ERROR;
+  }
+
+  if (hsd->State == HAL_SD_STATE_READY)
+  {
+    hsd->ErrorCode = HAL_SD_ERROR_NONE;
+
+    if ((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
+    {
+      hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
+      return HAL_ERROR;
+    }
+
+    hsd->State = HAL_SD_STATE_BUSY;
+
+    /* Initialize data control register */
+    hsd->Instance->DCTRL = 0U;
+
+    hsd->pRxBuffPtr = pData;
+    hsd->RxXferSize = BLOCKSIZE * NumberOfBlocks;
+
+    if (hsd->SdCard.CardType != CARD_SDHC_SDXC)
+    {
+      add *= 512U;
+    }
+
+    /* Configure the SD DPSM (Data Path State Machine) */
+    config.DataTimeOut   = SDMMC_DATATIMEOUT;
+    config.DataLength    = BLOCKSIZE * NumberOfBlocks;
+    config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
+    config.TransferDir   = SDMMC_TRANSFER_DIR_TO_SDMMC;
+    config.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
+    config.DPSM          = SDMMC_DPSM_DISABLE;
+    (void)SDMMC_ConfigData(hsd->Instance, &config);
+
+    __SDMMC_CMDTRANS_ENABLE(hsd->Instance);
+    hsd->Instance->IDMABASE0 = (uint32_t) pData ;
+    hsd->Instance->IDMACTRL  = SDMMC_ENABLE_IDMA_SINGLE_BUFF;
+
+    /* Read Blocks in DMA mode */
+    if (NumberOfBlocks > 1U)
+    {
+      hsd->Context = (SD_CONTEXT_READ_MULTIPLE_BLOCK | SD_CONTEXT_DMA);
+
+      /* Read Multi Block command */
+      errorstate = SDMMC_CmdReadMultiBlock(hsd->Instance, add);
+    }
+    else
+    {
+      hsd->Context = (SD_CONTEXT_READ_SINGLE_BLOCK | SD_CONTEXT_DMA);
+
+      /* Read Single Block command */
+      errorstate = SDMMC_CmdReadSingleBlock(hsd->Instance, add);
+    }
+    if (errorstate != HAL_SD_ERROR_NONE)
+    {
+      /* Clear all the static flags */
+      __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+      hsd->ErrorCode |= errorstate;
+      hsd->State = HAL_SD_STATE_READY;
+      hsd->Context = SD_CONTEXT_NONE;
+      return HAL_ERROR;
+    }
+
+    /* Enable transfer interrupts */
+    __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND));
+
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Writes block(s) to a specified address in a card. The Data transfer
+  *         is managed by DMA mode.
+  * @note   This API should be followed by a check on the card state through
+  *         HAL_SD_GetCardState().
+  * @note   You could also check the DMA transfer process through the SD Tx
+  *         interrupt event.
+  * @param  hsd: Pointer to SD handle
+  * @param  pData: Pointer to the buffer that will contain the data to transmit
+  * @param  BlockAdd: Block Address where data will be written
+  * @param  NumberOfBlocks: Number of blocks to write
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, const uint8_t *pData, uint32_t BlockAdd,
+                                         uint32_t NumberOfBlocks)
+{
+  SDMMC_DataInitTypeDef config;
+  uint32_t errorstate;
+  uint32_t add = BlockAdd;
+
+  if (NULL == pData)
+  {
+    hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
+    return HAL_ERROR;
+  }
+
+  if (hsd->State == HAL_SD_STATE_READY)
+  {
+    hsd->ErrorCode = HAL_SD_ERROR_NONE;
+
+    if ((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
+    {
+      hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
+      return HAL_ERROR;
+    }
+
+    hsd->State = HAL_SD_STATE_BUSY;
+
+    /* Initialize data control register */
+    hsd->Instance->DCTRL = 0U;
+
+    hsd->pTxBuffPtr = pData;
+    hsd->TxXferSize = BLOCKSIZE * NumberOfBlocks;
+
+    if (hsd->SdCard.CardType != CARD_SDHC_SDXC)
+    {
+      add *= 512U;
+    }
+
+    /* Configure the SD DPSM (Data Path State Machine) */
+    config.DataTimeOut   = SDMMC_DATATIMEOUT;
+    config.DataLength    = BLOCKSIZE * NumberOfBlocks;
+    config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
+    config.TransferDir   = SDMMC_TRANSFER_DIR_TO_CARD;
+    config.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
+    config.DPSM          = SDMMC_DPSM_DISABLE;
+    (void)SDMMC_ConfigData(hsd->Instance, &config);
+
+
+    __SDMMC_CMDTRANS_ENABLE(hsd->Instance);
+
+    hsd->Instance->IDMABASE0 = (uint32_t) pData ;
+    hsd->Instance->IDMACTRL  = SDMMC_ENABLE_IDMA_SINGLE_BUFF;
+
+    /* Write Blocks in Polling mode */
+    if (NumberOfBlocks > 1U)
+    {
+      hsd->Context = (SD_CONTEXT_WRITE_MULTIPLE_BLOCK | SD_CONTEXT_DMA);
+
+      /* Write Multi Block command */
+      errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, add);
+    }
+    else
+    {
+      hsd->Context = (SD_CONTEXT_WRITE_SINGLE_BLOCK | SD_CONTEXT_DMA);
+
+      /* Write Single Block command */
+      errorstate = SDMMC_CmdWriteSingleBlock(hsd->Instance, add);
+    }
+    if (errorstate != HAL_SD_ERROR_NONE)
+    {
+      /* Clear all the static flags */
+      __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+      hsd->ErrorCode |= errorstate;
+      hsd->State = HAL_SD_STATE_READY;
+      hsd->Context = SD_CONTEXT_NONE;
+      return HAL_ERROR;
+    }
+
+    /* Enable transfer interrupts */
+    __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND));
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Erases the specified memory area of the given SD card.
+  * @note   This API should be followed by a check on the card state through
+  *         HAL_SD_GetCardState().
+  * @param  hsd: Pointer to SD handle
+  * @param  BlockStartAdd: Start Block address
+  * @param  BlockEndAdd: End Block address
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint32_t BlockStartAdd, uint32_t BlockEndAdd)
+{
+  uint32_t errorstate;
+  uint32_t start_add = BlockStartAdd;
+  uint32_t end_add = BlockEndAdd;
+
+  if (hsd->State == HAL_SD_STATE_READY)
+  {
+    hsd->ErrorCode = HAL_SD_ERROR_NONE;
+
+    if (end_add < start_add)
+    {
+      hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
+      return HAL_ERROR;
+    }
+
+    if (end_add > (hsd->SdCard.LogBlockNbr))
+    {
+      hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
+      return HAL_ERROR;
+    }
+
+    hsd->State = HAL_SD_STATE_BUSY;
+
+    /* Check if the card command class supports erase command */
+    if (((hsd->SdCard.Class) & SDMMC_CCCC_ERASE) == 0U)
+    {
+      /* Clear all the static flags */
+      __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+      hsd->ErrorCode |= HAL_SD_ERROR_REQUEST_NOT_APPLICABLE;
+      hsd->State = HAL_SD_STATE_READY;
+      return HAL_ERROR;
+    }
+
+    if ((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)
+    {
+      /* Clear all the static flags */
+      __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+      hsd->ErrorCode |= HAL_SD_ERROR_LOCK_UNLOCK_FAILED;
+      hsd->State = HAL_SD_STATE_READY;
+      return HAL_ERROR;
+    }
+
+    /* Get start and end block for high capacity cards */
+    if (hsd->SdCard.CardType != CARD_SDHC_SDXC)
+    {
+      start_add *= 512U;
+      end_add   *= 512U;
+    }
+
+    /* According to sd-card spec 1.0 ERASE_GROUP_START (CMD32) and erase_group_end(CMD33) */
+    if (hsd->SdCard.CardType != CARD_SECURED)
+    {
+      /* Send CMD32 SD_ERASE_GRP_START with argument as addr  */
+      errorstate = SDMMC_CmdSDEraseStartAdd(hsd->Instance, start_add);
+      if (errorstate != HAL_SD_ERROR_NONE)
+      {
+        /* Clear all the static flags */
+        __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+        hsd->ErrorCode |= errorstate;
+        hsd->State = HAL_SD_STATE_READY;
+        return HAL_ERROR;
+      }
+
+      /* Send CMD33 SD_ERASE_GRP_END with argument as addr  */
+      errorstate = SDMMC_CmdSDEraseEndAdd(hsd->Instance, end_add);
+      if (errorstate != HAL_SD_ERROR_NONE)
+      {
+        /* Clear all the static flags */
+        __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+        hsd->ErrorCode |= errorstate;
+        hsd->State = HAL_SD_STATE_READY;
+        return HAL_ERROR;
+      }
+    }
+
+    /* Send CMD38 ERASE */
+    errorstate = SDMMC_CmdErase(hsd->Instance, 0UL);
+    if (errorstate != HAL_SD_ERROR_NONE)
+    {
+      /* Clear all the static flags */
+      __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+      hsd->ErrorCode |= errorstate;
+      hsd->State = HAL_SD_STATE_READY;
+      return HAL_ERROR;
+    }
+
+    hsd->State = HAL_SD_STATE_READY;
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  This function handles SD card interrupt request.
+  * @param  hsd: Pointer to SD handle
+  * @retval None
+  */
+void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd)
+{
+  uint32_t errorstate;
+  uint32_t context = hsd->Context;
+
+  /* Check for SDMMC interrupt flags */
+  if ((__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF) != RESET) && ((context & SD_CONTEXT_IT) != 0U))
+  {
+    SD_Read_IT(hsd);
+  }
+
+  else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DATAEND) != RESET)
+  {
+    __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DATAEND);
+
+    __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND  | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | \
+                        SDMMC_IT_TXUNDERR | SDMMC_IT_RXOVERR  | SDMMC_IT_TXFIFOHE | \
+                        SDMMC_IT_RXFIFOHF);
+
+    __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_IDMABTC);
+    __SDMMC_CMDTRANS_DISABLE(hsd->Instance);
+
+    if ((context & SD_CONTEXT_IT) != 0U)
+    {
+      if (((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U) || ((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U))
+      {
+        errorstate = SDMMC_CmdStopTransfer(hsd->Instance);
+        if (errorstate != HAL_SD_ERROR_NONE)
+        {
+          hsd->ErrorCode |= errorstate;
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+          hsd->ErrorCallback(hsd);
+#else
+          HAL_SD_ErrorCallback(hsd);
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+        }
+      }
+
+      /* Clear all the static flags */
+      __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS);
+
+      hsd->State = HAL_SD_STATE_READY;
+      hsd->Context = SD_CONTEXT_NONE;
+      if (((context & SD_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U))
+      {
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+        hsd->RxCpltCallback(hsd);
+#else
+        HAL_SD_RxCpltCallback(hsd);
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+      }
+      else
+      {
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+        hsd->TxCpltCallback(hsd);
+#else
+        HAL_SD_TxCpltCallback(hsd);
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+      }
+    }
+    else if ((context & SD_CONTEXT_DMA) != 0U)
+    {
+      hsd->Instance->DLEN = 0;
+      hsd->Instance->DCTRL = 0;
+      hsd->Instance->IDMACTRL = SDMMC_DISABLE_IDMA;
+
+      /* Stop Transfer for Write Multi blocks or Read Multi blocks */
+      if (((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U) || ((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U))
+      {
+        errorstate = SDMMC_CmdStopTransfer(hsd->Instance);
+        if (errorstate != HAL_SD_ERROR_NONE)
+        {
+          hsd->ErrorCode |= errorstate;
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+          hsd->ErrorCallback(hsd);
+#else
+          HAL_SD_ErrorCallback(hsd);
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+        }
+      }
+
+      hsd->State = HAL_SD_STATE_READY;
+      hsd->Context = SD_CONTEXT_NONE;
+      if (((context & SD_CONTEXT_WRITE_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U))
+      {
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+        hsd->TxCpltCallback(hsd);
+#else
+        HAL_SD_TxCpltCallback(hsd);
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+      }
+      if (((context & SD_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U))
+      {
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+        hsd->RxCpltCallback(hsd);
+#else
+        HAL_SD_RxCpltCallback(hsd);
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+      }
+    }
+    else
+    {
+      /* Nothing to do */
+    }
+  }
+
+  else if ((__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXFIFOHE) != RESET) && ((context & SD_CONTEXT_IT) != 0U))
+  {
+    SD_Write_IT(hsd);
+  }
+
+  else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_RXOVERR |
+                             SDMMC_FLAG_TXUNDERR) != RESET)
+  {
+    /* Set Error code */
+    if (__HAL_SD_GET_FLAG(hsd, SDMMC_IT_DCRCFAIL) != RESET)
+    {
+      hsd->ErrorCode |= HAL_SD_ERROR_DATA_CRC_FAIL;
+    }
+    if (__HAL_SD_GET_FLAG(hsd, SDMMC_IT_DTIMEOUT) != RESET)
+    {
+      hsd->ErrorCode |= HAL_SD_ERROR_DATA_TIMEOUT;
+    }
+    if (__HAL_SD_GET_FLAG(hsd, SDMMC_IT_RXOVERR) != RESET)
+    {
+      hsd->ErrorCode |= HAL_SD_ERROR_RX_OVERRUN;
+    }
+    if (__HAL_SD_GET_FLAG(hsd, SDMMC_IT_TXUNDERR) != RESET)
+    {
+      hsd->ErrorCode |= HAL_SD_ERROR_TX_UNDERRUN;
+    }
+
+    /* Clear All flags */
+    __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS);
+
+    /* Disable all interrupts */
+    __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | \
+                        SDMMC_IT_TXUNDERR | SDMMC_IT_RXOVERR);
+
+    __SDMMC_CMDTRANS_DISABLE(hsd->Instance);
+    hsd->Instance->DCTRL |= SDMMC_DCTRL_FIFORST;
+    hsd->Instance->CMD |= SDMMC_CMD_CMDSTOP;
+    hsd->ErrorCode |= SDMMC_CmdStopTransfer(hsd->Instance);
+    hsd->Instance->CMD &= ~(SDMMC_CMD_CMDSTOP);
+    __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DABORT);
+
+    if ((context & SD_CONTEXT_IT) != 0U)
+    {
+      /* Set the SD state to ready to be able to start again the process */
+      hsd->State = HAL_SD_STATE_READY;
+      hsd->Context = SD_CONTEXT_NONE;
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+      hsd->ErrorCallback(hsd);
+#else
+      HAL_SD_ErrorCallback(hsd);
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+    }
+    else if ((context & SD_CONTEXT_DMA) != 0U)
+    {
+      if (hsd->ErrorCode != HAL_SD_ERROR_NONE)
+      {
+        /* Disable Internal DMA */
+        __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_IDMABTC);
+        hsd->Instance->IDMACTRL = SDMMC_DISABLE_IDMA;
+
+        /* Set the SD state to ready to be able to start again the process */
+        hsd->State = HAL_SD_STATE_READY;
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+        hsd->ErrorCallback(hsd);
+#else
+        HAL_SD_ErrorCallback(hsd);
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+      }
+    }
+    else
+    {
+      /* Nothing to do */
+    }
+  }
+
+  else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_IDMABTC) != RESET)
+  {
+    __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_IDMABTC);
+    if (READ_BIT(hsd->Instance->IDMACTRL, SDMMC_IDMA_IDMABACT) == 0U)
+    {
+      /* Current buffer is buffer0, Transfer complete for buffer1 */
+      if ((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U)
+      {
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+        hsd->Write_DMADblBuf1CpltCallback(hsd);
+#else
+        HAL_SDEx_Write_DMADoubleBuf1CpltCallback(hsd);
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+      }
+      else /* SD_CONTEXT_READ_MULTIPLE_BLOCK */
+      {
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+        hsd->Read_DMADblBuf1CpltCallback(hsd);
+#else
+        HAL_SDEx_Read_DMADoubleBuf1CpltCallback(hsd);
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+      }
+    }
+    else /* SD_DMA_BUFFER1 */
+    {
+      /* Current buffer is buffer1, Transfer complete for buffer0 */
+      if ((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U)
+      {
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+        hsd->Write_DMADblBuf0CpltCallback(hsd);
+#else
+        HAL_SDEx_Write_DMADoubleBuf0CpltCallback(hsd);
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+      }
+      else /* SD_CONTEXT_READ_MULTIPLE_BLOCK */
+      {
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+        hsd->Read_DMADblBuf0CpltCallback(hsd);
+#else
+        HAL_SDEx_Read_DMADoubleBuf0CpltCallback(hsd);
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+      }
+    }
+  }
+  else
+  {
+    /* Nothing to do */
+  }
+}
+
+/**
+  * @brief return the SD state
+  * @param hsd: Pointer to sd handle
+  * @retval HAL state
+  */
+HAL_SD_StateTypeDef HAL_SD_GetState(SD_HandleTypeDef *hsd)
+{
+  return hsd->State;
+}
+
+/**
+  * @brief  Return the SD error code
+  * @param  hsd : Pointer to a SD_HandleTypeDef structure that contains
+  *              the configuration information.
+  * @retval SD Error Code
+  */
+uint32_t HAL_SD_GetError(SD_HandleTypeDef *hsd)
+{
+  return hsd->ErrorCode;
+}
+
+/**
+  * @brief Tx Transfer completed callbacks
+  * @param hsd: Pointer to SD handle
+  * @retval None
+  */
+__weak void HAL_SD_TxCpltCallback(SD_HandleTypeDef *hsd)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsd);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SD_TxCpltCallback can be implemented in the user file
+   */
+}
+
+/**
+  * @brief Rx Transfer completed callbacks
+  * @param hsd: Pointer SD handle
+  * @retval None
+  */
+__weak void HAL_SD_RxCpltCallback(SD_HandleTypeDef *hsd)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsd);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SD_RxCpltCallback can be implemented in the user file
+   */
+}
+
+/**
+  * @brief SD error callbacks
+  * @param hsd: Pointer SD handle
+  * @retval None
+  */
+__weak void HAL_SD_ErrorCallback(SD_HandleTypeDef *hsd)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsd);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SD_ErrorCallback can be implemented in the user file
+   */
+}
+
+/**
+  * @brief SD Abort callbacks
+  * @param hsd: Pointer SD handle
+  * @retval None
+  */
+__weak void HAL_SD_AbortCallback(SD_HandleTypeDef *hsd)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsd);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SD_AbortCallback can be implemented in the user file
+   */
+}
+
+#if (USE_SD_TRANSCEIVER != 0U)
+/**
+  * @brief  Enable/Disable the SD Transceiver 1.8V Mode Callback.
+  * @param  status: Voltage Switch State
+  * @retval None
+  */
+__weak  void HAL_SD_DriveTransceiver_1_8V_Callback(FlagStatus status)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(status);
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SD_EnableTransceiver could be implemented in the user file
+   */
+}
+#endif /* USE_SD_TRANSCEIVER  */
+
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+/**
+  * @brief  Register a User SD Callback
+  *         To be used instead of the weak (surcharged) predefined callback
+  * @note   The HAL_SD_RegisterCallback() may be called before HAL_SD_Init() in 
+  *         HAL_SD_STATE_RESET to register callbacks for HAL_SD_MSP_INIT_CB_ID 
+  *         and HAL_SD_MSP_DEINIT_CB_ID.
+  * @param hsd : SD handle
+  * @param CallbackID : ID of the callback to be registered
+  *        This parameter can be one of the following values:
+  *          @arg @ref HAL_SD_TX_CPLT_CB_ID                 SD Tx Complete Callback ID
+  *          @arg @ref HAL_SD_RX_CPLT_CB_ID                 SD Rx Complete Callback ID
+  *          @arg @ref HAL_SD_ERROR_CB_ID                   SD Error Callback ID
+  *          @arg @ref HAL_SD_ABORT_CB_ID                   SD Abort Callback ID
+  *          @arg @ref HAL_SD_READ_DMA_DBL_BUF0_CPLT_CB_ID  SD DMA Rx Double buffer 0 Callback ID
+  *          @arg @ref HAL_SD_READ_DMA_DBL_BUF1_CPLT_CB_ID  SD DMA Rx Double buffer 1 Callback ID
+  *          @arg @ref HAL_SD_WRITE_DMA_DBL_BUF0_CPLT_CB_ID SD DMA Tx Double buffer 0 Callback ID
+  *          @arg @ref HAL_SD_WRITE_DMA_DBL_BUF1_CPLT_CB_ID SD DMA Tx Double buffer 1 Callback ID
+  *          @arg @ref HAL_SD_MSP_INIT_CB_ID                SD MspInit Callback ID
+  *          @arg @ref HAL_SD_MSP_DEINIT_CB_ID              SD MspDeInit Callback ID
+  * @param pCallback : pointer to the Callback function
+  * @retval status
+  */
+HAL_StatusTypeDef HAL_SD_RegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef CallbackID,
+                                          pSD_CallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
+    return HAL_ERROR;
+  }
+
+  if (hsd->State == HAL_SD_STATE_READY)
+  {
+    switch (CallbackID)
+    {
+      case HAL_SD_TX_CPLT_CB_ID :
+        hsd->TxCpltCallback = pCallback;
+        break;
+      case HAL_SD_RX_CPLT_CB_ID :
+        hsd->RxCpltCallback = pCallback;
+        break;
+      case HAL_SD_ERROR_CB_ID :
+        hsd->ErrorCallback = pCallback;
+        break;
+      case HAL_SD_ABORT_CB_ID :
+        hsd->AbortCpltCallback = pCallback;
+        break;
+      case HAL_SD_READ_DMA_DBL_BUF0_CPLT_CB_ID :
+        hsd->Read_DMADblBuf0CpltCallback = pCallback;
+        break;
+      case HAL_SD_READ_DMA_DBL_BUF1_CPLT_CB_ID :
+        hsd->Read_DMADblBuf1CpltCallback = pCallback;
+        break;
+      case HAL_SD_WRITE_DMA_DBL_BUF0_CPLT_CB_ID :
+        hsd->Write_DMADblBuf0CpltCallback = pCallback;
+        break;
+      case HAL_SD_WRITE_DMA_DBL_BUF1_CPLT_CB_ID :
+        hsd->Write_DMADblBuf1CpltCallback = pCallback;
+        break;
+      case HAL_SD_MSP_INIT_CB_ID :
+        hsd->MspInitCallback = pCallback;
+        break;
+      case HAL_SD_MSP_DEINIT_CB_ID :
+        hsd->MspDeInitCallback = pCallback;
+        break;
+      default :
+        /* Update the error code */
+        hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
+        /* update return status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (hsd->State == HAL_SD_STATE_RESET)
+  {
+    switch (CallbackID)
+    {
+      case HAL_SD_MSP_INIT_CB_ID :
+        hsd->MspInitCallback = pCallback;
+        break;
+      case HAL_SD_MSP_DEINIT_CB_ID :
+        hsd->MspDeInitCallback = pCallback;
+        break;
+      default :
+        /* Update the error code */
+        hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
+        /* update return status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
+    /* update return status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Unregister a User SD Callback
+  *         SD Callback is redirected to the weak (surcharged) predefined callback
+  * @note   The HAL_SD_UnRegisterCallback() may be called before HAL_SD_Init() in 
+  *         HAL_SD_STATE_RESET to register callbacks for HAL_SD_MSP_INIT_CB_ID 
+  *         and HAL_SD_MSP_DEINIT_CB_ID.
+  * @param hsd : SD handle
+  * @param CallbackID : ID of the callback to be unregistered
+  *        This parameter can be one of the following values:
+  *          @arg @ref HAL_SD_TX_CPLT_CB_ID                 SD Tx Complete Callback ID
+  *          @arg @ref HAL_SD_RX_CPLT_CB_ID                 SD Rx Complete Callback ID
+  *          @arg @ref HAL_SD_ERROR_CB_ID                   SD Error Callback ID
+  *          @arg @ref HAL_SD_ABORT_CB_ID                   SD Abort Callback ID
+  *          @arg @ref HAL_SD_READ_DMA_DBL_BUF0_CPLT_CB_ID  SD DMA Rx Double buffer 0 Callback ID
+  *          @arg @ref HAL_SD_READ_DMA_DBL_BUF1_CPLT_CB_ID  SD DMA Rx Double buffer 1 Callback ID
+  *          @arg @ref HAL_SD_WRITE_DMA_DBL_BUF0_CPLT_CB_ID SD DMA Tx Double buffer 0 Callback ID
+  *          @arg @ref HAL_SD_WRITE_DMA_DBL_BUF1_CPLT_CB_ID SD DMA Tx Double buffer 1 Callback ID
+  *          @arg @ref HAL_SD_MSP_INIT_CB_ID                SD MspInit Callback ID
+  *          @arg @ref HAL_SD_MSP_DEINIT_CB_ID              SD MspDeInit Callback ID
+  * @retval status
+  */
+HAL_StatusTypeDef HAL_SD_UnRegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef CallbackID)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (hsd->State == HAL_SD_STATE_READY)
+  {
+    switch (CallbackID)
+    {
+      case HAL_SD_TX_CPLT_CB_ID :
+        hsd->TxCpltCallback = HAL_SD_TxCpltCallback;
+        break;
+      case HAL_SD_RX_CPLT_CB_ID :
+        hsd->RxCpltCallback = HAL_SD_RxCpltCallback;
+        break;
+      case HAL_SD_ERROR_CB_ID :
+        hsd->ErrorCallback = HAL_SD_ErrorCallback;
+        break;
+      case HAL_SD_ABORT_CB_ID :
+        hsd->AbortCpltCallback = HAL_SD_AbortCallback;
+        break;
+      case HAL_SD_READ_DMA_DBL_BUF0_CPLT_CB_ID :
+        hsd->Read_DMADblBuf0CpltCallback = HAL_SDEx_Read_DMADoubleBuf0CpltCallback;
+        break;
+      case HAL_SD_READ_DMA_DBL_BUF1_CPLT_CB_ID :
+        hsd->Read_DMADblBuf1CpltCallback = HAL_SDEx_Read_DMADoubleBuf1CpltCallback;
+        break;
+      case HAL_SD_WRITE_DMA_DBL_BUF0_CPLT_CB_ID :
+        hsd->Write_DMADblBuf0CpltCallback = HAL_SDEx_Write_DMADoubleBuf0CpltCallback;
+        break;
+      case HAL_SD_WRITE_DMA_DBL_BUF1_CPLT_CB_ID :
+        hsd->Write_DMADblBuf1CpltCallback = HAL_SDEx_Write_DMADoubleBuf1CpltCallback;
+        break;
+      case HAL_SD_MSP_INIT_CB_ID :
+        hsd->MspInitCallback = HAL_SD_MspInit;
+        break;
+      case HAL_SD_MSP_DEINIT_CB_ID :
+        hsd->MspDeInitCallback = HAL_SD_MspDeInit;
+        break;
+      default :
+        /* Update the error code */
+        hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
+        /* update return status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (hsd->State == HAL_SD_STATE_RESET)
+  {
+    switch (CallbackID)
+    {
+      case HAL_SD_MSP_INIT_CB_ID :
+        hsd->MspInitCallback = HAL_SD_MspInit;
+        break;
+      case HAL_SD_MSP_DEINIT_CB_ID :
+        hsd->MspDeInitCallback = HAL_SD_MspDeInit;
+        break;
+      default :
+        /* Update the error code */
+        hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
+        /* update return status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
+    /* update return status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+#if (USE_SD_TRANSCEIVER != 0U)
+/**
+  * @brief  Register a User SD Transceiver Callback
+  *         To be used instead of the weak (surcharged) predefined callback
+  * @param hsd : SD handle
+  * @param pCallback : pointer to the Callback function
+  * @retval status
+  */
+HAL_StatusTypeDef HAL_SD_RegisterTransceiverCallback(SD_HandleTypeDef *hsd, pSD_TransceiverCallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
+    return HAL_ERROR;
+  }
+
+  /* Process locked */
+  __HAL_LOCK(hsd);
+
+  if (hsd->State == HAL_SD_STATE_READY)
+  {
+    hsd->DriveTransceiver_1_8V_Callback = pCallback;
+  }
+  else
+  {
+    /* Update the error code */
+    hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
+    /* update return status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hsd);
+  return status;
+}
+
+/**
+  * @brief  Unregister a User SD Transceiver Callback
+  *         SD Callback is redirected to the weak (surcharged) predefined callback
+  * @param hsd : SD handle
+  * @retval status
+  */
+HAL_StatusTypeDef HAL_SD_UnRegisterTransceiverCallback(SD_HandleTypeDef *hsd)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process locked */
+  __HAL_LOCK(hsd);
+
+  if (hsd->State == HAL_SD_STATE_READY)
+  {
+    hsd->DriveTransceiver_1_8V_Callback = HAL_SD_DriveTransceiver_1_8V_Callback;
+  }
+  else
+  {
+    /* Update the error code */
+    hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
+    /* update return status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hsd);
+  return status;
+}
+#endif /* USE_SD_TRANSCEIVER */
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/** @addtogroup SD_Exported_Functions_Group3
+  *  @brief   management functions
+  *
+@verbatim
+  ==============================================================================
+                      ##### Peripheral Control functions #####
+  ==============================================================================
+  [..]
+    This subsection provides a set of functions allowing to control the SD card
+    operations and get the related information
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Returns information the information of the card which are stored on
+  *         the CID register.
+  * @param  hsd: Pointer to SD handle
+  * @param  pCID: Pointer to a HAL_SD_CardCIDTypeDef structure that
+  *         contains all CID register parameters
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SD_GetCardCID(SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypeDef *pCID)
+{
+  pCID->ManufacturerID = (uint8_t)((hsd->CID[0] & 0xFF000000U) >> 24U);
+
+  pCID->OEM_AppliID = (uint16_t)((hsd->CID[0] & 0x00FFFF00U) >> 8U);
+
+  pCID->ProdName1 = (((hsd->CID[0] & 0x000000FFU) << 24U) | ((hsd->CID[1] & 0xFFFFFF00U) >> 8U));
+
+  pCID->ProdName2 = (uint8_t)(hsd->CID[1] & 0x000000FFU);
+
+  pCID->ProdRev = (uint8_t)((hsd->CID[2] & 0xFF000000U) >> 24U);
+
+  pCID->ProdSN = (((hsd->CID[2] & 0x00FFFFFFU) << 8U) | ((hsd->CID[3] & 0xFF000000U) >> 24U));
+
+  pCID->Reserved1 = (uint8_t)((hsd->CID[3] & 0x00F00000U) >> 20U);
+
+  pCID->ManufactDate = (uint16_t)((hsd->CID[3] & 0x000FFF00U) >> 8U);
+
+  pCID->CID_CRC = (uint8_t)((hsd->CID[3] & 0x000000FEU) >> 1U);
+
+  pCID->Reserved2 = 1U;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Returns information the information of the card which are stored on
+  *         the CSD register.
+  * @param  hsd: Pointer to SD handle
+  * @param  pCSD: Pointer to a HAL_SD_CardCSDTypeDef structure that
+  *         contains all CSD register parameters
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SD_GetCardCSD(SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypeDef *pCSD)
+{
+  pCSD->CSDStruct = (uint8_t)((hsd->CSD[0] & 0xC0000000U) >> 30U);
+
+  pCSD->SysSpecVersion = (uint8_t)((hsd->CSD[0] & 0x3C000000U) >> 26U);
+
+  pCSD->Reserved1 = (uint8_t)((hsd->CSD[0] & 0x03000000U) >> 24U);
+
+  pCSD->TAAC = (uint8_t)((hsd->CSD[0] & 0x00FF0000U) >> 16U);
+
+  pCSD->NSAC = (uint8_t)((hsd->CSD[0] & 0x0000FF00U) >> 8U);
+
+  pCSD->MaxBusClkFrec = (uint8_t)(hsd->CSD[0] & 0x000000FFU);
+
+  pCSD->CardComdClasses = (uint16_t)((hsd->CSD[1] & 0xFFF00000U) >> 20U);
+
+  pCSD->RdBlockLen = (uint8_t)((hsd->CSD[1] & 0x000F0000U) >> 16U);
+
+  pCSD->PartBlockRead   = (uint8_t)((hsd->CSD[1] & 0x00008000U) >> 15U);
+
+  pCSD->WrBlockMisalign = (uint8_t)((hsd->CSD[1] & 0x00004000U) >> 14U);
+
+  pCSD->RdBlockMisalign = (uint8_t)((hsd->CSD[1] & 0x00002000U) >> 13U);
+
+  pCSD->DSRImpl = (uint8_t)((hsd->CSD[1] & 0x00001000U) >> 12U);
+
+  pCSD->Reserved2 = 0U; /*!< Reserved */
+
+  if (hsd->SdCard.CardType == CARD_SDSC)
+  {
+    pCSD->DeviceSize = (((hsd->CSD[1] & 0x000003FFU) << 2U) | ((hsd->CSD[2] & 0xC0000000U) >> 30U));
+
+    pCSD->MaxRdCurrentVDDMin = (uint8_t)((hsd->CSD[2] & 0x38000000U) >> 27U);
+
+    pCSD->MaxRdCurrentVDDMax = (uint8_t)((hsd->CSD[2] & 0x07000000U) >> 24U);
+
+    pCSD->MaxWrCurrentVDDMin = (uint8_t)((hsd->CSD[2] & 0x00E00000U) >> 21U);
+
+    pCSD->MaxWrCurrentVDDMax = (uint8_t)((hsd->CSD[2] & 0x001C0000U) >> 18U);
+
+    pCSD->DeviceSizeMul = (uint8_t)((hsd->CSD[2] & 0x00038000U) >> 15U);
+
+    hsd->SdCard.BlockNbr  = (pCSD->DeviceSize + 1U) ;
+    hsd->SdCard.BlockNbr *= (1UL << ((pCSD->DeviceSizeMul & 0x07U) + 2U));
+    hsd->SdCard.BlockSize = (1UL << (pCSD->RdBlockLen & 0x0FU));
+
+    hsd->SdCard.LogBlockNbr = (hsd->SdCard.BlockNbr) * ((hsd->SdCard.BlockSize) / 512U);
+    hsd->SdCard.LogBlockSize = 512U;
+  }
+  else if (hsd->SdCard.CardType == CARD_SDHC_SDXC)
+  {
+    /* Byte 7 */
+    pCSD->DeviceSize = (((hsd->CSD[1] & 0x0000003FU) << 16U) | ((hsd->CSD[2] & 0xFFFF0000U) >> 16U));
+
+    hsd->SdCard.BlockNbr = ((pCSD->DeviceSize + 1U) * 1024U);
+    hsd->SdCard.LogBlockNbr = hsd->SdCard.BlockNbr;
+    hsd->SdCard.BlockSize = 512U;
+    hsd->SdCard.LogBlockSize = hsd->SdCard.BlockSize;
+  }
+  else
+  {
+    /* Clear all the static flags */
+    __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+    hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
+    hsd->State = HAL_SD_STATE_READY;
+    return HAL_ERROR;
+  }
+
+  pCSD->EraseGrSize = (uint8_t)((hsd->CSD[2] & 0x00004000U) >> 14U);
+
+  pCSD->EraseGrMul = (uint8_t)((hsd->CSD[2] & 0x00003F80U) >> 7U);
+
+  pCSD->WrProtectGrSize = (uint8_t)(hsd->CSD[2] & 0x0000007FU);
+
+  pCSD->WrProtectGrEnable = (uint8_t)((hsd->CSD[3] & 0x80000000U) >> 31U);
+
+  pCSD->ManDeflECC = (uint8_t)((hsd->CSD[3] & 0x60000000U) >> 29U);
+
+  pCSD->WrSpeedFact = (uint8_t)((hsd->CSD[3] & 0x1C000000U) >> 26U);
+
+  pCSD->MaxWrBlockLen = (uint8_t)((hsd->CSD[3] & 0x03C00000U) >> 22U);
+
+  pCSD->WriteBlockPaPartial = (uint8_t)((hsd->CSD[3] & 0x00200000U) >> 21U);
+
+  pCSD->Reserved3 = 0;
+
+  pCSD->ContentProtectAppli = (uint8_t)((hsd->CSD[3] & 0x00010000U) >> 16U);
+
+  pCSD->FileFormatGroup = (uint8_t)((hsd->CSD[3] & 0x00008000U) >> 15U);
+
+  pCSD->CopyFlag = (uint8_t)((hsd->CSD[3] & 0x00004000U) >> 14U);
+
+  pCSD->PermWrProtect = (uint8_t)((hsd->CSD[3] & 0x00002000U) >> 13U);
+
+  pCSD->TempWrProtect = (uint8_t)((hsd->CSD[3] & 0x00001000U) >> 12U);
+
+  pCSD->FileFormat = (uint8_t)((hsd->CSD[3] & 0x00000C00U) >> 10U);
+
+  pCSD->ECC = (uint8_t)((hsd->CSD[3] & 0x00000300U) >> 8U);
+
+  pCSD->CSD_CRC = (uint8_t)((hsd->CSD[3] & 0x000000FEU) >> 1U);
+
+  pCSD->Reserved4 = 1;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Gets the SD status info.( shall be called if there is no SD transaction ongoing )
+  * @param  hsd: Pointer to SD handle
+  * @param  pStatus: Pointer to the HAL_SD_CardStatusTypeDef structure that
+  *         will contain the SD card status information
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypeDef *pStatus)
+{
+  uint32_t sd_status[16];
+  uint32_t errorstate;
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (hsd->State == HAL_SD_STATE_BUSY)
+  {
+    return HAL_ERROR;
+  }
+
+  errorstate = SD_SendSDStatus(hsd, sd_status);
+  if (errorstate != HAL_SD_ERROR_NONE)
+  {
+    /* Clear all the static flags */
+    __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+    hsd->ErrorCode |= errorstate;
+    hsd->State = HAL_SD_STATE_READY;
+    status = HAL_ERROR;
+  }
+  else
+  {
+    pStatus->DataBusWidth = (uint8_t)((sd_status[0] & 0xC0U) >> 6U);
+
+    pStatus->SecuredMode = (uint8_t)((sd_status[0] & 0x20U) >> 5U);
+
+    pStatus->CardType = (uint16_t)(((sd_status[0] & 0x00FF0000U) >> 8U) | ((sd_status[0] & 0xFF000000U) >> 24U));
+
+    pStatus->ProtectedAreaSize = (((sd_status[1] & 0xFFU) << 24U)    | ((sd_status[1] & 0xFF00U) << 8U) |
+                                  ((sd_status[1] & 0xFF0000U) >> 8U) | ((sd_status[1] & 0xFF000000U) >> 24U));
+
+    pStatus->SpeedClass = (uint8_t)(sd_status[2] & 0xFFU);
+
+    pStatus->PerformanceMove = (uint8_t)((sd_status[2] & 0xFF00U) >> 8U);
+
+    pStatus->AllocationUnitSize = (uint8_t)((sd_status[2] & 0xF00000U) >> 20U);
+
+    pStatus->EraseSize = (uint16_t)(((sd_status[2] & 0xFF000000U) >> 16U) | (sd_status[3] & 0xFFU));
+
+    pStatus->EraseTimeout = (uint8_t)((sd_status[3] & 0xFC00U) >> 10U);
+
+    pStatus->EraseOffset = (uint8_t)((sd_status[3] & 0x0300U) >> 8U);
+
+    pStatus->UhsSpeedGrade = (uint8_t)((sd_status[3] & 0x00F0U) >> 4U);
+    pStatus->UhsAllocationUnitSize = (uint8_t)(sd_status[3] & 0x000FU) ;
+    pStatus->VideoSpeedClass = (uint8_t)((sd_status[4] & 0xFF000000U) >> 24U);
+  }
+
+  /* Set Block Size for Card */
+  errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
+  if (errorstate != HAL_SD_ERROR_NONE)
+  {
+    /* Clear all the static flags */
+    __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+    hsd->ErrorCode = errorstate;
+    hsd->State = HAL_SD_STATE_READY;
+    status = HAL_ERROR;
+  }
+
+
+  return status;
+}
+
+/**
+  * @brief  Gets the SD card info.
+  * @param  hsd: Pointer to SD handle
+  * @param  pCardInfo: Pointer to the HAL_SD_CardInfoTypeDef structure that
+  *         will contain the SD card status information
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SD_GetCardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypeDef *pCardInfo)
+{
+  pCardInfo->CardType     = (uint32_t)(hsd->SdCard.CardType);
+  pCardInfo->CardVersion  = (uint32_t)(hsd->SdCard.CardVersion);
+  pCardInfo->Class        = (uint32_t)(hsd->SdCard.Class);
+  pCardInfo->RelCardAdd   = (uint32_t)(hsd->SdCard.RelCardAdd);
+  pCardInfo->BlockNbr     = (uint32_t)(hsd->SdCard.BlockNbr);
+  pCardInfo->BlockSize    = (uint32_t)(hsd->SdCard.BlockSize);
+  pCardInfo->LogBlockNbr  = (uint32_t)(hsd->SdCard.LogBlockNbr);
+  pCardInfo->LogBlockSize = (uint32_t)(hsd->SdCard.LogBlockSize);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enables wide bus operation for the requested card if supported by
+  *         card.
+  * @param  hsd: Pointer to SD handle
+  * @param  WideMode: Specifies the SD card wide bus mode
+  *          This parameter can be one of the following values:
+  *            @arg SDMMC_BUS_WIDE_8B: 8-bit data transfer
+  *            @arg SDMMC_BUS_WIDE_4B: 4-bit data transfer
+  *            @arg SDMMC_BUS_WIDE_1B: 1-bit data transfer
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SD_ConfigWideBusOperation(SD_HandleTypeDef *hsd, uint32_t WideMode)
+{
+  SDMMC_InitTypeDef Init;
+  uint32_t errorstate;
+  uint32_t sdmmc_clk;
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_SDMMC_BUS_WIDE(WideMode));
+
+  /* Change State */
+  hsd->State = HAL_SD_STATE_BUSY;
+
+  if (hsd->SdCard.CardType != CARD_SECURED)
+  {
+    if (WideMode == SDMMC_BUS_WIDE_8B)
+    {
+      hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
+    }
+    else if (WideMode == SDMMC_BUS_WIDE_4B)
+    {
+      errorstate = SD_WideBus_Enable(hsd);
+
+      hsd->ErrorCode |= errorstate;
+    }
+    else if (WideMode == SDMMC_BUS_WIDE_1B)
+    {
+      errorstate = SD_WideBus_Disable(hsd);
+
+      hsd->ErrorCode |= errorstate;
+    }
+    else
+    {
+      /* WideMode is not a valid argument*/
+      hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
+    }
+  }
+  else
+  {
+    /* SD Card does not support this feature */
+    hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
+  }
+
+  if (hsd->ErrorCode != HAL_SD_ERROR_NONE)
+  {
+    /* Clear all the static flags */
+    __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+    status = HAL_ERROR;
+  }
+  else
+  {
+    sdmmc_clk     = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SDMMC);
+    if (sdmmc_clk != 0U)
+    {
+      /* Configure the SDMMC peripheral */
+      Init.ClockEdge           = hsd->Init.ClockEdge;
+      Init.ClockPowerSave      = hsd->Init.ClockPowerSave;
+      Init.BusWide             = WideMode;
+      Init.HardwareFlowControl = hsd->Init.HardwareFlowControl;
+
+      /* Check if user Clock div < Normal speed 25Mhz, no change in Clockdiv */
+      if (hsd->Init.ClockDiv >= (sdmmc_clk / (2U * SD_NORMAL_SPEED_FREQ)))
+      {
+        Init.ClockDiv = hsd->Init.ClockDiv;
+      }
+      else if (hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED)
+      {
+        /* UltraHigh speed SD card,user Clock div */
+        Init.ClockDiv = hsd->Init.ClockDiv;
+      }
+      else if (hsd->SdCard.CardSpeed == CARD_HIGH_SPEED)
+      {
+        /* High speed SD card, Max Frequency = 50Mhz */
+        if (hsd->Init.ClockDiv == 0U)
+        {
+          if (sdmmc_clk > SD_HIGH_SPEED_FREQ)
+          {
+            Init.ClockDiv = sdmmc_clk / (2U * SD_HIGH_SPEED_FREQ);
+          }
+          else
+          {
+            Init.ClockDiv = hsd->Init.ClockDiv;
+          }
+        }
+        else
+        {
+          if ((sdmmc_clk / (2U * hsd->Init.ClockDiv)) > SD_HIGH_SPEED_FREQ)
+          {
+            Init.ClockDiv = sdmmc_clk / (2U * SD_HIGH_SPEED_FREQ);
+          }
+          else
+          {
+            Init.ClockDiv = hsd->Init.ClockDiv;
+          }
+        }
+      }
+      else
+      {
+        /* No High speed SD card, Max Frequency = 25Mhz */
+        if (hsd->Init.ClockDiv == 0U)
+        {
+          if (sdmmc_clk > SD_NORMAL_SPEED_FREQ)
+          {
+            Init.ClockDiv = sdmmc_clk / (2U * SD_NORMAL_SPEED_FREQ);
+          }
+          else
+          {
+            Init.ClockDiv = hsd->Init.ClockDiv;
+          }
+        }
+        else
+        {
+          if ((sdmmc_clk / (2U * hsd->Init.ClockDiv)) > SD_NORMAL_SPEED_FREQ)
+          {
+            Init.ClockDiv = sdmmc_clk / (2U * SD_NORMAL_SPEED_FREQ);
+          }
+          else
+          {
+            Init.ClockDiv = hsd->Init.ClockDiv;
+          }
+        }
+      }
+
+#if (USE_SD_TRANSCEIVER != 0U)
+      Init.TranceiverPresent = hsd->Init.TranceiverPresent;
+#endif /* USE_SD_TRANSCEIVER */
+
+      (void)SDMMC_Init(hsd->Instance, Init);
+    }
+    else
+    {
+      hsd->ErrorCode |= SDMMC_ERROR_INVALID_PARAMETER;
+      status = HAL_ERROR;
+    }
+  }
+
+  /* Set Block Size for Card */
+  errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
+  if (errorstate != HAL_SD_ERROR_NONE)
+  {
+    /* Clear all the static flags */
+    __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+    hsd->ErrorCode |= errorstate;
+    status = HAL_ERROR;
+  }
+
+  /* Change State */
+  hsd->State = HAL_SD_STATE_READY;
+
+  return status;
+}
+
+/**
+  * @brief  Configure the speed bus mode
+  * @param  hsd: Pointer to the SD handle
+  * @param  SpeedMode: Specifies the SD card speed bus mode
+  *          This parameter can be one of the following values:
+  *            @arg SDMMC_SPEED_MODE_AUTO: Max speed mode supported by the card
+  *            @arg SDMMC_SPEED_MODE_DEFAULT: Default Speed/SDR12 mode
+  *            @arg SDMMC_SPEED_MODE_HIGH: High Speed/SDR25 mode
+  *            @arg SDMMC_SPEED_MODE_ULTRA: Ultra high speed mode
+  * @retval HAL status
+  */
+
+HAL_StatusTypeDef HAL_SD_ConfigSpeedBusOperation(SD_HandleTypeDef *hsd, uint32_t SpeedMode)
+{
+  uint32_t tickstart;
+  uint32_t errorstate;
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_SDMMC_SPEED_MODE(SpeedMode));
+  /* Change State */
+  hsd->State = HAL_SD_STATE_BUSY;
+
+#if (USE_SD_TRANSCEIVER != 0U)
+  if (hsd->Init.TranceiverPresent == SDMMC_TRANSCEIVER_PRESENT)
+  {
+    switch (SpeedMode)
+    {
+      case SDMMC_SPEED_MODE_AUTO:
+      {
+        if ((hsd->SdCard.CardSpeed  == CARD_ULTRA_HIGH_SPEED) ||
+            (hsd->SdCard.CardType == CARD_SDHC_SDXC))
+        {
+          hsd->Instance->CLKCR |= SDMMC_CLKCR_BUSSPEED;
+          /* Enable Ultra High Speed */
+          if (SD_UltraHighSpeed(hsd, SDMMC_SDR104_SWITCH_PATTERN) != HAL_SD_ERROR_NONE)
+          {
+            if (SD_SwitchSpeed(hsd, SDMMC_SDR25_SWITCH_PATTERN) != HAL_SD_ERROR_NONE)
+            {
+              hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
+              status = HAL_ERROR;
+            }
+          }
+        }
+        else if (hsd->SdCard.CardSpeed  == CARD_HIGH_SPEED)
+        {
+          /* Enable High Speed */
+          if (SD_SwitchSpeed(hsd, SDMMC_SDR25_SWITCH_PATTERN) != HAL_SD_ERROR_NONE)
+          {
+            hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
+            status = HAL_ERROR;
+          }
+        }
+        else
+        {
+          /*Nothing to do, Use defaultSpeed */
+        }
+        break;
+      }
+      case SDMMC_SPEED_MODE_ULTRA_SDR104:
+      {
+        if ((hsd->SdCard.CardSpeed  == CARD_ULTRA_HIGH_SPEED) ||
+            (hsd->SdCard.CardType == CARD_SDHC_SDXC))
+        {
+          /* Enable UltraHigh Speed */
+          if (SD_UltraHighSpeed(hsd, SDMMC_SDR104_SWITCH_PATTERN) != HAL_SD_ERROR_NONE)
+          {
+            hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
+            status = HAL_ERROR;
+          }
+          hsd->Instance->CLKCR |= SDMMC_CLKCR_BUSSPEED;
+        }
+        else
+        {
+          hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
+          status = HAL_ERROR;
+        }
+        break;
+      }
+      case SDMMC_SPEED_MODE_ULTRA_SDR50:
+      {
+        if ((hsd->SdCard.CardSpeed  == CARD_ULTRA_HIGH_SPEED) ||
+            (hsd->SdCard.CardType == CARD_SDHC_SDXC))
+        {
+          /* Enable UltraHigh Speed */
+          if (SD_UltraHighSpeed(hsd, SDMMC_SDR50_SWITCH_PATTERN) != HAL_SD_ERROR_NONE)
+          {
+            hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
+            status = HAL_ERROR;
+          }
+          hsd->Instance->CLKCR |= SDMMC_CLKCR_BUSSPEED;
+        }
+        else
+        {
+          hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
+          status = HAL_ERROR;
+        }
+        break;
+      }
+      case SDMMC_SPEED_MODE_DDR:
+      {
+        if ((hsd->SdCard.CardSpeed  == CARD_ULTRA_HIGH_SPEED) ||
+            (hsd->SdCard.CardType == CARD_SDHC_SDXC))
+        {
+          /* Enable DDR Mode*/
+          if (SD_DDR_Mode(hsd) != HAL_SD_ERROR_NONE)
+          {
+            hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
+            status = HAL_ERROR;
+          }
+          hsd->Instance->CLKCR |=  SDMMC_CLKCR_BUSSPEED | SDMMC_CLKCR_DDR;
+        }
+        else
+        {
+          hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
+          status = HAL_ERROR;
+        }
+        break;
+      }
+      case SDMMC_SPEED_MODE_HIGH:
+      {
+        if ((hsd->SdCard.CardSpeed  == CARD_ULTRA_HIGH_SPEED) ||
+            (hsd->SdCard.CardSpeed  == CARD_HIGH_SPEED) ||
+            (hsd->SdCard.CardType == CARD_SDHC_SDXC))
+        {
+          /* Enable High Speed */
+          if (SD_SwitchSpeed(hsd, SDMMC_SDR25_SWITCH_PATTERN) != HAL_SD_ERROR_NONE)
+          {
+            hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
+            status = HAL_ERROR;
+          }
+        }
+        else
+        {
+          hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
+          status = HAL_ERROR;
+        }
+        break;
+      }
+      case SDMMC_SPEED_MODE_DEFAULT:
+      {
+        /* Switch to default Speed */
+        if (SD_SwitchSpeed(hsd, SDMMC_SDR12_SWITCH_PATTERN) != HAL_SD_ERROR_NONE)
+        {
+          hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
+          status = HAL_ERROR;
+        }
+
+        break;
+      }
+      default:
+        hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
+        status = HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    switch (SpeedMode)
+    {
+      case SDMMC_SPEED_MODE_AUTO:
+      {
+        if ((hsd->SdCard.CardSpeed  == CARD_ULTRA_HIGH_SPEED) ||
+            (hsd->SdCard.CardSpeed  == CARD_HIGH_SPEED) ||
+            (hsd->SdCard.CardType == CARD_SDHC_SDXC))
+        {
+          /* Enable High Speed */
+          if (SD_SwitchSpeed(hsd, SDMMC_SDR25_SWITCH_PATTERN) != HAL_SD_ERROR_NONE)
+          {
+            hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
+            status = HAL_ERROR;
+          }
+        }
+        else
+        {
+          /*Nothing to do, Use defaultSpeed */
+        }
+        break;
+      }
+      case SDMMC_SPEED_MODE_HIGH:
+      {
+        if ((hsd->SdCard.CardSpeed  == CARD_ULTRA_HIGH_SPEED) ||
+            (hsd->SdCard.CardSpeed  == CARD_HIGH_SPEED) ||
+            (hsd->SdCard.CardType == CARD_SDHC_SDXC))
+        {
+          /* Enable High Speed */
+          if (SD_SwitchSpeed(hsd, SDMMC_SDR25_SWITCH_PATTERN) != HAL_SD_ERROR_NONE)
+          {
+            hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
+            status = HAL_ERROR;
+          }
+        }
+        else
+        {
+          hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
+          status = HAL_ERROR;
+        }
+        break;
+      }
+      case SDMMC_SPEED_MODE_DEFAULT:
+      {
+        /* Switch to default Speed */
+        if (SD_SwitchSpeed(hsd, SDMMC_SDR12_SWITCH_PATTERN) != HAL_SD_ERROR_NONE)
+        {
+          hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
+          status = HAL_ERROR;
+        }
+
+        break;
+      }
+      case SDMMC_SPEED_MODE_ULTRA: /*not valid without transceiver*/
+      default:
+        hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
+        status = HAL_ERROR;
+        break;
+    }
+  }
+#else
+  switch (SpeedMode)
+  {
+    case SDMMC_SPEED_MODE_AUTO:
+    {
+      if ((hsd->SdCard.CardSpeed  == CARD_ULTRA_HIGH_SPEED) ||
+          (hsd->SdCard.CardSpeed  == CARD_HIGH_SPEED) ||
+          (hsd->SdCard.CardType == CARD_SDHC_SDXC))
+      {
+        /* Enable High Speed */
+        if (SD_SwitchSpeed(hsd, SDMMC_SDR25_SWITCH_PATTERN) != HAL_SD_ERROR_NONE)
+        {
+          hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
+          status = HAL_ERROR;
+        }
+      }
+      else
+      {
+        /*Nothing to do, Use defaultSpeed */
+      }
+      break;
+    }
+    case SDMMC_SPEED_MODE_HIGH:
+    {
+      if ((hsd->SdCard.CardSpeed  == CARD_ULTRA_HIGH_SPEED) ||
+          (hsd->SdCard.CardSpeed  == CARD_HIGH_SPEED) ||
+          (hsd->SdCard.CardType == CARD_SDHC_SDXC))
+      {
+        /* Enable High Speed */
+        if (SD_SwitchSpeed(hsd, SDMMC_SDR25_SWITCH_PATTERN) != HAL_SD_ERROR_NONE)
+        {
+          hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
+          status = HAL_ERROR;
+        }
+      }
+      else
+      {
+        hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
+        status = HAL_ERROR;
+      }
+      break;
+    }
+    case SDMMC_SPEED_MODE_DEFAULT:
+    {
+      /* Switch to default Speed */
+      if (SD_SwitchSpeed(hsd, SDMMC_SDR12_SWITCH_PATTERN) != HAL_SD_ERROR_NONE)
+      {
+        hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
+        status = HAL_ERROR;
+      }
+
+      break;
+    }
+    case SDMMC_SPEED_MODE_ULTRA: /*not valid without transceiver*/
+    default:
+      hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
+      status = HAL_ERROR;
+      break;
+  }
+#endif /* USE_SD_TRANSCEIVER */
+
+  /* Verify that SD card is ready to use after Speed mode switch*/
+  tickstart = HAL_GetTick();
+  while ((HAL_SD_GetCardState(hsd) != HAL_SD_CARD_TRANSFER))
+  {
+    if ((HAL_GetTick() - tickstart) >=  SDMMC_DATATIMEOUT)
+    {
+      hsd->ErrorCode = HAL_SD_ERROR_TIMEOUT;
+      hsd->State = HAL_SD_STATE_READY;
+      return HAL_TIMEOUT;
+    }
+  }
+
+  /* Set Block Size for Card */
+  errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
+  if (errorstate != HAL_SD_ERROR_NONE)
+  {
+    /* Clear all the static flags */
+    __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+    hsd->ErrorCode |= errorstate;
+    status = HAL_ERROR;
+  }
+
+  /* Change State */
+  hsd->State = HAL_SD_STATE_READY;
+  return status;
+}
+
+/**
+  * @brief  Gets the current sd card data state.
+  * @param  hsd: pointer to SD handle
+  * @retval Card state
+  */
+HAL_SD_CardStateTypeDef HAL_SD_GetCardState(SD_HandleTypeDef *hsd)
+{
+  uint32_t cardstate;
+  uint32_t errorstate;
+  uint32_t resp1 = 0;
+
+  errorstate = SD_SendStatus(hsd, &resp1);
+  if (errorstate != HAL_SD_ERROR_NONE)
+  {
+    hsd->ErrorCode |= errorstate;
+  }
+
+  cardstate = ((resp1 >> 9U) & 0x0FU);
+
+  return (HAL_SD_CardStateTypeDef)cardstate;
+}
+
+/**
+  * @brief  Abort the current transfer and disable the SD.
+  * @param  hsd: pointer to a SD_HandleTypeDef structure that contains
+  *                the configuration information for SD module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SD_Abort(SD_HandleTypeDef *hsd)
+{
+  uint32_t error_code;
+  uint32_t tickstart;
+
+  if (hsd->State == HAL_SD_STATE_BUSY)
+  {
+    /* DIsable All interrupts */
+    __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | \
+                         SDMMC_IT_TXUNDERR | SDMMC_IT_RXOVERR);
+    __SDMMC_CMDTRANS_DISABLE(hsd->Instance);
+
+    /*we will send the CMD12 in all cases in order to stop the data transfers*/
+    /*In case the data transfer just finished , the external memory will not respond and will return HAL_SD_ERROR_CMD_RSP_TIMEOUT*/
+    /*In case the data transfer aborted , the external memory will respond and will return HAL_SD_ERROR_NONE*/
+    /*Other scenario will return HAL_ERROR*/
+
+    hsd->ErrorCode = SDMMC_CmdStopTransfer(hsd->Instance);
+    error_code = hsd->ErrorCode;
+    if ((error_code != HAL_SD_ERROR_NONE) && (error_code != HAL_SD_ERROR_CMD_RSP_TIMEOUT))
+    {
+      return HAL_ERROR;
+    }
+
+    tickstart = HAL_GetTick();
+    if ((hsd->Instance->DCTRL & SDMMC_DCTRL_DTDIR) == SDMMC_TRANSFER_DIR_TO_CARD)
+    {
+      if (hsd->ErrorCode == HAL_SD_ERROR_NONE)
+      {
+         while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DABORT | SDMMC_FLAG_BUSYD0END))
+        {
+           if ((HAL_GetTick() - tickstart) >=  SDMMC_DATATIMEOUT)
+           {
+              hsd->ErrorCode = HAL_SD_ERROR_TIMEOUT;
+              hsd->State = HAL_SD_STATE_READY;
+              return HAL_TIMEOUT;
+           }
+        }
+      }
+
+      if (hsd->ErrorCode == HAL_SD_ERROR_CMD_RSP_TIMEOUT)
+      {
+        while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DATAEND))
+        {
+           if ((HAL_GetTick() - tickstart) >=  SDMMC_DATATIMEOUT)
+           {
+              hsd->ErrorCode = HAL_SD_ERROR_TIMEOUT;
+              hsd->State = HAL_SD_STATE_READY;
+              return HAL_TIMEOUT;
+           }
+        }
+      }
+    }
+    else if ((hsd->Instance->DCTRL & SDMMC_DCTRL_DTDIR) == SDMMC_TRANSFER_DIR_TO_SDMMC)
+    {
+      while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DABORT | SDMMC_FLAG_DATAEND))
+      {
+           if ((HAL_GetTick() - tickstart) >=  SDMMC_DATATIMEOUT)
+           {
+              hsd->ErrorCode = HAL_SD_ERROR_TIMEOUT;
+              hsd->State = HAL_SD_STATE_READY;
+              return HAL_TIMEOUT;
+           }
+      }
+    }
+    else
+    {
+      /* Nothing to do*/
+    }
+
+    /*The reason of all these while conditions previously is that we need to wait the SDMMC and clear
+      the appropriate flags that will be set depending of the abort/non abort of the memory */
+    /*Not waiting the SDMMC flags will cause the next SDMMC_DISABLE_IDMA to not get cleared
+      and will result in next SDMMC read/write operation to fail */
+
+    /*SDMMC ready for clear data flags*/
+    __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_BUSYD0END);
+    __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS);
+      /* If IDMA Context, disable Internal DMA */
+    hsd->Instance->IDMACTRL = SDMMC_DISABLE_IDMA;
+
+    hsd->State = HAL_SD_STATE_READY;
+
+    /* Initialize the SD operation */
+    hsd->Context = SD_CONTEXT_NONE;
+  }
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  Abort the current transfer and disable the SD (IT mode).
+  * @param  hsd: pointer to a SD_HandleTypeDef structure that contains
+  *                the configuration information for SD module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd)
+{
+  HAL_SD_CardStateTypeDef CardState;
+
+  /* Disable All interrupts */
+  __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | \
+                      SDMMC_IT_TXUNDERR | SDMMC_IT_RXOVERR);
+
+  /* If IDMA Context, disable Internal DMA */
+  hsd->Instance->IDMACTRL = SDMMC_DISABLE_IDMA;
+
+  /* Clear All flags */
+  __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS);
+
+  CardState = HAL_SD_GetCardState(hsd);
+  hsd->State = HAL_SD_STATE_READY;
+
+  if ((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING))
+  {
+    hsd->ErrorCode = SDMMC_CmdStopTransfer(hsd->Instance);
+  }
+
+  if (hsd->ErrorCode != HAL_SD_ERROR_NONE)
+  {
+    return HAL_ERROR;
+  }
+  else
+  {
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+    hsd->AbortCpltCallback(hsd);
+#else
+    HAL_SD_AbortCallback(hsd);
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private function ----------------------------------------------------------*/
+/** @addtogroup SD_Private_Functions
+  * @{
+  */
+
+
+/**
+  * @brief  Initializes the sd card.
+  * @param  hsd: Pointer to SD handle
+  * @retval SD Card error state
+  */
+static uint32_t SD_InitCard(SD_HandleTypeDef *hsd)
+{
+  HAL_SD_CardCSDTypeDef CSD;
+  uint32_t errorstate;
+  uint16_t sd_rca = 0U;
+  uint32_t tickstart = HAL_GetTick();
+
+  /* Check the power State */
+  if (SDMMC_GetPowerState(hsd->Instance) == 0U)
+  {
+    /* Power off */
+    return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE;
+  }
+
+  if (hsd->SdCard.CardType != CARD_SECURED)
+  {
+    /* Send CMD2 ALL_SEND_CID */
+    errorstate = SDMMC_CmdSendCID(hsd->Instance);
+    if (errorstate != HAL_SD_ERROR_NONE)
+    {
+      return errorstate;
+    }
+    else
+    {
+      /* Get Card identification number data */
+      hsd->CID[0U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1);
+      hsd->CID[1U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP2);
+      hsd->CID[2U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP3);
+      hsd->CID[3U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP4);
+    }
+  }
+
+  if (hsd->SdCard.CardType != CARD_SECURED)
+  {
+    /* Send CMD3 SET_REL_ADDR with argument 0 */
+    /* SD Card publishes its RCA. */
+    while (sd_rca == 0U)
+    {
+      errorstate = SDMMC_CmdSetRelAdd(hsd->Instance, &sd_rca);
+      if (errorstate != HAL_SD_ERROR_NONE)
+      {
+        return errorstate;
+      }
+      if ((HAL_GetTick() - tickstart) >=  SDMMC_CMDTIMEOUT)
+      {
+        return HAL_SD_ERROR_TIMEOUT;
+      }
+    }
+  }
+  if (hsd->SdCard.CardType != CARD_SECURED)
+  {
+    /* Get the SD card RCA */
+    hsd->SdCard.RelCardAdd = sd_rca;
+
+    /* Send CMD9 SEND_CSD with argument as card's RCA */
+    errorstate = SDMMC_CmdSendCSD(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U));
+    if (errorstate != HAL_SD_ERROR_NONE)
+    {
+      return errorstate;
+    }
+    else
+    {
+      /* Get Card Specific Data */
+      hsd->CSD[0U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1);
+      hsd->CSD[1U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP2);
+      hsd->CSD[2U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP3);
+      hsd->CSD[3U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP4);
+    }
+  }
+
+  /* Get the Card Class */
+  hsd->SdCard.Class = (SDMMC_GetResponse(hsd->Instance, SDMMC_RESP2) >> 20U);
+
+  /* Get CSD parameters */
+  if (HAL_SD_GetCardCSD(hsd, &CSD) != HAL_OK)
+  {
+    return HAL_SD_ERROR_UNSUPPORTED_FEATURE;
+  }
+
+  /* Select the Card */
+  errorstate = SDMMC_CmdSelDesel(hsd->Instance, (uint32_t)(((uint32_t)hsd->SdCard.RelCardAdd) << 16U));
+  if (errorstate != HAL_SD_ERROR_NONE)
+  {
+    return errorstate;
+  }
+
+  /* All cards are initialized */
+  return HAL_SD_ERROR_NONE;
+}
+
+/**
+  * @brief  Enquires cards about their operating voltage and configures clock
+  *         controls and stores SD information that will be needed in future
+  *         in the SD handle.
+  * @param  hsd: Pointer to SD handle
+  * @retval error state
+  */
+static uint32_t SD_PowerON(SD_HandleTypeDef *hsd)
+{
+  __IO uint32_t count = 0U;
+  uint32_t response = 0U;
+  uint32_t validvoltage = 0U;
+  uint32_t errorstate;
+#if (USE_SD_TRANSCEIVER != 0U)
+  uint32_t tickstart = HAL_GetTick();
+#endif /* USE_SD_TRANSCEIVER  */
+
+  /* CMD0: GO_IDLE_STATE */
+  errorstate = SDMMC_CmdGoIdleState(hsd->Instance);
+  if (errorstate != HAL_SD_ERROR_NONE)
+  {
+    return errorstate;
+  }
+
+  /* CMD8: SEND_IF_COND: Command available only on V2.0 cards */
+  errorstate = SDMMC_CmdOperCond(hsd->Instance);
+  if (errorstate == SDMMC_ERROR_TIMEOUT) /* No response to CMD8 */
+  {
+    hsd->SdCard.CardVersion = CARD_V1_X;
+    /* CMD0: GO_IDLE_STATE */
+    errorstate = SDMMC_CmdGoIdleState(hsd->Instance);
+    if (errorstate != HAL_SD_ERROR_NONE)
+    {
+      return errorstate;
+    }
+
+  }
+  else
+  {
+    hsd->SdCard.CardVersion = CARD_V2_X;
+  }
+
+  if (hsd->SdCard.CardVersion == CARD_V2_X)
+  {
+    /* SEND CMD55 APP_CMD with RCA as 0 */
+    errorstate = SDMMC_CmdAppCommand(hsd->Instance, 0);
+    if (errorstate != HAL_SD_ERROR_NONE)
+    {
+      return HAL_SD_ERROR_UNSUPPORTED_FEATURE;
+    }
+  }
+  /* SD CARD */
+  /* Send ACMD41 SD_APP_OP_COND with Argument 0x80100000 */
+  while ((count < SDMMC_MAX_VOLT_TRIAL) && (validvoltage == 0U))
+  {
+    /* SEND CMD55 APP_CMD with RCA as 0 */
+    errorstate = SDMMC_CmdAppCommand(hsd->Instance, 0);
+    if (errorstate != HAL_SD_ERROR_NONE)
+    {
+      return errorstate;
+    }
+
+    /* Send CMD41 */
+    errorstate = SDMMC_CmdAppOperCommand(hsd->Instance, SDMMC_VOLTAGE_WINDOW_SD | SDMMC_HIGH_CAPACITY |
+                                         SD_SWITCH_1_8V_CAPACITY);
+    if (errorstate != HAL_SD_ERROR_NONE)
+    {
+      return HAL_SD_ERROR_UNSUPPORTED_FEATURE;
+    }
+
+    /* Get command response */
+    response = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1);
+
+    /* Get operating voltage*/
+    validvoltage = (((response >> 31U) == 1U) ? 1U : 0U);
+
+    count++;
+  }
+
+  if (count >= SDMMC_MAX_VOLT_TRIAL)
+  {
+    return HAL_SD_ERROR_INVALID_VOLTRANGE;
+  }
+
+  /* Set default card type */
+  hsd->SdCard.CardType = CARD_SDSC;
+
+  if ((response & SDMMC_HIGH_CAPACITY) == SDMMC_HIGH_CAPACITY)
+  {
+    hsd->SdCard.CardType = CARD_SDHC_SDXC;
+#if (USE_SD_TRANSCEIVER != 0U)
+    if (hsd->Init.TranceiverPresent == SDMMC_TRANSCEIVER_PRESENT)
+    {
+      if ((response & SD_SWITCH_1_8V_CAPACITY) == SD_SWITCH_1_8V_CAPACITY)
+      {
+        hsd->SdCard.CardSpeed = CARD_ULTRA_HIGH_SPEED;
+
+        /* Start switching procedue */
+        hsd->Instance->POWER |= SDMMC_POWER_VSWITCHEN;
+
+        /* Send CMD11 to switch 1.8V mode */
+        errorstate = SDMMC_CmdVoltageSwitch(hsd->Instance);
+        if (errorstate != HAL_SD_ERROR_NONE)
+        {
+          return errorstate;
+        }
+
+        /* Check to CKSTOP */
+        while ((hsd->Instance->STA & SDMMC_FLAG_CKSTOP) != SDMMC_FLAG_CKSTOP)
+        {
+          if ((HAL_GetTick() - tickstart) >=  SDMMC_DATATIMEOUT)
+          {
+            return HAL_SD_ERROR_TIMEOUT;
+          }
+        }
+
+        /* Clear CKSTOP Flag */
+        hsd->Instance->ICR = SDMMC_FLAG_CKSTOP;
+
+        /* Check to BusyD0 */
+        if ((hsd->Instance->STA & SDMMC_FLAG_BUSYD0) != SDMMC_FLAG_BUSYD0)
+        {
+          /* Error when activate Voltage Switch in SDMMC Peripheral */
+          return SDMMC_ERROR_UNSUPPORTED_FEATURE;
+        }
+        else
+        {
+          /* Enable Transceiver Switch PIN */
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+          hsd->DriveTransceiver_1_8V_Callback(SET);
+#else
+          HAL_SD_DriveTransceiver_1_8V_Callback(SET);
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+
+          /* Switch ready */
+          hsd->Instance->POWER |= SDMMC_POWER_VSWITCH;
+
+          /* Check VSWEND Flag */
+          while ((hsd->Instance->STA & SDMMC_FLAG_VSWEND) != SDMMC_FLAG_VSWEND)
+          {
+            if ((HAL_GetTick() - tickstart) >=  SDMMC_DATATIMEOUT)
+            {
+              return HAL_SD_ERROR_TIMEOUT;
+            }
+          }
+
+          /* Clear VSWEND Flag */
+          hsd->Instance->ICR = SDMMC_FLAG_VSWEND;
+
+          /* Check BusyD0 status */
+          if ((hsd->Instance->STA & SDMMC_FLAG_BUSYD0) == SDMMC_FLAG_BUSYD0)
+          {
+            /* Error when enabling 1.8V mode */
+            return HAL_SD_ERROR_INVALID_VOLTRANGE;
+          }
+          /* Switch to 1.8V OK */
+
+          /* Disable VSWITCH FLAG from SDMMC Peripheral */
+          hsd->Instance->POWER = 0x13U;
+
+          /* Clean Status flags */
+          hsd->Instance->ICR = 0xFFFFFFFFU;
+        }
+      }
+    }
+#endif /* USE_SD_TRANSCEIVER  */
+  }
+
+  return HAL_SD_ERROR_NONE;
+}
+
+/**
+  * @brief  Turns the SDMMC output signals off.
+  * @param  hsd: Pointer to SD handle
+  * @retval None
+  */
+static void SD_PowerOFF(SD_HandleTypeDef *hsd)
+{
+  /* Set Power State to OFF */
+  (void)SDMMC_PowerState_OFF(hsd->Instance);
+}
+
+/**
+  * @brief  Send Status info command.
+  * @param  hsd: pointer to SD handle
+  * @param  pSDstatus: Pointer to the buffer that will contain the SD card status
+  *         SD Status register)
+  * @retval error state
+  */
+static uint32_t SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus)
+{
+  SDMMC_DataInitTypeDef config;
+  uint32_t errorstate;
+  uint32_t tickstart = HAL_GetTick();
+  uint32_t count;
+  uint32_t *pData = pSDstatus;
+
+  /* Check SD response */
+  if ((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)
+  {
+    return HAL_SD_ERROR_LOCK_UNLOCK_FAILED;
+  }
+
+  /* Set block size for card if it is not equal to current block size for card */
+  errorstate = SDMMC_CmdBlockLength(hsd->Instance, 64U);
+  if (errorstate != HAL_SD_ERROR_NONE)
+  {
+    hsd->ErrorCode |= HAL_SD_ERROR_NONE;
+    return errorstate;
+  }
+
+  /* Send CMD55 */
+  errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U));
+  if (errorstate != HAL_SD_ERROR_NONE)
+  {
+    hsd->ErrorCode |= HAL_SD_ERROR_NONE;
+    return errorstate;
+  }
+
+  /* Configure the SD DPSM (Data Path State Machine) */
+  config.DataTimeOut   = SDMMC_DATATIMEOUT;
+  config.DataLength    = 64U;
+  config.DataBlockSize = SDMMC_DATABLOCK_SIZE_64B;
+  config.TransferDir   = SDMMC_TRANSFER_DIR_TO_SDMMC;
+  config.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
+  config.DPSM          = SDMMC_DPSM_ENABLE;
+  (void)SDMMC_ConfigData(hsd->Instance, &config);
+
+  /* Send ACMD13 (SD_APP_STAUS)  with argument as card's RCA */
+  errorstate = SDMMC_CmdStatusRegister(hsd->Instance);
+  if (errorstate != HAL_SD_ERROR_NONE)
+  {
+    hsd->ErrorCode |= HAL_SD_ERROR_NONE;
+    return errorstate;
+  }
+
+  /* Get status data */
+  while (!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND))
+  {
+    if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF))
+    {
+      for (count = 0U; count < 8U; count++)
+      {
+        *pData = SDMMC_ReadFIFO(hsd->Instance);
+        pData++;
+      }
+    }
+
+    if ((HAL_GetTick() - tickstart) >=  SDMMC_DATATIMEOUT)
+    {
+      return HAL_SD_ERROR_TIMEOUT;
+    }
+  }
+
+  if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT))
+  {
+    return HAL_SD_ERROR_DATA_TIMEOUT;
+  }
+  else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL))
+  {
+    return HAL_SD_ERROR_DATA_CRC_FAIL;
+  }
+  else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR))
+  {
+    return HAL_SD_ERROR_RX_OVERRUN;
+  }
+  else
+  {
+    /* Nothing to do */
+  }
+
+  while ((__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DPSMACT)))
+  {
+    *pData = SDMMC_ReadFIFO(hsd->Instance);
+    pData++;
+
+    if ((HAL_GetTick() - tickstart) >=  SDMMC_DATATIMEOUT)
+    {
+      return HAL_SD_ERROR_TIMEOUT;
+    }
+  }
+
+  /* Clear all the static status flags*/
+  __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS);
+
+  return HAL_SD_ERROR_NONE;
+}
+
+/**
+  * @brief  Returns the current card's status.
+  * @param  hsd: Pointer to SD handle
+  * @param  pCardStatus: pointer to the buffer that will contain the SD card
+  *         status (Card Status register)
+  * @retval error state
+  */
+static uint32_t SD_SendStatus(SD_HandleTypeDef *hsd, uint32_t *pCardStatus)
+{
+  uint32_t errorstate;
+
+  if (pCardStatus == NULL)
+  {
+    return HAL_SD_ERROR_PARAM;
+  }
+
+  /* Send Status command */
+  errorstate = SDMMC_CmdSendStatus(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U));
+  if (errorstate != HAL_SD_ERROR_NONE)
+  {
+    return errorstate;
+  }
+
+  /* Get SD card status */
+  *pCardStatus = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1);
+
+  return HAL_SD_ERROR_NONE;
+}
+
+/**
+  * @brief  Enables the SDMMC wide bus mode.
+  * @param  hsd: pointer to SD handle
+  * @retval error state
+  */
+static uint32_t SD_WideBus_Enable(SD_HandleTypeDef *hsd)
+{
+  uint32_t scr[2U] = {0UL, 0UL};
+  uint32_t errorstate;
+
+  if ((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)
+  {
+    return HAL_SD_ERROR_LOCK_UNLOCK_FAILED;
+  }
+
+  /* Get SCR Register */
+  errorstate = SD_FindSCR(hsd, scr);
+  if (errorstate != HAL_SD_ERROR_NONE)
+  {
+    return errorstate;
+  }
+
+  /* If requested card supports wide bus operation */
+  if ((scr[1U] & SDMMC_WIDE_BUS_SUPPORT) != SDMMC_ALLZERO)
+  {
+    /* Send CMD55 APP_CMD with argument as card's RCA.*/
+    errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U));
+    if (errorstate != HAL_SD_ERROR_NONE)
+    {
+      return errorstate;
+    }
+
+    /* Send ACMD6 APP_CMD with argument as 2 for wide bus mode */
+    errorstate = SDMMC_CmdBusWidth(hsd->Instance, 2U);
+    if (errorstate != HAL_SD_ERROR_NONE)
+    {
+      return errorstate;
+    }
+
+    return HAL_SD_ERROR_NONE;
+  }
+  else
+  {
+    return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE;
+  }
+}
+
+/**
+  * @brief  Disables the SDMMC wide bus mode.
+  * @param  hsd: Pointer to SD handle
+  * @retval error state
+  */
+static uint32_t SD_WideBus_Disable(SD_HandleTypeDef *hsd)
+{
+  uint32_t scr[2U] = {0UL, 0UL};
+  uint32_t errorstate;
+
+  if ((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)
+  {
+    return HAL_SD_ERROR_LOCK_UNLOCK_FAILED;
+  }
+
+  /* Get SCR Register */
+  errorstate = SD_FindSCR(hsd, scr);
+  if (errorstate != HAL_SD_ERROR_NONE)
+  {
+    return errorstate;
+  }
+
+  /* If requested card supports 1 bit mode operation */
+  if ((scr[1U] & SDMMC_SINGLE_BUS_SUPPORT) != SDMMC_ALLZERO)
+  {
+    /* Send CMD55 APP_CMD with argument as card's RCA */
+    errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U));
+    if (errorstate != HAL_SD_ERROR_NONE)
+    {
+      return errorstate;
+    }
+
+    /* Send ACMD6 APP_CMD with argument as 0 for single bus mode */
+    errorstate = SDMMC_CmdBusWidth(hsd->Instance, 0U);
+    if (errorstate != HAL_SD_ERROR_NONE)
+    {
+      return errorstate;
+    }
+
+    return HAL_SD_ERROR_NONE;
+  }
+  else
+  {
+    return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE;
+  }
+}
+
+
+/**
+  * @brief  Finds the SD card SCR register value.
+  * @param  hsd: Pointer to SD handle
+  * @param  pSCR: pointer to the buffer that will contain the SCR value
+  * @retval error state
+  */
+static uint32_t SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR)
+{
+  SDMMC_DataInitTypeDef config;
+  uint32_t errorstate;
+  uint32_t tickstart = HAL_GetTick();
+  uint32_t index = 0U;
+  uint32_t tempscr[2U] = {0UL, 0UL};
+  uint32_t *scr = pSCR;
+
+  /* Set Block Size To 8 Bytes */
+  errorstate = SDMMC_CmdBlockLength(hsd->Instance, 8U);
+  if (errorstate != HAL_SD_ERROR_NONE)
+  {
+    return errorstate;
+  }
+
+  /* Send CMD55 APP_CMD with argument as card's RCA */
+  errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)((hsd->SdCard.RelCardAdd) << 16U));
+  if (errorstate != HAL_SD_ERROR_NONE)
+  {
+    return errorstate;
+  }
+
+  config.DataTimeOut   = SDMMC_DATATIMEOUT;
+  config.DataLength    = 8U;
+  config.DataBlockSize = SDMMC_DATABLOCK_SIZE_8B;
+  config.TransferDir   = SDMMC_TRANSFER_DIR_TO_SDMMC;
+  config.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
+  config.DPSM          = SDMMC_DPSM_ENABLE;
+  (void)SDMMC_ConfigData(hsd->Instance, &config);
+
+  /* Send ACMD51 SD_APP_SEND_SCR with argument as 0 */
+  errorstate = SDMMC_CmdSendSCR(hsd->Instance);
+  if (errorstate != HAL_SD_ERROR_NONE)
+  {
+    return errorstate;
+  }
+
+  while (!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND |
+                            SDMMC_FLAG_DATAEND))
+  {
+    if ((!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOE)) && (index == 0U))
+    {
+      tempscr[0] = SDMMC_ReadFIFO(hsd->Instance);
+      tempscr[1] = SDMMC_ReadFIFO(hsd->Instance);
+      index++;
+    }
+
+
+    if ((HAL_GetTick() - tickstart) >=  SDMMC_DATATIMEOUT)
+    {
+      return HAL_SD_ERROR_TIMEOUT;
+    }
+  }
+
+  if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT))
+  {
+    __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DTIMEOUT);
+
+    return HAL_SD_ERROR_DATA_TIMEOUT;
+  }
+  else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL))
+  {
+    __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DCRCFAIL);
+
+    return HAL_SD_ERROR_DATA_CRC_FAIL;
+  }
+  else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR))
+  {
+    __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_RXOVERR);
+
+    return HAL_SD_ERROR_RX_OVERRUN;
+  }
+  else
+  {
+    /* No error flag set */
+    /* Clear all the static flags */
+    __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS);
+
+    *scr = (((tempscr[1] & SDMMC_0TO7BITS) << 24)  | ((tempscr[1] & SDMMC_8TO15BITS) << 8) | \
+            ((tempscr[1] & SDMMC_16TO23BITS) >> 8) | ((tempscr[1] & SDMMC_24TO31BITS) >> 24));
+    scr++;
+    *scr = (((tempscr[0] & SDMMC_0TO7BITS) << 24)  | ((tempscr[0] & SDMMC_8TO15BITS) << 8) | \
+            ((tempscr[0] & SDMMC_16TO23BITS) >> 8) | ((tempscr[0] & SDMMC_24TO31BITS) >> 24));
+
+  }
+
+  return HAL_SD_ERROR_NONE;
+}
+
+/**
+  * @brief  Wrap up reading in non-blocking mode.
+  * @param  hsd: pointer to a SD_HandleTypeDef structure that contains
+  *              the configuration information.
+  * @retval None
+  */
+static void SD_Read_IT(SD_HandleTypeDef *hsd)
+{
+  uint32_t count;
+  uint32_t data;
+  uint8_t *tmp;
+
+  tmp = hsd->pRxBuffPtr;
+
+  if (hsd->RxXferSize >= 32U)
+  {
+    /* Read data from SDMMC Rx FIFO */
+    for (count = 0U; count < 8U; count++)
+    {
+      data = SDMMC_ReadFIFO(hsd->Instance);
+      *tmp = (uint8_t)(data & 0xFFU);
+      tmp++;
+      *tmp = (uint8_t)((data >> 8U) & 0xFFU);
+      tmp++;
+      *tmp = (uint8_t)((data >> 16U) & 0xFFU);
+      tmp++;
+      *tmp = (uint8_t)((data >> 24U) & 0xFFU);
+      tmp++;
+    }
+
+    hsd->pRxBuffPtr = tmp;
+    hsd->RxXferSize -= 32U;
+  }
+}
+
+/**
+  * @brief  Wrap up writing in non-blocking mode.
+  * @param  hsd: pointer to a SD_HandleTypeDef structure that contains
+  *              the configuration information.
+  * @retval None
+  */
+static void SD_Write_IT(SD_HandleTypeDef *hsd)
+{
+  uint32_t count;
+  uint32_t data;
+  const uint8_t *tmp;
+
+  tmp = hsd->pTxBuffPtr;
+
+  if (hsd->TxXferSize >= 32U)
+  {
+    /* Write data to SDMMC Tx FIFO */
+    for (count = 0U; count < 8U; count++)
+    {
+      data = (uint32_t)(*tmp);
+      tmp++;
+      data |= ((uint32_t)(*tmp) << 8U);
+      tmp++;
+      data |= ((uint32_t)(*tmp) << 16U);
+      tmp++;
+      data |= ((uint32_t)(*tmp) << 24U);
+      tmp++;
+      (void)SDMMC_WriteFIFO(hsd->Instance, &data);
+    }
+
+    hsd->pTxBuffPtr = tmp;
+    hsd->TxXferSize -= 32U;
+  }
+}
+
+/**
+  * @brief  Switches the SD card to High Speed mode.
+  *         This API must be used after "Transfer State"
+  * @note   This operation should be followed by the configuration
+  *         of PLL to have SDMMCCK clock between 25 and 50 MHz
+  * @param  hsd: SD handle
+  * @param  SwitchSpeedMode: SD speed mode( SDMMC_SDR12_SWITCH_PATTERN, SDMMC_SDR25_SWITCH_PATTERN)
+  * @retval SD Card error state
+  */
+uint32_t SD_SwitchSpeed(SD_HandleTypeDef *hsd, uint32_t SwitchSpeedMode)
+{
+  uint32_t errorstate = HAL_SD_ERROR_NONE;
+  SDMMC_DataInitTypeDef sdmmc_datainitstructure;
+  uint32_t SD_hs[16]  = {0};
+  uint32_t count;
+  uint32_t loop = 0 ;
+  uint32_t Timeout = HAL_GetTick();
+
+  if (hsd->SdCard.CardSpeed == CARD_NORMAL_SPEED)
+  {
+    /* Standard Speed Card <= 12.5Mhz  */
+    return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE;
+  }
+
+  if (hsd->SdCard.CardSpeed >= CARD_HIGH_SPEED)
+  {
+    /* Initialize the Data control register */
+    hsd->Instance->DCTRL = 0;
+    errorstate = SDMMC_CmdBlockLength(hsd->Instance, 64U);
+
+    if (errorstate != HAL_SD_ERROR_NONE)
+    {
+      return errorstate;
+    }
+
+    /* Configure the SD DPSM (Data Path State Machine) */
+    sdmmc_datainitstructure.DataTimeOut   = SDMMC_DATATIMEOUT;
+    sdmmc_datainitstructure.DataLength    = 64U;
+    sdmmc_datainitstructure.DataBlockSize = SDMMC_DATABLOCK_SIZE_64B ;
+    sdmmc_datainitstructure.TransferDir   = SDMMC_TRANSFER_DIR_TO_SDMMC;
+    sdmmc_datainitstructure.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
+    sdmmc_datainitstructure.DPSM          = SDMMC_DPSM_ENABLE;
+
+    (void)SDMMC_ConfigData(hsd->Instance, &sdmmc_datainitstructure);
+
+
+    errorstate = SDMMC_CmdSwitch(hsd->Instance, SwitchSpeedMode);
+    if (errorstate != HAL_SD_ERROR_NONE)
+    {
+      return errorstate;
+    }
+
+    while (!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND |
+                              SDMMC_FLAG_DATAEND))
+    {
+      if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF))
+      {
+        for (count = 0U; count < 8U; count++)
+        {
+          SD_hs[(8U * loop) + count]  = SDMMC_ReadFIFO(hsd->Instance);
+        }
+        loop ++;
+      }
+
+      if ((HAL_GetTick() - Timeout) >=  SDMMC_DATATIMEOUT)
+      {
+        hsd->ErrorCode = HAL_SD_ERROR_TIMEOUT;
+        hsd->State = HAL_SD_STATE_READY;
+        return HAL_SD_ERROR_TIMEOUT;
+      }
+    }
+
+    if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT))
+    {
+      __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DTIMEOUT);
+
+      return errorstate;
+    }
+    else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL))
+    {
+      __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DCRCFAIL);
+
+      errorstate = SDMMC_ERROR_DATA_CRC_FAIL;
+
+      return errorstate;
+    }
+    else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR))
+    {
+      __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_RXOVERR);
+
+      errorstate = SDMMC_ERROR_RX_OVERRUN;
+
+      return errorstate;
+    }
+    else
+    {
+      /* No error flag set */
+    }
+
+    /* Clear all the static flags */
+    __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS);
+
+    /* Test if the switch mode HS is ok */
+    if ((((uint8_t *)SD_hs)[13] & 2U) != 2U)
+    {
+      errorstate = SDMMC_ERROR_UNSUPPORTED_FEATURE;
+    }
+
+  }
+
+  return errorstate;
+}
+
+#if (USE_SD_TRANSCEIVER != 0U)
+/**
+  * @brief  Switches the SD card to Ultra High Speed mode.
+  *         This API must be used after "Transfer State"
+  * @note   This operation should be followed by the configuration
+  *         of PLL to have SDMMCCK clock between 50 and 120 MHz
+  * @param  hsd: SD handle
+  * @param  UltraHighSpeedMode: SD speed mode( SDMMC_SDR50_SWITCH_PATTERN, SDMMC_SDR104_SWITCH_PATTERN)
+  * @retval SD Card error state
+  */
+static uint32_t SD_UltraHighSpeed(SD_HandleTypeDef *hsd, uint32_t UltraHighSpeedMode)
+{
+  uint32_t errorstate = HAL_SD_ERROR_NONE;
+  SDMMC_DataInitTypeDef sdmmc_datainitstructure;
+  uint32_t SD_hs[16]  = {0};
+  uint32_t count;
+  uint32_t loop = 0 ;
+  uint32_t Timeout = HAL_GetTick();
+
+  if (hsd->SdCard.CardSpeed == CARD_NORMAL_SPEED)
+  {
+    /* Standard Speed Card <= 12.5Mhz  */
+    return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE;
+  }
+
+  if (hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED)
+  {
+    /* Initialize the Data control register */
+    hsd->Instance->DCTRL = 0;
+    errorstate = SDMMC_CmdBlockLength(hsd->Instance, 64U);
+
+    if (errorstate != HAL_SD_ERROR_NONE)
+    {
+      return errorstate;
+    }
+
+    /* Configure the SD DPSM (Data Path State Machine) */
+    sdmmc_datainitstructure.DataTimeOut   = SDMMC_DATATIMEOUT;
+    sdmmc_datainitstructure.DataLength    = 64U;
+    sdmmc_datainitstructure.DataBlockSize = SDMMC_DATABLOCK_SIZE_64B ;
+    sdmmc_datainitstructure.TransferDir   = SDMMC_TRANSFER_DIR_TO_SDMMC;
+    sdmmc_datainitstructure.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
+    sdmmc_datainitstructure.DPSM          = SDMMC_DPSM_ENABLE;
+
+    if (SDMMC_ConfigData(hsd->Instance, &sdmmc_datainitstructure) != HAL_OK)
+    {
+      return (HAL_SD_ERROR_GENERAL_UNKNOWN_ERR);
+    }
+
+    errorstate = SDMMC_CmdSwitch(hsd->Instance, UltraHighSpeedMode);
+    if (errorstate != HAL_SD_ERROR_NONE)
+    {
+      return errorstate;
+    }
+
+    while (!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND |
+                              SDMMC_FLAG_DATAEND))
+    {
+      if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF))
+      {
+        for (count = 0U; count < 8U; count++)
+        {
+          SD_hs[(8U * loop) + count]  = SDMMC_ReadFIFO(hsd->Instance);
+        }
+        loop ++;
+      }
+
+      if ((HAL_GetTick() - Timeout) >=  SDMMC_DATATIMEOUT)
+      {
+        hsd->ErrorCode = HAL_SD_ERROR_TIMEOUT;
+        hsd->State = HAL_SD_STATE_READY;
+        return HAL_SD_ERROR_TIMEOUT;
+      }
+    }
+
+    if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT))
+    {
+      __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DTIMEOUT);
+
+      return errorstate;
+    }
+    else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL))
+    {
+      __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DCRCFAIL);
+
+      errorstate = SDMMC_ERROR_DATA_CRC_FAIL;
+
+      return errorstate;
+    }
+    else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR))
+    {
+      __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_RXOVERR);
+
+      errorstate = SDMMC_ERROR_RX_OVERRUN;
+
+      return errorstate;
+    }
+    else
+    {
+      /* No error flag set */
+    }
+
+    /* Clear all the static flags */
+    __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS);
+
+    /* Test if the switch mode HS is ok */
+    if ((((uint8_t *)SD_hs)[13] & 2U) != 2U)
+    {
+      errorstate = SDMMC_ERROR_UNSUPPORTED_FEATURE;
+    }
+    else
+    {
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+      hsd->DriveTransceiver_1_8V_Callback(SET);
+#else
+      HAL_SD_DriveTransceiver_1_8V_Callback(SET);
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+#if defined (DLYB_SDMMC1) || defined (DLYB_SDMMC2)
+      /* Enable DelayBlock Peripheral */
+      /* SDMMC_FB_CLK tuned feedback clock selected as receive clock, for SDR104 */
+      MODIFY_REG(hsd->Instance->CLKCR, SDMMC_CLKCR_SELCLKRX, SDMMC_CLKCR_SELCLKRX_1);
+      if (DelayBlock_Enable(SD_GET_DLYB_INSTANCE(hsd->Instance)) != HAL_OK)
+      {
+        return (HAL_SD_ERROR_GENERAL_UNKNOWN_ERR);
+      }
+#endif /* (DLYB_SDMMC1) || (DLYB_SDMMC2) */
+    }
+  }
+
+  return errorstate;
+}
+
+/**
+  * @brief  Switches the SD card to Double Data Rate (DDR) mode.
+  *         This API must be used after "Transfer State"
+  * @note   This operation should be followed by the configuration
+  *         of PLL to have SDMMCCK clock less than 50MHz
+  * @param  hsd: SD handle
+  * @retval SD Card error state
+  */
+static uint32_t SD_DDR_Mode(SD_HandleTypeDef *hsd)
+{
+  uint32_t errorstate = HAL_SD_ERROR_NONE;
+  SDMMC_DataInitTypeDef sdmmc_datainitstructure;
+  uint32_t SD_hs[16]  = {0};
+  uint32_t count;
+  uint32_t loop = 0 ;
+  uint32_t Timeout = HAL_GetTick();
+
+  if (hsd->SdCard.CardSpeed == CARD_NORMAL_SPEED)
+  {
+    /* Standard Speed Card <= 12.5Mhz  */
+    return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE;
+  }
+
+  if (hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED)
+  {
+    /* Initialize the Data control register */
+    hsd->Instance->DCTRL = 0;
+    errorstate = SDMMC_CmdBlockLength(hsd->Instance, 64U);
+
+    if (errorstate != HAL_SD_ERROR_NONE)
+    {
+      return errorstate;
+    }
+
+    /* Configure the SD DPSM (Data Path State Machine) */
+    sdmmc_datainitstructure.DataTimeOut   = SDMMC_DATATIMEOUT;
+    sdmmc_datainitstructure.DataLength    = 64U;
+    sdmmc_datainitstructure.DataBlockSize = SDMMC_DATABLOCK_SIZE_64B ;
+    sdmmc_datainitstructure.TransferDir   = SDMMC_TRANSFER_DIR_TO_SDMMC;
+    sdmmc_datainitstructure.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
+    sdmmc_datainitstructure.DPSM          = SDMMC_DPSM_ENABLE;
+
+    if (SDMMC_ConfigData(hsd->Instance, &sdmmc_datainitstructure) != HAL_OK)
+    {
+      return (HAL_SD_ERROR_GENERAL_UNKNOWN_ERR);
+    }
+
+    errorstate = SDMMC_CmdSwitch(hsd->Instance, SDMMC_DDR50_SWITCH_PATTERN);
+    if (errorstate != HAL_SD_ERROR_NONE)
+    {
+      return errorstate;
+    }
+
+    while (!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND |
+                              SDMMC_FLAG_DATAEND))
+    {
+      if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF))
+      {
+        for (count = 0U; count < 8U; count++)
+        {
+          SD_hs[(8U * loop) + count]  = SDMMC_ReadFIFO(hsd->Instance);
+        }
+        loop ++;
+      }
+
+      if ((HAL_GetTick() - Timeout) >=  SDMMC_DATATIMEOUT)
+      {
+        hsd->ErrorCode = HAL_SD_ERROR_TIMEOUT;
+        hsd->State = HAL_SD_STATE_READY;
+        return HAL_SD_ERROR_TIMEOUT;
+      }
+    }
+
+    if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT))
+    {
+      __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DTIMEOUT);
+
+      return errorstate;
+    }
+    else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL))
+    {
+      __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DCRCFAIL);
+
+      errorstate = SDMMC_ERROR_DATA_CRC_FAIL;
+
+      return errorstate;
+    }
+    else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR))
+    {
+      __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_RXOVERR);
+
+      errorstate = SDMMC_ERROR_RX_OVERRUN;
+
+      return errorstate;
+    }
+    else
+    {
+      /* No error flag set */
+    }
+
+    /* Clear all the static flags */
+    __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS);
+
+    /* Test if the switch mode  is ok */
+    if ((((uint8_t *)SD_hs)[13] & 2U) != 2U)
+    {
+      errorstate = SDMMC_ERROR_UNSUPPORTED_FEATURE;
+    }
+    else
+    {
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+      hsd->DriveTransceiver_1_8V_Callback(SET);
+#else
+      HAL_SD_DriveTransceiver_1_8V_Callback(SET);
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+#if defined (DLYB_SDMMC1) || defined (DLYB_SDMMC2)
+      /* Enable DelayBlock Peripheral */
+      /* SDMMC_CKin feedback clock selected as receive clock, for DDR50 */
+      MODIFY_REG(hsd->Instance->CLKCR, SDMMC_CLKCR_SELCLKRX, SDMMC_CLKCR_SELCLKRX_0);
+      if (DelayBlock_Enable(SD_GET_DLYB_INSTANCE(hsd->Instance)) != HAL_OK)
+      {
+        return (HAL_SD_ERROR_GENERAL_UNKNOWN_ERR);
+      }
+#endif /* (DLYB_SDMMC1) || (DLYB_SDMMC2) */
+    }
+  }
+
+  return errorstate;
+}
+
+#endif /* USE_SD_TRANSCEIVER */
+
+/**
+  * @brief Read DMA Buffer 0 Transfer completed callbacks
+  * @param hsd: SD handle
+  * @retval None
+  */
+__weak void HAL_SDEx_Read_DMADoubleBuf0CpltCallback(SD_HandleTypeDef *hsd)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsd);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SDEx_Read_DMADoubleBuf0CpltCallback can be implemented in the user file
+   */
+}
+
+/**
+  * @brief Read DMA Buffer 1 Transfer completed callbacks
+  * @param hsd: SD handle
+  * @retval None
+  */
+__weak void HAL_SDEx_Read_DMADoubleBuf1CpltCallback(SD_HandleTypeDef *hsd)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsd);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SDEx_Read_DMADoubleBuf1CpltCallback can be implemented in the user file
+   */
+}
+
+/**
+  * @brief Write DMA Buffer 0 Transfer completed callbacks
+  * @param hsd: SD handle
+  * @retval None
+  */
+__weak void HAL_SDEx_Write_DMADoubleBuf0CpltCallback(SD_HandleTypeDef *hsd)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsd);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SDEx_Write_DMADoubleBuf0CpltCallback can be implemented in the user file
+   */
+}
+
+/**
+  * @brief Write DMA Buffer 1 Transfer completed callbacks
+  * @param hsd: SD handle
+  * @retval None
+  */
+__weak void HAL_SDEx_Write_DMADoubleBuf1CpltCallback(SD_HandleTypeDef *hsd)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsd);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SDEx_Write_DMADoubleBuf1CpltCallback can be implemented in the user file
+   */
+}
+
+
+/**
+  * @}
+  */
+
+#endif /* HAL_SD_MODULE_ENABLED */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
diff --git a/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd_ex.c b/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd_ex.c
new file mode 100644
index 0000000..1cc19e3
--- /dev/null
+++ b/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd_ex.c
@@ -0,0 +1,313 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_sd_ex.c
+  * @author  MCD Application Team
+  * @brief   SD card Extended HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Secure Digital (SD) peripheral:
+  *           + Extended features functions
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+                        ##### How to use this driver #####
+  ==============================================================================
+  [..]
+   The SD Extension HAL driver can be used as follows:
+   (+) Configure Buffer0 and Buffer1 start address and Buffer size using HAL_SDEx_ConfigDMAMultiBuffer() function.
+   (+) Start Read and Write for multibuffer mode using HAL_SDEx_ReadBlocksDMAMultiBuffer()
+       and HAL_SDEx_WriteBlocksDMAMultiBuffer() functions.
+
+  @endverbatim
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup SDEx SDEx
+  * @brief SD Extended HAL module driver
+  * @{
+  */
+
+#ifdef HAL_SD_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup SDEx_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup SDEx_Exported_Functions_Group1
+  *  @brief   Multibuffer functions
+  *
+@verbatim
+  ==============================================================================
+          ##### Multibuffer functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to configure the multibuffer mode and start read and write
+    multibuffer mode for SD HAL driver.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configure DMA Dual Buffer mode. The Data transfer is managed by an Internal DMA.
+  * @param  hsd: SD handle
+  * @param  pDataBuffer0: Pointer to the buffer0 that will contain/receive the transferred data
+  * @param  pDataBuffer1: Pointer to the buffer1 that will contain/receive the transferred data
+  * @param  BufferSize: Size of Buffer0 in Blocks. Buffer0 and Buffer1 must have the same size.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SDEx_ConfigDMAMultiBuffer(SD_HandleTypeDef *hsd, uint32_t *pDataBuffer0, uint32_t *pDataBuffer1,
+                                                uint32_t BufferSize)
+{
+  if (hsd->State == HAL_SD_STATE_READY)
+  {
+    hsd->Instance->IDMABASE0 = (uint32_t) pDataBuffer0;
+    hsd->Instance->IDMABASE1 = (uint32_t) pDataBuffer1;
+    hsd->Instance->IDMABSIZE = (uint32_t)(BLOCKSIZE * BufferSize);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Reads block(s) from a specified address in a card. The received Data will be stored in Buffer0 and Buffer1.
+  *         Buffer0, Buffer1 and BufferSize need to be configured by function HAL_SDEx_ConfigDMAMultiBuffer before
+  *         call this function.
+  * @param  hsd: SD handle
+  * @param  BlockAdd: Block Address from where data is to be read
+  * @param  NumberOfBlocks: Total number of blocks to read
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SDEx_ReadBlocksDMAMultiBuffer(SD_HandleTypeDef *hsd, uint32_t BlockAdd, uint32_t NumberOfBlocks)
+{
+  SDMMC_DataInitTypeDef config;
+  uint32_t errorstate;
+  uint32_t DmaBase0_reg;
+  uint32_t DmaBase1_reg;
+  uint32_t add = BlockAdd;
+
+  if (hsd->State == HAL_SD_STATE_READY)
+  {
+    if ((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
+    {
+      hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
+      return HAL_ERROR;
+    }
+
+    DmaBase0_reg = hsd->Instance->IDMABASE0;
+    DmaBase1_reg = hsd->Instance->IDMABASE1;
+
+    if ((hsd->Instance->IDMABSIZE == 0U) || (DmaBase0_reg == 0U) || (DmaBase1_reg == 0U))
+    {
+      hsd->ErrorCode = HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
+      return HAL_ERROR;
+    }
+
+    /* Initialize data control register */
+    hsd->Instance->DCTRL = 0;
+    /* Clear old Flags*/
+    __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS);
+
+    hsd->ErrorCode = HAL_SD_ERROR_NONE;
+    hsd->State = HAL_SD_STATE_BUSY;
+
+    if (hsd->SdCard.CardType != CARD_SDHC_SDXC)
+    {
+      add *= 512U;
+    }
+
+    /* Configure the SD DPSM (Data Path State Machine) */
+    config.DataTimeOut   = SDMMC_DATATIMEOUT;
+    config.DataLength    = BLOCKSIZE * NumberOfBlocks;
+    config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
+    config.TransferDir   = SDMMC_TRANSFER_DIR_TO_SDMMC;
+    config.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
+    config.DPSM          = SDMMC_DPSM_DISABLE;
+    (void)SDMMC_ConfigData(hsd->Instance, &config);
+
+    hsd->Instance->DCTRL |= SDMMC_DCTRL_FIFORST;
+
+    __SDMMC_CMDTRANS_ENABLE(hsd->Instance);
+
+    hsd->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_DOUBLE_BUFF0;
+
+    /* Read Blocks in DMA mode */
+    hsd->Context = (SD_CONTEXT_READ_MULTIPLE_BLOCK | SD_CONTEXT_DMA);
+
+    /* Read Multi Block command */
+    errorstate = SDMMC_CmdReadMultiBlock(hsd->Instance, add);
+    if (errorstate != HAL_SD_ERROR_NONE)
+    {
+      hsd->State = HAL_SD_STATE_READY;
+      hsd->ErrorCode |= errorstate;
+      return HAL_ERROR;
+    }
+
+    __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND |
+                             SDMMC_IT_IDMABTC));
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+
+}
+
+/**
+  * @brief  Write block(s) to a specified address in a card. The transferred Data are stored in Buffer0 and Buffer1.
+  *         Buffer0, Buffer1 and BufferSize need to be configured by function HAL_SDEx_ConfigDMAMultiBuffer before
+  *   call this function.
+  * @param  hsd: SD handle
+  * @param  BlockAdd: Block Address from where data is to be read
+  * @param  NumberOfBlocks: Total number of blocks to read
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SDEx_WriteBlocksDMAMultiBuffer(SD_HandleTypeDef *hsd, uint32_t BlockAdd, uint32_t NumberOfBlocks)
+{
+  SDMMC_DataInitTypeDef config;
+  uint32_t errorstate;
+  uint32_t DmaBase0_reg;
+  uint32_t DmaBase1_reg;
+  uint32_t add = BlockAdd;
+
+  if (hsd->State == HAL_SD_STATE_READY)
+  {
+    if ((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
+    {
+      hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
+      return HAL_ERROR;
+    }
+
+    DmaBase0_reg = hsd->Instance->IDMABASE0;
+    DmaBase1_reg = hsd->Instance->IDMABASE1;
+    if ((hsd->Instance->IDMABSIZE == 0U) || (DmaBase0_reg == 0U) || (DmaBase1_reg == 0U))
+    {
+      hsd->ErrorCode = HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
+      return HAL_ERROR;
+    }
+
+    /* Initialize data control register */
+    hsd->Instance->DCTRL = 0;
+
+    hsd->ErrorCode = HAL_SD_ERROR_NONE;
+
+    hsd->State = HAL_SD_STATE_BUSY;
+
+    if (hsd->SdCard.CardType != CARD_SDHC_SDXC)
+    {
+      add *= 512U;
+    }
+
+    /* Configure the SD DPSM (Data Path State Machine) */
+    config.DataTimeOut   = SDMMC_DATATIMEOUT;
+    config.DataLength    = BLOCKSIZE * NumberOfBlocks;
+    config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
+    config.TransferDir   = SDMMC_TRANSFER_DIR_TO_CARD;
+    config.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
+    config.DPSM          = SDMMC_DPSM_DISABLE;
+    (void)SDMMC_ConfigData(hsd->Instance, &config);
+
+    __SDMMC_CMDTRANS_ENABLE(hsd->Instance);
+
+    hsd->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_DOUBLE_BUFF0;
+
+    /* Write Blocks in DMA mode */
+    hsd->Context = (SD_CONTEXT_WRITE_MULTIPLE_BLOCK | SD_CONTEXT_DMA);
+
+    /* Write Multi Block command */
+    errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, add);
+    if (errorstate != HAL_SD_ERROR_NONE)
+    {
+      hsd->State = HAL_SD_STATE_READY;
+      hsd->ErrorCode |= errorstate;
+      return HAL_ERROR;
+    }
+
+    __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND |
+                             SDMMC_IT_IDMABTC));
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+
+/**
+  * @brief  Change the DMA Buffer0 or Buffer1 address on the fly.
+  * @param  hsd:           pointer to a SD_HandleTypeDef structure.
+  * @param  Buffer:        the buffer to be changed, This parameter can be one of
+  *                        the following values: SD_DMA_BUFFER0 or SD_DMA_BUFFER1
+  * @param  pDataBuffer:   The new address
+  * @note   The BUFFER0 address can be changed only when the current transfer use
+  *         BUFFER1 and the BUFFER1 address can be changed only when the current
+  *         transfer use BUFFER0.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SDEx_ChangeDMABuffer(SD_HandleTypeDef *hsd, HAL_SDEx_DMABuffer_MemoryTypeDef Buffer,
+                                           uint32_t *pDataBuffer)
+{
+  if (Buffer == SD_DMA_BUFFER0)
+  {
+    /* change the buffer0 address */
+    hsd->Instance->IDMABASE0 = (uint32_t)pDataBuffer;
+  }
+  else
+  {
+    /* change the memory1 address */
+    hsd->Instance->IDMABASE1 = (uint32_t)pDataBuffer;
+  }
+
+  return HAL_OK;
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_SD_MODULE_ENABLED */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
diff --git a/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c b/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c
new file mode 100644
index 0000000..016d568
--- /dev/null
+++ b/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c
@@ -0,0 +1,4722 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_uart.c
+  * @author  MCD Application Team
+  * @brief   UART HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART).
+  *           + Initialization and de-initialization functions
+  *           + IO operation functions
+  *           + Peripheral Control functions
+  *
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+ ===============================================================================
+                        ##### How to use this driver #####
+ ===============================================================================
+  [..]
+    The UART HAL driver can be used as follows:
+
+    (#) Declare a UART_HandleTypeDef handle structure (eg. UART_HandleTypeDef huart).
+    (#) Initialize the UART low level resources by implementing the HAL_UART_MspInit() API:
+        (++) Enable the USARTx interface clock.
+        (++) UART pins configuration:
+            (+++) Enable the clock for the UART GPIOs.
+            (+++) Configure these UART pins as alternate function pull-up.
+        (++) NVIC configuration if you need to use interrupt process (HAL_UART_Transmit_IT()
+             and HAL_UART_Receive_IT() APIs):
+            (+++) Configure the USARTx interrupt priority.
+            (+++) Enable the NVIC USART IRQ handle.
+        (++) UART interrupts handling:
+              -@@-  The specific UART interrupts (Transmission complete interrupt,
+                RXNE interrupt, RX/TX FIFOs related interrupts and Error Interrupts)
+                are managed using the macros __HAL_UART_ENABLE_IT() and __HAL_UART_DISABLE_IT()
+                inside the transmit and receive processes.
+        (++) DMA Configuration if you need to use DMA process (HAL_UART_Transmit_DMA()
+             and HAL_UART_Receive_DMA() APIs):
+            (+++) Declare a DMA handle structure for the Tx/Rx channel.
+            (+++) Enable the DMAx interface clock.
+            (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
+            (+++) Configure the DMA Tx/Rx channel.
+            (+++) Associate the initialized DMA handle to the UART DMA Tx/Rx handle.
+            (+++) Configure the priority and enable the NVIC for the transfer complete
+                  interrupt on the DMA Tx/Rx channel.
+
+    (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Prescaler value , Hardware
+        flow control and Mode (Receiver/Transmitter) in the huart handle Init structure.
+
+    (#) If required, program UART advanced features (TX/RX pins swap, auto Baud rate detection,...)
+        in the huart handle AdvancedInit structure.
+
+    (#) For the UART asynchronous mode, initialize the UART registers by calling
+        the HAL_UART_Init() API.
+
+    (#) For the UART Half duplex mode, initialize the UART registers by calling
+        the HAL_HalfDuplex_Init() API.
+
+    (#) For the UART LIN (Local Interconnection Network) mode, initialize the UART registers
+        by calling the HAL_LIN_Init() API.
+
+    (#) For the UART Multiprocessor mode, initialize the UART registers
+        by calling the HAL_MultiProcessor_Init() API.
+
+    (#) For the UART RS485 Driver Enabled mode, initialize the UART registers
+        by calling the HAL_RS485Ex_Init() API.
+
+    [..]
+    (@) These API's (HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(),
+        also configure the low level Hardware GPIO, CLOCK, CORTEX...etc) by
+        calling the customized HAL_UART_MspInit() API.
+
+    ##### Callback registration #####
+    ==================================
+
+    [..]
+    The compilation define USE_HAL_UART_REGISTER_CALLBACKS when set to 1
+    allows the user to configure dynamically the driver callbacks.
+
+    [..]
+    Use Function HAL_UART_RegisterCallback() to register a user callback.
+    Function HAL_UART_RegisterCallback() allows to register following callbacks:
+    (+) TxHalfCpltCallback        : Tx Half Complete Callback.
+    (+) TxCpltCallback            : Tx Complete Callback.
+    (+) RxHalfCpltCallback        : Rx Half Complete Callback.
+    (+) RxCpltCallback            : Rx Complete Callback.
+    (+) ErrorCallback             : Error Callback.
+    (+) AbortCpltCallback         : Abort Complete Callback.
+    (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.
+    (+) AbortReceiveCpltCallback  : Abort Receive Complete Callback.
+    (+) WakeupCallback            : Wakeup Callback.
+    (+) RxFifoFullCallback        : Rx Fifo Full Callback.
+    (+) TxFifoEmptyCallback       : Tx Fifo Empty Callback.
+    (+) MspInitCallback           : UART MspInit.
+    (+) MspDeInitCallback         : UART MspDeInit.
+    This function takes as parameters the HAL peripheral handle, the Callback ID
+    and a pointer to the user callback function.
+
+    [..]
+    Use function HAL_UART_UnRegisterCallback() to reset a callback to the default
+    weak (surcharged) function.
+    HAL_UART_UnRegisterCallback() takes as parameters the HAL peripheral handle,
+    and the Callback ID.
+    This function allows to reset following callbacks:
+    (+) TxHalfCpltCallback        : Tx Half Complete Callback.
+    (+) TxCpltCallback            : Tx Complete Callback.
+    (+) RxHalfCpltCallback        : Rx Half Complete Callback.
+    (+) RxCpltCallback            : Rx Complete Callback.
+    (+) ErrorCallback             : Error Callback.
+    (+) AbortCpltCallback         : Abort Complete Callback.
+    (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.
+    (+) AbortReceiveCpltCallback  : Abort Receive Complete Callback.
+    (+) WakeupCallback            : Wakeup Callback.
+    (+) RxFifoFullCallback        : Rx Fifo Full Callback.
+    (+) TxFifoEmptyCallback       : Tx Fifo Empty Callback.
+    (+) MspInitCallback           : UART MspInit.
+    (+) MspDeInitCallback         : UART MspDeInit.
+
+    [..]
+    For specific callback RxEventCallback, use dedicated registration/reset functions:
+    respectively HAL_UART_RegisterRxEventCallback() , HAL_UART_UnRegisterRxEventCallback().
+
+    [..]
+    By default, after the HAL_UART_Init() and when the state is HAL_UART_STATE_RESET
+    all callbacks are set to the corresponding weak (surcharged) functions:
+    examples HAL_UART_TxCpltCallback(), HAL_UART_RxHalfCpltCallback().
+    Exception done for MspInit and MspDeInit functions that are respectively
+    reset to the legacy weak (surcharged) functions in the HAL_UART_Init()
+    and HAL_UART_DeInit() only when these callbacks are null (not registered beforehand).
+    If not, MspInit or MspDeInit are not null, the HAL_UART_Init() and HAL_UART_DeInit()
+    keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
+
+    [..]
+    Callbacks can be registered/unregistered in HAL_UART_STATE_READY state only.
+    Exception done MspInit/MspDeInit that can be registered/unregistered
+    in HAL_UART_STATE_READY or HAL_UART_STATE_RESET state, thus registered (user)
+    MspInit/DeInit callbacks can be used during the Init/DeInit.
+    In that case first register the MspInit/MspDeInit user callbacks
+    using HAL_UART_RegisterCallback() before calling HAL_UART_DeInit()
+    or HAL_UART_Init() function.
+
+    [..]
+    When The compilation define USE_HAL_UART_REGISTER_CALLBACKS is set to 0 or
+    not defined, the callback registration feature is not available
+    and weak (surcharged) callbacks are used.
+
+
+  @endverbatim
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup UART UART
+  * @brief HAL UART module driver
+  * @{
+  */
+
+#ifdef HAL_UART_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup UART_Private_Constants UART Private Constants
+  * @{
+  */
+#define USART_CR1_FIELDS  ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | \
+                                      USART_CR1_OVER8 | USART_CR1_FIFOEN)) /*!< UART or USART CR1 fields of parameters set by UART_SetConfig API */
+
+#define USART_CR3_FIELDS  ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_ONEBIT | USART_CR3_TXFTCFG | \
+                                      USART_CR3_RXFTCFG)) /*!< UART or USART CR3 fields of parameters set by UART_SetConfig API */
+
+#define LPUART_BRR_MIN  0x00000300U  /* LPUART BRR minimum authorized value */
+#define LPUART_BRR_MAX  0x000FFFFFU  /* LPUART BRR maximum authorized value */
+
+#define UART_BRR_MIN    0x10U        /* UART BRR minimum authorized value */
+#define UART_BRR_MAX    0x0000FFFFU  /* UART BRR maximum authorized value */
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup UART_Private_Functions
+  * @{
+  */
+static void UART_EndTxTransfer(UART_HandleTypeDef *huart);
+static void UART_EndRxTransfer(UART_HandleTypeDef *huart);
+static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma);
+static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
+static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
+static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
+static void UART_DMAError(DMA_HandleTypeDef *hdma);
+static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma);
+static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
+static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
+static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
+static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
+static void UART_TxISR_8BIT(UART_HandleTypeDef *huart);
+static void UART_TxISR_16BIT(UART_HandleTypeDef *huart);
+static void UART_TxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart);
+static void UART_TxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart);
+static void UART_EndTransmit_IT(UART_HandleTypeDef *huart);
+static void UART_RxISR_8BIT(UART_HandleTypeDef *huart);
+static void UART_RxISR_16BIT(UART_HandleTypeDef *huart);
+static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart);
+static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart);
+/**
+  * @}
+  */
+
+/* Private variables ---------------------------------------------------------*/
+/** @addtogroup UART_Private_variables
+  * @{
+  */
+const uint16_t UARTPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U};
+/**
+  * @}
+  */
+
+/* Exported Constants --------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup UART_Exported_Functions UART Exported Functions
+  * @{
+  */
+
+/** @defgroup UART_Exported_Functions_Group1 Initialization and de-initialization functions
+  *  @brief    Initialization and Configuration functions
+  *
+@verbatim
+===============================================================================
+            ##### Initialization and Configuration functions #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to initialize the USARTx or the UARTy
+    in asynchronous mode.
+      (+) For the asynchronous mode the parameters below can be configured:
+        (++) Baud Rate
+        (++) Word Length
+        (++) Stop Bit
+        (++) Parity: If the parity is enabled, then the MSB bit of the data written
+             in the data register is transmitted but is changed by the parity bit.
+        (++) Hardware flow control
+        (++) Receiver/transmitter modes
+        (++) Over Sampling Method
+        (++) One-Bit Sampling Method
+      (+) For the asynchronous mode, the following advanced features can be configured as well:
+        (++) TX and/or RX pin level inversion
+        (++) data logical level inversion
+        (++) RX and TX pins swap
+        (++) RX overrun detection disabling
+        (++) DMA disabling on RX error
+        (++) MSB first on communication line
+        (++) auto Baud rate detection
+    [..]
+    The HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init()and HAL_MultiProcessor_Init()API
+    follow respectively the UART asynchronous, UART Half duplex, UART LIN mode
+    and UART multiprocessor mode configuration procedures (details for the procedures
+    are available in reference manual).
+
+@endverbatim
+
+  Depending on the frame length defined by the M1 and M0 bits (7-bit,
+  8-bit or 9-bit), the possible UART formats are listed in the
+  following table.
+
+  Table 1. UART frame format.
+    +-----------------------------------------------------------------------+
+    |  M1 bit |  M0 bit |  PCE bit  |             UART frame                |
+    |---------|---------|-----------|---------------------------------------|
+    |    0    |    0    |    0      |    | SB |    8 bit data   | STB |     |
+    |---------|---------|-----------|---------------------------------------|
+    |    0    |    0    |    1      |    | SB | 7 bit data | PB | STB |     |
+    |---------|---------|-----------|---------------------------------------|
+    |    0    |    1    |    0      |    | SB |    9 bit data   | STB |     |
+    |---------|---------|-----------|---------------------------------------|
+    |    0    |    1    |    1      |    | SB | 8 bit data | PB | STB |     |
+    |---------|---------|-----------|---------------------------------------|
+    |    1    |    0    |    0      |    | SB |    7 bit data   | STB |     |
+    |---------|---------|-----------|---------------------------------------|
+    |    1    |    0    |    1      |    | SB | 6 bit data | PB | STB |     |
+    +-----------------------------------------------------------------------+
+
+  * @{
+  */
+
+/**
+  * @brief Initialize the UART mode according to the specified
+  *        parameters in the UART_InitTypeDef and initialize the associated handle.
+  * @param huart UART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
+{
+  /* Check the UART handle allocation */
+  if (huart == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  if (huart->Init.HwFlowCtl != UART_HWCONTROL_NONE)
+  {
+    /* Check the parameters */
+    assert_param(IS_UART_HWFLOW_INSTANCE(huart->Instance));
+  }
+  else
+  {
+    /* Check the parameters */
+    assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance)));
+  }
+
+  if (huart->gState == HAL_UART_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    huart->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+    UART_InitCallbacksToDefault(huart);
+
+    if (huart->MspInitCallback == NULL)
+    {
+      huart->MspInitCallback = HAL_UART_MspInit;
+    }
+
+    /* Init the low level hardware */
+    huart->MspInitCallback(huart);
+#else
+    /* Init the low level hardware : GPIO, CLOCK */
+    HAL_UART_MspInit(huart);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+  }
+
+  huart->gState = HAL_UART_STATE_BUSY;
+
+  __HAL_UART_DISABLE(huart);
+
+  /* Set the UART Communication parameters */
+  if (UART_SetConfig(huart) == HAL_ERROR)
+  {
+    return HAL_ERROR;
+  }
+
+  if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
+  {
+    UART_AdvFeatureConfig(huart);
+  }
+
+  /* In asynchronous mode, the following bits must be kept cleared:
+  - LINEN and CLKEN bits in the USART_CR2 register,
+  - SCEN, HDSEL and IREN  bits in the USART_CR3 register.*/
+  CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+  CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
+
+  __HAL_UART_ENABLE(huart);
+
+  /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
+  return (UART_CheckIdleState(huart));
+}
+
+/**
+  * @brief Initialize the half-duplex mode according to the specified
+  *        parameters in the UART_InitTypeDef and creates the associated handle.
+  * @param huart UART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart)
+{
+  /* Check the UART handle allocation */
+  if (huart == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check UART instance */
+  assert_param(IS_UART_HALFDUPLEX_INSTANCE(huart->Instance));
+
+  if (huart->gState == HAL_UART_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    huart->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+    UART_InitCallbacksToDefault(huart);
+
+    if (huart->MspInitCallback == NULL)
+    {
+      huart->MspInitCallback = HAL_UART_MspInit;
+    }
+
+    /* Init the low level hardware */
+    huart->MspInitCallback(huart);
+#else
+    /* Init the low level hardware : GPIO, CLOCK */
+    HAL_UART_MspInit(huart);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+  }
+
+  huart->gState = HAL_UART_STATE_BUSY;
+
+  __HAL_UART_DISABLE(huart);
+
+  /* Set the UART Communication parameters */
+  if (UART_SetConfig(huart) == HAL_ERROR)
+  {
+    return HAL_ERROR;
+  }
+
+  if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
+  {
+    UART_AdvFeatureConfig(huart);
+  }
+
+  /* In half-duplex mode, the following bits must be kept cleared:
+  - LINEN and CLKEN bits in the USART_CR2 register,
+  - SCEN and IREN bits in the USART_CR3 register.*/
+  CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+  CLEAR_BIT(huart->Instance->CR3, (USART_CR3_IREN | USART_CR3_SCEN));
+
+  /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */
+  SET_BIT(huart->Instance->CR3, USART_CR3_HDSEL);
+
+  __HAL_UART_ENABLE(huart);
+
+  /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
+  return (UART_CheckIdleState(huart));
+}
+
+
+/**
+  * @brief Initialize the LIN mode according to the specified
+  *        parameters in the UART_InitTypeDef and creates the associated handle.
+  * @param huart             UART handle.
+  * @param BreakDetectLength Specifies the LIN break detection length.
+  *        This parameter can be one of the following values:
+  *          @arg @ref UART_LINBREAKDETECTLENGTH_10B 10-bit break detection
+  *          @arg @ref UART_LINBREAKDETECTLENGTH_11B 11-bit break detection
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength)
+{
+  /* Check the UART handle allocation */
+  if (huart == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the LIN UART instance */
+  assert_param(IS_UART_LIN_INSTANCE(huart->Instance));
+  /* Check the Break detection length parameter */
+  assert_param(IS_UART_LIN_BREAK_DETECT_LENGTH(BreakDetectLength));
+
+  /* LIN mode limited to 16-bit oversampling only */
+  if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
+  {
+    return HAL_ERROR;
+  }
+  /* LIN mode limited to 8-bit data length */
+  if (huart->Init.WordLength != UART_WORDLENGTH_8B)
+  {
+    return HAL_ERROR;
+  }
+
+  if (huart->gState == HAL_UART_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    huart->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+    UART_InitCallbacksToDefault(huart);
+
+    if (huart->MspInitCallback == NULL)
+    {
+      huart->MspInitCallback = HAL_UART_MspInit;
+    }
+
+    /* Init the low level hardware */
+    huart->MspInitCallback(huart);
+#else
+    /* Init the low level hardware : GPIO, CLOCK */
+    HAL_UART_MspInit(huart);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+  }
+
+  huart->gState = HAL_UART_STATE_BUSY;
+
+  __HAL_UART_DISABLE(huart);
+
+  /* Set the UART Communication parameters */
+  if (UART_SetConfig(huart) == HAL_ERROR)
+  {
+    return HAL_ERROR;
+  }
+
+  if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
+  {
+    UART_AdvFeatureConfig(huart);
+  }
+
+  /* In LIN mode, the following bits must be kept cleared:
+  - LINEN and CLKEN bits in the USART_CR2 register,
+  - SCEN and IREN bits in the USART_CR3 register.*/
+  CLEAR_BIT(huart->Instance->CR2, USART_CR2_CLKEN);
+  CLEAR_BIT(huart->Instance->CR3, (USART_CR3_HDSEL | USART_CR3_IREN | USART_CR3_SCEN));
+
+  /* Enable the LIN mode by setting the LINEN bit in the CR2 register */
+  SET_BIT(huart->Instance->CR2, USART_CR2_LINEN);
+
+  /* Set the USART LIN Break detection length. */
+  MODIFY_REG(huart->Instance->CR2, USART_CR2_LBDL, BreakDetectLength);
+
+  __HAL_UART_ENABLE(huart);
+
+  /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
+  return (UART_CheckIdleState(huart));
+}
+
+
+/**
+  * @brief Initialize the multiprocessor mode according to the specified
+  *        parameters in the UART_InitTypeDef and initialize the associated handle.
+  * @param huart        UART handle.
+  * @param Address      UART node address (4-, 6-, 7- or 8-bit long).
+  * @param WakeUpMethod Specifies the UART wakeup method.
+  *        This parameter can be one of the following values:
+  *          @arg @ref UART_WAKEUPMETHOD_IDLELINE WakeUp by an idle line detection
+  *          @arg @ref UART_WAKEUPMETHOD_ADDRESSMARK WakeUp by an address mark
+  * @note  If the user resorts to idle line detection wake up, the Address parameter
+  *        is useless and ignored by the initialization function.
+  * @note  If the user resorts to address mark wake up, the address length detection
+  *        is configured by default to 4 bits only. For the UART to be able to
+  *        manage 6-, 7- or 8-bit long addresses detection, the API
+  *        HAL_MultiProcessorEx_AddressLength_Set() must be called after
+  *        HAL_MultiProcessor_Init().
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod)
+{
+  /* Check the UART handle allocation */
+  if (huart == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the wake up method parameter */
+  assert_param(IS_UART_WAKEUPMETHOD(WakeUpMethod));
+
+  if (huart->gState == HAL_UART_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    huart->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+    UART_InitCallbacksToDefault(huart);
+
+    if (huart->MspInitCallback == NULL)
+    {
+      huart->MspInitCallback = HAL_UART_MspInit;
+    }
+
+    /* Init the low level hardware */
+    huart->MspInitCallback(huart);
+#else
+    /* Init the low level hardware : GPIO, CLOCK */
+    HAL_UART_MspInit(huart);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+  }
+
+  huart->gState = HAL_UART_STATE_BUSY;
+
+  __HAL_UART_DISABLE(huart);
+
+  /* Set the UART Communication parameters */
+  if (UART_SetConfig(huart) == HAL_ERROR)
+  {
+    return HAL_ERROR;
+  }
+
+  if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
+  {
+    UART_AdvFeatureConfig(huart);
+  }
+
+  /* In multiprocessor mode, the following bits must be kept cleared:
+  - LINEN and CLKEN bits in the USART_CR2 register,
+  - SCEN, HDSEL and IREN  bits in the USART_CR3 register. */
+  CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+  CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
+
+  if (WakeUpMethod == UART_WAKEUPMETHOD_ADDRESSMARK)
+  {
+    /* If address mark wake up method is chosen, set the USART address node */
+    MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)Address << UART_CR2_ADDRESS_LSB_POS));
+  }
+
+  /* Set the wake up method by setting the WAKE bit in the CR1 register */
+  MODIFY_REG(huart->Instance->CR1, USART_CR1_WAKE, WakeUpMethod);
+
+  __HAL_UART_ENABLE(huart);
+
+  /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
+  return (UART_CheckIdleState(huart));
+}
+
+
+/**
+  * @brief DeInitialize the UART peripheral.
+  * @param huart UART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart)
+{
+  /* Check the UART handle allocation */
+  if (huart == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance)));
+
+  huart->gState = HAL_UART_STATE_BUSY;
+
+  __HAL_UART_DISABLE(huart);
+
+  huart->Instance->CR1 = 0x0U;
+  huart->Instance->CR2 = 0x0U;
+  huart->Instance->CR3 = 0x0U;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+  if (huart->MspDeInitCallback == NULL)
+  {
+    huart->MspDeInitCallback = HAL_UART_MspDeInit;
+  }
+  /* DeInit the low level hardware */
+  huart->MspDeInitCallback(huart);
+#else
+  /* DeInit the low level hardware */
+  HAL_UART_MspDeInit(huart);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+
+  huart->ErrorCode = HAL_UART_ERROR_NONE;
+  huart->gState = HAL_UART_STATE_RESET;
+  huart->RxState = HAL_UART_STATE_RESET;
+  huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+  huart->RxEventType = HAL_UART_RXEVENT_TC;
+
+  __HAL_UNLOCK(huart);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Initialize the UART MSP.
+  * @param huart UART handle.
+  * @retval None
+  */
+__weak void HAL_UART_MspInit(UART_HandleTypeDef *huart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(huart);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_UART_MspInit can be implemented in the user file
+   */
+}
+
+/**
+  * @brief DeInitialize the UART MSP.
+  * @param huart UART handle.
+  * @retval None
+  */
+__weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(huart);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_UART_MspDeInit can be implemented in the user file
+   */
+}
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  Register a User UART Callback
+  *         To be used instead of the weak predefined callback
+  * @note   The HAL_UART_RegisterCallback() may be called before HAL_UART_Init(), HAL_HalfDuplex_Init(),
+  *         HAL_LIN_Init(), HAL_MultiProcessor_Init() or HAL_RS485Ex_Init() in HAL_UART_STATE_RESET to register
+  *         callbacks for HAL_UART_MSPINIT_CB_ID and HAL_UART_MSPDEINIT_CB_ID
+  * @param  huart uart handle
+  * @param  CallbackID ID of the callback to be registered
+  *         This parameter can be one of the following values:
+  *           @arg @ref HAL_UART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID
+  *           @arg @ref HAL_UART_TX_COMPLETE_CB_ID Tx Complete Callback ID
+  *           @arg @ref HAL_UART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID
+  *           @arg @ref HAL_UART_RX_COMPLETE_CB_ID Rx Complete Callback ID
+  *           @arg @ref HAL_UART_ERROR_CB_ID Error Callback ID
+  *           @arg @ref HAL_UART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
+  *           @arg @ref HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID
+  *           @arg @ref HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID
+  *           @arg @ref HAL_UART_WAKEUP_CB_ID Wakeup Callback ID
+  *           @arg @ref HAL_UART_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID
+  *           @arg @ref HAL_UART_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID
+  *           @arg @ref HAL_UART_MSPINIT_CB_ID MspInit Callback ID
+  *           @arg @ref HAL_UART_MSPDEINIT_CB_ID MspDeInit Callback ID
+  * @param  pCallback pointer to the Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID,
+                                            pUART_CallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+    return HAL_ERROR;
+  }
+
+  if (huart->gState == HAL_UART_STATE_READY)
+  {
+    switch (CallbackID)
+    {
+      case HAL_UART_TX_HALFCOMPLETE_CB_ID :
+        huart->TxHalfCpltCallback = pCallback;
+        break;
+
+      case HAL_UART_TX_COMPLETE_CB_ID :
+        huart->TxCpltCallback = pCallback;
+        break;
+
+      case HAL_UART_RX_HALFCOMPLETE_CB_ID :
+        huart->RxHalfCpltCallback = pCallback;
+        break;
+
+      case HAL_UART_RX_COMPLETE_CB_ID :
+        huart->RxCpltCallback = pCallback;
+        break;
+
+      case HAL_UART_ERROR_CB_ID :
+        huart->ErrorCallback = pCallback;
+        break;
+
+      case HAL_UART_ABORT_COMPLETE_CB_ID :
+        huart->AbortCpltCallback = pCallback;
+        break;
+
+      case HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID :
+        huart->AbortTransmitCpltCallback = pCallback;
+        break;
+
+      case HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID :
+        huart->AbortReceiveCpltCallback = pCallback;
+        break;
+
+      case HAL_UART_WAKEUP_CB_ID :
+        huart->WakeupCallback = pCallback;
+        break;
+
+      case HAL_UART_RX_FIFO_FULL_CB_ID :
+        huart->RxFifoFullCallback = pCallback;
+        break;
+
+      case HAL_UART_TX_FIFO_EMPTY_CB_ID :
+        huart->TxFifoEmptyCallback = pCallback;
+        break;
+
+      case HAL_UART_MSPINIT_CB_ID :
+        huart->MspInitCallback = pCallback;
+        break;
+
+      case HAL_UART_MSPDEINIT_CB_ID :
+        huart->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (huart->gState == HAL_UART_STATE_RESET)
+  {
+    switch (CallbackID)
+    {
+      case HAL_UART_MSPINIT_CB_ID :
+        huart->MspInitCallback = pCallback;
+        break;
+
+      case HAL_UART_MSPDEINIT_CB_ID :
+        huart->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Unregister an UART Callback
+  *         UART callaback is redirected to the weak predefined callback
+  * @note   The HAL_UART_UnRegisterCallback() may be called before HAL_UART_Init(), HAL_HalfDuplex_Init(),
+  *         HAL_LIN_Init(), HAL_MultiProcessor_Init() or HAL_RS485Ex_Init() in HAL_UART_STATE_RESET to un-register
+  *         callbacks for HAL_UART_MSPINIT_CB_ID and HAL_UART_MSPDEINIT_CB_ID
+  * @param  huart uart handle
+  * @param  CallbackID ID of the callback to be unregistered
+  *         This parameter can be one of the following values:
+  *           @arg @ref HAL_UART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID
+  *           @arg @ref HAL_UART_TX_COMPLETE_CB_ID Tx Complete Callback ID
+  *           @arg @ref HAL_UART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID
+  *           @arg @ref HAL_UART_RX_COMPLETE_CB_ID Rx Complete Callback ID
+  *           @arg @ref HAL_UART_ERROR_CB_ID Error Callback ID
+  *           @arg @ref HAL_UART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
+  *           @arg @ref HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID
+  *           @arg @ref HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID
+  *           @arg @ref HAL_UART_WAKEUP_CB_ID Wakeup Callback ID
+  *           @arg @ref HAL_UART_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID
+  *           @arg @ref HAL_UART_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID
+  *           @arg @ref HAL_UART_MSPINIT_CB_ID MspInit Callback ID
+  *           @arg @ref HAL_UART_MSPDEINIT_CB_ID MspDeInit Callback ID
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (HAL_UART_STATE_READY == huart->gState)
+  {
+    switch (CallbackID)
+    {
+      case HAL_UART_TX_HALFCOMPLETE_CB_ID :
+        huart->TxHalfCpltCallback = HAL_UART_TxHalfCpltCallback;               /* Legacy weak  TxHalfCpltCallback    */
+        break;
+
+      case HAL_UART_TX_COMPLETE_CB_ID :
+        huart->TxCpltCallback = HAL_UART_TxCpltCallback;                       /* Legacy weak TxCpltCallback         */
+        break;
+
+      case HAL_UART_RX_HALFCOMPLETE_CB_ID :
+        huart->RxHalfCpltCallback = HAL_UART_RxHalfCpltCallback;               /* Legacy weak RxHalfCpltCallback     */
+        break;
+
+      case HAL_UART_RX_COMPLETE_CB_ID :
+        huart->RxCpltCallback = HAL_UART_RxCpltCallback;                       /* Legacy weak RxCpltCallback         */
+        break;
+
+      case HAL_UART_ERROR_CB_ID :
+        huart->ErrorCallback = HAL_UART_ErrorCallback;                         /* Legacy weak ErrorCallback          */
+        break;
+
+      case HAL_UART_ABORT_COMPLETE_CB_ID :
+        huart->AbortCpltCallback = HAL_UART_AbortCpltCallback;                 /* Legacy weak AbortCpltCallback      */
+        break;
+
+      case HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID :
+        huart->AbortTransmitCpltCallback = HAL_UART_AbortTransmitCpltCallback; /* Legacy weak
+                                                                                  AbortTransmitCpltCallback          */
+        break;
+
+      case HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID :
+        huart->AbortReceiveCpltCallback = HAL_UART_AbortReceiveCpltCallback;   /* Legacy weak
+                                                                                  AbortReceiveCpltCallback           */
+        break;
+
+      case HAL_UART_WAKEUP_CB_ID :
+        huart->WakeupCallback = HAL_UARTEx_WakeupCallback;                     /* Legacy weak WakeupCallback         */
+        break;
+
+      case HAL_UART_RX_FIFO_FULL_CB_ID :
+        huart->RxFifoFullCallback = HAL_UARTEx_RxFifoFullCallback;             /* Legacy weak RxFifoFullCallback     */
+        break;
+
+      case HAL_UART_TX_FIFO_EMPTY_CB_ID :
+        huart->TxFifoEmptyCallback = HAL_UARTEx_TxFifoEmptyCallback;           /* Legacy weak TxFifoEmptyCallback    */
+        break;
+
+      case HAL_UART_MSPINIT_CB_ID :
+        huart->MspInitCallback = HAL_UART_MspInit;                             /* Legacy weak MspInitCallback        */
+        break;
+
+      case HAL_UART_MSPDEINIT_CB_ID :
+        huart->MspDeInitCallback = HAL_UART_MspDeInit;                         /* Legacy weak MspDeInitCallback      */
+        break;
+
+      default :
+        huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (HAL_UART_STATE_RESET == huart->gState)
+  {
+    switch (CallbackID)
+    {
+      case HAL_UART_MSPINIT_CB_ID :
+        huart->MspInitCallback = HAL_UART_MspInit;
+        break;
+
+      case HAL_UART_MSPDEINIT_CB_ID :
+        huart->MspDeInitCallback = HAL_UART_MspDeInit;
+        break;
+
+      default :
+        huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Register a User UART Rx Event Callback
+  *         To be used instead of the weak predefined callback
+  * @param  huart     Uart handle
+  * @param  pCallback Pointer to the Rx Event Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_RegisterRxEventCallback(UART_HandleTypeDef *huart, pUART_RxEventCallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+    return HAL_ERROR;
+  }
+
+  /* Process locked */
+  __HAL_LOCK(huart);
+
+  if (huart->gState == HAL_UART_STATE_READY)
+  {
+    huart->RxEventCallback = pCallback;
+  }
+  else
+  {
+    huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(huart);
+
+  return status;
+}
+
+/**
+  * @brief  UnRegister the UART Rx Event Callback
+  *         UART Rx Event Callback is redirected to the weak HAL_UARTEx_RxEventCallback() predefined callback
+  * @param  huart     Uart handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process locked */
+  __HAL_LOCK(huart);
+
+  if (huart->gState == HAL_UART_STATE_READY)
+  {
+    huart->RxEventCallback = HAL_UARTEx_RxEventCallback; /* Legacy weak UART Rx Event Callback  */
+  }
+  else
+  {
+    huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(huart);
+  return status;
+}
+
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/** @defgroup UART_Exported_Functions_Group2 IO operation functions
+  * @brief UART Transmit/Receive functions
+  *
+@verbatim
+ ===============================================================================
+                      ##### IO operation functions #####
+ ===============================================================================
+    This subsection provides a set of functions allowing to manage the UART asynchronous
+    and Half duplex data transfers.
+
+    (#) There are two mode of transfer:
+       (+) Blocking mode: The communication is performed in polling mode.
+           The HAL status of all data processing is returned by the same function
+           after finishing transfer.
+       (+) Non-Blocking mode: The communication is performed using Interrupts
+           or DMA, These API's return the HAL status.
+           The end of the data processing will be indicated through the
+           dedicated UART IRQ when using Interrupt mode or the DMA IRQ when
+           using DMA mode.
+           The HAL_UART_TxCpltCallback(), HAL_UART_RxCpltCallback() user callbacks
+           will be executed respectively at the end of the transmit or Receive process
+           The HAL_UART_ErrorCallback()user callback will be executed when a communication error is detected
+
+    (#) Blocking mode API's are :
+        (+) HAL_UART_Transmit()
+        (+) HAL_UART_Receive()
+
+    (#) Non-Blocking mode API's with Interrupt are :
+        (+) HAL_UART_Transmit_IT()
+        (+) HAL_UART_Receive_IT()
+        (+) HAL_UART_IRQHandler()
+
+    (#) Non-Blocking mode API's with DMA are :
+        (+) HAL_UART_Transmit_DMA()
+        (+) HAL_UART_Receive_DMA()
+        (+) HAL_UART_DMAPause()
+        (+) HAL_UART_DMAResume()
+        (+) HAL_UART_DMAStop()
+
+    (#) A set of Transfer Complete Callbacks are provided in Non_Blocking mode:
+        (+) HAL_UART_TxHalfCpltCallback()
+        (+) HAL_UART_TxCpltCallback()
+        (+) HAL_UART_RxHalfCpltCallback()
+        (+) HAL_UART_RxCpltCallback()
+        (+) HAL_UART_ErrorCallback()
+
+    (#) Non-Blocking mode transfers could be aborted using Abort API's :
+        (+) HAL_UART_Abort()
+        (+) HAL_UART_AbortTransmit()
+        (+) HAL_UART_AbortReceive()
+        (+) HAL_UART_Abort_IT()
+        (+) HAL_UART_AbortTransmit_IT()
+        (+) HAL_UART_AbortReceive_IT()
+
+    (#) For Abort services based on interrupts (HAL_UART_Abortxxx_IT), a set of Abort Complete Callbacks are provided:
+        (+) HAL_UART_AbortCpltCallback()
+        (+) HAL_UART_AbortTransmitCpltCallback()
+        (+) HAL_UART_AbortReceiveCpltCallback()
+
+    (#) A Rx Event Reception Callback (Rx event notification) is available for Non_Blocking modes of enhanced
+        reception services:
+        (+) HAL_UARTEx_RxEventCallback()
+
+    (#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
+        Errors are handled as follows :
+       (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
+           to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error
+           in Interrupt mode reception .
+           Received character is then retrieved and stored in Rx buffer, Error code is set to allow user
+           to identify error type, and HAL_UART_ErrorCallback() user callback is executed.
+           Transfer is kept ongoing on UART side.
+           If user wants to abort it, Abort services should be called by user.
+       (+) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
+           This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.
+           Error code is set to allow user to identify error type, and HAL_UART_ErrorCallback()
+           user callback is executed.
+
+    -@- In the Half duplex communication, it is forbidden to run the transmit
+        and receive process in parallel, the UART state HAL_UART_STATE_BUSY_TX_RX can't be useful.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief Send an amount of data in blocking mode.
+  * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+  *         the sent data is handled as a set of u16. In this case, Size must indicate the number
+  *         of u16 provided through pData.
+  * @note When FIFO mode is enabled, writing a data in the TDR register adds one
+  *       data to the TXFIFO. Write operations to the TDR register are performed
+  *       when TXFNF flag is set. From hardware perspective, TXFNF flag and
+  *       TXE are mapped on the same bit-field.
+  * @param huart   UART handle.
+  * @param pData   Pointer to data buffer (u8 or u16 data elements).
+  * @param Size    Amount of data elements (u8 or u16) to be sent.
+  * @param Timeout Timeout duration.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+  const uint8_t  *pdata8bits;
+  const uint16_t *pdata16bits;
+  uint32_t tickstart;
+
+  /* Check that a Tx process is not already ongoing */
+  if (huart->gState == HAL_UART_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      return  HAL_ERROR;
+    }
+
+    huart->ErrorCode = HAL_UART_ERROR_NONE;
+    huart->gState = HAL_UART_STATE_BUSY_TX;
+
+    /* Init tickstart for timeout management */
+    tickstart = HAL_GetTick();
+
+    huart->TxXferSize  = Size;
+    huart->TxXferCount = Size;
+
+    /* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */
+    if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
+    {
+      pdata8bits  = NULL;
+      pdata16bits = (const uint16_t *) pData;
+    }
+    else
+    {
+      pdata8bits  = pData;
+      pdata16bits = NULL;
+    }
+
+    while (huart->TxXferCount > 0U)
+    {
+      if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
+      {
+
+        huart->gState = HAL_UART_STATE_READY;
+
+        return HAL_TIMEOUT;
+      }
+      if (pdata8bits == NULL)
+      {
+        huart->Instance->TDR = (uint16_t)(*pdata16bits & 0x01FFU);
+        pdata16bits++;
+      }
+      else
+      {
+        huart->Instance->TDR = (uint8_t)(*pdata8bits & 0xFFU);
+        pdata8bits++;
+      }
+      huart->TxXferCount--;
+    }
+
+    if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
+    {
+      huart->gState = HAL_UART_STATE_READY;
+
+      return HAL_TIMEOUT;
+    }
+
+    /* At end of Tx process, restore huart->gState to Ready */
+    huart->gState = HAL_UART_STATE_READY;
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief Receive an amount of data in blocking mode.
+  * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+  *         the received data is handled as a set of u16. In this case, Size must indicate the number
+  *         of u16 available through pData.
+  * @note When FIFO mode is enabled, the RXFNE flag is set as long as the RXFIFO
+  *       is not empty. Read operations from the RDR register are performed when
+  *       RXFNE flag is set. From hardware perspective, RXFNE flag and
+  *       RXNE are mapped on the same bit-field.
+  * @param huart   UART handle.
+  * @param pData   Pointer to data buffer (u8 or u16 data elements).
+  * @param Size    Amount of data elements (u8 or u16) to be received.
+  * @param Timeout Timeout duration.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+  uint8_t  *pdata8bits;
+  uint16_t *pdata16bits;
+  uint16_t uhMask;
+  uint32_t tickstart;
+
+  /* Check that a Rx process is not already ongoing */
+  if (huart->RxState == HAL_UART_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      return  HAL_ERROR;
+    }
+
+    huart->ErrorCode = HAL_UART_ERROR_NONE;
+    huart->RxState = HAL_UART_STATE_BUSY_RX;
+    huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+    /* Init tickstart for timeout management */
+    tickstart = HAL_GetTick();
+
+    huart->RxXferSize  = Size;
+    huart->RxXferCount = Size;
+
+    /* Computation of UART mask to apply to RDR register */
+    UART_MASK_COMPUTATION(huart);
+    uhMask = huart->Mask;
+
+    /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */
+    if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
+    {
+      pdata8bits  = NULL;
+      pdata16bits = (uint16_t *) pData;
+    }
+    else
+    {
+      pdata8bits  = pData;
+      pdata16bits = NULL;
+    }
+
+    /* as long as data have to be received */
+    while (huart->RxXferCount > 0U)
+    {
+      if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
+      {
+        huart->RxState = HAL_UART_STATE_READY;
+
+        return HAL_TIMEOUT;
+      }
+      if (pdata8bits == NULL)
+      {
+        *pdata16bits = (uint16_t)(huart->Instance->RDR & uhMask);
+        pdata16bits++;
+      }
+      else
+      {
+        *pdata8bits = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask);
+        pdata8bits++;
+      }
+      huart->RxXferCount--;
+    }
+
+    /* At end of Rx process, restore huart->RxState to Ready */
+    huart->RxState = HAL_UART_STATE_READY;
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief Send an amount of data in interrupt mode.
+  * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+  *         the sent data is handled as a set of u16. In this case, Size must indicate the number
+  *         of u16 provided through pData.
+  * @param huart UART handle.
+  * @param pData Pointer to data buffer (u8 or u16 data elements).
+  * @param Size  Amount of data elements (u8 or u16) to be sent.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size)
+{
+  /* Check that a Tx process is not already ongoing */
+  if (huart->gState == HAL_UART_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      return HAL_ERROR;
+    }
+
+    huart->pTxBuffPtr  = pData;
+    huart->TxXferSize  = Size;
+    huart->TxXferCount = Size;
+    huart->TxISR       = NULL;
+
+    huart->ErrorCode = HAL_UART_ERROR_NONE;
+    huart->gState = HAL_UART_STATE_BUSY_TX;
+
+    /* Configure Tx interrupt processing */
+    if (huart->FifoMode == UART_FIFOMODE_ENABLE)
+    {
+      /* Set the Tx ISR function pointer according to the data word length */
+      if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
+      {
+        huart->TxISR = UART_TxISR_16BIT_FIFOEN;
+      }
+      else
+      {
+        huart->TxISR = UART_TxISR_8BIT_FIFOEN;
+      }
+
+      /* Enable the TX FIFO threshold interrupt */
+      ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
+    }
+    else
+    {
+      /* Set the Tx ISR function pointer according to the data word length */
+      if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
+      {
+        huart->TxISR = UART_TxISR_16BIT;
+      }
+      else
+      {
+        huart->TxISR = UART_TxISR_8BIT;
+      }
+
+      /* Enable the Transmit Data Register Empty interrupt */
+      ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
+    }
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief Receive an amount of data in interrupt mode.
+  * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+  *         the received data is handled as a set of u16. In this case, Size must indicate the number
+  *         of u16 available through pData.
+  * @param huart UART handle.
+  * @param pData Pointer to data buffer (u8 or u16 data elements).
+  * @param Size  Amount of data elements (u8 or u16) to be received.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
+{
+  /* Check that a Rx process is not already ongoing */
+  if (huart->RxState == HAL_UART_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      return HAL_ERROR;
+    }
+
+    /* Set Reception type to Standard reception */
+    huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+    if (!(IS_LPUART_INSTANCE(huart->Instance)))
+    {
+      /* Check that USART RTOEN bit is set */
+      if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
+      {
+        /* Enable the UART Receiver Timeout Interrupt */
+        ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
+      }
+    }
+
+    return (UART_Start_Receive_IT(huart, pData, Size));
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief Send an amount of data in DMA mode.
+  * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+  *         the sent data is handled as a set of u16. In this case, Size must indicate the number
+  *         of u16 provided through pData.
+  * @param huart UART handle.
+  * @param pData Pointer to data buffer (u8 or u16 data elements).
+  * @param Size  Amount of data elements (u8 or u16) to be sent.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size)
+{
+  /* Check that a Tx process is not already ongoing */
+  if (huart->gState == HAL_UART_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      return HAL_ERROR;
+    }
+
+    huart->pTxBuffPtr  = pData;
+    huart->TxXferSize  = Size;
+    huart->TxXferCount = Size;
+
+    huart->ErrorCode = HAL_UART_ERROR_NONE;
+    huart->gState = HAL_UART_STATE_BUSY_TX;
+
+    if (huart->hdmatx != NULL)
+    {
+      /* Set the UART DMA transfer complete callback */
+      huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt;
+
+      /* Set the UART DMA Half transfer complete callback */
+      huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt;
+
+      /* Set the DMA error callback */
+      huart->hdmatx->XferErrorCallback = UART_DMAError;
+
+      /* Set the DMA abort callback */
+      huart->hdmatx->XferAbortCallback = NULL;
+
+      /* Enable the UART transmit DMA channel */
+      if (HAL_DMA_Start_IT(huart->hdmatx, (uint32_t)huart->pTxBuffPtr, (uint32_t)&huart->Instance->TDR, Size) != HAL_OK)
+      {
+        /* Set error code to DMA */
+        huart->ErrorCode = HAL_UART_ERROR_DMA;
+
+        /* Restore huart->gState to ready */
+        huart->gState = HAL_UART_STATE_READY;
+
+        return HAL_ERROR;
+      }
+    }
+    /* Clear the TC flag in the ICR register */
+    __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_TCF);
+
+    /* Enable the DMA transfer for transmit request by setting the DMAT bit
+    in the UART CR3 register */
+    ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief Receive an amount of data in DMA mode.
+  * @note   When the UART parity is enabled (PCE = 1), the received data contain
+  *         the parity bit (MSB position).
+  * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+  *         the received data is handled as a set of u16. In this case, Size must indicate the number
+  *         of u16 available through pData.
+  * @param huart UART handle.
+  * @param pData Pointer to data buffer (u8 or u16 data elements).
+  * @param Size  Amount of data elements (u8 or u16) to be received.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
+{
+  /* Check that a Rx process is not already ongoing */
+  if (huart->RxState == HAL_UART_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      return HAL_ERROR;
+    }
+
+    /* Set Reception type to Standard reception */
+    huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+    if (!(IS_LPUART_INSTANCE(huart->Instance)))
+    {
+      /* Check that USART RTOEN bit is set */
+      if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
+      {
+        /* Enable the UART Receiver Timeout Interrupt */
+        ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
+      }
+    }
+
+    return (UART_Start_Receive_DMA(huart, pData, Size));
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief Pause the DMA Transfer.
+  * @param huart UART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart)
+{
+  const HAL_UART_StateTypeDef gstate = huart->gState;
+  const HAL_UART_StateTypeDef rxstate = huart->RxState;
+
+  if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) &&
+      (gstate == HAL_UART_STATE_BUSY_TX))
+  {
+    /* Disable the UART DMA Tx request */
+    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+  }
+  if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) &&
+      (rxstate == HAL_UART_STATE_BUSY_RX))
+  {
+    /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
+    ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+    /* Disable the UART DMA Rx request */
+    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Resume the DMA Transfer.
+  * @param huart UART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart)
+{
+  if (huart->gState == HAL_UART_STATE_BUSY_TX)
+  {
+    /* Enable the UART DMA Tx request */
+    ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+  }
+  if (huart->RxState == HAL_UART_STATE_BUSY_RX)
+  {
+    /* Clear the Overrun flag before resuming the Rx transfer */
+    __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
+
+    /* Re-enable PE and ERR (Frame error, noise error, overrun error) interrupts */
+    if (huart->Init.Parity != UART_PARITY_NONE)
+    {
+      ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+    }
+    ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+    /* Enable the UART DMA Rx request */
+    ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Stop the DMA Transfer.
+  * @param huart UART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart)
+{
+  /* The Lock is not implemented on this API to allow the user application
+     to call the HAL UART API under callbacks HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback() /
+     HAL_UART_TxHalfCpltCallback / HAL_UART_RxHalfCpltCallback:
+     indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete
+     interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of
+     the stream and the corresponding call back is executed. */
+
+  const HAL_UART_StateTypeDef gstate = huart->gState;
+  const HAL_UART_StateTypeDef rxstate = huart->RxState;
+
+  /* Stop UART DMA Tx request if ongoing */
+  if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) &&
+      (gstate == HAL_UART_STATE_BUSY_TX))
+  {
+    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+
+    /* Abort the UART DMA Tx channel */
+    if (huart->hdmatx != NULL)
+    {
+      if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK)
+      {
+        if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
+        {
+          /* Set error code to DMA */
+          huart->ErrorCode = HAL_UART_ERROR_DMA;
+
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+
+    UART_EndTxTransfer(huart);
+  }
+
+  /* Stop UART DMA Rx request if ongoing */
+  if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) &&
+      (rxstate == HAL_UART_STATE_BUSY_RX))
+  {
+    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+    /* Abort the UART DMA Rx channel */
+    if (huart->hdmarx != NULL)
+    {
+      if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK)
+      {
+        if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
+        {
+          /* Set error code to DMA */
+          huart->ErrorCode = HAL_UART_ERROR_DMA;
+
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+
+    UART_EndRxTransfer(huart);
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Abort ongoing transfers (blocking mode).
+  * @param  huart UART handle.
+  * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
+  *         This procedure performs following operations :
+  *           - Disable UART Interrupts (Tx and Rx)
+  *           - Disable the DMA transfer in the peripheral register (if enabled)
+  *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+  *           - Set handle State to READY
+  * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart)
+{
+  /* Disable TXE, TC, RXNE, PE, RXFT, TXFT and ERR (Frame error, noise error, overrun error) interrupts */
+  ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE |
+                                          USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
+  ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE);
+
+  /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */
+  if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+  {
+    ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE));
+  }
+
+  /* Abort the UART DMA Tx channel if enabled */
+  if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
+  {
+    /* Disable the UART DMA Tx request if enabled */
+    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+
+    /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */
+    if (huart->hdmatx != NULL)
+    {
+      /* Set the UART DMA Abort callback to Null.
+         No call back execution at end of DMA abort procedure */
+      huart->hdmatx->XferAbortCallback = NULL;
+
+      if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK)
+      {
+        if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
+        {
+          /* Set error code to DMA */
+          huart->ErrorCode = HAL_UART_ERROR_DMA;
+
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+  }
+
+  /* Abort the UART DMA Rx channel if enabled */
+  if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+  {
+    /* Disable the UART DMA Rx request if enabled */
+    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+    /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */
+    if (huart->hdmarx != NULL)
+    {
+      /* Set the UART DMA Abort callback to Null.
+         No call back execution at end of DMA abort procedure */
+      huart->hdmarx->XferAbortCallback = NULL;
+
+      if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK)
+      {
+        if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
+        {
+          /* Set error code to DMA */
+          huart->ErrorCode = HAL_UART_ERROR_DMA;
+
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+  }
+
+  /* Reset Tx and Rx transfer counters */
+  huart->TxXferCount = 0U;
+  huart->RxXferCount = 0U;
+
+  /* Clear the Error flags in the ICR register */
+  __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
+
+  /* Flush the whole TX FIFO (if needed) */
+  if (huart->FifoMode == UART_FIFOMODE_ENABLE)
+  {
+    __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST);
+  }
+
+  /* Discard the received data */
+  __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+
+  /* Restore huart->gState and huart->RxState to Ready */
+  huart->gState  = HAL_UART_STATE_READY;
+  huart->RxState = HAL_UART_STATE_READY;
+  huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+  huart->ErrorCode = HAL_UART_ERROR_NONE;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Abort ongoing Transmit transfer (blocking mode).
+  * @param  huart UART handle.
+  * @note   This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
+  *         This procedure performs following operations :
+  *           - Disable UART Interrupts (Tx)
+  *           - Disable the DMA transfer in the peripheral register (if enabled)
+  *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+  *           - Set handle State to READY
+  * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart)
+{
+  /* Disable TCIE, TXEIE and TXFTIE interrupts */
+  ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TCIE | USART_CR1_TXEIE_TXFNFIE));
+  ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
+
+  /* Abort the UART DMA Tx channel if enabled */
+  if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
+  {
+    /* Disable the UART DMA Tx request if enabled */
+    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+
+    /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */
+    if (huart->hdmatx != NULL)
+    {
+      /* Set the UART DMA Abort callback to Null.
+         No call back execution at end of DMA abort procedure */
+      huart->hdmatx->XferAbortCallback = NULL;
+
+      if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK)
+      {
+        if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
+        {
+          /* Set error code to DMA */
+          huart->ErrorCode = HAL_UART_ERROR_DMA;
+
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+  }
+
+  /* Reset Tx transfer counter */
+  huart->TxXferCount = 0U;
+
+  /* Flush the whole TX FIFO (if needed) */
+  if (huart->FifoMode == UART_FIFOMODE_ENABLE)
+  {
+    __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST);
+  }
+
+  /* Restore huart->gState to Ready */
+  huart->gState = HAL_UART_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Abort ongoing Receive transfer (blocking mode).
+  * @param  huart UART handle.
+  * @note   This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
+  *         This procedure performs following operations :
+  *           - Disable UART Interrupts (Rx)
+  *           - Disable the DMA transfer in the peripheral register (if enabled)
+  *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+  *           - Set handle State to READY
+  * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart)
+{
+  /* Disable PEIE, EIE, RXNEIE and RXFTIE interrupts */
+  ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE));
+  ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE | USART_CR3_RXFTIE);
+
+  /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */
+  if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+  {
+    ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE));
+  }
+
+  /* Abort the UART DMA Rx channel if enabled */
+  if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+  {
+    /* Disable the UART DMA Rx request if enabled */
+    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+    /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */
+    if (huart->hdmarx != NULL)
+    {
+      /* Set the UART DMA Abort callback to Null.
+         No call back execution at end of DMA abort procedure */
+      huart->hdmarx->XferAbortCallback = NULL;
+
+      if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK)
+      {
+        if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
+        {
+          /* Set error code to DMA */
+          huart->ErrorCode = HAL_UART_ERROR_DMA;
+
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+  }
+
+  /* Reset Rx transfer counter */
+  huart->RxXferCount = 0U;
+
+  /* Clear the Error flags in the ICR register */
+  __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
+
+  /* Discard the received data */
+  __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+
+  /* Restore huart->RxState to Ready */
+  huart->RxState = HAL_UART_STATE_READY;
+  huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Abort ongoing transfers (Interrupt mode).
+  * @param  huart UART handle.
+  * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
+  *         This procedure performs following operations :
+  *           - Disable UART Interrupts (Tx and Rx)
+  *           - Disable the DMA transfer in the peripheral register (if enabled)
+  *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+  *           - Set handle State to READY
+  *           - At abort completion, call user abort complete callback
+  * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
+  *         considered as completed only when user abort complete callback is executed (not when exiting function).
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart)
+{
+  uint32_t abortcplt = 1U;
+
+  /* Disable interrupts */
+  ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_TCIE | USART_CR1_RXNEIE_RXFNEIE |
+                                          USART_CR1_TXEIE_TXFNFIE));
+  ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE));
+
+  /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */
+  if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+  {
+    ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE));
+  }
+
+  /* If DMA Tx and/or DMA Rx Handles are associated to UART Handle, DMA Abort complete callbacks should be initialised
+     before any call to DMA Abort functions */
+  /* DMA Tx Handle is valid */
+  if (huart->hdmatx != NULL)
+  {
+    /* Set DMA Abort Complete callback if UART DMA Tx request if enabled.
+       Otherwise, set it to NULL */
+    if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
+    {
+      huart->hdmatx->XferAbortCallback = UART_DMATxAbortCallback;
+    }
+    else
+    {
+      huart->hdmatx->XferAbortCallback = NULL;
+    }
+  }
+  /* DMA Rx Handle is valid */
+  if (huart->hdmarx != NULL)
+  {
+    /* Set DMA Abort Complete callback if UART DMA Rx request if enabled.
+       Otherwise, set it to NULL */
+    if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+    {
+      huart->hdmarx->XferAbortCallback = UART_DMARxAbortCallback;
+    }
+    else
+    {
+      huart->hdmarx->XferAbortCallback = NULL;
+    }
+  }
+
+  /* Abort the UART DMA Tx channel if enabled */
+  if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
+  {
+    /* Disable DMA Tx at UART level */
+    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+
+    /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */
+    if (huart->hdmatx != NULL)
+    {
+      /* UART Tx DMA Abort callback has already been initialised :
+         will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
+
+      /* Abort DMA TX */
+      if (HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK)
+      {
+        huart->hdmatx->XferAbortCallback = NULL;
+      }
+      else
+      {
+        abortcplt = 0U;
+      }
+    }
+  }
+
+  /* Abort the UART DMA Rx channel if enabled */
+  if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+  {
+    /* Disable the UART DMA Rx request if enabled */
+    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+    /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */
+    if (huart->hdmarx != NULL)
+    {
+      /* UART Rx DMA Abort callback has already been initialised :
+         will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
+
+      /* Abort DMA RX */
+      if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
+      {
+        huart->hdmarx->XferAbortCallback = NULL;
+        abortcplt = 1U;
+      }
+      else
+      {
+        abortcplt = 0U;
+      }
+    }
+  }
+
+  /* if no DMA abort complete callback execution is required => call user Abort Complete callback */
+  if (abortcplt == 1U)
+  {
+    /* Reset Tx and Rx transfer counters */
+    huart->TxXferCount = 0U;
+    huart->RxXferCount = 0U;
+
+    /* Clear ISR function pointers */
+    huart->RxISR = NULL;
+    huart->TxISR = NULL;
+
+    /* Reset errorCode */
+    huart->ErrorCode = HAL_UART_ERROR_NONE;
+
+    /* Clear the Error flags in the ICR register */
+    __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
+
+    /* Flush the whole TX FIFO (if needed) */
+    if (huart->FifoMode == UART_FIFOMODE_ENABLE)
+    {
+      __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST);
+    }
+
+    /* Discard the received data */
+    __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+
+    /* Restore huart->gState and huart->RxState to Ready */
+    huart->gState  = HAL_UART_STATE_READY;
+    huart->RxState = HAL_UART_STATE_READY;
+    huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+    /* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+    /* Call registered Abort complete callback */
+    huart->AbortCpltCallback(huart);
+#else
+    /* Call legacy weak Abort complete callback */
+    HAL_UART_AbortCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Abort ongoing Transmit transfer (Interrupt mode).
+  * @param  huart UART handle.
+  * @note   This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
+  *         This procedure performs following operations :
+  *           - Disable UART Interrupts (Tx)
+  *           - Disable the DMA transfer in the peripheral register (if enabled)
+  *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+  *           - Set handle State to READY
+  *           - At abort completion, call user abort complete callback
+  * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
+  *         considered as completed only when user abort complete callback is executed (not when exiting function).
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart)
+{
+  /* Disable interrupts */
+  ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TCIE | USART_CR1_TXEIE_TXFNFIE));
+  ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
+
+  /* Abort the UART DMA Tx channel if enabled */
+  if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
+  {
+    /* Disable the UART DMA Tx request if enabled */
+    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+
+    /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */
+    if (huart->hdmatx != NULL)
+    {
+      /* Set the UART DMA Abort callback :
+         will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
+      huart->hdmatx->XferAbortCallback = UART_DMATxOnlyAbortCallback;
+
+      /* Abort DMA TX */
+      if (HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK)
+      {
+        /* Call Directly huart->hdmatx->XferAbortCallback function in case of error */
+        huart->hdmatx->XferAbortCallback(huart->hdmatx);
+      }
+    }
+    else
+    {
+      /* Reset Tx transfer counter */
+      huart->TxXferCount = 0U;
+
+      /* Clear TxISR function pointers */
+      huart->TxISR = NULL;
+
+      /* Restore huart->gState to Ready */
+      huart->gState = HAL_UART_STATE_READY;
+
+      /* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+      /* Call registered Abort Transmit Complete Callback */
+      huart->AbortTransmitCpltCallback(huart);
+#else
+      /* Call legacy weak Abort Transmit Complete Callback */
+      HAL_UART_AbortTransmitCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+    }
+  }
+  else
+  {
+    /* Reset Tx transfer counter */
+    huart->TxXferCount = 0U;
+
+    /* Clear TxISR function pointers */
+    huart->TxISR = NULL;
+
+    /* Flush the whole TX FIFO (if needed) */
+    if (huart->FifoMode == UART_FIFOMODE_ENABLE)
+    {
+      __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST);
+    }
+
+    /* Restore huart->gState to Ready */
+    huart->gState = HAL_UART_STATE_READY;
+
+    /* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+    /* Call registered Abort Transmit Complete Callback */
+    huart->AbortTransmitCpltCallback(huart);
+#else
+    /* Call legacy weak Abort Transmit Complete Callback */
+    HAL_UART_AbortTransmitCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Abort ongoing Receive transfer (Interrupt mode).
+  * @param  huart UART handle.
+  * @note   This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
+  *         This procedure performs following operations :
+  *           - Disable UART Interrupts (Rx)
+  *           - Disable the DMA transfer in the peripheral register (if enabled)
+  *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+  *           - Set handle State to READY
+  *           - At abort completion, call user abort complete callback
+  * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
+  *         considered as completed only when user abort complete callback is executed (not when exiting function).
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart)
+{
+  /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+  ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE));
+  ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
+
+  /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */
+  if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+  {
+    ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE));
+  }
+
+  /* Abort the UART DMA Rx channel if enabled */
+  if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+  {
+    /* Disable the UART DMA Rx request if enabled */
+    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+    /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */
+    if (huart->hdmarx != NULL)
+    {
+      /* Set the UART DMA Abort callback :
+         will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
+      huart->hdmarx->XferAbortCallback = UART_DMARxOnlyAbortCallback;
+
+      /* Abort DMA RX */
+      if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
+      {
+        /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */
+        huart->hdmarx->XferAbortCallback(huart->hdmarx);
+      }
+    }
+    else
+    {
+      /* Reset Rx transfer counter */
+      huart->RxXferCount = 0U;
+
+      /* Clear RxISR function pointer */
+      huart->pRxBuffPtr = NULL;
+
+      /* Clear the Error flags in the ICR register */
+      __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
+
+      /* Discard the received data */
+      __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+
+      /* Restore huart->RxState to Ready */
+      huart->RxState = HAL_UART_STATE_READY;
+      huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+      /* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+      /* Call registered Abort Receive Complete Callback */
+      huart->AbortReceiveCpltCallback(huart);
+#else
+      /* Call legacy weak Abort Receive Complete Callback */
+      HAL_UART_AbortReceiveCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+    }
+  }
+  else
+  {
+    /* Reset Rx transfer counter */
+    huart->RxXferCount = 0U;
+
+    /* Clear RxISR function pointer */
+    huart->pRxBuffPtr = NULL;
+
+    /* Clear the Error flags in the ICR register */
+    __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
+
+    /* Restore huart->RxState to Ready */
+    huart->RxState = HAL_UART_STATE_READY;
+    huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+    /* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+    /* Call registered Abort Receive Complete Callback */
+    huart->AbortReceiveCpltCallback(huart);
+#else
+    /* Call legacy weak Abort Receive Complete Callback */
+    HAL_UART_AbortReceiveCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Handle UART interrupt request.
+  * @param huart UART handle.
+  * @retval None
+  */
+void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
+{
+  uint32_t isrflags   = READ_REG(huart->Instance->ISR);
+  uint32_t cr1its     = READ_REG(huart->Instance->CR1);
+  uint32_t cr3its     = READ_REG(huart->Instance->CR3);
+
+  uint32_t errorflags;
+  uint32_t errorcode;
+
+  /* If no error occurs */
+  errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF));
+  if (errorflags == 0U)
+  {
+    /* UART in mode Receiver ---------------------------------------------------*/
+    if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U)
+        && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U)
+            || ((cr3its & USART_CR3_RXFTIE) != 0U)))
+    {
+      if (huart->RxISR != NULL)
+      {
+        huart->RxISR(huart);
+      }
+      return;
+    }
+  }
+
+  /* If some errors occur */
+  if ((errorflags != 0U)
+      && ((((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U)
+           || ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_RTOIE)) != 0U))))
+  {
+    /* UART parity error interrupt occurred -------------------------------------*/
+    if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))
+    {
+      __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF);
+
+      huart->ErrorCode |= HAL_UART_ERROR_PE;
+    }
+
+    /* UART frame error interrupt occurred --------------------------------------*/
+    if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
+    {
+      __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF);
+
+      huart->ErrorCode |= HAL_UART_ERROR_FE;
+    }
+
+    /* UART noise error interrupt occurred --------------------------------------*/
+    if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
+    {
+      __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF);
+
+      huart->ErrorCode |= HAL_UART_ERROR_NE;
+    }
+
+    /* UART Over-Run interrupt occurred -----------------------------------------*/
+    if (((isrflags & USART_ISR_ORE) != 0U)
+        && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) ||
+            ((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U)))
+    {
+      __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
+
+      huart->ErrorCode |= HAL_UART_ERROR_ORE;
+    }
+
+    /* UART Receiver Timeout interrupt occurred ---------------------------------*/
+    if (((isrflags & USART_ISR_RTOF) != 0U) && ((cr1its & USART_CR1_RTOIE) != 0U))
+    {
+      __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF);
+
+      huart->ErrorCode |= HAL_UART_ERROR_RTO;
+    }
+
+    /* Call UART Error Call back function if need be ----------------------------*/
+    if (huart->ErrorCode != HAL_UART_ERROR_NONE)
+    {
+      /* UART in mode Receiver --------------------------------------------------*/
+      if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U)
+          && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U)
+              || ((cr3its & USART_CR3_RXFTIE) != 0U)))
+      {
+        if (huart->RxISR != NULL)
+        {
+          huart->RxISR(huart);
+        }
+      }
+
+      /* If Error is to be considered as blocking :
+          - Receiver Timeout error in Reception
+          - Overrun error in Reception
+          - any error occurs in DMA mode reception
+      */
+      errorcode = huart->ErrorCode;
+      if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) ||
+          ((errorcode & (HAL_UART_ERROR_RTO | HAL_UART_ERROR_ORE)) != 0U))
+      {
+        /* Blocking error : transfer is aborted
+           Set the UART state ready to be able to start again the process,
+           Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
+        UART_EndRxTransfer(huart);
+
+        /* Abort the UART DMA Rx channel if enabled */
+        if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+        {
+          /* Disable the UART DMA Rx request if enabled */
+          ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+          /* Abort the UART DMA Rx channel */
+          if (huart->hdmarx != NULL)
+          {
+            /* Set the UART DMA Abort callback :
+               will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */
+            huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError;
+
+            /* Abort DMA RX */
+            if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
+            {
+              /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */
+              huart->hdmarx->XferAbortCallback(huart->hdmarx);
+            }
+          }
+          else
+          {
+            /* Call user error callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+            /*Call registered error callback*/
+            huart->ErrorCallback(huart);
+#else
+            /*Call legacy weak error callback*/
+            HAL_UART_ErrorCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+
+          }
+        }
+        else
+        {
+          /* Call user error callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+          /*Call registered error callback*/
+          huart->ErrorCallback(huart);
+#else
+          /*Call legacy weak error callback*/
+          HAL_UART_ErrorCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+        }
+      }
+      else
+      {
+        /* Non Blocking error : transfer could go on.
+           Error is notified to user through user error callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+        /*Call registered error callback*/
+        huart->ErrorCallback(huart);
+#else
+        /*Call legacy weak error callback*/
+        HAL_UART_ErrorCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+        huart->ErrorCode = HAL_UART_ERROR_NONE;
+      }
+    }
+    return;
+
+  } /* End if some error occurs */
+
+  /* Check current reception Mode :
+     If Reception till IDLE event has been selected : */
+  if ((huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+      && ((isrflags & USART_ISR_IDLE) != 0U)
+      && ((cr1its & USART_ISR_IDLE) != 0U))
+  {
+    __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
+
+    /* Check if DMA mode is enabled in UART */
+    if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+    {
+      /* DMA mode enabled */
+      /* Check received length : If all expected data are received, do nothing,
+         (DMA cplt callback will be called).
+         Otherwise, if at least one data has already been received, IDLE event is to be notified to user */
+      uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(huart->hdmarx);
+      if ((nb_remaining_rx_data > 0U)
+          && (nb_remaining_rx_data < huart->RxXferSize))
+      {
+        /* Reception is not complete */
+        huart->RxXferCount = nb_remaining_rx_data;
+
+        /* In Normal mode, end DMA xfer and HAL UART Rx process*/
+        if (huart->hdmarx->Init.Mode != DMA_CIRCULAR)
+        {
+          /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
+          ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+          ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+          /* Disable the DMA transfer for the receiver request by resetting the DMAR bit
+             in the UART CR3 register */
+          ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+          /* At end of Rx process, restore huart->RxState to Ready */
+          huart->RxState = HAL_UART_STATE_READY;
+          huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+          ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+
+          /* Last bytes received, so no need as the abort is immediate */
+          (void)HAL_DMA_Abort(huart->hdmarx);
+        }
+
+        /* Initialize type of RxEvent that correspond to RxEvent callback execution;
+           In this case, Rx Event type is Idle Event */
+        huart->RxEventType = HAL_UART_RXEVENT_IDLE;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+        /*Call registered Rx Event callback*/
+        huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
+#else
+        /*Call legacy weak Rx Event callback*/
+        HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+      }
+      return;
+    }
+    else
+    {
+      /* DMA mode not enabled */
+      /* Check received length : If all expected data are received, do nothing.
+         Otherwise, if at least one data has already been received, IDLE event is to be notified to user */
+      uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount;
+      if ((huart->RxXferCount > 0U)
+          && (nb_rx_data > 0U))
+      {
+        /* Disable the UART Parity Error Interrupt and RXNE interrupts */
+        ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
+
+        /* Disable the UART Error Interrupt:(Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */
+        ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
+
+        /* Rx process is completed, restore huart->RxState to Ready */
+        huart->RxState = HAL_UART_STATE_READY;
+        huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+        /* Clear RxISR function pointer */
+        huart->RxISR = NULL;
+
+        ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+
+        /* Initialize type of RxEvent that correspond to RxEvent callback execution;
+           In this case, Rx Event type is Idle Event */
+        huart->RxEventType = HAL_UART_RXEVENT_IDLE;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+        /*Call registered Rx complete callback*/
+        huart->RxEventCallback(huart, nb_rx_data);
+#else
+        /*Call legacy weak Rx Event callback*/
+        HAL_UARTEx_RxEventCallback(huart, nb_rx_data);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+      }
+      return;
+    }
+  }
+
+  /* UART wakeup from Stop mode interrupt occurred ---------------------------*/
+  if (((isrflags & USART_ISR_WUF) != 0U) && ((cr3its & USART_CR3_WUFIE) != 0U))
+  {
+    __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_WUF);
+
+    /* UART Rx state is not reset as a reception process might be ongoing.
+       If UART handle state fields need to be reset to READY, this could be done in Wakeup callback */
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+    /* Call registered Wakeup Callback */
+    huart->WakeupCallback(huart);
+#else
+    /* Call legacy weak Wakeup Callback */
+    HAL_UARTEx_WakeupCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+    return;
+  }
+
+  /* UART in mode Transmitter ------------------------------------------------*/
+  if (((isrflags & USART_ISR_TXE_TXFNF) != 0U)
+      && (((cr1its & USART_CR1_TXEIE_TXFNFIE) != 0U)
+          || ((cr3its & USART_CR3_TXFTIE) != 0U)))
+  {
+    if (huart->TxISR != NULL)
+    {
+      huart->TxISR(huart);
+    }
+    return;
+  }
+
+  /* UART in mode Transmitter (transmission end) -----------------------------*/
+  if (((isrflags & USART_ISR_TC) != 0U) && ((cr1its & USART_CR1_TCIE) != 0U))
+  {
+    UART_EndTransmit_IT(huart);
+    return;
+  }
+
+  /* UART TX Fifo Empty occurred ----------------------------------------------*/
+  if (((isrflags & USART_ISR_TXFE) != 0U) && ((cr1its & USART_CR1_TXFEIE) != 0U))
+  {
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+    /* Call registered Tx Fifo Empty Callback */
+    huart->TxFifoEmptyCallback(huart);
+#else
+    /* Call legacy weak Tx Fifo Empty Callback */
+    HAL_UARTEx_TxFifoEmptyCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+    return;
+  }
+
+  /* UART RX Fifo Full occurred ----------------------------------------------*/
+  if (((isrflags & USART_ISR_RXFF) != 0U) && ((cr1its & USART_CR1_RXFFIE) != 0U))
+  {
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+    /* Call registered Rx Fifo Full Callback */
+    huart->RxFifoFullCallback(huart);
+#else
+    /* Call legacy weak Rx Fifo Full Callback */
+    HAL_UARTEx_RxFifoFullCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+    return;
+  }
+}
+
+/**
+  * @brief Tx Transfer completed callback.
+  * @param huart UART handle.
+  * @retval None
+  */
+__weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(huart);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_UART_TxCpltCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  Tx Half Transfer completed callback.
+  * @param  huart UART handle.
+  * @retval None
+  */
+__weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(huart);
+
+  /* NOTE: This function should not be modified, when the callback is needed,
+           the HAL_UART_TxHalfCpltCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  Rx Transfer completed callback.
+  * @param  huart UART handle.
+  * @retval None
+  */
+__weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(huart);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_UART_RxCpltCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  Rx Half Transfer completed callback.
+  * @param  huart UART handle.
+  * @retval None
+  */
+__weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(huart);
+
+  /* NOTE: This function should not be modified, when the callback is needed,
+           the HAL_UART_RxHalfCpltCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  UART error callback.
+  * @param  huart UART handle.
+  * @retval None
+  */
+__weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(huart);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_UART_ErrorCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  UART Abort Complete callback.
+  * @param  huart UART handle.
+  * @retval None
+  */
+__weak void HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(huart);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_UART_AbortCpltCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  UART Abort Complete callback.
+  * @param  huart UART handle.
+  * @retval None
+  */
+__weak void HAL_UART_AbortTransmitCpltCallback(UART_HandleTypeDef *huart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(huart);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_UART_AbortTransmitCpltCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  UART Abort Receive Complete callback.
+  * @param  huart UART handle.
+  * @retval None
+  */
+__weak void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(huart);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_UART_AbortReceiveCpltCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  Reception Event Callback (Rx event notification called after use of advanced reception service).
+  * @param  huart UART handle
+  * @param  Size  Number of data available in application reception buffer (indicates a position in
+  *               reception buffer until which, data are available)
+  * @retval None
+  */
+__weak void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(huart);
+  UNUSED(Size);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_UARTEx_RxEventCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup UART_Exported_Functions_Group3 Peripheral Control functions
+  *  @brief   UART control functions
+  *
+@verbatim
+ ===============================================================================
+                      ##### Peripheral Control functions #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to control the UART.
+     (+) HAL_UART_ReceiverTimeout_Config() API allows to configure the receiver timeout value on the fly
+     (+) HAL_UART_EnableReceiverTimeout() API enables the receiver timeout feature
+     (+) HAL_UART_DisableReceiverTimeout() API disables the receiver timeout feature
+     (+) HAL_MultiProcessor_EnableMuteMode() API enables mute mode
+     (+) HAL_MultiProcessor_DisableMuteMode() API disables mute mode
+     (+) HAL_MultiProcessor_EnterMuteMode() API enters mute mode
+     (+) UART_SetConfig() API configures the UART peripheral
+     (+) UART_AdvFeatureConfig() API optionally configures the UART advanced features
+     (+) UART_CheckIdleState() API ensures that TEACK and/or REACK are set after initialization
+     (+) HAL_HalfDuplex_EnableTransmitter() API disables receiver and enables transmitter
+     (+) HAL_HalfDuplex_EnableReceiver() API disables transmitter and enables receiver
+     (+) HAL_LIN_SendBreak() API transmits the break characters
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Update on the fly the receiver timeout value in RTOR register.
+  * @param  huart Pointer to a UART_HandleTypeDef structure that contains
+  *                    the configuration information for the specified UART module.
+  * @param  TimeoutValue receiver timeout value in number of baud blocks. The timeout
+  *                     value must be less or equal to 0x0FFFFFFFF.
+  * @retval None
+  */
+void HAL_UART_ReceiverTimeout_Config(UART_HandleTypeDef *huart, uint32_t TimeoutValue)
+{
+  if (!(IS_LPUART_INSTANCE(huart->Instance)))
+  {
+    assert_param(IS_UART_RECEIVER_TIMEOUT_VALUE(TimeoutValue));
+    MODIFY_REG(huart->Instance->RTOR, USART_RTOR_RTO, TimeoutValue);
+  }
+}
+
+/**
+  * @brief  Enable the UART receiver timeout feature.
+  * @param  huart Pointer to a UART_HandleTypeDef structure that contains
+  *                    the configuration information for the specified UART module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_EnableReceiverTimeout(UART_HandleTypeDef *huart)
+{
+  if (!(IS_LPUART_INSTANCE(huart->Instance)))
+  {
+    if (huart->gState == HAL_UART_STATE_READY)
+    {
+      /* Process Locked */
+      __HAL_LOCK(huart);
+
+      huart->gState = HAL_UART_STATE_BUSY;
+
+      /* Set the USART RTOEN bit */
+      SET_BIT(huart->Instance->CR2, USART_CR2_RTOEN);
+
+      huart->gState = HAL_UART_STATE_READY;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(huart);
+
+      return HAL_OK;
+    }
+    else
+    {
+      return HAL_BUSY;
+    }
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Disable the UART receiver timeout feature.
+  * @param  huart Pointer to a UART_HandleTypeDef structure that contains
+  *                    the configuration information for the specified UART module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_DisableReceiverTimeout(UART_HandleTypeDef *huart)
+{
+  if (!(IS_LPUART_INSTANCE(huart->Instance)))
+  {
+    if (huart->gState == HAL_UART_STATE_READY)
+    {
+      /* Process Locked */
+      __HAL_LOCK(huart);
+
+      huart->gState = HAL_UART_STATE_BUSY;
+
+      /* Clear the USART RTOEN bit */
+      CLEAR_BIT(huart->Instance->CR2, USART_CR2_RTOEN);
+
+      huart->gState = HAL_UART_STATE_READY;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(huart);
+
+      return HAL_OK;
+    }
+    else
+    {
+      return HAL_BUSY;
+    }
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Enable UART in mute mode (does not mean UART enters mute mode;
+  *         to enter mute mode, HAL_MultiProcessor_EnterMuteMode() API must be called).
+  * @param  huart UART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart)
+{
+  __HAL_LOCK(huart);
+
+  huart->gState = HAL_UART_STATE_BUSY;
+
+  /* Enable USART mute mode by setting the MME bit in the CR1 register */
+  ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_MME);
+
+  huart->gState = HAL_UART_STATE_READY;
+
+  return (UART_CheckIdleState(huart));
+}
+
+/**
+  * @brief  Disable UART mute mode (does not mean the UART actually exits mute mode
+  *         as it may not have been in mute mode at this very moment).
+  * @param  huart UART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart)
+{
+  __HAL_LOCK(huart);
+
+  huart->gState = HAL_UART_STATE_BUSY;
+
+  /* Disable USART mute mode by clearing the MME bit in the CR1 register */
+  ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_MME);
+
+  huart->gState = HAL_UART_STATE_READY;
+
+  return (UART_CheckIdleState(huart));
+}
+
+/**
+  * @brief Enter UART mute mode (means UART actually enters mute mode).
+  * @note  To exit from mute mode, HAL_MultiProcessor_DisableMuteMode() API must be called.
+  * @param huart UART handle.
+  * @retval None
+  */
+void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart)
+{
+  __HAL_UART_SEND_REQ(huart, UART_MUTE_MODE_REQUEST);
+}
+
+/**
+  * @brief  Enable the UART transmitter and disable the UART receiver.
+  * @param  huart UART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart)
+{
+  __HAL_LOCK(huart);
+  huart->gState = HAL_UART_STATE_BUSY;
+
+  /* Clear TE and RE bits */
+  ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE));
+
+  /* Enable the USART's transmit interface by setting the TE bit in the USART CR1 register */
+  ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TE);
+
+  huart->gState = HAL_UART_STATE_READY;
+
+  __HAL_UNLOCK(huart);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enable the UART receiver and disable the UART transmitter.
+  * @param  huart UART handle.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart)
+{
+  __HAL_LOCK(huart);
+  huart->gState = HAL_UART_STATE_BUSY;
+
+  /* Clear TE and RE bits */
+  ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE));
+
+  /* Enable the USART's receive interface by setting the RE bit in the USART CR1 register */
+  ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RE);
+
+  huart->gState = HAL_UART_STATE_READY;
+
+  __HAL_UNLOCK(huart);
+
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  Transmit break characters.
+  * @param  huart UART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart)
+{
+  /* Check the parameters */
+  assert_param(IS_UART_LIN_INSTANCE(huart->Instance));
+
+  __HAL_LOCK(huart);
+
+  huart->gState = HAL_UART_STATE_BUSY;
+
+  /* Send break characters */
+  __HAL_UART_SEND_REQ(huart, UART_SENDBREAK_REQUEST);
+
+  huart->gState = HAL_UART_STATE_READY;
+
+  __HAL_UNLOCK(huart);
+
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup UART_Exported_Functions_Group4 Peripheral State and Error functions
+  *  @brief   UART Peripheral State functions
+  *
+@verbatim
+  ==============================================================================
+            ##### Peripheral State and Error functions #####
+  ==============================================================================
+    [..]
+    This subsection provides functions allowing to :
+      (+) Return the UART handle state.
+      (+) Return the UART handle error code
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief Return the UART handle state.
+  * @param  huart Pointer to a UART_HandleTypeDef structure that contains
+  *               the configuration information for the specified UART.
+  * @retval HAL state
+  */
+HAL_UART_StateTypeDef HAL_UART_GetState(const UART_HandleTypeDef *huart)
+{
+  uint32_t temp1;
+  uint32_t temp2;
+  temp1 = huart->gState;
+  temp2 = huart->RxState;
+
+  return (HAL_UART_StateTypeDef)(temp1 | temp2);
+}
+
+/**
+  * @brief  Return the UART handle error code.
+  * @param  huart Pointer to a UART_HandleTypeDef structure that contains
+  *               the configuration information for the specified UART.
+  * @retval UART Error Code
+  */
+uint32_t HAL_UART_GetError(const UART_HandleTypeDef *huart)
+{
+  return huart->ErrorCode;
+}
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup UART_Private_Functions UART Private Functions
+  * @{
+  */
+
+/**
+  * @brief  Initialize the callbacks to their default values.
+  * @param  huart UART handle.
+  * @retval none
+  */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart)
+{
+  /* Init the UART Callback settings */
+  huart->TxHalfCpltCallback        = HAL_UART_TxHalfCpltCallback;        /* Legacy weak TxHalfCpltCallback        */
+  huart->TxCpltCallback            = HAL_UART_TxCpltCallback;            /* Legacy weak TxCpltCallback            */
+  huart->RxHalfCpltCallback        = HAL_UART_RxHalfCpltCallback;        /* Legacy weak RxHalfCpltCallback        */
+  huart->RxCpltCallback            = HAL_UART_RxCpltCallback;            /* Legacy weak RxCpltCallback            */
+  huart->ErrorCallback             = HAL_UART_ErrorCallback;             /* Legacy weak ErrorCallback             */
+  huart->AbortCpltCallback         = HAL_UART_AbortCpltCallback;         /* Legacy weak AbortCpltCallback         */
+  huart->AbortTransmitCpltCallback = HAL_UART_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */
+  huart->AbortReceiveCpltCallback  = HAL_UART_AbortReceiveCpltCallback;  /* Legacy weak AbortReceiveCpltCallback  */
+  huart->WakeupCallback            = HAL_UARTEx_WakeupCallback;          /* Legacy weak WakeupCallback            */
+  huart->RxFifoFullCallback        = HAL_UARTEx_RxFifoFullCallback;      /* Legacy weak RxFifoFullCallback        */
+  huart->TxFifoEmptyCallback       = HAL_UARTEx_TxFifoEmptyCallback;     /* Legacy weak TxFifoEmptyCallback       */
+  huart->RxEventCallback           = HAL_UARTEx_RxEventCallback;         /* Legacy weak RxEventCallback           */
+
+}
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+
+/**
+  * @brief Configure the UART peripheral.
+  * @param huart UART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart)
+{
+  uint32_t tmpreg;
+  uint16_t brrtemp;
+  UART_ClockSourceTypeDef clocksource;
+  uint32_t usartdiv;
+  HAL_StatusTypeDef ret               = HAL_OK;
+  uint32_t lpuart_ker_ck_pres;
+  PLL2_ClocksTypeDef pll2_clocks;
+  PLL3_ClocksTypeDef pll3_clocks;
+  uint32_t pclk;
+
+  /* Check the parameters */
+  assert_param(IS_UART_BAUDRATE(huart->Init.BaudRate));
+  assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
+  if (UART_INSTANCE_LOWPOWER(huart))
+  {
+    assert_param(IS_LPUART_STOPBITS(huart->Init.StopBits));
+  }
+  else
+  {
+    assert_param(IS_UART_STOPBITS(huart->Init.StopBits));
+    assert_param(IS_UART_ONE_BIT_SAMPLE(huart->Init.OneBitSampling));
+  }
+
+  assert_param(IS_UART_PARITY(huart->Init.Parity));
+  assert_param(IS_UART_MODE(huart->Init.Mode));
+  assert_param(IS_UART_HARDWARE_FLOW_CONTROL(huart->Init.HwFlowCtl));
+  assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));
+  assert_param(IS_UART_PRESCALER(huart->Init.ClockPrescaler));
+
+  /*-------------------------- USART CR1 Configuration -----------------------*/
+  /* Clear M, PCE, PS, TE, RE and OVER8 bits and configure
+  *  the UART Word Length, Parity, Mode and oversampling:
+  *  set the M bits according to huart->Init.WordLength value
+  *  set PCE and PS bits according to huart->Init.Parity value
+  *  set TE and RE bits according to huart->Init.Mode value
+  *  set OVER8 bit according to huart->Init.OverSampling value */
+  tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ;
+  MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
+
+  /*-------------------------- USART CR2 Configuration -----------------------*/
+  /* Configure the UART Stop Bits: Set STOP[13:12] bits according
+  * to huart->Init.StopBits value */
+  MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
+
+  /*-------------------------- USART CR3 Configuration -----------------------*/
+  /* Configure
+  * - UART HardWare Flow Control: set CTSE and RTSE bits according
+  *   to huart->Init.HwFlowCtl value
+  * - one-bit sampling method versus three samples' majority rule according
+  *   to huart->Init.OneBitSampling (not applicable to LPUART) */
+  tmpreg = (uint32_t)huart->Init.HwFlowCtl;
+
+  if (!(UART_INSTANCE_LOWPOWER(huart)))
+  {
+    tmpreg |= huart->Init.OneBitSampling;
+  }
+  MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg);
+
+  /*-------------------------- USART PRESC Configuration -----------------------*/
+  /* Configure
+  * - UART Clock Prescaler : set PRESCALER according to huart->Init.ClockPrescaler value */
+  MODIFY_REG(huart->Instance->PRESC, USART_PRESC_PRESCALER, huart->Init.ClockPrescaler);
+
+  /*-------------------------- USART BRR Configuration -----------------------*/
+  UART_GETCLOCKSOURCE(huart, clocksource);
+
+  /* Check LPUART instance */
+  if (UART_INSTANCE_LOWPOWER(huart))
+  {
+    /* Retrieve frequency clock */
+    switch (clocksource)
+    {
+      case UART_CLOCKSOURCE_D3PCLK1:
+        pclk = HAL_RCCEx_GetD3PCLK1Freq();
+        break;
+      case UART_CLOCKSOURCE_PLL2:
+        HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
+        pclk = pll2_clocks.PLL2_Q_Frequency;
+        break;
+      case UART_CLOCKSOURCE_PLL3:
+        HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
+        pclk = pll3_clocks.PLL3_Q_Frequency;
+        break;
+      case UART_CLOCKSOURCE_HSI:
+        if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
+        {
+          pclk = (uint32_t)(HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3U));
+        }
+        else
+        {
+          pclk = (uint32_t) HSI_VALUE;
+        }
+        break;
+      case UART_CLOCKSOURCE_CSI:
+        pclk = (uint32_t) CSI_VALUE;
+        break;
+      case UART_CLOCKSOURCE_LSE:
+        pclk = (uint32_t) LSE_VALUE;
+        break;
+      default:
+        pclk = 0U;
+        ret = HAL_ERROR;
+        break;
+    }
+
+    /* If proper clock source reported */
+    if (pclk != 0U)
+    {
+      /* Compute clock after Prescaler */
+      lpuart_ker_ck_pres = (pclk / UARTPrescTable[huart->Init.ClockPrescaler]);
+
+      /* Ensure that Frequency clock is in the range [3 * baudrate, 4096 * baudrate] */
+      if ((lpuart_ker_ck_pres < (3U * huart->Init.BaudRate)) ||
+          (lpuart_ker_ck_pres > (4096U * huart->Init.BaudRate)))
+      {
+        ret = HAL_ERROR;
+      }
+      else
+      {
+        /* Check computed UsartDiv value is in allocated range
+           (it is forbidden to write values lower than 0x300 in the LPUART_BRR register) */
+        usartdiv = (uint32_t)(UART_DIV_LPUART(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
+        if ((usartdiv >= LPUART_BRR_MIN) && (usartdiv <= LPUART_BRR_MAX))
+        {
+          huart->Instance->BRR = usartdiv;
+        }
+        else
+        {
+          ret = HAL_ERROR;
+        }
+      } /* if ( (lpuart_ker_ck_pres < (3 * huart->Init.BaudRate) ) ||
+                (lpuart_ker_ck_pres > (4096 * huart->Init.BaudRate) )) */
+    } /* if (pclk != 0) */
+  }
+  /* Check UART Over Sampling to set Baud Rate Register */
+  else if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
+  {
+    switch (clocksource)
+    {
+      case UART_CLOCKSOURCE_D2PCLK1:
+        pclk = HAL_RCC_GetPCLK1Freq();
+        break;
+      case UART_CLOCKSOURCE_D2PCLK2:
+        pclk = HAL_RCC_GetPCLK2Freq();
+        break;
+      case UART_CLOCKSOURCE_PLL2:
+        HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
+        pclk = pll2_clocks.PLL2_Q_Frequency;
+        break;
+      case UART_CLOCKSOURCE_PLL3:
+        HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
+        pclk = pll3_clocks.PLL3_Q_Frequency;
+        break;
+      case UART_CLOCKSOURCE_HSI:
+        if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
+        {
+          pclk = (uint32_t)(HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3U));
+        }
+        else
+        {
+          pclk = (uint32_t) HSI_VALUE;
+        }
+        break;
+      case UART_CLOCKSOURCE_CSI:
+        pclk = (uint32_t) CSI_VALUE;
+        break;
+      case UART_CLOCKSOURCE_LSE:
+        pclk = (uint32_t) LSE_VALUE;
+        break;
+      default:
+        pclk = 0U;
+        ret = HAL_ERROR;
+        break;
+    }
+
+    /* USARTDIV must be greater than or equal to 0d16 */
+    if (pclk != 0U)
+    {
+      usartdiv = (uint32_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
+      if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
+      {
+        brrtemp = (uint16_t)(usartdiv & 0xFFF0U);
+        brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
+        huart->Instance->BRR = brrtemp;
+      }
+      else
+      {
+        ret = HAL_ERROR;
+      }
+    }
+  }
+  else
+  {
+    switch (clocksource)
+    {
+      case UART_CLOCKSOURCE_D2PCLK1:
+        pclk = HAL_RCC_GetPCLK1Freq();
+        break;
+      case UART_CLOCKSOURCE_D2PCLK2:
+        pclk = HAL_RCC_GetPCLK2Freq();
+        break;
+      case UART_CLOCKSOURCE_PLL2:
+        HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
+        pclk = pll2_clocks.PLL2_Q_Frequency;
+        break;
+      case UART_CLOCKSOURCE_PLL3:
+        HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
+        pclk = pll3_clocks.PLL3_Q_Frequency;
+        break;
+      case UART_CLOCKSOURCE_HSI:
+        if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
+        {
+          pclk = (uint32_t)(HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3U));
+        }
+        else
+        {
+          pclk = (uint32_t) HSI_VALUE;
+        }
+        break;
+      case UART_CLOCKSOURCE_CSI:
+        pclk = (uint32_t) CSI_VALUE;
+        break;
+      case UART_CLOCKSOURCE_LSE:
+        pclk = (uint32_t) LSE_VALUE;
+        break;
+      default:
+        pclk = 0U;
+        ret = HAL_ERROR;
+        break;
+    }
+
+    if (pclk != 0U)
+    {
+      /* USARTDIV must be greater than or equal to 0d16 */
+      usartdiv = (uint32_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
+      if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
+      {
+        huart->Instance->BRR = (uint16_t)usartdiv;
+      }
+      else
+      {
+        ret = HAL_ERROR;
+      }
+    }
+  }
+
+  /* Initialize the number of data to process during RX/TX ISR execution */
+  huart->NbTxDataToProcess = 1;
+  huart->NbRxDataToProcess = 1;
+
+  /* Clear ISR function pointers */
+  huart->RxISR = NULL;
+  huart->TxISR = NULL;
+
+  return ret;
+}
+
+/**
+  * @brief Configure the UART peripheral advanced features.
+  * @param huart UART handle.
+  * @retval None
+  */
+void UART_AdvFeatureConfig(UART_HandleTypeDef *huart)
+{
+  /* Check whether the set of advanced features to configure is properly set */
+  assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit));
+
+  /* if required, configure TX pin active level inversion */
+  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT))
+  {
+    assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert));
+    MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert);
+  }
+
+  /* if required, configure RX pin active level inversion */
+  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT))
+  {
+    assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert));
+    MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert);
+  }
+
+  /* if required, configure data inversion */
+  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT))
+  {
+    assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert));
+    MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert);
+  }
+
+  /* if required, configure RX/TX pins swap */
+  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT))
+  {
+    assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap));
+    MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap);
+  }
+
+  /* if required, configure RX overrun detection disabling */
+  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT))
+  {
+    assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable));
+    MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable);
+  }
+
+  /* if required, configure DMA disabling on reception error */
+  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT))
+  {
+    assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError));
+    MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError);
+  }
+
+  /* if required, configure auto Baud rate detection scheme */
+  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT))
+  {
+    assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance));
+    assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable));
+    MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable);
+    /* set auto Baudrate detection parameters if detection is enabled */
+    if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)
+    {
+      assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode));
+      MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode);
+    }
+  }
+
+  /* if required, configure MSB first on communication line */
+  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT))
+  {
+    assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst));
+    MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst);
+  }
+}
+
+/**
+  * @brief Check the UART Idle State.
+  * @param huart UART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart)
+{
+  uint32_t tickstart;
+
+  /* Initialize the UART ErrorCode */
+  huart->ErrorCode = HAL_UART_ERROR_NONE;
+
+  /* Init tickstart for timeout management */
+  tickstart = HAL_GetTick();
+
+  /* Check if the Transmitter is enabled */
+  if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
+  {
+    /* Wait until TEACK flag is set */
+    if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
+    {
+      /* Disable TXE interrupt for the interrupt process */
+      ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE));
+
+      huart->gState = HAL_UART_STATE_READY;
+
+      __HAL_UNLOCK(huart);
+
+      /* Timeout occurred */
+      return HAL_TIMEOUT;
+    }
+  }
+
+  /* Check if the Receiver is enabled */
+  if ((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
+  {
+    /* Wait until REACK flag is set */
+    if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
+    {
+      /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error)
+      interrupts for the interrupt process */
+      ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
+      ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+      huart->RxState = HAL_UART_STATE_READY;
+
+      __HAL_UNLOCK(huart);
+
+      /* Timeout occurred */
+      return HAL_TIMEOUT;
+    }
+  }
+
+  /* Initialize the UART State */
+  huart->gState = HAL_UART_STATE_READY;
+  huart->RxState = HAL_UART_STATE_READY;
+  huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+  huart->RxEventType = HAL_UART_RXEVENT_TC;
+
+  __HAL_UNLOCK(huart);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  This function handles UART Communication Timeout. It waits
+  *                  until a flag is no longer in the specified status.
+  * @param huart     UART handle.
+  * @param Flag      Specifies the UART flag to check
+  * @param Status    The actual Flag status (SET or RESET)
+  * @param Tickstart Tick start value
+  * @param Timeout   Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status,
+                                              uint32_t Tickstart, uint32_t Timeout)
+{
+  /* Wait until flag is set */
+  while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
+  {
+    /* Check for the Timeout */
+    if (Timeout != HAL_MAX_DELAY)
+    {
+      if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
+      {
+
+        return HAL_TIMEOUT;
+      }
+
+      if (READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U)
+      {
+        if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET)
+        {
+           /* Clear Overrun Error flag*/
+           __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
+
+           /* Blocking error : transfer is aborted
+           Set the UART state ready to be able to start again the process,
+           Disable Rx Interrupts if ongoing */
+           UART_EndRxTransfer(huart);
+
+           huart->ErrorCode = HAL_UART_ERROR_ORE;
+
+           /* Process Unlocked */
+           __HAL_UNLOCK(huart);
+
+           return HAL_ERROR;
+        }
+        if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET)
+        {
+          /* Clear Receiver Timeout flag*/
+          __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF);
+
+          /* Blocking error : transfer is aborted
+          Set the UART state ready to be able to start again the process,
+          Disable Rx Interrupts if ongoing */
+          UART_EndRxTransfer(huart);
+
+          huart->ErrorCode = HAL_UART_ERROR_RTO;
+
+          /* Process Unlocked */
+          __HAL_UNLOCK(huart);
+
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  Start Receive operation in interrupt mode.
+  * @note   This function could be called by all HAL UART API providing reception in Interrupt mode.
+  * @note   When calling this function, parameters validity is considered as already checked,
+  *         i.e. Rx State, buffer address, ...
+  *         UART Handle is assumed as Locked.
+  * @param  huart UART handle.
+  * @param  pData Pointer to data buffer (u8 or u16 data elements).
+  * @param  Size  Amount of data elements (u8 or u16) to be received.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
+{
+  huart->pRxBuffPtr  = pData;
+  huart->RxXferSize  = Size;
+  huart->RxXferCount = Size;
+  huart->RxISR       = NULL;
+
+  /* Computation of UART mask to apply to RDR register */
+  UART_MASK_COMPUTATION(huart);
+
+  huart->ErrorCode = HAL_UART_ERROR_NONE;
+  huart->RxState = HAL_UART_STATE_BUSY_RX;
+
+  /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
+  ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+  /* Configure Rx interrupt processing */
+  if ((huart->FifoMode == UART_FIFOMODE_ENABLE) && (Size >= huart->NbRxDataToProcess))
+  {
+    /* Set the Rx ISR function pointer according to the data word length */
+    if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
+    {
+      huart->RxISR = UART_RxISR_16BIT_FIFOEN;
+    }
+    else
+    {
+      huart->RxISR = UART_RxISR_8BIT_FIFOEN;
+    }
+
+    /* Enable the UART Parity Error interrupt and RX FIFO Threshold interrupt */
+    if (huart->Init.Parity != UART_PARITY_NONE)
+    {
+      ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+    }
+    ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_RXFTIE);
+  }
+  else
+  {
+    /* Set the Rx ISR function pointer according to the data word length */
+    if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
+    {
+      huart->RxISR = UART_RxISR_16BIT;
+    }
+    else
+    {
+      huart->RxISR = UART_RxISR_8BIT;
+    }
+
+    /* Enable the UART Parity Error interrupt and Data Register Not Empty interrupt */
+    if (huart->Init.Parity != UART_PARITY_NONE)
+    {
+      ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE);
+    }
+    else
+    {
+      ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
+    }
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  Start Receive operation in DMA mode.
+  * @note   This function could be called by all HAL UART API providing reception in DMA mode.
+  * @note   When calling this function, parameters validity is considered as already checked,
+  *         i.e. Rx State, buffer address, ...
+  *         UART Handle is assumed as Locked.
+  * @param  huart UART handle.
+  * @param  pData Pointer to data buffer (u8 or u16 data elements).
+  * @param  Size  Amount of data elements (u8 or u16) to be received.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
+{
+  huart->pRxBuffPtr = pData;
+  huart->RxXferSize = Size;
+
+  huart->ErrorCode = HAL_UART_ERROR_NONE;
+  huart->RxState = HAL_UART_STATE_BUSY_RX;
+
+  if (huart->hdmarx != NULL)
+  {
+    /* Set the UART DMA transfer complete callback */
+    huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt;
+
+    /* Set the UART DMA Half transfer complete callback */
+    huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt;
+
+    /* Set the DMA error callback */
+    huart->hdmarx->XferErrorCallback = UART_DMAError;
+
+    /* Set the DMA abort callback */
+    huart->hdmarx->XferAbortCallback = NULL;
+
+    /* Enable the DMA channel */
+    if (HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->RDR, (uint32_t)huart->pRxBuffPtr, Size) != HAL_OK)
+    {
+      /* Set error code to DMA */
+      huart->ErrorCode = HAL_UART_ERROR_DMA;
+
+      /* Restore huart->RxState to ready */
+      huart->RxState = HAL_UART_STATE_READY;
+
+      return HAL_ERROR;
+    }
+  }
+
+  /* Enable the UART Parity Error Interrupt */
+  if (huart->Init.Parity != UART_PARITY_NONE)
+  {
+    ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+  }
+
+  /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
+  ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+  /* Enable the DMA transfer for the receiver request by setting the DMAR bit
+  in the UART CR3 register */
+  ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion).
+  * @param  huart UART handle.
+  * @retval None
+  */
+static void UART_EndTxTransfer(UART_HandleTypeDef *huart)
+{
+  /* Disable TXEIE, TCIE, TXFT interrupts */
+  ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
+  ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_TXFTIE));
+
+  /* At end of Tx process, restore huart->gState to Ready */
+  huart->gState = HAL_UART_STATE_READY;
+}
+
+
+/**
+  * @brief  End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
+  * @param  huart UART handle.
+  * @retval None
+  */
+static void UART_EndRxTransfer(UART_HandleTypeDef *huart)
+{
+  /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+  ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
+  ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
+
+  /* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */
+  if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+  {
+    ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+  }
+
+  /* At end of Rx process, restore huart->RxState to Ready */
+  huart->RxState = HAL_UART_STATE_READY;
+  huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+  /* Reset RxIsr function pointer */
+  huart->RxISR = NULL;
+}
+
+
+/**
+  * @brief DMA UART transmit process complete callback.
+  * @param hdma DMA handle.
+  * @retval None
+  */
+static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma)
+{
+  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+
+  /* DMA Normal mode */
+  if (hdma->Init.Mode != DMA_CIRCULAR)
+  {
+    huart->TxXferCount = 0U;
+
+    /* Disable the DMA transfer for transmit request by resetting the DMAT bit
+       in the UART CR3 register */
+    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+
+    /* Enable the UART Transmit Complete Interrupt */
+    ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
+  }
+  /* DMA Circular mode */
+  else
+  {
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+    /*Call registered Tx complete callback*/
+    huart->TxCpltCallback(huart);
+#else
+    /*Call legacy weak Tx complete callback*/
+    HAL_UART_TxCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+  }
+}
+
+/**
+  * @brief DMA UART transmit process half complete callback.
+  * @param hdma DMA handle.
+  * @retval None
+  */
+static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
+{
+  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+  /*Call registered Tx Half complete callback*/
+  huart->TxHalfCpltCallback(huart);
+#else
+  /*Call legacy weak Tx Half complete callback*/
+  HAL_UART_TxHalfCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief DMA UART receive process complete callback.
+  * @param hdma DMA handle.
+  * @retval None
+  */
+static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+
+  /* DMA Normal mode */
+  if (hdma->Init.Mode != DMA_CIRCULAR)
+  {
+    huart->RxXferCount = 0U;
+
+    /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
+    ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+    /* Disable the DMA transfer for the receiver request by resetting the DMAR bit
+       in the UART CR3 register */
+    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+    /* At end of Rx process, restore huart->RxState to Ready */
+    huart->RxState = HAL_UART_STATE_READY;
+
+    /* If Reception till IDLE event has been selected, Disable IDLE Interrupt */
+    if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+    {
+      ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+    }
+  }
+
+  /* Initialize type of RxEvent that correspond to RxEvent callback execution;
+     In this case, Rx Event type is Transfer Complete */
+  huart->RxEventType = HAL_UART_RXEVENT_TC;
+
+  /* Check current reception Mode :
+     If Reception till IDLE event has been selected : use Rx Event callback */
+  if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+  {
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+    /*Call registered Rx Event callback*/
+    huart->RxEventCallback(huart, huart->RxXferSize);
+#else
+    /*Call legacy weak Rx Event callback*/
+    HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+  }
+  else
+  {
+    /* In other cases : use Rx Complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+    /*Call registered Rx complete callback*/
+    huart->RxCpltCallback(huart);
+#else
+    /*Call legacy weak Rx complete callback*/
+    HAL_UART_RxCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+  }
+}
+
+/**
+  * @brief DMA UART receive process half complete callback.
+  * @param hdma DMA handle.
+  * @retval None
+  */
+static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
+{
+  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+
+  /* Initialize type of RxEvent that correspond to RxEvent callback execution;
+     In this case, Rx Event type is Half Transfer */
+  huart->RxEventType = HAL_UART_RXEVENT_HT;
+
+  /* Check current reception Mode :
+     If Reception till IDLE event has been selected : use Rx Event callback */
+  if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+  {
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+    /*Call registered Rx Event callback*/
+    huart->RxEventCallback(huart, huart->RxXferSize / 2U);
+#else
+    /*Call legacy weak Rx Event callback*/
+    HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize / 2U);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+  }
+  else
+  {
+    /* In other cases : use Rx Half Complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+    /*Call registered Rx Half complete callback*/
+    huart->RxHalfCpltCallback(huart);
+#else
+    /*Call legacy weak Rx Half complete callback*/
+    HAL_UART_RxHalfCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+  }
+}
+
+/**
+  * @brief DMA UART communication error callback.
+  * @param hdma DMA handle.
+  * @retval None
+  */
+static void UART_DMAError(DMA_HandleTypeDef *hdma)
+{
+  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+
+  const HAL_UART_StateTypeDef gstate = huart->gState;
+  const HAL_UART_StateTypeDef rxstate = huart->RxState;
+
+  /* Stop UART DMA Tx request if ongoing */
+  if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) &&
+      (gstate == HAL_UART_STATE_BUSY_TX))
+  {
+    huart->TxXferCount = 0U;
+    UART_EndTxTransfer(huart);
+  }
+
+  /* Stop UART DMA Rx request if ongoing */
+  if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) &&
+      (rxstate == HAL_UART_STATE_BUSY_RX))
+  {
+    huart->RxXferCount = 0U;
+    UART_EndRxTransfer(huart);
+  }
+
+  huart->ErrorCode |= HAL_UART_ERROR_DMA;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+  /*Call registered error callback*/
+  huart->ErrorCallback(huart);
+#else
+  /*Call legacy weak error callback*/
+  HAL_UART_ErrorCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  DMA UART communication abort callback, when initiated by HAL services on Error
+  *         (To be called at end of DMA Abort procedure following error occurrence).
+  * @param  hdma DMA handle.
+  * @retval None
+  */
+static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma)
+{
+  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+  huart->RxXferCount = 0U;
+  huart->TxXferCount = 0U;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+  /*Call registered error callback*/
+  huart->ErrorCallback(huart);
+#else
+  /*Call legacy weak error callback*/
+  HAL_UART_ErrorCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  DMA UART Tx communication abort callback, when initiated by user
+  *         (To be called at end of DMA Tx Abort procedure following user abort request).
+  * @note   When this callback is executed, User Abort complete call back is called only if no
+  *         Abort still ongoing for Rx DMA Handle.
+  * @param  hdma DMA handle.
+  * @retval None
+  */
+static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
+{
+  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+
+  huart->hdmatx->XferAbortCallback = NULL;
+
+  /* Check if an Abort process is still ongoing */
+  if (huart->hdmarx != NULL)
+  {
+    if (huart->hdmarx->XferAbortCallback != NULL)
+    {
+      return;
+    }
+  }
+
+  /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
+  huart->TxXferCount = 0U;
+  huart->RxXferCount = 0U;
+
+  /* Reset errorCode */
+  huart->ErrorCode = HAL_UART_ERROR_NONE;
+
+  /* Clear the Error flags in the ICR register */
+  __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
+
+  /* Flush the whole TX FIFO (if needed) */
+  if (huart->FifoMode == UART_FIFOMODE_ENABLE)
+  {
+    __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST);
+  }
+
+  /* Restore huart->gState and huart->RxState to Ready */
+  huart->gState  = HAL_UART_STATE_READY;
+  huart->RxState = HAL_UART_STATE_READY;
+  huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+  /* Call user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+  /* Call registered Abort complete callback */
+  huart->AbortCpltCallback(huart);
+#else
+  /* Call legacy weak Abort complete callback */
+  HAL_UART_AbortCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+}
+
+
+/**
+  * @brief  DMA UART Rx communication abort callback, when initiated by user
+  *         (To be called at end of DMA Rx Abort procedure following user abort request).
+  * @note   When this callback is executed, User Abort complete call back is called only if no
+  *         Abort still ongoing for Tx DMA Handle.
+  * @param  hdma DMA handle.
+  * @retval None
+  */
+static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
+{
+  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+
+  huart->hdmarx->XferAbortCallback = NULL;
+
+  /* Check if an Abort process is still ongoing */
+  if (huart->hdmatx != NULL)
+  {
+    if (huart->hdmatx->XferAbortCallback != NULL)
+    {
+      return;
+    }
+  }
+
+  /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
+  huart->TxXferCount = 0U;
+  huart->RxXferCount = 0U;
+
+  /* Reset errorCode */
+  huart->ErrorCode = HAL_UART_ERROR_NONE;
+
+  /* Clear the Error flags in the ICR register */
+  __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
+
+  /* Discard the received data */
+  __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+
+  /* Restore huart->gState and huart->RxState to Ready */
+  huart->gState  = HAL_UART_STATE_READY;
+  huart->RxState = HAL_UART_STATE_READY;
+  huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+  /* Call user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+  /* Call registered Abort complete callback */
+  huart->AbortCpltCallback(huart);
+#else
+  /* Call legacy weak Abort complete callback */
+  HAL_UART_AbortCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+}
+
+
+/**
+  * @brief  DMA UART Tx communication abort callback, when initiated by user by a call to
+  *         HAL_UART_AbortTransmit_IT API (Abort only Tx transfer)
+  *         (This callback is executed at end of DMA Tx Abort procedure following user abort request,
+  *         and leads to user Tx Abort Complete callback execution).
+  * @param  hdma DMA handle.
+  * @retval None
+  */
+static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
+{
+  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+
+  huart->TxXferCount = 0U;
+
+  /* Flush the whole TX FIFO (if needed) */
+  if (huart->FifoMode == UART_FIFOMODE_ENABLE)
+  {
+    __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST);
+  }
+
+  /* Restore huart->gState to Ready */
+  huart->gState = HAL_UART_STATE_READY;
+
+  /* Call user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+  /* Call registered Abort Transmit Complete Callback */
+  huart->AbortTransmitCpltCallback(huart);
+#else
+  /* Call legacy weak Abort Transmit Complete Callback */
+  HAL_UART_AbortTransmitCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  DMA UART Rx communication abort callback, when initiated by user by a call to
+  *         HAL_UART_AbortReceive_IT API (Abort only Rx transfer)
+  *         (This callback is executed at end of DMA Rx Abort procedure following user abort request,
+  *         and leads to user Rx Abort Complete callback execution).
+  * @param  hdma DMA handle.
+  * @retval None
+  */
+static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
+{
+  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  huart->RxXferCount = 0U;
+
+  /* Clear the Error flags in the ICR register */
+  __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
+
+  /* Discard the received data */
+  __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+
+  /* Restore huart->RxState to Ready */
+  huart->RxState = HAL_UART_STATE_READY;
+  huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+  /* Call user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+  /* Call registered Abort Receive Complete Callback */
+  huart->AbortReceiveCpltCallback(huart);
+#else
+  /* Call legacy weak Abort Receive Complete Callback */
+  HAL_UART_AbortReceiveCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief TX interrupt handler for 7 or 8 bits data word length .
+  * @note   Function is called under interruption only, once
+  *         interruptions have been enabled by HAL_UART_Transmit_IT().
+  * @param huart UART handle.
+  * @retval None
+  */
+static void UART_TxISR_8BIT(UART_HandleTypeDef *huart)
+{
+  /* Check that a Tx process is ongoing */
+  if (huart->gState == HAL_UART_STATE_BUSY_TX)
+  {
+    if (huart->TxXferCount == 0U)
+    {
+      /* Disable the UART Transmit Data Register Empty Interrupt */
+      ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
+
+      /* Enable the UART Transmit Complete Interrupt */
+      ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
+    }
+    else
+    {
+      huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr & (uint8_t)0xFF);
+      huart->pTxBuffPtr++;
+      huart->TxXferCount--;
+    }
+  }
+}
+
+/**
+  * @brief TX interrupt handler for 9 bits data word length.
+  * @note   Function is called under interruption only, once
+  *         interruptions have been enabled by HAL_UART_Transmit_IT().
+  * @param huart UART handle.
+  * @retval None
+  */
+static void UART_TxISR_16BIT(UART_HandleTypeDef *huart)
+{
+  const uint16_t *tmp;
+
+  /* Check that a Tx process is ongoing */
+  if (huart->gState == HAL_UART_STATE_BUSY_TX)
+  {
+    if (huart->TxXferCount == 0U)
+    {
+      /* Disable the UART Transmit Data Register Empty Interrupt */
+      ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
+
+      /* Enable the UART Transmit Complete Interrupt */
+      ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
+    }
+    else
+    {
+      tmp = (const uint16_t *) huart->pTxBuffPtr;
+      huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL);
+      huart->pTxBuffPtr += 2U;
+      huart->TxXferCount--;
+    }
+  }
+}
+
+/**
+  * @brief TX interrupt handler for 7 or 8 bits data word length and FIFO mode is enabled.
+  * @note   Function is called under interruption only, once
+  *         interruptions have been enabled by HAL_UART_Transmit_IT().
+  * @param huart UART handle.
+  * @retval None
+  */
+static void UART_TxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart)
+{
+  uint16_t  nb_tx_data;
+
+  /* Check that a Tx process is ongoing */
+  if (huart->gState == HAL_UART_STATE_BUSY_TX)
+  {
+    for (nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--)
+    {
+      if (huart->TxXferCount == 0U)
+      {
+        /* Disable the TX FIFO threshold interrupt */
+        ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
+
+        /* Enable the UART Transmit Complete Interrupt */
+        ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
+
+        break; /* force exit loop */
+      }
+      else if (READ_BIT(huart->Instance->ISR, USART_ISR_TXE_TXFNF) != 0U)
+      {
+        huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr & (uint8_t)0xFF);
+        huart->pTxBuffPtr++;
+        huart->TxXferCount--;
+      }
+      else
+      {
+        /* Nothing to do */
+      }
+    }
+  }
+}
+
+/**
+  * @brief TX interrupt handler for 9 bits data word length and FIFO mode is enabled.
+  * @note   Function is called under interruption only, once
+  *         interruptions have been enabled by HAL_UART_Transmit_IT().
+  * @param huart UART handle.
+  * @retval None
+  */
+static void UART_TxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart)
+{
+  const uint16_t *tmp;
+  uint16_t  nb_tx_data;
+
+  /* Check that a Tx process is ongoing */
+  if (huart->gState == HAL_UART_STATE_BUSY_TX)
+  {
+    for (nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--)
+    {
+      if (huart->TxXferCount == 0U)
+      {
+        /* Disable the TX FIFO threshold interrupt */
+        ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
+
+        /* Enable the UART Transmit Complete Interrupt */
+        ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
+
+        break; /* force exit loop */
+      }
+      else if (READ_BIT(huart->Instance->ISR, USART_ISR_TXE_TXFNF) != 0U)
+      {
+        tmp = (const uint16_t *) huart->pTxBuffPtr;
+        huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL);
+        huart->pTxBuffPtr += 2U;
+        huart->TxXferCount--;
+      }
+      else
+      {
+        /* Nothing to do */
+      }
+    }
+  }
+}
+
+/**
+  * @brief  Wrap up transmission in non-blocking mode.
+  * @param  huart pointer to a UART_HandleTypeDef structure that contains
+  *                the configuration information for the specified UART module.
+  * @retval None
+  */
+static void UART_EndTransmit_IT(UART_HandleTypeDef *huart)
+{
+  /* Disable the UART Transmit Complete Interrupt */
+  ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE);
+
+  /* Tx process is ended, restore huart->gState to Ready */
+  huart->gState = HAL_UART_STATE_READY;
+
+  /* Cleat TxISR function pointer */
+  huart->TxISR = NULL;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+  /*Call registered Tx complete callback*/
+  huart->TxCpltCallback(huart);
+#else
+  /*Call legacy weak Tx complete callback*/
+  HAL_UART_TxCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief RX interrupt handler for 7 or 8 bits data word length .
+  * @param huart UART handle.
+  * @retval None
+  */
+static void UART_RxISR_8BIT(UART_HandleTypeDef *huart)
+{
+  uint16_t uhMask = huart->Mask;
+  uint16_t  uhdata;
+
+  /* Check that a Rx process is ongoing */
+  if (huart->RxState == HAL_UART_STATE_BUSY_RX)
+  {
+    uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
+    *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask);
+    huart->pRxBuffPtr++;
+    huart->RxXferCount--;
+
+    if (huart->RxXferCount == 0U)
+    {
+      /* Disable the UART Parity Error Interrupt and RXNE interrupts */
+      ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
+
+      /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
+      ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+      /* Rx process is completed, restore huart->RxState to Ready */
+      huart->RxState = HAL_UART_STATE_READY;
+
+      /* Clear RxISR function pointer */
+      huart->RxISR = NULL;
+
+      /* Initialize type of RxEvent to Transfer Complete */
+      huart->RxEventType = HAL_UART_RXEVENT_TC;
+
+      if (!(IS_LPUART_INSTANCE(huart->Instance)))
+      {
+        /* Check that USART RTOEN bit is set */
+        if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
+        {
+          /* Enable the UART Receiver Timeout Interrupt */
+          ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
+        }
+      }
+
+      /* Check current reception Mode :
+         If Reception till IDLE event has been selected : */
+      if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+      {
+        /* Set reception type to Standard */
+        huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+        /* Disable IDLE interrupt */
+        ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+
+        if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET)
+        {
+          /* Clear IDLE Flag */
+          __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
+        }
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+        /*Call registered Rx Event callback*/
+        huart->RxEventCallback(huart, huart->RxXferSize);
+#else
+        /*Call legacy weak Rx Event callback*/
+        HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+      }
+      else
+      {
+        /* Standard reception API called */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+        /*Call registered Rx complete callback*/
+        huart->RxCpltCallback(huart);
+#else
+        /*Call legacy weak Rx complete callback*/
+        HAL_UART_RxCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+      }
+    }
+  }
+  else
+  {
+    /* Clear RXNE interrupt flag */
+    __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+  }
+}
+
+/**
+  * @brief RX interrupt handler for 9 bits data word length .
+  * @note   Function is called under interruption only, once
+  *         interruptions have been enabled by HAL_UART_Receive_IT()
+  * @param huart UART handle.
+  * @retval None
+  */
+static void UART_RxISR_16BIT(UART_HandleTypeDef *huart)
+{
+  uint16_t *tmp;
+  uint16_t uhMask = huart->Mask;
+  uint16_t  uhdata;
+
+  /* Check that a Rx process is ongoing */
+  if (huart->RxState == HAL_UART_STATE_BUSY_RX)
+  {
+    uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
+    tmp = (uint16_t *) huart->pRxBuffPtr ;
+    *tmp = (uint16_t)(uhdata & uhMask);
+    huart->pRxBuffPtr += 2U;
+    huart->RxXferCount--;
+
+    if (huart->RxXferCount == 0U)
+    {
+      /* Disable the UART Parity Error Interrupt and RXNE interrupt*/
+      ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
+
+      /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
+      ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+      /* Rx process is completed, restore huart->RxState to Ready */
+      huart->RxState = HAL_UART_STATE_READY;
+
+      /* Clear RxISR function pointer */
+      huart->RxISR = NULL;
+
+      /* Initialize type of RxEvent to Transfer Complete */
+      huart->RxEventType = HAL_UART_RXEVENT_TC;
+
+      if (!(IS_LPUART_INSTANCE(huart->Instance)))
+      {
+        /* Check that USART RTOEN bit is set */
+        if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
+        {
+          /* Enable the UART Receiver Timeout Interrupt */
+          ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
+        }
+      }
+
+      /* Check current reception Mode :
+         If Reception till IDLE event has been selected : */
+      if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+      {
+        /* Set reception type to Standard */
+        huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+        /* Disable IDLE interrupt */
+        ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+
+        if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET)
+        {
+          /* Clear IDLE Flag */
+          __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
+        }
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+        /*Call registered Rx Event callback*/
+        huart->RxEventCallback(huart, huart->RxXferSize);
+#else
+        /*Call legacy weak Rx Event callback*/
+        HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+      }
+      else
+      {
+        /* Standard reception API called */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+        /*Call registered Rx complete callback*/
+        huart->RxCpltCallback(huart);
+#else
+        /*Call legacy weak Rx complete callback*/
+        HAL_UART_RxCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+      }
+    }
+  }
+  else
+  {
+    /* Clear RXNE interrupt flag */
+    __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+  }
+}
+
+/**
+  * @brief RX interrupt handler for 7 or 8  bits data word length and FIFO mode is enabled.
+  * @note   Function is called under interruption only, once
+  *         interruptions have been enabled by HAL_UART_Receive_IT()
+  * @param huart UART handle.
+  * @retval None
+  */
+static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart)
+{
+  uint16_t  uhMask = huart->Mask;
+  uint16_t  uhdata;
+  uint16_t  nb_rx_data;
+  uint16_t  rxdatacount;
+  uint32_t  isrflags = READ_REG(huart->Instance->ISR);
+  uint32_t  cr1its   = READ_REG(huart->Instance->CR1);
+  uint32_t  cr3its   = READ_REG(huart->Instance->CR3);
+
+  /* Check that a Rx process is ongoing */
+  if (huart->RxState == HAL_UART_STATE_BUSY_RX)
+  {
+    nb_rx_data = huart->NbRxDataToProcess;
+    while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U))
+    {
+      uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
+      *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask);
+      huart->pRxBuffPtr++;
+      huart->RxXferCount--;
+      isrflags = READ_REG(huart->Instance->ISR);
+
+      /* If some non blocking errors occurred */
+      if ((isrflags & (USART_ISR_PE | USART_ISR_FE | USART_ISR_NE)) != 0U)
+      {
+        /* UART parity error interrupt occurred -------------------------------------*/
+        if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))
+        {
+          __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF);
+
+          huart->ErrorCode |= HAL_UART_ERROR_PE;
+        }
+
+        /* UART frame error interrupt occurred --------------------------------------*/
+        if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
+        {
+          __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF);
+
+          huart->ErrorCode |= HAL_UART_ERROR_FE;
+        }
+
+        /* UART noise error interrupt occurred --------------------------------------*/
+        if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
+        {
+          __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF);
+
+          huart->ErrorCode |= HAL_UART_ERROR_NE;
+        }
+
+        /* Call UART Error Call back function if need be ----------------------------*/
+        if (huart->ErrorCode != HAL_UART_ERROR_NONE)
+        {
+          /* Non Blocking error : transfer could go on.
+          Error is notified to user through user error callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+          /*Call registered error callback*/
+          huart->ErrorCallback(huart);
+#else
+          /*Call legacy weak error callback*/
+          HAL_UART_ErrorCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+          huart->ErrorCode = HAL_UART_ERROR_NONE;
+        }
+      }
+
+      if (huart->RxXferCount == 0U)
+      {
+        /* Disable the UART Parity Error Interrupt and RXFT interrupt*/
+        ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+
+        /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error)
+           and RX FIFO Threshold interrupt */
+        ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
+
+        /* Rx process is completed, restore huart->RxState to Ready */
+        huart->RxState = HAL_UART_STATE_READY;
+
+        /* Clear RxISR function pointer */
+        huart->RxISR = NULL;
+
+        /* Initialize type of RxEvent to Transfer Complete */
+        huart->RxEventType = HAL_UART_RXEVENT_TC;
+
+        if (!(IS_LPUART_INSTANCE(huart->Instance)))
+        {
+          /* Check that USART RTOEN bit is set */
+          if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
+          {
+            /* Enable the UART Receiver Timeout Interrupt */
+            ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
+          }
+        }
+
+        /* Check current reception Mode :
+           If Reception till IDLE event has been selected : */
+        if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+        {
+          /* Set reception type to Standard */
+          huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+          /* Disable IDLE interrupt */
+          ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+
+          if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET)
+          {
+            /* Clear IDLE Flag */
+            __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
+          }
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+          /*Call registered Rx Event callback*/
+          huart->RxEventCallback(huart, huart->RxXferSize);
+#else
+          /*Call legacy weak Rx Event callback*/
+          HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+        }
+        else
+        {
+          /* Standard reception API called */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+          /*Call registered Rx complete callback*/
+          huart->RxCpltCallback(huart);
+#else
+          /*Call legacy weak Rx complete callback*/
+          HAL_UART_RxCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+        }
+      }
+    }
+
+    /* When remaining number of bytes to receive is less than the RX FIFO
+    threshold, next incoming frames are processed as if FIFO mode was
+    disabled (i.e. one interrupt per received frame).
+    */
+    rxdatacount = huart->RxXferCount;
+    if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess))
+    {
+      /* Disable the UART RXFT interrupt*/
+      ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE);
+
+      /* Update the RxISR function pointer */
+      huart->RxISR = UART_RxISR_8BIT;
+
+      /* Enable the UART Data Register Not Empty interrupt */
+      ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
+    }
+  }
+  else
+  {
+    /* Clear RXNE interrupt flag */
+    __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+  }
+}
+
+/**
+  * @brief RX interrupt handler for 9 bits data word length and FIFO mode is enabled.
+  * @note   Function is called under interruption only, once
+  *         interruptions have been enabled by HAL_UART_Receive_IT()
+  * @param huart UART handle.
+  * @retval None
+  */
+static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart)
+{
+  uint16_t *tmp;
+  uint16_t  uhMask = huart->Mask;
+  uint16_t  uhdata;
+  uint16_t  nb_rx_data;
+  uint16_t  rxdatacount;
+  uint32_t  isrflags = READ_REG(huart->Instance->ISR);
+  uint32_t  cr1its   = READ_REG(huart->Instance->CR1);
+  uint32_t  cr3its   = READ_REG(huart->Instance->CR3);
+
+  /* Check that a Rx process is ongoing */
+  if (huart->RxState == HAL_UART_STATE_BUSY_RX)
+  {
+    nb_rx_data = huart->NbRxDataToProcess;
+    while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U))
+    {
+      uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
+      tmp = (uint16_t *) huart->pRxBuffPtr ;
+      *tmp = (uint16_t)(uhdata & uhMask);
+      huart->pRxBuffPtr += 2U;
+      huart->RxXferCount--;
+      isrflags = READ_REG(huart->Instance->ISR);
+
+      /* If some non blocking errors occurred */
+      if ((isrflags & (USART_ISR_PE | USART_ISR_FE | USART_ISR_NE)) != 0U)
+      {
+        /* UART parity error interrupt occurred -------------------------------------*/
+        if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))
+        {
+          __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF);
+
+          huart->ErrorCode |= HAL_UART_ERROR_PE;
+        }
+
+        /* UART frame error interrupt occurred --------------------------------------*/
+        if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
+        {
+          __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF);
+
+          huart->ErrorCode |= HAL_UART_ERROR_FE;
+        }
+
+        /* UART noise error interrupt occurred --------------------------------------*/
+        if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
+        {
+          __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF);
+
+          huart->ErrorCode |= HAL_UART_ERROR_NE;
+        }
+
+        /* Call UART Error Call back function if need be ----------------------------*/
+        if (huart->ErrorCode != HAL_UART_ERROR_NONE)
+        {
+          /* Non Blocking error : transfer could go on.
+          Error is notified to user through user error callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+          /*Call registered error callback*/
+          huart->ErrorCallback(huart);
+#else
+          /*Call legacy weak error callback*/
+          HAL_UART_ErrorCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+          huart->ErrorCode = HAL_UART_ERROR_NONE;
+        }
+      }
+
+      if (huart->RxXferCount == 0U)
+      {
+        /* Disable the UART Parity Error Interrupt and RXFT interrupt*/
+        ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+
+        /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error)
+           and RX FIFO Threshold interrupt */
+        ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
+
+        /* Rx process is completed, restore huart->RxState to Ready */
+        huart->RxState = HAL_UART_STATE_READY;
+
+        /* Clear RxISR function pointer */
+        huart->RxISR = NULL;
+
+        /* Initialize type of RxEvent to Transfer Complete */
+        huart->RxEventType = HAL_UART_RXEVENT_TC;
+
+        if (!(IS_LPUART_INSTANCE(huart->Instance)))
+        {
+          /* Check that USART RTOEN bit is set */
+          if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
+          {
+            /* Enable the UART Receiver Timeout Interrupt */
+            ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
+          }
+        }
+
+        /* Check current reception Mode :
+           If Reception till IDLE event has been selected : */
+        if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+        {
+          /* Set reception type to Standard */
+          huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+          /* Disable IDLE interrupt */
+          ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+
+          if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET)
+          {
+            /* Clear IDLE Flag */
+            __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
+          }
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+          /*Call registered Rx Event callback*/
+          huart->RxEventCallback(huart, huart->RxXferSize);
+#else
+          /*Call legacy weak Rx Event callback*/
+          HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+        }
+        else
+        {
+          /* Standard reception API called */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+          /*Call registered Rx complete callback*/
+          huart->RxCpltCallback(huart);
+#else
+          /*Call legacy weak Rx complete callback*/
+          HAL_UART_RxCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+        }
+      }
+    }
+
+    /* When remaining number of bytes to receive is less than the RX FIFO
+    threshold, next incoming frames are processed as if FIFO mode was
+    disabled (i.e. one interrupt per received frame).
+    */
+    rxdatacount = huart->RxXferCount;
+    if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess))
+    {
+      /* Disable the UART RXFT interrupt*/
+      ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE);
+
+      /* Update the RxISR function pointer */
+      huart->RxISR = UART_RxISR_16BIT;
+
+      /* Enable the UART Data Register Not Empty interrupt */
+      ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
+    }
+  }
+  else
+  {
+    /* Clear RXNE interrupt flag */
+    __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+  }
+}
+
+/**
+  * @}
+  */
+
+#endif /* HAL_UART_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
diff --git a/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c b/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c
new file mode 100644
index 0000000..2bba9dc
--- /dev/null
+++ b/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c
@@ -0,0 +1,1044 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_uart_ex.c
+  * @author  MCD Application Team
+  * @brief   Extended UART HAL module driver.
+  *          This file provides firmware functions to manage the following extended
+  *          functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART).
+  *           + Initialization and de-initialization functions
+  *           + Peripheral Control functions
+  *
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+               ##### UART peripheral extended features  #####
+  ==============================================================================
+
+    (#) Declare a UART_HandleTypeDef handle structure.
+
+    (#) For the UART RS485 Driver Enable mode, initialize the UART registers
+        by calling the HAL_RS485Ex_Init() API.
+
+    (#) FIFO mode enabling/disabling and RX/TX FIFO threshold programming.
+
+        -@- When UART operates in FIFO mode, FIFO mode must be enabled prior
+            starting RX/TX transfers. Also RX/TX FIFO thresholds must be
+            configured prior starting RX/TX transfers.
+
+  @endverbatim
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup UARTEx UARTEx
+  * @brief UART Extended HAL module driver
+  * @{
+  */
+
+#ifdef HAL_UART_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup UARTEX_Private_Constants UARTEx Private Constants
+  * @{
+  */
+/* UART RX FIFO depth */
+#define RX_FIFO_DEPTH 16U
+
+/* UART TX FIFO depth */
+#define TX_FIFO_DEPTH 16U
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup UARTEx_Private_Functions UARTEx Private Functions
+  * @{
+  */
+static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection);
+static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart);
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup UARTEx_Exported_Functions  UARTEx Exported Functions
+  * @{
+  */
+
+/** @defgroup UARTEx_Exported_Functions_Group1 Initialization and de-initialization functions
+  * @brief    Extended Initialization and Configuration Functions
+  *
+@verbatim
+===============================================================================
+            ##### Initialization and Configuration functions #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to initialize the USARTx or the UARTy
+    in asynchronous mode.
+      (+) For the asynchronous mode the parameters below can be configured:
+        (++) Baud Rate
+        (++) Word Length
+        (++) Stop Bit
+        (++) Parity: If the parity is enabled, then the MSB bit of the data written
+             in the data register is transmitted but is changed by the parity bit.
+        (++) Hardware flow control
+        (++) Receiver/transmitter modes
+        (++) Over Sampling Method
+        (++) One-Bit Sampling Method
+      (+) For the asynchronous mode, the following advanced features can be configured as well:
+        (++) TX and/or RX pin level inversion
+        (++) data logical level inversion
+        (++) RX and TX pins swap
+        (++) RX overrun detection disabling
+        (++) DMA disabling on RX error
+        (++) MSB first on communication line
+        (++) auto Baud rate detection
+    [..]
+    The HAL_RS485Ex_Init() API follows the UART RS485 mode configuration
+     procedures (details for the procedures are available in reference manual).
+
+@endverbatim
+
+  Depending on the frame length defined by the M1 and M0 bits (7-bit,
+  8-bit or 9-bit), the possible UART formats are listed in the
+  following table.
+
+    Table 1. UART frame format.
+    +-----------------------------------------------------------------------+
+    |  M1 bit |  M0 bit |  PCE bit  |             UART frame                |
+    |---------|---------|-----------|---------------------------------------|
+    |    0    |    0    |    0      |    | SB |    8 bit data   | STB |     |
+    |---------|---------|-----------|---------------------------------------|
+    |    0    |    0    |    1      |    | SB | 7 bit data | PB | STB |     |
+    |---------|---------|-----------|---------------------------------------|
+    |    0    |    1    |    0      |    | SB |    9 bit data   | STB |     |
+    |---------|---------|-----------|---------------------------------------|
+    |    0    |    1    |    1      |    | SB | 8 bit data | PB | STB |     |
+    |---------|---------|-----------|---------------------------------------|
+    |    1    |    0    |    0      |    | SB |    7 bit data   | STB |     |
+    |---------|---------|-----------|---------------------------------------|
+    |    1    |    0    |    1      |    | SB | 6 bit data | PB | STB |     |
+    +-----------------------------------------------------------------------+
+
+  * @{
+  */
+
+/**
+  * @brief Initialize the RS485 Driver enable feature according to the specified
+  *         parameters in the UART_InitTypeDef and creates the associated handle.
+  * @param huart            UART handle.
+  * @param Polarity         Select the driver enable polarity.
+  *          This parameter can be one of the following values:
+  *          @arg @ref UART_DE_POLARITY_HIGH DE signal is active high
+  *          @arg @ref UART_DE_POLARITY_LOW  DE signal is active low
+  * @param AssertionTime    Driver Enable assertion time:
+  *       5-bit value defining the time between the activation of the DE (Driver Enable)
+  *       signal and the beginning of the start bit. It is expressed in sample time
+  *       units (1/8 or 1/16 bit time, depending on the oversampling rate)
+  * @param DeassertionTime  Driver Enable deassertion time:
+  *       5-bit value defining the time between the end of the last stop bit, in a
+  *       transmitted message, and the de-activation of the DE (Driver Enable) signal.
+  *       It is expressed in sample time units (1/8 or 1/16 bit time, depending on the
+  *       oversampling rate).
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime,
+                                   uint32_t DeassertionTime)
+{
+  uint32_t temp;
+
+  /* Check the UART handle allocation */
+  if (huart == NULL)
+  {
+    return HAL_ERROR;
+  }
+  /* Check the Driver Enable UART instance */
+  assert_param(IS_UART_DRIVER_ENABLE_INSTANCE(huart->Instance));
+
+  /* Check the Driver Enable polarity */
+  assert_param(IS_UART_DE_POLARITY(Polarity));
+
+  /* Check the Driver Enable assertion time */
+  assert_param(IS_UART_ASSERTIONTIME(AssertionTime));
+
+  /* Check the Driver Enable deassertion time */
+  assert_param(IS_UART_DEASSERTIONTIME(DeassertionTime));
+
+  if (huart->gState == HAL_UART_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    huart->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+    UART_InitCallbacksToDefault(huart);
+
+    if (huart->MspInitCallback == NULL)
+    {
+      huart->MspInitCallback = HAL_UART_MspInit;
+    }
+
+    /* Init the low level hardware */
+    huart->MspInitCallback(huart);
+#else
+    /* Init the low level hardware : GPIO, CLOCK, CORTEX */
+    HAL_UART_MspInit(huart);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+  }
+
+  huart->gState = HAL_UART_STATE_BUSY;
+
+  /* Disable the Peripheral */
+  __HAL_UART_DISABLE(huart);
+
+  /* Set the UART Communication parameters */
+  if (UART_SetConfig(huart) == HAL_ERROR)
+  {
+    return HAL_ERROR;
+  }
+
+  if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
+  {
+    UART_AdvFeatureConfig(huart);
+  }
+
+  /* Enable the Driver Enable mode by setting the DEM bit in the CR3 register */
+  SET_BIT(huart->Instance->CR3, USART_CR3_DEM);
+
+  /* Set the Driver Enable polarity */
+  MODIFY_REG(huart->Instance->CR3, USART_CR3_DEP, Polarity);
+
+  /* Set the Driver Enable assertion and deassertion times */
+  temp = (AssertionTime << UART_CR1_DEAT_ADDRESS_LSB_POS);
+  temp |= (DeassertionTime << UART_CR1_DEDT_ADDRESS_LSB_POS);
+  MODIFY_REG(huart->Instance->CR1, (USART_CR1_DEDT | USART_CR1_DEAT), temp);
+
+  /* Enable the Peripheral */
+  __HAL_UART_ENABLE(huart);
+
+  /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
+  return (UART_CheckIdleState(huart));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup UARTEx_Exported_Functions_Group2 IO operation functions
+  *  @brief Extended functions
+  *
+@verbatim
+ ===============================================================================
+                      ##### IO operation functions #####
+ ===============================================================================
+    This subsection provides a set of Wakeup and FIFO mode related callback functions.
+
+    (#) Wakeup from Stop mode Callback:
+        (+) HAL_UARTEx_WakeupCallback()
+
+    (#) TX/RX Fifos Callbacks:
+        (+) HAL_UARTEx_RxFifoFullCallback()
+        (+) HAL_UARTEx_TxFifoEmptyCallback()
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief UART wakeup from Stop mode callback.
+  * @param huart UART handle.
+  * @retval None
+  */
+__weak void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(huart);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_UARTEx_WakeupCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  UART RX Fifo full callback.
+  * @param  huart UART handle.
+  * @retval None
+  */
+__weak void HAL_UARTEx_RxFifoFullCallback(UART_HandleTypeDef *huart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(huart);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_UARTEx_RxFifoFullCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  UART TX Fifo empty callback.
+  * @param  huart UART handle.
+  * @retval None
+  */
+__weak void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(huart);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_UARTEx_TxFifoEmptyCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup UARTEx_Exported_Functions_Group3 Peripheral Control functions
+  * @brief    Extended Peripheral Control functions
+  *
+@verbatim
+ ===============================================================================
+                      ##### Peripheral Control functions #####
+ ===============================================================================
+    [..] This section provides the following functions:
+     (+) HAL_MultiProcessorEx_AddressLength_Set() API optionally sets the UART node address
+         detection length to more than 4 bits for multiprocessor address mark wake up.
+     (+) HAL_UARTEx_StopModeWakeUpSourceConfig() API defines the wake-up from stop mode
+         trigger: address match, Start Bit detection or RXNE bit status.
+     (+) HAL_UARTEx_EnableStopMode() API enables the UART to wake up the MCU from stop mode
+     (+) HAL_UARTEx_DisableStopMode() API disables the above functionality
+     (+) HAL_UARTEx_EnableFifoMode() API enables the FIFO mode
+     (+) HAL_UARTEx_DisableFifoMode() API disables the FIFO mode
+     (+) HAL_UARTEx_SetTxFifoThreshold() API sets the TX FIFO threshold
+     (+) HAL_UARTEx_SetRxFifoThreshold() API sets the RX FIFO threshold
+
+    [..] This subsection also provides a set of additional functions providing enhanced reception
+    services to user. (For example, these functions allow application to handle use cases
+    where number of data to be received is unknown).
+
+    (#) Compared to standard reception services which only consider number of received
+        data elements as reception completion criteria, these functions also consider additional events
+        as triggers for updating reception status to caller :
+       (+) Detection of inactivity period (RX line has not been active for a given period).
+          (++) RX inactivity detected by IDLE event, i.e. RX line has been in idle state (normally high state)
+               for 1 frame time, after last received byte.
+          (++) RX inactivity detected by RTO, i.e. line has been in idle state
+               for a programmable time, after last received byte.
+       (+) Detection that a specific character has been received.
+
+    (#) There are two mode of transfer:
+       (+) Blocking mode: The reception is performed in polling mode, until either expected number of data is received,
+           or till IDLE event occurs. Reception is handled only during function execution.
+           When function exits, no data reception could occur. HAL status and number of actually received data elements,
+           are returned by function after finishing transfer.
+       (+) Non-Blocking mode: The reception is performed using Interrupts or DMA.
+           These API's return the HAL status.
+           The end of the data processing will be indicated through the
+           dedicated UART IRQ when using Interrupt mode or the DMA IRQ when using DMA mode.
+           The HAL_UARTEx_RxEventCallback() user callback will be executed during Receive process
+           The HAL_UART_ErrorCallback()user callback will be executed when a reception error is detected.
+
+    (#) Blocking mode API:
+        (+) HAL_UARTEx_ReceiveToIdle()
+
+    (#) Non-Blocking mode API with Interrupt:
+        (+) HAL_UARTEx_ReceiveToIdle_IT()
+
+    (#) Non-Blocking mode API with DMA:
+        (+) HAL_UARTEx_ReceiveToIdle_DMA()
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief By default in multiprocessor mode, when the wake up method is set
+  *        to address mark, the UART handles only 4-bit long addresses detection;
+  *        this API allows to enable longer addresses detection (6-, 7- or 8-bit
+  *        long).
+  * @note  Addresses detection lengths are: 6-bit address detection in 7-bit data mode,
+  *        7-bit address detection in 8-bit data mode, 8-bit address detection in 9-bit data mode.
+  * @param huart         UART handle.
+  * @param AddressLength This parameter can be one of the following values:
+  *          @arg @ref UART_ADDRESS_DETECT_4B 4-bit long address
+  *          @arg @ref UART_ADDRESS_DETECT_7B 6-, 7- or 8-bit long address
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength)
+{
+  /* Check the UART handle allocation */
+  if (huart == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the address length parameter */
+  assert_param(IS_UART_ADDRESSLENGTH_DETECT(AddressLength));
+
+  huart->gState = HAL_UART_STATE_BUSY;
+
+  /* Disable the Peripheral */
+  __HAL_UART_DISABLE(huart);
+
+  /* Set the address length */
+  MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, AddressLength);
+
+  /* Enable the Peripheral */
+  __HAL_UART_ENABLE(huart);
+
+  /* TEACK and/or REACK to check before moving huart->gState to Ready */
+  return (UART_CheckIdleState(huart));
+}
+
+/**
+  * @brief Set Wakeup from Stop mode interrupt flag selection.
+  * @note It is the application responsibility to enable the interrupt used as
+  *       usart_wkup interrupt source before entering low-power mode.
+  * @param huart           UART handle.
+  * @param WakeUpSelection Address match, Start Bit detection or RXNE/RXFNE bit status.
+  *          This parameter can be one of the following values:
+  *          @arg @ref UART_WAKEUP_ON_ADDRESS
+  *          @arg @ref UART_WAKEUP_ON_STARTBIT
+  *          @arg @ref UART_WAKEUP_ON_READDATA_NONEMPTY
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t tickstart;
+
+  /* check the wake-up from stop mode UART instance */
+  assert_param(IS_UART_WAKEUP_FROMSTOP_INSTANCE(huart->Instance));
+  /* check the wake-up selection parameter */
+  assert_param(IS_UART_WAKEUP_SELECTION(WakeUpSelection.WakeUpEvent));
+
+  /* Process Locked */
+  __HAL_LOCK(huart);
+
+  huart->gState = HAL_UART_STATE_BUSY;
+
+  /* Disable the Peripheral */
+  __HAL_UART_DISABLE(huart);
+
+  /* Set the wake-up selection scheme */
+  MODIFY_REG(huart->Instance->CR3, USART_CR3_WUS, WakeUpSelection.WakeUpEvent);
+
+  if (WakeUpSelection.WakeUpEvent == UART_WAKEUP_ON_ADDRESS)
+  {
+    UARTEx_Wakeup_AddressConfig(huart, WakeUpSelection);
+  }
+
+  /* Enable the Peripheral */
+  __HAL_UART_ENABLE(huart);
+
+  /* Init tickstart for timeout management */
+  tickstart = HAL_GetTick();
+
+  /* Wait until REACK flag is set */
+  if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
+  {
+    status = HAL_TIMEOUT;
+  }
+  else
+  {
+    /* Initialize the UART State */
+    huart->gState = HAL_UART_STATE_READY;
+  }
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(huart);
+
+  return status;
+}
+
+/**
+  * @brief Enable UART Stop Mode.
+  * @note The UART is able to wake up the MCU from Stop 1 mode as long as UART clock is HSI or LSE.
+  * @param huart UART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart)
+{
+  /* Process Locked */
+  __HAL_LOCK(huart);
+
+  /* Set UESM bit */
+  ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_UESM);
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(huart);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Disable UART Stop Mode.
+  * @param huart UART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart)
+{
+  /* Process Locked */
+  __HAL_LOCK(huart);
+
+  /* Clear UESM bit */
+  ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_UESM);
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(huart);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enable the FIFO mode.
+  * @param huart      UART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UARTEx_EnableFifoMode(UART_HandleTypeDef *huart)
+{
+  uint32_t tmpcr1;
+
+  /* Check parameters */
+  assert_param(IS_UART_FIFO_INSTANCE(huart->Instance));
+
+  /* Process Locked */
+  __HAL_LOCK(huart);
+
+  huart->gState = HAL_UART_STATE_BUSY;
+
+  /* Save actual UART configuration */
+  tmpcr1 = READ_REG(huart->Instance->CR1);
+
+  /* Disable UART */
+  __HAL_UART_DISABLE(huart);
+
+  /* Enable FIFO mode */
+  SET_BIT(tmpcr1, USART_CR1_FIFOEN);
+  huart->FifoMode = UART_FIFOMODE_ENABLE;
+
+  /* Restore UART configuration */
+  WRITE_REG(huart->Instance->CR1, tmpcr1);
+
+  /* Determine the number of data to process during RX/TX ISR execution */
+  UARTEx_SetNbDataToProcess(huart);
+
+  huart->gState = HAL_UART_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(huart);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Disable the FIFO mode.
+  * @param huart      UART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart)
+{
+  uint32_t tmpcr1;
+
+  /* Check parameters */
+  assert_param(IS_UART_FIFO_INSTANCE(huart->Instance));
+
+  /* Process Locked */
+  __HAL_LOCK(huart);
+
+  huart->gState = HAL_UART_STATE_BUSY;
+
+  /* Save actual UART configuration */
+  tmpcr1 = READ_REG(huart->Instance->CR1);
+
+  /* Disable UART */
+  __HAL_UART_DISABLE(huart);
+
+  /* Enable FIFO mode */
+  CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN);
+  huart->FifoMode = UART_FIFOMODE_DISABLE;
+
+  /* Restore UART configuration */
+  WRITE_REG(huart->Instance->CR1, tmpcr1);
+
+  huart->gState = HAL_UART_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(huart);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Set the TXFIFO threshold.
+  * @param huart      UART handle.
+  * @param Threshold  TX FIFO threshold value
+  *          This parameter can be one of the following values:
+  *            @arg @ref UART_TXFIFO_THRESHOLD_1_8
+  *            @arg @ref UART_TXFIFO_THRESHOLD_1_4
+  *            @arg @ref UART_TXFIFO_THRESHOLD_1_2
+  *            @arg @ref UART_TXFIFO_THRESHOLD_3_4
+  *            @arg @ref UART_TXFIFO_THRESHOLD_7_8
+  *            @arg @ref UART_TXFIFO_THRESHOLD_8_8
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold)
+{
+  uint32_t tmpcr1;
+
+  /* Check parameters */
+  assert_param(IS_UART_FIFO_INSTANCE(huart->Instance));
+  assert_param(IS_UART_TXFIFO_THRESHOLD(Threshold));
+
+  /* Process Locked */
+  __HAL_LOCK(huart);
+
+  huart->gState = HAL_UART_STATE_BUSY;
+
+  /* Save actual UART configuration */
+  tmpcr1 = READ_REG(huart->Instance->CR1);
+
+  /* Disable UART */
+  __HAL_UART_DISABLE(huart);
+
+  /* Update TX threshold configuration */
+  MODIFY_REG(huart->Instance->CR3, USART_CR3_TXFTCFG, Threshold);
+
+  /* Determine the number of data to process during RX/TX ISR execution */
+  UARTEx_SetNbDataToProcess(huart);
+
+  /* Restore UART configuration */
+  WRITE_REG(huart->Instance->CR1, tmpcr1);
+
+  huart->gState = HAL_UART_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(huart);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Set the RXFIFO threshold.
+  * @param huart      UART handle.
+  * @param Threshold  RX FIFO threshold value
+  *          This parameter can be one of the following values:
+  *            @arg @ref UART_RXFIFO_THRESHOLD_1_8
+  *            @arg @ref UART_RXFIFO_THRESHOLD_1_4
+  *            @arg @ref UART_RXFIFO_THRESHOLD_1_2
+  *            @arg @ref UART_RXFIFO_THRESHOLD_3_4
+  *            @arg @ref UART_RXFIFO_THRESHOLD_7_8
+  *            @arg @ref UART_RXFIFO_THRESHOLD_8_8
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold)
+{
+  uint32_t tmpcr1;
+
+  /* Check the parameters */
+  assert_param(IS_UART_FIFO_INSTANCE(huart->Instance));
+  assert_param(IS_UART_RXFIFO_THRESHOLD(Threshold));
+
+  /* Process Locked */
+  __HAL_LOCK(huart);
+
+  huart->gState = HAL_UART_STATE_BUSY;
+
+  /* Save actual UART configuration */
+  tmpcr1 = READ_REG(huart->Instance->CR1);
+
+  /* Disable UART */
+  __HAL_UART_DISABLE(huart);
+
+  /* Update RX threshold configuration */
+  MODIFY_REG(huart->Instance->CR3, USART_CR3_RXFTCFG, Threshold);
+
+  /* Determine the number of data to process during RX/TX ISR execution */
+  UARTEx_SetNbDataToProcess(huart);
+
+  /* Restore UART configuration */
+  WRITE_REG(huart->Instance->CR1, tmpcr1);
+
+  huart->gState = HAL_UART_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(huart);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Receive an amount of data in blocking mode till either the expected number of data
+  *        is received or an IDLE event occurs.
+  * @note  HAL_OK is returned if reception is completed (expected number of data has been received)
+  *        or if reception is stopped after IDLE event (less than the expected number of data has been received)
+  *        In this case, RxLen output parameter indicates number of data available in reception buffer.
+  * @note  When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+  *        the received data is handled as a set of uint16_t. In this case, Size must indicate the number
+  *        of uint16_t available through pData.
+  * @note When FIFO mode is enabled, the RXFNE flag is set as long as the RXFIFO
+  *       is not empty. Read operations from the RDR register are performed when
+  *       RXFNE flag is set. From hardware perspective, RXFNE flag and
+  *       RXNE are mapped on the same bit-field.
+  * @param huart   UART handle.
+  * @param pData   Pointer to data buffer (uint8_t or uint16_t data elements).
+  * @param Size    Amount of data elements (uint8_t or uint16_t) to be received.
+  * @param RxLen   Number of data elements finally received
+  *                (could be lower than Size, in case reception ends on IDLE event)
+  * @param Timeout Timeout duration expressed in ms (covers the whole reception sequence).
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen,
+                                           uint32_t Timeout)
+{
+  uint8_t  *pdata8bits;
+  uint16_t *pdata16bits;
+  uint16_t uhMask;
+  uint32_t tickstart;
+
+  /* Check that a Rx process is not already ongoing */
+  if (huart->RxState == HAL_UART_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      return  HAL_ERROR;
+    }
+
+    huart->ErrorCode = HAL_UART_ERROR_NONE;
+    huart->RxState = HAL_UART_STATE_BUSY_RX;
+    huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE;
+    huart->RxEventType = HAL_UART_RXEVENT_TC;
+
+    /* Init tickstart for timeout management */
+    tickstart = HAL_GetTick();
+
+    huart->RxXferSize  = Size;
+    huart->RxXferCount = Size;
+
+    /* Computation of UART mask to apply to RDR register */
+    UART_MASK_COMPUTATION(huart);
+    uhMask = huart->Mask;
+
+    /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */
+    if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
+    {
+      pdata8bits  = NULL;
+      pdata16bits = (uint16_t *) pData;
+    }
+    else
+    {
+      pdata8bits  = pData;
+      pdata16bits = NULL;
+    }
+
+    /* Initialize output number of received elements */
+    *RxLen = 0U;
+
+    /* as long as data have to be received */
+    while (huart->RxXferCount > 0U)
+    {
+      /* Check if IDLE flag is set */
+      if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE))
+      {
+        /* Clear IDLE flag in ISR */
+        __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
+
+        /* If Set, but no data ever received, clear flag without exiting loop */
+        /* If Set, and data has already been received, this means Idle Event is valid : End reception */
+        if (*RxLen > 0U)
+        {
+          huart->RxEventType = HAL_UART_RXEVENT_IDLE;
+          huart->RxState = HAL_UART_STATE_READY;
+
+          return HAL_OK;
+        }
+      }
+
+      /* Check if RXNE flag is set */
+      if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RXNE))
+      {
+        if (pdata8bits == NULL)
+        {
+          *pdata16bits = (uint16_t)(huart->Instance->RDR & uhMask);
+          pdata16bits++;
+        }
+        else
+        {
+          *pdata8bits = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask);
+          pdata8bits++;
+        }
+        /* Increment number of received elements */
+        *RxLen += 1U;
+        huart->RxXferCount--;
+      }
+
+      /* Check for the Timeout */
+      if (Timeout != HAL_MAX_DELAY)
+      {
+        if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+        {
+          huart->RxState = HAL_UART_STATE_READY;
+
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+
+    /* Set number of received elements in output parameter : RxLen */
+    *RxLen = huart->RxXferSize - huart->RxXferCount;
+    /* At end of Rx process, restore huart->RxState to Ready */
+    huart->RxState = HAL_UART_STATE_READY;
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief Receive an amount of data in interrupt mode till either the expected number of data
+  *        is received or an IDLE event occurs.
+  * @note  Reception is initiated by this function call. Further progress of reception is achieved thanks
+  *        to UART interrupts raised by RXNE and IDLE events. Callback is called at end of reception indicating
+  *        number of received data elements.
+  * @note  When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+  *        the received data is handled as a set of uint16_t. In this case, Size must indicate the number
+  *        of uint16_t available through pData.
+  * @param huart UART handle.
+  * @param pData Pointer to data buffer (uint8_t or uint16_t data elements).
+  * @param Size  Amount of data elements (uint8_t or uint16_t) to be received.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
+{
+  HAL_StatusTypeDef status;
+
+  /* Check that a Rx process is not already ongoing */
+  if (huart->RxState == HAL_UART_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      return HAL_ERROR;
+    }
+
+    /* Set Reception type to reception till IDLE Event*/
+    huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE;
+    huart->RxEventType = HAL_UART_RXEVENT_TC;
+
+    status =  UART_Start_Receive_IT(huart, pData, Size);
+
+    /* Check Rx process has been successfully started */
+    if (status == HAL_OK)
+    {
+      if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+      {
+        __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
+        ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+      }
+      else
+      {
+        /* In case of errors already pending when reception is started,
+           Interrupts may have already been raised and lead to reception abortion.
+           (Overrun error for instance).
+           In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */
+        status = HAL_ERROR;
+      }
+    }
+
+    return status;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief Receive an amount of data in DMA mode till either the expected number
+  *        of data is received or an IDLE event occurs.
+  * @note  Reception is initiated by this function call. Further progress of reception is achieved thanks
+  *        to DMA services, transferring automatically received data elements in user reception buffer and
+  *        calling registered callbacks at half/end of reception. UART IDLE events are also used to consider
+  *        reception phase as ended. In all cases, callback execution will indicate number of received data elements.
+  * @note  When the UART parity is enabled (PCE = 1), the received data contain
+  *        the parity bit (MSB position).
+  * @note  When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+  *        the received data is handled as a set of uint16_t. In this case, Size must indicate the number
+  *        of uint16_t available through pData.
+  * @param huart UART handle.
+  * @param pData Pointer to data buffer (uint8_t or uint16_t data elements).
+  * @param Size  Amount of data elements (uint8_t or uint16_t) to be received.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
+{
+  HAL_StatusTypeDef status;
+
+  /* Check that a Rx process is not already ongoing */
+  if (huart->RxState == HAL_UART_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      return HAL_ERROR;
+    }
+
+    /* Set Reception type to reception till IDLE Event*/
+    huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE;
+    huart->RxEventType = HAL_UART_RXEVENT_TC;
+
+    status =  UART_Start_Receive_DMA(huart, pData, Size);
+
+    /* Check Rx process has been successfully started */
+    if (status == HAL_OK)
+    {
+      if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+      {
+        __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
+        ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+      }
+      else
+      {
+        /* In case of errors already pending when reception is started,
+           Interrupts may have already been raised and lead to reception abortion.
+           (Overrun error for instance).
+           In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */
+        status = HAL_ERROR;
+      }
+    }
+
+    return status;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief Provide Rx Event type that has lead to RxEvent callback execution.
+  * @note  When HAL_UARTEx_ReceiveToIdle_IT() or HAL_UARTEx_ReceiveToIdle_DMA() API are called, progress
+  *        of reception process is provided to application through calls of Rx Event callback (either default one
+  *        HAL_UARTEx_RxEventCallback() or user registered one). As several types of events could occur (IDLE event,
+  *        Half Transfer, or Transfer Complete), this function allows to retrieve the Rx Event type that has lead
+  *        to Rx Event callback execution.
+  * @note  This function is expected to be called within the user implementation of Rx Event Callback,
+  *        in order to provide the accurate value :
+  *        In Interrupt Mode :
+  *           - HAL_UART_RXEVENT_TC : when Reception has been completed (expected nb of data has been received)
+  *           - HAL_UART_RXEVENT_IDLE : when Idle event occurred prior reception has been completed (nb of
+  *             received data is lower than expected one)
+  *        In DMA Mode :
+  *           - HAL_UART_RXEVENT_TC : when Reception has been completed (expected nb of data has been received)
+  *           - HAL_UART_RXEVENT_HT : when half of expected nb of data has been received
+  *           - HAL_UART_RXEVENT_IDLE : when Idle event occurred prior reception has been completed (nb of
+  *             received data is lower than expected one).
+  *        In DMA mode, RxEvent callback could be called several times;
+  *        When DMA is configured in Normal Mode, HT event does not stop Reception process;
+  *        When DMA is configured in Circular Mode, HT, TC or IDLE events don't stop Reception process;
+  * @param  huart UART handle.
+  * @retval Rx Event Type (return vale will be a value of @ref UART_RxEvent_Type_Values)
+  */
+HAL_UART_RxEventTypeTypeDef HAL_UARTEx_GetRxEventType(UART_HandleTypeDef *huart)
+{
+  /* Return Rx Event type value, as stored in UART handle */
+  return (huart->RxEventType);
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup UARTEx_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief Initialize the UART wake-up from stop mode parameters when triggered by address detection.
+  * @param huart           UART handle.
+  * @param WakeUpSelection UART wake up from stop mode parameters.
+  * @retval None
+  */
+static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection)
+{
+  assert_param(IS_UART_ADDRESSLENGTH_DETECT(WakeUpSelection.AddressLength));
+
+  /* Set the USART address length */
+  MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, WakeUpSelection.AddressLength);
+
+  /* Set the USART address node */
+  MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)WakeUpSelection.Address << UART_CR2_ADDRESS_LSB_POS));
+}
+
+/**
+  * @brief Calculate the number of data to process in RX/TX ISR.
+  * @note The RX FIFO depth and the TX FIFO depth is extracted from
+  *       the UART configuration registers.
+  * @param huart UART handle.
+  * @retval None
+  */
+static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart)
+{
+  uint8_t rx_fifo_depth;
+  uint8_t tx_fifo_depth;
+  uint8_t rx_fifo_threshold;
+  uint8_t tx_fifo_threshold;
+  static const uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U};
+  static const uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U};
+
+  if (huart->FifoMode == UART_FIFOMODE_DISABLE)
+  {
+    huart->NbTxDataToProcess = 1U;
+    huart->NbRxDataToProcess = 1U;
+  }
+  else
+  {
+    rx_fifo_depth = RX_FIFO_DEPTH;
+    tx_fifo_depth = TX_FIFO_DEPTH;
+    rx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos);
+    tx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos);
+    huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) /
+                               (uint16_t)denominator[tx_fifo_threshold];
+    huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) /
+                               (uint16_t)denominator[rx_fifo_threshold];
+  }
+}
+/**
+  * @}
+  */
+
+#endif /* HAL_UART_MODULE_ENABLED */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
diff --git a/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_delayblock.c b/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_delayblock.c
new file mode 100644
index 0000000..d7ac9bc
--- /dev/null
+++ b/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_delayblock.c
@@ -0,0 +1,214 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_ll_delayblock.c
+  * @author  MCD Application Team
+  * @brief   DelayBlock Low Layer HAL module driver.
+  *    
+  *          This file provides firmware functions to manage the following 
+  *          functionalities of the Delay Block peripheral:
+  *           + input clock frequency range 25MHz to 208MHz
+  *           + up to 12 oversampling phases
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+                       ##### DelayBlock peripheral features #####
+  ==============================================================================        
+    [..] The Delay block is used to generate an Output clock which is de-phased from the Input
+          clock. The phase of the Output clock is programmed by FW. The Output clock is then used
+          to clock the receive data in i.e. a SDMMC or QSPI interface.
+         The delay is Voltage and Temperature dependent, which may require FW to do re-tuning
+          and recenter the Output clock phase to the receive data.
+    
+    [..] The Delay Block features include the following:
+         (+) Input clock frequency range 25MHz to 208MHz.
+         (+) Up to 12 oversampling phases.
+         
+                           ##### How to use this driver #####
+  ==============================================================================
+    [..]
+      This driver is a considered as a driver of service for external devices drivers
+      that interfaces with the DELAY peripheral.
+      The DelayBlock_Enable() function, enables the DelayBlock instance, configure the delay line length
+      and configure the Output clock phase.
+      The DelayBlock_Disable() function, disables the DelayBlock instance by setting DEN flag to 0.
+      
+  
+  @endverbatim
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup DELAYBLOCK_LL DELAYBLOCK_LL
+  * @brief Low layer module for Delay Block
+  * @{
+  */
+
+#if defined(HAL_SD_MODULE_ENABLED) || defined(HAL_QSPI_MODULE_ENABLED)
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup DelayBlock_LL_Private_Defines Delay Block Low Layer Private Defines
+  * @{
+  */
+#define DLYB_TIMEOUT 0xFFU
+/**
+  * @}
+  */
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup DelayBlock_LL_Exported_Functions Delay Block Low Layer Exported Functions
+  * @{
+  */
+
+/** @defgroup HAL_DELAY_LL_Group1 Initialization de-initialization functions 
+ *  @brief    Initialization and Configuration functions 
+ *
+@verbatim    
+ ===============================================================================
+              ##### Initialization and de-initialization functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+ 
+@endverbatim
+  * @{
+  */
+
+
+/**
+  * @brief  Enable the Delay Block instance.
+  * @param  DLYBx: Pointer to DLYB instance.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef DelayBlock_Enable(DLYB_TypeDef *DLYBx)
+{
+  uint32_t unit = 0U;
+  uint32_t sel = 0U;
+  uint32_t sel_current;
+  uint32_t unit_current;
+  uint32_t tuning;
+  uint32_t lng_mask;
+  uint32_t tickstart;
+
+  DLYBx->CR = DLYB_CR_DEN | DLYB_CR_SEN;
+
+  for (sel_current = 0U; sel_current < DLYB_MAX_SELECT; sel_current++)
+  {
+    /* lng_mask is the mask bit for the LNG field to check the output of the UNITx*/
+    lng_mask = DLYB_CFGR_LNG_0 << sel_current;
+    tuning = 0U;
+    for (unit_current = 0U; unit_current < DLYB_MAX_UNIT; unit_current++)
+    {
+      /* Set the Delay of the UNIT(s)*/
+      DLYBx->CFGR = DLYB_MAX_SELECT | (unit_current << DLYB_CFGR_UNIT_Pos);
+
+      /* Waiting for a LNG valid value */
+      tickstart =  HAL_GetTick();
+      while ((DLYBx->CFGR & DLYB_CFGR_LNGF) == 0U)
+      {
+        if((HAL_GetTick() - tickstart) >=  DLYB_TIMEOUT)
+        {
+          return HAL_TIMEOUT;
+        }
+      }
+      if (tuning == 0U)
+      {
+        if ((DLYBx->CFGR & lng_mask) != 0U)
+        {
+          /* 1/2 period HIGH is detected */
+          tuning = 1U;
+        }
+      }
+      else
+      {
+        /* 1/2 period LOW detected after the HIGH 1/2 period => FULL PERIOD passed*/
+        if((DLYBx->CFGR & lng_mask ) == 0U)
+        {
+          /* Save the first result */
+          if( unit == 0U )
+          {
+            unit = unit_current;
+            sel  = sel_current + 1U;
+          }
+          break;
+        }
+      }
+    }
+  }
+
+  /* Apply the Tuning settings */
+  DLYBx->CR   = 0U;
+  DLYBx->CR   = DLYB_CR_DEN | DLYB_CR_SEN;
+  DLYBx->CFGR = sel | (unit << DLYB_CFGR_UNIT_Pos);
+  DLYBx->CR   = DLYB_CR_DEN;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Disable the Delay Block instance.
+  * @param  DLYBx: Pointer to DLYB instance.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef DelayBlock_Disable(DLYB_TypeDef *DLYBx)
+{
+  /* Disable DLYB */
+  DLYBx->CR = 0U;
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configure the Delay Block instance.
+  * @param  DLYBx: Pointer to DLYB instance.
+  * @param  PhaseSel: Phase selection [0..11].
+  * @param  Units: Delay units[0..127].
+  * @retval HAL status
+  */
+HAL_StatusTypeDef DelayBlock_Configure(DLYB_TypeDef *DLYBx,uint32_t PhaseSel, uint32_t Units )
+{
+  /* Apply the delay settings */
+
+  DLYBx->CR   = 0U;
+  DLYBx->CR   = DLYB_CR_DEN | DLYB_CR_SEN;
+  DLYBx->CFGR = PhaseSel | (Units << DLYB_CFGR_UNIT_Pos);
+  DLYBx->CR   = DLYB_CR_DEN;
+
+  return HAL_OK;
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* (HAL_SD_MODULE_ENABLED) & (HAL_QSPI_MODULE_ENABLED)*/
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
diff --git a/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.c b/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.c
new file mode 100644
index 0000000..38e7697
--- /dev/null
+++ b/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.c
@@ -0,0 +1,1644 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_ll_sdmmc.c
+  * @author  MCD Application Team
+  * @brief   SDMMC Low Layer HAL module driver.
+  *
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the SDMMC peripheral:
+  *           + Initialization/de-initialization functions
+  *           + I/O operation functions
+  *           + Peripheral Control functions
+  *           + Peripheral State functions
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+                       ##### SDMMC peripheral features #####
+  ==============================================================================
+    [..] The SD/SDMMC MMC card host interface (SDMMC) provides an interface between the AHB
+         peripheral bus and MultiMedia cards (MMCs), SD memory cards, SDMMC cards and CE-ATA
+         devices.
+
+    [..] The SDMMC features include the following:
+         (+) Full compliance with MultiMediaCard System Specification Version 4.51. Card support
+             for three different databus modes: 1-bit (default), 4-bit and 8-bit.
+         (+) Full compatibility with previous versions of MultiMediaCards (backward compatibility).
+         (+) Full compliance with SD memory card specifications version 4.1.
+             (SDR104 SDMMC_CK speed limited to maximum allowed IO speed, SPI mode and
+              UHS-II mode not supported).
+         (+) Full compliance with SDIO card specification version 4.0. Card support
+             for two different databus modes: 1-bit (default) and 4-bit.
+             (SDR104 SDMMC_CK speed limited to maximum allowed IO speed, SPI mode and
+              UHS-II mode not supported).
+         (+) Data transfer up to 208 Mbyte/s for the 8 bit mode. (depending maximum allowed IO speed).
+         (+) Data and command output enable signals to control external bidirectional drivers
+
+                           ##### How to use this driver #####
+  ==============================================================================
+    [..]
+      This driver is a considered as a driver of service for external devices drivers
+      that interfaces with the SDMMC peripheral.
+      According to the device used (SD card/ MMC card / SDMMC card ...), a set of APIs
+      is used in the device's driver to perform SDMMC operations and functionalities.
+
+      This driver is almost transparent for the final user, it is only used to implement other
+      functionalities of the external device.
+
+    [..]
+      (+) The SDMMC clock is coming from output of PLL1_Q or PLL2_R.
+       Before start working with SDMMC peripheral make sure that the PLL is well configured.
+          The SDMMC peripheral uses two clock signals:
+          (++) PLL1_Q bus clock (default after reset)
+          (++) PLL2_R bus clock
+
+      (+) Enable/Disable peripheral clock using RCC peripheral macros related to SDMMC
+          peripheral.
+
+      (+) Enable the Power ON State using the SDMMC_PowerState_ON(SDMMCx)
+          function and disable it using the function SDMMC_PowerState_OFF(SDMMCx).
+
+      (+) Enable/Disable the peripheral interrupts using the macros __SDMMC_ENABLE_IT(hSDMMC, IT)
+          and __SDMMC_DISABLE_IT(hSDMMC, IT) if you need to use interrupt mode.
+
+      (+) When using the DMA mode
+          (++) Configure the IDMA mode (Single buffer or double)
+          (++) Configure the buffer address
+          (++) Configure Data Path State Machine
+
+      (+) To control the CPSM (Command Path State Machine) and send
+          commands to the card use the SDMMC_SendCommand(SDMMCx),
+          SDMMC_GetCommandResponse() and SDMMC_GetResponse() functions. First, user has
+          to fill the command structure (pointer to SDMMC_CmdInitTypeDef) according
+          to the selected command to be sent.
+          The parameters that should be filled are:
+           (++) Command Argument
+           (++) Command Index
+           (++) Command Response type
+           (++) Command Wait
+           (++) CPSM Status (Enable or Disable).
+
+          -@@- To check if the command is well received, read the SDMMC_CMDRESP
+              register using the SDMMC_GetCommandResponse().
+              The SDMMC responses registers (SDMMC_RESP1 to SDMMC_RESP2), use the
+              SDMMC_GetResponse() function.
+
+      (+) To control the DPSM (Data Path State Machine) and send/receive
+           data to/from the card use the SDMMC_DataConfig(), SDMMC_GetDataCounter(),
+          SDMMC_ReadFIFO(), SDMMC_WriteFIFO() and SDMMC_GetFIFOCount() functions.
+
+    *** Read Operations ***
+    =======================
+    [..]
+      (#) First, user has to fill the data structure (pointer to
+          SDMMC_DataInitTypeDef) according to the selected data type to be received.
+          The parameters that should be filled are:
+           (++) Data TimeOut
+           (++) Data Length
+           (++) Data Block size
+           (++) Data Transfer direction: should be from card (To SDMMC)
+           (++) Data Transfer mode
+           (++) DPSM Status (Enable or Disable)
+
+      (#) Configure the SDMMC resources to receive the data from the card
+          according to selected transfer mode (Refer to Step 8, 9 and 10).
+
+      (#) Send the selected Read command (refer to step 11).
+
+      (#) Use the SDMMC flags/interrupts to check the transfer status.
+
+    *** Write Operations ***
+    ========================
+    [..]
+     (#) First, user has to fill the data structure (pointer to
+         SDMMC_DataInitTypeDef) according to the selected data type to be received.
+         The parameters that should be filled are:
+          (++) Data TimeOut
+          (++) Data Length
+          (++) Data Block size
+          (++) Data Transfer direction:  should be to card (To CARD)
+          (++) Data Transfer mode
+          (++) DPSM Status (Enable or Disable)
+
+     (#) Configure the SDMMC resources to send the data to the card according to
+         selected transfer mode.
+
+     (#) Send the selected Write command.
+
+     (#) Use the SDMMC flags/interrupts to check the transfer status.
+
+    *** Command management operations ***
+    =====================================
+    [..]
+     (#) The commands used for Read/Write/Erase operations are managed in
+         separate functions.
+         Each function allows to send the needed command with the related argument,
+         then check the response.
+         By the same approach, you could implement a command and check the response.
+
+  @endverbatim
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup SDMMC_LL SDMMC Low Layer
+  * @brief Low layer module for SD
+  * @{
+  */
+
+#if defined (HAL_SD_MODULE_ENABLED) || defined (HAL_MMC_MODULE_ENABLED)
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+static uint32_t SDMMC_GetCmdError(SDMMC_TypeDef *SDMMCx);
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup SDMMC_LL_Exported_Functions SDMMC Low Layer Exported Functions
+  * @{
+  */
+
+/** @defgroup HAL_SDMMC_LL_Group1 Initialization de-initialization functions
+  *  @brief    Initialization and Configuration functions
+  *
+@verbatim
+ ===============================================================================
+              ##### Initialization/de-initialization functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the SDMMC according to the specified
+  *         parameters in the SDMMC_InitTypeDef and create the associated handle.
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @param  Init: SDMMC initialization structure
+  * @retval HAL status
+  */
+HAL_StatusTypeDef SDMMC_Init(SDMMC_TypeDef *SDMMCx, SDMMC_InitTypeDef Init)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_SDMMC_ALL_INSTANCE(SDMMCx));
+  assert_param(IS_SDMMC_CLOCK_EDGE(Init.ClockEdge));
+  assert_param(IS_SDMMC_CLOCK_POWER_SAVE(Init.ClockPowerSave));
+  assert_param(IS_SDMMC_BUS_WIDE(Init.BusWide));
+  assert_param(IS_SDMMC_HARDWARE_FLOW_CONTROL(Init.HardwareFlowControl));
+  assert_param(IS_SDMMC_CLKDIV(Init.ClockDiv));
+
+  /* Set SDMMC configuration parameters */
+  tmpreg |= (Init.ClockEdge           | \
+             Init.ClockPowerSave      | \
+             Init.BusWide             | \
+             Init.HardwareFlowControl | \
+             Init.ClockDiv
+            );
+
+  /* Write to SDMMC CLKCR */
+  MODIFY_REG(SDMMCx->CLKCR, CLKCR_CLEAR_MASK, tmpreg);
+
+  return HAL_OK;
+}
+
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_SDMMC_LL_Group2 IO operation functions
+  *  @brief   Data transfers functions
+  *
+@verbatim
+ ===============================================================================
+                      ##### I/O operation functions #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to manage the SDMMC data
+    transfers.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Read data (word) from Rx FIFO in blocking mode (polling)
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @retval HAL status
+  */
+uint32_t SDMMC_ReadFIFO(SDMMC_TypeDef *SDMMCx)
+{
+  /* Read data from Rx FIFO */
+  return (SDMMCx->FIFO);
+}
+
+/**
+  * @brief  Write data (word) to Tx FIFO in blocking mode (polling)
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @param  pWriteData: pointer to data to write
+  * @retval HAL status
+  */
+HAL_StatusTypeDef SDMMC_WriteFIFO(SDMMC_TypeDef *SDMMCx, uint32_t *pWriteData)
+{
+  /* Write data to FIFO */
+  SDMMCx->FIFO = *pWriteData;
+
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_SDMMC_LL_Group3 Peripheral Control functions
+  *  @brief   management functions
+  *
+@verbatim
+ ===============================================================================
+                      ##### Peripheral Control functions #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to control the SDMMC data
+    transfers.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Set SDMMC Power state to ON.
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @retval HAL status
+  */
+HAL_StatusTypeDef SDMMC_PowerState_ON(SDMMC_TypeDef *SDMMCx)
+{
+  /* Set power state to ON */
+  SDMMCx->POWER |= SDMMC_POWER_PWRCTRL;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Set SDMMC Power state to Power-Cycle.
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @retval HAL status
+  */
+HAL_StatusTypeDef SDMMC_PowerState_Cycle(SDMMC_TypeDef *SDMMCx)
+{
+  /* Set power state to Power Cycle*/
+  SDMMCx->POWER |= SDMMC_POWER_PWRCTRL_1;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Set SDMMC Power state to OFF.
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @retval HAL status
+  */
+HAL_StatusTypeDef SDMMC_PowerState_OFF(SDMMC_TypeDef *SDMMCx)
+{
+  /* Set power state to OFF */
+  SDMMCx->POWER &= ~(SDMMC_POWER_PWRCTRL);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Get SDMMC Power state.
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @retval Power status of the controller. The returned value can be one of the
+  *         following values:
+  *            - 0x00: Power OFF
+  *            - 0x02: Power UP
+  *            - 0x03: Power ON
+  */
+uint32_t SDMMC_GetPowerState(SDMMC_TypeDef *SDMMCx)
+{
+  return (SDMMCx->POWER & SDMMC_POWER_PWRCTRL);
+}
+
+/**
+  * @brief  Configure the SDMMC command path according to the specified parameters in
+  *         SDMMC_CmdInitTypeDef structure and send the command
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @param  Command: pointer to a SDMMC_CmdInitTypeDef structure that contains
+  *         the configuration information for the SDMMC command
+  * @retval HAL status
+  */
+HAL_StatusTypeDef SDMMC_SendCommand(SDMMC_TypeDef *SDMMCx, SDMMC_CmdInitTypeDef *Command)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_SDMMC_CMD_INDEX(Command->CmdIndex));
+  assert_param(IS_SDMMC_RESPONSE(Command->Response));
+  assert_param(IS_SDMMC_WAIT(Command->WaitForInterrupt));
+  assert_param(IS_SDMMC_CPSM(Command->CPSM));
+
+  /* Set the SDMMC Argument value */
+  SDMMCx->ARG = Command->Argument;
+
+  /* Set SDMMC command parameters */
+  tmpreg |= (uint32_t)(Command->CmdIndex         | \
+                       Command->Response         | \
+                       Command->WaitForInterrupt | \
+                       Command->CPSM);
+
+  /* Write to SDMMC CMD register */
+  MODIFY_REG(SDMMCx->CMD, CMD_CLEAR_MASK, tmpreg);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Return the command index of last command for which response received
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @retval Command index of the last command response received
+  */
+uint8_t SDMMC_GetCommandResponse(SDMMC_TypeDef *SDMMCx)
+{
+  return (uint8_t)(SDMMCx->RESPCMD);
+}
+
+
+/**
+  * @brief  Return the response received from the card for the last command
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @param  Response: Specifies the SDMMC response register.
+  *          This parameter can be one of the following values:
+  *            @arg SDMMC_RESP1: Response Register 1
+  *            @arg SDMMC_RESP2: Response Register 2
+  *            @arg SDMMC_RESP3: Response Register 3
+  *            @arg SDMMC_RESP4: Response Register 4
+  * @retval The Corresponding response register value
+  */
+uint32_t SDMMC_GetResponse(SDMMC_TypeDef *SDMMCx, uint32_t Response)
+{
+  uint32_t tmp;
+
+  /* Check the parameters */
+  assert_param(IS_SDMMC_RESP(Response));
+
+  /* Get the response */
+  tmp = (uint32_t)(&(SDMMCx->RESP1)) + Response;
+
+  return (*(__IO uint32_t *) tmp);
+}
+
+/**
+  * @brief  Configure the SDMMC data path according to the specified
+  *         parameters in the SDMMC_DataInitTypeDef.
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @param  Data : pointer to a SDMMC_DataInitTypeDef structure
+  *         that contains the configuration information for the SDMMC data.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef SDMMC_ConfigData(SDMMC_TypeDef *SDMMCx, SDMMC_DataInitTypeDef *Data)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_SDMMC_DATA_LENGTH(Data->DataLength));
+  assert_param(IS_SDMMC_BLOCK_SIZE(Data->DataBlockSize));
+  assert_param(IS_SDMMC_TRANSFER_DIR(Data->TransferDir));
+  assert_param(IS_SDMMC_TRANSFER_MODE(Data->TransferMode));
+  assert_param(IS_SDMMC_DPSM(Data->DPSM));
+
+  /* Set the SDMMC Data TimeOut value */
+  SDMMCx->DTIMER = Data->DataTimeOut;
+
+  /* Set the SDMMC DataLength value */
+  SDMMCx->DLEN = Data->DataLength;
+
+  /* Set the SDMMC data configuration parameters */
+  tmpreg |= (uint32_t)(Data->DataBlockSize | \
+                       Data->TransferDir   | \
+                       Data->TransferMode  | \
+                       Data->DPSM);
+
+  /* Write to SDMMC DCTRL */
+  MODIFY_REG(SDMMCx->DCTRL, DCTRL_CLEAR_MASK, tmpreg);
+
+  return HAL_OK;
+
+}
+
+/**
+  * @brief  Returns number of remaining data bytes to be transferred.
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @retval Number of remaining data bytes to be transferred
+  */
+uint32_t SDMMC_GetDataCounter(SDMMC_TypeDef *SDMMCx)
+{
+  return (SDMMCx->DCOUNT);
+}
+
+/**
+  * @brief  Get the FIFO data
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @retval Data received
+  */
+uint32_t SDMMC_GetFIFOCount(SDMMC_TypeDef *SDMMCx)
+{
+  return (SDMMCx->FIFO);
+}
+
+/**
+  * @brief  Sets one of the two options of inserting read wait interval.
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @param  SDMMC_ReadWaitMode: SDMMC Read Wait operation mode.
+  *          This parameter can be:
+  *            @arg SDMMC_READ_WAIT_MODE_CLK: Read Wait control by stopping SDMMCCLK
+  *            @arg SDMMC_READ_WAIT_MODE_DATA2: Read Wait control using SDMMC_DATA2
+  * @retval None
+  */
+HAL_StatusTypeDef SDMMC_SetSDMMCReadWaitMode(SDMMC_TypeDef *SDMMCx, uint32_t SDMMC_ReadWaitMode)
+{
+  /* Check the parameters */
+  assert_param(IS_SDMMC_READWAIT_MODE(SDMMC_ReadWaitMode));
+
+  /* Set SDMMC read wait mode */
+  MODIFY_REG(SDMMCx->DCTRL, SDMMC_DCTRL_RWMOD, SDMMC_ReadWaitMode);
+
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+
+/** @defgroup HAL_SDMMC_LL_Group4 Command management functions
+  *  @brief   Data transfers functions
+  *
+@verbatim
+ ===============================================================================
+                   ##### Commands management functions #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to manage the needed commands.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Send the Data Block Length command and check the response
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdBlockLength(SDMMC_TypeDef *SDMMCx, uint32_t BlockSize)
+{
+  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+
+  /* Set Block Size for Card */
+  sdmmc_cmdinit.Argument         = (uint32_t)BlockSize;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SET_BLOCKLEN;
+  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+  (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SET_BLOCKLEN, SDMMC_CMDTIMEOUT);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the Read Single Block command and check the response
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdReadSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd)
+{
+  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+
+  /* Set Block Size for Card */
+  sdmmc_cmdinit.Argument         = (uint32_t)ReadAdd;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_READ_SINGLE_BLOCK;
+  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+  (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_READ_SINGLE_BLOCK, SDMMC_CMDTIMEOUT);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the Read Multi Block command and check the response
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdReadMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd)
+{
+  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+
+  /* Set Block Size for Card */
+  sdmmc_cmdinit.Argument         = (uint32_t)ReadAdd;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_READ_MULT_BLOCK;
+  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+  (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_READ_MULT_BLOCK, SDMMC_CMDTIMEOUT);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the Write Single Block command and check the response
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdWriteSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd)
+{
+  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+
+  /* Set Block Size for Card */
+  sdmmc_cmdinit.Argument         = (uint32_t)WriteAdd;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_WRITE_SINGLE_BLOCK;
+  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+  (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_WRITE_SINGLE_BLOCK, SDMMC_CMDTIMEOUT);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the Write Multi Block command and check the response
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdWriteMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd)
+{
+  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+
+  /* Set Block Size for Card */
+  sdmmc_cmdinit.Argument         = (uint32_t)WriteAdd;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_WRITE_MULT_BLOCK;
+  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+  (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_WRITE_MULT_BLOCK, SDMMC_CMDTIMEOUT);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the Start Address Erase command for SD and check the response
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdSDEraseStartAdd(SDMMC_TypeDef *SDMMCx, uint32_t StartAdd)
+{
+  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+
+  /* Set Block Size for Card */
+  sdmmc_cmdinit.Argument         = (uint32_t)StartAdd;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SD_ERASE_GRP_START;
+  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+  (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SD_ERASE_GRP_START, SDMMC_CMDTIMEOUT);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the End Address Erase command for SD and check the response
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdSDEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd)
+{
+  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+
+  /* Set Block Size for Card */
+  sdmmc_cmdinit.Argument         = (uint32_t)EndAdd;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SD_ERASE_GRP_END;
+  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+  (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SD_ERASE_GRP_END, SDMMC_CMDTIMEOUT);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the Start Address Erase command and check the response
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdEraseStartAdd(SDMMC_TypeDef *SDMMCx, uint32_t StartAdd)
+{
+  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+
+  /* Set Block Size for Card */
+  sdmmc_cmdinit.Argument         = (uint32_t)StartAdd;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_ERASE_GRP_START;
+  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+  (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_ERASE_GRP_START, SDMMC_CMDTIMEOUT);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the End Address Erase command and check the response
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd)
+{
+  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+
+  /* Set Block Size for Card */
+  sdmmc_cmdinit.Argument         = (uint32_t)EndAdd;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_ERASE_GRP_END;
+  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+  (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_ERASE_GRP_END, SDMMC_CMDTIMEOUT);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the Erase command and check the response
+  * @param  SDMMCx Pointer to SDMMC register base
+  * @param  EraseType Type of erase to be performed
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdErase(SDMMC_TypeDef *SDMMCx, uint32_t EraseType)
+{
+  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+
+  /* Set Block Size for Card */
+  sdmmc_cmdinit.Argument         = EraseType;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_ERASE;
+  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+  (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_ERASE, SDMMC_MAXERASETIMEOUT);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the Stop Transfer command and check the response.
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdStopTransfer(SDMMC_TypeDef *SDMMCx)
+{
+  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+
+  /* Send CMD12 STOP_TRANSMISSION  */
+  sdmmc_cmdinit.Argument         = 0U;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_STOP_TRANSMISSION;
+  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+
+  __SDMMC_CMDSTOP_ENABLE(SDMMCx);
+  __SDMMC_CMDTRANS_DISABLE(SDMMCx);
+
+  (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_STOP_TRANSMISSION, SDMMC_STOPTRANSFERTIMEOUT);
+
+  __SDMMC_CMDSTOP_DISABLE(SDMMCx);
+
+  /* Ignore Address Out Of Range Error, Not relevant at end of memory */
+  if (errorstate == SDMMC_ERROR_ADDR_OUT_OF_RANGE)
+  {
+    errorstate = SDMMC_ERROR_NONE;
+  }
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the Select Deselect command and check the response.
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @param  addr: Address of the card to be selected
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdSelDesel(SDMMC_TypeDef *SDMMCx, uint32_t Addr)
+{
+  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+
+  /* Send CMD7 SDMMC_SEL_DESEL_CARD */
+  sdmmc_cmdinit.Argument         = (uint32_t)Addr;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SEL_DESEL_CARD;
+  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+  (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SEL_DESEL_CARD, SDMMC_CMDTIMEOUT);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the Go Idle State command and check the response.
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdGoIdleState(SDMMC_TypeDef *SDMMCx)
+{
+  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+
+  sdmmc_cmdinit.Argument         = 0U;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_GO_IDLE_STATE;
+  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_NO;
+  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+  (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdError(SDMMCx);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the Operating Condition command and check the response.
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdOperCond(SDMMC_TypeDef *SDMMCx)
+{
+  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+
+  /* Send CMD8 to verify SD card interface operating condition */
+  /* Argument: - [31:12]: Reserved (shall be set to '0')
+  - [11:8]: Supply Voltage (VHS) 0x1 (Range: 2.7-3.6 V)
+  - [7:0]: Check Pattern (recommended 0xAA) */
+  /* CMD Response: R7 */
+  sdmmc_cmdinit.Argument         = SDMMC_CHECK_PATTERN;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_HS_SEND_EXT_CSD;
+  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+  (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp7(SDMMCx);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the Application command to verify that that the next command
+  *         is an application specific com-mand rather than a standard command
+  *         and check the response.
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @param  Argument: Command Argument
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdAppCommand(SDMMC_TypeDef *SDMMCx, uint32_t Argument)
+{
+  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+
+  sdmmc_cmdinit.Argument         = (uint32_t)Argument;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_APP_CMD;
+  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+  (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+
+  /* Check for error conditions */
+  /* If there is a HAL_ERROR, it is a MMC card, else
+  it is a SD card: SD card 2.0 (voltage range mismatch)
+     or SD card 1.x */
+  errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_APP_CMD, SDMMC_CMDTIMEOUT);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the command asking the accessed card to send its operating
+  *         condition register (OCR)
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @param  Argument: Command Argument
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdAppOperCommand(SDMMC_TypeDef *SDMMCx, uint32_t Argument)
+{
+  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+
+  sdmmc_cmdinit.Argument         = Argument;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SD_APP_OP_COND;
+  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+  (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp3(SDMMCx);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the Bus Width command and check the response.
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @param  BusWidth: BusWidth
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdBusWidth(SDMMC_TypeDef *SDMMCx, uint32_t BusWidth)
+{
+  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+
+  sdmmc_cmdinit.Argument         = (uint32_t)BusWidth;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_APP_SD_SET_BUSWIDTH;
+  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+  (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_APP_SD_SET_BUSWIDTH, SDMMC_CMDTIMEOUT);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the Send SCR command and check the response.
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdSendSCR(SDMMC_TypeDef *SDMMCx)
+{
+  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+
+  /* Send CMD51 SD_APP_SEND_SCR */
+  sdmmc_cmdinit.Argument         = 0U;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SD_APP_SEND_SCR;
+  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+  (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SD_APP_SEND_SCR, SDMMC_CMDTIMEOUT);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the Send CID command and check the response.
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdSendCID(SDMMC_TypeDef *SDMMCx)
+{
+  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+
+  /* Send CMD2 ALL_SEND_CID */
+  sdmmc_cmdinit.Argument         = 0U;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_ALL_SEND_CID;
+  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_LONG;
+  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+  (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp2(SDMMCx);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the Send CSD command and check the response.
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @param  Argument: Command Argument
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdSendCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument)
+{
+  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+
+  /* Send CMD9 SEND_CSD */
+  sdmmc_cmdinit.Argument         = Argument;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SEND_CSD;
+  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_LONG;
+  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+  (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp2(SDMMCx);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the Send CSD command and check the response.
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @param  pRCA: Card RCA
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdSetRelAdd(SDMMC_TypeDef *SDMMCx, uint16_t *pRCA)
+{
+  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+
+  /* Send CMD3 SD_CMD_SET_REL_ADDR */
+  sdmmc_cmdinit.Argument         = 0U;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SET_REL_ADDR;
+  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+  (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp6(SDMMCx, SDMMC_CMD_SET_REL_ADDR, pRCA);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the Set Relative Address command to MMC card (not SD card).
+  * @param  SDMMCx Pointer to SDMMC register base
+  * @param  RCA Card RCA
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdSetRelAddMmc(SDMMC_TypeDef *SDMMCx, uint16_t RCA)
+{
+  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+
+  /* Send CMD3 SD_CMD_SET_REL_ADDR */
+  sdmmc_cmdinit.Argument         = ((uint32_t)RCA << 16U);
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SET_REL_ADDR;
+  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+  (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SET_REL_ADDR, SDMMC_CMDTIMEOUT);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the Sleep command to MMC card (not SD card).
+  * @param  SDMMCx Pointer to SDMMC register base
+  * @param  Argument Argument of the command (RCA and Sleep/Awake)
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdSleepMmc(SDMMC_TypeDef *SDMMCx, uint32_t Argument)
+{
+  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+
+  /* Send CMD5 SDMMC_CMD_MMC_SLEEP_AWAKE */
+  sdmmc_cmdinit.Argument         = Argument;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_MMC_SLEEP_AWAKE;
+  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+  (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_MMC_SLEEP_AWAKE, SDMMC_CMDTIMEOUT);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the Status command and check the response.
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @param  Argument: Command Argument
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdSendStatus(SDMMC_TypeDef *SDMMCx, uint32_t Argument)
+{
+  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+
+  sdmmc_cmdinit.Argument         = Argument;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SEND_STATUS;
+  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+  (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SEND_STATUS, SDMMC_CMDTIMEOUT);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the Status register command and check the response.
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdStatusRegister(SDMMC_TypeDef *SDMMCx)
+{
+  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+
+  sdmmc_cmdinit.Argument         = 0U;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SD_APP_STATUS;
+  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+  (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SD_APP_STATUS, SDMMC_CMDTIMEOUT);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Sends host capacity support information and activates the card's
+  *         initialization process. Send SDMMC_CMD_SEND_OP_COND command
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @parame Argument: Argument used for the command
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdOpCondition(SDMMC_TypeDef *SDMMCx, uint32_t Argument)
+{
+  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+
+  sdmmc_cmdinit.Argument         = Argument;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SEND_OP_COND;
+  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+  (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp3(SDMMCx);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Checks switchable function and switch card function. SDMMC_CMD_HS_SWITCH command
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @parame Argument: Argument used for the command
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdSwitch(SDMMC_TypeDef *SDMMCx, uint32_t Argument)
+{
+  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+
+  /* Send CMD6 to activate SDR50 Mode and Power Limit 1.44W */
+  /* CMD Response: R1 */
+  sdmmc_cmdinit.Argument         = Argument; /* SDMMC_SDR25_SWITCH_PATTERN*/
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_HS_SWITCH;
+  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+  (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_HS_SWITCH, SDMMC_CMDTIMEOUT);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the command asking the accessed card to send its operating
+  *         condition register (OCR)
+  * @param  None
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdVoltageSwitch(SDMMC_TypeDef *SDMMCx)
+{
+  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+
+  sdmmc_cmdinit.Argument         = 0x00000000;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_VOLTAGE_SWITCH;
+  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+  (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_VOLTAGE_SWITCH, SDMMC_CMDTIMEOUT);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the Send EXT_CSD command and check the response.
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @param  Argument: Command Argument
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdSendEXTCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument)
+{
+  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+
+  /* Send CMD9 SEND_CSD */
+  sdmmc_cmdinit.Argument         = Argument;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_HS_SEND_EXT_CSD;
+  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+  (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_HS_SEND_EXT_CSD, SDMMC_CMDTIMEOUT);
+
+  return errorstate;
+}
+
+/**
+  * @}
+  */
+
+
+/** @defgroup HAL_SDMMC_LL_Group5 Responses management functions
+  *  @brief   Responses functions
+  *
+@verbatim
+ ===============================================================================
+                   ##### Responses management functions #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to manage the needed responses.
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Checks for error conditions for R1 response.
+  * @param  hsd: SD handle
+  * @param  SD_CMD: The sent command index
+  * @retval SD Card error state
+  */
+uint32_t SDMMC_GetCmdResp1(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint32_t Timeout)
+{
+  uint32_t response_r1;
+  uint32_t sta_reg;
+
+  /* 8 is the number of required instructions cycles for the below loop statement.
+  The Timeout is expressed in ms */
+  uint32_t count = Timeout * (SystemCoreClock / 8U / 1000U);
+
+  do
+  {
+    if (count-- == 0U)
+    {
+      return SDMMC_ERROR_TIMEOUT;
+    }
+    sta_reg = SDMMCx->STA;
+  } while (((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT |
+                        SDMMC_FLAG_BUSYD0END)) == 0U) || ((sta_reg & SDMMC_FLAG_CMDACT) != 0U));
+
+  if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT))
+  {
+    __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT);
+
+    return SDMMC_ERROR_CMD_RSP_TIMEOUT;
+  }
+  else if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL))
+  {
+    __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL);
+
+    return SDMMC_ERROR_CMD_CRC_FAIL;
+  }
+  else
+  {
+    /* Nothing to do */
+  }
+
+  /* Clear all the static flags */
+  __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS);
+
+  /* Check response received is of desired command */
+  if (SDMMC_GetCommandResponse(SDMMCx) != SD_CMD)
+  {
+    return SDMMC_ERROR_CMD_CRC_FAIL;
+  }
+
+  /* We have received response, retrieve it for analysis  */
+  response_r1 = SDMMC_GetResponse(SDMMCx, SDMMC_RESP1);
+
+  if ((response_r1 & SDMMC_OCR_ERRORBITS) == SDMMC_ALLZERO)
+  {
+    return SDMMC_ERROR_NONE;
+  }
+  else if ((response_r1 & SDMMC_OCR_ADDR_OUT_OF_RANGE) == SDMMC_OCR_ADDR_OUT_OF_RANGE)
+  {
+    return SDMMC_ERROR_ADDR_OUT_OF_RANGE;
+  }
+  else if ((response_r1 & SDMMC_OCR_ADDR_MISALIGNED) == SDMMC_OCR_ADDR_MISALIGNED)
+  {
+    return SDMMC_ERROR_ADDR_MISALIGNED;
+  }
+  else if ((response_r1 & SDMMC_OCR_BLOCK_LEN_ERR) == SDMMC_OCR_BLOCK_LEN_ERR)
+  {
+    return SDMMC_ERROR_BLOCK_LEN_ERR;
+  }
+  else if ((response_r1 & SDMMC_OCR_ERASE_SEQ_ERR) == SDMMC_OCR_ERASE_SEQ_ERR)
+  {
+    return SDMMC_ERROR_ERASE_SEQ_ERR;
+  }
+  else if ((response_r1 & SDMMC_OCR_BAD_ERASE_PARAM) == SDMMC_OCR_BAD_ERASE_PARAM)
+  {
+    return SDMMC_ERROR_BAD_ERASE_PARAM;
+  }
+  else if ((response_r1 & SDMMC_OCR_WRITE_PROT_VIOLATION) == SDMMC_OCR_WRITE_PROT_VIOLATION)
+  {
+    return SDMMC_ERROR_WRITE_PROT_VIOLATION;
+  }
+  else if ((response_r1 & SDMMC_OCR_LOCK_UNLOCK_FAILED) == SDMMC_OCR_LOCK_UNLOCK_FAILED)
+  {
+    return SDMMC_ERROR_LOCK_UNLOCK_FAILED;
+  }
+  else if ((response_r1 & SDMMC_OCR_COM_CRC_FAILED) == SDMMC_OCR_COM_CRC_FAILED)
+  {
+    return SDMMC_ERROR_COM_CRC_FAILED;
+  }
+  else if ((response_r1 & SDMMC_OCR_ILLEGAL_CMD) == SDMMC_OCR_ILLEGAL_CMD)
+  {
+    return SDMMC_ERROR_ILLEGAL_CMD;
+  }
+  else if ((response_r1 & SDMMC_OCR_CARD_ECC_FAILED) == SDMMC_OCR_CARD_ECC_FAILED)
+  {
+    return SDMMC_ERROR_CARD_ECC_FAILED;
+  }
+  else if ((response_r1 & SDMMC_OCR_CC_ERROR) == SDMMC_OCR_CC_ERROR)
+  {
+    return SDMMC_ERROR_CC_ERR;
+  }
+  else if ((response_r1 & SDMMC_OCR_STREAM_READ_UNDERRUN) == SDMMC_OCR_STREAM_READ_UNDERRUN)
+  {
+    return SDMMC_ERROR_STREAM_READ_UNDERRUN;
+  }
+  else if ((response_r1 & SDMMC_OCR_STREAM_WRITE_OVERRUN) == SDMMC_OCR_STREAM_WRITE_OVERRUN)
+  {
+    return SDMMC_ERROR_STREAM_WRITE_OVERRUN;
+  }
+  else if ((response_r1 & SDMMC_OCR_CID_CSD_OVERWRITE) == SDMMC_OCR_CID_CSD_OVERWRITE)
+  {
+    return SDMMC_ERROR_CID_CSD_OVERWRITE;
+  }
+  else if ((response_r1 & SDMMC_OCR_WP_ERASE_SKIP) == SDMMC_OCR_WP_ERASE_SKIP)
+  {
+    return SDMMC_ERROR_WP_ERASE_SKIP;
+  }
+  else if ((response_r1 & SDMMC_OCR_CARD_ECC_DISABLED) == SDMMC_OCR_CARD_ECC_DISABLED)
+  {
+    return SDMMC_ERROR_CARD_ECC_DISABLED;
+  }
+  else if ((response_r1 & SDMMC_OCR_ERASE_RESET) == SDMMC_OCR_ERASE_RESET)
+  {
+    return SDMMC_ERROR_ERASE_RESET;
+  }
+  else if ((response_r1 & SDMMC_OCR_AKE_SEQ_ERROR) == SDMMC_OCR_AKE_SEQ_ERROR)
+  {
+    return SDMMC_ERROR_AKE_SEQ_ERR;
+  }
+  else
+  {
+    return SDMMC_ERROR_GENERAL_UNKNOWN_ERR;
+  }
+}
+
+/**
+  * @brief  Checks for error conditions for R2 (CID or CSD) response.
+  * @param  hsd: SD handle
+  * @retval SD Card error state
+  */
+uint32_t SDMMC_GetCmdResp2(SDMMC_TypeDef *SDMMCx)
+{
+  uint32_t sta_reg;
+  /* 8 is the number of required instructions cycles for the below loop statement.
+  The SDMMC_CMDTIMEOUT is expressed in ms */
+  uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U / 1000U);
+
+  do
+  {
+    if (count-- == 0U)
+    {
+      return SDMMC_ERROR_TIMEOUT;
+    }
+    sta_reg = SDMMCx->STA;
+  } while (((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) ||
+           ((sta_reg & SDMMC_FLAG_CMDACT) != 0U));
+
+  if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT))
+  {
+    __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT);
+
+    return SDMMC_ERROR_CMD_RSP_TIMEOUT;
+  }
+  else if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL))
+  {
+    __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL);
+
+    return SDMMC_ERROR_CMD_CRC_FAIL;
+  }
+  else
+  {
+    /* No error flag set */
+    /* Clear all the static flags */
+    __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS);
+  }
+
+  return SDMMC_ERROR_NONE;
+}
+
+/**
+  * @brief  Checks for error conditions for R3 (OCR) response.
+  * @param  hsd: SD handle
+  * @retval SD Card error state
+  */
+uint32_t SDMMC_GetCmdResp3(SDMMC_TypeDef *SDMMCx)
+{
+  uint32_t sta_reg;
+  /* 8 is the number of required instructions cycles for the below loop statement.
+  The SDMMC_CMDTIMEOUT is expressed in ms */
+  uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U / 1000U);
+
+  do
+  {
+    if (count-- == 0U)
+    {
+      return SDMMC_ERROR_TIMEOUT;
+    }
+    sta_reg = SDMMCx->STA;
+  } while (((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) ||
+           ((sta_reg & SDMMC_FLAG_CMDACT) != 0U));
+
+  if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT))
+  {
+    __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT);
+
+    return SDMMC_ERROR_CMD_RSP_TIMEOUT;
+  }
+  else
+  {
+    /* Clear all the static flags */
+    __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS);
+  }
+
+  return SDMMC_ERROR_NONE;
+}
+
+/**
+  * @brief  Checks for error conditions for R6 (RCA) response.
+  * @param  hsd: SD handle
+  * @param  SD_CMD: The sent command index
+  * @param  pRCA: Pointer to the variable that will contain the SD card relative
+  *         address RCA
+  * @retval SD Card error state
+  */
+uint32_t SDMMC_GetCmdResp6(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint16_t *pRCA)
+{
+  uint32_t response_r1;
+  uint32_t sta_reg;
+
+  /* 8 is the number of required instructions cycles for the below loop statement.
+  The SDMMC_CMDTIMEOUT is expressed in ms */
+  uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U / 1000U);
+
+  do
+  {
+    if (count-- == 0U)
+    {
+      return SDMMC_ERROR_TIMEOUT;
+    }
+    sta_reg = SDMMCx->STA;
+  } while (((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) ||
+           ((sta_reg & SDMMC_FLAG_CMDACT) != 0U));
+
+  if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT))
+  {
+    __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT);
+
+    return SDMMC_ERROR_CMD_RSP_TIMEOUT;
+  }
+  else if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL))
+  {
+    __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL);
+
+    return SDMMC_ERROR_CMD_CRC_FAIL;
+  }
+  else
+  {
+    /* Nothing to do */
+  }
+
+  /* Check response received is of desired command */
+  if (SDMMC_GetCommandResponse(SDMMCx) != SD_CMD)
+  {
+    return SDMMC_ERROR_CMD_CRC_FAIL;
+  }
+
+  /* Clear all the static flags */
+  __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS);
+
+  /* We have received response, retrieve it.  */
+  response_r1 = SDMMC_GetResponse(SDMMCx, SDMMC_RESP1);
+
+  if ((response_r1 & (SDMMC_R6_GENERAL_UNKNOWN_ERROR | SDMMC_R6_ILLEGAL_CMD |
+                      SDMMC_R6_COM_CRC_FAILED)) == SDMMC_ALLZERO)
+  {
+    *pRCA = (uint16_t)(response_r1 >> 16);
+
+    return SDMMC_ERROR_NONE;
+  }
+  else if ((response_r1 & SDMMC_R6_ILLEGAL_CMD) == SDMMC_R6_ILLEGAL_CMD)
+  {
+    return SDMMC_ERROR_ILLEGAL_CMD;
+  }
+  else if ((response_r1 & SDMMC_R6_COM_CRC_FAILED) == SDMMC_R6_COM_CRC_FAILED)
+  {
+    return SDMMC_ERROR_COM_CRC_FAILED;
+  }
+  else
+  {
+    return SDMMC_ERROR_GENERAL_UNKNOWN_ERR;
+  }
+}
+
+/**
+  * @brief  Checks for error conditions for R7 response.
+  * @param  hsd: SD handle
+  * @retval SD Card error state
+  */
+uint32_t SDMMC_GetCmdResp7(SDMMC_TypeDef *SDMMCx)
+{
+  uint32_t sta_reg;
+  /* 8 is the number of required instructions cycles for the below loop statement.
+  The SDMMC_CMDTIMEOUT is expressed in ms */
+  uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U / 1000U);
+
+  do
+  {
+    if (count-- == 0U)
+    {
+      return SDMMC_ERROR_TIMEOUT;
+    }
+    sta_reg = SDMMCx->STA;
+  } while (((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) ||
+           ((sta_reg & SDMMC_FLAG_CMDACT) != 0U));
+
+  if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT))
+  {
+    /* Card is not SD V2.0 compliant */
+    __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT);
+
+    return SDMMC_ERROR_CMD_RSP_TIMEOUT;
+  }
+
+  else if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL))
+  {
+    /* Card is not SD V2.0 compliant */
+    __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL);
+
+    return SDMMC_ERROR_CMD_CRC_FAIL;
+  }
+  else
+  {
+    /* Nothing to do */
+  }
+
+  if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CMDREND))
+  {
+    /* Card is SD V2.0 compliant */
+    __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CMDREND);
+  }
+
+  return SDMMC_ERROR_NONE;
+
+}
+
+/**
+  * @}
+  */
+
+/* Private function ----------------------------------------------------------*/
+/** @addtogroup SD_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Checks for error conditions for CMD0.
+  * @param  hsd: SD handle
+  * @retval SD Card error state
+  */
+static uint32_t SDMMC_GetCmdError(SDMMC_TypeDef *SDMMCx)
+{
+  /* 8 is the number of required instructions cycles for the below loop statement.
+  The SDMMC_CMDTIMEOUT is expressed in ms */
+  uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U / 1000U);
+
+  do
+  {
+    if (count-- == 0U)
+    {
+      return SDMMC_ERROR_TIMEOUT;
+    }
+
+  } while (!__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CMDSENT));
+
+  /* Clear all the static flags */
+  __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS);
+
+  return SDMMC_ERROR_NONE;
+}
+
+/**
+  * @}
+  */
+
+#endif /* HAL_SD_MODULE_ENABLED || HAL_MMC_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
diff --git a/FATFS/App/fatfs.c b/FATFS/App/fatfs.c
new file mode 100644
index 0000000..535a29b
--- /dev/null
+++ b/FATFS/App/fatfs.c
@@ -0,0 +1,54 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file   fatfs.c
+  * @brief  Code for fatfs applications
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2024 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+#include "fatfs.h"
+
+uint8_t retSD;    /* Return value for SD */
+char SDPath[4];   /* SD logical drive path */
+FATFS SDFatFS;    /* File system object for SD logical drive */
+FIL SDFile;       /* File object for SD */
+
+/* USER CODE BEGIN Variables */
+
+/* USER CODE END Variables */
+
+void MX_FATFS_Init(void)
+{
+  /*## FatFS: Link the SD driver ###########################*/
+  retSD = FATFS_LinkDriver(&SD_Driver, SDPath);
+
+  /* USER CODE BEGIN Init */
+  /* additional user code for init */
+  /* USER CODE END Init */
+}
+
+/**
+  * @brief  Gets Time from RTC
+  * @param  None
+  * @retval Time in DWORD
+  */
+DWORD get_fattime(void)
+{
+  /* USER CODE BEGIN get_fattime */
+  return 0;
+  /* USER CODE END get_fattime */
+}
+
+/* USER CODE BEGIN Application */
+
+/* USER CODE END Application */
diff --git a/FATFS/App/fatfs.h b/FATFS/App/fatfs.h
new file mode 100644
index 0000000..5e4720c
--- /dev/null
+++ b/FATFS/App/fatfs.h
@@ -0,0 +1,47 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file   fatfs.h
+  * @brief  Header for fatfs applications
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2024 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __fatfs_H
+#define __fatfs_H
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "ff.h"
+#include "ff_gen_drv.h"
+#include "sd_diskio.h" /* defines SD_Driver as external */
+
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+extern uint8_t retSD; /* Return value for SD */
+extern char SDPath[4]; /* SD logical drive path */
+extern FATFS SDFatFS; /* File system object for SD logical drive */
+extern FIL SDFile; /* File object for SD */
+
+void MX_FATFS_Init(void);
+
+/* USER CODE BEGIN Prototypes */
+
+/* USER CODE END Prototypes */
+#ifdef __cplusplus
+}
+#endif
+#endif /*__fatfs_H */
diff --git a/FATFS/Target/bsp_driver_sd.c b/FATFS/Target/bsp_driver_sd.c
new file mode 100644
index 0000000..72f807d
--- /dev/null
+++ b/FATFS/Target/bsp_driver_sd.c
@@ -0,0 +1,307 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+ * @file    bsp_driver_sd.c for H7 (based on stm32h743i_eval_sd.c)
+ * @brief   This file includes a generic uSD card driver.
+ *          To be completed by the user according to the board used for the project.
+ * @note    Some functions generated as weak: they can be overridden by
+ *          - code in user files
+ *          - or BSP code from the FW pack files
+ *          if such files are added to the generated project (by the user).
+ ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2024 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+
+/* USER CODE BEGIN FirstSection */
+/* can be used to modify / undefine following code or add new definitions */
+/* USER CODE END FirstSection */
+/* Includes ------------------------------------------------------------------*/
+#include "bsp_driver_sd.h"
+
+/* Extern variables ---------------------------------------------------------*/
+
+extern SD_HandleTypeDef hsd1;
+
+/* USER CODE BEGIN BeforeInitSection */
+/* can be used to modify / undefine following code or add code */
+/* USER CODE END BeforeInitSection */
+/**
+  * @brief  Initializes the SD card device.
+  * @retval SD status
+  */
+__weak uint8_t BSP_SD_Init(void)
+{
+  uint8_t sd_state = MSD_OK;
+  /* Check if the SD card is plugged in the slot */
+  if (BSP_SD_IsDetected() != SD_PRESENT)
+  {
+    return MSD_ERROR_SD_NOT_PRESENT;
+  }
+  /* HAL SD initialization */
+  sd_state = HAL_SD_Init(&hsd1);
+  /* Configure SD Bus width (4 bits mode selected) */
+  if (sd_state == MSD_OK)
+  {
+    /* Enable wide operation */
+    if (HAL_SD_ConfigWideBusOperation(&hsd1, SDMMC_BUS_WIDE_4B) != HAL_OK)
+    {
+      sd_state = MSD_ERROR;
+    }
+  }
+
+  return sd_state;
+}
+/* USER CODE BEGIN AfterInitSection */
+/* can be used to modify previous code / undefine following code / add code */
+/* USER CODE END AfterInitSection */
+
+/* USER CODE BEGIN InterruptMode */
+/**
+  * @brief  Configures Interrupt mode for SD detection pin.
+  * @retval Returns 0
+  */
+__weak uint8_t BSP_SD_ITConfig(void)
+{
+  /* Code to be updated by the user or replaced by one from the FW pack (in a stmxxxx_sd.c file) */
+
+  return (uint8_t)0;
+}
+
+/* USER CODE END InterruptMode */
+
+/* USER CODE BEGIN BeforeReadBlocksSection */
+/* can be used to modify previous code / undefine following code / add code */
+/* USER CODE END BeforeReadBlocksSection */
+/**
+  * @brief  Reads block(s) from a specified address in an SD card, in polling mode.
+  * @param  pData: Pointer to the buffer that will contain the data to transmit
+  * @param  ReadAddr: Address from where data is to be read
+  * @param  NumOfBlocks: Number of SD blocks to read
+  * @param  Timeout: Timeout for read operation
+  * @retval SD status
+  */
+__weak uint8_t BSP_SD_ReadBlocks(uint32_t *pData, uint32_t ReadAddr, uint32_t NumOfBlocks, uint32_t Timeout)
+{
+  uint8_t sd_state = MSD_OK;
+
+  if (HAL_SD_ReadBlocks(&hsd1, (uint8_t *)pData, ReadAddr, NumOfBlocks, Timeout) != HAL_OK)
+  {
+    sd_state = MSD_ERROR;
+  }
+
+  return sd_state;
+}
+
+/* USER CODE BEGIN BeforeWriteBlocksSection */
+/* can be used to modify previous code / undefine following code / add code */
+/* USER CODE END BeforeWriteBlocksSection */
+/**
+  * @brief  Writes block(s) to a specified address in an SD card, in polling mode.
+  * @param  pData: Pointer to the buffer that will contain the data to transmit
+  * @param  WriteAddr: Address from where data is to be written
+  * @param  NumOfBlocks: Number of SD blocks to write
+  * @param  Timeout: Timeout for write operation
+  * @retval SD status
+  */
+__weak uint8_t BSP_SD_WriteBlocks(uint32_t *pData, uint32_t WriteAddr, uint32_t NumOfBlocks, uint32_t Timeout)
+{
+  uint8_t sd_state = MSD_OK;
+
+  if (HAL_SD_WriteBlocks(&hsd1, (uint8_t *)pData, WriteAddr, NumOfBlocks, Timeout) != HAL_OK)
+  {
+    sd_state = MSD_ERROR;
+  }
+
+  return sd_state;
+}
+
+/* USER CODE BEGIN BeforeReadDMABlocksSection */
+/* can be used to modify previous code / undefine following code / add code */
+/* USER CODE END BeforeReadDMABlocksSection */
+/**
+  * @brief  Reads block(s) from a specified address in an SD card, in DMA mode.
+  * @param  pData: Pointer to the buffer that will contain the data to transmit
+  * @param  ReadAddr: Address from where data is to be read
+  * @param  NumOfBlocks: Number of SD blocks to read
+  * @retval SD status
+  */
+__weak uint8_t BSP_SD_ReadBlocks_DMA(uint32_t *pData, uint32_t ReadAddr, uint32_t NumOfBlocks)
+{
+  uint8_t sd_state = MSD_OK;
+
+  /* Read block(s) in DMA transfer mode */
+  if (HAL_SD_ReadBlocks_DMA(&hsd1, (uint8_t *)pData, ReadAddr, NumOfBlocks) != HAL_OK)
+  {
+    sd_state = MSD_ERROR;
+  }
+
+  return sd_state;
+}
+
+/* USER CODE BEGIN BeforeWriteDMABlocksSection */
+/* can be used to modify previous code / undefine following code / add code */
+/* USER CODE END BeforeWriteDMABlocksSection */
+/**
+  * @brief  Writes block(s) to a specified address in an SD card, in DMA mode.
+  * @param  pData: Pointer to the buffer that will contain the data to transmit
+  * @param  WriteAddr: Address from where data is to be written
+  * @param  NumOfBlocks: Number of SD blocks to write
+  * @retval SD status
+  */
+__weak uint8_t BSP_SD_WriteBlocks_DMA(uint32_t *pData, uint32_t WriteAddr, uint32_t NumOfBlocks)
+{
+  uint8_t sd_state = MSD_OK;
+
+  /* Write block(s) in DMA transfer mode */
+  if (HAL_SD_WriteBlocks_DMA(&hsd1, (uint8_t *)pData, WriteAddr, NumOfBlocks) != HAL_OK)
+  {
+    sd_state = MSD_ERROR;
+  }
+
+  return sd_state;
+}
+
+/* USER CODE BEGIN BeforeEraseSection */
+/* can be used to modify previous code / undefine following code / add code */
+/* USER CODE END BeforeEraseSection */
+/**
+  * @brief  Erases the specified memory area of the given SD card.
+  * @param  StartAddr: Start byte address
+  * @param  EndAddr: End byte address
+  * @retval SD status
+  */
+__weak uint8_t BSP_SD_Erase(uint32_t StartAddr, uint32_t EndAddr)
+{
+  uint8_t sd_state = MSD_OK;
+
+  if (HAL_SD_Erase(&hsd1, StartAddr, EndAddr) != HAL_OK)
+  {
+    sd_state = MSD_ERROR;
+  }
+
+  return sd_state;
+}
+
+/* USER CODE BEGIN BeforeGetCardStateSection */
+/* can be used to modify previous code / undefine following code / add code */
+/* USER CODE END BeforeGetCardStateSection */
+
+/**
+  * @brief  Gets the current SD card data status.
+  * @param  None
+  * @retval Data transfer state.
+  *          This value can be one of the following values:
+  *            @arg  SD_TRANSFER_OK: No data transfer is acting
+  *            @arg  SD_TRANSFER_BUSY: Data transfer is acting
+  */
+__weak uint8_t BSP_SD_GetCardState(void)
+{
+  return ((HAL_SD_GetCardState(&hsd1) == HAL_SD_CARD_TRANSFER ) ? SD_TRANSFER_OK : SD_TRANSFER_BUSY);
+}
+
+/**
+  * @brief  Get SD information about specific SD card.
+  * @param  CardInfo: Pointer to HAL_SD_CardInfoTypedef structure
+  * @retval None
+  */
+__weak void BSP_SD_GetCardInfo(HAL_SD_CardInfoTypeDef *CardInfo)
+{
+  /* Get SD card Information */
+  HAL_SD_GetCardInfo(&hsd1, CardInfo);
+}
+
+/* USER CODE BEGIN BeforeCallBacksSection */
+/* can be used to modify previous code / undefine following code / add code */
+/* USER CODE END BeforeCallBacksSection */
+/**
+  * @brief SD Abort callbacks
+  * @param hsd: SD handle
+  * @retval None
+  */
+void HAL_SD_AbortCallback(SD_HandleTypeDef *hsd)
+{
+  BSP_SD_AbortCallback();
+}
+
+/**
+  * @brief Tx Transfer completed callback
+  * @param hsd: SD handle
+  * @retval None
+  */
+void HAL_SD_TxCpltCallback(SD_HandleTypeDef *hsd)
+{
+  BSP_SD_WriteCpltCallback();
+}
+
+/**
+  * @brief Rx Transfer completed callback
+  * @param hsd: SD handle
+  * @retval None
+  */
+void HAL_SD_RxCpltCallback(SD_HandleTypeDef *hsd)
+{
+  BSP_SD_ReadCpltCallback();
+}
+
+/* USER CODE BEGIN CallBacksSection_C */
+/**
+  * @brief BSP SD Abort callback
+  * @retval None
+  * @note empty (up to the user to fill it in or to remove it if useless)
+  */
+__weak void BSP_SD_AbortCallback(void)
+{
+
+}
+
+/**
+  * @brief BSP Tx Transfer completed callback
+  * @retval None
+  * @note empty (up to the user to fill it in or to remove it if useless)
+  */
+__weak void BSP_SD_WriteCpltCallback(void)
+{
+
+}
+
+/**
+  * @brief BSP Rx Transfer completed callback
+  * @retval None
+  * @note empty (up to the user to fill it in or to remove it if useless)
+  */
+__weak void BSP_SD_ReadCpltCallback(void)
+{
+
+}
+/* USER CODE END CallBacksSection_C */
+
+/**
+ * @brief  Detects if SD card is correctly plugged in the memory slot or not.
+ * @param  None
+ * @retval Returns if SD is detected or not
+ */
+__weak uint8_t BSP_SD_IsDetected(void)
+{
+  __IO uint8_t status = SD_PRESENT;
+
+  if (BSP_PlatformIsDetected() == 0x0)
+  {
+    status = SD_NOT_PRESENT;
+  }
+
+  return status;
+}
+
+/* USER CODE BEGIN AdditionalCode */
+/* user code can be inserted here */
+/* USER CODE END AdditionalCode */
diff --git a/FATFS/Target/bsp_driver_sd.h b/FATFS/Target/bsp_driver_sd.h
new file mode 100644
index 0000000..6ef48ea
--- /dev/null
+++ b/FATFS/Target/bsp_driver_sd.h
@@ -0,0 +1,83 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+  * @file    bsp_driver_sd.h (based on stm32h743i_eval_sd.h)
+  * @brief   This file contains the common defines and functions prototypes for
+  *          the bsp_driver_sd.c driver.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2024 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32H7_SD_H
+#define __STM32H7_SD_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal.h"
+#include "fatfs_platform.h"
+
+/* Exported types --------------------------------------------------------*/
+/**
+  * @brief SD Card information structure
+  */
+#define BSP_SD_CardInfo HAL_SD_CardInfoTypeDef
+
+/* Exported constants --------------------------------------------------------*/
+/**
+  * @brief  SD status structure definition
+  */
+#define   MSD_OK                        ((uint8_t)0x00)
+#define   MSD_ERROR                     ((uint8_t)0x01)
+#define   MSD_ERROR_SD_NOT_PRESENT      ((uint8_t)0x02)
+
+/**
+  * @brief  SD transfer state definition
+  */
+#define   SD_TRANSFER_OK                ((uint8_t)0x00)
+#define   SD_TRANSFER_BUSY              ((uint8_t)0x01)
+
+#define SD_PRESENT               ((uint8_t)0x01)
+#define SD_NOT_PRESENT           ((uint8_t)0x00)
+#define SD_DATATIMEOUT           ((uint32_t)100000000)
+
+/* USER CODE BEGIN BSP_H_CODE */
+#define SD_DetectIRQHandler()             HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_8)
+
+/* Exported functions --------------------------------------------------------*/
+uint8_t BSP_SD_Init(void);
+uint8_t BSP_SD_ITConfig(void);
+uint8_t BSP_SD_ReadBlocks(uint32_t *pData, uint32_t ReadAddr, uint32_t NumOfBlocks, uint32_t Timeout);
+uint8_t BSP_SD_WriteBlocks(uint32_t *pData, uint32_t WriteAddr, uint32_t NumOfBlocks, uint32_t Timeout);
+uint8_t BSP_SD_ReadBlocks_DMA(uint32_t *pData, uint32_t ReadAddr, uint32_t NumOfBlocks);
+uint8_t BSP_SD_WriteBlocks_DMA(uint32_t *pData, uint32_t WriteAddr, uint32_t NumOfBlocks);
+uint8_t BSP_SD_Erase(uint32_t StartAddr, uint32_t EndAddr);
+uint8_t BSP_SD_GetCardState(void);
+void    BSP_SD_GetCardInfo(BSP_SD_CardInfo *CardInfo);
+uint8_t BSP_SD_IsDetected(void);
+
+/* These functions can be modified in case the current settings (e.g. DMA stream)
+   need to be changed for specific application needs */
+void    BSP_SD_AbortCallback(void);
+void    BSP_SD_WriteCpltCallback(void);
+void    BSP_SD_ReadCpltCallback(void);
+/* USER CODE END BSP_H_CODE */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32H7_SD_H */
diff --git a/FATFS/Target/fatfs_platform.c b/FATFS/Target/fatfs_platform.c
new file mode 100644
index 0000000..07e388d
--- /dev/null
+++ b/FATFS/Target/fatfs_platform.c
@@ -0,0 +1,32 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file           : fatfs_platform.c
+  * @brief          : fatfs_platform source file
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2024 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+*/
+/* USER CODE END Header */
+#include "fatfs_platform.h"
+
+uint8_t	BSP_PlatformIsDetected(void) {
+    uint8_t status = SD_PRESENT;
+    /* Check SD card detect pin */
+    if(HAL_GPIO_ReadPin(SD_DETECT_GPIO_PORT, SD_DETECT_PIN) != GPIO_PIN_RESET)
+    {
+        status = SD_NOT_PRESENT;
+    }
+    /* USER CODE BEGIN 1 */
+    /* user code can be inserted here */
+    /* USER CODE END 1 */
+    return status;
+}
diff --git a/FATFS/Target/fatfs_platform.h b/FATFS/Target/fatfs_platform.h
new file mode 100644
index 0000000..c44518f
--- /dev/null
+++ b/FATFS/Target/fatfs_platform.h
@@ -0,0 +1,27 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file           : fatfs_platform.h
+  * @brief          : fatfs_platform header file
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2024 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+*/
+/* USER CODE END Header */
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal.h"
+/* Defines ------------------------------------------------------------------*/
+#define SD_PRESENT               ((uint8_t)0x01)  /* also in bsp_driver_sd.h */
+#define SD_NOT_PRESENT           ((uint8_t)0x00)  /* also in bsp_driver_sd.h */
+#define SD_DETECT_PIN         GPIO_PIN_15
+#define SD_DETECT_GPIO_PORT   GPIOB
+/* Prototypes ---------------------------------------------------------------*/
+uint8_t	BSP_PlatformIsDetected(void);
diff --git a/FATFS/Target/ffconf.h b/FATFS/Target/ffconf.h
new file mode 100644
index 0000000..6f28d42
--- /dev/null
+++ b/FATFS/Target/ffconf.h
@@ -0,0 +1,270 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  *  FatFs - Generic FAT file system module  R0.12c (C)ChaN, 2017
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2024 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+#ifndef _FFCONF
+#define _FFCONF 68300	/* Revision ID */
+
+/*-----------------------------------------------------------------------------/
+/ Additional user header to be used
+/-----------------------------------------------------------------------------*/
+#include "main.h"
+#include "stm32h7xx_hal.h"
+#include "bsp_driver_sd.h"
+#include "cmsis_os.h" /* _FS_REENTRANT set to 1 and CMSIS API chosen */
+
+/*-----------------------------------------------------------------------------/
+/ Function Configurations
+/-----------------------------------------------------------------------------*/
+
+#define _FS_READONLY         0      /* 0:Read/Write or 1:Read only */
+/* This option switches read-only configuration. (0:Read/Write or 1:Read-only)
+/  Read-only configuration removes writing API functions, f_write(), f_sync(),
+/  f_unlink(), f_mkdir(), f_chmod(), f_rename(), f_truncate(), f_getfree()
+/  and optional writing functions as well. */
+
+#define _FS_MINIMIZE         0      /* 0 to 3 */
+/* This option defines minimization level to remove some basic API functions.
+/
+/   0: All basic functions are enabled.
+/   1: f_stat(), f_getfree(), f_unlink(), f_mkdir(), f_truncate() and f_rename()
+/      are removed.
+/   2: f_opendir(), f_readdir() and f_closedir() are removed in addition to 1.
+/   3: f_lseek() function is removed in addition to 2. */
+
+#define _USE_STRFUNC         2      /* 0:Disable or 1-2:Enable */
+/* This option switches string functions, f_gets(), f_putc(), f_puts() and
+/  f_printf().
+/
+/  0: Disable string functions.
+/  1: Enable without LF-CRLF conversion.
+/  2: Enable with LF-CRLF conversion. */
+
+#define _USE_FIND            0
+/* This option switches filtered directory read functions, f_findfirst() and
+/  f_findnext(). (0:Disable, 1:Enable 2:Enable with matching altname[] too) */
+
+#define _USE_MKFS            1
+/* This option switches f_mkfs() function. (0:Disable or 1:Enable) */
+
+#define _USE_FASTSEEK        1
+/* This option switches fast seek feature. (0:Disable or 1:Enable) */
+
+#define	_USE_EXPAND		0
+/* This option switches f_expand function. (0:Disable or 1:Enable) */
+
+#define _USE_CHMOD		0
+/* This option switches attribute manipulation functions, f_chmod() and f_utime().
+/  (0:Disable or 1:Enable) Also _FS_READONLY needs to be 0 to enable this option. */
+
+#define _USE_LABEL           0
+/* This option switches volume label functions, f_getlabel() and f_setlabel().
+/  (0:Disable or 1:Enable) */
+
+#define _USE_FORWARD         0
+/* This option switches f_forward() function. (0:Disable or 1:Enable) */
+
+/*-----------------------------------------------------------------------------/
+/ Locale and Namespace Configurations
+/-----------------------------------------------------------------------------*/
+
+#define _CODE_PAGE         850
+/* This option specifies the OEM code page to be used on the target system.
+/  Incorrect setting of the code page can cause a file open failure.
+/
+/   1   - ASCII (No extended character. Non-LFN cfg. only)
+/   437 - U.S.
+/   720 - Arabic
+/   737 - Greek
+/   771 - KBL
+/   775 - Baltic
+/   850 - Latin 1
+/   852 - Latin 2
+/   855 - Cyrillic
+/   857 - Turkish
+/   860 - Portuguese
+/   861 - Icelandic
+/   862 - Hebrew
+/   863 - Canadian French
+/   864 - Arabic
+/   865 - Nordic
+/   866 - Russian
+/   869 - Greek 2
+/   932 - Japanese (DBCS)
+/   936 - Simplified Chinese (DBCS)
+/   949 - Korean (DBCS)
+/   950 - Traditional Chinese (DBCS)
+*/
+
+#define _USE_LFN     2    /* 0 to 3 */
+#define _MAX_LFN     255  /* Maximum LFN length to handle (12 to 255) */
+/* The _USE_LFN switches the support of long file name (LFN).
+/
+/   0: Disable support of LFN. _MAX_LFN has no effect.
+/   1: Enable LFN with static working buffer on the BSS. Always NOT thread-safe.
+/   2: Enable LFN with dynamic working buffer on the STACK.
+/   3: Enable LFN with dynamic working buffer on the HEAP.
+/
+/  To enable the LFN, Unicode handling functions (option/unicode.c) must be added
+/  to the project. The working buffer occupies (_MAX_LFN + 1) * 2 bytes and
+/  additional 608 bytes at exFAT enabled. _MAX_LFN can be in range from 12 to 255.
+/  It should be set 255 to support full featured LFN operations.
+/  When use stack for the working buffer, take care on stack overflow. When use heap
+/  memory for the working buffer, memory management functions, ff_memalloc() and
+/  ff_memfree(), must be added to the project. */
+
+#define _LFN_UNICODE    0 /* 0:ANSI/OEM or 1:Unicode */
+/* This option switches character encoding on the API. (0:ANSI/OEM or 1:UTF-16)
+/  To use Unicode string for the path name, enable LFN and set _LFN_UNICODE = 1.
+/  This option also affects behavior of string I/O functions. */
+
+#define _STRF_ENCODE    3
+/* When _LFN_UNICODE == 1, this option selects the character encoding ON THE FILE to
+/  be read/written via string I/O functions, f_gets(), f_putc(), f_puts and f_printf().
+/
+/  0: ANSI/OEM
+/  1: UTF-16LE
+/  2: UTF-16BE
+/  3: UTF-8
+/
+/  This option has no effect when _LFN_UNICODE == 0. */
+
+#define _FS_RPATH       0 /* 0 to 2 */
+/* This option configures support of relative path.
+/
+/   0: Disable relative path and remove related functions.
+/   1: Enable relative path. f_chdir() and f_chdrive() are available.
+/   2: f_getcwd() function is available in addition to 1.
+*/
+
+/*---------------------------------------------------------------------------/
+/ Drive/Volume Configurations
+/----------------------------------------------------------------------------*/
+
+#define _VOLUMES    1
+/* Number of volumes (logical drives) to be used. */
+
+/* USER CODE BEGIN Volumes */
+#define _STR_VOLUME_ID          0	/* 0:Use only 0-9 for drive ID, 1:Use strings for drive ID */
+#define _VOLUME_STRS            "RAM","NAND","CF","SD1","SD2","USB1","USB2","USB3"
+/* _STR_VOLUME_ID switches string support of volume ID.
+/  When _STR_VOLUME_ID is set to 1, also pre-defined strings can be used as drive
+/  number in the path name. _VOLUME_STRS defines the drive ID strings for each
+/  logical drives. Number of items must be equal to _VOLUMES. Valid characters for
+/  the drive ID strings are: A-Z and 0-9. */
+/* USER CODE END Volumes */
+
+#define _MULTI_PARTITION     0 /* 0:Single partition, 1:Multiple partition */
+/* This option switches support of multi-partition on a physical drive.
+/  By default (0), each logical drive number is bound to the same physical drive
+/  number and only an FAT volume found on the physical drive will be mounted.
+/  When multi-partition is enabled (1), each logical drive number can be bound to
+/  arbitrary physical drive and partition listed in the VolToPart[]. Also f_fdisk()
+/  function will be available. */
+#define _MIN_SS    512  /* 512, 1024, 2048 or 4096 */
+#define _MAX_SS    4096  /* 512, 1024, 2048 or 4096 */
+/* These options configure the range of sector size to be supported. (512, 1024,
+/  2048 or 4096) Always set both 512 for most systems, all type of memory cards and
+/  harddisk. But a larger value may be required for on-board flash memory and some
+/  type of optical media. When _MAX_SS is larger than _MIN_SS, FatFs is configured
+/  to variable sector size and GET_SECTOR_SIZE command must be implemented to the
+/  disk_ioctl() function. */
+
+#define	_USE_TRIM      0
+/* This option switches support of ATA-TRIM. (0:Disable or 1:Enable)
+/  To enable Trim function, also CTRL_TRIM command should be implemented to the
+/  disk_ioctl() function. */
+
+#define _FS_NOFSINFO    0 /* 0,1,2 or 3 */
+/* If you need to know correct free space on the FAT32 volume, set bit 0 of this
+/  option, and f_getfree() function at first time after volume mount will force
+/  a full FAT scan. Bit 1 controls the use of last allocated cluster number.
+/
+/  bit0=0: Use free cluster count in the FSINFO if available.
+/  bit0=1: Do not trust free cluster count in the FSINFO.
+/  bit1=0: Use last allocated cluster number in the FSINFO if available.
+/  bit1=1: Do not trust last allocated cluster number in the FSINFO.
+*/
+
+/*---------------------------------------------------------------------------/
+/ System Configurations
+/----------------------------------------------------------------------------*/
+
+#define _FS_TINY    0      /* 0:Normal or 1:Tiny */
+/* This option switches tiny buffer configuration. (0:Normal or 1:Tiny)
+/  At the tiny configuration, size of file object (FIL) is reduced _MAX_SS bytes.
+/  Instead of private sector buffer eliminated from the file object, common sector
+/  buffer in the file system object (FATFS) is used for the file data transfer. */
+
+#define _FS_EXFAT	1
+/* This option switches support of exFAT file system. (0:Disable or 1:Enable)
+/  When enable exFAT, also LFN needs to be enabled. (_USE_LFN >= 1)
+/  Note that enabling exFAT discards C89 compatibility. */
+
+#define _FS_NORTC	0
+#define _NORTC_MON	6
+#define _NORTC_MDAY	4
+#define _NORTC_YEAR	2015
+/* The option _FS_NORTC switches timestamp functiton. If the system does not have
+/  any RTC function or valid timestamp is not needed, set _FS_NORTC = 1 to disable
+/  the timestamp function. All objects modified by FatFs will have a fixed timestamp
+/  defined by _NORTC_MON, _NORTC_MDAY and _NORTC_YEAR in local time.
+/  To enable timestamp function (_FS_NORTC = 0), get_fattime() function need to be
+/  added to the project to get current time form real-time clock. _NORTC_MON,
+/  _NORTC_MDAY and _NORTC_YEAR have no effect.
+/  These options have no effect at read-only configuration (_FS_READONLY = 1). */
+
+#define _FS_LOCK    2     /* 0:Disable or >=1:Enable */
+/* The option _FS_LOCK switches file lock function to control duplicated file open
+/  and illegal operation to open objects. This option must be 0 when _FS_READONLY
+/  is 1.
+/
+/  0:  Disable file lock function. To avoid volume corruption, application program
+/      should avoid illegal open, remove and rename to the open objects.
+/  >0: Enable file lock function. The value defines how many files/sub-directories
+/      can be opened simultaneously under file lock control. Note that the file
+/      lock control is independent of re-entrancy. */
+
+#define _FS_REENTRANT    1  /* 0:Disable or 1:Enable */
+
+#define _USE_MUTEX       0 /* 0:Disable or 1:Enable */
+#define _FS_TIMEOUT      1000 /* Timeout period in unit of time ticks */
+#define _SYNC_t          osSemaphoreId
+/* The option _FS_REENTRANT switches the re-entrancy (thread safe) of the FatFs
+/  module itself. Note that regardless of this option, file access to different
+/  volume is always re-entrant and volume control functions, f_mount(), f_mkfs()
+/  and f_fdisk() function, are always not re-entrant. Only file/directory access
+/  to the same volume is under control of this function.
+/
+/   0: Disable re-entrancy. _FS_TIMEOUT and _SYNC_t have no effect.
+/   1: Enable re-entrancy. Also user provided synchronization handlers,
+/      ff_req_grant(), ff_rel_grant(), ff_del_syncobj() and ff_cre_syncobj()
+/      function, must be added to the project. Samples are available in
+/      option/syscall.c.
+/
+/  The _FS_TIMEOUT defines timeout period in unit of time tick.
+/  The _SYNC_t defines O/S dependent sync object type. e.g. HANDLE, ID, OS_EVENT*,
+/  SemaphoreHandle_t and etc.. A header file for O/S definitions needs to be
+/  included somewhere in the scope of ff.h. */
+
+/* define the ff_malloc ff_free macros as FreeRTOS pvPortMalloc and vPortFree macros */
+#if !defined(ff_malloc) && !defined(ff_free)
+#define ff_malloc  pvPortMalloc
+#define ff_free  vPortFree
+#endif
+
+#endif /* _FFCONF */
diff --git a/FATFS/Target/sd_diskio.c b/FATFS/Target/sd_diskio.c
new file mode 100644
index 0000000..32d1451
--- /dev/null
+++ b/FATFS/Target/sd_diskio.c
@@ -0,0 +1,683 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    sd_diskio.c
+  * @brief   SD Disk I/O driver
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2024 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Note: code generation based on sd_diskio_dma_rtos_template_bspv1.c v2.1.4
+   as FreeRTOS is enabled. */
+
+/* USER CODE BEGIN firstSection */
+/* can be used to modify / undefine following code or add new definitions */
+/* USER CODE END firstSection*/
+
+/* Includes ------------------------------------------------------------------*/
+#include "ff_gen_drv.h"
+#include "sd_diskio.h"
+
+#include <string.h>
+#include <stdio.h>
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+#define QUEUE_SIZE         (uint32_t) 10
+#define READ_CPLT_MSG      (uint32_t) 1
+#define WRITE_CPLT_MSG     (uint32_t) 2
+/*
+==================================================================
+enable the defines below to send custom rtos messages
+when an error or an abort occurs.
+Notice: depending on the HAL/SD driver the HAL_SD_ErrorCallback()
+may not be available.
+See BSP_SD_ErrorCallback() and BSP_SD_AbortCallback() below
+==================================================================
+
+#define RW_ERROR_MSG       (uint32_t) 3
+#define RW_ABORT_MSG       (uint32_t) 4
+*/
+/*
+ * the following Timeout is useful to give the control back to the applications
+ * in case of errors in either BSP_SD_ReadCpltCallback() or BSP_SD_WriteCpltCallback()
+ * the value by default is as defined in the BSP platform driver otherwise 30 secs
+ */
+#define SD_TIMEOUT 30 * 1000
+
+#define SD_DEFAULT_BLOCK_SIZE 512
+
+/*
+ * Depending on the use case, the SD card initialization could be done at the
+ * application level: if it is the case define the flag below to disable
+ * the BSP_SD_Init() call in the SD_Initialize() and add a call to
+ * BSP_SD_Init() elsewhere in the application.
+ */
+/* USER CODE BEGIN disableSDInit */
+/* #define DISABLE_SD_INIT */
+/* USER CODE END disableSDInit */
+
+/*
+ * when using cacheable memory region, it may be needed to maintain the cache
+ * validity. Enable the define below to activate a cache maintenance at each
+ * read and write operation.
+ * Notice: This is applicable only for cortex M7 based platform.
+ */
+/* USER CODE BEGIN enableSDDmaCacheMaintenance */
+/* #define ENABLE_SD_DMA_CACHE_MAINTENANCE  1 */
+/* USER CODE END enableSDDmaCacheMaintenance */
+
+/*
+* Some DMA requires 4-Byte aligned address buffer to correctly read/write data,
+* in FatFs some accesses aren't thus we need a 4-byte aligned scratch buffer to correctly
+* transfer data
+*/
+/* USER CODE BEGIN enableScratchBuffer */
+/* #define ENABLE_SCRATCH_BUFFER */
+/* USER CODE END enableScratchBuffer */
+
+/* Private variables ---------------------------------------------------------*/
+#if defined(ENABLE_SCRATCH_BUFFER)
+#if defined (ENABLE_SD_DMA_CACHE_MAINTENANCE)
+ALIGN_32BYTES(static uint8_t scratch[BLOCKSIZE]); // 32-Byte aligned for cache maintenance
+#else
+__ALIGN_BEGIN static uint8_t scratch[BLOCKSIZE] __ALIGN_END;
+#endif
+#endif
+/* Disk status */
+static volatile DSTATUS Stat = STA_NOINIT;
+
+#if (osCMSIS <= 0x20000U)
+static osMessageQId SDQueueID = NULL;
+#else
+static osMessageQueueId_t SDQueueID = NULL;
+#endif
+/* Private function prototypes -----------------------------------------------*/
+static DSTATUS SD_CheckStatus(BYTE lun);
+DSTATUS SD_initialize (BYTE);
+DSTATUS SD_status (BYTE);
+DRESULT SD_read (BYTE, BYTE*, DWORD, UINT);
+#if _USE_WRITE == 1
+DRESULT SD_write (BYTE, const BYTE*, DWORD, UINT);
+#endif /* _USE_WRITE == 1 */
+#if _USE_IOCTL == 1
+DRESULT SD_ioctl (BYTE, BYTE, void*);
+#endif  /* _USE_IOCTL == 1 */
+
+const Diskio_drvTypeDef  SD_Driver =
+{
+  SD_initialize,
+  SD_status,
+  SD_read,
+#if  _USE_WRITE == 1
+  SD_write,
+#endif /* _USE_WRITE == 1 */
+
+#if  _USE_IOCTL == 1
+  SD_ioctl,
+#endif /* _USE_IOCTL == 1 */
+};
+
+/* USER CODE BEGIN beforeFunctionSection */
+/* can be used to modify / undefine following code or add new code */
+/* USER CODE END beforeFunctionSection */
+
+/* Private functions ---------------------------------------------------------*/
+
+static int SD_CheckStatusWithTimeout(uint32_t timeout)
+{
+  uint32_t timer;
+  /* block until SDIO peripheral is ready again or a timeout occur */
+#if (osCMSIS <= 0x20000U)
+  timer = osKernelSysTick();
+  while( osKernelSysTick() - timer < timeout)
+#else
+  timer = osKernelGetTickCount();
+  while( osKernelGetTickCount() - timer < timeout)
+#endif
+  {
+    if (BSP_SD_GetCardState() == SD_TRANSFER_OK)
+    {
+      return 0;
+    }
+  }
+
+  return -1;
+}
+
+static DSTATUS SD_CheckStatus(BYTE lun)
+{
+  Stat = STA_NOINIT;
+
+  if(BSP_SD_GetCardState() == SD_TRANSFER_OK)
+  {
+    Stat &= ~STA_NOINIT;
+  }
+
+  return Stat;
+}
+
+/**
+  * @brief  Initializes a Drive
+  * @param  lun : not used
+  * @retval DSTATUS: Operation status
+  */
+DSTATUS SD_initialize(BYTE lun)
+{
+Stat = STA_NOINIT;
+
+  /*
+   * check that the kernel has been started before continuing
+   * as the osMessage API will fail otherwise
+   */
+#if (osCMSIS <= 0x20000U)
+  if(osKernelRunning())
+#else
+  if(osKernelGetState() == osKernelRunning)
+#endif
+  {
+#if !defined(DISABLE_SD_INIT)
+
+    if(BSP_SD_Init() == MSD_OK)
+    {
+      Stat = SD_CheckStatus(lun);
+    }
+
+#else
+    Stat = SD_CheckStatus(lun);
+#endif
+
+    /*
+    * if the SD is correctly initialized, create the operation queue
+    * if not already created
+    */
+
+    if (Stat != STA_NOINIT)
+    {
+      if (SDQueueID == NULL)
+      {
+ #if (osCMSIS <= 0x20000U)
+      osMessageQDef(SD_Queue, QUEUE_SIZE, uint16_t);
+      SDQueueID = osMessageCreate (osMessageQ(SD_Queue), NULL);
+#else
+      SDQueueID = osMessageQueueNew(QUEUE_SIZE, 2, NULL);
+#endif
+      }
+
+      if (SDQueueID == NULL)
+      {
+        Stat |= STA_NOINIT;
+      }
+    }
+  }
+
+  return Stat;
+}
+
+/**
+  * @brief  Gets Disk Status
+  * @param  lun : not used
+  * @retval DSTATUS: Operation status
+  */
+DSTATUS SD_status(BYTE lun)
+{
+  return SD_CheckStatus(lun);
+}
+
+/* USER CODE BEGIN beforeReadSection */
+/* can be used to modify previous code / undefine following code / add new code */
+/* USER CODE END beforeReadSection */
+/**
+  * @brief  Reads Sector(s)
+  * @param  lun : not used
+  * @param  *buff: Data buffer to store read data
+  * @param  sector: Sector address (LBA)
+  * @param  count: Number of sectors to read (1..128)
+  * @retval DRESULT: Operation result
+  */
+
+DRESULT SD_read(BYTE lun, BYTE *buff, DWORD sector, UINT count)
+{
+  uint8_t ret;
+  DRESULT res = RES_ERROR;
+  uint32_t timer;
+#if (osCMSIS < 0x20000U)
+  osEvent event;
+#else
+  uint16_t event;
+  osStatus_t status;
+#endif
+#if (ENABLE_SD_DMA_CACHE_MAINTENANCE == 1)
+  uint32_t alignedAddr;
+#endif
+  /*
+  * ensure the SDCard is ready for a new operation
+  */
+
+  if (SD_CheckStatusWithTimeout(SD_TIMEOUT) < 0)
+  {
+    return res;
+  }
+
+#if defined(ENABLE_SCRATCH_BUFFER)
+  if (!((uint32_t)buff & 0x3))
+  {
+#endif
+    /* Fast path cause destination buffer is correctly aligned */
+    ret = BSP_SD_ReadBlocks_DMA((uint32_t*)buff, (uint32_t)(sector), count);
+
+    if (ret == MSD_OK) {
+#if (osCMSIS < 0x20000U)
+    /* wait for a message from the queue or a timeout */
+    event = osMessageGet(SDQueueID, SD_TIMEOUT);
+
+    if (event.status == osEventMessage)
+    {
+      if (event.value.v == READ_CPLT_MSG)
+      {
+        timer = osKernelSysTick();
+        /* block until SDIO IP is ready or a timeout occur */
+        while(osKernelSysTick() - timer <SD_TIMEOUT)
+#else
+          status = osMessageQueueGet(SDQueueID, (void *)&event, NULL, SD_TIMEOUT);
+          if ((status == osOK) && (event == READ_CPLT_MSG))
+          {
+            timer = osKernelGetTickCount();
+            /* block until SDIO IP is ready or a timeout occur */
+            while(osKernelGetTickCount() - timer <SD_TIMEOUT)
+#endif
+            {
+              if (BSP_SD_GetCardState() == SD_TRANSFER_OK)
+              {
+                res = RES_OK;
+#if (ENABLE_SD_DMA_CACHE_MAINTENANCE == 1)
+                /*
+                the SCB_InvalidateDCache_by_Addr() requires a 32-Byte aligned address,
+                adjust the address and the D-Cache size to invalidate accordingly.
+                */
+                alignedAddr = (uint32_t)buff & ~0x1F;
+                SCB_InvalidateDCache_by_Addr((uint32_t*)alignedAddr, count*BLOCKSIZE + ((uint32_t)buff - alignedAddr));
+#endif
+                break;
+              }
+            }
+#if (osCMSIS < 0x20000U)
+          }
+        }
+#else
+      }
+#endif
+    }
+
+#if defined(ENABLE_SCRATCH_BUFFER)
+    }
+    else
+    {
+      /* Slow path, fetch each sector a part and memcpy to destination buffer */
+      int i;
+
+      for (i = 0; i < count; i++)
+      {
+        ret = BSP_SD_ReadBlocks_DMA((uint32_t*)scratch, (uint32_t)sector++, 1);
+        if (ret == MSD_OK )
+        {
+          /* wait until the read is successful or a timeout occurs */
+#if (osCMSIS < 0x20000U)
+          /* wait for a message from the queue or a timeout */
+          event = osMessageGet(SDQueueID, SD_TIMEOUT);
+
+          if (event.status == osEventMessage)
+          {
+            if (event.value.v == READ_CPLT_MSG)
+            {
+              timer = osKernelSysTick();
+              /* block until SDIO IP is ready or a timeout occur */
+              while(osKernelSysTick() - timer <SD_TIMEOUT)
+#else
+                status = osMessageQueueGet(SDQueueID, (void *)&event, NULL, SD_TIMEOUT);
+              if ((status == osOK) && (event == READ_CPLT_MSG))
+              {
+                timer = osKernelGetTickCount();
+                /* block until SDIO IP is ready or a timeout occur */
+                ret = MSD_ERROR;
+                while(osKernelGetTickCount() - timer < SD_TIMEOUT)
+#endif
+                {
+                  ret = BSP_SD_GetCardState();
+
+                  if (ret == MSD_OK)
+                  {
+                    break;
+                  }
+                }
+
+                if (ret != MSD_OK)
+                {
+                  break;
+                }
+#if (osCMSIS < 0x20000U)
+              }
+            }
+#else
+          }
+#endif
+#if (ENABLE_SD_DMA_CACHE_MAINTENANCE == 1)
+          /*
+          *
+          * invalidate the scratch buffer before the next read to get the actual data instead of the cached one
+          */
+          SCB_InvalidateDCache_by_Addr((uint32_t*)scratch, BLOCKSIZE);
+#endif
+          memcpy(buff, scratch, BLOCKSIZE);
+          buff += BLOCKSIZE;
+        }
+        else
+        {
+          break;
+        }
+      }
+
+      if ((i == count) && (ret == MSD_OK ))
+        res = RES_OK;
+    }
+#endif
+  return res;
+}
+
+/* USER CODE BEGIN beforeWriteSection */
+/* can be used to modify previous code / undefine following code / add new code */
+/* USER CODE END beforeWriteSection */
+/**
+  * @brief  Writes Sector(s)
+  * @param  lun : not used
+  * @param  *buff: Data to be written
+  * @param  sector: Sector address (LBA)
+  * @param  count: Number of sectors to write (1..128)
+  * @retval DRESULT: Operation result
+  */
+#if _USE_WRITE == 1
+
+DRESULT SD_write(BYTE lun, const BYTE *buff, DWORD sector, UINT count)
+{
+  DRESULT res = RES_ERROR;
+  uint32_t timer;
+
+#if (osCMSIS < 0x20000U)
+  osEvent event;
+#else
+  uint16_t event;
+  osStatus_t status;
+#endif
+
+#if defined(ENABLE_SCRATCH_BUFFER)
+  int32_t ret;
+#endif
+
+  /*
+  * ensure the SDCard is ready for a new operation
+  */
+
+  if (SD_CheckStatusWithTimeout(SD_TIMEOUT) < 0)
+  {
+    return res;
+  }
+
+#if defined(ENABLE_SCRATCH_BUFFER)
+  if (!((uint32_t)buff & 0x3))
+  {
+#endif
+#if (ENABLE_SD_DMA_CACHE_MAINTENANCE == 1)
+  uint32_t alignedAddr;
+  /*
+    the SCB_CleanDCache_by_Addr() requires a 32-Byte aligned address
+    adjust the address and the D-Cache size to clean accordingly.
+  */
+  alignedAddr = (uint32_t)buff & ~0x1F;
+  SCB_CleanDCache_by_Addr((uint32_t*)alignedAddr, count*BLOCKSIZE + ((uint32_t)buff - alignedAddr));
+#endif
+
+  if(BSP_SD_WriteBlocks_DMA((uint32_t*)buff,
+                           (uint32_t) (sector),
+                           count) == MSD_OK)
+  {
+#if (osCMSIS < 0x20000U)
+    /* Get the message from the queue */
+    event = osMessageGet(SDQueueID, SD_TIMEOUT);
+
+    if (event.status == osEventMessage)
+    {
+      if (event.value.v == WRITE_CPLT_MSG)
+      {
+#else
+    status = osMessageQueueGet(SDQueueID, (void *)&event, NULL, SD_TIMEOUT);
+    if ((status == osOK) && (event == WRITE_CPLT_MSG))
+    {
+#endif
+ #if (osCMSIS < 0x20000U)
+        timer = osKernelSysTick();
+        /* block until SDIO IP is ready or a timeout occur */
+        while(osKernelSysTick() - timer  < SD_TIMEOUT)
+#else
+        timer = osKernelGetTickCount();
+        /* block until SDIO IP is ready or a timeout occur */
+        while(osKernelGetTickCount() - timer  < SD_TIMEOUT)
+#endif
+        {
+          if (BSP_SD_GetCardState() == SD_TRANSFER_OK)
+          {
+            res = RES_OK;
+            break;
+          }
+        }
+#if (osCMSIS < 0x20000U)
+      }
+    }
+#else
+    }
+#endif
+  }
+#if defined(ENABLE_SCRATCH_BUFFER)
+  else {
+    /* Slow path, fetch each sector a part and memcpy to destination buffer */
+    int i;
+
+#if (ENABLE_SD_DMA_CACHE_MAINTENANCE == 1)
+    /*
+     * invalidate the scratch buffer before the next write to get the actual data instead of the cached one
+     */
+     SCB_InvalidateDCache_by_Addr((uint32_t*)scratch, BLOCKSIZE);
+#endif
+      for (i = 0; i < count; i++)
+      {
+        memcpy((void *)scratch, buff, BLOCKSIZE);
+        buff += BLOCKSIZE;
+
+        ret = BSP_SD_WriteBlocks_DMA((uint32_t*)scratch, (uint32_t)sector++, 1);
+        if (ret == MSD_OK )
+        {
+          /* wait until the read is successful or a timeout occurs */
+#if (osCMSIS < 0x20000U)
+          /* wait for a message from the queue or a timeout */
+          event = osMessageGet(SDQueueID, SD_TIMEOUT);
+
+          if (event.status == osEventMessage)
+          {
+            if (event.value.v == READ_CPLT_MSG)
+            {
+              timer = osKernelSysTick();
+              /* block until SDIO IP is ready or a timeout occur */
+              while(osKernelSysTick() - timer <SD_TIMEOUT)
+#else
+                status = osMessageQueueGet(SDQueueID, (void *)&event, NULL, SD_TIMEOUT);
+              if ((status == osOK) && (event == READ_CPLT_MSG))
+              {
+                timer = osKernelGetTickCount();
+                /* block until SDIO IP is ready or a timeout occur */
+                ret = MSD_ERROR;
+                while(osKernelGetTickCount() - timer < SD_TIMEOUT)
+#endif
+                {
+                  ret = BSP_SD_GetCardState();
+
+                  if (ret == MSD_OK)
+                  {
+                    break;
+                  }
+                }
+
+                if (ret != MSD_OK)
+                {
+                  break;
+                }
+#if (osCMSIS < 0x20000U)
+              }
+            }
+#else
+          }
+#endif
+        }
+        else
+        {
+          break;
+        }
+      }
+
+      if ((i == count) && (ret == MSD_OK ))
+        res = RES_OK;
+    }
+
+  }
+#endif
+
+  return res;
+}
+ #endif /* _USE_WRITE == 1 */
+
+/* USER CODE BEGIN beforeIoctlSection */
+/* can be used to modify previous code / undefine following code / add new code */
+/* USER CODE END beforeIoctlSection */
+/**
+  * @brief  I/O control operation
+  * @param  lun : not used
+  * @param  cmd: Control code
+  * @param  *buff: Buffer to send/receive control data
+  * @retval DRESULT: Operation result
+  */
+#if _USE_IOCTL == 1
+DRESULT SD_ioctl(BYTE lun, BYTE cmd, void *buff)
+{
+  DRESULT res = RES_ERROR;
+  BSP_SD_CardInfo CardInfo;
+
+  if (Stat & STA_NOINIT) return RES_NOTRDY;
+
+  switch (cmd)
+  {
+  /* Make sure that no pending write process */
+  case CTRL_SYNC :
+    res = RES_OK;
+    break;
+
+  /* Get number of sectors on the disk (DWORD) */
+  case GET_SECTOR_COUNT :
+    BSP_SD_GetCardInfo(&CardInfo);
+    *(DWORD*)buff = CardInfo.LogBlockNbr;
+    res = RES_OK;
+    break;
+
+  /* Get R/W sector size (WORD) */
+  case GET_SECTOR_SIZE :
+    BSP_SD_GetCardInfo(&CardInfo);
+    *(WORD*)buff = CardInfo.LogBlockSize;
+    res = RES_OK;
+    break;
+
+  /* Get erase block size in unit of sector (DWORD) */
+  case GET_BLOCK_SIZE :
+    BSP_SD_GetCardInfo(&CardInfo);
+    *(DWORD*)buff = CardInfo.LogBlockSize / SD_DEFAULT_BLOCK_SIZE;
+    res = RES_OK;
+    break;
+
+  default:
+    res = RES_PARERR;
+  }
+
+  return res;
+}
+#endif /* _USE_IOCTL == 1 */
+
+/* USER CODE BEGIN afterIoctlSection */
+/* can be used to modify previous code / undefine following code / add new code */
+/* USER CODE END afterIoctlSection */
+
+/* USER CODE BEGIN callbackSection */
+/* can be used to modify / following code or add new code */
+/* USER CODE END callbackSection */
+/**
+  * @brief Tx Transfer completed callbacks
+  * @param hsd: SD handle
+  * @retval None
+  */
+void BSP_SD_WriteCpltCallback(void)
+{
+
+  /*
+   * No need to add an "osKernelRunning()" check here, as the SD_initialize()
+   * is always called before any SD_Read()/SD_Write() call
+   */
+#if (osCMSIS < 0x20000U)
+   osMessagePut(SDQueueID, WRITE_CPLT_MSG, 0);
+#else
+   const uint16_t msg = WRITE_CPLT_MSG;
+   osMessageQueuePut(SDQueueID, (const void *)&msg, 0, 0);
+#endif
+}
+
+/**
+  * @brief Rx Transfer completed callbacks
+  * @param hsd: SD handle
+  * @retval None
+  */
+void BSP_SD_ReadCpltCallback(void)
+{
+  /*
+   * No need to add an "osKernelRunning()" check here, as the SD_initialize()
+   * is always called before any SD_Read()/SD_Write() call
+   */
+#if (osCMSIS < 0x20000U)
+   osMessagePut(SDQueueID, READ_CPLT_MSG, 0);
+#else
+   const uint16_t msg = READ_CPLT_MSG;
+   osMessageQueuePut(SDQueueID, (const void *)&msg, 0, 0);
+#endif
+}
+
+/* USER CODE BEGIN ErrorAbortCallbacks */
+/*
+void BSP_SD_AbortCallback(void)
+{
+#if (osCMSIS < 0x20000U)
+   osMessagePut(SDQueueID, RW_ABORT_MSG, 0);
+#else
+   const uint16_t msg = RW_ABORT_MSG;
+   osMessageQueuePut(SDQueueID, (const void *)&msg, 0, 0);
+#endif
+}
+*/
+/* USER CODE END ErrorAbortCallbacks */
+
+/* USER CODE BEGIN lastSection */
+/* can be used to modify / undefine previous code or add new code */
+/* USER CODE END lastSection */
diff --git a/FATFS/Target/sd_diskio.h b/FATFS/Target/sd_diskio.h
new file mode 100644
index 0000000..58a204c
--- /dev/null
+++ b/FATFS/Target/sd_diskio.h
@@ -0,0 +1,41 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    sd_diskio.h
+  * @brief   Header for sd_diskio.c module
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2024 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Note: code generation based on sd_diskio_dma_rtos_template.h */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __SD_DISKIO_H
+#define __SD_DISKIO_H
+
+/* USER CODE BEGIN firstSection */
+/* can be used to modify / undefine following code or add new definitions */
+/* USER CODE END firstSection */
+
+/* Includes ------------------------------------------------------------------*/
+#include "bsp_driver_sd.h"
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+extern const Diskio_drvTypeDef  SD_Driver;
+
+/* USER CODE BEGIN lastSection */
+/* can be used to modify / undefine previous code or add new definitions */
+/* USER CODE END lastSection */
+
+#endif /* __SD_DISKIO_H */
diff --git a/LICENSE b/LICENSE
deleted file mode 100644
index 4ef3a4c..0000000
--- a/LICENSE
+++ /dev/null
@@ -1,9 +0,0 @@
-MIT License
-
-Copyright (c) 2024 allNighter
-
-Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions:
-
-The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
diff --git a/LWFTP/_lwftp.c b/LWFTP/_lwftp.c
deleted file mode 100644
index 4cf377c..0000000
--- a/LWFTP/_lwftp.c
+++ /dev/null
@@ -1,692 +0,0 @@
-/*
- * lwftp.c : a lightweight FTP client using raw API of LWIP
- *
- * Copyright (c) 2014 GEZEDO
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * Author: Laurent GONZALEZ <lwip@gezedo.com>
- *
- */
-
-#include <_lwftp.h>
-#include <string.h>
-#include "lwip/tcp.h"
-#include "lwip/tcpip.h"
-
-/** Enable debugging for LWFTP */
-#ifndef LWFTP_DEBUG
-#define LWFTP_DEBUG   LWIP_DBG_ON
-#endif
-
-#define LWFTP_TRACE   (LWFTP_DEBUG|LWIP_DBG_TRACE)
-#define LWFTP_STATE   (LWFTP_DEBUG|LWIP_DBG_STATE)
-#define LWFTP_WARNING (LWFTP_DEBUG|LWIP_DBG_LEVEL_WARNING)
-#define LWFTP_SERIOUS (LWFTP_DEBUG|LWIP_DBG_LEVEL_SERIOUS)
-#define LWFTP_SEVERE  (LWFTP_DEBUG|LWIP_DBG_LEVEL_SEVERE)
-
-#define PTRNLEN(s)  s,(sizeof(s)-1)
-
-static void lwftp_control_process(lwftp_session_t *s, struct tcp_pcb *tpcb,
-		struct pbuf *p);
-
-/** Close control or data pcb
- * @param pointer to lwftp session data
- */
-static err_t lwftp_pcb_close(struct tcp_pcb *tpcb) {
-	err_t error;
-
-	tcp_err(tpcb, NULL);
-	tcp_recv(tpcb, NULL);
-	tcp_sent(tpcb, NULL);
-	error = tcp_close(tpcb);
-	if (error != ERR_OK) {
-		LWIP_DEBUGF(LWFTP_SEVERE, ("lwftp:pcb close failure, not implemented\n"));
-	}
-	return ERR_OK;
-}
-
-/** Send data
- * @param pointer to lwftp session data
- * @param pointer to PCB
- * @param number of bytes sent
- */
-static err_t lwftp_send_next_data(lwftp_session_t *s) {
-	const char *data;
-	int len = 0;
-	err_t error = ERR_OK;
-
-	if (s->data_source) {
-		len = s->data_source(s->handle, &data, s->data_pcb->mss);
-		if (len) {
-			error = tcp_write(s->data_pcb, data, len, 0);
-			if (error != ERR_OK) {
-				LWIP_DEBUGF(LWFTP_SEVERE, ("lwftp:write failure (%s), not implemented\n",lwip_strerr(error)));
-			}
-		}
-	}
-	if (!len) {
-		LWIP_DEBUGF(LWFTP_STATE, ("lwftp:end of file\n"));
-		lwftp_pcb_close(s->data_pcb);
-		s->data_pcb = NULL;
-	}
-	return ERR_OK;
-}
-
-/** Handle data connection incoming data
- * @param pointer to lwftp session data
- * @param pointer to PCB
- * @param pointer to incoming pbuf
- * @param state of incoming process
- */
-static err_t lwftp_data_recv(void *arg, struct tcp_pcb *tpcb, struct pbuf *p,
-		err_t err) {
-	lwftp_session_t *s = (lwftp_session_t*) arg;
-	if (p) {
-		if (s->data_sink) {
-			struct pbuf *q;
-			for (q = p; q; q = q->next) {
-				s->data_sink(s->handle, q->payload, q->len);
-			}
-		} else {
-			LWIP_DEBUGF(LWFTP_SEVERE, ("lwftp: sinking %d bytes\n",p->tot_len));
-		}
-		tcp_recved(tpcb, p->tot_len);
-		pbuf_free(p);
-	} else {
-		// NULL pbuf shall lead to close the pcb. Close is postponed after
-		// the session state machine updates. No need to close right here.
-		// Instead we kindly tell data sink we are done
-		if (s->data_sink) {
-			s->data_sink(s->handle, NULL, 0);
-		}
-	}
-	return ERR_OK;
-}
-
-/** Handle data connection acknowledge of sent data
- * @param pointer to lwftp session data
- * @param pointer to PCB
- * @param number of bytes sent
- */
-static err_t lwftp_data_sent(void *arg, struct tcp_pcb *tpcb, u16_t len) {
-	lwftp_session_t *s = (lwftp_session_t*) arg;
-
-	if (s->data_source) {
-		s->data_source(s->handle, NULL, len);
-	}
-	return lwftp_send_next_data(s);
-}
-
-/** Handle data connection error
- * @param pointer to lwftp session data
- * @param state of connection
- */
-static void lwftp_data_err(void *arg, err_t err) {
-	LWIP_UNUSED_ARG(err);
-	if (arg != NULL) {
-		lwftp_session_t *s = (lwftp_session_t*) arg;
-		LWIP_DEBUGF(LWFTP_WARNING, ("lwftp:failed/error connecting for data to server (%s)\n",lwip_strerr(err)));
-		s->data_pcb = NULL; // No need to de-allocate PCB
-		if (s->control_state == LWFTP_XFERING) { // gracefully move control session ahead
-			s->control_state = LWFTP_DATAEND;
-			lwftp_control_process(s, NULL, NULL);
-		}
-	}
-}
-
-/** Process newly connected PCB
- * @param pointer to lwftp session data
- * @param pointer to PCB
- * @param state of connection
- */
-static err_t lwftp_data_connected(void *arg, struct tcp_pcb *tpcb, err_t err) {
-	lwftp_session_t *s = (lwftp_session_t*) arg;
-
-	if (err == ERR_OK) {
-		LWIP_DEBUGF(LWFTP_STATE, ("lwftp:connected for data to server\n"));
-		s->data_state = LWFTP_CONNECTED;
-	} else {
-		LWIP_DEBUGF(LWFTP_WARNING, ("lwftp:err in data_connected (%s)\n",lwip_strerr(err)));
-	}
-	return err;
-}
-
-/** Open data connection for passive transfer
- * @param pointer to lwftp session data
- * @param pointer to incoming PASV response
- */
-static err_t lwftp_data_open(lwftp_session_t *s, struct pbuf *p) {
-	err_t error;
-	char *ptr;
-	ip_addr_t data_server;
-	u16_t data_port;
-
-	// Find server connection parameter
-	ptr = strchr(p->payload, '(');
-	if (!ptr)
-		return ERR_BUF;
-	do {
-		unsigned int a = strtoul(ptr + 1, &ptr, 10);
-		unsigned int b = strtoul(ptr + 1, &ptr, 10);
-		unsigned int c = strtoul(ptr + 1, &ptr, 10);
-		unsigned int d = strtoul(ptr + 1, &ptr, 10);
-		IP4_ADDR(&data_server, a, b, c, d);
-	} while (0);
-	data_port = strtoul(ptr + 1, &ptr, 10) << 8;
-	data_port |= strtoul(ptr + 1, &ptr, 10) & 255;
-	if (*ptr != ')')
-		return ERR_BUF;
-
-	// Open data session
-	tcp_arg(s->data_pcb, s);
-	tcp_err(s->data_pcb, lwftp_data_err);
-	tcp_recv(s->data_pcb, lwftp_data_recv);
-	tcp_sent(s->data_pcb, lwftp_data_sent);
-	error = tcp_connect(s->data_pcb, &data_server, data_port,
-			lwftp_data_connected);
-	return error;
-}
-
-/** Send a message to control connection
- * @param pointer to lwftp session data
- * @param pointer to message string
- */
-static err_t lwftp_send_msg(lwftp_session_t *s, const char *msg, size_t len) {
-	err_t error;
-
-	LWIP_DEBUGF(LWFTP_TRACE,("lwftp:sending %s",msg));
-	error = tcp_write(s->control_pcb, msg, len, 0);
-	if (error != ERR_OK) {
-		LWIP_DEBUGF(LWFTP_WARNING, ("lwftp:cannot write (%s)\n",lwip_strerr(error)));
-	}
-	return error;
-}
-
-/** Close data connection
- * @param pointer to lwftp session data
- * @param result to pass to callback fn (if called)
- */
-static void lwftp_data_close(lwftp_session_t *s, int result) {
-	if (s->data_pcb) {
-		lwftp_pcb_close(s->data_pcb);
-		s->data_pcb = NULL;
-	}
-	if (s->done_fn) {
-		s->done_fn(s->handle, result);
-	}
-}
-
-/** Close control connection
- * @param pointer to lwftp session data
- * @param result to pass to callback fn (if called)
- */
-static void lwftp_control_close(lwftp_session_t *s, int result) {
-	if (s->data_pcb) {
-		lwftp_pcb_close(s->data_pcb);
-		s->data_pcb = NULL;
-	}
-	if (s->control_pcb) {
-		lwftp_pcb_close(s->control_pcb);
-		s->control_pcb = NULL;
-	}
-	s->control_state = LWFTP_CLOSED;
-	if ((result >= 0) && s->done_fn) {
-		s->done_fn(s->handle, result);
-	}
-}
-
-/** Main client state machine
- * @param pointer to lwftp session data
- * @param pointer to PCB
- * @param pointer to incoming data
- */
-static void lwftp_control_process(lwftp_session_t *s, struct tcp_pcb *tpcb,
-		struct pbuf *p) {
-	uint response = 0;
-	int result = LWFTP_RESULT_ERR_SRVR_RESP;
-
-	// Try to get response number
-	if (p) {
-		response = strtoul(p->payload, NULL, 10);
-		LWIP_DEBUGF(LWFTP_TRACE, ("lwftp:got response %d\n",response));
-	}
-
-	switch (s->control_state) {
-	case LWFTP_CONNECTED:
-		if (response > 0) {
-			if (response == 220) {
-				lwftp_send_msg(s, PTRNLEN("USER "));
-				lwftp_send_msg(s, s->user, strlen(s->user));
-				lwftp_send_msg(s, PTRNLEN("\r\n"));
-				s->control_state = LWFTP_USER_SENT;
-			} else {
-				s->control_state = LWFTP_QUIT;
-			}
-		}
-		break;
-	case LWFTP_USER_SENT:
-		if (response > 0) {
-			if (response == 331) {
-				lwftp_send_msg(s, PTRNLEN("PASS "));
-				lwftp_send_msg(s, s->pass, strlen(s->pass));
-				lwftp_send_msg(s, PTRNLEN("\r\n"));
-				s->control_state = LWFTP_PASS_SENT;
-			} else {
-				s->control_state = LWFTP_QUIT;
-			}
-		}
-		break;
-	case LWFTP_PASS_SENT:
-		if (response > 0) {
-			if (response == 230) {
-				s->control_state = LWFTP_LOGGED;
-				LWIP_DEBUGF(LWFTP_STATE, ("lwftp: now logged in\n"));
-				if (s->done_fn) {
-					s->done_fn(s->handle, LWFTP_RESULT_LOGGED);
-				}
-			} else {
-				s->control_state = LWFTP_QUIT;
-			}
-		}
-		break;
-	case LWFTP_TYPE_SENT:
-		if (response > 0) {
-			if (response == 200) {
-				lwftp_send_msg(s, PTRNLEN("PASV\r\n"));
-				s->control_state = LWFTP_PASV_SENT;
-			} else {
-				s->control_state = LWFTP_QUIT;
-			}
-		}
-		break;
-	case LWFTP_PASV_SENT:
-		if (response > 0) {
-			if (response == 227) {
-				lwftp_data_open(s, p);
-				switch (s->target_state) {
-				case LWFTP_STOR_SENT:
-					lwftp_send_msg(s, PTRNLEN("STOR "));
-					break;
-				case LWFTP_RETR_SENT:
-					lwftp_send_msg(s, PTRNLEN("RETR "));
-					break;
-				default:
-					LOG_ERROR("Unexpected internal state");
-					s->target_state = LWFTP_QUIT;
-				}
-				lwftp_send_msg(s, s->remote_path, strlen(s->remote_path));
-				lwftp_send_msg(s, PTRNLEN("\r\n"));
-				s->control_state = s->target_state;
-			} else {
-				s->control_state = LWFTP_QUIT;
-			}
-		}
-		break;
-	case LWFTP_RETR_SENT:
-		if (response > 0) {
-			if (response == 150) {
-				s->control_state = LWFTP_XFERING;
-			} else if (response == 550) {
-				s->control_state = LWFTP_DATAEND;
-				result = LWFTP_RESULT_ERR_FILENAME;
-				LWIP_DEBUGF(LWFTP_WARNING, ("lwftp: Failed to open file '%s'\n", s->remote_path));
-			} else {
-				s->control_state = LWFTP_DATAEND;
-				LWIP_DEBUGF(LWFTP_WARNING, ("lwftp:expected 150, received %d\n",response));
-			}
-		}
-		break;
-	case LWFTP_STOR_SENT:
-		if (response > 0) {
-			if (response == 150) {
-				s->control_state = LWFTP_XFERING;
-				lwftp_data_sent(s, NULL, 0);
-			} else {
-				s->control_state = LWFTP_DATAEND;
-				LWIP_DEBUGF(LWFTP_WARNING, ("lwftp:expected 150, received %d\n",response));
-			}
-		}
-		break;
-	case LWFTP_XFERING:
-		if (response > 0) {
-			if (response == 226) {
-				result = LWFTP_RESULT_OK;
-			} else {
-				result = LWFTP_RESULT_ERR_CLOSED;
-				LWIP_DEBUGF(LWFTP_WARNING, ("lwftp:expected 226, received %d\n",response));
-			}
-			s->control_state = LWFTP_DATAEND;
-		}
-		break;
-	case LWFTP_DATAEND:
-		LOG_TRACE("forced end of data session");
-		break;
-	case LWFTP_QUIT_SENT:
-		if (response > 0) {
-			if (response == 221) {
-				result = LWFTP_RESULT_OK;
-			} else {
-				result = LWFTP_RESULT_ERR_UNKNOWN;
-				LWIP_DEBUGF(LWFTP_WARNING, ("lwftp:expected 221, received %d\n",response));
-			}
-			s->control_state = LWFTP_CLOSING;
-		}
-		break;
-	default:
-		LWIP_DEBUGF(LWFTP_SEVERE, ("lwftp:unhandled state (%d)\n",s->control_state));
-	}
-
-	// Free receiving pbuf if any
-	if (p) {
-		pbuf_free(p);
-	}
-
-	// Handle second step in state machine
-	switch (s->control_state) {
-	case LWFTP_DATAEND:
-		lwftp_data_close(s, result);
-		s->control_state = LWFTP_LOGGED;
-		break;
-	case LWFTP_QUIT:
-		lwftp_send_msg(s, PTRNLEN("QUIT\r\n"));
-		tcp_output(s->control_pcb);
-		s->control_state = LWFTP_QUIT_SENT;
-		break;
-	case LWFTP_CLOSING:
-		// this function frees s, no use of s is allowed after
-		lwftp_control_close(s, result);
-		break;
-	default:
-		;
-	}
-}
-
-/** Start a RETR data session
- * @param pointer to lwftp session
- */
-static void lwftp_start_RETR(void *arg) {
-	lwftp_session_t *s = (lwftp_session_t*) arg;
-
-	if (s->control_state == LWFTP_LOGGED) {
-		lwftp_send_msg(s, PTRNLEN("TYPE I\r\n"));
-		s->control_state = LWFTP_TYPE_SENT;
-		s->target_state = LWFTP_RETR_SENT;
-	} else {
-		LOG_ERROR("Unexpected condition");
-		if (s->done_fn)
-			s->done_fn(s->handle, LWFTP_RESULT_ERR_INTERNAL);
-	}
-}
-
-/** Start a STOR data session
- * @param pointer to lwftp session
- */
-static void lwftp_start_STOR(void *arg) {
-	lwftp_session_t *s = (lwftp_session_t*) arg;
-
-	if (s->control_state == LWFTP_LOGGED) {
-		lwftp_send_msg(s, PTRNLEN("TYPE I\r\n"));
-		s->control_state = LWFTP_TYPE_SENT;
-		s->target_state = LWFTP_STOR_SENT;
-	} else {
-		LOG_ERROR("Unexpected condition");
-		if (s->done_fn)
-			s->done_fn(s->handle, LWFTP_RESULT_ERR_INTERNAL);
-	}
-}
-
-/** Send QUIT to terminate control session
- * @param pointer to lwftp session
- */
-static void lwftp_send_QUIT(void *arg) {
-	lwftp_session_t *s = (lwftp_session_t*) arg;
-
-	if (s->control_pcb) {
-		lwftp_send_msg(s, PTRNLEN("QUIT\r\n"));
-		tcp_output(s->control_pcb);
-		s->control_state = LWFTP_QUIT_SENT;
-	}
-}
-
-/** Handle control connection incoming data
- * @param pointer to lwftp session data
- * @param pointer to PCB
- * @param pointer to incoming pbuf
- * @param state of incoming process
- */
-static err_t lwftp_control_recv(void *arg, struct tcp_pcb *tpcb, struct pbuf *p,
-		err_t err) {
-	lwftp_session_t *s = (lwftp_session_t*) arg;
-
-	if (err == ERR_OK) {
-		if (p) {
-			tcp_recved(tpcb, p->tot_len);
-			lwftp_control_process(s, tpcb, p);
-		} else {
-			LWIP_DEBUGF(LWFTP_WARNING, ("lwftp:connection closed by remote host\n"));
-			lwftp_control_close(s, LWFTP_RESULT_ERR_CLOSED);
-		}
-	} else {
-		LWIP_DEBUGF(LWFTP_SERIOUS, ("lwftp:failed to receive (%s)\n",lwip_strerr(err)));
-		lwftp_control_close(s, LWFTP_RESULT_ERR_UNKNOWN);
-	}
-	return err;
-}
-
-/** Handle control connection acknowledge of sent data
- * @param pointer to lwftp session data
- * @param pointer to PCB
- * @param number of bytes sent
- */
-static err_t lwftp_control_sent(void *arg, struct tcp_pcb *tpcb, u16_t len) {
-	LWIP_DEBUGF(LWFTP_TRACE, ("lwftp:successfully sent %d bytes\n",len));
-	return ERR_OK;
-}
-
-/** Handle control connection error
- * @param pointer to lwftp session data
- * @param state of connection
- */
-static void lwftp_control_err(void *arg, err_t err) {
-	LWIP_UNUSED_ARG(err);
-	if (arg != NULL) {
-		lwftp_session_t *s = (lwftp_session_t*) arg;
-		int result;
-		if (s->control_state == LWFTP_CLOSED) {
-			LWIP_DEBUGF(LWFTP_WARNING, ("lwftp:failed to connect to server (%s)\n",lwip_strerr(err)));
-			result = LWFTP_RESULT_ERR_CONNECT;
-		} else {
-			LWIP_DEBUGF(LWFTP_WARNING, ("lwftp:connection closed by remote host\n"));
-			result = LWFTP_RESULT_ERR_CLOSED;
-		}
-		s->control_pcb = NULL; // No need to de-allocate PCB
-		lwftp_control_close(s, result);
-	}
-}
-
-/** Process newly connected PCB
- * @param pointer to lwftp session data
- * @param pointer to PCB
- * @param state of connection
- */
-static err_t lwftp_control_connected(void *arg, struct tcp_pcb *tpcb, err_t err) {
-	lwftp_session_t *s = (lwftp_session_t*) arg;
-
-	if (err == ERR_OK) {
-		LWIP_DEBUGF(LWFTP_STATE, ("lwftp:connected to server\n"));
-	} else {
-		LWIP_DEBUGF(LWFTP_WARNING, ("lwftp:err in control_connected (%s)\n", lwip_strerr(err)));
-		if (s->done_fn) {
-			s->done_fn(s->handle, LWFTP_RESULT_ERR_CONNECT); // 연결 실패 상태 전달
-		}
-	}
-	return err;
-}
-
-/** Open a control session
- * @param Session structure
- */
-err_t lwftp_connect(lwftp_session_t *s) {
-	err_t error;
-	enum lwftp_results retval = LWFTP_RESULT_ERR_UNKNOWN;
-
-	// Check user supplied data
-	if ((s->control_state != LWFTP_CLOSED) || s->control_pcb || s->data_pcb
-			|| !s->user || !s->pass) {
-		LWIP_DEBUGF(LWFTP_WARNING, ("lwftp:invalid control session\n"));
-		retval = LWFTP_RESULT_ERR_ARGUMENT;
-		goto exit;
-	}
-	// Get sessions pcb
-	s->control_pcb = tcp_new();
-	if (!s->control_pcb) {
-		LWIP_DEBUGF(LWFTP_SERIOUS, ("lwftp:cannot alloc control_pcb (low memory?)\n"));
-		retval = LWFTP_RESULT_ERR_MEMORY;
-		goto exit;
-	}
-	// Open control session
-	tcp_arg(s->control_pcb, s);
-	tcp_err(s->control_pcb, lwftp_control_err);
-	tcp_recv(s->control_pcb, lwftp_control_recv);
-	tcp_sent(s->control_pcb, lwftp_control_sent);
-	error = tcp_connect(s->control_pcb, &s->server_ip, s->server_port,
-			lwftp_control_connected);
-	if (error == ERR_OK) {
-		retval = LWFTP_RESULT_INPROGRESS;
-		goto exit;
-	}
-
-	// Release pcbs in case of failure
-	LWIP_DEBUGF(LWFTP_SERIOUS, ("lwftp:cannot connect control_pcb (%s)\n", lwip_strerr(error)));
-	lwftp_control_close(s, -1);
-
-	exit: if (s->done_fn)
-		s->done_fn(s->handle, retval);
-	return retval;
-}
-
-/** Retrieve data from a remote file
- * @param Session structure
- */
-err_t lwftp_retrieve(lwftp_session_t *s) {
-	err_t error;
-	enum lwftp_results retval = LWFTP_RESULT_ERR_UNKNOWN;
-
-	// Check user supplied data
-	if ((s->control_state != LWFTP_LOGGED) || !s->remote_path || s->data_pcb) {
-		LWIP_DEBUGF(LWFTP_WARNING, ("lwftp:invalid session data\n"));
-		retval = LWFTP_RESULT_ERR_ARGUMENT;
-		goto exit;
-	}
-	// Get data pcb
-	s->data_pcb = tcp_new();
-	if (!s->data_pcb) {
-		LWIP_DEBUGF(LWFTP_SERIOUS, ("lwftp:cannot alloc data_pcb (low memory?)\n"));
-		retval = LWFTP_RESULT_ERR_MEMORY;
-		goto exit;
-	}
-	// Initiate transfer
-	error = tcpip_callback(lwftp_start_RETR, s);
-	if (error == ERR_OK) {
-		retval = LWFTP_RESULT_INPROGRESS;
-	} else {
-		LOG_ERROR("cannot start RETR (%s)", lwip_strerr(error));
-		retval = LWFTP_RESULT_ERR_INTERNAL;
-	}
-
-	exit: if (s->done_fn)
-		s->done_fn(s->handle, retval);
-	return retval;
-}
-
-/** Store data to a remote file
- * @param Session structure
- */
-err_t lwftp_store(lwftp_session_t *s) {
-	err_t error;
-	enum lwftp_results retval = LWFTP_RESULT_ERR_UNKNOWN;
-
-	// Check user supplied data
-	if ((s->control_state != LWFTP_LOGGED) || !s->remote_path || s->data_pcb) {
-		LWIP_DEBUGF(LWFTP_WARNING, ("lwftp:invalid session data\n"));
-		retval = LWFTP_RESULT_ERR_ARGUMENT;
-		goto exit;
-	}
-	// Get data pcb
-	s->data_pcb = tcp_new();
-	if (!s->data_pcb) {
-		LWIP_DEBUGF(LWFTP_SERIOUS, ("lwftp:cannot alloc data_pcb (low memory?)\n"));
-		retval = LWFTP_RESULT_ERR_MEMORY;
-		goto exit;
-	}
-	// Initiate transfer
-	error = tcpip_callback(lwftp_start_STOR, s);
-	if (error == ERR_OK) {
-		retval = LWFTP_RESULT_INPROGRESS;
-	} else {
-		LOG_ERROR("cannot start STOR (%s)", lwip_strerr(error));
-		retval = LWFTP_RESULT_ERR_INTERNAL;
-	}
-
-	exit: if (s->done_fn)
-		s->done_fn(s->handle, retval);
-	return retval;
-}
-
-/** Terminate FTP session
- * @param Session structure
- */
-//void lwftp_close(lwftp_session_t *s)
-//{
-//  err_t error;
-//
-//  // Nothing to do when already closed
-//  if ( s->control_state == LWFTP_CLOSED ) return;
-//
-//  // Initiate transfer
-//  error = tcpip_callback(lwftp_send_QUIT, s);
-//  if ( error != ERR_OK ) {
-//    // This is a critical error, try to close anyway
-//    // polling process may save us
-//    LOG_ERROR("cannot request for close");
-//    s->control_state = LWFTP_QUIT;
-//  }
-//}
-void lwftp_close(lwftp_session_t *s) {
-	if (s->control_state == LWFTP_CLOSED)
-		return;
-	if (s->control_pcb != NULL) {
-		lwftp_send_msg(s, "QUIT\r\n", strlen("QUIT\r\n"));
-		tcp_output(s->control_pcb);
-
-		lwftp_pcb_close(s->control_pcb);
-		s->control_pcb = NULL;
-	}
-	if (s->data_pcb != NULL) {
-		lwftp_pcb_close(s->data_pcb);
-		s->data_pcb = NULL;
-	}
-	s->control_state = LWFTP_CLOSED;
-}
diff --git a/LWFTP/_lwftp.h b/LWFTP/_lwftp.h
deleted file mode 100644
index 9270884..0000000
--- a/LWFTP/_lwftp.h
+++ /dev/null
@@ -1,109 +0,0 @@
-/*
- * lwftp.h : a lightweight FTP client using raw API of LWIP
- *
- * Copyright (c) 2014 GEZEDO
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * Author: Laurent GONZALEZ <lwip@gezedo.com>
- *
- */
-
-#ifndef LWFTP_H
-#define LWFTP_H
-
-#include "lwip/opt.h"
-#include "lwip/ip.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-enum lwftp_results {
-  LWFTP_RESULT_OK=0,
-  LWFTP_RESULT_INPROGRESS,
-  LWFTP_RESULT_LOGGED,
-  LWFTP_RESULT_ERR_UNKNOWN,   /** Unknown error */
-  LWFTP_RESULT_ERR_ARGUMENT,  /** Wrong argument */
-  LWFTP_RESULT_ERR_MEMORY,    /** Out of memory */
-  LWFTP_RESULT_ERR_CONNECT,   /** Connection to server failed */
-  LWFTP_RESULT_ERR_HOSTNAME,  /** Failed to resolve server hostname */
-  LWFTP_RESULT_ERR_CLOSED,    /** Connection unexpectedly closed by remote server */
-  LWFTP_RESULT_ERR_TIMEOUT,   /** Connection timed out (server didn't respond in time) */
-  LWFTP_RESULT_ERR_SRVR_RESP, /** Server responded with an unknown response code */
-  LWFTP_RESULT_ERR_INTERNAL,  /** Internal network stack error */
-  LWFTP_RESULT_ERR_LOCAL,     /** Local storage error */
-  LWFTP_RESULT_ERR_FILENAME   /** Remote host could not find file */
-};
-
-/** LWFTP control connection state */
-typedef enum  {
-  LWFTP_CLOSED=0,
-  LWFTP_CONNECTED,
-  LWFTP_USER_SENT,
-  LWFTP_PASS_SENT,
-  LWFTP_LOGGED,
-  LWFTP_TYPE_SENT,
-  LWFTP_PASV_SENT,
-  LWFTP_RETR_SENT,
-  LWFTP_STOR_SENT,
-  LWFTP_XFERING,
-  LWFTP_DATAEND,
-  LWFTP_QUIT,
-  LWFTP_QUIT_SENT,
-  LWFTP_CLOSING,
-} lwftp_state_t;
-
-/** LWFTP session structure */
-typedef struct {
-  // User interface
-  ip_addr_t     server_ip;
-  u16_t         server_port;
-  const char    *remote_path;
-  const char    *user;
-  const char    *pass;
-  void          *handle;
-  uint          (*data_source)(void*, const char**, uint);
-  uint          (*data_sink)(void*, const char*, uint);
-  void          (*done_fn)(void*, int);
-  uint          timeout;
-  // Internal data
-  lwftp_state_t   control_state;
-  lwftp_state_t   target_state;
-  lwftp_state_t   data_state;
-  struct tcp_pcb  *control_pcb;
-  struct tcp_pcb  *data_pcb;
-} lwftp_session_t;
-
-// LWFTP API
-err_t lwftp_connect(lwftp_session_t *s);
-err_t lwftp_store(lwftp_session_t *s);
-err_t lwftp_retrieve(lwftp_session_t *s);
-void  lwftp_close(lwftp_session_t *s);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif // LWFTP_H
diff --git a/LWFTP/lwftp.c b/LWFTP/lwftp.c
deleted file mode 100644
index e017475..0000000
--- a/LWFTP/lwftp.c
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- * lwftp_mod.c
- *
- *  Created on: Feb 14, 2024
- *      Author: SeungJu Lim
- */
-#include <lwftp.h>
-#include <string.h>
-#include "lwip/tcp.h"
-#include "lwip/tcpip.h"
-
-/** Enable debugging for LWFTP */
-#ifndef LWFTP_DEBUG
-#define LWFTP_DEBUG   LWIP_DBG_ON
-#endif
-
-#define LWFTP_TRACE   (LWFTP_DEBUG|LWIP_DBG_TRACE)
-#define LWFTP_STATE   (LWFTP_DEBUG|LWIP_DBG_STATE)
-#define LWFTP_WARNING (LWFTP_DEBUG|LWIP_DBG_LEVEL_WARNING)
-#define LWFTP_SERIOUS (LWFTP_DEBUG|LWIP_DBG_LEVEL_SERIOUS)
-#define LWFTP_SEVERE  (LWFTP_DEBUG|LWIP_DBG_LEVEL_SEVERE)
-
-#define LOG_ERROR(format, ...) printf("ERROR: " format "\n", ##__VA_ARGS__)
-#define LOG_TRACE(format, ...) printf("TRACE: " format "\n", ##__VA_ARGS__)
-
-#define PTRNLEN(s)  s,(sizeof(s)-1)
-
-
-err_t lwftp_connect(lwftp_session_t *s) {
-	err_t error;
-	enum lwftp_results retval = LWFTP_RESULT_ERR_UNKNOWN;
-
-	// Check user supplied data
-	if ((s->control_state != LWFTP_CLOSED) || s->control_pcb || s->data_pcb
-			|| !s->user || !s->pass) {
-		LWIP_DEBUGF(LWFTP_WARNING, ("lwftp: invalid control session\n"));
-		retval = LWFTP_RESULT_ERR_ARGUMENT;
-		goto exit;
-	}
-	// Get sessions pcb
-	s->control_pcb = tcp_new();
-	if (!s->control_pcb) {
-		LWIP_DEBUGF(LWFTP_SERIOUS, ("lwftp: cannot alloc control_pcb (low memory?)\n"));
-		retval = LWFTP_RESULT_ERR_MEMORY;
-		goto exit;
-	}
-	// Open control session
-	tcp_arg(s->control_pcb, s);
-	tcp_err(s->control_pcb, lwftp_control_err);
-	tcp_recv(s->control_pcb, lwftp_control_recv);
-	tcp_sent(s->control_pcb, lwftp_control_sent);
-	error = tcp_connect(s->control_pcb, &s->server_ip, s->server_port,
-			lwftp_control_connected);
-	if (error == ERR_OK) {
-		retval = LWFTP_RESULT_INPROGRESS;
-		goto exit;
-	}
-
-	// Release pcbs in case of failure
-	LWIP_DEBUGF(LWFTP_SERIOUS, ("lwftp: cannot connect control_pcb (%s)\n", lwip_strerr(error)));
-	lwftp_control_close(s, -1);
-
-	exit: if (s->done_fn)
-		s->done_fn(s->handle, retval);
-
-	return retval;
-}
-
-//
-//err_t lwftp_store(lwftp_session_t *s) {
-//
-//}
-//err_t lwftp_retrieve(lwftp_session_t *s) {
-//
-//}
-//err_t lwftp_close(lwftp_session_t *s) {
-//
-//}
diff --git a/LWFTP/lwftp_control.c b/LWFTP/lwftp_control.c
deleted file mode 100644
index 76275e7..0000000
--- a/LWFTP/lwftp_control.c
+++ /dev/null
@@ -1,120 +0,0 @@
-/*
- * lwftp_mod.h
- *
- *  Created on: Feb 14, 2024
- *      Author: SeungJu Lim
- */
-
-/** Process newly connected PCB
- * @param pointer to lwftp session data
- * @param pointer to PCB
- * @param state of connection
- */
-static err_t lwftp_control_connected(void *arg, struct tcp_pcb *tpcb, err_t err) {
-	lwftp_session_t *s = (lwftp_session_t*) arg;
-
-	if (err == ERR_OK) {
-		LWIP_DEBUGF(LWFTP_STATE, ("lwftp:connected to server\n"));
-		s->control_state = LWFTP_CONNECTED;
-	} else {
-		LWIP_DEBUGF(LWFTP_WARNING,
-				("lwftp:err in control_connected (%s)\n", lwip_strerr(err)));
-	}
-	return err;
-}
-
-/** Close control connection
- * @param pointer to lwftp session data
- * @param result to pass to callback fn (if called)
- */
-static void lwftp_control_close(lwftp_session_t *s, int result) {
-	if (s->data_pcb) {
-		lwftp_pcb_close(s->data_pcb);
-		s->data_pcb = NULL;
-	}
-	if (s->control_pcb) {
-		lwftp_pcb_close(s->control_pcb);
-		s->control_pcb = NULL;
-	}
-	s->control_state = LWFTP_CLOSED;
-	if ((result >= 0) && s->done_fn) {
-		s->done_fn(s->handle, result);
-	}
-}
-
-/** Process newly connected PCB
- * @param pointer to lwftp session data
- * @param pointer to PCB
- * @param state of connection
- */
-static err_t lwftp_control_connected(void *arg, struct tcp_pcb *tpcb, err_t err) {
-	lwftp_session_t *s = (lwftp_session_t*) arg;
-
-	if (err == ERR_OK) {
-		LWIP_DEBUGF(LWFTP_STATE, ("lwftp: connected to server\n"));
-		s->control_state = LWFTP_CONNECTED;
-	} else {
-		LWIP_DEBUGF(LWFTP_WARNING,
-				("lwftp: err in control_connected (%s)\n", lwip_strerr(err)));
-	}
-	return err;
-}
-
-/** Handle control connection error
- * @param pointer to lwftp session data
- * @param state of connection
- */
-static void lwftp_control_err(void *arg, err_t err) {
-	LWIP_UNUSED_ARG(err);
-	if (arg != NULL) {
-		lwftp_session_t *s = (lwftp_session_t*) arg;
-		int result;
-		if (s->control_state == LWFTP_CLOSED) {
-			LWIP_DEBUGF(LWFTP_WARNING,
-					("lwftp: failed to connect to server (%s)\n", lwip_strerr(err)));
-			result = LWFTP_RESULT_ERR_CONNECT;
-		} else {
-			LWIP_DEBUGF(LWFTP_WARNING, ("lwftp: connection closed by remote host\n"));
-			result = LWFTP_RESULT_ERR_CLOSED;
-		}
-		s->control_pcb = NULL; // No need to de-allocate PCB
-		lwftp_control_close(s, result);
-	}
-}
-
-/** Handle control connection incoming data
- * @param pointer to lwftp session data
- * @param pointer to PCB
- * @param pointer to incoming pbuf
- * @param state of incoming process
- */
-static err_t lwftp_control_recv(void *arg, struct tcp_pcb *tpcb, struct pbuf *p,
-		err_t err) {
-	lwftp_session_t *s = (lwftp_session_t*) arg;
-
-	if (err == ERR_OK) {
-		if (p) {
-			tcp_recved(tpcb, p->tot_len);
-			lwftp_control_process(s, tpcb, p);
-		} else {
-			LWIP_DEBUGF(LWFTP_WARNING, ("lwftp: connection closed by remote host\n"));
-			lwftp_control_close(s, LWFTP_RESULT_ERR_CLOSED);
-		}
-	} else {
-		LWIP_DEBUGF(LWFTP_SERIOUS,
-				("lwftp: failed to receive (%s)\n", lwip_strerr(err)));
-		lwftp_control_close(s, LWFTP_RESULT_ERR_UNKNOWN);
-	}
-	return err;
-}
-
-/** Handle control connection acknowledge of sent data
- * @param pointer to lwftp session data
- * @param pointer to PCB
- * @param number of bytes sent
- */
-static err_t lwftp_control_sent(void *arg, struct tcp_pcb *tpcb, u16_t len) {
-	LWIP_DEBUGF(LWFTP_TRACE, ("lwftp: successfully sent %d bytes\n", len));
-	return ERR_OK;
-}
-
diff --git a/LWFTP/lwftp_pcb.c b/LWFTP/lwftp_pcb.c
deleted file mode 100644
index 3fb952d..0000000
--- a/LWFTP/lwftp_pcb.c
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
- * lwftp_mod.h
- *
- *  Created on: Feb 14, 2024
- *      Author: SeungJu Lim
- */
-
-/** Handle control connection error
- * @param pointer to lwftp session data
- * @param state of connection
- */
-static void lwftp_control_err(void *arg, err_t err) {
-	LWIP_UNUSED_ARG(err);
-	if (arg != NULL) {
-		lwftp_session_t *s = (lwftp_session_t*) arg;
-		int result;
-		if (s->control_state == LWFTP_CLOSED) {
-			LWIP_DEBUGF(LWFTP_WARNING,
-					("lwftp: failed to connect to server (%s)\n", lwip_strerr(err)));
-			result = LWFTP_RESULT_ERR_CONNECT;
-		} else {
-			LWIP_DEBUGF(LWFTP_WARNING, ("lwftp: connection closed by remote host\n"));
-			result = LWFTP_RESULT_ERR_CLOSED;
-		}
-		s->control_pcb = NULL; // No need to de-allocate PCB
-		lwftp_control_close(s, result);
-	}
-}
-
-/** Handle control connection incoming data
- * @param pointer to lwftp session data
- * @param pointer to PCB
- * @param pointer to incoming pbuf
- * @param state of incoming process
- */
-static err_t lwftp_control_recv(void *arg, struct tcp_pcb *tpcb, struct pbuf *p,
-		err_t err) {
-	lwftp_session_t *s = (lwftp_session_t*) arg;
-
-	if (err == ERR_OK) {
-		if (p) {
-			tcp_recved(tpcb, p->tot_len);
-			lwftp_control_process(s, tpcb, p);
-		} else {
-			LWIP_DEBUGF(LWFTP_WARNING, ("lwftp: connection closed by remote host\n"));
-			lwftp_control_close(s, LWFTP_RESULT_ERR_CLOSED);
-		}
-	} else {
-		LWIP_DEBUGF(LWFTP_SERIOUS, ("lwftp: failed to receive (%s)\n",lwip_strerr(err)));
-		lwftp_control_close(s, LWFTP_RESULT_ERR_UNKNOWN);
-	}
-	return err;
-}
-
-/** Handle control connection acknowledge of sent data
- * @param pointer to lwftp session data
- * @param pointer to PCB
- * @param number of bytes sent
- */
-static err_t lwftp_control_sent(void *arg, struct tcp_pcb *tpcb, u16_t len) {
-	LWIP_DEBUGF(LWFTP_TRACE, ("lwftp: successfully sent %d bytes\n",len));
-	return ERR_OK;
-}
-
-/** Close control connection
- * @param pointer to lwftp session data
- * @param result to pass to callback fn (if called)
- */
-static void lwftp_control_close(lwftp_session_t *s, int result) {
-	if (s->data_pcb) {
-		lwftp_pcb_close(s->data_pcb);
-		s->data_pcb = NULL;
-	}
-	if (s->control_pcb) {
-		lwftp_pcb_close(s->control_pcb);
-		s->control_pcb = NULL;
-	}
-	s->control_state = LWFTP_CLOSED;
-	if ((result >= 0) && s->done_fn) {
-		s->done_fn(s->handle, result);
-	}
-}
diff --git a/LWFTPC/lwftpc.c b/LWFTPC/lwftpc.c
new file mode 100644
index 0000000..e0c2357
--- /dev/null
+++ b/LWFTPC/lwftpc.c
@@ -0,0 +1,275 @@
+/*
+ * lwftpc.c
+ *
+ *  Created on: Feb 20, 2024
+ *      Author: "SeungJu Lim"
+ */
+
+#include "lwftpc.h"
+
+
+/** send the data to the connected connection */
+err_t lwftp_send(struct netconn *conn, const char *data) {
+	err_t err = 0;
+	if (strcmp(data, "\r\n") == 0)
+		printf(">> lwftp: ----> send <CRLF>\r\n");
+	else
+		printf(">> lwftp: ----> send %s", data);
+	err = netconn_write(conn, data, strlen(data), NETCONN_COPY);
+#if FTPSemaphore
+	// relaese the semaphore
+	sys_sem_signal(&ftpsem);
+#endif
+	return err;
+}
+
+
+err_t lwftp_data_open(lwftp_session_t *s, const char *response) {
+	err_t err = ERR_VAL;
+	char *ptr;
+	ip_addr_t addr_d;
+
+	ptr = strchr(response, '(');
+	if (ptr) {
+		unsigned int a = strtoul(ptr + 1, &ptr, 10);
+		unsigned int b = strtoul(ptr + 1, &ptr, 10);
+		unsigned int c = strtoul(ptr + 1, &ptr, 10);
+		unsigned int d = strtoul(ptr + 1, &ptr, 10);
+		IP4_ADDR(&addr_d, a, b, c, d);
+
+		s->data_port = strtoul(ptr + 1, &ptr, 10) << 8;
+		s->data_port |= strtoul(ptr + 1, &ptr, 10) & 255;
+		printf(">> lwftp: server data port: '%d'\r\n", s->data_port);
+
+		if (*ptr == ')') {
+			s->data_conn = netconn_new(NETCONN_TCP);
+			if (s->data_conn != NULL) {
+				err = netconn_connect(s->data_conn, &addr_d, s->data_port);
+			} else {
+				err = ERR_MEM;
+			}
+		}
+	} else {
+		err = ERR_BUF;
+	}
+	return err;
+}
+
+/**
+ *=============================================
+ *               Main functions
+ *=============================================
+ */
+
+/* Send data to Server*/
+err_t lwftp_store(lwftp_session_t *s, const char *filename, const char *data) {
+	char cmd[256];
+	err_t err;
+	size_t data_len = strlen(data);
+
+	snprintf(cmd, sizeof(cmd), "STOR %s\r\n", filename);
+	err = lwftp_send(s->conn, cmd);
+	if (err == ERR_OK) {
+		err = netconn_write(s->data_conn, data, data_len, NETCONN_COPY);
+		if (err == ERR_OK) {
+			printf(">> lwftp: data sent successfully\r\n");
+			netconn_close(s->data_conn);
+		}else{
+			printf(">> lwftp: send data failed with code %d\r\n", err);
+		}
+	}else{
+		printf(">> lwftp: send command failed with code %d\r\n", err);
+	}
+	return err;
+}
+
+
+/* Get data from Server*/
+err_t lwftp_retrieve(lwftp_session_t *s, const char *filename) {
+	char cmd[256];
+	err_t err;
+
+	snprintf(cmd, sizeof(cmd), "RETR %s\r\n", filename);
+	err = lwftp_send(s->conn, cmd);
+	if (err == ERR_OK) {
+		printf(">> lwftp: command sent successfully\r\n");
+	} else {
+		printf(">> lwftp: send command failed with code %d\r\n", err);
+	}
+	return err;
+}
+
+/* Get file list from Server*/
+err_t lwftp_list(lwftp_session_t *s) {
+	err_t err;
+
+	err = lwftp_send(s->conn, "LIST\r\n");
+	if (err == ERR_OK) {
+		printf(">> lwftp: command sent successfully\r\n");
+	} else {
+		printf(">> lwftp: send command failed with code %d\r\n", err);
+	}
+	return err;
+}
+
+
+
+void onDataReceived(void *data, size_t size) {
+	osDelay(1000);
+	printf("%s\r\n", (char*) data);
+}
+
+//void lwftp_data_thread(void *arg) {
+//	lwftp_session_t *s = (lwftp_session_t*) arg;
+//	static struct netbuf *d_buf;
+//
+//	while (1) {
+//		if (s->data_conn != NULL && s->data_state == LWFTP_CONNECTED) {
+//			if (netconn_recv(s->data_conn, &d_buf) == ERR_OK) {
+//				void *data;
+//				u16_t len;
+//				do {
+//					netbuf_data(d_buf, &data, &len);
+//				} while (netbuf_next(d_buf) >= 0);
+//				onDataReceived(data, len);
+//			}
+//			if (d_buf != NULL) {
+//				netbuf_delete(d_buf);
+//				d_buf = NULL;
+//			}
+//		}
+//	}
+//}
+
+void lwftp_data_thread(void *arg) {
+	lwftp_session_t *s = (lwftp_session_t*) arg;
+		static struct netbuf *d_buf;
+
+	while (1) {
+		if (s->data_conn != NULL && s->data_state == LWFTP_CONNECTED) {
+			err_t err = netconn_recv(s->data_conn, &d_buf);
+			if (err == ERR_OK && d_buf != NULL) {
+				void *data;
+				u16_t len;
+				do {
+					netbuf_data(d_buf, &data, &len);
+					onDataReceived(data, len);
+				} while (netbuf_next(d_buf) >= 0);
+				netbuf_delete(d_buf);
+			} else {
+			}
+		} else {
+			vTaskDelay(pdMS_TO_TICKS(100));
+		}
+	}
+}
+
+void lwftp_ctrl_thread(void *arg) {
+	lwftp_session_t *s = (lwftp_session_t*) arg;
+
+	static struct netbuf *buf;
+	uint response = 0;
+	char cmd[256];
+	err_t err;
+
+	// check session data invalid
+	if ((s->control_state != LWFTP_CLOSED) || s->conn || s->data_conn || !s->user
+			|| !s->pass) {
+		printf(">> lwftp: invalid session data\r\n");
+		return;
+	}
+
+	s->conn = netconn_new(NETCONN_TCP);
+	s->data_conn = netconn_new(NETCONN_TCP);
+
+	// create a new connection identifier
+	if (s->conn != NULL) {
+		err = netconn_bind(s->conn, &s->cli_ip, 0);
+
+		if (err == ERR_OK) {
+			printf(">> lwftp: client IP bind OK\r\n");
+			err = netconn_connect(s->conn, &s->svr_ip, s->svr_port);
+
+			// If the connection to the server is established, the following will continue, else delete the connection
+			if (err == ERR_OK) {
+				printf(">> lwftp: server connect OK\r\n");
+#if FTPSemaphore
+				// Release the semaphore once the connection is successful
+				sys_sem_signal(&ftpsem);
+#endif
+
+				/**
+				 * =====================
+				 * Response processing
+				 * =====================
+				 */
+				while (1) {
+					/* wait until the data is sent by the server*/
+					if (netconn_recv(s->conn, &buf) == ERR_OK) {
+						if (buf) {
+							response = strtoul(buf->p->payload, NULL, 10);
+							printf("\n>> lwftp: <==== resp '%d'\r\n", response);
+
+							/** [Response 220] Service ready for new user.*/
+							if (response == 220) {
+								snprintf(cmd, sizeof(cmd), "USER %s\r\n", s->user);
+								lwftp_send(s->conn, cmd);
+							}
+							/** [Response 331] User name okay, need password.*/
+							else if (response == 331) {
+								snprintf(cmd, sizeof(cmd), "PASS %s\r\n", s->pass);
+								lwftp_send(s->conn, cmd);
+							}
+							/** [Response 230] User logged in, proceed.*/
+							else if (response == 230) {
+								printf(">> lwftp: now logged in\r\n");
+								lwftp_send(s->conn, "PASV\r\n");
+							}
+
+							/** [Response 227] Entering Passive Mode (h1,h2,h3,h4,p1,p2).*/
+							else if (response == 227) {
+								printf(">> lwftp: entering passive Mode\r\n");
+								err = lwftp_data_open(s, buf->p->payload);
+								if (err != ERR_OK) {
+									printf(">> lwftp: data port connection failed with code %d\r\n",err);
+									goto exit;
+								}
+								s->data_state = LWFTP_CONNECTED;
+								printf(">> lwftp: data port connect OK\r\n");
+							}
+
+							/** [Response 125] Data connection already open; transfer starting.*/
+							else if (response == 125) {
+								printf(">> lwftp: transfer starting.\r\n");
+							}
+
+							/** [Response 226] Closing data connection. Requested file action successful*/
+							else if (response == 226) {
+								printf(">> lwftp: closing data connection.\r\n");
+								printf(">> lwftp: requested file action successful.\r\n");
+							}
+						}
+					}
+					memset(cmd, 0, sizeof(cmd));
+					if (buf != NULL) {
+						netbuf_delete(buf);
+						buf = NULL;
+					}
+				}
+			} else {
+				printf(">> lwftp: server connection failed with code %d\r\n", err);
+				goto exit;
+			}
+		} else {
+			printf(">> lwftp: client IP binding failed with code %d\r\n", err);
+			goto exit;
+		}
+	}
+	exit: if (s->data_conn) {
+		netconn_close(s->data_conn);
+		netconn_delete(s->data_conn);
+	}
+	netconn_close(s->conn);
+	netconn_delete(s->conn);
+	printf(">> lwftp: all ftp connection closed\r\n");
+}
diff --git a/LWFTP/lwftp.h b/LWFTPC/lwftpc.h
similarity index 59%
rename from LWFTP/lwftp.h
rename to LWFTPC/lwftpc.h
index 1a28986..23c18fe 100644
--- a/LWFTP/lwftp.h
+++ b/LWFTPC/lwftpc.h
@@ -1,21 +1,22 @@
 /*
- * lwftp_mod.h
+ * lwftpc.h
  *
- *  Created on: Feb 14, 2024
- *      Author: SeungJu Lim
+ *  Created on: Feb 20, 2024
+ *      Author: "SeungJu Lim"
  */
 
-
-#ifndef LWFTP_H
-#define LWFTP_H
-
-#include "lwip/opt.h"
-#include "lwip/ip.h"
+#include <stdio.h>
+#include <string.h>
+#include "lwip/api.h"
 
 #ifdef __cplusplus
 extern "C" {
 #endif
 
+#ifndef LWFTPC_H_
+#define LWFTPC_H_
+
+
 enum lwftp_results {
   LWFTP_RESULT_OK=0,
   LWFTP_RESULT_INPROGRESS,
@@ -33,7 +34,8 @@ enum lwftp_results {
   LWFTP_RESULT_ERR_FILENAME   /** Remote host could not find file */
 };
 
-/** LWFTP control connection state */
+
+/** LWFTPC control connection state */
 typedef enum  {
   LWFTP_CLOSED=0,
   LWFTP_CONNECTED,
@@ -51,35 +53,41 @@ typedef enum  {
   LWFTP_CLOSING,
 } lwftp_state_t;
 
-/** LWFTP session structure */
+
+/** LWFTPC session structure */
 typedef struct {
   // User interface
-  ip_addr_t     server_ip;
-  u16_t         server_port;
-  const char    *remote_path;
+	ip_addr_t			cli_ip;
+	ip_addr_t			svr_ip;
+  u16_t					svr_port;
+  u16_t         data_port;
   const char    *user;
   const char    *pass;
-  void          *handle;
-  uint          (*data_source)(void*, const char**, uint);
-  uint          (*data_sink)(void*, const char*, uint);
-  void          (*done_fn)(void*, int);
-  uint          timeout;
   // Internal data
   lwftp_state_t   control_state;
-  lwftp_state_t   target_state;
   lwftp_state_t   data_state;
-  struct tcp_pcb  *control_pcb;
-  struct tcp_pcb  *data_pcb;
+  lwftp_state_t   target_state;
+  struct netconn  *conn;
+  struct netconn  *data_conn;
 } lwftp_session_t;
 
-// LWFTP API
-err_t lwftp_connect(lwftp_session_t *s);
-err_t lwftp_store(lwftp_session_t *s);
-err_t lwftp_retrieve(lwftp_session_t *s);
-void  lwftp_close(lwftp_session_t *s);
+
+/** LWFTPC API prototypes*/
+err_t lwftp_send(struct netconn *conn, const char *data);
+err_t lwftp_data_open(lwftp_session_t *s, const char *response);
+void lwftp_data_thread(void *arg);
+void lwftp_ctrl_thread(void *arg);
+
+/** for callback*/
+typedef void (*lwftp_transfer_callback)(err_t result, void *context);
+void onDataReceived(void* data, size_t size);
+err_t lwftp_store(lwftp_session_t *s, const char *filename, const char *data);
+err_t lwftp_retrieve(lwftp_session_t *s, const char *filename);
+err_t lwftp_list(lwftp_session_t *s);
+
 
 #ifdef __cplusplus
 }
 #endif
 
-#endif // LWFTP_H
+#endif /* LWFTPC_H_ */
diff --git a/LWIP/App/lwip.c b/LWIP/App/lwip.c
index 52595a3..44ae6a2 100644
--- a/LWIP/App/lwip.c
+++ b/LWIP/App/lwip.c
@@ -32,14 +32,12 @@
 /* USER CODE END 0 */
 /* Private function prototypes -----------------------------------------------*/
 static void ethernet_link_status_updated(struct netif *netif);
-static void Ethernet_Link_Periodic_Handle(struct netif *netif);
 /* ETH Variables initialization ----------------------------------------------*/
 void Error_Handler(void);
 
 /* USER CODE BEGIN 1 */
 
 /* USER CODE END 1 */
-uint32_t EthernetLinkTimer;
 
 /* Variables Initialization */
 struct netif gnetif;
@@ -74,18 +72,19 @@ void MX_LWIP_Init(void)
   GATEWAY_ADDRESS[3] = 0;
 
 /* USER CODE BEGIN IP_ADDRESSES */
+
 /* USER CODE END IP_ADDRESSES */
 
-  /* Initilialize the LwIP stack without RTOS */
-  lwip_init();
+  /* Initilialize the LwIP stack with RTOS */
+  tcpip_init( NULL, NULL );
 
   /* IP addresses initialization without DHCP (IPv4) */
   IP4_ADDR(&ipaddr, IP_ADDRESS[0], IP_ADDRESS[1], IP_ADDRESS[2], IP_ADDRESS[3]);
   IP4_ADDR(&netmask, NETMASK_ADDRESS[0], NETMASK_ADDRESS[1] , NETMASK_ADDRESS[2], NETMASK_ADDRESS[3]);
   IP4_ADDR(&gw, GATEWAY_ADDRESS[0], GATEWAY_ADDRESS[1], GATEWAY_ADDRESS[2], GATEWAY_ADDRESS[3]);
 
-  /* add the network interface (IPv4/IPv6) without RTOS */
-  netif_add(&gnetif, &ipaddr, &netmask, &gw, NULL, &ethernetif_init, &ethernet_input);
+  /* add the network interface (IPv4/IPv6) with RTOS */
+  netif_add(&gnetif, &ipaddr, &netmask, &gw, NULL, &ethernetif_init, &tcpip_input);
 
   /* Registers the default network interface */
   netif_set_default(&gnetif);
@@ -97,6 +96,10 @@ void MX_LWIP_Init(void)
   netif_set_link_callback(&gnetif, ethernet_link_status_updated);
 
   /* Create the Ethernet link handler thread */
+/* USER CODE BEGIN H7_OS_THREAD_DEF_CREATE_CMSIS_RTOS_V1 */
+  osThreadDef(EthLink, ethernet_link_thread, osPriorityBelowNormal, 0, configMINIMAL_STACK_SIZE *2);
+  osThreadCreate (osThread(EthLink), &gnetif);
+/* USER CODE END H7_OS_THREAD_DEF_CREATE_CMSIS_RTOS_V1 */
 
 /* USER CODE BEGIN 3 */
 
@@ -110,54 +113,6 @@ void MX_LWIP_Init(void)
 /* USER CODE END 4 */
 #endif
 
-/**
-  * @brief  Ethernet Link periodic check
-  * @param  netif
-  * @retval None
-  */
-static void Ethernet_Link_Periodic_Handle(struct netif *netif)
-{
-/* USER CODE BEGIN 4_4_1 */
-/* USER CODE END 4_4_1 */
-
-  /* Ethernet Link every 100ms */
-  if (HAL_GetTick() - EthernetLinkTimer >= 100)
-  {
-    EthernetLinkTimer = HAL_GetTick();
-    ethernet_link_check_state(netif);
-  }
-/* USER CODE BEGIN 4_4 */
-/* USER CODE END 4_4 */
-}
-
-/**
- * ----------------------------------------------------------------------
- * Function given to help user to continue LwIP Initialization
- * Up to user to complete or change this function ...
- * Up to user to call this function in main.c in while (1) of main(void)
- *-----------------------------------------------------------------------
- * Read a received packet from the Ethernet buffers
- * Send it to the lwIP stack for handling
- * Handle timeouts if LWIP_TIMERS is set and without RTOS
- * Handle the llink status if LWIP_NETIF_LINK_CALLBACK is set and without RTOS
- */
-void MX_LWIP_Process(void)
-{
-/* USER CODE BEGIN 4_1 */
-/* USER CODE END 4_1 */
-  ethernetif_input(&gnetif);
-
-/* USER CODE BEGIN 4_2 */
-/* USER CODE END 4_2 */
-  /* Handle timeouts */
-  sys_check_timeouts();
-
-  Ethernet_Link_Periodic_Handle(&gnetif);
-
-/* USER CODE BEGIN 4_3 */
-/* USER CODE END 4_3 */
-}
-
 /**
   * @brief  Notify the User about the network interface config status
   * @param  netif: the network interface
diff --git a/LWIP/App/lwip.h b/LWIP/App/lwip.h
index b14adc0..911bb74 100644
--- a/LWIP/App/lwip.h
+++ b/LWIP/App/lwip.h
@@ -41,7 +41,6 @@
 #endif /* WITH_RTOS */
 
 /* USER CODE BEGIN 0 */
-
 /* USER CODE END 0 */
 
 /* Global Variables ----------------------------------------------------------*/
diff --git a/LWIP/Target/ethernetif.c b/LWIP/Target/ethernetif.c
index 2b51dc5..1d4e6c4 100644
--- a/LWIP/Target/ethernetif.c
+++ b/LWIP/Target/ethernetif.c
@@ -21,8 +21,6 @@
 /* Includes ------------------------------------------------------------------*/
 #include "main.h"
 #include "lwip/opt.h"
-#include "lwip/mem.h"
-#include "lwip/memp.h"
 #include "lwip/timeouts.h"
 #include "netif/ethernet.h"
 #include "netif/etharp.h"
@@ -30,6 +28,8 @@
 #include "ethernetif.h"
 #include "lan8742.h"
 #include <string.h>
+#include "cmsis_os.h"
+#include "lwip/tcpip.h"
 
 /* Within 'USER CODE' section, code will be kept by default at each generation */
 /* USER CODE BEGIN 0 */
@@ -37,7 +37,12 @@
 /* USER CODE END 0 */
 
 /* Private define ------------------------------------------------------------*/
-
+/* The time to block waiting for input. */
+#define TIME_WAITING_FOR_INPUT ( portMAX_DELAY )
+/* USER CODE BEGIN OS_THREAD_STACK_SIZE_WITH_RTOS */
+/* Stack size of the interface thread */
+#define INTERFACE_THREAD_STACK_SIZE ( 350 )
+/* USER CODE END OS_THREAD_STACK_SIZE_WITH_RTOS */
 /* Network interface name */
 #define IFNAME0 's'
 #define IFNAME1 't'
@@ -117,11 +122,15 @@ ETH_DMADescTypeDef DMATxDscrTab[ETH_TX_DESC_CNT] __attribute__((section(".TxDecr
 
 /* USER CODE END 2 */
 
+osSemaphoreId RxPktSemaphore = NULL;   /* Semaphore to signal incoming packets */
+osSemaphoreId TxPktSemaphore = NULL;   /* Semaphore to signal transmit packet complete */
+
 /* Global Ethernet handle */
 ETH_HandleTypeDef heth;
 ETH_TxPacketConfig TxConfig;
 
 /* Private function prototypes -----------------------------------------------*/
+static void ethernetif_input(void const * argument);
 int32_t ETH_PHY_IO_Init(void);
 int32_t ETH_PHY_IO_DeInit (void);
 int32_t ETH_PHY_IO_ReadReg(uint32_t DevAddr, uint32_t RegAddr, uint32_t *pRegVal);
@@ -142,6 +151,37 @@ lan8742_IOCtx_t  LAN8742_IOCtx = {ETH_PHY_IO_Init,
 /* Private functions ---------------------------------------------------------*/
 void pbuf_free_custom(struct pbuf *p);
 
+/**
+  * @brief  Ethernet Rx Transfer completed callback
+  * @param  handlerEth: ETH handler
+  * @retval None
+  */
+void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *handlerEth)
+{
+  osSemaphoreRelease(RxPktSemaphore);
+}
+/**
+  * @brief  Ethernet Tx Transfer completed callback
+  * @param  handlerEth: ETH handler
+  * @retval None
+  */
+void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *handlerEth)
+{
+  osSemaphoreRelease(TxPktSemaphore);
+}
+/**
+  * @brief  Ethernet DMA transfer error callback
+  * @param  handlerEth: ETH handler
+  * @retval None
+  */
+void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *handlerEth)
+{
+  if((HAL_ETH_GetDMAError(handlerEth) & ETH_DMACSR_RBU) == ETH_DMACSR_RBU)
+  {
+     osSemaphoreRelease(RxPktSemaphore);
+  }
+}
+
 /* USER CODE BEGIN 4 */
 
 /* USER CODE END 4 */
@@ -159,6 +199,9 @@ void pbuf_free_custom(struct pbuf *p);
 static void low_level_init(struct netif *netif)
 {
   HAL_StatusTypeDef hal_eth_init_status = HAL_OK;
+  uint32_t duplex, speed = 0;
+  int32_t PHYLinkState = 0;
+  ETH_MACConfigTypeDef MACConf = {0};
   /* Start ETH HAL Init */
 
    uint8_t MACAddr[6] ;
@@ -215,6 +258,24 @@ static void low_level_init(struct netif *netif)
     netif->flags |= NETIF_FLAG_BROADCAST;
   #endif /* LWIP_ARP */
 
+  /* create a binary semaphore used for informing ethernetif of frame reception */
+  osSemaphoreDef(RxSem);
+  RxPktSemaphore = osSemaphoreCreate(osSemaphore(RxSem), 1);
+
+  /* create a binary semaphore used for informing ethernetif of frame transmission */
+  osSemaphoreDef(TxSem);
+  TxPktSemaphore = osSemaphoreCreate(osSemaphore(TxSem), 1);
+
+  /* Decrease the semaphore's initial count from 1 to 0 */
+  osSemaphoreWait(RxPktSemaphore, 0);
+  osSemaphoreWait(TxPktSemaphore, 0);
+
+  /* create the task that handles the ETH_MAC */
+/* USER CODE BEGIN OS_THREAD_DEF_CREATE_CMSIS_RTOS_V1 */
+  osThreadDef(EthIf, ethernetif_input, osPriorityRealtime, 0, INTERFACE_THREAD_STACK_SIZE);
+  osThreadCreate (osThread(EthIf), netif);
+/* USER CODE END OS_THREAD_DEF_CREATE_CMSIS_RTOS_V1 */
+
 /* USER CODE BEGIN PHY_PRE_CONFIG */
 
 /* USER CODE END PHY_PRE_CONFIG */
@@ -226,8 +287,55 @@ static void low_level_init(struct netif *netif)
 
   if (hal_eth_init_status == HAL_OK)
   {
-  /* Get link state */
-  ethernet_link_check_state(netif);
+    PHYLinkState = LAN8742_GetLinkState(&LAN8742);
+
+    /* Get link state */
+    if(PHYLinkState <= LAN8742_STATUS_LINK_DOWN)
+    {
+      netif_set_link_down(netif);
+      netif_set_down(netif);
+    }
+    else
+    {
+      switch (PHYLinkState)
+      {
+      case LAN8742_STATUS_100MBITS_FULLDUPLEX:
+        duplex = ETH_FULLDUPLEX_MODE;
+        speed = ETH_SPEED_100M;
+        break;
+      case LAN8742_STATUS_100MBITS_HALFDUPLEX:
+        duplex = ETH_HALFDUPLEX_MODE;
+        speed = ETH_SPEED_100M;
+        break;
+      case LAN8742_STATUS_10MBITS_FULLDUPLEX:
+        duplex = ETH_FULLDUPLEX_MODE;
+        speed = ETH_SPEED_10M;
+        break;
+      case LAN8742_STATUS_10MBITS_HALFDUPLEX:
+        duplex = ETH_HALFDUPLEX_MODE;
+        speed = ETH_SPEED_10M;
+        break;
+      default:
+        duplex = ETH_FULLDUPLEX_MODE;
+        speed = ETH_SPEED_100M;
+        break;
+      }
+
+    /* Get MAC Config MAC */
+    HAL_ETH_GetMACConfig(&heth, &MACConf);
+    MACConf.DuplexMode = duplex;
+    MACConf.Speed = speed;
+    HAL_ETH_SetMACConfig(&heth, &MACConf);
+
+    HAL_ETH_Start_IT(&heth);
+    netif_set_up(netif);
+    netif_set_link_up(netif);
+
+/* USER CODE BEGIN PHY_POST_CONFIG */
+
+/* USER CODE END PHY_POST_CONFIG */
+    }
+
   }
   else
   {
@@ -290,7 +398,18 @@ static err_t low_level_output(struct netif *netif, struct pbuf *p)
   TxConfig.TxBuffer = Txbuffer;
   TxConfig.pData = p;
 
-  HAL_ETH_Transmit(&heth, &TxConfig, ETH_DMA_TRANSMIT_TIMEOUT);
+  pbuf_ref(p);
+
+  if (HAL_ETH_Transmit_IT(&heth, &TxConfig) == HAL_OK) {
+    while(osSemaphoreWait(TxPktSemaphore, TIME_WAITING_FOR_INPUT)!=osOK)
+
+    {
+    }
+
+    HAL_ETH_ReleaseTxPacket(&heth);
+  } else {
+    pbuf_free(p);
+  }
 
   return errval;
 }
@@ -324,21 +443,28 @@ static struct pbuf * low_level_input(struct netif *netif)
  *
  * @param netif the lwip network interface structure for this ethernetif
  */
-void ethernetif_input(struct netif *netif)
+static void ethernetif_input(void const * argument)
 {
   struct pbuf *p = NULL;
+  struct netif *netif = (struct netif *) argument;
 
-  do
+  for( ;; )
   {
-    p = low_level_input( netif );
-    if (p != NULL)
+    if (osSemaphoreWait(RxPktSemaphore, TIME_WAITING_FOR_INPUT) == osOK)
     {
-      if (netif->input( p, netif) != ERR_OK )
+      do
       {
-        pbuf_free(p);
-      }
+        p = low_level_input( netif );
+        if (p != NULL)
+        {
+          if (netif->input( p, netif) != ERR_OK )
+          {
+            pbuf_free(p);
+          }
+        }
+      } while(p!=NULL);
     }
-  } while(p!=NULL);
+  }
 }
 
 #if !LWIP_ARP
@@ -436,6 +562,7 @@ void pbuf_free_custom(struct pbuf *p)
   if (RxAllocStatus == RX_ALLOC_ERROR)
   {
     RxAllocStatus = RX_ALLOC_OK;
+    osSemaphoreRelease(RxPktSemaphore);
   }
 }
 
@@ -509,7 +636,7 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef* ethHandle)
     HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
 
     /* Peripheral interrupt init */
-    HAL_NVIC_SetPriority(ETH_IRQn, 0, 0);
+    HAL_NVIC_SetPriority(ETH_IRQn, 5, 0);
     HAL_NVIC_EnableIRQ(ETH_IRQn);
   /* USER CODE BEGIN ETH_MspInit 1 */
 
@@ -632,17 +759,25 @@ int32_t ETH_PHY_IO_GetTick(void)
   * @brief  Check the ETH link state then update ETH driver and netif link accordingly.
   * @retval None
   */
-void ethernet_link_check_state(struct netif *netif)
+
+void ethernet_link_thread(void const * argument)
 {
   ETH_MACConfigTypeDef MACConf = {0};
   int32_t PHYLinkState = 0;
   uint32_t linkchanged = 0U, speed = 0U, duplex = 0U;
 
+  struct netif *netif = (struct netif *) argument;
+/* USER CODE BEGIN ETH link init */
+
+/* USER CODE END ETH link init */
+
+  for(;;)
+  {
   PHYLinkState = LAN8742_GetLinkState(&LAN8742);
 
   if(netif_is_link_up(netif) && (PHYLinkState <= LAN8742_STATUS_LINK_DOWN))
   {
-    HAL_ETH_Stop(&heth);
+    HAL_ETH_Stop_IT(&heth);
     netif_set_down(netif);
     netif_set_link_down(netif);
   }
@@ -681,12 +816,18 @@ void ethernet_link_check_state(struct netif *netif)
       MACConf.DuplexMode = duplex;
       MACConf.Speed = speed;
       HAL_ETH_SetMACConfig(&heth, &MACConf);
-      HAL_ETH_Start(&heth);
+      HAL_ETH_Start_IT(&heth);
       netif_set_up(netif);
       netif_set_link_up(netif);
     }
   }
 
+/* USER CODE BEGIN ETH link Thread core code for User BSP */
+
+/* USER CODE END ETH link Thread core code for User BSP */
+
+    osDelay(100);
+  }
 }
 
 void HAL_ETH_RxAllocateCallback(uint8_t **buff)
diff --git a/LWIP/Target/ethernetif.h b/LWIP/Target/ethernetif.h
index 230fd62..cc2aff0 100644
--- a/LWIP/Target/ethernetif.h
+++ b/LWIP/Target/ethernetif.h
@@ -23,6 +23,7 @@
 
 #include "lwip/err.h"
 #include "lwip/netif.h"
+#include "cmsis_os.h"
 
 /* Within 'USER CODE' section, code will be kept by default at each generation */
 /* USER CODE BEGIN 0 */
@@ -32,8 +33,7 @@
 /* Exported functions ------------------------------------------------------- */
 err_t ethernetif_init(struct netif *netif);
 
-void ethernetif_input(struct netif *netif);
-void ethernet_link_check_state(struct netif *netif);
+void ethernet_link_thread(void const * argument);
 
 void Error_Handler(void);
 u32_t sys_jiffies(void);
diff --git a/LWIP/Target/lwipopts.h b/LWIP/Target/lwipopts.h
index 59e029b..82f7b20 100644
--- a/LWIP/Target/lwipopts.h
+++ b/LWIP/Target/lwipopts.h
@@ -36,7 +36,7 @@
 //#define UDP_DEBUG  LWIP_DBG_ON
 #define MEMP_DEBUG LWIP_DBG_ON
 #define MEM_DEBUG LWIP_DBG_ON
-#define ICMP_DEBUG LWIP_DBG_ON
+//#define ICMP_DEBUG LWIP_DBG_ON
 /* USER CODE END 0 */
 
 #ifdef __cplusplus
@@ -45,8 +45,8 @@
 
 /* STM32CubeMX Specific Parameters (not defined in opt.h) ---------------------*/
 /* Parameters set in STM32CubeMX LwIP Configuration GUI -*/
-/*----- WITH_RTOS disabled (Since FREERTOS is not set) -----*/
-#define WITH_RTOS 0
+/*----- WITH_RTOS enabled (Since FREERTOS is set) -----*/
+#define WITH_RTOS 1
 /*----- CHECKSUM_BY_HARDWARE enabled -----*/
 #define CHECKSUM_BY_HARDWARE 1
 /*-----------------------------------------------------------------------------*/
@@ -55,10 +55,6 @@
 /* Parameters set in STM32CubeMX LwIP Configuration GUI -*/
 /*----- Default value in ETH configuration GUI in CubeMx: 1524 -----*/
 #define ETH_RX_BUFFER_SIZE 1536
-/*----- Value in opt.h for NO_SYS: 0 -----*/
-#define NO_SYS 1
-/*----- Value in opt.h for SYS_LIGHTWEIGHT_PROT: 1 -----*/
-#define SYS_LIGHTWEIGHT_PROT 0
 /*----- Value in opt.h for MEM_ALIGNMENT: 1 -----*/
 #define MEM_ALIGNMENT 4
 /*----- Default Value for MEM_SIZE: 1600 ---*/
@@ -71,20 +67,34 @@
 #define LWIP_ETHERNET 1
 /*----- Value in opt.h for LWIP_DNS_SECURE: (LWIP_DNS_SECURE_RAND_XID | LWIP_DNS_SECURE_NO_MULTIPLE_OUTSTANDING | LWIP_DNS_SECURE_RAND_SRC_PORT) -*/
 #define LWIP_DNS_SECURE 7
-/*----- Value in opt.h for TCP_SND_QUEUELEN: (4*TCP_SND_BUF + (TCP_MSS - 1))/TCP_MSS -----*/
-#define TCP_SND_QUEUELEN 9
-/*----- Value in opt.h for TCP_SNDLOWAT: LWIP_MIN(LWIP_MAX(((TCP_SND_BUF)/2), (2 * TCP_MSS) + 1), (TCP_SND_BUF) - 1) -*/
-#define TCP_SNDLOWAT 1071
-/*----- Value in opt.h for TCP_SNDQUEUELOWAT: LWIP_MAX(TCP_SND_QUEUELEN)/2, 5) -*/
-#define TCP_SNDQUEUELOWAT 5
-/*----- Value in opt.h for TCP_WND_UPDATE_THRESHOLD: LWIP_MIN(TCP_WND/4, TCP_MSS*4) -----*/
-#define TCP_WND_UPDATE_THRESHOLD 536
+/*----- Default Value for TCP_MSS: 536 ---*/
+#define TCP_MSS 1460
+/*----- Default Value for TCP_SND_BUF: 2920 ---*/
+#define TCP_SND_BUF 5840
+/*----- Default Value for TCP_SND_QUEUELEN: 17 ---*/
+#define TCP_SND_QUEUELEN 16
 /*----- Value in opt.h for LWIP_NETIF_LINK_CALLBACK: 0 -----*/
 #define LWIP_NETIF_LINK_CALLBACK 1
-/*----- Value in opt.h for LWIP_NETCONN: 1 -----*/
-#define LWIP_NETCONN 0
-/*----- Value in opt.h for LWIP_SOCKET: 1 -----*/
-#define LWIP_SOCKET 0
+/*----- Value in opt.h for TCPIP_THREAD_STACKSIZE: 0 -----*/
+#define TCPIP_THREAD_STACKSIZE 1024
+/*----- Value in opt.h for TCPIP_THREAD_PRIO: 1 -----*/
+#define TCPIP_THREAD_PRIO osPriorityNormal
+/*----- Value in opt.h for TCPIP_MBOX_SIZE: 0 -----*/
+#define TCPIP_MBOX_SIZE 6
+/*----- Value in opt.h for SLIPIF_THREAD_STACKSIZE: 0 -----*/
+#define SLIPIF_THREAD_STACKSIZE 1024
+/*----- Value in opt.h for SLIPIF_THREAD_PRIO: 1 -----*/
+#define SLIPIF_THREAD_PRIO 3
+/*----- Value in opt.h for DEFAULT_THREAD_STACKSIZE: 0 -----*/
+#define DEFAULT_THREAD_STACKSIZE 2048
+/*----- Value in opt.h for DEFAULT_THREAD_PRIO: 1 -----*/
+#define DEFAULT_THREAD_PRIO 3
+/*----- Value in opt.h for DEFAULT_UDP_RECVMBOX_SIZE: 0 -----*/
+#define DEFAULT_UDP_RECVMBOX_SIZE 6
+/*----- Value in opt.h for DEFAULT_TCP_RECVMBOX_SIZE: 0 -----*/
+#define DEFAULT_TCP_RECVMBOX_SIZE 6
+/*----- Value in opt.h for DEFAULT_ACCEPTMBOX_SIZE: 0 -----*/
+#define DEFAULT_ACCEPTMBOX_SIZE 6
 /*----- Value in opt.h for RECV_BUFSIZE_DEFAULT: INT_MAX -----*/
 #define RECV_BUFSIZE_DEFAULT 2000000000
 /*----- Value in opt.h for LWIP_STATS: 1 -----*/
diff --git a/Middlewares/Third_Party/FatFs/src/diskio.c b/Middlewares/Third_Party/FatFs/src/diskio.c
new file mode 100644
index 0000000..5cf8edf
--- /dev/null
+++ b/Middlewares/Third_Party/FatFs/src/diskio.c
@@ -0,0 +1,141 @@
+/*-----------------------------------------------------------------------*/
+/* Low level disk I/O module skeleton for FatFs     (C)ChaN, 2017        */
+/*                                                                       */
+/*   Portions COPYRIGHT 2017 STMicroelectronics                          */
+/*   Portions Copyright (C) 2017, ChaN, all right reserved               */
+/*-----------------------------------------------------------------------*/
+/* If a working storage control module is available, it should be        */
+/* attached to the FatFs via a glue function rather than modifying it.   */
+/* This is an example of glue functions to attach various existing      */
+/* storage control modules to the FatFs module with a defined API.       */
+/*-----------------------------------------------------------------------*/
+
+/* Includes ------------------------------------------------------------------*/
+#include "diskio.h"
+#include "ff_gen_drv.h"
+
+#if defined ( __GNUC__ )
+#ifndef __weak
+#define __weak __attribute__((weak))
+#endif
+#endif
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+extern Disk_drvTypeDef  disk;
+
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/**
+  * @brief  Gets Disk Status
+  * @param  pdrv: Physical drive number (0..)
+  * @retval DSTATUS: Operation status
+  */
+DSTATUS disk_status (
+	BYTE pdrv		/* Physical drive number to identify the drive */
+)
+{
+  DSTATUS stat;
+
+  stat = disk.drv[pdrv]->disk_status(disk.lun[pdrv]);
+  return stat;
+}
+
+/**
+  * @brief  Initializes a Drive
+  * @param  pdrv: Physical drive number (0..)
+  * @retval DSTATUS: Operation status
+  */
+DSTATUS disk_initialize (
+	BYTE pdrv				/* Physical drive nmuber to identify the drive */
+)
+{
+  DSTATUS stat = RES_OK;
+
+  if(disk.is_initialized[pdrv] == 0)
+  {
+    disk.is_initialized[pdrv] = 1;
+    stat = disk.drv[pdrv]->disk_initialize(disk.lun[pdrv]);
+  }
+  return stat;
+}
+
+/**
+  * @brief  Reads Sector(s)
+  * @param  pdrv: Physical drive number (0..)
+  * @param  *buff: Data buffer to store read data
+  * @param  sector: Sector address (LBA)
+  * @param  count: Number of sectors to read (1..128)
+  * @retval DRESULT: Operation result
+  */
+DRESULT disk_read (
+	BYTE pdrv,		/* Physical drive nmuber to identify the drive */
+	BYTE *buff,		/* Data buffer to store read data */
+	DWORD sector,	        /* Sector address in LBA */
+	UINT count		/* Number of sectors to read */
+)
+{
+  DRESULT res;
+
+  res = disk.drv[pdrv]->disk_read(disk.lun[pdrv], buff, sector, count);
+  return res;
+}
+
+/**
+  * @brief  Writes Sector(s)
+  * @param  pdrv: Physical drive number (0..)
+  * @param  *buff: Data to be written
+  * @param  sector: Sector address (LBA)
+  * @param  count: Number of sectors to write (1..128)
+  * @retval DRESULT: Operation result
+  */
+#if _USE_WRITE == 1
+DRESULT disk_write (
+	BYTE pdrv,		/* Physical drive nmuber to identify the drive */
+	const BYTE *buff,	/* Data to be written */
+	DWORD sector,		/* Sector address in LBA */
+	UINT count        	/* Number of sectors to write */
+)
+{
+  DRESULT res;
+
+  res = disk.drv[pdrv]->disk_write(disk.lun[pdrv], buff, sector, count);
+  return res;
+}
+#endif /* _USE_WRITE == 1 */
+
+/**
+  * @brief  I/O control operation
+  * @param  pdrv: Physical drive number (0..)
+  * @param  cmd: Control code
+  * @param  *buff: Buffer to send/receive control data
+  * @retval DRESULT: Operation result
+  */
+#if _USE_IOCTL == 1
+DRESULT disk_ioctl (
+	BYTE pdrv,		/* Physical drive nmuber (0..) */
+	BYTE cmd,		/* Control code */
+	void *buff		/* Buffer to send/receive control data */
+)
+{
+  DRESULT res;
+
+  res = disk.drv[pdrv]->disk_ioctl(disk.lun[pdrv], cmd, buff);
+  return res;
+}
+#endif /* _USE_IOCTL == 1 */
+
+/**
+  * @brief  Gets Time from RTC
+  * @param  None
+  * @retval Time in DWORD
+  */
+__weak DWORD get_fattime (void)
+{
+  return 0;
+}
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Middlewares/Third_Party/FatFs/src/diskio.h b/Middlewares/Third_Party/FatFs/src/diskio.h
new file mode 100644
index 0000000..5b61e57
--- /dev/null
+++ b/Middlewares/Third_Party/FatFs/src/diskio.h
@@ -0,0 +1,80 @@
+/*-----------------------------------------------------------------------/
+/  Low level disk interface modlue include file   (C)ChaN, 2014          /
+/-----------------------------------------------------------------------*/
+
+#ifndef _DISKIO_DEFINED
+#define _DISKIO_DEFINED
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define _USE_WRITE	1	/* 1: Enable disk_write function */
+#define _USE_IOCTL	1	/* 1: Enable disk_ioctl function */
+
+#include "integer.h"
+
+
+/* Status of Disk Functions */
+typedef BYTE	DSTATUS;
+
+/* Results of Disk Functions */
+typedef enum {
+	RES_OK = 0,		/* 0: Successful */
+	RES_ERROR,		/* 1: R/W Error */
+	RES_WRPRT,		/* 2: Write Protected */
+	RES_NOTRDY,		/* 3: Not Ready */
+	RES_PARERR		/* 4: Invalid Parameter */
+} DRESULT;
+
+
+/*---------------------------------------*/
+/* Prototypes for disk control functions */
+
+
+DSTATUS disk_initialize (BYTE pdrv);
+DSTATUS disk_status (BYTE pdrv);
+DRESULT disk_read (BYTE pdrv, BYTE* buff, DWORD sector, UINT count);
+DRESULT disk_write (BYTE pdrv, const BYTE* buff, DWORD sector, UINT count);
+DRESULT disk_ioctl (BYTE pdrv, BYTE cmd, void* buff);
+DWORD get_fattime (void);
+
+/* Disk Status Bits (DSTATUS) */
+
+#define STA_NOINIT		0x01	/* Drive not initialized */
+#define STA_NODISK		0x02	/* No medium in the drive */
+#define STA_PROTECT		0x04	/* Write protected */
+
+
+/* Command code for disk_ioctrl fucntion */
+
+/* Generic command (Used by FatFs) */
+#define CTRL_SYNC		0	/* Complete pending write process (needed at _FS_READONLY == 0) */
+#define GET_SECTOR_COUNT	1	/* Get media size (needed at _USE_MKFS == 1) */
+#define GET_SECTOR_SIZE		2	/* Get sector size (needed at _MAX_SS != _MIN_SS) */
+#define GET_BLOCK_SIZE		3	/* Get erase block size (needed at _USE_MKFS == 1) */
+#define CTRL_TRIM		4	/* Inform device that the data on the block of sectors is no longer used (needed at _USE_TRIM == 1) */
+
+/* Generic command (Not used by FatFs) */
+#define CTRL_POWER			5	/* Get/Set power status */
+#define CTRL_LOCK			6	/* Lock/Unlock media removal */
+#define CTRL_EJECT			7	/* Eject media */
+#define CTRL_FORMAT			8	/* Create physical format on the media */
+
+/* MMC/SDC specific ioctl command */
+#define MMC_GET_TYPE		10	/* Get card type */
+#define MMC_GET_CSD			11	/* Get CSD */
+#define MMC_GET_CID			12	/* Get CID */
+#define MMC_GET_OCR			13	/* Get OCR */
+#define MMC_GET_SDSTAT		14	/* Get SD status */
+
+/* ATA/CF specific ioctl command */
+#define ATA_GET_REV			20	/* Get F/W revision */
+#define ATA_GET_MODEL		21	/* Get model name */
+#define ATA_GET_SN			22	/* Get serial number */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/Middlewares/Third_Party/FatFs/src/ff.c b/Middlewares/Third_Party/FatFs/src/ff.c
new file mode 100644
index 0000000..b0bd436
--- /dev/null
+++ b/Middlewares/Third_Party/FatFs/src/ff.c
@@ -0,0 +1,6140 @@
+/*----------------------------------------------------------------------------/
+/  FatFs - Generic FAT file system module  R0.12c                             /
+/-----------------------------------------------------------------------------/
+/
+/ Copyright (C) 2017, ChaN, all right reserved.
+/
+/ FatFs module is an open source software. Redistribution and use of FatFs in
+/ source and binary forms, with or without modification, are permitted provided
+/ that the following condition is met:
+/
+/ 1. Redistributions of source code must retain the above copyright notice,
+/    this condition and the following disclaimer.
+/
+/ This software is provided by the copyright holder and contributors "AS IS"
+/ and any warranties related to this software are DISCLAIMED.
+/ The copyright owner or contributors be NOT LIABLE for any damages caused
+/ by use of this software.
+/----------------------------------------------------------------------------*/
+
+
+#include "ff.h"			/* Declarations of FatFs API */
+#include "diskio.h"		/* Declarations of device I/O functions */
+
+
+/*--------------------------------------------------------------------------
+
+   Module Private Definitions
+
+---------------------------------------------------------------------------*/
+
+#if _FATFS != 68300	/* Revision ID */
+#error Wrong include file (ff.h).
+#endif
+
+
+/* DBCS code ranges and SBCS upper conversion tables */
+
+#if _CODE_PAGE == 932	/* Japanese Shift-JIS */
+#define _DF1S	0x81	/* DBC 1st byte range 1 start */
+#define _DF1E	0x9F	/* DBC 1st byte range 1 end */
+#define _DF2S	0xE0	/* DBC 1st byte range 2 start */
+#define _DF2E	0xFC	/* DBC 1st byte range 2 end */
+#define _DS1S	0x40	/* DBC 2nd byte range 1 start */
+#define _DS1E	0x7E	/* DBC 2nd byte range 1 end */
+#define _DS2S	0x80	/* DBC 2nd byte range 2 start */
+#define _DS2E	0xFC	/* DBC 2nd byte range 2 end */
+
+#elif _CODE_PAGE == 936	/* Simplified Chinese GBK */
+#define _DF1S	0x81
+#define _DF1E	0xFE
+#define _DS1S	0x40
+#define _DS1E	0x7E
+#define _DS2S	0x80
+#define _DS2E	0xFE
+
+#elif _CODE_PAGE == 949	/* Korean */
+#define _DF1S	0x81
+#define _DF1E	0xFE
+#define _DS1S	0x41
+#define _DS1E	0x5A
+#define _DS2S	0x61
+#define _DS2E	0x7A
+#define _DS3S	0x81
+#define _DS3E	0xFE
+
+#elif _CODE_PAGE == 950	/* Traditional Chinese Big5 */
+#define _DF1S	0x81
+#define _DF1E	0xFE
+#define _DS1S	0x40
+#define _DS1E	0x7E
+#define _DS2S	0xA1
+#define _DS2E	0xFE
+
+#elif _CODE_PAGE == 437	/* U.S. */
+#define _DF1S	0
+#define _EXCVT {0x80,0x9A,0x45,0x41,0x8E,0x41,0x8F,0x80,0x45,0x45,0x45,0x49,0x49,0x49,0x8E,0x8F, \
+				0x90,0x92,0x92,0x4F,0x99,0x4F,0x55,0x55,0x59,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+				0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \
+				0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
+				0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \
+				0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 720	/* Arabic */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \
+				0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+				0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \
+				0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
+				0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \
+				0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 737	/* Greek */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \
+				0x90,0x92,0x92,0x93,0x94,0x95,0x96,0x97,0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87, \
+				0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0xAA,0x92,0x93,0x94,0x95,0x96, \
+				0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
+				0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0x97,0xEA,0xEB,0xEC,0xE4,0xED,0xEE,0xEF,0xF5,0xF0,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \
+				0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 771	/* KBL */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \
+				0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+				0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \
+				0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
+				0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDC,0xDE,0xDE, \
+				0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+				0xF0,0xF0,0xF2,0xF2,0xF4,0xF4,0xF6,0xF6,0xF8,0xF8,0xFA,0xFA,0xFC,0xFC,0xFE,0xFF}
+
+#elif _CODE_PAGE == 775	/* Baltic */
+#define _DF1S	0
+#define _EXCVT {0x80,0x9A,0x91,0xA0,0x8E,0x95,0x8F,0x80,0xAD,0xED,0x8A,0x8A,0xA1,0x8D,0x8E,0x8F, \
+				0x90,0x92,0x92,0xE2,0x99,0x95,0x96,0x97,0x97,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9F, \
+				0xA0,0xA1,0xE0,0xA3,0xA3,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \
+				0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
+				0xB5,0xB6,0xB7,0xB8,0xBD,0xBE,0xC6,0xC7,0xA5,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE3,0xE8,0xE8,0xEA,0xEA,0xEE,0xED,0xEE,0xEF, \
+				0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 850	/* Latin 1 */
+#define _DF1S	0
+#define _EXCVT {0x43,0x55,0x45,0x41,0x41,0x41,0x41,0x43,0x45,0x45,0x45,0x49,0x49,0x49,0x41,0x41, \
+				0x45,0x92,0x92,0x4F,0x4F,0x4F,0x55,0x55,0x59,0x4F,0x55,0x4F,0x9C,0x4F,0x9E,0x9F, \
+				0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \
+				0xB0,0xB1,0xB2,0xB3,0xB4,0x41,0x41,0x41,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0x41,0x41,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
+				0xD1,0xD1,0x45,0x45,0x45,0x49,0x49,0x49,0x49,0xD9,0xDA,0xDB,0xDC,0xDD,0x49,0xDF, \
+				0x4F,0xE1,0x4F,0x4F,0x4F,0x4F,0xE6,0xE8,0xE8,0x55,0x55,0x55,0x59,0x59,0xEE,0xEF, \
+				0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 852	/* Latin 2 */
+#define _DF1S	0
+#define _EXCVT {0x80,0x9A,0x90,0xB6,0x8E,0xDE,0x8F,0x80,0x9D,0xD3,0x8A,0x8A,0xD7,0x8D,0x8E,0x8F, \
+				0x90,0x91,0x91,0xE2,0x99,0x95,0x95,0x97,0x97,0x99,0x9A,0x9B,0x9B,0x9D,0x9E,0xAC, \
+				0xB5,0xD6,0xE0,0xE9,0xA4,0xA4,0xA6,0xA6,0xA8,0xA8,0xAA,0x8D,0xAC,0xB8,0xAE,0xAF, \
+				0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBD,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC6,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
+				0xD1,0xD1,0xD2,0xD3,0xD2,0xD5,0xD6,0xD7,0xB7,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xE0,0xE1,0xE2,0xE3,0xE3,0xD5,0xE6,0xE6,0xE8,0xE9,0xE8,0xEB,0xED,0xED,0xDD,0xEF, \
+				0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xEB,0xFC,0xFC,0xFE,0xFF}
+
+#elif _CODE_PAGE == 855	/* Cyrillic */
+#define _DF1S	0
+#define _EXCVT {0x81,0x81,0x83,0x83,0x85,0x85,0x87,0x87,0x89,0x89,0x8B,0x8B,0x8D,0x8D,0x8F,0x8F, \
+				0x91,0x91,0x93,0x93,0x95,0x95,0x97,0x97,0x99,0x99,0x9B,0x9B,0x9D,0x9D,0x9F,0x9F, \
+				0xA1,0xA1,0xA3,0xA3,0xA5,0xA5,0xA7,0xA7,0xA9,0xA9,0xAB,0xAB,0xAD,0xAD,0xAE,0xAF, \
+				0xB0,0xB1,0xB2,0xB3,0xB4,0xB6,0xB6,0xB8,0xB8,0xB9,0xBA,0xBB,0xBC,0xBE,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
+				0xD1,0xD1,0xD3,0xD3,0xD5,0xD5,0xD7,0xD7,0xDD,0xD9,0xDA,0xDB,0xDC,0xDD,0xE0,0xDF, \
+				0xE0,0xE2,0xE2,0xE4,0xE4,0xE6,0xE6,0xE8,0xE8,0xEA,0xEA,0xEC,0xEC,0xEE,0xEE,0xEF, \
+				0xF0,0xF2,0xF2,0xF4,0xF4,0xF6,0xF6,0xF8,0xF8,0xFA,0xFA,0xFC,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 857	/* Turkish */
+#define _DF1S	0
+#define _EXCVT {0x80,0x9A,0x90,0xB6,0x8E,0xB7,0x8F,0x80,0xD2,0xD3,0xD4,0xD8,0xD7,0x49,0x8E,0x8F, \
+				0x90,0x92,0x92,0xE2,0x99,0xE3,0xEA,0xEB,0x98,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9E, \
+				0xB5,0xD6,0xE0,0xE9,0xA5,0xA5,0xA6,0xA6,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \
+				0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
+				0xD0,0xD1,0xD2,0xD3,0xD4,0x49,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xDE,0xED,0xEE,0xEF, \
+				0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 860	/* Portuguese */
+#define _DF1S	0
+#define _EXCVT {0x80,0x9A,0x90,0x8F,0x8E,0x91,0x86,0x80,0x89,0x89,0x92,0x8B,0x8C,0x98,0x8E,0x8F, \
+				0x90,0x91,0x92,0x8C,0x99,0xA9,0x96,0x9D,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+				0x86,0x8B,0x9F,0x96,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \
+				0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
+				0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \
+				0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 861	/* Icelandic */
+#define _DF1S	0
+#define _EXCVT {0x80,0x9A,0x90,0x41,0x8E,0x41,0x8F,0x80,0x45,0x45,0x45,0x8B,0x8B,0x8D,0x8E,0x8F, \
+				0x90,0x92,0x92,0x4F,0x99,0x8D,0x55,0x97,0x97,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9F, \
+				0xA4,0xA5,0xA6,0xA7,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \
+				0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
+				0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \
+				0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 862	/* Hebrew */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \
+				0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+				0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \
+				0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
+				0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \
+				0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 863	/* Canadian-French */
+#define _DF1S	0
+#define _EXCVT {0x43,0x55,0x45,0x41,0x41,0x41,0x86,0x43,0x45,0x45,0x45,0x49,0x49,0x8D,0x41,0x8F, \
+				0x45,0x45,0x45,0x4F,0x45,0x49,0x55,0x55,0x98,0x4F,0x55,0x9B,0x9C,0x55,0x55,0x9F, \
+				0xA0,0xA1,0x4F,0x55,0xA4,0xA5,0xA6,0xA7,0x49,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \
+				0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
+				0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \
+				0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 864	/* Arabic */
+#define _DF1S	0
+#define _EXCVT {0x80,0x9A,0x45,0x41,0x8E,0x41,0x8F,0x80,0x45,0x45,0x45,0x49,0x49,0x49,0x8E,0x8F, \
+				0x90,0x92,0x92,0x4F,0x99,0x4F,0x55,0x55,0x59,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+				0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \
+				0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
+				0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \
+				0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 865	/* Nordic */
+#define _DF1S	0
+#define _EXCVT {0x80,0x9A,0x90,0x41,0x8E,0x41,0x8F,0x80,0x45,0x45,0x45,0x49,0x49,0x49,0x8E,0x8F, \
+				0x90,0x92,0x92,0x4F,0x99,0x4F,0x55,0x55,0x59,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+				0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \
+				0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
+				0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \
+				0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 866	/* Russian */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \
+				0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+				0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \
+				0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
+				0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+				0xF0,0xF0,0xF2,0xF2,0xF4,0xF4,0xF6,0xF6,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 869	/* Greek 2 */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \
+				0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x86,0x9C,0x8D,0x8F,0x90, \
+				0x91,0x90,0x92,0x95,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \
+				0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
+				0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xA4,0xA5,0xA6,0xD9,0xDA,0xDB,0xDC,0xA7,0xA8,0xDF, \
+				0xA9,0xAA,0xAC,0xAD,0xB5,0xB6,0xB7,0xB8,0xBD,0xBE,0xC6,0xC7,0xCF,0xCF,0xD0,0xEF, \
+				0xF0,0xF1,0xD1,0xD2,0xD3,0xF5,0xD4,0xF7,0xF8,0xF9,0xD5,0x96,0x95,0x98,0xFE,0xFF}
+
+#elif _CODE_PAGE == 1	/* ASCII (for only non-LFN cfg) */
+#if _USE_LFN != 0
+#error Cannot enable LFN without valid code page.
+#endif
+#define _DF1S	0
+
+#else
+#error Unknown code page
+
+#endif
+
+
+/* Character code support macros */
+#define IsUpper(c)	(((c)>='A')&&((c)<='Z'))
+#define IsLower(c)	(((c)>='a')&&((c)<='z'))
+#define IsDigit(c)	(((c)>='0')&&((c)<='9'))
+
+#if _DF1S != 0	/* Code page is DBCS */
+
+#ifdef _DF2S	/* Two 1st byte areas */
+#define IsDBCS1(c)	(((BYTE)(c) >= _DF1S && (BYTE)(c) <= _DF1E) || ((BYTE)(c) >= _DF2S && (BYTE)(c) <= _DF2E))
+#else			/* One 1st byte area */
+#define IsDBCS1(c)	((BYTE)(c) >= _DF1S && (BYTE)(c) <= _DF1E)
+#endif
+
+#ifdef _DS3S	/* Three 2nd byte areas */
+#define IsDBCS2(c)	(((BYTE)(c) >= _DS1S && (BYTE)(c) <= _DS1E) || ((BYTE)(c) >= _DS2S && (BYTE)(c) <= _DS2E) || ((BYTE)(c) >= _DS3S && (BYTE)(c) <= _DS3E))
+#else			/* Two 2nd byte areas */
+#define IsDBCS2(c)	(((BYTE)(c) >= _DS1S && (BYTE)(c) <= _DS1E) || ((BYTE)(c) >= _DS2S && (BYTE)(c) <= _DS2E))
+#endif
+
+#else			/* Code page is SBCS */
+
+#define IsDBCS1(c)	0
+#define IsDBCS2(c)	0
+
+#endif /* _DF1S */
+
+
+/* Additional file attribute bits for internal use */
+#define	AM_VOL		0x08	/* Volume label */
+#define AM_LFN		0x0F	/* LFN entry */
+#define AM_MASK		0x3F	/* Mask of defined bits */
+
+
+/* Additional file access control and file status flags for internal use */
+#define FA_SEEKEND	0x20	/* Seek to end of the file on file open */
+#define FA_MODIFIED	0x40	/* File has been modified */
+#define FA_DIRTY	0x80	/* FIL.buf[] needs to be written-back */
+
+
+/* Name status flags in fn[] */
+#define NSFLAG		11		/* Index of the name status byte */
+#define NS_LOSS		0x01	/* Out of 8.3 format */
+#define NS_LFN		0x02	/* Force to create LFN entry */
+#define NS_LAST		0x04	/* Last segment */
+#define NS_BODY		0x08	/* Lower case flag (body) */
+#define NS_EXT		0x10	/* Lower case flag (ext) */
+#define NS_DOT		0x20	/* Dot entry */
+#define NS_NOLFN	0x40	/* Do not find LFN */
+#define NS_NONAME	0x80	/* Not followed */
+
+
+/* Limits and boundaries */
+#define MAX_DIR		0x200000		/* Max size of FAT directory */
+#define MAX_DIR_EX	0x10000000		/* Max size of exFAT directory */
+#define MAX_FAT12	0xFF5			/* Max FAT12 clusters (differs from specs, but correct for real DOS/Windows behavior) */
+#define	MAX_FAT16	0xFFF5			/* Max FAT16 clusters (differs from specs, but correct for real DOS/Windows behavior) */
+#define	MAX_FAT32	0x0FFFFFF5		/* Max FAT32 clusters (not specified, practical limit) */
+#define	MAX_EXFAT	0x7FFFFFFD		/* Max exFAT clusters (differs from specs, implementation limit) */
+
+
+/* FatFs refers the FAT structure as simple byte array instead of structure member
+/ because the C structure is not binary compatible between different platforms */
+
+#define BS_JmpBoot			0		/* x86 jump instruction (3-byte) */
+#define BS_OEMName			3		/* OEM name (8-byte) */
+#define BPB_BytsPerSec		11		/* Sector size [byte] (WORD) */
+#define BPB_SecPerClus		13		/* Cluster size [sector] (BYTE) */
+#define BPB_RsvdSecCnt		14		/* Size of reserved area [sector] (WORD) */
+#define BPB_NumFATs			16		/* Number of FATs (BYTE) */
+#define BPB_RootEntCnt		17		/* Size of root directory area for FAT12/16 [entry] (WORD) */
+#define BPB_TotSec16		19		/* Volume size (16-bit) [sector] (WORD) */
+#define BPB_Media			21		/* Media descriptor byte (BYTE) */
+#define BPB_FATSz16			22		/* FAT size (16-bit) [sector] (WORD) */
+#define BPB_SecPerTrk		24		/* Track size for int13h [sector] (WORD) */
+#define BPB_NumHeads		26		/* Number of heads for int13h (WORD) */
+#define BPB_HiddSec			28		/* Volume offset from top of the drive (DWORD) */
+#define BPB_TotSec32		32		/* Volume size (32-bit) [sector] (DWORD) */
+#define BS_DrvNum			36		/* Physical drive number for int13h (BYTE) */
+#define BS_NTres			37		/* Error flag (BYTE) */
+#define BS_BootSig			38		/* Extended boot signature (BYTE) */
+#define BS_VolID			39		/* Volume serial number (DWORD) */
+#define BS_VolLab			43		/* Volume label string (8-byte) */
+#define BS_FilSysType		54		/* File system type string (8-byte) */
+#define BS_BootCode			62		/* Boot code (448-byte) */
+#define BS_55AA				510		/* Signature word (WORD) */
+
+#define BPB_FATSz32			36		/* FAT32: FAT size [sector] (DWORD) */
+#define BPB_ExtFlags32		40		/* FAT32: Extended flags (WORD) */
+#define BPB_FSVer32			42		/* FAT32: File system version (WORD) */
+#define BPB_RootClus32		44		/* FAT32: Root directory cluster (DWORD) */
+#define BPB_FSInfo32		48		/* FAT32: Offset of FSINFO sector (WORD) */
+#define BPB_BkBootSec32		50		/* FAT32: Offset of backup boot sector (WORD) */
+#define BS_DrvNum32			64		/* FAT32: Physical drive number for int13h (BYTE) */
+#define BS_NTres32			65		/* FAT32: Error flag (BYTE) */
+#define BS_BootSig32		66		/* FAT32: Extended boot signature (BYTE) */
+#define BS_VolID32			67		/* FAT32: Volume serial number (DWORD) */
+#define BS_VolLab32			71		/* FAT32: Volume label string (8-byte) */
+#define BS_FilSysType32		82		/* FAT32: File system type string (8-byte) */
+#define BS_BootCode32		90		/* FAT32: Boot code (420-byte) */
+
+#define BPB_ZeroedEx		11		/* exFAT: MBZ field (53-byte) */
+#define BPB_VolOfsEx		64		/* exFAT: Volume offset from top of the drive [sector] (QWORD) */
+#define BPB_TotSecEx		72		/* exFAT: Volume size [sector] (QWORD) */
+#define BPB_FatOfsEx		80		/* exFAT: FAT offset from top of the volume [sector] (DWORD) */
+#define BPB_FatSzEx			84		/* exFAT: FAT size [sector] (DWORD) */
+#define BPB_DataOfsEx		88		/* exFAT: Data offset from top of the volume [sector] (DWORD) */
+#define BPB_NumClusEx		92		/* exFAT: Number of clusters (DWORD) */
+#define BPB_RootClusEx		96		/* exFAT: Root directory start cluster (DWORD) */
+#define BPB_VolIDEx			100		/* exFAT: Volume serial number (DWORD) */
+#define BPB_FSVerEx			104		/* exFAT: File system version (WORD) */
+#define BPB_VolFlagEx		106		/* exFAT: Volume flags (BYTE) */
+#define BPB_ActFatEx		107		/* exFAT: Active FAT flags (BYTE) */
+#define BPB_BytsPerSecEx	108		/* exFAT: Log2 of sector size in unit of byte (BYTE) */
+#define BPB_SecPerClusEx	109		/* exFAT: Log2 of cluster size in unit of sector (BYTE) */
+#define BPB_NumFATsEx		110		/* exFAT: Number of FATs (BYTE) */
+#define BPB_DrvNumEx		111		/* exFAT: Physical drive number for int13h (BYTE) */
+#define BPB_PercInUseEx		112		/* exFAT: Percent in use (BYTE) */
+#define	BPB_RsvdEx			113		/* exFAT: Reserved (7-byte) */
+#define BS_BootCodeEx		120		/* exFAT: Boot code (390-byte) */
+
+#define	DIR_Name			0		/* Short file name (11-byte) */
+#define	DIR_Attr			11		/* Attribute (BYTE) */
+#define	DIR_NTres			12		/* Lower case flag (BYTE) */
+#define DIR_CrtTime10		13		/* Created time sub-second (BYTE) */
+#define	DIR_CrtTime			14		/* Created time (DWORD) */
+#define DIR_LstAccDate		18		/* Last accessed date (WORD) */
+#define	DIR_FstClusHI		20		/* Higher 16-bit of first cluster (WORD) */
+#define	DIR_ModTime			22		/* Modified time (DWORD) */
+#define	DIR_FstClusLO		26		/* Lower 16-bit of first cluster (WORD) */
+#define	DIR_FileSize		28		/* File size (DWORD) */
+#define	LDIR_Ord			0		/* LFN: LFN order and LLE flag (BYTE) */
+#define	LDIR_Attr			11		/* LFN: LFN attribute (BYTE) */
+#define	LDIR_Type			12		/* LFN: Entry type (BYTE) */
+#define	LDIR_Chksum			13		/* LFN: Checksum of the SFN (BYTE) */
+#define	LDIR_FstClusLO		26		/* LFN: MBZ field (WORD) */
+#define	XDIR_Type			0		/* exFAT: Type of exFAT directory entry (BYTE) */
+#define	XDIR_NumLabel		1		/* exFAT: Number of volume label characters (BYTE) */
+#define	XDIR_Label			2		/* exFAT: Volume label (11-WORD) */
+#define	XDIR_CaseSum		4		/* exFAT: Sum of case conversion table (DWORD) */
+#define	XDIR_NumSec			1		/* exFAT: Number of secondary entries (BYTE) */
+#define	XDIR_SetSum			2		/* exFAT: Sum of the set of directory entries (WORD) */
+#define	XDIR_Attr			4		/* exFAT: File attribute (WORD) */
+#define	XDIR_CrtTime		8		/* exFAT: Created time (DWORD) */
+#define	XDIR_ModTime		12		/* exFAT: Modified time (DWORD) */
+#define	XDIR_AccTime		16		/* exFAT: Last accessed time (DWORD) */
+#define	XDIR_CrtTime10		20		/* exFAT: Created time subsecond (BYTE) */
+#define	XDIR_ModTime10		21		/* exFAT: Modified time subsecond (BYTE) */
+#define	XDIR_CrtTZ			22		/* exFAT: Created timezone (BYTE) */
+#define	XDIR_ModTZ			23		/* exFAT: Modified timezone (BYTE) */
+#define	XDIR_AccTZ			24		/* exFAT: Last accessed timezone (BYTE) */
+#define	XDIR_GenFlags		33		/* exFAT: General secondary flags (WORD) */
+#define	XDIR_NumName		35		/* exFAT: Number of file name characters (BYTE) */
+#define	XDIR_NameHash		36		/* exFAT: Hash of file name (WORD) */
+#define XDIR_ValidFileSize	40		/* exFAT: Valid file size (QWORD) */
+#define	XDIR_FstClus		52		/* exFAT: First cluster of the file data (DWORD) */
+#define	XDIR_FileSize		56		/* exFAT: File/Directory size (QWORD) */
+
+#define	SZDIRE				32		/* Size of a directory entry */
+#define	DDEM				0xE5	/* Deleted directory entry mark set to DIR_Name[0] */
+#define	RDDEM				0x05	/* Replacement of the character collides with DDEM */
+#define	LLEF				0x40	/* Last long entry flag in LDIR_Ord */
+
+#define	FSI_LeadSig			0		/* FAT32 FSI: Leading signature (DWORD) */
+#define	FSI_StrucSig		484		/* FAT32 FSI: Structure signature (DWORD) */
+#define	FSI_Free_Count		488		/* FAT32 FSI: Number of free clusters (DWORD) */
+#define	FSI_Nxt_Free		492		/* FAT32 FSI: Last allocated cluster (DWORD) */
+
+#define MBR_Table			446		/* MBR: Offset of partition table in the MBR */
+#define	SZ_PTE				16		/* MBR: Size of a partition table entry */
+#define PTE_Boot			0		/* MBR PTE: Boot indicator */
+#define PTE_StHead			1		/* MBR PTE: Start head */
+#define PTE_StSec			2		/* MBR PTE: Start sector */
+#define PTE_StCyl			3		/* MBR PTE: Start cylinder */
+#define PTE_System			4		/* MBR PTE: System ID */
+#define PTE_EdHead			5		/* MBR PTE: End head */
+#define PTE_EdSec			6		/* MBR PTE: End sector */
+#define PTE_EdCyl			7		/* MBR PTE: End cylinder */
+#define PTE_StLba			8		/* MBR PTE: Start in LBA */
+#define PTE_SizLba			12		/* MBR PTE: Size in LBA */
+
+
+/* Post process after fatal error on file operation */
+#define	ABORT(fs, res)		{ fp->err = (BYTE)(res); LEAVE_FF(fs, res); }
+
+
+/* Reentrancy related */
+#if _FS_REENTRANT
+#if _USE_LFN == 1
+#error Static LFN work area cannot be used at thread-safe configuration
+#endif
+#define	ENTER_FF(fs)		{ if (!lock_fs(fs)) return FR_TIMEOUT; }
+#define	LEAVE_FF(fs, res)	{ unlock_fs(fs, res); return res; }
+#else
+#define	ENTER_FF(fs)
+#define LEAVE_FF(fs, res)	return res
+#endif
+
+
+/* Definitions of volume - partition conversion */
+#if _MULTI_PARTITION
+#define LD2PD(vol) VolToPart[vol].pd	/* Get physical drive number */
+#define LD2PT(vol) VolToPart[vol].pt	/* Get partition index */
+#else
+#define LD2PD(vol) (BYTE)(vol)	/* Each logical drive is bound to the same physical drive number */
+#define LD2PT(vol) 0			/* Find first valid partition or in SFD */
+#endif
+
+
+/* Definitions of sector size */
+#if (_MAX_SS < _MIN_SS) || (_MAX_SS != 512 && _MAX_SS != 1024 && _MAX_SS != 2048 && _MAX_SS != 4096) || (_MIN_SS != 512 && _MIN_SS != 1024 && _MIN_SS != 2048 && _MIN_SS != 4096)
+#error Wrong sector size configuration
+#endif
+#if _MAX_SS == _MIN_SS
+#define	SS(fs)	((UINT)_MAX_SS)	/* Fixed sector size */
+#else
+#define	SS(fs)	((fs)->ssize)	/* Variable sector size */
+#endif
+
+
+/* Timestamp */
+#if _FS_NORTC == 1
+#if _NORTC_YEAR < 1980 || _NORTC_YEAR > 2107 || _NORTC_MON < 1 || _NORTC_MON > 12 || _NORTC_MDAY < 1 || _NORTC_MDAY > 31
+#error Invalid _FS_NORTC settings
+#endif
+#define GET_FATTIME()	((DWORD)(_NORTC_YEAR - 1980) << 25 | (DWORD)_NORTC_MON << 21 | (DWORD)_NORTC_MDAY << 16)
+#else
+#define GET_FATTIME()	get_fattime()
+#endif
+
+
+/* File lock controls */
+#if _FS_LOCK != 0
+#if _FS_READONLY
+#error _FS_LOCK must be 0 at read-only configuration
+#endif
+typedef struct {
+	FATFS *fs;		/* Object ID 1, volume (NULL:blank entry) */
+	DWORD clu;		/* Object ID 2, containing directory (0:root) */
+	DWORD ofs;		/* Object ID 3, offset in the directory */
+	WORD ctr;		/* Object open counter, 0:none, 0x01..0xFF:read mode open count, 0x100:write mode */
+} FILESEM;
+#endif
+
+
+
+
+
+/*--------------------------------------------------------------------------
+
+   Module Private Work Area
+
+---------------------------------------------------------------------------*/
+
+/* Remark: Variables defined here without initial value shall be guaranteed
+/  zero/null at start-up. If not, the linker option or start-up routine is
+/  not compliance with C standard. */
+
+#if _VOLUMES < 1 || _VOLUMES > 10
+#error Wrong _VOLUMES setting
+#endif
+static FATFS *FatFs[_VOLUMES];	/* Pointer to the file system objects (logical drives) */
+static WORD Fsid;				/* File system mount ID */
+
+#if _FS_RPATH != 0 && _VOLUMES >= 2
+static BYTE CurrVol;			/* Current drive */
+#endif
+
+#if _FS_LOCK != 0
+static FILESEM Files[_FS_LOCK];	/* Open object lock semaphores */
+#endif
+
+#if _USE_LFN == 0		/* Non-LFN configuration */
+#define	DEF_NAMBUF
+#define INIT_NAMBUF(fs)
+#define	FREE_NAMBUF()
+
+#else					/* LFN configuration */
+#if _MAX_LFN < 12 || _MAX_LFN > 255
+#error Wrong _MAX_LFN value
+#endif
+#define MAXDIRB(nc)	((nc + 44U) / 15 * SZDIRE)
+
+#if _USE_LFN == 1		/* LFN enabled with static working buffer */
+#if _FS_EXFAT
+static BYTE	DirBuf[MAXDIRB(_MAX_LFN)];	/* Directory entry block scratchpad buffer */
+#endif
+static WCHAR LfnBuf[_MAX_LFN + 1];	/* LFN enabled with static working buffer */
+#define	DEF_NAMBUF
+#define INIT_NAMBUF(fs)
+#define	FREE_NAMBUF()
+
+#elif _USE_LFN == 2 	/* LFN enabled with dynamic working buffer on the stack */
+#if _FS_EXFAT
+#define	DEF_NAMBUF		WCHAR lbuf[_MAX_LFN+1]; BYTE dbuf[MAXDIRB(_MAX_LFN)];
+#define INIT_NAMBUF(fs)	{ (fs)->lfnbuf = lbuf; (fs)->dirbuf = dbuf; }
+#define	FREE_NAMBUF()
+#else
+#define	DEF_NAMBUF		WCHAR lbuf[_MAX_LFN+1];
+#define INIT_NAMBUF(fs)	{ (fs)->lfnbuf = lbuf; }
+#define	FREE_NAMBUF()
+#endif
+
+#elif _USE_LFN == 3 	/* LFN enabled with dynamic working buffer on the heap */
+#if _FS_EXFAT
+#define	DEF_NAMBUF		WCHAR *lfn;
+#define INIT_NAMBUF(fs)	{ lfn = ff_memalloc((_MAX_LFN+1)*2 + MAXDIRB(_MAX_LFN)); if (!lfn) LEAVE_FF(fs, FR_NOT_ENOUGH_CORE); (fs)->lfnbuf = lfn; (fs)->dirbuf = (BYTE*)(lfn+_MAX_LFN+1); }
+#define	FREE_NAMBUF()	ff_memfree(lfn)
+#else
+#define	DEF_NAMBUF		WCHAR *lfn;
+#define INIT_NAMBUF(fs)	{ lfn = ff_memalloc((_MAX_LFN+1)*2); if (!lfn) LEAVE_FF(fs, FR_NOT_ENOUGH_CORE); (fs)->lfnbuf = lfn; }
+#define	FREE_NAMBUF()	ff_memfree(lfn)
+#endif
+
+#else
+#error Wrong _USE_LFN setting
+
+#endif
+#endif	/* else _USE_LFN == 0 */
+
+#ifdef _EXCVT
+static const BYTE ExCvt[] = _EXCVT;	/* Upper conversion table for SBCS extended characters */
+#endif
+
+
+
+
+
+
+/*--------------------------------------------------------------------------
+
+   Module Private Functions
+
+---------------------------------------------------------------------------*/
+
+
+/*-----------------------------------------------------------------------*/
+/* Load/Store multi-byte word in the FAT structure                       */
+/*-----------------------------------------------------------------------*/
+
+static
+WORD ld_word (const BYTE* ptr)	/*	 Load a 2-byte little-endian word */
+{
+	WORD rv;
+
+	rv = ptr[1];
+	rv = rv << 8 | ptr[0];
+	return rv;
+}
+
+static
+DWORD ld_dword (const BYTE* ptr)	/* Load a 4-byte little-endian word */
+{
+	DWORD rv;
+
+	rv = ptr[3];
+	rv = rv << 8 | ptr[2];
+	rv = rv << 8 | ptr[1];
+	rv = rv << 8 | ptr[0];
+	return rv;
+}
+
+#if _FS_EXFAT
+static
+QWORD ld_qword (const BYTE* ptr)	/* Load an 8-byte little-endian word */
+{
+	QWORD rv;
+
+	rv = ptr[7];
+	rv = rv << 8 | ptr[6];
+	rv = rv << 8 | ptr[5];
+	rv = rv << 8 | ptr[4];
+	rv = rv << 8 | ptr[3];
+	rv = rv << 8 | ptr[2];
+	rv = rv << 8 | ptr[1];
+	rv = rv << 8 | ptr[0];
+	return rv;
+}
+#endif
+
+#if !_FS_READONLY
+static
+void st_word (BYTE* ptr, WORD val)	/* Store a 2-byte word in little-endian */
+{
+	*ptr++ = (BYTE)val; val >>= 8;
+	*ptr++ = (BYTE)val;
+}
+
+static
+void st_dword (BYTE* ptr, DWORD val)	/* Store a 4-byte word in little-endian */
+{
+	*ptr++ = (BYTE)val; val >>= 8;
+	*ptr++ = (BYTE)val; val >>= 8;
+	*ptr++ = (BYTE)val; val >>= 8;
+	*ptr++ = (BYTE)val;
+}
+
+#if _FS_EXFAT
+static
+void st_qword (BYTE* ptr, QWORD val)	/* Store an 8-byte word in little-endian */
+{
+	*ptr++ = (BYTE)val; val >>= 8;
+	*ptr++ = (BYTE)val; val >>= 8;
+	*ptr++ = (BYTE)val; val >>= 8;
+	*ptr++ = (BYTE)val; val >>= 8;
+	*ptr++ = (BYTE)val; val >>= 8;
+	*ptr++ = (BYTE)val; val >>= 8;
+	*ptr++ = (BYTE)val; val >>= 8;
+	*ptr++ = (BYTE)val;
+}
+#endif
+#endif	/* !_FS_READONLY */
+
+
+
+/*-----------------------------------------------------------------------*/
+/* String functions                                                      */
+/*-----------------------------------------------------------------------*/
+
+/* Copy memory to memory */
+static
+void mem_cpy (void* dst, const void* src, UINT cnt) {
+	BYTE *d = (BYTE*)dst;
+	const BYTE *s = (const BYTE*)src;
+
+	if (cnt) {
+		do {
+			*d++ = *s++;
+		} while (--cnt);
+	}
+}
+
+/* Fill memory block */
+static
+void mem_set (void* dst, int val, UINT cnt) {
+	BYTE *d = (BYTE*)dst;
+
+	do {
+		*d++ = (BYTE)val;
+	} while (--cnt);
+}
+
+/* Compare memory block */
+static
+int mem_cmp (const void* dst, const void* src, UINT cnt) {	/* ZR:same, NZ:different */
+	const BYTE *d = (const BYTE *)dst, *s = (const BYTE *)src;
+	int r = 0;
+
+	do {
+		r = *d++ - *s++;
+	} while (--cnt && r == 0);
+
+	return r;
+}
+
+/* Check if chr is contained in the string */
+static
+int chk_chr (const char* str, int chr) {	/* NZ:contained, ZR:not contained */
+	while (*str && *str != chr) str++;
+	return *str;
+}
+
+
+
+
+#if _FS_REENTRANT
+/*-----------------------------------------------------------------------*/
+/* Request/Release grant to access the volume                            */
+/*-----------------------------------------------------------------------*/
+static
+int lock_fs (
+	FATFS* fs		/* File system object */
+)
+{
+	return (fs && ff_req_grant(fs->sobj)) ? 1 : 0;
+}
+
+
+static
+void unlock_fs (
+	FATFS* fs,		/* File system object */
+	FRESULT res		/* Result code to be returned */
+)
+{
+	if (fs && res != FR_NOT_ENABLED && res != FR_INVALID_DRIVE && res != FR_TIMEOUT) {
+		ff_rel_grant(fs->sobj);
+	}
+}
+
+#endif
+
+
+
+#if _FS_LOCK != 0
+/*-----------------------------------------------------------------------*/
+/* File lock control functions                                           */
+/*-----------------------------------------------------------------------*/
+
+static
+FRESULT chk_lock (	/* Check if the file can be accessed */
+	DIR* dp,		/* Directory object pointing the file to be checked */
+	int acc			/* Desired access type (0:Read, 1:Write, 2:Delete/Rename) */
+)
+{
+	UINT i, be;
+
+	/* Search file semaphore table */
+	for (i = be = 0; i < _FS_LOCK; i++) {
+		if (Files[i].fs) {	/* Existing entry */
+			if (Files[i].fs == dp->obj.fs &&	 	/* Check if the object matched with an open object */
+				Files[i].clu == dp->obj.sclust &&
+				Files[i].ofs == dp->dptr) break;
+		} else {			/* Blank entry */
+			be = 1;
+		}
+	}
+	if (i == _FS_LOCK) {	/* The object is not opened */
+		return (be || acc == 2) ? FR_OK : FR_TOO_MANY_OPEN_FILES;	/* Is there a blank entry for new object? */
+	}
+
+	/* The object has been opened. Reject any open against writing file and all write mode open */
+	return (acc || Files[i].ctr == 0x100) ? FR_LOCKED : FR_OK;
+}
+
+
+static
+int enq_lock (void)	/* Check if an entry is available for a new object */
+{
+	UINT i;
+
+	for (i = 0; i < _FS_LOCK && Files[i].fs; i++) ;
+	return (i == _FS_LOCK) ? 0 : 1;
+}
+
+
+static
+UINT inc_lock (	/* Increment object open counter and returns its index (0:Internal error) */
+	DIR* dp,	/* Directory object pointing the file to register or increment */
+	int acc		/* Desired access (0:Read, 1:Write, 2:Delete/Rename) */
+)
+{
+	UINT i;
+
+
+	for (i = 0; i < _FS_LOCK; i++) {	/* Find the object */
+		if (Files[i].fs == dp->obj.fs &&
+			Files[i].clu == dp->obj.sclust &&
+			Files[i].ofs == dp->dptr) break;
+	}
+
+	if (i == _FS_LOCK) {				/* Not opened. Register it as new. */
+		for (i = 0; i < _FS_LOCK && Files[i].fs; i++) ;
+		if (i == _FS_LOCK) return 0;	/* No free entry to register (int err) */
+		Files[i].fs = dp->obj.fs;
+		Files[i].clu = dp->obj.sclust;
+		Files[i].ofs = dp->dptr;
+		Files[i].ctr = 0;
+	}
+
+	if (acc && Files[i].ctr) return 0;	/* Access violation (int err) */
+
+	Files[i].ctr = acc ? 0x100 : Files[i].ctr + 1;	/* Set semaphore value */
+
+	return i + 1;
+}
+
+
+static
+FRESULT dec_lock (	/* Decrement object open counter */
+	UINT i			/* Semaphore index (1..) */
+)
+{
+	WORD n;
+	FRESULT res;
+
+
+	if (--i < _FS_LOCK) {	/* Shift index number origin from 0 */
+		n = Files[i].ctr;
+		if (n == 0x100) n = 0;		/* If write mode open, delete the entry */
+		if (n > 0) n--;				/* Decrement read mode open count */
+		Files[i].ctr = n;
+		if (n == 0) Files[i].fs = 0;	/* Delete the entry if open count gets zero */
+		res = FR_OK;
+	} else {
+		res = FR_INT_ERR;			/* Invalid index nunber */
+	}
+	return res;
+}
+
+
+static
+void clear_lock (	/* Clear lock entries of the volume */
+	FATFS *fs
+)
+{
+	UINT i;
+
+	for (i = 0; i < _FS_LOCK; i++) {
+		if (Files[i].fs == fs) Files[i].fs = 0;
+	}
+}
+
+#endif	/* _FS_LOCK != 0 */
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Move/Flush disk access window in the file system object               */
+/*-----------------------------------------------------------------------*/
+#if !_FS_READONLY
+static
+FRESULT sync_window (	/* Returns FR_OK or FR_DISK_ERROR */
+	FATFS* fs			/* File system object */
+)
+{
+	DWORD wsect;
+	UINT nf;
+	FRESULT res = FR_OK;
+
+
+	if (fs->wflag) {	/* Write back the sector if it is dirty */
+		wsect = fs->winsect;	/* Current sector number */
+		if (disk_write(fs->drv, fs->win, wsect, 1) != RES_OK) {
+			res = FR_DISK_ERR;
+		} else {
+			fs->wflag = 0;
+			if (wsect - fs->fatbase < fs->fsize) {		/* Is it in the FAT area? */
+				for (nf = fs->n_fats; nf >= 2; nf--) {	/* Reflect the change to all FAT copies */
+					wsect += fs->fsize;
+					disk_write(fs->drv, fs->win, wsect, 1);
+				}
+			}
+		}
+	}
+	return res;
+}
+#endif
+
+
+static
+FRESULT move_window (	/* Returns FR_OK or FR_DISK_ERROR */
+	FATFS* fs,			/* File system object */
+	DWORD sector		/* Sector number to make appearance in the fs->win[] */
+)
+{
+	FRESULT res = FR_OK;
+
+
+	if (sector != fs->winsect) {	/* Window offset changed? */
+#if !_FS_READONLY
+		res = sync_window(fs);		/* Write-back changes */
+#endif
+		if (res == FR_OK) {			/* Fill sector window with new data */
+			if (disk_read(fs->drv, fs->win, sector, 1) != RES_OK) {
+				sector = 0xFFFFFFFF;	/* Invalidate window if data is not reliable */
+				res = FR_DISK_ERR;
+			}
+			fs->winsect = sector;
+		}
+	}
+	return res;
+}
+
+
+
+
+#if !_FS_READONLY
+/*-----------------------------------------------------------------------*/
+/* Synchronize file system and strage device                             */
+/*-----------------------------------------------------------------------*/
+
+static
+FRESULT sync_fs (	/* FR_OK:succeeded, !=0:error */
+	FATFS* fs		/* File system object */
+)
+{
+	FRESULT res;
+
+
+	res = sync_window(fs);
+	if (res == FR_OK) {
+		/* Update FSInfo sector if needed */
+		if (fs->fs_type == FS_FAT32 && fs->fsi_flag == 1) {
+			/* Create FSInfo structure */
+			mem_set(fs->win, 0, SS(fs));
+			st_word(fs->win + BS_55AA, 0xAA55);
+			st_dword(fs->win + FSI_LeadSig, 0x41615252);
+			st_dword(fs->win + FSI_StrucSig, 0x61417272);
+			st_dword(fs->win + FSI_Free_Count, fs->free_clst);
+			st_dword(fs->win + FSI_Nxt_Free, fs->last_clst);
+			/* Write it into the FSInfo sector */
+			fs->winsect = fs->volbase + 1;
+			disk_write(fs->drv, fs->win, fs->winsect, 1);
+			fs->fsi_flag = 0;
+		}
+		/* Make sure that no pending write process in the physical drive */
+		if (disk_ioctl(fs->drv, CTRL_SYNC, 0) != RES_OK) res = FR_DISK_ERR;
+	}
+
+	return res;
+}
+
+#endif
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Get sector# from cluster#                                             */
+/*-----------------------------------------------------------------------*/
+
+static
+DWORD clust2sect (	/* !=0:Sector number, 0:Failed (invalid cluster#) */
+	FATFS* fs,		/* File system object */
+	DWORD clst		/* Cluster# to be converted */
+)
+{
+	clst -= 2;
+	if (clst >= fs->n_fatent - 2) return 0;		/* Invalid cluster# */
+	return clst * fs->csize + fs->database;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* FAT access - Read value of a FAT entry                                */
+/*-----------------------------------------------------------------------*/
+
+static
+DWORD get_fat (	/* 0xFFFFFFFF:Disk error, 1:Internal error, 2..0x7FFFFFFF:Cluster status */
+	_FDID* obj,	/* Corresponding object */
+	DWORD clst	/* Cluster number to get the value */
+)
+{
+	UINT wc, bc;
+	DWORD val;
+	FATFS *fs = obj->fs;
+
+
+	if (clst < 2 || clst >= fs->n_fatent) {	/* Check if in valid range */
+		val = 1;	/* Internal error */
+
+	} else {
+		val = 0xFFFFFFFF;	/* Default value falls on disk error */
+
+		switch (fs->fs_type) {
+		case FS_FAT12 :
+			bc = (UINT)clst; bc += bc / 2;
+			if (move_window(fs, fs->fatbase + (bc / SS(fs))) != FR_OK) break;
+			wc = fs->win[bc++ % SS(fs)];
+			if (move_window(fs, fs->fatbase + (bc / SS(fs))) != FR_OK) break;
+			wc |= fs->win[bc % SS(fs)] << 8;
+			val = (clst & 1) ? (wc >> 4) : (wc & 0xFFF);
+			break;
+
+		case FS_FAT16 :
+			if (move_window(fs, fs->fatbase + (clst / (SS(fs) / 2))) != FR_OK) break;
+			val = ld_word(fs->win + clst * 2 % SS(fs));
+			break;
+
+		case FS_FAT32 :
+			if (move_window(fs, fs->fatbase + (clst / (SS(fs) / 4))) != FR_OK) break;
+			val = ld_dword(fs->win + clst * 4 % SS(fs)) & 0x0FFFFFFF;
+			break;
+#if _FS_EXFAT
+		case FS_EXFAT :
+			if (obj->objsize) {
+				DWORD cofs = clst - obj->sclust;	/* Offset from start cluster */
+				DWORD clen = (DWORD)((obj->objsize - 1) / SS(fs)) / fs->csize;	/* Number of clusters - 1 */
+
+				if (obj->stat == 2) {	/* Is there no valid chain on the FAT? */
+					if (cofs <= clen) {
+						val = (cofs == clen) ? 0x7FFFFFFF : clst + 1;	/* Generate the value */
+						break;
+					}
+				}
+				if (obj->stat == 3 && cofs < obj->n_cont) {	/* Is it in the 1st fragment? */
+					val = clst + 1; 	/* Generate the value */
+					break;
+				}
+				if (obj->stat != 2) {	/* Get value from FAT if FAT chain is valid */
+					if (obj->n_frag != 0) {	/* Is it on the growing edge? */
+						val = 0x7FFFFFFF;	/* Generate EOC */
+					} else {
+						if (move_window(fs, fs->fatbase + (clst / (SS(fs) / 4))) != FR_OK) break;
+						val = ld_dword(fs->win + clst * 4 % SS(fs)) & 0x7FFFFFFF;
+					}
+					break;
+				}
+			}
+			/* go to default */
+#endif
+		default:
+			val = 1;	/* Internal error */
+		}
+	}
+
+	return val;
+}
+
+
+
+
+#if !_FS_READONLY
+/*-----------------------------------------------------------------------*/
+/* FAT access - Change value of a FAT entry                              */
+/*-----------------------------------------------------------------------*/
+
+static
+FRESULT put_fat (	/* FR_OK(0):succeeded, !=0:error */
+	FATFS* fs,		/* Corresponding file system object */
+	DWORD clst,		/* FAT index number (cluster number) to be changed */
+	DWORD val		/* New value to be set to the entry */
+)
+{
+	UINT bc;
+	BYTE *p;
+	FRESULT res = FR_INT_ERR;
+
+	if (clst >= 2 && clst < fs->n_fatent) {	/* Check if in valid range */
+		switch (fs->fs_type) {
+		case FS_FAT12 :	/* Bitfield items */
+			bc = (UINT)clst; bc += bc / 2;
+			res = move_window(fs, fs->fatbase + (bc / SS(fs)));
+			if (res != FR_OK) break;
+			p = fs->win + bc++ % SS(fs);
+			*p = (clst & 1) ? ((*p & 0x0F) | ((BYTE)val << 4)) : (BYTE)val;
+			fs->wflag = 1;
+			res = move_window(fs, fs->fatbase + (bc / SS(fs)));
+			if (res != FR_OK) break;
+			p = fs->win + bc % SS(fs);
+			*p = (clst & 1) ? (BYTE)(val >> 4) : ((*p & 0xF0) | ((BYTE)(val >> 8) & 0x0F));
+			fs->wflag = 1;
+			break;
+
+		case FS_FAT16 :	/* WORD aligned items */
+			res = move_window(fs, fs->fatbase + (clst / (SS(fs) / 2)));
+			if (res != FR_OK) break;
+			st_word(fs->win + clst * 2 % SS(fs), (WORD)val);
+			fs->wflag = 1;
+			break;
+
+		case FS_FAT32 :	/* DWORD aligned items */
+#if _FS_EXFAT
+		case FS_EXFAT :
+#endif
+			res = move_window(fs, fs->fatbase + (clst / (SS(fs) / 4)));
+			if (res != FR_OK) break;
+			if (!_FS_EXFAT || fs->fs_type != FS_EXFAT) {
+				val = (val & 0x0FFFFFFF) | (ld_dword(fs->win + clst * 4 % SS(fs)) & 0xF0000000);
+			}
+			st_dword(fs->win + clst * 4 % SS(fs), val);
+			fs->wflag = 1;
+			break;
+		}
+	}
+	return res;
+}
+
+#endif /* !_FS_READONLY */
+
+
+
+
+#if _FS_EXFAT && !_FS_READONLY
+/*-----------------------------------------------------------------------*/
+/* exFAT: Accessing FAT and Allocation Bitmap                            */
+/*-----------------------------------------------------------------------*/
+
+/*--------------------------------------*/
+/* Find a contiguous free cluster block */
+/*--------------------------------------*/
+
+static
+DWORD find_bitmap (	/* 0:Not found, 2..:Cluster block found, 0xFFFFFFFF:Disk error */
+	FATFS* fs,	/* File system object */
+	DWORD clst,	/* Cluster number to scan from */
+	DWORD ncl	/* Number of contiguous clusters to find (1..) */
+)
+{
+	BYTE bm, bv;
+	UINT i;
+	DWORD val, scl, ctr;
+
+
+	clst -= 2;	/* The first bit in the bitmap corresponds to cluster #2 */
+	if (clst >= fs->n_fatent - 2) clst = 0;
+	scl = val = clst; ctr = 0;
+	for (;;) {
+		if (move_window(fs, fs->database + val / 8 / SS(fs)) != FR_OK) return 0xFFFFFFFF;	/* (assuming bitmap is located top of the cluster heap) */
+		i = val / 8 % SS(fs); bm = 1 << (val % 8);
+		do {
+			do {
+				bv = fs->win[i] & bm; bm <<= 1;		/* Get bit value */
+				if (++val >= fs->n_fatent - 2) {	/* Next cluster (with wrap-around) */
+					val = 0; bm = 0; i = SS(fs);
+				}
+				if (!bv) {	/* Is it a free cluster? */
+					if (++ctr == ncl) return scl + 2;	/* Check if run length is sufficient for required */
+				} else {
+					scl = val; ctr = 0;		/* Encountered a cluster in-use, restart to scan */
+				}
+				if (val == clst) return 0;	/* All cluster scanned? */
+			} while (bm);
+			bm = 1;
+		} while (++i < SS(fs));
+	}
+}
+
+
+/*----------------------------------------*/
+/* Set/Clear a block of allocation bitmap */
+/*----------------------------------------*/
+
+static
+FRESULT change_bitmap (
+	FATFS* fs,	/* File system object */
+	DWORD clst,	/* Cluster number to change from */
+	DWORD ncl,	/* Number of clusters to be changed */
+	int bv		/* bit value to be set (0 or 1) */
+)
+{
+	BYTE bm;
+	UINT i;
+	DWORD sect;
+
+	clst -= 2;	/* The first bit corresponds to cluster #2 */
+	sect = fs->database + clst / 8 / SS(fs);	/* Sector address (assuming bitmap is located top of the cluster heap) */
+	i = clst / 8 % SS(fs);						/* Byte offset in the sector */
+	bm = 1 << (clst % 8);						/* Bit mask in the byte */
+	for (;;) {
+		if (move_window(fs, sect++) != FR_OK) return FR_DISK_ERR;
+		do {
+			do {
+				if (bv == (int)((fs->win[i] & bm) != 0)) return FR_INT_ERR;	/* Is the bit expected value? */
+				fs->win[i] ^= bm;	/* Flip the bit */
+				fs->wflag = 1;
+				if (--ncl == 0) return FR_OK;	/* All bits processed? */
+			} while (bm <<= 1);		/* Next bit */
+			bm = 1;
+		} while (++i < SS(fs));		/* Next byte */
+		i = 0;
+	}
+}
+
+
+/*---------------------------------------------*/
+/* Fill the first fragment of the FAT chain    */
+/*---------------------------------------------*/
+
+static
+FRESULT fill_first_frag (
+	_FDID* obj	/* Pointer to the corresponding object */
+)
+{
+	FRESULT res;
+	DWORD cl, n;
+
+	if (obj->stat == 3) {	/* Has the object been changed 'fragmented'? */
+		for (cl = obj->sclust, n = obj->n_cont; n; cl++, n--) {	/* Create cluster chain on the FAT */
+			res = put_fat(obj->fs, cl, cl + 1);
+			if (res != FR_OK) return res;
+		}
+		obj->stat = 0;	/* Change status 'FAT chain is valid' */
+	}
+	return FR_OK;
+}
+
+
+/*---------------------------------------------*/
+/* Fill the last fragment of the FAT chain     */
+/*---------------------------------------------*/
+
+static
+FRESULT fill_last_frag (
+	_FDID* obj,	/* Pointer to the corresponding object */
+	DWORD lcl,	/* Last cluster of the fragment */
+	DWORD term	/* Value to set the last FAT entry */
+)
+{
+	FRESULT res;
+
+	while (obj->n_frag > 0) {	/* Create the last chain on the FAT */
+		res = put_fat(obj->fs, lcl - obj->n_frag + 1, (obj->n_frag > 1) ? lcl - obj->n_frag + 2 : term);
+		if (res != FR_OK) return res;
+		obj->n_frag--;
+	}
+	return FR_OK;
+}
+
+#endif	/* _FS_EXFAT && !_FS_READONLY */
+
+
+
+#if !_FS_READONLY
+/*-----------------------------------------------------------------------*/
+/* FAT handling - Remove a cluster chain                                 */
+/*-----------------------------------------------------------------------*/
+static
+FRESULT remove_chain (	/* FR_OK(0):succeeded, !=0:error */
+	_FDID* obj,			/* Corresponding object */
+	DWORD clst,			/* Cluster to remove a chain from */
+	DWORD pclst			/* Previous cluster of clst (0:an entire chain) */
+)
+{
+	FRESULT res = FR_OK;
+	DWORD nxt;
+	FATFS *fs = obj->fs;
+#if _FS_EXFAT || _USE_TRIM
+	DWORD scl = clst, ecl = clst;
+#endif
+#if _USE_TRIM
+	DWORD rt[2];
+#endif
+
+	if (clst < 2 || clst >= fs->n_fatent) return FR_INT_ERR;	/* Check if in valid range */
+
+	/* Mark the previous cluster 'EOC' on the FAT if it exists */
+	if (pclst && (!_FS_EXFAT || fs->fs_type != FS_EXFAT || obj->stat != 2)) {
+		res = put_fat(fs, pclst, 0xFFFFFFFF);
+		if (res != FR_OK) return res;
+	}
+
+	/* Remove the chain */
+	do {
+		nxt = get_fat(obj, clst);			/* Get cluster status */
+		if (nxt == 0) break;				/* Empty cluster? */
+		if (nxt == 1) return FR_INT_ERR;	/* Internal error? */
+		if (nxt == 0xFFFFFFFF) return FR_DISK_ERR;	/* Disk error? */
+		if (!_FS_EXFAT || fs->fs_type != FS_EXFAT) {
+			res = put_fat(fs, clst, 0);		/* Mark the cluster 'free' on the FAT */
+			if (res != FR_OK) return res;
+		}
+		if (fs->free_clst < fs->n_fatent - 2) {	/* Update FSINFO */
+			fs->free_clst++;
+			fs->fsi_flag |= 1;
+		}
+#if _FS_EXFAT || _USE_TRIM
+		if (ecl + 1 == nxt) {	/* Is next cluster contiguous? */
+			ecl = nxt;
+		} else {				/* End of contiguous cluster block */
+#if _FS_EXFAT
+			if (fs->fs_type == FS_EXFAT) {
+				res = change_bitmap(fs, scl, ecl - scl + 1, 0);	/* Mark the cluster block 'free' on the bitmap */
+				if (res != FR_OK) return res;
+			}
+#endif
+#if _USE_TRIM
+			rt[0] = clust2sect(fs, scl);					/* Start sector */
+			rt[1] = clust2sect(fs, ecl) + fs->csize - 1;	/* End sector */
+			disk_ioctl(fs->drv, CTRL_TRIM, rt);				/* Inform device the block can be erased */
+#endif
+			scl = ecl = nxt;
+		}
+#endif
+		clst = nxt;					/* Next cluster */
+	} while (clst < fs->n_fatent);	/* Repeat while not the last link */
+
+#if _FS_EXFAT
+	if (fs->fs_type == FS_EXFAT) {
+		if (pclst == 0) {	/* Does the object have no chain? */
+			obj->stat = 0;		/* Change the object status 'initial' */
+		} else {
+			if (obj->stat == 3 && pclst >= obj->sclust && pclst <= obj->sclust + obj->n_cont) {	/* Did the chain get contiguous? */
+				obj->stat = 2;	/* Change the object status 'contiguous' */
+			}
+		}
+	}
+#endif
+	return FR_OK;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* FAT handling - Stretch a chain or Create a new chain                  */
+/*-----------------------------------------------------------------------*/
+static
+DWORD create_chain (	/* 0:No free cluster, 1:Internal error, 0xFFFFFFFF:Disk error, >=2:New cluster# */
+	_FDID* obj,			/* Corresponding object */
+	DWORD clst			/* Cluster# to stretch, 0:Create a new chain */
+)
+{
+	DWORD cs, ncl, scl;
+	FRESULT res;
+	FATFS *fs = obj->fs;
+
+
+	if (clst == 0) {	/* Create a new chain */
+		scl = fs->last_clst;				/* Get suggested cluster to start from */
+		if (scl == 0 || scl >= fs->n_fatent) scl = 1;
+	}
+	else {				/* Stretch current chain */
+		cs = get_fat(obj, clst);			/* Check the cluster status */
+		if (cs < 2) return 1;				/* Invalid FAT value */
+		if (cs == 0xFFFFFFFF) return cs;	/* A disk error occurred */
+		if (cs < fs->n_fatent) return cs;	/* It is already followed by next cluster */
+		scl = clst;
+	}
+
+#if _FS_EXFAT
+	if (fs->fs_type == FS_EXFAT) {	/* On the exFAT volume */
+		ncl = find_bitmap(fs, scl, 1);				/* Find a free cluster */
+		if (ncl == 0 || ncl == 0xFFFFFFFF) return ncl;	/* No free cluster or hard error? */
+		res = change_bitmap(fs, ncl, 1, 1);			/* Mark the cluster 'in use' */
+		if (res == FR_INT_ERR) return 1;
+		if (res == FR_DISK_ERR) return 0xFFFFFFFF;
+		if (clst == 0) {							/* Is it a new chain? */
+			obj->stat = 2;							/* Set status 'contiguous' */
+		} else {									/* It is a stretched chain */
+			if (obj->stat == 2 && ncl != scl + 1) {	/* Is the chain got fragmented? */
+				obj->n_cont = scl - obj->sclust;	/* Set size of the contiguous part */
+				obj->stat = 3;						/* Change status 'just fragmented' */
+			}
+		}
+		if (obj->stat != 2) {	/* Is the file non-contiguous? */
+			if (ncl == clst + 1) {	/* Is the cluster next to previous one? */
+				obj->n_frag = obj->n_frag ? obj->n_frag + 1 : 2;	/* Increment size of last framgent */
+			} else {				/* New fragment */
+				if (obj->n_frag == 0) obj->n_frag = 1;
+				res = fill_last_frag(obj, clst, ncl);	/* Fill last fragment on the FAT and link it to new one */
+				if (res == FR_OK) obj->n_frag = 1;
+			}
+		}
+	} else
+#endif
+	{	/* On the FAT12/16/32 volume */
+		ncl = scl;	/* Start cluster */
+		for (;;) {
+			ncl++;							/* Next cluster */
+			if (ncl >= fs->n_fatent) {		/* Check wrap-around */
+				ncl = 2;
+				if (ncl > scl) return 0;	/* No free cluster */
+			}
+			cs = get_fat(obj, ncl);			/* Get the cluster status */
+			if (cs == 0) break;				/* Found a free cluster */
+			if (cs == 1 || cs == 0xFFFFFFFF) return cs;	/* An error occurred */
+			if (ncl == scl) return 0;		/* No free cluster */
+		}
+		res = put_fat(fs, ncl, 0xFFFFFFFF);	/* Mark the new cluster 'EOC' */
+		if (res == FR_OK && clst != 0) {
+			res = put_fat(fs, clst, ncl);	/* Link it from the previous one if needed */
+		}
+	}
+
+	if (res == FR_OK) {			/* Update FSINFO if function succeeded. */
+		fs->last_clst = ncl;
+		if (fs->free_clst <= fs->n_fatent - 2) fs->free_clst--;
+		fs->fsi_flag |= 1;
+	} else {
+		ncl = (res == FR_DISK_ERR) ? 0xFFFFFFFF : 1;	/* Failed. Generate error status */
+	}
+
+	return ncl;		/* Return new cluster number or error status */
+}
+
+#endif /* !_FS_READONLY */
+
+
+
+
+#if _USE_FASTSEEK
+/*-----------------------------------------------------------------------*/
+/* FAT handling - Convert offset into cluster with link map table        */
+/*-----------------------------------------------------------------------*/
+
+static
+DWORD clmt_clust (	/* <2:Error, >=2:Cluster number */
+	FIL* fp,		/* Pointer to the file object */
+	FSIZE_t ofs		/* File offset to be converted to cluster# */
+)
+{
+	DWORD cl, ncl, *tbl;
+	FATFS *fs = fp->obj.fs;
+
+
+	tbl = fp->cltbl + 1;	/* Top of CLMT */
+	cl = (DWORD)(ofs / SS(fs) / fs->csize);	/* Cluster order from top of the file */
+	for (;;) {
+		ncl = *tbl++;			/* Number of cluters in the fragment */
+		if (ncl == 0) return 0;	/* End of table? (error) */
+		if (cl < ncl) break;	/* In this fragment? */
+		cl -= ncl; tbl++;		/* Next fragment */
+	}
+	return cl + *tbl;	/* Return the cluster number */
+}
+
+#endif	/* _USE_FASTSEEK */
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Directory handling - Set directory index                              */
+/*-----------------------------------------------------------------------*/
+
+static
+FRESULT dir_sdi (	/* FR_OK(0):succeeded, !=0:error */
+	DIR* dp,		/* Pointer to directory object */
+	DWORD ofs		/* Offset of directory table */
+)
+{
+	DWORD csz, clst;
+	FATFS *fs = dp->obj.fs;
+
+
+	if (ofs >= (DWORD)((_FS_EXFAT && fs->fs_type == FS_EXFAT) ? MAX_DIR_EX : MAX_DIR) || ofs % SZDIRE) {	/* Check range of offset and alignment */
+		return FR_INT_ERR;
+	}
+	dp->dptr = ofs;				/* Set current offset */
+	clst = dp->obj.sclust;		/* Table start cluster (0:root) */
+	if (clst == 0 && fs->fs_type >= FS_FAT32) {	/* Replace cluster# 0 with root cluster# */
+		clst = fs->dirbase;
+		if (_FS_EXFAT) dp->obj.stat = 0;	/* exFAT: Root dir has an FAT chain */
+	}
+
+	if (clst == 0) {	/* Static table (root-directory in FAT12/16) */
+		if (ofs / SZDIRE >= fs->n_rootdir)	return FR_INT_ERR;	/* Is index out of range? */
+		dp->sect = fs->dirbase;
+
+	} else {			/* Dynamic table (sub-directory or root-directory in FAT32+) */
+		csz = (DWORD)fs->csize * SS(fs);	/* Bytes per cluster */
+		while (ofs >= csz) {				/* Follow cluster chain */
+			clst = get_fat(&dp->obj, clst);				/* Get next cluster */
+			if (clst == 0xFFFFFFFF) return FR_DISK_ERR;	/* Disk error */
+			if (clst < 2 || clst >= fs->n_fatent) return FR_INT_ERR;	/* Reached to end of table or internal error */
+			ofs -= csz;
+		}
+		dp->sect = clust2sect(fs, clst);
+	}
+	dp->clust = clst;					/* Current cluster# */
+	if (!dp->sect) return FR_INT_ERR;
+	dp->sect += ofs / SS(fs);			/* Sector# of the directory entry */
+	dp->dir = fs->win + (ofs % SS(fs));	/* Pointer to the entry in the win[] */
+
+	return FR_OK;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Directory handling - Move directory table index next                  */
+/*-----------------------------------------------------------------------*/
+
+static
+FRESULT dir_next (	/* FR_OK(0):succeeded, FR_NO_FILE:End of table, FR_DENIED:Could not stretch */
+	DIR* dp,		/* Pointer to the directory object */
+	int stretch		/* 0: Do not stretch table, 1: Stretch table if needed */
+)
+{
+	DWORD ofs, clst;
+	FATFS *fs = dp->obj.fs;
+#if !_FS_READONLY
+	UINT n;
+#endif
+
+	ofs = dp->dptr + SZDIRE;	/* Next entry */
+	if (!dp->sect || ofs >= (DWORD)((_FS_EXFAT && fs->fs_type == FS_EXFAT) ? MAX_DIR_EX : MAX_DIR)) return FR_NO_FILE;	/* Report EOT when offset has reached max value */
+
+	if (ofs % SS(fs) == 0) {	/* Sector changed? */
+		dp->sect++;				/* Next sector */
+
+		if (!dp->clust) {		/* Static table */
+			if (ofs / SZDIRE >= fs->n_rootdir) {	/* Report EOT if it reached end of static table */
+				dp->sect = 0; return FR_NO_FILE;
+			}
+		}
+		else {					/* Dynamic table */
+			if ((ofs / SS(fs) & (fs->csize - 1)) == 0) {		/* Cluster changed? */
+				clst = get_fat(&dp->obj, dp->clust);			/* Get next cluster */
+				if (clst <= 1) return FR_INT_ERR;				/* Internal error */
+				if (clst == 0xFFFFFFFF) return FR_DISK_ERR;		/* Disk error */
+				if (clst >= fs->n_fatent) {						/* Reached end of dynamic table */
+#if !_FS_READONLY
+					if (!stretch) {								/* If no stretch, report EOT */
+						dp->sect = 0; return FR_NO_FILE;
+					}
+					clst = create_chain(&dp->obj, dp->clust);	/* Allocate a cluster */
+					if (clst == 0) return FR_DENIED;			/* No free cluster */
+					if (clst == 1) return FR_INT_ERR;			/* Internal error */
+					if (clst == 0xFFFFFFFF) return FR_DISK_ERR;	/* Disk error */
+					/* Clean-up the stretched table */
+					if (_FS_EXFAT) dp->obj.stat |= 4;			/* The directory needs to be updated */
+					if (sync_window(fs) != FR_OK) return FR_DISK_ERR;	/* Flush disk access window */
+					mem_set(fs->win, 0, SS(fs));				/* Clear window buffer */
+					for (n = 0, fs->winsect = clust2sect(fs, clst); n < fs->csize; n++, fs->winsect++) {	/* Fill the new cluster with 0 */
+						fs->wflag = 1;
+						if (sync_window(fs) != FR_OK) return FR_DISK_ERR;
+					}
+					fs->winsect -= n;							/* Restore window offset */
+#else
+					if (!stretch) dp->sect = 0;					/* (this line is to suppress compiler warning) */
+					dp->sect = 0; return FR_NO_FILE;			/* Report EOT */
+#endif
+				}
+				dp->clust = clst;		/* Initialize data for new cluster */
+				dp->sect = clust2sect(fs, clst);
+			}
+		}
+	}
+	dp->dptr = ofs;						/* Current entry */
+	dp->dir = fs->win + ofs % SS(fs);	/* Pointer to the entry in the win[] */
+
+	return FR_OK;
+}
+
+
+
+
+#if !_FS_READONLY
+/*-----------------------------------------------------------------------*/
+/* Directory handling - Reserve a block of directory entries             */
+/*-----------------------------------------------------------------------*/
+
+static
+FRESULT dir_alloc (	/* FR_OK(0):succeeded, !=0:error */
+	DIR* dp,		/* Pointer to the directory object */
+	UINT nent		/* Number of contiguous entries to allocate */
+)
+{
+	FRESULT res;
+	UINT n;
+	FATFS *fs = dp->obj.fs;
+
+
+	res = dir_sdi(dp, 0);
+	if (res == FR_OK) {
+		n = 0;
+		do {
+			res = move_window(fs, dp->sect);
+			if (res != FR_OK) break;
+#if _FS_EXFAT
+			if ((fs->fs_type == FS_EXFAT) ? (int)((dp->dir[XDIR_Type] & 0x80) == 0) : (int)(dp->dir[DIR_Name] == DDEM || dp->dir[DIR_Name] == 0)) {
+#else
+			if (dp->dir[DIR_Name] == DDEM || dp->dir[DIR_Name] == 0) {
+#endif
+				if (++n == nent) break;	/* A block of contiguous free entries is found */
+			} else {
+				n = 0;					/* Not a blank entry. Restart to search */
+			}
+			res = dir_next(dp, 1);
+		} while (res == FR_OK);	/* Next entry with table stretch enabled */
+	}
+
+	if (res == FR_NO_FILE) res = FR_DENIED;	/* No directory entry to allocate */
+	return res;
+}
+
+#endif	/* !_FS_READONLY */
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* FAT: Directory handling - Load/Store start cluster number             */
+/*-----------------------------------------------------------------------*/
+
+static
+DWORD ld_clust (	/* Returns the top cluster value of the SFN entry */
+	FATFS* fs,		/* Pointer to the fs object */
+	const BYTE* dir	/* Pointer to the key entry */
+)
+{
+	DWORD cl;
+
+	cl = ld_word(dir + DIR_FstClusLO);
+	if (fs->fs_type == FS_FAT32) {
+		cl |= (DWORD)ld_word(dir + DIR_FstClusHI) << 16;
+	}
+
+	return cl;
+}
+
+
+#if !_FS_READONLY
+static
+void st_clust (
+	FATFS* fs,	/* Pointer to the fs object */
+	BYTE* dir,	/* Pointer to the key entry */
+	DWORD cl	/* Value to be set */
+)
+{
+	st_word(dir + DIR_FstClusLO, (WORD)cl);
+	if (fs->fs_type == FS_FAT32) {
+		st_word(dir + DIR_FstClusHI, (WORD)(cl >> 16));
+	}
+}
+#endif
+
+
+
+#if _USE_LFN != 0
+/*------------------------------------------------------------------------*/
+/* FAT-LFN: LFN handling                                                  */
+/*------------------------------------------------------------------------*/
+static
+const BYTE LfnOfs[] = {1,3,5,7,9,14,16,18,20,22,24,28,30};	/* Offset of LFN characters in the directory entry */
+
+
+/*--------------------------------------------------------*/
+/* FAT-LFN: Compare a part of file name with an LFN entry */
+/*--------------------------------------------------------*/
+static
+int cmp_lfn (				/* 1:matched, 0:not matched */
+	const WCHAR* lfnbuf,	/* Pointer to the LFN working buffer to be compared */
+	BYTE* dir				/* Pointer to the directory entry containing the part of LFN */
+)
+{
+	UINT i, s;
+	WCHAR wc, uc;
+
+
+	if (ld_word(dir + LDIR_FstClusLO) != 0) return 0;	/* Check LDIR_FstClusLO */
+
+	i = ((dir[LDIR_Ord] & 0x3F) - 1) * 13;	/* Offset in the LFN buffer */
+
+	for (wc = 1, s = 0; s < 13; s++) {		/* Process all characters in the entry */
+		uc = ld_word(dir + LfnOfs[s]);		/* Pick an LFN character */
+		if (wc) {
+			if (i >= _MAX_LFN || ff_wtoupper(uc) != ff_wtoupper(lfnbuf[i++])) {	/* Compare it */
+				return 0;					/* Not matched */
+			}
+			wc = uc;
+		} else {
+			if (uc != 0xFFFF) return 0;		/* Check filler */
+		}
+	}
+
+	if ((dir[LDIR_Ord] & LLEF) && wc && lfnbuf[i]) return 0;	/* Last segment matched but different length */
+
+	return 1;		/* The part of LFN matched */
+}
+
+
+#if _FS_MINIMIZE <= 1 || _FS_RPATH >= 2 || _USE_LABEL || _FS_EXFAT
+/*-----------------------------------------------------*/
+/* FAT-LFN: Pick a part of file name from an LFN entry */
+/*-----------------------------------------------------*/
+static
+int pick_lfn (			/* 1:succeeded, 0:buffer overflow or invalid LFN entry */
+	WCHAR* lfnbuf,		/* Pointer to the LFN working buffer */
+	BYTE* dir			/* Pointer to the LFN entry */
+)
+{
+	UINT i, s;
+	WCHAR wc, uc;
+
+
+	if (ld_word(dir + LDIR_FstClusLO) != 0) return 0;	/* Check LDIR_FstClusLO is 0 */
+
+	i = ((dir[LDIR_Ord] & ~LLEF) - 1) * 13;	/* Offset in the LFN buffer */
+
+	for (wc = 1, s = 0; s < 13; s++) {		/* Process all characters in the entry */
+		uc = ld_word(dir + LfnOfs[s]);		/* Pick an LFN character */
+		if (wc) {
+			if (i >= _MAX_LFN) return 0;	/* Buffer overflow? */
+			lfnbuf[i++] = wc = uc;			/* Store it */
+		} else {
+			if (uc != 0xFFFF) return 0;		/* Check filler */
+		}
+	}
+
+	if (dir[LDIR_Ord] & LLEF) {				/* Put terminator if it is the last LFN part */
+		if (i >= _MAX_LFN) return 0;		/* Buffer overflow? */
+		lfnbuf[i] = 0;
+	}
+
+	return 1;		/* The part of LFN is valid */
+}
+#endif
+
+
+#if !_FS_READONLY
+/*-----------------------------------------*/
+/* FAT-LFN: Create an entry of LFN entries */
+/*-----------------------------------------*/
+static
+void put_lfn (
+	const WCHAR* lfn,	/* Pointer to the LFN */
+	BYTE* dir,			/* Pointer to the LFN entry to be created */
+	BYTE ord,			/* LFN order (1-20) */
+	BYTE sum			/* Checksum of the corresponding SFN */
+)
+{
+	UINT i, s;
+	WCHAR wc;
+
+
+	dir[LDIR_Chksum] = sum;			/* Set checksum */
+	dir[LDIR_Attr] = AM_LFN;		/* Set attribute. LFN entry */
+	dir[LDIR_Type] = 0;
+	st_word(dir + LDIR_FstClusLO, 0);
+
+	i = (ord - 1) * 13;				/* Get offset in the LFN working buffer */
+	s = wc = 0;
+	do {
+		if (wc != 0xFFFF) wc = lfn[i++];	/* Get an effective character */
+		st_word(dir + LfnOfs[s], wc);		/* Put it */
+		if (wc == 0) wc = 0xFFFF;		/* Padding characters for left locations */
+	} while (++s < 13);
+	if (wc == 0xFFFF || !lfn[i]) ord |= LLEF;	/* Last LFN part is the start of LFN sequence */
+	dir[LDIR_Ord] = ord;			/* Set the LFN order */
+}
+
+#endif	/* !_FS_READONLY */
+#endif	/* _USE_LFN != 0 */
+
+
+
+#if _USE_LFN != 0 && !_FS_READONLY
+/*-----------------------------------------------------------------------*/
+/* FAT-LFN: Create a Numbered SFN                                        */
+/*-----------------------------------------------------------------------*/
+
+static
+void gen_numname (
+	BYTE* dst,			/* Pointer to the buffer to store numbered SFN */
+	const BYTE* src,	/* Pointer to SFN */
+	const WCHAR* lfn,	/* Pointer to LFN */
+	UINT seq			/* Sequence number */
+)
+{
+	BYTE ns[8], c;
+	UINT i, j;
+	WCHAR wc;
+	DWORD sr;
+
+
+	mem_cpy(dst, src, 11);
+
+	if (seq > 5) {	/* In case of many collisions, generate a hash number instead of sequential number */
+		sr = seq;
+		while (*lfn) {	/* Create a CRC */
+			wc = *lfn++;
+			for (i = 0; i < 16; i++) {
+				sr = (sr << 1) + (wc & 1);
+				wc >>= 1;
+				if (sr & 0x10000) sr ^= 0x11021;
+			}
+		}
+		seq = (UINT)sr;
+	}
+
+	/* itoa (hexdecimal) */
+	i = 7;
+	do {
+		c = (BYTE)((seq % 16) + '0');
+		if (c > '9') c += 7;
+		ns[i--] = c;
+		seq /= 16;
+	} while (seq);
+	ns[i] = '~';
+
+	/* Append the number */
+	for (j = 0; j < i && dst[j] != ' '; j++) {
+		if (IsDBCS1(dst[j])) {
+			if (j == i - 1) break;
+			j++;
+		}
+	}
+	do {
+		dst[j++] = (i < 8) ? ns[i++] : ' ';
+	} while (j < 8);
+}
+#endif	/* _USE_LFN != 0 && !_FS_READONLY */
+
+
+
+#if _USE_LFN != 0
+/*-----------------------------------------------------------------------*/
+/* FAT-LFN: Calculate checksum of an SFN entry                           */
+/*-----------------------------------------------------------------------*/
+
+static
+BYTE sum_sfn (
+	const BYTE* dir		/* Pointer to the SFN entry */
+)
+{
+	BYTE sum = 0;
+	UINT n = 11;
+
+	do {
+		sum = (sum >> 1) + (sum << 7) + *dir++;
+	} while (--n);
+	return sum;
+}
+
+#endif	/* _USE_LFN != 0 */
+
+
+
+#if _FS_EXFAT
+/*-----------------------------------------------------------------------*/
+/* exFAT: Checksum                                                       */
+/*-----------------------------------------------------------------------*/
+
+static
+WORD xdir_sum (			/* Get checksum of the directoly block */
+	const BYTE* dir		/* Directory entry block to be calculated */
+)
+{
+	UINT i, szblk;
+	WORD sum;
+
+
+	szblk = (dir[XDIR_NumSec] + 1) * SZDIRE;
+	for (i = sum = 0; i < szblk; i++) {
+		if (i == XDIR_SetSum) {	/* Skip sum field */
+			i++;
+		} else {
+			sum = ((sum & 1) ? 0x8000 : 0) + (sum >> 1) + dir[i];
+		}
+	}
+	return sum;
+}
+
+
+
+static
+WORD xname_sum (		/* Get check sum (to be used as hash) of the name */
+	const WCHAR* name	/* File name to be calculated */
+)
+{
+	WCHAR chr;
+	WORD sum = 0;
+
+
+	while ((chr = *name++) != 0) {
+		chr = ff_wtoupper(chr);		/* File name needs to be ignored case */
+		sum = ((sum & 1) ? 0x8000 : 0) + (sum >> 1) + (chr & 0xFF);
+		sum = ((sum & 1) ? 0x8000 : 0) + (sum >> 1) + (chr >> 8);
+	}
+	return sum;
+}
+
+
+#if !_FS_READONLY && _USE_MKFS
+static
+DWORD xsum32 (
+	BYTE  dat,	/* Data to be sumed */
+	DWORD sum	/* Previous value */
+)
+{
+	sum = ((sum & 1) ? 0x80000000 : 0) + (sum >> 1) + dat;
+	return sum;
+}
+#endif
+
+
+#if _FS_MINIMIZE <= 1 || _FS_RPATH >= 2
+/*------------------------------------------------------*/
+/* exFAT: Get object information from a directory block */
+/*------------------------------------------------------*/
+
+static
+void get_xdir_info (
+	BYTE* dirb,			/* Pointer to the direcotry entry block 85+C0+C1s */
+	FILINFO* fno		/* Buffer to store the extracted file information */
+)
+{
+	UINT di, si;
+	WCHAR w;
+#if !_LFN_UNICODE
+	UINT nc;
+#endif
+
+	/* Get file name */
+	di = 0;
+#if _LFN_UNICODE
+	for (si = SZDIRE * 2; di < dirb[XDIR_NumName]; si += 2, di++) {
+		if ((si % SZDIRE) == 0) si += 2;		/* Skip entry type field */
+		w = ld_word(dirb + si);					/* Get a character */
+		if (di >= _MAX_LFN) { di = 0; break; }	/* Buffer overflow --> inaccessible object name */
+		fno->fname[di] = w;						/* Store it */
+	}
+#else
+	for (si = SZDIRE * 2, nc = 0; nc < dirb[XDIR_NumName]; si += 2, nc++) {
+		if ((si % SZDIRE) == 0) si += 2;		/* Skip entry type field */
+		w = ff_convert(ld_word(dirb + si), 0);	/* Get a character and Unicode -> OEM */
+		if (_DF1S && w >= 0x100) {				/* Is it a double byte char? (always false at SBCS cfg) */
+			fno->fname[di++] = (char)(w >> 8);	/* Put 1st byte of the DBC */
+		}
+		if (w == 0 || di >= _MAX_LFN) { di = 0; break; }	/* Invalid char or buffer overflow --> inaccessible object name */
+		fno->fname[di++] = (char)w;
+	}
+#endif
+	if (di == 0) fno->fname[di++] = '?';	/* Inaccessible object name? */
+	fno->fname[di] = 0;						/* Terminate file name */
+
+	fno->altname[0] = 0;							/* No SFN */
+	fno->fattrib = dirb[XDIR_Attr];					/* Attribute */
+	fno->fsize = (fno->fattrib & AM_DIR) ? 0 : ld_qword(dirb + XDIR_FileSize);	/* Size */
+	fno->ftime = ld_word(dirb + XDIR_ModTime + 0);	/* Time */
+	fno->fdate = ld_word(dirb + XDIR_ModTime + 2);	/* Date */
+}
+
+#endif	/* _FS_MINIMIZE <= 1 || _FS_RPATH >= 2 */
+
+
+/*-----------------------------------*/
+/* exFAT: Get a directry entry block */
+/*-----------------------------------*/
+
+static
+FRESULT load_xdir (	/* FR_INT_ERR: invalid entry block */
+	DIR* dp			/* Pointer to the reading direcotry object pointing the 85 entry */
+)
+{
+	FRESULT res;
+	UINT i, sz_ent;
+	BYTE* dirb = dp->obj.fs->dirbuf;	/* Pointer to the on-memory direcotry entry block 85+C0+C1s */
+
+
+	/* Load 85 entry */
+	res = move_window(dp->obj.fs, dp->sect);
+	if (res != FR_OK) return res;
+	if (dp->dir[XDIR_Type] != 0x85) return FR_INT_ERR;
+	mem_cpy(dirb + 0, dp->dir, SZDIRE);
+	sz_ent = (dirb[XDIR_NumSec] + 1) * SZDIRE;
+	if (sz_ent < 3 * SZDIRE || sz_ent > 19 * SZDIRE) return FR_INT_ERR;
+
+	/* Load C0 entry */
+	res = dir_next(dp, 0);
+	if (res != FR_OK) return res;
+	res = move_window(dp->obj.fs, dp->sect);
+	if (res != FR_OK) return res;
+	if (dp->dir[XDIR_Type] != 0xC0) return FR_INT_ERR;
+	mem_cpy(dirb + SZDIRE, dp->dir, SZDIRE);
+	if (MAXDIRB(dirb[XDIR_NumName]) > sz_ent) return FR_INT_ERR;
+
+	/* Load C1 entries */
+	i = SZDIRE * 2;	/* C1 offset */
+	do {
+		res = dir_next(dp, 0);
+		if (res != FR_OK) return res;
+		res = move_window(dp->obj.fs, dp->sect);
+		if (res != FR_OK) return res;
+		if (dp->dir[XDIR_Type] != 0xC1) return FR_INT_ERR;
+		if (i < MAXDIRB(_MAX_LFN)) mem_cpy(dirb + i, dp->dir, SZDIRE);
+	} while ((i += SZDIRE) < sz_ent);
+
+	/* Sanity check (do it when accessible object name) */
+	if (i <= MAXDIRB(_MAX_LFN)) {
+		if (xdir_sum(dirb) != ld_word(dirb + XDIR_SetSum)) return FR_INT_ERR;
+	}
+	return FR_OK;
+}
+
+
+#if !_FS_READONLY || _FS_RPATH != 0
+/*------------------------------------------------*/
+/* exFAT: Load the object's directory entry block */
+/*------------------------------------------------*/
+static
+FRESULT load_obj_dir (
+	DIR* dp,			/* Blank directory object to be used to access containing direcotry */
+	const _FDID* obj	/* Object with its containing directory information */
+)
+{
+	FRESULT res;
+
+	/* Open object containing directory */
+	dp->obj.fs = obj->fs;
+	dp->obj.sclust = obj->c_scl;
+	dp->obj.stat = (BYTE)obj->c_size;
+	dp->obj.objsize = obj->c_size & 0xFFFFFF00;
+	dp->blk_ofs = obj->c_ofs;
+
+	res = dir_sdi(dp, dp->blk_ofs);	/* Goto object's entry block */
+	if (res == FR_OK) {
+		res = load_xdir(dp);		/* Load the object's entry block */
+	}
+	return res;
+}
+#endif
+
+
+#if !_FS_READONLY
+/*-----------------------------------------------*/
+/* exFAT: Store the directory block to the media */
+/*-----------------------------------------------*/
+static
+FRESULT store_xdir (
+	DIR* dp				/* Pointer to the direcotry object */
+)
+{
+	FRESULT res;
+	UINT nent;
+	BYTE* dirb = dp->obj.fs->dirbuf;	/* Pointer to the direcotry entry block 85+C0+C1s */
+
+	/* Create set sum */
+	st_word(dirb + XDIR_SetSum, xdir_sum(dirb));
+	nent = dirb[XDIR_NumSec] + 1;
+
+	/* Store the set of directory to the volume */
+	res = dir_sdi(dp, dp->blk_ofs);
+	while (res == FR_OK) {
+		res = move_window(dp->obj.fs, dp->sect);
+		if (res != FR_OK) break;
+		mem_cpy(dp->dir, dirb, SZDIRE);
+		dp->obj.fs->wflag = 1;
+		if (--nent == 0) break;
+		dirb += SZDIRE;
+		res = dir_next(dp, 0);
+	}
+	return (res == FR_OK || res == FR_DISK_ERR) ? res : FR_INT_ERR;
+}
+
+
+
+/*-------------------------------------------*/
+/* exFAT: Create a new directory enrty block */
+/*-------------------------------------------*/
+
+static
+void create_xdir (
+	BYTE* dirb,			/* Pointer to the direcotry entry block buffer */
+	const WCHAR* lfn	/* Pointer to the nul terminated file name */
+)
+{
+	UINT i;
+	BYTE nb, nc;
+	WCHAR chr;
+
+
+	/* Create 85+C0 entry */
+	mem_set(dirb, 0, 2 * SZDIRE);
+	dirb[XDIR_Type] = 0x85;
+	dirb[XDIR_Type + SZDIRE] = 0xC0;
+
+	/* Create C1 entries */
+	nc = 0; nb = 1; chr = 1; i = SZDIRE * 2;
+	do {
+		dirb[i++] = 0xC1; dirb[i++] = 0;	/* Entry type C1 */
+		do {	/* Fill name field */
+			if (chr && (chr = lfn[nc]) != 0) nc++;	/* Get a character if exist */
+			st_word(dirb + i, chr); 		/* Store it */
+		} while ((i += 2) % SZDIRE != 0);
+		nb++;
+	} while (lfn[nc]);	/* Fill next entry if any char follows */
+
+	dirb[XDIR_NumName] = nc;	/* Set name length */
+	dirb[XDIR_NumSec] = nb;		/* Set block length */
+	st_word(dirb + XDIR_NameHash, xname_sum(lfn));	/* Set name hash */
+}
+
+#endif	/* !_FS_READONLY */
+#endif	/* _FS_EXFAT */
+
+
+
+#if _FS_MINIMIZE <= 1 || _FS_RPATH >= 2 || _USE_LABEL || _FS_EXFAT
+/*-----------------------------------------------------------------------*/
+/* Read an object from the directory                                     */
+/*-----------------------------------------------------------------------*/
+
+static
+FRESULT dir_read (
+	DIR* dp,		/* Pointer to the directory object */
+	int vol			/* Filtered by 0:file/directory or 1:volume label */
+)
+{
+	FRESULT res = FR_NO_FILE;
+	FATFS *fs = dp->obj.fs;
+	BYTE a, c;
+#if _USE_LFN != 0
+	BYTE ord = 0xFF, sum = 0xFF;
+#endif
+
+	while (dp->sect) {
+		res = move_window(fs, dp->sect);
+		if (res != FR_OK) break;
+		c = dp->dir[DIR_Name];	/* Test for the entry type */
+		if (c == 0) {
+			res = FR_NO_FILE; break; /* Reached to end of the directory */
+		}
+#if _FS_EXFAT
+		if (fs->fs_type == FS_EXFAT) {	/* On the exFAT volume */
+			if (_USE_LABEL && vol) {
+				if (c == 0x83) break;	/* Volume label entry? */
+			} else {
+				if (c == 0x85) {		/* Start of the file entry block? */
+					dp->blk_ofs = dp->dptr;	/* Get location of the block */
+					res = load_xdir(dp);	/* Load the entry block */
+					if (res == FR_OK) {
+						dp->obj.attr = fs->dirbuf[XDIR_Attr] & AM_MASK;	/* Get attribute */
+					}
+					break;
+				}
+			}
+		} else
+#endif
+		{	/* On the FAT12/16/32 volume */
+			dp->obj.attr = a = dp->dir[DIR_Attr] & AM_MASK;	/* Get attribute */
+#if _USE_LFN != 0	/* LFN configuration */
+			if (c == DDEM || c == '.' || (int)((a & ~AM_ARC) == AM_VOL) != vol) {	/* An entry without valid data */
+				ord = 0xFF;
+			} else {
+				if (a == AM_LFN) {			/* An LFN entry is found */
+					if (c & LLEF) {			/* Is it start of an LFN sequence? */
+						sum = dp->dir[LDIR_Chksum];
+						c &= (BYTE)~LLEF; ord = c;
+						dp->blk_ofs = dp->dptr;
+					}
+					/* Check LFN validity and capture it */
+					ord = (c == ord && sum == dp->dir[LDIR_Chksum] && pick_lfn(fs->lfnbuf, dp->dir)) ? ord - 1 : 0xFF;
+				} else {					/* An SFN entry is found */
+					if (ord || sum != sum_sfn(dp->dir)) {	/* Is there a valid LFN? */
+						dp->blk_ofs = 0xFFFFFFFF;			/* It has no LFN. */
+					}
+					break;
+				}
+			}
+#else		/* Non LFN configuration */
+			if (c != DDEM && c != '.' && a != AM_LFN && (int)((a & ~AM_ARC) == AM_VOL) == vol) {	/* Is it a valid entry? */
+				break;
+			}
+#endif
+		}
+		res = dir_next(dp, 0);		/* Next entry */
+		if (res != FR_OK) break;
+	}
+
+	if (res != FR_OK) dp->sect = 0;		/* Terminate the read operation on error or EOT */
+	return res;
+}
+
+#endif	/* _FS_MINIMIZE <= 1 || _USE_LABEL || _FS_RPATH >= 2 */
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Directory handling - Find an object in the directory                  */
+/*-----------------------------------------------------------------------*/
+
+static
+FRESULT dir_find (	/* FR_OK(0):succeeded, !=0:error */
+	DIR* dp			/* Pointer to the directory object with the file name */
+)
+{
+	FRESULT res;
+	FATFS *fs = dp->obj.fs;
+	BYTE c;
+#if _USE_LFN != 0
+	BYTE a, ord, sum;
+#endif
+
+	res = dir_sdi(dp, 0);			/* Rewind directory object */
+	if (res != FR_OK) return res;
+#if _FS_EXFAT
+	if (fs->fs_type == FS_EXFAT) {	/* On the exFAT volume */
+		BYTE nc;
+		UINT di, ni;
+		WORD hash = xname_sum(fs->lfnbuf);		/* Hash value of the name to find */
+
+		while ((res = dir_read(dp, 0)) == FR_OK) {	/* Read an item */
+#if _MAX_LFN < 255
+			if (fs->dirbuf[XDIR_NumName] > _MAX_LFN) continue;			/* Skip comparison if inaccessible object name */
+#endif
+			if (ld_word(fs->dirbuf + XDIR_NameHash) != hash) continue;	/* Skip comparison if hash mismatched */
+			for (nc = fs->dirbuf[XDIR_NumName], di = SZDIRE * 2, ni = 0; nc; nc--, di += 2, ni++) {	/* Compare the name */
+				if ((di % SZDIRE) == 0) di += 2;
+				if (ff_wtoupper(ld_word(fs->dirbuf + di)) != ff_wtoupper(fs->lfnbuf[ni])) break;
+			}
+			if (nc == 0 && !fs->lfnbuf[ni]) break;	/* Name matched? */
+		}
+		return res;
+	}
+#endif
+	/* On the FAT12/16/32 volume */
+#if _USE_LFN != 0
+	ord = sum = 0xFF; dp->blk_ofs = 0xFFFFFFFF;	/* Reset LFN sequence */
+#endif
+	do {
+		res = move_window(fs, dp->sect);
+		if (res != FR_OK) break;
+		c = dp->dir[DIR_Name];
+		if (c == 0) { res = FR_NO_FILE; break; }	/* Reached to end of table */
+#if _USE_LFN != 0	/* LFN configuration */
+		dp->obj.attr = a = dp->dir[DIR_Attr] & AM_MASK;
+		if (c == DDEM || ((a & AM_VOL) && a != AM_LFN)) {	/* An entry without valid data */
+			ord = 0xFF; dp->blk_ofs = 0xFFFFFFFF;	/* Reset LFN sequence */
+		} else {
+			if (a == AM_LFN) {			/* An LFN entry is found */
+				if (!(dp->fn[NSFLAG] & NS_NOLFN)) {
+					if (c & LLEF) {		/* Is it start of LFN sequence? */
+						sum = dp->dir[LDIR_Chksum];
+						c &= (BYTE)~LLEF; ord = c;	/* LFN start order */
+						dp->blk_ofs = dp->dptr;	/* Start offset of LFN */
+					}
+					/* Check validity of the LFN entry and compare it with given name */
+					ord = (c == ord && sum == dp->dir[LDIR_Chksum] && cmp_lfn(fs->lfnbuf, dp->dir)) ? ord - 1 : 0xFF;
+				}
+			} else {					/* An SFN entry is found */
+				if (!ord && sum == sum_sfn(dp->dir)) break;	/* LFN matched? */
+				if (!(dp->fn[NSFLAG] & NS_LOSS) && !mem_cmp(dp->dir, dp->fn, 11)) break;	/* SFN matched? */
+				ord = 0xFF; dp->blk_ofs = 0xFFFFFFFF;	/* Reset LFN sequence */
+			}
+		}
+#else		/* Non LFN configuration */
+		dp->obj.attr = dp->dir[DIR_Attr] & AM_MASK;
+		if (!(dp->dir[DIR_Attr] & AM_VOL) && !mem_cmp(dp->dir, dp->fn, 11)) break;	/* Is it a valid entry? */
+#endif
+		res = dir_next(dp, 0);	/* Next entry */
+	} while (res == FR_OK);
+
+	return res;
+}
+
+
+
+
+#if !_FS_READONLY
+/*-----------------------------------------------------------------------*/
+/* Register an object to the directory                                   */
+/*-----------------------------------------------------------------------*/
+
+static
+FRESULT dir_register (	/* FR_OK:succeeded, FR_DENIED:no free entry or too many SFN collision, FR_DISK_ERR:disk error */
+	DIR* dp				/* Target directory with object name to be created */
+)
+{
+	FRESULT res;
+	FATFS *fs = dp->obj.fs;
+#if _USE_LFN != 0	/* LFN configuration */
+	UINT n, nlen, nent;
+	BYTE sn[12], sum;
+
+
+	if (dp->fn[NSFLAG] & (NS_DOT | NS_NONAME)) return FR_INVALID_NAME;	/* Check name validity */
+	for (nlen = 0; fs->lfnbuf[nlen]; nlen++) ;	/* Get lfn length */
+
+#if _FS_EXFAT
+	if (fs->fs_type == FS_EXFAT) {	/* On the exFAT volume */
+		DIR dj;
+
+		nent = (nlen + 14) / 15 + 2;	/* Number of entries to allocate (85+C0+C1s) */
+		res = dir_alloc(dp, nent);		/* Allocate entries */
+		if (res != FR_OK) return res;
+		dp->blk_ofs = dp->dptr - SZDIRE * (nent - 1);	/* Set the allocated entry block offset */
+
+		if (dp->obj.sclust != 0 && (dp->obj.stat & 4)) {	/* Has the sub-directory been stretched? */
+			dp->obj.objsize += (DWORD)fs->csize * SS(fs);	/* Increase the directory size by cluster size */
+			res = fill_first_frag(&dp->obj);				/* Fill first fragment on the FAT if needed */
+			if (res != FR_OK) return res;
+			res = fill_last_frag(&dp->obj, dp->clust, 0xFFFFFFFF);	/* Fill last fragment on the FAT if needed */
+			if (res != FR_OK) return res;
+			res = load_obj_dir(&dj, &dp->obj);				/* Load the object status */
+			if (res != FR_OK) return res;
+			st_qword(fs->dirbuf + XDIR_FileSize, dp->obj.objsize);		/* Update the allocation status */
+			st_qword(fs->dirbuf + XDIR_ValidFileSize, dp->obj.objsize);
+			fs->dirbuf[XDIR_GenFlags] = dp->obj.stat | 1;
+			res = store_xdir(&dj);							/* Store the object status */
+			if (res != FR_OK) return res;
+		}
+
+		create_xdir(fs->dirbuf, fs->lfnbuf);	/* Create on-memory directory block to be written later */
+		return FR_OK;
+	}
+#endif
+	/* On the FAT12/16/32 volume */
+	mem_cpy(sn, dp->fn, 12);
+	if (sn[NSFLAG] & NS_LOSS) {			/* When LFN is out of 8.3 format, generate a numbered name */
+		dp->fn[NSFLAG] = NS_NOLFN;		/* Find only SFN */
+		for (n = 1; n < 100; n++) {
+			gen_numname(dp->fn, sn, fs->lfnbuf, n);	/* Generate a numbered name */
+			res = dir_find(dp);				/* Check if the name collides with existing SFN */
+			if (res != FR_OK) break;
+		}
+		if (n == 100) return FR_DENIED;		/* Abort if too many collisions */
+		if (res != FR_NO_FILE) return res;	/* Abort if the result is other than 'not collided' */
+		dp->fn[NSFLAG] = sn[NSFLAG];
+	}
+
+	/* Create an SFN with/without LFNs. */
+	nent = (sn[NSFLAG] & NS_LFN) ? (nlen + 12) / 13 + 1 : 1;	/* Number of entries to allocate */
+	res = dir_alloc(dp, nent);		/* Allocate entries */
+	if (res == FR_OK && --nent) {	/* Set LFN entry if needed */
+		res = dir_sdi(dp, dp->dptr - nent * SZDIRE);
+		if (res == FR_OK) {
+			sum = sum_sfn(dp->fn);	/* Checksum value of the SFN tied to the LFN */
+			do {					/* Store LFN entries in bottom first */
+				res = move_window(fs, dp->sect);
+				if (res != FR_OK) break;
+				put_lfn(fs->lfnbuf, dp->dir, (BYTE)nent, sum);
+				fs->wflag = 1;
+				res = dir_next(dp, 0);	/* Next entry */
+			} while (res == FR_OK && --nent);
+		}
+	}
+
+#else	/* Non LFN configuration */
+	res = dir_alloc(dp, 1);		/* Allocate an entry for SFN */
+
+#endif
+
+	/* Set SFN entry */
+	if (res == FR_OK) {
+		res = move_window(fs, dp->sect);
+		if (res == FR_OK) {
+			mem_set(dp->dir, 0, SZDIRE);	/* Clean the entry */
+			mem_cpy(dp->dir + DIR_Name, dp->fn, 11);	/* Put SFN */
+#if _USE_LFN != 0
+			dp->dir[DIR_NTres] = dp->fn[NSFLAG] & (NS_BODY | NS_EXT);	/* Put NT flag */
+#endif
+			fs->wflag = 1;
+		}
+	}
+
+	return res;
+}
+
+#endif /* !_FS_READONLY */
+
+
+
+#if !_FS_READONLY && _FS_MINIMIZE == 0
+/*-----------------------------------------------------------------------*/
+/* Remove an object from the directory                                   */
+/*-----------------------------------------------------------------------*/
+
+static
+FRESULT dir_remove (	/* FR_OK:Succeeded, FR_DISK_ERR:A disk error */
+	DIR* dp				/* Directory object pointing the entry to be removed */
+)
+{
+	FRESULT res;
+	FATFS *fs = dp->obj.fs;
+#if _USE_LFN != 0	/* LFN configuration */
+	DWORD last = dp->dptr;
+
+	res = (dp->blk_ofs == 0xFFFFFFFF) ? FR_OK : dir_sdi(dp, dp->blk_ofs);	/* Goto top of the entry block if LFN is exist */
+	if (res == FR_OK) {
+		do {
+			res = move_window(fs, dp->sect);
+			if (res != FR_OK) break;
+			/* Mark an entry 'deleted' */
+			if (_FS_EXFAT && fs->fs_type == FS_EXFAT) {	/* On the exFAT volume */
+				dp->dir[XDIR_Type] &= 0x7F;
+			} else {									/* On the FAT12/16/32 volume */
+				dp->dir[DIR_Name] = DDEM;
+			}
+			fs->wflag = 1;
+			if (dp->dptr >= last) break;	/* If reached last entry then all entries of the object has been deleted. */
+			res = dir_next(dp, 0);	/* Next entry */
+		} while (res == FR_OK);
+		if (res == FR_NO_FILE) res = FR_INT_ERR;
+	}
+#else			/* Non LFN configuration */
+
+	res = move_window(fs, dp->sect);
+	if (res == FR_OK) {
+		dp->dir[DIR_Name] = DDEM;
+		fs->wflag = 1;
+	}
+#endif
+
+	return res;
+}
+
+#endif /* !_FS_READONLY && _FS_MINIMIZE == 0 */
+
+
+
+#if _FS_MINIMIZE <= 1 || _FS_RPATH >= 2
+/*-----------------------------------------------------------------------*/
+/* Get file information from directory entry                             */
+/*-----------------------------------------------------------------------*/
+
+static
+void get_fileinfo (		/* No return code */
+	DIR* dp,			/* Pointer to the directory object */
+	FILINFO* fno	 	/* Pointer to the file information to be filled */
+)
+{
+	UINT i, j;
+	TCHAR c;
+	DWORD tm;
+#if _USE_LFN != 0
+	WCHAR w, lfv;
+	FATFS *fs = dp->obj.fs;
+#endif
+
+
+	fno->fname[0] = 0;		/* Invaidate file info */
+	if (!dp->sect) return;	/* Exit if read pointer has reached end of directory */
+
+#if _USE_LFN != 0	/* LFN configuration */
+#if _FS_EXFAT
+	if (fs->fs_type == FS_EXFAT) {	/* On the exFAT volume */
+		get_xdir_info(fs->dirbuf, fno);
+		return;
+	} else
+#endif
+	{	/* On the FAT12/16/32 volume */
+		if (dp->blk_ofs != 0xFFFFFFFF) {	/* Get LFN if available */
+			i = j = 0;
+			while ((w = fs->lfnbuf[j++]) != 0) {	/* Get an LFN character */
+#if !_LFN_UNICODE
+				w = ff_convert(w, 0);		/* Unicode -> OEM */
+				if (w == 0) { i = 0; break; }	/* No LFN if it could not be converted */
+				if (_DF1S && w >= 0x100) {	/* Put 1st byte if it is a DBC (always false at SBCS cfg) */
+					fno->fname[i++] = (char)(w >> 8);
+				}
+#endif
+				if (i >= _MAX_LFN) { i = 0; break; }	/* No LFN if buffer overflow */
+				fno->fname[i++] = (TCHAR)w;
+			}
+			fno->fname[i] = 0;	/* Terminate the LFN */
+		}
+	}
+
+	i = j = 0;
+	lfv = fno->fname[i];	/* LFN is exist if non-zero */
+	while (i < 11) {		/* Copy name body and extension */
+		c = (TCHAR)dp->dir[i++];
+		if (c == ' ') continue;				/* Skip padding spaces */
+		if (c == RDDEM) c = (TCHAR)DDEM;	/* Restore replaced DDEM character */
+		if (i == 9) {						/* Insert a . if extension is exist */
+			if (!lfv) fno->fname[j] = '.';
+			fno->altname[j++] = '.';
+		}
+#if _LFN_UNICODE
+		if (IsDBCS1(c) && i != 8 && i != 11 && IsDBCS2(dp->dir[i])) {
+			c = c << 8 | dp->dir[i++];
+		}
+		c = ff_convert(c, 1);	/* OEM -> Unicode */
+		if (!c) c = '?';
+#endif
+		fno->altname[j] = c;
+		if (!lfv) {
+			if (IsUpper(c) && (dp->dir[DIR_NTres] & ((i >= 9) ? NS_EXT : NS_BODY))) {
+				c += 0x20;			/* To lower */
+			}
+			fno->fname[j] = c;
+		}
+		j++;
+	}
+	if (!lfv) {
+		fno->fname[j] = 0;
+		if (!dp->dir[DIR_NTres]) j = 0;	/* Altname is no longer needed if neither LFN nor case info is exist. */
+	}
+	fno->altname[j] = 0;	/* Terminate the SFN */
+
+#else	/* Non-LFN configuration */
+	i = j = 0;
+	while (i < 11) {		/* Copy name body and extension */
+		c = (TCHAR)dp->dir[i++];
+		if (c == ' ') continue;				/* Skip padding spaces */
+		if (c == RDDEM) c = (TCHAR)DDEM;	/* Restore replaced DDEM character */
+		if (i == 9) fno->fname[j++] = '.';	/* Insert a . if extension is exist */
+		fno->fname[j++] = c;
+	}
+	fno->fname[j] = 0;
+#endif
+
+	fno->fattrib = dp->dir[DIR_Attr];				/* Attribute */
+	fno->fsize = ld_dword(dp->dir + DIR_FileSize);	/* Size */
+	tm = ld_dword(dp->dir + DIR_ModTime);			/* Timestamp */
+	fno->ftime = (WORD)tm; fno->fdate = (WORD)(tm >> 16);
+}
+
+#endif /* _FS_MINIMIZE <= 1 || _FS_RPATH >= 2 */
+
+
+
+#if _USE_FIND && _FS_MINIMIZE <= 1
+/*-----------------------------------------------------------------------*/
+/* Pattern matching                                                      */
+/*-----------------------------------------------------------------------*/
+
+static
+WCHAR get_achar (		/* Get a character and advances ptr 1 or 2 */
+	const TCHAR** ptr	/* Pointer to pointer to the SBCS/DBCS/Unicode string */
+)
+{
+#if !_LFN_UNICODE
+	WCHAR chr;
+
+	chr = (BYTE)*(*ptr)++;					/* Get a byte */
+	if (IsLower(chr)) chr -= 0x20;			/* To upper ASCII char */
+#ifdef _EXCVT
+	if (chr >= 0x80) chr = ExCvt[chr - 0x80];	/* To upper SBCS extended char */
+#else
+	if (IsDBCS1(chr) && IsDBCS2(**ptr)) {		/* Get DBC 2nd byte if needed */
+		chr = chr << 8 | (BYTE)*(*ptr)++;
+	}
+#endif
+	return chr;
+#else
+	return ff_wtoupper(*(*ptr)++);			/* Get a word and to upper */
+#endif
+}
+
+
+static
+int pattern_matching (	/* 0:not matched, 1:matched */
+	const TCHAR* pat,	/* Matching pattern */
+	const TCHAR* nam,	/* String to be tested */
+	int skip,			/* Number of pre-skip chars (number of ?s) */
+	int inf				/* Infinite search (* specified) */
+)
+{
+	const TCHAR *pp, *np;
+	WCHAR pc, nc;
+	int nm, nx;
+
+
+	while (skip--) {				/* Pre-skip name chars */
+		if (!get_achar(&nam)) return 0;	/* Branch mismatched if less name chars */
+	}
+	if (!*pat && inf) return 1;		/* (short circuit) */
+
+	do {
+		pp = pat; np = nam;			/* Top of pattern and name to match */
+		for (;;) {
+			if (*pp == '?' || *pp == '*') {	/* Wildcard? */
+				nm = nx = 0;
+				do {				/* Analyze the wildcard chars */
+					if (*pp++ == '?') nm++; else nx = 1;
+				} while (*pp == '?' || *pp == '*');
+				if (pattern_matching(pp, np, nm, nx)) return 1;	/* Test new branch (recurs upto number of wildcard blocks in the pattern) */
+				nc = *np; break;	/* Branch mismatched */
+			}
+			pc = get_achar(&pp);	/* Get a pattern char */
+			nc = get_achar(&np);	/* Get a name char */
+			if (pc != nc) break;	/* Branch mismatched? */
+			if (pc == 0) return 1;	/* Branch matched? (matched at end of both strings) */
+		}
+		get_achar(&nam);			/* nam++ */
+	} while (inf && nc);			/* Retry until end of name if infinite search is specified */
+
+	return 0;
+}
+
+#endif /* _USE_FIND && _FS_MINIMIZE <= 1 */
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Pick a top segment and create the object name in directory form       */
+/*-----------------------------------------------------------------------*/
+
+static
+FRESULT create_name (	/* FR_OK: successful, FR_INVALID_NAME: could not create */
+	DIR* dp,			/* Pointer to the directory object */
+	const TCHAR** path	/* Pointer to pointer to the segment in the path string */
+)
+{
+#if _USE_LFN != 0	/* LFN configuration */
+	BYTE b, cf;
+	WCHAR w, *lfn;
+	UINT i, ni, si, di;
+	const TCHAR *p;
+
+	/* Create LFN in Unicode */
+	p = *path; lfn = dp->obj.fs->lfnbuf; si = di = 0;
+	for (;;) {
+		w = p[si++];					/* Get a character */
+		if (w < ' ') break;				/* Break if end of the path name */
+		if (w == '/' || w == '\\') {	/* Break if a separator is found */
+			while (p[si] == '/' || p[si] == '\\') si++;	/* Skip duplicated separator if exist */
+			break;
+		}
+		if (di >= _MAX_LFN) return FR_INVALID_NAME;	/* Reject too long name */
+#if !_LFN_UNICODE
+		w &= 0xFF;
+		if (IsDBCS1(w)) {				/* Check if it is a DBC 1st byte (always false on SBCS cfg) */
+			b = (BYTE)p[si++];			/* Get 2nd byte */
+			w = (w << 8) + b;			/* Create a DBC */
+			if (!IsDBCS2(b)) return FR_INVALID_NAME;	/* Reject invalid sequence */
+		}
+		w = ff_convert(w, 1);			/* Convert ANSI/OEM to Unicode */
+		if (!w) return FR_INVALID_NAME;	/* Reject invalid code */
+#endif
+		if (w < 0x80 && chk_chr("\"*:<>\?|\x7F", w)) return FR_INVALID_NAME;	/* Reject illegal characters for LFN */
+		lfn[di++] = w;					/* Store the Unicode character */
+	}
+	*path = &p[si];						/* Return pointer to the next segment */
+	cf = (w < ' ') ? NS_LAST : 0;		/* Set last segment flag if end of the path */
+#if _FS_RPATH != 0
+	if ((di == 1 && lfn[di - 1] == '.') ||
+		(di == 2 && lfn[di - 1] == '.' && lfn[di - 2] == '.')) {	/* Is this segment a dot name? */
+		lfn[di] = 0;
+		for (i = 0; i < 11; i++)		/* Create dot name for SFN entry */
+			dp->fn[i] = (i < di) ? '.' : ' ';
+		dp->fn[i] = cf | NS_DOT;		/* This is a dot entry */
+		return FR_OK;
+	}
+#endif
+	while (di) {						/* Snip off trailing spaces and dots if exist */
+		w = lfn[di - 1];
+		if (w != ' ' && w != '.') break;
+		di--;
+	}
+	lfn[di] = 0;						/* LFN is created */
+	if (di == 0) return FR_INVALID_NAME;	/* Reject nul name */
+
+	/* Create SFN in directory form */
+	mem_set(dp->fn, ' ', 11);
+	for (si = 0; lfn[si] == ' ' || lfn[si] == '.'; si++) ;	/* Strip leading spaces and dots */
+	if (si) cf |= NS_LOSS | NS_LFN;
+	while (di && lfn[di - 1] != '.') di--;	/* Find extension (di<=si: no extension) */
+
+	i = b = 0; ni = 8;
+	for (;;) {
+		w = lfn[si++];					/* Get an LFN character */
+		if (!w) break;					/* Break on end of the LFN */
+		if (w == ' ' || (w == '.' && si != di)) {	/* Remove spaces and dots */
+			cf |= NS_LOSS | NS_LFN; continue;
+		}
+
+		if (i >= ni || si == di) {		/* Extension or end of SFN */
+			if (ni == 11) {				/* Long extension */
+				cf |= NS_LOSS | NS_LFN; break;
+			}
+			if (si != di) cf |= NS_LOSS | NS_LFN;	/* Out of 8.3 format */
+			if (si > di) break;			/* No extension */
+			si = di; i = 8; ni = 11;	/* Enter extension section */
+			b <<= 2; continue;
+		}
+
+		if (w >= 0x80) {				/* Non ASCII character */
+#ifdef _EXCVT
+			w = ff_convert(w, 0);		/* Unicode -> OEM code */
+			if (w) w = ExCvt[w - 0x80];	/* Convert extended character to upper (SBCS) */
+#else
+			w = ff_convert(ff_wtoupper(w), 0);	/* Upper converted Unicode -> OEM code */
+#endif
+			cf |= NS_LFN;				/* Force create LFN entry */
+		}
+
+		if (_DF1S && w >= 0x100) {		/* Is this DBC? (always false at SBCS cfg) */
+			if (i >= ni - 1) {
+				cf |= NS_LOSS | NS_LFN; i = ni; continue;
+			}
+			dp->fn[i++] = (BYTE)(w >> 8);
+		} else {						/* SBC */
+			if (!w || chk_chr("+,;=[]", w)) {	/* Replace illegal characters for SFN */
+				w = '_'; cf |= NS_LOSS | NS_LFN;/* Lossy conversion */
+			} else {
+				if (IsUpper(w)) {		/* ASCII large capital */
+					b |= 2;
+				} else {
+					if (IsLower(w)) {	/* ASCII small capital */
+						b |= 1; w -= 0x20;
+					}
+				}
+			}
+		}
+		dp->fn[i++] = (BYTE)w;
+	}
+
+	if (dp->fn[0] == DDEM) dp->fn[0] = RDDEM;	/* If the first character collides with DDEM, replace it with RDDEM */
+
+	if (ni == 8) b <<= 2;
+	if ((b & 0x0C) == 0x0C || (b & 0x03) == 0x03) cf |= NS_LFN;	/* Create LFN entry when there are composite capitals */
+	if (!(cf & NS_LFN)) {						/* When LFN is in 8.3 format without extended character, NT flags are created */
+		if ((b & 0x03) == 0x01) cf |= NS_EXT;	/* NT flag (Extension has only small capital) */
+		if ((b & 0x0C) == 0x04) cf |= NS_BODY;	/* NT flag (Filename has only small capital) */
+	}
+
+	dp->fn[NSFLAG] = cf;	/* SFN is created */
+
+	return FR_OK;
+
+
+#else	/* _USE_LFN != 0 : Non-LFN configuration */
+	BYTE c, d, *sfn;
+	UINT ni, si, i;
+	const char *p;
+
+	/* Create file name in directory form */
+	p = *path; sfn = dp->fn;
+	mem_set(sfn, ' ', 11);
+	si = i = 0; ni = 8;
+#if _FS_RPATH != 0
+	if (p[si] == '.') { /* Is this a dot entry? */
+		for (;;) {
+			c = (BYTE)p[si++];
+			if (c != '.' || si >= 3) break;
+			sfn[i++] = c;
+		}
+		if (c != '/' && c != '\\' && c > ' ') return FR_INVALID_NAME;
+		*path = p + si;								/* Return pointer to the next segment */
+		sfn[NSFLAG] = (c <= ' ') ? NS_LAST | NS_DOT : NS_DOT;	/* Set last segment flag if end of the path */
+		return FR_OK;
+	}
+#endif
+	for (;;) {
+		c = (BYTE)p[si++];
+		if (c <= ' ') break; 			/* Break if end of the path name */
+		if (c == '/' || c == '\\') {	/* Break if a separator is found */
+			while (p[si] == '/' || p[si] == '\\') si++;	/* Skip duplicated separator if exist */
+			break;
+		}
+		if (c == '.' || i >= ni) {		/* End of body or over size? */
+			if (ni == 11 || c != '.') return FR_INVALID_NAME;	/* Over size or invalid dot */
+			i = 8; ni = 11;				/* Goto extension */
+			continue;
+		}
+		if (c >= 0x80) {				/* Extended character? */
+#ifdef _EXCVT
+			c = ExCvt[c - 0x80];		/* To upper extended characters (SBCS cfg) */
+#else
+#if !_DF1S
+			return FR_INVALID_NAME;		/* Reject extended characters (ASCII only cfg) */
+#endif
+#endif
+		}
+		if (IsDBCS1(c)) {				/* Check if it is a DBC 1st byte (always false at SBCS cfg.) */
+			d = (BYTE)p[si++];			/* Get 2nd byte */
+			if (!IsDBCS2(d) || i >= ni - 1) return FR_INVALID_NAME;	/* Reject invalid DBC */
+			sfn[i++] = c;
+			sfn[i++] = d;
+		} else {						/* SBC */
+			if (chk_chr("\"*+,:;<=>\?[]|\x7F", c)) return FR_INVALID_NAME;	/* Reject illegal chrs for SFN */
+			if (IsLower(c)) c -= 0x20;	/* To upper */
+			sfn[i++] = c;
+		}
+	}
+	*path = p + si;						/* Return pointer to the next segment */
+	if (i == 0) return FR_INVALID_NAME;	/* Reject nul string */
+
+	if (sfn[0] == DDEM) sfn[0] = RDDEM;	/* If the first character collides with DDEM, replace it with RDDEM */
+	sfn[NSFLAG] = (c <= ' ') ? NS_LAST : 0;		/* Set last segment flag if end of the path */
+
+	return FR_OK;
+#endif /* _USE_LFN != 0 */
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Follow a file path                                                    */
+/*-----------------------------------------------------------------------*/
+
+static
+FRESULT follow_path (	/* FR_OK(0): successful, !=0: error code */
+	DIR* dp,			/* Directory object to return last directory and found object */
+	const TCHAR* path	/* Full-path string to find a file or directory */
+)
+{
+	FRESULT res;
+	BYTE ns;
+	_FDID *obj = &dp->obj;
+	FATFS *fs = obj->fs;
+
+
+#if _FS_RPATH != 0
+	if (*path != '/' && *path != '\\') {	/* Without heading separator */
+		obj->sclust = fs->cdir;				/* Start from current directory */
+	} else
+#endif
+	{										/* With heading separator */
+		while (*path == '/' || *path == '\\') path++;	/* Strip heading separator */
+		obj->sclust = 0;					/* Start from root directory */
+	}
+#if _FS_EXFAT
+	obj->n_frag = 0;	/* Invalidate last fragment counter of the object */
+#if _FS_RPATH != 0
+	if (fs->fs_type == FS_EXFAT && obj->sclust) {	/* Retrieve the sub-directory status if needed */
+		DIR dj;
+
+		obj->c_scl = fs->cdc_scl;
+		obj->c_size = fs->cdc_size;
+		obj->c_ofs = fs->cdc_ofs;
+		res = load_obj_dir(&dj, obj);
+		if (res != FR_OK) return res;
+		obj->objsize = ld_dword(fs->dirbuf + XDIR_FileSize);
+		obj->stat = fs->dirbuf[XDIR_GenFlags] & 2;
+	}
+#endif
+#endif
+
+	if ((UINT)*path < ' ') {				/* Null path name is the origin directory itself */
+		dp->fn[NSFLAG] = NS_NONAME;
+		res = dir_sdi(dp, 0);
+
+	} else {								/* Follow path */
+		for (;;) {
+			res = create_name(dp, &path);	/* Get a segment name of the path */
+			if (res != FR_OK) break;
+			res = dir_find(dp);				/* Find an object with the segment name */
+			ns = dp->fn[NSFLAG];
+			if (res != FR_OK) {				/* Failed to find the object */
+				if (res == FR_NO_FILE) {	/* Object is not found */
+					if (_FS_RPATH && (ns & NS_DOT)) {	/* If dot entry is not exist, stay there */
+						if (!(ns & NS_LAST)) continue;	/* Continue to follow if not last segment */
+						dp->fn[NSFLAG] = NS_NONAME;
+						res = FR_OK;
+					} else {							/* Could not find the object */
+						if (!(ns & NS_LAST)) res = FR_NO_PATH;	/* Adjust error code if not last segment */
+					}
+				}
+				break;
+			}
+			if (ns & NS_LAST) break;			/* Last segment matched. Function completed. */
+			/* Get into the sub-directory */
+			if (!(obj->attr & AM_DIR)) {		/* It is not a sub-directory and cannot follow */
+				res = FR_NO_PATH; break;
+			}
+#if _FS_EXFAT
+			if (fs->fs_type == FS_EXFAT) {		/* Save containing directory information for next dir */
+				obj->c_scl = obj->sclust;
+				obj->c_size = ((DWORD)obj->objsize & 0xFFFFFF00) | obj->stat;
+				obj->c_ofs = dp->blk_ofs;
+				obj->sclust = ld_dword(fs->dirbuf + XDIR_FstClus);	/* Open next directory */
+				obj->stat = fs->dirbuf[XDIR_GenFlags] & 2;
+				obj->objsize = ld_qword(fs->dirbuf + XDIR_FileSize);
+			} else
+#endif
+			{
+				obj->sclust = ld_clust(fs, fs->win + dp->dptr % SS(fs));	/* Open next directory */
+			}
+		}
+	}
+
+	return res;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Get logical drive number from path name                               */
+/*-----------------------------------------------------------------------*/
+
+static
+int get_ldnumber (		/* Returns logical drive number (-1:invalid drive) */
+	const TCHAR** path	/* Pointer to pointer to the path name */
+)
+{
+	const TCHAR *tp, *tt;
+	UINT i;
+	int vol = -1;
+#if _STR_VOLUME_ID		/* Find string drive id */
+	static const char* const volid[] = {_VOLUME_STRS};
+	const char *sp;
+	char c;
+	TCHAR tc;
+#endif
+
+
+	if (*path) {	/* If the pointer is not a null */
+		for (tt = *path; (UINT)*tt >= (_USE_LFN ? ' ' : '!') && *tt != ':'; tt++) ;	/* Find ':' in the path */
+		if (*tt == ':') {	/* If a ':' is exist in the path name */
+			tp = *path;
+			i = *tp++ - '0';
+			if (i < 10 && tp == tt) {	/* Is there a numeric drive id? */
+				if (i < _VOLUMES) {	/* If a drive id is found, get the value and strip it */
+					vol = (int)i;
+					*path = ++tt;
+				}
+			}
+#if _STR_VOLUME_ID
+			 else {	/* No numeric drive number, find string drive id */
+				i = 0; tt++;
+				do {
+					sp = volid[i]; tp = *path;
+					do {	/* Compare a string drive id with path name */
+						c = *sp++; tc = *tp++;
+						if (IsLower(tc)) tc -= 0x20;
+					} while (c && (TCHAR)c == tc);
+				} while ((c || tp != tt) && ++i < _VOLUMES);	/* Repeat for each id until pattern match */
+				if (i < _VOLUMES) {	/* If a drive id is found, get the value and strip it */
+					vol = (int)i;
+					*path = tt;
+				}
+			}
+#endif
+			return vol;
+		}
+#if _FS_RPATH != 0 && _VOLUMES >= 2
+		vol = CurrVol;	/* Current drive */
+#else
+		vol = 0;		/* Drive 0 */
+#endif
+	}
+	return vol;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Load a sector and check if it is an FAT boot sector                   */
+/*-----------------------------------------------------------------------*/
+
+static
+BYTE check_fs (	/* 0:FAT, 1:exFAT, 2:Valid BS but not FAT, 3:Not a BS, 4:Disk error */
+	FATFS* fs,	/* File system object */
+	DWORD sect	/* Sector# (lba) to load and check if it is an FAT-VBR or not */
+)
+{
+	fs->wflag = 0; fs->winsect = 0xFFFFFFFF;		/* Invaidate window */
+	if (move_window(fs, sect) != FR_OK) return 4;	/* Load boot record */
+
+	if (ld_word(fs->win + BS_55AA) != 0xAA55) return 3;	/* Check boot record signature (always placed here even if the sector size is >512) */
+
+	if (fs->win[BS_JmpBoot] == 0xE9 || (fs->win[BS_JmpBoot] == 0xEB && fs->win[BS_JmpBoot + 2] == 0x90)) {
+		if ((ld_dword(fs->win + BS_FilSysType) & 0xFFFFFF) == 0x544146) return 0;	/* Check "FAT" string */
+		if (ld_dword(fs->win + BS_FilSysType32) == 0x33544146) return 0;			/* Check "FAT3" string */
+	}
+#if _FS_EXFAT
+	if (!mem_cmp(fs->win + BS_JmpBoot, "\xEB\x76\x90" "EXFAT   ", 11)) return 1;
+#endif
+	return 2;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Find logical drive and check if the volume is mounted                 */
+/*-----------------------------------------------------------------------*/
+
+static
+FRESULT find_volume (	/* FR_OK(0): successful, !=0: any error occurred */
+	const TCHAR** path,	/* Pointer to pointer to the path name (drive number) */
+	FATFS** rfs,		/* Pointer to pointer to the found file system object */
+	BYTE mode			/* !=0: Check write protection for write access */
+)
+{
+	BYTE fmt, *pt;
+	int vol;
+	DSTATUS stat;
+	DWORD bsect, fasize, tsect, sysect, nclst, szbfat, br[4];
+	WORD nrsv;
+	FATFS *fs;
+	UINT i;
+
+
+	/* Get logical drive number */
+	*rfs = 0;
+	vol = get_ldnumber(path);
+	if (vol < 0) return FR_INVALID_DRIVE;
+
+	/* Check if the file system object is valid or not */
+	fs = FatFs[vol];					/* Get pointer to the file system object */
+	if (!fs) return FR_NOT_ENABLED;		/* Is the file system object available? */
+
+	ENTER_FF(fs);						/* Lock the volume */
+	*rfs = fs;							/* Return pointer to the file system object */
+
+	mode &= (BYTE)~FA_READ;				/* Desired access mode, write access or not */
+	if (fs->fs_type) {					/* If the volume has been mounted */
+		stat = disk_status(fs->drv);
+		if (!(stat & STA_NOINIT)) {		/* and the physical drive is kept initialized */
+			if (!_FS_READONLY && mode && (stat & STA_PROTECT)) {	/* Check write protection if needed */
+				return FR_WRITE_PROTECTED;
+			}
+			return FR_OK;				/* The file system object is valid */
+		}
+	}
+
+	/* The file system object is not valid. */
+	/* Following code attempts to mount the volume. (analyze BPB and initialize the fs object) */
+
+	fs->fs_type = 0;					/* Clear the file system object */
+	fs->drv = LD2PD(vol);				/* Bind the logical drive and a physical drive */
+	stat = disk_initialize(fs->drv);	/* Initialize the physical drive */
+	if (stat & STA_NOINIT) { 			/* Check if the initialization succeeded */
+		return FR_NOT_READY;			/* Failed to initialize due to no medium or hard error */
+	}
+	if (!_FS_READONLY && mode && (stat & STA_PROTECT)) { /* Check disk write protection if needed */
+		return FR_WRITE_PROTECTED;
+	}
+#if _MAX_SS != _MIN_SS					/* Get sector size (multiple sector size cfg only) */
+	if (disk_ioctl(fs->drv, GET_SECTOR_SIZE, &SS(fs)) != RES_OK) return FR_DISK_ERR;
+	if (SS(fs) > _MAX_SS || SS(fs) < _MIN_SS || (SS(fs) & (SS(fs) - 1))) return FR_DISK_ERR;
+#endif
+
+	/* Find an FAT partition on the drive. Supports only generic partitioning rules, FDISK and SFD. */
+	bsect = 0;
+	fmt = check_fs(fs, bsect);			/* Load sector 0 and check if it is an FAT-VBR as SFD */
+	if (fmt == 2 || (fmt < 2 && LD2PT(vol) != 0)) {	/* Not an FAT-VBR or forced partition number */
+		for (i = 0; i < 4; i++) {		/* Get partition offset */
+			pt = fs->win + (MBR_Table + i * SZ_PTE);
+			br[i] = pt[PTE_System] ? ld_dword(pt + PTE_StLba) : 0;
+		}
+		i = LD2PT(vol);					/* Partition number: 0:auto, 1-4:forced */
+		if (i) i--;
+		do {							/* Find an FAT volume */
+			bsect = br[i];
+			fmt = bsect ? check_fs(fs, bsect) : 3;	/* Check the partition */
+		} while (LD2PT(vol) == 0 && fmt >= 2 && ++i < 4);
+	}
+	if (fmt == 4) return FR_DISK_ERR;		/* An error occured in the disk I/O layer */
+	if (fmt >= 2) return FR_NO_FILESYSTEM;	/* No FAT volume is found */
+
+	/* An FAT volume is found (bsect). Following code initializes the file system object */
+
+#if _FS_EXFAT
+	if (fmt == 1) {
+		QWORD maxlba;
+
+		for (i = BPB_ZeroedEx; i < BPB_ZeroedEx + 53 && fs->win[i] == 0; i++) ;	/* Check zero filler */
+		if (i < BPB_ZeroedEx + 53) return FR_NO_FILESYSTEM;
+
+		if (ld_word(fs->win + BPB_FSVerEx) != 0x100) return FR_NO_FILESYSTEM;	/* Check exFAT revision (Must be 1.0) */
+
+		if (1 << fs->win[BPB_BytsPerSecEx] != SS(fs)) {	/* (BPB_BytsPerSecEx must be equal to the physical sector size) */
+			return FR_NO_FILESYSTEM;
+		}
+
+		maxlba = ld_qword(fs->win + BPB_TotSecEx) + bsect;	/* Last LBA + 1 of the volume */
+		if (maxlba >= 0x100000000) return FR_NO_FILESYSTEM;	/* (It cannot be handled in 32-bit LBA) */
+
+		fs->fsize = ld_dword(fs->win + BPB_FatSzEx);	/* Number of sectors per FAT */
+
+		fs->n_fats = fs->win[BPB_NumFATsEx];			/* Number of FATs */
+		if (fs->n_fats != 1) return FR_NO_FILESYSTEM;	/* (Supports only 1 FAT) */
+
+		fs->csize = 1 << fs->win[BPB_SecPerClusEx];		/* Cluster size */
+		if (fs->csize == 0)	return FR_NO_FILESYSTEM;	/* (Must be 1..32768) */
+
+		nclst = ld_dword(fs->win + BPB_NumClusEx);		/* Number of clusters */
+		if (nclst > MAX_EXFAT) return FR_NO_FILESYSTEM;	/* (Too many clusters) */
+		fs->n_fatent = nclst + 2;
+
+		/* Boundaries and Limits */
+		fs->volbase = bsect;
+		fs->database = bsect + ld_dword(fs->win + BPB_DataOfsEx);
+		fs->fatbase = bsect + ld_dword(fs->win + BPB_FatOfsEx);
+		if (maxlba < (QWORD)fs->database + nclst * fs->csize) return FR_NO_FILESYSTEM;	/* (Volume size must not be smaller than the size requiered) */
+		fs->dirbase = ld_dword(fs->win + BPB_RootClusEx);
+
+		/* Check if bitmap location is in assumption (at the first cluster) */
+		if (move_window(fs, clust2sect(fs, fs->dirbase)) != FR_OK) return FR_DISK_ERR;
+		for (i = 0; i < SS(fs); i += SZDIRE) {
+			if (fs->win[i] == 0x81 && ld_dword(fs->win + i + 20) == 2) break;	/* 81 entry with cluster #2? */
+		}
+		if (i == SS(fs)) return FR_NO_FILESYSTEM;
+#if !_FS_READONLY
+		fs->last_clst = fs->free_clst = 0xFFFFFFFF;		/* Initialize cluster allocation information */
+#endif
+		fmt = FS_EXFAT;			/* FAT sub-type */
+	} else
+#endif	/* _FS_EXFAT */
+	{
+		if (ld_word(fs->win + BPB_BytsPerSec) != SS(fs)) return FR_NO_FILESYSTEM;	/* (BPB_BytsPerSec must be equal to the physical sector size) */
+
+		fasize = ld_word(fs->win + BPB_FATSz16);		/* Number of sectors per FAT */
+		if (fasize == 0) fasize = ld_dword(fs->win + BPB_FATSz32);
+		fs->fsize = fasize;
+
+		fs->n_fats = fs->win[BPB_NumFATs];				/* Number of FATs */
+		if (fs->n_fats != 1 && fs->n_fats != 2) return FR_NO_FILESYSTEM;	/* (Must be 1 or 2) */
+		fasize *= fs->n_fats;							/* Number of sectors for FAT area */
+
+		fs->csize = fs->win[BPB_SecPerClus];			/* Cluster size */
+		if (fs->csize == 0 || (fs->csize & (fs->csize - 1))) return FR_NO_FILESYSTEM;	/* (Must be power of 2) */
+
+		fs->n_rootdir = ld_word(fs->win + BPB_RootEntCnt);	/* Number of root directory entries */
+		if (fs->n_rootdir % (SS(fs) / SZDIRE)) return FR_NO_FILESYSTEM;	/* (Must be sector aligned) */
+
+		tsect = ld_word(fs->win + BPB_TotSec16);		/* Number of sectors on the volume */
+		if (tsect == 0) tsect = ld_dword(fs->win + BPB_TotSec32);
+
+		nrsv = ld_word(fs->win + BPB_RsvdSecCnt);		/* Number of reserved sectors */
+		if (nrsv == 0) return FR_NO_FILESYSTEM;			/* (Must not be 0) */
+
+		/* Determine the FAT sub type */
+		sysect = nrsv + fasize + fs->n_rootdir / (SS(fs) / SZDIRE);	/* RSV + FAT + DIR */
+		if (tsect < sysect) return FR_NO_FILESYSTEM;	/* (Invalid volume size) */
+		nclst = (tsect - sysect) / fs->csize;			/* Number of clusters */
+		if (nclst == 0) return FR_NO_FILESYSTEM;		/* (Invalid volume size) */
+		fmt = FS_FAT32;
+		if (nclst <= MAX_FAT16) fmt = FS_FAT16;
+		if (nclst <= MAX_FAT12) fmt = FS_FAT12;
+
+		/* Boundaries and Limits */
+		fs->n_fatent = nclst + 2;						/* Number of FAT entries */
+		fs->volbase = bsect;							/* Volume start sector */
+		fs->fatbase = bsect + nrsv; 					/* FAT start sector */
+		fs->database = bsect + sysect;					/* Data start sector */
+		if (fmt == FS_FAT32) {
+			if (ld_word(fs->win + BPB_FSVer32) != 0) return FR_NO_FILESYSTEM;	/* (Must be FAT32 revision 0.0) */
+			if (fs->n_rootdir) return FR_NO_FILESYSTEM;	/* (BPB_RootEntCnt must be 0) */
+			fs->dirbase = ld_dword(fs->win + BPB_RootClus32);	/* Root directory start cluster */
+			szbfat = fs->n_fatent * 4;					/* (Needed FAT size) */
+		} else {
+			if (fs->n_rootdir == 0)	return FR_NO_FILESYSTEM;/* (BPB_RootEntCnt must not be 0) */
+			fs->dirbase = fs->fatbase + fasize;			/* Root directory start sector */
+			szbfat = (fmt == FS_FAT16) ?				/* (Needed FAT size) */
+				fs->n_fatent * 2 : fs->n_fatent * 3 / 2 + (fs->n_fatent & 1);
+		}
+		if (fs->fsize < (szbfat + (SS(fs) - 1)) / SS(fs)) return FR_NO_FILESYSTEM;	/* (BPB_FATSz must not be less than the size needed) */
+
+#if !_FS_READONLY
+		/* Get FSINFO if available */
+		fs->last_clst = fs->free_clst = 0xFFFFFFFF;		/* Initialize cluster allocation information */
+		fs->fsi_flag = 0x80;
+#if (_FS_NOFSINFO & 3) != 3
+		if (fmt == FS_FAT32				/* Enable FSINFO only if FAT32 and BPB_FSInfo32 == 1 */
+			&& ld_word(fs->win + BPB_FSInfo32) == 1
+			&& move_window(fs, bsect + 1) == FR_OK)
+		{
+			fs->fsi_flag = 0;
+			if (ld_word(fs->win + BS_55AA) == 0xAA55	/* Load FSINFO data if available */
+				&& ld_dword(fs->win + FSI_LeadSig) == 0x41615252
+				&& ld_dword(fs->win + FSI_StrucSig) == 0x61417272)
+			{
+#if (_FS_NOFSINFO & 1) == 0
+				fs->free_clst = ld_dword(fs->win + FSI_Free_Count);
+#endif
+#if (_FS_NOFSINFO & 2) == 0
+				fs->last_clst = ld_dword(fs->win + FSI_Nxt_Free);
+#endif
+			}
+		}
+#endif	/* (_FS_NOFSINFO & 3) != 3 */
+#endif	/* !_FS_READONLY */
+	}
+
+	fs->fs_type = fmt;		/* FAT sub-type */
+	fs->id = ++Fsid;		/* File system mount ID */
+#if _USE_LFN == 1
+	fs->lfnbuf = LfnBuf;	/* Static LFN working buffer */
+#if _FS_EXFAT
+	fs->dirbuf = DirBuf;	/* Static directory block scratchpad buuffer */
+#endif
+#endif
+#if _FS_RPATH != 0
+	fs->cdir = 0;			/* Initialize current directory */
+#endif
+#if _FS_LOCK != 0			/* Clear file lock semaphores */
+	clear_lock(fs);
+#endif
+	return FR_OK;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Check if the file/directory object is valid or not                    */
+/*-----------------------------------------------------------------------*/
+
+static
+FRESULT validate (	/* Returns FR_OK or FR_INVALID_OBJECT */
+	_FDID* obj,		/* Pointer to the _OBJ, the 1st member in the FIL/DIR object, to check validity */
+	FATFS** fs		/* Pointer to pointer to the owner file system object to return */
+)
+{
+	FRESULT res = FR_INVALID_OBJECT;
+
+
+	if (obj && obj->fs && obj->fs->fs_type && obj->id == obj->fs->id) {	/* Test if the object is valid */
+#if _FS_REENTRANT
+		if (lock_fs(obj->fs)) {	/* Obtain the filesystem object */
+			if (!(disk_status(obj->fs->drv) & STA_NOINIT)) { /* Test if the phsical drive is kept initialized */
+				res = FR_OK;
+			} else {
+				unlock_fs(obj->fs, FR_OK);
+			}
+		} else {
+			res = FR_TIMEOUT;
+		}
+#else
+		if (!(disk_status(obj->fs->drv) & STA_NOINIT)) { /* Test if the phsical drive is kept initialized */
+			res = FR_OK;
+		}
+#endif
+	}
+	*fs = (res == FR_OK) ? obj->fs : 0;	/* Corresponding filesystem object */
+	return res;
+}
+
+
+
+
+/*---------------------------------------------------------------------------
+
+   Public Functions (FatFs API)
+
+----------------------------------------------------------------------------*/
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Mount/Unmount a Logical Drive                                         */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_mount (
+	FATFS* fs,			/* Pointer to the file system object (NULL:unmount)*/
+	const TCHAR* path,	/* Logical drive number to be mounted/unmounted */
+	BYTE opt			/* Mode option 0:Do not mount (delayed mount), 1:Mount immediately */
+)
+{
+	FATFS *cfs;
+	int vol;
+	FRESULT res;
+	const TCHAR *rp = path;
+
+
+	/* Get logical drive number */
+	vol = get_ldnumber(&rp);
+	if (vol < 0) return FR_INVALID_DRIVE;
+	cfs = FatFs[vol];					/* Pointer to fs object */
+
+	if (cfs) {
+#if _FS_LOCK != 0
+		clear_lock(cfs);
+#endif
+#if _FS_REENTRANT						/* Discard sync object of the current volume */
+		if (!ff_del_syncobj(cfs->sobj)) return FR_INT_ERR;
+#endif
+		cfs->fs_type = 0;				/* Clear old fs object */
+	}
+
+	if (fs) {
+		fs->fs_type = 0;				/* Clear new fs object */
+#if _FS_REENTRANT						/* Create sync object for the new volume */
+		if (!ff_cre_syncobj((BYTE)vol, &fs->sobj)) return FR_INT_ERR;
+#endif
+	}
+	FatFs[vol] = fs;					/* Register new fs object */
+
+	if (!fs || opt != 1) return FR_OK;	/* Do not mount now, it will be mounted later */
+
+	res = find_volume(&path, &fs, 0);	/* Force mounted the volume */
+	LEAVE_FF(fs, res);
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Open or Create a File                                                 */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_open (
+	FIL* fp,			/* Pointer to the blank file object */
+	const TCHAR* path,	/* Pointer to the file name */
+	BYTE mode			/* Access mode and file open mode flags */
+)
+{
+	FRESULT res;
+	DIR dj;
+	FATFS *fs;
+#if !_FS_READONLY
+	DWORD dw, cl, bcs, clst, sc;
+	FSIZE_t ofs;
+#endif
+	DEF_NAMBUF
+
+
+	if (!fp) return FR_INVALID_OBJECT;
+
+	/* Get logical drive */
+	mode &= _FS_READONLY ? FA_READ : FA_READ | FA_WRITE | FA_CREATE_ALWAYS | FA_CREATE_NEW | FA_OPEN_ALWAYS | FA_OPEN_APPEND | FA_SEEKEND;
+	res = find_volume(&path, &fs, mode);
+	if (res == FR_OK) {
+		dj.obj.fs = fs;
+		INIT_NAMBUF(fs);
+		res = follow_path(&dj, path);	/* Follow the file path */
+#if !_FS_READONLY	/* R/W configuration */
+		if (res == FR_OK) {
+			if (dj.fn[NSFLAG] & NS_NONAME) {	/* Origin directory itself? */
+				res = FR_INVALID_NAME;
+			}
+#if _FS_LOCK != 0
+			else {
+				res = chk_lock(&dj, (mode & ~FA_READ) ? 1 : 0);
+			}
+#endif
+		}
+		/* Create or Open a file */
+		if (mode & (FA_CREATE_ALWAYS | FA_OPEN_ALWAYS | FA_CREATE_NEW)) {
+			if (res != FR_OK) {					/* No file, create new */
+				if (res == FR_NO_FILE) {		/* There is no file to open, create a new entry */
+#if _FS_LOCK != 0
+					res = enq_lock() ? dir_register(&dj) : FR_TOO_MANY_OPEN_FILES;
+#else
+					res = dir_register(&dj);
+#endif
+				}
+				mode |= FA_CREATE_ALWAYS;		/* File is created */
+			}
+			else {								/* Any object is already existing */
+				if (dj.obj.attr & (AM_RDO | AM_DIR)) {	/* Cannot overwrite it (R/O or DIR) */
+					res = FR_DENIED;
+				} else {
+					if (mode & FA_CREATE_NEW) res = FR_EXIST;	/* Cannot create as new file */
+				}
+			}
+			if (res == FR_OK && (mode & FA_CREATE_ALWAYS)) {	/* Truncate it if overwrite mode */
+				dw = GET_FATTIME();
+#if _FS_EXFAT
+				if (fs->fs_type == FS_EXFAT) {
+					/* Get current allocation info */
+					fp->obj.fs = fs;
+					fp->obj.sclust = ld_dword(fs->dirbuf + XDIR_FstClus);
+					fp->obj.objsize = ld_qword(fs->dirbuf + XDIR_FileSize);
+					fp->obj.stat = fs->dirbuf[XDIR_GenFlags] & 2;
+					fp->obj.n_frag = 0;
+					/* Initialize directory entry block */
+					st_dword(fs->dirbuf + XDIR_CrtTime, dw);	/* Set created time */
+					fs->dirbuf[XDIR_CrtTime10] = 0;
+					st_dword(fs->dirbuf + XDIR_ModTime, dw);	/* Set modified time */
+					fs->dirbuf[XDIR_ModTime10] = 0;
+					fs->dirbuf[XDIR_Attr] = AM_ARC;				/* Reset attribute */
+					st_dword(fs->dirbuf + XDIR_FstClus, 0);		/* Reset file allocation info */
+					st_qword(fs->dirbuf + XDIR_FileSize, 0);
+					st_qword(fs->dirbuf + XDIR_ValidFileSize, 0);
+					fs->dirbuf[XDIR_GenFlags] = 1;
+					res = store_xdir(&dj);
+					if (res == FR_OK && fp->obj.sclust) {		/* Remove the cluster chain if exist */
+						res = remove_chain(&fp->obj, fp->obj.sclust, 0);
+						fs->last_clst = fp->obj.sclust - 1;		/* Reuse the cluster hole */
+					}
+				} else
+#endif
+				{
+					/* Clean directory info */
+					st_dword(dj.dir + DIR_CrtTime, dw);	/* Set created time */
+					st_dword(dj.dir + DIR_ModTime, dw);	/* Set modified time */
+					dj.dir[DIR_Attr] = AM_ARC;			/* Reset attribute */
+					cl = ld_clust(fs, dj.dir);			/* Get cluster chain */
+					st_clust(fs, dj.dir, 0);			/* Reset file allocation info */
+					st_dword(dj.dir + DIR_FileSize, 0);
+					fs->wflag = 1;
+
+					if (cl) {							/* Remove the cluster chain if exist */
+						dw = fs->winsect;
+						res = remove_chain(&dj.obj, cl, 0);
+						if (res == FR_OK) {
+							res = move_window(fs, dw);
+							fs->last_clst = cl - 1;		/* Reuse the cluster hole */
+						}
+					}
+				}
+			}
+		}
+		else {	/* Open an existing file */
+			if (res == FR_OK) {					/* Following succeeded */
+				if (dj.obj.attr & AM_DIR) {		/* It is a directory */
+					res = FR_NO_FILE;
+				} else {
+					if ((mode & FA_WRITE) && (dj.obj.attr & AM_RDO)) { /* R/O violation */
+						res = FR_DENIED;
+					}
+				}
+			}
+		}
+		if (res == FR_OK) {
+			if (mode & FA_CREATE_ALWAYS)		/* Set file change flag if created or overwritten */
+				mode |= FA_MODIFIED;
+			fp->dir_sect = fs->winsect;			/* Pointer to the directory entry */
+			fp->dir_ptr = dj.dir;
+#if _FS_LOCK != 0
+			fp->obj.lockid = inc_lock(&dj, (mode & ~FA_READ) ? 1 : 0);
+			if (!fp->obj.lockid) res = FR_INT_ERR;
+#endif
+		}
+#else		/* R/O configuration */
+		if (res == FR_OK) {
+			if (dj.fn[NSFLAG] & NS_NONAME) {	/* Origin directory itself? */
+				res = FR_INVALID_NAME;
+			} else {
+				if (dj.obj.attr & AM_DIR) {		/* It is a directory */
+					res = FR_NO_FILE;
+				}
+			}
+		}
+#endif
+
+		if (res == FR_OK) {
+#if _FS_EXFAT
+			if (fs->fs_type == FS_EXFAT) {
+				fp->obj.c_scl = dj.obj.sclust;							/* Get containing directory info */
+				fp->obj.c_size = ((DWORD)dj.obj.objsize & 0xFFFFFF00) | dj.obj.stat;
+				fp->obj.c_ofs = dj.blk_ofs;
+				fp->obj.sclust = ld_dword(fs->dirbuf + XDIR_FstClus);	/* Get object allocation info */
+				fp->obj.objsize = ld_qword(fs->dirbuf + XDIR_FileSize);
+				fp->obj.stat = fs->dirbuf[XDIR_GenFlags] & 2;
+			} else
+#endif
+			{
+				fp->obj.sclust = ld_clust(fs, dj.dir);					/* Get object allocation info */
+				fp->obj.objsize = ld_dword(dj.dir + DIR_FileSize);
+			}
+#if _USE_FASTSEEK
+			fp->cltbl = 0;			/* Disable fast seek mode */
+#endif
+			fp->obj.fs = fs;	 	/* Validate the file object */
+			fp->obj.id = fs->id;
+			fp->flag = mode;		/* Set file access mode */
+			fp->err = 0;			/* Clear error flag */
+			fp->sect = 0;			/* Invalidate current data sector */
+			fp->fptr = 0;			/* Set file pointer top of the file */
+#if !_FS_READONLY
+#if !_FS_TINY
+			mem_set(fp->buf, 0, _MAX_SS);	/* Clear sector buffer */
+#endif
+			if ((mode & FA_SEEKEND) && fp->obj.objsize > 0) {	/* Seek to end of file if FA_OPEN_APPEND is specified */
+				fp->fptr = fp->obj.objsize;			/* Offset to seek */
+				bcs = (DWORD)fs->csize * SS(fs);	/* Cluster size in byte */
+				clst = fp->obj.sclust;				/* Follow the cluster chain */
+				for (ofs = fp->obj.objsize; res == FR_OK && ofs > bcs; ofs -= bcs) {
+					clst = get_fat(&fp->obj, clst);
+					if (clst <= 1) res = FR_INT_ERR;
+					if (clst == 0xFFFFFFFF) res = FR_DISK_ERR;
+				}
+				fp->clust = clst;
+				if (res == FR_OK && ofs % SS(fs)) {	/* Fill sector buffer if not on the sector boundary */
+					if ((sc = clust2sect(fs, clst)) == 0) {
+						res = FR_INT_ERR;
+					} else {
+						fp->sect = sc + (DWORD)(ofs / SS(fs));
+#if !_FS_TINY
+						if (disk_read(fs->drv, fp->buf, fp->sect, 1) != RES_OK) res = FR_DISK_ERR;
+#endif
+					}
+				}
+			}
+#endif
+		}
+
+		FREE_NAMBUF();
+	}
+
+	if (res != FR_OK) fp->obj.fs = 0;	/* Invalidate file object on error */
+
+	LEAVE_FF(fs, res);
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Read File                                                             */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_read (
+	FIL* fp, 	/* Pointer to the file object */
+	void* buff,	/* Pointer to data buffer */
+	UINT btr,	/* Number of bytes to read */
+	UINT* br	/* Pointer to number of bytes read */
+)
+{
+	FRESULT res;
+	FATFS *fs;
+	DWORD clst, sect;
+	FSIZE_t remain;
+	UINT rcnt, cc, csect;
+	BYTE *rbuff = (BYTE*)buff;
+
+
+	*br = 0;	/* Clear read byte counter */
+	res = validate(&fp->obj, &fs);				/* Check validity of the file object */
+	if (res != FR_OK || (res = (FRESULT)fp->err) != FR_OK) LEAVE_FF(fs, res);	/* Check validity */
+	if (!(fp->flag & FA_READ)) LEAVE_FF(fs, FR_DENIED); /* Check access mode */
+	remain = fp->obj.objsize - fp->fptr;
+	if (btr > remain) btr = (UINT)remain;		/* Truncate btr by remaining bytes */
+
+	for ( ;  btr;								/* Repeat until all data read */
+		rbuff += rcnt, fp->fptr += rcnt, *br += rcnt, btr -= rcnt) {
+		if (fp->fptr % SS(fs) == 0) {			/* On the sector boundary? */
+			csect = (UINT)(fp->fptr / SS(fs) & (fs->csize - 1));	/* Sector offset in the cluster */
+			if (csect == 0) {					/* On the cluster boundary? */
+				if (fp->fptr == 0) {			/* On the top of the file? */
+					clst = fp->obj.sclust;		/* Follow cluster chain from the origin */
+				} else {						/* Middle or end of the file */
+#if _USE_FASTSEEK
+					if (fp->cltbl) {
+						clst = clmt_clust(fp, fp->fptr);	/* Get cluster# from the CLMT */
+					} else
+#endif
+					{
+						clst = get_fat(&fp->obj, fp->clust);	/* Follow cluster chain on the FAT */
+					}
+				}
+				if (clst < 2) ABORT(fs, FR_INT_ERR);
+				if (clst == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR);
+				fp->clust = clst;				/* Update current cluster */
+			}
+			sect = clust2sect(fs, fp->clust);	/* Get current sector */
+			if (!sect) ABORT(fs, FR_INT_ERR);
+			sect += csect;
+			cc = btr / SS(fs);					/* When remaining bytes >= sector size, */
+			if (cc) {							/* Read maximum contiguous sectors directly */
+				if (csect + cc > fs->csize) {	/* Clip at cluster boundary */
+					cc = fs->csize - csect;
+				}
+				if (disk_read(fs->drv, rbuff, sect, cc) != RES_OK) ABORT(fs, FR_DISK_ERR);
+#if !_FS_READONLY && _FS_MINIMIZE <= 2			/* Replace one of the read sectors with cached data if it contains a dirty sector */
+#if _FS_TINY
+				if (fs->wflag && fs->winsect - sect < cc) {
+					mem_cpy(rbuff + ((fs->winsect - sect) * SS(fs)), fs->win, SS(fs));
+				}
+#else
+				if ((fp->flag & FA_DIRTY) && fp->sect - sect < cc) {
+					mem_cpy(rbuff + ((fp->sect - sect) * SS(fs)), fp->buf, SS(fs));
+				}
+#endif
+#endif
+				rcnt = SS(fs) * cc;				/* Number of bytes transferred */
+				continue;
+			}
+#if !_FS_TINY
+			if (fp->sect != sect) {			/* Load data sector if not in cache */
+#if !_FS_READONLY
+				if (fp->flag & FA_DIRTY) {		/* Write-back dirty sector cache */
+					if (disk_write(fs->drv, fp->buf, fp->sect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR);
+					fp->flag &= (BYTE)~FA_DIRTY;
+				}
+#endif
+				if (disk_read(fs->drv, fp->buf, sect, 1) != RES_OK)	ABORT(fs, FR_DISK_ERR);	/* Fill sector cache */
+			}
+#endif
+			fp->sect = sect;
+		}
+		rcnt = SS(fs) - (UINT)fp->fptr % SS(fs);	/* Number of bytes left in the sector */
+		if (rcnt > btr) rcnt = btr;					/* Clip it by btr if needed */
+#if _FS_TINY
+		if (move_window(fs, fp->sect) != FR_OK) ABORT(fs, FR_DISK_ERR);	/* Move sector window */
+		mem_cpy(rbuff, fs->win + fp->fptr % SS(fs), rcnt);	/* Extract partial sector */
+#else
+		mem_cpy(rbuff, fp->buf + fp->fptr % SS(fs), rcnt);	/* Extract partial sector */
+#endif
+	}
+
+	LEAVE_FF(fs, FR_OK);
+}
+
+
+
+
+#if !_FS_READONLY
+/*-----------------------------------------------------------------------*/
+/* Write File                                                            */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_write (
+	FIL* fp,			/* Pointer to the file object */
+	const void* buff,	/* Pointer to the data to be written */
+	UINT btw,			/* Number of bytes to write */
+	UINT* bw			/* Pointer to number of bytes written */
+)
+{
+	FRESULT res;
+	FATFS *fs;
+	DWORD clst, sect;
+	UINT wcnt, cc, csect;
+	const BYTE *wbuff = (const BYTE*)buff;
+
+
+	*bw = 0;	/* Clear write byte counter */
+	res = validate(&fp->obj, &fs);			/* Check validity of the file object */
+	if (res != FR_OK || (res = (FRESULT)fp->err) != FR_OK) LEAVE_FF(fs, res);	/* Check validity */
+	if (!(fp->flag & FA_WRITE)) LEAVE_FF(fs, FR_DENIED);	/* Check access mode */
+
+	/* Check fptr wrap-around (file size cannot reach 4GiB on FATxx) */
+	if ((!_FS_EXFAT || fs->fs_type != FS_EXFAT) && (DWORD)(fp->fptr + btw) < (DWORD)fp->fptr) {
+		btw = (UINT)(0xFFFFFFFF - (DWORD)fp->fptr);
+	}
+
+	for ( ;  btw;							/* Repeat until all data written */
+		wbuff += wcnt, fp->fptr += wcnt, fp->obj.objsize = (fp->fptr > fp->obj.objsize) ? fp->fptr : fp->obj.objsize, *bw += wcnt, btw -= wcnt) {
+		if (fp->fptr % SS(fs) == 0) {		/* On the sector boundary? */
+			csect = (UINT)(fp->fptr / SS(fs)) & (fs->csize - 1);	/* Sector offset in the cluster */
+			if (csect == 0) {				/* On the cluster boundary? */
+				if (fp->fptr == 0) {		/* On the top of the file? */
+					clst = fp->obj.sclust;	/* Follow from the origin */
+					if (clst == 0) {		/* If no cluster is allocated, */
+						clst = create_chain(&fp->obj, 0);	/* create a new cluster chain */
+					}
+				} else {					/* On the middle or end of the file */
+#if _USE_FASTSEEK
+					if (fp->cltbl) {
+						clst = clmt_clust(fp, fp->fptr);	/* Get cluster# from the CLMT */
+					} else
+#endif
+					{
+						clst = create_chain(&fp->obj, fp->clust);	/* Follow or stretch cluster chain on the FAT */
+					}
+				}
+				if (clst == 0) break;		/* Could not allocate a new cluster (disk full) */
+				if (clst == 1) ABORT(fs, FR_INT_ERR);
+				if (clst == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR);
+				fp->clust = clst;			/* Update current cluster */
+				if (fp->obj.sclust == 0) fp->obj.sclust = clst;	/* Set start cluster if the first write */
+			}
+#if _FS_TINY
+			if (fs->winsect == fp->sect && sync_window(fs) != FR_OK) ABORT(fs, FR_DISK_ERR);	/* Write-back sector cache */
+#else
+			if (fp->flag & FA_DIRTY) {		/* Write-back sector cache */
+				if (disk_write(fs->drv, fp->buf, fp->sect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR);
+				fp->flag &= (BYTE)~FA_DIRTY;
+			}
+#endif
+			sect = clust2sect(fs, fp->clust);	/* Get current sector */
+			if (!sect) ABORT(fs, FR_INT_ERR);
+			sect += csect;
+			cc = btw / SS(fs);				/* When remaining bytes >= sector size, */
+			if (cc) {						/* Write maximum contiguous sectors directly */
+				if (csect + cc > fs->csize) {	/* Clip at cluster boundary */
+					cc = fs->csize - csect;
+				}
+				if (disk_write(fs->drv, wbuff, sect, cc) != RES_OK) ABORT(fs, FR_DISK_ERR);
+#if _FS_MINIMIZE <= 2
+#if _FS_TINY
+				if (fs->winsect - sect < cc) {	/* Refill sector cache if it gets invalidated by the direct write */
+					mem_cpy(fs->win, wbuff + ((fs->winsect - sect) * SS(fs)), SS(fs));
+					fs->wflag = 0;
+				}
+#else
+				if (fp->sect - sect < cc) { /* Refill sector cache if it gets invalidated by the direct write */
+					mem_cpy(fp->buf, wbuff + ((fp->sect - sect) * SS(fs)), SS(fs));
+					fp->flag &= (BYTE)~FA_DIRTY;
+				}
+#endif
+#endif
+				wcnt = SS(fs) * cc;		/* Number of bytes transferred */
+				continue;
+			}
+#if _FS_TINY
+			if (fp->fptr >= fp->obj.objsize) {	/* Avoid silly cache filling on the growing edge */
+				if (sync_window(fs) != FR_OK) ABORT(fs, FR_DISK_ERR);
+				fs->winsect = sect;
+			}
+#else
+			if (fp->sect != sect && 		/* Fill sector cache with file data */
+				fp->fptr < fp->obj.objsize &&
+				disk_read(fs->drv, fp->buf, sect, 1) != RES_OK) {
+					ABORT(fs, FR_DISK_ERR);
+			}
+#endif
+			fp->sect = sect;
+		}
+		wcnt = SS(fs) - (UINT)fp->fptr % SS(fs);	/* Number of bytes left in the sector */
+		if (wcnt > btw) wcnt = btw;					/* Clip it by btw if needed */
+#if _FS_TINY
+		if (move_window(fs, fp->sect) != FR_OK) ABORT(fs, FR_DISK_ERR);	/* Move sector window */
+		mem_cpy(fs->win + fp->fptr % SS(fs), wbuff, wcnt);	/* Fit data to the sector */
+		fs->wflag = 1;
+#else
+		mem_cpy(fp->buf + fp->fptr % SS(fs), wbuff, wcnt);	/* Fit data to the sector */
+		fp->flag |= FA_DIRTY;
+#endif
+	}
+
+	fp->flag |= FA_MODIFIED;				/* Set file change flag */
+
+	LEAVE_FF(fs, FR_OK);
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Synchronize the File                                                  */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_sync (
+	FIL* fp		/* Pointer to the file object */
+)
+{
+	FRESULT res;
+	FATFS *fs;
+	DWORD tm;
+	BYTE *dir;
+#if _FS_EXFAT
+	DIR dj;
+	DEF_NAMBUF
+#endif
+
+	res = validate(&fp->obj, &fs);	/* Check validity of the file object */
+	if (res == FR_OK) {
+		if (fp->flag & FA_MODIFIED) {	/* Is there any change to the file? */
+#if !_FS_TINY
+			if (fp->flag & FA_DIRTY) {	/* Write-back cached data if needed */
+				if (disk_write(fs->drv, fp->buf, fp->sect, 1) != RES_OK) LEAVE_FF(fs, FR_DISK_ERR);
+				fp->flag &= (BYTE)~FA_DIRTY;
+			}
+#endif
+			/* Update the directory entry */
+			tm = GET_FATTIME();				/* Modified time */
+#if _FS_EXFAT
+			if (fs->fs_type == FS_EXFAT) {
+				res = fill_first_frag(&fp->obj);	/* Fill first fragment on the FAT if needed */
+				if (res == FR_OK) {
+					res = fill_last_frag(&fp->obj, fp->clust, 0xFFFFFFFF);	/* Fill last fragment on the FAT if needed */
+				}
+				if (res == FR_OK) {
+					INIT_NAMBUF(fs);
+					res = load_obj_dir(&dj, &fp->obj);	/* Load directory entry block */
+					if (res == FR_OK) {
+						fs->dirbuf[XDIR_Attr] |= AM_ARC;				/* Set archive bit */
+						fs->dirbuf[XDIR_GenFlags] = fp->obj.stat | 1;	/* Update file allocation info */
+						st_dword(fs->dirbuf + XDIR_FstClus, fp->obj.sclust);
+						st_qword(fs->dirbuf + XDIR_FileSize, fp->obj.objsize);
+						st_qword(fs->dirbuf + XDIR_ValidFileSize, fp->obj.objsize);
+						st_dword(fs->dirbuf + XDIR_ModTime, tm);		/* Update modified time */
+						fs->dirbuf[XDIR_ModTime10] = 0;
+						st_dword(fs->dirbuf + XDIR_AccTime, 0);
+						res = store_xdir(&dj);	/* Restore it to the directory */
+						if (res == FR_OK) {
+							res = sync_fs(fs);
+							fp->flag &= (BYTE)~FA_MODIFIED;
+						}
+					}
+					FREE_NAMBUF();
+				}
+			} else
+#endif
+			{
+				res = move_window(fs, fp->dir_sect);
+				if (res == FR_OK) {
+					dir = fp->dir_ptr;
+					dir[DIR_Attr] |= AM_ARC;						/* Set archive bit */
+					st_clust(fp->obj.fs, dir, fp->obj.sclust);		/* Update file allocation info  */
+					st_dword(dir + DIR_FileSize, (DWORD)fp->obj.objsize);	/* Update file size */
+					st_dword(dir + DIR_ModTime, tm);				/* Update modified time */
+					st_word(dir + DIR_LstAccDate, 0);
+					fs->wflag = 1;
+					res = sync_fs(fs);					/* Restore it to the directory */
+					fp->flag &= (BYTE)~FA_MODIFIED;
+				}
+			}
+		}
+	}
+
+	LEAVE_FF(fs, res);
+}
+
+#endif /* !_FS_READONLY */
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Close File                                                            */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_close (
+	FIL* fp		/* Pointer to the file object to be closed */
+)
+{
+	FRESULT res;
+	FATFS *fs;
+
+#if !_FS_READONLY
+	res = f_sync(fp);					/* Flush cached data */
+	if (res == FR_OK)
+#endif
+	{
+		res = validate(&fp->obj, &fs);	/* Lock volume */
+		if (res == FR_OK) {
+#if _FS_LOCK != 0
+			res = dec_lock(fp->obj.lockid);	/* Decrement file open counter */
+			if (res == FR_OK)
+#endif
+			{
+				fp->obj.fs = 0;			/* Invalidate file object */
+			}
+#if _FS_REENTRANT
+			unlock_fs(fs, FR_OK);		/* Unlock volume */
+#endif
+		}
+	}
+	return res;
+}
+
+
+
+
+#if _FS_RPATH >= 1
+/*-----------------------------------------------------------------------*/
+/* Change Current Directory or Current Drive, Get Current Directory      */
+/*-----------------------------------------------------------------------*/
+
+#if _VOLUMES >= 2
+FRESULT f_chdrive (
+	const TCHAR* path		/* Drive number */
+)
+{
+	int vol;
+
+
+	/* Get logical drive number */
+	vol = get_ldnumber(&path);
+	if (vol < 0) return FR_INVALID_DRIVE;
+
+	CurrVol = (BYTE)vol;	/* Set it as current volume */
+
+	return FR_OK;
+}
+#endif
+
+
+FRESULT f_chdir (
+	const TCHAR* path	/* Pointer to the directory path */
+)
+{
+	FRESULT res;
+	DIR dj;
+	FATFS *fs;
+	DEF_NAMBUF
+
+	/* Get logical drive */
+	res = find_volume(&path, &fs, 0);
+	if (res == FR_OK) {
+		dj.obj.fs = fs;
+		INIT_NAMBUF(fs);
+		res = follow_path(&dj, path);		/* Follow the path */
+		if (res == FR_OK) {					/* Follow completed */
+			if (dj.fn[NSFLAG] & NS_NONAME) {
+				fs->cdir = dj.obj.sclust;	/* It is the start directory itself */
+#if _FS_EXFAT
+				if (fs->fs_type == FS_EXFAT) {
+					fs->cdc_scl = dj.obj.c_scl;
+					fs->cdc_size = dj.obj.c_size;
+					fs->cdc_ofs = dj.obj.c_ofs;
+				}
+#endif
+			} else {
+				if (dj.obj.attr & AM_DIR) {	/* It is a sub-directory */
+#if _FS_EXFAT
+					if (fs->fs_type == FS_EXFAT) {
+						fs->cdir = ld_dword(fs->dirbuf + XDIR_FstClus);		/* Sub-directory cluster */
+						fs->cdc_scl = dj.obj.sclust;						/* Save containing directory information */
+						fs->cdc_size = ((DWORD)dj.obj.objsize & 0xFFFFFF00) | dj.obj.stat;
+						fs->cdc_ofs = dj.blk_ofs;
+					} else
+#endif
+					{
+						fs->cdir = ld_clust(fs, dj.dir);					/* Sub-directory cluster */
+					}
+				} else {
+					res = FR_NO_PATH;		/* Reached but a file */
+				}
+			}
+		}
+		FREE_NAMBUF();
+		if (res == FR_NO_FILE) res = FR_NO_PATH;
+	}
+
+	LEAVE_FF(fs, res);
+}
+
+
+#if _FS_RPATH >= 2
+FRESULT f_getcwd (
+	TCHAR* buff,	/* Pointer to the directory path */
+	UINT len		/* Size of path */
+)
+{
+	FRESULT res;
+	DIR dj;
+	FATFS *fs;
+	UINT i, n;
+	DWORD ccl;
+	TCHAR *tp;
+	FILINFO fno;
+	DEF_NAMBUF
+
+
+	*buff = 0;
+	/* Get logical drive */
+	res = find_volume((const TCHAR**)&buff, &fs, 0);	/* Get current volume */
+	if (res == FR_OK) {
+		dj.obj.fs = fs;
+		INIT_NAMBUF(fs);
+		i = len;			/* Bottom of buffer (directory stack base) */
+		if (!_FS_EXFAT || fs->fs_type != FS_EXFAT) {	/* (Cannot do getcwd on exFAT and returns root path) */
+			dj.obj.sclust = fs->cdir;				/* Start to follow upper directory from current directory */
+			while ((ccl = dj.obj.sclust) != 0) {	/* Repeat while current directory is a sub-directory */
+				res = dir_sdi(&dj, 1 * SZDIRE);	/* Get parent directory */
+				if (res != FR_OK) break;
+				res = move_window(fs, dj.sect);
+				if (res != FR_OK) break;
+				dj.obj.sclust = ld_clust(fs, dj.dir);	/* Goto parent directory */
+				res = dir_sdi(&dj, 0);
+				if (res != FR_OK) break;
+				do {							/* Find the entry links to the child directory */
+					res = dir_read(&dj, 0);
+					if (res != FR_OK) break;
+					if (ccl == ld_clust(fs, dj.dir)) break;	/* Found the entry */
+					res = dir_next(&dj, 0);
+				} while (res == FR_OK);
+				if (res == FR_NO_FILE) res = FR_INT_ERR;/* It cannot be 'not found'. */
+				if (res != FR_OK) break;
+				get_fileinfo(&dj, &fno);		/* Get the directory name and push it to the buffer */
+				for (n = 0; fno.fname[n]; n++) ;
+				if (i < n + 3) {
+					res = FR_NOT_ENOUGH_CORE; break;
+				}
+				while (n) buff[--i] = fno.fname[--n];
+				buff[--i] = '/';
+			}
+		}
+		tp = buff;
+		if (res == FR_OK) {
+#if _VOLUMES >= 2
+			*tp++ = '0' + CurrVol;			/* Put drive number */
+			*tp++ = ':';
+#endif
+			if (i == len) {					/* Root-directory */
+				*tp++ = '/';
+			} else {						/* Sub-directroy */
+				do		/* Add stacked path str */
+					*tp++ = buff[i++];
+				while (i < len);
+			}
+		}
+		*tp = 0;
+		FREE_NAMBUF();
+	}
+
+	LEAVE_FF(fs, res);
+}
+
+#endif /* _FS_RPATH >= 2 */
+#endif /* _FS_RPATH >= 1 */
+
+
+
+#if _FS_MINIMIZE <= 2
+/*-----------------------------------------------------------------------*/
+/* Seek File R/W Pointer                                                 */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_lseek (
+	FIL* fp,		/* Pointer to the file object */
+	FSIZE_t ofs		/* File pointer from top of file */
+)
+{
+	FRESULT res;
+	FATFS *fs;
+	DWORD clst, bcs, nsect;
+	FSIZE_t ifptr;
+#if _USE_FASTSEEK
+	DWORD cl, pcl, ncl, tcl, dsc, tlen, ulen, *tbl;
+#endif
+
+	res = validate(&fp->obj, &fs);		/* Check validity of the file object */
+	if (res == FR_OK) res = (FRESULT)fp->err;
+#if _FS_EXFAT && !_FS_READONLY
+	if (res == FR_OK && fs->fs_type == FS_EXFAT) {
+		res = fill_last_frag(&fp->obj, fp->clust, 0xFFFFFFFF);	/* Fill last fragment on the FAT if needed */
+	}
+#endif
+	if (res != FR_OK) LEAVE_FF(fs, res);
+
+#if _USE_FASTSEEK
+	if (fp->cltbl) {	/* Fast seek */
+		if (ofs == CREATE_LINKMAP) {	/* Create CLMT */
+			tbl = fp->cltbl;
+			tlen = *tbl++; ulen = 2;	/* Given table size and required table size */
+			cl = fp->obj.sclust;		/* Origin of the chain */
+			if (cl) {
+				do {
+					/* Get a fragment */
+					tcl = cl; ncl = 0; ulen += 2;	/* Top, length and used items */
+					do {
+						pcl = cl; ncl++;
+						cl = get_fat(&fp->obj, cl);
+						if (cl <= 1) ABORT(fs, FR_INT_ERR);
+						if (cl == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR);
+					} while (cl == pcl + 1);
+					if (ulen <= tlen) {		/* Store the length and top of the fragment */
+						*tbl++ = ncl; *tbl++ = tcl;
+					}
+				} while (cl < fs->n_fatent);	/* Repeat until end of chain */
+			}
+			*fp->cltbl = ulen;	/* Number of items used */
+			if (ulen <= tlen) {
+				*tbl = 0;		/* Terminate table */
+			} else {
+				res = FR_NOT_ENOUGH_CORE;	/* Given table size is smaller than required */
+			}
+		} else {						/* Fast seek */
+			if (ofs > fp->obj.objsize) ofs = fp->obj.objsize;	/* Clip offset at the file size */
+			fp->fptr = ofs;				/* Set file pointer */
+			if (ofs) {
+				fp->clust = clmt_clust(fp, ofs - 1);
+				dsc = clust2sect(fs, fp->clust);
+				if (!dsc) ABORT(fs, FR_INT_ERR);
+				dsc += (DWORD)((ofs - 1) / SS(fs)) & (fs->csize - 1);
+				if (fp->fptr % SS(fs) && dsc != fp->sect) {	/* Refill sector cache if needed */
+#if !_FS_TINY
+#if !_FS_READONLY
+					if (fp->flag & FA_DIRTY) {		/* Write-back dirty sector cache */
+						if (disk_write(fs->drv, fp->buf, fp->sect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR);
+						fp->flag &= (BYTE)~FA_DIRTY;
+					}
+#endif
+					if (disk_read(fs->drv, fp->buf, dsc, 1) != RES_OK) ABORT(fs, FR_DISK_ERR);	/* Load current sector */
+#endif
+					fp->sect = dsc;
+				}
+			}
+		}
+	} else
+#endif
+
+	/* Normal Seek */
+	{
+#if _FS_EXFAT
+		if (fs->fs_type != FS_EXFAT && ofs >= 0x100000000) ofs = 0xFFFFFFFF;	/* Clip at 4GiB-1 if at FATxx */
+#endif
+		if (ofs > fp->obj.objsize && (_FS_READONLY || !(fp->flag & FA_WRITE))) {	/* In read-only mode, clip offset with the file size */
+			ofs = fp->obj.objsize;
+		}
+		ifptr = fp->fptr;
+		fp->fptr = nsect = 0;
+		if (ofs) {
+			bcs = (DWORD)fs->csize * SS(fs);	/* Cluster size (byte) */
+			if (ifptr > 0 &&
+				(ofs - 1) / bcs >= (ifptr - 1) / bcs) {	/* When seek to same or following cluster, */
+				fp->fptr = (ifptr - 1) & ~(FSIZE_t)(bcs - 1);	/* start from the current cluster */
+				ofs -= fp->fptr;
+				clst = fp->clust;
+			} else {									/* When seek to back cluster, */
+				clst = fp->obj.sclust;					/* start from the first cluster */
+#if !_FS_READONLY
+				if (clst == 0) {						/* If no cluster chain, create a new chain */
+					clst = create_chain(&fp->obj, 0);
+					if (clst == 1) ABORT(fs, FR_INT_ERR);
+					if (clst == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR);
+					fp->obj.sclust = clst;
+				}
+#endif
+				fp->clust = clst;
+			}
+			if (clst != 0) {
+				while (ofs > bcs) {						/* Cluster following loop */
+					ofs -= bcs; fp->fptr += bcs;
+#if !_FS_READONLY
+					if (fp->flag & FA_WRITE) {			/* Check if in write mode or not */
+						if (_FS_EXFAT && fp->fptr > fp->obj.objsize) {	/* No FAT chain object needs correct objsize to generate FAT value */
+							fp->obj.objsize = fp->fptr;
+							fp->flag |= FA_MODIFIED;
+						}
+						clst = create_chain(&fp->obj, clst);	/* Follow chain with forceed stretch */
+						if (clst == 0) {				/* Clip file size in case of disk full */
+							ofs = 0; break;
+						}
+					} else
+#endif
+					{
+						clst = get_fat(&fp->obj, clst);	/* Follow cluster chain if not in write mode */
+					}
+					if (clst == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR);
+					if (clst <= 1 || clst >= fs->n_fatent) ABORT(fs, FR_INT_ERR);
+					fp->clust = clst;
+				}
+				fp->fptr += ofs;
+				if (ofs % SS(fs)) {
+					nsect = clust2sect(fs, clst);	/* Current sector */
+					if (!nsect) ABORT(fs, FR_INT_ERR);
+					nsect += (DWORD)(ofs / SS(fs));
+				}
+			}
+		}
+		if (!_FS_READONLY && fp->fptr > fp->obj.objsize) {		/* Set file change flag if the file size is extended */
+			fp->obj.objsize = fp->fptr;
+			fp->flag |= FA_MODIFIED;
+		}
+		if (fp->fptr % SS(fs) && nsect != fp->sect) {	/* Fill sector cache if needed */
+#if !_FS_TINY
+#if !_FS_READONLY
+			if (fp->flag & FA_DIRTY) {			/* Write-back dirty sector cache */
+				if (disk_write(fs->drv, fp->buf, fp->sect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR);
+				fp->flag &= (BYTE)~FA_DIRTY;
+			}
+#endif
+			if (disk_read(fs->drv, fp->buf, nsect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR);	/* Fill sector cache */
+#endif
+			fp->sect = nsect;
+		}
+	}
+
+	LEAVE_FF(fs, res);
+}
+
+
+
+#if _FS_MINIMIZE <= 1
+/*-----------------------------------------------------------------------*/
+/* Create a Directory Object                                             */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_opendir (
+	DIR* dp,			/* Pointer to directory object to create */
+	const TCHAR* path	/* Pointer to the directory path */
+)
+{
+	FRESULT res;
+	FATFS *fs;
+	_FDID *obj;
+	DEF_NAMBUF
+
+
+	if (!dp) return FR_INVALID_OBJECT;
+
+	/* Get logical drive */
+	obj = &dp->obj;
+	res = find_volume(&path, &fs, 0);
+	if (res == FR_OK) {
+		obj->fs = fs;
+		INIT_NAMBUF(fs);
+		res = follow_path(dp, path);			/* Follow the path to the directory */
+		if (res == FR_OK) {						/* Follow completed */
+			if (!(dp->fn[NSFLAG] & NS_NONAME)) {	/* It is not the origin directory itself */
+				if (obj->attr & AM_DIR) {		/* This object is a sub-directory */
+#if _FS_EXFAT
+					if (fs->fs_type == FS_EXFAT) {
+						obj->c_scl = obj->sclust;							/* Get containing directory inforamation */
+						obj->c_size = ((DWORD)obj->objsize & 0xFFFFFF00) | obj->stat;
+						obj->c_ofs = dp->blk_ofs;
+						obj->sclust = ld_dword(fs->dirbuf + XDIR_FstClus);	/* Get object allocation info */
+						obj->objsize = ld_qword(fs->dirbuf + XDIR_FileSize);
+						obj->stat = fs->dirbuf[XDIR_GenFlags] & 2;
+					} else
+#endif
+					{
+						obj->sclust = ld_clust(fs, dp->dir);	/* Get object allocation info */
+					}
+				} else {						/* This object is a file */
+					res = FR_NO_PATH;
+				}
+			}
+			if (res == FR_OK) {
+				obj->id = fs->id;
+				res = dir_sdi(dp, 0);			/* Rewind directory */
+#if _FS_LOCK != 0
+				if (res == FR_OK) {
+					if (obj->sclust) {
+						obj->lockid = inc_lock(dp, 0);	/* Lock the sub directory */
+						if (!obj->lockid) res = FR_TOO_MANY_OPEN_FILES;
+					} else {
+						obj->lockid = 0;	/* Root directory need not to be locked */
+					}
+				}
+#endif
+			}
+		}
+		FREE_NAMBUF();
+		if (res == FR_NO_FILE) res = FR_NO_PATH;
+	}
+	if (res != FR_OK) obj->fs = 0;		/* Invalidate the directory object if function faild */
+
+	LEAVE_FF(fs, res);
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Close Directory                                                       */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_closedir (
+	DIR *dp		/* Pointer to the directory object to be closed */
+)
+{
+	FRESULT res;
+	FATFS *fs;
+
+
+	res = validate(&dp->obj, &fs);			/* Check validity of the file object */
+	if (res == FR_OK) {
+#if _FS_LOCK != 0
+		if (dp->obj.lockid) {				/* Decrement sub-directory open counter */
+			res = dec_lock(dp->obj.lockid);
+		}
+		if (res == FR_OK)
+#endif
+		{
+			dp->obj.fs = 0;			/* Invalidate directory object */
+		}
+#if _FS_REENTRANT
+		unlock_fs(fs, FR_OK);		/* Unlock volume */
+#endif
+	}
+	return res;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Read Directory Entries in Sequence                                    */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_readdir (
+	DIR* dp,			/* Pointer to the open directory object */
+	FILINFO* fno		/* Pointer to file information to return */
+)
+{
+	FRESULT res;
+	FATFS *fs;
+	DEF_NAMBUF
+
+
+	res = validate(&dp->obj, &fs);	/* Check validity of the directory object */
+	if (res == FR_OK) {
+		if (!fno) {
+			res = dir_sdi(dp, 0);			/* Rewind the directory object */
+		} else {
+			INIT_NAMBUF(fs);
+			res = dir_read(dp, 0);			/* Read an item */
+			if (res == FR_NO_FILE) res = FR_OK;	/* Ignore end of directory */
+			if (res == FR_OK) {				/* A valid entry is found */
+				get_fileinfo(dp, fno);		/* Get the object information */
+				res = dir_next(dp, 0);		/* Increment index for next */
+				if (res == FR_NO_FILE) res = FR_OK;	/* Ignore end of directory now */
+			}
+			FREE_NAMBUF();
+		}
+	}
+	LEAVE_FF(fs, res);
+}
+
+
+
+#if _USE_FIND
+/*-----------------------------------------------------------------------*/
+/* Find Next File                                                        */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_findnext (
+	DIR* dp,		/* Pointer to the open directory object */
+	FILINFO* fno	/* Pointer to the file information structure */
+)
+{
+	FRESULT res;
+
+
+	for (;;) {
+		res = f_readdir(dp, fno);		/* Get a directory item */
+		if (res != FR_OK || !fno || !fno->fname[0]) break;	/* Terminate if any error or end of directory */
+		if (pattern_matching(dp->pat, fno->fname, 0, 0)) break;		/* Test for the file name */
+#if _USE_LFN != 0 && _USE_FIND == 2
+		if (pattern_matching(dp->pat, fno->altname, 0, 0)) break;	/* Test for alternative name if exist */
+#endif
+	}
+	return res;
+}
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Find First File                                                       */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_findfirst (
+	DIR* dp,				/* Pointer to the blank directory object */
+	FILINFO* fno,			/* Pointer to the file information structure */
+	const TCHAR* path,		/* Pointer to the directory to open */
+	const TCHAR* pattern	/* Pointer to the matching pattern */
+)
+{
+	FRESULT res;
+
+
+	dp->pat = pattern;		/* Save pointer to pattern string */
+	res = f_opendir(dp, path);		/* Open the target directory */
+	if (res == FR_OK) {
+		res = f_findnext(dp, fno);	/* Find the first item */
+	}
+	return res;
+}
+
+#endif	/* _USE_FIND */
+
+
+
+#if _FS_MINIMIZE == 0
+/*-----------------------------------------------------------------------*/
+/* Get File Status                                                       */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_stat (
+	const TCHAR* path,	/* Pointer to the file path */
+	FILINFO* fno		/* Pointer to file information to return */
+)
+{
+	FRESULT res;
+	DIR dj;
+	DEF_NAMBUF
+
+
+	/* Get logical drive */
+	res = find_volume(&path, &dj.obj.fs, 0);
+	if (res == FR_OK) {
+		INIT_NAMBUF(dj.obj.fs);
+		res = follow_path(&dj, path);	/* Follow the file path */
+		if (res == FR_OK) {				/* Follow completed */
+			if (dj.fn[NSFLAG] & NS_NONAME) {	/* It is origin directory */
+				res = FR_INVALID_NAME;
+			} else {							/* Found an object */
+				if (fno) get_fileinfo(&dj, fno);
+			}
+		}
+		FREE_NAMBUF();
+	}
+
+	LEAVE_FF(dj.obj.fs, res);
+}
+
+
+
+#if !_FS_READONLY
+/*-----------------------------------------------------------------------*/
+/* Get Number of Free Clusters                                           */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_getfree (
+	const TCHAR* path,	/* Path name of the logical drive number */
+	DWORD* nclst,		/* Pointer to a variable to return number of free clusters */
+	FATFS** fatfs		/* Pointer to return pointer to corresponding file system object */
+)
+{
+	FRESULT res;
+	FATFS *fs;
+	DWORD nfree, clst, sect, stat;
+	UINT i;
+	BYTE *p;
+	_FDID obj;
+
+
+	/* Get logical drive */
+	res = find_volume(&path, &fs, 0);
+	if (res == FR_OK) {
+		*fatfs = fs;				/* Return ptr to the fs object */
+		/* If free_clst is valid, return it without full cluster scan */
+		if (fs->free_clst <= fs->n_fatent - 2) {
+			*nclst = fs->free_clst;
+		} else {
+			/* Get number of free clusters */
+			nfree = 0;
+			if (fs->fs_type == FS_FAT12) {	/* FAT12: Sector unalighed FAT entries */
+				clst = 2; obj.fs = fs;
+				do {
+					stat = get_fat(&obj, clst);
+					if (stat == 0xFFFFFFFF) { res = FR_DISK_ERR; break; }
+					if (stat == 1) { res = FR_INT_ERR; break; }
+					if (stat == 0) nfree++;
+				} while (++clst < fs->n_fatent);
+			} else {
+#if _FS_EXFAT
+				if (fs->fs_type == FS_EXFAT) {	/* exFAT: Scan bitmap table */
+					BYTE bm;
+					UINT b;
+
+					clst = fs->n_fatent - 2;
+					sect = fs->database;
+					i = 0;
+					do {
+						if (i == 0 && (res = move_window(fs, sect++)) != FR_OK) break;
+						for (b = 8, bm = fs->win[i]; b && clst; b--, clst--) {
+							if (!(bm & 1)) nfree++;
+							bm >>= 1;
+						}
+						i = (i + 1) % SS(fs);
+					} while (clst);
+				} else
+#endif
+				{	/* FAT16/32: Sector alighed FAT entries */
+					clst = fs->n_fatent; sect = fs->fatbase;
+					i = 0; p = 0;
+					do {
+						if (i == 0) {
+							res = move_window(fs, sect++);
+							if (res != FR_OK) break;
+							p = fs->win;
+							i = SS(fs);
+						}
+						if (fs->fs_type == FS_FAT16) {
+							if (ld_word(p) == 0) nfree++;
+							p += 2; i -= 2;
+						} else {
+							if ((ld_dword(p) & 0x0FFFFFFF) == 0) nfree++;
+							p += 4; i -= 4;
+						}
+					} while (--clst);
+				}
+			}
+			*nclst = nfree;			/* Return the free clusters */
+			fs->free_clst = nfree;	/* Now free_clst is valid */
+			fs->fsi_flag |= 1;		/* FSInfo is to be updated */
+		}
+	}
+
+	LEAVE_FF(fs, res);
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Truncate File                                                         */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_truncate (
+	FIL* fp		/* Pointer to the file object */
+)
+{
+	FRESULT res;
+	FATFS *fs;
+	DWORD ncl;
+
+
+	res = validate(&fp->obj, &fs);	/* Check validity of the file object */
+	if (res != FR_OK || (res = (FRESULT)fp->err) != FR_OK) LEAVE_FF(fs, res);
+	if (!(fp->flag & FA_WRITE)) LEAVE_FF(fs, FR_DENIED);	/* Check access mode */
+
+	if (fp->fptr < fp->obj.objsize) {	/* Process when fptr is not on the eof */
+		if (fp->fptr == 0) {	/* When set file size to zero, remove entire cluster chain */
+			res = remove_chain(&fp->obj, fp->obj.sclust, 0);
+			fp->obj.sclust = 0;
+		} else {				/* When truncate a part of the file, remove remaining clusters */
+			ncl = get_fat(&fp->obj, fp->clust);
+			res = FR_OK;
+			if (ncl == 0xFFFFFFFF) res = FR_DISK_ERR;
+			if (ncl == 1) res = FR_INT_ERR;
+			if (res == FR_OK && ncl < fs->n_fatent) {
+				res = remove_chain(&fp->obj, ncl, fp->clust);
+			}
+		}
+		fp->obj.objsize = fp->fptr;	/* Set file size to current R/W point */
+		fp->flag |= FA_MODIFIED;
+#if !_FS_TINY
+		if (res == FR_OK && (fp->flag & FA_DIRTY)) {
+			if (disk_write(fs->drv, fp->buf, fp->sect, 1) != RES_OK) {
+				res = FR_DISK_ERR;
+			} else {
+				fp->flag &= (BYTE)~FA_DIRTY;
+			}
+		}
+#endif
+		if (res != FR_OK) ABORT(fs, res);
+	}
+
+	LEAVE_FF(fs, res);
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Delete a File/Directory                                               */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_unlink (
+	const TCHAR* path		/* Pointer to the file or directory path */
+)
+{
+	FRESULT res;
+	DIR dj, sdj;
+	DWORD dclst = 0;
+	FATFS *fs;
+#if _FS_EXFAT
+	_FDID obj;
+#endif
+	DEF_NAMBUF
+
+
+	/* Get logical drive */
+	res = find_volume(&path, &fs, FA_WRITE);
+	dj.obj.fs = fs;
+	if (res == FR_OK) {
+		INIT_NAMBUF(fs);
+		res = follow_path(&dj, path);		/* Follow the file path */
+		if (_FS_RPATH && res == FR_OK && (dj.fn[NSFLAG] & NS_DOT)) {
+			res = FR_INVALID_NAME;			/* Cannot remove dot entry */
+		}
+#if _FS_LOCK != 0
+		if (res == FR_OK) res = chk_lock(&dj, 2);	/* Check if it is an open object */
+#endif
+		if (res == FR_OK) {					/* The object is accessible */
+			if (dj.fn[NSFLAG] & NS_NONAME) {
+				res = FR_INVALID_NAME;		/* Cannot remove the origin directory */
+			} else {
+				if (dj.obj.attr & AM_RDO) {
+					res = FR_DENIED;		/* Cannot remove R/O object */
+				}
+			}
+			if (res == FR_OK) {
+#if _FS_EXFAT
+				obj.fs = fs;
+				if (fs->fs_type == FS_EXFAT) {
+					obj.sclust = dclst = ld_dword(fs->dirbuf + XDIR_FstClus);
+					obj.objsize = ld_qword(fs->dirbuf + XDIR_FileSize);
+					obj.stat = fs->dirbuf[XDIR_GenFlags] & 2;
+				} else
+#endif
+				{
+					dclst = ld_clust(fs, dj.dir);
+				}
+				if (dj.obj.attr & AM_DIR) {			/* Is it a sub-directory? */
+#if _FS_RPATH != 0
+					if (dclst == fs->cdir) {		 		/* Is it the current directory? */
+						res = FR_DENIED;
+					} else
+#endif
+					{
+						sdj.obj.fs = fs;						/* Open the sub-directory */
+						sdj.obj.sclust = dclst;
+#if _FS_EXFAT
+						if (fs->fs_type == FS_EXFAT) {
+							sdj.obj.objsize = obj.objsize;
+							sdj.obj.stat = obj.stat;
+						}
+#endif
+						res = dir_sdi(&sdj, 0);
+						if (res == FR_OK) {
+							res = dir_read(&sdj, 0);			/* Read an item */
+							if (res == FR_OK) res = FR_DENIED;	/* Not empty? */
+							if (res == FR_NO_FILE) res = FR_OK;	/* Empty? */
+						}
+					}
+				}
+			}
+			if (res == FR_OK) {
+				res = dir_remove(&dj);			/* Remove the directory entry */
+				if (res == FR_OK && dclst) {	/* Remove the cluster chain if exist */
+#if _FS_EXFAT
+					res = remove_chain(&obj, dclst, 0);
+#else
+					res = remove_chain(&dj.obj, dclst, 0);
+#endif
+				}
+				if (res == FR_OK) res = sync_fs(fs);
+			}
+		}
+		FREE_NAMBUF();
+	}
+
+	LEAVE_FF(fs, res);
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Create a Directory                                                    */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_mkdir (
+	const TCHAR* path		/* Pointer to the directory path */
+)
+{
+	FRESULT res;
+	DIR dj;
+	FATFS *fs;
+	BYTE *dir;
+	UINT n;
+	DWORD dsc, dcl, pcl, tm;
+	DEF_NAMBUF
+
+
+	/* Get logical drive */
+	res = find_volume(&path, &fs, FA_WRITE);
+	dj.obj.fs = fs;
+	if (res == FR_OK) {
+		INIT_NAMBUF(fs);
+		res = follow_path(&dj, path);			/* Follow the file path */
+		if (res == FR_OK) res = FR_EXIST;		/* Any object with same name is already existing */
+		if (_FS_RPATH && res == FR_NO_FILE && (dj.fn[NSFLAG] & NS_DOT)) {
+			res = FR_INVALID_NAME;
+		}
+		if (res == FR_NO_FILE) {				/* Can create a new directory */
+			dcl = create_chain(&dj.obj, 0);		/* Allocate a cluster for the new directory table */
+			dj.obj.objsize = (DWORD)fs->csize * SS(fs);
+			res = FR_OK;
+			if (dcl == 0) res = FR_DENIED;		/* No space to allocate a new cluster */
+			if (dcl == 1) res = FR_INT_ERR;
+			if (dcl == 0xFFFFFFFF) res = FR_DISK_ERR;
+			if (res == FR_OK) res = sync_window(fs);	/* Flush FAT */
+			tm = GET_FATTIME();
+			if (res == FR_OK) {					/* Initialize the new directory table */
+				dsc = clust2sect(fs, dcl);
+				dir = fs->win;
+				mem_set(dir, 0, SS(fs));
+				if (!_FS_EXFAT || fs->fs_type != FS_EXFAT) {
+					mem_set(dir + DIR_Name, ' ', 11);	/* Create "." entry */
+					dir[DIR_Name] = '.';
+					dir[DIR_Attr] = AM_DIR;
+					st_dword(dir + DIR_ModTime, tm);
+					st_clust(fs, dir, dcl);
+					mem_cpy(dir + SZDIRE, dir, SZDIRE); 	/* Create ".." entry */
+					dir[SZDIRE + 1] = '.'; pcl = dj.obj.sclust;
+					if (fs->fs_type == FS_FAT32 && pcl == fs->dirbase) pcl = 0;
+					st_clust(fs, dir + SZDIRE, pcl);
+				}
+				for (n = fs->csize; n; n--) {	/* Write dot entries and clear following sectors */
+					fs->winsect = dsc++;
+					fs->wflag = 1;
+					res = sync_window(fs);
+					if (res != FR_OK) break;
+					mem_set(dir, 0, SS(fs));
+				}
+			}
+			if (res == FR_OK) {
+				res = dir_register(&dj);	/* Register the object to the directoy */
+			}
+			if (res == FR_OK) {
+#if _FS_EXFAT
+				if (fs->fs_type == FS_EXFAT) {	/* Initialize directory entry block */
+					st_dword(fs->dirbuf + XDIR_ModTime, tm);	/* Created time */
+					st_dword(fs->dirbuf + XDIR_FstClus, dcl);	/* Table start cluster */
+					st_dword(fs->dirbuf + XDIR_FileSize, (DWORD)dj.obj.objsize);	/* File size needs to be valid */
+					st_dword(fs->dirbuf + XDIR_ValidFileSize, (DWORD)dj.obj.objsize);
+					fs->dirbuf[XDIR_GenFlags] = 3;				/* Initialize the object flag (contiguous) */
+					fs->dirbuf[XDIR_Attr] = AM_DIR;				/* Attribute */
+					res = store_xdir(&dj);
+				} else
+#endif
+				{
+					dir = dj.dir;
+					st_dword(dir + DIR_ModTime, tm);	/* Created time */
+					st_clust(fs, dir, dcl);				/* Table start cluster */
+					dir[DIR_Attr] = AM_DIR;				/* Attribute */
+					fs->wflag = 1;
+				}
+				if (res == FR_OK) {
+					res = sync_fs(fs);
+				}
+			} else {
+				remove_chain(&dj.obj, dcl, 0);		/* Could not register, remove cluster chain */
+			}
+		}
+		FREE_NAMBUF();
+	}
+
+	LEAVE_FF(fs, res);
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Rename a File/Directory                                               */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_rename (
+	const TCHAR* path_old,	/* Pointer to the object name to be renamed */
+	const TCHAR* path_new	/* Pointer to the new name */
+)
+{
+	FRESULT res;
+	DIR djo, djn;
+	FATFS *fs;
+	BYTE buf[_FS_EXFAT ? SZDIRE * 2 : 24], *dir;
+	DWORD dw;
+	DEF_NAMBUF
+
+
+	get_ldnumber(&path_new);						/* Snip drive number of new name off */
+	res = find_volume(&path_old, &fs, FA_WRITE);	/* Get logical drive of the old object */
+	if (res == FR_OK) {
+		djo.obj.fs = fs;
+		INIT_NAMBUF(fs);
+		res = follow_path(&djo, path_old);		/* Check old object */
+		if (res == FR_OK && (djo.fn[NSFLAG] & (NS_DOT | NS_NONAME))) res = FR_INVALID_NAME;	/* Check validity of name */
+#if _FS_LOCK != 0
+		if (res == FR_OK) {
+			res = chk_lock(&djo, 2);
+		}
+#endif
+		if (res == FR_OK) {						/* Object to be renamed is found */
+#if _FS_EXFAT
+			if (fs->fs_type == FS_EXFAT) {	/* At exFAT */
+				BYTE nf, nn;
+				WORD nh;
+
+				mem_cpy(buf, fs->dirbuf, SZDIRE * 2);	/* Save 85+C0 entry of old object */
+				mem_cpy(&djn, &djo, sizeof djo);
+				res = follow_path(&djn, path_new);		/* Make sure if new object name is not in use */
+				if (res == FR_OK) {						/* Is new name already in use by any other object? */
+					res = (djn.obj.sclust == djo.obj.sclust && djn.dptr == djo.dptr) ? FR_NO_FILE : FR_EXIST;
+				}
+				if (res == FR_NO_FILE) { 				/* It is a valid path and no name collision */
+					res = dir_register(&djn);			/* Register the new entry */
+					if (res == FR_OK) {
+						nf = fs->dirbuf[XDIR_NumSec]; nn = fs->dirbuf[XDIR_NumName];
+						nh = ld_word(fs->dirbuf + XDIR_NameHash);
+						mem_cpy(fs->dirbuf, buf, SZDIRE * 2);
+						fs->dirbuf[XDIR_NumSec] = nf; fs->dirbuf[XDIR_NumName] = nn;
+						st_word(fs->dirbuf + XDIR_NameHash, nh);
+/* Start of critical section where an interruption can cause a cross-link */
+						res = store_xdir(&djn);
+					}
+				}
+			} else
+#endif
+			{	/* At FAT12/FAT16/FAT32 */
+				mem_cpy(buf, djo.dir + DIR_Attr, 21);	/* Save information about the object except name */
+				mem_cpy(&djn, &djo, sizeof (DIR));		/* Duplicate the directory object */
+				res = follow_path(&djn, path_new);		/* Make sure if new object name is not in use */
+				if (res == FR_OK) {						/* Is new name already in use by any other object? */
+					res = (djn.obj.sclust == djo.obj.sclust && djn.dptr == djo.dptr) ? FR_NO_FILE : FR_EXIST;
+				}
+				if (res == FR_NO_FILE) { 				/* It is a valid path and no name collision */
+					res = dir_register(&djn);			/* Register the new entry */
+					if (res == FR_OK) {
+						dir = djn.dir;					/* Copy information about object except name */
+						mem_cpy(dir + 13, buf + 2, 19);
+						dir[DIR_Attr] = buf[0] | AM_ARC;
+						fs->wflag = 1;
+						if ((dir[DIR_Attr] & AM_DIR) && djo.obj.sclust != djn.obj.sclust) {	/* Update .. entry in the sub-directory if needed */
+							dw = clust2sect(fs, ld_clust(fs, dir));
+							if (!dw) {
+								res = FR_INT_ERR;
+							} else {
+/* Start of critical section where an interruption can cause a cross-link */
+								res = move_window(fs, dw);
+								dir = fs->win + SZDIRE * 1;	/* Ptr to .. entry */
+								if (res == FR_OK && dir[1] == '.') {
+									st_clust(fs, dir, djn.obj.sclust);
+									fs->wflag = 1;
+								}
+							}
+						}
+					}
+				}
+			}
+			if (res == FR_OK) {
+				res = dir_remove(&djo);		/* Remove old entry */
+				if (res == FR_OK) {
+					res = sync_fs(fs);
+				}
+			}
+/* End of the critical section */
+		}
+		FREE_NAMBUF();
+	}
+
+	LEAVE_FF(fs, res);
+}
+
+#endif /* !_FS_READONLY */
+#endif /* _FS_MINIMIZE == 0 */
+#endif /* _FS_MINIMIZE <= 1 */
+#endif /* _FS_MINIMIZE <= 2 */
+
+
+
+#if _USE_CHMOD && !_FS_READONLY
+/*-----------------------------------------------------------------------*/
+/* Change Attribute                                                      */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_chmod (
+	const TCHAR* path,	/* Pointer to the file path */
+	BYTE attr,			/* Attribute bits */
+	BYTE mask			/* Attribute mask to change */
+)
+{
+	FRESULT res;
+	DIR dj;
+	FATFS *fs;
+	DEF_NAMBUF
+
+
+	res = find_volume(&path, &fs, FA_WRITE);	/* Get logical drive */
+	dj.obj.fs = fs;
+	if (res == FR_OK) {
+		INIT_NAMBUF(fs);
+		res = follow_path(&dj, path);	/* Follow the file path */
+		if (res == FR_OK && (dj.fn[NSFLAG] & (NS_DOT | NS_NONAME))) res = FR_INVALID_NAME;	/* Check object validity */
+		if (res == FR_OK) {
+			mask &= AM_RDO|AM_HID|AM_SYS|AM_ARC;	/* Valid attribute mask */
+#if _FS_EXFAT
+			if (fs->fs_type == FS_EXFAT) {
+				fs->dirbuf[XDIR_Attr] = (attr & mask) | (fs->dirbuf[XDIR_Attr] & (BYTE)~mask);	/* Apply attribute change */
+				res = store_xdir(&dj);
+			} else
+#endif
+			{
+				dj.dir[DIR_Attr] = (attr & mask) | (dj.dir[DIR_Attr] & (BYTE)~mask);	/* Apply attribute change */
+				fs->wflag = 1;
+			}
+			if (res == FR_OK) {
+				res = sync_fs(fs);
+			}
+		}
+		FREE_NAMBUF();
+	}
+
+	LEAVE_FF(fs, res);
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Change Timestamp                                                      */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_utime (
+	const TCHAR* path,	/* Pointer to the file/directory name */
+	const FILINFO* fno	/* Pointer to the time stamp to be set */
+)
+{
+	FRESULT res;
+	DIR dj;
+	FATFS *fs;
+	DEF_NAMBUF
+
+
+	res = find_volume(&path, &fs, FA_WRITE);	/* Get logical drive */
+	dj.obj.fs = fs;
+	if (res == FR_OK) {
+		INIT_NAMBUF(fs);
+		res = follow_path(&dj, path);	/* Follow the file path */
+		if (res == FR_OK && (dj.fn[NSFLAG] & (NS_DOT | NS_NONAME))) res = FR_INVALID_NAME;	/* Check object validity */
+		if (res == FR_OK) {
+#if _FS_EXFAT
+			if (fs->fs_type == FS_EXFAT) {
+				st_dword(fs->dirbuf + XDIR_ModTime, (DWORD)fno->fdate << 16 | fno->ftime);
+				res = store_xdir(&dj);
+			} else
+#endif
+			{
+				st_dword(dj.dir + DIR_ModTime, (DWORD)fno->fdate << 16 | fno->ftime);
+				fs->wflag = 1;
+			}
+			if (res == FR_OK) {
+				res = sync_fs(fs);
+			}
+		}
+		FREE_NAMBUF();
+	}
+
+	LEAVE_FF(fs, res);
+}
+
+#endif	/* _USE_CHMOD && !_FS_READONLY */
+
+
+
+#if _USE_LABEL
+/*-----------------------------------------------------------------------*/
+/* Get Volume Label                                                      */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_getlabel (
+	const TCHAR* path,	/* Path name of the logical drive number */
+	TCHAR* label,		/* Pointer to a buffer to return the volume label */
+	DWORD* vsn			/* Pointer to a variable to return the volume serial number */
+)
+{
+	FRESULT res;
+	DIR dj;
+	FATFS *fs;
+	UINT si, di;
+#if _LFN_UNICODE || _FS_EXFAT
+	WCHAR w;
+#endif
+
+	/* Get logical drive */
+	res = find_volume(&path, &fs, 0);
+
+	/* Get volume label */
+	if (res == FR_OK && label) {
+		dj.obj.fs = fs; dj.obj.sclust = 0;	/* Open root directory */
+		res = dir_sdi(&dj, 0);
+		if (res == FR_OK) {
+		 	res = dir_read(&dj, 1);			/* Find a volume label entry */
+		 	if (res == FR_OK) {
+#if _FS_EXFAT
+				if (fs->fs_type == FS_EXFAT) {
+					for (si = di = 0; si < dj.dir[XDIR_NumLabel]; si++) {	/* Extract volume label from 83 entry */
+						w = ld_word(dj.dir + XDIR_Label + si * 2);
+#if _LFN_UNICODE
+						label[di++] = w;
+#else
+						w = ff_convert(w, 0);	/* Unicode -> OEM */
+						if (w == 0) w = '?';	/* Replace wrong character */
+						if (_DF1S && w >= 0x100) label[di++] = (char)(w >> 8);
+						label[di++] = (char)w;
+#endif
+					}
+					label[di] = 0;
+				} else
+#endif
+				{
+					si = di = 0;		/* Extract volume label from AM_VOL entry with code comversion */
+					do {
+#if _LFN_UNICODE
+						w = (si < 11) ? dj.dir[si++] : ' ';
+						if (IsDBCS1(w) && si < 11 && IsDBCS2(dj.dir[si])) {
+							w = w << 8 | dj.dir[si++];
+						}
+						label[di++] = ff_convert(w, 1);	/* OEM -> Unicode */
+#else
+						label[di++] = dj.dir[si++];
+#endif
+					} while (di < 11);
+					do {				/* Truncate trailing spaces */
+						label[di] = 0;
+						if (di == 0) break;
+					} while (label[--di] == ' ');
+				}
+			}
+		}
+		if (res == FR_NO_FILE) {	/* No label entry and return nul string */
+			label[0] = 0;
+			res = FR_OK;
+		}
+	}
+
+	/* Get volume serial number */
+	if (res == FR_OK && vsn) {
+		res = move_window(fs, fs->volbase);
+		if (res == FR_OK) {
+			switch (fs->fs_type) {
+			case FS_EXFAT:
+				di = BPB_VolIDEx; break;
+
+			case FS_FAT32:
+				di = BS_VolID32; break;
+
+			default:
+				di = BS_VolID;
+			}
+			*vsn = ld_dword(fs->win + di);
+		}
+	}
+
+	LEAVE_FF(fs, res);
+}
+
+
+
+#if !_FS_READONLY
+/*-----------------------------------------------------------------------*/
+/* Set Volume Label                                                      */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_setlabel (
+	const TCHAR* label	/* Pointer to the volume label to set */
+)
+{
+	FRESULT res;
+	DIR dj;
+	FATFS *fs;
+	BYTE dirvn[22];
+	UINT i, j, slen;
+	WCHAR w;
+	static const char badchr[] = "\"*+,.:;<=>\?[]|\x7F";
+
+
+	/* Get logical drive */
+	res = find_volume(&label, &fs, FA_WRITE);
+	if (res != FR_OK) LEAVE_FF(fs, res);
+	dj.obj.fs = fs;
+
+	/* Get length of given volume label */
+	for (slen = 0; (UINT)label[slen] >= ' '; slen++) ;	/* Get name length */
+
+#if _FS_EXFAT
+	if (fs->fs_type == FS_EXFAT) {	/* On the exFAT volume */
+		for (i = j = 0; i < slen; ) {	/* Create volume label in directory form */
+			w = label[i++];
+#if !_LFN_UNICODE
+			if (IsDBCS1(w)) {
+				w = (i < slen && IsDBCS2(label[i])) ? w << 8 | (BYTE)label[i++] : 0;
+			}
+			w = ff_convert(w, 1);
+#endif
+			if (w == 0 || chk_chr(badchr, w) || j == 22) {	/* Check validity check validity of the volume label */
+				LEAVE_FF(fs, FR_INVALID_NAME);
+			}
+			st_word(dirvn + j, w); j += 2;
+		}
+		slen = j;
+	} else
+#endif
+	{	/* On the FAT12/16/32 volume */
+		for ( ; slen && label[slen - 1] == ' '; slen--) ;	/* Remove trailing spaces */
+		if (slen) {		/* Is there a volume label to be set? */
+			dirvn[0] = 0; i = j = 0;	/* Create volume label in directory form */
+			do {
+#if _LFN_UNICODE
+				w = ff_convert(ff_wtoupper(label[i++]), 0);
+#else
+				w = (BYTE)label[i++];
+				if (IsDBCS1(w)) {
+					w = (j < 10 && i < slen && IsDBCS2(label[i])) ? w << 8 | (BYTE)label[i++] : 0;
+				}
+#if _USE_LFN != 0
+				w = ff_convert(ff_wtoupper(ff_convert(w, 1)), 0);
+#else
+				if (IsLower(w)) w -= 0x20;			/* To upper ASCII characters */
+#ifdef _EXCVT
+				if (w >= 0x80) w = ExCvt[w - 0x80];	/* To upper extended characters (SBCS cfg) */
+#else
+				if (!_DF1S && w >= 0x80) w = 0;		/* Reject extended characters (ASCII cfg) */
+#endif
+#endif
+#endif
+				if (w == 0 || chk_chr(badchr, w) || j >= (UINT)((w >= 0x100) ? 10 : 11)) {	/* Reject invalid characters for volume label */
+					LEAVE_FF(fs, FR_INVALID_NAME);
+				}
+				if (w >= 0x100) dirvn[j++] = (BYTE)(w >> 8);
+				dirvn[j++] = (BYTE)w;
+			} while (i < slen);
+			while (j < 11) dirvn[j++] = ' ';	/* Fill remaining name field */
+			if (dirvn[0] == DDEM) LEAVE_FF(fs, FR_INVALID_NAME);	/* Reject illegal name (heading DDEM) */
+		}
+	}
+
+	/* Set volume label */
+	dj.obj.sclust = 0;		/* Open root directory */
+	res = dir_sdi(&dj, 0);
+	if (res == FR_OK) {
+		res = dir_read(&dj, 1);	/* Get volume label entry */
+		if (res == FR_OK) {
+			if (_FS_EXFAT && fs->fs_type == FS_EXFAT) {
+				dj.dir[XDIR_NumLabel] = (BYTE)(slen / 2);	/* Change the volume label */
+				mem_cpy(dj.dir + XDIR_Label, dirvn, slen);
+			} else {
+				if (slen) {
+					mem_cpy(dj.dir, dirvn, 11);	/* Change the volume label */
+				} else {
+					dj.dir[DIR_Name] = DDEM;	/* Remove the volume label */
+				}
+			}
+			fs->wflag = 1;
+			res = sync_fs(fs);
+		} else {			/* No volume label entry is found or error */
+			if (res == FR_NO_FILE) {
+				res = FR_OK;
+				if (slen) {	/* Create a volume label entry */
+					res = dir_alloc(&dj, 1);	/* Allocate an entry */
+					if (res == FR_OK) {
+						mem_set(dj.dir, 0, SZDIRE);	/* Clear the entry */
+						if (_FS_EXFAT && fs->fs_type == FS_EXFAT) {
+							dj.dir[XDIR_Type] = 0x83;		/* Create 83 entry */
+							dj.dir[XDIR_NumLabel] = (BYTE)(slen / 2);
+							mem_cpy(dj.dir + XDIR_Label, dirvn, slen);
+						} else {
+							dj.dir[DIR_Attr] = AM_VOL;		/* Create volume label entry */
+							mem_cpy(dj.dir, dirvn, 11);
+						}
+						fs->wflag = 1;
+						res = sync_fs(fs);
+					}
+				}
+			}
+		}
+	}
+
+	LEAVE_FF(fs, res);
+}
+
+#endif /* !_FS_READONLY */
+#endif /* _USE_LABEL */
+
+
+
+#if _USE_EXPAND && !_FS_READONLY
+/*-----------------------------------------------------------------------*/
+/* Allocate a Contiguous Blocks to the File                              */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_expand (
+	FIL* fp,		/* Pointer to the file object */
+	FSIZE_t fsz,	/* File size to be expanded to */
+	BYTE opt		/* Operation mode 0:Find and prepare or 1:Find and allocate */
+)
+{
+	FRESULT res;
+	FATFS *fs;
+	DWORD n, clst, stcl, scl, ncl, tcl, lclst;
+
+
+	res = validate(&fp->obj, &fs);		/* Check validity of the file object */
+	if (res != FR_OK || (res = (FRESULT)fp->err) != FR_OK) LEAVE_FF(fs, res);
+	if (fsz == 0 || fp->obj.objsize != 0 || !(fp->flag & FA_WRITE)) LEAVE_FF(fs, FR_DENIED);
+#if _FS_EXFAT
+	if (fs->fs_type != FS_EXFAT && fsz >= 0x100000000) LEAVE_FF(fs, FR_DENIED);	/* Check if in size limit */
+#endif
+	n = (DWORD)fs->csize * SS(fs);	/* Cluster size */
+	tcl = (DWORD)(fsz / n) + ((fsz & (n - 1)) ? 1 : 0);	/* Number of clusters required */
+	stcl = fs->last_clst; lclst = 0;
+	if (stcl < 2 || stcl >= fs->n_fatent) stcl = 2;
+
+#if _FS_EXFAT
+	if (fs->fs_type == FS_EXFAT) {
+		scl = find_bitmap(fs, stcl, tcl);			/* Find a contiguous cluster block */
+		if (scl == 0) res = FR_DENIED;				/* No contiguous cluster block was found */
+		if (scl == 0xFFFFFFFF) res = FR_DISK_ERR;
+		if (res == FR_OK) {	/* A contiguous free area is found */
+			if (opt) {		/* Allocate it now */
+				res = change_bitmap(fs, scl, tcl, 1);	/* Mark the cluster block 'in use' */
+				lclst = scl + tcl - 1;
+			} else {		/* Set it as suggested point for next allocation */
+				lclst = scl - 1;
+			}
+		}
+	} else
+#endif
+	{
+		scl = clst = stcl; ncl = 0;
+		for (;;) {	/* Find a contiguous cluster block */
+			n = get_fat(&fp->obj, clst);
+			if (++clst >= fs->n_fatent) clst = 2;
+			if (n == 1) { res = FR_INT_ERR; break; }
+			if (n == 0xFFFFFFFF) { res = FR_DISK_ERR; break; }
+			if (n == 0) {	/* Is it a free cluster? */
+				if (++ncl == tcl) break;	/* Break if a contiguous cluster block is found */
+			} else {
+				scl = clst; ncl = 0;		/* Not a free cluster */
+			}
+			if (clst == stcl) { res = FR_DENIED; break; }	/* No contiguous cluster? */
+		}
+		if (res == FR_OK) {	/* A contiguous free area is found */
+			if (opt) {		/* Allocate it now */
+				for (clst = scl, n = tcl; n; clst++, n--) {	/* Create a cluster chain on the FAT */
+					res = put_fat(fs, clst, (n == 1) ? 0xFFFFFFFF : clst + 1);
+					if (res != FR_OK) break;
+					lclst = clst;
+				}
+			} else {		/* Set it as suggested point for next allocation */
+				lclst = scl - 1;
+			}
+		}
+	}
+
+	if (res == FR_OK) {
+		fs->last_clst = lclst;		/* Set suggested start cluster to start next */
+		if (opt) {	/* Is it allocated now? */
+			fp->obj.sclust = scl;		/* Update object allocation information */
+			fp->obj.objsize = fsz;
+			if (_FS_EXFAT) fp->obj.stat = 2;	/* Set status 'contiguous chain' */
+			fp->flag |= FA_MODIFIED;
+			if (fs->free_clst <= fs->n_fatent - 2) {	/* Update FSINFO */
+				fs->free_clst -= tcl;
+				fs->fsi_flag |= 1;
+			}
+		}
+	}
+
+	LEAVE_FF(fs, res);
+}
+
+#endif /* _USE_EXPAND && !_FS_READONLY */
+
+
+
+#if _USE_FORWARD
+/*-----------------------------------------------------------------------*/
+/* Forward data to the stream directly                                   */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_forward (
+	FIL* fp, 						/* Pointer to the file object */
+	UINT (*func)(const BYTE*,UINT),	/* Pointer to the streaming function */
+	UINT btf,						/* Number of bytes to forward */
+	UINT* bf						/* Pointer to number of bytes forwarded */
+)
+{
+	FRESULT res;
+	FATFS *fs;
+	DWORD clst, sect;
+	FSIZE_t remain;
+	UINT rcnt, csect;
+	BYTE *dbuf;
+
+
+	*bf = 0;	/* Clear transfer byte counter */
+	res = validate(&fp->obj, &fs);		/* Check validity of the file object */
+	if (res != FR_OK || (res = (FRESULT)fp->err) != FR_OK) LEAVE_FF(fs, res);
+	if (!(fp->flag & FA_READ)) LEAVE_FF(fs, FR_DENIED);	/* Check access mode */
+
+	remain = fp->obj.objsize - fp->fptr;
+	if (btf > remain) btf = (UINT)remain;			/* Truncate btf by remaining bytes */
+
+	for ( ;  btf && (*func)(0, 0);					/* Repeat until all data transferred or stream goes busy */
+		fp->fptr += rcnt, *bf += rcnt, btf -= rcnt) {
+		csect = (UINT)(fp->fptr / SS(fs) & (fs->csize - 1));	/* Sector offset in the cluster */
+		if (fp->fptr % SS(fs) == 0) {				/* On the sector boundary? */
+			if (csect == 0) {						/* On the cluster boundary? */
+				clst = (fp->fptr == 0) ?			/* On the top of the file? */
+					fp->obj.sclust : get_fat(&fp->obj, fp->clust);
+				if (clst <= 1) ABORT(fs, FR_INT_ERR);
+				if (clst == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR);
+				fp->clust = clst;					/* Update current cluster */
+			}
+		}
+		sect = clust2sect(fs, fp->clust);			/* Get current data sector */
+		if (!sect) ABORT(fs, FR_INT_ERR);
+		sect += csect;
+#if _FS_TINY
+		if (move_window(fs, sect) != FR_OK) ABORT(fs, FR_DISK_ERR);	/* Move sector window to the file data */
+		dbuf = fs->win;
+#else
+		if (fp->sect != sect) {		/* Fill sector cache with file data */
+#if !_FS_READONLY
+			if (fp->flag & FA_DIRTY) {		/* Write-back dirty sector cache */
+				if (disk_write(fs->drv, fp->buf, fp->sect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR);
+				fp->flag &= (BYTE)~FA_DIRTY;
+			}
+#endif
+			if (disk_read(fs->drv, fp->buf, sect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR);
+		}
+		dbuf = fp->buf;
+#endif
+		fp->sect = sect;
+		rcnt = SS(fs) - (UINT)fp->fptr % SS(fs);	/* Number of bytes left in the sector */
+		if (rcnt > btf) rcnt = btf;					/* Clip it by btr if needed */
+		rcnt = (*func)(dbuf + ((UINT)fp->fptr % SS(fs)), rcnt);	/* Forward the file data */
+		if (!rcnt) ABORT(fs, FR_INT_ERR);
+	}
+
+	LEAVE_FF(fs, FR_OK);
+}
+#endif /* _USE_FORWARD */
+
+
+
+#if _USE_MKFS && !_FS_READONLY
+/*-----------------------------------------------------------------------*/
+/* Create an FAT/exFAT volume                                            */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_mkfs (
+	const TCHAR* path,	/* Logical drive number */
+	BYTE opt,			/* Format option */
+	DWORD au,			/* Size of allocation unit (cluster) [byte] */
+	void* work,			/* Pointer to working buffer */
+	UINT len			/* Size of working buffer */
+)
+{
+	const UINT n_fats = 1;		/* Number of FATs for FAT12/16/32 volume (1 or 2) */
+	const UINT n_rootdir = 512;	/* Number of root directory entries for FAT12/16 volume */
+	static const WORD cst[] = {1, 4, 16, 64, 256, 512, 0};	/* Cluster size boundary for FAT12/16 volume (4Ks unit) */
+	static const WORD cst32[] = {1, 2, 4, 8, 16, 32, 0};	/* Cluster size boundary for FAT32 volume (128Ks unit) */
+	BYTE fmt, sys, *buf, *pte, pdrv, part;
+	WORD ss;
+	DWORD szb_buf, sz_buf, sz_blk, n_clst, pau, sect, nsect, n;
+	DWORD b_vol, b_fat, b_data;				/* Base LBA for volume, fat, data */
+	DWORD sz_vol, sz_rsv, sz_fat, sz_dir;	/* Size for volume, fat, dir, data */
+	UINT i;
+	int vol;
+	DSTATUS stat;
+#if _USE_TRIM || _FS_EXFAT
+	DWORD tbl[3];
+#endif
+
+
+	/* Check mounted drive and clear work area */
+	vol = get_ldnumber(&path);					/* Get target logical drive */
+	if (vol < 0) return FR_INVALID_DRIVE;
+	if (FatFs[vol]) FatFs[vol]->fs_type = 0;	/* Clear the volume */
+	pdrv = LD2PD(vol);	/* Physical drive */
+	part = LD2PT(vol);	/* Partition (0:create as new, 1-4:get from partition table) */
+
+	/* Check physical drive status */
+	stat = disk_initialize(pdrv);
+	if (stat & STA_NOINIT) return FR_NOT_READY;
+	if (stat & STA_PROTECT) return FR_WRITE_PROTECTED;
+	if (disk_ioctl(pdrv, GET_BLOCK_SIZE, &sz_blk) != RES_OK || !sz_blk || sz_blk > 32768 || (sz_blk & (sz_blk - 1))) sz_blk = 1;	/* Erase block to align data area */
+#if _MAX_SS != _MIN_SS		/* Get sector size of the medium if variable sector size cfg. */
+	if (disk_ioctl(pdrv, GET_SECTOR_SIZE, &ss) != RES_OK) return FR_DISK_ERR;
+	if (ss > _MAX_SS || ss < _MIN_SS || (ss & (ss - 1))) return FR_DISK_ERR;
+#else
+	ss = _MAX_SS;
+#endif
+	if ((au != 0 && au < ss) || au > 0x1000000 || (au & (au - 1))) return FR_INVALID_PARAMETER;	/* Check if au is valid */
+	au /= ss;	/* Cluster size in unit of sector */
+
+	/* Get working buffer */
+	buf = (BYTE*)work;		/* Working buffer */
+	sz_buf = len / ss;		/* Size of working buffer (sector) */
+	szb_buf = sz_buf * ss;	/* Size of working buffer (byte) */
+	if (!szb_buf) return FR_MKFS_ABORTED;
+
+	/* Determine where the volume to be located (b_vol, sz_vol) */
+	if (_MULTI_PARTITION && part != 0) {
+		/* Get partition information from partition table in the MBR */
+		if (disk_read(pdrv, buf, 0, 1) != RES_OK) return FR_DISK_ERR;	/* Load MBR */
+		if (ld_word(buf + BS_55AA) != 0xAA55) return FR_MKFS_ABORTED;	/* Check if MBR is valid */
+		pte = buf + (MBR_Table + (part - 1) * SZ_PTE);
+		if (!pte[PTE_System]) return FR_MKFS_ABORTED;	/* No partition? */
+		b_vol = ld_dword(pte + PTE_StLba);		/* Get volume start sector */
+		sz_vol = ld_dword(pte + PTE_SizLba);	/* Get volume size */
+	} else {
+		/* Create a single-partition in this function */
+		if (disk_ioctl(pdrv, GET_SECTOR_COUNT, &sz_vol) != RES_OK) return FR_DISK_ERR;
+		b_vol = (opt & FM_SFD) ? 0 : 63;		/* Volume start sector */
+		if (sz_vol < b_vol) return FR_MKFS_ABORTED;
+		sz_vol -= b_vol;						/* Volume size */
+	}
+	if (sz_vol < 128) return FR_MKFS_ABORTED;	/* Check if volume size is >=128s */
+
+	/* Pre-determine the FAT type */
+	do {
+		if (_FS_EXFAT && (opt & FM_EXFAT)) {	/* exFAT possible? */
+			if ((opt & FM_ANY) == FM_EXFAT || sz_vol >= 0x4000000 || au > 128) {	/* exFAT only, vol >= 64Ms or au > 128s ? */
+				fmt = FS_EXFAT; break;
+			}
+		}
+		if (au > 128) return FR_INVALID_PARAMETER;	/* Too large au for FAT/FAT32 */
+		if (opt & FM_FAT32) {	/* FAT32 possible? */
+			if ((opt & FM_ANY) == FM_FAT32 || !(opt & FM_FAT)) {	/* FAT32 only or no-FAT? */
+				fmt = FS_FAT32; break;
+			}
+		}
+		if (!(opt & FM_FAT)) return FR_INVALID_PARAMETER;	/* no-FAT? */
+		fmt = FS_FAT16;
+	} while (0);
+
+#if _FS_EXFAT
+	if (fmt == FS_EXFAT) {	/* Create an exFAT volume */
+		DWORD szb_bit, szb_case, sum, nb, cl;
+		WCHAR ch, si;
+		UINT j, st;
+		BYTE b;
+
+		if (sz_vol < 0x1000) return FR_MKFS_ABORTED;	/* Too small volume? */
+#if _USE_TRIM
+		tbl[0] = b_vol; tbl[1] = b_vol + sz_vol - 1;	/* Inform the device the volume area may be erased */
+		disk_ioctl(pdrv, CTRL_TRIM, tbl);
+#endif
+		/* Determine FAT location, data location and number of clusters */
+		if (!au) {	/* au auto-selection */
+			au = 8;
+			if (sz_vol >= 0x80000) au = 64;		/* >= 512Ks */
+			if (sz_vol >= 0x4000000) au = 256;	/* >= 64Ms */
+		}
+		b_fat = b_vol + 32;										/* FAT start at offset 32 */
+		sz_fat = ((sz_vol / au + 2) * 4 + ss - 1) / ss;			/* Number of FAT sectors */
+		b_data = (b_fat + sz_fat + sz_blk - 1) & ~(sz_blk - 1);	/* Align data area to the erase block boundary */
+		if (b_data >= sz_vol / 2) return FR_MKFS_ABORTED;		/* Too small volume? */
+		n_clst = (sz_vol - (b_data - b_vol)) / au;				/* Number of clusters */
+		if (n_clst <16) return FR_MKFS_ABORTED;					/* Too few clusters? */
+		if (n_clst > MAX_EXFAT) return FR_MKFS_ABORTED;			/* Too many clusters? */
+
+		szb_bit = (n_clst + 7) / 8;						/* Size of allocation bitmap */
+		tbl[0] = (szb_bit + au * ss - 1) / (au * ss);	/* Number of allocation bitmap clusters */
+
+		/* Create a compressed up-case table */
+		sect = b_data + au * tbl[0];	/* Table start sector */
+		sum = 0;						/* Table checksum to be stored in the 82 entry */
+		st = si = i = j = szb_case = 0;
+		do {
+			switch (st) {
+			case 0:
+				ch = ff_wtoupper(si);	/* Get an up-case char */
+				if (ch != si) {
+					si++; break;		/* Store the up-case char if exist */
+				}
+				for (j = 1; (WCHAR)(si + j) && (WCHAR)(si + j) == ff_wtoupper((WCHAR)(si + j)); j++) ;	/* Get run length of no-case block */
+				if (j >= 128) {
+					ch = 0xFFFF; st = 2; break;	/* Compress the no-case block if run is >= 128 */
+				}
+				st = 1;			/* Do not compress short run */
+				/* go to next case */
+			case 1:
+				ch = si++;		/* Fill the short run */
+				if (--j == 0) st = 0;
+				break;
+
+			default:
+				ch = (WCHAR)j; si += j;	/* Number of chars to skip */
+				st = 0;
+			}
+			sum = xsum32(buf[i + 0] = (BYTE)ch, sum);		/* Put it into the write buffer */
+			sum = xsum32(buf[i + 1] = (BYTE)(ch >> 8), sum);
+			i += 2; szb_case += 2;
+			if (!si || i == szb_buf) {		/* Write buffered data when buffer full or end of process */
+				n = (i + ss - 1) / ss;
+				if (disk_write(pdrv, buf, sect, n) != RES_OK) return FR_DISK_ERR;
+				sect += n; i = 0;
+			}
+		} while (si);
+		tbl[1] = (szb_case + au * ss - 1) / (au * ss);	/* Number of up-case table clusters */
+		tbl[2] = 1;										/* Number of root dir clusters */
+
+		/* Initialize the allocation bitmap */
+		sect = b_data; nsect = (szb_bit + ss - 1) / ss;	/* Start of bitmap and number of sectors */
+		nb = tbl[0] + tbl[1] + tbl[2];					/* Number of clusters in-use by system */
+		do {
+			mem_set(buf, 0, szb_buf);
+			for (i = 0; nb >= 8 && i < szb_buf; buf[i++] = 0xFF, nb -= 8) ;
+			for (b = 1; nb && i < szb_buf; buf[i] |= b, b <<= 1, nb--) ;
+			n = (nsect > sz_buf) ? sz_buf : nsect;		/* Write the buffered data */
+			if (disk_write(pdrv, buf, sect, n) != RES_OK) return FR_DISK_ERR;
+			sect += n; nsect -= n;
+		} while (nsect);
+
+		/* Initialize the FAT */
+		sect = b_fat; nsect = sz_fat;	/* Start of FAT and number of FAT sectors */
+		j = nb = cl = 0;
+		do {
+			mem_set(buf, 0, szb_buf); i = 0;	/* Clear work area and reset write index */
+			if (cl == 0) {	/* Set entry 0 and 1 */
+				st_dword(buf + i, 0xFFFFFFF8); i += 4; cl++;
+				st_dword(buf + i, 0xFFFFFFFF); i += 4; cl++;
+			}
+			do {			/* Create chains of bitmap, up-case and root dir */
+				while (nb && i < szb_buf) {			/* Create a chain */
+					st_dword(buf + i, (nb > 1) ? cl + 1 : 0xFFFFFFFF);
+					i += 4; cl++; nb--;
+				}
+				if (!nb && j < 3) nb = tbl[j++];	/* Next chain */
+			} while (nb && i < szb_buf);
+			n = (nsect > sz_buf) ? sz_buf : nsect;	/* Write the buffered data */
+			if (disk_write(pdrv, buf, sect, n) != RES_OK) return FR_DISK_ERR;
+			sect += n; nsect -= n;
+		} while (nsect);
+
+		/* Initialize the root directory */
+		mem_set(buf, 0, szb_buf);
+		buf[SZDIRE * 0 + 0] = 0x83;		/* 83 entry (volume label) */
+		buf[SZDIRE * 1 + 0] = 0x81;		/* 81 entry (allocation bitmap) */
+		st_dword(buf + SZDIRE * 1 + 20, 2);
+		st_dword(buf + SZDIRE * 1 + 24, szb_bit);
+		buf[SZDIRE * 2 + 0] = 0x82;		/* 82 entry (up-case table) */
+		st_dword(buf + SZDIRE * 2 + 4, sum);
+		st_dword(buf + SZDIRE * 2 + 20, 2 + tbl[0]);
+		st_dword(buf + SZDIRE * 2 + 24, szb_case);
+		sect = b_data + au * (tbl[0] + tbl[1]);	nsect = au;	/* Start of the root directory and number of sectors */
+		do {	/* Fill root directory sectors */
+			n = (nsect > sz_buf) ? sz_buf : nsect;
+			if (disk_write(pdrv, buf, sect, n) != RES_OK) return FR_DISK_ERR;
+			mem_set(buf, 0, ss);
+			sect += n; nsect -= n;
+		} while (nsect);
+
+		/* Create two set of the exFAT VBR blocks */
+		sect = b_vol;
+		for (n = 0; n < 2; n++) {
+			/* Main record (+0) */
+			mem_set(buf, 0, ss);
+			mem_cpy(buf + BS_JmpBoot, "\xEB\x76\x90" "EXFAT   ", 11);	/* Boot jump code (x86), OEM name */
+			st_dword(buf + BPB_VolOfsEx, b_vol);					/* Volume offset in the physical drive [sector] */
+			st_dword(buf + BPB_TotSecEx, sz_vol);					/* Volume size [sector] */
+			st_dword(buf + BPB_FatOfsEx, b_fat - b_vol);			/* FAT offset [sector] */
+			st_dword(buf + BPB_FatSzEx, sz_fat);					/* FAT size [sector] */
+			st_dword(buf + BPB_DataOfsEx, b_data - b_vol);			/* Data offset [sector] */
+			st_dword(buf + BPB_NumClusEx, n_clst);					/* Number of clusters */
+			st_dword(buf + BPB_RootClusEx, 2 + tbl[0] + tbl[1]);	/* Root dir cluster # */
+			st_dword(buf + BPB_VolIDEx, GET_FATTIME());				/* VSN */
+			st_word(buf + BPB_FSVerEx, 0x100);						/* File system version (1.00) */
+			for (buf[BPB_BytsPerSecEx] = 0, i = ss; i >>= 1; buf[BPB_BytsPerSecEx]++) ;	/* Log2 of sector size [byte] */
+			for (buf[BPB_SecPerClusEx] = 0, i = au; i >>= 1; buf[BPB_SecPerClusEx]++) ;	/* Log2 of cluster size [sector] */
+			buf[BPB_NumFATsEx] = 1;					/* Number of FATs */
+			buf[BPB_DrvNumEx] = 0x80;				/* Drive number (for int13) */
+			st_word(buf + BS_BootCodeEx, 0xFEEB);	/* Boot code (x86) */
+			st_word(buf + BS_55AA, 0xAA55);			/* Signature (placed here regardless of sector size) */
+			for (i = sum = 0; i < ss; i++) {		/* VBR checksum */
+				if (i != BPB_VolFlagEx && i != BPB_VolFlagEx + 1 && i != BPB_PercInUseEx) sum = xsum32(buf[i], sum);
+			}
+			if (disk_write(pdrv, buf, sect++, 1) != RES_OK) return FR_DISK_ERR;
+			/* Extended bootstrap record (+1..+8) */
+			mem_set(buf, 0, ss);
+			st_word(buf + ss - 2, 0xAA55);	/* Signature (placed at end of sector) */
+			for (j = 1; j < 9; j++) {
+				for (i = 0; i < ss; sum = xsum32(buf[i++], sum)) ;	/* VBR checksum */
+				if (disk_write(pdrv, buf, sect++, 1) != RES_OK) return FR_DISK_ERR;
+			}
+			/* OEM/Reserved record (+9..+10) */
+			mem_set(buf, 0, ss);
+			for ( ; j < 11; j++) {
+				for (i = 0; i < ss; sum = xsum32(buf[i++], sum)) ;	/* VBR checksum */
+				if (disk_write(pdrv, buf, sect++, 1) != RES_OK) return FR_DISK_ERR;
+			}
+			/* Sum record (+11) */
+			for (i = 0; i < ss; i += 4) st_dword(buf + i, sum);		/* Fill with checksum value */
+			if (disk_write(pdrv, buf, sect++, 1) != RES_OK) return FR_DISK_ERR;
+		}
+
+	} else
+#endif	/* _FS_EXFAT */
+	{	/* Create an FAT12/16/32 volume */
+		do {
+			pau = au;
+			/* Pre-determine number of clusters and FAT sub-type */
+			if (fmt == FS_FAT32) {	/* FAT32 volume */
+				if (!pau) {	/* au auto-selection */
+					n = sz_vol / 0x20000;	/* Volume size in unit of 128KS */
+					for (i = 0, pau = 1; cst32[i] && cst32[i] <= n; i++, pau <<= 1) ;	/* Get from table */
+				}
+				n_clst = sz_vol / pau;	/* Number of clusters */
+				sz_fat = (n_clst * 4 + 8 + ss - 1) / ss;	/* FAT size [sector] */
+				sz_rsv = 32;	/* Number of reserved sectors */
+				sz_dir = 0;		/* No static directory */
+				if (n_clst <= MAX_FAT16 || n_clst > MAX_FAT32) return FR_MKFS_ABORTED;
+			} else {				/* FAT12/16 volume */
+				if (!pau) {	/* au auto-selection */
+					n = sz_vol / 0x1000;	/* Volume size in unit of 4KS */
+					for (i = 0, pau = 1; cst[i] && cst[i] <= n; i++, pau <<= 1) ;	/* Get from table */
+				}
+				n_clst = sz_vol / pau;
+				if (n_clst > MAX_FAT12) {
+					n = n_clst * 2 + 4;		/* FAT size [byte] */
+				} else {
+					fmt = FS_FAT12;
+					n = (n_clst * 3 + 1) / 2 + 3;	/* FAT size [byte] */
+				}
+				sz_fat = (n + ss - 1) / ss;		/* FAT size [sector] */
+				sz_rsv = 1;						/* Number of reserved sectors */
+				sz_dir = (DWORD)n_rootdir * SZDIRE / ss;	/* Rootdir size [sector] */
+			}
+			b_fat = b_vol + sz_rsv;						/* FAT base */
+			b_data = b_fat + sz_fat * n_fats + sz_dir;	/* Data base */
+
+			/* Align data base to erase block boundary (for flash memory media) */
+			n = ((b_data + sz_blk - 1) & ~(sz_blk - 1)) - b_data;	/* Next nearest erase block from current data base */
+			if (fmt == FS_FAT32) {		/* FAT32: Move FAT base */
+				sz_rsv += n; b_fat += n;
+			} else {					/* FAT12/16: Expand FAT size */
+				sz_fat += n / n_fats;
+			}
+
+			/* Determine number of clusters and final check of validity of the FAT sub-type */
+			if (sz_vol < b_data + pau * 16 - b_vol) return FR_MKFS_ABORTED;	/* Too small volume */
+			n_clst = (sz_vol - sz_rsv - sz_fat * n_fats - sz_dir) / pau;
+			if (fmt == FS_FAT32) {
+				if (n_clst <= MAX_FAT16) {	/* Too few clusters for FAT32 */
+					if (!au && (au = pau / 2) != 0) continue;	/* Adjust cluster size and retry */
+					return FR_MKFS_ABORTED;
+				}
+			}
+			if (fmt == FS_FAT16) {
+				if (n_clst > MAX_FAT16) {	/* Too many clusters for FAT16 */
+					if (!au && (pau * 2) <= 64) {
+						au = pau * 2; continue;		/* Adjust cluster size and retry */
+					}
+					if ((opt & FM_FAT32)) {
+						fmt = FS_FAT32; continue;	/* Switch type to FAT32 and retry */
+					}
+					if (!au && (au = pau * 2) <= 128) continue;	/* Adjust cluster size and retry */
+					return FR_MKFS_ABORTED;
+				}
+				if  (n_clst <= MAX_FAT12) {	/* Too few clusters for FAT16 */
+					if (!au && (au = pau * 2) <= 128) continue;	/* Adjust cluster size and retry */
+					return FR_MKFS_ABORTED;
+				}
+			}
+			if (fmt == FS_FAT12 && n_clst > MAX_FAT12) return FR_MKFS_ABORTED;	/* Too many clusters for FAT12 */
+
+			/* Ok, it is the valid cluster configuration */
+			break;
+		} while (1);
+
+#if _USE_TRIM
+		tbl[0] = b_vol; tbl[1] = b_vol + sz_vol - 1;	/* Inform the device the volume area can be erased */
+		disk_ioctl(pdrv, CTRL_TRIM, tbl);
+#endif
+		/* Create FAT VBR */
+		mem_set(buf, 0, ss);
+		mem_cpy(buf + BS_JmpBoot, "\xEB\xFE\x90" "MSDOS5.0", 11);/* Boot jump code (x86), OEM name */
+		st_word(buf + BPB_BytsPerSec, ss);				/* Sector size [byte] */
+		buf[BPB_SecPerClus] = (BYTE)pau;				/* Cluster size [sector] */
+		st_word(buf + BPB_RsvdSecCnt, (WORD)sz_rsv);	/* Size of reserved area */
+		buf[BPB_NumFATs] = (BYTE)n_fats;				/* Number of FATs */
+		st_word(buf + BPB_RootEntCnt, (WORD)((fmt == FS_FAT32) ? 0 : n_rootdir));	/* Number of root directory entries */
+		if (sz_vol < 0x10000) {
+			st_word(buf + BPB_TotSec16, (WORD)sz_vol);	/* Volume size in 16-bit LBA */
+		} else {
+			st_dword(buf + BPB_TotSec32, sz_vol);		/* Volume size in 32-bit LBA */
+		}
+		buf[BPB_Media] = 0xF8;							/* Media descriptor byte */
+		st_word(buf + BPB_SecPerTrk, 63);				/* Number of sectors per track (for int13) */
+		st_word(buf + BPB_NumHeads, 255);				/* Number of heads (for int13) */
+		st_dword(buf + BPB_HiddSec, b_vol);				/* Volume offset in the physical drive [sector] */
+		if (fmt == FS_FAT32) {
+			st_dword(buf + BS_VolID32, GET_FATTIME());	/* VSN */
+			st_dword(buf + BPB_FATSz32, sz_fat);		/* FAT size [sector] */
+			st_dword(buf + BPB_RootClus32, 2);			/* Root directory cluster # (2) */
+			st_word(buf + BPB_FSInfo32, 1);				/* Offset of FSINFO sector (VBR + 1) */
+			st_word(buf + BPB_BkBootSec32, 6);			/* Offset of backup VBR (VBR + 6) */
+			buf[BS_DrvNum32] = 0x80;					/* Drive number (for int13) */
+			buf[BS_BootSig32] = 0x29;					/* Extended boot signature */
+			mem_cpy(buf + BS_VolLab32, "NO NAME    " "FAT32   ", 19);	/* Volume label, FAT signature */
+		} else {
+			st_dword(buf + BS_VolID, GET_FATTIME());	/* VSN */
+			st_word(buf + BPB_FATSz16, (WORD)sz_fat);	/* FAT size [sector] */
+			buf[BS_DrvNum] = 0x80;						/* Drive number (for int13) */
+			buf[BS_BootSig] = 0x29;						/* Extended boot signature */
+			mem_cpy(buf + BS_VolLab, "NO NAME    " "FAT     ", 19);	/* Volume label, FAT signature */
+		}
+		st_word(buf + BS_55AA, 0xAA55);					/* Signature (offset is fixed here regardless of sector size) */
+		if (disk_write(pdrv, buf, b_vol, 1) != RES_OK) return FR_DISK_ERR;	/* Write it to the VBR sector */
+
+		/* Create FSINFO record if needed */
+		if (fmt == FS_FAT32) {
+			disk_write(pdrv, buf, b_vol + 6, 1);		/* Write backup VBR (VBR + 6) */
+			mem_set(buf, 0, ss);
+			st_dword(buf + FSI_LeadSig, 0x41615252);
+			st_dword(buf + FSI_StrucSig, 0x61417272);
+			st_dword(buf + FSI_Free_Count, n_clst - 1);	/* Number of free clusters */
+			st_dword(buf + FSI_Nxt_Free, 2);			/* Last allocated cluster# */
+			st_word(buf + BS_55AA, 0xAA55);
+			disk_write(pdrv, buf, b_vol + 7, 1);		/* Write backup FSINFO (VBR + 7) */
+			disk_write(pdrv, buf, b_vol + 1, 1);		/* Write original FSINFO (VBR + 1) */
+		}
+
+		/* Initialize FAT area */
+		mem_set(buf, 0, (UINT)szb_buf);
+		sect = b_fat;		/* FAT start sector */
+		for (i = 0; i < n_fats; i++) {			/* Initialize FATs each */
+			if (fmt == FS_FAT32) {
+				st_dword(buf + 0, 0xFFFFFFF8);	/* Entry 0 */
+				st_dword(buf + 4, 0xFFFFFFFF);	/* Entry 1 */
+				st_dword(buf + 8, 0x0FFFFFFF);	/* Entry 2 (root directory) */
+			} else {
+				st_dword(buf + 0, (fmt == FS_FAT12) ? 0xFFFFF8 : 0xFFFFFFF8);	/* Entry 0 and 1 */
+			}
+			nsect = sz_fat;		/* Number of FAT sectors */
+			do {	/* Fill FAT sectors */
+				n = (nsect > sz_buf) ? sz_buf : nsect;
+				if (disk_write(pdrv, buf, sect, (UINT)n) != RES_OK) return FR_DISK_ERR;
+				mem_set(buf, 0, ss);
+				sect += n; nsect -= n;
+			} while (nsect);
+		}
+
+		/* Initialize root directory (fill with zero) */
+		nsect = (fmt == FS_FAT32) ? pau : sz_dir;	/* Number of root directory sectors */
+		do {
+			n = (nsect > sz_buf) ? sz_buf : nsect;
+			if (disk_write(pdrv, buf, sect, (UINT)n) != RES_OK) return FR_DISK_ERR;
+			sect += n; nsect -= n;
+		} while (nsect);
+	}
+
+	/* Determine system ID in the partition table */
+	if (_FS_EXFAT && fmt == FS_EXFAT) {
+		sys = 0x07;			/* HPFS/NTFS/exFAT */
+	} else {
+		if (fmt == FS_FAT32) {
+			sys = 0x0C;		/* FAT32X */
+		} else {
+			if (sz_vol >= 0x10000) {
+				sys = 0x06;	/* FAT12/16 (>=64KS) */
+			} else {
+				sys = (fmt == FS_FAT16) ? 0x04 : 0x01;	/* FAT16 (<64KS) : FAT12 (<64KS) */
+			}
+		}
+	}
+
+	/* Update partition information */
+	if (_MULTI_PARTITION && part != 0) {	/* Created in the existing partition */
+		/* Update system ID in the partition table */
+		if (disk_read(pdrv, buf, 0, 1) != RES_OK) return FR_DISK_ERR;	/* Read the MBR */
+		buf[MBR_Table + (part - 1) * SZ_PTE + PTE_System] = sys;		/* Set system ID */
+		if (disk_write(pdrv, buf, 0, 1) != RES_OK) return FR_DISK_ERR;	/* Write it back to the MBR */
+	} else {								/* Created as a new single partition */
+		if (!(opt & FM_SFD)) {	/* Create partition table if in FDISK format */
+			mem_set(buf, 0, ss);
+			st_word(buf + BS_55AA, 0xAA55);		/* MBR signature */
+			pte = buf + MBR_Table;				/* Create partition table for single partition in the drive */
+			pte[PTE_Boot] = 0;					/* Boot indicator */
+			pte[PTE_StHead] = 1;				/* Start head */
+			pte[PTE_StSec] = 1;					/* Start sector */
+			pte[PTE_StCyl] = 0;					/* Start cylinder */
+			pte[PTE_System] = sys;				/* System type */
+			n = (b_vol + sz_vol) / (63 * 255);	/* (End CHS may be invalid) */
+			pte[PTE_EdHead] = 254;				/* End head */
+			pte[PTE_EdSec] = (BYTE)(n >> 2 | 63);	/* End sector */
+			pte[PTE_EdCyl] = (BYTE)n;			/* End cylinder */
+			st_dword(pte + PTE_StLba, b_vol);	/* Start offset in LBA */
+			st_dword(pte + PTE_SizLba, sz_vol);	/* Size in sectors */
+			if (disk_write(pdrv, buf, 0, 1) != RES_OK) return FR_DISK_ERR;	/* Write it to the MBR */
+		}
+	}
+
+	if (disk_ioctl(pdrv, CTRL_SYNC, 0) != RES_OK) return FR_DISK_ERR;
+
+	return FR_OK;
+}
+
+
+
+#if _MULTI_PARTITION
+/*-----------------------------------------------------------------------*/
+/* Create partition table on the physical drive                          */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_fdisk (
+	BYTE pdrv,			/* Physical drive number */
+	const DWORD* szt,	/* Pointer to the size table for each partitions */
+	void* work			/* Pointer to the working buffer */
+)
+{
+	UINT i, n, sz_cyl, tot_cyl, b_cyl, e_cyl, p_cyl;
+	BYTE s_hd, e_hd, *p, *buf = (BYTE*)work;
+	DSTATUS stat;
+	DWORD sz_disk, sz_part, s_part;
+
+
+	stat = disk_initialize(pdrv);
+	if (stat & STA_NOINIT) return FR_NOT_READY;
+	if (stat & STA_PROTECT) return FR_WRITE_PROTECTED;
+	if (disk_ioctl(pdrv, GET_SECTOR_COUNT, &sz_disk)) return FR_DISK_ERR;
+
+	/* Determine the CHS without any consideration of the drive geometry */
+	for (n = 16; n < 256 && sz_disk / n / 63 > 1024; n *= 2) ;
+	if (n == 256) n--;
+	e_hd = n - 1;
+	sz_cyl = 63 * n;
+	tot_cyl = sz_disk / sz_cyl;
+
+	/* Create partition table */
+	mem_set(buf, 0, _MAX_SS);
+	p = buf + MBR_Table; b_cyl = 0;
+	for (i = 0; i < 4; i++, p += SZ_PTE) {
+		p_cyl = (szt[i] <= 100U) ? (DWORD)tot_cyl * szt[i] / 100 : szt[i] / sz_cyl;	/* Number of cylinders */
+		if (!p_cyl) continue;
+		s_part = (DWORD)sz_cyl * b_cyl;
+		sz_part = (DWORD)sz_cyl * p_cyl;
+		if (i == 0) {	/* Exclude first track of cylinder 0 */
+			s_hd = 1;
+			s_part += 63; sz_part -= 63;
+		} else {
+			s_hd = 0;
+		}
+		e_cyl = b_cyl + p_cyl - 1;	/* End cylinder */
+		if (e_cyl >= tot_cyl) return FR_INVALID_PARAMETER;
+
+		/* Set partition table */
+		p[1] = s_hd;						/* Start head */
+		p[2] = (BYTE)((b_cyl >> 2) + 1);	/* Start sector */
+		p[3] = (BYTE)b_cyl;					/* Start cylinder */
+		p[4] = 0x07;						/* System type (temporary setting) */
+		p[5] = e_hd;						/* End head */
+		p[6] = (BYTE)((e_cyl >> 2) + 63);	/* End sector */
+		p[7] = (BYTE)e_cyl;					/* End cylinder */
+		st_dword(p + 8, s_part);			/* Start sector in LBA */
+		st_dword(p + 12, sz_part);			/* Number of sectors */
+
+		/* Next partition */
+		b_cyl += p_cyl;
+	}
+	st_word(p, 0xAA55);
+
+	/* Write it to the MBR */
+	return (disk_write(pdrv, buf, 0, 1) != RES_OK || disk_ioctl(pdrv, CTRL_SYNC, 0) != RES_OK) ? FR_DISK_ERR : FR_OK;
+}
+
+#endif /* _MULTI_PARTITION */
+#endif /* _USE_MKFS && !_FS_READONLY */
+
+
+
+
+#if _USE_STRFUNC
+/*-----------------------------------------------------------------------*/
+/* Get a string from the file                                            */
+/*-----------------------------------------------------------------------*/
+
+TCHAR* f_gets (
+	TCHAR* buff,	/* Pointer to the string buffer to read */
+	int len,		/* Size of string buffer (characters) */
+	FIL* fp			/* Pointer to the file object */
+)
+{
+	int n = 0;
+	TCHAR c, *p = buff;
+	BYTE s[2];
+	UINT rc;
+
+
+	while (n < len - 1) {	/* Read characters until buffer gets filled */
+#if _LFN_UNICODE
+#if _STRF_ENCODE == 3		/* Read a character in UTF-8 */
+		f_read(fp, s, 1, &rc);
+		if (rc != 1) break;
+		c = s[0];
+		if (c >= 0x80) {
+			if (c < 0xC0) continue;	/* Skip stray trailer */
+			if (c < 0xE0) {			/* Two-byte sequence (0x80-0x7FF) */
+				f_read(fp, s, 1, &rc);
+				if (rc != 1) break;
+				c = (c & 0x1F) << 6 | (s[0] & 0x3F);
+				if (c < 0x80) c = '?';	/* Reject invalid code range */
+			} else {
+				if (c < 0xF0) {		/* Three-byte sequence (0x800-0xFFFF) */
+					f_read(fp, s, 2, &rc);
+					if (rc != 2) break;
+					c = c << 12 | (s[0] & 0x3F) << 6 | (s[1] & 0x3F);
+					if (c < 0x800) c = '?';	/* Reject invalid code range */
+				} else {			/* Reject four-byte sequence */
+					c = '?';
+				}
+			}
+		}
+#elif _STRF_ENCODE == 2		/* Read a character in UTF-16BE */
+		f_read(fp, s, 2, &rc);
+		if (rc != 2) break;
+		c = s[1] + (s[0] << 8);
+#elif _STRF_ENCODE == 1		/* Read a character in UTF-16LE */
+		f_read(fp, s, 2, &rc);
+		if (rc != 2) break;
+		c = s[0] + (s[1] << 8);
+#else						/* Read a character in ANSI/OEM */
+		f_read(fp, s, 1, &rc);
+		if (rc != 1) break;
+		c = s[0];
+		if (IsDBCS1(c)) {
+			f_read(fp, s, 1, &rc);
+			if (rc != 1) break;
+			c = (c << 8) + s[0];
+		}
+		c = ff_convert(c, 1);	/* OEM -> Unicode */
+		if (!c) c = '?';
+#endif
+#else						/* Read a character without conversion */
+		f_read(fp, s, 1, &rc);
+		if (rc != 1) break;
+		c = s[0];
+#endif
+		if (_USE_STRFUNC == 2 && c == '\r') continue;	/* Strip '\r' */
+		*p++ = c;
+		n++;
+		if (c == '\n') break;		/* Break on EOL */
+	}
+	*p = 0;
+	return n ? buff : 0;			/* When no data read (eof or error), return with error. */
+}
+
+
+
+
+#if !_FS_READONLY
+#include <stdarg.h>
+/*-----------------------------------------------------------------------*/
+/* Put a character to the file                                           */
+/*-----------------------------------------------------------------------*/
+
+typedef struct {
+	FIL *fp;		/* Ptr to the writing file */
+	int idx, nchr;	/* Write index of buf[] (-1:error), number of chars written */
+	BYTE buf[64];	/* Write buffer */
+} putbuff;
+
+
+static
+void putc_bfd (		/* Buffered write with code conversion */
+	putbuff* pb,
+	TCHAR c
+)
+{
+	UINT bw;
+	int i;
+
+
+	if (_USE_STRFUNC == 2 && c == '\n') {	 /* LF -> CRLF conversion */
+		putc_bfd(pb, '\r');
+	}
+
+	i = pb->idx;		/* Write index of pb->buf[] */
+	if (i < 0) return;
+
+#if _LFN_UNICODE
+#if _STRF_ENCODE == 3			/* Write a character in UTF-8 */
+	if (c < 0x80) {				/* 7-bit */
+		pb->buf[i++] = (BYTE)c;
+	} else {
+		if (c < 0x800) {		/* 11-bit */
+			pb->buf[i++] = (BYTE)(0xC0 | c >> 6);
+		} else {				/* 16-bit */
+			pb->buf[i++] = (BYTE)(0xE0 | c >> 12);
+			pb->buf[i++] = (BYTE)(0x80 | (c >> 6 & 0x3F));
+		}
+		pb->buf[i++] = (BYTE)(0x80 | (c & 0x3F));
+	}
+#elif _STRF_ENCODE == 2			/* Write a character in UTF-16BE */
+	pb->buf[i++] = (BYTE)(c >> 8);
+	pb->buf[i++] = (BYTE)c;
+#elif _STRF_ENCODE == 1			/* Write a character in UTF-16LE */
+	pb->buf[i++] = (BYTE)c;
+	pb->buf[i++] = (BYTE)(c >> 8);
+#else							/* Write a character in ANSI/OEM */
+	c = ff_convert(c, 0);	/* Unicode -> OEM */
+	if (!c) c = '?';
+	if (c >= 0x100)
+		pb->buf[i++] = (BYTE)(c >> 8);
+	pb->buf[i++] = (BYTE)c;
+#endif
+#else							/* Write a character without conversion */
+	pb->buf[i++] = (BYTE)c;
+#endif
+
+	if (i >= (int)(sizeof pb->buf) - 3) {	/* Write buffered characters to the file */
+		f_write(pb->fp, pb->buf, (UINT)i, &bw);
+		i = (bw == (UINT)i) ? 0 : -1;
+	}
+	pb->idx = i;
+	pb->nchr++;
+}
+
+
+static
+int putc_flush (		/* Flush left characters in the buffer */
+	putbuff* pb
+)
+{
+	UINT nw;
+
+	if (   pb->idx >= 0	/* Flush buffered characters to the file */
+		&& f_write(pb->fp, pb->buf, (UINT)pb->idx, &nw) == FR_OK
+		&& (UINT)pb->idx == nw) return pb->nchr;
+	return EOF;
+}
+
+
+static
+void putc_init (		/* Initialize write buffer */
+	putbuff* pb,
+	FIL* fp
+)
+{
+	pb->fp = fp;
+	pb->nchr = pb->idx = 0;
+}
+
+
+
+int f_putc (
+	TCHAR c,	/* A character to be output */
+	FIL* fp		/* Pointer to the file object */
+)
+{
+	putbuff pb;
+
+
+	putc_init(&pb, fp);
+	putc_bfd(&pb, c);	/* Put the character */
+	return putc_flush(&pb);
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Put a string to the file                                              */
+/*-----------------------------------------------------------------------*/
+
+int f_puts (
+	const TCHAR* str,	/* Pointer to the string to be output */
+	FIL* fp				/* Pointer to the file object */
+)
+{
+	putbuff pb;
+
+
+	putc_init(&pb, fp);
+	while (*str) putc_bfd(&pb, *str++);		/* Put the string */
+	return putc_flush(&pb);
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Put a formatted string to the file                                    */
+/*-----------------------------------------------------------------------*/
+
+int f_printf (
+	FIL* fp,			/* Pointer to the file object */
+	const TCHAR* fmt,	/* Pointer to the format string */
+	...					/* Optional arguments... */
+)
+{
+	va_list arp;
+	putbuff pb;
+	BYTE f, r;
+	UINT i, j, w;
+	DWORD v;
+	TCHAR c, d, str[32], *p;
+
+
+	putc_init(&pb, fp);
+
+	va_start(arp, fmt);
+
+	for (;;) {
+		c = *fmt++;
+		if (c == 0) break;			/* End of string */
+		if (c != '%') {				/* Non escape character */
+			putc_bfd(&pb, c);
+			continue;
+		}
+		w = f = 0;
+		c = *fmt++;
+		if (c == '0') {				/* Flag: '0' padding */
+			f = 1; c = *fmt++;
+		} else {
+			if (c == '-') {			/* Flag: left justified */
+				f = 2; c = *fmt++;
+			}
+		}
+		while (IsDigit(c)) {		/* Precision */
+			w = w * 10 + c - '0';
+			c = *fmt++;
+		}
+		if (c == 'l' || c == 'L') {	/* Prefix: Size is long int */
+			f |= 4; c = *fmt++;
+		}
+		if (!c) break;
+		d = c;
+		if (IsLower(d)) d -= 0x20;
+		switch (d) {				/* Type is... */
+		case 'S' :					/* String */
+			p = va_arg(arp, TCHAR*);
+			for (j = 0; p[j]; j++) ;
+			if (!(f & 2)) {
+				while (j++ < w) putc_bfd(&pb, ' ');
+			}
+			while (*p) putc_bfd(&pb, *p++);
+			while (j++ < w) putc_bfd(&pb, ' ');
+			continue;
+
+		case 'C' :					/* Character */
+			putc_bfd(&pb, (TCHAR)va_arg(arp, int)); continue;
+
+		case 'B' :					/* Binary */
+			r = 2; break;
+
+		case 'O' :					/* Octal */
+			r = 8; break;
+
+		case 'D' :					/* Signed decimal */
+		case 'U' :					/* Unsigned decimal */
+			r = 10; break;
+
+		case 'X' :					/* Hexdecimal */
+			r = 16; break;
+
+		default:					/* Unknown type (pass-through) */
+			putc_bfd(&pb, c); continue;
+		}
+
+		/* Get an argument and put it in numeral */
+		v = (f & 4) ? (DWORD)va_arg(arp, long) : ((d == 'D') ? (DWORD)(long)va_arg(arp, int) : (DWORD)va_arg(arp, unsigned int));
+		if (d == 'D' && (v & 0x80000000)) {
+			v = 0 - v;
+			f |= 8;
+		}
+		i = 0;
+		do {
+			d = (TCHAR)(v % r); v /= r;
+			if (d > 9) d += (c == 'x') ? 0x27 : 0x07;
+			str[i++] = d + '0';
+		} while (v && i < sizeof str / sizeof str[0]);
+		if (f & 8) str[i++] = '-';
+		j = i; d = (f & 1) ? '0' : ' ';
+		while (!(f & 2) && j++ < w) putc_bfd(&pb, d);
+		do {
+			putc_bfd(&pb, str[--i]);
+		} while (i);
+		while (j++ < w) putc_bfd(&pb, d);
+	}
+
+	va_end(arp);
+
+	return putc_flush(&pb);
+}
+
+#endif /* !_FS_READONLY */
+#endif /* _USE_STRFUNC */
diff --git a/Middlewares/Third_Party/FatFs/src/ff.h b/Middlewares/Third_Party/FatFs/src/ff.h
new file mode 100644
index 0000000..b14c3ce
--- /dev/null
+++ b/Middlewares/Third_Party/FatFs/src/ff.h
@@ -0,0 +1,361 @@
+/*----------------------------------------------------------------------------/
+/  FatFs - Generic FAT file system module  R0.12c                             /
+/-----------------------------------------------------------------------------/
+/
+/ Copyright (C) 2017, ChaN, all right reserved.
+/
+/ FatFs module is an open source software. Redistribution and use of FatFs in
+/ source and binary forms, with or without modification, are permitted provided
+/ that the following condition is met:
+
+/ 1. Redistributions of source code must retain the above copyright notice,
+/    this condition and the following disclaimer.
+/
+/ This software is provided by the copyright holder and contributors "AS IS"
+/ and any warranties related to this software are DISCLAIMED.
+/ The copyright owner or contributors be NOT LIABLE for any damages caused
+/ by use of this software.
+/----------------------------------------------------------------------------*/
+
+
+#ifndef _FATFS
+#define _FATFS	68300	/* Revision ID */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "integer.h"	/* Basic integer types */
+#include "ffconf.h"		/* FatFs configuration options */
+
+#if _FATFS != _FFCONF
+#error Wrong configuration file (ffconf.h).
+#endif
+
+
+
+/* Definitions of volume management */
+
+#if _MULTI_PARTITION		/* Multiple partition configuration */
+typedef struct {
+	BYTE pd;	/* Physical drive number */
+	BYTE pt;	/* Partition: 0:Auto detect, 1-4:Forced partition) */
+} PARTITION;
+extern PARTITION VolToPart[];	/* Volume - Partition resolution table */
+#endif
+
+
+
+/* Type of path name strings on FatFs API */
+
+#if _LFN_UNICODE			/* Unicode (UTF-16) string */
+#if _USE_LFN == 0
+#error _LFN_UNICODE must be 0 at non-LFN cfg.
+#endif
+#ifndef _INC_TCHAR
+typedef WCHAR TCHAR;
+#define _T(x) L ## x
+#define _TEXT(x) L ## x
+#endif
+#else						/* ANSI/OEM string */
+#ifndef _INC_TCHAR
+typedef char TCHAR;
+#define _T(x) x
+#define _TEXT(x) x
+#endif
+#endif
+
+
+
+/* Type of file size variables */
+
+#if _FS_EXFAT
+#if _USE_LFN == 0
+#error LFN must be enabled when enable exFAT
+#endif
+typedef QWORD FSIZE_t;
+#else
+typedef DWORD FSIZE_t;
+#endif
+
+
+
+/* File system object structure (FATFS) */
+
+typedef struct {
+	BYTE	fs_type;		/* File system type (0:N/A) */
+	BYTE	drv;			/* Physical drive number */
+	BYTE	n_fats;			/* Number of FATs (1 or 2) */
+	BYTE	wflag;			/* win[] flag (b0:dirty) */
+	BYTE	fsi_flag;		/* FSINFO flags (b7:disabled, b0:dirty) */
+	WORD	id;				/* File system mount ID */
+	WORD	n_rootdir;		/* Number of root directory entries (FAT12/16) */
+	WORD	csize;			/* Cluster size [sectors] */
+#if _MAX_SS != _MIN_SS
+	WORD	ssize;			/* Sector size (512, 1024, 2048 or 4096) */
+#endif
+#if _USE_LFN != 0
+	WCHAR*	lfnbuf;			/* LFN working buffer */
+#endif
+#if _FS_EXFAT
+	BYTE*	dirbuf;			/* Directory entry block scratchpad buffer */
+#endif
+#if _FS_REENTRANT
+	_SYNC_t	sobj;			/* Identifier of sync object */
+#endif
+#if !_FS_READONLY
+	DWORD	last_clst;		/* Last allocated cluster */
+	DWORD	free_clst;		/* Number of free clusters */
+#endif
+#if _FS_RPATH != 0
+	DWORD	cdir;			/* Current directory start cluster (0:root) */
+#if _FS_EXFAT
+	DWORD	cdc_scl;		/* Containing directory start cluster (invalid when cdir is 0) */
+	DWORD	cdc_size;		/* b31-b8:Size of containing directory, b7-b0: Chain status */
+	DWORD	cdc_ofs;		/* Offset in the containing directory (invalid when cdir is 0) */
+#endif
+#endif
+	DWORD	n_fatent;		/* Number of FAT entries (number of clusters + 2) */
+	DWORD	fsize;			/* Size of an FAT [sectors] */
+	DWORD	volbase;		/* Volume base sector */
+	DWORD	fatbase;		/* FAT base sector */
+	DWORD	dirbase;		/* Root directory base sector/cluster */
+	DWORD	database;		/* Data base sector */
+	DWORD	winsect;		/* Current sector appearing in the win[] */
+	BYTE	win[_MAX_SS];	/* Disk access window for Directory, FAT (and file data at tiny cfg) */
+} FATFS;
+
+
+
+/* Object ID and allocation information (_FDID) */
+
+typedef struct {
+	FATFS*	fs;			/* Pointer to the owner file system object */
+	WORD	id;			/* Owner file system mount ID */
+	BYTE	attr;		/* Object attribute */
+	BYTE	stat;		/* Object chain status (b1-0: =0:not contiguous, =2:contiguous (no data on FAT), =3:flagmented in this session, b2:sub-directory stretched) */
+	DWORD	sclust;		/* Object start cluster (0:no cluster or root directory) */
+	FSIZE_t	objsize;	/* Object size (valid when sclust != 0) */
+#if _FS_EXFAT
+	DWORD	n_cont;		/* Size of first fragment, clusters - 1 (valid when stat == 3) */
+	DWORD	n_frag;		/* Size of last fragment needs to be written (valid when not zero) */
+	DWORD	c_scl;		/* Containing directory start cluster (valid when sclust != 0) */
+	DWORD	c_size;		/* b31-b8:Size of containing directory, b7-b0: Chain status (valid when c_scl != 0) */
+	DWORD	c_ofs;		/* Offset in the containing directory (valid when sclust != 0 and non-directory object) */
+#endif
+#if _FS_LOCK != 0
+	UINT	lockid;		/* File lock ID origin from 1 (index of file semaphore table Files[]) */
+#endif
+} _FDID;
+
+
+
+/* File object structure (FIL) */
+
+typedef struct {
+	_FDID	obj;			/* Object identifier (must be the 1st member to detect invalid object pointer) */
+	BYTE	flag;			/* File status flags */
+	BYTE	err;			/* Abort flag (error code) */
+	FSIZE_t	fptr;			/* File read/write pointer (Zeroed on file open) */
+	DWORD	clust;			/* Current cluster of fpter (invalid when fptr is 0) */
+	DWORD	sect;			/* Sector number appearing in buf[] (0:invalid) */
+#if !_FS_READONLY
+	DWORD	dir_sect;		/* Sector number containing the directory entry */
+	BYTE*	dir_ptr;		/* Pointer to the directory entry in the win[] */
+#endif
+#if _USE_FASTSEEK
+	DWORD*	cltbl;			/* Pointer to the cluster link map table (nulled on open, set by application) */
+#endif
+#if !_FS_TINY
+	BYTE	buf[_MAX_SS];	/* File private data read/write window */
+#endif
+} FIL;
+
+
+
+/* Directory object structure (DIR) */
+
+typedef struct {
+	_FDID	obj;			/* Object identifier */
+	DWORD	dptr;			/* Current read/write offset */
+	DWORD	clust;			/* Current cluster */
+	DWORD	sect;			/* Current sector (0:Read operation has terminated) */
+	BYTE*	dir;			/* Pointer to the directory item in the win[] */
+	BYTE	fn[12];			/* SFN (in/out) {body[8],ext[3],status[1]} */
+#if _USE_LFN != 0
+	DWORD	blk_ofs;		/* Offset of current entry block being processed (0xFFFFFFFF:Invalid) */
+#endif
+#if _USE_FIND
+	const TCHAR* pat;		/* Pointer to the name matching pattern */
+#endif
+} DIR;
+
+
+
+/* File information structure (FILINFO) */
+
+typedef struct {
+	FSIZE_t	fsize;			/* File size */
+	WORD	fdate;			/* Modified date */
+	WORD	ftime;			/* Modified time */
+	BYTE	fattrib;		/* File attribute */
+#if _USE_LFN != 0
+	TCHAR	altname[13];			/* Alternative file name */
+	TCHAR	fname[_MAX_LFN + 1];	/* Primary file name */
+#else
+	TCHAR	fname[13];		/* File name */
+#endif
+} FILINFO;
+
+
+
+/* File function return code (FRESULT) */
+
+typedef enum {
+	FR_OK = 0,				/* (0) Succeeded */
+	FR_DISK_ERR,			/* (1) A hard error occurred in the low level disk I/O layer */
+	FR_INT_ERR,				/* (2) Assertion failed */
+	FR_NOT_READY,			/* (3) The physical drive cannot work */
+	FR_NO_FILE,				/* (4) Could not find the file */
+	FR_NO_PATH,				/* (5) Could not find the path */
+	FR_INVALID_NAME,		/* (6) The path name format is invalid */
+	FR_DENIED,				/* (7) Access denied due to prohibited access or directory full */
+	FR_EXIST,				/* (8) Access denied due to prohibited access */
+	FR_INVALID_OBJECT,		/* (9) The file/directory object is invalid */
+	FR_WRITE_PROTECTED,		/* (10) The physical drive is write protected */
+	FR_INVALID_DRIVE,		/* (11) The logical drive number is invalid */
+	FR_NOT_ENABLED,			/* (12) The volume has no work area */
+	FR_NO_FILESYSTEM,		/* (13) There is no valid FAT volume */
+	FR_MKFS_ABORTED,		/* (14) The f_mkfs() aborted due to any problem */
+	FR_TIMEOUT,				/* (15) Could not get a grant to access the volume within defined period */
+	FR_LOCKED,				/* (16) The operation is rejected according to the file sharing policy */
+	FR_NOT_ENOUGH_CORE,		/* (17) LFN working buffer could not be allocated */
+	FR_TOO_MANY_OPEN_FILES,	/* (18) Number of open files > _FS_LOCK */
+	FR_INVALID_PARAMETER	/* (19) Given parameter is invalid */
+} FRESULT;
+
+
+
+/*--------------------------------------------------------------*/
+/* FatFs module application interface                           */
+
+FRESULT f_open (FIL* fp, const TCHAR* path, BYTE mode);				/* Open or create a file */
+FRESULT f_close (FIL* fp);											/* Close an open file object */
+FRESULT f_read (FIL* fp, void* buff, UINT btr, UINT* br);			/* Read data from the file */
+FRESULT f_write (FIL* fp, const void* buff, UINT btw, UINT* bw);	/* Write data to the file */
+FRESULT f_lseek (FIL* fp, FSIZE_t ofs);								/* Move file pointer of the file object */
+FRESULT f_truncate (FIL* fp);										/* Truncate the file */
+FRESULT f_sync (FIL* fp);											/* Flush cached data of the writing file */
+FRESULT f_opendir (DIR* dp, const TCHAR* path);						/* Open a directory */
+FRESULT f_closedir (DIR* dp);										/* Close an open directory */
+FRESULT f_readdir (DIR* dp, FILINFO* fno);							/* Read a directory item */
+FRESULT f_findfirst (DIR* dp, FILINFO* fno, const TCHAR* path, const TCHAR* pattern);	/* Find first file */
+FRESULT f_findnext (DIR* dp, FILINFO* fno);							/* Find next file */
+FRESULT f_mkdir (const TCHAR* path);								/* Create a sub directory */
+FRESULT f_unlink (const TCHAR* path);								/* Delete an existing file or directory */
+FRESULT f_rename (const TCHAR* path_old, const TCHAR* path_new);	/* Rename/Move a file or directory */
+FRESULT f_stat (const TCHAR* path, FILINFO* fno);					/* Get file status */
+FRESULT f_chmod (const TCHAR* path, BYTE attr, BYTE mask);			/* Change attribute of a file/dir */
+FRESULT f_utime (const TCHAR* path, const FILINFO* fno);			/* Change timestamp of a file/dir */
+FRESULT f_chdir (const TCHAR* path);								/* Change current directory */
+FRESULT f_chdrive (const TCHAR* path);								/* Change current drive */
+FRESULT f_getcwd (TCHAR* buff, UINT len);							/* Get current directory */
+FRESULT f_getfree (const TCHAR* path, DWORD* nclst, FATFS** fatfs);	/* Get number of free clusters on the drive */
+FRESULT f_getlabel (const TCHAR* path, TCHAR* label, DWORD* vsn);	/* Get volume label */
+FRESULT f_setlabel (const TCHAR* label);							/* Set volume label */
+FRESULT f_forward (FIL* fp, UINT(*func)(const BYTE*,UINT), UINT btf, UINT* bf);	/* Forward data to the stream */
+FRESULT f_expand (FIL* fp, FSIZE_t szf, BYTE opt);					/* Allocate a contiguous block to the file */
+FRESULT f_mount (FATFS* fs, const TCHAR* path, BYTE opt);			/* Mount/Unmount a logical drive */
+FRESULT f_mkfs (const TCHAR* path, BYTE opt, DWORD au, void* work, UINT len);	/* Create a FAT volume */
+FRESULT f_fdisk (BYTE pdrv, const DWORD* szt, void* work);			/* Divide a physical drive into some partitions */
+int f_putc (TCHAR c, FIL* fp);										/* Put a character to the file */
+int f_puts (const TCHAR* str, FIL* cp);								/* Put a string to the file */
+int f_printf (FIL* fp, const TCHAR* str, ...);						/* Put a formatted string to the file */
+TCHAR* f_gets (TCHAR* buff, int len, FIL* fp);						/* Get a string from the file */
+
+#define f_eof(fp) ((int)((fp)->fptr == (fp)->obj.objsize))
+#define f_error(fp) ((fp)->err)
+#define f_tell(fp) ((fp)->fptr)
+#define f_size(fp) ((fp)->obj.objsize)
+#define f_rewind(fp) f_lseek((fp), 0)
+#define f_rewinddir(dp) f_readdir((dp), 0)
+#define f_rmdir(path) f_unlink(path)
+
+#ifndef EOF
+#define EOF (-1)
+#endif
+
+
+
+
+/*--------------------------------------------------------------*/
+/* Additional user defined functions                            */
+
+/* RTC function */
+#if !_FS_READONLY && !_FS_NORTC
+DWORD get_fattime (void);
+#endif
+
+/* Unicode support functions */
+#if _USE_LFN != 0						/* Unicode - OEM code conversion */
+WCHAR ff_convert (WCHAR chr, UINT dir);	/* OEM-Unicode bidirectional conversion */
+WCHAR ff_wtoupper (WCHAR chr);			/* Unicode upper-case conversion */
+#if _USE_LFN == 3						/* Memory functions */
+void* ff_memalloc (UINT msize);			/* Allocate memory block */
+void ff_memfree (void* mblock);			/* Free memory block */
+#endif
+#endif
+
+/* Sync functions */
+#if _FS_REENTRANT
+int ff_cre_syncobj (BYTE vol, _SYNC_t* sobj);	/* Create a sync object */
+int ff_req_grant (_SYNC_t sobj);				/* Lock sync object */
+void ff_rel_grant (_SYNC_t sobj);				/* Unlock sync object */
+int ff_del_syncobj (_SYNC_t sobj);				/* Delete a sync object */
+#endif
+
+
+
+
+/*--------------------------------------------------------------*/
+/* Flags and offset address                                     */
+
+
+/* File access mode and open method flags (3rd argument of f_open) */
+#define	FA_READ				0x01
+#define	FA_WRITE			0x02
+#define	FA_OPEN_EXISTING	0x00
+#define	FA_CREATE_NEW		0x04
+#define	FA_CREATE_ALWAYS	0x08
+#define	FA_OPEN_ALWAYS		0x10
+#define	FA_OPEN_APPEND		0x30
+
+/* Fast seek controls (2nd argument of f_lseek) */
+#define CREATE_LINKMAP	((FSIZE_t)0 - 1)
+
+/* Format options (2nd argument of f_mkfs) */
+#define FM_FAT		0x01
+#define FM_FAT32	0x02
+#define FM_EXFAT	0x04
+#define FM_ANY		0x07
+#define FM_SFD		0x08
+
+/* Filesystem type (FATFS.fs_type) */
+#define FS_FAT12	1
+#define FS_FAT16	2
+#define FS_FAT32	3
+#define FS_EXFAT	4
+
+/* File attribute bits for directory entry (FILINFO.fattrib) */
+#define	AM_RDO	0x01	/* Read only */
+#define	AM_HID	0x02	/* Hidden */
+#define	AM_SYS	0x04	/* System */
+#define AM_DIR	0x10	/* Directory */
+#define AM_ARC	0x20	/* Archive */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _FATFS */
diff --git a/Middlewares/Third_Party/FatFs/src/ff_gen_drv.c b/Middlewares/Third_Party/FatFs/src/ff_gen_drv.c
new file mode 100644
index 0000000..ccd595b
--- /dev/null
+++ b/Middlewares/Third_Party/FatFs/src/ff_gen_drv.c
@@ -0,0 +1,122 @@
+/**
+  ******************************************************************************
+  * @file    ff_gen_drv.c
+  * @author  MCD Application Team
+  * @brief   FatFs generic low level driver.
+  *****************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics. All rights reserved.
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                       opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+**/
+/* Includes ------------------------------------------------------------------*/
+#include "ff_gen_drv.h"
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+Disk_drvTypeDef disk = {{0},{0},{0},0};
+
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/**
+  * @brief  Links a compatible diskio driver/lun id and increments the number of active
+  *         linked drivers.
+  * @note   The number of linked drivers (volumes) is up to 10 due to FatFs limits.
+  * @param  drv: pointer to the disk IO Driver structure
+  * @param  path: pointer to the logical drive path
+  * @param  lun : only used for USB Key Disk to add multi-lun management
+            else the parameter must be equal to 0
+  * @retval Returns 0 in case of success, otherwise 1.
+  */
+uint8_t FATFS_LinkDriverEx(const Diskio_drvTypeDef *drv, char *path, uint8_t lun)
+{
+  uint8_t ret = 1;
+  uint8_t DiskNum = 0;
+
+  if(disk.nbr < _VOLUMES)
+  {
+    disk.is_initialized[disk.nbr] = 0;
+    disk.drv[disk.nbr] = drv;
+    disk.lun[disk.nbr] = lun;
+    DiskNum = disk.nbr++;
+    path[0] = DiskNum + '0';
+    path[1] = ':';
+    path[2] = '/';
+    path[3] = 0;
+    ret = 0;
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Links a compatible diskio driver and increments the number of active
+  *         linked drivers.
+  * @note   The number of linked drivers (volumes) is up to 10 due to FatFs limits
+  * @param  drv: pointer to the disk IO Driver structure
+  * @param  path: pointer to the logical drive path
+  * @retval Returns 0 in case of success, otherwise 1.
+  */
+uint8_t FATFS_LinkDriver(const Diskio_drvTypeDef *drv, char *path)
+{
+  return FATFS_LinkDriverEx(drv, path, 0);
+}
+
+/**
+  * @brief  Unlinks a diskio driver and decrements the number of active linked
+  *         drivers.
+  * @param  path: pointer to the logical drive path
+  * @param  lun : not used
+  * @retval Returns 0 in case of success, otherwise 1.
+  */
+uint8_t FATFS_UnLinkDriverEx(char *path, uint8_t lun)
+{
+  uint8_t DiskNum = 0;
+  uint8_t ret = 1;
+
+  if(disk.nbr >= 1)
+  {
+    DiskNum = path[0] - '0';
+    if(disk.drv[DiskNum] != 0)
+    {
+      disk.drv[DiskNum] = 0;
+      disk.lun[DiskNum] = 0;
+      disk.nbr--;
+      ret = 0;
+    }
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Unlinks a diskio driver and decrements the number of active linked
+  *         drivers.
+  * @param  path: pointer to the logical drive path
+  * @retval Returns 0 in case of success, otherwise 1.
+  */
+uint8_t FATFS_UnLinkDriver(char *path)
+{
+  return FATFS_UnLinkDriverEx(path, 0);
+}
+
+/**
+  * @brief  Gets number of linked drivers to the FatFs module.
+  * @param  None
+  * @retval Number of attached drivers.
+  */
+uint8_t FATFS_GetAttachedDriversNbr(void)
+{
+  return disk.nbr;
+}
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Middlewares/Third_Party/FatFs/src/ff_gen_drv.h b/Middlewares/Third_Party/FatFs/src/ff_gen_drv.h
new file mode 100644
index 0000000..5172e0d
--- /dev/null
+++ b/Middlewares/Third_Party/FatFs/src/ff_gen_drv.h
@@ -0,0 +1,80 @@
+/**
+  ******************************************************************************
+  * @file    ff_gen_drv.h
+  * @author  MCD Application Team
+  * @brief   Header for ff_gen_drv.c module.
+  *****************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics. All rights reserved.
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                       opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+**/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __FF_GEN_DRV_H
+#define __FF_GEN_DRV_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "diskio.h"
+#include "ff.h"
+#include "stdint.h"
+
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+  * @brief  Disk IO Driver structure definition
+  */
+typedef struct
+{
+  DSTATUS (*disk_initialize) (BYTE);                     /*!< Initialize Disk Drive                     */
+  DSTATUS (*disk_status)     (BYTE);                     /*!< Get Disk Status                           */
+  DRESULT (*disk_read)       (BYTE, BYTE*, DWORD, UINT);       /*!< Read Sector(s)                            */
+#if _USE_WRITE == 1
+  DRESULT (*disk_write)      (BYTE, const BYTE*, DWORD, UINT); /*!< Write Sector(s) when _USE_WRITE = 0       */
+#endif /* _USE_WRITE == 1 */
+#if _USE_IOCTL == 1
+  DRESULT (*disk_ioctl)      (BYTE, BYTE, void*);              /*!< I/O control operation when _USE_IOCTL = 1 */
+#endif /* _USE_IOCTL == 1 */
+
+}Diskio_drvTypeDef;
+
+/**
+  * @brief  Global Disk IO Drivers structure definition
+  */
+typedef struct
+{
+  uint8_t                 is_initialized[_VOLUMES];
+  const Diskio_drvTypeDef *drv[_VOLUMES];
+  uint8_t                 lun[_VOLUMES];
+  volatile uint8_t        nbr;
+
+}Disk_drvTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+uint8_t FATFS_LinkDriver(const Diskio_drvTypeDef *drv, char *path);
+uint8_t FATFS_UnLinkDriver(char *path);
+uint8_t FATFS_LinkDriverEx(const Diskio_drvTypeDef *drv, char *path, BYTE lun);
+uint8_t FATFS_UnLinkDriverEx(char *path, BYTE lun);
+uint8_t FATFS_GetAttachedDriversNbr(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __FF_GEN_DRV_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Middlewares/Third_Party/FatFs/src/integer.h b/Middlewares/Third_Party/FatFs/src/integer.h
new file mode 100644
index 0000000..9ce7865
--- /dev/null
+++ b/Middlewares/Third_Party/FatFs/src/integer.h
@@ -0,0 +1,38 @@
+/*-------------------------------------------*/
+/* Integer type definitions for FatFs module */
+/*-------------------------------------------*/
+
+#ifndef _FF_INTEGER
+#define _FF_INTEGER
+
+#ifdef _WIN32	/* FatFs development platform */
+
+#include <windows.h>
+#include <tchar.h>
+typedef unsigned __int64 QWORD;
+
+
+#else			/* Embedded platform */
+
+/* These types MUST be 16-bit or 32-bit */
+typedef int				INT;
+typedef unsigned int	UINT;
+
+/* This type MUST be 8-bit */
+typedef unsigned char	BYTE;
+
+/* These types MUST be 16-bit */
+typedef short			SHORT;
+typedef unsigned short	WORD;
+typedef unsigned short	WCHAR;
+
+/* These types MUST be 32-bit */
+typedef long			LONG;
+typedef unsigned long	DWORD;
+
+/* This type MUST be 64-bit (Remove this for ANSI C (C89) compatibility) */
+typedef unsigned long long QWORD;
+
+#endif
+
+#endif
diff --git a/Middlewares/Third_Party/FatFs/src/option/ccsbcs.c b/Middlewares/Third_Party/FatFs/src/option/ccsbcs.c
new file mode 100644
index 0000000..e2762dc
--- /dev/null
+++ b/Middlewares/Third_Party/FatFs/src/option/ccsbcs.c
@@ -0,0 +1,388 @@
+/*------------------------------------------------------------------------*/
+/* Unicode - Local code bidirectional converter  (C)ChaN, 2015            */
+/* (SBCS code pages)                                                      */
+/*------------------------------------------------------------------------*/
+/*  437   U.S.
+/   720   Arabic
+/   737   Greek
+/   771   KBL
+/   775   Baltic
+/   850   Latin 1
+/   852   Latin 2
+/   855   Cyrillic
+/   857   Turkish
+/   860   Portuguese
+/   861   Icelandic
+/   862   Hebrew
+/   863   Canadian French
+/   864   Arabic
+/   865   Nordic
+/   866   Russian
+/   869   Greek 2
+*/
+
+#include "../ff.h"
+
+
+#if _CODE_PAGE == 437
+#define _TBLDEF 1
+static
+const WCHAR Tbl[] = {	/*  CP437(0x80-0xFF) to Unicode conversion table */
+	0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x00E0, 0x00E5, 0x00E7, 0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x00EC, 0x00C4, 0x00C5,
+	0x00C9, 0x00E6, 0x00C6, 0x00F4, 0x00F6, 0x00F2, 0x00FB, 0x00F9, 0x00FF, 0x00D6, 0x00DC, 0x00A2, 0x00A3, 0x00A5, 0x20A7, 0x0192,
+	0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x00AA, 0x00BA, 0x00BF, 0x2310, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB,
+	0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510,
+	0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567,
+	0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580,
+	0x03B1, 0x00DF, 0x0393, 0x03C0, 0x03A3, 0x03C3, 0x00B5, 0x03C4, 0x03A6, 0x0398, 0x03A9, 0x03B4, 0x221E, 0x03C6, 0x03B5, 0x2229,
+	0x2261, 0x00B1, 0x2265, 0x2264, 0x2320, 0x2321, 0x00F7, 0x2248, 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0
+};
+
+#elif _CODE_PAGE == 720
+#define _TBLDEF 1
+static
+const WCHAR Tbl[] = {	/*  CP720(0x80-0xFF) to Unicode conversion table */
+	0x0000, 0x0000, 0x00E9, 0x00E2, 0x0000, 0x00E0, 0x0000, 0x00E7, 0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0651, 0x0652, 0x00F4, 0x00A4, 0x0640, 0x00FB, 0x00F9, 0x0621, 0x0622, 0x0623, 0x0624, 0x00A3, 0x0625, 0x0626, 0x0627,
+	0x0628, 0x0629, 0x062A, 0x062B, 0x062C, 0x062D, 0x062E, 0x062F, 0x0630, 0x0631, 0x0632, 0x0633, 0x0634, 0x0635, 0x00AB, 0x00BB,
+	0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510,
+	0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567,
+	0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580,
+	0x0636, 0x0637, 0x0638, 0x0639, 0x063A, 0x0641, 0x00B5, 0x0642, 0x0643, 0x0644, 0x0645, 0x0646, 0x0647, 0x0648, 0x0649, 0x064A,
+	0x2261, 0x064B, 0x064C, 0x064D, 0x064E, 0x064F, 0x0650, 0x2248, 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0
+};
+
+#elif _CODE_PAGE == 737
+#define _TBLDEF 1
+static
+const WCHAR Tbl[] = {	/*  CP737(0x80-0xFF) to Unicode conversion table */
+	0x0391, 0x0392, 0x0393, 0x0394, 0x0395, 0x0396, 0x0397, 0x0398, 0x0399, 0x039A, 0x039B, 0x039C, 0x039D, 0x039E, 0x039F, 0x03A0,
+	0x03A1, 0x03A3, 0x03A4, 0x03A5, 0x03A6, 0x03A7, 0x03A8, 0x03A9, 0x03B1, 0x03B2, 0x03B3, 0x03B4, 0x03B5, 0x03B6, 0x03B7, 0x03B8,
+	0x03B9, 0x03BA, 0x03BB, 0x03BC, 0x03BD, 0x03BE, 0x03BF, 0x03C0, 0x03C1, 0x03C3, 0x03C2, 0x03C4, 0x03C5, 0x03C6, 0x03C7, 0x03C8,
+	0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510,
+	0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567,
+	0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580,
+	0x03C9, 0x03AC, 0x03AD, 0x03AE, 0x03CA, 0x03AF, 0x03CC, 0x03CD, 0x03CB, 0x03CE, 0x0386, 0x0388, 0x0389, 0x038A, 0x038C, 0x038E,
+	0x038F, 0x00B1, 0x2265, 0x2264, 0x03AA, 0x03AB, 0x00F7, 0x2248, 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0
+};
+
+#elif _CODE_PAGE == 771
+#define _TBLDEF 1
+static
+const WCHAR Tbl[] = {	/*  CP771(0x80-0xFF) to Unicode conversion table */
+	0x0410, 0x0411, 0x0412, 0x0413, 0x0414, 0x0415, 0x0416, 0x0417, 0x0418, 0x0419, 0x041A, 0x041B, 0x041C, 0x041D, 0x041E, 0x041F,
+	0x0420, 0x0421, 0x0422, 0x0423, 0x0424, 0x0425, 0x0426, 0x0427, 0x0428, 0x0429, 0x042A, 0x042B, 0x042C, 0x042D, 0x042E, 0x042F,
+	0x0430, 0x0431, 0x0432, 0x0433, 0x0434, 0x0435, 0x0436, 0x0437, 0x0438, 0x0439, 0x043A, 0x043B, 0x043C, 0x043D, 0x043E, 0x043F,
+	0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x2558, 0x2510,
+	0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567,
+	0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, 0x256A, 0x2518, 0x250C, 0x2588, 0x0104, 0x0105, 0x010C, 0x010D,
+	0x0440, 0x0441, 0x0442, 0x0443, 0x0444, 0x0445, 0x0446, 0x0447, 0x0448, 0x0449, 0x044A, 0x044B, 0x044C, 0x044D, 0x044E, 0x044F,
+	0x0118, 0x0119, 0x0116, 0x0117, 0x012E, 0x012F, 0x0160, 0x0161, 0x0172, 0x0173, 0x016A, 0x016B, 0x017D, 0x017E, 0x25A0, 0x00A0
+};
+
+#elif _CODE_PAGE == 775
+#define _TBLDEF 1
+static
+const WCHAR Tbl[] = {	/*  CP775(0x80-0xFF) to Unicode conversion table */
+	0x0106, 0x00FC, 0x00E9, 0x0101, 0x00E4, 0x0123, 0x00E5, 0x0107, 0x0142, 0x0113, 0x0156, 0x0157, 0x012B, 0x0179, 0x00C4, 0x00C5,
+	0x00C9, 0x00E6, 0x00C6, 0x014D, 0x00F6, 0x0122, 0x00A2, 0x015A, 0x015B, 0x00D6, 0x00DC, 0x00F8, 0x00A3, 0x00D8, 0x00D7, 0x00A4,
+	0x0100, 0x012A, 0x00F3, 0x017B, 0x017C, 0x017A, 0x201D, 0x00A6, 0x00A9, 0x00AE, 0x00AC, 0x00BD, 0x00BC, 0x0141, 0x00AB, 0x00BB,
+	0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x0104, 0x010C, 0x0118, 0x0116, 0x2563, 0x2551, 0x2557, 0x255D, 0x012E, 0x0160, 0x2510,
+	0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x0172, 0x016A, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x017D,
+	0x0105, 0x010D, 0x0119, 0x0117, 0x012F, 0x0161, 0x0173, 0x016B, 0x017E, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580,
+	0x00D3, 0x00DF, 0x014C, 0x0143, 0x00F5, 0x00D5, 0x00B5, 0x0144, 0x0136, 0x0137, 0x013B, 0x013C, 0x0146, 0x0112, 0x0145, 0x2019,
+	0x00AD, 0x00B1, 0x201C, 0x00BE, 0x00B6, 0x00A7, 0x00F7, 0x201E, 0x00B0, 0x2219, 0x00B7, 0x00B9, 0x00B3, 0x00B2, 0x25A0, 0x00A0
+};
+
+#elif _CODE_PAGE == 850
+#define _TBLDEF 1
+static
+const WCHAR Tbl[] = {	/*  CP850(0x80-0xFF) to Unicode conversion table */
+	0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x00E0, 0x00E5, 0x00E7, 0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x00EC, 0x00C4, 0x00C5,
+	0x00C9, 0x00E6, 0x00C6, 0x00F4, 0x00F6, 0x00F2, 0x00FB, 0x00F9, 0x00FF, 0x00D6, 0x00DC, 0x00F8, 0x00A3, 0x00D8, 0x00D7, 0x0192,
+	0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x00AA, 0x00BA, 0x00BF, 0x00AE, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB,
+	0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x00C1, 0x00C2, 0x00C0, 0x00A9, 0x2563, 0x2551, 0x2557, 0x255D, 0x00A2, 0x00A5, 0x2510,
+	0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x00E3, 0x00C3, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x00A4,
+	0x00F0, 0x00D0, 0x00CA, 0x00CB, 0x00C8, 0x0131, 0x00CD, 0x00CE, 0x00CF, 0x2518, 0x250C, 0x2588, 0x2584, 0x00A6, 0x00CC, 0x2580,
+	0x00D3, 0x00DF, 0x00D4, 0x00D2, 0x00F5, 0x00D5, 0x00B5, 0x00FE, 0x00DE, 0x00DA, 0x00DB, 0x00D9, 0x00FD, 0x00DD, 0x00AF, 0x00B4,
+	0x00AD, 0x00B1, 0x2017, 0x00BE, 0x00B6, 0x00A7, 0x00F7, 0x00B8, 0x00B0, 0x00A8, 0x00B7, 0x00B9, 0x00B3, 0x00B2, 0x25A0, 0x00A0
+};
+
+#elif _CODE_PAGE == 852
+#define _TBLDEF 1
+static
+const WCHAR Tbl[] = {	/*  CP852(0x80-0xFF) to Unicode conversion table */
+	0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x016F, 0x0107, 0x00E7, 0x0142, 0x00EB, 0x0150, 0x0151, 0x00EE, 0x0179, 0x00C4, 0x0106,
+	0x00C9, 0x0139, 0x013A, 0x00F4, 0x00F6, 0x013D, 0x013E, 0x015A, 0x015B, 0x00D6, 0x00DC, 0x0164, 0x0165, 0x0141, 0x00D7, 0x010D,
+	0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x0104, 0x0105, 0x017D, 0x017E, 0x0118, 0x0119, 0x00AC, 0x017A, 0x010C, 0x015F, 0x00AB, 0x00BB,
+	0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x00C1, 0x00C2, 0x011A, 0x015E, 0x2563, 0x2551, 0x2557, 0x255D, 0x017B, 0x017C, 0x2510,
+	0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x0102, 0x0103, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x00A4,
+	0x0111, 0x0110, 0x010E, 0x00CB, 0x010F, 0x0147, 0x00CD, 0x00CE, 0x011B, 0x2518, 0x250C, 0x2588, 0x2584, 0x0162, 0x016E, 0x2580,
+	0x00D3, 0x00DF, 0x00D4, 0x0143, 0x0144, 0x0148, 0x0160, 0x0161, 0x0154, 0x00DA, 0x0155, 0x0170, 0x00FD, 0x00DD, 0x0163, 0x00B4,
+	0x00AD, 0x02DD, 0x02DB, 0x02C7, 0x02D8, 0x00A7, 0x00F7, 0x00B8, 0x00B0, 0x00A8, 0x02D9, 0x0171, 0x0158, 0x0159, 0x25A0, 0x00A0
+};
+
+#elif _CODE_PAGE == 855
+#define _TBLDEF 1
+static
+const WCHAR Tbl[] = {	/*  CP855(0x80-0xFF) to Unicode conversion table */
+	0x0452, 0x0402, 0x0453, 0x0403, 0x0451, 0x0401, 0x0454, 0x0404, 0x0455, 0x0405, 0x0456, 0x0406, 0x0457, 0x0407, 0x0458, 0x0408,
+	0x0459, 0x0409, 0x045A, 0x040A, 0x045B, 0x040B, 0x045C, 0x040C, 0x045E, 0x040E, 0x045F, 0x040F, 0x044E, 0x042E, 0x044A, 0x042A,
+	0x0430, 0x0410, 0x0431, 0x0411, 0x0446, 0x0426, 0x0434, 0x0414, 0x0435, 0x0415, 0x0444, 0x0424, 0x0433, 0x0413, 0x00AB, 0x00BB,
+	0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x0445, 0x0425, 0x0438, 0x0418, 0x2563, 0x2551, 0x2557, 0x255D, 0x0439, 0x0419, 0x2510,
+	0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x043A, 0x041A, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x00A4,
+	0x043B, 0x041B, 0x043C, 0x041C, 0x043D, 0x041D, 0x043E, 0x041E, 0x043F, 0x2518, 0x250C, 0x2588, 0x2584, 0x041F, 0x044F, 0x2580,
+	0x042F, 0x0440, 0x0420, 0x0441, 0x0421, 0x0442, 0x0422, 0x0443, 0x0423, 0x0436, 0x0416, 0x0432, 0x0412, 0x044C, 0x042C, 0x2116,
+	0x00AD, 0x044B, 0x042B, 0x0437, 0x0417, 0x0448, 0x0428, 0x044D, 0x042D, 0x0449, 0x0429, 0x0447, 0x0427, 0x00A7, 0x25A0, 0x00A0
+};
+
+#elif _CODE_PAGE == 857
+#define _TBLDEF 1
+static
+const WCHAR Tbl[] = {	/*  CP857(0x80-0xFF) to Unicode conversion table */
+	0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x00E0, 0x00E5, 0x00E7, 0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x0131, 0x00C4, 0x00C5,
+	0x00C9, 0x00E6, 0x00C6, 0x00F4, 0x00F6, 0x00F2, 0x00FB, 0x00F9, 0x0130, 0x00D6, 0x00DC, 0x00F8, 0x00A3, 0x00D8, 0x015E, 0x015F,
+	0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x011E, 0x011F, 0x00BF, 0x00AE, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB,
+	0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x00C1, 0x00C2, 0x00C0, 0x00A9, 0x2563, 0x2551, 0x2557, 0x255D, 0x00A2, 0x00A5, 0x2510,
+	0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x00E3, 0x00C3, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x00A4,
+	0x00BA, 0x00AA, 0x00CA, 0x00CB, 0x00C8, 0x0000, 0x00CD, 0x00CE, 0x00CF, 0x2518, 0x250C, 0x2588, 0x2584, 0x00A6, 0x00CC, 0x2580,
+	0x00D3, 0x00DF, 0x00D4, 0x00D2, 0x00F5, 0x00D5, 0x00B5, 0x0000, 0x00D7, 0x00DA, 0x00DB, 0x00D9, 0x00EC, 0x00FF, 0x00AF, 0x00B4,
+	0x00AD, 0x00B1, 0x0000, 0x00BE, 0x00B6, 0x00A7, 0x00F7, 0x00B8, 0x00B0, 0x00A8, 0x00B7, 0x00B9, 0x00B3, 0x00B2, 0x25A0, 0x00A0
+};
+
+#elif _CODE_PAGE == 860
+#define _TBLDEF 1
+static
+const WCHAR Tbl[] = {	/*  CP860(0x80-0xFF) to Unicode conversion table */
+	0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E3, 0x00E0, 0x00C1, 0x00E7, 0x00EA, 0x00CA, 0x00E8, 0x00CD, 0x00D4, 0x00EC, 0x00C3, 0x00C2,
+	0x00C9, 0x00C0, 0x00C8, 0x00F4, 0x00F5, 0x00F2, 0x00DA, 0x00F9, 0x00CC, 0x00D5, 0x00DC, 0x00A2, 0x00A3, 0x00D9, 0x20A7, 0x00D3,
+	0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x00AA, 0x00BA, 0x00BF, 0x00D2, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB,
+	0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x2558, 0x2510,
+	0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567,
+	0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580,
+	0x03B1, 0x00DF, 0x0393, 0x03C0, 0x03A3, 0x03C3, 0x00B5, 0x03C4, 0x03A6, 0x0398, 0x03A9, 0x03B4, 0x221E, 0x03C6, 0x03B5, 0x2229,
+	0x2261, 0x00B1, 0x2265, 0x2264, 0x2320, 0x2321, 0x00F7, 0x2248, 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0
+};
+
+#elif _CODE_PAGE == 861
+#define _TBLDEF 1
+static
+const WCHAR Tbl[] = {	/*  CP861(0x80-0xFF) to Unicode conversion table */
+	0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x00E0, 0x00E6, 0x00E7, 0x00EA, 0x00EB, 0x00E8, 0x00D0, 0x00F0, 0x00DE, 0x00C4, 0x00C5,
+	0x00C9, 0x00E6, 0x00C6, 0x00F4, 0x00F6, 0x00FE, 0x00FB, 0x00DD, 0x00FD, 0x00D6, 0x00DC, 0x00F8, 0x00A3, 0x00D8, 0x20A7, 0x0192,
+	0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00C1, 0x00CD, 0x00D3, 0x00DA, 0x00BF, 0x2310, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB,
+	0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510,
+	0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567,
+	0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580,
+	0x03B1, 0x00DF, 0x0393, 0x03C0, 0x03A3, 0x03C3, 0x00B5, 0x03C4, 0x03A6, 0x0398, 0x03A9, 0x03B4, 0x221E, 0x03C6, 0x03B5, 0x2229,
+	0x2261, 0x00B1, 0x2265, 0x2264, 0x2320, 0x2321, 0x00F7, 0x2248, 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0
+};
+
+#elif _CODE_PAGE == 862
+#define _TBLDEF 1
+static
+const WCHAR Tbl[] = {	/*  CP862(0x80-0xFF) to Unicode conversion table */
+	0x05D0, 0x05D1, 0x05D2, 0x05D3, 0x05D4, 0x05D5, 0x05D6, 0x05D7, 0x05D8, 0x05D9, 0x05DA, 0x05DB, 0x05DC, 0x05DD, 0x05DE, 0x05DF,
+	0x05E0, 0x05E1, 0x05E2, 0x05E3, 0x05E4, 0x05E5, 0x05E6, 0x05E7, 0x05E8, 0x05E9, 0x05EA, 0x00A2, 0x00A3, 0x00A5, 0x20A7, 0x0192,
+	0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x00AA, 0x00BA, 0x00BF, 0x2310, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB,
+	0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510,
+	0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567,
+	0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580,
+	0x03B1, 0x00DF, 0x0393, 0x03C0, 0x03A3, 0x03C3, 0x00B5, 0x03C4, 0x03A6, 0x0398, 0x03A9, 0x03B4, 0x221E, 0x03C6, 0x03B5, 0x2229,
+	0x2261, 0x00B1, 0x2265, 0x2264, 0x2320, 0x2321, 0x00F7, 0x2248, 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0
+};
+
+#elif _CODE_PAGE == 863
+#define _TBLDEF 1
+static
+const WCHAR Tbl[] = {	/*  CP863(0x80-0xFF) to Unicode conversion table */
+	0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00C2, 0x00E0, 0x00B6, 0x00E7, 0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x00EC, 0x2017, 0x00C0,
+	0x00C9, 0x00C8, 0x00CA, 0x00F4, 0x00CB, 0x00CF, 0x00FB, 0x00F9, 0x00A4, 0x00D4, 0x00DC, 0x00A2, 0x00A3, 0x00D9, 0x00DB, 0x0192,
+	0x00A6, 0x00B4, 0x00F3, 0x00FA, 0x00A8, 0x00BB, 0x00B3, 0x00AF, 0x00CE, 0x3210, 0x00AC, 0x00BD, 0x00BC, 0x00BE, 0x00AB, 0x00BB,
+	0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510,
+	0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567,
+	0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580,
+	0x03B1, 0x00DF, 0x0393, 0x03C0, 0x03A3, 0x03C3, 0x00B5, 0x03C4, 0x03A6, 0x0398, 0x03A9, 0x03B4, 0x221E, 0x03C6, 0x03B5, 0x2219,
+	0x2261, 0x00B1, 0x2265, 0x2264, 0x2320, 0x2321, 0x00F7, 0x2248, 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0
+};
+
+#elif _CODE_PAGE == 864
+#define _TBLDEF 1
+static
+const WCHAR Tbl[] = {	/*  CP864(0x80-0xFF) to Unicode conversion table */
+	0x00B0, 0x00B7, 0x2219, 0x221A, 0x2592, 0x2500, 0x2502, 0x253C, 0x2524, 0x252C, 0x251C, 0x2534, 0x2510, 0x250C, 0x2514, 0x2518,
+	0x03B2, 0x221E, 0x03C6, 0x00B1, 0x00BD, 0x00BC, 0x2248, 0x00AB, 0x00BB, 0xFEF7, 0xFEF8, 0x0000, 0x0000, 0xFEFB, 0xFEFC, 0x0000,
+	0x00A0, 0x00AD, 0xFE82, 0x00A3, 0x00A4, 0xFE84, 0x0000, 0x20AC, 0xFE8E, 0xFE8F, 0xFE95, 0xFE99, 0x060C, 0xFE9D, 0xFEA1, 0xFEA5,
+	0x0660, 0x0661, 0x0662, 0x0663, 0x0664, 0x0665, 0x0666, 0x0667, 0x0668, 0x0669, 0xFED1, 0x061B, 0xFEB1, 0xFEB5, 0xFEB9, 0x061F,
+	0x00A2, 0xFE80, 0xFE81, 0xFE83, 0xFE85, 0xFECA, 0xFE8B, 0xFE8D, 0xFE91, 0xFE93, 0xFE97, 0xFE9B, 0xFE9F, 0xFEA3, 0xFEA7, 0xFEA9,
+	0xFEAB, 0xFEAD, 0xFEAF, 0xFEB3, 0xFEB7, 0xFEBB, 0xFEBF, 0xFEC1, 0xFEC5, 0xFECB, 0xFECF, 0x00A6, 0x00AC, 0x00F7, 0x00D7, 0xFEC9,
+	0x0640, 0xFED3, 0xFED7, 0xFEDB, 0xFEDF, 0xFEE3, 0xFEE7, 0xFEEB, 0xFEED, 0xFEEF, 0xFEF3, 0xFEBD, 0xFECC, 0xFECE, 0xFECD, 0xFEE1,
+	0xFE7D, 0x0651, 0xFEE5, 0xFEE9, 0xFEEC, 0xFEF0, 0xFEF2, 0xFED0, 0xFED5, 0xFEF5, 0xFEF6, 0xFEDD, 0xFED9, 0xFEF1, 0x25A0, 0x0000
+};
+
+#elif _CODE_PAGE == 865
+#define _TBLDEF 1
+static
+const WCHAR Tbl[] = {	/*  CP865(0x80-0xFF) to Unicode conversion table */
+	0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x00E0, 0x00E5, 0x00E7, 0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x00EC, 0x00C4, 0x00C5,
+	0x00C5, 0x00E6, 0x00C6, 0x00F4, 0x00F6, 0x00F2, 0x00FB, 0x00F9, 0x00FF, 0x00D6, 0x00DC, 0x00F8, 0x00A3, 0x00D8, 0x20A7, 0x0192,
+	0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x00AA, 0x00BA, 0x00BF, 0x2310, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00A4,
+	0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x2558, 0x2510,
+	0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567,
+	0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580,
+	0x03B1, 0x00DF, 0x0393, 0x03C0, 0x03A3, 0x03C3, 0x00B5, 0x03C4, 0x03A6, 0x0398, 0x03A9, 0x03B4, 0x221E, 0x03C6, 0x03B5, 0x2229,
+	0x2261, 0x00B1, 0x2265, 0x2264, 0x2320, 0x2321, 0x00F7, 0x2248, 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0
+};
+
+#elif _CODE_PAGE == 866
+#define _TBLDEF 1
+static
+const WCHAR Tbl[] = {	/*  CP866(0x80-0xFF) to Unicode conversion table */
+	0x0410, 0x0411, 0x0412, 0x0413, 0x0414, 0x0415, 0x0416, 0x0417, 0x0418, 0x0419, 0x041A, 0x041B, 0x041C, 0x041D, 0x041E, 0x041F,
+	0x0420, 0x0421, 0x0422, 0x0423, 0x0424, 0x0425, 0x0426, 0x0427, 0x0428, 0x0429, 0x042A, 0x042B, 0x042C, 0x042D, 0x042E, 0x042F,
+	0x0430, 0x0431, 0x0432, 0x0433, 0x0434, 0x0435, 0x0436, 0x0437, 0x0438, 0x0439, 0x043A, 0x043B, 0x043C, 0x043D, 0x043E, 0x043F,
+	0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510,
+	0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567,
+	0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580,
+	0x0440, 0x0441, 0x0442, 0x0443, 0x0444, 0x0445, 0x0446, 0x0447, 0x0448, 0x0449, 0x044A, 0x044B, 0x044C, 0x044D, 0x044E, 0x044F,
+	0x0401, 0x0451, 0x0404, 0x0454, 0x0407, 0x0457, 0x040E, 0x045E, 0x00B0, 0x2219, 0x00B7, 0x221A, 0x2116, 0x00A4, 0x25A0, 0x00A0
+};
+
+#elif _CODE_PAGE == 869
+#define _TBLDEF 1
+static
+const WCHAR Tbl[] = {	/*  CP869(0x80-0xFF) to Unicode conversion table */
+	0x00B7, 0x00B7, 0x00B7, 0x00B7, 0x00B7, 0x00B7, 0x0386, 0x00B7, 0x00B7, 0x00AC, 0x00A6, 0x2018, 0x2019, 0x0388, 0x2015, 0x0389,
+	0x038A, 0x03AA, 0x038C, 0x00B7, 0x00B7, 0x038E, 0x03AB, 0x00A9, 0x038F, 0x00B2, 0x00B3, 0x03AC, 0x00A3, 0x03AD, 0x03AE, 0x03AF,
+	0x03CA, 0x0390, 0x03CC, 0x03CD, 0x0391, 0x0392, 0x0393, 0x0394, 0x0395, 0x0396, 0x0397, 0x00BD, 0x0398, 0x0399, 0x00AB, 0x00BB,
+	0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x039A, 0x039B, 0x039C, 0x039D, 0x2563, 0x2551, 0x2557, 0x255D, 0x039E, 0x039F, 0x2510,
+	0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x0A30, 0x03A1, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x03A3,
+	0x03A4, 0x03A5, 0x03A6, 0x03A7, 0x03A8, 0x03A9, 0x03B1, 0x03B2, 0x03B3, 0x2518, 0x250C, 0x2588, 0x2584, 0x03B4, 0x03B5, 0x2580,
+	0x03B6, 0x03B7, 0x03B8, 0x03B9, 0x03BA, 0x03BB, 0x03BC, 0x03BD, 0x03BE, 0x03BF, 0x03C0, 0x03C1, 0x03C3, 0x03C2, 0x03C4, 0x0384,
+	0x00AD, 0x00B1, 0x03C5, 0x03C6, 0x03C7, 0x00A7, 0x03C8, 0x0385, 0x00B0, 0x00A8, 0x03C9, 0x03CB, 0x03B0, 0x03CE, 0x25A0, 0x00A0
+};
+
+#endif
+
+
+#if !_TBLDEF || !_USE_LFN
+#error This file is not needed at current configuration. Remove from the project.
+#endif
+
+
+
+
+WCHAR ff_convert (	/* Converted character, Returns zero on error */
+	WCHAR	chr,	/* Character code to be converted */
+	UINT	dir		/* 0: Unicode to OEM code, 1: OEM code to Unicode */
+)
+{
+	WCHAR c;
+
+
+	if (chr < 0x80) {	/* ASCII */
+		c = chr;
+
+	} else {
+		if (dir) {		/* OEM code to Unicode */
+			c = (chr >= 0x100) ? 0 : Tbl[chr - 0x80];
+
+		} else {		/* Unicode to OEM code */
+			for (c = 0; c < 0x80; c++) {
+				if (chr == Tbl[c]) break;
+			}
+			c = (c + 0x80) & 0xFF;
+		}
+	}
+
+	return c;
+}
+
+
+
+WCHAR ff_wtoupper (	/* Returns upper converted character */
+	WCHAR chr		/* Unicode character to be upper converted (BMP only) */
+)
+{
+	/* Compressed upper conversion table */
+	static const WCHAR cvt1[] = {	/* U+0000 - U+0FFF */
+		/* Basic Latin */
+		0x0061,0x031A,
+		/* Latin-1 Supplement */
+		0x00E0,0x0317,  0x00F8,0x0307,  0x00FF,0x0001,0x0178,
+		/* Latin Extended-A */
+		0x0100,0x0130,  0x0132,0x0106,  0x0139,0x0110,  0x014A,0x012E,  0x0179,0x0106,
+		/* Latin Extended-B */
+		0x0180,0x004D,0x0243,0x0181,0x0182,0x0182,0x0184,0x0184,0x0186,0x0187,0x0187,0x0189,0x018A,0x018B,0x018B,0x018D,0x018E,0x018F,0x0190,0x0191,0x0191,0x0193,0x0194,0x01F6,0x0196,0x0197,0x0198,0x0198,0x023D,0x019B,0x019C,0x019D,0x0220,0x019F,0x01A0,0x01A0,0x01A2,0x01A2,0x01A4,0x01A4,0x01A6,0x01A7,0x01A7,0x01A9,0x01AA,0x01AB,0x01AC,0x01AC,0x01AE,0x01AF,0x01AF,0x01B1,0x01B2,0x01B3,0x01B3,0x01B5,0x01B5,0x01B7,0x01B8,0x01B8,0x01BA,0x01BB,0x01BC,0x01BC,0x01BE,0x01F7,0x01C0,0x01C1,0x01C2,0x01C3,0x01C4,0x01C5,0x01C4,0x01C7,0x01C8,0x01C7,0x01CA,0x01CB,0x01CA,
+		0x01CD,0x0110,  0x01DD,0x0001,0x018E,  0x01DE,0x0112,  0x01F3,0x0003,0x01F1,0x01F4,0x01F4,  0x01F8,0x0128,
+		0x0222,0x0112,  0x023A,0x0009,0x2C65,0x023B,0x023B,0x023D,0x2C66,0x023F,0x0240,0x0241,0x0241,  0x0246,0x010A,
+		/* IPA Extensions */
+		0x0253,0x0040,0x0181,0x0186,0x0255,0x0189,0x018A,0x0258,0x018F,0x025A,0x0190,0x025C,0x025D,0x025E,0x025F,0x0193,0x0261,0x0262,0x0194,0x0264,0x0265,0x0266,0x0267,0x0197,0x0196,0x026A,0x2C62,0x026C,0x026D,0x026E,0x019C,0x0270,0x0271,0x019D,0x0273,0x0274,0x019F,0x0276,0x0277,0x0278,0x0279,0x027A,0x027B,0x027C,0x2C64,0x027E,0x027F,0x01A6,0x0281,0x0282,0x01A9,0x0284,0x0285,0x0286,0x0287,0x01AE,0x0244,0x01B1,0x01B2,0x0245,0x028D,0x028E,0x028F,0x0290,0x0291,0x01B7,
+		/* Greek, Coptic */
+		0x037B,0x0003,0x03FD,0x03FE,0x03FF,  0x03AC,0x0004,0x0386,0x0388,0x0389,0x038A,  0x03B1,0x0311,
+		0x03C2,0x0002,0x03A3,0x03A3,  0x03C4,0x0308,  0x03CC,0x0003,0x038C,0x038E,0x038F,  0x03D8,0x0118,
+		0x03F2,0x000A,0x03F9,0x03F3,0x03F4,0x03F5,0x03F6,0x03F7,0x03F7,0x03F9,0x03FA,0x03FA,
+		/* Cyrillic */
+		0x0430,0x0320,  0x0450,0x0710,  0x0460,0x0122,  0x048A,0x0136,  0x04C1,0x010E,  0x04CF,0x0001,0x04C0,  0x04D0,0x0144,
+		/* Armenian */
+		0x0561,0x0426,
+
+		0x0000
+	};
+	static const WCHAR cvt2[] = {	/* U+1000 - U+FFFF */
+		/* Phonetic Extensions */
+		0x1D7D,0x0001,0x2C63,
+		/* Latin Extended Additional */
+		0x1E00,0x0196,  0x1EA0,0x015A,
+		/* Greek Extended */
+		0x1F00,0x0608,  0x1F10,0x0606,  0x1F20,0x0608,  0x1F30,0x0608,  0x1F40,0x0606,
+		0x1F51,0x0007,0x1F59,0x1F52,0x1F5B,0x1F54,0x1F5D,0x1F56,0x1F5F,  0x1F60,0x0608,
+		0x1F70,0x000E,0x1FBA,0x1FBB,0x1FC8,0x1FC9,0x1FCA,0x1FCB,0x1FDA,0x1FDB,0x1FF8,0x1FF9,0x1FEA,0x1FEB,0x1FFA,0x1FFB,
+		0x1F80,0x0608,  0x1F90,0x0608,  0x1FA0,0x0608,  0x1FB0,0x0004,0x1FB8,0x1FB9,0x1FB2,0x1FBC,
+		0x1FCC,0x0001,0x1FC3,  0x1FD0,0x0602,  0x1FE0,0x0602,  0x1FE5,0x0001,0x1FEC,  0x1FF2,0x0001,0x1FFC,
+		/* Letterlike Symbols */
+		0x214E,0x0001,0x2132,
+		/* Number forms */
+		0x2170,0x0210,  0x2184,0x0001,0x2183,
+		/* Enclosed Alphanumerics */
+		0x24D0,0x051A,  0x2C30,0x042F,
+		/* Latin Extended-C */
+		0x2C60,0x0102,  0x2C67,0x0106, 0x2C75,0x0102,
+		/* Coptic */
+		0x2C80,0x0164,
+		/* Georgian Supplement */
+		0x2D00,0x0826,
+		/* Full-width */
+		0xFF41,0x031A,
+
+		0x0000
+	};
+	const WCHAR *p;
+	WCHAR bc, nc, cmd;
+
+
+	p = chr < 0x1000 ? cvt1 : cvt2;
+	for (;;) {
+		bc = *p++;								/* Get block base */
+		if (!bc || chr < bc) break;
+		nc = *p++; cmd = nc >> 8; nc &= 0xFF;	/* Get processing command and block size */
+		if (chr < bc + nc) {	/* In the block? */
+			switch (cmd) {
+			case 0:	chr = p[chr - bc]; break;		/* Table conversion */
+			case 1:	chr -= (chr - bc) & 1; break;	/* Case pairs */
+			case 2: chr -= 16; break;				/* Shift -16 */
+			case 3:	chr -= 32; break;				/* Shift -32 */
+			case 4:	chr -= 48; break;				/* Shift -48 */
+			case 5:	chr -= 26; break;				/* Shift -26 */
+			case 6:	chr += 8; break;				/* Shift +8 */
+			case 7: chr -= 80; break;				/* Shift -80 */
+			case 8:	chr -= 0x1C60; break;			/* Shift -0x1C60 */
+			}
+			break;
+		}
+		if (!cmd) p += nc;
+	}
+
+	return chr;
+}
+
diff --git a/Middlewares/Third_Party/FatFs/src/option/syscall.c b/Middlewares/Third_Party/FatFs/src/option/syscall.c
new file mode 100644
index 0000000..cd6370d
--- /dev/null
+++ b/Middlewares/Third_Party/FatFs/src/option/syscall.c
@@ -0,0 +1,177 @@
+/*------------------------------------------------------------------------*/
+/* Sample code of OS dependent controls for FatFs                         */
+/* (C)ChaN, 2014                                                          */
+/*   Portions COPYRIGHT 2017 STMicroelectronics                           */
+/*   Portions Copyright (C) 2014, ChaN, all right reserved                */
+/*------------------------------------------------------------------------*/
+
+/**
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics. All rights reserved.
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                       opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+**/
+
+
+
+#include "../ff.h"
+
+
+#if _FS_REENTRANT
+/*------------------------------------------------------------------------*/
+/* Create a Synchronization Object                                        */
+/*------------------------------------------------------------------------*/
+/* This function is called in f_mount() function to create a new
+/  synchronization object, such as semaphore and mutex. When a 0 is returned,
+/  the f_mount() function fails with FR_INT_ERR.
+*/
+
+int ff_cre_syncobj (	/* 1:Function succeeded, 0:Could not create the sync object */
+	BYTE vol,			/* Corresponding volume (logical drive number) */
+	_SYNC_t *sobj		/* Pointer to return the created sync object */
+)
+{
+
+    int ret;
+#if _USE_MUTEX
+
+#if (osCMSIS < 0x20000U)
+    osMutexDef(MTX);
+    *sobj = osMutexCreate(osMutex(MTX));
+#else
+    *sobj = osMutexNew(NULL);
+#endif
+
+#else
+
+#if (osCMSIS < 0x20000U)
+    osSemaphoreDef(SEM);
+    *sobj = osSemaphoreCreate(osSemaphore(SEM), 1);
+#else
+    *sobj = osSemaphoreNew(1, 1, NULL);
+#endif
+
+#endif
+    ret = (*sobj != NULL);
+
+    return ret;
+}
+
+
+
+/*------------------------------------------------------------------------*/
+/* Delete a Synchronization Object                                        */
+/*------------------------------------------------------------------------*/
+/* This function is called in f_mount() function to delete a synchronization
+/  object that created with ff_cre_syncobj() function. When a 0 is returned,
+/  the f_mount() function fails with FR_INT_ERR.
+*/
+
+int ff_del_syncobj (	/* 1:Function succeeded, 0:Could not delete due to any error */
+	_SYNC_t sobj		/* Sync object tied to the logical drive to be deleted */
+)
+{
+#if _USE_MUTEX
+    osMutexDelete (sobj);
+#else
+    osSemaphoreDelete (sobj);
+#endif
+    return 1;
+}
+
+
+
+/*------------------------------------------------------------------------*/
+/* Request Grant to Access the Volume                                     */
+/*------------------------------------------------------------------------*/
+/* This function is called on entering file functions to lock the volume.
+/  When a 0 is returned, the file function fails with FR_TIMEOUT.
+*/
+
+int ff_req_grant (	/* 1:Got a grant to access the volume, 0:Could not get a grant */
+	_SYNC_t sobj	/* Sync object to wait */
+)
+{
+  int ret = 0;
+#if (osCMSIS < 0x20000U)
+
+#if _USE_MUTEX
+  if(osMutexWait(sobj, _FS_TIMEOUT) == osOK)
+#else
+  if(osSemaphoreWait(sobj, _FS_TIMEOUT) == osOK)
+#endif
+
+#else
+
+#if _USE_MUTEX
+   if(osMutexAcquire(sobj, _FS_TIMEOUT) == osOK)
+#else
+   if(osSemaphoreAcquire(sobj, _FS_TIMEOUT) == osOK)
+#endif
+
+#endif
+  {
+    ret = 1;
+  }
+
+  return ret;
+}
+
+
+
+/*------------------------------------------------------------------------*/
+/* Release Grant to Access the Volume                                     */
+/*------------------------------------------------------------------------*/
+/* This function is called on leaving file functions to unlock the volume.
+*/
+
+void ff_rel_grant (
+	_SYNC_t sobj	/* Sync object to be signaled */
+)
+{
+#if _USE_MUTEX
+  osMutexRelease(sobj);
+#else
+  osSemaphoreRelease(sobj);
+#endif
+}
+
+#endif
+
+
+
+
+#if _USE_LFN == 3	/* LFN with a working buffer on the heap */
+/*------------------------------------------------------------------------*/
+/* Allocate a memory block                                                */
+/*------------------------------------------------------------------------*/
+/* If a NULL is returned, the file function fails with FR_NOT_ENOUGH_CORE.
+*/
+
+void* ff_memalloc (	/* Returns pointer to the allocated memory block */
+	UINT msize		/* Number of bytes to allocate */
+)
+{
+	return ff_malloc(msize);	/* Allocate a new memory block with POSIX API */
+}
+
+
+/*------------------------------------------------------------------------*/
+/* Free a memory block                                                    */
+/*------------------------------------------------------------------------*/
+
+void ff_memfree (
+	void* mblock	/* Pointer to the memory block to free */
+)
+{
+	ff_free(mblock);	/* Discard the memory block with POSIX API */
+}
+
+#endif
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c b/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c
new file mode 100644
index 0000000..89c3633
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c
@@ -0,0 +1,1727 @@
+/* ----------------------------------------------------------------------
+ * $Date:        5. February 2013
+ * $Revision:    V1.02
+ *
+ * Project:      CMSIS-RTOS API
+ * Title:        cmsis_os.c
+ *
+ * Version 0.02
+ *    Initial Proposal Phase
+ * Version 0.03
+ *    osKernelStart added, optional feature: main started as thread
+ *    osSemaphores have standard behavior
+ *    osTimerCreate does not start the timer, added osTimerStart
+ *    osThreadPass is renamed to osThreadYield
+ * Version 1.01
+ *    Support for C++ interface
+ *     - const attribute removed from the osXxxxDef_t typedef's
+ *     - const attribute added to the osXxxxDef macros
+ *    Added: osTimerDelete, osMutexDelete, osSemaphoreDelete
+ *    Added: osKernelInitialize
+ * Version 1.02
+ *    Control functions for short timeouts in microsecond resolution:
+ *    Added: osKernelSysTick, osKernelSysTickFrequency, osKernelSysTickMicroSec
+ *    Removed: osSignalGet 
+ *    
+ *  
+ *----------------------------------------------------------------------------
+ *
+ * Portions Copyright � 2016 STMicroelectronics International N.V. All rights reserved.
+ * Portions Copyright (c) 2013 ARM LIMITED
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  - Neither the name of ARM  nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without
+ *    specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *---------------------------------------------------------------------------*/
+
+#include <string.h>
+#include "cmsis_os.h"
+
+/*
+ * ARM Compiler 4/5
+ */
+#if   defined ( __CC_ARM )
+
+  #define __ASM            __asm                                      
+  #define __INLINE         __inline                                     
+  #define __STATIC_INLINE  static __inline
+
+  #include "cmsis_armcc.h"
+
+/*
+ * GNU Compiler
+ */
+#elif defined ( __GNUC__ )
+
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+  #define __STATIC_INLINE  static inline
+
+  #include "cmsis_gcc.h"
+
+
+/*
+ * IAR Compiler
+ */
+#elif defined ( __ICCARM__ )
+
+  #ifndef   __ASM
+    #define __ASM                     __asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                  inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE           static inline
+  #endif
+
+  #include <cmsis_iar.h>
+#endif
+
+extern void xPortSysTickHandler(void);
+
+/* Convert from CMSIS type osPriority to FreeRTOS priority number */
+static unsigned portBASE_TYPE makeFreeRtosPriority (osPriority priority)
+{
+  unsigned portBASE_TYPE fpriority = tskIDLE_PRIORITY;
+  
+  if (priority != osPriorityError) {
+    fpriority += (priority - osPriorityIdle);
+  }
+  
+  return fpriority;
+}
+
+#if (INCLUDE_uxTaskPriorityGet == 1)
+/* Convert from FreeRTOS priority number to CMSIS type osPriority */
+static osPriority makeCmsisPriority (unsigned portBASE_TYPE fpriority)
+{
+  osPriority priority = osPriorityError;
+  
+  if ((fpriority - tskIDLE_PRIORITY) <= (osPriorityRealtime - osPriorityIdle)) {
+    priority = (osPriority)((int)osPriorityIdle + (int)(fpriority - tskIDLE_PRIORITY));
+  }
+  
+  return priority;
+}
+#endif
+
+
+/* Determine whether we are in thread mode or handler mode. */
+static int inHandlerMode (void)
+{
+  return __get_IPSR() != 0;
+}
+
+/*********************** Kernel Control Functions *****************************/
+/**
+* @brief  Initialize the RTOS Kernel for creating objects.
+* @retval status code that indicates the execution status of the function.
+* @note   MUST REMAIN UNCHANGED: \b osKernelInitialize shall be consistent in every CMSIS-RTOS.
+*/
+osStatus osKernelInitialize (void);
+
+/**
+* @brief  Start the RTOS Kernel with executing the specified thread.
+* @param  thread_def    thread definition referenced with \ref osThread.
+* @param  argument      pointer that is passed to the thread function as start argument.
+* @retval status code that indicates the execution status of the function
+* @note   MUST REMAIN UNCHANGED: \b osKernelStart shall be consistent in every CMSIS-RTOS.
+*/
+osStatus osKernelStart (void)
+{
+  vTaskStartScheduler();
+  
+  return osOK;
+}
+
+/**
+* @brief  Check if the RTOS kernel is already started
+* @param  None
+* @retval (0) RTOS is not started
+*         (1) RTOS is started
+*         (-1) if this feature is disabled in FreeRTOSConfig.h 
+* @note  MUST REMAIN UNCHANGED: \b osKernelRunning shall be consistent in every CMSIS-RTOS.
+*/
+int32_t osKernelRunning(void)
+{
+#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
+  if (xTaskGetSchedulerState() == taskSCHEDULER_NOT_STARTED)
+    return 0;
+  else
+    return 1;
+#else
+	return (-1);
+#endif	
+}
+
+#if (defined (osFeature_SysTick)  &&  (osFeature_SysTick != 0))     // System Timer available
+/**
+* @brief  Get the value of the Kernel SysTick timer
+* @param  None
+* @retval None
+* @note   MUST REMAIN UNCHANGED: \b osKernelSysTick shall be consistent in every CMSIS-RTOS.
+*/
+uint32_t osKernelSysTick(void)
+{
+  if (inHandlerMode()) {
+    return xTaskGetTickCountFromISR();
+  }
+  else {
+    return xTaskGetTickCount();
+  }
+}
+#endif    // System Timer available
+/*********************** Thread Management *****************************/
+/**
+* @brief  Create a thread and add it to Active Threads and set it to state READY.
+* @param  thread_def    thread definition referenced with \ref osThread.
+* @param  argument      pointer that is passed to the thread function as start argument.
+* @retval thread ID for reference by other functions or NULL in case of error.
+* @note   MUST REMAIN UNCHANGED: \b osThreadCreate shall be consistent in every CMSIS-RTOS.
+*/
+osThreadId osThreadCreate (const osThreadDef_t *thread_def, void *argument)
+{
+  TaskHandle_t handle;
+  
+#if( configSUPPORT_STATIC_ALLOCATION == 1 ) &&  ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+  if((thread_def->buffer != NULL) && (thread_def->controlblock != NULL)) {
+    handle = xTaskCreateStatic((TaskFunction_t)thread_def->pthread,(const portCHAR *)thread_def->name,
+              thread_def->stacksize, argument, makeFreeRtosPriority(thread_def->tpriority),
+              thread_def->buffer, thread_def->controlblock);
+  }
+  else {
+    if (xTaskCreate((TaskFunction_t)thread_def->pthread,(const portCHAR *)thread_def->name,
+              thread_def->stacksize, argument, makeFreeRtosPriority(thread_def->tpriority),
+              &handle) != pdPASS)  {
+      return NULL;
+    } 
+  }
+#elif( configSUPPORT_STATIC_ALLOCATION == 1 )
+
+    handle = xTaskCreateStatic((TaskFunction_t)thread_def->pthread,(const portCHAR *)thread_def->name,
+              thread_def->stacksize, argument, makeFreeRtosPriority(thread_def->tpriority),
+              thread_def->buffer, thread_def->controlblock);
+#else
+  if (xTaskCreate((TaskFunction_t)thread_def->pthread,(const portCHAR *)thread_def->name,
+                   thread_def->stacksize, argument, makeFreeRtosPriority(thread_def->tpriority),
+                   &handle) != pdPASS)  {
+    return NULL;
+  }     
+#endif
+  
+  return handle;
+}
+
+/**
+* @brief  Return the thread ID of the current running thread.
+* @retval thread ID for reference by other functions or NULL in case of error.
+* @note   MUST REMAIN UNCHANGED: \b osThreadGetId shall be consistent in every CMSIS-RTOS.
+*/
+osThreadId osThreadGetId (void)
+{
+#if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) )
+  return xTaskGetCurrentTaskHandle();
+#else
+	return NULL;
+#endif
+}
+
+/**
+* @brief  Terminate execution of a thread and remove it from Active Threads.
+* @param   thread_id   thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
+* @retval  status code that indicates the execution status of the function.
+* @note   MUST REMAIN UNCHANGED: \b osThreadTerminate shall be consistent in every CMSIS-RTOS.
+*/
+osStatus osThreadTerminate (osThreadId thread_id)
+{
+#if (INCLUDE_vTaskDelete == 1)
+  vTaskDelete(thread_id);
+  return osOK;
+#else
+  return osErrorOS;
+#endif
+}
+
+/**
+* @brief  Pass control to next thread that is in state \b READY.
+* @retval status code that indicates the execution status of the function.
+* @note   MUST REMAIN UNCHANGED: \b osThreadYield shall be consistent in every CMSIS-RTOS.
+*/
+osStatus osThreadYield (void)
+{
+  taskYIELD();
+  
+  return osOK;
+}
+
+/**
+* @brief   Change priority of an active thread.
+* @param   thread_id     thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
+* @param   priority      new priority value for the thread function.
+* @retval  status code that indicates the execution status of the function.
+* @note   MUST REMAIN UNCHANGED: \b osThreadSetPriority shall be consistent in every CMSIS-RTOS.
+*/
+osStatus osThreadSetPriority (osThreadId thread_id, osPriority priority)
+{
+#if (INCLUDE_vTaskPrioritySet == 1)
+  vTaskPrioritySet(thread_id, makeFreeRtosPriority(priority));
+  return osOK;
+#else
+  return osErrorOS;
+#endif
+}
+
+/**
+* @brief   Get current priority of an active thread.
+* @param   thread_id     thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
+* @retval  current priority value of the thread function.
+* @note   MUST REMAIN UNCHANGED: \b osThreadGetPriority shall be consistent in every CMSIS-RTOS.
+*/
+osPriority osThreadGetPriority (osThreadId thread_id)
+{
+#if (INCLUDE_uxTaskPriorityGet == 1)
+  if (inHandlerMode())
+  {
+    return makeCmsisPriority(uxTaskPriorityGetFromISR(thread_id));  
+  }
+  else
+  {  
+    return makeCmsisPriority(uxTaskPriorityGet(thread_id));
+  }
+#else
+  return osPriorityError;
+#endif
+}
+
+/*********************** Generic Wait Functions *******************************/
+/**
+* @brief   Wait for Timeout (Time Delay)
+* @param   millisec      time delay value
+* @retval  status code that indicates the execution status of the function.
+*/
+osStatus osDelay (uint32_t millisec)
+{
+#if INCLUDE_vTaskDelay
+  TickType_t ticks = millisec / portTICK_PERIOD_MS;
+  
+  vTaskDelay(ticks ? ticks : 1);          /* Minimum delay = 1 tick */
+  
+  return osOK;
+#else
+  (void) millisec;
+  
+  return osErrorResource;
+#endif
+}
+
+#if (defined (osFeature_Wait)  &&  (osFeature_Wait != 0)) /* Generic Wait available */
+/**
+* @brief  Wait for Signal, Message, Mail, or Timeout
+* @param   millisec  timeout value or 0 in case of no time-out
+* @retval  event that contains signal, message, or mail information or error code.
+* @note   MUST REMAIN UNCHANGED: \b osWait shall be consistent in every CMSIS-RTOS.
+*/
+osEvent osWait (uint32_t millisec);
+
+#endif  /* Generic Wait available */
+
+/***********************  Timer Management Functions ***************************/
+/**
+* @brief  Create a timer.
+* @param  timer_def     timer object referenced with \ref osTimer.
+* @param  type          osTimerOnce for one-shot or osTimerPeriodic for periodic behavior.
+* @param  argument      argument to the timer call back function.
+* @retval  timer ID for reference by other functions or NULL in case of error.
+* @note   MUST REMAIN UNCHANGED: \b osTimerCreate shall be consistent in every CMSIS-RTOS.
+*/
+osTimerId osTimerCreate (const osTimerDef_t *timer_def, os_timer_type type, void *argument)
+{
+#if (configUSE_TIMERS == 1)
+
+#if( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) 
+  if(timer_def->controlblock != NULL) {
+    return xTimerCreateStatic((const char *)"",
+                      1, // period should be filled when starting the Timer using osTimerStart
+                      (type == osTimerPeriodic) ? pdTRUE : pdFALSE,
+                      (void *) argument,
+                      (TimerCallbackFunction_t)timer_def->ptimer,
+                      (StaticTimer_t *)timer_def->controlblock);
+  }
+  else {
+    return xTimerCreate((const char *)"",
+                      1, // period should be filled when starting the Timer using osTimerStart
+                      (type == osTimerPeriodic) ? pdTRUE : pdFALSE,
+                      (void *) argument,
+                      (TimerCallbackFunction_t)timer_def->ptimer);
+ }
+#elif( configSUPPORT_STATIC_ALLOCATION == 1 )
+  return xTimerCreateStatic((const char *)"",
+                      1, // period should be filled when starting the Timer using osTimerStart
+                      (type == osTimerPeriodic) ? pdTRUE : pdFALSE,
+                      (void *) argument,
+                      (TimerCallbackFunction_t)timer_def->ptimer,
+                      (StaticTimer_t *)timer_def->controlblock);  
+#else
+  return xTimerCreate((const char *)"",
+                      1, // period should be filled when starting the Timer using osTimerStart
+                      (type == osTimerPeriodic) ? pdTRUE : pdFALSE,
+                      (void *) argument,
+                      (TimerCallbackFunction_t)timer_def->ptimer);
+#endif
+
+#else 
+	return NULL;
+#endif
+}
+
+/**
+* @brief  Start or restart a timer.
+* @param  timer_id      timer ID obtained by \ref osTimerCreate.
+* @param  millisec      time delay value of the timer.
+* @retval  status code that indicates the execution status of the function
+* @note   MUST REMAIN UNCHANGED: \b osTimerStart shall be consistent in every CMSIS-RTOS.
+*/
+osStatus osTimerStart (osTimerId timer_id, uint32_t millisec)
+{
+  osStatus result = osOK;
+#if (configUSE_TIMERS == 1)  
+  portBASE_TYPE taskWoken = pdFALSE;
+  TickType_t ticks = millisec / portTICK_PERIOD_MS;
+
+  if (ticks == 0)
+    ticks = 1;
+    
+  if (inHandlerMode()) 
+  {
+    if (xTimerChangePeriodFromISR(timer_id, ticks, &taskWoken) != pdPASS)
+    {
+      result = osErrorOS;
+    }
+    else
+    {
+      portEND_SWITCHING_ISR(taskWoken);     
+    }
+  }
+  else 
+  {
+    if (xTimerChangePeriod(timer_id, ticks, 0) != pdPASS)
+      result = osErrorOS;
+  }
+
+#else 
+  result = osErrorOS;
+#endif
+  return result;
+}
+
+/**
+* @brief  Stop a timer.
+* @param  timer_id      timer ID obtained by \ref osTimerCreate
+* @retval  status code that indicates the execution status of the function.
+* @note   MUST REMAIN UNCHANGED: \b osTimerStop shall be consistent in every CMSIS-RTOS.
+*/
+osStatus osTimerStop (osTimerId timer_id)
+{
+  osStatus result = osOK;
+#if (configUSE_TIMERS == 1)  
+  portBASE_TYPE taskWoken = pdFALSE;
+
+  if (inHandlerMode()) {
+    if (xTimerStopFromISR(timer_id, &taskWoken) != pdPASS) {
+      return osErrorOS;
+    }
+    portEND_SWITCHING_ISR(taskWoken);
+  }
+  else {
+    if (xTimerStop(timer_id, 0) != pdPASS) {
+      result = osErrorOS;
+    }
+  }
+#else 
+  result = osErrorOS;
+#endif 
+  return result;
+}
+
+/**
+* @brief  Delete a timer.
+* @param  timer_id      timer ID obtained by \ref osTimerCreate
+* @retval  status code that indicates the execution status of the function.
+* @note   MUST REMAIN UNCHANGED: \b osTimerDelete shall be consistent in every CMSIS-RTOS.
+*/
+osStatus osTimerDelete (osTimerId timer_id)
+{
+osStatus result = osOK;
+
+#if (configUSE_TIMERS == 1)
+
+   if (inHandlerMode()) {
+     return osErrorISR;
+  }
+  else { 
+    if ((xTimerDelete(timer_id, osWaitForever )) != pdPASS) {
+      result = osErrorOS;
+    }
+  } 
+    
+#else 
+  result = osErrorOS;
+#endif 
+ 
+  return result;
+}
+
+/***************************  Signal Management ********************************/
+/**
+* @brief  Set the specified Signal Flags of an active thread.
+* @param  thread_id     thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
+* @param  signals       specifies the signal flags of the thread that should be set.
+* @retval previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters.
+* @note   MUST REMAIN UNCHANGED: \b osSignalSet shall be consistent in every CMSIS-RTOS.
+*/
+int32_t osSignalSet (osThreadId thread_id, int32_t signal)
+{
+#if( configUSE_TASK_NOTIFICATIONS == 1 )	
+  BaseType_t xHigherPriorityTaskWoken = pdFALSE;
+  uint32_t ulPreviousNotificationValue = 0;
+  
+  if (inHandlerMode())
+  {
+    if(xTaskGenericNotifyFromISR( thread_id , (uint32_t)signal, eSetBits, &ulPreviousNotificationValue, &xHigherPriorityTaskWoken ) != pdPASS )
+      return 0x80000000;
+    
+    portYIELD_FROM_ISR( xHigherPriorityTaskWoken );
+  }  
+  else if(xTaskGenericNotify( thread_id , (uint32_t)signal, eSetBits, &ulPreviousNotificationValue) != pdPASS )
+    return 0x80000000;
+  
+  return ulPreviousNotificationValue;
+#else
+  (void) thread_id;
+  (void) signal;
+
+  return 0x80000000; /* Task Notification not supported */ 	
+#endif
+}
+
+/**
+* @brief  Clear the specified Signal Flags of an active thread.
+* @param  thread_id  thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
+* @param  signals    specifies the signal flags of the thread that shall be cleared.
+* @retval  previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters.
+* @note   MUST REMAIN UNCHANGED: \b osSignalClear shall be consistent in every CMSIS-RTOS.
+*/
+int32_t osSignalClear (osThreadId thread_id, int32_t signal);
+
+/**
+* @brief  Wait for one or more Signal Flags to become signaled for the current \b RUNNING thread.
+* @param  signals   wait until all specified signal flags set or 0 for any single signal flag.
+* @param  millisec  timeout value or 0 in case of no time-out.
+* @retval  event flag information or error code.
+* @note   MUST REMAIN UNCHANGED: \b osSignalWait shall be consistent in every CMSIS-RTOS.
+*/
+osEvent osSignalWait (int32_t signals, uint32_t millisec)
+{
+  osEvent ret;
+
+#if( configUSE_TASK_NOTIFICATIONS == 1 )
+	
+  TickType_t ticks;
+
+  ret.value.signals = 0;  
+  ticks = 0;
+  if (millisec == osWaitForever) {
+    ticks = portMAX_DELAY;
+  }
+  else if (millisec != 0) {
+    ticks = millisec / portTICK_PERIOD_MS;
+    if (ticks == 0) {
+      ticks = 1;
+    }
+  }  
+  
+  if (inHandlerMode())
+  {
+    ret.status = osErrorISR;  /*Not allowed in ISR*/
+  }
+  else
+  {
+    if(xTaskNotifyWait( 0,(uint32_t) signals, (uint32_t *)&ret.value.signals, ticks) != pdTRUE)
+    {
+      if(ticks == 0)  ret.status = osOK;
+      else  ret.status = osEventTimeout;
+    }
+    else if(ret.value.signals < 0)
+    {
+      ret.status =  osErrorValue;     
+    }
+    else  ret.status =  osEventSignal;
+  }
+#else
+  (void) signals;
+  (void) millisec;
+	
+  ret.status =  osErrorOS;	/* Task Notification not supported */
+#endif
+  
+  return ret;
+}
+
+/****************************  Mutex Management ********************************/
+/**
+* @brief  Create and Initialize a Mutex object
+* @param  mutex_def     mutex definition referenced with \ref osMutex.
+* @retval  mutex ID for reference by other functions or NULL in case of error.
+* @note   MUST REMAIN UNCHANGED: \b osMutexCreate shall be consistent in every CMSIS-RTOS.
+*/
+osMutexId osMutexCreate (const osMutexDef_t *mutex_def)
+{
+#if ( configUSE_MUTEXES == 1)
+
+#if( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+
+  if (mutex_def->controlblock != NULL) {
+    return xSemaphoreCreateMutexStatic( mutex_def->controlblock );
+     }
+  else {
+    return xSemaphoreCreateMutex(); 
+  }
+#elif ( configSUPPORT_STATIC_ALLOCATION == 1 )
+  return xSemaphoreCreateMutexStatic( mutex_def->controlblock );
+#else  
+    return xSemaphoreCreateMutex(); 
+#endif
+#else
+  return NULL;
+#endif
+}
+
+/**
+* @brief Wait until a Mutex becomes available
+* @param mutex_id      mutex ID obtained by \ref osMutexCreate.
+* @param millisec      timeout value or 0 in case of no time-out.
+* @retval  status code that indicates the execution status of the function.
+* @note   MUST REMAIN UNCHANGED: \b osMutexWait shall be consistent in every CMSIS-RTOS.
+*/
+osStatus osMutexWait (osMutexId mutex_id, uint32_t millisec)
+{
+  TickType_t ticks;
+  portBASE_TYPE taskWoken = pdFALSE;  
+  
+  
+  if (mutex_id == NULL) {
+    return osErrorParameter;
+  }
+  
+  ticks = 0;
+  if (millisec == osWaitForever) {
+    ticks = portMAX_DELAY;
+  }
+  else if (millisec != 0) {
+    ticks = millisec / portTICK_PERIOD_MS;
+    if (ticks == 0) {
+      ticks = 1;
+    }
+  }
+  
+  if (inHandlerMode()) {
+    if (xSemaphoreTakeFromISR(mutex_id, &taskWoken) != pdTRUE) {
+      return osErrorOS;
+    }
+	portEND_SWITCHING_ISR(taskWoken);
+  } 
+  else if (xSemaphoreTake(mutex_id, ticks) != pdTRUE) {
+    return osErrorOS;
+  }
+  
+  return osOK;
+}
+
+/**
+* @brief Release a Mutex that was obtained by \ref osMutexWait
+* @param mutex_id      mutex ID obtained by \ref osMutexCreate.
+* @retval  status code that indicates the execution status of the function.
+* @note   MUST REMAIN UNCHANGED: \b osMutexRelease shall be consistent in every CMSIS-RTOS.
+*/
+osStatus osMutexRelease (osMutexId mutex_id)
+{
+  osStatus result = osOK;
+  portBASE_TYPE taskWoken = pdFALSE;
+  
+  if (inHandlerMode()) {
+    if (xSemaphoreGiveFromISR(mutex_id, &taskWoken) != pdTRUE) {
+      return osErrorOS;
+    }
+    portEND_SWITCHING_ISR(taskWoken);
+  }
+  else if (xSemaphoreGive(mutex_id) != pdTRUE) 
+  {
+    result = osErrorOS;
+  }
+  return result;
+}
+
+/**
+* @brief Delete a Mutex
+* @param mutex_id  mutex ID obtained by \ref osMutexCreate.
+* @retval  status code that indicates the execution status of the function.
+* @note   MUST REMAIN UNCHANGED: \b osMutexDelete shall be consistent in every CMSIS-RTOS.
+*/
+osStatus osMutexDelete (osMutexId mutex_id)
+{
+  if (inHandlerMode()) {
+    return osErrorISR;
+  }
+
+  vQueueDelete(mutex_id);
+
+  return osOK;
+}
+
+/********************  Semaphore Management Functions **************************/
+
+#if (defined (osFeature_Semaphore)  &&  (osFeature_Semaphore != 0))
+
+/**
+* @brief Create and Initialize a Semaphore object used for managing resources
+* @param semaphore_def semaphore definition referenced with \ref osSemaphore.
+* @param count         number of available resources.
+* @retval  semaphore ID for reference by other functions or NULL in case of error.
+* @note   MUST REMAIN UNCHANGED: \b osSemaphoreCreate shall be consistent in every CMSIS-RTOS.
+*/
+osSemaphoreId osSemaphoreCreate (const osSemaphoreDef_t *semaphore_def, int32_t count)
+{ 
+#if( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+
+  osSemaphoreId sema;
+  
+  if (semaphore_def->controlblock != NULL){
+    if (count == 1) {
+      return xSemaphoreCreateBinaryStatic( semaphore_def->controlblock );
+    }
+    else {
+#if (configUSE_COUNTING_SEMAPHORES == 1 )
+      return xSemaphoreCreateCountingStatic( count, count, semaphore_def->controlblock );
+#else
+      return NULL;
+#endif
+    }
+  }
+  else {
+    if (count == 1) {
+      vSemaphoreCreateBinary(sema);
+      return sema;
+    }
+    else {
+#if (configUSE_COUNTING_SEMAPHORES == 1 )	
+      return xSemaphoreCreateCounting(count, count);
+#else
+      return NULL;
+#endif    
+    }
+  }
+#elif ( configSUPPORT_STATIC_ALLOCATION == 1 ) // configSUPPORT_DYNAMIC_ALLOCATION == 0
+  if(count == 1) {
+    return xSemaphoreCreateBinaryStatic( semaphore_def->controlblock );
+  }
+  else
+  {
+#if (configUSE_COUNTING_SEMAPHORES == 1 )
+      return xSemaphoreCreateCountingStatic( count, count, semaphore_def->controlblock );
+#else
+      return NULL;
+#endif    
+  }
+#else  // configSUPPORT_STATIC_ALLOCATION == 0  && configSUPPORT_DYNAMIC_ALLOCATION == 1
+  osSemaphoreId sema;
+ 
+  if (count == 1) {
+    vSemaphoreCreateBinary(sema);
+    return sema;
+  }
+  else {
+#if (configUSE_COUNTING_SEMAPHORES == 1 )	
+    return xSemaphoreCreateCounting(count, count);
+#else
+    return NULL;
+#endif
+  }
+#endif
+}
+
+/**
+* @brief Wait until a Semaphore token becomes available
+* @param  semaphore_id  semaphore object referenced with \ref osSemaphore.
+* @param  millisec      timeout value or 0 in case of no time-out.
+* @retval  number of available tokens, or -1 in case of incorrect parameters.
+* @note   MUST REMAIN UNCHANGED: \b osSemaphoreWait shall be consistent in every CMSIS-RTOS.
+*/
+int32_t osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec)
+{
+  TickType_t ticks;
+  portBASE_TYPE taskWoken = pdFALSE;  
+  
+  
+  if (semaphore_id == NULL) {
+    return osErrorParameter;
+  }
+  
+  ticks = 0;
+  if (millisec == osWaitForever) {
+    ticks = portMAX_DELAY;
+  }
+  else if (millisec != 0) {
+    ticks = millisec / portTICK_PERIOD_MS;
+    if (ticks == 0) {
+      ticks = 1;
+    }
+  }
+  
+  if (inHandlerMode()) {
+    if (xSemaphoreTakeFromISR(semaphore_id, &taskWoken) != pdTRUE) {
+      return osErrorOS;
+    }
+	portEND_SWITCHING_ISR(taskWoken);
+  }  
+  else if (xSemaphoreTake(semaphore_id, ticks) != pdTRUE) {
+    return osErrorOS;
+  }
+  
+  return osOK;
+}
+
+/**
+* @brief Release a Semaphore token
+* @param  semaphore_id  semaphore object referenced with \ref osSemaphore.
+* @retval  status code that indicates the execution status of the function.
+* @note   MUST REMAIN UNCHANGED: \b osSemaphoreRelease shall be consistent in every CMSIS-RTOS.
+*/
+osStatus osSemaphoreRelease (osSemaphoreId semaphore_id)
+{
+  osStatus result = osOK;
+  portBASE_TYPE taskWoken = pdFALSE;
+  
+  
+  if (inHandlerMode()) {
+    if (xSemaphoreGiveFromISR(semaphore_id, &taskWoken) != pdTRUE) {
+      return osErrorOS;
+    }
+    portEND_SWITCHING_ISR(taskWoken);
+  }
+  else {
+    if (xSemaphoreGive(semaphore_id) != pdTRUE) {
+      result = osErrorOS;
+    }
+  }
+  
+  return result;
+}
+
+/**
+* @brief Delete a Semaphore
+* @param  semaphore_id  semaphore object referenced with \ref osSemaphore.
+* @retval  status code that indicates the execution status of the function.
+* @note   MUST REMAIN UNCHANGED: \b osSemaphoreDelete shall be consistent in every CMSIS-RTOS.
+*/
+osStatus osSemaphoreDelete (osSemaphoreId semaphore_id)
+{
+  if (inHandlerMode()) {
+    return osErrorISR;
+  }
+
+  vSemaphoreDelete(semaphore_id);
+
+  return osOK; 
+}
+
+#endif    /* Use Semaphores */
+
+/*******************   Memory Pool Management Functions  ***********************/
+
+#if (defined (osFeature_Pool)  &&  (osFeature_Pool != 0)) 
+
+//TODO
+//This is a primitive and inefficient wrapper around the existing FreeRTOS memory management.
+//A better implementation will have to modify heap_x.c!
+
+
+typedef struct os_pool_cb {
+  void *pool;
+  uint8_t *markers;
+  uint32_t pool_sz;
+  uint32_t item_sz;
+  uint32_t currentIndex;
+} os_pool_cb_t;
+
+
+/**
+* @brief Create and Initialize a memory pool
+* @param  pool_def      memory pool definition referenced with \ref osPool.
+* @retval  memory pool ID for reference by other functions or NULL in case of error.
+* @note   MUST REMAIN UNCHANGED: \b osPoolCreate shall be consistent in every CMSIS-RTOS.
+*/
+osPoolId osPoolCreate (const osPoolDef_t *pool_def)
+{
+#if (configSUPPORT_DYNAMIC_ALLOCATION == 1)
+  osPoolId thePool;
+  int itemSize = 4 * ((pool_def->item_sz + 3) / 4);
+  uint32_t i;
+  
+  /* First have to allocate memory for the pool control block. */
+ thePool = pvPortMalloc(sizeof(os_pool_cb_t));
+
+  
+  if (thePool) {
+    thePool->pool_sz = pool_def->pool_sz;
+    thePool->item_sz = itemSize;
+    thePool->currentIndex = 0;
+    
+    /* Memory for markers */
+    thePool->markers = pvPortMalloc(pool_def->pool_sz);
+   
+    if (thePool->markers) {
+      /* Now allocate the pool itself. */
+     thePool->pool = pvPortMalloc(pool_def->pool_sz * itemSize);
+      
+      if (thePool->pool) {
+        for (i = 0; i < pool_def->pool_sz; i++) {
+          thePool->markers[i] = 0;
+        }
+      }
+      else {
+        vPortFree(thePool->markers);
+        vPortFree(thePool);
+        thePool = NULL;
+      }
+    }
+    else {
+      vPortFree(thePool);
+      thePool = NULL;
+    }
+  }
+
+  return thePool;
+ 
+#else
+  return NULL;
+#endif
+}
+
+/**
+* @brief Allocate a memory block from a memory pool
+* @param pool_id       memory pool ID obtain referenced with \ref osPoolCreate.
+* @retval  address of the allocated memory block or NULL in case of no memory available.
+* @note   MUST REMAIN UNCHANGED: \b osPoolAlloc shall be consistent in every CMSIS-RTOS.
+*/
+void *osPoolAlloc (osPoolId pool_id)
+{
+  int dummy = 0;
+  void *p = NULL;
+  uint32_t i;
+  uint32_t index;
+  
+  if (inHandlerMode()) {
+    dummy = portSET_INTERRUPT_MASK_FROM_ISR();
+  }
+  else {
+    vPortEnterCritical();
+  }
+  
+  for (i = 0; i < pool_id->pool_sz; i++) {
+    index = (pool_id->currentIndex + i) % pool_id->pool_sz;
+    
+    if (pool_id->markers[index] == 0) {
+      pool_id->markers[index] = 1;
+      p = (void *)((uint32_t)(pool_id->pool) + (index * pool_id->item_sz));
+      pool_id->currentIndex = index;
+      break;
+    }
+  }
+  
+  if (inHandlerMode()) {
+    portCLEAR_INTERRUPT_MASK_FROM_ISR(dummy);
+  }
+  else {
+    vPortExitCritical();
+  }
+  
+  return p;
+}
+
+/**
+* @brief Allocate a memory block from a memory pool and set memory block to zero
+* @param  pool_id       memory pool ID obtain referenced with \ref osPoolCreate.
+* @retval  address of the allocated memory block or NULL in case of no memory available.
+* @note   MUST REMAIN UNCHANGED: \b osPoolCAlloc shall be consistent in every CMSIS-RTOS.
+*/
+void *osPoolCAlloc (osPoolId pool_id)
+{
+  void *p = osPoolAlloc(pool_id);
+  
+  if (p != NULL)
+  {
+    memset(p, 0, sizeof(pool_id->pool_sz));
+  }
+  
+  return p;
+}
+
+/**
+* @brief Return an allocated memory block back to a specific memory pool
+* @param  pool_id       memory pool ID obtain referenced with \ref osPoolCreate.
+* @param  block         address of the allocated memory block that is returned to the memory pool.
+* @retval  status code that indicates the execution status of the function.
+* @note   MUST REMAIN UNCHANGED: \b osPoolFree shall be consistent in every CMSIS-RTOS.
+*/
+osStatus osPoolFree (osPoolId pool_id, void *block)
+{
+  uint32_t index;
+  
+  if (pool_id == NULL) {
+    return osErrorParameter;
+  }
+  
+  if (block == NULL) {
+    return osErrorParameter;
+  }
+  
+  if (block < pool_id->pool) {
+    return osErrorParameter;
+  }
+  
+  index = (uint32_t)block - (uint32_t)(pool_id->pool);
+  if (index % pool_id->item_sz) {
+    return osErrorParameter;
+  }
+  index = index / pool_id->item_sz;
+  if (index >= pool_id->pool_sz) {
+    return osErrorParameter;
+  }
+  
+  pool_id->markers[index] = 0;
+  
+  return osOK;
+}
+
+
+#endif   /* Use Memory Pool Management */
+
+/*******************   Message Queue Management Functions  *********************/
+
+#if (defined (osFeature_MessageQ)  &&  (osFeature_MessageQ != 0)) /* Use Message Queues */
+
+/**
+* @brief Create and Initialize a Message Queue
+* @param queue_def     queue definition referenced with \ref osMessageQ.
+* @param  thread_id     thread ID (obtained by \ref osThreadCreate or \ref osThreadGetId) or NULL.
+* @retval  message queue ID for reference by other functions or NULL in case of error.
+* @note   MUST REMAIN UNCHANGED: \b osMessageCreate shall be consistent in every CMSIS-RTOS.
+*/
+osMessageQId osMessageCreate (const osMessageQDef_t *queue_def, osThreadId thread_id)
+{
+  (void) thread_id;
+  
+#if( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+
+  if ((queue_def->buffer != NULL) && (queue_def->controlblock != NULL)) {
+    return xQueueCreateStatic(queue_def->queue_sz, queue_def->item_sz, queue_def->buffer, queue_def->controlblock);
+  }
+  else {
+    return xQueueCreate(queue_def->queue_sz, queue_def->item_sz);
+  }
+#elif ( configSUPPORT_STATIC_ALLOCATION == 1 )
+  return xQueueCreateStatic(queue_def->queue_sz, queue_def->item_sz, queue_def->buffer, queue_def->controlblock);
+#else  
+  return xQueueCreate(queue_def->queue_sz, queue_def->item_sz);
+#endif
+}
+
+/**
+* @brief Put a Message to a Queue.
+* @param  queue_id  message queue ID obtained with \ref osMessageCreate.
+* @param  info      message information.
+* @param  millisec  timeout value or 0 in case of no time-out.
+* @retval status code that indicates the execution status of the function.
+* @note   MUST REMAIN UNCHANGED: \b osMessagePut shall be consistent in every CMSIS-RTOS.
+*/
+osStatus osMessagePut (osMessageQId queue_id, uint32_t info, uint32_t millisec)
+{
+  portBASE_TYPE taskWoken = pdFALSE;
+  TickType_t ticks;
+  
+  ticks = millisec / portTICK_PERIOD_MS;
+  if (ticks == 0) {
+    ticks = 1;
+  }
+  
+  if (inHandlerMode()) {
+    if (xQueueSendFromISR(queue_id, &info, &taskWoken) != pdTRUE) {
+      return osErrorOS;
+    }
+    portEND_SWITCHING_ISR(taskWoken);
+  }
+  else {
+    if (xQueueSend(queue_id, &info, ticks) != pdTRUE) {
+      return osErrorOS;
+    }
+  }
+  
+  return osOK;
+}
+
+/**
+* @brief Get a Message or Wait for a Message from a Queue.
+* @param  queue_id  message queue ID obtained with \ref osMessageCreate.
+* @param  millisec  timeout value or 0 in case of no time-out.
+* @retval event information that includes status code.
+* @note   MUST REMAIN UNCHANGED: \b osMessageGet shall be consistent in every CMSIS-RTOS.
+*/
+osEvent osMessageGet (osMessageQId queue_id, uint32_t millisec)
+{
+  portBASE_TYPE taskWoken;
+  TickType_t ticks;
+  osEvent event;
+  
+  event.def.message_id = queue_id;
+  event.value.v = 0;
+  
+  if (queue_id == NULL) {
+    event.status = osErrorParameter;
+    return event;
+  }
+  
+  taskWoken = pdFALSE;
+  
+  ticks = 0;
+  if (millisec == osWaitForever) {
+    ticks = portMAX_DELAY;
+  }
+  else if (millisec != 0) {
+    ticks = millisec / portTICK_PERIOD_MS;
+    if (ticks == 0) {
+      ticks = 1;
+    }
+  }
+  
+  if (inHandlerMode()) {
+    if (xQueueReceiveFromISR(queue_id, &event.value.v, &taskWoken) == pdTRUE) {
+      /* We have mail */
+      event.status = osEventMessage;
+    }
+    else {
+      event.status = osOK;
+    }
+    portEND_SWITCHING_ISR(taskWoken);
+  }
+  else {
+    if (xQueueReceive(queue_id, &event.value.v, ticks) == pdTRUE) {
+      /* We have mail */
+      event.status = osEventMessage;
+    }
+    else {
+      event.status = (ticks == 0) ? osOK : osEventTimeout;
+    }
+  }
+  
+  return event;
+}
+
+#endif     /* Use Message Queues */
+
+/********************   Mail Queue Management Functions  ***********************/
+#if (defined (osFeature_MailQ)  &&  (osFeature_MailQ != 0))  /* Use Mail Queues */
+
+
+typedef struct os_mailQ_cb {
+  const osMailQDef_t *queue_def;
+  QueueHandle_t handle;
+  osPoolId pool;
+} os_mailQ_cb_t;
+
+/**
+* @brief Create and Initialize mail queue
+* @param  queue_def     reference to the mail queue definition obtain with \ref osMailQ
+* @param   thread_id     thread ID (obtained by \ref osThreadCreate or \ref osThreadGetId) or NULL.
+* @retval mail queue ID for reference by other functions or NULL in case of error.
+* @note   MUST REMAIN UNCHANGED: \b osMailCreate shall be consistent in every CMSIS-RTOS.
+*/
+osMailQId osMailCreate (const osMailQDef_t *queue_def, osThreadId thread_id)
+{
+#if (configSUPPORT_DYNAMIC_ALLOCATION == 1)
+  (void) thread_id;
+  
+  osPoolDef_t pool_def = {queue_def->queue_sz, queue_def->item_sz, NULL};
+  
+  /* Create a mail queue control block */
+
+  *(queue_def->cb) = pvPortMalloc(sizeof(struct os_mailQ_cb));
+
+  if (*(queue_def->cb) == NULL) {
+    return NULL;
+  }
+  (*(queue_def->cb))->queue_def = queue_def;
+  
+  /* Create a queue in FreeRTOS */
+  (*(queue_def->cb))->handle = xQueueCreate(queue_def->queue_sz, sizeof(void *));
+
+
+  if ((*(queue_def->cb))->handle == NULL) {
+    vPortFree(*(queue_def->cb));
+    return NULL;
+  }
+  
+  /* Create a mail pool */
+  (*(queue_def->cb))->pool = osPoolCreate(&pool_def);
+  if ((*(queue_def->cb))->pool == NULL) {
+    //TODO: Delete queue. How to do it in FreeRTOS?
+    vPortFree(*(queue_def->cb));
+    return NULL;
+  }
+  
+  return *(queue_def->cb);
+#else
+  return NULL;
+#endif
+}
+
+/**
+* @brief Allocate a memory block from a mail
+* @param  queue_id      mail queue ID obtained with \ref osMailCreate.
+* @param  millisec      timeout value or 0 in case of no time-out.
+* @retval pointer to memory block that can be filled with mail or NULL in case error.
+* @note   MUST REMAIN UNCHANGED: \b osMailAlloc shall be consistent in every CMSIS-RTOS.
+*/
+void *osMailAlloc (osMailQId queue_id, uint32_t millisec)
+{
+  (void) millisec;
+  void *p;
+  
+  
+  if (queue_id == NULL) {
+    return NULL;
+  }
+  
+  p = osPoolAlloc(queue_id->pool);
+  
+  return p;
+}
+
+/**
+* @brief Allocate a memory block from a mail and set memory block to zero
+* @param  queue_id      mail queue ID obtained with \ref osMailCreate.
+* @param  millisec      timeout value or 0 in case of no time-out.
+* @retval pointer to memory block that can be filled with mail or NULL in case error.
+* @note   MUST REMAIN UNCHANGED: \b osMailCAlloc shall be consistent in every CMSIS-RTOS.
+*/
+void *osMailCAlloc (osMailQId queue_id, uint32_t millisec)
+{
+  uint32_t i;
+  void *p = osMailAlloc(queue_id, millisec);
+  
+  if (p) {
+    for (i = 0; i < queue_id->queue_def->item_sz; i++) {
+      ((uint8_t *)p)[i] = 0;
+    }
+  }
+  
+  return p;
+}
+
+/**
+* @brief Put a mail to a queue
+* @param  queue_id      mail queue ID obtained with \ref osMailCreate.
+* @param  mail          memory block previously allocated with \ref osMailAlloc or \ref osMailCAlloc.
+* @retval status code that indicates the execution status of the function.
+* @note   MUST REMAIN UNCHANGED: \b osMailPut shall be consistent in every CMSIS-RTOS.
+*/
+osStatus osMailPut (osMailQId queue_id, void *mail)
+{
+  portBASE_TYPE taskWoken;
+  
+  
+  if (queue_id == NULL) {
+    return osErrorParameter;
+  }
+  
+  taskWoken = pdFALSE;
+  
+  if (inHandlerMode()) {
+    if (xQueueSendFromISR(queue_id->handle, &mail, &taskWoken) != pdTRUE) {
+      return osErrorOS;
+    }
+    portEND_SWITCHING_ISR(taskWoken);
+  }
+  else {
+    if (xQueueSend(queue_id->handle, &mail, 0) != pdTRUE) { 
+      return osErrorOS;
+    }
+  }
+  
+  return osOK;
+}
+
+/**
+* @brief Get a mail from a queue
+* @param  queue_id   mail queue ID obtained with \ref osMailCreate.
+* @param millisec    timeout value or 0 in case of no time-out
+* @retval event that contains mail information or error code.
+* @note   MUST REMAIN UNCHANGED: \b osMailGet shall be consistent in every CMSIS-RTOS.
+*/
+osEvent osMailGet (osMailQId queue_id, uint32_t millisec)
+{
+  portBASE_TYPE taskWoken;
+  TickType_t ticks;
+  osEvent event;
+  
+  event.def.mail_id = queue_id;
+  
+  if (queue_id == NULL) {
+    event.status = osErrorParameter;
+    return event;
+  }
+  
+  taskWoken = pdFALSE;
+  
+  ticks = 0;
+  if (millisec == osWaitForever) {
+    ticks = portMAX_DELAY;
+  }
+  else if (millisec != 0) {
+    ticks = millisec / portTICK_PERIOD_MS;
+    if (ticks == 0) {
+      ticks = 1;
+    }
+  }
+  
+  if (inHandlerMode()) {
+    if (xQueueReceiveFromISR(queue_id->handle, &event.value.p, &taskWoken) == pdTRUE) {
+      /* We have mail */
+      event.status = osEventMail;
+    }
+    else {
+      event.status = osOK;
+    }
+    portEND_SWITCHING_ISR(taskWoken);
+  }
+  else {
+    if (xQueueReceive(queue_id->handle, &event.value.p, ticks) == pdTRUE) {
+      /* We have mail */
+      event.status = osEventMail;
+    }
+    else {
+      event.status = (ticks == 0) ? osOK : osEventTimeout;
+    }
+  }
+  
+  return event;
+}
+
+/**
+* @brief Free a memory block from a mail
+* @param  queue_id mail queue ID obtained with \ref osMailCreate.
+* @param  mail     pointer to the memory block that was obtained with \ref osMailGet.
+* @retval status code that indicates the execution status of the function.
+* @note   MUST REMAIN UNCHANGED: \b osMailFree shall be consistent in every CMSIS-RTOS.
+*/
+osStatus osMailFree (osMailQId queue_id, void *mail)
+{
+  if (queue_id == NULL) {
+    return osErrorParameter;
+  }
+  
+  return osPoolFree(queue_id->pool, mail);
+}
+#endif  /* Use Mail Queues */
+
+/*************************** Additional specific APIs to Free RTOS ************/
+/**
+* @brief  Handles the tick increment
+* @param  none.
+* @retval none.
+*/
+void osSystickHandler(void)
+{
+
+#if (INCLUDE_xTaskGetSchedulerState  == 1 )
+  if (xTaskGetSchedulerState() != taskSCHEDULER_NOT_STARTED)
+  {
+#endif  /* INCLUDE_xTaskGetSchedulerState */  
+    xPortSysTickHandler();
+#if (INCLUDE_xTaskGetSchedulerState  == 1 )
+  }
+#endif  /* INCLUDE_xTaskGetSchedulerState */  
+}
+
+#if ( INCLUDE_eTaskGetState == 1 )
+/**
+* @brief  Obtain the state of any thread.
+* @param   thread_id   thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
+* @retval  the stae of the thread, states are encoded by the osThreadState enumerated type.
+*/
+osThreadState osThreadGetState(osThreadId thread_id)
+{
+  eTaskState ThreadState;
+  osThreadState result;
+  
+  ThreadState = eTaskGetState(thread_id);
+  
+  switch (ThreadState)
+  {
+  case eRunning :
+    result = osThreadRunning;
+    break;
+  case eReady :
+    result = osThreadReady;
+    break;
+  case eBlocked :
+    result = osThreadBlocked;
+    break;
+  case eSuspended :
+    result = osThreadSuspended;
+    break;
+  case eDeleted :
+    result = osThreadDeleted;
+    break;
+  default:
+    result = osThreadError;
+  } 
+  
+  return result;
+}
+#endif /* INCLUDE_eTaskGetState */
+
+#if (INCLUDE_eTaskGetState == 1)
+/**
+* @brief Check if a thread is already suspended or not.
+* @param thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
+* @retval status code that indicates the execution status of the function.
+*/
+osStatus osThreadIsSuspended(osThreadId thread_id)
+{
+  if (eTaskGetState(thread_id) == eSuspended)
+    return osOK;
+  else
+    return osErrorOS;
+}
+#endif /* INCLUDE_eTaskGetState */
+/**
+* @brief  Suspend execution of a thread.
+* @param   thread_id   thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
+* @retval  status code that indicates the execution status of the function.
+*/
+osStatus osThreadSuspend (osThreadId thread_id)
+{
+#if (INCLUDE_vTaskSuspend == 1)
+    vTaskSuspend(thread_id);
+  
+  return osOK;
+#else
+  return osErrorResource;
+#endif
+}
+
+/**
+* @brief  Resume execution of a suspended thread.
+* @param   thread_id   thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
+* @retval  status code that indicates the execution status of the function.
+*/
+osStatus osThreadResume (osThreadId thread_id)
+{
+#if (INCLUDE_vTaskSuspend == 1)  
+  if(inHandlerMode())
+  {
+    if (xTaskResumeFromISR(thread_id) == pdTRUE)
+    {
+      portYIELD_FROM_ISR(pdTRUE);
+    }
+  }
+  else
+  {
+    vTaskResume(thread_id);
+  }
+  return osOK;
+#else
+  return osErrorResource;
+#endif
+}
+
+/**
+* @brief  Suspend execution of a all active threads.
+* @retval  status code that indicates the execution status of the function.
+*/
+osStatus osThreadSuspendAll (void)
+{
+  vTaskSuspendAll();
+  
+  return osOK;
+}
+
+/**
+* @brief  Resume execution of a all suspended threads.
+* @retval  status code that indicates the execution status of the function.
+*/
+osStatus osThreadResumeAll (void)
+{
+  if (xTaskResumeAll() == pdTRUE)
+    return osOK;
+  else
+    return osErrorOS;
+  
+}
+
+/**
+* @brief  Delay a task until a specified time
+* @param   PreviousWakeTime   Pointer to a variable that holds the time at which the 
+*          task was last unblocked. PreviousWakeTime must be initialised with the current time
+*          prior to its first use (PreviousWakeTime = osKernelSysTick() )
+* @param   millisec    time delay value
+* @retval  status code that indicates the execution status of the function.
+*/
+osStatus osDelayUntil (uint32_t *PreviousWakeTime, uint32_t millisec)
+{
+#if INCLUDE_vTaskDelayUntil
+  TickType_t ticks = (millisec / portTICK_PERIOD_MS);
+  vTaskDelayUntil((TickType_t *) PreviousWakeTime, ticks ? ticks : 1);
+  
+  return osOK;
+#else
+  (void) millisec;
+  (void) PreviousWakeTime;
+  
+  return osErrorResource;
+#endif
+}
+
+/**
+* @brief   Abort the delay for a specific thread
+* @param   thread_id   thread ID obtained by \ref osThreadCreate or \ref osThreadGetId   
+* @retval  status code that indicates the execution status of the function.
+*/
+osStatus osAbortDelay(osThreadId thread_id)
+{
+#if INCLUDE_xTaskAbortDelay
+  
+  xTaskAbortDelay(thread_id);
+  
+  return osOK;
+#else
+  (void) thread_id;
+  
+  return osErrorResource;
+#endif
+}
+
+/**
+* @brief   Lists all the current threads, along with their current state 
+*          and stack usage high water mark.
+* @param   buffer   A buffer into which the above mentioned details
+*          will be written
+* @retval  status code that indicates the execution status of the function.
+*/
+osStatus osThreadList (uint8_t *buffer)
+{
+#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS == 1 ) )
+  vTaskList((char *)buffer);
+#endif
+  return osOK;
+}
+
+/**
+* @brief  Receive an item from a queue without removing the item from the queue.
+* @param  queue_id  message queue ID obtained with \ref osMessageCreate.
+* @param  millisec  timeout value or 0 in case of no time-out.
+* @retval event information that includes status code.
+*/
+osEvent osMessagePeek (osMessageQId queue_id, uint32_t millisec)
+{
+  TickType_t ticks;
+  osEvent event;
+  
+  event.def.message_id = queue_id;
+  
+  if (queue_id == NULL) {
+    event.status = osErrorParameter;
+    return event;
+  }
+  
+  ticks = 0;
+  if (millisec == osWaitForever) {
+    ticks = portMAX_DELAY;
+  }
+  else if (millisec != 0) {
+    ticks = millisec / portTICK_PERIOD_MS;
+    if (ticks == 0) {
+      ticks = 1;
+    }
+  }
+  
+  if (xQueuePeek(queue_id, &event.value.v, ticks) == pdTRUE) 
+  {
+    /* We have mail */
+    event.status = osEventMessage;
+  }
+  else 
+  {
+    event.status = (ticks == 0) ? osOK : osEventTimeout;
+  }
+  
+  return event;
+}
+
+/**
+* @brief  Get the number of messaged stored in a queue.
+* @param  queue_id  message queue ID obtained with \ref osMessageCreate.
+* @retval number of messages stored in a queue.
+*/
+uint32_t osMessageWaiting(osMessageQId queue_id)
+{
+  if (inHandlerMode()) {
+    return uxQueueMessagesWaitingFromISR(queue_id);
+  }
+  else
+  {
+    return uxQueueMessagesWaiting(queue_id);
+  }
+}
+
+/**
+* @brief  Get the available space in a message queue.
+* @param  queue_id  message queue ID obtained with \ref osMessageCreate.
+* @retval available space in a message queue.
+*/
+uint32_t osMessageAvailableSpace(osMessageQId queue_id)  
+{
+  return uxQueueSpacesAvailable(queue_id);
+}
+
+/**
+* @brief Delete a Message Queue
+* @param  queue_id  message queue ID obtained with \ref osMessageCreate.
+* @retval  status code that indicates the execution status of the function.
+*/
+osStatus osMessageDelete (osMessageQId queue_id)
+{
+  if (inHandlerMode()) {
+    return osErrorISR;
+  }
+
+  vQueueDelete(queue_id);
+
+  return osOK; 
+}
+
+/**
+* @brief  Create and Initialize a Recursive Mutex
+* @param  mutex_def     mutex definition referenced with \ref osMutex.
+* @retval  mutex ID for reference by other functions or NULL in case of error..
+*/
+osMutexId osRecursiveMutexCreate (const osMutexDef_t *mutex_def)
+{
+#if (configUSE_RECURSIVE_MUTEXES == 1)
+#if( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+
+  if (mutex_def->controlblock != NULL){
+    return xSemaphoreCreateRecursiveMutexStatic( mutex_def->controlblock );
+  }
+  else {
+    return xSemaphoreCreateRecursiveMutex();
+  }
+#elif ( configSUPPORT_STATIC_ALLOCATION == 1 )
+  return xSemaphoreCreateRecursiveMutexStatic( mutex_def->controlblock );
+#else 
+  return xSemaphoreCreateRecursiveMutex();
+#endif
+#else
+  return NULL;
+#endif	
+}
+
+/**
+* @brief  Release a Recursive Mutex
+* @param   mutex_id      mutex ID obtained by \ref osRecursiveMutexCreate.
+* @retval  status code that indicates the execution status of the function.
+*/
+osStatus osRecursiveMutexRelease (osMutexId mutex_id)
+{
+#if (configUSE_RECURSIVE_MUTEXES == 1)
+  osStatus result = osOK;
+ 
+  if (xSemaphoreGiveRecursive(mutex_id) != pdTRUE) 
+  {
+    result = osErrorOS;
+  }
+  return result;
+#else
+	return osErrorResource;
+#endif
+}
+
+/**
+* @brief  Release a Recursive Mutex
+* @param   mutex_id    mutex ID obtained by \ref osRecursiveMutexCreate.
+* @param millisec      timeout value or 0 in case of no time-out.
+* @retval  status code that indicates the execution status of the function.
+*/
+osStatus osRecursiveMutexWait (osMutexId mutex_id, uint32_t millisec)
+{
+#if (configUSE_RECURSIVE_MUTEXES == 1)
+  TickType_t ticks;
+  
+  if (mutex_id == NULL)
+  {
+    return osErrorParameter;
+  }
+  
+  ticks = 0;
+  if (millisec == osWaitForever) 
+  {
+    ticks = portMAX_DELAY;
+  }
+  else if (millisec != 0) 
+  {
+    ticks = millisec / portTICK_PERIOD_MS;
+    if (ticks == 0) 
+    {
+      ticks = 1;
+    }
+  }
+  
+  if (xSemaphoreTakeRecursive(mutex_id, ticks) != pdTRUE) 
+  {
+    return osErrorOS;
+  }
+  return osOK;
+#else
+	return osErrorResource;
+#endif
+}
+
+/**
+* @brief  Returns the current count value of a counting semaphore
+* @param  semaphore_id  semaphore_id ID obtained by \ref osSemaphoreCreate.
+* @retval  count value
+*/
+uint32_t osSemaphoreGetCount(osSemaphoreId semaphore_id)
+{
+  return uxSemaphoreGetCount(semaphore_id);
+}
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h b/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h
new file mode 100644
index 0000000..f53a132
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h
@@ -0,0 +1,1026 @@
+/* ----------------------------------------------------------------------
+ * $Date:        5. February 2013
+ * $Revision:    V1.02
+ *
+ * Project:      CMSIS-RTOS API
+ * Title:        cmsis_os.h header file
+ *
+ * Version 0.02
+ *    Initial Proposal Phase
+ * Version 0.03
+ *    osKernelStart added, optional feature: main started as thread
+ *    osSemaphores have standard behavior
+ *    osTimerCreate does not start the timer, added osTimerStart
+ *    osThreadPass is renamed to osThreadYield
+ * Version 1.01
+ *    Support for C++ interface
+ *     - const attribute removed from the osXxxxDef_t typedef's
+ *     - const attribute added to the osXxxxDef macros
+ *    Added: osTimerDelete, osMutexDelete, osSemaphoreDelete
+ *    Added: osKernelInitialize
+ * Version 1.02
+ *    Control functions for short timeouts in microsecond resolution:
+ *    Added: osKernelSysTick, osKernelSysTickFrequency, osKernelSysTickMicroSec
+ *    Removed: osSignalGet 
+ *    
+ *  
+ *----------------------------------------------------------------------------
+ *
+ * Portions Copyright � 2016 STMicroelectronics International N.V. All rights reserved.
+ * Portions Copyright (c) 2013 ARM LIMITED
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  - Neither the name of ARM  nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without
+ *    specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *---------------------------------------------------------------------------*/
+
+#include "FreeRTOS.h"
+#include "task.h"
+#include "timers.h"
+#include "queue.h"
+#include "semphr.h"
+#include "event_groups.h"
+
+/**
+\page cmsis_os_h Header File Template: cmsis_os.h
+
+The file \b cmsis_os.h is a template header file for a CMSIS-RTOS compliant Real-Time Operating System (RTOS).
+Each RTOS that is compliant with CMSIS-RTOS shall provide a specific \b cmsis_os.h header file that represents
+its implementation.
+
+The file cmsis_os.h contains:
+ - CMSIS-RTOS API function definitions
+ - struct definitions for parameters and return types
+ - status and priority values used by CMSIS-RTOS API functions
+ - macros for defining threads and other kernel objects
+
+
+<b>Name conventions and header file modifications</b>
+
+All definitions are prefixed with \b os to give an unique name space for CMSIS-RTOS functions.
+Definitions that are prefixed \b os_ are not used in the application code but local to this header file.
+All definitions and functions that belong to a module are grouped and have a common prefix, i.e. \b osThread.
+
+Definitions that are marked with <b>CAN BE CHANGED</b> can be adapted towards the needs of the actual CMSIS-RTOS implementation.
+These definitions can be specific to the underlying RTOS kernel.
+
+Definitions that are marked with <b>MUST REMAIN UNCHANGED</b> cannot be altered. Otherwise the CMSIS-RTOS implementation is no longer
+compliant to the standard. Note that some functions are optional and need not to be provided by every CMSIS-RTOS implementation.
+
+
+<b>Function calls from interrupt service routines</b>
+
+The following CMSIS-RTOS functions can be called from threads and interrupt service routines (ISR):
+  - \ref osSignalSet
+  - \ref osSemaphoreRelease
+  - \ref osPoolAlloc, \ref osPoolCAlloc, \ref osPoolFree
+  - \ref osMessagePut, \ref osMessageGet
+  - \ref osMailAlloc, \ref osMailCAlloc, \ref osMailGet, \ref osMailPut, \ref osMailFree
+
+Functions that cannot be called from an ISR are verifying the interrupt status and return in case that they are called
+from an ISR context the status code \b osErrorISR. In some implementations this condition might be caught using the HARD FAULT vector.
+
+Some CMSIS-RTOS implementations support CMSIS-RTOS function calls from multiple ISR at the same time.
+If this is impossible, the CMSIS-RTOS rejects calls by nested ISR functions with the status code \b osErrorISRRecursive.
+
+
+<b>Define and reference object definitions</b>
+
+With <b>\#define osObjectsExternal</b> objects are defined as external symbols. This allows to create a consistent header file
+that is used throughout a project as shown below:
+
+<i>Header File</i>
+\code
+#include <cmsis_os.h>                                         // CMSIS RTOS header file
+
+// Thread definition
+extern void thread_sample (void const *argument);             // function prototype
+osThreadDef (thread_sample, osPriorityBelowNormal, 1, 100);
+
+// Pool definition
+osPoolDef(MyPool, 10, long);
+\endcode
+
+
+This header file defines all objects when included in a C/C++ source file. When <b>\#define osObjectsExternal</b> is
+present before the header file, the objects are defined as external symbols. A single consistent header file can therefore be
+used throughout the whole project.
+
+<i>Example</i>
+\code
+#include "osObjects.h"     // Definition of the CMSIS-RTOS objects
+\endcode
+
+\code
+#define osObjectExternal   // Objects will be defined as external symbols
+#include "osObjects.h"     // Reference to the CMSIS-RTOS objects
+\endcode
+
+*/
+
+#ifndef _CMSIS_OS_H
+#define _CMSIS_OS_H
+
+/// \note MUST REMAIN UNCHANGED: \b osCMSIS identifies the CMSIS-RTOS API version.
+#define osCMSIS           0x10002      ///< API version (main [31:16] .sub [15:0])
+
+/// \note CAN BE CHANGED: \b osCMSIS_KERNEL identifies the underlying RTOS kernel and version number.
+#define osCMSIS_KERNEL    0x10000	   ///< RTOS identification and version (main [31:16] .sub [15:0])
+
+/// \note MUST REMAIN UNCHANGED: \b osKernelSystemId shall be consistent in every CMSIS-RTOS.
+#define osKernelSystemId "KERNEL V1.00"   ///< RTOS identification string
+
+/// \note MUST REMAIN UNCHANGED: \b osFeature_xxx shall be consistent in every CMSIS-RTOS.
+#define osFeature_MainThread   1       ///< main thread      1=main can be thread, 0=not available
+#define osFeature_Pool         1       ///< Memory Pools:    1=available, 0=not available
+#define osFeature_MailQ        1       ///< Mail Queues:     1=available, 0=not available
+#define osFeature_MessageQ     1       ///< Message Queues:  1=available, 0=not available
+#define osFeature_Signals      8       ///< maximum number of Signal Flags available per thread
+#define osFeature_Semaphore    1      ///< osFeature_Semaphore function: 1=available, 0=not available
+#define osFeature_Wait         0       ///< osWait function: 1=available, 0=not available
+#define osFeature_SysTick      1       ///< osKernelSysTick functions: 1=available, 0=not available
+
+#ifdef  __cplusplus
+extern "C"
+{
+#endif
+
+
+// ==== Enumeration, structures, defines ====
+
+/// Priority used for thread control.
+/// \note MUST REMAIN UNCHANGED: \b osPriority shall be consistent in every CMSIS-RTOS.
+typedef enum  {
+  osPriorityIdle          = -3,          ///< priority: idle (lowest)
+  osPriorityLow           = -2,          ///< priority: low
+  osPriorityBelowNormal   = -1,          ///< priority: below normal
+  osPriorityNormal        =  0,          ///< priority: normal (default)
+  osPriorityAboveNormal   = +1,          ///< priority: above normal
+  osPriorityHigh          = +2,          ///< priority: high
+  osPriorityRealtime      = +3,          ///< priority: realtime (highest)
+  osPriorityError         =  0x84        ///< system cannot determine priority or thread has illegal priority
+} osPriority;
+
+/// Timeout value.
+/// \note MUST REMAIN UNCHANGED: \b osWaitForever shall be consistent in every CMSIS-RTOS.
+#define osWaitForever     0xFFFFFFFF     ///< wait forever timeout value
+
+/// Status code values returned by CMSIS-RTOS functions.
+/// \note MUST REMAIN UNCHANGED: \b osStatus shall be consistent in every CMSIS-RTOS.
+typedef enum  {
+  osOK                    =     0,       ///< function completed; no error or event occurred.
+  osEventSignal           =  0x08,       ///< function completed; signal event occurred.
+  osEventMessage          =  0x10,       ///< function completed; message event occurred.
+  osEventMail             =  0x20,       ///< function completed; mail event occurred.
+  osEventTimeout          =  0x40,       ///< function completed; timeout occurred.
+  osErrorParameter        =  0x80,       ///< parameter error: a mandatory parameter was missing or specified an incorrect object.
+  osErrorResource         =  0x81,       ///< resource not available: a specified resource was not available.
+  osErrorTimeoutResource  =  0xC1,       ///< resource not available within given time: a specified resource was not available within the timeout period.
+  osErrorISR              =  0x82,       ///< not allowed in ISR context: the function cannot be called from interrupt service routines.
+  osErrorISRRecursive     =  0x83,       ///< function called multiple times from ISR with same object.
+  osErrorPriority         =  0x84,       ///< system cannot determine priority or thread has illegal priority.
+  osErrorNoMemory         =  0x85,       ///< system is out of memory: it was impossible to allocate or reserve memory for the operation.
+  osErrorValue            =  0x86,       ///< value of a parameter is out of range.
+  osErrorOS               =  0xFF,       ///< unspecified RTOS error: run-time error but no other error message fits.
+  os_status_reserved      =  0x7FFFFFFF  ///< prevent from enum down-size compiler optimization.
+} osStatus;
+
+#if ( INCLUDE_eTaskGetState == 1 )
+/* Thread state returned by osThreadGetState */
+typedef enum {
+	osThreadRunning   = 0x0,	      /* A thread is querying the state of itself, so must be running. */
+	osThreadReady     = 0x1 ,			        /* The thread being queried is in a read or pending ready list. */
+	osThreadBlocked   = 0x2,		        /* The thread being queried is in the Blocked state. */
+	osThreadSuspended = 0x3,	      /* The thread being queried is in the Suspended state, or is in the Blocked state with an infinite time out. */
+	osThreadDeleted   = 0x4,		          /* The thread being queried has been deleted, but its TCB has not yet been freed. */   
+  osThreadError     = 0x7FFFFFFF
+} osThreadState;
+#endif /* INCLUDE_eTaskGetState */
+
+/// Timer type value for the timer definition.
+/// \note MUST REMAIN UNCHANGED: \b os_timer_type shall be consistent in every CMSIS-RTOS.
+typedef enum  {
+  osTimerOnce             =     0,       ///< one-shot timer
+  osTimerPeriodic         =     1        ///< repeating timer
+} os_timer_type;
+
+/// Entry point of a thread.
+/// \note MUST REMAIN UNCHANGED: \b os_pthread shall be consistent in every CMSIS-RTOS.
+typedef void (*os_pthread) (void const *argument);
+
+/// Entry point of a timer call back function.
+/// \note MUST REMAIN UNCHANGED: \b os_ptimer shall be consistent in every CMSIS-RTOS.
+typedef void (*os_ptimer) (void const *argument);
+
+// >>> the following data type definitions may shall adapted towards a specific RTOS
+
+/// Thread ID identifies the thread (pointer to a thread control block).
+/// \note CAN BE CHANGED: \b os_thread_cb is implementation specific in every CMSIS-RTOS.
+typedef TaskHandle_t osThreadId;
+
+/// Timer ID identifies the timer (pointer to a timer control block).
+/// \note CAN BE CHANGED: \b os_timer_cb is implementation specific in every CMSIS-RTOS.
+typedef TimerHandle_t osTimerId;
+
+/// Mutex ID identifies the mutex (pointer to a mutex control block).
+/// \note CAN BE CHANGED: \b os_mutex_cb is implementation specific in every CMSIS-RTOS.
+typedef SemaphoreHandle_t osMutexId;
+
+/// Semaphore ID identifies the semaphore (pointer to a semaphore control block).
+/// \note CAN BE CHANGED: \b os_semaphore_cb is implementation specific in every CMSIS-RTOS.
+typedef SemaphoreHandle_t osSemaphoreId;
+
+/// Pool ID identifies the memory pool (pointer to a memory pool control block).
+/// \note CAN BE CHANGED: \b os_pool_cb is implementation specific in every CMSIS-RTOS.
+typedef struct os_pool_cb *osPoolId;
+
+/// Message ID identifies the message queue (pointer to a message queue control block).
+/// \note CAN BE CHANGED: \b os_messageQ_cb is implementation specific in every CMSIS-RTOS.
+typedef QueueHandle_t osMessageQId;
+
+/// Mail ID identifies the mail queue (pointer to a mail queue control block).
+/// \note CAN BE CHANGED: \b os_mailQ_cb is implementation specific in every CMSIS-RTOS.
+typedef struct os_mailQ_cb *osMailQId;
+
+
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+
+typedef StaticTask_t               osStaticThreadDef_t;
+typedef StaticTimer_t              osStaticTimerDef_t;
+typedef StaticSemaphore_t          osStaticMutexDef_t;         
+typedef StaticSemaphore_t          osStaticSemaphoreDef_t;
+typedef StaticQueue_t              osStaticMessageQDef_t;
+
+#endif
+
+
+
+
+/// Thread Definition structure contains startup information of a thread.
+/// \note CAN BE CHANGED: \b os_thread_def is implementation specific in every CMSIS-RTOS.
+typedef struct os_thread_def  {
+  char                   *name;        ///< Thread name 
+  os_pthread             pthread;      ///< start address of thread function
+  osPriority             tpriority;    ///< initial thread priority
+  uint32_t               instances;    ///< maximum number of instances of that thread function
+  uint32_t               stacksize;    ///< stack size requirements in bytes; 0 is default stack size
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+  uint32_t               *buffer;      ///< stack buffer for static allocation; NULL for dynamic allocation
+  osStaticThreadDef_t    *controlblock;     ///< control block to hold thread's data for static allocation; NULL for dynamic allocation
+#endif
+} osThreadDef_t;
+
+/// Timer Definition structure contains timer parameters.
+/// \note CAN BE CHANGED: \b os_timer_def is implementation specific in every CMSIS-RTOS.
+typedef struct os_timer_def  {
+  os_ptimer                 ptimer;    ///< start address of a timer function
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+  osStaticTimerDef_t        *controlblock;      ///< control block to hold timer's data for static allocation; NULL for dynamic allocation
+#endif
+} osTimerDef_t;
+
+/// Mutex Definition structure contains setup information for a mutex.
+/// \note CAN BE CHANGED: \b os_mutex_def is implementation specific in every CMSIS-RTOS.
+typedef struct os_mutex_def  {
+  uint32_t                   dummy;    ///< dummy value.
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+  osStaticMutexDef_t         *controlblock;      ///< control block for static allocation; NULL for dynamic allocation
+#endif
+} osMutexDef_t;
+
+/// Semaphore Definition structure contains setup information for a semaphore.
+/// \note CAN BE CHANGED: \b os_semaphore_def is implementation specific in every CMSIS-RTOS.
+typedef struct os_semaphore_def  {
+  uint32_t                   dummy;    ///< dummy value.
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+  osStaticSemaphoreDef_t     *controlblock;      ///< control block for static allocation; NULL for dynamic allocation
+#endif
+} osSemaphoreDef_t;
+
+/// Definition structure for memory block allocation.
+/// \note CAN BE CHANGED: \b os_pool_def is implementation specific in every CMSIS-RTOS.
+typedef struct os_pool_def  {
+  uint32_t                 pool_sz;    ///< number of items (elements) in the pool
+  uint32_t                 item_sz;    ///< size of an item
+  void                       *pool;    ///< pointer to memory for pool
+} osPoolDef_t;
+
+/// Definition structure for message queue.
+/// \note CAN BE CHANGED: \b os_messageQ_def is implementation specific in every CMSIS-RTOS.
+typedef struct os_messageQ_def  {
+  uint32_t                queue_sz;    ///< number of elements in the queue
+  uint32_t                item_sz;    ///< size of an item
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+  uint8_t                 *buffer;      ///< buffer for static allocation; NULL for dynamic allocation
+  osStaticMessageQDef_t   *controlblock;     ///< control block to hold queue's data for static allocation; NULL for dynamic allocation
+#endif
+  //void                       *pool;    ///< memory array for messages
+} osMessageQDef_t;
+
+/// Definition structure for mail queue.
+/// \note CAN BE CHANGED: \b os_mailQ_def is implementation specific in every CMSIS-RTOS.
+typedef struct os_mailQ_def  {
+  uint32_t                queue_sz;    ///< number of elements in the queue
+  uint32_t                 item_sz;    ///< size of an item
+  struct os_mailQ_cb **cb;
+} osMailQDef_t;
+
+/// Event structure contains detailed information about an event.
+/// \note MUST REMAIN UNCHANGED: \b os_event shall be consistent in every CMSIS-RTOS.
+///       However the struct may be extended at the end.
+typedef struct  {
+  osStatus                 status;     ///< status code: event or error information
+  union  {
+    uint32_t                    v;     ///< message as 32-bit value
+    void                       *p;     ///< message or mail as void pointer
+    int32_t               signals;     ///< signal flags
+  } value;                             ///< event value
+  union  {
+    osMailQId             mail_id;     ///< mail id obtained by \ref osMailCreate
+    osMessageQId       message_id;     ///< message id obtained by \ref osMessageCreate
+  } def;                               ///< event definition
+} osEvent;
+
+
+//  ==== Kernel Control Functions ====
+
+/// Initialize the RTOS Kernel for creating objects.
+/// \return status code that indicates the execution status of the function.
+/// \note MUST REMAIN UNCHANGED: \b osKernelInitialize shall be consistent in every CMSIS-RTOS.
+osStatus osKernelInitialize (void);
+
+/// Start the RTOS Kernel.
+/// \return status code that indicates the execution status of the function.
+/// \note MUST REMAIN UNCHANGED: \b osKernelStart shall be consistent in every CMSIS-RTOS.
+osStatus osKernelStart (void);
+
+/// Check if the RTOS kernel is already started.
+/// \note MUST REMAIN UNCHANGED: \b osKernelRunning shall be consistent in every CMSIS-RTOS.
+/// \return 0 RTOS is not started, 1 RTOS is started.
+int32_t osKernelRunning(void);
+
+#if (defined (osFeature_SysTick)  &&  (osFeature_SysTick != 0))     // System Timer available
+
+/// Get the RTOS kernel system timer counter 
+/// \note MUST REMAIN UNCHANGED: \b osKernelSysTick shall be consistent in every CMSIS-RTOS.
+/// \return RTOS kernel system timer as 32-bit value 
+uint32_t osKernelSysTick (void);
+
+/// The RTOS kernel system timer frequency in Hz
+/// \note Reflects the system timer setting and is typically defined in a configuration file.
+#define osKernelSysTickFrequency      (configTICK_RATE_HZ)
+
+/// Convert a microseconds value to a RTOS kernel system timer value.
+/// \param         microsec     time value in microseconds.
+/// \return time value normalized to the \ref osKernelSysTickFrequency
+#define osKernelSysTickMicroSec(microsec) (((uint64_t)microsec * (osKernelSysTickFrequency)) / 1000000)
+
+#endif    // System Timer available
+
+//  ==== Thread Management ====
+
+/// Create a Thread Definition with function, priority, and stack requirements.
+/// \param         name         name of the thread function.
+/// \param         priority     initial priority of the thread function.
+/// \param         instances    number of possible thread instances.
+/// \param         stacksz      stack size (in bytes) requirements for the thread function.
+/// \note CAN BE CHANGED: The parameters to \b osThreadDef shall be consistent but the
+///       macro body is implementation specific in every CMSIS-RTOS.
+#if defined (osObjectsExternal)  // object is external
+#define osThreadDef(name, thread, priority, instances, stacksz)  \
+extern const osThreadDef_t os_thread_def_##name
+#else                            // define the object
+
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+#define osThreadDef(name, thread, priority, instances, stacksz)  \
+const osThreadDef_t os_thread_def_##name = \
+{ #name, (thread), (priority), (instances), (stacksz), NULL, NULL }
+
+#define osThreadStaticDef(name, thread, priority, instances, stacksz, buffer, control)  \
+const osThreadDef_t os_thread_def_##name = \
+{ #name, (thread), (priority), (instances), (stacksz), (buffer), (control) }
+#else //configSUPPORT_STATIC_ALLOCATION == 0
+
+#define osThreadDef(name, thread, priority, instances, stacksz)  \
+const osThreadDef_t os_thread_def_##name = \
+{ #name, (thread), (priority), (instances), (stacksz)}
+#endif
+#endif
+
+/// Access a Thread definition.
+/// \param         name          name of the thread definition object.
+/// \note CAN BE CHANGED: The parameter to \b osThread shall be consistent but the
+///       macro body is implementation specific in every CMSIS-RTOS.
+#define osThread(name)  \
+&os_thread_def_##name
+
+/// Create a thread and add it to Active Threads and set it to state READY.
+/// \param[in]     thread_def    thread definition referenced with \ref osThread.
+/// \param[in]     argument      pointer that is passed to the thread function as start argument.
+/// \return thread ID for reference by other functions or NULL in case of error.
+/// \note MUST REMAIN UNCHANGED: \b osThreadCreate shall be consistent in every CMSIS-RTOS.
+osThreadId osThreadCreate (const osThreadDef_t *thread_def, void *argument);
+
+/// Return the thread ID of the current running thread.
+/// \return thread ID for reference by other functions or NULL in case of error.
+/// \note MUST REMAIN UNCHANGED: \b osThreadGetId shall be consistent in every CMSIS-RTOS.
+osThreadId osThreadGetId (void);
+
+/// Terminate execution of a thread and remove it from Active Threads.
+/// \param[in]     thread_id   thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
+/// \return status code that indicates the execution status of the function.
+/// \note MUST REMAIN UNCHANGED: \b osThreadTerminate shall be consistent in every CMSIS-RTOS.
+osStatus osThreadTerminate (osThreadId thread_id);
+
+/// Pass control to next thread that is in state \b READY.
+/// \return status code that indicates the execution status of the function.
+/// \note MUST REMAIN UNCHANGED: \b osThreadYield shall be consistent in every CMSIS-RTOS.
+osStatus osThreadYield (void);
+
+/// Change priority of an active thread.
+/// \param[in]     thread_id     thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
+/// \param[in]     priority      new priority value for the thread function.
+/// \return status code that indicates the execution status of the function.
+/// \note MUST REMAIN UNCHANGED: \b osThreadSetPriority shall be consistent in every CMSIS-RTOS.
+osStatus osThreadSetPriority (osThreadId thread_id, osPriority priority);
+
+/// Get current priority of an active thread.
+/// \param[in]     thread_id     thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
+/// \return current priority value of the thread function.
+/// \note MUST REMAIN UNCHANGED: \b osThreadGetPriority shall be consistent in every CMSIS-RTOS.
+osPriority osThreadGetPriority (osThreadId thread_id);
+
+
+//  ==== Generic Wait Functions ====
+
+/// Wait for Timeout (Time Delay).
+/// \param[in]     millisec      time delay value
+/// \return status code that indicates the execution status of the function.
+osStatus osDelay (uint32_t millisec);
+
+#if (defined (osFeature_Wait)  &&  (osFeature_Wait != 0))     // Generic Wait available
+
+/// Wait for Signal, Message, Mail, or Timeout.
+/// \param[in] millisec          timeout value or 0 in case of no time-out
+/// \return event that contains signal, message, or mail information or error code.
+/// \note MUST REMAIN UNCHANGED: \b osWait shall be consistent in every CMSIS-RTOS.
+osEvent osWait (uint32_t millisec);
+
+#endif  // Generic Wait available
+
+
+//  ==== Timer Management Functions ====
+/// Define a Timer object.
+/// \param         name          name of the timer object.
+/// \param         function      name of the timer call back function.
+/// \note CAN BE CHANGED: The parameter to \b osTimerDef shall be consistent but the
+///       macro body is implementation specific in every CMSIS-RTOS.
+#if defined (osObjectsExternal)  // object is external
+#define osTimerDef(name, function)  \
+extern const osTimerDef_t os_timer_def_##name
+#else                            // define the object
+
+#if( configSUPPORT_STATIC_ALLOCATION == 1 ) 
+#define osTimerDef(name, function)  \
+const osTimerDef_t os_timer_def_##name = \
+{ (function), NULL }
+
+#define osTimerStaticDef(name, function, control)  \
+const osTimerDef_t os_timer_def_##name = \
+{ (function), (control) }
+#else //configSUPPORT_STATIC_ALLOCATION == 0
+#define osTimerDef(name, function)  \
+const osTimerDef_t os_timer_def_##name = \
+{ (function) }
+#endif
+#endif
+
+/// Access a Timer definition.
+/// \param         name          name of the timer object.
+/// \note CAN BE CHANGED: The parameter to \b osTimer shall be consistent but the
+///       macro body is implementation specific in every CMSIS-RTOS.
+#define osTimer(name) \
+&os_timer_def_##name
+
+/// Create a timer.
+/// \param[in]     timer_def     timer object referenced with \ref osTimer.
+/// \param[in]     type          osTimerOnce for one-shot or osTimerPeriodic for periodic behavior.
+/// \param[in]     argument      argument to the timer call back function.
+/// \return timer ID for reference by other functions or NULL in case of error.
+/// \note MUST REMAIN UNCHANGED: \b osTimerCreate shall be consistent in every CMSIS-RTOS.
+osTimerId osTimerCreate (const osTimerDef_t *timer_def, os_timer_type type, void *argument);
+
+/// Start or restart a timer.
+/// \param[in]     timer_id      timer ID obtained by \ref osTimerCreate.
+/// \param[in]     millisec      time delay value of the timer.
+/// \return status code that indicates the execution status of the function.
+/// \note MUST REMAIN UNCHANGED: \b osTimerStart shall be consistent in every CMSIS-RTOS.
+osStatus osTimerStart (osTimerId timer_id, uint32_t millisec);
+
+/// Stop the timer.
+/// \param[in]     timer_id      timer ID obtained by \ref osTimerCreate.
+/// \return status code that indicates the execution status of the function.
+/// \note MUST REMAIN UNCHANGED: \b osTimerStop shall be consistent in every CMSIS-RTOS.
+osStatus osTimerStop (osTimerId timer_id);
+
+/// Delete a timer that was created by \ref osTimerCreate.
+/// \param[in]     timer_id      timer ID obtained by \ref osTimerCreate.
+/// \return status code that indicates the execution status of the function.
+/// \note MUST REMAIN UNCHANGED: \b osTimerDelete shall be consistent in every CMSIS-RTOS.
+osStatus osTimerDelete (osTimerId timer_id);
+
+
+//  ==== Signal Management ====
+
+/// Set the specified Signal Flags of an active thread.
+/// \param[in]     thread_id     thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
+/// \param[in]     signals       specifies the signal flags of the thread that should be set.
+/// \return osOK if successful, osErrorOS if failed.
+/// \note MUST REMAIN UNCHANGED: \b osSignalSet shall be consistent in every CMSIS-RTOS.
+int32_t osSignalSet (osThreadId thread_id, int32_t signals);
+
+/// Clear the specified Signal Flags of an active thread.
+/// \param[in]     thread_id     thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
+/// \param[in]     signals       specifies the signal flags of the thread that shall be cleared.
+/// \return previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters.
+/// \note MUST REMAIN UNCHANGED: \b osSignalClear shall be consistent in every CMSIS-RTOS.
+int32_t osSignalClear (osThreadId thread_id, int32_t signals);
+
+/// Wait for one or more Signal Flags to become signaled for the current \b RUNNING thread.
+/// \param[in]     signals       wait until all specified signal flags set or 0 for any single signal flag.
+/// \param[in]     millisec      timeout value or 0 in case of no time-out.
+/// \return event flag information or error code.
+/// \note MUST REMAIN UNCHANGED: \b osSignalWait shall be consistent in every CMSIS-RTOS.
+osEvent osSignalWait (int32_t signals, uint32_t millisec);
+
+
+//  ==== Mutex Management ====
+
+/// Define a Mutex.
+/// \param         name          name of the mutex object.
+/// \note CAN BE CHANGED: The parameter to \b osMutexDef shall be consistent but the
+///       macro body is implementation specific in every CMSIS-RTOS.
+#if defined (osObjectsExternal)  // object is external
+#define osMutexDef(name)  \
+extern const osMutexDef_t os_mutex_def_##name
+#else                            // define the object
+
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+#define osMutexDef(name)  \
+const osMutexDef_t os_mutex_def_##name = { 0, NULL }
+
+#define osMutexStaticDef(name, control)  \
+const osMutexDef_t os_mutex_def_##name = { 0, (control) }
+#else //configSUPPORT_STATIC_ALLOCATION == 0
+#define osMutexDef(name)  \
+const osMutexDef_t os_mutex_def_##name = { 0 }
+
+#endif
+
+#endif
+
+/// Access a Mutex definition.
+/// \param         name          name of the mutex object.
+/// \note CAN BE CHANGED: The parameter to \b osMutex shall be consistent but the
+///       macro body is implementation specific in every CMSIS-RTOS.
+#define osMutex(name)  \
+&os_mutex_def_##name
+
+/// Create and Initialize a Mutex object.
+/// \param[in]     mutex_def     mutex definition referenced with \ref osMutex.
+/// \return mutex ID for reference by other functions or NULL in case of error.
+/// \note MUST REMAIN UNCHANGED: \b osMutexCreate shall be consistent in every CMSIS-RTOS.
+osMutexId osMutexCreate (const osMutexDef_t *mutex_def);
+
+/// Wait until a Mutex becomes available.
+/// \param[in]     mutex_id      mutex ID obtained by \ref osMutexCreate.
+/// \param[in]     millisec      timeout value or 0 in case of no time-out.
+/// \return status code that indicates the execution status of the function.
+/// \note MUST REMAIN UNCHANGED: \b osMutexWait shall be consistent in every CMSIS-RTOS.
+osStatus osMutexWait (osMutexId mutex_id, uint32_t millisec);
+
+/// Release a Mutex that was obtained by \ref osMutexWait.
+/// \param[in]     mutex_id      mutex ID obtained by \ref osMutexCreate.
+/// \return status code that indicates the execution status of the function.
+/// \note MUST REMAIN UNCHANGED: \b osMutexRelease shall be consistent in every CMSIS-RTOS.
+osStatus osMutexRelease (osMutexId mutex_id);
+
+/// Delete a Mutex that was created by \ref osMutexCreate.
+/// \param[in]     mutex_id      mutex ID obtained by \ref osMutexCreate.
+/// \return status code that indicates the execution status of the function.
+/// \note MUST REMAIN UNCHANGED: \b osMutexDelete shall be consistent in every CMSIS-RTOS.
+osStatus osMutexDelete (osMutexId mutex_id);
+
+
+//  ==== Semaphore Management Functions ====
+
+#if (defined (osFeature_Semaphore)  &&  (osFeature_Semaphore != 0))     // Semaphore available
+
+/// Define a Semaphore object.
+/// \param         name          name of the semaphore object.
+/// \note CAN BE CHANGED: The parameter to \b osSemaphoreDef shall be consistent but the
+///       macro body is implementation specific in every CMSIS-RTOS.
+#if defined (osObjectsExternal)  // object is external
+#define osSemaphoreDef(name)  \
+extern const osSemaphoreDef_t os_semaphore_def_##name
+#else                            // define the object
+
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+#define osSemaphoreDef(name)  \
+const osSemaphoreDef_t os_semaphore_def_##name = { 0, NULL }
+
+#define osSemaphoreStaticDef(name, control)  \
+const osSemaphoreDef_t os_semaphore_def_##name = { 0, (control) }
+
+#else //configSUPPORT_STATIC_ALLOCATION == 0
+#define osSemaphoreDef(name)  \
+const osSemaphoreDef_t os_semaphore_def_##name = { 0 }
+#endif
+#endif
+
+/// Access a Semaphore definition.
+/// \param         name          name of the semaphore object.
+/// \note CAN BE CHANGED: The parameter to \b osSemaphore shall be consistent but the
+///       macro body is implementation specific in every CMSIS-RTOS.
+#define osSemaphore(name)  \
+&os_semaphore_def_##name
+
+/// Create and Initialize a Semaphore object used for managing resources.
+/// \param[in]     semaphore_def semaphore definition referenced with \ref osSemaphore.
+/// \param[in]     count         number of available resources.
+/// \return semaphore ID for reference by other functions or NULL in case of error.
+/// \note MUST REMAIN UNCHANGED: \b osSemaphoreCreate shall be consistent in every CMSIS-RTOS.
+osSemaphoreId osSemaphoreCreate (const osSemaphoreDef_t *semaphore_def, int32_t count);
+
+/// Wait until a Semaphore token becomes available.
+/// \param[in]     semaphore_id  semaphore object referenced with \ref osSemaphoreCreate.
+/// \param[in]     millisec      timeout value or 0 in case of no time-out.
+/// \return number of available tokens, or -1 in case of incorrect parameters.
+/// \note MUST REMAIN UNCHANGED: \b osSemaphoreWait shall be consistent in every CMSIS-RTOS.
+int32_t osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec);
+
+/// Release a Semaphore token.
+/// \param[in]     semaphore_id  semaphore object referenced with \ref osSemaphoreCreate.
+/// \return status code that indicates the execution status of the function.
+/// \note MUST REMAIN UNCHANGED: \b osSemaphoreRelease shall be consistent in every CMSIS-RTOS.
+osStatus osSemaphoreRelease (osSemaphoreId semaphore_id);
+
+/// Delete a Semaphore that was created by \ref osSemaphoreCreate.
+/// \param[in]     semaphore_id  semaphore object referenced with \ref osSemaphoreCreate.
+/// \return status code that indicates the execution status of the function.
+/// \note MUST REMAIN UNCHANGED: \b osSemaphoreDelete shall be consistent in every CMSIS-RTOS.
+osStatus osSemaphoreDelete (osSemaphoreId semaphore_id);
+
+#endif     // Semaphore available
+
+
+//  ==== Memory Pool Management Functions ====
+
+#if (defined (osFeature_Pool)  &&  (osFeature_Pool != 0))  // Memory Pool Management available
+
+/// \brief Define a Memory Pool.
+/// \param         name          name of the memory pool.
+/// \param         no            maximum number of blocks (objects) in the memory pool.
+/// \param         type          data type of a single block (object).
+/// \note CAN BE CHANGED: The parameter to \b osPoolDef shall be consistent but the
+///       macro body is implementation specific in every CMSIS-RTOS.
+#if defined (osObjectsExternal)  // object is external
+#define osPoolDef(name, no, type)   \
+extern const osPoolDef_t os_pool_def_##name
+#else                            // define the object
+#define osPoolDef(name, no, type)   \
+const osPoolDef_t os_pool_def_##name = \
+{ (no), sizeof(type), NULL }
+#endif
+
+/// \brief Access a Memory Pool definition.
+/// \param         name          name of the memory pool
+/// \note CAN BE CHANGED: The parameter to \b osPool shall be consistent but the
+///       macro body is implementation specific in every CMSIS-RTOS.
+#define osPool(name) \
+&os_pool_def_##name
+
+/// Create and Initialize a memory pool.
+/// \param[in]     pool_def      memory pool definition referenced with \ref osPool.
+/// \return memory pool ID for reference by other functions or NULL in case of error.
+/// \note MUST REMAIN UNCHANGED: \b osPoolCreate shall be consistent in every CMSIS-RTOS.
+osPoolId osPoolCreate (const osPoolDef_t *pool_def);
+
+/// Allocate a memory block from a memory pool.
+/// \param[in]     pool_id       memory pool ID obtain referenced with \ref osPoolCreate.
+/// \return address of the allocated memory block or NULL in case of no memory available.
+/// \note MUST REMAIN UNCHANGED: \b osPoolAlloc shall be consistent in every CMSIS-RTOS.
+void *osPoolAlloc (osPoolId pool_id);
+
+/// Allocate a memory block from a memory pool and set memory block to zero.
+/// \param[in]     pool_id       memory pool ID obtain referenced with \ref osPoolCreate.
+/// \return address of the allocated memory block or NULL in case of no memory available.
+/// \note MUST REMAIN UNCHANGED: \b osPoolCAlloc shall be consistent in every CMSIS-RTOS.
+void *osPoolCAlloc (osPoolId pool_id);
+
+/// Return an allocated memory block back to a specific memory pool.
+/// \param[in]     pool_id       memory pool ID obtain referenced with \ref osPoolCreate.
+/// \param[in]     block         address of the allocated memory block that is returned to the memory pool.
+/// \return status code that indicates the execution status of the function.
+/// \note MUST REMAIN UNCHANGED: \b osPoolFree shall be consistent in every CMSIS-RTOS.
+osStatus osPoolFree (osPoolId pool_id, void *block);
+
+#endif   // Memory Pool Management available
+
+
+//  ==== Message Queue Management Functions ====
+
+#if (defined (osFeature_MessageQ)  &&  (osFeature_MessageQ != 0))     // Message Queues available
+
+/// \brief Create a Message Queue Definition.
+/// \param         name          name of the queue.
+/// \param         queue_sz      maximum number of messages in the queue.
+/// \param         type          data type of a single message element (for debugger).
+/// \note CAN BE CHANGED: The parameter to \b osMessageQDef shall be consistent but the
+///       macro body is implementation specific in every CMSIS-RTOS.
+#if defined (osObjectsExternal)  // object is external
+#define osMessageQDef(name, queue_sz, type)   \
+extern const osMessageQDef_t os_messageQ_def_##name
+#else                            // define the object
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+#define osMessageQDef(name, queue_sz, type)   \
+const osMessageQDef_t os_messageQ_def_##name = \
+{ (queue_sz), sizeof (type), NULL, NULL  }
+
+#define osMessageQStaticDef(name, queue_sz, type, buffer, control)   \
+const osMessageQDef_t os_messageQ_def_##name = \
+{ (queue_sz), sizeof (type) , (buffer), (control)}
+#else //configSUPPORT_STATIC_ALLOCATION == 1
+#define osMessageQDef(name, queue_sz, type)   \
+const osMessageQDef_t os_messageQ_def_##name = \
+{ (queue_sz), sizeof (type) }
+
+#endif
+#endif
+
+/// \brief Access a Message Queue Definition.
+/// \param         name          name of the queue
+/// \note CAN BE CHANGED: The parameter to \b osMessageQ shall be consistent but the
+///       macro body is implementation specific in every CMSIS-RTOS.
+#define osMessageQ(name) \
+&os_messageQ_def_##name
+
+/// Create and Initialize a Message Queue.
+/// \param[in]     queue_def     queue definition referenced with \ref osMessageQ.
+/// \param[in]     thread_id     thread ID (obtained by \ref osThreadCreate or \ref osThreadGetId) or NULL.
+/// \return message queue ID for reference by other functions or NULL in case of error.
+/// \note MUST REMAIN UNCHANGED: \b osMessageCreate shall be consistent in every CMSIS-RTOS.
+osMessageQId osMessageCreate (const osMessageQDef_t *queue_def, osThreadId thread_id);
+
+/// Put a Message to a Queue.
+/// \param[in]     queue_id      message queue ID obtained with \ref osMessageCreate.
+/// \param[in]     info          message information.
+/// \param[in]     millisec      timeout value or 0 in case of no time-out.
+/// \return status code that indicates the execution status of the function.
+/// \note MUST REMAIN UNCHANGED: \b osMessagePut shall be consistent in every CMSIS-RTOS.
+osStatus osMessagePut (osMessageQId queue_id, uint32_t info, uint32_t millisec);
+
+/// Get a Message or Wait for a Message from a Queue.
+/// \param[in]     queue_id      message queue ID obtained with \ref osMessageCreate.
+/// \param[in]     millisec      timeout value or 0 in case of no time-out.
+/// \return event information that includes status code.
+/// \note MUST REMAIN UNCHANGED: \b osMessageGet shall be consistent in every CMSIS-RTOS.
+osEvent osMessageGet (osMessageQId queue_id, uint32_t millisec);
+
+#endif     // Message Queues available
+
+
+//  ==== Mail Queue Management Functions ====
+
+#if (defined (osFeature_MailQ)  &&  (osFeature_MailQ != 0))     // Mail Queues available
+
+/// \brief Create a Mail Queue Definition.
+/// \param         name          name of the queue
+/// \param         queue_sz      maximum number of messages in queue
+/// \param         type          data type of a single message element
+/// \note CAN BE CHANGED: The parameter to \b osMailQDef shall be consistent but the
+///       macro body is implementation specific in every CMSIS-RTOS.
+#if defined (osObjectsExternal)  // object is external
+#define osMailQDef(name, queue_sz, type) \
+extern struct os_mailQ_cb *os_mailQ_cb_##name \
+extern osMailQDef_t os_mailQ_def_##name
+#else                            // define the object
+#define osMailQDef(name, queue_sz, type) \
+struct os_mailQ_cb *os_mailQ_cb_##name; \
+const osMailQDef_t os_mailQ_def_##name =  \
+{ (queue_sz), sizeof (type), (&os_mailQ_cb_##name) }
+#endif
+
+/// \brief Access a Mail Queue Definition.
+/// \param         name          name of the queue
+/// \note CAN BE CHANGED: The parameter to \b osMailQ shall be consistent but the
+///       macro body is implementation specific in every CMSIS-RTOS.
+#define osMailQ(name)  \
+&os_mailQ_def_##name
+
+/// Create and Initialize mail queue.
+/// \param[in]     queue_def     reference to the mail queue definition obtain with \ref osMailQ
+/// \param[in]     thread_id     thread ID (obtained by \ref osThreadCreate or \ref osThreadGetId) or NULL.
+/// \return mail queue ID for reference by other functions or NULL in case of error.
+/// \note MUST REMAIN UNCHANGED: \b osMailCreate shall be consistent in every CMSIS-RTOS.
+osMailQId osMailCreate (const osMailQDef_t *queue_def, osThreadId thread_id);
+
+/// Allocate a memory block from a mail.
+/// \param[in]     queue_id      mail queue ID obtained with \ref osMailCreate.
+/// \param[in]     millisec      timeout value or 0 in case of no time-out
+/// \return pointer to memory block that can be filled with mail or NULL in case of error.
+/// \note MUST REMAIN UNCHANGED: \b osMailAlloc shall be consistent in every CMSIS-RTOS.
+void *osMailAlloc (osMailQId queue_id, uint32_t millisec);
+
+/// Allocate a memory block from a mail and set memory block to zero.
+/// \param[in]     queue_id      mail queue ID obtained with \ref osMailCreate.
+/// \param[in]     millisec      timeout value or 0 in case of no time-out
+/// \return pointer to memory block that can be filled with mail or NULL in case of error.
+/// \note MUST REMAIN UNCHANGED: \b osMailCAlloc shall be consistent in every CMSIS-RTOS.
+void *osMailCAlloc (osMailQId queue_id, uint32_t millisec);
+
+/// Put a mail to a queue.
+/// \param[in]     queue_id      mail queue ID obtained with \ref osMailCreate.
+/// \param[in]     mail          memory block previously allocated with \ref osMailAlloc or \ref osMailCAlloc.
+/// \return status code that indicates the execution status of the function.
+/// \note MUST REMAIN UNCHANGED: \b osMailPut shall be consistent in every CMSIS-RTOS.
+osStatus osMailPut (osMailQId queue_id, void *mail);
+
+/// Get a mail from a queue.
+/// \param[in]     queue_id      mail queue ID obtained with \ref osMailCreate.
+/// \param[in]     millisec      timeout value or 0 in case of no time-out
+/// \return event that contains mail information or error code.
+/// \note MUST REMAIN UNCHANGED: \b osMailGet shall be consistent in every CMSIS-RTOS.
+osEvent osMailGet (osMailQId queue_id, uint32_t millisec);
+
+/// Free a memory block from a mail.
+/// \param[in]     queue_id      mail queue ID obtained with \ref osMailCreate.
+/// \param[in]     mail          pointer to the memory block that was obtained with \ref osMailGet.
+/// \return status code that indicates the execution status of the function.
+/// \note MUST REMAIN UNCHANGED: \b osMailFree shall be consistent in every CMSIS-RTOS.
+osStatus osMailFree (osMailQId queue_id, void *mail);
+
+#endif  // Mail Queues available
+
+/*************************** Additional specific APIs to Free RTOS ************/
+/**
+* @brief  Handles the tick increment
+* @param  none.
+* @retval none.
+*/
+void osSystickHandler(void);
+
+#if ( INCLUDE_eTaskGetState == 1 )
+/**
+* @brief  Obtain the state of any thread.
+* @param   thread_id   thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
+* @retval  the stae of the thread, states are encoded by the osThreadState enumerated type.
+*/
+osThreadState osThreadGetState(osThreadId thread_id);
+#endif /* INCLUDE_eTaskGetState */
+
+#if ( INCLUDE_eTaskGetState == 1 )
+/**
+* @brief Check if a thread is already suspended or not.
+* @param thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
+* @retval status code that indicates the execution status of the function.
+*/
+
+osStatus osThreadIsSuspended(osThreadId thread_id);
+
+#endif /* INCLUDE_eTaskGetState */
+
+/**
+* @brief  Suspend execution of a thread.
+* @param   thread_id   thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
+* @retval  status code that indicates the execution status of the function.
+*/
+osStatus osThreadSuspend (osThreadId thread_id);
+
+/**
+* @brief  Resume execution of a suspended thread.
+* @param   thread_id   thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
+* @retval  status code that indicates the execution status of the function.
+*/
+osStatus osThreadResume (osThreadId thread_id);
+
+/**
+* @brief  Suspend execution of a all active threads.
+* @retval  status code that indicates the execution status of the function.
+*/
+osStatus osThreadSuspendAll (void);
+
+/**
+* @brief  Resume execution of a all suspended threads.
+* @retval  status code that indicates the execution status of the function.
+*/
+osStatus osThreadResumeAll (void);
+
+/**
+* @brief  Delay a task until a specified time
+* @param   PreviousWakeTime   Pointer to a variable that holds the time at which the 
+*          task was last unblocked. PreviousWakeTime must be initialised with the current time
+*          prior to its first use (PreviousWakeTime = osKernelSysTick() )
+* @param   millisec    time delay value
+* @retval  status code that indicates the execution status of the function.
+*/
+osStatus osDelayUntil (uint32_t *PreviousWakeTime, uint32_t millisec);
+
+/**
+* @brief   Abort the delay for a specific thread
+* @param   thread_id   thread ID obtained by \ref osThreadCreate or \ref osThreadGetId   
+* @retval  status code that indicates the execution status of the function.
+*/
+osStatus osAbortDelay(osThreadId thread_id);
+
+/**
+* @brief   Lists all the current threads, along with their current state 
+*          and stack usage high water mark.
+* @param   buffer   A buffer into which the above mentioned details
+*          will be written
+* @retval  status code that indicates the execution status of the function.
+*/
+osStatus osThreadList (uint8_t *buffer);
+
+/**
+* @brief  Receive an item from a queue without removing the item from the queue.
+* @param  queue_id  message queue ID obtained with \ref osMessageCreate.
+* @param  millisec  timeout value or 0 in case of no time-out.
+* @retval event information that includes status code.
+*/
+osEvent osMessagePeek (osMessageQId queue_id, uint32_t millisec);
+
+/**
+* @brief  Get the number of messaged stored in a queue.
+* @param  queue_id  message queue ID obtained with \ref osMessageCreate.
+* @retval number of messages stored in a queue.
+*/
+uint32_t osMessageWaiting(osMessageQId queue_id);
+
+/**
+* @brief  Get the available space in a message queue.
+* @param  queue_id  message queue ID obtained with \ref osMessageCreate.
+* @retval available space in a message queue.
+*/
+uint32_t osMessageAvailableSpace(osMessageQId queue_id);
+
+/**
+* @brief Delete a Message Queue
+* @param  queue_id  message queue ID obtained with \ref osMessageCreate.
+* @retval  status code that indicates the execution status of the function.
+*/
+osStatus osMessageDelete (osMessageQId queue_id);
+
+/**
+* @brief  Create and Initialize a Recursive Mutex
+* @param  mutex_def     mutex definition referenced with \ref osMutex.
+* @retval  mutex ID for reference by other functions or NULL in case of error..
+*/
+osMutexId osRecursiveMutexCreate (const osMutexDef_t *mutex_def);
+
+/**
+* @brief  Release a Recursive Mutex
+* @param   mutex_id      mutex ID obtained by \ref osRecursiveMutexCreate.
+* @retval  status code that indicates the execution status of the function.
+*/
+osStatus osRecursiveMutexRelease (osMutexId mutex_id);
+
+/**
+* @brief  Release a Recursive Mutex
+* @param   mutex_id    mutex ID obtained by \ref osRecursiveMutexCreate.
+* @param millisec      timeout value or 0 in case of no time-out.
+* @retval  status code that indicates the execution status of the function.
+*/
+osStatus osRecursiveMutexWait (osMutexId mutex_id, uint32_t millisec);
+
+/**
+* @brief  Returns the current count value of a counting semaphore
+* @param   semaphore_id  semaphore_id ID obtained by \ref osSemaphoreCreate.
+* @retval  count value
+*/
+uint32_t osSemaphoreGetCount(osSemaphoreId semaphore_id);
+
+#ifdef  __cplusplus
+}
+#endif
+
+#endif  // _CMSIS_OS_H
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/LICENSE b/Middlewares/Third_Party/FreeRTOS/Source/LICENSE
new file mode 100644
index 0000000..2ce4711
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/LICENSE
@@ -0,0 +1,18 @@
+Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+Permission is hereby granted, free of charge, to any person obtaining a copy of
+this software and associated documentation files (the "Software"), to deal in
+the Software without restriction, including without limitation the rights to
+use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+the Software, and to permit persons to whom the Software is furnished to do so,
+subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/croutine.c b/Middlewares/Third_Party/FreeRTOS/Source/croutine.c
new file mode 100644
index 0000000..9ce5003
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/croutine.c
@@ -0,0 +1,353 @@
+/*
+ * FreeRTOS Kernel V10.3.1
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#include "FreeRTOS.h"
+#include "task.h"
+#include "croutine.h"
+
+/* Remove the whole file is co-routines are not being used. */
+#if( configUSE_CO_ROUTINES != 0 )
+
+/*
+ * Some kernel aware debuggers require data to be viewed to be global, rather
+ * than file scope.
+ */
+#ifdef portREMOVE_STATIC_QUALIFIER
+	#define static
+#endif
+
+
+/* Lists for ready and blocked co-routines. --------------------*/
+static List_t pxReadyCoRoutineLists[ configMAX_CO_ROUTINE_PRIORITIES ];	/*< Prioritised ready co-routines. */
+static List_t xDelayedCoRoutineList1;									/*< Delayed co-routines. */
+static List_t xDelayedCoRoutineList2;									/*< Delayed co-routines (two lists are used - one for delays that have overflowed the current tick count. */
+static List_t * pxDelayedCoRoutineList;									/*< Points to the delayed co-routine list currently being used. */
+static List_t * pxOverflowDelayedCoRoutineList;							/*< Points to the delayed co-routine list currently being used to hold co-routines that have overflowed the current tick count. */
+static List_t xPendingReadyCoRoutineList;								/*< Holds co-routines that have been readied by an external event.  They cannot be added directly to the ready lists as the ready lists cannot be accessed by interrupts. */
+
+/* Other file private variables. --------------------------------*/
+CRCB_t * pxCurrentCoRoutine = NULL;
+static UBaseType_t uxTopCoRoutineReadyPriority = 0;
+static TickType_t xCoRoutineTickCount = 0, xLastTickCount = 0, xPassedTicks = 0;
+
+/* The initial state of the co-routine when it is created. */
+#define corINITIAL_STATE	( 0 )
+
+/*
+ * Place the co-routine represented by pxCRCB into the appropriate ready queue
+ * for the priority.  It is inserted at the end of the list.
+ *
+ * This macro accesses the co-routine ready lists and therefore must not be
+ * used from within an ISR.
+ */
+#define prvAddCoRoutineToReadyQueue( pxCRCB )																		\
+{																													\
+	if( pxCRCB->uxPriority > uxTopCoRoutineReadyPriority )															\
+	{																												\
+		uxTopCoRoutineReadyPriority = pxCRCB->uxPriority;															\
+	}																												\
+	vListInsertEnd( ( List_t * ) &( pxReadyCoRoutineLists[ pxCRCB->uxPriority ] ), &( pxCRCB->xGenericListItem ) );	\
+}
+
+/*
+ * Utility to ready all the lists used by the scheduler.  This is called
+ * automatically upon the creation of the first co-routine.
+ */
+static void prvInitialiseCoRoutineLists( void );
+
+/*
+ * Co-routines that are readied by an interrupt cannot be placed directly into
+ * the ready lists (there is no mutual exclusion).  Instead they are placed in
+ * in the pending ready list in order that they can later be moved to the ready
+ * list by the co-routine scheduler.
+ */
+static void prvCheckPendingReadyList( void );
+
+/*
+ * Macro that looks at the list of co-routines that are currently delayed to
+ * see if any require waking.
+ *
+ * Co-routines are stored in the queue in the order of their wake time -
+ * meaning once one co-routine has been found whose timer has not expired
+ * we need not look any further down the list.
+ */
+static void prvCheckDelayedList( void );
+
+/*-----------------------------------------------------------*/
+
+BaseType_t xCoRoutineCreate( crCOROUTINE_CODE pxCoRoutineCode, UBaseType_t uxPriority, UBaseType_t uxIndex )
+{
+BaseType_t xReturn;
+CRCB_t *pxCoRoutine;
+
+	/* Allocate the memory that will store the co-routine control block. */
+	pxCoRoutine = ( CRCB_t * ) pvPortMalloc( sizeof( CRCB_t ) );
+	if( pxCoRoutine )
+	{
+		/* If pxCurrentCoRoutine is NULL then this is the first co-routine to
+		be created and the co-routine data structures need initialising. */
+		if( pxCurrentCoRoutine == NULL )
+		{
+			pxCurrentCoRoutine = pxCoRoutine;
+			prvInitialiseCoRoutineLists();
+		}
+
+		/* Check the priority is within limits. */
+		if( uxPriority >= configMAX_CO_ROUTINE_PRIORITIES )
+		{
+			uxPriority = configMAX_CO_ROUTINE_PRIORITIES - 1;
+		}
+
+		/* Fill out the co-routine control block from the function parameters. */
+		pxCoRoutine->uxState = corINITIAL_STATE;
+		pxCoRoutine->uxPriority = uxPriority;
+		pxCoRoutine->uxIndex = uxIndex;
+		pxCoRoutine->pxCoRoutineFunction = pxCoRoutineCode;
+
+		/* Initialise all the other co-routine control block parameters. */
+		vListInitialiseItem( &( pxCoRoutine->xGenericListItem ) );
+		vListInitialiseItem( &( pxCoRoutine->xEventListItem ) );
+
+		/* Set the co-routine control block as a link back from the ListItem_t.
+		This is so we can get back to the containing CRCB from a generic item
+		in a list. */
+		listSET_LIST_ITEM_OWNER( &( pxCoRoutine->xGenericListItem ), pxCoRoutine );
+		listSET_LIST_ITEM_OWNER( &( pxCoRoutine->xEventListItem ), pxCoRoutine );
+
+		/* Event lists are always in priority order. */
+		listSET_LIST_ITEM_VALUE( &( pxCoRoutine->xEventListItem ), ( ( TickType_t ) configMAX_CO_ROUTINE_PRIORITIES - ( TickType_t ) uxPriority ) );
+
+		/* Now the co-routine has been initialised it can be added to the ready
+		list at the correct priority. */
+		prvAddCoRoutineToReadyQueue( pxCoRoutine );
+
+		xReturn = pdPASS;
+	}
+	else
+	{
+		xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;
+	}
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+void vCoRoutineAddToDelayedList( TickType_t xTicksToDelay, List_t *pxEventList )
+{
+TickType_t xTimeToWake;
+
+	/* Calculate the time to wake - this may overflow but this is
+	not a problem. */
+	xTimeToWake = xCoRoutineTickCount + xTicksToDelay;
+
+	/* We must remove ourselves from the ready list before adding
+	ourselves to the blocked list as the same list item is used for
+	both lists. */
+	( void ) uxListRemove( ( ListItem_t * ) &( pxCurrentCoRoutine->xGenericListItem ) );
+
+	/* The list item will be inserted in wake time order. */
+	listSET_LIST_ITEM_VALUE( &( pxCurrentCoRoutine->xGenericListItem ), xTimeToWake );
+
+	if( xTimeToWake < xCoRoutineTickCount )
+	{
+		/* Wake time has overflowed.  Place this item in the
+		overflow list. */
+		vListInsert( ( List_t * ) pxOverflowDelayedCoRoutineList, ( ListItem_t * ) &( pxCurrentCoRoutine->xGenericListItem ) );
+	}
+	else
+	{
+		/* The wake time has not overflowed, so we can use the
+		current block list. */
+		vListInsert( ( List_t * ) pxDelayedCoRoutineList, ( ListItem_t * ) &( pxCurrentCoRoutine->xGenericListItem ) );
+	}
+
+	if( pxEventList )
+	{
+		/* Also add the co-routine to an event list.  If this is done then the
+		function must be called with interrupts disabled. */
+		vListInsert( pxEventList, &( pxCurrentCoRoutine->xEventListItem ) );
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvCheckPendingReadyList( void )
+{
+	/* Are there any co-routines waiting to get moved to the ready list?  These
+	are co-routines that have been readied by an ISR.  The ISR cannot access
+	the	ready lists itself. */
+	while( listLIST_IS_EMPTY( &xPendingReadyCoRoutineList ) == pdFALSE )
+	{
+		CRCB_t *pxUnblockedCRCB;
+
+		/* The pending ready list can be accessed by an ISR. */
+		portDISABLE_INTERRUPTS();
+		{
+			pxUnblockedCRCB = ( CRCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( (&xPendingReadyCoRoutineList) );
+			( void ) uxListRemove( &( pxUnblockedCRCB->xEventListItem ) );
+		}
+		portENABLE_INTERRUPTS();
+
+		( void ) uxListRemove( &( pxUnblockedCRCB->xGenericListItem ) );
+		prvAddCoRoutineToReadyQueue( pxUnblockedCRCB );
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvCheckDelayedList( void )
+{
+CRCB_t *pxCRCB;
+
+	xPassedTicks = xTaskGetTickCount() - xLastTickCount;
+	while( xPassedTicks )
+	{
+		xCoRoutineTickCount++;
+		xPassedTicks--;
+
+		/* If the tick count has overflowed we need to swap the ready lists. */
+		if( xCoRoutineTickCount == 0 )
+		{
+			List_t * pxTemp;
+
+			/* Tick count has overflowed so we need to swap the delay lists.  If there are
+			any items in pxDelayedCoRoutineList here then there is an error! */
+			pxTemp = pxDelayedCoRoutineList;
+			pxDelayedCoRoutineList = pxOverflowDelayedCoRoutineList;
+			pxOverflowDelayedCoRoutineList = pxTemp;
+		}
+
+		/* See if this tick has made a timeout expire. */
+		while( listLIST_IS_EMPTY( pxDelayedCoRoutineList ) == pdFALSE )
+		{
+			pxCRCB = ( CRCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxDelayedCoRoutineList );
+
+			if( xCoRoutineTickCount < listGET_LIST_ITEM_VALUE( &( pxCRCB->xGenericListItem ) ) )
+			{
+				/* Timeout not yet expired. */
+				break;
+			}
+
+			portDISABLE_INTERRUPTS();
+			{
+				/* The event could have occurred just before this critical
+				section.  If this is the case then the generic list item will
+				have been moved to the pending ready list and the following
+				line is still valid.  Also the pvContainer parameter will have
+				been set to NULL so the following lines are also valid. */
+				( void ) uxListRemove( &( pxCRCB->xGenericListItem ) );
+
+				/* Is the co-routine waiting on an event also? */
+				if( pxCRCB->xEventListItem.pxContainer )
+				{
+					( void ) uxListRemove( &( pxCRCB->xEventListItem ) );
+				}
+			}
+			portENABLE_INTERRUPTS();
+
+			prvAddCoRoutineToReadyQueue( pxCRCB );
+		}
+	}
+
+	xLastTickCount = xCoRoutineTickCount;
+}
+/*-----------------------------------------------------------*/
+
+void vCoRoutineSchedule( void )
+{
+	/* See if any co-routines readied by events need moving to the ready lists. */
+	prvCheckPendingReadyList();
+
+	/* See if any delayed co-routines have timed out. */
+	prvCheckDelayedList();
+
+	/* Find the highest priority queue that contains ready co-routines. */
+	while( listLIST_IS_EMPTY( &( pxReadyCoRoutineLists[ uxTopCoRoutineReadyPriority ] ) ) )
+	{
+		if( uxTopCoRoutineReadyPriority == 0 )
+		{
+			/* No more co-routines to check. */
+			return;
+		}
+		--uxTopCoRoutineReadyPriority;
+	}
+
+	/* listGET_OWNER_OF_NEXT_ENTRY walks through the list, so the co-routines
+	 of the	same priority get an equal share of the processor time. */
+	listGET_OWNER_OF_NEXT_ENTRY( pxCurrentCoRoutine, &( pxReadyCoRoutineLists[ uxTopCoRoutineReadyPriority ] ) );
+
+	/* Call the co-routine. */
+	( pxCurrentCoRoutine->pxCoRoutineFunction )( pxCurrentCoRoutine, pxCurrentCoRoutine->uxIndex );
+
+	return;
+}
+/*-----------------------------------------------------------*/
+
+static void prvInitialiseCoRoutineLists( void )
+{
+UBaseType_t uxPriority;
+
+	for( uxPriority = 0; uxPriority < configMAX_CO_ROUTINE_PRIORITIES; uxPriority++ )
+	{
+		vListInitialise( ( List_t * ) &( pxReadyCoRoutineLists[ uxPriority ] ) );
+	}
+
+	vListInitialise( ( List_t * ) &xDelayedCoRoutineList1 );
+	vListInitialise( ( List_t * ) &xDelayedCoRoutineList2 );
+	vListInitialise( ( List_t * ) &xPendingReadyCoRoutineList );
+
+	/* Start with pxDelayedCoRoutineList using list1 and the
+	pxOverflowDelayedCoRoutineList using list2. */
+	pxDelayedCoRoutineList = &xDelayedCoRoutineList1;
+	pxOverflowDelayedCoRoutineList = &xDelayedCoRoutineList2;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xCoRoutineRemoveFromEventList( const List_t *pxEventList )
+{
+CRCB_t *pxUnblockedCRCB;
+BaseType_t xReturn;
+
+	/* This function is called from within an interrupt.  It can only access
+	event lists and the pending ready list.  This function assumes that a
+	check has already been made to ensure pxEventList is not empty. */
+	pxUnblockedCRCB = ( CRCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxEventList );
+	( void ) uxListRemove( &( pxUnblockedCRCB->xEventListItem ) );
+	vListInsertEnd( ( List_t * ) &( xPendingReadyCoRoutineList ), &( pxUnblockedCRCB->xEventListItem ) );
+
+	if( pxUnblockedCRCB->uxPriority >= pxCurrentCoRoutine->uxPriority )
+	{
+		xReturn = pdTRUE;
+	}
+	else
+	{
+		xReturn = pdFALSE;
+	}
+
+	return xReturn;
+}
+
+#endif /* configUSE_CO_ROUTINES == 0 */
+
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/event_groups.c b/Middlewares/Third_Party/FreeRTOS/Source/event_groups.c
new file mode 100644
index 0000000..bf4ec24
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/event_groups.c
@@ -0,0 +1,753 @@
+/*
+ * FreeRTOS Kernel V10.3.1
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Standard includes. */
+#include <stdlib.h>
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+all the API functions to use the MPU wrappers.  That should only be done when
+task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* FreeRTOS includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "timers.h"
+#include "event_groups.h"
+
+/* Lint e961, e750 and e9021 are suppressed as a MISRA exception justified
+because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined
+for the header files above, but not in this file, in order to generate the
+correct privileged Vs unprivileged linkage and placement. */
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750 !e9021 See comment above. */
+
+/* The following bit fields convey control information in a task's event list
+item value.  It is important they don't clash with the
+taskEVENT_LIST_ITEM_VALUE_IN_USE definition. */
+#if configUSE_16_BIT_TICKS == 1
+	#define eventCLEAR_EVENTS_ON_EXIT_BIT	0x0100U
+	#define eventUNBLOCKED_DUE_TO_BIT_SET	0x0200U
+	#define eventWAIT_FOR_ALL_BITS			0x0400U
+	#define eventEVENT_BITS_CONTROL_BYTES	0xff00U
+#else
+	#define eventCLEAR_EVENTS_ON_EXIT_BIT	0x01000000UL
+	#define eventUNBLOCKED_DUE_TO_BIT_SET	0x02000000UL
+	#define eventWAIT_FOR_ALL_BITS			0x04000000UL
+	#define eventEVENT_BITS_CONTROL_BYTES	0xff000000UL
+#endif
+
+typedef struct EventGroupDef_t
+{
+	EventBits_t uxEventBits;
+	List_t xTasksWaitingForBits;		/*< List of tasks waiting for a bit to be set. */
+
+	#if( configUSE_TRACE_FACILITY == 1 )
+		UBaseType_t uxEventGroupNumber;
+	#endif
+
+	#if( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+		uint8_t ucStaticallyAllocated; /*< Set to pdTRUE if the event group is statically allocated to ensure no attempt is made to free the memory. */
+	#endif
+} EventGroup_t;
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Test the bits set in uxCurrentEventBits to see if the wait condition is met.
+ * The wait condition is defined by xWaitForAllBits.  If xWaitForAllBits is
+ * pdTRUE then the wait condition is met if all the bits set in uxBitsToWaitFor
+ * are also set in uxCurrentEventBits.  If xWaitForAllBits is pdFALSE then the
+ * wait condition is met if any of the bits set in uxBitsToWait for are also set
+ * in uxCurrentEventBits.
+ */
+static BaseType_t prvTestWaitCondition( const EventBits_t uxCurrentEventBits, const EventBits_t uxBitsToWaitFor, const BaseType_t xWaitForAllBits ) PRIVILEGED_FUNCTION;
+
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+
+	EventGroupHandle_t xEventGroupCreateStatic( StaticEventGroup_t *pxEventGroupBuffer )
+	{
+	EventGroup_t *pxEventBits;
+
+		/* A StaticEventGroup_t object must be provided. */
+		configASSERT( pxEventGroupBuffer );
+
+		#if( configASSERT_DEFINED == 1 )
+		{
+			/* Sanity check that the size of the structure used to declare a
+			variable of type StaticEventGroup_t equals the size of the real
+			event group structure. */
+			volatile size_t xSize = sizeof( StaticEventGroup_t );
+			configASSERT( xSize == sizeof( EventGroup_t ) );
+		} /*lint !e529 xSize is referenced if configASSERT() is defined. */
+		#endif /* configASSERT_DEFINED */
+
+		/* The user has provided a statically allocated event group - use it. */
+		pxEventBits = ( EventGroup_t * ) pxEventGroupBuffer; /*lint !e740 !e9087 EventGroup_t and StaticEventGroup_t are deliberately aliased for data hiding purposes and guaranteed to have the same size and alignment requirement - checked by configASSERT(). */
+
+		if( pxEventBits != NULL )
+		{
+			pxEventBits->uxEventBits = 0;
+			vListInitialise( &( pxEventBits->xTasksWaitingForBits ) );
+
+			#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+			{
+				/* Both static and dynamic allocation can be used, so note that
+				this event group was created statically in case the event group
+				is later deleted. */
+				pxEventBits->ucStaticallyAllocated = pdTRUE;
+			}
+			#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+
+			traceEVENT_GROUP_CREATE( pxEventBits );
+		}
+		else
+		{
+			/* xEventGroupCreateStatic should only ever be called with
+			pxEventGroupBuffer pointing to a pre-allocated (compile time
+			allocated) StaticEventGroup_t variable. */
+			traceEVENT_GROUP_CREATE_FAILED();
+		}
+
+		return pxEventBits;
+	}
+
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+
+	EventGroupHandle_t xEventGroupCreate( void )
+	{
+	EventGroup_t *pxEventBits;
+
+		/* Allocate the event group.  Justification for MISRA deviation as
+		follows:  pvPortMalloc() always ensures returned memory blocks are
+		aligned per the requirements of the MCU stack.  In this case
+		pvPortMalloc() must return a pointer that is guaranteed to meet the
+		alignment requirements of the EventGroup_t structure - which (if you
+		follow it through) is the alignment requirements of the TickType_t type
+		(EventBits_t being of TickType_t itself).  Therefore, whenever the
+		stack alignment requirements are greater than or equal to the
+		TickType_t alignment requirements the cast is safe.  In other cases,
+		where the natural word size of the architecture is less than
+		sizeof( TickType_t ), the TickType_t variables will be accessed in two
+		or more reads operations, and the alignment requirements is only that
+		of each individual read. */
+		pxEventBits = ( EventGroup_t * ) pvPortMalloc( sizeof( EventGroup_t ) ); /*lint !e9087 !e9079 see comment above. */
+
+		if( pxEventBits != NULL )
+		{
+			pxEventBits->uxEventBits = 0;
+			vListInitialise( &( pxEventBits->xTasksWaitingForBits ) );
+
+			#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+			{
+				/* Both static and dynamic allocation can be used, so note this
+				event group was allocated statically in case the event group is
+				later deleted. */
+				pxEventBits->ucStaticallyAllocated = pdFALSE;
+			}
+			#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+			traceEVENT_GROUP_CREATE( pxEventBits );
+		}
+		else
+		{
+			traceEVENT_GROUP_CREATE_FAILED(); /*lint !e9063 Else branch only exists to allow tracing and does not generate code if trace macros are not defined. */
+		}
+
+		return pxEventBits;
+	}
+
+#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+EventBits_t xEventGroupSync( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, const EventBits_t uxBitsToWaitFor, TickType_t xTicksToWait )
+{
+EventBits_t uxOriginalBitValue, uxReturn;
+EventGroup_t *pxEventBits = xEventGroup;
+BaseType_t xAlreadyYielded;
+BaseType_t xTimeoutOccurred = pdFALSE;
+
+	configASSERT( ( uxBitsToWaitFor & eventEVENT_BITS_CONTROL_BYTES ) == 0 );
+	configASSERT( uxBitsToWaitFor != 0 );
+	#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
+	{
+		configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
+	}
+	#endif
+
+	vTaskSuspendAll();
+	{
+		uxOriginalBitValue = pxEventBits->uxEventBits;
+
+		( void ) xEventGroupSetBits( xEventGroup, uxBitsToSet );
+
+		if( ( ( uxOriginalBitValue | uxBitsToSet ) & uxBitsToWaitFor ) == uxBitsToWaitFor )
+		{
+			/* All the rendezvous bits are now set - no need to block. */
+			uxReturn = ( uxOriginalBitValue | uxBitsToSet );
+
+			/* Rendezvous always clear the bits.  They will have been cleared
+			already unless this is the only task in the rendezvous. */
+			pxEventBits->uxEventBits &= ~uxBitsToWaitFor;
+
+			xTicksToWait = 0;
+		}
+		else
+		{
+			if( xTicksToWait != ( TickType_t ) 0 )
+			{
+				traceEVENT_GROUP_SYNC_BLOCK( xEventGroup, uxBitsToSet, uxBitsToWaitFor );
+
+				/* Store the bits that the calling task is waiting for in the
+				task's event list item so the kernel knows when a match is
+				found.  Then enter the blocked state. */
+				vTaskPlaceOnUnorderedEventList( &( pxEventBits->xTasksWaitingForBits ), ( uxBitsToWaitFor | eventCLEAR_EVENTS_ON_EXIT_BIT | eventWAIT_FOR_ALL_BITS ), xTicksToWait );
+
+				/* This assignment is obsolete as uxReturn will get set after
+				the task unblocks, but some compilers mistakenly generate a
+				warning about uxReturn being returned without being set if the
+				assignment is omitted. */
+				uxReturn = 0;
+			}
+			else
+			{
+				/* The rendezvous bits were not set, but no block time was
+				specified - just return the current event bit value. */
+				uxReturn = pxEventBits->uxEventBits;
+				xTimeoutOccurred = pdTRUE;
+			}
+		}
+	}
+	xAlreadyYielded = xTaskResumeAll();
+
+	if( xTicksToWait != ( TickType_t ) 0 )
+	{
+		if( xAlreadyYielded == pdFALSE )
+		{
+			portYIELD_WITHIN_API();
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		/* The task blocked to wait for its required bits to be set - at this
+		point either the required bits were set or the block time expired.  If
+		the required bits were set they will have been stored in the task's
+		event list item, and they should now be retrieved then cleared. */
+		uxReturn = uxTaskResetEventItemValue();
+
+		if( ( uxReturn & eventUNBLOCKED_DUE_TO_BIT_SET ) == ( EventBits_t ) 0 )
+		{
+			/* The task timed out, just return the current event bit value. */
+			taskENTER_CRITICAL();
+			{
+				uxReturn = pxEventBits->uxEventBits;
+
+				/* Although the task got here because it timed out before the
+				bits it was waiting for were set, it is possible that since it
+				unblocked another task has set the bits.  If this is the case
+				then it needs to clear the bits before exiting. */
+				if( ( uxReturn & uxBitsToWaitFor ) == uxBitsToWaitFor )
+				{
+					pxEventBits->uxEventBits &= ~uxBitsToWaitFor;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			taskEXIT_CRITICAL();
+
+			xTimeoutOccurred = pdTRUE;
+		}
+		else
+		{
+			/* The task unblocked because the bits were set. */
+		}
+
+		/* Control bits might be set as the task had blocked should not be
+		returned. */
+		uxReturn &= ~eventEVENT_BITS_CONTROL_BYTES;
+	}
+
+	traceEVENT_GROUP_SYNC_END( xEventGroup, uxBitsToSet, uxBitsToWaitFor, xTimeoutOccurred );
+
+	/* Prevent compiler warnings when trace macros are not used. */
+	( void ) xTimeoutOccurred;
+
+	return uxReturn;
+}
+/*-----------------------------------------------------------*/
+
+EventBits_t xEventGroupWaitBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToWaitFor, const BaseType_t xClearOnExit, const BaseType_t xWaitForAllBits, TickType_t xTicksToWait )
+{
+EventGroup_t *pxEventBits = xEventGroup;
+EventBits_t uxReturn, uxControlBits = 0;
+BaseType_t xWaitConditionMet, xAlreadyYielded;
+BaseType_t xTimeoutOccurred = pdFALSE;
+
+	/* Check the user is not attempting to wait on the bits used by the kernel
+	itself, and that at least one bit is being requested. */
+	configASSERT( xEventGroup );
+	configASSERT( ( uxBitsToWaitFor & eventEVENT_BITS_CONTROL_BYTES ) == 0 );
+	configASSERT( uxBitsToWaitFor != 0 );
+	#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
+	{
+		configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
+	}
+	#endif
+
+	vTaskSuspendAll();
+	{
+		const EventBits_t uxCurrentEventBits = pxEventBits->uxEventBits;
+
+		/* Check to see if the wait condition is already met or not. */
+		xWaitConditionMet = prvTestWaitCondition( uxCurrentEventBits, uxBitsToWaitFor, xWaitForAllBits );
+
+		if( xWaitConditionMet != pdFALSE )
+		{
+			/* The wait condition has already been met so there is no need to
+			block. */
+			uxReturn = uxCurrentEventBits;
+			xTicksToWait = ( TickType_t ) 0;
+
+			/* Clear the wait bits if requested to do so. */
+			if( xClearOnExit != pdFALSE )
+			{
+				pxEventBits->uxEventBits &= ~uxBitsToWaitFor;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else if( xTicksToWait == ( TickType_t ) 0 )
+		{
+			/* The wait condition has not been met, but no block time was
+			specified, so just return the current value. */
+			uxReturn = uxCurrentEventBits;
+			xTimeoutOccurred = pdTRUE;
+		}
+		else
+		{
+			/* The task is going to block to wait for its required bits to be
+			set.  uxControlBits are used to remember the specified behaviour of
+			this call to xEventGroupWaitBits() - for use when the event bits
+			unblock the task. */
+			if( xClearOnExit != pdFALSE )
+			{
+				uxControlBits |= eventCLEAR_EVENTS_ON_EXIT_BIT;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+
+			if( xWaitForAllBits != pdFALSE )
+			{
+				uxControlBits |= eventWAIT_FOR_ALL_BITS;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+
+			/* Store the bits that the calling task is waiting for in the
+			task's event list item so the kernel knows when a match is
+			found.  Then enter the blocked state. */
+			vTaskPlaceOnUnorderedEventList( &( pxEventBits->xTasksWaitingForBits ), ( uxBitsToWaitFor | uxControlBits ), xTicksToWait );
+
+			/* This is obsolete as it will get set after the task unblocks, but
+			some compilers mistakenly generate a warning about the variable
+			being returned without being set if it is not done. */
+			uxReturn = 0;
+
+			traceEVENT_GROUP_WAIT_BITS_BLOCK( xEventGroup, uxBitsToWaitFor );
+		}
+	}
+	xAlreadyYielded = xTaskResumeAll();
+
+	if( xTicksToWait != ( TickType_t ) 0 )
+	{
+		if( xAlreadyYielded == pdFALSE )
+		{
+			portYIELD_WITHIN_API();
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		/* The task blocked to wait for its required bits to be set - at this
+		point either the required bits were set or the block time expired.  If
+		the required bits were set they will have been stored in the task's
+		event list item, and they should now be retrieved then cleared. */
+		uxReturn = uxTaskResetEventItemValue();
+
+		if( ( uxReturn & eventUNBLOCKED_DUE_TO_BIT_SET ) == ( EventBits_t ) 0 )
+		{
+			taskENTER_CRITICAL();
+			{
+				/* The task timed out, just return the current event bit value. */
+				uxReturn = pxEventBits->uxEventBits;
+
+				/* It is possible that the event bits were updated between this
+				task leaving the Blocked state and running again. */
+				if( prvTestWaitCondition( uxReturn, uxBitsToWaitFor, xWaitForAllBits ) != pdFALSE )
+				{
+					if( xClearOnExit != pdFALSE )
+					{
+						pxEventBits->uxEventBits &= ~uxBitsToWaitFor;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+				xTimeoutOccurred = pdTRUE;
+			}
+			taskEXIT_CRITICAL();
+		}
+		else
+		{
+			/* The task unblocked because the bits were set. */
+		}
+
+		/* The task blocked so control bits may have been set. */
+		uxReturn &= ~eventEVENT_BITS_CONTROL_BYTES;
+	}
+	traceEVENT_GROUP_WAIT_BITS_END( xEventGroup, uxBitsToWaitFor, xTimeoutOccurred );
+
+	/* Prevent compiler warnings when trace macros are not used. */
+	( void ) xTimeoutOccurred;
+
+	return uxReturn;
+}
+/*-----------------------------------------------------------*/
+
+EventBits_t xEventGroupClearBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear )
+{
+EventGroup_t *pxEventBits = xEventGroup;
+EventBits_t uxReturn;
+
+	/* Check the user is not attempting to clear the bits used by the kernel
+	itself. */
+	configASSERT( xEventGroup );
+	configASSERT( ( uxBitsToClear & eventEVENT_BITS_CONTROL_BYTES ) == 0 );
+
+	taskENTER_CRITICAL();
+	{
+		traceEVENT_GROUP_CLEAR_BITS( xEventGroup, uxBitsToClear );
+
+		/* The value returned is the event group value prior to the bits being
+		cleared. */
+		uxReturn = pxEventBits->uxEventBits;
+
+		/* Clear the bits. */
+		pxEventBits->uxEventBits &= ~uxBitsToClear;
+	}
+	taskEXIT_CRITICAL();
+
+	return uxReturn;
+}
+/*-----------------------------------------------------------*/
+
+#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) )
+
+	BaseType_t xEventGroupClearBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear )
+	{
+		BaseType_t xReturn;
+
+		traceEVENT_GROUP_CLEAR_BITS_FROM_ISR( xEventGroup, uxBitsToClear );
+		xReturn = xTimerPendFunctionCallFromISR( vEventGroupClearBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToClear, NULL ); /*lint !e9087 Can't avoid cast to void* as a generic callback function not specific to this use case. Callback casts back to original type so safe. */
+
+		return xReturn;
+	}
+
+#endif
+/*-----------------------------------------------------------*/
+
+EventBits_t xEventGroupGetBitsFromISR( EventGroupHandle_t xEventGroup )
+{
+UBaseType_t uxSavedInterruptStatus;
+EventGroup_t const * const pxEventBits = xEventGroup;
+EventBits_t uxReturn;
+
+	uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+	{
+		uxReturn = pxEventBits->uxEventBits;
+	}
+	portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+	return uxReturn;
+} /*lint !e818 EventGroupHandle_t is a typedef used in other functions to so can't be pointer to const. */
+/*-----------------------------------------------------------*/
+
+EventBits_t xEventGroupSetBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet )
+{
+ListItem_t *pxListItem, *pxNext;
+ListItem_t const *pxListEnd;
+List_t const * pxList;
+EventBits_t uxBitsToClear = 0, uxBitsWaitedFor, uxControlBits;
+EventGroup_t *pxEventBits = xEventGroup;
+BaseType_t xMatchFound = pdFALSE;
+
+	/* Check the user is not attempting to set the bits used by the kernel
+	itself. */
+	configASSERT( xEventGroup );
+	configASSERT( ( uxBitsToSet & eventEVENT_BITS_CONTROL_BYTES ) == 0 );
+
+	pxList = &( pxEventBits->xTasksWaitingForBits );
+	pxListEnd = listGET_END_MARKER( pxList ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM.  This is checked and valid. */
+	vTaskSuspendAll();
+	{
+		traceEVENT_GROUP_SET_BITS( xEventGroup, uxBitsToSet );
+
+		pxListItem = listGET_HEAD_ENTRY( pxList );
+
+		/* Set the bits. */
+		pxEventBits->uxEventBits |= uxBitsToSet;
+
+		/* See if the new bit value should unblock any tasks. */
+		while( pxListItem != pxListEnd )
+		{
+			pxNext = listGET_NEXT( pxListItem );
+			uxBitsWaitedFor = listGET_LIST_ITEM_VALUE( pxListItem );
+			xMatchFound = pdFALSE;
+
+			/* Split the bits waited for from the control bits. */
+			uxControlBits = uxBitsWaitedFor & eventEVENT_BITS_CONTROL_BYTES;
+			uxBitsWaitedFor &= ~eventEVENT_BITS_CONTROL_BYTES;
+
+			if( ( uxControlBits & eventWAIT_FOR_ALL_BITS ) == ( EventBits_t ) 0 )
+			{
+				/* Just looking for single bit being set. */
+				if( ( uxBitsWaitedFor & pxEventBits->uxEventBits ) != ( EventBits_t ) 0 )
+				{
+					xMatchFound = pdTRUE;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else if( ( uxBitsWaitedFor & pxEventBits->uxEventBits ) == uxBitsWaitedFor )
+			{
+				/* All bits are set. */
+				xMatchFound = pdTRUE;
+			}
+			else
+			{
+				/* Need all bits to be set, but not all the bits were set. */
+			}
+
+			if( xMatchFound != pdFALSE )
+			{
+				/* The bits match.  Should the bits be cleared on exit? */
+				if( ( uxControlBits & eventCLEAR_EVENTS_ON_EXIT_BIT ) != ( EventBits_t ) 0 )
+				{
+					uxBitsToClear |= uxBitsWaitedFor;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+
+				/* Store the actual event flag value in the task's event list
+				item before removing the task from the event list.  The
+				eventUNBLOCKED_DUE_TO_BIT_SET bit is set so the task knows
+				that is was unblocked due to its required bits matching, rather
+				than because it timed out. */
+				vTaskRemoveFromUnorderedEventList( pxListItem, pxEventBits->uxEventBits | eventUNBLOCKED_DUE_TO_BIT_SET );
+			}
+
+			/* Move onto the next list item.  Note pxListItem->pxNext is not
+			used here as the list item may have been removed from the event list
+			and inserted into the ready/pending reading list. */
+			pxListItem = pxNext;
+		}
+
+		/* Clear any bits that matched when the eventCLEAR_EVENTS_ON_EXIT_BIT
+		bit was set in the control word. */
+		pxEventBits->uxEventBits &= ~uxBitsToClear;
+	}
+	( void ) xTaskResumeAll();
+
+	return pxEventBits->uxEventBits;
+}
+/*-----------------------------------------------------------*/
+
+void vEventGroupDelete( EventGroupHandle_t xEventGroup )
+{
+EventGroup_t *pxEventBits = xEventGroup;
+const List_t *pxTasksWaitingForBits = &( pxEventBits->xTasksWaitingForBits );
+
+	vTaskSuspendAll();
+	{
+		traceEVENT_GROUP_DELETE( xEventGroup );
+
+		while( listCURRENT_LIST_LENGTH( pxTasksWaitingForBits ) > ( UBaseType_t ) 0 )
+		{
+			/* Unblock the task, returning 0 as the event list is being deleted
+			and cannot therefore have any bits set. */
+			configASSERT( pxTasksWaitingForBits->xListEnd.pxNext != ( const ListItem_t * ) &( pxTasksWaitingForBits->xListEnd ) );
+			vTaskRemoveFromUnorderedEventList( pxTasksWaitingForBits->xListEnd.pxNext, eventUNBLOCKED_DUE_TO_BIT_SET );
+		}
+
+		#if( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 0 ) )
+		{
+			/* The event group can only have been allocated dynamically - free
+			it again. */
+			vPortFree( pxEventBits );
+		}
+		#elif( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
+		{
+			/* The event group could have been allocated statically or
+			dynamically, so check before attempting to free the memory. */
+			if( pxEventBits->ucStaticallyAllocated == ( uint8_t ) pdFALSE )
+			{
+				vPortFree( pxEventBits );
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+	}
+	( void ) xTaskResumeAll();
+}
+/*-----------------------------------------------------------*/
+
+/* For internal use only - execute a 'set bits' command that was pended from
+an interrupt. */
+void vEventGroupSetBitsCallback( void *pvEventGroup, const uint32_t ulBitsToSet )
+{
+	( void ) xEventGroupSetBits( pvEventGroup, ( EventBits_t ) ulBitsToSet ); /*lint !e9079 Can't avoid cast to void* as a generic timer callback prototype. Callback casts back to original type so safe. */
+}
+/*-----------------------------------------------------------*/
+
+/* For internal use only - execute a 'clear bits' command that was pended from
+an interrupt. */
+void vEventGroupClearBitsCallback( void *pvEventGroup, const uint32_t ulBitsToClear )
+{
+	( void ) xEventGroupClearBits( pvEventGroup, ( EventBits_t ) ulBitsToClear ); /*lint !e9079 Can't avoid cast to void* as a generic timer callback prototype. Callback casts back to original type so safe. */
+}
+/*-----------------------------------------------------------*/
+
+static BaseType_t prvTestWaitCondition( const EventBits_t uxCurrentEventBits, const EventBits_t uxBitsToWaitFor, const BaseType_t xWaitForAllBits )
+{
+BaseType_t xWaitConditionMet = pdFALSE;
+
+	if( xWaitForAllBits == pdFALSE )
+	{
+		/* Task only has to wait for one bit within uxBitsToWaitFor to be
+		set.  Is one already set? */
+		if( ( uxCurrentEventBits & uxBitsToWaitFor ) != ( EventBits_t ) 0 )
+		{
+			xWaitConditionMet = pdTRUE;
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	else
+	{
+		/* Task has to wait for all the bits in uxBitsToWaitFor to be set.
+		Are they set already? */
+		if( ( uxCurrentEventBits & uxBitsToWaitFor ) == uxBitsToWaitFor )
+		{
+			xWaitConditionMet = pdTRUE;
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+
+	return xWaitConditionMet;
+}
+/*-----------------------------------------------------------*/
+
+#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) )
+
+	BaseType_t xEventGroupSetBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, BaseType_t *pxHigherPriorityTaskWoken )
+	{
+	BaseType_t xReturn;
+
+		traceEVENT_GROUP_SET_BITS_FROM_ISR( xEventGroup, uxBitsToSet );
+		xReturn = xTimerPendFunctionCallFromISR( vEventGroupSetBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToSet, pxHigherPriorityTaskWoken ); /*lint !e9087 Can't avoid cast to void* as a generic callback function not specific to this use case. Callback casts back to original type so safe. */
+
+		return xReturn;
+	}
+
+#endif
+/*-----------------------------------------------------------*/
+
+#if (configUSE_TRACE_FACILITY == 1)
+
+	UBaseType_t uxEventGroupGetNumber( void* xEventGroup )
+	{
+	UBaseType_t xReturn;
+	EventGroup_t const *pxEventBits = ( EventGroup_t * ) xEventGroup; /*lint !e9087 !e9079 EventGroupHandle_t is a pointer to an EventGroup_t, but EventGroupHandle_t is kept opaque outside of this file for data hiding purposes. */
+
+		if( xEventGroup == NULL )
+		{
+			xReturn = 0;
+		}
+		else
+		{
+			xReturn = pxEventBits->uxEventGroupNumber;
+		}
+
+		return xReturn;
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	void vEventGroupSetNumber( void * xEventGroup, UBaseType_t uxEventGroupNumber )
+	{
+		( ( EventGroup_t * ) xEventGroup )->uxEventGroupNumber = uxEventGroupNumber; /*lint !e9087 !e9079 EventGroupHandle_t is a pointer to an EventGroup_t, but EventGroupHandle_t is kept opaque outside of this file for data hiding purposes. */
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h b/Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h
new file mode 100644
index 0000000..ceb469a
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h
@@ -0,0 +1,1295 @@
+/*
+ * FreeRTOS Kernel V10.3.1
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef INC_FREERTOS_H
+#define INC_FREERTOS_H
+
+/*
+ * Include the generic headers required for the FreeRTOS port being used.
+ */
+#include <stddef.h>
+
+/*
+ * If stdint.h cannot be located then:
+ *   + If using GCC ensure the -nostdint options is *not* being used.
+ *   + Ensure the project's include path includes the directory in which your
+ *     compiler stores stdint.h.
+ *   + Set any compiler options necessary for it to support C99, as technically
+ *     stdint.h is only mandatory with C99 (FreeRTOS does not require C99 in any
+ *     other way).
+ *   + The FreeRTOS download includes a simple stdint.h definition that can be
+ *     used in cases where none is provided by the compiler.  The files only
+ *     contains the typedefs required to build FreeRTOS.  Read the instructions
+ *     in FreeRTOS/source/stdint.readme for more information.
+ */
+#include <stdint.h> /* READ COMMENT ABOVE. */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Application specific configuration options. */
+#include "FreeRTOSConfig.h"
+
+/* Basic FreeRTOS definitions. */
+#include "projdefs.h"
+
+/* Definitions specific to the port being used. */
+#include "portable.h"
+
+/* Must be defaulted before configUSE_NEWLIB_REENTRANT is used below. */
+#ifndef configUSE_NEWLIB_REENTRANT
+	#define configUSE_NEWLIB_REENTRANT 0
+#endif
+
+/* Required if struct _reent is used. */
+#if ( configUSE_NEWLIB_REENTRANT == 1 )
+	#include <reent.h>
+#endif
+/*
+ * Check all the required application specific macros have been defined.
+ * These macros are application specific and (as downloaded) are defined
+ * within FreeRTOSConfig.h.
+ */
+
+#ifndef configMINIMAL_STACK_SIZE
+	#error Missing definition:  configMINIMAL_STACK_SIZE must be defined in FreeRTOSConfig.h.  configMINIMAL_STACK_SIZE defines the size (in words) of the stack allocated to the idle task.  Refer to the demo project provided for your port for a suitable value.
+#endif
+
+#ifndef configMAX_PRIORITIES
+	#error Missing definition:  configMAX_PRIORITIES must be defined in FreeRTOSConfig.h.  See the Configuration section of the FreeRTOS API documentation for details.
+#endif
+
+#if configMAX_PRIORITIES < 1
+	#error configMAX_PRIORITIES must be defined to be greater than or equal to 1.
+#endif
+
+#ifndef configUSE_PREEMPTION
+	#error Missing definition:  configUSE_PREEMPTION must be defined in FreeRTOSConfig.h as either 1 or 0.  See the Configuration section of the FreeRTOS API documentation for details.
+#endif
+
+#ifndef configUSE_IDLE_HOOK
+	#error Missing definition:  configUSE_IDLE_HOOK must be defined in FreeRTOSConfig.h as either 1 or 0.  See the Configuration section of the FreeRTOS API documentation for details.
+#endif
+
+#ifndef configUSE_TICK_HOOK
+	#error Missing definition:  configUSE_TICK_HOOK must be defined in FreeRTOSConfig.h as either 1 or 0.  See the Configuration section of the FreeRTOS API documentation for details.
+#endif
+
+#ifndef configUSE_16_BIT_TICKS
+	#error Missing definition:  configUSE_16_BIT_TICKS must be defined in FreeRTOSConfig.h as either 1 or 0.  See the Configuration section of the FreeRTOS API documentation for details.
+#endif
+
+#ifndef configUSE_CO_ROUTINES
+	#define configUSE_CO_ROUTINES 0
+#endif
+
+#ifndef INCLUDE_vTaskPrioritySet
+	#define INCLUDE_vTaskPrioritySet 0
+#endif
+
+#ifndef INCLUDE_uxTaskPriorityGet
+	#define INCLUDE_uxTaskPriorityGet 0
+#endif
+
+#ifndef INCLUDE_vTaskDelete
+	#define INCLUDE_vTaskDelete 0
+#endif
+
+#ifndef INCLUDE_vTaskSuspend
+	#define INCLUDE_vTaskSuspend 0
+#endif
+
+#ifndef INCLUDE_vTaskDelayUntil
+	#define INCLUDE_vTaskDelayUntil 0
+#endif
+
+#ifndef INCLUDE_vTaskDelay
+	#define INCLUDE_vTaskDelay 0
+#endif
+
+#ifndef INCLUDE_xTaskGetIdleTaskHandle
+	#define INCLUDE_xTaskGetIdleTaskHandle 0
+#endif
+
+#ifndef INCLUDE_xTaskAbortDelay
+	#define INCLUDE_xTaskAbortDelay 0
+#endif
+
+#ifndef INCLUDE_xQueueGetMutexHolder
+	#define INCLUDE_xQueueGetMutexHolder 0
+#endif
+
+#ifndef INCLUDE_xSemaphoreGetMutexHolder
+	#define INCLUDE_xSemaphoreGetMutexHolder INCLUDE_xQueueGetMutexHolder
+#endif
+
+#ifndef INCLUDE_xTaskGetHandle
+	#define INCLUDE_xTaskGetHandle 0
+#endif
+
+#ifndef INCLUDE_uxTaskGetStackHighWaterMark
+	#define INCLUDE_uxTaskGetStackHighWaterMark 0
+#endif
+
+#ifndef INCLUDE_uxTaskGetStackHighWaterMark2
+	#define INCLUDE_uxTaskGetStackHighWaterMark2 0
+#endif
+
+#ifndef INCLUDE_eTaskGetState
+	#define INCLUDE_eTaskGetState 0
+#endif
+
+#ifndef INCLUDE_xTaskResumeFromISR
+	#define INCLUDE_xTaskResumeFromISR 1
+#endif
+
+#ifndef INCLUDE_xTimerPendFunctionCall
+	#define INCLUDE_xTimerPendFunctionCall 0
+#endif
+
+#ifndef INCLUDE_xTaskGetSchedulerState
+	#define INCLUDE_xTaskGetSchedulerState 0
+#endif
+
+#ifndef INCLUDE_xTaskGetCurrentTaskHandle
+	#define INCLUDE_xTaskGetCurrentTaskHandle 0
+#endif
+
+#if configUSE_CO_ROUTINES != 0
+	#ifndef configMAX_CO_ROUTINE_PRIORITIES
+		#error configMAX_CO_ROUTINE_PRIORITIES must be greater than or equal to 1.
+	#endif
+#endif
+
+#ifndef configUSE_DAEMON_TASK_STARTUP_HOOK
+	#define configUSE_DAEMON_TASK_STARTUP_HOOK 0
+#endif
+
+#ifndef configUSE_APPLICATION_TASK_TAG
+	#define configUSE_APPLICATION_TASK_TAG 0
+#endif
+
+#ifndef configNUM_THREAD_LOCAL_STORAGE_POINTERS
+	#define configNUM_THREAD_LOCAL_STORAGE_POINTERS 0
+#endif
+
+#ifndef configUSE_RECURSIVE_MUTEXES
+	#define configUSE_RECURSIVE_MUTEXES 0
+#endif
+
+#ifndef configUSE_MUTEXES
+	#define configUSE_MUTEXES 0
+#endif
+
+#ifndef configUSE_TIMERS
+	#define configUSE_TIMERS 0
+#endif
+
+#ifndef configUSE_COUNTING_SEMAPHORES
+	#define configUSE_COUNTING_SEMAPHORES 0
+#endif
+
+#ifndef configUSE_ALTERNATIVE_API
+	#define configUSE_ALTERNATIVE_API 0
+#endif
+
+#ifndef portCRITICAL_NESTING_IN_TCB
+	#define portCRITICAL_NESTING_IN_TCB 0
+#endif
+
+#ifndef configMAX_TASK_NAME_LEN
+	#define configMAX_TASK_NAME_LEN 16
+#endif
+
+#ifndef configIDLE_SHOULD_YIELD
+	#define configIDLE_SHOULD_YIELD		1
+#endif
+
+#if configMAX_TASK_NAME_LEN < 1
+	#error configMAX_TASK_NAME_LEN must be set to a minimum of 1 in FreeRTOSConfig.h
+#endif
+
+#ifndef configASSERT
+	#define configASSERT( x )
+	#define configASSERT_DEFINED 0
+#else
+	#define configASSERT_DEFINED 1
+#endif
+
+/* configPRECONDITION should be defined as configASSERT.
+The CBMC proofs need a way to track assumptions and assertions.
+A configPRECONDITION statement should express an implicit invariant or
+assumption made.  A configASSERT statement should express an invariant that must
+hold explicit before calling the code. */
+#ifndef configPRECONDITION
+	#define configPRECONDITION( X ) configASSERT(X)
+	#define configPRECONDITION_DEFINED 0
+#else
+	#define configPRECONDITION_DEFINED 1
+#endif
+
+#ifndef portMEMORY_BARRIER
+	#define portMEMORY_BARRIER()
+#endif
+
+#ifndef portSOFTWARE_BARRIER
+	#define portSOFTWARE_BARRIER()
+#endif
+
+/* The timers module relies on xTaskGetSchedulerState(). */
+#if configUSE_TIMERS == 1
+
+	#ifndef configTIMER_TASK_PRIORITY
+		#error If configUSE_TIMERS is set to 1 then configTIMER_TASK_PRIORITY must also be defined.
+	#endif /* configTIMER_TASK_PRIORITY */
+
+	#ifndef configTIMER_QUEUE_LENGTH
+		#error If configUSE_TIMERS is set to 1 then configTIMER_QUEUE_LENGTH must also be defined.
+	#endif /* configTIMER_QUEUE_LENGTH */
+
+	#ifndef configTIMER_TASK_STACK_DEPTH
+		#error If configUSE_TIMERS is set to 1 then configTIMER_TASK_STACK_DEPTH must also be defined.
+	#endif /* configTIMER_TASK_STACK_DEPTH */
+
+#endif /* configUSE_TIMERS */
+
+#ifndef portSET_INTERRUPT_MASK_FROM_ISR
+	#define portSET_INTERRUPT_MASK_FROM_ISR() 0
+#endif
+
+#ifndef portCLEAR_INTERRUPT_MASK_FROM_ISR
+	#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusValue ) ( void ) uxSavedStatusValue
+#endif
+
+#ifndef portCLEAN_UP_TCB
+	#define portCLEAN_UP_TCB( pxTCB ) ( void ) pxTCB
+#endif
+
+#ifndef portPRE_TASK_DELETE_HOOK
+	#define portPRE_TASK_DELETE_HOOK( pvTaskToDelete, pxYieldPending )
+#endif
+
+#ifndef portSETUP_TCB
+	#define portSETUP_TCB( pxTCB ) ( void ) pxTCB
+#endif
+
+#ifndef configQUEUE_REGISTRY_SIZE
+	#define configQUEUE_REGISTRY_SIZE 0U
+#endif
+
+#if ( configQUEUE_REGISTRY_SIZE < 1 )
+	#define vQueueAddToRegistry( xQueue, pcName )
+	#define vQueueUnregisterQueue( xQueue )
+	#define pcQueueGetName( xQueue )
+#endif
+
+#ifndef portPOINTER_SIZE_TYPE
+	#define portPOINTER_SIZE_TYPE uint32_t
+#endif
+
+/* Remove any unused trace macros. */
+#ifndef traceSTART
+	/* Used to perform any necessary initialisation - for example, open a file
+	into which trace is to be written. */
+	#define traceSTART()
+#endif
+
+#ifndef traceEND
+	/* Use to close a trace, for example close a file into which trace has been
+	written. */
+	#define traceEND()
+#endif
+
+#ifndef traceTASK_SWITCHED_IN
+	/* Called after a task has been selected to run.  pxCurrentTCB holds a pointer
+	to the task control block of the selected task. */
+	#define traceTASK_SWITCHED_IN()
+#endif
+
+#ifndef traceINCREASE_TICK_COUNT
+	/* Called before stepping the tick count after waking from tickless idle
+	sleep. */
+	#define traceINCREASE_TICK_COUNT( x )
+#endif
+
+#ifndef traceLOW_POWER_IDLE_BEGIN
+	/* Called immediately before entering tickless idle. */
+	#define traceLOW_POWER_IDLE_BEGIN()
+#endif
+
+#ifndef	traceLOW_POWER_IDLE_END
+	/* Called when returning to the Idle task after a tickless idle. */
+	#define traceLOW_POWER_IDLE_END()
+#endif
+
+#ifndef traceTASK_SWITCHED_OUT
+	/* Called before a task has been selected to run.  pxCurrentTCB holds a pointer
+	to the task control block of the task being switched out. */
+	#define traceTASK_SWITCHED_OUT()
+#endif
+
+#ifndef traceTASK_PRIORITY_INHERIT
+	/* Called when a task attempts to take a mutex that is already held by a
+	lower priority task.  pxTCBOfMutexHolder is a pointer to the TCB of the task
+	that holds the mutex.  uxInheritedPriority is the priority the mutex holder
+	will inherit (the priority of the task that is attempting to obtain the
+	muted. */
+	#define traceTASK_PRIORITY_INHERIT( pxTCBOfMutexHolder, uxInheritedPriority )
+#endif
+
+#ifndef traceTASK_PRIORITY_DISINHERIT
+	/* Called when a task releases a mutex, the holding of which had resulted in
+	the task inheriting the priority of a higher priority task.
+	pxTCBOfMutexHolder is a pointer to the TCB of the task that is releasing the
+	mutex.  uxOriginalPriority is the task's configured (base) priority. */
+	#define traceTASK_PRIORITY_DISINHERIT( pxTCBOfMutexHolder, uxOriginalPriority )
+#endif
+
+#ifndef traceBLOCKING_ON_QUEUE_RECEIVE
+	/* Task is about to block because it cannot read from a
+	queue/mutex/semaphore.  pxQueue is a pointer to the queue/mutex/semaphore
+	upon which the read was attempted.  pxCurrentTCB points to the TCB of the
+	task that attempted the read. */
+	#define traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue )
+#endif
+
+#ifndef traceBLOCKING_ON_QUEUE_PEEK
+	/* Task is about to block because it cannot read from a
+	queue/mutex/semaphore.  pxQueue is a pointer to the queue/mutex/semaphore
+	upon which the read was attempted.  pxCurrentTCB points to the TCB of the
+	task that attempted the read. */
+	#define traceBLOCKING_ON_QUEUE_PEEK( pxQueue )
+#endif
+
+#ifndef traceBLOCKING_ON_QUEUE_SEND
+	/* Task is about to block because it cannot write to a
+	queue/mutex/semaphore.  pxQueue is a pointer to the queue/mutex/semaphore
+	upon which the write was attempted.  pxCurrentTCB points to the TCB of the
+	task that attempted the write. */
+	#define traceBLOCKING_ON_QUEUE_SEND( pxQueue )
+#endif
+
+#ifndef configCHECK_FOR_STACK_OVERFLOW
+	#define configCHECK_FOR_STACK_OVERFLOW 0
+#endif
+
+#ifndef configRECORD_STACK_HIGH_ADDRESS
+	#define configRECORD_STACK_HIGH_ADDRESS 0
+#endif
+
+#ifndef configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H
+	#define configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H 0
+#endif
+
+/* The following event macros are embedded in the kernel API calls. */
+
+#ifndef traceMOVED_TASK_TO_READY_STATE
+	#define traceMOVED_TASK_TO_READY_STATE( pxTCB )
+#endif
+
+#ifndef tracePOST_MOVED_TASK_TO_READY_STATE
+	#define tracePOST_MOVED_TASK_TO_READY_STATE( pxTCB )
+#endif
+
+#ifndef traceQUEUE_CREATE
+	#define traceQUEUE_CREATE( pxNewQueue )
+#endif
+
+#ifndef traceQUEUE_CREATE_FAILED
+	#define traceQUEUE_CREATE_FAILED( ucQueueType )
+#endif
+
+#ifndef traceCREATE_MUTEX
+	#define traceCREATE_MUTEX( pxNewQueue )
+#endif
+
+#ifndef traceCREATE_MUTEX_FAILED
+	#define traceCREATE_MUTEX_FAILED()
+#endif
+
+#ifndef traceGIVE_MUTEX_RECURSIVE
+	#define traceGIVE_MUTEX_RECURSIVE( pxMutex )
+#endif
+
+#ifndef traceGIVE_MUTEX_RECURSIVE_FAILED
+	#define traceGIVE_MUTEX_RECURSIVE_FAILED( pxMutex )
+#endif
+
+#ifndef traceTAKE_MUTEX_RECURSIVE
+	#define traceTAKE_MUTEX_RECURSIVE( pxMutex )
+#endif
+
+#ifndef traceTAKE_MUTEX_RECURSIVE_FAILED
+	#define traceTAKE_MUTEX_RECURSIVE_FAILED( pxMutex )
+#endif
+
+#ifndef traceCREATE_COUNTING_SEMAPHORE
+	#define traceCREATE_COUNTING_SEMAPHORE()
+#endif
+
+#ifndef traceCREATE_COUNTING_SEMAPHORE_FAILED
+	#define traceCREATE_COUNTING_SEMAPHORE_FAILED()
+#endif
+
+#ifndef traceQUEUE_SEND
+	#define traceQUEUE_SEND( pxQueue )
+#endif
+
+#ifndef traceQUEUE_SEND_FAILED
+	#define traceQUEUE_SEND_FAILED( pxQueue )
+#endif
+
+#ifndef traceQUEUE_RECEIVE
+	#define traceQUEUE_RECEIVE( pxQueue )
+#endif
+
+#ifndef traceQUEUE_PEEK
+	#define traceQUEUE_PEEK( pxQueue )
+#endif
+
+#ifndef traceQUEUE_PEEK_FAILED
+	#define traceQUEUE_PEEK_FAILED( pxQueue )
+#endif
+
+#ifndef traceQUEUE_PEEK_FROM_ISR
+	#define traceQUEUE_PEEK_FROM_ISR( pxQueue )
+#endif
+
+#ifndef traceQUEUE_RECEIVE_FAILED
+	#define traceQUEUE_RECEIVE_FAILED( pxQueue )
+#endif
+
+#ifndef traceQUEUE_SEND_FROM_ISR
+	#define traceQUEUE_SEND_FROM_ISR( pxQueue )
+#endif
+
+#ifndef traceQUEUE_SEND_FROM_ISR_FAILED
+	#define traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue )
+#endif
+
+#ifndef traceQUEUE_RECEIVE_FROM_ISR
+	#define traceQUEUE_RECEIVE_FROM_ISR( pxQueue )
+#endif
+
+#ifndef traceQUEUE_RECEIVE_FROM_ISR_FAILED
+	#define traceQUEUE_RECEIVE_FROM_ISR_FAILED( pxQueue )
+#endif
+
+#ifndef traceQUEUE_PEEK_FROM_ISR_FAILED
+	#define traceQUEUE_PEEK_FROM_ISR_FAILED( pxQueue )
+#endif
+
+#ifndef traceQUEUE_DELETE
+	#define traceQUEUE_DELETE( pxQueue )
+#endif
+
+#ifndef traceTASK_CREATE
+	#define traceTASK_CREATE( pxNewTCB )
+#endif
+
+#ifndef traceTASK_CREATE_FAILED
+	#define traceTASK_CREATE_FAILED()
+#endif
+
+#ifndef traceTASK_DELETE
+	#define traceTASK_DELETE( pxTaskToDelete )
+#endif
+
+#ifndef traceTASK_DELAY_UNTIL
+	#define traceTASK_DELAY_UNTIL( x )
+#endif
+
+#ifndef traceTASK_DELAY
+	#define traceTASK_DELAY()
+#endif
+
+#ifndef traceTASK_PRIORITY_SET
+	#define traceTASK_PRIORITY_SET( pxTask, uxNewPriority )
+#endif
+
+#ifndef traceTASK_SUSPEND
+	#define traceTASK_SUSPEND( pxTaskToSuspend )
+#endif
+
+#ifndef traceTASK_RESUME
+	#define traceTASK_RESUME( pxTaskToResume )
+#endif
+
+#ifndef traceTASK_RESUME_FROM_ISR
+	#define traceTASK_RESUME_FROM_ISR( pxTaskToResume )
+#endif
+
+#ifndef traceTASK_INCREMENT_TICK
+	#define traceTASK_INCREMENT_TICK( xTickCount )
+#endif
+
+#ifndef traceTIMER_CREATE
+	#define traceTIMER_CREATE( pxNewTimer )
+#endif
+
+#ifndef traceTIMER_CREATE_FAILED
+	#define traceTIMER_CREATE_FAILED()
+#endif
+
+#ifndef traceTIMER_COMMAND_SEND
+	#define traceTIMER_COMMAND_SEND( xTimer, xMessageID, xMessageValueValue, xReturn )
+#endif
+
+#ifndef traceTIMER_EXPIRED
+	#define traceTIMER_EXPIRED( pxTimer )
+#endif
+
+#ifndef traceTIMER_COMMAND_RECEIVED
+	#define traceTIMER_COMMAND_RECEIVED( pxTimer, xMessageID, xMessageValue )
+#endif
+
+#ifndef traceMALLOC
+    #define traceMALLOC( pvAddress, uiSize )
+#endif
+
+#ifndef traceFREE
+    #define traceFREE( pvAddress, uiSize )
+#endif
+
+#ifndef traceEVENT_GROUP_CREATE
+	#define traceEVENT_GROUP_CREATE( xEventGroup )
+#endif
+
+#ifndef traceEVENT_GROUP_CREATE_FAILED
+	#define traceEVENT_GROUP_CREATE_FAILED()
+#endif
+
+#ifndef traceEVENT_GROUP_SYNC_BLOCK
+	#define traceEVENT_GROUP_SYNC_BLOCK( xEventGroup, uxBitsToSet, uxBitsToWaitFor )
+#endif
+
+#ifndef traceEVENT_GROUP_SYNC_END
+	#define traceEVENT_GROUP_SYNC_END( xEventGroup, uxBitsToSet, uxBitsToWaitFor, xTimeoutOccurred ) ( void ) xTimeoutOccurred
+#endif
+
+#ifndef traceEVENT_GROUP_WAIT_BITS_BLOCK
+	#define traceEVENT_GROUP_WAIT_BITS_BLOCK( xEventGroup, uxBitsToWaitFor )
+#endif
+
+#ifndef traceEVENT_GROUP_WAIT_BITS_END
+	#define traceEVENT_GROUP_WAIT_BITS_END( xEventGroup, uxBitsToWaitFor, xTimeoutOccurred ) ( void ) xTimeoutOccurred
+#endif
+
+#ifndef traceEVENT_GROUP_CLEAR_BITS
+	#define traceEVENT_GROUP_CLEAR_BITS( xEventGroup, uxBitsToClear )
+#endif
+
+#ifndef traceEVENT_GROUP_CLEAR_BITS_FROM_ISR
+	#define traceEVENT_GROUP_CLEAR_BITS_FROM_ISR( xEventGroup, uxBitsToClear )
+#endif
+
+#ifndef traceEVENT_GROUP_SET_BITS
+	#define traceEVENT_GROUP_SET_BITS( xEventGroup, uxBitsToSet )
+#endif
+
+#ifndef traceEVENT_GROUP_SET_BITS_FROM_ISR
+	#define traceEVENT_GROUP_SET_BITS_FROM_ISR( xEventGroup, uxBitsToSet )
+#endif
+
+#ifndef traceEVENT_GROUP_DELETE
+	#define traceEVENT_GROUP_DELETE( xEventGroup )
+#endif
+
+#ifndef tracePEND_FUNC_CALL
+	#define tracePEND_FUNC_CALL(xFunctionToPend, pvParameter1, ulParameter2, ret)
+#endif
+
+#ifndef tracePEND_FUNC_CALL_FROM_ISR
+	#define tracePEND_FUNC_CALL_FROM_ISR(xFunctionToPend, pvParameter1, ulParameter2, ret)
+#endif
+
+#ifndef traceQUEUE_REGISTRY_ADD
+	#define traceQUEUE_REGISTRY_ADD(xQueue, pcQueueName)
+#endif
+
+#ifndef traceTASK_NOTIFY_TAKE_BLOCK
+	#define traceTASK_NOTIFY_TAKE_BLOCK()
+#endif
+
+#ifndef traceTASK_NOTIFY_TAKE
+	#define traceTASK_NOTIFY_TAKE()
+#endif
+
+#ifndef traceTASK_NOTIFY_WAIT_BLOCK
+	#define traceTASK_NOTIFY_WAIT_BLOCK()
+#endif
+
+#ifndef traceTASK_NOTIFY_WAIT
+	#define traceTASK_NOTIFY_WAIT()
+#endif
+
+#ifndef traceTASK_NOTIFY
+	#define traceTASK_NOTIFY()
+#endif
+
+#ifndef traceTASK_NOTIFY_FROM_ISR
+	#define traceTASK_NOTIFY_FROM_ISR()
+#endif
+
+#ifndef traceTASK_NOTIFY_GIVE_FROM_ISR
+	#define traceTASK_NOTIFY_GIVE_FROM_ISR()
+#endif
+
+#ifndef traceSTREAM_BUFFER_CREATE_FAILED
+	#define traceSTREAM_BUFFER_CREATE_FAILED( xIsMessageBuffer )
+#endif
+
+#ifndef traceSTREAM_BUFFER_CREATE_STATIC_FAILED
+	#define traceSTREAM_BUFFER_CREATE_STATIC_FAILED( xReturn, xIsMessageBuffer )
+#endif
+
+#ifndef traceSTREAM_BUFFER_CREATE
+	#define traceSTREAM_BUFFER_CREATE( pxStreamBuffer, xIsMessageBuffer )
+#endif
+
+#ifndef traceSTREAM_BUFFER_DELETE
+	#define traceSTREAM_BUFFER_DELETE( xStreamBuffer )
+#endif
+
+#ifndef traceSTREAM_BUFFER_RESET
+	#define traceSTREAM_BUFFER_RESET( xStreamBuffer )
+#endif
+
+#ifndef traceBLOCKING_ON_STREAM_BUFFER_SEND
+	#define traceBLOCKING_ON_STREAM_BUFFER_SEND( xStreamBuffer )
+#endif
+
+#ifndef traceSTREAM_BUFFER_SEND
+	#define traceSTREAM_BUFFER_SEND( xStreamBuffer, xBytesSent )
+#endif
+
+#ifndef traceSTREAM_BUFFER_SEND_FAILED
+	#define traceSTREAM_BUFFER_SEND_FAILED( xStreamBuffer )
+#endif
+
+#ifndef traceSTREAM_BUFFER_SEND_FROM_ISR
+	#define traceSTREAM_BUFFER_SEND_FROM_ISR( xStreamBuffer, xBytesSent )
+#endif
+
+#ifndef traceBLOCKING_ON_STREAM_BUFFER_RECEIVE
+	#define traceBLOCKING_ON_STREAM_BUFFER_RECEIVE( xStreamBuffer )
+#endif
+
+#ifndef traceSTREAM_BUFFER_RECEIVE
+	#define traceSTREAM_BUFFER_RECEIVE( xStreamBuffer, xReceivedLength )
+#endif
+
+#ifndef traceSTREAM_BUFFER_RECEIVE_FAILED
+	#define traceSTREAM_BUFFER_RECEIVE_FAILED( xStreamBuffer )
+#endif
+
+#ifndef traceSTREAM_BUFFER_RECEIVE_FROM_ISR
+	#define traceSTREAM_BUFFER_RECEIVE_FROM_ISR( xStreamBuffer, xReceivedLength )
+#endif
+
+#ifndef configGENERATE_RUN_TIME_STATS
+	#define configGENERATE_RUN_TIME_STATS 0
+#endif
+
+#if ( configGENERATE_RUN_TIME_STATS == 1 )
+
+	#ifndef portCONFIGURE_TIMER_FOR_RUN_TIME_STATS
+		#error If configGENERATE_RUN_TIME_STATS is defined then portCONFIGURE_TIMER_FOR_RUN_TIME_STATS must also be defined.  portCONFIGURE_TIMER_FOR_RUN_TIME_STATS should call a port layer function to setup a peripheral timer/counter that can then be used as the run time counter time base.
+	#endif /* portCONFIGURE_TIMER_FOR_RUN_TIME_STATS */
+
+	#ifndef portGET_RUN_TIME_COUNTER_VALUE
+		#ifndef portALT_GET_RUN_TIME_COUNTER_VALUE
+			#error If configGENERATE_RUN_TIME_STATS is defined then either portGET_RUN_TIME_COUNTER_VALUE or portALT_GET_RUN_TIME_COUNTER_VALUE must also be defined.  See the examples provided and the FreeRTOS web site for more information.
+		#endif /* portALT_GET_RUN_TIME_COUNTER_VALUE */
+	#endif /* portGET_RUN_TIME_COUNTER_VALUE */
+
+#endif /* configGENERATE_RUN_TIME_STATS */
+
+#ifndef portCONFIGURE_TIMER_FOR_RUN_TIME_STATS
+	#define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS()
+#endif
+
+#ifndef configUSE_MALLOC_FAILED_HOOK
+	#define configUSE_MALLOC_FAILED_HOOK 0
+#endif
+
+#ifndef portPRIVILEGE_BIT
+	#define portPRIVILEGE_BIT ( ( UBaseType_t ) 0x00 )
+#endif
+
+#ifndef portYIELD_WITHIN_API
+	#define portYIELD_WITHIN_API portYIELD
+#endif
+
+#ifndef portSUPPRESS_TICKS_AND_SLEEP
+	#define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime )
+#endif
+
+#ifndef configEXPECTED_IDLE_TIME_BEFORE_SLEEP
+	#define configEXPECTED_IDLE_TIME_BEFORE_SLEEP 2
+#endif
+
+#if configEXPECTED_IDLE_TIME_BEFORE_SLEEP < 2
+	#error configEXPECTED_IDLE_TIME_BEFORE_SLEEP must not be less than 2
+#endif
+
+#ifndef configUSE_TICKLESS_IDLE
+	#define configUSE_TICKLESS_IDLE 0
+#endif
+
+#ifndef configPRE_SUPPRESS_TICKS_AND_SLEEP_PROCESSING
+	#define configPRE_SUPPRESS_TICKS_AND_SLEEP_PROCESSING( x )
+#endif
+
+#ifndef configPRE_SLEEP_PROCESSING
+	#define configPRE_SLEEP_PROCESSING( x )
+#endif
+
+#ifndef configPOST_SLEEP_PROCESSING
+	#define configPOST_SLEEP_PROCESSING( x )
+#endif
+
+#ifndef configUSE_QUEUE_SETS
+	#define configUSE_QUEUE_SETS 0
+#endif
+
+#ifndef portTASK_USES_FLOATING_POINT
+	#define portTASK_USES_FLOATING_POINT()
+#endif
+
+#ifndef portALLOCATE_SECURE_CONTEXT
+	#define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )
+#endif
+
+#ifndef portDONT_DISCARD
+	#define portDONT_DISCARD
+#endif
+
+#ifndef configUSE_TIME_SLICING
+	#define configUSE_TIME_SLICING 1
+#endif
+
+#ifndef configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS
+	#define configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS 0
+#endif
+
+#ifndef configUSE_STATS_FORMATTING_FUNCTIONS
+	#define configUSE_STATS_FORMATTING_FUNCTIONS 0
+#endif
+
+#ifndef portASSERT_IF_INTERRUPT_PRIORITY_INVALID
+	#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()
+#endif
+
+#ifndef configUSE_TRACE_FACILITY
+	#define configUSE_TRACE_FACILITY 0
+#endif
+
+#ifndef mtCOVERAGE_TEST_MARKER
+	#define mtCOVERAGE_TEST_MARKER()
+#endif
+
+#ifndef mtCOVERAGE_TEST_DELAY
+	#define mtCOVERAGE_TEST_DELAY()
+#endif
+
+#ifndef portASSERT_IF_IN_ISR
+	#define portASSERT_IF_IN_ISR()
+#endif
+
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+	#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+#endif
+
+#ifndef configAPPLICATION_ALLOCATED_HEAP
+	#define configAPPLICATION_ALLOCATED_HEAP 0
+#endif
+
+#ifndef configUSE_TASK_NOTIFICATIONS
+	#define configUSE_TASK_NOTIFICATIONS 1
+#endif
+
+#ifndef configUSE_POSIX_ERRNO
+	#define configUSE_POSIX_ERRNO 0
+#endif
+
+#ifndef portTICK_TYPE_IS_ATOMIC
+	#define portTICK_TYPE_IS_ATOMIC 0
+#endif
+
+#ifndef configSUPPORT_STATIC_ALLOCATION
+	/* Defaults to 0 for backward compatibility. */
+	#define configSUPPORT_STATIC_ALLOCATION 0
+#endif
+
+#ifndef configSUPPORT_DYNAMIC_ALLOCATION
+	/* Defaults to 1 for backward compatibility. */
+	#define configSUPPORT_DYNAMIC_ALLOCATION 1
+#endif
+
+#ifndef configSTACK_DEPTH_TYPE
+	/* Defaults to uint16_t for backward compatibility, but can be overridden
+	in FreeRTOSConfig.h if uint16_t is too restrictive. */
+	#define configSTACK_DEPTH_TYPE uint16_t
+#endif
+
+#ifndef configMESSAGE_BUFFER_LENGTH_TYPE
+	/* Defaults to size_t for backward compatibility, but can be overridden
+	in FreeRTOSConfig.h if lengths will always be less than the number of bytes
+	in a size_t. */
+	#define configMESSAGE_BUFFER_LENGTH_TYPE size_t
+#endif
+
+/* Sanity check the configuration. */
+#if( configUSE_TICKLESS_IDLE != 0 )
+	#if( INCLUDE_vTaskSuspend != 1 )
+		#error INCLUDE_vTaskSuspend must be set to 1 if configUSE_TICKLESS_IDLE is not set to 0
+	#endif /* INCLUDE_vTaskSuspend */
+#endif /* configUSE_TICKLESS_IDLE */
+
+#if( ( configSUPPORT_STATIC_ALLOCATION == 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 0 ) )
+	#error configSUPPORT_STATIC_ALLOCATION and configSUPPORT_DYNAMIC_ALLOCATION cannot both be 0, but can both be 1.
+#endif
+
+#if( ( configUSE_RECURSIVE_MUTEXES == 1 ) && ( configUSE_MUTEXES != 1 ) )
+	#error configUSE_MUTEXES must be set to 1 to use recursive mutexes
+#endif
+
+#ifndef configINITIAL_TICK_COUNT
+	#define configINITIAL_TICK_COUNT 0
+#endif
+
+#if( portTICK_TYPE_IS_ATOMIC == 0 )
+	/* Either variables of tick type cannot be read atomically, or
+	portTICK_TYPE_IS_ATOMIC was not set - map the critical sections used when
+	the tick count is returned to the standard critical section macros. */
+	#define portTICK_TYPE_ENTER_CRITICAL() portENTER_CRITICAL()
+	#define portTICK_TYPE_EXIT_CRITICAL() portEXIT_CRITICAL()
+	#define portTICK_TYPE_SET_INTERRUPT_MASK_FROM_ISR() portSET_INTERRUPT_MASK_FROM_ISR()
+	#define portTICK_TYPE_CLEAR_INTERRUPT_MASK_FROM_ISR( x ) portCLEAR_INTERRUPT_MASK_FROM_ISR( ( x ) )
+#else
+	/* The tick type can be read atomically, so critical sections used when the
+	tick count is returned can be defined away. */
+	#define portTICK_TYPE_ENTER_CRITICAL()
+	#define portTICK_TYPE_EXIT_CRITICAL()
+	#define portTICK_TYPE_SET_INTERRUPT_MASK_FROM_ISR() 0
+	#define portTICK_TYPE_CLEAR_INTERRUPT_MASK_FROM_ISR( x ) ( void ) x
+#endif
+
+/* Definitions to allow backward compatibility with FreeRTOS versions prior to
+V8 if desired. */
+#ifndef configENABLE_BACKWARD_COMPATIBILITY
+	#define configENABLE_BACKWARD_COMPATIBILITY 1
+#endif
+
+#ifndef configPRINTF
+	/* configPRINTF() was not defined, so define it away to nothing.  To use
+	configPRINTF() then define it as follows (where MyPrintFunction() is
+	provided by the application writer):
+
+	void MyPrintFunction(const char *pcFormat, ... );
+	#define configPRINTF( X )   MyPrintFunction X
+
+	Then call like a standard printf() function, but placing brackets around
+	all parameters so they are passed as a single parameter.  For example:
+	configPRINTF( ("Value = %d", MyVariable) ); */
+	#define configPRINTF( X )
+#endif
+
+#ifndef configMAX
+	/* The application writer has not provided their own MAX macro, so define
+	the following generic implementation. */
+	#define configMAX( a, b ) ( ( ( a ) > ( b ) ) ? ( a ) : ( b ) )
+#endif
+
+#ifndef configMIN
+	/* The application writer has not provided their own MAX macro, so define
+	the following generic implementation. */
+	#define configMIN( a, b ) ( ( ( a ) < ( b ) ) ? ( a ) : ( b ) )
+#endif
+
+#if configENABLE_BACKWARD_COMPATIBILITY == 1
+	#define eTaskStateGet eTaskGetState
+	#define portTickType TickType_t
+	#define xTaskHandle TaskHandle_t
+	#define xQueueHandle QueueHandle_t
+	#define xSemaphoreHandle SemaphoreHandle_t
+	#define xQueueSetHandle QueueSetHandle_t
+	#define xQueueSetMemberHandle QueueSetMemberHandle_t
+	#define xTimeOutType TimeOut_t
+	#define xMemoryRegion MemoryRegion_t
+	#define xTaskParameters TaskParameters_t
+	#define xTaskStatusType	TaskStatus_t
+	#define xTimerHandle TimerHandle_t
+	#define xCoRoutineHandle CoRoutineHandle_t
+	#define pdTASK_HOOK_CODE TaskHookFunction_t
+	#define portTICK_RATE_MS portTICK_PERIOD_MS
+	#define pcTaskGetTaskName pcTaskGetName
+	#define pcTimerGetTimerName pcTimerGetName
+	#define pcQueueGetQueueName pcQueueGetName
+	#define vTaskGetTaskInfo vTaskGetInfo
+	#define xTaskGetIdleRunTimeCounter ulTaskGetIdleRunTimeCounter
+
+	/* Backward compatibility within the scheduler code only - these definitions
+	are not really required but are included for completeness. */
+	#define tmrTIMER_CALLBACK TimerCallbackFunction_t
+	#define pdTASK_CODE TaskFunction_t
+	#define xListItem ListItem_t
+	#define xList List_t
+
+	/* For libraries that break the list data hiding, and access list structure
+	members directly (which is not supposed to be done). */
+	#define pxContainer pvContainer
+#endif /* configENABLE_BACKWARD_COMPATIBILITY */
+
+#if( configUSE_ALTERNATIVE_API != 0 )
+	#error The alternative API was deprecated some time ago, and was removed in FreeRTOS V9.0 0
+#endif
+
+/* Set configUSE_TASK_FPU_SUPPORT to 0 to omit floating point support even
+if floating point hardware is otherwise supported by the FreeRTOS port in use.
+This constant is not supported by all FreeRTOS ports that include floating
+point support. */
+#ifndef configUSE_TASK_FPU_SUPPORT
+	#define configUSE_TASK_FPU_SUPPORT 1
+#endif
+
+/* Set configENABLE_MPU to 1 to enable MPU support and 0 to disable it. This is
+currently used in ARMv8M ports. */
+#ifndef configENABLE_MPU
+	#define configENABLE_MPU 0
+#endif
+
+/* Set configENABLE_FPU to 1 to enable FPU support and 0 to disable it. This is
+currently used in ARMv8M ports. */
+#ifndef configENABLE_FPU
+	#define configENABLE_FPU 1
+#endif
+
+/* Set configENABLE_TRUSTZONE to 1 enable TrustZone support and 0 to disable it.
+This is currently used in ARMv8M ports. */
+#ifndef configENABLE_TRUSTZONE
+	#define configENABLE_TRUSTZONE 1
+#endif
+
+/* Set configRUN_FREERTOS_SECURE_ONLY to 1 to run the FreeRTOS ARMv8M port on
+the Secure Side only. */
+#ifndef configRUN_FREERTOS_SECURE_ONLY
+	#define configRUN_FREERTOS_SECURE_ONLY 0
+#endif
+
+/* Sometimes the FreeRTOSConfig.h settings only allow a task to be created using
+ * dynamically allocated RAM, in which case when any task is deleted it is known
+ * that both the task's stack and TCB need to be freed.  Sometimes the
+ * FreeRTOSConfig.h settings only allow a task to be created using statically
+ * allocated RAM, in which case when any task is deleted it is known that neither
+ * the task's stack or TCB should be freed.  Sometimes the FreeRTOSConfig.h
+ * settings allow a task to be created using either statically or dynamically
+ * allocated RAM, in which case a member of the TCB is used to record whether the
+ * stack and/or TCB were allocated statically or dynamically, so when a task is
+ * deleted the RAM that was allocated dynamically is freed again and no attempt is
+ * made to free the RAM that was allocated statically.
+ * tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE is only true if it is possible for a
+ * task to be created using either statically or dynamically allocated RAM.  Note
+ * that if portUSING_MPU_WRAPPERS is 1 then a protected task can be created with
+ * a statically allocated stack and a dynamically allocated TCB.
+ *
+ * The following table lists various combinations of portUSING_MPU_WRAPPERS,
+ * configSUPPORT_DYNAMIC_ALLOCATION and configSUPPORT_STATIC_ALLOCATION and
+ * when it is possible to have both static and dynamic allocation:
+ *  +-----+---------+--------+-----------------------------+-----------------------------------+------------------+-----------+
+ * | MPU | Dynamic | Static |     Available Functions     |       Possible Allocations        | Both Dynamic and | Need Free |
+ * |     |         |        |                             |                                   | Static Possible  |           |
+ * +-----+---------+--------+-----------------------------+-----------------------------------+------------------+-----------+
+ * | 0   | 0       | 1      | xTaskCreateStatic           | TCB - Static, Stack - Static      | No               | No        |
+ * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------|
+ * | 0   | 1       | 0      | xTaskCreate                 | TCB - Dynamic, Stack - Dynamic    | No               | Yes       |
+ * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------|
+ * | 0   | 1       | 1      | xTaskCreate,                | 1. TCB - Dynamic, Stack - Dynamic | Yes              | Yes       |
+ * |     |         |        | xTaskCreateStatic           | 2. TCB - Static, Stack - Static   |                  |           |
+ * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------|
+ * | 1   | 0       | 1      | xTaskCreateStatic,          | TCB - Static, Stack - Static      | No               | No        |
+ * |     |         |        | xTaskCreateRestrictedStatic |                                   |                  |           |
+ * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------|
+ * | 1   | 1       | 0      | xTaskCreate,                | 1. TCB - Dynamic, Stack - Dynamic | Yes              | Yes       |
+ * |     |         |        | xTaskCreateRestricted       | 2. TCB - Dynamic, Stack - Static  |                  |           |
+ * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------|
+ * | 1   | 1       | 1      | xTaskCreate,                | 1. TCB - Dynamic, Stack - Dynamic | Yes              | Yes       |
+ * |     |         |        | xTaskCreateStatic,          | 2. TCB - Dynamic, Stack - Static  |                  |           |
+ * |     |         |        | xTaskCreateRestricted,      | 3. TCB - Static, Stack - Static   |                  |           |
+ * |     |         |        | xTaskCreateRestrictedStatic |                                   |                  |           |
+ * +-----+---------+--------+-----------------------------+-----------------------------------+------------------+-----------+
+ */
+#define tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE	( ( ( portUSING_MPU_WRAPPERS == 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) || \
+													  ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) )
+
+/*
+ * In line with software engineering best practice, FreeRTOS implements a strict
+ * data hiding policy, so the real structures used by FreeRTOS to maintain the
+ * state of tasks, queues, semaphores, etc. are not accessible to the application
+ * code.  However, if the application writer wants to statically allocate such
+ * an object then the size of the object needs to be know.  Dummy structures
+ * that are guaranteed to have the same size and alignment requirements of the
+ * real objects are used for this purpose.  The dummy list and list item
+ * structures below are used for inclusion in such a dummy structure.
+ */
+struct xSTATIC_LIST_ITEM
+{
+	#if( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 )
+		TickType_t xDummy1;
+	#endif
+	TickType_t xDummy2;
+	void *pvDummy3[ 4 ];
+	#if( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 )
+		TickType_t xDummy4;
+	#endif
+};
+typedef struct xSTATIC_LIST_ITEM StaticListItem_t;
+
+/* See the comments above the struct xSTATIC_LIST_ITEM definition. */
+struct xSTATIC_MINI_LIST_ITEM
+{
+	#if( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 )
+		TickType_t xDummy1;
+	#endif
+	TickType_t xDummy2;
+	void *pvDummy3[ 2 ];
+};
+typedef struct xSTATIC_MINI_LIST_ITEM StaticMiniListItem_t;
+
+/* See the comments above the struct xSTATIC_LIST_ITEM definition. */
+typedef struct xSTATIC_LIST
+{
+	#if( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 )
+		TickType_t xDummy1;
+	#endif
+	UBaseType_t uxDummy2;
+	void *pvDummy3;
+	StaticMiniListItem_t xDummy4;
+	#if( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 )
+		TickType_t xDummy5;
+	#endif
+} StaticList_t;
+
+/*
+ * In line with software engineering best practice, especially when supplying a
+ * library that is likely to change in future versions, FreeRTOS implements a
+ * strict data hiding policy.  This means the Task structure used internally by
+ * FreeRTOS is not accessible to application code.  However, if the application
+ * writer wants to statically allocate the memory required to create a task then
+ * the size of the task object needs to be know.  The StaticTask_t structure
+ * below is provided for this purpose.  Its sizes and alignment requirements are
+ * guaranteed to match those of the genuine structure, no matter which
+ * architecture is being used, and no matter how the values in FreeRTOSConfig.h
+ * are set.  Its contents are somewhat obfuscated in the hope users will
+ * recognise that it would be unwise to make direct use of the structure members.
+ */
+typedef struct xSTATIC_TCB
+{
+	void				*pxDummy1;
+	#if ( portUSING_MPU_WRAPPERS == 1 )
+		xMPU_SETTINGS	xDummy2;
+	#endif
+	StaticListItem_t	xDummy3[ 2 ];
+	UBaseType_t			uxDummy5;
+	void				*pxDummy6;
+	uint8_t				ucDummy7[ configMAX_TASK_NAME_LEN ];
+	#if ( ( portSTACK_GROWTH > 0 ) || ( configRECORD_STACK_HIGH_ADDRESS == 1 ) )
+		void			*pxDummy8;
+	#endif
+	#if ( portCRITICAL_NESTING_IN_TCB == 1 )
+		UBaseType_t		uxDummy9;
+	#endif
+	#if ( configUSE_TRACE_FACILITY == 1 )
+		UBaseType_t		uxDummy10[ 2 ];
+	#endif
+	#if ( configUSE_MUTEXES == 1 )
+		UBaseType_t		uxDummy12[ 2 ];
+	#endif
+	#if ( configUSE_APPLICATION_TASK_TAG == 1 )
+		void			*pxDummy14;
+	#endif
+	#if( configNUM_THREAD_LOCAL_STORAGE_POINTERS > 0 )
+		void			*pvDummy15[ configNUM_THREAD_LOCAL_STORAGE_POINTERS ];
+	#endif
+	#if ( configGENERATE_RUN_TIME_STATS == 1 )
+		uint32_t		ulDummy16;
+	#endif
+	#if ( configUSE_NEWLIB_REENTRANT == 1 )
+		struct	_reent	xDummy17;
+	#endif
+	#if ( configUSE_TASK_NOTIFICATIONS == 1 )
+		uint32_t 		ulDummy18;
+		uint8_t 		ucDummy19;
+	#endif
+	#if ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 )
+		uint8_t			uxDummy20;
+	#endif
+
+	#if( INCLUDE_xTaskAbortDelay == 1 )
+		uint8_t ucDummy21;
+	#endif
+	#if ( configUSE_POSIX_ERRNO == 1 )
+		int				iDummy22;
+	#endif
+} StaticTask_t;
+
+/*
+ * In line with software engineering best practice, especially when supplying a
+ * library that is likely to change in future versions, FreeRTOS implements a
+ * strict data hiding policy.  This means the Queue structure used internally by
+ * FreeRTOS is not accessible to application code.  However, if the application
+ * writer wants to statically allocate the memory required to create a queue
+ * then the size of the queue object needs to be know.  The StaticQueue_t
+ * structure below is provided for this purpose.  Its sizes and alignment
+ * requirements are guaranteed to match those of the genuine structure, no
+ * matter which architecture is being used, and no matter how the values in
+ * FreeRTOSConfig.h are set.  Its contents are somewhat obfuscated in the hope
+ * users will recognise that it would be unwise to make direct use of the
+ * structure members.
+ */
+typedef struct xSTATIC_QUEUE
+{
+	void *pvDummy1[ 3 ];
+
+	union
+	{
+		void *pvDummy2;
+		UBaseType_t uxDummy2;
+	} u;
+
+	StaticList_t xDummy3[ 2 ];
+	UBaseType_t uxDummy4[ 3 ];
+	uint8_t ucDummy5[ 2 ];
+
+	#if( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+		uint8_t ucDummy6;
+	#endif
+
+	#if ( configUSE_QUEUE_SETS == 1 )
+		void *pvDummy7;
+	#endif
+
+	#if ( configUSE_TRACE_FACILITY == 1 )
+		UBaseType_t uxDummy8;
+		uint8_t ucDummy9;
+	#endif
+
+} StaticQueue_t;
+typedef StaticQueue_t StaticSemaphore_t;
+
+/*
+ * In line with software engineering best practice, especially when supplying a
+ * library that is likely to change in future versions, FreeRTOS implements a
+ * strict data hiding policy.  This means the event group structure used
+ * internally by FreeRTOS is not accessible to application code.  However, if
+ * the application writer wants to statically allocate the memory required to
+ * create an event group then the size of the event group object needs to be
+ * know.  The StaticEventGroup_t structure below is provided for this purpose.
+ * Its sizes and alignment requirements are guaranteed to match those of the
+ * genuine structure, no matter which architecture is being used, and no matter
+ * how the values in FreeRTOSConfig.h are set.  Its contents are somewhat
+ * obfuscated in the hope users will recognise that it would be unwise to make
+ * direct use of the structure members.
+ */
+typedef struct xSTATIC_EVENT_GROUP
+{
+	TickType_t xDummy1;
+	StaticList_t xDummy2;
+
+	#if( configUSE_TRACE_FACILITY == 1 )
+		UBaseType_t uxDummy3;
+	#endif
+
+	#if( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+			uint8_t ucDummy4;
+	#endif
+
+} StaticEventGroup_t;
+
+/*
+ * In line with software engineering best practice, especially when supplying a
+ * library that is likely to change in future versions, FreeRTOS implements a
+ * strict data hiding policy.  This means the software timer structure used
+ * internally by FreeRTOS is not accessible to application code.  However, if
+ * the application writer wants to statically allocate the memory required to
+ * create a software timer then the size of the queue object needs to be know.
+ * The StaticTimer_t structure below is provided for this purpose.  Its sizes
+ * and alignment requirements are guaranteed to match those of the genuine
+ * structure, no matter which architecture is being used, and no matter how the
+ * values in FreeRTOSConfig.h are set.  Its contents are somewhat obfuscated in
+ * the hope users will recognise that it would be unwise to make direct use of
+ * the structure members.
+ */
+typedef struct xSTATIC_TIMER
+{
+	void				*pvDummy1;
+	StaticListItem_t	xDummy2;
+	TickType_t			xDummy3;
+	void 				*pvDummy5;
+	TaskFunction_t		pvDummy6;
+	#if( configUSE_TRACE_FACILITY == 1 )
+		UBaseType_t		uxDummy7;
+	#endif
+	uint8_t 			ucDummy8;
+
+} StaticTimer_t;
+
+/*
+* In line with software engineering best practice, especially when supplying a
+* library that is likely to change in future versions, FreeRTOS implements a
+* strict data hiding policy.  This means the stream buffer structure used
+* internally by FreeRTOS is not accessible to application code.  However, if
+* the application writer wants to statically allocate the memory required to
+* create a stream buffer then the size of the stream buffer object needs to be
+* know.  The StaticStreamBuffer_t structure below is provided for this purpose.
+* Its size and alignment requirements are guaranteed to match those of the
+* genuine structure, no matter which architecture is being used, and no matter
+* how the values in FreeRTOSConfig.h are set.  Its contents are somewhat
+* obfuscated in the hope users will recognise that it would be unwise to make
+* direct use of the structure members.
+*/
+typedef struct xSTATIC_STREAM_BUFFER
+{
+	size_t uxDummy1[ 4 ];
+	void * pvDummy2[ 3 ];
+	uint8_t ucDummy3;
+	#if ( configUSE_TRACE_FACILITY == 1 )
+		UBaseType_t uxDummy4;
+	#endif
+} StaticStreamBuffer_t;
+
+/* Message buffers are built on stream buffers. */
+typedef StaticStreamBuffer_t StaticMessageBuffer_t;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* INC_FREERTOS_H */
+
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/StackMacros.h b/Middlewares/Third_Party/FreeRTOS/Source/include/StackMacros.h
new file mode 100644
index 0000000..5643991
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/include/StackMacros.h
@@ -0,0 +1,133 @@
+/*
+ * FreeRTOS Kernel V10.3.1
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef STACK_MACROS_H
+#define STACK_MACROS_H
+
+#ifndef _MSC_VER /* Visual Studio doesn't support #warning. */
+	#warning The name of this file has changed to stack_macros.h.  Please update your code accordingly.  This source file (which has the original name) will be removed in future released.
+#endif
+
+/*
+ * Call the stack overflow hook function if the stack of the task being swapped
+ * out is currently overflowed, or looks like it might have overflowed in the
+ * past.
+ *
+ * Setting configCHECK_FOR_STACK_OVERFLOW to 1 will cause the macro to check
+ * the current stack state only - comparing the current top of stack value to
+ * the stack limit.  Setting configCHECK_FOR_STACK_OVERFLOW to greater than 1
+ * will also cause the last few stack bytes to be checked to ensure the value
+ * to which the bytes were set when the task was created have not been
+ * overwritten.  Note this second test does not guarantee that an overflowed
+ * stack will always be recognised.
+ */
+
+/*-----------------------------------------------------------*/
+
+#if( ( configCHECK_FOR_STACK_OVERFLOW == 1 ) && ( portSTACK_GROWTH < 0 ) )
+
+	/* Only the current stack state is to be checked. */
+	#define taskCHECK_FOR_STACK_OVERFLOW()																\
+	{																									\
+		/* Is the currently saved stack pointer within the stack limit? */								\
+		if( pxCurrentTCB->pxTopOfStack <= pxCurrentTCB->pxStack )										\
+		{																								\
+			vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName );	\
+		}																								\
+	}
+
+#endif /* configCHECK_FOR_STACK_OVERFLOW == 1 */
+/*-----------------------------------------------------------*/
+
+#if( ( configCHECK_FOR_STACK_OVERFLOW == 1 ) && ( portSTACK_GROWTH > 0 ) )
+
+	/* Only the current stack state is to be checked. */
+	#define taskCHECK_FOR_STACK_OVERFLOW()																\
+	{																									\
+																										\
+		/* Is the currently saved stack pointer within the stack limit? */								\
+		if( pxCurrentTCB->pxTopOfStack >= pxCurrentTCB->pxEndOfStack )									\
+		{																								\
+			vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName );	\
+		}																								\
+	}
+
+#endif /* configCHECK_FOR_STACK_OVERFLOW == 1 */
+/*-----------------------------------------------------------*/
+
+#if( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) && ( portSTACK_GROWTH < 0 ) )
+
+	#define taskCHECK_FOR_STACK_OVERFLOW()																\
+	{																									\
+		const uint32_t * const pulStack = ( uint32_t * ) pxCurrentTCB->pxStack;							\
+		const uint32_t ulCheckValue = ( uint32_t ) 0xa5a5a5a5;											\
+																										\
+		if( ( pulStack[ 0 ] != ulCheckValue ) ||												\
+			( pulStack[ 1 ] != ulCheckValue ) ||												\
+			( pulStack[ 2 ] != ulCheckValue ) ||												\
+			( pulStack[ 3 ] != ulCheckValue ) )												\
+		{																								\
+			vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName );	\
+		}																								\
+	}
+
+#endif /* #if( configCHECK_FOR_STACK_OVERFLOW > 1 ) */
+/*-----------------------------------------------------------*/
+
+#if( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) && ( portSTACK_GROWTH > 0 ) )
+
+	#define taskCHECK_FOR_STACK_OVERFLOW()																								\
+	{																																	\
+	int8_t *pcEndOfStack = ( int8_t * ) pxCurrentTCB->pxEndOfStack;																		\
+	static const uint8_t ucExpectedStackBytes[] = {	tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,		\
+													tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,		\
+													tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,		\
+													tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,		\
+													tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE };	\
+																																		\
+																																		\
+		pcEndOfStack -= sizeof( ucExpectedStackBytes );																					\
+																																		\
+		/* Has the extremity of the task stack ever been written over? */																\
+		if( memcmp( ( void * ) pcEndOfStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) != 0 )					\
+		{																																\
+			vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName );									\
+		}																																\
+	}
+
+#endif /* #if( configCHECK_FOR_STACK_OVERFLOW > 1 ) */
+/*-----------------------------------------------------------*/
+
+/* Remove stack overflow macro if not being used. */
+#ifndef taskCHECK_FOR_STACK_OVERFLOW
+	#define taskCHECK_FOR_STACK_OVERFLOW()
+#endif
+
+
+
+#endif /* STACK_MACROS_H */
+
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/atomic.h b/Middlewares/Third_Party/FreeRTOS/Source/include/atomic.h
new file mode 100644
index 0000000..ceca696
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/include/atomic.h
@@ -0,0 +1,414 @@
+/*
+ * FreeRTOS Kernel V10.3.1
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/**
+ * @file atomic.h
+ * @brief FreeRTOS atomic operation support.
+ *
+ * This file implements atomic functions by disabling interrupts globally.
+ * Implementations with architecture specific atomic instructions can be
+ * provided under each compiler directory.
+ */
+
+#ifndef ATOMIC_H
+#define ATOMIC_H
+
+#ifndef INC_FREERTOS_H
+	#error "include FreeRTOS.h must appear in source files before include atomic.h"
+#endif
+
+/* Standard includes. */
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * Port specific definitions -- entering/exiting critical section.
+ * Refer template -- ./lib/FreeRTOS/portable/Compiler/Arch/portmacro.h
+ *
+ * Every call to ATOMIC_EXIT_CRITICAL() must be closely paired with
+ * ATOMIC_ENTER_CRITICAL().
+ *
+ */
+#if defined( portSET_INTERRUPT_MASK_FROM_ISR )
+
+	/* Nested interrupt scheme is supported in this port. */
+	#define ATOMIC_ENTER_CRITICAL()	 \
+		UBaseType_t uxCriticalSectionType = portSET_INTERRUPT_MASK_FROM_ISR()
+
+	#define ATOMIC_EXIT_CRITICAL()	  \
+		portCLEAR_INTERRUPT_MASK_FROM_ISR( uxCriticalSectionType )
+
+#else
+
+	/* Nested interrupt scheme is NOT supported in this port. */
+	#define ATOMIC_ENTER_CRITICAL()	 portENTER_CRITICAL()
+	#define ATOMIC_EXIT_CRITICAL()	  portEXIT_CRITICAL()
+
+#endif /* portSET_INTERRUPT_MASK_FROM_ISR() */
+
+/*
+ * Port specific definition -- "always inline".
+ * Inline is compiler specific, and may not always get inlined depending on your
+ * optimization level.  Also, inline is considered as performance optimization
+ * for atomic.  Thus, if portFORCE_INLINE is not provided by portmacro.h,
+ * instead of resulting error, simply define it away.
+ */
+#ifndef portFORCE_INLINE
+	#define portFORCE_INLINE
+#endif
+
+#define ATOMIC_COMPARE_AND_SWAP_SUCCESS	 0x1U		/**< Compare and swap succeeded, swapped. */
+#define ATOMIC_COMPARE_AND_SWAP_FAILURE	 0x0U		/**< Compare and swap failed, did not swap. */
+
+/*----------------------------- Swap && CAS ------------------------------*/
+
+/**
+ * Atomic compare-and-swap
+ *
+ * @brief Performs an atomic compare-and-swap operation on the specified values.
+ *
+ * @param[in, out] pulDestination  Pointer to memory location from where value is
+ *                               to be loaded and checked.
+ * @param[in] ulExchange         If condition meets, write this value to memory.
+ * @param[in] ulComparand        Swap condition.
+ *
+ * @return Unsigned integer of value 1 or 0. 1 for swapped, 0 for not swapped.
+ *
+ * @note This function only swaps *pulDestination with ulExchange, if previous
+ *       *pulDestination value equals ulComparand.
+ */
+static portFORCE_INLINE uint32_t Atomic_CompareAndSwap_u32( uint32_t volatile * pulDestination,
+															uint32_t ulExchange,
+															uint32_t ulComparand )
+{
+uint32_t ulReturnValue;
+
+	ATOMIC_ENTER_CRITICAL();
+	{
+		if( *pulDestination == ulComparand )
+		{
+			*pulDestination = ulExchange;
+			ulReturnValue = ATOMIC_COMPARE_AND_SWAP_SUCCESS;
+		}
+		else
+		{
+			ulReturnValue = ATOMIC_COMPARE_AND_SWAP_FAILURE;
+		}
+	}
+	ATOMIC_EXIT_CRITICAL();
+
+	return ulReturnValue;
+}
+/*-----------------------------------------------------------*/
+
+/**
+ * Atomic swap (pointers)
+ *
+ * @brief Atomically sets the address pointed to by *ppvDestination to the value
+ *        of *pvExchange.
+ *
+ * @param[in, out] ppvDestination  Pointer to memory location from where a pointer
+ *                                 value is to be loaded and written back to.
+ * @param[in] pvExchange           Pointer value to be written to *ppvDestination.
+ *
+ * @return The initial value of *ppvDestination.
+ */
+static portFORCE_INLINE void * Atomic_SwapPointers_p32( void * volatile * ppvDestination,
+														void * pvExchange )
+{
+void * pReturnValue;
+
+	ATOMIC_ENTER_CRITICAL();
+	{
+		pReturnValue = *ppvDestination;
+		*ppvDestination = pvExchange;
+	}
+	ATOMIC_EXIT_CRITICAL();
+
+	return pReturnValue;
+}
+/*-----------------------------------------------------------*/
+
+/**
+ * Atomic compare-and-swap (pointers)
+ *
+ * @brief Performs an atomic compare-and-swap operation on the specified pointer
+ *        values.
+ *
+ * @param[in, out] ppvDestination  Pointer to memory location from where a pointer
+ *                                 value is to be loaded and checked.
+ * @param[in] pvExchange           If condition meets, write this value to memory.
+ * @param[in] pvComparand          Swap condition.
+ *
+ * @return Unsigned integer of value 1 or 0. 1 for swapped, 0 for not swapped.
+ *
+ * @note This function only swaps *ppvDestination with pvExchange, if previous
+ *       *ppvDestination value equals pvComparand.
+ */
+static portFORCE_INLINE uint32_t Atomic_CompareAndSwapPointers_p32( void * volatile * ppvDestination,
+																	void * pvExchange,
+																	void * pvComparand )
+{
+uint32_t ulReturnValue = ATOMIC_COMPARE_AND_SWAP_FAILURE;
+
+	ATOMIC_ENTER_CRITICAL();
+	{
+		if( *ppvDestination == pvComparand )
+		{
+			*ppvDestination = pvExchange;
+			ulReturnValue = ATOMIC_COMPARE_AND_SWAP_SUCCESS;
+		}
+	}
+	ATOMIC_EXIT_CRITICAL();
+
+	return ulReturnValue;
+}
+
+
+/*----------------------------- Arithmetic ------------------------------*/
+
+/**
+ * Atomic add
+ *
+ * @brief Atomically adds count to the value of the specified pointer points to.
+ *
+ * @param[in,out] pulAddend  Pointer to memory location from where value is to be
+ *                         loaded and written back to.
+ * @param[in] ulCount      Value to be added to *pulAddend.
+ *
+ * @return previous *pulAddend value.
+ */
+static portFORCE_INLINE uint32_t Atomic_Add_u32( uint32_t volatile * pulAddend,
+												 uint32_t ulCount )
+{
+	uint32_t ulCurrent;
+
+	ATOMIC_ENTER_CRITICAL();
+	{
+		ulCurrent = *pulAddend;
+		*pulAddend += ulCount;
+	}
+	ATOMIC_EXIT_CRITICAL();
+
+	return ulCurrent;
+}
+/*-----------------------------------------------------------*/
+
+/**
+ * Atomic subtract
+ *
+ * @brief Atomically subtracts count from the value of the specified pointer
+ *        pointers to.
+ *
+ * @param[in,out] pulAddend  Pointer to memory location from where value is to be
+ *                         loaded and written back to.
+ * @param[in] ulCount      Value to be subtract from *pulAddend.
+ *
+ * @return previous *pulAddend value.
+ */
+static portFORCE_INLINE uint32_t Atomic_Subtract_u32( uint32_t volatile * pulAddend,
+													  uint32_t ulCount )
+{
+	uint32_t ulCurrent;
+
+	ATOMIC_ENTER_CRITICAL();
+	{
+		ulCurrent = *pulAddend;
+		*pulAddend -= ulCount;
+	}
+	ATOMIC_EXIT_CRITICAL();
+
+	return ulCurrent;
+}
+/*-----------------------------------------------------------*/
+
+/**
+ * Atomic increment
+ *
+ * @brief Atomically increments the value of the specified pointer points to.
+ *
+ * @param[in,out] pulAddend  Pointer to memory location from where value is to be
+ *                         loaded and written back to.
+ *
+ * @return *pulAddend value before increment.
+ */
+static portFORCE_INLINE uint32_t Atomic_Increment_u32( uint32_t volatile * pulAddend )
+{
+uint32_t ulCurrent;
+
+	ATOMIC_ENTER_CRITICAL();
+	{
+		ulCurrent = *pulAddend;
+		*pulAddend += 1;
+	}
+	ATOMIC_EXIT_CRITICAL();
+
+	return ulCurrent;
+}
+/*-----------------------------------------------------------*/
+
+/**
+ * Atomic decrement
+ *
+ * @brief Atomically decrements the value of the specified pointer points to
+ *
+ * @param[in,out] pulAddend  Pointer to memory location from where value is to be
+ *                         loaded and written back to.
+ *
+ * @return *pulAddend value before decrement.
+ */
+static portFORCE_INLINE uint32_t Atomic_Decrement_u32( uint32_t volatile * pulAddend )
+{
+uint32_t ulCurrent;
+
+	ATOMIC_ENTER_CRITICAL();
+	{
+		ulCurrent = *pulAddend;
+		*pulAddend -= 1;
+	}
+	ATOMIC_EXIT_CRITICAL();
+
+	return ulCurrent;
+}
+
+/*----------------------------- Bitwise Logical ------------------------------*/
+
+/**
+ * Atomic OR
+ *
+ * @brief Performs an atomic OR operation on the specified values.
+ *
+ * @param [in, out] pulDestination  Pointer to memory location from where value is
+ *                                to be loaded and written back to.
+ * @param [in] ulValue            Value to be ORed with *pulDestination.
+ *
+ * @return The original value of *pulDestination.
+ */
+static portFORCE_INLINE uint32_t Atomic_OR_u32( uint32_t volatile * pulDestination,
+												uint32_t ulValue )
+{
+uint32_t ulCurrent;
+
+	ATOMIC_ENTER_CRITICAL();
+	{
+		ulCurrent = *pulDestination;
+		*pulDestination |= ulValue;
+	}
+	ATOMIC_EXIT_CRITICAL();
+
+	return ulCurrent;
+}
+/*-----------------------------------------------------------*/
+
+/**
+ * Atomic AND
+ *
+ * @brief Performs an atomic AND operation on the specified values.
+ *
+ * @param [in, out] pulDestination  Pointer to memory location from where value is
+ *                                to be loaded and written back to.
+ * @param [in] ulValue            Value to be ANDed with *pulDestination.
+ *
+ * @return The original value of *pulDestination.
+ */
+static portFORCE_INLINE uint32_t Atomic_AND_u32( uint32_t volatile * pulDestination,
+												 uint32_t ulValue )
+{
+uint32_t ulCurrent;
+
+	ATOMIC_ENTER_CRITICAL();
+	{
+		ulCurrent = *pulDestination;
+		*pulDestination &= ulValue;
+	}
+	ATOMIC_EXIT_CRITICAL();
+
+	return ulCurrent;
+}
+/*-----------------------------------------------------------*/
+
+/**
+ * Atomic NAND
+ *
+ * @brief Performs an atomic NAND operation on the specified values.
+ *
+ * @param [in, out] pulDestination  Pointer to memory location from where value is
+ *                                to be loaded and written back to.
+ * @param [in] ulValue            Value to be NANDed with *pulDestination.
+ *
+ * @return The original value of *pulDestination.
+ */
+static portFORCE_INLINE uint32_t Atomic_NAND_u32( uint32_t volatile * pulDestination,
+												  uint32_t ulValue )
+{
+uint32_t ulCurrent;
+
+	ATOMIC_ENTER_CRITICAL();
+	{
+		ulCurrent = *pulDestination;
+		*pulDestination = ~( ulCurrent & ulValue );
+	}
+	ATOMIC_EXIT_CRITICAL();
+
+	return ulCurrent;
+}
+/*-----------------------------------------------------------*/
+
+/**
+ * Atomic XOR
+ *
+ * @brief Performs an atomic XOR operation on the specified values.
+ *
+ * @param [in, out] pulDestination  Pointer to memory location from where value is
+ *                                to be loaded and written back to.
+ * @param [in] ulValue            Value to be XORed with *pulDestination.
+ *
+ * @return The original value of *pulDestination.
+ */
+static portFORCE_INLINE uint32_t Atomic_XOR_u32( uint32_t volatile * pulDestination,
+												 uint32_t ulValue )
+{
+uint32_t ulCurrent;
+
+	ATOMIC_ENTER_CRITICAL();
+	{
+		ulCurrent = *pulDestination;
+		*pulDestination ^= ulValue;
+	}
+	ATOMIC_EXIT_CRITICAL();
+
+	return ulCurrent;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ATOMIC_H */
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/croutine.h b/Middlewares/Third_Party/FreeRTOS/Source/include/croutine.h
new file mode 100644
index 0000000..8d7069c
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/include/croutine.h
@@ -0,0 +1,720 @@
+/*
+ * FreeRTOS Kernel V10.3.1
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef CO_ROUTINE_H
+#define CO_ROUTINE_H
+
+#ifndef INC_FREERTOS_H
+	#error "include FreeRTOS.h must appear in source files before include croutine.h"
+#endif
+
+#include "list.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Used to hide the implementation of the co-routine control block.  The
+control block structure however has to be included in the header due to
+the macro implementation of the co-routine functionality. */
+typedef void * CoRoutineHandle_t;
+
+/* Defines the prototype to which co-routine functions must conform. */
+typedef void (*crCOROUTINE_CODE)( CoRoutineHandle_t, UBaseType_t );
+
+typedef struct corCoRoutineControlBlock
+{
+	crCOROUTINE_CODE 	pxCoRoutineFunction;
+	ListItem_t			xGenericListItem;	/*< List item used to place the CRCB in ready and blocked queues. */
+	ListItem_t			xEventListItem;		/*< List item used to place the CRCB in event lists. */
+	UBaseType_t 		uxPriority;			/*< The priority of the co-routine in relation to other co-routines. */
+	UBaseType_t 		uxIndex;			/*< Used to distinguish between co-routines when multiple co-routines use the same co-routine function. */
+	uint16_t 			uxState;			/*< Used internally by the co-routine implementation. */
+} CRCB_t; /* Co-routine control block.  Note must be identical in size down to uxPriority with TCB_t. */
+
+/**
+ * croutine. h
+ *<pre>
+ BaseType_t xCoRoutineCreate(
+                                 crCOROUTINE_CODE pxCoRoutineCode,
+                                 UBaseType_t uxPriority,
+                                 UBaseType_t uxIndex
+                               );</pre>
+ *
+ * Create a new co-routine and add it to the list of co-routines that are
+ * ready to run.
+ *
+ * @param pxCoRoutineCode Pointer to the co-routine function.  Co-routine
+ * functions require special syntax - see the co-routine section of the WEB
+ * documentation for more information.
+ *
+ * @param uxPriority The priority with respect to other co-routines at which
+ *  the co-routine will run.
+ *
+ * @param uxIndex Used to distinguish between different co-routines that
+ * execute the same function.  See the example below and the co-routine section
+ * of the WEB documentation for further information.
+ *
+ * @return pdPASS if the co-routine was successfully created and added to a ready
+ * list, otherwise an error code defined with ProjDefs.h.
+ *
+ * Example usage:
+   <pre>
+ // Co-routine to be created.
+ void vFlashCoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ {
+ // Variables in co-routines must be declared static if they must maintain value across a blocking call.
+ // This may not be necessary for const variables.
+ static const char cLedToFlash[ 2 ] = { 5, 6 };
+ static const TickType_t uxFlashRates[ 2 ] = { 200, 400 };
+
+     // Must start every co-routine with a call to crSTART();
+     crSTART( xHandle );
+
+     for( ;; )
+     {
+         // This co-routine just delays for a fixed period, then toggles
+         // an LED.  Two co-routines are created using this function, so
+         // the uxIndex parameter is used to tell the co-routine which
+         // LED to flash and how int32_t to delay.  This assumes xQueue has
+         // already been created.
+         vParTestToggleLED( cLedToFlash[ uxIndex ] );
+         crDELAY( xHandle, uxFlashRates[ uxIndex ] );
+     }
+
+     // Must end every co-routine with a call to crEND();
+     crEND();
+ }
+
+ // Function that creates two co-routines.
+ void vOtherFunction( void )
+ {
+ uint8_t ucParameterToPass;
+ TaskHandle_t xHandle;
+
+     // Create two co-routines at priority 0.  The first is given index 0
+     // so (from the code above) toggles LED 5 every 200 ticks.  The second
+     // is given index 1 so toggles LED 6 every 400 ticks.
+     for( uxIndex = 0; uxIndex < 2; uxIndex++ )
+     {
+         xCoRoutineCreate( vFlashCoRoutine, 0, uxIndex );
+     }
+ }
+   </pre>
+ * \defgroup xCoRoutineCreate xCoRoutineCreate
+ * \ingroup Tasks
+ */
+BaseType_t xCoRoutineCreate( crCOROUTINE_CODE pxCoRoutineCode, UBaseType_t uxPriority, UBaseType_t uxIndex );
+
+
+/**
+ * croutine. h
+ *<pre>
+ void vCoRoutineSchedule( void );</pre>
+ *
+ * Run a co-routine.
+ *
+ * vCoRoutineSchedule() executes the highest priority co-routine that is able
+ * to run.  The co-routine will execute until it either blocks, yields or is
+ * preempted by a task.  Co-routines execute cooperatively so one
+ * co-routine cannot be preempted by another, but can be preempted by a task.
+ *
+ * If an application comprises of both tasks and co-routines then
+ * vCoRoutineSchedule should be called from the idle task (in an idle task
+ * hook).
+ *
+ * Example usage:
+   <pre>
+ // This idle task hook will schedule a co-routine each time it is called.
+ // The rest of the idle task will execute between co-routine calls.
+ void vApplicationIdleHook( void )
+ {
+	vCoRoutineSchedule();
+ }
+
+ // Alternatively, if you do not require any other part of the idle task to
+ // execute, the idle task hook can call vCoRoutineSchedule() within an
+ // infinite loop.
+ void vApplicationIdleHook( void )
+ {
+    for( ;; )
+    {
+        vCoRoutineSchedule();
+    }
+ }
+ </pre>
+ * \defgroup vCoRoutineSchedule vCoRoutineSchedule
+ * \ingroup Tasks
+ */
+void vCoRoutineSchedule( void );
+
+/**
+ * croutine. h
+ * <pre>
+ crSTART( CoRoutineHandle_t xHandle );</pre>
+ *
+ * This macro MUST always be called at the start of a co-routine function.
+ *
+ * Example usage:
+   <pre>
+ // Co-routine to be created.
+ void vACoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ {
+ // Variables in co-routines must be declared static if they must maintain value across a blocking call.
+ static int32_t ulAVariable;
+
+     // Must start every co-routine with a call to crSTART();
+     crSTART( xHandle );
+
+     for( ;; )
+     {
+          // Co-routine functionality goes here.
+     }
+
+     // Must end every co-routine with a call to crEND();
+     crEND();
+ }</pre>
+ * \defgroup crSTART crSTART
+ * \ingroup Tasks
+ */
+#define crSTART( pxCRCB ) switch( ( ( CRCB_t * )( pxCRCB ) )->uxState ) { case 0:
+
+/**
+ * croutine. h
+ * <pre>
+ crEND();</pre>
+ *
+ * This macro MUST always be called at the end of a co-routine function.
+ *
+ * Example usage:
+   <pre>
+ // Co-routine to be created.
+ void vACoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ {
+ // Variables in co-routines must be declared static if they must maintain value across a blocking call.
+ static int32_t ulAVariable;
+
+     // Must start every co-routine with a call to crSTART();
+     crSTART( xHandle );
+
+     for( ;; )
+     {
+          // Co-routine functionality goes here.
+     }
+
+     // Must end every co-routine with a call to crEND();
+     crEND();
+ }</pre>
+ * \defgroup crSTART crSTART
+ * \ingroup Tasks
+ */
+#define crEND() }
+
+/*
+ * These macros are intended for internal use by the co-routine implementation
+ * only.  The macros should not be used directly by application writers.
+ */
+#define crSET_STATE0( xHandle ) ( ( CRCB_t * )( xHandle ) )->uxState = (__LINE__ * 2); return; case (__LINE__ * 2):
+#define crSET_STATE1( xHandle ) ( ( CRCB_t * )( xHandle ) )->uxState = ((__LINE__ * 2)+1); return; case ((__LINE__ * 2)+1):
+
+/**
+ * croutine. h
+ *<pre>
+ crDELAY( CoRoutineHandle_t xHandle, TickType_t xTicksToDelay );</pre>
+ *
+ * Delay a co-routine for a fixed period of time.
+ *
+ * crDELAY can only be called from the co-routine function itself - not
+ * from within a function called by the co-routine function.  This is because
+ * co-routines do not maintain their own stack.
+ *
+ * @param xHandle The handle of the co-routine to delay.  This is the xHandle
+ * parameter of the co-routine function.
+ *
+ * @param xTickToDelay The number of ticks that the co-routine should delay
+ * for.  The actual amount of time this equates to is defined by
+ * configTICK_RATE_HZ (set in FreeRTOSConfig.h).  The constant portTICK_PERIOD_MS
+ * can be used to convert ticks to milliseconds.
+ *
+ * Example usage:
+   <pre>
+ // Co-routine to be created.
+ void vACoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ {
+ // Variables in co-routines must be declared static if they must maintain value across a blocking call.
+ // This may not be necessary for const variables.
+ // We are to delay for 200ms.
+ static const xTickType xDelayTime = 200 / portTICK_PERIOD_MS;
+
+     // Must start every co-routine with a call to crSTART();
+     crSTART( xHandle );
+
+     for( ;; )
+     {
+        // Delay for 200ms.
+        crDELAY( xHandle, xDelayTime );
+
+        // Do something here.
+     }
+
+     // Must end every co-routine with a call to crEND();
+     crEND();
+ }</pre>
+ * \defgroup crDELAY crDELAY
+ * \ingroup Tasks
+ */
+#define crDELAY( xHandle, xTicksToDelay )												\
+	if( ( xTicksToDelay ) > 0 )															\
+	{																					\
+		vCoRoutineAddToDelayedList( ( xTicksToDelay ), NULL );							\
+	}																					\
+	crSET_STATE0( ( xHandle ) );
+
+/**
+ * <pre>
+ crQUEUE_SEND(
+                  CoRoutineHandle_t xHandle,
+                  QueueHandle_t pxQueue,
+                  void *pvItemToQueue,
+                  TickType_t xTicksToWait,
+                  BaseType_t *pxResult
+             )</pre>
+ *
+ * The macro's crQUEUE_SEND() and crQUEUE_RECEIVE() are the co-routine
+ * equivalent to the xQueueSend() and xQueueReceive() functions used by tasks.
+ *
+ * crQUEUE_SEND and crQUEUE_RECEIVE can only be used from a co-routine whereas
+ * xQueueSend() and xQueueReceive() can only be used from tasks.
+ *
+ * crQUEUE_SEND can only be called from the co-routine function itself - not
+ * from within a function called by the co-routine function.  This is because
+ * co-routines do not maintain their own stack.
+ *
+ * See the co-routine section of the WEB documentation for information on
+ * passing data between tasks and co-routines and between ISR's and
+ * co-routines.
+ *
+ * @param xHandle The handle of the calling co-routine.  This is the xHandle
+ * parameter of the co-routine function.
+ *
+ * @param pxQueue The handle of the queue on which the data will be posted.
+ * The handle is obtained as the return value when the queue is created using
+ * the xQueueCreate() API function.
+ *
+ * @param pvItemToQueue A pointer to the data being posted onto the queue.
+ * The number of bytes of each queued item is specified when the queue is
+ * created.  This number of bytes is copied from pvItemToQueue into the queue
+ * itself.
+ *
+ * @param xTickToDelay The number of ticks that the co-routine should block
+ * to wait for space to become available on the queue, should space not be
+ * available immediately. The actual amount of time this equates to is defined
+ * by configTICK_RATE_HZ (set in FreeRTOSConfig.h).  The constant
+ * portTICK_PERIOD_MS can be used to convert ticks to milliseconds (see example
+ * below).
+ *
+ * @param pxResult The variable pointed to by pxResult will be set to pdPASS if
+ * data was successfully posted onto the queue, otherwise it will be set to an
+ * error defined within ProjDefs.h.
+ *
+ * Example usage:
+   <pre>
+ // Co-routine function that blocks for a fixed period then posts a number onto
+ // a queue.
+ static void prvCoRoutineFlashTask( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ {
+ // Variables in co-routines must be declared static if they must maintain value across a blocking call.
+ static BaseType_t xNumberToPost = 0;
+ static BaseType_t xResult;
+
+    // Co-routines must begin with a call to crSTART().
+    crSTART( xHandle );
+
+    for( ;; )
+    {
+        // This assumes the queue has already been created.
+        crQUEUE_SEND( xHandle, xCoRoutineQueue, &xNumberToPost, NO_DELAY, &xResult );
+
+        if( xResult != pdPASS )
+        {
+            // The message was not posted!
+        }
+
+        // Increment the number to be posted onto the queue.
+        xNumberToPost++;
+
+        // Delay for 100 ticks.
+        crDELAY( xHandle, 100 );
+    }
+
+    // Co-routines must end with a call to crEND().
+    crEND();
+ }</pre>
+ * \defgroup crQUEUE_SEND crQUEUE_SEND
+ * \ingroup Tasks
+ */
+#define crQUEUE_SEND( xHandle, pxQueue, pvItemToQueue, xTicksToWait, pxResult )			\
+{																						\
+	*( pxResult ) = xQueueCRSend( ( pxQueue) , ( pvItemToQueue) , ( xTicksToWait ) );	\
+	if( *( pxResult ) == errQUEUE_BLOCKED )												\
+	{																					\
+		crSET_STATE0( ( xHandle ) );													\
+		*pxResult = xQueueCRSend( ( pxQueue ), ( pvItemToQueue ), 0 );					\
+	}																					\
+	if( *pxResult == errQUEUE_YIELD )													\
+	{																					\
+		crSET_STATE1( ( xHandle ) );													\
+		*pxResult = pdPASS;																\
+	}																					\
+}
+
+/**
+ * croutine. h
+ * <pre>
+  crQUEUE_RECEIVE(
+                     CoRoutineHandle_t xHandle,
+                     QueueHandle_t pxQueue,
+                     void *pvBuffer,
+                     TickType_t xTicksToWait,
+                     BaseType_t *pxResult
+                 )</pre>
+ *
+ * The macro's crQUEUE_SEND() and crQUEUE_RECEIVE() are the co-routine
+ * equivalent to the xQueueSend() and xQueueReceive() functions used by tasks.
+ *
+ * crQUEUE_SEND and crQUEUE_RECEIVE can only be used from a co-routine whereas
+ * xQueueSend() and xQueueReceive() can only be used from tasks.
+ *
+ * crQUEUE_RECEIVE can only be called from the co-routine function itself - not
+ * from within a function called by the co-routine function.  This is because
+ * co-routines do not maintain their own stack.
+ *
+ * See the co-routine section of the WEB documentation for information on
+ * passing data between tasks and co-routines and between ISR's and
+ * co-routines.
+ *
+ * @param xHandle The handle of the calling co-routine.  This is the xHandle
+ * parameter of the co-routine function.
+ *
+ * @param pxQueue The handle of the queue from which the data will be received.
+ * The handle is obtained as the return value when the queue is created using
+ * the xQueueCreate() API function.
+ *
+ * @param pvBuffer The buffer into which the received item is to be copied.
+ * The number of bytes of each queued item is specified when the queue is
+ * created.  This number of bytes is copied into pvBuffer.
+ *
+ * @param xTickToDelay The number of ticks that the co-routine should block
+ * to wait for data to become available from the queue, should data not be
+ * available immediately. The actual amount of time this equates to is defined
+ * by configTICK_RATE_HZ (set in FreeRTOSConfig.h).  The constant
+ * portTICK_PERIOD_MS can be used to convert ticks to milliseconds (see the
+ * crQUEUE_SEND example).
+ *
+ * @param pxResult The variable pointed to by pxResult will be set to pdPASS if
+ * data was successfully retrieved from the queue, otherwise it will be set to
+ * an error code as defined within ProjDefs.h.
+ *
+ * Example usage:
+ <pre>
+ // A co-routine receives the number of an LED to flash from a queue.  It
+ // blocks on the queue until the number is received.
+ static void prvCoRoutineFlashWorkTask( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ {
+ // Variables in co-routines must be declared static if they must maintain value across a blocking call.
+ static BaseType_t xResult;
+ static UBaseType_t uxLEDToFlash;
+
+    // All co-routines must start with a call to crSTART().
+    crSTART( xHandle );
+
+    for( ;; )
+    {
+        // Wait for data to become available on the queue.
+        crQUEUE_RECEIVE( xHandle, xCoRoutineQueue, &uxLEDToFlash, portMAX_DELAY, &xResult );
+
+        if( xResult == pdPASS )
+        {
+            // We received the LED to flash - flash it!
+            vParTestToggleLED( uxLEDToFlash );
+        }
+    }
+
+    crEND();
+ }</pre>
+ * \defgroup crQUEUE_RECEIVE crQUEUE_RECEIVE
+ * \ingroup Tasks
+ */
+#define crQUEUE_RECEIVE( xHandle, pxQueue, pvBuffer, xTicksToWait, pxResult )			\
+{																						\
+	*( pxResult ) = xQueueCRReceive( ( pxQueue) , ( pvBuffer ), ( xTicksToWait ) );		\
+	if( *( pxResult ) == errQUEUE_BLOCKED ) 											\
+	{																					\
+		crSET_STATE0( ( xHandle ) );													\
+		*( pxResult ) = xQueueCRReceive( ( pxQueue) , ( pvBuffer ), 0 );				\
+	}																					\
+	if( *( pxResult ) == errQUEUE_YIELD )												\
+	{																					\
+		crSET_STATE1( ( xHandle ) );													\
+		*( pxResult ) = pdPASS;															\
+	}																					\
+}
+
+/**
+ * croutine. h
+ * <pre>
+  crQUEUE_SEND_FROM_ISR(
+                            QueueHandle_t pxQueue,
+                            void *pvItemToQueue,
+                            BaseType_t xCoRoutinePreviouslyWoken
+                       )</pre>
+ *
+ * The macro's crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() are the
+ * co-routine equivalent to the xQueueSendFromISR() and xQueueReceiveFromISR()
+ * functions used by tasks.
+ *
+ * crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() can only be used to
+ * pass data between a co-routine and and ISR, whereas xQueueSendFromISR() and
+ * xQueueReceiveFromISR() can only be used to pass data between a task and and
+ * ISR.
+ *
+ * crQUEUE_SEND_FROM_ISR can only be called from an ISR to send data to a queue
+ * that is being used from within a co-routine.
+ *
+ * See the co-routine section of the WEB documentation for information on
+ * passing data between tasks and co-routines and between ISR's and
+ * co-routines.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param xCoRoutinePreviouslyWoken This is included so an ISR can post onto
+ * the same queue multiple times from a single interrupt.  The first call
+ * should always pass in pdFALSE.  Subsequent calls should pass in
+ * the value returned from the previous call.
+ *
+ * @return pdTRUE if a co-routine was woken by posting onto the queue.  This is
+ * used by the ISR to determine if a context switch may be required following
+ * the ISR.
+ *
+ * Example usage:
+ <pre>
+ // A co-routine that blocks on a queue waiting for characters to be received.
+ static void vReceivingCoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ {
+ char cRxedChar;
+ BaseType_t xResult;
+
+     // All co-routines must start with a call to crSTART().
+     crSTART( xHandle );
+
+     for( ;; )
+     {
+         // Wait for data to become available on the queue.  This assumes the
+         // queue xCommsRxQueue has already been created!
+         crQUEUE_RECEIVE( xHandle, xCommsRxQueue, &uxLEDToFlash, portMAX_DELAY, &xResult );
+
+         // Was a character received?
+         if( xResult == pdPASS )
+         {
+             // Process the character here.
+         }
+     }
+
+     // All co-routines must end with a call to crEND().
+     crEND();
+ }
+
+ // An ISR that uses a queue to send characters received on a serial port to
+ // a co-routine.
+ void vUART_ISR( void )
+ {
+ char cRxedChar;
+ BaseType_t xCRWokenByPost = pdFALSE;
+
+     // We loop around reading characters until there are none left in the UART.
+     while( UART_RX_REG_NOT_EMPTY() )
+     {
+         // Obtain the character from the UART.
+         cRxedChar = UART_RX_REG;
+
+         // Post the character onto a queue.  xCRWokenByPost will be pdFALSE
+         // the first time around the loop.  If the post causes a co-routine
+         // to be woken (unblocked) then xCRWokenByPost will be set to pdTRUE.
+         // In this manner we can ensure that if more than one co-routine is
+         // blocked on the queue only one is woken by this ISR no matter how
+         // many characters are posted to the queue.
+         xCRWokenByPost = crQUEUE_SEND_FROM_ISR( xCommsRxQueue, &cRxedChar, xCRWokenByPost );
+     }
+ }</pre>
+ * \defgroup crQUEUE_SEND_FROM_ISR crQUEUE_SEND_FROM_ISR
+ * \ingroup Tasks
+ */
+#define crQUEUE_SEND_FROM_ISR( pxQueue, pvItemToQueue, xCoRoutinePreviouslyWoken ) xQueueCRSendFromISR( ( pxQueue ), ( pvItemToQueue ), ( xCoRoutinePreviouslyWoken ) )
+
+
+/**
+ * croutine. h
+ * <pre>
+  crQUEUE_SEND_FROM_ISR(
+                            QueueHandle_t pxQueue,
+                            void *pvBuffer,
+                            BaseType_t * pxCoRoutineWoken
+                       )</pre>
+ *
+ * The macro's crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() are the
+ * co-routine equivalent to the xQueueSendFromISR() and xQueueReceiveFromISR()
+ * functions used by tasks.
+ *
+ * crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() can only be used to
+ * pass data between a co-routine and and ISR, whereas xQueueSendFromISR() and
+ * xQueueReceiveFromISR() can only be used to pass data between a task and and
+ * ISR.
+ *
+ * crQUEUE_RECEIVE_FROM_ISR can only be called from an ISR to receive data
+ * from a queue that is being used from within a co-routine (a co-routine
+ * posted to the queue).
+ *
+ * See the co-routine section of the WEB documentation for information on
+ * passing data between tasks and co-routines and between ISR's and
+ * co-routines.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvBuffer A pointer to a buffer into which the received item will be
+ * placed.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from the queue into
+ * pvBuffer.
+ *
+ * @param pxCoRoutineWoken A co-routine may be blocked waiting for space to become
+ * available on the queue.  If crQUEUE_RECEIVE_FROM_ISR causes such a
+ * co-routine to unblock *pxCoRoutineWoken will get set to pdTRUE, otherwise
+ * *pxCoRoutineWoken will remain unchanged.
+ *
+ * @return pdTRUE an item was successfully received from the queue, otherwise
+ * pdFALSE.
+ *
+ * Example usage:
+ <pre>
+ // A co-routine that posts a character to a queue then blocks for a fixed
+ // period.  The character is incremented each time.
+ static void vSendingCoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ {
+ // cChar holds its value while this co-routine is blocked and must therefore
+ // be declared static.
+ static char cCharToTx = 'a';
+ BaseType_t xResult;
+
+     // All co-routines must start with a call to crSTART().
+     crSTART( xHandle );
+
+     for( ;; )
+     {
+         // Send the next character to the queue.
+         crQUEUE_SEND( xHandle, xCoRoutineQueue, &cCharToTx, NO_DELAY, &xResult );
+
+         if( xResult == pdPASS )
+         {
+             // The character was successfully posted to the queue.
+         }
+		 else
+		 {
+			// Could not post the character to the queue.
+		 }
+
+         // Enable the UART Tx interrupt to cause an interrupt in this
+		 // hypothetical UART.  The interrupt will obtain the character
+		 // from the queue and send it.
+		 ENABLE_RX_INTERRUPT();
+
+		 // Increment to the next character then block for a fixed period.
+		 // cCharToTx will maintain its value across the delay as it is
+		 // declared static.
+		 cCharToTx++;
+		 if( cCharToTx > 'x' )
+		 {
+			cCharToTx = 'a';
+		 }
+		 crDELAY( 100 );
+     }
+
+     // All co-routines must end with a call to crEND().
+     crEND();
+ }
+
+ // An ISR that uses a queue to receive characters to send on a UART.
+ void vUART_ISR( void )
+ {
+ char cCharToTx;
+ BaseType_t xCRWokenByPost = pdFALSE;
+
+     while( UART_TX_REG_EMPTY() )
+     {
+         // Are there any characters in the queue waiting to be sent?
+		 // xCRWokenByPost will automatically be set to pdTRUE if a co-routine
+		 // is woken by the post - ensuring that only a single co-routine is
+		 // woken no matter how many times we go around this loop.
+         if( crQUEUE_RECEIVE_FROM_ISR( pxQueue, &cCharToTx, &xCRWokenByPost ) )
+		 {
+			 SEND_CHARACTER( cCharToTx );
+		 }
+     }
+ }</pre>
+ * \defgroup crQUEUE_RECEIVE_FROM_ISR crQUEUE_RECEIVE_FROM_ISR
+ * \ingroup Tasks
+ */
+#define crQUEUE_RECEIVE_FROM_ISR( pxQueue, pvBuffer, pxCoRoutineWoken ) xQueueCRReceiveFromISR( ( pxQueue ), ( pvBuffer ), ( pxCoRoutineWoken ) )
+
+/*
+ * This function is intended for internal use by the co-routine macros only.
+ * The macro nature of the co-routine implementation requires that the
+ * prototype appears here.  The function should not be used by application
+ * writers.
+ *
+ * Removes the current co-routine from its ready list and places it in the
+ * appropriate delayed list.
+ */
+void vCoRoutineAddToDelayedList( TickType_t xTicksToDelay, List_t *pxEventList );
+
+/*
+ * This function is intended for internal use by the queue implementation only.
+ * The function should not be used by application writers.
+ *
+ * Removes the highest priority co-routine from the event list and places it in
+ * the pending ready list.
+ */
+BaseType_t xCoRoutineRemoveFromEventList( const List_t *pxEventList );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* CO_ROUTINE_H */
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h b/Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h
new file mode 100644
index 0000000..21657b9
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h
@@ -0,0 +1,279 @@
+/*
+ * FreeRTOS Kernel V10.3.1
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef DEPRECATED_DEFINITIONS_H
+#define DEPRECATED_DEFINITIONS_H
+
+
+/* Each FreeRTOS port has a unique portmacro.h header file.  Originally a
+pre-processor definition was used to ensure the pre-processor found the correct
+portmacro.h file for the port being used.  That scheme was deprecated in favour
+of setting the compiler's include path such that it found the correct
+portmacro.h file - removing the need for the constant and allowing the
+portmacro.h file to be located anywhere in relation to the port being used.  The
+definitions below remain in the code for backward compatibility only.  New
+projects should not use them. */
+
+#ifdef OPEN_WATCOM_INDUSTRIAL_PC_PORT
+	#include "..\..\Source\portable\owatcom\16bitdos\pc\portmacro.h"
+	typedef void ( __interrupt __far *pxISR )();
+#endif
+
+#ifdef OPEN_WATCOM_FLASH_LITE_186_PORT
+	#include "..\..\Source\portable\owatcom\16bitdos\flsh186\portmacro.h"
+	typedef void ( __interrupt __far *pxISR )();
+#endif
+
+#ifdef GCC_MEGA_AVR
+	#include "../portable/GCC/ATMega323/portmacro.h"
+#endif
+
+#ifdef IAR_MEGA_AVR
+	#include "../portable/IAR/ATMega323/portmacro.h"
+#endif
+
+#ifdef MPLAB_PIC24_PORT
+	#include "../../Source/portable/MPLAB/PIC24_dsPIC/portmacro.h"
+#endif
+
+#ifdef MPLAB_DSPIC_PORT
+	#include "../../Source/portable/MPLAB/PIC24_dsPIC/portmacro.h"
+#endif
+
+#ifdef MPLAB_PIC18F_PORT
+	#include "../../Source/portable/MPLAB/PIC18F/portmacro.h"
+#endif
+
+#ifdef MPLAB_PIC32MX_PORT
+	#include "../../Source/portable/MPLAB/PIC32MX/portmacro.h"
+#endif
+
+#ifdef _FEDPICC
+	#include "libFreeRTOS/Include/portmacro.h"
+#endif
+
+#ifdef SDCC_CYGNAL
+	#include "../../Source/portable/SDCC/Cygnal/portmacro.h"
+#endif
+
+#ifdef GCC_ARM7
+	#include "../../Source/portable/GCC/ARM7_LPC2000/portmacro.h"
+#endif
+
+#ifdef GCC_ARM7_ECLIPSE
+	#include "portmacro.h"
+#endif
+
+#ifdef ROWLEY_LPC23xx
+	#include "../../Source/portable/GCC/ARM7_LPC23xx/portmacro.h"
+#endif
+
+#ifdef IAR_MSP430
+	#include "..\..\Source\portable\IAR\MSP430\portmacro.h"
+#endif
+
+#ifdef GCC_MSP430
+	#include "../../Source/portable/GCC/MSP430F449/portmacro.h"
+#endif
+
+#ifdef ROWLEY_MSP430
+	#include "../../Source/portable/Rowley/MSP430F449/portmacro.h"
+#endif
+
+#ifdef ARM7_LPC21xx_KEIL_RVDS
+	#include "..\..\Source\portable\RVDS\ARM7_LPC21xx\portmacro.h"
+#endif
+
+#ifdef SAM7_GCC
+	#include "../../Source/portable/GCC/ARM7_AT91SAM7S/portmacro.h"
+#endif
+
+#ifdef SAM7_IAR
+	#include "..\..\Source\portable\IAR\AtmelSAM7S64\portmacro.h"
+#endif
+
+#ifdef SAM9XE_IAR
+	#include "..\..\Source\portable\IAR\AtmelSAM9XE\portmacro.h"
+#endif
+
+#ifdef LPC2000_IAR
+	#include "..\..\Source\portable\IAR\LPC2000\portmacro.h"
+#endif
+
+#ifdef STR71X_IAR
+	#include "..\..\Source\portable\IAR\STR71x\portmacro.h"
+#endif
+
+#ifdef STR75X_IAR
+	#include "..\..\Source\portable\IAR\STR75x\portmacro.h"
+#endif
+
+#ifdef STR75X_GCC
+	#include "..\..\Source\portable\GCC\STR75x\portmacro.h"
+#endif
+
+#ifdef STR91X_IAR
+	#include "..\..\Source\portable\IAR\STR91x\portmacro.h"
+#endif
+
+#ifdef GCC_H8S
+	#include "../../Source/portable/GCC/H8S2329/portmacro.h"
+#endif
+
+#ifdef GCC_AT91FR40008
+	#include "../../Source/portable/GCC/ARM7_AT91FR40008/portmacro.h"
+#endif
+
+#ifdef RVDS_ARMCM3_LM3S102
+	#include "../../Source/portable/RVDS/ARM_CM3/portmacro.h"
+#endif
+
+#ifdef GCC_ARMCM3_LM3S102
+	#include "../../Source/portable/GCC/ARM_CM3/portmacro.h"
+#endif
+
+#ifdef GCC_ARMCM3
+	#include "../../Source/portable/GCC/ARM_CM3/portmacro.h"
+#endif
+
+#ifdef IAR_ARM_CM3
+	#include "../../Source/portable/IAR/ARM_CM3/portmacro.h"
+#endif
+
+#ifdef IAR_ARMCM3_LM
+	#include "../../Source/portable/IAR/ARM_CM3/portmacro.h"
+#endif
+
+#ifdef HCS12_CODE_WARRIOR
+	#include "../../Source/portable/CodeWarrior/HCS12/portmacro.h"
+#endif
+
+#ifdef MICROBLAZE_GCC
+	#include "../../Source/portable/GCC/MicroBlaze/portmacro.h"
+#endif
+
+#ifdef TERN_EE
+	#include "..\..\Source\portable\Paradigm\Tern_EE\small\portmacro.h"
+#endif
+
+#ifdef GCC_HCS12
+	#include "../../Source/portable/GCC/HCS12/portmacro.h"
+#endif
+
+#ifdef GCC_MCF5235
+    #include "../../Source/portable/GCC/MCF5235/portmacro.h"
+#endif
+
+#ifdef COLDFIRE_V2_GCC
+	#include "../../../Source/portable/GCC/ColdFire_V2/portmacro.h"
+#endif
+
+#ifdef COLDFIRE_V2_CODEWARRIOR
+	#include "../../Source/portable/CodeWarrior/ColdFire_V2/portmacro.h"
+#endif
+
+#ifdef GCC_PPC405
+	#include "../../Source/portable/GCC/PPC405_Xilinx/portmacro.h"
+#endif
+
+#ifdef GCC_PPC440
+	#include "../../Source/portable/GCC/PPC440_Xilinx/portmacro.h"
+#endif
+
+#ifdef _16FX_SOFTUNE
+	#include "..\..\Source\portable\Softune\MB96340\portmacro.h"
+#endif
+
+#ifdef BCC_INDUSTRIAL_PC_PORT
+	/* A short file name has to be used in place of the normal
+	FreeRTOSConfig.h when using the Borland compiler. */
+	#include "frconfig.h"
+	#include "..\portable\BCC\16BitDOS\PC\prtmacro.h"
+    typedef void ( __interrupt __far *pxISR )();
+#endif
+
+#ifdef BCC_FLASH_LITE_186_PORT
+	/* A short file name has to be used in place of the normal
+	FreeRTOSConfig.h when using the Borland compiler. */
+	#include "frconfig.h"
+	#include "..\portable\BCC\16BitDOS\flsh186\prtmacro.h"
+    typedef void ( __interrupt __far *pxISR )();
+#endif
+
+#ifdef __GNUC__
+   #ifdef __AVR32_AVR32A__
+	   #include "portmacro.h"
+   #endif
+#endif
+
+#ifdef __ICCAVR32__
+   #ifdef __CORE__
+      #if __CORE__ == __AVR32A__
+	      #include "portmacro.h"
+      #endif
+   #endif
+#endif
+
+#ifdef __91467D
+	#include "portmacro.h"
+#endif
+
+#ifdef __96340
+	#include "portmacro.h"
+#endif
+
+
+#ifdef __IAR_V850ES_Fx3__
+	#include "../../Source/portable/IAR/V850ES/portmacro.h"
+#endif
+
+#ifdef __IAR_V850ES_Jx3__
+	#include "../../Source/portable/IAR/V850ES/portmacro.h"
+#endif
+
+#ifdef __IAR_V850ES_Jx3_L__
+	#include "../../Source/portable/IAR/V850ES/portmacro.h"
+#endif
+
+#ifdef __IAR_V850ES_Jx2__
+	#include "../../Source/portable/IAR/V850ES/portmacro.h"
+#endif
+
+#ifdef __IAR_V850ES_Hx2__
+	#include "../../Source/portable/IAR/V850ES/portmacro.h"
+#endif
+
+#ifdef __IAR_78K0R_Kx3__
+	#include "../../Source/portable/IAR/78K0R/portmacro.h"
+#endif
+
+#ifdef __IAR_78K0R_Kx3L__
+	#include "../../Source/portable/IAR/78K0R/portmacro.h"
+#endif
+
+#endif /* DEPRECATED_DEFINITIONS_H */
+
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h b/Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h
new file mode 100644
index 0000000..a87fdf3
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h
@@ -0,0 +1,757 @@
+/*
+ * FreeRTOS Kernel V10.3.1
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef EVENT_GROUPS_H
+#define EVENT_GROUPS_H
+
+#ifndef INC_FREERTOS_H
+	#error "include FreeRTOS.h" must appear in source files before "include event_groups.h"
+#endif
+
+/* FreeRTOS includes. */
+#include "timers.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * An event group is a collection of bits to which an application can assign a
+ * meaning.  For example, an application may create an event group to convey
+ * the status of various CAN bus related events in which bit 0 might mean "A CAN
+ * message has been received and is ready for processing", bit 1 might mean "The
+ * application has queued a message that is ready for sending onto the CAN
+ * network", and bit 2 might mean "It is time to send a SYNC message onto the
+ * CAN network" etc.  A task can then test the bit values to see which events
+ * are active, and optionally enter the Blocked state to wait for a specified
+ * bit or a group of specified bits to be active.  To continue the CAN bus
+ * example, a CAN controlling task can enter the Blocked state (and therefore
+ * not consume any processing time) until either bit 0, bit 1 or bit 2 are
+ * active, at which time the bit that was actually active would inform the task
+ * which action it had to take (process a received message, send a message, or
+ * send a SYNC).
+ *
+ * The event groups implementation contains intelligence to avoid race
+ * conditions that would otherwise occur were an application to use a simple
+ * variable for the same purpose.  This is particularly important with respect
+ * to when a bit within an event group is to be cleared, and when bits have to
+ * be set and then tested atomically - as is the case where event groups are
+ * used to create a synchronisation point between multiple tasks (a
+ * 'rendezvous').
+ *
+ * \defgroup EventGroup
+ */
+
+
+
+/**
+ * event_groups.h
+ *
+ * Type by which event groups are referenced.  For example, a call to
+ * xEventGroupCreate() returns an EventGroupHandle_t variable that can then
+ * be used as a parameter to other event group functions.
+ *
+ * \defgroup EventGroupHandle_t EventGroupHandle_t
+ * \ingroup EventGroup
+ */
+struct EventGroupDef_t;
+typedef struct EventGroupDef_t * EventGroupHandle_t;
+
+/*
+ * The type that holds event bits always matches TickType_t - therefore the
+ * number of bits it holds is set by configUSE_16_BIT_TICKS (16 bits if set to 1,
+ * 32 bits if set to 0.
+ *
+ * \defgroup EventBits_t EventBits_t
+ * \ingroup EventGroup
+ */
+typedef TickType_t EventBits_t;
+
+/**
+ * event_groups.h
+ *<pre>
+ EventGroupHandle_t xEventGroupCreate( void );
+ </pre>
+ *
+ * Create a new event group.
+ *
+ * Internally, within the FreeRTOS implementation, event groups use a [small]
+ * block of memory, in which the event group's structure is stored.  If an event
+ * groups is created using xEventGropuCreate() then the required memory is
+ * automatically dynamically allocated inside the xEventGroupCreate() function.
+ * (see http://www.freertos.org/a00111.html).  If an event group is created
+ * using xEventGropuCreateStatic() then the application writer must instead
+ * provide the memory that will get used by the event group.
+ * xEventGroupCreateStatic() therefore allows an event group to be created
+ * without using any dynamic memory allocation.
+ *
+ * Although event groups are not related to ticks, for internal implementation
+ * reasons the number of bits available for use in an event group is dependent
+ * on the configUSE_16_BIT_TICKS setting in FreeRTOSConfig.h.  If
+ * configUSE_16_BIT_TICKS is 1 then each event group contains 8 usable bits (bit
+ * 0 to bit 7).  If configUSE_16_BIT_TICKS is set to 0 then each event group has
+ * 24 usable bits (bit 0 to bit 23).  The EventBits_t type is used to store
+ * event bits within an event group.
+ *
+ * @return If the event group was created then a handle to the event group is
+ * returned.  If there was insufficient FreeRTOS heap available to create the
+ * event group then NULL is returned.  See http://www.freertos.org/a00111.html
+ *
+ * Example usage:
+   <pre>
+	// Declare a variable to hold the created event group.
+	EventGroupHandle_t xCreatedEventGroup;
+
+	// Attempt to create the event group.
+	xCreatedEventGroup = xEventGroupCreate();
+
+	// Was the event group created successfully?
+	if( xCreatedEventGroup == NULL )
+	{
+		// The event group was not created because there was insufficient
+		// FreeRTOS heap available.
+	}
+	else
+	{
+		// The event group was created.
+	}
+   </pre>
+ * \defgroup xEventGroupCreate xEventGroupCreate
+ * \ingroup EventGroup
+ */
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+	EventGroupHandle_t xEventGroupCreate( void ) PRIVILEGED_FUNCTION;
+#endif
+
+/**
+ * event_groups.h
+ *<pre>
+ EventGroupHandle_t xEventGroupCreateStatic( EventGroupHandle_t * pxEventGroupBuffer );
+ </pre>
+ *
+ * Create a new event group.
+ *
+ * Internally, within the FreeRTOS implementation, event groups use a [small]
+ * block of memory, in which the event group's structure is stored.  If an event
+ * groups is created using xEventGropuCreate() then the required memory is
+ * automatically dynamically allocated inside the xEventGroupCreate() function.
+ * (see http://www.freertos.org/a00111.html).  If an event group is created
+ * using xEventGropuCreateStatic() then the application writer must instead
+ * provide the memory that will get used by the event group.
+ * xEventGroupCreateStatic() therefore allows an event group to be created
+ * without using any dynamic memory allocation.
+ *
+ * Although event groups are not related to ticks, for internal implementation
+ * reasons the number of bits available for use in an event group is dependent
+ * on the configUSE_16_BIT_TICKS setting in FreeRTOSConfig.h.  If
+ * configUSE_16_BIT_TICKS is 1 then each event group contains 8 usable bits (bit
+ * 0 to bit 7).  If configUSE_16_BIT_TICKS is set to 0 then each event group has
+ * 24 usable bits (bit 0 to bit 23).  The EventBits_t type is used to store
+ * event bits within an event group.
+ *
+ * @param pxEventGroupBuffer pxEventGroupBuffer must point to a variable of type
+ * StaticEventGroup_t, which will be then be used to hold the event group's data
+ * structures, removing the need for the memory to be allocated dynamically.
+ *
+ * @return If the event group was created then a handle to the event group is
+ * returned.  If pxEventGroupBuffer was NULL then NULL is returned.
+ *
+ * Example usage:
+   <pre>
+	// StaticEventGroup_t is a publicly accessible structure that has the same
+	// size and alignment requirements as the real event group structure.  It is
+	// provided as a mechanism for applications to know the size of the event
+	// group (which is dependent on the architecture and configuration file
+	// settings) without breaking the strict data hiding policy by exposing the
+	// real event group internals.  This StaticEventGroup_t variable is passed
+	// into the xSemaphoreCreateEventGroupStatic() function and is used to store
+	// the event group's data structures
+	StaticEventGroup_t xEventGroupBuffer;
+
+	// Create the event group without dynamically allocating any memory.
+	xEventGroup = xEventGroupCreateStatic( &xEventGroupBuffer );
+   </pre>
+ */
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+	EventGroupHandle_t xEventGroupCreateStatic( StaticEventGroup_t *pxEventGroupBuffer ) PRIVILEGED_FUNCTION;
+#endif
+
+/**
+ * event_groups.h
+ *<pre>
+	EventBits_t xEventGroupWaitBits( 	EventGroupHandle_t xEventGroup,
+										const EventBits_t uxBitsToWaitFor,
+										const BaseType_t xClearOnExit,
+										const BaseType_t xWaitForAllBits,
+										const TickType_t xTicksToWait );
+ </pre>
+ *
+ * [Potentially] block to wait for one or more bits to be set within a
+ * previously created event group.
+ *
+ * This function cannot be called from an interrupt.
+ *
+ * @param xEventGroup The event group in which the bits are being tested.  The
+ * event group must have previously been created using a call to
+ * xEventGroupCreate().
+ *
+ * @param uxBitsToWaitFor A bitwise value that indicates the bit or bits to test
+ * inside the event group.  For example, to wait for bit 0 and/or bit 2 set
+ * uxBitsToWaitFor to 0x05.  To wait for bits 0 and/or bit 1 and/or bit 2 set
+ * uxBitsToWaitFor to 0x07.  Etc.
+ *
+ * @param xClearOnExit If xClearOnExit is set to pdTRUE then any bits within
+ * uxBitsToWaitFor that are set within the event group will be cleared before
+ * xEventGroupWaitBits() returns if the wait condition was met (if the function
+ * returns for a reason other than a timeout).  If xClearOnExit is set to
+ * pdFALSE then the bits set in the event group are not altered when the call to
+ * xEventGroupWaitBits() returns.
+ *
+ * @param xWaitForAllBits If xWaitForAllBits is set to pdTRUE then
+ * xEventGroupWaitBits() will return when either all the bits in uxBitsToWaitFor
+ * are set or the specified block time expires.  If xWaitForAllBits is set to
+ * pdFALSE then xEventGroupWaitBits() will return when any one of the bits set
+ * in uxBitsToWaitFor is set or the specified block time expires.  The block
+ * time is specified by the xTicksToWait parameter.
+ *
+ * @param xTicksToWait The maximum amount of time (specified in 'ticks') to wait
+ * for one/all (depending on the xWaitForAllBits value) of the bits specified by
+ * uxBitsToWaitFor to become set.
+ *
+ * @return The value of the event group at the time either the bits being waited
+ * for became set, or the block time expired.  Test the return value to know
+ * which bits were set.  If xEventGroupWaitBits() returned because its timeout
+ * expired then not all the bits being waited for will be set.  If
+ * xEventGroupWaitBits() returned because the bits it was waiting for were set
+ * then the returned value is the event group value before any bits were
+ * automatically cleared in the case that xClearOnExit parameter was set to
+ * pdTRUE.
+ *
+ * Example usage:
+   <pre>
+   #define BIT_0	( 1 << 0 )
+   #define BIT_4	( 1 << 4 )
+
+   void aFunction( EventGroupHandle_t xEventGroup )
+   {
+   EventBits_t uxBits;
+   const TickType_t xTicksToWait = 100 / portTICK_PERIOD_MS;
+
+		// Wait a maximum of 100ms for either bit 0 or bit 4 to be set within
+		// the event group.  Clear the bits before exiting.
+		uxBits = xEventGroupWaitBits(
+					xEventGroup,	// The event group being tested.
+					BIT_0 | BIT_4,	// The bits within the event group to wait for.
+					pdTRUE,			// BIT_0 and BIT_4 should be cleared before returning.
+					pdFALSE,		// Don't wait for both bits, either bit will do.
+					xTicksToWait );	// Wait a maximum of 100ms for either bit to be set.
+
+		if( ( uxBits & ( BIT_0 | BIT_4 ) ) == ( BIT_0 | BIT_4 ) )
+		{
+			// xEventGroupWaitBits() returned because both bits were set.
+		}
+		else if( ( uxBits & BIT_0 ) != 0 )
+		{
+			// xEventGroupWaitBits() returned because just BIT_0 was set.
+		}
+		else if( ( uxBits & BIT_4 ) != 0 )
+		{
+			// xEventGroupWaitBits() returned because just BIT_4 was set.
+		}
+		else
+		{
+			// xEventGroupWaitBits() returned because xTicksToWait ticks passed
+			// without either BIT_0 or BIT_4 becoming set.
+		}
+   }
+   </pre>
+ * \defgroup xEventGroupWaitBits xEventGroupWaitBits
+ * \ingroup EventGroup
+ */
+EventBits_t xEventGroupWaitBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToWaitFor, const BaseType_t xClearOnExit, const BaseType_t xWaitForAllBits, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+/**
+ * event_groups.h
+ *<pre>
+	EventBits_t xEventGroupClearBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear );
+ </pre>
+ *
+ * Clear bits within an event group.  This function cannot be called from an
+ * interrupt.
+ *
+ * @param xEventGroup The event group in which the bits are to be cleared.
+ *
+ * @param uxBitsToClear A bitwise value that indicates the bit or bits to clear
+ * in the event group.  For example, to clear bit 3 only, set uxBitsToClear to
+ * 0x08.  To clear bit 3 and bit 0 set uxBitsToClear to 0x09.
+ *
+ * @return The value of the event group before the specified bits were cleared.
+ *
+ * Example usage:
+   <pre>
+   #define BIT_0	( 1 << 0 )
+   #define BIT_4	( 1 << 4 )
+
+   void aFunction( EventGroupHandle_t xEventGroup )
+   {
+   EventBits_t uxBits;
+
+		// Clear bit 0 and bit 4 in xEventGroup.
+		uxBits = xEventGroupClearBits(
+								xEventGroup,	// The event group being updated.
+								BIT_0 | BIT_4 );// The bits being cleared.
+
+		if( ( uxBits & ( BIT_0 | BIT_4 ) ) == ( BIT_0 | BIT_4 ) )
+		{
+			// Both bit 0 and bit 4 were set before xEventGroupClearBits() was
+			// called.  Both will now be clear (not set).
+		}
+		else if( ( uxBits & BIT_0 ) != 0 )
+		{
+			// Bit 0 was set before xEventGroupClearBits() was called.  It will
+			// now be clear.
+		}
+		else if( ( uxBits & BIT_4 ) != 0 )
+		{
+			// Bit 4 was set before xEventGroupClearBits() was called.  It will
+			// now be clear.
+		}
+		else
+		{
+			// Neither bit 0 nor bit 4 were set in the first place.
+		}
+   }
+   </pre>
+ * \defgroup xEventGroupClearBits xEventGroupClearBits
+ * \ingroup EventGroup
+ */
+EventBits_t xEventGroupClearBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear ) PRIVILEGED_FUNCTION;
+
+/**
+ * event_groups.h
+ *<pre>
+	BaseType_t xEventGroupClearBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet );
+ </pre>
+ *
+ * A version of xEventGroupClearBits() that can be called from an interrupt.
+ *
+ * Setting bits in an event group is not a deterministic operation because there
+ * are an unknown number of tasks that may be waiting for the bit or bits being
+ * set.  FreeRTOS does not allow nondeterministic operations to be performed
+ * while interrupts are disabled, so protects event groups that are accessed
+ * from tasks by suspending the scheduler rather than disabling interrupts.  As
+ * a result event groups cannot be accessed directly from an interrupt service
+ * routine.  Therefore xEventGroupClearBitsFromISR() sends a message to the
+ * timer task to have the clear operation performed in the context of the timer
+ * task.
+ *
+ * @param xEventGroup The event group in which the bits are to be cleared.
+ *
+ * @param uxBitsToClear A bitwise value that indicates the bit or bits to clear.
+ * For example, to clear bit 3 only, set uxBitsToClear to 0x08.  To clear bit 3
+ * and bit 0 set uxBitsToClear to 0x09.
+ *
+ * @return If the request to execute the function was posted successfully then
+ * pdPASS is returned, otherwise pdFALSE is returned.  pdFALSE will be returned
+ * if the timer service queue was full.
+ *
+ * Example usage:
+   <pre>
+   #define BIT_0	( 1 << 0 )
+   #define BIT_4	( 1 << 4 )
+
+   // An event group which it is assumed has already been created by a call to
+   // xEventGroupCreate().
+   EventGroupHandle_t xEventGroup;
+
+   void anInterruptHandler( void )
+   {
+		// Clear bit 0 and bit 4 in xEventGroup.
+		xResult = xEventGroupClearBitsFromISR(
+							xEventGroup,	 // The event group being updated.
+							BIT_0 | BIT_4 ); // The bits being set.
+
+		if( xResult == pdPASS )
+		{
+			// The message was posted successfully.
+		}
+  }
+   </pre>
+ * \defgroup xEventGroupClearBitsFromISR xEventGroupClearBitsFromISR
+ * \ingroup EventGroup
+ */
+#if( configUSE_TRACE_FACILITY == 1 )
+	BaseType_t xEventGroupClearBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear ) PRIVILEGED_FUNCTION;
+#else
+	#define xEventGroupClearBitsFromISR( xEventGroup, uxBitsToClear ) xTimerPendFunctionCallFromISR( vEventGroupClearBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToClear, NULL )
+#endif
+
+/**
+ * event_groups.h
+ *<pre>
+	EventBits_t xEventGroupSetBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet );
+ </pre>
+ *
+ * Set bits within an event group.
+ * This function cannot be called from an interrupt.  xEventGroupSetBitsFromISR()
+ * is a version that can be called from an interrupt.
+ *
+ * Setting bits in an event group will automatically unblock tasks that are
+ * blocked waiting for the bits.
+ *
+ * @param xEventGroup The event group in which the bits are to be set.
+ *
+ * @param uxBitsToSet A bitwise value that indicates the bit or bits to set.
+ * For example, to set bit 3 only, set uxBitsToSet to 0x08.  To set bit 3
+ * and bit 0 set uxBitsToSet to 0x09.
+ *
+ * @return The value of the event group at the time the call to
+ * xEventGroupSetBits() returns.  There are two reasons why the returned value
+ * might have the bits specified by the uxBitsToSet parameter cleared.  First,
+ * if setting a bit results in a task that was waiting for the bit leaving the
+ * blocked state then it is possible the bit will be cleared automatically
+ * (see the xClearBitOnExit parameter of xEventGroupWaitBits()).  Second, any
+ * unblocked (or otherwise Ready state) task that has a priority above that of
+ * the task that called xEventGroupSetBits() will execute and may change the
+ * event group value before the call to xEventGroupSetBits() returns.
+ *
+ * Example usage:
+   <pre>
+   #define BIT_0	( 1 << 0 )
+   #define BIT_4	( 1 << 4 )
+
+   void aFunction( EventGroupHandle_t xEventGroup )
+   {
+   EventBits_t uxBits;
+
+		// Set bit 0 and bit 4 in xEventGroup.
+		uxBits = xEventGroupSetBits(
+							xEventGroup,	// The event group being updated.
+							BIT_0 | BIT_4 );// The bits being set.
+
+		if( ( uxBits & ( BIT_0 | BIT_4 ) ) == ( BIT_0 | BIT_4 ) )
+		{
+			// Both bit 0 and bit 4 remained set when the function returned.
+		}
+		else if( ( uxBits & BIT_0 ) != 0 )
+		{
+			// Bit 0 remained set when the function returned, but bit 4 was
+			// cleared.  It might be that bit 4 was cleared automatically as a
+			// task that was waiting for bit 4 was removed from the Blocked
+			// state.
+		}
+		else if( ( uxBits & BIT_4 ) != 0 )
+		{
+			// Bit 4 remained set when the function returned, but bit 0 was
+			// cleared.  It might be that bit 0 was cleared automatically as a
+			// task that was waiting for bit 0 was removed from the Blocked
+			// state.
+		}
+		else
+		{
+			// Neither bit 0 nor bit 4 remained set.  It might be that a task
+			// was waiting for both of the bits to be set, and the bits were
+			// cleared as the task left the Blocked state.
+		}
+   }
+   </pre>
+ * \defgroup xEventGroupSetBits xEventGroupSetBits
+ * \ingroup EventGroup
+ */
+EventBits_t xEventGroupSetBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet ) PRIVILEGED_FUNCTION;
+
+/**
+ * event_groups.h
+ *<pre>
+	BaseType_t xEventGroupSetBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, BaseType_t *pxHigherPriorityTaskWoken );
+ </pre>
+ *
+ * A version of xEventGroupSetBits() that can be called from an interrupt.
+ *
+ * Setting bits in an event group is not a deterministic operation because there
+ * are an unknown number of tasks that may be waiting for the bit or bits being
+ * set.  FreeRTOS does not allow nondeterministic operations to be performed in
+ * interrupts or from critical sections.  Therefore xEventGroupSetBitsFromISR()
+ * sends a message to the timer task to have the set operation performed in the
+ * context of the timer task - where a scheduler lock is used in place of a
+ * critical section.
+ *
+ * @param xEventGroup The event group in which the bits are to be set.
+ *
+ * @param uxBitsToSet A bitwise value that indicates the bit or bits to set.
+ * For example, to set bit 3 only, set uxBitsToSet to 0x08.  To set bit 3
+ * and bit 0 set uxBitsToSet to 0x09.
+ *
+ * @param pxHigherPriorityTaskWoken As mentioned above, calling this function
+ * will result in a message being sent to the timer daemon task.  If the
+ * priority of the timer daemon task is higher than the priority of the
+ * currently running task (the task the interrupt interrupted) then
+ * *pxHigherPriorityTaskWoken will be set to pdTRUE by
+ * xEventGroupSetBitsFromISR(), indicating that a context switch should be
+ * requested before the interrupt exits.  For that reason
+ * *pxHigherPriorityTaskWoken must be initialised to pdFALSE.  See the
+ * example code below.
+ *
+ * @return If the request to execute the function was posted successfully then
+ * pdPASS is returned, otherwise pdFALSE is returned.  pdFALSE will be returned
+ * if the timer service queue was full.
+ *
+ * Example usage:
+   <pre>
+   #define BIT_0	( 1 << 0 )
+   #define BIT_4	( 1 << 4 )
+
+   // An event group which it is assumed has already been created by a call to
+   // xEventGroupCreate().
+   EventGroupHandle_t xEventGroup;
+
+   void anInterruptHandler( void )
+   {
+   BaseType_t xHigherPriorityTaskWoken, xResult;
+
+		// xHigherPriorityTaskWoken must be initialised to pdFALSE.
+		xHigherPriorityTaskWoken = pdFALSE;
+
+		// Set bit 0 and bit 4 in xEventGroup.
+		xResult = xEventGroupSetBitsFromISR(
+							xEventGroup,	// The event group being updated.
+							BIT_0 | BIT_4   // The bits being set.
+							&xHigherPriorityTaskWoken );
+
+		// Was the message posted successfully?
+		if( xResult == pdPASS )
+		{
+			// If xHigherPriorityTaskWoken is now set to pdTRUE then a context
+			// switch should be requested.  The macro used is port specific and
+			// will be either portYIELD_FROM_ISR() or portEND_SWITCHING_ISR() -
+			// refer to the documentation page for the port being used.
+			portYIELD_FROM_ISR( xHigherPriorityTaskWoken );
+		}
+  }
+   </pre>
+ * \defgroup xEventGroupSetBitsFromISR xEventGroupSetBitsFromISR
+ * \ingroup EventGroup
+ */
+#if( configUSE_TRACE_FACILITY == 1 )
+	BaseType_t xEventGroupSetBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, BaseType_t *pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+#else
+	#define xEventGroupSetBitsFromISR( xEventGroup, uxBitsToSet, pxHigherPriorityTaskWoken ) xTimerPendFunctionCallFromISR( vEventGroupSetBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToSet, pxHigherPriorityTaskWoken )
+#endif
+
+/**
+ * event_groups.h
+ *<pre>
+	EventBits_t xEventGroupSync(	EventGroupHandle_t xEventGroup,
+									const EventBits_t uxBitsToSet,
+									const EventBits_t uxBitsToWaitFor,
+									TickType_t xTicksToWait );
+ </pre>
+ *
+ * Atomically set bits within an event group, then wait for a combination of
+ * bits to be set within the same event group.  This functionality is typically
+ * used to synchronise multiple tasks, where each task has to wait for the other
+ * tasks to reach a synchronisation point before proceeding.
+ *
+ * This function cannot be used from an interrupt.
+ *
+ * The function will return before its block time expires if the bits specified
+ * by the uxBitsToWait parameter are set, or become set within that time.  In
+ * this case all the bits specified by uxBitsToWait will be automatically
+ * cleared before the function returns.
+ *
+ * @param xEventGroup The event group in which the bits are being tested.  The
+ * event group must have previously been created using a call to
+ * xEventGroupCreate().
+ *
+ * @param uxBitsToSet The bits to set in the event group before determining
+ * if, and possibly waiting for, all the bits specified by the uxBitsToWait
+ * parameter are set.
+ *
+ * @param uxBitsToWaitFor A bitwise value that indicates the bit or bits to test
+ * inside the event group.  For example, to wait for bit 0 and bit 2 set
+ * uxBitsToWaitFor to 0x05.  To wait for bits 0 and bit 1 and bit 2 set
+ * uxBitsToWaitFor to 0x07.  Etc.
+ *
+ * @param xTicksToWait The maximum amount of time (specified in 'ticks') to wait
+ * for all of the bits specified by uxBitsToWaitFor to become set.
+ *
+ * @return The value of the event group at the time either the bits being waited
+ * for became set, or the block time expired.  Test the return value to know
+ * which bits were set.  If xEventGroupSync() returned because its timeout
+ * expired then not all the bits being waited for will be set.  If
+ * xEventGroupSync() returned because all the bits it was waiting for were
+ * set then the returned value is the event group value before any bits were
+ * automatically cleared.
+ *
+ * Example usage:
+ <pre>
+ // Bits used by the three tasks.
+ #define TASK_0_BIT		( 1 << 0 )
+ #define TASK_1_BIT		( 1 << 1 )
+ #define TASK_2_BIT		( 1 << 2 )
+
+ #define ALL_SYNC_BITS ( TASK_0_BIT | TASK_1_BIT | TASK_2_BIT )
+
+ // Use an event group to synchronise three tasks.  It is assumed this event
+ // group has already been created elsewhere.
+ EventGroupHandle_t xEventBits;
+
+ void vTask0( void *pvParameters )
+ {
+ EventBits_t uxReturn;
+ TickType_t xTicksToWait = 100 / portTICK_PERIOD_MS;
+
+	 for( ;; )
+	 {
+		// Perform task functionality here.
+
+		// Set bit 0 in the event flag to note this task has reached the
+		// sync point.  The other two tasks will set the other two bits defined
+		// by ALL_SYNC_BITS.  All three tasks have reached the synchronisation
+		// point when all the ALL_SYNC_BITS are set.  Wait a maximum of 100ms
+		// for this to happen.
+		uxReturn = xEventGroupSync( xEventBits, TASK_0_BIT, ALL_SYNC_BITS, xTicksToWait );
+
+		if( ( uxReturn & ALL_SYNC_BITS ) == ALL_SYNC_BITS )
+		{
+			// All three tasks reached the synchronisation point before the call
+			// to xEventGroupSync() timed out.
+		}
+	}
+ }
+
+ void vTask1( void *pvParameters )
+ {
+	 for( ;; )
+	 {
+		// Perform task functionality here.
+
+		// Set bit 1 in the event flag to note this task has reached the
+		// synchronisation point.  The other two tasks will set the other two
+		// bits defined by ALL_SYNC_BITS.  All three tasks have reached the
+		// synchronisation point when all the ALL_SYNC_BITS are set.  Wait
+		// indefinitely for this to happen.
+		xEventGroupSync( xEventBits, TASK_1_BIT, ALL_SYNC_BITS, portMAX_DELAY );
+
+		// xEventGroupSync() was called with an indefinite block time, so
+		// this task will only reach here if the syncrhonisation was made by all
+		// three tasks, so there is no need to test the return value.
+	 }
+ }
+
+ void vTask2( void *pvParameters )
+ {
+	 for( ;; )
+	 {
+		// Perform task functionality here.
+
+		// Set bit 2 in the event flag to note this task has reached the
+		// synchronisation point.  The other two tasks will set the other two
+		// bits defined by ALL_SYNC_BITS.  All three tasks have reached the
+		// synchronisation point when all the ALL_SYNC_BITS are set.  Wait
+		// indefinitely for this to happen.
+		xEventGroupSync( xEventBits, TASK_2_BIT, ALL_SYNC_BITS, portMAX_DELAY );
+
+		// xEventGroupSync() was called with an indefinite block time, so
+		// this task will only reach here if the syncrhonisation was made by all
+		// three tasks, so there is no need to test the return value.
+	}
+ }
+
+ </pre>
+ * \defgroup xEventGroupSync xEventGroupSync
+ * \ingroup EventGroup
+ */
+EventBits_t xEventGroupSync( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, const EventBits_t uxBitsToWaitFor, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+
+/**
+ * event_groups.h
+ *<pre>
+	EventBits_t xEventGroupGetBits( EventGroupHandle_t xEventGroup );
+ </pre>
+ *
+ * Returns the current value of the bits in an event group.  This function
+ * cannot be used from an interrupt.
+ *
+ * @param xEventGroup The event group being queried.
+ *
+ * @return The event group bits at the time xEventGroupGetBits() was called.
+ *
+ * \defgroup xEventGroupGetBits xEventGroupGetBits
+ * \ingroup EventGroup
+ */
+#define xEventGroupGetBits( xEventGroup ) xEventGroupClearBits( xEventGroup, 0 )
+
+/**
+ * event_groups.h
+ *<pre>
+	EventBits_t xEventGroupGetBitsFromISR( EventGroupHandle_t xEventGroup );
+ </pre>
+ *
+ * A version of xEventGroupGetBits() that can be called from an ISR.
+ *
+ * @param xEventGroup The event group being queried.
+ *
+ * @return The event group bits at the time xEventGroupGetBitsFromISR() was called.
+ *
+ * \defgroup xEventGroupGetBitsFromISR xEventGroupGetBitsFromISR
+ * \ingroup EventGroup
+ */
+EventBits_t xEventGroupGetBitsFromISR( EventGroupHandle_t xEventGroup ) PRIVILEGED_FUNCTION;
+
+/**
+ * event_groups.h
+ *<pre>
+	void xEventGroupDelete( EventGroupHandle_t xEventGroup );
+ </pre>
+ *
+ * Delete an event group that was previously created by a call to
+ * xEventGroupCreate().  Tasks that are blocked on the event group will be
+ * unblocked and obtain 0 as the event group's value.
+ *
+ * @param xEventGroup The event group being deleted.
+ */
+void vEventGroupDelete( EventGroupHandle_t xEventGroup ) PRIVILEGED_FUNCTION;
+
+/* For internal use only. */
+void vEventGroupSetBitsCallback( void *pvEventGroup, const uint32_t ulBitsToSet ) PRIVILEGED_FUNCTION;
+void vEventGroupClearBitsCallback( void *pvEventGroup, const uint32_t ulBitsToClear ) PRIVILEGED_FUNCTION;
+
+
+#if (configUSE_TRACE_FACILITY == 1)
+	UBaseType_t uxEventGroupGetNumber( void* xEventGroup ) PRIVILEGED_FUNCTION;
+	void vEventGroupSetNumber( void* xEventGroup, UBaseType_t uxEventGroupNumber ) PRIVILEGED_FUNCTION;
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* EVENT_GROUPS_H */
+
+
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/list.h b/Middlewares/Third_Party/FreeRTOS/Source/include/list.h
new file mode 100644
index 0000000..a3e3024
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/include/list.h
@@ -0,0 +1,412 @@
+/*
+ * FreeRTOS Kernel V10.3.1
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*
+ * This is the list implementation used by the scheduler.  While it is tailored
+ * heavily for the schedulers needs, it is also available for use by
+ * application code.
+ *
+ * list_ts can only store pointers to list_item_ts.  Each ListItem_t contains a
+ * numeric value (xItemValue).  Most of the time the lists are sorted in
+ * descending item value order.
+ *
+ * Lists are created already containing one list item.  The value of this
+ * item is the maximum possible that can be stored, it is therefore always at
+ * the end of the list and acts as a marker.  The list member pxHead always
+ * points to this marker - even though it is at the tail of the list.  This
+ * is because the tail contains a wrap back pointer to the true head of
+ * the list.
+ *
+ * In addition to it's value, each list item contains a pointer to the next
+ * item in the list (pxNext), a pointer to the list it is in (pxContainer)
+ * and a pointer to back to the object that contains it.  These later two
+ * pointers are included for efficiency of list manipulation.  There is
+ * effectively a two way link between the object containing the list item and
+ * the list item itself.
+ *
+ *
+ * \page ListIntroduction List Implementation
+ * \ingroup FreeRTOSIntro
+ */
+
+#ifndef INC_FREERTOS_H
+	#error FreeRTOS.h must be included before list.h
+#endif
+
+#ifndef LIST_H
+#define LIST_H
+
+/*
+ * The list structure members are modified from within interrupts, and therefore
+ * by rights should be declared volatile.  However, they are only modified in a
+ * functionally atomic way (within critical sections of with the scheduler
+ * suspended) and are either passed by reference into a function or indexed via
+ * a volatile variable.  Therefore, in all use cases tested so far, the volatile
+ * qualifier can be omitted in order to provide a moderate performance
+ * improvement without adversely affecting functional behaviour.  The assembly
+ * instructions generated by the IAR, ARM and GCC compilers when the respective
+ * compiler's options were set for maximum optimisation has been inspected and
+ * deemed to be as intended.  That said, as compiler technology advances, and
+ * especially if aggressive cross module optimisation is used (a use case that
+ * has not been exercised to any great extend) then it is feasible that the
+ * volatile qualifier will be needed for correct optimisation.  It is expected
+ * that a compiler removing essential code because, without the volatile
+ * qualifier on the list structure members and with aggressive cross module
+ * optimisation, the compiler deemed the code unnecessary will result in
+ * complete and obvious failure of the scheduler.  If this is ever experienced
+ * then the volatile qualifier can be inserted in the relevant places within the
+ * list structures by simply defining configLIST_VOLATILE to volatile in
+ * FreeRTOSConfig.h (as per the example at the bottom of this comment block).
+ * If configLIST_VOLATILE is not defined then the preprocessor directives below
+ * will simply #define configLIST_VOLATILE away completely.
+ *
+ * To use volatile list structure members then add the following line to
+ * FreeRTOSConfig.h (without the quotes):
+ * "#define configLIST_VOLATILE volatile"
+ */
+#ifndef configLIST_VOLATILE
+	#define configLIST_VOLATILE
+#endif /* configSUPPORT_CROSS_MODULE_OPTIMISATION */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Macros that can be used to place known values within the list structures,
+then check that the known values do not get corrupted during the execution of
+the application.   These may catch the list data structures being overwritten in
+memory.  They will not catch data errors caused by incorrect configuration or
+use of FreeRTOS.*/
+#if( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 0 )
+	/* Define the macros to do nothing. */
+	#define listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE
+	#define listSECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE
+	#define listFIRST_LIST_INTEGRITY_CHECK_VALUE
+	#define listSECOND_LIST_INTEGRITY_CHECK_VALUE
+	#define listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem )
+	#define listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem )
+	#define listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList )
+	#define listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList )
+	#define listTEST_LIST_ITEM_INTEGRITY( pxItem )
+	#define listTEST_LIST_INTEGRITY( pxList )
+#else
+	/* Define macros that add new members into the list structures. */
+	#define listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE				TickType_t xListItemIntegrityValue1;
+	#define listSECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE				TickType_t xListItemIntegrityValue2;
+	#define listFIRST_LIST_INTEGRITY_CHECK_VALUE					TickType_t xListIntegrityValue1;
+	#define listSECOND_LIST_INTEGRITY_CHECK_VALUE					TickType_t xListIntegrityValue2;
+
+	/* Define macros that set the new structure members to known values. */
+	#define listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem )		( pxItem )->xListItemIntegrityValue1 = pdINTEGRITY_CHECK_VALUE
+	#define listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem )	( pxItem )->xListItemIntegrityValue2 = pdINTEGRITY_CHECK_VALUE
+	#define listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList )		( pxList )->xListIntegrityValue1 = pdINTEGRITY_CHECK_VALUE
+	#define listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList )		( pxList )->xListIntegrityValue2 = pdINTEGRITY_CHECK_VALUE
+
+	/* Define macros that will assert if one of the structure members does not
+	contain its expected value. */
+	#define listTEST_LIST_ITEM_INTEGRITY( pxItem )		configASSERT( ( ( pxItem )->xListItemIntegrityValue1 == pdINTEGRITY_CHECK_VALUE ) && ( ( pxItem )->xListItemIntegrityValue2 == pdINTEGRITY_CHECK_VALUE ) )
+	#define listTEST_LIST_INTEGRITY( pxList )			configASSERT( ( ( pxList )->xListIntegrityValue1 == pdINTEGRITY_CHECK_VALUE ) && ( ( pxList )->xListIntegrityValue2 == pdINTEGRITY_CHECK_VALUE ) )
+#endif /* configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES */
+
+
+/*
+ * Definition of the only type of object that a list can contain.
+ */
+struct xLIST;
+struct xLIST_ITEM
+{
+	listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE			/*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
+	configLIST_VOLATILE TickType_t xItemValue;			/*< The value being listed.  In most cases this is used to sort the list in descending order. */
+	struct xLIST_ITEM * configLIST_VOLATILE pxNext;		/*< Pointer to the next ListItem_t in the list. */
+	struct xLIST_ITEM * configLIST_VOLATILE pxPrevious;	/*< Pointer to the previous ListItem_t in the list. */
+	void * pvOwner;										/*< Pointer to the object (normally a TCB) that contains the list item.  There is therefore a two way link between the object containing the list item and the list item itself. */
+	struct xLIST * configLIST_VOLATILE pxContainer;		/*< Pointer to the list in which this list item is placed (if any). */
+	listSECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE			/*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
+};
+typedef struct xLIST_ITEM ListItem_t;					/* For some reason lint wants this as two separate definitions. */
+
+struct xMINI_LIST_ITEM
+{
+	listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE			/*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
+	configLIST_VOLATILE TickType_t xItemValue;
+	struct xLIST_ITEM * configLIST_VOLATILE pxNext;
+	struct xLIST_ITEM * configLIST_VOLATILE pxPrevious;
+};
+typedef struct xMINI_LIST_ITEM MiniListItem_t;
+
+/*
+ * Definition of the type of queue used by the scheduler.
+ */
+typedef struct xLIST
+{
+	listFIRST_LIST_INTEGRITY_CHECK_VALUE				/*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
+	volatile UBaseType_t uxNumberOfItems;
+	ListItem_t * configLIST_VOLATILE pxIndex;			/*< Used to walk through the list.  Points to the last item returned by a call to listGET_OWNER_OF_NEXT_ENTRY (). */
+	MiniListItem_t xListEnd;							/*< List item that contains the maximum possible item value meaning it is always at the end of the list and is therefore used as a marker. */
+	listSECOND_LIST_INTEGRITY_CHECK_VALUE				/*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
+} List_t;
+
+/*
+ * Access macro to set the owner of a list item.  The owner of a list item
+ * is the object (usually a TCB) that contains the list item.
+ *
+ * \page listSET_LIST_ITEM_OWNER listSET_LIST_ITEM_OWNER
+ * \ingroup LinkedList
+ */
+#define listSET_LIST_ITEM_OWNER( pxListItem, pxOwner )		( ( pxListItem )->pvOwner = ( void * ) ( pxOwner ) )
+
+/*
+ * Access macro to get the owner of a list item.  The owner of a list item
+ * is the object (usually a TCB) that contains the list item.
+ *
+ * \page listGET_LIST_ITEM_OWNER listSET_LIST_ITEM_OWNER
+ * \ingroup LinkedList
+ */
+#define listGET_LIST_ITEM_OWNER( pxListItem )	( ( pxListItem )->pvOwner )
+
+/*
+ * Access macro to set the value of the list item.  In most cases the value is
+ * used to sort the list in descending order.
+ *
+ * \page listSET_LIST_ITEM_VALUE listSET_LIST_ITEM_VALUE
+ * \ingroup LinkedList
+ */
+#define listSET_LIST_ITEM_VALUE( pxListItem, xValue )	( ( pxListItem )->xItemValue = ( xValue ) )
+
+/*
+ * Access macro to retrieve the value of the list item.  The value can
+ * represent anything - for example the priority of a task, or the time at
+ * which a task should be unblocked.
+ *
+ * \page listGET_LIST_ITEM_VALUE listGET_LIST_ITEM_VALUE
+ * \ingroup LinkedList
+ */
+#define listGET_LIST_ITEM_VALUE( pxListItem )	( ( pxListItem )->xItemValue )
+
+/*
+ * Access macro to retrieve the value of the list item at the head of a given
+ * list.
+ *
+ * \page listGET_LIST_ITEM_VALUE listGET_LIST_ITEM_VALUE
+ * \ingroup LinkedList
+ */
+#define listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxList )	( ( ( pxList )->xListEnd ).pxNext->xItemValue )
+
+/*
+ * Return the list item at the head of the list.
+ *
+ * \page listGET_HEAD_ENTRY listGET_HEAD_ENTRY
+ * \ingroup LinkedList
+ */
+#define listGET_HEAD_ENTRY( pxList )	( ( ( pxList )->xListEnd ).pxNext )
+
+/*
+ * Return the next list item.
+ *
+ * \page listGET_NEXT listGET_NEXT
+ * \ingroup LinkedList
+ */
+#define listGET_NEXT( pxListItem )	( ( pxListItem )->pxNext )
+
+/*
+ * Return the list item that marks the end of the list
+ *
+ * \page listGET_END_MARKER listGET_END_MARKER
+ * \ingroup LinkedList
+ */
+#define listGET_END_MARKER( pxList )	( ( ListItem_t const * ) ( &( ( pxList )->xListEnd ) ) )
+
+/*
+ * Access macro to determine if a list contains any items.  The macro will
+ * only have the value true if the list is empty.
+ *
+ * \page listLIST_IS_EMPTY listLIST_IS_EMPTY
+ * \ingroup LinkedList
+ */
+#define listLIST_IS_EMPTY( pxList )	( ( ( pxList )->uxNumberOfItems == ( UBaseType_t ) 0 ) ? pdTRUE : pdFALSE )
+
+/*
+ * Access macro to return the number of items in the list.
+ */
+#define listCURRENT_LIST_LENGTH( pxList )	( ( pxList )->uxNumberOfItems )
+
+/*
+ * Access function to obtain the owner of the next entry in a list.
+ *
+ * The list member pxIndex is used to walk through a list.  Calling
+ * listGET_OWNER_OF_NEXT_ENTRY increments pxIndex to the next item in the list
+ * and returns that entry's pxOwner parameter.  Using multiple calls to this
+ * function it is therefore possible to move through every item contained in
+ * a list.
+ *
+ * The pxOwner parameter of a list item is a pointer to the object that owns
+ * the list item.  In the scheduler this is normally a task control block.
+ * The pxOwner parameter effectively creates a two way link between the list
+ * item and its owner.
+ *
+ * @param pxTCB pxTCB is set to the address of the owner of the next list item.
+ * @param pxList The list from which the next item owner is to be returned.
+ *
+ * \page listGET_OWNER_OF_NEXT_ENTRY listGET_OWNER_OF_NEXT_ENTRY
+ * \ingroup LinkedList
+ */
+#define listGET_OWNER_OF_NEXT_ENTRY( pxTCB, pxList )										\
+{																							\
+List_t * const pxConstList = ( pxList );													\
+	/* Increment the index to the next item and return the item, ensuring */				\
+	/* we don't return the marker used at the end of the list.  */							\
+	( pxConstList )->pxIndex = ( pxConstList )->pxIndex->pxNext;							\
+	if( ( void * ) ( pxConstList )->pxIndex == ( void * ) &( ( pxConstList )->xListEnd ) )	\
+	{																						\
+		( pxConstList )->pxIndex = ( pxConstList )->pxIndex->pxNext;						\
+	}																						\
+	( pxTCB ) = ( pxConstList )->pxIndex->pvOwner;											\
+}
+
+
+/*
+ * Access function to obtain the owner of the first entry in a list.  Lists
+ * are normally sorted in ascending item value order.
+ *
+ * This function returns the pxOwner member of the first item in the list.
+ * The pxOwner parameter of a list item is a pointer to the object that owns
+ * the list item.  In the scheduler this is normally a task control block.
+ * The pxOwner parameter effectively creates a two way link between the list
+ * item and its owner.
+ *
+ * @param pxList The list from which the owner of the head item is to be
+ * returned.
+ *
+ * \page listGET_OWNER_OF_HEAD_ENTRY listGET_OWNER_OF_HEAD_ENTRY
+ * \ingroup LinkedList
+ */
+#define listGET_OWNER_OF_HEAD_ENTRY( pxList )  ( (&( ( pxList )->xListEnd ))->pxNext->pvOwner )
+
+/*
+ * Check to see if a list item is within a list.  The list item maintains a
+ * "container" pointer that points to the list it is in.  All this macro does
+ * is check to see if the container and the list match.
+ *
+ * @param pxList The list we want to know if the list item is within.
+ * @param pxListItem The list item we want to know if is in the list.
+ * @return pdTRUE if the list item is in the list, otherwise pdFALSE.
+ */
+#define listIS_CONTAINED_WITHIN( pxList, pxListItem ) ( ( ( pxListItem )->pxContainer == ( pxList ) ) ? ( pdTRUE ) : ( pdFALSE ) )
+
+/*
+ * Return the list a list item is contained within (referenced from).
+ *
+ * @param pxListItem The list item being queried.
+ * @return A pointer to the List_t object that references the pxListItem
+ */
+#define listLIST_ITEM_CONTAINER( pxListItem ) ( ( pxListItem )->pxContainer )
+
+/*
+ * This provides a crude means of knowing if a list has been initialised, as
+ * pxList->xListEnd.xItemValue is set to portMAX_DELAY by the vListInitialise()
+ * function.
+ */
+#define listLIST_IS_INITIALISED( pxList ) ( ( pxList )->xListEnd.xItemValue == portMAX_DELAY )
+
+/*
+ * Must be called before a list is used!  This initialises all the members
+ * of the list structure and inserts the xListEnd item into the list as a
+ * marker to the back of the list.
+ *
+ * @param pxList Pointer to the list being initialised.
+ *
+ * \page vListInitialise vListInitialise
+ * \ingroup LinkedList
+ */
+void vListInitialise( List_t * const pxList ) PRIVILEGED_FUNCTION;
+
+/*
+ * Must be called before a list item is used.  This sets the list container to
+ * null so the item does not think that it is already contained in a list.
+ *
+ * @param pxItem Pointer to the list item being initialised.
+ *
+ * \page vListInitialiseItem vListInitialiseItem
+ * \ingroup LinkedList
+ */
+void vListInitialiseItem( ListItem_t * const pxItem ) PRIVILEGED_FUNCTION;
+
+/*
+ * Insert a list item into a list.  The item will be inserted into the list in
+ * a position determined by its item value (descending item value order).
+ *
+ * @param pxList The list into which the item is to be inserted.
+ *
+ * @param pxNewListItem The item that is to be placed in the list.
+ *
+ * \page vListInsert vListInsert
+ * \ingroup LinkedList
+ */
+void vListInsert( List_t * const pxList, ListItem_t * const pxNewListItem ) PRIVILEGED_FUNCTION;
+
+/*
+ * Insert a list item into a list.  The item will be inserted in a position
+ * such that it will be the last item within the list returned by multiple
+ * calls to listGET_OWNER_OF_NEXT_ENTRY.
+ *
+ * The list member pxIndex is used to walk through a list.  Calling
+ * listGET_OWNER_OF_NEXT_ENTRY increments pxIndex to the next item in the list.
+ * Placing an item in a list using vListInsertEnd effectively places the item
+ * in the list position pointed to by pxIndex.  This means that every other
+ * item within the list will be returned by listGET_OWNER_OF_NEXT_ENTRY before
+ * the pxIndex parameter again points to the item being inserted.
+ *
+ * @param pxList The list into which the item is to be inserted.
+ *
+ * @param pxNewListItem The list item to be inserted into the list.
+ *
+ * \page vListInsertEnd vListInsertEnd
+ * \ingroup LinkedList
+ */
+void vListInsertEnd( List_t * const pxList, ListItem_t * const pxNewListItem ) PRIVILEGED_FUNCTION;
+
+/*
+ * Remove an item from a list.  The list item has a pointer to the list that
+ * it is in, so only the list item need be passed into the function.
+ *
+ * @param uxListRemove The item to be removed.  The item will remove itself from
+ * the list pointed to by it's pxContainer parameter.
+ *
+ * @return The number of items that remain in the list after the list item has
+ * been removed.
+ *
+ * \page uxListRemove uxListRemove
+ * \ingroup LinkedList
+ */
+UBaseType_t uxListRemove( ListItem_t * const pxItemToRemove ) PRIVILEGED_FUNCTION;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/message_buffer.h b/Middlewares/Third_Party/FreeRTOS/Source/include/message_buffer.h
new file mode 100644
index 0000000..0c3edb9
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/include/message_buffer.h
@@ -0,0 +1,803 @@
+/*
+ * FreeRTOS Kernel V10.3.1
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+/*
+ * Message buffers build functionality on top of FreeRTOS stream buffers.
+ * Whereas stream buffers are used to send a continuous stream of data from one
+ * task or interrupt to another, message buffers are used to send variable
+ * length discrete messages from one task or interrupt to another.  Their
+ * implementation is light weight, making them particularly suited for interrupt
+ * to task and core to core communication scenarios.
+ *
+ * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
+ * implementation (so also the message buffer implementation, as message buffers
+ * are built on top of stream buffers) assumes there is only one task or
+ * interrupt that will write to the buffer (the writer), and only one task or
+ * interrupt that will read from the buffer (the reader).  It is safe for the
+ * writer and reader to be different tasks or interrupts, but, unlike other
+ * FreeRTOS objects, it is not safe to have multiple different writers or
+ * multiple different readers.  If there are to be multiple different writers
+ * then the application writer must place each call to a writing API function
+ * (such as xMessageBufferSend()) inside a critical section and set the send
+ * block time to 0.  Likewise, if there are to be multiple different readers
+ * then the application writer must place each call to a reading API function
+ * (such as xMessageBufferRead()) inside a critical section and set the receive
+ * timeout to 0.
+ *
+ * Message buffers hold variable length messages.  To enable that, when a
+ * message is written to the message buffer an additional sizeof( size_t ) bytes
+ * are also written to store the message's length (that happens internally, with
+ * the API function).  sizeof( size_t ) is typically 4 bytes on a 32-bit
+ * architecture, so writing a 10 byte message to a message buffer on a 32-bit
+ * architecture will actually reduce the available space in the message buffer
+ * by 14 bytes (10 byte are used by the message, and 4 bytes to hold the length
+ * of the message).
+ */
+
+#ifndef FREERTOS_MESSAGE_BUFFER_H
+#define FREERTOS_MESSAGE_BUFFER_H
+
+#ifndef INC_FREERTOS_H
+	#error "include FreeRTOS.h must appear in source files before include message_buffer.h"
+#endif
+
+/* Message buffers are built onto of stream buffers. */
+#include "stream_buffer.h"
+
+#if defined( __cplusplus )
+extern "C" {
+#endif
+
+/**
+ * Type by which message buffers are referenced.  For example, a call to
+ * xMessageBufferCreate() returns an MessageBufferHandle_t variable that can
+ * then be used as a parameter to xMessageBufferSend(), xMessageBufferReceive(),
+ * etc.
+ */
+typedef void * MessageBufferHandle_t;
+
+/*-----------------------------------------------------------*/
+
+/**
+ * message_buffer.h
+ *
+<pre>
+MessageBufferHandle_t xMessageBufferCreate( size_t xBufferSizeBytes );
+</pre>
+ *
+ * Creates a new message buffer using dynamically allocated memory.  See
+ * xMessageBufferCreateStatic() for a version that uses statically allocated
+ * memory (memory that is allocated at compile time).
+ *
+ * configSUPPORT_DYNAMIC_ALLOCATION must be set to 1 or left undefined in
+ * FreeRTOSConfig.h for xMessageBufferCreate() to be available.
+ *
+ * @param xBufferSizeBytes The total number of bytes (not messages) the message
+ * buffer will be able to hold at any one time.  When a message is written to
+ * the message buffer an additional sizeof( size_t ) bytes are also written to
+ * store the message's length.  sizeof( size_t ) is typically 4 bytes on a
+ * 32-bit architecture, so on most 32-bit architectures a 10 byte message will
+ * take up 14 bytes of message buffer space.
+ *
+ * @return If NULL is returned, then the message buffer cannot be created
+ * because there is insufficient heap memory available for FreeRTOS to allocate
+ * the message buffer data structures and storage area.  A non-NULL value being
+ * returned indicates that the message buffer has been created successfully -
+ * the returned value should be stored as the handle to the created message
+ * buffer.
+ *
+ * Example use:
+<pre>
+
+void vAFunction( void )
+{
+MessageBufferHandle_t xMessageBuffer;
+const size_t xMessageBufferSizeBytes = 100;
+
+    // Create a message buffer that can hold 100 bytes.  The memory used to hold
+    // both the message buffer structure and the messages themselves is allocated
+    // dynamically.  Each message added to the buffer consumes an additional 4
+    // bytes which are used to hold the lengh of the message.
+    xMessageBuffer = xMessageBufferCreate( xMessageBufferSizeBytes );
+
+    if( xMessageBuffer == NULL )
+    {
+        // There was not enough heap memory space available to create the
+        // message buffer.
+    }
+    else
+    {
+        // The message buffer was created successfully and can now be used.
+    }
+
+</pre>
+ * \defgroup xMessageBufferCreate xMessageBufferCreate
+ * \ingroup MessageBufferManagement
+ */
+#define xMessageBufferCreate( xBufferSizeBytes ) ( MessageBufferHandle_t ) xStreamBufferGenericCreate( xBufferSizeBytes, ( size_t ) 0, pdTRUE )
+
+/**
+ * message_buffer.h
+ *
+<pre>
+MessageBufferHandle_t xMessageBufferCreateStatic( size_t xBufferSizeBytes,
+                                                  uint8_t *pucMessageBufferStorageArea,
+                                                  StaticMessageBuffer_t *pxStaticMessageBuffer );
+</pre>
+ * Creates a new message buffer using statically allocated memory.  See
+ * xMessageBufferCreate() for a version that uses dynamically allocated memory.
+ *
+ * @param xBufferSizeBytes The size, in bytes, of the buffer pointed to by the
+ * pucMessageBufferStorageArea parameter.  When a message is written to the
+ * message buffer an additional sizeof( size_t ) bytes are also written to store
+ * the message's length.  sizeof( size_t ) is typically 4 bytes on a 32-bit
+ * architecture, so on most 32-bit architecture a 10 byte message will take up
+ * 14 bytes of message buffer space.  The maximum number of bytes that can be
+ * stored in the message buffer is actually (xBufferSizeBytes - 1).
+ *
+ * @param pucMessageBufferStorageArea Must point to a uint8_t array that is at
+ * least xBufferSizeBytes + 1 big.  This is the array to which messages are
+ * copied when they are written to the message buffer.
+ *
+ * @param pxStaticMessageBuffer Must point to a variable of type
+ * StaticMessageBuffer_t, which will be used to hold the message buffer's data
+ * structure.
+ *
+ * @return If the message buffer is created successfully then a handle to the
+ * created message buffer is returned. If either pucMessageBufferStorageArea or
+ * pxStaticmessageBuffer are NULL then NULL is returned.
+ *
+ * Example use:
+<pre>
+
+// Used to dimension the array used to hold the messages.  The available space
+// will actually be one less than this, so 999.
+#define STORAGE_SIZE_BYTES 1000
+
+// Defines the memory that will actually hold the messages within the message
+// buffer.
+static uint8_t ucStorageBuffer[ STORAGE_SIZE_BYTES ];
+
+// The variable used to hold the message buffer structure.
+StaticMessageBuffer_t xMessageBufferStruct;
+
+void MyFunction( void )
+{
+MessageBufferHandle_t xMessageBuffer;
+
+    xMessageBuffer = xMessageBufferCreateStatic( sizeof( ucBufferStorage ),
+                                                 ucBufferStorage,
+                                                 &xMessageBufferStruct );
+
+    // As neither the pucMessageBufferStorageArea or pxStaticMessageBuffer
+    // parameters were NULL, xMessageBuffer will not be NULL, and can be used to
+    // reference the created message buffer in other message buffer API calls.
+
+    // Other code that uses the message buffer can go here.
+}
+
+</pre>
+ * \defgroup xMessageBufferCreateStatic xMessageBufferCreateStatic
+ * \ingroup MessageBufferManagement
+ */
+#define xMessageBufferCreateStatic( xBufferSizeBytes, pucMessageBufferStorageArea, pxStaticMessageBuffer ) ( MessageBufferHandle_t ) xStreamBufferGenericCreateStatic( xBufferSizeBytes, 0, pdTRUE, pucMessageBufferStorageArea, pxStaticMessageBuffer )
+
+/**
+ * message_buffer.h
+ *
+<pre>
+size_t xMessageBufferSend( MessageBufferHandle_t xMessageBuffer,
+                           const void *pvTxData,
+                           size_t xDataLengthBytes,
+                           TickType_t xTicksToWait );
+<pre>
+ *
+ * Sends a discrete message to the message buffer.  The message can be any
+ * length that fits within the buffer's free space, and is copied into the
+ * buffer.
+ *
+ * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
+ * implementation (so also the message buffer implementation, as message buffers
+ * are built on top of stream buffers) assumes there is only one task or
+ * interrupt that will write to the buffer (the writer), and only one task or
+ * interrupt that will read from the buffer (the reader).  It is safe for the
+ * writer and reader to be different tasks or interrupts, but, unlike other
+ * FreeRTOS objects, it is not safe to have multiple different writers or
+ * multiple different readers.  If there are to be multiple different writers
+ * then the application writer must place each call to a writing API function
+ * (such as xMessageBufferSend()) inside a critical section and set the send
+ * block time to 0.  Likewise, if there are to be multiple different readers
+ * then the application writer must place each call to a reading API function
+ * (such as xMessageBufferRead()) inside a critical section and set the receive
+ * block time to 0.
+ *
+ * Use xMessageBufferSend() to write to a message buffer from a task.  Use
+ * xMessageBufferSendFromISR() to write to a message buffer from an interrupt
+ * service routine (ISR).
+ *
+ * @param xMessageBuffer The handle of the message buffer to which a message is
+ * being sent.
+ *
+ * @param pvTxData A pointer to the message that is to be copied into the
+ * message buffer.
+ *
+ * @param xDataLengthBytes The length of the message.  That is, the number of
+ * bytes to copy from pvTxData into the message buffer.  When a message is
+ * written to the message buffer an additional sizeof( size_t ) bytes are also
+ * written to store the message's length.  sizeof( size_t ) is typically 4 bytes
+ * on a 32-bit architecture, so on most 32-bit architecture setting
+ * xDataLengthBytes to 20 will reduce the free space in the message buffer by 24
+ * bytes (20 bytes of message data and 4 bytes to hold the message length).
+ *
+ * @param xTicksToWait The maximum amount of time the calling task should remain
+ * in the Blocked state to wait for enough space to become available in the
+ * message buffer, should the message buffer have insufficient space when
+ * xMessageBufferSend() is called.  The calling task will never block if
+ * xTicksToWait is zero.  The block time is specified in tick periods, so the
+ * absolute time it represents is dependent on the tick frequency.  The macro
+ * pdMS_TO_TICKS() can be used to convert a time specified in milliseconds into
+ * a time specified in ticks.  Setting xTicksToWait to portMAX_DELAY will cause
+ * the task to wait indefinitely (without timing out), provided
+ * INCLUDE_vTaskSuspend is set to 1 in FreeRTOSConfig.h.  Tasks do not use any
+ * CPU time when they are in the Blocked state.
+ *
+ * @return The number of bytes written to the message buffer.  If the call to
+ * xMessageBufferSend() times out before there was enough space to write the
+ * message into the message buffer then zero is returned.  If the call did not
+ * time out then xDataLengthBytes is returned.
+ *
+ * Example use:
+<pre>
+void vAFunction( MessageBufferHandle_t xMessageBuffer )
+{
+size_t xBytesSent;
+uint8_t ucArrayToSend[] = { 0, 1, 2, 3 };
+char *pcStringToSend = "String to send";
+const TickType_t x100ms = pdMS_TO_TICKS( 100 );
+
+    // Send an array to the message buffer, blocking for a maximum of 100ms to
+    // wait for enough space to be available in the message buffer.
+    xBytesSent = xMessageBufferSend( xMessageBuffer, ( void * ) ucArrayToSend, sizeof( ucArrayToSend ), x100ms );
+
+    if( xBytesSent != sizeof( ucArrayToSend ) )
+    {
+        // The call to xMessageBufferSend() times out before there was enough
+        // space in the buffer for the data to be written.
+    }
+
+    // Send the string to the message buffer.  Return immediately if there is
+    // not enough space in the buffer.
+    xBytesSent = xMessageBufferSend( xMessageBuffer, ( void * ) pcStringToSend, strlen( pcStringToSend ), 0 );
+
+    if( xBytesSent != strlen( pcStringToSend ) )
+    {
+        // The string could not be added to the message buffer because there was
+        // not enough free space in the buffer.
+    }
+}
+</pre>
+ * \defgroup xMessageBufferSend xMessageBufferSend
+ * \ingroup MessageBufferManagement
+ */
+#define xMessageBufferSend( xMessageBuffer, pvTxData, xDataLengthBytes, xTicksToWait ) xStreamBufferSend( ( StreamBufferHandle_t ) xMessageBuffer, pvTxData, xDataLengthBytes, xTicksToWait )
+
+/**
+ * message_buffer.h
+ *
+<pre>
+size_t xMessageBufferSendFromISR( MessageBufferHandle_t xMessageBuffer,
+                                  const void *pvTxData,
+                                  size_t xDataLengthBytes,
+                                  BaseType_t *pxHigherPriorityTaskWoken );
+<pre>
+ *
+ * Interrupt safe version of the API function that sends a discrete message to
+ * the message buffer.  The message can be any length that fits within the
+ * buffer's free space, and is copied into the buffer.
+ *
+ * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
+ * implementation (so also the message buffer implementation, as message buffers
+ * are built on top of stream buffers) assumes there is only one task or
+ * interrupt that will write to the buffer (the writer), and only one task or
+ * interrupt that will read from the buffer (the reader).  It is safe for the
+ * writer and reader to be different tasks or interrupts, but, unlike other
+ * FreeRTOS objects, it is not safe to have multiple different writers or
+ * multiple different readers.  If there are to be multiple different writers
+ * then the application writer must place each call to a writing API function
+ * (such as xMessageBufferSend()) inside a critical section and set the send
+ * block time to 0.  Likewise, if there are to be multiple different readers
+ * then the application writer must place each call to a reading API function
+ * (such as xMessageBufferRead()) inside a critical section and set the receive
+ * block time to 0.
+ *
+ * Use xMessageBufferSend() to write to a message buffer from a task.  Use
+ * xMessageBufferSendFromISR() to write to a message buffer from an interrupt
+ * service routine (ISR).
+ *
+ * @param xMessageBuffer The handle of the message buffer to which a message is
+ * being sent.
+ *
+ * @param pvTxData A pointer to the message that is to be copied into the
+ * message buffer.
+ *
+ * @param xDataLengthBytes The length of the message.  That is, the number of
+ * bytes to copy from pvTxData into the message buffer.  When a message is
+ * written to the message buffer an additional sizeof( size_t ) bytes are also
+ * written to store the message's length.  sizeof( size_t ) is typically 4 bytes
+ * on a 32-bit architecture, so on most 32-bit architecture setting
+ * xDataLengthBytes to 20 will reduce the free space in the message buffer by 24
+ * bytes (20 bytes of message data and 4 bytes to hold the message length).
+ *
+ * @param pxHigherPriorityTaskWoken  It is possible that a message buffer will
+ * have a task blocked on it waiting for data.  Calling
+ * xMessageBufferSendFromISR() can make data available, and so cause a task that
+ * was waiting for data to leave the Blocked state.  If calling
+ * xMessageBufferSendFromISR() causes a task to leave the Blocked state, and the
+ * unblocked task has a priority higher than the currently executing task (the
+ * task that was interrupted), then, internally, xMessageBufferSendFromISR()
+ * will set *pxHigherPriorityTaskWoken to pdTRUE.  If
+ * xMessageBufferSendFromISR() sets this value to pdTRUE, then normally a
+ * context switch should be performed before the interrupt is exited.  This will
+ * ensure that the interrupt returns directly to the highest priority Ready
+ * state task.  *pxHigherPriorityTaskWoken should be set to pdFALSE before it
+ * is passed into the function.  See the code example below for an example.
+ *
+ * @return The number of bytes actually written to the message buffer.  If the
+ * message buffer didn't have enough free space for the message to be stored
+ * then 0 is returned, otherwise xDataLengthBytes is returned.
+ *
+ * Example use:
+<pre>
+// A message buffer that has already been created.
+MessageBufferHandle_t xMessageBuffer;
+
+void vAnInterruptServiceRoutine( void )
+{
+size_t xBytesSent;
+char *pcStringToSend = "String to send";
+BaseType_t xHigherPriorityTaskWoken = pdFALSE; // Initialised to pdFALSE.
+
+    // Attempt to send the string to the message buffer.
+    xBytesSent = xMessageBufferSendFromISR( xMessageBuffer,
+                                            ( void * ) pcStringToSend,
+                                            strlen( pcStringToSend ),
+                                            &xHigherPriorityTaskWoken );
+
+    if( xBytesSent != strlen( pcStringToSend ) )
+    {
+        // The string could not be added to the message buffer because there was
+        // not enough free space in the buffer.
+    }
+
+    // If xHigherPriorityTaskWoken was set to pdTRUE inside
+    // xMessageBufferSendFromISR() then a task that has a priority above the
+    // priority of the currently executing task was unblocked and a context
+    // switch should be performed to ensure the ISR returns to the unblocked
+    // task.  In most FreeRTOS ports this is done by simply passing
+    // xHigherPriorityTaskWoken into portYIELD_FROM_ISR(), which will test the
+    // variables value, and perform the context switch if necessary.  Check the
+    // documentation for the port in use for port specific instructions.
+    portYIELD_FROM_ISR( xHigherPriorityTaskWoken );
+}
+</pre>
+ * \defgroup xMessageBufferSendFromISR xMessageBufferSendFromISR
+ * \ingroup MessageBufferManagement
+ */
+#define xMessageBufferSendFromISR( xMessageBuffer, pvTxData, xDataLengthBytes, pxHigherPriorityTaskWoken ) xStreamBufferSendFromISR( ( StreamBufferHandle_t ) xMessageBuffer, pvTxData, xDataLengthBytes, pxHigherPriorityTaskWoken )
+
+/**
+ * message_buffer.h
+ *
+<pre>
+size_t xMessageBufferReceive( MessageBufferHandle_t xMessageBuffer,
+                              void *pvRxData,
+                              size_t xBufferLengthBytes,
+                              TickType_t xTicksToWait );
+</pre>
+ *
+ * Receives a discrete message from a message buffer.  Messages can be of
+ * variable length and are copied out of the buffer.
+ *
+ * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
+ * implementation (so also the message buffer implementation, as message buffers
+ * are built on top of stream buffers) assumes there is only one task or
+ * interrupt that will write to the buffer (the writer), and only one task or
+ * interrupt that will read from the buffer (the reader).  It is safe for the
+ * writer and reader to be different tasks or interrupts, but, unlike other
+ * FreeRTOS objects, it is not safe to have multiple different writers or
+ * multiple different readers.  If there are to be multiple different writers
+ * then the application writer must place each call to a writing API function
+ * (such as xMessageBufferSend()) inside a critical section and set the send
+ * block time to 0.  Likewise, if there are to be multiple different readers
+ * then the application writer must place each call to a reading API function
+ * (such as xMessageBufferRead()) inside a critical section and set the receive
+ * block time to 0.
+ *
+ * Use xMessageBufferReceive() to read from a message buffer from a task.  Use
+ * xMessageBufferReceiveFromISR() to read from a message buffer from an
+ * interrupt service routine (ISR).
+ *
+ * @param xMessageBuffer The handle of the message buffer from which a message
+ * is being received.
+ *
+ * @param pvRxData A pointer to the buffer into which the received message is
+ * to be copied.
+ *
+ * @param xBufferLengthBytes The length of the buffer pointed to by the pvRxData
+ * parameter.  This sets the maximum length of the message that can be received.
+ * If xBufferLengthBytes is too small to hold the next message then the message
+ * will be left in the message buffer and 0 will be returned.
+ *
+ * @param xTicksToWait The maximum amount of time the task should remain in the
+ * Blocked state to wait for a message, should the message buffer be empty.
+ * xMessageBufferReceive() will return immediately if xTicksToWait is zero and
+ * the message buffer is empty.  The block time is specified in tick periods, so
+ * the absolute time it represents is dependent on the tick frequency.  The
+ * macro pdMS_TO_TICKS() can be used to convert a time specified in milliseconds
+ * into a time specified in ticks.  Setting xTicksToWait to portMAX_DELAY will
+ * cause the task to wait indefinitely (without timing out), provided
+ * INCLUDE_vTaskSuspend is set to 1 in FreeRTOSConfig.h.  Tasks do not use any
+ * CPU time when they are in the Blocked state.
+ *
+ * @return The length, in bytes, of the message read from the message buffer, if
+ * any.  If xMessageBufferReceive() times out before a message became available
+ * then zero is returned.  If the length of the message is greater than
+ * xBufferLengthBytes then the message will be left in the message buffer and
+ * zero is returned.
+ *
+ * Example use:
+<pre>
+void vAFunction( MessageBuffer_t xMessageBuffer )
+{
+uint8_t ucRxData[ 20 ];
+size_t xReceivedBytes;
+const TickType_t xBlockTime = pdMS_TO_TICKS( 20 );
+
+    // Receive the next message from the message buffer.  Wait in the Blocked
+    // state (so not using any CPU processing time) for a maximum of 100ms for
+    // a message to become available.
+    xReceivedBytes = xMessageBufferReceive( xMessageBuffer,
+                                            ( void * ) ucRxData,
+                                            sizeof( ucRxData ),
+                                            xBlockTime );
+
+    if( xReceivedBytes > 0 )
+    {
+        // A ucRxData contains a message that is xReceivedBytes long.  Process
+        // the message here....
+    }
+}
+</pre>
+ * \defgroup xMessageBufferReceive xMessageBufferReceive
+ * \ingroup MessageBufferManagement
+ */
+#define xMessageBufferReceive( xMessageBuffer, pvRxData, xBufferLengthBytes, xTicksToWait ) xStreamBufferReceive( ( StreamBufferHandle_t ) xMessageBuffer, pvRxData, xBufferLengthBytes, xTicksToWait )
+
+
+/**
+ * message_buffer.h
+ *
+<pre>
+size_t xMessageBufferReceiveFromISR( MessageBufferHandle_t xMessageBuffer,
+                                     void *pvRxData,
+                                     size_t xBufferLengthBytes,
+                                     BaseType_t *pxHigherPriorityTaskWoken );
+</pre>
+ *
+ * An interrupt safe version of the API function that receives a discrete
+ * message from a message buffer.  Messages can be of variable length and are
+ * copied out of the buffer.
+ *
+ * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
+ * implementation (so also the message buffer implementation, as message buffers
+ * are built on top of stream buffers) assumes there is only one task or
+ * interrupt that will write to the buffer (the writer), and only one task or
+ * interrupt that will read from the buffer (the reader).  It is safe for the
+ * writer and reader to be different tasks or interrupts, but, unlike other
+ * FreeRTOS objects, it is not safe to have multiple different writers or
+ * multiple different readers.  If there are to be multiple different writers
+ * then the application writer must place each call to a writing API function
+ * (such as xMessageBufferSend()) inside a critical section and set the send
+ * block time to 0.  Likewise, if there are to be multiple different readers
+ * then the application writer must place each call to a reading API function
+ * (such as xMessageBufferRead()) inside a critical section and set the receive
+ * block time to 0.
+ *
+ * Use xMessageBufferReceive() to read from a message buffer from a task.  Use
+ * xMessageBufferReceiveFromISR() to read from a message buffer from an
+ * interrupt service routine (ISR).
+ *
+ * @param xMessageBuffer The handle of the message buffer from which a message
+ * is being received.
+ *
+ * @param pvRxData A pointer to the buffer into which the received message is
+ * to be copied.
+ *
+ * @param xBufferLengthBytes The length of the buffer pointed to by the pvRxData
+ * parameter.  This sets the maximum length of the message that can be received.
+ * If xBufferLengthBytes is too small to hold the next message then the message
+ * will be left in the message buffer and 0 will be returned.
+ *
+ * @param pxHigherPriorityTaskWoken  It is possible that a message buffer will
+ * have a task blocked on it waiting for space to become available.  Calling
+ * xMessageBufferReceiveFromISR() can make space available, and so cause a task
+ * that is waiting for space to leave the Blocked state.  If calling
+ * xMessageBufferReceiveFromISR() causes a task to leave the Blocked state, and
+ * the unblocked task has a priority higher than the currently executing task
+ * (the task that was interrupted), then, internally,
+ * xMessageBufferReceiveFromISR() will set *pxHigherPriorityTaskWoken to pdTRUE.
+ * If xMessageBufferReceiveFromISR() sets this value to pdTRUE, then normally a
+ * context switch should be performed before the interrupt is exited.  That will
+ * ensure the interrupt returns directly to the highest priority Ready state
+ * task.  *pxHigherPriorityTaskWoken should be set to pdFALSE before it is
+ * passed into the function.  See the code example below for an example.
+ *
+ * @return The length, in bytes, of the message read from the message buffer, if
+ * any.
+ *
+ * Example use:
+<pre>
+// A message buffer that has already been created.
+MessageBuffer_t xMessageBuffer;
+
+void vAnInterruptServiceRoutine( void )
+{
+uint8_t ucRxData[ 20 ];
+size_t xReceivedBytes;
+BaseType_t xHigherPriorityTaskWoken = pdFALSE;  // Initialised to pdFALSE.
+
+    // Receive the next message from the message buffer.
+    xReceivedBytes = xMessageBufferReceiveFromISR( xMessageBuffer,
+                                                  ( void * ) ucRxData,
+                                                  sizeof( ucRxData ),
+                                                  &xHigherPriorityTaskWoken );
+
+    if( xReceivedBytes > 0 )
+    {
+        // A ucRxData contains a message that is xReceivedBytes long.  Process
+        // the message here....
+    }
+
+    // If xHigherPriorityTaskWoken was set to pdTRUE inside
+    // xMessageBufferReceiveFromISR() then a task that has a priority above the
+    // priority of the currently executing task was unblocked and a context
+    // switch should be performed to ensure the ISR returns to the unblocked
+    // task.  In most FreeRTOS ports this is done by simply passing
+    // xHigherPriorityTaskWoken into portYIELD_FROM_ISR(), which will test the
+    // variables value, and perform the context switch if necessary.  Check the
+    // documentation for the port in use for port specific instructions.
+    portYIELD_FROM_ISR( xHigherPriorityTaskWoken );
+}
+</pre>
+ * \defgroup xMessageBufferReceiveFromISR xMessageBufferReceiveFromISR
+ * \ingroup MessageBufferManagement
+ */
+#define xMessageBufferReceiveFromISR( xMessageBuffer, pvRxData, xBufferLengthBytes, pxHigherPriorityTaskWoken ) xStreamBufferReceiveFromISR( ( StreamBufferHandle_t ) xMessageBuffer, pvRxData, xBufferLengthBytes, pxHigherPriorityTaskWoken )
+
+/**
+ * message_buffer.h
+ *
+<pre>
+void vMessageBufferDelete( MessageBufferHandle_t xMessageBuffer );
+</pre>
+ *
+ * Deletes a message buffer that was previously created using a call to
+ * xMessageBufferCreate() or xMessageBufferCreateStatic().  If the message
+ * buffer was created using dynamic memory (that is, by xMessageBufferCreate()),
+ * then the allocated memory is freed.
+ *
+ * A message buffer handle must not be used after the message buffer has been
+ * deleted.
+ *
+ * @param xMessageBuffer The handle of the message buffer to be deleted.
+ *
+ */
+#define vMessageBufferDelete( xMessageBuffer ) vStreamBufferDelete( ( StreamBufferHandle_t ) xMessageBuffer )
+
+/**
+ * message_buffer.h
+<pre>
+BaseType_t xMessageBufferIsFull( MessageBufferHandle_t xMessageBuffer ) );
+</pre>
+ *
+ * Tests to see if a message buffer is full.  A message buffer is full if it
+ * cannot accept any more messages, of any size, until space is made available
+ * by a message being removed from the message buffer.
+ *
+ * @param xMessageBuffer The handle of the message buffer being queried.
+ *
+ * @return If the message buffer referenced by xMessageBuffer is full then
+ * pdTRUE is returned.  Otherwise pdFALSE is returned.
+ */
+#define xMessageBufferIsFull( xMessageBuffer ) xStreamBufferIsFull( ( StreamBufferHandle_t ) xMessageBuffer )
+
+/**
+ * message_buffer.h
+<pre>
+BaseType_t xMessageBufferIsEmpty( MessageBufferHandle_t xMessageBuffer ) );
+</pre>
+ *
+ * Tests to see if a message buffer is empty (does not contain any messages).
+ *
+ * @param xMessageBuffer The handle of the message buffer being queried.
+ *
+ * @return If the message buffer referenced by xMessageBuffer is empty then
+ * pdTRUE is returned.  Otherwise pdFALSE is returned.
+ *
+ */
+#define xMessageBufferIsEmpty( xMessageBuffer ) xStreamBufferIsEmpty( ( StreamBufferHandle_t ) xMessageBuffer )
+
+/**
+ * message_buffer.h
+<pre>
+BaseType_t xMessageBufferReset( MessageBufferHandle_t xMessageBuffer );
+</pre>
+ *
+ * Resets a message buffer to its initial empty state, discarding any message it
+ * contained.
+ *
+ * A message buffer can only be reset if there are no tasks blocked on it.
+ *
+ * @param xMessageBuffer The handle of the message buffer being reset.
+ *
+ * @return If the message buffer was reset then pdPASS is returned.  If the
+ * message buffer could not be reset because either there was a task blocked on
+ * the message queue to wait for space to become available, or to wait for a
+ * a message to be available, then pdFAIL is returned.
+ *
+ * \defgroup xMessageBufferReset xMessageBufferReset
+ * \ingroup MessageBufferManagement
+ */
+#define xMessageBufferReset( xMessageBuffer ) xStreamBufferReset( ( StreamBufferHandle_t ) xMessageBuffer )
+
+
+/**
+ * message_buffer.h
+<pre>
+size_t xMessageBufferSpaceAvailable( MessageBufferHandle_t xMessageBuffer ) );
+</pre>
+ * Returns the number of bytes of free space in the message buffer.
+ *
+ * @param xMessageBuffer The handle of the message buffer being queried.
+ *
+ * @return The number of bytes that can be written to the message buffer before
+ * the message buffer would be full.  When a message is written to the message
+ * buffer an additional sizeof( size_t ) bytes are also written to store the
+ * message's length.  sizeof( size_t ) is typically 4 bytes on a 32-bit
+ * architecture, so if xMessageBufferSpacesAvailable() returns 10, then the size
+ * of the largest message that can be written to the message buffer is 6 bytes.
+ *
+ * \defgroup xMessageBufferSpaceAvailable xMessageBufferSpaceAvailable
+ * \ingroup MessageBufferManagement
+ */
+#define xMessageBufferSpaceAvailable( xMessageBuffer ) xStreamBufferSpacesAvailable( ( StreamBufferHandle_t ) xMessageBuffer )
+#define xMessageBufferSpacesAvailable( xMessageBuffer ) xStreamBufferSpacesAvailable( ( StreamBufferHandle_t ) xMessageBuffer ) /* Corrects typo in original macro name. */
+
+/**
+ * message_buffer.h
+ <pre>
+ size_t xMessageBufferNextLengthBytes( MessageBufferHandle_t xMessageBuffer ) );
+ </pre>
+ * Returns the length (in bytes) of the next message in a message buffer.
+ * Useful if xMessageBufferReceive() returned 0 because the size of the buffer
+ * passed into xMessageBufferReceive() was too small to hold the next message.
+ *
+ * @param xMessageBuffer The handle of the message buffer being queried.
+ *
+ * @return The length (in bytes) of the next message in the message buffer, or 0
+ * if the message buffer is empty.
+ *
+ * \defgroup xMessageBufferNextLengthBytes xMessageBufferNextLengthBytes
+ * \ingroup MessageBufferManagement
+ */
+#define xMessageBufferNextLengthBytes( xMessageBuffer ) xStreamBufferNextMessageLengthBytes( ( StreamBufferHandle_t ) xMessageBuffer ) PRIVILEGED_FUNCTION;
+
+/**
+ * message_buffer.h
+ *
+<pre>
+BaseType_t xMessageBufferSendCompletedFromISR( MessageBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken );
+</pre>
+ *
+ * For advanced users only.
+ *
+ * The sbSEND_COMPLETED() macro is called from within the FreeRTOS APIs when
+ * data is sent to a message buffer or stream buffer.  If there was a task that
+ * was blocked on the message or stream buffer waiting for data to arrive then
+ * the sbSEND_COMPLETED() macro sends a notification to the task to remove it
+ * from the Blocked state.  xMessageBufferSendCompletedFromISR() does the same
+ * thing.  It is provided to enable application writers to implement their own
+ * version of sbSEND_COMPLETED(), and MUST NOT BE USED AT ANY OTHER TIME.
+ *
+ * See the example implemented in FreeRTOS/Demo/Minimal/MessageBufferAMP.c for
+ * additional information.
+ *
+ * @param xStreamBuffer The handle of the stream buffer to which data was
+ * written.
+ *
+ * @param pxHigherPriorityTaskWoken *pxHigherPriorityTaskWoken should be
+ * initialised to pdFALSE before it is passed into
+ * xMessageBufferSendCompletedFromISR().  If calling
+ * xMessageBufferSendCompletedFromISR() removes a task from the Blocked state,
+ * and the task has a priority above the priority of the currently running task,
+ * then *pxHigherPriorityTaskWoken will get set to pdTRUE indicating that a
+ * context switch should be performed before exiting the ISR.
+ *
+ * @return If a task was removed from the Blocked state then pdTRUE is returned.
+ * Otherwise pdFALSE is returned.
+ *
+ * \defgroup xMessageBufferSendCompletedFromISR xMessageBufferSendCompletedFromISR
+ * \ingroup StreamBufferManagement
+ */
+#define xMessageBufferSendCompletedFromISR( xMessageBuffer, pxHigherPriorityTaskWoken ) xStreamBufferSendCompletedFromISR( ( StreamBufferHandle_t ) xMessageBuffer, pxHigherPriorityTaskWoken )
+
+/**
+ * message_buffer.h
+ *
+<pre>
+BaseType_t xMessageBufferReceiveCompletedFromISR( MessageBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken );
+</pre>
+ *
+ * For advanced users only.
+ *
+ * The sbRECEIVE_COMPLETED() macro is called from within the FreeRTOS APIs when
+ * data is read out of a message buffer or stream buffer.  If there was a task
+ * that was blocked on the message or stream buffer waiting for data to arrive
+ * then the sbRECEIVE_COMPLETED() macro sends a notification to the task to
+ * remove it from the Blocked state.  xMessageBufferReceiveCompletedFromISR()
+ * does the same thing.  It is provided to enable application writers to
+ * implement their own version of sbRECEIVE_COMPLETED(), and MUST NOT BE USED AT
+ * ANY OTHER TIME.
+ *
+ * See the example implemented in FreeRTOS/Demo/Minimal/MessageBufferAMP.c for
+ * additional information.
+ *
+ * @param xStreamBuffer The handle of the stream buffer from which data was
+ * read.
+ *
+ * @param pxHigherPriorityTaskWoken *pxHigherPriorityTaskWoken should be
+ * initialised to pdFALSE before it is passed into
+ * xMessageBufferReceiveCompletedFromISR().  If calling
+ * xMessageBufferReceiveCompletedFromISR() removes a task from the Blocked state,
+ * and the task has a priority above the priority of the currently running task,
+ * then *pxHigherPriorityTaskWoken will get set to pdTRUE indicating that a
+ * context switch should be performed before exiting the ISR.
+ *
+ * @return If a task was removed from the Blocked state then pdTRUE is returned.
+ * Otherwise pdFALSE is returned.
+ *
+ * \defgroup xMessageBufferReceiveCompletedFromISR xMessageBufferReceiveCompletedFromISR
+ * \ingroup StreamBufferManagement
+ */
+#define xMessageBufferReceiveCompletedFromISR( xMessageBuffer, pxHigherPriorityTaskWoken ) xStreamBufferReceiveCompletedFromISR( ( StreamBufferHandle_t ) xMessageBuffer, pxHigherPriorityTaskWoken )
+
+#if defined( __cplusplus )
+} /* extern "C" */
+#endif
+
+#endif	/* !defined( FREERTOS_MESSAGE_BUFFER_H ) */
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/mpu_prototypes.h b/Middlewares/Third_Party/FreeRTOS/Source/include/mpu_prototypes.h
new file mode 100644
index 0000000..a21b7a6
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/include/mpu_prototypes.h
@@ -0,0 +1,160 @@
+/*
+ * FreeRTOS Kernel V10.3.1
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*
+ * When the MPU is used the standard (non MPU) API functions are mapped to
+ * equivalents that start "MPU_", the prototypes for which are defined in this
+ * header files.  This will cause the application code to call the MPU_ version
+ * which wraps the non-MPU version with privilege promoting then demoting code,
+ * so the kernel code always runs will full privileges.
+ */
+
+
+#ifndef MPU_PROTOTYPES_H
+#define MPU_PROTOTYPES_H
+
+/* MPU versions of tasks.h API functions. */
+BaseType_t MPU_xTaskCreate( TaskFunction_t pxTaskCode, const char * const pcName, const uint16_t usStackDepth, void * const pvParameters, UBaseType_t uxPriority, TaskHandle_t * const pxCreatedTask ) FREERTOS_SYSTEM_CALL;
+TaskHandle_t MPU_xTaskCreateStatic( TaskFunction_t pxTaskCode, const char * const pcName, const uint32_t ulStackDepth, void * const pvParameters, UBaseType_t uxPriority, StackType_t * const puxStackBuffer, StaticTask_t * const pxTaskBuffer ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskCreateRestricted( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskCreateRestrictedStatic( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskAllocateMPURegions( TaskHandle_t xTask, const MemoryRegion_t * const pxRegions ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskDelete( TaskHandle_t xTaskToDelete ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskDelay( const TickType_t xTicksToDelay ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskDelayUntil( TickType_t * const pxPreviousWakeTime, const TickType_t xTimeIncrement ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
+UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
+eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskGetInfo( TaskHandle_t xTask, TaskStatus_t *pxTaskStatus, BaseType_t xGetFreeStackSpace, eTaskState eState ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskPrioritySet( TaskHandle_t xTask, UBaseType_t uxNewPriority ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskResume( TaskHandle_t xTaskToResume ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskStartScheduler( void ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskSuspendAll( void ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskResumeAll( void ) FREERTOS_SYSTEM_CALL;
+TickType_t MPU_xTaskGetTickCount( void ) FREERTOS_SYSTEM_CALL;
+UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) FREERTOS_SYSTEM_CALL;
+char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) FREERTOS_SYSTEM_CALL;
+TaskHandle_t MPU_xTaskGetHandle( const char *pcNameToQuery ) FREERTOS_SYSTEM_CALL;
+UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
+configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask, TaskHookFunction_t pxHookFunction ) FREERTOS_SYSTEM_CALL;
+TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, BaseType_t xIndex, void *pvValue ) FREERTOS_SYSTEM_CALL;
+void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, BaseType_t xIndex ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskCallApplicationTaskHook( TaskHandle_t xTask, void *pvParameter ) FREERTOS_SYSTEM_CALL;
+TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) FREERTOS_SYSTEM_CALL;
+UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, const UBaseType_t uxArraySize, uint32_t * const pulTotalRunTime ) FREERTOS_SYSTEM_CALL;
+uint32_t MPU_ulTaskGetIdleRunTimeCounter( void ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskList( char * pcWriteBuffer ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskGetRunTimeStats( char *pcWriteBuffer ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskNotifyWait( uint32_t ulBitsToClearOnEntry, uint32_t ulBitsToClearOnExit, uint32_t *pulNotificationValue, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+uint32_t MPU_ulTaskNotifyTake( BaseType_t xClearCountOnExit, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskNotifyStateClear( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
+uint32_t MPU_ulTaskNotifyValueClear( TaskHandle_t xTask, uint32_t ulBitsToClear ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskIncrementTick( void ) FREERTOS_SYSTEM_CALL;
+TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskMissedYield( void ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskGetSchedulerState( void ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskCatchUpTicks( TickType_t xTicksToCatchUp ) FREERTOS_SYSTEM_CALL;
+
+/* MPU versions of queue.h API functions. */
+BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, const BaseType_t xCopyPosition ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
+UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
+void MPU_vQueueDelete( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
+QueueHandle_t MPU_xQueueCreateMutex( const uint8_t ucQueueType ) FREERTOS_SYSTEM_CALL;
+QueueHandle_t MPU_xQueueCreateMutexStatic( const uint8_t ucQueueType, StaticQueue_t *pxStaticQueue ) FREERTOS_SYSTEM_CALL;
+QueueHandle_t MPU_xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount ) FREERTOS_SYSTEM_CALL;
+QueueHandle_t MPU_xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount, StaticQueue_t *pxStaticQueue ) FREERTOS_SYSTEM_CALL;
+TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) FREERTOS_SYSTEM_CALL;
+void MPU_vQueueAddToRegistry( QueueHandle_t xQueue, const char *pcName ) FREERTOS_SYSTEM_CALL;
+void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
+const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
+QueueHandle_t MPU_xQueueGenericCreate( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, const uint8_t ucQueueType ) FREERTOS_SYSTEM_CALL;
+QueueHandle_t MPU_xQueueGenericCreateStatic( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, StaticQueue_t *pxStaticQueue, const uint8_t ucQueueType ) FREERTOS_SYSTEM_CALL;
+QueueSetHandle_t MPU_xQueueCreateSet( const UBaseType_t uxEventQueueLength ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet ) FREERTOS_SYSTEM_CALL;
+QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet, const TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xQueueGenericReset( QueueHandle_t xQueue, BaseType_t xNewQueue ) FREERTOS_SYSTEM_CALL;
+void MPU_vQueueSetQueueNumber( QueueHandle_t xQueue, UBaseType_t uxQueueNumber ) FREERTOS_SYSTEM_CALL;
+UBaseType_t MPU_uxQueueGetQueueNumber( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
+uint8_t MPU_ucQueueGetQueueType( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
+
+/* MPU versions of timers.h API functions. */
+TimerHandle_t MPU_xTimerCreate( const char * const pcTimerName, const TickType_t xTimerPeriodInTicks, const UBaseType_t uxAutoReload, void * const pvTimerID, TimerCallbackFunction_t pxCallbackFunction ) FREERTOS_SYSTEM_CALL;
+TimerHandle_t MPU_xTimerCreateStatic( const char * const pcTimerName, const TickType_t xTimerPeriodInTicks, const UBaseType_t uxAutoReload, void * const pvTimerID, TimerCallbackFunction_t pxCallbackFunction, StaticTimer_t *pxTimerBuffer ) FREERTOS_SYSTEM_CALL;
+void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
+void MPU_vTimerSetTimerID( TimerHandle_t xTimer, void *pvNewID ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
+TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTimerPendFunctionCall( PendedFunction_t xFunctionToPend, void *pvParameter1, uint32_t ulParameter2, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
+void MPU_vTimerSetReloadMode( TimerHandle_t xTimer, const UBaseType_t uxAutoReload ) FREERTOS_SYSTEM_CALL;
+UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
+TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
+TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTimerCreateTimerTask( void ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTimerGenericCommand( TimerHandle_t xTimer, const BaseType_t xCommandID, const TickType_t xOptionalValue, BaseType_t * const pxHigherPriorityTaskWoken, const TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+
+/* MPU versions of event_group.h API functions. */
+EventGroupHandle_t MPU_xEventGroupCreate( void ) FREERTOS_SYSTEM_CALL;
+EventGroupHandle_t MPU_xEventGroupCreateStatic( StaticEventGroup_t *pxEventGroupBuffer ) FREERTOS_SYSTEM_CALL;
+EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToWaitFor, const BaseType_t xClearOnExit, const BaseType_t xWaitForAllBits, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear ) FREERTOS_SYSTEM_CALL;
+EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet ) FREERTOS_SYSTEM_CALL;
+EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, const EventBits_t uxBitsToWaitFor, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+void MPU_vEventGroupDelete( EventGroupHandle_t xEventGroup ) FREERTOS_SYSTEM_CALL;
+UBaseType_t MPU_uxEventGroupGetNumber( void* xEventGroup ) FREERTOS_SYSTEM_CALL;
+
+/* MPU versions of message/stream_buffer.h API functions. */
+size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer, const void *pvTxData, size_t xDataLengthBytes, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer, void *pvRxData, size_t xBufferLengthBytes, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
+void MPU_vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xStreamBufferReset( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
+size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
+size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, size_t xTriggerLevel ) FREERTOS_SYSTEM_CALL;
+StreamBufferHandle_t MPU_xStreamBufferGenericCreate( size_t xBufferSizeBytes, size_t xTriggerLevelBytes, BaseType_t xIsMessageBuffer ) FREERTOS_SYSTEM_CALL;
+StreamBufferHandle_t MPU_xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes, size_t xTriggerLevelBytes, BaseType_t xIsMessageBuffer, uint8_t * const pucStreamBufferStorageArea, StaticStreamBuffer_t * const pxStaticStreamBuffer ) FREERTOS_SYSTEM_CALL;
+
+
+
+#endif /* MPU_PROTOTYPES_H */
+
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h b/Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h
new file mode 100644
index 0000000..5f63d4f
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h
@@ -0,0 +1,189 @@
+/*
+ * FreeRTOS Kernel V10.3.1
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef MPU_WRAPPERS_H
+#define MPU_WRAPPERS_H
+
+/* This file redefines API functions to be called through a wrapper macro, but
+only for ports that are using the MPU. */
+#ifdef portUSING_MPU_WRAPPERS
+
+	/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE will be defined when this file is
+	included from queue.c or task.c to prevent it from having an effect within
+	those files. */
+	#ifndef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+		/*
+		 * Map standard (non MPU) API functions to equivalents that start
+		 * "MPU_".  This will cause the application code to call the MPU_
+		 * version, which wraps the non-MPU version with privilege promoting
+		 * then demoting code, so the kernel code always runs will full
+		 * privileges.
+		 */
+
+		/* Map standard tasks.h API functions to the MPU equivalents. */
+		#define xTaskCreate								MPU_xTaskCreate
+		#define xTaskCreateStatic						MPU_xTaskCreateStatic
+		#define xTaskCreateRestricted					MPU_xTaskCreateRestricted
+		#define vTaskAllocateMPURegions					MPU_vTaskAllocateMPURegions
+		#define vTaskDelete								MPU_vTaskDelete
+		#define vTaskDelay								MPU_vTaskDelay
+		#define vTaskDelayUntil							MPU_vTaskDelayUntil
+		#define xTaskAbortDelay							MPU_xTaskAbortDelay
+		#define uxTaskPriorityGet						MPU_uxTaskPriorityGet
+		#define eTaskGetState							MPU_eTaskGetState
+		#define vTaskGetInfo							MPU_vTaskGetInfo
+		#define vTaskPrioritySet						MPU_vTaskPrioritySet
+		#define vTaskSuspend							MPU_vTaskSuspend
+		#define vTaskResume								MPU_vTaskResume
+		#define vTaskSuspendAll							MPU_vTaskSuspendAll
+		#define xTaskResumeAll							MPU_xTaskResumeAll
+		#define xTaskGetTickCount						MPU_xTaskGetTickCount
+		#define uxTaskGetNumberOfTasks					MPU_uxTaskGetNumberOfTasks
+		#define pcTaskGetName							MPU_pcTaskGetName
+		#define xTaskGetHandle							MPU_xTaskGetHandle
+		#define uxTaskGetStackHighWaterMark				MPU_uxTaskGetStackHighWaterMark
+		#define uxTaskGetStackHighWaterMark2			MPU_uxTaskGetStackHighWaterMark2
+		#define vTaskSetApplicationTaskTag				MPU_vTaskSetApplicationTaskTag
+		#define xTaskGetApplicationTaskTag				MPU_xTaskGetApplicationTaskTag
+		#define vTaskSetThreadLocalStoragePointer		MPU_vTaskSetThreadLocalStoragePointer
+		#define pvTaskGetThreadLocalStoragePointer		MPU_pvTaskGetThreadLocalStoragePointer
+		#define xTaskCallApplicationTaskHook			MPU_xTaskCallApplicationTaskHook
+		#define xTaskGetIdleTaskHandle					MPU_xTaskGetIdleTaskHandle
+		#define uxTaskGetSystemState					MPU_uxTaskGetSystemState
+		#define vTaskList								MPU_vTaskList
+		#define vTaskGetRunTimeStats					MPU_vTaskGetRunTimeStats
+		#define ulTaskGetIdleRunTimeCounter				MPU_ulTaskGetIdleRunTimeCounter
+		#define xTaskGenericNotify						MPU_xTaskGenericNotify
+		#define xTaskNotifyWait							MPU_xTaskNotifyWait
+		#define ulTaskNotifyTake						MPU_ulTaskNotifyTake
+		#define xTaskNotifyStateClear					MPU_xTaskNotifyStateClear
+		#define ulTaskNotifyValueClear					MPU_ulTaskNotifyValueClear
+		#define xTaskCatchUpTicks						MPU_xTaskCatchUpTicks
+
+		#define xTaskGetCurrentTaskHandle				MPU_xTaskGetCurrentTaskHandle
+		#define vTaskSetTimeOutState					MPU_vTaskSetTimeOutState
+		#define xTaskCheckForTimeOut					MPU_xTaskCheckForTimeOut
+		#define xTaskGetSchedulerState					MPU_xTaskGetSchedulerState
+
+		/* Map standard queue.h API functions to the MPU equivalents. */
+		#define xQueueGenericSend						MPU_xQueueGenericSend
+		#define xQueueReceive							MPU_xQueueReceive
+		#define xQueuePeek								MPU_xQueuePeek
+		#define xQueueSemaphoreTake						MPU_xQueueSemaphoreTake
+		#define uxQueueMessagesWaiting					MPU_uxQueueMessagesWaiting
+		#define uxQueueSpacesAvailable					MPU_uxQueueSpacesAvailable
+		#define vQueueDelete							MPU_vQueueDelete
+		#define xQueueCreateMutex						MPU_xQueueCreateMutex
+		#define xQueueCreateMutexStatic					MPU_xQueueCreateMutexStatic
+		#define xQueueCreateCountingSemaphore			MPU_xQueueCreateCountingSemaphore
+		#define xQueueCreateCountingSemaphoreStatic		MPU_xQueueCreateCountingSemaphoreStatic
+		#define xQueueGetMutexHolder					MPU_xQueueGetMutexHolder
+		#define xQueueTakeMutexRecursive				MPU_xQueueTakeMutexRecursive
+		#define xQueueGiveMutexRecursive				MPU_xQueueGiveMutexRecursive
+		#define xQueueGenericCreate						MPU_xQueueGenericCreate
+		#define xQueueGenericCreateStatic				MPU_xQueueGenericCreateStatic
+		#define xQueueCreateSet							MPU_xQueueCreateSet
+		#define xQueueAddToSet							MPU_xQueueAddToSet
+		#define xQueueRemoveFromSet						MPU_xQueueRemoveFromSet
+		#define xQueueSelectFromSet						MPU_xQueueSelectFromSet
+		#define xQueueGenericReset						MPU_xQueueGenericReset
+
+		#if( configQUEUE_REGISTRY_SIZE > 0 )
+			#define vQueueAddToRegistry						MPU_vQueueAddToRegistry
+			#define vQueueUnregisterQueue					MPU_vQueueUnregisterQueue
+			#define pcQueueGetName							MPU_pcQueueGetName
+		#endif
+
+		/* Map standard timer.h API functions to the MPU equivalents. */
+		#define xTimerCreate							MPU_xTimerCreate
+		#define xTimerCreateStatic						MPU_xTimerCreateStatic
+		#define pvTimerGetTimerID						MPU_pvTimerGetTimerID
+		#define vTimerSetTimerID						MPU_vTimerSetTimerID
+		#define xTimerIsTimerActive						MPU_xTimerIsTimerActive
+		#define xTimerGetTimerDaemonTaskHandle			MPU_xTimerGetTimerDaemonTaskHandle
+		#define xTimerPendFunctionCall					MPU_xTimerPendFunctionCall
+		#define pcTimerGetName							MPU_pcTimerGetName
+		#define vTimerSetReloadMode						MPU_vTimerSetReloadMode
+		#define uxTimerGetReloadMode					MPU_uxTimerGetReloadMode
+		#define xTimerGetPeriod							MPU_xTimerGetPeriod
+		#define xTimerGetExpiryTime						MPU_xTimerGetExpiryTime
+		#define xTimerGenericCommand					MPU_xTimerGenericCommand
+
+		/* Map standard event_group.h API functions to the MPU equivalents. */
+		#define xEventGroupCreate						MPU_xEventGroupCreate
+		#define xEventGroupCreateStatic					MPU_xEventGroupCreateStatic
+		#define xEventGroupWaitBits						MPU_xEventGroupWaitBits
+		#define xEventGroupClearBits					MPU_xEventGroupClearBits
+		#define xEventGroupSetBits						MPU_xEventGroupSetBits
+		#define xEventGroupSync							MPU_xEventGroupSync
+		#define vEventGroupDelete						MPU_vEventGroupDelete
+
+		/* Map standard message/stream_buffer.h API functions to the MPU
+		equivalents. */
+		#define xStreamBufferSend						MPU_xStreamBufferSend
+		#define xStreamBufferReceive					MPU_xStreamBufferReceive
+		#define xStreamBufferNextMessageLengthBytes		MPU_xStreamBufferNextMessageLengthBytes
+		#define vStreamBufferDelete						MPU_vStreamBufferDelete
+		#define xStreamBufferIsFull						MPU_xStreamBufferIsFull
+		#define xStreamBufferIsEmpty					MPU_xStreamBufferIsEmpty
+		#define xStreamBufferReset						MPU_xStreamBufferReset
+		#define xStreamBufferSpacesAvailable			MPU_xStreamBufferSpacesAvailable
+		#define xStreamBufferBytesAvailable				MPU_xStreamBufferBytesAvailable
+		#define xStreamBufferSetTriggerLevel			MPU_xStreamBufferSetTriggerLevel
+		#define xStreamBufferGenericCreate				MPU_xStreamBufferGenericCreate
+		#define xStreamBufferGenericCreateStatic		MPU_xStreamBufferGenericCreateStatic
+
+
+		/* Remove the privileged function macro, but keep the PRIVILEGED_DATA
+		macro so applications can place data in privileged access sections
+		(useful when using statically allocated objects). */
+		#define PRIVILEGED_FUNCTION
+		#define PRIVILEGED_DATA __attribute__((section("privileged_data")))
+		#define FREERTOS_SYSTEM_CALL
+
+	#else /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE */
+
+		/* Ensure API functions go in the privileged execution section. */
+		#define PRIVILEGED_FUNCTION __attribute__((section("privileged_functions")))
+		#define PRIVILEGED_DATA __attribute__((section("privileged_data")))
+		#define FREERTOS_SYSTEM_CALL __attribute__((section( "freertos_system_calls")))
+
+	#endif /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE */
+
+#else /* portUSING_MPU_WRAPPERS */
+
+	#define PRIVILEGED_FUNCTION
+	#define PRIVILEGED_DATA
+	#define FREERTOS_SYSTEM_CALL
+	#define portUSING_MPU_WRAPPERS 0
+
+#endif /* portUSING_MPU_WRAPPERS */
+
+
+#endif /* MPU_WRAPPERS_H */
+
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/portable.h b/Middlewares/Third_Party/FreeRTOS/Source/include/portable.h
new file mode 100644
index 0000000..a2099c3
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/include/portable.h
@@ -0,0 +1,199 @@
+/*
+ * FreeRTOS Kernel V10.3.1
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*-----------------------------------------------------------
+ * Portable layer API.  Each function must be defined for each port.
+ *----------------------------------------------------------*/
+
+#ifndef PORTABLE_H
+#define PORTABLE_H
+
+/* Each FreeRTOS port has a unique portmacro.h header file.  Originally a
+pre-processor definition was used to ensure the pre-processor found the correct
+portmacro.h file for the port being used.  That scheme was deprecated in favour
+of setting the compiler's include path such that it found the correct
+portmacro.h file - removing the need for the constant and allowing the
+portmacro.h file to be located anywhere in relation to the port being used.
+Purely for reasons of backward compatibility the old method is still valid, but
+to make it clear that new projects should not use it, support for the port
+specific constants has been moved into the deprecated_definitions.h header
+file. */
+#include "deprecated_definitions.h"
+
+/* If portENTER_CRITICAL is not defined then including deprecated_definitions.h
+did not result in a portmacro.h header file being included - and it should be
+included here.  In this case the path to the correct portmacro.h header file
+must be set in the compiler's include path. */
+#ifndef portENTER_CRITICAL
+	#include "portmacro.h"
+#endif
+
+#if portBYTE_ALIGNMENT == 32
+	#define portBYTE_ALIGNMENT_MASK ( 0x001f )
+#endif
+
+#if portBYTE_ALIGNMENT == 16
+	#define portBYTE_ALIGNMENT_MASK ( 0x000f )
+#endif
+
+#if portBYTE_ALIGNMENT == 8
+	#define portBYTE_ALIGNMENT_MASK ( 0x0007 )
+#endif
+
+#if portBYTE_ALIGNMENT == 4
+	#define portBYTE_ALIGNMENT_MASK	( 0x0003 )
+#endif
+
+#if portBYTE_ALIGNMENT == 2
+	#define portBYTE_ALIGNMENT_MASK	( 0x0001 )
+#endif
+
+#if portBYTE_ALIGNMENT == 1
+	#define portBYTE_ALIGNMENT_MASK	( 0x0000 )
+#endif
+
+#ifndef portBYTE_ALIGNMENT_MASK
+	#error "Invalid portBYTE_ALIGNMENT definition"
+#endif
+
+#ifndef portNUM_CONFIGURABLE_REGIONS
+	#define portNUM_CONFIGURABLE_REGIONS 1
+#endif
+
+#ifndef portHAS_STACK_OVERFLOW_CHECKING
+	#define portHAS_STACK_OVERFLOW_CHECKING 0
+#endif
+
+#ifndef portARCH_NAME
+	#define portARCH_NAME NULL
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "mpu_wrappers.h"
+
+/*
+ * Setup the stack of a new task so it is ready to be placed under the
+ * scheduler control.  The registers have to be placed on the stack in
+ * the order that the port expects to find them.
+ *
+ */
+#if( portUSING_MPU_WRAPPERS == 1 )
+	#if( portHAS_STACK_OVERFLOW_CHECKING == 1 )
+		StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged ) PRIVILEGED_FUNCTION;
+	#else
+		StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged ) PRIVILEGED_FUNCTION;
+	#endif
+#else
+	#if( portHAS_STACK_OVERFLOW_CHECKING == 1 )
+		StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters ) PRIVILEGED_FUNCTION;
+	#else
+		StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) PRIVILEGED_FUNCTION;
+	#endif
+#endif
+
+/* Used by heap_5.c to define the start address and size of each memory region
+that together comprise the total FreeRTOS heap space. */
+typedef struct HeapRegion
+{
+	uint8_t *pucStartAddress;
+	size_t xSizeInBytes;
+} HeapRegion_t;
+
+/* Used to pass information about the heap out of vPortGetHeapStats(). */
+typedef struct xHeapStats
+{
+	size_t xAvailableHeapSpaceInBytes;		/* The total heap size currently available - this is the sum of all the free blocks, not the largest block that can be allocated. */
+	size_t xSizeOfLargestFreeBlockInBytes; 	/* The maximum size, in bytes, of all the free blocks within the heap at the time vPortGetHeapStats() is called. */
+	size_t xSizeOfSmallestFreeBlockInBytes; /* The minimum size, in bytes, of all the free blocks within the heap at the time vPortGetHeapStats() is called. */
+	size_t xNumberOfFreeBlocks;				/* The number of free memory blocks within the heap at the time vPortGetHeapStats() is called. */
+	size_t xMinimumEverFreeBytesRemaining;	/* The minimum amount of total free memory (sum of all free blocks) there has been in the heap since the system booted. */
+	size_t xNumberOfSuccessfulAllocations;	/* The number of calls to pvPortMalloc() that have returned a valid memory block. */
+	size_t xNumberOfSuccessfulFrees;		/* The number of calls to vPortFree() that has successfully freed a block of memory. */
+} HeapStats_t;
+
+/*
+ * Used to define multiple heap regions for use by heap_5.c.  This function
+ * must be called before any calls to pvPortMalloc() - not creating a task,
+ * queue, semaphore, mutex, software timer, event group, etc. will result in
+ * pvPortMalloc being called.
+ *
+ * pxHeapRegions passes in an array of HeapRegion_t structures - each of which
+ * defines a region of memory that can be used as the heap.  The array is
+ * terminated by a HeapRegions_t structure that has a size of 0.  The region
+ * with the lowest start address must appear first in the array.
+ */
+void vPortDefineHeapRegions( const HeapRegion_t * const pxHeapRegions ) PRIVILEGED_FUNCTION;
+
+/*
+ * Returns a HeapStats_t structure filled with information about the current
+ * heap state.
+ */
+void vPortGetHeapStats( HeapStats_t *pxHeapStats );
+
+/*
+ * Map to the memory management routines required for the port.
+ */
+void *pvPortMalloc( size_t xSize ) PRIVILEGED_FUNCTION;
+void vPortFree( void *pv ) PRIVILEGED_FUNCTION;
+void vPortInitialiseBlocks( void ) PRIVILEGED_FUNCTION;
+size_t xPortGetFreeHeapSize( void ) PRIVILEGED_FUNCTION;
+size_t xPortGetMinimumEverFreeHeapSize( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Setup the hardware ready for the scheduler to take control.  This generally
+ * sets up a tick interrupt and sets timers for the correct tick frequency.
+ */
+BaseType_t xPortStartScheduler( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Undo any hardware/ISR setup that was performed by xPortStartScheduler() so
+ * the hardware is left in its original condition after the scheduler stops
+ * executing.
+ */
+void vPortEndScheduler( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * The structures and methods of manipulating the MPU are contained within the
+ * port layer.
+ *
+ * Fills the xMPUSettings structure with the memory region information
+ * contained in xRegions.
+ */
+#if( portUSING_MPU_WRAPPERS == 1 )
+	struct xMEMORY_REGION;
+	void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth ) PRIVILEGED_FUNCTION;
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTABLE_H */
+
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h b/Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h
new file mode 100644
index 0000000..0d95130
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h
@@ -0,0 +1,124 @@
+/*
+ * FreeRTOS Kernel V10.3.1
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PROJDEFS_H
+#define PROJDEFS_H
+
+/*
+ * Defines the prototype to which task functions must conform.  Defined in this
+ * file to ensure the type is known before portable.h is included.
+ */
+typedef void (*TaskFunction_t)( void * );
+
+/* Converts a time in milliseconds to a time in ticks.  This macro can be
+overridden by a macro of the same name defined in FreeRTOSConfig.h in case the
+definition here is not suitable for your application. */
+#ifndef pdMS_TO_TICKS
+	#define pdMS_TO_TICKS( xTimeInMs ) ( ( TickType_t ) ( ( ( TickType_t ) ( xTimeInMs ) * ( TickType_t ) configTICK_RATE_HZ ) / ( TickType_t ) 1000 ) )
+#endif
+
+#define pdFALSE			( ( BaseType_t ) 0 )
+#define pdTRUE			( ( BaseType_t ) 1 )
+
+#define pdPASS			( pdTRUE )
+#define pdFAIL			( pdFALSE )
+#define errQUEUE_EMPTY	( ( BaseType_t ) 0 )
+#define errQUEUE_FULL	( ( BaseType_t ) 0 )
+
+/* FreeRTOS error definitions. */
+#define errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY	( -1 )
+#define errQUEUE_BLOCKED						( -4 )
+#define errQUEUE_YIELD							( -5 )
+
+/* Macros used for basic data corruption checks. */
+#ifndef configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES
+	#define configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES 0
+#endif
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	#define pdINTEGRITY_CHECK_VALUE 0x5a5a
+#else
+	#define pdINTEGRITY_CHECK_VALUE 0x5a5a5a5aUL
+#endif
+
+/* The following errno values are used by FreeRTOS+ components, not FreeRTOS
+itself. */
+#define pdFREERTOS_ERRNO_NONE			0	/* No errors */
+#define	pdFREERTOS_ERRNO_ENOENT			2	/* No such file or directory */
+#define	pdFREERTOS_ERRNO_EINTR			4	/* Interrupted system call */
+#define	pdFREERTOS_ERRNO_EIO			5	/* I/O error */
+#define	pdFREERTOS_ERRNO_ENXIO			6	/* No such device or address */
+#define	pdFREERTOS_ERRNO_EBADF			9	/* Bad file number */
+#define	pdFREERTOS_ERRNO_EAGAIN			11	/* No more processes */
+#define	pdFREERTOS_ERRNO_EWOULDBLOCK	11	/* Operation would block */
+#define	pdFREERTOS_ERRNO_ENOMEM			12	/* Not enough memory */
+#define	pdFREERTOS_ERRNO_EACCES			13	/* Permission denied */
+#define	pdFREERTOS_ERRNO_EFAULT			14	/* Bad address */
+#define	pdFREERTOS_ERRNO_EBUSY			16	/* Mount device busy */
+#define	pdFREERTOS_ERRNO_EEXIST			17	/* File exists */
+#define	pdFREERTOS_ERRNO_EXDEV			18	/* Cross-device link */
+#define	pdFREERTOS_ERRNO_ENODEV			19	/* No such device */
+#define	pdFREERTOS_ERRNO_ENOTDIR		20	/* Not a directory */
+#define	pdFREERTOS_ERRNO_EISDIR			21	/* Is a directory */
+#define	pdFREERTOS_ERRNO_EINVAL			22	/* Invalid argument */
+#define	pdFREERTOS_ERRNO_ENOSPC			28	/* No space left on device */
+#define	pdFREERTOS_ERRNO_ESPIPE			29	/* Illegal seek */
+#define	pdFREERTOS_ERRNO_EROFS			30	/* Read only file system */
+#define	pdFREERTOS_ERRNO_EUNATCH		42	/* Protocol driver not attached */
+#define	pdFREERTOS_ERRNO_EBADE			50	/* Invalid exchange */
+#define	pdFREERTOS_ERRNO_EFTYPE			79	/* Inappropriate file type or format */
+#define	pdFREERTOS_ERRNO_ENMFILE		89	/* No more files */
+#define	pdFREERTOS_ERRNO_ENOTEMPTY		90	/* Directory not empty */
+#define	pdFREERTOS_ERRNO_ENAMETOOLONG 	91	/* File or path name too long */
+#define	pdFREERTOS_ERRNO_EOPNOTSUPP		95	/* Operation not supported on transport endpoint */
+#define	pdFREERTOS_ERRNO_ENOBUFS		105	/* No buffer space available */
+#define	pdFREERTOS_ERRNO_ENOPROTOOPT	109	/* Protocol not available */
+#define	pdFREERTOS_ERRNO_EADDRINUSE		112	/* Address already in use */
+#define	pdFREERTOS_ERRNO_ETIMEDOUT		116	/* Connection timed out */
+#define	pdFREERTOS_ERRNO_EINPROGRESS	119	/* Connection already in progress */
+#define	pdFREERTOS_ERRNO_EALREADY		120	/* Socket already connected */
+#define	pdFREERTOS_ERRNO_EADDRNOTAVAIL 	125	/* Address not available */
+#define	pdFREERTOS_ERRNO_EISCONN		127	/* Socket is already connected */
+#define	pdFREERTOS_ERRNO_ENOTCONN		128	/* Socket is not connected */
+#define	pdFREERTOS_ERRNO_ENOMEDIUM		135	/* No medium inserted */
+#define	pdFREERTOS_ERRNO_EILSEQ			138	/* An invalid UTF-16 sequence was encountered. */
+#define	pdFREERTOS_ERRNO_ECANCELED		140	/* Operation canceled. */
+
+/* The following endian values are used by FreeRTOS+ components, not FreeRTOS
+itself. */
+#define pdFREERTOS_LITTLE_ENDIAN		0
+#define pdFREERTOS_BIG_ENDIAN			1
+
+/* Re-defining endian values for generic naming. */
+#define pdLITTLE_ENDIAN					pdFREERTOS_LITTLE_ENDIAN
+#define pdBIG_ENDIAN					pdFREERTOS_BIG_ENDIAN
+
+
+#endif /* PROJDEFS_H */
+
+
+
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/queue.h b/Middlewares/Third_Party/FreeRTOS/Source/include/queue.h
new file mode 100644
index 0000000..52ccca5
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/include/queue.h
@@ -0,0 +1,1655 @@
+/*
+ * FreeRTOS Kernel V10.3.1
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef QUEUE_H
+#define QUEUE_H
+
+#ifndef INC_FREERTOS_H
+	#error "include FreeRTOS.h" must appear in source files before "include queue.h"
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "task.h"
+
+/**
+ * Type by which queues are referenced.  For example, a call to xQueueCreate()
+ * returns an QueueHandle_t variable that can then be used as a parameter to
+ * xQueueSend(), xQueueReceive(), etc.
+ */
+struct QueueDefinition; /* Using old naming convention so as not to break kernel aware debuggers. */
+typedef struct QueueDefinition * QueueHandle_t;
+
+/**
+ * Type by which queue sets are referenced.  For example, a call to
+ * xQueueCreateSet() returns an xQueueSet variable that can then be used as a
+ * parameter to xQueueSelectFromSet(), xQueueAddToSet(), etc.
+ */
+typedef struct QueueDefinition * QueueSetHandle_t;
+
+/**
+ * Queue sets can contain both queues and semaphores, so the
+ * QueueSetMemberHandle_t is defined as a type to be used where a parameter or
+ * return value can be either an QueueHandle_t or an SemaphoreHandle_t.
+ */
+typedef struct QueueDefinition * QueueSetMemberHandle_t;
+
+/* For internal use only. */
+#define	queueSEND_TO_BACK		( ( BaseType_t ) 0 )
+#define	queueSEND_TO_FRONT		( ( BaseType_t ) 1 )
+#define queueOVERWRITE			( ( BaseType_t ) 2 )
+
+/* For internal use only.  These definitions *must* match those in queue.c. */
+#define queueQUEUE_TYPE_BASE				( ( uint8_t ) 0U )
+#define queueQUEUE_TYPE_SET					( ( uint8_t ) 0U )
+#define queueQUEUE_TYPE_MUTEX 				( ( uint8_t ) 1U )
+#define queueQUEUE_TYPE_COUNTING_SEMAPHORE	( ( uint8_t ) 2U )
+#define queueQUEUE_TYPE_BINARY_SEMAPHORE	( ( uint8_t ) 3U )
+#define queueQUEUE_TYPE_RECURSIVE_MUTEX		( ( uint8_t ) 4U )
+
+/**
+ * queue. h
+ * <pre>
+ QueueHandle_t xQueueCreate(
+							  UBaseType_t uxQueueLength,
+							  UBaseType_t uxItemSize
+						  );
+ * </pre>
+ *
+ * Creates a new queue instance, and returns a handle by which the new queue
+ * can be referenced.
+ *
+ * Internally, within the FreeRTOS implementation, queues use two blocks of
+ * memory.  The first block is used to hold the queue's data structures.  The
+ * second block is used to hold items placed into the queue.  If a queue is
+ * created using xQueueCreate() then both blocks of memory are automatically
+ * dynamically allocated inside the xQueueCreate() function.  (see
+ * http://www.freertos.org/a00111.html).  If a queue is created using
+ * xQueueCreateStatic() then the application writer must provide the memory that
+ * will get used by the queue.  xQueueCreateStatic() therefore allows a queue to
+ * be created without using any dynamic memory allocation.
+ *
+ * http://www.FreeRTOS.org/Embedded-RTOS-Queues.html
+ *
+ * @param uxQueueLength The maximum number of items that the queue can contain.
+ *
+ * @param uxItemSize The number of bytes each item in the queue will require.
+ * Items are queued by copy, not by reference, so this is the number of bytes
+ * that will be copied for each posted item.  Each item on the queue must be
+ * the same size.
+ *
+ * @return If the queue is successfully create then a handle to the newly
+ * created queue is returned.  If the queue cannot be created then 0 is
+ * returned.
+ *
+ * Example usage:
+   <pre>
+ struct AMessage
+ {
+	char ucMessageID;
+	char ucData[ 20 ];
+ };
+
+ void vATask( void *pvParameters )
+ {
+ QueueHandle_t xQueue1, xQueue2;
+
+	// Create a queue capable of containing 10 uint32_t values.
+	xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );
+	if( xQueue1 == 0 )
+	{
+		// Queue was not created and must not be used.
+	}
+
+	// Create a queue capable of containing 10 pointers to AMessage structures.
+	// These should be passed by pointer as they contain a lot of data.
+	xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
+	if( xQueue2 == 0 )
+	{
+		// Queue was not created and must not be used.
+	}
+
+	// ... Rest of task code.
+ }
+ </pre>
+ * \defgroup xQueueCreate xQueueCreate
+ * \ingroup QueueManagement
+ */
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+	#define xQueueCreate( uxQueueLength, uxItemSize ) xQueueGenericCreate( ( uxQueueLength ), ( uxItemSize ), ( queueQUEUE_TYPE_BASE ) )
+#endif
+
+/**
+ * queue. h
+ * <pre>
+ QueueHandle_t xQueueCreateStatic(
+							  UBaseType_t uxQueueLength,
+							  UBaseType_t uxItemSize,
+							  uint8_t *pucQueueStorageBuffer,
+							  StaticQueue_t *pxQueueBuffer
+						  );
+ * </pre>
+ *
+ * Creates a new queue instance, and returns a handle by which the new queue
+ * can be referenced.
+ *
+ * Internally, within the FreeRTOS implementation, queues use two blocks of
+ * memory.  The first block is used to hold the queue's data structures.  The
+ * second block is used to hold items placed into the queue.  If a queue is
+ * created using xQueueCreate() then both blocks of memory are automatically
+ * dynamically allocated inside the xQueueCreate() function.  (see
+ * http://www.freertos.org/a00111.html).  If a queue is created using
+ * xQueueCreateStatic() then the application writer must provide the memory that
+ * will get used by the queue.  xQueueCreateStatic() therefore allows a queue to
+ * be created without using any dynamic memory allocation.
+ *
+ * http://www.FreeRTOS.org/Embedded-RTOS-Queues.html
+ *
+ * @param uxQueueLength The maximum number of items that the queue can contain.
+ *
+ * @param uxItemSize The number of bytes each item in the queue will require.
+ * Items are queued by copy, not by reference, so this is the number of bytes
+ * that will be copied for each posted item.  Each item on the queue must be
+ * the same size.
+ *
+ * @param pucQueueStorageBuffer If uxItemSize is not zero then
+ * pucQueueStorageBuffer must point to a uint8_t array that is at least large
+ * enough to hold the maximum number of items that can be in the queue at any
+ * one time - which is ( uxQueueLength * uxItemsSize ) bytes.  If uxItemSize is
+ * zero then pucQueueStorageBuffer can be NULL.
+ *
+ * @param pxQueueBuffer Must point to a variable of type StaticQueue_t, which
+ * will be used to hold the queue's data structure.
+ *
+ * @return If the queue is created then a handle to the created queue is
+ * returned.  If pxQueueBuffer is NULL then NULL is returned.
+ *
+ * Example usage:
+   <pre>
+ struct AMessage
+ {
+	char ucMessageID;
+	char ucData[ 20 ];
+ };
+
+ #define QUEUE_LENGTH 10
+ #define ITEM_SIZE sizeof( uint32_t )
+
+ // xQueueBuffer will hold the queue structure.
+ StaticQueue_t xQueueBuffer;
+
+ // ucQueueStorage will hold the items posted to the queue.  Must be at least
+ // [(queue length) * ( queue item size)] bytes long.
+ uint8_t ucQueueStorage[ QUEUE_LENGTH * ITEM_SIZE ];
+
+ void vATask( void *pvParameters )
+ {
+ QueueHandle_t xQueue1;
+
+	// Create a queue capable of containing 10 uint32_t values.
+	xQueue1 = xQueueCreate( QUEUE_LENGTH, // The number of items the queue can hold.
+							ITEM_SIZE	  // The size of each item in the queue
+							&( ucQueueStorage[ 0 ] ), // The buffer that will hold the items in the queue.
+							&xQueueBuffer ); // The buffer that will hold the queue structure.
+
+	// The queue is guaranteed to be created successfully as no dynamic memory
+	// allocation is used.  Therefore xQueue1 is now a handle to a valid queue.
+
+	// ... Rest of task code.
+ }
+ </pre>
+ * \defgroup xQueueCreateStatic xQueueCreateStatic
+ * \ingroup QueueManagement
+ */
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+	#define xQueueCreateStatic( uxQueueLength, uxItemSize, pucQueueStorage, pxQueueBuffer ) xQueueGenericCreateStatic( ( uxQueueLength ), ( uxItemSize ), ( pucQueueStorage ), ( pxQueueBuffer ), ( queueQUEUE_TYPE_BASE ) )
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+/**
+ * queue. h
+ * <pre>
+ BaseType_t xQueueSendToToFront(
+								   QueueHandle_t	xQueue,
+								   const void		*pvItemToQueue,
+								   TickType_t		xTicksToWait
+							   );
+ * </pre>
+ *
+ * Post an item to the front of a queue.  The item is queued by copy, not by
+ * reference.  This function must not be called from an interrupt service
+ * routine.  See xQueueSendFromISR () for an alternative which may be used
+ * in an ISR.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param xTicksToWait The maximum amount of time the task should block
+ * waiting for space to become available on the queue, should it already
+ * be full.  The call will return immediately if this is set to 0 and the
+ * queue is full.  The time is defined in tick periods so the constant
+ * portTICK_PERIOD_MS should be used to convert to real time if this is required.
+ *
+ * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL.
+ *
+ * Example usage:
+   <pre>
+ struct AMessage
+ {
+	char ucMessageID;
+	char ucData[ 20 ];
+ } xMessage;
+
+ uint32_t ulVar = 10UL;
+
+ void vATask( void *pvParameters )
+ {
+ QueueHandle_t xQueue1, xQueue2;
+ struct AMessage *pxMessage;
+
+	// Create a queue capable of containing 10 uint32_t values.
+	xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );
+
+	// Create a queue capable of containing 10 pointers to AMessage structures.
+	// These should be passed by pointer as they contain a lot of data.
+	xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
+
+	// ...
+
+	if( xQueue1 != 0 )
+	{
+		// Send an uint32_t.  Wait for 10 ticks for space to become
+		// available if necessary.
+		if( xQueueSendToFront( xQueue1, ( void * ) &ulVar, ( TickType_t ) 10 ) != pdPASS )
+		{
+			// Failed to post the message, even after 10 ticks.
+		}
+	}
+
+	if( xQueue2 != 0 )
+	{
+		// Send a pointer to a struct AMessage object.  Don't block if the
+		// queue is already full.
+		pxMessage = & xMessage;
+		xQueueSendToFront( xQueue2, ( void * ) &pxMessage, ( TickType_t ) 0 );
+	}
+
+	// ... Rest of task code.
+ }
+ </pre>
+ * \defgroup xQueueSend xQueueSend
+ * \ingroup QueueManagement
+ */
+#define xQueueSendToFront( xQueue, pvItemToQueue, xTicksToWait ) xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), ( xTicksToWait ), queueSEND_TO_FRONT )
+
+/**
+ * queue. h
+ * <pre>
+ BaseType_t xQueueSendToBack(
+								   QueueHandle_t	xQueue,
+								   const void		*pvItemToQueue,
+								   TickType_t		xTicksToWait
+							   );
+ * </pre>
+ *
+ * This is a macro that calls xQueueGenericSend().
+ *
+ * Post an item to the back of a queue.  The item is queued by copy, not by
+ * reference.  This function must not be called from an interrupt service
+ * routine.  See xQueueSendFromISR () for an alternative which may be used
+ * in an ISR.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param xTicksToWait The maximum amount of time the task should block
+ * waiting for space to become available on the queue, should it already
+ * be full.  The call will return immediately if this is set to 0 and the queue
+ * is full.  The  time is defined in tick periods so the constant
+ * portTICK_PERIOD_MS should be used to convert to real time if this is required.
+ *
+ * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL.
+ *
+ * Example usage:
+   <pre>
+ struct AMessage
+ {
+	char ucMessageID;
+	char ucData[ 20 ];
+ } xMessage;
+
+ uint32_t ulVar = 10UL;
+
+ void vATask( void *pvParameters )
+ {
+ QueueHandle_t xQueue1, xQueue2;
+ struct AMessage *pxMessage;
+
+	// Create a queue capable of containing 10 uint32_t values.
+	xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );
+
+	// Create a queue capable of containing 10 pointers to AMessage structures.
+	// These should be passed by pointer as they contain a lot of data.
+	xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
+
+	// ...
+
+	if( xQueue1 != 0 )
+	{
+		// Send an uint32_t.  Wait for 10 ticks for space to become
+		// available if necessary.
+		if( xQueueSendToBack( xQueue1, ( void * ) &ulVar, ( TickType_t ) 10 ) != pdPASS )
+		{
+			// Failed to post the message, even after 10 ticks.
+		}
+	}
+
+	if( xQueue2 != 0 )
+	{
+		// Send a pointer to a struct AMessage object.  Don't block if the
+		// queue is already full.
+		pxMessage = & xMessage;
+		xQueueSendToBack( xQueue2, ( void * ) &pxMessage, ( TickType_t ) 0 );
+	}
+
+	// ... Rest of task code.
+ }
+ </pre>
+ * \defgroup xQueueSend xQueueSend
+ * \ingroup QueueManagement
+ */
+#define xQueueSendToBack( xQueue, pvItemToQueue, xTicksToWait ) xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), ( xTicksToWait ), queueSEND_TO_BACK )
+
+/**
+ * queue. h
+ * <pre>
+ BaseType_t xQueueSend(
+							  QueueHandle_t xQueue,
+							  const void * pvItemToQueue,
+							  TickType_t xTicksToWait
+						 );
+ * </pre>
+ *
+ * This is a macro that calls xQueueGenericSend().  It is included for
+ * backward compatibility with versions of FreeRTOS.org that did not
+ * include the xQueueSendToFront() and xQueueSendToBack() macros.  It is
+ * equivalent to xQueueSendToBack().
+ *
+ * Post an item on a queue.  The item is queued by copy, not by reference.
+ * This function must not be called from an interrupt service routine.
+ * See xQueueSendFromISR () for an alternative which may be used in an ISR.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param xTicksToWait The maximum amount of time the task should block
+ * waiting for space to become available on the queue, should it already
+ * be full.  The call will return immediately if this is set to 0 and the
+ * queue is full.  The time is defined in tick periods so the constant
+ * portTICK_PERIOD_MS should be used to convert to real time if this is required.
+ *
+ * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL.
+ *
+ * Example usage:
+   <pre>
+ struct AMessage
+ {
+	char ucMessageID;
+	char ucData[ 20 ];
+ } xMessage;
+
+ uint32_t ulVar = 10UL;
+
+ void vATask( void *pvParameters )
+ {
+ QueueHandle_t xQueue1, xQueue2;
+ struct AMessage *pxMessage;
+
+	// Create a queue capable of containing 10 uint32_t values.
+	xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );
+
+	// Create a queue capable of containing 10 pointers to AMessage structures.
+	// These should be passed by pointer as they contain a lot of data.
+	xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
+
+	// ...
+
+	if( xQueue1 != 0 )
+	{
+		// Send an uint32_t.  Wait for 10 ticks for space to become
+		// available if necessary.
+		if( xQueueSend( xQueue1, ( void * ) &ulVar, ( TickType_t ) 10 ) != pdPASS )
+		{
+			// Failed to post the message, even after 10 ticks.
+		}
+	}
+
+	if( xQueue2 != 0 )
+	{
+		// Send a pointer to a struct AMessage object.  Don't block if the
+		// queue is already full.
+		pxMessage = & xMessage;
+		xQueueSend( xQueue2, ( void * ) &pxMessage, ( TickType_t ) 0 );
+	}
+
+	// ... Rest of task code.
+ }
+ </pre>
+ * \defgroup xQueueSend xQueueSend
+ * \ingroup QueueManagement
+ */
+#define xQueueSend( xQueue, pvItemToQueue, xTicksToWait ) xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), ( xTicksToWait ), queueSEND_TO_BACK )
+
+/**
+ * queue. h
+ * <pre>
+ BaseType_t xQueueOverwrite(
+							  QueueHandle_t xQueue,
+							  const void * pvItemToQueue
+						 );
+ * </pre>
+ *
+ * Only for use with queues that have a length of one - so the queue is either
+ * empty or full.
+ *
+ * Post an item on a queue.  If the queue is already full then overwrite the
+ * value held in the queue.  The item is queued by copy, not by reference.
+ *
+ * This function must not be called from an interrupt service routine.
+ * See xQueueOverwriteFromISR () for an alternative which may be used in an ISR.
+ *
+ * @param xQueue The handle of the queue to which the data is being sent.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @return xQueueOverwrite() is a macro that calls xQueueGenericSend(), and
+ * therefore has the same return values as xQueueSendToFront().  However, pdPASS
+ * is the only value that can be returned because xQueueOverwrite() will write
+ * to the queue even when the queue is already full.
+ *
+ * Example usage:
+   <pre>
+
+ void vFunction( void *pvParameters )
+ {
+ QueueHandle_t xQueue;
+ uint32_t ulVarToSend, ulValReceived;
+
+	// Create a queue to hold one uint32_t value.  It is strongly
+	// recommended *not* to use xQueueOverwrite() on queues that can
+	// contain more than one value, and doing so will trigger an assertion
+	// if configASSERT() is defined.
+	xQueue = xQueueCreate( 1, sizeof( uint32_t ) );
+
+	// Write the value 10 to the queue using xQueueOverwrite().
+	ulVarToSend = 10;
+	xQueueOverwrite( xQueue, &ulVarToSend );
+
+	// Peeking the queue should now return 10, but leave the value 10 in
+	// the queue.  A block time of zero is used as it is known that the
+	// queue holds a value.
+	ulValReceived = 0;
+	xQueuePeek( xQueue, &ulValReceived, 0 );
+
+	if( ulValReceived != 10 )
+	{
+		// Error unless the item was removed by a different task.
+	}
+
+	// The queue is still full.  Use xQueueOverwrite() to overwrite the
+	// value held in the queue with 100.
+	ulVarToSend = 100;
+	xQueueOverwrite( xQueue, &ulVarToSend );
+
+	// This time read from the queue, leaving the queue empty once more.
+	// A block time of 0 is used again.
+	xQueueReceive( xQueue, &ulValReceived, 0 );
+
+	// The value read should be the last value written, even though the
+	// queue was already full when the value was written.
+	if( ulValReceived != 100 )
+	{
+		// Error!
+	}
+
+	// ...
+}
+ </pre>
+ * \defgroup xQueueOverwrite xQueueOverwrite
+ * \ingroup QueueManagement
+ */
+#define xQueueOverwrite( xQueue, pvItemToQueue ) xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), 0, queueOVERWRITE )
+
+
+/**
+ * queue. h
+ * <pre>
+ BaseType_t xQueueGenericSend(
+									QueueHandle_t xQueue,
+									const void * pvItemToQueue,
+									TickType_t xTicksToWait
+									BaseType_t xCopyPosition
+								);
+ * </pre>
+ *
+ * It is preferred that the macros xQueueSend(), xQueueSendToFront() and
+ * xQueueSendToBack() are used in place of calling this function directly.
+ *
+ * Post an item on a queue.  The item is queued by copy, not by reference.
+ * This function must not be called from an interrupt service routine.
+ * See xQueueSendFromISR () for an alternative which may be used in an ISR.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param xTicksToWait The maximum amount of time the task should block
+ * waiting for space to become available on the queue, should it already
+ * be full.  The call will return immediately if this is set to 0 and the
+ * queue is full.  The time is defined in tick periods so the constant
+ * portTICK_PERIOD_MS should be used to convert to real time if this is required.
+ *
+ * @param xCopyPosition Can take the value queueSEND_TO_BACK to place the
+ * item at the back of the queue, or queueSEND_TO_FRONT to place the item
+ * at the front of the queue (for high priority messages).
+ *
+ * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL.
+ *
+ * Example usage:
+   <pre>
+ struct AMessage
+ {
+	char ucMessageID;
+	char ucData[ 20 ];
+ } xMessage;
+
+ uint32_t ulVar = 10UL;
+
+ void vATask( void *pvParameters )
+ {
+ QueueHandle_t xQueue1, xQueue2;
+ struct AMessage *pxMessage;
+
+	// Create a queue capable of containing 10 uint32_t values.
+	xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );
+
+	// Create a queue capable of containing 10 pointers to AMessage structures.
+	// These should be passed by pointer as they contain a lot of data.
+	xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
+
+	// ...
+
+	if( xQueue1 != 0 )
+	{
+		// Send an uint32_t.  Wait for 10 ticks for space to become
+		// available if necessary.
+		if( xQueueGenericSend( xQueue1, ( void * ) &ulVar, ( TickType_t ) 10, queueSEND_TO_BACK ) != pdPASS )
+		{
+			// Failed to post the message, even after 10 ticks.
+		}
+	}
+
+	if( xQueue2 != 0 )
+	{
+		// Send a pointer to a struct AMessage object.  Don't block if the
+		// queue is already full.
+		pxMessage = & xMessage;
+		xQueueGenericSend( xQueue2, ( void * ) &pxMessage, ( TickType_t ) 0, queueSEND_TO_BACK );
+	}
+
+	// ... Rest of task code.
+ }
+ </pre>
+ * \defgroup xQueueSend xQueueSend
+ * \ingroup QueueManagement
+ */
+BaseType_t xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, const BaseType_t xCopyPosition ) PRIVILEGED_FUNCTION;
+
+/**
+ * queue. h
+ * <pre>
+ BaseType_t xQueuePeek(
+							 QueueHandle_t xQueue,
+							 void * const pvBuffer,
+							 TickType_t xTicksToWait
+						 );</pre>
+ *
+ * Receive an item from a queue without removing the item from the queue.
+ * The item is received by copy so a buffer of adequate size must be
+ * provided.  The number of bytes copied into the buffer was defined when
+ * the queue was created.
+ *
+ * Successfully received items remain on the queue so will be returned again
+ * by the next call, or a call to xQueueReceive().
+ *
+ * This macro must not be used in an interrupt service routine.  See
+ * xQueuePeekFromISR() for an alternative that can be called from an interrupt
+ * service routine.
+ *
+ * @param xQueue The handle to the queue from which the item is to be
+ * received.
+ *
+ * @param pvBuffer Pointer to the buffer into which the received item will
+ * be copied.
+ *
+ * @param xTicksToWait The maximum amount of time the task should block
+ * waiting for an item to receive should the queue be empty at the time
+ * of the call.	 The time is defined in tick periods so the constant
+ * portTICK_PERIOD_MS should be used to convert to real time if this is required.
+ * xQueuePeek() will return immediately if xTicksToWait is 0 and the queue
+ * is empty.
+ *
+ * @return pdTRUE if an item was successfully received from the queue,
+ * otherwise pdFALSE.
+ *
+ * Example usage:
+   <pre>
+ struct AMessage
+ {
+	char ucMessageID;
+	char ucData[ 20 ];
+ } xMessage;
+
+ QueueHandle_t xQueue;
+
+ // Task to create a queue and post a value.
+ void vATask( void *pvParameters )
+ {
+ struct AMessage *pxMessage;
+
+	// Create a queue capable of containing 10 pointers to AMessage structures.
+	// These should be passed by pointer as they contain a lot of data.
+	xQueue = xQueueCreate( 10, sizeof( struct AMessage * ) );
+	if( xQueue == 0 )
+	{
+		// Failed to create the queue.
+	}
+
+	// ...
+
+	// Send a pointer to a struct AMessage object.  Don't block if the
+	// queue is already full.
+	pxMessage = & xMessage;
+	xQueueSend( xQueue, ( void * ) &pxMessage, ( TickType_t ) 0 );
+
+	// ... Rest of task code.
+ }
+
+ // Task to peek the data from the queue.
+ void vADifferentTask( void *pvParameters )
+ {
+ struct AMessage *pxRxedMessage;
+
+	if( xQueue != 0 )
+	{
+		// Peek a message on the created queue.  Block for 10 ticks if a
+		// message is not immediately available.
+		if( xQueuePeek( xQueue, &( pxRxedMessage ), ( TickType_t ) 10 ) )
+		{
+			// pcRxedMessage now points to the struct AMessage variable posted
+			// by vATask, but the item still remains on the queue.
+		}
+	}
+
+	// ... Rest of task code.
+ }
+ </pre>
+ * \defgroup xQueuePeek xQueuePeek
+ * \ingroup QueueManagement
+ */
+BaseType_t xQueuePeek( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+/**
+ * queue. h
+ * <pre>
+ BaseType_t xQueuePeekFromISR(
+									QueueHandle_t xQueue,
+									void *pvBuffer,
+								);</pre>
+ *
+ * A version of xQueuePeek() that can be called from an interrupt service
+ * routine (ISR).
+ *
+ * Receive an item from a queue without removing the item from the queue.
+ * The item is received by copy so a buffer of adequate size must be
+ * provided.  The number of bytes copied into the buffer was defined when
+ * the queue was created.
+ *
+ * Successfully received items remain on the queue so will be returned again
+ * by the next call, or a call to xQueueReceive().
+ *
+ * @param xQueue The handle to the queue from which the item is to be
+ * received.
+ *
+ * @param pvBuffer Pointer to the buffer into which the received item will
+ * be copied.
+ *
+ * @return pdTRUE if an item was successfully received from the queue,
+ * otherwise pdFALSE.
+ *
+ * \defgroup xQueuePeekFromISR xQueuePeekFromISR
+ * \ingroup QueueManagement
+ */
+BaseType_t xQueuePeekFromISR( QueueHandle_t xQueue, void * const pvBuffer ) PRIVILEGED_FUNCTION;
+
+/**
+ * queue. h
+ * <pre>
+ BaseType_t xQueueReceive(
+								 QueueHandle_t xQueue,
+								 void *pvBuffer,
+								 TickType_t xTicksToWait
+							);</pre>
+ *
+ * Receive an item from a queue.  The item is received by copy so a buffer of
+ * adequate size must be provided.  The number of bytes copied into the buffer
+ * was defined when the queue was created.
+ *
+ * Successfully received items are removed from the queue.
+ *
+ * This function must not be used in an interrupt service routine.  See
+ * xQueueReceiveFromISR for an alternative that can.
+ *
+ * @param xQueue The handle to the queue from which the item is to be
+ * received.
+ *
+ * @param pvBuffer Pointer to the buffer into which the received item will
+ * be copied.
+ *
+ * @param xTicksToWait The maximum amount of time the task should block
+ * waiting for an item to receive should the queue be empty at the time
+ * of the call.	 xQueueReceive() will return immediately if xTicksToWait
+ * is zero and the queue is empty.  The time is defined in tick periods so the
+ * constant portTICK_PERIOD_MS should be used to convert to real time if this is
+ * required.
+ *
+ * @return pdTRUE if an item was successfully received from the queue,
+ * otherwise pdFALSE.
+ *
+ * Example usage:
+   <pre>
+ struct AMessage
+ {
+	char ucMessageID;
+	char ucData[ 20 ];
+ } xMessage;
+
+ QueueHandle_t xQueue;
+
+ // Task to create a queue and post a value.
+ void vATask( void *pvParameters )
+ {
+ struct AMessage *pxMessage;
+
+	// Create a queue capable of containing 10 pointers to AMessage structures.
+	// These should be passed by pointer as they contain a lot of data.
+	xQueue = xQueueCreate( 10, sizeof( struct AMessage * ) );
+	if( xQueue == 0 )
+	{
+		// Failed to create the queue.
+	}
+
+	// ...
+
+	// Send a pointer to a struct AMessage object.  Don't block if the
+	// queue is already full.
+	pxMessage = & xMessage;
+	xQueueSend( xQueue, ( void * ) &pxMessage, ( TickType_t ) 0 );
+
+	// ... Rest of task code.
+ }
+
+ // Task to receive from the queue.
+ void vADifferentTask( void *pvParameters )
+ {
+ struct AMessage *pxRxedMessage;
+
+	if( xQueue != 0 )
+	{
+		// Receive a message on the created queue.  Block for 10 ticks if a
+		// message is not immediately available.
+		if( xQueueReceive( xQueue, &( pxRxedMessage ), ( TickType_t ) 10 ) )
+		{
+			// pcRxedMessage now points to the struct AMessage variable posted
+			// by vATask.
+		}
+	}
+
+	// ... Rest of task code.
+ }
+ </pre>
+ * \defgroup xQueueReceive xQueueReceive
+ * \ingroup QueueManagement
+ */
+BaseType_t xQueueReceive( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+/**
+ * queue. h
+ * <pre>UBaseType_t uxQueueMessagesWaiting( const QueueHandle_t xQueue );</pre>
+ *
+ * Return the number of messages stored in a queue.
+ *
+ * @param xQueue A handle to the queue being queried.
+ *
+ * @return The number of messages available in the queue.
+ *
+ * \defgroup uxQueueMessagesWaiting uxQueueMessagesWaiting
+ * \ingroup QueueManagement
+ */
+UBaseType_t uxQueueMessagesWaiting( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+
+/**
+ * queue. h
+ * <pre>UBaseType_t uxQueueSpacesAvailable( const QueueHandle_t xQueue );</pre>
+ *
+ * Return the number of free spaces available in a queue.  This is equal to the
+ * number of items that can be sent to the queue before the queue becomes full
+ * if no items are removed.
+ *
+ * @param xQueue A handle to the queue being queried.
+ *
+ * @return The number of spaces available in the queue.
+ *
+ * \defgroup uxQueueMessagesWaiting uxQueueMessagesWaiting
+ * \ingroup QueueManagement
+ */
+UBaseType_t uxQueueSpacesAvailable( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+
+/**
+ * queue. h
+ * <pre>void vQueueDelete( QueueHandle_t xQueue );</pre>
+ *
+ * Delete a queue - freeing all the memory allocated for storing of items
+ * placed on the queue.
+ *
+ * @param xQueue A handle to the queue to be deleted.
+ *
+ * \defgroup vQueueDelete vQueueDelete
+ * \ingroup QueueManagement
+ */
+void vQueueDelete( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+
+/**
+ * queue. h
+ * <pre>
+ BaseType_t xQueueSendToFrontFromISR(
+										 QueueHandle_t xQueue,
+										 const void *pvItemToQueue,
+										 BaseType_t *pxHigherPriorityTaskWoken
+									  );
+ </pre>
+ *
+ * This is a macro that calls xQueueGenericSendFromISR().
+ *
+ * Post an item to the front of a queue.  It is safe to use this macro from
+ * within an interrupt service routine.
+ *
+ * Items are queued by copy not reference so it is preferable to only
+ * queue small items, especially when called from an ISR.  In most cases
+ * it would be preferable to store a pointer to the item being queued.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param pxHigherPriorityTaskWoken xQueueSendToFrontFromISR() will set
+ * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task
+ * to unblock, and the unblocked task has a priority higher than the currently
+ * running task.  If xQueueSendToFromFromISR() sets this value to pdTRUE then
+ * a context switch should be requested before the interrupt is exited.
+ *
+ * @return pdTRUE if the data was successfully sent to the queue, otherwise
+ * errQUEUE_FULL.
+ *
+ * Example usage for buffered IO (where the ISR can obtain more than one value
+ * per call):
+   <pre>
+ void vBufferISR( void )
+ {
+ char cIn;
+ BaseType_t xHigherPrioritTaskWoken;
+
+	// We have not woken a task at the start of the ISR.
+	xHigherPriorityTaskWoken = pdFALSE;
+
+	// Loop until the buffer is empty.
+	do
+	{
+		// Obtain a byte from the buffer.
+		cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );
+
+		// Post the byte.
+		xQueueSendToFrontFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWoken );
+
+	} while( portINPUT_BYTE( BUFFER_COUNT ) );
+
+	// Now the buffer is empty we can switch context if necessary.
+	if( xHigherPriorityTaskWoken )
+	{
+		taskYIELD ();
+	}
+ }
+ </pre>
+ *
+ * \defgroup xQueueSendFromISR xQueueSendFromISR
+ * \ingroup QueueManagement
+ */
+#define xQueueSendToFrontFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) xQueueGenericSendFromISR( ( xQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueSEND_TO_FRONT )
+
+
+/**
+ * queue. h
+ * <pre>
+ BaseType_t xQueueSendToBackFromISR(
+										 QueueHandle_t xQueue,
+										 const void *pvItemToQueue,
+										 BaseType_t *pxHigherPriorityTaskWoken
+									  );
+ </pre>
+ *
+ * This is a macro that calls xQueueGenericSendFromISR().
+ *
+ * Post an item to the back of a queue.  It is safe to use this macro from
+ * within an interrupt service routine.
+ *
+ * Items are queued by copy not reference so it is preferable to only
+ * queue small items, especially when called from an ISR.  In most cases
+ * it would be preferable to store a pointer to the item being queued.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param pxHigherPriorityTaskWoken xQueueSendToBackFromISR() will set
+ * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task
+ * to unblock, and the unblocked task has a priority higher than the currently
+ * running task.  If xQueueSendToBackFromISR() sets this value to pdTRUE then
+ * a context switch should be requested before the interrupt is exited.
+ *
+ * @return pdTRUE if the data was successfully sent to the queue, otherwise
+ * errQUEUE_FULL.
+ *
+ * Example usage for buffered IO (where the ISR can obtain more than one value
+ * per call):
+   <pre>
+ void vBufferISR( void )
+ {
+ char cIn;
+ BaseType_t xHigherPriorityTaskWoken;
+
+	// We have not woken a task at the start of the ISR.
+	xHigherPriorityTaskWoken = pdFALSE;
+
+	// Loop until the buffer is empty.
+	do
+	{
+		// Obtain a byte from the buffer.
+		cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );
+
+		// Post the byte.
+		xQueueSendToBackFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWoken );
+
+	} while( portINPUT_BYTE( BUFFER_COUNT ) );
+
+	// Now the buffer is empty we can switch context if necessary.
+	if( xHigherPriorityTaskWoken )
+	{
+		taskYIELD ();
+	}
+ }
+ </pre>
+ *
+ * \defgroup xQueueSendFromISR xQueueSendFromISR
+ * \ingroup QueueManagement
+ */
+#define xQueueSendToBackFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) xQueueGenericSendFromISR( ( xQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueSEND_TO_BACK )
+
+/**
+ * queue. h
+ * <pre>
+ BaseType_t xQueueOverwriteFromISR(
+							  QueueHandle_t xQueue,
+							  const void * pvItemToQueue,
+							  BaseType_t *pxHigherPriorityTaskWoken
+						 );
+ * </pre>
+ *
+ * A version of xQueueOverwrite() that can be used in an interrupt service
+ * routine (ISR).
+ *
+ * Only for use with queues that can hold a single item - so the queue is either
+ * empty or full.
+ *
+ * Post an item on a queue.  If the queue is already full then overwrite the
+ * value held in the queue.  The item is queued by copy, not by reference.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param pxHigherPriorityTaskWoken xQueueOverwriteFromISR() will set
+ * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task
+ * to unblock, and the unblocked task has a priority higher than the currently
+ * running task.  If xQueueOverwriteFromISR() sets this value to pdTRUE then
+ * a context switch should be requested before the interrupt is exited.
+ *
+ * @return xQueueOverwriteFromISR() is a macro that calls
+ * xQueueGenericSendFromISR(), and therefore has the same return values as
+ * xQueueSendToFrontFromISR().  However, pdPASS is the only value that can be
+ * returned because xQueueOverwriteFromISR() will write to the queue even when
+ * the queue is already full.
+ *
+ * Example usage:
+   <pre>
+
+ QueueHandle_t xQueue;
+
+ void vFunction( void *pvParameters )
+ {
+ 	// Create a queue to hold one uint32_t value.  It is strongly
+	// recommended *not* to use xQueueOverwriteFromISR() on queues that can
+	// contain more than one value, and doing so will trigger an assertion
+	// if configASSERT() is defined.
+	xQueue = xQueueCreate( 1, sizeof( uint32_t ) );
+}
+
+void vAnInterruptHandler( void )
+{
+// xHigherPriorityTaskWoken must be set to pdFALSE before it is used.
+BaseType_t xHigherPriorityTaskWoken = pdFALSE;
+uint32_t ulVarToSend, ulValReceived;
+
+	// Write the value 10 to the queue using xQueueOverwriteFromISR().
+	ulVarToSend = 10;
+	xQueueOverwriteFromISR( xQueue, &ulVarToSend, &xHigherPriorityTaskWoken );
+
+	// The queue is full, but calling xQueueOverwriteFromISR() again will still
+	// pass because the value held in the queue will be overwritten with the
+	// new value.
+	ulVarToSend = 100;
+	xQueueOverwriteFromISR( xQueue, &ulVarToSend, &xHigherPriorityTaskWoken );
+
+	// Reading from the queue will now return 100.
+
+	// ...
+
+	if( xHigherPrioritytaskWoken == pdTRUE )
+	{
+		// Writing to the queue caused a task to unblock and the unblocked task
+		// has a priority higher than or equal to the priority of the currently
+		// executing task (the task this interrupt interrupted).  Perform a context
+		// switch so this interrupt returns directly to the unblocked task.
+		portYIELD_FROM_ISR(); // or portEND_SWITCHING_ISR() depending on the port.
+	}
+}
+ </pre>
+ * \defgroup xQueueOverwriteFromISR xQueueOverwriteFromISR
+ * \ingroup QueueManagement
+ */
+#define xQueueOverwriteFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) xQueueGenericSendFromISR( ( xQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueOVERWRITE )
+
+/**
+ * queue. h
+ * <pre>
+ BaseType_t xQueueSendFromISR(
+									 QueueHandle_t xQueue,
+									 const void *pvItemToQueue,
+									 BaseType_t *pxHigherPriorityTaskWoken
+								);
+ </pre>
+ *
+ * This is a macro that calls xQueueGenericSendFromISR().  It is included
+ * for backward compatibility with versions of FreeRTOS.org that did not
+ * include the xQueueSendToBackFromISR() and xQueueSendToFrontFromISR()
+ * macros.
+ *
+ * Post an item to the back of a queue.  It is safe to use this function from
+ * within an interrupt service routine.
+ *
+ * Items are queued by copy not reference so it is preferable to only
+ * queue small items, especially when called from an ISR.  In most cases
+ * it would be preferable to store a pointer to the item being queued.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param pxHigherPriorityTaskWoken xQueueSendFromISR() will set
+ * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task
+ * to unblock, and the unblocked task has a priority higher than the currently
+ * running task.  If xQueueSendFromISR() sets this value to pdTRUE then
+ * a context switch should be requested before the interrupt is exited.
+ *
+ * @return pdTRUE if the data was successfully sent to the queue, otherwise
+ * errQUEUE_FULL.
+ *
+ * Example usage for buffered IO (where the ISR can obtain more than one value
+ * per call):
+   <pre>
+ void vBufferISR( void )
+ {
+ char cIn;
+ BaseType_t xHigherPriorityTaskWoken;
+
+	// We have not woken a task at the start of the ISR.
+	xHigherPriorityTaskWoken = pdFALSE;
+
+	// Loop until the buffer is empty.
+	do
+	{
+		// Obtain a byte from the buffer.
+		cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );
+
+		// Post the byte.
+		xQueueSendFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWoken );
+
+	} while( portINPUT_BYTE( BUFFER_COUNT ) );
+
+	// Now the buffer is empty we can switch context if necessary.
+	if( xHigherPriorityTaskWoken )
+	{
+		// Actual macro used here is port specific.
+		portYIELD_FROM_ISR ();
+	}
+ }
+ </pre>
+ *
+ * \defgroup xQueueSendFromISR xQueueSendFromISR
+ * \ingroup QueueManagement
+ */
+#define xQueueSendFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) xQueueGenericSendFromISR( ( xQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueSEND_TO_BACK )
+
+/**
+ * queue. h
+ * <pre>
+ BaseType_t xQueueGenericSendFromISR(
+										   QueueHandle_t		xQueue,
+										   const	void	*pvItemToQueue,
+										   BaseType_t	*pxHigherPriorityTaskWoken,
+										   BaseType_t	xCopyPosition
+									   );
+ </pre>
+ *
+ * It is preferred that the macros xQueueSendFromISR(),
+ * xQueueSendToFrontFromISR() and xQueueSendToBackFromISR() be used in place
+ * of calling this function directly.  xQueueGiveFromISR() is an
+ * equivalent for use by semaphores that don't actually copy any data.
+ *
+ * Post an item on a queue.  It is safe to use this function from within an
+ * interrupt service routine.
+ *
+ * Items are queued by copy not reference so it is preferable to only
+ * queue small items, especially when called from an ISR.  In most cases
+ * it would be preferable to store a pointer to the item being queued.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param pxHigherPriorityTaskWoken xQueueGenericSendFromISR() will set
+ * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task
+ * to unblock, and the unblocked task has a priority higher than the currently
+ * running task.  If xQueueGenericSendFromISR() sets this value to pdTRUE then
+ * a context switch should be requested before the interrupt is exited.
+ *
+ * @param xCopyPosition Can take the value queueSEND_TO_BACK to place the
+ * item at the back of the queue, or queueSEND_TO_FRONT to place the item
+ * at the front of the queue (for high priority messages).
+ *
+ * @return pdTRUE if the data was successfully sent to the queue, otherwise
+ * errQUEUE_FULL.
+ *
+ * Example usage for buffered IO (where the ISR can obtain more than one value
+ * per call):
+   <pre>
+ void vBufferISR( void )
+ {
+ char cIn;
+ BaseType_t xHigherPriorityTaskWokenByPost;
+
+	// We have not woken a task at the start of the ISR.
+	xHigherPriorityTaskWokenByPost = pdFALSE;
+
+	// Loop until the buffer is empty.
+	do
+	{
+		// Obtain a byte from the buffer.
+		cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );
+
+		// Post each byte.
+		xQueueGenericSendFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWokenByPost, queueSEND_TO_BACK );
+
+	} while( portINPUT_BYTE( BUFFER_COUNT ) );
+
+	// Now the buffer is empty we can switch context if necessary.  Note that the
+	// name of the yield function required is port specific.
+	if( xHigherPriorityTaskWokenByPost )
+	{
+		portYIELD_FROM_ISR();
+	}
+ }
+ </pre>
+ *
+ * \defgroup xQueueSendFromISR xQueueSendFromISR
+ * \ingroup QueueManagement
+ */
+BaseType_t xQueueGenericSendFromISR( QueueHandle_t xQueue, const void * const pvItemToQueue, BaseType_t * const pxHigherPriorityTaskWoken, const BaseType_t xCopyPosition ) PRIVILEGED_FUNCTION;
+BaseType_t xQueueGiveFromISR( QueueHandle_t xQueue, BaseType_t * const pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+
+/**
+ * queue. h
+ * <pre>
+ BaseType_t xQueueReceiveFromISR(
+									   QueueHandle_t	xQueue,
+									   void	*pvBuffer,
+									   BaseType_t *pxTaskWoken
+								   );
+ * </pre>
+ *
+ * Receive an item from a queue.  It is safe to use this function from within an
+ * interrupt service routine.
+ *
+ * @param xQueue The handle to the queue from which the item is to be
+ * received.
+ *
+ * @param pvBuffer Pointer to the buffer into which the received item will
+ * be copied.
+ *
+ * @param pxTaskWoken A task may be blocked waiting for space to become
+ * available on the queue.  If xQueueReceiveFromISR causes such a task to
+ * unblock *pxTaskWoken will get set to pdTRUE, otherwise *pxTaskWoken will
+ * remain unchanged.
+ *
+ * @return pdTRUE if an item was successfully received from the queue,
+ * otherwise pdFALSE.
+ *
+ * Example usage:
+   <pre>
+
+ QueueHandle_t xQueue;
+
+ // Function to create a queue and post some values.
+ void vAFunction( void *pvParameters )
+ {
+ char cValueToPost;
+ const TickType_t xTicksToWait = ( TickType_t )0xff;
+
+	// Create a queue capable of containing 10 characters.
+	xQueue = xQueueCreate( 10, sizeof( char ) );
+	if( xQueue == 0 )
+	{
+		// Failed to create the queue.
+	}
+
+	// ...
+
+	// Post some characters that will be used within an ISR.  If the queue
+	// is full then this task will block for xTicksToWait ticks.
+	cValueToPost = 'a';
+	xQueueSend( xQueue, ( void * ) &cValueToPost, xTicksToWait );
+	cValueToPost = 'b';
+	xQueueSend( xQueue, ( void * ) &cValueToPost, xTicksToWait );
+
+	// ... keep posting characters ... this task may block when the queue
+	// becomes full.
+
+	cValueToPost = 'c';
+	xQueueSend( xQueue, ( void * ) &cValueToPost, xTicksToWait );
+ }
+
+ // ISR that outputs all the characters received on the queue.
+ void vISR_Routine( void )
+ {
+ BaseType_t xTaskWokenByReceive = pdFALSE;
+ char cRxedChar;
+
+	while( xQueueReceiveFromISR( xQueue, ( void * ) &cRxedChar, &xTaskWokenByReceive) )
+	{
+		// A character was received.  Output the character now.
+		vOutputCharacter( cRxedChar );
+
+		// If removing the character from the queue woke the task that was
+		// posting onto the queue cTaskWokenByReceive will have been set to
+		// pdTRUE.  No matter how many times this loop iterates only one
+		// task will be woken.
+	}
+
+	if( cTaskWokenByPost != ( char ) pdFALSE;
+	{
+		taskYIELD ();
+	}
+ }
+ </pre>
+ * \defgroup xQueueReceiveFromISR xQueueReceiveFromISR
+ * \ingroup QueueManagement
+ */
+BaseType_t xQueueReceiveFromISR( QueueHandle_t xQueue, void * const pvBuffer, BaseType_t * const pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+
+/*
+ * Utilities to query queues that are safe to use from an ISR.  These utilities
+ * should be used only from witin an ISR, or within a critical section.
+ */
+BaseType_t xQueueIsQueueEmptyFromISR( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+UBaseType_t uxQueueMessagesWaitingFromISR( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+
+/*
+ * The functions defined above are for passing data to and from tasks.  The
+ * functions below are the equivalents for passing data to and from
+ * co-routines.
+ *
+ * These functions are called from the co-routine macro implementation and
+ * should not be called directly from application code.  Instead use the macro
+ * wrappers defined within croutine.h.
+ */
+BaseType_t xQueueCRSendFromISR( QueueHandle_t xQueue, const void *pvItemToQueue, BaseType_t xCoRoutinePreviouslyWoken );
+BaseType_t xQueueCRReceiveFromISR( QueueHandle_t xQueue, void *pvBuffer, BaseType_t *pxTaskWoken );
+BaseType_t xQueueCRSend( QueueHandle_t xQueue, const void *pvItemToQueue, TickType_t xTicksToWait );
+BaseType_t xQueueCRReceive( QueueHandle_t xQueue, void *pvBuffer, TickType_t xTicksToWait );
+
+/*
+ * For internal use only.  Use xSemaphoreCreateMutex(),
+ * xSemaphoreCreateCounting() or xSemaphoreGetMutexHolder() instead of calling
+ * these functions directly.
+ */
+QueueHandle_t xQueueCreateMutex( const uint8_t ucQueueType ) PRIVILEGED_FUNCTION;
+QueueHandle_t xQueueCreateMutexStatic( const uint8_t ucQueueType, StaticQueue_t *pxStaticQueue ) PRIVILEGED_FUNCTION;
+QueueHandle_t xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount ) PRIVILEGED_FUNCTION;
+QueueHandle_t xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount, StaticQueue_t *pxStaticQueue ) PRIVILEGED_FUNCTION;
+BaseType_t xQueueSemaphoreTake( QueueHandle_t xQueue, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+TaskHandle_t xQueueGetMutexHolder( QueueHandle_t xSemaphore ) PRIVILEGED_FUNCTION;
+TaskHandle_t xQueueGetMutexHolderFromISR( QueueHandle_t xSemaphore ) PRIVILEGED_FUNCTION;
+
+/*
+ * For internal use only.  Use xSemaphoreTakeMutexRecursive() or
+ * xSemaphoreGiveMutexRecursive() instead of calling these functions directly.
+ */
+BaseType_t xQueueTakeMutexRecursive( QueueHandle_t xMutex, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+BaseType_t xQueueGiveMutexRecursive( QueueHandle_t xMutex ) PRIVILEGED_FUNCTION;
+
+/*
+ * Reset a queue back to its original empty state.  The return value is now
+ * obsolete and is always set to pdPASS.
+ */
+#define xQueueReset( xQueue ) xQueueGenericReset( xQueue, pdFALSE )
+
+/*
+ * The registry is provided as a means for kernel aware debuggers to
+ * locate queues, semaphores and mutexes.  Call vQueueAddToRegistry() add
+ * a queue, semaphore or mutex handle to the registry if you want the handle
+ * to be available to a kernel aware debugger.  If you are not using a kernel
+ * aware debugger then this function can be ignored.
+ *
+ * configQUEUE_REGISTRY_SIZE defines the maximum number of handles the
+ * registry can hold.  configQUEUE_REGISTRY_SIZE must be greater than 0
+ * within FreeRTOSConfig.h for the registry to be available.  Its value
+ * does not effect the number of queues, semaphores and mutexes that can be
+ * created - just the number that the registry can hold.
+ *
+ * @param xQueue The handle of the queue being added to the registry.  This
+ * is the handle returned by a call to xQueueCreate().  Semaphore and mutex
+ * handles can also be passed in here.
+ *
+ * @param pcName The name to be associated with the handle.  This is the
+ * name that the kernel aware debugger will display.  The queue registry only
+ * stores a pointer to the string - so the string must be persistent (global or
+ * preferably in ROM/Flash), not on the stack.
+ */
+#if( configQUEUE_REGISTRY_SIZE > 0 )
+	void vQueueAddToRegistry( QueueHandle_t xQueue, const char *pcQueueName ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+#endif
+
+/*
+ * The registry is provided as a means for kernel aware debuggers to
+ * locate queues, semaphores and mutexes.  Call vQueueAddToRegistry() add
+ * a queue, semaphore or mutex handle to the registry if you want the handle
+ * to be available to a kernel aware debugger, and vQueueUnregisterQueue() to
+ * remove the queue, semaphore or mutex from the register.  If you are not using
+ * a kernel aware debugger then this function can be ignored.
+ *
+ * @param xQueue The handle of the queue being removed from the registry.
+ */
+#if( configQUEUE_REGISTRY_SIZE > 0 )
+	void vQueueUnregisterQueue( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+#endif
+
+/*
+ * The queue registry is provided as a means for kernel aware debuggers to
+ * locate queues, semaphores and mutexes.  Call pcQueueGetName() to look
+ * up and return the name of a queue in the queue registry from the queue's
+ * handle.
+ *
+ * @param xQueue The handle of the queue the name of which will be returned.
+ * @return If the queue is in the registry then a pointer to the name of the
+ * queue is returned.  If the queue is not in the registry then NULL is
+ * returned.
+ */
+#if( configQUEUE_REGISTRY_SIZE > 0 )
+	const char *pcQueueGetName( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+#endif
+
+/*
+ * Generic version of the function used to creaet a queue using dynamic memory
+ * allocation.  This is called by other functions and macros that create other
+ * RTOS objects that use the queue structure as their base.
+ */
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+	QueueHandle_t xQueueGenericCreate( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, const uint8_t ucQueueType ) PRIVILEGED_FUNCTION;
+#endif
+
+/*
+ * Generic version of the function used to creaet a queue using dynamic memory
+ * allocation.  This is called by other functions and macros that create other
+ * RTOS objects that use the queue structure as their base.
+ */
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+	QueueHandle_t xQueueGenericCreateStatic( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, StaticQueue_t *pxStaticQueue, const uint8_t ucQueueType ) PRIVILEGED_FUNCTION;
+#endif
+
+/*
+ * Queue sets provide a mechanism to allow a task to block (pend) on a read
+ * operation from multiple queues or semaphores simultaneously.
+ *
+ * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this
+ * function.
+ *
+ * A queue set must be explicitly created using a call to xQueueCreateSet()
+ * before it can be used.  Once created, standard FreeRTOS queues and semaphores
+ * can be added to the set using calls to xQueueAddToSet().
+ * xQueueSelectFromSet() is then used to determine which, if any, of the queues
+ * or semaphores contained in the set is in a state where a queue read or
+ * semaphore take operation would be successful.
+ *
+ * Note 1:  See the documentation on http://wwwFreeRTOS.org/RTOS-queue-sets.html
+ * for reasons why queue sets are very rarely needed in practice as there are
+ * simpler methods of blocking on multiple objects.
+ *
+ * Note 2:  Blocking on a queue set that contains a mutex will not cause the
+ * mutex holder to inherit the priority of the blocked task.
+ *
+ * Note 3:  An additional 4 bytes of RAM is required for each space in a every
+ * queue added to a queue set.  Therefore counting semaphores that have a high
+ * maximum count value should not be added to a queue set.
+ *
+ * Note 4:  A receive (in the case of a queue) or take (in the case of a
+ * semaphore) operation must not be performed on a member of a queue set unless
+ * a call to xQueueSelectFromSet() has first returned a handle to that set member.
+ *
+ * @param uxEventQueueLength Queue sets store events that occur on
+ * the queues and semaphores contained in the set.  uxEventQueueLength specifies
+ * the maximum number of events that can be queued at once.  To be absolutely
+ * certain that events are not lost uxEventQueueLength should be set to the
+ * total sum of the length of the queues added to the set, where binary
+ * semaphores and mutexes have a length of 1, and counting semaphores have a
+ * length set by their maximum count value.  Examples:
+ *  + If a queue set is to hold a queue of length 5, another queue of length 12,
+ *    and a binary semaphore, then uxEventQueueLength should be set to
+ *    (5 + 12 + 1), or 18.
+ *  + If a queue set is to hold three binary semaphores then uxEventQueueLength
+ *    should be set to (1 + 1 + 1 ), or 3.
+ *  + If a queue set is to hold a counting semaphore that has a maximum count of
+ *    5, and a counting semaphore that has a maximum count of 3, then
+ *    uxEventQueueLength should be set to (5 + 3), or 8.
+ *
+ * @return If the queue set is created successfully then a handle to the created
+ * queue set is returned.  Otherwise NULL is returned.
+ */
+QueueSetHandle_t xQueueCreateSet( const UBaseType_t uxEventQueueLength ) PRIVILEGED_FUNCTION;
+
+/*
+ * Adds a queue or semaphore to a queue set that was previously created by a
+ * call to xQueueCreateSet().
+ *
+ * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this
+ * function.
+ *
+ * Note 1:  A receive (in the case of a queue) or take (in the case of a
+ * semaphore) operation must not be performed on a member of a queue set unless
+ * a call to xQueueSelectFromSet() has first returned a handle to that set member.
+ *
+ * @param xQueueOrSemaphore The handle of the queue or semaphore being added to
+ * the queue set (cast to an QueueSetMemberHandle_t type).
+ *
+ * @param xQueueSet The handle of the queue set to which the queue or semaphore
+ * is being added.
+ *
+ * @return If the queue or semaphore was successfully added to the queue set
+ * then pdPASS is returned.  If the queue could not be successfully added to the
+ * queue set because it is already a member of a different queue set then pdFAIL
+ * is returned.
+ */
+BaseType_t xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet ) PRIVILEGED_FUNCTION;
+
+/*
+ * Removes a queue or semaphore from a queue set.  A queue or semaphore can only
+ * be removed from a set if the queue or semaphore is empty.
+ *
+ * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this
+ * function.
+ *
+ * @param xQueueOrSemaphore The handle of the queue or semaphore being removed
+ * from the queue set (cast to an QueueSetMemberHandle_t type).
+ *
+ * @param xQueueSet The handle of the queue set in which the queue or semaphore
+ * is included.
+ *
+ * @return If the queue or semaphore was successfully removed from the queue set
+ * then pdPASS is returned.  If the queue was not in the queue set, or the
+ * queue (or semaphore) was not empty, then pdFAIL is returned.
+ */
+BaseType_t xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet ) PRIVILEGED_FUNCTION;
+
+/*
+ * xQueueSelectFromSet() selects from the members of a queue set a queue or
+ * semaphore that either contains data (in the case of a queue) or is available
+ * to take (in the case of a semaphore).  xQueueSelectFromSet() effectively
+ * allows a task to block (pend) on a read operation on all the queues and
+ * semaphores in a queue set simultaneously.
+ *
+ * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this
+ * function.
+ *
+ * Note 1:  See the documentation on http://wwwFreeRTOS.org/RTOS-queue-sets.html
+ * for reasons why queue sets are very rarely needed in practice as there are
+ * simpler methods of blocking on multiple objects.
+ *
+ * Note 2:  Blocking on a queue set that contains a mutex will not cause the
+ * mutex holder to inherit the priority of the blocked task.
+ *
+ * Note 3:  A receive (in the case of a queue) or take (in the case of a
+ * semaphore) operation must not be performed on a member of a queue set unless
+ * a call to xQueueSelectFromSet() has first returned a handle to that set member.
+ *
+ * @param xQueueSet The queue set on which the task will (potentially) block.
+ *
+ * @param xTicksToWait The maximum time, in ticks, that the calling task will
+ * remain in the Blocked state (with other tasks executing) to wait for a member
+ * of the queue set to be ready for a successful queue read or semaphore take
+ * operation.
+ *
+ * @return xQueueSelectFromSet() will return the handle of a queue (cast to
+ * a QueueSetMemberHandle_t type) contained in the queue set that contains data,
+ * or the handle of a semaphore (cast to a QueueSetMemberHandle_t type) contained
+ * in the queue set that is available, or NULL if no such queue or semaphore
+ * exists before before the specified block time expires.
+ */
+QueueSetMemberHandle_t xQueueSelectFromSet( QueueSetHandle_t xQueueSet, const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+/*
+ * A version of xQueueSelectFromSet() that can be used from an ISR.
+ */
+QueueSetMemberHandle_t xQueueSelectFromSetFromISR( QueueSetHandle_t xQueueSet ) PRIVILEGED_FUNCTION;
+
+/* Not public API functions. */
+void vQueueWaitForMessageRestricted( QueueHandle_t xQueue, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely ) PRIVILEGED_FUNCTION;
+BaseType_t xQueueGenericReset( QueueHandle_t xQueue, BaseType_t xNewQueue ) PRIVILEGED_FUNCTION;
+void vQueueSetQueueNumber( QueueHandle_t xQueue, UBaseType_t uxQueueNumber ) PRIVILEGED_FUNCTION;
+UBaseType_t uxQueueGetQueueNumber( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+uint8_t ucQueueGetQueueType( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* QUEUE_H */
+
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h b/Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h
new file mode 100644
index 0000000..787c791
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h
@@ -0,0 +1,1140 @@
+/*
+ * FreeRTOS Kernel V10.3.1
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef SEMAPHORE_H
+#define SEMAPHORE_H
+
+#ifndef INC_FREERTOS_H
+	#error "include FreeRTOS.h" must appear in source files before "include semphr.h"
+#endif
+
+#include "queue.h"
+
+typedef QueueHandle_t SemaphoreHandle_t;
+
+#define semBINARY_SEMAPHORE_QUEUE_LENGTH	( ( uint8_t ) 1U )
+#define semSEMAPHORE_QUEUE_ITEM_LENGTH		( ( uint8_t ) 0U )
+#define semGIVE_BLOCK_TIME					( ( TickType_t ) 0U )
+
+
+/**
+ * semphr. h
+ * <pre>vSemaphoreCreateBinary( SemaphoreHandle_t xSemaphore )</pre>
+ *
+ * In many usage scenarios it is faster and more memory efficient to use a
+ * direct to task notification in place of a binary semaphore!
+ * http://www.freertos.org/RTOS-task-notifications.html
+ *
+ * This old vSemaphoreCreateBinary() macro is now deprecated in favour of the
+ * xSemaphoreCreateBinary() function.  Note that binary semaphores created using
+ * the vSemaphoreCreateBinary() macro are created in a state such that the
+ * first call to 'take' the semaphore would pass, whereas binary semaphores
+ * created using xSemaphoreCreateBinary() are created in a state such that the
+ * the semaphore must first be 'given' before it can be 'taken'.
+ *
+ * <i>Macro</i> that implements a semaphore by using the existing queue mechanism.
+ * The queue length is 1 as this is a binary semaphore.  The data size is 0
+ * as we don't want to actually store any data - we just want to know if the
+ * queue is empty or full.
+ *
+ * This type of semaphore can be used for pure synchronisation between tasks or
+ * between an interrupt and a task.  The semaphore need not be given back once
+ * obtained, so one task/interrupt can continuously 'give' the semaphore while
+ * another continuously 'takes' the semaphore.  For this reason this type of
+ * semaphore does not use a priority inheritance mechanism.  For an alternative
+ * that does use priority inheritance see xSemaphoreCreateMutex().
+ *
+ * @param xSemaphore Handle to the created semaphore.  Should be of type SemaphoreHandle_t.
+ *
+ * Example usage:
+ <pre>
+ SemaphoreHandle_t xSemaphore = NULL;
+
+ void vATask( void * pvParameters )
+ {
+    // Semaphore cannot be used before a call to vSemaphoreCreateBinary ().
+    // This is a macro so pass the variable in directly.
+    vSemaphoreCreateBinary( xSemaphore );
+
+    if( xSemaphore != NULL )
+    {
+        // The semaphore was created successfully.
+        // The semaphore can now be used.
+    }
+ }
+ </pre>
+ * \defgroup vSemaphoreCreateBinary vSemaphoreCreateBinary
+ * \ingroup Semaphores
+ */
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+	#define vSemaphoreCreateBinary( xSemaphore )																							\
+		{																																	\
+			( xSemaphore ) = xQueueGenericCreate( ( UBaseType_t ) 1, semSEMAPHORE_QUEUE_ITEM_LENGTH, queueQUEUE_TYPE_BINARY_SEMAPHORE );	\
+			if( ( xSemaphore ) != NULL )																									\
+			{																																\
+				( void ) xSemaphoreGive( ( xSemaphore ) );																					\
+			}																																\
+		}
+#endif
+
+/**
+ * semphr. h
+ * <pre>SemaphoreHandle_t xSemaphoreCreateBinary( void )</pre>
+ *
+ * Creates a new binary semaphore instance, and returns a handle by which the
+ * new semaphore can be referenced.
+ *
+ * In many usage scenarios it is faster and more memory efficient to use a
+ * direct to task notification in place of a binary semaphore!
+ * http://www.freertos.org/RTOS-task-notifications.html
+ *
+ * Internally, within the FreeRTOS implementation, binary semaphores use a block
+ * of memory, in which the semaphore structure is stored.  If a binary semaphore
+ * is created using xSemaphoreCreateBinary() then the required memory is
+ * automatically dynamically allocated inside the xSemaphoreCreateBinary()
+ * function.  (see http://www.freertos.org/a00111.html).  If a binary semaphore
+ * is created using xSemaphoreCreateBinaryStatic() then the application writer
+ * must provide the memory.  xSemaphoreCreateBinaryStatic() therefore allows a
+ * binary semaphore to be created without using any dynamic memory allocation.
+ *
+ * The old vSemaphoreCreateBinary() macro is now deprecated in favour of this
+ * xSemaphoreCreateBinary() function.  Note that binary semaphores created using
+ * the vSemaphoreCreateBinary() macro are created in a state such that the
+ * first call to 'take' the semaphore would pass, whereas binary semaphores
+ * created using xSemaphoreCreateBinary() are created in a state such that the
+ * the semaphore must first be 'given' before it can be 'taken'.
+ *
+ * This type of semaphore can be used for pure synchronisation between tasks or
+ * between an interrupt and a task.  The semaphore need not be given back once
+ * obtained, so one task/interrupt can continuously 'give' the semaphore while
+ * another continuously 'takes' the semaphore.  For this reason this type of
+ * semaphore does not use a priority inheritance mechanism.  For an alternative
+ * that does use priority inheritance see xSemaphoreCreateMutex().
+ *
+ * @return Handle to the created semaphore, or NULL if the memory required to
+ * hold the semaphore's data structures could not be allocated.
+ *
+ * Example usage:
+ <pre>
+ SemaphoreHandle_t xSemaphore = NULL;
+
+ void vATask( void * pvParameters )
+ {
+    // Semaphore cannot be used before a call to xSemaphoreCreateBinary().
+    // This is a macro so pass the variable in directly.
+    xSemaphore = xSemaphoreCreateBinary();
+
+    if( xSemaphore != NULL )
+    {
+        // The semaphore was created successfully.
+        // The semaphore can now be used.
+    }
+ }
+ </pre>
+ * \defgroup xSemaphoreCreateBinary xSemaphoreCreateBinary
+ * \ingroup Semaphores
+ */
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+	#define xSemaphoreCreateBinary() xQueueGenericCreate( ( UBaseType_t ) 1, semSEMAPHORE_QUEUE_ITEM_LENGTH, queueQUEUE_TYPE_BINARY_SEMAPHORE )
+#endif
+
+/**
+ * semphr. h
+ * <pre>SemaphoreHandle_t xSemaphoreCreateBinaryStatic( StaticSemaphore_t *pxSemaphoreBuffer )</pre>
+ *
+ * Creates a new binary semaphore instance, and returns a handle by which the
+ * new semaphore can be referenced.
+ *
+ * NOTE: In many usage scenarios it is faster and more memory efficient to use a
+ * direct to task notification in place of a binary semaphore!
+ * http://www.freertos.org/RTOS-task-notifications.html
+ *
+ * Internally, within the FreeRTOS implementation, binary semaphores use a block
+ * of memory, in which the semaphore structure is stored.  If a binary semaphore
+ * is created using xSemaphoreCreateBinary() then the required memory is
+ * automatically dynamically allocated inside the xSemaphoreCreateBinary()
+ * function.  (see http://www.freertos.org/a00111.html).  If a binary semaphore
+ * is created using xSemaphoreCreateBinaryStatic() then the application writer
+ * must provide the memory.  xSemaphoreCreateBinaryStatic() therefore allows a
+ * binary semaphore to be created without using any dynamic memory allocation.
+ *
+ * This type of semaphore can be used for pure synchronisation between tasks or
+ * between an interrupt and a task.  The semaphore need not be given back once
+ * obtained, so one task/interrupt can continuously 'give' the semaphore while
+ * another continuously 'takes' the semaphore.  For this reason this type of
+ * semaphore does not use a priority inheritance mechanism.  For an alternative
+ * that does use priority inheritance see xSemaphoreCreateMutex().
+ *
+ * @param pxSemaphoreBuffer Must point to a variable of type StaticSemaphore_t,
+ * which will then be used to hold the semaphore's data structure, removing the
+ * need for the memory to be allocated dynamically.
+ *
+ * @return If the semaphore is created then a handle to the created semaphore is
+ * returned.  If pxSemaphoreBuffer is NULL then NULL is returned.
+ *
+ * Example usage:
+ <pre>
+ SemaphoreHandle_t xSemaphore = NULL;
+ StaticSemaphore_t xSemaphoreBuffer;
+
+ void vATask( void * pvParameters )
+ {
+    // Semaphore cannot be used before a call to xSemaphoreCreateBinary().
+    // The semaphore's data structures will be placed in the xSemaphoreBuffer
+    // variable, the address of which is passed into the function.  The
+    // function's parameter is not NULL, so the function will not attempt any
+    // dynamic memory allocation, and therefore the function will not return
+    // return NULL.
+    xSemaphore = xSemaphoreCreateBinary( &xSemaphoreBuffer );
+
+    // Rest of task code goes here.
+ }
+ </pre>
+ * \defgroup xSemaphoreCreateBinaryStatic xSemaphoreCreateBinaryStatic
+ * \ingroup Semaphores
+ */
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+	#define xSemaphoreCreateBinaryStatic( pxStaticSemaphore ) xQueueGenericCreateStatic( ( UBaseType_t ) 1, semSEMAPHORE_QUEUE_ITEM_LENGTH, NULL, pxStaticSemaphore, queueQUEUE_TYPE_BINARY_SEMAPHORE )
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+/**
+ * semphr. h
+ * <pre>xSemaphoreTake(
+ *                   SemaphoreHandle_t xSemaphore,
+ *                   TickType_t xBlockTime
+ *               )</pre>
+ *
+ * <i>Macro</i> to obtain a semaphore.  The semaphore must have previously been
+ * created with a call to xSemaphoreCreateBinary(), xSemaphoreCreateMutex() or
+ * xSemaphoreCreateCounting().
+ *
+ * @param xSemaphore A handle to the semaphore being taken - obtained when
+ * the semaphore was created.
+ *
+ * @param xBlockTime The time in ticks to wait for the semaphore to become
+ * available.  The macro portTICK_PERIOD_MS can be used to convert this to a
+ * real time.  A block time of zero can be used to poll the semaphore.  A block
+ * time of portMAX_DELAY can be used to block indefinitely (provided
+ * INCLUDE_vTaskSuspend is set to 1 in FreeRTOSConfig.h).
+ *
+ * @return pdTRUE if the semaphore was obtained.  pdFALSE
+ * if xBlockTime expired without the semaphore becoming available.
+ *
+ * Example usage:
+ <pre>
+ SemaphoreHandle_t xSemaphore = NULL;
+
+ // A task that creates a semaphore.
+ void vATask( void * pvParameters )
+ {
+    // Create the semaphore to guard a shared resource.
+    xSemaphore = xSemaphoreCreateBinary();
+ }
+
+ // A task that uses the semaphore.
+ void vAnotherTask( void * pvParameters )
+ {
+    // ... Do other things.
+
+    if( xSemaphore != NULL )
+    {
+        // See if we can obtain the semaphore.  If the semaphore is not available
+        // wait 10 ticks to see if it becomes free.
+        if( xSemaphoreTake( xSemaphore, ( TickType_t ) 10 ) == pdTRUE )
+        {
+            // We were able to obtain the semaphore and can now access the
+            // shared resource.
+
+            // ...
+
+            // We have finished accessing the shared resource.  Release the
+            // semaphore.
+            xSemaphoreGive( xSemaphore );
+        }
+        else
+        {
+            // We could not obtain the semaphore and can therefore not access
+            // the shared resource safely.
+        }
+    }
+ }
+ </pre>
+ * \defgroup xSemaphoreTake xSemaphoreTake
+ * \ingroup Semaphores
+ */
+#define xSemaphoreTake( xSemaphore, xBlockTime )		xQueueSemaphoreTake( ( xSemaphore ), ( xBlockTime ) )
+
+/**
+ * semphr. h
+ * xSemaphoreTakeRecursive(
+ *                          SemaphoreHandle_t xMutex,
+ *                          TickType_t xBlockTime
+ *                        )
+ *
+ * <i>Macro</i> to recursively obtain, or 'take', a mutex type semaphore.
+ * The mutex must have previously been created using a call to
+ * xSemaphoreCreateRecursiveMutex();
+ *
+ * configUSE_RECURSIVE_MUTEXES must be set to 1 in FreeRTOSConfig.h for this
+ * macro to be available.
+ *
+ * This macro must not be used on mutexes created using xSemaphoreCreateMutex().
+ *
+ * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex
+ * doesn't become available again until the owner has called
+ * xSemaphoreGiveRecursive() for each successful 'take' request.  For example,
+ * if a task successfully 'takes' the same mutex 5 times then the mutex will
+ * not be available to any other task until it has also  'given' the mutex back
+ * exactly five times.
+ *
+ * @param xMutex A handle to the mutex being obtained.  This is the
+ * handle returned by xSemaphoreCreateRecursiveMutex();
+ *
+ * @param xBlockTime The time in ticks to wait for the semaphore to become
+ * available.  The macro portTICK_PERIOD_MS can be used to convert this to a
+ * real time.  A block time of zero can be used to poll the semaphore.  If
+ * the task already owns the semaphore then xSemaphoreTakeRecursive() will
+ * return immediately no matter what the value of xBlockTime.
+ *
+ * @return pdTRUE if the semaphore was obtained.  pdFALSE if xBlockTime
+ * expired without the semaphore becoming available.
+ *
+ * Example usage:
+ <pre>
+ SemaphoreHandle_t xMutex = NULL;
+
+ // A task that creates a mutex.
+ void vATask( void * pvParameters )
+ {
+    // Create the mutex to guard a shared resource.
+    xMutex = xSemaphoreCreateRecursiveMutex();
+ }
+
+ // A task that uses the mutex.
+ void vAnotherTask( void * pvParameters )
+ {
+    // ... Do other things.
+
+    if( xMutex != NULL )
+    {
+        // See if we can obtain the mutex.  If the mutex is not available
+        // wait 10 ticks to see if it becomes free.
+        if( xSemaphoreTakeRecursive( xSemaphore, ( TickType_t ) 10 ) == pdTRUE )
+        {
+            // We were able to obtain the mutex and can now access the
+            // shared resource.
+
+            // ...
+            // For some reason due to the nature of the code further calls to
+            // xSemaphoreTakeRecursive() are made on the same mutex.  In real
+            // code these would not be just sequential calls as this would make
+            // no sense.  Instead the calls are likely to be buried inside
+            // a more complex call structure.
+            xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 );
+            xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 );
+
+            // The mutex has now been 'taken' three times, so will not be
+            // available to another task until it has also been given back
+            // three times.  Again it is unlikely that real code would have
+            // these calls sequentially, but instead buried in a more complex
+            // call structure.  This is just for illustrative purposes.
+            xSemaphoreGiveRecursive( xMutex );
+            xSemaphoreGiveRecursive( xMutex );
+            xSemaphoreGiveRecursive( xMutex );
+
+            // Now the mutex can be taken by other tasks.
+        }
+        else
+        {
+            // We could not obtain the mutex and can therefore not access
+            // the shared resource safely.
+        }
+    }
+ }
+ </pre>
+ * \defgroup xSemaphoreTakeRecursive xSemaphoreTakeRecursive
+ * \ingroup Semaphores
+ */
+#if( configUSE_RECURSIVE_MUTEXES == 1 )
+	#define xSemaphoreTakeRecursive( xMutex, xBlockTime )	xQueueTakeMutexRecursive( ( xMutex ), ( xBlockTime ) )
+#endif
+
+/**
+ * semphr. h
+ * <pre>xSemaphoreGive( SemaphoreHandle_t xSemaphore )</pre>
+ *
+ * <i>Macro</i> to release a semaphore.  The semaphore must have previously been
+ * created with a call to xSemaphoreCreateBinary(), xSemaphoreCreateMutex() or
+ * xSemaphoreCreateCounting(). and obtained using sSemaphoreTake().
+ *
+ * This macro must not be used from an ISR.  See xSemaphoreGiveFromISR () for
+ * an alternative which can be used from an ISR.
+ *
+ * This macro must also not be used on semaphores created using
+ * xSemaphoreCreateRecursiveMutex().
+ *
+ * @param xSemaphore A handle to the semaphore being released.  This is the
+ * handle returned when the semaphore was created.
+ *
+ * @return pdTRUE if the semaphore was released.  pdFALSE if an error occurred.
+ * Semaphores are implemented using queues.  An error can occur if there is
+ * no space on the queue to post a message - indicating that the
+ * semaphore was not first obtained correctly.
+ *
+ * Example usage:
+ <pre>
+ SemaphoreHandle_t xSemaphore = NULL;
+
+ void vATask( void * pvParameters )
+ {
+    // Create the semaphore to guard a shared resource.
+    xSemaphore = vSemaphoreCreateBinary();
+
+    if( xSemaphore != NULL )
+    {
+        if( xSemaphoreGive( xSemaphore ) != pdTRUE )
+        {
+            // We would expect this call to fail because we cannot give
+            // a semaphore without first "taking" it!
+        }
+
+        // Obtain the semaphore - don't block if the semaphore is not
+        // immediately available.
+        if( xSemaphoreTake( xSemaphore, ( TickType_t ) 0 ) )
+        {
+            // We now have the semaphore and can access the shared resource.
+
+            // ...
+
+            // We have finished accessing the shared resource so can free the
+            // semaphore.
+            if( xSemaphoreGive( xSemaphore ) != pdTRUE )
+            {
+                // We would not expect this call to fail because we must have
+                // obtained the semaphore to get here.
+            }
+        }
+    }
+ }
+ </pre>
+ * \defgroup xSemaphoreGive xSemaphoreGive
+ * \ingroup Semaphores
+ */
+#define xSemaphoreGive( xSemaphore )		xQueueGenericSend( ( QueueHandle_t ) ( xSemaphore ), NULL, semGIVE_BLOCK_TIME, queueSEND_TO_BACK )
+
+/**
+ * semphr. h
+ * <pre>xSemaphoreGiveRecursive( SemaphoreHandle_t xMutex )</pre>
+ *
+ * <i>Macro</i> to recursively release, or 'give', a mutex type semaphore.
+ * The mutex must have previously been created using a call to
+ * xSemaphoreCreateRecursiveMutex();
+ *
+ * configUSE_RECURSIVE_MUTEXES must be set to 1 in FreeRTOSConfig.h for this
+ * macro to be available.
+ *
+ * This macro must not be used on mutexes created using xSemaphoreCreateMutex().
+ *
+ * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex
+ * doesn't become available again until the owner has called
+ * xSemaphoreGiveRecursive() for each successful 'take' request.  For example,
+ * if a task successfully 'takes' the same mutex 5 times then the mutex will
+ * not be available to any other task until it has also  'given' the mutex back
+ * exactly five times.
+ *
+ * @param xMutex A handle to the mutex being released, or 'given'.  This is the
+ * handle returned by xSemaphoreCreateMutex();
+ *
+ * @return pdTRUE if the semaphore was given.
+ *
+ * Example usage:
+ <pre>
+ SemaphoreHandle_t xMutex = NULL;
+
+ // A task that creates a mutex.
+ void vATask( void * pvParameters )
+ {
+    // Create the mutex to guard a shared resource.
+    xMutex = xSemaphoreCreateRecursiveMutex();
+ }
+
+ // A task that uses the mutex.
+ void vAnotherTask( void * pvParameters )
+ {
+    // ... Do other things.
+
+    if( xMutex != NULL )
+    {
+        // See if we can obtain the mutex.  If the mutex is not available
+        // wait 10 ticks to see if it becomes free.
+        if( xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 ) == pdTRUE )
+        {
+            // We were able to obtain the mutex and can now access the
+            // shared resource.
+
+            // ...
+            // For some reason due to the nature of the code further calls to
+			// xSemaphoreTakeRecursive() are made on the same mutex.  In real
+			// code these would not be just sequential calls as this would make
+			// no sense.  Instead the calls are likely to be buried inside
+			// a more complex call structure.
+            xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 );
+            xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 );
+
+            // The mutex has now been 'taken' three times, so will not be
+			// available to another task until it has also been given back
+			// three times.  Again it is unlikely that real code would have
+			// these calls sequentially, it would be more likely that the calls
+			// to xSemaphoreGiveRecursive() would be called as a call stack
+			// unwound.  This is just for demonstrative purposes.
+            xSemaphoreGiveRecursive( xMutex );
+			xSemaphoreGiveRecursive( xMutex );
+			xSemaphoreGiveRecursive( xMutex );
+
+			// Now the mutex can be taken by other tasks.
+        }
+        else
+        {
+            // We could not obtain the mutex and can therefore not access
+            // the shared resource safely.
+        }
+    }
+ }
+ </pre>
+ * \defgroup xSemaphoreGiveRecursive xSemaphoreGiveRecursive
+ * \ingroup Semaphores
+ */
+#if( configUSE_RECURSIVE_MUTEXES == 1 )
+	#define xSemaphoreGiveRecursive( xMutex )	xQueueGiveMutexRecursive( ( xMutex ) )
+#endif
+
+/**
+ * semphr. h
+ * <pre>
+ xSemaphoreGiveFromISR(
+                          SemaphoreHandle_t xSemaphore,
+                          BaseType_t *pxHigherPriorityTaskWoken
+                      )</pre>
+ *
+ * <i>Macro</i> to  release a semaphore.  The semaphore must have previously been
+ * created with a call to xSemaphoreCreateBinary() or xSemaphoreCreateCounting().
+ *
+ * Mutex type semaphores (those created using a call to xSemaphoreCreateMutex())
+ * must not be used with this macro.
+ *
+ * This macro can be used from an ISR.
+ *
+ * @param xSemaphore A handle to the semaphore being released.  This is the
+ * handle returned when the semaphore was created.
+ *
+ * @param pxHigherPriorityTaskWoken xSemaphoreGiveFromISR() will set
+ * *pxHigherPriorityTaskWoken to pdTRUE if giving the semaphore caused a task
+ * to unblock, and the unblocked task has a priority higher than the currently
+ * running task.  If xSemaphoreGiveFromISR() sets this value to pdTRUE then
+ * a context switch should be requested before the interrupt is exited.
+ *
+ * @return pdTRUE if the semaphore was successfully given, otherwise errQUEUE_FULL.
+ *
+ * Example usage:
+ <pre>
+ \#define LONG_TIME 0xffff
+ \#define TICKS_TO_WAIT	10
+ SemaphoreHandle_t xSemaphore = NULL;
+
+ // Repetitive task.
+ void vATask( void * pvParameters )
+ {
+    for( ;; )
+    {
+        // We want this task to run every 10 ticks of a timer.  The semaphore
+        // was created before this task was started.
+
+        // Block waiting for the semaphore to become available.
+        if( xSemaphoreTake( xSemaphore, LONG_TIME ) == pdTRUE )
+        {
+            // It is time to execute.
+
+            // ...
+
+            // We have finished our task.  Return to the top of the loop where
+            // we will block on the semaphore until it is time to execute
+            // again.  Note when using the semaphore for synchronisation with an
+			// ISR in this manner there is no need to 'give' the semaphore back.
+        }
+    }
+ }
+
+ // Timer ISR
+ void vTimerISR( void * pvParameters )
+ {
+ static uint8_t ucLocalTickCount = 0;
+ static BaseType_t xHigherPriorityTaskWoken;
+
+    // A timer tick has occurred.
+
+    // ... Do other time functions.
+
+    // Is it time for vATask () to run?
+	xHigherPriorityTaskWoken = pdFALSE;
+    ucLocalTickCount++;
+    if( ucLocalTickCount >= TICKS_TO_WAIT )
+    {
+        // Unblock the task by releasing the semaphore.
+        xSemaphoreGiveFromISR( xSemaphore, &xHigherPriorityTaskWoken );
+
+        // Reset the count so we release the semaphore again in 10 ticks time.
+        ucLocalTickCount = 0;
+    }
+
+    if( xHigherPriorityTaskWoken != pdFALSE )
+    {
+        // We can force a context switch here.  Context switching from an
+        // ISR uses port specific syntax.  Check the demo task for your port
+        // to find the syntax required.
+    }
+ }
+ </pre>
+ * \defgroup xSemaphoreGiveFromISR xSemaphoreGiveFromISR
+ * \ingroup Semaphores
+ */
+#define xSemaphoreGiveFromISR( xSemaphore, pxHigherPriorityTaskWoken )	xQueueGiveFromISR( ( QueueHandle_t ) ( xSemaphore ), ( pxHigherPriorityTaskWoken ) )
+
+/**
+ * semphr. h
+ * <pre>
+ xSemaphoreTakeFromISR(
+                          SemaphoreHandle_t xSemaphore,
+                          BaseType_t *pxHigherPriorityTaskWoken
+                      )</pre>
+ *
+ * <i>Macro</i> to  take a semaphore from an ISR.  The semaphore must have
+ * previously been created with a call to xSemaphoreCreateBinary() or
+ * xSemaphoreCreateCounting().
+ *
+ * Mutex type semaphores (those created using a call to xSemaphoreCreateMutex())
+ * must not be used with this macro.
+ *
+ * This macro can be used from an ISR, however taking a semaphore from an ISR
+ * is not a common operation.  It is likely to only be useful when taking a
+ * counting semaphore when an interrupt is obtaining an object from a resource
+ * pool (when the semaphore count indicates the number of resources available).
+ *
+ * @param xSemaphore A handle to the semaphore being taken.  This is the
+ * handle returned when the semaphore was created.
+ *
+ * @param pxHigherPriorityTaskWoken xSemaphoreTakeFromISR() will set
+ * *pxHigherPriorityTaskWoken to pdTRUE if taking the semaphore caused a task
+ * to unblock, and the unblocked task has a priority higher than the currently
+ * running task.  If xSemaphoreTakeFromISR() sets this value to pdTRUE then
+ * a context switch should be requested before the interrupt is exited.
+ *
+ * @return pdTRUE if the semaphore was successfully taken, otherwise
+ * pdFALSE
+ */
+#define xSemaphoreTakeFromISR( xSemaphore, pxHigherPriorityTaskWoken )	xQueueReceiveFromISR( ( QueueHandle_t ) ( xSemaphore ), NULL, ( pxHigherPriorityTaskWoken ) )
+
+/**
+ * semphr. h
+ * <pre>SemaphoreHandle_t xSemaphoreCreateMutex( void )</pre>
+ *
+ * Creates a new mutex type semaphore instance, and returns a handle by which
+ * the new mutex can be referenced.
+ *
+ * Internally, within the FreeRTOS implementation, mutex semaphores use a block
+ * of memory, in which the mutex structure is stored.  If a mutex is created
+ * using xSemaphoreCreateMutex() then the required memory is automatically
+ * dynamically allocated inside the xSemaphoreCreateMutex() function.  (see
+ * http://www.freertos.org/a00111.html).  If a mutex is created using
+ * xSemaphoreCreateMutexStatic() then the application writer must provided the
+ * memory.  xSemaphoreCreateMutexStatic() therefore allows a mutex to be created
+ * without using any dynamic memory allocation.
+ *
+ * Mutexes created using this function can be accessed using the xSemaphoreTake()
+ * and xSemaphoreGive() macros.  The xSemaphoreTakeRecursive() and
+ * xSemaphoreGiveRecursive() macros must not be used.
+ *
+ * This type of semaphore uses a priority inheritance mechanism so a task
+ * 'taking' a semaphore MUST ALWAYS 'give' the semaphore back once the
+ * semaphore it is no longer required.
+ *
+ * Mutex type semaphores cannot be used from within interrupt service routines.
+ *
+ * See xSemaphoreCreateBinary() for an alternative implementation that can be
+ * used for pure synchronisation (where one task or interrupt always 'gives' the
+ * semaphore and another always 'takes' the semaphore) and from within interrupt
+ * service routines.
+ *
+ * @return If the mutex was successfully created then a handle to the created
+ * semaphore is returned.  If there was not enough heap to allocate the mutex
+ * data structures then NULL is returned.
+ *
+ * Example usage:
+ <pre>
+ SemaphoreHandle_t xSemaphore;
+
+ void vATask( void * pvParameters )
+ {
+    // Semaphore cannot be used before a call to xSemaphoreCreateMutex().
+    // This is a macro so pass the variable in directly.
+    xSemaphore = xSemaphoreCreateMutex();
+
+    if( xSemaphore != NULL )
+    {
+        // The semaphore was created successfully.
+        // The semaphore can now be used.
+    }
+ }
+ </pre>
+ * \defgroup xSemaphoreCreateMutex xSemaphoreCreateMutex
+ * \ingroup Semaphores
+ */
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+	#define xSemaphoreCreateMutex() xQueueCreateMutex( queueQUEUE_TYPE_MUTEX )
+#endif
+
+/**
+ * semphr. h
+ * <pre>SemaphoreHandle_t xSemaphoreCreateMutexStatic( StaticSemaphore_t *pxMutexBuffer )</pre>
+ *
+ * Creates a new mutex type semaphore instance, and returns a handle by which
+ * the new mutex can be referenced.
+ *
+ * Internally, within the FreeRTOS implementation, mutex semaphores use a block
+ * of memory, in which the mutex structure is stored.  If a mutex is created
+ * using xSemaphoreCreateMutex() then the required memory is automatically
+ * dynamically allocated inside the xSemaphoreCreateMutex() function.  (see
+ * http://www.freertos.org/a00111.html).  If a mutex is created using
+ * xSemaphoreCreateMutexStatic() then the application writer must provided the
+ * memory.  xSemaphoreCreateMutexStatic() therefore allows a mutex to be created
+ * without using any dynamic memory allocation.
+ *
+ * Mutexes created using this function can be accessed using the xSemaphoreTake()
+ * and xSemaphoreGive() macros.  The xSemaphoreTakeRecursive() and
+ * xSemaphoreGiveRecursive() macros must not be used.
+ *
+ * This type of semaphore uses a priority inheritance mechanism so a task
+ * 'taking' a semaphore MUST ALWAYS 'give' the semaphore back once the
+ * semaphore it is no longer required.
+ *
+ * Mutex type semaphores cannot be used from within interrupt service routines.
+ *
+ * See xSemaphoreCreateBinary() for an alternative implementation that can be
+ * used for pure synchronisation (where one task or interrupt always 'gives' the
+ * semaphore and another always 'takes' the semaphore) and from within interrupt
+ * service routines.
+ *
+ * @param pxMutexBuffer Must point to a variable of type StaticSemaphore_t,
+ * which will be used to hold the mutex's data structure, removing the need for
+ * the memory to be allocated dynamically.
+ *
+ * @return If the mutex was successfully created then a handle to the created
+ * mutex is returned.  If pxMutexBuffer was NULL then NULL is returned.
+ *
+ * Example usage:
+ <pre>
+ SemaphoreHandle_t xSemaphore;
+ StaticSemaphore_t xMutexBuffer;
+
+ void vATask( void * pvParameters )
+ {
+    // A mutex cannot be used before it has been created.  xMutexBuffer is
+    // into xSemaphoreCreateMutexStatic() so no dynamic memory allocation is
+    // attempted.
+    xSemaphore = xSemaphoreCreateMutexStatic( &xMutexBuffer );
+
+    // As no dynamic memory allocation was performed, xSemaphore cannot be NULL,
+    // so there is no need to check it.
+ }
+ </pre>
+ * \defgroup xSemaphoreCreateMutexStatic xSemaphoreCreateMutexStatic
+ * \ingroup Semaphores
+ */
+ #if( configSUPPORT_STATIC_ALLOCATION == 1 )
+	#define xSemaphoreCreateMutexStatic( pxMutexBuffer ) xQueueCreateMutexStatic( queueQUEUE_TYPE_MUTEX, ( pxMutexBuffer ) )
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+
+/**
+ * semphr. h
+ * <pre>SemaphoreHandle_t xSemaphoreCreateRecursiveMutex( void )</pre>
+ *
+ * Creates a new recursive mutex type semaphore instance, and returns a handle
+ * by which the new recursive mutex can be referenced.
+ *
+ * Internally, within the FreeRTOS implementation, recursive mutexs use a block
+ * of memory, in which the mutex structure is stored.  If a recursive mutex is
+ * created using xSemaphoreCreateRecursiveMutex() then the required memory is
+ * automatically dynamically allocated inside the
+ * xSemaphoreCreateRecursiveMutex() function.  (see
+ * http://www.freertos.org/a00111.html).  If a recursive mutex is created using
+ * xSemaphoreCreateRecursiveMutexStatic() then the application writer must
+ * provide the memory that will get used by the mutex.
+ * xSemaphoreCreateRecursiveMutexStatic() therefore allows a recursive mutex to
+ * be created without using any dynamic memory allocation.
+ *
+ * Mutexes created using this macro can be accessed using the
+ * xSemaphoreTakeRecursive() and xSemaphoreGiveRecursive() macros.  The
+ * xSemaphoreTake() and xSemaphoreGive() macros must not be used.
+ *
+ * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex
+ * doesn't become available again until the owner has called
+ * xSemaphoreGiveRecursive() for each successful 'take' request.  For example,
+ * if a task successfully 'takes' the same mutex 5 times then the mutex will
+ * not be available to any other task until it has also  'given' the mutex back
+ * exactly five times.
+ *
+ * This type of semaphore uses a priority inheritance mechanism so a task
+ * 'taking' a semaphore MUST ALWAYS 'give' the semaphore back once the
+ * semaphore it is no longer required.
+ *
+ * Mutex type semaphores cannot be used from within interrupt service routines.
+ *
+ * See xSemaphoreCreateBinary() for an alternative implementation that can be
+ * used for pure synchronisation (where one task or interrupt always 'gives' the
+ * semaphore and another always 'takes' the semaphore) and from within interrupt
+ * service routines.
+ *
+ * @return xSemaphore Handle to the created mutex semaphore.  Should be of type
+ * SemaphoreHandle_t.
+ *
+ * Example usage:
+ <pre>
+ SemaphoreHandle_t xSemaphore;
+
+ void vATask( void * pvParameters )
+ {
+    // Semaphore cannot be used before a call to xSemaphoreCreateMutex().
+    // This is a macro so pass the variable in directly.
+    xSemaphore = xSemaphoreCreateRecursiveMutex();
+
+    if( xSemaphore != NULL )
+    {
+        // The semaphore was created successfully.
+        // The semaphore can now be used.
+    }
+ }
+ </pre>
+ * \defgroup xSemaphoreCreateRecursiveMutex xSemaphoreCreateRecursiveMutex
+ * \ingroup Semaphores
+ */
+#if( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configUSE_RECURSIVE_MUTEXES == 1 ) )
+	#define xSemaphoreCreateRecursiveMutex() xQueueCreateMutex( queueQUEUE_TYPE_RECURSIVE_MUTEX )
+#endif
+
+/**
+ * semphr. h
+ * <pre>SemaphoreHandle_t xSemaphoreCreateRecursiveMutexStatic( StaticSemaphore_t *pxMutexBuffer )</pre>
+ *
+ * Creates a new recursive mutex type semaphore instance, and returns a handle
+ * by which the new recursive mutex can be referenced.
+ *
+ * Internally, within the FreeRTOS implementation, recursive mutexs use a block
+ * of memory, in which the mutex structure is stored.  If a recursive mutex is
+ * created using xSemaphoreCreateRecursiveMutex() then the required memory is
+ * automatically dynamically allocated inside the
+ * xSemaphoreCreateRecursiveMutex() function.  (see
+ * http://www.freertos.org/a00111.html).  If a recursive mutex is created using
+ * xSemaphoreCreateRecursiveMutexStatic() then the application writer must
+ * provide the memory that will get used by the mutex.
+ * xSemaphoreCreateRecursiveMutexStatic() therefore allows a recursive mutex to
+ * be created without using any dynamic memory allocation.
+ *
+ * Mutexes created using this macro can be accessed using the
+ * xSemaphoreTakeRecursive() and xSemaphoreGiveRecursive() macros.  The
+ * xSemaphoreTake() and xSemaphoreGive() macros must not be used.
+ *
+ * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex
+ * doesn't become available again until the owner has called
+ * xSemaphoreGiveRecursive() for each successful 'take' request.  For example,
+ * if a task successfully 'takes' the same mutex 5 times then the mutex will
+ * not be available to any other task until it has also  'given' the mutex back
+ * exactly five times.
+ *
+ * This type of semaphore uses a priority inheritance mechanism so a task
+ * 'taking' a semaphore MUST ALWAYS 'give' the semaphore back once the
+ * semaphore it is no longer required.
+ *
+ * Mutex type semaphores cannot be used from within interrupt service routines.
+ *
+ * See xSemaphoreCreateBinary() for an alternative implementation that can be
+ * used for pure synchronisation (where one task or interrupt always 'gives' the
+ * semaphore and another always 'takes' the semaphore) and from within interrupt
+ * service routines.
+ *
+ * @param pxMutexBuffer Must point to a variable of type StaticSemaphore_t,
+ * which will then be used to hold the recursive mutex's data structure,
+ * removing the need for the memory to be allocated dynamically.
+ *
+ * @return If the recursive mutex was successfully created then a handle to the
+ * created recursive mutex is returned.  If pxMutexBuffer was NULL then NULL is
+ * returned.
+ *
+ * Example usage:
+ <pre>
+ SemaphoreHandle_t xSemaphore;
+ StaticSemaphore_t xMutexBuffer;
+
+ void vATask( void * pvParameters )
+ {
+    // A recursive semaphore cannot be used before it is created.  Here a
+    // recursive mutex is created using xSemaphoreCreateRecursiveMutexStatic().
+    // The address of xMutexBuffer is passed into the function, and will hold
+    // the mutexes data structures - so no dynamic memory allocation will be
+    // attempted.
+    xSemaphore = xSemaphoreCreateRecursiveMutexStatic( &xMutexBuffer );
+
+    // As no dynamic memory allocation was performed, xSemaphore cannot be NULL,
+    // so there is no need to check it.
+ }
+ </pre>
+ * \defgroup xSemaphoreCreateRecursiveMutexStatic xSemaphoreCreateRecursiveMutexStatic
+ * \ingroup Semaphores
+ */
+#if( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configUSE_RECURSIVE_MUTEXES == 1 ) )
+	#define xSemaphoreCreateRecursiveMutexStatic( pxStaticSemaphore ) xQueueCreateMutexStatic( queueQUEUE_TYPE_RECURSIVE_MUTEX, pxStaticSemaphore )
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+/**
+ * semphr. h
+ * <pre>SemaphoreHandle_t xSemaphoreCreateCounting( UBaseType_t uxMaxCount, UBaseType_t uxInitialCount )</pre>
+ *
+ * Creates a new counting semaphore instance, and returns a handle by which the
+ * new counting semaphore can be referenced.
+ *
+ * In many usage scenarios it is faster and more memory efficient to use a
+ * direct to task notification in place of a counting semaphore!
+ * http://www.freertos.org/RTOS-task-notifications.html
+ *
+ * Internally, within the FreeRTOS implementation, counting semaphores use a
+ * block of memory, in which the counting semaphore structure is stored.  If a
+ * counting semaphore is created using xSemaphoreCreateCounting() then the
+ * required memory is automatically dynamically allocated inside the
+ * xSemaphoreCreateCounting() function.  (see
+ * http://www.freertos.org/a00111.html).  If a counting semaphore is created
+ * using xSemaphoreCreateCountingStatic() then the application writer can
+ * instead optionally provide the memory that will get used by the counting
+ * semaphore.  xSemaphoreCreateCountingStatic() therefore allows a counting
+ * semaphore to be created without using any dynamic memory allocation.
+ *
+ * Counting semaphores are typically used for two things:
+ *
+ * 1) Counting events.
+ *
+ *    In this usage scenario an event handler will 'give' a semaphore each time
+ *    an event occurs (incrementing the semaphore count value), and a handler
+ *    task will 'take' a semaphore each time it processes an event
+ *    (decrementing the semaphore count value).  The count value is therefore
+ *    the difference between the number of events that have occurred and the
+ *    number that have been processed.  In this case it is desirable for the
+ *    initial count value to be zero.
+ *
+ * 2) Resource management.
+ *
+ *    In this usage scenario the count value indicates the number of resources
+ *    available.  To obtain control of a resource a task must first obtain a
+ *    semaphore - decrementing the semaphore count value.  When the count value
+ *    reaches zero there are no free resources.  When a task finishes with the
+ *    resource it 'gives' the semaphore back - incrementing the semaphore count
+ *    value.  In this case it is desirable for the initial count value to be
+ *    equal to the maximum count value, indicating that all resources are free.
+ *
+ * @param uxMaxCount The maximum count value that can be reached.  When the
+ *        semaphore reaches this value it can no longer be 'given'.
+ *
+ * @param uxInitialCount The count value assigned to the semaphore when it is
+ *        created.
+ *
+ * @return Handle to the created semaphore.  Null if the semaphore could not be
+ *         created.
+ *
+ * Example usage:
+ <pre>
+ SemaphoreHandle_t xSemaphore;
+
+ void vATask( void * pvParameters )
+ {
+ SemaphoreHandle_t xSemaphore = NULL;
+
+    // Semaphore cannot be used before a call to xSemaphoreCreateCounting().
+    // The max value to which the semaphore can count should be 10, and the
+    // initial value assigned to the count should be 0.
+    xSemaphore = xSemaphoreCreateCounting( 10, 0 );
+
+    if( xSemaphore != NULL )
+    {
+        // The semaphore was created successfully.
+        // The semaphore can now be used.
+    }
+ }
+ </pre>
+ * \defgroup xSemaphoreCreateCounting xSemaphoreCreateCounting
+ * \ingroup Semaphores
+ */
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+	#define xSemaphoreCreateCounting( uxMaxCount, uxInitialCount ) xQueueCreateCountingSemaphore( ( uxMaxCount ), ( uxInitialCount ) )
+#endif
+
+/**
+ * semphr. h
+ * <pre>SemaphoreHandle_t xSemaphoreCreateCountingStatic( UBaseType_t uxMaxCount, UBaseType_t uxInitialCount, StaticSemaphore_t *pxSemaphoreBuffer )</pre>
+ *
+ * Creates a new counting semaphore instance, and returns a handle by which the
+ * new counting semaphore can be referenced.
+ *
+ * In many usage scenarios it is faster and more memory efficient to use a
+ * direct to task notification in place of a counting semaphore!
+ * http://www.freertos.org/RTOS-task-notifications.html
+ *
+ * Internally, within the FreeRTOS implementation, counting semaphores use a
+ * block of memory, in which the counting semaphore structure is stored.  If a
+ * counting semaphore is created using xSemaphoreCreateCounting() then the
+ * required memory is automatically dynamically allocated inside the
+ * xSemaphoreCreateCounting() function.  (see
+ * http://www.freertos.org/a00111.html).  If a counting semaphore is created
+ * using xSemaphoreCreateCountingStatic() then the application writer must
+ * provide the memory.  xSemaphoreCreateCountingStatic() therefore allows a
+ * counting semaphore to be created without using any dynamic memory allocation.
+ *
+ * Counting semaphores are typically used for two things:
+ *
+ * 1) Counting events.
+ *
+ *    In this usage scenario an event handler will 'give' a semaphore each time
+ *    an event occurs (incrementing the semaphore count value), and a handler
+ *    task will 'take' a semaphore each time it processes an event
+ *    (decrementing the semaphore count value).  The count value is therefore
+ *    the difference between the number of events that have occurred and the
+ *    number that have been processed.  In this case it is desirable for the
+ *    initial count value to be zero.
+ *
+ * 2) Resource management.
+ *
+ *    In this usage scenario the count value indicates the number of resources
+ *    available.  To obtain control of a resource a task must first obtain a
+ *    semaphore - decrementing the semaphore count value.  When the count value
+ *    reaches zero there are no free resources.  When a task finishes with the
+ *    resource it 'gives' the semaphore back - incrementing the semaphore count
+ *    value.  In this case it is desirable for the initial count value to be
+ *    equal to the maximum count value, indicating that all resources are free.
+ *
+ * @param uxMaxCount The maximum count value that can be reached.  When the
+ *        semaphore reaches this value it can no longer be 'given'.
+ *
+ * @param uxInitialCount The count value assigned to the semaphore when it is
+ *        created.
+ *
+ * @param pxSemaphoreBuffer Must point to a variable of type StaticSemaphore_t,
+ * which will then be used to hold the semaphore's data structure, removing the
+ * need for the memory to be allocated dynamically.
+ *
+ * @return If the counting semaphore was successfully created then a handle to
+ * the created counting semaphore is returned.  If pxSemaphoreBuffer was NULL
+ * then NULL is returned.
+ *
+ * Example usage:
+ <pre>
+ SemaphoreHandle_t xSemaphore;
+ StaticSemaphore_t xSemaphoreBuffer;
+
+ void vATask( void * pvParameters )
+ {
+ SemaphoreHandle_t xSemaphore = NULL;
+
+    // Counting semaphore cannot be used before they have been created.  Create
+    // a counting semaphore using xSemaphoreCreateCountingStatic().  The max
+    // value to which the semaphore can count is 10, and the initial value
+    // assigned to the count will be 0.  The address of xSemaphoreBuffer is
+    // passed in and will be used to hold the semaphore structure, so no dynamic
+    // memory allocation will be used.
+    xSemaphore = xSemaphoreCreateCounting( 10, 0, &xSemaphoreBuffer );
+
+    // No memory allocation was attempted so xSemaphore cannot be NULL, so there
+    // is no need to check its value.
+ }
+ </pre>
+ * \defgroup xSemaphoreCreateCountingStatic xSemaphoreCreateCountingStatic
+ * \ingroup Semaphores
+ */
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+	#define xSemaphoreCreateCountingStatic( uxMaxCount, uxInitialCount, pxSemaphoreBuffer ) xQueueCreateCountingSemaphoreStatic( ( uxMaxCount ), ( uxInitialCount ), ( pxSemaphoreBuffer ) )
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+/**
+ * semphr. h
+ * <pre>void vSemaphoreDelete( SemaphoreHandle_t xSemaphore );</pre>
+ *
+ * Delete a semaphore.  This function must be used with care.  For example,
+ * do not delete a mutex type semaphore if the mutex is held by a task.
+ *
+ * @param xSemaphore A handle to the semaphore to be deleted.
+ *
+ * \defgroup vSemaphoreDelete vSemaphoreDelete
+ * \ingroup Semaphores
+ */
+#define vSemaphoreDelete( xSemaphore ) vQueueDelete( ( QueueHandle_t ) ( xSemaphore ) )
+
+/**
+ * semphr.h
+ * <pre>TaskHandle_t xSemaphoreGetMutexHolder( SemaphoreHandle_t xMutex );</pre>
+ *
+ * If xMutex is indeed a mutex type semaphore, return the current mutex holder.
+ * If xMutex is not a mutex type semaphore, or the mutex is available (not held
+ * by a task), return NULL.
+ *
+ * Note: This is a good way of determining if the calling task is the mutex
+ * holder, but not a good way of determining the identity of the mutex holder as
+ * the holder may change between the function exiting and the returned value
+ * being tested.
+ */
+#define xSemaphoreGetMutexHolder( xSemaphore ) xQueueGetMutexHolder( ( xSemaphore ) )
+
+/**
+ * semphr.h
+ * <pre>TaskHandle_t xSemaphoreGetMutexHolderFromISR( SemaphoreHandle_t xMutex );</pre>
+ *
+ * If xMutex is indeed a mutex type semaphore, return the current mutex holder.
+ * If xMutex is not a mutex type semaphore, or the mutex is available (not held
+ * by a task), return NULL.
+ *
+ */
+#define xSemaphoreGetMutexHolderFromISR( xSemaphore ) xQueueGetMutexHolderFromISR( ( xSemaphore ) )
+
+/**
+ * semphr.h
+ * <pre>UBaseType_t uxSemaphoreGetCount( SemaphoreHandle_t xSemaphore );</pre>
+ *
+ * If the semaphore is a counting semaphore then uxSemaphoreGetCount() returns
+ * its current count value.  If the semaphore is a binary semaphore then
+ * uxSemaphoreGetCount() returns 1 if the semaphore is available, and 0 if the
+ * semaphore is not available.
+ *
+ */
+#define uxSemaphoreGetCount( xSemaphore ) uxQueueMessagesWaiting( ( QueueHandle_t ) ( xSemaphore ) )
+
+#endif /* SEMAPHORE_H */
+
+
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/stack_macros.h b/Middlewares/Third_Party/FreeRTOS/Source/include/stack_macros.h
new file mode 100644
index 0000000..b5bac08
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/include/stack_macros.h
@@ -0,0 +1,129 @@
+/*
+ * FreeRTOS Kernel V10.3.1
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef STACK_MACROS_H
+#define STACK_MACROS_H
+
+/*
+ * Call the stack overflow hook function if the stack of the task being swapped
+ * out is currently overflowed, or looks like it might have overflowed in the
+ * past.
+ *
+ * Setting configCHECK_FOR_STACK_OVERFLOW to 1 will cause the macro to check
+ * the current stack state only - comparing the current top of stack value to
+ * the stack limit.  Setting configCHECK_FOR_STACK_OVERFLOW to greater than 1
+ * will also cause the last few stack bytes to be checked to ensure the value
+ * to which the bytes were set when the task was created have not been
+ * overwritten.  Note this second test does not guarantee that an overflowed
+ * stack will always be recognised.
+ */
+
+/*-----------------------------------------------------------*/
+
+#if( ( configCHECK_FOR_STACK_OVERFLOW == 1 ) && ( portSTACK_GROWTH < 0 ) )
+
+	/* Only the current stack state is to be checked. */
+	#define taskCHECK_FOR_STACK_OVERFLOW()																\
+	{																									\
+		/* Is the currently saved stack pointer within the stack limit? */								\
+		if( pxCurrentTCB->pxTopOfStack <= pxCurrentTCB->pxStack )										\
+		{																								\
+			vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName );	\
+		}																								\
+	}
+
+#endif /* configCHECK_FOR_STACK_OVERFLOW == 1 */
+/*-----------------------------------------------------------*/
+
+#if( ( configCHECK_FOR_STACK_OVERFLOW == 1 ) && ( portSTACK_GROWTH > 0 ) )
+
+	/* Only the current stack state is to be checked. */
+	#define taskCHECK_FOR_STACK_OVERFLOW()																\
+	{																									\
+																										\
+		/* Is the currently saved stack pointer within the stack limit? */								\
+		if( pxCurrentTCB->pxTopOfStack >= pxCurrentTCB->pxEndOfStack )									\
+		{																								\
+			vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName );	\
+		}																								\
+	}
+
+#endif /* configCHECK_FOR_STACK_OVERFLOW == 1 */
+/*-----------------------------------------------------------*/
+
+#if( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) && ( portSTACK_GROWTH < 0 ) )
+
+	#define taskCHECK_FOR_STACK_OVERFLOW()																\
+	{																									\
+		const uint32_t * const pulStack = ( uint32_t * ) pxCurrentTCB->pxStack;							\
+		const uint32_t ulCheckValue = ( uint32_t ) 0xa5a5a5a5;											\
+																										\
+		if( ( pulStack[ 0 ] != ulCheckValue ) ||														\
+			( pulStack[ 1 ] != ulCheckValue ) ||														\
+			( pulStack[ 2 ] != ulCheckValue ) ||														\
+			( pulStack[ 3 ] != ulCheckValue ) )															\
+		{																								\
+			vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName );	\
+		}																								\
+	}
+
+#endif /* #if( configCHECK_FOR_STACK_OVERFLOW > 1 ) */
+/*-----------------------------------------------------------*/
+
+#if( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) && ( portSTACK_GROWTH > 0 ) )
+
+	#define taskCHECK_FOR_STACK_OVERFLOW()																								\
+	{																																	\
+	int8_t *pcEndOfStack = ( int8_t * ) pxCurrentTCB->pxEndOfStack;																		\
+	static const uint8_t ucExpectedStackBytes[] = {	tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,		\
+													tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,		\
+													tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,		\
+													tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,		\
+													tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE };	\
+																																		\
+																																		\
+		pcEndOfStack -= sizeof( ucExpectedStackBytes );																					\
+																																		\
+		/* Has the extremity of the task stack ever been written over? */																\
+		if( memcmp( ( void * ) pcEndOfStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) != 0 )					\
+		{																																\
+			vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName );									\
+		}																																\
+	}
+
+#endif /* #if( configCHECK_FOR_STACK_OVERFLOW > 1 ) */
+/*-----------------------------------------------------------*/
+
+/* Remove stack overflow macro if not being used. */
+#ifndef taskCHECK_FOR_STACK_OVERFLOW
+	#define taskCHECK_FOR_STACK_OVERFLOW()
+#endif
+
+
+
+#endif /* STACK_MACROS_H */
+
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/stream_buffer.h b/Middlewares/Third_Party/FreeRTOS/Source/include/stream_buffer.h
new file mode 100644
index 0000000..a8b68ad
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/include/stream_buffer.h
@@ -0,0 +1,859 @@
+/*
+ * FreeRTOS Kernel V10.3.1
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*
+ * Stream buffers are used to send a continuous stream of data from one task or
+ * interrupt to another.  Their implementation is light weight, making them
+ * particularly suited for interrupt to task and core to core communication
+ * scenarios.
+ *
+ * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
+ * implementation (so also the message buffer implementation, as message buffers
+ * are built on top of stream buffers) assumes there is only one task or
+ * interrupt that will write to the buffer (the writer), and only one task or
+ * interrupt that will read from the buffer (the reader).  It is safe for the
+ * writer and reader to be different tasks or interrupts, but, unlike other
+ * FreeRTOS objects, it is not safe to have multiple different writers or
+ * multiple different readers.  If there are to be multiple different writers
+ * then the application writer must place each call to a writing API function
+ * (such as xStreamBufferSend()) inside a critical section and set the send
+ * block time to 0.  Likewise, if there are to be multiple different readers
+ * then the application writer must place each call to a reading API function
+ * (such as xStreamBufferReceive()) inside a critical section section and set the
+ * receive block time to 0.
+ *
+ */
+
+#ifndef STREAM_BUFFER_H
+#define STREAM_BUFFER_H
+
+#ifndef INC_FREERTOS_H
+	#error "include FreeRTOS.h must appear in source files before include stream_buffer.h"
+#endif
+
+#if defined( __cplusplus )
+extern "C" {
+#endif
+
+/**
+ * Type by which stream buffers are referenced.  For example, a call to
+ * xStreamBufferCreate() returns an StreamBufferHandle_t variable that can
+ * then be used as a parameter to xStreamBufferSend(), xStreamBufferReceive(),
+ * etc.
+ */
+struct StreamBufferDef_t;
+typedef struct StreamBufferDef_t * StreamBufferHandle_t;
+
+
+/**
+ * message_buffer.h
+ *
+<pre>
+StreamBufferHandle_t xStreamBufferCreate( size_t xBufferSizeBytes, size_t xTriggerLevelBytes );
+</pre>
+ *
+ * Creates a new stream buffer using dynamically allocated memory.  See
+ * xStreamBufferCreateStatic() for a version that uses statically allocated
+ * memory (memory that is allocated at compile time).
+ *
+ * configSUPPORT_DYNAMIC_ALLOCATION must be set to 1 or left undefined in
+ * FreeRTOSConfig.h for xStreamBufferCreate() to be available.
+ *
+ * @param xBufferSizeBytes The total number of bytes the stream buffer will be
+ * able to hold at any one time.
+ *
+ * @param xTriggerLevelBytes The number of bytes that must be in the stream
+ * buffer before a task that is blocked on the stream buffer to wait for data is
+ * moved out of the blocked state.  For example, if a task is blocked on a read
+ * of an empty stream buffer that has a trigger level of 1 then the task will be
+ * unblocked when a single byte is written to the buffer or the task's block
+ * time expires.  As another example, if a task is blocked on a read of an empty
+ * stream buffer that has a trigger level of 10 then the task will not be
+ * unblocked until the stream buffer contains at least 10 bytes or the task's
+ * block time expires.  If a reading task's block time expires before the
+ * trigger level is reached then the task will still receive however many bytes
+ * are actually available.  Setting a trigger level of 0 will result in a
+ * trigger level of 1 being used.  It is not valid to specify a trigger level
+ * that is greater than the buffer size.
+ *
+ * @return If NULL is returned, then the stream buffer cannot be created
+ * because there is insufficient heap memory available for FreeRTOS to allocate
+ * the stream buffer data structures and storage area.  A non-NULL value being
+ * returned indicates that the stream buffer has been created successfully -
+ * the returned value should be stored as the handle to the created stream
+ * buffer.
+ *
+ * Example use:
+<pre>
+
+void vAFunction( void )
+{
+StreamBufferHandle_t xStreamBuffer;
+const size_t xStreamBufferSizeBytes = 100, xTriggerLevel = 10;
+
+    // Create a stream buffer that can hold 100 bytes.  The memory used to hold
+    // both the stream buffer structure and the data in the stream buffer is
+    // allocated dynamically.
+    xStreamBuffer = xStreamBufferCreate( xStreamBufferSizeBytes, xTriggerLevel );
+
+    if( xStreamBuffer == NULL )
+    {
+        // There was not enough heap memory space available to create the
+        // stream buffer.
+    }
+    else
+    {
+        // The stream buffer was created successfully and can now be used.
+    }
+}
+</pre>
+ * \defgroup xStreamBufferCreate xStreamBufferCreate
+ * \ingroup StreamBufferManagement
+ */
+#define xStreamBufferCreate( xBufferSizeBytes, xTriggerLevelBytes ) xStreamBufferGenericCreate( xBufferSizeBytes, xTriggerLevelBytes, pdFALSE )
+
+/**
+ * stream_buffer.h
+ *
+<pre>
+StreamBufferHandle_t xStreamBufferCreateStatic( size_t xBufferSizeBytes,
+                                                size_t xTriggerLevelBytes,
+                                                uint8_t *pucStreamBufferStorageArea,
+                                                StaticStreamBuffer_t *pxStaticStreamBuffer );
+</pre>
+ * Creates a new stream buffer using statically allocated memory.  See
+ * xStreamBufferCreate() for a version that uses dynamically allocated memory.
+ *
+ * configSUPPORT_STATIC_ALLOCATION must be set to 1 in FreeRTOSConfig.h for
+ * xStreamBufferCreateStatic() to be available.
+ *
+ * @param xBufferSizeBytes The size, in bytes, of the buffer pointed to by the
+ * pucStreamBufferStorageArea parameter.
+ *
+ * @param xTriggerLevelBytes The number of bytes that must be in the stream
+ * buffer before a task that is blocked on the stream buffer to wait for data is
+ * moved out of the blocked state.  For example, if a task is blocked on a read
+ * of an empty stream buffer that has a trigger level of 1 then the task will be
+ * unblocked when a single byte is written to the buffer or the task's block
+ * time expires.  As another example, if a task is blocked on a read of an empty
+ * stream buffer that has a trigger level of 10 then the task will not be
+ * unblocked until the stream buffer contains at least 10 bytes or the task's
+ * block time expires.  If a reading task's block time expires before the
+ * trigger level is reached then the task will still receive however many bytes
+ * are actually available.  Setting a trigger level of 0 will result in a
+ * trigger level of 1 being used.  It is not valid to specify a trigger level
+ * that is greater than the buffer size.
+ *
+ * @param pucStreamBufferStorageArea Must point to a uint8_t array that is at
+ * least xBufferSizeBytes + 1 big.  This is the array to which streams are
+ * copied when they are written to the stream buffer.
+ *
+ * @param pxStaticStreamBuffer Must point to a variable of type
+ * StaticStreamBuffer_t, which will be used to hold the stream buffer's data
+ * structure.
+ *
+ * @return If the stream buffer is created successfully then a handle to the
+ * created stream buffer is returned. If either pucStreamBufferStorageArea or
+ * pxStaticstreamBuffer are NULL then NULL is returned.
+ *
+ * Example use:
+<pre>
+
+// Used to dimension the array used to hold the streams.  The available space
+// will actually be one less than this, so 999.
+#define STORAGE_SIZE_BYTES 1000
+
+// Defines the memory that will actually hold the streams within the stream
+// buffer.
+static uint8_t ucStorageBuffer[ STORAGE_SIZE_BYTES ];
+
+// The variable used to hold the stream buffer structure.
+StaticStreamBuffer_t xStreamBufferStruct;
+
+void MyFunction( void )
+{
+StreamBufferHandle_t xStreamBuffer;
+const size_t xTriggerLevel = 1;
+
+    xStreamBuffer = xStreamBufferCreateStatic( sizeof( ucBufferStorage ),
+                                               xTriggerLevel,
+                                               ucBufferStorage,
+                                               &xStreamBufferStruct );
+
+    // As neither the pucStreamBufferStorageArea or pxStaticStreamBuffer
+    // parameters were NULL, xStreamBuffer will not be NULL, and can be used to
+    // reference the created stream buffer in other stream buffer API calls.
+
+    // Other code that uses the stream buffer can go here.
+}
+
+</pre>
+ * \defgroup xStreamBufferCreateStatic xStreamBufferCreateStatic
+ * \ingroup StreamBufferManagement
+ */
+#define xStreamBufferCreateStatic( xBufferSizeBytes, xTriggerLevelBytes, pucStreamBufferStorageArea, pxStaticStreamBuffer ) xStreamBufferGenericCreateStatic( xBufferSizeBytes, xTriggerLevelBytes, pdFALSE, pucStreamBufferStorageArea, pxStaticStreamBuffer )
+
+/**
+ * stream_buffer.h
+ *
+<pre>
+size_t xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+                          const void *pvTxData,
+                          size_t xDataLengthBytes,
+                          TickType_t xTicksToWait );
+</pre>
+ *
+ * Sends bytes to a stream buffer.  The bytes are copied into the stream buffer.
+ *
+ * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
+ * implementation (so also the message buffer implementation, as message buffers
+ * are built on top of stream buffers) assumes there is only one task or
+ * interrupt that will write to the buffer (the writer), and only one task or
+ * interrupt that will read from the buffer (the reader).  It is safe for the
+ * writer and reader to be different tasks or interrupts, but, unlike other
+ * FreeRTOS objects, it is not safe to have multiple different writers or
+ * multiple different readers.  If there are to be multiple different writers
+ * then the application writer must place each call to a writing API function
+ * (such as xStreamBufferSend()) inside a critical section and set the send
+ * block time to 0.  Likewise, if there are to be multiple different readers
+ * then the application writer must place each call to a reading API function
+ * (such as xStreamBufferReceive()) inside a critical section and set the receive
+ * block time to 0.
+ *
+ * Use xStreamBufferSend() to write to a stream buffer from a task.  Use
+ * xStreamBufferSendFromISR() to write to a stream buffer from an interrupt
+ * service routine (ISR).
+ *
+ * @param xStreamBuffer The handle of the stream buffer to which a stream is
+ * being sent.
+ *
+ * @param pvTxData A pointer to the buffer that holds the bytes to be copied
+ * into the stream buffer.
+ *
+ * @param xDataLengthBytes   The maximum number of bytes to copy from pvTxData
+ * into the stream buffer.
+ *
+ * @param xTicksToWait The maximum amount of time the task should remain in the
+ * Blocked state to wait for enough space to become available in the stream
+ * buffer, should the stream buffer contain too little space to hold the
+ * another xDataLengthBytes bytes.  The block time is specified in tick periods,
+ * so the absolute time it represents is dependent on the tick frequency.  The
+ * macro pdMS_TO_TICKS() can be used to convert a time specified in milliseconds
+ * into a time specified in ticks.  Setting xTicksToWait to portMAX_DELAY will
+ * cause the task to wait indefinitely (without timing out), provided
+ * INCLUDE_vTaskSuspend is set to 1 in FreeRTOSConfig.h.  If a task times out
+ * before it can write all xDataLengthBytes into the buffer it will still write
+ * as many bytes as possible.  A task does not use any CPU time when it is in
+ * the blocked state.
+ *
+ * @return The number of bytes written to the stream buffer.  If a task times
+ * out before it can write all xDataLengthBytes into the buffer it will still
+ * write as many bytes as possible.
+ *
+ * Example use:
+<pre>
+void vAFunction( StreamBufferHandle_t xStreamBuffer )
+{
+size_t xBytesSent;
+uint8_t ucArrayToSend[] = { 0, 1, 2, 3 };
+char *pcStringToSend = "String to send";
+const TickType_t x100ms = pdMS_TO_TICKS( 100 );
+
+    // Send an array to the stream buffer, blocking for a maximum of 100ms to
+    // wait for enough space to be available in the stream buffer.
+    xBytesSent = xStreamBufferSend( xStreamBuffer, ( void * ) ucArrayToSend, sizeof( ucArrayToSend ), x100ms );
+
+    if( xBytesSent != sizeof( ucArrayToSend ) )
+    {
+        // The call to xStreamBufferSend() times out before there was enough
+        // space in the buffer for the data to be written, but it did
+        // successfully write xBytesSent bytes.
+    }
+
+    // Send the string to the stream buffer.  Return immediately if there is not
+    // enough space in the buffer.
+    xBytesSent = xStreamBufferSend( xStreamBuffer, ( void * ) pcStringToSend, strlen( pcStringToSend ), 0 );
+
+    if( xBytesSent != strlen( pcStringToSend ) )
+    {
+        // The entire string could not be added to the stream buffer because
+        // there was not enough free space in the buffer, but xBytesSent bytes
+        // were sent.  Could try again to send the remaining bytes.
+    }
+}
+</pre>
+ * \defgroup xStreamBufferSend xStreamBufferSend
+ * \ingroup StreamBufferManagement
+ */
+size_t xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+						  const void *pvTxData,
+						  size_t xDataLengthBytes,
+						  TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+<pre>
+size_t xStreamBufferSendFromISR( StreamBufferHandle_t xStreamBuffer,
+                                 const void *pvTxData,
+                                 size_t xDataLengthBytes,
+                                 BaseType_t *pxHigherPriorityTaskWoken );
+</pre>
+ *
+ * Interrupt safe version of the API function that sends a stream of bytes to
+ * the stream buffer.
+ *
+ * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
+ * implementation (so also the message buffer implementation, as message buffers
+ * are built on top of stream buffers) assumes there is only one task or
+ * interrupt that will write to the buffer (the writer), and only one task or
+ * interrupt that will read from the buffer (the reader).  It is safe for the
+ * writer and reader to be different tasks or interrupts, but, unlike other
+ * FreeRTOS objects, it is not safe to have multiple different writers or
+ * multiple different readers.  If there are to be multiple different writers
+ * then the application writer must place each call to a writing API function
+ * (such as xStreamBufferSend()) inside a critical section and set the send
+ * block time to 0.  Likewise, if there are to be multiple different readers
+ * then the application writer must place each call to a reading API function
+ * (such as xStreamBufferReceive()) inside a critical section and set the receive
+ * block time to 0.
+ *
+ * Use xStreamBufferSend() to write to a stream buffer from a task.  Use
+ * xStreamBufferSendFromISR() to write to a stream buffer from an interrupt
+ * service routine (ISR).
+ *
+ * @param xStreamBuffer The handle of the stream buffer to which a stream is
+ * being sent.
+ *
+ * @param pvTxData A pointer to the data that is to be copied into the stream
+ * buffer.
+ *
+ * @param xDataLengthBytes The maximum number of bytes to copy from pvTxData
+ * into the stream buffer.
+ *
+ * @param pxHigherPriorityTaskWoken  It is possible that a stream buffer will
+ * have a task blocked on it waiting for data.  Calling
+ * xStreamBufferSendFromISR() can make data available, and so cause a task that
+ * was waiting for data to leave the Blocked state.  If calling
+ * xStreamBufferSendFromISR() causes a task to leave the Blocked state, and the
+ * unblocked task has a priority higher than the currently executing task (the
+ * task that was interrupted), then, internally, xStreamBufferSendFromISR()
+ * will set *pxHigherPriorityTaskWoken to pdTRUE.  If
+ * xStreamBufferSendFromISR() sets this value to pdTRUE, then normally a
+ * context switch should be performed before the interrupt is exited.  This will
+ * ensure that the interrupt returns directly to the highest priority Ready
+ * state task.  *pxHigherPriorityTaskWoken should be set to pdFALSE before it
+ * is passed into the function.  See the example code below for an example.
+ *
+ * @return The number of bytes actually written to the stream buffer, which will
+ * be less than xDataLengthBytes if the stream buffer didn't have enough free
+ * space for all the bytes to be written.
+ *
+ * Example use:
+<pre>
+// A stream buffer that has already been created.
+StreamBufferHandle_t xStreamBuffer;
+
+void vAnInterruptServiceRoutine( void )
+{
+size_t xBytesSent;
+char *pcStringToSend = "String to send";
+BaseType_t xHigherPriorityTaskWoken = pdFALSE; // Initialised to pdFALSE.
+
+    // Attempt to send the string to the stream buffer.
+    xBytesSent = xStreamBufferSendFromISR( xStreamBuffer,
+                                           ( void * ) pcStringToSend,
+                                           strlen( pcStringToSend ),
+                                           &xHigherPriorityTaskWoken );
+
+    if( xBytesSent != strlen( pcStringToSend ) )
+    {
+        // There was not enough free space in the stream buffer for the entire
+        // string to be written, ut xBytesSent bytes were written.
+    }
+
+    // If xHigherPriorityTaskWoken was set to pdTRUE inside
+    // xStreamBufferSendFromISR() then a task that has a priority above the
+    // priority of the currently executing task was unblocked and a context
+    // switch should be performed to ensure the ISR returns to the unblocked
+    // task.  In most FreeRTOS ports this is done by simply passing
+    // xHigherPriorityTaskWoken into taskYIELD_FROM_ISR(), which will test the
+    // variables value, and perform the context switch if necessary.  Check the
+    // documentation for the port in use for port specific instructions.
+    taskYIELD_FROM_ISR( xHigherPriorityTaskWoken );
+}
+</pre>
+ * \defgroup xStreamBufferSendFromISR xStreamBufferSendFromISR
+ * \ingroup StreamBufferManagement
+ */
+size_t xStreamBufferSendFromISR( StreamBufferHandle_t xStreamBuffer,
+								 const void *pvTxData,
+								 size_t xDataLengthBytes,
+								 BaseType_t * const pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+<pre>
+size_t xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+                             void *pvRxData,
+                             size_t xBufferLengthBytes,
+                             TickType_t xTicksToWait );
+</pre>
+ *
+ * Receives bytes from a stream buffer.
+ *
+ * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
+ * implementation (so also the message buffer implementation, as message buffers
+ * are built on top of stream buffers) assumes there is only one task or
+ * interrupt that will write to the buffer (the writer), and only one task or
+ * interrupt that will read from the buffer (the reader).  It is safe for the
+ * writer and reader to be different tasks or interrupts, but, unlike other
+ * FreeRTOS objects, it is not safe to have multiple different writers or
+ * multiple different readers.  If there are to be multiple different writers
+ * then the application writer must place each call to a writing API function
+ * (such as xStreamBufferSend()) inside a critical section and set the send
+ * block time to 0.  Likewise, if there are to be multiple different readers
+ * then the application writer must place each call to a reading API function
+ * (such as xStreamBufferReceive()) inside a critical section and set the receive
+ * block time to 0.
+ *
+ * Use xStreamBufferReceive() to read from a stream buffer from a task.  Use
+ * xStreamBufferReceiveFromISR() to read from a stream buffer from an
+ * interrupt service routine (ISR).
+ *
+ * @param xStreamBuffer The handle of the stream buffer from which bytes are to
+ * be received.
+ *
+ * @param pvRxData A pointer to the buffer into which the received bytes will be
+ * copied.
+ *
+ * @param xBufferLengthBytes The length of the buffer pointed to by the
+ * pvRxData parameter.  This sets the maximum number of bytes to receive in one
+ * call.  xStreamBufferReceive will return as many bytes as possible up to a
+ * maximum set by xBufferLengthBytes.
+ *
+ * @param xTicksToWait The maximum amount of time the task should remain in the
+ * Blocked state to wait for data to become available if the stream buffer is
+ * empty.  xStreamBufferReceive() will return immediately if xTicksToWait is
+ * zero.  The block time is specified in tick periods, so the absolute time it
+ * represents is dependent on the tick frequency.  The macro pdMS_TO_TICKS() can
+ * be used to convert a time specified in milliseconds into a time specified in
+ * ticks.  Setting xTicksToWait to portMAX_DELAY will cause the task to wait
+ * indefinitely (without timing out), provided INCLUDE_vTaskSuspend is set to 1
+ * in FreeRTOSConfig.h.  A task does not use any CPU time when it is in the
+ * Blocked state.
+ *
+ * @return The number of bytes actually read from the stream buffer, which will
+ * be less than xBufferLengthBytes if the call to xStreamBufferReceive() timed
+ * out before xBufferLengthBytes were available.
+ *
+ * Example use:
+<pre>
+void vAFunction( StreamBuffer_t xStreamBuffer )
+{
+uint8_t ucRxData[ 20 ];
+size_t xReceivedBytes;
+const TickType_t xBlockTime = pdMS_TO_TICKS( 20 );
+
+    // Receive up to another sizeof( ucRxData ) bytes from the stream buffer.
+    // Wait in the Blocked state (so not using any CPU processing time) for a
+    // maximum of 100ms for the full sizeof( ucRxData ) number of bytes to be
+    // available.
+    xReceivedBytes = xStreamBufferReceive( xStreamBuffer,
+                                           ( void * ) ucRxData,
+                                           sizeof( ucRxData ),
+                                           xBlockTime );
+
+    if( xReceivedBytes > 0 )
+    {
+        // A ucRxData contains another xRecievedBytes bytes of data, which can
+        // be processed here....
+    }
+}
+</pre>
+ * \defgroup xStreamBufferReceive xStreamBufferReceive
+ * \ingroup StreamBufferManagement
+ */
+size_t xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+							 void *pvRxData,
+							 size_t xBufferLengthBytes,
+							 TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+<pre>
+size_t xStreamBufferReceiveFromISR( StreamBufferHandle_t xStreamBuffer,
+                                    void *pvRxData,
+                                    size_t xBufferLengthBytes,
+                                    BaseType_t *pxHigherPriorityTaskWoken );
+</pre>
+ *
+ * An interrupt safe version of the API function that receives bytes from a
+ * stream buffer.
+ *
+ * Use xStreamBufferReceive() to read bytes from a stream buffer from a task.
+ * Use xStreamBufferReceiveFromISR() to read bytes from a stream buffer from an
+ * interrupt service routine (ISR).
+ *
+ * @param xStreamBuffer The handle of the stream buffer from which a stream
+ * is being received.
+ *
+ * @param pvRxData A pointer to the buffer into which the received bytes are
+ * copied.
+ *
+ * @param xBufferLengthBytes The length of the buffer pointed to by the
+ * pvRxData parameter.  This sets the maximum number of bytes to receive in one
+ * call.  xStreamBufferReceive will return as many bytes as possible up to a
+ * maximum set by xBufferLengthBytes.
+ *
+ * @param pxHigherPriorityTaskWoken  It is possible that a stream buffer will
+ * have a task blocked on it waiting for space to become available.  Calling
+ * xStreamBufferReceiveFromISR() can make space available, and so cause a task
+ * that is waiting for space to leave the Blocked state.  If calling
+ * xStreamBufferReceiveFromISR() causes a task to leave the Blocked state, and
+ * the unblocked task has a priority higher than the currently executing task
+ * (the task that was interrupted), then, internally,
+ * xStreamBufferReceiveFromISR() will set *pxHigherPriorityTaskWoken to pdTRUE.
+ * If xStreamBufferReceiveFromISR() sets this value to pdTRUE, then normally a
+ * context switch should be performed before the interrupt is exited.  That will
+ * ensure the interrupt returns directly to the highest priority Ready state
+ * task.  *pxHigherPriorityTaskWoken should be set to pdFALSE before it is
+ * passed into the function.  See the code example below for an example.
+ *
+ * @return The number of bytes read from the stream buffer, if any.
+ *
+ * Example use:
+<pre>
+// A stream buffer that has already been created.
+StreamBuffer_t xStreamBuffer;
+
+void vAnInterruptServiceRoutine( void )
+{
+uint8_t ucRxData[ 20 ];
+size_t xReceivedBytes;
+BaseType_t xHigherPriorityTaskWoken = pdFALSE;  // Initialised to pdFALSE.
+
+    // Receive the next stream from the stream buffer.
+    xReceivedBytes = xStreamBufferReceiveFromISR( xStreamBuffer,
+                                                  ( void * ) ucRxData,
+                                                  sizeof( ucRxData ),
+                                                  &xHigherPriorityTaskWoken );
+
+    if( xReceivedBytes > 0 )
+    {
+        // ucRxData contains xReceivedBytes read from the stream buffer.
+        // Process the stream here....
+    }
+
+    // If xHigherPriorityTaskWoken was set to pdTRUE inside
+    // xStreamBufferReceiveFromISR() then a task that has a priority above the
+    // priority of the currently executing task was unblocked and a context
+    // switch should be performed to ensure the ISR returns to the unblocked
+    // task.  In most FreeRTOS ports this is done by simply passing
+    // xHigherPriorityTaskWoken into taskYIELD_FROM_ISR(), which will test the
+    // variables value, and perform the context switch if necessary.  Check the
+    // documentation for the port in use for port specific instructions.
+    taskYIELD_FROM_ISR( xHigherPriorityTaskWoken );
+}
+</pre>
+ * \defgroup xStreamBufferReceiveFromISR xStreamBufferReceiveFromISR
+ * \ingroup StreamBufferManagement
+ */
+size_t xStreamBufferReceiveFromISR( StreamBufferHandle_t xStreamBuffer,
+									void *pvRxData,
+									size_t xBufferLengthBytes,
+									BaseType_t * const pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+<pre>
+void vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer );
+</pre>
+ *
+ * Deletes a stream buffer that was previously created using a call to
+ * xStreamBufferCreate() or xStreamBufferCreateStatic().  If the stream
+ * buffer was created using dynamic memory (that is, by xStreamBufferCreate()),
+ * then the allocated memory is freed.
+ *
+ * A stream buffer handle must not be used after the stream buffer has been
+ * deleted.
+ *
+ * @param xStreamBuffer The handle of the stream buffer to be deleted.
+ *
+ * \defgroup vStreamBufferDelete vStreamBufferDelete
+ * \ingroup StreamBufferManagement
+ */
+void vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+<pre>
+BaseType_t xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer );
+</pre>
+ *
+ * Queries a stream buffer to see if it is full.  A stream buffer is full if it
+ * does not have any free space, and therefore cannot accept any more data.
+ *
+ * @param xStreamBuffer The handle of the stream buffer being queried.
+ *
+ * @return If the stream buffer is full then pdTRUE is returned.  Otherwise
+ * pdFALSE is returned.
+ *
+ * \defgroup xStreamBufferIsFull xStreamBufferIsFull
+ * \ingroup StreamBufferManagement
+ */
+BaseType_t xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+<pre>
+BaseType_t xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer );
+</pre>
+ *
+ * Queries a stream buffer to see if it is empty.  A stream buffer is empty if
+ * it does not contain any data.
+ *
+ * @param xStreamBuffer The handle of the stream buffer being queried.
+ *
+ * @return If the stream buffer is empty then pdTRUE is returned.  Otherwise
+ * pdFALSE is returned.
+ *
+ * \defgroup xStreamBufferIsEmpty xStreamBufferIsEmpty
+ * \ingroup StreamBufferManagement
+ */
+BaseType_t xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+<pre>
+BaseType_t xStreamBufferReset( StreamBufferHandle_t xStreamBuffer );
+</pre>
+ *
+ * Resets a stream buffer to its initial, empty, state.  Any data that was in
+ * the stream buffer is discarded.  A stream buffer can only be reset if there
+ * are no tasks blocked waiting to either send to or receive from the stream
+ * buffer.
+ *
+ * @param xStreamBuffer The handle of the stream buffer being reset.
+ *
+ * @return If the stream buffer is reset then pdPASS is returned.  If there was
+ * a task blocked waiting to send to or read from the stream buffer then the
+ * stream buffer is not reset and pdFAIL is returned.
+ *
+ * \defgroup xStreamBufferReset xStreamBufferReset
+ * \ingroup StreamBufferManagement
+ */
+BaseType_t xStreamBufferReset( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+<pre>
+size_t xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer );
+</pre>
+ *
+ * Queries a stream buffer to see how much free space it contains, which is
+ * equal to the amount of data that can be sent to the stream buffer before it
+ * is full.
+ *
+ * @param xStreamBuffer The handle of the stream buffer being queried.
+ *
+ * @return The number of bytes that can be written to the stream buffer before
+ * the stream buffer would be full.
+ *
+ * \defgroup xStreamBufferSpacesAvailable xStreamBufferSpacesAvailable
+ * \ingroup StreamBufferManagement
+ */
+size_t xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+<pre>
+size_t xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer );
+</pre>
+ *
+ * Queries a stream buffer to see how much data it contains, which is equal to
+ * the number of bytes that can be read from the stream buffer before the stream
+ * buffer would be empty.
+ *
+ * @param xStreamBuffer The handle of the stream buffer being queried.
+ *
+ * @return The number of bytes that can be read from the stream buffer before
+ * the stream buffer would be empty.
+ *
+ * \defgroup xStreamBufferBytesAvailable xStreamBufferBytesAvailable
+ * \ingroup StreamBufferManagement
+ */
+size_t xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+<pre>
+BaseType_t xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, size_t xTriggerLevel );
+</pre>
+ *
+ * A stream buffer's trigger level is the number of bytes that must be in the
+ * stream buffer before a task that is blocked on the stream buffer to
+ * wait for data is moved out of the blocked state.  For example, if a task is
+ * blocked on a read of an empty stream buffer that has a trigger level of 1
+ * then the task will be unblocked when a single byte is written to the buffer
+ * or the task's block time expires.  As another example, if a task is blocked
+ * on a read of an empty stream buffer that has a trigger level of 10 then the
+ * task will not be unblocked until the stream buffer contains at least 10 bytes
+ * or the task's block time expires.  If a reading task's block time expires
+ * before the trigger level is reached then the task will still receive however
+ * many bytes are actually available.  Setting a trigger level of 0 will result
+ * in a trigger level of 1 being used.  It is not valid to specify a trigger
+ * level that is greater than the buffer size.
+ *
+ * A trigger level is set when the stream buffer is created, and can be modified
+ * using xStreamBufferSetTriggerLevel().
+ *
+ * @param xStreamBuffer The handle of the stream buffer being updated.
+ *
+ * @param xTriggerLevel The new trigger level for the stream buffer.
+ *
+ * @return If xTriggerLevel was less than or equal to the stream buffer's length
+ * then the trigger level will be updated and pdTRUE is returned.  Otherwise
+ * pdFALSE is returned.
+ *
+ * \defgroup xStreamBufferSetTriggerLevel xStreamBufferSetTriggerLevel
+ * \ingroup StreamBufferManagement
+ */
+BaseType_t xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, size_t xTriggerLevel ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+<pre>
+BaseType_t xStreamBufferSendCompletedFromISR( StreamBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken );
+</pre>
+ *
+ * For advanced users only.
+ *
+ * The sbSEND_COMPLETED() macro is called from within the FreeRTOS APIs when
+ * data is sent to a message buffer or stream buffer.  If there was a task that
+ * was blocked on the message or stream buffer waiting for data to arrive then
+ * the sbSEND_COMPLETED() macro sends a notification to the task to remove it
+ * from the Blocked state.  xStreamBufferSendCompletedFromISR() does the same
+ * thing.  It is provided to enable application writers to implement their own
+ * version of sbSEND_COMPLETED(), and MUST NOT BE USED AT ANY OTHER TIME.
+ *
+ * See the example implemented in FreeRTOS/Demo/Minimal/MessageBufferAMP.c for
+ * additional information.
+ *
+ * @param xStreamBuffer The handle of the stream buffer to which data was
+ * written.
+ *
+ * @param pxHigherPriorityTaskWoken *pxHigherPriorityTaskWoken should be
+ * initialised to pdFALSE before it is passed into
+ * xStreamBufferSendCompletedFromISR().  If calling
+ * xStreamBufferSendCompletedFromISR() removes a task from the Blocked state,
+ * and the task has a priority above the priority of the currently running task,
+ * then *pxHigherPriorityTaskWoken will get set to pdTRUE indicating that a
+ * context switch should be performed before exiting the ISR.
+ *
+ * @return If a task was removed from the Blocked state then pdTRUE is returned.
+ * Otherwise pdFALSE is returned.
+ *
+ * \defgroup xStreamBufferSendCompletedFromISR xStreamBufferSendCompletedFromISR
+ * \ingroup StreamBufferManagement
+ */
+BaseType_t xStreamBufferSendCompletedFromISR( StreamBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+<pre>
+BaseType_t xStreamBufferReceiveCompletedFromISR( StreamBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken );
+</pre>
+ *
+ * For advanced users only.
+ *
+ * The sbRECEIVE_COMPLETED() macro is called from within the FreeRTOS APIs when
+ * data is read out of a message buffer or stream buffer.  If there was a task
+ * that was blocked on the message or stream buffer waiting for data to arrive
+ * then the sbRECEIVE_COMPLETED() macro sends a notification to the task to
+ * remove it from the Blocked state.  xStreamBufferReceiveCompletedFromISR()
+ * does the same thing.  It is provided to enable application writers to
+ * implement their own version of sbRECEIVE_COMPLETED(), and MUST NOT BE USED AT
+ * ANY OTHER TIME.
+ *
+ * See the example implemented in FreeRTOS/Demo/Minimal/MessageBufferAMP.c for
+ * additional information.
+ *
+ * @param xStreamBuffer The handle of the stream buffer from which data was
+ * read.
+ *
+ * @param pxHigherPriorityTaskWoken *pxHigherPriorityTaskWoken should be
+ * initialised to pdFALSE before it is passed into
+ * xStreamBufferReceiveCompletedFromISR().  If calling
+ * xStreamBufferReceiveCompletedFromISR() removes a task from the Blocked state,
+ * and the task has a priority above the priority of the currently running task,
+ * then *pxHigherPriorityTaskWoken will get set to pdTRUE indicating that a
+ * context switch should be performed before exiting the ISR.
+ *
+ * @return If a task was removed from the Blocked state then pdTRUE is returned.
+ * Otherwise pdFALSE is returned.
+ *
+ * \defgroup xStreamBufferReceiveCompletedFromISR xStreamBufferReceiveCompletedFromISR
+ * \ingroup StreamBufferManagement
+ */
+BaseType_t xStreamBufferReceiveCompletedFromISR( StreamBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+
+/* Functions below here are not part of the public API. */
+StreamBufferHandle_t xStreamBufferGenericCreate( size_t xBufferSizeBytes,
+												 size_t xTriggerLevelBytes,
+												 BaseType_t xIsMessageBuffer ) PRIVILEGED_FUNCTION;
+
+StreamBufferHandle_t xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes,
+													   size_t xTriggerLevelBytes,
+													   BaseType_t xIsMessageBuffer,
+													   uint8_t * const pucStreamBufferStorageArea,
+													   StaticStreamBuffer_t * const pxStaticStreamBuffer ) PRIVILEGED_FUNCTION;
+
+size_t xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+
+#if( configUSE_TRACE_FACILITY == 1 )
+	void vStreamBufferSetStreamBufferNumber( StreamBufferHandle_t xStreamBuffer, UBaseType_t uxStreamBufferNumber ) PRIVILEGED_FUNCTION;
+	UBaseType_t uxStreamBufferGetStreamBufferNumber( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+	uint8_t ucStreamBufferGetStreamBufferType( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+#endif
+
+#if defined( __cplusplus )
+}
+#endif
+
+#endif	/* !defined( STREAM_BUFFER_H ) */
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/task.h b/Middlewares/Third_Party/FreeRTOS/Source/include/task.h
new file mode 100644
index 0000000..b0cc60b
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/include/task.h
@@ -0,0 +1,2543 @@
+/*
+ * FreeRTOS Kernel V10.3.1
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef INC_TASK_H
+#define INC_TASK_H
+
+#ifndef INC_FREERTOS_H
+	#error "include FreeRTOS.h must appear in source files before include task.h"
+#endif
+
+#include "list.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * MACROS AND DEFINITIONS
+ *----------------------------------------------------------*/
+
+#define tskKERNEL_VERSION_NUMBER "V10.3.1"
+#define tskKERNEL_VERSION_MAJOR 10
+#define tskKERNEL_VERSION_MINOR 3
+#define tskKERNEL_VERSION_BUILD 1
+
+/* MPU region parameters passed in ulParameters
+ * of MemoryRegion_t struct. */
+#define tskMPU_REGION_READ_ONLY			( 1UL << 0UL )
+#define tskMPU_REGION_READ_WRITE		( 1UL << 1UL )
+#define tskMPU_REGION_EXECUTE_NEVER		( 1UL << 2UL )
+#define tskMPU_REGION_NORMAL_MEMORY		( 1UL << 3UL )
+#define tskMPU_REGION_DEVICE_MEMORY		( 1UL << 4UL )
+
+/**
+ * task. h
+ *
+ * Type by which tasks are referenced.  For example, a call to xTaskCreate
+ * returns (via a pointer parameter) an TaskHandle_t variable that can then
+ * be used as a parameter to vTaskDelete to delete the task.
+ *
+ * \defgroup TaskHandle_t TaskHandle_t
+ * \ingroup Tasks
+ */
+struct tskTaskControlBlock; /* The old naming convention is used to prevent breaking kernel aware debuggers. */
+typedef struct tskTaskControlBlock* TaskHandle_t;
+
+/*
+ * Defines the prototype to which the application task hook function must
+ * conform.
+ */
+typedef BaseType_t (*TaskHookFunction_t)( void * );
+
+/* Task states returned by eTaskGetState. */
+typedef enum
+{
+	eRunning = 0,	/* A task is querying the state of itself, so must be running. */
+	eReady,			/* The task being queried is in a read or pending ready list. */
+	eBlocked,		/* The task being queried is in the Blocked state. */
+	eSuspended,		/* The task being queried is in the Suspended state, or is in the Blocked state with an infinite time out. */
+	eDeleted,		/* The task being queried has been deleted, but its TCB has not yet been freed. */
+	eInvalid		/* Used as an 'invalid state' value. */
+} eTaskState;
+
+/* Actions that can be performed when vTaskNotify() is called. */
+typedef enum
+{
+	eNoAction = 0,				/* Notify the task without updating its notify value. */
+	eSetBits,					/* Set bits in the task's notification value. */
+	eIncrement,					/* Increment the task's notification value. */
+	eSetValueWithOverwrite,		/* Set the task's notification value to a specific value even if the previous value has not yet been read by the task. */
+	eSetValueWithoutOverwrite	/* Set the task's notification value if the previous value has been read by the task. */
+} eNotifyAction;
+
+/*
+ * Used internally only.
+ */
+typedef struct xTIME_OUT
+{
+	BaseType_t xOverflowCount;
+	TickType_t xTimeOnEntering;
+} TimeOut_t;
+
+/*
+ * Defines the memory ranges allocated to the task when an MPU is used.
+ */
+typedef struct xMEMORY_REGION
+{
+	void *pvBaseAddress;
+	uint32_t ulLengthInBytes;
+	uint32_t ulParameters;
+} MemoryRegion_t;
+
+/*
+ * Parameters required to create an MPU protected task.
+ */
+typedef struct xTASK_PARAMETERS
+{
+	TaskFunction_t pvTaskCode;
+	const char * const pcName;	/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+	configSTACK_DEPTH_TYPE usStackDepth;
+	void *pvParameters;
+	UBaseType_t uxPriority;
+	StackType_t *puxStackBuffer;
+	MemoryRegion_t xRegions[ portNUM_CONFIGURABLE_REGIONS ];
+	#if ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
+		StaticTask_t * const pxTaskBuffer;
+	#endif
+} TaskParameters_t;
+
+/* Used with the uxTaskGetSystemState() function to return the state of each task
+in the system. */
+typedef struct xTASK_STATUS
+{
+	TaskHandle_t xHandle;			/* The handle of the task to which the rest of the information in the structure relates. */
+	const char *pcTaskName;			/* A pointer to the task's name.  This value will be invalid if the task was deleted since the structure was populated! */ /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+	UBaseType_t xTaskNumber;		/* A number unique to the task. */
+	eTaskState eCurrentState;		/* The state in which the task existed when the structure was populated. */
+	UBaseType_t uxCurrentPriority;	/* The priority at which the task was running (may be inherited) when the structure was populated. */
+	UBaseType_t uxBasePriority;		/* The priority to which the task will return if the task's current priority has been inherited to avoid unbounded priority inversion when obtaining a mutex.  Only valid if configUSE_MUTEXES is defined as 1 in FreeRTOSConfig.h. */
+	uint32_t ulRunTimeCounter;		/* The total run time allocated to the task so far, as defined by the run time stats clock.  See http://www.freertos.org/rtos-run-time-stats.html.  Only valid when configGENERATE_RUN_TIME_STATS is defined as 1 in FreeRTOSConfig.h. */
+	StackType_t *pxStackBase;		/* Points to the lowest address of the task's stack area. */
+	configSTACK_DEPTH_TYPE usStackHighWaterMark;	/* The minimum amount of stack space that has remained for the task since the task was created.  The closer this value is to zero the closer the task has come to overflowing its stack. */
+} TaskStatus_t;
+
+/* Possible return values for eTaskConfirmSleepModeStatus(). */
+typedef enum
+{
+	eAbortSleep = 0,		/* A task has been made ready or a context switch pended since portSUPPORESS_TICKS_AND_SLEEP() was called - abort entering a sleep mode. */
+	eStandardSleep,			/* Enter a sleep mode that will not last any longer than the expected idle time. */
+	eNoTasksWaitingTimeout	/* No tasks are waiting for a timeout so it is safe to enter a sleep mode that can only be exited by an external interrupt. */
+} eSleepModeStatus;
+
+/**
+ * Defines the priority used by the idle task.  This must not be modified.
+ *
+ * \ingroup TaskUtils
+ */
+#define tskIDLE_PRIORITY			( ( UBaseType_t ) 0U )
+
+/**
+ * task. h
+ *
+ * Macro for forcing a context switch.
+ *
+ * \defgroup taskYIELD taskYIELD
+ * \ingroup SchedulerControl
+ */
+#define taskYIELD()					portYIELD()
+
+/**
+ * task. h
+ *
+ * Macro to mark the start of a critical code region.  Preemptive context
+ * switches cannot occur when in a critical region.
+ *
+ * NOTE: This may alter the stack (depending on the portable implementation)
+ * so must be used with care!
+ *
+ * \defgroup taskENTER_CRITICAL taskENTER_CRITICAL
+ * \ingroup SchedulerControl
+ */
+#define taskENTER_CRITICAL()		portENTER_CRITICAL()
+#define taskENTER_CRITICAL_FROM_ISR() portSET_INTERRUPT_MASK_FROM_ISR()
+
+/**
+ * task. h
+ *
+ * Macro to mark the end of a critical code region.  Preemptive context
+ * switches cannot occur when in a critical region.
+ *
+ * NOTE: This may alter the stack (depending on the portable implementation)
+ * so must be used with care!
+ *
+ * \defgroup taskEXIT_CRITICAL taskEXIT_CRITICAL
+ * \ingroup SchedulerControl
+ */
+#define taskEXIT_CRITICAL()			portEXIT_CRITICAL()
+#define taskEXIT_CRITICAL_FROM_ISR( x ) portCLEAR_INTERRUPT_MASK_FROM_ISR( x )
+/**
+ * task. h
+ *
+ * Macro to disable all maskable interrupts.
+ *
+ * \defgroup taskDISABLE_INTERRUPTS taskDISABLE_INTERRUPTS
+ * \ingroup SchedulerControl
+ */
+#define taskDISABLE_INTERRUPTS()	portDISABLE_INTERRUPTS()
+
+/**
+ * task. h
+ *
+ * Macro to enable microcontroller interrupts.
+ *
+ * \defgroup taskENABLE_INTERRUPTS taskENABLE_INTERRUPTS
+ * \ingroup SchedulerControl
+ */
+#define taskENABLE_INTERRUPTS()		portENABLE_INTERRUPTS()
+
+/* Definitions returned by xTaskGetSchedulerState().  taskSCHEDULER_SUSPENDED is
+0 to generate more optimal code when configASSERT() is defined as the constant
+is used in assert() statements. */
+#define taskSCHEDULER_SUSPENDED		( ( BaseType_t ) 0 )
+#define taskSCHEDULER_NOT_STARTED	( ( BaseType_t ) 1 )
+#define taskSCHEDULER_RUNNING		( ( BaseType_t ) 2 )
+
+
+/*-----------------------------------------------------------
+ * TASK CREATION API
+ *----------------------------------------------------------*/
+
+/**
+ * task. h
+ *<pre>
+ BaseType_t xTaskCreate(
+							  TaskFunction_t pvTaskCode,
+							  const char * const pcName,
+							  configSTACK_DEPTH_TYPE usStackDepth,
+							  void *pvParameters,
+							  UBaseType_t uxPriority,
+							  TaskHandle_t *pvCreatedTask
+						  );</pre>
+ *
+ * Create a new task and add it to the list of tasks that are ready to run.
+ *
+ * Internally, within the FreeRTOS implementation, tasks use two blocks of
+ * memory.  The first block is used to hold the task's data structures.  The
+ * second block is used by the task as its stack.  If a task is created using
+ * xTaskCreate() then both blocks of memory are automatically dynamically
+ * allocated inside the xTaskCreate() function.  (see
+ * http://www.freertos.org/a00111.html).  If a task is created using
+ * xTaskCreateStatic() then the application writer must provide the required
+ * memory.  xTaskCreateStatic() therefore allows a task to be created without
+ * using any dynamic memory allocation.
+ *
+ * See xTaskCreateStatic() for a version that does not use any dynamic memory
+ * allocation.
+ *
+ * xTaskCreate() can only be used to create a task that has unrestricted
+ * access to the entire microcontroller memory map.  Systems that include MPU
+ * support can alternatively create an MPU constrained task using
+ * xTaskCreateRestricted().
+ *
+ * @param pvTaskCode Pointer to the task entry function.  Tasks
+ * must be implemented to never return (i.e. continuous loop).
+ *
+ * @param pcName A descriptive name for the task.  This is mainly used to
+ * facilitate debugging.  Max length defined by configMAX_TASK_NAME_LEN - default
+ * is 16.
+ *
+ * @param usStackDepth The size of the task stack specified as the number of
+ * variables the stack can hold - not the number of bytes.  For example, if
+ * the stack is 16 bits wide and usStackDepth is defined as 100, 200 bytes
+ * will be allocated for stack storage.
+ *
+ * @param pvParameters Pointer that will be used as the parameter for the task
+ * being created.
+ *
+ * @param uxPriority The priority at which the task should run.  Systems that
+ * include MPU support can optionally create tasks in a privileged (system)
+ * mode by setting bit portPRIVILEGE_BIT of the priority parameter.  For
+ * example, to create a privileged task at priority 2 the uxPriority parameter
+ * should be set to ( 2 | portPRIVILEGE_BIT ).
+ *
+ * @param pvCreatedTask Used to pass back a handle by which the created task
+ * can be referenced.
+ *
+ * @return pdPASS if the task was successfully created and added to a ready
+ * list, otherwise an error code defined in the file projdefs.h
+ *
+ * Example usage:
+   <pre>
+ // Task to be created.
+ void vTaskCode( void * pvParameters )
+ {
+	 for( ;; )
+	 {
+		 // Task code goes here.
+	 }
+ }
+
+ // Function that creates a task.
+ void vOtherFunction( void )
+ {
+ static uint8_t ucParameterToPass;
+ TaskHandle_t xHandle = NULL;
+
+	 // Create the task, storing the handle.  Note that the passed parameter ucParameterToPass
+	 // must exist for the lifetime of the task, so in this case is declared static.  If it was just an
+	 // an automatic stack variable it might no longer exist, or at least have been corrupted, by the time
+	 // the new task attempts to access it.
+	 xTaskCreate( vTaskCode, "NAME", STACK_SIZE, &ucParameterToPass, tskIDLE_PRIORITY, &xHandle );
+	 configASSERT( xHandle );
+
+	 // Use the handle to delete the task.
+	 if( xHandle != NULL )
+	 {
+	 	vTaskDelete( xHandle );
+	 }
+ }
+   </pre>
+ * \defgroup xTaskCreate xTaskCreate
+ * \ingroup Tasks
+ */
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+	BaseType_t xTaskCreate(	TaskFunction_t pxTaskCode,
+							const char * const pcName,	/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+							const configSTACK_DEPTH_TYPE usStackDepth,
+							void * const pvParameters,
+							UBaseType_t uxPriority,
+							TaskHandle_t * const pxCreatedTask ) PRIVILEGED_FUNCTION;
+#endif
+
+/**
+ * task. h
+ *<pre>
+ TaskHandle_t xTaskCreateStatic( TaskFunction_t pvTaskCode,
+								 const char * const pcName,
+								 uint32_t ulStackDepth,
+								 void *pvParameters,
+								 UBaseType_t uxPriority,
+								 StackType_t *pxStackBuffer,
+								 StaticTask_t *pxTaskBuffer );</pre>
+ *
+ * Create a new task and add it to the list of tasks that are ready to run.
+ *
+ * Internally, within the FreeRTOS implementation, tasks use two blocks of
+ * memory.  The first block is used to hold the task's data structures.  The
+ * second block is used by the task as its stack.  If a task is created using
+ * xTaskCreate() then both blocks of memory are automatically dynamically
+ * allocated inside the xTaskCreate() function.  (see
+ * http://www.freertos.org/a00111.html).  If a task is created using
+ * xTaskCreateStatic() then the application writer must provide the required
+ * memory.  xTaskCreateStatic() therefore allows a task to be created without
+ * using any dynamic memory allocation.
+ *
+ * @param pvTaskCode Pointer to the task entry function.  Tasks
+ * must be implemented to never return (i.e. continuous loop).
+ *
+ * @param pcName A descriptive name for the task.  This is mainly used to
+ * facilitate debugging.  The maximum length of the string is defined by
+ * configMAX_TASK_NAME_LEN in FreeRTOSConfig.h.
+ *
+ * @param ulStackDepth The size of the task stack specified as the number of
+ * variables the stack can hold - not the number of bytes.  For example, if
+ * the stack is 32-bits wide and ulStackDepth is defined as 100 then 400 bytes
+ * will be allocated for stack storage.
+ *
+ * @param pvParameters Pointer that will be used as the parameter for the task
+ * being created.
+ *
+ * @param uxPriority The priority at which the task will run.
+ *
+ * @param pxStackBuffer Must point to a StackType_t array that has at least
+ * ulStackDepth indexes - the array will then be used as the task's stack,
+ * removing the need for the stack to be allocated dynamically.
+ *
+ * @param pxTaskBuffer Must point to a variable of type StaticTask_t, which will
+ * then be used to hold the task's data structures, removing the need for the
+ * memory to be allocated dynamically.
+ *
+ * @return If neither pxStackBuffer or pxTaskBuffer are NULL, then the task will
+ * be created and a handle to the created task is returned.  If either
+ * pxStackBuffer or pxTaskBuffer are NULL then the task will not be created and
+ * NULL is returned.
+ *
+ * Example usage:
+   <pre>
+
+    // Dimensions the buffer that the task being created will use as its stack.
+    // NOTE:  This is the number of words the stack will hold, not the number of
+    // bytes.  For example, if each stack item is 32-bits, and this is set to 100,
+    // then 400 bytes (100 * 32-bits) will be allocated.
+    #define STACK_SIZE 200
+
+    // Structure that will hold the TCB of the task being created.
+    StaticTask_t xTaskBuffer;
+
+    // Buffer that the task being created will use as its stack.  Note this is
+    // an array of StackType_t variables.  The size of StackType_t is dependent on
+    // the RTOS port.
+    StackType_t xStack[ STACK_SIZE ];
+
+    // Function that implements the task being created.
+    void vTaskCode( void * pvParameters )
+    {
+        // The parameter value is expected to be 1 as 1 is passed in the
+        // pvParameters value in the call to xTaskCreateStatic().
+        configASSERT( ( uint32_t ) pvParameters == 1UL );
+
+        for( ;; )
+        {
+            // Task code goes here.
+        }
+    }
+
+    // Function that creates a task.
+    void vOtherFunction( void )
+    {
+        TaskHandle_t xHandle = NULL;
+
+        // Create the task without using any dynamic memory allocation.
+        xHandle = xTaskCreateStatic(
+                      vTaskCode,       // Function that implements the task.
+                      "NAME",          // Text name for the task.
+                      STACK_SIZE,      // Stack size in words, not bytes.
+                      ( void * ) 1,    // Parameter passed into the task.
+                      tskIDLE_PRIORITY,// Priority at which the task is created.
+                      xStack,          // Array to use as the task's stack.
+                      &xTaskBuffer );  // Variable to hold the task's data structure.
+
+        // puxStackBuffer and pxTaskBuffer were not NULL, so the task will have
+        // been created, and xHandle will be the task's handle.  Use the handle
+        // to suspend the task.
+        vTaskSuspend( xHandle );
+    }
+   </pre>
+ * \defgroup xTaskCreateStatic xTaskCreateStatic
+ * \ingroup Tasks
+ */
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+	TaskHandle_t xTaskCreateStatic(	TaskFunction_t pxTaskCode,
+									const char * const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+									const uint32_t ulStackDepth,
+									void * const pvParameters,
+									UBaseType_t uxPriority,
+									StackType_t * const puxStackBuffer,
+									StaticTask_t * const pxTaskBuffer ) PRIVILEGED_FUNCTION;
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+/**
+ * task. h
+ *<pre>
+ BaseType_t xTaskCreateRestricted( TaskParameters_t *pxTaskDefinition, TaskHandle_t *pxCreatedTask );</pre>
+ *
+ * Only available when configSUPPORT_DYNAMIC_ALLOCATION is set to 1.
+ *
+ * xTaskCreateRestricted() should only be used in systems that include an MPU
+ * implementation.
+ *
+ * Create a new task and add it to the list of tasks that are ready to run.
+ * The function parameters define the memory regions and associated access
+ * permissions allocated to the task.
+ *
+ * See xTaskCreateRestrictedStatic() for a version that does not use any
+ * dynamic memory allocation.
+ *
+ * @param pxTaskDefinition Pointer to a structure that contains a member
+ * for each of the normal xTaskCreate() parameters (see the xTaskCreate() API
+ * documentation) plus an optional stack buffer and the memory region
+ * definitions.
+ *
+ * @param pxCreatedTask Used to pass back a handle by which the created task
+ * can be referenced.
+ *
+ * @return pdPASS if the task was successfully created and added to a ready
+ * list, otherwise an error code defined in the file projdefs.h
+ *
+ * Example usage:
+   <pre>
+// Create an TaskParameters_t structure that defines the task to be created.
+static const TaskParameters_t xCheckTaskParameters =
+{
+	vATask,		// pvTaskCode - the function that implements the task.
+	"ATask",	// pcName - just a text name for the task to assist debugging.
+	100,		// usStackDepth	- the stack size DEFINED IN WORDS.
+	NULL,		// pvParameters - passed into the task function as the function parameters.
+	( 1UL | portPRIVILEGE_BIT ),// uxPriority - task priority, set the portPRIVILEGE_BIT if the task should run in a privileged state.
+	cStackBuffer,// puxStackBuffer - the buffer to be used as the task stack.
+
+	// xRegions - Allocate up to three separate memory regions for access by
+	// the task, with appropriate access permissions.  Different processors have
+	// different memory alignment requirements - refer to the FreeRTOS documentation
+	// for full information.
+	{
+		// Base address					Length	Parameters
+		{ cReadWriteArray,				32,		portMPU_REGION_READ_WRITE },
+		{ cReadOnlyArray,				32,		portMPU_REGION_READ_ONLY },
+		{ cPrivilegedOnlyAccessArray,	128,	portMPU_REGION_PRIVILEGED_READ_WRITE }
+	}
+};
+
+int main( void )
+{
+TaskHandle_t xHandle;
+
+	// Create a task from the const structure defined above.  The task handle
+	// is requested (the second parameter is not NULL) but in this case just for
+	// demonstration purposes as its not actually used.
+	xTaskCreateRestricted( &xRegTest1Parameters, &xHandle );
+
+	// Start the scheduler.
+	vTaskStartScheduler();
+
+	// Will only get here if there was insufficient memory to create the idle
+	// and/or timer task.
+	for( ;; );
+}
+   </pre>
+ * \defgroup xTaskCreateRestricted xTaskCreateRestricted
+ * \ingroup Tasks
+ */
+#if( portUSING_MPU_WRAPPERS == 1 )
+	BaseType_t xTaskCreateRestricted( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask ) PRIVILEGED_FUNCTION;
+#endif
+
+/**
+ * task. h
+ *<pre>
+ BaseType_t xTaskCreateRestrictedStatic( TaskParameters_t *pxTaskDefinition, TaskHandle_t *pxCreatedTask );</pre>
+ *
+ * Only available when configSUPPORT_STATIC_ALLOCATION is set to 1.
+ *
+ * xTaskCreateRestrictedStatic() should only be used in systems that include an
+ * MPU implementation.
+ *
+ * Internally, within the FreeRTOS implementation, tasks use two blocks of
+ * memory.  The first block is used to hold the task's data structures.  The
+ * second block is used by the task as its stack.  If a task is created using
+ * xTaskCreateRestricted() then the stack is provided by the application writer,
+ * and the memory used to hold the task's data structure is automatically
+ * dynamically allocated inside the xTaskCreateRestricted() function.  If a task
+ * is created using xTaskCreateRestrictedStatic() then the application writer
+ * must provide the memory used to hold the task's data structures too.
+ * xTaskCreateRestrictedStatic() therefore allows a memory protected task to be
+ * created without using any dynamic memory allocation.
+ *
+ * @param pxTaskDefinition Pointer to a structure that contains a member
+ * for each of the normal xTaskCreate() parameters (see the xTaskCreate() API
+ * documentation) plus an optional stack buffer and the memory region
+ * definitions.  If configSUPPORT_STATIC_ALLOCATION is set to 1 the structure
+ * contains an additional member, which is used to point to a variable of type
+ * StaticTask_t - which is then used to hold the task's data structure.
+ *
+ * @param pxCreatedTask Used to pass back a handle by which the created task
+ * can be referenced.
+ *
+ * @return pdPASS if the task was successfully created and added to a ready
+ * list, otherwise an error code defined in the file projdefs.h
+ *
+ * Example usage:
+   <pre>
+// Create an TaskParameters_t structure that defines the task to be created.
+// The StaticTask_t variable is only included in the structure when
+// configSUPPORT_STATIC_ALLOCATION is set to 1.  The PRIVILEGED_DATA macro can
+// be used to force the variable into the RTOS kernel's privileged data area.
+static PRIVILEGED_DATA StaticTask_t xTaskBuffer;
+static const TaskParameters_t xCheckTaskParameters =
+{
+	vATask,		// pvTaskCode - the function that implements the task.
+	"ATask",	// pcName - just a text name for the task to assist debugging.
+	100,		// usStackDepth	- the stack size DEFINED IN WORDS.
+	NULL,		// pvParameters - passed into the task function as the function parameters.
+	( 1UL | portPRIVILEGE_BIT ),// uxPriority - task priority, set the portPRIVILEGE_BIT if the task should run in a privileged state.
+	cStackBuffer,// puxStackBuffer - the buffer to be used as the task stack.
+
+	// xRegions - Allocate up to three separate memory regions for access by
+	// the task, with appropriate access permissions.  Different processors have
+	// different memory alignment requirements - refer to the FreeRTOS documentation
+	// for full information.
+	{
+		// Base address					Length	Parameters
+		{ cReadWriteArray,				32,		portMPU_REGION_READ_WRITE },
+		{ cReadOnlyArray,				32,		portMPU_REGION_READ_ONLY },
+		{ cPrivilegedOnlyAccessArray,	128,	portMPU_REGION_PRIVILEGED_READ_WRITE }
+	}
+
+	&xTaskBuffer; // Holds the task's data structure.
+};
+
+int main( void )
+{
+TaskHandle_t xHandle;
+
+	// Create a task from the const structure defined above.  The task handle
+	// is requested (the second parameter is not NULL) but in this case just for
+	// demonstration purposes as its not actually used.
+	xTaskCreateRestricted( &xRegTest1Parameters, &xHandle );
+
+	// Start the scheduler.
+	vTaskStartScheduler();
+
+	// Will only get here if there was insufficient memory to create the idle
+	// and/or timer task.
+	for( ;; );
+}
+   </pre>
+ * \defgroup xTaskCreateRestrictedStatic xTaskCreateRestrictedStatic
+ * \ingroup Tasks
+ */
+#if( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
+	BaseType_t xTaskCreateRestrictedStatic( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask ) PRIVILEGED_FUNCTION;
+#endif
+
+/**
+ * task. h
+ *<pre>
+ void vTaskAllocateMPURegions( TaskHandle_t xTask, const MemoryRegion_t * const pxRegions );</pre>
+ *
+ * Memory regions are assigned to a restricted task when the task is created by
+ * a call to xTaskCreateRestricted().  These regions can be redefined using
+ * vTaskAllocateMPURegions().
+ *
+ * @param xTask The handle of the task being updated.
+ *
+ * @param xRegions A pointer to an MemoryRegion_t structure that contains the
+ * new memory region definitions.
+ *
+ * Example usage:
+   <pre>
+// Define an array of MemoryRegion_t structures that configures an MPU region
+// allowing read/write access for 1024 bytes starting at the beginning of the
+// ucOneKByte array.  The other two of the maximum 3 definable regions are
+// unused so set to zero.
+static const MemoryRegion_t xAltRegions[ portNUM_CONFIGURABLE_REGIONS ] =
+{
+	// Base address		Length		Parameters
+	{ ucOneKByte,		1024,		portMPU_REGION_READ_WRITE },
+	{ 0,				0,			0 },
+	{ 0,				0,			0 }
+};
+
+void vATask( void *pvParameters )
+{
+	// This task was created such that it has access to certain regions of
+	// memory as defined by the MPU configuration.  At some point it is
+	// desired that these MPU regions are replaced with that defined in the
+	// xAltRegions const struct above.  Use a call to vTaskAllocateMPURegions()
+	// for this purpose.  NULL is used as the task handle to indicate that this
+	// function should modify the MPU regions of the calling task.
+	vTaskAllocateMPURegions( NULL, xAltRegions );
+
+	// Now the task can continue its function, but from this point on can only
+	// access its stack and the ucOneKByte array (unless any other statically
+	// defined or shared regions have been declared elsewhere).
+}
+   </pre>
+ * \defgroup xTaskCreateRestricted xTaskCreateRestricted
+ * \ingroup Tasks
+ */
+void vTaskAllocateMPURegions( TaskHandle_t xTask, const MemoryRegion_t * const pxRegions ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * <pre>void vTaskDelete( TaskHandle_t xTask );</pre>
+ *
+ * INCLUDE_vTaskDelete must be defined as 1 for this function to be available.
+ * See the configuration section for more information.
+ *
+ * Remove a task from the RTOS real time kernel's management.  The task being
+ * deleted will be removed from all ready, blocked, suspended and event lists.
+ *
+ * NOTE:  The idle task is responsible for freeing the kernel allocated
+ * memory from tasks that have been deleted.  It is therefore important that
+ * the idle task is not starved of microcontroller processing time if your
+ * application makes any calls to vTaskDelete ().  Memory allocated by the
+ * task code is not automatically freed, and should be freed before the task
+ * is deleted.
+ *
+ * See the demo application file death.c for sample code that utilises
+ * vTaskDelete ().
+ *
+ * @param xTask The handle of the task to be deleted.  Passing NULL will
+ * cause the calling task to be deleted.
+ *
+ * Example usage:
+   <pre>
+ void vOtherFunction( void )
+ {
+ TaskHandle_t xHandle;
+
+	 // Create the task, storing the handle.
+	 xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
+
+	 // Use the handle to delete the task.
+	 vTaskDelete( xHandle );
+ }
+   </pre>
+ * \defgroup vTaskDelete vTaskDelete
+ * \ingroup Tasks
+ */
+void vTaskDelete( TaskHandle_t xTaskToDelete ) PRIVILEGED_FUNCTION;
+
+/*-----------------------------------------------------------
+ * TASK CONTROL API
+ *----------------------------------------------------------*/
+
+/**
+ * task. h
+ * <pre>void vTaskDelay( const TickType_t xTicksToDelay );</pre>
+ *
+ * Delay a task for a given number of ticks.  The actual time that the
+ * task remains blocked depends on the tick rate.  The constant
+ * portTICK_PERIOD_MS can be used to calculate real time from the tick
+ * rate - with the resolution of one tick period.
+ *
+ * INCLUDE_vTaskDelay must be defined as 1 for this function to be available.
+ * See the configuration section for more information.
+ *
+ *
+ * vTaskDelay() specifies a time at which the task wishes to unblock relative to
+ * the time at which vTaskDelay() is called.  For example, specifying a block
+ * period of 100 ticks will cause the task to unblock 100 ticks after
+ * vTaskDelay() is called.  vTaskDelay() does not therefore provide a good method
+ * of controlling the frequency of a periodic task as the path taken through the
+ * code, as well as other task and interrupt activity, will effect the frequency
+ * at which vTaskDelay() gets called and therefore the time at which the task
+ * next executes.  See vTaskDelayUntil() for an alternative API function designed
+ * to facilitate fixed frequency execution.  It does this by specifying an
+ * absolute time (rather than a relative time) at which the calling task should
+ * unblock.
+ *
+ * @param xTicksToDelay The amount of time, in tick periods, that
+ * the calling task should block.
+ *
+ * Example usage:
+
+ void vTaskFunction( void * pvParameters )
+ {
+ // Block for 500ms.
+ const TickType_t xDelay = 500 / portTICK_PERIOD_MS;
+
+	 for( ;; )
+	 {
+		 // Simply toggle the LED every 500ms, blocking between each toggle.
+		 vToggleLED();
+		 vTaskDelay( xDelay );
+	 }
+ }
+
+ * \defgroup vTaskDelay vTaskDelay
+ * \ingroup TaskCtrl
+ */
+void vTaskDelay( const TickType_t xTicksToDelay ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * <pre>void vTaskDelayUntil( TickType_t *pxPreviousWakeTime, const TickType_t xTimeIncrement );</pre>
+ *
+ * INCLUDE_vTaskDelayUntil must be defined as 1 for this function to be available.
+ * See the configuration section for more information.
+ *
+ * Delay a task until a specified time.  This function can be used by periodic
+ * tasks to ensure a constant execution frequency.
+ *
+ * This function differs from vTaskDelay () in one important aspect:  vTaskDelay () will
+ * cause a task to block for the specified number of ticks from the time vTaskDelay () is
+ * called.  It is therefore difficult to use vTaskDelay () by itself to generate a fixed
+ * execution frequency as the time between a task starting to execute and that task
+ * calling vTaskDelay () may not be fixed [the task may take a different path though the
+ * code between calls, or may get interrupted or preempted a different number of times
+ * each time it executes].
+ *
+ * Whereas vTaskDelay () specifies a wake time relative to the time at which the function
+ * is called, vTaskDelayUntil () specifies the absolute (exact) time at which it wishes to
+ * unblock.
+ *
+ * The constant portTICK_PERIOD_MS can be used to calculate real time from the tick
+ * rate - with the resolution of one tick period.
+ *
+ * @param pxPreviousWakeTime Pointer to a variable that holds the time at which the
+ * task was last unblocked.  The variable must be initialised with the current time
+ * prior to its first use (see the example below).  Following this the variable is
+ * automatically updated within vTaskDelayUntil ().
+ *
+ * @param xTimeIncrement The cycle time period.  The task will be unblocked at
+ * time *pxPreviousWakeTime + xTimeIncrement.  Calling vTaskDelayUntil with the
+ * same xTimeIncrement parameter value will cause the task to execute with
+ * a fixed interface period.
+ *
+ * Example usage:
+   <pre>
+ // Perform an action every 10 ticks.
+ void vTaskFunction( void * pvParameters )
+ {
+ TickType_t xLastWakeTime;
+ const TickType_t xFrequency = 10;
+
+	 // Initialise the xLastWakeTime variable with the current time.
+	 xLastWakeTime = xTaskGetTickCount ();
+	 for( ;; )
+	 {
+		 // Wait for the next cycle.
+		 vTaskDelayUntil( &xLastWakeTime, xFrequency );
+
+		 // Perform action here.
+	 }
+ }
+   </pre>
+ * \defgroup vTaskDelayUntil vTaskDelayUntil
+ * \ingroup TaskCtrl
+ */
+void vTaskDelayUntil( TickType_t * const pxPreviousWakeTime, const TickType_t xTimeIncrement ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * <pre>BaseType_t xTaskAbortDelay( TaskHandle_t xTask );</pre>
+ *
+ * INCLUDE_xTaskAbortDelay must be defined as 1 in FreeRTOSConfig.h for this
+ * function to be available.
+ *
+ * A task will enter the Blocked state when it is waiting for an event.  The
+ * event it is waiting for can be a temporal event (waiting for a time), such
+ * as when vTaskDelay() is called, or an event on an object, such as when
+ * xQueueReceive() or ulTaskNotifyTake() is called.  If the handle of a task
+ * that is in the Blocked state is used in a call to xTaskAbortDelay() then the
+ * task will leave the Blocked state, and return from whichever function call
+ * placed the task into the Blocked state.
+ *
+ * There is no 'FromISR' version of this function as an interrupt would need to
+ * know which object a task was blocked on in order to know which actions to
+ * take.  For example, if the task was blocked on a queue the interrupt handler
+ * would then need to know if the queue was locked.
+ *
+ * @param xTask The handle of the task to remove from the Blocked state.
+ *
+ * @return If the task referenced by xTask was not in the Blocked state then
+ * pdFAIL is returned.  Otherwise pdPASS is returned.
+ *
+ * \defgroup xTaskAbortDelay xTaskAbortDelay
+ * \ingroup TaskCtrl
+ */
+BaseType_t xTaskAbortDelay( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * <pre>UBaseType_t uxTaskPriorityGet( const TaskHandle_t xTask );</pre>
+ *
+ * INCLUDE_uxTaskPriorityGet must be defined as 1 for this function to be available.
+ * See the configuration section for more information.
+ *
+ * Obtain the priority of any task.
+ *
+ * @param xTask Handle of the task to be queried.  Passing a NULL
+ * handle results in the priority of the calling task being returned.
+ *
+ * @return The priority of xTask.
+ *
+ * Example usage:
+   <pre>
+ void vAFunction( void )
+ {
+ TaskHandle_t xHandle;
+
+	 // Create a task, storing the handle.
+	 xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
+
+	 // ...
+
+	 // Use the handle to obtain the priority of the created task.
+	 // It was created with tskIDLE_PRIORITY, but may have changed
+	 // it itself.
+	 if( uxTaskPriorityGet( xHandle ) != tskIDLE_PRIORITY )
+	 {
+		 // The task has changed it's priority.
+	 }
+
+	 // ...
+
+	 // Is our priority higher than the created task?
+	 if( uxTaskPriorityGet( xHandle ) < uxTaskPriorityGet( NULL ) )
+	 {
+		 // Our priority (obtained using NULL handle) is higher.
+	 }
+ }
+   </pre>
+ * \defgroup uxTaskPriorityGet uxTaskPriorityGet
+ * \ingroup TaskCtrl
+ */
+UBaseType_t uxTaskPriorityGet( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * <pre>UBaseType_t uxTaskPriorityGetFromISR( const TaskHandle_t xTask );</pre>
+ *
+ * A version of uxTaskPriorityGet() that can be used from an ISR.
+ */
+UBaseType_t uxTaskPriorityGetFromISR( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * <pre>eTaskState eTaskGetState( TaskHandle_t xTask );</pre>
+ *
+ * INCLUDE_eTaskGetState must be defined as 1 for this function to be available.
+ * See the configuration section for more information.
+ *
+ * Obtain the state of any task.  States are encoded by the eTaskState
+ * enumerated type.
+ *
+ * @param xTask Handle of the task to be queried.
+ *
+ * @return The state of xTask at the time the function was called.  Note the
+ * state of the task might change between the function being called, and the
+ * functions return value being tested by the calling task.
+ */
+eTaskState eTaskGetState( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * <pre>void vTaskGetInfo( TaskHandle_t xTask, TaskStatus_t *pxTaskStatus, BaseType_t xGetFreeStackSpace, eTaskState eState );</pre>
+ *
+ * configUSE_TRACE_FACILITY must be defined as 1 for this function to be
+ * available.  See the configuration section for more information.
+ *
+ * Populates a TaskStatus_t structure with information about a task.
+ *
+ * @param xTask Handle of the task being queried.  If xTask is NULL then
+ * information will be returned about the calling task.
+ *
+ * @param pxTaskStatus A pointer to the TaskStatus_t structure that will be
+ * filled with information about the task referenced by the handle passed using
+ * the xTask parameter.
+ *
+ * @xGetFreeStackSpace The TaskStatus_t structure contains a member to report
+ * the stack high water mark of the task being queried.  Calculating the stack
+ * high water mark takes a relatively long time, and can make the system
+ * temporarily unresponsive - so the xGetFreeStackSpace parameter is provided to
+ * allow the high water mark checking to be skipped.  The high watermark value
+ * will only be written to the TaskStatus_t structure if xGetFreeStackSpace is
+ * not set to pdFALSE;
+ *
+ * @param eState The TaskStatus_t structure contains a member to report the
+ * state of the task being queried.  Obtaining the task state is not as fast as
+ * a simple assignment - so the eState parameter is provided to allow the state
+ * information to be omitted from the TaskStatus_t structure.  To obtain state
+ * information then set eState to eInvalid - otherwise the value passed in
+ * eState will be reported as the task state in the TaskStatus_t structure.
+ *
+ * Example usage:
+   <pre>
+ void vAFunction( void )
+ {
+ TaskHandle_t xHandle;
+ TaskStatus_t xTaskDetails;
+
+    // Obtain the handle of a task from its name.
+    xHandle = xTaskGetHandle( "Task_Name" );
+
+    // Check the handle is not NULL.
+    configASSERT( xHandle );
+
+    // Use the handle to obtain further information about the task.
+    vTaskGetInfo( xHandle,
+                  &xTaskDetails,
+                  pdTRUE, // Include the high water mark in xTaskDetails.
+                  eInvalid ); // Include the task state in xTaskDetails.
+ }
+   </pre>
+ * \defgroup vTaskGetInfo vTaskGetInfo
+ * \ingroup TaskCtrl
+ */
+void vTaskGetInfo( TaskHandle_t xTask, TaskStatus_t *pxTaskStatus, BaseType_t xGetFreeStackSpace, eTaskState eState ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * <pre>void vTaskPrioritySet( TaskHandle_t xTask, UBaseType_t uxNewPriority );</pre>
+ *
+ * INCLUDE_vTaskPrioritySet must be defined as 1 for this function to be available.
+ * See the configuration section for more information.
+ *
+ * Set the priority of any task.
+ *
+ * A context switch will occur before the function returns if the priority
+ * being set is higher than the currently executing task.
+ *
+ * @param xTask Handle to the task for which the priority is being set.
+ * Passing a NULL handle results in the priority of the calling task being set.
+ *
+ * @param uxNewPriority The priority to which the task will be set.
+ *
+ * Example usage:
+   <pre>
+ void vAFunction( void )
+ {
+ TaskHandle_t xHandle;
+
+	 // Create a task, storing the handle.
+	 xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
+
+	 // ...
+
+	 // Use the handle to raise the priority of the created task.
+	 vTaskPrioritySet( xHandle, tskIDLE_PRIORITY + 1 );
+
+	 // ...
+
+	 // Use a NULL handle to raise our priority to the same value.
+	 vTaskPrioritySet( NULL, tskIDLE_PRIORITY + 1 );
+ }
+   </pre>
+ * \defgroup vTaskPrioritySet vTaskPrioritySet
+ * \ingroup TaskCtrl
+ */
+void vTaskPrioritySet( TaskHandle_t xTask, UBaseType_t uxNewPriority ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * <pre>void vTaskSuspend( TaskHandle_t xTaskToSuspend );</pre>
+ *
+ * INCLUDE_vTaskSuspend must be defined as 1 for this function to be available.
+ * See the configuration section for more information.
+ *
+ * Suspend any task.  When suspended a task will never get any microcontroller
+ * processing time, no matter what its priority.
+ *
+ * Calls to vTaskSuspend are not accumulative -
+ * i.e. calling vTaskSuspend () twice on the same task still only requires one
+ * call to vTaskResume () to ready the suspended task.
+ *
+ * @param xTaskToSuspend Handle to the task being suspended.  Passing a NULL
+ * handle will cause the calling task to be suspended.
+ *
+ * Example usage:
+   <pre>
+ void vAFunction( void )
+ {
+ TaskHandle_t xHandle;
+
+	 // Create a task, storing the handle.
+	 xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
+
+	 // ...
+
+	 // Use the handle to suspend the created task.
+	 vTaskSuspend( xHandle );
+
+	 // ...
+
+	 // The created task will not run during this period, unless
+	 // another task calls vTaskResume( xHandle ).
+
+	 //...
+
+
+	 // Suspend ourselves.
+	 vTaskSuspend( NULL );
+
+	 // We cannot get here unless another task calls vTaskResume
+	 // with our handle as the parameter.
+ }
+   </pre>
+ * \defgroup vTaskSuspend vTaskSuspend
+ * \ingroup TaskCtrl
+ */
+void vTaskSuspend( TaskHandle_t xTaskToSuspend ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * <pre>void vTaskResume( TaskHandle_t xTaskToResume );</pre>
+ *
+ * INCLUDE_vTaskSuspend must be defined as 1 for this function to be available.
+ * See the configuration section for more information.
+ *
+ * Resumes a suspended task.
+ *
+ * A task that has been suspended by one or more calls to vTaskSuspend ()
+ * will be made available for running again by a single call to
+ * vTaskResume ().
+ *
+ * @param xTaskToResume Handle to the task being readied.
+ *
+ * Example usage:
+   <pre>
+ void vAFunction( void )
+ {
+ TaskHandle_t xHandle;
+
+	 // Create a task, storing the handle.
+	 xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
+
+	 // ...
+
+	 // Use the handle to suspend the created task.
+	 vTaskSuspend( xHandle );
+
+	 // ...
+
+	 // The created task will not run during this period, unless
+	 // another task calls vTaskResume( xHandle ).
+
+	 //...
+
+
+	 // Resume the suspended task ourselves.
+	 vTaskResume( xHandle );
+
+	 // The created task will once again get microcontroller processing
+	 // time in accordance with its priority within the system.
+ }
+   </pre>
+ * \defgroup vTaskResume vTaskResume
+ * \ingroup TaskCtrl
+ */
+void vTaskResume( TaskHandle_t xTaskToResume ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * <pre>void xTaskResumeFromISR( TaskHandle_t xTaskToResume );</pre>
+ *
+ * INCLUDE_xTaskResumeFromISR must be defined as 1 for this function to be
+ * available.  See the configuration section for more information.
+ *
+ * An implementation of vTaskResume() that can be called from within an ISR.
+ *
+ * A task that has been suspended by one or more calls to vTaskSuspend ()
+ * will be made available for running again by a single call to
+ * xTaskResumeFromISR ().
+ *
+ * xTaskResumeFromISR() should not be used to synchronise a task with an
+ * interrupt if there is a chance that the interrupt could arrive prior to the
+ * task being suspended - as this can lead to interrupts being missed. Use of a
+ * semaphore as a synchronisation mechanism would avoid this eventuality.
+ *
+ * @param xTaskToResume Handle to the task being readied.
+ *
+ * @return pdTRUE if resuming the task should result in a context switch,
+ * otherwise pdFALSE. This is used by the ISR to determine if a context switch
+ * may be required following the ISR.
+ *
+ * \defgroup vTaskResumeFromISR vTaskResumeFromISR
+ * \ingroup TaskCtrl
+ */
+BaseType_t xTaskResumeFromISR( TaskHandle_t xTaskToResume ) PRIVILEGED_FUNCTION;
+
+/*-----------------------------------------------------------
+ * SCHEDULER CONTROL
+ *----------------------------------------------------------*/
+
+/**
+ * task. h
+ * <pre>void vTaskStartScheduler( void );</pre>
+ *
+ * Starts the real time kernel tick processing.  After calling the kernel
+ * has control over which tasks are executed and when.
+ *
+ * See the demo application file main.c for an example of creating
+ * tasks and starting the kernel.
+ *
+ * Example usage:
+   <pre>
+ void vAFunction( void )
+ {
+	 // Create at least one task before starting the kernel.
+	 xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );
+
+	 // Start the real time kernel with preemption.
+	 vTaskStartScheduler ();
+
+	 // Will not get here unless a task calls vTaskEndScheduler ()
+ }
+   </pre>
+ *
+ * \defgroup vTaskStartScheduler vTaskStartScheduler
+ * \ingroup SchedulerControl
+ */
+void vTaskStartScheduler( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * <pre>void vTaskEndScheduler( void );</pre>
+ *
+ * NOTE:  At the time of writing only the x86 real mode port, which runs on a PC
+ * in place of DOS, implements this function.
+ *
+ * Stops the real time kernel tick.  All created tasks will be automatically
+ * deleted and multitasking (either preemptive or cooperative) will
+ * stop.  Execution then resumes from the point where vTaskStartScheduler ()
+ * was called, as if vTaskStartScheduler () had just returned.
+ *
+ * See the demo application file main. c in the demo/PC directory for an
+ * example that uses vTaskEndScheduler ().
+ *
+ * vTaskEndScheduler () requires an exit function to be defined within the
+ * portable layer (see vPortEndScheduler () in port. c for the PC port).  This
+ * performs hardware specific operations such as stopping the kernel tick.
+ *
+ * vTaskEndScheduler () will cause all of the resources allocated by the
+ * kernel to be freed - but will not free resources allocated by application
+ * tasks.
+ *
+ * Example usage:
+   <pre>
+ void vTaskCode( void * pvParameters )
+ {
+	 for( ;; )
+	 {
+		 // Task code goes here.
+
+		 // At some point we want to end the real time kernel processing
+		 // so call ...
+		 vTaskEndScheduler ();
+	 }
+ }
+
+ void vAFunction( void )
+ {
+	 // Create at least one task before starting the kernel.
+	 xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );
+
+	 // Start the real time kernel with preemption.
+	 vTaskStartScheduler ();
+
+	 // Will only get here when the vTaskCode () task has called
+	 // vTaskEndScheduler ().  When we get here we are back to single task
+	 // execution.
+ }
+   </pre>
+ *
+ * \defgroup vTaskEndScheduler vTaskEndScheduler
+ * \ingroup SchedulerControl
+ */
+void vTaskEndScheduler( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * <pre>void vTaskSuspendAll( void );</pre>
+ *
+ * Suspends the scheduler without disabling interrupts.  Context switches will
+ * not occur while the scheduler is suspended.
+ *
+ * After calling vTaskSuspendAll () the calling task will continue to execute
+ * without risk of being swapped out until a call to xTaskResumeAll () has been
+ * made.
+ *
+ * API functions that have the potential to cause a context switch (for example,
+ * vTaskDelayUntil(), xQueueSend(), etc.) must not be called while the scheduler
+ * is suspended.
+ *
+ * Example usage:
+   <pre>
+ void vTask1( void * pvParameters )
+ {
+	 for( ;; )
+	 {
+		 // Task code goes here.
+
+		 // ...
+
+		 // At some point the task wants to perform a long operation during
+		 // which it does not want to get swapped out.  It cannot use
+		 // taskENTER_CRITICAL ()/taskEXIT_CRITICAL () as the length of the
+		 // operation may cause interrupts to be missed - including the
+		 // ticks.
+
+		 // Prevent the real time kernel swapping out the task.
+		 vTaskSuspendAll ();
+
+		 // Perform the operation here.  There is no need to use critical
+		 // sections as we have all the microcontroller processing time.
+		 // During this time interrupts will still operate and the kernel
+		 // tick count will be maintained.
+
+		 // ...
+
+		 // The operation is complete.  Restart the kernel.
+		 xTaskResumeAll ();
+	 }
+ }
+   </pre>
+ * \defgroup vTaskSuspendAll vTaskSuspendAll
+ * \ingroup SchedulerControl
+ */
+void vTaskSuspendAll( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * <pre>BaseType_t xTaskResumeAll( void );</pre>
+ *
+ * Resumes scheduler activity after it was suspended by a call to
+ * vTaskSuspendAll().
+ *
+ * xTaskResumeAll() only resumes the scheduler.  It does not unsuspend tasks
+ * that were previously suspended by a call to vTaskSuspend().
+ *
+ * @return If resuming the scheduler caused a context switch then pdTRUE is
+ *		  returned, otherwise pdFALSE is returned.
+ *
+ * Example usage:
+   <pre>
+ void vTask1( void * pvParameters )
+ {
+	 for( ;; )
+	 {
+		 // Task code goes here.
+
+		 // ...
+
+		 // At some point the task wants to perform a long operation during
+		 // which it does not want to get swapped out.  It cannot use
+		 // taskENTER_CRITICAL ()/taskEXIT_CRITICAL () as the length of the
+		 // operation may cause interrupts to be missed - including the
+		 // ticks.
+
+		 // Prevent the real time kernel swapping out the task.
+		 vTaskSuspendAll ();
+
+		 // Perform the operation here.  There is no need to use critical
+		 // sections as we have all the microcontroller processing time.
+		 // During this time interrupts will still operate and the real
+		 // time kernel tick count will be maintained.
+
+		 // ...
+
+		 // The operation is complete.  Restart the kernel.  We want to force
+		 // a context switch - but there is no point if resuming the scheduler
+		 // caused a context switch already.
+		 if( !xTaskResumeAll () )
+		 {
+			  taskYIELD ();
+		 }
+	 }
+ }
+   </pre>
+ * \defgroup xTaskResumeAll xTaskResumeAll
+ * \ingroup SchedulerControl
+ */
+BaseType_t xTaskResumeAll( void ) PRIVILEGED_FUNCTION;
+
+/*-----------------------------------------------------------
+ * TASK UTILITIES
+ *----------------------------------------------------------*/
+
+/**
+ * task. h
+ * <PRE>TickType_t xTaskGetTickCount( void );</PRE>
+ *
+ * @return The count of ticks since vTaskStartScheduler was called.
+ *
+ * \defgroup xTaskGetTickCount xTaskGetTickCount
+ * \ingroup TaskUtils
+ */
+TickType_t xTaskGetTickCount( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * <PRE>TickType_t xTaskGetTickCountFromISR( void );</PRE>
+ *
+ * @return The count of ticks since vTaskStartScheduler was called.
+ *
+ * This is a version of xTaskGetTickCount() that is safe to be called from an
+ * ISR - provided that TickType_t is the natural word size of the
+ * microcontroller being used or interrupt nesting is either not supported or
+ * not being used.
+ *
+ * \defgroup xTaskGetTickCountFromISR xTaskGetTickCountFromISR
+ * \ingroup TaskUtils
+ */
+TickType_t xTaskGetTickCountFromISR( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * <PRE>uint16_t uxTaskGetNumberOfTasks( void );</PRE>
+ *
+ * @return The number of tasks that the real time kernel is currently managing.
+ * This includes all ready, blocked and suspended tasks.  A task that
+ * has been deleted but not yet freed by the idle task will also be
+ * included in the count.
+ *
+ * \defgroup uxTaskGetNumberOfTasks uxTaskGetNumberOfTasks
+ * \ingroup TaskUtils
+ */
+UBaseType_t uxTaskGetNumberOfTasks( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * <PRE>char *pcTaskGetName( TaskHandle_t xTaskToQuery );</PRE>
+ *
+ * @return The text (human readable) name of the task referenced by the handle
+ * xTaskToQuery.  A task can query its own name by either passing in its own
+ * handle, or by setting xTaskToQuery to NULL.
+ *
+ * \defgroup pcTaskGetName pcTaskGetName
+ * \ingroup TaskUtils
+ */
+char *pcTaskGetName( TaskHandle_t xTaskToQuery ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+
+/**
+ * task. h
+ * <PRE>TaskHandle_t xTaskGetHandle( const char *pcNameToQuery );</PRE>
+ *
+ * NOTE:  This function takes a relatively long time to complete and should be
+ * used sparingly.
+ *
+ * @return The handle of the task that has the human readable name pcNameToQuery.
+ * NULL is returned if no matching name is found.  INCLUDE_xTaskGetHandle
+ * must be set to 1 in FreeRTOSConfig.h for pcTaskGetHandle() to be available.
+ *
+ * \defgroup pcTaskGetHandle pcTaskGetHandle
+ * \ingroup TaskUtils
+ */
+TaskHandle_t xTaskGetHandle( const char *pcNameToQuery ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+
+/**
+ * task.h
+ * <PRE>UBaseType_t uxTaskGetStackHighWaterMark( TaskHandle_t xTask );</PRE>
+ *
+ * INCLUDE_uxTaskGetStackHighWaterMark must be set to 1 in FreeRTOSConfig.h for
+ * this function to be available.
+ *
+ * Returns the high water mark of the stack associated with xTask.  That is,
+ * the minimum free stack space there has been (in words, so on a 32 bit machine
+ * a value of 1 means 4 bytes) since the task started.  The smaller the returned
+ * number the closer the task has come to overflowing its stack.
+ *
+ * uxTaskGetStackHighWaterMark() and uxTaskGetStackHighWaterMark2() are the
+ * same except for their return type.  Using configSTACK_DEPTH_TYPE allows the
+ * user to determine the return type.  It gets around the problem of the value
+ * overflowing on 8-bit types without breaking backward compatibility for
+ * applications that expect an 8-bit return type.
+ *
+ * @param xTask Handle of the task associated with the stack to be checked.
+ * Set xTask to NULL to check the stack of the calling task.
+ *
+ * @return The smallest amount of free stack space there has been (in words, so
+ * actual spaces on the stack rather than bytes) since the task referenced by
+ * xTask was created.
+ */
+UBaseType_t uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+
+/**
+ * task.h
+ * <PRE>configSTACK_DEPTH_TYPE uxTaskGetStackHighWaterMark2( TaskHandle_t xTask );</PRE>
+ *
+ * INCLUDE_uxTaskGetStackHighWaterMark2 must be set to 1 in FreeRTOSConfig.h for
+ * this function to be available.
+ *
+ * Returns the high water mark of the stack associated with xTask.  That is,
+ * the minimum free stack space there has been (in words, so on a 32 bit machine
+ * a value of 1 means 4 bytes) since the task started.  The smaller the returned
+ * number the closer the task has come to overflowing its stack.
+ *
+ * uxTaskGetStackHighWaterMark() and uxTaskGetStackHighWaterMark2() are the
+ * same except for their return type.  Using configSTACK_DEPTH_TYPE allows the
+ * user to determine the return type.  It gets around the problem of the value
+ * overflowing on 8-bit types without breaking backward compatibility for
+ * applications that expect an 8-bit return type.
+ *
+ * @param xTask Handle of the task associated with the stack to be checked.
+ * Set xTask to NULL to check the stack of the calling task.
+ *
+ * @return The smallest amount of free stack space there has been (in words, so
+ * actual spaces on the stack rather than bytes) since the task referenced by
+ * xTask was created.
+ */
+configSTACK_DEPTH_TYPE uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+
+/* When using trace macros it is sometimes necessary to include task.h before
+FreeRTOS.h.  When this is done TaskHookFunction_t will not yet have been defined,
+so the following two prototypes will cause a compilation error.  This can be
+fixed by simply guarding against the inclusion of these two prototypes unless
+they are explicitly required by the configUSE_APPLICATION_TASK_TAG configuration
+constant. */
+#ifdef configUSE_APPLICATION_TASK_TAG
+	#if configUSE_APPLICATION_TASK_TAG == 1
+		/**
+		 * task.h
+		 * <pre>void vTaskSetApplicationTaskTag( TaskHandle_t xTask, TaskHookFunction_t pxHookFunction );</pre>
+		 *
+		 * Sets pxHookFunction to be the task hook function used by the task xTask.
+		 * Passing xTask as NULL has the effect of setting the calling tasks hook
+		 * function.
+		 */
+		void vTaskSetApplicationTaskTag( TaskHandle_t xTask, TaskHookFunction_t pxHookFunction ) PRIVILEGED_FUNCTION;
+
+		/**
+		 * task.h
+		 * <pre>void xTaskGetApplicationTaskTag( TaskHandle_t xTask );</pre>
+		 *
+		 * Returns the pxHookFunction value assigned to the task xTask.  Do not
+		 * call from an interrupt service routine - call
+		 * xTaskGetApplicationTaskTagFromISR() instead.
+		 */
+		TaskHookFunction_t xTaskGetApplicationTaskTag( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+
+		/**
+		 * task.h
+		 * <pre>void xTaskGetApplicationTaskTagFromISR( TaskHandle_t xTask );</pre>
+		 *
+		 * Returns the pxHookFunction value assigned to the task xTask.  Can
+		 * be called from an interrupt service routine.
+		 */
+		TaskHookFunction_t xTaskGetApplicationTaskTagFromISR( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+	#endif /* configUSE_APPLICATION_TASK_TAG ==1 */
+#endif /* ifdef configUSE_APPLICATION_TASK_TAG */
+
+#if( configNUM_THREAD_LOCAL_STORAGE_POINTERS > 0 )
+
+	/* Each task contains an array of pointers that is dimensioned by the
+	configNUM_THREAD_LOCAL_STORAGE_POINTERS setting in FreeRTOSConfig.h.  The
+	kernel does not use the pointers itself, so the application writer can use
+	the pointers for any purpose they wish.  The following two functions are
+	used to set and query a pointer respectively. */
+	void vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, BaseType_t xIndex, void *pvValue ) PRIVILEGED_FUNCTION;
+	void *pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, BaseType_t xIndex ) PRIVILEGED_FUNCTION;
+
+#endif
+
+/**
+ * task.h
+ * <pre>BaseType_t xTaskCallApplicationTaskHook( TaskHandle_t xTask, void *pvParameter );</pre>
+ *
+ * Calls the hook function associated with xTask.  Passing xTask as NULL has
+ * the effect of calling the Running tasks (the calling task) hook function.
+ *
+ * pvParameter is passed to the hook function for the task to interpret as it
+ * wants.  The return value is the value returned by the task hook function
+ * registered by the user.
+ */
+BaseType_t xTaskCallApplicationTaskHook( TaskHandle_t xTask, void *pvParameter ) PRIVILEGED_FUNCTION;
+
+/**
+ * xTaskGetIdleTaskHandle() is only available if
+ * INCLUDE_xTaskGetIdleTaskHandle is set to 1 in FreeRTOSConfig.h.
+ *
+ * Simply returns the handle of the idle task.  It is not valid to call
+ * xTaskGetIdleTaskHandle() before the scheduler has been started.
+ */
+TaskHandle_t xTaskGetIdleTaskHandle( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * configUSE_TRACE_FACILITY must be defined as 1 in FreeRTOSConfig.h for
+ * uxTaskGetSystemState() to be available.
+ *
+ * uxTaskGetSystemState() populates an TaskStatus_t structure for each task in
+ * the system.  TaskStatus_t structures contain, among other things, members
+ * for the task handle, task name, task priority, task state, and total amount
+ * of run time consumed by the task.  See the TaskStatus_t structure
+ * definition in this file for the full member list.
+ *
+ * NOTE:  This function is intended for debugging use only as its use results in
+ * the scheduler remaining suspended for an extended period.
+ *
+ * @param pxTaskStatusArray A pointer to an array of TaskStatus_t structures.
+ * The array must contain at least one TaskStatus_t structure for each task
+ * that is under the control of the RTOS.  The number of tasks under the control
+ * of the RTOS can be determined using the uxTaskGetNumberOfTasks() API function.
+ *
+ * @param uxArraySize The size of the array pointed to by the pxTaskStatusArray
+ * parameter.  The size is specified as the number of indexes in the array, or
+ * the number of TaskStatus_t structures contained in the array, not by the
+ * number of bytes in the array.
+ *
+ * @param pulTotalRunTime If configGENERATE_RUN_TIME_STATS is set to 1 in
+ * FreeRTOSConfig.h then *pulTotalRunTime is set by uxTaskGetSystemState() to the
+ * total run time (as defined by the run time stats clock, see
+ * http://www.freertos.org/rtos-run-time-stats.html) since the target booted.
+ * pulTotalRunTime can be set to NULL to omit the total run time information.
+ *
+ * @return The number of TaskStatus_t structures that were populated by
+ * uxTaskGetSystemState().  This should equal the number returned by the
+ * uxTaskGetNumberOfTasks() API function, but will be zero if the value passed
+ * in the uxArraySize parameter was too small.
+ *
+ * Example usage:
+   <pre>
+    // This example demonstrates how a human readable table of run time stats
+	// information is generated from raw data provided by uxTaskGetSystemState().
+	// The human readable table is written to pcWriteBuffer
+	void vTaskGetRunTimeStats( char *pcWriteBuffer )
+	{
+	TaskStatus_t *pxTaskStatusArray;
+	volatile UBaseType_t uxArraySize, x;
+	uint32_t ulTotalRunTime, ulStatsAsPercentage;
+
+		// Make sure the write buffer does not contain a string.
+		*pcWriteBuffer = 0x00;
+
+		// Take a snapshot of the number of tasks in case it changes while this
+		// function is executing.
+		uxArraySize = uxTaskGetNumberOfTasks();
+
+		// Allocate a TaskStatus_t structure for each task.  An array could be
+		// allocated statically at compile time.
+		pxTaskStatusArray = pvPortMalloc( uxArraySize * sizeof( TaskStatus_t ) );
+
+		if( pxTaskStatusArray != NULL )
+		{
+			// Generate raw status information about each task.
+			uxArraySize = uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, &ulTotalRunTime );
+
+			// For percentage calculations.
+			ulTotalRunTime /= 100UL;
+
+			// Avoid divide by zero errors.
+			if( ulTotalRunTime > 0 )
+			{
+				// For each populated position in the pxTaskStatusArray array,
+				// format the raw data as human readable ASCII data
+				for( x = 0; x < uxArraySize; x++ )
+				{
+					// What percentage of the total run time has the task used?
+					// This will always be rounded down to the nearest integer.
+					// ulTotalRunTimeDiv100 has already been divided by 100.
+					ulStatsAsPercentage = pxTaskStatusArray[ x ].ulRunTimeCounter / ulTotalRunTime;
+
+					if( ulStatsAsPercentage > 0UL )
+					{
+						sprintf( pcWriteBuffer, "%s\t\t%lu\t\t%lu%%\r\n", pxTaskStatusArray[ x ].pcTaskName, pxTaskStatusArray[ x ].ulRunTimeCounter, ulStatsAsPercentage );
+					}
+					else
+					{
+						// If the percentage is zero here then the task has
+						// consumed less than 1% of the total run time.
+						sprintf( pcWriteBuffer, "%s\t\t%lu\t\t<1%%\r\n", pxTaskStatusArray[ x ].pcTaskName, pxTaskStatusArray[ x ].ulRunTimeCounter );
+					}
+
+					pcWriteBuffer += strlen( ( char * ) pcWriteBuffer );
+				}
+			}
+
+			// The array is no longer needed, free the memory it consumes.
+			vPortFree( pxTaskStatusArray );
+		}
+	}
+	</pre>
+ */
+UBaseType_t uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, const UBaseType_t uxArraySize, uint32_t * const pulTotalRunTime ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * <PRE>void vTaskList( char *pcWriteBuffer );</PRE>
+ *
+ * configUSE_TRACE_FACILITY and configUSE_STATS_FORMATTING_FUNCTIONS must
+ * both be defined as 1 for this function to be available.  See the
+ * configuration section of the FreeRTOS.org website for more information.
+ *
+ * NOTE 1: This function will disable interrupts for its duration.  It is
+ * not intended for normal application runtime use but as a debug aid.
+ *
+ * Lists all the current tasks, along with their current state and stack
+ * usage high water mark.
+ *
+ * Tasks are reported as blocked ('B'), ready ('R'), deleted ('D') or
+ * suspended ('S').
+ *
+ * PLEASE NOTE:
+ *
+ * This function is provided for convenience only, and is used by many of the
+ * demo applications.  Do not consider it to be part of the scheduler.
+ *
+ * vTaskList() calls uxTaskGetSystemState(), then formats part of the
+ * uxTaskGetSystemState() output into a human readable table that displays task
+ * names, states and stack usage.
+ *
+ * vTaskList() has a dependency on the sprintf() C library function that might
+ * bloat the code size, use a lot of stack, and provide different results on
+ * different platforms.  An alternative, tiny, third party, and limited
+ * functionality implementation of sprintf() is provided in many of the
+ * FreeRTOS/Demo sub-directories in a file called printf-stdarg.c (note
+ * printf-stdarg.c does not provide a full snprintf() implementation!).
+ *
+ * It is recommended that production systems call uxTaskGetSystemState()
+ * directly to get access to raw stats data, rather than indirectly through a
+ * call to vTaskList().
+ *
+ * @param pcWriteBuffer A buffer into which the above mentioned details
+ * will be written, in ASCII form.  This buffer is assumed to be large
+ * enough to contain the generated report.  Approximately 40 bytes per
+ * task should be sufficient.
+ *
+ * \defgroup vTaskList vTaskList
+ * \ingroup TaskUtils
+ */
+void vTaskList( char * pcWriteBuffer ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+
+/**
+ * task. h
+ * <PRE>void vTaskGetRunTimeStats( char *pcWriteBuffer );</PRE>
+ *
+ * configGENERATE_RUN_TIME_STATS and configUSE_STATS_FORMATTING_FUNCTIONS
+ * must both be defined as 1 for this function to be available.  The application
+ * must also then provide definitions for
+ * portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() and portGET_RUN_TIME_COUNTER_VALUE()
+ * to configure a peripheral timer/counter and return the timers current count
+ * value respectively.  The counter should be at least 10 times the frequency of
+ * the tick count.
+ *
+ * NOTE 1: This function will disable interrupts for its duration.  It is
+ * not intended for normal application runtime use but as a debug aid.
+ *
+ * Setting configGENERATE_RUN_TIME_STATS to 1 will result in a total
+ * accumulated execution time being stored for each task.  The resolution
+ * of the accumulated time value depends on the frequency of the timer
+ * configured by the portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() macro.
+ * Calling vTaskGetRunTimeStats() writes the total execution time of each
+ * task into a buffer, both as an absolute count value and as a percentage
+ * of the total system execution time.
+ *
+ * NOTE 2:
+ *
+ * This function is provided for convenience only, and is used by many of the
+ * demo applications.  Do not consider it to be part of the scheduler.
+ *
+ * vTaskGetRunTimeStats() calls uxTaskGetSystemState(), then formats part of the
+ * uxTaskGetSystemState() output into a human readable table that displays the
+ * amount of time each task has spent in the Running state in both absolute and
+ * percentage terms.
+ *
+ * vTaskGetRunTimeStats() has a dependency on the sprintf() C library function
+ * that might bloat the code size, use a lot of stack, and provide different
+ * results on different platforms.  An alternative, tiny, third party, and
+ * limited functionality implementation of sprintf() is provided in many of the
+ * FreeRTOS/Demo sub-directories in a file called printf-stdarg.c (note
+ * printf-stdarg.c does not provide a full snprintf() implementation!).
+ *
+ * It is recommended that production systems call uxTaskGetSystemState() directly
+ * to get access to raw stats data, rather than indirectly through a call to
+ * vTaskGetRunTimeStats().
+ *
+ * @param pcWriteBuffer A buffer into which the execution times will be
+ * written, in ASCII form.  This buffer is assumed to be large enough to
+ * contain the generated report.  Approximately 40 bytes per task should
+ * be sufficient.
+ *
+ * \defgroup vTaskGetRunTimeStats vTaskGetRunTimeStats
+ * \ingroup TaskUtils
+ */
+void vTaskGetRunTimeStats( char *pcWriteBuffer ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+
+/**
+* task. h
+* <PRE>uint32_t ulTaskGetIdleRunTimeCounter( void );</PRE>
+*
+* configGENERATE_RUN_TIME_STATS and configUSE_STATS_FORMATTING_FUNCTIONS
+* must both be defined as 1 for this function to be available.  The application
+* must also then provide definitions for
+* portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() and portGET_RUN_TIME_COUNTER_VALUE()
+* to configure a peripheral timer/counter and return the timers current count
+* value respectively.  The counter should be at least 10 times the frequency of
+* the tick count.
+*
+* Setting configGENERATE_RUN_TIME_STATS to 1 will result in a total
+* accumulated execution time being stored for each task.  The resolution
+* of the accumulated time value depends on the frequency of the timer
+* configured by the portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() macro.
+* While uxTaskGetSystemState() and vTaskGetRunTimeStats() writes the total
+* execution time of each task into a buffer, ulTaskGetIdleRunTimeCounter()
+* returns the total execution time of just the idle task.
+*
+* @return The total run time of the idle task.  This is the amount of time the
+* idle task has actually been executing.  The unit of time is dependent on the
+* frequency configured using the portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() and
+* portGET_RUN_TIME_COUNTER_VALUE() macros.
+*
+* \defgroup ulTaskGetIdleRunTimeCounter ulTaskGetIdleRunTimeCounter
+* \ingroup TaskUtils
+*/
+uint32_t ulTaskGetIdleRunTimeCounter( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * <PRE>BaseType_t xTaskNotify( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction );</PRE>
+ *
+ * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this
+ * function to be available.
+ *
+ * When configUSE_TASK_NOTIFICATIONS is set to one each task has its own private
+ * "notification value", which is a 32-bit unsigned integer (uint32_t).
+ *
+ * Events can be sent to a task using an intermediary object.  Examples of such
+ * objects are queues, semaphores, mutexes and event groups.  Task notifications
+ * are a method of sending an event directly to a task without the need for such
+ * an intermediary object.
+ *
+ * A notification sent to a task can optionally perform an action, such as
+ * update, overwrite or increment the task's notification value.  In that way
+ * task notifications can be used to send data to a task, or be used as light
+ * weight and fast binary or counting semaphores.
+ *
+ * A notification sent to a task will remain pending until it is cleared by the
+ * task calling xTaskNotifyWait() or ulTaskNotifyTake().  If the task was
+ * already in the Blocked state to wait for a notification when the notification
+ * arrives then the task will automatically be removed from the Blocked state
+ * (unblocked) and the notification cleared.
+ *
+ * A task can use xTaskNotifyWait() to [optionally] block to wait for a
+ * notification to be pending, or ulTaskNotifyTake() to [optionally] block
+ * to wait for its notification value to have a non-zero value.  The task does
+ * not consume any CPU time while it is in the Blocked state.
+ *
+ * See http://www.FreeRTOS.org/RTOS-task-notifications.html for details.
+ *
+ * @param xTaskToNotify The handle of the task being notified.  The handle to a
+ * task can be returned from the xTaskCreate() API function used to create the
+ * task, and the handle of the currently running task can be obtained by calling
+ * xTaskGetCurrentTaskHandle().
+ *
+ * @param ulValue Data that can be sent with the notification.  How the data is
+ * used depends on the value of the eAction parameter.
+ *
+ * @param eAction Specifies how the notification updates the task's notification
+ * value, if at all.  Valid values for eAction are as follows:
+ *
+ * eSetBits -
+ * The task's notification value is bitwise ORed with ulValue.  xTaskNofify()
+ * always returns pdPASS in this case.
+ *
+ * eIncrement -
+ * The task's notification value is incremented.  ulValue is not used and
+ * xTaskNotify() always returns pdPASS in this case.
+ *
+ * eSetValueWithOverwrite -
+ * The task's notification value is set to the value of ulValue, even if the
+ * task being notified had not yet processed the previous notification (the
+ * task already had a notification pending).  xTaskNotify() always returns
+ * pdPASS in this case.
+ *
+ * eSetValueWithoutOverwrite -
+ * If the task being notified did not already have a notification pending then
+ * the task's notification value is set to ulValue and xTaskNotify() will
+ * return pdPASS.  If the task being notified already had a notification
+ * pending then no action is performed and pdFAIL is returned.
+ *
+ * eNoAction -
+ * The task receives a notification without its notification value being
+ * updated.  ulValue is not used and xTaskNotify() always returns pdPASS in
+ * this case.
+ *
+ *  pulPreviousNotificationValue -
+ *  Can be used to pass out the subject task's notification value before any
+ *  bits are modified by the notify function.
+ *
+ * @return Dependent on the value of eAction.  See the description of the
+ * eAction parameter.
+ *
+ * \defgroup xTaskNotify xTaskNotify
+ * \ingroup TaskNotifications
+ */
+BaseType_t xTaskGenericNotify( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue ) PRIVILEGED_FUNCTION;
+#define xTaskNotify( xTaskToNotify, ulValue, eAction ) xTaskGenericNotify( ( xTaskToNotify ), ( ulValue ), ( eAction ), NULL )
+#define xTaskNotifyAndQuery( xTaskToNotify, ulValue, eAction, pulPreviousNotifyValue ) xTaskGenericNotify( ( xTaskToNotify ), ( ulValue ), ( eAction ), ( pulPreviousNotifyValue ) )
+
+/**
+ * task. h
+ * <PRE>BaseType_t xTaskNotifyFromISR( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, BaseType_t *pxHigherPriorityTaskWoken );</PRE>
+ *
+ * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this
+ * function to be available.
+ *
+ * When configUSE_TASK_NOTIFICATIONS is set to one each task has its own private
+ * "notification value", which is a 32-bit unsigned integer (uint32_t).
+ *
+ * A version of xTaskNotify() that can be used from an interrupt service routine
+ * (ISR).
+ *
+ * Events can be sent to a task using an intermediary object.  Examples of such
+ * objects are queues, semaphores, mutexes and event groups.  Task notifications
+ * are a method of sending an event directly to a task without the need for such
+ * an intermediary object.
+ *
+ * A notification sent to a task can optionally perform an action, such as
+ * update, overwrite or increment the task's notification value.  In that way
+ * task notifications can be used to send data to a task, or be used as light
+ * weight and fast binary or counting semaphores.
+ *
+ * A notification sent to a task will remain pending until it is cleared by the
+ * task calling xTaskNotifyWait() or ulTaskNotifyTake().  If the task was
+ * already in the Blocked state to wait for a notification when the notification
+ * arrives then the task will automatically be removed from the Blocked state
+ * (unblocked) and the notification cleared.
+ *
+ * A task can use xTaskNotifyWait() to [optionally] block to wait for a
+ * notification to be pending, or ulTaskNotifyTake() to [optionally] block
+ * to wait for its notification value to have a non-zero value.  The task does
+ * not consume any CPU time while it is in the Blocked state.
+ *
+ * See http://www.FreeRTOS.org/RTOS-task-notifications.html for details.
+ *
+ * @param xTaskToNotify The handle of the task being notified.  The handle to a
+ * task can be returned from the xTaskCreate() API function used to create the
+ * task, and the handle of the currently running task can be obtained by calling
+ * xTaskGetCurrentTaskHandle().
+ *
+ * @param ulValue Data that can be sent with the notification.  How the data is
+ * used depends on the value of the eAction parameter.
+ *
+ * @param eAction Specifies how the notification updates the task's notification
+ * value, if at all.  Valid values for eAction are as follows:
+ *
+ * eSetBits -
+ * The task's notification value is bitwise ORed with ulValue.  xTaskNofify()
+ * always returns pdPASS in this case.
+ *
+ * eIncrement -
+ * The task's notification value is incremented.  ulValue is not used and
+ * xTaskNotify() always returns pdPASS in this case.
+ *
+ * eSetValueWithOverwrite -
+ * The task's notification value is set to the value of ulValue, even if the
+ * task being notified had not yet processed the previous notification (the
+ * task already had a notification pending).  xTaskNotify() always returns
+ * pdPASS in this case.
+ *
+ * eSetValueWithoutOverwrite -
+ * If the task being notified did not already have a notification pending then
+ * the task's notification value is set to ulValue and xTaskNotify() will
+ * return pdPASS.  If the task being notified already had a notification
+ * pending then no action is performed and pdFAIL is returned.
+ *
+ * eNoAction -
+ * The task receives a notification without its notification value being
+ * updated.  ulValue is not used and xTaskNotify() always returns pdPASS in
+ * this case.
+ *
+ * @param pxHigherPriorityTaskWoken  xTaskNotifyFromISR() will set
+ * *pxHigherPriorityTaskWoken to pdTRUE if sending the notification caused the
+ * task to which the notification was sent to leave the Blocked state, and the
+ * unblocked task has a priority higher than the currently running task.  If
+ * xTaskNotifyFromISR() sets this value to pdTRUE then a context switch should
+ * be requested before the interrupt is exited.  How a context switch is
+ * requested from an ISR is dependent on the port - see the documentation page
+ * for the port in use.
+ *
+ * @return Dependent on the value of eAction.  See the description of the
+ * eAction parameter.
+ *
+ * \defgroup xTaskNotify xTaskNotify
+ * \ingroup TaskNotifications
+ */
+BaseType_t xTaskGenericNotifyFromISR( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue, BaseType_t *pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+#define xTaskNotifyFromISR( xTaskToNotify, ulValue, eAction, pxHigherPriorityTaskWoken ) xTaskGenericNotifyFromISR( ( xTaskToNotify ), ( ulValue ), ( eAction ), NULL, ( pxHigherPriorityTaskWoken ) )
+#define xTaskNotifyAndQueryFromISR( xTaskToNotify, ulValue, eAction, pulPreviousNotificationValue, pxHigherPriorityTaskWoken ) xTaskGenericNotifyFromISR( ( xTaskToNotify ), ( ulValue ), ( eAction ), ( pulPreviousNotificationValue ), ( pxHigherPriorityTaskWoken ) )
+
+/**
+ * task. h
+ * <PRE>BaseType_t xTaskNotifyWait( uint32_t ulBitsToClearOnEntry, uint32_t ulBitsToClearOnExit, uint32_t *pulNotificationValue, TickType_t xTicksToWait );</pre>
+ *
+ * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this
+ * function to be available.
+ *
+ * When configUSE_TASK_NOTIFICATIONS is set to one each task has its own private
+ * "notification value", which is a 32-bit unsigned integer (uint32_t).
+ *
+ * Events can be sent to a task using an intermediary object.  Examples of such
+ * objects are queues, semaphores, mutexes and event groups.  Task notifications
+ * are a method of sending an event directly to a task without the need for such
+ * an intermediary object.
+ *
+ * A notification sent to a task can optionally perform an action, such as
+ * update, overwrite or increment the task's notification value.  In that way
+ * task notifications can be used to send data to a task, or be used as light
+ * weight and fast binary or counting semaphores.
+ *
+ * A notification sent to a task will remain pending until it is cleared by the
+ * task calling xTaskNotifyWait() or ulTaskNotifyTake().  If the task was
+ * already in the Blocked state to wait for a notification when the notification
+ * arrives then the task will automatically be removed from the Blocked state
+ * (unblocked) and the notification cleared.
+ *
+ * A task can use xTaskNotifyWait() to [optionally] block to wait for a
+ * notification to be pending, or ulTaskNotifyTake() to [optionally] block
+ * to wait for its notification value to have a non-zero value.  The task does
+ * not consume any CPU time while it is in the Blocked state.
+ *
+ * See http://www.FreeRTOS.org/RTOS-task-notifications.html for details.
+ *
+ * @param ulBitsToClearOnEntry Bits that are set in ulBitsToClearOnEntry value
+ * will be cleared in the calling task's notification value before the task
+ * checks to see if any notifications are pending, and optionally blocks if no
+ * notifications are pending.  Setting ulBitsToClearOnEntry to ULONG_MAX (if
+ * limits.h is included) or 0xffffffffUL (if limits.h is not included) will have
+ * the effect of resetting the task's notification value to 0.  Setting
+ * ulBitsToClearOnEntry to 0 will leave the task's notification value unchanged.
+ *
+ * @param ulBitsToClearOnExit If a notification is pending or received before
+ * the calling task exits the xTaskNotifyWait() function then the task's
+ * notification value (see the xTaskNotify() API function) is passed out using
+ * the pulNotificationValue parameter.  Then any bits that are set in
+ * ulBitsToClearOnExit will be cleared in the task's notification value (note
+ * *pulNotificationValue is set before any bits are cleared).  Setting
+ * ulBitsToClearOnExit to ULONG_MAX (if limits.h is included) or 0xffffffffUL
+ * (if limits.h is not included) will have the effect of resetting the task's
+ * notification value to 0 before the function exits.  Setting
+ * ulBitsToClearOnExit to 0 will leave the task's notification value unchanged
+ * when the function exits (in which case the value passed out in
+ * pulNotificationValue will match the task's notification value).
+ *
+ * @param pulNotificationValue Used to pass the task's notification value out
+ * of the function.  Note the value passed out will not be effected by the
+ * clearing of any bits caused by ulBitsToClearOnExit being non-zero.
+ *
+ * @param xTicksToWait The maximum amount of time that the task should wait in
+ * the Blocked state for a notification to be received, should a notification
+ * not already be pending when xTaskNotifyWait() was called.  The task
+ * will not consume any processing time while it is in the Blocked state.  This
+ * is specified in kernel ticks, the macro pdMS_TO_TICSK( value_in_ms ) can be
+ * used to convert a time specified in milliseconds to a time specified in
+ * ticks.
+ *
+ * @return If a notification was received (including notifications that were
+ * already pending when xTaskNotifyWait was called) then pdPASS is
+ * returned.  Otherwise pdFAIL is returned.
+ *
+ * \defgroup xTaskNotifyWait xTaskNotifyWait
+ * \ingroup TaskNotifications
+ */
+BaseType_t xTaskNotifyWait( uint32_t ulBitsToClearOnEntry, uint32_t ulBitsToClearOnExit, uint32_t *pulNotificationValue, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * <PRE>BaseType_t xTaskNotifyGive( TaskHandle_t xTaskToNotify );</PRE>
+ *
+ * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this macro
+ * to be available.
+ *
+ * When configUSE_TASK_NOTIFICATIONS is set to one each task has its own private
+ * "notification value", which is a 32-bit unsigned integer (uint32_t).
+ *
+ * Events can be sent to a task using an intermediary object.  Examples of such
+ * objects are queues, semaphores, mutexes and event groups.  Task notifications
+ * are a method of sending an event directly to a task without the need for such
+ * an intermediary object.
+ *
+ * A notification sent to a task can optionally perform an action, such as
+ * update, overwrite or increment the task's notification value.  In that way
+ * task notifications can be used to send data to a task, or be used as light
+ * weight and fast binary or counting semaphores.
+ *
+ * xTaskNotifyGive() is a helper macro intended for use when task notifications
+ * are used as light weight and faster binary or counting semaphore equivalents.
+ * Actual FreeRTOS semaphores are given using the xSemaphoreGive() API function,
+ * the equivalent action that instead uses a task notification is
+ * xTaskNotifyGive().
+ *
+ * When task notifications are being used as a binary or counting semaphore
+ * equivalent then the task being notified should wait for the notification
+ * using the ulTaskNotificationTake() API function rather than the
+ * xTaskNotifyWait() API function.
+ *
+ * See http://www.FreeRTOS.org/RTOS-task-notifications.html for more details.
+ *
+ * @param xTaskToNotify The handle of the task being notified.  The handle to a
+ * task can be returned from the xTaskCreate() API function used to create the
+ * task, and the handle of the currently running task can be obtained by calling
+ * xTaskGetCurrentTaskHandle().
+ *
+ * @return xTaskNotifyGive() is a macro that calls xTaskNotify() with the
+ * eAction parameter set to eIncrement - so pdPASS is always returned.
+ *
+ * \defgroup xTaskNotifyGive xTaskNotifyGive
+ * \ingroup TaskNotifications
+ */
+#define xTaskNotifyGive( xTaskToNotify ) xTaskGenericNotify( ( xTaskToNotify ), ( 0 ), eIncrement, NULL )
+
+/**
+ * task. h
+ * <PRE>void vTaskNotifyGiveFromISR( TaskHandle_t xTaskHandle, BaseType_t *pxHigherPriorityTaskWoken );
+ *
+ * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this macro
+ * to be available.
+ *
+ * When configUSE_TASK_NOTIFICATIONS is set to one each task has its own private
+ * "notification value", which is a 32-bit unsigned integer (uint32_t).
+ *
+ * A version of xTaskNotifyGive() that can be called from an interrupt service
+ * routine (ISR).
+ *
+ * Events can be sent to a task using an intermediary object.  Examples of such
+ * objects are queues, semaphores, mutexes and event groups.  Task notifications
+ * are a method of sending an event directly to a task without the need for such
+ * an intermediary object.
+ *
+ * A notification sent to a task can optionally perform an action, such as
+ * update, overwrite or increment the task's notification value.  In that way
+ * task notifications can be used to send data to a task, or be used as light
+ * weight and fast binary or counting semaphores.
+ *
+ * vTaskNotifyGiveFromISR() is intended for use when task notifications are
+ * used as light weight and faster binary or counting semaphore equivalents.
+ * Actual FreeRTOS semaphores are given from an ISR using the
+ * xSemaphoreGiveFromISR() API function, the equivalent action that instead uses
+ * a task notification is vTaskNotifyGiveFromISR().
+ *
+ * When task notifications are being used as a binary or counting semaphore
+ * equivalent then the task being notified should wait for the notification
+ * using the ulTaskNotificationTake() API function rather than the
+ * xTaskNotifyWait() API function.
+ *
+ * See http://www.FreeRTOS.org/RTOS-task-notifications.html for more details.
+ *
+ * @param xTaskToNotify The handle of the task being notified.  The handle to a
+ * task can be returned from the xTaskCreate() API function used to create the
+ * task, and the handle of the currently running task can be obtained by calling
+ * xTaskGetCurrentTaskHandle().
+ *
+ * @param pxHigherPriorityTaskWoken  vTaskNotifyGiveFromISR() will set
+ * *pxHigherPriorityTaskWoken to pdTRUE if sending the notification caused the
+ * task to which the notification was sent to leave the Blocked state, and the
+ * unblocked task has a priority higher than the currently running task.  If
+ * vTaskNotifyGiveFromISR() sets this value to pdTRUE then a context switch
+ * should be requested before the interrupt is exited.  How a context switch is
+ * requested from an ISR is dependent on the port - see the documentation page
+ * for the port in use.
+ *
+ * \defgroup xTaskNotifyWait xTaskNotifyWait
+ * \ingroup TaskNotifications
+ */
+void vTaskNotifyGiveFromISR( TaskHandle_t xTaskToNotify, BaseType_t *pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * <PRE>uint32_t ulTaskNotifyTake( BaseType_t xClearCountOnExit, TickType_t xTicksToWait );</pre>
+ *
+ * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this
+ * function to be available.
+ *
+ * When configUSE_TASK_NOTIFICATIONS is set to one each task has its own private
+ * "notification value", which is a 32-bit unsigned integer (uint32_t).
+ *
+ * Events can be sent to a task using an intermediary object.  Examples of such
+ * objects are queues, semaphores, mutexes and event groups.  Task notifications
+ * are a method of sending an event directly to a task without the need for such
+ * an intermediary object.
+ *
+ * A notification sent to a task can optionally perform an action, such as
+ * update, overwrite or increment the task's notification value.  In that way
+ * task notifications can be used to send data to a task, or be used as light
+ * weight and fast binary or counting semaphores.
+ *
+ * ulTaskNotifyTake() is intended for use when a task notification is used as a
+ * faster and lighter weight binary or counting semaphore alternative.  Actual
+ * FreeRTOS semaphores are taken using the xSemaphoreTake() API function, the
+ * equivalent action that instead uses a task notification is
+ * ulTaskNotifyTake().
+ *
+ * When a task is using its notification value as a binary or counting semaphore
+ * other tasks should send notifications to it using the xTaskNotifyGive()
+ * macro, or xTaskNotify() function with the eAction parameter set to
+ * eIncrement.
+ *
+ * ulTaskNotifyTake() can either clear the task's notification value to
+ * zero on exit, in which case the notification value acts like a binary
+ * semaphore, or decrement the task's notification value on exit, in which case
+ * the notification value acts like a counting semaphore.
+ *
+ * A task can use ulTaskNotifyTake() to [optionally] block to wait for a
+ * the task's notification value to be non-zero.  The task does not consume any
+ * CPU time while it is in the Blocked state.
+ *
+ * Where as xTaskNotifyWait() will return when a notification is pending,
+ * ulTaskNotifyTake() will return when the task's notification value is
+ * not zero.
+ *
+ * See http://www.FreeRTOS.org/RTOS-task-notifications.html for details.
+ *
+ * @param xClearCountOnExit if xClearCountOnExit is pdFALSE then the task's
+ * notification value is decremented when the function exits.  In this way the
+ * notification value acts like a counting semaphore.  If xClearCountOnExit is
+ * not pdFALSE then the task's notification value is cleared to zero when the
+ * function exits.  In this way the notification value acts like a binary
+ * semaphore.
+ *
+ * @param xTicksToWait The maximum amount of time that the task should wait in
+ * the Blocked state for the task's notification value to be greater than zero,
+ * should the count not already be greater than zero when
+ * ulTaskNotifyTake() was called.  The task will not consume any processing
+ * time while it is in the Blocked state.  This is specified in kernel ticks,
+ * the macro pdMS_TO_TICSK( value_in_ms ) can be used to convert a time
+ * specified in milliseconds to a time specified in ticks.
+ *
+ * @return The task's notification count before it is either cleared to zero or
+ * decremented (see the xClearCountOnExit parameter).
+ *
+ * \defgroup ulTaskNotifyTake ulTaskNotifyTake
+ * \ingroup TaskNotifications
+ */
+uint32_t ulTaskNotifyTake( BaseType_t xClearCountOnExit, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * <PRE>BaseType_t xTaskNotifyStateClear( TaskHandle_t xTask );</pre>
+ *
+ * If the notification state of the task referenced by the handle xTask is
+ * eNotified, then set the task's notification state to eNotWaitingNotification.
+ * The task's notification value is not altered.  Set xTask to NULL to clear the
+ * notification state of the calling task.
+ *
+ * @return pdTRUE if the task's notification state was set to
+ * eNotWaitingNotification, otherwise pdFALSE.
+ * \defgroup xTaskNotifyStateClear xTaskNotifyStateClear
+ * \ingroup TaskNotifications
+ */
+BaseType_t xTaskNotifyStateClear( TaskHandle_t xTask );
+
+/**
+* task. h
+* <PRE>uint32_t ulTaskNotifyValueClear( TaskHandle_t xTask, uint32_t ulBitsToClear );</pre>
+*
+* Clears the bits specified by the ulBitsToClear bit mask in the notification
+* value of the task referenced by xTask.
+*
+* Set ulBitsToClear to 0xffffffff (UINT_MAX on 32-bit architectures) to clear
+* the notification value to 0.  Set ulBitsToClear to 0 to query the task's
+* notification value without clearing any bits.
+*
+* @return The value of the target task's notification value before the bits
+* specified by ulBitsToClear were cleared.
+* \defgroup ulTaskNotifyValueClear ulTaskNotifyValueClear
+* \ingroup TaskNotifications
+*/
+uint32_t ulTaskNotifyValueClear( TaskHandle_t xTask, uint32_t ulBitsToClear ) PRIVILEGED_FUNCTION;
+
+/**
+ * task.h
+ * <pre>void vTaskSetTimeOutState( TimeOut_t * const pxTimeOut )</pre>
+ *
+ * Capture the current time for future use with xTaskCheckForTimeOut().
+ *
+ * @param pxTimeOut Pointer to a timeout object into which the current time
+ * is to be captured.  The captured time includes the tick count and the number
+ * of times the tick count has overflowed since the system first booted.
+ * \defgroup vTaskSetTimeOutState vTaskSetTimeOutState
+ * \ingroup TaskCtrl
+ */
+void vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) PRIVILEGED_FUNCTION;
+
+/**
+ * task.h
+ * <pre>BaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait );</pre>
+ *
+ * Determines if pxTicksToWait ticks has passed since a time was captured
+ * using a call to vTaskSetTimeOutState().  The captured time includes the tick
+ * count and the number of times the tick count has overflowed.
+ *
+ * @param pxTimeOut The time status as captured previously using
+ * vTaskSetTimeOutState. If the timeout has not yet occurred, it is updated
+ * to reflect the current time status.
+ * @param pxTicksToWait The number of ticks to check for timeout i.e. if
+ * pxTicksToWait ticks have passed since pxTimeOut was last updated (either by
+ * vTaskSetTimeOutState() or xTaskCheckForTimeOut()), the timeout has occurred.
+ * If the timeout has not occurred, pxTIcksToWait is updated to reflect the
+ * number of remaining ticks.
+ *
+ * @return If timeout has occurred, pdTRUE is returned. Otherwise pdFALSE is
+ * returned and pxTicksToWait is updated to reflect the number of remaining
+ * ticks.
+ *
+ * @see https://www.freertos.org/xTaskCheckForTimeOut.html
+ *
+ * Example Usage:
+ * <pre>
+	// Driver library function used to receive uxWantedBytes from an Rx buffer
+	// that is filled by a UART interrupt. If there are not enough bytes in the
+	// Rx buffer then the task enters the Blocked state until it is notified that
+	// more data has been placed into the buffer. If there is still not enough
+	// data then the task re-enters the Blocked state, and xTaskCheckForTimeOut()
+	// is used to re-calculate the Block time to ensure the total amount of time
+	// spent in the Blocked state does not exceed MAX_TIME_TO_WAIT. This
+	// continues until either the buffer contains at least uxWantedBytes bytes,
+	// or the total amount of time spent in the Blocked state reaches
+	// MAX_TIME_TO_WAIT – at which point the task reads however many bytes are
+	// available up to a maximum of uxWantedBytes.
+
+	size_t xUART_Receive( uint8_t *pucBuffer, size_t uxWantedBytes )
+	{
+	size_t uxReceived = 0;
+	TickType_t xTicksToWait = MAX_TIME_TO_WAIT;
+	TimeOut_t xTimeOut;
+
+		// Initialize xTimeOut.  This records the time at which this function
+		// was entered.
+		vTaskSetTimeOutState( &xTimeOut );
+
+		// Loop until the buffer contains the wanted number of bytes, or a
+		// timeout occurs.
+		while( UART_bytes_in_rx_buffer( pxUARTInstance ) < uxWantedBytes )
+		{
+			// The buffer didn't contain enough data so this task is going to
+			// enter the Blocked state. Adjusting xTicksToWait to account for
+			// any time that has been spent in the Blocked state within this
+			// function so far to ensure the total amount of time spent in the
+			// Blocked state does not exceed MAX_TIME_TO_WAIT.
+			if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) != pdFALSE )
+			{
+				//Timed out before the wanted number of bytes were available,
+				// exit the loop.
+				break;
+			}
+
+			// Wait for a maximum of xTicksToWait ticks to be notified that the
+			// receive interrupt has placed more data into the buffer.
+			ulTaskNotifyTake( pdTRUE, xTicksToWait );
+		}
+
+		// Attempt to read uxWantedBytes from the receive buffer into pucBuffer.
+		// The actual number of bytes read (which might be less than
+		// uxWantedBytes) is returned.
+		uxReceived = UART_read_from_receive_buffer( pxUARTInstance,
+													pucBuffer,
+													uxWantedBytes );
+
+		return uxReceived;
+	}
+ </pre>
+ * \defgroup xTaskCheckForTimeOut xTaskCheckForTimeOut
+ * \ingroup TaskCtrl
+ */
+BaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait ) PRIVILEGED_FUNCTION;
+
+/*-----------------------------------------------------------
+ * SCHEDULER INTERNALS AVAILABLE FOR PORTING PURPOSES
+ *----------------------------------------------------------*/
+
+/*
+ * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE.  IT IS ONLY
+ * INTENDED FOR USE WHEN IMPLEMENTING A PORT OF THE SCHEDULER AND IS
+ * AN INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.
+ *
+ * Called from the real time kernel tick (either preemptive or cooperative),
+ * this increments the tick count and checks if any tasks that are blocked
+ * for a finite period required removing from a blocked list and placing on
+ * a ready list.  If a non-zero value is returned then a context switch is
+ * required because either:
+ *   + A task was removed from a blocked list because its timeout had expired,
+ *     or
+ *   + Time slicing is in use and there is a task of equal priority to the
+ *     currently running task.
+ */
+BaseType_t xTaskIncrementTick( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE.  IT IS AN
+ * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.
+ *
+ * THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED.
+ *
+ * Removes the calling task from the ready list and places it both
+ * on the list of tasks waiting for a particular event, and the
+ * list of delayed tasks.  The task will be removed from both lists
+ * and replaced on the ready list should either the event occur (and
+ * there be no higher priority tasks waiting on the same event) or
+ * the delay period expires.
+ *
+ * The 'unordered' version replaces the event list item value with the
+ * xItemValue value, and inserts the list item at the end of the list.
+ *
+ * The 'ordered' version uses the existing event list item value (which is the
+ * owning tasks priority) to insert the list item into the event list is task
+ * priority order.
+ *
+ * @param pxEventList The list containing tasks that are blocked waiting
+ * for the event to occur.
+ *
+ * @param xItemValue The item value to use for the event list item when the
+ * event list is not ordered by task priority.
+ *
+ * @param xTicksToWait The maximum amount of time that the task should wait
+ * for the event to occur.  This is specified in kernel ticks,the constant
+ * portTICK_PERIOD_MS can be used to convert kernel ticks into a real time
+ * period.
+ */
+void vTaskPlaceOnEventList( List_t * const pxEventList, const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+void vTaskPlaceOnUnorderedEventList( List_t * pxEventList, const TickType_t xItemValue, const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+/*
+ * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE.  IT IS AN
+ * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.
+ *
+ * THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED.
+ *
+ * This function performs nearly the same function as vTaskPlaceOnEventList().
+ * The difference being that this function does not permit tasks to block
+ * indefinitely, whereas vTaskPlaceOnEventList() does.
+ *
+ */
+void vTaskPlaceOnEventListRestricted( List_t * const pxEventList, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely ) PRIVILEGED_FUNCTION;
+
+/*
+ * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE.  IT IS AN
+ * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.
+ *
+ * THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED.
+ *
+ * Removes a task from both the specified event list and the list of blocked
+ * tasks, and places it on a ready queue.
+ *
+ * xTaskRemoveFromEventList()/vTaskRemoveFromUnorderedEventList() will be called
+ * if either an event occurs to unblock a task, or the block timeout period
+ * expires.
+ *
+ * xTaskRemoveFromEventList() is used when the event list is in task priority
+ * order.  It removes the list item from the head of the event list as that will
+ * have the highest priority owning task of all the tasks on the event list.
+ * vTaskRemoveFromUnorderedEventList() is used when the event list is not
+ * ordered and the event list items hold something other than the owning tasks
+ * priority.  In this case the event list item value is updated to the value
+ * passed in the xItemValue parameter.
+ *
+ * @return pdTRUE if the task being removed has a higher priority than the task
+ * making the call, otherwise pdFALSE.
+ */
+BaseType_t xTaskRemoveFromEventList( const List_t * const pxEventList ) PRIVILEGED_FUNCTION;
+void vTaskRemoveFromUnorderedEventList( ListItem_t * pxEventListItem, const TickType_t xItemValue ) PRIVILEGED_FUNCTION;
+
+/*
+ * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE.  IT IS ONLY
+ * INTENDED FOR USE WHEN IMPLEMENTING A PORT OF THE SCHEDULER AND IS
+ * AN INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.
+ *
+ * Sets the pointer to the current TCB to the TCB of the highest priority task
+ * that is ready to run.
+ */
+portDONT_DISCARD void vTaskSwitchContext( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * THESE FUNCTIONS MUST NOT BE USED FROM APPLICATION CODE.  THEY ARE USED BY
+ * THE EVENT BITS MODULE.
+ */
+TickType_t uxTaskResetEventItemValue( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Return the handle of the calling task.
+ */
+TaskHandle_t xTaskGetCurrentTaskHandle( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Shortcut used by the queue implementation to prevent unnecessary call to
+ * taskYIELD();
+ */
+void vTaskMissedYield( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Returns the scheduler state as taskSCHEDULER_RUNNING,
+ * taskSCHEDULER_NOT_STARTED or taskSCHEDULER_SUSPENDED.
+ */
+BaseType_t xTaskGetSchedulerState( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Raises the priority of the mutex holder to that of the calling task should
+ * the mutex holder have a priority less than the calling task.
+ */
+BaseType_t xTaskPriorityInherit( TaskHandle_t const pxMutexHolder ) PRIVILEGED_FUNCTION;
+
+/*
+ * Set the priority of a task back to its proper priority in the case that it
+ * inherited a higher priority while it was holding a semaphore.
+ */
+BaseType_t xTaskPriorityDisinherit( TaskHandle_t const pxMutexHolder ) PRIVILEGED_FUNCTION;
+
+/*
+ * If a higher priority task attempting to obtain a mutex caused a lower
+ * priority task to inherit the higher priority task's priority - but the higher
+ * priority task then timed out without obtaining the mutex, then the lower
+ * priority task will disinherit the priority again - but only down as far as
+ * the highest priority task that is still waiting for the mutex (if there were
+ * more than one task waiting for the mutex).
+ */
+void vTaskPriorityDisinheritAfterTimeout( TaskHandle_t const pxMutexHolder, UBaseType_t uxHighestPriorityWaitingTask ) PRIVILEGED_FUNCTION;
+
+/*
+ * Get the uxTCBNumber assigned to the task referenced by the xTask parameter.
+ */
+UBaseType_t uxTaskGetTaskNumber( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+
+/*
+ * Set the uxTaskNumber of the task referenced by the xTask parameter to
+ * uxHandle.
+ */
+void vTaskSetTaskNumber( TaskHandle_t xTask, const UBaseType_t uxHandle ) PRIVILEGED_FUNCTION;
+
+/*
+ * Only available when configUSE_TICKLESS_IDLE is set to 1.
+ * If tickless mode is being used, or a low power mode is implemented, then
+ * the tick interrupt will not execute during idle periods.  When this is the
+ * case, the tick count value maintained by the scheduler needs to be kept up
+ * to date with the actual execution time by being skipped forward by a time
+ * equal to the idle period.
+ */
+void vTaskStepTick( const TickType_t xTicksToJump ) PRIVILEGED_FUNCTION;
+
+/* Correct the tick count value after the application code has held
+interrupts disabled for an extended period.  xTicksToCatchUp is the number
+of tick interrupts that have been missed due to interrupts being disabled.
+Its value is not computed automatically, so must be computed by the
+application writer.
+
+This function is similar to vTaskStepTick(), however, unlike
+vTaskStepTick(), xTaskCatchUpTicks() may move the tick count forward past a
+time at which a task should be removed from the blocked state.  That means
+tasks may have to be removed from the blocked state as the tick count is
+moved. */
+BaseType_t xTaskCatchUpTicks( TickType_t xTicksToCatchUp ) PRIVILEGED_FUNCTION;
+
+/*
+ * Only available when configUSE_TICKLESS_IDLE is set to 1.
+ * Provided for use within portSUPPRESS_TICKS_AND_SLEEP() to allow the port
+ * specific sleep function to determine if it is ok to proceed with the sleep,
+ * and if it is ok to proceed, if it is ok to sleep indefinitely.
+ *
+ * This function is necessary because portSUPPRESS_TICKS_AND_SLEEP() is only
+ * called with the scheduler suspended, not from within a critical section.  It
+ * is therefore possible for an interrupt to request a context switch between
+ * portSUPPRESS_TICKS_AND_SLEEP() and the low power mode actually being
+ * entered.  eTaskConfirmSleepModeStatus() should be called from a short
+ * critical section between the timer being stopped and the sleep mode being
+ * entered to ensure it is ok to proceed into the sleep mode.
+ */
+eSleepModeStatus eTaskConfirmSleepModeStatus( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * For internal use only.  Increment the mutex held count when a mutex is
+ * taken and return the handle of the task that has taken the mutex.
+ */
+TaskHandle_t pvTaskIncrementMutexHeldCount( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * For internal use only.  Same as vTaskSetTimeOutState(), but without a critial
+ * section.
+ */
+void vTaskInternalSetTimeOutState( TimeOut_t * const pxTimeOut ) PRIVILEGED_FUNCTION;
+
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* INC_TASK_H */
+
+
+
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/timers.h b/Middlewares/Third_Party/FreeRTOS/Source/include/timers.h
new file mode 100644
index 0000000..307ea1f
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/include/timers.h
@@ -0,0 +1,1309 @@
+/*
+ * FreeRTOS Kernel V10.3.1
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef TIMERS_H
+#define TIMERS_H
+
+#ifndef INC_FREERTOS_H
+	#error "include FreeRTOS.h must appear in source files before include timers.h"
+#endif
+
+/*lint -save -e537 This headers are only multiply included if the application code
+happens to also be including task.h. */
+#include "task.h"
+/*lint -restore */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * MACROS AND DEFINITIONS
+ *----------------------------------------------------------*/
+
+/* IDs for commands that can be sent/received on the timer queue.  These are to
+be used solely through the macros that make up the public software timer API,
+as defined below.  The commands that are sent from interrupts must use the
+highest numbers as tmrFIRST_FROM_ISR_COMMAND is used to determine if the task
+or interrupt version of the queue send function should be used. */
+#define tmrCOMMAND_EXECUTE_CALLBACK_FROM_ISR 	( ( BaseType_t ) -2 )
+#define tmrCOMMAND_EXECUTE_CALLBACK				( ( BaseType_t ) -1 )
+#define tmrCOMMAND_START_DONT_TRACE				( ( BaseType_t ) 0 )
+#define tmrCOMMAND_START					    ( ( BaseType_t ) 1 )
+#define tmrCOMMAND_RESET						( ( BaseType_t ) 2 )
+#define tmrCOMMAND_STOP							( ( BaseType_t ) 3 )
+#define tmrCOMMAND_CHANGE_PERIOD				( ( BaseType_t ) 4 )
+#define tmrCOMMAND_DELETE						( ( BaseType_t ) 5 )
+
+#define tmrFIRST_FROM_ISR_COMMAND				( ( BaseType_t ) 6 )
+#define tmrCOMMAND_START_FROM_ISR				( ( BaseType_t ) 6 )
+#define tmrCOMMAND_RESET_FROM_ISR				( ( BaseType_t ) 7 )
+#define tmrCOMMAND_STOP_FROM_ISR				( ( BaseType_t ) 8 )
+#define tmrCOMMAND_CHANGE_PERIOD_FROM_ISR		( ( BaseType_t ) 9 )
+
+
+/**
+ * Type by which software timers are referenced.  For example, a call to
+ * xTimerCreate() returns an TimerHandle_t variable that can then be used to
+ * reference the subject timer in calls to other software timer API functions
+ * (for example, xTimerStart(), xTimerReset(), etc.).
+ */
+struct tmrTimerControl; /* The old naming convention is used to prevent breaking kernel aware debuggers. */
+typedef struct tmrTimerControl * TimerHandle_t;
+
+/*
+ * Defines the prototype to which timer callback functions must conform.
+ */
+typedef void (*TimerCallbackFunction_t)( TimerHandle_t xTimer );
+
+/*
+ * Defines the prototype to which functions used with the
+ * xTimerPendFunctionCallFromISR() function must conform.
+ */
+typedef void (*PendedFunction_t)( void *, uint32_t );
+
+/**
+ * TimerHandle_t xTimerCreate( 	const char * const pcTimerName,
+ * 								TickType_t xTimerPeriodInTicks,
+ * 								UBaseType_t uxAutoReload,
+ * 								void * pvTimerID,
+ * 								TimerCallbackFunction_t pxCallbackFunction );
+ *
+ * Creates a new software timer instance, and returns a handle by which the
+ * created software timer can be referenced.
+ *
+ * Internally, within the FreeRTOS implementation, software timers use a block
+ * of memory, in which the timer data structure is stored.  If a software timer
+ * is created using xTimerCreate() then the required memory is automatically
+ * dynamically allocated inside the xTimerCreate() function.  (see
+ * http://www.freertos.org/a00111.html).  If a software timer is created using
+ * xTimerCreateStatic() then the application writer must provide the memory that
+ * will get used by the software timer.  xTimerCreateStatic() therefore allows a
+ * software timer to be created without using any dynamic memory allocation.
+ *
+ * Timers are created in the dormant state.  The xTimerStart(), xTimerReset(),
+ * xTimerStartFromISR(), xTimerResetFromISR(), xTimerChangePeriod() and
+ * xTimerChangePeriodFromISR() API functions can all be used to transition a
+ * timer into the active state.
+ *
+ * @param pcTimerName A text name that is assigned to the timer.  This is done
+ * purely to assist debugging.  The kernel itself only ever references a timer
+ * by its handle, and never by its name.
+ *
+ * @param xTimerPeriodInTicks The timer period.  The time is defined in tick
+ * periods so the constant portTICK_PERIOD_MS can be used to convert a time that
+ * has been specified in milliseconds.  For example, if the timer must expire
+ * after 100 ticks, then xTimerPeriodInTicks should be set to 100.
+ * Alternatively, if the timer must expire after 500ms, then xPeriod can be set
+ * to ( 500 / portTICK_PERIOD_MS ) provided configTICK_RATE_HZ is less than or
+ * equal to 1000.  Time timer period must be greater than 0.
+ *
+ * @param uxAutoReload If uxAutoReload is set to pdTRUE then the timer will
+ * expire repeatedly with a frequency set by the xTimerPeriodInTicks parameter.
+ * If uxAutoReload is set to pdFALSE then the timer will be a one-shot timer and
+ * enter the dormant state after it expires.
+ *
+ * @param pvTimerID An identifier that is assigned to the timer being created.
+ * Typically this would be used in the timer callback function to identify which
+ * timer expired when the same callback function is assigned to more than one
+ * timer.
+ *
+ * @param pxCallbackFunction The function to call when the timer expires.
+ * Callback functions must have the prototype defined by TimerCallbackFunction_t,
+ * which is	"void vCallbackFunction( TimerHandle_t xTimer );".
+ *
+ * @return If the timer is successfully created then a handle to the newly
+ * created timer is returned.  If the timer cannot be created because there is
+ * insufficient FreeRTOS heap remaining to allocate the timer
+ * structures then NULL is returned.
+ *
+ * Example usage:
+ * @verbatim
+ * #define NUM_TIMERS 5
+ *
+ * // An array to hold handles to the created timers.
+ * TimerHandle_t xTimers[ NUM_TIMERS ];
+ *
+ * // An array to hold a count of the number of times each timer expires.
+ * int32_t lExpireCounters[ NUM_TIMERS ] = { 0 };
+ *
+ * // Define a callback function that will be used by multiple timer instances.
+ * // The callback function does nothing but count the number of times the
+ * // associated timer expires, and stop the timer once the timer has expired
+ * // 10 times.
+ * void vTimerCallback( TimerHandle_t pxTimer )
+ * {
+ * int32_t lArrayIndex;
+ * const int32_t xMaxExpiryCountBeforeStopping = 10;
+ *
+ * 	   // Optionally do something if the pxTimer parameter is NULL.
+ * 	   configASSERT( pxTimer );
+ *
+ *     // Which timer expired?
+ *     lArrayIndex = ( int32_t ) pvTimerGetTimerID( pxTimer );
+ *
+ *     // Increment the number of times that pxTimer has expired.
+ *     lExpireCounters[ lArrayIndex ] += 1;
+ *
+ *     // If the timer has expired 10 times then stop it from running.
+ *     if( lExpireCounters[ lArrayIndex ] == xMaxExpiryCountBeforeStopping )
+ *     {
+ *         // Do not use a block time if calling a timer API function from a
+ *         // timer callback function, as doing so could cause a deadlock!
+ *         xTimerStop( pxTimer, 0 );
+ *     }
+ * }
+ *
+ * void main( void )
+ * {
+ * int32_t x;
+ *
+ *     // Create then start some timers.  Starting the timers before the scheduler
+ *     // has been started means the timers will start running immediately that
+ *     // the scheduler starts.
+ *     for( x = 0; x < NUM_TIMERS; x++ )
+ *     {
+ *         xTimers[ x ] = xTimerCreate(    "Timer",       // Just a text name, not used by the kernel.
+ *                                         ( 100 * x ),   // The timer period in ticks.
+ *                                         pdTRUE,        // The timers will auto-reload themselves when they expire.
+ *                                         ( void * ) x,  // Assign each timer a unique id equal to its array index.
+ *                                         vTimerCallback // Each timer calls the same callback when it expires.
+ *                                     );
+ *
+ *         if( xTimers[ x ] == NULL )
+ *         {
+ *             // The timer was not created.
+ *         }
+ *         else
+ *         {
+ *             // Start the timer.  No block time is specified, and even if one was
+ *             // it would be ignored because the scheduler has not yet been
+ *             // started.
+ *             if( xTimerStart( xTimers[ x ], 0 ) != pdPASS )
+ *             {
+ *                 // The timer could not be set into the Active state.
+ *             }
+ *         }
+ *     }
+ *
+ *     // ...
+ *     // Create tasks here.
+ *     // ...
+ *
+ *     // Starting the scheduler will start the timers running as they have already
+ *     // been set into the active state.
+ *     vTaskStartScheduler();
+ *
+ *     // Should not reach here.
+ *     for( ;; );
+ * }
+ * @endverbatim
+ */
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+	TimerHandle_t xTimerCreate(	const char * const pcTimerName,			/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+								const TickType_t xTimerPeriodInTicks,
+								const UBaseType_t uxAutoReload,
+								void * const pvTimerID,
+								TimerCallbackFunction_t pxCallbackFunction ) PRIVILEGED_FUNCTION;
+#endif
+
+/**
+ * TimerHandle_t xTimerCreateStatic(const char * const pcTimerName,
+ * 									TickType_t xTimerPeriodInTicks,
+ * 									UBaseType_t uxAutoReload,
+ * 									void * pvTimerID,
+ * 									TimerCallbackFunction_t pxCallbackFunction,
+ *									StaticTimer_t *pxTimerBuffer );
+ *
+ * Creates a new software timer instance, and returns a handle by which the
+ * created software timer can be referenced.
+ *
+ * Internally, within the FreeRTOS implementation, software timers use a block
+ * of memory, in which the timer data structure is stored.  If a software timer
+ * is created using xTimerCreate() then the required memory is automatically
+ * dynamically allocated inside the xTimerCreate() function.  (see
+ * http://www.freertos.org/a00111.html).  If a software timer is created using
+ * xTimerCreateStatic() then the application writer must provide the memory that
+ * will get used by the software timer.  xTimerCreateStatic() therefore allows a
+ * software timer to be created without using any dynamic memory allocation.
+ *
+ * Timers are created in the dormant state.  The xTimerStart(), xTimerReset(),
+ * xTimerStartFromISR(), xTimerResetFromISR(), xTimerChangePeriod() and
+ * xTimerChangePeriodFromISR() API functions can all be used to transition a
+ * timer into the active state.
+ *
+ * @param pcTimerName A text name that is assigned to the timer.  This is done
+ * purely to assist debugging.  The kernel itself only ever references a timer
+ * by its handle, and never by its name.
+ *
+ * @param xTimerPeriodInTicks The timer period.  The time is defined in tick
+ * periods so the constant portTICK_PERIOD_MS can be used to convert a time that
+ * has been specified in milliseconds.  For example, if the timer must expire
+ * after 100 ticks, then xTimerPeriodInTicks should be set to 100.
+ * Alternatively, if the timer must expire after 500ms, then xPeriod can be set
+ * to ( 500 / portTICK_PERIOD_MS ) provided configTICK_RATE_HZ is less than or
+ * equal to 1000.  The timer period must be greater than 0.
+ *
+ * @param uxAutoReload If uxAutoReload is set to pdTRUE then the timer will
+ * expire repeatedly with a frequency set by the xTimerPeriodInTicks parameter.
+ * If uxAutoReload is set to pdFALSE then the timer will be a one-shot timer and
+ * enter the dormant state after it expires.
+ *
+ * @param pvTimerID An identifier that is assigned to the timer being created.
+ * Typically this would be used in the timer callback function to identify which
+ * timer expired when the same callback function is assigned to more than one
+ * timer.
+ *
+ * @param pxCallbackFunction The function to call when the timer expires.
+ * Callback functions must have the prototype defined by TimerCallbackFunction_t,
+ * which is "void vCallbackFunction( TimerHandle_t xTimer );".
+ *
+ * @param pxTimerBuffer Must point to a variable of type StaticTimer_t, which
+ * will be then be used to hold the software timer's data structures, removing
+ * the need for the memory to be allocated dynamically.
+ *
+ * @return If the timer is created then a handle to the created timer is
+ * returned.  If pxTimerBuffer was NULL then NULL is returned.
+ *
+ * Example usage:
+ * @verbatim
+ *
+ * // The buffer used to hold the software timer's data structure.
+ * static StaticTimer_t xTimerBuffer;
+ *
+ * // A variable that will be incremented by the software timer's callback
+ * // function.
+ * UBaseType_t uxVariableToIncrement = 0;
+ *
+ * // A software timer callback function that increments a variable passed to
+ * // it when the software timer was created.  After the 5th increment the
+ * // callback function stops the software timer.
+ * static void prvTimerCallback( TimerHandle_t xExpiredTimer )
+ * {
+ * UBaseType_t *puxVariableToIncrement;
+ * BaseType_t xReturned;
+ *
+ *     // Obtain the address of the variable to increment from the timer ID.
+ *     puxVariableToIncrement = ( UBaseType_t * ) pvTimerGetTimerID( xExpiredTimer );
+ *
+ *     // Increment the variable to show the timer callback has executed.
+ *     ( *puxVariableToIncrement )++;
+ *
+ *     // If this callback has executed the required number of times, stop the
+ *     // timer.
+ *     if( *puxVariableToIncrement == 5 )
+ *     {
+ *         // This is called from a timer callback so must not block.
+ *         xTimerStop( xExpiredTimer, staticDONT_BLOCK );
+ *     }
+ * }
+ *
+ *
+ * void main( void )
+ * {
+ *     // Create the software time.  xTimerCreateStatic() has an extra parameter
+ *     // than the normal xTimerCreate() API function.  The parameter is a pointer
+ *     // to the StaticTimer_t structure that will hold the software timer
+ *     // structure.  If the parameter is passed as NULL then the structure will be
+ *     // allocated dynamically, just as if xTimerCreate() had been called.
+ *     xTimer = xTimerCreateStatic( "T1",             // Text name for the task.  Helps debugging only.  Not used by FreeRTOS.
+ *                                  xTimerPeriod,     // The period of the timer in ticks.
+ *                                  pdTRUE,           // This is an auto-reload timer.
+ *                                  ( void * ) &uxVariableToIncrement,    // A variable incremented by the software timer's callback function
+ *                                  prvTimerCallback, // The function to execute when the timer expires.
+ *                                  &xTimerBuffer );  // The buffer that will hold the software timer structure.
+ *
+ *     // The scheduler has not started yet so a block time is not used.
+ *     xReturned = xTimerStart( xTimer, 0 );
+ *
+ *     // ...
+ *     // Create tasks here.
+ *     // ...
+ *
+ *     // Starting the scheduler will start the timers running as they have already
+ *     // been set into the active state.
+ *     vTaskStartScheduler();
+ *
+ *     // Should not reach here.
+ *     for( ;; );
+ * }
+ * @endverbatim
+ */
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+	TimerHandle_t xTimerCreateStatic(	const char * const pcTimerName,			/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+										const TickType_t xTimerPeriodInTicks,
+										const UBaseType_t uxAutoReload,
+										void * const pvTimerID,
+										TimerCallbackFunction_t pxCallbackFunction,
+										StaticTimer_t *pxTimerBuffer ) PRIVILEGED_FUNCTION;
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+/**
+ * void *pvTimerGetTimerID( TimerHandle_t xTimer );
+ *
+ * Returns the ID assigned to the timer.
+ *
+ * IDs are assigned to timers using the pvTimerID parameter of the call to
+ * xTimerCreated() that was used to create the timer, and by calling the
+ * vTimerSetTimerID() API function.
+ *
+ * If the same callback function is assigned to multiple timers then the timer
+ * ID can be used as time specific (timer local) storage.
+ *
+ * @param xTimer The timer being queried.
+ *
+ * @return The ID assigned to the timer being queried.
+ *
+ * Example usage:
+ *
+ * See the xTimerCreate() API function example usage scenario.
+ */
+void *pvTimerGetTimerID( const TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;
+
+/**
+ * void vTimerSetTimerID( TimerHandle_t xTimer, void *pvNewID );
+ *
+ * Sets the ID assigned to the timer.
+ *
+ * IDs are assigned to timers using the pvTimerID parameter of the call to
+ * xTimerCreated() that was used to create the timer.
+ *
+ * If the same callback function is assigned to multiple timers then the timer
+ * ID can be used as time specific (timer local) storage.
+ *
+ * @param xTimer The timer being updated.
+ *
+ * @param pvNewID The ID to assign to the timer.
+ *
+ * Example usage:
+ *
+ * See the xTimerCreate() API function example usage scenario.
+ */
+void vTimerSetTimerID( TimerHandle_t xTimer, void *pvNewID ) PRIVILEGED_FUNCTION;
+
+/**
+ * BaseType_t xTimerIsTimerActive( TimerHandle_t xTimer );
+ *
+ * Queries a timer to see if it is active or dormant.
+ *
+ * A timer will be dormant if:
+ *     1) It has been created but not started, or
+ *     2) It is an expired one-shot timer that has not been restarted.
+ *
+ * Timers are created in the dormant state.  The xTimerStart(), xTimerReset(),
+ * xTimerStartFromISR(), xTimerResetFromISR(), xTimerChangePeriod() and
+ * xTimerChangePeriodFromISR() API functions can all be used to transition a timer into the
+ * active state.
+ *
+ * @param xTimer The timer being queried.
+ *
+ * @return pdFALSE will be returned if the timer is dormant.  A value other than
+ * pdFALSE will be returned if the timer is active.
+ *
+ * Example usage:
+ * @verbatim
+ * // This function assumes xTimer has already been created.
+ * void vAFunction( TimerHandle_t xTimer )
+ * {
+ *     if( xTimerIsTimerActive( xTimer ) != pdFALSE ) // or more simply and equivalently "if( xTimerIsTimerActive( xTimer ) )"
+ *     {
+ *         // xTimer is active, do something.
+ *     }
+ *     else
+ *     {
+ *         // xTimer is not active, do something else.
+ *     }
+ * }
+ * @endverbatim
+ */
+BaseType_t xTimerIsTimerActive( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;
+
+/**
+ * TaskHandle_t xTimerGetTimerDaemonTaskHandle( void );
+ *
+ * Simply returns the handle of the timer service/daemon task.  It it not valid
+ * to call xTimerGetTimerDaemonTaskHandle() before the scheduler has been started.
+ */
+TaskHandle_t xTimerGetTimerDaemonTaskHandle( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * BaseType_t xTimerStart( TimerHandle_t xTimer, TickType_t xTicksToWait );
+ *
+ * Timer functionality is provided by a timer service/daemon task.  Many of the
+ * public FreeRTOS timer API functions send commands to the timer service task
+ * through a queue called the timer command queue.  The timer command queue is
+ * private to the kernel itself and is not directly accessible to application
+ * code.  The length of the timer command queue is set by the
+ * configTIMER_QUEUE_LENGTH configuration constant.
+ *
+ * xTimerStart() starts a timer that was previously created using the
+ * xTimerCreate() API function.  If the timer had already been started and was
+ * already in the active state, then xTimerStart() has equivalent functionality
+ * to the xTimerReset() API function.
+ *
+ * Starting a timer ensures the timer is in the active state.  If the timer
+ * is not stopped, deleted, or reset in the mean time, the callback function
+ * associated with the timer will get called 'n' ticks after xTimerStart() was
+ * called, where 'n' is the timers defined period.
+ *
+ * It is valid to call xTimerStart() before the scheduler has been started, but
+ * when this is done the timer will not actually start until the scheduler is
+ * started, and the timers expiry time will be relative to when the scheduler is
+ * started, not relative to when xTimerStart() was called.
+ *
+ * The configUSE_TIMERS configuration constant must be set to 1 for xTimerStart()
+ * to be available.
+ *
+ * @param xTimer The handle of the timer being started/restarted.
+ *
+ * @param xTicksToWait Specifies the time, in ticks, that the calling task should
+ * be held in the Blocked state to wait for the start command to be successfully
+ * sent to the timer command queue, should the queue already be full when
+ * xTimerStart() was called.  xTicksToWait is ignored if xTimerStart() is called
+ * before the scheduler is started.
+ *
+ * @return pdFAIL will be returned if the start command could not be sent to
+ * the timer command queue even after xTicksToWait ticks had passed.  pdPASS will
+ * be returned if the command was successfully sent to the timer command queue.
+ * When the command is actually processed will depend on the priority of the
+ * timer service/daemon task relative to other tasks in the system, although the
+ * timers expiry time is relative to when xTimerStart() is actually called.  The
+ * timer service/daemon task priority is set by the configTIMER_TASK_PRIORITY
+ * configuration constant.
+ *
+ * Example usage:
+ *
+ * See the xTimerCreate() API function example usage scenario.
+ *
+ */
+#define xTimerStart( xTimer, xTicksToWait ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_START, ( xTaskGetTickCount() ), NULL, ( xTicksToWait ) )
+
+/**
+ * BaseType_t xTimerStop( TimerHandle_t xTimer, TickType_t xTicksToWait );
+ *
+ * Timer functionality is provided by a timer service/daemon task.  Many of the
+ * public FreeRTOS timer API functions send commands to the timer service task
+ * through a queue called the timer command queue.  The timer command queue is
+ * private to the kernel itself and is not directly accessible to application
+ * code.  The length of the timer command queue is set by the
+ * configTIMER_QUEUE_LENGTH configuration constant.
+ *
+ * xTimerStop() stops a timer that was previously started using either of the
+ * The xTimerStart(), xTimerReset(), xTimerStartFromISR(), xTimerResetFromISR(),
+ * xTimerChangePeriod() or xTimerChangePeriodFromISR() API functions.
+ *
+ * Stopping a timer ensures the timer is not in the active state.
+ *
+ * The configUSE_TIMERS configuration constant must be set to 1 for xTimerStop()
+ * to be available.
+ *
+ * @param xTimer The handle of the timer being stopped.
+ *
+ * @param xTicksToWait Specifies the time, in ticks, that the calling task should
+ * be held in the Blocked state to wait for the stop command to be successfully
+ * sent to the timer command queue, should the queue already be full when
+ * xTimerStop() was called.  xTicksToWait is ignored if xTimerStop() is called
+ * before the scheduler is started.
+ *
+ * @return pdFAIL will be returned if the stop command could not be sent to
+ * the timer command queue even after xTicksToWait ticks had passed.  pdPASS will
+ * be returned if the command was successfully sent to the timer command queue.
+ * When the command is actually processed will depend on the priority of the
+ * timer service/daemon task relative to other tasks in the system.  The timer
+ * service/daemon task priority is set by the configTIMER_TASK_PRIORITY
+ * configuration constant.
+ *
+ * Example usage:
+ *
+ * See the xTimerCreate() API function example usage scenario.
+ *
+ */
+#define xTimerStop( xTimer, xTicksToWait ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_STOP, 0U, NULL, ( xTicksToWait ) )
+
+/**
+ * BaseType_t xTimerChangePeriod( 	TimerHandle_t xTimer,
+ *										TickType_t xNewPeriod,
+ *										TickType_t xTicksToWait );
+ *
+ * Timer functionality is provided by a timer service/daemon task.  Many of the
+ * public FreeRTOS timer API functions send commands to the timer service task
+ * through a queue called the timer command queue.  The timer command queue is
+ * private to the kernel itself and is not directly accessible to application
+ * code.  The length of the timer command queue is set by the
+ * configTIMER_QUEUE_LENGTH configuration constant.
+ *
+ * xTimerChangePeriod() changes the period of a timer that was previously
+ * created using the xTimerCreate() API function.
+ *
+ * xTimerChangePeriod() can be called to change the period of an active or
+ * dormant state timer.
+ *
+ * The configUSE_TIMERS configuration constant must be set to 1 for
+ * xTimerChangePeriod() to be available.
+ *
+ * @param xTimer The handle of the timer that is having its period changed.
+ *
+ * @param xNewPeriod The new period for xTimer. Timer periods are specified in
+ * tick periods, so the constant portTICK_PERIOD_MS can be used to convert a time
+ * that has been specified in milliseconds.  For example, if the timer must
+ * expire after 100 ticks, then xNewPeriod should be set to 100.  Alternatively,
+ * if the timer must expire after 500ms, then xNewPeriod can be set to
+ * ( 500 / portTICK_PERIOD_MS ) provided configTICK_RATE_HZ is less than
+ * or equal to 1000.
+ *
+ * @param xTicksToWait Specifies the time, in ticks, that the calling task should
+ * be held in the Blocked state to wait for the change period command to be
+ * successfully sent to the timer command queue, should the queue already be
+ * full when xTimerChangePeriod() was called.  xTicksToWait is ignored if
+ * xTimerChangePeriod() is called before the scheduler is started.
+ *
+ * @return pdFAIL will be returned if the change period command could not be
+ * sent to the timer command queue even after xTicksToWait ticks had passed.
+ * pdPASS will be returned if the command was successfully sent to the timer
+ * command queue.  When the command is actually processed will depend on the
+ * priority of the timer service/daemon task relative to other tasks in the
+ * system.  The timer service/daemon task priority is set by the
+ * configTIMER_TASK_PRIORITY configuration constant.
+ *
+ * Example usage:
+ * @verbatim
+ * // This function assumes xTimer has already been created.  If the timer
+ * // referenced by xTimer is already active when it is called, then the timer
+ * // is deleted.  If the timer referenced by xTimer is not active when it is
+ * // called, then the period of the timer is set to 500ms and the timer is
+ * // started.
+ * void vAFunction( TimerHandle_t xTimer )
+ * {
+ *     if( xTimerIsTimerActive( xTimer ) != pdFALSE ) // or more simply and equivalently "if( xTimerIsTimerActive( xTimer ) )"
+ *     {
+ *         // xTimer is already active - delete it.
+ *         xTimerDelete( xTimer );
+ *     }
+ *     else
+ *     {
+ *         // xTimer is not active, change its period to 500ms.  This will also
+ *         // cause the timer to start.  Block for a maximum of 100 ticks if the
+ *         // change period command cannot immediately be sent to the timer
+ *         // command queue.
+ *         if( xTimerChangePeriod( xTimer, 500 / portTICK_PERIOD_MS, 100 ) == pdPASS )
+ *         {
+ *             // The command was successfully sent.
+ *         }
+ *         else
+ *         {
+ *             // The command could not be sent, even after waiting for 100 ticks
+ *             // to pass.  Take appropriate action here.
+ *         }
+ *     }
+ * }
+ * @endverbatim
+ */
+ #define xTimerChangePeriod( xTimer, xNewPeriod, xTicksToWait ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_CHANGE_PERIOD, ( xNewPeriod ), NULL, ( xTicksToWait ) )
+
+/**
+ * BaseType_t xTimerDelete( TimerHandle_t xTimer, TickType_t xTicksToWait );
+ *
+ * Timer functionality is provided by a timer service/daemon task.  Many of the
+ * public FreeRTOS timer API functions send commands to the timer service task
+ * through a queue called the timer command queue.  The timer command queue is
+ * private to the kernel itself and is not directly accessible to application
+ * code.  The length of the timer command queue is set by the
+ * configTIMER_QUEUE_LENGTH configuration constant.
+ *
+ * xTimerDelete() deletes a timer that was previously created using the
+ * xTimerCreate() API function.
+ *
+ * The configUSE_TIMERS configuration constant must be set to 1 for
+ * xTimerDelete() to be available.
+ *
+ * @param xTimer The handle of the timer being deleted.
+ *
+ * @param xTicksToWait Specifies the time, in ticks, that the calling task should
+ * be held in the Blocked state to wait for the delete command to be
+ * successfully sent to the timer command queue, should the queue already be
+ * full when xTimerDelete() was called.  xTicksToWait is ignored if xTimerDelete()
+ * is called before the scheduler is started.
+ *
+ * @return pdFAIL will be returned if the delete command could not be sent to
+ * the timer command queue even after xTicksToWait ticks had passed.  pdPASS will
+ * be returned if the command was successfully sent to the timer command queue.
+ * When the command is actually processed will depend on the priority of the
+ * timer service/daemon task relative to other tasks in the system.  The timer
+ * service/daemon task priority is set by the configTIMER_TASK_PRIORITY
+ * configuration constant.
+ *
+ * Example usage:
+ *
+ * See the xTimerChangePeriod() API function example usage scenario.
+ */
+#define xTimerDelete( xTimer, xTicksToWait ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_DELETE, 0U, NULL, ( xTicksToWait ) )
+
+/**
+ * BaseType_t xTimerReset( TimerHandle_t xTimer, TickType_t xTicksToWait );
+ *
+ * Timer functionality is provided by a timer service/daemon task.  Many of the
+ * public FreeRTOS timer API functions send commands to the timer service task
+ * through a queue called the timer command queue.  The timer command queue is
+ * private to the kernel itself and is not directly accessible to application
+ * code.  The length of the timer command queue is set by the
+ * configTIMER_QUEUE_LENGTH configuration constant.
+ *
+ * xTimerReset() re-starts a timer that was previously created using the
+ * xTimerCreate() API function.  If the timer had already been started and was
+ * already in the active state, then xTimerReset() will cause the timer to
+ * re-evaluate its expiry time so that it is relative to when xTimerReset() was
+ * called.  If the timer was in the dormant state then xTimerReset() has
+ * equivalent functionality to the xTimerStart() API function.
+ *
+ * Resetting a timer ensures the timer is in the active state.  If the timer
+ * is not stopped, deleted, or reset in the mean time, the callback function
+ * associated with the timer will get called 'n' ticks after xTimerReset() was
+ * called, where 'n' is the timers defined period.
+ *
+ * It is valid to call xTimerReset() before the scheduler has been started, but
+ * when this is done the timer will not actually start until the scheduler is
+ * started, and the timers expiry time will be relative to when the scheduler is
+ * started, not relative to when xTimerReset() was called.
+ *
+ * The configUSE_TIMERS configuration constant must be set to 1 for xTimerReset()
+ * to be available.
+ *
+ * @param xTimer The handle of the timer being reset/started/restarted.
+ *
+ * @param xTicksToWait Specifies the time, in ticks, that the calling task should
+ * be held in the Blocked state to wait for the reset command to be successfully
+ * sent to the timer command queue, should the queue already be full when
+ * xTimerReset() was called.  xTicksToWait is ignored if xTimerReset() is called
+ * before the scheduler is started.
+ *
+ * @return pdFAIL will be returned if the reset command could not be sent to
+ * the timer command queue even after xTicksToWait ticks had passed.  pdPASS will
+ * be returned if the command was successfully sent to the timer command queue.
+ * When the command is actually processed will depend on the priority of the
+ * timer service/daemon task relative to other tasks in the system, although the
+ * timers expiry time is relative to when xTimerStart() is actually called.  The
+ * timer service/daemon task priority is set by the configTIMER_TASK_PRIORITY
+ * configuration constant.
+ *
+ * Example usage:
+ * @verbatim
+ * // When a key is pressed, an LCD back-light is switched on.  If 5 seconds pass
+ * // without a key being pressed, then the LCD back-light is switched off.  In
+ * // this case, the timer is a one-shot timer.
+ *
+ * TimerHandle_t xBacklightTimer = NULL;
+ *
+ * // The callback function assigned to the one-shot timer.  In this case the
+ * // parameter is not used.
+ * void vBacklightTimerCallback( TimerHandle_t pxTimer )
+ * {
+ *     // The timer expired, therefore 5 seconds must have passed since a key
+ *     // was pressed.  Switch off the LCD back-light.
+ *     vSetBacklightState( BACKLIGHT_OFF );
+ * }
+ *
+ * // The key press event handler.
+ * void vKeyPressEventHandler( char cKey )
+ * {
+ *     // Ensure the LCD back-light is on, then reset the timer that is
+ *     // responsible for turning the back-light off after 5 seconds of
+ *     // key inactivity.  Wait 10 ticks for the command to be successfully sent
+ *     // if it cannot be sent immediately.
+ *     vSetBacklightState( BACKLIGHT_ON );
+ *     if( xTimerReset( xBacklightTimer, 100 ) != pdPASS )
+ *     {
+ *         // The reset command was not executed successfully.  Take appropriate
+ *         // action here.
+ *     }
+ *
+ *     // Perform the rest of the key processing here.
+ * }
+ *
+ * void main( void )
+ * {
+ * int32_t x;
+ *
+ *     // Create then start the one-shot timer that is responsible for turning
+ *     // the back-light off if no keys are pressed within a 5 second period.
+ *     xBacklightTimer = xTimerCreate( "BacklightTimer",           // Just a text name, not used by the kernel.
+ *                                     ( 5000 / portTICK_PERIOD_MS), // The timer period in ticks.
+ *                                     pdFALSE,                    // The timer is a one-shot timer.
+ *                                     0,                          // The id is not used by the callback so can take any value.
+ *                                     vBacklightTimerCallback     // The callback function that switches the LCD back-light off.
+ *                                   );
+ *
+ *     if( xBacklightTimer == NULL )
+ *     {
+ *         // The timer was not created.
+ *     }
+ *     else
+ *     {
+ *         // Start the timer.  No block time is specified, and even if one was
+ *         // it would be ignored because the scheduler has not yet been
+ *         // started.
+ *         if( xTimerStart( xBacklightTimer, 0 ) != pdPASS )
+ *         {
+ *             // The timer could not be set into the Active state.
+ *         }
+ *     }
+ *
+ *     // ...
+ *     // Create tasks here.
+ *     // ...
+ *
+ *     // Starting the scheduler will start the timer running as it has already
+ *     // been set into the active state.
+ *     vTaskStartScheduler();
+ *
+ *     // Should not reach here.
+ *     for( ;; );
+ * }
+ * @endverbatim
+ */
+#define xTimerReset( xTimer, xTicksToWait ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_RESET, ( xTaskGetTickCount() ), NULL, ( xTicksToWait ) )
+
+/**
+ * BaseType_t xTimerStartFromISR( 	TimerHandle_t xTimer,
+ *									BaseType_t *pxHigherPriorityTaskWoken );
+ *
+ * A version of xTimerStart() that can be called from an interrupt service
+ * routine.
+ *
+ * @param xTimer The handle of the timer being started/restarted.
+ *
+ * @param pxHigherPriorityTaskWoken The timer service/daemon task spends most
+ * of its time in the Blocked state, waiting for messages to arrive on the timer
+ * command queue.  Calling xTimerStartFromISR() writes a message to the timer
+ * command queue, so has the potential to transition the timer service/daemon
+ * task out of the Blocked state.  If calling xTimerStartFromISR() causes the
+ * timer service/daemon task to leave the Blocked state, and the timer service/
+ * daemon task has a priority equal to or greater than the currently executing
+ * task (the task that was interrupted), then *pxHigherPriorityTaskWoken will
+ * get set to pdTRUE internally within the xTimerStartFromISR() function.  If
+ * xTimerStartFromISR() sets this value to pdTRUE then a context switch should
+ * be performed before the interrupt exits.
+ *
+ * @return pdFAIL will be returned if the start command could not be sent to
+ * the timer command queue.  pdPASS will be returned if the command was
+ * successfully sent to the timer command queue.  When the command is actually
+ * processed will depend on the priority of the timer service/daemon task
+ * relative to other tasks in the system, although the timers expiry time is
+ * relative to when xTimerStartFromISR() is actually called.  The timer
+ * service/daemon task priority is set by the configTIMER_TASK_PRIORITY
+ * configuration constant.
+ *
+ * Example usage:
+ * @verbatim
+ * // This scenario assumes xBacklightTimer has already been created.  When a
+ * // key is pressed, an LCD back-light is switched on.  If 5 seconds pass
+ * // without a key being pressed, then the LCD back-light is switched off.  In
+ * // this case, the timer is a one-shot timer, and unlike the example given for
+ * // the xTimerReset() function, the key press event handler is an interrupt
+ * // service routine.
+ *
+ * // The callback function assigned to the one-shot timer.  In this case the
+ * // parameter is not used.
+ * void vBacklightTimerCallback( TimerHandle_t pxTimer )
+ * {
+ *     // The timer expired, therefore 5 seconds must have passed since a key
+ *     // was pressed.  Switch off the LCD back-light.
+ *     vSetBacklightState( BACKLIGHT_OFF );
+ * }
+ *
+ * // The key press interrupt service routine.
+ * void vKeyPressEventInterruptHandler( void )
+ * {
+ * BaseType_t xHigherPriorityTaskWoken = pdFALSE;
+ *
+ *     // Ensure the LCD back-light is on, then restart the timer that is
+ *     // responsible for turning the back-light off after 5 seconds of
+ *     // key inactivity.  This is an interrupt service routine so can only
+ *     // call FreeRTOS API functions that end in "FromISR".
+ *     vSetBacklightState( BACKLIGHT_ON );
+ *
+ *     // xTimerStartFromISR() or xTimerResetFromISR() could be called here
+ *     // as both cause the timer to re-calculate its expiry time.
+ *     // xHigherPriorityTaskWoken was initialised to pdFALSE when it was
+ *     // declared (in this function).
+ *     if( xTimerStartFromISR( xBacklightTimer, &xHigherPriorityTaskWoken ) != pdPASS )
+ *     {
+ *         // The start command was not executed successfully.  Take appropriate
+ *         // action here.
+ *     }
+ *
+ *     // Perform the rest of the key processing here.
+ *
+ *     // If xHigherPriorityTaskWoken equals pdTRUE, then a context switch
+ *     // should be performed.  The syntax required to perform a context switch
+ *     // from inside an ISR varies from port to port, and from compiler to
+ *     // compiler.  Inspect the demos for the port you are using to find the
+ *     // actual syntax required.
+ *     if( xHigherPriorityTaskWoken != pdFALSE )
+ *     {
+ *         // Call the interrupt safe yield function here (actual function
+ *         // depends on the FreeRTOS port being used).
+ *     }
+ * }
+ * @endverbatim
+ */
+#define xTimerStartFromISR( xTimer, pxHigherPriorityTaskWoken ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_START_FROM_ISR, ( xTaskGetTickCountFromISR() ), ( pxHigherPriorityTaskWoken ), 0U )
+
+/**
+ * BaseType_t xTimerStopFromISR( 	TimerHandle_t xTimer,
+ *									BaseType_t *pxHigherPriorityTaskWoken );
+ *
+ * A version of xTimerStop() that can be called from an interrupt service
+ * routine.
+ *
+ * @param xTimer The handle of the timer being stopped.
+ *
+ * @param pxHigherPriorityTaskWoken The timer service/daemon task spends most
+ * of its time in the Blocked state, waiting for messages to arrive on the timer
+ * command queue.  Calling xTimerStopFromISR() writes a message to the timer
+ * command queue, so has the potential to transition the timer service/daemon
+ * task out of the Blocked state.  If calling xTimerStopFromISR() causes the
+ * timer service/daemon task to leave the Blocked state, and the timer service/
+ * daemon task has a priority equal to or greater than the currently executing
+ * task (the task that was interrupted), then *pxHigherPriorityTaskWoken will
+ * get set to pdTRUE internally within the xTimerStopFromISR() function.  If
+ * xTimerStopFromISR() sets this value to pdTRUE then a context switch should
+ * be performed before the interrupt exits.
+ *
+ * @return pdFAIL will be returned if the stop command could not be sent to
+ * the timer command queue.  pdPASS will be returned if the command was
+ * successfully sent to the timer command queue.  When the command is actually
+ * processed will depend on the priority of the timer service/daemon task
+ * relative to other tasks in the system.  The timer service/daemon task
+ * priority is set by the configTIMER_TASK_PRIORITY configuration constant.
+ *
+ * Example usage:
+ * @verbatim
+ * // This scenario assumes xTimer has already been created and started.  When
+ * // an interrupt occurs, the timer should be simply stopped.
+ *
+ * // The interrupt service routine that stops the timer.
+ * void vAnExampleInterruptServiceRoutine( void )
+ * {
+ * BaseType_t xHigherPriorityTaskWoken = pdFALSE;
+ *
+ *     // The interrupt has occurred - simply stop the timer.
+ *     // xHigherPriorityTaskWoken was set to pdFALSE where it was defined
+ *     // (within this function).  As this is an interrupt service routine, only
+ *     // FreeRTOS API functions that end in "FromISR" can be used.
+ *     if( xTimerStopFromISR( xTimer, &xHigherPriorityTaskWoken ) != pdPASS )
+ *     {
+ *         // The stop command was not executed successfully.  Take appropriate
+ *         // action here.
+ *     }
+ *
+ *     // If xHigherPriorityTaskWoken equals pdTRUE, then a context switch
+ *     // should be performed.  The syntax required to perform a context switch
+ *     // from inside an ISR varies from port to port, and from compiler to
+ *     // compiler.  Inspect the demos for the port you are using to find the
+ *     // actual syntax required.
+ *     if( xHigherPriorityTaskWoken != pdFALSE )
+ *     {
+ *         // Call the interrupt safe yield function here (actual function
+ *         // depends on the FreeRTOS port being used).
+ *     }
+ * }
+ * @endverbatim
+ */
+#define xTimerStopFromISR( xTimer, pxHigherPriorityTaskWoken ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_STOP_FROM_ISR, 0, ( pxHigherPriorityTaskWoken ), 0U )
+
+/**
+ * BaseType_t xTimerChangePeriodFromISR( TimerHandle_t xTimer,
+ *										 TickType_t xNewPeriod,
+ *										 BaseType_t *pxHigherPriorityTaskWoken );
+ *
+ * A version of xTimerChangePeriod() that can be called from an interrupt
+ * service routine.
+ *
+ * @param xTimer The handle of the timer that is having its period changed.
+ *
+ * @param xNewPeriod The new period for xTimer. Timer periods are specified in
+ * tick periods, so the constant portTICK_PERIOD_MS can be used to convert a time
+ * that has been specified in milliseconds.  For example, if the timer must
+ * expire after 100 ticks, then xNewPeriod should be set to 100.  Alternatively,
+ * if the timer must expire after 500ms, then xNewPeriod can be set to
+ * ( 500 / portTICK_PERIOD_MS ) provided configTICK_RATE_HZ is less than
+ * or equal to 1000.
+ *
+ * @param pxHigherPriorityTaskWoken The timer service/daemon task spends most
+ * of its time in the Blocked state, waiting for messages to arrive on the timer
+ * command queue.  Calling xTimerChangePeriodFromISR() writes a message to the
+ * timer command queue, so has the potential to transition the timer service/
+ * daemon task out of the Blocked state.  If calling xTimerChangePeriodFromISR()
+ * causes the timer service/daemon task to leave the Blocked state, and the
+ * timer service/daemon task has a priority equal to or greater than the
+ * currently executing task (the task that was interrupted), then
+ * *pxHigherPriorityTaskWoken will get set to pdTRUE internally within the
+ * xTimerChangePeriodFromISR() function.  If xTimerChangePeriodFromISR() sets
+ * this value to pdTRUE then a context switch should be performed before the
+ * interrupt exits.
+ *
+ * @return pdFAIL will be returned if the command to change the timers period
+ * could not be sent to the timer command queue.  pdPASS will be returned if the
+ * command was successfully sent to the timer command queue.  When the command
+ * is actually processed will depend on the priority of the timer service/daemon
+ * task relative to other tasks in the system.  The timer service/daemon task
+ * priority is set by the configTIMER_TASK_PRIORITY configuration constant.
+ *
+ * Example usage:
+ * @verbatim
+ * // This scenario assumes xTimer has already been created and started.  When
+ * // an interrupt occurs, the period of xTimer should be changed to 500ms.
+ *
+ * // The interrupt service routine that changes the period of xTimer.
+ * void vAnExampleInterruptServiceRoutine( void )
+ * {
+ * BaseType_t xHigherPriorityTaskWoken = pdFALSE;
+ *
+ *     // The interrupt has occurred - change the period of xTimer to 500ms.
+ *     // xHigherPriorityTaskWoken was set to pdFALSE where it was defined
+ *     // (within this function).  As this is an interrupt service routine, only
+ *     // FreeRTOS API functions that end in "FromISR" can be used.
+ *     if( xTimerChangePeriodFromISR( xTimer, &xHigherPriorityTaskWoken ) != pdPASS )
+ *     {
+ *         // The command to change the timers period was not executed
+ *         // successfully.  Take appropriate action here.
+ *     }
+ *
+ *     // If xHigherPriorityTaskWoken equals pdTRUE, then a context switch
+ *     // should be performed.  The syntax required to perform a context switch
+ *     // from inside an ISR varies from port to port, and from compiler to
+ *     // compiler.  Inspect the demos for the port you are using to find the
+ *     // actual syntax required.
+ *     if( xHigherPriorityTaskWoken != pdFALSE )
+ *     {
+ *         // Call the interrupt safe yield function here (actual function
+ *         // depends on the FreeRTOS port being used).
+ *     }
+ * }
+ * @endverbatim
+ */
+#define xTimerChangePeriodFromISR( xTimer, xNewPeriod, pxHigherPriorityTaskWoken ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_CHANGE_PERIOD_FROM_ISR, ( xNewPeriod ), ( pxHigherPriorityTaskWoken ), 0U )
+
+/**
+ * BaseType_t xTimerResetFromISR( 	TimerHandle_t xTimer,
+ *									BaseType_t *pxHigherPriorityTaskWoken );
+ *
+ * A version of xTimerReset() that can be called from an interrupt service
+ * routine.
+ *
+ * @param xTimer The handle of the timer that is to be started, reset, or
+ * restarted.
+ *
+ * @param pxHigherPriorityTaskWoken The timer service/daemon task spends most
+ * of its time in the Blocked state, waiting for messages to arrive on the timer
+ * command queue.  Calling xTimerResetFromISR() writes a message to the timer
+ * command queue, so has the potential to transition the timer service/daemon
+ * task out of the Blocked state.  If calling xTimerResetFromISR() causes the
+ * timer service/daemon task to leave the Blocked state, and the timer service/
+ * daemon task has a priority equal to or greater than the currently executing
+ * task (the task that was interrupted), then *pxHigherPriorityTaskWoken will
+ * get set to pdTRUE internally within the xTimerResetFromISR() function.  If
+ * xTimerResetFromISR() sets this value to pdTRUE then a context switch should
+ * be performed before the interrupt exits.
+ *
+ * @return pdFAIL will be returned if the reset command could not be sent to
+ * the timer command queue.  pdPASS will be returned if the command was
+ * successfully sent to the timer command queue.  When the command is actually
+ * processed will depend on the priority of the timer service/daemon task
+ * relative to other tasks in the system, although the timers expiry time is
+ * relative to when xTimerResetFromISR() is actually called.  The timer service/daemon
+ * task priority is set by the configTIMER_TASK_PRIORITY configuration constant.
+ *
+ * Example usage:
+ * @verbatim
+ * // This scenario assumes xBacklightTimer has already been created.  When a
+ * // key is pressed, an LCD back-light is switched on.  If 5 seconds pass
+ * // without a key being pressed, then the LCD back-light is switched off.  In
+ * // this case, the timer is a one-shot timer, and unlike the example given for
+ * // the xTimerReset() function, the key press event handler is an interrupt
+ * // service routine.
+ *
+ * // The callback function assigned to the one-shot timer.  In this case the
+ * // parameter is not used.
+ * void vBacklightTimerCallback( TimerHandle_t pxTimer )
+ * {
+ *     // The timer expired, therefore 5 seconds must have passed since a key
+ *     // was pressed.  Switch off the LCD back-light.
+ *     vSetBacklightState( BACKLIGHT_OFF );
+ * }
+ *
+ * // The key press interrupt service routine.
+ * void vKeyPressEventInterruptHandler( void )
+ * {
+ * BaseType_t xHigherPriorityTaskWoken = pdFALSE;
+ *
+ *     // Ensure the LCD back-light is on, then reset the timer that is
+ *     // responsible for turning the back-light off after 5 seconds of
+ *     // key inactivity.  This is an interrupt service routine so can only
+ *     // call FreeRTOS API functions that end in "FromISR".
+ *     vSetBacklightState( BACKLIGHT_ON );
+ *
+ *     // xTimerStartFromISR() or xTimerResetFromISR() could be called here
+ *     // as both cause the timer to re-calculate its expiry time.
+ *     // xHigherPriorityTaskWoken was initialised to pdFALSE when it was
+ *     // declared (in this function).
+ *     if( xTimerResetFromISR( xBacklightTimer, &xHigherPriorityTaskWoken ) != pdPASS )
+ *     {
+ *         // The reset command was not executed successfully.  Take appropriate
+ *         // action here.
+ *     }
+ *
+ *     // Perform the rest of the key processing here.
+ *
+ *     // If xHigherPriorityTaskWoken equals pdTRUE, then a context switch
+ *     // should be performed.  The syntax required to perform a context switch
+ *     // from inside an ISR varies from port to port, and from compiler to
+ *     // compiler.  Inspect the demos for the port you are using to find the
+ *     // actual syntax required.
+ *     if( xHigherPriorityTaskWoken != pdFALSE )
+ *     {
+ *         // Call the interrupt safe yield function here (actual function
+ *         // depends on the FreeRTOS port being used).
+ *     }
+ * }
+ * @endverbatim
+ */
+#define xTimerResetFromISR( xTimer, pxHigherPriorityTaskWoken ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_RESET_FROM_ISR, ( xTaskGetTickCountFromISR() ), ( pxHigherPriorityTaskWoken ), 0U )
+
+
+/**
+ * BaseType_t xTimerPendFunctionCallFromISR( PendedFunction_t xFunctionToPend,
+ *                                          void *pvParameter1,
+ *                                          uint32_t ulParameter2,
+ *                                          BaseType_t *pxHigherPriorityTaskWoken );
+ *
+ *
+ * Used from application interrupt service routines to defer the execution of a
+ * function to the RTOS daemon task (the timer service task, hence this function
+ * is implemented in timers.c and is prefixed with 'Timer').
+ *
+ * Ideally an interrupt service routine (ISR) is kept as short as possible, but
+ * sometimes an ISR either has a lot of processing to do, or needs to perform
+ * processing that is not deterministic.  In these cases
+ * xTimerPendFunctionCallFromISR() can be used to defer processing of a function
+ * to the RTOS daemon task.
+ *
+ * A mechanism is provided that allows the interrupt to return directly to the
+ * task that will subsequently execute the pended callback function.  This
+ * allows the callback function to execute contiguously in time with the
+ * interrupt - just as if the callback had executed in the interrupt itself.
+ *
+ * @param xFunctionToPend The function to execute from the timer service/
+ * daemon task.  The function must conform to the PendedFunction_t
+ * prototype.
+ *
+ * @param pvParameter1 The value of the callback function's first parameter.
+ * The parameter has a void * type to allow it to be used to pass any type.
+ * For example, unsigned longs can be cast to a void *, or the void * can be
+ * used to point to a structure.
+ *
+ * @param ulParameter2 The value of the callback function's second parameter.
+ *
+ * @param pxHigherPriorityTaskWoken As mentioned above, calling this function
+ * will result in a message being sent to the timer daemon task.  If the
+ * priority of the timer daemon task (which is set using
+ * configTIMER_TASK_PRIORITY in FreeRTOSConfig.h) is higher than the priority of
+ * the currently running task (the task the interrupt interrupted) then
+ * *pxHigherPriorityTaskWoken will be set to pdTRUE within
+ * xTimerPendFunctionCallFromISR(), indicating that a context switch should be
+ * requested before the interrupt exits.  For that reason
+ * *pxHigherPriorityTaskWoken must be initialised to pdFALSE.  See the
+ * example code below.
+ *
+ * @return pdPASS is returned if the message was successfully sent to the
+ * timer daemon task, otherwise pdFALSE is returned.
+ *
+ * Example usage:
+ * @verbatim
+ *
+ *	// The callback function that will execute in the context of the daemon task.
+ *  // Note callback functions must all use this same prototype.
+ *  void vProcessInterface( void *pvParameter1, uint32_t ulParameter2 )
+ *	{
+ *		BaseType_t xInterfaceToService;
+ *
+ *		// The interface that requires servicing is passed in the second
+ *      // parameter.  The first parameter is not used in this case.
+ *		xInterfaceToService = ( BaseType_t ) ulParameter2;
+ *
+ *		// ...Perform the processing here...
+ *	}
+ *
+ *	// An ISR that receives data packets from multiple interfaces
+ *  void vAnISR( void )
+ *	{
+ *		BaseType_t xInterfaceToService, xHigherPriorityTaskWoken;
+ *
+ *		// Query the hardware to determine which interface needs processing.
+ *		xInterfaceToService = prvCheckInterfaces();
+ *
+ *      // The actual processing is to be deferred to a task.  Request the
+ *      // vProcessInterface() callback function is executed, passing in the
+ *		// number of the interface that needs processing.  The interface to
+ *		// service is passed in the second parameter.  The first parameter is
+ *		// not used in this case.
+ *		xHigherPriorityTaskWoken = pdFALSE;
+ *		xTimerPendFunctionCallFromISR( vProcessInterface, NULL, ( uint32_t ) xInterfaceToService, &xHigherPriorityTaskWoken );
+ *
+ *		// If xHigherPriorityTaskWoken is now set to pdTRUE then a context
+ *		// switch should be requested.  The macro used is port specific and will
+ *		// be either portYIELD_FROM_ISR() or portEND_SWITCHING_ISR() - refer to
+ *		// the documentation page for the port being used.
+ *		portYIELD_FROM_ISR( xHigherPriorityTaskWoken );
+ *
+ *	}
+ * @endverbatim
+ */
+BaseType_t xTimerPendFunctionCallFromISR( PendedFunction_t xFunctionToPend, void *pvParameter1, uint32_t ulParameter2, BaseType_t *pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+
+ /**
+  * BaseType_t xTimerPendFunctionCall( PendedFunction_t xFunctionToPend,
+  *                                    void *pvParameter1,
+  *                                    uint32_t ulParameter2,
+  *                                    TickType_t xTicksToWait );
+  *
+  *
+  * Used to defer the execution of a function to the RTOS daemon task (the timer
+  * service task, hence this function is implemented in timers.c and is prefixed
+  * with 'Timer').
+  *
+  * @param xFunctionToPend The function to execute from the timer service/
+  * daemon task.  The function must conform to the PendedFunction_t
+  * prototype.
+  *
+  * @param pvParameter1 The value of the callback function's first parameter.
+  * The parameter has a void * type to allow it to be used to pass any type.
+  * For example, unsigned longs can be cast to a void *, or the void * can be
+  * used to point to a structure.
+  *
+  * @param ulParameter2 The value of the callback function's second parameter.
+  *
+  * @param xTicksToWait Calling this function will result in a message being
+  * sent to the timer daemon task on a queue.  xTicksToWait is the amount of
+  * time the calling task should remain in the Blocked state (so not using any
+  * processing time) for space to become available on the timer queue if the
+  * queue is found to be full.
+  *
+  * @return pdPASS is returned if the message was successfully sent to the
+  * timer daemon task, otherwise pdFALSE is returned.
+  *
+  */
+BaseType_t xTimerPendFunctionCall( PendedFunction_t xFunctionToPend, void *pvParameter1, uint32_t ulParameter2, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+/**
+ * const char * const pcTimerGetName( TimerHandle_t xTimer );
+ *
+ * Returns the name that was assigned to a timer when the timer was created.
+ *
+ * @param xTimer The handle of the timer being queried.
+ *
+ * @return The name assigned to the timer specified by the xTimer parameter.
+ */
+const char * pcTimerGetName( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+
+/**
+ * void vTimerSetReloadMode( TimerHandle_t xTimer, const UBaseType_t uxAutoReload );
+ *
+ * Updates a timer to be either an auto-reload timer, in which case the timer
+ * automatically resets itself each time it expires, or a one-shot timer, in
+ * which case the timer will only expire once unless it is manually restarted.
+ *
+ * @param xTimer The handle of the timer being updated.
+ *
+ * @param uxAutoReload If uxAutoReload is set to pdTRUE then the timer will
+ * expire repeatedly with a frequency set by the timer's period (see the
+ * xTimerPeriodInTicks parameter of the xTimerCreate() API function).  If
+ * uxAutoReload is set to pdFALSE then the timer will be a one-shot timer and
+ * enter the dormant state after it expires.
+ */
+void vTimerSetReloadMode( TimerHandle_t xTimer, const UBaseType_t uxAutoReload ) PRIVILEGED_FUNCTION;
+
+/**
+* UBaseType_t uxTimerGetReloadMode( TimerHandle_t xTimer );
+*
+* Queries a timer to determine if it is an auto-reload timer, in which case the timer
+* automatically resets itself each time it expires, or a one-shot timer, in
+* which case the timer will only expire once unless it is manually restarted.
+*
+* @param xTimer The handle of the timer being queried.
+*
+* @return If the timer is an auto-reload timer then pdTRUE is returned, otherwise
+* pdFALSE is returned.
+*/
+UBaseType_t uxTimerGetReloadMode( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;
+
+/**
+ * TickType_t xTimerGetPeriod( TimerHandle_t xTimer );
+ *
+ * Returns the period of a timer.
+ *
+ * @param xTimer The handle of the timer being queried.
+ *
+ * @return The period of the timer in ticks.
+ */
+TickType_t xTimerGetPeriod( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;
+
+/**
+* TickType_t xTimerGetExpiryTime( TimerHandle_t xTimer );
+*
+* Returns the time in ticks at which the timer will expire.  If this is less
+* than the current tick count then the expiry time has overflowed from the
+* current time.
+*
+* @param xTimer The handle of the timer being queried.
+*
+* @return If the timer is running then the time in ticks at which the timer
+* will next expire is returned.  If the timer is not running then the return
+* value is undefined.
+*/
+TickType_t xTimerGetExpiryTime( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;
+
+/*
+ * Functions beyond this part are not part of the public API and are intended
+ * for use by the kernel only.
+ */
+BaseType_t xTimerCreateTimerTask( void ) PRIVILEGED_FUNCTION;
+BaseType_t xTimerGenericCommand( TimerHandle_t xTimer, const BaseType_t xCommandID, const TickType_t xOptionalValue, BaseType_t * const pxHigherPriorityTaskWoken, const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+#if( configUSE_TRACE_FACILITY == 1 )
+	void vTimerSetTimerNumber( TimerHandle_t xTimer, UBaseType_t uxTimerNumber ) PRIVILEGED_FUNCTION;
+	UBaseType_t uxTimerGetTimerNumber( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* TIMERS_H */
+
+
+
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/list.c b/Middlewares/Third_Party/FreeRTOS/Source/list.c
new file mode 100644
index 0000000..7618ee8
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/list.c
@@ -0,0 +1,198 @@
+/*
+ * FreeRTOS Kernel V10.3.1
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#include <stdlib.h>
+#include "FreeRTOS.h"
+#include "list.h"
+
+/*-----------------------------------------------------------
+ * PUBLIC LIST API documented in list.h
+ *----------------------------------------------------------*/
+
+void vListInitialise( List_t * const pxList )
+{
+	/* The list structure contains a list item which is used to mark the
+	end of the list.  To initialise the list the list end is inserted
+	as the only list entry. */
+	pxList->pxIndex = ( ListItem_t * ) &( pxList->xListEnd );			/*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM.  This is checked and valid. */
+
+	/* The list end value is the highest possible value in the list to
+	ensure it remains at the end of the list. */
+	pxList->xListEnd.xItemValue = portMAX_DELAY;
+
+	/* The list end next and previous pointers point to itself so we know
+	when the list is empty. */
+	pxList->xListEnd.pxNext = ( ListItem_t * ) &( pxList->xListEnd );	/*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM.  This is checked and valid. */
+	pxList->xListEnd.pxPrevious = ( ListItem_t * ) &( pxList->xListEnd );/*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM.  This is checked and valid. */
+
+	pxList->uxNumberOfItems = ( UBaseType_t ) 0U;
+
+	/* Write known values into the list if
+	configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
+	listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList );
+	listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList );
+}
+/*-----------------------------------------------------------*/
+
+void vListInitialiseItem( ListItem_t * const pxItem )
+{
+	/* Make sure the list item is not recorded as being on a list. */
+	pxItem->pxContainer = NULL;
+
+	/* Write known values into the list item if
+	configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
+	listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem );
+	listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem );
+}
+/*-----------------------------------------------------------*/
+
+void vListInsertEnd( List_t * const pxList, ListItem_t * const pxNewListItem )
+{
+ListItem_t * const pxIndex = pxList->pxIndex;
+
+	/* Only effective when configASSERT() is also defined, these tests may catch
+	the list data structures being overwritten in memory.  They will not catch
+	data errors caused by incorrect configuration or use of FreeRTOS. */
+	listTEST_LIST_INTEGRITY( pxList );
+	listTEST_LIST_ITEM_INTEGRITY( pxNewListItem );
+
+	/* Insert a new list item into pxList, but rather than sort the list,
+	makes the new list item the last item to be removed by a call to
+	listGET_OWNER_OF_NEXT_ENTRY(). */
+	pxNewListItem->pxNext = pxIndex;
+	pxNewListItem->pxPrevious = pxIndex->pxPrevious;
+
+	/* Only used during decision coverage testing. */
+	mtCOVERAGE_TEST_DELAY();
+
+	pxIndex->pxPrevious->pxNext = pxNewListItem;
+	pxIndex->pxPrevious = pxNewListItem;
+
+	/* Remember which list the item is in. */
+	pxNewListItem->pxContainer = pxList;
+
+	( pxList->uxNumberOfItems )++;
+}
+/*-----------------------------------------------------------*/
+
+void vListInsert( List_t * const pxList, ListItem_t * const pxNewListItem )
+{
+ListItem_t *pxIterator;
+const TickType_t xValueOfInsertion = pxNewListItem->xItemValue;
+
+	/* Only effective when configASSERT() is also defined, these tests may catch
+	the list data structures being overwritten in memory.  They will not catch
+	data errors caused by incorrect configuration or use of FreeRTOS. */
+	listTEST_LIST_INTEGRITY( pxList );
+	listTEST_LIST_ITEM_INTEGRITY( pxNewListItem );
+
+	/* Insert the new list item into the list, sorted in xItemValue order.
+
+	If the list already contains a list item with the same item value then the
+	new list item should be placed after it.  This ensures that TCBs which are
+	stored in ready lists (all of which have the same xItemValue value) get a
+	share of the CPU.  However, if the xItemValue is the same as the back marker
+	the iteration loop below will not end.  Therefore the value is checked
+	first, and the algorithm slightly modified if necessary. */
+	if( xValueOfInsertion == portMAX_DELAY )
+	{
+		pxIterator = pxList->xListEnd.pxPrevious;
+	}
+	else
+	{
+		/* *** NOTE ***********************************************************
+		If you find your application is crashing here then likely causes are
+		listed below.  In addition see https://www.freertos.org/FAQHelp.html for
+		more tips, and ensure configASSERT() is defined!
+		https://www.freertos.org/a00110.html#configASSERT
+
+			1) Stack overflow -
+			   see https://www.freertos.org/Stacks-and-stack-overflow-checking.html
+			2) Incorrect interrupt priority assignment, especially on Cortex-M
+			   parts where numerically high priority values denote low actual
+			   interrupt priorities, which can seem counter intuitive.  See
+			   https://www.freertos.org/RTOS-Cortex-M3-M4.html and the definition
+			   of configMAX_SYSCALL_INTERRUPT_PRIORITY on
+			   https://www.freertos.org/a00110.html
+			3) Calling an API function from within a critical section or when
+			   the scheduler is suspended, or calling an API function that does
+			   not end in "FromISR" from an interrupt.
+			4) Using a queue or semaphore before it has been initialised or
+			   before the scheduler has been started (are interrupts firing
+			   before vTaskStartScheduler() has been called?).
+		**********************************************************************/
+
+		for( pxIterator = ( ListItem_t * ) &( pxList->xListEnd ); pxIterator->pxNext->xItemValue <= xValueOfInsertion; pxIterator = pxIterator->pxNext ) /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM.  This is checked and valid. *//*lint !e440 The iterator moves to a different value, not xValueOfInsertion. */
+		{
+			/* There is nothing to do here, just iterating to the wanted
+			insertion position. */
+		}
+	}
+
+	pxNewListItem->pxNext = pxIterator->pxNext;
+	pxNewListItem->pxNext->pxPrevious = pxNewListItem;
+	pxNewListItem->pxPrevious = pxIterator;
+	pxIterator->pxNext = pxNewListItem;
+
+	/* Remember which list the item is in.  This allows fast removal of the
+	item later. */
+	pxNewListItem->pxContainer = pxList;
+
+	( pxList->uxNumberOfItems )++;
+}
+/*-----------------------------------------------------------*/
+
+UBaseType_t uxListRemove( ListItem_t * const pxItemToRemove )
+{
+/* The list item knows which list it is in.  Obtain the list from the list
+item. */
+List_t * const pxList = pxItemToRemove->pxContainer;
+
+	pxItemToRemove->pxNext->pxPrevious = pxItemToRemove->pxPrevious;
+	pxItemToRemove->pxPrevious->pxNext = pxItemToRemove->pxNext;
+
+	/* Only used during decision coverage testing. */
+	mtCOVERAGE_TEST_DELAY();
+
+	/* Make sure the index is left pointing to a valid item. */
+	if( pxList->pxIndex == pxItemToRemove )
+	{
+		pxList->pxIndex = pxItemToRemove->pxPrevious;
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	pxItemToRemove->pxContainer = NULL;
+	( pxList->uxNumberOfItems )--;
+
+	return pxList->uxNumberOfItems;
+}
+/*-----------------------------------------------------------*/
+
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c b/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c
new file mode 100644
index 0000000..89a912c
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c
@@ -0,0 +1,775 @@
+/*
+ * FreeRTOS Kernel V10.3.1
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the ARM CM4F port.
+ *----------------------------------------------------------*/
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+#ifndef __VFP_FP__
+	#error This port can only be used when the project options are configured to enable hardware floating point support.
+#endif
+
+#ifndef configSYSTICK_CLOCK_HZ
+	#define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ
+	/* Ensure the SysTick is clocked at the same frequency as the core. */
+	#define portNVIC_SYSTICK_CLK_BIT	( 1UL << 2UL )
+#else
+	/* The way the SysTick is clocked is not modified in case it is not the same
+	as the core. */
+	#define portNVIC_SYSTICK_CLK_BIT	( 0 )
+#endif
+
+/* Constants required to manipulate the core.  Registers first... */
+#define portNVIC_SYSTICK_CTRL_REG			( * ( ( volatile uint32_t * ) 0xe000e010 ) )
+#define portNVIC_SYSTICK_LOAD_REG			( * ( ( volatile uint32_t * ) 0xe000e014 ) )
+#define portNVIC_SYSTICK_CURRENT_VALUE_REG	( * ( ( volatile uint32_t * ) 0xe000e018 ) )
+#define portNVIC_SYSPRI2_REG				( * ( ( volatile uint32_t * ) 0xe000ed20 ) )
+/* ...then bits in the registers. */
+#define portNVIC_SYSTICK_INT_BIT			( 1UL << 1UL )
+#define portNVIC_SYSTICK_ENABLE_BIT			( 1UL << 0UL )
+#define portNVIC_SYSTICK_COUNT_FLAG_BIT		( 1UL << 16UL )
+#define portNVIC_PENDSVCLEAR_BIT 			( 1UL << 27UL )
+#define portNVIC_PEND_SYSTICK_CLEAR_BIT		( 1UL << 25UL )
+
+/* Constants used to detect a Cortex-M7 r0p1 core, which should use the ARM_CM7
+r0p1 port. */
+#define portCPUID							( * ( ( volatile uint32_t * ) 0xE000ed00 ) )
+#define portCORTEX_M7_r0p1_ID				( 0x410FC271UL )
+#define portCORTEX_M7_r0p0_ID				( 0x410FC270UL )
+
+#define portNVIC_PENDSV_PRI					( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
+#define portNVIC_SYSTICK_PRI				( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
+
+/* Constants required to check the validity of an interrupt priority. */
+#define portFIRST_USER_INTERRUPT_NUMBER		( 16 )
+#define portNVIC_IP_REGISTERS_OFFSET_16 	( 0xE000E3F0 )
+#define portAIRCR_REG						( * ( ( volatile uint32_t * ) 0xE000ED0C ) )
+#define portMAX_8_BIT_VALUE					( ( uint8_t ) 0xff )
+#define portTOP_BIT_OF_BYTE					( ( uint8_t ) 0x80 )
+#define portMAX_PRIGROUP_BITS				( ( uint8_t ) 7 )
+#define portPRIORITY_GROUP_MASK				( 0x07UL << 8UL )
+#define portPRIGROUP_SHIFT					( 8UL )
+
+/* Masks off all bits but the VECTACTIVE bits in the ICSR register. */
+#define portVECTACTIVE_MASK					( 0xFFUL )
+
+/* Constants required to manipulate the VFP. */
+#define portFPCCR							( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating point context control register. */
+#define portASPEN_AND_LSPEN_BITS			( 0x3UL << 30UL )
+
+/* Constants required to set up the initial stack. */
+#define portINITIAL_XPSR					( 0x01000000 )
+#define portINITIAL_EXC_RETURN				( 0xfffffffd )
+
+/* The systick is a 24-bit counter. */
+#define portMAX_24_BIT_NUMBER				( 0xffffffUL )
+
+/* For strict compliance with the Cortex-M spec the task start address should
+have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
+#define portSTART_ADDRESS_MASK		( ( StackType_t ) 0xfffffffeUL )
+
+/* A fiddle factor to estimate the number of SysTick counts that would have
+occurred while the SysTick counter is stopped during tickless idle
+calculations. */
+#define portMISSED_COUNTS_FACTOR			( 45UL )
+
+/* Let the user override the pre-loading of the initial LR with the address of
+prvTaskExitError() in case it messes up unwinding of the stack in the
+debugger. */
+#ifdef configTASK_RETURN_ADDRESS
+	#define portTASK_RETURN_ADDRESS	configTASK_RETURN_ADDRESS
+#else
+	#define portTASK_RETURN_ADDRESS	prvTaskExitError
+#endif
+
+/*
+ * Setup the timer to generate the tick interrupts.  The implementation in this
+ * file is weak to allow application writers to change the timer used to
+ * generate the tick interrupt.
+ */
+void vPortSetupTimerInterrupt( void );
+
+/*
+ * Exception handlers.
+ */
+void xPortPendSVHandler( void ) __attribute__ (( naked ));
+void xPortSysTickHandler( void );
+void vPortSVCHandler( void ) __attribute__ (( naked ));
+
+/*
+ * Start first task is a separate function so it can be tested in isolation.
+ */
+static void prvPortStartFirstTask( void ) __attribute__ (( naked ));
+
+/*
+ * Function to enable the VFP.
+ */
+static void vPortEnableVFP( void ) __attribute__ (( naked ));
+
+/*
+ * Used to catch tasks that attempt to return from their implementing function.
+ */
+static void prvTaskExitError( void );
+
+/*-----------------------------------------------------------*/
+
+/* Each task maintains its own interrupt status in the critical nesting
+variable. */
+static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
+
+/*
+ * The number of SysTick increments that make up one tick period.
+ */
+#if( configUSE_TICKLESS_IDLE == 1 )
+	static uint32_t ulTimerCountsForOneTick = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*
+ * The maximum number of tick periods that can be suppressed is limited by the
+ * 24 bit resolution of the SysTick timer.
+ */
+#if( configUSE_TICKLESS_IDLE == 1 )
+	static uint32_t xMaximumPossibleSuppressedTicks = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*
+ * Compensate for the CPU cycles that pass while the SysTick is stopped (low
+ * power functionality only.
+ */
+#if( configUSE_TICKLESS_IDLE == 1 )
+	static uint32_t ulStoppedTimerCompensation = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*
+ * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
+ * FreeRTOS API functions are not called from interrupts that have been assigned
+ * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ */
+#if( configASSERT_DEFINED == 1 )
+	 static uint8_t ucMaxSysCallPriority = 0;
+	 static uint32_t ulMaxPRIGROUPValue = 0;
+	 static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16;
+#endif /* configASSERT_DEFINED */
+
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+	/* Simulate the stack frame as it would be created by a context switch
+	interrupt. */
+
+	/* Offset added to account for the way the MCU uses the stack on entry/exit
+	of interrupts, and to ensure alignment. */
+	pxTopOfStack--;
+
+	*pxTopOfStack = portINITIAL_XPSR;	/* xPSR */
+	pxTopOfStack--;
+	*pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK;	/* PC */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;	/* LR */
+
+	/* Save code space by skipping register initialisation. */
+	pxTopOfStack -= 5;	/* R12, R3, R2 and R1. */
+	*pxTopOfStack = ( StackType_t ) pvParameters;	/* R0 */
+
+	/* A save method is being used that requires each task to maintain its
+	own exec return value. */
+	pxTopOfStack--;
+	*pxTopOfStack = portINITIAL_EXC_RETURN;
+
+	pxTopOfStack -= 8;	/* R11, R10, R9, R8, R7, R6, R5 and R4. */
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+static void prvTaskExitError( void )
+{
+volatile uint32_t ulDummy = 0;
+
+	/* A function that implements a task must not exit or attempt to return to
+	its caller as there is nothing to return to.  If a task wants to exit it
+	should instead call vTaskDelete( NULL ).
+
+	Artificially force an assert() to be triggered if configASSERT() is
+	defined, then stop here so application writers can catch the error. */
+	configASSERT( uxCriticalNesting == ~0UL );
+	portDISABLE_INTERRUPTS();
+	while( ulDummy == 0 )
+	{
+		/* This file calls prvTaskExitError() after the scheduler has been
+		started to remove a compiler warning about the function being defined
+		but never called.  ulDummy is used purely to quieten other warnings
+		about code appearing after this function is called - making ulDummy
+		volatile makes the compiler think the function could return and
+		therefore not output an 'unreachable code' warning for code that appears
+		after it. */
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vPortSVCHandler( void )
+{
+	__asm volatile (
+					"	ldr	r3, pxCurrentTCBConst2		\n" /* Restore the context. */
+					"	ldr r1, [r3]					\n" /* Use pxCurrentTCBConst to get the pxCurrentTCB address. */
+					"	ldr r0, [r1]					\n" /* The first item in pxCurrentTCB is the task top of stack. */
+					"	ldmia r0!, {r4-r11, r14}		\n" /* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */
+					"	msr psp, r0						\n" /* Restore the task stack pointer. */
+					"	isb								\n"
+					"	mov r0, #0 						\n"
+					"	msr	basepri, r0					\n"
+					"	bx r14							\n"
+					"									\n"
+					"	.align 4						\n"
+					"pxCurrentTCBConst2: .word pxCurrentTCB				\n"
+				);
+}
+/*-----------------------------------------------------------*/
+
+static void prvPortStartFirstTask( void )
+{
+	/* Start the first task.  This also clears the bit that indicates the FPU is
+	in use in case the FPU was used before the scheduler was started - which
+	would otherwise result in the unnecessary leaving of space in the SVC stack
+	for lazy saving of FPU registers. */
+	__asm volatile(
+					" ldr r0, =0xE000ED08 	\n" /* Use the NVIC offset register to locate the stack. */
+					" ldr r0, [r0] 			\n"
+					" ldr r0, [r0] 			\n"
+					" msr msp, r0			\n" /* Set the msp back to the start of the stack. */
+					" mov r0, #0			\n" /* Clear the bit that indicates the FPU is in use, see comment above. */
+					" msr control, r0		\n"
+					" cpsie i				\n" /* Globally enable interrupts. */
+					" cpsie f				\n"
+					" dsb					\n"
+					" isb					\n"
+					" svc 0					\n" /* System call to start first task. */
+					" nop					\n"
+				);
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+BaseType_t xPortStartScheduler( void )
+{
+	/* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.
+	See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
+	configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );
+
+	/* This port can be used on all revisions of the Cortex-M7 core other than
+	the r0p1 parts.  r0p1 parts should use the port from the
+	/source/portable/GCC/ARM_CM7/r0p1 directory. */
+	configASSERT( portCPUID != portCORTEX_M7_r0p1_ID );
+	configASSERT( portCPUID != portCORTEX_M7_r0p0_ID );
+
+	#if( configASSERT_DEFINED == 1 )
+	{
+		volatile uint32_t ulOriginalPriority;
+		volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
+		volatile uint8_t ucMaxPriorityValue;
+
+		/* Determine the maximum priority from which ISR safe FreeRTOS API
+		functions can be called.  ISR safe functions are those that end in
+		"FromISR".  FreeRTOS maintains separate thread and ISR API functions to
+		ensure interrupt entry is as fast and simple as possible.
+
+		Save the interrupt priority value that is about to be clobbered. */
+		ulOriginalPriority = *pucFirstUserPriorityRegister;
+
+		/* Determine the number of priority bits available.  First write to all
+		possible bits. */
+		*pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
+
+		/* Read the value back to see how many bits stuck. */
+		ucMaxPriorityValue = *pucFirstUserPriorityRegister;
+
+		/* Use the same mask on the maximum system call priority. */
+		ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
+
+		/* Calculate the maximum acceptable priority group value for the number
+		of bits read back. */
+		ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
+		while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
+		{
+			ulMaxPRIGROUPValue--;
+			ucMaxPriorityValue <<= ( uint8_t ) 0x01;
+		}
+
+		#ifdef __NVIC_PRIO_BITS
+		{
+			/* Check the CMSIS configuration that defines the number of
+			priority bits matches the number of priority bits actually queried
+			from the hardware. */
+			configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );
+		}
+		#endif
+
+		#ifdef configPRIO_BITS
+		{
+			/* Check the FreeRTOS configuration that defines the number of
+			priority bits matches the number of priority bits actually queried
+			from the hardware. */
+			configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
+		}
+		#endif
+
+		/* Shift the priority group value back to its position within the AIRCR
+		register. */
+		ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
+		ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
+
+		/* Restore the clobbered interrupt priority register to its original
+		value. */
+		*pucFirstUserPriorityRegister = ulOriginalPriority;
+	}
+	#endif /* conifgASSERT_DEFINED */
+
+	/* Make PendSV and SysTick the lowest priority interrupts. */
+	portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;
+	portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;
+
+	/* Start the timer that generates the tick ISR.  Interrupts are disabled
+	here already. */
+	vPortSetupTimerInterrupt();
+
+	/* Initialise the critical nesting count ready for the first task. */
+	uxCriticalNesting = 0;
+
+	/* Ensure the VFP is enabled - it should be anyway. */
+	vPortEnableVFP();
+
+	/* Lazy save always. */
+	*( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;
+
+	/* Start the first task. */
+	prvPortStartFirstTask();
+
+	/* Should never get here as the tasks will now be executing!  Call the task
+	exit error function to prevent compiler warnings about a static function
+	not being called in the case that the application writer overrides this
+	functionality by defining configTASK_RETURN_ADDRESS.  Call
+	vTaskSwitchContext() so link time optimisation does not remove the
+	symbol. */
+	vTaskSwitchContext();
+	prvTaskExitError();
+
+	/* Should not get here! */
+	return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* Not implemented in ports where there is nothing to return to.
+	Artificially force an assert. */
+	configASSERT( uxCriticalNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void )
+{
+	portDISABLE_INTERRUPTS();
+	uxCriticalNesting++;
+
+	/* This is not the interrupt safe version of the enter critical function so
+	assert() if it is being called from an interrupt context.  Only API
+	functions that end in "FromISR" can be used in an interrupt.  Only assert if
+	the critical nesting count is 1 to protect against recursive calls if the
+	assert function also uses a critical section. */
+	if( uxCriticalNesting == 1 )
+	{
+		configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void )
+{
+	configASSERT( uxCriticalNesting );
+	uxCriticalNesting--;
+	if( uxCriticalNesting == 0 )
+	{
+		portENABLE_INTERRUPTS();
+	}
+}
+/*-----------------------------------------------------------*/
+
+void xPortPendSVHandler( void )
+{
+	/* This is a naked function. */
+
+	__asm volatile
+	(
+	"	mrs r0, psp							\n"
+	"	isb									\n"
+	"										\n"
+	"	ldr	r3, pxCurrentTCBConst			\n" /* Get the location of the current TCB. */
+	"	ldr	r2, [r3]						\n"
+	"										\n"
+	"	tst r14, #0x10						\n" /* Is the task using the FPU context?  If so, push high vfp registers. */
+	"	it eq								\n"
+	"	vstmdbeq r0!, {s16-s31}				\n"
+	"										\n"
+	"	stmdb r0!, {r4-r11, r14}			\n" /* Save the core registers. */
+	"	str r0, [r2]						\n" /* Save the new top of stack into the first member of the TCB. */
+	"										\n"
+	"	stmdb sp!, {r0, r3}					\n"
+	"	mov r0, %0 							\n"
+	"	msr basepri, r0						\n"
+	"	dsb									\n"
+	"	isb									\n"
+	"	bl vTaskSwitchContext				\n"
+	"	mov r0, #0							\n"
+	"	msr basepri, r0						\n"
+	"	ldmia sp!, {r0, r3}					\n"
+	"										\n"
+	"	ldr r1, [r3]						\n" /* The first item in pxCurrentTCB is the task top of stack. */
+	"	ldr r0, [r1]						\n"
+	"										\n"
+	"	ldmia r0!, {r4-r11, r14}			\n" /* Pop the core registers. */
+	"										\n"
+	"	tst r14, #0x10						\n" /* Is the task using the FPU context?  If so, pop the high vfp registers too. */
+	"	it eq								\n"
+	"	vldmiaeq r0!, {s16-s31}				\n"
+	"										\n"
+	"	msr psp, r0							\n"
+	"	isb									\n"
+	"										\n"
+	#ifdef WORKAROUND_PMU_CM001 /* XMC4000 specific errata workaround. */
+		#if WORKAROUND_PMU_CM001 == 1
+	"			push { r14 }				\n"
+	"			pop { pc }					\n"
+		#endif
+	#endif
+	"										\n"
+	"	bx r14								\n"
+	"										\n"
+	"	.align 4							\n"
+	"pxCurrentTCBConst: .word pxCurrentTCB	\n"
+	::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY)
+	);
+}
+/*-----------------------------------------------------------*/
+
+void xPortSysTickHandler( void )
+{
+	/* The SysTick runs at the lowest interrupt priority, so when this interrupt
+	executes all interrupts must be unmasked.  There is therefore no need to
+	save and then restore the interrupt mask value as its value is already
+	known. */
+	portDISABLE_INTERRUPTS();
+	{
+		/* Increment the RTOS tick. */
+		if( xTaskIncrementTick() != pdFALSE )
+		{
+			/* A context switch is required.  Context switching is performed in
+			the PendSV interrupt.  Pend the PendSV interrupt. */
+			portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
+		}
+	}
+	portENABLE_INTERRUPTS();
+}
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TICKLESS_IDLE == 1 )
+
+	__attribute__((weak)) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
+	{
+	uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;
+	TickType_t xModifiableIdleTime;
+
+		/* Make sure the SysTick reload value does not overflow the counter. */
+		if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
+		{
+			xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
+		}
+
+		/* Stop the SysTick momentarily.  The time the SysTick is stopped for
+		is accounted for as best it can be, but using the tickless mode will
+		inevitably result in some tiny drift of the time maintained by the
+		kernel with respect to calendar time. */
+		portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT;
+
+		/* Calculate the reload value required to wait xExpectedIdleTime
+		tick periods.  -1 is used because this code will execute part way
+		through one of the tick periods. */
+		ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
+		if( ulReloadValue > ulStoppedTimerCompensation )
+		{
+			ulReloadValue -= ulStoppedTimerCompensation;
+		}
+
+		/* Enter a critical section but don't use the taskENTER_CRITICAL()
+		method as that will mask interrupts that should exit sleep mode. */
+		__asm volatile( "cpsid i" ::: "memory" );
+		__asm volatile( "dsb" );
+		__asm volatile( "isb" );
+
+		/* If a context switch is pending or a task is waiting for the scheduler
+		to be unsuspended then abandon the low power entry. */
+		if( eTaskConfirmSleepModeStatus() == eAbortSleep )
+		{
+			/* Restart from whatever is left in the count register to complete
+			this tick period. */
+			portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;
+
+			/* Restart SysTick. */
+			portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+
+			/* Reset the reload register to the value required for normal tick
+			periods. */
+			portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+
+			/* Re-enable interrupts - see comments above the cpsid instruction()
+			above. */
+			__asm volatile( "cpsie i" ::: "memory" );
+		}
+		else
+		{
+			/* Set the new reload value. */
+			portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
+
+			/* Clear the SysTick count flag and set the count value back to
+			zero. */
+			portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+
+			/* Restart SysTick. */
+			portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+
+			/* Sleep until something happens.  configPRE_SLEEP_PROCESSING() can
+			set its parameter to 0 to indicate that its implementation contains
+			its own wait for interrupt or wait for event instruction, and so wfi
+			should not be executed again.  However, the original expected idle
+			time variable must remain unmodified, so a copy is taken. */
+			xModifiableIdleTime = xExpectedIdleTime;
+			configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
+			if( xModifiableIdleTime > 0 )
+			{
+				__asm volatile( "dsb" ::: "memory" );
+				__asm volatile( "wfi" );
+				__asm volatile( "isb" );
+			}
+			configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
+
+			/* Re-enable interrupts to allow the interrupt that brought the MCU
+			out of sleep mode to execute immediately.  see comments above
+			__disable_interrupt() call above. */
+			__asm volatile( "cpsie i" ::: "memory" );
+			__asm volatile( "dsb" );
+			__asm volatile( "isb" );
+
+			/* Disable interrupts again because the clock is about to be stopped
+			and interrupts that execute while the clock is stopped will increase
+			any slippage between the time maintained by the RTOS and calendar
+			time. */
+			__asm volatile( "cpsid i" ::: "memory" );
+			__asm volatile( "dsb" );
+			__asm volatile( "isb" );
+
+			/* Disable the SysTick clock without reading the
+			portNVIC_SYSTICK_CTRL_REG register to ensure the
+			portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set.  Again,
+			the time the SysTick is stopped for is accounted for as best it can
+			be, but using the tickless mode will inevitably result in some tiny
+			drift of the time maintained by the kernel with respect to calendar
+			time*/
+			portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT );
+
+			/* Determine if the SysTick clock has already counted to zero and
+			been set back to the current reload value (the reload back being
+			correct for the entire expected idle time) or if the SysTick is yet
+			to count to zero (in which case an interrupt other than the SysTick
+			must have brought the system out of sleep mode). */
+			if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
+			{
+				uint32_t ulCalculatedLoadValue;
+
+				/* The tick interrupt is already pending, and the SysTick count
+				reloaded with ulReloadValue.  Reset the
+				portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick
+				period. */
+				ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
+
+				/* Don't allow a tiny value, or values that have somehow
+				underflowed because the post sleep hook did something
+				that took too long. */
+				if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
+				{
+					ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
+				}
+
+				portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;
+
+				/* As the pending tick will be processed as soon as this
+				function exits, the tick value maintained by the tick is stepped
+				forward by one less than the time spent waiting. */
+				ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
+			}
+			else
+			{
+				/* Something other than the tick interrupt ended the sleep.
+				Work out how long the sleep lasted rounded to complete tick
+				periods (not the ulReload value which accounted for part
+				ticks). */
+				ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;
+
+				/* How many complete tick periods passed while the processor
+				was waiting? */
+				ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
+
+				/* The reload value is set to whatever fraction of a single tick
+				period remains. */
+				portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
+			}
+
+			/* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG
+			again, then set portNVIC_SYSTICK_LOAD_REG back to its standard
+			value. */
+			portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+			portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+			vTaskStepTick( ulCompleteTickPeriods );
+			portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+
+			/* Exit with interrupts enabled. */
+			__asm volatile( "cpsie i" ::: "memory" );
+		}
+	}
+
+#endif /* #if configUSE_TICKLESS_IDLE */
+/*-----------------------------------------------------------*/
+
+/*
+ * Setup the systick timer to generate the tick interrupts at the required
+ * frequency.
+ */
+__attribute__(( weak )) void vPortSetupTimerInterrupt( void )
+{
+	/* Calculate the constants required to configure the tick interrupt. */
+	#if( configUSE_TICKLESS_IDLE == 1 )
+	{
+		ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
+		xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
+		ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
+	}
+	#endif /* configUSE_TICKLESS_IDLE */
+
+	/* Stop and clear the SysTick. */
+	portNVIC_SYSTICK_CTRL_REG = 0UL;
+	portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+
+	/* Configure SysTick to interrupt at the requested rate. */
+	portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
+	portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
+}
+/*-----------------------------------------------------------*/
+
+/* This is a naked function. */
+static void vPortEnableVFP( void )
+{
+	__asm volatile
+	(
+		"	ldr.w r0, =0xE000ED88		\n" /* The FPU enable bits are in the CPACR. */
+		"	ldr r1, [r0]				\n"
+		"								\n"
+		"	orr r1, r1, #( 0xf << 20 )	\n" /* Enable CP10 and CP11 coprocessors, then save back. */
+		"	str r1, [r0]				\n"
+		"	bx r14						"
+	);
+}
+/*-----------------------------------------------------------*/
+
+#if( configASSERT_DEFINED == 1 )
+
+	void vPortValidateInterruptPriority( void )
+	{
+	uint32_t ulCurrentInterrupt;
+	uint8_t ucCurrentPriority;
+
+		/* Obtain the number of the currently executing interrupt. */
+		__asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" );
+
+		/* Is the interrupt number a user defined interrupt? */
+		if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
+		{
+			/* Look up the interrupt's priority. */
+			ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
+
+			/* The following assertion will fail if a service routine (ISR) for
+			an interrupt that has been assigned a priority above
+			configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
+			function.  ISR safe FreeRTOS API functions must *only* be called
+			from interrupts that have been assigned a priority at or below
+			configMAX_SYSCALL_INTERRUPT_PRIORITY.
+
+			Numerically low interrupt priority numbers represent logically high
+			interrupt priorities, therefore the priority of the interrupt must
+			be set to a value equal to or numerically *higher* than
+			configMAX_SYSCALL_INTERRUPT_PRIORITY.
+
+			Interrupts that	use the FreeRTOS API must not be left at their
+			default priority of	zero as that is the highest possible priority,
+			which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
+			and	therefore also guaranteed to be invalid.
+
+			FreeRTOS maintains separate thread and ISR API functions to ensure
+			interrupt entry is as fast and simple as possible.
+
+			The following links provide detailed information:
+			http://www.freertos.org/RTOS-Cortex-M3-M4.html
+			http://www.freertos.org/FAQHelp.html */
+			configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
+		}
+
+		/* Priority grouping:  The interrupt controller (NVIC) allows the bits
+		that define each interrupt's priority to be split between bits that
+		define the interrupt's pre-emption priority bits and bits that define
+		the interrupt's sub-priority.  For simplicity all bits must be defined
+		to be pre-emption priority bits.  The following assertion will fail if
+		this is not the case (if some bits represent a sub-priority).
+
+		If the application only uses CMSIS libraries for interrupt
+		configuration then the correct setting can be achieved on all Cortex-M
+		devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
+		scheduler.  Note however that some vendor specific peripheral libraries
+		assume a non-zero priority group setting, in which cases using a value
+		of zero will result in unpredictable behaviour. */
+		configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
+	}
+
+#endif /* configASSERT_DEFINED */
+
+
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h b/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h
new file mode 100644
index 0000000..d0a566a
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h
@@ -0,0 +1,243 @@
+/*
+ * FreeRTOS Kernel V10.3.1
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	uint32_t
+#define portBASE_TYPE	long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+
+	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+	not need to be guarded with a critical section. */
+	#define portTICK_TYPE_IS_ATOMIC 1
+#endif
+/*-----------------------------------------------------------*/
+
+/* Architecture specifics. */
+#define portSTACK_GROWTH			( -1 )
+#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT			8
+/*-----------------------------------------------------------*/
+
+/* Scheduler utilities. */
+#define portYIELD() 															\
+{																				\
+	/* Set a PendSV to request a context switch. */								\
+	portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;								\
+																				\
+	/* Barriers are normally not required but do ensure the code is completely	\
+	within the specified behaviour for the architecture. */						\
+	__asm volatile( "dsb" ::: "memory" );										\
+	__asm volatile( "isb" );													\
+}
+
+#define portNVIC_INT_CTRL_REG		( * ( ( volatile uint32_t * ) 0xe000ed04 ) )
+#define portNVIC_PENDSVSET_BIT		( 1UL << 28UL )
+#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired != pdFALSE ) portYIELD()
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+/*-----------------------------------------------------------*/
+
+/* Critical section management. */
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
+#define portSET_INTERRUPT_MASK_FROM_ISR()		ulPortRaiseBASEPRI()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)	vPortSetBASEPRI(x)
+#define portDISABLE_INTERRUPTS()				vPortRaiseBASEPRI()
+#define portENABLE_INTERRUPTS()					vPortSetBASEPRI(0)
+#define portENTER_CRITICAL()					vPortEnterCritical()
+#define portEXIT_CRITICAL()						vPortExitCritical()
+
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site.  These are
+not necessary for to use this port.  They are defined so the common demo files
+(which build with all the ports) will build. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+/*-----------------------------------------------------------*/
+
+/* Tickless idle/low power functionality. */
+#ifndef portSUPPRESS_TICKS_AND_SLEEP
+	extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
+	#define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
+#endif
+/*-----------------------------------------------------------*/
+
+/* Architecture specific optimisations. */
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+	#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+#endif
+
+#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+
+	/* Generic helper function. */
+	__attribute__( ( always_inline ) ) static inline uint8_t ucPortCountLeadingZeros( uint32_t ulBitmap )
+	{
+	uint8_t ucReturn;
+
+		__asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) : "memory" );
+		return ucReturn;
+	}
+
+	/* Check the configuration. */
+	#if( configMAX_PRIORITIES > 32 )
+		#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+	#endif
+
+	/* Store/clear the ready priorities in a bit map. */
+	#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+	#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+	/*-----------------------------------------------------------*/
+
+	#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) )
+
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+/*-----------------------------------------------------------*/
+
+#ifdef configASSERT
+	void vPortValidateInterruptPriority( void );
+	#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() 	vPortValidateInterruptPriority()
+#endif
+
+/* portNOP() is not required by this port. */
+#define portNOP()
+
+#define portINLINE	__inline
+
+#ifndef portFORCE_INLINE
+	#define portFORCE_INLINE inline __attribute__(( always_inline))
+#endif
+
+portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void )
+{
+uint32_t ulCurrentInterrupt;
+BaseType_t xReturn;
+
+	/* Obtain the number of the currently executing interrupt. */
+	__asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" );
+
+	if( ulCurrentInterrupt == 0 )
+	{
+		xReturn = pdFALSE;
+	}
+	else
+	{
+		xReturn = pdTRUE;
+	}
+
+	return xReturn;
+}
+
+/*-----------------------------------------------------------*/
+
+portFORCE_INLINE static void vPortRaiseBASEPRI( void )
+{
+uint32_t ulNewBASEPRI;
+
+	__asm volatile
+	(
+		"	mov %0, %1												\n"	\
+		"	msr basepri, %0											\n" \
+		"	isb														\n" \
+		"	dsb														\n" \
+		:"=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
+	);
+}
+
+/*-----------------------------------------------------------*/
+
+portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void )
+{
+uint32_t ulOriginalBASEPRI, ulNewBASEPRI;
+
+	__asm volatile
+	(
+		"	mrs %0, basepri											\n" \
+		"	mov %1, %2												\n"	\
+		"	msr basepri, %1											\n" \
+		"	isb														\n" \
+		"	dsb														\n" \
+		:"=r" (ulOriginalBASEPRI), "=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
+	);
+
+	/* This return will not be reached but is necessary to prevent compiler
+	warnings. */
+	return ulOriginalBASEPRI;
+}
+/*-----------------------------------------------------------*/
+
+portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue )
+{
+	__asm volatile
+	(
+		"	msr basepri, %0	" :: "r" ( ulNewMaskValue ) : "memory"
+	);
+}
+/*-----------------------------------------------------------*/
+
+#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c b/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c
new file mode 100644
index 0000000..eaf443f
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c
@@ -0,0 +1,492 @@
+/*
+ * FreeRTOS Kernel V10.3.1
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*
+ * A sample implementation of pvPortMalloc() and vPortFree() that combines
+ * (coalescences) adjacent memory blocks as they are freed, and in so doing
+ * limits memory fragmentation.
+ *
+ * See heap_1.c, heap_2.c and heap_3.c for alternative implementations, and the
+ * memory management pages of http://www.FreeRTOS.org for more information.
+ */
+#include <stdlib.h>
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+all the API functions to use the MPU wrappers.  That should only be done when
+task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+#include "FreeRTOS.h"
+#include "task.h"
+
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 0 )
+	#error This file must not be used if configSUPPORT_DYNAMIC_ALLOCATION is 0
+#endif
+
+/* Block sizes must not get too small. */
+#define heapMINIMUM_BLOCK_SIZE	( ( size_t ) ( xHeapStructSize << 1 ) )
+
+/* Assumes 8bit bytes! */
+#define heapBITS_PER_BYTE		( ( size_t ) 8 )
+
+/* Allocate the memory for the heap. */
+#if( configAPPLICATION_ALLOCATED_HEAP == 1 )
+	/* The application writer has already defined the array used for the RTOS
+	heap - probably so it can be placed in a special segment or address. */
+	extern uint8_t ucHeap[ configTOTAL_HEAP_SIZE ];
+#else
+	static uint8_t ucHeap[ configTOTAL_HEAP_SIZE ];
+#endif /* configAPPLICATION_ALLOCATED_HEAP */
+
+/* Define the linked list structure.  This is used to link free blocks in order
+of their memory address. */
+typedef struct A_BLOCK_LINK
+{
+	struct A_BLOCK_LINK *pxNextFreeBlock;	/*<< The next free block in the list. */
+	size_t xBlockSize;						/*<< The size of the free block. */
+} BlockLink_t;
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Inserts a block of memory that is being freed into the correct position in
+ * the list of free memory blocks.  The block being freed will be merged with
+ * the block in front it and/or the block behind it if the memory blocks are
+ * adjacent to each other.
+ */
+static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert );
+
+/*
+ * Called automatically to setup the required heap structures the first time
+ * pvPortMalloc() is called.
+ */
+static void prvHeapInit( void );
+
+/*-----------------------------------------------------------*/
+
+/* The size of the structure placed at the beginning of each allocated memory
+block must by correctly byte aligned. */
+static const size_t xHeapStructSize	= ( sizeof( BlockLink_t ) + ( ( size_t ) ( portBYTE_ALIGNMENT - 1 ) ) ) & ~( ( size_t ) portBYTE_ALIGNMENT_MASK );
+
+/* Create a couple of list links to mark the start and end of the list. */
+static BlockLink_t xStart, *pxEnd = NULL;
+
+/* Keeps track of the number of calls to allocate and free memory as well as the
+number of free bytes remaining, but says nothing about fragmentation. */
+static size_t xFreeBytesRemaining = 0U;
+static size_t xMinimumEverFreeBytesRemaining = 0U;
+static size_t xNumberOfSuccessfulAllocations = 0;
+static size_t xNumberOfSuccessfulFrees = 0;
+
+/* Gets set to the top bit of an size_t type.  When this bit in the xBlockSize
+member of an BlockLink_t structure is set then the block belongs to the
+application.  When the bit is free the block is still part of the free heap
+space. */
+static size_t xBlockAllocatedBit = 0;
+
+/*-----------------------------------------------------------*/
+
+void *pvPortMalloc( size_t xWantedSize )
+{
+BlockLink_t *pxBlock, *pxPreviousBlock, *pxNewBlockLink;
+void *pvReturn = NULL;
+
+	vTaskSuspendAll();
+	{
+		/* If this is the first call to malloc then the heap will require
+		initialisation to setup the list of free blocks. */
+		if( pxEnd == NULL )
+		{
+			prvHeapInit();
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		/* Check the requested block size is not so large that the top bit is
+		set.  The top bit of the block size member of the BlockLink_t structure
+		is used to determine who owns the block - the application or the
+		kernel, so it must be free. */
+		if( ( xWantedSize & xBlockAllocatedBit ) == 0 )
+		{
+			/* The wanted size is increased so it can contain a BlockLink_t
+			structure in addition to the requested amount of bytes. */
+			if( xWantedSize > 0 )
+			{
+				xWantedSize += xHeapStructSize;
+
+				/* Ensure that blocks are always aligned to the required number
+				of bytes. */
+				if( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) != 0x00 )
+				{
+					/* Byte alignment required. */
+					xWantedSize += ( portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ) );
+					configASSERT( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) == 0 );
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+
+			if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )
+			{
+				/* Traverse the list from the start	(lowest address) block until
+				one	of adequate size is found. */
+				pxPreviousBlock = &xStart;
+				pxBlock = xStart.pxNextFreeBlock;
+				while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )
+				{
+					pxPreviousBlock = pxBlock;
+					pxBlock = pxBlock->pxNextFreeBlock;
+				}
+
+				/* If the end marker was reached then a block of adequate size
+				was	not found. */
+				if( pxBlock != pxEnd )
+				{
+					/* Return the memory space pointed to - jumping over the
+					BlockLink_t structure at its start. */
+					pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize );
+
+					/* This block is being returned for use so must be taken out
+					of the list of free blocks. */
+					pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock;
+
+					/* If the block is larger than required it can be split into
+					two. */
+					if( ( pxBlock->xBlockSize - xWantedSize ) > heapMINIMUM_BLOCK_SIZE )
+					{
+						/* This block is to be split into two.  Create a new
+						block following the number of bytes requested. The void
+						cast is used to prevent byte alignment warnings from the
+						compiler. */
+						pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize );
+						configASSERT( ( ( ( size_t ) pxNewBlockLink ) & portBYTE_ALIGNMENT_MASK ) == 0 );
+
+						/* Calculate the sizes of two blocks split from the
+						single block. */
+						pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;
+						pxBlock->xBlockSize = xWantedSize;
+
+						/* Insert the new block into the list of free blocks. */
+						prvInsertBlockIntoFreeList( pxNewBlockLink );
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+
+					xFreeBytesRemaining -= pxBlock->xBlockSize;
+
+					if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining )
+					{
+						xMinimumEverFreeBytesRemaining = xFreeBytesRemaining;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+
+					/* The block is being returned - it is allocated and owned
+					by the application and has no "next" block. */
+					pxBlock->xBlockSize |= xBlockAllocatedBit;
+					pxBlock->pxNextFreeBlock = NULL;
+					xNumberOfSuccessfulAllocations++;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		traceMALLOC( pvReturn, xWantedSize );
+	}
+	( void ) xTaskResumeAll();
+
+	#if( configUSE_MALLOC_FAILED_HOOK == 1 )
+	{
+		if( pvReturn == NULL )
+		{
+			extern void vApplicationMallocFailedHook( void );
+			vApplicationMallocFailedHook();
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	#endif
+
+	configASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) portBYTE_ALIGNMENT_MASK ) == 0 );
+	return pvReturn;
+}
+/*-----------------------------------------------------------*/
+
+void vPortFree( void *pv )
+{
+uint8_t *puc = ( uint8_t * ) pv;
+BlockLink_t *pxLink;
+
+	if( pv != NULL )
+	{
+		/* The memory being freed will have an BlockLink_t structure immediately
+		before it. */
+		puc -= xHeapStructSize;
+
+		/* This casting is to keep the compiler from issuing warnings. */
+		pxLink = ( void * ) puc;
+
+		/* Check the block is actually allocated. */
+		configASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 );
+		configASSERT( pxLink->pxNextFreeBlock == NULL );
+
+		if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 )
+		{
+			if( pxLink->pxNextFreeBlock == NULL )
+			{
+				/* The block is being returned to the heap - it is no longer
+				allocated. */
+				pxLink->xBlockSize &= ~xBlockAllocatedBit;
+
+				vTaskSuspendAll();
+				{
+					/* Add this block to the list of free blocks. */
+					xFreeBytesRemaining += pxLink->xBlockSize;
+					traceFREE( pv, pxLink->xBlockSize );
+					prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) );
+					xNumberOfSuccessfulFrees++;
+				}
+				( void ) xTaskResumeAll();
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+size_t xPortGetFreeHeapSize( void )
+{
+	return xFreeBytesRemaining;
+}
+/*-----------------------------------------------------------*/
+
+size_t xPortGetMinimumEverFreeHeapSize( void )
+{
+	return xMinimumEverFreeBytesRemaining;
+}
+/*-----------------------------------------------------------*/
+
+void vPortInitialiseBlocks( void )
+{
+	/* This just exists to keep the linker quiet. */
+}
+/*-----------------------------------------------------------*/
+
+static void prvHeapInit( void )
+{
+BlockLink_t *pxFirstFreeBlock;
+uint8_t *pucAlignedHeap;
+size_t uxAddress;
+size_t xTotalHeapSize = configTOTAL_HEAP_SIZE;
+
+	/* Ensure the heap starts on a correctly aligned boundary. */
+	uxAddress = ( size_t ) ucHeap;
+
+	if( ( uxAddress & portBYTE_ALIGNMENT_MASK ) != 0 )
+	{
+		uxAddress += ( portBYTE_ALIGNMENT - 1 );
+		uxAddress &= ~( ( size_t ) portBYTE_ALIGNMENT_MASK );
+		xTotalHeapSize -= uxAddress - ( size_t ) ucHeap;
+	}
+
+	pucAlignedHeap = ( uint8_t * ) uxAddress;
+
+	/* xStart is used to hold a pointer to the first item in the list of free
+	blocks.  The void cast is used to prevent compiler warnings. */
+	xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap;
+	xStart.xBlockSize = ( size_t ) 0;
+
+	/* pxEnd is used to mark the end of the list of free blocks and is inserted
+	at the end of the heap space. */
+	uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize;
+	uxAddress -= xHeapStructSize;
+	uxAddress &= ~( ( size_t ) portBYTE_ALIGNMENT_MASK );
+	pxEnd = ( void * ) uxAddress;
+	pxEnd->xBlockSize = 0;
+	pxEnd->pxNextFreeBlock = NULL;
+
+	/* To start with there is a single free block that is sized to take up the
+	entire heap space, minus the space taken by pxEnd. */
+	pxFirstFreeBlock = ( void * ) pucAlignedHeap;
+	pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock;
+	pxFirstFreeBlock->pxNextFreeBlock = pxEnd;
+
+	/* Only one block exists - and it covers the entire usable heap space. */
+	xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
+	xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
+
+	/* Work out the position of the top bit in a size_t variable. */
+	xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * heapBITS_PER_BYTE ) - 1 );
+}
+/*-----------------------------------------------------------*/
+
+static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert )
+{
+BlockLink_t *pxIterator;
+uint8_t *puc;
+
+	/* Iterate through the list until a block is found that has a higher address
+	than the block being inserted. */
+	for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock )
+	{
+		/* Nothing to do here, just iterate to the right position. */
+	}
+
+	/* Do the block being inserted, and the block it is being inserted after
+	make a contiguous block of memory? */
+	puc = ( uint8_t * ) pxIterator;
+	if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert )
+	{
+		pxIterator->xBlockSize += pxBlockToInsert->xBlockSize;
+		pxBlockToInsert = pxIterator;
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	/* Do the block being inserted, and the block it is being inserted before
+	make a contiguous block of memory? */
+	puc = ( uint8_t * ) pxBlockToInsert;
+	if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock )
+	{
+		if( pxIterator->pxNextFreeBlock != pxEnd )
+		{
+			/* Form one big block from the two blocks. */
+			pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize;
+			pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock;
+		}
+		else
+		{
+			pxBlockToInsert->pxNextFreeBlock = pxEnd;
+		}
+	}
+	else
+	{
+		pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;
+	}
+
+	/* If the block being inserted plugged a gab, so was merged with the block
+	before and the block after, then it's pxNextFreeBlock pointer will have
+	already been set, and should not be set here as that would make it point
+	to itself. */
+	if( pxIterator != pxBlockToInsert )
+	{
+		pxIterator->pxNextFreeBlock = pxBlockToInsert;
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vPortGetHeapStats( HeapStats_t *pxHeapStats )
+{
+BlockLink_t *pxBlock;
+size_t xBlocks = 0, xMaxSize = 0, xMinSize = portMAX_DELAY; /* portMAX_DELAY used as a portable way of getting the maximum value. */
+
+	vTaskSuspendAll();
+	{
+		pxBlock = xStart.pxNextFreeBlock;
+
+		/* pxBlock will be NULL if the heap has not been initialised.  The heap
+		is initialised automatically when the first allocation is made. */
+		if( pxBlock != NULL )
+		{
+			do
+			{
+				/* Increment the number of blocks and record the largest block seen
+				so far. */
+				xBlocks++;
+
+				if( pxBlock->xBlockSize > xMaxSize )
+				{
+					xMaxSize = pxBlock->xBlockSize;
+				}
+
+				if( pxBlock->xBlockSize < xMinSize )
+				{
+					xMinSize = pxBlock->xBlockSize;
+				}
+
+				/* Move to the next block in the chain until the last block is
+				reached. */
+				pxBlock = pxBlock->pxNextFreeBlock;
+			} while( pxBlock != pxEnd );
+		}
+	}
+	xTaskResumeAll();
+
+	pxHeapStats->xSizeOfLargestFreeBlockInBytes = xMaxSize;
+	pxHeapStats->xSizeOfSmallestFreeBlockInBytes = xMinSize;
+	pxHeapStats->xNumberOfFreeBlocks = xBlocks;
+
+	taskENTER_CRITICAL();
+	{
+		pxHeapStats->xAvailableHeapSpaceInBytes = xFreeBytesRemaining;
+		pxHeapStats->xNumberOfSuccessfulAllocations = xNumberOfSuccessfulAllocations;
+		pxHeapStats->xNumberOfSuccessfulFrees = xNumberOfSuccessfulFrees;
+		pxHeapStats->xMinimumEverFreeBytesRemaining = xMinimumEverFreeBytesRemaining;
+	}
+	taskEXIT_CRITICAL();
+}
+
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/queue.c b/Middlewares/Third_Party/FreeRTOS/Source/queue.c
new file mode 100644
index 0000000..b3203b8
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/queue.c
@@ -0,0 +1,2945 @@
+/*
+ * FreeRTOS Kernel V10.3.1
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#include <stdlib.h>
+#include <string.h>
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+all the API functions to use the MPU wrappers.  That should only be done when
+task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+#include "FreeRTOS.h"
+#include "task.h"
+#include "queue.h"
+
+#if ( configUSE_CO_ROUTINES == 1 )
+	#include "croutine.h"
+#endif
+
+/* Lint e9021, e961 and e750 are suppressed as a MISRA exception justified
+because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined
+for the header files above, but not in this file, in order to generate the
+correct privileged Vs unprivileged linkage and placement. */
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750 !e9021. */
+
+
+/* Constants used with the cRxLock and cTxLock structure members. */
+#define queueUNLOCKED					( ( int8_t ) -1 )
+#define queueLOCKED_UNMODIFIED			( ( int8_t ) 0 )
+
+/* When the Queue_t structure is used to represent a base queue its pcHead and
+pcTail members are used as pointers into the queue storage area.  When the
+Queue_t structure is used to represent a mutex pcHead and pcTail pointers are
+not necessary, and the pcHead pointer is set to NULL to indicate that the
+structure instead holds a pointer to the mutex holder (if any).  Map alternative
+names to the pcHead and structure member to ensure the readability of the code
+is maintained.  The QueuePointers_t and SemaphoreData_t types are used to form
+a union as their usage is mutually exclusive dependent on what the queue is
+being used for. */
+#define uxQueueType						pcHead
+#define queueQUEUE_IS_MUTEX				NULL
+
+typedef struct QueuePointers
+{
+	int8_t *pcTail;					/*< Points to the byte at the end of the queue storage area.  Once more byte is allocated than necessary to store the queue items, this is used as a marker. */
+	int8_t *pcReadFrom;				/*< Points to the last place that a queued item was read from when the structure is used as a queue. */
+} QueuePointers_t;
+
+typedef struct SemaphoreData
+{
+	TaskHandle_t xMutexHolder;		 /*< The handle of the task that holds the mutex. */
+	UBaseType_t uxRecursiveCallCount;/*< Maintains a count of the number of times a recursive mutex has been recursively 'taken' when the structure is used as a mutex. */
+} SemaphoreData_t;
+
+/* Semaphores do not actually store or copy data, so have an item size of
+zero. */
+#define queueSEMAPHORE_QUEUE_ITEM_LENGTH ( ( UBaseType_t ) 0 )
+#define queueMUTEX_GIVE_BLOCK_TIME		 ( ( TickType_t ) 0U )
+
+#if( configUSE_PREEMPTION == 0 )
+	/* If the cooperative scheduler is being used then a yield should not be
+	performed just because a higher priority task has been woken. */
+	#define queueYIELD_IF_USING_PREEMPTION()
+#else
+	#define queueYIELD_IF_USING_PREEMPTION() portYIELD_WITHIN_API()
+#endif
+
+/*
+ * Definition of the queue used by the scheduler.
+ * Items are queued by copy, not reference.  See the following link for the
+ * rationale: https://www.freertos.org/Embedded-RTOS-Queues.html
+ */
+typedef struct QueueDefinition 		/* The old naming convention is used to prevent breaking kernel aware debuggers. */
+{
+	int8_t *pcHead;					/*< Points to the beginning of the queue storage area. */
+	int8_t *pcWriteTo;				/*< Points to the free next place in the storage area. */
+
+	union
+	{
+		QueuePointers_t xQueue;		/*< Data required exclusively when this structure is used as a queue. */
+		SemaphoreData_t xSemaphore; /*< Data required exclusively when this structure is used as a semaphore. */
+	} u;
+
+	List_t xTasksWaitingToSend;		/*< List of tasks that are blocked waiting to post onto this queue.  Stored in priority order. */
+	List_t xTasksWaitingToReceive;	/*< List of tasks that are blocked waiting to read from this queue.  Stored in priority order. */
+
+	volatile UBaseType_t uxMessagesWaiting;/*< The number of items currently in the queue. */
+	UBaseType_t uxLength;			/*< The length of the queue defined as the number of items it will hold, not the number of bytes. */
+	UBaseType_t uxItemSize;			/*< The size of each items that the queue will hold. */
+
+	volatile int8_t cRxLock;		/*< Stores the number of items received from the queue (removed from the queue) while the queue was locked.  Set to queueUNLOCKED when the queue is not locked. */
+	volatile int8_t cTxLock;		/*< Stores the number of items transmitted to the queue (added to the queue) while the queue was locked.  Set to queueUNLOCKED when the queue is not locked. */
+
+	#if( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+		uint8_t ucStaticallyAllocated;	/*< Set to pdTRUE if the memory used by the queue was statically allocated to ensure no attempt is made to free the memory. */
+	#endif
+
+	#if ( configUSE_QUEUE_SETS == 1 )
+		struct QueueDefinition *pxQueueSetContainer;
+	#endif
+
+	#if ( configUSE_TRACE_FACILITY == 1 )
+		UBaseType_t uxQueueNumber;
+		uint8_t ucQueueType;
+	#endif
+
+} xQUEUE;
+
+/* The old xQUEUE name is maintained above then typedefed to the new Queue_t
+name below to enable the use of older kernel aware debuggers. */
+typedef xQUEUE Queue_t;
+
+/*-----------------------------------------------------------*/
+
+/*
+ * The queue registry is just a means for kernel aware debuggers to locate
+ * queue structures.  It has no other purpose so is an optional component.
+ */
+#if ( configQUEUE_REGISTRY_SIZE > 0 )
+
+	/* The type stored within the queue registry array.  This allows a name
+	to be assigned to each queue making kernel aware debugging a little
+	more user friendly. */
+	typedef struct QUEUE_REGISTRY_ITEM
+	{
+		const char *pcQueueName; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+		QueueHandle_t xHandle;
+	} xQueueRegistryItem;
+
+	/* The old xQueueRegistryItem name is maintained above then typedefed to the
+	new xQueueRegistryItem name below to enable the use of older kernel aware
+	debuggers. */
+	typedef xQueueRegistryItem QueueRegistryItem_t;
+
+	/* The queue registry is simply an array of QueueRegistryItem_t structures.
+	The pcQueueName member of a structure being NULL is indicative of the
+	array position being vacant. */
+	PRIVILEGED_DATA QueueRegistryItem_t xQueueRegistry[ configQUEUE_REGISTRY_SIZE ];
+
+#endif /* configQUEUE_REGISTRY_SIZE */
+
+/*
+ * Unlocks a queue locked by a call to prvLockQueue.  Locking a queue does not
+ * prevent an ISR from adding or removing items to the queue, but does prevent
+ * an ISR from removing tasks from the queue event lists.  If an ISR finds a
+ * queue is locked it will instead increment the appropriate queue lock count
+ * to indicate that a task may require unblocking.  When the queue in unlocked
+ * these lock counts are inspected, and the appropriate action taken.
+ */
+static void prvUnlockQueue( Queue_t * const pxQueue ) PRIVILEGED_FUNCTION;
+
+/*
+ * Uses a critical section to determine if there is any data in a queue.
+ *
+ * @return pdTRUE if the queue contains no items, otherwise pdFALSE.
+ */
+static BaseType_t prvIsQueueEmpty( const Queue_t *pxQueue ) PRIVILEGED_FUNCTION;
+
+/*
+ * Uses a critical section to determine if there is any space in a queue.
+ *
+ * @return pdTRUE if there is no space, otherwise pdFALSE;
+ */
+static BaseType_t prvIsQueueFull( const Queue_t *pxQueue ) PRIVILEGED_FUNCTION;
+
+/*
+ * Copies an item into the queue, either at the front of the queue or the
+ * back of the queue.
+ */
+static BaseType_t prvCopyDataToQueue( Queue_t * const pxQueue, const void *pvItemToQueue, const BaseType_t xPosition ) PRIVILEGED_FUNCTION;
+
+/*
+ * Copies an item out of a queue.
+ */
+static void prvCopyDataFromQueue( Queue_t * const pxQueue, void * const pvBuffer ) PRIVILEGED_FUNCTION;
+
+#if ( configUSE_QUEUE_SETS == 1 )
+	/*
+	 * Checks to see if a queue is a member of a queue set, and if so, notifies
+	 * the queue set that the queue contains data.
+	 */
+	static BaseType_t prvNotifyQueueSetContainer( const Queue_t * const pxQueue ) PRIVILEGED_FUNCTION;
+#endif
+
+/*
+ * Called after a Queue_t structure has been allocated either statically or
+ * dynamically to fill in the structure's members.
+ */
+static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, const uint8_t ucQueueType, Queue_t *pxNewQueue ) PRIVILEGED_FUNCTION;
+
+/*
+ * Mutexes are a special type of queue.  When a mutex is created, first the
+ * queue is created, then prvInitialiseMutex() is called to configure the queue
+ * as a mutex.
+ */
+#if( configUSE_MUTEXES == 1 )
+	static void prvInitialiseMutex( Queue_t *pxNewQueue ) PRIVILEGED_FUNCTION;
+#endif
+
+#if( configUSE_MUTEXES == 1 )
+	/*
+	 * If a task waiting for a mutex causes the mutex holder to inherit a
+	 * priority, but the waiting task times out, then the holder should
+	 * disinherit the priority - but only down to the highest priority of any
+	 * other tasks that are waiting for the same mutex.  This function returns
+	 * that priority.
+	 */
+	static UBaseType_t prvGetDisinheritPriorityAfterTimeout( const Queue_t * const pxQueue ) PRIVILEGED_FUNCTION;
+#endif
+/*-----------------------------------------------------------*/
+
+/*
+ * Macro to mark a queue as locked.  Locking a queue prevents an ISR from
+ * accessing the queue event lists.
+ */
+#define prvLockQueue( pxQueue )								\
+	taskENTER_CRITICAL();									\
+	{														\
+		if( ( pxQueue )->cRxLock == queueUNLOCKED )			\
+		{													\
+			( pxQueue )->cRxLock = queueLOCKED_UNMODIFIED;	\
+		}													\
+		if( ( pxQueue )->cTxLock == queueUNLOCKED )			\
+		{													\
+			( pxQueue )->cTxLock = queueLOCKED_UNMODIFIED;	\
+		}													\
+	}														\
+	taskEXIT_CRITICAL()
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueGenericReset( QueueHandle_t xQueue, BaseType_t xNewQueue )
+{
+Queue_t * const pxQueue = xQueue;
+
+	configASSERT( pxQueue );
+
+	taskENTER_CRITICAL();
+	{
+		pxQueue->u.xQueue.pcTail = pxQueue->pcHead + ( pxQueue->uxLength * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
+		pxQueue->uxMessagesWaiting = ( UBaseType_t ) 0U;
+		pxQueue->pcWriteTo = pxQueue->pcHead;
+		pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead + ( ( pxQueue->uxLength - 1U ) * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
+		pxQueue->cRxLock = queueUNLOCKED;
+		pxQueue->cTxLock = queueUNLOCKED;
+
+		if( xNewQueue == pdFALSE )
+		{
+			/* If there are tasks blocked waiting to read from the queue, then
+			the tasks will remain blocked as after this function exits the queue
+			will still be empty.  If there are tasks blocked waiting to write to
+			the queue, then one should be unblocked as after this function exits
+			it will be possible to write to it. */
+			if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
+			{
+				if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
+				{
+					queueYIELD_IF_USING_PREEMPTION();
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			/* Ensure the event queues start in the correct state. */
+			vListInitialise( &( pxQueue->xTasksWaitingToSend ) );
+			vListInitialise( &( pxQueue->xTasksWaitingToReceive ) );
+		}
+	}
+	taskEXIT_CRITICAL();
+
+	/* A value is returned for calling semantic consistency with previous
+	versions. */
+	return pdPASS;
+}
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+
+	QueueHandle_t xQueueGenericCreateStatic( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, StaticQueue_t *pxStaticQueue, const uint8_t ucQueueType )
+	{
+	Queue_t *pxNewQueue;
+
+		configASSERT( uxQueueLength > ( UBaseType_t ) 0 );
+
+		/* The StaticQueue_t structure and the queue storage area must be
+		supplied. */
+		configASSERT( pxStaticQueue != NULL );
+
+		/* A queue storage area should be provided if the item size is not 0, and
+		should not be provided if the item size is 0. */
+		configASSERT( !( ( pucQueueStorage != NULL ) && ( uxItemSize == 0 ) ) );
+		configASSERT( !( ( pucQueueStorage == NULL ) && ( uxItemSize != 0 ) ) );
+
+		#if( configASSERT_DEFINED == 1 )
+		{
+			/* Sanity check that the size of the structure used to declare a
+			variable of type StaticQueue_t or StaticSemaphore_t equals the size of
+			the real queue and semaphore structures. */
+			volatile size_t xSize = sizeof( StaticQueue_t );
+			configASSERT( xSize == sizeof( Queue_t ) );
+			( void ) xSize; /* Keeps lint quiet when configASSERT() is not defined. */
+		}
+		#endif /* configASSERT_DEFINED */
+
+		/* The address of a statically allocated queue was passed in, use it.
+		The address of a statically allocated storage area was also passed in
+		but is already set. */
+		pxNewQueue = ( Queue_t * ) pxStaticQueue; /*lint !e740 !e9087 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */
+
+		if( pxNewQueue != NULL )
+		{
+			#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+			{
+				/* Queues can be allocated wither statically or dynamically, so
+				note this queue was allocated statically in case the queue is
+				later deleted. */
+				pxNewQueue->ucStaticallyAllocated = pdTRUE;
+			}
+			#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+
+			prvInitialiseNewQueue( uxQueueLength, uxItemSize, pucQueueStorage, ucQueueType, pxNewQueue );
+		}
+		else
+		{
+			traceQUEUE_CREATE_FAILED( ucQueueType );
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		return pxNewQueue;
+	}
+
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+
+	QueueHandle_t xQueueGenericCreate( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, const uint8_t ucQueueType )
+	{
+	Queue_t *pxNewQueue;
+	size_t xQueueSizeInBytes;
+	uint8_t *pucQueueStorage;
+
+		configASSERT( uxQueueLength > ( UBaseType_t ) 0 );
+
+		/* Allocate enough space to hold the maximum number of items that
+		can be in the queue at any time.  It is valid for uxItemSize to be
+		zero in the case the queue is used as a semaphore. */
+		xQueueSizeInBytes = ( size_t ) ( uxQueueLength * uxItemSize ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+
+		/* Allocate the queue and storage area.  Justification for MISRA
+		deviation as follows:  pvPortMalloc() always ensures returned memory
+		blocks are aligned per the requirements of the MCU stack.  In this case
+		pvPortMalloc() must return a pointer that is guaranteed to meet the
+		alignment requirements of the Queue_t structure - which in this case
+		is an int8_t *.  Therefore, whenever the stack alignment requirements
+		are greater than or equal to the pointer to char requirements the cast
+		is safe.  In other cases alignment requirements are not strict (one or
+		two bytes). */
+		pxNewQueue = ( Queue_t * ) pvPortMalloc( sizeof( Queue_t ) + xQueueSizeInBytes ); /*lint !e9087 !e9079 see comment above. */
+
+		if( pxNewQueue != NULL )
+		{
+			/* Jump past the queue structure to find the location of the queue
+			storage area. */
+			pucQueueStorage = ( uint8_t * ) pxNewQueue;
+			pucQueueStorage += sizeof( Queue_t ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
+
+			#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+			{
+				/* Queues can be created either statically or dynamically, so
+				note this task was created dynamically in case it is later
+				deleted. */
+				pxNewQueue->ucStaticallyAllocated = pdFALSE;
+			}
+			#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+			prvInitialiseNewQueue( uxQueueLength, uxItemSize, pucQueueStorage, ucQueueType, pxNewQueue );
+		}
+		else
+		{
+			traceQUEUE_CREATE_FAILED( ucQueueType );
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		return pxNewQueue;
+	}
+
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, const uint8_t ucQueueType, Queue_t *pxNewQueue )
+{
+	/* Remove compiler warnings about unused parameters should
+	configUSE_TRACE_FACILITY not be set to 1. */
+	( void ) ucQueueType;
+
+	if( uxItemSize == ( UBaseType_t ) 0 )
+	{
+		/* No RAM was allocated for the queue storage area, but PC head cannot
+		be set to NULL because NULL is used as a key to say the queue is used as
+		a mutex.  Therefore just set pcHead to point to the queue as a benign
+		value that is known to be within the memory map. */
+		pxNewQueue->pcHead = ( int8_t * ) pxNewQueue;
+	}
+	else
+	{
+		/* Set the head to the start of the queue storage area. */
+		pxNewQueue->pcHead = ( int8_t * ) pucQueueStorage;
+	}
+
+	/* Initialise the queue members as described where the queue type is
+	defined. */
+	pxNewQueue->uxLength = uxQueueLength;
+	pxNewQueue->uxItemSize = uxItemSize;
+	( void ) xQueueGenericReset( pxNewQueue, pdTRUE );
+
+	#if ( configUSE_TRACE_FACILITY == 1 )
+	{
+		pxNewQueue->ucQueueType = ucQueueType;
+	}
+	#endif /* configUSE_TRACE_FACILITY */
+
+	#if( configUSE_QUEUE_SETS == 1 )
+	{
+		pxNewQueue->pxQueueSetContainer = NULL;
+	}
+	#endif /* configUSE_QUEUE_SETS */
+
+	traceQUEUE_CREATE( pxNewQueue );
+}
+/*-----------------------------------------------------------*/
+
+#if( configUSE_MUTEXES == 1 )
+
+	static void prvInitialiseMutex( Queue_t *pxNewQueue )
+	{
+		if( pxNewQueue != NULL )
+		{
+			/* The queue create function will set all the queue structure members
+			correctly for a generic queue, but this function is creating a
+			mutex.  Overwrite those members that need to be set differently -
+			in particular the information required for priority inheritance. */
+			pxNewQueue->u.xSemaphore.xMutexHolder = NULL;
+			pxNewQueue->uxQueueType = queueQUEUE_IS_MUTEX;
+
+			/* In case this is a recursive mutex. */
+			pxNewQueue->u.xSemaphore.uxRecursiveCallCount = 0;
+
+			traceCREATE_MUTEX( pxNewQueue );
+
+			/* Start with the semaphore in the expected state. */
+			( void ) xQueueGenericSend( pxNewQueue, NULL, ( TickType_t ) 0U, queueSEND_TO_BACK );
+		}
+		else
+		{
+			traceCREATE_MUTEX_FAILED();
+		}
+	}
+
+#endif /* configUSE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+#if( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+
+	QueueHandle_t xQueueCreateMutex( const uint8_t ucQueueType )
+	{
+	QueueHandle_t xNewQueue;
+	const UBaseType_t uxMutexLength = ( UBaseType_t ) 1, uxMutexSize = ( UBaseType_t ) 0;
+
+		xNewQueue = xQueueGenericCreate( uxMutexLength, uxMutexSize, ucQueueType );
+		prvInitialiseMutex( ( Queue_t * ) xNewQueue );
+
+		return xNewQueue;
+	}
+
+#endif /* configUSE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+#if( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
+
+	QueueHandle_t xQueueCreateMutexStatic( const uint8_t ucQueueType, StaticQueue_t *pxStaticQueue )
+	{
+	QueueHandle_t xNewQueue;
+	const UBaseType_t uxMutexLength = ( UBaseType_t ) 1, uxMutexSize = ( UBaseType_t ) 0;
+
+		/* Prevent compiler warnings about unused parameters if
+		configUSE_TRACE_FACILITY does not equal 1. */
+		( void ) ucQueueType;
+
+		xNewQueue = xQueueGenericCreateStatic( uxMutexLength, uxMutexSize, NULL, pxStaticQueue, ucQueueType );
+		prvInitialiseMutex( ( Queue_t * ) xNewQueue );
+
+		return xNewQueue;
+	}
+
+#endif /* configUSE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+#if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) )
+
+	TaskHandle_t xQueueGetMutexHolder( QueueHandle_t xSemaphore )
+	{
+	TaskHandle_t pxReturn;
+	Queue_t * const pxSemaphore = ( Queue_t * ) xSemaphore;
+
+		/* This function is called by xSemaphoreGetMutexHolder(), and should not
+		be called directly.  Note:  This is a good way of determining if the
+		calling task is the mutex holder, but not a good way of determining the
+		identity of the mutex holder, as the holder may change between the
+		following critical section exiting and the function returning. */
+		taskENTER_CRITICAL();
+		{
+			if( pxSemaphore->uxQueueType == queueQUEUE_IS_MUTEX )
+			{
+				pxReturn = pxSemaphore->u.xSemaphore.xMutexHolder;
+			}
+			else
+			{
+				pxReturn = NULL;
+			}
+		}
+		taskEXIT_CRITICAL();
+
+		return pxReturn;
+	} /*lint !e818 xSemaphore cannot be a pointer to const because it is a typedef. */
+
+#endif
+/*-----------------------------------------------------------*/
+
+#if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) )
+
+	TaskHandle_t xQueueGetMutexHolderFromISR( QueueHandle_t xSemaphore )
+	{
+	TaskHandle_t pxReturn;
+
+		configASSERT( xSemaphore );
+
+		/* Mutexes cannot be used in interrupt service routines, so the mutex
+		holder should not change in an ISR, and therefore a critical section is
+		not required here. */
+		if( ( ( Queue_t * ) xSemaphore )->uxQueueType == queueQUEUE_IS_MUTEX )
+		{
+			pxReturn = ( ( Queue_t * ) xSemaphore )->u.xSemaphore.xMutexHolder;
+		}
+		else
+		{
+			pxReturn = NULL;
+		}
+
+		return pxReturn;
+	} /*lint !e818 xSemaphore cannot be a pointer to const because it is a typedef. */
+
+#endif
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_RECURSIVE_MUTEXES == 1 )
+
+	BaseType_t xQueueGiveMutexRecursive( QueueHandle_t xMutex )
+	{
+	BaseType_t xReturn;
+	Queue_t * const pxMutex = ( Queue_t * ) xMutex;
+
+		configASSERT( pxMutex );
+
+		/* If this is the task that holds the mutex then xMutexHolder will not
+		change outside of this task.  If this task does not hold the mutex then
+		pxMutexHolder can never coincidentally equal the tasks handle, and as
+		this is the only condition we are interested in it does not matter if
+		pxMutexHolder is accessed simultaneously by another task.  Therefore no
+		mutual exclusion is required to test the pxMutexHolder variable. */
+		if( pxMutex->u.xSemaphore.xMutexHolder == xTaskGetCurrentTaskHandle() )
+		{
+			traceGIVE_MUTEX_RECURSIVE( pxMutex );
+
+			/* uxRecursiveCallCount cannot be zero if xMutexHolder is equal to
+			the task handle, therefore no underflow check is required.  Also,
+			uxRecursiveCallCount is only modified by the mutex holder, and as
+			there can only be one, no mutual exclusion is required to modify the
+			uxRecursiveCallCount member. */
+			( pxMutex->u.xSemaphore.uxRecursiveCallCount )--;
+
+			/* Has the recursive call count unwound to 0? */
+			if( pxMutex->u.xSemaphore.uxRecursiveCallCount == ( UBaseType_t ) 0 )
+			{
+				/* Return the mutex.  This will automatically unblock any other
+				task that might be waiting to access the mutex. */
+				( void ) xQueueGenericSend( pxMutex, NULL, queueMUTEX_GIVE_BLOCK_TIME, queueSEND_TO_BACK );
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+
+			xReturn = pdPASS;
+		}
+		else
+		{
+			/* The mutex cannot be given because the calling task is not the
+			holder. */
+			xReturn = pdFAIL;
+
+			traceGIVE_MUTEX_RECURSIVE_FAILED( pxMutex );
+		}
+
+		return xReturn;
+	}
+
+#endif /* configUSE_RECURSIVE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_RECURSIVE_MUTEXES == 1 )
+
+	BaseType_t xQueueTakeMutexRecursive( QueueHandle_t xMutex, TickType_t xTicksToWait )
+	{
+	BaseType_t xReturn;
+	Queue_t * const pxMutex = ( Queue_t * ) xMutex;
+
+		configASSERT( pxMutex );
+
+		/* Comments regarding mutual exclusion as per those within
+		xQueueGiveMutexRecursive(). */
+
+		traceTAKE_MUTEX_RECURSIVE( pxMutex );
+
+		if( pxMutex->u.xSemaphore.xMutexHolder == xTaskGetCurrentTaskHandle() )
+		{
+			( pxMutex->u.xSemaphore.uxRecursiveCallCount )++;
+			xReturn = pdPASS;
+		}
+		else
+		{
+			xReturn = xQueueSemaphoreTake( pxMutex, xTicksToWait );
+
+			/* pdPASS will only be returned if the mutex was successfully
+			obtained.  The calling task may have entered the Blocked state
+			before reaching here. */
+			if( xReturn != pdFAIL )
+			{
+				( pxMutex->u.xSemaphore.uxRecursiveCallCount )++;
+			}
+			else
+			{
+				traceTAKE_MUTEX_RECURSIVE_FAILED( pxMutex );
+			}
+		}
+
+		return xReturn;
+	}
+
+#endif /* configUSE_RECURSIVE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+#if( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
+
+	QueueHandle_t xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount, StaticQueue_t *pxStaticQueue )
+	{
+	QueueHandle_t xHandle;
+
+		configASSERT( uxMaxCount != 0 );
+		configASSERT( uxInitialCount <= uxMaxCount );
+
+		xHandle = xQueueGenericCreateStatic( uxMaxCount, queueSEMAPHORE_QUEUE_ITEM_LENGTH, NULL, pxStaticQueue, queueQUEUE_TYPE_COUNTING_SEMAPHORE );
+
+		if( xHandle != NULL )
+		{
+			( ( Queue_t * ) xHandle )->uxMessagesWaiting = uxInitialCount;
+
+			traceCREATE_COUNTING_SEMAPHORE();
+		}
+		else
+		{
+			traceCREATE_COUNTING_SEMAPHORE_FAILED();
+		}
+
+		return xHandle;
+	}
+
+#endif /* ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+
+	QueueHandle_t xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount )
+	{
+	QueueHandle_t xHandle;
+
+		configASSERT( uxMaxCount != 0 );
+		configASSERT( uxInitialCount <= uxMaxCount );
+
+		xHandle = xQueueGenericCreate( uxMaxCount, queueSEMAPHORE_QUEUE_ITEM_LENGTH, queueQUEUE_TYPE_COUNTING_SEMAPHORE );
+
+		if( xHandle != NULL )
+		{
+			( ( Queue_t * ) xHandle )->uxMessagesWaiting = uxInitialCount;
+
+			traceCREATE_COUNTING_SEMAPHORE();
+		}
+		else
+		{
+			traceCREATE_COUNTING_SEMAPHORE_FAILED();
+		}
+
+		return xHandle;
+	}
+
+#endif /* ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, const BaseType_t xCopyPosition )
+{
+BaseType_t xEntryTimeSet = pdFALSE, xYieldRequired;
+TimeOut_t xTimeOut;
+Queue_t * const pxQueue = xQueue;
+
+	configASSERT( pxQueue );
+	configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
+	configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) );
+	#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
+	{
+		configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
+	}
+	#endif
+
+
+	/*lint -save -e904 This function relaxes the coding standard somewhat to
+	allow return statements within the function itself.  This is done in the
+	interest of execution time efficiency. */
+	for( ;; )
+	{
+		taskENTER_CRITICAL();
+		{
+			/* Is there room on the queue now?  The running task must be the
+			highest priority task wanting to access the queue.  If the head item
+			in the queue is to be overwritten then it does not matter if the
+			queue is full. */
+			if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) )
+			{
+				traceQUEUE_SEND( pxQueue );
+
+				#if ( configUSE_QUEUE_SETS == 1 )
+				{
+				const UBaseType_t uxPreviousMessagesWaiting = pxQueue->uxMessagesWaiting;
+
+					xYieldRequired = prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );
+
+					if( pxQueue->pxQueueSetContainer != NULL )
+					{
+						if( ( xCopyPosition == queueOVERWRITE ) && ( uxPreviousMessagesWaiting != ( UBaseType_t ) 0 ) )
+						{
+							/* Do not notify the queue set as an existing item
+							was overwritten in the queue so the number of items
+							in the queue has not changed. */
+							mtCOVERAGE_TEST_MARKER();
+						}
+						else if( prvNotifyQueueSetContainer( pxQueue ) != pdFALSE )
+						{
+							/* The queue is a member of a queue set, and posting
+							to the queue set caused a higher priority task to
+							unblock. A context switch is required. */
+							queueYIELD_IF_USING_PREEMPTION();
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+					else
+					{
+						/* If there was a task waiting for data to arrive on the
+						queue then unblock it now. */
+						if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+						{
+							if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+							{
+								/* The unblocked task has a priority higher than
+								our own so yield immediately.  Yes it is ok to
+								do this from within the critical section - the
+								kernel takes care of that. */
+								queueYIELD_IF_USING_PREEMPTION();
+							}
+							else
+							{
+								mtCOVERAGE_TEST_MARKER();
+							}
+						}
+						else if( xYieldRequired != pdFALSE )
+						{
+							/* This path is a special case that will only get
+							executed if the task was holding multiple mutexes
+							and the mutexes were given back in an order that is
+							different to that in which they were taken. */
+							queueYIELD_IF_USING_PREEMPTION();
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+				}
+				#else /* configUSE_QUEUE_SETS */
+				{
+					xYieldRequired = prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );
+
+					/* If there was a task waiting for data to arrive on the
+					queue then unblock it now. */
+					if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+					{
+						if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+						{
+							/* The unblocked task has a priority higher than
+							our own so yield immediately.  Yes it is ok to do
+							this from within the critical section - the kernel
+							takes care of that. */
+							queueYIELD_IF_USING_PREEMPTION();
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+					else if( xYieldRequired != pdFALSE )
+					{
+						/* This path is a special case that will only get
+						executed if the task was holding multiple mutexes and
+						the mutexes were given back in an order that is
+						different to that in which they were taken. */
+						queueYIELD_IF_USING_PREEMPTION();
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				#endif /* configUSE_QUEUE_SETS */
+
+				taskEXIT_CRITICAL();
+				return pdPASS;
+			}
+			else
+			{
+				if( xTicksToWait == ( TickType_t ) 0 )
+				{
+					/* The queue was full and no block time is specified (or
+					the block time has expired) so leave now. */
+					taskEXIT_CRITICAL();
+
+					/* Return to the original privilege level before exiting
+					the function. */
+					traceQUEUE_SEND_FAILED( pxQueue );
+					return errQUEUE_FULL;
+				}
+				else if( xEntryTimeSet == pdFALSE )
+				{
+					/* The queue was full and a block time was specified so
+					configure the timeout structure. */
+					vTaskInternalSetTimeOutState( &xTimeOut );
+					xEntryTimeSet = pdTRUE;
+				}
+				else
+				{
+					/* Entry time was already set. */
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+		}
+		taskEXIT_CRITICAL();
+
+		/* Interrupts and other tasks can send to and receive from the queue
+		now the critical section has been exited. */
+
+		vTaskSuspendAll();
+		prvLockQueue( pxQueue );
+
+		/* Update the timeout state to see if it has expired yet. */
+		if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
+		{
+			if( prvIsQueueFull( pxQueue ) != pdFALSE )
+			{
+				traceBLOCKING_ON_QUEUE_SEND( pxQueue );
+				vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToSend ), xTicksToWait );
+
+				/* Unlocking the queue means queue events can effect the
+				event list.  It is possible that interrupts occurring now
+				remove this task from the event list again - but as the
+				scheduler is suspended the task will go onto the pending
+				ready last instead of the actual ready list. */
+				prvUnlockQueue( pxQueue );
+
+				/* Resuming the scheduler will move tasks from the pending
+				ready list into the ready list - so it is feasible that this
+				task is already in a ready list before it yields - in which
+				case the yield will not cause a context switch unless there
+				is also a higher priority task in the pending ready list. */
+				if( xTaskResumeAll() == pdFALSE )
+				{
+					portYIELD_WITHIN_API();
+				}
+			}
+			else
+			{
+				/* Try again. */
+				prvUnlockQueue( pxQueue );
+				( void ) xTaskResumeAll();
+			}
+		}
+		else
+		{
+			/* The timeout has expired. */
+			prvUnlockQueue( pxQueue );
+			( void ) xTaskResumeAll();
+
+			traceQUEUE_SEND_FAILED( pxQueue );
+			return errQUEUE_FULL;
+		}
+	} /*lint -restore */
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueGenericSendFromISR( QueueHandle_t xQueue, const void * const pvItemToQueue, BaseType_t * const pxHigherPriorityTaskWoken, const BaseType_t xCopyPosition )
+{
+BaseType_t xReturn;
+UBaseType_t uxSavedInterruptStatus;
+Queue_t * const pxQueue = xQueue;
+
+	configASSERT( pxQueue );
+	configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
+	configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) );
+
+	/* RTOS ports that support interrupt nesting have the concept of a maximum
+	system call (or maximum API call) interrupt priority.  Interrupts that are
+	above the maximum system call priority are kept permanently enabled, even
+	when the RTOS kernel is in a critical section, but cannot make any calls to
+	FreeRTOS API functions.  If configASSERT() is defined in FreeRTOSConfig.h
+	then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
+	failure if a FreeRTOS API function is called from an interrupt that has been
+	assigned a priority above the configured maximum system call priority.
+	Only FreeRTOS functions that end in FromISR can be called from interrupts
+	that have been assigned a priority at or (logically) below the maximum
+	system call	interrupt priority.  FreeRTOS maintains a separate interrupt
+	safe API to ensure interrupt entry is as fast and as simple as possible.
+	More information (albeit Cortex-M specific) is provided on the following
+	link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */
+	portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+
+	/* Similar to xQueueGenericSend, except without blocking if there is no room
+	in the queue.  Also don't directly wake a task that was blocked on a queue
+	read, instead return a flag to say whether a context switch is required or
+	not (i.e. has a task with a higher priority than us been woken by this
+	post). */
+	uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+	{
+		if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) )
+		{
+			const int8_t cTxLock = pxQueue->cTxLock;
+			const UBaseType_t uxPreviousMessagesWaiting = pxQueue->uxMessagesWaiting;
+
+			traceQUEUE_SEND_FROM_ISR( pxQueue );
+
+			/* Semaphores use xQueueGiveFromISR(), so pxQueue will not be a
+			semaphore or mutex.  That means prvCopyDataToQueue() cannot result
+			in a task disinheriting a priority and prvCopyDataToQueue() can be
+			called here even though the disinherit function does not check if
+			the scheduler is suspended before accessing the ready lists. */
+			( void ) prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );
+
+			/* The event list is not altered if the queue is locked.  This will
+			be done when the queue is unlocked later. */
+			if( cTxLock == queueUNLOCKED )
+			{
+				#if ( configUSE_QUEUE_SETS == 1 )
+				{
+					if( pxQueue->pxQueueSetContainer != NULL )
+					{
+						if( ( xCopyPosition == queueOVERWRITE ) && ( uxPreviousMessagesWaiting != ( UBaseType_t ) 0 ) )
+						{
+							/* Do not notify the queue set as an existing item
+							was overwritten in the queue so the number of items
+							in the queue has not changed. */
+							mtCOVERAGE_TEST_MARKER();
+						}
+						else if( prvNotifyQueueSetContainer( pxQueue ) != pdFALSE )
+						{
+							/* The queue is a member of a queue set, and posting
+							to the queue set caused a higher priority task to
+							unblock.  A context switch is required. */
+							if( pxHigherPriorityTaskWoken != NULL )
+							{
+								*pxHigherPriorityTaskWoken = pdTRUE;
+							}
+							else
+							{
+								mtCOVERAGE_TEST_MARKER();
+							}
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+					else
+					{
+						if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+						{
+							if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+							{
+								/* The task waiting has a higher priority so
+								record that a context switch is required. */
+								if( pxHigherPriorityTaskWoken != NULL )
+								{
+									*pxHigherPriorityTaskWoken = pdTRUE;
+								}
+								else
+								{
+									mtCOVERAGE_TEST_MARKER();
+								}
+							}
+							else
+							{
+								mtCOVERAGE_TEST_MARKER();
+							}
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+				}
+				#else /* configUSE_QUEUE_SETS */
+				{
+					if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+					{
+						if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+						{
+							/* The task waiting has a higher priority so record that a
+							context	switch is required. */
+							if( pxHigherPriorityTaskWoken != NULL )
+							{
+								*pxHigherPriorityTaskWoken = pdTRUE;
+							}
+							else
+							{
+								mtCOVERAGE_TEST_MARKER();
+							}
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+					
+					/* Not used in this path. */
+					( void ) uxPreviousMessagesWaiting;
+				}
+				#endif /* configUSE_QUEUE_SETS */
+			}
+			else
+			{
+				/* Increment the lock count so the task that unlocks the queue
+				knows that data was posted while it was locked. */
+				pxQueue->cTxLock = ( int8_t ) ( cTxLock + 1 );
+			}
+
+			xReturn = pdPASS;
+		}
+		else
+		{
+			traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue );
+			xReturn = errQUEUE_FULL;
+		}
+	}
+	portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueGiveFromISR( QueueHandle_t xQueue, BaseType_t * const pxHigherPriorityTaskWoken )
+{
+BaseType_t xReturn;
+UBaseType_t uxSavedInterruptStatus;
+Queue_t * const pxQueue = xQueue;
+
+	/* Similar to xQueueGenericSendFromISR() but used with semaphores where the
+	item size is 0.  Don't directly wake a task that was blocked on a queue
+	read, instead return a flag to say whether a context switch is required or
+	not (i.e. has a task with a higher priority than us been woken by this
+	post). */
+
+	configASSERT( pxQueue );
+
+	/* xQueueGenericSendFromISR() should be used instead of xQueueGiveFromISR()
+	if the item size is not 0. */
+	configASSERT( pxQueue->uxItemSize == 0 );
+
+	/* Normally a mutex would not be given from an interrupt, especially if
+	there is a mutex holder, as priority inheritance makes no sense for an
+	interrupts, only tasks. */
+	configASSERT( !( ( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) && ( pxQueue->u.xSemaphore.xMutexHolder != NULL ) ) );
+
+	/* RTOS ports that support interrupt nesting have the concept of a maximum
+	system call (or maximum API call) interrupt priority.  Interrupts that are
+	above the maximum system call priority are kept permanently enabled, even
+	when the RTOS kernel is in a critical section, but cannot make any calls to
+	FreeRTOS API functions.  If configASSERT() is defined in FreeRTOSConfig.h
+	then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
+	failure if a FreeRTOS API function is called from an interrupt that has been
+	assigned a priority above the configured maximum system call priority.
+	Only FreeRTOS functions that end in FromISR can be called from interrupts
+	that have been assigned a priority at or (logically) below the maximum
+	system call	interrupt priority.  FreeRTOS maintains a separate interrupt
+	safe API to ensure interrupt entry is as fast and as simple as possible.
+	More information (albeit Cortex-M specific) is provided on the following
+	link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */
+	portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+
+	uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+	{
+		const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;
+
+		/* When the queue is used to implement a semaphore no data is ever
+		moved through the queue but it is still valid to see if the queue 'has
+		space'. */
+		if( uxMessagesWaiting < pxQueue->uxLength )
+		{
+			const int8_t cTxLock = pxQueue->cTxLock;
+
+			traceQUEUE_SEND_FROM_ISR( pxQueue );
+
+			/* A task can only have an inherited priority if it is a mutex
+			holder - and if there is a mutex holder then the mutex cannot be
+			given from an ISR.  As this is the ISR version of the function it
+			can be assumed there is no mutex holder and no need to determine if
+			priority disinheritance is needed.  Simply increase the count of
+			messages (semaphores) available. */
+			pxQueue->uxMessagesWaiting = uxMessagesWaiting + ( UBaseType_t ) 1;
+
+			/* The event list is not altered if the queue is locked.  This will
+			be done when the queue is unlocked later. */
+			if( cTxLock == queueUNLOCKED )
+			{
+				#if ( configUSE_QUEUE_SETS == 1 )
+				{
+					if( pxQueue->pxQueueSetContainer != NULL )
+					{
+						if( prvNotifyQueueSetContainer( pxQueue ) != pdFALSE )
+						{
+							/* The semaphore is a member of a queue set, and
+							posting	to the queue set caused a higher priority
+							task to	unblock.  A context switch is required. */
+							if( pxHigherPriorityTaskWoken != NULL )
+							{
+								*pxHigherPriorityTaskWoken = pdTRUE;
+							}
+							else
+							{
+								mtCOVERAGE_TEST_MARKER();
+							}
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+					else
+					{
+						if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+						{
+							if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+							{
+								/* The task waiting has a higher priority so
+								record that a context switch is required. */
+								if( pxHigherPriorityTaskWoken != NULL )
+								{
+									*pxHigherPriorityTaskWoken = pdTRUE;
+								}
+								else
+								{
+									mtCOVERAGE_TEST_MARKER();
+								}
+							}
+							else
+							{
+								mtCOVERAGE_TEST_MARKER();
+							}
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+				}
+				#else /* configUSE_QUEUE_SETS */
+				{
+					if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+					{
+						if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+						{
+							/* The task waiting has a higher priority so record that a
+							context	switch is required. */
+							if( pxHigherPriorityTaskWoken != NULL )
+							{
+								*pxHigherPriorityTaskWoken = pdTRUE;
+							}
+							else
+							{
+								mtCOVERAGE_TEST_MARKER();
+							}
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				#endif /* configUSE_QUEUE_SETS */
+			}
+			else
+			{
+				/* Increment the lock count so the task that unlocks the queue
+				knows that data was posted while it was locked. */
+				pxQueue->cTxLock = ( int8_t ) ( cTxLock + 1 );
+			}
+
+			xReturn = pdPASS;
+		}
+		else
+		{
+			traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue );
+			xReturn = errQUEUE_FULL;
+		}
+	}
+	portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueReceive( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait )
+{
+BaseType_t xEntryTimeSet = pdFALSE;
+TimeOut_t xTimeOut;
+Queue_t * const pxQueue = xQueue;
+
+	/* Check the pointer is not NULL. */
+	configASSERT( ( pxQueue ) );
+
+	/* The buffer into which data is received can only be NULL if the data size
+	is zero (so no data is copied into the buffer. */
+	configASSERT( !( ( ( pvBuffer ) == NULL ) && ( ( pxQueue )->uxItemSize != ( UBaseType_t ) 0U ) ) );
+
+	/* Cannot block if the scheduler is suspended. */
+	#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
+	{
+		configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
+	}
+	#endif
+
+
+	/*lint -save -e904  This function relaxes the coding standard somewhat to
+	allow return statements within the function itself.  This is done in the
+	interest of execution time efficiency. */
+	for( ;; )
+	{
+		taskENTER_CRITICAL();
+		{
+			const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;
+
+			/* Is there data in the queue now?  To be running the calling task
+			must be the highest priority task wanting to access the queue. */
+			if( uxMessagesWaiting > ( UBaseType_t ) 0 )
+			{
+				/* Data available, remove one item. */
+				prvCopyDataFromQueue( pxQueue, pvBuffer );
+				traceQUEUE_RECEIVE( pxQueue );
+				pxQueue->uxMessagesWaiting = uxMessagesWaiting - ( UBaseType_t ) 1;
+
+				/* There is now space in the queue, were any tasks waiting to
+				post to the queue?  If so, unblock the highest priority waiting
+				task. */
+				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
+				{
+					if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
+					{
+						queueYIELD_IF_USING_PREEMPTION();
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+
+				taskEXIT_CRITICAL();
+				return pdPASS;
+			}
+			else
+			{
+				if( xTicksToWait == ( TickType_t ) 0 )
+				{
+					/* The queue was empty and no block time is specified (or
+					the block time has expired) so leave now. */
+					taskEXIT_CRITICAL();
+					traceQUEUE_RECEIVE_FAILED( pxQueue );
+					return errQUEUE_EMPTY;
+				}
+				else if( xEntryTimeSet == pdFALSE )
+				{
+					/* The queue was empty and a block time was specified so
+					configure the timeout structure. */
+					vTaskInternalSetTimeOutState( &xTimeOut );
+					xEntryTimeSet = pdTRUE;
+				}
+				else
+				{
+					/* Entry time was already set. */
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+		}
+		taskEXIT_CRITICAL();
+
+		/* Interrupts and other tasks can send to and receive from the queue
+		now the critical section has been exited. */
+
+		vTaskSuspendAll();
+		prvLockQueue( pxQueue );
+
+		/* Update the timeout state to see if it has expired yet. */
+		if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
+		{
+			/* The timeout has not expired.  If the queue is still empty place
+			the task on the list of tasks waiting to receive from the queue. */
+			if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
+			{
+				traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue );
+				vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait );
+				prvUnlockQueue( pxQueue );
+				if( xTaskResumeAll() == pdFALSE )
+				{
+					portYIELD_WITHIN_API();
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				/* The queue contains data again.  Loop back to try and read the
+				data. */
+				prvUnlockQueue( pxQueue );
+				( void ) xTaskResumeAll();
+			}
+		}
+		else
+		{
+			/* Timed out.  If there is no data in the queue exit, otherwise loop
+			back and attempt to read the data. */
+			prvUnlockQueue( pxQueue );
+			( void ) xTaskResumeAll();
+
+			if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
+			{
+				traceQUEUE_RECEIVE_FAILED( pxQueue );
+				return errQUEUE_EMPTY;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+	} /*lint -restore */
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueSemaphoreTake( QueueHandle_t xQueue, TickType_t xTicksToWait )
+{
+BaseType_t xEntryTimeSet = pdFALSE;
+TimeOut_t xTimeOut;
+Queue_t * const pxQueue = xQueue;
+
+#if( configUSE_MUTEXES == 1 )
+	BaseType_t xInheritanceOccurred = pdFALSE;
+#endif
+
+	/* Check the queue pointer is not NULL. */
+	configASSERT( ( pxQueue ) );
+
+	/* Check this really is a semaphore, in which case the item size will be
+	0. */
+	configASSERT( pxQueue->uxItemSize == 0 );
+
+	/* Cannot block if the scheduler is suspended. */
+	#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
+	{
+		configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
+	}
+	#endif
+
+
+	/*lint -save -e904 This function relaxes the coding standard somewhat to allow return
+	statements within the function itself.  This is done in the interest
+	of execution time efficiency. */
+	for( ;; )
+	{
+		taskENTER_CRITICAL();
+		{
+			/* Semaphores are queues with an item size of 0, and where the
+			number of messages in the queue is the semaphore's count value. */
+			const UBaseType_t uxSemaphoreCount = pxQueue->uxMessagesWaiting;
+
+			/* Is there data in the queue now?  To be running the calling task
+			must be the highest priority task wanting to access the queue. */
+			if( uxSemaphoreCount > ( UBaseType_t ) 0 )
+			{
+				traceQUEUE_RECEIVE( pxQueue );
+
+				/* Semaphores are queues with a data size of zero and where the
+				messages waiting is the semaphore's count.  Reduce the count. */
+				pxQueue->uxMessagesWaiting = uxSemaphoreCount - ( UBaseType_t ) 1;
+
+				#if ( configUSE_MUTEXES == 1 )
+				{
+					if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )
+					{
+						/* Record the information required to implement
+						priority inheritance should it become necessary. */
+						pxQueue->u.xSemaphore.xMutexHolder = pvTaskIncrementMutexHeldCount();
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				#endif /* configUSE_MUTEXES */
+
+				/* Check to see if other tasks are blocked waiting to give the
+				semaphore, and if so, unblock the highest priority such task. */
+				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
+				{
+					if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
+					{
+						queueYIELD_IF_USING_PREEMPTION();
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+
+				taskEXIT_CRITICAL();
+				return pdPASS;
+			}
+			else
+			{
+				if( xTicksToWait == ( TickType_t ) 0 )
+				{
+					/* For inheritance to have occurred there must have been an
+					initial timeout, and an adjusted timeout cannot become 0, as
+					if it were 0 the function would have exited. */
+					#if( configUSE_MUTEXES == 1 )
+					{
+						configASSERT( xInheritanceOccurred == pdFALSE );
+					}
+					#endif /* configUSE_MUTEXES */
+
+					/* The semaphore count was 0 and no block time is specified
+					(or the block time has expired) so exit now. */
+					taskEXIT_CRITICAL();
+					traceQUEUE_RECEIVE_FAILED( pxQueue );
+					return errQUEUE_EMPTY;
+				}
+				else if( xEntryTimeSet == pdFALSE )
+				{
+					/* The semaphore count was 0 and a block time was specified
+					so configure the timeout structure ready to block. */
+					vTaskInternalSetTimeOutState( &xTimeOut );
+					xEntryTimeSet = pdTRUE;
+				}
+				else
+				{
+					/* Entry time was already set. */
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+		}
+		taskEXIT_CRITICAL();
+
+		/* Interrupts and other tasks can give to and take from the semaphore
+		now the critical section has been exited. */
+
+		vTaskSuspendAll();
+		prvLockQueue( pxQueue );
+
+		/* Update the timeout state to see if it has expired yet. */
+		if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
+		{
+			/* A block time is specified and not expired.  If the semaphore
+			count is 0 then enter the Blocked state to wait for a semaphore to
+			become available.  As semaphores are implemented with queues the
+			queue being empty is equivalent to the semaphore count being 0. */
+			if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
+			{
+				traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue );
+
+				#if ( configUSE_MUTEXES == 1 )
+				{
+					if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )
+					{
+						taskENTER_CRITICAL();
+						{
+							xInheritanceOccurred = xTaskPriorityInherit( pxQueue->u.xSemaphore.xMutexHolder );
+						}
+						taskEXIT_CRITICAL();
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				#endif
+
+				vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait );
+				prvUnlockQueue( pxQueue );
+				if( xTaskResumeAll() == pdFALSE )
+				{
+					portYIELD_WITHIN_API();
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				/* There was no timeout and the semaphore count was not 0, so
+				attempt to take the semaphore again. */
+				prvUnlockQueue( pxQueue );
+				( void ) xTaskResumeAll();
+			}
+		}
+		else
+		{
+			/* Timed out. */
+			prvUnlockQueue( pxQueue );
+			( void ) xTaskResumeAll();
+
+			/* If the semaphore count is 0 exit now as the timeout has
+			expired.  Otherwise return to attempt to take the semaphore that is
+			known to be available.  As semaphores are implemented by queues the
+			queue being empty is equivalent to the semaphore count being 0. */
+			if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
+			{
+				#if ( configUSE_MUTEXES == 1 )
+				{
+					/* xInheritanceOccurred could only have be set if
+					pxQueue->uxQueueType == queueQUEUE_IS_MUTEX so no need to
+					test the mutex type again to check it is actually a mutex. */
+					if( xInheritanceOccurred != pdFALSE )
+					{
+						taskENTER_CRITICAL();
+						{
+							UBaseType_t uxHighestWaitingPriority;
+
+							/* This task blocking on the mutex caused another
+							task to inherit this task's priority.  Now this task
+							has timed out the priority should be disinherited
+							again, but only as low as the next highest priority
+							task that is waiting for the same mutex. */
+							uxHighestWaitingPriority = prvGetDisinheritPriorityAfterTimeout( pxQueue );
+							vTaskPriorityDisinheritAfterTimeout( pxQueue->u.xSemaphore.xMutexHolder, uxHighestWaitingPriority );
+						}
+						taskEXIT_CRITICAL();
+					}
+				}
+				#endif /* configUSE_MUTEXES */
+
+				traceQUEUE_RECEIVE_FAILED( pxQueue );
+				return errQUEUE_EMPTY;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+	} /*lint -restore */
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueuePeek( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait )
+{
+BaseType_t xEntryTimeSet = pdFALSE;
+TimeOut_t xTimeOut;
+int8_t *pcOriginalReadPosition;
+Queue_t * const pxQueue = xQueue;
+
+	/* Check the pointer is not NULL. */
+	configASSERT( ( pxQueue ) );
+
+	/* The buffer into which data is received can only be NULL if the data size
+	is zero (so no data is copied into the buffer. */
+	configASSERT( !( ( ( pvBuffer ) == NULL ) && ( ( pxQueue )->uxItemSize != ( UBaseType_t ) 0U ) ) );
+
+	/* Cannot block if the scheduler is suspended. */
+	#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
+	{
+		configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
+	}
+	#endif
+
+
+	/*lint -save -e904  This function relaxes the coding standard somewhat to
+	allow return statements within the function itself.  This is done in the
+	interest of execution time efficiency. */
+	for( ;; )
+	{
+		taskENTER_CRITICAL();
+		{
+			const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;
+
+			/* Is there data in the queue now?  To be running the calling task
+			must be the highest priority task wanting to access the queue. */
+			if( uxMessagesWaiting > ( UBaseType_t ) 0 )
+			{
+				/* Remember the read position so it can be reset after the data
+				is read from the queue as this function is only peeking the
+				data, not removing it. */
+				pcOriginalReadPosition = pxQueue->u.xQueue.pcReadFrom;
+
+				prvCopyDataFromQueue( pxQueue, pvBuffer );
+				traceQUEUE_PEEK( pxQueue );
+
+				/* The data is not being removed, so reset the read pointer. */
+				pxQueue->u.xQueue.pcReadFrom = pcOriginalReadPosition;
+
+				/* The data is being left in the queue, so see if there are
+				any other tasks waiting for the data. */
+				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+				{
+					if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+					{
+						/* The task waiting has a higher priority than this task. */
+						queueYIELD_IF_USING_PREEMPTION();
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+
+				taskEXIT_CRITICAL();
+				return pdPASS;
+			}
+			else
+			{
+				if( xTicksToWait == ( TickType_t ) 0 )
+				{
+					/* The queue was empty and no block time is specified (or
+					the block time has expired) so leave now. */
+					taskEXIT_CRITICAL();
+					traceQUEUE_PEEK_FAILED( pxQueue );
+					return errQUEUE_EMPTY;
+				}
+				else if( xEntryTimeSet == pdFALSE )
+				{
+					/* The queue was empty and a block time was specified so
+					configure the timeout structure ready to enter the blocked
+					state. */
+					vTaskInternalSetTimeOutState( &xTimeOut );
+					xEntryTimeSet = pdTRUE;
+				}
+				else
+				{
+					/* Entry time was already set. */
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+		}
+		taskEXIT_CRITICAL();
+
+		/* Interrupts and other tasks can send to and receive from the queue
+		now the critical section has been exited. */
+
+		vTaskSuspendAll();
+		prvLockQueue( pxQueue );
+
+		/* Update the timeout state to see if it has expired yet. */
+		if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
+		{
+			/* Timeout has not expired yet, check to see if there is data in the
+			queue now, and if not enter the Blocked state to wait for data. */
+			if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
+			{
+				traceBLOCKING_ON_QUEUE_PEEK( pxQueue );
+				vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait );
+				prvUnlockQueue( pxQueue );
+				if( xTaskResumeAll() == pdFALSE )
+				{
+					portYIELD_WITHIN_API();
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				/* There is data in the queue now, so don't enter the blocked
+				state, instead return to try and obtain the data. */
+				prvUnlockQueue( pxQueue );
+				( void ) xTaskResumeAll();
+			}
+		}
+		else
+		{
+			/* The timeout has expired.  If there is still no data in the queue
+			exit, otherwise go back and try to read the data again. */
+			prvUnlockQueue( pxQueue );
+			( void ) xTaskResumeAll();
+
+			if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
+			{
+				traceQUEUE_PEEK_FAILED( pxQueue );
+				return errQUEUE_EMPTY;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+	} /*lint -restore */
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueReceiveFromISR( QueueHandle_t xQueue, void * const pvBuffer, BaseType_t * const pxHigherPriorityTaskWoken )
+{
+BaseType_t xReturn;
+UBaseType_t uxSavedInterruptStatus;
+Queue_t * const pxQueue = xQueue;
+
+	configASSERT( pxQueue );
+	configASSERT( !( ( pvBuffer == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
+
+	/* RTOS ports that support interrupt nesting have the concept of a maximum
+	system call (or maximum API call) interrupt priority.  Interrupts that are
+	above the maximum system call priority are kept permanently enabled, even
+	when the RTOS kernel is in a critical section, but cannot make any calls to
+	FreeRTOS API functions.  If configASSERT() is defined in FreeRTOSConfig.h
+	then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
+	failure if a FreeRTOS API function is called from an interrupt that has been
+	assigned a priority above the configured maximum system call priority.
+	Only FreeRTOS functions that end in FromISR can be called from interrupts
+	that have been assigned a priority at or (logically) below the maximum
+	system call	interrupt priority.  FreeRTOS maintains a separate interrupt
+	safe API to ensure interrupt entry is as fast and as simple as possible.
+	More information (albeit Cortex-M specific) is provided on the following
+	link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */
+	portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+
+	uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+	{
+		const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;
+
+		/* Cannot block in an ISR, so check there is data available. */
+		if( uxMessagesWaiting > ( UBaseType_t ) 0 )
+		{
+			const int8_t cRxLock = pxQueue->cRxLock;
+
+			traceQUEUE_RECEIVE_FROM_ISR( pxQueue );
+
+			prvCopyDataFromQueue( pxQueue, pvBuffer );
+			pxQueue->uxMessagesWaiting = uxMessagesWaiting - ( UBaseType_t ) 1;
+
+			/* If the queue is locked the event list will not be modified.
+			Instead update the lock count so the task that unlocks the queue
+			will know that an ISR has removed data while the queue was
+			locked. */
+			if( cRxLock == queueUNLOCKED )
+			{
+				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
+				{
+					if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
+					{
+						/* The task waiting has a higher priority than us so
+						force a context switch. */
+						if( pxHigherPriorityTaskWoken != NULL )
+						{
+							*pxHigherPriorityTaskWoken = pdTRUE;
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				/* Increment the lock count so the task that unlocks the queue
+				knows that data was removed while it was locked. */
+				pxQueue->cRxLock = ( int8_t ) ( cRxLock + 1 );
+			}
+
+			xReturn = pdPASS;
+		}
+		else
+		{
+			xReturn = pdFAIL;
+			traceQUEUE_RECEIVE_FROM_ISR_FAILED( pxQueue );
+		}
+	}
+	portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueuePeekFromISR( QueueHandle_t xQueue,  void * const pvBuffer )
+{
+BaseType_t xReturn;
+UBaseType_t uxSavedInterruptStatus;
+int8_t *pcOriginalReadPosition;
+Queue_t * const pxQueue = xQueue;
+
+	configASSERT( pxQueue );
+	configASSERT( !( ( pvBuffer == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
+	configASSERT( pxQueue->uxItemSize != 0 ); /* Can't peek a semaphore. */
+
+	/* RTOS ports that support interrupt nesting have the concept of a maximum
+	system call (or maximum API call) interrupt priority.  Interrupts that are
+	above the maximum system call priority are kept permanently enabled, even
+	when the RTOS kernel is in a critical section, but cannot make any calls to
+	FreeRTOS API functions.  If configASSERT() is defined in FreeRTOSConfig.h
+	then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
+	failure if a FreeRTOS API function is called from an interrupt that has been
+	assigned a priority above the configured maximum system call priority.
+	Only FreeRTOS functions that end in FromISR can be called from interrupts
+	that have been assigned a priority at or (logically) below the maximum
+	system call	interrupt priority.  FreeRTOS maintains a separate interrupt
+	safe API to ensure interrupt entry is as fast and as simple as possible.
+	More information (albeit Cortex-M specific) is provided on the following
+	link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */
+	portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+
+	uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+	{
+		/* Cannot block in an ISR, so check there is data available. */
+		if( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 )
+		{
+			traceQUEUE_PEEK_FROM_ISR( pxQueue );
+
+			/* Remember the read position so it can be reset as nothing is
+			actually being removed from the queue. */
+			pcOriginalReadPosition = pxQueue->u.xQueue.pcReadFrom;
+			prvCopyDataFromQueue( pxQueue, pvBuffer );
+			pxQueue->u.xQueue.pcReadFrom = pcOriginalReadPosition;
+
+			xReturn = pdPASS;
+		}
+		else
+		{
+			xReturn = pdFAIL;
+			traceQUEUE_PEEK_FROM_ISR_FAILED( pxQueue );
+		}
+	}
+	portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+UBaseType_t uxQueueMessagesWaiting( const QueueHandle_t xQueue )
+{
+UBaseType_t uxReturn;
+
+	configASSERT( xQueue );
+
+	taskENTER_CRITICAL();
+	{
+		uxReturn = ( ( Queue_t * ) xQueue )->uxMessagesWaiting;
+	}
+	taskEXIT_CRITICAL();
+
+	return uxReturn;
+} /*lint !e818 Pointer cannot be declared const as xQueue is a typedef not pointer. */
+/*-----------------------------------------------------------*/
+
+UBaseType_t uxQueueSpacesAvailable( const QueueHandle_t xQueue )
+{
+UBaseType_t uxReturn;
+Queue_t * const pxQueue = xQueue;
+
+	configASSERT( pxQueue );
+
+	taskENTER_CRITICAL();
+	{
+		uxReturn = pxQueue->uxLength - pxQueue->uxMessagesWaiting;
+	}
+	taskEXIT_CRITICAL();
+
+	return uxReturn;
+} /*lint !e818 Pointer cannot be declared const as xQueue is a typedef not pointer. */
+/*-----------------------------------------------------------*/
+
+UBaseType_t uxQueueMessagesWaitingFromISR( const QueueHandle_t xQueue )
+{
+UBaseType_t uxReturn;
+Queue_t * const pxQueue = xQueue;
+
+	configASSERT( pxQueue );
+	uxReturn = pxQueue->uxMessagesWaiting;
+
+	return uxReturn;
+} /*lint !e818 Pointer cannot be declared const as xQueue is a typedef not pointer. */
+/*-----------------------------------------------------------*/
+
+void vQueueDelete( QueueHandle_t xQueue )
+{
+Queue_t * const pxQueue = xQueue;
+
+	configASSERT( pxQueue );
+	traceQUEUE_DELETE( pxQueue );
+
+	#if ( configQUEUE_REGISTRY_SIZE > 0 )
+	{
+		vQueueUnregisterQueue( pxQueue );
+	}
+	#endif
+
+	#if( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 0 ) )
+	{
+		/* The queue can only have been allocated dynamically - free it
+		again. */
+		vPortFree( pxQueue );
+	}
+	#elif( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
+	{
+		/* The queue could have been allocated statically or dynamically, so
+		check before attempting to free the memory. */
+		if( pxQueue->ucStaticallyAllocated == ( uint8_t ) pdFALSE )
+		{
+			vPortFree( pxQueue );
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	#else
+	{
+		/* The queue must have been statically allocated, so is not going to be
+		deleted.  Avoid compiler warnings about the unused parameter. */
+		( void ) pxQueue;
+	}
+	#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+}
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	UBaseType_t uxQueueGetQueueNumber( QueueHandle_t xQueue )
+	{
+		return ( ( Queue_t * ) xQueue )->uxQueueNumber;
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	void vQueueSetQueueNumber( QueueHandle_t xQueue, UBaseType_t uxQueueNumber )
+	{
+		( ( Queue_t * ) xQueue )->uxQueueNumber = uxQueueNumber;
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	uint8_t ucQueueGetQueueType( QueueHandle_t xQueue )
+	{
+		return ( ( Queue_t * ) xQueue )->ucQueueType;
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+#if( configUSE_MUTEXES == 1 )
+
+	static UBaseType_t prvGetDisinheritPriorityAfterTimeout( const Queue_t * const pxQueue )
+	{
+	UBaseType_t uxHighestPriorityOfWaitingTasks;
+
+		/* If a task waiting for a mutex causes the mutex holder to inherit a
+		priority, but the waiting task times out, then the holder should
+		disinherit the priority - but only down to the highest priority of any
+		other tasks that are waiting for the same mutex.  For this purpose,
+		return the priority of the highest priority task that is waiting for the
+		mutex. */
+		if( listCURRENT_LIST_LENGTH( &( pxQueue->xTasksWaitingToReceive ) ) > 0U )
+		{
+			uxHighestPriorityOfWaitingTasks = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) listGET_ITEM_VALUE_OF_HEAD_ENTRY( &( pxQueue->xTasksWaitingToReceive ) );
+		}
+		else
+		{
+			uxHighestPriorityOfWaitingTasks = tskIDLE_PRIORITY;
+		}
+
+		return uxHighestPriorityOfWaitingTasks;
+	}
+
+#endif /* configUSE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+static BaseType_t prvCopyDataToQueue( Queue_t * const pxQueue, const void *pvItemToQueue, const BaseType_t xPosition )
+{
+BaseType_t xReturn = pdFALSE;
+UBaseType_t uxMessagesWaiting;
+
+	/* This function is called from a critical section. */
+
+	uxMessagesWaiting = pxQueue->uxMessagesWaiting;
+
+	if( pxQueue->uxItemSize == ( UBaseType_t ) 0 )
+	{
+		#if ( configUSE_MUTEXES == 1 )
+		{
+			if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )
+			{
+				/* The mutex is no longer being held. */
+				xReturn = xTaskPriorityDisinherit( pxQueue->u.xSemaphore.xMutexHolder );
+				pxQueue->u.xSemaphore.xMutexHolder = NULL;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		#endif /* configUSE_MUTEXES */
+	}
+	else if( xPosition == queueSEND_TO_BACK )
+	{
+		( void ) memcpy( ( void * ) pxQueue->pcWriteTo, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports, plus previous logic ensures a null pointer can only be passed to memcpy() if the copy size is 0.  Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */
+		pxQueue->pcWriteTo += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */
+		if( pxQueue->pcWriteTo >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */
+		{
+			pxQueue->pcWriteTo = pxQueue->pcHead;
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	else
+	{
+		( void ) memcpy( ( void * ) pxQueue->u.xQueue.pcReadFrom, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e9087 !e418 MISRA exception as the casts are only redundant for some ports.  Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes.  Assert checks null pointer only used when length is 0. */
+		pxQueue->u.xQueue.pcReadFrom -= pxQueue->uxItemSize;
+		if( pxQueue->u.xQueue.pcReadFrom < pxQueue->pcHead ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */
+		{
+			pxQueue->u.xQueue.pcReadFrom = ( pxQueue->u.xQueue.pcTail - pxQueue->uxItemSize );
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		if( xPosition == queueOVERWRITE )
+		{
+			if( uxMessagesWaiting > ( UBaseType_t ) 0 )
+			{
+				/* An item is not being added but overwritten, so subtract
+				one from the recorded number of items in the queue so when
+				one is added again below the number of recorded items remains
+				correct. */
+				--uxMessagesWaiting;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+
+	pxQueue->uxMessagesWaiting = uxMessagesWaiting + ( UBaseType_t ) 1;
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+static void prvCopyDataFromQueue( Queue_t * const pxQueue, void * const pvBuffer )
+{
+	if( pxQueue->uxItemSize != ( UBaseType_t ) 0 )
+	{
+		pxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */
+		if( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as use of the relational operator is the cleanest solutions. */
+		{
+			pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead;
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+		( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.xQueue.pcReadFrom, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports.  Also previous logic ensures a null pointer can only be passed to memcpy() when the count is 0.  Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvUnlockQueue( Queue_t * const pxQueue )
+{
+	/* THIS FUNCTION MUST BE CALLED WITH THE SCHEDULER SUSPENDED. */
+
+	/* The lock counts contains the number of extra data items placed or
+	removed from the queue while the queue was locked.  When a queue is
+	locked items can be added or removed, but the event lists cannot be
+	updated. */
+	taskENTER_CRITICAL();
+	{
+		int8_t cTxLock = pxQueue->cTxLock;
+
+		/* See if data was added to the queue while it was locked. */
+		while( cTxLock > queueLOCKED_UNMODIFIED )
+		{
+			/* Data was posted while the queue was locked.  Are any tasks
+			blocked waiting for data to become available? */
+			#if ( configUSE_QUEUE_SETS == 1 )
+			{
+				if( pxQueue->pxQueueSetContainer != NULL )
+				{
+					if( prvNotifyQueueSetContainer( pxQueue ) != pdFALSE )
+					{
+						/* The queue is a member of a queue set, and posting to
+						the queue set caused a higher priority task to unblock.
+						A context switch is required. */
+						vTaskMissedYield();
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					/* Tasks that are removed from the event list will get
+					added to the pending ready list as the scheduler is still
+					suspended. */
+					if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+					{
+						if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+						{
+							/* The task waiting has a higher priority so record that a
+							context	switch is required. */
+							vTaskMissedYield();
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+					else
+					{
+						break;
+					}
+				}
+			}
+			#else /* configUSE_QUEUE_SETS */
+			{
+				/* Tasks that are removed from the event list will get added to
+				the pending ready list as the scheduler is still suspended. */
+				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+				{
+					if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+					{
+						/* The task waiting has a higher priority so record that
+						a context switch is required. */
+						vTaskMissedYield();
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					break;
+				}
+			}
+			#endif /* configUSE_QUEUE_SETS */
+
+			--cTxLock;
+		}
+
+		pxQueue->cTxLock = queueUNLOCKED;
+	}
+	taskEXIT_CRITICAL();
+
+	/* Do the same for the Rx lock. */
+	taskENTER_CRITICAL();
+	{
+		int8_t cRxLock = pxQueue->cRxLock;
+
+		while( cRxLock > queueLOCKED_UNMODIFIED )
+		{
+			if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
+			{
+				if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
+				{
+					vTaskMissedYield();
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+
+				--cRxLock;
+			}
+			else
+			{
+				break;
+			}
+		}
+
+		pxQueue->cRxLock = queueUNLOCKED;
+	}
+	taskEXIT_CRITICAL();
+}
+/*-----------------------------------------------------------*/
+
+static BaseType_t prvIsQueueEmpty( const Queue_t *pxQueue )
+{
+BaseType_t xReturn;
+
+	taskENTER_CRITICAL();
+	{
+		if( pxQueue->uxMessagesWaiting == ( UBaseType_t )  0 )
+		{
+			xReturn = pdTRUE;
+		}
+		else
+		{
+			xReturn = pdFALSE;
+		}
+	}
+	taskEXIT_CRITICAL();
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueIsQueueEmptyFromISR( const QueueHandle_t xQueue )
+{
+BaseType_t xReturn;
+Queue_t * const pxQueue = xQueue;
+
+	configASSERT( pxQueue );
+	if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0 )
+	{
+		xReturn = pdTRUE;
+	}
+	else
+	{
+		xReturn = pdFALSE;
+	}
+
+	return xReturn;
+} /*lint !e818 xQueue could not be pointer to const because it is a typedef. */
+/*-----------------------------------------------------------*/
+
+static BaseType_t prvIsQueueFull( const Queue_t *pxQueue )
+{
+BaseType_t xReturn;
+
+	taskENTER_CRITICAL();
+	{
+		if( pxQueue->uxMessagesWaiting == pxQueue->uxLength )
+		{
+			xReturn = pdTRUE;
+		}
+		else
+		{
+			xReturn = pdFALSE;
+		}
+	}
+	taskEXIT_CRITICAL();
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue )
+{
+BaseType_t xReturn;
+Queue_t * const pxQueue = xQueue;
+
+	configASSERT( pxQueue );
+	if( pxQueue->uxMessagesWaiting == pxQueue->uxLength )
+	{
+		xReturn = pdTRUE;
+	}
+	else
+	{
+		xReturn = pdFALSE;
+	}
+
+	return xReturn;
+} /*lint !e818 xQueue could not be pointer to const because it is a typedef. */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_CO_ROUTINES == 1 )
+
+	BaseType_t xQueueCRSend( QueueHandle_t xQueue, const void *pvItemToQueue, TickType_t xTicksToWait )
+	{
+	BaseType_t xReturn;
+	Queue_t * const pxQueue = xQueue;
+
+		/* If the queue is already full we may have to block.  A critical section
+		is required to prevent an interrupt removing something from the queue
+		between the check to see if the queue is full and blocking on the queue. */
+		portDISABLE_INTERRUPTS();
+		{
+			if( prvIsQueueFull( pxQueue ) != pdFALSE )
+			{
+				/* The queue is full - do we want to block or just leave without
+				posting? */
+				if( xTicksToWait > ( TickType_t ) 0 )
+				{
+					/* As this is called from a coroutine we cannot block directly, but
+					return indicating that we need to block. */
+					vCoRoutineAddToDelayedList( xTicksToWait, &( pxQueue->xTasksWaitingToSend ) );
+					portENABLE_INTERRUPTS();
+					return errQUEUE_BLOCKED;
+				}
+				else
+				{
+					portENABLE_INTERRUPTS();
+					return errQUEUE_FULL;
+				}
+			}
+		}
+		portENABLE_INTERRUPTS();
+
+		portDISABLE_INTERRUPTS();
+		{
+			if( pxQueue->uxMessagesWaiting < pxQueue->uxLength )
+			{
+				/* There is room in the queue, copy the data into the queue. */
+				prvCopyDataToQueue( pxQueue, pvItemToQueue, queueSEND_TO_BACK );
+				xReturn = pdPASS;
+
+				/* Were any co-routines waiting for data to become available? */
+				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+				{
+					/* In this instance the co-routine could be placed directly
+					into the ready list as we are within a critical section.
+					Instead the same pending ready list mechanism is used as if
+					the event were caused from within an interrupt. */
+					if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+					{
+						/* The co-routine waiting has a higher priority so record
+						that a yield might be appropriate. */
+						xReturn = errQUEUE_YIELD;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				xReturn = errQUEUE_FULL;
+			}
+		}
+		portENABLE_INTERRUPTS();
+
+		return xReturn;
+	}
+
+#endif /* configUSE_CO_ROUTINES */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_CO_ROUTINES == 1 )
+
+	BaseType_t xQueueCRReceive( QueueHandle_t xQueue, void *pvBuffer, TickType_t xTicksToWait )
+	{
+	BaseType_t xReturn;
+	Queue_t * const pxQueue = xQueue;
+
+		/* If the queue is already empty we may have to block.  A critical section
+		is required to prevent an interrupt adding something to the queue
+		between the check to see if the queue is empty and blocking on the queue. */
+		portDISABLE_INTERRUPTS();
+		{
+			if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0 )
+			{
+				/* There are no messages in the queue, do we want to block or just
+				leave with nothing? */
+				if( xTicksToWait > ( TickType_t ) 0 )
+				{
+					/* As this is a co-routine we cannot block directly, but return
+					indicating that we need to block. */
+					vCoRoutineAddToDelayedList( xTicksToWait, &( pxQueue->xTasksWaitingToReceive ) );
+					portENABLE_INTERRUPTS();
+					return errQUEUE_BLOCKED;
+				}
+				else
+				{
+					portENABLE_INTERRUPTS();
+					return errQUEUE_FULL;
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		portENABLE_INTERRUPTS();
+
+		portDISABLE_INTERRUPTS();
+		{
+			if( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 )
+			{
+				/* Data is available from the queue. */
+				pxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize;
+				if( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail )
+				{
+					pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+				--( pxQueue->uxMessagesWaiting );
+				( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.xQueue.pcReadFrom, ( unsigned ) pxQueue->uxItemSize );
+
+				xReturn = pdPASS;
+
+				/* Were any co-routines waiting for space to become available? */
+				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
+				{
+					/* In this instance the co-routine could be placed directly
+					into the ready list as we are within a critical section.
+					Instead the same pending ready list mechanism is used as if
+					the event were caused from within an interrupt. */
+					if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
+					{
+						xReturn = errQUEUE_YIELD;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				xReturn = pdFAIL;
+			}
+		}
+		portENABLE_INTERRUPTS();
+
+		return xReturn;
+	}
+
+#endif /* configUSE_CO_ROUTINES */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_CO_ROUTINES == 1 )
+
+	BaseType_t xQueueCRSendFromISR( QueueHandle_t xQueue, const void *pvItemToQueue, BaseType_t xCoRoutinePreviouslyWoken )
+	{
+	Queue_t * const pxQueue = xQueue;
+
+		/* Cannot block within an ISR so if there is no space on the queue then
+		exit without doing anything. */
+		if( pxQueue->uxMessagesWaiting < pxQueue->uxLength )
+		{
+			prvCopyDataToQueue( pxQueue, pvItemToQueue, queueSEND_TO_BACK );
+
+			/* We only want to wake one co-routine per ISR, so check that a
+			co-routine has not already been woken. */
+			if( xCoRoutinePreviouslyWoken == pdFALSE )
+			{
+				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+				{
+					if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+					{
+						return pdTRUE;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		return xCoRoutinePreviouslyWoken;
+	}
+
+#endif /* configUSE_CO_ROUTINES */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_CO_ROUTINES == 1 )
+
+	BaseType_t xQueueCRReceiveFromISR( QueueHandle_t xQueue, void *pvBuffer, BaseType_t *pxCoRoutineWoken )
+	{
+	BaseType_t xReturn;
+	Queue_t * const pxQueue = xQueue;
+
+		/* We cannot block from an ISR, so check there is data available. If
+		not then just leave without doing anything. */
+		if( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 )
+		{
+			/* Copy the data from the queue. */
+			pxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize;
+			if( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail )
+			{
+				pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+			--( pxQueue->uxMessagesWaiting );
+			( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.xQueue.pcReadFrom, ( unsigned ) pxQueue->uxItemSize );
+
+			if( ( *pxCoRoutineWoken ) == pdFALSE )
+			{
+				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
+				{
+					if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
+					{
+						*pxCoRoutineWoken = pdTRUE;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+
+			xReturn = pdPASS;
+		}
+		else
+		{
+			xReturn = pdFAIL;
+		}
+
+		return xReturn;
+	}
+
+#endif /* configUSE_CO_ROUTINES */
+/*-----------------------------------------------------------*/
+
+#if ( configQUEUE_REGISTRY_SIZE > 0 )
+
+	void vQueueAddToRegistry( QueueHandle_t xQueue, const char *pcQueueName ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+	{
+	UBaseType_t ux;
+
+		/* See if there is an empty space in the registry.  A NULL name denotes
+		a free slot. */
+		for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ )
+		{
+			if( xQueueRegistry[ ux ].pcQueueName == NULL )
+			{
+				/* Store the information on this queue. */
+				xQueueRegistry[ ux ].pcQueueName = pcQueueName;
+				xQueueRegistry[ ux ].xHandle = xQueue;
+
+				traceQUEUE_REGISTRY_ADD( xQueue, pcQueueName );
+				break;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+	}
+
+#endif /* configQUEUE_REGISTRY_SIZE */
+/*-----------------------------------------------------------*/
+
+#if ( configQUEUE_REGISTRY_SIZE > 0 )
+
+	const char *pcQueueGetName( QueueHandle_t xQueue ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+	{
+	UBaseType_t ux;
+	const char *pcReturn = NULL; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+
+		/* Note there is nothing here to protect against another task adding or
+		removing entries from the registry while it is being searched. */
+		for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ )
+		{
+			if( xQueueRegistry[ ux ].xHandle == xQueue )
+			{
+				pcReturn = xQueueRegistry[ ux ].pcQueueName;
+				break;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+
+		return pcReturn;
+	} /*lint !e818 xQueue cannot be a pointer to const because it is a typedef. */
+
+#endif /* configQUEUE_REGISTRY_SIZE */
+/*-----------------------------------------------------------*/
+
+#if ( configQUEUE_REGISTRY_SIZE > 0 )
+
+	void vQueueUnregisterQueue( QueueHandle_t xQueue )
+	{
+	UBaseType_t ux;
+
+		/* See if the handle of the queue being unregistered in actually in the
+		registry. */
+		for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ )
+		{
+			if( xQueueRegistry[ ux ].xHandle == xQueue )
+			{
+				/* Set the name to NULL to show that this slot if free again. */
+				xQueueRegistry[ ux ].pcQueueName = NULL;
+
+				/* Set the handle to NULL to ensure the same queue handle cannot
+				appear in the registry twice if it is added, removed, then
+				added again. */
+				xQueueRegistry[ ux ].xHandle = ( QueueHandle_t ) 0;
+				break;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+
+	} /*lint !e818 xQueue could not be pointer to const because it is a typedef. */
+
+#endif /* configQUEUE_REGISTRY_SIZE */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TIMERS == 1 )
+
+	void vQueueWaitForMessageRestricted( QueueHandle_t xQueue, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely )
+	{
+	Queue_t * const pxQueue = xQueue;
+
+		/* This function should not be called by application code hence the
+		'Restricted' in its name.  It is not part of the public API.  It is
+		designed for use by kernel code, and has special calling requirements.
+		It can result in vListInsert() being called on a list that can only
+		possibly ever have one item in it, so the list will be fast, but even
+		so it should be called with the scheduler locked and not from a critical
+		section. */
+
+		/* Only do anything if there are no messages in the queue.  This function
+		will not actually cause the task to block, just place it on a blocked
+		list.  It will not block until the scheduler is unlocked - at which
+		time a yield will be performed.  If an item is added to the queue while
+		the queue is locked, and the calling task blocks on the queue, then the
+		calling task will be immediately unblocked when the queue is unlocked. */
+		prvLockQueue( pxQueue );
+		if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0U )
+		{
+			/* There is nothing in the queue, block for the specified period. */
+			vTaskPlaceOnEventListRestricted( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait, xWaitIndefinitely );
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+		prvUnlockQueue( pxQueue );
+	}
+
+#endif /* configUSE_TIMERS */
+/*-----------------------------------------------------------*/
+
+#if( ( configUSE_QUEUE_SETS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+
+	QueueSetHandle_t xQueueCreateSet( const UBaseType_t uxEventQueueLength )
+	{
+	QueueSetHandle_t pxQueue;
+
+		pxQueue = xQueueGenericCreate( uxEventQueueLength, ( UBaseType_t ) sizeof( Queue_t * ), queueQUEUE_TYPE_SET );
+
+		return pxQueue;
+	}
+
+#endif /* configUSE_QUEUE_SETS */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_QUEUE_SETS == 1 )
+
+	BaseType_t xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet )
+	{
+	BaseType_t xReturn;
+
+		taskENTER_CRITICAL();
+		{
+			if( ( ( Queue_t * ) xQueueOrSemaphore )->pxQueueSetContainer != NULL )
+			{
+				/* Cannot add a queue/semaphore to more than one queue set. */
+				xReturn = pdFAIL;
+			}
+			else if( ( ( Queue_t * ) xQueueOrSemaphore )->uxMessagesWaiting != ( UBaseType_t ) 0 )
+			{
+				/* Cannot add a queue/semaphore to a queue set if there are already
+				items in the queue/semaphore. */
+				xReturn = pdFAIL;
+			}
+			else
+			{
+				( ( Queue_t * ) xQueueOrSemaphore )->pxQueueSetContainer = xQueueSet;
+				xReturn = pdPASS;
+			}
+		}
+		taskEXIT_CRITICAL();
+
+		return xReturn;
+	}
+
+#endif /* configUSE_QUEUE_SETS */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_QUEUE_SETS == 1 )
+
+	BaseType_t xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet )
+	{
+	BaseType_t xReturn;
+	Queue_t * const pxQueueOrSemaphore = ( Queue_t * ) xQueueOrSemaphore;
+
+		if( pxQueueOrSemaphore->pxQueueSetContainer != xQueueSet )
+		{
+			/* The queue was not a member of the set. */
+			xReturn = pdFAIL;
+		}
+		else if( pxQueueOrSemaphore->uxMessagesWaiting != ( UBaseType_t ) 0 )
+		{
+			/* It is dangerous to remove a queue from a set when the queue is
+			not empty because the queue set will still hold pending events for
+			the queue. */
+			xReturn = pdFAIL;
+		}
+		else
+		{
+			taskENTER_CRITICAL();
+			{
+				/* The queue is no longer contained in the set. */
+				pxQueueOrSemaphore->pxQueueSetContainer = NULL;
+			}
+			taskEXIT_CRITICAL();
+			xReturn = pdPASS;
+		}
+
+		return xReturn;
+	} /*lint !e818 xQueueSet could not be declared as pointing to const as it is a typedef. */
+
+#endif /* configUSE_QUEUE_SETS */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_QUEUE_SETS == 1 )
+
+	QueueSetMemberHandle_t xQueueSelectFromSet( QueueSetHandle_t xQueueSet, TickType_t const xTicksToWait )
+	{
+	QueueSetMemberHandle_t xReturn = NULL;
+
+		( void ) xQueueReceive( ( QueueHandle_t ) xQueueSet, &xReturn, xTicksToWait ); /*lint !e961 Casting from one typedef to another is not redundant. */
+		return xReturn;
+	}
+
+#endif /* configUSE_QUEUE_SETS */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_QUEUE_SETS == 1 )
+
+	QueueSetMemberHandle_t xQueueSelectFromSetFromISR( QueueSetHandle_t xQueueSet )
+	{
+	QueueSetMemberHandle_t xReturn = NULL;
+
+		( void ) xQueueReceiveFromISR( ( QueueHandle_t ) xQueueSet, &xReturn, NULL ); /*lint !e961 Casting from one typedef to another is not redundant. */
+		return xReturn;
+	}
+
+#endif /* configUSE_QUEUE_SETS */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_QUEUE_SETS == 1 )
+
+	static BaseType_t prvNotifyQueueSetContainer( const Queue_t * const pxQueue )
+	{
+	Queue_t *pxQueueSetContainer = pxQueue->pxQueueSetContainer;
+	BaseType_t xReturn = pdFALSE;
+
+		/* This function must be called form a critical section. */
+
+		configASSERT( pxQueueSetContainer );
+		configASSERT( pxQueueSetContainer->uxMessagesWaiting < pxQueueSetContainer->uxLength );
+
+		if( pxQueueSetContainer->uxMessagesWaiting < pxQueueSetContainer->uxLength )
+		{
+			const int8_t cTxLock = pxQueueSetContainer->cTxLock;
+
+			traceQUEUE_SEND( pxQueueSetContainer );
+
+			/* The data copied is the handle of the queue that contains data. */
+			xReturn = prvCopyDataToQueue( pxQueueSetContainer, &pxQueue, queueSEND_TO_BACK );
+
+			if( cTxLock == queueUNLOCKED )
+			{
+				if( listLIST_IS_EMPTY( &( pxQueueSetContainer->xTasksWaitingToReceive ) ) == pdFALSE )
+				{
+					if( xTaskRemoveFromEventList( &( pxQueueSetContainer->xTasksWaitingToReceive ) ) != pdFALSE )
+					{
+						/* The task waiting has a higher priority. */
+						xReturn = pdTRUE;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				pxQueueSetContainer->cTxLock = ( int8_t ) ( cTxLock + 1 );
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		return xReturn;
+	}
+
+#endif /* configUSE_QUEUE_SETS */
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c b/Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c
new file mode 100644
index 0000000..7ad5d54
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c
@@ -0,0 +1,1263 @@
+/*
+ * FreeRTOS Kernel V10.3.1
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Standard includes. */
+#include <stdint.h>
+#include <string.h>
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+all the API functions to use the MPU wrappers.  That should only be done when
+task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* FreeRTOS includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "stream_buffer.h"
+
+#if( configUSE_TASK_NOTIFICATIONS != 1 )
+	#error configUSE_TASK_NOTIFICATIONS must be set to 1 to build stream_buffer.c
+#endif
+
+/* Lint e961, e9021 and e750 are suppressed as a MISRA exception justified
+because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined
+for the header files above, but not in this file, in order to generate the
+correct privileged Vs unprivileged linkage and placement. */
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750 !e9021. */
+
+/* If the user has not provided application specific Rx notification macros,
+or #defined the notification macros away, them provide default implementations
+that uses task notifications. */
+/*lint -save -e9026 Function like macros allowed and needed here so they can be overidden. */
+#ifndef sbRECEIVE_COMPLETED
+	#define sbRECEIVE_COMPLETED( pxStreamBuffer )										\
+		vTaskSuspendAll();																\
+		{																				\
+			if( ( pxStreamBuffer )->xTaskWaitingToSend != NULL )						\
+			{																			\
+				( void ) xTaskNotify( ( pxStreamBuffer )->xTaskWaitingToSend,			\
+									  ( uint32_t ) 0,									\
+									  eNoAction );										\
+				( pxStreamBuffer )->xTaskWaitingToSend = NULL;							\
+			}																			\
+		}																				\
+		( void ) xTaskResumeAll();
+#endif /* sbRECEIVE_COMPLETED */
+
+#ifndef sbRECEIVE_COMPLETED_FROM_ISR
+	#define sbRECEIVE_COMPLETED_FROM_ISR( pxStreamBuffer,								\
+										  pxHigherPriorityTaskWoken )					\
+	{																					\
+	UBaseType_t uxSavedInterruptStatus;													\
+																						\
+		uxSavedInterruptStatus = ( UBaseType_t ) portSET_INTERRUPT_MASK_FROM_ISR();		\
+		{																				\
+			if( ( pxStreamBuffer )->xTaskWaitingToSend != NULL )						\
+			{																			\
+				( void ) xTaskNotifyFromISR( ( pxStreamBuffer )->xTaskWaitingToSend,	\
+											 ( uint32_t ) 0,							\
+											 eNoAction,									\
+											 pxHigherPriorityTaskWoken );				\
+				( pxStreamBuffer )->xTaskWaitingToSend = NULL;							\
+			}																			\
+		}																				\
+		portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );					\
+	}
+#endif /* sbRECEIVE_COMPLETED_FROM_ISR */
+
+/* If the user has not provided an application specific Tx notification macro,
+or #defined the notification macro away, them provide a default implementation
+that uses task notifications. */
+#ifndef sbSEND_COMPLETED
+	#define sbSEND_COMPLETED( pxStreamBuffer )											\
+		vTaskSuspendAll();																\
+		{																				\
+			if( ( pxStreamBuffer )->xTaskWaitingToReceive != NULL )						\
+			{																			\
+				( void ) xTaskNotify( ( pxStreamBuffer )->xTaskWaitingToReceive,		\
+									  ( uint32_t ) 0,									\
+									  eNoAction );										\
+				( pxStreamBuffer )->xTaskWaitingToReceive = NULL;						\
+			}																			\
+		}																				\
+		( void ) xTaskResumeAll();
+#endif /* sbSEND_COMPLETED */
+
+#ifndef sbSEND_COMPLETE_FROM_ISR
+	#define sbSEND_COMPLETE_FROM_ISR( pxStreamBuffer, pxHigherPriorityTaskWoken )		\
+	{																					\
+	UBaseType_t uxSavedInterruptStatus;													\
+																						\
+		uxSavedInterruptStatus = ( UBaseType_t ) portSET_INTERRUPT_MASK_FROM_ISR();		\
+		{																				\
+			if( ( pxStreamBuffer )->xTaskWaitingToReceive != NULL )						\
+			{																			\
+				( void ) xTaskNotifyFromISR( ( pxStreamBuffer )->xTaskWaitingToReceive,	\
+											 ( uint32_t ) 0,							\
+											 eNoAction,									\
+											 pxHigherPriorityTaskWoken );				\
+				( pxStreamBuffer )->xTaskWaitingToReceive = NULL;						\
+			}																			\
+		}																				\
+		portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );					\
+	}
+#endif /* sbSEND_COMPLETE_FROM_ISR */
+/*lint -restore (9026) */
+
+/* The number of bytes used to hold the length of a message in the buffer. */
+#define sbBYTES_TO_STORE_MESSAGE_LENGTH ( sizeof( configMESSAGE_BUFFER_LENGTH_TYPE ) )
+
+/* Bits stored in the ucFlags field of the stream buffer. */
+#define sbFLAGS_IS_MESSAGE_BUFFER		( ( uint8_t ) 1 ) /* Set if the stream buffer was created as a message buffer, in which case it holds discrete messages rather than a stream. */
+#define sbFLAGS_IS_STATICALLY_ALLOCATED ( ( uint8_t ) 2 ) /* Set if the stream buffer was created using statically allocated memory. */
+
+/*-----------------------------------------------------------*/
+
+/* Structure that hold state information on the buffer. */
+typedef struct StreamBufferDef_t /*lint !e9058 Style convention uses tag. */
+{
+	volatile size_t xTail;				/* Index to the next item to read within the buffer. */
+	volatile size_t xHead;				/* Index to the next item to write within the buffer. */
+	size_t xLength;						/* The length of the buffer pointed to by pucBuffer. */
+	size_t xTriggerLevelBytes;			/* The number of bytes that must be in the stream buffer before a task that is waiting for data is unblocked. */
+	volatile TaskHandle_t xTaskWaitingToReceive; /* Holds the handle of a task waiting for data, or NULL if no tasks are waiting. */
+	volatile TaskHandle_t xTaskWaitingToSend;	/* Holds the handle of a task waiting to send data to a message buffer that is full. */
+	uint8_t *pucBuffer;					/* Points to the buffer itself - that is - the RAM that stores the data passed through the buffer. */
+	uint8_t ucFlags;
+
+	#if ( configUSE_TRACE_FACILITY == 1 )
+		UBaseType_t uxStreamBufferNumber;		/* Used for tracing purposes. */
+	#endif
+} StreamBuffer_t;
+
+/*
+ * The number of bytes available to be read from the buffer.
+ */
+static size_t prvBytesInBuffer( const StreamBuffer_t * const pxStreamBuffer ) PRIVILEGED_FUNCTION;
+
+/*
+ * Add xCount bytes from pucData into the pxStreamBuffer message buffer.
+ * Returns the number of bytes written, which will either equal xCount in the
+ * success case, or 0 if there was not enough space in the buffer (in which case
+ * no data is written into the buffer).
+ */
+static size_t prvWriteBytesToBuffer( StreamBuffer_t * const pxStreamBuffer, const uint8_t *pucData, size_t xCount ) PRIVILEGED_FUNCTION;
+
+/*
+ * If the stream buffer is being used as a message buffer, then reads an entire
+ * message out of the buffer.  If the stream buffer is being used as a stream
+ * buffer then read as many bytes as possible from the buffer.
+ * prvReadBytesFromBuffer() is called to actually extract the bytes from the
+ * buffer's data storage area.
+ */
+static size_t prvReadMessageFromBuffer( StreamBuffer_t *pxStreamBuffer,
+										void *pvRxData,
+										size_t xBufferLengthBytes,
+										size_t xBytesAvailable,
+										size_t xBytesToStoreMessageLength ) PRIVILEGED_FUNCTION;
+
+/*
+ * If the stream buffer is being used as a message buffer, then writes an entire
+ * message to the buffer.  If the stream buffer is being used as a stream
+ * buffer then write as many bytes as possible to the buffer.
+ * prvWriteBytestoBuffer() is called to actually send the bytes to the buffer's
+ * data storage area.
+ */
+static size_t prvWriteMessageToBuffer(  StreamBuffer_t * const pxStreamBuffer,
+										const void * pvTxData,
+										size_t xDataLengthBytes,
+										size_t xSpace,
+										size_t xRequiredSpace ) PRIVILEGED_FUNCTION;
+
+/*
+ * Read xMaxCount bytes from the pxStreamBuffer message buffer and write them
+ * to pucData.
+ */
+static size_t prvReadBytesFromBuffer( StreamBuffer_t *pxStreamBuffer,
+									  uint8_t *pucData,
+									  size_t xMaxCount,
+									  size_t xBytesAvailable ) PRIVILEGED_FUNCTION;
+
+/*
+ * Called by both pxStreamBufferCreate() and pxStreamBufferCreateStatic() to
+ * initialise the members of the newly created stream buffer structure.
+ */
+static void prvInitialiseNewStreamBuffer( StreamBuffer_t * const pxStreamBuffer,
+										  uint8_t * const pucBuffer,
+										  size_t xBufferSizeBytes,
+										  size_t xTriggerLevelBytes,
+										  uint8_t ucFlags ) PRIVILEGED_FUNCTION;
+
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+
+	StreamBufferHandle_t xStreamBufferGenericCreate( size_t xBufferSizeBytes, size_t xTriggerLevelBytes, BaseType_t xIsMessageBuffer )
+	{
+	uint8_t *pucAllocatedMemory;
+	uint8_t ucFlags;
+
+		/* In case the stream buffer is going to be used as a message buffer
+		(that is, it will hold discrete messages with a little meta data that
+		says how big the next message is) check the buffer will be large enough
+		to hold at least one message. */
+		if( xIsMessageBuffer == pdTRUE )
+		{
+			/* Is a message buffer but not statically allocated. */
+			ucFlags = sbFLAGS_IS_MESSAGE_BUFFER;
+			configASSERT( xBufferSizeBytes > sbBYTES_TO_STORE_MESSAGE_LENGTH );
+		}
+		else
+		{
+			/* Not a message buffer and not statically allocated. */
+			ucFlags = 0;
+			configASSERT( xBufferSizeBytes > 0 );
+		}
+		configASSERT( xTriggerLevelBytes <= xBufferSizeBytes );
+
+		/* A trigger level of 0 would cause a waiting task to unblock even when
+		the buffer was empty. */
+		if( xTriggerLevelBytes == ( size_t ) 0 )
+		{
+			xTriggerLevelBytes = ( size_t ) 1;
+		}
+
+		/* A stream buffer requires a StreamBuffer_t structure and a buffer.
+		Both are allocated in a single call to pvPortMalloc().  The
+		StreamBuffer_t structure is placed at the start of the allocated memory
+		and the buffer follows immediately after.  The requested size is
+		incremented so the free space is returned as the user would expect -
+		this is a quirk of the implementation that means otherwise the free
+		space would be reported as one byte smaller than would be logically
+		expected. */
+		xBufferSizeBytes++;
+		pucAllocatedMemory = ( uint8_t * ) pvPortMalloc( xBufferSizeBytes + sizeof( StreamBuffer_t ) ); /*lint !e9079 malloc() only returns void*. */
+
+		if( pucAllocatedMemory != NULL )
+		{
+			prvInitialiseNewStreamBuffer( ( StreamBuffer_t * ) pucAllocatedMemory, /* Structure at the start of the allocated memory. */ /*lint !e9087 Safe cast as allocated memory is aligned. */ /*lint !e826 Area is not too small and alignment is guaranteed provided malloc() behaves as expected and returns aligned buffer. */
+										   pucAllocatedMemory + sizeof( StreamBuffer_t ),  /* Storage area follows. */ /*lint !e9016 Indexing past structure valid for uint8_t pointer, also storage area has no alignment requirement. */
+										   xBufferSizeBytes,
+										   xTriggerLevelBytes,
+										   ucFlags );
+
+			traceSTREAM_BUFFER_CREATE( ( ( StreamBuffer_t * ) pucAllocatedMemory ), xIsMessageBuffer );
+		}
+		else
+		{
+			traceSTREAM_BUFFER_CREATE_FAILED( xIsMessageBuffer );
+		}
+
+		return ( StreamBufferHandle_t ) pucAllocatedMemory; /*lint !e9087 !e826 Safe cast as allocated memory is aligned. */
+	}
+
+#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+
+	StreamBufferHandle_t xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes,
+														   size_t xTriggerLevelBytes,
+														   BaseType_t xIsMessageBuffer,
+														   uint8_t * const pucStreamBufferStorageArea,
+														   StaticStreamBuffer_t * const pxStaticStreamBuffer )
+	{
+	StreamBuffer_t * const pxStreamBuffer = ( StreamBuffer_t * ) pxStaticStreamBuffer; /*lint !e740 !e9087 Safe cast as StaticStreamBuffer_t is opaque Streambuffer_t. */
+	StreamBufferHandle_t xReturn;
+	uint8_t ucFlags;
+
+		configASSERT( pucStreamBufferStorageArea );
+		configASSERT( pxStaticStreamBuffer );
+		configASSERT( xTriggerLevelBytes <= xBufferSizeBytes );
+
+		/* A trigger level of 0 would cause a waiting task to unblock even when
+		the buffer was empty. */
+		if( xTriggerLevelBytes == ( size_t ) 0 )
+		{
+			xTriggerLevelBytes = ( size_t ) 1;
+		}
+
+		if( xIsMessageBuffer != pdFALSE )
+		{
+			/* Statically allocated message buffer. */
+			ucFlags = sbFLAGS_IS_MESSAGE_BUFFER | sbFLAGS_IS_STATICALLY_ALLOCATED;
+		}
+		else
+		{
+			/* Statically allocated stream buffer. */
+			ucFlags = sbFLAGS_IS_STATICALLY_ALLOCATED;
+		}
+
+		/* In case the stream buffer is going to be used as a message buffer
+		(that is, it will hold discrete messages with a little meta data that
+		says how big the next message is) check the buffer will be large enough
+		to hold at least one message. */
+		configASSERT( xBufferSizeBytes > sbBYTES_TO_STORE_MESSAGE_LENGTH );
+
+		#if( configASSERT_DEFINED == 1 )
+		{
+			/* Sanity check that the size of the structure used to declare a
+			variable of type StaticStreamBuffer_t equals the size of the real
+			message buffer structure. */
+			volatile size_t xSize = sizeof( StaticStreamBuffer_t );
+			configASSERT( xSize == sizeof( StreamBuffer_t ) );
+		} /*lint !e529 xSize is referenced is configASSERT() is defined. */
+		#endif /* configASSERT_DEFINED */
+
+		if( ( pucStreamBufferStorageArea != NULL ) && ( pxStaticStreamBuffer != NULL ) )
+		{
+			prvInitialiseNewStreamBuffer( pxStreamBuffer,
+										  pucStreamBufferStorageArea,
+										  xBufferSizeBytes,
+										  xTriggerLevelBytes,
+										  ucFlags );
+
+			/* Remember this was statically allocated in case it is ever deleted
+			again. */
+			pxStreamBuffer->ucFlags |= sbFLAGS_IS_STATICALLY_ALLOCATED;
+
+			traceSTREAM_BUFFER_CREATE( pxStreamBuffer, xIsMessageBuffer );
+
+			xReturn = ( StreamBufferHandle_t ) pxStaticStreamBuffer; /*lint !e9087 Data hiding requires cast to opaque type. */
+		}
+		else
+		{
+			xReturn = NULL;
+			traceSTREAM_BUFFER_CREATE_STATIC_FAILED( xReturn, xIsMessageBuffer );
+		}
+
+		return xReturn;
+	}
+
+#endif /* ( configSUPPORT_STATIC_ALLOCATION == 1 ) */
+/*-----------------------------------------------------------*/
+
+void vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer )
+{
+StreamBuffer_t * pxStreamBuffer = xStreamBuffer;
+
+	configASSERT( pxStreamBuffer );
+
+	traceSTREAM_BUFFER_DELETE( xStreamBuffer );
+
+	if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_STATICALLY_ALLOCATED ) == ( uint8_t ) pdFALSE )
+	{
+		#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+		{
+			/* Both the structure and the buffer were allocated using a single call
+			to pvPortMalloc(), hence only one call to vPortFree() is required. */
+			vPortFree( ( void * ) pxStreamBuffer ); /*lint !e9087 Standard free() semantics require void *, plus pxStreamBuffer was allocated by pvPortMalloc(). */
+		}
+		#else
+		{
+			/* Should not be possible to get here, ucFlags must be corrupt.
+			Force an assert. */
+			configASSERT( xStreamBuffer == ( StreamBufferHandle_t ) ~0 );
+		}
+		#endif
+	}
+	else
+	{
+		/* The structure and buffer were not allocated dynamically and cannot be
+		freed - just scrub the structure so future use will assert. */
+		( void ) memset( pxStreamBuffer, 0x00, sizeof( StreamBuffer_t ) );
+	}
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xStreamBufferReset( StreamBufferHandle_t xStreamBuffer )
+{
+StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+BaseType_t xReturn = pdFAIL;
+
+#if( configUSE_TRACE_FACILITY == 1 )
+	UBaseType_t uxStreamBufferNumber;
+#endif
+
+	configASSERT( pxStreamBuffer );
+
+	#if( configUSE_TRACE_FACILITY == 1 )
+	{
+		/* Store the stream buffer number so it can be restored after the
+		reset. */
+		uxStreamBufferNumber = pxStreamBuffer->uxStreamBufferNumber;
+	}
+	#endif
+
+	/* Can only reset a message buffer if there are no tasks blocked on it. */
+	taskENTER_CRITICAL();
+	{
+		if( pxStreamBuffer->xTaskWaitingToReceive == NULL )
+		{
+			if( pxStreamBuffer->xTaskWaitingToSend == NULL )
+			{
+				prvInitialiseNewStreamBuffer( pxStreamBuffer,
+											  pxStreamBuffer->pucBuffer,
+											  pxStreamBuffer->xLength,
+											  pxStreamBuffer->xTriggerLevelBytes,
+											  pxStreamBuffer->ucFlags );
+				xReturn = pdPASS;
+
+				#if( configUSE_TRACE_FACILITY == 1 )
+				{
+					pxStreamBuffer->uxStreamBufferNumber = uxStreamBufferNumber;
+				}
+				#endif
+
+				traceSTREAM_BUFFER_RESET( xStreamBuffer );
+			}
+		}
+	}
+	taskEXIT_CRITICAL();
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, size_t xTriggerLevel )
+{
+StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+BaseType_t xReturn;
+
+	configASSERT( pxStreamBuffer );
+
+	/* It is not valid for the trigger level to be 0. */
+	if( xTriggerLevel == ( size_t ) 0 )
+	{
+		xTriggerLevel = ( size_t ) 1;
+	}
+
+	/* The trigger level is the number of bytes that must be in the stream
+	buffer before a task that is waiting for data is unblocked. */
+	if( xTriggerLevel <= pxStreamBuffer->xLength )
+	{
+		pxStreamBuffer->xTriggerLevelBytes = xTriggerLevel;
+		xReturn = pdPASS;
+	}
+	else
+	{
+		xReturn = pdFALSE;
+	}
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+size_t xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer )
+{
+const StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+size_t xSpace;
+
+	configASSERT( pxStreamBuffer );
+
+	xSpace = pxStreamBuffer->xLength + pxStreamBuffer->xTail;
+	xSpace -= pxStreamBuffer->xHead;
+	xSpace -= ( size_t ) 1;
+
+	if( xSpace >= pxStreamBuffer->xLength )
+	{
+		xSpace -= pxStreamBuffer->xLength;
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	return xSpace;
+}
+/*-----------------------------------------------------------*/
+
+size_t xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer )
+{
+const StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+size_t xReturn;
+
+	configASSERT( pxStreamBuffer );
+
+	xReturn = prvBytesInBuffer( pxStreamBuffer );
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+size_t xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+						  const void *pvTxData,
+						  size_t xDataLengthBytes,
+						  TickType_t xTicksToWait )
+{
+StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+size_t xReturn, xSpace = 0;
+size_t xRequiredSpace = xDataLengthBytes;
+TimeOut_t xTimeOut;
+
+	configASSERT( pvTxData );
+	configASSERT( pxStreamBuffer );
+
+	/* This send function is used to write to both message buffers and stream
+	buffers.  If this is a message buffer then the space needed must be
+	increased by the amount of bytes needed to store the length of the
+	message. */
+	if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )
+	{
+		xRequiredSpace += sbBYTES_TO_STORE_MESSAGE_LENGTH;
+
+		/* Overflow? */
+		configASSERT( xRequiredSpace > xDataLengthBytes );
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	if( xTicksToWait != ( TickType_t ) 0 )
+	{
+		vTaskSetTimeOutState( &xTimeOut );
+
+		do
+		{
+			/* Wait until the required number of bytes are free in the message
+			buffer. */
+			taskENTER_CRITICAL();
+			{
+				xSpace = xStreamBufferSpacesAvailable( pxStreamBuffer );
+
+				if( xSpace < xRequiredSpace )
+				{
+					/* Clear notification state as going to wait for space. */
+					( void ) xTaskNotifyStateClear( NULL );
+
+					/* Should only be one writer. */
+					configASSERT( pxStreamBuffer->xTaskWaitingToSend == NULL );
+					pxStreamBuffer->xTaskWaitingToSend = xTaskGetCurrentTaskHandle();
+				}
+				else
+				{
+					taskEXIT_CRITICAL();
+					break;
+				}
+			}
+			taskEXIT_CRITICAL();
+
+			traceBLOCKING_ON_STREAM_BUFFER_SEND( xStreamBuffer );
+			( void ) xTaskNotifyWait( ( uint32_t ) 0, ( uint32_t ) 0, NULL, xTicksToWait );
+			pxStreamBuffer->xTaskWaitingToSend = NULL;
+
+		} while( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE );
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	if( xSpace == ( size_t ) 0 )
+	{
+		xSpace = xStreamBufferSpacesAvailable( pxStreamBuffer );
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	xReturn = prvWriteMessageToBuffer( pxStreamBuffer, pvTxData, xDataLengthBytes, xSpace, xRequiredSpace );
+
+	if( xReturn > ( size_t ) 0 )
+	{
+		traceSTREAM_BUFFER_SEND( xStreamBuffer, xReturn );
+
+		/* Was a task waiting for the data? */
+		if( prvBytesInBuffer( pxStreamBuffer ) >= pxStreamBuffer->xTriggerLevelBytes )
+		{
+			sbSEND_COMPLETED( pxStreamBuffer );
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+		traceSTREAM_BUFFER_SEND_FAILED( xStreamBuffer );
+	}
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+size_t xStreamBufferSendFromISR( StreamBufferHandle_t xStreamBuffer,
+								 const void *pvTxData,
+								 size_t xDataLengthBytes,
+								 BaseType_t * const pxHigherPriorityTaskWoken )
+{
+StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+size_t xReturn, xSpace;
+size_t xRequiredSpace = xDataLengthBytes;
+
+	configASSERT( pvTxData );
+	configASSERT( pxStreamBuffer );
+
+	/* This send function is used to write to both message buffers and stream
+	buffers.  If this is a message buffer then the space needed must be
+	increased by the amount of bytes needed to store the length of the
+	message. */
+	if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )
+	{
+		xRequiredSpace += sbBYTES_TO_STORE_MESSAGE_LENGTH;
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	xSpace = xStreamBufferSpacesAvailable( pxStreamBuffer );
+	xReturn = prvWriteMessageToBuffer( pxStreamBuffer, pvTxData, xDataLengthBytes, xSpace, xRequiredSpace );
+
+	if( xReturn > ( size_t ) 0 )
+	{
+		/* Was a task waiting for the data? */
+		if( prvBytesInBuffer( pxStreamBuffer ) >= pxStreamBuffer->xTriggerLevelBytes )
+		{
+			sbSEND_COMPLETE_FROM_ISR( pxStreamBuffer, pxHigherPriorityTaskWoken );
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	traceSTREAM_BUFFER_SEND_FROM_ISR( xStreamBuffer, xReturn );
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+static size_t prvWriteMessageToBuffer( StreamBuffer_t * const pxStreamBuffer,
+									   const void * pvTxData,
+									   size_t xDataLengthBytes,
+									   size_t xSpace,
+									   size_t xRequiredSpace )
+{
+	BaseType_t xShouldWrite;
+	size_t xReturn;
+
+	if( xSpace == ( size_t ) 0 )
+	{
+		/* Doesn't matter if this is a stream buffer or a message buffer, there
+		is no space to write. */
+		xShouldWrite = pdFALSE;
+	}
+	else if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) == ( uint8_t ) 0 )
+	{
+		/* This is a stream buffer, as opposed to a message buffer, so writing a
+		stream of bytes rather than discrete messages.  Write as many bytes as
+		possible. */
+		xShouldWrite = pdTRUE;
+		xDataLengthBytes = configMIN( xDataLengthBytes, xSpace );
+	}
+	else if( xSpace >= xRequiredSpace )
+	{
+		/* This is a message buffer, as opposed to a stream buffer, and there
+		is enough space to write both the message length and the message itself
+		into the buffer.  Start by writing the length of the data, the data
+		itself will be written later in this function. */
+		xShouldWrite = pdTRUE;
+		( void ) prvWriteBytesToBuffer( pxStreamBuffer, ( const uint8_t * ) &( xDataLengthBytes ), sbBYTES_TO_STORE_MESSAGE_LENGTH );
+	}
+	else
+	{
+		/* There is space available, but not enough space. */
+		xShouldWrite = pdFALSE;
+	}
+
+	if( xShouldWrite != pdFALSE )
+	{
+		/* Writes the data itself. */
+		xReturn = prvWriteBytesToBuffer( pxStreamBuffer, ( const uint8_t * ) pvTxData, xDataLengthBytes ); /*lint !e9079 Storage buffer is implemented as uint8_t for ease of sizing, alighment and access. */
+	}
+	else
+	{
+		xReturn = 0;
+	}
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+size_t xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+							 void *pvRxData,
+							 size_t xBufferLengthBytes,
+							 TickType_t xTicksToWait )
+{
+StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+size_t xReceivedLength = 0, xBytesAvailable, xBytesToStoreMessageLength;
+
+	configASSERT( pvRxData );
+	configASSERT( pxStreamBuffer );
+
+	/* This receive function is used by both message buffers, which store
+	discrete messages, and stream buffers, which store a continuous stream of
+	bytes.  Discrete messages include an additional
+	sbBYTES_TO_STORE_MESSAGE_LENGTH bytes that hold the length of the
+	message. */
+	if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )
+	{
+		xBytesToStoreMessageLength = sbBYTES_TO_STORE_MESSAGE_LENGTH;
+	}
+	else
+	{
+		xBytesToStoreMessageLength = 0;
+	}
+
+	if( xTicksToWait != ( TickType_t ) 0 )
+	{
+		/* Checking if there is data and clearing the notification state must be
+		performed atomically. */
+		taskENTER_CRITICAL();
+		{
+			xBytesAvailable = prvBytesInBuffer( pxStreamBuffer );
+
+			/* If this function was invoked by a message buffer read then
+			xBytesToStoreMessageLength holds the number of bytes used to hold
+			the length of the next discrete message.  If this function was
+			invoked by a stream buffer read then xBytesToStoreMessageLength will
+			be 0. */
+			if( xBytesAvailable <= xBytesToStoreMessageLength )
+			{
+				/* Clear notification state as going to wait for data. */
+				( void ) xTaskNotifyStateClear( NULL );
+
+				/* Should only be one reader. */
+				configASSERT( pxStreamBuffer->xTaskWaitingToReceive == NULL );
+				pxStreamBuffer->xTaskWaitingToReceive = xTaskGetCurrentTaskHandle();
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		taskEXIT_CRITICAL();
+
+		if( xBytesAvailable <= xBytesToStoreMessageLength )
+		{
+			/* Wait for data to be available. */
+			traceBLOCKING_ON_STREAM_BUFFER_RECEIVE( xStreamBuffer );
+			( void ) xTaskNotifyWait( ( uint32_t ) 0, ( uint32_t ) 0, NULL, xTicksToWait );
+			pxStreamBuffer->xTaskWaitingToReceive = NULL;
+
+			/* Recheck the data available after blocking. */
+			xBytesAvailable = prvBytesInBuffer( pxStreamBuffer );
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	else
+	{
+		xBytesAvailable = prvBytesInBuffer( pxStreamBuffer );
+	}
+
+	/* Whether receiving a discrete message (where xBytesToStoreMessageLength
+	holds the number of bytes used to store the message length) or a stream of
+	bytes (where xBytesToStoreMessageLength is zero), the number of bytes
+	available must be greater than xBytesToStoreMessageLength to be able to
+	read bytes from the buffer. */
+	if( xBytesAvailable > xBytesToStoreMessageLength )
+	{
+		xReceivedLength = prvReadMessageFromBuffer( pxStreamBuffer, pvRxData, xBufferLengthBytes, xBytesAvailable, xBytesToStoreMessageLength );
+
+		/* Was a task waiting for space in the buffer? */
+		if( xReceivedLength != ( size_t ) 0 )
+		{
+			traceSTREAM_BUFFER_RECEIVE( xStreamBuffer, xReceivedLength );
+			sbRECEIVE_COMPLETED( pxStreamBuffer );
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	else
+	{
+		traceSTREAM_BUFFER_RECEIVE_FAILED( xStreamBuffer );
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	return xReceivedLength;
+}
+/*-----------------------------------------------------------*/
+
+size_t xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer )
+{
+StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+size_t xReturn, xBytesAvailable, xOriginalTail;
+configMESSAGE_BUFFER_LENGTH_TYPE xTempReturn;
+
+	configASSERT( pxStreamBuffer );
+
+	/* Ensure the stream buffer is being used as a message buffer. */
+	if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )
+	{
+		xBytesAvailable = prvBytesInBuffer( pxStreamBuffer );
+		if( xBytesAvailable > sbBYTES_TO_STORE_MESSAGE_LENGTH )
+		{
+			/* The number of bytes available is greater than the number of bytes
+			required to hold the length of the next message, so another message
+			is available.  Return its length without removing the length bytes
+			from the buffer.  A copy of the tail is stored so the buffer can be
+			returned to its prior state as the message is not actually being
+			removed from the buffer. */
+			xOriginalTail = pxStreamBuffer->xTail;
+			( void ) prvReadBytesFromBuffer( pxStreamBuffer, ( uint8_t * ) &xTempReturn, sbBYTES_TO_STORE_MESSAGE_LENGTH, xBytesAvailable );
+			xReturn = ( size_t ) xTempReturn;
+			pxStreamBuffer->xTail = xOriginalTail;
+		}
+		else
+		{
+			/* The minimum amount of bytes in a message buffer is
+			( sbBYTES_TO_STORE_MESSAGE_LENGTH + 1 ), so if xBytesAvailable is
+			less than sbBYTES_TO_STORE_MESSAGE_LENGTH the only other valid
+			value is 0. */
+			configASSERT( xBytesAvailable == 0 );
+			xReturn = 0;
+		}
+	}
+	else
+	{
+		xReturn = 0;
+	}
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+size_t xStreamBufferReceiveFromISR( StreamBufferHandle_t xStreamBuffer,
+									void *pvRxData,
+									size_t xBufferLengthBytes,
+									BaseType_t * const pxHigherPriorityTaskWoken )
+{
+StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+size_t xReceivedLength = 0, xBytesAvailable, xBytesToStoreMessageLength;
+
+	configASSERT( pvRxData );
+	configASSERT( pxStreamBuffer );
+
+	/* This receive function is used by both message buffers, which store
+	discrete messages, and stream buffers, which store a continuous stream of
+	bytes.  Discrete messages include an additional
+	sbBYTES_TO_STORE_MESSAGE_LENGTH bytes that hold the length of the
+	message. */
+	if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )
+	{
+		xBytesToStoreMessageLength = sbBYTES_TO_STORE_MESSAGE_LENGTH;
+	}
+	else
+	{
+		xBytesToStoreMessageLength = 0;
+	}
+
+	xBytesAvailable = prvBytesInBuffer( pxStreamBuffer );
+
+	/* Whether receiving a discrete message (where xBytesToStoreMessageLength
+	holds the number of bytes used to store the message length) or a stream of
+	bytes (where xBytesToStoreMessageLength is zero), the number of bytes
+	available must be greater than xBytesToStoreMessageLength to be able to
+	read bytes from the buffer. */
+	if( xBytesAvailable > xBytesToStoreMessageLength )
+	{
+		xReceivedLength = prvReadMessageFromBuffer( pxStreamBuffer, pvRxData, xBufferLengthBytes, xBytesAvailable, xBytesToStoreMessageLength );
+
+		/* Was a task waiting for space in the buffer? */
+		if( xReceivedLength != ( size_t ) 0 )
+		{
+			sbRECEIVE_COMPLETED_FROM_ISR( pxStreamBuffer, pxHigherPriorityTaskWoken );
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	traceSTREAM_BUFFER_RECEIVE_FROM_ISR( xStreamBuffer, xReceivedLength );
+
+	return xReceivedLength;
+}
+/*-----------------------------------------------------------*/
+
+static size_t prvReadMessageFromBuffer( StreamBuffer_t *pxStreamBuffer,
+										void *pvRxData,
+										size_t xBufferLengthBytes,
+										size_t xBytesAvailable,
+										size_t xBytesToStoreMessageLength )
+{
+size_t xOriginalTail, xReceivedLength, xNextMessageLength;
+configMESSAGE_BUFFER_LENGTH_TYPE xTempNextMessageLength;
+
+	if( xBytesToStoreMessageLength != ( size_t ) 0 )
+	{
+		/* A discrete message is being received.  First receive the length
+		of the message.  A copy of the tail is stored so the buffer can be
+		returned to its prior state if the length of the message is too
+		large for the provided buffer. */
+		xOriginalTail = pxStreamBuffer->xTail;
+		( void ) prvReadBytesFromBuffer( pxStreamBuffer, ( uint8_t * ) &xTempNextMessageLength, xBytesToStoreMessageLength, xBytesAvailable );
+		xNextMessageLength = ( size_t ) xTempNextMessageLength;
+
+		/* Reduce the number of bytes available by the number of bytes just
+		read out. */
+		xBytesAvailable -= xBytesToStoreMessageLength;
+
+		/* Check there is enough space in the buffer provided by the
+		user. */
+		if( xNextMessageLength > xBufferLengthBytes )
+		{
+			/* The user has provided insufficient space to read the message
+			so return the buffer to its previous state (so the length of
+			the message is in the buffer again). */
+			pxStreamBuffer->xTail = xOriginalTail;
+			xNextMessageLength = 0;
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	else
+	{
+		/* A stream of bytes is being received (as opposed to a discrete
+		message), so read as many bytes as possible. */
+		xNextMessageLength = xBufferLengthBytes;
+	}
+
+	/* Read the actual data. */
+	xReceivedLength = prvReadBytesFromBuffer( pxStreamBuffer, ( uint8_t * ) pvRxData, xNextMessageLength, xBytesAvailable ); /*lint !e9079 Data storage area is implemented as uint8_t array for ease of sizing, indexing and alignment. */
+
+	return xReceivedLength;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer )
+{
+const StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+BaseType_t xReturn;
+size_t xTail;
+
+	configASSERT( pxStreamBuffer );
+
+	/* True if no bytes are available. */
+	xTail = pxStreamBuffer->xTail;
+	if( pxStreamBuffer->xHead == xTail )
+	{
+		xReturn = pdTRUE;
+	}
+	else
+	{
+		xReturn = pdFALSE;
+	}
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer )
+{
+BaseType_t xReturn;
+size_t xBytesToStoreMessageLength;
+const StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+
+	configASSERT( pxStreamBuffer );
+
+	/* This generic version of the receive function is used by both message
+	buffers, which store discrete messages, and stream buffers, which store a
+	continuous stream of bytes.  Discrete messages include an additional
+	sbBYTES_TO_STORE_MESSAGE_LENGTH bytes that hold the length of the message. */
+	if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )
+	{
+		xBytesToStoreMessageLength = sbBYTES_TO_STORE_MESSAGE_LENGTH;
+	}
+	else
+	{
+		xBytesToStoreMessageLength = 0;
+	}
+
+	/* True if the available space equals zero. */
+	if( xStreamBufferSpacesAvailable( xStreamBuffer ) <= xBytesToStoreMessageLength )
+	{
+		xReturn = pdTRUE;
+	}
+	else
+	{
+		xReturn = pdFALSE;
+	}
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xStreamBufferSendCompletedFromISR( StreamBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken )
+{
+StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+BaseType_t xReturn;
+UBaseType_t uxSavedInterruptStatus;
+
+	configASSERT( pxStreamBuffer );
+
+	uxSavedInterruptStatus = ( UBaseType_t ) portSET_INTERRUPT_MASK_FROM_ISR();
+	{
+		if( ( pxStreamBuffer )->xTaskWaitingToReceive != NULL )
+		{
+			( void ) xTaskNotifyFromISR( ( pxStreamBuffer )->xTaskWaitingToReceive,
+										 ( uint32_t ) 0,
+										 eNoAction,
+										 pxHigherPriorityTaskWoken );
+			( pxStreamBuffer )->xTaskWaitingToReceive = NULL;
+			xReturn = pdTRUE;
+		}
+		else
+		{
+			xReturn = pdFALSE;
+		}
+	}
+	portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xStreamBufferReceiveCompletedFromISR( StreamBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken )
+{
+StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+BaseType_t xReturn;
+UBaseType_t uxSavedInterruptStatus;
+
+	configASSERT( pxStreamBuffer );
+
+	uxSavedInterruptStatus = ( UBaseType_t ) portSET_INTERRUPT_MASK_FROM_ISR();
+	{
+		if( ( pxStreamBuffer )->xTaskWaitingToSend != NULL )
+		{
+			( void ) xTaskNotifyFromISR( ( pxStreamBuffer )->xTaskWaitingToSend,
+										 ( uint32_t ) 0,
+										 eNoAction,
+										 pxHigherPriorityTaskWoken );
+			( pxStreamBuffer )->xTaskWaitingToSend = NULL;
+			xReturn = pdTRUE;
+		}
+		else
+		{
+			xReturn = pdFALSE;
+		}
+	}
+	portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+static size_t prvWriteBytesToBuffer( StreamBuffer_t * const pxStreamBuffer, const uint8_t *pucData, size_t xCount )
+{
+size_t xNextHead, xFirstLength;
+
+	configASSERT( xCount > ( size_t ) 0 );
+
+	xNextHead = pxStreamBuffer->xHead;
+
+	/* Calculate the number of bytes that can be added in the first write -
+	which may be less than the total number of bytes that need to be added if
+	the buffer will wrap back to the beginning. */
+	xFirstLength = configMIN( pxStreamBuffer->xLength - xNextHead, xCount );
+
+	/* Write as many bytes as can be written in the first write. */
+	configASSERT( ( xNextHead + xFirstLength ) <= pxStreamBuffer->xLength );
+	( void ) memcpy( ( void* ) ( &( pxStreamBuffer->pucBuffer[ xNextHead ] ) ), ( const void * ) pucData, xFirstLength ); /*lint !e9087 memcpy() requires void *. */
+
+	/* If the number of bytes written was less than the number that could be
+	written in the first write... */
+	if( xCount > xFirstLength )
+	{
+		/* ...then write the remaining bytes to the start of the buffer. */
+		configASSERT( ( xCount - xFirstLength ) <= pxStreamBuffer->xLength );
+		( void ) memcpy( ( void * ) pxStreamBuffer->pucBuffer, ( const void * ) &( pucData[ xFirstLength ] ), xCount - xFirstLength ); /*lint !e9087 memcpy() requires void *. */
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	xNextHead += xCount;
+	if( xNextHead >= pxStreamBuffer->xLength )
+	{
+		xNextHead -= pxStreamBuffer->xLength;
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	pxStreamBuffer->xHead = xNextHead;
+
+	return xCount;
+}
+/*-----------------------------------------------------------*/
+
+static size_t prvReadBytesFromBuffer( StreamBuffer_t *pxStreamBuffer, uint8_t *pucData, size_t xMaxCount, size_t xBytesAvailable )
+{
+size_t xCount, xFirstLength, xNextTail;
+
+	/* Use the minimum of the wanted bytes and the available bytes. */
+	xCount = configMIN( xBytesAvailable, xMaxCount );
+
+	if( xCount > ( size_t ) 0 )
+	{
+		xNextTail = pxStreamBuffer->xTail;
+
+		/* Calculate the number of bytes that can be read - which may be
+		less than the number wanted if the data wraps around to the start of
+		the buffer. */
+		xFirstLength = configMIN( pxStreamBuffer->xLength - xNextTail, xCount );
+
+		/* Obtain the number of bytes it is possible to obtain in the first
+		read.  Asserts check bounds of read and write. */
+		configASSERT( xFirstLength <= xMaxCount );
+		configASSERT( ( xNextTail + xFirstLength ) <= pxStreamBuffer->xLength );
+		( void ) memcpy( ( void * ) pucData, ( const void * ) &( pxStreamBuffer->pucBuffer[ xNextTail ] ), xFirstLength ); /*lint !e9087 memcpy() requires void *. */
+
+		/* If the total number of wanted bytes is greater than the number
+		that could be read in the first read... */
+		if( xCount > xFirstLength )
+		{
+			/*...then read the remaining bytes from the start of the buffer. */
+			configASSERT( xCount <= xMaxCount );
+			( void ) memcpy( ( void * ) &( pucData[ xFirstLength ] ), ( void * ) ( pxStreamBuffer->pucBuffer ), xCount - xFirstLength ); /*lint !e9087 memcpy() requires void *. */
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		/* Move the tail pointer to effectively remove the data read from
+		the buffer. */
+		xNextTail += xCount;
+
+		if( xNextTail >= pxStreamBuffer->xLength )
+		{
+			xNextTail -= pxStreamBuffer->xLength;
+		}
+
+		pxStreamBuffer->xTail = xNextTail;
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	return xCount;
+}
+/*-----------------------------------------------------------*/
+
+static size_t prvBytesInBuffer( const StreamBuffer_t * const pxStreamBuffer )
+{
+/* Returns the distance between xTail and xHead. */
+size_t xCount;
+
+	xCount = pxStreamBuffer->xLength + pxStreamBuffer->xHead;
+	xCount -= pxStreamBuffer->xTail;
+	if ( xCount >= pxStreamBuffer->xLength )
+	{
+		xCount -= pxStreamBuffer->xLength;
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	return xCount;
+}
+/*-----------------------------------------------------------*/
+
+static void prvInitialiseNewStreamBuffer( StreamBuffer_t * const pxStreamBuffer,
+										  uint8_t * const pucBuffer,
+										  size_t xBufferSizeBytes,
+										  size_t xTriggerLevelBytes,
+										  uint8_t ucFlags )
+{
+	/* Assert here is deliberately writing to the entire buffer to ensure it can
+	be written to without generating exceptions, and is setting the buffer to a
+	known value to assist in development/debugging. */
+	#if( configASSERT_DEFINED == 1 )
+	{
+		/* The value written just has to be identifiable when looking at the
+		memory.  Don't use 0xA5 as that is the stack fill value and could
+		result in confusion as to what is actually being observed. */
+		const BaseType_t xWriteValue = 0x55;
+		configASSERT( memset( pucBuffer, ( int ) xWriteValue, xBufferSizeBytes ) == pucBuffer );
+	} /*lint !e529 !e438 xWriteValue is only used if configASSERT() is defined. */
+	#endif
+
+	( void ) memset( ( void * ) pxStreamBuffer, 0x00, sizeof( StreamBuffer_t ) ); /*lint !e9087 memset() requires void *. */
+	pxStreamBuffer->pucBuffer = pucBuffer;
+	pxStreamBuffer->xLength = xBufferSizeBytes;
+	pxStreamBuffer->xTriggerLevelBytes = xTriggerLevelBytes;
+	pxStreamBuffer->ucFlags = ucFlags;
+}
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	UBaseType_t uxStreamBufferGetStreamBufferNumber( StreamBufferHandle_t xStreamBuffer )
+	{
+		return xStreamBuffer->uxStreamBufferNumber;
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	void vStreamBufferSetStreamBufferNumber( StreamBufferHandle_t xStreamBuffer, UBaseType_t uxStreamBufferNumber )
+	{
+		xStreamBuffer->uxStreamBufferNumber = uxStreamBufferNumber;
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	uint8_t ucStreamBufferGetStreamBufferType( StreamBufferHandle_t xStreamBuffer )
+	{
+		return ( xStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER );
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/tasks.c b/Middlewares/Third_Party/FreeRTOS/Source/tasks.c
new file mode 100644
index 0000000..f6a6a9b
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/tasks.c
@@ -0,0 +1,5310 @@
+/*
+ * FreeRTOS Kernel V10.3.1
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Standard includes. */
+#include <stdlib.h>
+#include <string.h>
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+all the API functions to use the MPU wrappers.  That should only be done when
+task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* FreeRTOS includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "timers.h"
+#include "stack_macros.h"
+
+/* Lint e9021, e961 and e750 are suppressed as a MISRA exception justified
+because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined
+for the header files above, but not in this file, in order to generate the
+correct privileged Vs unprivileged linkage and placement. */
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750 !e9021. */
+
+/* Set configUSE_STATS_FORMATTING_FUNCTIONS to 2 to include the stats formatting
+functions but without including stdio.h here. */
+#if ( configUSE_STATS_FORMATTING_FUNCTIONS == 1 )
+	/* At the bottom of this file are two optional functions that can be used
+	to generate human readable text from the raw data generated by the
+	uxTaskGetSystemState() function.  Note the formatting functions are provided
+	for convenience only, and are NOT considered part of the kernel. */
+	#include <stdio.h>
+#endif /* configUSE_STATS_FORMATTING_FUNCTIONS == 1 ) */
+
+#if( configUSE_PREEMPTION == 0 )
+	/* If the cooperative scheduler is being used then a yield should not be
+	performed just because a higher priority task has been woken. */
+	#define taskYIELD_IF_USING_PREEMPTION()
+#else
+	#define taskYIELD_IF_USING_PREEMPTION() portYIELD_WITHIN_API()
+#endif
+
+/* Values that can be assigned to the ucNotifyState member of the TCB. */
+#define taskNOT_WAITING_NOTIFICATION	( ( uint8_t ) 0 )
+#define taskWAITING_NOTIFICATION		( ( uint8_t ) 1 )
+#define taskNOTIFICATION_RECEIVED		( ( uint8_t ) 2 )
+
+/*
+ * The value used to fill the stack of a task when the task is created.  This
+ * is used purely for checking the high water mark for tasks.
+ */
+#define tskSTACK_FILL_BYTE	( 0xa5U )
+
+/* Bits used to recored how a task's stack and TCB were allocated. */
+#define tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB 		( ( uint8_t ) 0 )
+#define tskSTATICALLY_ALLOCATED_STACK_ONLY 			( ( uint8_t ) 1 )
+#define tskSTATICALLY_ALLOCATED_STACK_AND_TCB		( ( uint8_t ) 2 )
+
+/* If any of the following are set then task stacks are filled with a known
+value so the high water mark can be determined.  If none of the following are
+set then don't fill the stack so there is no unnecessary dependency on memset. */
+#if( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) || ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) )
+	#define tskSET_NEW_STACKS_TO_KNOWN_VALUE	1
+#else
+	#define tskSET_NEW_STACKS_TO_KNOWN_VALUE	0
+#endif
+
+/*
+ * Macros used by vListTask to indicate which state a task is in.
+ */
+#define tskRUNNING_CHAR		( 'X' )
+#define tskBLOCKED_CHAR		( 'B' )
+#define tskREADY_CHAR		( 'R' )
+#define tskDELETED_CHAR		( 'D' )
+#define tskSUSPENDED_CHAR	( 'S' )
+
+/*
+ * Some kernel aware debuggers require the data the debugger needs access to be
+ * global, rather than file scope.
+ */
+#ifdef portREMOVE_STATIC_QUALIFIER
+	#define static
+#endif
+
+/* The name allocated to the Idle task.  This can be overridden by defining
+configIDLE_TASK_NAME in FreeRTOSConfig.h. */
+#ifndef configIDLE_TASK_NAME
+	#define configIDLE_TASK_NAME "IDLE"
+#endif
+
+#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 0 )
+
+	/* If configUSE_PORT_OPTIMISED_TASK_SELECTION is 0 then task selection is
+	performed in a generic way that is not optimised to any particular
+	microcontroller architecture. */
+
+	/* uxTopReadyPriority holds the priority of the highest priority ready
+	state task. */
+	#define taskRECORD_READY_PRIORITY( uxPriority )														\
+	{																									\
+		if( ( uxPriority ) > uxTopReadyPriority )														\
+		{																								\
+			uxTopReadyPriority = ( uxPriority );														\
+		}																								\
+	} /* taskRECORD_READY_PRIORITY */
+
+	/*-----------------------------------------------------------*/
+
+	#define taskSELECT_HIGHEST_PRIORITY_TASK()															\
+	{																									\
+	UBaseType_t uxTopPriority = uxTopReadyPriority;														\
+																										\
+		/* Find the highest priority queue that contains ready tasks. */								\
+		while( listLIST_IS_EMPTY( &( pxReadyTasksLists[ uxTopPriority ] ) ) )							\
+		{																								\
+			configASSERT( uxTopPriority );																\
+			--uxTopPriority;																			\
+		}																								\
+																										\
+		/* listGET_OWNER_OF_NEXT_ENTRY indexes through the list, so the tasks of						\
+		the	same priority get an equal share of the processor time. */									\
+		listGET_OWNER_OF_NEXT_ENTRY( pxCurrentTCB, &( pxReadyTasksLists[ uxTopPriority ] ) );			\
+		uxTopReadyPriority = uxTopPriority;																\
+	} /* taskSELECT_HIGHEST_PRIORITY_TASK */
+
+	/*-----------------------------------------------------------*/
+
+	/* Define away taskRESET_READY_PRIORITY() and portRESET_READY_PRIORITY() as
+	they are only required when a port optimised method of task selection is
+	being used. */
+	#define taskRESET_READY_PRIORITY( uxPriority )
+	#define portRESET_READY_PRIORITY( uxPriority, uxTopReadyPriority )
+
+#else /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+	/* If configUSE_PORT_OPTIMISED_TASK_SELECTION is 1 then task selection is
+	performed in a way that is tailored to the particular microcontroller
+	architecture being used. */
+
+	/* A port optimised version is provided.  Call the port defined macros. */
+	#define taskRECORD_READY_PRIORITY( uxPriority )	portRECORD_READY_PRIORITY( uxPriority, uxTopReadyPriority )
+
+	/*-----------------------------------------------------------*/
+
+	#define taskSELECT_HIGHEST_PRIORITY_TASK()														\
+	{																								\
+	UBaseType_t uxTopPriority;																		\
+																									\
+		/* Find the highest priority list that contains ready tasks. */								\
+		portGET_HIGHEST_PRIORITY( uxTopPriority, uxTopReadyPriority );								\
+		configASSERT( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ uxTopPriority ] ) ) > 0 );		\
+		listGET_OWNER_OF_NEXT_ENTRY( pxCurrentTCB, &( pxReadyTasksLists[ uxTopPriority ] ) );		\
+	} /* taskSELECT_HIGHEST_PRIORITY_TASK() */
+
+	/*-----------------------------------------------------------*/
+
+	/* A port optimised version is provided, call it only if the TCB being reset
+	is being referenced from a ready list.  If it is referenced from a delayed
+	or suspended list then it won't be in a ready list. */
+	#define taskRESET_READY_PRIORITY( uxPriority )														\
+	{																									\
+		if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ ( uxPriority ) ] ) ) == ( UBaseType_t ) 0 )	\
+		{																								\
+			portRESET_READY_PRIORITY( ( uxPriority ), ( uxTopReadyPriority ) );							\
+		}																								\
+	}
+
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+/*-----------------------------------------------------------*/
+
+/* pxDelayedTaskList and pxOverflowDelayedTaskList are switched when the tick
+count overflows. */
+#define taskSWITCH_DELAYED_LISTS()																	\
+{																									\
+	List_t *pxTemp;																					\
+																									\
+	/* The delayed tasks list should be empty when the lists are switched. */						\
+	configASSERT( ( listLIST_IS_EMPTY( pxDelayedTaskList ) ) );										\
+																									\
+	pxTemp = pxDelayedTaskList;																		\
+	pxDelayedTaskList = pxOverflowDelayedTaskList;													\
+	pxOverflowDelayedTaskList = pxTemp;																\
+	xNumOfOverflows++;																				\
+	prvResetNextTaskUnblockTime();																	\
+}
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Place the task represented by pxTCB into the appropriate ready list for
+ * the task.  It is inserted at the end of the list.
+ */
+#define prvAddTaskToReadyList( pxTCB )																\
+	traceMOVED_TASK_TO_READY_STATE( pxTCB );														\
+	taskRECORD_READY_PRIORITY( ( pxTCB )->uxPriority );												\
+	vListInsertEnd( &( pxReadyTasksLists[ ( pxTCB )->uxPriority ] ), &( ( pxTCB )->xStateListItem ) ); \
+	tracePOST_MOVED_TASK_TO_READY_STATE( pxTCB )
+/*-----------------------------------------------------------*/
+
+/*
+ * Several functions take an TaskHandle_t parameter that can optionally be NULL,
+ * where NULL is used to indicate that the handle of the currently executing
+ * task should be used in place of the parameter.  This macro simply checks to
+ * see if the parameter is NULL and returns a pointer to the appropriate TCB.
+ */
+#define prvGetTCBFromHandle( pxHandle ) ( ( ( pxHandle ) == NULL ) ? pxCurrentTCB : ( pxHandle ) )
+
+/* The item value of the event list item is normally used to hold the priority
+of the task to which it belongs (coded to allow it to be held in reverse
+priority order).  However, it is occasionally borrowed for other purposes.  It
+is important its value is not updated due to a task priority change while it is
+being used for another purpose.  The following bit definition is used to inform
+the scheduler that the value should not be changed - in which case it is the
+responsibility of whichever module is using the value to ensure it gets set back
+to its original value when it is released. */
+#if( configUSE_16_BIT_TICKS == 1 )
+	#define taskEVENT_LIST_ITEM_VALUE_IN_USE	0x8000U
+#else
+	#define taskEVENT_LIST_ITEM_VALUE_IN_USE	0x80000000UL
+#endif
+
+/*
+ * Task control block.  A task control block (TCB) is allocated for each task,
+ * and stores task state information, including a pointer to the task's context
+ * (the task's run time environment, including register values)
+ */
+typedef struct tskTaskControlBlock 			/* The old naming convention is used to prevent breaking kernel aware debuggers. */
+{
+	volatile StackType_t	*pxTopOfStack;	/*< Points to the location of the last item placed on the tasks stack.  THIS MUST BE THE FIRST MEMBER OF THE TCB STRUCT. */
+
+	#if ( portUSING_MPU_WRAPPERS == 1 )
+		xMPU_SETTINGS	xMPUSettings;		/*< The MPU settings are defined as part of the port layer.  THIS MUST BE THE SECOND MEMBER OF THE TCB STRUCT. */
+	#endif
+
+	ListItem_t			xStateListItem;	/*< The list that the state list item of a task is reference from denotes the state of that task (Ready, Blocked, Suspended ). */
+	ListItem_t			xEventListItem;		/*< Used to reference a task from an event list. */
+	UBaseType_t			uxPriority;			/*< The priority of the task.  0 is the lowest priority. */
+	StackType_t			*pxStack;			/*< Points to the start of the stack. */
+	char				pcTaskName[ configMAX_TASK_NAME_LEN ];/*< Descriptive name given to the task when created.  Facilitates debugging only. */ /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+
+	#if ( ( portSTACK_GROWTH > 0 ) || ( configRECORD_STACK_HIGH_ADDRESS == 1 ) )
+		StackType_t		*pxEndOfStack;		/*< Points to the highest valid address for the stack. */
+	#endif
+
+	#if ( portCRITICAL_NESTING_IN_TCB == 1 )
+		UBaseType_t		uxCriticalNesting;	/*< Holds the critical section nesting depth for ports that do not maintain their own count in the port layer. */
+	#endif
+
+	#if ( configUSE_TRACE_FACILITY == 1 )
+		UBaseType_t		uxTCBNumber;		/*< Stores a number that increments each time a TCB is created.  It allows debuggers to determine when a task has been deleted and then recreated. */
+		UBaseType_t		uxTaskNumber;		/*< Stores a number specifically for use by third party trace code. */
+	#endif
+
+	#if ( configUSE_MUTEXES == 1 )
+		UBaseType_t		uxBasePriority;		/*< The priority last assigned to the task - used by the priority inheritance mechanism. */
+		UBaseType_t		uxMutexesHeld;
+	#endif
+
+	#if ( configUSE_APPLICATION_TASK_TAG == 1 )
+		TaskHookFunction_t pxTaskTag;
+	#endif
+
+	#if( configNUM_THREAD_LOCAL_STORAGE_POINTERS > 0 )
+		void			*pvThreadLocalStoragePointers[ configNUM_THREAD_LOCAL_STORAGE_POINTERS ];
+	#endif
+
+	#if( configGENERATE_RUN_TIME_STATS == 1 )
+		uint32_t		ulRunTimeCounter;	/*< Stores the amount of time the task has spent in the Running state. */
+	#endif
+
+	#if ( configUSE_NEWLIB_REENTRANT == 1 )
+		/* Allocate a Newlib reent structure that is specific to this task.
+		Note Newlib support has been included by popular demand, but is not
+		used by the FreeRTOS maintainers themselves.  FreeRTOS is not
+		responsible for resulting newlib operation.  User must be familiar with
+		newlib and must provide system-wide implementations of the necessary
+		stubs. Be warned that (at the time of writing) the current newlib design
+		implements a system-wide malloc() that must be provided with locks.
+
+		See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html
+		for additional information. */
+		struct	_reent xNewLib_reent;
+	#endif
+
+	#if( configUSE_TASK_NOTIFICATIONS == 1 )
+		volatile uint32_t ulNotifiedValue;
+		volatile uint8_t ucNotifyState;
+	#endif
+
+	/* See the comments in FreeRTOS.h with the definition of
+	tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE. */
+	#if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */
+		uint8_t	ucStaticallyAllocated; 		/*< Set to pdTRUE if the task is a statically allocated to ensure no attempt is made to free the memory. */
+	#endif
+
+	#if( INCLUDE_xTaskAbortDelay == 1 )
+		uint8_t ucDelayAborted;
+	#endif
+
+	#if( configUSE_POSIX_ERRNO == 1 )
+		int iTaskErrno;
+	#endif
+
+} tskTCB;
+
+/* The old tskTCB name is maintained above then typedefed to the new TCB_t name
+below to enable the use of older kernel aware debuggers. */
+typedef tskTCB TCB_t;
+
+/*lint -save -e956 A manual analysis and inspection has been used to determine
+which static variables must be declared volatile. */
+PRIVILEGED_DATA TCB_t * volatile pxCurrentTCB = NULL;
+
+/* Lists for ready and blocked tasks. --------------------
+xDelayedTaskList1 and xDelayedTaskList2 could be move to function scople but
+doing so breaks some kernel aware debuggers and debuggers that rely on removing
+the static qualifier. */
+PRIVILEGED_DATA static List_t pxReadyTasksLists[ configMAX_PRIORITIES ];/*< Prioritised ready tasks. */
+PRIVILEGED_DATA static List_t xDelayedTaskList1;						/*< Delayed tasks. */
+PRIVILEGED_DATA static List_t xDelayedTaskList2;						/*< Delayed tasks (two lists are used - one for delays that have overflowed the current tick count. */
+PRIVILEGED_DATA static List_t * volatile pxDelayedTaskList;				/*< Points to the delayed task list currently being used. */
+PRIVILEGED_DATA static List_t * volatile pxOverflowDelayedTaskList;		/*< Points to the delayed task list currently being used to hold tasks that have overflowed the current tick count. */
+PRIVILEGED_DATA static List_t xPendingReadyList;						/*< Tasks that have been readied while the scheduler was suspended.  They will be moved to the ready list when the scheduler is resumed. */
+
+#if( INCLUDE_vTaskDelete == 1 )
+
+	PRIVILEGED_DATA static List_t xTasksWaitingTermination;				/*< Tasks that have been deleted - but their memory not yet freed. */
+	PRIVILEGED_DATA static volatile UBaseType_t uxDeletedTasksWaitingCleanUp = ( UBaseType_t ) 0U;
+
+#endif
+
+#if ( INCLUDE_vTaskSuspend == 1 )
+
+	PRIVILEGED_DATA static List_t xSuspendedTaskList;					/*< Tasks that are currently suspended. */
+
+#endif
+
+/* Global POSIX errno. Its value is changed upon context switching to match
+the errno of the currently running task. */
+#if ( configUSE_POSIX_ERRNO == 1 )
+	int FreeRTOS_errno = 0;
+#endif
+
+/* Other file private variables. --------------------------------*/
+PRIVILEGED_DATA static volatile UBaseType_t uxCurrentNumberOfTasks 	= ( UBaseType_t ) 0U;
+PRIVILEGED_DATA static volatile TickType_t xTickCount 				= ( TickType_t ) configINITIAL_TICK_COUNT;
+PRIVILEGED_DATA static volatile UBaseType_t uxTopReadyPriority 		= tskIDLE_PRIORITY;
+PRIVILEGED_DATA static volatile BaseType_t xSchedulerRunning 		= pdFALSE;
+PRIVILEGED_DATA static volatile TickType_t xPendedTicks 			= ( TickType_t ) 0U;
+PRIVILEGED_DATA static volatile BaseType_t xYieldPending 			= pdFALSE;
+PRIVILEGED_DATA static volatile BaseType_t xNumOfOverflows 			= ( BaseType_t ) 0;
+PRIVILEGED_DATA static UBaseType_t uxTaskNumber 					= ( UBaseType_t ) 0U;
+PRIVILEGED_DATA static volatile TickType_t xNextTaskUnblockTime		= ( TickType_t ) 0U; /* Initialised to portMAX_DELAY before the scheduler starts. */
+PRIVILEGED_DATA static TaskHandle_t xIdleTaskHandle					= NULL;			/*< Holds the handle of the idle task.  The idle task is created automatically when the scheduler is started. */
+
+/* Context switches are held pending while the scheduler is suspended.  Also,
+interrupts must not manipulate the xStateListItem of a TCB, or any of the
+lists the xStateListItem can be referenced from, if the scheduler is suspended.
+If an interrupt needs to unblock a task while the scheduler is suspended then it
+moves the task's event list item into the xPendingReadyList, ready for the
+kernel to move the task from the pending ready list into the real ready list
+when the scheduler is unsuspended.  The pending ready list itself can only be
+accessed from a critical section. */
+PRIVILEGED_DATA static volatile UBaseType_t uxSchedulerSuspended	= ( UBaseType_t ) pdFALSE;
+
+#if ( configGENERATE_RUN_TIME_STATS == 1 )
+
+	/* Do not move these variables to function scope as doing so prevents the
+	code working with debuggers that need to remove the static qualifier. */
+	PRIVILEGED_DATA static uint32_t ulTaskSwitchedInTime = 0UL;	/*< Holds the value of a timer/counter the last time a task was switched in. */
+	PRIVILEGED_DATA static uint32_t ulTotalRunTime = 0UL;		/*< Holds the total amount of execution time as defined by the run time counter clock. */
+
+#endif
+
+/*lint -restore */
+
+/*-----------------------------------------------------------*/
+
+/* Callback function prototypes. --------------------------*/
+#if(  configCHECK_FOR_STACK_OVERFLOW > 0 )
+
+	extern void vApplicationStackOverflowHook( TaskHandle_t xTask, char *pcTaskName );
+
+#endif
+
+#if( configUSE_TICK_HOOK > 0 )
+
+	extern void vApplicationTickHook( void ); /*lint !e526 Symbol not defined as it is an application callback. */
+
+#endif
+
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+
+	extern void vApplicationGetIdleTaskMemory( StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize ); /*lint !e526 Symbol not defined as it is an application callback. */
+
+#endif
+
+/* File private functions. --------------------------------*/
+
+/**
+ * Utility task that simply returns pdTRUE if the task referenced by xTask is
+ * currently in the Suspended state, or pdFALSE if the task referenced by xTask
+ * is in any other state.
+ */
+#if ( INCLUDE_vTaskSuspend == 1 )
+
+	static BaseType_t prvTaskIsTaskSuspended( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+
+#endif /* INCLUDE_vTaskSuspend */
+
+/*
+ * Utility to ready all the lists used by the scheduler.  This is called
+ * automatically upon the creation of the first task.
+ */
+static void prvInitialiseTaskLists( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * The idle task, which as all tasks is implemented as a never ending loop.
+ * The idle task is automatically created and added to the ready lists upon
+ * creation of the first user task.
+ *
+ * The portTASK_FUNCTION_PROTO() macro is used to allow port/compiler specific
+ * language extensions.  The equivalent prototype for this function is:
+ *
+ * void prvIdleTask( void *pvParameters );
+ *
+ */
+static portTASK_FUNCTION_PROTO( prvIdleTask, pvParameters );
+
+/*
+ * Utility to free all memory allocated by the scheduler to hold a TCB,
+ * including the stack pointed to by the TCB.
+ *
+ * This does not free memory allocated by the task itself (i.e. memory
+ * allocated by calls to pvPortMalloc from within the tasks application code).
+ */
+#if ( INCLUDE_vTaskDelete == 1 )
+
+	static void prvDeleteTCB( TCB_t *pxTCB ) PRIVILEGED_FUNCTION;
+
+#endif
+
+/*
+ * Used only by the idle task.  This checks to see if anything has been placed
+ * in the list of tasks waiting to be deleted.  If so the task is cleaned up
+ * and its TCB deleted.
+ */
+static void prvCheckTasksWaitingTermination( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * The currently executing task is entering the Blocked state.  Add the task to
+ * either the current or the overflow delayed task list.
+ */
+static void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait, const BaseType_t xCanBlockIndefinitely ) PRIVILEGED_FUNCTION;
+
+/*
+ * Fills an TaskStatus_t structure with information on each task that is
+ * referenced from the pxList list (which may be a ready list, a delayed list,
+ * a suspended list, etc.).
+ *
+ * THIS FUNCTION IS INTENDED FOR DEBUGGING ONLY, AND SHOULD NOT BE CALLED FROM
+ * NORMAL APPLICATION CODE.
+ */
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	static UBaseType_t prvListTasksWithinSingleList( TaskStatus_t *pxTaskStatusArray, List_t *pxList, eTaskState eState ) PRIVILEGED_FUNCTION;
+
+#endif
+
+/*
+ * Searches pxList for a task with name pcNameToQuery - returning a handle to
+ * the task if it is found, or NULL if the task is not found.
+ */
+#if ( INCLUDE_xTaskGetHandle == 1 )
+
+	static TCB_t *prvSearchForNameWithinSingleList( List_t *pxList, const char pcNameToQuery[] ) PRIVILEGED_FUNCTION;
+
+#endif
+
+/*
+ * When a task is created, the stack of the task is filled with a known value.
+ * This function determines the 'high water mark' of the task stack by
+ * determining how much of the stack remains at the original preset value.
+ */
+#if ( ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) )
+
+	static configSTACK_DEPTH_TYPE prvTaskCheckFreeStackSpace( const uint8_t * pucStackByte ) PRIVILEGED_FUNCTION;
+
+#endif
+
+/*
+ * Return the amount of time, in ticks, that will pass before the kernel will
+ * next move a task from the Blocked state to the Running state.
+ *
+ * This conditional compilation should use inequality to 0, not equality to 1.
+ * This is to ensure portSUPPRESS_TICKS_AND_SLEEP() can be called when user
+ * defined low power mode implementations require configUSE_TICKLESS_IDLE to be
+ * set to a value other than 1.
+ */
+#if ( configUSE_TICKLESS_IDLE != 0 )
+
+	static TickType_t prvGetExpectedIdleTime( void ) PRIVILEGED_FUNCTION;
+
+#endif
+
+/*
+ * Set xNextTaskUnblockTime to the time at which the next Blocked state task
+ * will exit the Blocked state.
+ */
+static void prvResetNextTaskUnblockTime( void );
+
+#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) )
+
+	/*
+	 * Helper function used to pad task names with spaces when printing out
+	 * human readable tables of task information.
+	 */
+	static char *prvWriteNameToBuffer( char *pcBuffer, const char *pcTaskName ) PRIVILEGED_FUNCTION;
+
+#endif
+
+/*
+ * Called after a Task_t structure has been allocated either statically or
+ * dynamically to fill in the structure's members.
+ */
+static void prvInitialiseNewTask( 	TaskFunction_t pxTaskCode,
+									const char * const pcName, 		/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+									const uint32_t ulStackDepth,
+									void * const pvParameters,
+									UBaseType_t uxPriority,
+									TaskHandle_t * const pxCreatedTask,
+									TCB_t *pxNewTCB,
+									const MemoryRegion_t * const xRegions ) PRIVILEGED_FUNCTION;
+
+/*
+ * Called after a new task has been created and initialised to place the task
+ * under the control of the scheduler.
+ */
+static void prvAddNewTaskToReadyList( TCB_t *pxNewTCB ) PRIVILEGED_FUNCTION;
+
+/*
+ * freertos_tasks_c_additions_init() should only be called if the user definable
+ * macro FREERTOS_TASKS_C_ADDITIONS_INIT() is defined, as that is the only macro
+ * called by the function.
+ */
+#ifdef FREERTOS_TASKS_C_ADDITIONS_INIT
+
+	static void freertos_tasks_c_additions_init( void ) PRIVILEGED_FUNCTION;
+
+#endif
+
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+
+	TaskHandle_t xTaskCreateStatic(	TaskFunction_t pxTaskCode,
+									const char * const pcName,		/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+									const uint32_t ulStackDepth,
+									void * const pvParameters,
+									UBaseType_t uxPriority,
+									StackType_t * const puxStackBuffer,
+									StaticTask_t * const pxTaskBuffer )
+	{
+	TCB_t *pxNewTCB;
+	TaskHandle_t xReturn;
+
+		configASSERT( puxStackBuffer != NULL );
+		configASSERT( pxTaskBuffer != NULL );
+
+		#if( configASSERT_DEFINED == 1 )
+		{
+			/* Sanity check that the size of the structure used to declare a
+			variable of type StaticTask_t equals the size of the real task
+			structure. */
+			volatile size_t xSize = sizeof( StaticTask_t );
+			configASSERT( xSize == sizeof( TCB_t ) );
+			( void ) xSize; /* Prevent lint warning when configASSERT() is not used. */
+		}
+		#endif /* configASSERT_DEFINED */
+
+
+		if( ( pxTaskBuffer != NULL ) && ( puxStackBuffer != NULL ) )
+		{
+			/* The memory used for the task's TCB and stack are passed into this
+			function - use them. */
+			pxNewTCB = ( TCB_t * ) pxTaskBuffer; /*lint !e740 !e9087 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */
+			pxNewTCB->pxStack = ( StackType_t * ) puxStackBuffer;
+
+			#if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */
+			{
+				/* Tasks can be created statically or dynamically, so note this
+				task was created statically in case the task is later deleted. */
+				pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_AND_TCB;
+			}
+			#endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */
+
+			prvInitialiseNewTask( pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, &xReturn, pxNewTCB, NULL );
+			prvAddNewTaskToReadyList( pxNewTCB );
+		}
+		else
+		{
+			xReturn = NULL;
+		}
+
+		return xReturn;
+	}
+
+#endif /* SUPPORT_STATIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+#if( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
+
+	BaseType_t xTaskCreateRestrictedStatic( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask )
+	{
+	TCB_t *pxNewTCB;
+	BaseType_t xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;
+
+		configASSERT( pxTaskDefinition->puxStackBuffer != NULL );
+		configASSERT( pxTaskDefinition->pxTaskBuffer != NULL );
+
+		if( ( pxTaskDefinition->puxStackBuffer != NULL ) && ( pxTaskDefinition->pxTaskBuffer != NULL ) )
+		{
+			/* Allocate space for the TCB.  Where the memory comes from depends
+			on the implementation of the port malloc function and whether or
+			not static allocation is being used. */
+			pxNewTCB = ( TCB_t * ) pxTaskDefinition->pxTaskBuffer;
+
+			/* Store the stack location in the TCB. */
+			pxNewTCB->pxStack = pxTaskDefinition->puxStackBuffer;
+
+			#if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 )
+			{
+				/* Tasks can be created statically or dynamically, so note this
+				task was created statically in case the task is later deleted. */
+				pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_AND_TCB;
+			}
+			#endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */
+
+			prvInitialiseNewTask(	pxTaskDefinition->pvTaskCode,
+									pxTaskDefinition->pcName,
+									( uint32_t ) pxTaskDefinition->usStackDepth,
+									pxTaskDefinition->pvParameters,
+									pxTaskDefinition->uxPriority,
+									pxCreatedTask, pxNewTCB,
+									pxTaskDefinition->xRegions );
+
+			prvAddNewTaskToReadyList( pxNewTCB );
+			xReturn = pdPASS;
+		}
+
+		return xReturn;
+	}
+
+#endif /* ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) */
+/*-----------------------------------------------------------*/
+
+#if( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+
+	BaseType_t xTaskCreateRestricted( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask )
+	{
+	TCB_t *pxNewTCB;
+	BaseType_t xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;
+
+		configASSERT( pxTaskDefinition->puxStackBuffer );
+
+		if( pxTaskDefinition->puxStackBuffer != NULL )
+		{
+			/* Allocate space for the TCB.  Where the memory comes from depends
+			on the implementation of the port malloc function and whether or
+			not static allocation is being used. */
+			pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) );
+
+			if( pxNewTCB != NULL )
+			{
+				/* Store the stack location in the TCB. */
+				pxNewTCB->pxStack = pxTaskDefinition->puxStackBuffer;
+
+				#if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 )
+				{
+					/* Tasks can be created statically or dynamically, so note
+					this task had a statically allocated stack in case it is
+					later deleted.  The TCB was allocated dynamically. */
+					pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_ONLY;
+				}
+				#endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */
+
+				prvInitialiseNewTask(	pxTaskDefinition->pvTaskCode,
+										pxTaskDefinition->pcName,
+										( uint32_t ) pxTaskDefinition->usStackDepth,
+										pxTaskDefinition->pvParameters,
+										pxTaskDefinition->uxPriority,
+										pxCreatedTask, pxNewTCB,
+										pxTaskDefinition->xRegions );
+
+				prvAddNewTaskToReadyList( pxNewTCB );
+				xReturn = pdPASS;
+			}
+		}
+
+		return xReturn;
+	}
+
+#endif /* portUSING_MPU_WRAPPERS */
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+
+	BaseType_t xTaskCreate(	TaskFunction_t pxTaskCode,
+							const char * const pcName,		/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+							const configSTACK_DEPTH_TYPE usStackDepth,
+							void * const pvParameters,
+							UBaseType_t uxPriority,
+							TaskHandle_t * const pxCreatedTask )
+	{
+	TCB_t *pxNewTCB;
+	BaseType_t xReturn;
+
+		/* If the stack grows down then allocate the stack then the TCB so the stack
+		does not grow into the TCB.  Likewise if the stack grows up then allocate
+		the TCB then the stack. */
+		#if( portSTACK_GROWTH > 0 )
+		{
+			/* Allocate space for the TCB.  Where the memory comes from depends on
+			the implementation of the port malloc function and whether or not static
+			allocation is being used. */
+			pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) );
+
+			if( pxNewTCB != NULL )
+			{
+				/* Allocate space for the stack used by the task being created.
+				The base of the stack memory stored in the TCB so the task can
+				be deleted later if required. */
+				pxNewTCB->pxStack = ( StackType_t * ) pvPortMalloc( ( ( ( size_t ) usStackDepth ) * sizeof( StackType_t ) ) ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+
+				if( pxNewTCB->pxStack == NULL )
+				{
+					/* Could not allocate the stack.  Delete the allocated TCB. */
+					vPortFree( pxNewTCB );
+					pxNewTCB = NULL;
+				}
+			}
+		}
+		#else /* portSTACK_GROWTH */
+		{
+		StackType_t *pxStack;
+
+			/* Allocate space for the stack used by the task being created. */
+			pxStack = pvPortMalloc( ( ( ( size_t ) usStackDepth ) * sizeof( StackType_t ) ) ); /*lint !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack and this allocation is the stack. */
+
+			if( pxStack != NULL )
+			{
+				/* Allocate space for the TCB. */
+				pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) ); /*lint !e9087 !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack, and the first member of TCB_t is always a pointer to the task's stack. */
+
+				if( pxNewTCB != NULL )
+				{
+					/* Store the stack location in the TCB. */
+					pxNewTCB->pxStack = pxStack;
+				}
+				else
+				{
+					/* The stack cannot be used as the TCB was not created.  Free
+					it again. */
+					vPortFree( pxStack );
+				}
+			}
+			else
+			{
+				pxNewTCB = NULL;
+			}
+		}
+		#endif /* portSTACK_GROWTH */
+
+		if( pxNewTCB != NULL )
+		{
+			#if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e9029 !e731 Macro has been consolidated for readability reasons. */
+			{
+				/* Tasks can be created statically or dynamically, so note this
+				task was created dynamically in case it is later deleted. */
+				pxNewTCB->ucStaticallyAllocated = tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB;
+			}
+			#endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */
+
+			prvInitialiseNewTask( pxTaskCode, pcName, ( uint32_t ) usStackDepth, pvParameters, uxPriority, pxCreatedTask, pxNewTCB, NULL );
+			prvAddNewTaskToReadyList( pxNewTCB );
+			xReturn = pdPASS;
+		}
+		else
+		{
+			xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;
+		}
+
+		return xReturn;
+	}
+
+#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+static void prvInitialiseNewTask( 	TaskFunction_t pxTaskCode,
+									const char * const pcName,		/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+									const uint32_t ulStackDepth,
+									void * const pvParameters,
+									UBaseType_t uxPriority,
+									TaskHandle_t * const pxCreatedTask,
+									TCB_t *pxNewTCB,
+									const MemoryRegion_t * const xRegions )
+{
+StackType_t *pxTopOfStack;
+UBaseType_t x;
+
+	#if( portUSING_MPU_WRAPPERS == 1 )
+		/* Should the task be created in privileged mode? */
+		BaseType_t xRunPrivileged;
+		if( ( uxPriority & portPRIVILEGE_BIT ) != 0U )
+		{
+			xRunPrivileged = pdTRUE;
+		}
+		else
+		{
+			xRunPrivileged = pdFALSE;
+		}
+		uxPriority &= ~portPRIVILEGE_BIT;
+	#endif /* portUSING_MPU_WRAPPERS == 1 */
+
+	/* Avoid dependency on memset() if it is not required. */
+	#if( tskSET_NEW_STACKS_TO_KNOWN_VALUE == 1 )
+	{
+		/* Fill the stack with a known value to assist debugging. */
+		( void ) memset( pxNewTCB->pxStack, ( int ) tskSTACK_FILL_BYTE, ( size_t ) ulStackDepth * sizeof( StackType_t ) );
+	}
+	#endif /* tskSET_NEW_STACKS_TO_KNOWN_VALUE */
+
+	/* Calculate the top of stack address.  This depends on whether the stack
+	grows from high memory to low (as per the 80x86) or vice versa.
+	portSTACK_GROWTH is used to make the result positive or negative as required
+	by the port. */
+	#if( portSTACK_GROWTH < 0 )
+	{
+		pxTopOfStack = &( pxNewTCB->pxStack[ ulStackDepth - ( uint32_t ) 1 ] );
+		pxTopOfStack = ( StackType_t * ) ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) ); /*lint !e923 !e9033 !e9078 MISRA exception.  Avoiding casts between pointers and integers is not practical.  Size differences accounted for using portPOINTER_SIZE_TYPE type.  Checked by assert(). */
+
+		/* Check the alignment of the calculated top of stack is correct. */
+		configASSERT( ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack & ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) == 0UL ) );
+
+		#if( configRECORD_STACK_HIGH_ADDRESS == 1 )
+		{
+			/* Also record the stack's high address, which may assist
+			debugging. */
+			pxNewTCB->pxEndOfStack = pxTopOfStack;
+		}
+		#endif /* configRECORD_STACK_HIGH_ADDRESS */
+	}
+	#else /* portSTACK_GROWTH */
+	{
+		pxTopOfStack = pxNewTCB->pxStack;
+
+		/* Check the alignment of the stack buffer is correct. */
+		configASSERT( ( ( ( portPOINTER_SIZE_TYPE ) pxNewTCB->pxStack & ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) == 0UL ) );
+
+		/* The other extreme of the stack space is required if stack checking is
+		performed. */
+		pxNewTCB->pxEndOfStack = pxNewTCB->pxStack + ( ulStackDepth - ( uint32_t ) 1 );
+	}
+	#endif /* portSTACK_GROWTH */
+
+	/* Store the task name in the TCB. */
+	if( pcName != NULL )
+	{
+		for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ )
+		{
+			pxNewTCB->pcTaskName[ x ] = pcName[ x ];
+
+			/* Don't copy all configMAX_TASK_NAME_LEN if the string is shorter than
+			configMAX_TASK_NAME_LEN characters just in case the memory after the
+			string is not accessible (extremely unlikely). */
+			if( pcName[ x ] == ( char ) 0x00 )
+			{
+				break;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+
+		/* Ensure the name string is terminated in the case that the string length
+		was greater or equal to configMAX_TASK_NAME_LEN. */
+		pxNewTCB->pcTaskName[ configMAX_TASK_NAME_LEN - 1 ] = '\0';
+	}
+	else
+	{
+		/* The task has not been given a name, so just ensure there is a NULL
+		terminator when it is read out. */
+		pxNewTCB->pcTaskName[ 0 ] = 0x00;
+	}
+
+	/* This is used as an array index so must ensure it's not too large.  First
+	remove the privilege bit if one is present. */
+	if( uxPriority >= ( UBaseType_t ) configMAX_PRIORITIES )
+	{
+		uxPriority = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) 1U;
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	pxNewTCB->uxPriority = uxPriority;
+	#if ( configUSE_MUTEXES == 1 )
+	{
+		pxNewTCB->uxBasePriority = uxPriority;
+		pxNewTCB->uxMutexesHeld = 0;
+	}
+	#endif /* configUSE_MUTEXES */
+
+	vListInitialiseItem( &( pxNewTCB->xStateListItem ) );
+	vListInitialiseItem( &( pxNewTCB->xEventListItem ) );
+
+	/* Set the pxNewTCB as a link back from the ListItem_t.  This is so we can get
+	back to	the containing TCB from a generic item in a list. */
+	listSET_LIST_ITEM_OWNER( &( pxNewTCB->xStateListItem ), pxNewTCB );
+
+	/* Event lists are always in priority order. */
+	listSET_LIST_ITEM_VALUE( &( pxNewTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+	listSET_LIST_ITEM_OWNER( &( pxNewTCB->xEventListItem ), pxNewTCB );
+
+	#if ( portCRITICAL_NESTING_IN_TCB == 1 )
+	{
+		pxNewTCB->uxCriticalNesting = ( UBaseType_t ) 0U;
+	}
+	#endif /* portCRITICAL_NESTING_IN_TCB */
+
+	#if ( configUSE_APPLICATION_TASK_TAG == 1 )
+	{
+		pxNewTCB->pxTaskTag = NULL;
+	}
+	#endif /* configUSE_APPLICATION_TASK_TAG */
+
+	#if ( configGENERATE_RUN_TIME_STATS == 1 )
+	{
+		pxNewTCB->ulRunTimeCounter = 0UL;
+	}
+	#endif /* configGENERATE_RUN_TIME_STATS */
+
+	#if ( portUSING_MPU_WRAPPERS == 1 )
+	{
+		vPortStoreTaskMPUSettings( &( pxNewTCB->xMPUSettings ), xRegions, pxNewTCB->pxStack, ulStackDepth );
+	}
+	#else
+	{
+		/* Avoid compiler warning about unreferenced parameter. */
+		( void ) xRegions;
+	}
+	#endif
+
+	#if( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
+	{
+		for( x = 0; x < ( UBaseType_t ) configNUM_THREAD_LOCAL_STORAGE_POINTERS; x++ )
+		{
+			pxNewTCB->pvThreadLocalStoragePointers[ x ] = NULL;
+		}
+	}
+	#endif
+
+	#if ( configUSE_TASK_NOTIFICATIONS == 1 )
+	{
+		pxNewTCB->ulNotifiedValue = 0;
+		pxNewTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION;
+	}
+	#endif
+
+	#if ( configUSE_NEWLIB_REENTRANT == 1 )
+	{
+		/* Initialise this task's Newlib reent structure.
+		See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html
+		for additional information. */
+		_REENT_INIT_PTR( ( &( pxNewTCB->xNewLib_reent ) ) );
+	}
+	#endif
+
+	#if( INCLUDE_xTaskAbortDelay == 1 )
+	{
+		pxNewTCB->ucDelayAborted = pdFALSE;
+	}
+	#endif
+
+	/* Initialize the TCB stack to look as if the task was already running,
+	but had been interrupted by the scheduler.  The return address is set
+	to the start of the task function. Once the stack has been initialised
+	the top of stack variable is updated. */
+	#if( portUSING_MPU_WRAPPERS == 1 )
+	{
+		/* If the port has capability to detect stack overflow,
+		pass the stack end address to the stack initialization
+		function as well. */
+		#if( portHAS_STACK_OVERFLOW_CHECKING == 1 )
+		{
+			#if( portSTACK_GROWTH < 0 )
+			{
+				pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxNewTCB->pxStack, pxTaskCode, pvParameters, xRunPrivileged );
+			}
+			#else /* portSTACK_GROWTH */
+			{
+				pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxNewTCB->pxEndOfStack, pxTaskCode, pvParameters, xRunPrivileged );
+			}
+			#endif /* portSTACK_GROWTH */
+		}
+		#else /* portHAS_STACK_OVERFLOW_CHECKING */
+		{
+			pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters, xRunPrivileged );
+		}
+		#endif /* portHAS_STACK_OVERFLOW_CHECKING */
+	}
+	#else /* portUSING_MPU_WRAPPERS */
+	{
+		/* If the port has capability to detect stack overflow,
+		pass the stack end address to the stack initialization
+		function as well. */
+		#if( portHAS_STACK_OVERFLOW_CHECKING == 1 )
+		{
+			#if( portSTACK_GROWTH < 0 )
+			{
+				pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxNewTCB->pxStack, pxTaskCode, pvParameters );
+			}
+			#else /* portSTACK_GROWTH */
+			{
+				pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxNewTCB->pxEndOfStack, pxTaskCode, pvParameters );
+			}
+			#endif /* portSTACK_GROWTH */
+		}
+		#else /* portHAS_STACK_OVERFLOW_CHECKING */
+		{
+			pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters );
+		}
+		#endif /* portHAS_STACK_OVERFLOW_CHECKING */
+	}
+	#endif /* portUSING_MPU_WRAPPERS */
+
+	if( pxCreatedTask != NULL )
+	{
+		/* Pass the handle out in an anonymous way.  The handle can be used to
+		change the created task's priority, delete the created task, etc.*/
+		*pxCreatedTask = ( TaskHandle_t ) pxNewTCB;
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvAddNewTaskToReadyList( TCB_t *pxNewTCB )
+{
+	/* Ensure interrupts don't access the task lists while the lists are being
+	updated. */
+	taskENTER_CRITICAL();
+	{
+		uxCurrentNumberOfTasks++;
+		if( pxCurrentTCB == NULL )
+		{
+			/* There are no other tasks, or all the other tasks are in
+			the suspended state - make this the current task. */
+			pxCurrentTCB = pxNewTCB;
+
+			if( uxCurrentNumberOfTasks == ( UBaseType_t ) 1 )
+			{
+				/* This is the first task to be created so do the preliminary
+				initialisation required.  We will not recover if this call
+				fails, but we will report the failure. */
+				prvInitialiseTaskLists();
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			/* If the scheduler is not already running, make this task the
+			current task if it is the highest priority task to be created
+			so far. */
+			if( xSchedulerRunning == pdFALSE )
+			{
+				if( pxCurrentTCB->uxPriority <= pxNewTCB->uxPriority )
+				{
+					pxCurrentTCB = pxNewTCB;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+
+		uxTaskNumber++;
+
+		#if ( configUSE_TRACE_FACILITY == 1 )
+		{
+			/* Add a counter into the TCB for tracing only. */
+			pxNewTCB->uxTCBNumber = uxTaskNumber;
+		}
+		#endif /* configUSE_TRACE_FACILITY */
+		traceTASK_CREATE( pxNewTCB );
+
+		prvAddTaskToReadyList( pxNewTCB );
+
+		portSETUP_TCB( pxNewTCB );
+	}
+	taskEXIT_CRITICAL();
+
+	if( xSchedulerRunning != pdFALSE )
+	{
+		/* If the created task is of a higher priority than the current task
+		then it should run now. */
+		if( pxCurrentTCB->uxPriority < pxNewTCB->uxPriority )
+		{
+			taskYIELD_IF_USING_PREEMPTION();
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+}
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskDelete == 1 )
+
+	void vTaskDelete( TaskHandle_t xTaskToDelete )
+	{
+	TCB_t *pxTCB;
+
+		taskENTER_CRITICAL();
+		{
+			/* If null is passed in here then it is the calling task that is
+			being deleted. */
+			pxTCB = prvGetTCBFromHandle( xTaskToDelete );
+
+			/* Remove task from the ready/delayed list. */
+			if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
+			{
+				taskRESET_READY_PRIORITY( pxTCB->uxPriority );
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+
+			/* Is the task waiting on an event also? */
+			if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )
+			{
+				( void ) uxListRemove( &( pxTCB->xEventListItem ) );
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+
+			/* Increment the uxTaskNumber also so kernel aware debuggers can
+			detect that the task lists need re-generating.  This is done before
+			portPRE_TASK_DELETE_HOOK() as in the Windows port that macro will
+			not return. */
+			uxTaskNumber++;
+
+			if( pxTCB == pxCurrentTCB )
+			{
+				/* A task is deleting itself.  This cannot complete within the
+				task itself, as a context switch to another task is required.
+				Place the task in the termination list.  The idle task will
+				check the termination list and free up any memory allocated by
+				the scheduler for the TCB and stack of the deleted task. */
+				vListInsertEnd( &xTasksWaitingTermination, &( pxTCB->xStateListItem ) );
+
+				/* Increment the ucTasksDeleted variable so the idle task knows
+				there is a task that has been deleted and that it should therefore
+				check the xTasksWaitingTermination list. */
+				++uxDeletedTasksWaitingCleanUp;
+
+				/* Call the delete hook before portPRE_TASK_DELETE_HOOK() as
+				portPRE_TASK_DELETE_HOOK() does not return in the Win32 port. */
+				traceTASK_DELETE( pxTCB );
+
+				/* The pre-delete hook is primarily for the Windows simulator,
+				in which Windows specific clean up operations are performed,
+				after which it is not possible to yield away from this task -
+				hence xYieldPending is used to latch that a context switch is
+				required. */
+				portPRE_TASK_DELETE_HOOK( pxTCB, &xYieldPending );
+			}
+			else
+			{
+				--uxCurrentNumberOfTasks;
+				traceTASK_DELETE( pxTCB );
+				prvDeleteTCB( pxTCB );
+
+				/* Reset the next expected unblock time in case it referred to
+				the task that has just been deleted. */
+				prvResetNextTaskUnblockTime();
+			}
+		}
+		taskEXIT_CRITICAL();
+
+		/* Force a reschedule if it is the currently running task that has just
+		been deleted. */
+		if( xSchedulerRunning != pdFALSE )
+		{
+			if( pxTCB == pxCurrentTCB )
+			{
+				configASSERT( uxSchedulerSuspended == 0 );
+				portYIELD_WITHIN_API();
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+	}
+
+#endif /* INCLUDE_vTaskDelete */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskDelayUntil == 1 )
+
+	void vTaskDelayUntil( TickType_t * const pxPreviousWakeTime, const TickType_t xTimeIncrement )
+	{
+	TickType_t xTimeToWake;
+	BaseType_t xAlreadyYielded, xShouldDelay = pdFALSE;
+
+		configASSERT( pxPreviousWakeTime );
+		configASSERT( ( xTimeIncrement > 0U ) );
+		configASSERT( uxSchedulerSuspended == 0 );
+
+		vTaskSuspendAll();
+		{
+			/* Minor optimisation.  The tick count cannot change in this
+			block. */
+			const TickType_t xConstTickCount = xTickCount;
+
+			/* Generate the tick time at which the task wants to wake. */
+			xTimeToWake = *pxPreviousWakeTime + xTimeIncrement;
+
+			if( xConstTickCount < *pxPreviousWakeTime )
+			{
+				/* The tick count has overflowed since this function was
+				lasted called.  In this case the only time we should ever
+				actually delay is if the wake time has also	overflowed,
+				and the wake time is greater than the tick time.  When this
+				is the case it is as if neither time had overflowed. */
+				if( ( xTimeToWake < *pxPreviousWakeTime ) && ( xTimeToWake > xConstTickCount ) )
+				{
+					xShouldDelay = pdTRUE;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				/* The tick time has not overflowed.  In this case we will
+				delay if either the wake time has overflowed, and/or the
+				tick time is less than the wake time. */
+				if( ( xTimeToWake < *pxPreviousWakeTime ) || ( xTimeToWake > xConstTickCount ) )
+				{
+					xShouldDelay = pdTRUE;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+
+			/* Update the wake time ready for the next call. */
+			*pxPreviousWakeTime = xTimeToWake;
+
+			if( xShouldDelay != pdFALSE )
+			{
+				traceTASK_DELAY_UNTIL( xTimeToWake );
+
+				/* prvAddCurrentTaskToDelayedList() needs the block time, not
+				the time to wake, so subtract the current tick count. */
+				prvAddCurrentTaskToDelayedList( xTimeToWake - xConstTickCount, pdFALSE );
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		xAlreadyYielded = xTaskResumeAll();
+
+		/* Force a reschedule if xTaskResumeAll has not already done so, we may
+		have put ourselves to sleep. */
+		if( xAlreadyYielded == pdFALSE )
+		{
+			portYIELD_WITHIN_API();
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+
+#endif /* INCLUDE_vTaskDelayUntil */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskDelay == 1 )
+
+	void vTaskDelay( const TickType_t xTicksToDelay )
+	{
+	BaseType_t xAlreadyYielded = pdFALSE;
+
+		/* A delay time of zero just forces a reschedule. */
+		if( xTicksToDelay > ( TickType_t ) 0U )
+		{
+			configASSERT( uxSchedulerSuspended == 0 );
+			vTaskSuspendAll();
+			{
+				traceTASK_DELAY();
+
+				/* A task that is removed from the event list while the
+				scheduler is suspended will not get placed in the ready
+				list or removed from the blocked list until the scheduler
+				is resumed.
+
+				This task cannot be in an event list as it is the currently
+				executing task. */
+				prvAddCurrentTaskToDelayedList( xTicksToDelay, pdFALSE );
+			}
+			xAlreadyYielded = xTaskResumeAll();
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		/* Force a reschedule if xTaskResumeAll has not already done so, we may
+		have put ourselves to sleep. */
+		if( xAlreadyYielded == pdFALSE )
+		{
+			portYIELD_WITHIN_API();
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+
+#endif /* INCLUDE_vTaskDelay */
+/*-----------------------------------------------------------*/
+
+#if( ( INCLUDE_eTaskGetState == 1 ) || ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_xTaskAbortDelay == 1 ) )
+
+	eTaskState eTaskGetState( TaskHandle_t xTask )
+	{
+	eTaskState eReturn;
+	List_t const * pxStateList, *pxDelayedList, *pxOverflowedDelayedList;
+	const TCB_t * const pxTCB = xTask;
+
+		configASSERT( pxTCB );
+
+		if( pxTCB == pxCurrentTCB )
+		{
+			/* The task calling this function is querying its own state. */
+			eReturn = eRunning;
+		}
+		else
+		{
+			taskENTER_CRITICAL();
+			{
+				pxStateList = listLIST_ITEM_CONTAINER( &( pxTCB->xStateListItem ) );
+				pxDelayedList = pxDelayedTaskList;
+				pxOverflowedDelayedList = pxOverflowDelayedTaskList;
+			}
+			taskEXIT_CRITICAL();
+
+			if( ( pxStateList == pxDelayedList ) || ( pxStateList == pxOverflowedDelayedList ) )
+			{
+				/* The task being queried is referenced from one of the Blocked
+				lists. */
+				eReturn = eBlocked;
+			}
+
+			#if ( INCLUDE_vTaskSuspend == 1 )
+				else if( pxStateList == &xSuspendedTaskList )
+				{
+					/* The task being queried is referenced from the suspended
+					list.  Is it genuinely suspended or is it blocked
+					indefinitely? */
+					if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL )
+					{
+						#if( configUSE_TASK_NOTIFICATIONS == 1 )
+						{
+							/* The task does not appear on the event list item of
+							and of the RTOS objects, but could still be in the
+							blocked state if it is waiting on its notification
+							rather than waiting on an object. */
+							if( pxTCB->ucNotifyState == taskWAITING_NOTIFICATION )
+							{
+								eReturn = eBlocked;
+							}
+							else
+							{
+								eReturn = eSuspended;
+							}
+						}
+						#else
+						{
+							eReturn = eSuspended;
+						}
+						#endif
+					}
+					else
+					{
+						eReturn = eBlocked;
+					}
+				}
+			#endif
+
+			#if ( INCLUDE_vTaskDelete == 1 )
+				else if( ( pxStateList == &xTasksWaitingTermination ) || ( pxStateList == NULL ) )
+				{
+					/* The task being queried is referenced from the deleted
+					tasks list, or it is not referenced from any lists at
+					all. */
+					eReturn = eDeleted;
+				}
+			#endif
+
+			else /*lint !e525 Negative indentation is intended to make use of pre-processor clearer. */
+			{
+				/* If the task is not in any other state, it must be in the
+				Ready (including pending ready) state. */
+				eReturn = eReady;
+			}
+		}
+
+		return eReturn;
+	} /*lint !e818 xTask cannot be a pointer to const because it is a typedef. */
+
+#endif /* INCLUDE_eTaskGetState */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_uxTaskPriorityGet == 1 )
+
+	UBaseType_t uxTaskPriorityGet( const TaskHandle_t xTask )
+	{
+	TCB_t const *pxTCB;
+	UBaseType_t uxReturn;
+
+		taskENTER_CRITICAL();
+		{
+			/* If null is passed in here then it is the priority of the task
+			that called uxTaskPriorityGet() that is being queried. */
+			pxTCB = prvGetTCBFromHandle( xTask );
+			uxReturn = pxTCB->uxPriority;
+		}
+		taskEXIT_CRITICAL();
+
+		return uxReturn;
+	}
+
+#endif /* INCLUDE_uxTaskPriorityGet */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_uxTaskPriorityGet == 1 )
+
+	UBaseType_t uxTaskPriorityGetFromISR( const TaskHandle_t xTask )
+	{
+	TCB_t const *pxTCB;
+	UBaseType_t uxReturn, uxSavedInterruptState;
+
+		/* RTOS ports that support interrupt nesting have the concept of a
+		maximum	system call (or maximum API call) interrupt priority.
+		Interrupts that are	above the maximum system call priority are keep
+		permanently enabled, even when the RTOS kernel is in a critical section,
+		but cannot make any calls to FreeRTOS API functions.  If configASSERT()
+		is defined in FreeRTOSConfig.h then
+		portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
+		failure if a FreeRTOS API function is called from an interrupt that has
+		been assigned a priority above the configured maximum system call
+		priority.  Only FreeRTOS functions that end in FromISR can be called
+		from interrupts	that have been assigned a priority at or (logically)
+		below the maximum system call interrupt priority.  FreeRTOS maintains a
+		separate interrupt safe API to ensure interrupt entry is as fast and as
+		simple as possible.  More information (albeit Cortex-M specific) is
+		provided on the following link:
+		https://www.freertos.org/RTOS-Cortex-M3-M4.html */
+		portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+
+		uxSavedInterruptState = portSET_INTERRUPT_MASK_FROM_ISR();
+		{
+			/* If null is passed in here then it is the priority of the calling
+			task that is being queried. */
+			pxTCB = prvGetTCBFromHandle( xTask );
+			uxReturn = pxTCB->uxPriority;
+		}
+		portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptState );
+
+		return uxReturn;
+	}
+
+#endif /* INCLUDE_uxTaskPriorityGet */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskPrioritySet == 1 )
+
+	void vTaskPrioritySet( TaskHandle_t xTask, UBaseType_t uxNewPriority )
+	{
+	TCB_t *pxTCB;
+	UBaseType_t uxCurrentBasePriority, uxPriorityUsedOnEntry;
+	BaseType_t xYieldRequired = pdFALSE;
+
+		configASSERT( ( uxNewPriority < configMAX_PRIORITIES ) );
+
+		/* Ensure the new priority is valid. */
+		if( uxNewPriority >= ( UBaseType_t ) configMAX_PRIORITIES )
+		{
+			uxNewPriority = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) 1U;
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		taskENTER_CRITICAL();
+		{
+			/* If null is passed in here then it is the priority of the calling
+			task that is being changed. */
+			pxTCB = prvGetTCBFromHandle( xTask );
+
+			traceTASK_PRIORITY_SET( pxTCB, uxNewPriority );
+
+			#if ( configUSE_MUTEXES == 1 )
+			{
+				uxCurrentBasePriority = pxTCB->uxBasePriority;
+			}
+			#else
+			{
+				uxCurrentBasePriority = pxTCB->uxPriority;
+			}
+			#endif
+
+			if( uxCurrentBasePriority != uxNewPriority )
+			{
+				/* The priority change may have readied a task of higher
+				priority than the calling task. */
+				if( uxNewPriority > uxCurrentBasePriority )
+				{
+					if( pxTCB != pxCurrentTCB )
+					{
+						/* The priority of a task other than the currently
+						running task is being raised.  Is the priority being
+						raised above that of the running task? */
+						if( uxNewPriority >= pxCurrentTCB->uxPriority )
+						{
+							xYieldRequired = pdTRUE;
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+					else
+					{
+						/* The priority of the running task is being raised,
+						but the running task must already be the highest
+						priority task able to run so no yield is required. */
+					}
+				}
+				else if( pxTCB == pxCurrentTCB )
+				{
+					/* Setting the priority of the running task down means
+					there may now be another task of higher priority that
+					is ready to execute. */
+					xYieldRequired = pdTRUE;
+				}
+				else
+				{
+					/* Setting the priority of any other task down does not
+					require a yield as the running task must be above the
+					new priority of the task being modified. */
+				}
+
+				/* Remember the ready list the task might be referenced from
+				before its uxPriority member is changed so the
+				taskRESET_READY_PRIORITY() macro can function correctly. */
+				uxPriorityUsedOnEntry = pxTCB->uxPriority;
+
+				#if ( configUSE_MUTEXES == 1 )
+				{
+					/* Only change the priority being used if the task is not
+					currently using an inherited priority. */
+					if( pxTCB->uxBasePriority == pxTCB->uxPriority )
+					{
+						pxTCB->uxPriority = uxNewPriority;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+
+					/* The base priority gets set whatever. */
+					pxTCB->uxBasePriority = uxNewPriority;
+				}
+				#else
+				{
+					pxTCB->uxPriority = uxNewPriority;
+				}
+				#endif
+
+				/* Only reset the event list item value if the value is not
+				being used for anything else. */
+				if( ( listGET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL )
+				{
+					listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxNewPriority ) ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+
+				/* If the task is in the blocked or suspended list we need do
+				nothing more than change its priority variable. However, if
+				the task is in a ready list it needs to be removed and placed
+				in the list appropriate to its new priority. */
+				if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ uxPriorityUsedOnEntry ] ), &( pxTCB->xStateListItem ) ) != pdFALSE )
+				{
+					/* The task is currently in its ready list - remove before
+					adding it to it's new ready list.  As we are in a critical
+					section we can do this even if the scheduler is suspended. */
+					if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
+					{
+						/* It is known that the task is in its ready list so
+						there is no need to check again and the port level
+						reset macro can be called directly. */
+						portRESET_READY_PRIORITY( uxPriorityUsedOnEntry, uxTopReadyPriority );
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+					prvAddTaskToReadyList( pxTCB );
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+
+				if( xYieldRequired != pdFALSE )
+				{
+					taskYIELD_IF_USING_PREEMPTION();
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+
+				/* Remove compiler warning about unused variables when the port
+				optimised task selection is not being used. */
+				( void ) uxPriorityUsedOnEntry;
+			}
+		}
+		taskEXIT_CRITICAL();
+	}
+
+#endif /* INCLUDE_vTaskPrioritySet */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskSuspend == 1 )
+
+	void vTaskSuspend( TaskHandle_t xTaskToSuspend )
+	{
+	TCB_t *pxTCB;
+
+		taskENTER_CRITICAL();
+		{
+			/* If null is passed in here then it is the running task that is
+			being suspended. */
+			pxTCB = prvGetTCBFromHandle( xTaskToSuspend );
+
+			traceTASK_SUSPEND( pxTCB );
+
+			/* Remove task from the ready/delayed list and place in the
+			suspended list. */
+			if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
+			{
+				taskRESET_READY_PRIORITY( pxTCB->uxPriority );
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+
+			/* Is the task waiting on an event also? */
+			if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )
+			{
+				( void ) uxListRemove( &( pxTCB->xEventListItem ) );
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+
+			vListInsertEnd( &xSuspendedTaskList, &( pxTCB->xStateListItem ) );
+
+			#if( configUSE_TASK_NOTIFICATIONS == 1 )
+			{
+				if( pxTCB->ucNotifyState == taskWAITING_NOTIFICATION )
+				{
+					/* The task was blocked to wait for a notification, but is
+					now suspended, so no notification was received. */
+					pxTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION;
+				}
+			}
+			#endif
+		}
+		taskEXIT_CRITICAL();
+
+		if( xSchedulerRunning != pdFALSE )
+		{
+			/* Reset the next expected unblock time in case it referred to the
+			task that is now in the Suspended state. */
+			taskENTER_CRITICAL();
+			{
+				prvResetNextTaskUnblockTime();
+			}
+			taskEXIT_CRITICAL();
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		if( pxTCB == pxCurrentTCB )
+		{
+			if( xSchedulerRunning != pdFALSE )
+			{
+				/* The current task has just been suspended. */
+				configASSERT( uxSchedulerSuspended == 0 );
+				portYIELD_WITHIN_API();
+			}
+			else
+			{
+				/* The scheduler is not running, but the task that was pointed
+				to by pxCurrentTCB has just been suspended and pxCurrentTCB
+				must be adjusted to point to a different task. */
+				if( listCURRENT_LIST_LENGTH( &xSuspendedTaskList ) == uxCurrentNumberOfTasks ) /*lint !e931 Right has no side effect, just volatile. */
+				{
+					/* No other tasks are ready, so set pxCurrentTCB back to
+					NULL so when the next task is created pxCurrentTCB will
+					be set to point to it no matter what its relative priority
+					is. */
+					pxCurrentTCB = NULL;
+				}
+				else
+				{
+					vTaskSwitchContext();
+				}
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+
+#endif /* INCLUDE_vTaskSuspend */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskSuspend == 1 )
+
+	static BaseType_t prvTaskIsTaskSuspended( const TaskHandle_t xTask )
+	{
+	BaseType_t xReturn = pdFALSE;
+	const TCB_t * const pxTCB = xTask;
+
+		/* Accesses xPendingReadyList so must be called from a critical
+		section. */
+
+		/* It does not make sense to check if the calling task is suspended. */
+		configASSERT( xTask );
+
+		/* Is the task being resumed actually in the suspended list? */
+		if( listIS_CONTAINED_WITHIN( &xSuspendedTaskList, &( pxTCB->xStateListItem ) ) != pdFALSE )
+		{
+			/* Has the task already been resumed from within an ISR? */
+			if( listIS_CONTAINED_WITHIN( &xPendingReadyList, &( pxTCB->xEventListItem ) ) == pdFALSE )
+			{
+				/* Is it in the suspended list because it is in the	Suspended
+				state, or because is is blocked with no timeout? */
+				if( listIS_CONTAINED_WITHIN( NULL, &( pxTCB->xEventListItem ) ) != pdFALSE ) /*lint !e961.  The cast is only redundant when NULL is used. */
+				{
+					xReturn = pdTRUE;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		return xReturn;
+	} /*lint !e818 xTask cannot be a pointer to const because it is a typedef. */
+
+#endif /* INCLUDE_vTaskSuspend */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskSuspend == 1 )
+
+	void vTaskResume( TaskHandle_t xTaskToResume )
+	{
+	TCB_t * const pxTCB = xTaskToResume;
+
+		/* It does not make sense to resume the calling task. */
+		configASSERT( xTaskToResume );
+
+		/* The parameter cannot be NULL as it is impossible to resume the
+		currently executing task. */
+		if( ( pxTCB != pxCurrentTCB ) && ( pxTCB != NULL ) )
+		{
+			taskENTER_CRITICAL();
+			{
+				if( prvTaskIsTaskSuspended( pxTCB ) != pdFALSE )
+				{
+					traceTASK_RESUME( pxTCB );
+
+					/* The ready list can be accessed even if the scheduler is
+					suspended because this is inside a critical section. */
+					( void ) uxListRemove(  &( pxTCB->xStateListItem ) );
+					prvAddTaskToReadyList( pxTCB );
+
+					/* A higher priority task may have just been resumed. */
+					if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )
+					{
+						/* This yield may not cause the task just resumed to run,
+						but will leave the lists in the correct state for the
+						next yield. */
+						taskYIELD_IF_USING_PREEMPTION();
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			taskEXIT_CRITICAL();
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+
+#endif /* INCLUDE_vTaskSuspend */
+
+/*-----------------------------------------------------------*/
+
+#if ( ( INCLUDE_xTaskResumeFromISR == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) )
+
+	BaseType_t xTaskResumeFromISR( TaskHandle_t xTaskToResume )
+	{
+	BaseType_t xYieldRequired = pdFALSE;
+	TCB_t * const pxTCB = xTaskToResume;
+	UBaseType_t uxSavedInterruptStatus;
+
+		configASSERT( xTaskToResume );
+
+		/* RTOS ports that support interrupt nesting have the concept of a
+		maximum	system call (or maximum API call) interrupt priority.
+		Interrupts that are	above the maximum system call priority are keep
+		permanently enabled, even when the RTOS kernel is in a critical section,
+		but cannot make any calls to FreeRTOS API functions.  If configASSERT()
+		is defined in FreeRTOSConfig.h then
+		portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
+		failure if a FreeRTOS API function is called from an interrupt that has
+		been assigned a priority above the configured maximum system call
+		priority.  Only FreeRTOS functions that end in FromISR can be called
+		from interrupts	that have been assigned a priority at or (logically)
+		below the maximum system call interrupt priority.  FreeRTOS maintains a
+		separate interrupt safe API to ensure interrupt entry is as fast and as
+		simple as possible.  More information (albeit Cortex-M specific) is
+		provided on the following link:
+		https://www.freertos.org/RTOS-Cortex-M3-M4.html */
+		portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+
+		uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+		{
+			if( prvTaskIsTaskSuspended( pxTCB ) != pdFALSE )
+			{
+				traceTASK_RESUME_FROM_ISR( pxTCB );
+
+				/* Check the ready lists can be accessed. */
+				if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
+				{
+					/* Ready lists can be accessed so move the task from the
+					suspended list to the ready list directly. */
+					if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )
+					{
+						xYieldRequired = pdTRUE;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+
+					( void ) uxListRemove( &( pxTCB->xStateListItem ) );
+					prvAddTaskToReadyList( pxTCB );
+				}
+				else
+				{
+					/* The delayed or ready lists cannot be accessed so the task
+					is held in the pending ready list until the scheduler is
+					unsuspended. */
+					vListInsertEnd( &( xPendingReadyList ), &( pxTCB->xEventListItem ) );
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+		return xYieldRequired;
+	}
+
+#endif /* ( ( INCLUDE_xTaskResumeFromISR == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+void vTaskStartScheduler( void )
+{
+BaseType_t xReturn;
+
+	/* Add the idle task at the lowest priority. */
+	#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+	{
+		StaticTask_t *pxIdleTaskTCBBuffer = NULL;
+		StackType_t *pxIdleTaskStackBuffer = NULL;
+		uint32_t ulIdleTaskStackSize;
+
+		/* The Idle task is created using user provided RAM - obtain the
+		address of the RAM then create the idle task. */
+		vApplicationGetIdleTaskMemory( &pxIdleTaskTCBBuffer, &pxIdleTaskStackBuffer, &ulIdleTaskStackSize );
+		xIdleTaskHandle = xTaskCreateStatic(	prvIdleTask,
+												configIDLE_TASK_NAME,
+												ulIdleTaskStackSize,
+												( void * ) NULL, /*lint !e961.  The cast is not redundant for all compilers. */
+												portPRIVILEGE_BIT, /* In effect ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), but tskIDLE_PRIORITY is zero. */
+												pxIdleTaskStackBuffer,
+												pxIdleTaskTCBBuffer ); /*lint !e961 MISRA exception, justified as it is not a redundant explicit cast to all supported compilers. */
+
+		if( xIdleTaskHandle != NULL )
+		{
+			xReturn = pdPASS;
+		}
+		else
+		{
+			xReturn = pdFAIL;
+		}
+	}
+	#else
+	{
+		/* The Idle task is being created using dynamically allocated RAM. */
+		xReturn = xTaskCreate(	prvIdleTask,
+								configIDLE_TASK_NAME,
+								configMINIMAL_STACK_SIZE,
+								( void * ) NULL,
+								portPRIVILEGE_BIT, /* In effect ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), but tskIDLE_PRIORITY is zero. */
+								&xIdleTaskHandle ); /*lint !e961 MISRA exception, justified as it is not a redundant explicit cast to all supported compilers. */
+	}
+	#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+	#if ( configUSE_TIMERS == 1 )
+	{
+		if( xReturn == pdPASS )
+		{
+			xReturn = xTimerCreateTimerTask();
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	#endif /* configUSE_TIMERS */
+
+	if( xReturn == pdPASS )
+	{
+		/* freertos_tasks_c_additions_init() should only be called if the user
+		definable macro FREERTOS_TASKS_C_ADDITIONS_INIT() is defined, as that is
+		the only macro called by the function. */
+		#ifdef FREERTOS_TASKS_C_ADDITIONS_INIT
+		{
+			freertos_tasks_c_additions_init();
+		}
+		#endif
+
+		/* Interrupts are turned off here, to ensure a tick does not occur
+		before or during the call to xPortStartScheduler().  The stacks of
+		the created tasks contain a status word with interrupts switched on
+		so interrupts will automatically get re-enabled when the first task
+		starts to run. */
+		portDISABLE_INTERRUPTS();
+
+		#if ( configUSE_NEWLIB_REENTRANT == 1 )
+		{
+			/* Switch Newlib's _impure_ptr variable to point to the _reent
+			structure specific to the task that will run first.
+			See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html
+			for additional information. */
+			_impure_ptr = &( pxCurrentTCB->xNewLib_reent );
+		}
+		#endif /* configUSE_NEWLIB_REENTRANT */
+
+		xNextTaskUnblockTime = portMAX_DELAY;
+		xSchedulerRunning = pdTRUE;
+		xTickCount = ( TickType_t ) configINITIAL_TICK_COUNT;
+
+		/* If configGENERATE_RUN_TIME_STATS is defined then the following
+		macro must be defined to configure the timer/counter used to generate
+		the run time counter time base.   NOTE:  If configGENERATE_RUN_TIME_STATS
+		is set to 0 and the following line fails to build then ensure you do not
+		have portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() defined in your
+		FreeRTOSConfig.h file. */
+		portCONFIGURE_TIMER_FOR_RUN_TIME_STATS();
+
+		traceTASK_SWITCHED_IN();
+
+		/* Setting up the timer tick is hardware specific and thus in the
+		portable interface. */
+		if( xPortStartScheduler() != pdFALSE )
+		{
+			/* Should not reach here as if the scheduler is running the
+			function will not return. */
+		}
+		else
+		{
+			/* Should only reach here if a task calls xTaskEndScheduler(). */
+		}
+	}
+	else
+	{
+		/* This line will only be reached if the kernel could not be started,
+		because there was not enough FreeRTOS heap to create the idle task
+		or the timer task. */
+		configASSERT( xReturn != errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY );
+	}
+
+	/* Prevent compiler warnings if INCLUDE_xTaskGetIdleTaskHandle is set to 0,
+	meaning xIdleTaskHandle is not used anywhere else. */
+	( void ) xIdleTaskHandle;
+}
+/*-----------------------------------------------------------*/
+
+void vTaskEndScheduler( void )
+{
+	/* Stop the scheduler interrupts and call the portable scheduler end
+	routine so the original ISRs can be restored if necessary.  The port
+	layer must ensure interrupts enable	bit is left in the correct state. */
+	portDISABLE_INTERRUPTS();
+	xSchedulerRunning = pdFALSE;
+	vPortEndScheduler();
+}
+/*----------------------------------------------------------*/
+
+void vTaskSuspendAll( void )
+{
+	/* A critical section is not required as the variable is of type
+	BaseType_t.  Please read Richard Barry's reply in the following link to a
+	post in the FreeRTOS support forum before reporting this as a bug! -
+	http://goo.gl/wu4acr */
+
+	/* portSOFRWARE_BARRIER() is only implemented for emulated/simulated ports that
+	do not otherwise exhibit real time behaviour. */
+	portSOFTWARE_BARRIER();
+
+	/* The scheduler is suspended if uxSchedulerSuspended is non-zero.  An increment
+	is used to allow calls to vTaskSuspendAll() to nest. */
+	++uxSchedulerSuspended;
+
+	/* Enforces ordering for ports and optimised compilers that may otherwise place
+	the above increment elsewhere. */
+	portMEMORY_BARRIER();
+}
+/*----------------------------------------------------------*/
+
+#if ( configUSE_TICKLESS_IDLE != 0 )
+
+	static TickType_t prvGetExpectedIdleTime( void )
+	{
+	TickType_t xReturn;
+	UBaseType_t uxHigherPriorityReadyTasks = pdFALSE;
+
+		/* uxHigherPriorityReadyTasks takes care of the case where
+		configUSE_PREEMPTION is 0, so there may be tasks above the idle priority
+		task that are in the Ready state, even though the idle task is
+		running. */
+		#if( configUSE_PORT_OPTIMISED_TASK_SELECTION == 0 )
+		{
+			if( uxTopReadyPriority > tskIDLE_PRIORITY )
+			{
+				uxHigherPriorityReadyTasks = pdTRUE;
+			}
+		}
+		#else
+		{
+			const UBaseType_t uxLeastSignificantBit = ( UBaseType_t ) 0x01;
+
+			/* When port optimised task selection is used the uxTopReadyPriority
+			variable is used as a bit map.  If bits other than the least
+			significant bit are set then there are tasks that have a priority
+			above the idle priority that are in the Ready state.  This takes
+			care of the case where the co-operative scheduler is in use. */
+			if( uxTopReadyPriority > uxLeastSignificantBit )
+			{
+				uxHigherPriorityReadyTasks = pdTRUE;
+			}
+		}
+		#endif
+
+		if( pxCurrentTCB->uxPriority > tskIDLE_PRIORITY )
+		{
+			xReturn = 0;
+		}
+		else if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > 1 )
+		{
+			/* There are other idle priority tasks in the ready state.  If
+			time slicing is used then the very next tick interrupt must be
+			processed. */
+			xReturn = 0;
+		}
+		else if( uxHigherPriorityReadyTasks != pdFALSE )
+		{
+			/* There are tasks in the Ready state that have a priority above the
+			idle priority.  This path can only be reached if
+			configUSE_PREEMPTION is 0. */
+			xReturn = 0;
+		}
+		else
+		{
+			xReturn = xNextTaskUnblockTime - xTickCount;
+		}
+
+		return xReturn;
+	}
+
+#endif /* configUSE_TICKLESS_IDLE */
+/*----------------------------------------------------------*/
+
+BaseType_t xTaskResumeAll( void )
+{
+TCB_t *pxTCB = NULL;
+BaseType_t xAlreadyYielded = pdFALSE;
+
+	/* If uxSchedulerSuspended is zero then this function does not match a
+	previous call to vTaskSuspendAll(). */
+	configASSERT( uxSchedulerSuspended );
+
+	/* It is possible that an ISR caused a task to be removed from an event
+	list while the scheduler was suspended.  If this was the case then the
+	removed task will have been added to the xPendingReadyList.  Once the
+	scheduler has been resumed it is safe to move all the pending ready
+	tasks from this list into their appropriate ready list. */
+	taskENTER_CRITICAL();
+	{
+		--uxSchedulerSuspended;
+
+		if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
+		{
+			if( uxCurrentNumberOfTasks > ( UBaseType_t ) 0U )
+			{
+				/* Move any readied tasks from the pending list into the
+				appropriate ready list. */
+				while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE )
+				{
+					pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xPendingReadyList ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+					( void ) uxListRemove( &( pxTCB->xEventListItem ) );
+					( void ) uxListRemove( &( pxTCB->xStateListItem ) );
+					prvAddTaskToReadyList( pxTCB );
+
+					/* If the moved task has a priority higher than the current
+					task then a yield must be performed. */
+					if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )
+					{
+						xYieldPending = pdTRUE;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+
+				if( pxTCB != NULL )
+				{
+					/* A task was unblocked while the scheduler was suspended,
+					which may have prevented the next unblock time from being
+					re-calculated, in which case re-calculate it now.  Mainly
+					important for low power tickless implementations, where
+					this can prevent an unnecessary exit from low power
+					state. */
+					prvResetNextTaskUnblockTime();
+				}
+
+				/* If any ticks occurred while the scheduler was suspended then
+				they should be processed now.  This ensures the tick count does
+				not	slip, and that any delayed tasks are resumed at the correct
+				time. */
+				{
+					TickType_t xPendedCounts = xPendedTicks; /* Non-volatile copy. */
+
+					if( xPendedCounts > ( TickType_t ) 0U )
+					{
+						do
+						{
+							if( xTaskIncrementTick() != pdFALSE )
+							{
+								xYieldPending = pdTRUE;
+							}
+							else
+							{
+								mtCOVERAGE_TEST_MARKER();
+							}
+							--xPendedCounts;
+						} while( xPendedCounts > ( TickType_t ) 0U );
+
+						xPendedTicks = 0;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+
+				if( xYieldPending != pdFALSE )
+				{
+					#if( configUSE_PREEMPTION != 0 )
+					{
+						xAlreadyYielded = pdTRUE;
+					}
+					#endif
+					taskYIELD_IF_USING_PREEMPTION();
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	taskEXIT_CRITICAL();
+
+	return xAlreadyYielded;
+}
+/*-----------------------------------------------------------*/
+
+TickType_t xTaskGetTickCount( void )
+{
+TickType_t xTicks;
+
+	/* Critical section required if running on a 16 bit processor. */
+	portTICK_TYPE_ENTER_CRITICAL();
+	{
+		xTicks = xTickCount;
+	}
+	portTICK_TYPE_EXIT_CRITICAL();
+
+	return xTicks;
+}
+/*-----------------------------------------------------------*/
+
+TickType_t xTaskGetTickCountFromISR( void )
+{
+TickType_t xReturn;
+UBaseType_t uxSavedInterruptStatus;
+
+	/* RTOS ports that support interrupt nesting have the concept of a maximum
+	system call (or maximum API call) interrupt priority.  Interrupts that are
+	above the maximum system call priority are kept permanently enabled, even
+	when the RTOS kernel is in a critical section, but cannot make any calls to
+	FreeRTOS API functions.  If configASSERT() is defined in FreeRTOSConfig.h
+	then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
+	failure if a FreeRTOS API function is called from an interrupt that has been
+	assigned a priority above the configured maximum system call priority.
+	Only FreeRTOS functions that end in FromISR can be called from interrupts
+	that have been assigned a priority at or (logically) below the maximum
+	system call	interrupt priority.  FreeRTOS maintains a separate interrupt
+	safe API to ensure interrupt entry is as fast and as simple as possible.
+	More information (albeit Cortex-M specific) is provided on the following
+	link: https://www.freertos.org/RTOS-Cortex-M3-M4.html */
+	portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+
+	uxSavedInterruptStatus = portTICK_TYPE_SET_INTERRUPT_MASK_FROM_ISR();
+	{
+		xReturn = xTickCount;
+	}
+	portTICK_TYPE_CLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+UBaseType_t uxTaskGetNumberOfTasks( void )
+{
+	/* A critical section is not required because the variables are of type
+	BaseType_t. */
+	return uxCurrentNumberOfTasks;
+}
+/*-----------------------------------------------------------*/
+
+char *pcTaskGetName( TaskHandle_t xTaskToQuery ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+{
+TCB_t *pxTCB;
+
+	/* If null is passed in here then the name of the calling task is being
+	queried. */
+	pxTCB = prvGetTCBFromHandle( xTaskToQuery );
+	configASSERT( pxTCB );
+	return &( pxTCB->pcTaskName[ 0 ] );
+}
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_xTaskGetHandle == 1 )
+
+	static TCB_t *prvSearchForNameWithinSingleList( List_t *pxList, const char pcNameToQuery[] )
+	{
+	TCB_t *pxNextTCB, *pxFirstTCB, *pxReturn = NULL;
+	UBaseType_t x;
+	char cNextChar;
+	BaseType_t xBreakLoop;
+
+		/* This function is called with the scheduler suspended. */
+
+		if( listCURRENT_LIST_LENGTH( pxList ) > ( UBaseType_t ) 0 )
+		{
+			listGET_OWNER_OF_NEXT_ENTRY( pxFirstTCB, pxList );  /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+
+			do
+			{
+				listGET_OWNER_OF_NEXT_ENTRY( pxNextTCB, pxList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+
+				/* Check each character in the name looking for a match or
+				mismatch. */
+				xBreakLoop = pdFALSE;
+				for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ )
+				{
+					cNextChar = pxNextTCB->pcTaskName[ x ];
+
+					if( cNextChar != pcNameToQuery[ x ] )
+					{
+						/* Characters didn't match. */
+						xBreakLoop = pdTRUE;
+					}
+					else if( cNextChar == ( char ) 0x00 )
+					{
+						/* Both strings terminated, a match must have been
+						found. */
+						pxReturn = pxNextTCB;
+						xBreakLoop = pdTRUE;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+
+					if( xBreakLoop != pdFALSE )
+					{
+						break;
+					}
+				}
+
+				if( pxReturn != NULL )
+				{
+					/* The handle has been found. */
+					break;
+				}
+
+			} while( pxNextTCB != pxFirstTCB );
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		return pxReturn;
+	}
+
+#endif /* INCLUDE_xTaskGetHandle */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_xTaskGetHandle == 1 )
+
+	TaskHandle_t xTaskGetHandle( const char *pcNameToQuery ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+	{
+	UBaseType_t uxQueue = configMAX_PRIORITIES;
+	TCB_t* pxTCB;
+
+		/* Task names will be truncated to configMAX_TASK_NAME_LEN - 1 bytes. */
+		configASSERT( strlen( pcNameToQuery ) < configMAX_TASK_NAME_LEN );
+
+		vTaskSuspendAll();
+		{
+			/* Search the ready lists. */
+			do
+			{
+				uxQueue--;
+				pxTCB = prvSearchForNameWithinSingleList( ( List_t * ) &( pxReadyTasksLists[ uxQueue ] ), pcNameToQuery );
+
+				if( pxTCB != NULL )
+				{
+					/* Found the handle. */
+					break;
+				}
+
+			} while( uxQueue > ( UBaseType_t ) tskIDLE_PRIORITY ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+
+			/* Search the delayed lists. */
+			if( pxTCB == NULL )
+			{
+				pxTCB = prvSearchForNameWithinSingleList( ( List_t * ) pxDelayedTaskList, pcNameToQuery );
+			}
+
+			if( pxTCB == NULL )
+			{
+				pxTCB = prvSearchForNameWithinSingleList( ( List_t * ) pxOverflowDelayedTaskList, pcNameToQuery );
+			}
+
+			#if ( INCLUDE_vTaskSuspend == 1 )
+			{
+				if( pxTCB == NULL )
+				{
+					/* Search the suspended list. */
+					pxTCB = prvSearchForNameWithinSingleList( &xSuspendedTaskList, pcNameToQuery );
+				}
+			}
+			#endif
+
+			#if( INCLUDE_vTaskDelete == 1 )
+			{
+				if( pxTCB == NULL )
+				{
+					/* Search the deleted list. */
+					pxTCB = prvSearchForNameWithinSingleList( &xTasksWaitingTermination, pcNameToQuery );
+				}
+			}
+			#endif
+		}
+		( void ) xTaskResumeAll();
+
+		return pxTCB;
+	}
+
+#endif /* INCLUDE_xTaskGetHandle */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	UBaseType_t uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, const UBaseType_t uxArraySize, uint32_t * const pulTotalRunTime )
+	{
+	UBaseType_t uxTask = 0, uxQueue = configMAX_PRIORITIES;
+
+		vTaskSuspendAll();
+		{
+			/* Is there a space in the array for each task in the system? */
+			if( uxArraySize >= uxCurrentNumberOfTasks )
+			{
+				/* Fill in an TaskStatus_t structure with information on each
+				task in the Ready state. */
+				do
+				{
+					uxQueue--;
+					uxTask += prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), &( pxReadyTasksLists[ uxQueue ] ), eReady );
+
+				} while( uxQueue > ( UBaseType_t ) tskIDLE_PRIORITY ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+
+				/* Fill in an TaskStatus_t structure with information on each
+				task in the Blocked state. */
+				uxTask += prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), ( List_t * ) pxDelayedTaskList, eBlocked );
+				uxTask += prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), ( List_t * ) pxOverflowDelayedTaskList, eBlocked );
+
+				#if( INCLUDE_vTaskDelete == 1 )
+				{
+					/* Fill in an TaskStatus_t structure with information on
+					each task that has been deleted but not yet cleaned up. */
+					uxTask += prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), &xTasksWaitingTermination, eDeleted );
+				}
+				#endif
+
+				#if ( INCLUDE_vTaskSuspend == 1 )
+				{
+					/* Fill in an TaskStatus_t structure with information on
+					each task in the Suspended state. */
+					uxTask += prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), &xSuspendedTaskList, eSuspended );
+				}
+				#endif
+
+				#if ( configGENERATE_RUN_TIME_STATS == 1)
+				{
+					if( pulTotalRunTime != NULL )
+					{
+						#ifdef portALT_GET_RUN_TIME_COUNTER_VALUE
+							portALT_GET_RUN_TIME_COUNTER_VALUE( ( *pulTotalRunTime ) );
+						#else
+							*pulTotalRunTime = portGET_RUN_TIME_COUNTER_VALUE();
+						#endif
+					}
+				}
+				#else
+				{
+					if( pulTotalRunTime != NULL )
+					{
+						*pulTotalRunTime = 0;
+					}
+				}
+				#endif
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		( void ) xTaskResumeAll();
+
+		return uxTask;
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*----------------------------------------------------------*/
+
+#if ( INCLUDE_xTaskGetIdleTaskHandle == 1 )
+
+	TaskHandle_t xTaskGetIdleTaskHandle( void )
+	{
+		/* If xTaskGetIdleTaskHandle() is called before the scheduler has been
+		started, then xIdleTaskHandle will be NULL. */
+		configASSERT( ( xIdleTaskHandle != NULL ) );
+		return xIdleTaskHandle;
+	}
+
+#endif /* INCLUDE_xTaskGetIdleTaskHandle */
+/*----------------------------------------------------------*/
+
+/* This conditional compilation should use inequality to 0, not equality to 1.
+This is to ensure vTaskStepTick() is available when user defined low power mode
+implementations require configUSE_TICKLESS_IDLE to be set to a value other than
+1. */
+#if ( configUSE_TICKLESS_IDLE != 0 )
+
+	void vTaskStepTick( const TickType_t xTicksToJump )
+	{
+		/* Correct the tick count value after a period during which the tick
+		was suppressed.  Note this does *not* call the tick hook function for
+		each stepped tick. */
+		configASSERT( ( xTickCount + xTicksToJump ) <= xNextTaskUnblockTime );
+		xTickCount += xTicksToJump;
+		traceINCREASE_TICK_COUNT( xTicksToJump );
+	}
+
+#endif /* configUSE_TICKLESS_IDLE */
+/*----------------------------------------------------------*/
+
+BaseType_t xTaskCatchUpTicks( TickType_t xTicksToCatchUp )
+{
+BaseType_t xYieldRequired = pdFALSE;
+
+	/* Must not be called with the scheduler suspended as the implementation
+	relies on xPendedTicks being wound down to 0 in xTaskResumeAll(). */
+	configASSERT( uxSchedulerSuspended == 0 );
+
+	/* Use xPendedTicks to mimic xTicksToCatchUp number of ticks occurring when
+	the scheduler is suspended so the ticks are executed in xTaskResumeAll(). */
+	vTaskSuspendAll();
+	xPendedTicks += xTicksToCatchUp;
+	xYieldRequired = xTaskResumeAll();
+
+	return xYieldRequired;
+}
+/*----------------------------------------------------------*/
+
+#if ( INCLUDE_xTaskAbortDelay == 1 )
+
+	BaseType_t xTaskAbortDelay( TaskHandle_t xTask )
+	{
+	TCB_t *pxTCB = xTask;
+	BaseType_t xReturn;
+
+		configASSERT( pxTCB );
+
+		vTaskSuspendAll();
+		{
+			/* A task can only be prematurely removed from the Blocked state if
+			it is actually in the Blocked state. */
+			if( eTaskGetState( xTask ) == eBlocked )
+			{
+				xReturn = pdPASS;
+
+				/* Remove the reference to the task from the blocked list.  An
+				interrupt won't touch the xStateListItem because the
+				scheduler is suspended. */
+				( void ) uxListRemove( &( pxTCB->xStateListItem ) );
+
+				/* Is the task waiting on an event also?  If so remove it from
+				the event list too.  Interrupts can touch the event list item,
+				even though the scheduler is suspended, so a critical section
+				is used. */
+				taskENTER_CRITICAL();
+				{
+					if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )
+					{
+						( void ) uxListRemove( &( pxTCB->xEventListItem ) );
+
+						/* This lets the task know it was forcibly removed from the
+						blocked state so it should not re-evaluate its block time and
+						then block again. */
+						pxTCB->ucDelayAborted = pdTRUE;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				taskEXIT_CRITICAL();
+
+				/* Place the unblocked task into the appropriate ready list. */
+				prvAddTaskToReadyList( pxTCB );
+
+				/* A task being unblocked cannot cause an immediate context
+				switch if preemption is turned off. */
+				#if (  configUSE_PREEMPTION == 1 )
+				{
+					/* Preemption is on, but a context switch should only be
+					performed if the unblocked task has a priority that is
+					equal to or higher than the currently executing task. */
+					if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )
+					{
+						/* Pend the yield to be performed when the scheduler
+						is unsuspended. */
+						xYieldPending = pdTRUE;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				#endif /* configUSE_PREEMPTION */
+			}
+			else
+			{
+				xReturn = pdFAIL;
+			}
+		}
+		( void ) xTaskResumeAll();
+
+		return xReturn;
+	}
+
+#endif /* INCLUDE_xTaskAbortDelay */
+/*----------------------------------------------------------*/
+
+BaseType_t xTaskIncrementTick( void )
+{
+TCB_t * pxTCB;
+TickType_t xItemValue;
+BaseType_t xSwitchRequired = pdFALSE;
+
+	/* Called by the portable layer each time a tick interrupt occurs.
+	Increments the tick then checks to see if the new tick value will cause any
+	tasks to be unblocked. */
+	traceTASK_INCREMENT_TICK( xTickCount );
+	if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
+	{
+		/* Minor optimisation.  The tick count cannot change in this
+		block. */
+		const TickType_t xConstTickCount = xTickCount + ( TickType_t ) 1;
+
+		/* Increment the RTOS tick, switching the delayed and overflowed
+		delayed lists if it wraps to 0. */
+		xTickCount = xConstTickCount;
+
+		if( xConstTickCount == ( TickType_t ) 0U ) /*lint !e774 'if' does not always evaluate to false as it is looking for an overflow. */
+		{
+			taskSWITCH_DELAYED_LISTS();
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		/* See if this tick has made a timeout expire.  Tasks are stored in
+		the	queue in the order of their wake time - meaning once one task
+		has been found whose block time has not expired there is no need to
+		look any further down the list. */
+		if( xConstTickCount >= xNextTaskUnblockTime )
+		{
+			for( ;; )
+			{
+				if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE )
+				{
+					/* The delayed list is empty.  Set xNextTaskUnblockTime
+					to the maximum possible value so it is extremely
+					unlikely that the
+					if( xTickCount >= xNextTaskUnblockTime ) test will pass
+					next time through. */
+					xNextTaskUnblockTime = portMAX_DELAY; /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+					break;
+				}
+				else
+				{
+					/* The delayed list is not empty, get the value of the
+					item at the head of the delayed list.  This is the time
+					at which the task at the head of the delayed list must
+					be removed from the Blocked state. */
+					pxTCB = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+					xItemValue = listGET_LIST_ITEM_VALUE( &( pxTCB->xStateListItem ) );
+
+					if( xConstTickCount < xItemValue )
+					{
+						/* It is not time to unblock this item yet, but the
+						item value is the time at which the task at the head
+						of the blocked list must be removed from the Blocked
+						state -	so record the item value in
+						xNextTaskUnblockTime. */
+						xNextTaskUnblockTime = xItemValue;
+						break; /*lint !e9011 Code structure here is deedmed easier to understand with multiple breaks. */
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+
+					/* It is time to remove the item from the Blocked state. */
+					( void ) uxListRemove( &( pxTCB->xStateListItem ) );
+
+					/* Is the task waiting on an event also?  If so remove
+					it from the event list. */
+					if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )
+					{
+						( void ) uxListRemove( &( pxTCB->xEventListItem ) );
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+
+					/* Place the unblocked task into the appropriate ready
+					list. */
+					prvAddTaskToReadyList( pxTCB );
+
+					/* A task being unblocked cannot cause an immediate
+					context switch if preemption is turned off. */
+					#if (  configUSE_PREEMPTION == 1 )
+					{
+						/* Preemption is on, but a context switch should
+						only be performed if the unblocked task has a
+						priority that is equal to or higher than the
+						currently executing task. */
+						if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )
+						{
+							xSwitchRequired = pdTRUE;
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+					#endif /* configUSE_PREEMPTION */
+				}
+			}
+		}
+
+		/* Tasks of equal priority to the currently running task will share
+		processing time (time slice) if preemption is on, and the application
+		writer has not explicitly turned time slicing off. */
+		#if ( ( configUSE_PREEMPTION == 1 ) && ( configUSE_TIME_SLICING == 1 ) )
+		{
+			if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ pxCurrentTCB->uxPriority ] ) ) > ( UBaseType_t ) 1 )
+			{
+				xSwitchRequired = pdTRUE;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		#endif /* ( ( configUSE_PREEMPTION == 1 ) && ( configUSE_TIME_SLICING == 1 ) ) */
+
+		#if ( configUSE_TICK_HOOK == 1 )
+		{
+			/* Guard against the tick hook being called when the pended tick
+			count is being unwound (when the scheduler is being unlocked). */
+			if( xPendedTicks == ( TickType_t ) 0 )
+			{
+				vApplicationTickHook();
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		#endif /* configUSE_TICK_HOOK */
+
+		#if ( configUSE_PREEMPTION == 1 )
+		{
+			if( xYieldPending != pdFALSE )
+			{
+				xSwitchRequired = pdTRUE;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		#endif /* configUSE_PREEMPTION */
+	}
+	else
+	{
+		++xPendedTicks;
+
+		/* The tick hook gets called at regular intervals, even if the
+		scheduler is locked. */
+		#if ( configUSE_TICK_HOOK == 1 )
+		{
+			vApplicationTickHook();
+		}
+		#endif
+	}
+
+	return xSwitchRequired;
+}
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_APPLICATION_TASK_TAG == 1 )
+
+	void vTaskSetApplicationTaskTag( TaskHandle_t xTask, TaskHookFunction_t pxHookFunction )
+	{
+	TCB_t *xTCB;
+
+		/* If xTask is NULL then it is the task hook of the calling task that is
+		getting set. */
+		if( xTask == NULL )
+		{
+			xTCB = ( TCB_t * ) pxCurrentTCB;
+		}
+		else
+		{
+			xTCB = xTask;
+		}
+
+		/* Save the hook function in the TCB.  A critical section is required as
+		the value can be accessed from an interrupt. */
+		taskENTER_CRITICAL();
+		{
+			xTCB->pxTaskTag = pxHookFunction;
+		}
+		taskEXIT_CRITICAL();
+	}
+
+#endif /* configUSE_APPLICATION_TASK_TAG */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_APPLICATION_TASK_TAG == 1 )
+
+	TaskHookFunction_t xTaskGetApplicationTaskTag( TaskHandle_t xTask )
+	{
+	TCB_t *pxTCB;
+	TaskHookFunction_t xReturn;
+
+		/* If xTask is NULL then set the calling task's hook. */
+		pxTCB = prvGetTCBFromHandle( xTask );
+
+		/* Save the hook function in the TCB.  A critical section is required as
+		the value can be accessed from an interrupt. */
+		taskENTER_CRITICAL();
+		{
+			xReturn = pxTCB->pxTaskTag;
+		}
+		taskEXIT_CRITICAL();
+
+		return xReturn;
+	}
+
+#endif /* configUSE_APPLICATION_TASK_TAG */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_APPLICATION_TASK_TAG == 1 )
+
+	TaskHookFunction_t xTaskGetApplicationTaskTagFromISR( TaskHandle_t xTask )
+	{
+	TCB_t *pxTCB;
+	TaskHookFunction_t xReturn;
+	UBaseType_t uxSavedInterruptStatus;
+
+		/* If xTask is NULL then set the calling task's hook. */
+		pxTCB = prvGetTCBFromHandle( xTask );
+
+		/* Save the hook function in the TCB.  A critical section is required as
+		the value can be accessed from an interrupt. */
+		uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+		{
+			xReturn = pxTCB->pxTaskTag;
+		}
+		portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+		return xReturn;
+	}
+
+#endif /* configUSE_APPLICATION_TASK_TAG */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_APPLICATION_TASK_TAG == 1 )
+
+	BaseType_t xTaskCallApplicationTaskHook( TaskHandle_t xTask, void *pvParameter )
+	{
+	TCB_t *xTCB;
+	BaseType_t xReturn;
+
+		/* If xTask is NULL then we are calling our own task hook. */
+		if( xTask == NULL )
+		{
+			xTCB = pxCurrentTCB;
+		}
+		else
+		{
+			xTCB = xTask;
+		}
+
+		if( xTCB->pxTaskTag != NULL )
+		{
+			xReturn = xTCB->pxTaskTag( pvParameter );
+		}
+		else
+		{
+			xReturn = pdFAIL;
+		}
+
+		return xReturn;
+	}
+
+#endif /* configUSE_APPLICATION_TASK_TAG */
+/*-----------------------------------------------------------*/
+
+void vTaskSwitchContext( void )
+{
+	if( uxSchedulerSuspended != ( UBaseType_t ) pdFALSE )
+	{
+		/* The scheduler is currently suspended - do not allow a context
+		switch. */
+		xYieldPending = pdTRUE;
+	}
+	else
+	{
+		xYieldPending = pdFALSE;
+		traceTASK_SWITCHED_OUT();
+
+		#if ( configGENERATE_RUN_TIME_STATS == 1 )
+		{
+			#ifdef portALT_GET_RUN_TIME_COUNTER_VALUE
+				portALT_GET_RUN_TIME_COUNTER_VALUE( ulTotalRunTime );
+			#else
+				ulTotalRunTime = portGET_RUN_TIME_COUNTER_VALUE();
+			#endif
+
+			/* Add the amount of time the task has been running to the
+			accumulated time so far.  The time the task started running was
+			stored in ulTaskSwitchedInTime.  Note that there is no overflow
+			protection here so count values are only valid until the timer
+			overflows.  The guard against negative values is to protect
+			against suspect run time stat counter implementations - which
+			are provided by the application, not the kernel. */
+			if( ulTotalRunTime > ulTaskSwitchedInTime )
+			{
+				pxCurrentTCB->ulRunTimeCounter += ( ulTotalRunTime - ulTaskSwitchedInTime );
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+			ulTaskSwitchedInTime = ulTotalRunTime;
+		}
+		#endif /* configGENERATE_RUN_TIME_STATS */
+
+		/* Check for stack overflow, if configured. */
+		taskCHECK_FOR_STACK_OVERFLOW();
+
+		/* Before the currently running task is switched out, save its errno. */
+		#if( configUSE_POSIX_ERRNO == 1 )
+		{
+			pxCurrentTCB->iTaskErrno = FreeRTOS_errno;
+		}
+		#endif
+
+		/* Select a new task to run using either the generic C or port
+		optimised asm code. */
+		taskSELECT_HIGHEST_PRIORITY_TASK(); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+		traceTASK_SWITCHED_IN();
+
+		/* After the new task is switched in, update the global errno. */
+		#if( configUSE_POSIX_ERRNO == 1 )
+		{
+			FreeRTOS_errno = pxCurrentTCB->iTaskErrno;
+		}
+		#endif
+
+		#if ( configUSE_NEWLIB_REENTRANT == 1 )
+		{
+			/* Switch Newlib's _impure_ptr variable to point to the _reent
+			structure specific to this task.
+			See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html
+			for additional information. */
+			_impure_ptr = &( pxCurrentTCB->xNewLib_reent );
+		}
+		#endif /* configUSE_NEWLIB_REENTRANT */
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vTaskPlaceOnEventList( List_t * const pxEventList, const TickType_t xTicksToWait )
+{
+	configASSERT( pxEventList );
+
+	/* THIS FUNCTION MUST BE CALLED WITH EITHER INTERRUPTS DISABLED OR THE
+	SCHEDULER SUSPENDED AND THE QUEUE BEING ACCESSED LOCKED. */
+
+	/* Place the event list item of the TCB in the appropriate event list.
+	This is placed in the list in priority order so the highest priority task
+	is the first to be woken by the event.  The queue that contains the event
+	list is locked, preventing simultaneous access from interrupts. */
+	vListInsert( pxEventList, &( pxCurrentTCB->xEventListItem ) );
+
+	prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE );
+}
+/*-----------------------------------------------------------*/
+
+void vTaskPlaceOnUnorderedEventList( List_t * pxEventList, const TickType_t xItemValue, const TickType_t xTicksToWait )
+{
+	configASSERT( pxEventList );
+
+	/* THIS FUNCTION MUST BE CALLED WITH THE SCHEDULER SUSPENDED.  It is used by
+	the event groups implementation. */
+	configASSERT( uxSchedulerSuspended != 0 );
+
+	/* Store the item value in the event list item.  It is safe to access the
+	event list item here as interrupts won't access the event list item of a
+	task that is not in the Blocked state. */
+	listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xEventListItem ), xItemValue | taskEVENT_LIST_ITEM_VALUE_IN_USE );
+
+	/* Place the event list item of the TCB at the end of the appropriate event
+	list.  It is safe to access the event list here because it is part of an
+	event group implementation - and interrupts don't access event groups
+	directly (instead they access them indirectly by pending function calls to
+	the task level). */
+	vListInsertEnd( pxEventList, &( pxCurrentTCB->xEventListItem ) );
+
+	prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE );
+}
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TIMERS == 1 )
+
+	void vTaskPlaceOnEventListRestricted( List_t * const pxEventList, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely )
+	{
+		configASSERT( pxEventList );
+
+		/* This function should not be called by application code hence the
+		'Restricted' in its name.  It is not part of the public API.  It is
+		designed for use by kernel code, and has special calling requirements -
+		it should be called with the scheduler suspended. */
+
+
+		/* Place the event list item of the TCB in the appropriate event list.
+		In this case it is assume that this is the only task that is going to
+		be waiting on this event list, so the faster vListInsertEnd() function
+		can be used in place of vListInsert. */
+		vListInsertEnd( pxEventList, &( pxCurrentTCB->xEventListItem ) );
+
+		/* If the task should block indefinitely then set the block time to a
+		value that will be recognised as an indefinite delay inside the
+		prvAddCurrentTaskToDelayedList() function. */
+		if( xWaitIndefinitely != pdFALSE )
+		{
+			xTicksToWait = portMAX_DELAY;
+		}
+
+		traceTASK_DELAY_UNTIL( ( xTickCount + xTicksToWait ) );
+		prvAddCurrentTaskToDelayedList( xTicksToWait, xWaitIndefinitely );
+	}
+
+#endif /* configUSE_TIMERS */
+/*-----------------------------------------------------------*/
+
+BaseType_t xTaskRemoveFromEventList( const List_t * const pxEventList )
+{
+TCB_t *pxUnblockedTCB;
+BaseType_t xReturn;
+
+	/* THIS FUNCTION MUST BE CALLED FROM A CRITICAL SECTION.  It can also be
+	called from a critical section within an ISR. */
+
+	/* The event list is sorted in priority order, so the first in the list can
+	be removed as it is known to be the highest priority.  Remove the TCB from
+	the delayed list, and add it to the ready list.
+
+	If an event is for a queue that is locked then this function will never
+	get called - the lock count on the queue will get modified instead.  This
+	means exclusive access to the event list is guaranteed here.
+
+	This function assumes that a check has already been made to ensure that
+	pxEventList is not empty. */
+	pxUnblockedTCB = listGET_OWNER_OF_HEAD_ENTRY( pxEventList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+	configASSERT( pxUnblockedTCB );
+	( void ) uxListRemove( &( pxUnblockedTCB->xEventListItem ) );
+
+	if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
+	{
+		( void ) uxListRemove( &( pxUnblockedTCB->xStateListItem ) );
+		prvAddTaskToReadyList( pxUnblockedTCB );
+
+		#if( configUSE_TICKLESS_IDLE != 0 )
+		{
+			/* If a task is blocked on a kernel object then xNextTaskUnblockTime
+			might be set to the blocked task's time out time.  If the task is
+			unblocked for a reason other than a timeout xNextTaskUnblockTime is
+			normally left unchanged, because it is automatically reset to a new
+			value when the tick count equals xNextTaskUnblockTime.  However if
+			tickless idling is used it might be more important to enter sleep mode
+			at the earliest possible time - so reset xNextTaskUnblockTime here to
+			ensure it is updated at the earliest possible time. */
+			prvResetNextTaskUnblockTime();
+		}
+		#endif
+	}
+	else
+	{
+		/* The delayed and ready lists cannot be accessed, so hold this task
+		pending until the scheduler is resumed. */
+		vListInsertEnd( &( xPendingReadyList ), &( pxUnblockedTCB->xEventListItem ) );
+	}
+
+	if( pxUnblockedTCB->uxPriority > pxCurrentTCB->uxPriority )
+	{
+		/* Return true if the task removed from the event list has a higher
+		priority than the calling task.  This allows the calling task to know if
+		it should force a context switch now. */
+		xReturn = pdTRUE;
+
+		/* Mark that a yield is pending in case the user is not using the
+		"xHigherPriorityTaskWoken" parameter to an ISR safe FreeRTOS function. */
+		xYieldPending = pdTRUE;
+	}
+	else
+	{
+		xReturn = pdFALSE;
+	}
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+void vTaskRemoveFromUnorderedEventList( ListItem_t * pxEventListItem, const TickType_t xItemValue )
+{
+TCB_t *pxUnblockedTCB;
+
+	/* THIS FUNCTION MUST BE CALLED WITH THE SCHEDULER SUSPENDED.  It is used by
+	the event flags implementation. */
+	configASSERT( uxSchedulerSuspended != pdFALSE );
+
+	/* Store the new item value in the event list. */
+	listSET_LIST_ITEM_VALUE( pxEventListItem, xItemValue | taskEVENT_LIST_ITEM_VALUE_IN_USE );
+
+	/* Remove the event list form the event flag.  Interrupts do not access
+	event flags. */
+	pxUnblockedTCB = listGET_LIST_ITEM_OWNER( pxEventListItem ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+	configASSERT( pxUnblockedTCB );
+	( void ) uxListRemove( pxEventListItem );
+
+	#if( configUSE_TICKLESS_IDLE != 0 )
+	{
+		/* If a task is blocked on a kernel object then xNextTaskUnblockTime
+		might be set to the blocked task's time out time.  If the task is
+		unblocked for a reason other than a timeout xNextTaskUnblockTime is
+		normally left unchanged, because it is automatically reset to a new
+		value when the tick count equals xNextTaskUnblockTime.  However if
+		tickless idling is used it might be more important to enter sleep mode
+		at the earliest possible time - so reset xNextTaskUnblockTime here to
+		ensure it is updated at the earliest possible time. */
+		prvResetNextTaskUnblockTime();
+	}
+	#endif
+
+	/* Remove the task from the delayed list and add it to the ready list.  The
+	scheduler is suspended so interrupts will not be accessing the ready
+	lists. */
+	( void ) uxListRemove( &( pxUnblockedTCB->xStateListItem ) );
+	prvAddTaskToReadyList( pxUnblockedTCB );
+
+	if( pxUnblockedTCB->uxPriority > pxCurrentTCB->uxPriority )
+	{
+		/* The unblocked task has a priority above that of the calling task, so
+		a context switch is required.  This function is called with the
+		scheduler suspended so xYieldPending is set so the context switch
+		occurs immediately that the scheduler is resumed (unsuspended). */
+		xYieldPending = pdTRUE;
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vTaskSetTimeOutState( TimeOut_t * const pxTimeOut )
+{
+	configASSERT( pxTimeOut );
+	taskENTER_CRITICAL();
+	{
+		pxTimeOut->xOverflowCount = xNumOfOverflows;
+		pxTimeOut->xTimeOnEntering = xTickCount;
+	}
+	taskEXIT_CRITICAL();
+}
+/*-----------------------------------------------------------*/
+
+void vTaskInternalSetTimeOutState( TimeOut_t * const pxTimeOut )
+{
+	/* For internal use only as it does not use a critical section. */
+	pxTimeOut->xOverflowCount = xNumOfOverflows;
+	pxTimeOut->xTimeOnEntering = xTickCount;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait )
+{
+BaseType_t xReturn;
+
+	configASSERT( pxTimeOut );
+	configASSERT( pxTicksToWait );
+
+	taskENTER_CRITICAL();
+	{
+		/* Minor optimisation.  The tick count cannot change in this block. */
+		const TickType_t xConstTickCount = xTickCount;
+		const TickType_t xElapsedTime = xConstTickCount - pxTimeOut->xTimeOnEntering;
+
+		#if( INCLUDE_xTaskAbortDelay == 1 )
+			if( pxCurrentTCB->ucDelayAborted != ( uint8_t ) pdFALSE )
+			{
+				/* The delay was aborted, which is not the same as a time out,
+				but has the same result. */
+				pxCurrentTCB->ucDelayAborted = pdFALSE;
+				xReturn = pdTRUE;
+			}
+			else
+		#endif
+
+		#if ( INCLUDE_vTaskSuspend == 1 )
+			if( *pxTicksToWait == portMAX_DELAY )
+			{
+				/* If INCLUDE_vTaskSuspend is set to 1 and the block time
+				specified is the maximum block time then the task should block
+				indefinitely, and therefore never time out. */
+				xReturn = pdFALSE;
+			}
+			else
+		#endif
+
+		if( ( xNumOfOverflows != pxTimeOut->xOverflowCount ) && ( xConstTickCount >= pxTimeOut->xTimeOnEntering ) ) /*lint !e525 Indentation preferred as is to make code within pre-processor directives clearer. */
+		{
+			/* The tick count is greater than the time at which
+			vTaskSetTimeout() was called, but has also overflowed since
+			vTaskSetTimeOut() was called.  It must have wrapped all the way
+			around and gone past again. This passed since vTaskSetTimeout()
+			was called. */
+			xReturn = pdTRUE;
+		}
+		else if( xElapsedTime < *pxTicksToWait ) /*lint !e961 Explicit casting is only redundant with some compilers, whereas others require it to prevent integer conversion errors. */
+		{
+			/* Not a genuine timeout. Adjust parameters for time remaining. */
+			*pxTicksToWait -= xElapsedTime;
+			vTaskInternalSetTimeOutState( pxTimeOut );
+			xReturn = pdFALSE;
+		}
+		else
+		{
+			*pxTicksToWait = 0;
+			xReturn = pdTRUE;
+		}
+	}
+	taskEXIT_CRITICAL();
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+void vTaskMissedYield( void )
+{
+	xYieldPending = pdTRUE;
+}
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	UBaseType_t uxTaskGetTaskNumber( TaskHandle_t xTask )
+	{
+	UBaseType_t uxReturn;
+	TCB_t const *pxTCB;
+
+		if( xTask != NULL )
+		{
+			pxTCB = xTask;
+			uxReturn = pxTCB->uxTaskNumber;
+		}
+		else
+		{
+			uxReturn = 0U;
+		}
+
+		return uxReturn;
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	void vTaskSetTaskNumber( TaskHandle_t xTask, const UBaseType_t uxHandle )
+	{
+	TCB_t * pxTCB;
+
+		if( xTask != NULL )
+		{
+			pxTCB = xTask;
+			pxTCB->uxTaskNumber = uxHandle;
+		}
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+
+/*
+ * -----------------------------------------------------------
+ * The Idle task.
+ * ----------------------------------------------------------
+ *
+ * The portTASK_FUNCTION() macro is used to allow port/compiler specific
+ * language extensions.  The equivalent prototype for this function is:
+ *
+ * void prvIdleTask( void *pvParameters );
+ *
+ */
+static portTASK_FUNCTION( prvIdleTask, pvParameters )
+{
+	/* Stop warnings. */
+	( void ) pvParameters;
+
+	/** THIS IS THE RTOS IDLE TASK - WHICH IS CREATED AUTOMATICALLY WHEN THE
+	SCHEDULER IS STARTED. **/
+
+	/* In case a task that has a secure context deletes itself, in which case
+	the idle task is responsible for deleting the task's secure context, if
+	any. */
+	portALLOCATE_SECURE_CONTEXT( configMINIMAL_SECURE_STACK_SIZE );
+
+	for( ;; )
+	{
+		/* See if any tasks have deleted themselves - if so then the idle task
+		is responsible for freeing the deleted task's TCB and stack. */
+		prvCheckTasksWaitingTermination();
+
+		#if ( configUSE_PREEMPTION == 0 )
+		{
+			/* If we are not using preemption we keep forcing a task switch to
+			see if any other task has become available.  If we are using
+			preemption we don't need to do this as any task becoming available
+			will automatically get the processor anyway. */
+			taskYIELD();
+		}
+		#endif /* configUSE_PREEMPTION */
+
+		#if ( ( configUSE_PREEMPTION == 1 ) && ( configIDLE_SHOULD_YIELD == 1 ) )
+		{
+			/* When using preemption tasks of equal priority will be
+			timesliced.  If a task that is sharing the idle priority is ready
+			to run then the idle task should yield before the end of the
+			timeslice.
+
+			A critical region is not required here as we are just reading from
+			the list, and an occasional incorrect value will not matter.  If
+			the ready list at the idle priority contains more than one task
+			then a task other than the idle task is ready to execute. */
+			if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > ( UBaseType_t ) 1 )
+			{
+				taskYIELD();
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		#endif /* ( ( configUSE_PREEMPTION == 1 ) && ( configIDLE_SHOULD_YIELD == 1 ) ) */
+
+		#if ( configUSE_IDLE_HOOK == 1 )
+		{
+			extern void vApplicationIdleHook( void );
+
+			/* Call the user defined function from within the idle task.  This
+			allows the application designer to add background functionality
+			without the overhead of a separate task.
+			NOTE: vApplicationIdleHook() MUST NOT, UNDER ANY CIRCUMSTANCES,
+			CALL A FUNCTION THAT MIGHT BLOCK. */
+			vApplicationIdleHook();
+		}
+		#endif /* configUSE_IDLE_HOOK */
+
+		/* This conditional compilation should use inequality to 0, not equality
+		to 1.  This is to ensure portSUPPRESS_TICKS_AND_SLEEP() is called when
+		user defined low power mode	implementations require
+		configUSE_TICKLESS_IDLE to be set to a value other than 1. */
+		#if ( configUSE_TICKLESS_IDLE != 0 )
+		{
+		TickType_t xExpectedIdleTime;
+
+			/* It is not desirable to suspend then resume the scheduler on
+			each iteration of the idle task.  Therefore, a preliminary
+			test of the expected idle time is performed without the
+			scheduler suspended.  The result here is not necessarily
+			valid. */
+			xExpectedIdleTime = prvGetExpectedIdleTime();
+
+			if( xExpectedIdleTime >= configEXPECTED_IDLE_TIME_BEFORE_SLEEP )
+			{
+				vTaskSuspendAll();
+				{
+					/* Now the scheduler is suspended, the expected idle
+					time can be sampled again, and this time its value can
+					be used. */
+					configASSERT( xNextTaskUnblockTime >= xTickCount );
+					xExpectedIdleTime = prvGetExpectedIdleTime();
+
+					/* Define the following macro to set xExpectedIdleTime to 0
+					if the application does not want
+					portSUPPRESS_TICKS_AND_SLEEP() to be called. */
+					configPRE_SUPPRESS_TICKS_AND_SLEEP_PROCESSING( xExpectedIdleTime );
+
+					if( xExpectedIdleTime >= configEXPECTED_IDLE_TIME_BEFORE_SLEEP )
+					{
+						traceLOW_POWER_IDLE_BEGIN();
+						portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime );
+						traceLOW_POWER_IDLE_END();
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				( void ) xTaskResumeAll();
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		#endif /* configUSE_TICKLESS_IDLE */
+	}
+}
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TICKLESS_IDLE != 0 )
+
+	eSleepModeStatus eTaskConfirmSleepModeStatus( void )
+	{
+	/* The idle task exists in addition to the application tasks. */
+	const UBaseType_t uxNonApplicationTasks = 1;
+	eSleepModeStatus eReturn = eStandardSleep;
+
+		/* This function must be called from a critical section. */
+
+		if( listCURRENT_LIST_LENGTH( &xPendingReadyList ) != 0 )
+		{
+			/* A task was made ready while the scheduler was suspended. */
+			eReturn = eAbortSleep;
+		}
+		else if( xYieldPending != pdFALSE )
+		{
+			/* A yield was pended while the scheduler was suspended. */
+			eReturn = eAbortSleep;
+		}
+		else
+		{
+			/* If all the tasks are in the suspended list (which might mean they
+			have an infinite block time rather than actually being suspended)
+			then it is safe to turn all clocks off and just wait for external
+			interrupts. */
+			if( listCURRENT_LIST_LENGTH( &xSuspendedTaskList ) == ( uxCurrentNumberOfTasks - uxNonApplicationTasks ) )
+			{
+				eReturn = eNoTasksWaitingTimeout;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+
+		return eReturn;
+	}
+
+#endif /* configUSE_TICKLESS_IDLE */
+/*-----------------------------------------------------------*/
+
+#if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
+
+	void vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, BaseType_t xIndex, void *pvValue )
+	{
+	TCB_t *pxTCB;
+
+		if( xIndex < configNUM_THREAD_LOCAL_STORAGE_POINTERS )
+		{
+			pxTCB = prvGetTCBFromHandle( xTaskToSet );
+			configASSERT( pxTCB != NULL );
+			pxTCB->pvThreadLocalStoragePointers[ xIndex ] = pvValue;
+		}
+	}
+
+#endif /* configNUM_THREAD_LOCAL_STORAGE_POINTERS */
+/*-----------------------------------------------------------*/
+
+#if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
+
+	void *pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, BaseType_t xIndex )
+	{
+	void *pvReturn = NULL;
+	TCB_t *pxTCB;
+
+		if( xIndex < configNUM_THREAD_LOCAL_STORAGE_POINTERS )
+		{
+			pxTCB = prvGetTCBFromHandle( xTaskToQuery );
+			pvReturn = pxTCB->pvThreadLocalStoragePointers[ xIndex ];
+		}
+		else
+		{
+			pvReturn = NULL;
+		}
+
+		return pvReturn;
+	}
+
+#endif /* configNUM_THREAD_LOCAL_STORAGE_POINTERS */
+/*-----------------------------------------------------------*/
+
+#if ( portUSING_MPU_WRAPPERS == 1 )
+
+	void vTaskAllocateMPURegions( TaskHandle_t xTaskToModify, const MemoryRegion_t * const xRegions )
+	{
+	TCB_t *pxTCB;
+
+		/* If null is passed in here then we are modifying the MPU settings of
+		the calling task. */
+		pxTCB = prvGetTCBFromHandle( xTaskToModify );
+
+		vPortStoreTaskMPUSettings( &( pxTCB->xMPUSettings ), xRegions, NULL, 0 );
+	}
+
+#endif /* portUSING_MPU_WRAPPERS */
+/*-----------------------------------------------------------*/
+
+static void prvInitialiseTaskLists( void )
+{
+UBaseType_t uxPriority;
+
+	for( uxPriority = ( UBaseType_t ) 0U; uxPriority < ( UBaseType_t ) configMAX_PRIORITIES; uxPriority++ )
+	{
+		vListInitialise( &( pxReadyTasksLists[ uxPriority ] ) );
+	}
+
+	vListInitialise( &xDelayedTaskList1 );
+	vListInitialise( &xDelayedTaskList2 );
+	vListInitialise( &xPendingReadyList );
+
+	#if ( INCLUDE_vTaskDelete == 1 )
+	{
+		vListInitialise( &xTasksWaitingTermination );
+	}
+	#endif /* INCLUDE_vTaskDelete */
+
+	#if ( INCLUDE_vTaskSuspend == 1 )
+	{
+		vListInitialise( &xSuspendedTaskList );
+	}
+	#endif /* INCLUDE_vTaskSuspend */
+
+	/* Start with pxDelayedTaskList using list1 and the pxOverflowDelayedTaskList
+	using list2. */
+	pxDelayedTaskList = &xDelayedTaskList1;
+	pxOverflowDelayedTaskList = &xDelayedTaskList2;
+}
+/*-----------------------------------------------------------*/
+
+static void prvCheckTasksWaitingTermination( void )
+{
+
+	/** THIS FUNCTION IS CALLED FROM THE RTOS IDLE TASK **/
+
+	#if ( INCLUDE_vTaskDelete == 1 )
+	{
+		TCB_t *pxTCB;
+
+		/* uxDeletedTasksWaitingCleanUp is used to prevent taskENTER_CRITICAL()
+		being called too often in the idle task. */
+		while( uxDeletedTasksWaitingCleanUp > ( UBaseType_t ) 0U )
+		{
+			taskENTER_CRITICAL();
+			{
+				pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xTasksWaitingTermination ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+				( void ) uxListRemove( &( pxTCB->xStateListItem ) );
+				--uxCurrentNumberOfTasks;
+				--uxDeletedTasksWaitingCleanUp;
+			}
+			taskEXIT_CRITICAL();
+
+			prvDeleteTCB( pxTCB );
+		}
+	}
+	#endif /* INCLUDE_vTaskDelete */
+}
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TRACE_FACILITY == 1 )
+
+	void vTaskGetInfo( TaskHandle_t xTask, TaskStatus_t *pxTaskStatus, BaseType_t xGetFreeStackSpace, eTaskState eState )
+	{
+	TCB_t *pxTCB;
+
+		/* xTask is NULL then get the state of the calling task. */
+		pxTCB = prvGetTCBFromHandle( xTask );
+
+		pxTaskStatus->xHandle = ( TaskHandle_t ) pxTCB;
+		pxTaskStatus->pcTaskName = ( const char * ) &( pxTCB->pcTaskName [ 0 ] );
+		pxTaskStatus->uxCurrentPriority = pxTCB->uxPriority;
+		pxTaskStatus->pxStackBase = pxTCB->pxStack;
+		pxTaskStatus->xTaskNumber = pxTCB->uxTCBNumber;
+
+		#if ( configUSE_MUTEXES == 1 )
+		{
+			pxTaskStatus->uxBasePriority = pxTCB->uxBasePriority;
+		}
+		#else
+		{
+			pxTaskStatus->uxBasePriority = 0;
+		}
+		#endif
+
+		#if ( configGENERATE_RUN_TIME_STATS == 1 )
+		{
+			pxTaskStatus->ulRunTimeCounter = pxTCB->ulRunTimeCounter;
+		}
+		#else
+		{
+			pxTaskStatus->ulRunTimeCounter = 0;
+		}
+		#endif
+
+		/* Obtaining the task state is a little fiddly, so is only done if the
+		value of eState passed into this function is eInvalid - otherwise the
+		state is just set to whatever is passed in. */
+		if( eState != eInvalid )
+		{
+			if( pxTCB == pxCurrentTCB )
+			{
+				pxTaskStatus->eCurrentState = eRunning;
+			}
+			else
+			{
+				pxTaskStatus->eCurrentState = eState;
+
+				#if ( INCLUDE_vTaskSuspend == 1 )
+				{
+					/* If the task is in the suspended list then there is a
+					chance it is actually just blocked indefinitely - so really
+					it should be reported as being in the Blocked state. */
+					if( eState == eSuspended )
+					{
+						vTaskSuspendAll();
+						{
+							if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )
+							{
+								pxTaskStatus->eCurrentState = eBlocked;
+							}
+						}
+						( void ) xTaskResumeAll();
+					}
+				}
+				#endif /* INCLUDE_vTaskSuspend */
+			}
+		}
+		else
+		{
+			pxTaskStatus->eCurrentState = eTaskGetState( pxTCB );
+		}
+
+		/* Obtaining the stack space takes some time, so the xGetFreeStackSpace
+		parameter is provided to allow it to be skipped. */
+		if( xGetFreeStackSpace != pdFALSE )
+		{
+			#if ( portSTACK_GROWTH > 0 )
+			{
+				pxTaskStatus->usStackHighWaterMark = prvTaskCheckFreeStackSpace( ( uint8_t * ) pxTCB->pxEndOfStack );
+			}
+			#else
+			{
+				pxTaskStatus->usStackHighWaterMark = prvTaskCheckFreeStackSpace( ( uint8_t * ) pxTCB->pxStack );
+			}
+			#endif
+		}
+		else
+		{
+			pxTaskStatus->usStackHighWaterMark = 0;
+		}
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	static UBaseType_t prvListTasksWithinSingleList( TaskStatus_t *pxTaskStatusArray, List_t *pxList, eTaskState eState )
+	{
+	configLIST_VOLATILE TCB_t *pxNextTCB, *pxFirstTCB;
+	UBaseType_t uxTask = 0;
+
+		if( listCURRENT_LIST_LENGTH( pxList ) > ( UBaseType_t ) 0 )
+		{
+			listGET_OWNER_OF_NEXT_ENTRY( pxFirstTCB, pxList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+
+			/* Populate an TaskStatus_t structure within the
+			pxTaskStatusArray array for each task that is referenced from
+			pxList.  See the definition of TaskStatus_t in task.h for the
+			meaning of each TaskStatus_t structure member. */
+			do
+			{
+				listGET_OWNER_OF_NEXT_ENTRY( pxNextTCB, pxList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+				vTaskGetInfo( ( TaskHandle_t ) pxNextTCB, &( pxTaskStatusArray[ uxTask ] ), pdTRUE, eState );
+				uxTask++;
+			} while( pxNextTCB != pxFirstTCB );
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		return uxTask;
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+#if ( ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) )
+
+	static configSTACK_DEPTH_TYPE prvTaskCheckFreeStackSpace( const uint8_t * pucStackByte )
+	{
+	uint32_t ulCount = 0U;
+
+		while( *pucStackByte == ( uint8_t ) tskSTACK_FILL_BYTE )
+		{
+			pucStackByte -= portSTACK_GROWTH;
+			ulCount++;
+		}
+
+		ulCount /= ( uint32_t ) sizeof( StackType_t ); /*lint !e961 Casting is not redundant on smaller architectures. */
+
+		return ( configSTACK_DEPTH_TYPE ) ulCount;
+	}
+
+#endif /* ( ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 )
+
+	/* uxTaskGetStackHighWaterMark() and uxTaskGetStackHighWaterMark2() are the
+	same except for their return type.  Using configSTACK_DEPTH_TYPE allows the
+	user to determine the return type.  It gets around the problem of the value
+	overflowing on 8-bit types without breaking backward compatibility for
+	applications that expect an 8-bit return type. */
+	configSTACK_DEPTH_TYPE uxTaskGetStackHighWaterMark2( TaskHandle_t xTask )
+	{
+	TCB_t *pxTCB;
+	uint8_t *pucEndOfStack;
+	configSTACK_DEPTH_TYPE uxReturn;
+
+		/* uxTaskGetStackHighWaterMark() and uxTaskGetStackHighWaterMark2() are
+		the same except for their return type.  Using configSTACK_DEPTH_TYPE
+		allows the user to determine the return type.  It gets around the
+		problem of the value overflowing on 8-bit types without breaking
+		backward compatibility for applications that expect an 8-bit return
+		type. */
+
+		pxTCB = prvGetTCBFromHandle( xTask );
+
+		#if portSTACK_GROWTH < 0
+		{
+			pucEndOfStack = ( uint8_t * ) pxTCB->pxStack;
+		}
+		#else
+		{
+			pucEndOfStack = ( uint8_t * ) pxTCB->pxEndOfStack;
+		}
+		#endif
+
+		uxReturn = prvTaskCheckFreeStackSpace( pucEndOfStack );
+
+		return uxReturn;
+	}
+
+#endif /* INCLUDE_uxTaskGetStackHighWaterMark2 */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 )
+
+	UBaseType_t uxTaskGetStackHighWaterMark( TaskHandle_t xTask )
+	{
+	TCB_t *pxTCB;
+	uint8_t *pucEndOfStack;
+	UBaseType_t uxReturn;
+
+		pxTCB = prvGetTCBFromHandle( xTask );
+
+		#if portSTACK_GROWTH < 0
+		{
+			pucEndOfStack = ( uint8_t * ) pxTCB->pxStack;
+		}
+		#else
+		{
+			pucEndOfStack = ( uint8_t * ) pxTCB->pxEndOfStack;
+		}
+		#endif
+
+		uxReturn = ( UBaseType_t ) prvTaskCheckFreeStackSpace( pucEndOfStack );
+
+		return uxReturn;
+	}
+
+#endif /* INCLUDE_uxTaskGetStackHighWaterMark */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskDelete == 1 )
+
+	static void prvDeleteTCB( TCB_t *pxTCB )
+	{
+		/* This call is required specifically for the TriCore port.  It must be
+		above the vPortFree() calls.  The call is also used by ports/demos that
+		want to allocate and clean RAM statically. */
+		portCLEAN_UP_TCB( pxTCB );
+
+		/* Free up the memory allocated by the scheduler for the task.  It is up
+		to the task to free any memory allocated at the application level.
+		See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html
+		for additional information. */
+		#if ( configUSE_NEWLIB_REENTRANT == 1 )
+		{
+			_reclaim_reent( &( pxTCB->xNewLib_reent ) );
+		}
+		#endif /* configUSE_NEWLIB_REENTRANT */
+
+		#if( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 0 ) && ( portUSING_MPU_WRAPPERS == 0 ) )
+		{
+			/* The task can only have been allocated dynamically - free both
+			the stack and TCB. */
+			vPortFree( pxTCB->pxStack );
+			vPortFree( pxTCB );
+		}
+		#elif( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */
+		{
+			/* The task could have been allocated statically or dynamically, so
+			check what was statically allocated before trying to free the
+			memory. */
+			if( pxTCB->ucStaticallyAllocated == tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB )
+			{
+				/* Both the stack and TCB were allocated dynamically, so both
+				must be freed. */
+				vPortFree( pxTCB->pxStack );
+				vPortFree( pxTCB );
+			}
+			else if( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_ONLY )
+			{
+				/* Only the stack was statically allocated, so the TCB is the
+				only memory that must be freed. */
+				vPortFree( pxTCB );
+			}
+			else
+			{
+				/* Neither the stack nor the TCB were allocated dynamically, so
+				nothing needs to be freed. */
+				configASSERT( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_AND_TCB	);
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+	}
+
+#endif /* INCLUDE_vTaskDelete */
+/*-----------------------------------------------------------*/
+
+static void prvResetNextTaskUnblockTime( void )
+{
+TCB_t *pxTCB;
+
+	if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE )
+	{
+		/* The new current delayed list is empty.  Set xNextTaskUnblockTime to
+		the maximum possible value so it is	extremely unlikely that the
+		if( xTickCount >= xNextTaskUnblockTime ) test will pass until
+		there is an item in the delayed list. */
+		xNextTaskUnblockTime = portMAX_DELAY;
+	}
+	else
+	{
+		/* The new current delayed list is not empty, get the value of
+		the item at the head of the delayed list.  This is the time at
+		which the task at the head of the delayed list should be removed
+		from the Blocked state. */
+		( pxTCB ) = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+		xNextTaskUnblockTime = listGET_LIST_ITEM_VALUE( &( ( pxTCB )->xStateListItem ) );
+	}
+}
+/*-----------------------------------------------------------*/
+
+#if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) )
+
+	TaskHandle_t xTaskGetCurrentTaskHandle( void )
+	{
+	TaskHandle_t xReturn;
+
+		/* A critical section is not required as this is not called from
+		an interrupt and the current TCB will always be the same for any
+		individual execution thread. */
+		xReturn = pxCurrentTCB;
+
+		return xReturn;
+	}
+
+#endif /* ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
+
+	BaseType_t xTaskGetSchedulerState( void )
+	{
+	BaseType_t xReturn;
+
+		if( xSchedulerRunning == pdFALSE )
+		{
+			xReturn = taskSCHEDULER_NOT_STARTED;
+		}
+		else
+		{
+			if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
+			{
+				xReturn = taskSCHEDULER_RUNNING;
+			}
+			else
+			{
+				xReturn = taskSCHEDULER_SUSPENDED;
+			}
+		}
+
+		return xReturn;
+	}
+
+#endif /* ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_MUTEXES == 1 )
+
+	BaseType_t xTaskPriorityInherit( TaskHandle_t const pxMutexHolder )
+	{
+	TCB_t * const pxMutexHolderTCB = pxMutexHolder;
+	BaseType_t xReturn = pdFALSE;
+
+		/* If the mutex was given back by an interrupt while the queue was
+		locked then the mutex holder might now be NULL.  _RB_ Is this still
+		needed as interrupts can no longer use mutexes? */
+		if( pxMutexHolder != NULL )
+		{
+			/* If the holder of the mutex has a priority below the priority of
+			the task attempting to obtain the mutex then it will temporarily
+			inherit the priority of the task attempting to obtain the mutex. */
+			if( pxMutexHolderTCB->uxPriority < pxCurrentTCB->uxPriority )
+			{
+				/* Adjust the mutex holder state to account for its new
+				priority.  Only reset the event list item value if the value is
+				not being used for anything else. */
+				if( ( listGET_LIST_ITEM_VALUE( &( pxMutexHolderTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL )
+				{
+					listSET_LIST_ITEM_VALUE( &( pxMutexHolderTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxCurrentTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+
+				/* If the task being modified is in the ready state it will need
+				to be moved into a new list. */
+				if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ pxMutexHolderTCB->uxPriority ] ), &( pxMutexHolderTCB->xStateListItem ) ) != pdFALSE )
+				{
+					if( uxListRemove( &( pxMutexHolderTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
+					{
+						/* It is known that the task is in its ready list so
+						there is no need to check again and the port level
+						reset macro can be called directly. */
+						portRESET_READY_PRIORITY( pxMutexHolderTCB->uxPriority, uxTopReadyPriority );
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+
+					/* Inherit the priority before being moved into the new list. */
+					pxMutexHolderTCB->uxPriority = pxCurrentTCB->uxPriority;
+					prvAddTaskToReadyList( pxMutexHolderTCB );
+				}
+				else
+				{
+					/* Just inherit the priority. */
+					pxMutexHolderTCB->uxPriority = pxCurrentTCB->uxPriority;
+				}
+
+				traceTASK_PRIORITY_INHERIT( pxMutexHolderTCB, pxCurrentTCB->uxPriority );
+
+				/* Inheritance occurred. */
+				xReturn = pdTRUE;
+			}
+			else
+			{
+				if( pxMutexHolderTCB->uxBasePriority < pxCurrentTCB->uxPriority )
+				{
+					/* The base priority of the mutex holder is lower than the
+					priority of the task attempting to take the mutex, but the
+					current priority of the mutex holder is not lower than the
+					priority of the task attempting to take the mutex.
+					Therefore the mutex holder must have already inherited a
+					priority, but inheritance would have occurred if that had
+					not been the case. */
+					xReturn = pdTRUE;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		return xReturn;
+	}
+
+#endif /* configUSE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_MUTEXES == 1 )
+
+	BaseType_t xTaskPriorityDisinherit( TaskHandle_t const pxMutexHolder )
+	{
+	TCB_t * const pxTCB = pxMutexHolder;
+	BaseType_t xReturn = pdFALSE;
+
+		if( pxMutexHolder != NULL )
+		{
+			/* A task can only have an inherited priority if it holds the mutex.
+			If the mutex is held by a task then it cannot be given from an
+			interrupt, and if a mutex is given by the holding task then it must
+			be the running state task. */
+			configASSERT( pxTCB == pxCurrentTCB );
+			configASSERT( pxTCB->uxMutexesHeld );
+			( pxTCB->uxMutexesHeld )--;
+
+			/* Has the holder of the mutex inherited the priority of another
+			task? */
+			if( pxTCB->uxPriority != pxTCB->uxBasePriority )
+			{
+				/* Only disinherit if no other mutexes are held. */
+				if( pxTCB->uxMutexesHeld == ( UBaseType_t ) 0 )
+				{
+					/* A task can only have an inherited priority if it holds
+					the mutex.  If the mutex is held by a task then it cannot be
+					given from an interrupt, and if a mutex is given by the
+					holding task then it must be the running state task.  Remove
+					the holding task from the ready/delayed list. */
+					if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
+					{
+						taskRESET_READY_PRIORITY( pxTCB->uxPriority );
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+
+					/* Disinherit the priority before adding the task into the
+					new	ready list. */
+					traceTASK_PRIORITY_DISINHERIT( pxTCB, pxTCB->uxBasePriority );
+					pxTCB->uxPriority = pxTCB->uxBasePriority;
+
+					/* Reset the event list item value.  It cannot be in use for
+					any other purpose if this task is running, and it must be
+					running to give back the mutex. */
+					listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+					prvAddTaskToReadyList( pxTCB );
+
+					/* Return true to indicate that a context switch is required.
+					This is only actually required in the corner case whereby
+					multiple mutexes were held and the mutexes were given back
+					in an order different to that in which they were taken.
+					If a context switch did not occur when the first mutex was
+					returned, even if a task was waiting on it, then a context
+					switch should occur when the last mutex is returned whether
+					a task is waiting on it or not. */
+					xReturn = pdTRUE;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		return xReturn;
+	}
+
+#endif /* configUSE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_MUTEXES == 1 )
+
+	void vTaskPriorityDisinheritAfterTimeout( TaskHandle_t const pxMutexHolder, UBaseType_t uxHighestPriorityWaitingTask )
+	{
+	TCB_t * const pxTCB = pxMutexHolder;
+	UBaseType_t uxPriorityUsedOnEntry, uxPriorityToUse;
+	const UBaseType_t uxOnlyOneMutexHeld = ( UBaseType_t ) 1;
+
+		if( pxMutexHolder != NULL )
+		{
+			/* If pxMutexHolder is not NULL then the holder must hold at least
+			one mutex. */
+			configASSERT( pxTCB->uxMutexesHeld );
+
+			/* Determine the priority to which the priority of the task that
+			holds the mutex should be set.  This will be the greater of the
+			holding task's base priority and the priority of the highest
+			priority task that is waiting to obtain the mutex. */
+			if( pxTCB->uxBasePriority < uxHighestPriorityWaitingTask )
+			{
+				uxPriorityToUse = uxHighestPriorityWaitingTask;
+			}
+			else
+			{
+				uxPriorityToUse = pxTCB->uxBasePriority;
+			}
+
+			/* Does the priority need to change? */
+			if( pxTCB->uxPriority != uxPriorityToUse )
+			{
+				/* Only disinherit if no other mutexes are held.  This is a
+				simplification in the priority inheritance implementation.  If
+				the task that holds the mutex is also holding other mutexes then
+				the other mutexes may have caused the priority inheritance. */
+				if( pxTCB->uxMutexesHeld == uxOnlyOneMutexHeld )
+				{
+					/* If a task has timed out because it already holds the
+					mutex it was trying to obtain then it cannot of inherited
+					its own priority. */
+					configASSERT( pxTCB != pxCurrentTCB );
+
+					/* Disinherit the priority, remembering the previous
+					priority to facilitate determining the subject task's
+					state. */
+					traceTASK_PRIORITY_DISINHERIT( pxTCB, pxTCB->uxBasePriority );
+					uxPriorityUsedOnEntry = pxTCB->uxPriority;
+					pxTCB->uxPriority = uxPriorityToUse;
+
+					/* Only reset the event list item value if the value is not
+					being used for anything else. */
+					if( ( listGET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL )
+					{
+						listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriorityToUse ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+
+					/* If the running task is not the task that holds the mutex
+					then the task that holds the mutex could be in either the
+					Ready, Blocked or Suspended states.  Only remove the task
+					from its current state list if it is in the Ready state as
+					the task's priority is going to change and there is one
+					Ready list per priority. */
+					if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ uxPriorityUsedOnEntry ] ), &( pxTCB->xStateListItem ) ) != pdFALSE )
+					{
+						if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
+						{
+							/* It is known that the task is in its ready list so
+							there is no need to check again and the port level
+							reset macro can be called directly. */
+							portRESET_READY_PRIORITY( pxTCB->uxPriority, uxTopReadyPriority );
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+
+						prvAddTaskToReadyList( pxTCB );
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+
+#endif /* configUSE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+#if ( portCRITICAL_NESTING_IN_TCB == 1 )
+
+	void vTaskEnterCritical( void )
+	{
+		portDISABLE_INTERRUPTS();
+
+		if( xSchedulerRunning != pdFALSE )
+		{
+			( pxCurrentTCB->uxCriticalNesting )++;
+
+			/* This is not the interrupt safe version of the enter critical
+			function so	assert() if it is being called from an interrupt
+			context.  Only API functions that end in "FromISR" can be used in an
+			interrupt.  Only assert if the critical nesting count is 1 to
+			protect against recursive calls if the assert function also uses a
+			critical section. */
+			if( pxCurrentTCB->uxCriticalNesting == 1 )
+			{
+				portASSERT_IF_IN_ISR();
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+
+#endif /* portCRITICAL_NESTING_IN_TCB */
+/*-----------------------------------------------------------*/
+
+#if ( portCRITICAL_NESTING_IN_TCB == 1 )
+
+	void vTaskExitCritical( void )
+	{
+		if( xSchedulerRunning != pdFALSE )
+		{
+			if( pxCurrentTCB->uxCriticalNesting > 0U )
+			{
+				( pxCurrentTCB->uxCriticalNesting )--;
+
+				if( pxCurrentTCB->uxCriticalNesting == 0U )
+				{
+					portENABLE_INTERRUPTS();
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+
+#endif /* portCRITICAL_NESTING_IN_TCB */
+/*-----------------------------------------------------------*/
+
+#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) )
+
+	static char *prvWriteNameToBuffer( char *pcBuffer, const char *pcTaskName )
+	{
+	size_t x;
+
+		/* Start by copying the entire string. */
+		strcpy( pcBuffer, pcTaskName );
+
+		/* Pad the end of the string with spaces to ensure columns line up when
+		printed out. */
+		for( x = strlen( pcBuffer ); x < ( size_t ) ( configMAX_TASK_NAME_LEN - 1 ); x++ )
+		{
+			pcBuffer[ x ] = ' ';
+		}
+
+		/* Terminate. */
+		pcBuffer[ x ] = ( char ) 0x00;
+
+		/* Return the new end of string. */
+		return &( pcBuffer[ x ] );
+	}
+
+#endif /* ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) */
+/*-----------------------------------------------------------*/
+
+#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+
+	void vTaskList( char * pcWriteBuffer )
+	{
+	TaskStatus_t *pxTaskStatusArray;
+	UBaseType_t uxArraySize, x;
+	char cStatus;
+
+		/*
+		 * PLEASE NOTE:
+		 *
+		 * This function is provided for convenience only, and is used by many
+		 * of the demo applications.  Do not consider it to be part of the
+		 * scheduler.
+		 *
+		 * vTaskList() calls uxTaskGetSystemState(), then formats part of the
+		 * uxTaskGetSystemState() output into a human readable table that
+		 * displays task names, states and stack usage.
+		 *
+		 * vTaskList() has a dependency on the sprintf() C library function that
+		 * might bloat the code size, use a lot of stack, and provide different
+		 * results on different platforms.  An alternative, tiny, third party,
+		 * and limited functionality implementation of sprintf() is provided in
+		 * many of the FreeRTOS/Demo sub-directories in a file called
+		 * printf-stdarg.c (note printf-stdarg.c does not provide a full
+		 * snprintf() implementation!).
+		 *
+		 * It is recommended that production systems call uxTaskGetSystemState()
+		 * directly to get access to raw stats data, rather than indirectly
+		 * through a call to vTaskList().
+		 */
+
+
+		/* Make sure the write buffer does not contain a string. */
+		*pcWriteBuffer = ( char ) 0x00;
+
+		/* Take a snapshot of the number of tasks in case it changes while this
+		function is executing. */
+		uxArraySize = uxCurrentNumberOfTasks;
+
+		/* Allocate an array index for each task.  NOTE!  if
+		configSUPPORT_DYNAMIC_ALLOCATION is set to 0 then pvPortMalloc() will
+		equate to NULL. */
+		pxTaskStatusArray = pvPortMalloc( uxCurrentNumberOfTasks * sizeof( TaskStatus_t ) ); /*lint !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack and this allocation allocates a struct that has the alignment requirements of a pointer. */
+
+		if( pxTaskStatusArray != NULL )
+		{
+			/* Generate the (binary) data. */
+			uxArraySize = uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, NULL );
+
+			/* Create a human readable table from the binary data. */
+			for( x = 0; x < uxArraySize; x++ )
+			{
+				switch( pxTaskStatusArray[ x ].eCurrentState )
+				{
+					case eRunning:		cStatus = tskRUNNING_CHAR;
+										break;
+
+					case eReady:		cStatus = tskREADY_CHAR;
+										break;
+
+					case eBlocked:		cStatus = tskBLOCKED_CHAR;
+										break;
+
+					case eSuspended:	cStatus = tskSUSPENDED_CHAR;
+										break;
+
+					case eDeleted:		cStatus = tskDELETED_CHAR;
+										break;
+
+					case eInvalid:		/* Fall through. */
+					default:			/* Should not get here, but it is included
+										to prevent static checking errors. */
+										cStatus = ( char ) 0x00;
+										break;
+				}
+
+				/* Write the task name to the string, padding with spaces so it
+				can be printed in tabular form more easily. */
+				pcWriteBuffer = prvWriteNameToBuffer( pcWriteBuffer, pxTaskStatusArray[ x ].pcTaskName );
+
+				/* Write the rest of the string. */
+				sprintf( pcWriteBuffer, "\t%c\t%u\t%u\t%u\r\n", cStatus, ( unsigned int ) pxTaskStatusArray[ x ].uxCurrentPriority, ( unsigned int ) pxTaskStatusArray[ x ].usStackHighWaterMark, ( unsigned int ) pxTaskStatusArray[ x ].xTaskNumber ); /*lint !e586 sprintf() allowed as this is compiled with many compilers and this is a utility function only - not part of the core kernel implementation. */
+				pcWriteBuffer += strlen( pcWriteBuffer ); /*lint !e9016 Pointer arithmetic ok on char pointers especially as in this case where it best denotes the intent of the code. */
+			}
+
+			/* Free the array again.  NOTE!  If configSUPPORT_DYNAMIC_ALLOCATION
+			is 0 then vPortFree() will be #defined to nothing. */
+			vPortFree( pxTaskStatusArray );
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+
+#endif /* ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */
+/*----------------------------------------------------------*/
+
+#if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+
+	void vTaskGetRunTimeStats( char *pcWriteBuffer )
+	{
+	TaskStatus_t *pxTaskStatusArray;
+	UBaseType_t uxArraySize, x;
+	uint32_t ulTotalTime, ulStatsAsPercentage;
+
+		#if( configUSE_TRACE_FACILITY != 1 )
+		{
+			#error configUSE_TRACE_FACILITY must also be set to 1 in FreeRTOSConfig.h to use vTaskGetRunTimeStats().
+		}
+		#endif
+
+		/*
+		 * PLEASE NOTE:
+		 *
+		 * This function is provided for convenience only, and is used by many
+		 * of the demo applications.  Do not consider it to be part of the
+		 * scheduler.
+		 *
+		 * vTaskGetRunTimeStats() calls uxTaskGetSystemState(), then formats part
+		 * of the uxTaskGetSystemState() output into a human readable table that
+		 * displays the amount of time each task has spent in the Running state
+		 * in both absolute and percentage terms.
+		 *
+		 * vTaskGetRunTimeStats() has a dependency on the sprintf() C library
+		 * function that might bloat the code size, use a lot of stack, and
+		 * provide different results on different platforms.  An alternative,
+		 * tiny, third party, and limited functionality implementation of
+		 * sprintf() is provided in many of the FreeRTOS/Demo sub-directories in
+		 * a file called printf-stdarg.c (note printf-stdarg.c does not provide
+		 * a full snprintf() implementation!).
+		 *
+		 * It is recommended that production systems call uxTaskGetSystemState()
+		 * directly to get access to raw stats data, rather than indirectly
+		 * through a call to vTaskGetRunTimeStats().
+		 */
+
+		/* Make sure the write buffer does not contain a string. */
+		*pcWriteBuffer = ( char ) 0x00;
+
+		/* Take a snapshot of the number of tasks in case it changes while this
+		function is executing. */
+		uxArraySize = uxCurrentNumberOfTasks;
+
+		/* Allocate an array index for each task.  NOTE!  If
+		configSUPPORT_DYNAMIC_ALLOCATION is set to 0 then pvPortMalloc() will
+		equate to NULL. */
+		pxTaskStatusArray = pvPortMalloc( uxCurrentNumberOfTasks * sizeof( TaskStatus_t ) ); /*lint !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack and this allocation allocates a struct that has the alignment requirements of a pointer. */
+
+		if( pxTaskStatusArray != NULL )
+		{
+			/* Generate the (binary) data. */
+			uxArraySize = uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, &ulTotalTime );
+
+			/* For percentage calculations. */
+			ulTotalTime /= 100UL;
+
+			/* Avoid divide by zero errors. */
+			if( ulTotalTime > 0UL )
+			{
+				/* Create a human readable table from the binary data. */
+				for( x = 0; x < uxArraySize; x++ )
+				{
+					/* What percentage of the total run time has the task used?
+					This will always be rounded down to the nearest integer.
+					ulTotalRunTimeDiv100 has already been divided by 100. */
+					ulStatsAsPercentage = pxTaskStatusArray[ x ].ulRunTimeCounter / ulTotalTime;
+
+					/* Write the task name to the string, padding with
+					spaces so it can be printed in tabular form more
+					easily. */
+					pcWriteBuffer = prvWriteNameToBuffer( pcWriteBuffer, pxTaskStatusArray[ x ].pcTaskName );
+
+					if( ulStatsAsPercentage > 0UL )
+					{
+						#ifdef portLU_PRINTF_SPECIFIER_REQUIRED
+						{
+							sprintf( pcWriteBuffer, "\t%lu\t\t%lu%%\r\n", pxTaskStatusArray[ x ].ulRunTimeCounter, ulStatsAsPercentage );
+						}
+						#else
+						{
+							/* sizeof( int ) == sizeof( long ) so a smaller
+							printf() library can be used. */
+							sprintf( pcWriteBuffer, "\t%u\t\t%u%%\r\n", ( unsigned int ) pxTaskStatusArray[ x ].ulRunTimeCounter, ( unsigned int ) ulStatsAsPercentage ); /*lint !e586 sprintf() allowed as this is compiled with many compilers and this is a utility function only - not part of the core kernel implementation. */
+						}
+						#endif
+					}
+					else
+					{
+						/* If the percentage is zero here then the task has
+						consumed less than 1% of the total run time. */
+						#ifdef portLU_PRINTF_SPECIFIER_REQUIRED
+						{
+							sprintf( pcWriteBuffer, "\t%lu\t\t<1%%\r\n", pxTaskStatusArray[ x ].ulRunTimeCounter );
+						}
+						#else
+						{
+							/* sizeof( int ) == sizeof( long ) so a smaller
+							printf() library can be used. */
+							sprintf( pcWriteBuffer, "\t%u\t\t<1%%\r\n", ( unsigned int ) pxTaskStatusArray[ x ].ulRunTimeCounter ); /*lint !e586 sprintf() allowed as this is compiled with many compilers and this is a utility function only - not part of the core kernel implementation. */
+						}
+						#endif
+					}
+
+					pcWriteBuffer += strlen( pcWriteBuffer ); /*lint !e9016 Pointer arithmetic ok on char pointers especially as in this case where it best denotes the intent of the code. */
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+
+			/* Free the array again.  NOTE!  If configSUPPORT_DYNAMIC_ALLOCATION
+			is 0 then vPortFree() will be #defined to nothing. */
+			vPortFree( pxTaskStatusArray );
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+
+#endif /* ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+TickType_t uxTaskResetEventItemValue( void )
+{
+TickType_t uxReturn;
+
+	uxReturn = listGET_LIST_ITEM_VALUE( &( pxCurrentTCB->xEventListItem ) );
+
+	/* Reset the event list item to its normal value - so it can be used with
+	queues and semaphores. */
+	listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xEventListItem ), ( ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxCurrentTCB->uxPriority ) ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+
+	return uxReturn;
+}
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_MUTEXES == 1 )
+
+	TaskHandle_t pvTaskIncrementMutexHeldCount( void )
+	{
+		/* If xSemaphoreCreateMutex() is called before any tasks have been created
+		then pxCurrentTCB will be NULL. */
+		if( pxCurrentTCB != NULL )
+		{
+			( pxCurrentTCB->uxMutexesHeld )++;
+		}
+
+		return pxCurrentTCB;
+	}
+
+#endif /* configUSE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TASK_NOTIFICATIONS == 1 )
+
+	uint32_t ulTaskNotifyTake( BaseType_t xClearCountOnExit, TickType_t xTicksToWait )
+	{
+	uint32_t ulReturn;
+
+		taskENTER_CRITICAL();
+		{
+			/* Only block if the notification count is not already non-zero. */
+			if( pxCurrentTCB->ulNotifiedValue == 0UL )
+			{
+				/* Mark this task as waiting for a notification. */
+				pxCurrentTCB->ucNotifyState = taskWAITING_NOTIFICATION;
+
+				if( xTicksToWait > ( TickType_t ) 0 )
+				{
+					prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE );
+					traceTASK_NOTIFY_TAKE_BLOCK();
+
+					/* All ports are written to allow a yield in a critical
+					section (some will yield immediately, others wait until the
+					critical section exits) - but it is not something that
+					application code should ever do. */
+					portYIELD_WITHIN_API();
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		taskEXIT_CRITICAL();
+
+		taskENTER_CRITICAL();
+		{
+			traceTASK_NOTIFY_TAKE();
+			ulReturn = pxCurrentTCB->ulNotifiedValue;
+
+			if( ulReturn != 0UL )
+			{
+				if( xClearCountOnExit != pdFALSE )
+				{
+					pxCurrentTCB->ulNotifiedValue = 0UL;
+				}
+				else
+				{
+					pxCurrentTCB->ulNotifiedValue = ulReturn - ( uint32_t ) 1;
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+
+			pxCurrentTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION;
+		}
+		taskEXIT_CRITICAL();
+
+		return ulReturn;
+	}
+
+#endif /* configUSE_TASK_NOTIFICATIONS */
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TASK_NOTIFICATIONS == 1 )
+
+	BaseType_t xTaskNotifyWait( uint32_t ulBitsToClearOnEntry, uint32_t ulBitsToClearOnExit, uint32_t *pulNotificationValue, TickType_t xTicksToWait )
+	{
+	BaseType_t xReturn;
+
+		taskENTER_CRITICAL();
+		{
+			/* Only block if a notification is not already pending. */
+			if( pxCurrentTCB->ucNotifyState != taskNOTIFICATION_RECEIVED )
+			{
+				/* Clear bits in the task's notification value as bits may get
+				set	by the notifying task or interrupt.  This can be used to
+				clear the value to zero. */
+				pxCurrentTCB->ulNotifiedValue &= ~ulBitsToClearOnEntry;
+
+				/* Mark this task as waiting for a notification. */
+				pxCurrentTCB->ucNotifyState = taskWAITING_NOTIFICATION;
+
+				if( xTicksToWait > ( TickType_t ) 0 )
+				{
+					prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE );
+					traceTASK_NOTIFY_WAIT_BLOCK();
+
+					/* All ports are written to allow a yield in a critical
+					section (some will yield immediately, others wait until the
+					critical section exits) - but it is not something that
+					application code should ever do. */
+					portYIELD_WITHIN_API();
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		taskEXIT_CRITICAL();
+
+		taskENTER_CRITICAL();
+		{
+			traceTASK_NOTIFY_WAIT();
+
+			if( pulNotificationValue != NULL )
+			{
+				/* Output the current notification value, which may or may not
+				have changed. */
+				*pulNotificationValue = pxCurrentTCB->ulNotifiedValue;
+			}
+
+			/* If ucNotifyValue is set then either the task never entered the
+			blocked state (because a notification was already pending) or the
+			task unblocked because of a notification.  Otherwise the task
+			unblocked because of a timeout. */
+			if( pxCurrentTCB->ucNotifyState != taskNOTIFICATION_RECEIVED )
+			{
+				/* A notification was not received. */
+				xReturn = pdFALSE;
+			}
+			else
+			{
+				/* A notification was already pending or a notification was
+				received while the task was waiting. */
+				pxCurrentTCB->ulNotifiedValue &= ~ulBitsToClearOnExit;
+				xReturn = pdTRUE;
+			}
+
+			pxCurrentTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION;
+		}
+		taskEXIT_CRITICAL();
+
+		return xReturn;
+	}
+
+#endif /* configUSE_TASK_NOTIFICATIONS */
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TASK_NOTIFICATIONS == 1 )
+
+	BaseType_t xTaskGenericNotify( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue )
+	{
+	TCB_t * pxTCB;
+	BaseType_t xReturn = pdPASS;
+	uint8_t ucOriginalNotifyState;
+
+		configASSERT( xTaskToNotify );
+		pxTCB = xTaskToNotify;
+
+		taskENTER_CRITICAL();
+		{
+			if( pulPreviousNotificationValue != NULL )
+			{
+				*pulPreviousNotificationValue = pxTCB->ulNotifiedValue;
+			}
+
+			ucOriginalNotifyState = pxTCB->ucNotifyState;
+
+			pxTCB->ucNotifyState = taskNOTIFICATION_RECEIVED;
+
+			switch( eAction )
+			{
+				case eSetBits	:
+					pxTCB->ulNotifiedValue |= ulValue;
+					break;
+
+				case eIncrement	:
+					( pxTCB->ulNotifiedValue )++;
+					break;
+
+				case eSetValueWithOverwrite	:
+					pxTCB->ulNotifiedValue = ulValue;
+					break;
+
+				case eSetValueWithoutOverwrite :
+					if( ucOriginalNotifyState != taskNOTIFICATION_RECEIVED )
+					{
+						pxTCB->ulNotifiedValue = ulValue;
+					}
+					else
+					{
+						/* The value could not be written to the task. */
+						xReturn = pdFAIL;
+					}
+					break;
+
+				case eNoAction:
+					/* The task is being notified without its notify value being
+					updated. */
+					break;
+
+				default:
+					/* Should not get here if all enums are handled.
+					Artificially force an assert by testing a value the
+					compiler can't assume is const. */
+					configASSERT( pxTCB->ulNotifiedValue == ~0UL );
+
+					break;
+			}
+
+			traceTASK_NOTIFY();
+
+			/* If the task is in the blocked state specifically to wait for a
+			notification then unblock it now. */
+			if( ucOriginalNotifyState == taskWAITING_NOTIFICATION )
+			{
+				( void ) uxListRemove( &( pxTCB->xStateListItem ) );
+				prvAddTaskToReadyList( pxTCB );
+
+				/* The task should not have been on an event list. */
+				configASSERT( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL );
+
+				#if( configUSE_TICKLESS_IDLE != 0 )
+				{
+					/* If a task is blocked waiting for a notification then
+					xNextTaskUnblockTime might be set to the blocked task's time
+					out time.  If the task is unblocked for a reason other than
+					a timeout xNextTaskUnblockTime is normally left unchanged,
+					because it will automatically get reset to a new value when
+					the tick count equals xNextTaskUnblockTime.  However if
+					tickless idling is used it might be more important to enter
+					sleep mode at the earliest possible time - so reset
+					xNextTaskUnblockTime here to ensure it is updated at the
+					earliest possible time. */
+					prvResetNextTaskUnblockTime();
+				}
+				#endif
+
+				if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )
+				{
+					/* The notified task has a priority above the currently
+					executing task so a yield is required. */
+					taskYIELD_IF_USING_PREEMPTION();
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		taskEXIT_CRITICAL();
+
+		return xReturn;
+	}
+
+#endif /* configUSE_TASK_NOTIFICATIONS */
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TASK_NOTIFICATIONS == 1 )
+
+	BaseType_t xTaskGenericNotifyFromISR( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue, BaseType_t *pxHigherPriorityTaskWoken )
+	{
+	TCB_t * pxTCB;
+	uint8_t ucOriginalNotifyState;
+	BaseType_t xReturn = pdPASS;
+	UBaseType_t uxSavedInterruptStatus;
+
+		configASSERT( xTaskToNotify );
+
+		/* RTOS ports that support interrupt nesting have the concept of a
+		maximum	system call (or maximum API call) interrupt priority.
+		Interrupts that are	above the maximum system call priority are keep
+		permanently enabled, even when the RTOS kernel is in a critical section,
+		but cannot make any calls to FreeRTOS API functions.  If configASSERT()
+		is defined in FreeRTOSConfig.h then
+		portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
+		failure if a FreeRTOS API function is called from an interrupt that has
+		been assigned a priority above the configured maximum system call
+		priority.  Only FreeRTOS functions that end in FromISR can be called
+		from interrupts	that have been assigned a priority at or (logically)
+		below the maximum system call interrupt priority.  FreeRTOS maintains a
+		separate interrupt safe API to ensure interrupt entry is as fast and as
+		simple as possible.  More information (albeit Cortex-M specific) is
+		provided on the following link:
+		http://www.freertos.org/RTOS-Cortex-M3-M4.html */
+		portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+
+		pxTCB = xTaskToNotify;
+
+		uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+		{
+			if( pulPreviousNotificationValue != NULL )
+			{
+				*pulPreviousNotificationValue = pxTCB->ulNotifiedValue;
+			}
+
+			ucOriginalNotifyState = pxTCB->ucNotifyState;
+			pxTCB->ucNotifyState = taskNOTIFICATION_RECEIVED;
+
+			switch( eAction )
+			{
+				case eSetBits	:
+					pxTCB->ulNotifiedValue |= ulValue;
+					break;
+
+				case eIncrement	:
+					( pxTCB->ulNotifiedValue )++;
+					break;
+
+				case eSetValueWithOverwrite	:
+					pxTCB->ulNotifiedValue = ulValue;
+					break;
+
+				case eSetValueWithoutOverwrite :
+					if( ucOriginalNotifyState != taskNOTIFICATION_RECEIVED )
+					{
+						pxTCB->ulNotifiedValue = ulValue;
+					}
+					else
+					{
+						/* The value could not be written to the task. */
+						xReturn = pdFAIL;
+					}
+					break;
+
+				case eNoAction :
+					/* The task is being notified without its notify value being
+					updated. */
+					break;
+
+				default:
+					/* Should not get here if all enums are handled.
+					Artificially force an assert by testing a value the
+					compiler can't assume is const. */
+					configASSERT( pxTCB->ulNotifiedValue == ~0UL );
+					break;
+			}
+
+			traceTASK_NOTIFY_FROM_ISR();
+
+			/* If the task is in the blocked state specifically to wait for a
+			notification then unblock it now. */
+			if( ucOriginalNotifyState == taskWAITING_NOTIFICATION )
+			{
+				/* The task should not have been on an event list. */
+				configASSERT( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL );
+
+				if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
+				{
+					( void ) uxListRemove( &( pxTCB->xStateListItem ) );
+					prvAddTaskToReadyList( pxTCB );
+				}
+				else
+				{
+					/* The delayed and ready lists cannot be accessed, so hold
+					this task pending until the scheduler is resumed. */
+					vListInsertEnd( &( xPendingReadyList ), &( pxTCB->xEventListItem ) );
+				}
+
+				if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )
+				{
+					/* The notified task has a priority above the currently
+					executing task so a yield is required. */
+					if( pxHigherPriorityTaskWoken != NULL )
+					{
+						*pxHigherPriorityTaskWoken = pdTRUE;
+					}
+
+					/* Mark that a yield is pending in case the user is not
+					using the "xHigherPriorityTaskWoken" parameter to an ISR
+					safe FreeRTOS function. */
+					xYieldPending = pdTRUE;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+		}
+		portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+		return xReturn;
+	}
+
+#endif /* configUSE_TASK_NOTIFICATIONS */
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TASK_NOTIFICATIONS == 1 )
+
+	void vTaskNotifyGiveFromISR( TaskHandle_t xTaskToNotify, BaseType_t *pxHigherPriorityTaskWoken )
+	{
+	TCB_t * pxTCB;
+	uint8_t ucOriginalNotifyState;
+	UBaseType_t uxSavedInterruptStatus;
+
+		configASSERT( xTaskToNotify );
+
+		/* RTOS ports that support interrupt nesting have the concept of a
+		maximum	system call (or maximum API call) interrupt priority.
+		Interrupts that are	above the maximum system call priority are keep
+		permanently enabled, even when the RTOS kernel is in a critical section,
+		but cannot make any calls to FreeRTOS API functions.  If configASSERT()
+		is defined in FreeRTOSConfig.h then
+		portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
+		failure if a FreeRTOS API function is called from an interrupt that has
+		been assigned a priority above the configured maximum system call
+		priority.  Only FreeRTOS functions that end in FromISR can be called
+		from interrupts	that have been assigned a priority at or (logically)
+		below the maximum system call interrupt priority.  FreeRTOS maintains a
+		separate interrupt safe API to ensure interrupt entry is as fast and as
+		simple as possible.  More information (albeit Cortex-M specific) is
+		provided on the following link:
+		http://www.freertos.org/RTOS-Cortex-M3-M4.html */
+		portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+
+		pxTCB = xTaskToNotify;
+
+		uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+		{
+			ucOriginalNotifyState = pxTCB->ucNotifyState;
+			pxTCB->ucNotifyState = taskNOTIFICATION_RECEIVED;
+
+			/* 'Giving' is equivalent to incrementing a count in a counting
+			semaphore. */
+			( pxTCB->ulNotifiedValue )++;
+
+			traceTASK_NOTIFY_GIVE_FROM_ISR();
+
+			/* If the task is in the blocked state specifically to wait for a
+			notification then unblock it now. */
+			if( ucOriginalNotifyState == taskWAITING_NOTIFICATION )
+			{
+				/* The task should not have been on an event list. */
+				configASSERT( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL );
+
+				if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
+				{
+					( void ) uxListRemove( &( pxTCB->xStateListItem ) );
+					prvAddTaskToReadyList( pxTCB );
+				}
+				else
+				{
+					/* The delayed and ready lists cannot be accessed, so hold
+					this task pending until the scheduler is resumed. */
+					vListInsertEnd( &( xPendingReadyList ), &( pxTCB->xEventListItem ) );
+				}
+
+				if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )
+				{
+					/* The notified task has a priority above the currently
+					executing task so a yield is required. */
+					if( pxHigherPriorityTaskWoken != NULL )
+					{
+						*pxHigherPriorityTaskWoken = pdTRUE;
+					}
+
+					/* Mark that a yield is pending in case the user is not
+					using the "xHigherPriorityTaskWoken" parameter in an ISR
+					safe FreeRTOS function. */
+					xYieldPending = pdTRUE;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+		}
+		portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+	}
+
+#endif /* configUSE_TASK_NOTIFICATIONS */
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TASK_NOTIFICATIONS == 1 )
+
+	BaseType_t xTaskNotifyStateClear( TaskHandle_t xTask )
+	{
+	TCB_t *pxTCB;
+	BaseType_t xReturn;
+
+		/* If null is passed in here then it is the calling task that is having
+		its notification state cleared. */
+		pxTCB = prvGetTCBFromHandle( xTask );
+
+		taskENTER_CRITICAL();
+		{
+			if( pxTCB->ucNotifyState == taskNOTIFICATION_RECEIVED )
+			{
+				pxTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION;
+				xReturn = pdPASS;
+			}
+			else
+			{
+				xReturn = pdFAIL;
+			}
+		}
+		taskEXIT_CRITICAL();
+
+		return xReturn;
+	}
+
+#endif /* configUSE_TASK_NOTIFICATIONS */
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TASK_NOTIFICATIONS == 1 )
+
+	uint32_t ulTaskNotifyValueClear( TaskHandle_t xTask, uint32_t ulBitsToClear )
+	{
+	TCB_t *pxTCB;
+	uint32_t ulReturn;
+
+		/* If null is passed in here then it is the calling task that is having
+		its notification state cleared. */
+		pxTCB = prvGetTCBFromHandle( xTask );
+
+		taskENTER_CRITICAL();
+		{
+			/* Return the notification as it was before the bits were cleared,
+			then clear the bit mask. */
+			ulReturn = pxCurrentTCB->ulNotifiedValue;
+			pxTCB->ulNotifiedValue &= ~ulBitsToClear;
+		}
+		taskEXIT_CRITICAL();
+
+		return ulReturn;
+	}
+
+#endif /* configUSE_TASK_NOTIFICATIONS */
+/*-----------------------------------------------------------*/
+
+#if( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) )
+
+	uint32_t ulTaskGetIdleRunTimeCounter( void )
+	{
+		return xIdleTaskHandle->ulRunTimeCounter;
+	}
+
+#endif
+/*-----------------------------------------------------------*/
+
+static void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait, const BaseType_t xCanBlockIndefinitely )
+{
+TickType_t xTimeToWake;
+const TickType_t xConstTickCount = xTickCount;
+
+	#if( INCLUDE_xTaskAbortDelay == 1 )
+	{
+		/* About to enter a delayed list, so ensure the ucDelayAborted flag is
+		reset to pdFALSE so it can be detected as having been set to pdTRUE
+		when the task leaves the Blocked state. */
+		pxCurrentTCB->ucDelayAborted = pdFALSE;
+	}
+	#endif
+
+	/* Remove the task from the ready list before adding it to the blocked list
+	as the same list item is used for both lists. */
+	if( uxListRemove( &( pxCurrentTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
+	{
+		/* The current task must be in a ready list, so there is no need to
+		check, and the port reset macro can be called directly. */
+		portRESET_READY_PRIORITY( pxCurrentTCB->uxPriority, uxTopReadyPriority ); /*lint !e931 pxCurrentTCB cannot change as it is the calling task.  pxCurrentTCB->uxPriority and uxTopReadyPriority cannot change as called with scheduler suspended or in a critical section. */
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	#if ( INCLUDE_vTaskSuspend == 1 )
+	{
+		if( ( xTicksToWait == portMAX_DELAY ) && ( xCanBlockIndefinitely != pdFALSE ) )
+		{
+			/* Add the task to the suspended task list instead of a delayed task
+			list to ensure it is not woken by a timing event.  It will block
+			indefinitely. */
+			vListInsertEnd( &xSuspendedTaskList, &( pxCurrentTCB->xStateListItem ) );
+		}
+		else
+		{
+			/* Calculate the time at which the task should be woken if the event
+			does not occur.  This may overflow but this doesn't matter, the
+			kernel will manage it correctly. */
+			xTimeToWake = xConstTickCount + xTicksToWait;
+
+			/* The list item will be inserted in wake time order. */
+			listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xStateListItem ), xTimeToWake );
+
+			if( xTimeToWake < xConstTickCount )
+			{
+				/* Wake time has overflowed.  Place this item in the overflow
+				list. */
+				vListInsert( pxOverflowDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
+			}
+			else
+			{
+				/* The wake time has not overflowed, so the current block list
+				is used. */
+				vListInsert( pxDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
+
+				/* If the task entering the blocked state was placed at the
+				head of the list of blocked tasks then xNextTaskUnblockTime
+				needs to be updated too. */
+				if( xTimeToWake < xNextTaskUnblockTime )
+				{
+					xNextTaskUnblockTime = xTimeToWake;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+		}
+	}
+	#else /* INCLUDE_vTaskSuspend */
+	{
+		/* Calculate the time at which the task should be woken if the event
+		does not occur.  This may overflow but this doesn't matter, the kernel
+		will manage it correctly. */
+		xTimeToWake = xConstTickCount + xTicksToWait;
+
+		/* The list item will be inserted in wake time order. */
+		listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xStateListItem ), xTimeToWake );
+
+		if( xTimeToWake < xConstTickCount )
+		{
+			/* Wake time has overflowed.  Place this item in the overflow list. */
+			vListInsert( pxOverflowDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
+		}
+		else
+		{
+			/* The wake time has not overflowed, so the current block list is used. */
+			vListInsert( pxDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
+
+			/* If the task entering the blocked state was placed at the head of the
+			list of blocked tasks then xNextTaskUnblockTime needs to be updated
+			too. */
+			if( xTimeToWake < xNextTaskUnblockTime )
+			{
+				xNextTaskUnblockTime = xTimeToWake;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+
+		/* Avoid compiler warning when INCLUDE_vTaskSuspend is not 1. */
+		( void ) xCanBlockIndefinitely;
+	}
+	#endif /* INCLUDE_vTaskSuspend */
+}
+
+/* Code below here allows additional code to be inserted into this source file,
+especially where access to file scope functions and data is needed (for example
+when performing module tests). */
+
+#ifdef FREERTOS_MODULE_TEST
+	#include "tasks_test_access_functions.h"
+#endif
+
+
+#if( configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H == 1 )
+
+	#include "freertos_tasks_c_additions.h"
+
+	#ifdef FREERTOS_TASKS_C_ADDITIONS_INIT
+		static void freertos_tasks_c_additions_init( void )
+		{
+			FREERTOS_TASKS_C_ADDITIONS_INIT();
+		}
+	#endif
+
+#endif
+
+
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/timers.c b/Middlewares/Third_Party/FreeRTOS/Source/timers.c
new file mode 100644
index 0000000..00200b8
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/timers.c
@@ -0,0 +1,1127 @@
+/*
+ * FreeRTOS Kernel V10.3.1
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Standard includes. */
+#include <stdlib.h>
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+all the API functions to use the MPU wrappers.  That should only be done when
+task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+#include "FreeRTOS.h"
+#include "task.h"
+#include "queue.h"
+#include "timers.h"
+
+#if ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 0 )
+	#error configUSE_TIMERS must be set to 1 to make the xTimerPendFunctionCall() function available.
+#endif
+
+/* Lint e9021, e961 and e750 are suppressed as a MISRA exception justified
+because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined
+for the header files above, but not in this file, in order to generate the
+correct privileged Vs unprivileged linkage and placement. */
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e9021 !e961 !e750. */
+
+
+/* This entire source file will be skipped if the application is not configured
+to include software timer functionality.  This #if is closed at the very bottom
+of this file.  If you want to include software timer functionality then ensure
+configUSE_TIMERS is set to 1 in FreeRTOSConfig.h. */
+#if ( configUSE_TIMERS == 1 )
+
+/* Misc definitions. */
+#define tmrNO_DELAY		( TickType_t ) 0U
+
+/* The name assigned to the timer service task.  This can be overridden by
+defining trmTIMER_SERVICE_TASK_NAME in FreeRTOSConfig.h. */
+#ifndef configTIMER_SERVICE_TASK_NAME
+	#define configTIMER_SERVICE_TASK_NAME "Tmr Svc"
+#endif
+
+/* Bit definitions used in the ucStatus member of a timer structure. */
+#define tmrSTATUS_IS_ACTIVE					( ( uint8_t ) 0x01 )
+#define tmrSTATUS_IS_STATICALLY_ALLOCATED	( ( uint8_t ) 0x02 )
+#define tmrSTATUS_IS_AUTORELOAD				( ( uint8_t ) 0x04 )
+
+/* The definition of the timers themselves. */
+typedef struct tmrTimerControl /* The old naming convention is used to prevent breaking kernel aware debuggers. */
+{
+	const char				*pcTimerName;		/*<< Text name.  This is not used by the kernel, it is included simply to make debugging easier. */ /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+	ListItem_t				xTimerListItem;		/*<< Standard linked list item as used by all kernel features for event management. */
+	TickType_t				xTimerPeriodInTicks;/*<< How quickly and often the timer expires. */
+	void 					*pvTimerID;			/*<< An ID to identify the timer.  This allows the timer to be identified when the same callback is used for multiple timers. */
+	TimerCallbackFunction_t	pxCallbackFunction;	/*<< The function that will be called when the timer expires. */
+	#if( configUSE_TRACE_FACILITY == 1 )
+		UBaseType_t			uxTimerNumber;		/*<< An ID assigned by trace tools such as FreeRTOS+Trace */
+	#endif
+	uint8_t 				ucStatus;			/*<< Holds bits to say if the timer was statically allocated or not, and if it is active or not. */
+} xTIMER;
+
+/* The old xTIMER name is maintained above then typedefed to the new Timer_t
+name below to enable the use of older kernel aware debuggers. */
+typedef xTIMER Timer_t;
+
+/* The definition of messages that can be sent and received on the timer queue.
+Two types of message can be queued - messages that manipulate a software timer,
+and messages that request the execution of a non-timer related callback.  The
+two message types are defined in two separate structures, xTimerParametersType
+and xCallbackParametersType respectively. */
+typedef struct tmrTimerParameters
+{
+	TickType_t			xMessageValue;		/*<< An optional value used by a subset of commands, for example, when changing the period of a timer. */
+	Timer_t *			pxTimer;			/*<< The timer to which the command will be applied. */
+} TimerParameter_t;
+
+
+typedef struct tmrCallbackParameters
+{
+	PendedFunction_t	pxCallbackFunction;	/* << The callback function to execute. */
+	void *pvParameter1;						/* << The value that will be used as the callback functions first parameter. */
+	uint32_t ulParameter2;					/* << The value that will be used as the callback functions second parameter. */
+} CallbackParameters_t;
+
+/* The structure that contains the two message types, along with an identifier
+that is used to determine which message type is valid. */
+typedef struct tmrTimerQueueMessage
+{
+	BaseType_t			xMessageID;			/*<< The command being sent to the timer service task. */
+	union
+	{
+		TimerParameter_t xTimerParameters;
+
+		/* Don't include xCallbackParameters if it is not going to be used as
+		it makes the structure (and therefore the timer queue) larger. */
+		#if ( INCLUDE_xTimerPendFunctionCall == 1 )
+			CallbackParameters_t xCallbackParameters;
+		#endif /* INCLUDE_xTimerPendFunctionCall */
+	} u;
+} DaemonTaskMessage_t;
+
+/*lint -save -e956 A manual analysis and inspection has been used to determine
+which static variables must be declared volatile. */
+
+/* The list in which active timers are stored.  Timers are referenced in expire
+time order, with the nearest expiry time at the front of the list.  Only the
+timer service task is allowed to access these lists.
+xActiveTimerList1 and xActiveTimerList2 could be at function scope but that
+breaks some kernel aware debuggers, and debuggers that reply on removing the
+static qualifier. */
+PRIVILEGED_DATA static List_t xActiveTimerList1;
+PRIVILEGED_DATA static List_t xActiveTimerList2;
+PRIVILEGED_DATA static List_t *pxCurrentTimerList;
+PRIVILEGED_DATA static List_t *pxOverflowTimerList;
+
+/* A queue that is used to send commands to the timer service task. */
+PRIVILEGED_DATA static QueueHandle_t xTimerQueue = NULL;
+PRIVILEGED_DATA static TaskHandle_t xTimerTaskHandle = NULL;
+
+/*lint -restore */
+
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+
+	/* If static allocation is supported then the application must provide the
+	following callback function - which enables the application to optionally
+	provide the memory that will be used by the timer task as the task's stack
+	and TCB. */
+	extern void vApplicationGetTimerTaskMemory( StaticTask_t **ppxTimerTaskTCBBuffer, StackType_t **ppxTimerTaskStackBuffer, uint32_t *pulTimerTaskStackSize );
+
+#endif
+
+/*
+ * Initialise the infrastructure used by the timer service task if it has not
+ * been initialised already.
+ */
+static void prvCheckForValidListAndQueue( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * The timer service task (daemon).  Timer functionality is controlled by this
+ * task.  Other tasks communicate with the timer service task using the
+ * xTimerQueue queue.
+ */
+static portTASK_FUNCTION_PROTO( prvTimerTask, pvParameters ) PRIVILEGED_FUNCTION;
+
+/*
+ * Called by the timer service task to interpret and process a command it
+ * received on the timer queue.
+ */
+static void prvProcessReceivedCommands( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Insert the timer into either xActiveTimerList1, or xActiveTimerList2,
+ * depending on if the expire time causes a timer counter overflow.
+ */
+static BaseType_t prvInsertTimerInActiveList( Timer_t * const pxTimer, const TickType_t xNextExpiryTime, const TickType_t xTimeNow, const TickType_t xCommandTime ) PRIVILEGED_FUNCTION;
+
+/*
+ * An active timer has reached its expire time.  Reload the timer if it is an
+ * auto-reload timer, then call its callback.
+ */
+static void prvProcessExpiredTimer( const TickType_t xNextExpireTime, const TickType_t xTimeNow ) PRIVILEGED_FUNCTION;
+
+/*
+ * The tick count has overflowed.  Switch the timer lists after ensuring the
+ * current timer list does not still reference some timers.
+ */
+static void prvSwitchTimerLists( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Obtain the current tick count, setting *pxTimerListsWereSwitched to pdTRUE
+ * if a tick count overflow occurred since prvSampleTimeNow() was last called.
+ */
+static TickType_t prvSampleTimeNow( BaseType_t * const pxTimerListsWereSwitched ) PRIVILEGED_FUNCTION;
+
+/*
+ * If the timer list contains any active timers then return the expire time of
+ * the timer that will expire first and set *pxListWasEmpty to false.  If the
+ * timer list does not contain any timers then return 0 and set *pxListWasEmpty
+ * to pdTRUE.
+ */
+static TickType_t prvGetNextExpireTime( BaseType_t * const pxListWasEmpty ) PRIVILEGED_FUNCTION;
+
+/*
+ * If a timer has expired, process it.  Otherwise, block the timer service task
+ * until either a timer does expire or a command is received.
+ */
+static void prvProcessTimerOrBlockTask( const TickType_t xNextExpireTime, BaseType_t xListWasEmpty ) PRIVILEGED_FUNCTION;
+
+/*
+ * Called after a Timer_t structure has been allocated either statically or
+ * dynamically to fill in the structure's members.
+ */
+static void prvInitialiseNewTimer(	const char * const pcTimerName,			/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+									const TickType_t xTimerPeriodInTicks,
+									const UBaseType_t uxAutoReload,
+									void * const pvTimerID,
+									TimerCallbackFunction_t pxCallbackFunction,
+									Timer_t *pxNewTimer ) PRIVILEGED_FUNCTION;
+/*-----------------------------------------------------------*/
+
+BaseType_t xTimerCreateTimerTask( void )
+{
+BaseType_t xReturn = pdFAIL;
+
+	/* This function is called when the scheduler is started if
+	configUSE_TIMERS is set to 1.  Check that the infrastructure used by the
+	timer service task has been created/initialised.  If timers have already
+	been created then the initialisation will already have been performed. */
+	prvCheckForValidListAndQueue();
+
+	if( xTimerQueue != NULL )
+	{
+		#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+		{
+			StaticTask_t *pxTimerTaskTCBBuffer = NULL;
+			StackType_t *pxTimerTaskStackBuffer = NULL;
+			uint32_t ulTimerTaskStackSize;
+
+			vApplicationGetTimerTaskMemory( &pxTimerTaskTCBBuffer, &pxTimerTaskStackBuffer, &ulTimerTaskStackSize );
+			xTimerTaskHandle = xTaskCreateStatic(	prvTimerTask,
+													configTIMER_SERVICE_TASK_NAME,
+													ulTimerTaskStackSize,
+													NULL,
+													( ( UBaseType_t ) configTIMER_TASK_PRIORITY ) | portPRIVILEGE_BIT,
+													pxTimerTaskStackBuffer,
+													pxTimerTaskTCBBuffer );
+
+			if( xTimerTaskHandle != NULL )
+			{
+				xReturn = pdPASS;
+			}
+		}
+		#else
+		{
+			xReturn = xTaskCreate(	prvTimerTask,
+									configTIMER_SERVICE_TASK_NAME,
+									configTIMER_TASK_STACK_DEPTH,
+									NULL,
+									( ( UBaseType_t ) configTIMER_TASK_PRIORITY ) | portPRIVILEGE_BIT,
+									&xTimerTaskHandle );
+		}
+		#endif /* configSUPPORT_STATIC_ALLOCATION */
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	configASSERT( xReturn );
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+
+	TimerHandle_t xTimerCreate(	const char * const pcTimerName,			/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+								const TickType_t xTimerPeriodInTicks,
+								const UBaseType_t uxAutoReload,
+								void * const pvTimerID,
+								TimerCallbackFunction_t pxCallbackFunction )
+	{
+	Timer_t *pxNewTimer;
+
+		pxNewTimer = ( Timer_t * ) pvPortMalloc( sizeof( Timer_t ) ); /*lint !e9087 !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack, and the first member of Timer_t is always a pointer to the timer's mame. */
+
+		if( pxNewTimer != NULL )
+		{
+			/* Status is thus far zero as the timer is not created statically
+			and has not been started.  The auto-reload bit may get set in
+			prvInitialiseNewTimer. */
+			pxNewTimer->ucStatus = 0x00;
+			prvInitialiseNewTimer( pcTimerName, xTimerPeriodInTicks, uxAutoReload, pvTimerID, pxCallbackFunction, pxNewTimer );
+		}
+
+		return pxNewTimer;
+	}
+
+#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+
+	TimerHandle_t xTimerCreateStatic(	const char * const pcTimerName,		/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+										const TickType_t xTimerPeriodInTicks,
+										const UBaseType_t uxAutoReload,
+										void * const pvTimerID,
+										TimerCallbackFunction_t pxCallbackFunction,
+										StaticTimer_t *pxTimerBuffer )
+	{
+	Timer_t *pxNewTimer;
+
+		#if( configASSERT_DEFINED == 1 )
+		{
+			/* Sanity check that the size of the structure used to declare a
+			variable of type StaticTimer_t equals the size of the real timer
+			structure. */
+			volatile size_t xSize = sizeof( StaticTimer_t );
+			configASSERT( xSize == sizeof( Timer_t ) );
+			( void ) xSize; /* Keeps lint quiet when configASSERT() is not defined. */
+		}
+		#endif /* configASSERT_DEFINED */
+
+		/* A pointer to a StaticTimer_t structure MUST be provided, use it. */
+		configASSERT( pxTimerBuffer );
+		pxNewTimer = ( Timer_t * ) pxTimerBuffer; /*lint !e740 !e9087 StaticTimer_t is a pointer to a Timer_t, so guaranteed to be aligned and sized correctly (checked by an assert()), so this is safe. */
+
+		if( pxNewTimer != NULL )
+		{
+			/* Timers can be created statically or dynamically so note this
+			timer was created statically in case it is later deleted.  The
+			auto-reload bit may get set in prvInitialiseNewTimer(). */
+			pxNewTimer->ucStatus = tmrSTATUS_IS_STATICALLY_ALLOCATED;
+
+			prvInitialiseNewTimer( pcTimerName, xTimerPeriodInTicks, uxAutoReload, pvTimerID, pxCallbackFunction, pxNewTimer );
+		}
+
+		return pxNewTimer;
+	}
+
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+static void prvInitialiseNewTimer(	const char * const pcTimerName,			/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+									const TickType_t xTimerPeriodInTicks,
+									const UBaseType_t uxAutoReload,
+									void * const pvTimerID,
+									TimerCallbackFunction_t pxCallbackFunction,
+									Timer_t *pxNewTimer )
+{
+	/* 0 is not a valid value for xTimerPeriodInTicks. */
+	configASSERT( ( xTimerPeriodInTicks > 0 ) );
+
+	if( pxNewTimer != NULL )
+	{
+		/* Ensure the infrastructure used by the timer service task has been
+		created/initialised. */
+		prvCheckForValidListAndQueue();
+
+		/* Initialise the timer structure members using the function
+		parameters. */
+		pxNewTimer->pcTimerName = pcTimerName;
+		pxNewTimer->xTimerPeriodInTicks = xTimerPeriodInTicks;
+		pxNewTimer->pvTimerID = pvTimerID;
+		pxNewTimer->pxCallbackFunction = pxCallbackFunction;
+		vListInitialiseItem( &( pxNewTimer->xTimerListItem ) );
+		if( uxAutoReload != pdFALSE )
+		{
+			pxNewTimer->ucStatus |= tmrSTATUS_IS_AUTORELOAD;
+		}
+		traceTIMER_CREATE( pxNewTimer );
+	}
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xTimerGenericCommand( TimerHandle_t xTimer, const BaseType_t xCommandID, const TickType_t xOptionalValue, BaseType_t * const pxHigherPriorityTaskWoken, const TickType_t xTicksToWait )
+{
+BaseType_t xReturn = pdFAIL;
+DaemonTaskMessage_t xMessage;
+
+	configASSERT( xTimer );
+
+	/* Send a message to the timer service task to perform a particular action
+	on a particular timer definition. */
+	if( xTimerQueue != NULL )
+	{
+		/* Send a command to the timer service task to start the xTimer timer. */
+		xMessage.xMessageID = xCommandID;
+		xMessage.u.xTimerParameters.xMessageValue = xOptionalValue;
+		xMessage.u.xTimerParameters.pxTimer = xTimer;
+
+		if( xCommandID < tmrFIRST_FROM_ISR_COMMAND )
+		{
+			if( xTaskGetSchedulerState() == taskSCHEDULER_RUNNING )
+			{
+				xReturn = xQueueSendToBack( xTimerQueue, &xMessage, xTicksToWait );
+			}
+			else
+			{
+				xReturn = xQueueSendToBack( xTimerQueue, &xMessage, tmrNO_DELAY );
+			}
+		}
+		else
+		{
+			xReturn = xQueueSendToBackFromISR( xTimerQueue, &xMessage, pxHigherPriorityTaskWoken );
+		}
+
+		traceTIMER_COMMAND_SEND( xTimer, xCommandID, xOptionalValue, xReturn );
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+TaskHandle_t xTimerGetTimerDaemonTaskHandle( void )
+{
+	/* If xTimerGetTimerDaemonTaskHandle() is called before the scheduler has been
+	started, then xTimerTaskHandle will be NULL. */
+	configASSERT( ( xTimerTaskHandle != NULL ) );
+	return xTimerTaskHandle;
+}
+/*-----------------------------------------------------------*/
+
+TickType_t xTimerGetPeriod( TimerHandle_t xTimer )
+{
+Timer_t *pxTimer = xTimer;
+
+	configASSERT( xTimer );
+	return pxTimer->xTimerPeriodInTicks;
+}
+/*-----------------------------------------------------------*/
+
+void vTimerSetReloadMode( TimerHandle_t xTimer, const UBaseType_t uxAutoReload )
+{
+Timer_t * pxTimer =  xTimer;
+
+	configASSERT( xTimer );
+	taskENTER_CRITICAL();
+	{
+		if( uxAutoReload != pdFALSE )
+		{
+			pxTimer->ucStatus |= tmrSTATUS_IS_AUTORELOAD;
+		}
+		else
+		{
+			pxTimer->ucStatus &= ~tmrSTATUS_IS_AUTORELOAD;
+		}
+	}
+	taskEXIT_CRITICAL();
+}
+/*-----------------------------------------------------------*/
+
+UBaseType_t uxTimerGetReloadMode( TimerHandle_t xTimer )
+{
+Timer_t * pxTimer =  xTimer;
+UBaseType_t uxReturn;
+
+	configASSERT( xTimer );
+	taskENTER_CRITICAL();
+	{
+		if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) == 0 )
+		{
+			/* Not an auto-reload timer. */
+			uxReturn = ( UBaseType_t ) pdFALSE;
+		}
+		else
+		{
+			/* Is an auto-reload timer. */
+			uxReturn = ( UBaseType_t ) pdTRUE;
+		}
+	}
+	taskEXIT_CRITICAL();
+
+	return uxReturn;
+}
+/*-----------------------------------------------------------*/
+
+TickType_t xTimerGetExpiryTime( TimerHandle_t xTimer )
+{
+Timer_t * pxTimer =  xTimer;
+TickType_t xReturn;
+
+	configASSERT( xTimer );
+	xReturn = listGET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ) );
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+const char * pcTimerGetName( TimerHandle_t xTimer ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+{
+Timer_t *pxTimer = xTimer;
+
+	configASSERT( xTimer );
+	return pxTimer->pcTimerName;
+}
+/*-----------------------------------------------------------*/
+
+static void prvProcessExpiredTimer( const TickType_t xNextExpireTime, const TickType_t xTimeNow )
+{
+BaseType_t xResult;
+Timer_t * const pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList ); /*lint !e9087 !e9079 void * is used as this macro is used with tasks and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+
+	/* Remove the timer from the list of active timers.  A check has already
+	been performed to ensure the list is not empty. */
+	( void ) uxListRemove( &( pxTimer->xTimerListItem ) );
+	traceTIMER_EXPIRED( pxTimer );
+
+	/* If the timer is an auto-reload timer then calculate the next
+	expiry time and re-insert the timer in the list of active timers. */
+	if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 )
+	{
+		/* The timer is inserted into a list using a time relative to anything
+		other than the current time.  It will therefore be inserted into the
+		correct list relative to the time this task thinks it is now. */
+		if( prvInsertTimerInActiveList( pxTimer, ( xNextExpireTime + pxTimer->xTimerPeriodInTicks ), xTimeNow, xNextExpireTime ) != pdFALSE )
+		{
+			/* The timer expired before it was added to the active timer
+			list.  Reload it now.  */
+			xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xNextExpireTime, NULL, tmrNO_DELAY );
+			configASSERT( xResult );
+			( void ) xResult;
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	else
+	{
+		pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE;
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	/* Call the timer callback. */
+	pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer );
+}
+/*-----------------------------------------------------------*/
+
+static portTASK_FUNCTION( prvTimerTask, pvParameters )
+{
+TickType_t xNextExpireTime;
+BaseType_t xListWasEmpty;
+
+	/* Just to avoid compiler warnings. */
+	( void ) pvParameters;
+
+	#if( configUSE_DAEMON_TASK_STARTUP_HOOK == 1 )
+	{
+		extern void vApplicationDaemonTaskStartupHook( void );
+
+		/* Allow the application writer to execute some code in the context of
+		this task at the point the task starts executing.  This is useful if the
+		application includes initialisation code that would benefit from
+		executing after the scheduler has been started. */
+		vApplicationDaemonTaskStartupHook();
+	}
+	#endif /* configUSE_DAEMON_TASK_STARTUP_HOOK */
+
+	for( ;; )
+	{
+		/* Query the timers list to see if it contains any timers, and if so,
+		obtain the time at which the next timer will expire. */
+		xNextExpireTime = prvGetNextExpireTime( &xListWasEmpty );
+
+		/* If a timer has expired, process it.  Otherwise, block this task
+		until either a timer does expire, or a command is received. */
+		prvProcessTimerOrBlockTask( xNextExpireTime, xListWasEmpty );
+
+		/* Empty the command queue. */
+		prvProcessReceivedCommands();
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvProcessTimerOrBlockTask( const TickType_t xNextExpireTime, BaseType_t xListWasEmpty )
+{
+TickType_t xTimeNow;
+BaseType_t xTimerListsWereSwitched;
+
+	vTaskSuspendAll();
+	{
+		/* Obtain the time now to make an assessment as to whether the timer
+		has expired or not.  If obtaining the time causes the lists to switch
+		then don't process this timer as any timers that remained in the list
+		when the lists were switched will have been processed within the
+		prvSampleTimeNow() function. */
+		xTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched );
+		if( xTimerListsWereSwitched == pdFALSE )
+		{
+			/* The tick count has not overflowed, has the timer expired? */
+			if( ( xListWasEmpty == pdFALSE ) && ( xNextExpireTime <= xTimeNow ) )
+			{
+				( void ) xTaskResumeAll();
+				prvProcessExpiredTimer( xNextExpireTime, xTimeNow );
+			}
+			else
+			{
+				/* The tick count has not overflowed, and the next expire
+				time has not been reached yet.  This task should therefore
+				block to wait for the next expire time or a command to be
+				received - whichever comes first.  The following line cannot
+				be reached unless xNextExpireTime > xTimeNow, except in the
+				case when the current timer list is empty. */
+				if( xListWasEmpty != pdFALSE )
+				{
+					/* The current timer list is empty - is the overflow list
+					also empty? */
+					xListWasEmpty = listLIST_IS_EMPTY( pxOverflowTimerList );
+				}
+
+				vQueueWaitForMessageRestricted( xTimerQueue, ( xNextExpireTime - xTimeNow ), xListWasEmpty );
+
+				if( xTaskResumeAll() == pdFALSE )
+				{
+					/* Yield to wait for either a command to arrive, or the
+					block time to expire.  If a command arrived between the
+					critical section being exited and this yield then the yield
+					will not cause the task to block. */
+					portYIELD_WITHIN_API();
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+		}
+		else
+		{
+			( void ) xTaskResumeAll();
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+static TickType_t prvGetNextExpireTime( BaseType_t * const pxListWasEmpty )
+{
+TickType_t xNextExpireTime;
+
+	/* Timers are listed in expiry time order, with the head of the list
+	referencing the task that will expire first.  Obtain the time at which
+	the timer with the nearest expiry time will expire.  If there are no
+	active timers then just set the next expire time to 0.  That will cause
+	this task to unblock when the tick count overflows, at which point the
+	timer lists will be switched and the next expiry time can be
+	re-assessed.  */
+	*pxListWasEmpty = listLIST_IS_EMPTY( pxCurrentTimerList );
+	if( *pxListWasEmpty == pdFALSE )
+	{
+		xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList );
+	}
+	else
+	{
+		/* Ensure the task unblocks when the tick count rolls over. */
+		xNextExpireTime = ( TickType_t ) 0U;
+	}
+
+	return xNextExpireTime;
+}
+/*-----------------------------------------------------------*/
+
+static TickType_t prvSampleTimeNow( BaseType_t * const pxTimerListsWereSwitched )
+{
+TickType_t xTimeNow;
+PRIVILEGED_DATA static TickType_t xLastTime = ( TickType_t ) 0U; /*lint !e956 Variable is only accessible to one task. */
+
+	xTimeNow = xTaskGetTickCount();
+
+	if( xTimeNow < xLastTime )
+	{
+		prvSwitchTimerLists();
+		*pxTimerListsWereSwitched = pdTRUE;
+	}
+	else
+	{
+		*pxTimerListsWereSwitched = pdFALSE;
+	}
+
+	xLastTime = xTimeNow;
+
+	return xTimeNow;
+}
+/*-----------------------------------------------------------*/
+
+static BaseType_t prvInsertTimerInActiveList( Timer_t * const pxTimer, const TickType_t xNextExpiryTime, const TickType_t xTimeNow, const TickType_t xCommandTime )
+{
+BaseType_t xProcessTimerNow = pdFALSE;
+
+	listSET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ), xNextExpiryTime );
+	listSET_LIST_ITEM_OWNER( &( pxTimer->xTimerListItem ), pxTimer );
+
+	if( xNextExpiryTime <= xTimeNow )
+	{
+		/* Has the expiry time elapsed between the command to start/reset a
+		timer was issued, and the time the command was processed? */
+		if( ( ( TickType_t ) ( xTimeNow - xCommandTime ) ) >= pxTimer->xTimerPeriodInTicks ) /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+		{
+			/* The time between a command being issued and the command being
+			processed actually exceeds the timers period.  */
+			xProcessTimerNow = pdTRUE;
+		}
+		else
+		{
+			vListInsert( pxOverflowTimerList, &( pxTimer->xTimerListItem ) );
+		}
+	}
+	else
+	{
+		if( ( xTimeNow < xCommandTime ) && ( xNextExpiryTime >= xCommandTime ) )
+		{
+			/* If, since the command was issued, the tick count has overflowed
+			but the expiry time has not, then the timer must have already passed
+			its expiry time and should be processed immediately. */
+			xProcessTimerNow = pdTRUE;
+		}
+		else
+		{
+			vListInsert( pxCurrentTimerList, &( pxTimer->xTimerListItem ) );
+		}
+	}
+
+	return xProcessTimerNow;
+}
+/*-----------------------------------------------------------*/
+
+static void	prvProcessReceivedCommands( void )
+{
+DaemonTaskMessage_t xMessage;
+Timer_t *pxTimer;
+BaseType_t xTimerListsWereSwitched, xResult;
+TickType_t xTimeNow;
+
+	while( xQueueReceive( xTimerQueue, &xMessage, tmrNO_DELAY ) != pdFAIL ) /*lint !e603 xMessage does not have to be initialised as it is passed out, not in, and it is not used unless xQueueReceive() returns pdTRUE. */
+	{
+		#if ( INCLUDE_xTimerPendFunctionCall == 1 )
+		{
+			/* Negative commands are pended function calls rather than timer
+			commands. */
+			if( xMessage.xMessageID < ( BaseType_t ) 0 )
+			{
+				const CallbackParameters_t * const pxCallback = &( xMessage.u.xCallbackParameters );
+
+				/* The timer uses the xCallbackParameters member to request a
+				callback be executed.  Check the callback is not NULL. */
+				configASSERT( pxCallback );
+
+				/* Call the function. */
+				pxCallback->pxCallbackFunction( pxCallback->pvParameter1, pxCallback->ulParameter2 );
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		#endif /* INCLUDE_xTimerPendFunctionCall */
+
+		/* Commands that are positive are timer commands rather than pended
+		function calls. */
+		if( xMessage.xMessageID >= ( BaseType_t ) 0 )
+		{
+			/* The messages uses the xTimerParameters member to work on a
+			software timer. */
+			pxTimer = xMessage.u.xTimerParameters.pxTimer;
+
+			if( listIS_CONTAINED_WITHIN( NULL, &( pxTimer->xTimerListItem ) ) == pdFALSE ) /*lint !e961. The cast is only redundant when NULL is passed into the macro. */
+			{
+				/* The timer is in a list, remove it. */
+				( void ) uxListRemove( &( pxTimer->xTimerListItem ) );
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+
+			traceTIMER_COMMAND_RECEIVED( pxTimer, xMessage.xMessageID, xMessage.u.xTimerParameters.xMessageValue );
+
+			/* In this case the xTimerListsWereSwitched parameter is not used, but
+			it must be present in the function call.  prvSampleTimeNow() must be
+			called after the message is received from xTimerQueue so there is no
+			possibility of a higher priority task adding a message to the message
+			queue with a time that is ahead of the timer daemon task (because it
+			pre-empted the timer daemon task after the xTimeNow value was set). */
+			xTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched );
+
+			switch( xMessage.xMessageID )
+			{
+				case tmrCOMMAND_START :
+				case tmrCOMMAND_START_FROM_ISR :
+				case tmrCOMMAND_RESET :
+				case tmrCOMMAND_RESET_FROM_ISR :
+				case tmrCOMMAND_START_DONT_TRACE :
+					/* Start or restart a timer. */
+					pxTimer->ucStatus |= tmrSTATUS_IS_ACTIVE;
+					if( prvInsertTimerInActiveList( pxTimer,  xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, xTimeNow, xMessage.u.xTimerParameters.xMessageValue ) != pdFALSE )
+					{
+						/* The timer expired before it was added to the active
+						timer list.  Process it now. */
+						pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer );
+						traceTIMER_EXPIRED( pxTimer );
+
+						if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 )
+						{
+							xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, NULL, tmrNO_DELAY );
+							configASSERT( xResult );
+							( void ) xResult;
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+					break;
+
+				case tmrCOMMAND_STOP :
+				case tmrCOMMAND_STOP_FROM_ISR :
+					/* The timer has already been removed from the active list. */
+					pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE;
+					break;
+
+				case tmrCOMMAND_CHANGE_PERIOD :
+				case tmrCOMMAND_CHANGE_PERIOD_FROM_ISR :
+					pxTimer->ucStatus |= tmrSTATUS_IS_ACTIVE;
+					pxTimer->xTimerPeriodInTicks = xMessage.u.xTimerParameters.xMessageValue;
+					configASSERT( ( pxTimer->xTimerPeriodInTicks > 0 ) );
+
+					/* The new period does not really have a reference, and can
+					be longer or shorter than the old one.  The command time is
+					therefore set to the current time, and as the period cannot
+					be zero the next expiry time can only be in the future,
+					meaning (unlike for the xTimerStart() case above) there is
+					no fail case that needs to be handled here. */
+					( void ) prvInsertTimerInActiveList( pxTimer, ( xTimeNow + pxTimer->xTimerPeriodInTicks ), xTimeNow, xTimeNow );
+					break;
+
+				case tmrCOMMAND_DELETE :
+					#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+					{
+						/* The timer has already been removed from the active list,
+						just free up the memory if the memory was dynamically
+						allocated. */
+						if( ( pxTimer->ucStatus & tmrSTATUS_IS_STATICALLY_ALLOCATED ) == ( uint8_t ) 0 )
+						{
+							vPortFree( pxTimer );
+						}
+						else
+						{
+							pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE;
+						}
+					}
+					#else
+					{
+						/* If dynamic allocation is not enabled, the memory
+						could not have been dynamically allocated. So there is
+						no need to free the memory - just mark the timer as
+						"not active". */
+						pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE;
+					}
+					#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+					break;
+
+				default	:
+					/* Don't expect to get here. */
+					break;
+			}
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvSwitchTimerLists( void )
+{
+TickType_t xNextExpireTime, xReloadTime;
+List_t *pxTemp;
+Timer_t *pxTimer;
+BaseType_t xResult;
+
+	/* The tick count has overflowed.  The timer lists must be switched.
+	If there are any timers still referenced from the current timer list
+	then they must have expired and should be processed before the lists
+	are switched. */
+	while( listLIST_IS_EMPTY( pxCurrentTimerList ) == pdFALSE )
+	{
+		xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList );
+
+		/* Remove the timer from the list. */
+		pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList ); /*lint !e9087 !e9079 void * is used as this macro is used with tasks and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+		( void ) uxListRemove( &( pxTimer->xTimerListItem ) );
+		traceTIMER_EXPIRED( pxTimer );
+
+		/* Execute its callback, then send a command to restart the timer if
+		it is an auto-reload timer.  It cannot be restarted here as the lists
+		have not yet been switched. */
+		pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer );
+
+		if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 )
+		{
+			/* Calculate the reload value, and if the reload value results in
+			the timer going into the same timer list then it has already expired
+			and the timer should be re-inserted into the current list so it is
+			processed again within this loop.  Otherwise a command should be sent
+			to restart the timer to ensure it is only inserted into a list after
+			the lists have been swapped. */
+			xReloadTime = ( xNextExpireTime + pxTimer->xTimerPeriodInTicks );
+			if( xReloadTime > xNextExpireTime )
+			{
+				listSET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ), xReloadTime );
+				listSET_LIST_ITEM_OWNER( &( pxTimer->xTimerListItem ), pxTimer );
+				vListInsert( pxCurrentTimerList, &( pxTimer->xTimerListItem ) );
+			}
+			else
+			{
+				xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xNextExpireTime, NULL, tmrNO_DELAY );
+				configASSERT( xResult );
+				( void ) xResult;
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+
+	pxTemp = pxCurrentTimerList;
+	pxCurrentTimerList = pxOverflowTimerList;
+	pxOverflowTimerList = pxTemp;
+}
+/*-----------------------------------------------------------*/
+
+static void prvCheckForValidListAndQueue( void )
+{
+	/* Check that the list from which active timers are referenced, and the
+	queue used to communicate with the timer service, have been
+	initialised. */
+	taskENTER_CRITICAL();
+	{
+		if( xTimerQueue == NULL )
+		{
+			vListInitialise( &xActiveTimerList1 );
+			vListInitialise( &xActiveTimerList2 );
+			pxCurrentTimerList = &xActiveTimerList1;
+			pxOverflowTimerList = &xActiveTimerList2;
+
+			#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+			{
+				/* The timer queue is allocated statically in case
+				configSUPPORT_DYNAMIC_ALLOCATION is 0. */
+				static StaticQueue_t xStaticTimerQueue; /*lint !e956 Ok to declare in this manner to prevent additional conditional compilation guards in other locations. */
+				static uint8_t ucStaticTimerQueueStorage[ ( size_t ) configTIMER_QUEUE_LENGTH * sizeof( DaemonTaskMessage_t ) ]; /*lint !e956 Ok to declare in this manner to prevent additional conditional compilation guards in other locations. */
+
+				xTimerQueue = xQueueCreateStatic( ( UBaseType_t ) configTIMER_QUEUE_LENGTH, ( UBaseType_t ) sizeof( DaemonTaskMessage_t ), &( ucStaticTimerQueueStorage[ 0 ] ), &xStaticTimerQueue );
+			}
+			#else
+			{
+				xTimerQueue = xQueueCreate( ( UBaseType_t ) configTIMER_QUEUE_LENGTH, sizeof( DaemonTaskMessage_t ) );
+			}
+			#endif
+
+			#if ( configQUEUE_REGISTRY_SIZE > 0 )
+			{
+				if( xTimerQueue != NULL )
+				{
+					vQueueAddToRegistry( xTimerQueue, "TmrQ" );
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			#endif /* configQUEUE_REGISTRY_SIZE */
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	taskEXIT_CRITICAL();
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xTimerIsTimerActive( TimerHandle_t xTimer )
+{
+BaseType_t xReturn;
+Timer_t *pxTimer = xTimer;
+
+	configASSERT( xTimer );
+
+	/* Is the timer in the list of active timers? */
+	taskENTER_CRITICAL();
+	{
+		if( ( pxTimer->ucStatus & tmrSTATUS_IS_ACTIVE ) == 0 )
+		{
+			xReturn = pdFALSE;
+		}
+		else
+		{
+			xReturn = pdTRUE;
+		}
+	}
+	taskEXIT_CRITICAL();
+
+	return xReturn;
+} /*lint !e818 Can't be pointer to const due to the typedef. */
+/*-----------------------------------------------------------*/
+
+void *pvTimerGetTimerID( const TimerHandle_t xTimer )
+{
+Timer_t * const pxTimer = xTimer;
+void *pvReturn;
+
+	configASSERT( xTimer );
+
+	taskENTER_CRITICAL();
+	{
+		pvReturn = pxTimer->pvTimerID;
+	}
+	taskEXIT_CRITICAL();
+
+	return pvReturn;
+}
+/*-----------------------------------------------------------*/
+
+void vTimerSetTimerID( TimerHandle_t xTimer, void *pvNewID )
+{
+Timer_t * const pxTimer = xTimer;
+
+	configASSERT( xTimer );
+
+	taskENTER_CRITICAL();
+	{
+		pxTimer->pvTimerID = pvNewID;
+	}
+	taskEXIT_CRITICAL();
+}
+/*-----------------------------------------------------------*/
+
+#if( INCLUDE_xTimerPendFunctionCall == 1 )
+
+	BaseType_t xTimerPendFunctionCallFromISR( PendedFunction_t xFunctionToPend, void *pvParameter1, uint32_t ulParameter2, BaseType_t *pxHigherPriorityTaskWoken )
+	{
+	DaemonTaskMessage_t xMessage;
+	BaseType_t xReturn;
+
+		/* Complete the message with the function parameters and post it to the
+		daemon task. */
+		xMessage.xMessageID = tmrCOMMAND_EXECUTE_CALLBACK_FROM_ISR;
+		xMessage.u.xCallbackParameters.pxCallbackFunction = xFunctionToPend;
+		xMessage.u.xCallbackParameters.pvParameter1 = pvParameter1;
+		xMessage.u.xCallbackParameters.ulParameter2 = ulParameter2;
+
+		xReturn = xQueueSendFromISR( xTimerQueue, &xMessage, pxHigherPriorityTaskWoken );
+
+		tracePEND_FUNC_CALL_FROM_ISR( xFunctionToPend, pvParameter1, ulParameter2, xReturn );
+
+		return xReturn;
+	}
+
+#endif /* INCLUDE_xTimerPendFunctionCall */
+/*-----------------------------------------------------------*/
+
+#if( INCLUDE_xTimerPendFunctionCall == 1 )
+
+	BaseType_t xTimerPendFunctionCall( PendedFunction_t xFunctionToPend, void *pvParameter1, uint32_t ulParameter2, TickType_t xTicksToWait )
+	{
+	DaemonTaskMessage_t xMessage;
+	BaseType_t xReturn;
+
+		/* This function can only be called after a timer has been created or
+		after the scheduler has been started because, until then, the timer
+		queue does not exist. */
+		configASSERT( xTimerQueue );
+
+		/* Complete the message with the function parameters and post it to the
+		daemon task. */
+		xMessage.xMessageID = tmrCOMMAND_EXECUTE_CALLBACK;
+		xMessage.u.xCallbackParameters.pxCallbackFunction = xFunctionToPend;
+		xMessage.u.xCallbackParameters.pvParameter1 = pvParameter1;
+		xMessage.u.xCallbackParameters.ulParameter2 = ulParameter2;
+
+		xReturn = xQueueSendToBack( xTimerQueue, &xMessage, xTicksToWait );
+
+		tracePEND_FUNC_CALL( xFunctionToPend, pvParameter1, ulParameter2, xReturn );
+
+		return xReturn;
+	}
+
+#endif /* INCLUDE_xTimerPendFunctionCall */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	UBaseType_t uxTimerGetTimerNumber( TimerHandle_t xTimer )
+	{
+		return ( ( Timer_t * ) xTimer )->uxTimerNumber;
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	void vTimerSetTimerNumber( TimerHandle_t xTimer, UBaseType_t uxTimerNumber )
+	{
+		( ( Timer_t * ) xTimer )->uxTimerNumber = uxTimerNumber;
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+/* This entire source file will be skipped if the application is not configured
+to include software timer functionality.  If you want to include software timer
+functionality then ensure configUSE_TIMERS is set to 1 in FreeRTOSConfig.h. */
+#endif /* configUSE_TIMERS == 1 */
+
+
+
diff --git a/Middlewares/Third_Party/LwIP/src/core/tcp.c b/Middlewares/Third_Party/LwIP/src/core/tcp.c
index 1ad705e..bd7d64e 100644
--- a/Middlewares/Third_Party/LwIP/src/core/tcp.c
+++ b/Middlewares/Third_Party/LwIP/src/core/tcp.c
@@ -1711,14 +1711,14 @@ tcp_kill_prio(u8_t prio)
 
   mprio = LWIP_MIN(TCP_PRIO_MAX, prio);
 
-  /* We want to kill connections with a lower prio, so bail out if
+  /* We want to kill connections with a lower prio, so bail out if 
    * supplied prio is 0 - there can never be a lower prio
    */
   if (mprio == 0) {
     return;
   }
 
-  /* We only want kill connections with a lower prio, so decrement prio by one
+  /* We only want kill connections with a lower prio, so decrement prio by one 
    * and start searching for oldest connection with same or lower priority than mprio.
    * We want to find the connections with the lowest possible prio, and among
    * these the one with the longest inactivity time.
diff --git a/Middlewares/Third_Party/LwIP/system/OS/sys_arch.c b/Middlewares/Third_Party/LwIP/system/OS/sys_arch.c
new file mode 100644
index 0000000..65d9bf9
--- /dev/null
+++ b/Middlewares/Third_Party/LwIP/system/OS/sys_arch.c
@@ -0,0 +1,512 @@
+/*
+ * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+
+/* lwIP includes. */
+#include "lwip/debug.h"
+#include "lwip/def.h"
+#include "lwip/sys.h"
+#include "lwip/mem.h"
+#include "lwip/stats.h"
+
+#if !NO_SYS
+
+#include "cmsis_os.h"
+
+#if defined(LWIP_PROVIDE_ERRNO)
+int errno;
+#endif
+
+/*-----------------------------------------------------------------------------------*/
+//  Creates an empty mailbox.
+err_t sys_mbox_new(sys_mbox_t *mbox, int size)
+{
+#if (osCMSIS < 0x20000U)
+  osMessageQDef(QUEUE, size, void *);
+  *mbox = osMessageCreate(osMessageQ(QUEUE), NULL);
+#else
+  *mbox = osMessageQueueNew(size, sizeof(void *), NULL);
+#endif
+#if SYS_STATS
+  ++lwip_stats.sys.mbox.used;
+  if(lwip_stats.sys.mbox.max < lwip_stats.sys.mbox.used)
+  {
+    lwip_stats.sys.mbox.max = lwip_stats.sys.mbox.used;
+  }
+#endif /* SYS_STATS */
+  if(*mbox == NULL)
+    return ERR_MEM;
+
+  return ERR_OK;
+}
+
+/*-----------------------------------------------------------------------------------*/
+/*
+  Deallocates a mailbox. If there are messages still present in the
+  mailbox when the mailbox is deallocated, it is an indication of a
+  programming error in lwIP and the developer should be notified.
+*/
+void sys_mbox_free(sys_mbox_t *mbox)
+{
+#if (osCMSIS < 0x20000U)
+  if(osMessageWaiting(*mbox))
+#else
+  if(osMessageQueueGetCount(*mbox))
+#endif
+  {
+    /* Line for breakpoint.  Should never break here! */
+    portNOP();
+#if SYS_STATS
+    lwip_stats.sys.mbox.err++;
+#endif /* SYS_STATS */
+
+  }
+#if (osCMSIS < 0x20000U)
+  osMessageDelete(*mbox);
+#else
+  osMessageQueueDelete(*mbox);
+#endif
+#if SYS_STATS
+  --lwip_stats.sys.mbox.used;
+#endif /* SYS_STATS */
+}
+
+/*-----------------------------------------------------------------------------------*/
+//   Posts the "msg" to the mailbox.
+void sys_mbox_post(sys_mbox_t *mbox, void *data)
+{
+#if (osCMSIS < 0x20000U)
+  while(osMessagePut(*mbox, (uint32_t)data, osWaitForever) != osOK);
+#else
+  while(osMessageQueuePut(*mbox, &data, 0, osWaitForever) != osOK);
+#endif
+}
+
+
+/*-----------------------------------------------------------------------------------*/
+//   Try to post the "msg" to the mailbox.
+err_t sys_mbox_trypost(sys_mbox_t *mbox, void *msg)
+{
+  err_t result;
+#if (osCMSIS < 0x20000U)
+  if(osMessagePut(*mbox, (uint32_t)msg, 0) == osOK)
+#else
+  if(osMessageQueuePut(*mbox, &msg, 0, 0) == osOK)
+#endif
+  {
+    result = ERR_OK;
+  }
+  else
+  {
+    // could not post, queue must be full
+    result = ERR_MEM;
+
+#if SYS_STATS
+    lwip_stats.sys.mbox.err++;
+#endif /* SYS_STATS */
+  }
+
+  return result;
+}
+
+
+/*-----------------------------------------------------------------------------------*/
+//   Try to post the "msg" to the mailbox.
+err_t sys_mbox_trypost_fromisr(sys_mbox_t *mbox, void *msg)
+{
+  return sys_mbox_trypost(mbox, msg);
+}
+
+/*-----------------------------------------------------------------------------------*/
+/*
+  Blocks the thread until a message arrives in the mailbox, but does
+  not block the thread longer than "timeout" milliseconds (similar to
+  the sys_arch_sem_wait() function). The "msg" argument is a result
+  parameter that is set by the function (i.e., by doing "*msg =
+  ptr"). The "msg" parameter maybe NULL to indicate that the message
+  should be dropped.
+
+  The return values are the same as for the sys_arch_sem_wait() function:
+  Number of milliseconds spent waiting or SYS_ARCH_TIMEOUT if there was a
+  timeout.
+
+  Note that a function with a similar name, sys_mbox_fetch(), is
+  implemented by lwIP.
+*/
+u32_t sys_arch_mbox_fetch(sys_mbox_t *mbox, void **msg, u32_t timeout)
+{
+#if (osCMSIS < 0x20000U)
+  osEvent event;
+  uint32_t starttime = osKernelSysTick();
+#else
+  osStatus_t status;
+  uint32_t starttime = osKernelGetTickCount();
+#endif
+  if(timeout != 0)
+  {
+#if (osCMSIS < 0x20000U)
+    event = osMessageGet (*mbox, timeout);
+
+    if(event.status == osEventMessage)
+    {
+      *msg = (void *)event.value.v;
+      return (osKernelSysTick() - starttime);
+    }
+#else
+    status = osMessageQueueGet(*mbox, msg, 0, timeout);
+    if (status == osOK)
+    {
+      return (osKernelGetTickCount() - starttime);
+    }
+#endif
+    else
+    {
+      return SYS_ARCH_TIMEOUT;
+    }
+  }
+  else
+  {
+#if (osCMSIS < 0x20000U)
+    event = osMessageGet (*mbox, osWaitForever);
+    *msg = (void *)event.value.v;
+    return (osKernelSysTick() - starttime);
+#else
+    osMessageQueueGet(*mbox, msg, 0, osWaitForever );
+    return (osKernelGetTickCount() - starttime);
+#endif
+  }
+}
+
+/*-----------------------------------------------------------------------------------*/
+/*
+  Similar to sys_arch_mbox_fetch, but if message is not ready immediately, we'll
+  return with SYS_MBOX_EMPTY.  On success, 0 is returned.
+*/
+u32_t sys_arch_mbox_tryfetch(sys_mbox_t *mbox, void **msg)
+{
+#if (osCMSIS < 0x20000U)
+  osEvent event;
+
+  event = osMessageGet (*mbox, 0);
+
+  if(event.status == osEventMessage)
+  {
+    *msg = (void *)event.value.v;
+#else
+  if (osMessageQueueGet(*mbox, msg, 0, 0) == osOK)
+  {
+#endif
+    return ERR_OK;
+  }
+  else
+  {
+    return SYS_MBOX_EMPTY;
+  }
+}
+/*----------------------------------------------------------------------------------*/
+int sys_mbox_valid(sys_mbox_t *mbox)
+{
+  if (*mbox == SYS_MBOX_NULL)
+    return 0;
+  else
+    return 1;
+}
+/*-----------------------------------------------------------------------------------*/
+void sys_mbox_set_invalid(sys_mbox_t *mbox)
+{
+  *mbox = SYS_MBOX_NULL;
+}
+
+/*-----------------------------------------------------------------------------------*/
+//  Creates a new semaphore. The "count" argument specifies
+//  the initial state of the semaphore.
+err_t sys_sem_new(sys_sem_t *sem, u8_t count)
+{
+#if (osCMSIS < 0x20000U)
+  osSemaphoreDef(SEM);
+  *sem = osSemaphoreCreate (osSemaphore(SEM), 1);
+#else
+  *sem = osSemaphoreNew(UINT16_MAX, count, NULL);
+#endif
+
+  if(*sem == NULL)
+  {
+#if SYS_STATS
+    ++lwip_stats.sys.sem.err;
+#endif /* SYS_STATS */
+    return ERR_MEM;
+  }
+
+  if(count == 0)	// Means it can't be taken
+  {
+#if (osCMSIS < 0x20000U)
+    osSemaphoreWait(*sem, 0);
+#else
+    osSemaphoreAcquire(*sem, 0);
+#endif
+  }
+
+#if SYS_STATS
+  ++lwip_stats.sys.sem.used;
+  if (lwip_stats.sys.sem.max < lwip_stats.sys.sem.used) {
+    lwip_stats.sys.sem.max = lwip_stats.sys.sem.used;
+  }
+#endif /* SYS_STATS */
+
+  return ERR_OK;
+}
+
+/*-----------------------------------------------------------------------------------*/
+/*
+  Blocks the thread while waiting for the semaphore to be
+  signaled. If the "timeout" argument is non-zero, the thread should
+  only be blocked for the specified time (measured in
+  milliseconds).
+
+  If the timeout argument is non-zero, the return value is the number of
+  milliseconds spent waiting for the semaphore to be signaled. If the
+  semaphore wasn't signaled within the specified time, the return value is
+  SYS_ARCH_TIMEOUT. If the thread didn't have to wait for the semaphore
+  (i.e., it was already signaled), the function may return zero.
+
+  Notice that lwIP implements a function with a similar name,
+  sys_sem_wait(), that uses the sys_arch_sem_wait() function.
+*/
+u32_t sys_arch_sem_wait(sys_sem_t *sem, u32_t timeout)
+{
+#if (osCMSIS < 0x20000U)
+  uint32_t starttime = osKernelSysTick();
+#else
+  uint32_t starttime = osKernelGetTickCount();
+#endif
+  if(timeout != 0)
+  {
+#if (osCMSIS < 0x20000U)
+    if(osSemaphoreWait (*sem, timeout) == osOK)
+    {
+      return (osKernelSysTick() - starttime);
+#else
+    if(osSemaphoreAcquire(*sem, timeout) == osOK)
+    {
+        return (osKernelGetTickCount() - starttime);
+#endif
+    }
+    else
+    {
+      return SYS_ARCH_TIMEOUT;
+    }
+  }
+  else
+  {
+#if (osCMSIS < 0x20000U)
+    while(osSemaphoreWait (*sem, osWaitForever) != osOK);
+    return (osKernelSysTick() - starttime);
+#else
+    while(osSemaphoreAcquire(*sem, osWaitForever) != osOK);
+    return (osKernelGetTickCount() - starttime);
+#endif
+  }
+}
+
+/*-----------------------------------------------------------------------------------*/
+// Signals a semaphore
+void sys_sem_signal(sys_sem_t *sem)
+{
+  osSemaphoreRelease(*sem);
+}
+
+/*-----------------------------------------------------------------------------------*/
+// Deallocates a semaphore
+void sys_sem_free(sys_sem_t *sem)
+{
+#if SYS_STATS
+  --lwip_stats.sys.sem.used;
+#endif /* SYS_STATS */
+
+  osSemaphoreDelete(*sem);
+}
+/*-----------------------------------------------------------------------------------*/
+int sys_sem_valid(sys_sem_t *sem)
+{
+  if (*sem == SYS_SEM_NULL)
+    return 0;
+  else
+    return 1;
+}
+
+/*-----------------------------------------------------------------------------------*/
+void sys_sem_set_invalid(sys_sem_t *sem)
+{
+  *sem = SYS_SEM_NULL;
+}
+
+/*-----------------------------------------------------------------------------------*/
+#if (osCMSIS < 0x20000U)
+osMutexId lwip_sys_mutex;
+osMutexDef(lwip_sys_mutex);
+#else
+osMutexId_t lwip_sys_mutex;
+#endif
+// Initialize sys arch
+void sys_init(void)
+{
+#if (osCMSIS < 0x20000U)
+  lwip_sys_mutex = osMutexCreate(osMutex(lwip_sys_mutex));
+#else
+  lwip_sys_mutex = osMutexNew(NULL);
+#endif
+}
+/*-----------------------------------------------------------------------------------*/
+                                      /* Mutexes*/
+/*-----------------------------------------------------------------------------------*/
+/*-----------------------------------------------------------------------------------*/
+#if LWIP_COMPAT_MUTEX == 0
+/* Create a new mutex*/
+err_t sys_mutex_new(sys_mutex_t *mutex) {
+
+#if (osCMSIS < 0x20000U)
+  osMutexDef(MUTEX);
+  *mutex = osMutexCreate(osMutex(MUTEX));
+#else
+  *mutex = osMutexNew(NULL);
+#endif
+
+  if(*mutex == NULL)
+  {
+#if SYS_STATS
+    ++lwip_stats.sys.mutex.err;
+#endif /* SYS_STATS */
+    return ERR_MEM;
+  }
+
+#if SYS_STATS
+  ++lwip_stats.sys.mutex.used;
+  if (lwip_stats.sys.mutex.max < lwip_stats.sys.mutex.used) {
+    lwip_stats.sys.mutex.max = lwip_stats.sys.mutex.used;
+  }
+#endif /* SYS_STATS */
+  return ERR_OK;
+}
+/*-----------------------------------------------------------------------------------*/
+/* Deallocate a mutex*/
+void sys_mutex_free(sys_mutex_t *mutex)
+{
+#if SYS_STATS
+      --lwip_stats.sys.mutex.used;
+#endif /* SYS_STATS */
+
+  osMutexDelete(*mutex);
+}
+/*-----------------------------------------------------------------------------------*/
+/* Lock a mutex*/
+void sys_mutex_lock(sys_mutex_t *mutex)
+{
+#if (osCMSIS < 0x20000U)
+  osMutexWait(*mutex, osWaitForever);
+#else
+  osMutexAcquire(*mutex, osWaitForever);
+#endif
+}
+
+/*-----------------------------------------------------------------------------------*/
+/* Unlock a mutex*/
+void sys_mutex_unlock(sys_mutex_t *mutex)
+{
+  osMutexRelease(*mutex);
+}
+#endif /*LWIP_COMPAT_MUTEX*/
+/*-----------------------------------------------------------------------------------*/
+// TODO
+/*-----------------------------------------------------------------------------------*/
+/*
+  Starts a new thread with priority "prio" that will begin its execution in the
+  function "thread()". The "arg" argument will be passed as an argument to the
+  thread() function. The id of the new thread is returned. Both the id and
+  the priority are system dependent.
+*/
+sys_thread_t sys_thread_new(const char *name, lwip_thread_fn thread , void *arg, int stacksize, int prio)
+{
+#if (osCMSIS < 0x20000U)
+  const osThreadDef_t os_thread_def = { (char *)name, (os_pthread)thread, (osPriority)prio, 0, stacksize};
+  return osThreadCreate(&os_thread_def, arg);
+#else
+  const osThreadAttr_t attributes = {
+                        .name = name,
+                        .stack_size = stacksize,
+                        .priority = (osPriority_t)prio,
+                      };
+  return osThreadNew(thread, arg, &attributes);
+#endif
+}
+
+/*
+  This optional function does a "fast" critical region protection and returns
+  the previous protection level. This function is only called during very short
+  critical regions. An embedded system which supports ISR-based drivers might
+  want to implement this function by disabling interrupts. Task-based systems
+  might want to implement this by using a mutex or disabling tasking. This
+  function should support recursive calls from the same task or interrupt. In
+  other words, sys_arch_protect() could be called while already protected. In
+  that case the return value indicates that it is already protected.
+
+  sys_arch_protect() is only required if your port is supporting an operating
+  system.
+
+  Note: This function is based on FreeRTOS API, because no equivalent CMSIS-RTOS
+        API is available
+*/
+sys_prot_t sys_arch_protect(void)
+{
+#if (osCMSIS < 0x20000U)
+  osMutexWait(lwip_sys_mutex, osWaitForever);
+#else
+  osMutexAcquire(lwip_sys_mutex, osWaitForever);
+#endif
+  return (sys_prot_t)1;
+}
+
+
+/*
+  This optional function does a "fast" set of critical region protection to the
+  value specified by pval. See the documentation for sys_arch_protect() for
+  more information. This function is only required if your port is supporting
+  an operating system.
+
+  Note: This function is based on FreeRTOS API, because no equivalent CMSIS-RTOS
+        API is available
+*/
+void sys_arch_unprotect(sys_prot_t pval)
+{
+  ( void ) pval;
+  osMutexRelease(lwip_sys_mutex);
+}
+
+#endif /* !NO_SYS */
diff --git a/README.md b/README.md
deleted file mode 100644
index 11eeeda..0000000
--- a/README.md
+++ /dev/null
@@ -1,34 +0,0 @@
-# lwip_ftp_client
-
-## lwftp 모듈 설명
-### 유틸리티
-- PTRNLEN: 문자열 리터럴과 그 길이를 전달하는 매크로입니다.
-
-### 네트워크 연결 및 세션 관리
-- lwftp_connect: FTP 서버에 연결을 시작합니다.
-- lwftp_control_connected: 컨트롤 연결이 성공적으로 설정되었을 때 호출됩니다.
-- lwftp_close: FTP 세션을 종료합니다.
-
-### 데이터 전송 관리
-- lwftp_start_RETR: 서버에서 파일을 다운로드하기 위한 RETR 세션을 시작합니다.
-- lwftp_start_STOR: 서버에 파일을 업로드하기 위한 STOR 세션을 시작합니다.
-- lwftp_retrieve: 서버에서 파일을 다운로드하는 작업을 시작합니다.
-- lwftp_store: 서버에 파일을 업로드하는 작업을 시작합니다.
-
-### TCP 커넥션 핸들링
-- lwftp_pcb_close: TCP 프로토콜 컨트롤 블록(PCB)을 닫습니다.
-- lwftp_send_next_data: 데이터 연결을 통해 다음 데이터 블록을 전송합니다.
-- lwftp_data_recv: 데이터 연결로부터 데이터를 수신합니다.
-- lwftp_data_sent: 데이터 전송이 확인되었을 때 호출됩니다.
-- lwftp_data_err: 데이터 연결 중 오류가 발생했을 때 처리합니다.
-
-### FTP 프로토콜 커맨드 처리
-- lwftp_control_process: FTP 컨트롤 연결로부터의 응답을 처리합니다.
-- lwftp_send_msg: FTP 서버에 특정 메시지를 전송합니다.
-- lwftp_data_open: 데이터 연결을 위한 패시브 모드(PASV) 연결을 엽니다.
-
-### TCP 이벤트 핸들러
-- lwftp_control_recv: 컨트롤 연결로부터 데이터를 수신할 때 호출됩니다.
-- lwftp_control_sent: 컨트롤 연결을 통해 데이터를 성공적으로 전송했을 때 호출됩니다.
-- lwftp_control_err: 컨트롤 연결 중 오류가 발생했을 때 처리합니다.
-- lwftp_control_close: 컨트롤 연결을 종료합니다.
\ No newline at end of file
diff --git a/STM32H723VGHX_FLASH.ld b/STM32H723VGHX_FLASH.ld
index 362840c..73e2a3c 100644
--- a/STM32H723VGHX_FLASH.ld
+++ b/STM32H723VGHX_FLASH.ld
@@ -37,8 +37,8 @@ ENTRY(Reset_Handler)
 /* Highest address of the user mode stack */
 _estack = ORIGIN(RAM_D1) + LENGTH(RAM_D1);    /* end of RAM */
 /* Generate a link error if heap and stack don't fit into RAM */
-_Min_Heap_Size = 0x200;      /* required amount of heap  */
-_Min_Stack_Size = 0x400; /* required amount of stack */
+_Min_Heap_Size = 0x2000;      /* required amount of heap  */
+_Min_Stack_Size = 0x4000; /* required amount of stack */
 
 /* Specify the memory areas */
 MEMORY
@@ -161,8 +161,8 @@ SECTIONS
     . = . + _Min_Stack_Size;
     . = ALIGN(8);
   } >RAM_D1
-  
-  /* Modification start */
+
+	/* Modification start */
   .lwip_sec (NOLOAD) :
   {
     . = ABSOLUTE(0x30000000);
@@ -170,7 +170,7 @@ SECTIONS
     
     . = ABSOLUTE(0x30000100);
     *(.TxDecripSection)
-  } >RAM_D2
+	} >RAM_D2
   /* Modification end */
 
   /* Remove information from the standard libraries */
diff --git a/STM32H723VGHX_RAM.ld b/STM32H723VGHX_RAM.ld
index b00b194..dc79280 100644
--- a/STM32H723VGHX_RAM.ld
+++ b/STM32H723VGHX_RAM.ld
@@ -37,8 +37,8 @@ ENTRY(Reset_Handler)
 /* Highest address of the user mode stack */
 _estack = ORIGIN(DTCMRAM) + LENGTH(DTCMRAM);    /* end of RAM */
 /* Generate a link error if heap and stack don't fit into RAM */
-_Min_Heap_Size = 0x200;      /* required amount of heap  */
-_Min_Stack_Size = 0x400; /* required amount of stack */
+_Min_Heap_Size = 0x2000;      /* required amount of heap  */
+_Min_Stack_Size = 0x4000; /* required amount of stack */
 
 /* Specify the memory areas */
 MEMORY
diff --git a/lwip_test Debug.launch b/TBD_TaxiBoard Debug.launch
similarity index 95%
rename from lwip_test Debug.launch
rename to TBD_TaxiBoard Debug.launch
index b15ee9b..b1cf034 100644
--- a/lwip_test Debug.launch	
+++ b/TBD_TaxiBoard Debug.launch	
@@ -12,7 +12,7 @@
     <stringAttribute key="com.st.stm32cube.ide.mcu.debug.launch.ip_address_local" value="localhost"/>
     <booleanAttribute key="com.st.stm32cube.ide.mcu.debug.launch.limit_swo_clock.enabled" value="false"/>
     <stringAttribute key="com.st.stm32cube.ide.mcu.debug.launch.limit_swo_clock.value" value=""/>
-    <stringAttribute key="com.st.stm32cube.ide.mcu.debug.launch.loadList" value="{&quot;fItems&quot;:[{&quot;fIsFromMainTab&quot;:true,&quot;fPath&quot;:&quot;Debug/lwip_test.elf&quot;,&quot;fProjectName&quot;:&quot;lwip_test&quot;,&quot;fPerformBuild&quot;:true,&quot;fDownload&quot;:true,&quot;fLoadSymbols&quot;:true}]}"/>
+    <stringAttribute key="com.st.stm32cube.ide.mcu.debug.launch.loadList" value="{&quot;fItems&quot;:[{&quot;fIsFromMainTab&quot;:true,&quot;fPath&quot;:&quot;Debug/TBD_TaxiBoard.elf&quot;,&quot;fProjectName&quot;:&quot;TBD_TaxiBoard&quot;,&quot;fPerformBuild&quot;:true,&quot;fDownload&quot;:true,&quot;fLoadSymbols&quot;:true}]}"/>
     <stringAttribute key="com.st.stm32cube.ide.mcu.debug.launch.override_start_address_mode" value="default"/>
     <stringAttribute key="com.st.stm32cube.ide.mcu.debug.launch.remoteCommand" value="target remote"/>
     <booleanAttribute key="com.st.stm32cube.ide.mcu.debug.launch.startServer" value="true"/>
@@ -33,7 +33,7 @@
     <booleanAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.enable_shared_stlink" value="false"/>
     <stringAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.frequency" value="0"/>
     <booleanAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.halt_all_on_reset" value="false"/>
-    <stringAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.log_file" value="C:\_NoSleep\STM32\lwip_test\Debug\st-link_gdbserver_log.txt"/>
+    <stringAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.log_file" value="C:\_NoSleep\STM32\TBD_TaxiBoard\Debug\st-link_gdbserver_log.txt"/>
     <stringAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.low_power_debug" value="enable"/>
     <stringAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.max_halt_delay" value="2"/>
     <stringAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.reset_strategy" value="connect_under_reset"/>
@@ -77,13 +77,13 @@
     <stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_START_MODE" value="remote"/>
     <booleanAttribute key="org.eclipse.cdt.launch.DEBUGGER_STOP_AT_MAIN" value="true"/>
     <stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_STOP_AT_MAIN_SYMBOL" value="main"/>
-    <stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug/lwip_test.elf"/>
-    <stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="lwip_test"/>
+    <stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug/TBD_TaxiBoard.elf"/>
+    <stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="TBD_TaxiBoard"/>
     <booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="true"/>
-    <stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug.898215809"/>
+    <stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug.200712874"/>
     <booleanAttribute key="org.eclipse.debug.core.ATTR_FORCE_SYSTEM_CONSOLE_ENCODING" value="false"/>
     <listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
-        <listEntry value="/lwip_test"/>
+        <listEntry value="/TBD_TaxiBoard"/>
     </listAttribute>
     <listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
         <listEntry value="4"/>
diff --git a/TBD_TaxiBoard.ioc b/TBD_TaxiBoard.ioc
new file mode 100644
index 0000000..5152be2
--- /dev/null
+++ b/TBD_TaxiBoard.ioc
@@ -0,0 +1,534 @@
+#MicroXplorer Configuration settings - do not modify
+CAD.formats=[]
+CAD.pinconfig=Project naming
+CAD.provider=
+CORTEX_M7.AccessPermission_S-Cortex_Memory_Protection_Unit_Region1_Settings_S=MPU_REGION_FULL_ACCESS
+CORTEX_M7.AccessPermission_S-Cortex_Memory_Protection_Unit_Region2_Settings_S=MPU_REGION_FULL_ACCESS
+CORTEX_M7.AccessPermission_S-Cortex_Memory_Protection_Unit_Region3_Settings_S=MPU_REGION_FULL_ACCESS
+CORTEX_M7.BaseAddress_S-Cortex_Memory_Protection_Unit_Region1_Settings_S=0x30000000
+CORTEX_M7.BaseAddress_S-Cortex_Memory_Protection_Unit_Region2_Settings_S=0x30000000
+CORTEX_M7.BaseAddress_S-Cortex_Memory_Protection_Unit_Region3_Settings_S=0x24000000
+CORTEX_M7.CPU_DCache=Enabled
+CORTEX_M7.CPU_ICache=Enabled
+CORTEX_M7.DisableExec_S-Cortex_Memory_Protection_Unit_Region1_Settings_S=MPU_INSTRUCTION_ACCESS_DISABLE
+CORTEX_M7.DisableExec_S-Cortex_Memory_Protection_Unit_Region2_Settings_S=MPU_INSTRUCTION_ACCESS_DISABLE
+CORTEX_M7.Enable_S-Cortex_Memory_Protection_Unit_Region1_Settings_S=MPU_REGION_ENABLE
+CORTEX_M7.Enable_S-Cortex_Memory_Protection_Unit_Region2_Settings_S=MPU_REGION_ENABLE
+CORTEX_M7.Enable_S-Cortex_Memory_Protection_Unit_Region3_Settings_S=MPU_REGION_ENABLE
+CORTEX_M7.IPParameters=default_mode_Activation,CPU_ICache,CPU_DCache,Enable_S-Cortex_Memory_Protection_Unit_Region1_Settings_S,BaseAddress_S-Cortex_Memory_Protection_Unit_Region1_Settings_S,TypeExtField_S-Cortex_Memory_Protection_Unit_Region1_Settings_S,AccessPermission_S-Cortex_Memory_Protection_Unit_Region1_Settings_S,DisableExec_S-Cortex_Memory_Protection_Unit_Region1_Settings_S,Enable_S-Cortex_Memory_Protection_Unit_Region2_Settings_S,BaseAddress_S-Cortex_Memory_Protection_Unit_Region2_Settings_S,Size_S-Cortex_Memory_Protection_Unit_Region2_Settings_S,AccessPermission_S-Cortex_Memory_Protection_Unit_Region2_Settings_S,DisableExec_S-Cortex_Memory_Protection_Unit_Region2_Settings_S,IsShareable_S-Cortex_Memory_Protection_Unit_Region2_Settings_S,IsBufferable_S-Cortex_Memory_Protection_Unit_Region2_Settings_S,Size_S-Cortex_Memory_Protection_Unit_Region1_Settings_S,Enable_S-Cortex_Memory_Protection_Unit_Region3_Settings_S,BaseAddress_S-Cortex_Memory_Protection_Unit_Region3_Settings_S,Size_S-Cortex_Memory_Protection_Unit_Region3_Settings_S,TypeExtField_S-Cortex_Memory_Protection_Unit_Region3_Settings_S,AccessPermission_S-Cortex_Memory_Protection_Unit_Region3_Settings_S,IsShareable_S-Cortex_Memory_Protection_Unit_Region3_Settings_S
+CORTEX_M7.IsBufferable_S-Cortex_Memory_Protection_Unit_Region2_Settings_S=MPU_ACCESS_BUFFERABLE
+CORTEX_M7.IsShareable_S-Cortex_Memory_Protection_Unit_Region2_Settings_S=MPU_ACCESS_SHAREABLE
+CORTEX_M7.IsShareable_S-Cortex_Memory_Protection_Unit_Region3_Settings_S=MPU_ACCESS_SHAREABLE
+CORTEX_M7.Size_S-Cortex_Memory_Protection_Unit_Region1_Settings_S=MPU_REGION_SIZE_32KB
+CORTEX_M7.Size_S-Cortex_Memory_Protection_Unit_Region2_Settings_S=MPU_REGION_SIZE_512B
+CORTEX_M7.Size_S-Cortex_Memory_Protection_Unit_Region3_Settings_S=MPU_REGION_SIZE_128KB
+CORTEX_M7.TypeExtField_S-Cortex_Memory_Protection_Unit_Region1_Settings_S=MPU_TEX_LEVEL1
+CORTEX_M7.TypeExtField_S-Cortex_Memory_Protection_Unit_Region3_Settings_S=MPU_TEX_LEVEL1
+CORTEX_M7.default_mode_Activation=1
+Dma.Request0=UART8_RX
+Dma.RequestsNb=1
+Dma.UART8_RX.0.Direction=DMA_PERIPH_TO_MEMORY
+Dma.UART8_RX.0.EventEnable=DISABLE
+Dma.UART8_RX.0.FIFOMode=DMA_FIFOMODE_DISABLE
+Dma.UART8_RX.0.Instance=DMA1_Stream0
+Dma.UART8_RX.0.MemDataAlignment=DMA_MDATAALIGN_BYTE
+Dma.UART8_RX.0.MemInc=DMA_MINC_ENABLE
+Dma.UART8_RX.0.Mode=DMA_CIRCULAR
+Dma.UART8_RX.0.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
+Dma.UART8_RX.0.PeriphInc=DMA_PINC_DISABLE
+Dma.UART8_RX.0.Polarity=HAL_DMAMUX_REQ_GEN_RISING
+Dma.UART8_RX.0.Priority=DMA_PRIORITY_LOW
+Dma.UART8_RX.0.RequestNumber=1
+Dma.UART8_RX.0.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode,SignalID,Polarity,RequestNumber,SyncSignalID,SyncPolarity,SyncEnable,EventEnable,SyncRequestNumber
+Dma.UART8_RX.0.SignalID=NONE
+Dma.UART8_RX.0.SyncEnable=DISABLE
+Dma.UART8_RX.0.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT
+Dma.UART8_RX.0.SyncRequestNumber=1
+Dma.UART8_RX.0.SyncSignalID=NONE
+ETH.IPParameters=MediaInterface,TxDescAddress
+ETH.MediaInterface=HAL_ETH_RMII_MODE
+ETH.TxDescAddress=0x30000100
+FATFS.BSP.number=1
+FATFS.IPParameters=_USE_LFN,_MAX_SS,_FS_EXFAT
+FATFS._FS_EXFAT=1
+FATFS._MAX_SS=4096
+FATFS._USE_LFN=2
+FATFS0.BSP.STBoard=false
+FATFS0.BSP.api=Unknown
+FATFS0.BSP.component=
+FATFS0.BSP.condition=
+FATFS0.BSP.instance=PB15
+FATFS0.BSP.ip=GPIO
+FATFS0.BSP.mode=Input
+FATFS0.BSP.name=Detect_SDIO
+FATFS0.BSP.semaphore=
+FATFS0.BSP.solution=PB15
+FDCAN1.CalculateBaudRateNominal=500000
+FDCAN1.CalculateTimeBitNominal=2000
+FDCAN1.CalculateTimeQuantumNominal=50.0
+FDCAN1.DataPrescaler=4
+FDCAN1.DataSyncJumpWidth=4
+FDCAN1.DataTimeSeg1=11
+FDCAN1.DataTimeSeg2=3
+FDCAN1.FrameFormat=FDCAN_FRAME_FD_BRS
+FDCAN1.IPParameters=CalculateTimeQuantumNominal,CalculateTimeBitNominal,CalculateBaudRateNominal,FrameFormat,NominalSyncJumpWidth,DataPrescaler,DataSyncJumpWidth,DataTimeSeg1,DataTimeSeg2,RxFifo0ElmtsNbr,RxFifo0ElmtSize,RxFifo1ElmtSize,RxBufferSize,TxEventsNbr,TxFifoQueueElmtsNbr,TxElmtSize,NominalPrescaler,NominalTimeSeg1,NominalTimeSeg2
+FDCAN1.NominalPrescaler=6
+FDCAN1.NominalSyncJumpWidth=4
+FDCAN1.NominalTimeSeg1=29
+FDCAN1.NominalTimeSeg2=10
+FDCAN1.RxBufferSize=FDCAN_DATA_BYTES_64
+FDCAN1.RxFifo0ElmtSize=FDCAN_DATA_BYTES_64
+FDCAN1.RxFifo0ElmtsNbr=8
+FDCAN1.RxFifo1ElmtSize=FDCAN_DATA_BYTES_64
+FDCAN1.TxElmtSize=FDCAN_DATA_BYTES_64
+FDCAN1.TxEventsNbr=8
+FDCAN1.TxFifoQueueElmtsNbr=8
+FDCAN2.CalculateBaudRateNominal=500000
+FDCAN2.CalculateTimeBitNominal=2000
+FDCAN2.CalculateTimeQuantumNominal=50.0
+FDCAN2.DataPrescaler=4
+FDCAN2.DataSyncJumpWidth=4
+FDCAN2.DataTimeSeg1=11
+FDCAN2.DataTimeSeg2=3
+FDCAN2.FrameFormat=FDCAN_FRAME_FD_BRS
+FDCAN2.IPParameters=CalculateTimeQuantumNominal,CalculateTimeBitNominal,CalculateBaudRateNominal,FrameFormat,NominalSyncJumpWidth,DataPrescaler,DataSyncJumpWidth,DataTimeSeg1,DataTimeSeg2,RxFifo0ElmtsNbr,RxFifo0ElmtSize,RxFifo1ElmtSize,RxBufferSize,TxEventsNbr,TxFifoQueueElmtsNbr,TxElmtSize,NominalPrescaler,NominalTimeSeg1,NominalTimeSeg2,MessageRAMOffset
+FDCAN2.MessageRAMOffset=512
+FDCAN2.NominalPrescaler=6
+FDCAN2.NominalSyncJumpWidth=4
+FDCAN2.NominalTimeSeg1=29
+FDCAN2.NominalTimeSeg2=10
+FDCAN2.RxBufferSize=FDCAN_DATA_BYTES_64
+FDCAN2.RxFifo0ElmtSize=FDCAN_DATA_BYTES_64
+FDCAN2.RxFifo0ElmtsNbr=8
+FDCAN2.RxFifo1ElmtSize=FDCAN_DATA_BYTES_64
+FDCAN2.TxElmtSize=FDCAN_DATA_BYTES_64
+FDCAN2.TxEventsNbr=8
+FDCAN2.TxFifoQueueElmtsNbr=8
+FDCAN3.CalculateBaudRateNominal=500000
+FDCAN3.CalculateTimeBitNominal=2000
+FDCAN3.CalculateTimeQuantumNominal=50.0
+FDCAN3.DataPrescaler=4
+FDCAN3.DataSyncJumpWidth=4
+FDCAN3.DataTimeSeg1=11
+FDCAN3.DataTimeSeg2=3
+FDCAN3.FrameFormat=FDCAN_FRAME_FD_BRS
+FDCAN3.IPParameters=CalculateTimeQuantumNominal,CalculateTimeBitNominal,CalculateBaudRateNominal,FrameFormat,NominalSyncJumpWidth,DataPrescaler,DataSyncJumpWidth,DataTimeSeg1,DataTimeSeg2,RxFifo0ElmtsNbr,RxFifo0ElmtSize,RxFifo1ElmtSize,RxBufferSize,TxEventsNbr,TxFifoQueueElmtsNbr,TxElmtSize,NominalPrescaler,NominalTimeSeg1,NominalTimeSeg2,MessageRAMOffset
+FDCAN3.MessageRAMOffset=1024
+FDCAN3.NominalPrescaler=6
+FDCAN3.NominalSyncJumpWidth=4
+FDCAN3.NominalTimeSeg1=29
+FDCAN3.NominalTimeSeg2=10
+FDCAN3.RxBufferSize=FDCAN_DATA_BYTES_64
+FDCAN3.RxFifo0ElmtSize=FDCAN_DATA_BYTES_64
+FDCAN3.RxFifo0ElmtsNbr=8
+FDCAN3.RxFifo1ElmtSize=FDCAN_DATA_BYTES_64
+FDCAN3.TxElmtSize=FDCAN_DATA_BYTES_64
+FDCAN3.TxEventsNbr=8
+FDCAN3.TxFifoQueueElmtsNbr=8
+FREERTOS.FootprintOK=true
+FREERTOS.INCLUDE_vTaskDelayUntil=1
+FREERTOS.IPParameters=Tasks01,configMINIMAL_STACK_SIZE,configTOTAL_HEAP_SIZE,FootprintOK,configCHECK_FOR_STACK_OVERFLOW,configUSE_TIMERS,INCLUDE_vTaskDelayUntil
+FREERTOS.Tasks01=defaultTask,0,4096,StartDefaultTask,Default,NULL,Static,defaultTaskBuffer,defaultTaskControlBlock;debugTask,0,2048,StartDebugTask,Default,NULL,Static,debugTaskBuffer,debugTaskControlBlock
+FREERTOS.configCHECK_FOR_STACK_OVERFLOW=1
+FREERTOS.configMINIMAL_STACK_SIZE=256
+FREERTOS.configTOTAL_HEAP_SIZE=30720
+FREERTOS.configUSE_TIMERS=1
+File.Version=6
+GPIO.groupedBy=Group By Peripherals
+KeepUserPlacement=false
+LWIP.BSP.number=1
+LWIP.DEFAULT_THREAD_STACKSIZE=2048
+LWIP.IPParameters=LWIP_DHCP,IP_ADDRESS,NETMASK_ADDRESS,MEM_SIZE,LWIP_RAM_HEAP_POINTER,TCP_WND,TCP_MSS,TCP_SND_BUF,TCP_SND_QUEUELEN,DEFAULT_THREAD_STACKSIZE
+LWIP.IP_ADDRESS=192.168.000.120
+LWIP.LWIP_DHCP=0
+LWIP.LWIP_RAM_HEAP_POINTER=0x30000200
+LWIP.MEM_SIZE=32232
+LWIP.NETMASK_ADDRESS=255.255.255.000
+LWIP.TCP_MSS=1460
+LWIP.TCP_SND_BUF=5840
+LWIP.TCP_SND_QUEUELEN=16
+LWIP.TCP_WND=5840
+LWIP.Version=v2.1.2_Cube
+LWIP0.BSP.STBoard=false
+LWIP0.BSP.api=BSP_COMPONENT_DRIVER
+LWIP0.BSP.component=LAN8742
+LWIP0.BSP.condition=
+LWIP0.BSP.instance=LAN8742
+LWIP0.BSP.ip=
+LWIP0.BSP.mode=
+LWIP0.BSP.name=Driver_PHY
+LWIP0.BSP.semaphore=S_LAN8742
+LWIP0.BSP.solution=LAN8742
+Mcu.CPN=STM32H723VGH6
+Mcu.Family=STM32H7
+Mcu.IP0=CORTEX_M7
+Mcu.IP1=DEBUG
+Mcu.IP10=MDMA
+Mcu.IP11=NVIC
+Mcu.IP12=RCC
+Mcu.IP13=SDMMC1
+Mcu.IP14=SYS
+Mcu.IP15=TIM3
+Mcu.IP16=UART4
+Mcu.IP17=UART7
+Mcu.IP18=UART8
+Mcu.IP2=DMA
+Mcu.IP3=ETH
+Mcu.IP4=FATFS
+Mcu.IP5=FDCAN1
+Mcu.IP6=FDCAN2
+Mcu.IP7=FDCAN3
+Mcu.IP8=FREERTOS
+Mcu.IP9=LWIP
+Mcu.IPNb=19
+Mcu.Name=STM32H723VGHx
+Mcu.Package=TFBGA100
+Mcu.Pin0=PB9
+Mcu.Pin1=PB3(JTDO/TRACESWO)
+Mcu.Pin10=PH0-OSC_IN
+Mcu.Pin11=PE1
+Mcu.Pin12=PB5
+Mcu.Pin13=PC12
+Mcu.Pin14=PH1-OSC_OUT
+Mcu.Pin15=PE0
+Mcu.Pin16=PD0
+Mcu.Pin17=PD1
+Mcu.Pin18=PC9
+Mcu.Pin19=PC1
+Mcu.Pin2=PA15(JTDI)
+Mcu.Pin20=PC8
+Mcu.Pin21=PC4
+Mcu.Pin22=PE10
+Mcu.Pin23=PB15
+Mcu.Pin24=PA1
+Mcu.Pin25=PC5
+Mcu.Pin26=PE7
+Mcu.Pin27=PE11
+Mcu.Pin28=PA2
+Mcu.Pin29=PE8
+Mcu.Pin3=PA14(JTCK/SWCLK)
+Mcu.Pin30=PE12
+Mcu.Pin31=PB13
+Mcu.Pin32=PD13
+Mcu.Pin33=PA7
+Mcu.Pin34=PE9
+Mcu.Pin35=PE13
+Mcu.Pin36=PB11
+Mcu.Pin37=PB12
+Mcu.Pin38=PD12
+Mcu.Pin39=VP_FATFS_VS_SDIO
+Mcu.Pin4=PA13(JTMS/SWDIO)
+Mcu.Pin40=VP_FREERTOS_VS_CMSIS_V1
+Mcu.Pin41=VP_LWIP_VS_Enabled
+Mcu.Pin42=VP_SYS_VS_tim6
+Mcu.Pin43=VP_TIM3_VS_ClockSourceINT
+Mcu.Pin5=PB8
+Mcu.Pin6=PB6
+Mcu.Pin7=PD2
+Mcu.Pin8=PC11
+Mcu.Pin9=PC10
+Mcu.PinsNb=44
+Mcu.ThirdPartyNb=0
+Mcu.UserConstants=
+Mcu.UserName=STM32H723VGHx
+Mdma.MDMA_Channel0.Request0=SDMMC1_END_DATA
+Mdma.MDMA_Channel0.RequestsNb=1
+Mdma.MDMA_Channel0.SDMMC1_END_DATA.0.BlockCount=0
+Mdma.MDMA_Channel0.SDMMC1_END_DATA.0.BlockDataLength=0
+Mdma.MDMA_Channel0.SDMMC1_END_DATA.0.BufferTransferLength=1
+Mdma.MDMA_Channel0.SDMMC1_END_DATA.0.CircularMode=MDMA_LINEAR_LIST
+Mdma.MDMA_Channel0.SDMMC1_END_DATA.0.DataAlignment=MDMA_DATAALIGN_PACKENABLE
+Mdma.MDMA_Channel0.SDMMC1_END_DATA.0.DestBlockAddressOffset=0
+Mdma.MDMA_Channel0.SDMMC1_END_DATA.0.DestBurst=MDMA_DEST_BURST_SINGLE
+Mdma.MDMA_Channel0.SDMMC1_END_DATA.0.DestDataSize=MDMA_DEST_DATASIZE_BYTE
+Mdma.MDMA_Channel0.SDMMC1_END_DATA.0.DestinationInc=MDMA_DEST_INC_BYTE
+Mdma.MDMA_Channel0.SDMMC1_END_DATA.0.DstAddress=0
+Mdma.MDMA_Channel0.SDMMC1_END_DATA.0.Endianness=MDMA_LITTLE_ENDIANNESS_PRESERVE
+Mdma.MDMA_Channel0.SDMMC1_END_DATA.0.Instance=MDMA_Channel0
+Mdma.MDMA_Channel0.SDMMC1_END_DATA.0.MaskAddress=0
+Mdma.MDMA_Channel0.SDMMC1_END_DATA.0.MaskData=0
+Mdma.MDMA_Channel0.SDMMC1_END_DATA.0.Priority=MDMA_PRIORITY_LOW
+Mdma.MDMA_Channel0.SDMMC1_END_DATA.0.Rank=First
+Mdma.MDMA_Channel0.SDMMC1_END_DATA.0.RequestParameters=Instance,CircularMode,TransferTriggerMode,Priority,Endianness,SourceInc,DestinationInc,SourceDataSize,DestDataSize,DataAlignment,BufferTransferLength,SourceBurst,DestBurst,SourceBlockAddressOffset,DestBlockAddressOffset,MaskAddress,MaskData,SrcAddress,DstAddress,BlockDataLength,BlockCount,Rank
+Mdma.MDMA_Channel0.SDMMC1_END_DATA.0.SourceBlockAddressOffset=0
+Mdma.MDMA_Channel0.SDMMC1_END_DATA.0.SourceBurst=MDMA_SOURCE_BURST_SINGLE
+Mdma.MDMA_Channel0.SDMMC1_END_DATA.0.SourceDataSize=MDMA_SRC_DATASIZE_BYTE
+Mdma.MDMA_Channel0.SDMMC1_END_DATA.0.SourceInc=MDMA_SRC_INC_BYTE
+Mdma.MDMA_Channel0.SDMMC1_END_DATA.0.SrcAddress=0
+Mdma.MDMA_Channel0.SDMMC1_END_DATA.0.TransferTriggerMode=MDMA_BUFFER_TRANSFER
+Mdma.RequestSet0=MDMA_Channel0
+Mdma.RequestSetsNb=1
+MxCube.Version=6.10.0
+MxDb.Version=DB.6.0.100
+NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false
+NVIC.DMA1_Stream0_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true
+NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false
+NVIC.ETH_IRQn=true\:5\:0\:false\:false\:true\:true\:true\:true\:true
+NVIC.FDCAN1_IT0_IRQn=true\:5\:0\:false\:false\:true\:true\:true\:true\:true
+NVIC.FDCAN2_IT0_IRQn=true\:5\:0\:false\:false\:true\:true\:true\:true\:true
+NVIC.FDCAN3_IT0_IRQn=true\:5\:0\:false\:false\:true\:true\:true\:true\:true
+NVIC.ForceEnableDMAVector=true
+NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false
+NVIC.MDMA_IRQn=true\:5\:0\:false\:false\:true\:false\:false\:true\:true
+NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false
+NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false
+NVIC.PendSV_IRQn=true\:15\:0\:false\:false\:false\:true\:false\:false\:false
+NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
+NVIC.SDMMC1_IRQn=true\:5\:0\:false\:false\:true\:true\:true\:true\:true
+NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:false\:false\:false\:false\:false
+NVIC.SavedPendsvIrqHandlerGenerated=true
+NVIC.SavedSvcallIrqHandlerGenerated=true
+NVIC.SavedSystickIrqHandlerGenerated=true
+NVIC.SysTick_IRQn=true\:15\:0\:false\:false\:false\:true\:false\:true\:false
+NVIC.TIM6_DAC_IRQn=true\:15\:0\:false\:false\:true\:false\:false\:true\:true
+NVIC.TimeBase=TIM6_DAC_IRQn
+NVIC.TimeBaseIP=TIM6
+NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false
+PA1.GPIOParameters=GPIO_Speed
+PA1.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PA1.Mode=RMII
+PA1.Signal=ETH_REF_CLK
+PA13(JTMS/SWDIO).Mode=Trace_Asynchronous_SW
+PA13(JTMS/SWDIO).Signal=DEBUG_JTMS-SWDIO
+PA14(JTCK/SWCLK).Mode=Trace_Asynchronous_SW
+PA14(JTCK/SWCLK).Signal=DEBUG_JTCK-SWCLK
+PA15(JTDI).GPIOParameters=GPIO_Label
+PA15(JTDI).GPIO_Label=mLED
+PA15(JTDI).Locked=true
+PA15(JTDI).Signal=GPIO_Output
+PA2.GPIOParameters=GPIO_Speed
+PA2.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PA2.Mode=RMII
+PA2.Signal=ETH_MDIO
+PA7.GPIOParameters=GPIO_Speed
+PA7.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PA7.Mode=RMII
+PA7.Signal=ETH_CRS_DV
+PB11.GPIOParameters=GPIO_Speed
+PB11.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PB11.Mode=RMII
+PB11.Signal=ETH_TX_EN
+PB12.GPIOParameters=GPIO_Speed
+PB12.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PB12.Mode=RMII
+PB12.Signal=ETH_TXD0
+PB13.GPIOParameters=GPIO_Speed
+PB13.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PB13.Mode=RMII
+PB13.Signal=ETH_TXD1
+PB15.GPIOParameters=GPIO_Label
+PB15.GPIO_Label=sdDetect
+PB15.Locked=true
+PB15.Signal=GPIO_Input
+PB3(JTDO/TRACESWO).Mode=Trace_Asynchronous_SW
+PB3(JTDO/TRACESWO).Signal=DEBUG_JTDO-SWO
+PB5.Mode=FDCAN_Activate
+PB5.Signal=FDCAN2_RX
+PB6.Mode=FDCAN_Activate
+PB6.Signal=FDCAN2_TX
+PB8.Mode=FDCAN_Activate
+PB8.Signal=FDCAN1_RX
+PB9.Mode=FDCAN_Activate
+PB9.Signal=FDCAN1_TX
+PC1.GPIOParameters=GPIO_Speed
+PC1.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PC1.Mode=RMII
+PC1.Signal=ETH_MDC
+PC10.Mode=SD_4_bits_Wide_bus
+PC10.Signal=SDMMC1_D2
+PC11.Mode=SD_4_bits_Wide_bus
+PC11.Signal=SDMMC1_D3
+PC12.Mode=SD_4_bits_Wide_bus
+PC12.Signal=SDMMC1_CK
+PC4.GPIOParameters=GPIO_Speed
+PC4.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PC4.Mode=RMII
+PC4.Signal=ETH_RXD0
+PC5.GPIOParameters=GPIO_Speed
+PC5.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PC5.Mode=RMII
+PC5.Signal=ETH_RXD1
+PC8.Mode=SD_4_bits_Wide_bus
+PC8.Signal=SDMMC1_D0
+PC9.Mode=SD_4_bits_Wide_bus
+PC9.Signal=SDMMC1_D1
+PD0.Locked=true
+PD0.Mode=Asynchronous
+PD0.Signal=UART4_RX
+PD1.Locked=true
+PD1.Mode=Asynchronous
+PD1.Signal=UART4_TX
+PD12.Mode=FDCAN_Activate
+PD12.Signal=FDCAN3_RX
+PD13.Mode=FDCAN_Activate
+PD13.Signal=FDCAN3_TX
+PD2.Mode=SD_4_bits_Wide_bus
+PD2.Signal=SDMMC1_CMD
+PE0.Mode=Asynchronous
+PE0.Signal=UART8_RX
+PE1.Mode=Asynchronous
+PE1.Signal=UART8_TX
+PE10.GPIOParameters=GPIO_Label
+PE10.GPIO_Label=SD_LED
+PE10.Locked=true
+PE10.Signal=GPIO_Output
+PE11.GPIOParameters=GPIO_Label
+PE11.GPIO_Label=VIN_IG
+PE11.Locked=true
+PE11.Signal=GPIO_Input
+PE12.GPIOParameters=GPIO_Label
+PE12.GPIO_Label=VIN_ON
+PE12.Locked=true
+PE12.Signal=GPIO_Output
+PE13.GPIOParameters=GPIO_Label
+PE13.GPIO_Label=VIN_1_4
+PE13.Locked=true
+PE13.Signal=GPIO_Input
+PE7.Locked=true
+PE7.Mode=Asynchronous
+PE7.Signal=UART7_RX
+PE8.Locked=true
+PE8.Mode=Asynchronous
+PE8.Signal=UART7_TX
+PE9.GPIOParameters=GPIO_Label
+PE9.GPIO_Label=PICO_EN
+PE9.Locked=true
+PE9.Signal=GPIO_Output
+PH0-OSC_IN.Mode=HSE-External-Oscillator
+PH0-OSC_IN.Signal=RCC_OSC_IN
+PH1-OSC_OUT.Mode=HSE-External-Oscillator
+PH1-OSC_OUT.Signal=RCC_OSC_OUT
+PinOutPanel.CurrentBGAView=Top
+PinOutPanel.RotationAngle=0
+ProjectManager.AskForMigrate=true
+ProjectManager.BackupPrevious=false
+ProjectManager.CompilerOptimize=6
+ProjectManager.ComputerToolchain=false
+ProjectManager.CoupleFile=false
+ProjectManager.CustomerFirmwarePackage=
+ProjectManager.DefaultFWLocation=true
+ProjectManager.DeletePrevious=true
+ProjectManager.DeviceId=STM32H723VGHx
+ProjectManager.FirmwarePackage=STM32Cube FW_H7 V1.11.1
+ProjectManager.FreePins=false
+ProjectManager.HalAssertFull=false
+ProjectManager.HeapSize=0x2000
+ProjectManager.KeepUserCode=true
+ProjectManager.LastFirmware=true
+ProjectManager.LibraryCopy=1
+ProjectManager.MainLocation=Core/Src
+ProjectManager.NoMain=false
+ProjectManager.PreviousToolchain=STM32CubeIDE
+ProjectManager.ProjectBuild=false
+ProjectManager.ProjectFileName=TBD_TaxiBoard.ioc
+ProjectManager.ProjectName=TBD_TaxiBoard
+ProjectManager.ProjectStructure=
+ProjectManager.RegisterCallBack=
+ProjectManager.StackSize=0x4000
+ProjectManager.TargetToolchain=STM32CubeIDE
+ProjectManager.ToolChainLocation=
+ProjectManager.UAScriptAfterPath=
+ProjectManager.UAScriptBeforePath=
+ProjectManager.UnderRoot=true
+ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-false-HAL-true,3-MX_DMA_Init-DMA-false-HAL-true,4-MX_MDMA_Init-MDMA-false-HAL-true,5-MX_FDCAN3_Init-FDCAN3-false-HAL-true,6-MX_SDMMC1_SD_Init-SDMMC1-false-HAL-true,7-MX_TIM3_Init-TIM3-false-HAL-true,8-MX_UART4_Init-UART4-false-HAL-true,9-MX_UART7_Init-UART7-false-HAL-true,10-MX_FDCAN1_Init-FDCAN1-false-HAL-true,11-MX_FDCAN2_Init-FDCAN2-false-HAL-true,12-MX_FATFS_Init-FATFS-false-HAL-false,13-MX_LWIP_Init-LWIP-false-HAL-false,14-MX_UART8_Init-UART8-false-HAL-true,0-MX_CORTEX_M7_Init-CORTEX_M7-false-HAL-true
+RCC.ADCFreq_Value=100000000
+RCC.AHB12Freq_Value=240000000
+RCC.AHB4Freq_Value=240000000
+RCC.APB1Freq_Value=120000000
+RCC.APB2Freq_Value=120000000
+RCC.APB3Freq_Value=120000000
+RCC.APB4Freq_Value=120000000
+RCC.AXIClockFreq_Value=240000000
+RCC.CECFreq_Value=32000
+RCC.CKPERFreq_Value=64000000
+RCC.CortexFreq_Value=480000000
+RCC.CpuClockFreq_Value=480000000
+RCC.D1CPREFreq_Value=480000000
+RCC.D1PPRE=RCC_APB3_DIV2
+RCC.D2PPRE1=RCC_APB1_DIV2
+RCC.D2PPRE2=RCC_APB2_DIV2
+RCC.D3PPRE=RCC_APB4_DIV2
+RCC.DFSDMACLkFreq_Value=120000000
+RCC.DFSDMFreq_Value=120000000
+RCC.DIVM1=5
+RCC.DIVM2=16
+RCC.DIVM3=16
+RCC.DIVN1=96
+RCC.DIVN2=128
+RCC.DIVN3=128
+RCC.DIVP1=1
+RCC.DIVP1Freq_Value=480000000
+RCC.DIVP2Freq_Value=100000000
+RCC.DIVP3Freq_Value=100000000
+RCC.DIVQ1=4
+RCC.DIVQ1Freq_Value=120000000
+RCC.DIVQ2Freq_Value=100000000
+RCC.DIVQ3Freq_Value=100000000
+RCC.DIVR1Freq_Value=240000000
+RCC.DIVR2Freq_Value=100000000
+RCC.DIVR3Freq_Value=100000000
+RCC.FDCANFreq_Value=120000000
+RCC.FMCFreq_Value=240000000
+RCC.FamilyName=M
+RCC.HCLK3ClockFreq_Value=240000000
+RCC.HCLKFreq_Value=240000000
+RCC.HPRE=RCC_HCLK_DIV2
+RCC.I2C123Freq_Value=120000000
+RCC.I2C4Freq_Value=120000000
+RCC.IPParameters=ADCFreq_Value,AHB12Freq_Value,AHB4Freq_Value,APB1Freq_Value,APB2Freq_Value,APB3Freq_Value,APB4Freq_Value,AXIClockFreq_Value,CECFreq_Value,CKPERFreq_Value,CortexFreq_Value,CpuClockFreq_Value,D1CPREFreq_Value,D1PPRE,D2PPRE1,D2PPRE2,D3PPRE,DFSDMACLkFreq_Value,DFSDMFreq_Value,DIVM1,DIVM2,DIVM3,DIVN1,DIVN2,DIVN3,DIVP1,DIVP1Freq_Value,DIVP2Freq_Value,DIVP3Freq_Value,DIVQ1,DIVQ1Freq_Value,DIVQ2Freq_Value,DIVQ3Freq_Value,DIVR1Freq_Value,DIVR2Freq_Value,DIVR3Freq_Value,FDCANFreq_Value,FMCFreq_Value,FamilyName,HCLK3ClockFreq_Value,HCLKFreq_Value,HPRE,I2C123Freq_Value,I2C4Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPTIM345Freq_Value,LPUART1Freq_Value,LTDCFreq_Value,MCO1PinFreq_Value,MCO2PinFreq_Value,PLLFRACN,PLLSourceVirtual,QSPIFreq_Value,RNGFreq_Value,RTCFreq_Value,SAI1Freq_Value,SAI4AFreq_Value,SAI4BFreq_Value,SDMMCFreq_Value,SPDIFRXFreq_Value,SPI123Freq_Value,SPI45Freq_Value,SPI6Freq_Value,SWPMI1Freq_Value,SYSCLKFreq_VALUE,SYSCLKSource,Tim1OutputFreq_Value,Tim2OutputFreq_Value,TraceFreq_Value,USART16Freq_Value,USART234578Freq_Value,USBFreq_Value,VCO1OutputFreq_Value,VCO2OutputFreq_Value,VCO3OutputFreq_Value,VCOInput1Freq_Value,VCOInput2Freq_Value,VCOInput3Freq_Value
+RCC.LPTIM1Freq_Value=120000000
+RCC.LPTIM2Freq_Value=120000000
+RCC.LPTIM345Freq_Value=120000000
+RCC.LPUART1Freq_Value=120000000
+RCC.LTDCFreq_Value=100000000
+RCC.MCO1PinFreq_Value=64000000
+RCC.MCO2PinFreq_Value=480000000
+RCC.PLLFRACN=0
+RCC.PLLSourceVirtual=RCC_PLLSOURCE_HSE
+RCC.QSPIFreq_Value=240000000
+RCC.RNGFreq_Value=48000000
+RCC.RTCFreq_Value=32000
+RCC.SAI1Freq_Value=120000000
+RCC.SAI4AFreq_Value=120000000
+RCC.SAI4BFreq_Value=120000000
+RCC.SDMMCFreq_Value=120000000
+RCC.SPDIFRXFreq_Value=120000000
+RCC.SPI123Freq_Value=120000000
+RCC.SPI45Freq_Value=120000000
+RCC.SPI6Freq_Value=120000000
+RCC.SWPMI1Freq_Value=120000000
+RCC.SYSCLKFreq_VALUE=480000000
+RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
+RCC.Tim1OutputFreq_Value=240000000
+RCC.Tim2OutputFreq_Value=240000000
+RCC.TraceFreq_Value=240000000
+RCC.USART16Freq_Value=120000000
+RCC.USART234578Freq_Value=120000000
+RCC.USBFreq_Value=120000000
+RCC.VCO1OutputFreq_Value=480000000
+RCC.VCO2OutputFreq_Value=200000000
+RCC.VCO3OutputFreq_Value=200000000
+RCC.VCOInput1Freq_Value=5000000
+RCC.VCOInput2Freq_Value=1562500
+RCC.VCOInput3Freq_Value=1562500
+SDMMC1.ClockDiv=1
+SDMMC1.HardwareFlowControl=SDMMC_HARDWARE_FLOW_CONTROL_ENABLE
+SDMMC1.IPParameters=HardwareFlowControl,ClockDiv
+TIM3.IPParameters=Prescaler
+TIM3.Prescaler=119
+UART4.BaudRate=9600
+UART4.IPParameters=BaudRate
+VP_FATFS_VS_SDIO.Mode=SDIO
+VP_FATFS_VS_SDIO.Signal=FATFS_VS_SDIO
+VP_FREERTOS_VS_CMSIS_V1.Mode=CMSIS_V1
+VP_FREERTOS_VS_CMSIS_V1.Signal=FREERTOS_VS_CMSIS_V1
+VP_LWIP_VS_Enabled.Mode=Enabled
+VP_LWIP_VS_Enabled.Signal=LWIP_VS_Enabled
+VP_SYS_VS_tim6.Mode=TIM6
+VP_SYS_VS_tim6.Signal=SYS_VS_tim6
+VP_TIM3_VS_ClockSourceINT.Mode=Internal
+VP_TIM3_VS_ClockSourceINT.Signal=TIM3_VS_ClockSourceINT
+board=custom
+rtos.0.ip=FREERTOS
+rtos.0.tasks.0=allocationType,Dynamic;bufferName,NULL;codeGen,Default;controlBlockName,NULL;entry,StartDefaultTask;name,defaultTask;parameter,NULL;priority,osPriorityNormal;stackSize,128
+isbadioc=false
diff --git a/lwip_test.ioc b/lwip_test.ioc
deleted file mode 100644
index a09c8a3..0000000
--- a/lwip_test.ioc
+++ /dev/null
@@ -1,250 +0,0 @@
-#MicroXplorer Configuration settings - do not modify
-CAD.formats=
-CAD.pinconfig=
-CAD.provider=
-CORTEX_M7.AccessPermission_S-Cortex_Memory_Protection_Unit_Region1_Settings_S=MPU_REGION_FULL_ACCESS
-CORTEX_M7.AccessPermission_S-Cortex_Memory_Protection_Unit_Region2_Settings_S=MPU_REGION_FULL_ACCESS
-CORTEX_M7.BaseAddress_S-Cortex_Memory_Protection_Unit_Region1_Settings_S=0x30000000
-CORTEX_M7.BaseAddress_S-Cortex_Memory_Protection_Unit_Region2_Settings_S=0x30000000
-CORTEX_M7.CPU_DCache=Enabled
-CORTEX_M7.CPU_ICache=Enabled
-CORTEX_M7.DisableExec_S-Cortex_Memory_Protection_Unit_Region1_Settings_S=MPU_INSTRUCTION_ACCESS_DISABLE
-CORTEX_M7.DisableExec_S-Cortex_Memory_Protection_Unit_Region2_Settings_S=MPU_INSTRUCTION_ACCESS_DISABLE
-CORTEX_M7.Enable_S-Cortex_Memory_Protection_Unit_Region1_Settings_S=MPU_REGION_ENABLE
-CORTEX_M7.Enable_S-Cortex_Memory_Protection_Unit_Region2_Settings_S=MPU_REGION_ENABLE
-CORTEX_M7.IPParameters=CPU_ICache,CPU_DCache,Enable_S-Cortex_Memory_Protection_Unit_Region1_Settings_S,BaseAddress_S-Cortex_Memory_Protection_Unit_Region1_Settings_S,Size_S-Cortex_Memory_Protection_Unit_Region1_Settings_S,TypeExtField_S-Cortex_Memory_Protection_Unit_Region1_Settings_S,AccessPermission_S-Cortex_Memory_Protection_Unit_Region1_Settings_S,DisableExec_S-Cortex_Memory_Protection_Unit_Region1_Settings_S,Enable_S-Cortex_Memory_Protection_Unit_Region2_Settings_S,BaseAddress_S-Cortex_Memory_Protection_Unit_Region2_Settings_S,Size_S-Cortex_Memory_Protection_Unit_Region2_Settings_S,AccessPermission_S-Cortex_Memory_Protection_Unit_Region2_Settings_S,DisableExec_S-Cortex_Memory_Protection_Unit_Region2_Settings_S,IsShareable_S-Cortex_Memory_Protection_Unit_Region2_Settings_S,IsBufferable_S-Cortex_Memory_Protection_Unit_Region2_Settings_S
-CORTEX_M7.IsBufferable_S-Cortex_Memory_Protection_Unit_Region2_Settings_S=MPU_ACCESS_BUFFERABLE
-CORTEX_M7.IsShareable_S-Cortex_Memory_Protection_Unit_Region2_Settings_S=MPU_ACCESS_SHAREABLE
-CORTEX_M7.Size_S-Cortex_Memory_Protection_Unit_Region1_Settings_S=MPU_REGION_SIZE_32KB
-CORTEX_M7.Size_S-Cortex_Memory_Protection_Unit_Region2_Settings_S=MPU_REGION_SIZE_512B
-CORTEX_M7.TypeExtField_S-Cortex_Memory_Protection_Unit_Region1_Settings_S=MPU_TEX_LEVEL1
-ETH.IPParameters=MediaInterface,TxDescAddress
-ETH.MediaInterface=HAL_ETH_RMII_MODE
-ETH.TxDescAddress=0x30000100
-File.Version=6
-GPIO.groupedBy=Group By Peripherals
-KeepUserPlacement=false
-LWIP.BSP.number=1
-LWIP.IPParameters=MEM_SIZE,LWIP_RAM_HEAP_POINTER,LWIP_DHCP,IP_ADDRESS,NETMASK_ADDRESS
-LWIP.IP_ADDRESS=192.168.000.120
-LWIP.LWIP_DHCP=0
-LWIP.LWIP_RAM_HEAP_POINTER=0x30000200
-LWIP.MEM_SIZE=32232
-LWIP.NETMASK_ADDRESS=255.255.255.000
-LWIP.Version=v2.1.2_Cube
-LWIP0.BSP.STBoard=false
-LWIP0.BSP.api=BSP_COMPONENT_DRIVER
-LWIP0.BSP.component=LAN8742
-LWIP0.BSP.condition=
-LWIP0.BSP.instance=LAN8742
-LWIP0.BSP.ip=
-LWIP0.BSP.mode=
-LWIP0.BSP.name=Driver_PHY
-LWIP0.BSP.semaphore=S_LAN8742
-LWIP0.BSP.solution=LAN8742
-Mcu.CPN=STM32H723VGH6
-Mcu.Family=STM32H7
-Mcu.IP0=CORTEX_M7
-Mcu.IP1=DEBUG
-Mcu.IP2=ETH
-Mcu.IP3=LWIP
-Mcu.IP4=NVIC
-Mcu.IP5=RCC
-Mcu.IP6=SYS
-Mcu.IPNb=7
-Mcu.Name=STM32H723VGHx
-Mcu.Package=TFBGA100
-Mcu.Pin0=PB3(JTDO/TRACESWO)
-Mcu.Pin1=PA14(JTCK/SWCLK)
-Mcu.Pin10=PB13
-Mcu.Pin11=PA7
-Mcu.Pin12=PB11
-Mcu.Pin13=PB12
-Mcu.Pin14=VP_LWIP_VS_Enabled
-Mcu.Pin15=VP_SYS_VS_Systick
-Mcu.Pin2=PA13(JTMS/SWDIO)
-Mcu.Pin3=PH0-OSC_IN
-Mcu.Pin4=PH1-OSC_OUT
-Mcu.Pin5=PC1
-Mcu.Pin6=PC4
-Mcu.Pin7=PA1
-Mcu.Pin8=PC5
-Mcu.Pin9=PA2
-Mcu.PinsNb=16
-Mcu.ThirdPartyNb=0
-Mcu.UserConstants=
-Mcu.UserName=STM32H723VGHx
-MxCube.Version=6.10.0
-MxDb.Version=DB.6.0.100
-NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
-NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
-NVIC.ETH_IRQn=true\:0\:0\:false\:false\:true\:true\:true\:true
-NVIC.ForceEnableDMAVector=true
-NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
-NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
-NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
-NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
-NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
-NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
-NVIC.SysTick_IRQn=true\:15\:0\:false\:false\:true\:false\:true\:false
-NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
-PA1.GPIOParameters=GPIO_Speed
-PA1.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
-PA1.Mode=RMII
-PA1.Signal=ETH_REF_CLK
-PA13(JTMS/SWDIO).Mode=Trace_Asynchronous_SW
-PA13(JTMS/SWDIO).Signal=DEBUG_JTMS-SWDIO
-PA14(JTCK/SWCLK).Mode=Trace_Asynchronous_SW
-PA14(JTCK/SWCLK).Signal=DEBUG_JTCK-SWCLK
-PA2.GPIOParameters=GPIO_Speed
-PA2.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
-PA2.Mode=RMII
-PA2.Signal=ETH_MDIO
-PA7.GPIOParameters=GPIO_Speed
-PA7.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
-PA7.Mode=RMII
-PA7.Signal=ETH_CRS_DV
-PB11.GPIOParameters=GPIO_Speed
-PB11.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
-PB11.Mode=RMII
-PB11.Signal=ETH_TX_EN
-PB12.GPIOParameters=GPIO_Speed
-PB12.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
-PB12.Mode=RMII
-PB12.Signal=ETH_TXD0
-PB13.GPIOParameters=GPIO_Speed
-PB13.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
-PB13.Mode=RMII
-PB13.Signal=ETH_TXD1
-PB3(JTDO/TRACESWO).Mode=Trace_Asynchronous_SW
-PB3(JTDO/TRACESWO).Signal=DEBUG_JTDO-SWO
-PC1.GPIOParameters=GPIO_Speed
-PC1.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
-PC1.Mode=RMII
-PC1.Signal=ETH_MDC
-PC4.GPIOParameters=GPIO_Speed
-PC4.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
-PC4.Mode=RMII
-PC4.Signal=ETH_RXD0
-PC5.GPIOParameters=GPIO_Speed
-PC5.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
-PC5.Mode=RMII
-PC5.Signal=ETH_RXD1
-PH0-OSC_IN.Mode=HSE-External-Oscillator
-PH0-OSC_IN.Signal=RCC_OSC_IN
-PH1-OSC_OUT.Mode=HSE-External-Oscillator
-PH1-OSC_OUT.Signal=RCC_OSC_OUT
-PinOutPanel.CurrentBGAView=Top
-PinOutPanel.RotationAngle=0
-ProjectManager.AskForMigrate=true
-ProjectManager.BackupPrevious=false
-ProjectManager.CompilerOptimize=6
-ProjectManager.ComputerToolchain=false
-ProjectManager.CoupleFile=false
-ProjectManager.CustomerFirmwarePackage=
-ProjectManager.DefaultFWLocation=true
-ProjectManager.DeletePrevious=true
-ProjectManager.DeviceId=STM32H723VGHx
-ProjectManager.FirmwarePackage=STM32Cube FW_H7 V1.11.1
-ProjectManager.FreePins=false
-ProjectManager.HalAssertFull=false
-ProjectManager.HeapSize=0x200
-ProjectManager.KeepUserCode=true
-ProjectManager.LastFirmware=true
-ProjectManager.LibraryCopy=1
-ProjectManager.MainLocation=Core/Src
-ProjectManager.NoMain=false
-ProjectManager.PreviousToolchain=
-ProjectManager.ProjectBuild=false
-ProjectManager.ProjectFileName=lwip_test.ioc
-ProjectManager.ProjectName=lwip_test
-ProjectManager.ProjectStructure=
-ProjectManager.RegisterCallBack=
-ProjectManager.StackSize=0x400
-ProjectManager.TargetToolchain=STM32CubeIDE
-ProjectManager.ToolChainLocation=
-ProjectManager.UAScriptAfterPath=
-ProjectManager.UAScriptBeforePath=
-ProjectManager.UnderRoot=true
-ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,0-MX_CORTEX_M7_Init-CORTEX_M7-false-HAL-true
-RCC.ADCFreq_Value=50390625
-RCC.AHB12Freq_Value=240000000
-RCC.AHB4Freq_Value=240000000
-RCC.APB1Freq_Value=120000000
-RCC.APB2Freq_Value=120000000
-RCC.APB3Freq_Value=120000000
-RCC.APB4Freq_Value=120000000
-RCC.AXIClockFreq_Value=240000000
-RCC.CECFreq_Value=32000
-RCC.CKPERFreq_Value=64000000
-RCC.CortexFreq_Value=480000000
-RCC.CpuClockFreq_Value=480000000
-RCC.D1CPREFreq_Value=480000000
-RCC.D1PPRE=RCC_APB3_DIV2
-RCC.D2PPRE1=RCC_APB1_DIV2
-RCC.D2PPRE2=RCC_APB2_DIV2
-RCC.D3PPRE=RCC_APB4_DIV2
-RCC.DFSDMACLkFreq_Value=240000000
-RCC.DFSDMFreq_Value=120000000
-RCC.DIVM1=5
-RCC.DIVN1=96
-RCC.DIVP1=1
-RCC.DIVP1Freq_Value=480000000
-RCC.DIVP2Freq_Value=50390625
-RCC.DIVP3Freq_Value=50390625
-RCC.DIVQ1Freq_Value=240000000
-RCC.DIVQ2Freq_Value=50390625
-RCC.DIVQ3Freq_Value=50390625
-RCC.DIVR1Freq_Value=240000000
-RCC.DIVR2Freq_Value=50390625
-RCC.DIVR3Freq_Value=50390625
-RCC.FDCANFreq_Value=240000000
-RCC.FMCFreq_Value=240000000
-RCC.FamilyName=M
-RCC.HCLK3ClockFreq_Value=240000000
-RCC.HCLKFreq_Value=240000000
-RCC.HPRE=RCC_HCLK_DIV2
-RCC.I2C123Freq_Value=120000000
-RCC.I2C4Freq_Value=120000000
-RCC.IPParameters=ADCFreq_Value,AHB12Freq_Value,AHB4Freq_Value,APB1Freq_Value,APB2Freq_Value,APB3Freq_Value,APB4Freq_Value,AXIClockFreq_Value,CECFreq_Value,CKPERFreq_Value,CortexFreq_Value,CpuClockFreq_Value,D1CPREFreq_Value,D1PPRE,D2PPRE1,D2PPRE2,D3PPRE,DFSDMACLkFreq_Value,DFSDMFreq_Value,DIVM1,DIVN1,DIVP1,DIVP1Freq_Value,DIVP2Freq_Value,DIVP3Freq_Value,DIVQ1Freq_Value,DIVQ2Freq_Value,DIVQ3Freq_Value,DIVR1Freq_Value,DIVR2Freq_Value,DIVR3Freq_Value,FDCANFreq_Value,FMCFreq_Value,FamilyName,HCLK3ClockFreq_Value,HCLKFreq_Value,HPRE,I2C123Freq_Value,I2C4Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPTIM345Freq_Value,LPUART1Freq_Value,LTDCFreq_Value,MCO1PinFreq_Value,MCO2PinFreq_Value,PLLFRACN,PLLSourceVirtual,QSPIFreq_Value,RNGFreq_Value,RTCFreq_Value,SAI1Freq_Value,SAI4AFreq_Value,SAI4BFreq_Value,SDMMCFreq_Value,SPDIFRXFreq_Value,SPI123Freq_Value,SPI45Freq_Value,SPI6Freq_Value,SWPMI1Freq_Value,SYSCLKFreq_VALUE,SYSCLKSource,Tim1OutputFreq_Value,Tim2OutputFreq_Value,TraceFreq_Value,USART16Freq_Value,USART234578Freq_Value,USBFreq_Value,VCO1OutputFreq_Value,VCO2OutputFreq_Value,VCO3OutputFreq_Value,VCOInput1Freq_Value,VCOInput2Freq_Value,VCOInput3Freq_Value
-RCC.LPTIM1Freq_Value=120000000
-RCC.LPTIM2Freq_Value=120000000
-RCC.LPTIM345Freq_Value=120000000
-RCC.LPUART1Freq_Value=120000000
-RCC.LTDCFreq_Value=50390625
-RCC.MCO1PinFreq_Value=64000000
-RCC.MCO2PinFreq_Value=480000000
-RCC.PLLFRACN=0
-RCC.PLLSourceVirtual=RCC_PLLSOURCE_HSE
-RCC.QSPIFreq_Value=240000000
-RCC.RNGFreq_Value=48000000
-RCC.RTCFreq_Value=32000
-RCC.SAI1Freq_Value=240000000
-RCC.SAI4AFreq_Value=240000000
-RCC.SAI4BFreq_Value=240000000
-RCC.SDMMCFreq_Value=240000000
-RCC.SPDIFRXFreq_Value=240000000
-RCC.SPI123Freq_Value=240000000
-RCC.SPI45Freq_Value=120000000
-RCC.SPI6Freq_Value=120000000
-RCC.SWPMI1Freq_Value=120000000
-RCC.SYSCLKFreq_VALUE=480000000
-RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
-RCC.Tim1OutputFreq_Value=240000000
-RCC.Tim2OutputFreq_Value=240000000
-RCC.TraceFreq_Value=240000000
-RCC.USART16Freq_Value=120000000
-RCC.USART234578Freq_Value=120000000
-RCC.USBFreq_Value=240000000
-RCC.VCO1OutputFreq_Value=480000000
-RCC.VCO2OutputFreq_Value=100781250
-RCC.VCO3OutputFreq_Value=100781250
-RCC.VCOInput1Freq_Value=5000000
-RCC.VCOInput2Freq_Value=781250
-RCC.VCOInput3Freq_Value=781250
-VP_LWIP_VS_Enabled.Mode=Enabled
-VP_LWIP_VS_Enabled.Signal=LWIP_VS_Enabled
-VP_SYS_VS_Systick.Mode=SysTick
-VP_SYS_VS_Systick.Signal=SYS_VS_Systick
-board=custom
-isbadioc=false